Repository: ophub/kernel
Branch: main
Commit: 25ed29db5ca6
Files: 48
Total size: 8.4 MB

Directory structure:
gitextract_zrrni0xv/

├── .github/
│   ├── ISSUE_TEMPLATE/
│   │   └── bug-report.md
│   └── workflows/
│       ├── compile-allwinner-h6-kernel.yml
│       ├── compile-mainline-beta-kernel.yml
│       ├── compile-mainline-stable-kernel.yml
│       ├── compile-rockchip-rk3588-kernel.yml
│       ├── compile-rockchip-rk35xx-kernel.yml
│       └── delete-older-releases-workflows.yml
├── .gitignore
├── LICENSE
├── README.cn.md
├── README.md
├── kernel-config/
│   ├── README.md
│   └── release/
│       ├── h6/
│       │   ├── config-6.4
│       │   ├── config-6.5
│       │   └── config-6.6
│       ├── rk3588/
│       │   ├── config-5.10
│       │   └── config-6.1
│       ├── rk35xx/
│       │   ├── config-5.10
│       │   └── config-6.1
│       └── stable/
│           ├── config-5.10
│           ├── config-5.15
│           ├── config-5.4
│           ├── config-6.1
│           ├── config-6.12
│           ├── config-6.18
│           └── config-6.6
└── kernel-patch/
    ├── README.md
    └── beta/
        ├── common-kernel-patches/
        │   └── 301-dts-add-rockchip-rk3399-mpc1903-dtb.patch
        ├── deprecated-patches/
        │   ├── 5.10.y-101-arm64-add-text_offset.patch
        │   ├── 5.10.y-201-wifi-add-ssv6051-driver.patch
        │   ├── 5.15.y-201-wifi-add-ssv6051-driver.patch
        │   ├── 6.1.y-101-arm64-add-text_offset.patch
        │   ├── 6.12.y-301-dts-add-rockchip-rk3568-alark35-3500-dtb.patch
        │   ├── 6.18.y-101-arm64-add-text_offset.patch
        │   ├── 6.18.y-301-dts-add-g12a-g12b-gxbb-series-devices.patch
        │   ├── 6.18.y-302-dts-add-gxl-series-devices.patch
        │   ├── 6.18.y-303-dts-add-gxm-sm1-series-devices.patch
        │   ├── 6.18.y-304-dts-add-rk3328-rk3399-series-devices.patch
        │   ├── 6.18.y-305-dts-add-rk3566-series-devices.patch
        │   ├── 6.18.y-306-dts-add-rk3568-series-devices.patch
        │   ├── 6.18.y-307-dts-add-rk3588-series-devices.patch
        │   ├── 6.18.y-308-dts-add-rk3568-series-devices.patch
        │   ├── 6.18.y-309-dts-add-skip-version-detect-for-oes-plus.patch
        │   └── 6.6.y-101-arm64-add-text_offset.patch
        ├── linux-5.15.y/
        │   ├── 201-drm-meson-venc-add-support-for-ws7.9.patch
        │   └── 301-dts-add-rockchip-rk3399-cdhx-rb30-dtb.patch
        ├── linux-6.1.y/
        │   └── 201-fix-i2ca-and-i2cb-miossing-pins.patch
        └── linux-6.6.y/
            └── 201-fix-i2ca-and-i2cb-miossing-pins.patch

================================================
FILE CONTENTS
================================================

================================================
FILE: .github/ISSUE_TEMPLATE/bug-report.md
================================================
---
name: Bug report
about: Create a report to help us improve
title: ''
labels: ''
assignees: ''
---

**Device Information | 设备信息**
 - SOC: [e.g. S095x3]
 - Model [e.g. HK1]

**System Version | 系统版本**
 - System: [e.g. Armbian/OpenWrt]

**Kernel Version | 内核版本**
 - Kernel Version: [e.g. 5.15.100]

**Describe the bug | 问题描述**
All issues will only remain open for one week to prioritize resolving them.
After that period, they will be closed but can still continue to be discussed in the thread.
所有的问题都只保留一周的开启状态供重点关注解决，超时将关闭，但仍然可以长期继续跟帖讨论。

Please provide a detailed description of the issue and, if necessary, attach a screenshot.
详细描述问题，并在必要时附上屏幕截图。




================================================
FILE: .github/workflows/compile-allwinner-h6-kernel.yml
================================================
#==========================================================================
# Description: Compile allwinner h6 kernel
# Copyright (C) 2023 https://github.com/13584452567
# Copyright (C) 2023 https://github.com/ophub/kernel
#==========================================================================

name: Compile allwinner h6 kernel

on:
  repository_dispatch:
  workflow_dispatch:
    inputs:
      kernel_source:
        description: "Select the kernel source"
        required: false
        default: "ophub/linux-h6-6.6.y"
        type: choice
        options:
          - 13584452567/linux-6.6.y
          - ophub/linux-h6-6.6.y
      kernel_version:
        description: "Select kernel version"
        required: false
        default: "6.6.y"
        type: choice
        options:
          - 6.6.y
      kernel_auto:
        description: "Auto use the latest kernel"
        required: false
        default: true
        type: boolean
      delete_source:
        description: "Delete source after compilation"
        required: false
        default: true
        type: boolean
      kernel_package:
        description: "Select compile package list"
        required: false
        default: "all"
        type: choice
        options:
          - all
          - dtbs
      kernel_toolchain:
        description: "Select the compilation toolchain"
        required: false
        default: "gcc"
        type: choice
        options:
          - clang
          - gcc
          - gcc-15.2
          - gcc-14.3
          - gcc-14.2
      ccache_clear:
        description: "Set whether to clear the cache"
        required: false
        default: false
        type: boolean
      docker_image:
        description: "Select Armbian docker image"
        required: false
        default: "trixie"
        type: choice
        options:
          - trixie
          - bookworm
          - resolute
          - noble
      kernel_sign:
        description: "Set the kernel custom signature"
        required: false
        default: "-zicai"
        type: choice
        options:
          - -zicai
          - -ophub
          - -happy-new-year
          - -dragon-boat-festival
          - -mid-autumn-festival
          - -happy-national-day
          - -merry-christmas
          - -spring-plowing
          - -summer-growing
          - -autumn-harvesting
          - -winter-storing
          - -yourname
      kernel_config:
        description: "Set the path of kernel .config"
        required: false
        default: "kernel-config/release/h6"
        type: choice
        options:
          - kernel-config/release/h6
          - false

env:
  TZ: Etc/UTC

jobs:
  build:
    runs-on: ubuntu-24.04-arm
    if: ${{ github.event.repository.owner.id == github.event.sender.id }}

    steps:
      - name: Checkout
        uses: actions/checkout@v6

      - name: Initialize the build environment
        id: init
        env:
          DEBIAN_FRONTEND: noninteractive
        run: |
          docker rmi -f $(docker images -q) 2>/dev/null || true
          [[ -n "${AGENT_TOOLSDIRECTORY}" ]] && sudo rm -rf "${AGENT_TOOLSDIRECTORY}"
          sudo rm -rf /usr/share/dotnet /usr/local/lib/android 2>/dev/null
          sudo swapoff -a
          sudo rm -f /swapfile /mnt/swapfile
          sudo -E apt-get -y update
          sudo -E apt-get -y purge azure-cli ghc* zulu* llvm* firefox google* dotnet* powershell openjdk* mongodb* moby* || true
          sudo -E apt-get -y install $(curl -fsSL https://ophub.org/ubuntu2404-build-armbian-depends)
          sudo -E systemctl daemon-reload
          #sudo -E apt-get -y full-upgrade
          sudo -E apt-get -y autoremove --purge
          sudo -E apt-get clean
          sudo sed -i '/NVM_DIR/d;/skel/d' /root/{.bashrc,.profile}
          sudo rm -rf ~/{.cargo,.dotnet,.rustup}
          sudo -E timedatectl set-timezone "${TZ:-Etc/UTC}"
          sudo -E ntpdate ntp.ubuntu.com 0.pool.ntp.org || true
          sudo -E timedatectl set-ntp true
          date -u
          timedatectl status || true
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Create virtual disk for extended storage
        id: disk
        run: |
          mnt_size=$(expr $(df -h /mnt | tail -1 | awk '{print $4}' | sed 's/[[:alpha:]]//g' | sed 's/\..*//') - 1)
          root_size=$(expr $(df -h / | tail -1 | awk '{print $4}' | sed 's/[[:alpha:]]//g' | sed 's/\..*//') - 4)
          sudo truncate -s "${mnt_size}"G /mnt/mnt.img
          sudo truncate -s "${root_size}"G /root.img
          sudo losetup /dev/loop6 /mnt/mnt.img
          sudo losetup /dev/loop7 /root.img
          sudo pvcreate /dev/loop6
          sudo pvcreate /dev/loop7
          sudo vgcreate github /dev/loop6 /dev/loop7
          sudo lvcreate -n runner -l 100%FREE github
          sudo mkfs.xfs -f -i sparse=0 -b size=4096 /dev/github/runner
          sudo mkdir -p /builder
          sudo mount /dev/github/runner /builder
          sudo chown -R runner:runner /builder
          df -Th
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Get kernel source commit hash
        id: kernelhash
        run: |
          # Get the latest source hash from the kernel repository
          api_url="https://api.github.com/repos/${{ inputs.kernel_source }}/git/ref/heads/main"
          source_hash=$(curl -fsSL -m 20 \
              -H "Accept: application/vnd.github+json" \
              -H "Authorization: Bearer ${{ secrets.GITHUB_TOKEN }}" \
              ${api_url} |
              jq -r '.object.sha'
          )
          [[ -z "${source_hash}" || "${source_hash}" == "null" ]] && source_hash="${{ github.sha }}"
          echo "source_hash=${source_hash}" >> ${GITHUB_ENV}
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Cache ccache
        uses: actions/cache@v5
        with:
          path: /builder/ccache
          key: kernel-h6-${{ inputs.kernel_toolchain }}-${{ inputs.kernel_version }}-${{ env.source_hash }}
          restore-keys: |
            kernel-h6-${{ inputs.kernel_toolchain }}-${{ inputs.kernel_version }}-

      - name: Compile the kernel [ ${{ inputs.kernel_version }} ]
        uses: ophub/amlogic-s9xxx-armbian@main
        if: ${{ steps.disk.outputs.status == 'success' && !cancelled() }}
        with:
          build_target: kernel
          kernel_source: ${{ inputs.kernel_source }}
          kernel_version: ${{ inputs.kernel_version }}
          kernel_auto: ${{ inputs.kernel_auto }}
          delete_source: ${{ inputs.delete_source }}
          kernel_package: ${{ inputs.kernel_package }}
          kernel_toolchain: ${{ inputs.kernel_toolchain }}
          kernel_sign: ${{ inputs.kernel_sign }}
          kernel_config: ${{ inputs.kernel_config }}
          ccache_clear: ${{ inputs.ccache_clear }}
          docker_hostpath: /builder
          docker_image: ophub/armbian-${{ inputs.docker_image }}:arm64

      - name: Upload Kernel to Release
        uses: ncipollo/release-action@main
        if: ${{ env.PACKAGED_STATUS == 'success' && !cancelled() }}
        with:
          tag: kernel_h6
          artifacts: ${{ env.PACKAGED_OUTPUTPATH }}/*
          allowUpdates: true
          removeArtifacts: false
          replacesArtifacts: true
          makeLatest: true
          token: ${{ secrets.GITHUB_TOKEN }}
          body: |
            - These kernels can be used for `Armbian`, `OpenWrt` and `FnNAS`.
            - These are dedicated kernels for `Allwinner H6 (TQC-A01)` devices and are not compatible with other series.
            - 这些内核可用于 `Armbian`, `OpenWrt` 和 `FnNAS`。
            - 这些是 `全志 H6（TQC-A01）` 设备的专用内核，和其他系列不通用。

================================================
FILE: .github/workflows/compile-mainline-beta-kernel.yml
================================================
#==========================================================================
# Description: Compile mainline beta kernel
# Copyright (C) 2021 https://github.com/unifreq/openwrt_packit
# Copyright (C) 2021 https://github.com/ophub/kernel
#==========================================================================

name: Compile mainline beta kernel

on:
  repository_dispatch:
  workflow_dispatch:
    inputs:
      kernel_source:
        description: "Select the kernel source"
        required: false
        default: "unifreq"
        type: choice
        options:
          - unifreq
          - ophub
      kernel_version:
        description: "Select kernel version"
        required: false
        default: "6.12.y"
        type: choice
        options:
          - 5.10.y
          - 5.15.y
          - 6.1.y
          - 6.6.y
          - 6.12.y
          - 6.18.y
      kernel_auto:
        description: "Auto use the latest kernel"
        required: false
        default: true
        type: boolean
      kernel_package:
        description: "Select compile package list"
        required: false
        default: "all"
        type: choice
        options:
          - all
          - dtbs
      kernel_config:
        description: "Set the path of kernel .config"
        required: false
        default: "kernel-config/release/stable"
        type: choice
        options:
          - kernel-config/release/stable
          - false
      kernel_patch:
        description: "Set the directory for kernel patches"
        required: false
        default: "kernel-patch/beta"
        type: choice
        options:
          - kernel-patch/beta
          - false
      auto_patch:
        description: "Set whether to use kernel patches"
        required: false
        default: "true"
        type: choice
        options:
          - true
          - false
      kernel_toolchain:
        description: "Select the compilation toolchain"
        required: false
        default: "gcc"
        type: choice
        options:
          - clang
          - gcc
          - gcc-15.2
          - gcc-14.3
          - gcc-14.2
      ccache_clear:
        description: "Set whether to clear the cache"
        required: false
        default: false
        type: boolean
      docker_image:
        description: "Select Armbian docker image"
        required: false
        default: "trixie"
        type: choice
        options:
          - trixie
          - bookworm
          - resolute
          - noble

env:
  TZ: Etc/UTC

jobs:
  build:
    runs-on: ubuntu-24.04-arm
    if: ${{ github.event.repository.owner.id == github.event.sender.id }}

    steps:
      - name: Checkout
        uses: actions/checkout@v6

      - name: Initialize the build environment
        id: init
        env:
          DEBIAN_FRONTEND: noninteractive
        run: |
          docker rmi -f $(docker images -q) 2>/dev/null || true
          [[ -n "${AGENT_TOOLSDIRECTORY}" ]] && sudo rm -rf "${AGENT_TOOLSDIRECTORY}"
          sudo rm -rf /usr/share/dotnet /usr/local/lib/android 2>/dev/null
          sudo swapoff -a
          sudo rm -f /swapfile /mnt/swapfile
          sudo -E apt-get -y update
          sudo -E apt-get -y purge azure-cli ghc* zulu* llvm* firefox google* dotnet* powershell openjdk* mongodb* moby* || true
          sudo -E apt-get -y install $(curl -fsSL https://ophub.org/ubuntu2404-build-armbian-depends)
          sudo -E systemctl daemon-reload
          #sudo -E apt-get -y full-upgrade
          sudo -E apt-get -y autoremove --purge
          sudo -E apt-get clean
          sudo sed -i '/NVM_DIR/d;/skel/d' /root/{.bashrc,.profile}
          sudo rm -rf ~/{.cargo,.dotnet,.rustup}
          sudo -E timedatectl set-timezone "${TZ:-Etc/UTC}"
          sudo -E ntpdate ntp.ubuntu.com 0.pool.ntp.org || true
          sudo -E timedatectl set-ntp true
          date -u
          timedatectl status || true
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Create virtual disk for extended storage
        id: disk
        run: |
          mnt_size=$(expr $(df -h /mnt | tail -1 | awk '{print $4}' | sed 's/[[:alpha:]]//g' | sed 's/\..*//') - 1)
          root_size=$(expr $(df -h / | tail -1 | awk '{print $4}' | sed 's/[[:alpha:]]//g' | sed 's/\..*//') - 4)
          sudo truncate -s "${mnt_size}"G /mnt/mnt.img
          sudo truncate -s "${root_size}"G /root.img
          sudo losetup /dev/loop6 /mnt/mnt.img
          sudo losetup /dev/loop7 /root.img
          sudo pvcreate /dev/loop6
          sudo pvcreate /dev/loop7
          sudo vgcreate github /dev/loop6 /dev/loop7
          sudo lvcreate -n runner -l 100%FREE github
          sudo mkfs.xfs -f -i sparse=0 -b size=4096 /dev/github/runner
          sudo mkdir -p /builder
          sudo mount /dev/github/runner /builder
          sudo chown -R runner:runner /builder
          df -Th
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Get kernel source commit hash
        id: kernelhash
        run: |
          # Get the latest source hash from the kernel repository
          api_url="https://api.github.com/repos/${{ inputs.kernel_source }}/linux-${{ inputs.kernel_version }}/git/ref/heads/main"
          source_hash=$(curl -fsSL -m 20 \
              -H "Accept: application/vnd.github+json" \
              -H "Authorization: Bearer ${{ secrets.GITHUB_TOKEN }}" \
              ${api_url} |
              jq -r '.object.sha'
          )
          [[ -z "${source_hash}" || "${source_hash}" == "null" ]] && source_hash="${{ github.sha }}"
          echo "source_hash=${source_hash}" >> ${GITHUB_ENV}
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Cache ccache
        uses: actions/cache@v5
        with:
          path: /builder/ccache
          key: kernel-mainline-${{ inputs.kernel_toolchain }}-${{ inputs.kernel_version }}-${{ env.source_hash }}
          restore-keys: |
            kernel-mainline-${{ inputs.kernel_toolchain }}-${{ inputs.kernel_version }}-

      - name: Compile the kernel [ ${{ inputs.kernel_version }} ]
        uses: ophub/amlogic-s9xxx-armbian@main
        if: ${{ steps.disk.outputs.status == 'success' && !cancelled() }}
        with:
          build_target: kernel
          kernel_source: ${{ inputs.kernel_source }}
          kernel_version: ${{ inputs.kernel_version }}
          kernel_auto: ${{ inputs.kernel_auto }}
          kernel_package: ${{ inputs.kernel_package }}
          kernel_toolchain: ${{ inputs.kernel_toolchain }}
          kernel_config: ${{ inputs.kernel_config }}
          kernel_patch: ${{ inputs.kernel_patch }}
          auto_patch: ${{ inputs.auto_patch }}
          ccache_clear: ${{ inputs.ccache_clear }}
          kernel_sign: -beta
          delete_source: true
          docker_hostpath: /builder
          docker_image: ophub/armbian-${{ inputs.docker_image }}:arm64

      - name: Upload Kernel to Release
        uses: ncipollo/release-action@main
        if: ${{ env.PACKAGED_STATUS == 'success' && !cancelled() }}
        with:
          tag: kernel_beta
          artifacts: ${{ env.PACKAGED_OUTPUTPATH }}/*
          allowUpdates: true
          removeArtifacts: false
          replacesArtifacts: true
          makeLatest: true
          token: ${{ secrets.GITHUB_TOKEN }}
          body: |
            - These kernels can be used for `Armbian`, `OpenWrt` and `FnNAS`.
            - These are mainline `beta` kernels that may contain experimental features. Do not use unless you know what you are doing.
            - 这些内核可用于 `Armbian`, `OpenWrt` 和 `FnNAS`。
            - 这些是主线 `测试版` 内核，可能包含实验性功能，不知情勿用。


================================================
FILE: .github/workflows/compile-mainline-stable-kernel.yml
================================================
#==========================================================================
# Description: Compile mainline stable kernel
# Copyright (C) 2021 https://github.com/unifreq/openwrt_packit
# Copyright (C) 2021 https://github.com/ophub/kernel
#==========================================================================

name: Compile mainline stable kernel

on:
  repository_dispatch:
  workflow_dispatch:
    inputs:
      kernel_source:
        description: "Select the kernel source"
        required: false
        default: "unifreq"
        type: choice
        options:
          - unifreq
          - ophub
      kernel_version:
        description: "Select kernel version"
        required: false
        default: "6.12.y"
        type: choice
        options:
          - 5.10.y
          - 5.15.y
          - 6.1.y
          - 6.6.y
          - 6.12.y
          - 6.18.y
      kernel_auto:
        description: "Auto use the latest kernel"
        required: false
        default: true
        type: boolean
      delete_source:
        description: "Delete source after compilation"
        required: false
        default: true
        type: boolean
      kernel_package:
        description: "Select compile package list"
        required: false
        default: "all"
        type: choice
        options:
          - all
          - dtbs
      kernel_toolchain:
        description: "Select the compilation toolchain"
        required: false
        default: "gcc"
        type: choice
        options:
          - clang
          - gcc
          - gcc-15.2
          - gcc-14.3
          - gcc-14.2
      ccache_clear:
        description: "Set whether to clear the cache"
        required: false
        default: false
        type: boolean
      docker_image:
        description: "Select Armbian docker image"
        required: false
        default: "trixie"
        type: choice
        options:
          - trixie
          - bookworm
          - resolute
          - noble
      kernel_sign:
        description: "Set the kernel custom signature"
        required: false
        default: "-ophub"
        type: choice
        options:
          - -ophub
          - -happy-new-year
          - -dragon-boat-festival
          - -mid-autumn-festival
          - -happy-national-day
          - -merry-christmas
          - -spring-plowing
          - -summer-growing
          - -autumn-harvesting
          - -winter-storing
          - -yourname
      kernel_config:
        description: "Set the path of kernel .config"
        required: false
        default: "kernel-config/release/stable"
        type: choice
        options:
          - kernel-config/release/stable
          - false

env:
  TZ: Etc/UTC

jobs:
  build:
    runs-on: ubuntu-24.04-arm
    if: ${{ github.event.repository.owner.id == github.event.sender.id }}

    steps:
      - name: Checkout
        uses: actions/checkout@v6

      - name: Initialize the build environment
        id: init
        env:
          DEBIAN_FRONTEND: noninteractive
        run: |
          docker rmi -f $(docker images -q) 2>/dev/null || true
          [[ -n "${AGENT_TOOLSDIRECTORY}" ]] && sudo rm -rf "${AGENT_TOOLSDIRECTORY}"
          sudo rm -rf /usr/share/dotnet /usr/local/lib/android 2>/dev/null
          sudo swapoff -a
          sudo rm -f /swapfile /mnt/swapfile
          sudo -E apt-get -y update
          sudo -E apt-get -y purge azure-cli ghc* zulu* llvm* firefox google* dotnet* powershell openjdk* mongodb* moby* || true
          sudo -E apt-get -y install $(curl -fsSL https://ophub.org/ubuntu2404-build-armbian-depends)
          sudo -E systemctl daemon-reload
          #sudo -E apt-get -y full-upgrade
          sudo -E apt-get -y autoremove --purge
          sudo -E apt-get clean
          sudo sed -i '/NVM_DIR/d;/skel/d' /root/{.bashrc,.profile}
          sudo rm -rf ~/{.cargo,.dotnet,.rustup}
          sudo -E timedatectl set-timezone "${TZ:-Etc/UTC}"
          sudo -E ntpdate ntp.ubuntu.com 0.pool.ntp.org || true
          sudo -E timedatectl set-ntp true
          date -u
          timedatectl status || true
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Create virtual disk for extended storage
        id: disk
        run: |
          mnt_size=$(expr $(df -h /mnt | tail -1 | awk '{print $4}' | sed 's/[[:alpha:]]//g' | sed 's/\..*//') - 1)
          root_size=$(expr $(df -h / | tail -1 | awk '{print $4}' | sed 's/[[:alpha:]]//g' | sed 's/\..*//') - 4)
          sudo truncate -s "${mnt_size}"G /mnt/mnt.img
          sudo truncate -s "${root_size}"G /root.img
          sudo losetup /dev/loop6 /mnt/mnt.img
          sudo losetup /dev/loop7 /root.img
          sudo pvcreate /dev/loop6
          sudo pvcreate /dev/loop7
          sudo vgcreate github /dev/loop6 /dev/loop7
          sudo lvcreate -n runner -l 100%FREE github
          sudo mkfs.xfs -f -i sparse=0 -b size=4096 /dev/github/runner
          sudo mkdir -p /builder
          sudo mount /dev/github/runner /builder
          sudo chown -R runner:runner /builder
          df -Th
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Get kernel source commit hash
        id: kernelhash
        run: |
          # Get the latest source hash from the kernel repository
          api_url="https://api.github.com/repos/${{ inputs.kernel_source }}/linux-${{ inputs.kernel_version }}/git/ref/heads/main"
          source_hash=$(curl -fsSL -m 20 \
              -H "Accept: application/vnd.github+json" \
              -H "Authorization: Bearer ${{ secrets.GITHUB_TOKEN }}" \
              ${api_url} |
              jq -r '.object.sha'
          )
          [[ -z "${source_hash}" || "${source_hash}" == "null" ]] && source_hash="${{ github.sha }}"
          echo "source_hash=${source_hash}" >> ${GITHUB_ENV}
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Cache ccache
        uses: actions/cache@v5
        with:
          path: /builder/ccache
          key: kernel-mainline-${{ inputs.kernel_toolchain }}-${{ inputs.kernel_version }}-${{ env.source_hash }}
          restore-keys: |
            kernel-mainline-${{ inputs.kernel_toolchain }}-${{ inputs.kernel_version }}-

      - name: Compile the kernel [ ${{ inputs.kernel_version }} ]
        uses: ophub/amlogic-s9xxx-armbian@main
        if: ${{ steps.disk.outputs.status == 'success' && !cancelled() }}
        with:
          build_target: kernel
          kernel_source: ${{ inputs.kernel_source }}
          kernel_version: ${{ inputs.kernel_version }}
          kernel_auto: ${{ inputs.kernel_auto }}
          delete_source: ${{ inputs.delete_source }}
          kernel_package: ${{ inputs.kernel_package }}
          kernel_toolchain: ${{ inputs.kernel_toolchain }}
          kernel_sign: ${{ inputs.kernel_sign }}
          kernel_config: ${{ inputs.kernel_config }}
          ccache_clear: ${{ inputs.ccache_clear }}
          docker_hostpath: /builder
          docker_image: ophub/armbian-${{ inputs.docker_image }}:arm64

      - name: Upload Kernel to Release
        uses: ncipollo/release-action@main
        if: ${{ env.PACKAGED_STATUS == 'success' && !cancelled() }}
        with:
          tag: kernel_stable
          artifacts: ${{ env.PACKAGED_OUTPUTPATH }}/*
          allowUpdates: true
          removeArtifacts: false
          replacesArtifacts: true
          makeLatest: true
          token: ${{ secrets.GITHUB_TOKEN }}
          body: |
            - These are Mainline `stable` kernels that provide support for `Armbian`, `OpenWrt` and `FnNAS`.
            - It works with most `Amlogic`, `Rockchip`, and `Allwinner` devices. For specific details, please refer to the instructions on the homepage of each system's repository.
            - 这些是主线稳定内核，为 `Armbian`、`OpenWrt` 和 `FnNAS` 提供支持。
            - 适用于 `amlogic`，`rockchip`，`allwinner` 的大部分设备，具体可以参考各系统仓库首页的说明。


================================================
FILE: .github/workflows/compile-rockchip-rk3588-kernel.yml
================================================
#==========================================================================
# Description: Compile rockchip rk3588 kernel
# Copyright (C) 2023 https://github.com/unifreq/linux-5.10.y-rk35xx
# Copyright (C) 2023 https://github.com/ophub/kernel
#==========================================================================

name: Compile rockchip rk3588 kernel

on:
  repository_dispatch:
  workflow_dispatch:
    inputs:
      kernel_source:
        description: "Select the kernel source"
        required: false
        default: "unifreq/linux-6.1.y-rockchip"
        type: choice
        options:
          - unifreq/linux-6.1.y-rockchip
          - unifreq/linux-5.10.y-rk35xx
          - ophub/linux-6.1.y-rockchip
          - ophub/linux-5.10.y-rk35xx
          - armbian/linux-rockchip@rk-6.1-rkr6.1
          - armbian/linux-rockchip@rk-6.1-rkr5.1
      kernel_version:
        description: "Select kernel version"
        required: false
        default: "6.1.y"
        type: choice
        options:
          - 6.1.y
          - 5.10.y
      kernel_auto:
        description: "Auto use the latest kernel"
        required: false
        default: true
        type: boolean
      kernel_package:
        description: "Select compile package list"
        required: false
        default: "all"
        type: choice
        options:
          - all
          - dtbs
      kernel_toolchain:
        description: "Select the compilation toolchain"
        required: false
        default: "gcc"
        type: choice
        options:
          - gcc
          - gcc-15.2
          - gcc-14.3
          - gcc-14.2
      ccache_clear:
        description: "Set whether to clear the cache"
        required: false
        default: false
        type: boolean
      docker_image:
        description: "Select Armbian docker image"
        required: false
        default: "trixie"
        type: choice
        options:
          - trixie
          - bookworm
          - resolute
          - noble
      kernel_sign:
        description: "Set the kernel custom signature"
        required: false
        default: "-rk3588-ophub"
        type: choice
        options:
          - -rk3588-ophub
          - -happy-new-year
          - -dragon-boat-festival
          - -mid-autumn-festival
          - -happy-national-day
          - -merry-christmas
          - -spring-plowing
          - -summer-growing
          - -autumn-harvesting
          - -winter-storing
          - -yourname
      kernel_config:
        description: "Set the path of kernel .config"
        required: false
        default: "kernel-config/release/rk3588"
        type: choice
        options:
          - kernel-config/release/rk3588
          - false

env:
  TZ: Etc/UTC

jobs:
  build:
    runs-on: ubuntu-24.04-arm
    if: ${{ github.event.repository.owner.id == github.event.sender.id }}

    steps:
      - name: Checkout
        uses: actions/checkout@v6

      - name: Initialize the build environment
        id: init
        env:
          DEBIAN_FRONTEND: noninteractive
        run: |
          docker rmi -f $(docker images -q) 2>/dev/null || true
          [[ -n "${AGENT_TOOLSDIRECTORY}" ]] && sudo rm -rf "${AGENT_TOOLSDIRECTORY}"
          sudo rm -rf /usr/share/dotnet /usr/local/lib/android 2>/dev/null
          sudo swapoff -a
          sudo rm -f /swapfile /mnt/swapfile
          sudo -E apt-get -y update
          sudo -E apt-get -y purge azure-cli ghc* zulu* llvm* firefox google* dotnet* powershell openjdk* mongodb* moby* || true
          sudo -E apt-get -y install $(curl -fsSL https://ophub.org/ubuntu2404-build-armbian-depends)
          sudo -E systemctl daemon-reload
          #sudo -E apt-get -y full-upgrade
          sudo -E apt-get -y autoremove --purge
          sudo -E apt-get clean
          sudo sed -i '/NVM_DIR/d;/skel/d' /root/{.bashrc,.profile}
          sudo rm -rf ~/{.cargo,.dotnet,.rustup}
          sudo -E timedatectl set-timezone "${TZ:-Etc/UTC}"
          sudo -E ntpdate ntp.ubuntu.com 0.pool.ntp.org || true
          sudo -E timedatectl set-ntp true
          date -u
          timedatectl status || true
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Create virtual disk for extended storage
        id: disk
        run: |
          mnt_size=$(expr $(df -h /mnt | tail -1 | awk '{print $4}' | sed 's/[[:alpha:]]//g' | sed 's/\..*//') - 1)
          root_size=$(expr $(df -h / | tail -1 | awk '{print $4}' | sed 's/[[:alpha:]]//g' | sed 's/\..*//') - 4)
          sudo truncate -s "${mnt_size}"G /mnt/mnt.img
          sudo truncate -s "${root_size}"G /root.img
          sudo losetup /dev/loop6 /mnt/mnt.img
          sudo losetup /dev/loop7 /root.img
          sudo pvcreate /dev/loop6
          sudo pvcreate /dev/loop7
          sudo vgcreate github /dev/loop6 /dev/loop7
          sudo lvcreate -n runner -l 100%FREE github
          sudo mkfs.xfs -f -i sparse=0 -b size=4096 /dev/github/runner
          sudo mkdir -p /builder
          sudo mount /dev/github/runner /builder
          sudo chown -R runner:runner /builder
          df -Th
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Get kernel source commit hash
        id: kernelhash
        run: |
          # Get the kernel source branch
          kernel_source="${{ inputs.kernel_source }}"
          [[ "${kernel_source}" =~ @ ]] && kernel_branch="$(echo "${kernel_source}" | awk -F'@' '{print $2}')" || kernel_branch="main"

          # Get the latest source hash from the kernel repository
          api_url="https://api.github.com/repos/${{ inputs.kernel_source }}/git/ref/heads/${kernel_branch}"
          source_hash=$(curl -fsSL -m 20 \
              -H "Accept: application/vnd.github+json" \
              -H "Authorization: Bearer ${{ secrets.GITHUB_TOKEN }}" \
              ${api_url} |
              jq -r '.object.sha'
          )
          [[ -z "${source_hash}" || "${source_hash}" == "null" ]] && source_hash="${{ github.sha }}"
          echo "source_hash=${source_hash}" >> ${GITHUB_ENV}
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Cache ccache
        uses: actions/cache@v5
        with:
          path: /builder/ccache
          key: kernel-rk3588-${{ inputs.kernel_toolchain }}-${{ inputs.kernel_version }}-${{ env.source_hash }}
          restore-keys: |
            kernel-rk3588-${{ inputs.kernel_toolchain }}-${{ inputs.kernel_version }}-

      - name: Compile the kernel [ ${{ inputs.kernel_version }} ]
        uses: ophub/amlogic-s9xxx-armbian@main
        if: ${{ steps.disk.outputs.status == 'success' && !cancelled() }}
        with:
          build_target: kernel
          kernel_source: ${{ inputs.kernel_source }}
          kernel_version: ${{ inputs.kernel_version }}
          kernel_auto: ${{ inputs.kernel_auto }}
          kernel_package: ${{ inputs.kernel_package }}
          kernel_toolchain: ${{ inputs.kernel_toolchain }}
          kernel_sign: ${{ inputs.kernel_sign }}
          kernel_config: ${{ inputs.kernel_config }}
          ccache_clear: ${{ inputs.ccache_clear }}
          docker_hostpath: /builder
          docker_image: ophub/armbian-${{ inputs.docker_image }}:arm64

      - name: Upload Kernel to Release
        uses: ncipollo/release-action@main
        if: ${{ env.PACKAGED_STATUS == 'success' && !cancelled() }}
        with:
          tag: kernel_rk3588
          artifacts: ${{ env.PACKAGED_OUTPUTPATH }}/*
          allowUpdates: true
          removeArtifacts: false
          replacesArtifacts: true
          makeLatest: true
          token: ${{ secrets.GITHUB_TOKEN }}
          body: |
            - These kernels can be used for `Armbian`, `OpenWrt` and `FnNAS`.
            - These are dedicated BSP kernels for `Rockchip rk3588` and are not compatible with other series.
            - Those with `flippy` in the filename are manually uploaded kernels maintained and shared by [flippy](https://github.com/unifreq), while the others are automatically compiled online.
            - 这些内核可用于 `Armbian`, `OpenWrt` 和 `FnNAS`。
            - 这些是 `Rockchip rk3588` 专用 BSP 内核，和其他系列不通用。
            - 其中名字里带有 `flippy` 的是手动上传的由 [flippy](https://github.com/unifreq) 大佬维护制作分享的内核，其他是在线自动编译的。


================================================
FILE: .github/workflows/compile-rockchip-rk35xx-kernel.yml
================================================
#==========================================================================
# Description: Compile rockchip rk35xx kernel
# Copyright (C) 2023 https://github.com/unifreq/linux-5.10.y-rk35xx
# Copyright (C) 2023 https://github.com/ophub/kernel
#==========================================================================

name: Compile rockchip rk35xx kernel

on:
  repository_dispatch:
  workflow_dispatch:
    inputs:
      kernel_source:
        description: "Select the kernel source"
        required: false
        default: "unifreq/linux-6.1.y-rockchip"
        type: choice
        options:
          - unifreq/linux-6.1.y-rockchip
          - unifreq/linux-5.10.y-rk35xx
          - ophub/linux-6.1.y-rockchip
          - ophub/linux-5.10.y-rk35xx
          - armbian/linux-rockchip@rk-6.1-rkr6.1
          - armbian/linux-rockchip@rk-6.1-rkr5.1
      kernel_version:
        description: "Select kernel version"
        required: false
        default: "6.1.y"
        type: choice
        options:
          - 6.1.y
          - 5.10.y
      kernel_auto:
        description: "Auto use the latest kernel"
        required: false
        default: true
        type: boolean
      kernel_package:
        description: "Select compile package list"
        required: false
        default: "all"
        type: choice
        options:
          - all
          - dtbs
      kernel_toolchain:
        description: "Select the compilation toolchain"
        required: false
        default: "gcc"
        type: choice
        options:
          - gcc
          - gcc-15.2
          - gcc-14.3
          - gcc-14.2
      ccache_clear:
        description: "Set whether to clear the cache"
        required: false
        default: false
        type: boolean
      docker_image:
        description: "Select Armbian docker image"
        required: false
        default: "trixie"
        type: choice
        options:
          - trixie
          - bookworm
          - resolute
          - noble
      kernel_sign:
        description: "Set the kernel custom signature"
        required: false
        default: "-rk35xx-ophub"
        type: choice
        options:
          - -rk35xx-ophub
          - -happy-new-year
          - -dragon-boat-festival
          - -mid-autumn-festival
          - -happy-national-day
          - -merry-christmas
          - -spring-plowing
          - -summer-growing
          - -autumn-harvesting
          - -winter-storing
          - -yourname
      kernel_config:
        description: "Set the path of kernel .config"
        required: false
        default: "kernel-config/release/rk35xx"
        type: choice
        options:
          - kernel-config/release/rk35xx
          - false

env:
  TZ: Etc/UTC

jobs:
  build:
    runs-on: ubuntu-24.04-arm
    if: ${{ github.event.repository.owner.id == github.event.sender.id }}

    steps:
      - name: Checkout
        uses: actions/checkout@v6

      - name: Initialize the build environment
        id: init
        env:
          DEBIAN_FRONTEND: noninteractive
        run: |
          docker rmi -f $(docker images -q) 2>/dev/null || true
          [[ -n "${AGENT_TOOLSDIRECTORY}" ]] && sudo rm -rf "${AGENT_TOOLSDIRECTORY}"
          sudo rm -rf /usr/share/dotnet /usr/local/lib/android 2>/dev/null
          sudo swapoff -a
          sudo rm -f /swapfile /mnt/swapfile
          sudo -E apt-get -y update
          sudo -E apt-get -y purge azure-cli ghc* zulu* llvm* firefox google* dotnet* powershell openjdk* mongodb* moby* || true
          sudo -E apt-get -y install $(curl -fsSL https://ophub.org/ubuntu2404-build-armbian-depends)
          sudo -E systemctl daemon-reload
          #sudo -E apt-get -y full-upgrade
          sudo -E apt-get -y autoremove --purge
          sudo -E apt-get clean
          sudo sed -i '/NVM_DIR/d;/skel/d' /root/{.bashrc,.profile}
          sudo rm -rf ~/{.cargo,.dotnet,.rustup}
          sudo -E timedatectl set-timezone "${TZ:-Etc/UTC}"
          sudo -E ntpdate ntp.ubuntu.com 0.pool.ntp.org || true
          sudo -E timedatectl set-ntp true
          date -u
          timedatectl status || true
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Create virtual disk for extended storage
        id: disk
        run: |
          mnt_size=$(expr $(df -h /mnt | tail -1 | awk '{print $4}' | sed 's/[[:alpha:]]//g' | sed 's/\..*//') - 1)
          root_size=$(expr $(df -h / | tail -1 | awk '{print $4}' | sed 's/[[:alpha:]]//g' | sed 's/\..*//') - 4)
          sudo truncate -s "${mnt_size}"G /mnt/mnt.img
          sudo truncate -s "${root_size}"G /root.img
          sudo losetup /dev/loop6 /mnt/mnt.img
          sudo losetup /dev/loop7 /root.img
          sudo pvcreate /dev/loop6
          sudo pvcreate /dev/loop7
          sudo vgcreate github /dev/loop6 /dev/loop7
          sudo lvcreate -n runner -l 100%FREE github
          sudo mkfs.xfs -f -i sparse=0 -b size=4096 /dev/github/runner
          sudo mkdir -p /builder
          sudo mount /dev/github/runner /builder
          sudo chown -R runner:runner /builder
          df -Th
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Get kernel source commit hash
        id: kernelhash
        run: |
          # Get the kernel source branch
          kernel_source="${{ inputs.kernel_source }}"
          [[ "${kernel_source}" =~ @ ]] && kernel_branch="$(echo "${kernel_source}" | awk -F'@' '{print $2}')" || kernel_branch="main"

          # Get the latest source hash from the kernel repository
          api_url="https://api.github.com/repos/${{ inputs.kernel_source }}/git/ref/heads/${kernel_branch}"
          source_hash=$(curl -fsSL -m 20 \
              -H "Accept: application/vnd.github+json" \
              -H "Authorization: Bearer ${{ secrets.GITHUB_TOKEN }}" \
              ${api_url} |
              jq -r '.object.sha'
          )
          [[ -z "${source_hash}" || "${source_hash}" == "null" ]] && source_hash="${{ github.sha }}"
          echo "source_hash=${source_hash}" >> ${GITHUB_ENV}
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Cache ccache
        uses: actions/cache@v5
        with:
          path: /builder/ccache
          key: kernel-rk35xx-${{ inputs.kernel_toolchain }}-${{ inputs.kernel_version }}-${{ env.source_hash }}
          restore-keys: |
            kernel-rk35xx-${{ inputs.kernel_toolchain }}-${{ inputs.kernel_version }}-

      - name: Compile the kernel [ ${{ inputs.kernel_version }} ]
        uses: ophub/amlogic-s9xxx-armbian@main
        if: ${{ steps.disk.outputs.status == 'success' && !cancelled() }}
        with:
          build_target: kernel
          kernel_source: ${{ inputs.kernel_source }}
          kernel_version: ${{ inputs.kernel_version }}
          kernel_auto: ${{ inputs.kernel_auto }}
          kernel_package: ${{ inputs.kernel_package }}
          kernel_toolchain: ${{ inputs.kernel_toolchain }}
          kernel_sign: ${{ inputs.kernel_sign }}
          kernel_config: ${{ inputs.kernel_config }}
          ccache_clear: ${{ inputs.ccache_clear }}
          docker_hostpath: /builder
          docker_image: ophub/armbian-${{ inputs.docker_image }}:arm64

      - name: Upload Kernel to Release
        uses: ncipollo/release-action@main
        if: ${{ env.PACKAGED_STATUS == 'success' && !cancelled() }}
        with:
          tag: kernel_rk35xx
          artifacts: ${{ env.PACKAGED_OUTPUTPATH }}/*
          allowUpdates: true
          removeArtifacts: false
          replacesArtifacts: true
          makeLatest: true
          token: ${{ secrets.GITHUB_TOKEN }}
          body: |
            - These kernels can be used for `Armbian`, `OpenWrt` and `FnNAS`.
            - These are dedicated BSP kernels for `Rockchip rk3528/rk3566/rk3568` and are not compatible with other series.
            - Those with `flippy` in the filename are manually uploaded kernels maintained and shared by [flippy](https://github.com/unifreq), while the others are automatically compiled online.
            - 这些内核可用于 `Armbian`, `OpenWrt` 和 `FnNAS`。
            - 这些是 `Rockchip rk3528/rk3566/rk3568` 专用 BSP 内核，和其他系列不通用。
            - 其中名字里带有 `flippy` 的是手动上传的由 [flippy](https://github.com/unifreq) 大佬维护制作分享的内核，其他是在线自动编译的。


================================================
FILE: .github/workflows/delete-older-releases-workflows.yml
================================================
#==========================================================================
# https://github.com/ophub/kernel
# Description: Delete older releases and workflows runs
#==========================================================================

name: Delete older releases and workflows

on:
  repository_dispatch:
  workflow_dispatch:
    inputs:
      del_workflows:
        description: "Delete workflows records?"
        required: true
        default: true
        type: boolean
      workflows_keep_day:
        description: "Days to keep workflows."
        required: false
        default: "1"
        type: choice
        options:
          - 30
          - 20
          - 10
          - 9
          - 8
          - 7
          - 6
          - 5
          - 4
          - 3
          - 2
          - 1
          - 0
      workflows_keep_keyword:
        description: "keywords for keep workflows."
        required: false
        default: ""
      out_log:
        description: "Output detailed JSON logs."
        required: false
        default: true
        type: boolean

env:
  TZ: Etc/UTC

jobs:
  build:
    runs-on: ubuntu-24.04-arm
    if: ${{ github.event.repository.owner.id == github.event.sender.id }}

    steps:
      - name: Checkout
        uses: actions/checkout@v6

      - name: Initialize the environment
        id: init
        env:
          DEBIAN_FRONTEND: noninteractive
        run: |
          sudo timedatectl set-timezone "${TZ}"
          echo "status=success" >> ${GITHUB_OUTPUT}

      - name: Delete releases and workflows runs
        uses: ophub/delete-releases-workflows@main
        with:
          delete_releases: false
          delete_tags: false
          delete_workflows: ${{ inputs.del_workflows }}
          workflows_keep_day: ${{ inputs.workflows_keep_day }}
          workflows_keep_keyword: ${{ inputs.workflows_keep_keyword }}
          out_log: ${{ inputs.out_log }}
          gh_token: ${{ secrets.GITHUB_TOKEN }}


================================================
FILE: .gitignore
================================================
!.gitignore
.DS_Store
npm-debug.log*
*.rej
*.orig
*~
\#*#


================================================
FILE: LICENSE
================================================
                    GNU GENERAL PUBLIC LICENSE
                       Version 2, June 1991

 Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
 Everyone is permitted to copy and distribute verbatim copies
 of this license document, but changing it is not allowed.

                            Preamble

  The licenses for most software are designed to take away your
freedom to share and change it.  By contrast, the GNU General Public
License is intended to guarantee your freedom to share and change free
software--to make sure the software is free for all its users.  This
General Public License applies to most of the Free Software
Foundation's software and to any other program whose authors commit to
using it.  (Some other Free Software Foundation software is covered by
the GNU Lesser General Public License instead.)  You can apply it to
your programs, too.

  When we speak of free software, we are referring to freedom, not
price.  Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
this service if you wish), that you receive source code or can get it
if you want it, that you can change the software or use pieces of it
in new free programs; and that you know you can do these things.

  To protect your rights, we need to make restrictions that forbid
anyone to deny you these rights or to ask you to surrender the rights.
These restrictions translate to certain responsibilities for you if you
distribute copies of the software, or if you modify it.

  For example, if you distribute copies of such a program, whether
gratis or for a fee, you must give the recipients all the rights that
you have.  You must make sure that they, too, receive or can get the
source code.  And you must show them these terms so they know their
rights.

  We protect your rights with two steps: (1) copyright the software, and
(2) offer you this license which gives you legal permission to copy,
distribute and/or modify the software.

  Also, for each author's protection and ours, we want to make certain
that everyone understands that there is no warranty for this free
software.  If the software is modified by someone else and passed on, we
want its recipients to know that what they have is not the original, so
that any problems introduced by others will not reflect on the original
authors' reputations.

  Finally, any free program is threatened constantly by software
patents.  We wish to avoid the danger that redistributors of a free
program will individually obtain patent licenses, in effect making the
program proprietary.  To prevent this, we have made it clear that any
patent must be licensed for everyone's free use or not licensed at all.

  The precise terms and conditions for copying, distribution and
modification follow.

                    GNU GENERAL PUBLIC LICENSE
   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION

  0. This License applies to any program or other work which contains
a notice placed by the copyright holder saying it may be distributed
under the terms of this General Public License.  The "Program", below,
refers to any such program or work, and a "work based on the Program"
means either the Program or any derivative work under copyright law:
that is to say, a work containing the Program or a portion of it,
either verbatim or with modifications and/or translated into another
language.  (Hereinafter, translation is included without limitation in
the term "modification".)  Each licensee is addressed as "you".

Activities other than copying, distribution and modification are not
covered by this License; they are outside its scope.  The act of
running the Program is not restricted, and the output from the Program
is covered only if its contents constitute a work based on the
Program (independent of having been made by running the Program).
Whether that is true depends on what the Program does.

  1. You may copy and distribute verbatim copies of the Program's
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  <signature of Ty Coon>, 1 April 1989
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consider it more useful to permit linking proprietary applications with the
library.  If this is what you want to do, use the GNU Lesser General
Public License instead of this License.


================================================
FILE: README.cn.md
================================================
# 内核说明

[English Instructions](README.md) | [中文说明](README.cn.md)

这些内核适用于 `Armbian`、`OpenWrt` 和 `FnNAS` 系统，例如 [amlogic-s9xxx-armbian](https://github.com/ophub/amlogic-s9xxx-armbian)、[amlogic-s9xxx-openwrt](https://github.com/ophub/amlogic-s9xxx-openwrt)、[fnnas](https://github.com/ophub/fnnas)、[flippy-openwrt-actions](https://github.com/ophub/flippy-openwrt-actions) 和 [unifreq/openwrt_packit](https://github.com/unifreq/openwrt_packit) 等项目。内核既可以在编译固件时集成，也可以安装到现有系统中使用。其中 [kernel_stable](https://github.com/ophub/kernel/releases/tag/kernel_stable)、[kernel_flippy](https://github.com/ophub/kernel/releases/tag/kernel_flippy) 和 [kernel_beta](https://github.com/ophub/kernel/releases/tag/kernel_beta) 是可互换使用的主线内核。具体使用方法详见[内核使用说明](https://github.com/ophub/amlogic-s9xxx-armbian/blob/main/compile-kernel/README.cn.md#内核使用说明)。


- Releases 中的 [kernel_stable](https://github.com/ophub/kernel/releases/tag/kernel_stable) 为`稳定版`内核，根据用户需求启用了更多支持选项。
- Releases 中的 [kernel_flippy](https://github.com/ophub/kernel/releases/tag/kernel_flippy) 为`稳定版`内核，由 `flippy` 制作并分享的系列内核。
- Releases 中的 [kernel_beta](https://github.com/ophub/kernel/releases/tag/kernel_beta) 为`测试版`内核，支持自定义添加第三方驱动补丁，并支持自定义配置编译。
- Releases 中的 [kernel_rk3588](https://github.com/ophub/kernel/releases/tag/kernel_rk3588) 为 `rk3588` 系列的`专用版本`，与其他系列不通用。
- Releases 中的 [kernel_rk35xx](https://github.com/ophub/kernel/releases/tag/kernel_rk35xx) 为 `rk3528/rk3566/rk3568` 系列的`专用版本`，与其他系列不通用。
- Releases 中的 [kernel_h6](https://github.com/ophub/kernel/releases/tag/kernel_h6) 为 `全志 H6（TQC-A01）` 设备的`专用版本`，与其他系列不通用。
- Releases 中的 [dev](https://github.com/ophub/kernel/releases/tag/dev) 提供了编译内核所需的`交叉编译工具链`下载镜像。
- Releases 中的 [tools](https://github.com/ophub/kernel/releases/tag/tools) 提供了部分常见电视盒子的`安卓系统`下载镜像，在使用 Armbian 或 OpenWrt 系统时可用于恢复安卓系统。

## 编译内核

- 内核编译方法详见 [compile-kernel](https://github.com/ophub/amlogic-s9xxx-armbian/tree/main/compile-kernel)。使用 GitHub Actions 编译内核的方法可参考 [.github/workflows](.github/workflows)。可通过修改 [kernel-config](kernel-config) 中的内核配置文件自定义内核，也可在 [kernel-patch](kernel-patch) 目录下添加自定义内核补丁。

- 你可以根据需要调整内核配置，例如添加驱动和补丁。也可以编译具有特殊意义的个性化签名内核，例如 `5.10.95-happy-new-year`、`5.10.96-beijing-winter-olympics`、`5.10.99-valentines-day` 等。


```yaml
- name: Compile the kernel
  uses: ophub/amlogic-s9xxx-armbian@main
  with:
    build_target: kernel
    kernel_version: 6.1.y_6.12.y
    kernel_auto: true
    kernel_sign: -yourname
```

## 内核源码

特别感谢 unifreq 等贡献者维护的内核源码。目前本仓库中的内核文件所使用的源码如下：

| 内核标签        | 源码仓库               | 适用设备               |
| ------------- | --------------------- | --------------------- |
| [kernel_stable](https://github.com/ophub/kernel/releases/tag/kernel_stable)<br>[kernel_flippy](https://github.com/ophub/kernel/releases/tag/kernel_flippy)<br>[kernel_beta](https://github.com/ophub/kernel/releases/tag/kernel_beta) | [unifreq/linux-5.10.y](https://github.com/unifreq/linux-5.10.y)<br>[unifreq/linux-5.15.y](https://github.com/unifreq/linux-5.15.y)<br>[unifreq/linux-6.1.y](https://github.com/unifreq/linux-6.1.y)<br>[unifreq/linux-6.6.y](https://github.com/unifreq/linux-6.6.y)<br>[unifreq/linux-6.12.y](https://github.com/unifreq/linux-6.12.y)<br>[unifreq/linux-6.18.y](https://github.com/unifreq/linux-6.18.y) | Amlogic<br>Allwinner<br>Rockchip |
| [kernel_rk3588](https://github.com/ophub/kernel/releases/tag/kernel_rk3588) | [unifreq/linux-5.10.y-rk35xx](https://github.com/unifreq/linux-5.10.y-rk35xx)<br>[unifreq/linux-6.1.y-rockchip](https://github.com/unifreq/linux-6.1.y-rockchip) | Rockchip-RK3588 |
| [kernel_rk35xx](https://github.com/ophub/kernel/releases/tag/kernel_rk35xx) | [unifreq/linux-5.10.y-rk35xx](https://github.com/unifreq/linux-5.10.y-rk35xx)<br>[unifreq/linux-6.1.y-rockchip](https://github.com/unifreq/linux-6.1.y-rockchip) | Rockchip-RK3528/RK3566/RK3568 |
| [kernel_h6](https://github.com/ophub/kernel/releases/tag/kernel_h6) | [13584452567/linux-6.4.y](https://github.com/13584452567/linux-6.4.y)<br>[13584452567/linux-6.5.y](https://github.com/13584452567/linux-6.5.y)<br>[13584452567/linux-6.6.y](https://github.com/13584452567/linux-6.6.y) | Allwinner-H6(TQC-A01) |
| [kernel_stable](https://github.com/ophub/kernel/releases/tag/kernel_stable)<br>[kernel_h6](https://github.com/ophub/kernel/releases/tag/kernel_h6)<br>[kernel_rk3588](https://github.com/ophub/kernel/releases/tag/kernel_rk3588)<br>[kernel_rk35xx](https://github.com/ophub/kernel/releases/tag/kernel_rk35xx) | [ophub/linux-5.10.y](https://github.com/ophub/linux-5.10.y)<br>[ophub/linux-5.15.y](https://github.com/ophub/linux-5.15.y)<br>[ophub/linux-6.1.y](https://github.com/ophub/linux-6.1.y)<br>[ophub/linux-6.6.y](https://github.com/ophub/linux-6.6.y)<br>[ophub/linux-6.12.y](https://github.com/ophub/linux-6.12.y)<br>[ophub/linux-6.18.y](https://github.com/ophub/linux-6.18.y)<br>[ophub/linux-h6-6.6.y](https://github.com/ophub/linux-h6-6.6.y)<br>[ophub/linux-5.10.y-rk35xx](https://github.com/ophub/linux-5.10.y-rk35xx)<br>[ophub/linux-6.1.y-rockchip](https://github.com/ophub/linux-6.1.y-rockchip) | 内核源码复制自 [unifreq](https://github.com/unifreq)、[13584452567](https://github.com/13584452567) 和 [chewitt](https://github.com/chewitt/linux) 的仓库，<br>便于学习和参考内核补丁的制作方法。 |
| [kernel_rk3588](https://github.com/ophub/kernel/releases/tag/kernel_rk3588) | [armbian/linux-rockchip](https://github.com/armbian/linux-rockchip) | Rockchip-Beta(6.1.y) |
| [kernel_rk35xx](https://github.com/ophub/kernel/releases/tag/kernel_rk35xx) | [armbian/linux-rockchip](https://github.com/armbian/linux-rockchip) | Rockchip-Beta(6.1.y) |


## 链接

- [unifreq/kernel](https://github.com/unifreq)
- [13584452567/kernel](https://github.com/13584452567/linux-6.4.y)
- [chewitt/linux](https://github.com/chewitt/linux)
- [torvalds/linux](https://github.com/torvalds/linux)
- [kernel.org](https://kernel.org)
- [amlogic-s9xxx-armbian](https://github.com/ophub/amlogic-s9xxx-armbian)
- [amlogic-s9xxx-openwrt](https://github.com/ophub/amlogic-s9xxx-openwrt)
- [flippy-openwrt-actions](https://github.com/ophub/flippy-openwrt-actions)
- [fnnas](https://github.com/ophub/fnnas)

## License

The kernel © OPHUB is licensed under [GPL-2.0](https://github.com/ophub/kernel/blob/main/LICENSE)


================================================
FILE: README.md
================================================
# Kernel Description

[English Instructions](README.md) | [中文说明](README.cn.md)

These kernels can be used with `Armbian`, `OpenWrt`, and `FnNAS` systems, such as the [amlogic-s9xxx-armbian](https://github.com/ophub/amlogic-s9xxx-armbian), [amlogic-s9xxx-openwrt](https://github.com/ophub/amlogic-s9xxx-openwrt), [fnnas](https://github.com/ophub/fnnas), [flippy-openwrt-actions](https://github.com/ophub/flippy-openwrt-actions), and [unifreq/openwrt_packit](https://github.com/unifreq/openwrt_packit) projects. They can be integrated during firmware compilation or installed into an existing system. Among them, [kernel_stable](https://github.com/ophub/kernel/releases/tag/kernel_stable), [kernel_flippy](https://github.com/ophub/kernel/releases/tag/kernel_flippy), and [kernel_beta](https://github.com/ophub/kernel/releases/tag/kernel_beta) are interchangeable mainline kernels. For detailed usage instructions, see the [Kernel Use Instructions](https://github.com/ophub/amlogic-s9xxx-armbian/tree/main/compile-kernel).

- The kernel files in the [kernel_stable](https://github.com/ophub/kernel/releases/tag/kernel_stable) section of the Releases are the `stable version`, with additional support options enabled based on user requirements.
- The kernel files in the [kernel_flippy](https://github.com/ophub/kernel/releases/tag/kernel_flippy) section of the Releases are the `stable version`, a series of kernels created and shared by `flippy`.
- The kernel files in the [kernel_beta](https://github.com/ophub/kernel/releases/tag/kernel_beta) section of the Releases are the `beta version`, which support adding custom third-party driver patches and custom build configurations.
- The kernel files in the [kernel_rk3588](https://github.com/ophub/kernel/releases/tag/kernel_rk3588) section of the Releases are a `dedicated version` for the `rk3588` series and are not interchangeable with other series.
- The kernel files in the [kernel_rk35xx](https://github.com/ophub/kernel/releases/tag/kernel_rk35xx) section of the Releases are a `dedicated version` for the `rk3528/rk3566/rk3568` series and are not interchangeable with other series.
- The kernel files in the [kernel_h6](https://github.com/ophub/kernel/releases/tag/kernel_h6) section of the Releases are a `dedicated version` for the `Allwinner H6 (TQC-A01)` device and are not interchangeable with other series.
- The [dev](https://github.com/ophub/kernel/releases/tag/dev) section in the Releases provides `cross-compilation toolchain` downloads required for kernel compilation.
- The [tools](https://github.com/ophub/kernel/releases/tag/tools) section in the Releases provides `Android system` images for common TV boxes, which can be used to restore the Android system when running Armbian or OpenWrt.


## Kernel Compilation

- For kernel compilation instructions, please refer to [compile-kernel](https://github.com/ophub/amlogic-s9xxx-armbian/tree/main/compile-kernel). For compiling kernels using GitHub Actions, refer to [.github/workflows](.github/workflows). You can customize the kernel by modifying the kernel configuration files in [kernel-config](kernel-config) and add custom kernel patches in the [kernel-patch](kernel-patch) directory.

- You can adjust the kernel configuration as needed, such as adding drivers and patches. You can also compile a personalized signature kernel with special meaning, such as `5.10.95-happy-new-year`, `5.10.96-beijing-winter-olympics`, `5.10.99-valentines-day`, etc.

```yaml
- name: Compile the kernel
  uses: ophub/amlogic-s9xxx-armbian@main
  with:
    build_target: kernel
    kernel_version: 6.1.y_6.12.y
    kernel_auto: true
    kernel_sign: -yourname
```

## Kernel Source Code

Special thanks to unifreq and other contributors for maintaining the kernel source code. The source code used by the kernels in this repository is as follows:

| Kernel Tags   | Source Code Repository  | Applicable devices      |
| ------------- | ----------------------- | ----------------------- |
| [kernel_stable](https://github.com/ophub/kernel/releases/tag/kernel_stable)<br>[kernel_flippy](https://github.com/ophub/kernel/releases/tag/kernel_flippy)<br>[kernel_beta](https://github.com/ophub/kernel/releases/tag/kernel_beta) | [unifreq/linux-5.10.y](https://github.com/unifreq/linux-5.10.y)<br>[unifreq/linux-5.15.y](https://github.com/unifreq/linux-5.15.y)<br>[unifreq/linux-6.1.y](https://github.com/unifreq/linux-6.1.y)<br>[unifreq/linux-6.6.y](https://github.com/unifreq/linux-6.6.y)<br>[unifreq/linux-6.12.y](https://github.com/unifreq/linux-6.12.y)<br>[unifreq/linux-6.18.y](https://github.com/unifreq/linux-6.18.y) | Amlogic<br>Allwinner<br>Rockchip |
| [kernel_rk3588](https://github.com/ophub/kernel/releases/tag/kernel_rk3588) | [unifreq/linux-5.10.y-rk35xx](https://github.com/unifreq/linux-5.10.y-rk35xx)<br>[unifreq/linux-6.1.y-rockchip](https://github.com/unifreq/linux-6.1.y-rockchip) | Rockchip-RK3588 |
| [kernel_rk35xx](https://github.com/ophub/kernel/releases/tag/kernel_rk35xx) | [unifreq/linux-5.10.y-rk35xx](https://github.com/unifreq/linux-5.10.y-rk35xx)<br>[unifreq/linux-6.1.y-rockchip](https://github.com/unifreq/linux-6.1.y-rockchip) | Rockchip-RK3528/RK3566/RK3568 |
| [kernel_h6](https://github.com/ophub/kernel/releases/tag/kernel_h6) | [13584452567/linux-6.4.y](https://github.com/13584452567/linux-6.4.y)<br>[13584452567/linux-6.5.y](https://github.com/13584452567/linux-6.5.y)<br>[13584452567/linux-6.6.y](https://github.com/13584452567/linux-6.6.y) | Allwinner-H6(TQC-A01) |
| [kernel_stable](https://github.com/ophub/kernel/releases/tag/kernel_stable)<br>[kernel_h6](https://github.com/ophub/kernel/releases/tag/kernel_h6)<br>[kernel_rk3588](https://github.com/ophub/kernel/releases/tag/kernel_rk3588)<br>[kernel_rk35xx](https://github.com/ophub/kernel/releases/tag/kernel_rk35xx) | [ophub/linux-5.10.y](https://github.com/ophub/linux-5.10.y)<br>[ophub/linux-5.15.y](https://github.com/ophub/linux-5.15.y)<br>[ophub/linux-6.1.y](https://github.com/ophub/linux-6.1.y)<br>[ophub/linux-6.6.y](https://github.com/ophub/linux-6.6.y)<br>[ophub/linux-6.12.y](https://github.com/ophub/linux-6.12.y)<br>[ophub/linux-6.18.y](https://github.com/ophub/linux-6.18.y)<br>[ophub/linux-h6-6.6.y](https://github.com/ophub/linux-h6-6.6.y)<br>[ophub/linux-5.10.y-rk35xx](https://github.com/ophub/linux-5.10.y-rk35xx)<br>[ophub/linux-6.1.y-rockchip](https://github.com/ophub/linux-6.1.y-rockchip) | The kernel source code was forked from the repositories <br>of [unifreq](https://github.com/unifreq), [13584452567](https://github.com/13584452567), and [chewitt](https://github.com/chewitt/linux), to facilitate learning <br>kernel patching techniques from these contributors. |
| [kernel_rk3588](https://github.com/ophub/kernel/releases/tag/kernel_rk3588) | [armbian/linux-rockchip](https://github.com/armbian/linux-rockchip) | Rockchip-Beta(6.1.y) |
| [kernel_rk35xx](https://github.com/ophub/kernel/releases/tag/kernel_rk35xx) | [armbian/linux-rockchip](https://github.com/armbian/linux-rockchip) | Rockchip-Beta(6.1.y) |

## Links

- [unifreq/kernel](https://github.com/unifreq)
- [13584452567/kernel](https://github.com/13584452567/linux-6.4.y)
- [chewitt/linux](https://github.com/chewitt/linux)
- [torvalds/linux](https://github.com/torvalds/linux)
- [kernel.org](https://kernel.org)
- [amlogic-s9xxx-armbian](https://github.com/ophub/amlogic-s9xxx-armbian)
- [amlogic-s9xxx-openwrt](https://github.com/ophub/amlogic-s9xxx-openwrt)
- [flippy-openwrt-actions](https://github.com/ophub/flippy-openwrt-actions)
- [fnnas](https://github.com/ophub/fnnas)

## License

The kernel © OPHUB is licensed under [GPL-2.0](https://github.com/ophub/kernel/blob/main/LICENSE)


================================================
FILE: kernel-config/README.md
================================================
# Kernel Custom Configuration Guide

When performing cloud compilation using GitHub Actions, you can use the `kernel_config` parameter to specify a custom kernel configuration. Configuration files for each kernel version are named using the major version number (e.g., config-6.1). Refer to the settings in [compile-mainline-stable-kernel.yml](../.github/workflows/compile-mainline-stable-kernel.yml):

```yaml
- name: Compile the kernel
  uses: ophub/amlogic-s9xxx-armbian@main
  with:
    build_target: kernel
    kernel_version: 5.15.y_6.1.y
    kernel_auto: true
    kernel_config: kernel-config/release/stable
```

If no custom configuration is required, this parameter can be omitted. The default kernel configuration file [compile-kernel/tools/config](https://github.com/ophub/amlogic-s9xxx-armbian/tree/main/compile-kernel/tools/config) will be used for compilation. For more details, please refer to the [Kernel Compilation Guide](https://github.com/ophub/amlogic-s9xxx-armbian/tree/main/compile-kernel).

# 内核自定义配置说明

在 GitHub Actions 云编译时，可以使用 `kernel_config` 参数指定自定义内核配置。各内核版本的配置文件（config-k.x）以主版本号命名（例如：config-6.1），使用方法可参考 [compile-mainline-stable-kernel.yml](../.github/workflows/compile-mainline-stable-kernel.yml) 中的设置：

```yaml
- name: Compile the kernel
  uses: ophub/amlogic-s9xxx-armbian@main
  with:
    build_target: kernel
    kernel_version: 5.15.y_6.1.y
    kernel_auto: true
    kernel_config: kernel-config/release/stable
```

如果没有特殊需求，可以不指定自定义配置，编译时将采用默认内核配置文件 [compile-kernel/tools/config](https://github.com/ophub/amlogic-s9xxx-armbian/tree/main/compile-kernel/tools/config) 进行编译。更多详情请参考[内核编译说明](https://github.com/ophub/amlogic-s9xxx-armbian/tree/main/compile-kernel)文档。


================================================
FILE: kernel-config/release/h6/config-6.4
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 6.4.12 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 12.3.Rel1 (Build arm-12.35)) 12.3.1 20230626"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=120301
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=24000
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=24000
CONFIG_LLD_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_PAHOLE_VERSION=125
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
CONFIG_WATCH_QUEUE=y
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_USELIB is not set
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_INJECTION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem

CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
# CONFIG_NO_HZ_FULL is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y

#
# BPF subsystem
#
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_JIT=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
CONFIG_BPF_JIT_DEFAULT_ON=y
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
CONFIG_USERMODE_DRIVER=y
# CONFIG_BPF_PRELOAD is not set
# end of BPF subsystem

CONFIG_PREEMPT_VOLUNTARY_BUILD=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
# CONFIG_PREEMPT_DYNAMIC is not set
CONFIG_SCHED_CORE=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_SCHED_AVG_IRQ=y
CONFIG_SCHED_THERMAL_PRESSURE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_PSI=y
# CONFIG_PSI_DEFAULT_DISABLED is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
# CONFIG_PRINTK_INDEX is not set
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
# CONFIG_UCLAMP_TASK is not set
# end of Scheduler features

CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_CC_HAS_INT128=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
# CONFIG_RT_GROUP_SCHED is not set
CONFIG_SCHED_MM_CID=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
# CONFIG_CGROUP_MISC is not set
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_SCHED_AUTOGROUP=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
# CONFIG_BOOT_CONFIG_FORCE is not set
# CONFIG_BOOT_CONFIG_EMBED is not set
# CONFIG_INITRAMFS_PRESERVE_MTIME is not set
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
# CONFIG_SGETMASK_SYSCALL is not set
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_SELFTEST is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_GUEST_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
# end of General setup

CONFIG_ARM64=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_CONT_PTE_SHIFT=4
CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y

#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
CONFIG_ARCH_SUNXI=y
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_APPLE is not set
# CONFIG_ARCH_BCM is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SPARX5 is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_KEEMBAY is not set
# CONFIG_ARCH_MEDIATEK is not set
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_NXP is not set
# CONFIG_ARCH_NPCM is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_RENESAS is not set
# CONFIG_ARCH_ROCKCHIP is not set
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_INTEL_SOCFPGA is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
CONFIG_ARCH_VEXPRESS=y
# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZYNQMP is not set
# end of Platform selection

#
# Kernel Features
#

#
# ARM errata workarounds via the alternatives framework
#
# CONFIG_AMPERE_ERRATUM_AC03_CPU_38 is not set
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_834220=y
# CONFIG_ARM64_ERRATUM_1742098 is not set
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1319367=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
# CONFIG_ARM64_ERRATUM_2441007 is not set
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_ARM64_ERRATUM_2051678=y
CONFIG_ARM64_ERRATUM_2077057=y
# CONFIG_ARM64_ERRATUM_2658417 is not set
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
CONFIG_ARM64_ERRATUM_2054223=y
CONFIG_ARM64_ERRATUM_2067961=y
# CONFIG_ARM64_ERRATUM_2441009 is not set
# CONFIG_ARM64_ERRATUM_2457168 is not set
# CONFIG_ARM64_ERRATUM_2645198 is not set
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
CONFIG_QCOM_FALKOR_ERRATUM_1009=y
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
# CONFIG_ROCKCHIP_ERRATUM_3588001 is not set
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
# end of ARM errata workarounds via the alternatives framework

CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
# CONFIG_ARM64_VA_BITS_39 is not set
CONFIG_ARM64_VA_BITS_48=y
CONFIG_ARM64_VA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SCHED_MC=y
# CONFIG_SCHED_CLUSTER is not set
CONFIG_SCHED_SMT=y
CONFIG_NR_CPUS=8
CONFIG_HOTPLUG_CPU=y
# CONFIG_NUMA is not set
CONFIG_HZ_100=y
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=100
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_PARAVIRT=y
CONFIG_PARAVIRT_TIME_ACCOUNTING=y
CONFIG_KEXEC=y
CONFIG_KEXEC_FILE=y
# CONFIG_KEXEC_SIG is not set
# CONFIG_CRASH_DUMP is not set
CONFIG_TRANS_TABLE=y
# CONFIG_XEN is not set
CONFIG_ARCH_FORCE_MAX_ORDER=10
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y
# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y

#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
CONFIG_AS_HAS_LDAPR=y
CONFIG_AS_HAS_LSE_ATOMICS=y
CONFIG_ARM64_LSE_ATOMICS=y
CONFIG_ARM64_USE_LSE_ATOMICS=y
# end of ARMv8.1 architectural features

#
# ARMv8.2 architectural features
#
CONFIG_AS_HAS_ARMV8_2=y
CONFIG_AS_HAS_SHA3=y
# CONFIG_ARM64_PMEM is not set
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features

#
# ARMv8.3 architectural features
#
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
CONFIG_AS_HAS_ARMV8_3=y
CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
# end of ARMv8.3 architectural features

#
# ARMv8.4 architectural features
#
CONFIG_ARM64_AMU_EXTN=y
CONFIG_AS_HAS_ARMV8_4=y
CONFIG_ARM64_TLB_RANGE=y
# end of ARMv8.4 architectural features

#
# ARMv8.5 architectural features
#
CONFIG_AS_HAS_ARMV8_5=y
CONFIG_ARM64_BTI=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARM64_AS_HAS_MTE=y
CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features

#
# ARMv8.7 architectural features
#
CONFIG_ARM64_EPAN=y
# end of ARMv8.7 architectural features

CONFIG_ARM64_SVE=y
# CONFIG_ARM64_SME is not set
CONFIG_ARM64_MODULE_PLTS=y
# CONFIG_ARM64_PSEUDO_NMI is not set
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
# end of Kernel Features

#
# Boot options
#
CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
CONFIG_CMDLINE="console=ttyAMA0"
CONFIG_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_CMDLINE_FORCE is not set
CONFIG_EFI_STUB=y
CONFIG_EFI=y
CONFIG_DMI=y
# end of Boot options

#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
CONFIG_HIBERNATE_CALLBACKS=y
CONFIG_HIBERNATION=y
CONFIG_HIBERNATION_SNAPSHOT_DEV=y
CONFIG_PM_STD_PARTITION=""
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
CONFIG_PM_DEBUG=y
# CONFIG_PM_ADVANCED_DEBUG is not set
CONFIG_PM_TEST_SUSPEND=y
CONFIG_PM_SLEEP_DEBUG=y
# CONFIG_DPM_WATCHDOG is not set
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_HIBERNATION_HEADER=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options

#
# CPU Power Management
#

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_DT_IDLE_STATES=y
CONFIG_DT_IDLE_GENPD=y

#
# ARM CPU Idle Drivers
#
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
# end of ARM CPU Idle Drivers
# end of CPU Idle

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_ACPI_CPPC_CPUFREQ=y
CONFIG_ACPI_CPPC_CPUFREQ_FIE=y
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_SCMI_CPUFREQ=y
# end of CPU Frequency scaling
# end of CPU Power Management

CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_GENERIC_GSI=y
CONFIG_ACPI_CCA_REQUIRED=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
# CONFIG_ACPI_FPDT is not set
CONFIG_ACPI_EC_DEBUGFS=y
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_VIDEO=m
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_TAD is not set
CONFIG_ACPI_DOCK=y
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_MCFG=y
CONFIG_ACPI_CPPC_LIB=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_IPMI=m
CONFIG_ACPI_HOTPLUG_CPU=y
CONFIG_ACPI_THERMAL=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_PCI_SLOT=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_CUSTOM_METHOD=y
# CONFIG_ACPI_BGRT is not set
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
CONFIG_HAVE_ACPI_APEI=y
# CONFIG_ACPI_APEI is not set
CONFIG_ACPI_CONFIGFS=m
# CONFIG_ACPI_PFRUT is not set
CONFIG_ACPI_IORT=y
CONFIG_ACPI_GTDT=y
CONFIG_ACPI_APMT=y
CONFIG_ACPI_PPTT=y
CONFIG_ACPI_PCC=y
# CONFIG_ACPI_FFH is not set
CONFIG_PMIC_OPREGION=y
# CONFIG_ACPI_PRMT is not set
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_HAVE_KVM=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_DIRTY_RING=y
CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y
CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_MMIO=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_KVM_XFER_TO_GUEST_WORK=y
CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
# CONFIG_NVHE_EL2_DEBUG is not set

#
# General architecture-dependent options
#
CONFIG_CRASH_CORE=y
CONFIG_KEXEC_CORE=y
CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
# CONFIG_SECCOMP_CACHE_DEBUG is not set
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
# CONFIG_SHADOW_CALL_STACK is not set
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
CONFIG_HAVE_CONTEXT_TRACKING_USER=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_ARCH_HUGE_VMALLOC=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET=y
# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
CONFIG_HAVE_PREEMPT_DYNAMIC=y
CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FUNCTION_ALIGNMENT=4
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_DEBUG is not set
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS_NONE is not set
CONFIG_MODULE_COMPRESS_GZIP=y
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
# CONFIG_MODULE_DECOMPRESS is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BLK_CGROUP_RWSTAT=y
CONFIG_BLK_CGROUP_PUNT_BIO=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_ICQ=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=y
CONFIG_BLK_DEV_ZONED=y
CONFIG_BLK_DEV_THROTTLING=y
# CONFIG_BLK_DEV_THROTTLING_LOW is not set
CONFIG_BLK_WBT=y
CONFIG_BLK_WBT_MQ=y
# CONFIG_BLK_CGROUP_IOLATENCY is not set
# CONFIG_BLK_CGROUP_IOCOST is not set
CONFIG_BLK_CGROUP_IOPRIO=y
CONFIG_BLK_DEBUG_FS=y
CONFIG_BLK_DEBUG_FS_ZONED=y
CONFIG_BLK_SED_OPAL=y
# CONFIG_BLK_INLINE_ENCRYPTION is not set

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
CONFIG_AIX_PARTITION=y
CONFIG_OSF_PARTITION=y
CONFIG_AMIGA_PARTITION=y
# CONFIG_ATARI_PARTITION is not set
CONFIG_MAC_PARTITION=y
CONFIG_MSDOS_PARTITION=y
CONFIG_BSD_DISKLABEL=y
CONFIG_MINIX_SUBPARTITION=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_UNIXWARE_DISKLABEL=y
CONFIG_LDM_PARTITION=y
# CONFIG_LDM_DEBUG is not set
CONFIG_SGI_PARTITION=y
# CONFIG_ULTRIX_PARTITION is not set
CONFIG_SUN_PARTITION=y
CONFIG_KARMA_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
# CONFIG_CMDLINE_PARTITION is not set
# end of Partition Types

CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_HOLDER_DEPRECATED=y
CONFIG_BLK_MQ_STACKING=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
# CONFIG_BFQ_CGROUP_DEBUG is not set
# end of IO Schedulers

CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK=y
CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_READ_LOCK=y
CONFIG_ARCH_INLINE_READ_LOCK_BH=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_READ_UNLOCK=y
CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_WRITE_LOCK=y
CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_SPIN_TRYLOCK=y
CONFIG_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_INLINE_SPIN_LOCK=y
CONFIG_INLINE_SPIN_LOCK_BH=y
CONFIG_INLINE_SPIN_LOCK_IRQ=y
CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_INLINE_SPIN_UNLOCK_BH=y
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_READ_LOCK=y
CONFIG_INLINE_READ_LOCK_BH=y
CONFIG_INLINE_READ_LOCK_IRQ=y
CONFIG_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_INLINE_READ_UNLOCK=y
CONFIG_INLINE_READ_UNLOCK_BH=y
CONFIG_INLINE_READ_UNLOCK_IRQ=y
CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_WRITE_LOCK=y
CONFIG_INLINE_WRITE_LOCK_BH=y
CONFIG_INLINE_WRITE_LOCK_IRQ=y
CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_INLINE_WRITE_UNLOCK=y
CONFIG_INLINE_WRITE_UNLOCK_BH=y
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_HAVE_ELF_PROT=y
CONFIG_ARCH_USE_GNU_PROPERTY=y
CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=y
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_ZPOOL=y
CONFIG_SWAP=y
CONFIG_ZSWAP=y
# CONFIG_ZSWAP_DEFAULT_ON is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set
CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo"
CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
CONFIG_ZBUD=y
CONFIG_Z3FOLD=y
CONFIG_ZSMALLOC=y
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_ZSMALLOC_CHAIN_SIZE=8

#
# SLAB allocator options
#
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLUB_TINY is not set
CONFIG_SLAB_MERGE_DEFAULT=y
CONFIG_SLAB_FREELIST_RANDOM=y
# CONFIG_SLAB_FREELIST_HARDENED is not set
# CONFIG_SLUB_STATS is not set
CONFIG_SLUB_CPU_PARTIAL=y
# end of SLAB allocator options

# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_MMU_NOTIFIER=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
# CONFIG_MEMORY_FAILURE is not set
CONFIG_ARCH_WANTS_THP_SWAP=y
# CONFIG_TRANSPARENT_HUGEPAGE is not set
CONFIG_FRONTSWAP=y
CONFIG_CMA=y
# CONFIG_CMA_DEBUG is not set
CONFIG_CMA_DEBUGFS=y
# CONFIG_CMA_SYSFS is not set
CONFIG_CMA_AREAS=7
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_ARCH_HAS_ZONE_DMA_SET=y
CONFIG_ZONE_DMA=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
CONFIG_ARCH_USES_PG_ARCH_X=y
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_TEST is not set
# CONFIG_DMAPOOL_TEST is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_SECRETMEM=y
# CONFIG_ANON_VMA_NAME is not set
# CONFIG_USERFAULTFD is not set
# CONFIG_LRU_GEN is not set
CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y
CONFIG_PER_VMA_LOCK=y
CONFIG_LOCK_MM_AND_FIND_VMA=y

#
# Data Access Monitoring
#
# CONFIG_DAMON is not set
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_EXTENSIONS=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=m
CONFIG_UNIX=y
CONFIG_UNIX_SCM=y
CONFIG_AF_UNIX_OOB=y
CONFIG_UNIX_DIAG=m
CONFIG_TLS=m
# CONFIG_TLS_DEVICE is not set
# CONFIG_TLS_TOE is not set
CONFIG_XFRM=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
# CONFIG_XFRM_INTERFACE is not set
CONFIG_XFRM_SUB_POLICY=y
CONFIG_XFRM_MIGRATE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_XFRM_AH=m
CONFIG_XFRM_ESP=m
CONFIG_XFRM_IPCOMP=m
CONFIG_NET_KEY=m
CONFIG_NET_KEY_MIGRATE=y
# CONFIG_XDP_SOCKETS is not set
CONFIG_NET_HANDSHAKE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_FIB_TRIE_STATS=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_ROUTE_CLASSID=y
# CONFIG_IP_PNP is not set
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=m
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=m
CONFIG_NET_FOU=m
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
# CONFIG_INET_ESP_OFFLOAD is not set
# CONFIG_INET_ESPINTCP is not set
CONFIG_INET_IPCOMP=m
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_DIAG=m
CONFIG_INET_TCP_DIAG=m
CONFIG_INET_UDP_DIAG=m
CONFIG_INET_RAW_DIAG=m
# CONFIG_INET_DIAG_DESTROY is not set
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_NV=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_CONG_DCTCP=m
CONFIG_TCP_CONG_CDG=m
CONFIG_TCP_CONG_BBR=m
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_TCP_MD5SIG=y
CONFIG_IPV6=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
# CONFIG_INET6_ESP_OFFLOAD is not set
# CONFIG_INET6_ESPINTCP is not set
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_MIP6=y
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=m
CONFIG_INET6_TUNNEL=m
CONFIG_IPV6_VTI=m
CONFIG_IPV6_SIT=m
CONFIG_IPV6_SIT_6RD=y
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=m
CONFIG_IPV6_GRE=m
CONFIG_IPV6_FOU=m
CONFIG_IPV6_FOU_TUNNEL=m
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
CONFIG_IPV6_SEG6_LWTUNNEL=y
CONFIG_IPV6_SEG6_HMAC=y
CONFIG_IPV6_SEG6_BPF=y
# CONFIG_IPV6_RPL_LWTUNNEL is not set
# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
CONFIG_NETLABEL=y
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=m
CONFIG_MPTCP_IPV6=y
# CONFIG_NETWORK_SECMARK is not set
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NETWORK_PHY_TIMESTAMPING=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_EGRESS=y
CONFIG_NETFILTER_SKIP_EGRESS=y
CONFIG_NETFILTER_NETLINK=m
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
CONFIG_NETFILTER_BPF_LINK=y
CONFIG_NETFILTER_NETLINK_HOOK=m
CONFIG_NETFILTER_NETLINK_ACCT=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NETFILTER_NETLINK_OSF=m
CONFIG_NF_CONNTRACK=m
CONFIG_NF_LOG_SYSLOG=m
CONFIG_NETFILTER_CONNCOUNT=m
CONFIG_NF_CONNTRACK_MARK=y
CONFIG_NF_CONNTRACK_ZONES=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_TIMEOUT=y
CONFIG_NF_CONNTRACK_TIMESTAMP=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CONNTRACK_OVS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_CT_NETLINK_TIMEOUT=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=m
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NF_NAT_OVS=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=m
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
CONFIG_NFT_OSF=m
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NF_DUP_NETDEV=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NFT_REJECT_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
# CONFIG_NF_FLOW_TABLE_PROCFS is not set
CONFIG_NETFILTER_XTABLES=y
CONFIG_NETFILTER_XTABLES_COMPAT=y

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=m
CONFIG_NETFILTER_XT_CONNMARK=m
CONFIG_NETFILTER_XT_SET=m

#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_AUDIT=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LED=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=m
CONFIG_NETFILTER_XT_TARGET_NETMAP=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
CONFIG_NETFILTER_XT_TARGET_RATEEST=m
CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=m
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# end of Core Netfilter Configuration

CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
# CONFIG_IP_VS_DEBUG is not set
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m
# CONFIG_IP_VS_TWOS is not set

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=m
CONFIG_NF_SOCKET_IPV4=m
CONFIG_NF_TPROXY_IPV4=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=y
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_SECURITY=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP6_NF_SECURITY=m
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=m
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_NFT_BRIDGE_META=m
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
CONFIG_BPFILTER=y
CONFIG_BPFILTER_UMH=m
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m

#
# DCCP CCIDs Configuration
#
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
CONFIG_IP_DCCP_CCID3=y
# CONFIG_IP_DCCP_CCID3_DEBUG is not set
CONFIG_IP_DCCP_TFRC_LIB=y
# end of DCCP CCIDs Configuration

#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
# end of DCCP Kernel Hacking

CONFIG_IP_SCTP=m
# CONFIG_SCTP_DBG_OBJCNT is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5 is not set
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=m
CONFIG_RDS=m
CONFIG_RDS_TCP=m
# CONFIG_RDS_DEBUG is not set
CONFIG_TIPC=m
CONFIG_TIPC_MEDIA_UDP=y
CONFIG_TIPC_CRYPTO=y
CONFIG_TIPC_DIAG=m
CONFIG_ATM=m
CONFIG_ATM_CLIP=m
# CONFIG_ATM_CLIP_NO_ICMP is not set
CONFIG_ATM_LANE=m
# CONFIG_ATM_MPOA is not set
CONFIG_ATM_BR2684=m
# CONFIG_ATM_BR2684_IPFILTER is not set
CONFIG_L2TP=m
CONFIG_L2TP_DEBUGFS=m
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=m
CONFIG_L2TP_ETH=m
CONFIG_STP=m
CONFIG_GARP=m
CONFIG_MRP=m
CONFIG_BRIDGE=m
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
# CONFIG_BRIDGE_MRP is not set
# CONFIG_BRIDGE_CFM is not set
CONFIG_NET_DSA=m
CONFIG_NET_DSA_TAG_NONE=m
# CONFIG_NET_DSA_TAG_AR9331 is not set
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
CONFIG_NET_DSA_TAG_BRCM=m
CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
# CONFIG_NET_DSA_TAG_HELLCREEK is not set
# CONFIG_NET_DSA_TAG_GSWIP is not set
CONFIG_NET_DSA_TAG_DSA_COMMON=m
CONFIG_NET_DSA_TAG_DSA=m
CONFIG_NET_DSA_TAG_EDSA=m
# CONFIG_NET_DSA_TAG_MTK is not set
# CONFIG_NET_DSA_TAG_KSZ is not set
# CONFIG_NET_DSA_TAG_OCELOT is not set
# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set
CONFIG_NET_DSA_TAG_QCA=m
# CONFIG_NET_DSA_TAG_RTL4_A is not set
# CONFIG_NET_DSA_TAG_RTL8_4 is not set
# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set
# CONFIG_NET_DSA_TAG_LAN9303 is not set
# CONFIG_NET_DSA_TAG_SJA1105 is not set
CONFIG_NET_DSA_TAG_TRAILER=m
# CONFIG_NET_DSA_TAG_XRS700X is not set
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q_MVRP=y
CONFIG_LLC=m
# CONFIG_LLC2 is not set
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
CONFIG_6LOWPAN=m
# CONFIG_6LOWPAN_DEBUGFS is not set
CONFIG_6LOWPAN_NHC=m
CONFIG_6LOWPAN_NHC_DEST=m
CONFIG_6LOWPAN_NHC_FRAGMENT=m
CONFIG_6LOWPAN_NHC_HOP=m
CONFIG_6LOWPAN_NHC_IPV6=m
CONFIG_6LOWPAN_NHC_MOBILITY=m
CONFIG_6LOWPAN_NHC_ROUTING=m
CONFIG_6LOWPAN_NHC_UDP=m
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
CONFIG_6LOWPAN_GHC_UDP=m
CONFIG_6LOWPAN_GHC_ICMPV6=m
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
CONFIG_IEEE802154=m
# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set
CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_MAC802154=m
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFB=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_MQPRIO_LIB=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_SKBPRIO=m
CONFIG_NET_SCH_CHOKE=m
CONFIG_NET_SCH_QFQ=m
CONFIG_NET_SCH_CODEL=m
CONFIG_NET_SCH_FQ_CODEL=y
CONFIG_NET_SCH_CAKE=m
CONFIG_NET_SCH_FQ=m
CONFIG_NET_SCH_HHF=m
CONFIG_NET_SCH_PIE=m
CONFIG_NET_SCH_FQ_PIE=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_SCH_PLUG=m
CONFIG_NET_SCH_ETS=m
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_PERF=y
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=y
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_EMATCH_CANID=m
CONFIG_NET_EMATCH_IPSET=m
CONFIG_NET_EMATCH_IPT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_SAMPLE=m
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
# CONFIG_NET_ACT_MPLS is not set
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_NET_ACT_CONNMARK=m
CONFIG_NET_ACT_CTINFO=m
CONFIG_NET_ACT_SKBMOD=m
CONFIG_NET_ACT_IFE=m
CONFIG_NET_ACT_TUNNEL_KEY=m
CONFIG_NET_ACT_CT=m
CONFIG_NET_ACT_GATE=m
CONFIG_NET_IFE_SKBMARK=m
CONFIG_NET_IFE_SKBPRIO=m
CONFIG_NET_IFE_SKBTCINDEX=m
# CONFIG_NET_TC_SKB_EXT is not set
CONFIG_NET_SCH_FIFO=y
CONFIG_DCB=y
CONFIG_DNS_RESOLVER=y
CONFIG_BATMAN_ADV=m
# CONFIG_BATMAN_ADV_BATMAN_V is not set
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
CONFIG_BATMAN_ADV_NC=y
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUG is not set
CONFIG_OPENVSWITCH=m
CONFIG_OPENVSWITCH_GRE=m
CONFIG_OPENVSWITCH_VXLAN=m
CONFIG_OPENVSWITCH_GENEVE=m
CONFIG_VSOCKETS=m
CONFIG_VSOCKETS_DIAG=m
CONFIG_VSOCKETS_LOOPBACK=m
CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO_VSOCKETS_COMMON=m
CONFIG_NETLINK_DIAG=m
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=m
CONFIG_MPLS_ROUTING=m
# CONFIG_MPLS_IPTUNNEL is not set
CONFIG_NET_NSH=m
# CONFIG_HSR is not set
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=m
CONFIG_QRTR_SMD=m
CONFIG_QRTR_TUN=m
# CONFIG_NET_NCSI is not set
CONFIG_PCPU_DEV_REFCNT=y
CONFIG_MAX_SKB_FRAGS=17
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_XPS=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
CONFIG_NET_PKTGEN=m
# end of Network testing
# end of Networking options

CONFIG_HAMRADIO=y

#
# Packet Radio protocols
#
CONFIG_AX25=m
CONFIG_AX25_DAMA_SLAVE=y
CONFIG_NETROM=m
CONFIG_ROSE=m

#
# AX.25 network device drivers
#
CONFIG_MKISS=m
CONFIG_6PACK=m
CONFIG_BPQETHER=m
CONFIG_BAYCOM_SER_FDX=m
CONFIG_BAYCOM_SER_HDX=m
CONFIG_YAM=m
# end of AX.25 network device drivers

CONFIG_CAN=m
CONFIG_CAN_RAW=m
CONFIG_CAN_BCM=m
CONFIG_CAN_GW=m
# CONFIG_CAN_J1939 is not set
# CONFIG_CAN_ISOTP is not set
CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
# CONFIG_BT_HIDP is not set
CONFIG_BT_HS=y
CONFIG_BT_LE=y
CONFIG_BT_LE_L2CAP_ECRED=y
CONFIG_BT_6LOWPAN=m
# CONFIG_BT_LEDS is not set
# CONFIG_BT_MSFTEXT is not set
# CONFIG_BT_AOSPEXT is not set
# CONFIG_BT_DEBUGFS is not set
# CONFIG_BT_SELFTEST is not set

#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=m
CONFIG_BT_BCM=m
CONFIG_BT_RTL=m
CONFIG_BT_QCA=m
CONFIG_BT_HCIBTUSB=m
# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
CONFIG_BT_HCIBTUSB_POLL_SYNC=y
CONFIG_BT_HCIBTUSB_BCM=y
# CONFIG_BT_HCIBTUSB_MTK is not set
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
# CONFIG_BT_HCIUART_NOKIA is not set
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_BCM=y
# CONFIG_BT_HCIUART_RTL is not set
CONFIG_BT_HCIUART_QCA=y
# CONFIG_BT_HCIUART_AG6XX is not set
CONFIG_BT_HCIUART_MRVL=y
CONFIG_BT_HCIBCM203X=m
# CONFIG_BT_HCIBCM4377 is not set
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
# CONFIG_BT_MTKSDIO is not set
# CONFIG_BT_MTKUART is not set
CONFIG_BT_HCIRSI=m
# CONFIG_BT_VIRTIO is not set
# CONFIG_BT_NXPUART is not set
# end of Bluetooth device drivers

# CONFIG_AF_RXRPC is not set
# CONFIG_AF_KCM is not set
CONFIG_STREAM_PARSER=y
# CONFIG_MCTP is not set
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_SPY=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_DEFAULT_PS=y
CONFIG_CFG80211_DEBUGFS=y
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_CFG80211_WEXT_EXPORT=y
CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
CONFIG_LIB80211_CRYPT_TKIP=m
# CONFIG_LIB80211_DEBUG is not set
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
CONFIG_MAC80211_DEBUGFS=y
# CONFIG_MAC80211_MESSAGE_TRACING is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_RFKILL=m
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=m
CONFIG_NET_9P=m
CONFIG_NET_9P_FD=m
CONFIG_NET_9P_VIRTIO=m
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
CONFIG_CEPH_LIB=m
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
CONFIG_NFC=m
CONFIG_NFC_DIGITAL=m
CONFIG_NFC_NCI=m
# CONFIG_NFC_NCI_SPI is not set
# CONFIG_NFC_NCI_UART is not set
CONFIG_NFC_HCI=m
CONFIG_NFC_SHDLC=y

#
# Near Field Communication (NFC) devices
#
# CONFIG_NFC_TRF7970A is not set
CONFIG_NFC_SIM=m
CONFIG_NFC_PORT100=m
# CONFIG_NFC_VIRTUAL_NCI is not set
# CONFIG_NFC_FDP is not set
CONFIG_NFC_PN544=m
CONFIG_NFC_PN544_I2C=m
# CONFIG_NFC_PN533_USB is not set
# CONFIG_NFC_PN533_I2C is not set
# CONFIG_NFC_PN532_UART is not set
CONFIG_NFC_MICROREAD=m
CONFIG_NFC_MICROREAD_I2C=m
CONFIG_NFC_MRVL=m
CONFIG_NFC_MRVL_USB=m
# CONFIG_NFC_MRVL_I2C is not set
CONFIG_NFC_ST21NFCA=m
CONFIG_NFC_ST21NFCA_I2C=m
# CONFIG_NFC_ST_NCI_I2C is not set
# CONFIG_NFC_ST_NCI_SPI is not set
# CONFIG_NFC_NXP_NCI is not set
CONFIG_NFC_S3FWRN5=m
CONFIG_NFC_S3FWRN5_I2C=m
# CONFIG_NFC_S3FWRN82_UART is not set
# CONFIG_NFC_ST95HF is not set
# end of Near Field Communication (NFC) devices

CONFIG_PSAMPLE=m
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_FAILOVER=m
CONFIG_ETHTOOL_NETLINK=y

#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
CONFIG_PCIEPORTBUS=y
CONFIG_HOTPLUG_PCI_PCIE=y
CONFIG_PCIEAER=y
CONFIG_PCIEAER_INJECT=m
CONFIG_PCIE_ECRC=y
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
# CONFIG_PCIEASPM_PERFORMANCE is not set
CONFIG_PCIE_PME=y
# CONFIG_PCIE_DPC is not set
# CONFIG_PCIE_PTM is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
CONFIG_PCI_STUB=y
# CONFIG_PCI_PF_STUB is not set
CONFIG_PCI_ATS=y
CONFIG_PCI_ECAM=y
CONFIG_PCI_IOV=y
CONFIG_PCI_PRI=y
CONFIG_PCI_PASID=y
CONFIG_PCI_LABEL=y
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
CONFIG_HOTPLUG_PCI=y
CONFIG_HOTPLUG_PCI_ACPI=y
# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
# CONFIG_HOTPLUG_PCI_CPCI is not set
# CONFIG_HOTPLUG_PCI_SHPC is not set

#
# PCI controller drivers
#
# CONFIG_PCIE_ALTERA is not set
# CONFIG_PCI_HOST_THUNDER_PEM is not set
# CONFIG_PCI_HOST_THUNDER_ECAM is not set
# CONFIG_PCI_FTPCI100 is not set
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
# CONFIG_PCIE_MICROCHIP_HOST is not set
CONFIG_PCI_XGENE=y
CONFIG_PCI_XGENE_MSI=y
# CONFIG_PCIE_XILINX is not set

#
# Cadence-based PCIe controllers
#
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCI_J721E_HOST is not set
# end of Cadence-based PCIe controllers

#
# DesignWare-based PCIe controllers
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
# CONFIG_PCIE_AL is not set
CONFIG_PCI_MESON=y
CONFIG_PCI_HISI=y
# CONFIG_PCIE_KIRIN is not set
CONFIG_PCIE_DW_PLAT=y
CONFIG_PCIE_DW_PLAT_HOST=y
# end of DesignWare-based PCIe controllers

#
# Mobiveil-based PCIe controllers
#
# end of Mobiveil-based PCIe controllers
# end of PCI controller drivers

#
# PCI Endpoint
#
# CONFIG_PCI_ENDPOINT is not set
# end of PCI Endpoint

#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set
# end of PCI switch controller drivers

# CONFIG_CXL_BUS is not set
# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
CONFIG_AUXILIARY_BUS=y
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_DEVTMPFS_SAFE is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_DEBUG=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_FW_LOADER_USER_HELPER is not set
# CONFIG_FW_LOADER_COMPRESS is not set
CONFIG_FW_CACHE=y
# CONFIG_FW_UPLOAD is not set
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
CONFIG_DEBUG_DEVRES=y
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SLIMBUS=m
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_SPMI=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SOUNDWIRE=m
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
# CONFIG_BRCMSTB_GISB_ARB is not set
# CONFIG_MOXTET is not set
CONFIG_SUN50I_DE2_BUS=y
CONFIG_SUNXI_RSB=y
CONFIG_VEXPRESS_CONFIG=y
# CONFIG_MHI_BUS is not set
# CONFIG_MHI_BUS_EP is not set
# end of Bus devices

CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y

#
# Firmware Drivers
#

#
# ARM System Control and Management Interface Protocol
#
CONFIG_ARM_SCMI_PROTOCOL=y
# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
CONFIG_ARM_SCMI_HAVE_SHMEM=y
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set
CONFIG_ARM_SCMI_POWER_DOMAIN=y
# CONFIG_ARM_SCMI_POWER_CONTROL is not set
# end of ARM System Control and Management Interface Protocol

CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
# CONFIG_FIRMWARE_MEMMAP is not set
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=y
# CONFIG_ISCSI_IBFT is not set
# CONFIG_FW_CFG_SYSFS is not set
CONFIG_SYSFB=y
# CONFIG_SYSFB_SIMPLEFB is not set
CONFIG_ARM_FFA_TRANSPORT=m
CONFIG_ARM_FFA_SMCCC=y
# CONFIG_GOOGLE_FIRMWARE is not set

#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_VARS_PSTORE=y
CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_GENERIC_STUB=y
# CONFIG_EFI_ZBOOT is not set
# CONFIG_EFI_ARMSTUB_DTB_LOADER is not set
CONFIG_EFI_BOOTLOADER_CONTROL=y
# CONFIG_EFI_CAPSULE_LOADER is not set
# CONFIG_EFI_TEST is not set
# CONFIG_RESET_ATTACK_MITIGATION is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
# CONFIG_EFI_DISABLE_RUNTIME is not set
# CONFIG_EFI_COCO_SECRET is not set
# end of EFI (Extensible Firmware Interface) Support

CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_PSCI_CHECKER is not set
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_ARM_SMCCC_SOC_ID=y

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_GNSS=m
CONFIG_GNSS_SERIAL=m
CONFIG_GNSS_MTK_SERIAL=m
# CONFIG_GNSS_SIRF_SERIAL is not set
# CONFIG_GNSS_UBX_SERIAL is not set
# CONFIG_GNSS_USB is not set
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_OF_PARTS=m
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=m
CONFIG_MTD_BLOCK=m
# CONFIG_MTD_BLOCK_RO is not set

#
# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
#
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=m
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=m
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
CONFIG_MTD_CFI_INTELEXT=m
CONFIG_MTD_CFI_AMDSTD=m
CONFIG_MTD_CFI_STAA=m
CONFIG_MTD_CFI_UTIL=m
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=m
# CONFIG_MTD_PHYSMAP_COMPAT is not set
CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_PHYSMAP_VERSATILE is not set
# CONFIG_MTD_PHYSMAP_GEMINI is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_MCHP48L640 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
CONFIG_MTD_NAND_CORE=y
# CONFIG_MTD_ONENAND is not set
CONFIG_MTD_RAW_NAND=y

#
# Raw/parallel NAND flash controllers
#
# CONFIG_MTD_NAND_DENALI_PCI is not set
# CONFIG_MTD_NAND_DENALI_DT is not set
# CONFIG_MTD_NAND_CAFE is not set
# CONFIG_MTD_NAND_BRCMNAND is not set
# CONFIG_MTD_NAND_SUNXI is not set
# CONFIG_MTD_NAND_MXIC is not set
# CONFIG_MTD_NAND_GPIO is not set
# CONFIG_MTD_NAND_PLATFORM is not set
# CONFIG_MTD_NAND_CADENCE is not set
# CONFIG_MTD_NAND_ARASAN is not set
# CONFIG_MTD_NAND_INTEL_LGM is not set

#
# Misc
#
# CONFIG_MTD_NAND_NANDSIM is not set
# CONFIG_MTD_NAND_RICOH is not set
# CONFIG_MTD_NAND_DISKONCHIP is not set
# CONFIG_MTD_SPI_NAND is not set

#
# ECC engine support
#
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
CONFIG_MTD_NAND_ECC_SW_BCH=y
# CONFIG_MTD_NAND_ECC_MXIC is not set
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
# CONFIG_MTD_UBI_BLOCK is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_NULL_BLK=m
CONFIG_CDROM=y
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
CONFIG_ZRAM=m
CONFIG_ZRAM_DEF_COMP_LZORLE=y
# CONFIG_ZRAM_DEF_COMP_ZSTD is not set
# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
# CONFIG_ZRAM_DEF_COMP_LZO is not set
# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
# CONFIG_ZRAM_DEF_COMP_842 is not set
CONFIG_ZRAM_DEF_COMP="lzo-rle"
# CONFIG_ZRAM_WRITEBACK is not set
# CONFIG_ZRAM_MEMORY_TRACKING is not set
# CONFIG_ZRAM_MULTI_COMP is not set
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_LOOP_MIN_COUNT=0
CONFIG_BLK_DEV_DRBD=m
# CONFIG_DRBD_FAULT_INJECTION is not set
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=m
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_CDROM_PKTCDVD=m
CONFIG_CDROM_PKTCDVD_BUFFERS=8
# CONFIG_CDROM_PKTCDVD_WCACHE is not set
CONFIG_ATA_OVER_ETH=m
CONFIG_VIRTIO_BLK=y
CONFIG_BLK_DEV_RBD=m
# CONFIG_BLK_DEV_UBLK is not set

#
# NVME Support
#
CONFIG_NVME_CORE=m
CONFIG_BLK_DEV_NVME=m
CONFIG_NVME_MULTIPATH=y
# CONFIG_NVME_VERBOSE_ERRORS is not set
# CONFIG_NVME_HWMON is not set
# CONFIG_NVME_FC is not set
# CONFIG_NVME_TCP is not set
# CONFIG_NVME_AUTH is not set
# CONFIG_NVME_TARGET is not set
# end of NVME Support

#
# Misc devices
#
CONFIG_SENSORS_LIS3LV02D=m
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
CONFIG_TIFM_CORE=y
CONFIG_TIFM_7XX1=m
# CONFIG_ICS932S401 is not set
CONFIG_ENCLOSURE_SERVICES=m
# CONFIG_HI6421V600_IRQ is not set
# CONFIG_HP_ILO is not set
CONFIG_APDS9802ALS=m
CONFIG_ISL29003=m
CONFIG_ISL29020=m
CONFIG_SENSORS_TSL2550=m
CONFIG_SENSORS_BH1770=m
CONFIG_SENSORS_APDS990X=m
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
# CONFIG_DW_XDATA_PCIE is not set
CONFIG_PCI_ENDPOINT_TEST=m
# CONFIG_XILINX_SDFEC is not set
# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_OPEN_DICE is not set
# CONFIG_VCPU_STALL_DETECTOR is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
CONFIG_EEPROM_AT24=m
# CONFIG_EEPROM_AT25 is not set
CONFIG_EEPROM_LEGACY=m
CONFIG_EEPROM_MAX6875=m
CONFIG_EEPROM_93CX6=m
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

CONFIG_CB710_CORE=y
# CONFIG_CB710_DEBUG is not set
CONFIG_CB710_DEBUG_ASSUMPTIONS=y

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline

CONFIG_SENSORS_LIS3_I2C=m
CONFIG_ALTERA_STAPL=m
# CONFIG_VMWARE_VMCI is not set
# CONFIG_GENWQE is not set
CONFIG_ECHO=m
# CONFIG_BCM_VK is not set
# CONFIG_MISC_ALCOR_PCI is not set
# CONFIG_MISC_RTSX_PCI is not set
# CONFIG_MISC_RTSX_USB is not set
CONFIG_UACCE=m
# CONFIG_PVPANIC is not set
# CONFIG_GP_PCI1XXXX is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
CONFIG_RAID_ATTRS=m
CONFIG_SCSI_COMMON=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_NETLINK=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=m
CONFIG_BLK_DEV_SR=y
CONFIG_CHR_DEV_SG=y
CONFIG_BLK_DEV_BSG=y
CONFIG_CHR_DEV_SCH=m
CONFIG_SCSI_ENCLOSURE=m
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y

#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=m
CONFIG_SCSI_FC_ATTRS=m
CONFIG_SCSI_ISCSI_ATTRS=m
CONFIG_SCSI_SAS_ATTRS=m
CONFIG_SCSI_SAS_LIBSAS=m
CONFIG_SCSI_SAS_ATA=y
CONFIG_SCSI_SAS_HOST_SMP=y
CONFIG_SCSI_SRP_ATTRS=m
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_ISCSI_BOOT_SYSFS=m
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
CONFIG_SCSI_BNX2_ISCSI=m
CONFIG_SCSI_BNX2X_FCOE=m
CONFIG_BE2ISCSI=m
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
CONFIG_SCSI_HPSA=m
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
CONFIG_SCSI_MVSAS=m
# CONFIG_SCSI_MVSAS_DEBUG is not set
CONFIG_SCSI_MVSAS_TASKLET=y
CONFIG_SCSI_MVUMI=m
# CONFIG_SCSI_ADVANSYS is not set
CONFIG_SCSI_ARCMSR=m
CONFIG_SCSI_ESAS2R=m
CONFIG_MEGARAID_NEWGEN=y
CONFIG_MEGARAID_MM=m
CONFIG_MEGARAID_MAILBOX=m
CONFIG_MEGARAID_LEGACY=m
CONFIG_MEGARAID_SAS=m
CONFIG_SCSI_MPT3SAS=m
CONFIG_SCSI_MPT2SAS_MAX_SGE=128
CONFIG_SCSI_MPT3SAS_MAX_SGE=128
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_MPI3MR is not set
# CONFIG_SCSI_SMARTPQI is not set
CONFIG_SCSI_HPTIOP=m
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
CONFIG_LIBFC=m
CONFIG_LIBFCOE=m
CONFIG_FCOE=m
CONFIG_SCSI_SNIC=m
# CONFIG_SCSI_SNIC_DEBUG_FS is not set
CONFIG_SCSI_DMX3191D=m
# CONFIG_SCSI_FDOMAIN_PCI is not set
# CONFIG_SCSI_IPS is not set
CONFIG_SCSI_INITIO=m
CONFIG_SCSI_INIA100=m
CONFIG_SCSI_STEX=m
CONFIG_SCSI_SYM53C8XX_2=m
CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
CONFIG_SCSI_SYM53C8XX_MMIO=y
CONFIG_SCSI_IPR=m
CONFIG_SCSI_IPR_TRACE=y
CONFIG_SCSI_IPR_DUMP=y
CONFIG_SCSI_QLOGIC_1280=m
CONFIG_SCSI_QLA_FC=m
CONFIG_TCM_QLA2XXX=m
# CONFIG_TCM_QLA2XXX_DEBUG is not set
CONFIG_SCSI_QLA_ISCSI=m
# CONFIG_SCSI_LPFC is not set
# CONFIG_SCSI_EFCT is not set
CONFIG_SCSI_DC395x=m
CONFIG_SCSI_AM53C974=m
CONFIG_SCSI_WD719X=m
CONFIG_SCSI_DEBUG=m
CONFIG_SCSI_PMCRAID=m
# CONFIG_SCSI_PM8001 is not set
# CONFIG_SCSI_BFA_FC is not set
CONFIG_SCSI_VIRTIO=y
CONFIG_SCSI_CHELSIO_FCOE=m
CONFIG_SCSI_DH=y
CONFIG_SCSI_DH_RDAC=m
CONFIG_SCSI_DH_HP_SW=m
CONFIG_SCSI_DH_EMC=m
CONFIG_SCSI_DH_ALUA=m
# end of SCSI device support

CONFIG_ATA=y
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=y
# CONFIG_AHCI_DWC is not set
# CONFIG_AHCI_CEVA is not set
CONFIG_AHCI_SUNXI=y
CONFIG_SATA_INIC162X=m
CONFIG_SATA_ACARD_AHCI=m
CONFIG_SATA_SIL24=y
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#
CONFIG_PDC_ADMA=m
CONFIG_SATA_QSTOR=m
CONFIG_SATA_SX4=m
CONFIG_ATA_BMDMA=y

#
# SATA SFF controllers with BMDMA
#
CONFIG_ATA_PIIX=y
# CONFIG_SATA_DWC is not set
CONFIG_SATA_MV=m
CONFIG_SATA_NV=m
CONFIG_SATA_PROMISE=m
CONFIG_SATA_SIL=m
CONFIG_SATA_SIS=m
CONFIG_SATA_SVW=m
CONFIG_SATA_ULI=m
CONFIG_SATA_VIA=m
CONFIG_SATA_VITESSE=m

#
# PATA SFF controllers with BMDMA
#
CONFIG_PATA_ALI=m
CONFIG_PATA_AMD=m
CONFIG_PATA_ARTOP=m
CONFIG_PATA_ATIIXP=m
CONFIG_PATA_ATP867X=m
CONFIG_PATA_CMD64X=m
CONFIG_PATA_CYPRESS=m
CONFIG_PATA_EFAR=m
CONFIG_PATA_HPT366=m
CONFIG_PATA_HPT37X=m
CONFIG_PATA_HPT3X2N=m
CONFIG_PATA_HPT3X3=m
# CONFIG_PATA_HPT3X3_DMA is not set
CONFIG_PATA_IT8213=m
CONFIG_PATA_IT821X=m
CONFIG_PATA_JMICRON=m
CONFIG_PATA_MARVELL=m
CONFIG_PATA_NETCELL=m
CONFIG_PATA_NINJA32=m
CONFIG_PATA_NS87415=m
CONFIG_PATA_OLDPIIX=m
CONFIG_PATA_OPTIDMA=m
CONFIG_PATA_PDC2027X=m
CONFIG_PATA_PDC_OLD=m
# CONFIG_PATA_RADISYS is not set
CONFIG_PATA_RDC=m
CONFIG_PATA_SCH=m
CONFIG_PATA_SERVERWORKS=m
CONFIG_PATA_SIL680=m
CONFIG_PATA_SIS=m
CONFIG_PATA_TOSHIBA=m
CONFIG_PATA_TRIFLEX=m
CONFIG_PATA_VIA=m
CONFIG_PATA_WINBOND=m

#
# PIO-only SFF controllers
#
CONFIG_PATA_CMD640_PCI=m
CONFIG_PATA_MPIIX=m
CONFIG_PATA_NS87410=m
CONFIG_PATA_OPTI=m
CONFIG_PATA_PLATFORM=y
CONFIG_PATA_OF_PLATFORM=y
# CONFIG_PATA_RZ1000 is not set

#
# Generic fallback / legacy drivers
#
# CONFIG_PATA_ACPI is not set
CONFIG_ATA_GENERIC=m
# CONFIG_PATA_LEGACY is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=y
CONFIG_MD_AUTODETECT=y
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
CONFIG_MD_CLUSTER=m
CONFIG_BCACHE=m
# CONFIG_BCACHE_DEBUG is not set
# CONFIG_BCACHE_CLOSURES_DEBUG is not set
# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_DEBUG=y
CONFIG_DM_BUFIO=y
# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
# CONFIG_DM_UNSTRIPED is not set
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=y
CONFIG_DM_THIN_PROVISIONING=m
CONFIG_DM_CACHE=m
CONFIG_DM_CACHE_SMQ=m
CONFIG_DM_WRITECACHE=m
# CONFIG_DM_EBS is not set
# CONFIG_DM_ERA is not set
# CONFIG_DM_CLONE is not set
CONFIG_DM_MIRROR=y
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=y
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
# CONFIG_DM_MULTIPATH_HST is not set
# CONFIG_DM_MULTIPATH_IOA is not set
CONFIG_DM_DELAY=m
CONFIG_DM_DUST=m
CONFIG_DM_INIT=y
CONFIG_DM_UEVENT=y
CONFIG_DM_FLAKEY=m
CONFIG_DM_VERITY=m
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
CONFIG_DM_VERITY_FEC=y
CONFIG_DM_SWITCH=m
CONFIG_DM_LOG_WRITES=m
CONFIG_DM_INTEGRITY=m
CONFIG_DM_ZONED=m
CONFIG_DM_AUDIT=y
CONFIG_TARGET_CORE=m
CONFIG_TCM_IBLOCK=m
CONFIG_TCM_FILEIO=m
CONFIG_TCM_PSCSI=m
CONFIG_TCM_USER2=m
CONFIG_LOOPBACK_TARGET=m
CONFIG_TCM_FC=m
CONFIG_ISCSI_TARGET=m
# CONFIG_REMOTE_TARGET is not set
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
CONFIG_FIREWIRE_NOSY=m
# end of IEEE 1394 (FireWire) support

CONFIG_NETDEVICES=y
CONFIG_MII=m
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_WIREGUARD=m
# CONFIG_WIREGUARD_DEBUG is not set
CONFIG_EQUALIZER=m
CONFIG_NET_FC=y
CONFIG_IFB=m
CONFIG_NET_TEAM=m
CONFIG_NET_TEAM_MODE_BROADCAST=m
CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
CONFIG_NET_TEAM_MODE_RANDOM=m
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
CONFIG_NET_TEAM_MODE_LOADBALANCE=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=m
CONFIG_IPVTAP=m
CONFIG_VXLAN=m
CONFIG_GENEVE=m
# CONFIG_BAREUDP is not set
# CONFIG_GTP is not set
# CONFIG_AMT is not set
# CONFIG_MACSEC is not set
CONFIG_NETCONSOLE=m
CONFIG_NETCONSOLE_DYNAMIC=y
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=m
CONFIG_TAP=m
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_NLMON=m
CONFIG_NET_VRF=m
# CONFIG_VSOCKMON is not set
# CONFIG_ARCNET is not set
# CONFIG_ATM_DRIVERS is not set

#
# Distributed Switch Architecture drivers
#
CONFIG_B53=m
# CONFIG_B53_SPI_DRIVER is not set
# CONFIG_B53_MDIO_DRIVER is not set
# CONFIG_B53_MMAP_DRIVER is not set
# CONFIG_B53_SRAB_DRIVER is not set
# CONFIG_B53_SERDES is not set
CONFIG_NET_DSA_BCM_SF2=m
# CONFIG_NET_DSA_LOOP is not set
# CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK is not set
# CONFIG_NET_DSA_LANTIQ_GSWIP is not set
# CONFIG_NET_DSA_MT7530 is not set
CONFIG_NET_DSA_MV88E6060=m
# CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON is not set
CONFIG_NET_DSA_MV88E6XXX=m
CONFIG_NET_DSA_MV88E6XXX_PTP=y
# CONFIG_NET_DSA_MSCC_OCELOT_EXT is not set
# CONFIG_NET_DSA_MSCC_SEVILLE is not set
# CONFIG_NET_DSA_AR9331 is not set
CONFIG_NET_DSA_QCA8K=m
# CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT is not set
# CONFIG_NET_DSA_SJA1105 is not set
# CONFIG_NET_DSA_XRS700X_I2C is not set
# CONFIG_NET_DSA_XRS700X_MDIO is not set
# CONFIG_NET_DSA_REALTEK is not set
# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set
# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set
# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set
# end of Distributed Switch Architecture drivers

CONFIG_ETHERNET=y
CONFIG_MDIO=m
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
CONFIG_NET_VENDOR_AGERE=y
CONFIG_ET131X=m
CONFIG_NET_VENDOR_ALACRITECH=y
# CONFIG_SLICOSS is not set
CONFIG_NET_VENDOR_ALLWINNER=y
# CONFIG_SUN4I_EMAC is not set
CONFIG_NET_VENDOR_ALTEON=y
CONFIG_ACENIC=m
# CONFIG_ACENIC_OMIT_TIGON_I is not set
CONFIG_ALTERA_TSE=m
CONFIG_NET_VENDOR_AMAZON=y
# CONFIG_ENA_ETHERNET is not set
CONFIG_NET_VENDOR_AMD=y
CONFIG_AMD8111_ETH=m
CONFIG_PCNET32=m
CONFIG_AMD_XGBE=m
# CONFIG_AMD_XGBE_DCB is not set
# CONFIG_PDS_CORE is not set
CONFIG_NET_VENDOR_AQUANTIA=y
CONFIG_AQTION=m
CONFIG_NET_VENDOR_ARC=y
CONFIG_NET_VENDOR_ASIX=y
# CONFIG_SPI_AX88796C is not set
CONFIG_NET_VENDOR_ATHEROS=y
CONFIG_ATL2=m
CONFIG_ATL1=m
CONFIG_ATL1E=m
CONFIG_ATL1C=m
CONFIG_ALX=m
CONFIG_NET_VENDOR_BROADCOM=y
CONFIG_B44=m
CONFIG_B44_PCI_AUTOSELECT=y
CONFIG_B44_PCICORE_AUTOSELECT=y
CONFIG_B44_PCI=y
CONFIG_BCMGENET=m
CONFIG_BNX2=m
CONFIG_CNIC=m
CONFIG_TIGON3=m
CONFIG_TIGON3_HWMON=y
CONFIG_BNX2X=m
CONFIG_BNX2X_SRIOV=y
# CONFIG_SYSTEMPORT is not set
# CONFIG_BNXT is not set
CONFIG_NET_VENDOR_CADENCE=y
CONFIG_MACB=m
CONFIG_MACB_USE_HWSTAMP=y
# CONFIG_MACB_PCI is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
CONFIG_NET_VENDOR_CORTINA=y
# CONFIG_GEMINI_ETHERNET is not set
CONFIG_NET_VENDOR_DAVICOM=y
# CONFIG_DM9051 is not set
CONFIG_DNET=m
# CONFIG_NET_VENDOR_DEC is not set
CONFIG_NET_VENDOR_DLINK=y
CONFIG_DL2K=m
CONFIG_SUNDANCE=m
# CONFIG_SUNDANCE_MMIO is not set
# CONFIG_NET_VENDOR_EMULEX is not set
CONFIG_NET_VENDOR_ENGLEDER=y
# CONFIG_TSNEP is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
CONFIG_NET_VENDOR_FUNGIBLE=y
# CONFIG_FUN_ETH is not set
CONFIG_NET_VENDOR_GOOGLE=y
# CONFIG_GVE is not set
CONFIG_NET_VENDOR_HISILICON=y
CONFIG_HIX5HD2_GMAC=m
# CONFIG_HISI_FEMAC is not set
CONFIG_HIP04_ETH=m
# CONFIG_HI13X1_GMAC is not set
CONFIG_HNS_MDIO=m
CONFIG_HNS=m
CONFIG_HNS_DSAF=m
CONFIG_HNS_ENET=m
# CONFIG_HNS3 is not set
CONFIG_NET_VENDOR_HUAWEI=y
# CONFIG_HINIC is not set
# CONFIG_NET_VENDOR_I825XX is not set
CONFIG_NET_VENDOR_INTEL=y
CONFIG_E100=m
CONFIG_E1000=m
CONFIG_E1000E=m
CONFIG_IGB=m
CONFIG_IGB_HWMON=y
CONFIG_IGBVF=m
CONFIG_IXGBE=m
CONFIG_IXGBE_HWMON=y
CONFIG_IXGBE_DCB=y
CONFIG_IXGBEVF=m
CONFIG_I40E=m
# CONFIG_I40E_DCB is not set
CONFIG_IAVF=m
CONFIG_I40EVF=m
# CONFIG_ICE is not set
CONFIG_FM10K=m
# CONFIG_IGC is not set
CONFIG_JME=m
CONFIG_NET_VENDOR_ADI=y
# CONFIG_ADIN1110 is not set
CONFIG_NET_VENDOR_LITEX=y
# CONFIG_LITEX_LITEETH is not set
CONFIG_NET_VENDOR_MARVELL=y
CONFIG_MVMDIO=m
CONFIG_SKGE=m
# CONFIG_SKGE_DEBUG is not set
CONFIG_SKGE_GENESIS=y
CONFIG_SKY2=m
# CONFIG_SKY2_DEBUG is not set
# CONFIG_OCTEONTX2_AF is not set
# CONFIG_OCTEONTX2_PF is not set
# CONFIG_OCTEON_EP is not set
# CONFIG_PRESTERA is not set
CONFIG_NET_VENDOR_MELLANOX=y
CONFIG_MLX4_EN=m
CONFIG_MLX4_EN_DCB=y
CONFIG_MLX4_CORE=m
CONFIG_MLX4_DEBUG=y
CONFIG_MLX4_CORE_GEN2=y
CONFIG_MLX5_CORE=m
# CONFIG_MLX5_FPGA is not set
CONFIG_MLX5_CORE_EN=y
CONFIG_MLX5_EN_ARFS=y
CONFIG_MLX5_EN_RXNFC=y
CONFIG_MLX5_MPFS=y
# CONFIG_MLX5_ESWITCH is not set
# CONFIG_MLX5_CORE_EN_DCB is not set
# CONFIG_MLX5_CORE_IPOIB is not set
# CONFIG_MLX5_SF is not set
# CONFIG_MLXSW_CORE is not set
# CONFIG_MLXFW is not set
# CONFIG_MLXBF_GIGE is not set
CONFIG_NET_VENDOR_MICREL=y
# CONFIG_KS8842 is not set
# CONFIG_KS8851 is not set
# CONFIG_KS8851_MLL is not set
CONFIG_KSZ884X_PCI=m
CONFIG_NET_VENDOR_MICROCHIP=y
# CONFIG_ENC28J60 is not set
# CONFIG_ENCX24J600 is not set
# CONFIG_LAN743X is not set
# CONFIG_LAN966X_SWITCH is not set
# CONFIG_VCAP is not set
CONFIG_NET_VENDOR_MICROSEMI=y
# CONFIG_MSCC_OCELOT_SWITCH is not set
CONFIG_NET_VENDOR_MICROSOFT=y
CONFIG_NET_VENDOR_MYRI=y
CONFIG_MYRI10GE=m
CONFIG_FEALNX=m
CONFIG_NET_VENDOR_NI=y
# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
CONFIG_NET_VENDOR_NATSEMI=y
CONFIG_NATSEMI=m
CONFIG_NS83820=m
CONFIG_NET_VENDOR_NETERION=y
# CONFIG_S2IO is not set
CONFIG_NET_VENDOR_NETRONOME=y
# CONFIG_NFP is not set
CONFIG_NET_VENDOR_8390=y
CONFIG_NE2K_PCI=m
CONFIG_NET_VENDOR_NVIDIA=y
CONFIG_FORCEDETH=m
CONFIG_NET_VENDOR_OKI=y
CONFIG_ETHOC=m
CONFIG_NET_VENDOR_PACKET_ENGINES=y
CONFIG_HAMACHI=m
CONFIG_YELLOWFIN=m
CONFIG_NET_VENDOR_PENSANDO=y
# CONFIG_IONIC is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_BROCADE is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCA7000_UART is not set
# CONFIG_QCOM_EMAC is not set
CONFIG_RMNET=m
CONFIG_NET_VENDOR_RDC=y
CONFIG_R6040=m
CONFIG_NET_VENDOR_REALTEK=y
CONFIG_8139CP=m
CONFIG_8139TOO=m
# CONFIG_8139TOO_PIO is not set
# CONFIG_8139TOO_TUNE_TWISTER is not set
CONFIG_8139TOO_8129=y
# CONFIG_8139_OLD_RX_RESET is not set
CONFIG_R8169=m
# CONFIG_NET_VENDOR_RENESAS is not set
CONFIG_NET_VENDOR_ROCKER=y
CONFIG_ROCKER=m
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
CONFIG_NET_VENDOR_SILAN=y
CONFIG_SC92031=m
CONFIG_NET_VENDOR_SIS=y
CONFIG_SIS900=m
CONFIG_SIS190=m
CONFIG_NET_VENDOR_SOLARFLARE=y
# CONFIG_SFC is not set
# CONFIG_SFC_FALCON is not set
# CONFIG_SFC_SIENA is not set
CONFIG_NET_VENDOR_SMSC=y
CONFIG_SMC91X=m
CONFIG_EPIC100=m
CONFIG_SMSC911X=m
CONFIG_SMSC9420=m
CONFIG_NET_VENDOR_SOCIONEXT=y
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=m
# CONFIG_STMMAC_SELFTESTS is not set
CONFIG_STMMAC_PLATFORM=m
CONFIG_DWMAC_DWC_QOS_ETH=m
CONFIG_DWMAC_GENERIC=m
CONFIG_DWMAC_SUNXI=m
CONFIG_DWMAC_SUN8I=m
# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_DWMAC_LOONGSON is not set
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
CONFIG_NET_VENDOR_SYNOPSYS=y
# CONFIG_DWC_XLGMAC is not set
CONFIG_NET_VENDOR_TEHUTI=y
CONFIG_TEHUTI=m
CONFIG_NET_VENDOR_TI=y
# CONFIG_TI_CPSW_PHY_SEL is not set
# CONFIG_TLAN is not set
CONFIG_NET_VENDOR_VERTEXCOM=y
# CONFIG_MSE102X is not set
CONFIG_NET_VENDOR_VIA=y
CONFIG_VIA_RHINE=m
CONFIG_VIA_RHINE_MMIO=y
CONFIG_VIA_VELOCITY=m
# CONFIG_NET_VENDOR_WANGXUN is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_NET_VENDOR_XILINX=y
# CONFIG_XILINX_EMACLITE is not set
# CONFIG_XILINX_AXI_EMAC is not set
# CONFIG_XILINX_LL_TEMAC is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
CONFIG_NET_SB1000=y
CONFIG_PHYLINK=m
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_PHYLIB_LEDS=y
CONFIG_FIXED_PHY=y
CONFIG_SFP=m

#
# MII PHY device drivers
#
CONFIG_AC200_PHY=y
CONFIG_AMD_PHY=m
# CONFIG_ADIN_PHY is not set
# CONFIG_ADIN1100_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
CONFIG_AX88796B_PHY=m
CONFIG_BROADCOM_PHY=m
# CONFIG_BCM54140_PHY is not set
CONFIG_BCM7XXX_PHY=m
# CONFIG_BCM84881_PHY is not set
CONFIG_BCM87XX_PHY=m
CONFIG_BCM_NET_PHYLIB=m
CONFIG_BCM_NET_PHYPTP=m
CONFIG_CICADA_PHY=m
# CONFIG_CORTINA_PHY is not set
CONFIG_DAVICOM_PHY=m
CONFIG_ICPLUS_PHY=m
CONFIG_LXT_PHY=m
# CONFIG_INTEL_XWAY_PHY is not set
CONFIG_LSI_ET1011C_PHY=m
CONFIG_MARVELL_PHY=m
CONFIG_MARVELL_10G_PHY=m
# CONFIG_MARVELL_88X2222_PHY is not set
# CONFIG_MAXLINEAR_GPHY is not set
# CONFIG_MEDIATEK_GE_PHY is not set
CONFIG_MICREL_PHY=m
# CONFIG_MICROCHIP_T1S_PHY is not set
CONFIG_MICROCHIP_PHY=m
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
# CONFIG_MOTORCOMM_PHY is not set
CONFIG_NATIONAL_PHY=m
# CONFIG_NXP_CBTX_PHY is not set
# CONFIG_NXP_C45_TJA11XX_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
# CONFIG_NCN26000_PHY is not set
CONFIG_AT803X_PHY=y
CONFIG_QSEMI_PHY=m
CONFIG_REALTEK_PHY=m
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
CONFIG_SMSC_PHY=m
CONFIG_STE10XP=m
# CONFIG_TERANETICS_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
CONFIG_DP83848_PHY=m
CONFIG_DP83867_PHY=m
# CONFIG_DP83869_PHY is not set
# CONFIG_DP83TD510_PHY is not set
CONFIG_VITESSE_PHY=m
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_PSE_CONTROLLER is not set
CONFIG_CAN_DEV=m
CONFIG_CAN_VCAN=m
CONFIG_CAN_VXCAN=m
# CONFIG_CAN_NETLINK is not set
# CONFIG_CAN_DEBUG_DEVICES is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_FWNODE_MDIO=y
CONFIG_OF_MDIO=y
CONFIG_ACPI_MDIO=y
CONFIG_MDIO_DEVRES=y
# CONFIG_MDIO_SUN4I is not set
CONFIG_MDIO_BITBANG=m
CONFIG_MDIO_BCM_UNIMAC=y
# CONFIG_MDIO_GPIO is not set
# CONFIG_MDIO_HISI_FEMAC is not set
CONFIG_MDIO_I2C=m
# CONFIG_MDIO_MVUSB is not set
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_OCTEON is not set
# CONFIG_MDIO_IPQ4019 is not set
# CONFIG_MDIO_IPQ8064 is not set
# CONFIG_MDIO_THUNDER is not set

#
# MDIO Multiplexers
#
CONFIG_MDIO_BUS_MUX=m
CONFIG_MDIO_BUS_MUX_GPIO=m
# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
CONFIG_MDIO_BUS_MUX_MMIOREG=m

#
# PCS device drivers
#
CONFIG_PCS_XPCS=m
CONFIG_PCS_ALTERA_TSE=m
# end of PCS device drivers

CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOATM=m
CONFIG_PPPOE=m
CONFIG_PPTP=m
CONFIG_PPPOL2TP=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_SLIP=m
CONFIG_SLHC=m
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_SMART=y
# CONFIG_SLIP_MODE_SLIP6 is not set
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_AX8817X=m
CONFIG_USB_NET_AX88179_178A=m
CONFIG_USB_NET_CDCETHER=m
CONFIG_USB_NET_CDC_EEM=m
CONFIG_USB_NET_CDC_NCM=m
CONFIG_USB_NET_HUAWEI_CDC_NCM=m
CONFIG_USB_NET_CDC_MBIM=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9700=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
CONFIG_USB_NET_CDC_SUBSET=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
CONFIG_USB_EPSON2888=y
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=m
CONFIG_USB_NET_CX82310_ETH=m
CONFIG_USB_NET_KALMIA=m
CONFIG_USB_NET_QMI_WWAN=m
CONFIG_USB_HSO=m
CONFIG_USB_NET_INT51X1=m
CONFIG_USB_IPHETH=m
CONFIG_USB_SIERRA_NET=m
CONFIG_USB_VL600=m
CONFIG_USB_NET_CH9200=m
# CONFIG_USB_NET_AQC111 is not set
CONFIG_USB_RTL8153_ECM=m
CONFIG_WLAN=y
CONFIG_WLAN_VENDOR_ADMTEK=y
CONFIG_ADM8211=m
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
# CONFIG_ATH_DEBUG is not set
CONFIG_ATH5K=m
CONFIG_ATH5K_DEBUG=y
CONFIG_ATH5K_PCI=y
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_COMMON_DEBUG=y
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=m
CONFIG_ATH9K_PCI=y
CONFIG_ATH9K_AHB=y
CONFIG_ATH9K_DEBUGFS=y
# CONFIG_ATH9K_STATION_STATISTICS is not set
# CONFIG_ATH9K_DYNACK is not set
# CONFIG_ATH9K_WOW is not set
CONFIG_ATH9K_RFKILL=y
# CONFIG_ATH9K_CHANNEL_CONTEXT is not set
CONFIG_ATH9K_PCOEM=y
# CONFIG_ATH9K_PCI_NO_EEPROM is not set
CONFIG_ATH9K_HTC=m
# CONFIG_ATH9K_HTC_DEBUGFS is not set
CONFIG_ATH9K_HWRNG=y
CONFIG_ATH9K_COMMON_SPECTRAL=y
CONFIG_CARL9170=m
CONFIG_CARL9170_LEDS=y
# CONFIG_CARL9170_DEBUGFS is not set
CONFIG_CARL9170_WPC=y
# CONFIG_CARL9170_HWRNG is not set
CONFIG_ATH6KL=m
CONFIG_ATH6KL_SDIO=m
CONFIG_ATH6KL_USB=m
CONFIG_ATH6KL_DEBUG=y
CONFIG_AR5523=m
CONFIG_WIL6210=m
CONFIG_WIL6210_ISR_COR=y
CONFIG_WIL6210_DEBUGFS=y
CONFIG_ATH10K=m
CONFIG_ATH10K_CE=y
CONFIG_ATH10K_PCI=m
# CONFIG_ATH10K_AHB is not set
# CONFIG_ATH10K_SDIO is not set
# CONFIG_ATH10K_USB is not set
# CONFIG_ATH10K_DEBUG is not set
CONFIG_ATH10K_DEBUGFS=y
# CONFIG_ATH10K_SPECTRAL is not set
CONFIG_WCN36XX=m
# CONFIG_WCN36XX_DEBUGFS is not set
# CONFIG_ATH11K is not set
# CONFIG_ATH12K is not set
CONFIG_WLAN_VENDOR_ATMEL=y
CONFIG_ATMEL=m
CONFIG_PCI_ATMEL=m
CONFIG_AT76C50X_USB=m
CONFIG_WLAN_VENDOR_BROADCOM=y
CONFIG_B43=m
CONFIG_B43_BCMA=y
CONFIG_B43_SSB=y
CONFIG_B43_BUSES_BCMA_AND_SSB=y
# CONFIG_B43_BUSES_BCMA is not set
# CONFIG_B43_BUSES_SSB is not set
CONFIG_B43_PCI_AUTOSELECT=y
CONFIG_B43_PCICORE_AUTOSELECT=y
CONFIG_B43_SDIO=y
CONFIG_B43_BCMA_PIO=y
CONFIG_B43_PIO=y
CONFIG_B43_PHY_G=y
CONFIG_B43_PHY_N=y
CONFIG_B43_PHY_LP=y
CONFIG_B43_PHY_HT=y
CONFIG_B43_LEDS=y
CONFIG_B43_HWRNG=y
CONFIG_B43_DEBUG=y
CONFIG_B43LEGACY=m
CONFIG_B43LEGACY_PCI_AUTOSELECT=y
CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
CONFIG_B43LEGACY_LEDS=y
CONFIG_B43LEGACY_HWRNG=y
CONFIG_B43LEGACY_DEBUG=y
CONFIG_B43LEGACY_DMA=y
CONFIG_B43LEGACY_PIO=y
CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
# CONFIG_B43LEGACY_DMA_MODE is not set
# CONFIG_B43LEGACY_PIO_MODE is not set
CONFIG_BRCMUTIL=m
CONFIG_BRCMSMAC=m
CONFIG_BRCMSMAC_LEDS=y
CONFIG_BRCMFMAC=m
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_PROTO_MSGBUF=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
CONFIG_BRCMFMAC_PCIE=y
# CONFIG_BRCM_TRACING is not set
# CONFIG_BRCMDBG is not set
CONFIG_WLAN_VENDOR_CISCO=y
# CONFIG_AIRO is not set
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_IPW2100=m
CONFIG_IPW2100_MONITOR=y
# CONFIG_IPW2100_DEBUG is not set
CONFIG_IPW2200=m
CONFIG_IPW2200_MONITOR=y
CONFIG_IPW2200_RADIOTAP=y
CONFIG_IPW2200_PROMISCUOUS=y
CONFIG_IPW2200_QOS=y
# CONFIG_IPW2200_DEBUG is not set
CONFIG_LIBIPW=m
# CONFIG_LIBIPW_DEBUG is not set
CONFIG_IWLEGACY=m
CONFIG_IWL4965=m
CONFIG_IWL3945=m

#
# iwl3945 / iwl4965 Debugging Options
#
CONFIG_IWLEGACY_DEBUG=y
CONFIG_IWLEGACY_DEBUGFS=y
# end of iwl3945 / iwl4965 Debugging Options

CONFIG_IWLWIFI=m
CONFIG_IWLWIFI_LEDS=y
CONFIG_IWLDVM=m
CONFIG_IWLMVM=m
CONFIG_IWLWIFI_OPMODE_MODULAR=y

#
# Debugging Options
#
CONFIG_IWLWIFI_DEBUG=y
CONFIG_IWLWIFI_DEBUGFS=y
# end of Debugging Options

CONFIG_WLAN_VENDOR_INTERSIL=y
CONFIG_HOSTAP=m
CONFIG_HOSTAP_FIRMWARE=y
# CONFIG_HOSTAP_FIRMWARE_NVRAM is not set
CONFIG_HOSTAP_PLX=m
CONFIG_HOSTAP_PCI=m
CONFIG_HERMES=m
CONFIG_HERMES_PRISM=y
CONFIG_HERMES_CACHE_FW_ON_INIT=y
CONFIG_PLX_HERMES=m
CONFIG_TMD_HERMES=m
CONFIG_NORTEL_HERMES=m
CONFIG_PCI_HERMES=m
CONFIG_ORINOCO_USB=m
CONFIG_P54_COMMON=m
CONFIG_P54_USB=m
CONFIG_P54_PCI=m
# CONFIG_P54_SPI is not set
CONFIG_P54_LEDS=y
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_USB=m
CONFIG_LIBERTAS_SDIO=m
# CONFIG_LIBERTAS_SPI is not set
# CONFIG_LIBERTAS_DEBUG is not set
CONFIG_LIBERTAS_MESH=y
CONFIG_LIBERTAS_THINFIRM=m
# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
CONFIG_LIBERTAS_THINFIRM_USB=m
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_SDIO=m
CONFIG_MWIFIEX_PCIE=m
CONFIG_MWIFIEX_USB=m
CONFIG_MWL8K=m
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=m
CONFIG_MT76_CORE=m
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=m
CONFIG_MT76x02_LIB=m
CONFIG_MT76x02_USB=m
CONFIG_MT76_CONNAC_LIB=m
CONFIG_MT76x0_COMMON=m
CONFIG_MT76x0U=m
CONFIG_MT76x0E=m
CONFIG_MT76x2_COMMON=m
CONFIG_MT76x2E=m
CONFIG_MT76x2U=m
CONFIG_MT7603E=m
CONFIG_MT7615_COMMON=m
CONFIG_MT7615E=m
# CONFIG_MT7663U is not set
# CONFIG_MT7663S is not set
# CONFIG_MT7915E is not set
# CONFIG_MT7921E is not set
# CONFIG_MT7921S is not set
# CONFIG_MT7921U is not set
# CONFIG_MT7996E is not set
CONFIG_WLAN_VENDOR_MICROCHIP=y
# CONFIG_WILC1000_SDIO is not set
# CONFIG_WILC1000_SPI is not set
# CONFIG_WLAN_VENDOR_PURELIFI is not set
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=m
CONFIG_RT2400PCI=m
CONFIG_RT2500PCI=m
CONFIG_RT61PCI=m
CONFIG_RT2800PCI=m
CONFIG_RT2800PCI_RT33XX=y
CONFIG_RT2800PCI_RT35XX=y
CONFIG_RT2800PCI_RT53XX=y
CONFIG_RT2800PCI_RT3290=y
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
CONFIG_RT2800USB_RT33XX=y
CONFIG_RT2800USB_RT35XX=y
CONFIG_RT2800USB_RT3573=y
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
CONFIG_RT2800USB_UNKNOWN=y
CONFIG_RT2800_LIB=m
CONFIG_RT2800_LIB_MMIO=m
CONFIG_RT2X00_LIB_MMIO=m
CONFIG_RT2X00_LIB_PCI=m
CONFIG_RT2X00_LIB_USB=m
CONFIG_RT2X00_LIB=m
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
CONFIG_RT2X00_LIB_DEBUGFS=y
# CONFIG_RT2X00_DEBUG is not set
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_RTL8180=m
CONFIG_RTL8187=m
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=m
CONFIG_RTL8192CE=m
CONFIG_RTL8192SE=m
CONFIG_RTL8192DE=m
CONFIG_RTL8723AE=m
CONFIG_RTL8723BE=m
CONFIG_RTL8188EE=m
CONFIG_RTL8192EE=m
CONFIG_RTL8821AE=m
CONFIG_RTL8192CU=m
CONFIG_RTLWIFI=m
CONFIG_RTLWIFI_PCI=m
CONFIG_RTLWIFI_USB=m
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8723_COMMON=m
CONFIG_RTLBTCOEXIST=m
CONFIG_RTL8XXXU=m
# CONFIG_RTL8XXXU_UNTESTED is not set
# CONFIG_RTW88 is not set
# CONFIG_RTW89 is not set
CONFIG_WLAN_VENDOR_RSI=y
CONFIG_RSI_91X=m
CONFIG_RSI_DEBUGFS=y
CONFIG_RSI_SDIO=m
CONFIG_RSI_USB=m
CONFIG_RSI_COEX=y
# CONFIG_WLAN_VENDOR_SILABS is not set
CONFIG_WLAN_VENDOR_ST=y
CONFIG_CW1200=m
CONFIG_CW1200_WLAN_SDIO=m
# CONFIG_CW1200_WLAN_SPI is not set
CONFIG_WLAN_VENDOR_TI=y
CONFIG_WL1251=m
CONFIG_WL1251_SPI=m
CONFIG_WL1251_SDIO=m
CONFIG_WL12XX=m
CONFIG_WL18XX=m
CONFIG_WLCORE=m
CONFIG_WLCORE_SPI=m
CONFIG_WLCORE_SDIO=m
CONFIG_WLAN_VENDOR_ZYDAS=y
CONFIG_USB_ZD1201=m
CONFIG_ZD1211RW=m
# CONFIG_ZD1211RW_DEBUG is not set
CONFIG_WLAN_VENDOR_QUANTENNA=y
CONFIG_QTNFMAC=m
CONFIG_QTNFMAC_PCIE=m
CONFIG_USB_NET_RNDIS_WLAN=m
CONFIG_MAC80211_HWSIM=m
# CONFIG_VIRT_WIFI is not set
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
# CONFIG_IEEE802154_AT86RF230 is not set
# CONFIG_IEEE802154_MRF24J40 is not set
# CONFIG_IEEE802154_CC2520 is not set
CONFIG_IEEE802154_ATUSB=m
# CONFIG_IEEE802154_ADF7242 is not set
# CONFIG_IEEE802154_CA8210 is not set
# CONFIG_IEEE802154_MCR20A is not set
# CONFIG_IEEE802154_HWSIM is not set

#
# Wireless WAN
#
# CONFIG_WWAN is not set
# end of Wireless WAN

# CONFIG_VMXNET3 is not set
# CONFIG_FUJITSU_ES is not set
# CONFIG_NETDEVSIM is not set
CONFIG_NET_FAILOVER=m
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=m
CONFIG_INPUT_SPARSEKMAP=m
CONFIG_INPUT_MATRIXKMAP=y
CONFIG_INPUT_VIVALDIFMAP=y

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=m
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ADC=m
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=m
CONFIG_KEYBOARD_GPIO_POLLED=m
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_PINEPHONE is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_SUN4I_LRADC is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
CONFIG_KEYBOARD_CROS_EC=y
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_KEYBOARD_CYPRESS_SF is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
CONFIG_MOUSE_PS2_SENTELIC=y
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_SMBUS=y
CONFIG_MOUSE_SERIAL=m
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=m
CONFIG_MOUSE_ELAN_I2C=y
CONFIG_MOUSE_ELAN_I2C_I2C=y
CONFIG_MOUSE_ELAN_I2C_SMBUS=y
CONFIG_MOUSE_VSXXXAA=m
# CONFIG_MOUSE_GPIO is not set
CONFIG_MOUSE_SYNAPTICS_I2C=m
CONFIG_MOUSE_SYNAPTICS_USB=m
CONFIG_INPUT_JOYSTICK=y
# CONFIG_JOYSTICK_ANALOG is not set
# CONFIG_JOYSTICK_A3D is not set
# CONFIG_JOYSTICK_ADC is not set
# CONFIG_JOYSTICK_ADI is not set
# CONFIG_JOYSTICK_COBRA is not set
# CONFIG_JOYSTICK_GF2K is not set
# CONFIG_JOYSTICK_GRIP is not set
# CONFIG_JOYSTICK_GRIP_MP is not set
# CONFIG_JOYSTICK_GUILLEMOT is not set
# CONFIG_JOYSTICK_INTERACT is not set
# CONFIG_JOYSTICK_SIDEWINDER is not set
# CONFIG_JOYSTICK_TMDC is not set
CONFIG_JOYSTICK_IFORCE=m
CONFIG_JOYSTICK_IFORCE_USB=m
CONFIG_JOYSTICK_IFORCE_232=m
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
CONFIG_JOYSTICK_STINGER=m
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
# CONFIG_JOYSTICK_AS5011 is not set
# CONFIG_JOYSTICK_JOYDUMP is not set
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
# CONFIG_JOYSTICK_PSXPAD_SPI is not set
# CONFIG_JOYSTICK_PXRC is not set
# CONFIG_JOYSTICK_QWIIC is not set
# CONFIG_JOYSTICK_FSIA6B is not set
# CONFIG_JOYSTICK_SENSEHAT is not set
CONFIG_INPUT_TABLET=y
CONFIG_TABLET_USB_ACECAD=m
CONFIG_TABLET_USB_AIPTEK=m
CONFIG_TABLET_USB_HANWANG=m
CONFIG_TABLET_USB_KBTAB=m
CONFIG_TABLET_USB_PEGASUS=m
CONFIG_TABLET_SERIAL_WACOM4=m
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_AD7877 is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ADC is not set
# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_BU21029 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 is not set
# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP5 is not set
CONFIG_TOUCHSCREEN_DYNAPRO=m
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
CONFIG_TOUCHSCREEN_EETI=m
CONFIG_TOUCHSCREEN_EGALAX=m
# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
# CONFIG_TOUCHSCREEN_EXC3000 is not set
CONFIG_TOUCHSCREEN_FUJITSU=m
# CONFIG_TOUCHSCREEN_GOODIX is not set
# CONFIG_TOUCHSCREEN_HIDEEP is not set
# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set
# CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set
CONFIG_TOUCHSCREEN_ILI210X=m
# CONFIG_TOUCHSCREEN_ILITEK is not set
# CONFIG_TOUCHSCREEN_S6SY761 is not set
CONFIG_TOUCHSCREEN_GUNZE=m
# CONFIG_TOUCHSCREEN_EKTF2127 is not set
CONFIG_TOUCHSCREEN_ELAN=m
CONFIG_TOUCHSCREEN_ELO=m
CONFIG_TOUCHSCREEN_WACOM_W8001=m
CONFIG_TOUCHSCREEN_WACOM_I2C=m
# CONFIG_TOUCHSCREEN_MAX11801 is not set
CONFIG_TOUCHSCREEN_MCS5000=m
CONFIG_TOUCHSCREEN_MMS114=m
# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
# CONFIG_TOUCHSCREEN_MSG2638 is not set
CONFIG_TOUCHSCREEN_MTOUCH=m
# CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS is not set
# CONFIG_TOUCHSCREEN_IMAGIS is not set
# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
CONFIG_TOUCHSCREEN_INEXIO=m
CONFIG_TOUCHSCREEN_MK712=m
CONFIG_TOUCHSCREEN_PENMOUNT=m
CONFIG_TOUCHSCREEN_EDT_FT5X06=m
CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
CONFIG_TOUCHSCREEN_TOUCHWIN=m
CONFIG_TOUCHSCREEN_PIXCIR=m
# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
# CONFIG_TOUCHSCREEN_WM97XX is not set
CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
CONFIG_TOUCHSCREEN_TOUCHIT213=m
CONFIG_TOUCHSCREEN_TSC_SERIO=m
# CONFIG_TOUCHSCREEN_TSC2004 is not set
# CONFIG_TOUCHSCREEN_TSC2005 is not set
CONFIG_TOUCHSCREEN_TSC2007=m
# CONFIG_TOUCHSCREEN_TSC2007_IIO is not set
# CONFIG_TOUCHSCREEN_RM_TS is not set
# CONFIG_TOUCHSCREEN_SILEAD is not set
# CONFIG_TOUCHSCREEN_SIS_I2C is not set
CONFIG_TOUCHSCREEN_ST1232=m
# CONFIG_TOUCHSCREEN_STMFTS is not set
# CONFIG_TOUCHSCREEN_SUN4I is not set
# CONFIG_TOUCHSCREEN_SUR40 is not set
# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
# CONFIG_TOUCHSCREEN_SX8654 is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_TOUCHSCREEN_ZET6223 is not set
CONFIG_TOUCHSCREEN_ZFORCE=m
# CONFIG_TOUCHSCREEN_COLIBRI_VF50 is not set
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
# CONFIG_TOUCHSCREEN_IQS5XX is not set
# CONFIG_TOUCHSCREEN_ZINITIX is not set
# CONFIG_TOUCHSCREEN_HIMAX_HX83112B is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
# CONFIG_INPUT_BMA150 is not set
CONFIG_INPUT_E3X0_BUTTON=m
CONFIG_INPUT_MMA8450=m
# CONFIG_INPUT_GPIO_BEEPER is not set
# CONFIG_INPUT_GPIO_DECODER is not set
# CONFIG_INPUT_GPIO_VIBRA is not set
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
CONFIG_INPUT_KXTJ9=m
CONFIG_INPUT_POWERMATE=m
CONFIG_INPUT_YEALINK=m
CONFIG_INPUT_CM109=m
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
CONFIG_INPUT_AXP20X_PEK=m
CONFIG_INPUT_UINPUT=m
# CONFIG_INPUT_PCF8574 is not set
CONFIG_INPUT_PWM_BEEPER=m
# CONFIG_INPUT_PWM_VIBRA is not set
CONFIG_INPUT_RK805_PWRKEY=m
CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
# CONFIG_INPUT_DA7280_HAPTICS is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_IBM_PANEL is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_INPUT_IQS269A is not set
# CONFIG_INPUT_IQS626A is not set
# CONFIG_INPUT_IQS7222 is not set
CONFIG_INPUT_CMA3000=m
CONFIG_INPUT_CMA3000_I2C=m
# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
# CONFIG_INPUT_DRV260X_HAPTICS is not set
# CONFIG_INPUT_DRV2665_HAPTICS is not set
# CONFIG_INPUT_DRV2667_HAPTICS is not set
CONFIG_RMI4_CORE=m
# CONFIG_RMI4_I2C is not set
# CONFIG_RMI4_SPI is not set
# CONFIG_RMI4_SMB is not set
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=m
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
# CONFIG_RMI4_F34 is not set
# CONFIG_RMI4_F3A is not set
# CONFIG_RMI4_F54 is not set
# CONFIG_RMI4_F55 is not set

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO_AMBAKMI=y
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIO_RAW=m
CONFIG_SERIO_ALTERA_PS2=m
# CONFIG_SERIO_PS2MULT is not set
CONFIG_SERIO_ARC_PS2=m
# CONFIG_SERIO_APBPS2 is not set
# CONFIG_SERIO_SUN4I_PS2 is not set
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
# CONFIG_GAMEPORT is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_LEGACY_TIOCSTI is not set
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
CONFIG_SERIAL_8250_PCILIB=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_EXAR=y
CONFIG_SERIAL_8250_NR_UARTS=32
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
# CONFIG_SERIAL_8250_PCI1XXXX is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_8250_PERICOM=y
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
# CONFIG_SERIAL_AMBA_PL010 is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set
# CONFIG_SERIAL_KGDB_NMI is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_CONSOLE_POLL=y
CONFIG_SERIAL_JSM=m
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
CONFIG_SERIAL_ARC=m
CONFIG_SERIAL_ARC_NR_PORTS=1
# CONFIG_SERIAL_RP2 is not set
CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_SERIAL_FSL_LINFLEXUART=y
CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_NONSTANDARD=y
# CONFIG_MOXA_INTELLIO is not set
# CONFIG_MOXA_SMARTIO is not set
CONFIG_SYNCLINK_GT=m
CONFIG_N_HDLC=m
CONFIG_N_GSM=m
CONFIG_NOZOMI=m
# CONFIG_NULL_TTY is not set
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
# CONFIG_RPMSG_TTY is not set
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_TTY_PRINTK is not set
CONFIG_VIRTIO_CONSOLE=y
CONFIG_IPMI_HANDLER=y
CONFIG_IPMI_DMI_DECODE=y
CONFIG_IPMI_PLAT_DATA=y
# CONFIG_IPMI_PANIC_EVENT is not set
CONFIG_IPMI_DEVICE_INTERFACE=m
CONFIG_IPMI_SI=m
CONFIG_IPMI_SSIF=m
# CONFIG_IPMI_IPMB is not set
CONFIG_IPMI_WATCHDOG=m
CONFIG_IPMI_POWEROFF=m
# CONFIG_SSIF_IPMI_BMC is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=m
# CONFIG_HW_RANDOM_BA431 is not set
CONFIG_HW_RANDOM_VIRTIO=m
# CONFIG_HW_RANDOM_CCTRNG is not set
# CONFIG_HW_RANDOM_XIPHERA is not set
CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
CONFIG_HW_RANDOM_CN10K=y
# CONFIG_APPLICOM is not set
CONFIG_DEVMEM=y
CONFIG_DEVPORT=y
CONFIG_TCG_TPM=y
CONFIG_HW_RANDOM_TPM=y
# CONFIG_TCG_TIS is not set
# CONFIG_TCG_TIS_SPI is not set
# CONFIG_TCG_TIS_I2C is not set
# CONFIG_TCG_TIS_I2C_CR50 is not set
# CONFIG_TCG_TIS_I2C_ATMEL is not set
CONFIG_TCG_TIS_I2C_INFINEON=y
# CONFIG_TCG_TIS_I2C_NUVOTON is not set
CONFIG_TCG_ATMEL=m
# CONFIG_TCG_INFINEON is not set
# CONFIG_TCG_CRB is not set
# CONFIG_TCG_VTPM_PROXY is not set
# CONFIG_TCG_TIS_ST33ZP24_I2C is not set
# CONFIG_TCG_TIS_ST33ZP24_SPI is not set
# CONFIG_XILLYBUS is not set
# CONFIG_XILLYUSB is not set
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=m
CONFIG_I2C_MUX_GPIO=m
CONFIG_I2C_MUX_GPMUX=m
# CONFIG_I2C_MUX_LTC4306 is not set
CONFIG_I2C_MUX_PCA9541=m
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_MUX_PINCTRL=m
CONFIG_I2C_MUX_REG=m
CONFIG_I2C_DEMUX_PINCTRL=m
# CONFIG_I2C_MUX_MLXCPLD is not set
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_SMBUS=m
CONFIG_I2C_ALGOBIT=m
CONFIG_I2C_ALGOPCA=m

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
CONFIG_I2C_CCGX_UCSI=m
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
CONFIG_I2C_NFORCE2=m
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set

#
# ACPI drivers
#
CONFIG_I2C_SCMI=y

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CADENCE is not set
# CONFIG_I2C_CBUS_GPIO is not set
CONFIG_I2C_DESIGNWARE_CORE=y
# CONFIG_I2C_DESIGNWARE_SLAVE is not set
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_DESIGNWARE_PCI=m
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=m
# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
# CONFIG_I2C_HISI is not set
CONFIG_I2C_MV64XXX=y
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_PCA_PLATFORM=m
CONFIG_I2C_RK3X=y
CONFIG_I2C_SIMTEC=m
CONFIG_I2C_VERSATILE=m
# CONFIG_I2C_THUNDERX is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
CONFIG_I2C_DIOLAN_U2C=m
# CONFIG_I2C_CP2615 is not set
# CONFIG_I2C_PCI1XXXX is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
CONFIG_I2C_TINY_USB=m
CONFIG_I2C_VIPERBOARD=m

#
# Other I2C/SMBus bus drivers
#
CONFIG_I2C_CROS_EC_TUNNEL=y
# CONFIG_I2C_VIRTIO is not set
# end of I2C Hardware Bus support

CONFIG_I2C_STUB=m
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=m
# CONFIG_I2C_SLAVE_TESTUNIT is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

# CONFIG_I3C is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y

#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
CONFIG_SPI_BITBANG=y
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_CADENCE_XSPI is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_HISI_KUNPENG is not set
# CONFIG_SPI_HISI_SFC_V3XX is not set
CONFIG_SPI_GPIO=y
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_MICROCHIP_CORE is not set
# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PCI1XXXX is not set
CONFIG_SPI_PL022=y
# CONFIG_SPI_PXA2XX is not set
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_SN_F_OSPI is not set
# CONFIG_SPI_SUN4I is not set
CONFIG_SPI_SUN6I=y
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_THUNDERX is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_SPI_AMD is not set

#
# SPI Multiplexer support
#
# CONFIG_SPI_MUX is not set

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=m
# CONFIG_SPI_LOOPBACK_TEST is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_DYNAMIC=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set

#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
CONFIG_PPS_CLIENT_LDISC=m
CONFIG_PPS_CLIENT_GPIO=m

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_DP83640_PHY=m
# CONFIG_PTP_1588_CLOCK_INES is not set
CONFIG_PTP_1588_CLOCK_KVM=y
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
# CONFIG_PTP_1588_CLOCK_OCP is not set
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
CONFIG_PINCTRL_AMD=y
CONFIG_PINCTRL_AXP209=y
# CONFIG_PINCTRL_CY8C95X0 is not set
CONFIG_PINCTRL_MAX77620=y
# CONFIG_PINCTRL_MCP23S08 is not set
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
# CONFIG_PINCTRL_OCELOT is not set
CONFIG_PINCTRL_RK805=y
CONFIG_PINCTRL_SINGLE=y
# CONFIG_PINCTRL_STMFX is not set
# CONFIG_PINCTRL_SX150X is not set

#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers

CONFIG_PINCTRL_SUNXI=y
# CONFIG_PINCTRL_SUN4I_A10 is not set
# CONFIG_PINCTRL_SUN5I is not set
# CONFIG_PINCTRL_SUN6I_A31 is not set
# CONFIG_PINCTRL_SUN6I_A31_R is not set
# CONFIG_PINCTRL_SUN8I_A23 is not set
# CONFIG_PINCTRL_SUN8I_A33 is not set
# CONFIG_PINCTRL_SUN8I_A83T is not set
# CONFIG_PINCTRL_SUN8I_A83T_R is not set
# CONFIG_PINCTRL_SUN8I_A23_R is not set
# CONFIG_PINCTRL_SUN8I_H3 is not set
CONFIG_PINCTRL_SUN8I_H3_R=y
# CONFIG_PINCTRL_SUN8I_V3S is not set
# CONFIG_PINCTRL_SUN9I_A80 is not set
# CONFIG_PINCTRL_SUN9I_A80_R is not set
# CONFIG_PINCTRL_SUN20I_D1 is not set
CONFIG_PINCTRL_SUN50I_A64=y
CONFIG_PINCTRL_SUN50I_A64_R=y
CONFIG_PINCTRL_SUN50I_A100=y
CONFIG_PINCTRL_SUN50I_A100_R=y
CONFIG_PINCTRL_SUN50I_H5=y
CONFIG_PINCTRL_SUN50I_H6=y
CONFIG_PINCTRL_SUN50I_H6_R=y
CONFIG_PINCTRL_SUN50I_H616=y
CONFIG_PINCTRL_SUN50I_H616_R=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_CADENCE is not set
CONFIG_GPIO_DWAPB=y
# CONFIG_GPIO_EXAR is not set
# CONFIG_GPIO_FTGPIO010 is not set
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HISI is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_LOGICVC is not set
# CONFIG_GPIO_MB86S7X is not set
CONFIG_GPIO_PL061=y
# CONFIG_GPIO_SIFIVE is not set
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_WCD934X=m
CONFIG_GPIO_XGENE=y
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
# CONFIG_GPIO_ADNP is not set
# CONFIG_GPIO_FXL6408 is not set
# CONFIG_GPIO_GW_PLD is not set
# CONFIG_GPIO_MAX7300 is not set
CONFIG_GPIO_MAX732X=y
# CONFIG_GPIO_MAX732X_IRQ is not set
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
# CONFIG_GPIO_PCA9570 is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_TPIC2810 is not set
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
CONFIG_GPIO_MAX77620=y
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set
# end of PCI GPIO expanders

#
# SPI GPIO expanders
#
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
CONFIG_GPIO_VIPERBOARD=m
# end of USB GPIO expanders

#
# Virtual GPIO drivers
#
# CONFIG_GPIO_AGGREGATOR is not set
# CONFIG_GPIO_LATCH is not set
# CONFIG_GPIO_MOCKUP is not set
# CONFIG_GPIO_VIRTIO is not set
# CONFIG_GPIO_SIM is not set
# end of Virtual GPIO drivers

CONFIG_W1=m
CONFIG_W1_CON=y

#
# 1-wire Bus Masters
#
# CONFIG_W1_MASTER_MATROX is not set
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
# CONFIG_W1_MASTER_GPIO is not set
# CONFIG_W1_MASTER_SGI is not set
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
# CONFIG_W1_SLAVE_DS2405 is not set
CONFIG_W1_SLAVE_DS2408=m
# CONFIG_W1_SLAVE_DS2408_READBACK is not set
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
# CONFIG_W1_SLAVE_DS2805 is not set
# CONFIG_W1_SLAVE_DS2430 is not set
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
# CONFIG_W1_SLAVE_DS2438 is not set
# CONFIG_W1_SLAVE_DS250X is not set
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
# CONFIG_W1_SLAVE_DS28E17 is not set
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_BRCMSTB is not set
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
# CONFIG_POWER_RESET_LTC2952 is not set
# CONFIG_POWER_RESET_REGULATOR is not set
CONFIG_POWER_RESET_RESTART=y
CONFIG_POWER_RESET_VEXPRESS=y
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
# CONFIG_NVMEM_REBOOT_MODE is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_IP5XXX_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SAMSUNG_SDI is not set
CONFIG_BATTERY_SBS=m
CONFIG_CHARGER_SBS=m
CONFIG_MANAGER_SBS=m
# CONFIG_BATTERY_BQ27XXX is not set
CONFIG_CHARGER_AXP20X=m
CONFIG_BATTERY_AXP20X=m
CONFIG_AXP20X_POWER=m
# CONFIG_BATTERY_MAX17040 is not set
CONFIG_BATTERY_MAX17042=m
# CONFIG_BATTERY_MAX1721X is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
# CONFIG_CHARGER_GPIO is not set
# CONFIG_CHARGER_MANAGER is not set
# CONFIG_CHARGER_LT3651 is not set
# CONFIG_CHARGER_LTC4162L is not set
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_MAX77976 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25890 is not set
CONFIG_CHARGER_BQ25980=m
# CONFIG_CHARGER_BQ256XX is not set
# CONFIG_CHARGER_RK817 is not set
CONFIG_CHARGER_SMB347=m
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_BATTERY_GOLDFISH is not set
# CONFIG_BATTERY_RT5033 is not set
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_RT9467 is not set
# CONFIG_CHARGER_RT9471 is not set
CONFIG_CHARGER_CROS_USBPD=m
CONFIG_CHARGER_CROS_PCHG=y
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
# CONFIG_BATTERY_UG3105 is not set
CONFIG_HWMON=y
CONFIG_HWMON_VID=m
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
CONFIG_SENSORS_AD7414=m
CONFIG_SENSORS_AD7418=m
CONFIG_SENSORS_ADM1025=m
CONFIG_SENSORS_ADM1026=m
CONFIG_SENSORS_ADM1029=m
CONFIG_SENSORS_ADM1031=m
# CONFIG_SENSORS_ADM1177 is not set
CONFIG_SENSORS_ADM9240=m
CONFIG_SENSORS_ADT7X10=m
# CONFIG_SENSORS_ADT7310 is not set
CONFIG_SENSORS_ADT7410=m
CONFIG_SENSORS_ADT7411=m
CONFIG_SENSORS_ADT7462=m
CONFIG_SENSORS_ADT7470=m
CONFIG_SENSORS_ADT7475=m
# CONFIG_SENSORS_AHT10 is not set
# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
# CONFIG_SENSORS_AS370 is not set
CONFIG_SENSORS_ASC7621=m
# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
CONFIG_SENSORS_ARM_SCMI=y
CONFIG_SENSORS_ARM_SCPI=y
CONFIG_SENSORS_ATXP1=m
# CONFIG_SENSORS_CORSAIR_CPRO is not set
# CONFIG_SENSORS_CORSAIR_PSU is not set
CONFIG_SENSORS_DRIVETEMP=m
CONFIG_SENSORS_DS620=m
CONFIG_SENSORS_DS1621=m
# CONFIG_SENSORS_I5K_AMB is not set
CONFIG_SENSORS_F71805F=m
CONFIG_SENSORS_F71882FG=m
CONFIG_SENSORS_F75375S=m
# CONFIG_SENSORS_FTSTEUTATES is not set
CONFIG_SENSORS_GL518SM=m
CONFIG_SENSORS_GL520SM=m
CONFIG_SENSORS_G760A=m
CONFIG_SENSORS_G762=m
CONFIG_SENSORS_GPIO_FAN=m
# CONFIG_SENSORS_HIH6130 is not set
CONFIG_SENSORS_IBMAEM=m
CONFIG_SENSORS_IBMPEX=m
CONFIG_SENSORS_IIO_HWMON=m
CONFIG_SENSORS_IT87=m
# CONFIG_SENSORS_JC42 is not set
CONFIG_SENSORS_POWR1220=m
CONFIG_SENSORS_LINEAGE=m
CONFIG_SENSORS_LTC2945=m
# CONFIG_SENSORS_LTC2947_I2C is not set
# CONFIG_SENSORS_LTC2947_SPI is not set
# CONFIG_SENSORS_LTC2990 is not set
# CONFIG_SENSORS_LTC2992 is not set
CONFIG_SENSORS_LTC4151=m
CONFIG_SENSORS_LTC4215=m
CONFIG_SENSORS_LTC4222=m
CONFIG_SENSORS_LTC4245=m
CONFIG_SENSORS_LTC4260=m
CONFIG_SENSORS_LTC4261=m
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX127 is not set
CONFIG_SENSORS_MAX16065=m
CONFIG_SENSORS_MAX1619=m
CONFIG_SENSORS_MAX1668=m
CONFIG_SENSORS_MAX197=m
# CONFIG_SENSORS_MAX31722 is not set
# CONFIG_SENSORS_MAX31730 is not set
# CONFIG_SENSORS_MAX31760 is not set
# CONFIG_SENSORS_MAX6620 is not set
# CONFIG_SENSORS_MAX6621 is not set
CONFIG_SENSORS_MAX6639=m
CONFIG_SENSORS_MAX6650=m
CONFIG_SENSORS_MAX6697=m
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MC34VR500 is not set
CONFIG_SENSORS_MCP3021=m
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_TPS23861 is not set
# CONFIG_SENSORS_MR75203 is not set
# CONFIG_SENSORS_ADCXX is not set
CONFIG_SENSORS_LM63=m
# CONFIG_SENSORS_LM70 is not set
CONFIG_SENSORS_LM73=m
CONFIG_SENSORS_LM75=m
CONFIG_SENSORS_LM77=m
CONFIG_SENSORS_LM78=m
CONFIG_SENSORS_LM80=m
CONFIG_SENSORS_LM83=m
CONFIG_SENSORS_LM85=m
CONFIG_SENSORS_LM87=m
CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_LM92=m
CONFIG_SENSORS_LM93=m
CONFIG_SENSORS_LM95234=m
CONFIG_SENSORS_LM95241=m
CONFIG_SENSORS_LM95245=m
CONFIG_SENSORS_PC87360=m
CONFIG_SENSORS_PC87427=m
CONFIG_SENSORS_NTC_THERMISTOR=m
CONFIG_SENSORS_NCT6683=m
CONFIG_SENSORS_NCT6775_CORE=m
CONFIG_SENSORS_NCT6775=m
# CONFIG_SENSORS_NCT6775_I2C is not set
CONFIG_SENSORS_NCT7802=m
CONFIG_SENSORS_NCT7904=m
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
# CONFIG_SENSORS_NZXT_SMART2 is not set
# CONFIG_SENSORS_OCC_P8_I2C is not set
CONFIG_SENSORS_PCF8591=m
CONFIG_PMBUS=m
CONFIG_SENSORS_PMBUS=m
# CONFIG_SENSORS_ACBEL_FSG032 is not set
# CONFIG_SENSORS_ADM1266 is not set
CONFIG_SENSORS_ADM1275=m
# CONFIG_SENSORS_BEL_PFE is not set
# CONFIG_SENSORS_BPA_RS600 is not set
# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set
# CONFIG_SENSORS_FSP_3Y is not set
# CONFIG_SENSORS_IBM_CFFPS is not set
# CONFIG_SENSORS_DPS920AB is not set
# CONFIG_SENSORS_INSPUR_IPSPS is not set
# CONFIG_SENSORS_IR35221 is not set
# CONFIG_SENSORS_IR36021 is not set
# CONFIG_SENSORS_IR38064 is not set
# CONFIG_SENSORS_IRPS5401 is not set
# CONFIG_SENSORS_ISL68137 is not set
CONFIG_SENSORS_LM25066=m
# CONFIG_SENSORS_LM25066_REGULATOR is not set
# CONFIG_SENSORS_LT7182S is not set
CONFIG_SENSORS_LTC2978=m
# CONFIG_SENSORS_LTC2978_REGULATOR is not set
# CONFIG_SENSORS_LTC3815 is not set
# CONFIG_SENSORS_MAX15301 is not set
CONFIG_SENSORS_MAX16064=m
# CONFIG_SENSORS_MAX16601 is not set
# CONFIG_SENSORS_MAX20730 is not set
# CONFIG_SENSORS_MAX20751 is not set
# CONFIG_SENSORS_MAX31785 is not set
CONFIG_SENSORS_MAX34440=m
CONFIG_SENSORS_MAX8688=m
# CONFIG_SENSORS_MP2888 is not set
# CONFIG_SENSORS_MP2975 is not set
# CONFIG_SENSORS_MP5023 is not set
# CONFIG_SENSORS_MPQ7932 is not set
# CONFIG_SENSORS_PIM4328 is not set
# CONFIG_SENSORS_PLI1209BC is not set
# CONFIG_SENSORS_PM6764TR is not set
# CONFIG_SENSORS_PXE1610 is not set
# CONFIG_SENSORS_Q54SJ108A2 is not set
# CONFIG_SENSORS_STPDDC60 is not set
# CONFIG_SENSORS_TDA38640 is not set
CONFIG_SENSORS_TPS40422=m
# CONFIG_SENSORS_TPS53679 is not set
# CONFIG_SENSORS_TPS546D24 is not set
CONFIG_SENSORS_UCD9000=m
CONFIG_SENSORS_UCD9200=m
# CONFIG_SENSORS_XDPE152 is not set
# CONFIG_SENSORS_XDPE122 is not set
CONFIG_SENSORS_ZL6100=m
CONFIG_SENSORS_PWM_FAN=m
# CONFIG_SENSORS_SBTSI is not set
# CONFIG_SENSORS_SBRMI is not set
CONFIG_SENSORS_SHT15=m
CONFIG_SENSORS_SHT21=m
CONFIG_SENSORS_SHT3x=m
# CONFIG_SENSORS_SHT4x is not set
CONFIG_SENSORS_SHTC1=m
CONFIG_SENSORS_SIS5595=m
CONFIG_SENSORS_DME1737=m
CONFIG_SENSORS_EMC1403=m
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC2305 is not set
CONFIG_SENSORS_EMC6W201=m
CONFIG_SENSORS_SMSC47M1=m
CONFIG_SENSORS_SMSC47M192=m
CONFIG_SENSORS_SMSC47B397=m
CONFIG_SENSORS_SCH56XX_COMMON=m
CONFIG_SENSORS_SCH5627=m
CONFIG_SENSORS_SCH5636=m
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
CONFIG_SENSORS_ADC128D818=m
CONFIG_SENSORS_ADS7828=m
# CONFIG_SENSORS_ADS7871 is not set
CONFIG_SENSORS_AMC6821=m
CONFIG_SENSORS_INA209=m
CONFIG_SENSORS_INA2XX=m
# CONFIG_SENSORS_INA238 is not set
CONFIG_SENSORS_INA3221=m
CONFIG_SENSORS_TC74=m
CONFIG_SENSORS_THMC50=m
CONFIG_SENSORS_TMP102=m
CONFIG_SENSORS_TMP103=m
CONFIG_SENSORS_TMP108=m
CONFIG_SENSORS_TMP401=m
CONFIG_SENSORS_TMP421=m
# CONFIG_SENSORS_TMP464 is not set
# CONFIG_SENSORS_TMP513 is not set
CONFIG_SENSORS_VEXPRESS=m
CONFIG_SENSORS_VIA686A=m
CONFIG_SENSORS_VT1211=m
CONFIG_SENSORS_VT8231=m
# CONFIG_SENSORS_W83773G is not set
CONFIG_SENSORS_W83781D=m
CONFIG_SENSORS_W83791D=m
CONFIG_SENSORS_W83792D=m
CONFIG_SENSORS_W83793=m
CONFIG_SENSORS_W83795=m
# CONFIG_SENSORS_W83795_FANCTRL is not set
CONFIG_SENSORS_W83L785TS=m
CONFIG_SENSORS_W83L786NG=m
CONFIG_SENSORS_W83627HF=m
CONFIG_SENSORS_W83627EHF=m
# CONFIG_SENSORS_XGENE is not set

#
# ACPI drivers
#
CONFIG_SENSORS_ACPI_POWER=m
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_BANG_BANG=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_THERMAL_EMULATION=y
# CONFIG_THERMAL_MMIO is not set
CONFIG_MAX77620_THERMAL=m
CONFIG_SUN8I_THERMAL=m
CONFIG_GENERIC_ADC_THERMAL=m
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set
CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=m
CONFIG_GPIO_WATCHDOG=m
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
CONFIG_ARM_SP805_WATCHDOG=m
CONFIG_ARM_SBSA_WATCHDOG=m
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=m
CONFIG_SUNXI_WATCHDOG=m
# CONFIG_MAX63XX_WATCHDOG is not set
CONFIG_MAX77620_WATCHDOG=m
CONFIG_ARM_SMC_WATCHDOG=y
CONFIG_ALIM7101_WDT=m
CONFIG_I6300ESB_WDT=m
# CONFIG_HP_WATCHDOG is not set
# CONFIG_MEN_A21_WDT is not set

#
# PCI-based Watchdog Cards
#
CONFIG_PCIPCWATCHDOG=m
CONFIG_WDTPCI=m

#
# USB-based Watchdog Cards
#
CONFIG_USBPCWATCHDOG=m
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB=m
CONFIG_SSB_SPROM=y
CONFIG_SSB_BLOCKIO=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_PCIHOST=y
CONFIG_SSB_B43_PCI_BRIDGE=y
CONFIG_SSB_SDIOHOST_POSSIBLE=y
CONFIG_SSB_SDIOHOST=y
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
CONFIG_SSB_DRIVER_PCICORE=y
CONFIG_SSB_DRIVER_GPIO=y
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_BLOCKIO=y
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
CONFIG_BCMA_HOST_PCI=y
# CONFIG_BCMA_HOST_SOC is not set
CONFIG_BCMA_DRIVER_PCI=y
CONFIG_BCMA_DRIVER_GMAC_CMN=y
CONFIG_BCMA_DRIVER_GPIO=y
# CONFIG_BCMA_DEBUG is not set

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_SUN4I_GPADC is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_SMPRO is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AC100 is not set
CONFIG_MFD_AC200=y
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
CONFIG_MFD_CROS_EC_DEV=y
# CONFIG_MFD_MADERA is not set
# CONFIG_MFD_MAX597X is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
CONFIG_MFD_MAX77620=y
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77714 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6370 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_MFD_OCELOT is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
CONFIG_MFD_VIPERBOARD=m
# CONFIG_MFD_NTXEC is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_SY7636A is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT4831 is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RT5120 is not set
# CONFIG_MFD_RC5T583 is not set
CONFIG_MFD_RK808=y
# CONFIG_MFD_RN5T618 is not set
CONFIG_MFD_SEC_CORE=y
# CONFIG_MFD_SI476X_CORE is not set
CONFIG_MFD_SM501=m
CONFIG_MFD_SM501_GPIO=y
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SUN6I_PRCM=y
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS65219 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TQMX86 is not set
CONFIG_MFD_VX855=m
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
CONFIG_MFD_ROHM_BD718XX=y
# CONFIG_MFD_ROHM_BD71828 is not set
# CONFIG_MFD_ROHM_BD957XMUF is not set
# CONFIG_MFD_STPMIC1 is not set
# CONFIG_MFD_STMFX is not set
CONFIG_MFD_WCD934X=m
# CONFIG_MFD_ATC260X_I2C is not set
# CONFIG_MFD_QCOM_PM8008 is not set
CONFIG_MFD_VEXPRESS_SYSREG=y
# CONFIG_RAVE_SP_CORE is not set
# CONFIG_MFD_INTEL_M10_BMC_SPI is not set
# CONFIG_MFD_RSMU_I2C is not set
# CONFIG_MFD_RSMU_SPI is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_88PG86X is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_AD5398 is not set
# CONFIG_REGULATOR_ARM_SCMI is not set
CONFIG_REGULATOR_AXP20X=y
CONFIG_REGULATOR_BD718XX=y
# CONFIG_REGULATOR_CROS_EC is not set
# CONFIG_REGULATOR_DA9121 is not set
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
CONFIG_REGULATOR_FAN53555=y
# CONFIG_REGULATOR_FAN53880 is not set
CONFIG_REGULATOR_GPIO=y
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_LP8755 is not set
# CONFIG_REGULATOR_LTC3589 is not set
# CONFIG_REGULATOR_LTC3676 is not set
# CONFIG_REGULATOR_MAX1586 is not set
CONFIG_REGULATOR_MAX77620=y
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8893 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_MAX8973 is not set
# CONFIG_REGULATOR_MAX20086 is not set
# CONFIG_REGULATOR_MAX20411 is not set
# CONFIG_REGULATOR_MAX77826 is not set
# CONFIG_REGULATOR_MCP16502 is not set
# CONFIG_REGULATOR_MP5416 is not set
# CONFIG_REGULATOR_MP8859 is not set
# CONFIG_REGULATOR_MP886X is not set
# CONFIG_REGULATOR_MPQ7920 is not set
# CONFIG_REGULATOR_MT6311 is not set
# CONFIG_REGULATOR_MT6315 is not set
CONFIG_REGULATOR_PCA9450=y
# CONFIG_REGULATOR_PF8X00 is not set
CONFIG_REGULATOR_PFUZE100=y
# CONFIG_REGULATOR_PV88060 is not set
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_QCOM_SPMI=y
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
CONFIG_REGULATOR_RK808=y
CONFIG_REGULATOR_ROHM=y
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RT4803 is not set
# CONFIG_REGULATOR_RT5190A is not set
# CONFIG_REGULATOR_RT5739 is not set
# CONFIG_REGULATOR_RT5759 is not set
# CONFIG_REGULATOR_RT6160 is not set
# CONFIG_REGULATOR_RT6190 is not set
# CONFIG_REGULATOR_RT6245 is not set
# CONFIG_REGULATOR_RTQ2134 is not set
# CONFIG_REGULATOR_RTMV20 is not set
# CONFIG_REGULATOR_RTQ6752 is not set
# CONFIG_REGULATOR_S2MPA01 is not set
CONFIG_REGULATOR_S2MPS11=y
# CONFIG_REGULATOR_S5M8767 is not set
# CONFIG_REGULATOR_SLG51000 is not set
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
# CONFIG_REGULATOR_SY8827N is not set
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS6286X is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
CONFIG_REGULATOR_TPS65132=m
# CONFIG_REGULATOR_TPS6524X is not set
CONFIG_REGULATOR_VCTRL=y
CONFIG_REGULATOR_VEXPRESS=y
# CONFIG_REGULATOR_QCOM_LABIBB is not set
CONFIG_RC_CORE=m
CONFIG_LIRC=y
CONFIG_RC_MAP=m
CONFIG_RC_DECODERS=y
CONFIG_IR_IMON_DECODER=m
CONFIG_IR_JVC_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
CONFIG_IR_RCMM_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_XMP_DECODER=m
CONFIG_RC_DEVICES=y
CONFIG_IR_ENE=m
CONFIG_IR_FINTEK=m
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_GPIO_TX=m
CONFIG_IR_HIX5HD2=m
CONFIG_IR_IGORPLUGUSB=m
CONFIG_IR_IGUANA=m
CONFIG_IR_IMON=m
CONFIG_IR_IMON_RAW=m
CONFIG_IR_ITE_CIR=m
CONFIG_IR_MCEUSB=m
CONFIG_IR_NUVOTON=m
CONFIG_IR_PWM_TX=m
CONFIG_IR_REDRAT3=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m
CONFIG_IR_SUNXI=m
CONFIG_IR_TOY=m
CONFIG_IR_TTUSBIR=m
CONFIG_RC_ATI_REMOTE=m
CONFIG_RC_LOOPBACK=m
# CONFIG_RC_XBOX_DVD is not set
CONFIG_CEC_CORE=m
CONFIG_CEC_NOTIFIER=y

#
# CEC support
#
CONFIG_MEDIA_CEC_RC=y
CONFIG_MEDIA_CEC_SUPPORT=y
CONFIG_CEC_CH7322=m
CONFIG_CEC_CROS_EC=m
CONFIG_USB_PULSE8_CEC=m
CONFIG_USB_RAINSHADOW_CEC=m
# end of CEC support

CONFIG_MEDIA_SUPPORT=m
# CONFIG_MEDIA_SUPPORT_FILTER is not set
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
CONFIG_MEDIA_RADIO_SUPPORT=y
CONFIG_MEDIA_SDR_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_TEST_SUPPORT=y
# end of Media device types

#
# Media core support
#
CONFIG_VIDEO_DEV=m
CONFIG_MEDIA_CONTROLLER=y
CONFIG_DVB_CORE=m
# end of Media core support

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_H264=m
CONFIG_V4L2_VP9=m
CONFIG_V4L2_MEM2MEM_DEV=m
# CONFIG_V4L2_FLASH_LED_CLASS is not set
CONFIG_V4L2_FWNODE=m
CONFIG_V4L2_ASYNC=m
CONFIG_VIDEOBUF_GEN=m
CONFIG_VIDEOBUF_DMA_SG=m
# end of Video4Linux options

#
# Media controller options
#
CONFIG_MEDIA_CONTROLLER_DVB=y
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
# end of Media controller options

#
# Digital TV options
#
# CONFIG_DVB_MMAP is not set
CONFIG_DVB_NET=y
CONFIG_DVB_MAX_ADAPTERS=8
CONFIG_DVB_DYNAMIC_MINORS=y
# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
# CONFIG_DVB_ULE_DEBUG is not set
# end of Digital TV options

#
# Media drivers
#

#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_GSPCA=m
CONFIG_USB_GSPCA_BENQ=m
CONFIG_USB_GSPCA_CONEX=m
CONFIG_USB_GSPCA_CPIA1=m
CONFIG_USB_GSPCA_DTCS033=m
CONFIG_USB_GSPCA_ETOMS=m
CONFIG_USB_GSPCA_FINEPIX=m
CONFIG_USB_GSPCA_JEILINJ=m
CONFIG_USB_GSPCA_JL2005BCD=m
CONFIG_USB_GSPCA_KINECT=m
CONFIG_USB_GSPCA_KONICA=m
CONFIG_USB_GSPCA_MARS=m
CONFIG_USB_GSPCA_MR97310A=m
CONFIG_USB_GSPCA_NW80X=m
CONFIG_USB_GSPCA_OV519=m
CONFIG_USB_GSPCA_OV534=m
CONFIG_USB_GSPCA_OV534_9=m
CONFIG_USB_GSPCA_PAC207=m
CONFIG_USB_GSPCA_PAC7302=m
CONFIG_USB_GSPCA_PAC7311=m
CONFIG_USB_GSPCA_SE401=m
CONFIG_USB_GSPCA_SN9C2028=m
CONFIG_USB_GSPCA_SN9C20X=m
CONFIG_USB_GSPCA_SONIXB=m
CONFIG_USB_GSPCA_SONIXJ=m
CONFIG_USB_GSPCA_SPCA1528=m
CONFIG_USB_GSPCA_SPCA500=m
CONFIG_USB_GSPCA_SPCA501=m
CONFIG_USB_GSPCA_SPCA505=m
CONFIG_USB_GSPCA_SPCA506=m
CONFIG_USB_GSPCA_SPCA508=m
CONFIG_USB_GSPCA_SPCA561=m
CONFIG_USB_GSPCA_SQ905=m
CONFIG_USB_GSPCA_SQ905C=m
CONFIG_USB_GSPCA_SQ930X=m
CONFIG_USB_GSPCA_STK014=m
CONFIG_USB_GSPCA_STK1135=m
CONFIG_USB_GSPCA_STV0680=m
CONFIG_USB_GSPCA_SUNPLUS=m
CONFIG_USB_GSPCA_T613=m
CONFIG_USB_GSPCA_TOPRO=m
CONFIG_USB_GSPCA_TOUPTEK=m
CONFIG_USB_GSPCA_TV8532=m
CONFIG_USB_GSPCA_VC032X=m
CONFIG_USB_GSPCA_VICAM=m
CONFIG_USB_GSPCA_XIRLINK_CIT=m
CONFIG_USB_GSPCA_ZC3XX=m
CONFIG_USB_GL860=m
CONFIG_USB_M5602=m
CONFIG_USB_STV06XX=m
CONFIG_USB_PWC=m
# CONFIG_USB_PWC_DEBUG is not set
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_USB_S2255=m
CONFIG_VIDEO_USBTV=m
CONFIG_USB_VIDEO_CLASS=m
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y

#
# Analog TV USB devices
#
CONFIG_VIDEO_GO7007=m
CONFIG_VIDEO_GO7007_USB=m
CONFIG_VIDEO_GO7007_LOADER=m
CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
CONFIG_VIDEO_HDPVR=m
CONFIG_VIDEO_PVRUSB2=m
CONFIG_VIDEO_PVRUSB2_SYSFS=y
CONFIG_VIDEO_PVRUSB2_DVB=y
# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
CONFIG_VIDEO_STK1160_COMMON=m
CONFIG_VIDEO_STK1160=m

#
# Analog/digital TV USB devices
#
CONFIG_VIDEO_AU0828=m
CONFIG_VIDEO_AU0828_V4L2=y
CONFIG_VIDEO_AU0828_RC=y
CONFIG_VIDEO_CX231XX=m
CONFIG_VIDEO_CX231XX_RC=y
CONFIG_VIDEO_CX231XX_ALSA=m
CONFIG_VIDEO_CX231XX_DVB=m

#
# Digital TV USB devices
#
CONFIG_DVB_AS102=m
CONFIG_DVB_B2C2_FLEXCOP_USB=m
# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
CONFIG_DVB_USB_V2=m
CONFIG_DVB_USB_AF9015=m
CONFIG_DVB_USB_AF9035=m
CONFIG_DVB_USB_ANYSEE=m
CONFIG_DVB_USB_AU6610=m
CONFIG_DVB_USB_AZ6007=m
CONFIG_DVB_USB_CE6230=m
CONFIG_DVB_USB_DVBSKY=m
CONFIG_DVB_USB_EC168=m
CONFIG_DVB_USB_GL861=m
CONFIG_DVB_USB_LME2510=m
CONFIG_DVB_USB_MXL111SF=m
CONFIG_DVB_USB_RTL28XXU=m
CONFIG_DVB_USB_ZD1301=m
CONFIG_DVB_USB=m
# CONFIG_DVB_USB_DEBUG is not set
CONFIG_DVB_USB_A800=m
CONFIG_DVB_USB_AF9005=m
CONFIG_DVB_USB_AF9005_REMOTE=m
CONFIG_DVB_USB_AZ6027=m
CONFIG_DVB_USB_CINERGY_T2=m
CONFIG_DVB_USB_CXUSB=m
# CONFIG_DVB_USB_CXUSB_ANALOG is not set
CONFIG_DVB_USB_DIB0700=m
CONFIG_DVB_USB_DIB3000MC=m
CONFIG_DVB_USB_DIBUSB_MB=m
# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
CONFIG_DVB_USB_DIBUSB_MC=m
CONFIG_DVB_USB_DIGITV=m
CONFIG_DVB_USB_DTT200U=m
CONFIG_DVB_USB_DTV5100=m
CONFIG_DVB_USB_DW2102=m
CONFIG_DVB_USB_GP8PSK=m
CONFIG_DVB_USB_M920X=m
CONFIG_DVB_USB_NOVA_T_USB2=m
CONFIG_DVB_USB_OPERA1=m
CONFIG_DVB_USB_PCTV452E=m
CONFIG_DVB_USB_TECHNISAT_USB2=m
CONFIG_DVB_USB_TTUSB2=m
CONFIG_DVB_USB_UMT_010=m
CONFIG_DVB_USB_VP702X=m
CONFIG_DVB_USB_VP7045=m
CONFIG_SMS_USB_DRV=m
CONFIG_DVB_TTUSB_BUDGET=m
CONFIG_DVB_TTUSB_DEC=m

#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=m
CONFIG_VIDEO_EM28XX_V4L2=m
CONFIG_VIDEO_EM28XX_ALSA=m
CONFIG_VIDEO_EM28XX_DVB=m
CONFIG_VIDEO_EM28XX_RC=m

#
# Software defined radio USB devices
#
CONFIG_USB_AIRSPY=m
CONFIG_USB_HACKRF=m
# CONFIG_USB_MSI2500 is not set
CONFIG_MEDIA_PCI_SUPPORT=y

#
# Media capture support
#
CONFIG_VIDEO_SOLO6X10=m
# CONFIG_VIDEO_TW5864 is not set
CONFIG_VIDEO_TW68=m
# CONFIG_VIDEO_TW686X is not set
# CONFIG_VIDEO_ZORAN is not set

#
# Media capture/analog TV support
#
CONFIG_VIDEO_DT3155=m
CONFIG_VIDEO_IVTV=m
CONFIG_VIDEO_IVTV_ALSA=m
CONFIG_VIDEO_FB_IVTV=m
CONFIG_VIDEO_HEXIUM_GEMINI=m
CONFIG_VIDEO_HEXIUM_ORION=m
CONFIG_VIDEO_MXB=m

#
# Media capture/analog/hybrid TV support
#
CONFIG_VIDEO_BT848=m
CONFIG_DVB_BT8XX=m
CONFIG_VIDEO_CX18=m
CONFIG_VIDEO_CX18_ALSA=m
CONFIG_VIDEO_CX23885=m
CONFIG_MEDIA_ALTERA_CI=m
CONFIG_VIDEO_CX25821=m
CONFIG_VIDEO_CX25821_ALSA=m
CONFIG_VIDEO_CX88=m
CONFIG_VIDEO_CX88_ALSA=m
CONFIG_VIDEO_CX88_BLACKBIRD=m
CONFIG_VIDEO_CX88_DVB=m
CONFIG_VIDEO_CX88_ENABLE_VP3054=y
CONFIG_VIDEO_CX88_VP3054=m
CONFIG_VIDEO_CX88_MPEG=m
CONFIG_VIDEO_SAA7134=m
CONFIG_VIDEO_SAA7134_ALSA=m
CONFIG_VIDEO_SAA7134_RC=y
CONFIG_VIDEO_SAA7134_DVB=m
CONFIG_VIDEO_SAA7134_GO7007=m
CONFIG_VIDEO_SAA7164=m

#
# Media digital TV PCI Adapters
#
CONFIG_DVB_B2C2_FLEXCOP_PCI=m
# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
CONFIG_DVB_DDBRIDGE=m
# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set
CONFIG_DVB_DM1105=m
CONFIG_MANTIS_CORE=m
CONFIG_DVB_MANTIS=m
CONFIG_DVB_HOPPER=m
# CONFIG_DVB_NETUP_UNIDVB is not set
CONFIG_DVB_NGENE=m
CONFIG_DVB_PLUTO2=m
CONFIG_DVB_PT1=m
CONFIG_DVB_PT3=m
CONFIG_DVB_SMIPCIE=m
CONFIG_DVB_BUDGET_CORE=m
CONFIG_DVB_BUDGET=m
CONFIG_DVB_BUDGET_CI=m
CONFIG_DVB_BUDGET_AV=m
CONFIG_RADIO_ADAPTERS=m
CONFIG_RADIO_MAXIRADIO=m
CONFIG_RADIO_SAA7706H=m
CONFIG_RADIO_SHARK=m
CONFIG_RADIO_SHARK2=m
CONFIG_RADIO_SI4713=m
CONFIG_RADIO_TEA575X=m
CONFIG_RADIO_TEA5764=m
CONFIG_RADIO_TEF6862=m
CONFIG_RADIO_WL1273=m
CONFIG_USB_DSBR=m
CONFIG_USB_KEENE=m
CONFIG_USB_MA901=m
CONFIG_USB_MR800=m
CONFIG_USB_RAREMONO=m
CONFIG_RADIO_SI470X=m
CONFIG_USB_SI470X=m
CONFIG_I2C_SI470X=m
CONFIG_USB_SI4713=m
CONFIG_PLATFORM_SI4713=m
CONFIG_I2C_SI4713=m
CONFIG_MEDIA_PLATFORM_DRIVERS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
# CONFIG_SDR_PLATFORM_DRIVERS is not set
# CONFIG_DVB_PLATFORM_DRIVERS is not set
CONFIG_V4L_MEM2MEM_DRIVERS=y
# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
# CONFIG_VIDEO_MUX is not set

#
# Allegro DVT media platform drivers
#

#
# Amlogic media platform drivers
#

#
# Amphion drivers
#

#
# Aspeed media platform drivers
#

#
# Atmel media platform drivers
#

#
# Cadence media platform drivers
#
# CONFIG_VIDEO_CADENCE_CSI2RX is not set
# CONFIG_VIDEO_CADENCE_CSI2TX is not set

#
# Chips&Media media platform drivers
#

#
# Intel media platform drivers
#

#
# Marvell media platform drivers
#
# CONFIG_VIDEO_CAFE_CCIC is not set

#
# Mediatek media platform drivers
#

#
# Microchip Technology, Inc. media platform drivers
#

#
# NVidia media platform drivers
#

#
# NXP media platform drivers
#

#
# Qualcomm media platform drivers
#

#
# Renesas media platform drivers
#

#
# Rockchip media platform drivers
#

#
# Samsung media platform drivers
#

#
# STMicroelectronics media platform drivers
#

#
# Sunxi media platform drivers
#
# CONFIG_VIDEO_SUN4I_CSI is not set
CONFIG_VIDEO_SUN6I_CSI=m
# CONFIG_VIDEO_SUN6I_MIPI_CSI2 is not set
# CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2 is not set
CONFIG_VIDEO_SUN8I_DEINTERLACE=m
# CONFIG_VIDEO_SUN8I_ROTATE is not set

#
# Texas Instruments drivers
#

#
# Verisilicon media platform drivers
#
CONFIG_VIDEO_HANTRO=m
CONFIG_VIDEO_HANTRO_SUNXI=y

#
# VIA media platform drivers
#

#
# Xilinx media platform drivers
#
# CONFIG_VIDEO_XILINX is not set

#
# MMC/SDIO DVB adapters
#
CONFIG_SMS_SDIO_DRV=m
# CONFIG_V4L_TEST_DRIVERS is not set
# CONFIG_DVB_TEST_DRIVERS is not set
CONFIG_MEDIA_COMMON_OPTIONS=y

#
# common driver options
#
CONFIG_CYPRESS_FIRMWARE=m
CONFIG_TTPCI_EEPROM=m
CONFIG_UVC_COMMON=m
CONFIG_VIDEO_CX2341X=m
CONFIG_VIDEO_TVEEPROM=m
CONFIG_DVB_B2C2_FLEXCOP=m
CONFIG_VIDEO_SAA7146=m
CONFIG_VIDEO_SAA7146_VV=m
CONFIG_SMS_SIANO_MDTV=m
CONFIG_SMS_SIANO_RC=y
# CONFIG_SMS_SIANO_DEBUGFS is not set
CONFIG_VIDEOBUF2_CORE=m
CONFIG_VIDEOBUF2_V4L2=m
CONFIG_VIDEOBUF2_MEMOPS=m
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=m
CONFIG_VIDEOBUF2_DMA_SG=m
CONFIG_VIDEOBUF2_DVB=m
# end of Media drivers

#
# Media ancillary drivers
#
CONFIG_MEDIA_ATTACH=y

#
# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
#
CONFIG_VIDEO_IR_I2C=m

#
# Camera sensor devices
#
# CONFIG_VIDEO_AR0521 is not set
# CONFIG_VIDEO_HI556 is not set
# CONFIG_VIDEO_HI846 is not set
# CONFIG_VIDEO_HI847 is not set
# CONFIG_VIDEO_IMX208 is not set
# CONFIG_VIDEO_IMX214 is not set
CONFIG_VIDEO_IMX219=m
# CONFIG_VIDEO_IMX258 is not set
# CONFIG_VIDEO_IMX274 is not set
# CONFIG_VIDEO_IMX290 is not set
# CONFIG_VIDEO_IMX296 is not set
# CONFIG_VIDEO_IMX319 is not set
# CONFIG_VIDEO_IMX334 is not set
# CONFIG_VIDEO_IMX335 is not set
# CONFIG_VIDEO_IMX355 is not set
# CONFIG_VIDEO_IMX412 is not set
# CONFIG_VIDEO_IMX415 is not set
# CONFIG_VIDEO_MT9M001 is not set
# CONFIG_VIDEO_MT9M111 is not set
# CONFIG_VIDEO_MT9P031 is not set
# CONFIG_VIDEO_MT9T112 is not set
CONFIG_VIDEO_MT9V011=m
# CONFIG_VIDEO_MT9V032 is not set
# CONFIG_VIDEO_MT9V111 is not set
# CONFIG_VIDEO_OG01A1B is not set
# CONFIG_VIDEO_OV02A10 is not set
# CONFIG_VIDEO_OV08D10 is not set
# CONFIG_VIDEO_OV08X40 is not set
# CONFIG_VIDEO_OV13858 is not set
# CONFIG_VIDEO_OV13B10 is not set
CONFIG_VIDEO_OV2640=m
# CONFIG_VIDEO_OV2659 is not set
# CONFIG_VIDEO_OV2680 is not set
# CONFIG_VIDEO_OV2685 is not set
# CONFIG_VIDEO_OV2740 is not set
# CONFIG_VIDEO_OV4689 is not set
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
# CONFIG_VIDEO_OV5647 is not set
# CONFIG_VIDEO_OV5648 is not set
# CONFIG_VIDEO_OV5670 is not set
# CONFIG_VIDEO_OV5675 is not set
# CONFIG_VIDEO_OV5693 is not set
# CONFIG_VIDEO_OV5695 is not set
# CONFIG_VIDEO_OV6650 is not set
# CONFIG_VIDEO_OV7251 is not set
CONFIG_VIDEO_OV7640=m
# CONFIG_VIDEO_OV7670 is not set
# CONFIG_VIDEO_OV772X is not set
# CONFIG_VIDEO_OV7740 is not set
# CONFIG_VIDEO_OV8856 is not set
# CONFIG_VIDEO_OV8858 is not set
# CONFIG_VIDEO_OV8865 is not set
# CONFIG_VIDEO_OV9282 is not set
# CONFIG_VIDEO_OV9640 is not set
# CONFIG_VIDEO_OV9650 is not set
# CONFIG_VIDEO_OV9734 is not set
# CONFIG_VIDEO_RDACM20 is not set
# CONFIG_VIDEO_RDACM21 is not set
# CONFIG_VIDEO_RJ54N1 is not set
# CONFIG_VIDEO_S5C73M3 is not set
# CONFIG_VIDEO_S5K5BAF is not set
# CONFIG_VIDEO_S5K6A3 is not set
# CONFIG_VIDEO_ST_VGXY61 is not set
# CONFIG_VIDEO_CCS is not set
# CONFIG_VIDEO_ET8EK8 is not set
# end of Camera sensor devices

#
# Lens drivers
#
# CONFIG_VIDEO_AD5820 is not set
# CONFIG_VIDEO_AK7375 is not set
# CONFIG_VIDEO_DW9714 is not set
# CONFIG_VIDEO_DW9768 is not set
# CONFIG_VIDEO_DW9807_VCM is not set
# end of Lens drivers

#
# Flash devices
#
# CONFIG_VIDEO_ADP1653 is not set
# CONFIG_VIDEO_LM3560 is not set
# CONFIG_VIDEO_LM3646 is not set
# end of Flash devices

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_CS3308=m
CONFIG_VIDEO_CS5345=m
CONFIG_VIDEO_CS53L32A=m
CONFIG_VIDEO_MSP3400=m
CONFIG_VIDEO_SONY_BTF_MPX=m
# CONFIG_VIDEO_TDA1997X is not set
CONFIG_VIDEO_TDA7432=m
CONFIG_VIDEO_TDA9840=m
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
# CONFIG_VIDEO_TLV320AIC23B is not set
CONFIG_VIDEO_TVAUDIO=m
CONFIG_VIDEO_UDA1342=m
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_WM8739=m
CONFIG_VIDEO_WM8775=m
# end of Audio decoders, processors and mixers

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders

#
# Video decoders
#
# CONFIG_VIDEO_ADV7180 is not set
# CONFIG_VIDEO_ADV7183 is not set
# CONFIG_VIDEO_ADV748X is not set
# CONFIG_VIDEO_ADV7604 is not set
# CONFIG_VIDEO_ADV7842 is not set
# CONFIG_VIDEO_BT819 is not set
# CONFIG_VIDEO_BT856 is not set
# CONFIG_VIDEO_BT866 is not set
# CONFIG_VIDEO_ISL7998X is not set
# CONFIG_VIDEO_KS0127 is not set
# CONFIG_VIDEO_MAX9286 is not set
# CONFIG_VIDEO_ML86V7667 is not set
# CONFIG_VIDEO_SAA7110 is not set
CONFIG_VIDEO_SAA711X=m
# CONFIG_VIDEO_TC358743 is not set
# CONFIG_VIDEO_TC358746 is not set
# CONFIG_VIDEO_TVP514X is not set
CONFIG_VIDEO_TVP5150=m
# CONFIG_VIDEO_TVP7002 is not set
CONFIG_VIDEO_TW2804=m
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=m
# CONFIG_VIDEO_TW9910 is not set
# CONFIG_VIDEO_VPX3220 is not set

#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=m
CONFIG_VIDEO_CX25840=m
# end of Video decoders

#
# Video encoders
#
# CONFIG_VIDEO_ADV7170 is not set
# CONFIG_VIDEO_ADV7175 is not set
# CONFIG_VIDEO_ADV7343 is not set
# CONFIG_VIDEO_ADV7393 is not set
# CONFIG_VIDEO_AK881X is not set
CONFIG_VIDEO_SAA7127=m
# CONFIG_VIDEO_SAA7185 is not set
# CONFIG_VIDEO_THS8200 is not set
# end of Video encoders

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
CONFIG_VIDEO_UPD64083=m
# end of Video improvement chips

#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips

#
# SDR tuner chips
#
# CONFIG_SDR_MAX2175 is not set
# end of SDR tuner chips

#
# Miscellaneous helper chips
#
# CONFIG_VIDEO_I2C is not set
CONFIG_VIDEO_M52790=m
# CONFIG_VIDEO_ST_MIPID02 is not set
# CONFIG_VIDEO_THS7303 is not set
# end of Miscellaneous helper chips

#
# Media SPI Adapters
#
# CONFIG_CXD2880_SPI_DRV is not set
# CONFIG_VIDEO_GS1662 is not set
# end of Media SPI Adapters

CONFIG_MEDIA_TUNER=m

#
# Customize TV tuners
#
CONFIG_MEDIA_TUNER_E4000=m
CONFIG_MEDIA_TUNER_FC0011=m
CONFIG_MEDIA_TUNER_FC0012=m
CONFIG_MEDIA_TUNER_FC0013=m
CONFIG_MEDIA_TUNER_FC2580=m
CONFIG_MEDIA_TUNER_IT913X=m
CONFIG_MEDIA_TUNER_M88RS6000T=m
CONFIG_MEDIA_TUNER_MAX2165=m
CONFIG_MEDIA_TUNER_MC44S803=m
# CONFIG_MEDIA_TUNER_MSI001 is not set
CONFIG_MEDIA_TUNER_MT2060=m
CONFIG_MEDIA_TUNER_MT2063=m
CONFIG_MEDIA_TUNER_MT20XX=m
CONFIG_MEDIA_TUNER_MT2131=m
CONFIG_MEDIA_TUNER_MT2266=m
CONFIG_MEDIA_TUNER_MXL301RF=m
CONFIG_MEDIA_TUNER_MXL5005S=m
CONFIG_MEDIA_TUNER_MXL5007T=m
CONFIG_MEDIA_TUNER_QM1D1B0004=m
CONFIG_MEDIA_TUNER_QM1D1C0042=m
CONFIG_MEDIA_TUNER_QT1010=m
CONFIG_MEDIA_TUNER_R820T=m
CONFIG_MEDIA_TUNER_SI2157=m
CONFIG_MEDIA_TUNER_SIMPLE=m
CONFIG_MEDIA_TUNER_TDA18212=m
CONFIG_MEDIA_TUNER_TDA18218=m
CONFIG_MEDIA_TUNER_TDA18250=m
CONFIG_MEDIA_TUNER_TDA18271=m
CONFIG_MEDIA_TUNER_TDA827X=m
CONFIG_MEDIA_TUNER_TDA8290=m
CONFIG_MEDIA_TUNER_TDA9887=m
CONFIG_MEDIA_TUNER_TEA5761=m
CONFIG_MEDIA_TUNER_TEA5767=m
CONFIG_MEDIA_TUNER_TUA9001=m
CONFIG_MEDIA_TUNER_XC2028=m
CONFIG_MEDIA_TUNER_XC4000=m
CONFIG_MEDIA_TUNER_XC5000=m
# end of Customize TV tuners

#
# Customise DVB Frontends
#

#
# Multistandard (satellite) frontends
#
CONFIG_DVB_M88DS3103=m
CONFIG_DVB_MXL5XX=m
CONFIG_DVB_STB0899=m
CONFIG_DVB_STB6100=m
CONFIG_DVB_STV090x=m
CONFIG_DVB_STV0910=m
CONFIG_DVB_STV6110x=m
CONFIG_DVB_STV6111=m

#
# Multistandard (cable + terrestrial) frontends
#
CONFIG_DVB_DRXK=m
CONFIG_DVB_MN88472=m
CONFIG_DVB_MN88473=m
CONFIG_DVB_SI2165=m
CONFIG_DVB_TDA18271C2DD=m

#
# DVB-S (satellite) frontends
#
CONFIG_DVB_CX24110=m
CONFIG_DVB_CX24116=m
CONFIG_DVB_CX24117=m
CONFIG_DVB_CX24120=m
CONFIG_DVB_CX24123=m
CONFIG_DVB_DS3000=m
CONFIG_DVB_MB86A16=m
CONFIG_DVB_MT312=m
CONFIG_DVB_S5H1420=m
CONFIG_DVB_SI21XX=m
CONFIG_DVB_STB6000=m
CONFIG_DVB_STV0288=m
CONFIG_DVB_STV0299=m
CONFIG_DVB_STV0900=m
CONFIG_DVB_STV6110=m
CONFIG_DVB_TDA10071=m
CONFIG_DVB_TDA10086=m
CONFIG_DVB_TDA8083=m
CONFIG_DVB_TDA8261=m
CONFIG_DVB_TDA826X=m
CONFIG_DVB_TS2020=m
CONFIG_DVB_TUA6100=m
CONFIG_DVB_TUNER_CX24113=m
CONFIG_DVB_TUNER_ITD1000=m
CONFIG_DVB_VES1X93=m
CONFIG_DVB_ZL10036=m
CONFIG_DVB_ZL10039=m

#
# DVB-T (terrestrial) frontends
#
CONFIG_DVB_AF9013=m
CONFIG_DVB_AS102_FE=m
CONFIG_DVB_CX22700=m
CONFIG_DVB_CX22702=m
CONFIG_DVB_CXD2820R=m
CONFIG_DVB_CXD2841ER=m
CONFIG_DVB_DIB3000MB=m
CONFIG_DVB_DIB3000MC=m
CONFIG_DVB_DIB7000M=m
CONFIG_DVB_DIB7000P=m
# CONFIG_DVB_DIB9000 is not set
CONFIG_DVB_DRXD=m
CONFIG_DVB_EC100=m
CONFIG_DVB_GP8PSK_FE=m
CONFIG_DVB_L64781=m
CONFIG_DVB_MT352=m
CONFIG_DVB_NXT6000=m
CONFIG_DVB_RTL2830=m
CONFIG_DVB_RTL2832=m
CONFIG_DVB_RTL2832_SDR=m
# CONFIG_DVB_S5H1432 is not set
CONFIG_DVB_SI2168=m
CONFIG_DVB_SP887X=m
CONFIG_DVB_STV0367=m
CONFIG_DVB_TDA10048=m
CONFIG_DVB_TDA1004X=m
CONFIG_DVB_ZD1301_DEMOD=m
CONFIG_DVB_ZL10353=m
# CONFIG_DVB_CXD2880 is not set

#
# DVB-C (cable) frontends
#
CONFIG_DVB_STV0297=m
CONFIG_DVB_TDA10021=m
CONFIG_DVB_TDA10023=m
CONFIG_DVB_VES1820=m

#
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
#
CONFIG_DVB_AU8522=m
CONFIG_DVB_AU8522_DTV=m
CONFIG_DVB_AU8522_V4L=m
CONFIG_DVB_BCM3510=m
CONFIG_DVB_LG2160=m
CONFIG_DVB_LGDT3305=m
CONFIG_DVB_LGDT3306A=m
CONFIG_DVB_LGDT330X=m
CONFIG_DVB_MXL692=m
CONFIG_DVB_NXT200X=m
CONFIG_DVB_OR51132=m
CONFIG_DVB_OR51211=m
CONFIG_DVB_S5H1409=m
CONFIG_DVB_S5H1411=m

#
# ISDB-T (terrestrial) frontends
#
CONFIG_DVB_DIB8000=m
CONFIG_DVB_MB86A20S=m
CONFIG_DVB_S921=m

#
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
#
# CONFIG_DVB_MN88443X is not set
CONFIG_DVB_TC90522=m

#
# Digital terrestrial only tuners/PLL
#
CONFIG_DVB_PLL=m
CONFIG_DVB_TUNER_DIB0070=m
CONFIG_DVB_TUNER_DIB0090=m

#
# SEC control devices for DVB-S
#
CONFIG_DVB_A8293=m
CONFIG_DVB_AF9033=m
# CONFIG_DVB_ASCOT2E is not set
CONFIG_DVB_ATBM8830=m
# CONFIG_DVB_HELENE is not set
# CONFIG_DVB_HORUS3A is not set
CONFIG_DVB_ISL6405=m
CONFIG_DVB_ISL6421=m
CONFIG_DVB_ISL6423=m
CONFIG_DVB_IX2505V=m
# CONFIG_DVB_LGS8GL5 is not set
CONFIG_DVB_LGS8GXX=m
CONFIG_DVB_LNBH25=m
# CONFIG_DVB_LNBH29 is not set
CONFIG_DVB_LNBP21=m
CONFIG_DVB_LNBP22=m
CONFIG_DVB_M88RS2000=m
CONFIG_DVB_TDA665x=m
CONFIG_DVB_DRX39XYJ=m

#
# Common Interface (EN50221) controller drivers
#
CONFIG_DVB_CXD2099=m
CONFIG_DVB_SP2=m
# end of Customise DVB Frontends

#
# Tools to develop new frontends
#
CONFIG_DVB_DUMMY_FE=m
# end of Media ancillary drivers

#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
CONFIG_VIDEO_CMDLINE=y
CONFIG_VIDEO_NOMODESET=y
CONFIG_DRM=m
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_KMS_HELPER=m
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
CONFIG_DRM_LOAD_EDID_FIRMWARE=y
CONFIG_DRM_DP_AUX_BUS=m
CONFIG_DRM_DISPLAY_HELPER=m
CONFIG_DRM_DISPLAY_DP_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_TTM=m
CONFIG_DRM_VRAM_HELPER=m
CONFIG_DRM_TTM_HELPER=m
CONFIG_DRM_GEM_DMA_HELPER=m
CONFIG_DRM_GEM_SHMEM_HELPER=m
CONFIG_DRM_SUBALLOC_HELPER=m
CONFIG_DRM_SCHED=m

#
# I2C encoder or helper chips
#
CONFIG_DRM_I2C_CH7006=m
CONFIG_DRM_I2C_SIL164=m
CONFIG_DRM_I2C_NXP_TDA998X=m
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips

#
# ARM devices
#
CONFIG_DRM_HDLCD=m
# CONFIG_DRM_HDLCD_SHOW_UNDERRUN is not set
CONFIG_DRM_MALI_DISPLAY=m
# CONFIG_DRM_KOMEDA is not set
# end of ARM devices

CONFIG_DRM_RADEON=m
CONFIG_DRM_RADEON_USERPTR=y
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
CONFIG_DRM_VGEM=m
# CONFIG_DRM_VKMS is not set
# CONFIG_DRM_VMWGFX is not set
CONFIG_DRM_UDL=m
CONFIG_DRM_AST=m
CONFIG_DRM_MGAG200=m
CONFIG_DRM_SUN4I=m
CONFIG_DRM_SUN6I_DSI=m
CONFIG_DRM_SUN8I_DW_HDMI=m
CONFIG_DRM_SUN8I_MIXER=m
CONFIG_DRM_SUN8I_TCON_TOP=m
CONFIG_DRM_QXL=m
CONFIG_DRM_VIRTIO_GPU=m
# CONFIG_DRM_VIRTIO_GPU_KMS is not set
CONFIG_DRM_PANEL=y

#
# Display Panels
#
# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set
# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
# CONFIG_DRM_PANEL_DSI_CM is not set
# CONFIG_DRM_PANEL_LVDS is not set
CONFIG_DRM_PANEL_SIMPLE=m
# CONFIG_DRM_PANEL_EDP is not set
# CONFIG_DRM_PANEL_EBBG_FT8719 is not set
# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
# CONFIG_DRM_PANEL_JDI_R63452 is not set
# CONFIG_DRM_PANEL_KHADAS_TS050 is not set
# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
# CONFIG_DRM_PANEL_LG_LG4573 is not set
# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set
# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set
# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set
# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set
# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_CHIPONE_ICN6211 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
# CONFIG_DRM_CROS_EC_ANX7688 is not set
CONFIG_DRM_DISPLAY_CONNECTOR=m
# CONFIG_DRM_ITE_IT6505 is not set
# CONFIG_DRM_LONTIUM_LT8912B is not set
# CONFIG_DRM_LONTIUM_LT9211 is not set
CONFIG_DRM_LONTIUM_LT9611=m
# CONFIG_DRM_LONTIUM_LT9611UXC is not set
# CONFIG_DRM_ITE_IT66121 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
CONFIG_DRM_NWL_MIPI_DSI=m
CONFIG_DRM_NXP_PTN3460=m
CONFIG_DRM_PARADE_PS8622=m
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_SAMSUNG_DSIM is not set
CONFIG_DRM_SIL_SII8620=m
CONFIG_DRM_SII902X=m
# CONFIG_DRM_SII9234 is not set
CONFIG_DRM_SIMPLE_BRIDGE=m
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
CONFIG_DRM_TOSHIBA_TC358767=m
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_DLPC3433 is not set
CONFIG_DRM_TI_TFP410=m
# CONFIG_DRM_TI_SN65DSI83 is not set
CONFIG_DRM_TI_SN65DSI86=m
# CONFIG_DRM_TI_TPD12S015 is not set
CONFIG_DRM_ANALOGIX_ANX6345=m
CONFIG_DRM_ANALOGIX_ANX78XX=m
CONFIG_DRM_ANALOGIX_DP=m
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
CONFIG_DRM_I2C_ADV7511=m
CONFIG_DRM_I2C_ADV7511_AUDIO=y
CONFIG_DRM_I2C_ADV7511_CEC=y
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=m
# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set
CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
CONFIG_DRM_DW_HDMI_CEC=m
# end of Display Interface Bridges

CONFIG_DRM_ETNAVIV=m
CONFIG_DRM_ETNAVIV_THERMAL=y
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
# CONFIG_DRM_LOGICVC is not set
# CONFIG_DRM_ARCPGU is not set
CONFIG_DRM_BOCHS=m
CONFIG_DRM_CIRRUS_QEMU=m
# CONFIG_DRM_GM12U320 is not set
# CONFIG_DRM_PANEL_MIPI_DBI is not set
# CONFIG_DRM_SIMPLEDRM is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9163 is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
CONFIG_DRM_PL111=m
CONFIG_DRM_LIMA=m
CONFIG_DRM_PANFROST=m
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_GUD is not set
# CONFIG_DRM_SSD130X is not set
CONFIG_DRM_LEGACY=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y

#
# Frame buffer Devices
#
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=m
CONFIG_FB_SYS_COPYAREA=m
CONFIG_FB_SYS_IMAGEBLIT=m
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=m
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_BACKLIGHT=m
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y

#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_ARMCLCD is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_UVESA is not set
CONFIG_FB_EFI=y
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SM501 is not set
# CONFIG_FB_SMSCUFX is not set
CONFIG_FB_UDL=m
# CONFIG_FB_IBM_GXT4500 is not set
CONFIG_FB_VIRTUAL=m
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
CONFIG_FB_SIMPLE=y
CONFIG_FB_SSD1307=m
# CONFIG_FB_SM712 is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_L4F00242T03 is not set
# CONFIG_LCD_LMS283GF05 is not set
# CONFIG_LCD_LTV350QV is not set
# CONFIG_LCD_ILI922X is not set
# CONFIG_LCD_ILI9320 is not set
# CONFIG_LCD_TDO24M is not set
# CONFIG_LCD_VGG2432A4 is not set
CONFIG_LCD_PLATFORM=m
# CONFIG_LCD_AMS369FG06 is not set
# CONFIG_LCD_LMS501KF03 is not set
# CONFIG_LCD_HX8357 is not set
# CONFIG_LCD_OTM3225A is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_KTD253 is not set
# CONFIG_BACKLIGHT_KTZ8866 is not set
CONFIG_BACKLIGHT_PWM=m
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
CONFIG_BACKLIGHT_LP855X=m
CONFIG_BACKLIGHT_GPIO=m
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# CONFIG_BACKLIGHT_LED is not set
# end of Backlight & LCD device support

CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
# end of Console display driver support

CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_LOGO_LINUX_CLUT224=y
# end of Graphics support

# CONFIG_DRM_ACCEL is not set
CONFIG_SOUND=y
CONFIG_SOUND_OSS_CORE=y
CONFIG_SOUND_OSS_CORE_PRECLAIM=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=m
CONFIG_SND_SEQ_DEVICE=m
CONFIG_SND_RAWMIDI=m
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=m
CONFIG_SND_PCM_OSS=m
CONFIG_SND_PCM_OSS_PLUGINS=y
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=m
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_CTL_FAST_LOOKUP is not set
# CONFIG_SND_DEBUG is not set
# CONFIG_SND_CTL_INPUT_VALIDATION is not set
CONFIG_SND_VMASTER=y
CONFIG_SND_CTL_LED=m
CONFIG_SND_SEQUENCER=m
CONFIG_SND_SEQ_DUMMY=m
CONFIG_SND_SEQUENCER_OSS=m
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
CONFIG_SND_SEQ_MIDI_EVENT=m
CONFIG_SND_SEQ_MIDI=m
CONFIG_SND_SEQ_MIDI_EMUL=m
CONFIG_SND_SEQ_VIRMIDI=m
CONFIG_SND_MPU401_UART=m
CONFIG_SND_OPL3_LIB=m
CONFIG_SND_OPL3_LIB_SEQ=m
CONFIG_SND_VX_LIB=m
CONFIG_SND_AC97_CODEC=m
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
CONFIG_SND_VIRMIDI=m
CONFIG_SND_MTPAV=m
CONFIG_SND_SERIAL_U16550=m
# CONFIG_SND_SERIAL_GENERIC is not set
CONFIG_SND_MPU401=m
CONFIG_SND_AC97_POWER_SAVE=y
CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
CONFIG_SND_PCI=y
CONFIG_SND_AD1889=m
# CONFIG_SND_ALS300 is not set
# CONFIG_SND_ALI5451 is not set
CONFIG_SND_ATIIXP=m
CONFIG_SND_ATIIXP_MODEM=m
CONFIG_SND_AU8810=m
CONFIG_SND_AU8820=m
CONFIG_SND_AU8830=m
# CONFIG_SND_AW2 is not set
# CONFIG_SND_AZT3328 is not set
CONFIG_SND_BT87X=m
# CONFIG_SND_BT87X_OVERCLOCK is not set
CONFIG_SND_CA0106=m
CONFIG_SND_CMIPCI=m
CONFIG_SND_OXYGEN_LIB=m
CONFIG_SND_OXYGEN=m
CONFIG_SND_CS4281=m
CONFIG_SND_CS46XX=m
CONFIG_SND_CS46XX_NEW_DSP=y
CONFIG_SND_CTXFI=m
CONFIG_SND_DARLA20=m
CONFIG_SND_GINA20=m
CONFIG_SND_LAYLA20=m
CONFIG_SND_DARLA24=m
CONFIG_SND_GINA24=m
CONFIG_SND_LAYLA24=m
CONFIG_SND_MONA=m
CONFIG_SND_MIA=m
CONFIG_SND_ECHO3G=m
CONFIG_SND_INDIGO=m
CONFIG_SND_INDIGOIO=m
CONFIG_SND_INDIGODJ=m
CONFIG_SND_INDIGOIOX=m
CONFIG_SND_INDIGODJX=m
# CONFIG_SND_EMU10K1 is not set
# CONFIG_SND_EMU10K1X is not set
CONFIG_SND_ENS1370=m
CONFIG_SND_ENS1371=m
# CONFIG_SND_ES1938 is not set
# CONFIG_SND_ES1968 is not set
CONFIG_SND_FM801=m
CONFIG_SND_FM801_TEA575X_BOOL=y
CONFIG_SND_HDSP=m
CONFIG_SND_HDSPM=m
# CONFIG_SND_ICE1712 is not set
CONFIG_SND_ICE1724=m
CONFIG_SND_INTEL8X0=m
CONFIG_SND_INTEL8X0M=m
CONFIG_SND_KORG1212=m
CONFIG_SND_LOLA=m
CONFIG_SND_LX6464ES=m
# CONFIG_SND_MAESTRO3 is not set
CONFIG_SND_MIXART=m
CONFIG_SND_NM256=m
CONFIG_SND_PCXHR=m
CONFIG_SND_RIPTIDE=m
CONFIG_SND_RME32=m
CONFIG_SND_RME96=m
CONFIG_SND_RME9652=m
# CONFIG_SND_SONICVIBES is not set
# CONFIG_SND_TRIDENT is not set
CONFIG_SND_VIA82XX=m
CONFIG_SND_VIA82XX_MODEM=m
CONFIG_SND_VIRTUOSO=m
CONFIG_SND_VX222=m
CONFIG_SND_YMFPCI=m

#
# HD-Audio
#
CONFIG_SND_HDA=m
CONFIG_SND_HDA_GENERIC_LEDS=y
CONFIG_SND_HDA_INTEL=m
CONFIG_SND_HDA_HWDEP=y
CONFIG_SND_HDA_RECONFIG=y
CONFIG_SND_HDA_INPUT_BEEP=y
CONFIG_SND_HDA_INPUT_BEEP_MODE=0
CONFIG_SND_HDA_PATCH_LOADER=y
# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
CONFIG_SND_HDA_CODEC_REALTEK=m
CONFIG_SND_HDA_CODEC_ANALOG=m
CONFIG_SND_HDA_CODEC_SIGMATEL=m
CONFIG_SND_HDA_CODEC_VIA=m
CONFIG_SND_HDA_CODEC_HDMI=m
CONFIG_SND_HDA_CODEC_CIRRUS=m
# CONFIG_SND_HDA_CODEC_CS8409 is not set
CONFIG_SND_HDA_CODEC_CONEXANT=m
CONFIG_SND_HDA_CODEC_CA0110=m
CONFIG_SND_HDA_CODEC_CA0132=m
CONFIG_SND_HDA_CODEC_CA0132_DSP=y
CONFIG_SND_HDA_CODEC_CMEDIA=m
CONFIG_SND_HDA_CODEC_SI3054=m
CONFIG_SND_HDA_GENERIC=m
CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
# CONFIG_SND_HDA_CTL_DEV_ID is not set
# end of HD-Audio

CONFIG_SND_HDA_CORE=m
CONFIG_SND_HDA_DSP_LOADER=y
CONFIG_SND_HDA_COMPONENT=y
CONFIG_SND_HDA_PREALLOC_SIZE=4096
CONFIG_SND_INTEL_NHLT=y
CONFIG_SND_INTEL_DSP_CONFIG=m
CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m
CONFIG_SND_SPI=y
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
# CONFIG_SND_BCD2000 is not set
CONFIG_SND_USB_LINE6=m
CONFIG_SND_USB_POD=m
CONFIG_SND_USB_PODHD=m
CONFIG_SND_USB_TONEPORT=m
CONFIG_SND_USB_VARIAX=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
# CONFIG_SND_SOC_ADI is not set
CONFIG_SND_SOC_AMD_ACP=m
# CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH is not set
# CONFIG_SND_SOC_AMD_CZ_RT5645_MACH is not set
# CONFIG_SND_SOC_AMD_ST_ES8336_MACH is not set
# CONFIG_SND_AMD_ACP_CONFIG is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
# CONFIG_SND_DESIGNWARE_I2S is not set

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
CONFIG_SND_SOC_FSL_ASRC=m
CONFIG_SND_SOC_FSL_SAI=m
# CONFIG_SND_SOC_FSL_MQS is not set
CONFIG_SND_SOC_FSL_AUDMIX=m
# CONFIG_SND_SOC_FSL_SSI is not set
CONFIG_SND_SOC_FSL_SPDIF=m
# CONFIG_SND_SOC_FSL_ESAI is not set
CONFIG_SND_SOC_FSL_MICFIL=m
CONFIG_SND_SOC_FSL_EASRC=m
# CONFIG_SND_SOC_FSL_XCVR is not set
CONFIG_SND_SOC_FSL_UTILS=m
# CONFIG_SND_SOC_FSL_RPMSG is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs

CONFIG_SND_I2S_HI6210_I2S=m
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set

#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support

#
# Allwinner SoC Audio support
#
CONFIG_SND_SUN4I_CODEC=m
CONFIG_SND_SUN8I_CODEC=m
CONFIG_SND_SUN8I_CODEC_ANALOG=m
CONFIG_SND_SUN50I_CODEC_ANALOG=m
CONFIG_SND_SUN4I_I2S=m
CONFIG_SND_SUN4I_SPDIF=m
# CONFIG_SND_SUN50I_DMIC is not set
CONFIG_SND_SUN9I_HDMI_AUDIO=m
CONFIG_SND_SUN8I_ADDA_PR_REGMAP=m
# end of Allwinner SoC Audio support

# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# CONFIG_SND_SOC_XTFPGA_I2S is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
# CONFIG_SND_SOC_AC97_CODEC is not set
# CONFIG_SND_SOC_ADAU1372_I2C is not set
# CONFIG_SND_SOC_ADAU1372_SPI is not set
# CONFIG_SND_SOC_ADAU1701 is not set
# CONFIG_SND_SOC_ADAU1761_I2C is not set
# CONFIG_SND_SOC_ADAU1761_SPI is not set
# CONFIG_SND_SOC_ADAU7002 is not set
# CONFIG_SND_SOC_ADAU7118_HW is not set
# CONFIG_SND_SOC_ADAU7118_I2C is not set
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_AK4118 is not set
# CONFIG_SND_SOC_AK4375 is not set
# CONFIG_SND_SOC_AK4458 is not set
# CONFIG_SND_SOC_AK4554 is not set
# CONFIG_SND_SOC_AK4613 is not set
# CONFIG_SND_SOC_AK4642 is not set
# CONFIG_SND_SOC_AK5386 is not set
# CONFIG_SND_SOC_AK5558 is not set
# CONFIG_SND_SOC_ALC5623 is not set
# CONFIG_SND_SOC_AW8738 is not set
# CONFIG_SND_SOC_AW88395 is not set
# CONFIG_SND_SOC_BD28623 is not set
# CONFIG_SND_SOC_BT_SCO is not set
CONFIG_SND_SOC_CROS_EC_CODEC=m
# CONFIG_SND_SOC_CS35L32 is not set
# CONFIG_SND_SOC_CS35L33 is not set
# CONFIG_SND_SOC_CS35L34 is not set
# CONFIG_SND_SOC_CS35L35 is not set
# CONFIG_SND_SOC_CS35L36 is not set
# CONFIG_SND_SOC_CS35L41_SPI is not set
# CONFIG_SND_SOC_CS35L41_I2C is not set
# CONFIG_SND_SOC_CS35L45_SPI is not set
# CONFIG_SND_SOC_CS35L45_I2C is not set
# CONFIG_SND_SOC_CS35L56_I2C is not set
# CONFIG_SND_SOC_CS35L56_SPI is not set
# CONFIG_SND_SOC_CS35L56_SDW is not set
# CONFIG_SND_SOC_CS42L42 is not set
# CONFIG_SND_SOC_CS42L42_SDW is not set
# CONFIG_SND_SOC_CS42L51_I2C is not set
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_CS42L73 is not set
# CONFIG_SND_SOC_CS42L83 is not set
# CONFIG_SND_SOC_CS4234 is not set
# CONFIG_SND_SOC_CS4265 is not set
# CONFIG_SND_SOC_CS4270 is not set
# CONFIG_SND_SOC_CS4271_I2C is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_CS42XX8_I2C is not set
# CONFIG_SND_SOC_CS43130 is not set
# CONFIG_SND_SOC_CS4341 is not set
# CONFIG_SND_SOC_CS4349 is not set
# CONFIG_SND_SOC_CS53L30 is not set
# CONFIG_SND_SOC_CX2072X is not set
# CONFIG_SND_SOC_DA7213 is not set
CONFIG_SND_SOC_DMIC=m
CONFIG_SND_SOC_HDMI_CODEC=m
# CONFIG_SND_SOC_ES7134 is not set
# CONFIG_SND_SOC_ES7241 is not set
# CONFIG_SND_SOC_ES8316 is not set
# CONFIG_SND_SOC_ES8326 is not set
CONFIG_SND_SOC_ES8328=m
CONFIG_SND_SOC_ES8328_I2C=m
CONFIG_SND_SOC_ES8328_SPI=m
# CONFIG_SND_SOC_GTM601 is not set
# CONFIG_SND_SOC_HDA is not set
# CONFIG_SND_SOC_ICS43432 is not set
# CONFIG_SND_SOC_IDT821034 is not set
# CONFIG_SND_SOC_INNO_RK3036 is not set
# CONFIG_SND_SOC_MAX98088 is not set
# CONFIG_SND_SOC_MAX98090 is not set
CONFIG_SND_SOC_MAX98357A=m
# CONFIG_SND_SOC_MAX98504 is not set
# CONFIG_SND_SOC_MAX9867 is not set
CONFIG_SND_SOC_MAX98927=m
# CONFIG_SND_SOC_MAX98520 is not set
# CONFIG_SND_SOC_MAX98363 is not set
# CONFIG_SND_SOC_MAX98373_I2C is not set
# CONFIG_SND_SOC_MAX98373_SDW is not set
# CONFIG_SND_SOC_MAX98390 is not set
# CONFIG_SND_SOC_MAX98396 is not set
# CONFIG_SND_SOC_MAX9860 is not set
CONFIG_SND_SOC_MSM8916_WCD_ANALOG=y
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y
# CONFIG_SND_SOC_PCM1681 is not set
# CONFIG_SND_SOC_PCM1789_I2C is not set
# CONFIG_SND_SOC_PCM179X_I2C is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_I2C is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3060_I2C is not set
# CONFIG_SND_SOC_PCM3060_SPI is not set
CONFIG_SND_SOC_PCM3168A=m
CONFIG_SND_SOC_PCM3168A_I2C=m
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM5102A is not set
# CONFIG_SND_SOC_PCM512x_I2C is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
# CONFIG_SND_SOC_PEB2466 is not set
CONFIG_SND_SOC_RK3328=m
# CONFIG_SND_SOC_RK817 is not set
# CONFIG_SND_SOC_RT1308_SDW is not set
# CONFIG_SND_SOC_RT1316_SDW is not set
# CONFIG_SND_SOC_RT1318_SDW is not set
# CONFIG_SND_SOC_RT5616 is not set
# CONFIG_SND_SOC_RT5631 is not set
# CONFIG_SND_SOC_RT5640 is not set
# CONFIG_SND_SOC_RT5659 is not set
# CONFIG_SND_SOC_RT5682_SDW is not set
# CONFIG_SND_SOC_RT700_SDW is not set
# CONFIG_SND_SOC_RT711_SDW is not set
# CONFIG_SND_SOC_RT711_SDCA_SDW is not set
# CONFIG_SND_SOC_RT712_SDCA_SDW is not set
# CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW is not set
# CONFIG_SND_SOC_RT715_SDW is not set
# CONFIG_SND_SOC_RT715_SDCA_SDW is not set
# CONFIG_SND_SOC_RT9120 is not set
# CONFIG_SND_SOC_SDW_MOCKUP is not set
# CONFIG_SND_SOC_SGTL5000 is not set
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
# CONFIG_SND_SOC_SIMPLE_MUX is not set
# CONFIG_SND_SOC_SMA1303 is not set
# CONFIG_SND_SOC_SPDIF is not set
# CONFIG_SND_SOC_SRC4XXX_I2C is not set
# CONFIG_SND_SOC_SSM2305 is not set
# CONFIG_SND_SOC_SSM2518 is not set
# CONFIG_SND_SOC_SSM2602_SPI is not set
# CONFIG_SND_SOC_SSM2602_I2C is not set
# CONFIG_SND_SOC_SSM4567 is not set
# CONFIG_SND_SOC_STA32X is not set
# CONFIG_SND_SOC_STA350 is not set
# CONFIG_SND_SOC_STI_SAS is not set
# CONFIG_SND_SOC_TAS2552 is not set
# CONFIG_SND_SOC_TAS2562 is not set
# CONFIG_SND_SOC_TAS2764 is not set
# CONFIG_SND_SOC_TAS2770 is not set
# CONFIG_SND_SOC_TAS2780 is not set
# CONFIG_SND_SOC_TAS5086 is not set
# CONFIG_SND_SOC_TAS571X is not set
# CONFIG_SND_SOC_TAS5720 is not set
# CONFIG_SND_SOC_TAS5805M is not set
# CONFIG_SND_SOC_TAS6424 is not set
# CONFIG_SND_SOC_TDA7419 is not set
# CONFIG_SND_SOC_TFA9879 is not set
# CONFIG_SND_SOC_TFA989X is not set
# CONFIG_SND_SOC_TLV320ADC3XXX is not set
# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC31XX is not set
# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set
# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set
# CONFIG_SND_SOC_TLV320ADCX140 is not set
CONFIG_SND_SOC_TS3A227E=m
# CONFIG_SND_SOC_TSCS42XX is not set
# CONFIG_SND_SOC_TSCS454 is not set
# CONFIG_SND_SOC_UDA1334 is not set
# CONFIG_SND_SOC_WCD9335 is not set
CONFIG_SND_SOC_WCD_MBHC=m
CONFIG_SND_SOC_WCD934X=m
# CONFIG_SND_SOC_WCD938X_SDW is not set
# CONFIG_SND_SOC_WM8510 is not set
# CONFIG_SND_SOC_WM8523 is not set
# CONFIG_SND_SOC_WM8524 is not set
# CONFIG_SND_SOC_WM8580 is not set
# CONFIG_SND_SOC_WM8711 is not set
# CONFIG_SND_SOC_WM8728 is not set
# CONFIG_SND_SOC_WM8731_I2C is not set
# CONFIG_SND_SOC_WM8731_SPI is not set
# CONFIG_SND_SOC_WM8737 is not set
# CONFIG_SND_SOC_WM8741 is not set
# CONFIG_SND_SOC_WM8750 is not set
# CONFIG_SND_SOC_WM8753 is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8776 is not set
# CONFIG_SND_SOC_WM8782 is not set
# CONFIG_SND_SOC_WM8804_I2C is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_WM8903 is not set
CONFIG_SND_SOC_WM8904=m
# CONFIG_SND_SOC_WM8940 is not set
# CONFIG_SND_SOC_WM8960 is not set
# CONFIG_SND_SOC_WM8961 is not set
# CONFIG_SND_SOC_WM8962 is not set
# CONFIG_SND_SOC_WM8974 is not set
# CONFIG_SND_SOC_WM8978 is not set
# CONFIG_SND_SOC_WM8985 is not set
CONFIG_SND_SOC_WSA881X=m
# CONFIG_SND_SOC_WSA883X is not set
# CONFIG_SND_SOC_ZL38060 is not set
# CONFIG_SND_SOC_MAX9759 is not set
# CONFIG_SND_SOC_MT6351 is not set
# CONFIG_SND_SOC_MT6358 is not set
# CONFIG_SND_SOC_MT6660 is not set
# CONFIG_SND_SOC_NAU8315 is not set
# CONFIG_SND_SOC_NAU8540 is not set
# CONFIG_SND_SOC_NAU8810 is not set
# CONFIG_SND_SOC_NAU8821 is not set
# CONFIG_SND_SOC_NAU8822 is not set
# CONFIG_SND_SOC_NAU8824 is not set
# CONFIG_SND_SOC_TPA6130A2 is not set
# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set
# CONFIG_SND_SOC_LPASS_VA_MACRO is not set
# CONFIG_SND_SOC_LPASS_RX_MACRO is not set
# CONFIG_SND_SOC_LPASS_TX_MACRO is not set
CONFIG_SND_SOC_ACX00=y
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set
# CONFIG_SND_TEST_COMPONENT is not set
# CONFIG_SND_VIRTIO is not set
CONFIG_AC97_BUS=m
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_BATTERY_STRENGTH is not set
# CONFIG_HIDRAW is not set
# CONFIG_UHID is not set
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
# CONFIG_HID_A4TECH is not set
# CONFIG_HID_ACCUTOUCH is not set
# CONFIG_HID_ACRUX is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_APPLEIR is not set
# CONFIG_HID_ASUS is not set
# CONFIG_HID_AUREAL is not set
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_BETOP_FF is not set
# CONFIG_HID_BIGBEN_FF is not set
# CONFIG_HID_CHERRY is not set
# CONFIG_HID_CHICONY is not set
# CONFIG_HID_CORSAIR is not set
# CONFIG_HID_COUGAR is not set
# CONFIG_HID_MACALLY is not set
# CONFIG_HID_PRODIKEYS is not set
# CONFIG_HID_CMEDIA is not set
# CONFIG_HID_CREATIVE_SB0540 is not set
# CONFIG_HID_CYPRESS is not set
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EMS_FF is not set
# CONFIG_HID_ELAN is not set
# CONFIG_HID_ELECOM is not set
# CONFIG_HID_ELO is not set
# CONFIG_HID_EVISION is not set
# CONFIG_HID_EZKEY is not set
# CONFIG_HID_GEMBIRD is not set
# CONFIG_HID_GFRM is not set
# CONFIG_HID_GLORIOUS is not set
# CONFIG_HID_HOLTEK is not set
# CONFIG_HID_GOOGLE_HAMMER is not set
# CONFIG_HID_VIVALDI is not set
# CONFIG_HID_GT683R is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
# CONFIG_HID_UCLOGIC is not set
# CONFIG_HID_WALTOP is not set
# CONFIG_HID_VIEWSONIC is not set
# CONFIG_HID_VRC2 is not set
# CONFIG_HID_XIAOMI is not set
# CONFIG_HID_GYRATION is not set
# CONFIG_HID_ICADE is not set
# CONFIG_HID_ITE is not set
# CONFIG_HID_JABRA is not set
# CONFIG_HID_TWINHAN is not set
# CONFIG_HID_KENSINGTON is not set
# CONFIG_HID_LCPOWER is not set
# CONFIG_HID_LED is not set
# CONFIG_HID_LENOVO is not set
# CONFIG_HID_LETSKETCH is not set
# CONFIG_HID_LOGITECH is not set
# CONFIG_HID_MAGICMOUSE is not set
# CONFIG_HID_MALTRON is not set
# CONFIG_HID_MAYFLASH is not set
# CONFIG_HID_MEGAWORLD_FF is not set
# CONFIG_HID_REDRAGON is not set
# CONFIG_HID_MICROSOFT is not set
# CONFIG_HID_MONTEREY is not set
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_NINTENDO is not set
# CONFIG_HID_NTI is not set
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_ORTEK is not set
# CONFIG_HID_PANTHERLORD is not set
# CONFIG_HID_PENMOUNT is not set
# CONFIG_HID_PETALYNX is not set
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_PLANTRONICS is not set
# CONFIG_HID_PXRC is not set
# CONFIG_HID_RAZER is not set
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_RETRODE is not set
# CONFIG_HID_ROCCAT is not set
# CONFIG_HID_SAITEK is not set
# CONFIG_HID_SAMSUNG is not set
# CONFIG_HID_SEMITEK is not set
# CONFIG_HID_SIGMAMICRO is not set
# CONFIG_HID_SONY is not set
# CONFIG_HID_SPEEDLINK is not set
# CONFIG_HID_STEAM is not set
# CONFIG_HID_STEELSERIES is not set
# CONFIG_HID_SUNPLUS is not set
# CONFIG_HID_RMI is not set
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
# CONFIG_HID_TIVO is not set
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_TOPRE is not set
# CONFIG_HID_THINGM is not set
# CONFIG_HID_THRUSTMASTER is not set
# CONFIG_HID_UDRAW_PS3 is not set
# CONFIG_HID_U2FZERO is not set
# CONFIG_HID_WACOM is not set
# CONFIG_HID_WIIMOTE is not set
# CONFIG_HID_XINMO is not set
# CONFIG_HID_ZEROPLUS is not set
# CONFIG_HID_ZYDACRON is not set
# CONFIG_HID_SENSOR_HUB is not set
# CONFIG_HID_ALPS is not set
# CONFIG_HID_MCP2221 is not set
# end of Special HID drivers

#
# HID-BPF support
#
# end of HID-BPF support

#
# USB HID support
#
CONFIG_USB_HID=m
# CONFIG_HID_PID is not set
# CONFIG_USB_HIDDEV is not set

#
# USB HID Boot Protocol drivers
#
# CONFIG_USB_KBD is not set
# CONFIG_USB_MOUSE is not set
# end of USB HID Boot Protocol drivers
# end of USB HID support

CONFIG_I2C_HID=y
# CONFIG_I2C_HID_ACPI is not set
# CONFIG_I2C_HID_OF is not set
# CONFIG_I2C_HID_OF_ELAN is not set
# CONFIG_I2C_HID_OF_GOODIX is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_LED_TRIG=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_CONN_GPIO=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
# CONFIG_USB_OTG_FSM is not set
# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=y

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=y
# CONFIG_USB_XHCI_PCI_RENESAS is not set
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
# CONFIG_USB_EHCI_FSL is not set
CONFIG_USB_EHCI_HCD_PLATFORM=y
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_MAX3421_HCD is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PCI=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_UHCI_HCD=y
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_HCD_BCMA is not set
# CONFIG_USB_HCD_SSB is not set
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=m
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
# CONFIG_USB_STORAGE is not set

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
CONFIG_USB_MICROTEK=m
CONFIG_USBIP_CORE=m
CONFIG_USBIP_VHCI_HCD=m
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=m
CONFIG_USBIP_VUDC=m
# CONFIG_USBIP_DEBUG is not set

#
# USB dual-mode controller drivers
#
# CONFIG_USB_CDNS_SUPPORT is not set
CONFIG_USB_MUSB_HDRC=y
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y

#
# Platform Glue Layer
#
CONFIG_USB_MUSB_SUNXI=y

#
# MUSB DMA mode
#
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_ULPI=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y

#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=y
CONFIG_USB_DWC3_HAPS=y
CONFIG_USB_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
CONFIG_USB_DWC2_PCI=y
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
# CONFIG_USB_CHIPIDEA is not set
CONFIG_USB_ISP1760=y
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_ISP1761_UDC=y
# CONFIG_USB_ISP1760_HOST_ROLE is not set
# CONFIG_USB_ISP1760_GADGET_ROLE is not set
CONFIG_USB_ISP1760_DUAL_ROLE=y

#
# USB port drivers
#
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=m
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=m
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=m
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=m
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_F81232=m
CONFIG_USB_SERIAL_F8153X=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=m
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_METRO=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MXUPORT=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=m
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=m
CONFIG_USB_SERIAL_QUALCOMM=m
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
CONFIG_USB_SERIAL_SAFE_PADDED=y
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
CONFIG_USB_SERIAL_SYMBOL=m
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_WWAN=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=m
CONFIG_USB_SERIAL_XSENS_MT=m
CONFIG_USB_SERIAL_WISHBONE=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_SERIAL_QT2=m
CONFIG_USB_SERIAL_UPD78F0730=m
# CONFIG_USB_SERIAL_XR is not set
CONFIG_USB_SERIAL_DEBUG=m

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
CONFIG_USB_IDMOUSE=m
CONFIG_USB_APPLEDISPLAY=m
# CONFIG_APPLE_MFI_FASTCHARGE is not set
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
# CONFIG_USB_TEST is not set
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=m
# CONFIG_USB_HUB_USB251XB is not set
CONFIG_USB_HSIC_USB3503=y
CONFIG_USB_HSIC_USB4604=y
# CONFIG_USB_LINK_LAYER_TEST is not set
CONFIG_USB_CHAOSKEY=m
# CONFIG_USB_ONBOARD_HUB is not set
CONFIG_USB_ATM=m
# CONFIG_USB_SPEEDTOUCH is not set
CONFIG_USB_CXACRU=m
CONFIG_USB_UEAGLEATM=m
CONFIG_USB_XUSBATM=m

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_ISP1301=y
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set

#
# USB Peripheral Controller
#
# CONFIG_USB_GR_UDC is not set
# CONFIG_USB_R8A66597 is not set
# CONFIG_USB_PXA27X is not set
# CONFIG_USB_MV_UDC is not set
# CONFIG_USB_MV_U3D is not set
# CONFIG_USB_SNP_UDC_PLAT is not set
# CONFIG_USB_M66592 is not set
# CONFIG_USB_BDC_UDC is not set
# CONFIG_USB_AMD5536UDC is not set
# CONFIG_USB_NET2272 is not set
# CONFIG_USB_NET2280 is not set
# CONFIG_USB_GOKU is not set
# CONFIG_USB_EG20T is not set
# CONFIG_USB_GADGET_XILINX is not set
# CONFIG_USB_MAX3420_UDC is not set
# CONFIG_USB_DUMMY_HCD is not set
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=m
CONFIG_USB_F_ACM=m
CONFIG_USB_U_SERIAL=m
CONFIG_USB_U_ETHER=m
CONFIG_USB_U_AUDIO=m
CONFIG_USB_F_SERIAL=m
CONFIG_USB_F_OBEX=m
CONFIG_USB_F_NCM=m
CONFIG_USB_F_ECM=m
CONFIG_USB_F_EEM=m
CONFIG_USB_F_SUBSET=m
CONFIG_USB_F_RNDIS=m
CONFIG_USB_F_MASS_STORAGE=m
CONFIG_USB_F_FS=m
CONFIG_USB_F_UAC1=m
CONFIG_USB_F_UAC1_LEGACY=m
CONFIG_USB_F_UAC2=m
CONFIG_USB_F_UVC=m
CONFIG_USB_F_MIDI=m
CONFIG_USB_F_HID=m
CONFIG_USB_F_PRINTER=m
CONFIG_USB_F_TCM=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
# CONFIG_USB_CONFIGFS_F_LB_SS is not set
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y
CONFIG_USB_CONFIGFS_F_TCM=y

#
# USB Gadget precomposed configurations
#
# CONFIG_USB_ZERO is not set
CONFIG_USB_AUDIO=m
CONFIG_GADGET_UAC1=y
# CONFIG_GADGET_UAC1_LEGACY is not set
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
CONFIG_USB_FUNCTIONFS_ETH=y
CONFIG_USB_FUNCTIONFS_RNDIS=y
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_GADGET_TARGET=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_G_HID=m
# CONFIG_USB_G_DBGP is not set
CONFIG_USB_G_WEBCAM=m
# CONFIG_USB_RAW_GADGET is not set
# end of USB Gadget precomposed configurations

CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
# CONFIG_TYPEC_RT1711H is not set
# CONFIG_TYPEC_TCPCI_MAXIM is not set
CONFIG_TYPEC_FUSB302=y
# CONFIG_TYPEC_UCSI is not set
CONFIG_TYPEC_TPS6598X=m
# CONFIG_TYPEC_ANX7411 is not set
# CONFIG_TYPEC_RT1719 is not set
CONFIG_TYPEC_HD3SS3220=m
# CONFIG_TYPEC_STUSB160X is not set
# CONFIG_TYPEC_WUSB3801 is not set

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
# CONFIG_TYPEC_MUX_FSA4480 is not set
# CONFIG_TYPEC_MUX_GPIO_SBU is not set
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
# CONFIG_TYPEC_DP_ALTMODE is not set
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
CONFIG_PWRSEQ_SD8787=m
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_SDIO_UART=m
# CONFIG_MMC_TEST is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_ARMMMCI=y
# CONFIG_MMC_STM32_SDMMC is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_PCI=y
CONFIG_MMC_RICOH_MMC=y
CONFIG_MMC_SDHCI_ACPI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
CONFIG_MMC_SDHCI_OF_AT91=y
# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set
CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MMC_SDHCI_F_SDH30=y
# CONFIG_MMC_SDHCI_MILBEAUT is not set
CONFIG_MMC_TIFM_SD=y
CONFIG_MMC_SPI=y
CONFIG_MMC_CB710=y
CONFIG_MMC_VIA_SDMMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
# CONFIG_MMC_DW_BLUEFIELD is not set
CONFIG_MMC_DW_EXYNOS=y
# CONFIG_MMC_DW_HI3798CV200 is not set
CONFIG_MMC_DW_K3=y
CONFIG_MMC_DW_PCI=y
CONFIG_MMC_VUB300=m
CONFIG_MMC_USHC=m
CONFIG_MMC_USDHI6ROL0=y
CONFIG_MMC_SUNXI=y
CONFIG_MMC_CQHCI=y
# CONFIG_MMC_HSQ is not set
CONFIG_MMC_TOSHIBA_PCI=y
CONFIG_MMC_MTK=y
CONFIG_MMC_SDHCI_XENON=y
# CONFIG_MMC_SDHCI_OMAP is not set
CONFIG_MMC_SDHCI_AM654=y
CONFIG_SCSI_UFSHCD=y
# CONFIG_SCSI_UFS_BSG is not set
# CONFIG_SCSI_UFS_HPB is not set
# CONFIG_SCSI_UFS_HWMON is not set
CONFIG_SCSI_UFSHCD_PCI=m
# CONFIG_SCSI_UFS_DWC_TC_PCI is not set
CONFIG_SCSI_UFSHCD_PLATFORM=y
# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set
# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set
CONFIG_MEMSTICK=m
# CONFIG_MEMSTICK_DEBUG is not set

#
# MemoryStick drivers
#
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
CONFIG_MSPRO_BLOCK=m
# CONFIG_MS_BLOCK is not set

#
# MemoryStick Host Controller Drivers
#
CONFIG_MEMSTICK_TIFM_MS=m
CONFIG_MEMSTICK_JMICRON_38X=m
CONFIG_MEMSTICK_R592=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=m
# CONFIG_LEDS_CLASS_MULTICOLOR is not set
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set

#
# LED drivers
#
# CONFIG_LEDS_AN30259A is not set
# CONFIG_LEDS_AW2013 is not set
# CONFIG_LEDS_BCM6328 is not set
# CONFIG_LEDS_BCM6358 is not set
# CONFIG_LEDS_CR0014114 is not set
# CONFIG_LEDS_EL15203000 is not set
CONFIG_LEDS_LM3530=m
# CONFIG_LEDS_LM3532 is not set
# CONFIG_LEDS_LM3642 is not set
CONFIG_LEDS_LM3692X=m
# CONFIG_LEDS_PCA9532 is not set
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=m
# CONFIG_LEDS_LP3952 is not set
# CONFIG_LEDS_LP50XX is not set
# CONFIG_LEDS_LP55XX_COMMON is not set
# CONFIG_LEDS_LP8860 is not set
CONFIG_LEDS_PCA955X=m
# CONFIG_LEDS_PCA955X_GPIO is not set
CONFIG_LEDS_PCA963X=m
# CONFIG_LEDS_DAC124S085 is not set
CONFIG_LEDS_PWM=m
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2606MVV is not set
# CONFIG_LEDS_BD2802 is not set
CONFIG_LEDS_LT3593=m
# CONFIG_LEDS_TCA6507 is not set
# CONFIG_LEDS_TLC591XX is not set
# CONFIG_LEDS_LM355x is not set
# CONFIG_LEDS_IS31FL319X is not set
# CONFIG_LEDS_IS31FL32XX is not set

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=m
CONFIG_LEDS_SYSCON=y
# CONFIG_LEDS_MLXREG is not set
CONFIG_LEDS_USER=m
# CONFIG_LEDS_SPI_BYTE is not set
# CONFIG_LEDS_TI_LMU_COMMON is not set

#
# Flash and Torch LED drivers
#
# CONFIG_LEDS_AAT1290 is not set
# CONFIG_LEDS_AS3645A is not set
# CONFIG_LEDS_KTD2692 is not set
# CONFIG_LEDS_LM3601X is not set
# CONFIG_LEDS_RT4505 is not set
# CONFIG_LEDS_RT8515 is not set
# CONFIG_LEDS_SGM3140 is not set

#
# RGB LED drivers
#

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_ACTIVITY=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=y
CONFIG_LEDS_TRIGGER_PATTERN=m
CONFIG_LEDS_TRIGGER_AUDIO=m
# CONFIG_LEDS_TRIGGER_TTY is not set

#
# Simple LED drivers
#
CONFIG_ACCESSIBILITY=y
CONFIG_A11Y_BRAILLE_CONSOLE=y

#
# Speakup console speech
#
# CONFIG_SPEAKUP is not set
# end of Speakup console speech

# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
# CONFIG_EDAC_DEBUG is not set
# CONFIG_EDAC_THUNDERX is not set
CONFIG_EDAC_XGENE=m
# CONFIG_EDAC_DMC520 is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_SYSTOHC is not set
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_ABB5ZES3 is not set
# CONFIG_RTC_DRV_ABEOZ9 is not set
CONFIG_RTC_DRV_ABX80X=m
CONFIG_RTC_DRV_DS1307=m
# CONFIG_RTC_DRV_DS1307_CENTURY is not set
CONFIG_RTC_DRV_DS1374=m
CONFIG_RTC_DRV_DS1374_WDT=y
CONFIG_RTC_DRV_DS1672=m
CONFIG_RTC_DRV_HYM8563=m
CONFIG_RTC_DRV_MAX6900=m
# CONFIG_RTC_DRV_MAX77686 is not set
# CONFIG_RTC_DRV_NCT3018Y is not set
CONFIG_RTC_DRV_RK808=m
CONFIG_RTC_DRV_RS5C372=m
CONFIG_RTC_DRV_ISL1208=m
CONFIG_RTC_DRV_ISL12022=m
# CONFIG_RTC_DRV_ISL12026 is not set
CONFIG_RTC_DRV_X1205=m
CONFIG_RTC_DRV_PCF8523=m
CONFIG_RTC_DRV_PCF85063=m
CONFIG_RTC_DRV_PCF85363=m
CONFIG_RTC_DRV_PCF8563=m
CONFIG_RTC_DRV_PCF8583=m
CONFIG_RTC_DRV_M41T80=m
CONFIG_RTC_DRV_M41T80_WDT=y
CONFIG_RTC_DRV_BQ32K=m
# CONFIG_RTC_DRV_S35390A is not set
CONFIG_RTC_DRV_FM3130=m
# CONFIG_RTC_DRV_RX8010 is not set
CONFIG_RTC_DRV_RX8581=m
CONFIG_RTC_DRV_RX8025=m
CONFIG_RTC_DRV_EM3027=m
# CONFIG_RTC_DRV_RV3028 is not set
# CONFIG_RTC_DRV_RV3032 is not set
CONFIG_RTC_DRV_RV8803=m
# CONFIG_RTC_DRV_S5M is not set
# CONFIG_RTC_DRV_SD3078 is not set

#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_MCP795 is not set
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
CONFIG_RTC_DRV_DS3232=m
CONFIG_RTC_DRV_DS3232_HWMON=y
CONFIG_RTC_DRV_PCF2127=m
CONFIG_RTC_DRV_RV3029C2=m
CONFIG_RTC_DRV_RV3029_HWMON=y
# CONFIG_RTC_DRV_RX6110 is not set

#
# Platform RTC drivers
#
CONFIG_RTC_DRV_DS1286=m
CONFIG_RTC_DRV_DS1511=m
CONFIG_RTC_DRV_DS1553=m
CONFIG_RTC_DRV_DS1685_FAMILY=m
CONFIG_RTC_DRV_DS1685=y
# CONFIG_RTC_DRV_DS1689 is not set
# CONFIG_RTC_DRV_DS17285 is not set
# CONFIG_RTC_DRV_DS17485 is not set
# CONFIG_RTC_DRV_DS17885 is not set
CONFIG_RTC_DRV_DS1742=m
CONFIG_RTC_DRV_DS2404=m
CONFIG_RTC_DRV_EFI=y
CONFIG_RTC_DRV_STK17TA8=m
# CONFIG_RTC_DRV_M48T86 is not set
CONFIG_RTC_DRV_M48T35=m
CONFIG_RTC_DRV_M48T59=m
CONFIG_RTC_DRV_MSM6242=m
CONFIG_RTC_DRV_BQ4802=m
CONFIG_RTC_DRV_RP5C01=m
# CONFIG_RTC_DRV_ZYNQMP is not set
CONFIG_RTC_DRV_CROS_EC=y

#
# on-CPU RTC drivers
#
# CONFIG_RTC_DRV_PL030 is not set
CONFIG_RTC_DRV_PL031=y
CONFIG_RTC_DRV_SUN6I=y
# CONFIG_RTC_DRV_CADENCE is not set
# CONFIG_RTC_DRV_FTRTC010 is not set
# CONFIG_RTC_DRV_R7301 is not set

#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_GOLDFISH is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
# CONFIG_AMBA_PL08X is not set
# CONFIG_BCM_SBA_RAID is not set
CONFIG_DMA_SUN6I=y
# CONFIG_DW_AXI_DMAC is not set
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_INTEL_IDMA64 is not set
CONFIG_MV_XOR_V2=y
CONFIG_PL330_DMA=y
# CONFIG_PLX_DMA is not set
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_XDMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
# CONFIG_XILINX_ZYNQMP_DPDMA is not set
CONFIG_QCOM_HIDMA_MGMT=y
CONFIG_QCOM_HIDMA=y
CONFIG_DW_DMAC_CORE=m
CONFIG_DW_DMAC=m
CONFIG_DW_DMAC_PCI=m
# CONFIG_DW_EDMA is not set
# CONFIG_SF_PDMA is not set

#
# DMA Clients
#
CONFIG_ASYNC_TX_DMA=y
# CONFIG_DMATEST is not set
CONFIG_DMA_ENGINE_RAID=y

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
# CONFIG_SW_SYNC is not set
# CONFIG_UDMABUF is not set
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_DEBUG is not set
# CONFIG_DMABUF_SELFTESTS is not set
# CONFIG_DMABUF_HEAPS is not set
# CONFIG_DMABUF_SYSFS_STATS is not set
# end of DMABUF options

CONFIG_AUXDISPLAY=y
# CONFIG_HD44780 is not set
# CONFIG_IMG_ASCII_LCD is not set
# CONFIG_HT16K33 is not set
# CONFIG_LCD2S is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_UIO=m
CONFIG_UIO_CIF=m
# CONFIG_UIO_PDRV_GENIRQ is not set
# CONFIG_UIO_DMEM_GENIRQ is not set
CONFIG_UIO_AEC=m
CONFIG_UIO_SERCOS3=m
CONFIG_UIO_PCI_GENERIC=m
# CONFIG_UIO_NETX is not set
# CONFIG_UIO_PRUSS is not set
# CONFIG_UIO_MF624 is not set
CONFIG_VFIO=m
CONFIG_VFIO_CONTAINER=y
CONFIG_VFIO_IOMMU_TYPE1=m
# CONFIG_VFIO_NOIOMMU is not set
CONFIG_VFIO_VIRQFD=y
CONFIG_VFIO_PCI_CORE=m
CONFIG_VFIO_PCI_MMAP=y
CONFIG_VFIO_PCI_INTX=y
CONFIG_VFIO_PCI=m
# CONFIG_MLX5_VFIO_PCI is not set
CONFIG_VFIO_PLATFORM=m
CONFIG_VFIO_AMBA=m
CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET=m
CONFIG_VFIO_PLATFORM_AMDXGBE_RESET=m
# CONFIG_VIRT_DRIVERS is not set
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_PCI_LIB=y
CONFIG_VIRTIO_PCI_LIB_LEGACY=y
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_PCI_LEGACY=y
# CONFIG_VIRTIO_PMEM is not set
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
# CONFIG_VDPA is not set
CONFIG_VHOST_IOTLB=m
CONFIG_VHOST_TASK=y
CONFIG_VHOST=m
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_SCSI=m
CONFIG_VHOST_VSOCK=m
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set

#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
# CONFIG_COMEDI is not set
CONFIG_STAGING=y
CONFIG_PRISM2_USB=m
CONFIG_RTL8192U=m
CONFIG_RTLLIB=m
CONFIG_RTLLIB_CRYPTO_CCMP=m
CONFIG_RTLLIB_CRYPTO_TKIP=m
CONFIG_RTLLIB_CRYPTO_WEP=m
CONFIG_RTL8192E=m
# CONFIG_RTL8723BS is not set
CONFIG_R8712U=m
# CONFIG_RTS5208 is not set
# CONFIG_VT6655 is not set
# CONFIG_VT6656 is not set

#
# IIO staging drivers
#

#
# Accelerometers
#
CONFIG_ADIS16203=m
CONFIG_ADIS16240=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD7816=m
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
CONFIG_ADT7316=m
CONFIG_ADT7316_SPI=m
CONFIG_ADT7316_I2C=m
# end of Analog digital bi-direction converters

#
# Direct Digital Synthesis
#
CONFIG_AD9832=m
CONFIG_AD9834=m
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
CONFIG_AD5933=m
# end of Network Analyzer, Impedance Converters

#
# Resolver to digital converters
#
CONFIG_AD2S1210=m
# end of Resolver to digital converters
# end of IIO staging drivers

# CONFIG_FB_SM750 is not set
CONFIG_STAGING_MEDIA=y
CONFIG_DVB_AV7110_IR=y
CONFIG_DVB_AV7110=m
CONFIG_DVB_AV7110_OSD=y
CONFIG_DVB_BUDGET_PATCH=m
CONFIG_DVB_SP8870=m
# CONFIG_VIDEO_MAX96712 is not set
CONFIG_VIDEO_SUNXI=y
CONFIG_VIDEO_SUNXI_CEDRUS=m
# CONFIG_VIDEO_SUN6I_ISP is not set
# CONFIG_STAGING_MEDIA_DEPRECATED is not set
# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
CONFIG_FB_TFT=m
CONFIG_FB_TFT_AGM1264K_FL=m
CONFIG_FB_TFT_BD663474=m
CONFIG_FB_TFT_HX8340BN=m
CONFIG_FB_TFT_HX8347D=m
CONFIG_FB_TFT_HX8353D=m
CONFIG_FB_TFT_HX8357D=m
CONFIG_FB_TFT_ILI9163=m
CONFIG_FB_TFT_ILI9320=m
CONFIG_FB_TFT_ILI9325=m
CONFIG_FB_TFT_ILI9340=m
CONFIG_FB_TFT_ILI9341=m
CONFIG_FB_TFT_ILI9481=m
CONFIG_FB_TFT_ILI9486=m
CONFIG_FB_TFT_PCD8544=m
CONFIG_FB_TFT_RA8875=m
CONFIG_FB_TFT_S6D02A1=m
CONFIG_FB_TFT_S6D1121=m
CONFIG_FB_TFT_SEPS525=m
CONFIG_FB_TFT_SH1106=m
CONFIG_FB_TFT_SSD1289=m
CONFIG_FB_TFT_SSD1305=m
CONFIG_FB_TFT_SSD1306=m
CONFIG_FB_TFT_SSD1331=m
CONFIG_FB_TFT_SSD1351=m
CONFIG_FB_TFT_ST7735R=m
CONFIG_FB_TFT_ST7789V=m
CONFIG_FB_TFT_TINYLCD=m
CONFIG_FB_TFT_TLS8204=m
CONFIG_FB_TFT_UC1611=m
CONFIG_FB_TFT_UC1701=m
CONFIG_FB_TFT_UPD161704=m
# CONFIG_KS7010 is not set
# CONFIG_PI433 is not set
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_QLGE is not set
# CONFIG_VME_BUS is not set
# CONFIG_GOLDFISH is not set
CONFIG_CHROME_PLATFORMS=y
# CONFIG_CHROMEOS_ACPI is not set
CONFIG_CHROMEOS_TBMC=m
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_RPMSG=m
CONFIG_CROS_EC_SPI=y
# CONFIG_CROS_EC_UART is not set
CONFIG_CROS_EC_PROTO=y
CONFIG_CROS_KBD_LED_BACKLIGHT=y
CONFIG_CROS_EC_CHARDEV=y
CONFIG_CROS_EC_LIGHTBAR=m
CONFIG_CROS_EC_VBC=m
CONFIG_CROS_EC_DEBUGFS=m
CONFIG_CROS_EC_SENSORHUB=y
CONFIG_CROS_EC_SYSFS=m
CONFIG_CROS_EC_TYPEC=y
# CONFIG_CROS_HPS_I2C is not set
CONFIG_CROS_USBPD_LOGGER=m
CONFIG_CROS_USBPD_NOTIFY=y
# CONFIG_CHROMEOS_PRIVACY_SCREEN is not set
# CONFIG_CROS_TYPEC_SWITCH is not set
# CONFIG_MELLANOX_PLATFORM is not set
# CONFIG_SURFACE_PLATFORMS is not set
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Clock driver for ARM Reference designs
#
# CONFIG_CLK_ICST is not set
CONFIG_CLK_SP810=y
CONFIG_CLK_VEXPRESS_OSC=y
# end of Clock driver for ARM Reference designs

# CONFIG_LMK04832 is not set
# CONFIG_COMMON_CLK_MAX77686 is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
# CONFIG_COMMON_CLK_S2MPS11 is not set
# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
CONFIG_COMMON_CLK_XGENE=y
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_RS9_PCIE is not set
# CONFIG_COMMON_CLK_SI521XX is not set
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_VC7 is not set
CONFIG_COMMON_CLK_BD718XX=m
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
CONFIG_SUNXI_CCU=y
CONFIG_SUN50I_A64_CCU=y
CONFIG_SUN50I_A100_CCU=y
CONFIG_SUN50I_A100_R_CCU=y
CONFIG_SUN50I_H6_CCU=y
CONFIG_SUN50I_H616_CCU=y
CONFIG_SUN50I_H6_R_CCU=y
# CONFIG_SUN6I_RTC_CCU is not set
CONFIG_SUN8I_H3_CCU=y
CONFIG_SUN8I_DE2_CCU=y
CONFIG_SUN8I_R_CCU=y
# CONFIG_XILINX_VCU is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
CONFIG_HWSPINLOCK=y
# CONFIG_HWSPINLOCK_SUN6I is not set

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_ACPI=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_SUN4I_TIMER=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
# end of Clock Source drivers

CONFIG_MAILBOX=y
CONFIG_ARM_MHU=y
# CONFIG_ARM_MHU_V2 is not set
CONFIG_PLATFORM_MHU=y
# CONFIG_PL320_MBOX is not set
CONFIG_PCC=y
# CONFIG_ALTERA_MBOX is not set
# CONFIG_MAILBOX_TEST is not set
CONFIG_SUN6I_MSGBOX=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_DART is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
# CONFIG_IOMMUFD is not set
# CONFIG_SUN50I_IOMMU is not set
CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
CONFIG_ARM_SMMU_V3=y
# CONFIG_ARM_SMMU_V3_SVA is not set
# CONFIG_VIRTIO_IOMMU is not set

#
# Remoteproc drivers
#
CONFIG_REMOTEPROC=y
# CONFIG_REMOTEPROC_CDEV is not set
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=y
CONFIG_RPMSG_CHAR=y
# CONFIG_RPMSG_CTRL is not set
# CONFIG_RPMSG_NS is not set
CONFIG_RPMSG_QCOM_GLINK=y
CONFIG_RPMSG_QCOM_GLINK_RPM=y
# CONFIG_RPMSG_VIRTIO is not set
# end of Rpmsg drivers

CONFIG_SOUNDWIRE=m

#
# SoundWire Devices
#
# CONFIG_SOUNDWIRE_AMD is not set
# CONFIG_SOUNDWIRE_INTEL is not set
CONFIG_SOUNDWIRE_QCOM=m

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
# end of Amlogic SoC drivers

#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
# CONFIG_QUICC_ENGINE is not set
# CONFIG_FSL_RCPM is not set
# end of NXP/Freescale QorIQ SoC drivers

#
# fujitsu SoC drivers
#
# CONFIG_A64FX_DIAG is not set
# end of fujitsu SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Enable LiteX SoC Builder specific drivers
#
# CONFIG_LITEX_SOC_CONTROLLER is not set
# end of Enable LiteX SoC Builder specific drivers

# CONFIG_WPCM450_SOC is not set

#
# Qualcomm SoC drivers
#
# CONFIG_QCOM_PMIC_GLINK is not set
# end of Qualcomm SoC drivers

CONFIG_SUNXI_MBUS=y
CONFIG_SUNXI_SRAM=y
# CONFIG_SUN20I_PPU is not set
# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEVFREQ_GOV_PASSIVE=y

#
# DEVFREQ Drivers
#
CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
CONFIG_EXTCON_ADC_JACK=m
# CONFIG_EXTCON_FSA9480 is not set
CONFIG_EXTCON_GPIO=y
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_PTN5150 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
CONFIG_EXTCON_USB_GPIO=y
CONFIG_EXTCON_USBC_CROS_EC=y
# CONFIG_EXTCON_USBC_TUSB320 is not set
CONFIG_MEMORY=y
# CONFIG_ARM_PL172_MPMC is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=y
CONFIG_IIO_BUFFER_DMA=m
CONFIG_IIO_BUFFER_DMAENGINE=m
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
CONFIG_IIO_TRIGGERED_EVENT=m

#
# Accelerometers
#
CONFIG_ADIS16201=m
CONFIG_ADIS16209=m
# CONFIG_ADXL313_I2C is not set
# CONFIG_ADXL313_SPI is not set
CONFIG_ADXL345=m
CONFIG_ADXL345_I2C=m
CONFIG_ADXL345_SPI=m
# CONFIG_ADXL355_I2C is not set
# CONFIG_ADXL355_SPI is not set
# CONFIG_ADXL367_SPI is not set
# CONFIG_ADXL367_I2C is not set
CONFIG_ADXL372=m
CONFIG_ADXL372_SPI=m
CONFIG_ADXL372_I2C=m
CONFIG_BMA180=m
CONFIG_BMA220=m
CONFIG_BMA400=m
CONFIG_BMA400_I2C=m
CONFIG_BMA400_SPI=m
CONFIG_BMC150_ACCEL=m
CONFIG_BMC150_ACCEL_I2C=m
CONFIG_BMC150_ACCEL_SPI=m
# CONFIG_BMI088_ACCEL is not set
CONFIG_DA280=m
CONFIG_DA311=m
CONFIG_DMARD06=m
CONFIG_DMARD09=m
CONFIG_DMARD10=m
# CONFIG_FXLS8962AF_I2C is not set
# CONFIG_FXLS8962AF_SPI is not set
CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
# CONFIG_IIO_KX022A_SPI is not set
# CONFIG_IIO_KX022A_I2C is not set
CONFIG_KXSD9=m
CONFIG_KXSD9_SPI=m
CONFIG_KXSD9_I2C=m
CONFIG_KXCJK1013=m
CONFIG_MC3230=m
CONFIG_MMA7455=m
CONFIG_MMA7455_I2C=m
CONFIG_MMA7455_SPI=m
CONFIG_MMA7660=m
CONFIG_MMA8452=m
CONFIG_MMA9551_CORE=m
CONFIG_MMA9551=m
CONFIG_MMA9553=m
# CONFIG_MSA311 is not set
CONFIG_MXC4005=m
CONFIG_MXC6255=m
CONFIG_SCA3000=m
# CONFIG_SCA3300 is not set
CONFIG_STK8312=m
CONFIG_STK8BA50=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=m
# CONFIG_AD4130 is not set
CONFIG_AD7091R5=m
CONFIG_AD7124=m
CONFIG_AD7192=m
CONFIG_AD7266=m
CONFIG_AD7280=m
CONFIG_AD7291=m
CONFIG_AD7292=m
CONFIG_AD7298=m
CONFIG_AD7476=m
CONFIG_AD7606=m
CONFIG_AD7606_IFACE_PARALLEL=m
CONFIG_AD7606_IFACE_SPI=m
CONFIG_AD7766=m
CONFIG_AD7768_1=m
CONFIG_AD7780=m
CONFIG_AD7791=m
CONFIG_AD7793=m
CONFIG_AD7887=m
CONFIG_AD7923=m
CONFIG_AD7949=m
CONFIG_AD799X=m
CONFIG_AD9467=m
CONFIG_ADI_AXI_ADC=m
CONFIG_AXP20X_ADC=m
CONFIG_AXP288_ADC=m
CONFIG_CC10001_ADC=m
CONFIG_ENVELOPE_DETECTOR=m
CONFIG_HI8435=m
CONFIG_HX711=m
CONFIG_INA2XX_ADC=m
CONFIG_LTC2471=m
CONFIG_LTC2485=m
CONFIG_LTC2496=m
CONFIG_LTC2497=m
CONFIG_MAX1027=m
CONFIG_MAX11100=m
CONFIG_MAX1118=m
# CONFIG_MAX11205 is not set
# CONFIG_MAX11410 is not set
CONFIG_MAX1241=m
CONFIG_MAX1363=m
CONFIG_MAX9611=m
CONFIG_MCP320X=m
CONFIG_MCP3422=m
CONFIG_MCP3911=m
CONFIG_NAU7802=m
CONFIG_QCOM_VADC_COMMON=y
CONFIG_QCOM_SPMI_IADC=m
CONFIG_QCOM_SPMI_VADC=y
CONFIG_QCOM_SPMI_ADC5=m
# CONFIG_RICHTEK_RTQ6056 is not set
CONFIG_SD_ADC_MODULATOR=m
CONFIG_TI_ADC081C=m
CONFIG_TI_ADC0832=m
CONFIG_TI_ADC084S021=m
CONFIG_TI_ADC12138=m
CONFIG_TI_ADC108S102=m
CONFIG_TI_ADC128S052=m
CONFIG_TI_ADC161S626=m
CONFIG_TI_ADS1015=m
# CONFIG_TI_ADS7924 is not set
# CONFIG_TI_ADS1100 is not set
CONFIG_TI_ADS7950=m
CONFIG_TI_ADS8344=m
CONFIG_TI_ADS8688=m
CONFIG_TI_ADS124S08=m
# CONFIG_TI_ADS131E08 is not set
# CONFIG_TI_LMP92064 is not set
CONFIG_TI_TLC4541=m
# CONFIG_TI_TSC2046 is not set
CONFIG_VF610_ADC=m
CONFIG_VIPERBOARD_ADC=m
# CONFIG_XILINX_XADC is not set
# end of Analog to digital converters

#
# Analog to digital and digital to analog converters
#
# CONFIG_AD74115 is not set
# CONFIG_AD74413R is not set
# end of Analog to digital and digital to analog converters

#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=m
# end of Analog Front Ends

#
# Amplifiers
#
CONFIG_AD8366=m
# CONFIG_ADA4250 is not set
CONFIG_HMC425=m
# end of Amplifiers

#
# Capacitance to digital converters
#
CONFIG_AD7150=m
CONFIG_AD7746=m
# end of Capacitance to digital converters

#
# Chemical Sensors
#
CONFIG_ATLAS_PH_SENSOR=m
CONFIG_ATLAS_EZO_SENSOR=m
CONFIG_BME680=m
CONFIG_BME680_I2C=m
CONFIG_BME680_SPI=m
CONFIG_CCS811=m
CONFIG_IAQCORE=m
CONFIG_PMS7003=m
CONFIG_SCD30_CORE=m
CONFIG_SCD30_I2C=m
CONFIG_SCD30_SERIAL=m
# CONFIG_SCD4X is not set
CONFIG_SENSIRION_SGP30=m
# CONFIG_SENSIRION_SGP40 is not set
# CONFIG_SPS30_I2C is not set
# CONFIG_SPS30_SERIAL is not set
# CONFIG_SENSEAIR_SUNRISE_CO2 is not set
CONFIG_VZ89X=m
# end of Chemical Sensors

CONFIG_IIO_CROS_EC_SENSORS_CORE=m
CONFIG_IIO_CROS_EC_SENSORS=m
CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m

#
# Hid Sensor IIO Common
#
# end of Hid Sensor IIO Common

CONFIG_IIO_MS_SENSORS_I2C=m

#
# IIO SCMI Sensors
#
# CONFIG_IIO_SCMI is not set
# end of IIO SCMI Sensors

#
# SSP Sensor Common
#
# CONFIG_IIO_SSP_SENSORHUB is not set
# end of SSP Sensor Common

CONFIG_IIO_ST_SENSORS_I2C=m
CONFIG_IIO_ST_SENSORS_SPI=m
CONFIG_IIO_ST_SENSORS_CORE=m

#
# Digital to analog converters
#
# CONFIG_AD3552R is not set
CONFIG_AD5064=m
CONFIG_AD5360=m
CONFIG_AD5380=m
CONFIG_AD5421=m
CONFIG_AD5446=m
CONFIG_AD5449=m
CONFIG_AD5592R_BASE=m
CONFIG_AD5592R=m
CONFIG_AD5593R=m
CONFIG_AD5504=m
CONFIG_AD5624R_SPI=m
# CONFIG_LTC2688 is not set
CONFIG_AD5686=m
CONFIG_AD5686_SPI=m
CONFIG_AD5696_I2C=m
CONFIG_AD5755=m
CONFIG_AD5758=m
CONFIG_AD5761=m
CONFIG_AD5764=m
# CONFIG_AD5766 is not set
CONFIG_AD5770R=m
CONFIG_AD5791=m
# CONFIG_AD7293 is not set
CONFIG_AD7303=m
CONFIG_AD8801=m
CONFIG_DPOT_DAC=m
CONFIG_DS4424=m
CONFIG_LTC1660=m
CONFIG_LTC2632=m
CONFIG_M62332=m
CONFIG_MAX517=m
# CONFIG_MAX5522 is not set
CONFIG_MAX5821=m
CONFIG_MCP4725=m
CONFIG_MCP4922=m
CONFIG_TI_DAC082S085=m
CONFIG_TI_DAC5571=m
CONFIG_TI_DAC7311=m
CONFIG_TI_DAC7612=m
CONFIG_VF610_DAC=m
# end of Digital to analog converters

#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver

#
# Filters
#
# CONFIG_ADMV8818 is not set
# end of Filters

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
CONFIG_AD9523=m
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4350=m
CONFIG_ADF4371=m
# CONFIG_ADF4377 is not set
# CONFIG_ADMV1013 is not set
# CONFIG_ADMV1014 is not set
# CONFIG_ADMV4420 is not set
# CONFIG_ADRF6780 is not set
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=m
CONFIG_ADIS16130=m
CONFIG_ADIS16136=m
CONFIG_ADIS16260=m
CONFIG_ADXRS290=m
CONFIG_ADXRS450=m
CONFIG_BMG160=m
CONFIG_BMG160_I2C=m
CONFIG_BMG160_SPI=m
CONFIG_FXAS21002C=m
CONFIG_FXAS21002C_I2C=m
CONFIG_FXAS21002C_SPI=m
CONFIG_MPU3050=m
CONFIG_MPU3050_I2C=m
CONFIG_IIO_ST_GYRO_3AXIS=m
CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
CONFIG_ITG3200=m
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
CONFIG_AFE4403=m
CONFIG_AFE4404=m
CONFIG_MAX30100=m
CONFIG_MAX30102=m
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
CONFIG_AM2315=m
CONFIG_DHT11=m
CONFIG_HDC100X=m
CONFIG_HDC2010=m
CONFIG_HTS221=m
CONFIG_HTS221_I2C=m
CONFIG_HTS221_SPI=m
CONFIG_HTU21=m
CONFIG_SI7005=m
CONFIG_SI7020=m
# end of Humidity sensors

#
# Inertial measurement units
#
CONFIG_ADIS16400=m
CONFIG_ADIS16460=m
CONFIG_ADIS16475=m
CONFIG_ADIS16480=m
CONFIG_BMI160=m
CONFIG_BMI160_I2C=m
CONFIG_BMI160_SPI=m
# CONFIG_BOSCH_BNO055_SERIAL is not set
# CONFIG_BOSCH_BNO055_I2C is not set
CONFIG_FXOS8700=m
CONFIG_FXOS8700_I2C=m
CONFIG_FXOS8700_SPI=m
CONFIG_KMX61=m
CONFIG_INV_ICM42600=m
CONFIG_INV_ICM42600_I2C=m
CONFIG_INV_ICM42600_SPI=m
CONFIG_INV_MPU6050_IIO=m
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_SPI=m
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_LSM6DSX_I2C=m
CONFIG_IIO_ST_LSM6DSX_SPI=m
# CONFIG_IIO_ST_LSM9DS0 is not set
# end of Inertial measurement units

CONFIG_IIO_ADIS_LIB=m
CONFIG_IIO_ADIS_LIB_BUFFER=y

#
# Light sensors
#
CONFIG_ACPI_ALS=m
CONFIG_ADJD_S311=m
CONFIG_ADUX1020=m
CONFIG_AL3010=m
CONFIG_AL3320A=m
CONFIG_APDS9300=m
CONFIG_APDS9960=m
CONFIG_AS73211=m
CONFIG_BH1750=m
CONFIG_BH1780=m
CONFIG_CM32181=m
CONFIG_CM3232=m
CONFIG_CM3323=m
CONFIG_CM3605=m
CONFIG_CM36651=m
CONFIG_IIO_CROS_EC_LIGHT_PROX=m
CONFIG_GP2AP002=m
CONFIG_GP2AP020A00F=m
CONFIG_SENSORS_ISL29018=m
CONFIG_SENSORS_ISL29028=m
CONFIG_ISL29125=m
CONFIG_JSA1212=m
# CONFIG_ROHM_BU27034 is not set
CONFIG_RPR0521=m
CONFIG_LTR501=m
# CONFIG_LTRF216A is not set
CONFIG_LV0104CS=m
CONFIG_MAX44000=m
CONFIG_MAX44009=m
CONFIG_NOA1305=m
CONFIG_OPT3001=m
CONFIG_PA12203001=m
CONFIG_SI1133=m
CONFIG_SI1145=m
CONFIG_STK3310=m
CONFIG_ST_UVIS25=m
CONFIG_ST_UVIS25_I2C=m
CONFIG_ST_UVIS25_SPI=m
CONFIG_TCS3414=m
CONFIG_TCS3472=m
CONFIG_SENSORS_TSL2563=m
CONFIG_TSL2583=m
# CONFIG_TSL2591 is not set
CONFIG_TSL2772=m
CONFIG_TSL4531=m
CONFIG_US5182D=m
CONFIG_VCNL4000=m
CONFIG_VCNL4035=m
CONFIG_VEML6030=m
CONFIG_VEML6070=m
CONFIG_VL6180=m
CONFIG_ZOPT2201=m
# end of Light sensors

#
# Magnetometer sensors
#
CONFIG_AK8974=m
CONFIG_AK8975=m
CONFIG_AK09911=m
CONFIG_BMC150_MAGN=m
CONFIG_BMC150_MAGN_I2C=m
CONFIG_BMC150_MAGN_SPI=m
CONFIG_MAG3110=m
CONFIG_MMC35240=m
CONFIG_IIO_ST_MAGN_3AXIS=m
CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
CONFIG_SENSORS_HMC5843=m
CONFIG_SENSORS_HMC5843_I2C=m
CONFIG_SENSORS_HMC5843_SPI=m
CONFIG_SENSORS_RM3100=m
CONFIG_SENSORS_RM3100_I2C=m
CONFIG_SENSORS_RM3100_SPI=m
# CONFIG_TI_TMAG5273 is not set
# CONFIG_YAMAHA_YAS530 is not set
# end of Magnetometer sensors

#
# Multiplexers
#
CONFIG_IIO_MUX=y
# end of Multiplexers

#
# Inclinometer sensors
#
# end of Inclinometer sensors

#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=m
CONFIG_IIO_INTERRUPT_TRIGGER=m
CONFIG_IIO_TIGHTLOOP_TRIGGER=m
CONFIG_IIO_SYSFS_TRIGGER=m
# end of Triggers - standalone

#
# Linear and angular position sensors
#
# end of Linear and angular position sensors

#
# Digital potentiometers
#
# CONFIG_AD5110 is not set
CONFIG_AD5272=m
CONFIG_DS1803=m
CONFIG_MAX5432=m
CONFIG_MAX5481=m
CONFIG_MAX5487=m
CONFIG_MCP4018=m
CONFIG_MCP4131=m
CONFIG_MCP4531=m
CONFIG_MCP41010=m
CONFIG_TPL0102=m
# end of Digital potentiometers

#
# Digital potentiostats
#
CONFIG_LMP91000=m
# end of Digital potentiostats

#
# Pressure sensors
#
CONFIG_ABP060MG=m
CONFIG_BMP280=m
CONFIG_BMP280_I2C=m
CONFIG_BMP280_SPI=m
CONFIG_IIO_CROS_EC_BARO=m
CONFIG_DLHL60D=m
CONFIG_DPS310=m
CONFIG_HP03=m
CONFIG_ICP10100=m
CONFIG_MPL115=m
CONFIG_MPL115_I2C=m
CONFIG_MPL115_SPI=m
CONFIG_MPL3115=m
CONFIG_MS5611=m
CONFIG_MS5611_I2C=m
CONFIG_MS5611_SPI=m
CONFIG_MS5637=m
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_PRESS_I2C=m
CONFIG_IIO_ST_PRESS_SPI=m
CONFIG_T5403=m
CONFIG_HP206C=m
CONFIG_ZPA2326=m
CONFIG_ZPA2326_I2C=m
CONFIG_ZPA2326_SPI=m
# end of Pressure sensors

#
# Lightning sensors
#
CONFIG_AS3935=m
# end of Lightning sensors

#
# Proximity and distance sensors
#
# CONFIG_CROS_EC_MKBP_PROXIMITY is not set
CONFIG_ISL29501=m
CONFIG_LIDAR_LITE_V2=m
CONFIG_MB1232=m
CONFIG_PING=m
CONFIG_RFD77402=m
CONFIG_SRF04=m
CONFIG_SX_COMMON=m
CONFIG_SX9310=m
# CONFIG_SX9324 is not set
# CONFIG_SX9360 is not set
CONFIG_SX9500=m
CONFIG_SRF08=m
CONFIG_VCNL3020=m
CONFIG_VL53L0X_I2C=m
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
CONFIG_AD2S90=m
CONFIG_AD2S1200=m
# end of Resolver to digital converters

#
# Temperature sensors
#
CONFIG_LTC2983=m
CONFIG_MAXIM_THERMOCOUPLE=m
CONFIG_MLX90614=m
CONFIG_MLX90632=m
CONFIG_TMP006=m
CONFIG_TMP007=m
# CONFIG_TMP117 is not set
CONFIG_TSYS01=m
CONFIG_TSYS02D=m
# CONFIG_MAX30208 is not set
CONFIG_MAX31856=m
# CONFIG_MAX31865 is not set
# end of Temperature sensors

# CONFIG_NTB is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_ATMEL_TCB is not set
# CONFIG_PWM_CLK is not set
CONFIG_PWM_CROS_EC=m
# CONFIG_PWM_DWC is not set
# CONFIG_PWM_FSL_FTM is not set
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_SUN4I=y
# CONFIG_PWM_XILINX is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_AL_FIC is not set
CONFIG_SUN6I_R_INTC=y
CONFIG_SUNXI_NMI_INTC=y
# CONFIG_XILINX_INTC is not set
CONFIG_PARTITION_PERCPU=y
# end of IRQ chip support

# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_SCMI=y
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SUNXI=y
# CONFIG_RESET_TI_SYSCON is not set
# CONFIG_RESET_TI_TPS380X is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_PHY_CAN_TRANSCEIVER is not set
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_SUN6I_MIPI_DPHY=m
# CONFIG_PHY_SUN9I_USB is not set
CONFIG_PHY_SUN50I_USB3=y

#
# PHY drivers for Broadcom platforms
#
# CONFIG_BCM_KONA_USB2_PHY is not set
# end of PHY drivers for Broadcom platforms

# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_DPHY_RX is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_LAN966X_SERDES is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
CONFIG_PHY_QCOM_USB_HS=y
CONFIG_PHY_QCOM_USB_HSIC=y
# CONFIG_PHY_SAMSUNG_USB2 is not set
# CONFIG_PHY_TUSB1210 is not set
# end of PHY Subsystem

CONFIG_POWERCAP=y
# CONFIG_IDLE_INJECT is not set
# CONFIG_ARM_SCMI_POWERCAP is not set
# CONFIG_DTPM is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=y
CONFIG_ARM_CCI400_PMU=y
CONFIG_ARM_CCI5xx_PMU=y
CONFIG_ARM_CCN=y
# CONFIG_ARM_CMN is not set
CONFIG_ARM_PMU=y
CONFIG_ARM_PMU_ACPI=y
# CONFIG_ARM_SMMU_V3_PMU is not set
CONFIG_ARM_PMUV3=y
# CONFIG_ARM_DSU_PMU is not set
# CONFIG_ARM_SPE_PMU is not set
# CONFIG_ARM_DMC620_PMU is not set
# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set
CONFIG_HISI_PMU=y
# CONFIG_HISI_PCIE_PMU is not set
# CONFIG_HNS3_PMU is not set
# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set
# end of Performance monitor support

CONFIG_RAS=y
# CONFIG_USB4 is not set

#
# Android
#
# CONFIG_ANDROID_BINDER_IPC is not set
# end of Android

CONFIG_LIBNVDIMM=y
CONFIG_BLK_DEV_PMEM=m
CONFIG_ND_CLAIM=y
CONFIG_ND_BTT=m
CONFIG_BTT=y
CONFIG_OF_PMEM=y
CONFIG_NVDIMM_KEYS=y
# CONFIG_NVDIMM_SECURITY_TEST is not set
CONFIG_DAX=y
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y

#
# Layout Types
#
# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set
# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set
# end of Layout Types

# CONFIG_NVMEM_RMEM is not set
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_NVMEM_SUNXI_SID=y
# CONFIG_NVMEM_U_BOOT_ENV is not set

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# CONFIG_HISI_PTT is not set
# end of HW tracing support

# CONFIG_FPGA is not set
# CONFIG_FSI is not set
# CONFIG_TEE is not set
CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
# CONFIG_MUX_ADGS1408 is not set
CONFIG_MUX_GPIO=y
# CONFIG_MUX_MMIO is not set
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
CONFIG_SLIMBUS=m
CONFIG_SLIM_QCOM_CTRL=m
CONFIG_INTERCONNECT=y
# CONFIG_COUNTER is not set
# CONFIG_MOST is not set
# CONFIG_PECI is not set
# CONFIG_HTE is not set
# CONFIG_CDX_BUS is not set
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_IOMAP=y
CONFIG_LEGACY_DIRECT_IO=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=m
# CONFIG_REISERFS_CHECK is not set
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
# CONFIG_JFS_DEBUG is not set
# CONFIG_JFS_STATISTICS is not set
CONFIG_XFS_FS=y
CONFIG_XFS_SUPPORT_V4=y
# CONFIG_XFS_SUPPORT_ASCII_CI is not set
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
# CONFIG_XFS_RT is not set
# CONFIG_XFS_ONLINE_SCRUB is not set
# CONFIG_XFS_WARN is not set
# CONFIG_XFS_DEBUG is not set
CONFIG_GFS2_FS=m
CONFIG_GFS2_FS_LOCKING_DLM=y
CONFIG_OCFS2_FS=m
CONFIG_OCFS2_FS_O2CB=m
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
# CONFIG_OCFS2_FS_STATS is not set
# CONFIG_OCFS2_DEBUG_MASKLOG is not set
# CONFIG_OCFS2_DEBUG_FS is not set
CONFIG_BTRFS_FS=m
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
# CONFIG_BTRFS_FS_REF_VERIFY is not set
CONFIG_NILFS2_FS=m
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
# CONFIG_F2FS_FAULT_INJECTION is not set
# CONFIG_F2FS_FS_COMPRESSION is not set
CONFIG_F2FS_IOSTAT=y
# CONFIG_F2FS_UNFAIR_RWSEM is not set
# CONFIG_ZONEFS_FS is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
CONFIG_AUTOFS4_FS=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=m
CONFIG_CUSE=m
# CONFIG_VIRTIO_FS is not set
CONFIG_OVERLAY_FS=m
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set

#
# Caches
#
CONFIG_NETFS_SUPPORT=m
CONFIG_NETFS_STATS=y
CONFIG_FSCACHE=m
CONFIG_FSCACHE_STATS=y
# CONFIG_FSCACHE_DEBUG is not set
CONFIG_CACHEFILES=m
# CONFIG_CACHEFILES_DEBUG is not set
# CONFIG_CACHEFILES_ERROR_INJECTION is not set
# CONFIG_CACHEFILES_ONDEMAND is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
# CONFIG_FAT_DEFAULT_UTF8 is not set
CONFIG_EXFAT_FS=m
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS3_FS is not set
# end of DOS/FAT/EXFAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_TMPFS_INODE64 is not set
CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_MEMFD_CREATE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=y
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
CONFIG_AFFS_FS=m
CONFIG_ECRYPT_FS=m
# CONFIG_ECRYPT_FS_MESSAGING is not set
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
CONFIG_BEFS_FS=m
# CONFIG_BEFS_DEBUG is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_UBIFS_FS=m
# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
CONFIG_CRAMFS=m
CONFIG_CRAMFS_BLOCKDEV=y
# CONFIG_CRAMFS_MTD is not set
CONFIG_SQUASHFS=m
CONFIG_SQUASHFS_FILE_CACHE=y
# CONFIG_SQUASHFS_FILE_DIRECT is not set
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set
CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
# CONFIG_SQUASHFS_ZSTD is not set
# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
# CONFIG_SQUASHFS_EMBEDDED is not set
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
CONFIG_MINIX_FS=m
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
CONFIG_ROMFS_FS=m
CONFIG_ROMFS_BACKED_BY_BLOCK=y
# CONFIG_ROMFS_BACKED_BY_MTD is not set
# CONFIG_ROMFS_BACKED_BY_BOTH is not set
CONFIG_ROMFS_ON_BLOCK=y
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
CONFIG_PSTORE_DEFLATE_COMPRESS=y
# CONFIG_PSTORE_LZO_COMPRESS is not set
# CONFIG_PSTORE_LZ4_COMPRESS is not set
# CONFIG_PSTORE_LZ4HC_COMPRESS is not set
# CONFIG_PSTORE_842_COMPRESS is not set
# CONFIG_PSTORE_ZSTD_COMPRESS is not set
CONFIG_PSTORE_COMPRESS=y
CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
# CONFIG_PSTORE_CONSOLE is not set
# CONFIG_PSTORE_PMSG is not set
CONFIG_PSTORE_RAM=m
# CONFIG_PSTORE_BLK is not set
CONFIG_SYSV_FS=m
CONFIG_UFS_FS=m
# CONFIG_UFS_FS_WRITE is not set
# CONFIG_UFS_DEBUG is not set
# CONFIG_EROFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
# CONFIG_NFS_V2 is not set
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_SWAP=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=y
CONFIG_PNFS_BLOCK=y
CONFIG_PNFS_FLEXFILE_LAYOUT=y
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
# CONFIG_NFS_V4_1_MIGRATION is not set
CONFIG_NFS_V4_SECURITY_LABEL=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DEBUG=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
# CONFIG_NFS_V4_2_READ_PLUS is not set
CONFIG_NFSD=m
# CONFIG_NFSD_V2 is not set
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
CONFIG_NFSD_PNFS=y
CONFIG_NFSD_BLOCKLAYOUT=y
CONFIG_NFSD_SCSILAYOUT=y
CONFIG_NFSD_FLEXFILELAYOUT=y
CONFIG_NFSD_V4_2_INTER_SSC=y
CONFIG_NFSD_V4_SECURITY_LABEL=y
CONFIG_GRACE_PERIOD=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_NFS_V4_2_SSC_HELPER=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_BACKCHANNEL=y
CONFIG_SUNRPC_SWAP=y
CONFIG_RPCSEC_GSS_KRB5=m
# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_DES is not set
# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1 is not set
# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA is not set
# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 is not set
CONFIG_SUNRPC_DEBUG=y
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
# CONFIG_CEPH_FS_SECURITY_LABEL is not set
CONFIG_CIFS=m
# CONFIG_CIFS_STATS2 is not set
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CIFS_DEBUG=y
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
CONFIG_CIFS_DFS_UPCALL=y
# CONFIG_CIFS_SWN_UPCALL is not set
CONFIG_CIFS_FSCACHE=y
# CONFIG_SMB_SERVER is not set
CONFIG_SMBFS=m
CONFIG_CODA_FS=m
# CONFIG_AFS_FS is not set
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
CONFIG_9P_FS_SECURITY=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=m
CONFIG_NLS_MAC_GAELIC=m
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=m
CONFIG_DLM=m
CONFIG_DLM_DEBUG=y
# CONFIG_UNICODE is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
CONFIG_PERSISTENT_KEYRINGS=y
CONFIG_TRUSTED_KEYS=m
# CONFIG_TRUSTED_KEYS_TPM is not set

#
# No trust source selected!
#
CONFIG_ENCRYPTED_KEYS=y
# CONFIG_USER_DECRYPTED_DATA is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_KEY_NOTIFICATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_NETWORK_XFRM=y
# CONFIG_SECURITY_PATH is not set
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
# CONFIG_SECURITY_SELINUX is not set
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_SECURITY_APPARMOR is not set
# CONFIG_SECURITY_LOADPIN is not set
CONFIG_SECURITY_YAMA=y
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
# CONFIG_SECURITY_LANDLOCK is not set
# CONFIG_INTEGRITY is not set
# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
CONFIG_INIT_STACK_NONE=y
# CONFIG_INIT_STACK_ALL_PATTERN is not set
# CONFIG_INIT_STACK_ALL_ZERO is not set
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
# CONFIG_ZERO_CALL_USED_REGS is not set
# end of Memory initialization

CONFIG_RANDSTRUCT_NONE=y
# CONFIG_RANDSTRUCT_FULL is not set
# CONFIG_RANDSTRUCT_PERFORMANCE is not set
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=m
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=m
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=m
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=m
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=m
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_ENGINE=y
# end of Crypto core or helper

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=m
# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set
CONFIG_CRYPTO_ECC=m
CONFIG_CRYPTO_ECDH=m
# CONFIG_CRYPTO_ECDSA is not set
# CONFIG_CRYPTO_ECRDSA is not set
# CONFIG_CRYPTO_SM2 is not set
# CONFIG_CRYPTO_CURVE25519 is not set
# end of Public-key cryptography

#
# Block ciphers
#
CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_AES_TI is not set
CONFIG_CRYPTO_ANUBIS=m
# CONFIG_CRYPTO_ARIA is not set
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_BLOWFISH_COMMON=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST_COMMON=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=m
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_GENERIC=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_TWOFISH_COMMON=m
# end of Block ciphers

#
# Length-preserving ciphers and modes
#
CONFIG_CRYPTO_ADIANTUM=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=m
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_HCTR2 is not set
CONFIG_CRYPTO_KEYWRAP=m
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_OFB=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_NHPOLY1305=y
# end of Length-preserving ciphers and modes

#
# AEAD (authenticated encryption with associated data) ciphers
#
CONFIG_CRYPTO_AEGIS128=m
# CONFIG_CRYPTO_AEGIS128_SIMD is not set
CONFIG_CRYPTO_CHACHA20POLY1305=m
CONFIG_CRYPTO_CCM=m
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=m
CONFIG_CRYPTO_ESSIV=m
# end of AEAD (authenticated encryption with associated data) ciphers

#
# Hashes, digests, and MACs
#
CONFIG_CRYPTO_BLAKE2B=m
CONFIG_CRYPTO_CMAC=m
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_SM3_GENERIC=m
# CONFIG_CRYPTO_STREEBOG is not set
CONFIG_CRYPTO_VMAC=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_XXHASH=m
# end of Hashes, digests, and MACs

#
# CRCs (cyclic redundancy checks)
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
# end of CRCs (cyclic redundancy checks)

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=m
CONFIG_CRYPTO_LZ4=m
CONFIG_CRYPTO_LZ4HC=m
CONFIG_CRYPTO_ZSTD=m
# end of Compression

#
# Random number generation
#
CONFIG_CRYPTO_ANSI_CPRNG=m
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
# end of Random number generation

#
# Userspace interface
#
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
# CONFIG_CRYPTO_STATS is not set
# end of Userspace interface

CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_NHPOLY1305_NEON=y
CONFIG_CRYPTO_CHACHA20_NEON=y

#
# Accelerated Cryptographic Algorithms for CPU (arm64)
#
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_POLY1305_NEON=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA512_ARM64_CE=y
CONFIG_CRYPTO_SHA3_ARM64=y
# CONFIG_CRYPTO_SM3_NEON is not set
CONFIG_CRYPTO_SM3_ARM64_CE=y
# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CRYPTO_SM4_ARM64_CE=y
# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
# CONFIG_CRYPTO_SM4_ARM64_CE_CCM is not set
# CONFIG_CRYPTO_SM4_ARM64_CE_GCM is not set
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
# end of Accelerated Cryptographic Algorithms for CPU (arm64)

CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_ALLWINNER=y
# CONFIG_CRYPTO_DEV_SUN4I_SS is not set
CONFIG_CRYPTO_DEV_SUN8I_CE=m
# CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG is not set
# CONFIG_CRYPTO_DEV_SUN8I_CE_HASH is not set
# CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG is not set
# CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG is not set
CONFIG_CRYPTO_DEV_SUN8I_SS=m
# CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG is not set
# CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG is not set
# CONFIG_CRYPTO_DEV_SUN8I_SS_HASH is not set
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
CONFIG_CRYPTO_DEV_CCP=y
CONFIG_CRYPTO_DEV_CCP_DD=m
CONFIG_CRYPTO_DEV_SP_CCP=y
CONFIG_CRYPTO_DEV_CCP_CRYPTO=m
# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set
# CONFIG_CRYPTO_DEV_QAT_C62X is not set
# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set
# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_VIRTIO=m
CONFIG_CRYPTO_DEV_SAFEXCEL=m
CONFIG_CRYPTO_DEV_CCREE=m
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
# CONFIG_CRYPTO_DEV_HISI_TRNG is not set
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_PKCS7_TEST_KEY is not set
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
# CONFIG_FIPS_SIGNATURE_SELFTEST is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_RAID6_PQ=m
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
# CONFIG_PACKING is not set
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=m
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
# CONFIG_INDIRECT_PIO is not set

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=m
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=m
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
CONFIG_CRYPTO_LIB_CURVE25519=m
CONFIG_CRYPTO_LIB_DES=m
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=m
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines

CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC64_ROCKSOFT=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=y
# CONFIG_CRC4 is not set
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=y
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_842_COMPRESS=m
CONFIG_842_DECOMPRESS=m
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=m
CONFIG_LZ4HC_COMPRESS=m
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=m
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
# CONFIG_XZ_DEC_SPARC is not set
# CONFIG_XZ_DEC_MICROLZMA is not set
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_REED_SOLOMON=m
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_BCH=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_BTREE=y
CONFIG_INTERVAL_TREE=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_SWIOTLB=y
# CONFIG_DMA_RESTRICTED_POOL is not set
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y
# CONFIG_DMA_PERNUMA_CMA is not set

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_DMA_MAP_BENCHMARK is not set
CONFIG_SGL_ALLOC=y
CONFIG_CHECK_SIGNATURE=y
# CONFIG_FORCE_NR_CPUS is not set
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
CONFIG_IRQ_POLL=y
CONFIG_MPILIB=y
CONFIG_DIMLIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_MEMREGION=y
CONFIG_ARCH_STACKWALK=y
CONFIG_STACKDEPOT=y
CONFIG_SBITMAP=y
# end of Library routines

CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_CALLER is not set
CONFIG_STACKTRACE_BUILD_ID=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
CONFIG_BOOT_PRINTK_DELAY=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Compile-time checks and compiler options
#
CONFIG_AS_HAS_NON_CONST_LEB128=y
CONFIG_DEBUG_INFO_NONE=y
# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_DEBUG_INFO_DWARF5 is not set
CONFIG_FRAME_WARN=1024
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_READABLE_ASM is not set
# CONFIG_HEADERS_INSTALL is not set
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_VMLINUX_MAP is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_KGDB=y
CONFIG_KGDB_HONOUR_BLOCKLIST=y
CONFIG_KGDB_SERIAL_CONSOLE=y
CONFIG_KGDB_TESTS=y
# CONFIG_KGDB_TESTS_ON_BOOT is not set
# CONFIG_KGDB_KDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_ARCH_KCSAN=y
CONFIG_HAVE_KCSAN_COMPILER=y
# CONFIG_KCSAN is not set
# end of Generic Kernel Debugging Instruments

#
# Networking Debugging
#
# CONFIG_NET_DEV_REFCNT_TRACKER is not set
# CONFIG_NET_NS_REFCNT_TRACKER is not set
# CONFIG_DEBUG_NET is not set
# end of Networking Debugging

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_SLUB_DEBUG=y
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_TABLE_CHECK is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_PER_VMA_LOCK_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SHRINKER_DEBUG is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
CONFIG_DEBUG_VM_IRQSOFF=y
CONFIG_DEBUG_VM=y
# CONFIG_DEBUG_VM_MAPLE_TREE is not set
# CONFIG_DEBUG_VM_RB is not set
# CONFIG_DEBUG_VM_PGFLAGS is not set
CONFIG_DEBUG_VM_PGTABLE=y
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
# end of Memory Debugging

# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
CONFIG_SCHED_DEBUG=y
CONFIG_SCHED_INFO=y
CONFIG_SCHEDSTATS=y
# end of Scheduler Debugging

# CONFIG_DEBUG_TIMEKEEPING is not set

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

# CONFIG_DEBUG_IRQFLAGS is not set
CONFIG_STACKTRACE=y
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set

#
# Debug kernel data structures
#
CONFIG_DEBUG_LIST=y
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# CONFIG_DEBUG_MAPLE_TREE is not set
# end of Debug kernel data structures

# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
CONFIG_TORTURE_TEST=m
# CONFIG_RCU_SCALE_TEST is not set
CONFIG_RCU_TORTURE_TEST=m
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=60
CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
# CONFIG_RCU_CPU_STALL_CPUTIME is not set
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
# CONFIG_LATENCYTOP is not set
# CONFIG_DEBUG_CGROUP_REF is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_SAMPLES is not set
CONFIG_STRICT_DEVMEM=y
# CONFIG_IO_STRICT_DEVMEM is not set

#
# arm64 Debugging
#
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
# end of arm64 Debugging

#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
CONFIG_FUNCTION_ERROR_INJECTION=y
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_ARCH_USE_MEMTEST=y
# CONFIG_MEMTEST is not set
# end of Kernel Testing and Coverage

#
# Rust hacking
#
# end of Rust hacking
# end of Kernel hacking


================================================
FILE: kernel-config/release/h6/config-6.5
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 6.5.1 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 12.3.Rel1 (Build arm-12.35)) 12.3.1 20230626"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=120301
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=24000
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=24000
CONFIG_LLD_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_PAHOLE_VERSION=125
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
CONFIG_WATCH_QUEUE=y
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_USELIB is not set
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_INJECTION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem

CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
# CONFIG_NO_HZ_FULL is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y

#
# BPF subsystem
#
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_JIT=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
CONFIG_BPF_JIT_DEFAULT_ON=y
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
CONFIG_USERMODE_DRIVER=y
# CONFIG_BPF_PRELOAD is not set
# end of BPF subsystem

CONFIG_PREEMPT_VOLUNTARY_BUILD=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
# CONFIG_PREEMPT_DYNAMIC is not set
CONFIG_SCHED_CORE=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_SCHED_AVG_IRQ=y
CONFIG_SCHED_THERMAL_PRESSURE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_PSI=y
# CONFIG_PSI_DEFAULT_DISABLED is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
# CONFIG_PRINTK_INDEX is not set
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
# CONFIG_UCLAMP_TASK is not set
# end of Scheduler features

CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_CC_HAS_INT128=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
# CONFIG_RT_GROUP_SCHED is not set
CONFIG_SCHED_MM_CID=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
# CONFIG_CGROUP_MISC is not set
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_SCHED_AUTOGROUP=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
# CONFIG_BOOT_CONFIG_FORCE is not set
# CONFIG_BOOT_CONFIG_EMBED is not set
# CONFIG_INITRAMFS_PRESERVE_MTIME is not set
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
# CONFIG_SGETMASK_SYSCALL is not set
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_SELFTEST is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
CONFIG_CACHESTAT_SYSCALL=y
# CONFIG_DEBUG_RSEQ is not set
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_GUEST_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
# end of General setup

CONFIG_ARM64=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_CONT_PTE_SHIFT=4
CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y

#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
CONFIG_ARCH_SUNXI=y
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_APPLE is not set
# CONFIG_ARCH_BCM is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SPARX5 is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_KEEMBAY is not set
# CONFIG_ARCH_MEDIATEK is not set
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_NXP is not set
# CONFIG_ARCH_MA35 is not set
# CONFIG_ARCH_NPCM is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_RENESAS is not set
# CONFIG_ARCH_ROCKCHIP is not set
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_INTEL_SOCFPGA is not set
# CONFIG_ARCH_STM32 is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
CONFIG_ARCH_VEXPRESS=y
# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZYNQMP is not set
# end of Platform selection

#
# Kernel Features
#

#
# ARM errata workarounds via the alternatives framework
#
# CONFIG_AMPERE_ERRATUM_AC03_CPU_38 is not set
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_834220=y
# CONFIG_ARM64_ERRATUM_1742098 is not set
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1319367=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
# CONFIG_ARM64_ERRATUM_2441007 is not set
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_ARM64_ERRATUM_2051678=y
CONFIG_ARM64_ERRATUM_2077057=y
# CONFIG_ARM64_ERRATUM_2658417 is not set
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
CONFIG_ARM64_ERRATUM_2054223=y
CONFIG_ARM64_ERRATUM_2067961=y
# CONFIG_ARM64_ERRATUM_2441009 is not set
# CONFIG_ARM64_ERRATUM_2457168 is not set
# CONFIG_ARM64_ERRATUM_2645198 is not set
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
CONFIG_QCOM_FALKOR_ERRATUM_1009=y
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
# CONFIG_ROCKCHIP_ERRATUM_3588001 is not set
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
# end of ARM errata workarounds via the alternatives framework

CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
# CONFIG_ARM64_VA_BITS_39 is not set
CONFIG_ARM64_VA_BITS_48=y
CONFIG_ARM64_VA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SCHED_MC=y
# CONFIG_SCHED_CLUSTER is not set
CONFIG_SCHED_SMT=y
CONFIG_NR_CPUS=8
CONFIG_HOTPLUG_CPU=y
# CONFIG_NUMA is not set
CONFIG_HZ_100=y
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=100
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_PARAVIRT=y
CONFIG_PARAVIRT_TIME_ACCOUNTING=y
CONFIG_KEXEC=y
CONFIG_KEXEC_FILE=y
# CONFIG_KEXEC_SIG is not set
# CONFIG_CRASH_DUMP is not set
CONFIG_TRANS_TABLE=y
# CONFIG_XEN is not set
CONFIG_ARCH_FORCE_MAX_ORDER=10
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y
# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y

#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
CONFIG_AS_HAS_LDAPR=y
CONFIG_AS_HAS_LSE_ATOMICS=y
CONFIG_ARM64_LSE_ATOMICS=y
CONFIG_ARM64_USE_LSE_ATOMICS=y
# end of ARMv8.1 architectural features

#
# ARMv8.2 architectural features
#
CONFIG_AS_HAS_ARMV8_2=y
CONFIG_AS_HAS_SHA3=y
# CONFIG_ARM64_PMEM is not set
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features

#
# ARMv8.3 architectural features
#
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
CONFIG_AS_HAS_ARMV8_3=y
CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
# end of ARMv8.3 architectural features

#
# ARMv8.4 architectural features
#
CONFIG_ARM64_AMU_EXTN=y
CONFIG_AS_HAS_ARMV8_4=y
CONFIG_ARM64_TLB_RANGE=y
# end of ARMv8.4 architectural features

#
# ARMv8.5 architectural features
#
CONFIG_AS_HAS_ARMV8_5=y
CONFIG_ARM64_BTI=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARM64_AS_HAS_MTE=y
CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features

#
# ARMv8.7 architectural features
#
CONFIG_ARM64_EPAN=y
# end of ARMv8.7 architectural features

CONFIG_ARM64_SVE=y
# CONFIG_ARM64_SME is not set
# CONFIG_ARM64_PSEUDO_NMI is not set
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
# end of Kernel Features

#
# Boot options
#
CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
CONFIG_CMDLINE="console=ttyAMA0"
CONFIG_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_CMDLINE_FORCE is not set
CONFIG_EFI_STUB=y
CONFIG_EFI=y
CONFIG_DMI=y
# end of Boot options

#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
CONFIG_HIBERNATE_CALLBACKS=y
CONFIG_HIBERNATION=y
CONFIG_HIBERNATION_SNAPSHOT_DEV=y
CONFIG_PM_STD_PARTITION=""
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
CONFIG_PM_DEBUG=y
# CONFIG_PM_ADVANCED_DEBUG is not set
CONFIG_PM_TEST_SUSPEND=y
CONFIG_PM_SLEEP_DEBUG=y
# CONFIG_DPM_WATCHDOG is not set
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_HIBERNATION_HEADER=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options

#
# CPU Power Management
#

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_DT_IDLE_STATES=y
CONFIG_DT_IDLE_GENPD=y

#
# ARM CPU Idle Drivers
#
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
# end of ARM CPU Idle Drivers
# end of CPU Idle

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_ACPI_CPPC_CPUFREQ=y
CONFIG_ACPI_CPPC_CPUFREQ_FIE=y
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_SCMI_CPUFREQ=y
# end of CPU Frequency scaling
# end of CPU Power Management

CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_GENERIC_GSI=y
CONFIG_ACPI_CCA_REQUIRED=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
# CONFIG_ACPI_FPDT is not set
CONFIG_ACPI_EC_DEBUGFS=y
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_VIDEO=m
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_TAD is not set
CONFIG_ACPI_DOCK=y
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_MCFG=y
CONFIG_ACPI_CPPC_LIB=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_IPMI=m
CONFIG_ACPI_HOTPLUG_CPU=y
CONFIG_ACPI_THERMAL=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_PCI_SLOT=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_CUSTOM_METHOD=y
# CONFIG_ACPI_BGRT is not set
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
CONFIG_HAVE_ACPI_APEI=y
# CONFIG_ACPI_APEI is not set
CONFIG_ACPI_CONFIGFS=m
# CONFIG_ACPI_PFRUT is not set
CONFIG_ACPI_IORT=y
CONFIG_ACPI_GTDT=y
CONFIG_ACPI_APMT=y
CONFIG_ACPI_PPTT=y
CONFIG_ACPI_PCC=y
# CONFIG_ACPI_FFH is not set
CONFIG_PMIC_OPREGION=y
# CONFIG_ACPI_PRMT is not set
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_HAVE_KVM=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_DIRTY_RING=y
CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y
CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_MMIO=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_KVM_XFER_TO_GUEST_WORK=y
CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
# CONFIG_NVHE_EL2_DEBUG is not set

#
# General architecture-dependent options
#
CONFIG_CRASH_CORE=y
CONFIG_KEXEC_CORE=y
CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y
CONFIG_HOTPLUG_CORE_SYNC=y
CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
# CONFIG_SECCOMP_CACHE_DEBUG is not set
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
# CONFIG_SHADOW_CALL_STACK is not set
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
CONFIG_HAVE_CONTEXT_TRACKING_USER=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_ARCH_HUGE_VMALLOC=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET=y
# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
CONFIG_HAVE_PREEMPT_DYNAMIC=y
CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FUNCTION_ALIGNMENT=4
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_DEBUG is not set
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS_NONE is not set
CONFIG_MODULE_COMPRESS_GZIP=y
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
# CONFIG_MODULE_DECOMPRESS is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BLK_CGROUP_RWSTAT=y
CONFIG_BLK_CGROUP_PUNT_BIO=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_ICQ=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=y
CONFIG_BLK_DEV_ZONED=y
CONFIG_BLK_DEV_THROTTLING=y
# CONFIG_BLK_DEV_THROTTLING_LOW is not set
CONFIG_BLK_WBT=y
CONFIG_BLK_WBT_MQ=y
# CONFIG_BLK_CGROUP_IOLATENCY is not set
# CONFIG_BLK_CGROUP_IOCOST is not set
CONFIG_BLK_CGROUP_IOPRIO=y
CONFIG_BLK_DEBUG_FS=y
CONFIG_BLK_DEBUG_FS_ZONED=y
CONFIG_BLK_SED_OPAL=y
# CONFIG_BLK_INLINE_ENCRYPTION is not set

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
CONFIG_AIX_PARTITION=y
CONFIG_OSF_PARTITION=y
CONFIG_AMIGA_PARTITION=y
# CONFIG_ATARI_PARTITION is not set
CONFIG_MAC_PARTITION=y
CONFIG_MSDOS_PARTITION=y
CONFIG_BSD_DISKLABEL=y
CONFIG_MINIX_SUBPARTITION=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_UNIXWARE_DISKLABEL=y
CONFIG_LDM_PARTITION=y
# CONFIG_LDM_DEBUG is not set
CONFIG_SGI_PARTITION=y
# CONFIG_ULTRIX_PARTITION is not set
CONFIG_SUN_PARTITION=y
CONFIG_KARMA_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
# CONFIG_CMDLINE_PARTITION is not set
# end of Partition Types

CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_HOLDER_DEPRECATED=y
CONFIG_BLK_MQ_STACKING=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
# CONFIG_BFQ_CGROUP_DEBUG is not set
# end of IO Schedulers

CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK=y
CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_READ_LOCK=y
CONFIG_ARCH_INLINE_READ_LOCK_BH=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_READ_UNLOCK=y
CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_WRITE_LOCK=y
CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_SPIN_TRYLOCK=y
CONFIG_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_INLINE_SPIN_LOCK=y
CONFIG_INLINE_SPIN_LOCK_BH=y
CONFIG_INLINE_SPIN_LOCK_IRQ=y
CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_INLINE_SPIN_UNLOCK_BH=y
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_READ_LOCK=y
CONFIG_INLINE_READ_LOCK_BH=y
CONFIG_INLINE_READ_LOCK_IRQ=y
CONFIG_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_INLINE_READ_UNLOCK=y
CONFIG_INLINE_READ_UNLOCK_BH=y
CONFIG_INLINE_READ_UNLOCK_IRQ=y
CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_WRITE_LOCK=y
CONFIG_INLINE_WRITE_LOCK_BH=y
CONFIG_INLINE_WRITE_LOCK_IRQ=y
CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_INLINE_WRITE_UNLOCK=y
CONFIG_INLINE_WRITE_UNLOCK_BH=y
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_HAVE_ELF_PROT=y
CONFIG_ARCH_USE_GNU_PROPERTY=y
CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=y
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_ZPOOL=y
CONFIG_SWAP=y
CONFIG_ZSWAP=y
# CONFIG_ZSWAP_DEFAULT_ON is not set
# CONFIG_ZSWAP_EXCLUSIVE_LOADS_DEFAULT_ON is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set
CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo"
CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
CONFIG_ZBUD=y
CONFIG_Z3FOLD=y
CONFIG_ZSMALLOC=y
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_ZSMALLOC_CHAIN_SIZE=8

#
# SLAB allocator options
#
# CONFIG_SLAB_DEPRECATED is not set
CONFIG_SLUB=y
# CONFIG_SLUB_TINY is not set
CONFIG_SLAB_MERGE_DEFAULT=y
CONFIG_SLAB_FREELIST_RANDOM=y
# CONFIG_SLAB_FREELIST_HARDENED is not set
# CONFIG_SLUB_STATS is not set
CONFIG_SLUB_CPU_PARTIAL=y
# end of SLAB allocator options

# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_MMU_NOTIFIER=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
# CONFIG_MEMORY_FAILURE is not set
CONFIG_ARCH_WANTS_THP_SWAP=y
# CONFIG_TRANSPARENT_HUGEPAGE is not set
CONFIG_FRONTSWAP=y
CONFIG_CMA=y
# CONFIG_CMA_DEBUG is not set
CONFIG_CMA_DEBUGFS=y
# CONFIG_CMA_SYSFS is not set
CONFIG_CMA_AREAS=7
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_ARCH_HAS_ZONE_DMA_SET=y
CONFIG_ZONE_DMA=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
CONFIG_ARCH_USES_PG_ARCH_X=y
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_TEST is not set
# CONFIG_DMAPOOL_TEST is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_SECRETMEM=y
# CONFIG_ANON_VMA_NAME is not set
# CONFIG_USERFAULTFD is not set
# CONFIG_LRU_GEN is not set
CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y
CONFIG_PER_VMA_LOCK=y
CONFIG_LOCK_MM_AND_FIND_VMA=y

#
# Data Access Monitoring
#
# CONFIG_DAMON is not set
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_EXTENSIONS=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=m
CONFIG_UNIX=y
CONFIG_UNIX_SCM=y
CONFIG_AF_UNIX_OOB=y
CONFIG_UNIX_DIAG=m
CONFIG_TLS=m
# CONFIG_TLS_DEVICE is not set
# CONFIG_TLS_TOE is not set
CONFIG_XFRM=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
# CONFIG_XFRM_INTERFACE is not set
CONFIG_XFRM_SUB_POLICY=y
CONFIG_XFRM_MIGRATE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_XFRM_AH=m
CONFIG_XFRM_ESP=m
CONFIG_XFRM_IPCOMP=m
CONFIG_NET_KEY=m
CONFIG_NET_KEY_MIGRATE=y
# CONFIG_XDP_SOCKETS is not set
CONFIG_NET_HANDSHAKE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_FIB_TRIE_STATS=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_ROUTE_CLASSID=y
# CONFIG_IP_PNP is not set
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=m
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=m
CONFIG_NET_FOU=m
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
# CONFIG_INET_ESP_OFFLOAD is not set
# CONFIG_INET_ESPINTCP is not set
CONFIG_INET_IPCOMP=m
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_DIAG=m
CONFIG_INET_TCP_DIAG=m
CONFIG_INET_UDP_DIAG=m
CONFIG_INET_RAW_DIAG=m
# CONFIG_INET_DIAG_DESTROY is not set
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_NV=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_CONG_DCTCP=m
CONFIG_TCP_CONG_CDG=m
CONFIG_TCP_CONG_BBR=m
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_TCP_MD5SIG=y
CONFIG_IPV6=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
# CONFIG_INET6_ESP_OFFLOAD is not set
# CONFIG_INET6_ESPINTCP is not set
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_MIP6=y
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=m
CONFIG_INET6_TUNNEL=m
CONFIG_IPV6_VTI=m
CONFIG_IPV6_SIT=m
CONFIG_IPV6_SIT_6RD=y
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=m
CONFIG_IPV6_GRE=m
CONFIG_IPV6_FOU=m
CONFIG_IPV6_FOU_TUNNEL=m
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
CONFIG_IPV6_SEG6_LWTUNNEL=y
CONFIG_IPV6_SEG6_HMAC=y
CONFIG_IPV6_SEG6_BPF=y
# CONFIG_IPV6_RPL_LWTUNNEL is not set
# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
CONFIG_NETLABEL=y
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=m
CONFIG_MPTCP_IPV6=y
# CONFIG_NETWORK_SECMARK is not set
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NETWORK_PHY_TIMESTAMPING=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_EGRESS=y
CONFIG_NETFILTER_SKIP_EGRESS=y
CONFIG_NETFILTER_NETLINK=m
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
CONFIG_NETFILTER_BPF_LINK=y
CONFIG_NETFILTER_NETLINK_HOOK=m
CONFIG_NETFILTER_NETLINK_ACCT=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NETFILTER_NETLINK_OSF=m
CONFIG_NF_CONNTRACK=m
CONFIG_NF_LOG_SYSLOG=m
CONFIG_NETFILTER_CONNCOUNT=m
CONFIG_NF_CONNTRACK_MARK=y
CONFIG_NF_CONNTRACK_ZONES=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_TIMEOUT=y
CONFIG_NF_CONNTRACK_TIMESTAMP=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CONNTRACK_OVS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_CT_NETLINK_TIMEOUT=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=m
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NF_NAT_OVS=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=m
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
CONFIG_NFT_OSF=m
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NF_DUP_NETDEV=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NFT_REJECT_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
# CONFIG_NF_FLOW_TABLE_PROCFS is not set
CONFIG_NETFILTER_XTABLES=y
CONFIG_NETFILTER_XTABLES_COMPAT=y

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=m
CONFIG_NETFILTER_XT_CONNMARK=m
CONFIG_NETFILTER_XT_SET=m

#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_AUDIT=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LED=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=m
CONFIG_NETFILTER_XT_TARGET_NETMAP=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
CONFIG_NETFILTER_XT_TARGET_RATEEST=m
CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=m
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# end of Core Netfilter Configuration

CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
# CONFIG_IP_VS_DEBUG is not set
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m
# CONFIG_IP_VS_TWOS is not set

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=m
CONFIG_NF_SOCKET_IPV4=m
CONFIG_NF_TPROXY_IPV4=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=y
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_SECURITY=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP6_NF_SECURITY=m
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=m
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_NFT_BRIDGE_META=m
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
CONFIG_BPFILTER=y
CONFIG_BPFILTER_UMH=m
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m

#
# DCCP CCIDs Configuration
#
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
CONFIG_IP_DCCP_CCID3=y
# CONFIG_IP_DCCP_CCID3_DEBUG is not set
CONFIG_IP_DCCP_TFRC_LIB=y
# end of DCCP CCIDs Configuration

#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
# end of DCCP Kernel Hacking

CONFIG_IP_SCTP=m
# CONFIG_SCTP_DBG_OBJCNT is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5 is not set
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=m
CONFIG_RDS=m
CONFIG_RDS_TCP=m
# CONFIG_RDS_DEBUG is not set
CONFIG_TIPC=m
CONFIG_TIPC_MEDIA_UDP=y
CONFIG_TIPC_CRYPTO=y
CONFIG_TIPC_DIAG=m
CONFIG_ATM=m
CONFIG_ATM_CLIP=m
# CONFIG_ATM_CLIP_NO_ICMP is not set
CONFIG_ATM_LANE=m
# CONFIG_ATM_MPOA is not set
CONFIG_ATM_BR2684=m
# CONFIG_ATM_BR2684_IPFILTER is not set
CONFIG_L2TP=m
CONFIG_L2TP_DEBUGFS=m
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=m
CONFIG_L2TP_ETH=m
CONFIG_STP=m
CONFIG_GARP=m
CONFIG_MRP=m
CONFIG_BRIDGE=m
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
# CONFIG_BRIDGE_MRP is not set
# CONFIG_BRIDGE_CFM is not set
CONFIG_NET_DSA=m
CONFIG_NET_DSA_TAG_NONE=m
# CONFIG_NET_DSA_TAG_AR9331 is not set
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
CONFIG_NET_DSA_TAG_BRCM=m
CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
# CONFIG_NET_DSA_TAG_HELLCREEK is not set
# CONFIG_NET_DSA_TAG_GSWIP is not set
CONFIG_NET_DSA_TAG_DSA_COMMON=m
CONFIG_NET_DSA_TAG_DSA=m
CONFIG_NET_DSA_TAG_EDSA=m
# CONFIG_NET_DSA_TAG_MTK is not set
# CONFIG_NET_DSA_TAG_KSZ is not set
# CONFIG_NET_DSA_TAG_OCELOT is not set
# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set
CONFIG_NET_DSA_TAG_QCA=m
# CONFIG_NET_DSA_TAG_RTL4_A is not set
# CONFIG_NET_DSA_TAG_RTL8_4 is not set
# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set
# CONFIG_NET_DSA_TAG_LAN9303 is not set
# CONFIG_NET_DSA_TAG_SJA1105 is not set
CONFIG_NET_DSA_TAG_TRAILER=m
# CONFIG_NET_DSA_TAG_XRS700X is not set
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q_MVRP=y
CONFIG_LLC=m
# CONFIG_LLC2 is not set
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
CONFIG_6LOWPAN=m
# CONFIG_6LOWPAN_DEBUGFS is not set
CONFIG_6LOWPAN_NHC=m
CONFIG_6LOWPAN_NHC_DEST=m
CONFIG_6LOWPAN_NHC_FRAGMENT=m
CONFIG_6LOWPAN_NHC_HOP=m
CONFIG_6LOWPAN_NHC_IPV6=m
CONFIG_6LOWPAN_NHC_MOBILITY=m
CONFIG_6LOWPAN_NHC_ROUTING=m
CONFIG_6LOWPAN_NHC_UDP=m
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
CONFIG_6LOWPAN_GHC_UDP=m
CONFIG_6LOWPAN_GHC_ICMPV6=m
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
CONFIG_IEEE802154=m
# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set
CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_MAC802154=m
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFB=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_MQPRIO_LIB=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_SKBPRIO=m
CONFIG_NET_SCH_CHOKE=m
CONFIG_NET_SCH_QFQ=m
CONFIG_NET_SCH_CODEL=m
CONFIG_NET_SCH_FQ_CODEL=y
CONFIG_NET_SCH_CAKE=m
CONFIG_NET_SCH_FQ=m
CONFIG_NET_SCH_HHF=m
CONFIG_NET_SCH_PIE=m
CONFIG_NET_SCH_FQ_PIE=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_SCH_PLUG=m
CONFIG_NET_SCH_ETS=m
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_PERF=y
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=y
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_EMATCH_CANID=m
CONFIG_NET_EMATCH_IPSET=m
CONFIG_NET_EMATCH_IPT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_SAMPLE=m
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
# CONFIG_NET_ACT_MPLS is not set
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_NET_ACT_CONNMARK=m
CONFIG_NET_ACT_CTINFO=m
CONFIG_NET_ACT_SKBMOD=m
CONFIG_NET_ACT_IFE=m
CONFIG_NET_ACT_TUNNEL_KEY=m
CONFIG_NET_ACT_CT=m
CONFIG_NET_ACT_GATE=m
CONFIG_NET_IFE_SKBMARK=m
CONFIG_NET_IFE_SKBPRIO=m
CONFIG_NET_IFE_SKBTCINDEX=m
# CONFIG_NET_TC_SKB_EXT is not set
CONFIG_NET_SCH_FIFO=y
CONFIG_DCB=y
CONFIG_DNS_RESOLVER=y
CONFIG_BATMAN_ADV=m
# CONFIG_BATMAN_ADV_BATMAN_V is not set
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
CONFIG_BATMAN_ADV_NC=y
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUG is not set
CONFIG_OPENVSWITCH=m
CONFIG_OPENVSWITCH_GRE=m
CONFIG_OPENVSWITCH_VXLAN=m
CONFIG_OPENVSWITCH_GENEVE=m
CONFIG_VSOCKETS=m
CONFIG_VSOCKETS_DIAG=m
CONFIG_VSOCKETS_LOOPBACK=m
CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO_VSOCKETS_COMMON=m
CONFIG_NETLINK_DIAG=m
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=m
CONFIG_MPLS_ROUTING=m
# CONFIG_MPLS_IPTUNNEL is not set
CONFIG_NET_NSH=m
# CONFIG_HSR is not set
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=m
CONFIG_QRTR_SMD=m
CONFIG_QRTR_TUN=m
# CONFIG_NET_NCSI is not set
CONFIG_PCPU_DEV_REFCNT=y
CONFIG_MAX_SKB_FRAGS=17
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_XPS=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
CONFIG_NET_PKTGEN=m
# end of Network testing
# end of Networking options

CONFIG_HAMRADIO=y

#
# Packet Radio protocols
#
CONFIG_AX25=m
CONFIG_AX25_DAMA_SLAVE=y
CONFIG_NETROM=m
CONFIG_ROSE=m

#
# AX.25 network device drivers
#
CONFIG_MKISS=m
CONFIG_6PACK=m
CONFIG_BPQETHER=m
CONFIG_BAYCOM_SER_FDX=m
CONFIG_BAYCOM_SER_HDX=m
CONFIG_YAM=m
# end of AX.25 network device drivers

CONFIG_CAN=m
CONFIG_CAN_RAW=m
CONFIG_CAN_BCM=m
CONFIG_CAN_GW=m
# CONFIG_CAN_J1939 is not set
# CONFIG_CAN_ISOTP is not set
CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
# CONFIG_BT_HIDP is not set
CONFIG_BT_HS=y
CONFIG_BT_LE=y
CONFIG_BT_LE_L2CAP_ECRED=y
CONFIG_BT_6LOWPAN=m
# CONFIG_BT_LEDS is not set
# CONFIG_BT_MSFTEXT is not set
# CONFIG_BT_AOSPEXT is not set
# CONFIG_BT_DEBUGFS is not set
# CONFIG_BT_SELFTEST is not set

#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=m
CONFIG_BT_BCM=m
CONFIG_BT_RTL=m
CONFIG_BT_QCA=m
CONFIG_BT_HCIBTUSB=m
# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
CONFIG_BT_HCIBTUSB_POLL_SYNC=y
CONFIG_BT_HCIBTUSB_BCM=y
# CONFIG_BT_HCIBTUSB_MTK is not set
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
# CONFIG_BT_HCIUART_NOKIA is not set
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_BCM=y
# CONFIG_BT_HCIUART_RTL is not set
CONFIG_BT_HCIUART_QCA=y
# CONFIG_BT_HCIUART_AG6XX is not set
CONFIG_BT_HCIUART_MRVL=y
CONFIG_BT_HCIBCM203X=m
# CONFIG_BT_HCIBCM4377 is not set
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
# CONFIG_BT_MTKSDIO is not set
# CONFIG_BT_MTKUART is not set
CONFIG_BT_HCIRSI=m
# CONFIG_BT_VIRTIO is not set
# CONFIG_BT_NXPUART is not set
# end of Bluetooth device drivers

# CONFIG_AF_RXRPC is not set
# CONFIG_AF_KCM is not set
CONFIG_STREAM_PARSER=y
# CONFIG_MCTP is not set
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_SPY=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_DEFAULT_PS=y
CONFIG_CFG80211_DEBUGFS=y
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_CFG80211_WEXT_EXPORT=y
CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
CONFIG_LIB80211_CRYPT_TKIP=m
# CONFIG_LIB80211_DEBUG is not set
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
CONFIG_MAC80211_DEBUGFS=y
# CONFIG_MAC80211_MESSAGE_TRACING is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_RFKILL=m
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=m
CONFIG_NET_9P=m
CONFIG_NET_9P_FD=m
CONFIG_NET_9P_VIRTIO=m
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
CONFIG_CEPH_LIB=m
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
CONFIG_NFC=m
CONFIG_NFC_DIGITAL=m
CONFIG_NFC_NCI=m
# CONFIG_NFC_NCI_SPI is not set
# CONFIG_NFC_NCI_UART is not set
CONFIG_NFC_HCI=m
CONFIG_NFC_SHDLC=y

#
# Near Field Communication (NFC) devices
#
# CONFIG_NFC_TRF7970A is not set
CONFIG_NFC_SIM=m
CONFIG_NFC_PORT100=m
# CONFIG_NFC_VIRTUAL_NCI is not set
# CONFIG_NFC_FDP is not set
CONFIG_NFC_PN544=m
CONFIG_NFC_PN544_I2C=m
# CONFIG_NFC_PN533_USB is not set
# CONFIG_NFC_PN533_I2C is not set
# CONFIG_NFC_PN532_UART is not set
CONFIG_NFC_MICROREAD=m
CONFIG_NFC_MICROREAD_I2C=m
CONFIG_NFC_MRVL=m
CONFIG_NFC_MRVL_USB=m
# CONFIG_NFC_MRVL_I2C is not set
CONFIG_NFC_ST21NFCA=m
CONFIG_NFC_ST21NFCA_I2C=m
# CONFIG_NFC_ST_NCI_I2C is not set
# CONFIG_NFC_ST_NCI_SPI is not set
# CONFIG_NFC_NXP_NCI is not set
CONFIG_NFC_S3FWRN5=m
CONFIG_NFC_S3FWRN5_I2C=m
# CONFIG_NFC_S3FWRN82_UART is not set
# CONFIG_NFC_ST95HF is not set
# end of Near Field Communication (NFC) devices

CONFIG_PSAMPLE=m
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_FAILOVER=m
CONFIG_ETHTOOL_NETLINK=y

#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
CONFIG_PCIEPORTBUS=y
CONFIG_HOTPLUG_PCI_PCIE=y
CONFIG_PCIEAER=y
CONFIG_PCIEAER_INJECT=m
CONFIG_PCIE_ECRC=y
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
# CONFIG_PCIEASPM_PERFORMANCE is not set
CONFIG_PCIE_PME=y
# CONFIG_PCIE_DPC is not set
# CONFIG_PCIE_PTM is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
CONFIG_PCI_STUB=y
# CONFIG_PCI_PF_STUB is not set
CONFIG_PCI_ATS=y
CONFIG_PCI_ECAM=y
CONFIG_PCI_IOV=y
CONFIG_PCI_PRI=y
CONFIG_PCI_PASID=y
CONFIG_PCI_LABEL=y
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
CONFIG_HOTPLUG_PCI=y
CONFIG_HOTPLUG_PCI_ACPI=y
# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
# CONFIG_HOTPLUG_PCI_CPCI is not set
# CONFIG_HOTPLUG_PCI_SHPC is not set

#
# PCI controller drivers
#
# CONFIG_PCIE_ALTERA is not set
# CONFIG_PCI_HOST_THUNDER_PEM is not set
# CONFIG_PCI_HOST_THUNDER_ECAM is not set
# CONFIG_PCI_FTPCI100 is not set
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
# CONFIG_PCIE_MICROCHIP_HOST is not set
CONFIG_PCI_XGENE=y
CONFIG_PCI_XGENE_MSI=y
# CONFIG_PCIE_XILINX is not set

#
# Cadence-based PCIe controllers
#
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCI_J721E_HOST is not set
# end of Cadence-based PCIe controllers

#
# DesignWare-based PCIe controllers
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
# CONFIG_PCIE_AL is not set
CONFIG_PCI_MESON=y
CONFIG_PCI_HISI=y
# CONFIG_PCIE_KIRIN is not set
CONFIG_PCIE_DW_PLAT=y
CONFIG_PCIE_DW_PLAT_HOST=y
# end of DesignWare-based PCIe controllers

#
# Mobiveil-based PCIe controllers
#
# end of Mobiveil-based PCIe controllers
# end of PCI controller drivers

#
# PCI Endpoint
#
# CONFIG_PCI_ENDPOINT is not set
# end of PCI Endpoint

#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set
# end of PCI switch controller drivers

# CONFIG_CXL_BUS is not set
# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
CONFIG_AUXILIARY_BUS=y
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_DEVTMPFS_SAFE is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_DEBUG=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_FW_LOADER_USER_HELPER is not set
# CONFIG_FW_LOADER_COMPRESS is not set
CONFIG_FW_CACHE=y
# CONFIG_FW_UPLOAD is not set
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
CONFIG_DEBUG_DEVRES=y
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SLIMBUS=m
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_SPMI=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SOUNDWIRE=m
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
# CONFIG_BRCMSTB_GISB_ARB is not set
# CONFIG_MOXTET is not set
CONFIG_SUN50I_DE2_BUS=y
CONFIG_SUNXI_RSB=y
CONFIG_VEXPRESS_CONFIG=y
# CONFIG_MHI_BUS is not set
# CONFIG_MHI_BUS_EP is not set
# end of Bus devices

CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y

#
# Firmware Drivers
#

#
# ARM System Control and Management Interface Protocol
#
CONFIG_ARM_SCMI_PROTOCOL=y
# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
CONFIG_ARM_SCMI_HAVE_SHMEM=y
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set
CONFIG_ARM_SCMI_POWER_DOMAIN=y
# CONFIG_ARM_SCMI_POWER_CONTROL is not set
# end of ARM System Control and Management Interface Protocol

CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
# CONFIG_FIRMWARE_MEMMAP is not set
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=y
# CONFIG_ISCSI_IBFT is not set
# CONFIG_FW_CFG_SYSFS is not set
CONFIG_SYSFB=y
# CONFIG_SYSFB_SIMPLEFB is not set
CONFIG_ARM_FFA_TRANSPORT=m
CONFIG_ARM_FFA_SMCCC=y
# CONFIG_GOOGLE_FIRMWARE is not set

#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_VARS_PSTORE=y
CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_GENERIC_STUB=y
# CONFIG_EFI_ZBOOT is not set
# CONFIG_EFI_ARMSTUB_DTB_LOADER is not set
CONFIG_EFI_BOOTLOADER_CONTROL=y
# CONFIG_EFI_CAPSULE_LOADER is not set
# CONFIG_EFI_TEST is not set
# CONFIG_RESET_ATTACK_MITIGATION is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
# CONFIG_EFI_DISABLE_RUNTIME is not set
# CONFIG_EFI_COCO_SECRET is not set
# end of EFI (Extensible Firmware Interface) Support

CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_PSCI_CHECKER is not set
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_ARM_SMCCC_SOC_ID=y

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_GNSS=m
CONFIG_GNSS_SERIAL=m
CONFIG_GNSS_MTK_SERIAL=m
# CONFIG_GNSS_SIRF_SERIAL is not set
# CONFIG_GNSS_UBX_SERIAL is not set
# CONFIG_GNSS_USB is not set
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_OF_PARTS=m
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=m
CONFIG_MTD_BLOCK=m
# CONFIG_MTD_BLOCK_RO is not set

#
# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
#
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=m
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=m
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
CONFIG_MTD_CFI_INTELEXT=m
CONFIG_MTD_CFI_AMDSTD=m
CONFIG_MTD_CFI_STAA=m
CONFIG_MTD_CFI_UTIL=m
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=m
# CONFIG_MTD_PHYSMAP_COMPAT is not set
CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_PHYSMAP_VERSATILE is not set
# CONFIG_MTD_PHYSMAP_GEMINI is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_MCHP48L640 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
CONFIG_MTD_NAND_CORE=y
# CONFIG_MTD_ONENAND is not set
CONFIG_MTD_RAW_NAND=y

#
# Raw/parallel NAND flash controllers
#
# CONFIG_MTD_NAND_DENALI_PCI is not set
# CONFIG_MTD_NAND_DENALI_DT is not set
# CONFIG_MTD_NAND_CAFE is not set
# CONFIG_MTD_NAND_BRCMNAND is not set
# CONFIG_MTD_NAND_SUNXI is not set
# CONFIG_MTD_NAND_MXIC is not set
# CONFIG_MTD_NAND_GPIO is not set
# CONFIG_MTD_NAND_PLATFORM is not set
# CONFIG_MTD_NAND_CADENCE is not set
# CONFIG_MTD_NAND_ARASAN is not set
# CONFIG_MTD_NAND_INTEL_LGM is not set

#
# Misc
#
# CONFIG_MTD_NAND_NANDSIM is not set
# CONFIG_MTD_NAND_RICOH is not set
# CONFIG_MTD_NAND_DISKONCHIP is not set
# CONFIG_MTD_SPI_NAND is not set

#
# ECC engine support
#
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
CONFIG_MTD_NAND_ECC_SW_BCH=y
# CONFIG_MTD_NAND_ECC_MXIC is not set
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
# CONFIG_MTD_UBI_BLOCK is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_NULL_BLK=m
CONFIG_CDROM=y
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
CONFIG_ZRAM=m
CONFIG_ZRAM_DEF_COMP_LZORLE=y
# CONFIG_ZRAM_DEF_COMP_ZSTD is not set
# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
# CONFIG_ZRAM_DEF_COMP_LZO is not set
# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
# CONFIG_ZRAM_DEF_COMP_842 is not set
CONFIG_ZRAM_DEF_COMP="lzo-rle"
CONFIG_ZRAM_WRITEBACK=y
CONFIG_ZRAM_MEMORY_TRACKING=y
# CONFIG_ZRAM_MULTI_COMP is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=128
CONFIG_BLK_DEV_DRBD=m
# CONFIG_DRBD_FAULT_INJECTION is not set
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=m
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_CDROM_PKTCDVD=m
CONFIG_CDROM_PKTCDVD_BUFFERS=8
# CONFIG_CDROM_PKTCDVD_WCACHE is not set
CONFIG_ATA_OVER_ETH=m
CONFIG_VIRTIO_BLK=y
CONFIG_BLK_DEV_RBD=m
# CONFIG_BLK_DEV_UBLK is not set

#
# NVME Support
#
CONFIG_NVME_CORE=m
CONFIG_BLK_DEV_NVME=m
CONFIG_NVME_MULTIPATH=y
# CONFIG_NVME_VERBOSE_ERRORS is not set
# CONFIG_NVME_HWMON is not set
# CONFIG_NVME_FC is not set
# CONFIG_NVME_TCP is not set
# CONFIG_NVME_AUTH is not set
# CONFIG_NVME_TARGET is not set
# end of NVME Support

#
# Misc devices
#
CONFIG_SENSORS_LIS3LV02D=m
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
CONFIG_TIFM_CORE=y
CONFIG_TIFM_7XX1=m
# CONFIG_ICS932S401 is not set
CONFIG_ENCLOSURE_SERVICES=m
# CONFIG_HI6421V600_IRQ is not set
# CONFIG_HP_ILO is not set
CONFIG_APDS9802ALS=m
CONFIG_ISL29003=m
CONFIG_ISL29020=m
CONFIG_SENSORS_TSL2550=m
CONFIG_SENSORS_BH1770=m
CONFIG_SENSORS_APDS990X=m
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
# CONFIG_DW_XDATA_PCIE is not set
CONFIG_PCI_ENDPOINT_TEST=m
# CONFIG_XILINX_SDFEC is not set
# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_OPEN_DICE is not set
# CONFIG_VCPU_STALL_DETECTOR is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
CONFIG_EEPROM_AT24=m
# CONFIG_EEPROM_AT25 is not set
CONFIG_EEPROM_LEGACY=m
CONFIG_EEPROM_MAX6875=m
CONFIG_EEPROM_93CX6=m
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

CONFIG_CB710_CORE=y
# CONFIG_CB710_DEBUG is not set
CONFIG_CB710_DEBUG_ASSUMPTIONS=y

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline

CONFIG_SENSORS_LIS3_I2C=m
CONFIG_ALTERA_STAPL=m
# CONFIG_VMWARE_VMCI is not set
# CONFIG_GENWQE is not set
CONFIG_ECHO=m
# CONFIG_BCM_VK is not set
# CONFIG_MISC_ALCOR_PCI is not set
# CONFIG_MISC_RTSX_PCI is not set
# CONFIG_MISC_RTSX_USB is not set
CONFIG_UACCE=m
# CONFIG_PVPANIC is not set
# CONFIG_GP_PCI1XXXX is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
CONFIG_RAID_ATTRS=m
CONFIG_SCSI_COMMON=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_NETLINK=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=m
CONFIG_BLK_DEV_SR=y
CONFIG_CHR_DEV_SG=y
CONFIG_BLK_DEV_BSG=y
CONFIG_CHR_DEV_SCH=m
CONFIG_SCSI_ENCLOSURE=m
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y

#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=m
CONFIG_SCSI_FC_ATTRS=m
CONFIG_SCSI_ISCSI_ATTRS=m
CONFIG_SCSI_SAS_ATTRS=m
CONFIG_SCSI_SAS_LIBSAS=m
CONFIG_SCSI_SAS_ATA=y
CONFIG_SCSI_SAS_HOST_SMP=y
CONFIG_SCSI_SRP_ATTRS=m
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_ISCSI_BOOT_SYSFS=m
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
CONFIG_SCSI_BNX2_ISCSI=m
CONFIG_SCSI_BNX2X_FCOE=m
CONFIG_BE2ISCSI=m
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
CONFIG_SCSI_HPSA=m
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
CONFIG_SCSI_MVSAS=m
# CONFIG_SCSI_MVSAS_DEBUG is not set
CONFIG_SCSI_MVSAS_TASKLET=y
CONFIG_SCSI_MVUMI=m
# CONFIG_SCSI_ADVANSYS is not set
CONFIG_SCSI_ARCMSR=m
CONFIG_SCSI_ESAS2R=m
CONFIG_MEGARAID_NEWGEN=y
CONFIG_MEGARAID_MM=m
CONFIG_MEGARAID_MAILBOX=m
CONFIG_MEGARAID_LEGACY=m
CONFIG_MEGARAID_SAS=m
CONFIG_SCSI_MPT3SAS=m
CONFIG_SCSI_MPT2SAS_MAX_SGE=128
CONFIG_SCSI_MPT3SAS_MAX_SGE=128
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_MPI3MR is not set
# CONFIG_SCSI_SMARTPQI is not set
CONFIG_SCSI_HPTIOP=m
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
CONFIG_LIBFC=m
CONFIG_LIBFCOE=m
CONFIG_FCOE=m
CONFIG_SCSI_SNIC=m
# CONFIG_SCSI_SNIC_DEBUG_FS is not set
CONFIG_SCSI_DMX3191D=m
# CONFIG_SCSI_FDOMAIN_PCI is not set
# CONFIG_SCSI_IPS is not set
CONFIG_SCSI_INITIO=m
CONFIG_SCSI_INIA100=m
CONFIG_SCSI_STEX=m
CONFIG_SCSI_SYM53C8XX_2=m
CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
CONFIG_SCSI_SYM53C8XX_MMIO=y
CONFIG_SCSI_IPR=m
CONFIG_SCSI_IPR_TRACE=y
CONFIG_SCSI_IPR_DUMP=y
CONFIG_SCSI_QLOGIC_1280=m
CONFIG_SCSI_QLA_FC=m
CONFIG_TCM_QLA2XXX=m
# CONFIG_TCM_QLA2XXX_DEBUG is not set
CONFIG_SCSI_QLA_ISCSI=m
# CONFIG_SCSI_LPFC is not set
# CONFIG_SCSI_EFCT is not set
CONFIG_SCSI_DC395x=m
CONFIG_SCSI_AM53C974=m
CONFIG_SCSI_WD719X=m
CONFIG_SCSI_DEBUG=m
CONFIG_SCSI_PMCRAID=m
# CONFIG_SCSI_PM8001 is not set
# CONFIG_SCSI_BFA_FC is not set
CONFIG_SCSI_VIRTIO=y
CONFIG_SCSI_CHELSIO_FCOE=m
CONFIG_SCSI_DH=y
CONFIG_SCSI_DH_RDAC=m
CONFIG_SCSI_DH_HP_SW=m
CONFIG_SCSI_DH_EMC=m
CONFIG_SCSI_DH_ALUA=m
# end of SCSI device support

CONFIG_ATA=y
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=y
# CONFIG_AHCI_DWC is not set
# CONFIG_AHCI_CEVA is not set
CONFIG_AHCI_SUNXI=y
CONFIG_SATA_INIC162X=m
CONFIG_SATA_ACARD_AHCI=m
CONFIG_SATA_SIL24=y
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#
CONFIG_PDC_ADMA=m
CONFIG_SATA_QSTOR=m
CONFIG_SATA_SX4=m
CONFIG_ATA_BMDMA=y

#
# SATA SFF controllers with BMDMA
#
CONFIG_ATA_PIIX=y
# CONFIG_SATA_DWC is not set
CONFIG_SATA_MV=m
CONFIG_SATA_NV=m
CONFIG_SATA_PROMISE=m
CONFIG_SATA_SIL=m
CONFIG_SATA_SIS=m
CONFIG_SATA_SVW=m
CONFIG_SATA_ULI=m
CONFIG_SATA_VIA=m
CONFIG_SATA_VITESSE=m

#
# PATA SFF controllers with BMDMA
#
CONFIG_PATA_ALI=m
CONFIG_PATA_AMD=m
CONFIG_PATA_ARTOP=m
CONFIG_PATA_ATIIXP=m
CONFIG_PATA_ATP867X=m
CONFIG_PATA_CMD64X=m
CONFIG_PATA_CYPRESS=m
CONFIG_PATA_EFAR=m
CONFIG_PATA_HPT366=m
CONFIG_PATA_HPT37X=m
CONFIG_PATA_HPT3X2N=m
CONFIG_PATA_HPT3X3=m
# CONFIG_PATA_HPT3X3_DMA is not set
CONFIG_PATA_IT8213=m
CONFIG_PATA_IT821X=m
CONFIG_PATA_JMICRON=m
CONFIG_PATA_MARVELL=m
CONFIG_PATA_NETCELL=m
CONFIG_PATA_NINJA32=m
CONFIG_PATA_NS87415=m
CONFIG_PATA_OLDPIIX=m
CONFIG_PATA_OPTIDMA=m
CONFIG_PATA_PDC2027X=m
CONFIG_PATA_PDC_OLD=m
# CONFIG_PATA_RADISYS is not set
CONFIG_PATA_RDC=m
CONFIG_PATA_SCH=m
CONFIG_PATA_SERVERWORKS=m
CONFIG_PATA_SIL680=m
CONFIG_PATA_SIS=m
CONFIG_PATA_TOSHIBA=m
CONFIG_PATA_TRIFLEX=m
CONFIG_PATA_VIA=m
CONFIG_PATA_WINBOND=m

#
# PIO-only SFF controllers
#
CONFIG_PATA_CMD640_PCI=m
CONFIG_PATA_MPIIX=m
CONFIG_PATA_NS87410=m
CONFIG_PATA_OPTI=m
CONFIG_PATA_PLATFORM=y
CONFIG_PATA_OF_PLATFORM=y
# CONFIG_PATA_RZ1000 is not set

#
# Generic fallback / legacy drivers
#
# CONFIG_PATA_ACPI is not set
CONFIG_ATA_GENERIC=m
# CONFIG_PATA_LEGACY is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=y
CONFIG_MD_AUTODETECT=y
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
CONFIG_MD_CLUSTER=m
CONFIG_BCACHE=m
# CONFIG_BCACHE_DEBUG is not set
# CONFIG_BCACHE_CLOSURES_DEBUG is not set
# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_DEBUG=y
CONFIG_DM_BUFIO=y
# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
# CONFIG_DM_UNSTRIPED is not set
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=y
CONFIG_DM_THIN_PROVISIONING=m
CONFIG_DM_CACHE=m
CONFIG_DM_CACHE_SMQ=m
CONFIG_DM_WRITECACHE=m
# CONFIG_DM_EBS is not set
# CONFIG_DM_ERA is not set
# CONFIG_DM_CLONE is not set
CONFIG_DM_MIRROR=y
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=y
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
# CONFIG_DM_MULTIPATH_HST is not set
# CONFIG_DM_MULTIPATH_IOA is not set
CONFIG_DM_DELAY=m
CONFIG_DM_DUST=m
CONFIG_DM_INIT=y
CONFIG_DM_UEVENT=y
CONFIG_DM_FLAKEY=m
CONFIG_DM_VERITY=m
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
CONFIG_DM_VERITY_FEC=y
CONFIG_DM_SWITCH=m
CONFIG_DM_LOG_WRITES=m
CONFIG_DM_INTEGRITY=m
CONFIG_DM_ZONED=m
CONFIG_DM_AUDIT=y
CONFIG_TARGET_CORE=m
CONFIG_TCM_IBLOCK=m
CONFIG_TCM_FILEIO=m
CONFIG_TCM_PSCSI=m
CONFIG_TCM_USER2=m
CONFIG_LOOPBACK_TARGET=m
CONFIG_TCM_FC=m
CONFIG_ISCSI_TARGET=m
# CONFIG_REMOTE_TARGET is not set
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
CONFIG_FIREWIRE_NOSY=m
# end of IEEE 1394 (FireWire) support

CONFIG_NETDEVICES=y
CONFIG_MII=m
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_WIREGUARD=m
# CONFIG_WIREGUARD_DEBUG is not set
CONFIG_EQUALIZER=m
CONFIG_NET_FC=y
CONFIG_IFB=m
CONFIG_NET_TEAM=m
CONFIG_NET_TEAM_MODE_BROADCAST=m
CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
CONFIG_NET_TEAM_MODE_RANDOM=m
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
CONFIG_NET_TEAM_MODE_LOADBALANCE=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=m
CONFIG_IPVTAP=m
CONFIG_VXLAN=m
CONFIG_GENEVE=m
# CONFIG_BAREUDP is not set
# CONFIG_GTP is not set
# CONFIG_AMT is not set
# CONFIG_MACSEC is not set
CONFIG_NETCONSOLE=m
CONFIG_NETCONSOLE_DYNAMIC=y
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=m
CONFIG_TAP=m
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_NLMON=m
CONFIG_NET_VRF=m
# CONFIG_VSOCKMON is not set
# CONFIG_ARCNET is not set
# CONFIG_ATM_DRIVERS is not set

#
# Distributed Switch Architecture drivers
#
CONFIG_B53=m
# CONFIG_B53_SPI_DRIVER is not set
# CONFIG_B53_MDIO_DRIVER is not set
# CONFIG_B53_MMAP_DRIVER is not set
# CONFIG_B53_SRAB_DRIVER is not set
# CONFIG_B53_SERDES is not set
CONFIG_NET_DSA_BCM_SF2=m
# CONFIG_NET_DSA_LOOP is not set
# CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK is not set
# CONFIG_NET_DSA_LANTIQ_GSWIP is not set
# CONFIG_NET_DSA_MT7530 is not set
CONFIG_NET_DSA_MV88E6060=m
# CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON is not set
CONFIG_NET_DSA_MV88E6XXX=m
CONFIG_NET_DSA_MV88E6XXX_PTP=y
# CONFIG_NET_DSA_MSCC_OCELOT_EXT is not set
# CONFIG_NET_DSA_MSCC_SEVILLE is not set
# CONFIG_NET_DSA_AR9331 is not set
CONFIG_NET_DSA_QCA8K=m
# CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT is not set
# CONFIG_NET_DSA_SJA1105 is not set
# CONFIG_NET_DSA_XRS700X_I2C is not set
# CONFIG_NET_DSA_XRS700X_MDIO is not set
# CONFIG_NET_DSA_REALTEK is not set
# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set
# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set
# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set
# end of Distributed Switch Architecture drivers

CONFIG_ETHERNET=y
CONFIG_MDIO=m
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
CONFIG_NET_VENDOR_AGERE=y
CONFIG_ET131X=m
CONFIG_NET_VENDOR_ALACRITECH=y
# CONFIG_SLICOSS is not set
CONFIG_NET_VENDOR_ALLWINNER=y
# CONFIG_SUN4I_EMAC is not set
CONFIG_NET_VENDOR_ALTEON=y
CONFIG_ACENIC=m
# CONFIG_ACENIC_OMIT_TIGON_I is not set
CONFIG_ALTERA_TSE=m
CONFIG_NET_VENDOR_AMAZON=y
# CONFIG_ENA_ETHERNET is not set
CONFIG_NET_VENDOR_AMD=y
CONFIG_AMD8111_ETH=m
CONFIG_PCNET32=m
CONFIG_AMD_XGBE=m
# CONFIG_AMD_XGBE_DCB is not set
# CONFIG_PDS_CORE is not set
CONFIG_NET_VENDOR_AQUANTIA=y
CONFIG_AQTION=m
CONFIG_NET_VENDOR_ARC=y
CONFIG_NET_VENDOR_ASIX=y
# CONFIG_SPI_AX88796C is not set
CONFIG_NET_VENDOR_ATHEROS=y
CONFIG_ATL2=m
CONFIG_ATL1=m
CONFIG_ATL1E=m
CONFIG_ATL1C=m
CONFIG_ALX=m
CONFIG_NET_VENDOR_BROADCOM=y
CONFIG_B44=m
CONFIG_B44_PCI_AUTOSELECT=y
CONFIG_B44_PCICORE_AUTOSELECT=y
CONFIG_B44_PCI=y
CONFIG_BCMGENET=m
CONFIG_BNX2=m
CONFIG_CNIC=m
CONFIG_TIGON3=m
CONFIG_TIGON3_HWMON=y
CONFIG_BNX2X=m
CONFIG_BNX2X_SRIOV=y
# CONFIG_SYSTEMPORT is not set
# CONFIG_BNXT is not set
CONFIG_NET_VENDOR_CADENCE=y
CONFIG_MACB=m
CONFIG_MACB_USE_HWSTAMP=y
# CONFIG_MACB_PCI is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
CONFIG_NET_VENDOR_CORTINA=y
# CONFIG_GEMINI_ETHERNET is not set
CONFIG_NET_VENDOR_DAVICOM=y
# CONFIG_DM9051 is not set
CONFIG_DNET=m
# CONFIG_NET_VENDOR_DEC is not set
CONFIG_NET_VENDOR_DLINK=y
CONFIG_DL2K=m
CONFIG_SUNDANCE=m
# CONFIG_SUNDANCE_MMIO is not set
# CONFIG_NET_VENDOR_EMULEX is not set
CONFIG_NET_VENDOR_ENGLEDER=y
# CONFIG_TSNEP is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
CONFIG_NET_VENDOR_FUNGIBLE=y
# CONFIG_FUN_ETH is not set
CONFIG_NET_VENDOR_GOOGLE=y
# CONFIG_GVE is not set
CONFIG_NET_VENDOR_HISILICON=y
CONFIG_HIX5HD2_GMAC=m
# CONFIG_HISI_FEMAC is not set
CONFIG_HIP04_ETH=m
# CONFIG_HI13X1_GMAC is not set
CONFIG_HNS_MDIO=m
CONFIG_HNS=m
CONFIG_HNS_DSAF=m
CONFIG_HNS_ENET=m
# CONFIG_HNS3 is not set
CONFIG_NET_VENDOR_HUAWEI=y
# CONFIG_HINIC is not set
# CONFIG_NET_VENDOR_I825XX is not set
CONFIG_NET_VENDOR_INTEL=y
CONFIG_E100=m
CONFIG_E1000=m
CONFIG_E1000E=m
CONFIG_IGB=m
CONFIG_IGB_HWMON=y
CONFIG_IGBVF=m
CONFIG_IXGBE=m
CONFIG_IXGBE_HWMON=y
CONFIG_IXGBE_DCB=y
CONFIG_IXGBEVF=m
CONFIG_I40E=m
# CONFIG_I40E_DCB is not set
CONFIG_IAVF=m
CONFIG_I40EVF=m
# CONFIG_ICE is not set
CONFIG_FM10K=m
# CONFIG_IGC is not set
CONFIG_JME=m
CONFIG_NET_VENDOR_ADI=y
# CONFIG_ADIN1110 is not set
CONFIG_NET_VENDOR_LITEX=y
# CONFIG_LITEX_LITEETH is not set
CONFIG_NET_VENDOR_MARVELL=y
CONFIG_MVMDIO=m
CONFIG_SKGE=m
# CONFIG_SKGE_DEBUG is not set
CONFIG_SKGE_GENESIS=y
CONFIG_SKY2=m
# CONFIG_SKY2_DEBUG is not set
# CONFIG_OCTEONTX2_AF is not set
# CONFIG_OCTEONTX2_PF is not set
# CONFIG_OCTEON_EP is not set
# CONFIG_PRESTERA is not set
CONFIG_NET_VENDOR_MELLANOX=y
CONFIG_MLX4_EN=m
CONFIG_MLX4_EN_DCB=y
CONFIG_MLX4_CORE=m
CONFIG_MLX4_DEBUG=y
CONFIG_MLX4_CORE_GEN2=y
CONFIG_MLX5_CORE=m
# CONFIG_MLX5_FPGA is not set
CONFIG_MLX5_CORE_EN=y
CONFIG_MLX5_EN_ARFS=y
CONFIG_MLX5_EN_RXNFC=y
CONFIG_MLX5_MPFS=y
# CONFIG_MLX5_ESWITCH is not set
# CONFIG_MLX5_CORE_EN_DCB is not set
# CONFIG_MLX5_CORE_IPOIB is not set
# CONFIG_MLX5_SF is not set
# CONFIG_MLXSW_CORE is not set
# CONFIG_MLXFW is not set
# CONFIG_MLXBF_GIGE is not set
CONFIG_NET_VENDOR_MICREL=y
# CONFIG_KS8842 is not set
# CONFIG_KS8851 is not set
# CONFIG_KS8851_MLL is not set
CONFIG_KSZ884X_PCI=m
CONFIG_NET_VENDOR_MICROCHIP=y
# CONFIG_ENC28J60 is not set
# CONFIG_ENCX24J600 is not set
# CONFIG_LAN743X is not set
# CONFIG_LAN966X_SWITCH is not set
# CONFIG_VCAP is not set
CONFIG_NET_VENDOR_MICROSEMI=y
# CONFIG_MSCC_OCELOT_SWITCH is not set
CONFIG_NET_VENDOR_MICROSOFT=y
CONFIG_NET_VENDOR_MYRI=y
CONFIG_MYRI10GE=m
CONFIG_FEALNX=m
CONFIG_NET_VENDOR_NI=y
# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
CONFIG_NET_VENDOR_NATSEMI=y
CONFIG_NATSEMI=m
CONFIG_NS83820=m
CONFIG_NET_VENDOR_NETERION=y
# CONFIG_S2IO is not set
CONFIG_NET_VENDOR_NETRONOME=y
# CONFIG_NFP is not set
CONFIG_NET_VENDOR_8390=y
CONFIG_NE2K_PCI=m
CONFIG_NET_VENDOR_NVIDIA=y
CONFIG_FORCEDETH=m
CONFIG_NET_VENDOR_OKI=y
CONFIG_ETHOC=m
CONFIG_NET_VENDOR_PACKET_ENGINES=y
CONFIG_HAMACHI=m
CONFIG_YELLOWFIN=m
CONFIG_NET_VENDOR_PENSANDO=y
# CONFIG_IONIC is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_BROCADE is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCA7000_UART is not set
# CONFIG_QCOM_EMAC is not set
CONFIG_RMNET=m
CONFIG_NET_VENDOR_RDC=y
CONFIG_R6040=m
CONFIG_NET_VENDOR_REALTEK=y
CONFIG_8139CP=m
CONFIG_8139TOO=m
# CONFIG_8139TOO_PIO is not set
# CONFIG_8139TOO_TUNE_TWISTER is not set
CONFIG_8139TOO_8129=y
# CONFIG_8139_OLD_RX_RESET is not set
CONFIG_R8169=m
# CONFIG_NET_VENDOR_RENESAS is not set
CONFIG_NET_VENDOR_ROCKER=y
CONFIG_ROCKER=m
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
CONFIG_NET_VENDOR_SILAN=y
CONFIG_SC92031=m
CONFIG_NET_VENDOR_SIS=y
CONFIG_SIS900=m
CONFIG_SIS190=m
CONFIG_NET_VENDOR_SOLARFLARE=y
# CONFIG_SFC is not set
# CONFIG_SFC_FALCON is not set
# CONFIG_SFC_SIENA is not set
CONFIG_NET_VENDOR_SMSC=y
CONFIG_SMC91X=m
CONFIG_EPIC100=m
CONFIG_SMSC911X=m
CONFIG_SMSC9420=m
CONFIG_NET_VENDOR_SOCIONEXT=y
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=m
# CONFIG_STMMAC_SELFTESTS is not set
CONFIG_STMMAC_PLATFORM=m
CONFIG_DWMAC_DWC_QOS_ETH=m
CONFIG_DWMAC_GENERIC=m
CONFIG_DWMAC_SUNXI=m
CONFIG_DWMAC_SUN8I=m
# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_DWMAC_LOONGSON is not set
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
CONFIG_NET_VENDOR_SYNOPSYS=y
# CONFIG_DWC_XLGMAC is not set
CONFIG_NET_VENDOR_TEHUTI=y
CONFIG_TEHUTI=m
CONFIG_NET_VENDOR_TI=y
# CONFIG_TI_CPSW_PHY_SEL is not set
# CONFIG_TLAN is not set
CONFIG_NET_VENDOR_VERTEXCOM=y
# CONFIG_MSE102X is not set
CONFIG_NET_VENDOR_VIA=y
CONFIG_VIA_RHINE=m
CONFIG_VIA_RHINE_MMIO=y
CONFIG_VIA_VELOCITY=m
# CONFIG_NET_VENDOR_WANGXUN is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_NET_VENDOR_XILINX=y
# CONFIG_XILINX_EMACLITE is not set
# CONFIG_XILINX_AXI_EMAC is not set
# CONFIG_XILINX_LL_TEMAC is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
CONFIG_NET_SB1000=y
CONFIG_PHYLINK=m
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_PHYLIB_LEDS=y
CONFIG_FIXED_PHY=y
CONFIG_SFP=m

#
# MII PHY device drivers
#
CONFIG_AC200_PHY=y
CONFIG_AMD_PHY=m
# CONFIG_ADIN_PHY is not set
# CONFIG_ADIN1100_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
CONFIG_AX88796B_PHY=m
CONFIG_BROADCOM_PHY=m
# CONFIG_BCM54140_PHY is not set
CONFIG_BCM7XXX_PHY=m
# CONFIG_BCM84881_PHY is not set
CONFIG_BCM87XX_PHY=m
CONFIG_BCM_NET_PHYLIB=m
CONFIG_BCM_NET_PHYPTP=m
CONFIG_CICADA_PHY=m
# CONFIG_CORTINA_PHY is not set
CONFIG_DAVICOM_PHY=m
CONFIG_ICPLUS_PHY=m
CONFIG_LXT_PHY=m
# CONFIG_INTEL_XWAY_PHY is not set
CONFIG_LSI_ET1011C_PHY=m
CONFIG_MARVELL_PHY=m
CONFIG_MARVELL_10G_PHY=m
# CONFIG_MARVELL_88X2222_PHY is not set
# CONFIG_MAXLINEAR_GPHY is not set
# CONFIG_MEDIATEK_GE_PHY is not set
CONFIG_MICREL_PHY=m
# CONFIG_MICROCHIP_T1S_PHY is not set
CONFIG_MICROCHIP_PHY=m
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
# CONFIG_MOTORCOMM_PHY is not set
CONFIG_NATIONAL_PHY=m
# CONFIG_NXP_CBTX_PHY is not set
# CONFIG_NXP_C45_TJA11XX_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
# CONFIG_NCN26000_PHY is not set
CONFIG_AT803X_PHY=y
CONFIG_QSEMI_PHY=m
CONFIG_REALTEK_PHY=m
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
CONFIG_SMSC_PHY=m
CONFIG_STE10XP=m
# CONFIG_TERANETICS_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
CONFIG_DP83848_PHY=m
CONFIG_DP83867_PHY=m
# CONFIG_DP83869_PHY is not set
# CONFIG_DP83TD510_PHY is not set
CONFIG_VITESSE_PHY=m
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_PSE_CONTROLLER is not set
CONFIG_CAN_DEV=m
CONFIG_CAN_VCAN=m
CONFIG_CAN_VXCAN=m
# CONFIG_CAN_NETLINK is not set
# CONFIG_CAN_DEBUG_DEVICES is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_FWNODE_MDIO=y
CONFIG_OF_MDIO=y
CONFIG_ACPI_MDIO=y
CONFIG_MDIO_DEVRES=y
# CONFIG_MDIO_SUN4I is not set
CONFIG_MDIO_BITBANG=m
CONFIG_MDIO_BCM_UNIMAC=y
# CONFIG_MDIO_GPIO is not set
# CONFIG_MDIO_HISI_FEMAC is not set
CONFIG_MDIO_I2C=m
# CONFIG_MDIO_MVUSB is not set
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_OCTEON is not set
# CONFIG_MDIO_IPQ4019 is not set
# CONFIG_MDIO_IPQ8064 is not set
CONFIG_MDIO_REGMAP=m
# CONFIG_MDIO_THUNDER is not set

#
# MDIO Multiplexers
#
CONFIG_MDIO_BUS_MUX=m
CONFIG_MDIO_BUS_MUX_GPIO=m
# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
CONFIG_MDIO_BUS_MUX_MMIOREG=m

#
# PCS device drivers
#
CONFIG_PCS_XPCS=m
CONFIG_PCS_LYNX=m
# end of PCS device drivers

CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOATM=m
CONFIG_PPPOE=m
# CONFIG_PPPOE_HASH_BITS_1 is not set
# CONFIG_PPPOE_HASH_BITS_2 is not set
CONFIG_PPPOE_HASH_BITS_4=y
# CONFIG_PPPOE_HASH_BITS_8 is not set
CONFIG_PPPOE_HASH_BITS=4
CONFIG_PPTP=m
CONFIG_PPPOL2TP=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_SLIP=m
CONFIG_SLHC=m
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_SMART=y
# CONFIG_SLIP_MODE_SLIP6 is not set
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_AX8817X=m
CONFIG_USB_NET_AX88179_178A=m
CONFIG_USB_NET_CDCETHER=m
CONFIG_USB_NET_CDC_EEM=m
CONFIG_USB_NET_CDC_NCM=m
CONFIG_USB_NET_HUAWEI_CDC_NCM=m
CONFIG_USB_NET_CDC_MBIM=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9700=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
CONFIG_USB_NET_CDC_SUBSET=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
CONFIG_USB_EPSON2888=y
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=m
CONFIG_USB_NET_CX82310_ETH=m
CONFIG_USB_NET_KALMIA=m
CONFIG_USB_NET_QMI_WWAN=m
CONFIG_USB_HSO=m
CONFIG_USB_NET_INT51X1=m
CONFIG_USB_IPHETH=m
CONFIG_USB_SIERRA_NET=m
CONFIG_USB_VL600=m
CONFIG_USB_NET_CH9200=m
# CONFIG_USB_NET_AQC111 is not set
CONFIG_USB_RTL8153_ECM=m
CONFIG_WLAN=y
CONFIG_WLAN_VENDOR_ADMTEK=y
CONFIG_ADM8211=m
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
# CONFIG_ATH_DEBUG is not set
CONFIG_ATH5K=m
CONFIG_ATH5K_DEBUG=y
CONFIG_ATH5K_PCI=y
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_COMMON_DEBUG=y
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=m
CONFIG_ATH9K_PCI=y
CONFIG_ATH9K_AHB=y
CONFIG_ATH9K_DEBUGFS=y
# CONFIG_ATH9K_STATION_STATISTICS is not set
# CONFIG_ATH9K_DYNACK is not set
# CONFIG_ATH9K_WOW is not set
CONFIG_ATH9K_RFKILL=y
# CONFIG_ATH9K_CHANNEL_CONTEXT is not set
CONFIG_ATH9K_PCOEM=y
# CONFIG_ATH9K_PCI_NO_EEPROM is not set
CONFIG_ATH9K_HTC=m
# CONFIG_ATH9K_HTC_DEBUGFS is not set
CONFIG_ATH9K_HWRNG=y
CONFIG_ATH9K_COMMON_SPECTRAL=y
CONFIG_CARL9170=m
CONFIG_CARL9170_LEDS=y
# CONFIG_CARL9170_DEBUGFS is not set
CONFIG_CARL9170_WPC=y
# CONFIG_CARL9170_HWRNG is not set
CONFIG_ATH6KL=m
CONFIG_ATH6KL_SDIO=m
CONFIG_ATH6KL_USB=m
CONFIG_ATH6KL_DEBUG=y
CONFIG_AR5523=m
CONFIG_WIL6210=m
CONFIG_WIL6210_ISR_COR=y
CONFIG_WIL6210_DEBUGFS=y
CONFIG_ATH10K=m
CONFIG_ATH10K_CE=y
CONFIG_ATH10K_PCI=m
# CONFIG_ATH10K_AHB is not set
# CONFIG_ATH10K_SDIO is not set
# CONFIG_ATH10K_USB is not set
# CONFIG_ATH10K_DEBUG is not set
CONFIG_ATH10K_DEBUGFS=y
# CONFIG_ATH10K_SPECTRAL is not set
CONFIG_WCN36XX=m
# CONFIG_WCN36XX_DEBUGFS is not set
# CONFIG_ATH11K is not set
# CONFIG_ATH12K is not set
CONFIG_WLAN_VENDOR_ATMEL=y
CONFIG_ATMEL=m
CONFIG_PCI_ATMEL=m
CONFIG_AT76C50X_USB=m
CONFIG_WLAN_VENDOR_BROADCOM=y
CONFIG_B43=m
CONFIG_B43_BCMA=y
CONFIG_B43_SSB=y
CONFIG_B43_BUSES_BCMA_AND_SSB=y
# CONFIG_B43_BUSES_BCMA is not set
# CONFIG_B43_BUSES_SSB is not set
CONFIG_B43_PCI_AUTOSELECT=y
CONFIG_B43_PCICORE_AUTOSELECT=y
CONFIG_B43_SDIO=y
CONFIG_B43_BCMA_PIO=y
CONFIG_B43_PIO=y
CONFIG_B43_PHY_G=y
CONFIG_B43_PHY_N=y
CONFIG_B43_PHY_LP=y
CONFIG_B43_PHY_HT=y
CONFIG_B43_LEDS=y
CONFIG_B43_HWRNG=y
CONFIG_B43_DEBUG=y
CONFIG_B43LEGACY=m
CONFIG_B43LEGACY_PCI_AUTOSELECT=y
CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
CONFIG_B43LEGACY_LEDS=y
CONFIG_B43LEGACY_HWRNG=y
CONFIG_B43LEGACY_DEBUG=y
CONFIG_B43LEGACY_DMA=y
CONFIG_B43LEGACY_PIO=y
CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
# CONFIG_B43LEGACY_DMA_MODE is not set
# CONFIG_B43LEGACY_PIO_MODE is not set
CONFIG_BRCMUTIL=m
CONFIG_BRCMSMAC=m
CONFIG_BRCMSMAC_LEDS=y
CONFIG_BRCMFMAC=m
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_PROTO_MSGBUF=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
CONFIG_BRCMFMAC_PCIE=y
# CONFIG_BRCM_TRACING is not set
# CONFIG_BRCMDBG is not set
CONFIG_WLAN_VENDOR_CISCO=y
# CONFIG_AIRO is not set
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_IPW2100=m
CONFIG_IPW2100_MONITOR=y
# CONFIG_IPW2100_DEBUG is not set
CONFIG_IPW2200=m
CONFIG_IPW2200_MONITOR=y
CONFIG_IPW2200_RADIOTAP=y
CONFIG_IPW2200_PROMISCUOUS=y
CONFIG_IPW2200_QOS=y
# CONFIG_IPW2200_DEBUG is not set
CONFIG_LIBIPW=m
# CONFIG_LIBIPW_DEBUG is not set
CONFIG_IWLEGACY=m
CONFIG_IWL4965=m
CONFIG_IWL3945=m

#
# iwl3945 / iwl4965 Debugging Options
#
CONFIG_IWLEGACY_DEBUG=y
CONFIG_IWLEGACY_DEBUGFS=y
# end of iwl3945 / iwl4965 Debugging Options

CONFIG_IWLWIFI=m
CONFIG_IWLWIFI_LEDS=y
CONFIG_IWLDVM=m
CONFIG_IWLMVM=m
CONFIG_IWLWIFI_OPMODE_MODULAR=y

#
# Debugging Options
#
CONFIG_IWLWIFI_DEBUG=y
CONFIG_IWLWIFI_DEBUGFS=y
# end of Debugging Options

CONFIG_WLAN_VENDOR_INTERSIL=y
CONFIG_HOSTAP=m
CONFIG_HOSTAP_FIRMWARE=y
# CONFIG_HOSTAP_FIRMWARE_NVRAM is not set
CONFIG_HOSTAP_PLX=m
CONFIG_HOSTAP_PCI=m
CONFIG_HERMES=m
CONFIG_HERMES_PRISM=y
CONFIG_HERMES_CACHE_FW_ON_INIT=y
CONFIG_PLX_HERMES=m
CONFIG_TMD_HERMES=m
CONFIG_NORTEL_HERMES=m
CONFIG_PCI_HERMES=m
CONFIG_ORINOCO_USB=m
CONFIG_P54_COMMON=m
CONFIG_P54_USB=m
CONFIG_P54_PCI=m
# CONFIG_P54_SPI is not set
CONFIG_P54_LEDS=y
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_USB=m
CONFIG_LIBERTAS_SDIO=m
# CONFIG_LIBERTAS_SPI is not set
# CONFIG_LIBERTAS_DEBUG is not set
CONFIG_LIBERTAS_MESH=y
CONFIG_LIBERTAS_THINFIRM=m
# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
CONFIG_LIBERTAS_THINFIRM_USB=m
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_SDIO=m
CONFIG_MWIFIEX_PCIE=m
CONFIG_MWIFIEX_USB=m
CONFIG_MWL8K=m
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=m
CONFIG_MT76_CORE=m
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=m
CONFIG_MT76x02_LIB=m
CONFIG_MT76x02_USB=m
CONFIG_MT76_CONNAC_LIB=m
CONFIG_MT76x0_COMMON=m
CONFIG_MT76x0U=m
CONFIG_MT76x0E=m
CONFIG_MT76x2_COMMON=m
CONFIG_MT76x2E=m
CONFIG_MT76x2U=m
CONFIG_MT7603E=m
CONFIG_MT7615_COMMON=m
CONFIG_MT7615E=m
# CONFIG_MT7663U is not set
# CONFIG_MT7663S is not set
# CONFIG_MT7915E is not set
# CONFIG_MT7921E is not set
# CONFIG_MT7921S is not set
# CONFIG_MT7921U is not set
# CONFIG_MT7996E is not set
CONFIG_WLAN_VENDOR_MICROCHIP=y
# CONFIG_WILC1000_SDIO is not set
# CONFIG_WILC1000_SPI is not set
# CONFIG_WLAN_VENDOR_PURELIFI is not set
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=m
CONFIG_RT2400PCI=m
CONFIG_RT2500PCI=m
CONFIG_RT61PCI=m
CONFIG_RT2800PCI=m
CONFIG_RT2800PCI_RT33XX=y
CONFIG_RT2800PCI_RT35XX=y
CONFIG_RT2800PCI_RT53XX=y
CONFIG_RT2800PCI_RT3290=y
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
CONFIG_RT2800USB_RT33XX=y
CONFIG_RT2800USB_RT35XX=y
CONFIG_RT2800USB_RT3573=y
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
CONFIG_RT2800USB_UNKNOWN=y
CONFIG_RT2800_LIB=m
CONFIG_RT2800_LIB_MMIO=m
CONFIG_RT2X00_LIB_MMIO=m
CONFIG_RT2X00_LIB_PCI=m
CONFIG_RT2X00_LIB_USB=m
CONFIG_RT2X00_LIB=m
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
CONFIG_RT2X00_LIB_DEBUGFS=y
# CONFIG_RT2X00_DEBUG is not set
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_RTL8180=m
CONFIG_RTL8187=m
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=m
CONFIG_RTL8192CE=m
CONFIG_RTL8192SE=m
CONFIG_RTL8192DE=m
CONFIG_RTL8723AE=m
CONFIG_RTL8723BE=m
CONFIG_RTL8188EE=m
CONFIG_RTL8192EE=m
CONFIG_RTL8821AE=m
CONFIG_RTL8192CU=m
CONFIG_RTLWIFI=m
CONFIG_RTLWIFI_PCI=m
CONFIG_RTLWIFI_USB=m
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8723_COMMON=m
CONFIG_RTLBTCOEXIST=m
CONFIG_RTL8XXXU=m
# CONFIG_RTL8XXXU_UNTESTED is not set
# CONFIG_RTW88 is not set
# CONFIG_RTW89 is not set
CONFIG_WLAN_VENDOR_RSI=y
CONFIG_RSI_91X=m
CONFIG_RSI_DEBUGFS=y
CONFIG_RSI_SDIO=m
CONFIG_RSI_USB=m
CONFIG_RSI_COEX=y
# CONFIG_WLAN_VENDOR_SILABS is not set
CONFIG_WLAN_VENDOR_ST=y
CONFIG_CW1200=m
CONFIG_CW1200_WLAN_SDIO=m
# CONFIG_CW1200_WLAN_SPI is not set
CONFIG_WLAN_VENDOR_TI=y
CONFIG_WL1251=m
CONFIG_WL1251_SPI=m
CONFIG_WL1251_SDIO=m
CONFIG_WL12XX=m
CONFIG_WL18XX=m
CONFIG_WLCORE=m
CONFIG_WLCORE_SPI=m
CONFIG_WLCORE_SDIO=m
CONFIG_WLAN_VENDOR_ZYDAS=y
CONFIG_USB_ZD1201=m
CONFIG_ZD1211RW=m
# CONFIG_ZD1211RW_DEBUG is not set
CONFIG_WLAN_VENDOR_QUANTENNA=y
CONFIG_QTNFMAC=m
CONFIG_QTNFMAC_PCIE=m
CONFIG_USB_NET_RNDIS_WLAN=m
CONFIG_MAC80211_HWSIM=m
# CONFIG_VIRT_WIFI is not set
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
# CONFIG_IEEE802154_AT86RF230 is not set
# CONFIG_IEEE802154_MRF24J40 is not set
# CONFIG_IEEE802154_CC2520 is not set
CONFIG_IEEE802154_ATUSB=m
# CONFIG_IEEE802154_ADF7242 is not set
# CONFIG_IEEE802154_CA8210 is not set
# CONFIG_IEEE802154_MCR20A is not set
# CONFIG_IEEE802154_HWSIM is not set

#
# Wireless WAN
#
# CONFIG_WWAN is not set
# end of Wireless WAN

# CONFIG_VMXNET3 is not set
# CONFIG_FUJITSU_ES is not set
# CONFIG_NETDEVSIM is not set
CONFIG_NET_FAILOVER=m
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=m
CONFIG_INPUT_SPARSEKMAP=m
CONFIG_INPUT_MATRIXKMAP=y
CONFIG_INPUT_VIVALDIFMAP=y

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=m
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ADC=m
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=m
CONFIG_KEYBOARD_GPIO_POLLED=m
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_PINEPHONE is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_SUN4I_LRADC is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
CONFIG_KEYBOARD_CROS_EC=y
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_KEYBOARD_CYPRESS_SF is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
CONFIG_MOUSE_PS2_SENTELIC=y
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_SMBUS=y
CONFIG_MOUSE_SERIAL=m
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=m
CONFIG_MOUSE_ELAN_I2C=y
CONFIG_MOUSE_ELAN_I2C_I2C=y
CONFIG_MOUSE_ELAN_I2C_SMBUS=y
CONFIG_MOUSE_VSXXXAA=m
# CONFIG_MOUSE_GPIO is not set
CONFIG_MOUSE_SYNAPTICS_I2C=m
CONFIG_MOUSE_SYNAPTICS_USB=m
CONFIG_INPUT_JOYSTICK=y
# CONFIG_JOYSTICK_ANALOG is not set
# CONFIG_JOYSTICK_A3D is not set
# CONFIG_JOYSTICK_ADC is not set
# CONFIG_JOYSTICK_ADI is not set
# CONFIG_JOYSTICK_COBRA is not set
# CONFIG_JOYSTICK_GF2K is not set
# CONFIG_JOYSTICK_GRIP is not set
# CONFIG_JOYSTICK_GRIP_MP is not set
# CONFIG_JOYSTICK_GUILLEMOT is not set
# CONFIG_JOYSTICK_INTERACT is not set
# CONFIG_JOYSTICK_SIDEWINDER is not set
# CONFIG_JOYSTICK_TMDC is not set
CONFIG_JOYSTICK_IFORCE=m
CONFIG_JOYSTICK_IFORCE_USB=m
CONFIG_JOYSTICK_IFORCE_232=m
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
CONFIG_JOYSTICK_STINGER=m
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
# CONFIG_JOYSTICK_AS5011 is not set
# CONFIG_JOYSTICK_JOYDUMP is not set
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
# CONFIG_JOYSTICK_PSXPAD_SPI is not set
# CONFIG_JOYSTICK_PXRC is not set
# CONFIG_JOYSTICK_QWIIC is not set
# CONFIG_JOYSTICK_FSIA6B is not set
# CONFIG_JOYSTICK_SENSEHAT is not set
CONFIG_INPUT_TABLET=y
CONFIG_TABLET_USB_ACECAD=m
CONFIG_TABLET_USB_AIPTEK=m
CONFIG_TABLET_USB_HANWANG=m
CONFIG_TABLET_USB_KBTAB=m
CONFIG_TABLET_USB_PEGASUS=m
CONFIG_TABLET_SERIAL_WACOM4=m
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_AD7877 is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ADC is not set
# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_BU21029 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 is not set
# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP5 is not set
CONFIG_TOUCHSCREEN_DYNAPRO=m
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
CONFIG_TOUCHSCREEN_EETI=m
CONFIG_TOUCHSCREEN_EGALAX=m
# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
# CONFIG_TOUCHSCREEN_EXC3000 is not set
CONFIG_TOUCHSCREEN_FUJITSU=m
# CONFIG_TOUCHSCREEN_GOODIX is not set
# CONFIG_TOUCHSCREEN_HIDEEP is not set
# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set
# CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set
CONFIG_TOUCHSCREEN_ILI210X=m
# CONFIG_TOUCHSCREEN_ILITEK is not set
# CONFIG_TOUCHSCREEN_S6SY761 is not set
CONFIG_TOUCHSCREEN_GUNZE=m
# CONFIG_TOUCHSCREEN_EKTF2127 is not set
CONFIG_TOUCHSCREEN_ELAN=m
CONFIG_TOUCHSCREEN_ELO=m
CONFIG_TOUCHSCREEN_WACOM_W8001=m
CONFIG_TOUCHSCREEN_WACOM_I2C=m
# CONFIG_TOUCHSCREEN_MAX11801 is not set
CONFIG_TOUCHSCREEN_MCS5000=m
CONFIG_TOUCHSCREEN_MMS114=m
# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
# CONFIG_TOUCHSCREEN_MSG2638 is not set
CONFIG_TOUCHSCREEN_MTOUCH=m
# CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS is not set
# CONFIG_TOUCHSCREEN_IMAGIS is not set
# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
CONFIG_TOUCHSCREEN_INEXIO=m
CONFIG_TOUCHSCREEN_PENMOUNT=m
CONFIG_TOUCHSCREEN_EDT_FT5X06=m
CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
CONFIG_TOUCHSCREEN_TOUCHWIN=m
CONFIG_TOUCHSCREEN_PIXCIR=m
# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
# CONFIG_TOUCHSCREEN_WM97XX is not set
CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
CONFIG_TOUCHSCREEN_TOUCHIT213=m
CONFIG_TOUCHSCREEN_TSC_SERIO=m
# CONFIG_TOUCHSCREEN_TSC2004 is not set
# CONFIG_TOUCHSCREEN_TSC2005 is not set
CONFIG_TOUCHSCREEN_TSC2007=m
# CONFIG_TOUCHSCREEN_TSC2007_IIO is not set
# CONFIG_TOUCHSCREEN_RM_TS is not set
# CONFIG_TOUCHSCREEN_SILEAD is not set
# CONFIG_TOUCHSCREEN_SIS_I2C is not set
CONFIG_TOUCHSCREEN_ST1232=m
# CONFIG_TOUCHSCREEN_STMFTS is not set
# CONFIG_TOUCHSCREEN_SUN4I is not set
# CONFIG_TOUCHSCREEN_SUR40 is not set
# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
# CONFIG_TOUCHSCREEN_SX8654 is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_TOUCHSCREEN_ZET6223 is not set
CONFIG_TOUCHSCREEN_ZFORCE=m
# CONFIG_TOUCHSCREEN_COLIBRI_VF50 is not set
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
# CONFIG_TOUCHSCREEN_IQS5XX is not set
# CONFIG_TOUCHSCREEN_ZINITIX is not set
# CONFIG_TOUCHSCREEN_HIMAX_HX83112B is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
# CONFIG_INPUT_BMA150 is not set
CONFIG_INPUT_E3X0_BUTTON=m
CONFIG_INPUT_MMA8450=m
# CONFIG_INPUT_GPIO_BEEPER is not set
# CONFIG_INPUT_GPIO_DECODER is not set
# CONFIG_INPUT_GPIO_VIBRA is not set
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
CONFIG_INPUT_KXTJ9=m
CONFIG_INPUT_POWERMATE=m
CONFIG_INPUT_YEALINK=m
CONFIG_INPUT_CM109=m
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
CONFIG_INPUT_AXP20X_PEK=m
CONFIG_INPUT_UINPUT=m
# CONFIG_INPUT_PCF8574 is not set
CONFIG_INPUT_PWM_BEEPER=m
# CONFIG_INPUT_PWM_VIBRA is not set
CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
# CONFIG_INPUT_DA7280_HAPTICS is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_IBM_PANEL is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_INPUT_IQS269A is not set
# CONFIG_INPUT_IQS626A is not set
# CONFIG_INPUT_IQS7222 is not set
CONFIG_INPUT_CMA3000=m
CONFIG_INPUT_CMA3000_I2C=m
# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
# CONFIG_INPUT_DRV260X_HAPTICS is not set
# CONFIG_INPUT_DRV2665_HAPTICS is not set
# CONFIG_INPUT_DRV2667_HAPTICS is not set
CONFIG_RMI4_CORE=m
# CONFIG_RMI4_I2C is not set
# CONFIG_RMI4_SPI is not set
# CONFIG_RMI4_SMB is not set
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=m
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
# CONFIG_RMI4_F34 is not set
# CONFIG_RMI4_F3A is not set
# CONFIG_RMI4_F54 is not set
# CONFIG_RMI4_F55 is not set

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO_AMBAKMI=y
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIO_RAW=m
CONFIG_SERIO_ALTERA_PS2=m
# CONFIG_SERIO_PS2MULT is not set
CONFIG_SERIO_ARC_PS2=m
# CONFIG_SERIO_APBPS2 is not set
# CONFIG_SERIO_SUN4I_PS2 is not set
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
# CONFIG_GAMEPORT is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_LEGACY_TIOCSTI is not set
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
CONFIG_SERIAL_8250_PCILIB=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_EXAR=y
CONFIG_SERIAL_8250_NR_UARTS=32
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
# CONFIG_SERIAL_8250_PCI1XXXX is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_8250_PERICOM=y
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
# CONFIG_SERIAL_AMBA_PL010 is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set
# CONFIG_SERIAL_KGDB_NMI is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_CONSOLE_POLL=y
CONFIG_SERIAL_JSM=m
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
CONFIG_SERIAL_ARC=m
CONFIG_SERIAL_ARC_NR_PORTS=1
# CONFIG_SERIAL_RP2 is not set
CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_SERIAL_FSL_LINFLEXUART=y
CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_NONSTANDARD=y
# CONFIG_MOXA_INTELLIO is not set
# CONFIG_MOXA_SMARTIO is not set
CONFIG_SYNCLINK_GT=m
CONFIG_N_HDLC=m
CONFIG_N_GSM=m
CONFIG_NOZOMI=m
# CONFIG_NULL_TTY is not set
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
# CONFIG_RPMSG_TTY is not set
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_TTY_PRINTK is not set
CONFIG_VIRTIO_CONSOLE=y
CONFIG_IPMI_HANDLER=y
CONFIG_IPMI_DMI_DECODE=y
CONFIG_IPMI_PLAT_DATA=y
# CONFIG_IPMI_PANIC_EVENT is not set
CONFIG_IPMI_DEVICE_INTERFACE=m
CONFIG_IPMI_SI=m
CONFIG_IPMI_SSIF=m
# CONFIG_IPMI_IPMB is not set
CONFIG_IPMI_WATCHDOG=m
CONFIG_IPMI_POWEROFF=m
# CONFIG_SSIF_IPMI_BMC is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=m
# CONFIG_HW_RANDOM_BA431 is not set
CONFIG_HW_RANDOM_VIRTIO=m
# CONFIG_HW_RANDOM_CCTRNG is not set
# CONFIG_HW_RANDOM_XIPHERA is not set
CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
CONFIG_HW_RANDOM_CN10K=y
# CONFIG_APPLICOM is not set
CONFIG_DEVMEM=y
CONFIG_DEVPORT=y
CONFIG_TCG_TPM=y
CONFIG_HW_RANDOM_TPM=y
# CONFIG_TCG_TIS is not set
# CONFIG_TCG_TIS_SPI is not set
# CONFIG_TCG_TIS_I2C is not set
# CONFIG_TCG_TIS_I2C_CR50 is not set
# CONFIG_TCG_TIS_I2C_ATMEL is not set
CONFIG_TCG_TIS_I2C_INFINEON=y
# CONFIG_TCG_TIS_I2C_NUVOTON is not set
CONFIG_TCG_ATMEL=m
# CONFIG_TCG_INFINEON is not set
# CONFIG_TCG_CRB is not set
# CONFIG_TCG_VTPM_PROXY is not set
# CONFIG_TCG_TIS_ST33ZP24_I2C is not set
# CONFIG_TCG_TIS_ST33ZP24_SPI is not set
# CONFIG_XILLYBUS is not set
# CONFIG_XILLYUSB is not set
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=m
CONFIG_I2C_MUX_GPIO=m
CONFIG_I2C_MUX_GPMUX=m
# CONFIG_I2C_MUX_LTC4306 is not set
CONFIG_I2C_MUX_PCA9541=m
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_MUX_PINCTRL=m
CONFIG_I2C_MUX_REG=m
CONFIG_I2C_DEMUX_PINCTRL=m
# CONFIG_I2C_MUX_MLXCPLD is not set
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_SMBUS=m
CONFIG_I2C_ALGOBIT=m
CONFIG_I2C_ALGOPCA=m

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
CONFIG_I2C_CCGX_UCSI=m
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
CONFIG_I2C_NFORCE2=m
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set

#
# ACPI drivers
#
CONFIG_I2C_SCMI=y

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CADENCE is not set
# CONFIG_I2C_CBUS_GPIO is not set
CONFIG_I2C_DESIGNWARE_CORE=y
# CONFIG_I2C_DESIGNWARE_SLAVE is not set
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_DESIGNWARE_PCI=m
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=m
# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
# CONFIG_I2C_HISI is not set
CONFIG_I2C_MV64XXX=y
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_PCA_PLATFORM=m
CONFIG_I2C_RK3X=y
CONFIG_I2C_SIMTEC=m
CONFIG_I2C_VERSATILE=m
# CONFIG_I2C_THUNDERX is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
CONFIG_I2C_DIOLAN_U2C=m
# CONFIG_I2C_CP2615 is not set
# CONFIG_I2C_PCI1XXXX is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
CONFIG_I2C_TINY_USB=m
CONFIG_I2C_VIPERBOARD=m

#
# Other I2C/SMBus bus drivers
#
CONFIG_I2C_CROS_EC_TUNNEL=y
# CONFIG_I2C_VIRTIO is not set
# end of I2C Hardware Bus support

CONFIG_I2C_STUB=m
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=m
# CONFIG_I2C_SLAVE_TESTUNIT is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

# CONFIG_I3C is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y

#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
CONFIG_SPI_BITBANG=y
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_CADENCE_XSPI is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_HISI_KUNPENG is not set
# CONFIG_SPI_HISI_SFC_V3XX is not set
CONFIG_SPI_GPIO=y
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_MICROCHIP_CORE is not set
# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PCI1XXXX is not set
CONFIG_SPI_PL022=y
# CONFIG_SPI_PXA2XX is not set
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_SN_F_OSPI is not set
# CONFIG_SPI_SUN4I is not set
CONFIG_SPI_SUN6I=y
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_THUNDERX is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_SPI_AMD is not set

#
# SPI Multiplexer support
#
# CONFIG_SPI_MUX is not set

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=m
# CONFIG_SPI_LOOPBACK_TEST is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_DYNAMIC=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set

#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
CONFIG_PPS_CLIENT_LDISC=m
CONFIG_PPS_CLIENT_GPIO=m

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_DP83640_PHY=m
# CONFIG_PTP_1588_CLOCK_INES is not set
CONFIG_PTP_1588_CLOCK_KVM=y
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
# CONFIG_PTP_1588_CLOCK_OCP is not set
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
CONFIG_PINCTRL_AMD=y
CONFIG_PINCTRL_AXP209=y
# CONFIG_PINCTRL_CY8C95X0 is not set
CONFIG_PINCTRL_MAX77620=y
# CONFIG_PINCTRL_MCP23S08 is not set
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
# CONFIG_PINCTRL_OCELOT is not set
CONFIG_PINCTRL_SINGLE=y
# CONFIG_PINCTRL_STMFX is not set
# CONFIG_PINCTRL_SX150X is not set

#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers

CONFIG_PINCTRL_SUNXI=y
# CONFIG_PINCTRL_SUN4I_A10 is not set
# CONFIG_PINCTRL_SUN5I is not set
# CONFIG_PINCTRL_SUN6I_A31 is not set
# CONFIG_PINCTRL_SUN6I_A31_R is not set
# CONFIG_PINCTRL_SUN8I_A23 is not set
# CONFIG_PINCTRL_SUN8I_A33 is not set
# CONFIG_PINCTRL_SUN8I_A83T is not set
# CONFIG_PINCTRL_SUN8I_A83T_R is not set
# CONFIG_PINCTRL_SUN8I_A23_R is not set
# CONFIG_PINCTRL_SUN8I_H3 is not set
CONFIG_PINCTRL_SUN8I_H3_R=y
# CONFIG_PINCTRL_SUN8I_V3S is not set
# CONFIG_PINCTRL_SUN9I_A80 is not set
# CONFIG_PINCTRL_SUN9I_A80_R is not set
# CONFIG_PINCTRL_SUN20I_D1 is not set
CONFIG_PINCTRL_SUN50I_A64=y
CONFIG_PINCTRL_SUN50I_A64_R=y
CONFIG_PINCTRL_SUN50I_A100=y
CONFIG_PINCTRL_SUN50I_A100_R=y
CONFIG_PINCTRL_SUN50I_H5=y
CONFIG_PINCTRL_SUN50I_H6=y
CONFIG_PINCTRL_SUN50I_H6_R=y
CONFIG_PINCTRL_SUN50I_H616=y
CONFIG_PINCTRL_SUN50I_H616_R=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_CADENCE is not set
CONFIG_GPIO_DWAPB=y
# CONFIG_GPIO_EXAR is not set
# CONFIG_GPIO_FTGPIO010 is not set
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HISI is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_LOGICVC is not set
# CONFIG_GPIO_MB86S7X is not set
CONFIG_GPIO_PL061=y
# CONFIG_GPIO_SIFIVE is not set
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_WCD934X=m
CONFIG_GPIO_XGENE=y
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
# CONFIG_GPIO_ADNP is not set
# CONFIG_GPIO_FXL6408 is not set
# CONFIG_GPIO_GW_PLD is not set
# CONFIG_GPIO_MAX7300 is not set
CONFIG_GPIO_MAX732X=y
# CONFIG_GPIO_MAX732X_IRQ is not set
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
# CONFIG_GPIO_PCA9570 is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_TPIC2810 is not set
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
CONFIG_GPIO_MAX77620=y
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set
# end of PCI GPIO expanders

#
# SPI GPIO expanders
#
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
CONFIG_GPIO_VIPERBOARD=m
# end of USB GPIO expanders

#
# Virtual GPIO drivers
#
# CONFIG_GPIO_AGGREGATOR is not set
# CONFIG_GPIO_LATCH is not set
# CONFIG_GPIO_MOCKUP is not set
# CONFIG_GPIO_VIRTIO is not set
# CONFIG_GPIO_SIM is not set
# end of Virtual GPIO drivers

CONFIG_W1=m
CONFIG_W1_CON=y

#
# 1-wire Bus Masters
#
# CONFIG_W1_MASTER_MATROX is not set
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
# CONFIG_W1_MASTER_GPIO is not set
# CONFIG_W1_MASTER_SGI is not set
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
# CONFIG_W1_SLAVE_DS2405 is not set
CONFIG_W1_SLAVE_DS2408=m
# CONFIG_W1_SLAVE_DS2408_READBACK is not set
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
# CONFIG_W1_SLAVE_DS2805 is not set
# CONFIG_W1_SLAVE_DS2430 is not set
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
# CONFIG_W1_SLAVE_DS2438 is not set
# CONFIG_W1_SLAVE_DS250X is not set
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
# CONFIG_W1_SLAVE_DS28E17 is not set
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_BRCMSTB is not set
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
# CONFIG_POWER_RESET_LTC2952 is not set
# CONFIG_POWER_RESET_REGULATOR is not set
CONFIG_POWER_RESET_RESTART=y
CONFIG_POWER_RESET_VEXPRESS=y
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
# CONFIG_NVMEM_REBOOT_MODE is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_IP5XXX_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SAMSUNG_SDI is not set
CONFIG_BATTERY_SBS=m
CONFIG_CHARGER_SBS=m
CONFIG_MANAGER_SBS=m
# CONFIG_BATTERY_BQ27XXX is not set
CONFIG_CHARGER_AXP20X=m
CONFIG_BATTERY_AXP20X=m
CONFIG_AXP20X_POWER=m
# CONFIG_BATTERY_MAX17040 is not set
CONFIG_BATTERY_MAX17042=m
# CONFIG_BATTERY_MAX1721X is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
# CONFIG_CHARGER_GPIO is not set
# CONFIG_CHARGER_MANAGER is not set
# CONFIG_CHARGER_LT3651 is not set
# CONFIG_CHARGER_LTC4162L is not set
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_MAX77976 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25890 is not set
CONFIG_CHARGER_BQ25980=m
# CONFIG_CHARGER_BQ256XX is not set
CONFIG_CHARGER_SMB347=m
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_BATTERY_GOLDFISH is not set
# CONFIG_BATTERY_RT5033 is not set
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_RT9467 is not set
# CONFIG_CHARGER_RT9471 is not set
CONFIG_CHARGER_CROS_USBPD=m
CONFIG_CHARGER_CROS_PCHG=y
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
# CONFIG_BATTERY_UG3105 is not set
CONFIG_HWMON=y
CONFIG_HWMON_VID=m
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
CONFIG_SENSORS_AD7414=m
CONFIG_SENSORS_AD7418=m
CONFIG_SENSORS_ADM1025=m
CONFIG_SENSORS_ADM1026=m
CONFIG_SENSORS_ADM1029=m
CONFIG_SENSORS_ADM1031=m
# CONFIG_SENSORS_ADM1177 is not set
CONFIG_SENSORS_ADM9240=m
CONFIG_SENSORS_ADT7X10=m
# CONFIG_SENSORS_ADT7310 is not set
CONFIG_SENSORS_ADT7410=m
CONFIG_SENSORS_ADT7411=m
CONFIG_SENSORS_ADT7462=m
CONFIG_SENSORS_ADT7470=m
CONFIG_SENSORS_ADT7475=m
# CONFIG_SENSORS_AHT10 is not set
# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
# CONFIG_SENSORS_AS370 is not set
CONFIG_SENSORS_ASC7621=m
# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
CONFIG_SENSORS_ARM_SCMI=y
CONFIG_SENSORS_ARM_SCPI=y
CONFIG_SENSORS_ATXP1=m
# CONFIG_SENSORS_CORSAIR_CPRO is not set
# CONFIG_SENSORS_CORSAIR_PSU is not set
CONFIG_SENSORS_DRIVETEMP=m
CONFIG_SENSORS_DS620=m
CONFIG_SENSORS_DS1621=m
# CONFIG_SENSORS_I5K_AMB is not set
CONFIG_SENSORS_F71805F=m
CONFIG_SENSORS_F71882FG=m
CONFIG_SENSORS_F75375S=m
# CONFIG_SENSORS_FTSTEUTATES is not set
CONFIG_SENSORS_GL518SM=m
CONFIG_SENSORS_GL520SM=m
CONFIG_SENSORS_G760A=m
CONFIG_SENSORS_G762=m
CONFIG_SENSORS_GPIO_FAN=m
# CONFIG_SENSORS_HIH6130 is not set
CONFIG_SENSORS_IBMAEM=m
CONFIG_SENSORS_IBMPEX=m
CONFIG_SENSORS_IIO_HWMON=m
CONFIG_SENSORS_IT87=m
# CONFIG_SENSORS_JC42 is not set
CONFIG_SENSORS_POWR1220=m
CONFIG_SENSORS_LINEAGE=m
CONFIG_SENSORS_LTC2945=m
# CONFIG_SENSORS_LTC2947_I2C is not set
# CONFIG_SENSORS_LTC2947_SPI is not set
# CONFIG_SENSORS_LTC2990 is not set
# CONFIG_SENSORS_LTC2992 is not set
CONFIG_SENSORS_LTC4151=m
CONFIG_SENSORS_LTC4215=m
CONFIG_SENSORS_LTC4222=m
CONFIG_SENSORS_LTC4245=m
CONFIG_SENSORS_LTC4260=m
CONFIG_SENSORS_LTC4261=m
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX127 is not set
CONFIG_SENSORS_MAX16065=m
CONFIG_SENSORS_MAX1619=m
CONFIG_SENSORS_MAX1668=m
CONFIG_SENSORS_MAX197=m
# CONFIG_SENSORS_MAX31722 is not set
# CONFIG_SENSORS_MAX31730 is not set
# CONFIG_SENSORS_MAX31760 is not set
# CONFIG_MAX31827 is not set
# CONFIG_SENSORS_MAX6620 is not set
# CONFIG_SENSORS_MAX6621 is not set
CONFIG_SENSORS_MAX6639=m
CONFIG_SENSORS_MAX6650=m
CONFIG_SENSORS_MAX6697=m
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MC34VR500 is not set
CONFIG_SENSORS_MCP3021=m
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_TPS23861 is not set
# CONFIG_SENSORS_MR75203 is not set
# CONFIG_SENSORS_ADCXX is not set
CONFIG_SENSORS_LM63=m
# CONFIG_SENSORS_LM70 is not set
CONFIG_SENSORS_LM73=m
CONFIG_SENSORS_LM75=m
CONFIG_SENSORS_LM77=m
CONFIG_SENSORS_LM78=m
CONFIG_SENSORS_LM80=m
CONFIG_SENSORS_LM83=m
CONFIG_SENSORS_LM85=m
CONFIG_SENSORS_LM87=m
CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_LM92=m
CONFIG_SENSORS_LM93=m
CONFIG_SENSORS_LM95234=m
CONFIG_SENSORS_LM95241=m
CONFIG_SENSORS_LM95245=m
CONFIG_SENSORS_PC87360=m
CONFIG_SENSORS_PC87427=m
CONFIG_SENSORS_NTC_THERMISTOR=m
CONFIG_SENSORS_NCT6683=m
CONFIG_SENSORS_NCT6775_CORE=m
CONFIG_SENSORS_NCT6775=m
# CONFIG_SENSORS_NCT6775_I2C is not set
CONFIG_SENSORS_NCT7802=m
CONFIG_SENSORS_NCT7904=m
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
# CONFIG_SENSORS_NZXT_SMART2 is not set
# CONFIG_SENSORS_OCC_P8_I2C is not set
CONFIG_SENSORS_PCF8591=m
CONFIG_PMBUS=m
CONFIG_SENSORS_PMBUS=m
# CONFIG_SENSORS_ACBEL_FSG032 is not set
# CONFIG_SENSORS_ADM1266 is not set
CONFIG_SENSORS_ADM1275=m
# CONFIG_SENSORS_BEL_PFE is not set
# CONFIG_SENSORS_BPA_RS600 is not set
# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set
# CONFIG_SENSORS_FSP_3Y is not set
# CONFIG_SENSORS_IBM_CFFPS is not set
# CONFIG_SENSORS_DPS920AB is not set
# CONFIG_SENSORS_INSPUR_IPSPS is not set
# CONFIG_SENSORS_IR35221 is not set
# CONFIG_SENSORS_IR36021 is not set
# CONFIG_SENSORS_IR38064 is not set
# CONFIG_SENSORS_IRPS5401 is not set
# CONFIG_SENSORS_ISL68137 is not set
CONFIG_SENSORS_LM25066=m
# CONFIG_SENSORS_LM25066_REGULATOR is not set
# CONFIG_SENSORS_LT7182S is not set
CONFIG_SENSORS_LTC2978=m
# CONFIG_SENSORS_LTC2978_REGULATOR is not set
# CONFIG_SENSORS_LTC3815 is not set
# CONFIG_SENSORS_MAX15301 is not set
CONFIG_SENSORS_MAX16064=m
# CONFIG_SENSORS_MAX16601 is not set
# CONFIG_SENSORS_MAX20730 is not set
# CONFIG_SENSORS_MAX20751 is not set
# CONFIG_SENSORS_MAX31785 is not set
CONFIG_SENSORS_MAX34440=m
CONFIG_SENSORS_MAX8688=m
# CONFIG_SENSORS_MP2888 is not set
# CONFIG_SENSORS_MP2975 is not set
# CONFIG_SENSORS_MP5023 is not set
# CONFIG_SENSORS_MPQ7932 is not set
# CONFIG_SENSORS_PIM4328 is not set
# CONFIG_SENSORS_PLI1209BC is not set
# CONFIG_SENSORS_PM6764TR is not set
# CONFIG_SENSORS_PXE1610 is not set
# CONFIG_SENSORS_Q54SJ108A2 is not set
# CONFIG_SENSORS_STPDDC60 is not set
# CONFIG_SENSORS_TDA38640 is not set
CONFIG_SENSORS_TPS40422=m
# CONFIG_SENSORS_TPS53679 is not set
# CONFIG_SENSORS_TPS546D24 is not set
CONFIG_SENSORS_UCD9000=m
CONFIG_SENSORS_UCD9200=m
# CONFIG_SENSORS_XDPE152 is not set
# CONFIG_SENSORS_XDPE122 is not set
CONFIG_SENSORS_ZL6100=m
CONFIG_SENSORS_PWM_FAN=m
# CONFIG_SENSORS_SBTSI is not set
# CONFIG_SENSORS_SBRMI is not set
CONFIG_SENSORS_SHT15=m
CONFIG_SENSORS_SHT21=m
CONFIG_SENSORS_SHT3x=m
# CONFIG_SENSORS_SHT4x is not set
CONFIG_SENSORS_SHTC1=m
CONFIG_SENSORS_SIS5595=m
CONFIG_SENSORS_DME1737=m
CONFIG_SENSORS_EMC1403=m
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC2305 is not set
CONFIG_SENSORS_EMC6W201=m
CONFIG_SENSORS_SMSC47M1=m
CONFIG_SENSORS_SMSC47M192=m
CONFIG_SENSORS_SMSC47B397=m
CONFIG_SENSORS_SCH56XX_COMMON=m
CONFIG_SENSORS_SCH5627=m
CONFIG_SENSORS_SCH5636=m
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
CONFIG_SENSORS_ADC128D818=m
CONFIG_SENSORS_ADS7828=m
# CONFIG_SENSORS_ADS7871 is not set
CONFIG_SENSORS_AMC6821=m
CONFIG_SENSORS_INA209=m
CONFIG_SENSORS_INA2XX=m
# CONFIG_SENSORS_INA238 is not set
CONFIG_SENSORS_INA3221=m
CONFIG_SENSORS_TC74=m
CONFIG_SENSORS_THMC50=m
CONFIG_SENSORS_TMP102=m
CONFIG_SENSORS_TMP103=m
CONFIG_SENSORS_TMP108=m
CONFIG_SENSORS_TMP401=m
CONFIG_SENSORS_TMP421=m
# CONFIG_SENSORS_TMP464 is not set
# CONFIG_SENSORS_TMP513 is not set
CONFIG_SENSORS_VEXPRESS=m
CONFIG_SENSORS_VIA686A=m
CONFIG_SENSORS_VT1211=m
CONFIG_SENSORS_VT8231=m
# CONFIG_SENSORS_W83773G is not set
CONFIG_SENSORS_W83781D=m
CONFIG_SENSORS_W83791D=m
CONFIG_SENSORS_W83792D=m
CONFIG_SENSORS_W83793=m
CONFIG_SENSORS_W83795=m
# CONFIG_SENSORS_W83795_FANCTRL is not set
CONFIG_SENSORS_W83L785TS=m
CONFIG_SENSORS_W83L786NG=m
CONFIG_SENSORS_W83627HF=m
CONFIG_SENSORS_W83627EHF=m
# CONFIG_SENSORS_XGENE is not set

#
# ACPI drivers
#
CONFIG_SENSORS_ACPI_POWER=m
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
# CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG is not set
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_BANG_BANG=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_THERMAL_EMULATION=y
# CONFIG_THERMAL_MMIO is not set
CONFIG_MAX77620_THERMAL=m
CONFIG_SUN8I_THERMAL=m
CONFIG_GENERIC_ADC_THERMAL=m
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set
CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=m
CONFIG_GPIO_WATCHDOG=m
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_XILINX_WINDOW_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
CONFIG_ARM_SP805_WATCHDOG=m
CONFIG_ARM_SBSA_WATCHDOG=m
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=m
CONFIG_SUNXI_WATCHDOG=m
# CONFIG_MAX63XX_WATCHDOG is not set
CONFIG_MAX77620_WATCHDOG=m
CONFIG_ARM_SMC_WATCHDOG=y
CONFIG_ALIM7101_WDT=m
CONFIG_I6300ESB_WDT=m
# CONFIG_HP_WATCHDOG is not set
# CONFIG_MEN_A21_WDT is not set

#
# PCI-based Watchdog Cards
#
CONFIG_PCIPCWATCHDOG=m
CONFIG_WDTPCI=m

#
# USB-based Watchdog Cards
#
CONFIG_USBPCWATCHDOG=m
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB=m
CONFIG_SSB_SPROM=y
CONFIG_SSB_BLOCKIO=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_PCIHOST=y
CONFIG_SSB_B43_PCI_BRIDGE=y
CONFIG_SSB_SDIOHOST_POSSIBLE=y
CONFIG_SSB_SDIOHOST=y
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
CONFIG_SSB_DRIVER_PCICORE=y
CONFIG_SSB_DRIVER_GPIO=y
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_BLOCKIO=y
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
CONFIG_BCMA_HOST_PCI=y
# CONFIG_BCMA_HOST_SOC is not set
CONFIG_BCMA_DRIVER_PCI=y
CONFIG_BCMA_DRIVER_GMAC_CMN=y
CONFIG_BCMA_DRIVER_GPIO=y
# CONFIG_BCMA_DEBUG is not set

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_SUN4I_GPADC is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_SMPRO is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AC100 is not set
CONFIG_MFD_AC200=y
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
CONFIG_MFD_CROS_EC_DEV=y
# CONFIG_MFD_MADERA is not set
# CONFIG_MFD_MAX5970 is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77541 is not set
CONFIG_MFD_MAX77620=y
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77714 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6370 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_MFD_OCELOT is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
CONFIG_MFD_VIPERBOARD=m
# CONFIG_MFD_NTXEC is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_SY7636A is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT4831 is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RT5120 is not set
# CONFIG_MFD_RC5T583 is not set
# CONFIG_MFD_RK8XX_I2C is not set
# CONFIG_MFD_RK8XX_SPI is not set
# CONFIG_MFD_RN5T618 is not set
CONFIG_MFD_SEC_CORE=y
# CONFIG_MFD_SI476X_CORE is not set
CONFIG_MFD_SM501=m
CONFIG_MFD_SM501_GPIO=y
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SUN6I_PRCM=y
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS65219 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS6594_I2C is not set
# CONFIG_MFD_TPS6594_SPI is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TQMX86 is not set
CONFIG_MFD_VX855=m
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
CONFIG_MFD_ROHM_BD718XX=y
# CONFIG_MFD_ROHM_BD71828 is not set
# CONFIG_MFD_ROHM_BD957XMUF is not set
# CONFIG_MFD_STPMIC1 is not set
# CONFIG_MFD_STMFX is not set
CONFIG_MFD_WCD934X=m
# CONFIG_MFD_ATC260X_I2C is not set
# CONFIG_MFD_QCOM_PM8008 is not set
CONFIG_MFD_VEXPRESS_SYSREG=y
# CONFIG_RAVE_SP_CORE is not set
# CONFIG_MFD_INTEL_M10_BMC_SPI is not set
# CONFIG_MFD_RSMU_I2C is not set
# CONFIG_MFD_RSMU_SPI is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_88PG86X is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_AD5398 is not set
# CONFIG_REGULATOR_ARM_SCMI is not set
CONFIG_REGULATOR_AXP20X=y
CONFIG_REGULATOR_BD718XX=y
# CONFIG_REGULATOR_CROS_EC is not set
# CONFIG_REGULATOR_DA9121 is not set
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
CONFIG_REGULATOR_FAN53555=y
# CONFIG_REGULATOR_FAN53880 is not set
CONFIG_REGULATOR_GPIO=y
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_LP8755 is not set
# CONFIG_REGULATOR_LTC3589 is not set
# CONFIG_REGULATOR_LTC3676 is not set
# CONFIG_REGULATOR_MAX1586 is not set
CONFIG_REGULATOR_MAX77620=y
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8893 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_MAX8973 is not set
# CONFIG_REGULATOR_MAX20086 is not set
# CONFIG_REGULATOR_MAX20411 is not set
# CONFIG_REGULATOR_MAX77826 is not set
# CONFIG_REGULATOR_MCP16502 is not set
# CONFIG_REGULATOR_MP5416 is not set
# CONFIG_REGULATOR_MP8859 is not set
# CONFIG_REGULATOR_MP886X is not set
# CONFIG_REGULATOR_MPQ7920 is not set
# CONFIG_REGULATOR_MT6311 is not set
# CONFIG_REGULATOR_MT6315 is not set
CONFIG_REGULATOR_PCA9450=y
# CONFIG_REGULATOR_PF8X00 is not set
CONFIG_REGULATOR_PFUZE100=y
# CONFIG_REGULATOR_PV88060 is not set
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_QCOM_SPMI=y
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
# CONFIG_REGULATOR_RAA215300 is not set
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
CONFIG_REGULATOR_ROHM=y
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RT4803 is not set
# CONFIG_REGULATOR_RT5190A is not set
# CONFIG_REGULATOR_RT5739 is not set
# CONFIG_REGULATOR_RT5759 is not set
# CONFIG_REGULATOR_RT6160 is not set
# CONFIG_REGULATOR_RT6190 is not set
# CONFIG_REGULATOR_RT6245 is not set
# CONFIG_REGULATOR_RTQ2134 is not set
# CONFIG_REGULATOR_RTMV20 is not set
# CONFIG_REGULATOR_RTQ6752 is not set
# CONFIG_REGULATOR_S2MPA01 is not set
CONFIG_REGULATOR_S2MPS11=y
# CONFIG_REGULATOR_S5M8767 is not set
# CONFIG_REGULATOR_SLG51000 is not set
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
# CONFIG_REGULATOR_SY8827N is not set
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS6286X is not set
# CONFIG_REGULATOR_TPS6287X is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
CONFIG_REGULATOR_TPS65132=m
# CONFIG_REGULATOR_TPS6524X is not set
CONFIG_REGULATOR_VCTRL=y
CONFIG_REGULATOR_VEXPRESS=y
# CONFIG_REGULATOR_QCOM_LABIBB is not set
CONFIG_RC_CORE=m
CONFIG_LIRC=y
CONFIG_RC_MAP=m
CONFIG_RC_DECODERS=y
CONFIG_IR_IMON_DECODER=m
CONFIG_IR_JVC_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
CONFIG_IR_RCMM_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_XMP_DECODER=m
CONFIG_RC_DEVICES=y
CONFIG_IR_ENE=m
CONFIG_IR_FINTEK=m
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_GPIO_TX=m
CONFIG_IR_HIX5HD2=m
CONFIG_IR_IGORPLUGUSB=m
CONFIG_IR_IGUANA=m
CONFIG_IR_IMON=m
CONFIG_IR_IMON_RAW=m
CONFIG_IR_ITE_CIR=m
CONFIG_IR_MCEUSB=m
CONFIG_IR_NUVOTON=m
CONFIG_IR_PWM_TX=m
CONFIG_IR_REDRAT3=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m
CONFIG_IR_SUNXI=m
CONFIG_IR_TOY=m
CONFIG_IR_TTUSBIR=m
CONFIG_RC_ATI_REMOTE=m
CONFIG_RC_LOOPBACK=m
# CONFIG_RC_XBOX_DVD is not set
CONFIG_CEC_CORE=m
CONFIG_CEC_NOTIFIER=y

#
# CEC support
#
CONFIG_MEDIA_CEC_RC=y
CONFIG_MEDIA_CEC_SUPPORT=y
CONFIG_CEC_CH7322=m
CONFIG_CEC_CROS_EC=m
CONFIG_USB_PULSE8_CEC=m
CONFIG_USB_RAINSHADOW_CEC=m
# end of CEC support

CONFIG_MEDIA_SUPPORT=m
# CONFIG_MEDIA_SUPPORT_FILTER is not set
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
CONFIG_MEDIA_RADIO_SUPPORT=y
CONFIG_MEDIA_SDR_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_TEST_SUPPORT=y
# end of Media device types

#
# Media core support
#
CONFIG_VIDEO_DEV=m
CONFIG_MEDIA_CONTROLLER=y
CONFIG_DVB_CORE=m
# end of Media core support

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_H264=m
CONFIG_V4L2_VP9=m
CONFIG_V4L2_MEM2MEM_DEV=m
# CONFIG_V4L2_FLASH_LED_CLASS is not set
CONFIG_V4L2_FWNODE=m
CONFIG_V4L2_ASYNC=m
CONFIG_VIDEOBUF_GEN=m
CONFIG_VIDEOBUF_DMA_SG=m
# end of Video4Linux options

#
# Media controller options
#
CONFIG_MEDIA_CONTROLLER_DVB=y
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
# end of Media controller options

#
# Digital TV options
#
# CONFIG_DVB_MMAP is not set
CONFIG_DVB_NET=y
CONFIG_DVB_MAX_ADAPTERS=8
CONFIG_DVB_DYNAMIC_MINORS=y
# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
# CONFIG_DVB_ULE_DEBUG is not set
# end of Digital TV options

#
# Media drivers
#

#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_GSPCA=m
CONFIG_USB_GSPCA_BENQ=m
CONFIG_USB_GSPCA_CONEX=m
CONFIG_USB_GSPCA_CPIA1=m
CONFIG_USB_GSPCA_DTCS033=m
CONFIG_USB_GSPCA_ETOMS=m
CONFIG_USB_GSPCA_FINEPIX=m
CONFIG_USB_GSPCA_JEILINJ=m
CONFIG_USB_GSPCA_JL2005BCD=m
CONFIG_USB_GSPCA_KINECT=m
CONFIG_USB_GSPCA_KONICA=m
CONFIG_USB_GSPCA_MARS=m
CONFIG_USB_GSPCA_MR97310A=m
CONFIG_USB_GSPCA_NW80X=m
CONFIG_USB_GSPCA_OV519=m
CONFIG_USB_GSPCA_OV534=m
CONFIG_USB_GSPCA_OV534_9=m
CONFIG_USB_GSPCA_PAC207=m
CONFIG_USB_GSPCA_PAC7302=m
CONFIG_USB_GSPCA_PAC7311=m
CONFIG_USB_GSPCA_SE401=m
CONFIG_USB_GSPCA_SN9C2028=m
CONFIG_USB_GSPCA_SN9C20X=m
CONFIG_USB_GSPCA_SONIXB=m
CONFIG_USB_GSPCA_SONIXJ=m
CONFIG_USB_GSPCA_SPCA1528=m
CONFIG_USB_GSPCA_SPCA500=m
CONFIG_USB_GSPCA_SPCA501=m
CONFIG_USB_GSPCA_SPCA505=m
CONFIG_USB_GSPCA_SPCA506=m
CONFIG_USB_GSPCA_SPCA508=m
CONFIG_USB_GSPCA_SPCA561=m
CONFIG_USB_GSPCA_SQ905=m
CONFIG_USB_GSPCA_SQ905C=m
CONFIG_USB_GSPCA_SQ930X=m
CONFIG_USB_GSPCA_STK014=m
CONFIG_USB_GSPCA_STK1135=m
CONFIG_USB_GSPCA_STV0680=m
CONFIG_USB_GSPCA_SUNPLUS=m
CONFIG_USB_GSPCA_T613=m
CONFIG_USB_GSPCA_TOPRO=m
CONFIG_USB_GSPCA_TOUPTEK=m
CONFIG_USB_GSPCA_TV8532=m
CONFIG_USB_GSPCA_VC032X=m
CONFIG_USB_GSPCA_VICAM=m
CONFIG_USB_GSPCA_XIRLINK_CIT=m
CONFIG_USB_GSPCA_ZC3XX=m
CONFIG_USB_GL860=m
CONFIG_USB_M5602=m
CONFIG_USB_STV06XX=m
CONFIG_USB_PWC=m
# CONFIG_USB_PWC_DEBUG is not set
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_USB_S2255=m
CONFIG_VIDEO_USBTV=m
CONFIG_USB_VIDEO_CLASS=m
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y

#
# Analog TV USB devices
#
CONFIG_VIDEO_GO7007=m
CONFIG_VIDEO_GO7007_USB=m
CONFIG_VIDEO_GO7007_LOADER=m
CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
CONFIG_VIDEO_HDPVR=m
CONFIG_VIDEO_PVRUSB2=m
CONFIG_VIDEO_PVRUSB2_SYSFS=y
CONFIG_VIDEO_PVRUSB2_DVB=y
# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
CONFIG_VIDEO_STK1160=m

#
# Analog/digital TV USB devices
#
CONFIG_VIDEO_AU0828=m
CONFIG_VIDEO_AU0828_V4L2=y
CONFIG_VIDEO_AU0828_RC=y
CONFIG_VIDEO_CX231XX=m
CONFIG_VIDEO_CX231XX_RC=y
CONFIG_VIDEO_CX231XX_ALSA=m
CONFIG_VIDEO_CX231XX_DVB=m

#
# Digital TV USB devices
#
CONFIG_DVB_AS102=m
CONFIG_DVB_B2C2_FLEXCOP_USB=m
# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
CONFIG_DVB_USB_V2=m
CONFIG_DVB_USB_AF9015=m
CONFIG_DVB_USB_AF9035=m
CONFIG_DVB_USB_ANYSEE=m
CONFIG_DVB_USB_AU6610=m
CONFIG_DVB_USB_AZ6007=m
CONFIG_DVB_USB_CE6230=m
CONFIG_DVB_USB_DVBSKY=m
CONFIG_DVB_USB_EC168=m
CONFIG_DVB_USB_GL861=m
CONFIG_DVB_USB_LME2510=m
CONFIG_DVB_USB_MXL111SF=m
CONFIG_DVB_USB_RTL28XXU=m
CONFIG_DVB_USB_ZD1301=m
CONFIG_DVB_USB=m
# CONFIG_DVB_USB_DEBUG is not set
CONFIG_DVB_USB_A800=m
CONFIG_DVB_USB_AF9005=m
CONFIG_DVB_USB_AF9005_REMOTE=m
CONFIG_DVB_USB_AZ6027=m
CONFIG_DVB_USB_CINERGY_T2=m
CONFIG_DVB_USB_CXUSB=m
# CONFIG_DVB_USB_CXUSB_ANALOG is not set
CONFIG_DVB_USB_DIB0700=m
CONFIG_DVB_USB_DIB3000MC=m
CONFIG_DVB_USB_DIBUSB_MB=m
# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
CONFIG_DVB_USB_DIBUSB_MC=m
CONFIG_DVB_USB_DIGITV=m
CONFIG_DVB_USB_DTT200U=m
CONFIG_DVB_USB_DTV5100=m
CONFIG_DVB_USB_DW2102=m
CONFIG_DVB_USB_GP8PSK=m
CONFIG_DVB_USB_M920X=m
CONFIG_DVB_USB_NOVA_T_USB2=m
CONFIG_DVB_USB_OPERA1=m
CONFIG_DVB_USB_PCTV452E=m
CONFIG_DVB_USB_TECHNISAT_USB2=m
CONFIG_DVB_USB_TTUSB2=m
CONFIG_DVB_USB_UMT_010=m
CONFIG_DVB_USB_VP702X=m
CONFIG_DVB_USB_VP7045=m
CONFIG_SMS_USB_DRV=m
CONFIG_DVB_TTUSB_BUDGET=m
CONFIG_DVB_TTUSB_DEC=m

#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=m
CONFIG_VIDEO_EM28XX_V4L2=m
CONFIG_VIDEO_EM28XX_ALSA=m
CONFIG_VIDEO_EM28XX_DVB=m
CONFIG_VIDEO_EM28XX_RC=m

#
# Software defined radio USB devices
#
CONFIG_USB_AIRSPY=m
CONFIG_USB_HACKRF=m
# CONFIG_USB_MSI2500 is not set
CONFIG_MEDIA_PCI_SUPPORT=y

#
# Media capture support
#
CONFIG_VIDEO_SOLO6X10=m
# CONFIG_VIDEO_TW5864 is not set
CONFIG_VIDEO_TW68=m
# CONFIG_VIDEO_TW686X is not set
# CONFIG_VIDEO_ZORAN is not set

#
# Media capture/analog TV support
#
CONFIG_VIDEO_DT3155=m
CONFIG_VIDEO_IVTV=m
CONFIG_VIDEO_IVTV_ALSA=m
CONFIG_VIDEO_FB_IVTV=m
CONFIG_VIDEO_HEXIUM_GEMINI=m
CONFIG_VIDEO_HEXIUM_ORION=m
CONFIG_VIDEO_MXB=m

#
# Media capture/analog/hybrid TV support
#
CONFIG_VIDEO_BT848=m
CONFIG_DVB_BT8XX=m
CONFIG_VIDEO_CX18=m
CONFIG_VIDEO_CX18_ALSA=m
CONFIG_VIDEO_CX23885=m
CONFIG_MEDIA_ALTERA_CI=m
CONFIG_VIDEO_CX25821=m
CONFIG_VIDEO_CX25821_ALSA=m
CONFIG_VIDEO_CX88=m
CONFIG_VIDEO_CX88_ALSA=m
CONFIG_VIDEO_CX88_BLACKBIRD=m
CONFIG_VIDEO_CX88_DVB=m
CONFIG_VIDEO_CX88_ENABLE_VP3054=y
CONFIG_VIDEO_CX88_VP3054=m
CONFIG_VIDEO_CX88_MPEG=m
CONFIG_VIDEO_SAA7134=m
CONFIG_VIDEO_SAA7134_ALSA=m
CONFIG_VIDEO_SAA7134_RC=y
CONFIG_VIDEO_SAA7134_DVB=m
CONFIG_VIDEO_SAA7134_GO7007=m
CONFIG_VIDEO_SAA7164=m

#
# Media digital TV PCI Adapters
#
CONFIG_DVB_B2C2_FLEXCOP_PCI=m
# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
CONFIG_DVB_DDBRIDGE=m
# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set
CONFIG_DVB_DM1105=m
CONFIG_MANTIS_CORE=m
CONFIG_DVB_MANTIS=m
CONFIG_DVB_HOPPER=m
# CONFIG_DVB_NETUP_UNIDVB is not set
CONFIG_DVB_NGENE=m
CONFIG_DVB_PLUTO2=m
CONFIG_DVB_PT1=m
CONFIG_DVB_PT3=m
CONFIG_DVB_SMIPCIE=m
CONFIG_DVB_BUDGET_CORE=m
CONFIG_DVB_BUDGET=m
CONFIG_DVB_BUDGET_CI=m
CONFIG_DVB_BUDGET_AV=m
CONFIG_RADIO_ADAPTERS=m
CONFIG_RADIO_MAXIRADIO=m
CONFIG_RADIO_SAA7706H=m
CONFIG_RADIO_SHARK=m
CONFIG_RADIO_SHARK2=m
CONFIG_RADIO_SI4713=m
CONFIG_RADIO_TEA575X=m
CONFIG_RADIO_TEA5764=m
CONFIG_RADIO_TEF6862=m
CONFIG_RADIO_WL1273=m
CONFIG_USB_DSBR=m
CONFIG_USB_KEENE=m
CONFIG_USB_MA901=m
CONFIG_USB_MR800=m
CONFIG_USB_RAREMONO=m
CONFIG_RADIO_SI470X=m
CONFIG_USB_SI470X=m
CONFIG_I2C_SI470X=m
CONFIG_USB_SI4713=m
CONFIG_PLATFORM_SI4713=m
CONFIG_I2C_SI4713=m
CONFIG_MEDIA_PLATFORM_DRIVERS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
# CONFIG_SDR_PLATFORM_DRIVERS is not set
# CONFIG_DVB_PLATFORM_DRIVERS is not set
CONFIG_V4L_MEM2MEM_DRIVERS=y
# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
# CONFIG_VIDEO_MUX is not set

#
# Allegro DVT media platform drivers
#

#
# Amlogic media platform drivers
#

#
# Amphion drivers
#

#
# Aspeed media platform drivers
#

#
# Atmel media platform drivers
#

#
# Cadence media platform drivers
#
# CONFIG_VIDEO_CADENCE_CSI2RX is not set
# CONFIG_VIDEO_CADENCE_CSI2TX is not set

#
# Chips&Media media platform drivers
#

#
# Intel media platform drivers
#

#
# Marvell media platform drivers
#
# CONFIG_VIDEO_CAFE_CCIC is not set

#
# Mediatek media platform drivers
#

#
# Microchip Technology, Inc. media platform drivers
#

#
# NVidia media platform drivers
#

#
# NXP media platform drivers
#

#
# Qualcomm media platform drivers
#

#
# Renesas media platform drivers
#

#
# Rockchip media platform drivers
#

#
# Samsung media platform drivers
#

#
# STMicroelectronics media platform drivers
#

#
# Sunxi media platform drivers
#
# CONFIG_VIDEO_SUN4I_CSI is not set
CONFIG_VIDEO_SUN6I_CSI=m
# CONFIG_VIDEO_SUN6I_MIPI_CSI2 is not set
# CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2 is not set
CONFIG_VIDEO_SUN8I_DEINTERLACE=m
# CONFIG_VIDEO_SUN8I_ROTATE is not set

#
# Texas Instruments drivers
#

#
# Verisilicon media platform drivers
#
CONFIG_VIDEO_HANTRO=m
CONFIG_VIDEO_HANTRO_SUNXI=y

#
# VIA media platform drivers
#

#
# Xilinx media platform drivers
#
# CONFIG_VIDEO_XILINX is not set

#
# MMC/SDIO DVB adapters
#
CONFIG_SMS_SDIO_DRV=m
# CONFIG_V4L_TEST_DRIVERS is not set
# CONFIG_DVB_TEST_DRIVERS is not set
CONFIG_MEDIA_COMMON_OPTIONS=y

#
# common driver options
#
CONFIG_CYPRESS_FIRMWARE=m
CONFIG_TTPCI_EEPROM=m
CONFIG_UVC_COMMON=m
CONFIG_VIDEO_CX2341X=m
CONFIG_VIDEO_TVEEPROM=m
CONFIG_DVB_B2C2_FLEXCOP=m
CONFIG_VIDEO_SAA7146=m
CONFIG_VIDEO_SAA7146_VV=m
CONFIG_SMS_SIANO_MDTV=m
CONFIG_SMS_SIANO_RC=y
# CONFIG_SMS_SIANO_DEBUGFS is not set
CONFIG_VIDEOBUF2_CORE=m
CONFIG_VIDEOBUF2_V4L2=m
CONFIG_VIDEOBUF2_MEMOPS=m
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=m
CONFIG_VIDEOBUF2_DMA_SG=m
CONFIG_VIDEOBUF2_DVB=m
# end of Media drivers

#
# Media ancillary drivers
#
CONFIG_MEDIA_ATTACH=y

#
# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
#
CONFIG_VIDEO_IR_I2C=m

#
# Camera sensor devices
#
# CONFIG_VIDEO_AR0521 is not set
# CONFIG_VIDEO_HI556 is not set
# CONFIG_VIDEO_HI846 is not set
# CONFIG_VIDEO_HI847 is not set
# CONFIG_VIDEO_IMX208 is not set
# CONFIG_VIDEO_IMX214 is not set
CONFIG_VIDEO_IMX219=m
# CONFIG_VIDEO_IMX258 is not set
# CONFIG_VIDEO_IMX274 is not set
# CONFIG_VIDEO_IMX290 is not set
# CONFIG_VIDEO_IMX296 is not set
# CONFIG_VIDEO_IMX319 is not set
# CONFIG_VIDEO_IMX334 is not set
# CONFIG_VIDEO_IMX335 is not set
# CONFIG_VIDEO_IMX355 is not set
# CONFIG_VIDEO_IMX412 is not set
# CONFIG_VIDEO_IMX415 is not set
# CONFIG_VIDEO_MT9M001 is not set
# CONFIG_VIDEO_MT9M111 is not set
# CONFIG_VIDEO_MT9P031 is not set
# CONFIG_VIDEO_MT9T112 is not set
CONFIG_VIDEO_MT9V011=m
# CONFIG_VIDEO_MT9V032 is not set
# CONFIG_VIDEO_MT9V111 is not set
# CONFIG_VIDEO_OG01A1B is not set
# CONFIG_VIDEO_OV01A10 is not set
# CONFIG_VIDEO_OV02A10 is not set
# CONFIG_VIDEO_OV08D10 is not set
# CONFIG_VIDEO_OV08X40 is not set
# CONFIG_VIDEO_OV13858 is not set
# CONFIG_VIDEO_OV13B10 is not set
CONFIG_VIDEO_OV2640=m
# CONFIG_VIDEO_OV2659 is not set
# CONFIG_VIDEO_OV2680 is not set
# CONFIG_VIDEO_OV2685 is not set
# CONFIG_VIDEO_OV2740 is not set
# CONFIG_VIDEO_OV4689 is not set
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
# CONFIG_VIDEO_OV5647 is not set
# CONFIG_VIDEO_OV5648 is not set
# CONFIG_VIDEO_OV5670 is not set
# CONFIG_VIDEO_OV5675 is not set
# CONFIG_VIDEO_OV5693 is not set
# CONFIG_VIDEO_OV5695 is not set
# CONFIG_VIDEO_OV6650 is not set
# CONFIG_VIDEO_OV7251 is not set
CONFIG_VIDEO_OV7640=m
# CONFIG_VIDEO_OV7670 is not set
# CONFIG_VIDEO_OV772X is not set
# CONFIG_VIDEO_OV7740 is not set
# CONFIG_VIDEO_OV8856 is not set
# CONFIG_VIDEO_OV8858 is not set
# CONFIG_VIDEO_OV8865 is not set
# CONFIG_VIDEO_OV9282 is not set
# CONFIG_VIDEO_OV9640 is not set
# CONFIG_VIDEO_OV9650 is not set
# CONFIG_VIDEO_OV9734 is not set
# CONFIG_VIDEO_RDACM20 is not set
# CONFIG_VIDEO_RDACM21 is not set
# CONFIG_VIDEO_RJ54N1 is not set
# CONFIG_VIDEO_S5C73M3 is not set
# CONFIG_VIDEO_S5K5BAF is not set
# CONFIG_VIDEO_S5K6A3 is not set
# CONFIG_VIDEO_ST_VGXY61 is not set
# CONFIG_VIDEO_CCS is not set
# CONFIG_VIDEO_ET8EK8 is not set
# end of Camera sensor devices

#
# Lens drivers
#
# CONFIG_VIDEO_AD5820 is not set
# CONFIG_VIDEO_AK7375 is not set
# CONFIG_VIDEO_DW9714 is not set
# CONFIG_VIDEO_DW9768 is not set
# CONFIG_VIDEO_DW9807_VCM is not set
# end of Lens drivers

#
# Flash devices
#
# CONFIG_VIDEO_ADP1653 is not set
# CONFIG_VIDEO_LM3560 is not set
# CONFIG_VIDEO_LM3646 is not set
# end of Flash devices

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_CS3308=m
CONFIG_VIDEO_CS5345=m
CONFIG_VIDEO_CS53L32A=m
CONFIG_VIDEO_MSP3400=m
CONFIG_VIDEO_SONY_BTF_MPX=m
# CONFIG_VIDEO_TDA1997X is not set
CONFIG_VIDEO_TDA7432=m
CONFIG_VIDEO_TDA9840=m
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
# CONFIG_VIDEO_TLV320AIC23B is not set
CONFIG_VIDEO_TVAUDIO=m
CONFIG_VIDEO_UDA1342=m
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_WM8739=m
CONFIG_VIDEO_WM8775=m
# end of Audio decoders, processors and mixers

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders

#
# Video decoders
#
# CONFIG_VIDEO_ADV7180 is not set
# CONFIG_VIDEO_ADV7183 is not set
# CONFIG_VIDEO_ADV748X is not set
# CONFIG_VIDEO_ADV7604 is not set
# CONFIG_VIDEO_ADV7842 is not set
# CONFIG_VIDEO_BT819 is not set
# CONFIG_VIDEO_BT856 is not set
# CONFIG_VIDEO_BT866 is not set
# CONFIG_VIDEO_ISL7998X is not set
# CONFIG_VIDEO_KS0127 is not set
# CONFIG_VIDEO_MAX9286 is not set
# CONFIG_VIDEO_ML86V7667 is not set
# CONFIG_VIDEO_SAA7110 is not set
CONFIG_VIDEO_SAA711X=m
# CONFIG_VIDEO_TC358743 is not set
# CONFIG_VIDEO_TC358746 is not set
# CONFIG_VIDEO_TVP514X is not set
CONFIG_VIDEO_TVP5150=m
# CONFIG_VIDEO_TVP7002 is not set
CONFIG_VIDEO_TW2804=m
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=m
# CONFIG_VIDEO_TW9910 is not set
# CONFIG_VIDEO_VPX3220 is not set

#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=m
CONFIG_VIDEO_CX25840=m
# end of Video decoders

#
# Video encoders
#
# CONFIG_VIDEO_ADV7170 is not set
# CONFIG_VIDEO_ADV7175 is not set
# CONFIG_VIDEO_ADV7343 is not set
# CONFIG_VIDEO_ADV7393 is not set
# CONFIG_VIDEO_AK881X is not set
CONFIG_VIDEO_SAA7127=m
# CONFIG_VIDEO_SAA7185 is not set
# CONFIG_VIDEO_THS8200 is not set
# end of Video encoders

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
CONFIG_VIDEO_UPD64083=m
# end of Video improvement chips

#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips

#
# SDR tuner chips
#
# CONFIG_SDR_MAX2175 is not set
# end of SDR tuner chips

#
# Miscellaneous helper chips
#
# CONFIG_VIDEO_I2C is not set
CONFIG_VIDEO_M52790=m
# CONFIG_VIDEO_ST_MIPID02 is not set
# CONFIG_VIDEO_THS7303 is not set
# end of Miscellaneous helper chips

#
# Media SPI Adapters
#
# CONFIG_CXD2880_SPI_DRV is not set
# CONFIG_VIDEO_GS1662 is not set
# end of Media SPI Adapters

CONFIG_MEDIA_TUNER=m

#
# Customize TV tuners
#
CONFIG_MEDIA_TUNER_E4000=m
CONFIG_MEDIA_TUNER_FC0011=m
CONFIG_MEDIA_TUNER_FC0012=m
CONFIG_MEDIA_TUNER_FC0013=m
CONFIG_MEDIA_TUNER_FC2580=m
CONFIG_MEDIA_TUNER_IT913X=m
CONFIG_MEDIA_TUNER_M88RS6000T=m
CONFIG_MEDIA_TUNER_MAX2165=m
CONFIG_MEDIA_TUNER_MC44S803=m
# CONFIG_MEDIA_TUNER_MSI001 is not set
CONFIG_MEDIA_TUNER_MT2060=m
CONFIG_MEDIA_TUNER_MT2063=m
CONFIG_MEDIA_TUNER_MT20XX=m
CONFIG_MEDIA_TUNER_MT2131=m
CONFIG_MEDIA_TUNER_MT2266=m
CONFIG_MEDIA_TUNER_MXL301RF=m
CONFIG_MEDIA_TUNER_MXL5005S=m
CONFIG_MEDIA_TUNER_MXL5007T=m
CONFIG_MEDIA_TUNER_QM1D1B0004=m
CONFIG_MEDIA_TUNER_QM1D1C0042=m
CONFIG_MEDIA_TUNER_QT1010=m
CONFIG_MEDIA_TUNER_R820T=m
CONFIG_MEDIA_TUNER_SI2157=m
CONFIG_MEDIA_TUNER_SIMPLE=m
CONFIG_MEDIA_TUNER_TDA18212=m
CONFIG_MEDIA_TUNER_TDA18218=m
CONFIG_MEDIA_TUNER_TDA18250=m
CONFIG_MEDIA_TUNER_TDA18271=m
CONFIG_MEDIA_TUNER_TDA827X=m
CONFIG_MEDIA_TUNER_TDA8290=m
CONFIG_MEDIA_TUNER_TDA9887=m
CONFIG_MEDIA_TUNER_TEA5761=m
CONFIG_MEDIA_TUNER_TEA5767=m
CONFIG_MEDIA_TUNER_TUA9001=m
CONFIG_MEDIA_TUNER_XC2028=m
CONFIG_MEDIA_TUNER_XC4000=m
CONFIG_MEDIA_TUNER_XC5000=m
# end of Customize TV tuners

#
# Customise DVB Frontends
#

#
# Multistandard (satellite) frontends
#
CONFIG_DVB_M88DS3103=m
CONFIG_DVB_MXL5XX=m
CONFIG_DVB_STB0899=m
CONFIG_DVB_STB6100=m
CONFIG_DVB_STV090x=m
CONFIG_DVB_STV0910=m
CONFIG_DVB_STV6110x=m
CONFIG_DVB_STV6111=m

#
# Multistandard (cable + terrestrial) frontends
#
CONFIG_DVB_DRXK=m
CONFIG_DVB_MN88472=m
CONFIG_DVB_MN88473=m
CONFIG_DVB_SI2165=m
CONFIG_DVB_TDA18271C2DD=m

#
# DVB-S (satellite) frontends
#
CONFIG_DVB_CX24110=m
CONFIG_DVB_CX24116=m
CONFIG_DVB_CX24117=m
CONFIG_DVB_CX24120=m
CONFIG_DVB_CX24123=m
CONFIG_DVB_DS3000=m
CONFIG_DVB_MB86A16=m
CONFIG_DVB_MT312=m
CONFIG_DVB_S5H1420=m
CONFIG_DVB_SI21XX=m
CONFIG_DVB_STB6000=m
CONFIG_DVB_STV0288=m
CONFIG_DVB_STV0299=m
CONFIG_DVB_STV0900=m
CONFIG_DVB_STV6110=m
CONFIG_DVB_TDA10071=m
CONFIG_DVB_TDA10086=m
CONFIG_DVB_TDA8083=m
CONFIG_DVB_TDA8261=m
CONFIG_DVB_TDA826X=m
CONFIG_DVB_TS2020=m
CONFIG_DVB_TUA6100=m
CONFIG_DVB_TUNER_CX24113=m
CONFIG_DVB_TUNER_ITD1000=m
CONFIG_DVB_VES1X93=m
CONFIG_DVB_ZL10036=m
CONFIG_DVB_ZL10039=m

#
# DVB-T (terrestrial) frontends
#
CONFIG_DVB_AF9013=m
CONFIG_DVB_AS102_FE=m
CONFIG_DVB_CX22700=m
CONFIG_DVB_CX22702=m
CONFIG_DVB_CXD2820R=m
CONFIG_DVB_CXD2841ER=m
CONFIG_DVB_DIB3000MB=m
CONFIG_DVB_DIB3000MC=m
CONFIG_DVB_DIB7000M=m
CONFIG_DVB_DIB7000P=m
# CONFIG_DVB_DIB9000 is not set
CONFIG_DVB_DRXD=m
CONFIG_DVB_EC100=m
CONFIG_DVB_GP8PSK_FE=m
CONFIG_DVB_L64781=m
CONFIG_DVB_MT352=m
CONFIG_DVB_NXT6000=m
CONFIG_DVB_RTL2830=m
CONFIG_DVB_RTL2832=m
CONFIG_DVB_RTL2832_SDR=m
# CONFIG_DVB_S5H1432 is not set
CONFIG_DVB_SI2168=m
CONFIG_DVB_SP887X=m
CONFIG_DVB_STV0367=m
CONFIG_DVB_TDA10048=m
CONFIG_DVB_TDA1004X=m
CONFIG_DVB_ZD1301_DEMOD=m
CONFIG_DVB_ZL10353=m
# CONFIG_DVB_CXD2880 is not set

#
# DVB-C (cable) frontends
#
CONFIG_DVB_STV0297=m
CONFIG_DVB_TDA10021=m
CONFIG_DVB_TDA10023=m
CONFIG_DVB_VES1820=m

#
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
#
CONFIG_DVB_AU8522=m
CONFIG_DVB_AU8522_DTV=m
CONFIG_DVB_AU8522_V4L=m
CONFIG_DVB_BCM3510=m
CONFIG_DVB_LG2160=m
CONFIG_DVB_LGDT3305=m
CONFIG_DVB_LGDT3306A=m
CONFIG_DVB_LGDT330X=m
CONFIG_DVB_MXL692=m
CONFIG_DVB_NXT200X=m
CONFIG_DVB_OR51132=m
CONFIG_DVB_OR51211=m
CONFIG_DVB_S5H1409=m
CONFIG_DVB_S5H1411=m

#
# ISDB-T (terrestrial) frontends
#
CONFIG_DVB_DIB8000=m
CONFIG_DVB_MB86A20S=m
CONFIG_DVB_S921=m

#
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
#
# CONFIG_DVB_MN88443X is not set
CONFIG_DVB_TC90522=m

#
# Digital terrestrial only tuners/PLL
#
CONFIG_DVB_PLL=m
CONFIG_DVB_TUNER_DIB0070=m
CONFIG_DVB_TUNER_DIB0090=m

#
# SEC control devices for DVB-S
#
CONFIG_DVB_A8293=m
CONFIG_DVB_AF9033=m
# CONFIG_DVB_ASCOT2E is not set
CONFIG_DVB_ATBM8830=m
# CONFIG_DVB_HELENE is not set
# CONFIG_DVB_HORUS3A is not set
CONFIG_DVB_ISL6405=m
CONFIG_DVB_ISL6421=m
CONFIG_DVB_ISL6423=m
CONFIG_DVB_IX2505V=m
# CONFIG_DVB_LGS8GL5 is not set
CONFIG_DVB_LGS8GXX=m
CONFIG_DVB_LNBH25=m
# CONFIG_DVB_LNBH29 is not set
CONFIG_DVB_LNBP21=m
CONFIG_DVB_LNBP22=m
CONFIG_DVB_M88RS2000=m
CONFIG_DVB_TDA665x=m
CONFIG_DVB_DRX39XYJ=m

#
# Common Interface (EN50221) controller drivers
#
CONFIG_DVB_CXD2099=m
CONFIG_DVB_SP2=m
# end of Customise DVB Frontends

#
# Tools to develop new frontends
#
CONFIG_DVB_DUMMY_FE=m
# end of Media ancillary drivers

#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
CONFIG_VIDEO_CMDLINE=y
CONFIG_VIDEO_NOMODESET=y
CONFIG_DRM=m
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_KMS_HELPER=m
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
CONFIG_DRM_LOAD_EDID_FIRMWARE=y
CONFIG_DRM_DP_AUX_BUS=m
CONFIG_DRM_DISPLAY_HELPER=m
CONFIG_DRM_DISPLAY_DP_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_TTM=m
CONFIG_DRM_VRAM_HELPER=m
CONFIG_DRM_TTM_HELPER=m
CONFIG_DRM_GEM_DMA_HELPER=m
CONFIG_DRM_GEM_SHMEM_HELPER=m
CONFIG_DRM_SUBALLOC_HELPER=m
CONFIG_DRM_SCHED=m

#
# I2C encoder or helper chips
#
CONFIG_DRM_I2C_CH7006=m
CONFIG_DRM_I2C_SIL164=m
CONFIG_DRM_I2C_NXP_TDA998X=m
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips

#
# ARM devices
#
CONFIG_DRM_HDLCD=m
# CONFIG_DRM_HDLCD_SHOW_UNDERRUN is not set
CONFIG_DRM_MALI_DISPLAY=m
# CONFIG_DRM_KOMEDA is not set
# end of ARM devices

CONFIG_DRM_RADEON=m
CONFIG_DRM_RADEON_USERPTR=y
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
CONFIG_DRM_VGEM=m
# CONFIG_DRM_VKMS is not set
# CONFIG_DRM_VMWGFX is not set
CONFIG_DRM_UDL=m
CONFIG_DRM_AST=m
CONFIG_DRM_MGAG200=m
CONFIG_DRM_SUN4I=m
CONFIG_DRM_SUN6I_DSI=m
CONFIG_DRM_SUN8I_DW_HDMI=m
CONFIG_DRM_SUN8I_MIXER=m
CONFIG_DRM_SUN8I_TCON_TOP=m
CONFIG_DRM_QXL=m
CONFIG_DRM_VIRTIO_GPU=m
# CONFIG_DRM_VIRTIO_GPU_KMS is not set
CONFIG_DRM_PANEL=y

#
# Display Panels
#
# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set
# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
# CONFIG_DRM_PANEL_DSI_CM is not set
# CONFIG_DRM_PANEL_LVDS is not set
CONFIG_DRM_PANEL_SIMPLE=m
# CONFIG_DRM_PANEL_EDP is not set
# CONFIG_DRM_PANEL_EBBG_FT8719 is not set
# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
# CONFIG_DRM_PANEL_JDI_R63452 is not set
# CONFIG_DRM_PANEL_KHADAS_TS050 is not set
# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
# CONFIG_DRM_PANEL_LG_LG4573 is not set
# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set
# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set
# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set
# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set
# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_CHIPONE_ICN6211 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
# CONFIG_DRM_CROS_EC_ANX7688 is not set
CONFIG_DRM_DISPLAY_CONNECTOR=m
# CONFIG_DRM_ITE_IT6505 is not set
# CONFIG_DRM_LONTIUM_LT8912B is not set
# CONFIG_DRM_LONTIUM_LT9211 is not set
CONFIG_DRM_LONTIUM_LT9611=m
# CONFIG_DRM_LONTIUM_LT9611UXC is not set
# CONFIG_DRM_ITE_IT66121 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
CONFIG_DRM_NWL_MIPI_DSI=m
CONFIG_DRM_NXP_PTN3460=m
CONFIG_DRM_PARADE_PS8622=m
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_SAMSUNG_DSIM is not set
CONFIG_DRM_SIL_SII8620=m
CONFIG_DRM_SII902X=m
# CONFIG_DRM_SII9234 is not set
CONFIG_DRM_SIMPLE_BRIDGE=m
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
CONFIG_DRM_TOSHIBA_TC358767=m
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_DLPC3433 is not set
CONFIG_DRM_TI_TFP410=m
# CONFIG_DRM_TI_SN65DSI83 is not set
CONFIG_DRM_TI_SN65DSI86=m
# CONFIG_DRM_TI_TPD12S015 is not set
CONFIG_DRM_ANALOGIX_ANX6345=m
CONFIG_DRM_ANALOGIX_ANX78XX=m
CONFIG_DRM_ANALOGIX_DP=m
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
CONFIG_DRM_I2C_ADV7511=m
CONFIG_DRM_I2C_ADV7511_AUDIO=y
CONFIG_DRM_I2C_ADV7511_CEC=y
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=m
# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set
CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
CONFIG_DRM_DW_HDMI_CEC=m
# end of Display Interface Bridges

CONFIG_DRM_ETNAVIV=m
CONFIG_DRM_ETNAVIV_THERMAL=y
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
# CONFIG_DRM_LOGICVC is not set
# CONFIG_DRM_ARCPGU is not set
CONFIG_DRM_BOCHS=m
CONFIG_DRM_CIRRUS_QEMU=m
# CONFIG_DRM_GM12U320 is not set
# CONFIG_DRM_PANEL_MIPI_DBI is not set
# CONFIG_DRM_SIMPLEDRM is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9163 is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
CONFIG_DRM_PL111=m
CONFIG_DRM_LIMA=m
CONFIG_DRM_PANFROST=m
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_GUD is not set
# CONFIG_DRM_SSD130X is not set
CONFIG_DRM_LEGACY=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y

#
# Frame buffer Devices
#
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_IO_HELPERS=y
CONFIG_FB_SYS_HELPERS=y
CONFIG_FB_SYS_HELPERS_DEFERRED=y
CONFIG_FB_BACKLIGHT=m
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y

#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_ARMCLCD is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_UVESA is not set
CONFIG_FB_EFI=y
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SM501 is not set
# CONFIG_FB_SMSCUFX is not set
CONFIG_FB_UDL=m
# CONFIG_FB_IBM_GXT4500 is not set
CONFIG_FB_VIRTUAL=m
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
CONFIG_FB_SIMPLE=y
CONFIG_FB_SSD1307=m
# CONFIG_FB_SM712 is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_L4F00242T03 is not set
# CONFIG_LCD_LMS283GF05 is not set
# CONFIG_LCD_LTV350QV is not set
# CONFIG_LCD_ILI922X is not set
# CONFIG_LCD_ILI9320 is not set
# CONFIG_LCD_TDO24M is not set
# CONFIG_LCD_VGG2432A4 is not set
CONFIG_LCD_PLATFORM=m
# CONFIG_LCD_AMS369FG06 is not set
# CONFIG_LCD_LMS501KF03 is not set
# CONFIG_LCD_HX8357 is not set
# CONFIG_LCD_OTM3225A is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_KTD253 is not set
# CONFIG_BACKLIGHT_KTZ8866 is not set
CONFIG_BACKLIGHT_PWM=m
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
CONFIG_BACKLIGHT_LP855X=m
CONFIG_BACKLIGHT_GPIO=m
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# CONFIG_BACKLIGHT_LED is not set
# end of Backlight & LCD device support

CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
# end of Console display driver support

CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_LOGO_LINUX_CLUT224=y
# end of Graphics support

# CONFIG_DRM_ACCEL is not set
CONFIG_SOUND=y
CONFIG_SOUND_OSS_CORE=y
CONFIG_SOUND_OSS_CORE_PRECLAIM=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=m
CONFIG_SND_SEQ_DEVICE=m
CONFIG_SND_RAWMIDI=m
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=m
CONFIG_SND_PCM_OSS=m
CONFIG_SND_PCM_OSS_PLUGINS=y
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=m
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_CTL_FAST_LOOKUP is not set
# CONFIG_SND_DEBUG is not set
# CONFIG_SND_CTL_INPUT_VALIDATION is not set
CONFIG_SND_VMASTER=y
CONFIG_SND_CTL_LED=m
CONFIG_SND_SEQUENCER=m
CONFIG_SND_SEQ_DUMMY=m
CONFIG_SND_SEQUENCER_OSS=m
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
CONFIG_SND_SEQ_MIDI_EVENT=m
CONFIG_SND_SEQ_MIDI=m
CONFIG_SND_SEQ_MIDI_EMUL=m
CONFIG_SND_SEQ_VIRMIDI=m
# CONFIG_SND_SEQ_UMP is not set
CONFIG_SND_MPU401_UART=m
CONFIG_SND_OPL3_LIB=m
CONFIG_SND_OPL3_LIB_SEQ=m
CONFIG_SND_VX_LIB=m
CONFIG_SND_AC97_CODEC=m
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
# CONFIG_SND_PCMTEST is not set
CONFIG_SND_VIRMIDI=m
CONFIG_SND_MTPAV=m
CONFIG_SND_SERIAL_U16550=m
# CONFIG_SND_SERIAL_GENERIC is not set
CONFIG_SND_MPU401=m
CONFIG_SND_AC97_POWER_SAVE=y
CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
CONFIG_SND_PCI=y
CONFIG_SND_AD1889=m
# CONFIG_SND_ALS300 is not set
# CONFIG_SND_ALI5451 is not set
CONFIG_SND_ATIIXP=m
CONFIG_SND_ATIIXP_MODEM=m
CONFIG_SND_AU8810=m
CONFIG_SND_AU8820=m
CONFIG_SND_AU8830=m
# CONFIG_SND_AW2 is not set
# CONFIG_SND_AZT3328 is not set
CONFIG_SND_BT87X=m
# CONFIG_SND_BT87X_OVERCLOCK is not set
CONFIG_SND_CA0106=m
CONFIG_SND_CMIPCI=m
CONFIG_SND_OXYGEN_LIB=m
CONFIG_SND_OXYGEN=m
CONFIG_SND_CS4281=m
CONFIG_SND_CS46XX=m
CONFIG_SND_CS46XX_NEW_DSP=y
CONFIG_SND_CTXFI=m
CONFIG_SND_DARLA20=m
CONFIG_SND_GINA20=m
CONFIG_SND_LAYLA20=m
CONFIG_SND_DARLA24=m
CONFIG_SND_GINA24=m
CONFIG_SND_LAYLA24=m
CONFIG_SND_MONA=m
CONFIG_SND_MIA=m
CONFIG_SND_ECHO3G=m
CONFIG_SND_INDIGO=m
CONFIG_SND_INDIGOIO=m
CONFIG_SND_INDIGODJ=m
CONFIG_SND_INDIGOIOX=m
CONFIG_SND_INDIGODJX=m
# CONFIG_SND_EMU10K1 is not set
# CONFIG_SND_EMU10K1X is not set
CONFIG_SND_ENS1370=m
CONFIG_SND_ENS1371=m
# CONFIG_SND_ES1938 is not set
# CONFIG_SND_ES1968 is not set
CONFIG_SND_FM801=m
CONFIG_SND_FM801_TEA575X_BOOL=y
CONFIG_SND_HDSP=m
CONFIG_SND_HDSPM=m
# CONFIG_SND_ICE1712 is not set
CONFIG_SND_ICE1724=m
CONFIG_SND_INTEL8X0=m
CONFIG_SND_INTEL8X0M=m
CONFIG_SND_KORG1212=m
CONFIG_SND_LOLA=m
CONFIG_SND_LX6464ES=m
# CONFIG_SND_MAESTRO3 is not set
CONFIG_SND_MIXART=m
CONFIG_SND_NM256=m
CONFIG_SND_PCXHR=m
CONFIG_SND_RIPTIDE=m
CONFIG_SND_RME32=m
CONFIG_SND_RME96=m
CONFIG_SND_RME9652=m
# CONFIG_SND_SONICVIBES is not set
# CONFIG_SND_TRIDENT is not set
CONFIG_SND_VIA82XX=m
CONFIG_SND_VIA82XX_MODEM=m
CONFIG_SND_VIRTUOSO=m
CONFIG_SND_VX222=m
CONFIG_SND_YMFPCI=m

#
# HD-Audio
#
CONFIG_SND_HDA=m
CONFIG_SND_HDA_GENERIC_LEDS=y
CONFIG_SND_HDA_INTEL=m
CONFIG_SND_HDA_HWDEP=y
CONFIG_SND_HDA_RECONFIG=y
CONFIG_SND_HDA_INPUT_BEEP=y
CONFIG_SND_HDA_INPUT_BEEP_MODE=0
CONFIG_SND_HDA_PATCH_LOADER=y
# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
CONFIG_SND_HDA_CODEC_REALTEK=m
CONFIG_SND_HDA_CODEC_ANALOG=m
CONFIG_SND_HDA_CODEC_SIGMATEL=m
CONFIG_SND_HDA_CODEC_VIA=m
CONFIG_SND_HDA_CODEC_HDMI=m
CONFIG_SND_HDA_CODEC_CIRRUS=m
# CONFIG_SND_HDA_CODEC_CS8409 is not set
CONFIG_SND_HDA_CODEC_CONEXANT=m
CONFIG_SND_HDA_CODEC_CA0110=m
CONFIG_SND_HDA_CODEC_CA0132=m
CONFIG_SND_HDA_CODEC_CA0132_DSP=y
CONFIG_SND_HDA_CODEC_CMEDIA=m
CONFIG_SND_HDA_CODEC_SI3054=m
CONFIG_SND_HDA_GENERIC=m
CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
# CONFIG_SND_HDA_CTL_DEV_ID is not set
# end of HD-Audio

CONFIG_SND_HDA_CORE=m
CONFIG_SND_HDA_DSP_LOADER=y
CONFIG_SND_HDA_COMPONENT=y
CONFIG_SND_HDA_PREALLOC_SIZE=4096
CONFIG_SND_INTEL_NHLT=y
CONFIG_SND_INTEL_DSP_CONFIG=m
CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m
CONFIG_SND_SPI=y
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
# CONFIG_SND_USB_AUDIO_MIDI_V2 is not set
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
# CONFIG_SND_BCD2000 is not set
CONFIG_SND_USB_LINE6=m
CONFIG_SND_USB_POD=m
CONFIG_SND_USB_PODHD=m
CONFIG_SND_USB_TONEPORT=m
CONFIG_SND_USB_VARIAX=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
# CONFIG_SND_SOC_ADI is not set
CONFIG_SND_SOC_AMD_ACP=m
# CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH is not set
# CONFIG_SND_SOC_AMD_CZ_RT5645_MACH is not set
# CONFIG_SND_SOC_AMD_ST_ES8336_MACH is not set
# CONFIG_SND_AMD_ACP_CONFIG is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
# CONFIG_SND_DESIGNWARE_I2S is not set

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
CONFIG_SND_SOC_FSL_ASRC=m
CONFIG_SND_SOC_FSL_SAI=m
# CONFIG_SND_SOC_FSL_MQS is not set
CONFIG_SND_SOC_FSL_AUDMIX=m
# CONFIG_SND_SOC_FSL_SSI is not set
CONFIG_SND_SOC_FSL_SPDIF=m
# CONFIG_SND_SOC_FSL_ESAI is not set
CONFIG_SND_SOC_FSL_MICFIL=m
CONFIG_SND_SOC_FSL_EASRC=m
# CONFIG_SND_SOC_FSL_XCVR is not set
CONFIG_SND_SOC_FSL_UTILS=m
# CONFIG_SND_SOC_FSL_RPMSG is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs

# CONFIG_SND_SOC_CHV3_I2S is not set
CONFIG_SND_I2S_HI6210_I2S=m
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set

#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support

#
# Allwinner SoC Audio support
#
CONFIG_SND_SUN4I_CODEC=m
CONFIG_SND_SUN8I_CODEC=m
CONFIG_SND_SUN8I_CODEC_ANALOG=m
CONFIG_SND_SUN50I_CODEC_ANALOG=m
CONFIG_SND_SUN4I_I2S=m
CONFIG_SND_SUN4I_SPDIF=m
# CONFIG_SND_SUN50I_DMIC is not set
CONFIG_SND_SUN9I_HDMI_AUDIO=m
CONFIG_SND_SUN8I_ADDA_PR_REGMAP=m
# end of Allwinner SoC Audio support

# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# CONFIG_SND_SOC_XTFPGA_I2S is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
# CONFIG_SND_SOC_AC97_CODEC is not set
# CONFIG_SND_SOC_ADAU1372_I2C is not set
# CONFIG_SND_SOC_ADAU1372_SPI is not set
# CONFIG_SND_SOC_ADAU1701 is not set
# CONFIG_SND_SOC_ADAU1761_I2C is not set
# CONFIG_SND_SOC_ADAU1761_SPI is not set
# CONFIG_SND_SOC_ADAU7002 is not set
# CONFIG_SND_SOC_ADAU7118_HW is not set
# CONFIG_SND_SOC_ADAU7118_I2C is not set
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_AK4118 is not set
# CONFIG_SND_SOC_AK4375 is not set
# CONFIG_SND_SOC_AK4458 is not set
# CONFIG_SND_SOC_AK4554 is not set
# CONFIG_SND_SOC_AK4613 is not set
# CONFIG_SND_SOC_AK4642 is not set
# CONFIG_SND_SOC_AK5386 is not set
# CONFIG_SND_SOC_AK5558 is not set
# CONFIG_SND_SOC_ALC5623 is not set
# CONFIG_SND_SOC_AW8738 is not set
# CONFIG_SND_SOC_AW88395 is not set
# CONFIG_SND_SOC_BD28623 is not set
# CONFIG_SND_SOC_BT_SCO is not set
# CONFIG_SND_SOC_CHV3_CODEC is not set
CONFIG_SND_SOC_CROS_EC_CODEC=m
# CONFIG_SND_SOC_CS35L32 is not set
# CONFIG_SND_SOC_CS35L33 is not set
# CONFIG_SND_SOC_CS35L34 is not set
# CONFIG_SND_SOC_CS35L35 is not set
# CONFIG_SND_SOC_CS35L36 is not set
# CONFIG_SND_SOC_CS35L41_SPI is not set
# CONFIG_SND_SOC_CS35L41_I2C is not set
# CONFIG_SND_SOC_CS35L45_SPI is not set
# CONFIG_SND_SOC_CS35L45_I2C is not set
# CONFIG_SND_SOC_CS35L56_I2C is not set
# CONFIG_SND_SOC_CS35L56_SPI is not set
# CONFIG_SND_SOC_CS35L56_SDW is not set
# CONFIG_SND_SOC_CS42L42 is not set
# CONFIG_SND_SOC_CS42L42_SDW is not set
# CONFIG_SND_SOC_CS42L51_I2C is not set
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_CS42L73 is not set
# CONFIG_SND_SOC_CS42L83 is not set
# CONFIG_SND_SOC_CS4234 is not set
# CONFIG_SND_SOC_CS4265 is not set
# CONFIG_SND_SOC_CS4270 is not set
# CONFIG_SND_SOC_CS4271_I2C is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_CS42XX8_I2C is not set
# CONFIG_SND_SOC_CS43130 is not set
# CONFIG_SND_SOC_CS4341 is not set
# CONFIG_SND_SOC_CS4349 is not set
# CONFIG_SND_SOC_CS53L30 is not set
# CONFIG_SND_SOC_CX2072X is not set
# CONFIG_SND_SOC_DA7213 is not set
CONFIG_SND_SOC_DMIC=m
CONFIG_SND_SOC_HDMI_CODEC=m
# CONFIG_SND_SOC_ES7134 is not set
# CONFIG_SND_SOC_ES7241 is not set
# CONFIG_SND_SOC_ES8316 is not set
# CONFIG_SND_SOC_ES8326 is not set
CONFIG_SND_SOC_ES8328=m
CONFIG_SND_SOC_ES8328_I2C=m
CONFIG_SND_SOC_ES8328_SPI=m
# CONFIG_SND_SOC_GTM601 is not set
# CONFIG_SND_SOC_HDA is not set
# CONFIG_SND_SOC_ICS43432 is not set
# CONFIG_SND_SOC_IDT821034 is not set
# CONFIG_SND_SOC_INNO_RK3036 is not set
# CONFIG_SND_SOC_MAX98088 is not set
# CONFIG_SND_SOC_MAX98090 is not set
CONFIG_SND_SOC_MAX98357A=m
# CONFIG_SND_SOC_MAX98504 is not set
# CONFIG_SND_SOC_MAX9867 is not set
CONFIG_SND_SOC_MAX98927=m
# CONFIG_SND_SOC_MAX98520 is not set
# CONFIG_SND_SOC_MAX98363 is not set
# CONFIG_SND_SOC_MAX98373_I2C is not set
# CONFIG_SND_SOC_MAX98373_SDW is not set
# CONFIG_SND_SOC_MAX98388 is not set
# CONFIG_SND_SOC_MAX98390 is not set
# CONFIG_SND_SOC_MAX98396 is not set
# CONFIG_SND_SOC_MAX9860 is not set
CONFIG_SND_SOC_MSM8916_WCD_ANALOG=y
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y
# CONFIG_SND_SOC_PCM1681 is not set
# CONFIG_SND_SOC_PCM1789_I2C is not set
# CONFIG_SND_SOC_PCM179X_I2C is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_I2C is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3060_I2C is not set
# CONFIG_SND_SOC_PCM3060_SPI is not set
CONFIG_SND_SOC_PCM3168A=m
CONFIG_SND_SOC_PCM3168A_I2C=m
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM5102A is not set
# CONFIG_SND_SOC_PCM512x_I2C is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
# CONFIG_SND_SOC_PEB2466 is not set
CONFIG_SND_SOC_RK3328=m
# CONFIG_SND_SOC_RT1308_SDW is not set
# CONFIG_SND_SOC_RT1316_SDW is not set
# CONFIG_SND_SOC_RT1318_SDW is not set
# CONFIG_SND_SOC_RT5616 is not set
# CONFIG_SND_SOC_RT5631 is not set
# CONFIG_SND_SOC_RT5640 is not set
# CONFIG_SND_SOC_RT5659 is not set
# CONFIG_SND_SOC_RT5682_SDW is not set
# CONFIG_SND_SOC_RT700_SDW is not set
# CONFIG_SND_SOC_RT711_SDW is not set
# CONFIG_SND_SOC_RT711_SDCA_SDW is not set
# CONFIG_SND_SOC_RT712_SDCA_SDW is not set
# CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW is not set
# CONFIG_SND_SOC_RT722_SDCA_SDW is not set
# CONFIG_SND_SOC_RT715_SDW is not set
# CONFIG_SND_SOC_RT715_SDCA_SDW is not set
# CONFIG_SND_SOC_RT9120 is not set
# CONFIG_SND_SOC_SDW_MOCKUP is not set
# CONFIG_SND_SOC_SGTL5000 is not set
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
# CONFIG_SND_SOC_SIMPLE_MUX is not set
# CONFIG_SND_SOC_SMA1303 is not set
# CONFIG_SND_SOC_SPDIF is not set
# CONFIG_SND_SOC_SRC4XXX_I2C is not set
# CONFIG_SND_SOC_SSM2305 is not set
# CONFIG_SND_SOC_SSM2518 is not set
# CONFIG_SND_SOC_SSM2602_SPI is not set
# CONFIG_SND_SOC_SSM2602_I2C is not set
# CONFIG_SND_SOC_SSM3515 is not set
# CONFIG_SND_SOC_SSM4567 is not set
# CONFIG_SND_SOC_STA32X is not set
# CONFIG_SND_SOC_STA350 is not set
# CONFIG_SND_SOC_STI_SAS is not set
# CONFIG_SND_SOC_TAS2552 is not set
# CONFIG_SND_SOC_TAS2562 is not set
# CONFIG_SND_SOC_TAS2764 is not set
# CONFIG_SND_SOC_TAS2770 is not set
# CONFIG_SND_SOC_TAS2780 is not set
# CONFIG_SND_SOC_TAS2781_I2C is not set
# CONFIG_SND_SOC_TAS5086 is not set
# CONFIG_SND_SOC_TAS571X is not set
# CONFIG_SND_SOC_TAS5720 is not set
# CONFIG_SND_SOC_TAS5805M is not set
# CONFIG_SND_SOC_TAS6424 is not set
# CONFIG_SND_SOC_TDA7419 is not set
# CONFIG_SND_SOC_TFA9879 is not set
# CONFIG_SND_SOC_TFA989X is not set
# CONFIG_SND_SOC_TLV320ADC3XXX is not set
# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC31XX is not set
# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set
# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set
# CONFIG_SND_SOC_TLV320ADCX140 is not set
CONFIG_SND_SOC_TS3A227E=m
# CONFIG_SND_SOC_TSCS42XX is not set
# CONFIG_SND_SOC_TSCS454 is not set
# CONFIG_SND_SOC_UDA1334 is not set
# CONFIG_SND_SOC_WCD9335 is not set
CONFIG_SND_SOC_WCD_MBHC=m
CONFIG_SND_SOC_WCD934X=m
# CONFIG_SND_SOC_WCD938X_SDW is not set
# CONFIG_SND_SOC_WM8510 is not set
# CONFIG_SND_SOC_WM8523 is not set
# CONFIG_SND_SOC_WM8524 is not set
# CONFIG_SND_SOC_WM8580 is not set
# CONFIG_SND_SOC_WM8711 is not set
# CONFIG_SND_SOC_WM8728 is not set
# CONFIG_SND_SOC_WM8731_I2C is not set
# CONFIG_SND_SOC_WM8731_SPI is not set
# CONFIG_SND_SOC_WM8737 is not set
# CONFIG_SND_SOC_WM8741 is not set
# CONFIG_SND_SOC_WM8750 is not set
# CONFIG_SND_SOC_WM8753 is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8776 is not set
# CONFIG_SND_SOC_WM8782 is not set
# CONFIG_SND_SOC_WM8804_I2C is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_WM8903 is not set
CONFIG_SND_SOC_WM8904=m
# CONFIG_SND_SOC_WM8940 is not set
# CONFIG_SND_SOC_WM8960 is not set
# CONFIG_SND_SOC_WM8961 is not set
# CONFIG_SND_SOC_WM8962 is not set
# CONFIG_SND_SOC_WM8974 is not set
# CONFIG_SND_SOC_WM8978 is not set
# CONFIG_SND_SOC_WM8985 is not set
CONFIG_SND_SOC_WSA881X=m
# CONFIG_SND_SOC_WSA883X is not set
# CONFIG_SND_SOC_WSA884X is not set
# CONFIG_SND_SOC_ZL38060 is not set
# CONFIG_SND_SOC_MAX9759 is not set
# CONFIG_SND_SOC_MT6351 is not set
# CONFIG_SND_SOC_MT6358 is not set
# CONFIG_SND_SOC_MT6660 is not set
# CONFIG_SND_SOC_NAU8315 is not set
# CONFIG_SND_SOC_NAU8540 is not set
# CONFIG_SND_SOC_NAU8810 is not set
# CONFIG_SND_SOC_NAU8821 is not set
# CONFIG_SND_SOC_NAU8822 is not set
# CONFIG_SND_SOC_NAU8824 is not set
# CONFIG_SND_SOC_TPA6130A2 is not set
# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set
# CONFIG_SND_SOC_LPASS_VA_MACRO is not set
# CONFIG_SND_SOC_LPASS_RX_MACRO is not set
# CONFIG_SND_SOC_LPASS_TX_MACRO is not set
CONFIG_SND_SOC_ACX00=y
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set
# CONFIG_SND_TEST_COMPONENT is not set
# CONFIG_SND_VIRTIO is not set
CONFIG_AC97_BUS=m
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_BATTERY_STRENGTH is not set
# CONFIG_HIDRAW is not set
# CONFIG_UHID is not set
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
# CONFIG_HID_A4TECH is not set
# CONFIG_HID_ACCUTOUCH is not set
# CONFIG_HID_ACRUX is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_APPLEIR is not set
# CONFIG_HID_ASUS is not set
# CONFIG_HID_AUREAL is not set
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_BETOP_FF is not set
# CONFIG_HID_BIGBEN_FF is not set
# CONFIG_HID_CHERRY is not set
# CONFIG_HID_CHICONY is not set
# CONFIG_HID_CORSAIR is not set
# CONFIG_HID_COUGAR is not set
# CONFIG_HID_MACALLY is not set
# CONFIG_HID_PRODIKEYS is not set
# CONFIG_HID_CMEDIA is not set
# CONFIG_HID_CREATIVE_SB0540 is not set
# CONFIG_HID_CYPRESS is not set
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EMS_FF is not set
# CONFIG_HID_ELAN is not set
# CONFIG_HID_ELECOM is not set
# CONFIG_HID_ELO is not set
# CONFIG_HID_EVISION is not set
# CONFIG_HID_EZKEY is not set
# CONFIG_HID_GEMBIRD is not set
# CONFIG_HID_GFRM is not set
# CONFIG_HID_GLORIOUS is not set
# CONFIG_HID_HOLTEK is not set
# CONFIG_HID_GOOGLE_HAMMER is not set
# CONFIG_HID_VIVALDI is not set
# CONFIG_HID_GT683R is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
# CONFIG_HID_UCLOGIC is not set
# CONFIG_HID_WALTOP is not set
# CONFIG_HID_VIEWSONIC is not set
# CONFIG_HID_VRC2 is not set
# CONFIG_HID_XIAOMI is not set
# CONFIG_HID_GYRATION is not set
# CONFIG_HID_ICADE is not set
# CONFIG_HID_ITE is not set
# CONFIG_HID_JABRA is not set
# CONFIG_HID_TWINHAN is not set
# CONFIG_HID_KENSINGTON is not set
# CONFIG_HID_LCPOWER is not set
# CONFIG_HID_LED is not set
# CONFIG_HID_LENOVO is not set
# CONFIG_HID_LETSKETCH is not set
# CONFIG_HID_LOGITECH is not set
# CONFIG_HID_MAGICMOUSE is not set
# CONFIG_HID_MALTRON is not set
# CONFIG_HID_MAYFLASH is not set
# CONFIG_HID_MEGAWORLD_FF is not set
# CONFIG_HID_REDRAGON is not set
# CONFIG_HID_MICROSOFT is not set
# CONFIG_HID_MONTEREY is not set
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_NINTENDO is not set
# CONFIG_HID_NTI is not set
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_ORTEK is not set
# CONFIG_HID_PANTHERLORD is not set
# CONFIG_HID_PENMOUNT is not set
# CONFIG_HID_PETALYNX is not set
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_PLANTRONICS is not set
# CONFIG_HID_PXRC is not set
# CONFIG_HID_RAZER is not set
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_RETRODE is not set
# CONFIG_HID_ROCCAT is not set
# CONFIG_HID_SAITEK is not set
# CONFIG_HID_SAMSUNG is not set
# CONFIG_HID_SEMITEK is not set
# CONFIG_HID_SIGMAMICRO is not set
# CONFIG_HID_SONY is not set
# CONFIG_HID_SPEEDLINK is not set
# CONFIG_HID_STEAM is not set
# CONFIG_HID_STEELSERIES is not set
# CONFIG_HID_SUNPLUS is not set
# CONFIG_HID_RMI is not set
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
# CONFIG_HID_TIVO is not set
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_TOPRE is not set
# CONFIG_HID_THINGM is not set
# CONFIG_HID_THRUSTMASTER is not set
# CONFIG_HID_UDRAW_PS3 is not set
# CONFIG_HID_U2FZERO is not set
# CONFIG_HID_WACOM is not set
# CONFIG_HID_WIIMOTE is not set
# CONFIG_HID_XINMO is not set
# CONFIG_HID_ZEROPLUS is not set
# CONFIG_HID_ZYDACRON is not set
# CONFIG_HID_SENSOR_HUB is not set
# CONFIG_HID_ALPS is not set
# CONFIG_HID_MCP2221 is not set
# end of Special HID drivers

#
# HID-BPF support
#
# end of HID-BPF support

#
# USB HID support
#
CONFIG_USB_HID=m
# CONFIG_HID_PID is not set
# CONFIG_USB_HIDDEV is not set

#
# USB HID Boot Protocol drivers
#
# CONFIG_USB_KBD is not set
# CONFIG_USB_MOUSE is not set
# end of USB HID Boot Protocol drivers
# end of USB HID support

CONFIG_I2C_HID=y
# CONFIG_I2C_HID_ACPI is not set
# CONFIG_I2C_HID_OF is not set
# CONFIG_I2C_HID_OF_ELAN is not set
# CONFIG_I2C_HID_OF_GOODIX is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_LED_TRIG=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_CONN_GPIO=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
# CONFIG_USB_OTG_FSM is not set
# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=y

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=y
# CONFIG_USB_XHCI_PCI_RENESAS is not set
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
# CONFIG_USB_EHCI_FSL is not set
CONFIG_USB_EHCI_HCD_PLATFORM=y
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_MAX3421_HCD is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PCI=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_UHCI_HCD=y
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_HCD_BCMA is not set
# CONFIG_USB_HCD_SSB is not set
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=m
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
# CONFIG_USB_STORAGE is not set

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
CONFIG_USB_MICROTEK=m
CONFIG_USBIP_CORE=m
CONFIG_USBIP_VHCI_HCD=m
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=m
CONFIG_USBIP_VUDC=m
# CONFIG_USBIP_DEBUG is not set

#
# USB dual-mode controller drivers
#
# CONFIG_USB_CDNS_SUPPORT is not set
CONFIG_USB_MUSB_HDRC=y
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y

#
# Platform Glue Layer
#
CONFIG_USB_MUSB_SUNXI=y

#
# MUSB DMA mode
#
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_ULPI=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y

#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=y
CONFIG_USB_DWC3_HAPS=y
CONFIG_USB_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
CONFIG_USB_DWC2_PCI=y
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
# CONFIG_USB_CHIPIDEA is not set
CONFIG_USB_ISP1760=y
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_ISP1761_UDC=y
# CONFIG_USB_ISP1760_HOST_ROLE is not set
# CONFIG_USB_ISP1760_GADGET_ROLE is not set
CONFIG_USB_ISP1760_DUAL_ROLE=y

#
# USB port drivers
#
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=m
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=m
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=m
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=m
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_F81232=m
CONFIG_USB_SERIAL_F8153X=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=m
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_METRO=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MXUPORT=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=m
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=m
CONFIG_USB_SERIAL_QUALCOMM=m
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
CONFIG_USB_SERIAL_SAFE_PADDED=y
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
CONFIG_USB_SERIAL_SYMBOL=m
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_WWAN=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=m
CONFIG_USB_SERIAL_XSENS_MT=m
CONFIG_USB_SERIAL_WISHBONE=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_SERIAL_QT2=m
CONFIG_USB_SERIAL_UPD78F0730=m
# CONFIG_USB_SERIAL_XR is not set
CONFIG_USB_SERIAL_DEBUG=m

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
CONFIG_USB_IDMOUSE=m
CONFIG_USB_APPLEDISPLAY=m
# CONFIG_APPLE_MFI_FASTCHARGE is not set
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
# CONFIG_USB_TEST is not set
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=m
# CONFIG_USB_HUB_USB251XB is not set
CONFIG_USB_HSIC_USB3503=y
CONFIG_USB_HSIC_USB4604=y
# CONFIG_USB_LINK_LAYER_TEST is not set
CONFIG_USB_CHAOSKEY=m
# CONFIG_USB_ONBOARD_HUB is not set
CONFIG_USB_ATM=m
# CONFIG_USB_SPEEDTOUCH is not set
CONFIG_USB_CXACRU=m
CONFIG_USB_UEAGLEATM=m
CONFIG_USB_XUSBATM=m

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_ISP1301=y
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set

#
# USB Peripheral Controller
#
# CONFIG_USB_GR_UDC is not set
# CONFIG_USB_R8A66597 is not set
# CONFIG_USB_PXA27X is not set
# CONFIG_USB_MV_UDC is not set
# CONFIG_USB_MV_U3D is not set
# CONFIG_USB_SNP_UDC_PLAT is not set
# CONFIG_USB_M66592 is not set
# CONFIG_USB_BDC_UDC is not set
# CONFIG_USB_AMD5536UDC is not set
# CONFIG_USB_NET2272 is not set
# CONFIG_USB_NET2280 is not set
# CONFIG_USB_GOKU is not set
# CONFIG_USB_EG20T is not set
# CONFIG_USB_GADGET_XILINX is not set
# CONFIG_USB_MAX3420_UDC is not set
# CONFIG_USB_CDNS2_UDC is not set
# CONFIG_USB_DUMMY_HCD is not set
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=m
CONFIG_USB_F_ACM=m
CONFIG_USB_U_SERIAL=m
CONFIG_USB_U_ETHER=m
CONFIG_USB_U_AUDIO=m
CONFIG_USB_F_SERIAL=m
CONFIG_USB_F_OBEX=m
CONFIG_USB_F_NCM=m
CONFIG_USB_F_ECM=m
CONFIG_USB_F_EEM=m
CONFIG_USB_F_SUBSET=m
CONFIG_USB_F_RNDIS=m
CONFIG_USB_F_MASS_STORAGE=m
CONFIG_USB_F_FS=m
CONFIG_USB_F_UAC1=m
CONFIG_USB_F_UAC1_LEGACY=m
CONFIG_USB_F_UAC2=m
CONFIG_USB_F_UVC=m
CONFIG_USB_F_MIDI=m
CONFIG_USB_F_HID=m
CONFIG_USB_F_PRINTER=m
CONFIG_USB_F_TCM=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
# CONFIG_USB_CONFIGFS_F_LB_SS is not set
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y
CONFIG_USB_CONFIGFS_F_TCM=y

#
# USB Gadget precomposed configurations
#
# CONFIG_USB_ZERO is not set
CONFIG_USB_AUDIO=m
CONFIG_GADGET_UAC1=y
# CONFIG_GADGET_UAC1_LEGACY is not set
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
CONFIG_USB_FUNCTIONFS_ETH=y
CONFIG_USB_FUNCTIONFS_RNDIS=y
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_GADGET_TARGET=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_G_HID=m
# CONFIG_USB_G_DBGP is not set
CONFIG_USB_G_WEBCAM=m
# CONFIG_USB_RAW_GADGET is not set
# end of USB Gadget precomposed configurations

CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
# CONFIG_TYPEC_RT1711H is not set
# CONFIG_TYPEC_TCPCI_MAXIM is not set
CONFIG_TYPEC_FUSB302=y
# CONFIG_TYPEC_UCSI is not set
CONFIG_TYPEC_TPS6598X=m
# CONFIG_TYPEC_ANX7411 is not set
# CONFIG_TYPEC_RT1719 is not set
CONFIG_TYPEC_HD3SS3220=m
# CONFIG_TYPEC_STUSB160X is not set
# CONFIG_TYPEC_WUSB3801 is not set

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
# CONFIG_TYPEC_MUX_FSA4480 is not set
# CONFIG_TYPEC_MUX_GPIO_SBU is not set
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
# CONFIG_TYPEC_MUX_NB7VPQ904M is not set
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
# CONFIG_TYPEC_DP_ALTMODE is not set
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
CONFIG_PWRSEQ_SD8787=m
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_SDIO_UART=m
# CONFIG_MMC_TEST is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_ARMMMCI=y
# CONFIG_MMC_STM32_SDMMC is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_PCI=y
CONFIG_MMC_RICOH_MMC=y
CONFIG_MMC_SDHCI_ACPI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
CONFIG_MMC_SDHCI_OF_AT91=y
# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set
CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MMC_SDHCI_F_SDH30=y
# CONFIG_MMC_SDHCI_MILBEAUT is not set
CONFIG_MMC_TIFM_SD=y
CONFIG_MMC_SPI=y
CONFIG_MMC_CB710=y
CONFIG_MMC_VIA_SDMMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
# CONFIG_MMC_DW_BLUEFIELD is not set
CONFIG_MMC_DW_EXYNOS=y
# CONFIG_MMC_DW_HI3798CV200 is not set
CONFIG_MMC_DW_K3=y
CONFIG_MMC_DW_PCI=y
CONFIG_MMC_VUB300=m
CONFIG_MMC_USHC=m
CONFIG_MMC_USDHI6ROL0=y
CONFIG_MMC_SUNXI=y
CONFIG_MMC_CQHCI=y
# CONFIG_MMC_HSQ is not set
CONFIG_MMC_TOSHIBA_PCI=y
CONFIG_MMC_MTK=y
CONFIG_MMC_SDHCI_XENON=y
# CONFIG_MMC_SDHCI_OMAP is not set
CONFIG_MMC_SDHCI_AM654=y
CONFIG_SCSI_UFSHCD=y
# CONFIG_SCSI_UFS_BSG is not set
# CONFIG_SCSI_UFS_HPB is not set
# CONFIG_SCSI_UFS_HWMON is not set
CONFIG_SCSI_UFSHCD_PCI=m
# CONFIG_SCSI_UFS_DWC_TC_PCI is not set
CONFIG_SCSI_UFSHCD_PLATFORM=y
# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set
# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set
CONFIG_MEMSTICK=m
# CONFIG_MEMSTICK_DEBUG is not set

#
# MemoryStick drivers
#
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
CONFIG_MSPRO_BLOCK=m
# CONFIG_MS_BLOCK is not set

#
# MemoryStick Host Controller Drivers
#
CONFIG_MEMSTICK_TIFM_MS=m
CONFIG_MEMSTICK_JMICRON_38X=m
CONFIG_MEMSTICK_R592=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=m
# CONFIG_LEDS_CLASS_MULTICOLOR is not set
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set

#
# LED drivers
#
# CONFIG_LEDS_AN30259A is not set
# CONFIG_LEDS_AW200XX is not set
# CONFIG_LEDS_AW2013 is not set
# CONFIG_LEDS_BCM6328 is not set
# CONFIG_LEDS_BCM6358 is not set
# CONFIG_LEDS_CR0014114 is not set
# CONFIG_LEDS_EL15203000 is not set
CONFIG_LEDS_LM3530=m
# CONFIG_LEDS_LM3532 is not set
# CONFIG_LEDS_LM3642 is not set
CONFIG_LEDS_LM3692X=m
# CONFIG_LEDS_PCA9532 is not set
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=m
# CONFIG_LEDS_LP3952 is not set
# CONFIG_LEDS_LP50XX is not set
# CONFIG_LEDS_LP55XX_COMMON is not set
# CONFIG_LEDS_LP8860 is not set
CONFIG_LEDS_PCA955X=m
# CONFIG_LEDS_PCA955X_GPIO is not set
CONFIG_LEDS_PCA963X=m
# CONFIG_LEDS_DAC124S085 is not set
CONFIG_LEDS_PWM=m
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2606MVV is not set
# CONFIG_LEDS_BD2802 is not set
CONFIG_LEDS_LT3593=m
# CONFIG_LEDS_TCA6507 is not set
# CONFIG_LEDS_TLC591XX is not set
# CONFIG_LEDS_LM355x is not set
# CONFIG_LEDS_IS31FL319X is not set
# CONFIG_LEDS_IS31FL32XX is not set

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=m
CONFIG_LEDS_SYSCON=y
# CONFIG_LEDS_MLXREG is not set
CONFIG_LEDS_USER=m
# CONFIG_LEDS_SPI_BYTE is not set
# CONFIG_LEDS_LM3697 is not set

#
# Flash and Torch LED drivers
#
# CONFIG_LEDS_AAT1290 is not set
# CONFIG_LEDS_AS3645A is not set
# CONFIG_LEDS_KTD2692 is not set
# CONFIG_LEDS_LM3601X is not set
# CONFIG_LEDS_RT4505 is not set
# CONFIG_LEDS_RT8515 is not set
# CONFIG_LEDS_SGM3140 is not set

#
# RGB LED drivers
#

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_ACTIVITY=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=y
CONFIG_LEDS_TRIGGER_PATTERN=m
CONFIG_LEDS_TRIGGER_AUDIO=m
# CONFIG_LEDS_TRIGGER_TTY is not set

#
# Simple LED drivers
#
CONFIG_ACCESSIBILITY=y
CONFIG_A11Y_BRAILLE_CONSOLE=y

#
# Speakup console speech
#
# CONFIG_SPEAKUP is not set
# end of Speakup console speech

# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
# CONFIG_EDAC_DEBUG is not set
# CONFIG_EDAC_THUNDERX is not set
CONFIG_EDAC_XGENE=m
# CONFIG_EDAC_DMC520 is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_SYSTOHC is not set
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_ABB5ZES3 is not set
# CONFIG_RTC_DRV_ABEOZ9 is not set
CONFIG_RTC_DRV_ABX80X=m
CONFIG_RTC_DRV_DS1307=m
# CONFIG_RTC_DRV_DS1307_CENTURY is not set
CONFIG_RTC_DRV_DS1374=m
CONFIG_RTC_DRV_DS1374_WDT=y
CONFIG_RTC_DRV_DS1672=m
CONFIG_RTC_DRV_HYM8563=m
CONFIG_RTC_DRV_MAX6900=m
# CONFIG_RTC_DRV_MAX77686 is not set
# CONFIG_RTC_DRV_NCT3018Y is not set
CONFIG_RTC_DRV_RS5C372=m
CONFIG_RTC_DRV_ISL1208=m
CONFIG_RTC_DRV_ISL12022=m
# CONFIG_RTC_DRV_ISL12026 is not set
CONFIG_RTC_DRV_X1205=m
CONFIG_RTC_DRV_PCF8523=m
CONFIG_RTC_DRV_PCF85063=m
CONFIG_RTC_DRV_PCF85363=m
CONFIG_RTC_DRV_PCF8563=m
CONFIG_RTC_DRV_PCF8583=m
CONFIG_RTC_DRV_M41T80=m
CONFIG_RTC_DRV_M41T80_WDT=y
CONFIG_RTC_DRV_BQ32K=m
# CONFIG_RTC_DRV_S35390A is not set
CONFIG_RTC_DRV_FM3130=m
# CONFIG_RTC_DRV_RX8010 is not set
CONFIG_RTC_DRV_RX8581=m
CONFIG_RTC_DRV_RX8025=m
CONFIG_RTC_DRV_EM3027=m
# CONFIG_RTC_DRV_RV3028 is not set
# CONFIG_RTC_DRV_RV3032 is not set
CONFIG_RTC_DRV_RV8803=m
# CONFIG_RTC_DRV_S5M is not set
# CONFIG_RTC_DRV_SD3078 is not set

#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_MCP795 is not set
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
CONFIG_RTC_DRV_DS3232=m
CONFIG_RTC_DRV_DS3232_HWMON=y
CONFIG_RTC_DRV_PCF2127=m
CONFIG_RTC_DRV_RV3029C2=m
CONFIG_RTC_DRV_RV3029_HWMON=y
# CONFIG_RTC_DRV_RX6110 is not set

#
# Platform RTC drivers
#
CONFIG_RTC_DRV_DS1286=m
CONFIG_RTC_DRV_DS1511=m
CONFIG_RTC_DRV_DS1553=m
CONFIG_RTC_DRV_DS1685_FAMILY=m
CONFIG_RTC_DRV_DS1685=y
# CONFIG_RTC_DRV_DS1689 is not set
# CONFIG_RTC_DRV_DS17285 is not set
# CONFIG_RTC_DRV_DS17485 is not set
# CONFIG_RTC_DRV_DS17885 is not set
CONFIG_RTC_DRV_DS1742=m
CONFIG_RTC_DRV_DS2404=m
CONFIG_RTC_DRV_EFI=y
CONFIG_RTC_DRV_STK17TA8=m
# CONFIG_RTC_DRV_M48T86 is not set
CONFIG_RTC_DRV_M48T35=m
CONFIG_RTC_DRV_M48T59=m
CONFIG_RTC_DRV_MSM6242=m
CONFIG_RTC_DRV_BQ4802=m
CONFIG_RTC_DRV_RP5C01=m
# CONFIG_RTC_DRV_ZYNQMP is not set
CONFIG_RTC_DRV_CROS_EC=y

#
# on-CPU RTC drivers
#
# CONFIG_RTC_DRV_PL030 is not set
CONFIG_RTC_DRV_PL031=y
CONFIG_RTC_DRV_SUN6I=y
# CONFIG_RTC_DRV_CADENCE is not set
# CONFIG_RTC_DRV_FTRTC010 is not set
# CONFIG_RTC_DRV_R7301 is not set

#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_GOLDFISH is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
# CONFIG_AMBA_PL08X is not set
# CONFIG_BCM_SBA_RAID is not set
CONFIG_DMA_SUN6I=y
# CONFIG_DW_AXI_DMAC is not set
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_INTEL_IDMA64 is not set
CONFIG_MV_XOR_V2=y
CONFIG_PL330_DMA=y
# CONFIG_PLX_DMA is not set
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_XDMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
# CONFIG_XILINX_ZYNQMP_DPDMA is not set
CONFIG_QCOM_HIDMA_MGMT=y
CONFIG_QCOM_HIDMA=y
CONFIG_DW_DMAC_CORE=m
CONFIG_DW_DMAC=m
CONFIG_DW_DMAC_PCI=m
# CONFIG_DW_EDMA is not set
# CONFIG_SF_PDMA is not set

#
# DMA Clients
#
CONFIG_ASYNC_TX_DMA=y
# CONFIG_DMATEST is not set
CONFIG_DMA_ENGINE_RAID=y

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
# CONFIG_SW_SYNC is not set
# CONFIG_UDMABUF is not set
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_DEBUG is not set
# CONFIG_DMABUF_SELFTESTS is not set
# CONFIG_DMABUF_HEAPS is not set
# CONFIG_DMABUF_SYSFS_STATS is not set
# end of DMABUF options

CONFIG_AUXDISPLAY=y
# CONFIG_HD44780 is not set
# CONFIG_IMG_ASCII_LCD is not set
# CONFIG_HT16K33 is not set
# CONFIG_LCD2S is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_UIO=m
CONFIG_UIO_CIF=m
# CONFIG_UIO_PDRV_GENIRQ is not set
# CONFIG_UIO_DMEM_GENIRQ is not set
CONFIG_UIO_AEC=m
CONFIG_UIO_SERCOS3=m
CONFIG_UIO_PCI_GENERIC=m
# CONFIG_UIO_NETX is not set
# CONFIG_UIO_PRUSS is not set
# CONFIG_UIO_MF624 is not set
CONFIG_VFIO=m
CONFIG_VFIO_CONTAINER=y
CONFIG_VFIO_IOMMU_TYPE1=m
# CONFIG_VFIO_NOIOMMU is not set
CONFIG_VFIO_VIRQFD=y

#
# VFIO support for PCI devices
#
CONFIG_VFIO_PCI_CORE=m
CONFIG_VFIO_PCI_MMAP=y
CONFIG_VFIO_PCI_INTX=y
CONFIG_VFIO_PCI=m
# CONFIG_MLX5_VFIO_PCI is not set
# end of VFIO support for PCI devices

#
# VFIO support for platform devices
#
CONFIG_VFIO_PLATFORM_BASE=m
CONFIG_VFIO_PLATFORM=m
CONFIG_VFIO_AMBA=m

#
# VFIO platform reset drivers
#
CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET=m
CONFIG_VFIO_PLATFORM_AMDXGBE_RESET=m
# end of VFIO platform reset drivers
# end of VFIO support for platform devices

# CONFIG_VIRT_DRIVERS is not set
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_PCI_LIB=y
CONFIG_VIRTIO_PCI_LIB_LEGACY=y
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_PCI_LEGACY=y
# CONFIG_VIRTIO_PMEM is not set
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
# CONFIG_VDPA is not set
CONFIG_VHOST_IOTLB=m
CONFIG_VHOST_TASK=y
CONFIG_VHOST=m
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_SCSI=m
CONFIG_VHOST_VSOCK=m
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set

#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
# CONFIG_COMEDI is not set
CONFIG_STAGING=y
CONFIG_PRISM2_USB=m
CONFIG_RTL8192U=m
CONFIG_RTLLIB=m
CONFIG_RTLLIB_CRYPTO_CCMP=m
CONFIG_RTLLIB_CRYPTO_TKIP=m
CONFIG_RTLLIB_CRYPTO_WEP=m
CONFIG_RTL8192E=m
# CONFIG_RTL8723BS is not set
CONFIG_R8712U=m
# CONFIG_RTS5208 is not set
# CONFIG_VT6655 is not set
# CONFIG_VT6656 is not set

#
# IIO staging drivers
#

#
# Accelerometers
#
CONFIG_ADIS16203=m
CONFIG_ADIS16240=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD7816=m
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
CONFIG_ADT7316=m
CONFIG_ADT7316_SPI=m
CONFIG_ADT7316_I2C=m
# end of Analog digital bi-direction converters

#
# Direct Digital Synthesis
#
CONFIG_AD9832=m
CONFIG_AD9834=m
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
CONFIG_AD5933=m
# end of Network Analyzer, Impedance Converters

#
# Resolver to digital converters
#
CONFIG_AD2S1210=m
# end of Resolver to digital converters
# end of IIO staging drivers

# CONFIG_FB_SM750 is not set
CONFIG_STAGING_MEDIA=y
CONFIG_DVB_AV7110_IR=y
CONFIG_DVB_AV7110=m
CONFIG_DVB_AV7110_OSD=y
CONFIG_DVB_BUDGET_PATCH=m
CONFIG_DVB_SP8870=m
# CONFIG_VIDEO_MAX96712 is not set
CONFIG_VIDEO_SUNXI=y
CONFIG_VIDEO_SUNXI_CEDRUS=m
# CONFIG_VIDEO_SUN6I_ISP is not set
# CONFIG_STAGING_MEDIA_DEPRECATED is not set
# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
CONFIG_FB_TFT=m
CONFIG_FB_TFT_AGM1264K_FL=m
CONFIG_FB_TFT_BD663474=m
CONFIG_FB_TFT_HX8340BN=m
CONFIG_FB_TFT_HX8347D=m
CONFIG_FB_TFT_HX8353D=m
CONFIG_FB_TFT_HX8357D=m
CONFIG_FB_TFT_ILI9163=m
CONFIG_FB_TFT_ILI9320=m
CONFIG_FB_TFT_ILI9325=m
CONFIG_FB_TFT_ILI9340=m
CONFIG_FB_TFT_ILI9341=m
CONFIG_FB_TFT_ILI9481=m
CONFIG_FB_TFT_ILI9486=m
CONFIG_FB_TFT_PCD8544=m
CONFIG_FB_TFT_RA8875=m
CONFIG_FB_TFT_S6D02A1=m
CONFIG_FB_TFT_S6D1121=m
CONFIG_FB_TFT_SEPS525=m
CONFIG_FB_TFT_SH1106=m
CONFIG_FB_TFT_SSD1289=m
CONFIG_FB_TFT_SSD1305=m
CONFIG_FB_TFT_SSD1306=m
CONFIG_FB_TFT_SSD1331=m
CONFIG_FB_TFT_SSD1351=m
CONFIG_FB_TFT_ST7735R=m
CONFIG_FB_TFT_ST7789V=m
CONFIG_FB_TFT_TINYLCD=m
CONFIG_FB_TFT_TLS8204=m
CONFIG_FB_TFT_UC1611=m
CONFIG_FB_TFT_UC1701=m
CONFIG_FB_TFT_UPD161704=m
# CONFIG_KS7010 is not set
# CONFIG_PI433 is not set
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_QLGE is not set
# CONFIG_VME_BUS is not set
# CONFIG_GOLDFISH is not set
CONFIG_CHROME_PLATFORMS=y
# CONFIG_CHROMEOS_ACPI is not set
CONFIG_CHROMEOS_TBMC=m
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_RPMSG=m
CONFIG_CROS_EC_SPI=y
# CONFIG_CROS_EC_UART is not set
CONFIG_CROS_EC_PROTO=y
CONFIG_CROS_KBD_LED_BACKLIGHT=y
CONFIG_CROS_EC_CHARDEV=y
CONFIG_CROS_EC_LIGHTBAR=m
CONFIG_CROS_EC_VBC=m
CONFIG_CROS_EC_DEBUGFS=m
CONFIG_CROS_EC_SENSORHUB=y
CONFIG_CROS_EC_SYSFS=m
CONFIG_CROS_EC_TYPEC=y
# CONFIG_CROS_HPS_I2C is not set
CONFIG_CROS_USBPD_LOGGER=m
CONFIG_CROS_USBPD_NOTIFY=y
# CONFIG_CHROMEOS_PRIVACY_SCREEN is not set
# CONFIG_CROS_TYPEC_SWITCH is not set
# CONFIG_MELLANOX_PLATFORM is not set
# CONFIG_SURFACE_PLATFORMS is not set
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Clock driver for ARM Reference designs
#
# CONFIG_CLK_ICST is not set
CONFIG_CLK_SP810=y
CONFIG_CLK_VEXPRESS_OSC=y
# end of Clock driver for ARM Reference designs

# CONFIG_LMK04832 is not set
# CONFIG_COMMON_CLK_MAX77686 is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
# CONFIG_COMMON_CLK_S2MPS11 is not set
# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
CONFIG_COMMON_CLK_XGENE=y
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_RS9_PCIE is not set
# CONFIG_COMMON_CLK_SI521XX is not set
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_VC7 is not set
CONFIG_COMMON_CLK_BD718XX=m
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
CONFIG_SUNXI_CCU=y
CONFIG_SUN50I_A64_CCU=y
CONFIG_SUN50I_A100_CCU=y
CONFIG_SUN50I_A100_R_CCU=y
CONFIG_SUN50I_H6_CCU=y
CONFIG_SUN50I_H616_CCU=y
CONFIG_SUN50I_H6_R_CCU=y
# CONFIG_SUN6I_RTC_CCU is not set
CONFIG_SUN8I_H3_CCU=y
CONFIG_SUN8I_DE2_CCU=y
CONFIG_SUN8I_R_CCU=y
# CONFIG_XILINX_VCU is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
CONFIG_HWSPINLOCK=y
# CONFIG_HWSPINLOCK_SUN6I is not set

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_ACPI=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_SUN4I_TIMER=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
# end of Clock Source drivers

CONFIG_MAILBOX=y
CONFIG_ARM_MHU=y
# CONFIG_ARM_MHU_V2 is not set
CONFIG_PLATFORM_MHU=y
# CONFIG_PL320_MBOX is not set
CONFIG_PCC=y
# CONFIG_ALTERA_MBOX is not set
# CONFIG_MAILBOX_TEST is not set
CONFIG_SUN6I_MSGBOX=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_DART is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
# CONFIG_IOMMUFD is not set
# CONFIG_SUN50I_IOMMU is not set
CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
CONFIG_ARM_SMMU_V3=y
# CONFIG_ARM_SMMU_V3_SVA is not set
# CONFIG_VIRTIO_IOMMU is not set

#
# Remoteproc drivers
#
CONFIG_REMOTEPROC=y
# CONFIG_REMOTEPROC_CDEV is not set
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=y
CONFIG_RPMSG_CHAR=y
# CONFIG_RPMSG_CTRL is not set
# CONFIG_RPMSG_NS is not set
CONFIG_RPMSG_QCOM_GLINK=y
CONFIG_RPMSG_QCOM_GLINK_RPM=y
# CONFIG_RPMSG_VIRTIO is not set
# end of Rpmsg drivers

CONFIG_SOUNDWIRE=m

#
# SoundWire Devices
#
# CONFIG_SOUNDWIRE_AMD is not set
# CONFIG_SOUNDWIRE_INTEL is not set
CONFIG_SOUNDWIRE_QCOM=m

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
# end of Amlogic SoC drivers

#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
# CONFIG_QUICC_ENGINE is not set
# CONFIG_FSL_RCPM is not set
# end of NXP/Freescale QorIQ SoC drivers

#
# fujitsu SoC drivers
#
# CONFIG_A64FX_DIAG is not set
# end of fujitsu SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Enable LiteX SoC Builder specific drivers
#
# CONFIG_LITEX_SOC_CONTROLLER is not set
# end of Enable LiteX SoC Builder specific drivers

# CONFIG_WPCM450_SOC is not set

#
# Qualcomm SoC drivers
#
# CONFIG_QCOM_PMIC_GLINK is not set
# end of Qualcomm SoC drivers

CONFIG_SUNXI_MBUS=y
CONFIG_SUNXI_SRAM=y
# CONFIG_SUN20I_PPU is not set
# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEVFREQ_GOV_PASSIVE=y

#
# DEVFREQ Drivers
#
CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
CONFIG_EXTCON_ADC_JACK=m
# CONFIG_EXTCON_FSA9480 is not set
CONFIG_EXTCON_GPIO=y
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_PTN5150 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
CONFIG_EXTCON_USB_GPIO=y
CONFIG_EXTCON_USBC_CROS_EC=y
# CONFIG_EXTCON_USBC_TUSB320 is not set
CONFIG_MEMORY=y
# CONFIG_ARM_PL172_MPMC is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=y
CONFIG_IIO_BUFFER_DMA=m
CONFIG_IIO_BUFFER_DMAENGINE=m
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
CONFIG_IIO_TRIGGERED_EVENT=m

#
# Accelerometers
#
CONFIG_ADIS16201=m
CONFIG_ADIS16209=m
# CONFIG_ADXL313_I2C is not set
# CONFIG_ADXL313_SPI is not set
CONFIG_ADXL345=m
CONFIG_ADXL345_I2C=m
CONFIG_ADXL345_SPI=m
# CONFIG_ADXL355_I2C is not set
# CONFIG_ADXL355_SPI is not set
# CONFIG_ADXL367_SPI is not set
# CONFIG_ADXL367_I2C is not set
CONFIG_ADXL372=m
CONFIG_ADXL372_SPI=m
CONFIG_ADXL372_I2C=m
CONFIG_BMA180=m
CONFIG_BMA220=m
CONFIG_BMA400=m
CONFIG_BMA400_I2C=m
CONFIG_BMA400_SPI=m
CONFIG_BMC150_ACCEL=m
CONFIG_BMC150_ACCEL_I2C=m
CONFIG_BMC150_ACCEL_SPI=m
# CONFIG_BMI088_ACCEL is not set
CONFIG_DA280=m
CONFIG_DA311=m
CONFIG_DMARD06=m
CONFIG_DMARD09=m
CONFIG_DMARD10=m
# CONFIG_FXLS8962AF_I2C is not set
# CONFIG_FXLS8962AF_SPI is not set
CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
# CONFIG_IIO_KX022A_SPI is not set
# CONFIG_IIO_KX022A_I2C is not set
CONFIG_KXSD9=m
CONFIG_KXSD9_SPI=m
CONFIG_KXSD9_I2C=m
CONFIG_KXCJK1013=m
CONFIG_MC3230=m
CONFIG_MMA7455=m
CONFIG_MMA7455_I2C=m
CONFIG_MMA7455_SPI=m
CONFIG_MMA7660=m
CONFIG_MMA8452=m
CONFIG_MMA9551_CORE=m
CONFIG_MMA9551=m
CONFIG_MMA9553=m
# CONFIG_MSA311 is not set
CONFIG_MXC4005=m
CONFIG_MXC6255=m
CONFIG_SCA3000=m
# CONFIG_SCA3300 is not set
CONFIG_STK8312=m
CONFIG_STK8BA50=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=m
# CONFIG_AD4130 is not set
CONFIG_AD7091R5=m
CONFIG_AD7124=m
CONFIG_AD7192=m
CONFIG_AD7266=m
CONFIG_AD7280=m
CONFIG_AD7291=m
CONFIG_AD7292=m
CONFIG_AD7298=m
CONFIG_AD7476=m
CONFIG_AD7606=m
CONFIG_AD7606_IFACE_PARALLEL=m
CONFIG_AD7606_IFACE_SPI=m
CONFIG_AD7766=m
CONFIG_AD7768_1=m
CONFIG_AD7780=m
CONFIG_AD7791=m
CONFIG_AD7793=m
CONFIG_AD7887=m
CONFIG_AD7923=m
CONFIG_AD7949=m
CONFIG_AD799X=m
CONFIG_AD9467=m
CONFIG_ADI_AXI_ADC=m
CONFIG_AXP20X_ADC=m
CONFIG_AXP288_ADC=m
CONFIG_CC10001_ADC=m
CONFIG_ENVELOPE_DETECTOR=m
CONFIG_HI8435=m
CONFIG_HX711=m
CONFIG_INA2XX_ADC=m
CONFIG_LTC2471=m
CONFIG_LTC2485=m
CONFIG_LTC2496=m
CONFIG_LTC2497=m
CONFIG_MAX1027=m
CONFIG_MAX11100=m
CONFIG_MAX1118=m
# CONFIG_MAX11205 is not set
# CONFIG_MAX11410 is not set
CONFIG_MAX1241=m
CONFIG_MAX1363=m
CONFIG_MAX9611=m
CONFIG_MCP320X=m
CONFIG_MCP3422=m
CONFIG_MCP3911=m
CONFIG_NAU7802=m
CONFIG_QCOM_VADC_COMMON=y
CONFIG_QCOM_SPMI_IADC=m
CONFIG_QCOM_SPMI_VADC=y
CONFIG_QCOM_SPMI_ADC5=m
# CONFIG_RICHTEK_RTQ6056 is not set
CONFIG_SD_ADC_MODULATOR=m
CONFIG_TI_ADC081C=m
CONFIG_TI_ADC0832=m
CONFIG_TI_ADC084S021=m
CONFIG_TI_ADC12138=m
CONFIG_TI_ADC108S102=m
CONFIG_TI_ADC128S052=m
CONFIG_TI_ADC161S626=m
CONFIG_TI_ADS1015=m
# CONFIG_TI_ADS7924 is not set
# CONFIG_TI_ADS1100 is not set
CONFIG_TI_ADS7950=m
CONFIG_TI_ADS8344=m
CONFIG_TI_ADS8688=m
CONFIG_TI_ADS124S08=m
# CONFIG_TI_ADS131E08 is not set
# CONFIG_TI_LMP92064 is not set
CONFIG_TI_TLC4541=m
# CONFIG_TI_TSC2046 is not set
CONFIG_VF610_ADC=m
CONFIG_VIPERBOARD_ADC=m
# CONFIG_XILINX_XADC is not set
# end of Analog to digital converters

#
# Analog to digital and digital to analog converters
#
# CONFIG_AD74115 is not set
# CONFIG_AD74413R is not set
# end of Analog to digital and digital to analog converters

#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=m
# end of Analog Front Ends

#
# Amplifiers
#
CONFIG_AD8366=m
# CONFIG_ADA4250 is not set
CONFIG_HMC425=m
# end of Amplifiers

#
# Capacitance to digital converters
#
CONFIG_AD7150=m
CONFIG_AD7746=m
# end of Capacitance to digital converters

#
# Chemical Sensors
#
CONFIG_ATLAS_PH_SENSOR=m
CONFIG_ATLAS_EZO_SENSOR=m
CONFIG_BME680=m
CONFIG_BME680_I2C=m
CONFIG_BME680_SPI=m
CONFIG_CCS811=m
CONFIG_IAQCORE=m
CONFIG_PMS7003=m
CONFIG_SCD30_CORE=m
CONFIG_SCD30_I2C=m
CONFIG_SCD30_SERIAL=m
# CONFIG_SCD4X is not set
CONFIG_SENSIRION_SGP30=m
# CONFIG_SENSIRION_SGP40 is not set
# CONFIG_SPS30_I2C is not set
# CONFIG_SPS30_SERIAL is not set
# CONFIG_SENSEAIR_SUNRISE_CO2 is not set
CONFIG_VZ89X=m
# end of Chemical Sensors

CONFIG_IIO_CROS_EC_SENSORS_CORE=m
CONFIG_IIO_CROS_EC_SENSORS=m
CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m

#
# Hid Sensor IIO Common
#
# end of Hid Sensor IIO Common

CONFIG_IIO_MS_SENSORS_I2C=m

#
# IIO SCMI Sensors
#
# CONFIG_IIO_SCMI is not set
# end of IIO SCMI Sensors

#
# SSP Sensor Common
#
# CONFIG_IIO_SSP_SENSORHUB is not set
# end of SSP Sensor Common

CONFIG_IIO_ST_SENSORS_I2C=m
CONFIG_IIO_ST_SENSORS_SPI=m
CONFIG_IIO_ST_SENSORS_CORE=m

#
# Digital to analog converters
#
# CONFIG_AD3552R is not set
CONFIG_AD5064=m
CONFIG_AD5360=m
CONFIG_AD5380=m
CONFIG_AD5421=m
CONFIG_AD5446=m
CONFIG_AD5449=m
CONFIG_AD5592R_BASE=m
CONFIG_AD5592R=m
CONFIG_AD5593R=m
CONFIG_AD5504=m
CONFIG_AD5624R_SPI=m
# CONFIG_LTC2688 is not set
CONFIG_AD5686=m
CONFIG_AD5686_SPI=m
CONFIG_AD5696_I2C=m
CONFIG_AD5755=m
CONFIG_AD5758=m
CONFIG_AD5761=m
CONFIG_AD5764=m
# CONFIG_AD5766 is not set
CONFIG_AD5770R=m
CONFIG_AD5791=m
# CONFIG_AD7293 is not set
CONFIG_AD7303=m
CONFIG_AD8801=m
CONFIG_DPOT_DAC=m
CONFIG_DS4424=m
CONFIG_LTC1660=m
CONFIG_LTC2632=m
CONFIG_M62332=m
CONFIG_MAX517=m
# CONFIG_MAX5522 is not set
CONFIG_MAX5821=m
CONFIG_MCP4725=m
CONFIG_MCP4922=m
CONFIG_TI_DAC082S085=m
CONFIG_TI_DAC5571=m
CONFIG_TI_DAC7311=m
CONFIG_TI_DAC7612=m
CONFIG_VF610_DAC=m
# end of Digital to analog converters

#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver

#
# Filters
#
# CONFIG_ADMV8818 is not set
# end of Filters

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
CONFIG_AD9523=m
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4350=m
CONFIG_ADF4371=m
# CONFIG_ADF4377 is not set
# CONFIG_ADMV1013 is not set
# CONFIG_ADMV1014 is not set
# CONFIG_ADMV4420 is not set
# CONFIG_ADRF6780 is not set
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=m
CONFIG_ADIS16130=m
CONFIG_ADIS16136=m
CONFIG_ADIS16260=m
CONFIG_ADXRS290=m
CONFIG_ADXRS450=m
CONFIG_BMG160=m
CONFIG_BMG160_I2C=m
CONFIG_BMG160_SPI=m
CONFIG_FXAS21002C=m
CONFIG_FXAS21002C_I2C=m
CONFIG_FXAS21002C_SPI=m
CONFIG_MPU3050=m
CONFIG_MPU3050_I2C=m
CONFIG_IIO_ST_GYRO_3AXIS=m
CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
CONFIG_ITG3200=m
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
CONFIG_AFE4403=m
CONFIG_AFE4404=m
CONFIG_MAX30100=m
CONFIG_MAX30102=m
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
CONFIG_AM2315=m
CONFIG_DHT11=m
CONFIG_HDC100X=m
CONFIG_HDC2010=m
CONFIG_HTS221=m
CONFIG_HTS221_I2C=m
CONFIG_HTS221_SPI=m
CONFIG_HTU21=m
CONFIG_SI7005=m
CONFIG_SI7020=m
# end of Humidity sensors

#
# Inertial measurement units
#
CONFIG_ADIS16400=m
CONFIG_ADIS16460=m
CONFIG_ADIS16475=m
CONFIG_ADIS16480=m
CONFIG_BMI160=m
CONFIG_BMI160_I2C=m
CONFIG_BMI160_SPI=m
# CONFIG_BOSCH_BNO055_SERIAL is not set
# CONFIG_BOSCH_BNO055_I2C is not set
CONFIG_FXOS8700=m
CONFIG_FXOS8700_I2C=m
CONFIG_FXOS8700_SPI=m
CONFIG_KMX61=m
CONFIG_INV_ICM42600=m
CONFIG_INV_ICM42600_I2C=m
CONFIG_INV_ICM42600_SPI=m
CONFIG_INV_MPU6050_IIO=m
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_SPI=m
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_LSM6DSX_I2C=m
CONFIG_IIO_ST_LSM6DSX_SPI=m
# CONFIG_IIO_ST_LSM9DS0 is not set
# end of Inertial measurement units

CONFIG_IIO_ADIS_LIB=m
CONFIG_IIO_ADIS_LIB_BUFFER=y

#
# Light sensors
#
CONFIG_ACPI_ALS=m
CONFIG_ADJD_S311=m
CONFIG_ADUX1020=m
CONFIG_AL3010=m
CONFIG_AL3320A=m
CONFIG_APDS9300=m
CONFIG_APDS9960=m
CONFIG_AS73211=m
CONFIG_BH1750=m
CONFIG_BH1780=m
CONFIG_CM32181=m
CONFIG_CM3232=m
CONFIG_CM3323=m
CONFIG_CM3605=m
CONFIG_CM36651=m
CONFIG_IIO_CROS_EC_LIGHT_PROX=m
CONFIG_GP2AP002=m
CONFIG_GP2AP020A00F=m
CONFIG_SENSORS_ISL29018=m
CONFIG_SENSORS_ISL29028=m
CONFIG_ISL29125=m
CONFIG_JSA1212=m
# CONFIG_ROHM_BU27008 is not set
# CONFIG_ROHM_BU27034 is not set
CONFIG_RPR0521=m
CONFIG_LTR501=m
# CONFIG_LTRF216A is not set
CONFIG_LV0104CS=m
CONFIG_MAX44000=m
CONFIG_MAX44009=m
CONFIG_NOA1305=m
CONFIG_OPT3001=m
# CONFIG_OPT4001 is not set
CONFIG_PA12203001=m
CONFIG_SI1133=m
CONFIG_SI1145=m
CONFIG_STK3310=m
CONFIG_ST_UVIS25=m
CONFIG_ST_UVIS25_I2C=m
CONFIG_ST_UVIS25_SPI=m
CONFIG_TCS3414=m
CONFIG_TCS3472=m
CONFIG_SENSORS_TSL2563=m
CONFIG_TSL2583=m
# CONFIG_TSL2591 is not set
CONFIG_TSL2772=m
CONFIG_TSL4531=m
CONFIG_US5182D=m
CONFIG_VCNL4000=m
CONFIG_VCNL4035=m
CONFIG_VEML6030=m
CONFIG_VEML6070=m
CONFIG_VL6180=m
CONFIG_ZOPT2201=m
# end of Light sensors

#
# Magnetometer sensors
#
CONFIG_AK8974=m
CONFIG_AK8975=m
CONFIG_AK09911=m
CONFIG_BMC150_MAGN=m
CONFIG_BMC150_MAGN_I2C=m
CONFIG_BMC150_MAGN_SPI=m
CONFIG_MAG3110=m
CONFIG_MMC35240=m
CONFIG_IIO_ST_MAGN_3AXIS=m
CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
CONFIG_SENSORS_HMC5843=m
CONFIG_SENSORS_HMC5843_I2C=m
CONFIG_SENSORS_HMC5843_SPI=m
CONFIG_SENSORS_RM3100=m
CONFIG_SENSORS_RM3100_I2C=m
CONFIG_SENSORS_RM3100_SPI=m
# CONFIG_TI_TMAG5273 is not set
# CONFIG_YAMAHA_YAS530 is not set
# end of Magnetometer sensors

#
# Multiplexers
#
CONFIG_IIO_MUX=y
# end of Multiplexers

#
# Inclinometer sensors
#
# end of Inclinometer sensors

#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=m
CONFIG_IIO_INTERRUPT_TRIGGER=m
CONFIG_IIO_TIGHTLOOP_TRIGGER=m
CONFIG_IIO_SYSFS_TRIGGER=m
# end of Triggers - standalone

#
# Linear and angular position sensors
#
# end of Linear and angular position sensors

#
# Digital potentiometers
#
# CONFIG_AD5110 is not set
CONFIG_AD5272=m
CONFIG_DS1803=m
CONFIG_MAX5432=m
CONFIG_MAX5481=m
CONFIG_MAX5487=m
CONFIG_MCP4018=m
CONFIG_MCP4131=m
CONFIG_MCP4531=m
CONFIG_MCP41010=m
CONFIG_TPL0102=m
# CONFIG_X9250 is not set
# end of Digital potentiometers

#
# Digital potentiostats
#
CONFIG_LMP91000=m
# end of Digital potentiostats

#
# Pressure sensors
#
CONFIG_ABP060MG=m
CONFIG_BMP280=m
CONFIG_BMP280_I2C=m
CONFIG_BMP280_SPI=m
CONFIG_IIO_CROS_EC_BARO=m
CONFIG_DLHL60D=m
CONFIG_DPS310=m
CONFIG_HP03=m
CONFIG_ICP10100=m
CONFIG_MPL115=m
CONFIG_MPL115_I2C=m
CONFIG_MPL115_SPI=m
CONFIG_MPL3115=m
# CONFIG_MPRLS0025PA is not set
CONFIG_MS5611=m
CONFIG_MS5611_I2C=m
CONFIG_MS5611_SPI=m
CONFIG_MS5637=m
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_PRESS_I2C=m
CONFIG_IIO_ST_PRESS_SPI=m
CONFIG_T5403=m
CONFIG_HP206C=m
CONFIG_ZPA2326=m
CONFIG_ZPA2326_I2C=m
CONFIG_ZPA2326_SPI=m
# end of Pressure sensors

#
# Lightning sensors
#
CONFIG_AS3935=m
# end of Lightning sensors

#
# Proximity and distance sensors
#
# CONFIG_CROS_EC_MKBP_PROXIMITY is not set
CONFIG_ISL29501=m
CONFIG_LIDAR_LITE_V2=m
CONFIG_MB1232=m
CONFIG_PING=m
CONFIG_RFD77402=m
CONFIG_SRF04=m
CONFIG_SX_COMMON=m
CONFIG_SX9310=m
# CONFIG_SX9324 is not set
# CONFIG_SX9360 is not set
CONFIG_SX9500=m
CONFIG_SRF08=m
CONFIG_VCNL3020=m
CONFIG_VL53L0X_I2C=m
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
CONFIG_AD2S90=m
CONFIG_AD2S1200=m
# end of Resolver to digital converters

#
# Temperature sensors
#
CONFIG_LTC2983=m
CONFIG_MAXIM_THERMOCOUPLE=m
CONFIG_MLX90614=m
CONFIG_MLX90632=m
CONFIG_TMP006=m
CONFIG_TMP007=m
# CONFIG_TMP117 is not set
CONFIG_TSYS01=m
CONFIG_TSYS02D=m
# CONFIG_MAX30208 is not set
CONFIG_MAX31856=m
# CONFIG_MAX31865 is not set
# end of Temperature sensors

# CONFIG_NTB is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_ATMEL_TCB is not set
# CONFIG_PWM_CLK is not set
CONFIG_PWM_CROS_EC=m
# CONFIG_PWM_DWC is not set
# CONFIG_PWM_FSL_FTM is not set
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_SUN4I=y
# CONFIG_PWM_XILINX is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_AL_FIC is not set
CONFIG_SUN6I_R_INTC=y
CONFIG_SUNXI_NMI_INTC=y
# CONFIG_XILINX_INTC is not set
CONFIG_PARTITION_PERCPU=y
# end of IRQ chip support

# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_SCMI=y
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SUNXI=y
# CONFIG_RESET_TI_SYSCON is not set
# CONFIG_RESET_TI_TPS380X is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_PHY_CAN_TRANSCEIVER is not set
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_SUN6I_MIPI_DPHY=m
# CONFIG_PHY_SUN9I_USB is not set
CONFIG_PHY_SUN50I_USB3=y

#
# PHY drivers for Broadcom platforms
#
# CONFIG_BCM_KONA_USB2_PHY is not set
# end of PHY drivers for Broadcom platforms

# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_DPHY_RX is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_LAN966X_SERDES is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
CONFIG_PHY_QCOM_USB_HS=y
CONFIG_PHY_QCOM_USB_HSIC=y
# CONFIG_PHY_SAMSUNG_USB2 is not set
# CONFIG_PHY_TUSB1210 is not set
# end of PHY Subsystem

CONFIG_POWERCAP=y
# CONFIG_IDLE_INJECT is not set
# CONFIG_ARM_SCMI_POWERCAP is not set
# CONFIG_DTPM is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=y
CONFIG_ARM_CCI400_PMU=y
CONFIG_ARM_CCI5xx_PMU=y
CONFIG_ARM_CCN=y
# CONFIG_ARM_CMN is not set
CONFIG_ARM_PMU=y
CONFIG_ARM_PMU_ACPI=y
# CONFIG_ARM_SMMU_V3_PMU is not set
CONFIG_ARM_PMUV3=y
# CONFIG_ARM_DSU_PMU is not set
# CONFIG_ARM_SPE_PMU is not set
# CONFIG_ARM_DMC620_PMU is not set
# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set
CONFIG_HISI_PMU=y
# CONFIG_HISI_PCIE_PMU is not set
# CONFIG_HNS3_PMU is not set
# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set
# end of Performance monitor support

CONFIG_RAS=y
# CONFIG_USB4 is not set

#
# Android
#
# CONFIG_ANDROID_BINDER_IPC is not set
# end of Android

CONFIG_LIBNVDIMM=y
CONFIG_BLK_DEV_PMEM=m
CONFIG_ND_CLAIM=y
CONFIG_ND_BTT=m
CONFIG_BTT=y
CONFIG_OF_PMEM=y
CONFIG_NVDIMM_KEYS=y
# CONFIG_NVDIMM_SECURITY_TEST is not set
CONFIG_DAX=y
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y

#
# Layout Types
#
# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set
# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set
# end of Layout Types

# CONFIG_NVMEM_RMEM is not set
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_NVMEM_SUNXI_SID=y
# CONFIG_NVMEM_U_BOOT_ENV is not set

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# CONFIG_HISI_PTT is not set
# end of HW tracing support

# CONFIG_FPGA is not set
# CONFIG_FSI is not set
# CONFIG_TEE is not set
CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
# CONFIG_MUX_ADGS1408 is not set
CONFIG_MUX_GPIO=y
# CONFIG_MUX_MMIO is not set
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
CONFIG_SLIMBUS=m
CONFIG_SLIM_QCOM_CTRL=m
CONFIG_INTERCONNECT=y
# CONFIG_COUNTER is not set
# CONFIG_MOST is not set
# CONFIG_PECI is not set
# CONFIG_HTE is not set
# CONFIG_CDX_BUS is not set
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_IOMAP=y
CONFIG_LEGACY_DIRECT_IO=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=m
# CONFIG_REISERFS_CHECK is not set
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
# CONFIG_JFS_DEBUG is not set
# CONFIG_JFS_STATISTICS is not set
CONFIG_XFS_FS=y
CONFIG_XFS_SUPPORT_V4=y
# CONFIG_XFS_SUPPORT_ASCII_CI is not set
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
# CONFIG_XFS_RT is not set
# CONFIG_XFS_ONLINE_SCRUB is not set
# CONFIG_XFS_WARN is not set
# CONFIG_XFS_DEBUG is not set
CONFIG_GFS2_FS=m
CONFIG_GFS2_FS_LOCKING_DLM=y
CONFIG_OCFS2_FS=m
CONFIG_OCFS2_FS_O2CB=m
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
# CONFIG_OCFS2_FS_STATS is not set
# CONFIG_OCFS2_DEBUG_MASKLOG is not set
# CONFIG_OCFS2_DEBUG_FS is not set
CONFIG_BTRFS_FS=m
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
# CONFIG_BTRFS_FS_REF_VERIFY is not set
CONFIG_NILFS2_FS=m
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
# CONFIG_F2FS_FAULT_INJECTION is not set
# CONFIG_F2FS_FS_COMPRESSION is not set
CONFIG_F2FS_IOSTAT=y
# CONFIG_F2FS_UNFAIR_RWSEM is not set
# CONFIG_ZONEFS_FS is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=m
CONFIG_CUSE=m
# CONFIG_VIRTIO_FS is not set
CONFIG_OVERLAY_FS=m
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set

#
# Caches
#
CONFIG_NETFS_SUPPORT=m
CONFIG_NETFS_STATS=y
CONFIG_FSCACHE=m
CONFIG_FSCACHE_STATS=y
# CONFIG_FSCACHE_DEBUG is not set
CONFIG_CACHEFILES=m
# CONFIG_CACHEFILES_DEBUG is not set
# CONFIG_CACHEFILES_ERROR_INJECTION is not set
# CONFIG_CACHEFILES_ONDEMAND is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
# CONFIG_FAT_DEFAULT_UTF8 is not set
CONFIG_EXFAT_FS=m
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS3_FS is not set
# end of DOS/FAT/EXFAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_TMPFS_INODE64 is not set
CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_MEMFD_CREATE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=y
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
CONFIG_AFFS_FS=m
CONFIG_ECRYPT_FS=m
# CONFIG_ECRYPT_FS_MESSAGING is not set
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
CONFIG_BEFS_FS=m
# CONFIG_BEFS_DEBUG is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_UBIFS_FS=m
# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
CONFIG_CRAMFS=m
CONFIG_CRAMFS_BLOCKDEV=y
# CONFIG_CRAMFS_MTD is not set
CONFIG_SQUASHFS=m
CONFIG_SQUASHFS_FILE_CACHE=y
# CONFIG_SQUASHFS_FILE_DIRECT is not set
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set
CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
# CONFIG_SQUASHFS_ZSTD is not set
# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
# CONFIG_SQUASHFS_EMBEDDED is not set
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
CONFIG_MINIX_FS=m
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
CONFIG_ROMFS_FS=m
CONFIG_ROMFS_BACKED_BY_BLOCK=y
# CONFIG_ROMFS_BACKED_BY_MTD is not set
# CONFIG_ROMFS_BACKED_BY_BOTH is not set
CONFIG_ROMFS_ON_BLOCK=y
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
CONFIG_PSTORE_DEFLATE_COMPRESS=y
# CONFIG_PSTORE_LZO_COMPRESS is not set
# CONFIG_PSTORE_LZ4_COMPRESS is not set
# CONFIG_PSTORE_LZ4HC_COMPRESS is not set
# CONFIG_PSTORE_842_COMPRESS is not set
# CONFIG_PSTORE_ZSTD_COMPRESS is not set
CONFIG_PSTORE_COMPRESS=y
CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
# CONFIG_PSTORE_CONSOLE is not set
# CONFIG_PSTORE_PMSG is not set
CONFIG_PSTORE_RAM=m
# CONFIG_PSTORE_BLK is not set
CONFIG_SYSV_FS=m
CONFIG_UFS_FS=m
# CONFIG_UFS_FS_WRITE is not set
# CONFIG_UFS_DEBUG is not set
# CONFIG_EROFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
# CONFIG_NFS_V2 is not set
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_SWAP=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=y
CONFIG_PNFS_BLOCK=y
CONFIG_PNFS_FLEXFILE_LAYOUT=y
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
# CONFIG_NFS_V4_1_MIGRATION is not set
CONFIG_NFS_V4_SECURITY_LABEL=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DEBUG=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
# CONFIG_NFS_V4_2_READ_PLUS is not set
CONFIG_NFSD=m
# CONFIG_NFSD_V2 is not set
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
CONFIG_NFSD_PNFS=y
CONFIG_NFSD_BLOCKLAYOUT=y
CONFIG_NFSD_SCSILAYOUT=y
CONFIG_NFSD_FLEXFILELAYOUT=y
CONFIG_NFSD_V4_2_INTER_SSC=y
CONFIG_NFSD_V4_SECURITY_LABEL=y
CONFIG_GRACE_PERIOD=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_NFS_V4_2_SSC_HELPER=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_BACKCHANNEL=y
CONFIG_SUNRPC_SWAP=y
CONFIG_RPCSEC_GSS_KRB5=m
# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_DES is not set
# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1 is not set
# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA is not set
# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 is not set
CONFIG_SUNRPC_DEBUG=y
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
# CONFIG_CEPH_FS_SECURITY_LABEL is not set
CONFIG_CIFS=m
# CONFIG_CIFS_STATS2 is not set
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CIFS_DEBUG=y
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
CONFIG_CIFS_DFS_UPCALL=y
# CONFIG_CIFS_SWN_UPCALL is not set
CONFIG_CIFS_FSCACHE=y
# CONFIG_SMB_SERVER is not set
CONFIG_SMBFS=m
CONFIG_CODA_FS=m
# CONFIG_AFS_FS is not set
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
CONFIG_9P_FS_SECURITY=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=m
CONFIG_NLS_MAC_GAELIC=m
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=m
CONFIG_DLM=m
CONFIG_DLM_DEBUG=y
# CONFIG_UNICODE is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
CONFIG_PERSISTENT_KEYRINGS=y
CONFIG_TRUSTED_KEYS=m
# CONFIG_TRUSTED_KEYS_TPM is not set

#
# No trust source selected!
#
CONFIG_ENCRYPTED_KEYS=y
# CONFIG_USER_DECRYPTED_DATA is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_KEY_NOTIFICATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_NETWORK_XFRM=y
# CONFIG_SECURITY_PATH is not set
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
# CONFIG_SECURITY_SELINUX is not set
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_SECURITY_APPARMOR is not set
# CONFIG_SECURITY_LOADPIN is not set
CONFIG_SECURITY_YAMA=y
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
# CONFIG_SECURITY_LANDLOCK is not set
# CONFIG_INTEGRITY is not set
# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
CONFIG_INIT_STACK_NONE=y
# CONFIG_INIT_STACK_ALL_PATTERN is not set
# CONFIG_INIT_STACK_ALL_ZERO is not set
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
# CONFIG_ZERO_CALL_USED_REGS is not set
# end of Memory initialization

CONFIG_RANDSTRUCT_NONE=y
# CONFIG_RANDSTRUCT_FULL is not set
# CONFIG_RANDSTRUCT_PERFORMANCE is not set
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=m
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SIG2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=m
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=m
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=m
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=m
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_ENGINE=y
# end of Crypto core or helper

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=m
# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set
CONFIG_CRYPTO_ECC=m
CONFIG_CRYPTO_ECDH=m
# CONFIG_CRYPTO_ECDSA is not set
# CONFIG_CRYPTO_ECRDSA is not set
# CONFIG_CRYPTO_SM2 is not set
# CONFIG_CRYPTO_CURVE25519 is not set
# end of Public-key cryptography

#
# Block ciphers
#
CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_AES_TI is not set
CONFIG_CRYPTO_ANUBIS=m
# CONFIG_CRYPTO_ARIA is not set
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_BLOWFISH_COMMON=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST_COMMON=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=m
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_GENERIC=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_TWOFISH_COMMON=m
# end of Block ciphers

#
# Length-preserving ciphers and modes
#
CONFIG_CRYPTO_ADIANTUM=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=m
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_HCTR2 is not set
CONFIG_CRYPTO_KEYWRAP=m
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_OFB=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_NHPOLY1305=y
# end of Length-preserving ciphers and modes

#
# AEAD (authenticated encryption with associated data) ciphers
#
CONFIG_CRYPTO_AEGIS128=m
# CONFIG_CRYPTO_AEGIS128_SIMD is not set
CONFIG_CRYPTO_CHACHA20POLY1305=m
CONFIG_CRYPTO_CCM=m
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_GENIV=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=m
CONFIG_CRYPTO_ESSIV=m
# end of AEAD (authenticated encryption with associated data) ciphers

#
# Hashes, digests, and MACs
#
CONFIG_CRYPTO_BLAKE2B=m
CONFIG_CRYPTO_CMAC=m
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_SM3_GENERIC=m
# CONFIG_CRYPTO_STREEBOG is not set
CONFIG_CRYPTO_VMAC=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_XXHASH=m
# end of Hashes, digests, and MACs

#
# CRCs (cyclic redundancy checks)
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
# end of CRCs (cyclic redundancy checks)

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=m
CONFIG_CRYPTO_LZ4=m
CONFIG_CRYPTO_LZ4HC=m
CONFIG_CRYPTO_ZSTD=m
# end of Compression

#
# Random number generation
#
CONFIG_CRYPTO_ANSI_CPRNG=m
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
# CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE is not set
# end of Random number generation

#
# Userspace interface
#
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
# CONFIG_CRYPTO_STATS is not set
# end of Userspace interface

CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_NHPOLY1305_NEON=y
CONFIG_CRYPTO_CHACHA20_NEON=y

#
# Accelerated Cryptographic Algorithms for CPU (arm64)
#
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_POLY1305_NEON=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA512_ARM64_CE=y
CONFIG_CRYPTO_SHA3_ARM64=y
# CONFIG_CRYPTO_SM3_NEON is not set
CONFIG_CRYPTO_SM3_ARM64_CE=y
# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CRYPTO_SM4_ARM64_CE=y
# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
# CONFIG_CRYPTO_SM4_ARM64_CE_CCM is not set
# CONFIG_CRYPTO_SM4_ARM64_CE_GCM is not set
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
# end of Accelerated Cryptographic Algorithms for CPU (arm64)

CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_ALLWINNER=y
# CONFIG_CRYPTO_DEV_SUN4I_SS is not set
CONFIG_CRYPTO_DEV_SUN8I_CE=m
# CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG is not set
# CONFIG_CRYPTO_DEV_SUN8I_CE_HASH is not set
# CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG is not set
# CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG is not set
CONFIG_CRYPTO_DEV_SUN8I_SS=m
# CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG is not set
# CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG is not set
# CONFIG_CRYPTO_DEV_SUN8I_SS_HASH is not set
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
CONFIG_CRYPTO_DEV_CCP=y
CONFIG_CRYPTO_DEV_CCP_DD=m
CONFIG_CRYPTO_DEV_SP_CCP=y
CONFIG_CRYPTO_DEV_CCP_CRYPTO=m
# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set
# CONFIG_CRYPTO_DEV_QAT_C62X is not set
# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set
# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_VIRTIO=m
CONFIG_CRYPTO_DEV_SAFEXCEL=m
CONFIG_CRYPTO_DEV_CCREE=m
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
# CONFIG_CRYPTO_DEV_HISI_TRNG is not set
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_PKCS7_TEST_KEY is not set
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
# CONFIG_FIPS_SIGNATURE_SELFTEST is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_RAID6_PQ=m
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
# CONFIG_PACKING is not set
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=m
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
# CONFIG_INDIRECT_PIO is not set

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=m
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=m
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
CONFIG_CRYPTO_LIB_CURVE25519=m
CONFIG_CRYPTO_LIB_DES=m
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=m
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines

CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC64_ROCKSOFT=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=y
# CONFIG_CRC4 is not set
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=y
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_842_COMPRESS=m
CONFIG_842_DECOMPRESS=m
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=m
CONFIG_LZ4HC_COMPRESS=m
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=m
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
# CONFIG_XZ_DEC_SPARC is not set
# CONFIG_XZ_DEC_MICROLZMA is not set
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_REED_SOLOMON=m
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_BCH=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_BTREE=y
CONFIG_INTERVAL_TREE=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_FLAGS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_SWIOTLB=y
CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
# CONFIG_DMA_RESTRICTED_POOL is not set
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y
# CONFIG_DMA_PERNUMA_CMA is not set

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_DMA_MAP_BENCHMARK is not set
CONFIG_SGL_ALLOC=y
CONFIG_CHECK_SIGNATURE=y
# CONFIG_FORCE_NR_CPUS is not set
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
CONFIG_IRQ_POLL=y
CONFIG_MPILIB=y
CONFIG_DIMLIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_MEMREGION=y
CONFIG_ARCH_STACKWALK=y
CONFIG_STACKDEPOT=y
CONFIG_SBITMAP=y
# end of Library routines

CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_CALLER is not set
CONFIG_STACKTRACE_BUILD_ID=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
CONFIG_BOOT_PRINTK_DELAY=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Compile-time checks and compiler options
#
CONFIG_AS_HAS_NON_CONST_LEB128=y
CONFIG_DEBUG_INFO_NONE=y
# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_DEBUG_INFO_DWARF5 is not set
CONFIG_FRAME_WARN=1024
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_READABLE_ASM is not set
# CONFIG_HEADERS_INSTALL is not set
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_VMLINUX_MAP is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_KGDB=y
CONFIG_KGDB_HONOUR_BLOCKLIST=y
CONFIG_KGDB_SERIAL_CONSOLE=y
CONFIG_KGDB_TESTS=y
# CONFIG_KGDB_TESTS_ON_BOOT is not set
# CONFIG_KGDB_KDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_ARCH_KCSAN=y
CONFIG_HAVE_KCSAN_COMPILER=y
# CONFIG_KCSAN is not set
# end of Generic Kernel Debugging Instruments

#
# Networking Debugging
#
# CONFIG_NET_DEV_REFCNT_TRACKER is not set
# CONFIG_NET_NS_REFCNT_TRACKER is not set
# CONFIG_DEBUG_NET is not set
# end of Networking Debugging

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_SLUB_DEBUG=y
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_TABLE_CHECK is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_PER_VMA_LOCK_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SHRINKER_DEBUG is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
CONFIG_DEBUG_VM_IRQSOFF=y
CONFIG_DEBUG_VM=y
# CONFIG_DEBUG_VM_MAPLE_TREE is not set
# CONFIG_DEBUG_VM_RB is not set
# CONFIG_DEBUG_VM_PGFLAGS is not set
CONFIG_DEBUG_VM_PGTABLE=y
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
# end of Memory Debugging

# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y
# CONFIG_HARDLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
CONFIG_SCHED_DEBUG=y
CONFIG_SCHED_INFO=y
CONFIG_SCHEDSTATS=y
# end of Scheduler Debugging

# CONFIG_DEBUG_TIMEKEEPING is not set

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

# CONFIG_DEBUG_IRQFLAGS is not set
CONFIG_STACKTRACE=y
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set

#
# Debug kernel data structures
#
CONFIG_DEBUG_LIST=y
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# CONFIG_DEBUG_MAPLE_TREE is not set
# end of Debug kernel data structures

# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
CONFIG_TORTURE_TEST=m
# CONFIG_RCU_SCALE_TEST is not set
CONFIG_RCU_TORTURE_TEST=m
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=60
CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
# CONFIG_RCU_CPU_STALL_CPUTIME is not set
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
# CONFIG_LATENCYTOP is not set
# CONFIG_DEBUG_CGROUP_REF is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y
CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y
CONFIG_STRICT_DEVMEM=y
# CONFIG_IO_STRICT_DEVMEM is not set

#
# arm64 Debugging
#
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
# end of arm64 Debugging

#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
CONFIG_FUNCTION_ERROR_INJECTION=y
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_ARCH_USE_MEMTEST=y
# CONFIG_MEMTEST is not set
# end of Kernel Testing and Coverage

#
# Rust hacking
#
# end of Rust hacking
# end of Kernel hacking


================================================
FILE: kernel-config/release/h6/config-6.6
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 6.6.130 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 15.2.Rel1 (Build arm-15.86)) 15.2.1 20251203"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=150201
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=24501
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=24501
CONFIG_LLD_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_TOOLS_SUPPORT_RELR=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_CC_HAS_COUNTED_BY=y
CONFIG_PAHOLE_VERSION=130
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
CONFIG_WATCH_QUEUE=y
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_USELIB is not set
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_INJECTION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem

CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
# CONFIG_NO_HZ_FULL is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y

#
# BPF subsystem
#
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_JIT=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
CONFIG_BPF_JIT_DEFAULT_ON=y
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
CONFIG_USERMODE_DRIVER=y
# CONFIG_BPF_PRELOAD is not set
# end of BPF subsystem

CONFIG_PREEMPT_VOLUNTARY_BUILD=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
# CONFIG_PREEMPT_DYNAMIC is not set
CONFIG_SCHED_CORE=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_SCHED_AVG_IRQ=y
CONFIG_SCHED_THERMAL_PRESSURE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_PSI=y
# CONFIG_PSI_DEFAULT_DISABLED is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
# CONFIG_PRINTK_INDEX is not set
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
# CONFIG_UCLAMP_TASK is not set
# end of Scheduler features

CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
CONFIG_CC_HAS_INT128=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_GCC10_NO_ARRAY_BOUNDS=y
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
# CONFIG_RT_GROUP_SCHED is not set
CONFIG_SCHED_MM_CID=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
# CONFIG_CGROUP_MISC is not set
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_SCHED_AUTOGROUP=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
# CONFIG_BOOT_CONFIG_FORCE is not set
# CONFIG_BOOT_CONFIG_EMBED is not set
# CONFIG_INITRAMFS_PRESERVE_MTIME is not set
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
# CONFIG_SGETMASK_SYSCALL is not set
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_SELFTEST is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
CONFIG_CACHESTAT_SYSCALL=y
# CONFIG_DEBUG_RSEQ is not set
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_GUEST_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y

#
# Kexec and crash features
#
CONFIG_CRASH_CORE=y
CONFIG_KEXEC_CORE=y
CONFIG_KEXEC=y
CONFIG_KEXEC_FILE=y
# CONFIG_KEXEC_SIG is not set
# CONFIG_CRASH_DUMP is not set
# end of Kexec and crash features
# end of General setup

CONFIG_ARM64=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_CONT_PTE_SHIFT=4
CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y

#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
CONFIG_ARCH_SUNXI=y
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_APPLE is not set
# CONFIG_ARCH_BCM is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SPARX5 is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_KEEMBAY is not set
# CONFIG_ARCH_MEDIATEK is not set
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_NXP is not set
# CONFIG_ARCH_MA35 is not set
# CONFIG_ARCH_NPCM is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_RENESAS is not set
# CONFIG_ARCH_ROCKCHIP is not set
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_INTEL_SOCFPGA is not set
# CONFIG_ARCH_STM32 is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
CONFIG_ARCH_VEXPRESS=y
# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZYNQMP is not set
# end of Platform selection

#
# Kernel Features
#

#
# ARM errata workarounds via the alternatives framework
#
# CONFIG_AMPERE_ERRATUM_AC03_CPU_38 is not set
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_834220=y
# CONFIG_ARM64_ERRATUM_1742098 is not set
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1319367=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
# CONFIG_ARM64_ERRATUM_2441007 is not set
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_ARM64_ERRATUM_2051678=y
CONFIG_ARM64_ERRATUM_2077057=y
# CONFIG_ARM64_ERRATUM_2658417 is not set
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
CONFIG_ARM64_ERRATUM_2054223=y
CONFIG_ARM64_ERRATUM_2067961=y
# CONFIG_ARM64_ERRATUM_2441009 is not set
# CONFIG_ARM64_ERRATUM_2457168 is not set
# CONFIG_ARM64_ERRATUM_2645198 is not set
CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y
CONFIG_ARM64_ERRATUM_2966298=y
CONFIG_ARM64_ERRATUM_3117295=y
CONFIG_ARM64_ERRATUM_3194386=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
CONFIG_QCOM_FALKOR_ERRATUM_1009=y
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
# CONFIG_ROCKCHIP_ERRATUM_3588001 is not set
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
# end of ARM errata workarounds via the alternatives framework

CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
# CONFIG_ARM64_VA_BITS_39 is not set
CONFIG_ARM64_VA_BITS_48=y
CONFIG_ARM64_VA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SCHED_MC=y
# CONFIG_SCHED_CLUSTER is not set
CONFIG_SCHED_SMT=y
CONFIG_NR_CPUS=8
CONFIG_HOTPLUG_CPU=y
# CONFIG_NUMA is not set
CONFIG_HZ_100=y
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=100
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_PARAVIRT=y
CONFIG_PARAVIRT_TIME_ACCOUNTING=y
CONFIG_ARCH_SUPPORTS_KEXEC=y
CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y
CONFIG_ARCH_SELECTS_KEXEC_FILE=y
CONFIG_ARCH_SUPPORTS_KEXEC_SIG=y
CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG=y
CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y
CONFIG_TRANS_TABLE=y
# CONFIG_XEN is not set
CONFIG_ARCH_FORCE_MAX_ORDER=10
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y
# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y

#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
CONFIG_AS_HAS_LSE_ATOMICS=y
CONFIG_ARM64_LSE_ATOMICS=y
CONFIG_ARM64_USE_LSE_ATOMICS=y
# end of ARMv8.1 architectural features

#
# ARMv8.2 architectural features
#
CONFIG_AS_HAS_ARMV8_2=y
CONFIG_AS_HAS_SHA3=y
# CONFIG_ARM64_PMEM is not set
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features

#
# ARMv8.3 architectural features
#
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
CONFIG_AS_HAS_ARMV8_3=y
CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
CONFIG_AS_HAS_LDAPR=y
# end of ARMv8.3 architectural features

#
# ARMv8.4 architectural features
#
CONFIG_ARM64_AMU_EXTN=y
CONFIG_AS_HAS_ARMV8_4=y
CONFIG_ARM64_TLB_RANGE=y
# end of ARMv8.4 architectural features

#
# ARMv8.5 architectural features
#
CONFIG_AS_HAS_ARMV8_5=y
CONFIG_ARM64_BTI=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARM64_AS_HAS_MTE=y
CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features

#
# ARMv8.7 architectural features
#
CONFIG_ARM64_EPAN=y
# end of ARMv8.7 architectural features

CONFIG_ARM64_SVE=y
# CONFIG_ARM64_PSEUDO_NMI is not set
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
# end of Kernel Features

#
# Boot options
#
CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
CONFIG_CMDLINE="console=ttyAMA0"
CONFIG_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_CMDLINE_FORCE is not set
CONFIG_EFI_STUB=y
CONFIG_EFI=y
CONFIG_DMI=y
# end of Boot options

#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
CONFIG_HIBERNATE_CALLBACKS=y
CONFIG_HIBERNATION=y
CONFIG_HIBERNATION_SNAPSHOT_DEV=y
CONFIG_PM_STD_PARTITION=""
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
CONFIG_PM_DEBUG=y
# CONFIG_PM_ADVANCED_DEBUG is not set
CONFIG_PM_TEST_SUSPEND=y
CONFIG_PM_SLEEP_DEBUG=y
# CONFIG_DPM_WATCHDOG is not set
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_HIBERNATION_HEADER=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options

#
# CPU Power Management
#

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_DT_IDLE_STATES=y
CONFIG_DT_IDLE_GENPD=y

#
# ARM CPU Idle Drivers
#
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
# end of ARM CPU Idle Drivers
# end of CPU Idle

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_ACPI_CPPC_CPUFREQ=y
CONFIG_ACPI_CPPC_CPUFREQ_FIE=y
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_SCMI_CPUFREQ=y
# end of CPU Frequency scaling
# end of CPU Power Management

CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_GENERIC_GSI=y
CONFIG_ACPI_CCA_REQUIRED=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
# CONFIG_ACPI_FPDT is not set
CONFIG_ACPI_EC_DEBUGFS=y
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_VIDEO=m
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_TAD is not set
CONFIG_ACPI_DOCK=y
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_MCFG=y
CONFIG_ACPI_CPPC_LIB=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_IPMI=m
CONFIG_ACPI_HOTPLUG_CPU=y
CONFIG_ACPI_THERMAL=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_PCI_SLOT=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_CUSTOM_METHOD=y
# CONFIG_ACPI_BGRT is not set
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
CONFIG_HAVE_ACPI_APEI=y
# CONFIG_ACPI_APEI is not set
CONFIG_ACPI_CONFIGFS=m
# CONFIG_ACPI_PFRUT is not set
CONFIG_ACPI_IORT=y
CONFIG_ACPI_GTDT=y
CONFIG_ACPI_APMT=y
CONFIG_ACPI_PPTT=y
CONFIG_ACPI_PCC=y
# CONFIG_ACPI_FFH is not set
CONFIG_PMIC_OPREGION=y
# CONFIG_ACPI_PRMT is not set
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_HAVE_KVM=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_DIRTY_RING=y
CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y
CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_MMIO=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_KVM_XFER_TO_GUEST_WORK=y
CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
# CONFIG_NVHE_EL2_DEBUG is not set
CONFIG_CPU_MITIGATIONS=y

#
# General architecture-dependent options
#
CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y
CONFIG_HOTPLUG_CORE_SYNC=y
CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
# CONFIG_SECCOMP_CACHE_DEBUG is not set
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
# CONFIG_SHADOW_CALL_STACK is not set
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
CONFIG_HAVE_CONTEXT_TRACKING_USER=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_ARCH_HUGE_VMALLOC=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET=y
# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
CONFIG_RELR=y
CONFIG_HAVE_PREEMPT_DYNAMIC=y
CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FUNCTION_ALIGNMENT=4
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_DEBUG is not set
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS_NONE is not set
CONFIG_MODULE_COMPRESS_GZIP=y
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
# CONFIG_MODULE_DECOMPRESS is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BLK_CGROUP_RWSTAT=y
CONFIG_BLK_CGROUP_PUNT_BIO=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_ICQ=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=y
CONFIG_BLK_DEV_ZONED=y
CONFIG_BLK_DEV_THROTTLING=y
# CONFIG_BLK_DEV_THROTTLING_LOW is not set
CONFIG_BLK_WBT=y
CONFIG_BLK_WBT_MQ=y
# CONFIG_BLK_CGROUP_IOLATENCY is not set
# CONFIG_BLK_CGROUP_IOCOST is not set
CONFIG_BLK_CGROUP_IOPRIO=y
CONFIG_BLK_DEBUG_FS=y
CONFIG_BLK_DEBUG_FS_ZONED=y
CONFIG_BLK_SED_OPAL=y
# CONFIG_BLK_INLINE_ENCRYPTION is not set

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
CONFIG_AIX_PARTITION=y
CONFIG_OSF_PARTITION=y
CONFIG_AMIGA_PARTITION=y
# CONFIG_ATARI_PARTITION is not set
CONFIG_MAC_PARTITION=y
CONFIG_MSDOS_PARTITION=y
CONFIG_BSD_DISKLABEL=y
CONFIG_MINIX_SUBPARTITION=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_UNIXWARE_DISKLABEL=y
CONFIG_LDM_PARTITION=y
# CONFIG_LDM_DEBUG is not set
CONFIG_SGI_PARTITION=y
# CONFIG_ULTRIX_PARTITION is not set
CONFIG_SUN_PARTITION=y
CONFIG_KARMA_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
# CONFIG_CMDLINE_PARTITION is not set
# end of Partition Types

CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_HOLDER_DEPRECATED=y
CONFIG_BLK_MQ_STACKING=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
# CONFIG_BFQ_CGROUP_DEBUG is not set
# end of IO Schedulers

CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK=y
CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_READ_LOCK=y
CONFIG_ARCH_INLINE_READ_LOCK_BH=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_READ_UNLOCK=y
CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_WRITE_LOCK=y
CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_SPIN_TRYLOCK=y
CONFIG_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_INLINE_SPIN_LOCK=y
CONFIG_INLINE_SPIN_LOCK_BH=y
CONFIG_INLINE_SPIN_LOCK_IRQ=y
CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_INLINE_SPIN_UNLOCK_BH=y
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_READ_LOCK=y
CONFIG_INLINE_READ_LOCK_BH=y
CONFIG_INLINE_READ_LOCK_IRQ=y
CONFIG_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_INLINE_READ_UNLOCK=y
CONFIG_INLINE_READ_UNLOCK_BH=y
CONFIG_INLINE_READ_UNLOCK_IRQ=y
CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_WRITE_LOCK=y
CONFIG_INLINE_WRITE_LOCK_BH=y
CONFIG_INLINE_WRITE_LOCK_IRQ=y
CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_INLINE_WRITE_UNLOCK=y
CONFIG_INLINE_WRITE_UNLOCK_BH=y
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_HAVE_ELF_PROT=y
CONFIG_ARCH_USE_GNU_PROPERTY=y
CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=y
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_ZPOOL=y
CONFIG_SWAP=y
CONFIG_ZSWAP=y
# CONFIG_ZSWAP_DEFAULT_ON is not set
# CONFIG_ZSWAP_EXCLUSIVE_LOADS_DEFAULT_ON is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set
CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo"
CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD_DEPRECATED is not set
# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
CONFIG_ZBUD=y
# CONFIG_Z3FOLD_DEPRECATED is not set
CONFIG_ZSMALLOC=y
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_ZSMALLOC_CHAIN_SIZE=8

#
# SLAB allocator options
#
# CONFIG_SLAB_DEPRECATED is not set
CONFIG_SLUB=y
# CONFIG_SLUB_TINY is not set
CONFIG_SLAB_MERGE_DEFAULT=y
CONFIG_SLAB_FREELIST_RANDOM=y
# CONFIG_SLAB_FREELIST_HARDENED is not set
# CONFIG_SLUB_STATS is not set
CONFIG_SLUB_CPU_PARTIAL=y
# CONFIG_RANDOM_KMALLOC_CACHES is not set
# end of SLAB allocator options

# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PCP_BATCH_SCALE_MAX=5
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_MMU_NOTIFIER=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
# CONFIG_MEMORY_FAILURE is not set
CONFIG_ARCH_WANTS_THP_SWAP=y
# CONFIG_TRANSPARENT_HUGEPAGE is not set
CONFIG_CMA=y
# CONFIG_CMA_DEBUG is not set
CONFIG_CMA_DEBUGFS=y
# CONFIG_CMA_SYSFS is not set
CONFIG_CMA_AREAS=7
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_ARCH_HAS_ZONE_DMA_SET=y
CONFIG_ZONE_DMA=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
CONFIG_ARCH_USES_PG_ARCH_X=y
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_TEST is not set
# CONFIG_DMAPOOL_TEST is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_MEMFD_CREATE=y
CONFIG_SECRETMEM=y
# CONFIG_ANON_VMA_NAME is not set
# CONFIG_USERFAULTFD is not set
# CONFIG_LRU_GEN is not set
CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y
CONFIG_PER_VMA_LOCK=y
CONFIG_LOCK_MM_AND_FIND_VMA=y

#
# Data Access Monitoring
#
# CONFIG_DAMON is not set
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_XGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_EXTENSIONS=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=m
CONFIG_UNIX=y
CONFIG_AF_UNIX_OOB=y
CONFIG_UNIX_DIAG=m
CONFIG_TLS=m
# CONFIG_TLS_DEVICE is not set
# CONFIG_TLS_TOE is not set
CONFIG_XFRM=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
# CONFIG_XFRM_INTERFACE is not set
CONFIG_XFRM_SUB_POLICY=y
CONFIG_XFRM_MIGRATE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_XFRM_AH=m
CONFIG_XFRM_ESP=m
CONFIG_XFRM_IPCOMP=m
CONFIG_NET_KEY=m
CONFIG_NET_KEY_MIGRATE=y
# CONFIG_XDP_SOCKETS is not set
CONFIG_NET_HANDSHAKE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_FIB_TRIE_STATS=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_ROUTE_CLASSID=y
# CONFIG_IP_PNP is not set
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=m
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=m
CONFIG_NET_FOU=m
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
# CONFIG_INET_ESP_OFFLOAD is not set
# CONFIG_INET_ESPINTCP is not set
CONFIG_INET_IPCOMP=m
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_DIAG=m
CONFIG_INET_TCP_DIAG=m
CONFIG_INET_UDP_DIAG=m
CONFIG_INET_RAW_DIAG=m
# CONFIG_INET_DIAG_DESTROY is not set
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_NV=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_CONG_DCTCP=m
CONFIG_TCP_CONG_CDG=m
CONFIG_TCP_CONG_BBR=m
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_TCP_MD5SIG=y
CONFIG_IPV6=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
# CONFIG_INET6_ESP_OFFLOAD is not set
# CONFIG_INET6_ESPINTCP is not set
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_MIP6=y
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=m
CONFIG_INET6_TUNNEL=m
CONFIG_IPV6_VTI=m
CONFIG_IPV6_SIT=m
CONFIG_IPV6_SIT_6RD=y
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=m
CONFIG_IPV6_GRE=m
CONFIG_IPV6_FOU=m
CONFIG_IPV6_FOU_TUNNEL=m
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
CONFIG_IPV6_SEG6_LWTUNNEL=y
CONFIG_IPV6_SEG6_HMAC=y
CONFIG_IPV6_SEG6_BPF=y
# CONFIG_IPV6_RPL_LWTUNNEL is not set
# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
CONFIG_NETLABEL=y
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=m
CONFIG_MPTCP_IPV6=y
# CONFIG_NETWORK_SECMARK is not set
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NETWORK_PHY_TIMESTAMPING=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_EGRESS=y
CONFIG_NETFILTER_SKIP_EGRESS=y
CONFIG_NETFILTER_NETLINK=m
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
CONFIG_NETFILTER_BPF_LINK=y
CONFIG_NETFILTER_NETLINK_HOOK=m
CONFIG_NETFILTER_NETLINK_ACCT=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NETFILTER_NETLINK_OSF=m
CONFIG_NF_CONNTRACK=m
CONFIG_NF_LOG_SYSLOG=m
CONFIG_NETFILTER_CONNCOUNT=m
CONFIG_NF_CONNTRACK_MARK=y
CONFIG_NF_CONNTRACK_ZONES=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_TIMEOUT=y
CONFIG_NF_CONNTRACK_TIMESTAMP=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CONNTRACK_OVS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_CT_NETLINK_TIMEOUT=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=m
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NF_NAT_OVS=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=m
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
CONFIG_NFT_OSF=m
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NF_DUP_NETDEV=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NFT_REJECT_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
# CONFIG_NF_FLOW_TABLE_PROCFS is not set
CONFIG_NETFILTER_XTABLES=y
CONFIG_NETFILTER_XTABLES_COMPAT=y

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=m
CONFIG_NETFILTER_XT_CONNMARK=m
CONFIG_NETFILTER_XT_SET=m

#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_AUDIT=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LED=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=m
CONFIG_NETFILTER_XT_TARGET_NETMAP=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
CONFIG_NETFILTER_XT_TARGET_RATEEST=m
CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=m
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# end of Core Netfilter Configuration

CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
# CONFIG_IP_VS_DEBUG is not set
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m
# CONFIG_IP_VS_TWOS is not set

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=m
CONFIG_NF_SOCKET_IPV4=m
CONFIG_NF_TPROXY_IPV4=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=y
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_SECURITY=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP6_NF_SECURITY=m
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=m
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_NFT_BRIDGE_META=m
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
CONFIG_BPFILTER=y
CONFIG_BPFILTER_UMH=m
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m

#
# DCCP CCIDs Configuration
#
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
CONFIG_IP_DCCP_CCID3=y
# CONFIG_IP_DCCP_CCID3_DEBUG is not set
CONFIG_IP_DCCP_TFRC_LIB=y
# end of DCCP CCIDs Configuration

#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
# end of DCCP Kernel Hacking

CONFIG_IP_SCTP=m
# CONFIG_SCTP_DBG_OBJCNT is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5 is not set
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=m
CONFIG_RDS=m
CONFIG_RDS_TCP=m
# CONFIG_RDS_DEBUG is not set
CONFIG_TIPC=m
CONFIG_TIPC_MEDIA_UDP=y
CONFIG_TIPC_CRYPTO=y
CONFIG_TIPC_DIAG=m
CONFIG_ATM=m
CONFIG_ATM_CLIP=m
# CONFIG_ATM_CLIP_NO_ICMP is not set
CONFIG_ATM_LANE=m
# CONFIG_ATM_MPOA is not set
CONFIG_ATM_BR2684=m
# CONFIG_ATM_BR2684_IPFILTER is not set
CONFIG_L2TP=m
CONFIG_L2TP_DEBUGFS=m
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=m
CONFIG_L2TP_ETH=m
CONFIG_STP=m
CONFIG_GARP=m
CONFIG_MRP=m
CONFIG_BRIDGE=m
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
# CONFIG_BRIDGE_MRP is not set
# CONFIG_BRIDGE_CFM is not set
CONFIG_NET_DSA=m
CONFIG_NET_DSA_TAG_NONE=m
# CONFIG_NET_DSA_TAG_AR9331 is not set
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
CONFIG_NET_DSA_TAG_BRCM=m
CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
# CONFIG_NET_DSA_TAG_HELLCREEK is not set
# CONFIG_NET_DSA_TAG_GSWIP is not set
CONFIG_NET_DSA_TAG_DSA_COMMON=m
CONFIG_NET_DSA_TAG_DSA=m
CONFIG_NET_DSA_TAG_EDSA=m
# CONFIG_NET_DSA_TAG_MTK is not set
# CONFIG_NET_DSA_TAG_KSZ is not set
# CONFIG_NET_DSA_TAG_OCELOT is not set
# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set
CONFIG_NET_DSA_TAG_QCA=m
# CONFIG_NET_DSA_TAG_RTL4_A is not set
# CONFIG_NET_DSA_TAG_RTL8_4 is not set
# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set
# CONFIG_NET_DSA_TAG_LAN9303 is not set
# CONFIG_NET_DSA_TAG_SJA1105 is not set
CONFIG_NET_DSA_TAG_TRAILER=m
# CONFIG_NET_DSA_TAG_XRS700X is not set
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q_MVRP=y
CONFIG_LLC=m
# CONFIG_LLC2 is not set
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
CONFIG_6LOWPAN=m
# CONFIG_6LOWPAN_DEBUGFS is not set
CONFIG_6LOWPAN_NHC=m
CONFIG_6LOWPAN_NHC_DEST=m
CONFIG_6LOWPAN_NHC_FRAGMENT=m
CONFIG_6LOWPAN_NHC_HOP=m
CONFIG_6LOWPAN_NHC_IPV6=m
CONFIG_6LOWPAN_NHC_MOBILITY=m
CONFIG_6LOWPAN_NHC_ROUTING=m
CONFIG_6LOWPAN_NHC_UDP=m
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
CONFIG_6LOWPAN_GHC_UDP=m
CONFIG_6LOWPAN_GHC_ICMPV6=m
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
CONFIG_IEEE802154=m
# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set
CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_MAC802154=m
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFB=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_MQPRIO_LIB=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_SKBPRIO=m
CONFIG_NET_SCH_CHOKE=m
CONFIG_NET_SCH_QFQ=m
CONFIG_NET_SCH_CODEL=m
CONFIG_NET_SCH_FQ_CODEL=y
CONFIG_NET_SCH_CAKE=m
CONFIG_NET_SCH_FQ=m
CONFIG_NET_SCH_HHF=m
CONFIG_NET_SCH_PIE=m
CONFIG_NET_SCH_FQ_PIE=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_SCH_PLUG=m
CONFIG_NET_SCH_ETS=m
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_PERF=y
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=y
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_EMATCH_CANID=m
CONFIG_NET_EMATCH_IPSET=m
CONFIG_NET_EMATCH_IPT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_SAMPLE=m
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
# CONFIG_NET_ACT_MPLS is not set
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_NET_ACT_CONNMARK=m
CONFIG_NET_ACT_CTINFO=m
CONFIG_NET_ACT_SKBMOD=m
CONFIG_NET_ACT_IFE=m
CONFIG_NET_ACT_TUNNEL_KEY=m
CONFIG_NET_ACT_CT=m
CONFIG_NET_ACT_GATE=m
CONFIG_NET_IFE_SKBMARK=m
CONFIG_NET_IFE_SKBPRIO=m
CONFIG_NET_IFE_SKBTCINDEX=m
# CONFIG_NET_TC_SKB_EXT is not set
CONFIG_NET_SCH_FIFO=y
CONFIG_DCB=y
CONFIG_DNS_RESOLVER=y
CONFIG_BATMAN_ADV=m
# CONFIG_BATMAN_ADV_BATMAN_V is not set
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
CONFIG_BATMAN_ADV_NC=y
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUG is not set
CONFIG_OPENVSWITCH=m
CONFIG_OPENVSWITCH_GRE=m
CONFIG_OPENVSWITCH_VXLAN=m
CONFIG_OPENVSWITCH_GENEVE=m
CONFIG_VSOCKETS=m
CONFIG_VSOCKETS_DIAG=m
CONFIG_VSOCKETS_LOOPBACK=m
CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO_VSOCKETS_COMMON=m
CONFIG_NETLINK_DIAG=m
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=m
CONFIG_MPLS_ROUTING=m
# CONFIG_MPLS_IPTUNNEL is not set
CONFIG_NET_NSH=m
# CONFIG_HSR is not set
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=m
CONFIG_QRTR_SMD=m
CONFIG_QRTR_TUN=m
# CONFIG_NET_NCSI is not set
CONFIG_PCPU_DEV_REFCNT=y
CONFIG_MAX_SKB_FRAGS=17
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_XPS=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
CONFIG_NET_PKTGEN=m
# end of Network testing
# end of Networking options

CONFIG_HAMRADIO=y

#
# Packet Radio protocols
#
CONFIG_AX25=m
CONFIG_AX25_DAMA_SLAVE=y
CONFIG_NETROM=m
CONFIG_ROSE=m

#
# AX.25 network device drivers
#
CONFIG_MKISS=m
CONFIG_6PACK=m
CONFIG_BPQETHER=m
CONFIG_BAYCOM_SER_FDX=m
CONFIG_BAYCOM_SER_HDX=m
CONFIG_YAM=m
# end of AX.25 network device drivers

CONFIG_CAN=m
CONFIG_CAN_RAW=m
CONFIG_CAN_BCM=m
CONFIG_CAN_GW=m
# CONFIG_CAN_J1939 is not set
# CONFIG_CAN_ISOTP is not set
CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
# CONFIG_BT_HIDP is not set
CONFIG_BT_LE=y
CONFIG_BT_LE_L2CAP_ECRED=y
CONFIG_BT_6LOWPAN=m
# CONFIG_BT_LEDS is not set
# CONFIG_BT_MSFTEXT is not set
# CONFIG_BT_AOSPEXT is not set
# CONFIG_BT_DEBUGFS is not set
# CONFIG_BT_SELFTEST is not set

#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=m
CONFIG_BT_BCM=m
CONFIG_BT_RTL=m
CONFIG_BT_QCA=m
CONFIG_BT_HCIBTUSB=m
# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
CONFIG_BT_HCIBTUSB_POLL_SYNC=y
CONFIG_BT_HCIBTUSB_BCM=y
# CONFIG_BT_HCIBTUSB_MTK is not set
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
# CONFIG_BT_HCIUART_NOKIA is not set
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_BCM=y
# CONFIG_BT_HCIUART_RTL is not set
CONFIG_BT_HCIUART_QCA=y
# CONFIG_BT_HCIUART_AG6XX is not set
CONFIG_BT_HCIUART_MRVL=y
CONFIG_BT_HCIBCM203X=m
# CONFIG_BT_HCIBCM4377 is not set
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
# CONFIG_BT_MTKSDIO is not set
# CONFIG_BT_MTKUART is not set
CONFIG_BT_HCIRSI=m
# CONFIG_BT_VIRTIO is not set
# CONFIG_BT_NXPUART is not set
# end of Bluetooth device drivers

# CONFIG_AF_RXRPC is not set
# CONFIG_AF_KCM is not set
CONFIG_STREAM_PARSER=y
# CONFIG_MCTP is not set
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_SPY=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_DEFAULT_PS=y
CONFIG_CFG80211_DEBUGFS=y
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_CFG80211_WEXT_EXPORT=y
CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
CONFIG_LIB80211_CRYPT_TKIP=m
# CONFIG_LIB80211_DEBUG is not set
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
CONFIG_MAC80211_DEBUGFS=y
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_RFKILL=m
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=m
CONFIG_NET_9P=m
CONFIG_NET_9P_FD=m
CONFIG_NET_9P_VIRTIO=m
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
CONFIG_CEPH_LIB=m
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
CONFIG_NFC=m
CONFIG_NFC_DIGITAL=m
CONFIG_NFC_NCI=m
# CONFIG_NFC_NCI_SPI is not set
# CONFIG_NFC_NCI_UART is not set
CONFIG_NFC_HCI=m
CONFIG_NFC_SHDLC=y

#
# Near Field Communication (NFC) devices
#
# CONFIG_NFC_TRF7970A is not set
CONFIG_NFC_SIM=m
CONFIG_NFC_PORT100=m
# CONFIG_NFC_VIRTUAL_NCI is not set
# CONFIG_NFC_FDP is not set
CONFIG_NFC_PN544=m
CONFIG_NFC_PN544_I2C=m
# CONFIG_NFC_PN533_USB is not set
# CONFIG_NFC_PN533_I2C is not set
# CONFIG_NFC_PN532_UART is not set
CONFIG_NFC_MICROREAD=m
CONFIG_NFC_MICROREAD_I2C=m
CONFIG_NFC_MRVL=m
CONFIG_NFC_MRVL_USB=m
# CONFIG_NFC_MRVL_I2C is not set
CONFIG_NFC_ST21NFCA=m
CONFIG_NFC_ST21NFCA_I2C=m
# CONFIG_NFC_ST_NCI_I2C is not set
# CONFIG_NFC_ST_NCI_SPI is not set
# CONFIG_NFC_NXP_NCI is not set
CONFIG_NFC_S3FWRN5=m
CONFIG_NFC_S3FWRN5_I2C=m
# CONFIG_NFC_S3FWRN82_UART is not set
# CONFIG_NFC_ST95HF is not set
# end of Near Field Communication (NFC) devices

CONFIG_PSAMPLE=m
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_FAILOVER=m
CONFIG_ETHTOOL_NETLINK=y

#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
CONFIG_PCIEPORTBUS=y
CONFIG_HOTPLUG_PCI_PCIE=y
CONFIG_PCIEAER=y
CONFIG_PCIEAER_INJECT=m
CONFIG_PCIE_ECRC=y
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
# CONFIG_PCIEASPM_PERFORMANCE is not set
CONFIG_PCIE_PME=y
# CONFIG_PCIE_DPC is not set
# CONFIG_PCIE_PTM is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
CONFIG_PCI_STUB=y
# CONFIG_PCI_PF_STUB is not set
CONFIG_PCI_ATS=y
CONFIG_PCI_ECAM=y
CONFIG_PCI_IOV=y
CONFIG_PCI_PRI=y
CONFIG_PCI_PASID=y
CONFIG_PCI_LABEL=y
# CONFIG_PCI_DYNAMIC_OF_NODES is not set
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
CONFIG_HOTPLUG_PCI=y
CONFIG_HOTPLUG_PCI_ACPI=y
# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
# CONFIG_HOTPLUG_PCI_CPCI is not set
# CONFIG_HOTPLUG_PCI_SHPC is not set

#
# PCI controller drivers
#
# CONFIG_PCIE_ALTERA is not set
# CONFIG_PCI_HOST_THUNDER_PEM is not set
# CONFIG_PCI_HOST_THUNDER_ECAM is not set
# CONFIG_PCI_FTPCI100 is not set
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
# CONFIG_PCIE_MICROCHIP_HOST is not set
CONFIG_PCI_XGENE=y
CONFIG_PCI_XGENE_MSI=y
# CONFIG_PCIE_XILINX is not set

#
# Cadence-based PCIe controllers
#
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCI_J721E_HOST is not set
# end of Cadence-based PCIe controllers

#
# DesignWare-based PCIe controllers
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
# CONFIG_PCIE_AL is not set
CONFIG_PCI_MESON=y
CONFIG_PCI_HISI=y
# CONFIG_PCIE_KIRIN is not set
CONFIG_PCIE_DW_PLAT=y
CONFIG_PCIE_DW_PLAT_HOST=y
# end of DesignWare-based PCIe controllers

#
# Mobiveil-based PCIe controllers
#
# end of Mobiveil-based PCIe controllers
# end of PCI controller drivers

#
# PCI Endpoint
#
# CONFIG_PCI_ENDPOINT is not set
# end of PCI Endpoint

#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set
# end of PCI switch controller drivers

# CONFIG_CXL_BUS is not set
# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
CONFIG_AUXILIARY_BUS=y
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_DEVTMPFS_SAFE is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_DEBUG=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_FW_LOADER_USER_HELPER is not set
# CONFIG_FW_LOADER_COMPRESS is not set
CONFIG_FW_CACHE=y
# CONFIG_FW_UPLOAD is not set
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
CONFIG_DEBUG_DEVRES=y
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SLIMBUS=m
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_SPMI=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SOUNDWIRE=m
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
# CONFIG_BRCMSTB_GISB_ARB is not set
# CONFIG_MOXTET is not set
CONFIG_SUN50I_DE2_BUS=y
CONFIG_SUNXI_RSB=y
CONFIG_VEXPRESS_CONFIG=y
# CONFIG_MHI_BUS is not set
# CONFIG_MHI_BUS_EP is not set
# end of Bus devices

#
# Cache Drivers
#
# end of Cache Drivers

CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y

#
# Firmware Drivers
#

#
# ARM System Control and Management Interface Protocol
#
CONFIG_ARM_SCMI_PROTOCOL=y
# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
# CONFIG_ARM_SCMI_DEBUG_COUNTERS is not set
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
CONFIG_ARM_SCMI_HAVE_SHMEM=y
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set
CONFIG_ARM_SCMI_POWER_DOMAIN=y
# CONFIG_ARM_SCMI_POWER_CONTROL is not set
# end of ARM System Control and Management Interface Protocol

CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
# CONFIG_ARM_SDE_INTERFACE is not set
# CONFIG_FIRMWARE_MEMMAP is not set
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=y
# CONFIG_ISCSI_IBFT is not set
# CONFIG_FW_CFG_SYSFS is not set
CONFIG_SYSFB=y
# CONFIG_SYSFB_SIMPLEFB is not set
CONFIG_ARM_FFA_TRANSPORT=m
CONFIG_ARM_FFA_SMCCC=y
# CONFIG_GOOGLE_FIRMWARE is not set

#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_VARS_PSTORE=y
CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_GENERIC_STUB=y
# CONFIG_EFI_ZBOOT is not set
# CONFIG_EFI_ARMSTUB_DTB_LOADER is not set
CONFIG_EFI_BOOTLOADER_CONTROL=y
# CONFIG_EFI_CAPSULE_LOADER is not set
# CONFIG_EFI_TEST is not set
# CONFIG_RESET_ATTACK_MITIGATION is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
# CONFIG_EFI_DISABLE_RUNTIME is not set
# CONFIG_EFI_COCO_SECRET is not set
# end of EFI (Extensible Firmware Interface) Support

CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_PSCI_CHECKER is not set
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_ARM_SMCCC_SOC_ID=y

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_GNSS=m
CONFIG_GNSS_SERIAL=m
CONFIG_GNSS_MTK_SERIAL=m
# CONFIG_GNSS_SIRF_SERIAL is not set
# CONFIG_GNSS_UBX_SERIAL is not set
# CONFIG_GNSS_USB is not set
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_OF_PARTS=m
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=m
CONFIG_MTD_BLOCK=m
# CONFIG_MTD_BLOCK_RO is not set

#
# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
#
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=m
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=m
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
CONFIG_MTD_CFI_INTELEXT=m
CONFIG_MTD_CFI_AMDSTD=m
CONFIG_MTD_CFI_STAA=m
CONFIG_MTD_CFI_UTIL=m
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=m
# CONFIG_MTD_PHYSMAP_COMPAT is not set
CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_PHYSMAP_VERSATILE is not set
# CONFIG_MTD_PHYSMAP_GEMINI is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_MCHP48L640 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
CONFIG_MTD_NAND_CORE=y
# CONFIG_MTD_ONENAND is not set
CONFIG_MTD_RAW_NAND=y

#
# Raw/parallel NAND flash controllers
#
# CONFIG_MTD_NAND_DENALI_PCI is not set
# CONFIG_MTD_NAND_DENALI_DT is not set
# CONFIG_MTD_NAND_CAFE is not set
# CONFIG_MTD_NAND_BRCMNAND is not set
# CONFIG_MTD_NAND_SUNXI is not set
# CONFIG_MTD_NAND_MXIC is not set
# CONFIG_MTD_NAND_GPIO is not set
# CONFIG_MTD_NAND_PLATFORM is not set
# CONFIG_MTD_NAND_CADENCE is not set
# CONFIG_MTD_NAND_ARASAN is not set
# CONFIG_MTD_NAND_INTEL_LGM is not set

#
# Misc
#
# CONFIG_MTD_NAND_NANDSIM is not set
# CONFIG_MTD_NAND_RICOH is not set
# CONFIG_MTD_NAND_DISKONCHIP is not set
# CONFIG_MTD_SPI_NAND is not set

#
# ECC engine support
#
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
CONFIG_MTD_NAND_ECC_SW_BCH=y
# CONFIG_MTD_NAND_ECC_MXIC is not set
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
# CONFIG_MTD_UBI_BLOCK is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_NULL_BLK=m
CONFIG_CDROM=y
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
CONFIG_ZRAM=m
CONFIG_ZRAM_DEF_COMP_LZORLE=y
# CONFIG_ZRAM_DEF_COMP_ZSTD is not set
# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
# CONFIG_ZRAM_DEF_COMP_LZO is not set
# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
# CONFIG_ZRAM_DEF_COMP_842 is not set
CONFIG_ZRAM_DEF_COMP="lzo-rle"
# CONFIG_ZRAM_WRITEBACK is not set
# CONFIG_ZRAM_TRACK_ENTRY_ACTIME is not set
# CONFIG_ZRAM_MEMORY_TRACKING is not set
# CONFIG_ZRAM_MULTI_COMP is not set
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_LOOP_MIN_COUNT=0
CONFIG_BLK_DEV_DRBD=m
# CONFIG_DRBD_FAULT_INJECTION is not set
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=m
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_CDROM_PKTCDVD=m
CONFIG_CDROM_PKTCDVD_BUFFERS=8
# CONFIG_CDROM_PKTCDVD_WCACHE is not set
CONFIG_ATA_OVER_ETH=m
CONFIG_VIRTIO_BLK=y
CONFIG_BLK_DEV_RBD=m
# CONFIG_BLK_DEV_UBLK is not set

#
# NVME Support
#
CONFIG_NVME_CORE=m
CONFIG_BLK_DEV_NVME=m
CONFIG_NVME_MULTIPATH=y
# CONFIG_NVME_VERBOSE_ERRORS is not set
# CONFIG_NVME_HWMON is not set
# CONFIG_NVME_FC is not set
# CONFIG_NVME_TCP is not set
# CONFIG_NVME_AUTH is not set
# CONFIG_NVME_TARGET is not set
# end of NVME Support

#
# Misc devices
#
CONFIG_SENSORS_LIS3LV02D=m
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
CONFIG_TIFM_CORE=y
CONFIG_TIFM_7XX1=m
# CONFIG_ICS932S401 is not set
CONFIG_ENCLOSURE_SERVICES=m
# CONFIG_HI6421V600_IRQ is not set
# CONFIG_HP_ILO is not set
CONFIG_APDS9802ALS=m
CONFIG_ISL29003=m
CONFIG_ISL29020=m
CONFIG_SENSORS_TSL2550=m
CONFIG_SENSORS_BH1770=m
CONFIG_SENSORS_APDS990X=m
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
# CONFIG_DW_XDATA_PCIE is not set
CONFIG_PCI_ENDPOINT_TEST=m
# CONFIG_XILINX_SDFEC is not set
# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_OPEN_DICE is not set
# CONFIG_VCPU_STALL_DETECTOR is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
CONFIG_EEPROM_AT24=m
# CONFIG_EEPROM_AT25 is not set
CONFIG_EEPROM_LEGACY=m
CONFIG_EEPROM_MAX6875=m
CONFIG_EEPROM_93CX6=m
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

CONFIG_CB710_CORE=y
# CONFIG_CB710_DEBUG is not set
CONFIG_CB710_DEBUG_ASSUMPTIONS=y

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline

CONFIG_SENSORS_LIS3_I2C=m
CONFIG_ALTERA_STAPL=m
# CONFIG_VMWARE_VMCI is not set
# CONFIG_GENWQE is not set
CONFIG_ECHO=m
# CONFIG_BCM_VK is not set
# CONFIG_MISC_ALCOR_PCI is not set
# CONFIG_MISC_RTSX_PCI is not set
# CONFIG_MISC_RTSX_USB is not set
CONFIG_UACCE=m
# CONFIG_PVPANIC is not set
# CONFIG_GP_PCI1XXXX is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
CONFIG_RAID_ATTRS=m
CONFIG_SCSI_COMMON=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_NETLINK=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=m
CONFIG_BLK_DEV_SR=y
CONFIG_CHR_DEV_SG=y
CONFIG_BLK_DEV_BSG=y
CONFIG_CHR_DEV_SCH=m
CONFIG_SCSI_ENCLOSURE=m
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y

#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=m
CONFIG_SCSI_FC_ATTRS=m
CONFIG_SCSI_ISCSI_ATTRS=m
CONFIG_SCSI_SAS_ATTRS=m
CONFIG_SCSI_SAS_LIBSAS=m
CONFIG_SCSI_SAS_ATA=y
CONFIG_SCSI_SAS_HOST_SMP=y
CONFIG_SCSI_SRP_ATTRS=m
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_ISCSI_BOOT_SYSFS=m
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
CONFIG_SCSI_BNX2_ISCSI=m
CONFIG_SCSI_BNX2X_FCOE=m
CONFIG_BE2ISCSI=m
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
CONFIG_SCSI_HPSA=m
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
CONFIG_SCSI_MVSAS=m
# CONFIG_SCSI_MVSAS_DEBUG is not set
CONFIG_SCSI_MVSAS_TASKLET=y
CONFIG_SCSI_MVUMI=m
# CONFIG_SCSI_ADVANSYS is not set
CONFIG_SCSI_ARCMSR=m
CONFIG_SCSI_ESAS2R=m
CONFIG_MEGARAID_NEWGEN=y
CONFIG_MEGARAID_MM=m
CONFIG_MEGARAID_MAILBOX=m
CONFIG_MEGARAID_LEGACY=m
CONFIG_MEGARAID_SAS=m
CONFIG_SCSI_MPT3SAS=m
CONFIG_SCSI_MPT2SAS_MAX_SGE=128
CONFIG_SCSI_MPT3SAS_MAX_SGE=128
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_MPI3MR is not set
# CONFIG_SCSI_SMARTPQI is not set
CONFIG_SCSI_HPTIOP=m
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
CONFIG_LIBFC=m
CONFIG_LIBFCOE=m
CONFIG_FCOE=m
CONFIG_SCSI_SNIC=m
# CONFIG_SCSI_SNIC_DEBUG_FS is not set
CONFIG_SCSI_DMX3191D=m
# CONFIG_SCSI_FDOMAIN_PCI is not set
# CONFIG_SCSI_IPS is not set
CONFIG_SCSI_INITIO=m
CONFIG_SCSI_INIA100=m
CONFIG_SCSI_STEX=m
CONFIG_SCSI_SYM53C8XX_2=m
CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
CONFIG_SCSI_SYM53C8XX_MMIO=y
CONFIG_SCSI_IPR=m
CONFIG_SCSI_IPR_TRACE=y
CONFIG_SCSI_IPR_DUMP=y
CONFIG_SCSI_QLOGIC_1280=m
CONFIG_SCSI_QLA_FC=m
CONFIG_TCM_QLA2XXX=m
# CONFIG_TCM_QLA2XXX_DEBUG is not set
CONFIG_SCSI_QLA_ISCSI=m
# CONFIG_SCSI_LPFC is not set
# CONFIG_SCSI_EFCT is not set
CONFIG_SCSI_DC395x=m
CONFIG_SCSI_AM53C974=m
CONFIG_SCSI_WD719X=m
CONFIG_SCSI_DEBUG=m
CONFIG_SCSI_PMCRAID=m
# CONFIG_SCSI_PM8001 is not set
# CONFIG_SCSI_BFA_FC is not set
CONFIG_SCSI_VIRTIO=y
CONFIG_SCSI_CHELSIO_FCOE=m
CONFIG_SCSI_DH=y
CONFIG_SCSI_DH_RDAC=m
CONFIG_SCSI_DH_HP_SW=m
CONFIG_SCSI_DH_EMC=m
CONFIG_SCSI_DH_ALUA=m
# end of SCSI device support

CONFIG_ATA=y
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_AHCI_DWC=y
CONFIG_AHCI_CEVA=m
CONFIG_AHCI_SUNXI=y
CONFIG_SATA_INIC162X=m
CONFIG_SATA_ACARD_AHCI=m
CONFIG_SATA_SIL24=y
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#
CONFIG_PDC_ADMA=m
CONFIG_SATA_QSTOR=m
CONFIG_SATA_SX4=m
CONFIG_ATA_BMDMA=y

#
# SATA SFF controllers with BMDMA
#
CONFIG_ATA_PIIX=y
# CONFIG_SATA_DWC is not set
CONFIG_SATA_MV=m
CONFIG_SATA_NV=m
CONFIG_SATA_PROMISE=m
CONFIG_SATA_SIL=m
CONFIG_SATA_SIS=m
CONFIG_SATA_SVW=m
CONFIG_SATA_ULI=m
CONFIG_SATA_VIA=m
CONFIG_SATA_VITESSE=m

#
# PATA SFF controllers with BMDMA
#
CONFIG_PATA_ALI=m
CONFIG_PATA_AMD=m
CONFIG_PATA_ARTOP=m
CONFIG_PATA_ATIIXP=m
CONFIG_PATA_ATP867X=m
CONFIG_PATA_CMD64X=m
CONFIG_PATA_CYPRESS=m
CONFIG_PATA_EFAR=m
CONFIG_PATA_HPT366=m
CONFIG_PATA_HPT37X=m
CONFIG_PATA_HPT3X2N=m
CONFIG_PATA_HPT3X3=m
# CONFIG_PATA_HPT3X3_DMA is not set
CONFIG_PATA_IT8213=m
CONFIG_PATA_IT821X=m
CONFIG_PATA_JMICRON=m
CONFIG_PATA_MARVELL=m
CONFIG_PATA_NETCELL=m
CONFIG_PATA_NINJA32=m
CONFIG_PATA_NS87415=m
CONFIG_PATA_OLDPIIX=m
CONFIG_PATA_OPTIDMA=m
CONFIG_PATA_PDC2027X=m
CONFIG_PATA_PDC_OLD=m
# CONFIG_PATA_RADISYS is not set
CONFIG_PATA_RDC=m
CONFIG_PATA_SCH=m
CONFIG_PATA_SERVERWORKS=m
CONFIG_PATA_SIL680=m
CONFIG_PATA_SIS=m
CONFIG_PATA_TOSHIBA=m
CONFIG_PATA_TRIFLEX=m
CONFIG_PATA_VIA=m
CONFIG_PATA_WINBOND=m

#
# PIO-only SFF controllers
#
CONFIG_PATA_CMD640_PCI=m
CONFIG_PATA_MPIIX=m
CONFIG_PATA_NS87410=m
CONFIG_PATA_OPTI=m
CONFIG_PATA_PLATFORM=y
CONFIG_PATA_OF_PLATFORM=y
# CONFIG_PATA_RZ1000 is not set

#
# Generic fallback / legacy drivers
#
# CONFIG_PATA_ACPI is not set
CONFIG_ATA_GENERIC=m
# CONFIG_PATA_LEGACY is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=y
CONFIG_MD_AUTODETECT=y
CONFIG_MD_BITMAP_FILE=y
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
CONFIG_MD_CLUSTER=m
CONFIG_BCACHE=m
# CONFIG_BCACHE_DEBUG is not set
# CONFIG_BCACHE_CLOSURES_DEBUG is not set
# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_DEBUG=y
CONFIG_DM_BUFIO=y
# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
# CONFIG_DM_UNSTRIPED is not set
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=y
CONFIG_DM_THIN_PROVISIONING=m
CONFIG_DM_CACHE=m
CONFIG_DM_CACHE_SMQ=m
CONFIG_DM_WRITECACHE=m
# CONFIG_DM_EBS is not set
# CONFIG_DM_ERA is not set
# CONFIG_DM_CLONE is not set
CONFIG_DM_MIRROR=y
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=y
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
# CONFIG_DM_MULTIPATH_HST is not set
# CONFIG_DM_MULTIPATH_IOA is not set
CONFIG_DM_DELAY=m
CONFIG_DM_DUST=m
CONFIG_DM_INIT=y
CONFIG_DM_UEVENT=y
CONFIG_DM_FLAKEY=m
CONFIG_DM_VERITY=m
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
CONFIG_DM_VERITY_FEC=y
CONFIG_DM_SWITCH=m
CONFIG_DM_LOG_WRITES=m
CONFIG_DM_INTEGRITY=m
CONFIG_DM_ZONED=m
CONFIG_DM_AUDIT=y
CONFIG_TARGET_CORE=m
CONFIG_TCM_IBLOCK=m
CONFIG_TCM_FILEIO=m
CONFIG_TCM_PSCSI=m
CONFIG_TCM_USER2=m
CONFIG_LOOPBACK_TARGET=m
CONFIG_TCM_FC=m
CONFIG_ISCSI_TARGET=m
# CONFIG_REMOTE_TARGET is not set
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
CONFIG_FIREWIRE_NOSY=m
# end of IEEE 1394 (FireWire) support

CONFIG_NETDEVICES=y
CONFIG_MII=m
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_WIREGUARD=m
# CONFIG_WIREGUARD_DEBUG is not set
CONFIG_EQUALIZER=m
CONFIG_NET_FC=y
CONFIG_IFB=m
CONFIG_NET_TEAM=m
CONFIG_NET_TEAM_MODE_BROADCAST=m
CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
CONFIG_NET_TEAM_MODE_RANDOM=m
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
CONFIG_NET_TEAM_MODE_LOADBALANCE=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=m
CONFIG_IPVTAP=m
CONFIG_VXLAN=m
CONFIG_GENEVE=m
# CONFIG_BAREUDP is not set
# CONFIG_GTP is not set
# CONFIG_AMT is not set
# CONFIG_MACSEC is not set
CONFIG_NETCONSOLE=m
CONFIG_NETCONSOLE_DYNAMIC=y
# CONFIG_NETCONSOLE_EXTENDED_LOG is not set
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=m
CONFIG_TAP=m
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_NLMON=m
CONFIG_NET_VRF=m
# CONFIG_VSOCKMON is not set
# CONFIG_ARCNET is not set
# CONFIG_ATM_DRIVERS is not set

#
# Distributed Switch Architecture drivers
#
CONFIG_B53=m
# CONFIG_B53_SPI_DRIVER is not set
# CONFIG_B53_MDIO_DRIVER is not set
# CONFIG_B53_MMAP_DRIVER is not set
# CONFIG_B53_SRAB_DRIVER is not set
# CONFIG_B53_SERDES is not set
CONFIG_NET_DSA_BCM_SF2=m
# CONFIG_NET_DSA_LOOP is not set
# CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK is not set
# CONFIG_NET_DSA_LANTIQ_GSWIP is not set
# CONFIG_NET_DSA_MT7530 is not set
CONFIG_NET_DSA_MV88E6060=m
# CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON is not set
CONFIG_NET_DSA_MV88E6XXX=m
CONFIG_NET_DSA_MV88E6XXX_PTP=y
# CONFIG_NET_DSA_MSCC_OCELOT_EXT is not set
# CONFIG_NET_DSA_MSCC_SEVILLE is not set
# CONFIG_NET_DSA_AR9331 is not set
CONFIG_NET_DSA_QCA8K=m
# CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT is not set
# CONFIG_NET_DSA_SJA1105 is not set
# CONFIG_NET_DSA_XRS700X_I2C is not set
# CONFIG_NET_DSA_XRS700X_MDIO is not set
# CONFIG_NET_DSA_REALTEK is not set
# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set
# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set
# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set
# end of Distributed Switch Architecture drivers

CONFIG_ETHERNET=y
CONFIG_MDIO=m
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
CONFIG_NET_VENDOR_AGERE=y
CONFIG_ET131X=m
CONFIG_NET_VENDOR_ALACRITECH=y
# CONFIG_SLICOSS is not set
CONFIG_NET_VENDOR_ALLWINNER=y
# CONFIG_SUN4I_EMAC is not set
CONFIG_NET_VENDOR_ALTEON=y
CONFIG_ACENIC=m
# CONFIG_ACENIC_OMIT_TIGON_I is not set
CONFIG_ALTERA_TSE=m
CONFIG_NET_VENDOR_AMAZON=y
# CONFIG_ENA_ETHERNET is not set
CONFIG_NET_VENDOR_AMD=y
CONFIG_AMD8111_ETH=m
CONFIG_PCNET32=m
CONFIG_AMD_XGBE=m
# CONFIG_AMD_XGBE_DCB is not set
# CONFIG_PDS_CORE is not set
CONFIG_NET_VENDOR_AQUANTIA=y
CONFIG_AQTION=m
CONFIG_NET_VENDOR_ARC=y
CONFIG_NET_VENDOR_ASIX=y
# CONFIG_SPI_AX88796C is not set
CONFIG_NET_VENDOR_ATHEROS=y
CONFIG_ATL2=m
CONFIG_ATL1=m
CONFIG_ATL1E=m
CONFIG_ATL1C=m
CONFIG_ALX=m
CONFIG_NET_VENDOR_BROADCOM=y
CONFIG_B44=m
CONFIG_B44_PCI_AUTOSELECT=y
CONFIG_B44_PCICORE_AUTOSELECT=y
CONFIG_B44_PCI=y
CONFIG_BCMGENET=m
CONFIG_BNX2=m
CONFIG_CNIC=m
CONFIG_TIGON3=m
CONFIG_TIGON3_HWMON=y
CONFIG_BNX2X=m
CONFIG_BNX2X_SRIOV=y
# CONFIG_SYSTEMPORT is not set
# CONFIG_BNXT is not set
CONFIG_NET_VENDOR_CADENCE=y
CONFIG_MACB=m
CONFIG_MACB_USE_HWSTAMP=y
# CONFIG_MACB_PCI is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
CONFIG_NET_VENDOR_CORTINA=y
# CONFIG_GEMINI_ETHERNET is not set
CONFIG_NET_VENDOR_DAVICOM=y
# CONFIG_DM9051 is not set
CONFIG_DNET=m
# CONFIG_NET_VENDOR_DEC is not set
CONFIG_NET_VENDOR_DLINK=y
CONFIG_DL2K=m
CONFIG_SUNDANCE=m
# CONFIG_SUNDANCE_MMIO is not set
# CONFIG_NET_VENDOR_EMULEX is not set
CONFIG_NET_VENDOR_ENGLEDER=y
# CONFIG_TSNEP is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
CONFIG_NET_VENDOR_FUNGIBLE=y
# CONFIG_FUN_ETH is not set
CONFIG_NET_VENDOR_GOOGLE=y
# CONFIG_GVE is not set
CONFIG_NET_VENDOR_HISILICON=y
CONFIG_HIX5HD2_GMAC=m
# CONFIG_HISI_FEMAC is not set
CONFIG_HIP04_ETH=m
# CONFIG_HI13X1_GMAC is not set
CONFIG_HNS_MDIO=m
CONFIG_HNS=m
CONFIG_HNS_DSAF=m
CONFIG_HNS_ENET=m
# CONFIG_HNS3 is not set
CONFIG_NET_VENDOR_HUAWEI=y
# CONFIG_HINIC is not set
# CONFIG_NET_VENDOR_I825XX is not set
CONFIG_NET_VENDOR_INTEL=y
CONFIG_E100=m
CONFIG_E1000=m
CONFIG_E1000E=m
CONFIG_IGB=m
CONFIG_IGB_HWMON=y
CONFIG_IGBVF=m
CONFIG_IXGBE=m
CONFIG_IXGBE_HWMON=y
CONFIG_IXGBE_DCB=y
CONFIG_IXGBEVF=m
CONFIG_I40E=m
# CONFIG_I40E_DCB is not set
CONFIG_IAVF=m
CONFIG_I40EVF=m
# CONFIG_ICE is not set
CONFIG_FM10K=m
# CONFIG_IGC is not set
CONFIG_JME=m
CONFIG_NET_VENDOR_ADI=y
# CONFIG_ADIN1110 is not set
CONFIG_NET_VENDOR_LITEX=y
# CONFIG_LITEX_LITEETH is not set
CONFIG_NET_VENDOR_MARVELL=y
CONFIG_MVMDIO=m
CONFIG_SKGE=m
# CONFIG_SKGE_DEBUG is not set
CONFIG_SKGE_GENESIS=y
CONFIG_SKY2=m
# CONFIG_SKY2_DEBUG is not set
# CONFIG_OCTEONTX2_AF is not set
# CONFIG_OCTEONTX2_PF is not set
# CONFIG_OCTEON_EP is not set
# CONFIG_PRESTERA is not set
CONFIG_NET_VENDOR_MELLANOX=y
CONFIG_MLX4_EN=m
CONFIG_MLX4_EN_DCB=y
CONFIG_MLX4_CORE=m
CONFIG_MLX4_DEBUG=y
CONFIG_MLX4_CORE_GEN2=y
CONFIG_MLX5_CORE=m
# CONFIG_MLX5_FPGA is not set
CONFIG_MLX5_CORE_EN=y
CONFIG_MLX5_EN_ARFS=y
CONFIG_MLX5_EN_RXNFC=y
CONFIG_MLX5_MPFS=y
# CONFIG_MLX5_ESWITCH is not set
# CONFIG_MLX5_CORE_EN_DCB is not set
# CONFIG_MLX5_CORE_IPOIB is not set
# CONFIG_MLX5_SF is not set
# CONFIG_MLXSW_CORE is not set
# CONFIG_MLXFW is not set
# CONFIG_MLXBF_GIGE is not set
CONFIG_NET_VENDOR_MICREL=y
# CONFIG_KS8842 is not set
# CONFIG_KS8851 is not set
# CONFIG_KS8851_MLL is not set
CONFIG_KSZ884X_PCI=m
CONFIG_NET_VENDOR_MICROCHIP=y
# CONFIG_ENC28J60 is not set
# CONFIG_ENCX24J600 is not set
# CONFIG_LAN743X is not set
# CONFIG_LAN966X_SWITCH is not set
# CONFIG_VCAP is not set
CONFIG_NET_VENDOR_MICROSEMI=y
# CONFIG_MSCC_OCELOT_SWITCH is not set
CONFIG_NET_VENDOR_MICROSOFT=y
CONFIG_NET_VENDOR_MYRI=y
CONFIG_MYRI10GE=m
CONFIG_FEALNX=m
CONFIG_NET_VENDOR_NI=y
# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
CONFIG_NET_VENDOR_NATSEMI=y
CONFIG_NATSEMI=m
CONFIG_NS83820=m
CONFIG_NET_VENDOR_NETERION=y
# CONFIG_S2IO is not set
CONFIG_NET_VENDOR_NETRONOME=y
# CONFIG_NFP is not set
CONFIG_NET_VENDOR_8390=y
CONFIG_NE2K_PCI=m
CONFIG_NET_VENDOR_NVIDIA=y
CONFIG_FORCEDETH=m
CONFIG_NET_VENDOR_OKI=y
CONFIG_ETHOC=m
CONFIG_NET_VENDOR_PACKET_ENGINES=y
CONFIG_HAMACHI=m
CONFIG_YELLOWFIN=m
CONFIG_NET_VENDOR_PENSANDO=y
# CONFIG_IONIC is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_BROCADE is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCA7000_UART is not set
# CONFIG_QCOM_EMAC is not set
CONFIG_RMNET=m
CONFIG_NET_VENDOR_RDC=y
CONFIG_R6040=m
CONFIG_NET_VENDOR_REALTEK=y
CONFIG_8139CP=m
CONFIG_8139TOO=m
# CONFIG_8139TOO_PIO is not set
# CONFIG_8139TOO_TUNE_TWISTER is not set
CONFIG_8139TOO_8129=y
# CONFIG_8139_OLD_RX_RESET is not set
CONFIG_R8169=m
# CONFIG_NET_VENDOR_RENESAS is not set
CONFIG_NET_VENDOR_ROCKER=y
CONFIG_ROCKER=m
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
CONFIG_NET_VENDOR_SILAN=y
CONFIG_SC92031=m
CONFIG_NET_VENDOR_SIS=y
CONFIG_SIS900=m
CONFIG_SIS190=m
CONFIG_NET_VENDOR_SOLARFLARE=y
# CONFIG_SFC is not set
# CONFIG_SFC_FALCON is not set
# CONFIG_SFC_SIENA is not set
CONFIG_NET_VENDOR_SMSC=y
CONFIG_SMC91X=m
CONFIG_EPIC100=m
CONFIG_SMSC911X=m
CONFIG_SMSC9420=m
CONFIG_NET_VENDOR_SOCIONEXT=y
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=m
# CONFIG_STMMAC_SELFTESTS is not set
CONFIG_STMMAC_PLATFORM=m
CONFIG_DWMAC_DWC_QOS_ETH=m
CONFIG_DWMAC_GENERIC=m
CONFIG_DWMAC_SUNXI=m
CONFIG_DWMAC_SUN8I=m
# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
CONFIG_NET_VENDOR_SYNOPSYS=y
# CONFIG_DWC_XLGMAC is not set
CONFIG_NET_VENDOR_TEHUTI=y
CONFIG_TEHUTI=m
CONFIG_NET_VENDOR_TI=y
# CONFIG_TI_CPSW_PHY_SEL is not set
# CONFIG_TLAN is not set
CONFIG_NET_VENDOR_VERTEXCOM=y
# CONFIG_MSE102X is not set
CONFIG_NET_VENDOR_VIA=y
CONFIG_VIA_RHINE=m
CONFIG_VIA_RHINE_MMIO=y
CONFIG_VIA_VELOCITY=m
# CONFIG_NET_VENDOR_WANGXUN is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_NET_VENDOR_XILINX=y
# CONFIG_XILINX_EMACLITE is not set
# CONFIG_XILINX_AXI_EMAC is not set
# CONFIG_XILINX_LL_TEMAC is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
CONFIG_NET_SB1000=y
CONFIG_PHYLINK=m
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_PHYLIB_LEDS=y
CONFIG_FIXED_PHY=y
CONFIG_SFP=m

#
# MII PHY device drivers
#
CONFIG_AC200_PHY=y
CONFIG_AMD_PHY=m
# CONFIG_ADIN_PHY is not set
# CONFIG_ADIN1100_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
CONFIG_AX88796B_PHY=m
CONFIG_BROADCOM_PHY=m
# CONFIG_BCM54140_PHY is not set
CONFIG_BCM7XXX_PHY=m
# CONFIG_BCM84881_PHY is not set
CONFIG_BCM87XX_PHY=m
CONFIG_BCM_NET_PHYLIB=m
CONFIG_BCM_NET_PHYPTP=m
CONFIG_CICADA_PHY=m
# CONFIG_CORTINA_PHY is not set
CONFIG_DAVICOM_PHY=m
CONFIG_ICPLUS_PHY=m
CONFIG_LXT_PHY=m
# CONFIG_INTEL_XWAY_PHY is not set
CONFIG_LSI_ET1011C_PHY=m
CONFIG_MARVELL_PHY=m
CONFIG_MARVELL_10G_PHY=m
# CONFIG_MARVELL_88Q2XXX_PHY is not set
# CONFIG_MARVELL_88X2222_PHY is not set
# CONFIG_MAXLINEAR_GPHY is not set
# CONFIG_MEDIATEK_GE_PHY is not set
CONFIG_MICREL_PHY=m
# CONFIG_MICROCHIP_T1S_PHY is not set
CONFIG_MICROCHIP_PHY=m
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
# CONFIG_MOTORCOMM_PHY is not set
CONFIG_NATIONAL_PHY=m
# CONFIG_NXP_CBTX_PHY is not set
# CONFIG_NXP_C45_TJA11XX_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
# CONFIG_NCN26000_PHY is not set
CONFIG_AT803X_PHY=y
CONFIG_QSEMI_PHY=m
CONFIG_REALTEK_PHY=m
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
CONFIG_SMSC_PHY=m
CONFIG_STE10XP=m
# CONFIG_TERANETICS_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
CONFIG_DP83848_PHY=m
CONFIG_DP83867_PHY=m
# CONFIG_DP83869_PHY is not set
# CONFIG_DP83TD510_PHY is not set
CONFIG_VITESSE_PHY=m
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_PSE_CONTROLLER is not set
CONFIG_CAN_DEV=m
CONFIG_CAN_VCAN=m
CONFIG_CAN_VXCAN=m
# CONFIG_CAN_NETLINK is not set
# CONFIG_CAN_DEBUG_DEVICES is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_FWNODE_MDIO=y
CONFIG_OF_MDIO=y
CONFIG_ACPI_MDIO=y
CONFIG_MDIO_DEVRES=y
# CONFIG_MDIO_SUN4I is not set
CONFIG_MDIO_BITBANG=m
CONFIG_MDIO_BCM_UNIMAC=y
# CONFIG_MDIO_GPIO is not set
# CONFIG_MDIO_HISI_FEMAC is not set
CONFIG_MDIO_I2C=m
# CONFIG_MDIO_MVUSB is not set
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_OCTEON is not set
# CONFIG_MDIO_IPQ4019 is not set
# CONFIG_MDIO_IPQ8064 is not set
CONFIG_MDIO_REGMAP=m
# CONFIG_MDIO_THUNDER is not set

#
# MDIO Multiplexers
#
CONFIG_MDIO_BUS_MUX=m
CONFIG_MDIO_BUS_MUX_GPIO=m
# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
CONFIG_MDIO_BUS_MUX_MMIOREG=m

#
# PCS device drivers
#
CONFIG_PCS_XPCS=m
CONFIG_PCS_LYNX=m
# end of PCS device drivers

CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOATM=m
CONFIG_PPPOE=m
# CONFIG_PPPOE_HASH_BITS_1 is not set
# CONFIG_PPPOE_HASH_BITS_2 is not set
CONFIG_PPPOE_HASH_BITS_4=y
# CONFIG_PPPOE_HASH_BITS_8 is not set
CONFIG_PPPOE_HASH_BITS=4
CONFIG_PPTP=m
CONFIG_PPPOL2TP=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_SLIP=m
CONFIG_SLHC=m
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_SMART=y
# CONFIG_SLIP_MODE_SLIP6 is not set
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_AX8817X=m
CONFIG_USB_NET_AX88179_178A=m
CONFIG_USB_NET_CDCETHER=m
CONFIG_USB_NET_CDC_EEM=m
CONFIG_USB_NET_CDC_NCM=m
CONFIG_USB_NET_HUAWEI_CDC_NCM=m
CONFIG_USB_NET_CDC_MBIM=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9700=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
CONFIG_USB_NET_CDC_SUBSET=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
CONFIG_USB_EPSON2888=y
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=m
CONFIG_USB_NET_CX82310_ETH=m
CONFIG_USB_NET_KALMIA=m
CONFIG_USB_NET_QMI_WWAN=m
CONFIG_USB_HSO=m
CONFIG_USB_NET_INT51X1=m
CONFIG_USB_IPHETH=m
CONFIG_USB_SIERRA_NET=m
CONFIG_USB_VL600=m
CONFIG_USB_NET_CH9200=m
# CONFIG_USB_NET_AQC111 is not set
CONFIG_USB_RTL8153_ECM=m
CONFIG_WLAN=y
CONFIG_WLAN_VENDOR_ADMTEK=y
CONFIG_ADM8211=m
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
# CONFIG_ATH_DEBUG is not set
CONFIG_ATH5K=m
CONFIG_ATH5K_DEBUG=y
CONFIG_ATH5K_PCI=y
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_COMMON_DEBUG=y
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=m
CONFIG_ATH9K_PCI=y
CONFIG_ATH9K_AHB=y
CONFIG_ATH9K_DEBUGFS=y
# CONFIG_ATH9K_STATION_STATISTICS is not set
# CONFIG_ATH9K_DYNACK is not set
# CONFIG_ATH9K_WOW is not set
CONFIG_ATH9K_RFKILL=y
# CONFIG_ATH9K_CHANNEL_CONTEXT is not set
CONFIG_ATH9K_PCOEM=y
# CONFIG_ATH9K_PCI_NO_EEPROM is not set
CONFIG_ATH9K_HTC=m
# CONFIG_ATH9K_HTC_DEBUGFS is not set
CONFIG_ATH9K_HWRNG=y
CONFIG_ATH9K_COMMON_SPECTRAL=y
CONFIG_CARL9170=m
CONFIG_CARL9170_LEDS=y
# CONFIG_CARL9170_DEBUGFS is not set
CONFIG_CARL9170_WPC=y
# CONFIG_CARL9170_HWRNG is not set
CONFIG_ATH6KL=m
CONFIG_ATH6KL_SDIO=m
CONFIG_ATH6KL_USB=m
CONFIG_ATH6KL_DEBUG=y
CONFIG_AR5523=m
CONFIG_WIL6210=m
CONFIG_WIL6210_ISR_COR=y
CONFIG_WIL6210_DEBUGFS=y
CONFIG_ATH10K=m
CONFIG_ATH10K_CE=y
CONFIG_ATH10K_PCI=m
# CONFIG_ATH10K_AHB is not set
# CONFIG_ATH10K_SDIO is not set
# CONFIG_ATH10K_USB is not set
# CONFIG_ATH10K_DEBUG is not set
CONFIG_ATH10K_DEBUGFS=y
# CONFIG_ATH10K_SPECTRAL is not set
CONFIG_WCN36XX=m
# CONFIG_WCN36XX_DEBUGFS is not set
# CONFIG_ATH11K is not set
# CONFIG_ATH12K is not set
CONFIG_WLAN_VENDOR_ATMEL=y
CONFIG_ATMEL=m
CONFIG_PCI_ATMEL=m
CONFIG_AT76C50X_USB=m
CONFIG_WLAN_VENDOR_BROADCOM=y
CONFIG_B43=m
CONFIG_B43_BCMA=y
CONFIG_B43_SSB=y
CONFIG_B43_BUSES_BCMA_AND_SSB=y
# CONFIG_B43_BUSES_BCMA is not set
# CONFIG_B43_BUSES_SSB is not set
CONFIG_B43_PCI_AUTOSELECT=y
CONFIG_B43_PCICORE_AUTOSELECT=y
CONFIG_B43_SDIO=y
CONFIG_B43_BCMA_PIO=y
CONFIG_B43_PIO=y
CONFIG_B43_PHY_G=y
CONFIG_B43_PHY_N=y
CONFIG_B43_PHY_LP=y
CONFIG_B43_PHY_HT=y
CONFIG_B43_LEDS=y
CONFIG_B43_HWRNG=y
CONFIG_B43_DEBUG=y
CONFIG_B43LEGACY=m
CONFIG_B43LEGACY_PCI_AUTOSELECT=y
CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
CONFIG_B43LEGACY_LEDS=y
CONFIG_B43LEGACY_HWRNG=y
CONFIG_B43LEGACY_DEBUG=y
CONFIG_B43LEGACY_DMA=y
CONFIG_B43LEGACY_PIO=y
CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
# CONFIG_B43LEGACY_DMA_MODE is not set
# CONFIG_B43LEGACY_PIO_MODE is not set
CONFIG_BRCMUTIL=m
CONFIG_BRCMSMAC=m
CONFIG_BRCMSMAC_LEDS=y
CONFIG_BRCMFMAC=m
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_PROTO_MSGBUF=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
CONFIG_BRCMFMAC_PCIE=y
# CONFIG_BRCMDBG is not set
CONFIG_WLAN_VENDOR_CISCO=y
# CONFIG_AIRO is not set
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_IPW2100=m
CONFIG_IPW2100_MONITOR=y
# CONFIG_IPW2100_DEBUG is not set
CONFIG_IPW2200=m
CONFIG_IPW2200_MONITOR=y
CONFIG_IPW2200_RADIOTAP=y
CONFIG_IPW2200_PROMISCUOUS=y
CONFIG_IPW2200_QOS=y
# CONFIG_IPW2200_DEBUG is not set
CONFIG_LIBIPW=m
# CONFIG_LIBIPW_DEBUG is not set
CONFIG_IWLEGACY=m
CONFIG_IWL4965=m
CONFIG_IWL3945=m

#
# iwl3945 / iwl4965 Debugging Options
#
CONFIG_IWLEGACY_DEBUG=y
CONFIG_IWLEGACY_DEBUGFS=y
# end of iwl3945 / iwl4965 Debugging Options

CONFIG_IWLWIFI=m
CONFIG_IWLWIFI_LEDS=y
CONFIG_IWLDVM=m
CONFIG_IWLMVM=m
CONFIG_IWLWIFI_OPMODE_MODULAR=y

#
# Debugging Options
#
CONFIG_IWLWIFI_DEBUG=y
CONFIG_IWLWIFI_DEBUGFS=y
# end of Debugging Options

CONFIG_WLAN_VENDOR_INTERSIL=y
CONFIG_HOSTAP=m
CONFIG_HOSTAP_FIRMWARE=y
# CONFIG_HOSTAP_FIRMWARE_NVRAM is not set
CONFIG_HOSTAP_PLX=m
CONFIG_HOSTAP_PCI=m
CONFIG_HERMES=m
CONFIG_HERMES_PRISM=y
CONFIG_HERMES_CACHE_FW_ON_INIT=y
CONFIG_PLX_HERMES=m
CONFIG_TMD_HERMES=m
CONFIG_NORTEL_HERMES=m
CONFIG_PCI_HERMES=m
CONFIG_ORINOCO_USB=m
CONFIG_P54_COMMON=m
CONFIG_P54_USB=m
CONFIG_P54_PCI=m
# CONFIG_P54_SPI is not set
CONFIG_P54_LEDS=y
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_USB=m
CONFIG_LIBERTAS_SDIO=m
# CONFIG_LIBERTAS_SPI is not set
# CONFIG_LIBERTAS_DEBUG is not set
CONFIG_LIBERTAS_MESH=y
CONFIG_LIBERTAS_THINFIRM=m
# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
CONFIG_LIBERTAS_THINFIRM_USB=m
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_SDIO=m
CONFIG_MWIFIEX_PCIE=m
CONFIG_MWIFIEX_USB=m
CONFIG_MWL8K=m
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=m
CONFIG_MT76_CORE=m
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=m
CONFIG_MT76x02_LIB=m
CONFIG_MT76x02_USB=m
CONFIG_MT76_CONNAC_LIB=m
CONFIG_MT76x0_COMMON=m
CONFIG_MT76x0U=m
CONFIG_MT76x0E=m
CONFIG_MT76x2_COMMON=m
CONFIG_MT76x2E=m
CONFIG_MT76x2U=m
CONFIG_MT7603E=m
CONFIG_MT7615_COMMON=m
CONFIG_MT7615E=m
# CONFIG_MT7663U is not set
# CONFIG_MT7663S is not set
# CONFIG_MT7915E is not set
# CONFIG_MT7921E is not set
# CONFIG_MT7921S is not set
# CONFIG_MT7921U is not set
# CONFIG_MT7996E is not set
CONFIG_WLAN_VENDOR_MICROCHIP=y
# CONFIG_WILC1000_SDIO is not set
# CONFIG_WILC1000_SPI is not set
# CONFIG_WLAN_VENDOR_PURELIFI is not set
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=m
CONFIG_RT2400PCI=m
CONFIG_RT2500PCI=m
CONFIG_RT61PCI=m
CONFIG_RT2800PCI=m
CONFIG_RT2800PCI_RT33XX=y
CONFIG_RT2800PCI_RT35XX=y
CONFIG_RT2800PCI_RT53XX=y
CONFIG_RT2800PCI_RT3290=y
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
CONFIG_RT2800USB_RT33XX=y
CONFIG_RT2800USB_RT35XX=y
CONFIG_RT2800USB_RT3573=y
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
CONFIG_RT2800USB_UNKNOWN=y
CONFIG_RT2800_LIB=m
CONFIG_RT2800_LIB_MMIO=m
CONFIG_RT2X00_LIB_MMIO=m
CONFIG_RT2X00_LIB_PCI=m
CONFIG_RT2X00_LIB_USB=m
CONFIG_RT2X00_LIB=m
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
CONFIG_RT2X00_LIB_DEBUGFS=y
# CONFIG_RT2X00_DEBUG is not set
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_RTL8180=m
CONFIG_RTL8187=m
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=m
CONFIG_RTL8192CE=m
CONFIG_RTL8192SE=m
CONFIG_RTL8192DE=m
CONFIG_RTL8723AE=m
CONFIG_RTL8723BE=m
CONFIG_RTL8188EE=m
CONFIG_RTL8192EE=m
CONFIG_RTL8821AE=m
CONFIG_RTL8192CU=m
CONFIG_RTLWIFI=m
CONFIG_RTLWIFI_PCI=m
CONFIG_RTLWIFI_USB=m
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8723_COMMON=m
CONFIG_RTLBTCOEXIST=m
CONFIG_RTL8XXXU=m
# CONFIG_RTL8XXXU_UNTESTED is not set
# CONFIG_RTW88 is not set
# CONFIG_RTW89 is not set
CONFIG_WLAN_VENDOR_RSI=y
CONFIG_RSI_91X=m
CONFIG_RSI_DEBUGFS=y
CONFIG_RSI_SDIO=m
CONFIG_RSI_USB=m
CONFIG_RSI_COEX=y
# CONFIG_WLAN_VENDOR_SILABS is not set
CONFIG_WLAN_VENDOR_ST=y
CONFIG_CW1200=m
CONFIG_CW1200_WLAN_SDIO=m
# CONFIG_CW1200_WLAN_SPI is not set
CONFIG_WLAN_VENDOR_TI=y
CONFIG_WL1251=m
CONFIG_WL1251_SPI=m
CONFIG_WL1251_SDIO=m
CONFIG_WL12XX=m
CONFIG_WL18XX=m
CONFIG_WLCORE=m
CONFIG_WLCORE_SPI=m
CONFIG_WLCORE_SDIO=m
CONFIG_WLAN_VENDOR_ZYDAS=y
CONFIG_USB_ZD1201=m
CONFIG_ZD1211RW=m
# CONFIG_ZD1211RW_DEBUG is not set
CONFIG_WLAN_VENDOR_QUANTENNA=y
CONFIG_QTNFMAC=m
CONFIG_QTNFMAC_PCIE=m
CONFIG_USB_NET_RNDIS_WLAN=m
CONFIG_MAC80211_HWSIM=m
# CONFIG_VIRT_WIFI is not set
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
# CONFIG_IEEE802154_AT86RF230 is not set
# CONFIG_IEEE802154_MRF24J40 is not set
# CONFIG_IEEE802154_CC2520 is not set
CONFIG_IEEE802154_ATUSB=m
# CONFIG_IEEE802154_ADF7242 is not set
# CONFIG_IEEE802154_CA8210 is not set
# CONFIG_IEEE802154_MCR20A is not set
# CONFIG_IEEE802154_HWSIM is not set

#
# Wireless WAN
#
# CONFIG_WWAN is not set
# end of Wireless WAN

# CONFIG_VMXNET3 is not set
# CONFIG_FUJITSU_ES is not set
# CONFIG_NETDEVSIM is not set
CONFIG_NET_FAILOVER=m
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=m
CONFIG_INPUT_SPARSEKMAP=m
CONFIG_INPUT_MATRIXKMAP=y
CONFIG_INPUT_VIVALDIFMAP=y

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=m
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ADC=m
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=m
CONFIG_KEYBOARD_GPIO_POLLED=m
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_PINEPHONE is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_SUN4I_LRADC is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
CONFIG_KEYBOARD_CROS_EC=y
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_KEYBOARD_CYPRESS_SF is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
CONFIG_MOUSE_PS2_SENTELIC=y
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_SMBUS=y
CONFIG_MOUSE_SERIAL=m
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=m
CONFIG_MOUSE_ELAN_I2C=y
CONFIG_MOUSE_ELAN_I2C_I2C=y
CONFIG_MOUSE_ELAN_I2C_SMBUS=y
CONFIG_MOUSE_VSXXXAA=m
# CONFIG_MOUSE_GPIO is not set
CONFIG_MOUSE_SYNAPTICS_I2C=m
CONFIG_MOUSE_SYNAPTICS_USB=m
CONFIG_INPUT_JOYSTICK=y
# CONFIG_JOYSTICK_ANALOG is not set
# CONFIG_JOYSTICK_A3D is not set
# CONFIG_JOYSTICK_ADC is not set
# CONFIG_JOYSTICK_ADI is not set
# CONFIG_JOYSTICK_COBRA is not set
# CONFIG_JOYSTICK_GF2K is not set
# CONFIG_JOYSTICK_GRIP is not set
# CONFIG_JOYSTICK_GRIP_MP is not set
# CONFIG_JOYSTICK_GUILLEMOT is not set
# CONFIG_JOYSTICK_INTERACT is not set
# CONFIG_JOYSTICK_SIDEWINDER is not set
# CONFIG_JOYSTICK_TMDC is not set
CONFIG_JOYSTICK_IFORCE=m
CONFIG_JOYSTICK_IFORCE_USB=m
CONFIG_JOYSTICK_IFORCE_232=m
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
CONFIG_JOYSTICK_STINGER=m
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
# CONFIG_JOYSTICK_AS5011 is not set
# CONFIG_JOYSTICK_JOYDUMP is not set
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
# CONFIG_JOYSTICK_PSXPAD_SPI is not set
# CONFIG_JOYSTICK_PXRC is not set
# CONFIG_JOYSTICK_QWIIC is not set
# CONFIG_JOYSTICK_FSIA6B is not set
# CONFIG_JOYSTICK_SENSEHAT is not set
CONFIG_INPUT_TABLET=y
CONFIG_TABLET_USB_ACECAD=m
CONFIG_TABLET_USB_AIPTEK=m
CONFIG_TABLET_USB_HANWANG=m
CONFIG_TABLET_USB_KBTAB=m
CONFIG_TABLET_USB_PEGASUS=m
CONFIG_TABLET_SERIAL_WACOM4=m
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_AD7877 is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ADC is not set
# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_BU21029 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 is not set
# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP5 is not set
CONFIG_TOUCHSCREEN_DYNAPRO=m
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
CONFIG_TOUCHSCREEN_EETI=m
CONFIG_TOUCHSCREEN_EGALAX=m
# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
# CONFIG_TOUCHSCREEN_EXC3000 is not set
CONFIG_TOUCHSCREEN_FUJITSU=m
# CONFIG_TOUCHSCREEN_GOODIX is not set
# CONFIG_TOUCHSCREEN_HIDEEP is not set
# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set
# CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set
CONFIG_TOUCHSCREEN_ILI210X=m
# CONFIG_TOUCHSCREEN_ILITEK is not set
# CONFIG_TOUCHSCREEN_S6SY761 is not set
CONFIG_TOUCHSCREEN_GUNZE=m
# CONFIG_TOUCHSCREEN_EKTF2127 is not set
CONFIG_TOUCHSCREEN_ELAN=m
CONFIG_TOUCHSCREEN_ELO=m
CONFIG_TOUCHSCREEN_WACOM_W8001=m
CONFIG_TOUCHSCREEN_WACOM_I2C=m
# CONFIG_TOUCHSCREEN_MAX11801 is not set
CONFIG_TOUCHSCREEN_MCS5000=m
CONFIG_TOUCHSCREEN_MMS114=m
# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
# CONFIG_TOUCHSCREEN_MSG2638 is not set
CONFIG_TOUCHSCREEN_MTOUCH=m
# CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS is not set
# CONFIG_TOUCHSCREEN_IMAGIS is not set
# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
CONFIG_TOUCHSCREEN_INEXIO=m
CONFIG_TOUCHSCREEN_PENMOUNT=m
CONFIG_TOUCHSCREEN_EDT_FT5X06=m
CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
CONFIG_TOUCHSCREEN_TOUCHWIN=m
CONFIG_TOUCHSCREEN_PIXCIR=m
# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
# CONFIG_TOUCHSCREEN_WM97XX is not set
CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
CONFIG_TOUCHSCREEN_TOUCHIT213=m
CONFIG_TOUCHSCREEN_TSC_SERIO=m
# CONFIG_TOUCHSCREEN_TSC2004 is not set
# CONFIG_TOUCHSCREEN_TSC2005 is not set
CONFIG_TOUCHSCREEN_TSC2007=m
# CONFIG_TOUCHSCREEN_TSC2007_IIO is not set
# CONFIG_TOUCHSCREEN_RM_TS is not set
# CONFIG_TOUCHSCREEN_SILEAD is not set
# CONFIG_TOUCHSCREEN_SIS_I2C is not set
CONFIG_TOUCHSCREEN_ST1232=m
# CONFIG_TOUCHSCREEN_STMFTS is not set
# CONFIG_TOUCHSCREEN_SUN4I is not set
# CONFIG_TOUCHSCREEN_SUR40 is not set
# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
# CONFIG_TOUCHSCREEN_SX8654 is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_TOUCHSCREEN_ZET6223 is not set
CONFIG_TOUCHSCREEN_ZFORCE=m
# CONFIG_TOUCHSCREEN_COLIBRI_VF50 is not set
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
# CONFIG_TOUCHSCREEN_IQS5XX is not set
# CONFIG_TOUCHSCREEN_IQS7211 is not set
# CONFIG_TOUCHSCREEN_ZINITIX is not set
# CONFIG_TOUCHSCREEN_HIMAX_HX83112B is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
# CONFIG_INPUT_BMA150 is not set
CONFIG_INPUT_E3X0_BUTTON=m
CONFIG_INPUT_MMA8450=m
# CONFIG_INPUT_GPIO_BEEPER is not set
# CONFIG_INPUT_GPIO_DECODER is not set
# CONFIG_INPUT_GPIO_VIBRA is not set
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
CONFIG_INPUT_KXTJ9=m
CONFIG_INPUT_POWERMATE=m
CONFIG_INPUT_YEALINK=m
CONFIG_INPUT_CM109=m
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
CONFIG_INPUT_AXP20X_PEK=m
CONFIG_INPUT_UINPUT=m
# CONFIG_INPUT_PCF8574 is not set
CONFIG_INPUT_PWM_BEEPER=m
# CONFIG_INPUT_PWM_VIBRA is not set
CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
# CONFIG_INPUT_DA7280_HAPTICS is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_IBM_PANEL is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_INPUT_IQS269A is not set
# CONFIG_INPUT_IQS626A is not set
# CONFIG_INPUT_IQS7222 is not set
CONFIG_INPUT_CMA3000=m
CONFIG_INPUT_CMA3000_I2C=m
# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
# CONFIG_INPUT_DRV260X_HAPTICS is not set
# CONFIG_INPUT_DRV2665_HAPTICS is not set
# CONFIG_INPUT_DRV2667_HAPTICS is not set
CONFIG_RMI4_CORE=m
# CONFIG_RMI4_I2C is not set
# CONFIG_RMI4_SPI is not set
# CONFIG_RMI4_SMB is not set
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=m
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
# CONFIG_RMI4_F34 is not set
# CONFIG_RMI4_F3A is not set
# CONFIG_RMI4_F54 is not set
# CONFIG_RMI4_F55 is not set

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO_AMBAKMI=y
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIO_RAW=m
CONFIG_SERIO_ALTERA_PS2=m
# CONFIG_SERIO_PS2MULT is not set
CONFIG_SERIO_ARC_PS2=m
# CONFIG_SERIO_APBPS2 is not set
# CONFIG_SERIO_SUN4I_PS2 is not set
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
# CONFIG_GAMEPORT is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_LEGACY_TIOCSTI is not set
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
CONFIG_SERIAL_8250_PCILIB=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_EXAR=y
CONFIG_SERIAL_8250_NR_UARTS=32
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
# CONFIG_SERIAL_8250_PCI1XXXX is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_8250_PERICOM=y
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
# CONFIG_SERIAL_AMBA_PL010 is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set
# CONFIG_SERIAL_KGDB_NMI is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_CONSOLE_POLL=y
CONFIG_SERIAL_JSM=m
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
CONFIG_SERIAL_ARC=m
CONFIG_SERIAL_ARC_NR_PORTS=1
# CONFIG_SERIAL_RP2 is not set
CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_SERIAL_FSL_LINFLEXUART=y
CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_NONSTANDARD=y
# CONFIG_MOXA_INTELLIO is not set
# CONFIG_MOXA_SMARTIO is not set
CONFIG_N_HDLC=m
CONFIG_N_GSM=m
CONFIG_NOZOMI=m
# CONFIG_NULL_TTY is not set
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
# CONFIG_RPMSG_TTY is not set
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_TTY_PRINTK is not set
CONFIG_VIRTIO_CONSOLE=y
CONFIG_IPMI_HANDLER=y
CONFIG_IPMI_DMI_DECODE=y
CONFIG_IPMI_PLAT_DATA=y
# CONFIG_IPMI_PANIC_EVENT is not set
CONFIG_IPMI_DEVICE_INTERFACE=m
CONFIG_IPMI_SI=m
CONFIG_IPMI_SSIF=m
# CONFIG_IPMI_IPMB is not set
CONFIG_IPMI_WATCHDOG=m
CONFIG_IPMI_POWEROFF=m
# CONFIG_SSIF_IPMI_BMC is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=m
# CONFIG_HW_RANDOM_BA431 is not set
CONFIG_HW_RANDOM_VIRTIO=m
# CONFIG_HW_RANDOM_CCTRNG is not set
# CONFIG_HW_RANDOM_XIPHERA is not set
CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
CONFIG_HW_RANDOM_CN10K=y
# CONFIG_APPLICOM is not set
CONFIG_DEVMEM=y
CONFIG_DEVPORT=y
CONFIG_TCG_TPM=y
CONFIG_HW_RANDOM_TPM=y
# CONFIG_TCG_TIS is not set
# CONFIG_TCG_TIS_SPI is not set
# CONFIG_TCG_TIS_I2C is not set
# CONFIG_TCG_TIS_I2C_CR50 is not set
# CONFIG_TCG_TIS_I2C_ATMEL is not set
CONFIG_TCG_TIS_I2C_INFINEON=y
# CONFIG_TCG_TIS_I2C_NUVOTON is not set
CONFIG_TCG_ATMEL=m
# CONFIG_TCG_INFINEON is not set
# CONFIG_TCG_CRB is not set
# CONFIG_TCG_VTPM_PROXY is not set
# CONFIG_TCG_TIS_ST33ZP24_I2C is not set
# CONFIG_TCG_TIS_ST33ZP24_SPI is not set
# CONFIG_XILLYBUS is not set
# CONFIG_XILLYUSB is not set
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=m
CONFIG_I2C_MUX_GPIO=m
CONFIG_I2C_MUX_GPMUX=m
# CONFIG_I2C_MUX_LTC4306 is not set
CONFIG_I2C_MUX_PCA9541=m
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_MUX_PINCTRL=m
CONFIG_I2C_MUX_REG=m
CONFIG_I2C_DEMUX_PINCTRL=m
# CONFIG_I2C_MUX_MLXCPLD is not set
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_SMBUS=m
CONFIG_I2C_ALGOBIT=m
CONFIG_I2C_ALGOPCA=m

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
CONFIG_I2C_CCGX_UCSI=m
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
CONFIG_I2C_NFORCE2=m
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set

#
# ACPI drivers
#
CONFIG_I2C_SCMI=y

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CADENCE is not set
# CONFIG_I2C_CBUS_GPIO is not set
CONFIG_I2C_DESIGNWARE_CORE=y
# CONFIG_I2C_DESIGNWARE_SLAVE is not set
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_DESIGNWARE_PCI=m
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=m
# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
# CONFIG_I2C_HISI is not set
CONFIG_I2C_MV64XXX=y
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_PCA_PLATFORM=m
CONFIG_I2C_RK3X=y
CONFIG_I2C_SIMTEC=m
CONFIG_I2C_VERSATILE=m
# CONFIG_I2C_THUNDERX is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
CONFIG_I2C_DIOLAN_U2C=m
# CONFIG_I2C_CP2615 is not set
# CONFIG_I2C_PCI1XXXX is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
CONFIG_I2C_TINY_USB=m
CONFIG_I2C_VIPERBOARD=m

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_MLXCPLD is not set
CONFIG_I2C_CROS_EC_TUNNEL=y
# CONFIG_I2C_VIRTIO is not set
# end of I2C Hardware Bus support

CONFIG_I2C_STUB=m
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=m
# CONFIG_I2C_SLAVE_TESTUNIT is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

# CONFIG_I3C is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y

#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
CONFIG_SPI_BITBANG=y
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_CADENCE_XSPI is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_HISI_KUNPENG is not set
# CONFIG_SPI_HISI_SFC_V3XX is not set
CONFIG_SPI_GPIO=y
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_MICROCHIP_CORE is not set
# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PCI1XXXX is not set
CONFIG_SPI_PL022=y
# CONFIG_SPI_PXA2XX is not set
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_SN_F_OSPI is not set
# CONFIG_SPI_SUN4I is not set
CONFIG_SPI_SUN6I=y
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_THUNDERX is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_SPI_AMD is not set

#
# SPI Multiplexer support
#
# CONFIG_SPI_MUX is not set

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=m
# CONFIG_SPI_LOOPBACK_TEST is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_DYNAMIC=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set

#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
CONFIG_PPS_CLIENT_LDISC=m
CONFIG_PPS_CLIENT_GPIO=m

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_DP83640_PHY=m
# CONFIG_PTP_1588_CLOCK_INES is not set
CONFIG_PTP_1588_CLOCK_KVM=y
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
# CONFIG_PTP_1588_CLOCK_MOCK is not set
# CONFIG_PTP_1588_CLOCK_OCP is not set
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
CONFIG_PINCTRL_AMD=y
CONFIG_PINCTRL_AXP209=y
# CONFIG_PINCTRL_CY8C95X0 is not set
CONFIG_PINCTRL_MAX77620=y
# CONFIG_PINCTRL_MCP23S08 is not set
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
# CONFIG_PINCTRL_OCELOT is not set
CONFIG_PINCTRL_SINGLE=y
# CONFIG_PINCTRL_STMFX is not set
# CONFIG_PINCTRL_SX150X is not set

#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers

CONFIG_PINCTRL_SUNXI=y
# CONFIG_PINCTRL_SUN4I_A10 is not set
# CONFIG_PINCTRL_SUN5I is not set
# CONFIG_PINCTRL_SUN6I_A31 is not set
# CONFIG_PINCTRL_SUN6I_A31_R is not set
# CONFIG_PINCTRL_SUN8I_A23 is not set
# CONFIG_PINCTRL_SUN8I_A33 is not set
# CONFIG_PINCTRL_SUN8I_A83T is not set
# CONFIG_PINCTRL_SUN8I_A83T_R is not set
# CONFIG_PINCTRL_SUN8I_A23_R is not set
# CONFIG_PINCTRL_SUN8I_H3 is not set
CONFIG_PINCTRL_SUN8I_H3_R=y
# CONFIG_PINCTRL_SUN8I_V3S is not set
# CONFIG_PINCTRL_SUN9I_A80 is not set
# CONFIG_PINCTRL_SUN9I_A80_R is not set
# CONFIG_PINCTRL_SUN20I_D1 is not set
CONFIG_PINCTRL_SUN50I_A64=y
CONFIG_PINCTRL_SUN50I_A64_R=y
CONFIG_PINCTRL_SUN50I_A100=y
CONFIG_PINCTRL_SUN50I_A100_R=y
CONFIG_PINCTRL_SUN50I_H5=y
CONFIG_PINCTRL_SUN50I_H6=y
CONFIG_PINCTRL_SUN50I_H6_R=y
CONFIG_PINCTRL_SUN50I_H616=y
CONFIG_PINCTRL_SUN50I_H616_R=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_CADENCE is not set
CONFIG_GPIO_DWAPB=y
# CONFIG_GPIO_EXAR is not set
# CONFIG_GPIO_FTGPIO010 is not set
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HISI is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_LOGICVC is not set
# CONFIG_GPIO_MB86S7X is not set
CONFIG_GPIO_PL061=y
# CONFIG_GPIO_SIFIVE is not set
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_WCD934X=m
CONFIG_GPIO_XGENE=y
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
# CONFIG_GPIO_ADNP is not set
# CONFIG_GPIO_FXL6408 is not set
# CONFIG_GPIO_DS4520 is not set
# CONFIG_GPIO_GW_PLD is not set
# CONFIG_GPIO_MAX7300 is not set
CONFIG_GPIO_MAX732X=y
# CONFIG_GPIO_MAX732X_IRQ is not set
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
# CONFIG_GPIO_PCA9570 is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_TPIC2810 is not set
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
CONFIG_GPIO_MAX77620=y
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set
# end of PCI GPIO expanders

#
# SPI GPIO expanders
#
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
CONFIG_GPIO_VIPERBOARD=m
# end of USB GPIO expanders

#
# Virtual GPIO drivers
#
# CONFIG_GPIO_AGGREGATOR is not set
# CONFIG_GPIO_LATCH is not set
# CONFIG_GPIO_MOCKUP is not set
# CONFIG_GPIO_VIRTIO is not set
# CONFIG_GPIO_SIM is not set
# end of Virtual GPIO drivers

CONFIG_W1=m
CONFIG_W1_CON=y

#
# 1-wire Bus Masters
#
# CONFIG_W1_MASTER_MATROX is not set
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
# CONFIG_W1_MASTER_GPIO is not set
# CONFIG_W1_MASTER_SGI is not set
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
# CONFIG_W1_SLAVE_DS2405 is not set
CONFIG_W1_SLAVE_DS2408=m
# CONFIG_W1_SLAVE_DS2408_READBACK is not set
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
# CONFIG_W1_SLAVE_DS2805 is not set
# CONFIG_W1_SLAVE_DS2430 is not set
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
# CONFIG_W1_SLAVE_DS2438 is not set
# CONFIG_W1_SLAVE_DS250X is not set
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
# CONFIG_W1_SLAVE_DS28E17 is not set
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_BRCMSTB is not set
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
# CONFIG_POWER_RESET_LTC2952 is not set
# CONFIG_POWER_RESET_REGULATOR is not set
CONFIG_POWER_RESET_RESTART=y
CONFIG_POWER_RESET_VEXPRESS=y
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
# CONFIG_NVMEM_REBOOT_MODE is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_IP5XXX_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SAMSUNG_SDI is not set
CONFIG_BATTERY_SBS=m
CONFIG_CHARGER_SBS=m
CONFIG_MANAGER_SBS=m
# CONFIG_BATTERY_BQ27XXX is not set
CONFIG_CHARGER_AXP20X=m
CONFIG_BATTERY_AXP20X=m
CONFIG_AXP20X_POWER=m
# CONFIG_BATTERY_MAX17040 is not set
CONFIG_BATTERY_MAX17042=m
# CONFIG_BATTERY_MAX1721X is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
# CONFIG_CHARGER_GPIO is not set
# CONFIG_CHARGER_MANAGER is not set
# CONFIG_CHARGER_LT3651 is not set
# CONFIG_CHARGER_LTC4162L is not set
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_MAX77976 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25890 is not set
CONFIG_CHARGER_BQ25980=m
# CONFIG_CHARGER_BQ256XX is not set
CONFIG_CHARGER_SMB347=m
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_BATTERY_GOLDFISH is not set
# CONFIG_BATTERY_RT5033 is not set
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_RT9467 is not set
# CONFIG_CHARGER_RT9471 is not set
CONFIG_CHARGER_CROS_USBPD=m
CONFIG_CHARGER_CROS_PCHG=y
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
# CONFIG_BATTERY_UG3105 is not set
CONFIG_HWMON=y
CONFIG_HWMON_VID=m
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
CONFIG_SENSORS_AD7414=m
CONFIG_SENSORS_AD7418=m
CONFIG_SENSORS_ADM1025=m
CONFIG_SENSORS_ADM1026=m
CONFIG_SENSORS_ADM1029=m
CONFIG_SENSORS_ADM1031=m
# CONFIG_SENSORS_ADM1177 is not set
CONFIG_SENSORS_ADM9240=m
CONFIG_SENSORS_ADT7X10=m
# CONFIG_SENSORS_ADT7310 is not set
CONFIG_SENSORS_ADT7410=m
CONFIG_SENSORS_ADT7411=m
CONFIG_SENSORS_ADT7462=m
CONFIG_SENSORS_ADT7470=m
CONFIG_SENSORS_ADT7475=m
# CONFIG_SENSORS_AHT10 is not set
# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
# CONFIG_SENSORS_AS370 is not set
CONFIG_SENSORS_ASC7621=m
# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
CONFIG_SENSORS_ARM_SCMI=y
CONFIG_SENSORS_ARM_SCPI=y
CONFIG_SENSORS_ATXP1=m
# CONFIG_SENSORS_CORSAIR_CPRO is not set
# CONFIG_SENSORS_CORSAIR_PSU is not set
CONFIG_SENSORS_DRIVETEMP=m
CONFIG_SENSORS_DS620=m
CONFIG_SENSORS_DS1621=m
# CONFIG_SENSORS_I5K_AMB is not set
CONFIG_SENSORS_F71805F=m
CONFIG_SENSORS_F71882FG=m
CONFIG_SENSORS_F75375S=m
# CONFIG_SENSORS_FTSTEUTATES is not set
CONFIG_SENSORS_GL518SM=m
CONFIG_SENSORS_GL520SM=m
CONFIG_SENSORS_G760A=m
CONFIG_SENSORS_G762=m
CONFIG_SENSORS_GPIO_FAN=m
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_HS3001 is not set
CONFIG_SENSORS_IBMAEM=m
CONFIG_SENSORS_IBMPEX=m
CONFIG_SENSORS_IIO_HWMON=m
CONFIG_SENSORS_IT87=m
# CONFIG_SENSORS_JC42 is not set
CONFIG_SENSORS_POWR1220=m
CONFIG_SENSORS_LINEAGE=m
CONFIG_SENSORS_LTC2945=m
# CONFIG_SENSORS_LTC2947_I2C is not set
# CONFIG_SENSORS_LTC2947_SPI is not set
# CONFIG_SENSORS_LTC2990 is not set
# CONFIG_SENSORS_LTC2992 is not set
CONFIG_SENSORS_LTC4151=m
CONFIG_SENSORS_LTC4215=m
CONFIG_SENSORS_LTC4222=m
CONFIG_SENSORS_LTC4245=m
CONFIG_SENSORS_LTC4260=m
CONFIG_SENSORS_LTC4261=m
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX127 is not set
CONFIG_SENSORS_MAX16065=m
CONFIG_SENSORS_MAX1619=m
CONFIG_SENSORS_MAX1668=m
CONFIG_SENSORS_MAX197=m
# CONFIG_SENSORS_MAX31722 is not set
# CONFIG_SENSORS_MAX31730 is not set
# CONFIG_SENSORS_MAX31760 is not set
# CONFIG_MAX31827 is not set
# CONFIG_SENSORS_MAX6620 is not set
# CONFIG_SENSORS_MAX6621 is not set
CONFIG_SENSORS_MAX6639=m
CONFIG_SENSORS_MAX6650=m
CONFIG_SENSORS_MAX6697=m
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MC34VR500 is not set
CONFIG_SENSORS_MCP3021=m
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_TPS23861 is not set
# CONFIG_SENSORS_MR75203 is not set
# CONFIG_SENSORS_ADCXX is not set
CONFIG_SENSORS_LM63=m
# CONFIG_SENSORS_LM70 is not set
CONFIG_SENSORS_LM73=m
CONFIG_SENSORS_LM75=m
CONFIG_SENSORS_LM77=m
CONFIG_SENSORS_LM78=m
CONFIG_SENSORS_LM80=m
CONFIG_SENSORS_LM83=m
CONFIG_SENSORS_LM85=m
CONFIG_SENSORS_LM87=m
CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_LM92=m
CONFIG_SENSORS_LM93=m
CONFIG_SENSORS_LM95234=m
CONFIG_SENSORS_LM95241=m
CONFIG_SENSORS_LM95245=m
CONFIG_SENSORS_PC87360=m
CONFIG_SENSORS_PC87427=m
CONFIG_SENSORS_NTC_THERMISTOR=m
CONFIG_SENSORS_NCT6683=m
CONFIG_SENSORS_NCT6775_CORE=m
CONFIG_SENSORS_NCT6775=m
# CONFIG_SENSORS_NCT6775_I2C is not set
CONFIG_SENSORS_NCT7802=m
CONFIG_SENSORS_NCT7904=m
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
# CONFIG_SENSORS_NZXT_SMART2 is not set
# CONFIG_SENSORS_OCC_P8_I2C is not set
CONFIG_SENSORS_PCF8591=m
CONFIG_PMBUS=m
CONFIG_SENSORS_PMBUS=m
# CONFIG_SENSORS_ACBEL_FSG032 is not set
# CONFIG_SENSORS_ADM1266 is not set
CONFIG_SENSORS_ADM1275=m
# CONFIG_SENSORS_BEL_PFE is not set
# CONFIG_SENSORS_BPA_RS600 is not set
# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set
# CONFIG_SENSORS_FSP_3Y is not set
# CONFIG_SENSORS_IBM_CFFPS is not set
# CONFIG_SENSORS_DPS920AB is not set
# CONFIG_SENSORS_INSPUR_IPSPS is not set
# CONFIG_SENSORS_IR35221 is not set
# CONFIG_SENSORS_IR36021 is not set
# CONFIG_SENSORS_IR38064 is not set
# CONFIG_SENSORS_IRPS5401 is not set
# CONFIG_SENSORS_ISL68137 is not set
CONFIG_SENSORS_LM25066=m
# CONFIG_SENSORS_LM25066_REGULATOR is not set
# CONFIG_SENSORS_LT7182S is not set
CONFIG_SENSORS_LTC2978=m
# CONFIG_SENSORS_LTC2978_REGULATOR is not set
# CONFIG_SENSORS_LTC3815 is not set
# CONFIG_SENSORS_MAX15301 is not set
CONFIG_SENSORS_MAX16064=m
# CONFIG_SENSORS_MAX16601 is not set
# CONFIG_SENSORS_MAX20730 is not set
# CONFIG_SENSORS_MAX20751 is not set
# CONFIG_SENSORS_MAX31785 is not set
CONFIG_SENSORS_MAX34440=m
CONFIG_SENSORS_MAX8688=m
# CONFIG_SENSORS_MP2888 is not set
# CONFIG_SENSORS_MP2975 is not set
# CONFIG_SENSORS_MP5023 is not set
# CONFIG_SENSORS_MPQ7932 is not set
# CONFIG_SENSORS_PIM4328 is not set
# CONFIG_SENSORS_PLI1209BC is not set
# CONFIG_SENSORS_PM6764TR is not set
# CONFIG_SENSORS_PXE1610 is not set
# CONFIG_SENSORS_Q54SJ108A2 is not set
# CONFIG_SENSORS_STPDDC60 is not set
# CONFIG_SENSORS_TDA38640 is not set
CONFIG_SENSORS_TPS40422=m
# CONFIG_SENSORS_TPS53679 is not set
# CONFIG_SENSORS_TPS546D24 is not set
CONFIG_SENSORS_UCD9000=m
CONFIG_SENSORS_UCD9200=m
# CONFIG_SENSORS_XDPE152 is not set
# CONFIG_SENSORS_XDPE122 is not set
CONFIG_SENSORS_ZL6100=m
CONFIG_SENSORS_PWM_FAN=m
# CONFIG_SENSORS_SBTSI is not set
# CONFIG_SENSORS_SBRMI is not set
CONFIG_SENSORS_SHT15=m
CONFIG_SENSORS_SHT21=m
CONFIG_SENSORS_SHT3x=m
# CONFIG_SENSORS_SHT4x is not set
CONFIG_SENSORS_SHTC1=m
CONFIG_SENSORS_SIS5595=m
CONFIG_SENSORS_DME1737=m
CONFIG_SENSORS_EMC1403=m
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC2305 is not set
CONFIG_SENSORS_EMC6W201=m
CONFIG_SENSORS_SMSC47M1=m
CONFIG_SENSORS_SMSC47M192=m
CONFIG_SENSORS_SMSC47B397=m
CONFIG_SENSORS_SCH56XX_COMMON=m
CONFIG_SENSORS_SCH5627=m
CONFIG_SENSORS_SCH5636=m
# CONFIG_SENSORS_STTS751 is not set
CONFIG_SENSORS_ADC128D818=m
CONFIG_SENSORS_ADS7828=m
# CONFIG_SENSORS_ADS7871 is not set
CONFIG_SENSORS_AMC6821=m
CONFIG_SENSORS_INA209=m
CONFIG_SENSORS_INA2XX=m
# CONFIG_SENSORS_INA238 is not set
CONFIG_SENSORS_INA3221=m
CONFIG_SENSORS_TC74=m
CONFIG_SENSORS_THMC50=m
CONFIG_SENSORS_TMP102=m
CONFIG_SENSORS_TMP103=m
CONFIG_SENSORS_TMP108=m
CONFIG_SENSORS_TMP401=m
CONFIG_SENSORS_TMP421=m
# CONFIG_SENSORS_TMP464 is not set
# CONFIG_SENSORS_TMP513 is not set
CONFIG_SENSORS_VEXPRESS=m
CONFIG_SENSORS_VIA686A=m
CONFIG_SENSORS_VT1211=m
CONFIG_SENSORS_VT8231=m
# CONFIG_SENSORS_W83773G is not set
CONFIG_SENSORS_W83781D=m
CONFIG_SENSORS_W83791D=m
CONFIG_SENSORS_W83792D=m
CONFIG_SENSORS_W83793=m
CONFIG_SENSORS_W83795=m
# CONFIG_SENSORS_W83795_FANCTRL is not set
CONFIG_SENSORS_W83L785TS=m
CONFIG_SENSORS_W83L786NG=m
CONFIG_SENSORS_W83627HF=m
CONFIG_SENSORS_W83627EHF=m
# CONFIG_SENSORS_XGENE is not set

#
# ACPI drivers
#
CONFIG_SENSORS_ACPI_POWER=m
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
# CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG is not set
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_BANG_BANG=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_THERMAL_EMULATION=y
# CONFIG_THERMAL_MMIO is not set
CONFIG_MAX77620_THERMAL=m
CONFIG_SUN8I_THERMAL=m
CONFIG_GENERIC_ADC_THERMAL=m
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set
CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=m
CONFIG_GPIO_WATCHDOG=m
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_XILINX_WINDOW_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
CONFIG_ARM_SP805_WATCHDOG=m
CONFIG_ARM_SBSA_WATCHDOG=m
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=m
CONFIG_SUNXI_WATCHDOG=m
# CONFIG_MAX63XX_WATCHDOG is not set
CONFIG_MAX77620_WATCHDOG=m
CONFIG_ARM_SMC_WATCHDOG=y
CONFIG_ALIM7101_WDT=m
CONFIG_I6300ESB_WDT=m
# CONFIG_HP_WATCHDOG is not set
# CONFIG_MEN_A21_WDT is not set

#
# PCI-based Watchdog Cards
#
CONFIG_PCIPCWATCHDOG=m
CONFIG_WDTPCI=m

#
# USB-based Watchdog Cards
#
CONFIG_USBPCWATCHDOG=m
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB=m
CONFIG_SSB_SPROM=y
CONFIG_SSB_BLOCKIO=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_PCIHOST=y
CONFIG_SSB_B43_PCI_BRIDGE=y
CONFIG_SSB_SDIOHOST_POSSIBLE=y
CONFIG_SSB_SDIOHOST=y
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
CONFIG_SSB_DRIVER_PCICORE=y
CONFIG_SSB_DRIVER_GPIO=y
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_BLOCKIO=y
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
CONFIG_BCMA_HOST_PCI=y
# CONFIG_BCMA_HOST_SOC is not set
CONFIG_BCMA_DRIVER_PCI=y
CONFIG_BCMA_DRIVER_GMAC_CMN=y
CONFIG_BCMA_DRIVER_GPIO=y
# CONFIG_BCMA_DEBUG is not set

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_SUN4I_GPADC is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_SMPRO is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AC100 is not set
CONFIG_MFD_AC200=y
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
CONFIG_MFD_CROS_EC_DEV=y
# CONFIG_MFD_CS42L43_I2C is not set
# CONFIG_MFD_CS42L43_SDW is not set
# CONFIG_MFD_MADERA is not set
# CONFIG_MFD_MAX5970 is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77541 is not set
CONFIG_MFD_MAX77620=y
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77714 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6370 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_MFD_OCELOT is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
CONFIG_MFD_VIPERBOARD=m
# CONFIG_MFD_NTXEC is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_SY7636A is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT4831 is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RT5120 is not set
# CONFIG_MFD_RC5T583 is not set
# CONFIG_MFD_RK8XX_I2C is not set
# CONFIG_MFD_RK8XX_SPI is not set
# CONFIG_MFD_RN5T618 is not set
CONFIG_MFD_SEC_CORE=y
# CONFIG_MFD_SI476X_CORE is not set
CONFIG_MFD_SM501=m
CONFIG_MFD_SM501_GPIO=y
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SUN6I_PRCM=y
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS65219 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS6594_I2C is not set
# CONFIG_MFD_TPS6594_SPI is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TQMX86 is not set
CONFIG_MFD_VX855=m
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
CONFIG_MFD_ROHM_BD718XX=y
# CONFIG_MFD_ROHM_BD71828 is not set
# CONFIG_MFD_ROHM_BD957XMUF is not set
# CONFIG_MFD_STPMIC1 is not set
# CONFIG_MFD_STMFX is not set
CONFIG_MFD_WCD934X=m
# CONFIG_MFD_ATC260X_I2C is not set
# CONFIG_MFD_QCOM_PM8008 is not set
CONFIG_MFD_VEXPRESS_SYSREG=y
# CONFIG_RAVE_SP_CORE is not set
# CONFIG_MFD_INTEL_M10_BMC_SPI is not set
# CONFIG_MFD_RSMU_I2C is not set
# CONFIG_MFD_RSMU_SPI is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_88PG86X is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_AD5398 is not set
# CONFIG_REGULATOR_ARM_SCMI is not set
# CONFIG_REGULATOR_AW37503 is not set
CONFIG_REGULATOR_AXP20X=y
CONFIG_REGULATOR_BD718XX=y
# CONFIG_REGULATOR_CROS_EC is not set
# CONFIG_REGULATOR_DA9121 is not set
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
CONFIG_REGULATOR_FAN53555=y
# CONFIG_REGULATOR_FAN53880 is not set
CONFIG_REGULATOR_GPIO=y
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_LP8755 is not set
# CONFIG_REGULATOR_LTC3589 is not set
# CONFIG_REGULATOR_LTC3676 is not set
# CONFIG_REGULATOR_MAX1586 is not set
CONFIG_REGULATOR_MAX77620=y
# CONFIG_REGULATOR_MAX77857 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8893 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_MAX8973 is not set
# CONFIG_REGULATOR_MAX20086 is not set
# CONFIG_REGULATOR_MAX20411 is not set
# CONFIG_REGULATOR_MAX77826 is not set
# CONFIG_REGULATOR_MCP16502 is not set
# CONFIG_REGULATOR_MP5416 is not set
# CONFIG_REGULATOR_MP8859 is not set
# CONFIG_REGULATOR_MP886X is not set
# CONFIG_REGULATOR_MPQ7920 is not set
# CONFIG_REGULATOR_MT6311 is not set
# CONFIG_REGULATOR_MT6315 is not set
CONFIG_REGULATOR_PCA9450=y
# CONFIG_REGULATOR_PF8X00 is not set
CONFIG_REGULATOR_PFUZE100=y
# CONFIG_REGULATOR_PV88060 is not set
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_QCOM_SPMI=y
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
# CONFIG_REGULATOR_RAA215300 is not set
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
CONFIG_REGULATOR_ROHM=y
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RT4803 is not set
# CONFIG_REGULATOR_RT5190A is not set
# CONFIG_REGULATOR_RT5739 is not set
# CONFIG_REGULATOR_RT5759 is not set
# CONFIG_REGULATOR_RT6160 is not set
# CONFIG_REGULATOR_RT6190 is not set
# CONFIG_REGULATOR_RT6245 is not set
# CONFIG_REGULATOR_RTQ2134 is not set
# CONFIG_REGULATOR_RTMV20 is not set
# CONFIG_REGULATOR_RTQ6752 is not set
# CONFIG_REGULATOR_RTQ2208 is not set
# CONFIG_REGULATOR_S2MPA01 is not set
CONFIG_REGULATOR_S2MPS11=y
# CONFIG_REGULATOR_S5M8767 is not set
# CONFIG_REGULATOR_SLG51000 is not set
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
# CONFIG_REGULATOR_SY8827N is not set
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS6286X is not set
# CONFIG_REGULATOR_TPS6287X is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
CONFIG_REGULATOR_TPS65132=m
# CONFIG_REGULATOR_TPS6524X is not set
CONFIG_REGULATOR_VCTRL=y
CONFIG_REGULATOR_VEXPRESS=y
# CONFIG_REGULATOR_QCOM_LABIBB is not set
CONFIG_RC_CORE=m
CONFIG_LIRC=y
CONFIG_RC_MAP=m
CONFIG_RC_DECODERS=y
CONFIG_IR_IMON_DECODER=m
CONFIG_IR_JVC_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
CONFIG_IR_RCMM_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_XMP_DECODER=m
CONFIG_RC_DEVICES=y
CONFIG_IR_ENE=m
CONFIG_IR_FINTEK=m
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_GPIO_TX=m
CONFIG_IR_HIX5HD2=m
CONFIG_IR_IGORPLUGUSB=m
CONFIG_IR_IGUANA=m
CONFIG_IR_IMON=m
CONFIG_IR_IMON_RAW=m
CONFIG_IR_ITE_CIR=m
CONFIG_IR_MCEUSB=m
CONFIG_IR_NUVOTON=m
CONFIG_IR_PWM_TX=m
CONFIG_IR_REDRAT3=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m
CONFIG_IR_SUNXI=m
CONFIG_IR_TOY=m
CONFIG_IR_TTUSBIR=m
CONFIG_RC_ATI_REMOTE=m
CONFIG_RC_LOOPBACK=m
# CONFIG_RC_XBOX_DVD is not set
CONFIG_CEC_CORE=m
CONFIG_CEC_NOTIFIER=y

#
# CEC support
#
CONFIG_MEDIA_CEC_RC=y
CONFIG_MEDIA_CEC_SUPPORT=y
CONFIG_CEC_CH7322=m
CONFIG_CEC_CROS_EC=m
CONFIG_USB_PULSE8_CEC=m
CONFIG_USB_RAINSHADOW_CEC=m
# end of CEC support

CONFIG_MEDIA_SUPPORT=m
# CONFIG_MEDIA_SUPPORT_FILTER is not set
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
CONFIG_MEDIA_RADIO_SUPPORT=y
CONFIG_MEDIA_SDR_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_TEST_SUPPORT=y
# end of Media device types

#
# Media core support
#
CONFIG_VIDEO_DEV=m
CONFIG_MEDIA_CONTROLLER=y
CONFIG_DVB_CORE=m
# end of Media core support

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_H264=m
CONFIG_V4L2_VP9=m
CONFIG_V4L2_MEM2MEM_DEV=m
# CONFIG_V4L2_FLASH_LED_CLASS is not set
CONFIG_V4L2_FWNODE=m
CONFIG_V4L2_ASYNC=m
CONFIG_V4L2_CCI=m
CONFIG_V4L2_CCI_I2C=m
# end of Video4Linux options

#
# Media controller options
#
CONFIG_MEDIA_CONTROLLER_DVB=y
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
# end of Media controller options

#
# Digital TV options
#
# CONFIG_DVB_MMAP is not set
CONFIG_DVB_NET=y
CONFIG_DVB_MAX_ADAPTERS=8
CONFIG_DVB_DYNAMIC_MINORS=y
# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
# CONFIG_DVB_ULE_DEBUG is not set
# end of Digital TV options

#
# Media drivers
#

#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_GSPCA=m
CONFIG_USB_GSPCA_BENQ=m
CONFIG_USB_GSPCA_CONEX=m
CONFIG_USB_GSPCA_CPIA1=m
CONFIG_USB_GSPCA_DTCS033=m
CONFIG_USB_GSPCA_ETOMS=m
CONFIG_USB_GSPCA_FINEPIX=m
CONFIG_USB_GSPCA_JEILINJ=m
CONFIG_USB_GSPCA_JL2005BCD=m
CONFIG_USB_GSPCA_KINECT=m
CONFIG_USB_GSPCA_KONICA=m
CONFIG_USB_GSPCA_MARS=m
CONFIG_USB_GSPCA_MR97310A=m
CONFIG_USB_GSPCA_NW80X=m
CONFIG_USB_GSPCA_OV519=m
CONFIG_USB_GSPCA_OV534=m
CONFIG_USB_GSPCA_OV534_9=m
CONFIG_USB_GSPCA_PAC207=m
CONFIG_USB_GSPCA_PAC7302=m
CONFIG_USB_GSPCA_PAC7311=m
CONFIG_USB_GSPCA_SE401=m
CONFIG_USB_GSPCA_SN9C2028=m
CONFIG_USB_GSPCA_SN9C20X=m
CONFIG_USB_GSPCA_SONIXB=m
CONFIG_USB_GSPCA_SONIXJ=m
CONFIG_USB_GSPCA_SPCA1528=m
CONFIG_USB_GSPCA_SPCA500=m
CONFIG_USB_GSPCA_SPCA501=m
CONFIG_USB_GSPCA_SPCA505=m
CONFIG_USB_GSPCA_SPCA506=m
CONFIG_USB_GSPCA_SPCA508=m
CONFIG_USB_GSPCA_SPCA561=m
CONFIG_USB_GSPCA_SQ905=m
CONFIG_USB_GSPCA_SQ905C=m
CONFIG_USB_GSPCA_SQ930X=m
CONFIG_USB_GSPCA_STK014=m
CONFIG_USB_GSPCA_STK1135=m
CONFIG_USB_GSPCA_STV0680=m
CONFIG_USB_GSPCA_SUNPLUS=m
CONFIG_USB_GSPCA_T613=m
CONFIG_USB_GSPCA_TOPRO=m
CONFIG_USB_GSPCA_TOUPTEK=m
CONFIG_USB_GSPCA_TV8532=m
CONFIG_USB_GSPCA_VC032X=m
CONFIG_USB_GSPCA_VICAM=m
CONFIG_USB_GSPCA_XIRLINK_CIT=m
CONFIG_USB_GSPCA_ZC3XX=m
CONFIG_USB_GL860=m
CONFIG_USB_M5602=m
CONFIG_USB_STV06XX=m
CONFIG_USB_PWC=m
# CONFIG_USB_PWC_DEBUG is not set
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_USB_S2255=m
CONFIG_VIDEO_USBTV=m
CONFIG_USB_VIDEO_CLASS=m
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y

#
# Analog TV USB devices
#
CONFIG_VIDEO_GO7007=m
CONFIG_VIDEO_GO7007_USB=m
CONFIG_VIDEO_GO7007_LOADER=m
CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
CONFIG_VIDEO_HDPVR=m
CONFIG_VIDEO_PVRUSB2=m
CONFIG_VIDEO_PVRUSB2_SYSFS=y
CONFIG_VIDEO_PVRUSB2_DVB=y
# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
CONFIG_VIDEO_STK1160=m

#
# Analog/digital TV USB devices
#
CONFIG_VIDEO_AU0828=m
CONFIG_VIDEO_AU0828_V4L2=y
CONFIG_VIDEO_AU0828_RC=y
CONFIG_VIDEO_CX231XX=m
CONFIG_VIDEO_CX231XX_RC=y
CONFIG_VIDEO_CX231XX_ALSA=m
CONFIG_VIDEO_CX231XX_DVB=m

#
# Digital TV USB devices
#
CONFIG_DVB_AS102=m
CONFIG_DVB_B2C2_FLEXCOP_USB=m
# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
CONFIG_DVB_USB_V2=m
CONFIG_DVB_USB_AF9015=m
CONFIG_DVB_USB_AF9035=m
CONFIG_DVB_USB_ANYSEE=m
CONFIG_DVB_USB_AU6610=m
CONFIG_DVB_USB_AZ6007=m
CONFIG_DVB_USB_CE6230=m
CONFIG_DVB_USB_DVBSKY=m
CONFIG_DVB_USB_EC168=m
CONFIG_DVB_USB_GL861=m
CONFIG_DVB_USB_LME2510=m
CONFIG_DVB_USB_MXL111SF=m
CONFIG_DVB_USB_RTL28XXU=m
CONFIG_DVB_USB_ZD1301=m
CONFIG_DVB_USB=m
# CONFIG_DVB_USB_DEBUG is not set
CONFIG_DVB_USB_A800=m
CONFIG_DVB_USB_AF9005=m
CONFIG_DVB_USB_AF9005_REMOTE=m
CONFIG_DVB_USB_AZ6027=m
CONFIG_DVB_USB_CINERGY_T2=m
CONFIG_DVB_USB_CXUSB=m
# CONFIG_DVB_USB_CXUSB_ANALOG is not set
CONFIG_DVB_USB_DIB0700=m
CONFIG_DVB_USB_DIB3000MC=m
CONFIG_DVB_USB_DIBUSB_MB=m
# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
CONFIG_DVB_USB_DIBUSB_MC=m
CONFIG_DVB_USB_DIGITV=m
CONFIG_DVB_USB_DTT200U=m
CONFIG_DVB_USB_DTV5100=m
CONFIG_DVB_USB_DW2102=m
CONFIG_DVB_USB_GP8PSK=m
CONFIG_DVB_USB_M920X=m
CONFIG_DVB_USB_NOVA_T_USB2=m
CONFIG_DVB_USB_OPERA1=m
CONFIG_DVB_USB_PCTV452E=m
CONFIG_DVB_USB_TECHNISAT_USB2=m
CONFIG_DVB_USB_TTUSB2=m
CONFIG_DVB_USB_UMT_010=m
CONFIG_DVB_USB_VP702X=m
CONFIG_DVB_USB_VP7045=m
CONFIG_SMS_USB_DRV=m
CONFIG_DVB_TTUSB_BUDGET=m
CONFIG_DVB_TTUSB_DEC=m

#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=m
CONFIG_VIDEO_EM28XX_V4L2=m
CONFIG_VIDEO_EM28XX_ALSA=m
CONFIG_VIDEO_EM28XX_DVB=m
CONFIG_VIDEO_EM28XX_RC=m

#
# Software defined radio USB devices
#
CONFIG_USB_AIRSPY=m
CONFIG_USB_HACKRF=m
# CONFIG_USB_MSI2500 is not set
CONFIG_MEDIA_PCI_SUPPORT=y

#
# Media capture support
#
CONFIG_VIDEO_SOLO6X10=m
# CONFIG_VIDEO_TW5864 is not set
CONFIG_VIDEO_TW68=m
# CONFIG_VIDEO_TW686X is not set
# CONFIG_VIDEO_ZORAN is not set

#
# Media capture/analog TV support
#
CONFIG_VIDEO_DT3155=m
CONFIG_VIDEO_IVTV=m
CONFIG_VIDEO_IVTV_ALSA=m
CONFIG_VIDEO_FB_IVTV=m
CONFIG_VIDEO_HEXIUM_GEMINI=m
CONFIG_VIDEO_HEXIUM_ORION=m
CONFIG_VIDEO_MXB=m

#
# Media capture/analog/hybrid TV support
#
CONFIG_VIDEO_BT848=m
CONFIG_DVB_BT8XX=m
CONFIG_VIDEO_CX18=m
CONFIG_VIDEO_CX18_ALSA=m
CONFIG_VIDEO_CX23885=m
CONFIG_MEDIA_ALTERA_CI=m
CONFIG_VIDEO_CX25821=m
CONFIG_VIDEO_CX25821_ALSA=m
CONFIG_VIDEO_CX88=m
CONFIG_VIDEO_CX88_ALSA=m
CONFIG_VIDEO_CX88_BLACKBIRD=m
CONFIG_VIDEO_CX88_DVB=m
CONFIG_VIDEO_CX88_ENABLE_VP3054=y
CONFIG_VIDEO_CX88_VP3054=m
CONFIG_VIDEO_CX88_MPEG=m
CONFIG_VIDEO_SAA7134=m
CONFIG_VIDEO_SAA7134_ALSA=m
CONFIG_VIDEO_SAA7134_RC=y
CONFIG_VIDEO_SAA7134_DVB=m
CONFIG_VIDEO_SAA7134_GO7007=m
CONFIG_VIDEO_SAA7164=m

#
# Media digital TV PCI Adapters
#
CONFIG_DVB_B2C2_FLEXCOP_PCI=m
# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
CONFIG_DVB_DDBRIDGE=m
# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set
CONFIG_DVB_DM1105=m
CONFIG_MANTIS_CORE=m
CONFIG_DVB_MANTIS=m
CONFIG_DVB_HOPPER=m
# CONFIG_DVB_NETUP_UNIDVB is not set
CONFIG_DVB_NGENE=m
CONFIG_DVB_PLUTO2=m
CONFIG_DVB_PT1=m
CONFIG_DVB_PT3=m
CONFIG_DVB_SMIPCIE=m
CONFIG_DVB_BUDGET_CORE=m
CONFIG_DVB_BUDGET=m
CONFIG_DVB_BUDGET_CI=m
CONFIG_DVB_BUDGET_AV=m
# CONFIG_IPU_BRIDGE is not set
CONFIG_RADIO_ADAPTERS=m
CONFIG_RADIO_MAXIRADIO=m
CONFIG_RADIO_SAA7706H=m
CONFIG_RADIO_SHARK=m
CONFIG_RADIO_SHARK2=m
CONFIG_RADIO_SI4713=m
CONFIG_RADIO_TEA575X=m
CONFIG_RADIO_TEA5764=m
CONFIG_RADIO_TEF6862=m
CONFIG_RADIO_WL1273=m
CONFIG_USB_DSBR=m
CONFIG_USB_KEENE=m
CONFIG_USB_MA901=m
CONFIG_USB_MR800=m
CONFIG_USB_RAREMONO=m
CONFIG_RADIO_SI470X=m
CONFIG_USB_SI470X=m
CONFIG_I2C_SI470X=m
CONFIG_USB_SI4713=m
CONFIG_PLATFORM_SI4713=m
CONFIG_I2C_SI4713=m
CONFIG_MEDIA_PLATFORM_DRIVERS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
# CONFIG_SDR_PLATFORM_DRIVERS is not set
# CONFIG_DVB_PLATFORM_DRIVERS is not set
CONFIG_V4L_MEM2MEM_DRIVERS=y
# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
# CONFIG_VIDEO_MUX is not set

#
# Allegro DVT media platform drivers
#

#
# Amlogic media platform drivers
#

#
# Amphion drivers
#

#
# Aspeed media platform drivers
#

#
# Atmel media platform drivers
#

#
# Cadence media platform drivers
#
# CONFIG_VIDEO_CADENCE_CSI2RX is not set
# CONFIG_VIDEO_CADENCE_CSI2TX is not set

#
# Chips&Media media platform drivers
#

#
# Intel media platform drivers
#

#
# Marvell media platform drivers
#
# CONFIG_VIDEO_CAFE_CCIC is not set

#
# Mediatek media platform drivers
#

#
# Microchip Technology, Inc. media platform drivers
#

#
# NVidia media platform drivers
#

#
# NXP media platform drivers
#

#
# Qualcomm media platform drivers
#

#
# Renesas media platform drivers
#

#
# Rockchip media platform drivers
#

#
# Samsung media platform drivers
#

#
# STMicroelectronics media platform drivers
#

#
# Sunxi media platform drivers
#
# CONFIG_VIDEO_SUN4I_CSI is not set
CONFIG_VIDEO_SUN6I_CSI=m
# CONFIG_VIDEO_SUN6I_MIPI_CSI2 is not set
# CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2 is not set
CONFIG_VIDEO_SUN8I_DEINTERLACE=m
# CONFIG_VIDEO_SUN8I_ROTATE is not set

#
# Texas Instruments drivers
#

#
# Verisilicon media platform drivers
#
CONFIG_VIDEO_HANTRO=m
CONFIG_VIDEO_HANTRO_SUNXI=y

#
# VIA media platform drivers
#

#
# Xilinx media platform drivers
#
# CONFIG_VIDEO_XILINX is not set

#
# MMC/SDIO DVB adapters
#
CONFIG_SMS_SDIO_DRV=m
# CONFIG_V4L_TEST_DRIVERS is not set
# CONFIG_DVB_TEST_DRIVERS is not set
CONFIG_MEDIA_COMMON_OPTIONS=y

#
# common driver options
#
CONFIG_CYPRESS_FIRMWARE=m
CONFIG_TTPCI_EEPROM=m
CONFIG_UVC_COMMON=m
CONFIG_VIDEO_CX2341X=m
CONFIG_VIDEO_TVEEPROM=m
CONFIG_DVB_B2C2_FLEXCOP=m
CONFIG_VIDEO_SAA7146=m
CONFIG_VIDEO_SAA7146_VV=m
CONFIG_SMS_SIANO_MDTV=m
CONFIG_SMS_SIANO_RC=y
# CONFIG_SMS_SIANO_DEBUGFS is not set
CONFIG_VIDEOBUF2_CORE=m
CONFIG_VIDEOBUF2_V4L2=m
CONFIG_VIDEOBUF2_MEMOPS=m
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=m
CONFIG_VIDEOBUF2_DMA_SG=m
CONFIG_VIDEOBUF2_DVB=m
# end of Media drivers

#
# Media ancillary drivers
#
CONFIG_MEDIA_ATTACH=y

#
# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
#
CONFIG_VIDEO_IR_I2C=m
CONFIG_VIDEO_CAMERA_SENSOR=y
# CONFIG_VIDEO_AR0521 is not set
# CONFIG_VIDEO_HI556 is not set
# CONFIG_VIDEO_HI846 is not set
# CONFIG_VIDEO_HI847 is not set
# CONFIG_VIDEO_IMX208 is not set
# CONFIG_VIDEO_IMX214 is not set
CONFIG_VIDEO_IMX219=m
# CONFIG_VIDEO_IMX258 is not set
# CONFIG_VIDEO_IMX274 is not set
# CONFIG_VIDEO_IMX290 is not set
# CONFIG_VIDEO_IMX296 is not set
# CONFIG_VIDEO_IMX319 is not set
# CONFIG_VIDEO_IMX334 is not set
# CONFIG_VIDEO_IMX335 is not set
# CONFIG_VIDEO_IMX355 is not set
# CONFIG_VIDEO_IMX412 is not set
# CONFIG_VIDEO_IMX415 is not set
# CONFIG_VIDEO_MT9M001 is not set
# CONFIG_VIDEO_MT9M111 is not set
# CONFIG_VIDEO_MT9P031 is not set
# CONFIG_VIDEO_MT9T112 is not set
CONFIG_VIDEO_MT9V011=m
# CONFIG_VIDEO_MT9V032 is not set
# CONFIG_VIDEO_MT9V111 is not set
# CONFIG_VIDEO_OG01A1B is not set
# CONFIG_VIDEO_OV01A10 is not set
# CONFIG_VIDEO_OV02A10 is not set
# CONFIG_VIDEO_OV08D10 is not set
# CONFIG_VIDEO_OV08X40 is not set
# CONFIG_VIDEO_OV13858 is not set
# CONFIG_VIDEO_OV13B10 is not set
CONFIG_VIDEO_OV2640=m
# CONFIG_VIDEO_OV2659 is not set
# CONFIG_VIDEO_OV2680 is not set
# CONFIG_VIDEO_OV2685 is not set
# CONFIG_VIDEO_OV2740 is not set
# CONFIG_VIDEO_OV4689 is not set
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
# CONFIG_VIDEO_OV5647 is not set
# CONFIG_VIDEO_OV5648 is not set
# CONFIG_VIDEO_OV5670 is not set
# CONFIG_VIDEO_OV5675 is not set
# CONFIG_VIDEO_OV5693 is not set
# CONFIG_VIDEO_OV5695 is not set
# CONFIG_VIDEO_OV6650 is not set
# CONFIG_VIDEO_OV7251 is not set
CONFIG_VIDEO_OV7640=m
# CONFIG_VIDEO_OV7670 is not set
# CONFIG_VIDEO_OV772X is not set
# CONFIG_VIDEO_OV7740 is not set
# CONFIG_VIDEO_OV8856 is not set
# CONFIG_VIDEO_OV8858 is not set
# CONFIG_VIDEO_OV8865 is not set
# CONFIG_VIDEO_OV9282 is not set
# CONFIG_VIDEO_OV9640 is not set
# CONFIG_VIDEO_OV9650 is not set
# CONFIG_VIDEO_OV9734 is not set
# CONFIG_VIDEO_RDACM20 is not set
# CONFIG_VIDEO_RDACM21 is not set
# CONFIG_VIDEO_RJ54N1 is not set
# CONFIG_VIDEO_S5C73M3 is not set
# CONFIG_VIDEO_S5K5BAF is not set
# CONFIG_VIDEO_S5K6A3 is not set
# CONFIG_VIDEO_ST_VGXY61 is not set
# CONFIG_VIDEO_CCS is not set
# CONFIG_VIDEO_ET8EK8 is not set

#
# Lens drivers
#
# CONFIG_VIDEO_AD5820 is not set
# CONFIG_VIDEO_AK7375 is not set
# CONFIG_VIDEO_DW9714 is not set
# CONFIG_VIDEO_DW9719 is not set
# CONFIG_VIDEO_DW9768 is not set
# CONFIG_VIDEO_DW9807_VCM is not set
# end of Lens drivers

#
# Flash devices
#
# CONFIG_VIDEO_ADP1653 is not set
# CONFIG_VIDEO_LM3560 is not set
# CONFIG_VIDEO_LM3646 is not set
# end of Flash devices

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_CS3308=m
CONFIG_VIDEO_CS5345=m
CONFIG_VIDEO_CS53L32A=m
CONFIG_VIDEO_MSP3400=m
CONFIG_VIDEO_SONY_BTF_MPX=m
# CONFIG_VIDEO_TDA1997X is not set
CONFIG_VIDEO_TDA7432=m
CONFIG_VIDEO_TDA9840=m
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
# CONFIG_VIDEO_TLV320AIC23B is not set
CONFIG_VIDEO_TVAUDIO=m
CONFIG_VIDEO_UDA1342=m
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_WM8739=m
CONFIG_VIDEO_WM8775=m
# end of Audio decoders, processors and mixers

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders

#
# Video decoders
#
# CONFIG_VIDEO_ADV7180 is not set
# CONFIG_VIDEO_ADV7183 is not set
# CONFIG_VIDEO_ADV748X is not set
# CONFIG_VIDEO_ADV7604 is not set
# CONFIG_VIDEO_ADV7842 is not set
# CONFIG_VIDEO_BT819 is not set
# CONFIG_VIDEO_BT856 is not set
# CONFIG_VIDEO_BT866 is not set
# CONFIG_VIDEO_ISL7998X is not set
# CONFIG_VIDEO_KS0127 is not set
# CONFIG_VIDEO_MAX9286 is not set
# CONFIG_VIDEO_ML86V7667 is not set
# CONFIG_VIDEO_SAA7110 is not set
CONFIG_VIDEO_SAA711X=m
# CONFIG_VIDEO_TC358743 is not set
# CONFIG_VIDEO_TC358746 is not set
# CONFIG_VIDEO_TVP514X is not set
CONFIG_VIDEO_TVP5150=m
# CONFIG_VIDEO_TVP7002 is not set
CONFIG_VIDEO_TW2804=m
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=m
# CONFIG_VIDEO_TW9910 is not set
# CONFIG_VIDEO_VPX3220 is not set

#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=m
CONFIG_VIDEO_CX25840=m
# end of Video decoders

#
# Video encoders
#
# CONFIG_VIDEO_ADV7170 is not set
# CONFIG_VIDEO_ADV7175 is not set
# CONFIG_VIDEO_ADV7343 is not set
# CONFIG_VIDEO_ADV7393 is not set
# CONFIG_VIDEO_AK881X is not set
CONFIG_VIDEO_SAA7127=m
# CONFIG_VIDEO_SAA7185 is not set
# CONFIG_VIDEO_THS8200 is not set
# end of Video encoders

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
CONFIG_VIDEO_UPD64083=m
# end of Video improvement chips

#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips

#
# SDR tuner chips
#
# CONFIG_SDR_MAX2175 is not set
# end of SDR tuner chips

#
# Miscellaneous helper chips
#
# CONFIG_VIDEO_I2C is not set
CONFIG_VIDEO_M52790=m
# CONFIG_VIDEO_ST_MIPID02 is not set
# CONFIG_VIDEO_THS7303 is not set
# end of Miscellaneous helper chips

#
# Video serializers and deserializers
#
# CONFIG_VIDEO_DS90UB913 is not set
# CONFIG_VIDEO_DS90UB953 is not set
# CONFIG_VIDEO_DS90UB960 is not set
# end of Video serializers and deserializers

#
# Media SPI Adapters
#
# CONFIG_CXD2880_SPI_DRV is not set
# CONFIG_VIDEO_GS1662 is not set
# end of Media SPI Adapters

CONFIG_MEDIA_TUNER=m

#
# Customize TV tuners
#
CONFIG_MEDIA_TUNER_E4000=m
CONFIG_MEDIA_TUNER_FC0011=m
CONFIG_MEDIA_TUNER_FC0012=m
CONFIG_MEDIA_TUNER_FC0013=m
CONFIG_MEDIA_TUNER_FC2580=m
CONFIG_MEDIA_TUNER_IT913X=m
CONFIG_MEDIA_TUNER_M88RS6000T=m
CONFIG_MEDIA_TUNER_MAX2165=m
CONFIG_MEDIA_TUNER_MC44S803=m
# CONFIG_MEDIA_TUNER_MSI001 is not set
CONFIG_MEDIA_TUNER_MT2060=m
CONFIG_MEDIA_TUNER_MT2063=m
CONFIG_MEDIA_TUNER_MT20XX=m
CONFIG_MEDIA_TUNER_MT2131=m
CONFIG_MEDIA_TUNER_MT2266=m
CONFIG_MEDIA_TUNER_MXL301RF=m
CONFIG_MEDIA_TUNER_MXL5005S=m
CONFIG_MEDIA_TUNER_MXL5007T=m
CONFIG_MEDIA_TUNER_QM1D1B0004=m
CONFIG_MEDIA_TUNER_QM1D1C0042=m
CONFIG_MEDIA_TUNER_QT1010=m
CONFIG_MEDIA_TUNER_R820T=m
CONFIG_MEDIA_TUNER_SI2157=m
CONFIG_MEDIA_TUNER_SIMPLE=m
CONFIG_MEDIA_TUNER_TDA18212=m
CONFIG_MEDIA_TUNER_TDA18218=m
CONFIG_MEDIA_TUNER_TDA18250=m
CONFIG_MEDIA_TUNER_TDA18271=m
CONFIG_MEDIA_TUNER_TDA827X=m
CONFIG_MEDIA_TUNER_TDA8290=m
CONFIG_MEDIA_TUNER_TDA9887=m
CONFIG_MEDIA_TUNER_TEA5761=m
CONFIG_MEDIA_TUNER_TEA5767=m
CONFIG_MEDIA_TUNER_TUA9001=m
CONFIG_MEDIA_TUNER_XC2028=m
CONFIG_MEDIA_TUNER_XC4000=m
CONFIG_MEDIA_TUNER_XC5000=m
# end of Customize TV tuners

#
# Customise DVB Frontends
#

#
# Multistandard (satellite) frontends
#
CONFIG_DVB_M88DS3103=m
CONFIG_DVB_MXL5XX=m
CONFIG_DVB_STB0899=m
CONFIG_DVB_STB6100=m
CONFIG_DVB_STV090x=m
CONFIG_DVB_STV0910=m
CONFIG_DVB_STV6110x=m
CONFIG_DVB_STV6111=m

#
# Multistandard (cable + terrestrial) frontends
#
CONFIG_DVB_DRXK=m
CONFIG_DVB_MN88472=m
CONFIG_DVB_MN88473=m
CONFIG_DVB_SI2165=m
CONFIG_DVB_TDA18271C2DD=m

#
# DVB-S (satellite) frontends
#
CONFIG_DVB_CX24110=m
CONFIG_DVB_CX24116=m
CONFIG_DVB_CX24117=m
CONFIG_DVB_CX24120=m
CONFIG_DVB_CX24123=m
CONFIG_DVB_DS3000=m
CONFIG_DVB_MB86A16=m
CONFIG_DVB_MT312=m
CONFIG_DVB_S5H1420=m
CONFIG_DVB_SI21XX=m
CONFIG_DVB_STB6000=m
CONFIG_DVB_STV0288=m
CONFIG_DVB_STV0299=m
CONFIG_DVB_STV0900=m
CONFIG_DVB_STV6110=m
CONFIG_DVB_TDA10071=m
CONFIG_DVB_TDA10086=m
CONFIG_DVB_TDA8083=m
CONFIG_DVB_TDA8261=m
CONFIG_DVB_TDA826X=m
CONFIG_DVB_TS2020=m
CONFIG_DVB_TUA6100=m
CONFIG_DVB_TUNER_CX24113=m
CONFIG_DVB_TUNER_ITD1000=m
CONFIG_DVB_VES1X93=m
CONFIG_DVB_ZL10036=m
CONFIG_DVB_ZL10039=m

#
# DVB-T (terrestrial) frontends
#
CONFIG_DVB_AF9013=m
CONFIG_DVB_AS102_FE=m
CONFIG_DVB_CX22700=m
CONFIG_DVB_CX22702=m
CONFIG_DVB_CXD2820R=m
CONFIG_DVB_CXD2841ER=m
CONFIG_DVB_DIB3000MB=m
CONFIG_DVB_DIB3000MC=m
CONFIG_DVB_DIB7000M=m
CONFIG_DVB_DIB7000P=m
# CONFIG_DVB_DIB9000 is not set
CONFIG_DVB_DRXD=m
CONFIG_DVB_EC100=m
CONFIG_DVB_GP8PSK_FE=m
CONFIG_DVB_L64781=m
CONFIG_DVB_MT352=m
CONFIG_DVB_NXT6000=m
CONFIG_DVB_RTL2830=m
CONFIG_DVB_RTL2832=m
CONFIG_DVB_RTL2832_SDR=m
# CONFIG_DVB_S5H1432 is not set
CONFIG_DVB_SI2168=m
CONFIG_DVB_SP887X=m
CONFIG_DVB_STV0367=m
CONFIG_DVB_TDA10048=m
CONFIG_DVB_TDA1004X=m
CONFIG_DVB_ZD1301_DEMOD=m
CONFIG_DVB_ZL10353=m
# CONFIG_DVB_CXD2880 is not set

#
# DVB-C (cable) frontends
#
CONFIG_DVB_STV0297=m
CONFIG_DVB_TDA10021=m
CONFIG_DVB_TDA10023=m
CONFIG_DVB_VES1820=m

#
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
#
CONFIG_DVB_AU8522=m
CONFIG_DVB_AU8522_DTV=m
CONFIG_DVB_AU8522_V4L=m
CONFIG_DVB_BCM3510=m
CONFIG_DVB_LG2160=m
CONFIG_DVB_LGDT3305=m
CONFIG_DVB_LGDT3306A=m
CONFIG_DVB_LGDT330X=m
CONFIG_DVB_MXL692=m
CONFIG_DVB_NXT200X=m
CONFIG_DVB_OR51132=m
CONFIG_DVB_OR51211=m
CONFIG_DVB_S5H1409=m
CONFIG_DVB_S5H1411=m

#
# ISDB-T (terrestrial) frontends
#
CONFIG_DVB_DIB8000=m
CONFIG_DVB_MB86A20S=m
CONFIG_DVB_S921=m

#
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
#
# CONFIG_DVB_MN88443X is not set
CONFIG_DVB_TC90522=m

#
# Digital terrestrial only tuners/PLL
#
CONFIG_DVB_PLL=m
CONFIG_DVB_TUNER_DIB0070=m
CONFIG_DVB_TUNER_DIB0090=m

#
# SEC control devices for DVB-S
#
CONFIG_DVB_A8293=m
CONFIG_DVB_AF9033=m
# CONFIG_DVB_ASCOT2E is not set
CONFIG_DVB_ATBM8830=m
# CONFIG_DVB_HELENE is not set
# CONFIG_DVB_HORUS3A is not set
CONFIG_DVB_ISL6405=m
CONFIG_DVB_ISL6421=m
CONFIG_DVB_ISL6423=m
CONFIG_DVB_IX2505V=m
# CONFIG_DVB_LGS8GL5 is not set
CONFIG_DVB_LGS8GXX=m
CONFIG_DVB_LNBH25=m
# CONFIG_DVB_LNBH29 is not set
CONFIG_DVB_LNBP21=m
CONFIG_DVB_LNBP22=m
CONFIG_DVB_M88RS2000=m
CONFIG_DVB_TDA665x=m
CONFIG_DVB_DRX39XYJ=m

#
# Common Interface (EN50221) controller drivers
#
CONFIG_DVB_CXD2099=m
CONFIG_DVB_SP2=m
# end of Customise DVB Frontends

#
# Tools to develop new frontends
#
CONFIG_DVB_DUMMY_FE=m
# end of Media ancillary drivers

#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
CONFIG_SCREEN_INFO=y
CONFIG_VIDEO_CMDLINE=y
CONFIG_VIDEO_NOMODESET=y
CONFIG_AUXDISPLAY=y
# CONFIG_HD44780 is not set
# CONFIG_IMG_ASCII_LCD is not set
# CONFIG_HT16K33 is not set
# CONFIG_LCD2S is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_DRM=m
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_KMS_HELPER=m
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
CONFIG_DRM_LOAD_EDID_FIRMWARE=y
CONFIG_DRM_DP_AUX_BUS=m
CONFIG_DRM_DISPLAY_HELPER=m
CONFIG_DRM_DISPLAY_DP_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_TTM=m
CONFIG_DRM_VRAM_HELPER=m
CONFIG_DRM_TTM_HELPER=m
CONFIG_DRM_GEM_DMA_HELPER=m
CONFIG_DRM_GEM_SHMEM_HELPER=m
CONFIG_DRM_SUBALLOC_HELPER=m
CONFIG_DRM_SCHED=m

#
# I2C encoder or helper chips
#
CONFIG_DRM_I2C_CH7006=m
CONFIG_DRM_I2C_SIL164=m
CONFIG_DRM_I2C_NXP_TDA998X=m
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips

#
# ARM devices
#
CONFIG_DRM_HDLCD=m
# CONFIG_DRM_HDLCD_SHOW_UNDERRUN is not set
CONFIG_DRM_MALI_DISPLAY=m
# CONFIG_DRM_KOMEDA is not set
# end of ARM devices

CONFIG_DRM_RADEON=m
CONFIG_DRM_RADEON_USERPTR=y
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
CONFIG_DRM_VGEM=m
# CONFIG_DRM_VKMS is not set
# CONFIG_DRM_VMWGFX is not set
CONFIG_DRM_UDL=m
CONFIG_DRM_AST=m
CONFIG_DRM_MGAG200=m
CONFIG_DRM_SUN4I=m
CONFIG_DRM_SUN6I_DSI=m
CONFIG_DRM_SUN8I_DW_HDMI=m
CONFIG_DRM_SUN8I_MIXER=m
CONFIG_DRM_SUN8I_TCON_TOP=m
CONFIG_DRM_QXL=m
CONFIG_DRM_VIRTIO_GPU=m
# CONFIG_DRM_VIRTIO_GPU_KMS is not set
CONFIG_DRM_PANEL=y

#
# Display Panels
#
# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set
# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
# CONFIG_DRM_PANEL_DSI_CM is not set
# CONFIG_DRM_PANEL_LVDS is not set
CONFIG_DRM_PANEL_SIMPLE=m
# CONFIG_DRM_PANEL_EDP is not set
# CONFIG_DRM_PANEL_EBBG_FT8719 is not set
# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
# CONFIG_DRM_PANEL_JDI_R63452 is not set
# CONFIG_DRM_PANEL_KHADAS_TS050 is not set
# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
# CONFIG_DRM_PANEL_LG_LG4573 is not set
# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set
# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set
# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set
# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set
# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set
# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set
# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_CHIPONE_ICN6211 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
# CONFIG_DRM_CROS_EC_ANX7688 is not set
CONFIG_DRM_DISPLAY_CONNECTOR=m
# CONFIG_DRM_ITE_IT6505 is not set
# CONFIG_DRM_LONTIUM_LT8912B is not set
# CONFIG_DRM_LONTIUM_LT9211 is not set
CONFIG_DRM_LONTIUM_LT9611=m
# CONFIG_DRM_LONTIUM_LT9611UXC is not set
# CONFIG_DRM_ITE_IT66121 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
CONFIG_DRM_NWL_MIPI_DSI=m
CONFIG_DRM_NXP_PTN3460=m
CONFIG_DRM_PARADE_PS8622=m
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_SAMSUNG_DSIM is not set
CONFIG_DRM_SIL_SII8620=m
CONFIG_DRM_SII902X=m
# CONFIG_DRM_SII9234 is not set
CONFIG_DRM_SIMPLE_BRIDGE=m
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
CONFIG_DRM_TOSHIBA_TC358767=m
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_DLPC3433 is not set
CONFIG_DRM_TI_TFP410=m
# CONFIG_DRM_TI_SN65DSI83 is not set
CONFIG_DRM_TI_SN65DSI86=m
# CONFIG_DRM_TI_TPD12S015 is not set
CONFIG_DRM_ANALOGIX_ANX6345=m
CONFIG_DRM_ANALOGIX_ANX78XX=m
CONFIG_DRM_ANALOGIX_DP=m
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
CONFIG_DRM_I2C_ADV7511=m
CONFIG_DRM_I2C_ADV7511_AUDIO=y
CONFIG_DRM_I2C_ADV7511_CEC=y
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=m
# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set
CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
CONFIG_DRM_DW_HDMI_CEC=m
# end of Display Interface Bridges

# CONFIG_DRM_LOONGSON is not set
CONFIG_DRM_ETNAVIV=m
CONFIG_DRM_ETNAVIV_THERMAL=y
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
# CONFIG_DRM_LOGICVC is not set
# CONFIG_DRM_ARCPGU is not set
CONFIG_DRM_BOCHS=m
CONFIG_DRM_CIRRUS_QEMU=m
# CONFIG_DRM_GM12U320 is not set
# CONFIG_DRM_PANEL_MIPI_DBI is not set
# CONFIG_DRM_SIMPLEDRM is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9163 is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
CONFIG_DRM_PL111=m
CONFIG_DRM_LIMA=m
CONFIG_DRM_PANFROST=m
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_GUD is not set
# CONFIG_DRM_SSD130X is not set
CONFIG_DRM_LEGACY=y
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y

#
# Frame buffer Devices
#
CONFIG_FB=y
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_ARMCLCD is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_UVESA is not set
CONFIG_FB_EFI=y
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SM501 is not set
# CONFIG_FB_SMSCUFX is not set
CONFIG_FB_UDL=m
# CONFIG_FB_IBM_GXT4500 is not set
CONFIG_FB_VIRTUAL=m
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
CONFIG_FB_SIMPLE=y
CONFIG_FB_SSD1307=m
# CONFIG_FB_SM712 is not set
CONFIG_FB_CORE=y
CONFIG_FB_NOTIFY=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_DEVICE=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_DMAMEM_HELPERS=y
CONFIG_FB_IOMEM_FOPS=y
CONFIG_FB_IOMEM_HELPERS=y
CONFIG_FB_SYSMEM_HELPERS=y
CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
CONFIG_FB_BACKLIGHT=m
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_L4F00242T03 is not set
# CONFIG_LCD_LMS283GF05 is not set
# CONFIG_LCD_LTV350QV is not set
# CONFIG_LCD_ILI922X is not set
# CONFIG_LCD_ILI9320 is not set
# CONFIG_LCD_TDO24M is not set
# CONFIG_LCD_VGG2432A4 is not set
CONFIG_LCD_PLATFORM=m
# CONFIG_LCD_AMS369FG06 is not set
# CONFIG_LCD_LMS501KF03 is not set
# CONFIG_LCD_HX8357 is not set
# CONFIG_LCD_OTM3225A is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_KTD253 is not set
# CONFIG_BACKLIGHT_KTZ8866 is not set
CONFIG_BACKLIGHT_PWM=m
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
CONFIG_BACKLIGHT_LP855X=m
CONFIG_BACKLIGHT_GPIO=m
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# CONFIG_BACKLIGHT_LED is not set
# end of Backlight & LCD device support

CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
# end of Console display driver support

CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_LOGO_LINUX_CLUT224=y
# end of Graphics support

# CONFIG_DRM_ACCEL is not set
CONFIG_SOUND=y
CONFIG_SOUND_OSS_CORE=y
CONFIG_SOUND_OSS_CORE_PRECLAIM=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=m
CONFIG_SND_SEQ_DEVICE=m
CONFIG_SND_RAWMIDI=m
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=m
CONFIG_SND_PCM_OSS=m
CONFIG_SND_PCM_OSS_PLUGINS=y
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=m
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_CTL_FAST_LOOKUP is not set
# CONFIG_SND_DEBUG is not set
# CONFIG_SND_CTL_INPUT_VALIDATION is not set
CONFIG_SND_VMASTER=y
CONFIG_SND_CTL_LED=m
CONFIG_SND_SEQUENCER=m
CONFIG_SND_SEQ_DUMMY=m
CONFIG_SND_SEQUENCER_OSS=m
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
CONFIG_SND_SEQ_MIDI_EVENT=m
CONFIG_SND_SEQ_MIDI=m
CONFIG_SND_SEQ_MIDI_EMUL=m
CONFIG_SND_SEQ_VIRMIDI=m
# CONFIG_SND_SEQ_UMP is not set
CONFIG_SND_MPU401_UART=m
CONFIG_SND_OPL3_LIB=m
CONFIG_SND_OPL3_LIB_SEQ=m
CONFIG_SND_VX_LIB=m
CONFIG_SND_AC97_CODEC=m
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
# CONFIG_SND_PCMTEST is not set
CONFIG_SND_VIRMIDI=m
CONFIG_SND_MTPAV=m
CONFIG_SND_SERIAL_U16550=m
# CONFIG_SND_SERIAL_GENERIC is not set
CONFIG_SND_MPU401=m
CONFIG_SND_AC97_POWER_SAVE=y
CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
CONFIG_SND_PCI=y
CONFIG_SND_AD1889=m
# CONFIG_SND_ALS300 is not set
# CONFIG_SND_ALI5451 is not set
CONFIG_SND_ATIIXP=m
CONFIG_SND_ATIIXP_MODEM=m
CONFIG_SND_AU8810=m
CONFIG_SND_AU8820=m
CONFIG_SND_AU8830=m
# CONFIG_SND_AW2 is not set
# CONFIG_SND_AZT3328 is not set
CONFIG_SND_BT87X=m
# CONFIG_SND_BT87X_OVERCLOCK is not set
CONFIG_SND_CA0106=m
CONFIG_SND_CMIPCI=m
CONFIG_SND_OXYGEN_LIB=m
CONFIG_SND_OXYGEN=m
CONFIG_SND_CS4281=m
CONFIG_SND_CS46XX=m
CONFIG_SND_CS46XX_NEW_DSP=y
CONFIG_SND_CTXFI=m
CONFIG_SND_DARLA20=m
CONFIG_SND_GINA20=m
CONFIG_SND_LAYLA20=m
CONFIG_SND_DARLA24=m
CONFIG_SND_GINA24=m
CONFIG_SND_LAYLA24=m
CONFIG_SND_MONA=m
CONFIG_SND_MIA=m
CONFIG_SND_ECHO3G=m
CONFIG_SND_INDIGO=m
CONFIG_SND_INDIGOIO=m
CONFIG_SND_INDIGODJ=m
CONFIG_SND_INDIGOIOX=m
CONFIG_SND_INDIGODJX=m
# CONFIG_SND_EMU10K1 is not set
# CONFIG_SND_EMU10K1X is not set
CONFIG_SND_ENS1370=m
CONFIG_SND_ENS1371=m
# CONFIG_SND_ES1938 is not set
# CONFIG_SND_ES1968 is not set
CONFIG_SND_FM801=m
CONFIG_SND_FM801_TEA575X_BOOL=y
CONFIG_SND_HDSP=m
CONFIG_SND_HDSPM=m
# CONFIG_SND_ICE1712 is not set
CONFIG_SND_ICE1724=m
CONFIG_SND_INTEL8X0=m
CONFIG_SND_INTEL8X0M=m
CONFIG_SND_KORG1212=m
CONFIG_SND_LOLA=m
CONFIG_SND_LX6464ES=m
# CONFIG_SND_MAESTRO3 is not set
CONFIG_SND_MIXART=m
CONFIG_SND_NM256=m
CONFIG_SND_PCXHR=m
CONFIG_SND_RIPTIDE=m
CONFIG_SND_RME32=m
CONFIG_SND_RME96=m
CONFIG_SND_RME9652=m
# CONFIG_SND_SONICVIBES is not set
# CONFIG_SND_TRIDENT is not set
CONFIG_SND_VIA82XX=m
CONFIG_SND_VIA82XX_MODEM=m
CONFIG_SND_VIRTUOSO=m
CONFIG_SND_VX222=m
CONFIG_SND_YMFPCI=m

#
# HD-Audio
#
CONFIG_SND_HDA=m
CONFIG_SND_HDA_GENERIC_LEDS=y
CONFIG_SND_HDA_INTEL=m
CONFIG_SND_HDA_HWDEP=y
CONFIG_SND_HDA_RECONFIG=y
CONFIG_SND_HDA_INPUT_BEEP=y
CONFIG_SND_HDA_INPUT_BEEP_MODE=0
CONFIG_SND_HDA_PATCH_LOADER=y
# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
# CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set
# CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set
CONFIG_SND_HDA_CODEC_REALTEK=m
CONFIG_SND_HDA_CODEC_ANALOG=m
CONFIG_SND_HDA_CODEC_SIGMATEL=m
CONFIG_SND_HDA_CODEC_VIA=m
CONFIG_SND_HDA_CODEC_HDMI=m
CONFIG_SND_HDA_CODEC_CIRRUS=m
# CONFIG_SND_HDA_CODEC_CS8409 is not set
CONFIG_SND_HDA_CODEC_CONEXANT=m
CONFIG_SND_HDA_CODEC_CA0110=m
CONFIG_SND_HDA_CODEC_CA0132=m
CONFIG_SND_HDA_CODEC_CA0132_DSP=y
CONFIG_SND_HDA_CODEC_CMEDIA=m
CONFIG_SND_HDA_CODEC_SI3054=m
CONFIG_SND_HDA_GENERIC=m
CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
# CONFIG_SND_HDA_CTL_DEV_ID is not set
# end of HD-Audio

CONFIG_SND_HDA_CORE=m
CONFIG_SND_HDA_DSP_LOADER=y
CONFIG_SND_HDA_COMPONENT=y
CONFIG_SND_HDA_PREALLOC_SIZE=4096
CONFIG_SND_INTEL_NHLT=y
CONFIG_SND_INTEL_DSP_CONFIG=m
CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m
CONFIG_SND_SPI=y
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
# CONFIG_SND_USB_AUDIO_MIDI_V2 is not set
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
# CONFIG_SND_BCD2000 is not set
CONFIG_SND_USB_LINE6=m
CONFIG_SND_USB_POD=m
CONFIG_SND_USB_PODHD=m
CONFIG_SND_USB_TONEPORT=m
CONFIG_SND_USB_VARIAX=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
# CONFIG_SND_SOC_ADI is not set
CONFIG_SND_SOC_AMD_ACP=m
# CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH is not set
# CONFIG_SND_SOC_AMD_CZ_RT5645_MACH is not set
# CONFIG_SND_SOC_AMD_ST_ES8336_MACH is not set
# CONFIG_SND_AMD_ACP_CONFIG is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
# CONFIG_SND_DESIGNWARE_I2S is not set

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
CONFIG_SND_SOC_FSL_ASRC=m
CONFIG_SND_SOC_FSL_SAI=m
# CONFIG_SND_SOC_FSL_MQS is not set
CONFIG_SND_SOC_FSL_AUDMIX=m
# CONFIG_SND_SOC_FSL_SSI is not set
CONFIG_SND_SOC_FSL_SPDIF=m
# CONFIG_SND_SOC_FSL_ESAI is not set
CONFIG_SND_SOC_FSL_MICFIL=m
CONFIG_SND_SOC_FSL_EASRC=m
# CONFIG_SND_SOC_FSL_XCVR is not set
CONFIG_SND_SOC_FSL_UTILS=m
# CONFIG_SND_SOC_FSL_RPMSG is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs

# CONFIG_SND_SOC_CHV3_I2S is not set
CONFIG_SND_I2S_HI6210_I2S=m
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set

#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support

#
# Allwinner SoC Audio support
#
CONFIG_SND_SUN4I_CODEC=m
CONFIG_SND_SUN8I_CODEC=m
CONFIG_SND_SUN8I_CODEC_ANALOG=m
CONFIG_SND_SUN50I_CODEC_ANALOG=m
CONFIG_SND_SUN4I_I2S=m
CONFIG_SND_SUN4I_SPDIF=m
# CONFIG_SND_SUN50I_DMIC is not set
CONFIG_SND_SUN9I_HDMI_AUDIO=m
CONFIG_SND_SUN8I_ADDA_PR_REGMAP=m
# end of Allwinner SoC Audio support

# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# CONFIG_SND_SOC_XTFPGA_I2S is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
# CONFIG_SND_SOC_AC97_CODEC is not set
# CONFIG_SND_SOC_ADAU1372_I2C is not set
# CONFIG_SND_SOC_ADAU1372_SPI is not set
# CONFIG_SND_SOC_ADAU1701 is not set
# CONFIG_SND_SOC_ADAU1761_I2C is not set
# CONFIG_SND_SOC_ADAU1761_SPI is not set
# CONFIG_SND_SOC_ADAU7002 is not set
# CONFIG_SND_SOC_ADAU7118_HW is not set
# CONFIG_SND_SOC_ADAU7118_I2C is not set
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_AK4118 is not set
# CONFIG_SND_SOC_AK4375 is not set
# CONFIG_SND_SOC_AK4458 is not set
# CONFIG_SND_SOC_AK4554 is not set
# CONFIG_SND_SOC_AK4613 is not set
# CONFIG_SND_SOC_AK4642 is not set
# CONFIG_SND_SOC_AK5386 is not set
# CONFIG_SND_SOC_AK5558 is not set
# CONFIG_SND_SOC_ALC5623 is not set
# CONFIG_SND_SOC_AUDIO_IIO_AUX is not set
# CONFIG_SND_SOC_AW8738 is not set
# CONFIG_SND_SOC_AW88395 is not set
# CONFIG_SND_SOC_AW88261 is not set
# CONFIG_SND_SOC_BD28623 is not set
# CONFIG_SND_SOC_BT_SCO is not set
# CONFIG_SND_SOC_CHV3_CODEC is not set
CONFIG_SND_SOC_CROS_EC_CODEC=m
# CONFIG_SND_SOC_CS35L32 is not set
# CONFIG_SND_SOC_CS35L33 is not set
# CONFIG_SND_SOC_CS35L34 is not set
# CONFIG_SND_SOC_CS35L35 is not set
# CONFIG_SND_SOC_CS35L36 is not set
# CONFIG_SND_SOC_CS35L41_SPI is not set
# CONFIG_SND_SOC_CS35L41_I2C is not set
# CONFIG_SND_SOC_CS35L45_SPI is not set
# CONFIG_SND_SOC_CS35L45_I2C is not set
# CONFIG_SND_SOC_CS35L56_I2C is not set
# CONFIG_SND_SOC_CS35L56_SPI is not set
# CONFIG_SND_SOC_CS35L56_SDW is not set
# CONFIG_SND_SOC_CS42L42 is not set
# CONFIG_SND_SOC_CS42L42_SDW is not set
# CONFIG_SND_SOC_CS42L51_I2C is not set
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_CS42L73 is not set
# CONFIG_SND_SOC_CS42L83 is not set
# CONFIG_SND_SOC_CS4234 is not set
# CONFIG_SND_SOC_CS4265 is not set
# CONFIG_SND_SOC_CS4270 is not set
# CONFIG_SND_SOC_CS4271_I2C is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_CS42XX8_I2C is not set
# CONFIG_SND_SOC_CS43130 is not set
# CONFIG_SND_SOC_CS4341 is not set
# CONFIG_SND_SOC_CS4349 is not set
# CONFIG_SND_SOC_CS53L30 is not set
# CONFIG_SND_SOC_CX2072X is not set
# CONFIG_SND_SOC_DA7213 is not set
CONFIG_SND_SOC_DMIC=m
CONFIG_SND_SOC_HDMI_CODEC=m
# CONFIG_SND_SOC_ES7134 is not set
# CONFIG_SND_SOC_ES7241 is not set
# CONFIG_SND_SOC_ES8316 is not set
# CONFIG_SND_SOC_ES8326 is not set
CONFIG_SND_SOC_ES8328=m
CONFIG_SND_SOC_ES8328_I2C=m
CONFIG_SND_SOC_ES8328_SPI=m
# CONFIG_SND_SOC_GTM601 is not set
# CONFIG_SND_SOC_HDA is not set
# CONFIG_SND_SOC_ICS43432 is not set
# CONFIG_SND_SOC_IDT821034 is not set
# CONFIG_SND_SOC_INNO_RK3036 is not set
# CONFIG_SND_SOC_MAX98088 is not set
# CONFIG_SND_SOC_MAX98090 is not set
CONFIG_SND_SOC_MAX98357A=m
# CONFIG_SND_SOC_MAX98504 is not set
# CONFIG_SND_SOC_MAX9867 is not set
CONFIG_SND_SOC_MAX98927=m
# CONFIG_SND_SOC_MAX98520 is not set
# CONFIG_SND_SOC_MAX98363 is not set
# CONFIG_SND_SOC_MAX98373_I2C is not set
# CONFIG_SND_SOC_MAX98373_SDW is not set
# CONFIG_SND_SOC_MAX98388 is not set
# CONFIG_SND_SOC_MAX98390 is not set
# CONFIG_SND_SOC_MAX98396 is not set
# CONFIG_SND_SOC_MAX9860 is not set
CONFIG_SND_SOC_MSM8916_WCD_ANALOG=y
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y
# CONFIG_SND_SOC_PCM1681 is not set
# CONFIG_SND_SOC_PCM1789_I2C is not set
# CONFIG_SND_SOC_PCM179X_I2C is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_I2C is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3060_I2C is not set
# CONFIG_SND_SOC_PCM3060_SPI is not set
CONFIG_SND_SOC_PCM3168A=m
CONFIG_SND_SOC_PCM3168A_I2C=m
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM5102A is not set
# CONFIG_SND_SOC_PCM512x_I2C is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
# CONFIG_SND_SOC_PEB2466 is not set
CONFIG_SND_SOC_RK3328=m
# CONFIG_SND_SOC_RT1017_SDCA_SDW is not set
# CONFIG_SND_SOC_RT1308_SDW is not set
# CONFIG_SND_SOC_RT1316_SDW is not set
# CONFIG_SND_SOC_RT1318_SDW is not set
# CONFIG_SND_SOC_RT5616 is not set
# CONFIG_SND_SOC_RT5631 is not set
# CONFIG_SND_SOC_RT5640 is not set
# CONFIG_SND_SOC_RT5659 is not set
# CONFIG_SND_SOC_RT5682_SDW is not set
# CONFIG_SND_SOC_RT700_SDW is not set
# CONFIG_SND_SOC_RT711_SDW is not set
# CONFIG_SND_SOC_RT711_SDCA_SDW is not set
# CONFIG_SND_SOC_RT712_SDCA_SDW is not set
# CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW is not set
# CONFIG_SND_SOC_RT722_SDCA_SDW is not set
# CONFIG_SND_SOC_RT715_SDW is not set
# CONFIG_SND_SOC_RT715_SDCA_SDW is not set
# CONFIG_SND_SOC_RT9120 is not set
# CONFIG_SND_SOC_SDW_MOCKUP is not set
# CONFIG_SND_SOC_SGTL5000 is not set
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
# CONFIG_SND_SOC_SIMPLE_MUX is not set
# CONFIG_SND_SOC_SMA1303 is not set
# CONFIG_SND_SOC_SPDIF is not set
# CONFIG_SND_SOC_SRC4XXX_I2C is not set
# CONFIG_SND_SOC_SSM2305 is not set
# CONFIG_SND_SOC_SSM2518 is not set
# CONFIG_SND_SOC_SSM2602_SPI is not set
# CONFIG_SND_SOC_SSM2602_I2C is not set
# CONFIG_SND_SOC_SSM3515 is not set
# CONFIG_SND_SOC_SSM4567 is not set
# CONFIG_SND_SOC_STA32X is not set
# CONFIG_SND_SOC_STA350 is not set
# CONFIG_SND_SOC_STI_SAS is not set
# CONFIG_SND_SOC_TAS2552 is not set
# CONFIG_SND_SOC_TAS2562 is not set
# CONFIG_SND_SOC_TAS2764 is not set
# CONFIG_SND_SOC_TAS2770 is not set
# CONFIG_SND_SOC_TAS2780 is not set
# CONFIG_SND_SOC_TAS2781_I2C is not set
# CONFIG_SND_SOC_TAS5086 is not set
# CONFIG_SND_SOC_TAS571X is not set
# CONFIG_SND_SOC_TAS5720 is not set
# CONFIG_SND_SOC_TAS5805M is not set
# CONFIG_SND_SOC_TAS6424 is not set
# CONFIG_SND_SOC_TDA7419 is not set
# CONFIG_SND_SOC_TFA9879 is not set
# CONFIG_SND_SOC_TFA989X is not set
# CONFIG_SND_SOC_TLV320ADC3XXX is not set
# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC31XX is not set
# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set
# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set
# CONFIG_SND_SOC_TLV320ADCX140 is not set
CONFIG_SND_SOC_TS3A227E=m
# CONFIG_SND_SOC_TSCS42XX is not set
# CONFIG_SND_SOC_TSCS454 is not set
# CONFIG_SND_SOC_UDA1334 is not set
CONFIG_SND_SOC_WCD_CLASSH=m
# CONFIG_SND_SOC_WCD9335 is not set
CONFIG_SND_SOC_WCD_MBHC=m
CONFIG_SND_SOC_WCD934X=m
# CONFIG_SND_SOC_WCD938X_SDW is not set
# CONFIG_SND_SOC_WM8510 is not set
# CONFIG_SND_SOC_WM8523 is not set
# CONFIG_SND_SOC_WM8524 is not set
# CONFIG_SND_SOC_WM8580 is not set
# CONFIG_SND_SOC_WM8711 is not set
# CONFIG_SND_SOC_WM8728 is not set
# CONFIG_SND_SOC_WM8731_I2C is not set
# CONFIG_SND_SOC_WM8731_SPI is not set
# CONFIG_SND_SOC_WM8737 is not set
# CONFIG_SND_SOC_WM8741 is not set
# CONFIG_SND_SOC_WM8750 is not set
# CONFIG_SND_SOC_WM8753 is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8776 is not set
# CONFIG_SND_SOC_WM8782 is not set
# CONFIG_SND_SOC_WM8804_I2C is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_WM8903 is not set
CONFIG_SND_SOC_WM8904=m
# CONFIG_SND_SOC_WM8940 is not set
# CONFIG_SND_SOC_WM8960 is not set
# CONFIG_SND_SOC_WM8961 is not set
# CONFIG_SND_SOC_WM8962 is not set
# CONFIG_SND_SOC_WM8974 is not set
# CONFIG_SND_SOC_WM8978 is not set
# CONFIG_SND_SOC_WM8985 is not set
CONFIG_SND_SOC_WSA881X=m
# CONFIG_SND_SOC_WSA883X is not set
# CONFIG_SND_SOC_WSA884X is not set
# CONFIG_SND_SOC_ZL38060 is not set
# CONFIG_SND_SOC_MAX9759 is not set
# CONFIG_SND_SOC_MT6351 is not set
# CONFIG_SND_SOC_MT6358 is not set
# CONFIG_SND_SOC_MT6660 is not set
# CONFIG_SND_SOC_NAU8315 is not set
# CONFIG_SND_SOC_NAU8540 is not set
# CONFIG_SND_SOC_NAU8810 is not set
# CONFIG_SND_SOC_NAU8821 is not set
# CONFIG_SND_SOC_NAU8822 is not set
# CONFIG_SND_SOC_NAU8824 is not set
# CONFIG_SND_SOC_TPA6130A2 is not set
# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set
# CONFIG_SND_SOC_LPASS_VA_MACRO is not set
# CONFIG_SND_SOC_LPASS_RX_MACRO is not set
# CONFIG_SND_SOC_LPASS_TX_MACRO is not set
CONFIG_SND_SOC_ACX00=y
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set
# CONFIG_SND_TEST_COMPONENT is not set
# CONFIG_SND_VIRTIO is not set
CONFIG_AC97_BUS=m
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_BATTERY_STRENGTH is not set
# CONFIG_HIDRAW is not set
# CONFIG_UHID is not set
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
# CONFIG_HID_A4TECH is not set
# CONFIG_HID_ACCUTOUCH is not set
# CONFIG_HID_ACRUX is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_APPLEIR is not set
# CONFIG_HID_ASUS is not set
# CONFIG_HID_AUREAL is not set
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_BETOP_FF is not set
# CONFIG_HID_BIGBEN_FF is not set
# CONFIG_HID_CHERRY is not set
# CONFIG_HID_CHICONY is not set
# CONFIG_HID_CORSAIR is not set
# CONFIG_HID_COUGAR is not set
# CONFIG_HID_MACALLY is not set
# CONFIG_HID_PRODIKEYS is not set
# CONFIG_HID_CMEDIA is not set
# CONFIG_HID_CREATIVE_SB0540 is not set
# CONFIG_HID_CYPRESS is not set
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EMS_FF is not set
# CONFIG_HID_ELAN is not set
# CONFIG_HID_ELECOM is not set
# CONFIG_HID_ELO is not set
# CONFIG_HID_EVISION is not set
# CONFIG_HID_EZKEY is not set
# CONFIG_HID_GEMBIRD is not set
# CONFIG_HID_GFRM is not set
# CONFIG_HID_GLORIOUS is not set
# CONFIG_HID_HOLTEK is not set
# CONFIG_HID_GOOGLE_HAMMER is not set
# CONFIG_HID_GOOGLE_STADIA_FF is not set
# CONFIG_HID_VIVALDI is not set
# CONFIG_HID_GT683R is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
# CONFIG_HID_UCLOGIC is not set
# CONFIG_HID_WALTOP is not set
# CONFIG_HID_VIEWSONIC is not set
# CONFIG_HID_VRC2 is not set
# CONFIG_HID_XIAOMI is not set
# CONFIG_HID_GYRATION is not set
# CONFIG_HID_ICADE is not set
# CONFIG_HID_ITE is not set
# CONFIG_HID_JABRA is not set
# CONFIG_HID_TWINHAN is not set
# CONFIG_HID_KENSINGTON is not set
# CONFIG_HID_LCPOWER is not set
# CONFIG_HID_LED is not set
# CONFIG_HID_LENOVO is not set
# CONFIG_HID_LETSKETCH is not set
# CONFIG_HID_LOGITECH is not set
# CONFIG_HID_MAGICMOUSE is not set
# CONFIG_HID_MALTRON is not set
# CONFIG_HID_MAYFLASH is not set
# CONFIG_HID_MEGAWORLD_FF is not set
# CONFIG_HID_REDRAGON is not set
# CONFIG_HID_MICROSOFT is not set
# CONFIG_HID_MONTEREY is not set
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_NINTENDO is not set
# CONFIG_HID_NTI is not set
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_ORTEK is not set
# CONFIG_HID_PANTHERLORD is not set
# CONFIG_HID_PENMOUNT is not set
# CONFIG_HID_PETALYNX is not set
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_PLANTRONICS is not set
# CONFIG_HID_PXRC is not set
# CONFIG_HID_RAZER is not set
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_RETRODE is not set
# CONFIG_HID_ROCCAT is not set
# CONFIG_HID_SAITEK is not set
# CONFIG_HID_SAMSUNG is not set
# CONFIG_HID_SEMITEK is not set
# CONFIG_HID_SIGMAMICRO is not set
# CONFIG_HID_SONY is not set
# CONFIG_HID_SPEEDLINK is not set
# CONFIG_HID_STEAM is not set
# CONFIG_HID_STEELSERIES is not set
# CONFIG_HID_SUNPLUS is not set
# CONFIG_HID_RMI is not set
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
# CONFIG_HID_TIVO is not set
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_TOPRE is not set
# CONFIG_HID_THINGM is not set
# CONFIG_HID_THRUSTMASTER is not set
# CONFIG_HID_UDRAW_PS3 is not set
# CONFIG_HID_U2FZERO is not set
# CONFIG_HID_WACOM is not set
# CONFIG_HID_WIIMOTE is not set
# CONFIG_HID_XINMO is not set
# CONFIG_HID_ZEROPLUS is not set
# CONFIG_HID_ZYDACRON is not set
# CONFIG_HID_SENSOR_HUB is not set
# CONFIG_HID_ALPS is not set
# CONFIG_HID_MCP2200 is not set
# CONFIG_HID_MCP2221 is not set
# end of Special HID drivers

#
# HID-BPF support
#
# end of HID-BPF support

#
# USB HID support
#
CONFIG_USB_HID=m
# CONFIG_HID_PID is not set
# CONFIG_USB_HIDDEV is not set

#
# USB HID Boot Protocol drivers
#
# CONFIG_USB_KBD is not set
# CONFIG_USB_MOUSE is not set
# end of USB HID Boot Protocol drivers
# end of USB HID support

CONFIG_I2C_HID=y
# CONFIG_I2C_HID_ACPI is not set
# CONFIG_I2C_HID_OF is not set
# CONFIG_I2C_HID_OF_ELAN is not set
# CONFIG_I2C_HID_OF_GOODIX is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_LED_TRIG=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_CONN_GPIO=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
# CONFIG_USB_OTG_FSM is not set
# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=y

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=y
# CONFIG_USB_XHCI_PCI_RENESAS is not set
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
# CONFIG_USB_EHCI_FSL is not set
CONFIG_USB_EHCI_HCD_PLATFORM=y
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_MAX3421_HCD is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PCI=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_UHCI_HCD=y
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_HCD_BCMA is not set
# CONFIG_USB_HCD_SSB is not set
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=m
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
CONFIG_USB_STORAGE_REALTEK=y
CONFIG_REALTEK_AUTOPM=y
CONFIG_USB_STORAGE_DATAFAB=y
CONFIG_USB_STORAGE_FREECOM=y
CONFIG_USB_STORAGE_ISD200=y
CONFIG_USB_STORAGE_USBAT=y
CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_STORAGE_JUMPSHOT=y
CONFIG_USB_STORAGE_ALAUDA=y
CONFIG_USB_STORAGE_ONETOUCH=y
CONFIG_USB_STORAGE_KARMA=y
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
CONFIG_USB_STORAGE_ENE_UB6250=y
CONFIG_USB_UAS=y

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
CONFIG_USB_MICROTEK=m
CONFIG_USBIP_CORE=m
CONFIG_USBIP_VHCI_HCD=m
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=m
CONFIG_USBIP_VUDC=m
# CONFIG_USBIP_DEBUG is not set

#
# USB dual-mode controller drivers
#
# CONFIG_USB_CDNS_SUPPORT is not set
CONFIG_USB_MUSB_HDRC=y
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y

#
# Platform Glue Layer
#
CONFIG_USB_MUSB_SUNXI=y

#
# MUSB DMA mode
#
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_ULPI=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y

#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=y
CONFIG_USB_DWC3_HAPS=y
CONFIG_USB_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
CONFIG_USB_DWC2_PCI=y
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
# CONFIG_USB_CHIPIDEA is not set
CONFIG_USB_ISP1760=y
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_ISP1761_UDC=y
# CONFIG_USB_ISP1760_HOST_ROLE is not set
# CONFIG_USB_ISP1760_GADGET_ROLE is not set
CONFIG_USB_ISP1760_DUAL_ROLE=y

#
# USB port drivers
#
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=m
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=m
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=m
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=m
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_F81232=m
CONFIG_USB_SERIAL_F8153X=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=m
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_METRO=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MXUPORT=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=m
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=m
CONFIG_USB_SERIAL_QUALCOMM=m
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
CONFIG_USB_SERIAL_SAFE_PADDED=y
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
CONFIG_USB_SERIAL_SYMBOL=m
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_WWAN=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=m
CONFIG_USB_SERIAL_XSENS_MT=m
CONFIG_USB_SERIAL_WISHBONE=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_SERIAL_QT2=m
CONFIG_USB_SERIAL_UPD78F0730=m
# CONFIG_USB_SERIAL_XR is not set
CONFIG_USB_SERIAL_DEBUG=m

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
CONFIG_USB_IDMOUSE=m
CONFIG_USB_APPLEDISPLAY=m
# CONFIG_APPLE_MFI_FASTCHARGE is not set
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
# CONFIG_USB_TEST is not set
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=m
# CONFIG_USB_HUB_USB251XB is not set
CONFIG_USB_HSIC_USB3503=y
CONFIG_USB_HSIC_USB4604=y
# CONFIG_USB_LINK_LAYER_TEST is not set
CONFIG_USB_CHAOSKEY=m
# CONFIG_USB_ONBOARD_HUB is not set
CONFIG_USB_ATM=m
# CONFIG_USB_SPEEDTOUCH is not set
CONFIG_USB_CXACRU=m
CONFIG_USB_UEAGLEATM=m
CONFIG_USB_XUSBATM=m

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_ISP1301=y
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set

#
# USB Peripheral Controller
#
# CONFIG_USB_GR_UDC is not set
# CONFIG_USB_R8A66597 is not set
# CONFIG_USB_PXA27X is not set
# CONFIG_USB_MV_UDC is not set
# CONFIG_USB_MV_U3D is not set
# CONFIG_USB_SNP_UDC_PLAT is not set
# CONFIG_USB_M66592 is not set
# CONFIG_USB_BDC_UDC is not set
# CONFIG_USB_AMD5536UDC is not set
# CONFIG_USB_NET2272 is not set
# CONFIG_USB_NET2280 is not set
# CONFIG_USB_GOKU is not set
# CONFIG_USB_EG20T is not set
# CONFIG_USB_GADGET_XILINX is not set
# CONFIG_USB_MAX3420_UDC is not set
# CONFIG_USB_CDNS2_UDC is not set
# CONFIG_USB_DUMMY_HCD is not set
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=m
CONFIG_USB_F_ACM=m
CONFIG_USB_U_SERIAL=m
CONFIG_USB_U_ETHER=m
CONFIG_USB_U_AUDIO=m
CONFIG_USB_F_SERIAL=m
CONFIG_USB_F_OBEX=m
CONFIG_USB_F_NCM=m
CONFIG_USB_F_ECM=m
CONFIG_USB_F_EEM=m
CONFIG_USB_F_SUBSET=m
CONFIG_USB_F_RNDIS=m
CONFIG_USB_F_MASS_STORAGE=m
CONFIG_USB_F_FS=m
CONFIG_USB_F_UAC1=m
CONFIG_USB_F_UAC1_LEGACY=m
CONFIG_USB_F_UAC2=m
CONFIG_USB_F_UVC=m
CONFIG_USB_F_MIDI=m
CONFIG_USB_F_HID=m
CONFIG_USB_F_PRINTER=m
CONFIG_USB_F_TCM=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
# CONFIG_USB_CONFIGFS_F_LB_SS is not set
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
# CONFIG_USB_CONFIGFS_F_MIDI2 is not set
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y
CONFIG_USB_CONFIGFS_F_TCM=y

#
# USB Gadget precomposed configurations
#
# CONFIG_USB_ZERO is not set
CONFIG_USB_AUDIO=m
CONFIG_GADGET_UAC1=y
# CONFIG_GADGET_UAC1_LEGACY is not set
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
CONFIG_USB_FUNCTIONFS_ETH=y
CONFIG_USB_FUNCTIONFS_RNDIS=y
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_GADGET_TARGET=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_G_HID=m
# CONFIG_USB_G_DBGP is not set
CONFIG_USB_G_WEBCAM=m
# CONFIG_USB_RAW_GADGET is not set
# end of USB Gadget precomposed configurations

CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
# CONFIG_TYPEC_RT1711H is not set
# CONFIG_TYPEC_TCPCI_MAXIM is not set
CONFIG_TYPEC_FUSB302=y
# CONFIG_TYPEC_UCSI is not set
CONFIG_TYPEC_TPS6598X=m
# CONFIG_TYPEC_ANX7411 is not set
# CONFIG_TYPEC_RT1719 is not set
CONFIG_TYPEC_HD3SS3220=m
# CONFIG_TYPEC_STUSB160X is not set
# CONFIG_TYPEC_WUSB3801 is not set

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
# CONFIG_TYPEC_MUX_FSA4480 is not set
# CONFIG_TYPEC_MUX_GPIO_SBU is not set
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
# CONFIG_TYPEC_MUX_NB7VPQ904M is not set
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
# CONFIG_TYPEC_DP_ALTMODE is not set
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
CONFIG_PWRSEQ_SD8787=m
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_SDIO_UART=m
# CONFIG_MMC_TEST is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_ARMMMCI=y
# CONFIG_MMC_STM32_SDMMC is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_PCI=y
CONFIG_MMC_RICOH_MMC=y
CONFIG_MMC_SDHCI_ACPI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
CONFIG_MMC_SDHCI_OF_AT91=y
# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set
CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MMC_SDHCI_F_SDH30=y
# CONFIG_MMC_SDHCI_MILBEAUT is not set
CONFIG_MMC_TIFM_SD=y
CONFIG_MMC_SPI=y
CONFIG_MMC_CB710=y
CONFIG_MMC_VIA_SDMMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
# CONFIG_MMC_DW_BLUEFIELD is not set
CONFIG_MMC_DW_EXYNOS=y
# CONFIG_MMC_DW_HI3798CV200 is not set
CONFIG_MMC_DW_K3=y
CONFIG_MMC_DW_PCI=y
CONFIG_MMC_VUB300=m
CONFIG_MMC_USHC=m
CONFIG_MMC_USDHI6ROL0=y
CONFIG_MMC_SUNXI=y
CONFIG_MMC_CQHCI=y
# CONFIG_MMC_HSQ is not set
CONFIG_MMC_TOSHIBA_PCI=y
CONFIG_MMC_MTK=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_SCSI_UFSHCD=y
# CONFIG_SCSI_UFS_BSG is not set
# CONFIG_SCSI_UFS_HWMON is not set
CONFIG_SCSI_UFSHCD_PCI=m
# CONFIG_SCSI_UFS_DWC_TC_PCI is not set
CONFIG_SCSI_UFSHCD_PLATFORM=y
# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set
# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set
CONFIG_MEMSTICK=m
# CONFIG_MEMSTICK_DEBUG is not set

#
# MemoryStick drivers
#
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
CONFIG_MSPRO_BLOCK=m
# CONFIG_MS_BLOCK is not set

#
# MemoryStick Host Controller Drivers
#
CONFIG_MEMSTICK_TIFM_MS=m
CONFIG_MEMSTICK_JMICRON_38X=m
CONFIG_MEMSTICK_R592=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=m
# CONFIG_LEDS_CLASS_MULTICOLOR is not set
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set

#
# LED drivers
#
# CONFIG_LEDS_AN30259A is not set
# CONFIG_LEDS_AW200XX is not set
# CONFIG_LEDS_AW2013 is not set
# CONFIG_LEDS_BCM6328 is not set
# CONFIG_LEDS_BCM6358 is not set
# CONFIG_LEDS_CR0014114 is not set
# CONFIG_LEDS_EL15203000 is not set
CONFIG_LEDS_LM3530=m
# CONFIG_LEDS_LM3532 is not set
# CONFIG_LEDS_LM3642 is not set
CONFIG_LEDS_LM3692X=m
# CONFIG_LEDS_PCA9532 is not set
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=m
# CONFIG_LEDS_LP3952 is not set
# CONFIG_LEDS_LP50XX is not set
# CONFIG_LEDS_LP55XX_COMMON is not set
# CONFIG_LEDS_LP8860 is not set
CONFIG_LEDS_PCA955X=m
# CONFIG_LEDS_PCA955X_GPIO is not set
CONFIG_LEDS_PCA963X=m
# CONFIG_LEDS_PCA995X is not set
# CONFIG_LEDS_DAC124S085 is not set
CONFIG_LEDS_PWM=m
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2606MVV is not set
# CONFIG_LEDS_BD2802 is not set
CONFIG_LEDS_LT3593=m
# CONFIG_LEDS_TCA6507 is not set
# CONFIG_LEDS_TLC591XX is not set
# CONFIG_LEDS_LM355x is not set
# CONFIG_LEDS_IS31FL319X is not set
# CONFIG_LEDS_IS31FL32XX is not set

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=m
CONFIG_LEDS_SYSCON=y
# CONFIG_LEDS_MLXREG is not set
CONFIG_LEDS_USER=m
# CONFIG_LEDS_SPI_BYTE is not set
# CONFIG_LEDS_LM3697 is not set

#
# Flash and Torch LED drivers
#
# CONFIG_LEDS_AAT1290 is not set
# CONFIG_LEDS_AS3645A is not set
# CONFIG_LEDS_KTD2692 is not set
# CONFIG_LEDS_LM3601X is not set
# CONFIG_LEDS_RT4505 is not set
# CONFIG_LEDS_RT8515 is not set
# CONFIG_LEDS_SGM3140 is not set

#
# RGB LED drivers
#

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_ACTIVITY=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=y
CONFIG_LEDS_TRIGGER_PATTERN=m
CONFIG_LEDS_TRIGGER_AUDIO=m
# CONFIG_LEDS_TRIGGER_TTY is not set

#
# Simple LED drivers
#
CONFIG_ACCESSIBILITY=y
CONFIG_A11Y_BRAILLE_CONSOLE=y

#
# Speakup console speech
#
# CONFIG_SPEAKUP is not set
# end of Speakup console speech

# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
# CONFIG_EDAC_DEBUG is not set
# CONFIG_EDAC_THUNDERX is not set
CONFIG_EDAC_XGENE=m
# CONFIG_EDAC_DMC520 is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_SYSTOHC is not set
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_ABB5ZES3 is not set
# CONFIG_RTC_DRV_ABEOZ9 is not set
CONFIG_RTC_DRV_ABX80X=m
CONFIG_RTC_DRV_DS1307=m
# CONFIG_RTC_DRV_DS1307_CENTURY is not set
CONFIG_RTC_DRV_DS1374=m
CONFIG_RTC_DRV_DS1374_WDT=y
CONFIG_RTC_DRV_DS1672=m
CONFIG_RTC_DRV_HYM8563=m
CONFIG_RTC_DRV_MAX6900=m
# CONFIG_RTC_DRV_MAX77686 is not set
# CONFIG_RTC_DRV_NCT3018Y is not set
CONFIG_RTC_DRV_RS5C372=m
CONFIG_RTC_DRV_ISL1208=m
CONFIG_RTC_DRV_ISL12022=m
# CONFIG_RTC_DRV_ISL12026 is not set
CONFIG_RTC_DRV_X1205=m
CONFIG_RTC_DRV_PCF8523=m
CONFIG_RTC_DRV_PCF85063=m
CONFIG_RTC_DRV_PCF85363=m
CONFIG_RTC_DRV_PCF8563=m
CONFIG_RTC_DRV_PCF8583=m
CONFIG_RTC_DRV_M41T80=m
CONFIG_RTC_DRV_M41T80_WDT=y
CONFIG_RTC_DRV_BQ32K=m
# CONFIG_RTC_DRV_S35390A is not set
CONFIG_RTC_DRV_FM3130=m
# CONFIG_RTC_DRV_RX8010 is not set
CONFIG_RTC_DRV_RX8581=m
CONFIG_RTC_DRV_RX8025=m
CONFIG_RTC_DRV_EM3027=m
# CONFIG_RTC_DRV_RV3028 is not set
# CONFIG_RTC_DRV_RV3032 is not set
CONFIG_RTC_DRV_RV8803=m
# CONFIG_RTC_DRV_S5M is not set
# CONFIG_RTC_DRV_SD3078 is not set

#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_MCP795 is not set
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
CONFIG_RTC_DRV_DS3232=m
CONFIG_RTC_DRV_DS3232_HWMON=y
CONFIG_RTC_DRV_PCF2127=m
CONFIG_RTC_DRV_RV3029C2=m
CONFIG_RTC_DRV_RV3029_HWMON=y
# CONFIG_RTC_DRV_RX6110 is not set

#
# Platform RTC drivers
#
CONFIG_RTC_DRV_DS1286=m
CONFIG_RTC_DRV_DS1511=m
CONFIG_RTC_DRV_DS1553=m
CONFIG_RTC_DRV_DS1685_FAMILY=m
CONFIG_RTC_DRV_DS1685=y
# CONFIG_RTC_DRV_DS1689 is not set
# CONFIG_RTC_DRV_DS17285 is not set
# CONFIG_RTC_DRV_DS17485 is not set
# CONFIG_RTC_DRV_DS17885 is not set
CONFIG_RTC_DRV_DS1742=m
CONFIG_RTC_DRV_DS2404=m
CONFIG_RTC_DRV_EFI=y
CONFIG_RTC_DRV_STK17TA8=m
# CONFIG_RTC_DRV_M48T86 is not set
CONFIG_RTC_DRV_M48T35=m
CONFIG_RTC_DRV_M48T59=m
CONFIG_RTC_DRV_MSM6242=m
CONFIG_RTC_DRV_RP5C01=m
# CONFIG_RTC_DRV_ZYNQMP is not set
CONFIG_RTC_DRV_CROS_EC=y

#
# on-CPU RTC drivers
#
# CONFIG_RTC_DRV_PL030 is not set
CONFIG_RTC_DRV_PL031=y
CONFIG_RTC_DRV_SUN6I=y
# CONFIG_RTC_DRV_CADENCE is not set
# CONFIG_RTC_DRV_FTRTC010 is not set
# CONFIG_RTC_DRV_R7301 is not set

#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_GOLDFISH is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
# CONFIG_AMBA_PL08X is not set
# CONFIG_BCM_SBA_RAID is not set
CONFIG_DMA_SUN6I=y
# CONFIG_DW_AXI_DMAC is not set
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_INTEL_IDMA64 is not set
CONFIG_MV_XOR_V2=y
CONFIG_PL330_DMA=y
# CONFIG_PLX_DMA is not set
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_XDMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
# CONFIG_XILINX_ZYNQMP_DPDMA is not set
CONFIG_QCOM_HIDMA_MGMT=y
CONFIG_QCOM_HIDMA=y
CONFIG_DW_DMAC_CORE=m
CONFIG_DW_DMAC=m
CONFIG_DW_DMAC_PCI=m
# CONFIG_DW_EDMA is not set
# CONFIG_SF_PDMA is not set

#
# DMA Clients
#
CONFIG_ASYNC_TX_DMA=y
# CONFIG_DMATEST is not set
CONFIG_DMA_ENGINE_RAID=y

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
# CONFIG_SW_SYNC is not set
# CONFIG_UDMABUF is not set
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_DEBUG is not set
# CONFIG_DMABUF_SELFTESTS is not set
# CONFIG_DMABUF_HEAPS is not set
# CONFIG_DMABUF_SYSFS_STATS is not set
# end of DMABUF options

CONFIG_UIO=m
CONFIG_UIO_CIF=m
# CONFIG_UIO_PDRV_GENIRQ is not set
# CONFIG_UIO_DMEM_GENIRQ is not set
CONFIG_UIO_AEC=m
CONFIG_UIO_SERCOS3=m
CONFIG_UIO_PCI_GENERIC=m
# CONFIG_UIO_NETX is not set
# CONFIG_UIO_PRUSS is not set
# CONFIG_UIO_MF624 is not set
CONFIG_VFIO=m
CONFIG_VFIO_GROUP=y
CONFIG_VFIO_CONTAINER=y
CONFIG_VFIO_IOMMU_TYPE1=m
# CONFIG_VFIO_NOIOMMU is not set
CONFIG_VFIO_VIRQFD=y

#
# VFIO support for PCI devices
#
CONFIG_VFIO_PCI_CORE=m
CONFIG_VFIO_PCI_MMAP=y
CONFIG_VFIO_PCI_INTX=y
CONFIG_VFIO_PCI=m
# CONFIG_MLX5_VFIO_PCI is not set
# end of VFIO support for PCI devices

#
# VFIO support for platform devices
#
CONFIG_VFIO_PLATFORM_BASE=m
CONFIG_VFIO_PLATFORM=m
CONFIG_VFIO_AMBA=m

#
# VFIO platform reset drivers
#
CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET=m
CONFIG_VFIO_PLATFORM_AMDXGBE_RESET=m
# end of VFIO platform reset drivers
# end of VFIO support for platform devices

# CONFIG_VIRT_DRIVERS is not set
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_PCI_LIB=y
CONFIG_VIRTIO_PCI_LIB_LEGACY=y
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_PCI_LEGACY=y
# CONFIG_VIRTIO_PMEM is not set
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
# CONFIG_VDPA is not set
CONFIG_VHOST_IOTLB=m
CONFIG_VHOST_TASK=y
CONFIG_VHOST=m
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_SCSI=m
CONFIG_VHOST_VSOCK=m
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set

#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
# CONFIG_COMEDI is not set
CONFIG_STAGING=y
CONFIG_PRISM2_USB=m
CONFIG_RTL8192U=m
CONFIG_RTLLIB=m
CONFIG_RTLLIB_CRYPTO_CCMP=m
CONFIG_RTLLIB_CRYPTO_TKIP=m
CONFIG_RTLLIB_CRYPTO_WEP=m
CONFIG_RTL8192E=m
# CONFIG_RTL8723BS is not set
# CONFIG_RTS5208 is not set
# CONFIG_VT6655 is not set
# CONFIG_VT6656 is not set

#
# IIO staging drivers
#

#
# Accelerometers
#
CONFIG_ADIS16203=m
CONFIG_ADIS16240=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD7816=m
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
CONFIG_ADT7316=m
CONFIG_ADT7316_SPI=m
CONFIG_ADT7316_I2C=m
# end of Analog digital bi-direction converters

#
# Direct Digital Synthesis
#
CONFIG_AD9832=m
CONFIG_AD9834=m
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
CONFIG_AD5933=m
# end of Network Analyzer, Impedance Converters

#
# Resolver to digital converters
#
CONFIG_AD2S1210=m
# end of Resolver to digital converters
# end of IIO staging drivers

# CONFIG_FB_SM750 is not set
CONFIG_STAGING_MEDIA=y
CONFIG_DVB_AV7110_IR=y
CONFIG_DVB_AV7110=m
CONFIG_DVB_AV7110_OSD=y
CONFIG_DVB_BUDGET_PATCH=m
CONFIG_DVB_SP8870=m
# CONFIG_VIDEO_MAX96712 is not set
CONFIG_VIDEO_SUNXI=y
CONFIG_VIDEO_SUNXI_CEDRUS=m
# CONFIG_VIDEO_SUN6I_ISP is not set
# CONFIG_STAGING_MEDIA_DEPRECATED is not set
# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
CONFIG_FB_TFT=m
CONFIG_FB_TFT_AGM1264K_FL=m
CONFIG_FB_TFT_BD663474=m
CONFIG_FB_TFT_HX8340BN=m
CONFIG_FB_TFT_HX8347D=m
CONFIG_FB_TFT_HX8353D=m
CONFIG_FB_TFT_HX8357D=m
CONFIG_FB_TFT_ILI9163=m
CONFIG_FB_TFT_ILI9320=m
CONFIG_FB_TFT_ILI9325=m
CONFIG_FB_TFT_ILI9340=m
CONFIG_FB_TFT_ILI9341=m
CONFIG_FB_TFT_ILI9481=m
CONFIG_FB_TFT_ILI9486=m
CONFIG_FB_TFT_PCD8544=m
CONFIG_FB_TFT_RA8875=m
CONFIG_FB_TFT_S6D02A1=m
CONFIG_FB_TFT_S6D1121=m
CONFIG_FB_TFT_SEPS525=m
CONFIG_FB_TFT_SH1106=m
CONFIG_FB_TFT_SSD1289=m
CONFIG_FB_TFT_SSD1305=m
CONFIG_FB_TFT_SSD1306=m
CONFIG_FB_TFT_SSD1331=m
CONFIG_FB_TFT_SSD1351=m
CONFIG_FB_TFT_ST7735R=m
CONFIG_FB_TFT_ST7789V=m
CONFIG_FB_TFT_TINYLCD=m
CONFIG_FB_TFT_TLS8204=m
CONFIG_FB_TFT_UC1611=m
CONFIG_FB_TFT_UC1701=m
CONFIG_FB_TFT_UPD161704=m
# CONFIG_KS7010 is not set
# CONFIG_PI433 is not set
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_QLGE is not set
# CONFIG_VME_BUS is not set
# CONFIG_GOLDFISH is not set
CONFIG_CHROME_PLATFORMS=y
# CONFIG_CHROMEOS_ACPI is not set
CONFIG_CHROMEOS_TBMC=m
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_RPMSG=m
CONFIG_CROS_EC_SPI=y
# CONFIG_CROS_EC_UART is not set
CONFIG_CROS_EC_PROTO=y
CONFIG_CROS_KBD_LED_BACKLIGHT=y
CONFIG_CROS_EC_CHARDEV=y
CONFIG_CROS_EC_LIGHTBAR=m
CONFIG_CROS_EC_VBC=m
CONFIG_CROS_EC_DEBUGFS=m
CONFIG_CROS_EC_SENSORHUB=y
CONFIG_CROS_EC_SYSFS=m
CONFIG_CROS_EC_TYPEC=y
# CONFIG_CROS_HPS_I2C is not set
CONFIG_CROS_USBPD_LOGGER=m
CONFIG_CROS_USBPD_NOTIFY=y
# CONFIG_CHROMEOS_PRIVACY_SCREEN is not set
# CONFIG_CROS_TYPEC_SWITCH is not set
# CONFIG_MELLANOX_PLATFORM is not set
# CONFIG_SURFACE_PLATFORMS is not set
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Clock driver for ARM Reference designs
#
# CONFIG_CLK_ICST is not set
CONFIG_CLK_SP810=y
CONFIG_CLK_VEXPRESS_OSC=y
# end of Clock driver for ARM Reference designs

# CONFIG_LMK04832 is not set
# CONFIG_COMMON_CLK_MAX77686 is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
# CONFIG_COMMON_CLK_S2MPS11 is not set
# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
CONFIG_COMMON_CLK_XGENE=y
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_RS9_PCIE is not set
# CONFIG_COMMON_CLK_SI521XX is not set
# CONFIG_COMMON_CLK_VC3 is not set
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_VC7 is not set
CONFIG_COMMON_CLK_BD718XX=m
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
CONFIG_SUNXI_CCU=y
CONFIG_SUN50I_A64_CCU=y
CONFIG_SUN50I_A100_CCU=y
CONFIG_SUN50I_A100_R_CCU=y
CONFIG_SUN50I_H6_CCU=y
CONFIG_SUN50I_H616_CCU=y
CONFIG_SUN50I_H6_R_CCU=y
# CONFIG_SUN6I_RTC_CCU is not set
CONFIG_SUN8I_H3_CCU=y
CONFIG_SUN8I_DE2_CCU=y
CONFIG_SUN8I_R_CCU=y
# CONFIG_XILINX_VCU is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
CONFIG_HWSPINLOCK=y
# CONFIG_HWSPINLOCK_SUN6I is not set

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_ACPI=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_SUN4I_TIMER=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
# CONFIG_ARM_TIMER_SP804 is not set
# end of Clock Source drivers

CONFIG_MAILBOX=y
CONFIG_ARM_MHU=y
# CONFIG_ARM_MHU_V2 is not set
CONFIG_PLATFORM_MHU=y
# CONFIG_PL320_MBOX is not set
CONFIG_PCC=y
# CONFIG_ALTERA_MBOX is not set
# CONFIG_MAILBOX_TEST is not set
CONFIG_SUN6I_MSGBOX=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_DART is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
# CONFIG_IOMMUFD is not set
# CONFIG_SUN50I_IOMMU is not set
CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
CONFIG_ARM_SMMU_V3=y
# CONFIG_ARM_SMMU_V3_SVA is not set
# CONFIG_VIRTIO_IOMMU is not set

#
# Remoteproc drivers
#
CONFIG_REMOTEPROC=y
# CONFIG_REMOTEPROC_CDEV is not set
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=y
CONFIG_RPMSG_CHAR=y
# CONFIG_RPMSG_CTRL is not set
# CONFIG_RPMSG_NS is not set
CONFIG_RPMSG_QCOM_GLINK=y
CONFIG_RPMSG_QCOM_GLINK_RPM=y
# CONFIG_RPMSG_VIRTIO is not set
# end of Rpmsg drivers

CONFIG_SOUNDWIRE=m

#
# SoundWire Devices
#
# CONFIG_SOUNDWIRE_AMD is not set
# CONFIG_SOUNDWIRE_INTEL is not set
CONFIG_SOUNDWIRE_QCOM=m

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
# end of Amlogic SoC drivers

#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
# CONFIG_QUICC_ENGINE is not set
# CONFIG_FSL_RCPM is not set
# end of NXP/Freescale QorIQ SoC drivers

#
# fujitsu SoC drivers
#
# CONFIG_A64FX_DIAG is not set
# end of fujitsu SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Enable LiteX SoC Builder specific drivers
#
# CONFIG_LITEX_SOC_CONTROLLER is not set
# end of Enable LiteX SoC Builder specific drivers

# CONFIG_WPCM450_SOC is not set

#
# Qualcomm SoC drivers
#
# CONFIG_QCOM_PMIC_GLINK is not set
# end of Qualcomm SoC drivers

CONFIG_SUNXI_MBUS=y
CONFIG_SUNXI_SRAM=y
# CONFIG_SUN20I_PPU is not set
# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEVFREQ_GOV_PASSIVE=y

#
# DEVFREQ Drivers
#
CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
CONFIG_EXTCON_ADC_JACK=m
# CONFIG_EXTCON_FSA9480 is not set
CONFIG_EXTCON_GPIO=y
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_PTN5150 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
CONFIG_EXTCON_USB_GPIO=y
CONFIG_EXTCON_USBC_CROS_EC=y
# CONFIG_EXTCON_USBC_TUSB320 is not set
CONFIG_MEMORY=y
# CONFIG_ARM_PL172_MPMC is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=y
CONFIG_IIO_BUFFER_DMA=m
CONFIG_IIO_BUFFER_DMAENGINE=m
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
CONFIG_IIO_TRIGGERED_EVENT=m
CONFIG_IIO_BACKEND=m

#
# Accelerometers
#
CONFIG_ADIS16201=m
CONFIG_ADIS16209=m
# CONFIG_ADXL313_I2C is not set
# CONFIG_ADXL313_SPI is not set
CONFIG_ADXL345=m
CONFIG_ADXL345_I2C=m
CONFIG_ADXL345_SPI=m
# CONFIG_ADXL355_I2C is not set
# CONFIG_ADXL355_SPI is not set
# CONFIG_ADXL367_SPI is not set
# CONFIG_ADXL367_I2C is not set
CONFIG_ADXL372=m
CONFIG_ADXL372_SPI=m
CONFIG_ADXL372_I2C=m
CONFIG_BMA180=m
CONFIG_BMA220=m
CONFIG_BMA400=m
CONFIG_BMA400_I2C=m
CONFIG_BMA400_SPI=m
CONFIG_BMC150_ACCEL=m
CONFIG_BMC150_ACCEL_I2C=m
CONFIG_BMC150_ACCEL_SPI=m
# CONFIG_BMI088_ACCEL is not set
CONFIG_DA280=m
CONFIG_DA311=m
CONFIG_DMARD06=m
CONFIG_DMARD09=m
CONFIG_DMARD10=m
# CONFIG_FXLS8962AF_I2C is not set
# CONFIG_FXLS8962AF_SPI is not set
CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
# CONFIG_IIO_KX022A_SPI is not set
# CONFIG_IIO_KX022A_I2C is not set
CONFIG_KXSD9=m
CONFIG_KXSD9_SPI=m
CONFIG_KXSD9_I2C=m
CONFIG_KXCJK1013=m
CONFIG_MC3230=m
CONFIG_MMA7455=m
CONFIG_MMA7455_I2C=m
CONFIG_MMA7455_SPI=m
CONFIG_MMA7660=m
CONFIG_MMA8452=m
CONFIG_MMA9551_CORE=m
CONFIG_MMA9551=m
CONFIG_MMA9553=m
# CONFIG_MSA311 is not set
CONFIG_MXC4005=m
CONFIG_MXC6255=m
CONFIG_SCA3000=m
# CONFIG_SCA3300 is not set
CONFIG_STK8312=m
CONFIG_STK8BA50=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=m
# CONFIG_AD4130 is not set
CONFIG_AD7091R5=m
CONFIG_AD7124=m
CONFIG_AD7192=m
CONFIG_AD7266=m
CONFIG_AD7280=m
CONFIG_AD7291=m
CONFIG_AD7292=m
CONFIG_AD7298=m
CONFIG_AD7476=m
CONFIG_AD7606=m
CONFIG_AD7606_IFACE_PARALLEL=m
CONFIG_AD7606_IFACE_SPI=m
CONFIG_AD7766=m
CONFIG_AD7768_1=m
CONFIG_AD7780=m
CONFIG_AD7791=m
CONFIG_AD7793=m
CONFIG_AD7887=m
CONFIG_AD7923=m
CONFIG_AD7949=m
CONFIG_AD799X=m
CONFIG_AD9467=m
CONFIG_ADI_AXI_ADC=m
CONFIG_AXP20X_ADC=m
CONFIG_AXP288_ADC=m
CONFIG_CC10001_ADC=m
CONFIG_ENVELOPE_DETECTOR=m
CONFIG_HI8435=m
CONFIG_HX711=m
CONFIG_INA2XX_ADC=m
CONFIG_LTC2471=m
CONFIG_LTC2485=m
CONFIG_LTC2496=m
CONFIG_LTC2497=m
CONFIG_MAX1027=m
CONFIG_MAX11100=m
CONFIG_MAX1118=m
# CONFIG_MAX11205 is not set
# CONFIG_MAX11410 is not set
CONFIG_MAX1241=m
CONFIG_MAX1363=m
CONFIG_MAX9611=m
CONFIG_MCP320X=m
CONFIG_MCP3422=m
CONFIG_MCP3911=m
CONFIG_NAU7802=m
CONFIG_QCOM_VADC_COMMON=y
CONFIG_QCOM_SPMI_IADC=m
CONFIG_QCOM_SPMI_VADC=y
CONFIG_QCOM_SPMI_ADC5=m
# CONFIG_RICHTEK_RTQ6056 is not set
CONFIG_SD_ADC_MODULATOR=m
# CONFIG_SUN20I_GPADC is not set
CONFIG_TI_ADC081C=m
CONFIG_TI_ADC0832=m
CONFIG_TI_ADC084S021=m
CONFIG_TI_ADC12138=m
CONFIG_TI_ADC108S102=m
CONFIG_TI_ADC128S052=m
CONFIG_TI_ADC161S626=m
CONFIG_TI_ADS1015=m
# CONFIG_TI_ADS7924 is not set
# CONFIG_TI_ADS1100 is not set
CONFIG_TI_ADS7950=m
CONFIG_TI_ADS8344=m
CONFIG_TI_ADS8688=m
CONFIG_TI_ADS124S08=m
# CONFIG_TI_ADS131E08 is not set
# CONFIG_TI_LMP92064 is not set
CONFIG_TI_TLC4541=m
# CONFIG_TI_TSC2046 is not set
CONFIG_VF610_ADC=m
CONFIG_VIPERBOARD_ADC=m
# CONFIG_XILINX_XADC is not set
# end of Analog to digital converters

#
# Analog to digital and digital to analog converters
#
# CONFIG_AD74115 is not set
# CONFIG_AD74413R is not set
# end of Analog to digital and digital to analog converters

#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=m
# end of Analog Front Ends

#
# Amplifiers
#
CONFIG_AD8366=m
# CONFIG_ADA4250 is not set
CONFIG_HMC425=m
# end of Amplifiers

#
# Capacitance to digital converters
#
CONFIG_AD7150=m
CONFIG_AD7746=m
# end of Capacitance to digital converters

#
# Chemical Sensors
#
CONFIG_ATLAS_PH_SENSOR=m
CONFIG_ATLAS_EZO_SENSOR=m
CONFIG_BME680=m
CONFIG_BME680_I2C=m
CONFIG_BME680_SPI=m
CONFIG_CCS811=m
CONFIG_IAQCORE=m
CONFIG_PMS7003=m
CONFIG_SCD30_CORE=m
CONFIG_SCD30_I2C=m
CONFIG_SCD30_SERIAL=m
# CONFIG_SCD4X is not set
CONFIG_SENSIRION_SGP30=m
# CONFIG_SENSIRION_SGP40 is not set
# CONFIG_SPS30_I2C is not set
# CONFIG_SPS30_SERIAL is not set
# CONFIG_SENSEAIR_SUNRISE_CO2 is not set
CONFIG_VZ89X=m
# end of Chemical Sensors

CONFIG_IIO_CROS_EC_SENSORS_CORE=m
CONFIG_IIO_CROS_EC_SENSORS=m
CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m

#
# Hid Sensor IIO Common
#
# end of Hid Sensor IIO Common

CONFIG_IIO_INV_SENSORS_TIMESTAMP=m
CONFIG_IIO_MS_SENSORS_I2C=m

#
# IIO SCMI Sensors
#
# CONFIG_IIO_SCMI is not set
# end of IIO SCMI Sensors

#
# SSP Sensor Common
#
# CONFIG_IIO_SSP_SENSORHUB is not set
# end of SSP Sensor Common

CONFIG_IIO_ST_SENSORS_I2C=m
CONFIG_IIO_ST_SENSORS_SPI=m
CONFIG_IIO_ST_SENSORS_CORE=m

#
# Digital to analog converters
#
# CONFIG_AD3552R is not set
CONFIG_AD5064=m
CONFIG_AD5360=m
CONFIG_AD5380=m
CONFIG_AD5421=m
CONFIG_AD5446=m
CONFIG_AD5449=m
CONFIG_AD5592R_BASE=m
CONFIG_AD5592R=m
CONFIG_AD5593R=m
CONFIG_AD5504=m
CONFIG_AD5624R_SPI=m
# CONFIG_LTC2688 is not set
CONFIG_AD5686=m
CONFIG_AD5686_SPI=m
CONFIG_AD5696_I2C=m
CONFIG_AD5755=m
CONFIG_AD5758=m
CONFIG_AD5761=m
CONFIG_AD5764=m
# CONFIG_AD5766 is not set
CONFIG_AD5770R=m
CONFIG_AD5791=m
# CONFIG_AD7293 is not set
CONFIG_AD7303=m
CONFIG_AD8801=m
CONFIG_DPOT_DAC=m
CONFIG_DS4424=m
CONFIG_LTC1660=m
CONFIG_LTC2632=m
CONFIG_M62332=m
CONFIG_MAX517=m
# CONFIG_MAX5522 is not set
CONFIG_MAX5821=m
CONFIG_MCP4725=m
# CONFIG_MCP4728 is not set
CONFIG_MCP4922=m
CONFIG_TI_DAC082S085=m
CONFIG_TI_DAC5571=m
CONFIG_TI_DAC7311=m
CONFIG_TI_DAC7612=m
CONFIG_VF610_DAC=m
# end of Digital to analog converters

#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver

#
# Filters
#
# CONFIG_ADMV8818 is not set
# end of Filters

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
CONFIG_AD9523=m
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4350=m
CONFIG_ADF4371=m
# CONFIG_ADF4377 is not set
# CONFIG_ADMV1013 is not set
# CONFIG_ADMV1014 is not set
# CONFIG_ADMV4420 is not set
# CONFIG_ADRF6780 is not set
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=m
CONFIG_ADIS16130=m
CONFIG_ADIS16136=m
CONFIG_ADIS16260=m
CONFIG_ADXRS290=m
CONFIG_ADXRS450=m
CONFIG_BMG160=m
CONFIG_BMG160_I2C=m
CONFIG_BMG160_SPI=m
CONFIG_FXAS21002C=m
CONFIG_FXAS21002C_I2C=m
CONFIG_FXAS21002C_SPI=m
CONFIG_MPU3050=m
CONFIG_MPU3050_I2C=m
CONFIG_IIO_ST_GYRO_3AXIS=m
CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
CONFIG_ITG3200=m
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
CONFIG_AFE4403=m
CONFIG_AFE4404=m
CONFIG_MAX30100=m
CONFIG_MAX30102=m
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
CONFIG_AM2315=m
CONFIG_DHT11=m
CONFIG_HDC100X=m
CONFIG_HDC2010=m
CONFIG_HTS221=m
CONFIG_HTS221_I2C=m
CONFIG_HTS221_SPI=m
CONFIG_HTU21=m
CONFIG_SI7005=m
CONFIG_SI7020=m
# end of Humidity sensors

#
# Inertial measurement units
#
CONFIG_ADIS16400=m
CONFIG_ADIS16460=m
CONFIG_ADIS16475=m
CONFIG_ADIS16480=m
CONFIG_BMI160=m
CONFIG_BMI160_I2C=m
CONFIG_BMI160_SPI=m
# CONFIG_BOSCH_BNO055_SERIAL is not set
# CONFIG_BOSCH_BNO055_I2C is not set
CONFIG_FXOS8700=m
CONFIG_FXOS8700_I2C=m
CONFIG_FXOS8700_SPI=m
CONFIG_KMX61=m
CONFIG_INV_ICM42600=m
CONFIG_INV_ICM42600_I2C=m
CONFIG_INV_ICM42600_SPI=m
CONFIG_INV_MPU6050_IIO=m
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_SPI=m
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_LSM6DSX_I2C=m
CONFIG_IIO_ST_LSM6DSX_SPI=m
# CONFIG_IIO_ST_LSM9DS0 is not set
# end of Inertial measurement units

CONFIG_IIO_ADIS_LIB=m
CONFIG_IIO_ADIS_LIB_BUFFER=y

#
# Light sensors
#
CONFIG_ACPI_ALS=m
CONFIG_ADJD_S311=m
CONFIG_ADUX1020=m
CONFIG_AL3010=m
CONFIG_AL3320A=m
CONFIG_APDS9300=m
CONFIG_APDS9960=m
CONFIG_AS73211=m
CONFIG_BH1750=m
CONFIG_BH1780=m
CONFIG_CM32181=m
CONFIG_CM3232=m
CONFIG_CM3323=m
CONFIG_CM3605=m
CONFIG_CM36651=m
CONFIG_IIO_CROS_EC_LIGHT_PROX=m
CONFIG_GP2AP002=m
CONFIG_GP2AP020A00F=m
CONFIG_SENSORS_ISL29018=m
CONFIG_SENSORS_ISL29028=m
CONFIG_ISL29125=m
CONFIG_JSA1212=m
# CONFIG_ROHM_BU27008 is not set
# CONFIG_ROHM_BU27034 is not set
CONFIG_RPR0521=m
CONFIG_LTR501=m
# CONFIG_LTRF216A is not set
CONFIG_LV0104CS=m
CONFIG_MAX44000=m
CONFIG_MAX44009=m
CONFIG_NOA1305=m
CONFIG_OPT3001=m
# CONFIG_OPT4001 is not set
CONFIG_PA12203001=m
CONFIG_SI1133=m
CONFIG_SI1145=m
CONFIG_STK3310=m
CONFIG_ST_UVIS25=m
CONFIG_ST_UVIS25_I2C=m
CONFIG_ST_UVIS25_SPI=m
CONFIG_TCS3414=m
CONFIG_TCS3472=m
CONFIG_SENSORS_TSL2563=m
CONFIG_TSL2583=m
# CONFIG_TSL2591 is not set
CONFIG_TSL2772=m
CONFIG_TSL4531=m
CONFIG_US5182D=m
CONFIG_VCNL4000=m
CONFIG_VCNL4035=m
CONFIG_VEML6030=m
CONFIG_VEML6070=m
CONFIG_VL6180=m
CONFIG_ZOPT2201=m
# end of Light sensors

#
# Magnetometer sensors
#
CONFIG_AK8974=m
CONFIG_AK8975=m
CONFIG_AK09911=m
CONFIG_BMC150_MAGN=m
CONFIG_BMC150_MAGN_I2C=m
CONFIG_BMC150_MAGN_SPI=m
CONFIG_MAG3110=m
CONFIG_MMC35240=m
CONFIG_IIO_ST_MAGN_3AXIS=m
CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
CONFIG_SENSORS_HMC5843=m
CONFIG_SENSORS_HMC5843_I2C=m
CONFIG_SENSORS_HMC5843_SPI=m
CONFIG_SENSORS_RM3100=m
CONFIG_SENSORS_RM3100_I2C=m
CONFIG_SENSORS_RM3100_SPI=m
# CONFIG_TI_TMAG5273 is not set
# CONFIG_YAMAHA_YAS530 is not set
# end of Magnetometer sensors

#
# Multiplexers
#
CONFIG_IIO_MUX=y
# end of Multiplexers

#
# Inclinometer sensors
#
# end of Inclinometer sensors

#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=m
CONFIG_IIO_INTERRUPT_TRIGGER=m
CONFIG_IIO_TIGHTLOOP_TRIGGER=m
CONFIG_IIO_SYSFS_TRIGGER=m
# end of Triggers - standalone

#
# Linear and angular position sensors
#
# end of Linear and angular position sensors

#
# Digital potentiometers
#
# CONFIG_AD5110 is not set
CONFIG_AD5272=m
CONFIG_DS1803=m
CONFIG_MAX5432=m
CONFIG_MAX5481=m
CONFIG_MAX5487=m
CONFIG_MCP4018=m
CONFIG_MCP4131=m
CONFIG_MCP4531=m
CONFIG_MCP41010=m
CONFIG_TPL0102=m
# CONFIG_X9250 is not set
# end of Digital potentiometers

#
# Digital potentiostats
#
CONFIG_LMP91000=m
# end of Digital potentiostats

#
# Pressure sensors
#
CONFIG_ABP060MG=m
CONFIG_BMP280=m
CONFIG_BMP280_I2C=m
CONFIG_BMP280_SPI=m
CONFIG_IIO_CROS_EC_BARO=m
CONFIG_DLHL60D=m
CONFIG_DPS310=m
CONFIG_HP03=m
CONFIG_ICP10100=m
CONFIG_MPL115=m
CONFIG_MPL115_I2C=m
CONFIG_MPL115_SPI=m
CONFIG_MPL3115=m
# CONFIG_MPRLS0025PA is not set
CONFIG_MS5611=m
CONFIG_MS5611_I2C=m
CONFIG_MS5611_SPI=m
CONFIG_MS5637=m
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_PRESS_I2C=m
CONFIG_IIO_ST_PRESS_SPI=m
CONFIG_T5403=m
CONFIG_HP206C=m
CONFIG_ZPA2326=m
CONFIG_ZPA2326_I2C=m
CONFIG_ZPA2326_SPI=m
# end of Pressure sensors

#
# Lightning sensors
#
CONFIG_AS3935=m
# end of Lightning sensors

#
# Proximity and distance sensors
#
# CONFIG_CROS_EC_MKBP_PROXIMITY is not set
# CONFIG_IRSD200 is not set
CONFIG_ISL29501=m
CONFIG_LIDAR_LITE_V2=m
CONFIG_MB1232=m
CONFIG_PING=m
CONFIG_RFD77402=m
CONFIG_SRF04=m
CONFIG_SX_COMMON=m
CONFIG_SX9310=m
# CONFIG_SX9324 is not set
# CONFIG_SX9360 is not set
CONFIG_SX9500=m
CONFIG_SRF08=m
CONFIG_VCNL3020=m
CONFIG_VL53L0X_I2C=m
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
CONFIG_AD2S90=m
CONFIG_AD2S1200=m
# end of Resolver to digital converters

#
# Temperature sensors
#
CONFIG_LTC2983=m
CONFIG_MAXIM_THERMOCOUPLE=m
CONFIG_MLX90614=m
CONFIG_MLX90632=m
CONFIG_TMP006=m
CONFIG_TMP007=m
# CONFIG_TMP117 is not set
CONFIG_TSYS01=m
CONFIG_TSYS02D=m
# CONFIG_MAX30208 is not set
CONFIG_MAX31856=m
# CONFIG_MAX31865 is not set
# end of Temperature sensors

# CONFIG_NTB is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_ATMEL_TCB is not set
# CONFIG_PWM_CLK is not set
CONFIG_PWM_CROS_EC=m
# CONFIG_PWM_DWC is not set
# CONFIG_PWM_FSL_FTM is not set
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_SUN4I=y
# CONFIG_PWM_XILINX is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_AL_FIC is not set
CONFIG_SUN6I_R_INTC=y
CONFIG_SUNXI_NMI_INTC=y
# CONFIG_XILINX_INTC is not set
CONFIG_PARTITION_PERCPU=y
# end of IRQ chip support

# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_SCMI=y
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SUNXI=y
# CONFIG_RESET_TI_SYSCON is not set
# CONFIG_RESET_TI_TPS380X is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_PHY_CAN_TRANSCEIVER is not set
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_SUN6I_MIPI_DPHY=m
# CONFIG_PHY_SUN9I_USB is not set
CONFIG_PHY_SUN50I_USB3=y

#
# PHY drivers for Broadcom platforms
#
# CONFIG_BCM_KONA_USB2_PHY is not set
# end of PHY drivers for Broadcom platforms

# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_DPHY_RX is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_LAN966X_SERDES is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
CONFIG_PHY_QCOM_USB_HS=y
CONFIG_PHY_QCOM_USB_HSIC=y
# CONFIG_PHY_SAMSUNG_USB2 is not set
# CONFIG_PHY_TUSB1210 is not set
# end of PHY Subsystem

CONFIG_POWERCAP=y
# CONFIG_IDLE_INJECT is not set
# CONFIG_ARM_SCMI_POWERCAP is not set
# CONFIG_DTPM is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=y
CONFIG_ARM_CCI400_PMU=y
CONFIG_ARM_CCI5xx_PMU=y
CONFIG_ARM_CCN=y
# CONFIG_ARM_CMN is not set
CONFIG_ARM_PMU=y
CONFIG_ARM_PMU_ACPI=y
# CONFIG_ARM_SMMU_V3_PMU is not set
CONFIG_ARM_PMUV3=y
# CONFIG_ARM_DSU_PMU is not set
# CONFIG_ARM_SPE_PMU is not set
# CONFIG_ARM_DMC620_PMU is not set
# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set
CONFIG_HISI_PMU=y
# CONFIG_HISI_PCIE_PMU is not set
# CONFIG_HNS3_PMU is not set
# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set
# end of Performance monitor support

CONFIG_RAS=y
# CONFIG_USB4 is not set

#
# Android
#
# CONFIG_ANDROID_BINDER_IPC is not set
# end of Android

CONFIG_LIBNVDIMM=y
CONFIG_BLK_DEV_PMEM=m
CONFIG_ND_CLAIM=y
CONFIG_ND_BTT=m
CONFIG_BTT=y
CONFIG_OF_PMEM=y
CONFIG_NVDIMM_KEYS=y
# CONFIG_NVDIMM_SECURITY_TEST is not set
CONFIG_DAX=y
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y

#
# Layout Types
#
# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set
# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set
# end of Layout Types

# CONFIG_NVMEM_RMEM is not set
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_NVMEM_SUNXI_SID=y
# CONFIG_NVMEM_U_BOOT_ENV is not set

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# CONFIG_HISI_PTT is not set
# end of HW tracing support

# CONFIG_FPGA is not set
# CONFIG_FSI is not set
# CONFIG_TEE is not set
CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
# CONFIG_MUX_ADGS1408 is not set
CONFIG_MUX_GPIO=y
# CONFIG_MUX_MMIO is not set
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
CONFIG_SLIMBUS=m
CONFIG_SLIM_QCOM_CTRL=m
CONFIG_INTERCONNECT=y
# CONFIG_COUNTER is not set
# CONFIG_MOST is not set
# CONFIG_PECI is not set
# CONFIG_HTE is not set
# CONFIG_CDX_BUS is not set
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_IOMAP=y
CONFIG_BUFFER_HEAD=y
CONFIG_LEGACY_DIRECT_IO=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=m
# CONFIG_REISERFS_CHECK is not set
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
# CONFIG_JFS_DEBUG is not set
# CONFIG_JFS_STATISTICS is not set
CONFIG_XFS_FS=y
CONFIG_XFS_SUPPORT_V4=y
# CONFIG_XFS_SUPPORT_ASCII_CI is not set
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
# CONFIG_XFS_RT is not set
# CONFIG_XFS_ONLINE_SCRUB is not set
# CONFIG_XFS_WARN is not set
# CONFIG_XFS_DEBUG is not set
CONFIG_GFS2_FS=m
CONFIG_GFS2_FS_LOCKING_DLM=y
CONFIG_OCFS2_FS=m
CONFIG_OCFS2_FS_O2CB=m
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
# CONFIG_OCFS2_FS_STATS is not set
# CONFIG_OCFS2_DEBUG_MASKLOG is not set
# CONFIG_OCFS2_DEBUG_FS is not set
CONFIG_BTRFS_FS=m
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
# CONFIG_BTRFS_FS_REF_VERIFY is not set
CONFIG_NILFS2_FS=m
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
# CONFIG_F2FS_FAULT_INJECTION is not set
# CONFIG_F2FS_FS_COMPRESSION is not set
CONFIG_F2FS_IOSTAT=y
# CONFIG_F2FS_UNFAIR_RWSEM is not set
# CONFIG_ZONEFS_FS is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=m
CONFIG_CUSE=m
# CONFIG_VIRTIO_FS is not set
CONFIG_OVERLAY_FS=m
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set
# CONFIG_OVERLAY_FS_DEBUG is not set

#
# Caches
#
CONFIG_NETFS_SUPPORT=m
CONFIG_NETFS_STATS=y
CONFIG_FSCACHE=m
CONFIG_FSCACHE_STATS=y
# CONFIG_FSCACHE_DEBUG is not set
CONFIG_CACHEFILES=m
# CONFIG_CACHEFILES_DEBUG is not set
# CONFIG_CACHEFILES_ERROR_INJECTION is not set
# CONFIG_CACHEFILES_ONDEMAND is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
# CONFIG_FAT_DEFAULT_UTF8 is not set
CONFIG_EXFAT_FS=m
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS3_FS is not set
# end of DOS/FAT/EXFAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_TMPFS_INODE64 is not set
# CONFIG_TMPFS_QUOTA is not set
CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=y
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
CONFIG_AFFS_FS=m
CONFIG_ECRYPT_FS=m
# CONFIG_ECRYPT_FS_MESSAGING is not set
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
CONFIG_BEFS_FS=m
# CONFIG_BEFS_DEBUG is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_UBIFS_FS=m
# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
CONFIG_CRAMFS=m
CONFIG_CRAMFS_BLOCKDEV=y
# CONFIG_CRAMFS_MTD is not set
CONFIG_SQUASHFS=m
CONFIG_SQUASHFS_FILE_CACHE=y
# CONFIG_SQUASHFS_FILE_DIRECT is not set
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set
CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
# CONFIG_SQUASHFS_ZSTD is not set
# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
# CONFIG_SQUASHFS_EMBEDDED is not set
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
CONFIG_MINIX_FS=m
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
CONFIG_ROMFS_FS=m
CONFIG_ROMFS_BACKED_BY_BLOCK=y
# CONFIG_ROMFS_BACKED_BY_MTD is not set
# CONFIG_ROMFS_BACKED_BY_BOTH is not set
CONFIG_ROMFS_ON_BLOCK=y
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
CONFIG_PSTORE_COMPRESS=y
# CONFIG_PSTORE_CONSOLE is not set
# CONFIG_PSTORE_PMSG is not set
CONFIG_PSTORE_RAM=m
# CONFIG_PSTORE_BLK is not set
CONFIG_SYSV_FS=m
CONFIG_UFS_FS=m
# CONFIG_UFS_FS_WRITE is not set
# CONFIG_UFS_DEBUG is not set
# CONFIG_EROFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
# CONFIG_NFS_V2 is not set
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_SWAP=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=y
CONFIG_PNFS_BLOCK=y
CONFIG_PNFS_FLEXFILE_LAYOUT=y
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
# CONFIG_NFS_V4_1_MIGRATION is not set
CONFIG_NFS_V4_SECURITY_LABEL=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DEBUG=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
# CONFIG_NFS_V4_2_READ_PLUS is not set
CONFIG_NFSD=m
# CONFIG_NFSD_V2 is not set
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
CONFIG_NFSD_PNFS=y
CONFIG_NFSD_BLOCKLAYOUT=y
CONFIG_NFSD_SCSILAYOUT=y
CONFIG_NFSD_FLEXFILELAYOUT=y
CONFIG_NFSD_V4_2_INTER_SSC=y
CONFIG_NFSD_V4_SECURITY_LABEL=y
CONFIG_GRACE_PERIOD=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_NFS_V4_2_SSC_HELPER=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_BACKCHANNEL=y
CONFIG_SUNRPC_SWAP=y
CONFIG_RPCSEC_GSS_KRB5=m
# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1 is not set
# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA is not set
# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 is not set
CONFIG_SUNRPC_DEBUG=y
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
# CONFIG_CEPH_FS_SECURITY_LABEL is not set
CONFIG_CIFS=m
# CONFIG_CIFS_STATS2 is not set
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CIFS_DEBUG=y
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
CONFIG_CIFS_DFS_UPCALL=y
# CONFIG_CIFS_SWN_UPCALL is not set
CONFIG_CIFS_FSCACHE=y
# CONFIG_SMB_SERVER is not set
CONFIG_SMBFS=m
CONFIG_CODA_FS=m
# CONFIG_AFS_FS is not set
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
CONFIG_9P_FS_SECURITY=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=m
CONFIG_NLS_MAC_GAELIC=m
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=m
CONFIG_NLS_UCS2_UTILS=m
CONFIG_DLM=m
CONFIG_DLM_DEBUG=y
# CONFIG_UNICODE is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
CONFIG_PERSISTENT_KEYRINGS=y
CONFIG_TRUSTED_KEYS=m
# CONFIG_TRUSTED_KEYS_TPM is not set

#
# No trust source selected!
#
CONFIG_ENCRYPTED_KEYS=y
# CONFIG_USER_DECRYPTED_DATA is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_KEY_NOTIFICATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_PROC_MEM_ALWAYS_FORCE=y
# CONFIG_PROC_MEM_FORCE_PTRACE is not set
# CONFIG_PROC_MEM_NO_FORCE is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_NETWORK_XFRM=y
# CONFIG_SECURITY_PATH is not set
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
# CONFIG_SECURITY_SELINUX is not set
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_SECURITY_APPARMOR is not set
# CONFIG_SECURITY_LOADPIN is not set
CONFIG_SECURITY_YAMA=y
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
# CONFIG_SECURITY_LANDLOCK is not set
# CONFIG_INTEGRITY is not set
# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
CONFIG_INIT_STACK_NONE=y
# CONFIG_INIT_STACK_ALL_PATTERN is not set
# CONFIG_INIT_STACK_ALL_ZERO is not set
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
# CONFIG_ZERO_CALL_USED_REGS is not set
# end of Memory initialization

#
# Hardening of kernel data structures
#
CONFIG_LIST_HARDENED=y
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# end of Hardening of kernel data structures

CONFIG_RANDSTRUCT_NONE=y
# CONFIG_RANDSTRUCT_FULL is not set
# CONFIG_RANDSTRUCT_PERFORMANCE is not set
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=m
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SIG=y
CONFIG_CRYPTO_SIG2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=m
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=m
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=m
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=m
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_ENGINE=y
# end of Crypto core or helper

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=m
# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set
CONFIG_CRYPTO_ECC=m
CONFIG_CRYPTO_ECDH=m
# CONFIG_CRYPTO_ECDSA is not set
# CONFIG_CRYPTO_ECRDSA is not set
# CONFIG_CRYPTO_SM2 is not set
# CONFIG_CRYPTO_CURVE25519 is not set
# end of Public-key cryptography

#
# Block ciphers
#
CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_AES_TI is not set
CONFIG_CRYPTO_ANUBIS=m
# CONFIG_CRYPTO_ARIA is not set
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_BLOWFISH_COMMON=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST_COMMON=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=m
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_GENERIC=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_TWOFISH_COMMON=m
# end of Block ciphers

#
# Length-preserving ciphers and modes
#
CONFIG_CRYPTO_ADIANTUM=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=m
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_HCTR2 is not set
CONFIG_CRYPTO_KEYWRAP=m
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_OFB=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_NHPOLY1305=y
# end of Length-preserving ciphers and modes

#
# AEAD (authenticated encryption with associated data) ciphers
#
CONFIG_CRYPTO_AEGIS128=m
# CONFIG_CRYPTO_AEGIS128_SIMD is not set
CONFIG_CRYPTO_CHACHA20POLY1305=m
CONFIG_CRYPTO_CCM=m
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_GENIV=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=m
CONFIG_CRYPTO_ESSIV=m
# end of AEAD (authenticated encryption with associated data) ciphers

#
# Hashes, digests, and MACs
#
CONFIG_CRYPTO_BLAKE2B=m
CONFIG_CRYPTO_CMAC=m
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_SM3_GENERIC=m
# CONFIG_CRYPTO_STREEBOG is not set
CONFIG_CRYPTO_VMAC=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_XXHASH=m
# end of Hashes, digests, and MACs

#
# CRCs (cyclic redundancy checks)
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
# end of CRCs (cyclic redundancy checks)

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=m
CONFIG_CRYPTO_LZ4=m
CONFIG_CRYPTO_LZ4HC=m
CONFIG_CRYPTO_ZSTD=m
# end of Compression

#
# Random number generation
#
CONFIG_CRYPTO_ANSI_CPRNG=m
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
# CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE is not set
# end of Random number generation

#
# Userspace interface
#
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
# CONFIG_CRYPTO_STATS is not set
# end of Userspace interface

CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_NHPOLY1305_NEON=y
CONFIG_CRYPTO_CHACHA20_NEON=y

#
# Accelerated Cryptographic Algorithms for CPU (arm64)
#
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_POLY1305_NEON=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA512_ARM64_CE=y
CONFIG_CRYPTO_SHA3_ARM64=y
# CONFIG_CRYPTO_SM3_NEON is not set
CONFIG_CRYPTO_SM3_ARM64_CE=y
# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CRYPTO_SM4_ARM64_CE=y
# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
# CONFIG_CRYPTO_SM4_ARM64_CE_CCM is not set
# CONFIG_CRYPTO_SM4_ARM64_CE_GCM is not set
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
# end of Accelerated Cryptographic Algorithms for CPU (arm64)

CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_ALLWINNER=y
# CONFIG_CRYPTO_DEV_SUN4I_SS is not set
CONFIG_CRYPTO_DEV_SUN8I_CE=m
# CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG is not set
# CONFIG_CRYPTO_DEV_SUN8I_CE_HASH is not set
# CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG is not set
# CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG is not set
CONFIG_CRYPTO_DEV_SUN8I_SS=m
# CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG is not set
# CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG is not set
# CONFIG_CRYPTO_DEV_SUN8I_SS_HASH is not set
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
CONFIG_CRYPTO_DEV_CCP=y
CONFIG_CRYPTO_DEV_CCP_DD=m
CONFIG_CRYPTO_DEV_SP_CCP=y
CONFIG_CRYPTO_DEV_CCP_CRYPTO=m
# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set
# CONFIG_CRYPTO_DEV_QAT_C62X is not set
# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set
# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_VIRTIO=m
CONFIG_CRYPTO_DEV_SAFEXCEL=m
CONFIG_CRYPTO_DEV_CCREE=m
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
# CONFIG_CRYPTO_DEV_HISI_TRNG is not set
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_PKCS7_TEST_KEY is not set
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
# CONFIG_FIPS_SIGNATURE_SELFTEST is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_RAID6_PQ=m
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
# CONFIG_PACKING is not set
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=m
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
# CONFIG_INDIRECT_PIO is not set

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=m
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=m
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
CONFIG_CRYPTO_LIB_CURVE25519=m
CONFIG_CRYPTO_LIB_DES=m
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=m
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines

CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC64_ROCKSOFT=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=y
# CONFIG_CRC4 is not set
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=y
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_842_COMPRESS=m
CONFIG_842_DECOMPRESS=m
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=m
CONFIG_LZ4HC_COMPRESS=m
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=m
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
# CONFIG_XZ_DEC_SPARC is not set
# CONFIG_XZ_DEC_MICROLZMA is not set
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_REED_SOLOMON=m
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_BCH=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_BTREE=y
CONFIG_INTERVAL_TREE=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_FLAGS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_SWIOTLB=y
# CONFIG_SWIOTLB_DYNAMIC is not set
CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
# CONFIG_DMA_RESTRICTED_POOL is not set
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_DMA_MAP_BENCHMARK is not set
CONFIG_SGL_ALLOC=y
CONFIG_CHECK_SIGNATURE=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
CONFIG_IRQ_POLL=y
CONFIG_MPILIB=y
CONFIG_DIMLIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_MEMREGION=y
CONFIG_ARCH_STACKWALK=y
CONFIG_STACKDEPOT=y
CONFIG_SBITMAP=y
# end of Library routines

CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_CALLER is not set
CONFIG_STACKTRACE_BUILD_ID=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
CONFIG_BOOT_PRINTK_DELAY=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Compile-time checks and compiler options
#
CONFIG_AS_HAS_NON_CONST_LEB128=y
CONFIG_DEBUG_INFO_NONE=y
# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_DEBUG_INFO_DWARF5 is not set
CONFIG_FRAME_WARN=1024
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_READABLE_ASM is not set
# CONFIG_HEADERS_INSTALL is not set
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_VMLINUX_MAP is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_KGDB=y
CONFIG_KGDB_HONOUR_BLOCKLIST=y
CONFIG_KGDB_SERIAL_CONSOLE=y
CONFIG_KGDB_TESTS=y
# CONFIG_KGDB_TESTS_ON_BOOT is not set
# CONFIG_KGDB_KDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_ARCH_KCSAN=y
CONFIG_HAVE_KCSAN_COMPILER=y
# CONFIG_KCSAN is not set
# end of Generic Kernel Debugging Instruments

#
# Networking Debugging
#
# CONFIG_NET_DEV_REFCNT_TRACKER is not set
# CONFIG_NET_NS_REFCNT_TRACKER is not set
# CONFIG_DEBUG_NET is not set
# end of Networking Debugging

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_SLUB_DEBUG=y
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_TABLE_CHECK is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_PER_VMA_LOCK_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SHRINKER_DEBUG is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
CONFIG_DEBUG_VM_IRQSOFF=y
CONFIG_DEBUG_VM=y
# CONFIG_DEBUG_VM_MAPLE_TREE is not set
# CONFIG_DEBUG_VM_RB is not set
# CONFIG_DEBUG_VM_PGFLAGS is not set
CONFIG_DEBUG_VM_PGTABLE=y
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
# end of Memory Debugging

# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y
# CONFIG_HARDLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
CONFIG_SCHED_DEBUG=y
CONFIG_SCHED_INFO=y
CONFIG_SCHEDSTATS=y
# end of Scheduler Debugging

# CONFIG_DEBUG_TIMEKEEPING is not set

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

# CONFIG_DEBUG_IRQFLAGS is not set
CONFIG_STACKTRACE=y
# CONFIG_DEBUG_KOBJECT is not set

#
# Debug kernel data structures
#
CONFIG_DEBUG_LIST=y
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_MAPLE_TREE is not set
# end of Debug kernel data structures

#
# RCU Debugging
#
CONFIG_TORTURE_TEST=m
# CONFIG_RCU_SCALE_TEST is not set
CONFIG_RCU_TORTURE_TEST=m
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=60
CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
# CONFIG_RCU_CPU_STALL_CPUTIME is not set
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
# CONFIG_LATENCYTOP is not set
# CONFIG_DEBUG_CGROUP_REF is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y
CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y
CONFIG_STRICT_DEVMEM=y
# CONFIG_IO_STRICT_DEVMEM is not set

#
# arm64 Debugging
#
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
# end of arm64 Debugging

#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
CONFIG_FUNCTION_ERROR_INJECTION=y
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_ARCH_USE_MEMTEST=y
# CONFIG_MEMTEST is not set
# end of Kernel Testing and Coverage

#
# Rust hacking
#
# end of Rust hacking
# end of Kernel hacking


================================================
FILE: kernel-config/release/rk3588/config-5.10
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 5.10.160 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 15.2.Rel1 (Build arm-15.86)) 15.2.1 20251203"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=150201
CONFIG_LD_VERSION=245010000
CONFIG_CLANG_VERSION=0
CONFIG_LLD_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
# CONFIG_UAPI_HEADER_TEST is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT="/sbin/init"
CONFIG_DEFAULT_HOSTNAME="none"
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
# CONFIG_WATCH_QUEUE is not set
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_USELIB is not set
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_ARCH_WANTS_IRQ_RAW=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem

CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
# CONFIG_NO_HZ_FULL is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_PREEMPTION=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_SCHED_THERMAL_PRESSURE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
CONFIG_PREEMPT_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_TASKS_RCU=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
CONFIG_UCLAMP_TASK=y
CONFIG_UCLAMP_BUCKETS_COUNT=20
# end of Scheduler features

CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_CC_HAS_INT128=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
CONFIG_MEMCG=y
CONFIG_MEMCG_SWAP=y
CONFIG_MEMCG_KMEM=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_UCLAMP_TASK_GROUP=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_SCHED_AUTOGROUP=y
# CONFIG_RT_SOFTINT_OPTIMIZATION is not set
# CONFIG_SYSFS_DEPRECATED is not set
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
# CONFIG_INITRD_ASYNC is not set
# CONFIG_BOOT_CONFIG is not set
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_BPF=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
# CONFIG_SGETMASK_SYSCALL is not set
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_PRINTK_NMI=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_HAVE_FUTEX_CMPXCHG=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
CONFIG_KALLSYMS_BASE_RELATIVE=y
# CONFIG_BPF_LSM is not set
CONFIG_BPF_SYSCALL=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
CONFIG_BPF_JIT_DEFAULT_ON=y
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
# CONFIG_BPF_PRELOAD is not set
# CONFIG_USERFAULTFD is not set
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_SYSFS=y
CONFIG_SLUB_DEBUG=y
# CONFIG_SLUB_MEMCG_SYSFS_ON is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
# CONFIG_SLAB_FREELIST_RANDOM is not set
# CONFIG_SLAB_FREELIST_HARDENED is not set
CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
# CONFIG_SLUB_CPU_PARTIAL is not set
CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
# end of General setup

CONFIG_ARM64=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_CONT_PTE_SHIFT=4
CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ZONE_DMA=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y

#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
# CONFIG_ARCH_AGILEX is not set
# CONFIG_ARCH_SUNXI is not set
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_BCM2835 is not set
# CONFIG_ARCH_BCM_IPROC is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
# CONFIG_ARCH_BRCMSTB is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SPARX5 is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LAYERSCAPE is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_KEEMBAY is not set
# CONFIG_ARCH_MEDIATEK is not set
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_RENESAS is not set
CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_S32 is not set
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_STRATIX10 is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZX is not set
# CONFIG_ARCH_ZYNQMP is not set
# end of Platform selection

#
# Kernel Features
#

#
# ARM errata workarounds via the alternatives framework
#
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_834220=y
CONFIG_ARM64_ERRATUM_1742098=y
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1319367=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_ARM64_ERRATUM_2051678=y
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
CONFIG_ARM64_ERRATUM_2054223=y
CONFIG_ARM64_ERRATUM_2067961=y
CONFIG_ARM64_ERRATUM_2454944=y
CONFIG_ARM64_ERRATUM_2457168=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
CONFIG_QCOM_FALKOR_ERRATUM_1009=y
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
# end of ARM errata workarounds via the alternatives framework

CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
# CONFIG_ARM64_VA_BITS_39 is not set
CONFIG_ARM64_VA_BITS_48=y
CONFIG_ARM64_VA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SCHED_MC=y
# CONFIG_SCHED_SMT is not set
CONFIG_NR_CPUS=8
CONFIG_HOTPLUG_CPU=y
# CONFIG_NUMA is not set
CONFIG_HOLES_IN_ZONE=y
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
CONFIG_HZ_300=y
# CONFIG_HZ_1000 is not set
CONFIG_HZ=300
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_KEXEC is not set
# CONFIG_KEXEC_FILE is not set
# CONFIG_CRASH_DUMP is not set
# CONFIG_XEN is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y

#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
CONFIG_AS_HAS_LDAPR=y
CONFIG_AS_HAS_LSE_ATOMICS=y
CONFIG_ARM64_VHE=y
# end of ARMv8.1 architectural features

#
# ARMv8.2 architectural features
#
CONFIG_ARM64_UAO=y
# CONFIG_ARM64_PMEM is not set
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features

#
# ARMv8.3 architectural features
#
CONFIG_ARM64_PTR_AUTH=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
CONFIG_AS_HAS_PAC=y
CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
# end of ARMv8.3 architectural features

#
# ARMv8.4 architectural features
#
CONFIG_ARM64_AMU_EXTN=y
CONFIG_AS_HAS_ARMV8_4=y
CONFIG_ARM64_TLB_RANGE=y
# end of ARMv8.4 architectural features

#
# ARMv8.5 architectural features
#
CONFIG_AS_HAS_ARMV8_5=y
CONFIG_ARM64_BTI=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARCH_RANDOM=y
CONFIG_ARM64_AS_HAS_MTE=y
CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features

CONFIG_ARM64_SVE=y
CONFIG_ARM64_MODULE_PLTS=y
CONFIG_ARM64_PSEUDO_NMI=y
# CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
# end of Kernel Features

#
# Boot options
#
CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
CONFIG_CMDLINE=""
CONFIG_EFI_STUB=y
CONFIG_EFI=y
CONFIG_DMI=y
# end of Boot options

CONFIG_SYSVIPC_COMPAT=y
CONFIG_ARCH_ENABLE_THP_MIGRATION=y

#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
# CONFIG_HIBERNATION is not set
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
# CONFIG_PM_TEST_SUSPEND is not set
CONFIG_PM_SLEEP_DEBUG=y
CONFIG_DPM_WATCHDOG=y
CONFIG_DPM_WATCHDOG_TIMEOUT=120
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options

#
# CPU Power Management
#

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
# CONFIG_CPU_IDLE_GOV_LADDER is not set
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_DT_IDLE_STATES=y

#
# ARM CPU Idle Drivers
#
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
# end of ARM CPU Idle Drivers
# end of CPU Idle

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_TIMES=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
# CONFIG_CPU_FREQ_GOV_INTERACTIVE is not set

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
# CONFIG_CPUFREQ_DUMMY is not set
CONFIG_ACPI_CPPC_CPUFREQ=y
CONFIG_ARM_ROCKCHIP_CPUFREQ=y
CONFIG_ARM_SCMI_CPUFREQ=y
# end of CPU Frequency scaling
# end of CPU Power Management

#
# Firmware Drivers
#
CONFIG_ARM_SCMI_PROTOCOL=y
CONFIG_ARM_SCMI_POWER_DOMAIN=y
# CONFIG_ARM_SCPI_PROTOCOL is not set
# CONFIG_ARM_SDE_INTERFACE is not set
# CONFIG_FIRMWARE_MEMMAP is not set
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=y
# CONFIG_ISCSI_IBFT is not set
CONFIG_FW_CFG_SYSFS=y
CONFIG_FW_CFG_SYSFS_CMDLINE=y
# CONFIG_QCOM_SCM is not set
CONFIG_ROCKCHIP_SIP=y
# CONFIG_GOOGLE_FIRMWARE is not set

#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_VARS_PSTORE=y
# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_GENERIC_STUB=y
CONFIG_EFI_ARMSTUB_DTB_LOADER=y
CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
# CONFIG_EFI_BOOTLOADER_CONTROL is not set
# CONFIG_EFI_CAPSULE_LOADER is not set
# CONFIG_EFI_TEST is not set
# CONFIG_RESET_ATTACK_MITIGATION is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
# end of EFI (Extensible Firmware Interface) Support

CONFIG_UEFI_CPER=y
CONFIG_UEFI_CPER_ARM=y
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_PSCI_CHECKER is not set
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_ARM_SMCCC_SOC_ID=y

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_GENERIC_GSI=y
CONFIG_ACPI_CCA_REQUIRED=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
CONFIG_ACPI_EC_DEBUGFS=m
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_FAN=y
CONFIG_ACPI_TAD=m
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_MCFG=y
CONFIG_ACPI_CPPC_LIB=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_HOTPLUG_CPU=y
CONFIG_ACPI_THERMAL=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_PCI_SLOT=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_CUSTOM_METHOD=m
CONFIG_ACPI_BGRT=y
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
CONFIG_HAVE_ACPI_APEI=y
CONFIG_ACPI_APEI=y
CONFIG_ACPI_APEI_GHES=y
CONFIG_ACPI_APEI_SEA=y
CONFIG_ACPI_APEI_EINJ=m
CONFIG_ACPI_APEI_ERST_DEBUG=m
CONFIG_ACPI_CONFIGFS=m
CONFIG_ACPI_IORT=y
CONFIG_ACPI_GTDT=y
CONFIG_ACPI_PPTT=y
CONFIG_PMIC_OPREGION=y
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_MMIO=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_ARM64_CRYPTO=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64_CE=y
CONFIG_CRYPTO_SHA3_ARM64=y
CONFIG_CRYPTO_SM3_ARM64_CE=y
CONFIG_CRYPTO_SM4_ARM64_CE=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_CHACHA20_NEON=y
CONFIG_CRYPTO_POLY1305_NEON=y
CONFIG_CRYPTO_NHPOLY1305_NEON=y
CONFIG_CRYPTO_AES_ARM64_BS=y

#
# General architecture-dependent options
#
CONFIG_SET_FS=y
CONFIG_KPROBES=y
# CONFIG_JUMP_LABEL is not set
CONFIG_UPROBES=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLK_RQ_ALLOC_TIME=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BLK_CGROUP_RWSTAT=y
CONFIG_BLK_DEV_BSG=y
CONFIG_BLK_DEV_BSGLIB=y
# CONFIG_BLK_DEV_INTEGRITY is not set
# CONFIG_BLK_DEV_ZONED is not set
# CONFIG_BLK_DEV_THROTTLING is not set
CONFIG_BLK_CMDLINE_PARSER=y
CONFIG_BLK_WBT=y
CONFIG_BLK_WBT_MQ=y
# CONFIG_BLK_CGROUP_IOLATENCY is not set
CONFIG_BLK_CGROUP_IOCOST=y
CONFIG_BLK_CGROUP_IOPRIO=y
CONFIG_BLK_DEBUG_FS=y
# CONFIG_BLK_SED_OPAL is not set
# CONFIG_BLK_INLINE_ENCRYPTION is not set

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_AIX_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
CONFIG_CMDLINE_PARTITION=y
# end of Partition Types

CONFIG_BLOCK_COMPAT=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=m
CONFIG_BLK_PM=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_DEADLINE_CGROUP=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
# CONFIG_BFQ_CGROUP_DEBUG is not set
# end of IO Schedulers

CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
# CONFIG_GKI_HIDDEN_DRM_CONFIGS is not set
# CONFIG_GKI_HIDDEN_REGMAP_CONFIGS is not set
# CONFIG_GKI_HIDDEN_CRYPTO_CONFIGS is not set
# CONFIG_GKI_HIDDEN_SND_CONFIGS is not set
# CONFIG_GKI_HIDDEN_SND_SOC_CONFIGS is not set
# CONFIG_GKI_HIDDEN_MMC_CONFIGS is not set
# CONFIG_GKI_HIDDEN_GPIO_CONFIGS is not set
# CONFIG_GKI_HIDDEN_QCOM_CONFIGS is not set
# CONFIG_GKI_HIDDEN_MEDIA_CONFIGS is not set
# CONFIG_GKI_HIDDEN_VIRTUAL_CONFIGS is not set
# CONFIG_GKI_LEGACY_WEXT_ALLCONFIG is not set
# CONFIG_GKI_HIDDEN_USB_CONFIGS is not set
# CONFIG_GKI_HIDDEN_SOC_BUS_CONFIGS is not set
# CONFIG_GKI_HIDDEN_RPMSG_CONFIGS is not set
# CONFIG_GKI_HIDDEN_GPU_CONFIGS is not set
# CONFIG_GKI_HIDDEN_IRQ_CONFIGS is not set
# CONFIG_GKI_HIDDEN_HYPERVISOR_CONFIGS is not set
# CONFIG_GKI_HIDDEN_NET_CONFIGS is not set
# CONFIG_GKI_HIDDEN_PHY_CONFIGS is not set
# CONFIG_GKI_HIDDEN_MM_CONFIGS is not set
# CONFIG_GKI_HIDDEN_DMA_CONFIGS is not set
# CONFIG_GKI_HIDDEN_ETHERNET_CONFIGS is not set
# CONFIG_GKI_HACKS_TO_FIX is not set
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_HAVE_ELF_PROT=y
CONFIG_ARCH_USE_GNU_PROPERTY=y
CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=m
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_BOUNCE=y
CONFIG_MMU_NOTIFIER=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
# CONFIG_MEMORY_FAILURE is not set
CONFIG_TRANSPARENT_HUGEPAGE=y
# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set
CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
CONFIG_CLEANCACHE=y
CONFIG_FRONTSWAP=y
CONFIG_CMA=y
# CONFIG_CMA_INACTIVE is not set
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_CMA_AREAS=7
# CONFIG_ZSWAP is not set
CONFIG_ZPOOL=y
CONFIG_ZBUD=y
CONFIG_Z3FOLD=y
CONFIG_ZSMALLOC=y
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_PAGE_IDLE_FLAG=y
CONFIG_IDLE_PAGE_TRACKING=y
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_FRAME_VECTOR=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
CONFIG_PERCPU_STATS=y
CONFIG_ARCH_SUPPORTS_SPECULATIVE_PAGE_FAULT=y
CONFIG_SPECULATIVE_PAGE_FAULT=y
# CONFIG_GUP_BENCHMARK is not set
# CONFIG_READ_ONLY_THP_FOR_FS is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
# CONFIG_LRU_GEN is not set

#
# Data Access Monitoring
#
# CONFIG_DAMON is not set
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_EXTENSIONS=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_UNIX_SCM=y
CONFIG_UNIX_DIAG=y
# CONFIG_TLS is not set
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
# CONFIG_XFRM_INTERFACE is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_AH=m
CONFIG_XFRM_ESP=m
CONFIG_XFRM_IPCOMP=m
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_XFRM_ESPINTCP=y
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
# CONFIG_IP_FIB_TRIE_STATS is not set
CONFIG_IP_MULTIPLE_TABLES=y
# CONFIG_IP_ROUTE_MULTIPATH is not set
# CONFIG_IP_ROUTE_VERBOSE is not set
CONFIG_IP_ROUTE_CLASSID=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=m
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=m
CONFIG_NET_FOU=m
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_ESP_OFFLOAD=m
CONFIG_INET_ESPINTCP=y
CONFIG_INET_IPCOMP=m
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_DIAG=m
CONFIG_INET_TCP_DIAG=m
CONFIG_INET_UDP_DIAG=m
CONFIG_INET_RAW_DIAG=m
# CONFIG_INET_DIAG_DESTROY is not set
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_NV=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_CONG_DCTCP=m
CONFIG_TCP_CONG_CDG=m
CONFIG_TCP_CONG_BBR=m
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=m
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_ESP_OFFLOAD=m
CONFIG_INET6_ESPINTCP=y
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_MIP6=m
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=m
CONFIG_INET6_TUNNEL=m
CONFIG_IPV6_VTI=m
CONFIG_IPV6_SIT=m
CONFIG_IPV6_SIT_6RD=y
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=m
CONFIG_IPV6_GRE=m
CONFIG_IPV6_FOU=m
CONFIG_IPV6_FOU_TUNNEL=m
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
# CONFIG_IPV6_SEG6_HMAC is not set
# CONFIG_IPV6_RPL_LWTUNNEL is not set
# CONFIG_NETLABEL is not set
# CONFIG_MPTCP is not set
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NETWORK_PHY_TIMESTAMPING=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_NETLINK=y
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
CONFIG_NETFILTER_NETLINK_ACCT=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NETFILTER_NETLINK_OSF=m
CONFIG_NF_CONNTRACK=y
CONFIG_NF_LOG_COMMON=m
CONFIG_NF_LOG_NETDEV=m
CONFIG_NETFILTER_CONNCOUNT=m
CONFIG_NF_CONNTRACK_MARK=y
# CONFIG_NF_CONNTRACK_SECMARK is not set
# CONFIG_NF_CONNTRACK_ZONES is not set
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y
# CONFIG_NF_CONNTRACK_TIMEOUT is not set
CONFIG_NF_CONNTRACK_TIMESTAMP=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=y
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=y
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_COUNTER=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_OBJREF=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
CONFIG_NFT_OSF=m
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NF_DUP_NETDEV=y
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XTABLES=y

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=y
CONFIG_NETFILTER_XT_CONNMARK=y
CONFIG_NETFILTER_XT_SET=m

#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_AUDIT=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LED=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=y
CONFIG_NETFILTER_XT_TARGET_NETMAP=y
CONFIG_NETFILTER_XT_TARGET_FULLCONENAT=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD=m
CONFIG_NETFILTER_XT_TARGET_RATEEST=y
CONFIG_NETFILTER_XT_TARGET_REDIRECT=y
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
CONFIG_NETFILTER_XT_TARGET_SECMARK=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=y
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=y
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_QUOTA2=m
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# end of Core Netfilter Configuration

CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
# CONFIG_IP_VS_DEBUG is not set
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_SOCKET_IPV4=m
CONFIG_NF_TPROXY_IPV4=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=m
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_FULLCONENAT=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_SECURITY=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP6_NF_SECURITY=m
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=y
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_NFT_BRIDGE_META=m
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NF_LOG_BRIDGE=m
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
# CONFIG_BPFILTER is not set
# CONFIG_IP_DCCP is not set
CONFIG_IP_SCTP=m
# CONFIG_SCTP_DBG_OBJCNT is not set
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=m
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
CONFIG_ATM=m
# CONFIG_ATM_CLIP is not set
# CONFIG_ATM_LANE is not set
CONFIG_ATM_BR2684=m
# CONFIG_ATM_BR2684_IPFILTER is not set
CONFIG_L2TP=m
# CONFIG_L2TP_DEBUGFS is not set
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=m
CONFIG_L2TP_ETH=m
CONFIG_STP=m
CONFIG_BRIDGE=m
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
# CONFIG_BRIDGE_MRP is not set
CONFIG_HAVE_NET_DSA=y
CONFIG_NET_DSA=m
CONFIG_NET_DSA_TAG_8021Q=m
CONFIG_NET_DSA_TAG_AR9331=m
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
CONFIG_NET_DSA_TAG_BRCM=m
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
CONFIG_NET_DSA_TAG_GSWIP=m
CONFIG_NET_DSA_TAG_DSA=m
CONFIG_NET_DSA_TAG_EDSA=m
CONFIG_NET_DSA_TAG_MTK=m
CONFIG_NET_DSA_TAG_KSZ=m
CONFIG_NET_DSA_TAG_RTL4_A=m
CONFIG_NET_DSA_TAG_OCELOT=m
CONFIG_NET_DSA_TAG_QCA=m
CONFIG_NET_DSA_TAG_LAN9303=m
CONFIG_NET_DSA_TAG_SJA1105=m
CONFIG_NET_DSA_TAG_TRAILER=m
CONFIG_VLAN_8021Q=m
# CONFIG_VLAN_8021Q_GVRP is not set
# CONFIG_VLAN_8021Q_MVRP is not set
# CONFIG_DECNET is not set
CONFIG_LLC=m
CONFIG_LLC2=m
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
CONFIG_6LOWPAN=m
# CONFIG_6LOWPAN_DEBUGFS is not set
CONFIG_6LOWPAN_NHC=m
CONFIG_6LOWPAN_NHC_DEST=m
CONFIG_6LOWPAN_NHC_FRAGMENT=m
CONFIG_6LOWPAN_NHC_HOP=m
CONFIG_6LOWPAN_NHC_IPV6=m
CONFIG_6LOWPAN_NHC_MOBILITY=m
CONFIG_6LOWPAN_NHC_ROUTING=m
CONFIG_6LOWPAN_NHC_UDP=m
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
CONFIG_6LOWPAN_GHC_UDP=m
CONFIG_6LOWPAN_GHC_ICMPV6=m
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
CONFIG_IEEE802154=m
# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set
CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_MAC802154=m
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_ATM=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFB=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_SKBPRIO=m
CONFIG_NET_SCH_CHOKE=m
CONFIG_NET_SCH_QFQ=m
CONFIG_NET_SCH_CODEL=m
CONFIG_NET_SCH_FQ_CODEL=m
CONFIG_NET_SCH_CAKE=m
CONFIG_NET_SCH_FQ=m
CONFIG_NET_SCH_HHF=m
CONFIG_NET_SCH_PIE=m
CONFIG_NET_SCH_FQ_PIE=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_SCH_PLUG=m
CONFIG_NET_SCH_ETS=m
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
# CONFIG_CLS_U32_PERF is not set
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_RSVP=m
CONFIG_NET_CLS_RSVP6=m
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=m
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_EMATCH_CANID=m
CONFIG_NET_EMATCH_IPSET=m
CONFIG_NET_EMATCH_IPT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
# CONFIG_NET_ACT_SAMPLE is not set
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
CONFIG_NET_ACT_MPLS=m
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_NET_ACT_CONNMARK=m
CONFIG_NET_ACT_CTINFO=m
CONFIG_NET_ACT_SKBMOD=m
CONFIG_NET_ACT_IFE=m
CONFIG_NET_ACT_TUNNEL_KEY=m
# CONFIG_NET_ACT_CT is not set
CONFIG_NET_ACT_GATE=m
CONFIG_NET_IFE_SKBMARK=m
CONFIG_NET_IFE_SKBPRIO=m
CONFIG_NET_IFE_SKBTCINDEX=m
# CONFIG_NET_TC_SKB_EXT is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=y
CONFIG_BATMAN_ADV=m
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
# CONFIG_BATMAN_ADV_NC is not set
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUGFS is not set
# CONFIG_BATMAN_ADV_DEBUG is not set
# CONFIG_BATMAN_ADV_SYSFS is not set
# CONFIG_BATMAN_ADV_TRACING is not set
CONFIG_OPENVSWITCH=m
CONFIG_OPENVSWITCH_GRE=m
CONFIG_OPENVSWITCH_VXLAN=m
CONFIG_OPENVSWITCH_GENEVE=m
CONFIG_VSOCKETS=m
CONFIG_VSOCKETS_DIAG=m
CONFIG_VSOCKETS_LOOPBACK=m
CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO_VSOCKETS_COMMON=m
CONFIG_NETLINK_DIAG=y
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=m
# CONFIG_MPLS_ROUTING is not set
CONFIG_NET_NSH=m
# CONFIG_HSR is not set
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=m
# CONFIG_QRTR_SMD is not set
# CONFIG_QRTR_TUN is not set
CONFIG_QRTR_MHI=m
# CONFIG_NET_NCSI is not set
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_XPS=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_JIT=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_NET_DROP_MONITOR is not set
# end of Network testing
# end of Networking options

# CONFIG_HAMRADIO is not set
CONFIG_CAN=m
CONFIG_CAN_RAW=m
CONFIG_CAN_BCM=m
CONFIG_CAN_GW=m
# CONFIG_CAN_J1939 is not set
# CONFIG_CAN_ISOTP is not set

#
# CAN Device Drivers
#
CONFIG_CAN_VCAN=m
# CONFIG_CAN_VXCAN is not set
CONFIG_CAN_SLCAN=m
CONFIG_CAN_DEV=m
CONFIG_CAN_CALC_BITTIMING=y
# CONFIG_CAN_FLEXCAN is not set
CONFIG_CAN_GRCAN=m
# CONFIG_CAN_KVASER_PCIEFD is not set
CONFIG_CAN_XILINXCAN=m
CONFIG_CAN_C_CAN=m
CONFIG_CAN_C_CAN_PLATFORM=m
CONFIG_CAN_C_CAN_PCI=m
CONFIG_CAN_CC770=m
CONFIG_CAN_CC770_ISA=m
CONFIG_CAN_CC770_PLATFORM=m
# CONFIG_CAN_IFI_CANFD is not set
CONFIG_CAN_M_CAN=m
# CONFIG_CAN_M_CAN_PLATFORM is not set
# CONFIG_CAN_M_CAN_TCAN4X5X is not set
# CONFIG_CAN_PEAK_PCIEFD is not set
# CONFIG_CAN_ROCKCHIP is not set
# CONFIG_CANFD_ROCKCHIP is not set
CONFIG_CAN_SJA1000=m
CONFIG_CAN_EMS_PCI=m
# CONFIG_CAN_F81601 is not set
CONFIG_CAN_KVASER_PCI=m
CONFIG_CAN_PEAK_PCI=m
CONFIG_CAN_PEAK_PCIEC=y
CONFIG_CAN_PLX_PCI=m
CONFIG_CAN_SJA1000_ISA=m
CONFIG_CAN_SJA1000_PLATFORM=m
CONFIG_CAN_SOFTING=m

#
# CAN SPI interfaces
#
# CONFIG_CAN_HI311X is not set
CONFIG_CAN_MCP251X=m
# CONFIG_CAN_MCP251XFD is not set
# end of CAN SPI interfaces

#
# CAN USB interfaces
#
CONFIG_CAN_8DEV_USB=m
CONFIG_CAN_EMS_USB=m
CONFIG_CAN_ESD_USB2=m
CONFIG_CAN_GS_USB=m
CONFIG_CAN_KVASER_USB=m
# CONFIG_CAN_MCBA_USB is not set
CONFIG_CAN_PEAK_USB=m
# CONFIG_CAN_UCAN is not set
# end of CAN USB interfaces

CONFIG_CAN_DEBUG_DEVICES=y
# end of CAN Device Drivers

CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=y
CONFIG_BT_HS=y
CONFIG_BT_LE=y
CONFIG_BT_6LOWPAN=m
CONFIG_BT_LEDS=y
CONFIG_BT_MSFTEXT=y
CONFIG_BT_AOSPEXT=y
CONFIG_BT_DEBUGFS=y
# CONFIG_BT_SELFTEST is not set

#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=m
CONFIG_BT_BCM=m
CONFIG_BT_RTL=m
CONFIG_BT_MTK=m
CONFIG_BT_HCIBTUSB=m
# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
CONFIG_BT_HCIBTUSB_BCM=y
CONFIG_BT_HCIBTUSB_MTK=y
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_AG6XX=y
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
CONFIG_BT_MTKSDIO=m
CONFIG_BT_HCIBTUSB_RTLBTUSB=m
CONFIG_BT_VIRTIO=m
# end of Bluetooth device drivers

CONFIG_AF_RXRPC=m
# CONFIG_AF_RXRPC_IPV6 is not set
# CONFIG_AF_RXRPC_INJECT_LOSS is not set
# CONFIG_AF_RXRPC_DEBUG is not set
# CONFIG_RXKAD is not set
# CONFIG_AF_KCM is not set
CONFIG_STREAM_PARSER=y
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_SPY=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_CFG80211_WEXT_EXPORT=y
CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
CONFIG_LIB80211_CRYPT_TKIP=m
# CONFIG_LIB80211_DEBUG is not set
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
# CONFIG_MAC80211_MESH is not set
CONFIG_MAC80211_LEDS=y
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_MESSAGE_TRACING is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
# CONFIG_WIMAX is not set
CONFIG_RFKILL=y
CONFIG_RFKILL_LEDS=y
# CONFIG_RFKILL_INPUT is not set
# CONFIG_RFKILL_GPIO is not set
CONFIG_RFKILL_RK=y
CONFIG_NET_9P=m
CONFIG_NET_9P_VIRTIO=m
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
CONFIG_CEPH_LIB=m
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
# CONFIG_NFC is not set
# CONFIG_PSAMPLE is not set
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
CONFIG_FAILOVER=m
CONFIG_ETHTOOL_NETLINK=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_SHORTCUT_FE=y

#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIEAER is not set
CONFIG_PCIEASPM=y
# CONFIG_PCIEASPM_DEFAULT is not set
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEASPM_PERFORMANCE=y
# CONFIG_PCIEASPM_EXT is not set
CONFIG_PCIE_PME=y
CONFIG_PCIE_PTM=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_STUB is not set
CONFIG_PCI_ATS=y
CONFIG_PCI_ECAM=y
# CONFIG_PCI_IOV is not set
CONFIG_PCI_PRI=y
CONFIG_PCI_PASID=y
CONFIG_PCI_LABEL=y
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
# CONFIG_HOTPLUG_PCI is not set

#
# PCI controller drivers
#
# CONFIG_PCI_FTPCI100 is not set
# CONFIG_PCI_HOST_GENERIC is not set
# CONFIG_PCIE_XILINX is not set
# CONFIG_PCI_XGENE is not set
# CONFIG_PCIE_ALTERA is not set
# CONFIG_PCI_HOST_THUNDER_PEM is not set
# CONFIG_PCI_HOST_THUNDER_ECAM is not set
CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_HOST=y
# CONFIG_ROCKCHIP_PCIE_DMA_OBJ is not set
# CONFIG_PCIE_HISI_ERR is not set

#
# DesignWare PCI Core Support
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
CONFIG_PCIE_DW_ROCKCHIP=y
# CONFIG_PCIE_RK_THREADED_INIT is not set
# CONFIG_PCIE_DW_DMATEST is not set
# CONFIG_PCIE_DW_ROCKCHIP_EP is not set
# CONFIG_PCI_HISI is not set
# CONFIG_PCIE_KIRIN is not set
# CONFIG_PCI_MESON is not set
# CONFIG_PCIE_AL is not set
# end of DesignWare PCI Core Support

#
# Mobiveil PCIe Core Support
#
# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set
# end of Mobiveil PCIe Core Support

#
# Cadence PCIe controllers support
#
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCI_J721E_HOST is not set
# end of Cadence PCIe controllers support
# end of PCI controller drivers

#
# PCI Endpoint
#
# CONFIG_PCI_ENDPOINT is not set
# end of PCI Endpoint

#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set
# end of PCI switch controller drivers

# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
CONFIG_FW_LOADER_COMPRESS=y
# CONFIG_FW_LOADER_COMPRESS_XZ is not set
# CONFIG_FW_LOADER_COMPRESS_ZSTD is not set
CONFIG_FW_CACHE=y
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
CONFIG_DEBUG_DEVRES=y
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SCCB=m
CONFIG_MALI_BASE_MODULES=y
CONFIG_DMA_SHARED_BUFFER_TEST_EXPORTER=y
CONFIG_MALI_MEMORY_GROUP_MANAGER=y
CONFIG_MALI_PROTECTED_MEMORY_ALLOCATOR=y
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
# CONFIG_BRCMSTB_GISB_ARB is not set
# CONFIG_MOXTET is not set
# CONFIG_SIMPLE_PM_BUS is not set
# CONFIG_VEXPRESS_CONFIG is not set
CONFIG_MHI_BUS=m
# CONFIG_MHI_BUS_DEBUG is not set
# CONFIG_MHI_BUS_PCI_GENERIC is not set
# CONFIG_MHI_BUS_EP is not set
# end of Bus devices

CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
CONFIG_GNSS=m
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_OF_PARTS=y
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
CONFIG_MTD_NAND_CORE=y
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
CONFIG_MTD_SPI_NAND=y

#
# ECC engine support
#
CONFIG_MTD_NAND_BBT_USING_FLASH=y
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
# CONFIG_MTD_SPI_NOR_MISC is not set
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
# CONFIG_MTD_UBI_BLOCK is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_DTC_SYMBOLS is not set
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_NET=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_NULL_BLK is not set
CONFIG_CDROM=m
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
CONFIG_ZRAM=y
CONFIG_ZRAM_WRITEBACK=y
CONFIG_ZRAM_MEMORY_TRACKING=y
# CONFIG_BLK_DEV_UMEM is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=128
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
CONFIG_BLK_DEV_DRBD=m
# CONFIG_DRBD_FAULT_INJECTION is not set
CONFIG_BLK_DEV_NBD=m
# CONFIG_BLK_DEV_SKD is not set
# CONFIG_BLK_DEV_SX8 is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_VIRTIO_BLK=m
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_RSXX is not set

#
# NVME Support
#
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
# CONFIG_NVME_MULTIPATH is not set
# CONFIG_NVME_HWMON is not set
# CONFIG_NVME_FC is not set
# CONFIG_NVME_TCP is not set
# CONFIG_NVME_TARGET is not set
# end of NVME Support

#
# Misc devices
#

#
# RK628 misc driver
#
# CONFIG_RK628_MISC is not set
# end of RK628 misc driver

CONFIG_RK803=m
CONFIG_PCIE_FUNC_RKEP=m
# CONFIG_LT7911D_FB_NOTIFIER is not set
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
# CONFIG_TIFM_CORE is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_XILINX_SDFEC is not set
CONFIG_MISC_RTSX=m
# CONFIG_UID_SYS_STATS is not set
# CONFIG_PVPANIC is not set
# CONFIG_HISI_HIKEY_USB is not set
CONFIG_ROCKPI_MCU=y
# CONFIG_C2PORT is not set

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
CONFIG_EEPROM_93CX6=m
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

# CONFIG_CB710_CORE is not set

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline

# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_MISC_ALCOR_PCI is not set
# CONFIG_MISC_RTSX_PCI is not set
CONFIG_MISC_RTSX_USB=m
# CONFIG_HABANA_AI is not set
# CONFIG_UACCE is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
CONFIG_RAID_ATTRS=m
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=m
# CONFIG_CHR_DEV_ST is not set
CONFIG_BLK_DEV_SR=m
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
CONFIG_SCSI_SCAN_ASYNC=y

#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=m
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=m
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_ISCSI_BOOT_SYSFS=m
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
CONFIG_SCSI_BNX2_ISCSI=m
CONFIG_BE2ISCSI=m
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
CONFIG_MEGARAID_NEWGEN=y
CONFIG_MEGARAID_MM=m
CONFIG_MEGARAID_MAILBOX=m
CONFIG_MEGARAID_LEGACY=m
CONFIG_MEGARAID_SAS=m
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_FDOMAIN_PCI is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
CONFIG_SCSI_VIRTIO=m
# CONFIG_SCSI_DH is not set
# end of SCSI device support

CONFIG_HAVE_PATA_PLATFORM=y
CONFIG_ATA=y
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_AHCI_CEVA=m
CONFIG_AHCI_QORIQ=m
CONFIG_SATA_INIC162X=m
CONFIG_SATA_ACARD_AHCI=m
CONFIG_SATA_SIL24=m
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#
CONFIG_PDC_ADMA=m
CONFIG_SATA_QSTOR=m
CONFIG_SATA_SX4=m
CONFIG_ATA_BMDMA=y

#
# SATA SFF controllers with BMDMA
#
# CONFIG_ATA_PIIX is not set
CONFIG_SATA_DWC=y
# CONFIG_SATA_DWC_OLD_DMA is not set
# CONFIG_SATA_DWC_DEBUG is not set
CONFIG_SATA_MV=m
# CONFIG_SATA_NV is not set
CONFIG_SATA_PROMISE=m
CONFIG_SATA_SIL=m
CONFIG_SATA_SIS=m
# CONFIG_SATA_SVW is not set
CONFIG_SATA_ULI=m
CONFIG_SATA_VIA=m
# CONFIG_SATA_VITESSE is not set

#
# PATA SFF controllers with BMDMA
#
# CONFIG_PATA_ALI is not set
# CONFIG_PATA_AMD is not set
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_ATP867X is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CYPRESS is not set
# CONFIG_PATA_EFAR is not set
# CONFIG_PATA_HPT366 is not set
# CONFIG_PATA_HPT37X is not set
# CONFIG_PATA_HPT3X2N is not set
# CONFIG_PATA_HPT3X3 is not set
# CONFIG_PATA_IT8213 is not set
# CONFIG_PATA_IT821X is not set
# CONFIG_PATA_JMICRON is not set
# CONFIG_PATA_MARVELL is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_OPTIDMA is not set
# CONFIG_PATA_PDC2027X is not set
# CONFIG_PATA_PDC_OLD is not set
# CONFIG_PATA_RADISYS is not set
# CONFIG_PATA_RDC is not set
# CONFIG_PATA_SCH is not set
# CONFIG_PATA_SERVERWORKS is not set
# CONFIG_PATA_SIL680 is not set
CONFIG_PATA_SIS=m
# CONFIG_PATA_TOSHIBA is not set
# CONFIG_PATA_TRIFLEX is not set
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set

#
# PIO-only SFF controllers
#
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_PLATFORM is not set
# CONFIG_PATA_RZ1000 is not set

#
# Generic fallback / legacy drivers
#
CONFIG_PATA_ACPI=y
# CONFIG_ATA_GENERIC is not set
# CONFIG_PATA_LEGACY is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
# CONFIG_MD_CLUSTER is not set
CONFIG_BCACHE=m
# CONFIG_BCACHE_DEBUG is not set
# CONFIG_BCACHE_CLOSURES_DEBUG is not set
# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=m
# CONFIG_DM_DEBUG is not set
CONFIG_DM_BUFIO=m
# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
# CONFIG_DM_UNSTRIPED is not set
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
CONFIG_DM_CACHE=m
CONFIG_DM_CACHE_SMQ=m
CONFIG_DM_WRITECACHE=m
# CONFIG_DM_EBS is not set
CONFIG_DM_ERA=m
# CONFIG_DM_CLONE is not set
CONFIG_DM_MIRROR=m
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
# CONFIG_DM_MULTIPATH_HST is not set
CONFIG_DM_DELAY=m
# CONFIG_DM_DUST is not set
# CONFIG_DM_UEVENT is not set
CONFIG_DM_FLAKEY=m
CONFIG_DM_VERITY=m
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
# CONFIG_DM_VERITY_FEC is not set
CONFIG_DM_SWITCH=m
CONFIG_DM_LOG_WRITES=m
# CONFIG_DM_INTEGRITY is not set
# CONFIG_DM_BOW is not set
CONFIG_DM_USER=m
# CONFIG_TARGET_CORE is not set
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
# end of IEEE 1394 (FireWire) support

CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_WIREGUARD=m
# CONFIG_WIREGUARD_DEBUG is not set
CONFIG_EQUALIZER=m
# CONFIG_NET_FC is not set
CONFIG_IFB=m
CONFIG_NET_TEAM=m
CONFIG_NET_TEAM_MODE_BROADCAST=m
CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
CONFIG_NET_TEAM_MODE_RANDOM=m
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
CONFIG_NET_TEAM_MODE_LOADBALANCE=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=m
CONFIG_IPVTAP=m
CONFIG_VXLAN=m
CONFIG_GENEVE=m
CONFIG_BAREUDP=m
CONFIG_GTP=m
CONFIG_MACSEC=m
CONFIG_NETCONSOLE=m
# CONFIG_NETCONSOLE_DYNAMIC is not set
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=m
CONFIG_TAP=m
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_NLMON=m
CONFIG_NET_VRF=m
CONFIG_VSOCKMON=m
CONFIG_ARCNET=m
# CONFIG_ARCNET_1201 is not set
# CONFIG_ARCNET_1051 is not set
# CONFIG_ARCNET_RAW is not set
# CONFIG_ARCNET_CAP is not set
# CONFIG_ARCNET_COM90xx is not set
# CONFIG_ARCNET_COM90xxIO is not set
# CONFIG_ARCNET_RIM_I is not set
# CONFIG_ARCNET_COM20020 is not set
CONFIG_ATM_DRIVERS=y
# CONFIG_ATM_DUMMY is not set
# CONFIG_ATM_TCP is not set
# CONFIG_ATM_LANAI is not set
# CONFIG_ATM_ENI is not set
# CONFIG_ATM_NICSTAR is not set
# CONFIG_ATM_IDT77252 is not set
# CONFIG_ATM_IA is not set
# CONFIG_ATM_FORE200E is not set
# CONFIG_ATM_HE is not set
# CONFIG_ATM_SOLOS is not set

#
# Distributed Switch Architecture drivers
#
CONFIG_B53=m
# CONFIG_B53_SPI_DRIVER is not set
# CONFIG_B53_MDIO_DRIVER is not set
# CONFIG_B53_MMAP_DRIVER is not set
# CONFIG_B53_SRAB_DRIVER is not set
# CONFIG_B53_SERDES is not set
CONFIG_NET_DSA_BCM_SF2=m
CONFIG_NET_DSA_LOOP=m
CONFIG_NET_DSA_LANTIQ_GSWIP=m
CONFIG_NET_DSA_MT7530=m
CONFIG_NET_DSA_MV88E6060=m
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
# CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C is not set
# CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI is not set
CONFIG_NET_DSA_MICROCHIP_KSZ8795=m
# CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI is not set
CONFIG_NET_DSA_MV88E6XXX=m
CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
# CONFIG_NET_DSA_MV88E6XXX_PTP is not set
CONFIG_NET_DSA_AR9331=m
CONFIG_NET_DSA_SJA1105=m
# CONFIG_NET_DSA_SJA1105_PTP is not set
CONFIG_NET_DSA_QCA8K=m
CONFIG_NET_DSA_REALTEK_SMI=m
CONFIG_NET_DSA_SMSC_LAN9303=m
CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
CONFIG_NET_DSA_VITESSE_VSC73XX=m
CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
# end of Distributed Switch Architecture drivers

CONFIG_ETHERNET=y
CONFIG_MDIO=m
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_ALTERA_TSE is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_ATHEROS is not set
# CONFIG_NET_VENDOR_AURORA is not set
CONFIG_NET_VENDOR_BROADCOM=y
CONFIG_B44=m
CONFIG_B44_PCI_AUTOSELECT=y
CONFIG_B44_PCICORE_AUTOSELECT=y
CONFIG_B44_PCI=y
# CONFIG_BCMGENET is not set
CONFIG_BNX2=m
CONFIG_CNIC=m
CONFIG_TIGON3=m
# CONFIG_TIGON3_HWMON is not set
CONFIG_BNX2X=m
# CONFIG_SYSTEMPORT is not set
CONFIG_BNXT=m
CONFIG_BNXT_FLOWER_OFFLOAD=y
CONFIG_BNXT_HWMON=y
CONFIG_NET_VENDOR_BROCADE=y
CONFIG_BNA=m
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_DNET is not set
# CONFIG_NET_VENDOR_DEC is not set
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
CONFIG_NET_VENDOR_HISILICON=y
CONFIG_HIX5HD2_GMAC=m
CONFIG_HISI_FEMAC=m
CONFIG_HIP04_ETH=m
# CONFIG_HI13X1_GMAC is not set
CONFIG_HNS_MDIO=m
CONFIG_HNS=m
CONFIG_HNS_DSAF=m
CONFIG_HNS_ENET=m
CONFIG_HNS3=m
CONFIG_HNS3_HCLGE=m
CONFIG_HNS3_HCLGEVF=m
CONFIG_HNS3_ENET=m
CONFIG_NET_VENDOR_HUAWEI=y
CONFIG_HINIC=m
CONFIG_NET_VENDOR_I825XX=y
CONFIG_NET_VENDOR_INTEL=y
# CONFIG_E100 is not set
CONFIG_E1000=m
CONFIG_E1000E=m
CONFIG_IGB=m
# CONFIG_IGB_HWMON is not set
CONFIG_IGBVF=m
CONFIG_IXGB=m
CONFIG_IXGBE=m
CONFIG_IXGBE_HWMON=y
CONFIG_IXGBE_IPSEC=y
CONFIG_IXGBEVF=m
CONFIG_IXGBEVF_IPSEC=y
CONFIG_I40E=m
CONFIG_IAVF=m
CONFIG_I40EVF=m
CONFIG_ICE=m
CONFIG_FM10K=m
CONFIG_IGC=m
# CONFIG_JME is not set
# CONFIG_NET_VENDOR_MARVELL is not set
CONFIG_NET_VENDOR_MELLANOX=y
CONFIG_MLX4_EN=m
CONFIG_MLX4_CORE=m
CONFIG_MLX4_DEBUG=y
CONFIG_MLX4_CORE_GEN2=y
CONFIG_MLX5_CORE=m
CONFIG_MLX5_ACCEL=y
CONFIG_MLX5_FPGA=y
CONFIG_MLX5_CORE_EN=y
CONFIG_MLX5_EN_ARFS=y
CONFIG_MLX5_EN_RXNFC=y
CONFIG_MLX5_MPFS=y
CONFIG_MLX5_ESWITCH=y
CONFIG_MLX5_CLS_ACT=y
CONFIG_MLX5_CORE_IPOIB=y
CONFIG_MLX5_FPGA_IPSEC=y
CONFIG_MLX5_IPSEC=y
CONFIG_MLX5_EN_IPSEC=y
CONFIG_MLX5_SW_STEERING=y
CONFIG_MLXSW_CORE=m
CONFIG_MLXSW_CORE_HWMON=y
CONFIG_MLXSW_CORE_THERMAL=y
CONFIG_MLXSW_PCI=m
CONFIG_MLXSW_I2C=m
CONFIG_MLXSW_SWITCHIB=m
CONFIG_MLXSW_SWITCHX2=m
CONFIG_MLXSW_SPECTRUM=m
CONFIG_MLXSW_MINIMAL=m
CONFIG_MLXFW=m
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_FEALNX is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETERION is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCOM_EMAC is not set
CONFIG_SFE_SUPPORT_IPV6=y
CONFIG_SFE_ECM=y
CONFIG_FAST_CLASSIFIER=y
# CONFIG_RMNET is not set
# CONFIG_NET_VENDOR_RDC is not set
CONFIG_NET_VENDOR_REALTEK=y
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
# CONFIG_R8126 is not set
CONFIG_R8168=m
# CONFIG_R8168_SOC_LAN is not set
# CONFIG_R8168_FIBER_SUPPORT is not set
# CONFIG_R8168_REALWOW_SUPPORT is not set
# CONFIG_R8168_DASH_SUPPORT is not set
# CONFIG_R8168_DOWN_SPEED_100 is not set
CONFIG_R8168_ASPM=y
CONFIG_R8168_DYNAMIC_ASPM=y
CONFIG_R8168_WOL_SUPPORT=y
CONFIG_R8168_S5WOL=y
# CONFIG_R8168_S5_KEEP_CURR_MAC is not set
CONFIG_R8168_EEE=y
# CONFIG_R8168_S0_MAGIC_PACKET is not set
# CONFIG_R8168_USE_FIRMWARE_FILE is not set
# CONFIG_R8168_CTAP_SHORT_OFF is not set
# CONFIG_R8168_MULTIPLE_TX_QUEUE is not set
# CONFIG_R8168_RSS_SUPPORT is not set
CONFIG_R8168_GIGA_LITE=y
# CONFIG_R8169 is not set
CONFIG_R8125=m
# CONFIG_R8125_SOC_LAN is not set
# CONFIG_R8125_REALWOW_SUPPORT is not set
# CONFIG_R8125_DASH_SUPPORT is not set
# CONFIG_R8125_DOWN_SPEED_100 is not set
CONFIG_R8125_ASPM=y
CONFIG_R8125_WOL_SUPPORT=y
CONFIG_R8125_S5WOL=y
# CONFIG_R8125_S5_KEEP_CURR_MAC is not set
CONFIG_R8125_EEE=y
# CONFIG_R8125_S0_MAGIC_PACKET is not set
CONFIG_R8125_TX_NO_CLOSE=y
CONFIG_R8125_MULTI_MSIX_VECTOR=y
CONFIG_R8125_MULTIPLE_TX_QUEUE=y
CONFIG_R8125_RSS_SUPPORT=y
# CONFIG_R8125_PTP_SUPPORT is not set
CONFIG_R8125_FIBER_SUPPORT=y
CONFIG_R8125_USE_FIRMWARE_FILE=y
# CONFIG_R8125_DOUBLE_VLAN is not set
# CONFIG_R8125_PAGE_REUSE is not set
CONFIG_R8125_GIGA_LITE=y
# CONFIG_REALTEK_PGTOOL is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
# CONFIG_STMMAC_SELFTESTS is not set
CONFIG_STMMAC_UIO=m
CONFIG_STMMAC_ETHTOOL=y
CONFIG_STMMAC_FULL=y
CONFIG_STMMAC_PLATFORM=y
# CONFIG_DWMAC_DWC_QOS_ETH is not set
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_ROCKCHIP=y
CONFIG_DWMAC_ROCKCHIP_TOOL=y
# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_NET_SB1000 is not set
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
# CONFIG_LED_TRIGGER_PHY is not set
CONFIG_FIXED_PHY=y
# CONFIG_SFP is not set

#
# Switch configuration API + drivers
#
# CONFIG_SWCONFIG is not set
# CONFIG_RTL8306_PHY is not set
# CONFIG_RTL8366_SMI is not set

#
# MII PHY device drivers
#
# CONFIG_AMD_PHY is not set
# CONFIG_ADIN_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
# CONFIG_AX88796B_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM54140_PHY is not set
CONFIG_BCM7XXX_PHY=m
# CONFIG_BCM84881_PHY is not set
# CONFIG_BCM87XX_PHY is not set
CONFIG_BCM_NET_PHYLIB=m
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
CONFIG_ICPLUS_PHY=y
# CONFIG_JLSEMI_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
CONFIG_MARVELL_PHY=m
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MICREL_PHY is not set
CONFIG_MICROCHIP_PHY=m
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
# CONFIG_MOTORCOMM_PHY is not set
# CONFIG_NATIONAL_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
# CONFIG_AT803X_PHY is not set
# CONFIG_QSEMI_PHY is not set
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
# CONFIG_RK630_PHY is not set
CONFIG_SMSC_PHY=m
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
# CONFIG_DP83869_PHY is not set
CONFIG_VITESSE_PHY=m
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_OF_MDIO=y
CONFIG_MDIO_DEVRES=y
# CONFIG_MDIO_BITBANG is not set
CONFIG_MDIO_BCM_UNIMAC=m
CONFIG_MDIO_CAVIUM=m
# CONFIG_MDIO_HISI_FEMAC is not set
# CONFIG_MDIO_MVUSB is not set
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_OCTEON is not set
# CONFIG_MDIO_IPQ4019 is not set
# CONFIG_MDIO_IPQ8064 is not set
CONFIG_MDIO_THUNDER=m

#
# MDIO Multiplexers
#
# CONFIG_MDIO_BUS_MUX_GPIO is not set
# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
# CONFIG_MDIO_BUS_MUX_MMIOREG is not set

#
# PCS device drivers
#
CONFIG_PCS_XPCS=y
# end of PCS device drivers

CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
# CONFIG_PPP_FILTER is not set
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOATM=m
CONFIG_PPPOE=m
# CONFIG_PPTP is not set
CONFIG_PPPOL2TP=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
# CONFIG_SLIP is not set
CONFIG_SLHC=m
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_AX8817X=m
CONFIG_USB_NET_AX88179_178A=m
CONFIG_USB_NET_CDCETHER=m
CONFIG_USB_NET_CDC_EEM=m
CONFIG_USB_NET_CDC_NCM=m
CONFIG_USB_NET_HUAWEI_CDC_NCM=m
CONFIG_USB_NET_CDC_MBIM=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9700=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
CONFIG_USB_NET_CDC_SUBSET=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
# CONFIG_USB_ARMLINUX is not set
# CONFIG_USB_EPSON2888 is not set
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=m
CONFIG_USB_NET_CX82310_ETH=m
CONFIG_USB_NET_KALMIA=m
CONFIG_USB_NET_QMI_WWAN=m
CONFIG_USB_HSO=m
CONFIG_USB_NET_INT51X1=m
CONFIG_USB_IPHETH=m
CONFIG_USB_SIERRA_NET=m
CONFIG_USB_VL600=m
CONFIG_USB_NET_CH9200=m
CONFIG_USB_NET_AQC111=m
CONFIG_WLAN=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_AIC_WLAN_SUPPORT is not set
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
CONFIG_ATH_USER_REGD=y
# CONFIG_ATH_DEBUG is not set
CONFIG_ATH5K=m
# CONFIG_ATH5K_DEBUG is not set
# CONFIG_ATH5K_TRACER is not set
CONFIG_ATH5K_PCI=y
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=m
# CONFIG_ATH9K_PCI is not set
# CONFIG_ATH9K_AHB is not set
# CONFIG_ATH9K_DEBUGFS is not set
# CONFIG_ATH9K_DYNACK is not set
# CONFIG_ATH9K_WOW is not set
CONFIG_ATH9K_RFKILL=y
# CONFIG_ATH9K_CHANNEL_CONTEXT is not set
CONFIG_ATH9K_PCOEM=y
# CONFIG_ATH9K_HTC is not set
# CONFIG_ATH9K_HWRNG is not set
CONFIG_CARL9170=m
CONFIG_CARL9170_LEDS=y
CONFIG_CARL9170_WPC=y
# CONFIG_CARL9170_HWRNG is not set
CONFIG_ATH6KL=m
# CONFIG_ATH6KL_SDIO is not set
CONFIG_ATH6KL_USB=m
# CONFIG_ATH6KL_DEBUG is not set
# CONFIG_ATH6KL_TRACING is not set
CONFIG_AR5523=m
# CONFIG_WIL6210 is not set
CONFIG_ATH10K=m
CONFIG_ATH10K_CE=y
CONFIG_ATH10K_PCI=m
# CONFIG_ATH10K_AHB is not set
# CONFIG_ATH10K_SDIO is not set
CONFIG_ATH10K_USB=m
# CONFIG_ATH10K_DEBUG is not set
# CONFIG_ATH10K_DEBUGFS is not set
CONFIG_ATH10K_LEDS=y
# CONFIG_ATH10K_TRACING is not set
# CONFIG_ATH10K_THERMAL is not set
CONFIG_WCN36XX=m
# CONFIG_WCN36XX_DEBUGFS is not set
CONFIG_ATH11K=m
CONFIG_ATH11K_PCI=m
# CONFIG_ATH11K_DEBUG is not set
# CONFIG_ATH11K_TRACING is not set
CONFIG_ATH12K=m
# CONFIG_ATH12K_DEBUG is not set
# CONFIG_ATH12K_TRACING is not set
# CONFIG_WLAN_VENDOR_ATMEL is not set
CONFIG_WLAN_VENDOR_BROADCOM=y
CONFIG_B43=m
CONFIG_B43_BCMA=y
CONFIG_B43_SSB=y
CONFIG_B43_BUSES_BCMA_AND_SSB=y
# CONFIG_B43_BUSES_BCMA is not set
# CONFIG_B43_BUSES_SSB is not set
CONFIG_B43_PCI_AUTOSELECT=y
CONFIG_B43_PCICORE_AUTOSELECT=y
# CONFIG_B43_SDIO is not set
CONFIG_B43_BCMA_PIO=y
CONFIG_B43_PIO=y
CONFIG_B43_PHY_G=y
CONFIG_B43_PHY_N=y
CONFIG_B43_PHY_LP=y
CONFIG_B43_PHY_HT=y
CONFIG_B43_LEDS=y
CONFIG_B43_HWRNG=y
# CONFIG_B43_DEBUG is not set
CONFIG_B43LEGACY=m
CONFIG_B43LEGACY_PCI_AUTOSELECT=y
CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
CONFIG_B43LEGACY_LEDS=y
CONFIG_B43LEGACY_HWRNG=y
CONFIG_B43LEGACY_DEBUG=y
CONFIG_B43LEGACY_DMA=y
CONFIG_B43LEGACY_PIO=y
CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
# CONFIG_B43LEGACY_DMA_MODE is not set
# CONFIG_B43LEGACY_PIO_MODE is not set
CONFIG_BRCMUTIL=m
CONFIG_BRCMFMAC=m
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_PROTO_MSGBUF=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
CONFIG_BRCMFMAC_PCIE=y
# CONFIG_BRCMFMAC_BT_SHARED_SDIO is not set
CONFIG_BRCM_TRACING=y
# CONFIG_BRCMDBG is not set
# CONFIG_BRCMFMAC_PCIE_BARWIN_SZ is not set
# CONFIG_WLAN_VENDOR_CISCO is not set
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_IPW2100=m
# CONFIG_IPW2100_MONITOR is not set
# CONFIG_IPW2100_DEBUG is not set
CONFIG_IPW2200=m
# CONFIG_IPW2200_MONITOR is not set
# CONFIG_IPW2200_QOS is not set
# CONFIG_IPW2200_DEBUG is not set
CONFIG_LIBIPW=m
# CONFIG_LIBIPW_DEBUG is not set
CONFIG_IWLEGACY=m
CONFIG_IWL4965=m
CONFIG_IWL3945=m

#
# iwl3945 / iwl4965 Debugging Options
#
# CONFIG_IWLEGACY_DEBUG is not set
# end of iwl3945 / iwl4965 Debugging Options

CONFIG_IWLWIFI=m
CONFIG_IWLWIFI_LEDS=y
CONFIG_IWLDVM=m
CONFIG_IWLMVM=m
CONFIG_IWLWIFI_OPMODE_MODULAR=y

#
# Debugging Options
#
# CONFIG_IWLWIFI_DEBUG is not set
# CONFIG_IWLWIFI_DEVICE_TRACING is not set
# end of Debugging Options

# CONFIG_WLAN_VENDOR_INTERSIL is not set
# CONFIG_WLAN_VENDOR_MARVELL is not set
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=m
CONFIG_MT76_CORE=m
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=m
CONFIG_MT76_SDIO=m
CONFIG_MT76x02_LIB=m
CONFIG_MT76x02_USB=m
CONFIG_MT76_CONNAC_LIB=m
CONFIG_MT76x0_COMMON=m
CONFIG_MT76x0U=m
CONFIG_MT76x0E=m
CONFIG_MT76x2_COMMON=m
CONFIG_MT76x2E=m
CONFIG_MT76x2U=m
CONFIG_MT7603E=m
CONFIG_MT7615_COMMON=m
CONFIG_MT7615E=m
CONFIG_MT7663_USB_SDIO_COMMON=m
CONFIG_MT7663U=m
CONFIG_MT7663S=m
CONFIG_MT7915E=m
CONFIG_MT7921_COMMON=m
CONFIG_MT7921E=m
CONFIG_MT7921S=m
CONFIG_MT7921U=m
CONFIG_MT7996E=m
CONFIG_WLAN_VENDOR_MICROCHIP=y
CONFIG_WILC1000=m
CONFIG_WILC1000_SDIO=m
CONFIG_WILC1000_SPI=m
CONFIG_WILC1000_HW_OOB_INTR=y
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=m
CONFIG_RT2400PCI=m
CONFIG_RT2500PCI=m
CONFIG_RT61PCI=m
CONFIG_RT2800PCI=m
CONFIG_RT2800PCI_RT33XX=y
CONFIG_RT2800PCI_RT35XX=y
CONFIG_RT2800PCI_RT53XX=y
CONFIG_RT2800PCI_RT3290=y
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
CONFIG_RT2800USB_RT33XX=y
CONFIG_RT2800USB_RT35XX=y
CONFIG_RT2800USB_RT3573=y
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
# CONFIG_RT2800USB_UNKNOWN is not set
CONFIG_RT2800_LIB=m
CONFIG_RT2800_LIB_MMIO=m
CONFIG_RT2X00_LIB_MMIO=m
CONFIG_RT2X00_LIB_PCI=m
CONFIG_RT2X00_LIB_USB=m
CONFIG_RT2X00_LIB=m
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
# CONFIG_RT2X00_DEBUG is not set
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_RTL8180=m
CONFIG_RTL8187=m
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=m
CONFIG_RTL8192CE=m
CONFIG_RTL8192SE=m
CONFIG_RTL8192DE=m
CONFIG_RTL8723AE=m
CONFIG_RTL8723BE=m
CONFIG_RTL8188EE=m
CONFIG_RTL8192EE=m
CONFIG_RTL8821AE=m
CONFIG_RTL8192CU=m
CONFIG_RTLWIFI=m
CONFIG_RTLWIFI_PCI=m
CONFIG_RTLWIFI_USB=m
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8723_COMMON=m
CONFIG_RTLBTCOEXIST=m
CONFIG_RTL8XXXU=m
# CONFIG_RTL8XXXU_UNTESTED is not set
CONFIG_RTW88=m
CONFIG_RTW88_CORE=m
CONFIG_RTW88_PCI=m
CONFIG_RTW88_SDIO=m
CONFIG_RTW88_USB=m
CONFIG_RTW88_8822B=m
CONFIG_RTW88_8822C=m
CONFIG_RTW88_8723D=m
CONFIG_RTW88_8821C=m
CONFIG_RTW88_8822BE=m
CONFIG_RTW88_8822BS=m
CONFIG_RTW88_8822BU=m
CONFIG_RTW88_8822CE=m
CONFIG_RTW88_8822CS=m
CONFIG_RTW88_8822CU=m
CONFIG_RTW88_8723DE=m
CONFIG_RTW88_8723DS=m
CONFIG_RTW88_8723DU=m
CONFIG_RTW88_8821CE=m
CONFIG_RTW88_8821CS=m
CONFIG_RTW88_8821CU=m
# CONFIG_RTW88_DEBUG is not set
# CONFIG_RTW88_DEBUGFS is not set
CONFIG_RTW89=m
CONFIG_RTW89_CORE=m
CONFIG_RTW89_PCI=m
CONFIG_RTW89_8851B=m
CONFIG_RTW89_8852A=m
CONFIG_RTW89_8852B=m
CONFIG_RTW89_8852C=m
CONFIG_RTW89_8851BE=m
CONFIG_RTW89_8852AE=m
CONFIG_RTW89_8852BE=m
CONFIG_RTW89_8852CE=m
# CONFIG_RTW89_DEBUGMSG is not set
# CONFIG_RTW89_DEBUGFS is not set
# CONFIG_WLAN_VENDOR_RSI is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
# CONFIG_WLAN_VENDOR_ZYDAS is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
CONFIG_WL_ROCKCHIP=m
CONFIG_WIFI_BUILD_MODULE=y
# CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP is not set
# CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR is not set
CONFIG_BCMDHD=y
CONFIG_AP6XXX=m
# CONFIG_BCMDHD_SDIO is not set
CONFIG_BCMDHD_PCIE=y
CONFIG_BCMDHD_FW_PATH="/lib/firmware/ap6275p/fw_bcmdhd.bin"
CONFIG_BCMDHD_NVRAM_PATH="/lib/firmware/ap6275p/nvram.txt"
# CONFIG_BCMDHD_STATIC_IF is not set
# CONFIG_CYW_BCMDHD is not set
# CONFIG_INFINEON_DHD is not set
CONFIG_USB_NET_RNDIS_WLAN=m
# CONFIG_MAC80211_HWSIM is not set
CONFIG_VIRT_WIFI=m

#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
CONFIG_IEEE802154_AT86RF230=m
# CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set
CONFIG_IEEE802154_MRF24J40=m
CONFIG_IEEE802154_CC2520=m
CONFIG_IEEE802154_ATUSB=m
CONFIG_IEEE802154_ADF7242=m
CONFIG_IEEE802154_CA8210=m
# CONFIG_IEEE802154_CA8210_DEBUGFS is not set
CONFIG_IEEE802154_MCR20A=m
CONFIG_IEEE802154_HWSIM=m
# CONFIG_VMXNET3 is not set
# CONFIG_FUJITSU_ES is not set
CONFIG_LTE=y
CONFIG_LTE_RM310=y
CONFIG_LTE_EM05=y
CONFIG_NETDEVSIM=m
CONFIG_NET_FAILOVER=m
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
CONFIG_INPUT_MATRIXKMAP=m

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ADC=y
CONFIG_KEYBOARD_ADP5588=m
CONFIG_KEYBOARD_ADP5589=m
CONFIG_KEYBOARD_ATKBD=m
CONFIG_KEYBOARD_QT1050=m
CONFIG_KEYBOARD_QT1070=m
CONFIG_KEYBOARD_QT2160=m
CONFIG_KEYBOARD_DLINK_DIR685=m
CONFIG_KEYBOARD_LKKBD=m
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_GPIO_BUTTON_HOTPLUG is not set
CONFIG_KEYBOARD_GPIO_POLLED=y
CONFIG_KEYBOARD_TCA6416=m
CONFIG_KEYBOARD_TCA8418=m
CONFIG_KEYBOARD_MATRIX=m
CONFIG_KEYBOARD_LM8323=m
CONFIG_KEYBOARD_LM8333=m
CONFIG_KEYBOARD_MAX7359=m
CONFIG_KEYBOARD_MCS=m
CONFIG_KEYBOARD_MPR121=m
CONFIG_KEYBOARD_NEWTON=m
CONFIG_KEYBOARD_OPENCORES=m
CONFIG_KEYBOARD_SAMSUNG=m
CONFIG_KEYBOARD_STOWAWAY=m
CONFIG_KEYBOARD_SUNKBD=m
CONFIG_KEYBOARD_OMAP4=m
CONFIG_KEYBOARD_TM2_TOUCHKEY=m
CONFIG_KEYBOARD_XTKBD=m
CONFIG_KEYBOARD_CAP11XX=m
CONFIG_KEYBOARD_BCM=m
CONFIG_INPUT_MOUSE=y
# CONFIG_MOUSE_PS2 is not set
# CONFIG_MOUSE_SERIAL is not set
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=m
CONFIG_MOUSE_ELAN_I2C=m
CONFIG_MOUSE_ELAN_I2C_I2C=y
# CONFIG_MOUSE_ELAN_I2C_SMBUS is not set
# CONFIG_MOUSE_VSXXXAA is not set
CONFIG_MOUSE_GPIO=m
CONFIG_MOUSE_SYNAPTICS_I2C=m
CONFIG_MOUSE_SYNAPTICS_USB=m
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_ANALOG=m
CONFIG_JOYSTICK_A3D=m
CONFIG_JOYSTICK_ADC=m
CONFIG_JOYSTICK_ADI=m
CONFIG_JOYSTICK_COBRA=m
CONFIG_JOYSTICK_GF2K=m
CONFIG_JOYSTICK_GRIP=m
CONFIG_JOYSTICK_GRIP_MP=m
CONFIG_JOYSTICK_GUILLEMOT=m
CONFIG_JOYSTICK_INTERACT=m
CONFIG_JOYSTICK_SIDEWINDER=m
CONFIG_JOYSTICK_TMDC=m
CONFIG_JOYSTICK_IFORCE=m
CONFIG_JOYSTICK_IFORCE_USB=m
CONFIG_JOYSTICK_IFORCE_232=m
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
CONFIG_JOYSTICK_STINGER=m
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
CONFIG_JOYSTICK_AS5011=m
CONFIG_JOYSTICK_JOYDUMP=m
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_JOYSTICK_PSXPAD_SPI=m
CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
CONFIG_JOYSTICK_PXRC=m
CONFIG_JOYSTICK_FSIA6B=m
CONFIG_INPUT_TABLET=y
CONFIG_TABLET_USB_ACECAD=m
CONFIG_TABLET_USB_AIPTEK=m
CONFIG_TABLET_USB_GTCO=m
CONFIG_TABLET_USB_HANWANG=m
CONFIG_TABLET_USB_KBTAB=m
CONFIG_TABLET_USB_PEGASUS=m
CONFIG_TABLET_SERIAL_WACOM4=m
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_PROPERTIES=y
CONFIG_TOUCHSCREEN_ADS7846=m
CONFIG_TOUCHSCREEN_AD7877=m
CONFIG_TOUCHSCREEN_AD7879=m
CONFIG_TOUCHSCREEN_AD7879_I2C=m
CONFIG_TOUCHSCREEN_AD7879_SPI=m
CONFIG_TOUCHSCREEN_ADC=m
CONFIG_TOUCHSCREEN_AR1021_I2C=m
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set
CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
CONFIG_TOUCHSCREEN_BU21013=m
CONFIG_TOUCHSCREEN_BU21029=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
CONFIG_TOUCHSCREEN_CY8CTMA140=m
CONFIG_TOUCHSCREEN_CY8CTMG110=m
CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
CONFIG_TOUCHSCREEN_DYNAPRO=m
CONFIG_TOUCHSCREEN_HAMPSHIRE=m
CONFIG_TOUCHSCREEN_EETI=m
CONFIG_TOUCHSCREEN_EGALAX=m
CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
CONFIG_TOUCHSCREEN_EXC3000=m
CONFIG_TOUCHSCREEN_FTS=y
CONFIG_TOUCHSCREEN_FUJITSU=m
CONFIG_TOUCHSCREEN_GOODIX=m
CONFIG_TOUCHSCREEN_GSL3673=y
CONFIG_TOUCHSCREEN_GSL3673_800X1280=m
CONFIG_TOUCHSCREEN_GSLX680_PAD=m
CONFIG_TOUCHSCREEN_GT1X=y
CONFIG_TOUCHSCREEN_GT9XX=m
CONFIG_TOUCHSCREEN_HIDEEP=m
CONFIG_TOUCHSCREEN_ILI210X=m
CONFIG_TOUCHSCREEN_S6SY761=m
CONFIG_TOUCHSCREEN_GUNZE=m
CONFIG_TOUCHSCREEN_EKTF2127=m
CONFIG_TOUCHSCREEN_ELAN=y
CONFIG_TOUCHSCREEN_ELAN5515=m
CONFIG_TOUCHSCREEN_ELO=m
CONFIG_TOUCHSCREEN_WACOM_W8001=m
CONFIG_TOUCHSCREEN_WACOM_I2C=m
CONFIG_TOUCHSCREEN_MAX11801=m
CONFIG_TOUCHSCREEN_MCS5000=m
CONFIG_TOUCHSCREEN_MMS114=m
CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
CONFIG_TOUCHSCREEN_MTOUCH=m
CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
CONFIG_TOUCHSCREEN_INEXIO=m
CONFIG_TOUCHSCREEN_MK712=m
CONFIG_TOUCHSCREEN_PENMOUNT=m
CONFIG_TOUCHSCREEN_EDT_FT5X06=m
CONFIG_TOUCHSCREEN_RASPITS_FT5426=m
CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
CONFIG_TOUCHSCREEN_TOUCHWIN=m
CONFIG_TOUCHSCREEN_PIXCIR=m
CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
CONFIG_TOUCHSCREEN_WM97XX=m
CONFIG_TOUCHSCREEN_WM9705=y
CONFIG_TOUCHSCREEN_WM9712=y
CONFIG_TOUCHSCREEN_WM9713=y
CONFIG_TOUCHSCREEN_USB_COMPOSITE=y
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
CONFIG_TOUCHSCREEN_TOUCHIT213=m
CONFIG_TOUCHSCREEN_TSC_SERIO=m
CONFIG_TOUCHSCREEN_TSC200X_CORE=m
CONFIG_TOUCHSCREEN_TSC2004=m
CONFIG_TOUCHSCREEN_TSC2005=m
CONFIG_TOUCHSCREEN_TSC2007=m
# CONFIG_TOUCHSCREEN_TSC2007_IIO is not set
CONFIG_TOUCHSCREEN_RM_TS=m
CONFIG_TOUCHSCREEN_SILEAD=m
CONFIG_TOUCHSCREEN_SIS_I2C=m
CONFIG_TOUCHSCREEN_ST1232=m
CONFIG_TOUCHSCREEN_STMFTS=m
CONFIG_TOUCHSCREEN_SUR40=m
CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
CONFIG_TOUCHSCREEN_SX8654=m
CONFIG_TOUCHSCREEN_TPS6507X=m
CONFIG_TOUCHSCREEN_ZET6223=m
CONFIG_TOUCHSCREEN_ZFORCE=m
CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
CONFIG_TOUCHSCREEN_ROHM_BU21023=m
CONFIG_TOUCHSCREEN_IQS5XX=m
CONFIG_TOUCHSCREEN_ZINITIX=m
CONFIG_ROCKCHIP_REMOTECTL=y
CONFIG_ROCKCHIP_REMOTECTL_PWM=y

#
# handle all sensors
#
# CONFIG_SENSOR_DEVICE is not set
CONFIG_INPUT_MISC=y
CONFIG_INPUT_AD714X=m
CONFIG_INPUT_AD714X_I2C=m
CONFIG_INPUT_AD714X_SPI=m
CONFIG_INPUT_ATMEL_CAPTOUCH=m
CONFIG_INPUT_BMA150=m
CONFIG_INPUT_E3X0_BUTTON=m
CONFIG_INPUT_MMA8450=m
CONFIG_INPUT_GPIO_BEEPER=m
CONFIG_INPUT_GPIO_DECODER=m
CONFIG_INPUT_GPIO_VIBRA=m
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
CONFIG_INPUT_KXTJ9=m
CONFIG_INPUT_POWERMATE=m
CONFIG_INPUT_YEALINK=m
CONFIG_INPUT_CM109=m
CONFIG_INPUT_REGULATOR_HAPTIC=m
CONFIG_INPUT_UINPUT=y
CONFIG_INPUT_PCF8574=m
CONFIG_INPUT_PWM_BEEPER=m
CONFIG_INPUT_PWM_VIBRA=m
CONFIG_INPUT_RK805_PWRKEY=y
CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
CONFIG_INPUT_ADXL34X=m
CONFIG_INPUT_ADXL34X_I2C=m
CONFIG_INPUT_ADXL34X_SPI=m
CONFIG_INPUT_IMS_PCU=m
CONFIG_INPUT_IQS269A=m
CONFIG_INPUT_CMA3000=m
CONFIG_INPUT_CMA3000_I2C=m
CONFIG_INPUT_SOC_BUTTON_ARRAY=m
CONFIG_INPUT_DRV260X_HAPTICS=m
CONFIG_INPUT_DRV2665_HAPTICS=m
CONFIG_INPUT_DRV2667_HAPTICS=m
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=m
CONFIG_RMI4_SPI=m
CONFIG_RMI4_SMB=m
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=y
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
CONFIG_RMI4_F3A=y
CONFIG_RMI4_F54=y
CONFIG_RMI4_F55=y

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=m
CONFIG_SERIO_AMBAKMI=m
CONFIG_SERIO_PCIPS2=m
CONFIG_SERIO_LIBPS2=m
CONFIG_SERIO_RAW=m
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
CONFIG_GAMEPORT=m
# CONFIG_GAMEPORT_NS558 is not set
# CONFIG_GAMEPORT_L4 is not set
# CONFIG_GAMEPORT_EMU10K1 is not set
# CONFIG_GAMEPORT_FM801 is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_PNP=y
CONFIG_SERIAL_8250_16550A_VARIANTS=y
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=10
CONFIG_SERIAL_8250_RUNTIME_UARTS=10
# CONFIG_SERIAL_8250_EXTENDED is not set
# CONFIG_SERIAL_8250_ASPEED_VUART is not set
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
CONFIG_SERIAL_AMBA_PL010=m
CONFIG_SERIAL_AMBA_PL011=m
# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
# CONFIG_SERIAL_SAMSUNG is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_MSM_GENI_EARLY_CONSOLE is not set
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_IFX6X60 is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_NOZOMI is not set
# CONFIG_NULL_TTY is not set
# CONFIG_TRACE_SINK is not set
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
# CONFIG_SERIAL_DEV_BUS is not set
# CONFIG_TTY_PRINTK is not set
CONFIG_VIRTIO_CONSOLE=m
# CONFIG_IPMI_HANDLER is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
# CONFIG_HW_RANDOM_BA431 is not set
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_HISI_V2=y
CONFIG_HW_RANDOM_OPTEE=y
# CONFIG_HW_RANDOM_CCTRNG is not set
# CONFIG_HW_RANDOM_XIPHERA is not set
CONFIG_HW_RANDOM_ROCKCHIP=y
# CONFIG_APPLICOM is not set
CONFIG_DEVMEM=y
# CONFIG_RAW_DRIVER is not set
CONFIG_DEVPORT=y
CONFIG_TCG_TPM=y
CONFIG_HW_RANDOM_TPM=y
# CONFIG_TCG_TIS is not set
# CONFIG_TCG_TIS_SPI is not set
# CONFIG_TCG_TIS_I2C_ATMEL is not set
CONFIG_TCG_TIS_I2C_INFINEON=y
# CONFIG_TCG_TIS_I2C_NUVOTON is not set
# CONFIG_TCG_ATMEL is not set
# CONFIG_TCG_INFINEON is not set
# CONFIG_TCG_CRB is not set
# CONFIG_TCG_VTPM_PROXY is not set
# CONFIG_TCG_FTPM_TEE is not set
# CONFIG_TCG_TIS_ST33ZP24_I2C is not set
# CONFIG_TCG_TIS_ST33ZP24_SPI is not set
# CONFIG_XILLYBUS is not set
# CONFIG_RANDOM_TRUST_CPU is not set
# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
# CONFIG_I2C_MUX_GPIO is not set
# CONFIG_I2C_MUX_GPMUX is not set
# CONFIG_I2C_MUX_LTC4306 is not set
# CONFIG_I2C_MUX_PCA9541 is not set
# CONFIG_I2C_MUX_PCA954x is not set
CONFIG_I2C_MUX_PINCTRL=m
CONFIG_I2C_MUX_REG=m
CONFIG_I2C_DEMUX_PINCTRL=m
# CONFIG_I2C_MUX_MLXCPLD is not set
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_ALGOBIT=y

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set

#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CADENCE is not set
# CONFIG_I2C_CBUS_GPIO is not set
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
# CONFIG_I2C_DESIGNWARE_PCI is not set
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=m
# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
CONFIG_I2C_RK3X=y
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_THUNDERX is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
CONFIG_I2C_TINY_USB=m

#
# Other I2C/SMBus bus drivers
#
# end of I2C Hardware Bus support

# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=m
CONFIG_I2C_SLAVE_TESTUNIT=m
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

# CONFIG_I3C is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y

#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
CONFIG_SPI_BITBANG=y
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_HISI_SFC_V3XX is not set
# CONFIG_SPI_NXP_FLEXSPI is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PL022 is not set
# CONFIG_SPI_PXA2XX is not set
CONFIG_SPI_ROCKCHIP=y
# CONFIG_SPI_ROCKCHIP_MISCDEV is not set
CONFIG_SPI_ROCKCHIP_SFC=y
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_THUNDERX is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_SPI_AMD is not set

#
# SPI Multiplexer support
#
# CONFIG_SPI_MUX is not set

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_LOOPBACK_TEST is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_DYNAMIC=y
# CONFIG_SPMI is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set

#
# PPS clients support
#
CONFIG_PPS_CLIENT_KTIMER=m
# CONFIG_PPS_CLIENT_LDISC is not set
CONFIG_PPS_CLIENT_GPIO=m

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
# CONFIG_DP83640_PHY is not set
# CONFIG_PTP_1588_CLOCK_INES is not set
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_PINMUX=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_PINCTRL_AMD is not set
# CONFIG_PINCTRL_MCP23S08 is not set
CONFIG_PINCTRL_ROCKCHIP=y
# CONFIG_PINCTRL_SINGLE is not set
# CONFIG_PINCTRL_SX150X is not set
# CONFIG_PINCTRL_STMFX is not set
CONFIG_PINCTRL_RK805=y
CONFIG_PINCTRL_RK806=y
# CONFIG_PINCTRL_OCELOT is not set

#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers

CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_FTGPIO010 is not set
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_LOGICVC is not set
# CONFIG_GPIO_MB86S7X is not set
# CONFIG_GPIO_PL061 is not set
CONFIG_GPIO_ROCKCHIP=y
# CONFIG_GPIO_SAMA5D2_PIOBU is not set
# CONFIG_GPIO_SIFIVE is not set
# CONFIG_GPIO_SYSCON is not set
# CONFIG_GPIO_XGENE is not set
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
# CONFIG_GPIO_ADP5588 is not set
# CONFIG_GPIO_ADNP is not set
# CONFIG_GPIO_AW9110 is not set
# CONFIG_GPIO_GW_PLD is not set
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_NCA9539 is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCA9570 is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_TPIC2810 is not set
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
# CONFIG_GPIO_TPS6586X is not set
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set
# end of PCI GPIO expanders

#
# SPI GPIO expanders
#
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
# end of USB GPIO expanders

# CONFIG_GPIO_AGGREGATOR is not set
# CONFIG_GPIO_MOCKUP is not set
CONFIG_W1=m
CONFIG_W1_CON=y

#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_MATROX=m
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
CONFIG_W1_MASTER_DS1WM=m
CONFIG_W1_MASTER_GPIO=m
# CONFIG_W1_MASTER_SGI is not set
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
# CONFIG_W1_SLAVE_DS2405 is not set
CONFIG_W1_SLAVE_DS2408=m
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
# CONFIG_W1_SLAVE_DS2805 is not set
# CONFIG_W1_SLAVE_DS2430 is not set
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
# CONFIG_W1_SLAVE_DS2438 is not set
# CONFIG_W1_SLAVE_DS250X is not set
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
# CONFIG_W1_SLAVE_DS28E17 is not set
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_BRCMSTB is not set
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
# CONFIG_POWER_RESET_LTC2952 is not set
# CONFIG_POWER_RESET_RESTART is not set
# CONFIG_POWER_RESET_XGENE is not set
# CONFIG_POWER_RESET_SYSCON is not set
# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
# CONFIG_NVMEM_REBOOT_MODE is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_PDA_POWER is not set
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_CW2015 is not set
CONFIG_BATTERY_CW2017=m
# CONFIG_BATTERY_CW221X is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
CONFIG_BATTERY_SBS=m
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_BATTERY_MAX1721X is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
CONFIG_CHARGER_GPIO=m
# CONFIG_CHARGER_MANAGER is not set
# CONFIG_ROCKCHIP_CHARGER_MANAGER is not set
# CONFIG_CHARGER_LT3651 is not set
# CONFIG_CHARGER_SC8551 is not set
# CONFIG_CHARGER_SC89890 is not set
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
CONFIG_CHARGER_BQ24735=m
# CONFIG_CHARGER_BQ2515X is not set
CONFIG_CHARGER_BQ25700=m
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_BQ25980 is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
CONFIG_BATTERY_RT5033=m
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
CONFIG_BATTERY_RK816=m
CONFIG_BATTERY_RK817=m
CONFIG_CHARGER_RK817=m
CONFIG_BATTERY_RK818=m
CONFIG_CHARGER_RK818=m
# CONFIG_CHARGER_SGM41542 is not set
CONFIG_HWMON=y
CONFIG_HWMON_VID=m
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM1177 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7310 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_AS370 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
CONFIG_SENSORS_ARM_SCMI=m
CONFIG_SENSORS_ASPEED=m
CONFIG_SENSORS_ATXP1=m
CONFIG_SENSORS_CORSAIR_CPRO=m
CONFIG_SENSORS_DRIVETEMP=m
CONFIG_SENSORS_DS620=m
CONFIG_SENSORS_DS1621=m
CONFIG_SENSORS_I5K_AMB=m
CONFIG_SENSORS_F71805F=m
CONFIG_SENSORS_F71882FG=m
CONFIG_SENSORS_F75375S=m
CONFIG_SENSORS_FTSTEUTATES=m
CONFIG_SENSORS_GL518SM=m
CONFIG_SENSORS_GL520SM=m
CONFIG_SENSORS_G760A=m
CONFIG_SENSORS_G762=m
CONFIG_SENSORS_GPIO_FAN=m
CONFIG_SENSORS_HIH6130=m
CONFIG_SENSORS_IIO_HWMON=m
CONFIG_SENSORS_IT87=m
CONFIG_SENSORS_JC42=m
CONFIG_SENSORS_POWR1220=m
CONFIG_SENSORS_LINEAGE=m
CONFIG_SENSORS_LTC2945=m
CONFIG_SENSORS_LTC2947=m
CONFIG_SENSORS_LTC2947_I2C=m
CONFIG_SENSORS_LTC2947_SPI=m
CONFIG_SENSORS_LTC2990=m
CONFIG_SENSORS_LTC4151=m
CONFIG_SENSORS_LTC4215=m
CONFIG_SENSORS_LTC4222=m
CONFIG_SENSORS_LTC4245=m
CONFIG_SENSORS_LTC4260=m
CONFIG_SENSORS_LTC4261=m
# CONFIG_SENSORS_MAX1111 is not set
CONFIG_SENSORS_MAX16065=m
CONFIG_SENSORS_MAX1619=m
CONFIG_SENSORS_MAX1668=m
CONFIG_SENSORS_MAX197=m
CONFIG_SENSORS_MAX31722=m
CONFIG_SENSORS_MAX31730=m
CONFIG_SENSORS_MAX6621=m
CONFIG_SENSORS_MAX6639=m
CONFIG_SENSORS_MAX6642=m
CONFIG_SENSORS_MAX6650=m
CONFIG_SENSORS_MAX6697=m
CONFIG_SENSORS_MAX31790=m
CONFIG_SENSORS_MCP3021=m
CONFIG_SENSORS_TC654=m
CONFIG_SENSORS_MR75203=m
CONFIG_SENSORS_ADCXX=m
CONFIG_SENSORS_LM63=m
CONFIG_SENSORS_LM70=m
CONFIG_SENSORS_LM73=m
CONFIG_SENSORS_LM75=m
CONFIG_SENSORS_LM77=m
CONFIG_SENSORS_LM78=m
CONFIG_SENSORS_LM80=m
CONFIG_SENSORS_LM83=m
CONFIG_SENSORS_LM85=m
CONFIG_SENSORS_LM87=m
CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_LM92=m
CONFIG_SENSORS_LM93=m
CONFIG_SENSORS_LM95234=m
CONFIG_SENSORS_LM95241=m
CONFIG_SENSORS_LM95245=m
CONFIG_SENSORS_PC87360=m
CONFIG_SENSORS_PC87427=m
CONFIG_SENSORS_NTC_THERMISTOR=m
CONFIG_SENSORS_NCT6683=m
CONFIG_SENSORS_NCT6775=m
CONFIG_SENSORS_NCT7802=m
CONFIG_SENSORS_NCT7904=m
CONFIG_SENSORS_NPCM7XX=m
CONFIG_SENSORS_OCC_P8_I2C=m
CONFIG_SENSORS_OCC=m
CONFIG_SENSORS_PCF8591=m
CONFIG_PMBUS=m
CONFIG_SENSORS_PMBUS=m
# CONFIG_SENSORS_ADM1266 is not set
# CONFIG_SENSORS_ADM1275 is not set
# CONFIG_SENSORS_BEL_PFE is not set
# CONFIG_SENSORS_IBM_CFFPS is not set
# CONFIG_SENSORS_INSPUR_IPSPS is not set
# CONFIG_SENSORS_IR35221 is not set
# CONFIG_SENSORS_IR38064 is not set
# CONFIG_SENSORS_IRPS5401 is not set
# CONFIG_SENSORS_ISL68137 is not set
# CONFIG_SENSORS_LM25066 is not set
# CONFIG_SENSORS_LTC2978 is not set
# CONFIG_SENSORS_LTC3815 is not set
# CONFIG_SENSORS_MAX16064 is not set
# CONFIG_SENSORS_MAX16601 is not set
# CONFIG_SENSORS_MAX20730 is not set
# CONFIG_SENSORS_MAX20751 is not set
# CONFIG_SENSORS_MAX31785 is not set
# CONFIG_SENSORS_MAX34440 is not set
# CONFIG_SENSORS_MAX8688 is not set
# CONFIG_SENSORS_MP2975 is not set
# CONFIG_SENSORS_PXE1610 is not set
# CONFIG_SENSORS_TPS40422 is not set
# CONFIG_SENSORS_TPS53679 is not set
# CONFIG_SENSORS_UCD9000 is not set
# CONFIG_SENSORS_UCD9200 is not set
# CONFIG_SENSORS_XDPE122 is not set
# CONFIG_SENSORS_ZL6100 is not set
CONFIG_SENSORS_PWM_FAN=m
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC2305 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_TMP513 is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_XGENE is not set

#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
# CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE is not set
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR=y
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
# CONFIG_THERMAL_EMULATION is not set
# CONFIG_THERMAL_MMIO is not set
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_RK_VIRTUAL_THERMAL=y
# CONFIG_GENERIC_ADC_THERMAL is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_GPIO_WATCHDOG is not set
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
# CONFIG_ARM_SP805_WATCHDOG is not set
# CONFIG_ARM_SBSA_WATCHDOG is not set
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=y
# CONFIG_MAX63XX_WATCHDOG is not set
# CONFIG_ARM_SMC_WATCHDOG is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_MEN_A21_WDT is not set

#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB=m
CONFIG_SSB_SPROM=y
CONFIG_SSB_BLOCKIO=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_PCIHOST=y
CONFIG_SSB_B43_PCI_BRIDGE=y
CONFIG_SSB_SDIOHOST_POSSIBLE=y
# CONFIG_SSB_SDIOHOST is not set
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
CONFIG_SSB_DRIVER_PCICORE=y
# CONFIG_SSB_DRIVER_GPIO is not set
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_BLOCKIO=y
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
CONFIG_BCMA_HOST_PCI=y
# CONFIG_BCMA_HOST_SOC is not set
CONFIG_BCMA_DRIVER_PCI=y
# CONFIG_BCMA_DRIVER_GMAC_CMN is not set
# CONFIG_BCMA_DRIVER_GPIO is not set
# CONFIG_BCMA_DEBUG is not set

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AXP20X_I2C is not set
# CONFIG_MFD_MADERA is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MAX96745 is not set
# CONFIG_MFD_MAX96755F is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_UCB1400_CORE is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RC5T583 is not set
# CONFIG_MFD_RK618 is not set
# CONFIG_MFD_RK628 is not set
# CONFIG_MFD_RK630 is not set
# CONFIG_MFD_RK630_I2C is not set
# CONFIG_MFD_RK630_SPI is not set
CONFIG_MFD_RK806=y
CONFIG_MFD_RK806_SPI=y
CONFIG_MFD_RK808=y
CONFIG_MFD_RK1000=m

#
# driver for different display serdes
#
# CONFIG_MFD_SERDES_DISPLAY is not set
# CONFIG_MFD_RKX110_X120 is not set
# CONFIG_ROCKCHIP_SERDES_DRM_PANEL is not set
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
CONFIG_MFD_TPS6586X=y
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS80031 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TQMX86 is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
# CONFIG_MFD_ROHM_BD70528 is not set
# CONFIG_MFD_ROHM_BD71828 is not set
# CONFIG_MFD_STPMIC1 is not set
# CONFIG_MFD_STMFX is not set
# CONFIG_MFD_KHADAS_MCU is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
CONFIG_REGULATOR_USERSPACE_CONSUMER=m
CONFIG_REGULATOR_88PG86X=m
CONFIG_REGULATOR_ACT8865=m
CONFIG_REGULATOR_AD5398=m
CONFIG_REGULATOR_ARM_SCMI=y
CONFIG_REGULATOR_DA9210=m
CONFIG_REGULATOR_DA9211=m
CONFIG_REGULATOR_FAN53555=m
CONFIG_REGULATOR_FAN53880=m
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_ISL9305=m
CONFIG_REGULATOR_ISL6271A=m
CONFIG_REGULATOR_LP3971=m
CONFIG_REGULATOR_LP3972=m
CONFIG_REGULATOR_LP872X=m
CONFIG_REGULATOR_LP8752=m
CONFIG_REGULATOR_LP8755=m
CONFIG_REGULATOR_LTC3589=m
CONFIG_REGULATOR_LTC3676=m
CONFIG_REGULATOR_MAX1586=m
CONFIG_REGULATOR_MAX8649=m
CONFIG_REGULATOR_MAX8660=m
CONFIG_REGULATOR_MAX8952=m
CONFIG_REGULATOR_MAX8973=m
CONFIG_REGULATOR_MAX77826=m
CONFIG_REGULATOR_MCP16502=m
CONFIG_REGULATOR_MP5416=m
CONFIG_REGULATOR_MP8859=m
CONFIG_REGULATOR_MP8865=m
CONFIG_REGULATOR_MP886X=m
CONFIG_REGULATOR_MPQ7920=m
CONFIG_REGULATOR_MT6311=m
CONFIG_REGULATOR_PCA9450=m
CONFIG_REGULATOR_PFUZE100=m
CONFIG_REGULATOR_PV88060=m
CONFIG_REGULATOR_PV88080=m
CONFIG_REGULATOR_PV88090=m
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
CONFIG_REGULATOR_RK806=y
CONFIG_REGULATOR_RK808=y
CONFIG_REGULATOR_RK860X=y
CONFIG_REGULATOR_RT4801=m
CONFIG_REGULATOR_RTMV20=m
CONFIG_REGULATOR_SLG51000=m
CONFIG_REGULATOR_SY8106A=m
CONFIG_REGULATOR_SY8824X=m
CONFIG_REGULATOR_SY8827N=m
CONFIG_REGULATOR_TPS51632=m
CONFIG_REGULATOR_TPS62360=m
CONFIG_REGULATOR_TPS65023=m
CONFIG_REGULATOR_TPS6507X=m
CONFIG_REGULATOR_TPS65132=m
CONFIG_REGULATOR_TPS6524X=m
CONFIG_REGULATOR_TPS6586X=m
CONFIG_REGULATOR_VCTRL=y
# CONFIG_REGULATOR_WL2868C is not set
CONFIG_REGULATOR_XZ3216=m
CONFIG_RC_CORE=y
CONFIG_RC_MAP=m
# CONFIG_LIRC is not set
CONFIG_RC_DECODERS=y
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
CONFIG_IR_JVC_DECODER=m
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_XMP_DECODER=m
CONFIG_IR_IMON_DECODER=m
CONFIG_IR_RCMM_DECODER=m
CONFIG_RC_DEVICES=y
CONFIG_RC_ATI_REMOTE=m
CONFIG_IR_ENE=m
CONFIG_IR_HIX5HD2=m
CONFIG_IR_IMON=m
CONFIG_IR_IMON_RAW=m
CONFIG_IR_MCEUSB=m
CONFIG_IR_ITE_CIR=m
CONFIG_IR_FINTEK=m
CONFIG_IR_NUVOTON=m
CONFIG_IR_REDRAT3=m
CONFIG_IR_STREAMZAP=m
CONFIG_IR_IGORPLUGUSB=m
CONFIG_IR_IGUANA=m
CONFIG_IR_TTUSBIR=m
CONFIG_RC_LOOPBACK=m
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_SERIAL=m
# CONFIG_IR_SERIAL_TRANSMITTER is not set
CONFIG_IR_SIR=m
CONFIG_RC_XBOX_DVD=m
CONFIG_IR_TOY=m
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y
CONFIG_MEDIA_CEC_RC=y
CONFIG_MEDIA_CEC_SUPPORT=y
# CONFIG_CEC_CH7322 is not set
# CONFIG_CEC_GPIO is not set
# CONFIG_USB_PULSE8_CEC is not set
# CONFIG_USB_RAINSHADOW_CEC is not set
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_SUPPORT_FILTER=y
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_SDR_SUPPORT is not set
CONFIG_MEDIA_PLATFORM_SUPPORT=y
# CONFIG_MEDIA_TEST_SUPPORT is not set
# end of Media device types

CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CONTROLLER=y

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2=y
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_H264=y
CONFIG_V4L2_MEM2MEM_DEV=y
# CONFIG_V4L2_FLASH_LED_CLASS is not set
CONFIG_V4L2_FWNODE=y
CONFIG_VIDEOBUF_GEN=m
CONFIG_VIDEOBUF_VMALLOC=m
# end of Video4Linux options

#
# Media controller options
#
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y

#
# Please notice that the enabled Media controller Request API is EXPERIMENTAL
#
# end of Media controller options

#
# Media drivers
#

#
# Drivers filtered as selected at 'Filter media drivers'
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_VIDEO_CLASS=y
# CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set
CONFIG_USB_GSPCA=m
# CONFIG_USB_M5602 is not set
# CONFIG_USB_STV06XX is not set
# CONFIG_USB_GL860 is not set
# CONFIG_USB_GSPCA_BENQ is not set
# CONFIG_USB_GSPCA_CONEX is not set
# CONFIG_USB_GSPCA_CPIA1 is not set
# CONFIG_USB_GSPCA_DTCS033 is not set
# CONFIG_USB_GSPCA_ETOMS is not set
# CONFIG_USB_GSPCA_FINEPIX is not set
# CONFIG_USB_GSPCA_JEILINJ is not set
# CONFIG_USB_GSPCA_JL2005BCD is not set
# CONFIG_USB_GSPCA_KINECT is not set
# CONFIG_USB_GSPCA_KONICA is not set
# CONFIG_USB_GSPCA_MARS is not set
# CONFIG_USB_GSPCA_MR97310A is not set
# CONFIG_USB_GSPCA_NW80X is not set
# CONFIG_USB_GSPCA_OV519 is not set
# CONFIG_USB_GSPCA_OV534 is not set
# CONFIG_USB_GSPCA_OV534_9 is not set
# CONFIG_USB_GSPCA_PAC207 is not set
# CONFIG_USB_GSPCA_PAC7302 is not set
# CONFIG_USB_GSPCA_PAC7311 is not set
# CONFIG_USB_GSPCA_SE401 is not set
# CONFIG_USB_GSPCA_SN9C2028 is not set
# CONFIG_USB_GSPCA_SN9C20X is not set
# CONFIG_USB_GSPCA_SONIXB is not set
# CONFIG_USB_GSPCA_SONIXJ is not set
# CONFIG_USB_GSPCA_SPCA500 is not set
# CONFIG_USB_GSPCA_SPCA501 is not set
# CONFIG_USB_GSPCA_SPCA505 is not set
# CONFIG_USB_GSPCA_SPCA506 is not set
# CONFIG_USB_GSPCA_SPCA508 is not set
# CONFIG_USB_GSPCA_SPCA561 is not set
# CONFIG_USB_GSPCA_SPCA1528 is not set
# CONFIG_USB_GSPCA_SQ905 is not set
# CONFIG_USB_GSPCA_SQ905C is not set
# CONFIG_USB_GSPCA_SQ930X is not set
# CONFIG_USB_GSPCA_STK014 is not set
# CONFIG_USB_GSPCA_STK1135 is not set
# CONFIG_USB_GSPCA_STV0680 is not set
# CONFIG_USB_GSPCA_SUNPLUS is not set
# CONFIG_USB_GSPCA_T613 is not set
# CONFIG_USB_GSPCA_TOPRO is not set
# CONFIG_USB_GSPCA_TOUPTEK is not set
# CONFIG_USB_GSPCA_TV8532 is not set
# CONFIG_USB_GSPCA_VC032X is not set
# CONFIG_USB_GSPCA_VICAM is not set
# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
# CONFIG_USB_GSPCA_ZC3XX is not set
CONFIG_USB_PWC=m
# CONFIG_USB_PWC_DEBUG is not set
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_VIDEO_CPIA2=m
CONFIG_USB_ZR364XX=m
CONFIG_USB_STKWEBCAM=m
CONFIG_USB_S2255=m
CONFIG_VIDEO_USBTV=m

#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=m
CONFIG_VIDEO_EM28XX_V4L2=m
CONFIG_VIDEO_EM28XX_ALSA=m
CONFIG_VIDEO_EM28XX_RC=m
CONFIG_MEDIA_PCI_SUPPORT=y

#
# Media capture support
#
CONFIG_VIDEO_SOLO6X10=m
CONFIG_VIDEO_TW5864=m
CONFIG_VIDEO_TW68=m
CONFIG_VIDEO_TW686X=m
CONFIG_VIDEO_TVEEPROM=m
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_CMA_SG=y
CONFIG_VIDEOBUF2_DMA_CONTIG=y
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_VIDEOBUF2_DMA_SG=y
CONFIG_V4L_PLATFORM_DRIVERS=y
# CONFIG_VIDEO_CAFE_CCIC is not set
# CONFIG_VIDEO_CADENCE is not set
# CONFIG_VIDEO_ASPEED is not set
CONFIG_VIDEO_MUX=y
CONFIG_VIDEO_ROCKCHIP_CIF=y
CONFIG_ROCKCHIP_CIF_WORKMODE_PINGPONG=y
# CONFIG_ROCKCHIP_CIF_WORKMODE_ONEFRAME is not set
CONFIG_ROCKCHIP_CIF_USE_DUMMY_BUF=y
# CONFIG_ROCKCHIP_CIF_USE_NONE_DUMMY_BUF is not set
# CONFIG_ROCKCHIP_CIF_USE_MONITOR is not set
# CONFIG_VIDEO_ROCKCHIP_RKISP1 is not set
CONFIG_VIDEO_ROCKCHIP_ISP=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V1X=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V20=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V21=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V30=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32=y
CONFIG_VIDEO_ROCKCHIP_ISPP=y
CONFIG_VIDEO_ROCKCHIP_ISPP_FEC=y
CONFIG_VIDEO_ROCKCHIP_ISPP_VERSION_V10=y
CONFIG_VIDEO_ROCKCHIP_ISPP_VERSION_V20=y
CONFIG_VIDEO_ROCKCHIP_HDMIRX_CLASS=y
CONFIG_VIDEO_ROCKCHIP_HDMIRX=y
# CONFIG_VIDEO_XILINX is not set
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
CONFIG_VIDEO_ROCKCHIP_RGA=y
# end of Media drivers

#
# Media ancillary drivers
#
CONFIG_VIDEO_IR_I2C=y

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_TVAUDIO=m
CONFIG_VIDEO_TDA7432=m
CONFIG_VIDEO_TDA9840=m
CONFIG_VIDEO_TDA1997X=m
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
CONFIG_VIDEO_MSP3400=m
CONFIG_VIDEO_CS3308=m
CONFIG_VIDEO_CS5345=m
CONFIG_VIDEO_CS53L32A=m
CONFIG_VIDEO_TLV320AIC23B=m
CONFIG_VIDEO_UDA1342=m
CONFIG_VIDEO_WM8775=m
CONFIG_VIDEO_WM8739=m
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_SONY_BTF_MPX=m
# end of Audio decoders, processors and mixers

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders

#
# Video decoders
#
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_ADV7183=m
CONFIG_VIDEO_ADV748X=m
CONFIG_VIDEO_ADV7604=m
# CONFIG_VIDEO_ADV7604_CEC is not set
CONFIG_VIDEO_ADV7842=m
# CONFIG_VIDEO_ADV7842_CEC is not set
CONFIG_VIDEO_BT819=m
CONFIG_VIDEO_BT856=m
CONFIG_VIDEO_BT866=m
CONFIG_VIDEO_EP9461E=m
CONFIG_VIDEO_KS0127=m
CONFIG_VIDEO_IT6616=m
CONFIG_VIDEO_LT6911UXC=m
CONFIG_VIDEO_LT6911UXE=m
CONFIG_VIDEO_LT7911D=m
CONFIG_VIDEO_LT7911UXC=m
CONFIG_VIDEO_LT8619C=m
CONFIG_VIDEO_ML86V7667=m
CONFIG_VIDEO_NVP6158=m
CONFIG_VIDEO_NVP6188=m
CONFIG_VIDEO_NVP6324=m
CONFIG_VIDEO_OTP_EEPROM=m
CONFIG_VIDEO_RK628=y
CONFIG_VIDEO_RK628_CSI=y
CONFIG_VIDEO_RK628_BT1120=y
CONFIG_VIDEO_SAA7110=m
CONFIG_VIDEO_SAA711X=m
CONFIG_VIDEO_TC358743=m
# CONFIG_VIDEO_TC358743_CEC is not set
CONFIG_VIDEO_TC35874X=m
CONFIG_VIDEO_TECHPOINT=m
CONFIG_VIDEO_THCV244=m
CONFIG_VIDEO_TVP514X=m
CONFIG_VIDEO_TVP5150=m
CONFIG_VIDEO_TVP7002=m
CONFIG_VIDEO_TW2804=m
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=m
CONFIG_VIDEO_TW9910=m
CONFIG_VIDEO_VPX3220=m
CONFIG_VIDEO_MAX9286=m
CONFIG_VIDEO_MAX96712=m
CONFIG_VIDEO_MAX96714=m
CONFIG_VIDEO_MAX96722=m
CONFIG_VIDEO_DES_MAXIM4C=m

#
# Maxim Quad GMSL serializer devices support
#
# CONFIG_MAXIM4C_SER_MAX9295 is not set
# CONFIG_MAXIM4C_SER_MAX96715 is not set
# CONFIG_MAXIM4C_SER_MAX96717 is not set
# end of Maxim Quad GMSL serializer devices support

#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=m
CONFIG_VIDEO_CX25840=m
CONFIG_VIDEO_IT66353=m
# end of Video decoders

#
# Video encoders
#
CONFIG_VIDEO_SAA7127=m
CONFIG_VIDEO_SAA7185=m
CONFIG_VIDEO_ADV7170=m
CONFIG_VIDEO_ADV7175=m
CONFIG_VIDEO_ADV7343=m
CONFIG_VIDEO_ADV7393=m
CONFIG_VIDEO_ADV7511=m
# CONFIG_VIDEO_ADV7511_CEC is not set
CONFIG_VIDEO_AD9389B=m
CONFIG_VIDEO_AK881X=m
CONFIG_VIDEO_THS8200=m
# end of Video encoders

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
CONFIG_VIDEO_UPD64083=m
# end of Video improvement chips

#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips

#
# SDR tuner chips
#
# end of SDR tuner chips

#
# Miscellaneous helper chips
#
CONFIG_VIDEO_THS7303=m
CONFIG_VIDEO_M52790=m
CONFIG_VIDEO_I2C=m
CONFIG_VIDEO_ST_MIPID02=m
CONFIG_VIDEO_RK_IRCUT=y
# end of Miscellaneous helper chips

#
# Camera sensor devices
#
CONFIG_VIDEO_APTINA_PLL=m
CONFIG_VIDEO_SMIAPP_PLL=m
CONFIG_VIDEO_AR0230=m
CONFIG_VIDEO_AR0822=m
CONFIG_VIDEO_GC02M2=m
CONFIG_VIDEO_GC08A3=m
CONFIG_VIDEO_GC1084=m
CONFIG_VIDEO_GC2053=m
CONFIG_VIDEO_GC2093=m
CONFIG_VIDEO_GC2145=m
CONFIG_VIDEO_GC2385=m
CONFIG_VIDEO_GC3003=m
CONFIG_VIDEO_GC4023=m
CONFIG_VIDEO_GC4653=m
CONFIG_VIDEO_GC4663=m
CONFIG_VIDEO_GC4C33=m
CONFIG_VIDEO_GC5025=m
CONFIG_VIDEO_GC5035=m
CONFIG_VIDEO_GC8034=m
CONFIG_VIDEO_HI556=m
CONFIG_VIDEO_IMX214=m
CONFIG_VIDEO_IMX214_EEPROM=m
CONFIG_VIDEO_IMX219=m
CONFIG_VIDEO_IMX258=m
CONFIG_VIDEO_IMX258_EEPROM=m
CONFIG_VIDEO_IMX274=m
CONFIG_VIDEO_IMX290=m
CONFIG_VIDEO_IMX307=m
CONFIG_VIDEO_IMX317=m
CONFIG_VIDEO_IMX319=m
CONFIG_VIDEO_IMX323=m
CONFIG_VIDEO_IMX327=m
CONFIG_VIDEO_IMX334=m
CONFIG_VIDEO_IMX335=m
CONFIG_VIDEO_IMX347=m
CONFIG_VIDEO_IMX378=m
CONFIG_VIDEO_IMX415=m
CONFIG_VIDEO_IMX464=m
CONFIG_VIDEO_IMX492=m
CONFIG_VIDEO_IMX355=m
CONFIG_VIDEO_IMX577=m
CONFIG_VIDEO_IMX586=m
CONFIG_VIDEO_JX_K17=m
CONFIG_VIDEO_OS02G10=m
CONFIG_VIDEO_OS02K10=m
CONFIG_VIDEO_OS03B10=m
CONFIG_VIDEO_OS04A10=m
CONFIG_VIDEO_OS05A20=m
CONFIG_VIDEO_OS08A20=m
CONFIG_VIDEO_OV02B10=m
CONFIG_VIDEO_OV02K10=m
CONFIG_VIDEO_OV16A10=m
CONFIG_VIDEO_OV16A1Q=m
CONFIG_VIDEO_OV2640=m
CONFIG_VIDEO_OV2659=m
CONFIG_VIDEO_OV2680=m
CONFIG_VIDEO_OV2685=m
CONFIG_VIDEO_OV2718=m
CONFIG_VIDEO_OV2740=m
CONFIG_VIDEO_OV4686=m
CONFIG_VIDEO_OV4688=m
CONFIG_VIDEO_OV4689=m
CONFIG_VIDEO_OV50C40=m
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_OV5647=m
CONFIG_VIDEO_OV6650=m
CONFIG_VIDEO_OV5670=m
CONFIG_VIDEO_OV5675=m
CONFIG_VIDEO_OV5695=m
CONFIG_VIDEO_OV7251=m
CONFIG_VIDEO_OV772X=m
CONFIG_VIDEO_OV7640=m
CONFIG_VIDEO_OV7670=m
CONFIG_VIDEO_OV7740=m
CONFIG_VIDEO_OV8856=m
CONFIG_VIDEO_OV8858=m
CONFIG_VIDEO_OV9281=m
CONFIG_VIDEO_OV9640=m
CONFIG_VIDEO_OV9650=m
CONFIG_VIDEO_OV12D2Q=m
CONFIG_VIDEO_OV13850=m
CONFIG_VIDEO_OV13855=m
CONFIG_VIDEO_OV13858=m
CONFIG_VIDEO_VS6624=m
CONFIG_VIDEO_MT9M001=m
CONFIG_VIDEO_MT9M032=m
CONFIG_VIDEO_MT9M111=m
CONFIG_VIDEO_MT9P031=m
CONFIG_VIDEO_MT9T001=m
CONFIG_VIDEO_MT9T112=m
CONFIG_VIDEO_MT9V011=m
CONFIG_VIDEO_MT9V032=m
CONFIG_VIDEO_MT9V111=m
CONFIG_VIDEO_SC031GS=m
CONFIG_VIDEO_SC035GS=m
CONFIG_VIDEO_SC132GS=m
CONFIG_VIDEO_SC1346=m
CONFIG_VIDEO_SC200AI=m
CONFIG_VIDEO_SC210IOT=m
CONFIG_VIDEO_SC2232=m
CONFIG_VIDEO_SC2239=m
CONFIG_VIDEO_SC223A=m
CONFIG_VIDEO_SC230AI=m
CONFIG_VIDEO_SC2310=m
CONFIG_VIDEO_SC2336=m
CONFIG_VIDEO_SC301IOT=m
CONFIG_VIDEO_SC3336=m
CONFIG_VIDEO_SC3338=m
CONFIG_VIDEO_SC401AI=m
CONFIG_VIDEO_SC4210=m
CONFIG_VIDEO_SC4238=m
CONFIG_VIDEO_SC430CS=m
CONFIG_VIDEO_SC4336=m
CONFIG_VIDEO_SC500AI=m
CONFIG_VIDEO_SC501AI=m
CONFIG_VIDEO_SC530AI=m
CONFIG_VIDEO_SC5336=m
CONFIG_VIDEO_SC850SL=m
CONFIG_VIDEO_SENSOR_ADAPTER=y
CONFIG_VIDEO_SR030PC30=m
CONFIG_VIDEO_NOON010PC30=m
CONFIG_VIDEO_M5MOLS=m
CONFIG_VIDEO_RDACM20=m
CONFIG_VIDEO_RJ54N1=m
CONFIG_VIDEO_S5K3L6XX=m
CONFIG_VIDEO_S5K6AA=m
CONFIG_VIDEO_S5K6A3=m
CONFIG_VIDEO_S5K4ECGX=m
CONFIG_VIDEO_S5K5BAF=m
CONFIG_VIDEO_S5KJN1=m
CONFIG_VIDEO_SMIAPP=m
CONFIG_VIDEO_ET8EK8=m
CONFIG_VIDEO_S5C73M3=m
CONFIG_VIDEO_PREISP_DUMMY_SENSOR=m
# end of Camera sensor devices

#
# Lens drivers
#
CONFIG_VIDEO_AD5820=m
CONFIG_VIDEO_AK7375=m
CONFIG_VIDEO_AW8601=m
CONFIG_VIDEO_CN3927V=m
CONFIG_VIDEO_DW9714=m
CONFIG_VIDEO_DW9763=m
CONFIG_VIDEO_DW9768=m
CONFIG_VIDEO_DW9800W=m
CONFIG_VIDEO_DW9807_VCM=m
CONFIG_VIDEO_FP5510=m
# end of Lens drivers

#
# Flash devices
#
CONFIG_VIDEO_ADP1653=m
CONFIG_VIDEO_AW36518=m
CONFIG_VIDEO_LM3560=m
CONFIG_VIDEO_LM3646=m
CONFIG_VIDEO_SGM3784=m
# end of Flash devices

#
# SPI helper chips
#
CONFIG_VIDEO_GS1662=m
CONFIG_VIDEO_ROCKCHIP_PREISP=y
# end of SPI helper chips

#
# Media SPI Adapters
#
# end of Media SPI Adapters
# end of Media ancillary drivers

#
# Graphics support
#
# CONFIG_VGA_ARB is not set
CONFIG_DRM=y
CONFIG_DRM_EDID=y
CONFIG_DRM_IGNORE_IOTCL_PERMIT=y
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_DP=y
CONFIG_DRM_DP_AUX_CHARDEV=y
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_KMS_FB_HELPER=y
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
CONFIG_DRM_LOAD_EDID_FIRMWARE=y
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_TTM=m
CONFIG_DRM_TTM_DMA_PAGE_POOL=y
CONFIG_DRM_TTM_HELPER=m
CONFIG_DRM_GEM_CMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=y
CONFIG_DRM_VM=y
CONFIG_DRM_SCHED=m

#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips

#
# ARM devices
#
# CONFIG_DRM_HDLCD is not set
# CONFIG_DRM_MALI_DISPLAY is not set
# CONFIG_DRM_KOMEDA is not set
# end of ARM devices

CONFIG_DRM_RADEON=m
# CONFIG_DRM_RADEON_USERPTR is not set
CONFIG_DRM_AMDGPU=m
# CONFIG_DRM_AMDGPU_SI is not set
# CONFIG_DRM_AMDGPU_CIK is not set
# CONFIG_DRM_AMDGPU_USERPTR is not set
# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set

#
# ACP (Audio CoProcessor) Configuration
#
# CONFIG_DRM_AMD_ACP is not set
# end of ACP (Audio CoProcessor) Configuration

#
# Display Engine Configuration
#
CONFIG_DRM_AMD_DC=y
# CONFIG_DRM_AMD_DC_HDCP is not set
# end of Display Engine Configuration

# CONFIG_HSA_AMD is not set
CONFIG_DRM_NOUVEAU=m
CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT=y
CONFIG_NOUVEAU_DEBUG=5
CONFIG_NOUVEAU_DEBUG_DEFAULT=3
# CONFIG_NOUVEAU_DEBUG_MMU is not set
# CONFIG_NOUVEAU_DEBUG_PUSH is not set
CONFIG_DRM_NOUVEAU_BACKLIGHT=y
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
CONFIG_DRM_ROCKCHIP=y
# CONFIG_ROCKCHIP_DRM_DEBUG is not set
# CONFIG_ROCKCHIP_DRM_DIRECT_SHOW is not set
CONFIG_ROCKCHIP_VOP=y
CONFIG_ROCKCHIP_VOP2=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DRM_TVE=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_DW_DP=y
CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_ROCKCHIP_LVDS=y
CONFIG_ROCKCHIP_RGB=y
# CONFIG_ROCKCHIP_RK3066_HDMI is not set
# CONFIG_ROCKCHIP_VCONN is not set
# CONFIG_DRM_ROCKCHIP_VVOP is not set
CONFIG_ROCKCHIP_DW_HDCP2=y
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_LVDS is not set
CONFIG_DRM_QXL=m
# CONFIG_DRM_BOCHS is not set
CONFIG_DRM_VIRTIO_GPU=m
CONFIG_DRM_PANEL=y

#
# Display Panels
#
CONFIG_DRM_PANEL_ARM_VERSATILE=m
CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
CONFIG_DRM_PANEL_LVDS=m
CONFIG_DRM_PANEL_SIMPLE=m
CONFIG_DRM_PANEL_ELIDA_KD35T133=m
CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
CONFIG_DRM_PANEL_ILITEK_IL9322=m
CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=m
CONFIG_DRM_PANEL_JDI_LT070ME05000=m
CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
CONFIG_DRM_PANEL_LG_LB035Q02=m
CONFIG_DRM_PANEL_LG_LG4573=m
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
CONFIG_DRM_PANEL_NOVATEK_NT35510=m
CONFIG_DRM_PANEL_NOVATEK_NT39016=m
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
CONFIG_DRM_PANEL_MAXIM_MAX96752F=m
CONFIG_DRM_PANEL_MAXIM_MAX96772=m
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
CONFIG_DRM_PANEL_RADXA_DISPLAY_8HD=m
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
CONFIG_DRM_PANEL_RASPITS_TC358762=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
CONFIG_DRM_PANEL_RONBO_RB070D30=m
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
CONFIG_DRM_PANEL_SITRONIX_ST7789V=m
CONFIG_DRM_PANEL_SONY_ACX424AKP=m
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
CONFIG_DRM_PANEL_TPO_TPG110=m
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
CONFIG_DRM_PANEL_VISIONOX_RM69299=m
CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
CONFIG_DRM_DISPLAY_CONNECTOR=y
# CONFIG_DRM_ITE_IT6161 is not set
# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MAXIM_MAX96745 is not set
# CONFIG_DRM_MAXIM_MAX96755F is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
CONFIG_DRM_RK1000_TVE=m
# CONFIG_DRM_ROHM_BU18XL82 is not set
# CONFIG_DRM_SIL_SII8620 is not set
CONFIG_DRM_SII902X=m
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
CONFIG_DRM_ANALOGIX_DP=y
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=y
# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
CONFIG_DRM_DW_HDMI_CEC=m
CONFIG_DRM_DW_MIPI_DSI=y
# end of Display Interface Bridges

# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
# CONFIG_DRM_MXSFB is not set
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_GM12U320 is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_DRM_PL111 is not set
# CONFIG_DRM_LIMA is not set
# CONFIG_DRM_PANFROST is not set
# CONFIG_DRM_TIDSS is not set
CONFIG_DRM_LEGACY=y
# CONFIG_DRM_TDFX is not set
# CONFIG_DRM_R128 is not set
# CONFIG_DRM_MGA is not set
# CONFIG_DRM_VIA is not set
# CONFIG_DRM_SAVAGE is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_MALI400=m
CONFIG_MALI450=y
# CONFIG_MALI470 is not set
# CONFIG_MALI400_DEBUG is not set
# CONFIG_MALI400_PROFILING is not set
# CONFIG_MALI400_UMP is not set
CONFIG_MALI_DMA_BUF_MAP_ON_ATTACH=y
CONFIG_MALI_SHARED_INTERRUPTS=y
# CONFIG_MALI_PMU_PARALLEL_POWER_UP is not set
CONFIG_MALI_DT=y
CONFIG_MALI_DEVFREQ=y
# CONFIG_MALI_QUIET is not set
CONFIG_MALI_MIDGARD=m
# CONFIG_MALI_GATOR_SUPPORT is not set
# CONFIG_MALI_MIDGARD_ENABLE_TRACE is not set
# CONFIG_MALI_DMA_FENCE is not set
CONFIG_MALI_EXPERT=y
# CONFIG_MALI_CORESTACK is not set
# CONFIG_MALI_PRFCNT_SET_SECONDARY is not set
# CONFIG_MALI_PLATFORM_FAKE is not set
# CONFIG_MALI_PLATFORM_DEVICETREE is not set
CONFIG_MALI_PLATFORM_THIRDPARTY=y
CONFIG_MALI_PLATFORM_THIRDPARTY_NAME="rk"
CONFIG_MALI_DEBUG=y
CONFIG_MALI_FENCE_DEBUG=y
# CONFIG_MALI_NO_MALI is not set
# CONFIG_MALI_TRACE_TIMELINE is not set
# CONFIG_MALI_SYSTEM_TRACE is not set
# CONFIG_MALI_GPU_MMU_AARCH64 is not set
CONFIG_MALI_PWRSOFT_765=y
# CONFIG_MALI_KUTF is not set
CONFIG_MALI_BIFROST=m
CONFIG_MALI_PLATFORM_NAME="rk"
CONFIG_MALI_REAL_HW=y
# CONFIG_MALI_BIFROST_NO_MALI is not set

#
# Platform specific options
#
CONFIG_MALI_CSF_SUPPORT=y
CONFIG_MALI_BIFROST_DEVFREQ=y
CONFIG_MALI_BIFROST_GATOR_SUPPORT=y
CONFIG_MALI_BIFROST_ENABLE_TRACE=y
# CONFIG_MALI_DMA_BUF_MAP_ON_DEMAND is not set
# CONFIG_MALI_DMA_BUF_LEGACY_COMPAT is not set
# CONFIG_MALI_CORESIGHT is not set
CONFIG_MALI_BIFROST_EXPERT=y
# CONFIG_LARGE_PAGE_ALLOC_OVERRIDE is not set
# CONFIG_LARGE_PAGE_ALLOC is not set
# CONFIG_MALI_MEMORY_FULLY_BACKED is not set

#
# Platform options
#

#
# Debug options
#
CONFIG_MALI_BIFROST_DEBUG=y
CONFIG_MALI_BIFROST_FENCE_DEBUG=y
CONFIG_MALI_BIFROST_SYSTEM_TRACE=y

#
# Instrumentation options
#
CONFIG_MALI_PRFCNT_SET_PRIMARY=y
# CONFIG_MALI_BIFROST_PRFCNT_SET_SECONDARY is not set
# CONFIG_MALI_PRFCNT_SET_TERTIARY is not set
# CONFIG_MALI_PRFCNT_SET_SELECT_VIA_DEBUG_FS is not set
# CONFIG_MALI_JOB_DUMP is not set

#
# Workarounds
#
# CONFIG_MALI_HW_ERRATA_1485982_NOT_AFFECTED is not set
# CONFIG_MALI_HW_ERRATA_1485982_USE_CLOCK_ALTERNATIVE is not set
# CONFIG_MALI_ARBITRATION is not set

#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_BACKLIGHT=m
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_ARMCLCD is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_UVESA is not set
# CONFIG_FB_EFI is not set
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SSD1307 is not set
# CONFIG_FB_SM712 is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_KTD253 is not set
CONFIG_BACKLIGHT_PWM=y
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
# CONFIG_BACKLIGHT_GPIO is not set
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# CONFIG_BACKLIGHT_LED is not set
# end of Backlight & LCD device support

#
# Rockchip Misc Video driver
#

#
# RGA
#
CONFIG_ROCKCHIP_RGA=m
# end of RGA

CONFIG_ROCKCHIP_MULTI_RGA=y
CONFIG_ROCKCHIP_RGA_ASYNC=y
CONFIG_ROCKCHIP_RGA_PROC_FS=y
CONFIG_ROCKCHIP_RGA_DEBUG_FS=y
CONFIG_ROCKCHIP_RGA_DEBUGGER=y
CONFIG_ROCKCHIP_RVE=y
# CONFIG_ROCKCHIP_RVE_PROC_FS is not set
CONFIG_ROCKCHIP_RVE_DEBUG_FS=y
CONFIG_ROCKCHIP_RVE_DEBUGGER=y

#
# IEP
#
CONFIG_IEP=y
# end of IEP

CONFIG_ROCKCHIP_MPP_SERVICE=y
CONFIG_ROCKCHIP_MPP_PROC_FS=y
CONFIG_ROCKCHIP_MPP_RKVDEC=y
CONFIG_ROCKCHIP_MPP_RKVDEC2=y
CONFIG_ROCKCHIP_MPP_RKVENC=y
CONFIG_ROCKCHIP_MPP_RKVENC2=y
CONFIG_ROCKCHIP_MPP_VDPU1=y
CONFIG_ROCKCHIP_MPP_VEPU1=y
CONFIG_ROCKCHIP_MPP_VDPU2=y
CONFIG_ROCKCHIP_MPP_VEPU2=y
CONFIG_ROCKCHIP_MPP_IEP2=y
CONFIG_ROCKCHIP_MPP_JPGDEC=y
CONFIG_ROCKCHIP_MPP_AV1DEC=y
CONFIG_ROCKCHIP_MPP_VDPP=y
CONFIG_ROCKCHIP_DVBM=y
CONFIG_ROCKCHIP_DVBM_PROC_FS=y
# end of Rockchip Misc Video driver

CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
# end of Console display driver support

CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
# end of Graphics support

CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=m
CONFIG_SND_SEQ_DEVICE=y
CONFIG_SND_RAWMIDI=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_OSSEMUL is not set
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
CONFIG_SND_VMASTER=y
CONFIG_SND_SEQUENCER=m
CONFIG_SND_SEQ_DUMMY=m
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
CONFIG_SND_SEQ_MIDI_EVENT=m
CONFIG_SND_SEQ_MIDI=m
CONFIG_SND_SEQ_VIRMIDI=m
CONFIG_SND_MPU401_UART=m
CONFIG_SND_AC97_CODEC=y
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
CONFIG_SND_VIRMIDI=m
CONFIG_SND_MTPAV=m
CONFIG_SND_SERIAL_U16550=m
CONFIG_SND_MPU401=m
# CONFIG_SND_AC97_POWER_SAVE is not set
# CONFIG_SND_PCI is not set

#
# HD-Audio
#
# end of HD-Audio

CONFIG_SND_HDA_PREALLOC_SIZE=64
# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
CONFIG_SND_BCD2000=m
CONFIG_SND_USB_LINE6=m
CONFIG_SND_USB_POD=m
CONFIG_SND_USB_PODHD=m
CONFIG_SND_USB_TONEPORT=m
CONFIG_SND_USB_VARIAX=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
# CONFIG_SND_SOC_AMD_ACP is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
CONFIG_SND_DESIGNWARE_I2S=y
# CONFIG_SND_DESIGNWARE_PCM is not set

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
# CONFIG_SND_SOC_FSL_SAI is not set
# CONFIG_SND_SOC_FSL_AUDMIX is not set
# CONFIG_SND_SOC_FSL_SSI is not set
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
# CONFIG_SND_SOC_FSL_MICFIL is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs

# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_I2S_HI3660_I2S is not set
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set
CONFIG_SND_SOC_ROCKCHIP=y
CONFIG_SND_SOC_ROCKCHIP_DLP=y
CONFIG_SND_SOC_ROCKCHIP_I2S=y
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES=y
CONFIG_SND_SOC_ROCKCHIP_MULTI_DAIS=y
CONFIG_SND_SOC_ROCKCHIP_PDM=y
CONFIG_SND_SOC_ROCKCHIP_SAI=y
CONFIG_SND_SOC_ROCKCHIP_SAI_VERBOSE=y
CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
CONFIG_SND_SOC_ROCKCHIP_SPDIFRX=y
CONFIG_SND_SOC_ROCKCHIP_VAD=y
CONFIG_SND_SOC_ROCKCHIP_MAX98090=y
CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
CONFIG_SND_SOC_ROCKCHIP_RT5645=y
CONFIG_SND_SOC_ROCKCHIP_HDMI=y
CONFIG_SND_SOC_RK3288_HDMI_ANALOG=y
CONFIG_SND_SOC_RK3399_GRU_SOUND=y
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set

#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support

# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# CONFIG_SND_SOC_XTFPGA_I2S is not set
# CONFIG_ZX_TDM is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
CONFIG_SND_SOC_AC97_CODEC=y
CONFIG_SND_SOC_ADAU_UTILS=y
CONFIG_SND_SOC_ADAU1701=y
CONFIG_SND_SOC_ADAU17X1=y
CONFIG_SND_SOC_ADAU1761=y
CONFIG_SND_SOC_ADAU1761_I2C=y
CONFIG_SND_SOC_ADAU1761_SPI=y
CONFIG_SND_SOC_ADAU7002=y
CONFIG_SND_SOC_ADAU7118=y
CONFIG_SND_SOC_ADAU7118_HW=y
CONFIG_SND_SOC_ADAU7118_I2C=y
CONFIG_SND_SOC_AK4104=y
CONFIG_SND_SOC_AK4118=y
CONFIG_SND_SOC_AK4458=y
CONFIG_SND_SOC_AK4554=y
CONFIG_SND_SOC_AK4613=y
CONFIG_SND_SOC_AK4642=y
CONFIG_SND_SOC_AK5386=y
CONFIG_SND_SOC_AK5558=y
CONFIG_SND_SOC_ALC5623=y
CONFIG_SND_SOC_BD28623=y
CONFIG_SND_SOC_BT_SCO=y
CONFIG_SND_SOC_CS35L32=y
CONFIG_SND_SOC_CS35L33=y
CONFIG_SND_SOC_CS35L34=y
CONFIG_SND_SOC_CS35L35=y
CONFIG_SND_SOC_CS35L36=y
CONFIG_SND_SOC_CS42L42=y
CONFIG_SND_SOC_CS42L51=y
CONFIG_SND_SOC_CS42L51_I2C=y
CONFIG_SND_SOC_CS42L52=y
CONFIG_SND_SOC_CS42L56=y
CONFIG_SND_SOC_CS42L73=y
CONFIG_SND_SOC_CS4234=y
CONFIG_SND_SOC_CS4265=y
CONFIG_SND_SOC_CS4270=y
CONFIG_SND_SOC_CS4271=y
CONFIG_SND_SOC_CS4271_I2C=y
CONFIG_SND_SOC_CS4271_SPI=y
CONFIG_SND_SOC_CS42XX8=y
CONFIG_SND_SOC_CS42XX8_I2C=y
CONFIG_SND_SOC_CS43130=y
CONFIG_SND_SOC_CS4341=y
CONFIG_SND_SOC_CS4349=y
CONFIG_SND_SOC_CS53L30=y
CONFIG_SND_SOC_CX2072X=y
CONFIG_SND_SOC_DA7213=y
CONFIG_SND_SOC_DA7219=y
CONFIG_SND_SOC_DMIC=y
CONFIG_SND_SOC_DUMMY_CODEC=y
CONFIG_SND_SOC_HDMI_CODEC=y
CONFIG_SND_SOC_ES7134=y
CONFIG_SND_SOC_ES7202=y
CONFIG_SND_SOC_ES7202_MIC_MAX_CHANNELS=2
CONFIG_SND_SOC_ES7202_I2C_BUS=1
CONFIG_SND_SOC_ES7210=y
CONFIG_SND_SOC_ES7241=y
CONFIG_SND_SOC_ES7243E=y
CONFIG_SND_SOC_ES8311=y
CONFIG_SND_SOC_ES8316=y
CONFIG_SND_SOC_ES8323=y
CONFIG_SND_SOC_ES8326=y
CONFIG_SND_SOC_ES8328=y
CONFIG_SND_SOC_ES8328_I2C=y
CONFIG_SND_SOC_ES8328_SPI=y
CONFIG_SND_SOC_ES8396=y
CONFIG_SND_SOC_GTM601=y
CONFIG_SND_SOC_INNO_RK3036=y
CONFIG_SND_SOC_MAX98088=y
CONFIG_SND_SOC_MAX98090=y
CONFIG_SND_SOC_MAX98357A=y
CONFIG_SND_SOC_MAX98504=y
CONFIG_SND_SOC_MAX9867=y
CONFIG_SND_SOC_MAX98927=y
CONFIG_SND_SOC_MAX98373=y
CONFIG_SND_SOC_MAX98373_I2C=y
CONFIG_SND_SOC_MAX98390=y
CONFIG_SND_SOC_MAX9860=y
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y
CONFIG_SND_SOC_PCM1681=y
CONFIG_SND_SOC_PCM1789=y
CONFIG_SND_SOC_PCM1789_I2C=y
CONFIG_SND_SOC_PCM179X=y
CONFIG_SND_SOC_PCM179X_I2C=y
CONFIG_SND_SOC_PCM179X_SPI=y
CONFIG_SND_SOC_PCM186X=y
CONFIG_SND_SOC_PCM186X_I2C=y
CONFIG_SND_SOC_PCM186X_SPI=y
CONFIG_SND_SOC_PCM3060=y
CONFIG_SND_SOC_PCM3060_I2C=y
CONFIG_SND_SOC_PCM3060_SPI=y
CONFIG_SND_SOC_PCM3168A=y
CONFIG_SND_SOC_PCM3168A_I2C=y
CONFIG_SND_SOC_PCM3168A_SPI=y
CONFIG_SND_SOC_PCM512x=y
CONFIG_SND_SOC_PCM512x_I2C=y
CONFIG_SND_SOC_PCM512x_SPI=y
CONFIG_SND_SOC_RK1000=m
CONFIG_SND_SOC_RK312X=y
CONFIG_SND_SOC_RK3228=y
CONFIG_SND_SOC_RK3308=y
CONFIG_SND_SOC_RK3328=y
CONFIG_SND_SOC_RK3528=y
CONFIG_SND_SOC_RK730=y
CONFIG_SND_SOC_RK817=y
CONFIG_SND_SOC_RK_CODEC_DIGITAL=y
CONFIG_SND_SOC_RK_DSM=y
CONFIG_SND_SOC_RL6231=y
CONFIG_SND_SOC_RT5514=y
CONFIG_SND_SOC_RT5514_SPI=y
CONFIG_SND_SOC_RT5616=y
CONFIG_SND_SOC_RT5631=y
CONFIG_SND_SOC_RT5640=y
CONFIG_SND_SOC_RT5645=y
CONFIG_SND_SOC_RT5651=y
CONFIG_SND_SOC_RV1106=y
CONFIG_SND_SOC_SGTL5000=y
CONFIG_SND_SOC_SIGMADSP=y
CONFIG_SND_SOC_SIGMADSP_I2C=y
CONFIG_SND_SOC_SIGMADSP_REGMAP=y
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
CONFIG_SND_SOC_SIRF_AUDIO_CODEC=y
CONFIG_SND_SOC_SPDIF=y
CONFIG_SND_SOC_SSM2305=y
CONFIG_SND_SOC_SSM2602=y
CONFIG_SND_SOC_SSM2602_SPI=y
CONFIG_SND_SOC_SSM2602_I2C=y
CONFIG_SND_SOC_SSM4567=y
CONFIG_SND_SOC_STA32X=y
CONFIG_SND_SOC_STA350=y
CONFIG_SND_SOC_STI_SAS=y
CONFIG_SND_SOC_TAS2552=y
CONFIG_SND_SOC_TAS2562=y
CONFIG_SND_SOC_TAS2764=y
CONFIG_SND_SOC_TAS2770=y
CONFIG_SND_SOC_TAS5086=y
CONFIG_SND_SOC_TAS571X=y
CONFIG_SND_SOC_TAS5720=y
CONFIG_SND_SOC_TAS6424=y
CONFIG_SND_SOC_TDA7419=y
CONFIG_SND_SOC_TDA7803=y
CONFIG_SND_SOC_TFA9879=y
CONFIG_SND_SOC_TLV320AIC23=y
CONFIG_SND_SOC_TLV320AIC23_I2C=y
CONFIG_SND_SOC_TLV320AIC23_SPI=y
CONFIG_SND_SOC_TLV320AIC31XX=y
CONFIG_SND_SOC_TLV320AIC32X4=y
CONFIG_SND_SOC_TLV320AIC32X4_I2C=y
CONFIG_SND_SOC_TLV320AIC32X4_SPI=y
CONFIG_SND_SOC_TLV320AIC3X=y
CONFIG_SND_SOC_TLV320ADCX140=y
CONFIG_SND_SOC_TS3A227E=y
CONFIG_SND_SOC_TSCS42XX=y
CONFIG_SND_SOC_TSCS454=y
CONFIG_SND_SOC_UDA1334=y
CONFIG_SND_SOC_WM8510=y
CONFIG_SND_SOC_WM8523=y
CONFIG_SND_SOC_WM8524=y
CONFIG_SND_SOC_WM8580=y
CONFIG_SND_SOC_WM8711=y
CONFIG_SND_SOC_WM8728=y
CONFIG_SND_SOC_WM8731=y
CONFIG_SND_SOC_WM8737=y
CONFIG_SND_SOC_WM8741=y
CONFIG_SND_SOC_WM8750=y
CONFIG_SND_SOC_WM8753=y
CONFIG_SND_SOC_WM8770=y
CONFIG_SND_SOC_WM8776=y
CONFIG_SND_SOC_WM8782=y
CONFIG_SND_SOC_WM8804=y
CONFIG_SND_SOC_WM8804_I2C=y
CONFIG_SND_SOC_WM8804_SPI=y
CONFIG_SND_SOC_WM8903=y
CONFIG_SND_SOC_WM8904=y
CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SOC_WM8962=y
CONFIG_SND_SOC_WM8974=y
CONFIG_SND_SOC_WM8978=y
CONFIG_SND_SOC_WM8985=y
CONFIG_SND_SOC_ZL38060=y
CONFIG_SND_SOC_ZX_AUD96P22=y
CONFIG_SND_SOC_MAX9759=y
CONFIG_SND_SOC_MT6351=y
CONFIG_SND_SOC_MT6358=y
CONFIG_SND_SOC_MT6660=y
CONFIG_SND_SOC_NAU8540=y
CONFIG_SND_SOC_NAU8810=y
CONFIG_SND_SOC_NAU8822=y
CONFIG_SND_SOC_NAU8824=y
CONFIG_SND_SOC_TPA6130A2=y
CONFIG_SND_SOC_AW87XXX=m
CONFIG_SND_SOC_AW883XX=m
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD=y
CONFIG_AC97_BUS=y

#
# HID support
#
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=m
CONFIG_HID_GENERIC=m

#
# Special HID drivers
#
CONFIG_HID_A4TECH=m
CONFIG_HID_ACCUTOUCH=m
CONFIG_HID_ACRUX=m
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=m
CONFIG_HID_APPLEIR=m
CONFIG_HID_ASUS=m
CONFIG_HID_AUREAL=m
CONFIG_HID_BELKIN=m
CONFIG_HID_BETOP_FF=m
CONFIG_HID_BIGBEN_FF=m
CONFIG_HID_CHERRY=m
CONFIG_HID_CHICONY=m
CONFIG_HID_CORSAIR=m
CONFIG_HID_COUGAR=m
CONFIG_HID_MACALLY=m
CONFIG_HID_PRODIKEYS=m
CONFIG_HID_CMEDIA=m
CONFIG_HID_CP2112=m
CONFIG_HID_CREATIVE_SB0540=m
CONFIG_HID_CYPRESS=m
CONFIG_HID_DRAGONRISE=m
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=m
CONFIG_HID_ELAN=m
CONFIG_HID_ELECOM=m
CONFIG_HID_ELO=m
CONFIG_HID_EZKEY=m
CONFIG_HID_GEMBIRD=m
CONFIG_HID_GFRM=m
CONFIG_HID_GLORIOUS=m
CONFIG_HID_HOLTEK=m
CONFIG_HOLTEK_FF=y
CONFIG_HID_VIVALDI=m
CONFIG_HID_GT683R=m
CONFIG_HID_KEYTOUCH=m
CONFIG_HID_KYE=m
CONFIG_HID_UCLOGIC=m
CONFIG_HID_WALTOP=m
CONFIG_HID_VIEWSONIC=m
CONFIG_HID_GYRATION=m
CONFIG_HID_ICADE=m
CONFIG_HID_ITE=m
CONFIG_HID_JABRA=m
CONFIG_HID_TWINHAN=m
CONFIG_HID_KENSINGTON=m
CONFIG_HID_LCPOWER=m
CONFIG_HID_LED=m
CONFIG_HID_LENOVO=m
CONFIG_HID_LOGITECH=m
CONFIG_HID_LOGITECH_DJ=m
CONFIG_HID_LOGITECH_HIDPP=m
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
CONFIG_HID_MAGICMOUSE=m
CONFIG_HID_MALTRON=m
CONFIG_HID_MAYFLASH=m
CONFIG_HID_REDRAGON=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
CONFIG_HID_MULTITOUCH=m
CONFIG_HID_NINTENDO=m
CONFIG_HID_NTI=m
CONFIG_HID_NTRIG=m
CONFIG_HID_ORTEK=m
CONFIG_HID_PANTHERLORD=m
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PENMOUNT=m
CONFIG_HID_PETALYNX=m
CONFIG_HID_PICOLCD=m
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
CONFIG_HID_PICOLCD_LEDS=y
CONFIG_HID_PICOLCD_CIR=y
CONFIG_HID_PLANTRONICS=m
CONFIG_HID_PLAYSTATION=m
CONFIG_PLAYSTATION_FF=y
CONFIG_HID_PRIMAX=m
CONFIG_HID_RETRODE=m
CONFIG_HID_ROCCAT=m
CONFIG_HID_SAITEK=m
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SONY=m
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=m
CONFIG_HID_STEAM=m
CONFIG_HID_STEELSERIES=m
CONFIG_HID_SUNPLUS=m
CONFIG_HID_RMI=m
CONFIG_HID_GREENASIA=m
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=m
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TIVO=m
CONFIG_HID_TOPSEED=m
CONFIG_HID_THINGM=m
CONFIG_HID_THRUSTMASTER=m
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_UDRAW_PS3=m
CONFIG_HID_U2FZERO=m
CONFIG_HID_WACOM=m
CONFIG_HID_WIIMOTE=m
CONFIG_HID_XINMO=m
CONFIG_HID_ZEROPLUS=m
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=m
CONFIG_HID_SENSOR_HUB=m
CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
CONFIG_HID_ALPS=m
CONFIG_HID_MCP2221=m
# end of Special HID drivers

#
# USB HID support
#
CONFIG_USB_HID=y
# CONFIG_HID_PID is not set
CONFIG_USB_HIDDEV=y
# end of USB HID support

#
# I2C HID support
#
CONFIG_I2C_HID=y
# end of I2C HID support
# end of HID support

CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
# CONFIG_USB_LED_TRIG is not set
# CONFIG_USB_ULPI_BUS is not set
# CONFIG_USB_CONN_GPIO is not set
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
CONFIG_USB_OTG_FSM=y
# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=m

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=y
# CONFIG_USB_XHCI_PCI_RENESAS is not set
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
# CONFIG_USB_EHCI_FSL is not set
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OXU210HP_HCD=m
CONFIG_USB_ISP116X_HCD=m
CONFIG_USB_FOTG210_HCD=m
CONFIG_USB_MAX3421_HCD=m
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PCI=m
CONFIG_USB_OHCI_HCD_PLATFORM=y
# CONFIG_USB_UHCI_HCD is not set
CONFIG_USB_U132_HCD=m
CONFIG_USB_SL811_HCD=m
# CONFIG_USB_SL811_HCD_ISO is not set
CONFIG_USB_R8A66597_HCD=m
CONFIG_USB_HCD_BCMA=m
CONFIG_USB_HCD_SSB=m
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=y
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=m
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
CONFIG_USB_STORAGE_REALTEK=m
CONFIG_REALTEK_AUTOPM=y
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_FREECOM=m
CONFIG_USB_STORAGE_ISD200=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_STORAGE_ALAUDA=m
CONFIG_USB_STORAGE_ONETOUCH=m
CONFIG_USB_STORAGE_KARMA=m
CONFIG_USB_STORAGE_CYPRESS_ATACB=m
CONFIG_USB_STORAGE_ENE_UB6250=m
CONFIG_USB_UAS=y

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
CONFIG_USB_MICROTEK=m
CONFIG_USBIP_CORE=m
CONFIG_USBIP_VHCI_HCD=m
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=m
CONFIG_USBIP_VUDC=m
CONFIG_USBIP_DEBUG=y
CONFIG_USB_CDNS3=m
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_USB_CDNS3_PCI_WRAP=m
CONFIG_USB_MUSB_HDRC=m
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y

#
# Platform Glue Layer
#

#
# MUSB DMA mode
#
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y

#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=y
CONFIG_USB_DWC3_HAPS=y
CONFIG_USB_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC3_ROCKCHIP_INNO=y
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
CONFIG_USB_DWC2_PCI=m
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
# CONFIG_USB_CHIPIDEA is not set
# CONFIG_USB_ISP1760 is not set

#
# USB port drivers
#
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=y
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=y
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=y
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=y
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=y
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_F81232=m
CONFIG_USB_SERIAL_F8153X=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=y
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_METRO=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MXUPORT=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=y
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=m
CONFIG_USB_SERIAL_QUALCOMM=y
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
CONFIG_USB_SERIAL_SAFE_PADDED=y
CONFIG_USB_SERIAL_SIERRAWIRELESS=y
CONFIG_USB_SERIAL_SYMBOL=y
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_XIRCOM=m
CONFIG_USB_SERIAL_WWAN=y
CONFIG_USB_SERIAL_OPTION=y
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=y
CONFIG_USB_SERIAL_XSENS_MT=m
CONFIG_USB_SERIAL_WISHBONE=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_SERIAL_QT2=y
CONFIG_USB_SERIAL_UPD78F0730=m
# CONFIG_USB_SERIAL_DEBUG is not set

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
CONFIG_USB_CYPRESS_CY7C63=m
CONFIG_USB_CYTHERM=m
CONFIG_USB_IDMOUSE=m
CONFIG_USB_FTDI_ELAN=m
CONFIG_USB_APPLEDISPLAY=m
CONFIG_APPLE_MFI_FASTCHARGE=m
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
CONFIG_USB_TEST=m
CONFIG_USB_EHSET_TEST_FIXTURE=m
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=y
CONFIG_USB_HUB_USB251XB=m
CONFIG_USB_HSIC_USB3503=m
CONFIG_USB_HSIC_USB4604=m
CONFIG_USB_LINK_LAYER_TEST=m
CONFIG_USB_CHAOSKEY=m
# CONFIG_USB_ONBOARD_HUB is not set
CONFIG_USB_ATM=m
CONFIG_USB_SPEEDTOUCH=m
CONFIG_USB_CXACRU=m
CONFIG_USB_UEAGLEATM=m
CONFIG_USB_XUSBATM=m

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=m
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_ULPI is not set
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
CONFIG_USB_GADGET_DEBUG_FILES=y
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set

#
# USB Peripheral Controller
#
# CONFIG_USB_FOTG210_UDC is not set
# CONFIG_USB_GR_UDC is not set
# CONFIG_USB_R8A66597 is not set
# CONFIG_USB_PXA27X is not set
# CONFIG_USB_MV_UDC is not set
# CONFIG_USB_MV_U3D is not set
# CONFIG_USB_SNP_UDC_PLAT is not set
# CONFIG_USB_M66592 is not set
# CONFIG_USB_BDC_UDC is not set
# CONFIG_USB_AMD5536UDC is not set
# CONFIG_USB_NET2272 is not set
# CONFIG_USB_NET2280 is not set
# CONFIG_USB_GOKU is not set
# CONFIG_USB_EG20T is not set
# CONFIG_USB_GADGET_XILINX is not set
# CONFIG_USB_MAX3420_UDC is not set
# CONFIG_USB_DUMMY_HCD is not set
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_F_ACM=y
CONFIG_USB_F_SS_LB=y
CONFIG_USB_U_SERIAL=y
CONFIG_USB_U_ETHER=y
CONFIG_USB_U_AUDIO=y
CONFIG_USB_F_SERIAL=m
CONFIG_USB_F_OBEX=y
CONFIG_USB_F_NCM=y
CONFIG_USB_F_ECM=y
CONFIG_USB_F_EEM=y
CONFIG_USB_F_SUBSET=y
CONFIG_USB_F_RNDIS=y
CONFIG_USB_F_MASS_STORAGE=y
CONFIG_USB_F_FS=y
CONFIG_USB_F_UAC1=y
CONFIG_USB_F_UAC1_LEGACY=y
CONFIG_USB_F_UAC2=y
CONFIG_USB_F_UVC=y
CONFIG_USB_F_MIDI=y
CONFIG_USB_F_HID=y
CONFIG_USB_F_PRINTER=y
CONFIG_USB_F_ACC=y
CONFIG_USB_F_AUDIO_SRC=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_UEVENT=y
# CONFIG_USB_CONFIGFS_SERIAL is not set
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_LB_SS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_ACC=y
CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y

#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=m
# CONFIG_USB_ZERO_HNPTEST is not set
CONFIG_USB_AUDIO=m
# CONFIG_GADGET_UAC1 is not set
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
# CONFIG_USB_ETH_EEM is not set
CONFIG_USB_G_NCM=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
# CONFIG_USB_FUNCTIONFS_ETH is not set
# CONFIG_USB_FUNCTIONFS_RNDIS is not set
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
# CONFIG_USB_G_MULTI_CDC is not set
CONFIG_USB_G_HID=m
CONFIG_USB_G_DBGP=m
# CONFIG_USB_G_DBGP_PRINTK is not set
CONFIG_USB_G_DBGP_SERIAL=y
CONFIG_USB_G_WEBCAM=m
CONFIG_USB_RAW_GADGET=m
# end of USB Gadget precomposed configurations

CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
CONFIG_TYPEC_ET7303=y
CONFIG_TYPEC_HUSB311=y
CONFIG_TYPEC_RT1711H=y
CONFIG_TYPEC_TCPCI_MAXIM=y
CONFIG_TYPEC_FUSB302=y
CONFIG_TYPEC_UCSI=m
CONFIG_UCSI_CCG=m
CONFIG_UCSI_ACPI=m
CONFIG_TYPEC_HD3SS3220=m
CONFIG_TYPEC_TPS6598X=m
CONFIG_TYPEC_STUSB160X=m

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
CONFIG_TYPEC_MUX_PI3USB30532=m
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
CONFIG_TYPEC_DP_ALTMODE=y
# CONFIG_TYPEC_NVIDIA_ALTMODE is not set
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
# CONFIG_PWRSEQ_SD8787 is not set
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_SDIO_UART is not set
CONFIG_MMC_TEST=y

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_ARMMMCI is not set
CONFIG_MMC_SDHCI=y
# CONFIG_MMC_SDHCI_PCI is not set
# CONFIG_MMC_SDHCI_ACPI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
# CONFIG_MMC_SDHCI_OF_ASPEED is not set
# CONFIG_MMC_SDHCI_OF_AT91 is not set
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
# CONFIG_MMC_SDHCI_CADENCE is not set
# CONFIG_MMC_SDHCI_F_SDH30 is not set
# CONFIG_MMC_SDHCI_MILBEAUT is not set
# CONFIG_MMC_TIFM_SD is not set
# CONFIG_MMC_SPI is not set
# CONFIG_MMC_CB710 is not set
# CONFIG_MMC_VIA_SDMMC is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
# CONFIG_MMC_DW_BLUEFIELD is not set
# CONFIG_MMC_DW_EXYNOS is not set
# CONFIG_MMC_DW_HI3798CV200 is not set
# CONFIG_MMC_DW_K3 is not set
# CONFIG_MMC_DW_PCI is not set
CONFIG_MMC_DW_ROCKCHIP=y
# CONFIG_MMC_VUB300 is not set
# CONFIG_MMC_USHC is not set
# CONFIG_MMC_USDHI6ROL0 is not set
# CONFIG_MMC_REALTEK_USB is not set
CONFIG_MMC_CQHCI=y
CONFIG_MMC_HSQ=y
# CONFIG_MMC_TOSHIBA_PCI is not set
# CONFIG_MMC_MTK is not set
# CONFIG_MMC_SDHCI_XENON is not set
# CONFIG_MMC_SDHCI_OMAP is not set
# CONFIG_MMC_SDHCI_AM654 is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
CONFIG_LEDS_CLASS_MULTICOLOR=y
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y

#
# LED drivers
#
CONFIG_LEDS_AAT1290=m
CONFIG_LEDS_AN30259A=m
CONFIG_LEDS_AS3645A=m
CONFIG_LEDS_AW2013=m
CONFIG_LEDS_BCM6328=m
CONFIG_LEDS_BCM6358=m
CONFIG_LEDS_CR0014114=m
CONFIG_LEDS_EL15203000=m
CONFIG_LEDS_LM3530=m
CONFIG_LEDS_LM3532=m
CONFIG_LEDS_LM3642=m
CONFIG_LEDS_LM3692X=y
CONFIG_LEDS_LM3601X=y
CONFIG_LEDS_PCA9532=m
CONFIG_LEDS_PCA9532_GPIO=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=m
CONFIG_LEDS_LP3952=m
CONFIG_LEDS_LP50XX=m
CONFIG_LEDS_LP55XX_COMMON=m
CONFIG_LEDS_LP5521=m
CONFIG_LEDS_LP5523=m
CONFIG_LEDS_LP5562=m
CONFIG_LEDS_LP8501=m
CONFIG_LEDS_LP8860=m
CONFIG_LEDS_PCA955X=m
CONFIG_LEDS_PCA955X_GPIO=y
CONFIG_LEDS_PCA963X=m
CONFIG_LEDS_DAC124S085=m
CONFIG_LEDS_PWM=y
CONFIG_LEDS_REGULATOR=y
CONFIG_LEDS_BD2802=m
CONFIG_LEDS_LT3593=m
CONFIG_LEDS_TCA6507=m
CONFIG_LEDS_TLC591XX=m
CONFIG_LEDS_LM355x=m
CONFIG_LEDS_KTD2692=m
CONFIG_LEDS_IS31FL319X=m
CONFIG_LEDS_IS31FL32XX=m
CONFIG_LEDS_RGB13H=m

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=m
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_MLXREG=m
CONFIG_LEDS_USER=y
CONFIG_LEDS_SPI_BYTE=m
CONFIG_LEDS_TI_LMU_COMMON=m
CONFIG_LEDS_LM3697=m
CONFIG_LEDS_SGM3140=m

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
# CONFIG_LEDS_TRIGGER_MTD is not set
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
# CONFIG_LEDS_TRIGGER_CPU is not set
# CONFIG_LEDS_TRIGGER_ACTIVITY is not set
# CONFIG_LEDS_TRIGGER_GPIO is not set
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=y
# CONFIG_LEDS_TRIGGER_PATTERN is not set
# CONFIG_LEDS_TRIGGER_AUDIO is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
CONFIG_RTC_DRV_TEST=m

#
# I2C RTC drivers
#
CONFIG_RTC_DRV_ABB5ZES3=m
CONFIG_RTC_DRV_ABEOZ9=m
CONFIG_RTC_DRV_ABX80X=m
CONFIG_RTC_DRV_DS1307=m
CONFIG_RTC_DRV_DS1307_CENTURY=y
CONFIG_RTC_DRV_DS1374=m
CONFIG_RTC_DRV_DS1374_WDT=y
CONFIG_RTC_DRV_DS1672=m
CONFIG_RTC_DRV_HYM8563=y
CONFIG_RTC_DRV_MAX6900=m
CONFIG_RTC_DRV_RK808=y
CONFIG_RTC_DRV_ROCKCHIP=y
CONFIG_RTC_DRV_RS5C372=m
CONFIG_RTC_DRV_ISL1208=m
CONFIG_RTC_DRV_ISL12022=m
CONFIG_RTC_DRV_ISL12026=m
CONFIG_RTC_DRV_X1205=m
CONFIG_RTC_DRV_PCF8523=m
CONFIG_RTC_DRV_PCF85063=m
CONFIG_RTC_DRV_PCF85363=m
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_PCF8583=m
CONFIG_RTC_DRV_M41T80=m
CONFIG_RTC_DRV_M41T80_WDT=y
CONFIG_RTC_DRV_BQ32K=m
CONFIG_RTC_DRV_TPS6586X=m
CONFIG_RTC_DRV_S35390A=m
CONFIG_RTC_DRV_FM3130=m
CONFIG_RTC_DRV_RX8010=m
CONFIG_RTC_DRV_RX8581=m
CONFIG_RTC_DRV_RX8025=m
CONFIG_RTC_DRV_EM3027=m
CONFIG_RTC_DRV_RV3028=m
CONFIG_RTC_DRV_RV3032=m
CONFIG_RTC_DRV_RV8803=m
CONFIG_RTC_DRV_SD3078=m

#
# SPI RTC drivers
#
CONFIG_RTC_DRV_M41T93=m
CONFIG_RTC_DRV_M41T94=m
CONFIG_RTC_DRV_DS1302=m
CONFIG_RTC_DRV_DS1305=m
CONFIG_RTC_DRV_DS1343=m
CONFIG_RTC_DRV_DS1347=m
CONFIG_RTC_DRV_DS1390=m
CONFIG_RTC_DRV_MAX6916=m
CONFIG_RTC_DRV_R9701=m
CONFIG_RTC_DRV_RX4581=m
CONFIG_RTC_DRV_RX6110=m
CONFIG_RTC_DRV_RS5C348=m
CONFIG_RTC_DRV_MAX6902=m
CONFIG_RTC_DRV_PCF2123=m
CONFIG_RTC_DRV_MCP795=m
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
CONFIG_RTC_DRV_DS3232=m
CONFIG_RTC_DRV_DS3232_HWMON=y
CONFIG_RTC_DRV_PCF2127=m
CONFIG_RTC_DRV_RV3029C2=m
CONFIG_RTC_DRV_RV3029_HWMON=y

#
# Platform RTC drivers
#
CONFIG_RTC_DRV_DS1286=m
CONFIG_RTC_DRV_DS1511=m
CONFIG_RTC_DRV_DS1553=m
CONFIG_RTC_DRV_DS1685_FAMILY=m
CONFIG_RTC_DRV_DS1685=y
# CONFIG_RTC_DRV_DS1689 is not set
# CONFIG_RTC_DRV_DS17285 is not set
# CONFIG_RTC_DRV_DS17485 is not set
# CONFIG_RTC_DRV_DS17885 is not set
CONFIG_RTC_DRV_DS1742=m
CONFIG_RTC_DRV_DS2404=m
CONFIG_RTC_DRV_EFI=m
CONFIG_RTC_DRV_STK17TA8=m
CONFIG_RTC_DRV_M48T86=m
CONFIG_RTC_DRV_M48T35=m
CONFIG_RTC_DRV_M48T59=m
CONFIG_RTC_DRV_MSM6242=m
CONFIG_RTC_DRV_BQ4802=m
CONFIG_RTC_DRV_RP5C01=m
CONFIG_RTC_DRV_V3020=m
CONFIG_RTC_DRV_ZYNQMP=m

#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_PL030=y
CONFIG_RTC_DRV_PL031=y
CONFIG_RTC_DRV_CADENCE=m
CONFIG_RTC_DRV_FTRTC010=m
CONFIG_RTC_DRV_R7301=m

#
# HID Sensor RTC drivers
#
CONFIG_RTC_DRV_HID_SENSOR_TIME=m
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
CONFIG_AMBA_PL08X=y
# CONFIG_BCM_SBA_RAID is not set
CONFIG_DW_AXI_DMAC=m
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_HISI_DMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_MV_XOR_V2 is not set
CONFIG_PL330_DMA=y
# CONFIG_PLX_DMA is not set
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
# CONFIG_XILINX_ZYNQMP_DPDMA is not set
# CONFIG_QCOM_HIDMA_MGMT is not set
# CONFIG_QCOM_HIDMA is not set
# CONFIG_DW_DMAC is not set
# CONFIG_DW_DMAC_PCI is not set
# CONFIG_DW_EDMA is not set
# CONFIG_DW_EDMA_PCIE is not set
# CONFIG_SF_PDMA is not set

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set

#
# DMABUF options
#
CONFIG_DMABUF_CACHE=y
# CONFIG_RK_DMABUF_DEBUG is not set
CONFIG_DMABUF_PARTIAL=y
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_SW_SYNC_DEBUG=y
# CONFIG_UDMABUF is not set
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_SELFTESTS is not set
CONFIG_DMABUF_HEAPS=y
CONFIG_DMABUF_SYSFS_STATS=y
CONFIG_DMABUF_HEAPS_DEFERRED_FREE=y
CONFIG_DMABUF_HEAPS_PAGE_POOL=y
CONFIG_DMABUF_HEAPS_SYSTEM=y
CONFIG_DMABUF_HEAPS_CMA=y
# CONFIG_DMABUF_HEAPS_SRAM is not set
# CONFIG_DMABUF_HEAPS_ROCKCHIP is not set
# end of DMABUF options

CONFIG_AUXDISPLAY=y
CONFIG_HD44780=m
CONFIG_IMG_ASCII_LCD=m
CONFIG_HT16K33=m
# CONFIG_PANEL_CHANGE_MESSAGE is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_CHARLCD=m
CONFIG_UIO=m
# CONFIG_UIO_CIF is not set
# CONFIG_UIO_PDRV_GENIRQ is not set
# CONFIG_UIO_DMEM_GENIRQ is not set
# CONFIG_UIO_AEC is not set
# CONFIG_UIO_SERCOS3 is not set
# CONFIG_UIO_PCI_GENERIC is not set
# CONFIG_UIO_NETX is not set
# CONFIG_UIO_PRUSS is not set
# CONFIG_UIO_MF624 is not set
# CONFIG_VFIO is not set
CONFIG_VIRT_DRIVERS=y
CONFIG_VIRTIO=m
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=m
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
# CONFIG_VDPA is not set
CONFIG_VHOST_IOTLB=m
CONFIG_VHOST=m
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_VSOCK=m
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set

#
# Microsoft Hyper-V guest support
#
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
CONFIG_STAGING=y
# CONFIG_PRISM2_USB is not set
# CONFIG_COMEDI is not set
CONFIG_RTL8192U=m
CONFIG_RTLLIB=m
CONFIG_RTLLIB_CRYPTO_CCMP=m
CONFIG_RTLLIB_CRYPTO_TKIP=m
CONFIG_RTLLIB_CRYPTO_WEP=m
CONFIG_RTL8192E=m
CONFIG_R8712U=m
CONFIG_RTS5208=m
CONFIG_VT6655=m
CONFIG_VT6656=m

#
# IIO staging drivers
#

#
# Accelerometers
#
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16240 is not set
# end of Accelerometers

#
# Analog to digital converters
#
# CONFIG_AD7816 is not set
# CONFIG_AD7280 is not set
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
# CONFIG_ADT7316 is not set
# end of Analog digital bi-direction converters

#
# Capacitance to digital converters
#
# CONFIG_AD7150 is not set
# CONFIG_AD7746 is not set
# end of Capacitance to digital converters

#
# Direct Digital Synthesis
#
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
# CONFIG_AD5933 is not set
# end of Network Analyzer, Impedance Converters

#
# Active energy metering IC
#
# CONFIG_ADE7854 is not set
# end of Active energy metering IC

#
# Resolver to digital converters
#
# CONFIG_AD2S1210 is not set
# end of Resolver to digital converters
# end of IIO staging drivers

# CONFIG_FB_SM750 is not set
CONFIG_STAGING_MEDIA=y
# CONFIG_VIDEO_HANTRO is not set
CONFIG_VIDEO_ROCKCHIP_VDEC=y
# CONFIG_VIDEO_ZORAN is not set
CONFIG_VIDEO_ROCKCHIP_ISP1=y

#
# Android
#
# CONFIG_ASHMEM is not set
# CONFIG_DEBUG_KINFO is not set
# CONFIG_ION is not set
# end of Android

# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
# CONFIG_GS_FPGABOOT is not set
# CONFIG_UNISYSSPAR is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
# CONFIG_FB_TFT is not set
# CONFIG_KS7010 is not set
# CONFIG_PI433 is not set

#
# Gasket devices
#
# CONFIG_STAGING_GASKET_FRAMEWORK is not set
# end of Gasket devices

# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_KPC2000 is not set
# CONFIG_QLGE is not set
# CONFIG_WFX is not set
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
CONFIG_HAVE_CLK=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
# CONFIG_COMMON_CLK_PROCFS is not set

#
# Clock driver for ARM Reference designs
#
# CONFIG_ICST is not set
# CONFIG_CLK_SP810 is not set
# end of Clock driver for ARM Reference designs

# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
# CONFIG_CLK_QORIQ is not set
# CONFIG_COMMON_CLK_XGENE is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
CONFIG_COMMON_CLK_ROCKCHIP=y
CONFIG_CLK_PX30=y
CONFIG_CLK_RK1808=y
CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
CONFIG_CLK_RK3399=y
CONFIG_CLK_RK3528=y
CONFIG_CLK_RK3562=y
CONFIG_CLK_RK3568=y
CONFIG_CLK_RK3588=y
# CONFIG_ROCKCHIP_CLK_COMPENSATION is not set
CONFIG_ROCKCHIP_CLK_LINK=y
CONFIG_ROCKCHIP_CLK_BOOST=y
CONFIG_ROCKCHIP_CLK_INV=y
CONFIG_ROCKCHIP_CLK_OUT=y
CONFIG_ROCKCHIP_CLK_PVTM=y
CONFIG_ROCKCHIP_DDRCLK=y
CONFIG_ROCKCHIP_DDRCLK_SIP=y
CONFIG_ROCKCHIP_DDRCLK_SIP_V2=y
CONFIG_ROCKCHIP_PLL_RK3066=y
CONFIG_ROCKCHIP_PLL_RK3399=y
CONFIG_ROCKCHIP_PLL_RK3588=y
# CONFIG_HWSPINLOCK is not set

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_ACPI=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_ROCKCHIP_TIMER=y
# CONFIG_SUN4I_TIMER is not set
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
# CONFIG_MTK_TIMER is not set
# CONFIG_MICROCHIP_PIT64B is not set
# end of Clock Source drivers

CONFIG_MAILBOX=y
# CONFIG_ARM_MHU is not set
# CONFIG_PLATFORM_MHU is not set
# CONFIG_PL320_MBOX is not set
CONFIG_ROCKCHIP_MBOX=y
# CONFIG_ROCKCHIP_MBOX_DEMO is not set
CONFIG_PCC=y
# CONFIG_ALTERA_MBOX is not set
# CONFIG_MAILBOX_TEST is not set
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
# CONFIG_IOMMU_LIMIT_IOVA_ALIGNMENT is not set
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set
CONFIG_ARM_SMMU_V3=y
CONFIG_ARM_SMMU_V3_SVA=y
CONFIG_VIRTIO_IOMMU=m

#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=m
CONFIG_RPMSG_CHAR=m
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
CONFIG_RPMSG_ROCKCHIP=m
# CONFIG_RPMSG_ROCKCHIP_TEST is not set
CONFIG_RPMSG_VIRTIO=m
# end of Rpmsg drivers

# CONFIG_SOUNDWIRE is not set

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
# end of Amlogic SoC drivers

#
# Aspeed SoC drivers
#
# end of Aspeed SoC drivers

#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
# CONFIG_QUICC_ENGINE is not set
# CONFIG_FSL_RCPM is not set
# end of NXP/Freescale QorIQ SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Qualcomm SoC drivers
#
CONFIG_QCOM_QMI_HELPERS=m
# end of Qualcomm SoC drivers

#
# Rockchip SoC drivers
#

#
# Rockchip CPU selection
#
CONFIG_CPU_PX30=y
CONFIG_CPU_RK1808=y
CONFIG_CPU_RK3308=y
CONFIG_CPU_RK3328=y
CONFIG_CPU_RK3368=y
CONFIG_CPU_RK3399=y
CONFIG_CPU_RK3528=y
CONFIG_CPU_RK3562=y
CONFIG_CPU_RK3568=y
CONFIG_CPU_RK3588=y
# end of Rockchip CPU selection

CONFIG_NO_GKI=y
CONFIG_ROCKCHIP_AMP=m
CONFIG_ROCKCHIP_ARM64_ALIGN_FAULT_FIX=y
CONFIG_ROCKCHIP_CPUINFO=y
CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_ROCKCHIP_HW_DECOMPRESS_USER=y
CONFIG_ROCKCHIP_IODOMAIN=y
# CONFIG_ROCKCHIP_IOMUX is not set
CONFIG_ROCKCHIP_IPA=y
CONFIG_ROCKCHIP_OPP=y
# CONFIG_ROCKCHIP_OPTIMIZE_RT_PRIO is not set
CONFIG_ROCKCHIP_PERFORMANCE=y
CONFIG_ROCKCHIP_PERFORMANCE_LEVEL=2
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ROCKCHIP_PVTM=y
# CONFIG_ROCKCHIP_RAMDISK is not set
# CONFIG_ROCKCHIP_SUSPEND_MODE is not set
CONFIG_ROCKCHIP_SYSTEM_MONITOR=y
CONFIG_ROCKCHIP_VENDOR_STORAGE=y
CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE=y
CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=y
CONFIG_ROCKCHIP_RAM_VENDOR_STORAGE=y
CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER=y

#
# FIQ Debugger
#
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
# CONFIG_FIQ_DEBUGGER_WAKEUP_IRQ_ALWAYS_ON is not set
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y
# CONFIG_FIQ_DEBUGGER_UART_OVERLAY is not set
CONFIG_RK_CONSOLE_THREAD=y
CONFIG_ROCKCHIP_FIQ_DEBUGGER=y
# end of FIQ Debugger

CONFIG_ROCKCHIP_DEBUG=y
# CONFIG_ROCKCHIP_MINI_KERNEL is not set
# CONFIG_ROCKCHIP_THUNDER_BOOT is not set
CONFIG_ROCKCHIP_NPOR_POWERGOOD=y
CONFIG_RK_CMA_PROCFS=y
CONFIG_RK_DMABUF_PROCFS=y
CONFIG_RK_MEMBLOCK_PROCFS=y

#
# Rockchip Minidump drivers
#
# CONFIG_ROCKCHIP_MINIDUMP is not set
# end of Rockchip Minidump drivers
# end of Rockchip SoC drivers

# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# CONFIG_XILINX_VCU is not set
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEVFREQ_GOV_PASSIVE=y

#
# DEVFREQ Drivers
#
CONFIG_ARM_ROCKCHIP_BUS_DEVFREQ=y
CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_NOCP=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
# CONFIG_EXTCON_ADC_JACK is not set
# CONFIG_EXTCON_FSA9480 is not set
# CONFIG_EXTCON_GPIO is not set
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_PTN5150 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
# CONFIG_EXTCON_USB_GPIO is not set
CONFIG_EXTCON_USBC_VIRTUAL_PD=y
# CONFIG_MEMORY is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
CONFIG_IIO_BUFFER_DMA=m
CONFIG_IIO_BUFFER_DMAENGINE=m
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
CONFIG_IIO_TRIGGERED_EVENT=m

#
# Accelerometers
#
CONFIG_ADIS16201=m
CONFIG_ADIS16209=m
CONFIG_ADXL372=m
CONFIG_ADXL372_SPI=m
CONFIG_ADXL372_I2C=m
CONFIG_BMA220=m
CONFIG_BMA400=m
CONFIG_BMA400_I2C=m
CONFIG_BMA400_SPI=m
CONFIG_BMC150_ACCEL=m
CONFIG_BMC150_ACCEL_I2C=m
CONFIG_BMC150_ACCEL_SPI=m
CONFIG_DA280=m
CONFIG_DA311=m
CONFIG_DMARD06=m
CONFIG_DMARD09=m
CONFIG_DMARD10=m
CONFIG_HID_SENSOR_ACCEL_3D=m
CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
CONFIG_KXSD9=m
CONFIG_KXSD9_SPI=m
CONFIG_KXSD9_I2C=m
CONFIG_KXCJK1013=m
CONFIG_MC3230=m
CONFIG_MMA7455=m
CONFIG_MMA7455_I2C=m
CONFIG_MMA7455_SPI=m
CONFIG_MMA7660=m
CONFIG_MMA8452=m
CONFIG_MMA9551_CORE=m
CONFIG_MMA9551=m
CONFIG_MMA9553=m
CONFIG_MXC4005=m
CONFIG_MXC6255=m
CONFIG_SCA3000=m
CONFIG_STK8312=m
CONFIG_STK8BA50=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=m
CONFIG_AD7091R5=m
CONFIG_AD7124=m
CONFIG_AD7192=m
CONFIG_AD7266=m
CONFIG_AD7291=m
CONFIG_AD7292=m
CONFIG_AD7298=m
CONFIG_AD7476=m
CONFIG_AD7606=m
CONFIG_AD7606_IFACE_PARALLEL=m
CONFIG_AD7606_IFACE_SPI=m
CONFIG_AD7766=m
CONFIG_AD7768_1=m
CONFIG_AD7780=m
CONFIG_AD7791=m
CONFIG_AD7793=m
CONFIG_AD7887=m
CONFIG_AD7923=m
CONFIG_AD7949=m
CONFIG_AD799X=m
CONFIG_AD9467=m
CONFIG_ADI_AXI_ADC=m
CONFIG_CC10001_ADC=m
CONFIG_ENVELOPE_DETECTOR=m
CONFIG_HI8435=m
CONFIG_HX711=m
CONFIG_INA2XX_ADC=m
CONFIG_LTC2471=m
CONFIG_LTC2485=m
CONFIG_LTC2496=m
CONFIG_LTC2497=m
CONFIG_MAX1027=m
CONFIG_MAX11100=m
CONFIG_MAX1118=m
CONFIG_MAX1241=m
CONFIG_MAX1363=m
CONFIG_MAX9611=m
CONFIG_MCP320X=m
CONFIG_MCP3422=m
CONFIG_MCP3911=m
CONFIG_NAU7802=m
CONFIG_ROCKCHIP_SARADC=y
# CONFIG_ROCKCHIP_SARADC_TEST_CHN is not set
CONFIG_SD_ADC_MODULATOR=m
CONFIG_TI_ADC081C=m
CONFIG_TI_ADC0832=m
CONFIG_TI_ADC084S021=m
CONFIG_TI_ADC12138=m
CONFIG_TI_ADC108S102=m
CONFIG_TI_ADC128S052=m
CONFIG_TI_ADC161S626=m
CONFIG_TI_ADS1015=m
CONFIG_TI_ADS7950=m
CONFIG_TI_ADS8344=m
CONFIG_TI_ADS8688=m
CONFIG_TI_ADS124S08=m
CONFIG_TI_TLC4541=m
CONFIG_VF610_ADC=m
CONFIG_XILINX_XADC=m
# end of Analog to digital converters

#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=m
# end of Analog Front Ends

#
# Amplifiers
#
CONFIG_AD8366=m
CONFIG_HMC425=m
# end of Amplifiers

#
# Chemical Sensors
#
CONFIG_ATLAS_PH_SENSOR=m
CONFIG_ATLAS_EZO_SENSOR=m
CONFIG_BME680=m
CONFIG_BME680_I2C=m
CONFIG_BME680_SPI=m
CONFIG_CCS811=m
CONFIG_IAQCORE=m
CONFIG_SCD30_CORE=m
CONFIG_SCD30_I2C=m
CONFIG_SENSIRION_SGP30=m
CONFIG_SPS30=m
CONFIG_VZ89X=m
# end of Chemical Sensors

#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
# end of Hid Sensor IIO Common

CONFIG_IIO_MS_SENSORS_I2C=m

#
# SSP Sensor Common
#
CONFIG_IIO_SSP_SENSORS_COMMONS=m
CONFIG_IIO_SSP_SENSORHUB=m
# end of SSP Sensor Common

CONFIG_IIO_ST_SENSORS_I2C=m
CONFIG_IIO_ST_SENSORS_SPI=m
CONFIG_IIO_ST_SENSORS_CORE=m

#
# Digital to analog converters
#
CONFIG_AD5064=m
CONFIG_AD5360=m
CONFIG_AD5380=m
CONFIG_AD5421=m
CONFIG_AD5446=m
CONFIG_AD5449=m
CONFIG_AD5592R_BASE=m
CONFIG_AD5592R=m
CONFIG_AD5593R=m
CONFIG_AD5504=m
CONFIG_AD5624R_SPI=m
CONFIG_AD5686=m
CONFIG_AD5686_SPI=m
CONFIG_AD5696_I2C=m
CONFIG_AD5755=m
CONFIG_AD5758=m
CONFIG_AD5761=m
CONFIG_AD5764=m
CONFIG_AD5770R=m
CONFIG_AD5791=m
CONFIG_AD7303=m
CONFIG_AD8801=m
CONFIG_DPOT_DAC=m
CONFIG_DS4424=m
CONFIG_LTC1660=m
CONFIG_LTC2632=m
CONFIG_M62332=m
CONFIG_MAX517=m
CONFIG_MAX5821=m
CONFIG_MCP4725=m
CONFIG_MCP4922=m
CONFIG_TI_DAC082S085=m
CONFIG_TI_DAC5571=m
CONFIG_TI_DAC7311=m
CONFIG_TI_DAC7612=m
CONFIG_VF610_DAC=m
# end of Digital to analog converters

#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
CONFIG_AD9523=m
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4350=m
CONFIG_ADF4371=m
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=m
CONFIG_ADIS16130=m
CONFIG_ADIS16136=m
CONFIG_ADIS16260=m
CONFIG_ADXRS290=m
CONFIG_ADXRS450=m
CONFIG_BMG160=m
CONFIG_BMG160_I2C=m
CONFIG_BMG160_SPI=m
CONFIG_FXAS21002C=m
CONFIG_FXAS21002C_I2C=m
CONFIG_FXAS21002C_SPI=m
CONFIG_HID_SENSOR_GYRO_3D=m
CONFIG_MPU3050=m
CONFIG_MPU3050_I2C=m
CONFIG_IIO_ST_GYRO_3AXIS=m
CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
CONFIG_ITG3200=m
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
CONFIG_AFE4403=m
CONFIG_AFE4404=m
CONFIG_MAX30100=m
CONFIG_MAX30102=m
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
CONFIG_AM2315=m
CONFIG_DHT11=m
CONFIG_HDC100X=m
CONFIG_HDC2010=m
CONFIG_HID_SENSOR_HUMIDITY=m
CONFIG_HTS221=m
CONFIG_HTS221_I2C=m
CONFIG_HTS221_SPI=m
CONFIG_HTU21=m
CONFIG_SI7005=m
CONFIG_SI7020=m
# end of Humidity sensors

#
# Inertial measurement units
#
CONFIG_ADIS16400=m
CONFIG_ADIS16460=m
CONFIG_ADIS16475=m
CONFIG_ADIS16480=m
CONFIG_BMI160=m
CONFIG_BMI160_I2C=m
CONFIG_BMI160_SPI=m
CONFIG_FXOS8700=m
CONFIG_FXOS8700_I2C=m
CONFIG_FXOS8700_SPI=m
CONFIG_KMX61=m
CONFIG_INV_ICM42600=m
CONFIG_INV_ICM42600_I2C=m
CONFIG_INV_ICM42600_SPI=m
CONFIG_INV_MPU6050_IIO=m
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_SPI=m
# CONFIG_IIO_ST_LSM6DSR is not set
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_LSM6DSX_I2C=m
CONFIG_IIO_ST_LSM6DSX_SPI=m
# end of Inertial measurement units

CONFIG_IIO_ADIS_LIB=m
CONFIG_IIO_ADIS_LIB_BUFFER=y

#
# Light sensors
#
CONFIG_ACPI_ALS=m
CONFIG_ADJD_S311=m
CONFIG_ADUX1020=m
CONFIG_AL3010=m
CONFIG_AL3320A=m
CONFIG_APDS9300=m
CONFIG_APDS9960=m
CONFIG_AS73211=m
CONFIG_BH1750=m
CONFIG_BH1780=m
CONFIG_CM32181=m
CONFIG_CM3232=m
CONFIG_CM3323=m
CONFIG_CM3605=m
CONFIG_CM36651=m
CONFIG_GP2AP002=m
CONFIG_GP2AP020A00F=m
CONFIG_SENSORS_ISL29018=m
CONFIG_SENSORS_ISL29028=m
CONFIG_ISL29125=m
CONFIG_HID_SENSOR_ALS=m
CONFIG_HID_SENSOR_PROX=m
CONFIG_JSA1212=m
CONFIG_RPR0521=m
CONFIG_LTR501=m
CONFIG_LV0104CS=m
CONFIG_MAX44000=m
CONFIG_MAX44009=m
CONFIG_NOA1305=m
CONFIG_OPT3001=m
CONFIG_PA12203001=m
CONFIG_SI1133=m
CONFIG_SI1145=m
CONFIG_STK3310=m
CONFIG_ST_UVIS25=m
CONFIG_ST_UVIS25_I2C=m
CONFIG_ST_UVIS25_SPI=m
CONFIG_TCS3414=m
CONFIG_TCS3472=m
CONFIG_SENSORS_TSL2563=m
CONFIG_TSL2583=m
CONFIG_TSL2772=m
CONFIG_TSL4531=m
# CONFIG_UCS12CM0 is not set
CONFIG_US5182D=m
CONFIG_VCNL4000=m
CONFIG_VCNL4035=m
CONFIG_VEML6030=m
CONFIG_VEML6070=m
CONFIG_VL6180=m
CONFIG_ZOPT2201=m
# end of Light sensors

#
# Magnetometer sensors
#
CONFIG_AK8974=m
CONFIG_AK8975=m
CONFIG_AK09911=m
CONFIG_BMC150_MAGN=m
CONFIG_BMC150_MAGN_I2C=m
CONFIG_BMC150_MAGN_SPI=m
CONFIG_MAG3110=m
CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
CONFIG_MMC35240=m
CONFIG_IIO_ST_MAGN_3AXIS=m
CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
CONFIG_SENSORS_HMC5843=m
CONFIG_SENSORS_HMC5843_I2C=m
CONFIG_SENSORS_HMC5843_SPI=m
CONFIG_SENSORS_RM3100=m
CONFIG_SENSORS_RM3100_I2C=m
CONFIG_SENSORS_RM3100_SPI=m
# end of Magnetometer sensors

#
# Multiplexers
#
CONFIG_IIO_MUX=m
# end of Multiplexers

#
# Inclinometer sensors
#
CONFIG_HID_SENSOR_INCLINOMETER_3D=m
CONFIG_HID_SENSOR_DEVICE_ROTATION=m
# end of Inclinometer sensors

#
# Triggers - standalone
#
# CONFIG_IIO_HRTIMER_TRIGGER is not set
CONFIG_IIO_INTERRUPT_TRIGGER=y
# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set
CONFIG_IIO_SYSFS_TRIGGER=y
# end of Triggers - standalone

#
# Linear and angular position sensors
#
# end of Linear and angular position sensors

#
# Digital potentiometers
#
CONFIG_AD5272=m
CONFIG_DS1803=m
CONFIG_MAX5432=m
CONFIG_MAX5481=m
CONFIG_MAX5487=m
CONFIG_MCP4018=m
CONFIG_MCP4131=m
CONFIG_MCP4531=m
CONFIG_MCP41010=m
CONFIG_TPL0102=m
# end of Digital potentiometers

#
# Digital potentiostats
#
CONFIG_LMP91000=m
# end of Digital potentiostats

#
# Pressure sensors
#
CONFIG_ABP060MG=m
CONFIG_BMP280=m
CONFIG_BMP280_I2C=m
CONFIG_BMP280_SPI=m
CONFIG_DLHL60D=m
CONFIG_DPS310=m
CONFIG_HID_SENSOR_PRESS=m
CONFIG_HP03=m
CONFIG_ICP10100=m
CONFIG_MPL115=m
CONFIG_MPL115_I2C=m
CONFIG_MPL115_SPI=m
CONFIG_MPL3115=m
CONFIG_MS5611=m
CONFIG_MS5611_I2C=m
CONFIG_MS5611_SPI=m
CONFIG_MS5637=m
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_PRESS_I2C=m
CONFIG_IIO_ST_PRESS_SPI=m
CONFIG_T5403=m
CONFIG_HP206C=m
CONFIG_ZPA2326=m
CONFIG_ZPA2326_I2C=m
CONFIG_ZPA2326_SPI=m
# end of Pressure sensors

#
# Lightning sensors
#
CONFIG_AS3935=m
# end of Lightning sensors

#
# Proximity and distance sensors
#
CONFIG_ISL29501=m
CONFIG_LIDAR_LITE_V2=m
CONFIG_MB1232=m
CONFIG_PING=m
CONFIG_RFD77402=m
CONFIG_SRF04=m
CONFIG_SX9310=m
CONFIG_SX9500=m
CONFIG_SRF08=m
CONFIG_VCNL3020=m
CONFIG_VL53L0X_I2C=m
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
CONFIG_AD2S90=m
CONFIG_AD2S1200=m
# end of Resolver to digital converters

#
# Temperature sensors
#
CONFIG_LTC2983=m
CONFIG_MAXIM_THERMOCOUPLE=m
CONFIG_HID_SENSOR_TEMP=m
CONFIG_MLX90614=m
CONFIG_MLX90632=m
CONFIG_TMP006=m
CONFIG_TMP007=m
CONFIG_TSYS01=m
CONFIG_TSYS02D=m
CONFIG_MAX31856=m
# end of Temperature sensors

# CONFIG_NTB is not set
# CONFIG_VME_BUS is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_FSL_FTM is not set
CONFIG_PWM_GPIO=m
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_ROCKCHIP=y
# CONFIG_PWM_ROCKCHIP_ONESHOT is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_AL_FIC is not set
CONFIG_PARTITION_PERCPU=y
# end of IRQ chip support

# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_SCMI=y
# CONFIG_RESET_TI_SYSCON is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_PHY_XGENE is not set
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_FSL_IMX8MQ_USB is not set
# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y
CONFIG_PHY_ROCKCHIP_DP=y
CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_COMBPHY=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_USB3=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
CONFIG_PHY_ROCKCHIP_MIPI_RX=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
CONFIG_PHY_ROCKCHIP_NANENG_EDP=y
CONFIG_PHY_ROCKCHIP_NANENG_USB2=y
CONFIG_PHY_ROCKCHIP_PCIE=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PHY_ROCKCHIP_USB=y
CONFIG_PHY_ROCKCHIP_USBDP=y
# CONFIG_PHY_SAMSUNG_USB2 is not set
# end of PHY Subsystem

# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCI400_PMU=y
CONFIG_ARM_CCI5xx_PMU=y
CONFIG_ARM_CCN=m
CONFIG_ARM_CMN=m
CONFIG_ARM_PMU=y
CONFIG_ARM_PMU_ACPI=y
CONFIG_ARM_SMMU_V3_PMU=m
CONFIG_ARM_DSU_PMU=m
CONFIG_ARM_SPE_PMU=m
# CONFIG_HISI_PMU is not set
# end of Performance monitor support

# CONFIG_RAS is not set
# CONFIG_USB4 is not set

#
# Android
#
CONFIG_ANDROID=y
# CONFIG_ANDROID_BINDER_IPC is not set
# CONFIG_ANDROID_DEBUG_SYMBOLS is not set
# CONFIG_ANDROID_VENDOR_HOOKS is not set
# CONFIG_ANDROID_KABI_RESERVE is not set
# CONFIG_ANDROID_VENDOR_OEM_DATA is not set
# end of Android

# CONFIG_LIBNVDIMM is not set
CONFIG_DAX=y
# CONFIG_DEV_DAX is not set
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_NVMEM_ROCKCHIP_SEC_OTP=m

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# end of HW tracing support

# CONFIG_FPGA is not set
# CONFIG_FSI is not set
CONFIG_TEE=y

#
# TEE drivers
#
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
# end of TEE drivers

CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
# CONFIG_MUX_ADGS1408 is not set
# CONFIG_MUX_GPIO is not set
# CONFIG_MUX_MMIO is not set
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set
# CONFIG_INTERCONNECT is not set
# CONFIG_COUNTER is not set
# CONFIG_MOST is not set
# CONFIG_RK_FLASH is not set
# CONFIG_RK_NAND is not set

#
# Headset device support
#
CONFIG_RK_HEADSET=y
# end of Headset device support

#
# RKNPU
#
CONFIG_ROCKCHIP_RKNPU=m
CONFIG_ROCKCHIP_RKNPU_DEBUG_FS=y
CONFIG_ROCKCHIP_RKNPU_PROC_FS=y
CONFIG_ROCKCHIP_RKNPU_FENCE=y
CONFIG_ROCKCHIP_RKNPU_SRAM=y
CONFIG_ROCKCHIP_RKNPU_DRM_GEM=y
# end of RKNPU
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_IOMAP=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=y
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
# CONFIG_JFS_FS is not set
CONFIG_XFS_FS=y
CONFIG_XFS_SUPPORT_V4=y
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
CONFIG_XFS_RT=y
# CONFIG_XFS_ONLINE_SCRUB is not set
CONFIG_XFS_WARN=y
# CONFIG_XFS_DEBUG is not set
CONFIG_GFS2_FS=m
# CONFIG_GFS2_FS_LOCKING_DLM is not set
CONFIG_OCFS2_FS=m
CONFIG_OCFS2_FS_O2CB=m
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
CONFIG_OCFS2_FS_STATS=y
CONFIG_OCFS2_DEBUG_MASKLOG=y
# CONFIG_OCFS2_DEBUG_FS is not set
CONFIG_BTRFS_FS=y
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
# CONFIG_BTRFS_FS_REF_VERIFY is not set
# CONFIG_NILFS2_FS is not set
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
# CONFIG_F2FS_FAULT_INJECTION is not set
CONFIG_F2FS_FS_COMPRESSION=y
CONFIG_F2FS_FS_LZO=y
CONFIG_F2FS_FS_LZ4=y
CONFIG_F2FS_FS_LZ4HC=y
CONFIG_F2FS_FS_ZSTD=y
CONFIG_F2FS_FS_LZORLE=y
CONFIG_FS_DAX=y
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_MANDATORY_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_PRINT_QUOTA_WARNING is not set
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
# CONFIG_AUTOFS4_FS is not set
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=m
CONFIG_CUSE=m
CONFIG_VIRTIO_FS=m
CONFIG_OVERLAY_FS=m
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set
CONFIG_INCREMENTAL_FS=m

#
# Caches
#
CONFIG_FSCACHE=m
# CONFIG_FSCACHE_STATS is not set
# CONFIG_FSCACHE_HISTOGRAM is not set
# CONFIG_FSCACHE_DEBUG is not set
# CONFIG_FSCACHE_OBJECT_LIST is not set
CONFIG_CACHEFILES=m
# CONFIG_CACHEFILES_DEBUG is not set
# CONFIG_CACHEFILES_HISTOGRAM is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=936
CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_EXFAT_FS=y
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_NTFS_FS is not set
CONFIG_NTFS3_FS=m
# CONFIG_NTFS3_64BIT_CLUSTER is not set
CONFIG_NTFS3_LZX_XPRESS=y
# CONFIG_NTFS3_FS_POSIX_ACL is not set
# end of DOS/FAT/EXFAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_TMPFS_INODE64 is not set
# CONFIG_HUGETLBFS is not set
CONFIG_MEMFD_CREATE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=y
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
CONFIG_ECRYPT_FS=m
# CONFIG_ECRYPT_FS_MESSAGING is not set
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
CONFIG_JFFS2_SUMMARY=y
# CONFIG_JFFS2_FS_XATTR is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
CONFIG_UBIFS_FS=m
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
# CONFIG_CRAMFS is not set
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_FILE_CACHE=y
# CONFIG_SQUASHFS_FILE_DIRECT is not set
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_ZSTD=y
CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
# CONFIG_SQUASHFS_EMBEDDED is not set
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFLATE_COMPRESS=y
CONFIG_PSTORE_LZO_COMPRESS=y
CONFIG_PSTORE_LZ4_COMPRESS=y
CONFIG_PSTORE_LZ4HC_COMPRESS=y
CONFIG_PSTORE_842_COMPRESS=y
CONFIG_PSTORE_ZSTD_COMPRESS=y
CONFIG_PSTORE_COMPRESS=y
# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT=y
CONFIG_PSTORE_COMPRESS_DEFAULT="zstd"
CONFIG_PSTORE_CONSOLE=y
# CONFIG_PSTORE_PMSG is not set
CONFIG_PSTORE_RAM=y
# CONFIG_PSTORE_BOOT_LOG is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_EROFS_FS=m
# CONFIG_EROFS_FS_DEBUG is not set
CONFIG_EROFS_FS_XATTR=y
CONFIG_EROFS_FS_POSIX_ACL=y
CONFIG_EROFS_FS_SECURITY=y
CONFIG_EROFS_FS_ZIP=y
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V2=m
CONFIG_NFS_V3=m
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=m
CONFIG_NFS_SWAP=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=m
CONFIG_PNFS_BLOCK=m
CONFIG_PNFS_FLEXFILE_LAYOUT=m
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
CONFIG_NFS_V4_1_MIGRATION=y
CONFIG_NFS_V4_SECURITY_LABEL=y
CONFIG_NFS_FSCACHE=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
CONFIG_NFS_V4_2_READ_PLUS=y
CONFIG_NFSD=m
CONFIG_NFSD_V2_ACL=y
CONFIG_NFSD_V3=y
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
# CONFIG_NFSD_BLOCKLAYOUT is not set
# CONFIG_NFSD_SCSILAYOUT is not set
# CONFIG_NFSD_FLEXFILELAYOUT is not set
# CONFIG_NFSD_V4_2_INTER_SSC is not set
# CONFIG_NFSD_V4_SECURITY_LABEL is not set
CONFIG_SMB_SERVER=m
CONFIG_SMB_INSECURE_SERVER=y
CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
# CONFIG_SMB_SERVER_KERBEROS5 is not set
CONFIG_GRACE_PERIOD=m
CONFIG_LOCKD=m
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=m
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=m
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_BACKCHANNEL=y
CONFIG_SUNRPC_SWAP=y
CONFIG_RPCSEC_GSS_KRB5=m
# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
# CONFIG_SUNRPC_DEBUG is not set
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
# CONFIG_CEPH_FS_SECURITY_LABEL is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
CONFIG_CIFS_WEAK_PW_HASH=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
# CONFIG_CIFS_DEBUG is not set
CONFIG_CIFS_DFS_UPCALL=y
# CONFIG_CIFS_FSCACHE is not set
CONFIG_CODA_FS=m
CONFIG_AFS_FS=m
# CONFIG_AFS_DEBUG is not set
# CONFIG_AFS_FSCACHE is not set
# CONFIG_AFS_DEBUG_CURSOR is not set
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
# CONFIG_9P_FS_SECURITY is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=m
CONFIG_NLS_MAC_GAELIC=m
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=y
CONFIG_DLM=m
# CONFIG_DLM_DEBUG is not set
CONFIG_UNICODE=y
# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_TRUSTED_KEYS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
# CONFIG_SECURITY_NETWORK_XFRM is not set
CONFIG_SECURITY_PATH=y
CONFIG_LSM_MMAP_MIN_ADDR=32768
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_SECURITY_SELINUX=y
# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set
# CONFIG_SECURITY_SELINUX_DISABLE is not set
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
CONFIG_SECURITY_APPARMOR=y
CONFIG_SECURITY_APPARMOR_HASH=y
CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
# CONFIG_SECURITY_APPARMOR_DEBUG is not set
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
CONFIG_INTEGRITY_AUDIT=y
# CONFIG_IMA is not set
# CONFIG_EVM is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor "

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
CONFIG_INIT_STACK_NONE=y
# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
# CONFIG_INIT_STACK_ALL_PATTERN is not set
# CONFIG_INIT_STACK_ALL_ZERO is not set
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
# end of Memory initialization
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=y
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_FIPS140=y
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=m
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
# CONFIG_CRYPTO_USER is not set
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_CRYPTD=m
CONFIG_CRYPTO_AUTHENC=m
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_ENGINE=m

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=m
CONFIG_CRYPTO_ECC=m
CONFIG_CRYPTO_ECDH=m
CONFIG_CRYPTO_ECRDSA=m
CONFIG_CRYPTO_SM2=y
CONFIG_CRYPTO_CURVE25519=y

#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_AEGIS128=y
CONFIG_CRYPTO_AEGIS128_SIMD=y
CONFIG_CRYPTO_SEQIV=m
CONFIG_CRYPTO_ECHAINIV=m

#
# Block modes
#
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_KEYWRAP=m
CONFIG_CRYPTO_NHPOLY1305=y
CONFIG_CRYPTO_ADIANTUM=m
CONFIG_CRYPTO_ESSIV=m

#
# Hash modes
#
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_VMAC=m

#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_XXHASH=y
CONFIG_CRYPTO_BLAKE2B=y
CONFIG_CRYPTO_BLAKE2S=m
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_RMD128=m
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_RMD256=m
CONFIG_CRYPTO_RMD320=m
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_STREEBOG=m
CONFIG_CRYPTO_TGR192=m
CONFIG_CRYPTO_WP512=m

#
# Ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_BLOWFISH_COMMON=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST_COMMON=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SALSA20=m
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=y
CONFIG_CRYPTO_ZSTD=y

#
# Random Number Generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=m
CONFIG_CRYPTO_DRBG_HMAC=y
# CONFIG_CRYPTO_DRBG_HASH is not set
# CONFIG_CRYPTO_DRBG_CTR is not set
CONFIG_CRYPTO_DRBG=m
CONFIG_CRYPTO_JITTERENTROPY=m
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=m
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_CCP is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_ROCKCHIP=m
CONFIG_CRYPTO_DEV_ROCKCHIP_V1=y
CONFIG_CRYPTO_DEV_ROCKCHIP_V2=y
CONFIG_CRYPTO_DEV_ROCKCHIP_V3=y
# CONFIG_CRYPTO_DEV_ROCKCHIP_DEV is not set
CONFIG_CRYPTO_DEV_VIRTIO=m
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
# CONFIG_CRYPTO_DEV_CCREE is not set
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_PKCS7_TEST_KEY is not set
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_RAID6_PQ=y
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=m
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
# CONFIG_INDIRECT_PIO is not set

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=m
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=m
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
CONFIG_CRYPTO_LIB_CURVE25519=m
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=m
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines

CONFIG_LIB_MEMNEQ=y
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=m
CONFIG_CRC4=m
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=m
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
# CONFIG_XZ_DEC_SPARC is not set
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_INTERVAL_TREE=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_SWIOTLB=y
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y
# CONFIG_DMA_PERNUMA_CMA is not set

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=256
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
CONFIG_SGL_ALLOC=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
CONFIG_IRQ_POLL=y
CONFIG_MPILIB=y
CONFIG_DIMLIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_ARCH_STACKWALK=y
CONFIG_SBITMAP=y
CONFIG_PARMAN=m
CONFIG_OBJAGG=m
# CONFIG_STRING_SELFTEST is not set
# end of Library routines

CONFIG_PLDMFW=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER is not set
# CONFIG_PRINTK_CALLER is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_INFO_REDUCED is not set
CONFIG_DEBUG_INFO_COMPRESSED=y
# CONFIG_DEBUG_INFO_SPLIT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
CONFIG_DEBUG_INFO_BTF=y
# CONFIG_GDB_SCRIPTS is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=2048
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_READABLE_ASM is not set
CONFIG_HEADERS_INSTALL=y
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_KCSAN_COMPILER=y
# end of Generic Kernel Debugging Instruments

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_PINNER is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
# end of Memory Debugging

# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SOFTLOCKUP_DETECTOR is not set
CONFIG_HAVE_HARDLOCKUP_DETECTOR_OTHER_CPU=y
# CONFIG_HARDLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHED_INFO=y
# CONFIG_SCHEDSTATS is not set
# end of Scheduler Debugging

# CONFIG_DEBUG_TIMEKEEPING is not set
CONFIG_DEBUG_PREEMPT=y

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

CONFIG_STACKTRACE=y
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_HAVE_DEBUG_BUGVERBOSE=y

#
# Debug kernel data structures
#
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# end of Debug kernel data structures

# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
# CONFIG_RCU_SCALE_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
# CONFIG_BOOTPARAM_RCU_STALL_PANIC is not set
CONFIG_BOOTPARAM_RCU_STALL_PANIC_VALUE=0
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
# CONFIG_LATENCYTOP is not set
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
# CONFIG_TRACE_MMIO_ACCESS is not set
# CONFIG_TRACEFS_DISABLE_AUTOMOUNT is not set
CONFIG_TRACING=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_BOOTTIME_TRACING is not set
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_PREEMPT_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_HWLAT_TRACER is not set
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
# CONFIG_FTRACE_SYSCALLS is not set
# CONFIG_TRACER_SNAPSHOT is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_KPROBE_EVENTS=y
CONFIG_UPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_DYNAMIC_EVENTS=y
CONFIG_PROBE_EVENTS=y
# CONFIG_SYNTH_EVENTS is not set
# CONFIG_HIST_TRIGGERS is not set
# CONFIG_TRACE_EVENT_INJECT is not set
# CONFIG_TRACEPOINT_BENCHMARK is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_TRACE_EVAL_MAP_FILE is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
# CONFIG_KPROBE_EVENT_GEN_TEST is not set
# CONFIG_SAMPLES is not set
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
# CONFIG_STRICT_DEVMEM is not set

#
# arm64 Debugging
#
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_DEBUG_EFI is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
# end of arm64 Debugging

#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FUNCTION_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_LKDTM is not set
# CONFIG_TEST_LIST_SORT is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_SORT is not set
# CONFIG_KPROBES_SANITY_TEST is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_ASYNC_RAID6_TEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_STRSCPY is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_OVERFLOW is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_HASH is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_PARMAN is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_VMALLOC is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_BPF is not set
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_OBJAGG is not set
# CONFIG_TEST_STACKINIT is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_FREE_PAGES is not set
CONFIG_MEMTEST=y
# end of Kernel Testing and Coverage
# end of Kernel hacking


================================================
FILE: kernel-config/release/rk3588/config-6.1
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 6.1.141 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 15.2.Rel1 (Build arm-15.86)) 15.2.1 20251203"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=150201
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=24501
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=24501
CONFIG_LLD_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_PAHOLE_VERSION=130
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
# CONFIG_UAPI_HEADER_TEST is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT="/sbin/init"
CONFIG_DEFAULT_HOSTNAME="none"
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
# CONFIG_WATCH_QUEUE is not set
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_USELIB is not set
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_SIM=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem

CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
# CONFIG_NO_HZ_FULL is not set
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y

#
# BPF subsystem
#
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_JIT=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
CONFIG_BPF_JIT_DEFAULT_ON=y
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
CONFIG_USERMODE_DRIVER=y
CONFIG_BPF_PRELOAD=y
CONFIG_BPF_PRELOAD_UMD=y
# CONFIG_BPF_LSM is not set
# end of BPF subsystem

CONFIG_PREEMPT_VOLUNTARY_BUILD=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
# CONFIG_PREEMPT_DYNAMIC is not set

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_SCHED_THERMAL_PRESSURE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
# CONFIG_PRINTK_INDEX is not set
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
CONFIG_UCLAMP_TASK=y
CONFIG_UCLAMP_BUCKETS_COUNT=20
# end of Scheduler features

CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_CC_HAS_INT128=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_GCC10_NO_ARRAY_BOUNDS=y
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_UCLAMP_TASK_GROUP=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
CONFIG_CGROUP_MISC=y
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_SCHED_AUTOGROUP=y
# CONFIG_SYSFS_DEPRECATED is not set
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
# CONFIG_BOOT_CONFIG_EMBED is not set
CONFIG_INITRAMFS_PRESERVE_MTIME=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
# CONFIG_SGETMASK_SYSCALL is not set
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_GUEST_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
# end of General setup

CONFIG_ARM64=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_CONT_PTE_SHIFT=4
CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y

#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
# CONFIG_ARCH_SUNXI is not set
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_APPLE is not set
# CONFIG_ARCH_BCM is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SPARX5 is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_KEEMBAY is not set
# CONFIG_ARCH_MEDIATEK is not set
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_NXP is not set
# CONFIG_ARCH_NPCM is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_RENESAS is not set
CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_INTEL_SOCFPGA is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZYNQMP is not set
# end of Platform selection

#
# Kernel Features
#

#
# ARM errata workarounds via the alternatives framework
#
CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_834220=y
CONFIG_ARM64_ERRATUM_1742098=y
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1319367=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_ERRATUM_2441007=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_ARM64_ERRATUM_2051678=y
CONFIG_ARM64_ERRATUM_2077057=y
CONFIG_ARM64_ERRATUM_2658417=y
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
CONFIG_ARM64_ERRATUM_2054223=y
CONFIG_ARM64_ERRATUM_2067961=y
CONFIG_ARM64_ERRATUM_2441009=y
CONFIG_ARM64_ERRATUM_2457168=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y
CONFIG_ARM64_ERRATUM_2966298=y
CONFIG_ARM64_ERRATUM_3194386=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
CONFIG_QCOM_FALKOR_ERRATUM_1009=y
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
# end of ARM errata workarounds via the alternatives framework

CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
# CONFIG_ARM64_VA_BITS_39 is not set
CONFIG_ARM64_VA_BITS_48=y
CONFIG_ARM64_VA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SCHED_MC=y
# CONFIG_SCHED_CLUSTER is not set
# CONFIG_SCHED_SMT is not set
CONFIG_NR_CPUS=8
CONFIG_HOTPLUG_CPU=y
# CONFIG_NUMA is not set
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
CONFIG_HZ_300=y
# CONFIG_HZ_1000 is not set
CONFIG_HZ=300
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_KEXEC is not set
# CONFIG_KEXEC_FILE is not set
# CONFIG_CRASH_DUMP is not set
# CONFIG_XEN is not set
CONFIG_ARCH_FORCE_MAX_ORDER=11
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_ARM64_SW_TTBR0_PAN=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y
# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y

#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
CONFIG_AS_HAS_LDAPR=y
CONFIG_AS_HAS_LSE_ATOMICS=y
CONFIG_ARM64_LSE_ATOMICS=y
CONFIG_ARM64_USE_LSE_ATOMICS=y
# end of ARMv8.1 architectural features

#
# ARMv8.2 architectural features
#
CONFIG_AS_HAS_ARMV8_2=y
CONFIG_AS_HAS_SHA3=y
# CONFIG_ARM64_PMEM is not set
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features

#
# ARMv8.3 architectural features
#
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
CONFIG_AS_HAS_PAC=y
CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
# end of ARMv8.3 architectural features

#
# ARMv8.4 architectural features
#
CONFIG_ARM64_AMU_EXTN=y
CONFIG_AS_HAS_ARMV8_4=y
CONFIG_ARM64_TLB_RANGE=y
# end of ARMv8.4 architectural features

#
# ARMv8.5 architectural features
#
CONFIG_AS_HAS_ARMV8_5=y
CONFIG_ARM64_BTI=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARM64_AS_HAS_MTE=y
CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features

#
# ARMv8.7 architectural features
#
CONFIG_ARM64_EPAN=y
# end of ARMv8.7 architectural features

CONFIG_ARM64_SVE=y
CONFIG_ARM64_MODULE_PLTS=y
CONFIG_ARM64_PSEUDO_NMI=y
# CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set
CONFIG_RELOCATABLE=y
CONFIG_RANDOMIZE_BASE=y
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
CONFIG_ARCH_NR_GPIO=0
# end of Kernel Features

#
# Boot options
#
CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
CONFIG_CMDLINE=""
CONFIG_EFI_STUB=y
CONFIG_EFI=y
CONFIG_DMI=y
# end of Boot options

#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
# CONFIG_HIBERNATION is not set
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
# CONFIG_PM_TEST_SUSPEND is not set
CONFIG_PM_SLEEP_DEBUG=y
CONFIG_DPM_WATCHDOG=y
CONFIG_DPM_WATCHDOG_TIMEOUT=120
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options

#
# CPU Power Management
#

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
# CONFIG_CPU_IDLE_GOV_LADDER is not set
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_DT_IDLE_STATES=y
CONFIG_DT_IDLE_GENPD=y

#
# ARM CPU Idle Drivers
#
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
# end of ARM CPU Idle Drivers
# end of CPU Idle

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_INTERACTIVE=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_ACPI_CPPC_CPUFREQ=y
CONFIG_ACPI_CPPC_CPUFREQ_FIE=y
CONFIG_ARM_ROCKCHIP_CPUFREQ=y
CONFIG_ARM_SCMI_CPUFREQ=y
# end of CPU Frequency scaling
# end of CPU Power Management

CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_GENERIC_GSI=y
CONFIG_ACPI_CCA_REQUIRED=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
CONFIG_ACPI_EC_DEBUGFS=m
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
# CONFIG_ACPI_VIDEO is not set
CONFIG_ACPI_FAN=y
CONFIG_ACPI_TAD=m
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_MCFG=y
CONFIG_ACPI_CPPC_LIB=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_HOTPLUG_CPU=y
CONFIG_ACPI_THERMAL=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_PCI_SLOT=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_CUSTOM_METHOD=m
CONFIG_ACPI_BGRT=y
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
CONFIG_HAVE_ACPI_APEI=y
CONFIG_ACPI_APEI=y
CONFIG_ACPI_APEI_GHES=y
CONFIG_ACPI_APEI_SEA=y
CONFIG_ACPI_APEI_EINJ=m
CONFIG_ACPI_APEI_ERST_DEBUG=m
CONFIG_ACPI_CONFIGFS=m
# CONFIG_ACPI_PFRUT is not set
CONFIG_ACPI_IORT=y
CONFIG_ACPI_GTDT=y
# CONFIG_ACPI_AGDI is not set
CONFIG_ACPI_PPTT=y
CONFIG_ACPI_PCC=y
CONFIG_PMIC_OPREGION=y
CONFIG_ACPI_VIOT=y
CONFIG_ACPI_PRMT=y
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_HAVE_KVM=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_MMIO=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_KVM_XFER_TO_GUEST_WORK=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
# CONFIG_NVHE_EL2_DEBUG is not set
CONFIG_CPU_MITIGATIONS=y

#
# General architecture-dependent options
#
CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y
CONFIG_KPROBES=y
# CONFIG_JUMP_LABEL is not set
CONFIG_UPROBES=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
# CONFIG_SECCOMP_CACHE_DEBUG is not set
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
# CONFIG_SHADOW_CALL_STACK is not set
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
CONFIG_HAVE_CONTEXT_TRACKING_USER=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_ARCH_HUGE_VMALLOC=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET=y
# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
CONFIG_HAVE_PREEMPT_DYNAMIC=y
CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
CONFIG_MODULE_COMPRESS_NONE=y
# CONFIG_MODULE_COMPRESS_GZIP is not set
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BLK_RQ_ALLOC_TIME=y
CONFIG_BLK_CGROUP_RWSTAT=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_ICQ=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=y
CONFIG_BLK_DEV_ZONED=y
CONFIG_BLK_DEV_THROTTLING=y
# CONFIG_BLK_DEV_THROTTLING_LOW is not set
CONFIG_BLK_WBT=y
CONFIG_BLK_WBT_MQ=y
CONFIG_BLK_CGROUP_IOLATENCY=y
# CONFIG_BLK_CGROUP_FC_APPID is not set
CONFIG_BLK_CGROUP_IOCOST=y
CONFIG_BLK_CGROUP_IOPRIO=y
CONFIG_BLK_DEBUG_FS=y
CONFIG_BLK_DEBUG_FS_ZONED=y
CONFIG_BLK_SED_OPAL=y
# CONFIG_BLK_INLINE_ENCRYPTION is not set

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_AIX_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
CONFIG_CMDLINE_PARTITION=y
# end of Partition Types

CONFIG_BLOCK_COMPAT=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_HOLDER_DEPRECATED=y
CONFIG_BLK_MQ_STACKING=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
# CONFIG_BFQ_CGROUP_DEBUG is not set
# end of IO Schedulers

CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK=y
CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_READ_LOCK=y
CONFIG_ARCH_INLINE_READ_LOCK_BH=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_READ_UNLOCK=y
CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_WRITE_LOCK=y
CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_SPIN_TRYLOCK=y
CONFIG_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_INLINE_SPIN_LOCK=y
CONFIG_INLINE_SPIN_LOCK_BH=y
CONFIG_INLINE_SPIN_LOCK_IRQ=y
CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_INLINE_SPIN_UNLOCK_BH=y
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_READ_LOCK=y
CONFIG_INLINE_READ_LOCK_BH=y
CONFIG_INLINE_READ_LOCK_IRQ=y
CONFIG_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_INLINE_READ_UNLOCK=y
CONFIG_INLINE_READ_UNLOCK_BH=y
CONFIG_INLINE_READ_UNLOCK_IRQ=y
CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_WRITE_LOCK=y
CONFIG_INLINE_WRITE_LOCK_BH=y
CONFIG_INLINE_WRITE_LOCK_IRQ=y
CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_INLINE_WRITE_UNLOCK=y
CONFIG_INLINE_WRITE_UNLOCK_BH=y
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_HAVE_ELF_PROT=y
CONFIG_ARCH_USE_GNU_PROPERTY=y
CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=y
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_SWAP=y
# CONFIG_ZSWAP is not set
CONFIG_ZSMALLOC=y
# CONFIG_ZSMALLOC_STAT is not set

#
# SLAB allocator options
#
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
# CONFIG_SLAB_FREELIST_RANDOM is not set
# CONFIG_SLAB_FREELIST_HARDENED is not set
CONFIG_SLUB_SYSFS=y
# CONFIG_SLUB_STATS is not set
# CONFIG_SLUB_CPU_PARTIAL is not set
# end of SLAB allocator options

CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_THP_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PCP_BATCH_SCALE_MAX=5
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_MMU_NOTIFIER=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
# CONFIG_MEMORY_FAILURE is not set
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_TRANSPARENT_HUGEPAGE=y
# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set
CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
CONFIG_THP_SWAP=y
# CONFIG_READ_ONLY_THP_FOR_FS is not set
CONFIG_CMA=y
# CONFIG_CMA_INACTIVE is not set
# CONFIG_CMA_DEBUG is not set
CONFIG_CMA_DEBUGFS=y
CONFIG_CMA_DEBUGFS_BITMAP_HEX=y
CONFIG_CMA_SYSFS=y
CONFIG_CMA_AREAS=7
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
CONFIG_PAGE_IDLE_FLAG=y
CONFIG_IDLE_PAGE_TRACKING=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_ARCH_HAS_ZONE_DMA_SET=y
CONFIG_ZONE_DMA=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_PERCPU_STATS=y
# CONFIG_GUP_TEST is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_SECRETMEM=y
# CONFIG_ANON_VMA_NAME is not set
# CONFIG_USERFAULTFD is not set
CONFIG_LRU_GEN=y
CONFIG_LRU_GEN_ENABLED=y
# CONFIG_LRU_GEN_STATS is not set
CONFIG_LOCK_MM_AND_FIND_VMA=y

#
# Data Access Monitoring
#
# CONFIG_DAMON is not set
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_EXTENSIONS=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_AF_UNIX_OOB=y
CONFIG_UNIX_DIAG=y
CONFIG_TLS=m
CONFIG_TLS_DEVICE=y
CONFIG_TLS_TOE=y
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
CONFIG_XFRM_INTERFACE=m
CONFIG_XFRM_SUB_POLICY=y
CONFIG_XFRM_MIGRATE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_XFRM_AH=m
CONFIG_XFRM_ESP=m
CONFIG_XFRM_IPCOMP=m
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_XFRM_ESPINTCP=y
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
# CONFIG_IP_FIB_TRIE_STATS is not set
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_ROUTE_CLASSID=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=m
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=m
CONFIG_NET_FOU=m
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_ESP_OFFLOAD=m
CONFIG_INET_ESPINTCP=y
CONFIG_INET_IPCOMP=m
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_DIAG=m
CONFIG_INET_TCP_DIAG=m
CONFIG_INET_UDP_DIAG=m
CONFIG_INET_RAW_DIAG=m
# CONFIG_INET_DIAG_DESTROY is not set
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_NV=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_CONG_DCTCP=m
CONFIG_TCP_CONG_CDG=m
CONFIG_TCP_CONG_BBR=m
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=m
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_ESP_OFFLOAD=m
CONFIG_INET6_ESPINTCP=y
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_MIP6=m
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=m
CONFIG_INET6_TUNNEL=m
CONFIG_IPV6_VTI=m
CONFIG_IPV6_SIT=m
CONFIG_IPV6_SIT_6RD=y
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=m
CONFIG_IPV6_GRE=m
CONFIG_IPV6_FOU=m
CONFIG_IPV6_FOU_TUNNEL=m
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
# CONFIG_IPV6_SEG6_HMAC is not set
# CONFIG_IPV6_RPL_LWTUNNEL is not set
# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
CONFIG_NETLABEL=y
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=m
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NETWORK_PHY_TIMESTAMPING=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_EGRESS=y
CONFIG_NETFILTER_SKIP_EGRESS=y
CONFIG_NETFILTER_NETLINK=y
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
# CONFIG_NETFILTER_NETLINK_HOOK is not set
CONFIG_NETFILTER_NETLINK_ACCT=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NETFILTER_NETLINK_OSF=m
CONFIG_NF_CONNTRACK=y
CONFIG_NF_LOG_SYSLOG=m
CONFIG_NETFILTER_CONNCOUNT=m
CONFIG_NF_CONNTRACK_MARK=y
# CONFIG_NF_CONNTRACK_SECMARK is not set
CONFIG_NF_CONNTRACK_ZONES=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y
# CONFIG_NF_CONNTRACK_TIMEOUT is not set
CONFIG_NF_CONNTRACK_TIMESTAMP=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=y
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=y
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_FULLCONE=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_OBJREF=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
CONFIG_NFT_OSF=m
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NF_DUP_NETDEV=y
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NFT_REJECT_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
# CONFIG_NF_FLOW_TABLE_PROCFS is not set
CONFIG_NETFILTER_XTABLES=y
CONFIG_NETFILTER_XTABLES_COMPAT=y

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=y
CONFIG_NETFILTER_XT_CONNMARK=y
CONFIG_NETFILTER_XT_SET=m

#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_AUDIT=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LED=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=y
CONFIG_NETFILTER_XT_TARGET_NETMAP=y
CONFIG_NETFILTER_XT_TARGET_FULLCONENAT=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD=m
CONFIG_NETFILTER_XT_TARGET_RATEEST=y
CONFIG_NETFILTER_XT_TARGET_REDIRECT=y
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
CONFIG_NETFILTER_XT_TARGET_SECMARK=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=y
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=y
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# end of Core Netfilter Configuration

CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
# CONFIG_IP_VS_DEBUG is not set
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m
# CONFIG_IP_VS_TWOS is not set

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_SOCKET_IPV4=m
CONFIG_NF_TPROXY_IPV4=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=m
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_FULLCONENAT=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_SECURITY=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP6_NF_SECURITY=m
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=y
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_NFT_BRIDGE_META=m
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
# CONFIG_BPFILTER is not set
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m

#
# DCCP CCIDs Configuration
#
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
CONFIG_IP_DCCP_CCID3=y
# CONFIG_IP_DCCP_CCID3_DEBUG is not set
CONFIG_IP_DCCP_TFRC_LIB=y
# end of DCCP CCIDs Configuration

#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
# end of DCCP Kernel Hacking

CONFIG_IP_SCTP=m
# CONFIG_SCTP_DBG_OBJCNT is not set
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=m
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
CONFIG_L2TP=m
# CONFIG_L2TP_DEBUGFS is not set
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=m
CONFIG_L2TP_ETH=m
CONFIG_STP=m
CONFIG_GARP=m
CONFIG_MRP=m
CONFIG_BRIDGE=m
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_BRIDGE_MRP=y
CONFIG_BRIDGE_CFM=y
CONFIG_NET_DSA=m
CONFIG_NET_DSA_TAG_AR9331=m
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
CONFIG_NET_DSA_TAG_BRCM=m
CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
CONFIG_NET_DSA_TAG_HELLCREEK=m
CONFIG_NET_DSA_TAG_GSWIP=m
CONFIG_NET_DSA_TAG_DSA_COMMON=m
CONFIG_NET_DSA_TAG_DSA=m
CONFIG_NET_DSA_TAG_EDSA=m
CONFIG_NET_DSA_TAG_MTK=m
CONFIG_NET_DSA_TAG_KSZ=m
CONFIG_NET_DSA_TAG_OCELOT=m
# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set
CONFIG_NET_DSA_TAG_QCA=m
CONFIG_NET_DSA_TAG_RTL4_A=m
CONFIG_NET_DSA_TAG_RTL8_4=m
# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set
CONFIG_NET_DSA_TAG_LAN9303=m
CONFIG_NET_DSA_TAG_SJA1105=m
CONFIG_NET_DSA_TAG_TRAILER=m
CONFIG_NET_DSA_TAG_XRS700X=m
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q_MVRP=y
CONFIG_LLC=m
CONFIG_LLC2=m
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
CONFIG_6LOWPAN=m
# CONFIG_6LOWPAN_DEBUGFS is not set
CONFIG_6LOWPAN_NHC=m
CONFIG_6LOWPAN_NHC_DEST=m
CONFIG_6LOWPAN_NHC_FRAGMENT=m
CONFIG_6LOWPAN_NHC_HOP=m
CONFIG_6LOWPAN_NHC_IPV6=m
CONFIG_6LOWPAN_NHC_MOBILITY=m
CONFIG_6LOWPAN_NHC_ROUTING=m
CONFIG_6LOWPAN_NHC_UDP=m
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
CONFIG_6LOWPAN_GHC_UDP=m
CONFIG_6LOWPAN_GHC_ICMPV6=m
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
CONFIG_IEEE802154=m
# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set
CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_MAC802154=m
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFB=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_SKBPRIO=m
CONFIG_NET_SCH_CHOKE=m
CONFIG_NET_SCH_QFQ=m
CONFIG_NET_SCH_CODEL=m
CONFIG_NET_SCH_FQ_CODEL=y
CONFIG_NET_SCH_CAKE=m
CONFIG_NET_SCH_FQ=m
CONFIG_NET_SCH_HHF=m
CONFIG_NET_SCH_PIE=m
CONFIG_NET_SCH_FQ_PIE=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_SCH_PLUG=m
CONFIG_NET_SCH_ETS=m
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
# CONFIG_CLS_U32_PERF is not set
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=m
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_EMATCH_CANID=m
CONFIG_NET_EMATCH_IPSET=m
CONFIG_NET_EMATCH_IPT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
# CONFIG_NET_ACT_SAMPLE is not set
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
CONFIG_NET_ACT_MPLS=m
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_NET_ACT_CONNMARK=m
CONFIG_NET_ACT_CTINFO=m
CONFIG_NET_ACT_SKBMOD=m
CONFIG_NET_ACT_IFE=m
CONFIG_NET_ACT_TUNNEL_KEY=m
# CONFIG_NET_ACT_CT is not set
CONFIG_NET_ACT_GATE=m
CONFIG_NET_IFE_SKBMARK=m
CONFIG_NET_IFE_SKBPRIO=m
CONFIG_NET_IFE_SKBTCINDEX=m
# CONFIG_NET_TC_SKB_EXT is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=y
CONFIG_BATMAN_ADV=m
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
# CONFIG_BATMAN_ADV_NC is not set
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUG is not set
# CONFIG_BATMAN_ADV_TRACING is not set
CONFIG_OPENVSWITCH=m
CONFIG_OPENVSWITCH_GRE=m
CONFIG_OPENVSWITCH_VXLAN=m
CONFIG_OPENVSWITCH_GENEVE=m
CONFIG_VSOCKETS=m
CONFIG_VSOCKETS_DIAG=m
CONFIG_VSOCKETS_LOOPBACK=m
CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO_VSOCKETS_COMMON=m
CONFIG_NETLINK_DIAG=y
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=m
# CONFIG_MPLS_ROUTING is not set
CONFIG_NET_NSH=m
# CONFIG_HSR is not set
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=m
# CONFIG_QRTR_SMD is not set
# CONFIG_QRTR_TUN is not set
CONFIG_QRTR_MHI=m
# CONFIG_NET_NCSI is not set
CONFIG_PCPU_DEV_REFCNT=y
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_XPS=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_NET_DROP_MONITOR is not set
# end of Network testing
# end of Networking options

# CONFIG_HAMRADIO is not set
CONFIG_CAN=m
CONFIG_CAN_RAW=m
CONFIG_CAN_BCM=m
CONFIG_CAN_GW=m
# CONFIG_CAN_J1939 is not set
# CONFIG_CAN_ISOTP is not set
CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=m
CONFIG_BT_LE=y
CONFIG_BT_LE_L2CAP_ECRED=y
CONFIG_BT_6LOWPAN=m
CONFIG_BT_LEDS=y
CONFIG_BT_MSFTEXT=y
# CONFIG_BT_AOSPEXT is not set
CONFIG_BT_DEBUGFS=y
# CONFIG_BT_SELFTEST is not set

#
# Bluetooth device drivers
#
CONFIG_AIC8800_BTSDIO_SUPPORT=m
CONFIG_AIC8800_BTUSB_SUPPORT=m
CONFIG_BT_INTEL=m
CONFIG_BT_BCM=m
CONFIG_BT_RTL=m
CONFIG_BT_QCA=m
CONFIG_BT_MTK=m
CONFIG_BT_HCIBTUSB=m
CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y
CONFIG_BT_HCIBTUSB_POLL_SYNC=y
CONFIG_BT_HCIBTUSB_BCM=y
CONFIG_BT_HCIBTUSB_MTK=y
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
# CONFIG_BT_HCIUART_NOKIA is not set
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_RTL=y
CONFIG_BT_HCIUART_QCA=y
CONFIG_BT_HCIUART_AG6XX=y
CONFIG_BT_HCIUART_MRVL=y
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBCM4377=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
CONFIG_BT_MTKSDIO=m
CONFIG_BT_MTKUART=m
CONFIG_BT_VIRTIO=m
CONFIG_BT_HCIBTUSB_RTLBTUSB=m
CONFIG_BT_INTEL_PCIE=m
# end of Bluetooth device drivers

CONFIG_AF_RXRPC=m
# CONFIG_AF_RXRPC_IPV6 is not set
# CONFIG_AF_RXRPC_INJECT_LOSS is not set
# CONFIG_AF_RXRPC_DEBUG is not set
# CONFIG_RXKAD is not set
# CONFIG_AF_KCM is not set
CONFIG_STREAM_PARSER=y
# CONFIG_MCTP is not set
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_SPY=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
CONFIG_CFG80211_HEADERS=y
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_CFG80211_WEXT_EXPORT=y
CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
CONFIG_LIB80211_CRYPT_TKIP=m
# CONFIG_LIB80211_DEBUG is not set
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
# CONFIG_MAC80211_MESH is not set
CONFIG_MAC80211_LEDS=y
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_MESSAGE_TRACING is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_RFKILL=y
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=y
CONFIG_RFKILL_RK=y
CONFIG_NET_9P=m
CONFIG_NET_9P_FD=m
CONFIG_NET_9P_VIRTIO=m
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
CONFIG_CEPH_LIB=m
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
# CONFIG_NFC is not set
# CONFIG_PSAMPLE is not set
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_SOCK_VALIDATE_XMIT=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
# CONFIG_PAGE_POOL_STATS is not set
CONFIG_FAILOVER=m
CONFIG_SHORTCUT_FE=y
CONFIG_ETHTOOL_NETLINK=y

#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIEAER is not set
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIEASPM_EXT is not set
CONFIG_PCIE_PME=y
# CONFIG_PCIE_PTM is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_STUB is not set
# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set
CONFIG_PCI_ECAM=y
# CONFIG_PCI_IOV is not set
# CONFIG_PCI_PRI is not set
# CONFIG_PCI_PASID is not set
CONFIG_PCI_LABEL=y
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
# CONFIG_VGA_ARB is not set
# CONFIG_HOTPLUG_PCI is not set

#
# PCI controller drivers
#
# CONFIG_PCI_FTPCI100 is not set
# CONFIG_PCI_HOST_GENERIC is not set
# CONFIG_PCIE_XILINX is not set
# CONFIG_PCI_XGENE is not set
# CONFIG_PCIE_ALTERA is not set
# CONFIG_PCI_HOST_THUNDER_PEM is not set
# CONFIG_PCI_HOST_THUNDER_ECAM is not set
CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_HOST=y
CONFIG_PCIE_ROCKCHIP_EP=y
CONFIG_ROCKCHIP_PCIE_DMA_OBJ=y
# CONFIG_PCIE_MICROCHIP_HOST is not set
# CONFIG_PCIE_HISI_ERR is not set

#
# DesignWare PCI Core Support
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_EP=y
CONFIG_PCIE_DW_PLAT=y
CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCIE_DW_PLAT_EP=y
CONFIG_PCIE_DW_ROCKCHIP=y
# CONFIG_PCIE_RK_THREADED_INIT is not set
CONFIG_PCIE_DW_ROCKCHIP_EP=y
# CONFIG_PCI_HISI is not set
# CONFIG_PCIE_KIRIN is not set
# CONFIG_PCI_MESON is not set
# CONFIG_PCIE_AL is not set
# end of DesignWare PCI Core Support

#
# Mobiveil PCIe Core Support
#
# end of Mobiveil PCIe Core Support

#
# Cadence PCIe controllers support
#
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCIE_CADENCE_PLAT_EP is not set
# CONFIG_PCI_J721E_HOST is not set
# CONFIG_PCI_J721E_EP is not set
# end of Cadence PCIe controllers support
# end of PCI controller drivers

#
# PCI Endpoint
#
CONFIG_PCI_ENDPOINT=y
# CONFIG_PCI_ENDPOINT_CONFIGFS is not set
# CONFIG_PCI_EPF_TEST is not set
# CONFIG_PCI_EPF_NTB is not set
# end of PCI Endpoint

#
# PCI switch controller drivers
#
CONFIG_PCI_SW_SWITCHTEC=m
# end of PCI switch controller drivers

# CONFIG_CXL_BUS is not set
# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
CONFIG_AUXILIARY_BUS=y
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_DEVTMPFS_SAFE is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
CONFIG_FW_LOADER_COMPRESS=y
CONFIG_FW_LOADER_COMPRESS_XZ=y
CONFIG_FW_LOADER_COMPRESS_ZSTD=y
CONFIG_FW_CACHE=y
# CONFIG_FW_UPLOAD is not set
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
CONFIG_DEBUG_DEVRES=y
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SCCB=m
CONFIG_MALI_BASE_MODULES=y
CONFIG_DMA_SHARED_BUFFER_TEST_EXPORTER=y
CONFIG_MALI_MEMORY_GROUP_MANAGER=y
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
# CONFIG_BRCMSTB_GISB_ARB is not set
# CONFIG_MOXTET is not set
# CONFIG_VEXPRESS_CONFIG is not set
CONFIG_MHI_BUS=m
# CONFIG_MHI_BUS_DEBUG is not set
CONFIG_MHI_BUS_PCI_GENERIC=m
CONFIG_MHI_BUS_EP=m
# end of Bus devices

CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y

#
# Firmware Drivers
#

#
# ARM System Control and Management Interface Protocol
#
CONFIG_ARM_SCMI_PROTOCOL=y
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
CONFIG_ARM_SCMI_HAVE_SHMEM=y
CONFIG_ARM_SCMI_HAVE_MSG=y
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set
CONFIG_ARM_SCMI_POWER_DOMAIN=y
CONFIG_ARM_SCMI_POWER_CONTROL=y
# end of ARM System Control and Management Interface Protocol

CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
CONFIG_ARM_SDE_INTERFACE=y
CONFIG_FIRMWARE_MEMMAP=y
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=y
# CONFIG_ISCSI_IBFT is not set
CONFIG_FW_CFG_SYSFS=m
CONFIG_FW_CFG_SYSFS_CMDLINE=y
CONFIG_ROCKCHIP_SIP=y
# CONFIG_SYSFB_SIMPLEFB is not set
# CONFIG_ARM_FFA_TRANSPORT is not set
CONFIG_CS_DSP=m
# CONFIG_GOOGLE_FIRMWARE is not set

#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_VARS_PSTORE=y
# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_GENERIC_STUB=y
# CONFIG_EFI_ZBOOT is not set
CONFIG_EFI_ARMSTUB_DTB_LOADER=y
CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
# CONFIG_EFI_BOOTLOADER_CONTROL is not set
# CONFIG_EFI_CAPSULE_LOADER is not set
# CONFIG_EFI_TEST is not set
# CONFIG_RESET_ATTACK_MITIGATION is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
# CONFIG_EFI_DISABLE_RUNTIME is not set
# CONFIG_EFI_COCO_SECRET is not set
# end of EFI (Extensible Firmware Interface) Support

CONFIG_UEFI_CPER=y
CONFIG_UEFI_CPER_ARM=y
CONFIG_ARM_PSCI_FW=y
CONFIG_ARM_PSCI_CHECKER=y
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_ARM_SMCCC_SOC_ID=y

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_GNSS=m
CONFIG_GNSS_SERIAL=m
CONFIG_GNSS_MTK_SERIAL=m
CONFIG_GNSS_SIRF_SERIAL=m
CONFIG_GNSS_UBX_SERIAL=m
CONFIG_GNSS_USB=m
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_OF_PARTS=y
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y

#
# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
#
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_MCHP48L640 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
CONFIG_MTD_BLOCK2MTD=m

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
CONFIG_MTD_NAND_CORE=y
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NAND_DEVICE_AUTOSELECT=y
CONFIG_MTD_SPI_NAND_ATO=y
CONFIG_MTD_SPI_NAND_BIWIN=y
CONFIG_MTD_SPI_NAND_DOSILICON=y
CONFIG_MTD_SPI_NAND_ESMT=y
CONFIG_MTD_SPI_NAND_ETRON=y
CONFIG_MTD_SPI_NAND_FMSH=y
CONFIG_MTD_SPI_NAND_FORESEE=y
CONFIG_MTD_SPI_NAND_GIGADEVICE=y
CONFIG_MTD_SPI_NAND_GSTO=y
CONFIG_MTD_SPI_NAND_HIKSEMI=y
CONFIG_MTD_SPI_NAND_HYF=y
CONFIG_MTD_SPI_NAND_JSC=y
CONFIG_MTD_SPI_NAND_MACRONIX=y
CONFIG_MTD_SPI_NAND_MICRON=y
CONFIG_MTD_SPI_NAND_PARAGON=y
CONFIG_MTD_SPI_NAND_SILICONGO=y
CONFIG_MTD_SPI_NAND_SKYHIGH=y
CONFIG_MTD_SPI_NAND_TOSHIBA=y
CONFIG_MTD_SPI_NAND_UNIM=y
CONFIG_MTD_SPI_NAND_WINBOND=y
CONFIG_MTD_SPI_NAND_XINCUN=y
CONFIG_MTD_SPI_NAND_XTX=y
CONFIG_MTD_SPI_NAND_ZBIT=y

#
# ECC engine support
#
CONFIG_MTD_NAND_ECC=y
# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
# CONFIG_MTD_NAND_ECC_MXIC is not set
CONFIG_MTD_NAND_BBT_USING_FLASH=y
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
CONFIG_MTD_SPI_NOR_MISC=y
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
CONFIG_MTD_SPI_NOR_DEVICE_AUTOSELECT=y
CONFIG_MTD_SPI_NOR_ATMEL=y
CONFIG_MTD_SPI_NOR_BOYA=y
CONFIG_MTD_SPI_NOR_CATALYST=y
CONFIG_MTD_SPI_NOR_DOSILICON=y
CONFIG_MTD_SPI_NOR_EON=y
CONFIG_MTD_SPI_NOR_ESMT=y
CONFIG_MTD_SPI_NOR_EVERSPIN=y
CONFIG_MTD_SPI_NOR_FMSH=y
CONFIG_MTD_SPI_NOR_FUJITSU=y
CONFIG_MTD_SPI_NOR_GIGADEVICE=y
CONFIG_MTD_SPI_NOR_INTEL=y
CONFIG_MTD_SPI_NOR_ISSI=y
CONFIG_MTD_SPI_NOR_MACRONIX=y
CONFIG_MTD_SPI_NOR_NORMEM=y
CONFIG_MTD_SPI_NOR_PUYA=y
CONFIG_MTD_SPI_NOR_SPANSION=y
CONFIG_MTD_SPI_NOR_STMICRO=y
CONFIG_MTD_SPI_NOR_SST=y
CONFIG_MTD_SPI_NOR_WINBOND=y
CONFIG_MTD_SPI_NOR_XILINX=y
CONFIG_MTD_SPI_NOR_XMC=y
CONFIG_MTD_SPI_NOR_XTX=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
# CONFIG_MTD_UBI_BLOCK is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_DTC_SYMBOLS is not set
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_NULL_BLK is not set
CONFIG_CDROM=m
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
CONFIG_ZRAM=y
CONFIG_ZRAM_DEF_COMP_LZORLE=y
# CONFIG_ZRAM_DEF_COMP_ZSTD is not set
# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
# CONFIG_ZRAM_DEF_COMP_LZO is not set
# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
# CONFIG_ZRAM_DEF_COMP_842 is not set
CONFIG_ZRAM_DEF_COMP="lzo-rle"
# CONFIG_ZRAM_WRITEBACK is not set
# CONFIG_ZRAM_MEMORY_TRACKING is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
CONFIG_BLK_DEV_DRBD=m
# CONFIG_DRBD_FAULT_INJECTION is not set
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_VIRTIO_BLK=m
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_UBLK is not set

#
# NVME Support
#
CONFIG_NVME_COMMON=y
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
CONFIG_NVME_MULTIPATH=y
CONFIG_NVME_VERBOSE_ERRORS=y
CONFIG_NVME_HWMON=y
CONFIG_NVME_FABRICS=m
CONFIG_NVME_FC=m
CONFIG_NVME_TCP=m
CONFIG_NVME_AUTH=y
CONFIG_NVME_TARGET=m
CONFIG_NVME_TARGET_PASSTHRU=y
CONFIG_NVME_TARGET_LOOP=m
CONFIG_NVME_TARGET_FC=m
CONFIG_NVME_TARGET_FCLOOP=m
CONFIG_NVME_TARGET_TCP=m
CONFIG_NVME_TARGET_AUTH=y
# end of NVME Support

#
# Misc devices
#

#
# RK628 misc driver
#
CONFIG_RK628_MISC=y
CONFIG_RK628_MISC_HDMITX=y
CONFIG_RK628_MISC_GPIO_TEST=y
# CONFIG_ROCKCHIP_THUNDER_BOOT_RK628 is not set
# end of RK628 misc driver

CONFIG_RK803=m
# CONFIG_CONFIG_ROCKPI_MCU is not set
# CONFIG_PCIE_FUNC_RKEP is not set

#
# misc vehicle setting
#
# CONFIG_VEHICLE_CORE is not set
# CONFIG_VEHICLE_GPIO_MCU_EXPANDER is not set
# CONFIG_VEHICLE_DRIVER_OREO is not set
# end of misc vehicle setting

# CONFIG_LT7911D_FB_NOTIFIER is not set
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
CONFIG_TIFM_CORE=m
CONFIG_TIFM_7XX1=m
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
# CONFIG_DW_XDATA_PCIE is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_XILINX_SDFEC is not set
CONFIG_MISC_RTSX=m
# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_OPEN_DICE is not set
# CONFIG_VCPU_STALL_DETECTOR is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
CONFIG_EEPROM_AT24=m
CONFIG_EEPROM_AT25=m
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
CONFIG_EEPROM_93CX6=m
CONFIG_EEPROM_93XX46=m
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

# CONFIG_CB710_CORE is not set

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline

# CONFIG_SENSORS_LIS3_I2C is not set
CONFIG_ALTERA_STAPL=m
# CONFIG_VMWARE_VMCI is not set
# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_BCM_VK is not set
# CONFIG_MISC_ALCOR_PCI is not set
CONFIG_MISC_RTSX_PCI=m
CONFIG_MISC_RTSX_USB=m
# CONFIG_HABANA_AI is not set
# CONFIG_UACCE is not set
# CONFIG_PVPANIC is not set
# CONFIG_GP_PCI1XXXX is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
CONFIG_RAID_ATTRS=m
CONFIG_SCSI_COMMON=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=m
# CONFIG_CHR_DEV_ST is not set
CONFIG_BLK_DEV_SR=m
# CONFIG_CHR_DEV_SG is not set
CONFIG_BLK_DEV_BSG=y
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
CONFIG_SCSI_SCAN_ASYNC=y

#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=m
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=m
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_ISCSI_BOOT_SYSFS=m
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_MPI3MR is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_FDOMAIN_PCI is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
CONFIG_SCSI_VIRTIO=m
# CONFIG_SCSI_DH is not set
# end of SCSI device support

CONFIG_ATA=y
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_ARCH_WANT_LIBATA_LEDS=y
CONFIG_ATA_LEDS=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_AHCI_DWC=y
CONFIG_AHCI_CEVA=m
CONFIG_AHCI_QORIQ=m
CONFIG_SATA_INIC162X=m
CONFIG_SATA_ACARD_AHCI=m
CONFIG_SATA_SIL24=m
# CONFIG_ATA_SFF is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
# CONFIG_MD_CLUSTER is not set
CONFIG_BCACHE=m
# CONFIG_BCACHE_DEBUG is not set
# CONFIG_BCACHE_CLOSURES_DEBUG is not set
# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=m
# CONFIG_DM_DEBUG is not set
CONFIG_DM_BUFIO=m
# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
# CONFIG_DM_UNSTRIPED is not set
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
CONFIG_DM_CACHE=m
CONFIG_DM_CACHE_SMQ=m
CONFIG_DM_WRITECACHE=m
# CONFIG_DM_EBS is not set
CONFIG_DM_ERA=m
# CONFIG_DM_CLONE is not set
CONFIG_DM_MIRROR=m
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
# CONFIG_DM_MULTIPATH_HST is not set
# CONFIG_DM_MULTIPATH_IOA is not set
CONFIG_DM_DELAY=m
# CONFIG_DM_DUST is not set
# CONFIG_DM_UEVENT is not set
CONFIG_DM_FLAKEY=m
CONFIG_DM_VERITY=m
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
# CONFIG_DM_VERITY_FEC is not set
CONFIG_DM_SWITCH=m
CONFIG_DM_LOG_WRITES=m
# CONFIG_DM_INTEGRITY is not set
# CONFIG_DM_ZONED is not set
# CONFIG_DM_AUDIT is not set
# CONFIG_TARGET_CORE is not set
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
# end of IEEE 1394 (FireWire) support

CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_WIREGUARD=m
# CONFIG_WIREGUARD_DEBUG is not set
CONFIG_EQUALIZER=m
# CONFIG_NET_FC is not set
CONFIG_IFB=m
CONFIG_NET_TEAM=m
CONFIG_NET_TEAM_MODE_BROADCAST=m
CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
CONFIG_NET_TEAM_MODE_RANDOM=m
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
CONFIG_NET_TEAM_MODE_LOADBALANCE=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=m
CONFIG_IPVTAP=m
CONFIG_VXLAN=m
CONFIG_GENEVE=m
CONFIG_BAREUDP=m
CONFIG_GTP=m
CONFIG_AMT=m
CONFIG_MACSEC=m
CONFIG_NETCONSOLE=m
# CONFIG_NETCONSOLE_DYNAMIC is not set
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=m
CONFIG_TAP=m
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_NLMON=m
CONFIG_NET_VRF=m
CONFIG_VSOCKMON=m
CONFIG_MHI_NET=m
# CONFIG_ARCNET is not set

#
# Distributed Switch Architecture drivers
#
CONFIG_B53=m
# CONFIG_B53_SPI_DRIVER is not set
# CONFIG_B53_MDIO_DRIVER is not set
# CONFIG_B53_MMAP_DRIVER is not set
# CONFIG_B53_SRAB_DRIVER is not set
# CONFIG_B53_SERDES is not set
CONFIG_NET_DSA_BCM_SF2=m
CONFIG_NET_DSA_LOOP=m
CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
CONFIG_NET_DSA_LANTIQ_GSWIP=m
CONFIG_NET_DSA_MT7530=m
CONFIG_NET_DSA_MT7530_MDIO=m
CONFIG_NET_DSA_MT7530_MMIO=m
CONFIG_NET_DSA_MV88E6060=m
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
# CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C is not set
# CONFIG_NET_DSA_MICROCHIP_KSZ_SPI is not set
# CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI is not set
CONFIG_NET_DSA_MV88E6XXX=m
CONFIG_NET_DSA_MV88E6XXX_PTP=y
CONFIG_NET_DSA_AR9331=m
CONFIG_NET_DSA_QCA8K=m
# CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT is not set
CONFIG_NET_DSA_SJA1105=m
CONFIG_NET_DSA_SJA1105_PTP=y
CONFIG_NET_DSA_SJA1105_TAS=y
CONFIG_NET_DSA_SJA1105_VL=y
CONFIG_NET_DSA_XRS700X=m
CONFIG_NET_DSA_XRS700X_I2C=m
CONFIG_NET_DSA_XRS700X_MDIO=m
CONFIG_NET_DSA_REALTEK=m
CONFIG_NET_DSA_REALTEK_MDIO=m
CONFIG_NET_DSA_REALTEK_SMI=m
CONFIG_NET_DSA_REALTEK_RTL8365MB=m
CONFIG_NET_DSA_REALTEK_RTL8366RB=m
CONFIG_NET_DSA_SMSC_LAN9303=m
CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
CONFIG_NET_DSA_VITESSE_VSC73XX=m
CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
# end of Distributed Switch Architecture drivers

CONFIG_ETHERNET=y
CONFIG_MDIO=m
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_ALTERA_TSE is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
CONFIG_NET_VENDOR_ASIX=y
# CONFIG_SPI_AX88796C is not set
# CONFIG_NET_VENDOR_ATHEROS is not set
CONFIG_NET_VENDOR_MOTORCOMM=y
# CONFIG_FUXI is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_CORTINA is not set
CONFIG_NET_VENDOR_DAVICOM=y
# CONFIG_DM9051 is not set
# CONFIG_DNET is not set
# CONFIG_NET_VENDOR_DEC is not set
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
CONFIG_NET_VENDOR_ENGLEDER=y
# CONFIG_TSNEP is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
CONFIG_NET_VENDOR_FUNGIBLE=y
# CONFIG_FUN_ETH is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_I825XX is not set
CONFIG_NET_VENDOR_INTEL=y
# CONFIG_E100 is not set
CONFIG_E1000=m
CONFIG_E1000E=m
CONFIG_IGB=m
# CONFIG_IGB_HWMON is not set
CONFIG_IGBVF=m
CONFIG_IXGB=m
CONFIG_IXGBE=m
CONFIG_IXGBE_HWMON=y
CONFIG_IXGBE_IPSEC=y
CONFIG_IXGBEVF=m
CONFIG_IXGBEVF_IPSEC=y
CONFIG_I40E=m
# CONFIG_I40EVF is not set
# CONFIG_ICE is not set
# CONFIG_FM10K is not set
CONFIG_IGC=m
# CONFIG_JME is not set
CONFIG_NET_VENDOR_ADI=y
# CONFIG_ADIN1110 is not set
CONFIG_NET_VENDOR_LITEX=y
# CONFIG_LITEX_LITEETH is not set
# CONFIG_NET_VENDOR_MARVELL is not set
CONFIG_NET_VENDOR_MELLANOX=y
CONFIG_MLX4_EN=m
CONFIG_MLX4_CORE=m
CONFIG_MLX4_DEBUG=y
CONFIG_MLX4_CORE_GEN2=y
CONFIG_MLX5_CORE=m
CONFIG_MLX5_FPGA=y
CONFIG_MLX5_CORE_EN=y
CONFIG_MLX5_EN_ARFS=y
CONFIG_MLX5_EN_RXNFC=y
CONFIG_MLX5_MPFS=y
CONFIG_MLX5_ESWITCH=y
CONFIG_MLX5_BRIDGE=y
CONFIG_MLX5_CLS_ACT=y
CONFIG_MLX5_TC_SAMPLE=y
CONFIG_MLX5_CORE_IPOIB=y
# CONFIG_MLX5_EN_MACSEC is not set
CONFIG_MLX5_EN_IPSEC=y
# CONFIG_MLX5_EN_TLS is not set
CONFIG_MLX5_SW_STEERING=y
# CONFIG_MLX5_SF is not set
CONFIG_MLXSW_CORE=m
CONFIG_MLXSW_CORE_HWMON=y
CONFIG_MLXSW_CORE_THERMAL=y
CONFIG_MLXSW_PCI=m
CONFIG_MLXSW_I2C=m
CONFIG_MLXSW_SPECTRUM=m
CONFIG_MLXSW_MINIMAL=m
CONFIG_MLXFW=m
# CONFIG_MLXBF_GIGE is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
CONFIG_NET_VENDOR_MICROSOFT=y
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_FEALNX is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETERION is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_BROCADE is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCA7000_UART is not set
# CONFIG_QCOM_EMAC is not set
CONFIG_SFE_SUPPORT_IPV6=y
CONFIG_SFE_ECM=y
CONFIG_FAST_CLASSIFIER=y
# CONFIG_RMNET is not set
# CONFIG_NET_VENDOR_RDC is not set
CONFIG_NET_VENDOR_REALTEK=y
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
CONFIG_R8125=m
CONFIG_R8125_SOC_LAN=y
# CONFIG_R8125_REALWOW_SUPPORT is not set
# CONFIG_R8125_DASH_SUPPORT is not set
# CONFIG_R8125_DOWN_SPEED_100 is not set
# CONFIG_R8125_ASPM is not set
CONFIG_R8125_WOL_SUPPORT=y
CONFIG_R8125_S5WOL=y
# CONFIG_R8125_S5_KEEP_CURR_MAC is not set
# CONFIG_R8125_EEE is not set
# CONFIG_R8125_S0_MAGIC_PACKET is not set
CONFIG_R8125_TX_NO_CLOSE=y
CONFIG_R8125_MULTI_MSIX_VECTOR=y
CONFIG_R8125_MULTIPLE_TX_QUEUE=y
CONFIG_R8125_RSS_SUPPORT=y
# CONFIG_R8125_PTP_SUPPORT is not set
CONFIG_R8125_FIBER_SUPPORT=y
CONFIG_R8125_USE_FIRMWARE_FILE=y
# CONFIG_R8125_DOUBLE_VLAN is not set
# CONFIG_R8125_PAGE_REUSE is not set
CONFIG_R8125_GIGA_LITE=y
CONFIG_R8126=m
CONFIG_R8126_SOC_LAN=y
# CONFIG_R8126_REALWOW_SUPPORT is not set
# CONFIG_R8126_DASH_SUPPORT is not set
# CONFIG_R8126_DOWN_SPEED_100 is not set
# CONFIG_R8126_ASPM is not set
CONFIG_R8126_WOL_SUPPORT=y
CONFIG_R8126_S5WOL=y
# CONFIG_R8126_S5_KEEP_CURR_MAC is not set
# CONFIG_R8126_EEE is not set
# CONFIG_R8126_S0_MAGIC_PACKET is not set
CONFIG_R8126_TX_NO_CLOSE=y
CONFIG_R8126_MULTI_MSIX_VECTOR=y
CONFIG_R8126_MULTIPLE_TX_QUEUE=y
CONFIG_R8126_RSS_SUPPORT=y
CONFIG_R8126_PTP_SUPPORT=y
CONFIG_R8126_FIBER_SUPPORT=y
CONFIG_R8126_USE_FIRMWARE_FILE=y
# CONFIG_R8126_DOUBLE_VLAN is not set
# CONFIG_R8126_PAGE_REUSE is not set
CONFIG_R8126_GIGA_LITE=y
CONFIG_R8168=m
CONFIG_R8168_SOC_LAN=y
# CONFIG_R8168_FIBER_SUPPORT is not set
# CONFIG_R8168_REALWOW_SUPPORT is not set
# CONFIG_R8168_DASH_SUPPORT is not set
# CONFIG_R8168_DOWN_SPEED_100 is not set
# CONFIG_R8168_ASPM is not set
CONFIG_R8168_WOL_SUPPORT=y
CONFIG_R8168_S5WOL=y
# CONFIG_R8168_S5_KEEP_CURR_MAC is not set
# CONFIG_R8168_EEE is not set
# CONFIG_R8168_S0_MAGIC_PACKET is not set
CONFIG_R8168_USE_FIRMWARE_FILE=y
# CONFIG_R8168_CTAP_SHORT_OFF is not set
# CONFIG_R8168_MULTIPLE_TX_QUEUE is not set
# CONFIG_R8168_RSS_SUPPORT is not set
CONFIG_R8168_GIGA_LITE=y
# CONFIG_R8169 is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
# CONFIG_STMMAC_SELFTESTS is not set
# CONFIG_STMMAC_UIO is not set
CONFIG_STMMAC_ETHTOOL=y
CONFIG_STMMAC_FULL=y
CONFIG_STMMAC_PLATFORM=y
# CONFIG_DWMAC_DWC_QOS_ETH is not set
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_ROCKCHIP=y
CONFIG_DWMAC_ROCKCHIP_TOOL=y
# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
CONFIG_NET_VENDOR_VERTEXCOM=y
# CONFIG_MSE102X is not set
# CONFIG_NET_VENDOR_VIA is not set
CONFIG_NET_VENDOR_WANGXUN=y
# CONFIG_NGBE is not set
# CONFIG_TXGBE is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_NET_SB1000 is not set
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_PHYLIB_LEDS=y
CONFIG_FIXED_PHY=y
# CONFIG_SFP is not set

#
# Switch configuration API + drivers
#
CONFIG_SWCONFIG=m
CONFIG_SWCONFIG_LEDS=y
CONFIG_RTL8306_PHY=m
CONFIG_RTL8366_SMI=m
CONFIG_RTL8366_SMI_DEBUG_FS=y
CONFIG_RTL8366S_PHY=m
CONFIG_RTL8366RB_PHY=m
CONFIG_RTL8367_PHY=m
CONFIG_RTL8367B_PHY=m

#
# MII PHY device drivers
#
# CONFIG_AIR_EN8811H_PHY is not set
# CONFIG_AMD_PHY is not set
# CONFIG_ADIN_PHY is not set
# CONFIG_ADIN1100_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
CONFIG_AX88796B_PHY=m
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM54140_PHY is not set
CONFIG_BCM7XXX_PHY=m
# CONFIG_BCM84881_PHY is not set
# CONFIG_BCM87XX_PHY is not set
CONFIG_BCM_NET_PHYLIB=m
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
CONFIG_ICPLUS_PHY=y
# CONFIG_LXT_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MARVELL_88X2222_PHY is not set
# CONFIG_MAXLINEAR_GPHY is not set
CONFIG_MEDIATEK_GE_PHY=m
# CONFIG_MICREL_PHY is not set
CONFIG_MICROCHIP_PHY=m
# CONFIG_MICROCHIP_T1_PHY is not set
CONFIG_MICROSEMI_PHY=m
CONFIG_MOTORCOMM_PHY=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_NXP_C45_TJA11XX_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
# CONFIG_AT803X_PHY is not set
# CONFIG_QCA83XX_PHY is not set
# CONFIG_QCA808X_PHY is not set
# CONFIG_QCA807X_PHY is not set
# CONFIG_QSEMI_PHY is not set
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_FEPHY=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_RK630_PHY=y
CONFIG_SMSC_PHY=m
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
# CONFIG_DP83869_PHY is not set
# CONFIG_DP83TD510_PHY is not set
CONFIG_VITESSE_PHY=m
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_PSE_CONTROLLER is not set
CONFIG_CAN_DEV=m
CONFIG_CAN_VCAN=m
CONFIG_CAN_VXCAN=m
CONFIG_CAN_NETLINK=y
CONFIG_CAN_CALC_BITTIMING=y
CONFIG_CAN_RX_OFFLOAD=y
CONFIG_CAN_CAN327=m
# CONFIG_CAN_FLEXCAN is not set
# CONFIG_CAN_GRCAN is not set
# CONFIG_CAN_KVASER_PCIEFD is not set
CONFIG_CAN_SLCAN=m
# CONFIG_CAN_XILINXCAN is not set
# CONFIG_CAN_C_CAN is not set
# CONFIG_CAN_CC770 is not set
# CONFIG_CAN_CTUCANFD_PCI is not set
# CONFIG_CAN_CTUCANFD_PLATFORM is not set
# CONFIG_CAN_IFI_CANFD is not set
# CONFIG_CAN_M_CAN is not set
# CONFIG_CAN_PEAK_PCIEFD is not set
CONFIG_CAN_ROCKCHIP=m
CONFIG_CANFD_ROCKCHIP=m
CONFIG_CAN_RK3562=m
CONFIG_CANFD_RK3576=m
# CONFIG_CAN_SJA1000 is not set
# CONFIG_CAN_SOFTING is not set

#
# CAN SPI interfaces
#
CONFIG_CAN_HI311X=m
CONFIG_CAN_MCP251X=m
CONFIG_CAN_MCP251XFD=m
CONFIG_CAN_MCP251XFD_SANITY=y
# end of CAN SPI interfaces

#
# CAN USB interfaces
#
CONFIG_CAN_8DEV_USB=m
CONFIG_CAN_EMS_USB=m
CONFIG_CAN_ESD_USB=m
CONFIG_CAN_ETAS_ES58X=m
CONFIG_CAN_GS_USB=m
CONFIG_CAN_KVASER_USB=m
CONFIG_CAN_MCBA_USB=m
CONFIG_CAN_PEAK_USB=m
CONFIG_CAN_UCAN=m
# end of CAN USB interfaces

CONFIG_CAN_DEBUG_DEVICES=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_FWNODE_MDIO=y
CONFIG_OF_MDIO=y
CONFIG_ACPI_MDIO=y
CONFIG_MDIO_DEVRES=y
# CONFIG_MDIO_BITBANG is not set
CONFIG_MDIO_BCM_UNIMAC=m
# CONFIG_MDIO_HISI_FEMAC is not set
# CONFIG_MDIO_MVUSB is not set
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_OCTEON is not set
# CONFIG_MDIO_IPQ4019 is not set
# CONFIG_MDIO_IPQ8064 is not set
# CONFIG_MDIO_THUNDER is not set

#
# MDIO Multiplexers
#
# CONFIG_MDIO_BUS_MUX_GPIO is not set
# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
# CONFIG_MDIO_BUS_MUX_MMIOREG is not set

#
# PCS device drivers
#
CONFIG_PCS_XPCS=y
# CONFIG_PCS_MTK_USXGMII is not set
CONFIG_PCS_MTK_LYNXI=m
# end of PCS device drivers

CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
# CONFIG_PPP_FILTER is not set
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=m
CONFIG_PPTP=m
CONFIG_PPPOL2TP=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
# CONFIG_SLIP is not set
CONFIG_SLHC=m
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_AX8817X=m
CONFIG_USB_NET_AX88179_178A=m
CONFIG_USB_NET_CDCETHER=m
CONFIG_USB_NET_CDC_EEM=m
CONFIG_USB_NET_CDC_NCM=m
CONFIG_USB_NET_HUAWEI_CDC_NCM=m
CONFIG_USB_NET_CDC_MBIM=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9700=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
CONFIG_USB_NET_CDC_SUBSET=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
# CONFIG_USB_ARMLINUX is not set
# CONFIG_USB_EPSON2888 is not set
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=m
CONFIG_USB_NET_CX82310_ETH=m
CONFIG_USB_NET_KALMIA=m
CONFIG_USB_NET_QMI_WWAN=m
CONFIG_USB_HSO=m
CONFIG_USB_NET_INT51X1=m
CONFIG_USB_IPHETH=m
CONFIG_USB_SIERRA_NET=m
CONFIG_USB_VL600=m
CONFIG_USB_NET_CH9200=m
CONFIG_USB_NET_AQC111=m
CONFIG_USB_RTL8153_ECM=m
CONFIG_WLAN=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
CONFIG_WLAN_VENDOR_AIC=y
CONFIG_AIC8800_SUPPORT=y
CONFIG_AIC8800_SDIO_WLAN=y
CONFIG_AIC8800_SDIO_FW_PATH="/lib/firmware/aic8800_sdio"
CONFIG_AIC8800_USB_WLAN=y
CONFIG_AIC8800_USB_FW_PATH="/lib/firmware/aic8800_usb"
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
CONFIG_ATH_USER_REGD=y
# CONFIG_ATH_DEBUG is not set
CONFIG_ATH5K=m
# CONFIG_ATH5K_DEBUG is not set
# CONFIG_ATH5K_TRACER is not set
CONFIG_ATH5K_PCI=y
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=m
CONFIG_ATH9K_PCI=y
# CONFIG_ATH9K_AHB is not set
# CONFIG_ATH9K_DEBUGFS is not set
# CONFIG_ATH9K_DYNACK is not set
# CONFIG_ATH9K_WOW is not set
CONFIG_ATH9K_RFKILL=y
# CONFIG_ATH9K_CHANNEL_CONTEXT is not set
CONFIG_ATH9K_PCOEM=y
CONFIG_ATH9K_PCI_NO_EEPROM=y
# CONFIG_ATH9K_HTC is not set
CONFIG_ATH9K_HWRNG=y
CONFIG_CARL9170=m
CONFIG_CARL9170_LEDS=y
CONFIG_CARL9170_WPC=y
CONFIG_CARL9170_HWRNG=y
CONFIG_ATH6KL=m
# CONFIG_ATH6KL_SDIO is not set
CONFIG_ATH6KL_USB=m
# CONFIG_ATH6KL_DEBUG is not set
# CONFIG_ATH6KL_TRACING is not set
CONFIG_AR5523=m
# CONFIG_WIL6210 is not set
CONFIG_ATH10K=m
CONFIG_ATH10K_CE=y
CONFIG_ATH10K_PCI=m
# CONFIG_ATH10K_AHB is not set
# CONFIG_ATH10K_SDIO is not set
CONFIG_ATH10K_USB=m
# CONFIG_ATH10K_DEBUG is not set
# CONFIG_ATH10K_DEBUGFS is not set
CONFIG_ATH10K_LEDS=y
# CONFIG_ATH10K_TRACING is not set
CONFIG_ATH10K_THERMAL=y
CONFIG_WCN36XX=m
# CONFIG_WCN36XX_DEBUGFS is not set
CONFIG_ATH11K=m
CONFIG_ATH11K_PCI=m
# CONFIG_ATH11K_DEBUG is not set
# CONFIG_ATH11K_TRACING is not set
CONFIG_ATH11K_THERMAL=y
# CONFIG_WLAN_VENDOR_ATMEL is not set
CONFIG_WLAN_VENDOR_BROADCOM=y
# CONFIG_B43 is not set
# CONFIG_B43LEGACY is not set
CONFIG_BRCMUTIL=m
# CONFIG_BRCMSMAC is not set
CONFIG_BRCMFMAC=m
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_PROTO_MSGBUF=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
CONFIG_BRCMFMAC_PCIE=y
CONFIG_BRCM_TRACING=y
# CONFIG_BRCMDBG is not set
# CONFIG_WLAN_VENDOR_CISCO is not set
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_IPW2100=m
# CONFIG_IPW2100_MONITOR is not set
# CONFIG_IPW2100_DEBUG is not set
CONFIG_IPW2200=m
# CONFIG_IPW2200_MONITOR is not set
# CONFIG_IPW2200_QOS is not set
# CONFIG_IPW2200_DEBUG is not set
CONFIG_LIBIPW=m
# CONFIG_LIBIPW_DEBUG is not set
CONFIG_IWLEGACY=m
CONFIG_IWL4965=m
CONFIG_IWL3945=m

#
# iwl3945 / iwl4965 Debugging Options
#
# CONFIG_IWLEGACY_DEBUG is not set
# end of iwl3945 / iwl4965 Debugging Options

CONFIG_IWLWIFI=m
CONFIG_IWLWIFI_LEDS=y
CONFIG_IWLDVM=m
CONFIG_IWLMVM=m
CONFIG_IWLWIFI_OPMODE_MODULAR=y

#
# Debugging Options
#
# CONFIG_IWLWIFI_DEBUG is not set
# CONFIG_IWLWIFI_DEVICE_TRACING is not set
# end of Debugging Options

# CONFIG_WLAN_VENDOR_INTERSIL is not set
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_USB=m
CONFIG_LIBERTAS_SDIO=m
CONFIG_LIBERTAS_SPI=m
# CONFIG_LIBERTAS_DEBUG is not set
# CONFIG_LIBERTAS_MESH is not set
CONFIG_LIBERTAS_THINFIRM=m
# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
CONFIG_LIBERTAS_THINFIRM_USB=m
# CONFIG_MWIFIEX is not set
CONFIG_MWL8K=m
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=m
CONFIG_MT76_CORE=m
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=m
CONFIG_MT76_SDIO=m
CONFIG_MT76x02_LIB=m
CONFIG_MT76x02_USB=m
CONFIG_MT76_CONNAC_LIB=m
CONFIG_MT792x_LIB=m
CONFIG_MT792x_USB=m
CONFIG_MT76x0_COMMON=m
CONFIG_MT76x0U=m
CONFIG_MT76x0E=m
CONFIG_MT76x2_COMMON=m
CONFIG_MT76x2E=m
CONFIG_MT76x2U=m
CONFIG_MT7603E=m
CONFIG_MT7615_COMMON=m
CONFIG_MT7615E=m
CONFIG_MT7663_USB_SDIO_COMMON=m
CONFIG_MT7663U=m
CONFIG_MT7663S=m
CONFIG_MT7915E=m
CONFIG_MT7921_COMMON=m
CONFIG_MT7921E=m
CONFIG_MT7921S=m
CONFIG_MT7921U=m
CONFIG_MT7996E=m
CONFIG_WLAN_VENDOR_MICROCHIP=y
CONFIG_WILC1000=m
CONFIG_WILC1000_SDIO=m
CONFIG_WILC1000_SPI=m
CONFIG_WILC1000_HW_OOB_INTR=y
CONFIG_WLAN_VENDOR_PURELIFI=y
# CONFIG_PLFXLC is not set
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=m
CONFIG_RT2400PCI=m
CONFIG_RT2500PCI=m
CONFIG_RT61PCI=m
CONFIG_RT2800PCI=m
CONFIG_RT2800PCI_RT33XX=y
CONFIG_RT2800PCI_RT35XX=y
CONFIG_RT2800PCI_RT53XX=y
CONFIG_RT2800PCI_RT3290=y
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
CONFIG_RT2800USB_RT33XX=y
CONFIG_RT2800USB_RT35XX=y
CONFIG_RT2800USB_RT3573=y
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
# CONFIG_RT2800USB_UNKNOWN is not set
CONFIG_RT2800_LIB=m
CONFIG_RT2800_LIB_MMIO=m
CONFIG_RT2X00_LIB_MMIO=m
CONFIG_RT2X00_LIB_PCI=m
CONFIG_RT2X00_LIB_USB=m
CONFIG_RT2X00_LIB=m
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
# CONFIG_RT2X00_DEBUG is not set
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_RTL8180=m
CONFIG_RTL8187=m
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=m
CONFIG_RTL8192CE=m
CONFIG_RTL8192SE=m
CONFIG_RTL8192DE=m
CONFIG_RTL8723AE=m
CONFIG_RTL8723BE=m
CONFIG_RTL8188EE=m
CONFIG_RTL8192EE=m
CONFIG_RTL8821AE=m
CONFIG_RTL8192CU=m
CONFIG_RTLWIFI=m
CONFIG_RTLWIFI_PCI=m
CONFIG_RTLWIFI_USB=m
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8723_COMMON=m
CONFIG_RTLBTCOEXIST=m
CONFIG_RTL8XXXU=m
# CONFIG_RTL8XXXU_UNTESTED is not set
CONFIG_RTW88=m
CONFIG_RTW88_CORE=m
CONFIG_RTW88_PCI=m
CONFIG_RTW88_SDIO=m
CONFIG_RTW88_USB=m
CONFIG_RTW88_8822B=m
CONFIG_RTW88_8822C=m
CONFIG_RTW88_8723X=m
CONFIG_RTW88_8703B=m
CONFIG_RTW88_8723D=m
CONFIG_RTW88_8821C=m
CONFIG_RTW88_8822BE=m
CONFIG_RTW88_8822BS=m
CONFIG_RTW88_8822BU=m
CONFIG_RTW88_8822CE=m
CONFIG_RTW88_8822CS=m
CONFIG_RTW88_8822CU=m
CONFIG_RTW88_8723DE=m
CONFIG_RTW88_8723DS=m
CONFIG_RTW88_8723CS=m
CONFIG_RTW88_8723DU=m
CONFIG_RTW88_8821CE=m
CONFIG_RTW88_8821CS=m
CONFIG_RTW88_8821CU=m
# CONFIG_RTW88_DEBUG is not set
# CONFIG_RTW88_DEBUGFS is not set
CONFIG_RTW89=m
CONFIG_RTW89_CORE=m
CONFIG_RTW89_PCI=m
CONFIG_RTW89_8851B=m
CONFIG_RTW89_8852A=m
CONFIG_RTW89_8852B=m
CONFIG_RTW89_8852C=m
CONFIG_RTW89_8851BE=m
CONFIG_RTW89_8852AE=m
CONFIG_RTW89_8852BE=m
CONFIG_RTW89_8852CE=m
# CONFIG_RTW89_DEBUGMSG is not set
# CONFIG_RTW89_DEBUGFS is not set
CONFIG_WL_ROCKCHIP=m
CONFIG_WIFI_BUILD_MODULE=y
# CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP is not set
# CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR is not set
CONFIG_BCMDHD=y
CONFIG_AP6XXX=m
# CONFIG_BCMDHD_SDIO is not set
CONFIG_BCMDHD_PCIE=y
CONFIG_BCMDHD_FW_PATH="/vendor/etc/firmware/fw_bcmdhd.bin"
CONFIG_BCMDHD_NVRAM_PATH="/vendor/etc/firmware/nvram.txt"
# CONFIG_BCMDHD_STATIC_IF is not set
# CONFIG_WLAN_VENDOR_RSI is not set
CONFIG_WLAN_VENDOR_SILABS=y
# CONFIG_WFX is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
# CONFIG_WLAN_VENDOR_ZYDAS is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
# CONFIG_MAC80211_HWSIM is not set
CONFIG_USB_NET_RNDIS_WLAN=m
CONFIG_VIRT_WIFI=m
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
CONFIG_IEEE802154_AT86RF230=m
CONFIG_IEEE802154_MRF24J40=m
CONFIG_IEEE802154_CC2520=m
CONFIG_IEEE802154_ATUSB=m
CONFIG_IEEE802154_ADF7242=m
CONFIG_IEEE802154_CA8210=m
# CONFIG_IEEE802154_CA8210_DEBUGFS is not set
CONFIG_IEEE802154_MCR20A=m
CONFIG_IEEE802154_HWSIM=m

#
# Wireless WAN
#
CONFIG_WWAN=m
CONFIG_WWAN_DEBUGFS=y
CONFIG_WWAN_HWSIM=m
CONFIG_MHI_WWAN_CTRL=m
CONFIG_MHI_WWAN_MBIM=m
CONFIG_RPMSG_WWAN_CTRL=m
CONFIG_IOSM=m
CONFIG_MTK_T7XX=m
# end of Wireless WAN

# CONFIG_VMXNET3 is not set
# CONFIG_FUJITSU_ES is not set
CONFIG_LTE=y
CONFIG_LTE_RM310=y
CONFIG_LTE_EM05=y
CONFIG_NETDEVSIM=m
CONFIG_NET_FAILOVER=m
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_SPARSEKMAP is not set
CONFIG_INPUT_MATRIXKMAP=m
CONFIG_INPUT_VIVALDIFMAP=m

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=m
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=m
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ADC=y
CONFIG_KEYBOARD_ADP5588=m
CONFIG_KEYBOARD_ADP5589=m
CONFIG_KEYBOARD_ATKBD=m
CONFIG_KEYBOARD_QT1050=m
CONFIG_KEYBOARD_QT1070=m
CONFIG_KEYBOARD_QT2160=m
CONFIG_KEYBOARD_DLINK_DIR685=m
CONFIG_KEYBOARD_LKKBD=m
CONFIG_KEYBOARD_GPIO_DISABLED=y
CONFIG_KEYBOARD_GPIO_BUTTON_HOTPLUG=m
CONFIG_KEYBOARD_TCA6416=m
CONFIG_KEYBOARD_TCA8418=m
CONFIG_KEYBOARD_MATRIX=m
CONFIG_KEYBOARD_LM8323=m
CONFIG_KEYBOARD_LM8333=m
CONFIG_KEYBOARD_MAX7359=m
CONFIG_KEYBOARD_MCS=m
CONFIG_KEYBOARD_MPR121=m
CONFIG_KEYBOARD_NEWTON=m
CONFIG_KEYBOARD_OPENCORES=m
CONFIG_KEYBOARD_PINEPHONE=m
CONFIG_KEYBOARD_SAMSUNG=m
CONFIG_KEYBOARD_STOWAWAY=m
CONFIG_KEYBOARD_SUNKBD=m
CONFIG_KEYBOARD_OMAP4=m
CONFIG_KEYBOARD_TM2_TOUCHKEY=m
CONFIG_KEYBOARD_XTKBD=m
CONFIG_KEYBOARD_CAP11XX=m
CONFIG_KEYBOARD_BCM=m
CONFIG_KEYBOARD_CYPRESS_SF=m
CONFIG_INPUT_MOUSE=y
# CONFIG_MOUSE_PS2 is not set
CONFIG_MOUSE_SERIAL=m
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=m
CONFIG_MOUSE_ELAN_I2C=m
CONFIG_MOUSE_ELAN_I2C_I2C=y
CONFIG_MOUSE_ELAN_I2C_SMBUS=y
# CONFIG_MOUSE_VSXXXAA is not set
CONFIG_MOUSE_GPIO=m
CONFIG_MOUSE_SYNAPTICS_I2C=m
CONFIG_MOUSE_SYNAPTICS_USB=m
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_ANALOG=m
CONFIG_JOYSTICK_A3D=m
CONFIG_JOYSTICK_ADC=m
CONFIG_JOYSTICK_ADI=m
CONFIG_JOYSTICK_COBRA=m
CONFIG_JOYSTICK_GF2K=m
CONFIG_JOYSTICK_GRIP=m
CONFIG_JOYSTICK_GRIP_MP=m
CONFIG_JOYSTICK_GUILLEMOT=m
CONFIG_JOYSTICK_INTERACT=m
CONFIG_JOYSTICK_SIDEWINDER=m
CONFIG_JOYSTICK_TMDC=m
CONFIG_JOYSTICK_IFORCE=m
CONFIG_JOYSTICK_IFORCE_USB=m
CONFIG_JOYSTICK_IFORCE_232=m
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
CONFIG_JOYSTICK_STINGER=m
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
CONFIG_JOYSTICK_AS5011=m
CONFIG_JOYSTICK_JOYDUMP=m
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_JOYSTICK_PSXPAD_SPI=m
CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
CONFIG_JOYSTICK_PXRC=m
CONFIG_JOYSTICK_QWIIC=m
CONFIG_JOYSTICK_FSIA6B=m
CONFIG_JOYSTICK_SENSEHAT=m
CONFIG_INPUT_TABLET=y
CONFIG_TABLET_USB_ACECAD=m
CONFIG_TABLET_USB_AIPTEK=m
CONFIG_TABLET_USB_HANWANG=m
CONFIG_TABLET_USB_KBTAB=m
CONFIG_TABLET_USB_PEGASUS=m
CONFIG_TABLET_SERIAL_WACOM4=m
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=m
CONFIG_TOUCHSCREEN_AD7877=m
CONFIG_TOUCHSCREEN_AD7879=m
CONFIG_TOUCHSCREEN_AD7879_I2C=m
CONFIG_TOUCHSCREEN_AD7879_SPI=m
CONFIG_TOUCHSCREEN_ADC=m
CONFIG_TOUCHSCREEN_AR1021_I2C=m
CONFIG_TOUCHSCREEN_ATMEL_MXT=m
# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set
CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
CONFIG_TOUCHSCREEN_BU21013=m
CONFIG_TOUCHSCREEN_BU21029=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
# CONFIG_TOUCHSCREEN_CHIPONE_9551R is not set
CONFIG_TOUCHSCREEN_CY8CTMA140=m
CONFIG_TOUCHSCREEN_CY8CTMG110=m
CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5 is not set
CONFIG_TOUCHSCREEN_DYNAPRO=m
CONFIG_TOUCHSCREEN_HAMPSHIRE=m
CONFIG_TOUCHSCREEN_EETI=m
CONFIG_TOUCHSCREEN_EGALAX=m
CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
CONFIG_TOUCHSCREEN_EXC3000=m
CONFIG_TOUCHSCREEN_FTS=m
CONFIG_TOUCHSCREEN_FT5726=m
CONFIG_TOUCHSCREEN_FUJITSU=m
CONFIG_TOUCHSCREEN_GOODIX=m
CONFIG_TOUCHSCREEN_GSL3673=m
CONFIG_TOUCHSCREEN_GSL3673_800X1280=m
CONFIG_TOUCHSCREEN_GSLX680_PAD=m
CONFIG_TOUCHSCREEN_GT1X=m
CONFIG_TOUCHSCREEN_GT9XX=m
# CONFIG_TOUCHSCREEN_GOODIX_GTX8 is not set
CONFIG_TOUCHSCREEN_HIDEEP=m
CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
CONFIG_TOUCHSCREEN_HYN=m
CONFIG_TOUCHSCREEN_ILI210X=m
CONFIG_TOUCHSCREEN_ILITEK=m
CONFIG_TOUCHSCREEN_S6SY761=m
CONFIG_TOUCHSCREEN_GUNZE=m
CONFIG_TOUCHSCREEN_EKTF2127=m
CONFIG_TOUCHSCREEN_ELAN=m
CONFIG_TOUCHSCREEN_ELAN5515=m
CONFIG_TOUCHSCREEN_ELO=m
CONFIG_TOUCHSCREEN_WACOM_W8001=m
CONFIG_TOUCHSCREEN_WACOM_W9013=m
CONFIG_TOUCHSCREEN_WACOM_I2C=m
CONFIG_TOUCHSCREEN_MAX11801=m
CONFIG_TOUCHSCREEN_MCS5000=m
CONFIG_TOUCHSCREEN_MMS114=m
CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
CONFIG_TOUCHSCREEN_MSG2638=m
CONFIG_TOUCHSCREEN_MTOUCH=m
CONFIG_TOUCHSCREEN_IMAGIS=m
CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
CONFIG_TOUCHSCREEN_INEXIO=m
CONFIG_TOUCHSCREEN_MK712=m
# CONFIG_TOUCHSCREEN_PARADE is not set
CONFIG_TOUCHSCREEN_PENMOUNT=m
CONFIG_TOUCHSCREEN_EDT_FT5X06=m
CONFIG_TOUCHSCREEN_RASPITS_FT5426=m
CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
CONFIG_TOUCHSCREEN_TOUCHWIN=m
CONFIG_TOUCHSCREEN_PIXCIR=m
CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
CONFIG_TOUCHSCREEN_WM97XX=m
CONFIG_TOUCHSCREEN_WM9705=y
CONFIG_TOUCHSCREEN_WM9712=y
CONFIG_TOUCHSCREEN_WM9713=y
CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
CONFIG_TOUCHSCREEN_TOUCHIT213=m
CONFIG_TOUCHSCREEN_TSC_SERIO=m
CONFIG_TOUCHSCREEN_TSC200X_CORE=m
CONFIG_TOUCHSCREEN_TSC2004=m
CONFIG_TOUCHSCREEN_TSC2005=m
CONFIG_TOUCHSCREEN_TSC2007=m
CONFIG_TOUCHSCREEN_TSC2007_IIO=y
CONFIG_TOUCHSCREEN_RM_TS=m
CONFIG_TOUCHSCREEN_SILEAD=m
CONFIG_TOUCHSCREEN_SIS_I2C=m
CONFIG_TOUCHSCREEN_ST1232=m
CONFIG_TOUCHSCREEN_STMFTS=m
CONFIG_TOUCHSCREEN_SUR40=m
CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
CONFIG_TOUCHSCREEN_SX8654=m
CONFIG_TOUCHSCREEN_TPS6507X=m
CONFIG_TOUCHSCREEN_ZET6223=m
CONFIG_TOUCHSCREEN_ZFORCE=m
CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
CONFIG_TOUCHSCREEN_ROHM_BU21023=m
CONFIG_TOUCHSCREEN_IQS5XX=m
CONFIG_TOUCHSCREEN_ZINITIX=m
# CONFIG_TOUCHSCREEN_HIMAX_CHIPSET is not set
CONFIG_ROCKCHIP_REMOTECTL=y
CONFIG_ROCKCHIP_REMOTECTL_PWM=y

#
# handle all sensors
#
# CONFIG_SENSOR_DEVICE is not set
CONFIG_INPUT_MISC=y
CONFIG_INPUT_AD714X=m
CONFIG_INPUT_AD714X_I2C=m
CONFIG_INPUT_AD714X_SPI=m
CONFIG_INPUT_ATMEL_CAPTOUCH=m
CONFIG_INPUT_BMA150=m
CONFIG_INPUT_E3X0_BUTTON=m
CONFIG_INPUT_MMA8450=m
CONFIG_INPUT_GPIO_BEEPER=m
CONFIG_INPUT_GPIO_DECODER=m
CONFIG_INPUT_GPIO_VIBRA=m
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
CONFIG_INPUT_KXTJ9=m
CONFIG_INPUT_POWERMATE=m
CONFIG_INPUT_YEALINK=m
CONFIG_INPUT_CM109=m
CONFIG_INPUT_REGULATOR_HAPTIC=m
CONFIG_INPUT_UINPUT=y
CONFIG_INPUT_PCF8574=m
CONFIG_INPUT_PWM_BEEPER=m
CONFIG_INPUT_PWM_VIBRA=m
CONFIG_INPUT_RK805_PWRKEY=y
CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
# CONFIG_INPUT_DA7280_HAPTICS is not set
CONFIG_INPUT_ADXL34X=m
CONFIG_INPUT_ADXL34X_I2C=m
CONFIG_INPUT_ADXL34X_SPI=m
# CONFIG_INPUT_IBM_PANEL is not set
CONFIG_INPUT_IMS_PCU=m
CONFIG_INPUT_IQS269A=m
# CONFIG_INPUT_IQS626A is not set
# CONFIG_INPUT_IQS7222 is not set
CONFIG_INPUT_CMA3000=m
CONFIG_INPUT_CMA3000_I2C=m
CONFIG_INPUT_DRV260X_HAPTICS=m
CONFIG_INPUT_DRV2665_HAPTICS=m
CONFIG_INPUT_DRV2667_HAPTICS=m
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=m
CONFIG_RMI4_SPI=m
CONFIG_RMI4_SMB=m
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=y
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
CONFIG_RMI4_F3A=y
CONFIG_RMI4_F54=y
CONFIG_RMI4_F55=y

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=m
CONFIG_SERIO_AMBAKMI=m
CONFIG_SERIO_PCIPS2=m
CONFIG_SERIO_LIBPS2=m
CONFIG_SERIO_RAW=m
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
CONFIG_GAMEPORT=m
# CONFIG_GAMEPORT_NS558 is not set
# CONFIG_GAMEPORT_L4 is not set
# CONFIG_GAMEPORT_EMU10K1 is not set
# CONFIG_GAMEPORT_FM801 is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_PNP=y
CONFIG_SERIAL_8250_16550A_VARIANTS=y
CONFIG_SERIAL_8250_FINTEK=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=10
CONFIG_SERIAL_8250_RUNTIME_UARTS=10
# CONFIG_SERIAL_8250_EXTENDED is not set
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_8250_PERICOM=y
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
CONFIG_SERIAL_AMBA_PL010=m
CONFIG_SERIAL_AMBA_PL011=m
# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_NOZOMI is not set
# CONFIG_NULL_TTY is not set
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
# CONFIG_RPMSG_TTY is not set
CONFIG_SERIAL_DEV_BUS=m
# CONFIG_TTY_PRINTK is not set
CONFIG_VIRTIO_CONSOLE=m
# CONFIG_IPMI_HANDLER is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
# CONFIG_HW_RANDOM_BA431 is not set
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_OPTEE=y
# CONFIG_HW_RANDOM_CCTRNG is not set
# CONFIG_HW_RANDOM_XIPHERA is not set
CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
CONFIG_HW_RANDOM_CN10K=y
CONFIG_HW_RANDOM_ROCKCHIP=y
# CONFIG_APPLICOM is not set
CONFIG_DEVMEM=y
CONFIG_DEVPORT=y
CONFIG_TCG_TPM=m
CONFIG_HW_RANDOM_TPM=y
CONFIG_TCG_TIS_CORE=m
CONFIG_TCG_TIS=m
CONFIG_TCG_TIS_SPI=m
CONFIG_TCG_TIS_SPI_CR50=y
CONFIG_TCG_TIS_I2C=m
CONFIG_TCG_TIS_I2C_CR50=m
CONFIG_TCG_TIS_I2C_ATMEL=m
CONFIG_TCG_TIS_I2C_INFINEON=m
CONFIG_TCG_TIS_I2C_NUVOTON=m
CONFIG_TCG_ATMEL=m
CONFIG_TCG_INFINEON=m
CONFIG_TCG_CRB=m
CONFIG_TCG_VTPM_PROXY=m
CONFIG_TCG_FTPM_TEE=m
CONFIG_TCG_TIS_ST33ZP24=m
CONFIG_TCG_TIS_ST33ZP24_I2C=m
CONFIG_TCG_TIS_ST33ZP24_SPI=m
# CONFIG_XILLYBUS is not set
# CONFIG_XILLYUSB is not set
CONFIG_RANDOM_TRUST_CPU=y
CONFIG_RANDOM_TRUST_BOOTLOADER=y
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=m
CONFIG_I2C_MUX_GPIO=m
CONFIG_I2C_MUX_GPMUX=m
CONFIG_I2C_MUX_LTC4306=m
CONFIG_I2C_MUX_PCA9541=m
CONFIG_I2C_MUX_PCA954x=m
CONFIG_I2C_MUX_PINCTRL=m
CONFIG_I2C_MUX_REG=m
CONFIG_I2C_DEMUX_PINCTRL=m
CONFIG_I2C_MUX_MLXCPLD=m
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_ALGOBIT=y

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
CONFIG_I2C_CCGX_UCSI=m
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set

#
# ACPI drivers
#
CONFIG_I2C_SCMI=m

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CADENCE is not set
# CONFIG_I2C_CBUS_GPIO is not set
CONFIG_I2C_DESIGNWARE_CORE=m
CONFIG_I2C_DESIGNWARE_SLAVE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=m
CONFIG_I2C_DESIGNWARE_PCI=m
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=m
# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
# CONFIG_I2C_HISI is not set
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
CONFIG_I2C_RK3X=y
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_THUNDERX is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_CP2615 is not set
# CONFIG_I2C_PCI1XXXX is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
CONFIG_I2C_TINY_USB=m

#
# Other I2C/SMBus bus drivers
#
CONFIG_I2C_VIRTIO=m
# end of I2C Hardware Bus support

CONFIG_I2C_STUB=m
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=m
CONFIG_I2C_SLAVE_TESTUNIT=m
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

# CONFIG_I3C is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y

#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
CONFIG_SPI_BITBANG=y
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_CADENCE_XSPI is not set
CONFIG_SPI_DESIGNWARE=m
CONFIG_SPI_DW_DMA=y
# CONFIG_SPI_DW_PCI is not set
# CONFIG_SPI_DW_MMIO is not set
# CONFIG_SPI_HISI_KUNPENG is not set
# CONFIG_SPI_HISI_SFC_V3XX is not set
# CONFIG_SPI_NXP_FLEXSPI is not set
CONFIG_SPI_GPIO=m
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_MICROCHIP_CORE is not set
# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
# CONFIG_SPI_OC_TINY is not set
CONFIG_SPI_PL022=m
# CONFIG_SPI_PXA2XX is not set
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_ROCKCHIP_MISCDEV=y
CONFIG_SPI_ROCKCHIP_FLEXBUS_FSPI=y
CONFIG_SPI_ROCKCHIP_FLEXBUS_SPI=y
CONFIG_SPI_ROCKCHIP_SFC=y
CONFIG_SPI_ROCKCHIP_SLAVE=y
CONFIG_SPI_ROCKCHIP_SLAVE_MISCDEV=y
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_THUNDERX is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_SPI_AMD is not set

#
# SPI Multiplexer support
#
# CONFIG_SPI_MUX is not set

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_LOOPBACK_TEST is not set
# CONFIG_SPI_TLE62X0 is not set
CONFIG_SPI_SLAVE=y
CONFIG_SPI_SLAVE_TIME=y
CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y
CONFIG_SPI_SLAVE_ROCKCHIP_OBJ=y
CONFIG_SPI_DYNAMIC=y
# CONFIG_SPMI is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set

#
# PPS clients support
#
CONFIG_PPS_CLIENT_KTIMER=m
# CONFIG_PPS_CLIENT_LDISC is not set
CONFIG_PPS_CLIENT_GPIO=m

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
# CONFIG_DP83640_PHY is not set
# CONFIG_PTP_1588_CLOCK_INES is not set
CONFIG_PTP_1588_CLOCK_KVM=y
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
# CONFIG_PTP_1588_CLOCK_OCP is not set
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_PINCTRL_AMD is not set
# CONFIG_PINCTRL_CY8C95X0 is not set
# CONFIG_PINCTRL_MCP23S08 is not set
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
# CONFIG_PINCTRL_OCELOT is not set
CONFIG_PINCTRL_RK805=y
CONFIG_PINCTRL_RK806=y
CONFIG_PINCTRL_ROCKCHIP=y
# CONFIG_PINCTRL_SINGLE is not set
# CONFIG_PINCTRL_STMFX is not set
# CONFIG_PINCTRL_SX150X is not set

#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers

CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_FTGPIO010 is not set
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HISI is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_LOGICVC is not set
# CONFIG_GPIO_MB86S7X is not set
# CONFIG_GPIO_PL061 is not set
CONFIG_GPIO_ROCKCHIP=y
# CONFIG_GPIO_SIFIVE is not set
# CONFIG_GPIO_SYSCON is not set
# CONFIG_GPIO_XGENE is not set
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
# CONFIG_GPIO_ADNP is not set
# CONFIG_GPIO_AW9110 is not set
# CONFIG_GPIO_GW_PLD is not set
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_NCA9539 is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCA9570 is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_TPIC2810 is not set
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set
# end of PCI GPIO expanders

#
# SPI GPIO expanders
#
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
# end of USB GPIO expanders

#
# Virtual GPIO drivers
#
# CONFIG_GPIO_AGGREGATOR is not set
# CONFIG_GPIO_MOCKUP is not set
# CONFIG_GPIO_VIRTIO is not set
# CONFIG_GPIO_SIM is not set
# end of Virtual GPIO drivers

#
# Other GPIO expanders
#
# CONFIG_GPIO_CASCADE is not set
CONFIG_W1=m
CONFIG_W1_CON=y

#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_MATROX=m
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
CONFIG_W1_MASTER_DS1WM=m
CONFIG_W1_MASTER_GPIO=m
CONFIG_W1_MASTER_SGI=m
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
CONFIG_W1_SLAVE_DS2405=m
CONFIG_W1_SLAVE_DS2408=m
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
CONFIG_W1_SLAVE_DS2805=m
CONFIG_W1_SLAVE_DS2430=m
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
CONFIG_W1_SLAVE_DS2438=m
CONFIG_W1_SLAVE_DS250X=m
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
CONFIG_W1_SLAVE_DS28E17=m
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_BRCMSTB is not set
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
# CONFIG_POWER_RESET_LTC2952 is not set
CONFIG_POWER_RESET_REGULATOR=y
# CONFIG_POWER_RESET_RESTART is not set
# CONFIG_POWER_RESET_XGENE is not set
# CONFIG_POWER_RESET_SYSCON is not set
# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
CONFIG_NVMEM_REBOOT_MODE=y
# CONFIG_POWER_SEQUENCING is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_PDA_POWER is not set
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_IP5XXX_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_CW2017 is not set
# CONFIG_BATTERY_CW221X is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SAMSUNG_SDI is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_BATTERY_MAX1721X is not set
CONFIG_CHARGER_CPS5601X=m
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
CONFIG_CHARGER_GPIO=m
# CONFIG_CHARGER_MANAGER is not set
CONFIG_ROCKCHIP_CHARGER_MANAGER=m
CONFIG_ROCKCHIP_CHARGER_MANAGER_CHARGE_PUMP=y
# CONFIG_CHARGER_LT3651 is not set
# CONFIG_CHARGER_LTC4162L is not set
# CONFIG_CHARGER_SC8551 is not set
CONFIG_CHARGER_SC89601=m
# CONFIG_CHARGER_SC89890 is not set
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_MAX77976 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25700 is not set
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_BQ25980 is not set
# CONFIG_CHARGER_BQ256XX is not set
CONFIG_BATTERY_RK816=m
CONFIG_BATTERY_RK817=m
CONFIG_CHARGER_RK817=m
CONFIG_BATTERY_RK818=m
CONFIG_CHARGER_RK818=m
# CONFIG_CHARGER_SGM41542 is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_BATTERY_GOLDFISH is not set
# CONFIG_BATTERY_RT5033 is not set
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
# CONFIG_BATTERY_UG3105 is not set
# CONFIG_NANOPI_ADC_POWER is not set
CONFIG_HWMON=y
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM1177 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7310 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_AHT10 is not set
# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
# CONFIG_SENSORS_AS370 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
CONFIG_SENSORS_ARM_SCMI=y
CONFIG_SENSORS_ARM_SCPI=y
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_CORSAIR_CPRO is not set
# CONFIG_SENSORS_CORSAIR_PSU is not set
# CONFIG_SENSORS_DRIVETEMP is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_I5K_AMB is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_FTSTEUTATES is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_G762 is not set
CONFIG_SENSORS_GPIO_FAN=m
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_IIO_HWMON is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_POWR1220 is not set
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LTC2945 is not set
# CONFIG_SENSORS_LTC2947_I2C is not set
# CONFIG_SENSORS_LTC2947_SPI is not set
# CONFIG_SENSORS_LTC2990 is not set
# CONFIG_SENSORS_LTC2992 is not set
# CONFIG_SENSORS_LTC4151 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4222 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LTC4260 is not set
# CONFIG_SENSORS_LTC4261 is not set
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX127 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX197 is not set
# CONFIG_SENSORS_MAX31722 is not set
# CONFIG_SENSORS_MAX31730 is not set
# CONFIG_SENSORS_MAX31760 is not set
# CONFIG_SENSORS_MAX6620 is not set
# CONFIG_SENSORS_MAX6621 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MAX6697 is not set
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_TPS23861 is not set
# CONFIG_SENSORS_MR75203 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LM95234 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_NCT6683 is not set
# CONFIG_SENSORS_NCT6775 is not set
# CONFIG_SENSORS_NCT6775_I2C is not set
# CONFIG_SENSORS_NCT7802 is not set
# CONFIG_SENSORS_NCT7904 is not set
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
# CONFIG_SENSORS_NZXT_SMART2 is not set
# CONFIG_SENSORS_OCC_P8_I2C is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_PMBUS is not set
CONFIG_SENSORS_PWM_FAN=m
# CONFIG_SENSORS_SBTSI is not set
# CONFIG_SENSORS_SBRMI is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHT4x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC2305 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA238 is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_TMP464 is not set
# CONFIG_SENSORS_TMP513 is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_XGENE is not set

#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
# CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE is not set
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR=y
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
# CONFIG_THERMAL_EMULATION is not set
# CONFIG_THERMAL_MMIO is not set
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_RK_VIRTUAL_THERMAL=y
CONFIG_GENERIC_ADC_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set
# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=m
CONFIG_GPIO_WATCHDOG=m
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
# CONFIG_ARM_SP805_WATCHDOG is not set
# CONFIG_ARM_SBSA_WATCHDOG is not set
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=y
# CONFIG_MAX63XX_WATCHDOG is not set
CONFIG_KHADAS_WATCHDOG=y
# CONFIG_ARM_SMC_WATCHDOG is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_HP_WATCHDOG is not set
# CONFIG_MEN_A21_WDT is not set

#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
CONFIG_BCMA_HOST_PCI=y
# CONFIG_BCMA_HOST_SOC is not set
CONFIG_BCMA_DRIVER_PCI=y
# CONFIG_BCMA_DRIVER_GMAC_CMN is not set
# CONFIG_BCMA_DRIVER_GPIO is not set
# CONFIG_BCMA_DEBUG is not set

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AXP20X_I2C is not set
# CONFIG_MFD_MADERA is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77714 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MAX96745 is not set
# CONFIG_MFD_MAX96755F is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6370 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_MFD_OCELOT is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_NTXEC is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_UCB1400_CORE is not set
# CONFIG_MFD_SY7636A is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT4831 is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RT5120 is not set
# CONFIG_MFD_RC5T583 is not set
CONFIG_MFD_RK618=y
CONFIG_MFD_RK630=m
CONFIG_MFD_RK630_I2C=m
CONFIG_MFD_RK630_SPI=m
CONFIG_MFD_RK806=y
CONFIG_MFD_RK806_I2C=y
CONFIG_MFD_RK806_SPI=y
CONFIG_MFD_RK808=y
CONFIG_MFD_RK1000=y

#
# driver for different display serdes
#
CONFIG_MFD_SERDES_DISPLAY=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96745=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96749=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96752=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96755=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96772=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96789=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18TL82=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18RL82=y
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP=y
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP_RKX111=y
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP_RKX121=y
CONFIG_SERDES_DISPLAY_CHIP_NOVO=y
CONFIG_SERDES_DISPLAY_CHIP_NOVO_NCA9539=y
CONFIG_MFD_RKX110_X120=m
CONFIG_PWM_RKX120=m
CONFIG_ROCKCHIP_SERDES_DRM_PANEL=m
CONFIG_MFD_ROCKCHIP_FLEXBUS=y
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
CONFIG_MFD_SIMPLE_MFD_I2C=m
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TQMX86 is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
# CONFIG_MFD_ROHM_BD71828 is not set
# CONFIG_MFD_ROHM_BD957XMUF is not set
# CONFIG_MFD_STPMIC1 is not set
# CONFIG_MFD_STMFX is not set
# CONFIG_MFD_ATC260X_I2C is not set
# CONFIG_MFD_KHADAS_MCU is not set
# CONFIG_MFD_QCOM_PM8008 is not set
# CONFIG_RAVE_SP_CORE is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# CONFIG_MFD_RSMU_I2C is not set
# CONFIG_MFD_RSMU_SPI is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
CONFIG_REGULATOR_USERSPACE_CONSUMER=m
CONFIG_REGULATOR_88PG86X=m
CONFIG_REGULATOR_ACT8865=m
CONFIG_REGULATOR_AD5398=m
CONFIG_REGULATOR_ARM_SCMI=y
CONFIG_REGULATOR_DA9121=m
CONFIG_REGULATOR_DA9210=m
CONFIG_REGULATOR_DA9211=m
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_FAN53880=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_ISL9305=m
CONFIG_REGULATOR_ISL6271A=m
CONFIG_REGULATOR_LP3971=m
CONFIG_REGULATOR_LP3972=m
CONFIG_REGULATOR_LP872X=m
CONFIG_REGULATOR_LP8752=m
CONFIG_REGULATOR_LP8755=m
CONFIG_REGULATOR_LTC3589=m
CONFIG_REGULATOR_LTC3676=m
CONFIG_REGULATOR_MAX1586=m
CONFIG_REGULATOR_MAX8649=m
CONFIG_REGULATOR_MAX8660=m
CONFIG_REGULATOR_MAX8893=m
CONFIG_REGULATOR_MAX8952=m
CONFIG_REGULATOR_MAX8973=m
CONFIG_REGULATOR_MAX20086=m
CONFIG_REGULATOR_MAX77826=m
CONFIG_REGULATOR_MCP16502=m
CONFIG_REGULATOR_MP5416=m
CONFIG_REGULATOR_MP8859=m
CONFIG_REGULATOR_MP8865=m
CONFIG_REGULATOR_MP886X=m
CONFIG_REGULATOR_MPQ7920=m
CONFIG_REGULATOR_MT6311=m
CONFIG_REGULATOR_PCA9450=m
CONFIG_REGULATOR_PF8X00=m
CONFIG_REGULATOR_PFUZE100=m
CONFIG_REGULATOR_PV88060=m
CONFIG_REGULATOR_PV88080=m
CONFIG_REGULATOR_PV88090=m
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
CONFIG_REGULATOR_RK801=y
CONFIG_REGULATOR_RK806=y
CONFIG_REGULATOR_RK808=y
CONFIG_REGULATOR_RK860X=y
CONFIG_REGULATOR_RT4801=m
CONFIG_REGULATOR_RT5190A=m
CONFIG_REGULATOR_RT5759=m
CONFIG_REGULATOR_RT6160=m
CONFIG_REGULATOR_RT6245=m
CONFIG_REGULATOR_RTQ2134=m
CONFIG_REGULATOR_RTMV20=m
CONFIG_REGULATOR_RTQ6752=m
CONFIG_REGULATOR_SLG51000=m
CONFIG_REGULATOR_SY8106A=m
CONFIG_REGULATOR_SY8824X=m
CONFIG_REGULATOR_SY8827N=m
CONFIG_REGULATOR_TPS51632=m
CONFIG_REGULATOR_TPS62360=m
CONFIG_REGULATOR_TPS6286X=m
CONFIG_REGULATOR_TPS65023=m
CONFIG_REGULATOR_TPS6507X=m
CONFIG_REGULATOR_TPS65132=m
CONFIG_REGULATOR_TPS6524X=m
CONFIG_REGULATOR_VCTRL=m
CONFIG_REGULATOR_WL2868C=m
CONFIG_REGULATOR_XZ3216=m
CONFIG_RC_CORE=y
# CONFIG_LIRC is not set
CONFIG_RC_MAP=m
CONFIG_RC_DECODERS=y
CONFIG_IR_IMON_DECODER=m
CONFIG_IR_JVC_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
CONFIG_IR_RCMM_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_XMP_DECODER=m
CONFIG_RC_DEVICES=y
CONFIG_IR_ENE=m
CONFIG_IR_FINTEK=m
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_HIX5HD2=m
CONFIG_IR_IGORPLUGUSB=m
CONFIG_IR_IGUANA=m
CONFIG_IR_IMON=m
CONFIG_IR_IMON_RAW=m
CONFIG_IR_ITE_CIR=m
CONFIG_IR_MCEUSB=m
CONFIG_IR_NUVOTON=m
CONFIG_IR_REDRAT3=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_STREAMZAP=m
CONFIG_IR_TOY=m
CONFIG_IR_TTUSBIR=m
CONFIG_RC_ATI_REMOTE=m
CONFIG_RC_LOOPBACK=m
CONFIG_RC_XBOX_DVD=m
CONFIG_CEC_CORE=y

#
# CEC support
#
CONFIG_MEDIA_CEC_RC=y
CONFIG_MEDIA_CEC_SUPPORT=y
CONFIG_CEC_CH7322=m
CONFIG_USB_PULSE8_CEC=m
CONFIG_USB_RAINSHADOW_CEC=m
# end of CEC support

CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_SUPPORT_FILTER=y
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_SDR_SUPPORT is not set
CONFIG_MEDIA_PLATFORM_SUPPORT=y
# CONFIG_MEDIA_TEST_SUPPORT is not set
# end of Media device types

CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CONTROLLER=y

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_H264=y
CONFIG_V4L2_VP9=y
CONFIG_V4L2_MEM2MEM_DEV=y
# CONFIG_V4L2_FLASH_LED_CLASS is not set
CONFIG_V4L2_FWNODE=y
CONFIG_V4L2_ASYNC=y
# end of Video4Linux options

#
# Media controller options
#
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
# end of Media controller options

#
# Media drivers
#

#
# Drivers filtered as selected at 'Filter media drivers'
#

#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_GSPCA=m
CONFIG_USB_GSPCA_BENQ=m
CONFIG_USB_GSPCA_CONEX=m
CONFIG_USB_GSPCA_CPIA1=m
CONFIG_USB_GSPCA_DTCS033=m
CONFIG_USB_GSPCA_ETOMS=m
CONFIG_USB_GSPCA_FINEPIX=m
CONFIG_USB_GSPCA_JEILINJ=m
CONFIG_USB_GSPCA_JL2005BCD=m
CONFIG_USB_GSPCA_KINECT=m
CONFIG_USB_GSPCA_KONICA=m
CONFIG_USB_GSPCA_MARS=m
CONFIG_USB_GSPCA_MR97310A=m
CONFIG_USB_GSPCA_NW80X=m
CONFIG_USB_GSPCA_OV519=m
CONFIG_USB_GSPCA_OV534=m
CONFIG_USB_GSPCA_OV534_9=m
CONFIG_USB_GSPCA_PAC207=m
CONFIG_USB_GSPCA_PAC7302=m
CONFIG_USB_GSPCA_PAC7311=m
CONFIG_USB_GSPCA_SE401=m
CONFIG_USB_GSPCA_SN9C2028=m
CONFIG_USB_GSPCA_SN9C20X=m
CONFIG_USB_GSPCA_SONIXB=m
CONFIG_USB_GSPCA_SONIXJ=m
CONFIG_USB_GSPCA_SPCA1528=m
CONFIG_USB_GSPCA_SPCA500=m
CONFIG_USB_GSPCA_SPCA501=m
CONFIG_USB_GSPCA_SPCA505=m
CONFIG_USB_GSPCA_SPCA506=m
CONFIG_USB_GSPCA_SPCA508=m
CONFIG_USB_GSPCA_SPCA561=m
CONFIG_USB_GSPCA_SQ905=m
CONFIG_USB_GSPCA_SQ905C=m
CONFIG_USB_GSPCA_SQ930X=m
CONFIG_USB_GSPCA_STK014=m
CONFIG_USB_GSPCA_STK1135=m
CONFIG_USB_GSPCA_STV0680=m
CONFIG_USB_GSPCA_SUNPLUS=m
CONFIG_USB_GSPCA_T613=m
CONFIG_USB_GSPCA_TOPRO=m
CONFIG_USB_GSPCA_TOUPTEK=m
CONFIG_USB_GSPCA_TV8532=m
CONFIG_USB_GSPCA_VC032X=m
CONFIG_USB_GSPCA_VICAM=m
CONFIG_USB_GSPCA_XIRLINK_CIT=m
CONFIG_USB_GSPCA_ZC3XX=m
CONFIG_USB_GL860=m
CONFIG_USB_M5602=m
CONFIG_USB_STV06XX=m
CONFIG_USB_PWC=m
# CONFIG_USB_PWC_DEBUG is not set
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_USB_S2255=m
CONFIG_VIDEO_USBTV=m
CONFIG_USB_VIDEO_CLASS=m
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y

#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=m
CONFIG_VIDEO_EM28XX_V4L2=m
CONFIG_VIDEO_EM28XX_ALSA=m
CONFIG_VIDEO_EM28XX_RC=m
CONFIG_MEDIA_PCI_SUPPORT=y

#
# Media capture support
#
CONFIG_VIDEO_SOLO6X10=m
CONFIG_VIDEO_TW5864=m
CONFIG_VIDEO_TW68=m
CONFIG_VIDEO_TW686X=m
CONFIG_VIDEO_ZORAN=m
CONFIG_VIDEO_ZORAN_DC30=y
CONFIG_VIDEO_ZORAN_ZR36060=y
CONFIG_VIDEO_ZORAN_BUZ=y
CONFIG_VIDEO_ZORAN_DC10=y
CONFIG_VIDEO_ZORAN_LML33=y
CONFIG_VIDEO_ZORAN_LML33R10=y
CONFIG_VIDEO_ZORAN_AVS6EYES=y
CONFIG_MEDIA_PLATFORM_DRIVERS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
CONFIG_VIDEO_MUX=m

#
# Allegro DVT media platform drivers
#

#
# Amlogic media platform drivers
#

#
# Amphion drivers
#

#
# Aspeed media platform drivers
#
# CONFIG_VIDEO_ASPEED is not set

#
# Atmel media platform drivers
#

#
# Cadence media platform drivers
#
# CONFIG_VIDEO_CADENCE_CSI2RX is not set
# CONFIG_VIDEO_CADENCE_CSI2TX is not set

#
# Chips&Media media platform drivers
#

#
# Intel media platform drivers
#

#
# Marvell media platform drivers
#
# CONFIG_VIDEO_CAFE_CCIC is not set

#
# Mediatek media platform drivers
#

#
# NVidia media platform drivers
#

#
# NXP media platform drivers
#

#
# Qualcomm media platform drivers
#

#
# Renesas media platform drivers
#

#
# Rockchip media platform drivers
#
CONFIG_VIDEO_ROCKCHIP_AIISP=y
CONFIG_VIDEO_ROCKCHIP_AVSP=y
CONFIG_VIDEO_ROCKCHIP_CIF=y
CONFIG_ROCKCHIP_CIF_WORKMODE_PINGPONG=y
# CONFIG_ROCKCHIP_CIF_WORKMODE_ONEFRAME is not set
CONFIG_ROCKCHIP_CIF_USE_DUMMY_BUF=y
# CONFIG_ROCKCHIP_CIF_USE_NONE_DUMMY_BUF is not set
CONFIG_ROCKCHIP_CIF_USE_MONITOR=y
CONFIG_ROCKCHIP_CIF_MONITOR_MODE=0x1
CONFIG_ROCKCHIP_CIF_MONITOR_START_FRAME=0
CONFIG_ROCKCHIP_CIF_MONITOR_CYCLE=0x8
CONFIG_ROCKCHIP_CIF_MONITOR_KEEP_TIME=0x3e8
CONFIG_ROCKCHIP_CIF_MONITOR_ERR_CNT=0x5
CONFIG_ROCKCHIP_CIF_RESET_BY_USER=y
CONFIG_VIDEO_ROCKCHIP_FEC=y
CONFIG_ROCKCHIP_FLEXBUS_CIF=y
CONFIG_ROCKCHIP_FLEXBUS_CIF_USE_DUMMY_BUF=y
# CONFIG_ROCKCHIP_FLEXBUS_CIF_USE_NONE_DUMMY_BUF is not set
CONFIG_VIDEO_ROCKCHIP_RKISP1=m
CONFIG_VIDEO_ROCKCHIP_ISP=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V1X=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V21=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V30=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35=y
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35_DBG is not set
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39=y
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39_DBG is not set
CONFIG_VIDEO_ROCKCHIP_ISPP=y
CONFIG_VIDEO_ROCKCHIP_ISPP_FEC=y
CONFIG_VIDEO_ROCKCHIP_ISPP_VERSION_V20=y
CONFIG_VIDEO_ROCKCHIP_HDMIRX_CLASS=y
CONFIG_VIDEO_ROCKCHIP_HDMIRX=y
CONFIG_VIDEO_ROCKCHIP_RGA=y
CONFIG_VIDEO_ROCKCHIP_ISP1=m
CONFIG_VIDEO_ROCKCHIP_VPSS=y
CONFIG_VIDEO_ROCKCHIP_VPSS_V10=y
CONFIG_VIDEO_ROCKCHIP_VPSS_V20=y

#
# Samsung media platform drivers
#

#
# STMicroelectronics media platform drivers
#

#
# Sunxi media platform drivers
#

#
# Texas Instruments drivers
#

#
# Verisilicon media platform drivers
#
CONFIG_VIDEO_HANTRO=y
CONFIG_VIDEO_HANTRO_ROCKCHIP=y

#
# VIA media platform drivers
#

#
# Xilinx media platform drivers
#
# CONFIG_VIDEO_XILINX is not set
CONFIG_VIDEO_TVEEPROM=m
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_CMA_SG=y
CONFIG_VIDEOBUF2_DMA_CONTIG=y
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_VIDEOBUF2_DMA_SG=y
# end of Media drivers

#
# Media ancillary drivers
#
CONFIG_VIDEO_CAM_SLEEP_WAKEUP=m

#
# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
#
CONFIG_VIDEO_IR_I2C=m
CONFIG_VIDEO_CAMERA_SENSOR=y
CONFIG_VIDEO_APTINA_PLL=m
CONFIG_VIDEO_CCS_PLL=m
CONFIG_VIDEO_AR0230=m
CONFIG_VIDEO_AR0521=m
# CONFIG_VIDEO_AR0822 is not set
# CONFIG_VIDEO_AR2020 is not set
CONFIG_VIDEO_BF3925=m
CONFIG_VIDEO_GC02M2=m
CONFIG_VIDEO_GC0312=m
CONFIG_VIDEO_GC0329=m
CONFIG_VIDEO_GC0403=m
CONFIG_VIDEO_GC05A2=m
CONFIG_VIDEO_GC08A3=m
CONFIG_VIDEO_GC1084=m
CONFIG_VIDEO_GC16B3C=m
CONFIG_VIDEO_GC2035=m
CONFIG_VIDEO_GC2053=m
CONFIG_VIDEO_GC2093=m
CONFIG_VIDEO_GC2145=m
CONFIG_VIDEO_GC2155=m
CONFIG_VIDEO_GC2355=m
CONFIG_VIDEO_GC2375H=m
CONFIG_VIDEO_GC2385=m
CONFIG_VIDEO_GC3003=m
CONFIG_VIDEO_GC32E1=m
CONFIG_VIDEO_GC4023=m
CONFIG_VIDEO_GC4653=m
CONFIG_VIDEO_GC4663=m
CONFIG_VIDEO_GC4C33=m
CONFIG_VIDEO_GC5024=m
CONFIG_VIDEO_GC5025=m
CONFIG_VIDEO_GC5035=m
CONFIG_VIDEO_GC6603=m
CONFIG_VIDEO_GC8034=m
CONFIG_VIDEO_GC8613=m
CONFIG_VIDEO_HI556=m
CONFIG_VIDEO_HI846=m
CONFIG_VIDEO_HI847=m
CONFIG_VIDEO_IMX208=m
CONFIG_VIDEO_IMX214=m
CONFIG_VIDEO_IMX214_EEPROM=m
CONFIG_VIDEO_IMX219=m
CONFIG_VIDEO_IMX258=m
CONFIG_VIDEO_IMX258_EEPROM=m
CONFIG_VIDEO_IMX274=m
CONFIG_VIDEO_IMX290=m
CONFIG_VIDEO_IMX307=m
CONFIG_VIDEO_IMX317=m
CONFIG_VIDEO_IMX319=m
CONFIG_VIDEO_IMX323=m
CONFIG_VIDEO_IMX327=m
CONFIG_VIDEO_IMX334=m
CONFIG_VIDEO_IMX335=m
CONFIG_VIDEO_IMX347=m
CONFIG_VIDEO_IMX355=m
CONFIG_VIDEO_IMX378=m
CONFIG_VIDEO_IMX386=m
CONFIG_VIDEO_IMX412=m
CONFIG_VIDEO_IMX415=m
CONFIG_VIDEO_IMX464=m
CONFIG_VIDEO_IMX492=m
CONFIG_VIDEO_IMX498=m
CONFIG_VIDEO_IMX577=m
CONFIG_VIDEO_IMX582=m
CONFIG_VIDEO_IMX586=m
CONFIG_VIDEO_IMX678=m
CONFIG_VIDEO_IMX766=m
CONFIG_VIDEO_JX_F37=m
CONFIG_VIDEO_JX_H62=m
CONFIG_VIDEO_JX_H65=m
CONFIG_VIDEO_JX_K17=m
CONFIG_VIDEO_MAX9271_LIB=m
# CONFIG_VIDEO_MIS2031 is not set
# CONFIG_VIDEO_MIS4001 is not set
CONFIG_VIDEO_MT9M001=m
CONFIG_VIDEO_MT9M032=m
CONFIG_VIDEO_MT9M111=m
CONFIG_VIDEO_MT9P031=m
CONFIG_VIDEO_MT9T001=m
CONFIG_VIDEO_MT9T112=m
CONFIG_VIDEO_MT9V011=m
CONFIG_VIDEO_MT9V032=m
CONFIG_VIDEO_MT9V111=m
CONFIG_VIDEO_NOON010PC30=m
# CONFIG_VIDEO_OG01A10 is not set
CONFIG_VIDEO_OG01A1B=m
# CONFIG_VIDEO_OG02B10 is not set
CONFIG_VIDEO_OS02G10=m
# CONFIG_VIDEO_OS02K10 is not set
CONFIG_VIDEO_OS03B10=m
CONFIG_VIDEO_OS04A10=m
CONFIG_VIDEO_OS04D10=m
CONFIG_VIDEO_OS04E10=m
CONFIG_VIDEO_OS05A20=m
CONFIG_VIDEO_OS05L10=m
CONFIG_VIDEO_OS08A20=m
CONFIG_VIDEO_OS12D40=m
CONFIG_VIDEO_OV02A10=m
CONFIG_VIDEO_OV02B10=m
CONFIG_VIDEO_OV02K10=m
CONFIG_VIDEO_OV08D10=m
CONFIG_VIDEO_OV12D2Q=m
CONFIG_VIDEO_OV13850=m
CONFIG_VIDEO_OV13855=m
CONFIG_VIDEO_OV13858=m
CONFIG_VIDEO_OV13B10=m
CONFIG_VIDEO_OV16880=m
CONFIG_VIDEO_OV16885=m
CONFIG_VIDEO_OV16A10=m
CONFIG_VIDEO_OV16A1Q=m
CONFIG_VIDEO_OV2640=m
CONFIG_VIDEO_OV2659=m
CONFIG_VIDEO_OV2680=m
CONFIG_VIDEO_OV2685=m
CONFIG_VIDEO_OV2718=m
CONFIG_VIDEO_OV2740=m
CONFIG_VIDEO_OV4686=m
CONFIG_VIDEO_OV4688=m
CONFIG_VIDEO_OV4689=m
CONFIG_VIDEO_OV50C40=m
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_OV5647=m
CONFIG_VIDEO_OV5648=m
CONFIG_VIDEO_OV5670=m
CONFIG_VIDEO_OV5675=m
CONFIG_VIDEO_OV5693=m
CONFIG_VIDEO_OV5695=m
CONFIG_VIDEO_OV6650=m
CONFIG_VIDEO_OV7251=m
CONFIG_VIDEO_OV7640=m
CONFIG_VIDEO_OV7670=m
CONFIG_VIDEO_OV772X=m
CONFIG_VIDEO_OV7740=m
CONFIG_VIDEO_OV8856=m
CONFIG_VIDEO_OV8858=m
CONFIG_VIDEO_OV8865=m
CONFIG_VIDEO_OV9281=m
CONFIG_VIDEO_OV9282=m
CONFIG_VIDEO_OV9640=m
CONFIG_VIDEO_OV9650=m
CONFIG_VIDEO_OV9734=m
CONFIG_VIDEO_OX03C10=m
CONFIG_VIDEO_PREISP_DUMMY_SENSOR=m
CONFIG_VIDEO_PS5458=m
CONFIG_VIDEO_RDACM20=m
CONFIG_VIDEO_RDACM21=m
CONFIG_VIDEO_RJ54N1=m
CONFIG_VIDEO_S5C73M3=m
CONFIG_VIDEO_S5K3L6XX=m
CONFIG_VIDEO_S5K3L8XX=m
CONFIG_VIDEO_S5K4ECGX=m
CONFIG_VIDEO_S5K5BAF=m
CONFIG_VIDEO_S5K6A3=m
CONFIG_VIDEO_S5K6AA=m
CONFIG_VIDEO_S5KJN1=m
CONFIG_VIDEO_SC031GS=m
CONFIG_VIDEO_SC035GS=m
CONFIG_VIDEO_SC132GS=m
# CONFIG_VIDEO_SC1346 is not set
CONFIG_VIDEO_SC200AI=m
CONFIG_VIDEO_SC210IOT=m
CONFIG_VIDEO_SC2232=m
CONFIG_VIDEO_SC2239=m
# CONFIG_VIDEO_SC223A is not set
CONFIG_VIDEO_SC230AI=m
CONFIG_VIDEO_SC2310=m
CONFIG_VIDEO_SC231HAI=m
CONFIG_VIDEO_SC2336=m
# CONFIG_VIDEO_SC2355 is not set
CONFIG_VIDEO_SC235HAI=m
CONFIG_VIDEO_SC301IOT=m
CONFIG_VIDEO_SC3336=m
# CONFIG_VIDEO_SC3336P is not set
CONFIG_VIDEO_SC3338=m
CONFIG_VIDEO_SC401AI=m
CONFIG_VIDEO_SC4210=m
CONFIG_VIDEO_SC4238=m
CONFIG_VIDEO_SC430CS=m
CONFIG_VIDEO_SC4336=m
# CONFIG_VIDEO_SC4336P is not set
CONFIG_VIDEO_SC450AI=m
CONFIG_VIDEO_SC485SL=m
CONFIG_VIDEO_SC500AI=m
CONFIG_VIDEO_SC501AI=m
CONFIG_VIDEO_SC530AI=m
# CONFIG_VIDEO_SC5336 is not set
CONFIG_VIDEO_SC635HAI=m
# CONFIG_VIDEO_SC830AI is not set
# CONFIG_VIDEO_SC831AI is not set
CONFIG_VIDEO_SC850SL=m
CONFIG_VIDEO_SENSOR_ADAPTER=y
CONFIG_VIDEO_SR030PC30=m
CONFIG_VIDEO_VS6624=m
CONFIG_VIDEO_CCS=m
CONFIG_VIDEO_ET8EK8=m
CONFIG_VIDEO_M5MOLS=m

#
# Lens drivers
#
CONFIG_VIDEO_AD5820=m
CONFIG_VIDEO_AK7375=m
CONFIG_VIDEO_AW8601=m
CONFIG_VIDEO_CES6301=m
CONFIG_VIDEO_CN3927V=m
CONFIG_VIDEO_DW9714=m
CONFIG_VIDEO_DW9763=m
CONFIG_VIDEO_DW9768=m
CONFIG_VIDEO_DW9800V=m
CONFIG_VIDEO_DW9800W=m
CONFIG_VIDEO_DW9807_VCM=m
CONFIG_VIDEO_FP5510=m
CONFIG_VIDEO_VM149C=m
# end of Lens drivers

#
# Flash devices
#
CONFIG_VIDEO_ADP1653=m
CONFIG_VIDEO_AW36518=m
CONFIG_VIDEO_LM3560=m
CONFIG_VIDEO_LM3646=m
CONFIG_VIDEO_SGM3784=m
# end of Flash devices

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_CS3308=m
CONFIG_VIDEO_CS5345=m
CONFIG_VIDEO_CS53L32A=m
CONFIG_VIDEO_MSP3400=m
CONFIG_VIDEO_SONY_BTF_MPX=m
CONFIG_VIDEO_TDA1997X=m
CONFIG_VIDEO_TDA7432=m
CONFIG_VIDEO_TDA9840=m
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
CONFIG_VIDEO_TLV320AIC23B=m
CONFIG_VIDEO_TVAUDIO=m
CONFIG_VIDEO_UDA1342=m
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_WM8739=m
CONFIG_VIDEO_WM8775=m
# end of Audio decoders, processors and mixers

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders

#
# Video decoders
#
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_ADV7183=m
CONFIG_VIDEO_ADV748X=m
CONFIG_VIDEO_ADV7604=m
# CONFIG_VIDEO_ADV7604_CEC is not set
CONFIG_VIDEO_ADV7842=m
# CONFIG_VIDEO_ADV7842_CEC is not set
CONFIG_VIDEO_BT819=m
CONFIG_VIDEO_BT856=m
CONFIG_VIDEO_BT866=m
CONFIG_VIDEO_EP9461E=m
CONFIG_VIDEO_ISL7998X=m
CONFIG_VIDEO_IT6616=m
CONFIG_VIDEO_KS0127=m
CONFIG_VIDEO_LT6911C=m
CONFIG_VIDEO_LT6911UXC=m
CONFIG_VIDEO_LT6911UXE=m
CONFIG_VIDEO_LT7911D=m
CONFIG_VIDEO_LT7911UXC=m
CONFIG_VIDEO_LT8619C=m
CONFIG_VIDEO_LT8668SX=m
CONFIG_VIDEO_MAX9286=m
# CONFIG_VIDEO_MAX96712 is not set
# CONFIG_VIDEO_MAX96714 is not set
# CONFIG_VIDEO_MAX96722 is not set
# CONFIG_VIDEO_MAX96756 is not set
CONFIG_VIDEO_ML86V7667=m
CONFIG_VIDEO_NVP6158=m
CONFIG_VIDEO_NVP6188=m
CONFIG_VIDEO_NVP6324=m
CONFIG_VIDEO_OTP_EEPROM=m
CONFIG_VIDEO_SAA7110=m
CONFIG_VIDEO_SAA711X=m
CONFIG_VIDEO_TC358743=m
# CONFIG_VIDEO_TC358743_CEC is not set
CONFIG_VIDEO_TC35874X=m
CONFIG_VIDEO_TECHPOINT=m
CONFIG_VIDEO_THCV244=m
CONFIG_VIDEO_TP2855=m
CONFIG_VIDEO_TVP514X=m
CONFIG_VIDEO_TVP5150=m
CONFIG_VIDEO_TVP7002=m
CONFIG_VIDEO_TW2804=m
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=m
CONFIG_VIDEO_TW9910=m
CONFIG_VIDEO_VPX3220=m
CONFIG_VIDEO_RK628=y
CONFIG_VIDEO_RK628_CSI=y
CONFIG_VIDEO_RK628_BT1120=y
CONFIG_VIDEO_MAXIM_SERDES=m

#
# Maxim Deserializer devices support
#
CONFIG_VIDEO_MAXIM_DES_MAXIM2C=m
CONFIG_VIDEO_MAXIM_DES_MAXIM4C=m
# end of Maxim Deserializer devices support

#
# Maxim GMSL Remote Serializer devices support
#
CONFIG_VIDEO_MAXIM_SER_MAX9295=m
CONFIG_VIDEO_MAXIM_SER_MAX96715=m
CONFIG_VIDEO_MAXIM_SER_MAX96717=m
# end of Maxim GMSL Remote Serializer devices support

#
# Maxim GMSL Remote Sensor devices support
#
CONFIG_VIDEO_MAXIM_CAM_DUMMY=m
CONFIG_VIDEO_MAXIM_CAM_SC320AT=m
CONFIG_VIDEO_MAXIM_CAM_OX01F10=m
CONFIG_VIDEO_MAXIM_CAM_OV231X=m
CONFIG_VIDEO_MAXIM_CAM_OX03C10=m
CONFIG_VIDEO_MAXIM_CAM_OX03J10=m
CONFIG_VIDEO_MAXIM_CAM_OS04A10=m
# end of Maxim GMSL Remote Sensor devices support

#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=m
CONFIG_VIDEO_CX25840=m
CONFIG_VIDEO_IT66353=m
# end of Video decoders

#
# Video encoders
#
CONFIG_VIDEO_AD9389B=m
CONFIG_VIDEO_ADV7170=m
CONFIG_VIDEO_ADV7175=m
CONFIG_VIDEO_ADV7343=m
CONFIG_VIDEO_ADV7393=m
CONFIG_VIDEO_ADV7511=m
# CONFIG_VIDEO_ADV7511_CEC is not set
CONFIG_VIDEO_AK881X=m
CONFIG_VIDEO_SAA7127=m
CONFIG_VIDEO_SAA7185=m
CONFIG_VIDEO_THS8200=m
# end of Video encoders

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
CONFIG_VIDEO_UPD64083=m
# end of Video improvement chips

#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips

#
# SDR tuner chips
#
# end of SDR tuner chips

#
# Miscellaneous helper chips
#
CONFIG_VIDEO_I2C=m
CONFIG_VIDEO_M52790=m
CONFIG_VIDEO_RK_IRCUT=y
CONFIG_VIDEO_ST_MIPID02=m
CONFIG_VIDEO_THS7303=m
# end of Miscellaneous helper chips

#
# Media SPI Adapters
#
CONFIG_VIDEO_GS1662=m
# CONFIG_VIDEO_ROCKCHIP_PREISP is not set
# CONFIG_VIDEO_MS41908 is not set
# CONFIG_VIDEO_MS41968 is not set
# end of Media SPI Adapters
# end of Media ancillary drivers

#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
CONFIG_DRM=y
CONFIG_DRM_MIPI_DBI=m
CONFIG_DRM_EDID=y
# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_DEBUG_MM is not set
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
CONFIG_DRM_LOAD_EDID_FIRMWARE=y
CONFIG_DRM_DP=y
CONFIG_DRM_DP_AUX_BUS=m
CONFIG_DRM_DISPLAY_HELPER=y
CONFIG_DRM_DISPLAY_DP_HELPER=y
CONFIG_DRM_DISPLAY_HDCP_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
CONFIG_DRM_DP_AUX_CHARDEV=y
CONFIG_DRM_DP_CEC=y
CONFIG_DRM_TTM=m
CONFIG_DRM_TTM_HELPER=m
CONFIG_DRM_GEM_DMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=m

#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips

#
# ARM devices
#
# CONFIG_DRM_HDLCD is not set
# CONFIG_DRM_MALI_DISPLAY is not set
# CONFIG_DRM_KOMEDA is not set
# end of ARM devices

# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
CONFIG_DRM_ROCKCHIP=y
# CONFIG_ROCKCHIP_DRM_DEBUG is not set
CONFIG_ROCKCHIP_DRM_DIRECT_SHOW=y
# CONFIG_ROCKCHIP_DRM_SELF_TEST is not set
CONFIG_ROCKCHIP_VOP=y
CONFIG_ROCKCHIP_VOP2=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DIMMING_PANEL=y
CONFIG_ROCKCHIP_DRM_TVE=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI2=y
CONFIG_ROCKCHIP_DW_DP=y
CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_ROCKCHIP_LVDS=y
CONFIG_ROCKCHIP_PANEL_NOTIFIER=y
CONFIG_ROCKCHIP_RGB=y
CONFIG_ROCKCHIP_RK3066_HDMI=y
# CONFIG_ROCKCHIP_VCONN is not set
# CONFIG_DRM_ROCKCHIP_VKMS is not set
CONFIG_ROCKCHIP_DW_HDCP2=y
# CONFIG_ROCKCHIP_DP_MST_AUX_CLIENT is not set
CONFIG_DRM_ROCKCHIP_RK618=m
# CONFIG_DRM_VMWGFX is not set
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_USE_LVDS is not set
# CONFIG_DRM_RCAR_USE_MIPI_DSI is not set
CONFIG_DRM_QXL=m
CONFIG_DRM_VIRTIO_GPU=m
CONFIG_DRM_PANEL=y

#
# Display Panels
#
CONFIG_DRM_PANEL_ABT_Y030XX067A=m
CONFIG_DRM_PANEL_ARM_VERSATILE=m
CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
CONFIG_DRM_PANEL_DSI_CM=m
CONFIG_DRM_PANEL_LVDS=m
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_EDP=m
CONFIG_DRM_PANEL_EBBG_FT8719=m
CONFIG_DRM_PANEL_ELIDA_KD35T133=m
CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
CONFIG_DRM_PANEL_ILITEK_IL9322=m
CONFIG_DRM_PANEL_ILITEK_ILI9341=m
CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=m
CONFIG_DRM_PANEL_JDI_LT070ME05000=m
CONFIG_DRM_PANEL_JDI_R63452=m
CONFIG_DRM_PANEL_KHADAS_TS050=m
CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
CONFIG_DRM_PANEL_LG_LB035Q02=m
CONFIG_DRM_PANEL_LG_LG4573=m
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
CONFIG_DRM_PANEL_NOVATEK_NT35510=m
CONFIG_DRM_PANEL_NOVATEK_NT35560=m
CONFIG_DRM_PANEL_NOVATEK_NT35950=m
CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
CONFIG_DRM_PANEL_NOVATEK_NT39016=m
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
CONFIG_DRM_PANEL_MAXIM_MAX96752F=m
CONFIG_DRM_PANEL_MAXIM_MAX96772=m
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
CONFIG_DRM_PANEL_RADXA_DISPLAY_8HD=m
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
CONFIG_DRM_PANEL_RASPITS_TC358762=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
CONFIG_DRM_PANEL_RONBO_RB070D30=m
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
CONFIG_DRM_PANEL_TDO_TL070WSH30=m
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
CONFIG_DRM_PANEL_TPO_TPG110=m
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
CONFIG_DRM_PANEL_VISIONOX_RM69299=m
CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
# CONFIG_DRM_PANEL_INNOLUX_AFJ101_BA2131 is not set
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CHIPONE_ICN6211 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
CONFIG_DRM_DISPLAY_CONNECTOR=m
# CONFIG_DRM_ITE_IT6161 is not set
# CONFIG_DRM_ITE_IT6505 is not set
# CONFIG_DRM_LONTIUM_LT8912B is not set
# CONFIG_DRM_LONTIUM_LT9211 is not set
CONFIG_DRM_LONTIUM_LT9611=m
CONFIG_DRM_LONTIUM_LT9611UXC=m
# CONFIG_DRM_ITE_IT66121 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MAXIM_MAX96745 is not set
# CONFIG_DRM_MAXIM_MAX96755F is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
CONFIG_DRM_RK630_TVE=m
CONFIG_DRM_RK1000_TVE=m
# CONFIG_DRM_ROHM_BU18XL82 is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_DLPC3433 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI83 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
CONFIG_DRM_ANALOGIX_DP=y
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=y
# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
# CONFIG_DRM_DW_HDMI_CEC is not set
CONFIG_DRM_DW_MIPI_DSI=y
# end of Display Interface Bridges

# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
# CONFIG_DRM_LOGICVC is not set
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_BOCHS is not set
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_GM12U320 is not set
# CONFIG_DRM_PANEL_MIPI_DBI is not set
# CONFIG_DRM_SIMPLEDRM is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9163 is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_DRM_PL111 is not set
# CONFIG_DRM_LIMA is not set
# CONFIG_DRM_PANFROST is not set
# CONFIG_DRM_PANTHOR is not set
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_GUD is not set
# CONFIG_DRM_SSD130X is not set
# CONFIG_DRM_LEGACY is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_DRM_NOMODESET=y
CONFIG_MALI400=m
CONFIG_MALI450=y
CONFIG_MALI470=y
# CONFIG_MALI400_DEBUG is not set
# CONFIG_MALI400_PROFILING is not set
# CONFIG_MALI400_UMP is not set
CONFIG_MALI_DMA_BUF_MAP_ON_ATTACH=y
CONFIG_MALI_SHARED_INTERRUPTS=y
# CONFIG_MALI_PMU_PARALLEL_POWER_UP is not set
CONFIG_MALI_DT=y
CONFIG_MALI_DEVFREQ=y
# CONFIG_MALI_QUIET is not set
CONFIG_MALI_MIDGARD=m
# CONFIG_MALI_GATOR_SUPPORT is not set
# CONFIG_MALI_MIDGARD_ENABLE_TRACE is not set
# CONFIG_MALI_DMA_FENCE is not set
CONFIG_MALI_EXPERT=y
# CONFIG_MALI_CORESTACK is not set
# CONFIG_MALI_PRFCNT_SET_SECONDARY is not set
# CONFIG_MALI_PLATFORM_FAKE is not set
# CONFIG_MALI_PLATFORM_DEVICETREE is not set
CONFIG_MALI_PLATFORM_THIRDPARTY=y
CONFIG_MALI_PLATFORM_THIRDPARTY_NAME="rk"
CONFIG_MALI_DEBUG=y
CONFIG_MALI_FENCE_DEBUG=y
# CONFIG_MALI_NO_MALI is not set
# CONFIG_MALI_TRACE_TIMELINE is not set
# CONFIG_MALI_SYSTEM_TRACE is not set
# CONFIG_MALI_GPU_MMU_AARCH64 is not set
CONFIG_MALI_PWRSOFT_765=y
# CONFIG_MALI_KUTF is not set
# CONFIG_MALI_BIFROST is not set
# CONFIG_MALI_CSF_INCLUDE_FW is not set
CONFIG_MALI_VALHALL=m
CONFIG_MALI_VALHALL_PLATFORM_NAME="rk"
CONFIG_MALI_VALHALL_REAL_HW=y
# CONFIG_MALI_VALHALL_NO_MALI is not set

#
# Platform specific options
#
# end of Platform specific options

CONFIG_MALI_VALHALL_CSF_SUPPORT=y
CONFIG_MALI_VALHALL_DEVFREQ=y
CONFIG_MALI_VALHALL_GATOR_SUPPORT=y
CONFIG_MALI_VALHALL_ENABLE_TRACE=y
# CONFIG_MALI_VALHALL_DMA_BUF_MAP_ON_DEMAND is not set
# CONFIG_MALI_VALHALL_DMA_BUF_LEGACY_COMPAT is not set
# CONFIG_MALI_VALHALL_CORESIGHT is not set
CONFIG_MALI_VALHALL_EXPERT=y
CONFIG_VALHALL_LARGE_PAGE_SUPPORT=y
# CONFIG_MALI_VALHALL_CORESTACK is not set

#
# Debug options
#
CONFIG_MALI_VALHALL_DEBUG=y
CONFIG_MALI_VALHALL_FENCE_DEBUG=y
CONFIG_MALI_VALHALL_SYSTEM_TRACE=y

#
# Instrumentation options
#
CONFIG_MALI_VALHALL_PRFCNT_SET_PRIMARY=y
# CONFIG_MALI_VALHALL_PRFCNT_SET_SECONDARY is not set
# CONFIG_MALI_VALHALL_PRFCNT_SET_TERTIARY is not set
# CONFIG_MALI_VALHALL_JOB_DUMP is not set

#
# Workarounds
#
# CONFIG_MALI_VALHALL_HW_ERRATA_1485982_NOT_AFFECTED is not set
# CONFIG_MALI_VALHALL_HW_ERRATA_1485982_USE_CLOCK_ALTERNATIVE is not set
CONFIG_MALI_VALHALL_TRACE_POWER_GPU_WORK_PERIOD=y

#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_BACKLIGHT=m
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
CONFIG_FB_ARMCLCD=m
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
CONFIG_FB_UVESA=m
# CONFIG_FB_EFI is not set
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
CONFIG_FB_SIMPLE=y
# CONFIG_FB_SSD1307 is not set
# CONFIG_FB_SM712 is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_L4F00242T03 is not set
# CONFIG_LCD_LMS283GF05 is not set
# CONFIG_LCD_LTV350QV is not set
# CONFIG_LCD_ILI922X is not set
# CONFIG_LCD_ILI9320 is not set
# CONFIG_LCD_TDO24M is not set
# CONFIG_LCD_VGG2432A4 is not set
# CONFIG_LCD_PLATFORM is not set
# CONFIG_LCD_AMS369FG06 is not set
# CONFIG_LCD_LMS501KF03 is not set
# CONFIG_LCD_HX8357 is not set
# CONFIG_LCD_OTM3225A is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_KTD253 is not set
CONFIG_BACKLIGHT_PWM=m
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
CONFIG_BACKLIGHT_GPIO=m
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
CONFIG_BACKLIGHT_LED=m
# end of Backlight & LCD device support

#
# Rockchip Misc Video driver
#

#
# RGA
#
# CONFIG_ROCKCHIP_RGA is not set
# end of RGA

CONFIG_ROCKCHIP_MULTI_RGA=y
CONFIG_ROCKCHIP_RGA_ASYNC=y
CONFIG_ROCKCHIP_RGA_PROC_FS=y
CONFIG_ROCKCHIP_RGA_DEBUG_FS=y
CONFIG_ROCKCHIP_RGA_DEBUGGER=y
# CONFIG_ROCKCHIP_RGA_GENPOOL is not set
CONFIG_ROCKCHIP_RVE=y
CONFIG_ROCKCHIP_RVE_PROC_FS=y
CONFIG_ROCKCHIP_RVE_DEBUG_FS=y
CONFIG_ROCKCHIP_RVE_DEBUGGER=y

#
# IEP
#
CONFIG_IEP=y
# end of IEP

CONFIG_ROCKCHIP_MPP_SERVICE=y
CONFIG_ROCKCHIP_MPP_PROC_FS=y
CONFIG_ROCKCHIP_MPP_RKVDEC=y
CONFIG_ROCKCHIP_MPP_RKVDEC2=y
CONFIG_ROCKCHIP_MPP_RKVENC=y
CONFIG_ROCKCHIP_MPP_RKVENC2=y
CONFIG_ROCKCHIP_MPP_VDPU1=y
CONFIG_ROCKCHIP_MPP_VEPU1=y
CONFIG_ROCKCHIP_MPP_VDPU2=y
CONFIG_ROCKCHIP_MPP_VEPU2=y
CONFIG_ROCKCHIP_MPP_IEP2=y
CONFIG_ROCKCHIP_MPP_JPGDEC=y
CONFIG_ROCKCHIP_MPP_JPGENC=y
CONFIG_ROCKCHIP_MPP_AV1DEC=y
CONFIG_ROCKCHIP_MPP_VDPP=y
CONFIG_ROCKCHIP_MPP_OSAL=y
# CONFIG_ROCKCHIP_DVBM is not set
# CONFIG_VIDEO_REVERSE_IMAGE is not set

#
# Rockchip video tunnel support
#
CONFIG_ROCKCHIP_VIDEO_TUNNEL=m
# end of Rockchip video tunnel support
# end of Rockchip Misc Video driver

CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
# end of Console display driver support

CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
# end of Graphics support

CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=m
CONFIG_SND_SEQ_DEVICE=y
CONFIG_SND_RAWMIDI=y
CONFIG_SND_COMPRESS_OFFLOAD=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_OSSEMUL is not set
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_VERBOSE_PRINTK is not set
CONFIG_SND_CTL_FAST_LOOKUP=y
# CONFIG_SND_DEBUG is not set
# CONFIG_SND_CTL_INPUT_VALIDATION is not set
CONFIG_SND_VMASTER=y
CONFIG_SND_SEQUENCER=m
CONFIG_SND_SEQ_DUMMY=m
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
CONFIG_SND_SEQ_MIDI_EVENT=m
CONFIG_SND_SEQ_MIDI=m
CONFIG_SND_SEQ_VIRMIDI=m
CONFIG_SND_MPU401_UART=m
CONFIG_SND_AC97_CODEC=m
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
CONFIG_SND_VIRMIDI=m
CONFIG_SND_MTPAV=m
CONFIG_SND_SERIAL_U16550=m
# CONFIG_SND_SERIAL_GENERIC is not set
CONFIG_SND_MPU401=m
# CONFIG_SND_AC97_POWER_SAVE is not set
# CONFIG_SND_PCI is not set

#
# HD-Audio
#
CONFIG_SND_HDA=m
# CONFIG_SND_HDA_HWDEP is not set
# CONFIG_SND_HDA_RECONFIG is not set
# CONFIG_SND_HDA_INPUT_BEEP is not set
# CONFIG_SND_HDA_PATCH_LOADER is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
# CONFIG_SND_HDA_CODEC_REALTEK is not set
# CONFIG_SND_HDA_CODEC_ANALOG is not set
# CONFIG_SND_HDA_CODEC_SIGMATEL is not set
# CONFIG_SND_HDA_CODEC_VIA is not set
# CONFIG_SND_HDA_CODEC_HDMI is not set
# CONFIG_SND_HDA_CODEC_CIRRUS is not set
# CONFIG_SND_HDA_CODEC_CS8409 is not set
# CONFIG_SND_HDA_CODEC_CONEXANT is not set
# CONFIG_SND_HDA_CODEC_CA0110 is not set
# CONFIG_SND_HDA_CODEC_CA0132 is not set
# CONFIG_SND_HDA_CODEC_CMEDIA is not set
# CONFIG_SND_HDA_CODEC_SI3054 is not set
# CONFIG_SND_HDA_GENERIC is not set
CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
# end of HD-Audio

CONFIG_SND_HDA_CORE=m
CONFIG_SND_HDA_EXT_CORE=m
CONFIG_SND_HDA_PREALLOC_SIZE=64
# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
CONFIG_SND_BCD2000=m
CONFIG_SND_USB_LINE6=m
CONFIG_SND_USB_POD=m
CONFIG_SND_USB_PODHD=m
CONFIG_SND_USB_TONEPORT=m
CONFIG_SND_USB_VARIAX=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
# CONFIG_SND_SOC_DYNAMIC_DMA_CHAN is not set
CONFIG_SND_SOC_COMPRESS=y
# CONFIG_SND_SOC_ADI is not set
# CONFIG_SND_SOC_AMD_ACP is not set
# CONFIG_SND_AMD_ACP_CONFIG is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
CONFIG_SND_DESIGNWARE_I2S=m
# CONFIG_SND_DESIGNWARE_PCM is not set

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
# CONFIG_SND_SOC_FSL_SAI is not set
# CONFIG_SND_SOC_FSL_AUDMIX is not set
# CONFIG_SND_SOC_FSL_SSI is not set
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
# CONFIG_SND_SOC_FSL_MICFIL is not set
# CONFIG_SND_SOC_FSL_XCVR is not set
# CONFIG_SND_SOC_FSL_RPMSG is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs

# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set
CONFIG_SND_SOC_ROCKCHIP=y
CONFIG_SND_SOC_ROCKCHIP_ASRC=y
CONFIG_SND_SOC_ROCKCHIP_DLP=y
CONFIG_SND_SOC_ROCKCHIP_DLP_PCM=y
CONFIG_SND_SOC_ROCKCHIP_DUMMY_DAI=y
CONFIG_SND_SOC_ROCKCHIP_I2S=y
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES=y
CONFIG_SND_SOC_ROCKCHIP_MULTI_DAIS=y
CONFIG_SND_SOC_ROCKCHIP_PDM=y
CONFIG_SND_SOC_ROCKCHIP_PDM_V2=y
CONFIG_SND_SOC_ROCKCHIP_SAI=y
CONFIG_SND_SOC_ROCKCHIP_SAI_VERBOSE=y
CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
CONFIG_SND_SOC_ROCKCHIP_SPDIFRX=y
CONFIG_SND_SOC_ROCKCHIP_TRCM=y
CONFIG_SND_SOC_ROCKCHIP_VAD=y
CONFIG_SND_SOC_ROCKCHIP_MAX98090=y
CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
CONFIG_SND_SOC_ROCKCHIP_RT5645=y
CONFIG_SND_SOC_ROCKCHIP_HDMI=y
CONFIG_SND_SOC_RK3288_HDMI_ANALOG=y
CONFIG_SND_SOC_RK3399_GRU_SOUND=y
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set

#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support

# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# CONFIG_SND_SOC_XTFPGA_I2S is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
CONFIG_SND_SOC_WM_ADSP=m
CONFIG_SND_SOC_AC97_CODEC=m
CONFIG_SND_SOC_ADAU_UTILS=m
CONFIG_SND_SOC_ADAU1372=m
CONFIG_SND_SOC_ADAU1372_I2C=m
CONFIG_SND_SOC_ADAU1372_SPI=m
CONFIG_SND_SOC_ADAU1701=m
CONFIG_SND_SOC_ADAU17X1=m
CONFIG_SND_SOC_ADAU1761=m
CONFIG_SND_SOC_ADAU1761_I2C=m
CONFIG_SND_SOC_ADAU1761_SPI=m
CONFIG_SND_SOC_ADAU7002=m
CONFIG_SND_SOC_ADAU7118=m
CONFIG_SND_SOC_ADAU7118_HW=m
CONFIG_SND_SOC_ADAU7118_I2C=m
CONFIG_SND_SOC_AK4104=m
CONFIG_SND_SOC_AK4118=m
CONFIG_SND_SOC_AK4375=m
CONFIG_SND_SOC_AK4458=m
CONFIG_SND_SOC_AK4554=m
CONFIG_SND_SOC_AK4613=m
CONFIG_SND_SOC_AK4642=m
CONFIG_SND_SOC_AK5386=m
CONFIG_SND_SOC_AK5558=m
CONFIG_SND_SOC_ALC5623=m
CONFIG_SND_SOC_AW8738=m
CONFIG_SND_SOC_BD28623=m
CONFIG_SND_SOC_BT_SCO=m
CONFIG_SND_SOC_CS35L32=m
CONFIG_SND_SOC_CS35L33=m
CONFIG_SND_SOC_CS35L34=m
CONFIG_SND_SOC_CS35L35=m
CONFIG_SND_SOC_CS35L36=m
CONFIG_SND_SOC_CS35L41_LIB=m
CONFIG_SND_SOC_CS35L41=m
CONFIG_SND_SOC_CS35L41_SPI=m
CONFIG_SND_SOC_CS35L41_I2C=m
CONFIG_SND_SOC_CS35L45_TABLES=m
CONFIG_SND_SOC_CS35L45=m
CONFIG_SND_SOC_CS35L45_SPI=m
CONFIG_SND_SOC_CS35L45_I2C=m
CONFIG_SND_SOC_CS42L42_CORE=m
CONFIG_SND_SOC_CS42L42=m
CONFIG_SND_SOC_CS42L51=m
CONFIG_SND_SOC_CS42L51_I2C=m
CONFIG_SND_SOC_CS42L52=m
CONFIG_SND_SOC_CS42L56=m
CONFIG_SND_SOC_CS42L73=m
CONFIG_SND_SOC_CS42L83=m
CONFIG_SND_SOC_CS4234=m
CONFIG_SND_SOC_CS4265=m
CONFIG_SND_SOC_CS4270=m
CONFIG_SND_SOC_CS4271=m
CONFIG_SND_SOC_CS4271_I2C=m
CONFIG_SND_SOC_CS4271_SPI=m
CONFIG_SND_SOC_CS42XX8=m
CONFIG_SND_SOC_CS42XX8_I2C=m
CONFIG_SND_SOC_CS43130=m
CONFIG_SND_SOC_CS4341=m
CONFIG_SND_SOC_CS4349=m
CONFIG_SND_SOC_CS53L30=m
CONFIG_SND_SOC_CX2072X=m
CONFIG_SND_SOC_DA7213=m
CONFIG_SND_SOC_DA7219=y
CONFIG_SND_SOC_DMIC=y
CONFIG_SND_SOC_DUMMY_CODEC=y
CONFIG_SND_SOC_HDMI_CODEC=y
CONFIG_SND_SOC_ES7134=m
CONFIG_SND_SOC_ES7202=m
CONFIG_SND_SOC_ES7202_MIC_MAX_CHANNELS=2
CONFIG_SND_SOC_ES7202_I2C_BUS=1
CONFIG_SND_SOC_ES7210=m
CONFIG_SND_SOC_ES7241=m
CONFIG_SND_SOC_ES7243E=m
CONFIG_SND_SOC_ES8311=m
CONFIG_SND_SOC_ES8316=m
CONFIG_SND_SOC_ES8323=m
CONFIG_SND_SOC_ES8326=m
CONFIG_SND_SOC_ES8328=y
CONFIG_SND_SOC_ES8328_I2C=y
CONFIG_SND_SOC_ES8328_SPI=y
CONFIG_SND_SOC_ES8389=m
CONFIG_SND_SOC_ES8396=m
CONFIG_SND_SOC_GTM601=m
CONFIG_SND_SOC_HDA=m
CONFIG_SND_SOC_ICS43432=m
CONFIG_SND_SOC_INNO_RK3036=m
CONFIG_SND_SOC_MAX98088=m
CONFIG_SND_SOC_MAX98090=y
CONFIG_SND_SOC_MAX98357A=y
CONFIG_SND_SOC_MAX98504=m
CONFIG_SND_SOC_MAX9867=m
CONFIG_SND_SOC_MAX98927=m
CONFIG_SND_SOC_MAX98520=m
CONFIG_SND_SOC_MAX98373=m
CONFIG_SND_SOC_MAX98373_I2C=m
CONFIG_SND_SOC_MAX98390=m
CONFIG_SND_SOC_MAX98396=m
CONFIG_SND_SOC_MAX9860=m
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
CONFIG_SND_SOC_PCM1681=m
CONFIG_SND_SOC_PCM1789=m
CONFIG_SND_SOC_PCM1789_I2C=m
CONFIG_SND_SOC_PCM179X=m
CONFIG_SND_SOC_PCM179X_I2C=m
CONFIG_SND_SOC_PCM179X_SPI=m
CONFIG_SND_SOC_PCM186X=m
CONFIG_SND_SOC_PCM186X_I2C=m
CONFIG_SND_SOC_PCM186X_SPI=m
CONFIG_SND_SOC_PCM3060=m
CONFIG_SND_SOC_PCM3060_I2C=m
CONFIG_SND_SOC_PCM3060_SPI=m
CONFIG_SND_SOC_PCM3168A=m
CONFIG_SND_SOC_PCM3168A_I2C=m
CONFIG_SND_SOC_PCM3168A_SPI=m
CONFIG_SND_SOC_PCM5102A=m
CONFIG_SND_SOC_PCM512x=m
CONFIG_SND_SOC_PCM512x_I2C=m
CONFIG_SND_SOC_PCM512x_SPI=m
CONFIG_SND_SOC_RK1000=y
CONFIG_SND_SOC_RK312X=y
CONFIG_SND_SOC_RK3228=y
CONFIG_SND_SOC_RK3308=y
CONFIG_SND_SOC_RK3328=y
CONFIG_SND_SOC_RK3506=y
CONFIG_SND_SOC_RK3528=y
CONFIG_SND_SOC_RK730=y
CONFIG_SND_SOC_RK817=y
CONFIG_SND_SOC_RK_CODEC_DIGITAL=y
CONFIG_SND_SOC_RK_DSM=y
CONFIG_SND_SOC_RL6231=y
CONFIG_SND_SOC_ROCKCHIP_SPI_CODEC=y
CONFIG_SND_SOC_RT5514=y
CONFIG_SND_SOC_RT5514_SPI=y
CONFIG_SND_SOC_RT5616=m
CONFIG_SND_SOC_RT5631=m
CONFIG_SND_SOC_RT5640=m
CONFIG_SND_SOC_RT5645=y
CONFIG_SND_SOC_RT5651=m
CONFIG_SND_SOC_RT5659=m
CONFIG_SND_SOC_RT9120=m
CONFIG_SND_SOC_RV1106=y
CONFIG_SND_SOC_SGTL5000=m
CONFIG_SND_SOC_SIGMADSP=m
CONFIG_SND_SOC_SIGMADSP_I2C=m
CONFIG_SND_SOC_SIGMADSP_REGMAP=m
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
CONFIG_SND_SOC_SIMPLE_MUX=y
CONFIG_SND_SOC_SPDIF=y
CONFIG_SND_SOC_SRC4XXX_I2C=m
CONFIG_SND_SOC_SRC4XXX=m
CONFIG_SND_SOC_SSM2305=m
CONFIG_SND_SOC_SSM2518=m
CONFIG_SND_SOC_SSM2602=m
CONFIG_SND_SOC_SSM2602_SPI=m
CONFIG_SND_SOC_SSM2602_I2C=m
CONFIG_SND_SOC_SSM4567=m
CONFIG_SND_SOC_STA32X=m
CONFIG_SND_SOC_STA350=m
CONFIG_SND_SOC_STI_SAS=m
CONFIG_SND_SOC_TAS2552=m
CONFIG_SND_SOC_TAS2562=m
CONFIG_SND_SOC_TAS2764=m
CONFIG_SND_SOC_TAS2770=m
CONFIG_SND_SOC_TAS2780=m
CONFIG_SND_SOC_TAS5086=m
CONFIG_SND_SOC_TAS571X=m
CONFIG_SND_SOC_TAS5720=m
CONFIG_SND_SOC_TAS5805M=m
CONFIG_SND_SOC_TAS6424=m
CONFIG_SND_SOC_TDA7419=m
CONFIG_SND_SOC_TDA7803=m
CONFIG_SND_SOC_TFA9879=m
CONFIG_SND_SOC_TFA989X=m
CONFIG_SND_SOC_TLV320ADC3XXX=m
CONFIG_SND_SOC_TLV320AIC23=m
CONFIG_SND_SOC_TLV320AIC23_I2C=m
CONFIG_SND_SOC_TLV320AIC23_SPI=m
CONFIG_SND_SOC_TLV320AIC31XX=m
CONFIG_SND_SOC_TLV320AIC32X4=m
CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
CONFIG_SND_SOC_TLV320AIC3X=m
CONFIG_SND_SOC_TLV320AIC3X_I2C=m
CONFIG_SND_SOC_TLV320AIC3X_SPI=m
CONFIG_SND_SOC_TLV320ADCX140=m
CONFIG_SND_SOC_TS3A227E=y
CONFIG_SND_SOC_TSCS42XX=m
CONFIG_SND_SOC_TSCS454=m
CONFIG_SND_SOC_UDA1334=m
CONFIG_SND_SOC_WM8510=m
CONFIG_SND_SOC_WM8523=m
CONFIG_SND_SOC_WM8524=m
CONFIG_SND_SOC_WM8580=m
CONFIG_SND_SOC_WM8711=m
CONFIG_SND_SOC_WM8728=m
CONFIG_SND_SOC_WM8731=m
CONFIG_SND_SOC_WM8731_I2C=m
CONFIG_SND_SOC_WM8731_SPI=m
CONFIG_SND_SOC_WM8737=m
CONFIG_SND_SOC_WM8741=m
CONFIG_SND_SOC_WM8750=m
CONFIG_SND_SOC_WM8753=m
CONFIG_SND_SOC_WM8770=m
CONFIG_SND_SOC_WM8776=m
CONFIG_SND_SOC_WM8782=m
CONFIG_SND_SOC_WM8804=m
CONFIG_SND_SOC_WM8804_I2C=m
CONFIG_SND_SOC_WM8804_SPI=m
CONFIG_SND_SOC_WM8903=m
CONFIG_SND_SOC_WM8904=m
CONFIG_SND_SOC_WM8940=m
CONFIG_SND_SOC_WM8960=m
CONFIG_SND_SOC_WM8962=m
CONFIG_SND_SOC_WM8974=m
CONFIG_SND_SOC_WM8978=m
CONFIG_SND_SOC_WM8985=m
CONFIG_SND_SOC_ZL38060=m
CONFIG_SND_SOC_MAX9759=m
CONFIG_SND_SOC_MT6351=m
CONFIG_SND_SOC_MT6358=m
CONFIG_SND_SOC_MT6660=m
CONFIG_SND_SOC_NAU8315=m
CONFIG_SND_SOC_NAU8540=m
CONFIG_SND_SOC_NAU8810=m
CONFIG_SND_SOC_NAU8821=m
CONFIG_SND_SOC_NAU8822=m
CONFIG_SND_SOC_NAU8824=m
CONFIG_SND_SOC_TPA6130A2=m
CONFIG_SND_SOC_LPASS_MACRO_COMMON=m
CONFIG_SND_SOC_LPASS_WSA_MACRO=m
CONFIG_SND_SOC_LPASS_VA_MACRO=m
CONFIG_SND_SOC_LPASS_RX_MACRO=m
CONFIG_SND_SOC_LPASS_TX_MACRO=m
CONFIG_SND_SOC_AW87XXX=m
CONFIG_SND_SOC_AW882XX=m
CONFIG_SND_SOC_AW883XX=m
CONFIG_SND_SOC_IT6621=m
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD2=y
CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=y
# CONFIG_SND_TEST_COMPONENT is not set
CONFIG_SND_VIRTIO=y
CONFIG_AC97_BUS=y

#
# HID support
#
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=y
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
CONFIG_HID_A4TECH=m
CONFIG_HID_ACCUTOUCH=m
CONFIG_HID_ACRUX=m
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=m
CONFIG_HID_APPLEIR=m
CONFIG_HID_ASUS=m
CONFIG_HID_AUREAL=m
CONFIG_HID_BELKIN=m
CONFIG_HID_BETOP_FF=m
CONFIG_HID_BIGBEN_FF=m
CONFIG_HID_CHERRY=m
CONFIG_HID_CHICONY=m
CONFIG_HID_CORSAIR=m
CONFIG_HID_COUGAR=m
CONFIG_HID_MACALLY=m
CONFIG_HID_PRODIKEYS=m
CONFIG_HID_CMEDIA=m
CONFIG_HID_CP2112=m
CONFIG_HID_CREATIVE_SB0540=m
CONFIG_HID_CYPRESS=m
CONFIG_HID_DRAGONRISE=m
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=m
CONFIG_HID_ELAN=m
CONFIG_HID_ELECOM=m
CONFIG_HID_ELO=m
CONFIG_HID_EZKEY=m
CONFIG_HID_FT260=m
CONFIG_HID_GEMBIRD=m
CONFIG_HID_GFRM=m
CONFIG_HID_GLORIOUS=m
CONFIG_HID_HOLTEK=m
CONFIG_HOLTEK_FF=y
CONFIG_HID_VIVALDI_COMMON=m
CONFIG_HID_VIVALDI=m
CONFIG_HID_GT683R=m
CONFIG_HID_KEYTOUCH=m
CONFIG_HID_KYE=m
CONFIG_HID_UCLOGIC=m
CONFIG_HID_WALTOP=m
CONFIG_HID_VIEWSONIC=m
CONFIG_HID_VRC2=m
CONFIG_HID_XIAOMI=m
CONFIG_HID_GYRATION=m
CONFIG_HID_ICADE=m
CONFIG_HID_ITE=m
CONFIG_HID_JABRA=m
CONFIG_HID_TWINHAN=m
CONFIG_HID_KENSINGTON=m
CONFIG_HID_LCPOWER=m
CONFIG_HID_LED=m
CONFIG_HID_LENOVO=m
CONFIG_HID_LETSKETCH=m
CONFIG_HID_LOGITECH=m
CONFIG_HID_LOGITECH_DJ=m
CONFIG_HID_LOGITECH_HIDPP=m
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
CONFIG_HID_MAGICMOUSE=m
CONFIG_HID_MALTRON=m
CONFIG_HID_MAYFLASH=m
CONFIG_HID_MEGAWORLD_FF=m
CONFIG_HID_REDRAGON=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
CONFIG_HID_MULTITOUCH=m
CONFIG_HID_NINTENDO=m
# CONFIG_NINTENDO_FF is not set
CONFIG_HID_NTI=m
CONFIG_HID_NTRIG=m
CONFIG_HID_ORTEK=m
CONFIG_HID_PANTHERLORD=m
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PENMOUNT=m
CONFIG_HID_PETALYNX=m
CONFIG_HID_PICOLCD=m
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
CONFIG_HID_PICOLCD_LCD=y
CONFIG_HID_PICOLCD_LEDS=y
CONFIG_HID_PICOLCD_CIR=y
CONFIG_HID_PLANTRONICS=m
CONFIG_HID_PLAYSTATION=m
CONFIG_PLAYSTATION_FF=y
CONFIG_HID_PXRC=m
CONFIG_HID_RAZER=m
CONFIG_HID_PRIMAX=m
CONFIG_HID_RETRODE=m
CONFIG_HID_ROCCAT=m
CONFIG_HID_SAITEK=m
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SEMITEK=m
CONFIG_HID_SIGMAMICRO=m
CONFIG_HID_SONY=m
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=m
CONFIG_HID_STEAM=m
CONFIG_HID_STEELSERIES=m
CONFIG_HID_SUNPLUS=m
CONFIG_HID_RMI=m
CONFIG_HID_GREENASIA=m
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=m
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TIVO=m
CONFIG_HID_TOPSEED=m
CONFIG_HID_TOPRE=m
CONFIG_HID_THINGM=m
CONFIG_HID_THRUSTMASTER=m
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_UDRAW_PS3=m
CONFIG_HID_U2FZERO=m
CONFIG_HID_WACOM=m
CONFIG_HID_WIIMOTE=m
CONFIG_HID_XINMO=m
CONFIG_HID_ZEROPLUS=m
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=m
CONFIG_HID_SENSOR_HUB=m
CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
CONFIG_HID_ALPS=m
CONFIG_HID_MCP2221=m
# end of Special HID drivers

#
# USB HID support
#
CONFIG_USB_HID=y
# CONFIG_HID_PID is not set
CONFIG_USB_HIDDEV=y
# end of USB HID support

#
# I2C HID support
#
CONFIG_I2C_HID_ACPI=m
CONFIG_I2C_HID_OF=m
CONFIG_I2C_HID_OF_ELAN=m
CONFIG_I2C_HID_OF_GOODIX=m
# end of I2C HID support

CONFIG_I2C_HID_CORE=m
# end of HID support

CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_LED_TRIG=y
CONFIG_USB_ULPI_BUS=m
CONFIG_USB_CONN_GPIO=m
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
CONFIG_USB_OTG_FSM=y
CONFIG_USB_LEDS_TRIGGER_USBPORT=y
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=m

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=m
CONFIG_USB_XHCI_PCI_RENESAS=m
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_EHCI_FSL=m
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OXU210HP_HCD=m
CONFIG_USB_ISP116X_HCD=m
CONFIG_USB_FOTG210_HCD=m
CONFIG_USB_MAX3421_HCD=m
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PCI=m
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_UHCI_HCD=m
CONFIG_USB_U132_HCD=m
CONFIG_USB_SL811_HCD=m
# CONFIG_USB_SL811_HCD_ISO is not set
CONFIG_USB_R8A66597_HCD=m
CONFIG_USB_HCD_BCMA=m
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=y
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=m
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
CONFIG_USB_STORAGE_REALTEK=m
CONFIG_REALTEK_AUTOPM=y
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_FREECOM=m
CONFIG_USB_STORAGE_ISD200=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_STORAGE_ALAUDA=m
CONFIG_USB_STORAGE_ONETOUCH=m
CONFIG_USB_STORAGE_KARMA=m
CONFIG_USB_STORAGE_CYPRESS_ATACB=m
CONFIG_USB_STORAGE_ENE_UB6250=m
# CONFIG_USB_UAS is not set

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
CONFIG_USB_MICROTEK=m
CONFIG_USBIP_CORE=m
CONFIG_USBIP_VHCI_HCD=m
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=m
CONFIG_USBIP_VUDC=m
CONFIG_USBIP_DEBUG=y
# CONFIG_USB_CDNS_SUPPORT is not set
CONFIG_USB_MUSB_HDRC=m
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y

#
# Platform Glue Layer
#

#
# MUSB DMA mode
#
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y

#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=m
CONFIG_USB_DWC3_HAPS=m
CONFIG_USB_DWC3_OF_SIMPLE=m
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
CONFIG_USB_DWC2_PCI=m
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
CONFIG_USB_CHIPIDEA=m
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_CHIPIDEA_PCI=m
CONFIG_USB_CHIPIDEA_MSM=m
CONFIG_USB_CHIPIDEA_IMX=m
CONFIG_USB_CHIPIDEA_GENERIC=m
CONFIG_USB_CHIPIDEA_TEGRA=m
# CONFIG_USB_ISP1760 is not set

#
# USB port drivers
#
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=y
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=y
CONFIG_USB_SERIAL_CH348=y
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=y
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=y
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=m
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_F81232=m
CONFIG_USB_SERIAL_F8153X=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=m
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_METRO=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MXUPORT=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=y
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=m
CONFIG_USB_SERIAL_QUALCOMM=m
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
CONFIG_USB_SERIAL_SAFE_PADDED=y
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
CONFIG_USB_SERIAL_SYMBOL=m
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_WWAN=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=m
CONFIG_USB_SERIAL_XSENS_MT=m
CONFIG_USB_SERIAL_WISHBONE=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_SERIAL_QT2=m
CONFIG_USB_SERIAL_UPD78F0730=m
CONFIG_USB_SERIAL_XR=m
CONFIG_USB_SERIAL_DEBUG=m

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
CONFIG_USB_CYPRESS_CY7C63=m
CONFIG_USB_CYTHERM=m
CONFIG_USB_IDMOUSE=m
CONFIG_USB_FTDI_ELAN=m
CONFIG_USB_APPLEDISPLAY=m
CONFIG_APPLE_MFI_FASTCHARGE=m
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
CONFIG_USB_TEST=m
CONFIG_USB_EHSET_TEST_FIXTURE=m
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=y
CONFIG_USB_HUB_USB251XB=m
CONFIG_USB_HSIC_USB3503=m
CONFIG_USB_HSIC_USB4604=m
CONFIG_USB_LINK_LAYER_TEST=m
CONFIG_USB_CHAOSKEY=m
CONFIG_USB_ONBOARD_HUB=y

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=m
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_ULPI is not set
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
CONFIG_USB_GADGET_DEBUG_FILES=y
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
CONFIG_U_SERIAL_CONSOLE=y

#
# USB Peripheral Controller
#
# CONFIG_USB_FOTG210_UDC is not set
# CONFIG_USB_GR_UDC is not set
# CONFIG_USB_R8A66597 is not set
# CONFIG_USB_PXA27X is not set
# CONFIG_USB_MV_UDC is not set
# CONFIG_USB_MV_U3D is not set
CONFIG_USB_SNP_CORE=y
CONFIG_USB_SNP_UDC_PLAT=y
# CONFIG_USB_M66592 is not set
# CONFIG_USB_BDC_UDC is not set
# CONFIG_USB_AMD5536UDC is not set
# CONFIG_USB_NET2272 is not set
# CONFIG_USB_NET2280 is not set
# CONFIG_USB_GOKU is not set
# CONFIG_USB_EG20T is not set
# CONFIG_USB_GADGET_XILINX is not set
# CONFIG_USB_MAX3420_UDC is not set
# CONFIG_USB_DUMMY_HCD is not set
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_F_ACM=y
CONFIG_USB_F_SS_LB=y
CONFIG_USB_U_SERIAL=y
CONFIG_USB_U_ETHER=y
CONFIG_USB_U_AUDIO=y
CONFIG_USB_F_SERIAL=y
CONFIG_USB_F_OBEX=y
CONFIG_USB_F_NCM=y
CONFIG_USB_F_ECM=y
CONFIG_USB_F_EEM=y
CONFIG_USB_F_SUBSET=y
CONFIG_USB_F_RNDIS=y
CONFIG_USB_F_MASS_STORAGE=y
CONFIG_USB_F_FS=y
CONFIG_USB_F_UAC1=y
CONFIG_USB_F_UAC1_LEGACY=y
CONFIG_USB_F_UAC2=y
CONFIG_USB_F_UVC=y
CONFIG_USB_F_MIDI=y
CONFIG_USB_F_HID=y
CONFIG_USB_F_PRINTER=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_UEVENT=y
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_LB_SS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y

#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=m
# CONFIG_USB_ZERO_HNPTEST is not set
CONFIG_USB_AUDIO=m
# CONFIG_GADGET_UAC1 is not set
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
CONFIG_USB_FUNCTIONFS_ETH=y
CONFIG_USB_FUNCTIONFS_RNDIS=y
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_G_HID=m
CONFIG_USB_G_DBGP=m
# CONFIG_USB_G_DBGP_PRINTK is not set
CONFIG_USB_G_DBGP_SERIAL=y
CONFIG_USB_G_WEBCAM=m
CONFIG_USB_RAW_GADGET=m
# end of USB Gadget precomposed configurations

CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
CONFIG_TYPEC_ET7303=y
CONFIG_TYPEC_HUSB311=y
CONFIG_TYPEC_RT1711H=y
CONFIG_TYPEC_TCPCI_MAXIM=y
CONFIG_TYPEC_FUSB302=y
CONFIG_TYPEC_UCSI=m
CONFIG_UCSI_CCG=m
CONFIG_UCSI_ACPI=m
CONFIG_UCSI_STM32G0=m
CONFIG_TYPEC_TPS6598X=m
CONFIG_TYPEC_ANX7411=m
CONFIG_TYPEC_RT1719=m
CONFIG_TYPEC_HD3SS3220=m
CONFIG_TYPEC_STUSB160X=m
CONFIG_TYPEC_WUSB3801=m

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
CONFIG_TYPEC_MUX_FSA4480=m
CONFIG_TYPEC_MUX_PI3USB30532=m
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
CONFIG_TYPEC_DP_ALTMODE=y
# CONFIG_TYPEC_NVIDIA_ALTMODE is not set
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
# CONFIG_PWRSEQ_SD8787 is not set
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_SDIO_UART is not set
CONFIG_MMC_TEST=y

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_ARMMMCI is not set
CONFIG_MMC_SDHCI=y
# CONFIG_MMC_SDHCI_PCI is not set
# CONFIG_MMC_SDHCI_ACPI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
CONFIG_MMC_SDHCI_OF_AT91=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_MMC_SDHCI_CADENCE=y
# CONFIG_MMC_SDHCI_F_SDH30 is not set
# CONFIG_MMC_SDHCI_MILBEAUT is not set
CONFIG_MMC_TIFM_SD=m
CONFIG_MMC_SPI=m
# CONFIG_MMC_CB710 is not set
CONFIG_MMC_VIA_SDMMC=m
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
# CONFIG_MMC_DW_BLUEFIELD is not set
# CONFIG_MMC_DW_EXYNOS is not set
# CONFIG_MMC_DW_HI3798CV200 is not set
# CONFIG_MMC_DW_K3 is not set
# CONFIG_MMC_DW_PCI is not set
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_VUB300=m
CONFIG_MMC_USHC=m
CONFIG_MMC_USDHI6ROL0=m
CONFIG_MMC_REALTEK_PCI=m
CONFIG_MMC_REALTEK_USB=m
CONFIG_MMC_CQHCI=y
CONFIG_MMC_HSQ=y
CONFIG_MMC_TOSHIBA_PCI=m
CONFIG_MMC_MTK=m
# CONFIG_MMC_SDHCI_XENON is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
CONFIG_LEDS_CLASS_MULTICOLOR=y
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y

#
# LED drivers
#
CONFIG_LEDS_AN30259A=m
CONFIG_LEDS_AW2013=m
CONFIG_LEDS_BCM6328=m
CONFIG_LEDS_BCM6358=m
CONFIG_LEDS_CR0014114=m
CONFIG_LEDS_EL15203000=m
CONFIG_LEDS_LM3530=m
CONFIG_LEDS_LM3532=m
CONFIG_LEDS_LM3642=m
CONFIG_LEDS_LM3692X=y
CONFIG_LEDS_PCA9532=m
CONFIG_LEDS_PCA9532_GPIO=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=m
CONFIG_LEDS_LP3952=m
CONFIG_LEDS_LP50XX=m
CONFIG_LEDS_LP55XX_COMMON=m
CONFIG_LEDS_LP5521=m
CONFIG_LEDS_LP5523=m
CONFIG_LEDS_LP5562=m
CONFIG_LEDS_LP8501=m
CONFIG_LEDS_LP8860=m
CONFIG_LEDS_PCA955X=m
CONFIG_LEDS_PCA955X_GPIO=y
CONFIG_LEDS_PCA963X=m
CONFIG_LEDS_DAC124S085=m
CONFIG_LEDS_PWM=y
CONFIG_LEDS_REGULATOR=y
CONFIG_LEDS_BD2802=m
CONFIG_LEDS_LT3593=m
CONFIG_LEDS_TCA6507=m
CONFIG_LEDS_TLC591XX=m
CONFIG_LEDS_LM355x=m
CONFIG_LEDS_IS31FL319X=m
CONFIG_LEDS_IS31FL32XX=m
CONFIG_LEDS_RGB13H=m

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=m
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_MLXREG=m
CONFIG_LEDS_USER=y
CONFIG_LEDS_SPI_BYTE=m
CONFIG_LEDS_TI_LMU_COMMON=m
CONFIG_LEDS_LM3697=m

#
# Flash and Torch LED drivers
#
CONFIG_LEDS_AAT1290=m
CONFIG_LEDS_AS3645A=m
CONFIG_LEDS_KTD2692=m
CONFIG_LEDS_LM3601X=y
CONFIG_LEDS_RT4505=m
CONFIG_LEDS_RT8515=m
CONFIG_LEDS_SGM3140=y

#
# RGB LED drivers
#
CONFIG_LEDS_PWM_MULTICOLOR=m

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_ACTIVITY=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=y
CONFIG_LEDS_TRIGGER_PATTERN=y
CONFIG_LEDS_TRIGGER_AUDIO=y
CONFIG_LEDS_TRIGGER_TTY=y

#
# Simple LED drivers
#
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
CONFIG_RTC_DRV_TEST=m

#
# I2C RTC drivers
#
CONFIG_RTC_DRV_ABB5ZES3=m
CONFIG_RTC_DRV_ABEOZ9=m
CONFIG_RTC_DRV_ABX80X=m
CONFIG_RTC_DRV_DS1307=m
CONFIG_RTC_DRV_DS1307_CENTURY=y
CONFIG_RTC_DRV_DS1374=m
CONFIG_RTC_DRV_DS1374_WDT=y
CONFIG_RTC_DRV_DS1672=m
CONFIG_RTC_DRV_HYM8563=y
CONFIG_RTC_DRV_MAX6900=m
CONFIG_RTC_DRV_NCT3018Y=m
# CONFIG_RTC_DRV_RK630 is not set
CONFIG_RTC_DRV_RK808=m
CONFIG_RTC_DRV_ROCKCHIP=m
CONFIG_RTC_DRV_RS5C372=m
CONFIG_RTC_DRV_ISL1208=m
CONFIG_RTC_DRV_ISL12022=m
CONFIG_RTC_DRV_ISL12026=m
CONFIG_RTC_DRV_X1205=m
CONFIG_RTC_DRV_PCF8523=m
CONFIG_RTC_DRV_PCF85063=m
CONFIG_RTC_DRV_PCF85363=m
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_PCF8583=y
CONFIG_RTC_DRV_M41T80=m
CONFIG_RTC_DRV_M41T80_WDT=y
CONFIG_RTC_DRV_BQ32K=m
CONFIG_RTC_DRV_S35390A=m
CONFIG_RTC_DRV_FM3130=m
CONFIG_RTC_DRV_RX8010=m
CONFIG_RTC_DRV_RX8581=m
CONFIG_RTC_DRV_RX8025=m
CONFIG_RTC_DRV_EM3027=m
CONFIG_RTC_DRV_RV3028=m
CONFIG_RTC_DRV_RV3032=m
CONFIG_RTC_DRV_RV8803=m
CONFIG_RTC_DRV_SD3078=m

#
# SPI RTC drivers
#
CONFIG_RTC_DRV_M41T93=m
CONFIG_RTC_DRV_M41T94=m
CONFIG_RTC_DRV_DS1302=m
CONFIG_RTC_DRV_DS1305=m
CONFIG_RTC_DRV_DS1343=m
CONFIG_RTC_DRV_DS1347=m
CONFIG_RTC_DRV_DS1390=m
CONFIG_RTC_DRV_MAX6916=m
CONFIG_RTC_DRV_R9701=m
CONFIG_RTC_DRV_RX4581=m
CONFIG_RTC_DRV_RS5C348=m
CONFIG_RTC_DRV_MAX6902=m
CONFIG_RTC_DRV_PCF2123=m
CONFIG_RTC_DRV_MCP795=m
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
CONFIG_RTC_DRV_DS3232=m
CONFIG_RTC_DRV_DS3232_HWMON=y
CONFIG_RTC_DRV_PCF2127=m
CONFIG_RTC_DRV_RV3029C2=m
CONFIG_RTC_DRV_RV3029_HWMON=y
CONFIG_RTC_DRV_RX6110=m

#
# Platform RTC drivers
#
CONFIG_RTC_DRV_DS1286=m
CONFIG_RTC_DRV_DS1511=m
CONFIG_RTC_DRV_DS1553=m
CONFIG_RTC_DRV_DS1685_FAMILY=m
CONFIG_RTC_DRV_DS1685=y
# CONFIG_RTC_DRV_DS1689 is not set
# CONFIG_RTC_DRV_DS17285 is not set
# CONFIG_RTC_DRV_DS17485 is not set
# CONFIG_RTC_DRV_DS17885 is not set
CONFIG_RTC_DRV_DS1742=m
CONFIG_RTC_DRV_DS2404=m
CONFIG_RTC_DRV_EFI=m
CONFIG_RTC_DRV_STK17TA8=m
CONFIG_RTC_DRV_M48T86=m
CONFIG_RTC_DRV_M48T35=m
CONFIG_RTC_DRV_M48T59=m
CONFIG_RTC_DRV_MSM6242=m
CONFIG_RTC_DRV_BQ4802=m
CONFIG_RTC_DRV_RP5C01=m
CONFIG_RTC_DRV_V3020=m
CONFIG_RTC_DRV_OPTEE=m
CONFIG_RTC_DRV_ZYNQMP=m

#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_PL030=m
CONFIG_RTC_DRV_PL031=m
CONFIG_RTC_DRV_CADENCE=m
CONFIG_RTC_DRV_FTRTC010=m
CONFIG_RTC_DRV_R7301=m

#
# HID Sensor RTC drivers
#
CONFIG_RTC_DRV_HID_SENSOR_TIME=m
CONFIG_RTC_DRV_GOLDFISH=m
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
CONFIG_AMBA_PL08X=y
# CONFIG_BCM_SBA_RAID is not set
CONFIG_DW_AXI_DMAC=m
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_MV_XOR_V2 is not set
CONFIG_PL330_DMA=y
# CONFIG_PLX_DMA is not set
CONFIG_ROCKCHIP_DMA=y
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
# CONFIG_XILINX_ZYNQMP_DPDMA is not set
# CONFIG_QCOM_HIDMA_MGMT is not set
# CONFIG_QCOM_HIDMA is not set
CONFIG_DW_DMAC_CORE=m
CONFIG_DW_DMAC=m
CONFIG_DW_DMAC_PCI=m
CONFIG_DW_EDMA=m
CONFIG_DW_EDMA_PCIE=m
# CONFIG_SF_PDMA is not set

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set

#
# DMABUF options
#
CONFIG_DMABUF_CACHE=y
# CONFIG_RK_DMABUF_DEBUG is not set
CONFIG_DMABUF_PARTIAL=y
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_SW_SYNC_DEBUG=y
# CONFIG_UDMABUF is not set
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_DEBUG is not set
# CONFIG_DMABUF_SELFTESTS is not set
CONFIG_DMABUF_HEAPS=y
CONFIG_DMABUF_SYSFS_STATS=y
CONFIG_DMABUF_HEAPS_SYSTEM=y
CONFIG_DMABUF_HEAPS_CMA=y
# CONFIG_DMABUF_HEAPS_SRAM is not set
CONFIG_DMABUF_HEAPS_ROCKCHIP=y
CONFIG_DMABUF_HEAPS_ROCKCHIP_CMA_HEAP=y
CONFIG_DMABUF_HEAPS_ROCKCHIP_CMA_ALIGNMENT=8
CONFIG_DMABUF_HEAPS_ROCKCHIP_SYSTEM_HEAP=y
# CONFIG_DMABUF_RK_HEAPS_DEBUG is not set
# CONFIG_DMABUF_RK_HEAPS_DEBUG_PRINT is not set
# end of DMABUF options

CONFIG_AUXDISPLAY=y
CONFIG_CHARLCD=m
CONFIG_LINEDISP=m
CONFIG_HD44780_COMMON=m
CONFIG_HD44780=m
CONFIG_IMG_ASCII_LCD=m
CONFIG_HT16K33=m
CONFIG_LCD2S=m
# CONFIG_PANEL_CHANGE_MESSAGE is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_UIO=m
# CONFIG_UIO_CIF is not set
# CONFIG_UIO_PDRV_GENIRQ is not set
# CONFIG_UIO_DMEM_GENIRQ is not set
# CONFIG_UIO_AEC is not set
# CONFIG_UIO_SERCOS3 is not set
# CONFIG_UIO_PCI_GENERIC is not set
# CONFIG_UIO_NETX is not set
# CONFIG_UIO_PRUSS is not set
# CONFIG_UIO_MF624 is not set
# CONFIG_VFIO is not set
CONFIG_VIRT_DRIVERS=y
CONFIG_VMGENID=y
# CONFIG_NITRO_ENCLAVES is not set
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_PCI_LIB=m
CONFIG_VIRTIO_PCI_LIB_LEGACY=m
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=m
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
# CONFIG_VDPA is not set
CONFIG_VHOST_IOTLB=m
CONFIG_VHOST=m
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_VSOCK=m
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set

#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
# CONFIG_COMEDI is not set
CONFIG_STAGING=y
CONFIG_PRISM2_USB=m
CONFIG_RTL8192U=m
CONFIG_RTLLIB=m
CONFIG_RTLLIB_CRYPTO_CCMP=m
CONFIG_RTLLIB_CRYPTO_TKIP=m
CONFIG_RTLLIB_CRYPTO_WEP=m
CONFIG_RTL8192E=m
CONFIG_RTL8723BS=m
CONFIG_R8712U=m
CONFIG_RTS5208=m
CONFIG_VT6655=m
CONFIG_VT6656=m

#
# IIO staging drivers
#

#
# Accelerometers
#
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16240 is not set
# end of Accelerometers

#
# Analog to digital converters
#
# CONFIG_AD7816 is not set
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
# CONFIG_ADT7316 is not set
# end of Analog digital bi-direction converters

#
# Direct Digital Synthesis
#
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
# CONFIG_AD5933 is not set
# end of Network Analyzer, Impedance Converters

#
# Active energy metering IC
#
# CONFIG_ADE7854 is not set
# end of Active energy metering IC

#
# Resolver to digital converters
#
# CONFIG_AD2S1210 is not set
# end of Resolver to digital converters
# end of IIO staging drivers

# CONFIG_FB_SM750 is not set
CONFIG_STAGING_MEDIA=y
CONFIG_VIDEO_ROCKCHIP_VDEC=y
# CONFIG_STAGING_MEDIA_DEPRECATED is not set
# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
CONFIG_FB_TFT=m
CONFIG_FB_TFT_AGM1264K_FL=m
CONFIG_FB_TFT_BD663474=m
CONFIG_FB_TFT_HX8340BN=m
CONFIG_FB_TFT_HX8347D=m
CONFIG_FB_TFT_HX8353D=m
CONFIG_FB_TFT_HX8357D=m
CONFIG_FB_TFT_ILI9163=m
CONFIG_FB_TFT_ILI9320=m
CONFIG_FB_TFT_ILI9325=m
CONFIG_FB_TFT_ILI9340=m
CONFIG_FB_TFT_ILI9341=m
CONFIG_FB_TFT_ILI9481=m
CONFIG_FB_TFT_ILI9486=m
CONFIG_FB_TFT_PCD8544=m
CONFIG_FB_TFT_RA8875=m
CONFIG_FB_TFT_S6D02A1=m
CONFIG_FB_TFT_S6D1121=m
CONFIG_FB_TFT_SEPS525=m
CONFIG_FB_TFT_SH1106=m
CONFIG_FB_TFT_SSD1289=m
CONFIG_FB_TFT_SSD1305=m
CONFIG_FB_TFT_SSD1306=m
CONFIG_FB_TFT_SSD1331=m
CONFIG_FB_TFT_SSD1351=m
CONFIG_FB_TFT_ST7735R=m
CONFIG_FB_TFT_ST7789V=m
CONFIG_FB_TFT_TINYLCD=m
CONFIG_FB_TFT_TLS8204=m
CONFIG_FB_TFT_UC1611=m
CONFIG_FB_TFT_UC1701=m
CONFIG_FB_TFT_UPD161704=m
# CONFIG_KS7010 is not set
# CONFIG_PI433 is not set
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_QLGE is not set
# CONFIG_VME_BUS is not set
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
# CONFIG_SURFACE_PLATFORMS is not set
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
# CONFIG_COMMON_CLK_PROCFS is not set

#
# Clock driver for ARM Reference designs
#
# CONFIG_CLK_ICST is not set
# CONFIG_CLK_SP810 is not set
# end of Clock driver for ARM Reference designs

# CONFIG_LMK04832 is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
# CONFIG_COMMON_CLK_SCPI is not set
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
# CONFIG_COMMON_CLK_XGENE is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_RS9_PCIE is not set
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_VC7 is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
CONFIG_COMMON_CLK_ROCKCHIP=y
CONFIG_CLK_PX30=y
CONFIG_CLK_RV1126B=y
CONFIG_CLK_RK1808=y
CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
CONFIG_CLK_RK3399=y
CONFIG_CLK_RK3506=y
CONFIG_CLK_RK3528=y
CONFIG_CLK_RK3562=y
CONFIG_CLK_RK3568=y
CONFIG_CLK_RK3576=y
CONFIG_CLK_RK3588=y
CONFIG_ROCKCHIP_CLK_COMPENSATION=y
CONFIG_ROCKCHIP_CLK_LINK=y
CONFIG_ROCKCHIP_CLK_BOOST=y
CONFIG_ROCKCHIP_CLK_INV=y
CONFIG_ROCKCHIP_CLK_OUT=y
CONFIG_ROCKCHIP_CLK_PVTM=y
CONFIG_ROCKCHIP_CLK_PVTPLL=y
CONFIG_ROCKCHIP_DDRCLK=y
CONFIG_ROCKCHIP_DDRCLK_SIP=y
CONFIG_ROCKCHIP_DDRCLK_SIP_V2=y
CONFIG_ROCKCHIP_PLL_RK3066=y
CONFIG_ROCKCHIP_PLL_RK3399=y
CONFIG_ROCKCHIP_PLL_RK3588=y
CONFIG_COMMON_CLK_ROCKCHIP_REGMAP=m
CONFIG_CLK_RK618=m
# CONFIG_XILINX_VCU is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_ROCKCHIP=y

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_ACPI=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
# CONFIG_ARM_TIMER_SP804 is not set
# CONFIG_MICROCHIP_PIT64B is not set
# end of Clock Source drivers

CONFIG_MAILBOX=y
CONFIG_MAILBOX_POLL_PERIOD_US=y
CONFIG_ARM_MHU=m
CONFIG_ARM_MHU_V2=m
CONFIG_PLATFORM_MHU=m
CONFIG_PL320_MBOX=y
CONFIG_ROCKCHIP_MBOX=y
CONFIG_ROCKCHIP_MBOX_DEMO=y
CONFIG_PCC=y
CONFIG_ALTERA_MBOX=m
CONFIG_MAILBOX_TEST=m
CONFIG_IOMMU_IOVA=y
CONFIG_IOASID=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_DART is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
CONFIG_IOMMU_SVA=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set
CONFIG_ARM_SMMU_V3=y
CONFIG_ARM_SMMU_V3_SVA=y
CONFIG_VIRTIO_IOMMU=m

#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=y
CONFIG_RPMSG_CHAR=m
CONFIG_RPMSG_CTRL=m
CONFIG_RPMSG_NS=m
CONFIG_RPMSG_QCOM_GLINK=m
CONFIG_RPMSG_QCOM_GLINK_RPM=m
CONFIG_RPMSG_ROCKCHIP_MBOX=y
CONFIG_RPMSG_ROCKCHIP_SOFTIRQ=y
CONFIG_RPMSG_ROCKCHIP_TEST=y
CONFIG_RPMSG_VIRTIO=m
# end of Rpmsg drivers

# CONFIG_SOUNDWIRE is not set

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
# end of Amlogic SoC drivers

#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
# CONFIG_QUICC_ENGINE is not set
# CONFIG_FSL_RCPM is not set
# end of NXP/Freescale QorIQ SoC drivers

#
# fujitsu SoC drivers
#
# CONFIG_A64FX_DIAG is not set
# end of fujitsu SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Enable LiteX SoC Builder specific drivers
#
# CONFIG_LITEX_SOC_CONTROLLER is not set
# end of Enable LiteX SoC Builder specific drivers

#
# Qualcomm SoC drivers
#
CONFIG_QCOM_QMI_HELPERS=m
# end of Qualcomm SoC drivers

#
# Rockchip SoC drivers
#

#
# Rockchip CPU selection
#
CONFIG_CPU_RV1126B=y
CONFIG_CPU_PX30=y
CONFIG_CPU_RK1808=y
CONFIG_CPU_RK3308=y
CONFIG_CPU_RK3328=y
CONFIG_CPU_RK3368=y
CONFIG_CPU_RK3399=y
CONFIG_CPU_RK3506=y
CONFIG_CPU_RK3528=y
CONFIG_CPU_RK3562=y
CONFIG_CPU_RK3568=y
CONFIG_CPU_RK3576=y
CONFIG_CPU_RK3588=y
# end of Rockchip CPU selection

CONFIG_NO_GKI=y
# CONFIG_ROCKCHIP_DISABLE_UNUSED is not set
CONFIG_ROCKCHIP_AMP=y
# CONFIG_ROCKCHIP_ARM64_ALIGN_FAULT_FIX is not set
CONFIG_ROCKCHIP_CPUINFO=y
CONFIG_ROCKCHIP_CSU=y
# CONFIG_ROCKCHIP_DMC_DEBUG is not set
CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
# CONFIG_ROCKCHIP_HW_DECOMPRESS_TEST is not set
CONFIG_ROCKCHIP_HW_DECOMPRESS_USER=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_IOMUX=y
CONFIG_ROCKCHIP_IPA=y
CONFIG_ROCKCHIP_OPP=y
# CONFIG_ROCKCHIP_OPTIMIZE_RT_PRIO is not set
CONFIG_ROCKCHIP_PERFORMANCE=y
CONFIG_ROCKCHIP_PERFORMANCE_LEVEL=2
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ROCKCHIP_PVTM=y
CONFIG_ROCKCHIP_RAMDISK=y
# CONFIG_ROCKCHIP_LITE_ULTRA_SUSPEND is not set
CONFIG_ROCKCHIP_SUSPEND_MODE=y
# CONFIG_ROCKCHIP_SUSPEND_DEBUG is not set
CONFIG_ROCKCHIP_SYSTEM_MONITOR=y
CONFIG_ROCKCHIP_VENDOR_STORAGE=y
CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE=y
# CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE is not set
# CONFIG_ROCKCHIP_RAM_VENDOR_STORAGE is not set
CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER=y

#
# FIQ Debugger
#
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
# CONFIG_FIQ_DEBUGGER_WAKEUP_IRQ_ALWAYS_ON is not set
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y
# CONFIG_FIQ_DEBUGGER_UART_OVERLAY is not set
CONFIG_RK_CONSOLE_THREAD=y
CONFIG_ROCKCHIP_FIQ_DEBUGGER=y
# end of FIQ Debugger

CONFIG_ROCKCHIP_DEBUG=y
# CONFIG_ROCKCHIP_MINI_KERNEL is not set
# CONFIG_ROCKCHIP_THUNDER_BOOT is not set
CONFIG_ROCKCHIP_NPOR_POWERGOOD=y
# CONFIG_RK_CMA_PROCFS is not set
# CONFIG_RK_DMABUF_PROCFS is not set
CONFIG_RK_MEMBLOCK_PROCFS=y
# CONFIG_RK_ZONEINFO_PROCFS is not set
CONFIG_ROCKCHIP_AOA_MIDDLEWARE=m

#
# Rockchip Minidump drivers
#
# CONFIG_ROCKCHIP_MINIDUMP is not set
# end of Rockchip Minidump drivers
# end of Rockchip SoC drivers

# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEVFREQ_GOV_PASSIVE=y

#
# DEVFREQ Drivers
#
CONFIG_ARM_ROCKCHIP_BUS_DEVFREQ=y
CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_NOCP=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
CONFIG_EXTCON_ADC_JACK=m
# CONFIG_EXTCON_FSA9480 is not set
CONFIG_EXTCON_GPIO=m
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_PTN5150 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
# CONFIG_EXTCON_USB_GPIO is not set
# CONFIG_EXTCON_USBC_TUSB320 is not set
CONFIG_EXTCON_USBC_VIRTUAL_PD=y
# CONFIG_MEMORY is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
CONFIG_IIO_BUFFER_DMA=m
CONFIG_IIO_BUFFER_DMAENGINE=m
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
CONFIG_IIO_TRIGGERED_EVENT=m

#
# Accelerometers
#
CONFIG_ADIS16201=m
CONFIG_ADIS16209=m
CONFIG_ADXL313=m
CONFIG_ADXL313_I2C=m
CONFIG_ADXL313_SPI=m
CONFIG_ADXL355=m
CONFIG_ADXL355_I2C=m
CONFIG_ADXL355_SPI=m
CONFIG_ADXL367=m
CONFIG_ADXL367_SPI=m
CONFIG_ADXL367_I2C=m
CONFIG_ADXL372=m
CONFIG_ADXL372_SPI=m
CONFIG_ADXL372_I2C=m
CONFIG_BMA220=m
CONFIG_BMA400=m
CONFIG_BMA400_I2C=m
CONFIG_BMA400_SPI=m
CONFIG_BMC150_ACCEL=m
CONFIG_BMC150_ACCEL_I2C=m
CONFIG_BMC150_ACCEL_SPI=m
CONFIG_BMI088_ACCEL=m
CONFIG_BMI088_ACCEL_SPI=m
CONFIG_DA280=m
CONFIG_DA311=m
CONFIG_DMARD06=m
CONFIG_DMARD09=m
CONFIG_DMARD10=m
CONFIG_FXLS8962AF=m
CONFIG_FXLS8962AF_I2C=m
CONFIG_FXLS8962AF_SPI=m
CONFIG_HID_SENSOR_ACCEL_3D=m
CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
CONFIG_KXSD9=m
CONFIG_KXSD9_SPI=m
CONFIG_KXSD9_I2C=m
CONFIG_KXCJK1013=m
CONFIG_MC3230=m
CONFIG_MMA7455=m
CONFIG_MMA7455_I2C=m
CONFIG_MMA7455_SPI=m
CONFIG_MMA7660=m
CONFIG_MMA8452=m
CONFIG_MMA9551_CORE=m
CONFIG_MMA9551=m
CONFIG_MMA9553=m
CONFIG_MSA311=m
CONFIG_MXC4005=m
CONFIG_MXC6255=m
CONFIG_SCA3000=m
CONFIG_SCA3300=m
CONFIG_STK8312=m
CONFIG_STK8BA50=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=m
CONFIG_AD7091R5=m
CONFIG_AD7124=m
CONFIG_AD7192=m
CONFIG_AD7266=m
CONFIG_AD7280=m
CONFIG_AD7291=m
CONFIG_AD7292=m
CONFIG_AD7298=m
CONFIG_AD7476=m
CONFIG_AD7606=m
CONFIG_AD7606_IFACE_PARALLEL=m
CONFIG_AD7606_IFACE_SPI=m
CONFIG_AD7766=m
CONFIG_AD7768_1=m
CONFIG_AD7780=m
CONFIG_AD7791=m
CONFIG_AD7793=m
CONFIG_AD7887=m
CONFIG_AD7923=m
CONFIG_AD7949=m
CONFIG_AD799X=m
CONFIG_AD9467=m
CONFIG_ADI_AXI_ADC=m
CONFIG_CC10001_ADC=m
CONFIG_ENVELOPE_DETECTOR=m
CONFIG_HI8435=m
CONFIG_HX711=m
CONFIG_INA2XX_ADC=m
CONFIG_LTC2471=m
CONFIG_LTC2485=m
CONFIG_LTC2496=m
CONFIG_LTC2497=m
CONFIG_MAX1027=m
CONFIG_MAX11100=m
CONFIG_MAX1118=m
CONFIG_MAX11205=m
CONFIG_MAX1241=m
CONFIG_MAX1363=m
CONFIG_MAX9611=m
CONFIG_MCP320X=m
CONFIG_MCP3422=m
CONFIG_MCP3911=m
CONFIG_NAU7802=m
CONFIG_ROCKCHIP_FLEXBUS_ADC=m
CONFIG_ROCKCHIP_SARADC=y
CONFIG_ROCKCHIP_SARADC_TEST_CHN=y
CONFIG_RICHTEK_RTQ6056=m
CONFIG_SD_ADC_MODULATOR=m
CONFIG_TI_ADC081C=m
CONFIG_TI_ADC0832=m
CONFIG_TI_ADC084S021=m
CONFIG_TI_ADC12138=m
CONFIG_TI_ADC108S102=m
CONFIG_TI_ADC128S052=m
CONFIG_TI_ADC161S626=m
CONFIG_TI_ADS1015=m
CONFIG_TI_ADS7950=m
CONFIG_TI_ADS8344=m
CONFIG_TI_ADS8688=m
CONFIG_TI_ADS124S08=m
CONFIG_TI_ADS131E08=m
CONFIG_TI_TLC4541=m
CONFIG_TI_TSC2046=m
CONFIG_VF610_ADC=m
CONFIG_XILINX_XADC=m
# end of Analog to digital converters

#
# Analog to digital and digital to analog converters
#
CONFIG_AD74413R=m
# end of Analog to digital and digital to analog converters

#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=m
# end of Analog Front Ends

#
# Amplifiers
#
CONFIG_AD8366=m
CONFIG_ADA4250=m
CONFIG_HMC425=m
# end of Amplifiers

#
# Capacitance to digital converters
#
CONFIG_AD7150=m
CONFIG_AD7746=m
# end of Capacitance to digital converters

#
# Chemical Sensors
#
CONFIG_ATLAS_PH_SENSOR=m
CONFIG_ATLAS_EZO_SENSOR=m
CONFIG_BME680=m
CONFIG_BME680_I2C=m
CONFIG_BME680_SPI=m
CONFIG_CCS811=m
CONFIG_IAQCORE=m
# CONFIG_PMS7003 is not set
CONFIG_SCD30_CORE=m
CONFIG_SCD30_I2C=m
# CONFIG_SCD30_SERIAL is not set
CONFIG_SCD4X=m
CONFIG_SENSIRION_SGP30=m
CONFIG_SENSIRION_SGP40=m
CONFIG_SPS30=m
CONFIG_SPS30_I2C=m
# CONFIG_SPS30_SERIAL is not set
CONFIG_SENSEAIR_SUNRISE_CO2=m
CONFIG_VZ89X=m
# end of Chemical Sensors

#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
# end of Hid Sensor IIO Common

CONFIG_IIO_MS_SENSORS_I2C=m

#
# IIO SCMI Sensors
#
CONFIG_IIO_SCMI=m
# end of IIO SCMI Sensors

#
# SSP Sensor Common
#
CONFIG_IIO_SSP_SENSORS_COMMONS=m
CONFIG_IIO_SSP_SENSORHUB=m
# end of SSP Sensor Common

CONFIG_IIO_ST_SENSORS_I2C=m
CONFIG_IIO_ST_SENSORS_SPI=m
CONFIG_IIO_ST_SENSORS_CORE=m

#
# Digital to analog converters
#
# CONFIG_AD3552R is not set
CONFIG_AD5064=m
CONFIG_AD5360=m
CONFIG_AD5380=m
CONFIG_AD5421=m
CONFIG_AD5446=m
CONFIG_AD5449=m
CONFIG_AD5592R_BASE=m
CONFIG_AD5592R=m
CONFIG_AD5593R=m
CONFIG_AD5504=m
CONFIG_AD5624R_SPI=m
CONFIG_LTC2688=m
CONFIG_AD5686=m
CONFIG_AD5686_SPI=m
CONFIG_AD5696_I2C=m
CONFIG_AD5755=m
CONFIG_AD5758=m
CONFIG_AD5761=m
CONFIG_AD5764=m
CONFIG_AD5766=m
CONFIG_AD5770R=m
CONFIG_AD5791=m
CONFIG_AD7293=m
CONFIG_AD7303=m
CONFIG_AD8801=m
CONFIG_DPOT_DAC=m
CONFIG_DS4424=m
CONFIG_LTC1660=m
CONFIG_LTC2632=m
CONFIG_M62332=m
CONFIG_MAX517=m
CONFIG_MAX5821=m
CONFIG_MCP4725=m
CONFIG_MCP4922=m
CONFIG_ROCKCHIP_FLEXBUS_DAC=m
CONFIG_TI_DAC082S085=m
CONFIG_TI_DAC5571=m
CONFIG_TI_DAC7311=m
CONFIG_TI_DAC7612=m
CONFIG_VF610_DAC=m
# end of Digital to analog converters

#
# IIO dummy driver
#
CONFIG_IIO_DUMMY_EVGEN=m
CONFIG_IIO_SIMPLE_DUMMY=m
CONFIG_IIO_SIMPLE_DUMMY_EVENTS=y
CONFIG_IIO_SIMPLE_DUMMY_BUFFER=y
# end of IIO dummy driver

#
# Filters
#
CONFIG_ADMV8818=m
# end of Filters

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
CONFIG_AD9523=m
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4350=m
CONFIG_ADF4371=m
CONFIG_ADMV1013=m
CONFIG_ADMV1014=m
CONFIG_ADMV4420=m
CONFIG_ADRF6780=m
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=m
CONFIG_ADIS16130=m
CONFIG_ADIS16136=m
CONFIG_ADIS16260=m
CONFIG_ADXRS290=m
CONFIG_ADXRS450=m
CONFIG_BMG160=m
CONFIG_BMG160_I2C=m
CONFIG_BMG160_SPI=m
CONFIG_FXAS21002C=m
CONFIG_FXAS21002C_I2C=m
CONFIG_FXAS21002C_SPI=m
CONFIG_HID_SENSOR_GYRO_3D=m
CONFIG_MPU3050=m
CONFIG_MPU3050_I2C=m
CONFIG_IIO_ST_GYRO_3AXIS=m
CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
CONFIG_ITG3200=m
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
CONFIG_AFE4403=m
CONFIG_AFE4404=m
CONFIG_MAX30100=m
CONFIG_MAX30102=m
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
CONFIG_AM2315=m
CONFIG_DHT11=m
CONFIG_HDC100X=m
CONFIG_HDC2010=m
CONFIG_HID_SENSOR_HUMIDITY=m
CONFIG_HTS221=m
CONFIG_HTS221_I2C=m
CONFIG_HTS221_SPI=m
CONFIG_HTU21=m
CONFIG_SI7005=m
CONFIG_SI7020=m
# end of Humidity sensors

#
# Inertial measurement units
#
CONFIG_ADIS16400=m
CONFIG_ADIS16460=m
CONFIG_ADIS16475=m
CONFIG_ADIS16480=m
CONFIG_BMI160=m
CONFIG_BMI160_I2C=m
CONFIG_BMI160_SPI=m
CONFIG_BOSCH_BNO055=m
# CONFIG_BOSCH_BNO055_SERIAL is not set
CONFIG_BOSCH_BNO055_I2C=m
CONFIG_FXOS8700=m
CONFIG_FXOS8700_I2C=m
CONFIG_FXOS8700_SPI=m
CONFIG_KMX61=m
CONFIG_INV_ICM42600=m
CONFIG_INV_ICM42600_I2C=m
CONFIG_INV_ICM42600_SPI=m
# CONFIG_IIO_INV_ICM42607 is not set
CONFIG_INV_ICM42670=m
CONFIG_INV_ICM42670_I2C=m
CONFIG_INV_ICM42670_SPI=m
CONFIG_INV_MPU6050_IIO=m
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_SPI=m
CONFIG_IIO_ST_LSM6DSR=m
CONFIG_IIO_ST_LSM6DSR_I2C=m
CONFIG_IIO_ST_LSM6DSR_SPI=m
CONFIG_IIO_ST_LSM6DSR_MAY_WAKEUP=y
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_LSM6DSX_I2C=m
CONFIG_IIO_ST_LSM6DSX_SPI=m
CONFIG_IIO_ST_LSM9DS0=m
CONFIG_IIO_ST_LSM9DS0_I2C=m
CONFIG_IIO_ST_LSM9DS0_SPI=m
# end of Inertial measurement units

CONFIG_IIO_ADIS_LIB=m
CONFIG_IIO_ADIS_LIB_BUFFER=y

#
# Light sensors
#
CONFIG_ACPI_ALS=m
CONFIG_ADJD_S311=m
CONFIG_ADUX1020=m
CONFIG_AL3010=m
CONFIG_AL3320A=m
CONFIG_APDS9300=m
CONFIG_APDS9960=m
CONFIG_AS73211=m
CONFIG_BH1750=m
CONFIG_BH1780=m
CONFIG_CM32181=m
CONFIG_CM3232=m
CONFIG_CM3323=m
CONFIG_CM3605=m
CONFIG_CM36651=m
CONFIG_GP2AP002=m
CONFIG_GP2AP020A00F=m
CONFIG_SENSORS_ISL29018=m
CONFIG_SENSORS_ISL29028=m
CONFIG_ISL29125=m
CONFIG_HID_SENSOR_ALS=m
CONFIG_HID_SENSOR_PROX=m
CONFIG_JSA1212=m
CONFIG_RPR0521=m
CONFIG_LTR501=m
CONFIG_LTRF216A=m
CONFIG_LV0104CS=m
CONFIG_MAX44000=m
CONFIG_MAX44009=m
CONFIG_NOA1305=m
CONFIG_OPT3001=m
CONFIG_PA12203001=m
CONFIG_SI1133=m
CONFIG_SI1145=m
CONFIG_STK3310=m
CONFIG_ST_UVIS25=m
CONFIG_ST_UVIS25_I2C=m
CONFIG_ST_UVIS25_SPI=m
CONFIG_TCS3414=m
CONFIG_TCS3472=m
CONFIG_SENSORS_TSL2563=m
CONFIG_TSL2583=m
CONFIG_TSL2591=m
CONFIG_TSL2772=m
CONFIG_TSL4531=m
CONFIG_UCS12CM0=m
CONFIG_US5182D=m
CONFIG_VCNL4000=m
CONFIG_VCNL4035=m
CONFIG_VEML6030=m
CONFIG_VEML6070=m
CONFIG_VL6180=m
CONFIG_ZOPT2201=m
# end of Light sensors

#
# Magnetometer sensors
#
CONFIG_AK8974=m
CONFIG_AK8975=m
CONFIG_AK09911=m
CONFIG_BMC150_MAGN=m
CONFIG_BMC150_MAGN_I2C=m
CONFIG_BMC150_MAGN_SPI=m
CONFIG_MAG3110=m
CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
CONFIG_MMC35240=m
CONFIG_IIO_ST_MAGN_3AXIS=m
CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
CONFIG_SENSORS_HMC5843=m
CONFIG_SENSORS_HMC5843_I2C=m
CONFIG_SENSORS_HMC5843_SPI=m
CONFIG_SENSORS_RM3100=m
CONFIG_SENSORS_RM3100_I2C=m
CONFIG_SENSORS_RM3100_SPI=m
CONFIG_YAMAHA_YAS530=m
# end of Magnetometer sensors

#
# Multiplexers
#
CONFIG_IIO_MUX=m
# end of Multiplexers

#
# Inclinometer sensors
#
CONFIG_HID_SENSOR_INCLINOMETER_3D=m
CONFIG_HID_SENSOR_DEVICE_ROTATION=m
# end of Inclinometer sensors

#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=m
CONFIG_IIO_INTERRUPT_TRIGGER=m
CONFIG_IIO_TIGHTLOOP_TRIGGER=m
CONFIG_IIO_SYSFS_TRIGGER=m
# end of Triggers - standalone

#
# Linear and angular position sensors
#
CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
# end of Linear and angular position sensors

#
# Digital potentiometers
#
CONFIG_AD5110=m
CONFIG_AD5272=m
CONFIG_DS1803=m
CONFIG_MAX5432=m
CONFIG_MAX5481=m
CONFIG_MAX5487=m
CONFIG_MCP4018=m
CONFIG_MCP4131=m
CONFIG_MCP4531=m
CONFIG_MCP41010=m
CONFIG_TPL0102=m
# end of Digital potentiometers

#
# Digital potentiostats
#
CONFIG_LMP91000=m
# end of Digital potentiostats

#
# Pressure sensors
#
CONFIG_ABP060MG=m
CONFIG_BMP280=m
CONFIG_BMP280_I2C=m
CONFIG_BMP280_SPI=m
CONFIG_DLHL60D=m
CONFIG_DPS310=m
CONFIG_HID_SENSOR_PRESS=m
CONFIG_HP03=m
CONFIG_ICP10100=m
CONFIG_MPL115=m
CONFIG_MPL115_I2C=m
CONFIG_MPL115_SPI=m
CONFIG_MPL3115=m
CONFIG_MS5611=m
CONFIG_MS5611_I2C=m
CONFIG_MS5611_SPI=m
CONFIG_MS5637=m
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_PRESS_I2C=m
CONFIG_IIO_ST_PRESS_SPI=m
CONFIG_T5403=m
CONFIG_HP206C=m
CONFIG_ZPA2326=m
CONFIG_ZPA2326_I2C=m
CONFIG_ZPA2326_SPI=m
# end of Pressure sensors

#
# Lightning sensors
#
CONFIG_AS3935=m
# end of Lightning sensors

#
# Proximity and distance sensors
#
# CONFIG_DTOF_NDS03 is not set
CONFIG_ISL29501=m
CONFIG_LIDAR_LITE_V2=m
CONFIG_MB1232=m
CONFIG_PING=m
CONFIG_RFD77402=m
CONFIG_SRF04=m
CONFIG_SX_COMMON=m
CONFIG_SX9310=m
CONFIG_SX9324=m
CONFIG_SX9360=m
CONFIG_SX9500=m
CONFIG_SRF08=m
CONFIG_VCNL3020=m
CONFIG_VL53L0X_I2C=m
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
CONFIG_AD2S90=m
CONFIG_AD2S1200=m
# end of Resolver to digital converters

#
# Temperature sensors
#
CONFIG_LTC2983=m
CONFIG_MAXIM_THERMOCOUPLE=m
CONFIG_HID_SENSOR_TEMP=m
CONFIG_MLX90614=m
CONFIG_MLX90632=m
CONFIG_TMP006=m
CONFIG_TMP007=m
CONFIG_TMP117=m
CONFIG_TSYS01=m
CONFIG_TSYS02D=m
CONFIG_MAX31856=m
CONFIG_MAX31865=m
# end of Temperature sensors

# CONFIG_NTB is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_ATMEL_TCB is not set
# CONFIG_PWM_CLK is not set
# CONFIG_PWM_DWC is not set
# CONFIG_PWM_FSL_FTM is not set
CONFIG_PWM_GPIO=m
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_ROCKCHIP=y
# CONFIG_PWM_ROCKCHIP_ONESHOT is not set
# CONFIG_PWM_ROCKCHIP_TEST is not set
# CONFIG_PWM_R7F701 is not set
# CONFIG_PWM_XILINX is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_AL_FIC is not set
# CONFIG_XILINX_INTC is not set
CONFIG_PARTITION_PERCPU=y
# end of IRQ chip support

# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_SCMI=y
# CONFIG_RESET_SIMPLE is not set
# CONFIG_RESET_TI_SYSCON is not set
# CONFIG_RESET_TI_TPS380X is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_PHY_XGENE is not set
# CONFIG_PHY_CAN_TRANSCEIVER is not set

#
# PHY drivers for Broadcom platforms
#
# CONFIG_BCM_KONA_USB2_PHY is not set
# end of PHY drivers for Broadcom platforms

# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_DPHY_RX is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_LAN966X_SERDES is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
# CONFIG_PHY_QCOM_USB_HS is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y
CONFIG_PHY_ROCKCHIP_DP=y
CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_USB3=y
CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
CONFIG_PHY_ROCKCHIP_MIPI_RX=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
CONFIG_PHY_ROCKCHIP_NANENG_EDP=y
CONFIG_PHY_ROCKCHIP_NANENG_USB2=y
CONFIG_PHY_ROCKCHIP_PCIE=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PHY_ROCKCHIP_USB=y
CONFIG_PHY_ROCKCHIP_USBDP=y
# CONFIG_PHY_SAMSUNG_USB2 is not set
# CONFIG_PHY_TUSB1210 is not set
# end of PHY Subsystem

# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCI400_PMU=y
CONFIG_ARM_CCI5xx_PMU=y
CONFIG_ARM_CCN=m
CONFIG_ARM_CMN=m
CONFIG_ARM_PMU=y
CONFIG_ARM_PMU_ACPI=y
CONFIG_ARM_SMMU_V3_PMU=m
CONFIG_ARM_DSU_PMU=m
CONFIG_ARM_SPE_PMU=m
# CONFIG_ARM_DMC620_PMU is not set
# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set
# CONFIG_HISI_PMU is not set
# CONFIG_HISI_PCIE_PMU is not set
# CONFIG_HNS3_PMU is not set
# CONFIG_DWC_PCIE_PMU is not set
# end of Performance monitor support

# CONFIG_RAS is not set
# CONFIG_USB4 is not set

#
# Android
#
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_BINDERFS=y
CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder,anbox-binder,anbox-hwbinder,anbox-vndbinder"
# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
# end of Android

# CONFIG_LIBNVDIMM is not set
CONFIG_DAX=y
CONFIG_DEV_DAX=y
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
# CONFIG_NVMEM_RMEM is not set
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
CONFIG_NVMEM_ROCKCHIP_OTP=y
CONFIG_NVMEM_ROCKCHIP_SEC_OTP=y
CONFIG_NVMEM_U_BOOT_ENV=y

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# CONFIG_HISI_PTT is not set
# end of HW tracing support

# CONFIG_FPGA is not set
# CONFIG_FSI is not set
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_MULTIPLEXER=m

#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
# CONFIG_MUX_ADGS1408 is not set
# CONFIG_MUX_GPIO is not set
# CONFIG_MUX_MMIO is not set
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set
# CONFIG_INTERCONNECT is not set
# CONFIG_COUNTER is not set
# CONFIG_MOST is not set
# CONFIG_PECI is not set
# CONFIG_HTE is not set
# CONFIG_RK_FLASH is not set
# CONFIG_RK_NAND is not set

#
# Headset device support
#
CONFIG_RK_HEADSET=y
# end of Headset device support

#
# RKNPU
#
CONFIG_ROCKCHIP_RKNPU=y
CONFIG_ROCKCHIP_RKNPU_DEBUG_FS=y
CONFIG_ROCKCHIP_RKNPU_PROC_FS=y
CONFIG_ROCKCHIP_RKNPU_FENCE=y
CONFIG_ROCKCHIP_RKNPU_SRAM=y
# CONFIG_ROCKCHIP_RKNPU_DRM_GEM is not set
CONFIG_ROCKCHIP_RKNPU_DMA_HEAP=y
# end of RKNPU
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
# CONFIG_VALIDATE_FS_PARSER is not set
CONFIG_FS_IOMAP=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=m
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
# CONFIG_REISERFS_FS_XATTR is not set
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
# CONFIG_JFS_DEBUG is not set
# CONFIG_JFS_STATISTICS is not set
CONFIG_XFS_FS=y
# CONFIG_XFS_SUPPORT_V4 is not set
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
# CONFIG_XFS_RT is not set
# CONFIG_XFS_ONLINE_SCRUB is not set
# CONFIG_XFS_WARN is not set
# CONFIG_XFS_DEBUG is not set
CONFIG_GFS2_FS=m
# CONFIG_GFS2_FS_LOCKING_DLM is not set
CONFIG_OCFS2_FS=m
CONFIG_OCFS2_FS_O2CB=m
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
CONFIG_OCFS2_FS_STATS=y
CONFIG_OCFS2_DEBUG_MASKLOG=y
# CONFIG_OCFS2_DEBUG_FS is not set
CONFIG_BTRFS_FS=y
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
# CONFIG_BTRFS_FS_REF_VERIFY is not set
# CONFIG_NILFS2_FS is not set
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
# CONFIG_F2FS_FAULT_INJECTION is not set
CONFIG_F2FS_FS_COMPRESSION=y
CONFIG_F2FS_FS_LZO=y
CONFIG_F2FS_FS_LZORLE=y
CONFIG_F2FS_FS_LZ4=y
CONFIG_F2FS_FS_LZ4HC=y
CONFIG_F2FS_FS_ZSTD=y
CONFIG_F2FS_IOSTAT=y
# CONFIG_F2FS_UNFAIR_RWSEM is not set
# CONFIG_ZONEFS_FS is not set
# CONFIG_FS_DAX is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_PRINT_QUOTA_WARNING is not set
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
# CONFIG_AUTOFS4_FS is not set
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=m
CONFIG_CUSE=m
CONFIG_VIRTIO_FS=m
CONFIG_OVERLAY_FS=m
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set

#
# Caches
#
CONFIG_NETFS_SUPPORT=m
# CONFIG_NETFS_STATS is not set
CONFIG_FSCACHE=m
# CONFIG_FSCACHE_STATS is not set
# CONFIG_FSCACHE_DEBUG is not set
CONFIG_CACHEFILES=m
# CONFIG_CACHEFILES_DEBUG is not set
# CONFIG_CACHEFILES_ERROR_INJECTION is not set
# CONFIG_CACHEFILES_ONDEMAND is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=936
CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_EXFAT_FS=y
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_NTFS_FS is not set
CONFIG_NTFS3_FS=m
CONFIG_NTFS3_64BIT_CLUSTER=y
CONFIG_NTFS3_LZX_XPRESS=y
CONFIG_NTFS3_FS_POSIX_ACL=y
# end of DOS/FAT/EXFAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_TMPFS_INODE64 is not set
CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
# CONFIG_HUGETLBFS is not set
CONFIG_MEMFD_CREATE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=y
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
CONFIG_ECRYPT_FS=m
# CONFIG_ECRYPT_FS_MESSAGING is not set
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
CONFIG_JFFS2_SUMMARY=y
# CONFIG_JFFS2_FS_XATTR is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
CONFIG_UBIFS_FS=m
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
# CONFIG_CRAMFS is not set
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_FILE_CACHE=y
# CONFIG_SQUASHFS_FILE_DIRECT is not set
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_ZSTD=y
CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
# CONFIG_SQUASHFS_EMBEDDED is not set
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
CONFIG_PSTORE_DEFLATE_COMPRESS=y
CONFIG_PSTORE_LZO_COMPRESS=y
CONFIG_PSTORE_LZ4_COMPRESS=y
CONFIG_PSTORE_LZ4HC_COMPRESS=y
CONFIG_PSTORE_842_COMPRESS=y
CONFIG_PSTORE_ZSTD_COMPRESS=y
CONFIG_PSTORE_COMPRESS=y
# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT=y
CONFIG_PSTORE_COMPRESS_DEFAULT="zstd"
CONFIG_PSTORE_CONSOLE=y
# CONFIG_PSTORE_PMSG is not set
CONFIG_PSTORE_RAM=y
# CONFIG_PSTORE_BLK is not set
# CONFIG_PSTORE_BOOT_LOG is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_EROFS_FS=m
# CONFIG_EROFS_FS_DEBUG is not set
CONFIG_EROFS_FS_XATTR=y
CONFIG_EROFS_FS_POSIX_ACL=y
CONFIG_EROFS_FS_SECURITY=y
CONFIG_EROFS_FS_ZIP=y
# CONFIG_EROFS_FS_ZIP_LZMA is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V2=m
CONFIG_NFS_V3=m
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=m
CONFIG_NFS_SWAP=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=m
CONFIG_PNFS_BLOCK=m
CONFIG_PNFS_FLEXFILE_LAYOUT=m
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
CONFIG_NFS_V4_1_MIGRATION=y
CONFIG_NFS_V4_SECURITY_LABEL=y
CONFIG_NFS_FSCACHE=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
CONFIG_NFS_V4_2_READ_PLUS=y
CONFIG_NFSD=m
# CONFIG_NFSD_V2 is not set
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
CONFIG_NFSD_PNFS=y
CONFIG_NFSD_BLOCKLAYOUT=y
CONFIG_NFSD_SCSILAYOUT=y
CONFIG_NFSD_FLEXFILELAYOUT=y
CONFIG_NFSD_V4_2_INTER_SSC=y
# CONFIG_NFSD_V4_SECURITY_LABEL is not set
CONFIG_GRACE_PERIOD=m
CONFIG_LOCKD=m
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=m
CONFIG_NFS_COMMON=y
CONFIG_NFS_V4_2_SSC_HELPER=y
CONFIG_SUNRPC=m
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_BACKCHANNEL=y
CONFIG_SUNRPC_SWAP=y
CONFIG_RPCSEC_GSS_KRB5=m
# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
# CONFIG_SUNRPC_DEBUG is not set
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
# CONFIG_CEPH_FS_SECURITY_LABEL is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
# CONFIG_CIFS_DEBUG is not set
CONFIG_CIFS_DFS_UPCALL=y
# CONFIG_CIFS_SWN_UPCALL is not set
# CONFIG_CIFS_FSCACHE is not set
# CONFIG_SMB_SERVER is not set
CONFIG_SMBFS=m
CONFIG_CODA_FS=m
CONFIG_AFS_FS=m
# CONFIG_AFS_DEBUG is not set
# CONFIG_AFS_FSCACHE is not set
# CONFIG_AFS_DEBUG_CURSOR is not set
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
# CONFIG_9P_FS_SECURITY is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=m
CONFIG_NLS_MAC_GAELIC=m
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=y
CONFIG_DLM=m
# CONFIG_DLM_DEPRECATED_API is not set
# CONFIG_DLM_DEBUG is not set
CONFIG_UNICODE=y
# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_TRUSTED_KEYS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_PROC_MEM_ALWAYS_FORCE=y
# CONFIG_PROC_MEM_FORCE_PTRACE is not set
# CONFIG_PROC_MEM_NO_FORCE is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
# CONFIG_SECURITY_NETWORK_XFRM is not set
CONFIG_SECURITY_PATH=y
CONFIG_LSM_MMAP_MIN_ADDR=32768
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_SECURITY_SELINUX=y
# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set
# CONFIG_SECURITY_SELINUX_DISABLE is not set
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
CONFIG_SECURITY_APPARMOR=y
# CONFIG_SECURITY_APPARMOR_DEBUG is not set
CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y
CONFIG_SECURITY_APPARMOR_HASH=y
CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y
CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
# CONFIG_SECURITY_LANDLOCK is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
CONFIG_INTEGRITY_AUDIT=y
# CONFIG_IMA is not set
# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
# CONFIG_EVM is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor "

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
CONFIG_INIT_STACK_NONE=y
# CONFIG_INIT_STACK_ALL_PATTERN is not set
# CONFIG_INIT_STACK_ALL_ZERO is not set
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
# CONFIG_ZERO_CALL_USED_REGS is not set
# end of Memory initialization

CONFIG_RANDSTRUCT_NONE=y
# CONFIG_RANDSTRUCT_FULL is not set
# CONFIG_RANDSTRUCT_PERFORMANCE is not set
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=y
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
# CONFIG_CRYPTO_USER is not set
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_CRYPTD=m
CONFIG_CRYPTO_AUTHENC=m
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_ENGINE=m
# end of Crypto core or helper

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
CONFIG_CRYPTO_ECC=m
CONFIG_CRYPTO_ECDH=m
CONFIG_CRYPTO_ECDSA=m
CONFIG_CRYPTO_ECRDSA=m
CONFIG_CRYPTO_SM2=y
CONFIG_CRYPTO_CURVE25519=y
# end of Public-key cryptography

#
# Block ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_ARIA=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_BLOWFISH_COMMON=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST_COMMON=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_GENERIC=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y
# end of Block ciphers

#
# Length-preserving ciphers and modes
#
CONFIG_CRYPTO_ADIANTUM=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HCTR2=m
CONFIG_CRYPTO_KEYWRAP=m
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XCTR=m
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_NHPOLY1305=y
# end of Length-preserving ciphers and modes

#
# AEAD (authenticated encryption with associated data) ciphers
#
CONFIG_CRYPTO_AEGIS128=y
CONFIG_CRYPTO_AEGIS128_SIMD=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_SEQIV=m
CONFIG_CRYPTO_ECHAINIV=m
CONFIG_CRYPTO_ESSIV=m
# end of AEAD (authenticated encryption with associated data) ciphers

#
# Hashes, digests, and MACs
#
CONFIG_CRYPTO_BLAKE2B=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_POLYVAL=m
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_SM3_GENERIC=y
CONFIG_CRYPTO_STREEBOG=m
CONFIG_CRYPTO_VMAC=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_XXHASH=y
# end of Hashes, digests, and MACs

#
# CRCs (cyclic redundancy checks)
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
# end of CRCs (cyclic redundancy checks)

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=y
CONFIG_CRYPTO_ZSTD=y
# end of Compression

#
# Random number generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
# CONFIG_CRYPTO_DRBG_HASH is not set
# CONFIG_CRYPTO_DRBG_CTR is not set
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
# end of Random number generation

#
# Userspace interface
#
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=m
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
# end of Userspace interface

CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_NHPOLY1305_NEON=y
CONFIG_CRYPTO_CHACHA20_NEON=y

#
# Accelerated Cryptographic Algorithms for CPU (arm64)
#
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_POLY1305_NEON=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA512_ARM64_CE=y
CONFIG_CRYPTO_SHA3_ARM64=y
# CONFIG_CRYPTO_SM3_NEON is not set
CONFIG_CRYPTO_SM3_ARM64_CE=y
# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CRYPTO_SM4_ARM64_CE=y
# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
# end of Accelerated Cryptographic Algorithms for CPU (arm64)

CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_CCP is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set
# CONFIG_CRYPTO_DEV_QAT_C62X is not set
# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set
# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_ROCKCHIP=m
CONFIG_CRYPTO_DEV_ROCKCHIP_V1=y
CONFIG_CRYPTO_DEV_ROCKCHIP_V2=y
CONFIG_CRYPTO_DEV_ROCKCHIP_V3=y
CONFIG_CRYPTO_DEV_ROCKCHIP_CRYPTO=m
CONFIG_CRYPTO_DEV_ROCKCHIP_CE=y
# CONFIG_CRYPTO_DEV_ROCKCHIP_DEV is not set
CONFIG_CRYPTO_DEV_VIRTIO=m
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
# CONFIG_CRYPTO_DEV_CCREE is not set
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
# CONFIG_CRYPTO_DEV_HISI_TRNG is not set
# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_PKCS7_TEST_KEY is not set
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
# CONFIG_FIPS_SIGNATURE_SELFTEST is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_RAID6_PQ=y
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=m
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
# CONFIG_INDIRECT_PIO is not set
# CONFIG_TRACE_MMIO_ACCESS is not set

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=m
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=m
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
CONFIG_CRYPTO_LIB_CURVE25519=m
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=m
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines

CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC64_ROCKSOFT=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=y
CONFIG_CRC4=m
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=m
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
# CONFIG_XZ_DEC_SPARC is not set
# CONFIG_XZ_DEC_MICROLZMA is not set
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_INTERVAL_TREE=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_SWIOTLB=y
# CONFIG_DMA_RESTRICTED_POOL is not set
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y
# CONFIG_DMA_PERNUMA_CMA is not set

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=256
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_DMA_MAP_BENCHMARK is not set
CONFIG_SGL_ALLOC=y
# CONFIG_FORCE_NR_CPUS is not set
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
CONFIG_IRQ_POLL=y
CONFIG_MPILIB=y
CONFIG_DIMLIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_ARCH_STACKWALK=y
CONFIG_STACKDEPOT=y
CONFIG_SBITMAP=y
CONFIG_PARMAN=m
CONFIG_OBJAGG=m
# end of Library routines

CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER=y
# CONFIG_PRINTK_CALLER is not set
# CONFIG_STACKTRACE_BUILD_ID is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
CONFIG_AS_HAS_NON_CONST_LEB128=y
# CONFIG_DEBUG_INFO_NONE is not set
# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
CONFIG_DEBUG_INFO_DWARF5=y
# CONFIG_DEBUG_INFO_REDUCED is not set
CONFIG_DEBUG_INFO_COMPRESSED=y
# CONFIG_DEBUG_INFO_SPLIT is not set
CONFIG_DEBUG_INFO_BTF=y
CONFIG_PAHOLE_HAS_SPLIT_BTF=y
CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
CONFIG_DEBUG_INFO_BTF_MODULES=y
CONFIG_MODULE_ALLOW_BTF_MISMATCH=y
# CONFIG_GDB_SCRIPTS is not set
CONFIG_FRAME_WARN=2048
CONFIG_STRIP_ASM_SYMS=y
CONFIG_READABLE_ASM=y
CONFIG_HEADERS_INSTALL=y
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_VMLINUX_MAP is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_ARCH_KCSAN=y
CONFIG_HAVE_KCSAN_COMPILER=y
# CONFIG_KCSAN is not set
# end of Generic Kernel Debugging Instruments

#
# Networking Debugging
#
# CONFIG_NET_DEV_REFCNT_TRACKER is not set
# CONFIG_NET_NS_REFCNT_TRACKER is not set
# CONFIG_DEBUG_NET is not set
# end of Networking Debugging

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_SLUB_DEBUG=y
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SHRINKER_DEBUG is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
# end of Memory Debugging

# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SOFTLOCKUP_DETECTOR is not set
CONFIG_HAVE_HARDLOCKUP_DETECTOR_OTHER_CPU=y
# CONFIG_HARDLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
CONFIG_SCHED_DEBUG=y
CONFIG_SCHED_INFO=y
CONFIG_SCHEDSTATS=y
# end of Scheduler Debugging

# CONFIG_DEBUG_TIMEKEEPING is not set

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

# CONFIG_DEBUG_IRQFLAGS is not set
CONFIG_STACKTRACE=y
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set

#
# Debug kernel data structures
#
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# CONFIG_DEBUG_MAPLE_TREE is not set
# end of Debug kernel data structures

# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
# CONFIG_RCU_SCALE_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=60
# CONFIG_BOOTPARAM_RCU_STALL_PANIC is not set
CONFIG_BOOTPARAM_RCU_STALL_PANIC_VALUE=0
CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
CONFIG_RCU_TRACE=y
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
# CONFIG_LATENCYTOP is not set
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_TRACING=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_BOOTTIME_TRACING is not set
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_HWLAT_TRACER is not set
# CONFIG_OSNOISE_TRACER is not set
# CONFIG_TIMERLAT_TRACER is not set
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
# CONFIG_FTRACE_SYSCALLS is not set
# CONFIG_TRACER_SNAPSHOT is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_KPROBE_EVENTS=y
CONFIG_UPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_DYNAMIC_EVENTS=y
CONFIG_PROBE_EVENTS=y
# CONFIG_SYNTH_EVENTS is not set
# CONFIG_HIST_TRIGGERS is not set
# CONFIG_TRACE_EVENT_INJECT is not set
# CONFIG_TRACEPOINT_BENCHMARK is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_TRACE_EVAL_MAP_FILE is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
# CONFIG_KPROBE_EVENT_GEN_TEST is not set
# CONFIG_RV is not set
# CONFIG_SAMPLES is not set
# CONFIG_STRICT_DEVMEM is not set

#
# arm64 Debugging
#
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_DEBUG_EFI is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
# end of arm64 Debugging

#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FUNCTION_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_LKDTM is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_DIV64 is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TEST_REF_TRACKER is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_ASYNC_RAID6_TEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_STRING_SELFTEST is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_STRSCPY is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_SCANF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_MAPLE_TREE is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_SIPHASH is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_PARMAN is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_VMALLOC is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_BPF is not set
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_DYNAMIC_DEBUG is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_OBJAGG is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_FREE_PAGES is not set
CONFIG_ARCH_USE_MEMTEST=y
CONFIG_MEMTEST=y
# end of Kernel Testing and Coverage

#
# Rust hacking
#
# end of Rust hacking
# end of Kernel hacking


================================================
FILE: kernel-config/release/rk35xx/config-5.10
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 5.10.160 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 15.2.Rel1 (Build arm-15.86)) 15.2.1 20251203"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=150201
CONFIG_LD_VERSION=245010000
CONFIG_CLANG_VERSION=0
CONFIG_LLD_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
# CONFIG_UAPI_HEADER_TEST is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT="/sbin/init"
CONFIG_DEFAULT_HOSTNAME="none"
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
# CONFIG_WATCH_QUEUE is not set
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_USELIB is not set
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_ARCH_WANTS_IRQ_RAW=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem

CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
# CONFIG_NO_HZ_FULL is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_PREEMPTION=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_SCHED_THERMAL_PRESSURE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
CONFIG_PREEMPT_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_TASKS_RCU=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
CONFIG_UCLAMP_TASK=y
CONFIG_UCLAMP_BUCKETS_COUNT=20
# end of Scheduler features

CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_CC_HAS_INT128=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
CONFIG_MEMCG=y
CONFIG_MEMCG_SWAP=y
CONFIG_MEMCG_KMEM=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_UCLAMP_TASK_GROUP=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_SCHED_AUTOGROUP=y
# CONFIG_RT_SOFTINT_OPTIMIZATION is not set
# CONFIG_SYSFS_DEPRECATED is not set
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
# CONFIG_INITRD_ASYNC is not set
# CONFIG_BOOT_CONFIG is not set
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_BPF=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
# CONFIG_SGETMASK_SYSCALL is not set
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_PRINTK_NMI=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_HAVE_FUTEX_CMPXCHG=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
CONFIG_KALLSYMS_BASE_RELATIVE=y
# CONFIG_BPF_LSM is not set
CONFIG_BPF_SYSCALL=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
CONFIG_BPF_JIT_DEFAULT_ON=y
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
# CONFIG_BPF_PRELOAD is not set
# CONFIG_USERFAULTFD is not set
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_SYSFS=y
CONFIG_SLUB_DEBUG=y
# CONFIG_SLUB_MEMCG_SYSFS_ON is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
# CONFIG_SLAB_FREELIST_RANDOM is not set
# CONFIG_SLAB_FREELIST_HARDENED is not set
CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
# CONFIG_SLUB_CPU_PARTIAL is not set
CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
# end of General setup

CONFIG_ARM64=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_CONT_PTE_SHIFT=4
CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ZONE_DMA=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y

#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
# CONFIG_ARCH_AGILEX is not set
# CONFIG_ARCH_SUNXI is not set
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_BCM2835 is not set
# CONFIG_ARCH_BCM_IPROC is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
# CONFIG_ARCH_BRCMSTB is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SPARX5 is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LAYERSCAPE is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_KEEMBAY is not set
# CONFIG_ARCH_MEDIATEK is not set
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_RENESAS is not set
CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_S32 is not set
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_STRATIX10 is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZX is not set
# CONFIG_ARCH_ZYNQMP is not set
# end of Platform selection

#
# Kernel Features
#

#
# ARM errata workarounds via the alternatives framework
#
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_834220=y
CONFIG_ARM64_ERRATUM_1742098=y
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1319367=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_ARM64_ERRATUM_2051678=y
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
CONFIG_ARM64_ERRATUM_2054223=y
CONFIG_ARM64_ERRATUM_2067961=y
CONFIG_ARM64_ERRATUM_2454944=y
CONFIG_ARM64_ERRATUM_2457168=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
CONFIG_QCOM_FALKOR_ERRATUM_1009=y
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
# end of ARM errata workarounds via the alternatives framework

CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
CONFIG_ARM64_VA_BITS_39=y
# CONFIG_ARM64_VA_BITS_48 is not set
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SCHED_MC=y
# CONFIG_SCHED_SMT is not set
CONFIG_NR_CPUS=8
CONFIG_HOTPLUG_CPU=y
# CONFIG_NUMA is not set
CONFIG_HOLES_IN_ZONE=y
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
CONFIG_HZ_300=y
# CONFIG_HZ_1000 is not set
CONFIG_HZ=300
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_KEXEC is not set
# CONFIG_KEXEC_FILE is not set
# CONFIG_CRASH_DUMP is not set
# CONFIG_XEN is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y

#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
CONFIG_AS_HAS_LDAPR=y
CONFIG_AS_HAS_LSE_ATOMICS=y
CONFIG_ARM64_VHE=y
# end of ARMv8.1 architectural features

#
# ARMv8.2 architectural features
#
CONFIG_ARM64_UAO=y
# CONFIG_ARM64_PMEM is not set
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features

#
# ARMv8.3 architectural features
#
CONFIG_ARM64_PTR_AUTH=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
CONFIG_AS_HAS_PAC=y
CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
# end of ARMv8.3 architectural features

#
# ARMv8.4 architectural features
#
CONFIG_ARM64_AMU_EXTN=y
CONFIG_AS_HAS_ARMV8_4=y
CONFIG_ARM64_TLB_RANGE=y
# end of ARMv8.4 architectural features

#
# ARMv8.5 architectural features
#
CONFIG_AS_HAS_ARMV8_5=y
CONFIG_ARM64_BTI=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARCH_RANDOM=y
CONFIG_ARM64_AS_HAS_MTE=y
CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features

CONFIG_ARM64_SVE=y
CONFIG_ARM64_MODULE_PLTS=y
CONFIG_ARM64_PSEUDO_NMI=y
# CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
# end of Kernel Features

#
# Boot options
#
CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
CONFIG_CMDLINE=""
CONFIG_EFI_STUB=y
CONFIG_EFI=y
CONFIG_DMI=y
# end of Boot options

CONFIG_SYSVIPC_COMPAT=y
CONFIG_ARCH_ENABLE_THP_MIGRATION=y

#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
# CONFIG_HIBERNATION is not set
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
# CONFIG_PM_TEST_SUSPEND is not set
CONFIG_PM_SLEEP_DEBUG=y
CONFIG_DPM_WATCHDOG=y
CONFIG_DPM_WATCHDOG_TIMEOUT=120
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options

#
# CPU Power Management
#

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
# CONFIG_CPU_IDLE_GOV_LADDER is not set
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_DT_IDLE_STATES=y

#
# ARM CPU Idle Drivers
#
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
# end of ARM CPU Idle Drivers
# end of CPU Idle

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_TIMES=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_INTERACTIVE=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
# CONFIG_CPUFREQ_DUMMY is not set
CONFIG_ACPI_CPPC_CPUFREQ=y
CONFIG_ARM_ROCKCHIP_CPUFREQ=y
CONFIG_ARM_SCMI_CPUFREQ=y
# end of CPU Frequency scaling
# end of CPU Power Management

#
# Firmware Drivers
#
CONFIG_ARM_SCMI_PROTOCOL=y
CONFIG_ARM_SCMI_POWER_DOMAIN=y
# CONFIG_ARM_SCPI_PROTOCOL is not set
# CONFIG_ARM_SDE_INTERFACE is not set
# CONFIG_FIRMWARE_MEMMAP is not set
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=y
# CONFIG_ISCSI_IBFT is not set
CONFIG_FW_CFG_SYSFS=y
CONFIG_FW_CFG_SYSFS_CMDLINE=y
# CONFIG_QCOM_SCM is not set
CONFIG_ROCKCHIP_SIP=y
# CONFIG_GOOGLE_FIRMWARE is not set

#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_VARS_PSTORE=y
# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_GENERIC_STUB=y
CONFIG_EFI_ARMSTUB_DTB_LOADER=y
CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
# CONFIG_EFI_BOOTLOADER_CONTROL is not set
# CONFIG_EFI_CAPSULE_LOADER is not set
# CONFIG_EFI_TEST is not set
# CONFIG_RESET_ATTACK_MITIGATION is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
# end of EFI (Extensible Firmware Interface) Support

CONFIG_UEFI_CPER=y
CONFIG_UEFI_CPER_ARM=y
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_PSCI_CHECKER is not set
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_ARM_SMCCC_SOC_ID=y

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_GENERIC_GSI=y
CONFIG_ACPI_CCA_REQUIRED=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
CONFIG_ACPI_EC_DEBUGFS=m
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_FAN=y
CONFIG_ACPI_TAD=m
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_MCFG=y
CONFIG_ACPI_CPPC_LIB=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_HOTPLUG_CPU=y
CONFIG_ACPI_THERMAL=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_PCI_SLOT=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_CUSTOM_METHOD=m
CONFIG_ACPI_BGRT=y
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
CONFIG_HAVE_ACPI_APEI=y
CONFIG_ACPI_APEI=y
CONFIG_ACPI_APEI_GHES=y
CONFIG_ACPI_APEI_SEA=y
CONFIG_ACPI_APEI_EINJ=m
CONFIG_ACPI_APEI_ERST_DEBUG=m
CONFIG_ACPI_CONFIGFS=m
CONFIG_ACPI_IORT=y
CONFIG_ACPI_GTDT=y
CONFIG_ACPI_PPTT=y
CONFIG_PMIC_OPREGION=y
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_MMIO=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_ARM64_CRYPTO=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64_CE=y
CONFIG_CRYPTO_SHA3_ARM64=y
CONFIG_CRYPTO_SM3_ARM64_CE=y
CONFIG_CRYPTO_SM4_ARM64_CE=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_CHACHA20_NEON=y
CONFIG_CRYPTO_POLY1305_NEON=y
CONFIG_CRYPTO_NHPOLY1305_NEON=y
CONFIG_CRYPTO_AES_ARM64_BS=y

#
# General architecture-dependent options
#
CONFIG_SET_FS=y
CONFIG_KPROBES=y
# CONFIG_JUMP_LABEL is not set
CONFIG_UPROBES=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLK_RQ_ALLOC_TIME=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BLK_CGROUP_RWSTAT=y
CONFIG_BLK_DEV_BSG=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=y
CONFIG_BLK_DEV_ZONED=y
CONFIG_BLK_DEV_THROTTLING=y
# CONFIG_BLK_DEV_THROTTLING_LOW is not set
CONFIG_BLK_CMDLINE_PARSER=y
CONFIG_BLK_WBT=y
CONFIG_BLK_WBT_MQ=y
CONFIG_BLK_CGROUP_IOLATENCY=y
CONFIG_BLK_CGROUP_IOCOST=y
CONFIG_BLK_CGROUP_IOPRIO=y
CONFIG_BLK_DEBUG_FS=y
CONFIG_BLK_DEBUG_FS_ZONED=y
CONFIG_BLK_SED_OPAL=y
# CONFIG_BLK_INLINE_ENCRYPTION is not set

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_AIX_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
CONFIG_CMDLINE_PARTITION=y
# end of Partition Types

CONFIG_BLOCK_COMPAT=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=m
CONFIG_BLK_PM=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_DEADLINE_CGROUP=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=m
CONFIG_BFQ_GROUP_IOSCHED=y
# CONFIG_BFQ_CGROUP_DEBUG is not set
# end of IO Schedulers

CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
# CONFIG_GKI_HIDDEN_DRM_CONFIGS is not set
# CONFIG_GKI_HIDDEN_REGMAP_CONFIGS is not set
# CONFIG_GKI_HIDDEN_CRYPTO_CONFIGS is not set
# CONFIG_GKI_HIDDEN_SND_CONFIGS is not set
# CONFIG_GKI_HIDDEN_SND_SOC_CONFIGS is not set
# CONFIG_GKI_HIDDEN_MMC_CONFIGS is not set
# CONFIG_GKI_HIDDEN_GPIO_CONFIGS is not set
# CONFIG_GKI_HIDDEN_QCOM_CONFIGS is not set
# CONFIG_GKI_HIDDEN_MEDIA_CONFIGS is not set
# CONFIG_GKI_HIDDEN_VIRTUAL_CONFIGS is not set
# CONFIG_GKI_LEGACY_WEXT_ALLCONFIG is not set
# CONFIG_GKI_HIDDEN_USB_CONFIGS is not set
# CONFIG_GKI_HIDDEN_SOC_BUS_CONFIGS is not set
# CONFIG_GKI_HIDDEN_RPMSG_CONFIGS is not set
# CONFIG_GKI_HIDDEN_GPU_CONFIGS is not set
# CONFIG_GKI_HIDDEN_IRQ_CONFIGS is not set
# CONFIG_GKI_HIDDEN_HYPERVISOR_CONFIGS is not set
# CONFIG_GKI_HIDDEN_NET_CONFIGS is not set
# CONFIG_GKI_HIDDEN_PHY_CONFIGS is not set
# CONFIG_GKI_HIDDEN_MM_CONFIGS is not set
# CONFIG_GKI_HIDDEN_DMA_CONFIGS is not set
# CONFIG_GKI_HIDDEN_ETHERNET_CONFIGS is not set
# CONFIG_GKI_HACKS_TO_FIX is not set
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_HAVE_ELF_PROT=y
CONFIG_ARCH_USE_GNU_PROPERTY=y
CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=m
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_BOUNCE=y
CONFIG_MMU_NOTIFIER=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
# CONFIG_MEMORY_FAILURE is not set
CONFIG_TRANSPARENT_HUGEPAGE=y
# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set
CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
CONFIG_CLEANCACHE=y
CONFIG_FRONTSWAP=y
CONFIG_CMA=y
# CONFIG_CMA_INACTIVE is not set
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_CMA_AREAS=7
# CONFIG_ZSWAP is not set
CONFIG_ZPOOL=y
CONFIG_ZBUD=y
CONFIG_Z3FOLD=y
CONFIG_ZSMALLOC=y
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_PAGE_IDLE_FLAG=y
CONFIG_IDLE_PAGE_TRACKING=y
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_FRAME_VECTOR=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
CONFIG_PERCPU_STATS=y
CONFIG_ARCH_SUPPORTS_SPECULATIVE_PAGE_FAULT=y
CONFIG_SPECULATIVE_PAGE_FAULT=y
# CONFIG_GUP_BENCHMARK is not set
# CONFIG_READ_ONLY_THP_FOR_FS is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_LRU_GEN=y
CONFIG_LRU_GEN_ENABLED=y
# CONFIG_LRU_GEN_STATS is not set

#
# Data Access Monitoring
#
# CONFIG_DAMON is not set
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_EXTENSIONS=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_UNIX_SCM=y
CONFIG_UNIX_DIAG=y
# CONFIG_TLS is not set
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
# CONFIG_XFRM_INTERFACE is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_AH=m
CONFIG_XFRM_ESP=m
CONFIG_XFRM_IPCOMP=m
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_XFRM_ESPINTCP=y
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
# CONFIG_IP_FIB_TRIE_STATS is not set
CONFIG_IP_MULTIPLE_TABLES=y
# CONFIG_IP_ROUTE_MULTIPATH is not set
# CONFIG_IP_ROUTE_VERBOSE is not set
CONFIG_IP_ROUTE_CLASSID=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=m
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=m
CONFIG_NET_FOU=m
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_ESP_OFFLOAD=m
CONFIG_INET_ESPINTCP=y
CONFIG_INET_IPCOMP=m
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_DIAG=m
CONFIG_INET_TCP_DIAG=m
CONFIG_INET_UDP_DIAG=m
CONFIG_INET_RAW_DIAG=m
# CONFIG_INET_DIAG_DESTROY is not set
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_NV=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_CONG_DCTCP=m
CONFIG_TCP_CONG_CDG=m
CONFIG_TCP_CONG_BBR=m
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=m
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_ESP_OFFLOAD=m
CONFIG_INET6_ESPINTCP=y
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_MIP6=m
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=m
CONFIG_INET6_TUNNEL=m
CONFIG_IPV6_VTI=m
CONFIG_IPV6_SIT=m
CONFIG_IPV6_SIT_6RD=y
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=m
CONFIG_IPV6_GRE=m
CONFIG_IPV6_FOU=m
CONFIG_IPV6_FOU_TUNNEL=m
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
# CONFIG_IPV6_SEG6_HMAC is not set
# CONFIG_IPV6_RPL_LWTUNNEL is not set
# CONFIG_NETLABEL is not set
# CONFIG_MPTCP is not set
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NETWORK_PHY_TIMESTAMPING=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_NETLINK=y
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
CONFIG_NETFILTER_NETLINK_ACCT=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NETFILTER_NETLINK_OSF=m
CONFIG_NF_CONNTRACK=y
CONFIG_NF_LOG_COMMON=m
CONFIG_NF_LOG_NETDEV=m
CONFIG_NETFILTER_CONNCOUNT=m
CONFIG_NF_CONNTRACK_MARK=y
# CONFIG_NF_CONNTRACK_SECMARK is not set
# CONFIG_NF_CONNTRACK_ZONES is not set
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y
# CONFIG_NF_CONNTRACK_TIMEOUT is not set
CONFIG_NF_CONNTRACK_TIMESTAMP=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=y
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=y
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_COUNTER=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_OBJREF=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
CONFIG_NFT_OSF=m
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NF_DUP_NETDEV=y
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XTABLES=y

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=y
CONFIG_NETFILTER_XT_CONNMARK=y
CONFIG_NETFILTER_XT_SET=m

#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_AUDIT=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LED=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=y
CONFIG_NETFILTER_XT_TARGET_NETMAP=y
CONFIG_NETFILTER_XT_TARGET_FULLCONENAT=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD=m
CONFIG_NETFILTER_XT_TARGET_RATEEST=y
CONFIG_NETFILTER_XT_TARGET_REDIRECT=y
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
CONFIG_NETFILTER_XT_TARGET_SECMARK=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=y
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=y
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_QUOTA2=m
CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# end of Core Netfilter Configuration

CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
# CONFIG_IP_VS_DEBUG is not set
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_SOCKET_IPV4=m
CONFIG_NF_TPROXY_IPV4=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=m
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_FULLCONENAT=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_SECURITY=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP6_NF_SECURITY=m
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=y
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_NFT_BRIDGE_META=m
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NF_LOG_BRIDGE=m
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
# CONFIG_BPFILTER is not set
# CONFIG_IP_DCCP is not set
CONFIG_IP_SCTP=m
# CONFIG_SCTP_DBG_OBJCNT is not set
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=m
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
CONFIG_ATM=m
# CONFIG_ATM_CLIP is not set
# CONFIG_ATM_LANE is not set
CONFIG_ATM_BR2684=m
# CONFIG_ATM_BR2684_IPFILTER is not set
CONFIG_L2TP=m
# CONFIG_L2TP_DEBUGFS is not set
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=m
CONFIG_L2TP_ETH=m
CONFIG_STP=m
CONFIG_BRIDGE=m
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
# CONFIG_BRIDGE_MRP is not set
CONFIG_HAVE_NET_DSA=y
CONFIG_NET_DSA=m
CONFIG_NET_DSA_TAG_8021Q=m
CONFIG_NET_DSA_TAG_AR9331=m
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
CONFIG_NET_DSA_TAG_BRCM=m
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
CONFIG_NET_DSA_TAG_GSWIP=m
CONFIG_NET_DSA_TAG_DSA=m
CONFIG_NET_DSA_TAG_EDSA=m
CONFIG_NET_DSA_TAG_MTK=m
CONFIG_NET_DSA_TAG_KSZ=m
CONFIG_NET_DSA_TAG_RTL4_A=m
CONFIG_NET_DSA_TAG_OCELOT=m
CONFIG_NET_DSA_TAG_QCA=m
CONFIG_NET_DSA_TAG_LAN9303=m
CONFIG_NET_DSA_TAG_SJA1105=m
CONFIG_NET_DSA_TAG_TRAILER=m
CONFIG_VLAN_8021Q=m
# CONFIG_VLAN_8021Q_GVRP is not set
# CONFIG_VLAN_8021Q_MVRP is not set
# CONFIG_DECNET is not set
CONFIG_LLC=m
CONFIG_LLC2=m
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
CONFIG_6LOWPAN=m
# CONFIG_6LOWPAN_DEBUGFS is not set
CONFIG_6LOWPAN_NHC=m
CONFIG_6LOWPAN_NHC_DEST=m
CONFIG_6LOWPAN_NHC_FRAGMENT=m
CONFIG_6LOWPAN_NHC_HOP=m
CONFIG_6LOWPAN_NHC_IPV6=m
CONFIG_6LOWPAN_NHC_MOBILITY=m
CONFIG_6LOWPAN_NHC_ROUTING=m
CONFIG_6LOWPAN_NHC_UDP=m
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
CONFIG_6LOWPAN_GHC_UDP=m
CONFIG_6LOWPAN_GHC_ICMPV6=m
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
CONFIG_IEEE802154=m
# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set
CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_MAC802154=m
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_ATM=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFB=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_SKBPRIO=m
CONFIG_NET_SCH_CHOKE=m
CONFIG_NET_SCH_QFQ=m
CONFIG_NET_SCH_CODEL=m
CONFIG_NET_SCH_FQ_CODEL=m
CONFIG_NET_SCH_CAKE=m
CONFIG_NET_SCH_FQ=m
CONFIG_NET_SCH_HHF=m
CONFIG_NET_SCH_PIE=m
CONFIG_NET_SCH_FQ_PIE=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_SCH_PLUG=m
CONFIG_NET_SCH_ETS=m
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
# CONFIG_CLS_U32_PERF is not set
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_RSVP=m
CONFIG_NET_CLS_RSVP6=m
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=m
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_EMATCH_CANID=m
CONFIG_NET_EMATCH_IPSET=m
CONFIG_NET_EMATCH_IPT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
# CONFIG_NET_ACT_SAMPLE is not set
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
CONFIG_NET_ACT_MPLS=m
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_NET_ACT_CONNMARK=m
CONFIG_NET_ACT_CTINFO=m
CONFIG_NET_ACT_SKBMOD=m
CONFIG_NET_ACT_IFE=m
CONFIG_NET_ACT_TUNNEL_KEY=m
# CONFIG_NET_ACT_CT is not set
CONFIG_NET_ACT_GATE=m
CONFIG_NET_IFE_SKBMARK=m
CONFIG_NET_IFE_SKBPRIO=m
CONFIG_NET_IFE_SKBTCINDEX=m
# CONFIG_NET_TC_SKB_EXT is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=y
CONFIG_BATMAN_ADV=m
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
# CONFIG_BATMAN_ADV_NC is not set
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUGFS is not set
# CONFIG_BATMAN_ADV_DEBUG is not set
# CONFIG_BATMAN_ADV_SYSFS is not set
# CONFIG_BATMAN_ADV_TRACING is not set
CONFIG_OPENVSWITCH=m
CONFIG_OPENVSWITCH_GRE=m
CONFIG_OPENVSWITCH_VXLAN=m
CONFIG_OPENVSWITCH_GENEVE=m
CONFIG_VSOCKETS=m
CONFIG_VSOCKETS_DIAG=m
CONFIG_VSOCKETS_LOOPBACK=m
CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO_VSOCKETS_COMMON=m
CONFIG_NETLINK_DIAG=y
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=m
# CONFIG_MPLS_ROUTING is not set
CONFIG_NET_NSH=m
# CONFIG_HSR is not set
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=m
# CONFIG_QRTR_SMD is not set
# CONFIG_QRTR_TUN is not set
CONFIG_QRTR_MHI=m
# CONFIG_NET_NCSI is not set
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_XPS=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_JIT=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_NET_DROP_MONITOR is not set
# end of Network testing
# end of Networking options

# CONFIG_HAMRADIO is not set
CONFIG_CAN=m
CONFIG_CAN_RAW=m
CONFIG_CAN_BCM=m
CONFIG_CAN_GW=m
# CONFIG_CAN_J1939 is not set
# CONFIG_CAN_ISOTP is not set

#
# CAN Device Drivers
#
CONFIG_CAN_VCAN=m
# CONFIG_CAN_VXCAN is not set
CONFIG_CAN_SLCAN=m
CONFIG_CAN_DEV=m
CONFIG_CAN_CALC_BITTIMING=y
# CONFIG_CAN_FLEXCAN is not set
CONFIG_CAN_GRCAN=m
# CONFIG_CAN_KVASER_PCIEFD is not set
CONFIG_CAN_XILINXCAN=m
CONFIG_CAN_C_CAN=m
CONFIG_CAN_C_CAN_PLATFORM=m
CONFIG_CAN_C_CAN_PCI=m
CONFIG_CAN_CC770=m
CONFIG_CAN_CC770_ISA=m
CONFIG_CAN_CC770_PLATFORM=m
# CONFIG_CAN_IFI_CANFD is not set
CONFIG_CAN_M_CAN=m
# CONFIG_CAN_M_CAN_PLATFORM is not set
# CONFIG_CAN_M_CAN_TCAN4X5X is not set
# CONFIG_CAN_PEAK_PCIEFD is not set
CONFIG_CAN_ROCKCHIP=m
CONFIG_CANFD_ROCKCHIP=m
CONFIG_CAN_SJA1000=m
CONFIG_CAN_EMS_PCI=m
# CONFIG_CAN_F81601 is not set
CONFIG_CAN_KVASER_PCI=m
CONFIG_CAN_PEAK_PCI=m
CONFIG_CAN_PEAK_PCIEC=y
CONFIG_CAN_PLX_PCI=m
CONFIG_CAN_SJA1000_ISA=m
CONFIG_CAN_SJA1000_PLATFORM=m
CONFIG_CAN_SOFTING=m

#
# CAN SPI interfaces
#
# CONFIG_CAN_HI311X is not set
CONFIG_CAN_MCP251X=m
# CONFIG_CAN_MCP251XFD is not set
# end of CAN SPI interfaces

#
# CAN USB interfaces
#
CONFIG_CAN_8DEV_USB=m
CONFIG_CAN_EMS_USB=m
CONFIG_CAN_ESD_USB2=m
CONFIG_CAN_GS_USB=m
CONFIG_CAN_KVASER_USB=m
# CONFIG_CAN_MCBA_USB is not set
CONFIG_CAN_PEAK_USB=m
# CONFIG_CAN_UCAN is not set
# end of CAN USB interfaces

CONFIG_CAN_DEBUG_DEVICES=y
# end of CAN Device Drivers

CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=y
CONFIG_BT_HS=y
CONFIG_BT_LE=y
CONFIG_BT_6LOWPAN=m
CONFIG_BT_LEDS=y
CONFIG_BT_MSFTEXT=y
CONFIG_BT_AOSPEXT=y
CONFIG_BT_DEBUGFS=y
# CONFIG_BT_SELFTEST is not set

#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=m
CONFIG_BT_BCM=m
CONFIG_BT_RTL=m
CONFIG_BT_MTK=m
CONFIG_BT_HCIBTUSB=m
# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
CONFIG_BT_HCIBTUSB_BCM=y
CONFIG_BT_HCIBTUSB_MTK=y
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_AG6XX=y
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
CONFIG_BT_MTKSDIO=m
CONFIG_BT_HCIBTUSB_RTLBTUSB=m
CONFIG_BT_VIRTIO=m
# end of Bluetooth device drivers

CONFIG_AF_RXRPC=m
# CONFIG_AF_RXRPC_IPV6 is not set
# CONFIG_AF_RXRPC_INJECT_LOSS is not set
# CONFIG_AF_RXRPC_DEBUG is not set
# CONFIG_RXKAD is not set
# CONFIG_AF_KCM is not set
CONFIG_STREAM_PARSER=y
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_SPY=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_CFG80211_WEXT_EXPORT=y
CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
CONFIG_LIB80211_CRYPT_TKIP=m
# CONFIG_LIB80211_DEBUG is not set
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
# CONFIG_MAC80211_MESH is not set
CONFIG_MAC80211_LEDS=y
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_MESSAGE_TRACING is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
# CONFIG_WIMAX is not set
CONFIG_RFKILL=y
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=y
CONFIG_RFKILL_RK=y
CONFIG_NET_9P=m
CONFIG_NET_9P_VIRTIO=m
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
CONFIG_CEPH_LIB=m
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
# CONFIG_NFC is not set
# CONFIG_PSAMPLE is not set
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
CONFIG_FAILOVER=m
CONFIG_ETHTOOL_NETLINK=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_SHORTCUT_FE=y

#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIEAER is not set
CONFIG_PCIEASPM=y
# CONFIG_PCIEASPM_DEFAULT is not set
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEASPM_PERFORMANCE=y
# CONFIG_PCIEASPM_EXT is not set
CONFIG_PCIE_PME=y
CONFIG_PCIE_PTM=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_STUB is not set
CONFIG_PCI_ATS=y
CONFIG_PCI_ECAM=y
# CONFIG_PCI_IOV is not set
CONFIG_PCI_PRI=y
CONFIG_PCI_PASID=y
CONFIG_PCI_LABEL=y
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
# CONFIG_HOTPLUG_PCI is not set

#
# PCI controller drivers
#
# CONFIG_PCI_FTPCI100 is not set
# CONFIG_PCI_HOST_GENERIC is not set
# CONFIG_PCIE_XILINX is not set
# CONFIG_PCI_XGENE is not set
# CONFIG_PCIE_ALTERA is not set
# CONFIG_PCI_HOST_THUNDER_PEM is not set
# CONFIG_PCI_HOST_THUNDER_ECAM is not set
CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_HOST=y
# CONFIG_ROCKCHIP_PCIE_DMA_OBJ is not set
# CONFIG_PCIE_HISI_ERR is not set

#
# DesignWare PCI Core Support
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
CONFIG_PCIE_DW_ROCKCHIP=y
# CONFIG_PCIE_RK_THREADED_INIT is not set
# CONFIG_PCIE_DW_DMATEST is not set
CONFIG_PCIE_DW_ROCKCHIP_EP=y
# CONFIG_PCI_HISI is not set
# CONFIG_PCIE_KIRIN is not set
# CONFIG_PCI_MESON is not set
# CONFIG_PCIE_AL is not set
# end of DesignWare PCI Core Support

#
# Mobiveil PCIe Core Support
#
# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set
# end of Mobiveil PCIe Core Support

#
# Cadence PCIe controllers support
#
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCI_J721E_HOST is not set
# end of Cadence PCIe controllers support
# end of PCI controller drivers

#
# PCI Endpoint
#
# CONFIG_PCI_ENDPOINT is not set
# end of PCI Endpoint

#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set
# end of PCI switch controller drivers

# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
CONFIG_FW_LOADER_COMPRESS=y
# CONFIG_FW_LOADER_COMPRESS_XZ is not set
# CONFIG_FW_LOADER_COMPRESS_ZSTD is not set
CONFIG_FW_CACHE=y
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
CONFIG_DEBUG_DEVRES=y
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SCCB=m
CONFIG_MALI_BASE_MODULES=y
CONFIG_DMA_SHARED_BUFFER_TEST_EXPORTER=y
CONFIG_MALI_MEMORY_GROUP_MANAGER=y
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
# CONFIG_BRCMSTB_GISB_ARB is not set
# CONFIG_MOXTET is not set
# CONFIG_SIMPLE_PM_BUS is not set
# CONFIG_VEXPRESS_CONFIG is not set
CONFIG_MHI_BUS=m
# CONFIG_MHI_BUS_DEBUG is not set
# CONFIG_MHI_BUS_PCI_GENERIC is not set
# CONFIG_MHI_BUS_EP is not set
# end of Bus devices

CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
CONFIG_GNSS=m
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_OF_PARTS=y
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
CONFIG_MTD_NAND_CORE=y
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
CONFIG_MTD_SPI_NAND=y

#
# ECC engine support
#
CONFIG_MTD_NAND_BBT_USING_FLASH=y
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
# CONFIG_MTD_SPI_NOR_MISC is not set
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
# CONFIG_MTD_UBI_BLOCK is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_DTC_SYMBOLS is not set
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_NET=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_NULL_BLK is not set
CONFIG_CDROM=m
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
CONFIG_ZRAM=y
# CONFIG_ZRAM_WRITEBACK is not set
# CONFIG_ZRAM_MEMORY_TRACKING is not set
# CONFIG_BLK_DEV_UMEM is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=128
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
CONFIG_BLK_DEV_DRBD=m
# CONFIG_DRBD_FAULT_INJECTION is not set
CONFIG_BLK_DEV_NBD=m
# CONFIG_BLK_DEV_SKD is not set
# CONFIG_BLK_DEV_SX8 is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_VIRTIO_BLK=m
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_RSXX is not set

#
# NVME Support
#
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
# CONFIG_NVME_MULTIPATH is not set
# CONFIG_NVME_HWMON is not set
# CONFIG_NVME_FC is not set
# CONFIG_NVME_TCP is not set
# CONFIG_NVME_TARGET is not set
# end of NVME Support

#
# Misc devices
#

#
# RK628 misc driver
#
# CONFIG_RK628_MISC is not set
# end of RK628 misc driver

CONFIG_RK803=m
CONFIG_PCIE_FUNC_RKEP=m
CONFIG_LT7911D_FB_NOTIFIER=m
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
# CONFIG_TIFM_CORE is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_XILINX_SDFEC is not set
CONFIG_MISC_RTSX=m
# CONFIG_UID_SYS_STATS is not set
# CONFIG_PVPANIC is not set
# CONFIG_HISI_HIKEY_USB is not set
CONFIG_ROCKPI_MCU=y
# CONFIG_C2PORT is not set

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
CONFIG_EEPROM_93CX6=m
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

# CONFIG_CB710_CORE is not set

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline

# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_MISC_ALCOR_PCI is not set
# CONFIG_MISC_RTSX_PCI is not set
CONFIG_MISC_RTSX_USB=m
# CONFIG_HABANA_AI is not set
# CONFIG_UACCE is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
CONFIG_RAID_ATTRS=m
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=m
# CONFIG_CHR_DEV_ST is not set
CONFIG_BLK_DEV_SR=m
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
CONFIG_SCSI_SCAN_ASYNC=y

#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=m
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=m
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_ISCSI_BOOT_SYSFS=m
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_FDOMAIN_PCI is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
CONFIG_SCSI_VIRTIO=m
# CONFIG_SCSI_DH is not set
# end of SCSI device support

CONFIG_HAVE_PATA_PLATFORM=y
CONFIG_ATA=y
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_AHCI_CEVA=m
CONFIG_AHCI_QORIQ=m
CONFIG_SATA_INIC162X=m
CONFIG_SATA_ACARD_AHCI=m
CONFIG_SATA_SIL24=m
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#
CONFIG_PDC_ADMA=m
CONFIG_SATA_QSTOR=m
CONFIG_SATA_SX4=m
CONFIG_ATA_BMDMA=y

#
# SATA SFF controllers with BMDMA
#
# CONFIG_ATA_PIIX is not set
CONFIG_SATA_DWC=y
# CONFIG_SATA_DWC_OLD_DMA is not set
# CONFIG_SATA_DWC_DEBUG is not set
CONFIG_SATA_MV=m
# CONFIG_SATA_NV is not set
CONFIG_SATA_PROMISE=m
CONFIG_SATA_SIL=m
CONFIG_SATA_SIS=m
# CONFIG_SATA_SVW is not set
CONFIG_SATA_ULI=m
CONFIG_SATA_VIA=m
# CONFIG_SATA_VITESSE is not set

#
# PATA SFF controllers with BMDMA
#
# CONFIG_PATA_ALI is not set
# CONFIG_PATA_AMD is not set
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_ATP867X is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CYPRESS is not set
# CONFIG_PATA_EFAR is not set
# CONFIG_PATA_HPT366 is not set
# CONFIG_PATA_HPT37X is not set
# CONFIG_PATA_HPT3X2N is not set
# CONFIG_PATA_HPT3X3 is not set
# CONFIG_PATA_IT8213 is not set
# CONFIG_PATA_IT821X is not set
# CONFIG_PATA_JMICRON is not set
# CONFIG_PATA_MARVELL is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_OPTIDMA is not set
# CONFIG_PATA_PDC2027X is not set
# CONFIG_PATA_PDC_OLD is not set
# CONFIG_PATA_RADISYS is not set
# CONFIG_PATA_RDC is not set
# CONFIG_PATA_SCH is not set
# CONFIG_PATA_SERVERWORKS is not set
# CONFIG_PATA_SIL680 is not set
CONFIG_PATA_SIS=m
# CONFIG_PATA_TOSHIBA is not set
# CONFIG_PATA_TRIFLEX is not set
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set

#
# PIO-only SFF controllers
#
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_PLATFORM is not set
# CONFIG_PATA_RZ1000 is not set

#
# Generic fallback / legacy drivers
#
CONFIG_PATA_ACPI=y
# CONFIG_ATA_GENERIC is not set
# CONFIG_PATA_LEGACY is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
# CONFIG_MD_CLUSTER is not set
CONFIG_BCACHE=m
# CONFIG_BCACHE_DEBUG is not set
# CONFIG_BCACHE_CLOSURES_DEBUG is not set
# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=m
# CONFIG_DM_DEBUG is not set
CONFIG_DM_BUFIO=m
# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
# CONFIG_DM_UNSTRIPED is not set
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
CONFIG_DM_CACHE=m
CONFIG_DM_CACHE_SMQ=m
CONFIG_DM_WRITECACHE=m
# CONFIG_DM_EBS is not set
CONFIG_DM_ERA=m
# CONFIG_DM_CLONE is not set
CONFIG_DM_MIRROR=m
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
# CONFIG_DM_MULTIPATH_HST is not set
CONFIG_DM_DELAY=m
# CONFIG_DM_DUST is not set
# CONFIG_DM_UEVENT is not set
CONFIG_DM_FLAKEY=m
CONFIG_DM_VERITY=m
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
# CONFIG_DM_VERITY_FEC is not set
CONFIG_DM_SWITCH=m
CONFIG_DM_LOG_WRITES=m
# CONFIG_DM_INTEGRITY is not set
# CONFIG_DM_ZONED is not set
# CONFIG_DM_BOW is not set
CONFIG_DM_USER=m
# CONFIG_TARGET_CORE is not set
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
# end of IEEE 1394 (FireWire) support

CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_WIREGUARD=m
# CONFIG_WIREGUARD_DEBUG is not set
CONFIG_EQUALIZER=m
# CONFIG_NET_FC is not set
CONFIG_IFB=m
CONFIG_NET_TEAM=m
CONFIG_NET_TEAM_MODE_BROADCAST=m
CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
CONFIG_NET_TEAM_MODE_RANDOM=m
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
CONFIG_NET_TEAM_MODE_LOADBALANCE=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=m
CONFIG_IPVTAP=m
CONFIG_VXLAN=m
CONFIG_GENEVE=m
CONFIG_BAREUDP=m
CONFIG_GTP=m
CONFIG_MACSEC=m
CONFIG_NETCONSOLE=m
# CONFIG_NETCONSOLE_DYNAMIC is not set
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=m
CONFIG_TAP=m
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_NLMON=m
CONFIG_NET_VRF=m
CONFIG_VSOCKMON=m
CONFIG_ARCNET=m
# CONFIG_ARCNET_1201 is not set
# CONFIG_ARCNET_1051 is not set
# CONFIG_ARCNET_RAW is not set
# CONFIG_ARCNET_CAP is not set
# CONFIG_ARCNET_COM90xx is not set
# CONFIG_ARCNET_COM90xxIO is not set
# CONFIG_ARCNET_RIM_I is not set
# CONFIG_ARCNET_COM20020 is not set
CONFIG_ATM_DRIVERS=y
# CONFIG_ATM_DUMMY is not set
# CONFIG_ATM_TCP is not set
# CONFIG_ATM_LANAI is not set
# CONFIG_ATM_ENI is not set
# CONFIG_ATM_NICSTAR is not set
# CONFIG_ATM_IDT77252 is not set
# CONFIG_ATM_IA is not set
# CONFIG_ATM_FORE200E is not set
# CONFIG_ATM_HE is not set
# CONFIG_ATM_SOLOS is not set

#
# Distributed Switch Architecture drivers
#
CONFIG_B53=m
# CONFIG_B53_SPI_DRIVER is not set
# CONFIG_B53_MDIO_DRIVER is not set
# CONFIG_B53_MMAP_DRIVER is not set
# CONFIG_B53_SRAB_DRIVER is not set
# CONFIG_B53_SERDES is not set
CONFIG_NET_DSA_BCM_SF2=m
CONFIG_NET_DSA_LOOP=m
CONFIG_NET_DSA_LANTIQ_GSWIP=m
CONFIG_NET_DSA_MT7530=m
CONFIG_NET_DSA_MV88E6060=m
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
# CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C is not set
# CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI is not set
CONFIG_NET_DSA_MICROCHIP_KSZ8795=m
# CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI is not set
CONFIG_NET_DSA_MV88E6XXX=m
CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
# CONFIG_NET_DSA_MV88E6XXX_PTP is not set
CONFIG_NET_DSA_AR9331=m
CONFIG_NET_DSA_SJA1105=m
# CONFIG_NET_DSA_SJA1105_PTP is not set
CONFIG_NET_DSA_QCA8K=m
CONFIG_NET_DSA_REALTEK_SMI=m
CONFIG_NET_DSA_SMSC_LAN9303=m
CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
CONFIG_NET_DSA_VITESSE_VSC73XX=m
CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
# end of Distributed Switch Architecture drivers

CONFIG_ETHERNET=y
CONFIG_MDIO=m
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_ALTERA_TSE is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_ATHEROS is not set
# CONFIG_NET_VENDOR_AURORA is not set
CONFIG_NET_VENDOR_BROADCOM=y
CONFIG_B44=m
CONFIG_B44_PCI_AUTOSELECT=y
CONFIG_B44_PCICORE_AUTOSELECT=y
CONFIG_B44_PCI=y
# CONFIG_BCMGENET is not set
CONFIG_BNX2=m
CONFIG_CNIC=m
CONFIG_TIGON3=m
# CONFIG_TIGON3_HWMON is not set
CONFIG_BNX2X=m
# CONFIG_SYSTEMPORT is not set
CONFIG_BNXT=m
CONFIG_BNXT_FLOWER_OFFLOAD=y
CONFIG_BNXT_HWMON=y
CONFIG_NET_VENDOR_BROCADE=y
CONFIG_BNA=m
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_DNET is not set
# CONFIG_NET_VENDOR_DEC is not set
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
CONFIG_NET_VENDOR_HISILICON=y
CONFIG_HIX5HD2_GMAC=m
CONFIG_HISI_FEMAC=m
CONFIG_HIP04_ETH=m
# CONFIG_HI13X1_GMAC is not set
CONFIG_HNS_MDIO=m
CONFIG_HNS=m
CONFIG_HNS_DSAF=m
CONFIG_HNS_ENET=m
CONFIG_HNS3=m
CONFIG_HNS3_HCLGE=m
CONFIG_HNS3_HCLGEVF=m
CONFIG_HNS3_ENET=m
CONFIG_NET_VENDOR_HUAWEI=y
CONFIG_HINIC=m
CONFIG_NET_VENDOR_I825XX=y
CONFIG_NET_VENDOR_INTEL=y
# CONFIG_E100 is not set
CONFIG_E1000=m
CONFIG_E1000E=m
CONFIG_IGB=m
# CONFIG_IGB_HWMON is not set
CONFIG_IGBVF=m
CONFIG_IXGB=m
CONFIG_IXGBE=m
CONFIG_IXGBE_HWMON=y
CONFIG_IXGBE_IPSEC=y
CONFIG_IXGBEVF=m
CONFIG_IXGBEVF_IPSEC=y
CONFIG_I40E=m
CONFIG_IAVF=m
CONFIG_I40EVF=m
CONFIG_ICE=m
CONFIG_FM10K=m
CONFIG_IGC=m
# CONFIG_JME is not set
# CONFIG_NET_VENDOR_MARVELL is not set
CONFIG_NET_VENDOR_MELLANOX=y
CONFIG_MLX4_EN=m
CONFIG_MLX4_CORE=m
CONFIG_MLX4_DEBUG=y
CONFIG_MLX4_CORE_GEN2=y
CONFIG_MLX5_CORE=m
CONFIG_MLX5_ACCEL=y
CONFIG_MLX5_FPGA=y
CONFIG_MLX5_CORE_EN=y
CONFIG_MLX5_EN_ARFS=y
CONFIG_MLX5_EN_RXNFC=y
CONFIG_MLX5_MPFS=y
CONFIG_MLX5_ESWITCH=y
CONFIG_MLX5_CLS_ACT=y
CONFIG_MLX5_CORE_IPOIB=y
CONFIG_MLX5_FPGA_IPSEC=y
CONFIG_MLX5_IPSEC=y
CONFIG_MLX5_EN_IPSEC=y
CONFIG_MLX5_SW_STEERING=y
CONFIG_MLXSW_CORE=m
CONFIG_MLXSW_CORE_HWMON=y
CONFIG_MLXSW_CORE_THERMAL=y
CONFIG_MLXSW_PCI=m
CONFIG_MLXSW_I2C=m
CONFIG_MLXSW_SWITCHIB=m
CONFIG_MLXSW_SWITCHX2=m
CONFIG_MLXSW_SPECTRUM=m
CONFIG_MLXSW_MINIMAL=m
CONFIG_MLXFW=m
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_FEALNX is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETERION is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCOM_EMAC is not set
CONFIG_SFE_SUPPORT_IPV6=y
CONFIG_SFE_ECM=y
CONFIG_FAST_CLASSIFIER=y
# CONFIG_RMNET is not set
# CONFIG_NET_VENDOR_RDC is not set
CONFIG_NET_VENDOR_REALTEK=y
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
# CONFIG_R8126 is not set
CONFIG_R8168=m
# CONFIG_R8168_SOC_LAN is not set
# CONFIG_R8168_FIBER_SUPPORT is not set
# CONFIG_R8168_REALWOW_SUPPORT is not set
# CONFIG_R8168_DASH_SUPPORT is not set
# CONFIG_R8168_DOWN_SPEED_100 is not set
CONFIG_R8168_ASPM=y
CONFIG_R8168_DYNAMIC_ASPM=y
CONFIG_R8168_WOL_SUPPORT=y
CONFIG_R8168_S5WOL=y
# CONFIG_R8168_S5_KEEP_CURR_MAC is not set
CONFIG_R8168_EEE=y
# CONFIG_R8168_S0_MAGIC_PACKET is not set
# CONFIG_R8168_USE_FIRMWARE_FILE is not set
# CONFIG_R8168_CTAP_SHORT_OFF is not set
# CONFIG_R8168_MULTIPLE_TX_QUEUE is not set
# CONFIG_R8168_RSS_SUPPORT is not set
CONFIG_R8168_GIGA_LITE=y
# CONFIG_R8169 is not set
CONFIG_R8125=m
# CONFIG_R8125_SOC_LAN is not set
# CONFIG_R8125_REALWOW_SUPPORT is not set
# CONFIG_R8125_DASH_SUPPORT is not set
# CONFIG_R8125_DOWN_SPEED_100 is not set
CONFIG_R8125_ASPM=y
CONFIG_R8125_WOL_SUPPORT=y
CONFIG_R8125_S5WOL=y
# CONFIG_R8125_S5_KEEP_CURR_MAC is not set
CONFIG_R8125_EEE=y
# CONFIG_R8125_S0_MAGIC_PACKET is not set
CONFIG_R8125_TX_NO_CLOSE=y
CONFIG_R8125_MULTI_MSIX_VECTOR=y
CONFIG_R8125_MULTIPLE_TX_QUEUE=y
CONFIG_R8125_RSS_SUPPORT=y
# CONFIG_R8125_PTP_SUPPORT is not set
CONFIG_R8125_FIBER_SUPPORT=y
CONFIG_R8125_USE_FIRMWARE_FILE=y
# CONFIG_R8125_DOUBLE_VLAN is not set
# CONFIG_R8125_PAGE_REUSE is not set
CONFIG_R8125_GIGA_LITE=y
# CONFIG_REALTEK_PGTOOL is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
# CONFIG_STMMAC_SELFTESTS is not set
CONFIG_STMMAC_UIO=m
CONFIG_STMMAC_ETHTOOL=y
CONFIG_STMMAC_FULL=y
CONFIG_STMMAC_PLATFORM=y
# CONFIG_DWMAC_DWC_QOS_ETH is not set
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_ROCKCHIP=y
CONFIG_DWMAC_ROCKCHIP_TOOL=y
# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_NET_SB1000 is not set
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
# CONFIG_LED_TRIGGER_PHY is not set
CONFIG_FIXED_PHY=y
# CONFIG_SFP is not set

#
# Switch configuration API + drivers
#
# CONFIG_SWCONFIG is not set
# CONFIG_RTL8306_PHY is not set
# CONFIG_RTL8366_SMI is not set

#
# MII PHY device drivers
#
# CONFIG_AMD_PHY is not set
# CONFIG_ADIN_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
# CONFIG_AX88796B_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM54140_PHY is not set
CONFIG_BCM7XXX_PHY=m
# CONFIG_BCM84881_PHY is not set
# CONFIG_BCM87XX_PHY is not set
CONFIG_BCM_NET_PHYLIB=m
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
CONFIG_ICPLUS_PHY=y
CONFIG_JLSEMI_PHY=y
# CONFIG_LXT_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
CONFIG_MARVELL_PHY=m
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MICREL_PHY is not set
CONFIG_MICROCHIP_PHY=m
# CONFIG_MICROCHIP_T1_PHY is not set
CONFIG_MICROSEMI_PHY=m
CONFIG_MOTORCOMM_PHY=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
# CONFIG_AT803X_PHY is not set
# CONFIG_QSEMI_PHY is not set
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
# CONFIG_RK630_PHY is not set
CONFIG_SMSC_PHY=m
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
# CONFIG_DP83869_PHY is not set
CONFIG_VITESSE_PHY=m
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_OF_MDIO=y
CONFIG_MDIO_DEVRES=y
# CONFIG_MDIO_BITBANG is not set
CONFIG_MDIO_BCM_UNIMAC=m
CONFIG_MDIO_CAVIUM=m
# CONFIG_MDIO_HISI_FEMAC is not set
# CONFIG_MDIO_MVUSB is not set
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_OCTEON is not set
# CONFIG_MDIO_IPQ4019 is not set
# CONFIG_MDIO_IPQ8064 is not set
CONFIG_MDIO_THUNDER=m

#
# MDIO Multiplexers
#
# CONFIG_MDIO_BUS_MUX_GPIO is not set
# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
# CONFIG_MDIO_BUS_MUX_MMIOREG is not set

#
# PCS device drivers
#
CONFIG_PCS_XPCS=y
# end of PCS device drivers

CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
# CONFIG_PPP_FILTER is not set
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOATM=m
CONFIG_PPPOE=m
# CONFIG_PPTP is not set
CONFIG_PPPOL2TP=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
# CONFIG_SLIP is not set
CONFIG_SLHC=m
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_AX8817X=m
CONFIG_USB_NET_AX88179_178A=m
CONFIG_USB_NET_CDCETHER=m
CONFIG_USB_NET_CDC_EEM=m
CONFIG_USB_NET_CDC_NCM=m
CONFIG_USB_NET_HUAWEI_CDC_NCM=m
CONFIG_USB_NET_CDC_MBIM=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9700=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
CONFIG_USB_NET_CDC_SUBSET=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
# CONFIG_USB_ARMLINUX is not set
# CONFIG_USB_EPSON2888 is not set
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=m
CONFIG_USB_NET_CX82310_ETH=m
CONFIG_USB_NET_KALMIA=m
CONFIG_USB_NET_QMI_WWAN=m
CONFIG_USB_HSO=m
CONFIG_USB_NET_INT51X1=m
CONFIG_USB_IPHETH=m
CONFIG_USB_SIERRA_NET=m
CONFIG_USB_VL600=m
CONFIG_USB_NET_CH9200=m
CONFIG_USB_NET_AQC111=m
CONFIG_WLAN=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_AIC_WLAN_SUPPORT is not set
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
CONFIG_ATH_USER_REGD=y
# CONFIG_ATH_DEBUG is not set
CONFIG_ATH5K=m
# CONFIG_ATH5K_DEBUG is not set
# CONFIG_ATH5K_TRACER is not set
CONFIG_ATH5K_PCI=y
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=m
CONFIG_ATH9K_PCI=y
# CONFIG_ATH9K_AHB is not set
# CONFIG_ATH9K_DEBUGFS is not set
# CONFIG_ATH9K_DYNACK is not set
# CONFIG_ATH9K_WOW is not set
CONFIG_ATH9K_RFKILL=y
# CONFIG_ATH9K_CHANNEL_CONTEXT is not set
CONFIG_ATH9K_PCOEM=y
CONFIG_ATH9K_PCI_NO_EEPROM=y
# CONFIG_ATH9K_HTC is not set
# CONFIG_ATH9K_HWRNG is not set
CONFIG_CARL9170=m
CONFIG_CARL9170_LEDS=y
CONFIG_CARL9170_WPC=y
# CONFIG_CARL9170_HWRNG is not set
CONFIG_ATH6KL=m
# CONFIG_ATH6KL_SDIO is not set
CONFIG_ATH6KL_USB=m
# CONFIG_ATH6KL_DEBUG is not set
# CONFIG_ATH6KL_TRACING is not set
CONFIG_AR5523=m
# CONFIG_WIL6210 is not set
CONFIG_ATH10K=m
CONFIG_ATH10K_CE=y
CONFIG_ATH10K_PCI=m
# CONFIG_ATH10K_AHB is not set
# CONFIG_ATH10K_SDIO is not set
CONFIG_ATH10K_USB=m
# CONFIG_ATH10K_DEBUG is not set
# CONFIG_ATH10K_DEBUGFS is not set
CONFIG_ATH10K_LEDS=y
# CONFIG_ATH10K_TRACING is not set
CONFIG_ATH10K_THERMAL=y
CONFIG_WCN36XX=m
# CONFIG_WCN36XX_DEBUGFS is not set
CONFIG_ATH11K=m
CONFIG_ATH11K_PCI=m
# CONFIG_ATH11K_DEBUG is not set
# CONFIG_ATH11K_TRACING is not set
CONFIG_ATH12K=m
# CONFIG_ATH12K_DEBUG is not set
# CONFIG_ATH12K_TRACING is not set
# CONFIG_WLAN_VENDOR_ATMEL is not set
CONFIG_WLAN_VENDOR_BROADCOM=y
CONFIG_B43=m
CONFIG_B43_BCMA=y
CONFIG_B43_SSB=y
CONFIG_B43_BUSES_BCMA_AND_SSB=y
# CONFIG_B43_BUSES_BCMA is not set
# CONFIG_B43_BUSES_SSB is not set
CONFIG_B43_PCI_AUTOSELECT=y
CONFIG_B43_PCICORE_AUTOSELECT=y
# CONFIG_B43_SDIO is not set
CONFIG_B43_BCMA_PIO=y
CONFIG_B43_PIO=y
CONFIG_B43_PHY_G=y
CONFIG_B43_PHY_N=y
CONFIG_B43_PHY_LP=y
CONFIG_B43_PHY_HT=y
CONFIG_B43_LEDS=y
CONFIG_B43_HWRNG=y
# CONFIG_B43_DEBUG is not set
CONFIG_B43LEGACY=m
CONFIG_B43LEGACY_PCI_AUTOSELECT=y
CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
CONFIG_B43LEGACY_LEDS=y
CONFIG_B43LEGACY_HWRNG=y
CONFIG_B43LEGACY_DEBUG=y
CONFIG_B43LEGACY_DMA=y
CONFIG_B43LEGACY_PIO=y
CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
# CONFIG_B43LEGACY_DMA_MODE is not set
# CONFIG_B43LEGACY_PIO_MODE is not set
CONFIG_BRCMUTIL=m
CONFIG_BRCMFMAC=m
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_PROTO_MSGBUF=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
CONFIG_BRCMFMAC_PCIE=y
# CONFIG_BRCMFMAC_BT_SHARED_SDIO is not set
CONFIG_BRCM_TRACING=y
# CONFIG_BRCMDBG is not set
# CONFIG_BRCMFMAC_PCIE_BARWIN_SZ is not set
# CONFIG_WLAN_VENDOR_CISCO is not set
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_IPW2100=m
# CONFIG_IPW2100_MONITOR is not set
# CONFIG_IPW2100_DEBUG is not set
CONFIG_IPW2200=m
# CONFIG_IPW2200_MONITOR is not set
# CONFIG_IPW2200_QOS is not set
# CONFIG_IPW2200_DEBUG is not set
CONFIG_LIBIPW=m
# CONFIG_LIBIPW_DEBUG is not set
CONFIG_IWLEGACY=m
CONFIG_IWL4965=m
CONFIG_IWL3945=m

#
# iwl3945 / iwl4965 Debugging Options
#
# CONFIG_IWLEGACY_DEBUG is not set
# end of iwl3945 / iwl4965 Debugging Options

CONFIG_IWLWIFI=m
CONFIG_IWLWIFI_LEDS=y
CONFIG_IWLDVM=m
CONFIG_IWLMVM=m
CONFIG_IWLWIFI_OPMODE_MODULAR=y

#
# Debugging Options
#
# CONFIG_IWLWIFI_DEBUG is not set
# CONFIG_IWLWIFI_DEVICE_TRACING is not set
# end of Debugging Options

# CONFIG_WLAN_VENDOR_INTERSIL is not set
CONFIG_WLAN_VENDOR_MARVELL=y
# CONFIG_LIBERTAS is not set
# CONFIG_LIBERTAS_THINFIRM is not set
# CONFIG_MWIFIEX is not set
CONFIG_MWL8K=m
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=m
CONFIG_MT76_CORE=m
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=m
CONFIG_MT76_SDIO=m
CONFIG_MT76x02_LIB=m
CONFIG_MT76x02_USB=m
CONFIG_MT76_CONNAC_LIB=m
CONFIG_MT76x0_COMMON=m
CONFIG_MT76x0U=m
CONFIG_MT76x0E=m
CONFIG_MT76x2_COMMON=m
CONFIG_MT76x2E=m
CONFIG_MT76x2U=m
CONFIG_MT7603E=m
CONFIG_MT7615_COMMON=m
CONFIG_MT7615E=m
CONFIG_MT7663_USB_SDIO_COMMON=m
CONFIG_MT7663U=m
CONFIG_MT7663S=m
CONFIG_MT7915E=m
CONFIG_MT7921_COMMON=m
CONFIG_MT7921E=m
CONFIG_MT7921S=m
CONFIG_MT7921U=m
CONFIG_MT7996E=m
# CONFIG_WLAN_VENDOR_MICROCHIP is not set
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=m
CONFIG_RT2400PCI=m
CONFIG_RT2500PCI=m
CONFIG_RT61PCI=m
CONFIG_RT2800PCI=m
CONFIG_RT2800PCI_RT33XX=y
CONFIG_RT2800PCI_RT35XX=y
CONFIG_RT2800PCI_RT53XX=y
CONFIG_RT2800PCI_RT3290=y
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
CONFIG_RT2800USB_RT33XX=y
CONFIG_RT2800USB_RT35XX=y
CONFIG_RT2800USB_RT3573=y
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
# CONFIG_RT2800USB_UNKNOWN is not set
CONFIG_RT2800_LIB=m
CONFIG_RT2800_LIB_MMIO=m
CONFIG_RT2X00_LIB_MMIO=m
CONFIG_RT2X00_LIB_PCI=m
CONFIG_RT2X00_LIB_USB=m
CONFIG_RT2X00_LIB=m
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
# CONFIG_RT2X00_DEBUG is not set
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_RTL8180=m
CONFIG_RTL8187=m
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=m
CONFIG_RTL8192CE=m
CONFIG_RTL8192SE=m
CONFIG_RTL8192DE=m
CONFIG_RTL8723AE=m
CONFIG_RTL8723BE=m
CONFIG_RTL8188EE=m
CONFIG_RTL8192EE=m
CONFIG_RTL8821AE=m
CONFIG_RTL8192CU=m
CONFIG_RTLWIFI=m
CONFIG_RTLWIFI_PCI=m
CONFIG_RTLWIFI_USB=m
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8723_COMMON=m
CONFIG_RTLBTCOEXIST=m
CONFIG_RTL8XXXU=m
# CONFIG_RTL8XXXU_UNTESTED is not set
CONFIG_RTW88=m
CONFIG_RTW88_CORE=m
CONFIG_RTW88_PCI=m
CONFIG_RTW88_SDIO=m
CONFIG_RTW88_USB=m
CONFIG_RTW88_8822B=m
CONFIG_RTW88_8822C=m
CONFIG_RTW88_8723D=m
CONFIG_RTW88_8821C=m
CONFIG_RTW88_8822BE=m
CONFIG_RTW88_8822BS=m
CONFIG_RTW88_8822BU=m
CONFIG_RTW88_8822CE=m
CONFIG_RTW88_8822CS=m
CONFIG_RTW88_8822CU=m
CONFIG_RTW88_8723DE=m
CONFIG_RTW88_8723DS=m
CONFIG_RTW88_8723DU=m
CONFIG_RTW88_8821CE=m
CONFIG_RTW88_8821CS=m
CONFIG_RTW88_8821CU=m
# CONFIG_RTW88_DEBUG is not set
# CONFIG_RTW88_DEBUGFS is not set
CONFIG_RTW89=m
CONFIG_RTW89_CORE=m
CONFIG_RTW89_PCI=m
CONFIG_RTW89_8851B=m
CONFIG_RTW89_8852A=m
CONFIG_RTW89_8852B=m
CONFIG_RTW89_8852C=m
CONFIG_RTW89_8851BE=m
CONFIG_RTW89_8852AE=m
CONFIG_RTW89_8852BE=m
CONFIG_RTW89_8852CE=m
# CONFIG_RTW89_DEBUGMSG is not set
# CONFIG_RTW89_DEBUGFS is not set
# CONFIG_WLAN_VENDOR_RSI is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
# CONFIG_WLAN_VENDOR_ZYDAS is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
CONFIG_WL_ROCKCHIP=m
CONFIG_WIFI_BUILD_MODULE=y
# CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP is not set
# CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR is not set
CONFIG_BCMDHD=y
CONFIG_AP6XXX=m
# CONFIG_BCMDHD_SDIO is not set
CONFIG_BCMDHD_PCIE=y
CONFIG_BCMDHD_FW_PATH="/lib/firmware/ap6275p/fw_bcmdhd.bin"
CONFIG_BCMDHD_NVRAM_PATH="/lib/firmware/ap6275p/nvram.txt"
# CONFIG_BCMDHD_STATIC_IF is not set
# CONFIG_CYW_BCMDHD is not set
# CONFIG_INFINEON_DHD is not set
CONFIG_USB_NET_RNDIS_WLAN=m
# CONFIG_MAC80211_HWSIM is not set
CONFIG_VIRT_WIFI=m

#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
CONFIG_IEEE802154_AT86RF230=m
# CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set
CONFIG_IEEE802154_MRF24J40=m
CONFIG_IEEE802154_CC2520=m
CONFIG_IEEE802154_ATUSB=m
CONFIG_IEEE802154_ADF7242=m
CONFIG_IEEE802154_CA8210=m
# CONFIG_IEEE802154_CA8210_DEBUGFS is not set
CONFIG_IEEE802154_MCR20A=m
CONFIG_IEEE802154_HWSIM=m
# CONFIG_VMXNET3 is not set
# CONFIG_FUJITSU_ES is not set
# CONFIG_LTE is not set
CONFIG_NETDEVSIM=m
CONFIG_NET_FAILOVER=m
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
CONFIG_INPUT_MATRIXKMAP=m

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ADC=y
CONFIG_KEYBOARD_ADP5588=m
CONFIG_KEYBOARD_ADP5589=m
CONFIG_KEYBOARD_ATKBD=m
CONFIG_KEYBOARD_QT1050=m
CONFIG_KEYBOARD_QT1070=m
CONFIG_KEYBOARD_QT2160=m
CONFIG_KEYBOARD_DLINK_DIR685=m
CONFIG_KEYBOARD_LKKBD=m
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_GPIO_BUTTON_HOTPLUG is not set
CONFIG_KEYBOARD_GPIO_POLLED=y
CONFIG_KEYBOARD_TCA6416=m
CONFIG_KEYBOARD_TCA8418=m
CONFIG_KEYBOARD_MATRIX=m
CONFIG_KEYBOARD_LM8323=m
CONFIG_KEYBOARD_LM8333=m
CONFIG_KEYBOARD_MAX7359=m
CONFIG_KEYBOARD_MCS=m
CONFIG_KEYBOARD_MPR121=m
CONFIG_KEYBOARD_NEWTON=m
CONFIG_KEYBOARD_OPENCORES=m
CONFIG_KEYBOARD_SAMSUNG=m
CONFIG_KEYBOARD_STOWAWAY=m
CONFIG_KEYBOARD_SUNKBD=m
CONFIG_KEYBOARD_OMAP4=m
CONFIG_KEYBOARD_TM2_TOUCHKEY=m
CONFIG_KEYBOARD_XTKBD=m
CONFIG_KEYBOARD_CAP11XX=m
CONFIG_KEYBOARD_BCM=m
CONFIG_INPUT_MOUSE=y
# CONFIG_MOUSE_PS2 is not set
# CONFIG_MOUSE_SERIAL is not set
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=m
CONFIG_MOUSE_ELAN_I2C=m
CONFIG_MOUSE_ELAN_I2C_I2C=y
# CONFIG_MOUSE_ELAN_I2C_SMBUS is not set
# CONFIG_MOUSE_VSXXXAA is not set
CONFIG_MOUSE_GPIO=m
CONFIG_MOUSE_SYNAPTICS_I2C=m
CONFIG_MOUSE_SYNAPTICS_USB=m
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_ANALOG=m
CONFIG_JOYSTICK_A3D=m
CONFIG_JOYSTICK_ADC=m
CONFIG_JOYSTICK_ADI=m
CONFIG_JOYSTICK_COBRA=m
CONFIG_JOYSTICK_GF2K=m
CONFIG_JOYSTICK_GRIP=m
CONFIG_JOYSTICK_GRIP_MP=m
CONFIG_JOYSTICK_GUILLEMOT=m
CONFIG_JOYSTICK_INTERACT=m
CONFIG_JOYSTICK_SIDEWINDER=m
CONFIG_JOYSTICK_TMDC=m
CONFIG_JOYSTICK_IFORCE=m
CONFIG_JOYSTICK_IFORCE_USB=m
CONFIG_JOYSTICK_IFORCE_232=m
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
CONFIG_JOYSTICK_STINGER=m
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
CONFIG_JOYSTICK_AS5011=m
CONFIG_JOYSTICK_JOYDUMP=m
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_JOYSTICK_PSXPAD_SPI=m
CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
CONFIG_JOYSTICK_PXRC=m
CONFIG_JOYSTICK_FSIA6B=m
CONFIG_INPUT_TABLET=y
CONFIG_TABLET_USB_ACECAD=m
CONFIG_TABLET_USB_AIPTEK=m
CONFIG_TABLET_USB_GTCO=m
CONFIG_TABLET_USB_HANWANG=m
CONFIG_TABLET_USB_KBTAB=m
CONFIG_TABLET_USB_PEGASUS=m
CONFIG_TABLET_SERIAL_WACOM4=m
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_PROPERTIES=y
CONFIG_TOUCHSCREEN_ADS7846=m
CONFIG_TOUCHSCREEN_AD7877=m
CONFIG_TOUCHSCREEN_AD7879=m
CONFIG_TOUCHSCREEN_AD7879_I2C=m
CONFIG_TOUCHSCREEN_AD7879_SPI=m
CONFIG_TOUCHSCREEN_ADC=m
CONFIG_TOUCHSCREEN_AR1021_I2C=m
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set
CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
CONFIG_TOUCHSCREEN_BU21013=m
CONFIG_TOUCHSCREEN_BU21029=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
CONFIG_TOUCHSCREEN_CY8CTMA140=m
CONFIG_TOUCHSCREEN_CY8CTMG110=m
CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
CONFIG_TOUCHSCREEN_DYNAPRO=m
CONFIG_TOUCHSCREEN_HAMPSHIRE=m
CONFIG_TOUCHSCREEN_EETI=m
CONFIG_TOUCHSCREEN_EGALAX=m
CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
CONFIG_TOUCHSCREEN_EXC3000=m
CONFIG_TOUCHSCREEN_FTS=y
CONFIG_TOUCHSCREEN_FUJITSU=m
CONFIG_TOUCHSCREEN_GOODIX=m
CONFIG_TOUCHSCREEN_GSL3673=y
CONFIG_TOUCHSCREEN_GSL3673_800X1280=m
CONFIG_TOUCHSCREEN_GSLX680_PAD=m
CONFIG_TOUCHSCREEN_GT1X=y
CONFIG_TOUCHSCREEN_GT9XX=m
CONFIG_TOUCHSCREEN_HIDEEP=m
CONFIG_TOUCHSCREEN_ILI210X=m
CONFIG_TOUCHSCREEN_S6SY761=m
CONFIG_TOUCHSCREEN_GUNZE=m
CONFIG_TOUCHSCREEN_EKTF2127=m
CONFIG_TOUCHSCREEN_ELAN=y
CONFIG_TOUCHSCREEN_ELAN5515=m
CONFIG_TOUCHSCREEN_ELO=m
CONFIG_TOUCHSCREEN_WACOM_W8001=m
CONFIG_TOUCHSCREEN_WACOM_I2C=m
CONFIG_TOUCHSCREEN_MAX11801=m
CONFIG_TOUCHSCREEN_MCS5000=m
CONFIG_TOUCHSCREEN_MMS114=m
CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
CONFIG_TOUCHSCREEN_MTOUCH=m
CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
CONFIG_TOUCHSCREEN_INEXIO=m
CONFIG_TOUCHSCREEN_MK712=m
CONFIG_TOUCHSCREEN_PENMOUNT=m
CONFIG_TOUCHSCREEN_EDT_FT5X06=m
CONFIG_TOUCHSCREEN_RASPITS_FT5426=m
CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
CONFIG_TOUCHSCREEN_TOUCHWIN=m
CONFIG_TOUCHSCREEN_PIXCIR=m
CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
CONFIG_TOUCHSCREEN_WM97XX=m
CONFIG_TOUCHSCREEN_WM9705=y
CONFIG_TOUCHSCREEN_WM9712=y
CONFIG_TOUCHSCREEN_WM9713=y
CONFIG_TOUCHSCREEN_USB_COMPOSITE=y
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
CONFIG_TOUCHSCREEN_TOUCHIT213=m
CONFIG_TOUCHSCREEN_TSC_SERIO=m
CONFIG_TOUCHSCREEN_TSC200X_CORE=m
CONFIG_TOUCHSCREEN_TSC2004=m
CONFIG_TOUCHSCREEN_TSC2005=m
CONFIG_TOUCHSCREEN_TSC2007=m
# CONFIG_TOUCHSCREEN_TSC2007_IIO is not set
CONFIG_TOUCHSCREEN_RM_TS=m
CONFIG_TOUCHSCREEN_SILEAD=m
CONFIG_TOUCHSCREEN_SIS_I2C=m
CONFIG_TOUCHSCREEN_ST1232=m
CONFIG_TOUCHSCREEN_STMFTS=m
CONFIG_TOUCHSCREEN_SUR40=m
CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
CONFIG_TOUCHSCREEN_SX8654=m
CONFIG_TOUCHSCREEN_TPS6507X=m
CONFIG_TOUCHSCREEN_ZET6223=m
CONFIG_TOUCHSCREEN_ZFORCE=m
CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
CONFIG_TOUCHSCREEN_ROHM_BU21023=m
CONFIG_TOUCHSCREEN_IQS5XX=m
CONFIG_TOUCHSCREEN_ZINITIX=m
CONFIG_ROCKCHIP_REMOTECTL=y
CONFIG_ROCKCHIP_REMOTECTL_PWM=y

#
# handle all sensors
#
# CONFIG_SENSOR_DEVICE is not set
CONFIG_INPUT_MISC=y
CONFIG_INPUT_AD714X=m
CONFIG_INPUT_AD714X_I2C=m
CONFIG_INPUT_AD714X_SPI=m
CONFIG_INPUT_ATMEL_CAPTOUCH=m
CONFIG_INPUT_BMA150=m
CONFIG_INPUT_E3X0_BUTTON=m
CONFIG_INPUT_MMA8450=m
CONFIG_INPUT_GPIO_BEEPER=m
CONFIG_INPUT_GPIO_DECODER=m
CONFIG_INPUT_GPIO_VIBRA=m
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
CONFIG_INPUT_KXTJ9=m
CONFIG_INPUT_POWERMATE=m
CONFIG_INPUT_YEALINK=m
CONFIG_INPUT_CM109=m
CONFIG_INPUT_REGULATOR_HAPTIC=m
CONFIG_INPUT_UINPUT=y
CONFIG_INPUT_PCF8574=m
CONFIG_INPUT_PWM_BEEPER=m
CONFIG_INPUT_PWM_VIBRA=m
CONFIG_INPUT_RK805_PWRKEY=y
CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
CONFIG_INPUT_ADXL34X=m
CONFIG_INPUT_ADXL34X_I2C=m
CONFIG_INPUT_ADXL34X_SPI=m
CONFIG_INPUT_IMS_PCU=m
CONFIG_INPUT_IQS269A=m
CONFIG_INPUT_CMA3000=m
CONFIG_INPUT_CMA3000_I2C=m
CONFIG_INPUT_SOC_BUTTON_ARRAY=m
CONFIG_INPUT_DRV260X_HAPTICS=m
CONFIG_INPUT_DRV2665_HAPTICS=m
CONFIG_INPUT_DRV2667_HAPTICS=m
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=m
CONFIG_RMI4_SPI=m
CONFIG_RMI4_SMB=m
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=y
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
CONFIG_RMI4_F3A=y
CONFIG_RMI4_F54=y
CONFIG_RMI4_F55=y

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=m
CONFIG_SERIO_AMBAKMI=m
CONFIG_SERIO_PCIPS2=m
CONFIG_SERIO_LIBPS2=m
CONFIG_SERIO_RAW=m
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
CONFIG_GAMEPORT=m
# CONFIG_GAMEPORT_NS558 is not set
# CONFIG_GAMEPORT_L4 is not set
# CONFIG_GAMEPORT_EMU10K1 is not set
# CONFIG_GAMEPORT_FM801 is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_PNP=y
CONFIG_SERIAL_8250_16550A_VARIANTS=y
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=10
CONFIG_SERIAL_8250_RUNTIME_UARTS=10
# CONFIG_SERIAL_8250_EXTENDED is not set
# CONFIG_SERIAL_8250_ASPEED_VUART is not set
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
CONFIG_SERIAL_AMBA_PL010=m
CONFIG_SERIAL_AMBA_PL011=m
# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
# CONFIG_SERIAL_SAMSUNG is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_MSM_GENI_EARLY_CONSOLE is not set
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_IFX6X60 is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_NOZOMI is not set
# CONFIG_NULL_TTY is not set
# CONFIG_TRACE_SINK is not set
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
# CONFIG_SERIAL_DEV_BUS is not set
# CONFIG_TTY_PRINTK is not set
CONFIG_VIRTIO_CONSOLE=m
# CONFIG_IPMI_HANDLER is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
# CONFIG_HW_RANDOM_BA431 is not set
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_HISI_V2=y
CONFIG_HW_RANDOM_OPTEE=y
# CONFIG_HW_RANDOM_CCTRNG is not set
# CONFIG_HW_RANDOM_XIPHERA is not set
CONFIG_HW_RANDOM_ROCKCHIP=y
# CONFIG_APPLICOM is not set
CONFIG_DEVMEM=y
# CONFIG_RAW_DRIVER is not set
CONFIG_DEVPORT=y
CONFIG_TCG_TPM=y
CONFIG_HW_RANDOM_TPM=y
# CONFIG_TCG_TIS is not set
# CONFIG_TCG_TIS_SPI is not set
# CONFIG_TCG_TIS_I2C_ATMEL is not set
CONFIG_TCG_TIS_I2C_INFINEON=y
# CONFIG_TCG_TIS_I2C_NUVOTON is not set
# CONFIG_TCG_ATMEL is not set
# CONFIG_TCG_INFINEON is not set
# CONFIG_TCG_CRB is not set
# CONFIG_TCG_VTPM_PROXY is not set
# CONFIG_TCG_FTPM_TEE is not set
# CONFIG_TCG_TIS_ST33ZP24_I2C is not set
# CONFIG_TCG_TIS_ST33ZP24_SPI is not set
# CONFIG_XILLYBUS is not set
# CONFIG_RANDOM_TRUST_CPU is not set
# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
# CONFIG_I2C_MUX_GPIO is not set
# CONFIG_I2C_MUX_GPMUX is not set
# CONFIG_I2C_MUX_LTC4306 is not set
# CONFIG_I2C_MUX_PCA9541 is not set
# CONFIG_I2C_MUX_PCA954x is not set
CONFIG_I2C_MUX_PINCTRL=m
CONFIG_I2C_MUX_REG=m
CONFIG_I2C_DEMUX_PINCTRL=m
# CONFIG_I2C_MUX_MLXCPLD is not set
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_ALGOBIT=y

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set

#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CADENCE is not set
# CONFIG_I2C_CBUS_GPIO is not set
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
# CONFIG_I2C_DESIGNWARE_PCI is not set
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=m
# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
CONFIG_I2C_RK3X=y
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_THUNDERX is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
CONFIG_I2C_TINY_USB=m

#
# Other I2C/SMBus bus drivers
#
# end of I2C Hardware Bus support

# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=m
CONFIG_I2C_SLAVE_TESTUNIT=m
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

# CONFIG_I3C is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y

#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
CONFIG_SPI_BITBANG=y
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_HISI_SFC_V3XX is not set
# CONFIG_SPI_NXP_FLEXSPI is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PL022 is not set
# CONFIG_SPI_PXA2XX is not set
CONFIG_SPI_ROCKCHIP=y
# CONFIG_SPI_ROCKCHIP_MISCDEV is not set
CONFIG_SPI_ROCKCHIP_SFC=y
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_THUNDERX is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_SPI_AMD is not set

#
# SPI Multiplexer support
#
# CONFIG_SPI_MUX is not set

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_LOOPBACK_TEST is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_DYNAMIC=y
# CONFIG_SPMI is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set

#
# PPS clients support
#
CONFIG_PPS_CLIENT_KTIMER=m
# CONFIG_PPS_CLIENT_LDISC is not set
CONFIG_PPS_CLIENT_GPIO=m

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
# CONFIG_DP83640_PHY is not set
# CONFIG_PTP_1588_CLOCK_INES is not set
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_PINCTRL_AMD is not set
# CONFIG_PINCTRL_MCP23S08 is not set
CONFIG_PINCTRL_ROCKCHIP=y
# CONFIG_PINCTRL_SINGLE is not set
# CONFIG_PINCTRL_SX150X is not set
# CONFIG_PINCTRL_STMFX is not set
CONFIG_PINCTRL_RK628=m
CONFIG_PINCTRL_RK805=y
CONFIG_PINCTRL_RK806=y
# CONFIG_PINCTRL_OCELOT is not set

#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers

CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_FTGPIO010 is not set
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_LOGICVC is not set
# CONFIG_GPIO_MB86S7X is not set
# CONFIG_GPIO_PL061 is not set
CONFIG_GPIO_ROCKCHIP=y
# CONFIG_GPIO_SAMA5D2_PIOBU is not set
# CONFIG_GPIO_SIFIVE is not set
# CONFIG_GPIO_SYSCON is not set
# CONFIG_GPIO_XGENE is not set
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
# CONFIG_GPIO_ADP5588 is not set
# CONFIG_GPIO_ADNP is not set
# CONFIG_GPIO_AW9110 is not set
# CONFIG_GPIO_GW_PLD is not set
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_NCA9539 is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCA9570 is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_TPIC2810 is not set
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
# CONFIG_GPIO_TPS6586X is not set
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set
# end of PCI GPIO expanders

#
# SPI GPIO expanders
#
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
# end of USB GPIO expanders

# CONFIG_GPIO_AGGREGATOR is not set
# CONFIG_GPIO_MOCKUP is not set
CONFIG_W1=m
CONFIG_W1_CON=y

#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_MATROX=m
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
CONFIG_W1_MASTER_DS1WM=m
CONFIG_W1_MASTER_GPIO=m
# CONFIG_W1_MASTER_SGI is not set
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
# CONFIG_W1_SLAVE_DS2405 is not set
CONFIG_W1_SLAVE_DS2408=m
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
# CONFIG_W1_SLAVE_DS2805 is not set
# CONFIG_W1_SLAVE_DS2430 is not set
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
# CONFIG_W1_SLAVE_DS2438 is not set
# CONFIG_W1_SLAVE_DS250X is not set
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
# CONFIG_W1_SLAVE_DS28E17 is not set
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_BRCMSTB is not set
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
# CONFIG_POWER_RESET_LTC2952 is not set
# CONFIG_POWER_RESET_RESTART is not set
# CONFIG_POWER_RESET_XGENE is not set
# CONFIG_POWER_RESET_SYSCON is not set
# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
# CONFIG_NVMEM_REBOOT_MODE is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_PDA_POWER is not set
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_CW2015 is not set
CONFIG_BATTERY_CW2017=m
# CONFIG_BATTERY_CW221X is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
CONFIG_BATTERY_SBS=m
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_BATTERY_MAX1721X is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
CONFIG_CHARGER_GPIO=m
# CONFIG_CHARGER_MANAGER is not set
CONFIG_ROCKCHIP_CHARGER_MANAGER=m
# CONFIG_CHARGER_LT3651 is not set
# CONFIG_CHARGER_SC8551 is not set
# CONFIG_CHARGER_SC89890 is not set
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
CONFIG_CHARGER_BQ24735=m
# CONFIG_CHARGER_BQ2515X is not set
CONFIG_CHARGER_BQ25700=m
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_BQ25980 is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
CONFIG_BATTERY_RT5033=m
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
CONFIG_BATTERY_RK816=m
CONFIG_BATTERY_RK817=m
CONFIG_CHARGER_RK817=m
CONFIG_BATTERY_RK818=m
CONFIG_CHARGER_RK818=m
# CONFIG_CHARGER_SGM41542 is not set
CONFIG_HWMON=y
CONFIG_HWMON_VID=m
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM1177 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7310 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_AS370 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
CONFIG_SENSORS_ARM_SCMI=m
CONFIG_SENSORS_ASPEED=m
CONFIG_SENSORS_ATXP1=m
CONFIG_SENSORS_CORSAIR_CPRO=m
CONFIG_SENSORS_DRIVETEMP=m
CONFIG_SENSORS_DS620=m
CONFIG_SENSORS_DS1621=m
CONFIG_SENSORS_I5K_AMB=m
CONFIG_SENSORS_F71805F=m
CONFIG_SENSORS_F71882FG=m
CONFIG_SENSORS_F75375S=m
CONFIG_SENSORS_FTSTEUTATES=m
CONFIG_SENSORS_GL518SM=m
CONFIG_SENSORS_GL520SM=m
CONFIG_SENSORS_G760A=m
CONFIG_SENSORS_G762=m
CONFIG_SENSORS_GPIO_FAN=m
CONFIG_SENSORS_HIH6130=m
CONFIG_SENSORS_IIO_HWMON=m
CONFIG_SENSORS_IT87=m
CONFIG_SENSORS_JC42=m
CONFIG_SENSORS_POWR1220=m
CONFIG_SENSORS_LINEAGE=m
CONFIG_SENSORS_LTC2945=m
CONFIG_SENSORS_LTC2947=m
CONFIG_SENSORS_LTC2947_I2C=m
CONFIG_SENSORS_LTC2947_SPI=m
CONFIG_SENSORS_LTC2990=m
CONFIG_SENSORS_LTC4151=m
CONFIG_SENSORS_LTC4215=m
CONFIG_SENSORS_LTC4222=m
CONFIG_SENSORS_LTC4245=m
CONFIG_SENSORS_LTC4260=m
CONFIG_SENSORS_LTC4261=m
# CONFIG_SENSORS_MAX1111 is not set
CONFIG_SENSORS_MAX16065=m
CONFIG_SENSORS_MAX1619=m
CONFIG_SENSORS_MAX1668=m
CONFIG_SENSORS_MAX197=m
CONFIG_SENSORS_MAX31722=m
CONFIG_SENSORS_MAX31730=m
CONFIG_SENSORS_MAX6621=m
CONFIG_SENSORS_MAX6639=m
CONFIG_SENSORS_MAX6642=m
CONFIG_SENSORS_MAX6650=m
CONFIG_SENSORS_MAX6697=m
CONFIG_SENSORS_MAX31790=m
CONFIG_SENSORS_MCP3021=m
CONFIG_SENSORS_TC654=m
CONFIG_SENSORS_MR75203=m
CONFIG_SENSORS_ADCXX=m
CONFIG_SENSORS_LM63=m
CONFIG_SENSORS_LM70=m
CONFIG_SENSORS_LM73=m
CONFIG_SENSORS_LM75=m
CONFIG_SENSORS_LM77=m
CONFIG_SENSORS_LM78=m
CONFIG_SENSORS_LM80=m
CONFIG_SENSORS_LM83=m
CONFIG_SENSORS_LM85=m
CONFIG_SENSORS_LM87=m
CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_LM92=m
CONFIG_SENSORS_LM93=m
CONFIG_SENSORS_LM95234=m
CONFIG_SENSORS_LM95241=m
CONFIG_SENSORS_LM95245=m
CONFIG_SENSORS_PC87360=m
CONFIG_SENSORS_PC87427=m
CONFIG_SENSORS_NTC_THERMISTOR=m
CONFIG_SENSORS_NCT6683=m
CONFIG_SENSORS_NCT6775=m
CONFIG_SENSORS_NCT7802=m
CONFIG_SENSORS_NCT7904=m
CONFIG_SENSORS_NPCM7XX=m
CONFIG_SENSORS_OCC_P8_I2C=m
CONFIG_SENSORS_OCC=m
CONFIG_SENSORS_PCF8591=m
CONFIG_PMBUS=m
CONFIG_SENSORS_PMBUS=m
# CONFIG_SENSORS_ADM1266 is not set
# CONFIG_SENSORS_ADM1275 is not set
# CONFIG_SENSORS_BEL_PFE is not set
# CONFIG_SENSORS_IBM_CFFPS is not set
# CONFIG_SENSORS_INSPUR_IPSPS is not set
# CONFIG_SENSORS_IR35221 is not set
# CONFIG_SENSORS_IR38064 is not set
# CONFIG_SENSORS_IRPS5401 is not set
# CONFIG_SENSORS_ISL68137 is not set
# CONFIG_SENSORS_LM25066 is not set
# CONFIG_SENSORS_LTC2978 is not set
# CONFIG_SENSORS_LTC3815 is not set
# CONFIG_SENSORS_MAX16064 is not set
# CONFIG_SENSORS_MAX16601 is not set
# CONFIG_SENSORS_MAX20730 is not set
# CONFIG_SENSORS_MAX20751 is not set
# CONFIG_SENSORS_MAX31785 is not set
# CONFIG_SENSORS_MAX34440 is not set
# CONFIG_SENSORS_MAX8688 is not set
# CONFIG_SENSORS_MP2975 is not set
# CONFIG_SENSORS_PXE1610 is not set
# CONFIG_SENSORS_TPS40422 is not set
# CONFIG_SENSORS_TPS53679 is not set
# CONFIG_SENSORS_UCD9000 is not set
# CONFIG_SENSORS_UCD9200 is not set
# CONFIG_SENSORS_XDPE122 is not set
# CONFIG_SENSORS_ZL6100 is not set
CONFIG_SENSORS_PWM_FAN=m
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
CONFIG_SENSORS_EMC2305=m
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_TMP513 is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_XGENE is not set

#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
# CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE is not set
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR=y
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
# CONFIG_THERMAL_EMULATION is not set
# CONFIG_THERMAL_MMIO is not set
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_RK_VIRTUAL_THERMAL=y
# CONFIG_GENERIC_ADC_THERMAL is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_GPIO_WATCHDOG is not set
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
# CONFIG_ARM_SP805_WATCHDOG is not set
# CONFIG_ARM_SBSA_WATCHDOG is not set
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=y
# CONFIG_MAX63XX_WATCHDOG is not set
# CONFIG_ARM_SMC_WATCHDOG is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_MEN_A21_WDT is not set

#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB=m
CONFIG_SSB_SPROM=y
CONFIG_SSB_BLOCKIO=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_PCIHOST=y
CONFIG_SSB_B43_PCI_BRIDGE=y
CONFIG_SSB_SDIOHOST_POSSIBLE=y
# CONFIG_SSB_SDIOHOST is not set
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
CONFIG_SSB_DRIVER_PCICORE=y
# CONFIG_SSB_DRIVER_GPIO is not set
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_BLOCKIO=y
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
CONFIG_BCMA_HOST_PCI=y
# CONFIG_BCMA_HOST_SOC is not set
CONFIG_BCMA_DRIVER_PCI=y
# CONFIG_BCMA_DRIVER_GMAC_CMN is not set
# CONFIG_BCMA_DRIVER_GPIO is not set
# CONFIG_BCMA_DEBUG is not set

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AXP20X_I2C is not set
# CONFIG_MFD_MADERA is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MAX96745 is not set
# CONFIG_MFD_MAX96755F is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_UCB1400_CORE is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RC5T583 is not set
CONFIG_MFD_RK618=m
CONFIG_MFD_RK628=m
# CONFIG_MFD_RK630 is not set
# CONFIG_MFD_RK630_I2C is not set
# CONFIG_MFD_RK630_SPI is not set
CONFIG_MFD_RK806=y
CONFIG_MFD_RK806_SPI=y
CONFIG_MFD_RK808=y
CONFIG_MFD_RK1000=m

#
# driver for different display serdes
#
CONFIG_MFD_SERDES_DISPLAY=m
CONFIG_SERDES_DISPLAY_CHIP_MAXIM=m
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96745=m
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96752=m
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96755=m
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96772=m
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96789=m
CONFIG_SERDES_DISPLAY_CHIP_ROHM=m
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18TL82=m
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18RL82=m
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP=m
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP_RKX111=m
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP_RKX121=m
CONFIG_SERDES_DISPLAY_CHIP_NOVO=m
CONFIG_SERDES_DISPLAY_CHIP_NOVO_NCA9539=m
CONFIG_MFD_RKX110_X120=m
CONFIG_ROCKCHIP_SERDES_DRM_PANEL=m
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
CONFIG_MFD_TPS6586X=y
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS80031 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TQMX86 is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
# CONFIG_MFD_ROHM_BD70528 is not set
# CONFIG_MFD_ROHM_BD71828 is not set
# CONFIG_MFD_STPMIC1 is not set
# CONFIG_MFD_STMFX is not set
# CONFIG_MFD_KHADAS_MCU is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
CONFIG_REGULATOR_USERSPACE_CONSUMER=m
CONFIG_REGULATOR_88PG86X=m
CONFIG_REGULATOR_ACT8865=m
CONFIG_REGULATOR_AD5398=m
CONFIG_REGULATOR_ARM_SCMI=y
CONFIG_REGULATOR_DA9210=m
CONFIG_REGULATOR_DA9211=m
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_FAN53880=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_ISL9305=m
CONFIG_REGULATOR_ISL6271A=m
CONFIG_REGULATOR_LP3971=m
CONFIG_REGULATOR_LP3972=m
CONFIG_REGULATOR_LP872X=m
CONFIG_REGULATOR_LP8752=m
CONFIG_REGULATOR_LP8755=m
CONFIG_REGULATOR_LTC3589=m
CONFIG_REGULATOR_LTC3676=m
CONFIG_REGULATOR_MAX1586=m
CONFIG_REGULATOR_MAX8649=m
CONFIG_REGULATOR_MAX8660=m
CONFIG_REGULATOR_MAX8952=m
CONFIG_REGULATOR_MAX8973=m
CONFIG_REGULATOR_MAX77826=m
CONFIG_REGULATOR_MCP16502=m
CONFIG_REGULATOR_MP5416=m
CONFIG_REGULATOR_MP8859=m
CONFIG_REGULATOR_MP8865=m
CONFIG_REGULATOR_MP886X=m
CONFIG_REGULATOR_MPQ7920=m
CONFIG_REGULATOR_MT6311=m
CONFIG_REGULATOR_PCA9450=m
CONFIG_REGULATOR_PFUZE100=m
CONFIG_REGULATOR_PV88060=m
CONFIG_REGULATOR_PV88080=m
CONFIG_REGULATOR_PV88090=m
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
CONFIG_REGULATOR_RK806=y
CONFIG_REGULATOR_RK808=y
CONFIG_REGULATOR_RK860X=y
CONFIG_REGULATOR_RT4801=m
CONFIG_REGULATOR_RTMV20=m
CONFIG_REGULATOR_SLG51000=m
CONFIG_REGULATOR_SY8106A=m
CONFIG_REGULATOR_SY8824X=m
CONFIG_REGULATOR_SY8827N=m
CONFIG_REGULATOR_TPS51632=m
CONFIG_REGULATOR_TPS62360=m
CONFIG_REGULATOR_TPS65023=m
CONFIG_REGULATOR_TPS6507X=m
CONFIG_REGULATOR_TPS65132=m
CONFIG_REGULATOR_TPS6524X=m
CONFIG_REGULATOR_TPS6586X=m
CONFIG_REGULATOR_VCTRL=y
# CONFIG_REGULATOR_WL2868C is not set
CONFIG_REGULATOR_XZ3216=m
CONFIG_RC_CORE=y
CONFIG_RC_MAP=m
# CONFIG_LIRC is not set
CONFIG_RC_DECODERS=y
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
CONFIG_IR_JVC_DECODER=m
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_XMP_DECODER=m
CONFIG_IR_IMON_DECODER=m
CONFIG_IR_RCMM_DECODER=m
CONFIG_RC_DEVICES=y
CONFIG_RC_ATI_REMOTE=m
CONFIG_IR_ENE=m
CONFIG_IR_HIX5HD2=m
CONFIG_IR_IMON=m
CONFIG_IR_IMON_RAW=m
CONFIG_IR_MCEUSB=m
CONFIG_IR_ITE_CIR=m
CONFIG_IR_FINTEK=m
CONFIG_IR_NUVOTON=m
CONFIG_IR_REDRAT3=m
CONFIG_IR_STREAMZAP=m
CONFIG_IR_IGORPLUGUSB=m
CONFIG_IR_IGUANA=m
CONFIG_IR_TTUSBIR=m
CONFIG_RC_LOOPBACK=m
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_SERIAL=m
# CONFIG_IR_SERIAL_TRANSMITTER is not set
CONFIG_IR_SIR=m
CONFIG_RC_XBOX_DVD=m
CONFIG_IR_TOY=m
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y
CONFIG_MEDIA_CEC_RC=y
CONFIG_MEDIA_CEC_SUPPORT=y
# CONFIG_CEC_CH7322 is not set
# CONFIG_CEC_GPIO is not set
# CONFIG_USB_PULSE8_CEC is not set
# CONFIG_USB_RAINSHADOW_CEC is not set
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_SUPPORT_FILTER=y
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_SDR_SUPPORT is not set
CONFIG_MEDIA_PLATFORM_SUPPORT=y
# CONFIG_MEDIA_TEST_SUPPORT is not set
# end of Media device types

CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CONTROLLER=y

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2=y
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_H264=y
CONFIG_V4L2_MEM2MEM_DEV=y
# CONFIG_V4L2_FLASH_LED_CLASS is not set
CONFIG_V4L2_FWNODE=y
CONFIG_VIDEOBUF_GEN=m
CONFIG_VIDEOBUF_VMALLOC=m
# end of Video4Linux options

#
# Media controller options
#
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y

#
# Please notice that the enabled Media controller Request API is EXPERIMENTAL
#
# end of Media controller options

#
# Media drivers
#

#
# Drivers filtered as selected at 'Filter media drivers'
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_VIDEO_CLASS=y
# CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set
CONFIG_USB_GSPCA=m
# CONFIG_USB_M5602 is not set
# CONFIG_USB_STV06XX is not set
# CONFIG_USB_GL860 is not set
# CONFIG_USB_GSPCA_BENQ is not set
# CONFIG_USB_GSPCA_CONEX is not set
# CONFIG_USB_GSPCA_CPIA1 is not set
# CONFIG_USB_GSPCA_DTCS033 is not set
# CONFIG_USB_GSPCA_ETOMS is not set
# CONFIG_USB_GSPCA_FINEPIX is not set
# CONFIG_USB_GSPCA_JEILINJ is not set
# CONFIG_USB_GSPCA_JL2005BCD is not set
# CONFIG_USB_GSPCA_KINECT is not set
# CONFIG_USB_GSPCA_KONICA is not set
# CONFIG_USB_GSPCA_MARS is not set
# CONFIG_USB_GSPCA_MR97310A is not set
# CONFIG_USB_GSPCA_NW80X is not set
# CONFIG_USB_GSPCA_OV519 is not set
# CONFIG_USB_GSPCA_OV534 is not set
# CONFIG_USB_GSPCA_OV534_9 is not set
# CONFIG_USB_GSPCA_PAC207 is not set
# CONFIG_USB_GSPCA_PAC7302 is not set
# CONFIG_USB_GSPCA_PAC7311 is not set
# CONFIG_USB_GSPCA_SE401 is not set
# CONFIG_USB_GSPCA_SN9C2028 is not set
# CONFIG_USB_GSPCA_SN9C20X is not set
# CONFIG_USB_GSPCA_SONIXB is not set
# CONFIG_USB_GSPCA_SONIXJ is not set
# CONFIG_USB_GSPCA_SPCA500 is not set
# CONFIG_USB_GSPCA_SPCA501 is not set
# CONFIG_USB_GSPCA_SPCA505 is not set
# CONFIG_USB_GSPCA_SPCA506 is not set
# CONFIG_USB_GSPCA_SPCA508 is not set
# CONFIG_USB_GSPCA_SPCA561 is not set
# CONFIG_USB_GSPCA_SPCA1528 is not set
# CONFIG_USB_GSPCA_SQ905 is not set
# CONFIG_USB_GSPCA_SQ905C is not set
# CONFIG_USB_GSPCA_SQ930X is not set
# CONFIG_USB_GSPCA_STK014 is not set
# CONFIG_USB_GSPCA_STK1135 is not set
# CONFIG_USB_GSPCA_STV0680 is not set
# CONFIG_USB_GSPCA_SUNPLUS is not set
# CONFIG_USB_GSPCA_T613 is not set
# CONFIG_USB_GSPCA_TOPRO is not set
# CONFIG_USB_GSPCA_TOUPTEK is not set
# CONFIG_USB_GSPCA_TV8532 is not set
# CONFIG_USB_GSPCA_VC032X is not set
# CONFIG_USB_GSPCA_VICAM is not set
# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
# CONFIG_USB_GSPCA_ZC3XX is not set
CONFIG_USB_PWC=m
# CONFIG_USB_PWC_DEBUG is not set
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_VIDEO_CPIA2=m
CONFIG_USB_ZR364XX=m
CONFIG_USB_STKWEBCAM=m
CONFIG_USB_S2255=m
CONFIG_VIDEO_USBTV=m

#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=m
CONFIG_VIDEO_EM28XX_V4L2=m
CONFIG_VIDEO_EM28XX_ALSA=m
CONFIG_VIDEO_EM28XX_RC=m
CONFIG_MEDIA_PCI_SUPPORT=y

#
# Media capture support
#
CONFIG_VIDEO_SOLO6X10=m
CONFIG_VIDEO_TW5864=m
CONFIG_VIDEO_TW68=m
CONFIG_VIDEO_TW686X=m
CONFIG_VIDEO_TVEEPROM=m
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_CMA_SG=y
CONFIG_VIDEOBUF2_DMA_CONTIG=y
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_VIDEOBUF2_DMA_SG=y
CONFIG_V4L_PLATFORM_DRIVERS=y
# CONFIG_VIDEO_CAFE_CCIC is not set
# CONFIG_VIDEO_CADENCE is not set
# CONFIG_VIDEO_ASPEED is not set
CONFIG_VIDEO_MUX=y
CONFIG_VIDEO_ROCKCHIP_CIF=y
CONFIG_ROCKCHIP_CIF_WORKMODE_PINGPONG=y
# CONFIG_ROCKCHIP_CIF_WORKMODE_ONEFRAME is not set
CONFIG_ROCKCHIP_CIF_USE_DUMMY_BUF=y
# CONFIG_ROCKCHIP_CIF_USE_NONE_DUMMY_BUF is not set
# CONFIG_ROCKCHIP_CIF_USE_MONITOR is not set
# CONFIG_VIDEO_ROCKCHIP_RKISP1 is not set
CONFIG_VIDEO_ROCKCHIP_ISP=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V1X=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V20=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V21=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V30=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32=y
CONFIG_VIDEO_ROCKCHIP_ISPP=y
CONFIG_VIDEO_ROCKCHIP_ISPP_FEC=y
CONFIG_VIDEO_ROCKCHIP_ISPP_VERSION_V10=y
CONFIG_VIDEO_ROCKCHIP_ISPP_VERSION_V20=y
CONFIG_VIDEO_ROCKCHIP_HDMIRX_CLASS=y
CONFIG_VIDEO_ROCKCHIP_HDMIRX=y
# CONFIG_VIDEO_XILINX is not set
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
CONFIG_VIDEO_ROCKCHIP_RGA=y
# end of Media drivers

#
# Media ancillary drivers
#
CONFIG_VIDEO_IR_I2C=y

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_TVAUDIO=m
CONFIG_VIDEO_TDA7432=m
CONFIG_VIDEO_TDA9840=m
CONFIG_VIDEO_TDA1997X=m
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
CONFIG_VIDEO_MSP3400=m
CONFIG_VIDEO_CS3308=m
CONFIG_VIDEO_CS5345=m
CONFIG_VIDEO_CS53L32A=m
CONFIG_VIDEO_TLV320AIC23B=m
CONFIG_VIDEO_UDA1342=m
CONFIG_VIDEO_WM8775=m
CONFIG_VIDEO_WM8739=m
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_SONY_BTF_MPX=m
# end of Audio decoders, processors and mixers

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders

#
# Video decoders
#
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_ADV7183=m
CONFIG_VIDEO_ADV748X=m
CONFIG_VIDEO_ADV7604=m
# CONFIG_VIDEO_ADV7604_CEC is not set
CONFIG_VIDEO_ADV7842=m
# CONFIG_VIDEO_ADV7842_CEC is not set
CONFIG_VIDEO_BT819=m
CONFIG_VIDEO_BT856=m
CONFIG_VIDEO_BT866=m
CONFIG_VIDEO_EP9461E=m
CONFIG_VIDEO_KS0127=m
CONFIG_VIDEO_IT6616=m
CONFIG_VIDEO_LT6911UXC=m
CONFIG_VIDEO_LT6911UXE=m
CONFIG_VIDEO_LT7911D=m
CONFIG_VIDEO_LT7911UXC=m
CONFIG_VIDEO_LT8619C=m
CONFIG_VIDEO_ML86V7667=m
CONFIG_VIDEO_NVP6158=m
CONFIG_VIDEO_NVP6188=m
CONFIG_VIDEO_NVP6324=m
CONFIG_VIDEO_OTP_EEPROM=m
CONFIG_VIDEO_RK628=y
CONFIG_VIDEO_RK628_CSI=y
CONFIG_VIDEO_RK628_BT1120=y
CONFIG_VIDEO_SAA7110=m
CONFIG_VIDEO_SAA711X=m
CONFIG_VIDEO_TC358743=m
# CONFIG_VIDEO_TC358743_CEC is not set
CONFIG_VIDEO_TC35874X=m
CONFIG_VIDEO_TECHPOINT=m
CONFIG_VIDEO_THCV244=m
CONFIG_VIDEO_TVP514X=m
CONFIG_VIDEO_TVP5150=m
CONFIG_VIDEO_TVP7002=m
CONFIG_VIDEO_TW2804=m
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=m
CONFIG_VIDEO_TW9910=m
CONFIG_VIDEO_VPX3220=m
CONFIG_VIDEO_MAX9286=m
CONFIG_VIDEO_MAX96712=m
CONFIG_VIDEO_MAX96714=m
CONFIG_VIDEO_MAX96722=m
CONFIG_VIDEO_DES_MAXIM4C=m

#
# Maxim Quad GMSL serializer devices support
#
# CONFIG_MAXIM4C_SER_MAX9295 is not set
# CONFIG_MAXIM4C_SER_MAX96715 is not set
# CONFIG_MAXIM4C_SER_MAX96717 is not set
# end of Maxim Quad GMSL serializer devices support

#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=m
CONFIG_VIDEO_CX25840=m
CONFIG_VIDEO_IT66353=m
# end of Video decoders

#
# Video encoders
#
CONFIG_VIDEO_SAA7127=m
CONFIG_VIDEO_SAA7185=m
CONFIG_VIDEO_ADV7170=m
CONFIG_VIDEO_ADV7175=m
CONFIG_VIDEO_ADV7343=m
CONFIG_VIDEO_ADV7393=m
CONFIG_VIDEO_ADV7511=m
# CONFIG_VIDEO_ADV7511_CEC is not set
CONFIG_VIDEO_AD9389B=m
CONFIG_VIDEO_AK881X=m
CONFIG_VIDEO_THS8200=m
# end of Video encoders

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
CONFIG_VIDEO_UPD64083=m
# end of Video improvement chips

#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips

#
# SDR tuner chips
#
# end of SDR tuner chips

#
# Miscellaneous helper chips
#
CONFIG_VIDEO_THS7303=m
CONFIG_VIDEO_M52790=m
CONFIG_VIDEO_I2C=m
CONFIG_VIDEO_ST_MIPID02=m
CONFIG_VIDEO_RK_IRCUT=y
# end of Miscellaneous helper chips

#
# Camera sensor devices
#
CONFIG_VIDEO_APTINA_PLL=m
CONFIG_VIDEO_SMIAPP_PLL=m
CONFIG_VIDEO_AR0230=m
# CONFIG_VIDEO_AR0822 is not set
CONFIG_VIDEO_GC02M2=m
CONFIG_VIDEO_GC08A3=m
CONFIG_VIDEO_GC1084=m
CONFIG_VIDEO_GC2053=m
CONFIG_VIDEO_GC2093=m
CONFIG_VIDEO_GC2145=m
CONFIG_VIDEO_GC2385=m
CONFIG_VIDEO_GC3003=m
CONFIG_VIDEO_GC4023=m
CONFIG_VIDEO_GC4653=m
CONFIG_VIDEO_GC4663=m
CONFIG_VIDEO_GC4C33=m
CONFIG_VIDEO_GC5025=m
CONFIG_VIDEO_GC5035=m
CONFIG_VIDEO_GC8034=m
CONFIG_VIDEO_HI556=m
CONFIG_VIDEO_IMX214=m
CONFIG_VIDEO_IMX214_EEPROM=m
CONFIG_VIDEO_IMX219=m
CONFIG_VIDEO_IMX258=m
CONFIG_VIDEO_IMX258_EEPROM=m
CONFIG_VIDEO_IMX274=m
CONFIG_VIDEO_IMX290=m
CONFIG_VIDEO_IMX307=m
CONFIG_VIDEO_IMX317=m
CONFIG_VIDEO_IMX319=m
CONFIG_VIDEO_IMX323=m
CONFIG_VIDEO_IMX327=m
CONFIG_VIDEO_IMX334=m
CONFIG_VIDEO_IMX335=m
CONFIG_VIDEO_IMX347=m
CONFIG_VIDEO_IMX378=m
CONFIG_VIDEO_IMX415=m
CONFIG_VIDEO_IMX464=m
CONFIG_VIDEO_IMX492=m
CONFIG_VIDEO_IMX355=m
CONFIG_VIDEO_IMX577=m
CONFIG_VIDEO_IMX586=m
CONFIG_VIDEO_JX_K17=m
CONFIG_VIDEO_OS02G10=m
CONFIG_VIDEO_OS02K10=m
CONFIG_VIDEO_OS03B10=m
CONFIG_VIDEO_OS04A10=m
CONFIG_VIDEO_OS05A20=m
CONFIG_VIDEO_OS08A20=m
CONFIG_VIDEO_OV02B10=m
CONFIG_VIDEO_OV02K10=m
CONFIG_VIDEO_OV16A10=m
CONFIG_VIDEO_OV16A1Q=m
CONFIG_VIDEO_OV2640=m
CONFIG_VIDEO_OV2659=m
CONFIG_VIDEO_OV2680=m
CONFIG_VIDEO_OV2685=m
CONFIG_VIDEO_OV2718=m
CONFIG_VIDEO_OV2740=m
CONFIG_VIDEO_OV4686=m
CONFIG_VIDEO_OV4688=m
CONFIG_VIDEO_OV4689=m
CONFIG_VIDEO_OV50C40=m
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_OV5647=m
CONFIG_VIDEO_OV6650=m
CONFIG_VIDEO_OV5670=m
CONFIG_VIDEO_OV5675=m
CONFIG_VIDEO_OV5695=m
CONFIG_VIDEO_OV7251=m
CONFIG_VIDEO_OV772X=m
CONFIG_VIDEO_OV7640=m
CONFIG_VIDEO_OV7670=m
CONFIG_VIDEO_OV7740=m
CONFIG_VIDEO_OV8856=m
CONFIG_VIDEO_OV8858=m
CONFIG_VIDEO_OV9281=m
CONFIG_VIDEO_OV9640=m
CONFIG_VIDEO_OV9650=m
CONFIG_VIDEO_OV12D2Q=m
CONFIG_VIDEO_OV13850=m
CONFIG_VIDEO_OV13855=m
CONFIG_VIDEO_OV13858=m
CONFIG_VIDEO_VS6624=m
CONFIG_VIDEO_MT9M001=m
CONFIG_VIDEO_MT9M032=m
CONFIG_VIDEO_MT9M111=m
CONFIG_VIDEO_MT9P031=m
CONFIG_VIDEO_MT9T001=m
CONFIG_VIDEO_MT9T112=m
CONFIG_VIDEO_MT9V011=m
CONFIG_VIDEO_MT9V032=m
CONFIG_VIDEO_MT9V111=m
CONFIG_VIDEO_SC031GS=m
CONFIG_VIDEO_SC035GS=m
CONFIG_VIDEO_SC132GS=m
CONFIG_VIDEO_SC1346=m
CONFIG_VIDEO_SC200AI=m
CONFIG_VIDEO_SC210IOT=m
CONFIG_VIDEO_SC2232=m
CONFIG_VIDEO_SC2239=m
CONFIG_VIDEO_SC223A=m
CONFIG_VIDEO_SC230AI=m
CONFIG_VIDEO_SC2310=m
CONFIG_VIDEO_SC2336=m
CONFIG_VIDEO_SC301IOT=m
CONFIG_VIDEO_SC3336=m
CONFIG_VIDEO_SC3338=m
CONFIG_VIDEO_SC401AI=m
CONFIG_VIDEO_SC4210=m
CONFIG_VIDEO_SC4238=m
CONFIG_VIDEO_SC430CS=m
CONFIG_VIDEO_SC4336=m
CONFIG_VIDEO_SC500AI=m
CONFIG_VIDEO_SC501AI=m
CONFIG_VIDEO_SC530AI=m
CONFIG_VIDEO_SC5336=m
CONFIG_VIDEO_SC850SL=m
CONFIG_VIDEO_SENSOR_ADAPTER=y
CONFIG_VIDEO_SR030PC30=m
CONFIG_VIDEO_NOON010PC30=m
CONFIG_VIDEO_M5MOLS=m
CONFIG_VIDEO_RDACM20=m
CONFIG_VIDEO_RJ54N1=m
CONFIG_VIDEO_S5K3L6XX=m
CONFIG_VIDEO_S5K6AA=m
CONFIG_VIDEO_S5K6A3=m
CONFIG_VIDEO_S5K4ECGX=m
CONFIG_VIDEO_S5K5BAF=m
CONFIG_VIDEO_S5KJN1=m
CONFIG_VIDEO_SMIAPP=m
CONFIG_VIDEO_ET8EK8=m
CONFIG_VIDEO_S5C73M3=m
CONFIG_VIDEO_PREISP_DUMMY_SENSOR=m
# end of Camera sensor devices

#
# Lens drivers
#
CONFIG_VIDEO_AD5820=m
CONFIG_VIDEO_AK7375=m
CONFIG_VIDEO_AW8601=m
CONFIG_VIDEO_CN3927V=m
CONFIG_VIDEO_DW9714=m
CONFIG_VIDEO_DW9763=m
CONFIG_VIDEO_DW9768=m
CONFIG_VIDEO_DW9800W=m
CONFIG_VIDEO_DW9807_VCM=m
CONFIG_VIDEO_FP5510=m
# end of Lens drivers

#
# Flash devices
#
CONFIG_VIDEO_ADP1653=m
CONFIG_VIDEO_AW36518=m
CONFIG_VIDEO_LM3560=m
CONFIG_VIDEO_LM3646=m
CONFIG_VIDEO_SGM3784=m
# end of Flash devices

#
# SPI helper chips
#
CONFIG_VIDEO_GS1662=m
CONFIG_VIDEO_ROCKCHIP_PREISP=y
# end of SPI helper chips

#
# Media SPI Adapters
#
# end of Media SPI Adapters
# end of Media ancillary drivers

#
# Graphics support
#
# CONFIG_VGA_ARB is not set
CONFIG_DRM=y
CONFIG_DRM_EDID=y
# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_DP=y
CONFIG_DRM_DP_AUX_CHARDEV=y
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_KMS_FB_HELPER=y
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
CONFIG_DRM_LOAD_EDID_FIRMWARE=y
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_GEM_CMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=y
CONFIG_DRM_SCHED=m

#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips

#
# ARM devices
#
# CONFIG_DRM_HDLCD is not set
# CONFIG_DRM_MALI_DISPLAY is not set
# CONFIG_DRM_KOMEDA is not set
# end of ARM devices

# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
CONFIG_DRM_ROCKCHIP=y
# CONFIG_ROCKCHIP_DRM_DEBUG is not set
# CONFIG_ROCKCHIP_DRM_DIRECT_SHOW is not set
CONFIG_ROCKCHIP_VOP=y
CONFIG_ROCKCHIP_VOP2=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DRM_TVE=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_DW_DP=y
CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_ROCKCHIP_LVDS=y
CONFIG_ROCKCHIP_RGB=y
CONFIG_ROCKCHIP_RK3066_HDMI=y
# CONFIG_ROCKCHIP_VCONN is not set
# CONFIG_DRM_ROCKCHIP_VVOP is not set
CONFIG_ROCKCHIP_DW_HDCP2=y
CONFIG_DRM_ROCKCHIP_RK618=m
CONFIG_DRM_ROCKCHIP_RK628=m
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_LVDS is not set
# CONFIG_DRM_QXL is not set
# CONFIG_DRM_BOCHS is not set
# CONFIG_DRM_VIRTIO_GPU is not set
CONFIG_DRM_PANEL=y

#
# Display Panels
#
CONFIG_DRM_PANEL_ARM_VERSATILE=m
CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
CONFIG_DRM_PANEL_LVDS=m
CONFIG_DRM_PANEL_SIMPLE=m
CONFIG_DRM_PANEL_ELIDA_KD35T133=m
CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
CONFIG_DRM_PANEL_ILITEK_IL9322=m
CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=m
CONFIG_DRM_PANEL_JDI_LT070ME05000=m
CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
CONFIG_DRM_PANEL_LG_LB035Q02=m
CONFIG_DRM_PANEL_LG_LG4573=m
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
CONFIG_DRM_PANEL_NOVATEK_NT35510=m
CONFIG_DRM_PANEL_NOVATEK_NT39016=m
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
CONFIG_DRM_PANEL_MAXIM_MAX96752F=m
# CONFIG_DRM_PANEL_MAXIM_MAX96772 is not set
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
CONFIG_DRM_PANEL_RADXA_DISPLAY_8HD=m
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
CONFIG_DRM_PANEL_RASPITS_TC358762=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
CONFIG_DRM_PANEL_RONBO_RB070D30=m
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
CONFIG_DRM_PANEL_SITRONIX_ST7789V=m
CONFIG_DRM_PANEL_SONY_ACX424AKP=m
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
CONFIG_DRM_PANEL_TPO_TPG110=m
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
CONFIG_DRM_PANEL_VISIONOX_RM69299=m
CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
CONFIG_DRM_DISPLAY_CONNECTOR=y
# CONFIG_DRM_ITE_IT6161 is not set
# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MAXIM_MAX96745 is not set
# CONFIG_DRM_MAXIM_MAX96755F is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
CONFIG_DRM_RK1000_TVE=m
# CONFIG_DRM_ROHM_BU18XL82 is not set
# CONFIG_DRM_SIL_SII8620 is not set
CONFIG_DRM_SII902X=m
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
CONFIG_DRM_ANALOGIX_DP=y
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=y
# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
CONFIG_DRM_DW_HDMI_CEC=m
CONFIG_DRM_DW_MIPI_DSI=y
# end of Display Interface Bridges

# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
# CONFIG_DRM_MXSFB is not set
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_GM12U320 is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_DRM_PL111 is not set
# CONFIG_DRM_LIMA is not set
CONFIG_DRM_PANFROST=m
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_LEGACY is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_MALI400=m
CONFIG_MALI450=y
CONFIG_MALI470=y
# CONFIG_MALI400_DEBUG is not set
# CONFIG_MALI400_PROFILING is not set
# CONFIG_MALI400_UMP is not set
CONFIG_MALI_DMA_BUF_MAP_ON_ATTACH=y
CONFIG_MALI_SHARED_INTERRUPTS=y
# CONFIG_MALI_PMU_PARALLEL_POWER_UP is not set
CONFIG_MALI_DT=y
CONFIG_MALI_DEVFREQ=y
# CONFIG_MALI_QUIET is not set
# CONFIG_MALI_MIDGARD is not set
# CONFIG_MALI_KUTF is not set
# CONFIG_MALI_BIFROST is not set

#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_BACKLIGHT=m
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_ARMCLCD is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_UVESA is not set
# CONFIG_FB_EFI is not set
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SSD1307 is not set
# CONFIG_FB_SM712 is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_L4F00242T03 is not set
# CONFIG_LCD_LMS283GF05 is not set
# CONFIG_LCD_LTV350QV is not set
# CONFIG_LCD_ILI922X is not set
# CONFIG_LCD_ILI9320 is not set
# CONFIG_LCD_TDO24M is not set
# CONFIG_LCD_VGG2432A4 is not set
# CONFIG_LCD_PLATFORM is not set
# CONFIG_LCD_AMS369FG06 is not set
# CONFIG_LCD_LMS501KF03 is not set
# CONFIG_LCD_HX8357 is not set
# CONFIG_LCD_OTM3225A is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_KTD253 is not set
CONFIG_BACKLIGHT_PWM=y
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
# CONFIG_BACKLIGHT_GPIO is not set
CONFIG_BACKLIGHT_LV5207LP=m
CONFIG_BACKLIGHT_BD6107=m
CONFIG_BACKLIGHT_ARCXCNN=m
CONFIG_BACKLIGHT_LED=y
# end of Backlight & LCD device support

#
# Rockchip Misc Video driver
#

#
# RGA
#
# CONFIG_ROCKCHIP_RGA is not set
# end of RGA

CONFIG_ROCKCHIP_RGA2=y
# CONFIG_ROCKCHIP_RGA2_PROC_FS is not set
CONFIG_ROCKCHIP_RGA2_DEBUG_FS=y
CONFIG_ROCKCHIP_RGA2_DEBUGGER=y
# CONFIG_ROCKCHIP_MULTI_RGA is not set
CONFIG_ROCKCHIP_RVE=m
# CONFIG_ROCKCHIP_RVE_PROC_FS is not set
CONFIG_ROCKCHIP_RVE_DEBUG_FS=y
CONFIG_ROCKCHIP_RVE_DEBUGGER=y

#
# IEP
#
CONFIG_IEP=y
# end of IEP

CONFIG_ROCKCHIP_MPP_SERVICE=y
CONFIG_ROCKCHIP_MPP_PROC_FS=y
CONFIG_ROCKCHIP_MPP_RKVDEC=y
CONFIG_ROCKCHIP_MPP_RKVDEC2=y
CONFIG_ROCKCHIP_MPP_RKVENC=y
CONFIG_ROCKCHIP_MPP_RKVENC2=y
CONFIG_ROCKCHIP_MPP_VDPU1=y
CONFIG_ROCKCHIP_MPP_VEPU1=y
CONFIG_ROCKCHIP_MPP_VDPU2=y
CONFIG_ROCKCHIP_MPP_VEPU2=y
CONFIG_ROCKCHIP_MPP_IEP2=y
CONFIG_ROCKCHIP_MPP_JPGDEC=y
CONFIG_ROCKCHIP_MPP_AV1DEC=y
CONFIG_ROCKCHIP_MPP_VDPP=y
CONFIG_ROCKCHIP_DVBM=y
CONFIG_ROCKCHIP_DVBM_PROC_FS=y
# end of Rockchip Misc Video driver

CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
# end of Console display driver support

CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
# end of Graphics support

CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=m
CONFIG_SND_SEQ_DEVICE=y
CONFIG_SND_RAWMIDI=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_OSSEMUL is not set
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
CONFIG_SND_VMASTER=y
CONFIG_SND_SEQUENCER=m
CONFIG_SND_SEQ_DUMMY=m
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
CONFIG_SND_SEQ_MIDI_EVENT=m
CONFIG_SND_SEQ_MIDI=m
CONFIG_SND_SEQ_VIRMIDI=m
CONFIG_SND_MPU401_UART=m
CONFIG_SND_AC97_CODEC=y
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
CONFIG_SND_VIRMIDI=m
CONFIG_SND_MTPAV=m
CONFIG_SND_SERIAL_U16550=m
CONFIG_SND_MPU401=m
# CONFIG_SND_AC97_POWER_SAVE is not set
# CONFIG_SND_PCI is not set

#
# HD-Audio
#
# end of HD-Audio

CONFIG_SND_HDA_PREALLOC_SIZE=64
# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
CONFIG_SND_BCD2000=m
CONFIG_SND_USB_LINE6=m
CONFIG_SND_USB_POD=m
CONFIG_SND_USB_PODHD=m
CONFIG_SND_USB_TONEPORT=m
CONFIG_SND_USB_VARIAX=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
# CONFIG_SND_SOC_AMD_ACP is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
CONFIG_SND_DESIGNWARE_I2S=y
# CONFIG_SND_DESIGNWARE_PCM is not set

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
# CONFIG_SND_SOC_FSL_SAI is not set
# CONFIG_SND_SOC_FSL_AUDMIX is not set
# CONFIG_SND_SOC_FSL_SSI is not set
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
# CONFIG_SND_SOC_FSL_MICFIL is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs

# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_I2S_HI3660_I2S is not set
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set
CONFIG_SND_SOC_ROCKCHIP=y
CONFIG_SND_SOC_ROCKCHIP_DLP=y
CONFIG_SND_SOC_ROCKCHIP_I2S=y
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y
# CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES is not set
CONFIG_SND_SOC_ROCKCHIP_MULTI_DAIS=y
CONFIG_SND_SOC_ROCKCHIP_PDM=y
CONFIG_SND_SOC_ROCKCHIP_SAI=y
CONFIG_SND_SOC_ROCKCHIP_SAI_VERBOSE=y
CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
CONFIG_SND_SOC_ROCKCHIP_SPDIFRX=y
CONFIG_SND_SOC_ROCKCHIP_VAD=y
CONFIG_SND_SOC_ROCKCHIP_MAX98090=y
CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
CONFIG_SND_SOC_ROCKCHIP_RT5645=y
CONFIG_SND_SOC_ROCKCHIP_HDMI=y
CONFIG_SND_SOC_RK3288_HDMI_ANALOG=y
CONFIG_SND_SOC_RK3399_GRU_SOUND=y
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set

#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support

# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# CONFIG_SND_SOC_XTFPGA_I2S is not set
# CONFIG_ZX_TDM is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
CONFIG_SND_SOC_AC97_CODEC=y
CONFIG_SND_SOC_ADAU_UTILS=y
CONFIG_SND_SOC_ADAU1701=y
CONFIG_SND_SOC_ADAU17X1=y
CONFIG_SND_SOC_ADAU1761=y
CONFIG_SND_SOC_ADAU1761_I2C=y
CONFIG_SND_SOC_ADAU1761_SPI=y
CONFIG_SND_SOC_ADAU7002=y
CONFIG_SND_SOC_ADAU7118=y
CONFIG_SND_SOC_ADAU7118_HW=y
CONFIG_SND_SOC_ADAU7118_I2C=y
CONFIG_SND_SOC_AK4104=y
CONFIG_SND_SOC_AK4118=y
CONFIG_SND_SOC_AK4458=y
CONFIG_SND_SOC_AK4554=y
CONFIG_SND_SOC_AK4613=y
CONFIG_SND_SOC_AK4642=y
CONFIG_SND_SOC_AK5386=y
CONFIG_SND_SOC_AK5558=y
CONFIG_SND_SOC_ALC5623=y
CONFIG_SND_SOC_BD28623=y
CONFIG_SND_SOC_BT_SCO=y
CONFIG_SND_SOC_CS35L32=y
CONFIG_SND_SOC_CS35L33=y
CONFIG_SND_SOC_CS35L34=y
CONFIG_SND_SOC_CS35L35=y
CONFIG_SND_SOC_CS35L36=y
CONFIG_SND_SOC_CS42L42=y
CONFIG_SND_SOC_CS42L51=y
CONFIG_SND_SOC_CS42L51_I2C=y
CONFIG_SND_SOC_CS42L52=y
CONFIG_SND_SOC_CS42L56=y
CONFIG_SND_SOC_CS42L73=y
CONFIG_SND_SOC_CS4234=y
CONFIG_SND_SOC_CS4265=y
CONFIG_SND_SOC_CS4270=y
CONFIG_SND_SOC_CS4271=y
CONFIG_SND_SOC_CS4271_I2C=y
CONFIG_SND_SOC_CS4271_SPI=y
CONFIG_SND_SOC_CS42XX8=y
CONFIG_SND_SOC_CS42XX8_I2C=y
CONFIG_SND_SOC_CS43130=y
CONFIG_SND_SOC_CS4341=y
CONFIG_SND_SOC_CS4349=y
CONFIG_SND_SOC_CS53L30=y
CONFIG_SND_SOC_CX2072X=y
CONFIG_SND_SOC_DA7213=y
CONFIG_SND_SOC_DA7219=y
CONFIG_SND_SOC_DMIC=y
CONFIG_SND_SOC_DUMMY_CODEC=y
CONFIG_SND_SOC_HDMI_CODEC=y
CONFIG_SND_SOC_ES7134=y
CONFIG_SND_SOC_ES7202=y
CONFIG_SND_SOC_ES7202_MIC_MAX_CHANNELS=2
CONFIG_SND_SOC_ES7202_I2C_BUS=1
CONFIG_SND_SOC_ES7210=y
CONFIG_SND_SOC_ES7241=y
CONFIG_SND_SOC_ES7243E=y
CONFIG_SND_SOC_ES8311=y
CONFIG_SND_SOC_ES8316=y
CONFIG_SND_SOC_ES8323=y
CONFIG_SND_SOC_ES8326=y
CONFIG_SND_SOC_ES8328=y
CONFIG_SND_SOC_ES8328_I2C=y
CONFIG_SND_SOC_ES8328_SPI=y
CONFIG_SND_SOC_ES8396=y
CONFIG_SND_SOC_GTM601=y
CONFIG_SND_SOC_INNO_RK3036=y
CONFIG_SND_SOC_MAX98088=y
CONFIG_SND_SOC_MAX98090=y
CONFIG_SND_SOC_MAX98357A=y
CONFIG_SND_SOC_MAX98504=y
CONFIG_SND_SOC_MAX9867=y
CONFIG_SND_SOC_MAX98927=y
CONFIG_SND_SOC_MAX98373=y
CONFIG_SND_SOC_MAX98373_I2C=y
CONFIG_SND_SOC_MAX98390=y
CONFIG_SND_SOC_MAX9860=y
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y
CONFIG_SND_SOC_PCM1681=y
CONFIG_SND_SOC_PCM1789=y
CONFIG_SND_SOC_PCM1789_I2C=y
CONFIG_SND_SOC_PCM179X=y
CONFIG_SND_SOC_PCM179X_I2C=y
CONFIG_SND_SOC_PCM179X_SPI=y
CONFIG_SND_SOC_PCM186X=y
CONFIG_SND_SOC_PCM186X_I2C=y
CONFIG_SND_SOC_PCM186X_SPI=y
CONFIG_SND_SOC_PCM3060=y
CONFIG_SND_SOC_PCM3060_I2C=y
CONFIG_SND_SOC_PCM3060_SPI=y
CONFIG_SND_SOC_PCM3168A=y
CONFIG_SND_SOC_PCM3168A_I2C=y
CONFIG_SND_SOC_PCM3168A_SPI=y
CONFIG_SND_SOC_PCM512x=y
CONFIG_SND_SOC_PCM512x_I2C=y
CONFIG_SND_SOC_PCM512x_SPI=y
CONFIG_SND_SOC_RK1000=m
CONFIG_SND_SOC_RK312X=y
CONFIG_SND_SOC_RK3228=y
CONFIG_SND_SOC_RK3308=y
CONFIG_SND_SOC_RK3328=y
CONFIG_SND_SOC_RK3528=y
CONFIG_SND_SOC_RK730=y
CONFIG_SND_SOC_RK817=y
CONFIG_SND_SOC_RK_CODEC_DIGITAL=y
CONFIG_SND_SOC_RK_DSM=y
CONFIG_SND_SOC_RL6231=y
CONFIG_SND_SOC_RT5514=y
CONFIG_SND_SOC_RT5514_SPI=y
CONFIG_SND_SOC_RT5616=y
CONFIG_SND_SOC_RT5631=y
CONFIG_SND_SOC_RT5640=y
CONFIG_SND_SOC_RT5645=y
CONFIG_SND_SOC_RT5651=y
CONFIG_SND_SOC_RV1106=y
CONFIG_SND_SOC_SGTL5000=y
CONFIG_SND_SOC_SIGMADSP=y
CONFIG_SND_SOC_SIGMADSP_I2C=y
CONFIG_SND_SOC_SIGMADSP_REGMAP=y
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
CONFIG_SND_SOC_SIRF_AUDIO_CODEC=y
CONFIG_SND_SOC_SPDIF=y
CONFIG_SND_SOC_SSM2305=y
CONFIG_SND_SOC_SSM2602=y
CONFIG_SND_SOC_SSM2602_SPI=y
CONFIG_SND_SOC_SSM2602_I2C=y
CONFIG_SND_SOC_SSM4567=y
CONFIG_SND_SOC_STA32X=y
CONFIG_SND_SOC_STA350=y
CONFIG_SND_SOC_STI_SAS=y
CONFIG_SND_SOC_TAS2552=y
CONFIG_SND_SOC_TAS2562=y
CONFIG_SND_SOC_TAS2764=y
CONFIG_SND_SOC_TAS2770=y
CONFIG_SND_SOC_TAS5086=y
CONFIG_SND_SOC_TAS571X=y
CONFIG_SND_SOC_TAS5720=y
CONFIG_SND_SOC_TAS6424=y
CONFIG_SND_SOC_TDA7419=y
CONFIG_SND_SOC_TDA7803=y
CONFIG_SND_SOC_TFA9879=y
CONFIG_SND_SOC_TLV320AIC23=y
CONFIG_SND_SOC_TLV320AIC23_I2C=y
CONFIG_SND_SOC_TLV320AIC23_SPI=y
CONFIG_SND_SOC_TLV320AIC31XX=y
CONFIG_SND_SOC_TLV320AIC32X4=y
CONFIG_SND_SOC_TLV320AIC32X4_I2C=y
CONFIG_SND_SOC_TLV320AIC32X4_SPI=y
CONFIG_SND_SOC_TLV320AIC3X=y
CONFIG_SND_SOC_TLV320ADCX140=y
CONFIG_SND_SOC_TS3A227E=y
CONFIG_SND_SOC_TSCS42XX=y
CONFIG_SND_SOC_TSCS454=y
CONFIG_SND_SOC_UDA1334=y
CONFIG_SND_SOC_WM8510=y
CONFIG_SND_SOC_WM8523=y
CONFIG_SND_SOC_WM8524=y
CONFIG_SND_SOC_WM8580=y
CONFIG_SND_SOC_WM8711=y
CONFIG_SND_SOC_WM8728=y
CONFIG_SND_SOC_WM8731=y
CONFIG_SND_SOC_WM8737=y
CONFIG_SND_SOC_WM8741=y
CONFIG_SND_SOC_WM8750=y
CONFIG_SND_SOC_WM8753=y
CONFIG_SND_SOC_WM8770=y
CONFIG_SND_SOC_WM8776=y
CONFIG_SND_SOC_WM8782=y
CONFIG_SND_SOC_WM8804=y
CONFIG_SND_SOC_WM8804_I2C=y
CONFIG_SND_SOC_WM8804_SPI=y
CONFIG_SND_SOC_WM8903=y
CONFIG_SND_SOC_WM8904=y
CONFIG_SND_SOC_WM8960=y
CONFIG_SND_SOC_WM8962=y
CONFIG_SND_SOC_WM8974=y
CONFIG_SND_SOC_WM8978=y
CONFIG_SND_SOC_WM8985=y
CONFIG_SND_SOC_ZL38060=y
CONFIG_SND_SOC_ZX_AUD96P22=y
CONFIG_SND_SOC_MAX9759=y
CONFIG_SND_SOC_MT6351=y
CONFIG_SND_SOC_MT6358=y
CONFIG_SND_SOC_MT6660=y
CONFIG_SND_SOC_NAU8540=y
CONFIG_SND_SOC_NAU8810=y
CONFIG_SND_SOC_NAU8822=y
CONFIG_SND_SOC_NAU8824=y
CONFIG_SND_SOC_TPA6130A2=y
CONFIG_SND_SOC_AW87XXX=m
CONFIG_SND_SOC_AW883XX=m
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD=y
CONFIG_AC97_BUS=y

#
# HID support
#
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=m
CONFIG_HID_GENERIC=m

#
# Special HID drivers
#
CONFIG_HID_A4TECH=m
CONFIG_HID_ACCUTOUCH=m
CONFIG_HID_ACRUX=m
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=m
CONFIG_HID_APPLEIR=m
CONFIG_HID_ASUS=m
CONFIG_HID_AUREAL=m
CONFIG_HID_BELKIN=m
CONFIG_HID_BETOP_FF=m
CONFIG_HID_BIGBEN_FF=m
CONFIG_HID_CHERRY=m
CONFIG_HID_CHICONY=m
CONFIG_HID_CORSAIR=m
CONFIG_HID_COUGAR=m
CONFIG_HID_MACALLY=m
CONFIG_HID_PRODIKEYS=m
CONFIG_HID_CMEDIA=m
CONFIG_HID_CP2112=m
CONFIG_HID_CREATIVE_SB0540=m
CONFIG_HID_CYPRESS=m
CONFIG_HID_DRAGONRISE=m
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=m
CONFIG_HID_ELAN=m
CONFIG_HID_ELECOM=m
CONFIG_HID_ELO=m
CONFIG_HID_EZKEY=m
CONFIG_HID_GEMBIRD=m
CONFIG_HID_GFRM=m
CONFIG_HID_GLORIOUS=m
CONFIG_HID_HOLTEK=m
CONFIG_HOLTEK_FF=y
CONFIG_HID_VIVALDI=m
CONFIG_HID_GT683R=m
CONFIG_HID_KEYTOUCH=m
CONFIG_HID_KYE=m
CONFIG_HID_UCLOGIC=m
CONFIG_HID_WALTOP=m
CONFIG_HID_VIEWSONIC=m
CONFIG_HID_GYRATION=m
CONFIG_HID_ICADE=m
CONFIG_HID_ITE=m
CONFIG_HID_JABRA=m
CONFIG_HID_TWINHAN=m
CONFIG_HID_KENSINGTON=m
CONFIG_HID_LCPOWER=m
CONFIG_HID_LED=m
CONFIG_HID_LENOVO=m
CONFIG_HID_LOGITECH=m
CONFIG_HID_LOGITECH_DJ=m
CONFIG_HID_LOGITECH_HIDPP=m
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
CONFIG_HID_MAGICMOUSE=m
CONFIG_HID_MALTRON=m
CONFIG_HID_MAYFLASH=m
CONFIG_HID_REDRAGON=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
CONFIG_HID_MULTITOUCH=m
CONFIG_HID_NINTENDO=m
CONFIG_HID_NTI=m
CONFIG_HID_NTRIG=m
CONFIG_HID_ORTEK=m
CONFIG_HID_PANTHERLORD=m
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PENMOUNT=m
CONFIG_HID_PETALYNX=m
CONFIG_HID_PICOLCD=m
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
# CONFIG_HID_PICOLCD_LCD is not set
CONFIG_HID_PICOLCD_LEDS=y
CONFIG_HID_PICOLCD_CIR=y
CONFIG_HID_PLANTRONICS=m
CONFIG_HID_PLAYSTATION=m
CONFIG_PLAYSTATION_FF=y
CONFIG_HID_PRIMAX=m
CONFIG_HID_RETRODE=m
CONFIG_HID_ROCCAT=m
CONFIG_HID_SAITEK=m
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SONY=m
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=m
CONFIG_HID_STEAM=m
CONFIG_HID_STEELSERIES=m
CONFIG_HID_SUNPLUS=m
CONFIG_HID_RMI=m
CONFIG_HID_GREENASIA=m
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=m
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TIVO=m
CONFIG_HID_TOPSEED=m
CONFIG_HID_THINGM=m
CONFIG_HID_THRUSTMASTER=m
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_UDRAW_PS3=m
CONFIG_HID_U2FZERO=m
CONFIG_HID_WACOM=m
CONFIG_HID_WIIMOTE=m
CONFIG_HID_XINMO=m
CONFIG_HID_ZEROPLUS=m
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=m
CONFIG_HID_SENSOR_HUB=m
CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
CONFIG_HID_ALPS=m
CONFIG_HID_MCP2221=m
# end of Special HID drivers

#
# USB HID support
#
CONFIG_USB_HID=y
# CONFIG_HID_PID is not set
CONFIG_USB_HIDDEV=y
# end of USB HID support

#
# I2C HID support
#
CONFIG_I2C_HID=y
# end of I2C HID support
# end of HID support

CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
# CONFIG_USB_LED_TRIG is not set
# CONFIG_USB_ULPI_BUS is not set
# CONFIG_USB_CONN_GPIO is not set
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
CONFIG_USB_OTG_FSM=y
# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=m

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=y
# CONFIG_USB_XHCI_PCI_RENESAS is not set
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
# CONFIG_USB_EHCI_FSL is not set
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OXU210HP_HCD=m
CONFIG_USB_ISP116X_HCD=m
CONFIG_USB_FOTG210_HCD=m
CONFIG_USB_MAX3421_HCD=m
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PCI=m
CONFIG_USB_OHCI_HCD_PLATFORM=y
# CONFIG_USB_UHCI_HCD is not set
CONFIG_USB_U132_HCD=m
CONFIG_USB_SL811_HCD=m
# CONFIG_USB_SL811_HCD_ISO is not set
CONFIG_USB_R8A66597_HCD=m
CONFIG_USB_HCD_BCMA=m
CONFIG_USB_HCD_SSB=m
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=y
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=m
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
CONFIG_USB_STORAGE_REALTEK=m
CONFIG_REALTEK_AUTOPM=y
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_FREECOM=m
CONFIG_USB_STORAGE_ISD200=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_STORAGE_ALAUDA=m
CONFIG_USB_STORAGE_ONETOUCH=m
CONFIG_USB_STORAGE_KARMA=m
CONFIG_USB_STORAGE_CYPRESS_ATACB=m
CONFIG_USB_STORAGE_ENE_UB6250=m
CONFIG_USB_UAS=y

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
CONFIG_USB_MICROTEK=m
CONFIG_USBIP_CORE=m
CONFIG_USBIP_VHCI_HCD=m
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=m
CONFIG_USBIP_VUDC=m
CONFIG_USBIP_DEBUG=y
CONFIG_USB_CDNS3=m
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_USB_CDNS3_PCI_WRAP=m
CONFIG_USB_MUSB_HDRC=m
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y

#
# Platform Glue Layer
#

#
# MUSB DMA mode
#
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y

#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=y
CONFIG_USB_DWC3_HAPS=y
CONFIG_USB_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC3_ROCKCHIP_INNO=y
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
CONFIG_USB_DWC2_PCI=m
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
# CONFIG_USB_CHIPIDEA is not set
# CONFIG_USB_ISP1760 is not set

#
# USB port drivers
#
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=y
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=y
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=y
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=y
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=y
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_F81232=m
CONFIG_USB_SERIAL_F8153X=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=y
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_METRO=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MXUPORT=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=y
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=m
CONFIG_USB_SERIAL_QUALCOMM=y
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
CONFIG_USB_SERIAL_SAFE_PADDED=y
CONFIG_USB_SERIAL_SIERRAWIRELESS=y
CONFIG_USB_SERIAL_SYMBOL=y
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_XIRCOM=m
CONFIG_USB_SERIAL_WWAN=y
CONFIG_USB_SERIAL_OPTION=y
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=y
CONFIG_USB_SERIAL_XSENS_MT=m
CONFIG_USB_SERIAL_WISHBONE=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_SERIAL_QT2=y
CONFIG_USB_SERIAL_UPD78F0730=m
# CONFIG_USB_SERIAL_DEBUG is not set

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
CONFIG_USB_CYPRESS_CY7C63=m
CONFIG_USB_CYTHERM=m
CONFIG_USB_IDMOUSE=m
CONFIG_USB_FTDI_ELAN=m
CONFIG_USB_APPLEDISPLAY=m
CONFIG_APPLE_MFI_FASTCHARGE=m
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
CONFIG_USB_TEST=m
CONFIG_USB_EHSET_TEST_FIXTURE=m
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=y
CONFIG_USB_HUB_USB251XB=m
CONFIG_USB_HSIC_USB3503=m
CONFIG_USB_HSIC_USB4604=m
CONFIG_USB_LINK_LAYER_TEST=m
CONFIG_USB_CHAOSKEY=m
CONFIG_USB_ONBOARD_HUB=y
CONFIG_USB_ATM=m
CONFIG_USB_SPEEDTOUCH=m
CONFIG_USB_CXACRU=m
CONFIG_USB_UEAGLEATM=m
CONFIG_USB_XUSBATM=m

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=m
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_ULPI is not set
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
CONFIG_USB_GADGET_DEBUG_FILES=y
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set

#
# USB Peripheral Controller
#
# CONFIG_USB_FOTG210_UDC is not set
# CONFIG_USB_GR_UDC is not set
# CONFIG_USB_R8A66597 is not set
# CONFIG_USB_PXA27X is not set
# CONFIG_USB_MV_UDC is not set
# CONFIG_USB_MV_U3D is not set
# CONFIG_USB_SNP_UDC_PLAT is not set
# CONFIG_USB_M66592 is not set
# CONFIG_USB_BDC_UDC is not set
# CONFIG_USB_AMD5536UDC is not set
# CONFIG_USB_NET2272 is not set
# CONFIG_USB_NET2280 is not set
# CONFIG_USB_GOKU is not set
# CONFIG_USB_EG20T is not set
# CONFIG_USB_GADGET_XILINX is not set
# CONFIG_USB_MAX3420_UDC is not set
# CONFIG_USB_DUMMY_HCD is not set
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_F_ACM=y
CONFIG_USB_F_SS_LB=y
CONFIG_USB_U_SERIAL=y
CONFIG_USB_U_ETHER=y
CONFIG_USB_U_AUDIO=y
CONFIG_USB_F_SERIAL=m
CONFIG_USB_F_OBEX=y
CONFIG_USB_F_NCM=y
CONFIG_USB_F_ECM=y
CONFIG_USB_F_EEM=y
CONFIG_USB_F_SUBSET=y
CONFIG_USB_F_RNDIS=y
CONFIG_USB_F_MASS_STORAGE=y
CONFIG_USB_F_FS=y
CONFIG_USB_F_UAC1=y
CONFIG_USB_F_UAC1_LEGACY=y
CONFIG_USB_F_UAC2=y
CONFIG_USB_F_UVC=y
CONFIG_USB_F_MIDI=y
CONFIG_USB_F_HID=y
CONFIG_USB_F_PRINTER=y
CONFIG_USB_F_ACC=y
CONFIG_USB_F_AUDIO_SRC=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_UEVENT=y
# CONFIG_USB_CONFIGFS_SERIAL is not set
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_LB_SS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_ACC=y
CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y

#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=m
# CONFIG_USB_ZERO_HNPTEST is not set
CONFIG_USB_AUDIO=m
# CONFIG_GADGET_UAC1 is not set
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
# CONFIG_USB_ETH_EEM is not set
CONFIG_USB_G_NCM=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
# CONFIG_USB_FUNCTIONFS_ETH is not set
# CONFIG_USB_FUNCTIONFS_RNDIS is not set
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
# CONFIG_USB_G_MULTI_CDC is not set
CONFIG_USB_G_HID=m
CONFIG_USB_G_DBGP=m
# CONFIG_USB_G_DBGP_PRINTK is not set
CONFIG_USB_G_DBGP_SERIAL=y
CONFIG_USB_G_WEBCAM=m
CONFIG_USB_RAW_GADGET=m
# end of USB Gadget precomposed configurations

CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
CONFIG_TYPEC_ET7303=y
CONFIG_TYPEC_HUSB311=y
CONFIG_TYPEC_RT1711H=y
CONFIG_TYPEC_TCPCI_MAXIM=y
CONFIG_TYPEC_FUSB302=y
CONFIG_TYPEC_UCSI=m
CONFIG_UCSI_CCG=m
CONFIG_UCSI_ACPI=m
CONFIG_TYPEC_HD3SS3220=m
CONFIG_TYPEC_TPS6598X=m
CONFIG_TYPEC_STUSB160X=m

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
CONFIG_TYPEC_MUX_PI3USB30532=m
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
CONFIG_TYPEC_DP_ALTMODE=y
# CONFIG_TYPEC_NVIDIA_ALTMODE is not set
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
# CONFIG_PWRSEQ_SD8787 is not set
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_SDIO_UART is not set
CONFIG_MMC_TEST=y

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_ARMMMCI is not set
CONFIG_MMC_SDHCI=y
# CONFIG_MMC_SDHCI_PCI is not set
# CONFIG_MMC_SDHCI_ACPI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
# CONFIG_MMC_SDHCI_OF_ASPEED is not set
# CONFIG_MMC_SDHCI_OF_AT91 is not set
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
# CONFIG_MMC_SDHCI_CADENCE is not set
# CONFIG_MMC_SDHCI_F_SDH30 is not set
# CONFIG_MMC_SDHCI_MILBEAUT is not set
# CONFIG_MMC_TIFM_SD is not set
# CONFIG_MMC_SPI is not set
# CONFIG_MMC_CB710 is not set
# CONFIG_MMC_VIA_SDMMC is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
# CONFIG_MMC_DW_BLUEFIELD is not set
# CONFIG_MMC_DW_EXYNOS is not set
# CONFIG_MMC_DW_HI3798CV200 is not set
# CONFIG_MMC_DW_K3 is not set
# CONFIG_MMC_DW_PCI is not set
CONFIG_MMC_DW_ROCKCHIP=y
# CONFIG_MMC_VUB300 is not set
# CONFIG_MMC_USHC is not set
# CONFIG_MMC_USDHI6ROL0 is not set
# CONFIG_MMC_REALTEK_USB is not set
CONFIG_MMC_CQHCI=y
CONFIG_MMC_HSQ=y
# CONFIG_MMC_TOSHIBA_PCI is not set
# CONFIG_MMC_MTK is not set
# CONFIG_MMC_SDHCI_XENON is not set
# CONFIG_MMC_SDHCI_OMAP is not set
# CONFIG_MMC_SDHCI_AM654 is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
CONFIG_LEDS_CLASS_MULTICOLOR=y
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y

#
# LED drivers
#
CONFIG_LEDS_AAT1290=m
CONFIG_LEDS_AN30259A=m
CONFIG_LEDS_AS3645A=m
CONFIG_LEDS_AW2013=m
CONFIG_LEDS_BCM6328=m
CONFIG_LEDS_BCM6358=m
CONFIG_LEDS_CR0014114=m
CONFIG_LEDS_EL15203000=m
CONFIG_LEDS_LM3530=m
CONFIG_LEDS_LM3532=m
CONFIG_LEDS_LM3642=m
CONFIG_LEDS_LM3692X=y
CONFIG_LEDS_LM3601X=y
CONFIG_LEDS_PCA9532=m
CONFIG_LEDS_PCA9532_GPIO=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=m
CONFIG_LEDS_LP3952=m
CONFIG_LEDS_LP50XX=m
CONFIG_LEDS_LP55XX_COMMON=m
CONFIG_LEDS_LP5521=m
CONFIG_LEDS_LP5523=m
CONFIG_LEDS_LP5562=m
CONFIG_LEDS_LP8501=m
CONFIG_LEDS_LP8860=m
CONFIG_LEDS_PCA955X=m
CONFIG_LEDS_PCA955X_GPIO=y
CONFIG_LEDS_PCA963X=m
CONFIG_LEDS_DAC124S085=m
CONFIG_LEDS_PWM=y
CONFIG_LEDS_REGULATOR=y
CONFIG_LEDS_BD2802=m
CONFIG_LEDS_LT3593=m
CONFIG_LEDS_TCA6507=m
CONFIG_LEDS_TLC591XX=m
CONFIG_LEDS_LM355x=m
CONFIG_LEDS_KTD2692=m
CONFIG_LEDS_IS31FL319X=m
CONFIG_LEDS_IS31FL32XX=m
CONFIG_LEDS_RGB13H=m

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=m
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_MLXREG=m
CONFIG_LEDS_USER=y
CONFIG_LEDS_SPI_BYTE=m
CONFIG_LEDS_TI_LMU_COMMON=m
CONFIG_LEDS_LM3697=m
CONFIG_LEDS_SGM3140=m

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
# CONFIG_LEDS_TRIGGER_MTD is not set
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
# CONFIG_LEDS_TRIGGER_CPU is not set
# CONFIG_LEDS_TRIGGER_ACTIVITY is not set
# CONFIG_LEDS_TRIGGER_GPIO is not set
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=y
# CONFIG_LEDS_TRIGGER_PATTERN is not set
# CONFIG_LEDS_TRIGGER_AUDIO is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
CONFIG_RTC_DRV_TEST=m

#
# I2C RTC drivers
#
CONFIG_RTC_DRV_ABB5ZES3=m
CONFIG_RTC_DRV_ABEOZ9=m
CONFIG_RTC_DRV_ABX80X=m
CONFIG_RTC_DRV_DS1307=m
CONFIG_RTC_DRV_DS1307_CENTURY=y
CONFIG_RTC_DRV_DS1374=m
CONFIG_RTC_DRV_DS1374_WDT=y
CONFIG_RTC_DRV_DS1672=m
CONFIG_RTC_DRV_HYM8563=y
CONFIG_RTC_DRV_MAX6900=m
CONFIG_RTC_DRV_RK808=y
CONFIG_RTC_DRV_ROCKCHIP=y
CONFIG_RTC_DRV_RS5C372=m
CONFIG_RTC_DRV_ISL1208=m
CONFIG_RTC_DRV_ISL12022=m
CONFIG_RTC_DRV_ISL12026=m
CONFIG_RTC_DRV_X1205=m
CONFIG_RTC_DRV_PCF8523=m
CONFIG_RTC_DRV_PCF85063=m
CONFIG_RTC_DRV_PCF85363=m
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_PCF8583=m
CONFIG_RTC_DRV_M41T80=m
CONFIG_RTC_DRV_M41T80_WDT=y
CONFIG_RTC_DRV_BQ32K=m
CONFIG_RTC_DRV_TPS6586X=m
CONFIG_RTC_DRV_S35390A=m
CONFIG_RTC_DRV_FM3130=m
CONFIG_RTC_DRV_RX8010=m
CONFIG_RTC_DRV_RX8581=m
CONFIG_RTC_DRV_RX8025=m
CONFIG_RTC_DRV_EM3027=m
CONFIG_RTC_DRV_RV3028=m
CONFIG_RTC_DRV_RV3032=m
CONFIG_RTC_DRV_RV8803=m
CONFIG_RTC_DRV_SD3078=m

#
# SPI RTC drivers
#
CONFIG_RTC_DRV_M41T93=m
CONFIG_RTC_DRV_M41T94=m
CONFIG_RTC_DRV_DS1302=m
CONFIG_RTC_DRV_DS1305=m
CONFIG_RTC_DRV_DS1343=m
CONFIG_RTC_DRV_DS1347=m
CONFIG_RTC_DRV_DS1390=m
CONFIG_RTC_DRV_MAX6916=m
CONFIG_RTC_DRV_R9701=m
CONFIG_RTC_DRV_RX4581=m
CONFIG_RTC_DRV_RX6110=m
CONFIG_RTC_DRV_RS5C348=m
CONFIG_RTC_DRV_MAX6902=m
CONFIG_RTC_DRV_PCF2123=m
CONFIG_RTC_DRV_MCP795=m
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
CONFIG_RTC_DRV_DS3232=m
CONFIG_RTC_DRV_DS3232_HWMON=y
CONFIG_RTC_DRV_PCF2127=m
CONFIG_RTC_DRV_RV3029C2=m
CONFIG_RTC_DRV_RV3029_HWMON=y

#
# Platform RTC drivers
#
CONFIG_RTC_DRV_DS1286=m
CONFIG_RTC_DRV_DS1511=m
CONFIG_RTC_DRV_DS1553=m
CONFIG_RTC_DRV_DS1685_FAMILY=m
CONFIG_RTC_DRV_DS1685=y
# CONFIG_RTC_DRV_DS1689 is not set
# CONFIG_RTC_DRV_DS17285 is not set
# CONFIG_RTC_DRV_DS17485 is not set
# CONFIG_RTC_DRV_DS17885 is not set
CONFIG_RTC_DRV_DS1742=m
CONFIG_RTC_DRV_DS2404=m
CONFIG_RTC_DRV_EFI=m
CONFIG_RTC_DRV_STK17TA8=m
CONFIG_RTC_DRV_M48T86=m
CONFIG_RTC_DRV_M48T35=m
CONFIG_RTC_DRV_M48T59=m
CONFIG_RTC_DRV_MSM6242=m
CONFIG_RTC_DRV_BQ4802=m
CONFIG_RTC_DRV_RP5C01=m
CONFIG_RTC_DRV_V3020=m
CONFIG_RTC_DRV_ZYNQMP=m

#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_PL030=y
CONFIG_RTC_DRV_PL031=y
CONFIG_RTC_DRV_CADENCE=m
CONFIG_RTC_DRV_FTRTC010=m
CONFIG_RTC_DRV_R7301=m

#
# HID Sensor RTC drivers
#
CONFIG_RTC_DRV_HID_SENSOR_TIME=m
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
CONFIG_AMBA_PL08X=y
# CONFIG_BCM_SBA_RAID is not set
CONFIG_DW_AXI_DMAC=m
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_HISI_DMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_MV_XOR_V2 is not set
CONFIG_PL330_DMA=y
# CONFIG_PLX_DMA is not set
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
# CONFIG_XILINX_ZYNQMP_DPDMA is not set
# CONFIG_QCOM_HIDMA_MGMT is not set
# CONFIG_QCOM_HIDMA is not set
# CONFIG_DW_DMAC is not set
# CONFIG_DW_DMAC_PCI is not set
# CONFIG_DW_EDMA is not set
# CONFIG_DW_EDMA_PCIE is not set
# CONFIG_SF_PDMA is not set

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set

#
# DMABUF options
#
CONFIG_DMABUF_CACHE=y
# CONFIG_RK_DMABUF_DEBUG is not set
CONFIG_DMABUF_PARTIAL=y
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_SW_SYNC_DEBUG=y
# CONFIG_UDMABUF is not set
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_SELFTESTS is not set
CONFIG_DMABUF_HEAPS=y
CONFIG_DMABUF_SYSFS_STATS=y
CONFIG_DMABUF_HEAPS_DEFERRED_FREE=y
CONFIG_DMABUF_HEAPS_PAGE_POOL=y
CONFIG_DMABUF_HEAPS_SYSTEM=y
CONFIG_DMABUF_HEAPS_CMA=y
# CONFIG_DMABUF_HEAPS_SRAM is not set
CONFIG_DMABUF_HEAPS_ROCKCHIP=y
CONFIG_DMABUF_HEAPS_ROCKCHIP_CMA_HEAP=y
CONFIG_DMABUF_HEAPS_ROCKCHIP_CMA_ALIGNMENT=8
# CONFIG_DMABUF_RK_HEAPS_DEBUG is not set
# CONFIG_DMABUF_RK_HEAPS_DEBUG_PRINT is not set
# end of DMABUF options

CONFIG_AUXDISPLAY=y
CONFIG_HD44780=m
CONFIG_IMG_ASCII_LCD=m
CONFIG_HT16K33=m
# CONFIG_PANEL_CHANGE_MESSAGE is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_CHARLCD=m
CONFIG_UIO=m
# CONFIG_UIO_CIF is not set
# CONFIG_UIO_PDRV_GENIRQ is not set
# CONFIG_UIO_DMEM_GENIRQ is not set
# CONFIG_UIO_AEC is not set
# CONFIG_UIO_SERCOS3 is not set
# CONFIG_UIO_PCI_GENERIC is not set
# CONFIG_UIO_NETX is not set
# CONFIG_UIO_PRUSS is not set
# CONFIG_UIO_MF624 is not set
# CONFIG_VFIO is not set
CONFIG_VIRT_DRIVERS=y
CONFIG_VIRTIO=m
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=m
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
# CONFIG_VDPA is not set
CONFIG_VHOST_IOTLB=m
CONFIG_VHOST=m
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_VSOCK=m
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set

#
# Microsoft Hyper-V guest support
#
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
CONFIG_STAGING=y
# CONFIG_PRISM2_USB is not set
# CONFIG_COMEDI is not set
CONFIG_RTL8192U=m
CONFIG_RTLLIB=m
CONFIG_RTLLIB_CRYPTO_CCMP=m
CONFIG_RTLLIB_CRYPTO_TKIP=m
CONFIG_RTLLIB_CRYPTO_WEP=m
CONFIG_RTL8192E=m
CONFIG_R8712U=m
CONFIG_RTS5208=m
CONFIG_VT6655=m
CONFIG_VT6656=m

#
# IIO staging drivers
#

#
# Accelerometers
#
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16240 is not set
# end of Accelerometers

#
# Analog to digital converters
#
# CONFIG_AD7816 is not set
# CONFIG_AD7280 is not set
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
# CONFIG_ADT7316 is not set
# end of Analog digital bi-direction converters

#
# Capacitance to digital converters
#
# CONFIG_AD7150 is not set
# CONFIG_AD7746 is not set
# end of Capacitance to digital converters

#
# Direct Digital Synthesis
#
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
# CONFIG_AD5933 is not set
# end of Network Analyzer, Impedance Converters

#
# Active energy metering IC
#
# CONFIG_ADE7854 is not set
# end of Active energy metering IC

#
# Resolver to digital converters
#
# CONFIG_AD2S1210 is not set
# end of Resolver to digital converters
# end of IIO staging drivers

# CONFIG_FB_SM750 is not set
CONFIG_STAGING_MEDIA=y
# CONFIG_VIDEO_HANTRO is not set
CONFIG_VIDEO_ROCKCHIP_VDEC=y
# CONFIG_VIDEO_ZORAN is not set
CONFIG_VIDEO_ROCKCHIP_ISP1=y

#
# Android
#
CONFIG_ASHMEM=y
# CONFIG_DEBUG_KINFO is not set
# CONFIG_ION is not set
# end of Android

# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
# CONFIG_GS_FPGABOOT is not set
# CONFIG_UNISYSSPAR is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
CONFIG_FB_TFT=m
# CONFIG_FB_TFT_AGM1264K_FL is not set
# CONFIG_FB_TFT_BD663474 is not set
# CONFIG_FB_TFT_HX8340BN is not set
# CONFIG_FB_TFT_HX8347D is not set
# CONFIG_FB_TFT_HX8353D is not set
# CONFIG_FB_TFT_HX8357D is not set
# CONFIG_FB_TFT_ILI9163 is not set
# CONFIG_FB_TFT_ILI9320 is not set
# CONFIG_FB_TFT_ILI9325 is not set
# CONFIG_FB_TFT_ILI9340 is not set
# CONFIG_FB_TFT_ILI9341 is not set
# CONFIG_FB_TFT_ILI9481 is not set
# CONFIG_FB_TFT_ILI9486 is not set
# CONFIG_FB_TFT_PCD8544 is not set
# CONFIG_FB_TFT_RA8875 is not set
# CONFIG_FB_TFT_S6D02A1 is not set
# CONFIG_FB_TFT_S6D1121 is not set
# CONFIG_FB_TFT_SEPS525 is not set
# CONFIG_FB_TFT_SH1106 is not set
# CONFIG_FB_TFT_SSD1289 is not set
# CONFIG_FB_TFT_SSD1305 is not set
# CONFIG_FB_TFT_SSD1306 is not set
# CONFIG_FB_TFT_SSD1331 is not set
# CONFIG_FB_TFT_SSD1351 is not set
CONFIG_FB_TFT_ST7735R=m
# CONFIG_FB_TFT_ST7789V is not set
# CONFIG_FB_TFT_TINYLCD is not set
# CONFIG_FB_TFT_TLS8204 is not set
# CONFIG_FB_TFT_UC1611 is not set
# CONFIG_FB_TFT_UC1701 is not set
# CONFIG_FB_TFT_UPD161704 is not set
# CONFIG_FB_TFT_WATTEROTT is not set
# CONFIG_KS7010 is not set
# CONFIG_PI433 is not set

#
# Gasket devices
#
# CONFIG_STAGING_GASKET_FRAMEWORK is not set
# end of Gasket devices

# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_KPC2000 is not set
# CONFIG_QLGE is not set
# CONFIG_WFX is not set
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
CONFIG_HAVE_CLK=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
# CONFIG_COMMON_CLK_PROCFS is not set

#
# Clock driver for ARM Reference designs
#
# CONFIG_ICST is not set
# CONFIG_CLK_SP810 is not set
# end of Clock driver for ARM Reference designs

# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
# CONFIG_CLK_QORIQ is not set
# CONFIG_COMMON_CLK_XGENE is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
CONFIG_COMMON_CLK_ROCKCHIP=y
CONFIG_CLK_PX30=y
CONFIG_CLK_RK1808=y
CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
CONFIG_CLK_RK3399=y
CONFIG_CLK_RK3528=y
CONFIG_CLK_RK3562=y
CONFIG_CLK_RK3568=y
CONFIG_CLK_RK3588=y
CONFIG_ROCKCHIP_CLK_COMPENSATION=y
CONFIG_ROCKCHIP_CLK_LINK=y
CONFIG_ROCKCHIP_CLK_BOOST=y
CONFIG_ROCKCHIP_CLK_INV=y
CONFIG_ROCKCHIP_CLK_OUT=y
CONFIG_ROCKCHIP_CLK_PVTM=y
CONFIG_ROCKCHIP_DDRCLK=y
CONFIG_ROCKCHIP_DDRCLK_SIP=y
CONFIG_ROCKCHIP_DDRCLK_SIP_V2=y
CONFIG_ROCKCHIP_PLL_RK3066=y
CONFIG_ROCKCHIP_PLL_RK3399=y
CONFIG_ROCKCHIP_PLL_RK3588=y
CONFIG_COMMON_CLK_ROCKCHIP_REGMAP=m
CONFIG_CLK_RK618=m
CONFIG_CLK_RK628=m
# CONFIG_HWSPINLOCK is not set

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_ACPI=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_ROCKCHIP_TIMER=y
# CONFIG_SUN4I_TIMER is not set
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
# CONFIG_MTK_TIMER is not set
# CONFIG_MICROCHIP_PIT64B is not set
# end of Clock Source drivers

CONFIG_MAILBOX=y
# CONFIG_ARM_MHU is not set
# CONFIG_PLATFORM_MHU is not set
# CONFIG_PL320_MBOX is not set
CONFIG_ROCKCHIP_MBOX=y
# CONFIG_ROCKCHIP_MBOX_DEMO is not set
CONFIG_PCC=y
# CONFIG_ALTERA_MBOX is not set
# CONFIG_MAILBOX_TEST is not set
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
# CONFIG_IOMMU_LIMIT_IOVA_ALIGNMENT is not set
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set
CONFIG_ARM_SMMU_V3=y
CONFIG_ARM_SMMU_V3_SVA=y
CONFIG_VIRTIO_IOMMU=m

#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=m
CONFIG_RPMSG_CHAR=m
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
CONFIG_RPMSG_ROCKCHIP=m
# CONFIG_RPMSG_ROCKCHIP_TEST is not set
CONFIG_RPMSG_VIRTIO=m
# end of Rpmsg drivers

# CONFIG_SOUNDWIRE is not set

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
# end of Amlogic SoC drivers

#
# Aspeed SoC drivers
#
# end of Aspeed SoC drivers

#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
# CONFIG_QUICC_ENGINE is not set
# CONFIG_FSL_RCPM is not set
# end of NXP/Freescale QorIQ SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Qualcomm SoC drivers
#
CONFIG_QCOM_QMI_HELPERS=m
# end of Qualcomm SoC drivers

#
# Rockchip SoC drivers
#

#
# Rockchip CPU selection
#
CONFIG_CPU_PX30=y
CONFIG_CPU_RK1808=y
CONFIG_CPU_RK3308=y
CONFIG_CPU_RK3328=y
CONFIG_CPU_RK3368=y
CONFIG_CPU_RK3399=y
CONFIG_CPU_RK3528=y
CONFIG_CPU_RK3562=y
CONFIG_CPU_RK3568=y
CONFIG_CPU_RK3588=y
# end of Rockchip CPU selection

CONFIG_NO_GKI=y
CONFIG_ROCKCHIP_AMP=m
CONFIG_ROCKCHIP_ARM64_ALIGN_FAULT_FIX=y
CONFIG_ROCKCHIP_CPUINFO=y
CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_ROCKCHIP_HW_DECOMPRESS_USER=y
CONFIG_ROCKCHIP_IODOMAIN=y
# CONFIG_ROCKCHIP_IOMUX is not set
CONFIG_ROCKCHIP_IPA=y
CONFIG_ROCKCHIP_OPP=y
# CONFIG_ROCKCHIP_OPTIMIZE_RT_PRIO is not set
CONFIG_ROCKCHIP_PERFORMANCE=y
CONFIG_ROCKCHIP_PERFORMANCE_LEVEL=2
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ROCKCHIP_PVTM=y
# CONFIG_ROCKCHIP_RAMDISK is not set
CONFIG_ROCKCHIP_SUSPEND_MODE=y
CONFIG_ROCKCHIP_SYSTEM_MONITOR=y
CONFIG_ROCKCHIP_VENDOR_STORAGE=y
CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE=y
CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=y
CONFIG_ROCKCHIP_RAM_VENDOR_STORAGE=y
CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER=y

#
# FIQ Debugger
#
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
# CONFIG_FIQ_DEBUGGER_WAKEUP_IRQ_ALWAYS_ON is not set
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y
# CONFIG_FIQ_DEBUGGER_UART_OVERLAY is not set
CONFIG_RK_CONSOLE_THREAD=y
CONFIG_ROCKCHIP_FIQ_DEBUGGER=y
# end of FIQ Debugger

CONFIG_ROCKCHIP_DEBUG=y
# CONFIG_ROCKCHIP_MINI_KERNEL is not set
# CONFIG_ROCKCHIP_THUNDER_BOOT is not set
CONFIG_ROCKCHIP_NPOR_POWERGOOD=y
CONFIG_RK_CMA_PROCFS=y
CONFIG_RK_DMABUF_PROCFS=y
CONFIG_RK_MEMBLOCK_PROCFS=y

#
# Rockchip Minidump drivers
#
# CONFIG_ROCKCHIP_MINIDUMP is not set
# end of Rockchip Minidump drivers
# end of Rockchip SoC drivers

# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# CONFIG_XILINX_VCU is not set
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEVFREQ_GOV_PASSIVE=y

#
# DEVFREQ Drivers
#
CONFIG_ARM_ROCKCHIP_BUS_DEVFREQ=y
CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_NOCP=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
# CONFIG_EXTCON_ADC_JACK is not set
# CONFIG_EXTCON_FSA9480 is not set
# CONFIG_EXTCON_GPIO is not set
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_PTN5150 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
# CONFIG_EXTCON_USB_GPIO is not set
CONFIG_EXTCON_USBC_VIRTUAL_PD=y
# CONFIG_MEMORY is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
CONFIG_IIO_BUFFER_DMA=m
CONFIG_IIO_BUFFER_DMAENGINE=m
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
CONFIG_IIO_TRIGGERED_EVENT=m

#
# Accelerometers
#
CONFIG_ADIS16201=m
CONFIG_ADIS16209=m
CONFIG_ADXL372=m
CONFIG_ADXL372_SPI=m
CONFIG_ADXL372_I2C=m
CONFIG_BMA220=m
CONFIG_BMA400=m
CONFIG_BMA400_I2C=m
CONFIG_BMA400_SPI=m
CONFIG_BMC150_ACCEL=m
CONFIG_BMC150_ACCEL_I2C=m
CONFIG_BMC150_ACCEL_SPI=m
CONFIG_DA280=m
CONFIG_DA311=m
CONFIG_DMARD06=m
CONFIG_DMARD09=m
CONFIG_DMARD10=m
CONFIG_HID_SENSOR_ACCEL_3D=m
CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
CONFIG_KXSD9=m
CONFIG_KXSD9_SPI=m
CONFIG_KXSD9_I2C=m
CONFIG_KXCJK1013=m
CONFIG_MC3230=m
CONFIG_MMA7455=m
CONFIG_MMA7455_I2C=m
CONFIG_MMA7455_SPI=m
CONFIG_MMA7660=m
CONFIG_MMA8452=m
CONFIG_MMA9551_CORE=m
CONFIG_MMA9551=m
CONFIG_MMA9553=m
CONFIG_MXC4005=m
CONFIG_MXC6255=m
CONFIG_SCA3000=m
CONFIG_STK8312=m
CONFIG_STK8BA50=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=m
CONFIG_AD7091R5=m
CONFIG_AD7124=m
CONFIG_AD7192=m
CONFIG_AD7266=m
CONFIG_AD7291=m
CONFIG_AD7292=m
CONFIG_AD7298=m
CONFIG_AD7476=m
CONFIG_AD7606=m
CONFIG_AD7606_IFACE_PARALLEL=m
CONFIG_AD7606_IFACE_SPI=m
CONFIG_AD7766=m
CONFIG_AD7768_1=m
CONFIG_AD7780=m
CONFIG_AD7791=m
CONFIG_AD7793=m
CONFIG_AD7887=m
CONFIG_AD7923=m
CONFIG_AD7949=m
CONFIG_AD799X=m
CONFIG_AD9467=m
CONFIG_ADI_AXI_ADC=m
CONFIG_CC10001_ADC=m
CONFIG_ENVELOPE_DETECTOR=m
CONFIG_HI8435=m
CONFIG_HX711=m
CONFIG_INA2XX_ADC=m
CONFIG_LTC2471=m
CONFIG_LTC2485=m
CONFIG_LTC2496=m
CONFIG_LTC2497=m
CONFIG_MAX1027=m
CONFIG_MAX11100=m
CONFIG_MAX1118=m
CONFIG_MAX1241=m
CONFIG_MAX1363=m
CONFIG_MAX9611=m
CONFIG_MCP320X=m
CONFIG_MCP3422=m
CONFIG_MCP3911=m
CONFIG_NAU7802=m
CONFIG_ROCKCHIP_SARADC=y
# CONFIG_ROCKCHIP_SARADC_TEST_CHN is not set
CONFIG_SD_ADC_MODULATOR=m
CONFIG_TI_ADC081C=m
CONFIG_TI_ADC0832=m
CONFIG_TI_ADC084S021=m
CONFIG_TI_ADC12138=m
CONFIG_TI_ADC108S102=m
CONFIG_TI_ADC128S052=m
CONFIG_TI_ADC161S626=m
CONFIG_TI_ADS1015=m
CONFIG_TI_ADS7950=m
CONFIG_TI_ADS8344=m
CONFIG_TI_ADS8688=m
CONFIG_TI_ADS124S08=m
CONFIG_TI_TLC4541=m
CONFIG_VF610_ADC=m
CONFIG_XILINX_XADC=m
# end of Analog to digital converters

#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=m
# end of Analog Front Ends

#
# Amplifiers
#
CONFIG_AD8366=m
CONFIG_HMC425=m
# end of Amplifiers

#
# Chemical Sensors
#
CONFIG_ATLAS_PH_SENSOR=m
CONFIG_ATLAS_EZO_SENSOR=m
CONFIG_BME680=m
CONFIG_BME680_I2C=m
CONFIG_BME680_SPI=m
CONFIG_CCS811=m
CONFIG_IAQCORE=m
CONFIG_SCD30_CORE=m
CONFIG_SCD30_I2C=m
CONFIG_SENSIRION_SGP30=m
CONFIG_SPS30=m
CONFIG_VZ89X=m
# end of Chemical Sensors

#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
# end of Hid Sensor IIO Common

CONFIG_IIO_MS_SENSORS_I2C=m

#
# SSP Sensor Common
#
CONFIG_IIO_SSP_SENSORS_COMMONS=m
CONFIG_IIO_SSP_SENSORHUB=m
# end of SSP Sensor Common

CONFIG_IIO_ST_SENSORS_I2C=m
CONFIG_IIO_ST_SENSORS_SPI=m
CONFIG_IIO_ST_SENSORS_CORE=m

#
# Digital to analog converters
#
CONFIG_AD5064=m
CONFIG_AD5360=m
CONFIG_AD5380=m
CONFIG_AD5421=m
CONFIG_AD5446=m
CONFIG_AD5449=m
CONFIG_AD5592R_BASE=m
CONFIG_AD5592R=m
CONFIG_AD5593R=m
CONFIG_AD5504=m
CONFIG_AD5624R_SPI=m
CONFIG_AD5686=m
CONFIG_AD5686_SPI=m
CONFIG_AD5696_I2C=m
CONFIG_AD5755=m
CONFIG_AD5758=m
CONFIG_AD5761=m
CONFIG_AD5764=m
CONFIG_AD5770R=m
CONFIG_AD5791=m
CONFIG_AD7303=m
CONFIG_AD8801=m
CONFIG_DPOT_DAC=m
CONFIG_DS4424=m
CONFIG_LTC1660=m
CONFIG_LTC2632=m
CONFIG_M62332=m
CONFIG_MAX517=m
CONFIG_MAX5821=m
CONFIG_MCP4725=m
CONFIG_MCP4922=m
CONFIG_TI_DAC082S085=m
CONFIG_TI_DAC5571=m
CONFIG_TI_DAC7311=m
CONFIG_TI_DAC7612=m
CONFIG_VF610_DAC=m
# end of Digital to analog converters

#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
CONFIG_AD9523=m
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4350=m
CONFIG_ADF4371=m
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=m
CONFIG_ADIS16130=m
CONFIG_ADIS16136=m
CONFIG_ADIS16260=m
CONFIG_ADXRS290=m
CONFIG_ADXRS450=m
CONFIG_BMG160=m
CONFIG_BMG160_I2C=m
CONFIG_BMG160_SPI=m
CONFIG_FXAS21002C=m
CONFIG_FXAS21002C_I2C=m
CONFIG_FXAS21002C_SPI=m
CONFIG_HID_SENSOR_GYRO_3D=m
CONFIG_MPU3050=m
CONFIG_MPU3050_I2C=m
CONFIG_IIO_ST_GYRO_3AXIS=m
CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
CONFIG_ITG3200=m
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
CONFIG_AFE4403=m
CONFIG_AFE4404=m
CONFIG_MAX30100=m
CONFIG_MAX30102=m
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
CONFIG_AM2315=m
CONFIG_DHT11=m
CONFIG_HDC100X=m
CONFIG_HDC2010=m
CONFIG_HID_SENSOR_HUMIDITY=m
CONFIG_HTS221=m
CONFIG_HTS221_I2C=m
CONFIG_HTS221_SPI=m
CONFIG_HTU21=m
CONFIG_SI7005=m
CONFIG_SI7020=m
# end of Humidity sensors

#
# Inertial measurement units
#
CONFIG_ADIS16400=m
CONFIG_ADIS16460=m
CONFIG_ADIS16475=m
CONFIG_ADIS16480=m
CONFIG_BMI160=m
CONFIG_BMI160_I2C=m
CONFIG_BMI160_SPI=m
CONFIG_FXOS8700=m
CONFIG_FXOS8700_I2C=m
CONFIG_FXOS8700_SPI=m
CONFIG_KMX61=m
CONFIG_INV_ICM42600=m
CONFIG_INV_ICM42600_I2C=m
CONFIG_INV_ICM42600_SPI=m
CONFIG_INV_MPU6050_IIO=m
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_SPI=m
# CONFIG_IIO_ST_LSM6DSR is not set
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_LSM6DSX_I2C=m
CONFIG_IIO_ST_LSM6DSX_SPI=m
# end of Inertial measurement units

CONFIG_IIO_ADIS_LIB=m
CONFIG_IIO_ADIS_LIB_BUFFER=y

#
# Light sensors
#
CONFIG_ACPI_ALS=m
CONFIG_ADJD_S311=m
CONFIG_ADUX1020=m
CONFIG_AL3010=m
CONFIG_AL3320A=m
CONFIG_APDS9300=m
CONFIG_APDS9960=m
CONFIG_AS73211=m
CONFIG_BH1750=m
CONFIG_BH1780=m
CONFIG_CM32181=m
CONFIG_CM3232=m
CONFIG_CM3323=m
CONFIG_CM3605=m
CONFIG_CM36651=m
CONFIG_GP2AP002=m
CONFIG_GP2AP020A00F=m
CONFIG_SENSORS_ISL29018=m
CONFIG_SENSORS_ISL29028=m
CONFIG_ISL29125=m
CONFIG_HID_SENSOR_ALS=m
CONFIG_HID_SENSOR_PROX=m
CONFIG_JSA1212=m
CONFIG_RPR0521=m
CONFIG_LTR501=m
CONFIG_LV0104CS=m
CONFIG_MAX44000=m
CONFIG_MAX44009=m
CONFIG_NOA1305=m
CONFIG_OPT3001=m
CONFIG_PA12203001=m
CONFIG_SI1133=m
CONFIG_SI1145=m
CONFIG_STK3310=m
CONFIG_ST_UVIS25=m
CONFIG_ST_UVIS25_I2C=m
CONFIG_ST_UVIS25_SPI=m
CONFIG_TCS3414=m
CONFIG_TCS3472=m
CONFIG_SENSORS_TSL2563=m
CONFIG_TSL2583=m
CONFIG_TSL2772=m
CONFIG_TSL4531=m
# CONFIG_UCS12CM0 is not set
CONFIG_US5182D=m
CONFIG_VCNL4000=m
CONFIG_VCNL4035=m
CONFIG_VEML6030=m
CONFIG_VEML6070=m
CONFIG_VL6180=m
CONFIG_ZOPT2201=m
# end of Light sensors

#
# Magnetometer sensors
#
CONFIG_AK8974=m
CONFIG_AK8975=m
CONFIG_AK09911=m
CONFIG_BMC150_MAGN=m
CONFIG_BMC150_MAGN_I2C=m
CONFIG_BMC150_MAGN_SPI=m
CONFIG_MAG3110=m
CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
CONFIG_MMC35240=m
CONFIG_IIO_ST_MAGN_3AXIS=m
CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
CONFIG_SENSORS_HMC5843=m
CONFIG_SENSORS_HMC5843_I2C=m
CONFIG_SENSORS_HMC5843_SPI=m
CONFIG_SENSORS_RM3100=m
CONFIG_SENSORS_RM3100_I2C=m
CONFIG_SENSORS_RM3100_SPI=m
# end of Magnetometer sensors

#
# Multiplexers
#
CONFIG_IIO_MUX=m
# end of Multiplexers

#
# Inclinometer sensors
#
CONFIG_HID_SENSOR_INCLINOMETER_3D=m
CONFIG_HID_SENSOR_DEVICE_ROTATION=m
# end of Inclinometer sensors

#
# Triggers - standalone
#
# CONFIG_IIO_HRTIMER_TRIGGER is not set
CONFIG_IIO_INTERRUPT_TRIGGER=y
# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set
CONFIG_IIO_SYSFS_TRIGGER=y
# end of Triggers - standalone

#
# Linear and angular position sensors
#
# end of Linear and angular position sensors

#
# Digital potentiometers
#
CONFIG_AD5272=m
CONFIG_DS1803=m
CONFIG_MAX5432=m
CONFIG_MAX5481=m
CONFIG_MAX5487=m
CONFIG_MCP4018=m
CONFIG_MCP4131=m
CONFIG_MCP4531=m
CONFIG_MCP41010=m
CONFIG_TPL0102=m
# end of Digital potentiometers

#
# Digital potentiostats
#
CONFIG_LMP91000=m
# end of Digital potentiostats

#
# Pressure sensors
#
CONFIG_ABP060MG=m
CONFIG_BMP280=m
CONFIG_BMP280_I2C=m
CONFIG_BMP280_SPI=m
CONFIG_DLHL60D=m
CONFIG_DPS310=m
CONFIG_HID_SENSOR_PRESS=m
CONFIG_HP03=m
CONFIG_ICP10100=m
CONFIG_MPL115=m
CONFIG_MPL115_I2C=m
CONFIG_MPL115_SPI=m
CONFIG_MPL3115=m
CONFIG_MS5611=m
CONFIG_MS5611_I2C=m
CONFIG_MS5611_SPI=m
CONFIG_MS5637=m
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_PRESS_I2C=m
CONFIG_IIO_ST_PRESS_SPI=m
CONFIG_T5403=m
CONFIG_HP206C=m
CONFIG_ZPA2326=m
CONFIG_ZPA2326_I2C=m
CONFIG_ZPA2326_SPI=m
# end of Pressure sensors

#
# Lightning sensors
#
CONFIG_AS3935=m
# end of Lightning sensors

#
# Proximity and distance sensors
#
CONFIG_ISL29501=m
CONFIG_LIDAR_LITE_V2=m
CONFIG_MB1232=m
CONFIG_PING=m
CONFIG_RFD77402=m
CONFIG_SRF04=m
CONFIG_SX9310=m
CONFIG_SX9500=m
CONFIG_SRF08=m
CONFIG_VCNL3020=m
CONFIG_VL53L0X_I2C=m
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
CONFIG_AD2S90=m
CONFIG_AD2S1200=m
# end of Resolver to digital converters

#
# Temperature sensors
#
CONFIG_LTC2983=m
CONFIG_MAXIM_THERMOCOUPLE=m
CONFIG_HID_SENSOR_TEMP=m
CONFIG_MLX90614=m
CONFIG_MLX90632=m
CONFIG_TMP006=m
CONFIG_TMP007=m
CONFIG_TSYS01=m
CONFIG_TSYS02D=m
CONFIG_MAX31856=m
# end of Temperature sensors

# CONFIG_NTB is not set
# CONFIG_VME_BUS is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_FSL_FTM is not set
CONFIG_PWM_GPIO=m
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_ROCKCHIP=y
# CONFIG_PWM_ROCKCHIP_ONESHOT is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_AL_FIC is not set
CONFIG_PARTITION_PERCPU=y
# end of IRQ chip support

# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_SCMI=y
# CONFIG_RESET_TI_SYSCON is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_PHY_XGENE is not set
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_FSL_IMX8MQ_USB is not set
# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y
CONFIG_PHY_ROCKCHIP_DP=y
CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_COMBPHY=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_USB3=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
CONFIG_PHY_ROCKCHIP_MIPI_RX=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
CONFIG_PHY_ROCKCHIP_NANENG_EDP=y
CONFIG_PHY_ROCKCHIP_NANENG_USB2=y
CONFIG_PHY_ROCKCHIP_PCIE=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PHY_ROCKCHIP_USB=y
CONFIG_PHY_ROCKCHIP_USBDP=y
# CONFIG_PHY_SAMSUNG_USB2 is not set
# end of PHY Subsystem

# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCI400_PMU=y
CONFIG_ARM_CCI5xx_PMU=y
CONFIG_ARM_CCN=m
CONFIG_ARM_CMN=m
CONFIG_ARM_PMU=y
CONFIG_ARM_PMU_ACPI=y
CONFIG_ARM_SMMU_V3_PMU=m
CONFIG_ARM_DSU_PMU=m
CONFIG_ARM_SPE_PMU=m
# CONFIG_HISI_PMU is not set
# end of Performance monitor support

# CONFIG_RAS is not set
# CONFIG_USB4 is not set

#
# Android
#
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_BINDERFS=y
CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
# CONFIG_ANDROID_DEBUG_SYMBOLS is not set
# CONFIG_ANDROID_VENDOR_HOOKS is not set
CONFIG_ANDROID_KABI_RESERVE=y
CONFIG_ANDROID_VENDOR_OEM_DATA=y
# end of Android

# CONFIG_LIBNVDIMM is not set
CONFIG_DAX=y
# CONFIG_DEV_DAX is not set
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
# CONFIG_RK628_EFUSE is not set
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_NVMEM_ROCKCHIP_SEC_OTP=y

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# end of HW tracing support

# CONFIG_FPGA is not set
# CONFIG_FSI is not set
CONFIG_TEE=y

#
# TEE drivers
#
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
# end of TEE drivers

CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
# CONFIG_MUX_ADGS1408 is not set
# CONFIG_MUX_GPIO is not set
# CONFIG_MUX_MMIO is not set
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set
# CONFIG_INTERCONNECT is not set
# CONFIG_COUNTER is not set
# CONFIG_MOST is not set
# CONFIG_RK_FLASH is not set
# CONFIG_RK_NAND is not set

#
# Headset device support
#
CONFIG_RK_HEADSET=y
# end of Headset device support

#
# RKNPU
#
CONFIG_ROCKCHIP_RKNPU=m
CONFIG_ROCKCHIP_RKNPU_DEBUG_FS=y
CONFIG_ROCKCHIP_RKNPU_PROC_FS=y
CONFIG_ROCKCHIP_RKNPU_FENCE=y
CONFIG_ROCKCHIP_RKNPU_SRAM=y
CONFIG_ROCKCHIP_RKNPU_DRM_GEM=y
# CONFIG_ROCKCHIP_RKNPU_DMA_HEAP is not set
# end of RKNPU
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_IOMAP=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=y
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
# CONFIG_JFS_FS is not set
CONFIG_XFS_FS=y
CONFIG_XFS_SUPPORT_V4=y
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
CONFIG_XFS_RT=y
# CONFIG_XFS_ONLINE_SCRUB is not set
CONFIG_XFS_WARN=y
# CONFIG_XFS_DEBUG is not set
CONFIG_GFS2_FS=m
# CONFIG_GFS2_FS_LOCKING_DLM is not set
CONFIG_OCFS2_FS=m
CONFIG_OCFS2_FS_O2CB=m
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
CONFIG_OCFS2_FS_STATS=y
CONFIG_OCFS2_DEBUG_MASKLOG=y
# CONFIG_OCFS2_DEBUG_FS is not set
CONFIG_BTRFS_FS=y
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
# CONFIG_BTRFS_FS_REF_VERIFY is not set
# CONFIG_NILFS2_FS is not set
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
# CONFIG_F2FS_FAULT_INJECTION is not set
CONFIG_F2FS_FS_COMPRESSION=y
CONFIG_F2FS_FS_LZO=y
CONFIG_F2FS_FS_LZ4=y
CONFIG_F2FS_FS_LZ4HC=y
CONFIG_F2FS_FS_ZSTD=y
CONFIG_F2FS_FS_LZORLE=y
# CONFIG_ZONEFS_FS is not set
CONFIG_FS_DAX=y
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_MANDATORY_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_PRINT_QUOTA_WARNING is not set
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
# CONFIG_AUTOFS4_FS is not set
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=m
CONFIG_CUSE=m
CONFIG_VIRTIO_FS=m
CONFIG_OVERLAY_FS=m
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set
CONFIG_INCREMENTAL_FS=m

#
# Caches
#
CONFIG_FSCACHE=m
# CONFIG_FSCACHE_STATS is not set
# CONFIG_FSCACHE_HISTOGRAM is not set
# CONFIG_FSCACHE_DEBUG is not set
# CONFIG_FSCACHE_OBJECT_LIST is not set
CONFIG_CACHEFILES=m
# CONFIG_CACHEFILES_DEBUG is not set
# CONFIG_CACHEFILES_HISTOGRAM is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=936
CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_EXFAT_FS=y
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_NTFS_FS is not set
CONFIG_NTFS3_FS=m
# CONFIG_NTFS3_64BIT_CLUSTER is not set
CONFIG_NTFS3_LZX_XPRESS=y
# CONFIG_NTFS3_FS_POSIX_ACL is not set
# end of DOS/FAT/EXFAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_TMPFS_INODE64 is not set
# CONFIG_HUGETLBFS is not set
CONFIG_MEMFD_CREATE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=y
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
CONFIG_ECRYPT_FS=m
# CONFIG_ECRYPT_FS_MESSAGING is not set
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
CONFIG_JFFS2_SUMMARY=y
# CONFIG_JFFS2_FS_XATTR is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
CONFIG_UBIFS_FS=m
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
# CONFIG_CRAMFS is not set
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_FILE_CACHE=y
# CONFIG_SQUASHFS_FILE_DIRECT is not set
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_ZSTD=y
CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
# CONFIG_SQUASHFS_EMBEDDED is not set
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFLATE_COMPRESS=y
CONFIG_PSTORE_LZO_COMPRESS=y
CONFIG_PSTORE_LZ4_COMPRESS=y
CONFIG_PSTORE_LZ4HC_COMPRESS=y
CONFIG_PSTORE_842_COMPRESS=y
CONFIG_PSTORE_ZSTD_COMPRESS=y
CONFIG_PSTORE_COMPRESS=y
# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT=y
CONFIG_PSTORE_COMPRESS_DEFAULT="zstd"
CONFIG_PSTORE_CONSOLE=y
# CONFIG_PSTORE_PMSG is not set
CONFIG_PSTORE_RAM=y
# CONFIG_PSTORE_BOOT_LOG is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_EROFS_FS=m
# CONFIG_EROFS_FS_DEBUG is not set
CONFIG_EROFS_FS_XATTR=y
CONFIG_EROFS_FS_POSIX_ACL=y
CONFIG_EROFS_FS_SECURITY=y
CONFIG_EROFS_FS_ZIP=y
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V2=m
CONFIG_NFS_V3=m
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=m
CONFIG_NFS_SWAP=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=m
CONFIG_PNFS_BLOCK=m
CONFIG_PNFS_FLEXFILE_LAYOUT=m
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
CONFIG_NFS_V4_1_MIGRATION=y
CONFIG_NFS_V4_SECURITY_LABEL=y
CONFIG_NFS_FSCACHE=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
CONFIG_NFS_V4_2_READ_PLUS=y
CONFIG_NFSD=m
CONFIG_NFSD_V2_ACL=y
CONFIG_NFSD_V3=y
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
# CONFIG_NFSD_BLOCKLAYOUT is not set
# CONFIG_NFSD_SCSILAYOUT is not set
# CONFIG_NFSD_FLEXFILELAYOUT is not set
# CONFIG_NFSD_V4_2_INTER_SSC is not set
# CONFIG_NFSD_V4_SECURITY_LABEL is not set
CONFIG_SMB_SERVER=m
CONFIG_SMB_INSECURE_SERVER=y
CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
# CONFIG_SMB_SERVER_KERBEROS5 is not set
CONFIG_GRACE_PERIOD=m
CONFIG_LOCKD=m
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=m
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=m
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_BACKCHANNEL=y
CONFIG_SUNRPC_SWAP=y
CONFIG_RPCSEC_GSS_KRB5=m
# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
# CONFIG_SUNRPC_DEBUG is not set
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
# CONFIG_CEPH_FS_SECURITY_LABEL is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
CONFIG_CIFS_WEAK_PW_HASH=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
# CONFIG_CIFS_DEBUG is not set
CONFIG_CIFS_DFS_UPCALL=y
# CONFIG_CIFS_FSCACHE is not set
CONFIG_CODA_FS=m
CONFIG_AFS_FS=m
# CONFIG_AFS_DEBUG is not set
# CONFIG_AFS_FSCACHE is not set
# CONFIG_AFS_DEBUG_CURSOR is not set
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
# CONFIG_9P_FS_SECURITY is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=m
CONFIG_NLS_MAC_GAELIC=m
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=y
CONFIG_DLM=m
# CONFIG_DLM_DEBUG is not set
CONFIG_UNICODE=y
# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_TRUSTED_KEYS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
# CONFIG_SECURITY_NETWORK_XFRM is not set
CONFIG_SECURITY_PATH=y
CONFIG_LSM_MMAP_MIN_ADDR=32768
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_SECURITY_SELINUX=y
# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set
# CONFIG_SECURITY_SELINUX_DISABLE is not set
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
CONFIG_SECURITY_APPARMOR=y
CONFIG_SECURITY_APPARMOR_HASH=y
CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
# CONFIG_SECURITY_APPARMOR_DEBUG is not set
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
CONFIG_INTEGRITY_AUDIT=y
# CONFIG_IMA is not set
# CONFIG_EVM is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor "

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
CONFIG_INIT_STACK_NONE=y
# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
# CONFIG_INIT_STACK_ALL_PATTERN is not set
# CONFIG_INIT_STACK_ALL_ZERO is not set
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
# end of Memory initialization
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=y
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_FIPS140=y
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=m
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
# CONFIG_CRYPTO_USER is not set
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_CRYPTD=m
CONFIG_CRYPTO_AUTHENC=m
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_ENGINE=m

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=m
CONFIG_CRYPTO_ECC=m
CONFIG_CRYPTO_ECDH=m
CONFIG_CRYPTO_ECRDSA=m
CONFIG_CRYPTO_SM2=y
CONFIG_CRYPTO_CURVE25519=y

#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_AEGIS128=y
CONFIG_CRYPTO_AEGIS128_SIMD=y
CONFIG_CRYPTO_SEQIV=m
CONFIG_CRYPTO_ECHAINIV=m

#
# Block modes
#
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_KEYWRAP=m
CONFIG_CRYPTO_NHPOLY1305=y
CONFIG_CRYPTO_ADIANTUM=m
CONFIG_CRYPTO_ESSIV=m

#
# Hash modes
#
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_VMAC=m

#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_XXHASH=y
CONFIG_CRYPTO_BLAKE2B=y
CONFIG_CRYPTO_BLAKE2S=m
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_RMD128=m
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_RMD256=m
CONFIG_CRYPTO_RMD320=m
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_STREEBOG=m
CONFIG_CRYPTO_TGR192=m
CONFIG_CRYPTO_WP512=m

#
# Ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_BLOWFISH_COMMON=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST_COMMON=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SALSA20=m
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=y
CONFIG_CRYPTO_ZSTD=y

#
# Random Number Generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=m
CONFIG_CRYPTO_DRBG_HMAC=y
# CONFIG_CRYPTO_DRBG_HASH is not set
# CONFIG_CRYPTO_DRBG_CTR is not set
CONFIG_CRYPTO_DRBG=m
CONFIG_CRYPTO_JITTERENTROPY=m
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=m
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_CCP is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_ROCKCHIP=m
CONFIG_CRYPTO_DEV_ROCKCHIP_V1=y
CONFIG_CRYPTO_DEV_ROCKCHIP_V2=y
CONFIG_CRYPTO_DEV_ROCKCHIP_V3=y
# CONFIG_CRYPTO_DEV_ROCKCHIP_DEV is not set
CONFIG_CRYPTO_DEV_VIRTIO=m
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
# CONFIG_CRYPTO_DEV_CCREE is not set
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_PKCS7_TEST_KEY is not set
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_RAID6_PQ=y
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=m
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
# CONFIG_INDIRECT_PIO is not set

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=m
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=m
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
CONFIG_CRYPTO_LIB_CURVE25519=m
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=m
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines

CONFIG_LIB_MEMNEQ=y
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=m
CONFIG_CRC4=m
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=m
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
# CONFIG_XZ_DEC_SPARC is not set
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_INTERVAL_TREE=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_SWIOTLB=y
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y
# CONFIG_DMA_PERNUMA_CMA is not set

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=256
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
CONFIG_SGL_ALLOC=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
CONFIG_IRQ_POLL=y
CONFIG_MPILIB=y
CONFIG_DIMLIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_ARCH_STACKWALK=y
CONFIG_SBITMAP=y
CONFIG_PARMAN=m
CONFIG_OBJAGG=m
# CONFIG_STRING_SELFTEST is not set
# end of Library routines

CONFIG_PLDMFW=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER is not set
# CONFIG_PRINTK_CALLER is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_INFO_REDUCED is not set
CONFIG_DEBUG_INFO_COMPRESSED=y
# CONFIG_DEBUG_INFO_SPLIT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
CONFIG_DEBUG_INFO_BTF=y
# CONFIG_GDB_SCRIPTS is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=2048
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_READABLE_ASM is not set
CONFIG_HEADERS_INSTALL=y
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_KCSAN_COMPILER=y
# end of Generic Kernel Debugging Instruments

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_PINNER is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
# end of Memory Debugging

# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SOFTLOCKUP_DETECTOR is not set
CONFIG_HAVE_HARDLOCKUP_DETECTOR_OTHER_CPU=y
# CONFIG_HARDLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHED_INFO=y
# CONFIG_SCHEDSTATS is not set
# end of Scheduler Debugging

# CONFIG_DEBUG_TIMEKEEPING is not set
CONFIG_DEBUG_PREEMPT=y

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

CONFIG_STACKTRACE=y
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_HAVE_DEBUG_BUGVERBOSE=y

#
# Debug kernel data structures
#
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# end of Debug kernel data structures

# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
# CONFIG_RCU_SCALE_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
# CONFIG_BOOTPARAM_RCU_STALL_PANIC is not set
CONFIG_BOOTPARAM_RCU_STALL_PANIC_VALUE=0
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
# CONFIG_LATENCYTOP is not set
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
# CONFIG_TRACE_MMIO_ACCESS is not set
# CONFIG_TRACEFS_DISABLE_AUTOMOUNT is not set
CONFIG_TRACING=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_BOOTTIME_TRACING is not set
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_PREEMPT_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_HWLAT_TRACER is not set
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
# CONFIG_FTRACE_SYSCALLS is not set
# CONFIG_TRACER_SNAPSHOT is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_KPROBE_EVENTS=y
CONFIG_UPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_DYNAMIC_EVENTS=y
CONFIG_PROBE_EVENTS=y
# CONFIG_SYNTH_EVENTS is not set
# CONFIG_HIST_TRIGGERS is not set
# CONFIG_TRACE_EVENT_INJECT is not set
# CONFIG_TRACEPOINT_BENCHMARK is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_TRACE_EVAL_MAP_FILE is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
# CONFIG_KPROBE_EVENT_GEN_TEST is not set
# CONFIG_SAMPLES is not set
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
# CONFIG_STRICT_DEVMEM is not set

#
# arm64 Debugging
#
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_DEBUG_EFI is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
# end of arm64 Debugging

#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FUNCTION_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_LKDTM is not set
# CONFIG_TEST_LIST_SORT is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_SORT is not set
# CONFIG_KPROBES_SANITY_TEST is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_ASYNC_RAID6_TEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_STRSCPY is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_OVERFLOW is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_HASH is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_PARMAN is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_VMALLOC is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_BPF is not set
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_OBJAGG is not set
# CONFIG_TEST_STACKINIT is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_FREE_PAGES is not set
CONFIG_MEMTEST=y
# end of Kernel Testing and Coverage
# end of Kernel hacking


================================================
FILE: kernel-config/release/rk35xx/config-6.1
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 6.1.141 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 15.2.Rel1 (Build arm-15.86)) 15.2.1 20251203"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=150201
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=24501
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=24501
CONFIG_LLD_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_PAHOLE_VERSION=130
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
# CONFIG_UAPI_HEADER_TEST is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT="/sbin/init"
CONFIG_DEFAULT_HOSTNAME="none"
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
# CONFIG_WATCH_QUEUE is not set
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_USELIB is not set
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_SIM=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem

CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
# CONFIG_NO_HZ_FULL is not set
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y

#
# BPF subsystem
#
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_JIT=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
CONFIG_BPF_JIT_DEFAULT_ON=y
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
CONFIG_USERMODE_DRIVER=y
CONFIG_BPF_PRELOAD=y
CONFIG_BPF_PRELOAD_UMD=y
# CONFIG_BPF_LSM is not set
# end of BPF subsystem

CONFIG_PREEMPT_VOLUNTARY_BUILD=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
# CONFIG_PREEMPT_DYNAMIC is not set

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_SCHED_THERMAL_PRESSURE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
# CONFIG_PRINTK_INDEX is not set
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
CONFIG_UCLAMP_TASK=y
CONFIG_UCLAMP_BUCKETS_COUNT=20
# end of Scheduler features

CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_CC_HAS_INT128=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_GCC10_NO_ARRAY_BOUNDS=y
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_UCLAMP_TASK_GROUP=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
CONFIG_CGROUP_MISC=y
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_SCHED_AUTOGROUP=y
# CONFIG_SYSFS_DEPRECATED is not set
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
# CONFIG_BOOT_CONFIG_EMBED is not set
CONFIG_INITRAMFS_PRESERVE_MTIME=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
# CONFIG_SGETMASK_SYSCALL is not set
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_GUEST_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
# end of General setup

CONFIG_ARM64=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_CONT_PTE_SHIFT=4
CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y

#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
# CONFIG_ARCH_SUNXI is not set
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_APPLE is not set
# CONFIG_ARCH_BCM is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SPARX5 is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_KEEMBAY is not set
# CONFIG_ARCH_MEDIATEK is not set
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_NXP is not set
# CONFIG_ARCH_NPCM is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_RENESAS is not set
CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_INTEL_SOCFPGA is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZYNQMP is not set
# end of Platform selection

#
# Kernel Features
#

#
# ARM errata workarounds via the alternatives framework
#
CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_834220=y
CONFIG_ARM64_ERRATUM_1742098=y
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1319367=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_ERRATUM_2441007=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_ARM64_ERRATUM_2051678=y
CONFIG_ARM64_ERRATUM_2077057=y
CONFIG_ARM64_ERRATUM_2658417=y
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
CONFIG_ARM64_ERRATUM_2054223=y
CONFIG_ARM64_ERRATUM_2067961=y
CONFIG_ARM64_ERRATUM_2441009=y
CONFIG_ARM64_ERRATUM_2457168=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y
CONFIG_ARM64_ERRATUM_2966298=y
CONFIG_ARM64_ERRATUM_3194386=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
CONFIG_QCOM_FALKOR_ERRATUM_1009=y
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
# end of ARM errata workarounds via the alternatives framework

CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
# CONFIG_ARM64_VA_BITS_39 is not set
CONFIG_ARM64_VA_BITS_48=y
CONFIG_ARM64_VA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SCHED_MC=y
# CONFIG_SCHED_CLUSTER is not set
# CONFIG_SCHED_SMT is not set
CONFIG_NR_CPUS=8
CONFIG_HOTPLUG_CPU=y
# CONFIG_NUMA is not set
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
CONFIG_HZ_300=y
# CONFIG_HZ_1000 is not set
CONFIG_HZ=300
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_KEXEC is not set
# CONFIG_KEXEC_FILE is not set
# CONFIG_CRASH_DUMP is not set
# CONFIG_XEN is not set
CONFIG_ARCH_FORCE_MAX_ORDER=11
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_ARM64_SW_TTBR0_PAN=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y
# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y

#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
CONFIG_AS_HAS_LDAPR=y
CONFIG_AS_HAS_LSE_ATOMICS=y
CONFIG_ARM64_LSE_ATOMICS=y
CONFIG_ARM64_USE_LSE_ATOMICS=y
# end of ARMv8.1 architectural features

#
# ARMv8.2 architectural features
#
CONFIG_AS_HAS_ARMV8_2=y
CONFIG_AS_HAS_SHA3=y
# CONFIG_ARM64_PMEM is not set
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features

#
# ARMv8.3 architectural features
#
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
CONFIG_AS_HAS_PAC=y
CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
# end of ARMv8.3 architectural features

#
# ARMv8.4 architectural features
#
CONFIG_ARM64_AMU_EXTN=y
CONFIG_AS_HAS_ARMV8_4=y
CONFIG_ARM64_TLB_RANGE=y
# end of ARMv8.4 architectural features

#
# ARMv8.5 architectural features
#
CONFIG_AS_HAS_ARMV8_5=y
CONFIG_ARM64_BTI=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARM64_AS_HAS_MTE=y
CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features

#
# ARMv8.7 architectural features
#
CONFIG_ARM64_EPAN=y
# end of ARMv8.7 architectural features

CONFIG_ARM64_SVE=y
CONFIG_ARM64_MODULE_PLTS=y
CONFIG_ARM64_PSEUDO_NMI=y
# CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set
CONFIG_RELOCATABLE=y
CONFIG_RANDOMIZE_BASE=y
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
CONFIG_ARCH_NR_GPIO=0
# end of Kernel Features

#
# Boot options
#
CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
CONFIG_CMDLINE=""
CONFIG_EFI_STUB=y
CONFIG_EFI=y
CONFIG_DMI=y
# end of Boot options

#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
# CONFIG_HIBERNATION is not set
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
# CONFIG_PM_TEST_SUSPEND is not set
CONFIG_PM_SLEEP_DEBUG=y
CONFIG_DPM_WATCHDOG=y
CONFIG_DPM_WATCHDOG_TIMEOUT=120
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options

#
# CPU Power Management
#

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
# CONFIG_CPU_IDLE_GOV_LADDER is not set
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_DT_IDLE_STATES=y
CONFIG_DT_IDLE_GENPD=y

#
# ARM CPU Idle Drivers
#
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
# end of ARM CPU Idle Drivers
# end of CPU Idle

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_INTERACTIVE=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_ACPI_CPPC_CPUFREQ=y
CONFIG_ACPI_CPPC_CPUFREQ_FIE=y
CONFIG_ARM_ROCKCHIP_CPUFREQ=y
CONFIG_ARM_SCMI_CPUFREQ=y
# end of CPU Frequency scaling
# end of CPU Power Management

CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_GENERIC_GSI=y
CONFIG_ACPI_CCA_REQUIRED=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
CONFIG_ACPI_EC_DEBUGFS=m
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
# CONFIG_ACPI_VIDEO is not set
CONFIG_ACPI_FAN=y
CONFIG_ACPI_TAD=m
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_MCFG=y
CONFIG_ACPI_CPPC_LIB=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_HOTPLUG_CPU=y
CONFIG_ACPI_THERMAL=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_PCI_SLOT=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_CUSTOM_METHOD=m
CONFIG_ACPI_BGRT=y
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
CONFIG_HAVE_ACPI_APEI=y
CONFIG_ACPI_APEI=y
CONFIG_ACPI_APEI_GHES=y
CONFIG_ACPI_APEI_SEA=y
CONFIG_ACPI_APEI_EINJ=m
CONFIG_ACPI_APEI_ERST_DEBUG=m
CONFIG_ACPI_CONFIGFS=m
# CONFIG_ACPI_PFRUT is not set
CONFIG_ACPI_IORT=y
CONFIG_ACPI_GTDT=y
# CONFIG_ACPI_AGDI is not set
CONFIG_ACPI_PPTT=y
CONFIG_ACPI_PCC=y
CONFIG_PMIC_OPREGION=y
CONFIG_ACPI_VIOT=y
CONFIG_ACPI_PRMT=y
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_HAVE_KVM=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_MMIO=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_KVM_XFER_TO_GUEST_WORK=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
# CONFIG_NVHE_EL2_DEBUG is not set
CONFIG_CPU_MITIGATIONS=y

#
# General architecture-dependent options
#
CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y
CONFIG_KPROBES=y
# CONFIG_JUMP_LABEL is not set
CONFIG_UPROBES=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
# CONFIG_SECCOMP_CACHE_DEBUG is not set
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
# CONFIG_SHADOW_CALL_STACK is not set
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
CONFIG_HAVE_CONTEXT_TRACKING_USER=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_ARCH_HUGE_VMALLOC=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET=y
# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
CONFIG_HAVE_PREEMPT_DYNAMIC=y
CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
CONFIG_MODULE_COMPRESS_NONE=y
# CONFIG_MODULE_COMPRESS_GZIP is not set
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BLK_RQ_ALLOC_TIME=y
CONFIG_BLK_CGROUP_RWSTAT=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_ICQ=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=y
CONFIG_BLK_DEV_ZONED=y
CONFIG_BLK_DEV_THROTTLING=y
# CONFIG_BLK_DEV_THROTTLING_LOW is not set
CONFIG_BLK_WBT=y
CONFIG_BLK_WBT_MQ=y
CONFIG_BLK_CGROUP_IOLATENCY=y
# CONFIG_BLK_CGROUP_FC_APPID is not set
CONFIG_BLK_CGROUP_IOCOST=y
CONFIG_BLK_CGROUP_IOPRIO=y
CONFIG_BLK_DEBUG_FS=y
CONFIG_BLK_DEBUG_FS_ZONED=y
CONFIG_BLK_SED_OPAL=y
# CONFIG_BLK_INLINE_ENCRYPTION is not set

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_AIX_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
CONFIG_CMDLINE_PARTITION=y
# end of Partition Types

CONFIG_BLOCK_COMPAT=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_HOLDER_DEPRECATED=y
CONFIG_BLK_MQ_STACKING=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
# CONFIG_BFQ_CGROUP_DEBUG is not set
# end of IO Schedulers

CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK=y
CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_READ_LOCK=y
CONFIG_ARCH_INLINE_READ_LOCK_BH=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_READ_UNLOCK=y
CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_WRITE_LOCK=y
CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_SPIN_TRYLOCK=y
CONFIG_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_INLINE_SPIN_LOCK=y
CONFIG_INLINE_SPIN_LOCK_BH=y
CONFIG_INLINE_SPIN_LOCK_IRQ=y
CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_INLINE_SPIN_UNLOCK_BH=y
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_READ_LOCK=y
CONFIG_INLINE_READ_LOCK_BH=y
CONFIG_INLINE_READ_LOCK_IRQ=y
CONFIG_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_INLINE_READ_UNLOCK=y
CONFIG_INLINE_READ_UNLOCK_BH=y
CONFIG_INLINE_READ_UNLOCK_IRQ=y
CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_WRITE_LOCK=y
CONFIG_INLINE_WRITE_LOCK_BH=y
CONFIG_INLINE_WRITE_LOCK_IRQ=y
CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_INLINE_WRITE_UNLOCK=y
CONFIG_INLINE_WRITE_UNLOCK_BH=y
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_HAVE_ELF_PROT=y
CONFIG_ARCH_USE_GNU_PROPERTY=y
CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=y
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_SWAP=y
# CONFIG_ZSWAP is not set
CONFIG_ZSMALLOC=y
# CONFIG_ZSMALLOC_STAT is not set

#
# SLAB allocator options
#
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
# CONFIG_SLAB_FREELIST_RANDOM is not set
# CONFIG_SLAB_FREELIST_HARDENED is not set
CONFIG_SLUB_SYSFS=y
# CONFIG_SLUB_STATS is not set
# CONFIG_SLUB_CPU_PARTIAL is not set
# end of SLAB allocator options

CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_THP_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PCP_BATCH_SCALE_MAX=5
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_MMU_NOTIFIER=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
# CONFIG_MEMORY_FAILURE is not set
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_TRANSPARENT_HUGEPAGE=y
# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set
CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
CONFIG_THP_SWAP=y
# CONFIG_READ_ONLY_THP_FOR_FS is not set
CONFIG_CMA=y
# CONFIG_CMA_INACTIVE is not set
# CONFIG_CMA_DEBUG is not set
CONFIG_CMA_DEBUGFS=y
CONFIG_CMA_DEBUGFS_BITMAP_HEX=y
CONFIG_CMA_SYSFS=y
CONFIG_CMA_AREAS=7
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
CONFIG_PAGE_IDLE_FLAG=y
CONFIG_IDLE_PAGE_TRACKING=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_ARCH_HAS_ZONE_DMA_SET=y
CONFIG_ZONE_DMA=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_PERCPU_STATS=y
# CONFIG_GUP_TEST is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_SECRETMEM=y
# CONFIG_ANON_VMA_NAME is not set
# CONFIG_USERFAULTFD is not set
CONFIG_LRU_GEN=y
CONFIG_LRU_GEN_ENABLED=y
# CONFIG_LRU_GEN_STATS is not set
CONFIG_LOCK_MM_AND_FIND_VMA=y

#
# Data Access Monitoring
#
# CONFIG_DAMON is not set
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_EXTENSIONS=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_AF_UNIX_OOB=y
CONFIG_UNIX_DIAG=y
CONFIG_TLS=m
CONFIG_TLS_DEVICE=y
CONFIG_TLS_TOE=y
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
CONFIG_XFRM_INTERFACE=m
CONFIG_XFRM_SUB_POLICY=y
CONFIG_XFRM_MIGRATE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_XFRM_AH=m
CONFIG_XFRM_ESP=m
CONFIG_XFRM_IPCOMP=m
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_XFRM_ESPINTCP=y
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
# CONFIG_IP_FIB_TRIE_STATS is not set
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_ROUTE_CLASSID=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=m
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=m
CONFIG_NET_FOU=m
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_ESP_OFFLOAD=m
CONFIG_INET_ESPINTCP=y
CONFIG_INET_IPCOMP=m
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_DIAG=m
CONFIG_INET_TCP_DIAG=m
CONFIG_INET_UDP_DIAG=m
CONFIG_INET_RAW_DIAG=m
# CONFIG_INET_DIAG_DESTROY is not set
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_NV=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_CONG_DCTCP=m
CONFIG_TCP_CONG_CDG=m
CONFIG_TCP_CONG_BBR=m
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=m
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_ESP_OFFLOAD=m
CONFIG_INET6_ESPINTCP=y
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_MIP6=m
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=m
CONFIG_INET6_TUNNEL=m
CONFIG_IPV6_VTI=m
CONFIG_IPV6_SIT=m
CONFIG_IPV6_SIT_6RD=y
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=m
CONFIG_IPV6_GRE=m
CONFIG_IPV6_FOU=m
CONFIG_IPV6_FOU_TUNNEL=m
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
# CONFIG_IPV6_SEG6_HMAC is not set
# CONFIG_IPV6_RPL_LWTUNNEL is not set
# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
CONFIG_NETLABEL=y
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=m
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NETWORK_PHY_TIMESTAMPING=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_EGRESS=y
CONFIG_NETFILTER_SKIP_EGRESS=y
CONFIG_NETFILTER_NETLINK=y
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
# CONFIG_NETFILTER_NETLINK_HOOK is not set
CONFIG_NETFILTER_NETLINK_ACCT=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NETFILTER_NETLINK_OSF=m
CONFIG_NF_CONNTRACK=y
CONFIG_NF_LOG_SYSLOG=m
CONFIG_NETFILTER_CONNCOUNT=m
CONFIG_NF_CONNTRACK_MARK=y
# CONFIG_NF_CONNTRACK_SECMARK is not set
CONFIG_NF_CONNTRACK_ZONES=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y
# CONFIG_NF_CONNTRACK_TIMEOUT is not set
CONFIG_NF_CONNTRACK_TIMESTAMP=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=y
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=y
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_FULLCONE=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_OBJREF=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
CONFIG_NFT_OSF=m
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NF_DUP_NETDEV=y
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NFT_REJECT_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
# CONFIG_NF_FLOW_TABLE_PROCFS is not set
CONFIG_NETFILTER_XTABLES=y
CONFIG_NETFILTER_XTABLES_COMPAT=y

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=y
CONFIG_NETFILTER_XT_CONNMARK=y
CONFIG_NETFILTER_XT_SET=m

#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_AUDIT=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LED=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=y
CONFIG_NETFILTER_XT_TARGET_NETMAP=y
CONFIG_NETFILTER_XT_TARGET_FULLCONENAT=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD=m
CONFIG_NETFILTER_XT_TARGET_RATEEST=y
CONFIG_NETFILTER_XT_TARGET_REDIRECT=y
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
CONFIG_NETFILTER_XT_TARGET_SECMARK=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=y
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=y
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# end of Core Netfilter Configuration

CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
# CONFIG_IP_VS_DEBUG is not set
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m
# CONFIG_IP_VS_TWOS is not set

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_SOCKET_IPV4=m
CONFIG_NF_TPROXY_IPV4=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=m
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_FULLCONENAT=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_SECURITY=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP6_NF_SECURITY=m
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=y
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_NFT_BRIDGE_META=m
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
# CONFIG_BPFILTER is not set
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m

#
# DCCP CCIDs Configuration
#
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
CONFIG_IP_DCCP_CCID3=y
# CONFIG_IP_DCCP_CCID3_DEBUG is not set
CONFIG_IP_DCCP_TFRC_LIB=y
# end of DCCP CCIDs Configuration

#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
# end of DCCP Kernel Hacking

CONFIG_IP_SCTP=m
# CONFIG_SCTP_DBG_OBJCNT is not set
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=m
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
CONFIG_L2TP=m
# CONFIG_L2TP_DEBUGFS is not set
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=m
CONFIG_L2TP_ETH=m
CONFIG_STP=m
CONFIG_GARP=m
CONFIG_MRP=m
CONFIG_BRIDGE=m
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_BRIDGE_MRP=y
CONFIG_BRIDGE_CFM=y
CONFIG_NET_DSA=m
CONFIG_NET_DSA_TAG_AR9331=m
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
CONFIG_NET_DSA_TAG_BRCM=m
CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
CONFIG_NET_DSA_TAG_HELLCREEK=m
CONFIG_NET_DSA_TAG_GSWIP=m
CONFIG_NET_DSA_TAG_DSA_COMMON=m
CONFIG_NET_DSA_TAG_DSA=m
CONFIG_NET_DSA_TAG_EDSA=m
CONFIG_NET_DSA_TAG_MTK=m
CONFIG_NET_DSA_TAG_KSZ=m
CONFIG_NET_DSA_TAG_OCELOT=m
# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set
CONFIG_NET_DSA_TAG_QCA=m
CONFIG_NET_DSA_TAG_RTL4_A=m
CONFIG_NET_DSA_TAG_RTL8_4=m
# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set
CONFIG_NET_DSA_TAG_LAN9303=m
CONFIG_NET_DSA_TAG_SJA1105=m
CONFIG_NET_DSA_TAG_TRAILER=m
CONFIG_NET_DSA_TAG_XRS700X=m
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q_MVRP=y
CONFIG_LLC=m
CONFIG_LLC2=m
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
CONFIG_6LOWPAN=m
# CONFIG_6LOWPAN_DEBUGFS is not set
CONFIG_6LOWPAN_NHC=m
CONFIG_6LOWPAN_NHC_DEST=m
CONFIG_6LOWPAN_NHC_FRAGMENT=m
CONFIG_6LOWPAN_NHC_HOP=m
CONFIG_6LOWPAN_NHC_IPV6=m
CONFIG_6LOWPAN_NHC_MOBILITY=m
CONFIG_6LOWPAN_NHC_ROUTING=m
CONFIG_6LOWPAN_NHC_UDP=m
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
CONFIG_6LOWPAN_GHC_UDP=m
CONFIG_6LOWPAN_GHC_ICMPV6=m
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
CONFIG_IEEE802154=m
# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set
CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_MAC802154=m
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFB=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_SKBPRIO=m
CONFIG_NET_SCH_CHOKE=m
CONFIG_NET_SCH_QFQ=m
CONFIG_NET_SCH_CODEL=m
CONFIG_NET_SCH_FQ_CODEL=y
CONFIG_NET_SCH_CAKE=m
CONFIG_NET_SCH_FQ=m
CONFIG_NET_SCH_HHF=m
CONFIG_NET_SCH_PIE=m
CONFIG_NET_SCH_FQ_PIE=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_SCH_PLUG=m
CONFIG_NET_SCH_ETS=m
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
# CONFIG_CLS_U32_PERF is not set
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=m
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_EMATCH_CANID=m
CONFIG_NET_EMATCH_IPSET=m
CONFIG_NET_EMATCH_IPT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
# CONFIG_NET_ACT_SAMPLE is not set
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
CONFIG_NET_ACT_MPLS=m
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_NET_ACT_CONNMARK=m
CONFIG_NET_ACT_CTINFO=m
CONFIG_NET_ACT_SKBMOD=m
CONFIG_NET_ACT_IFE=m
CONFIG_NET_ACT_TUNNEL_KEY=m
# CONFIG_NET_ACT_CT is not set
CONFIG_NET_ACT_GATE=m
CONFIG_NET_IFE_SKBMARK=m
CONFIG_NET_IFE_SKBPRIO=m
CONFIG_NET_IFE_SKBTCINDEX=m
# CONFIG_NET_TC_SKB_EXT is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=y
CONFIG_BATMAN_ADV=m
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
# CONFIG_BATMAN_ADV_NC is not set
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUG is not set
# CONFIG_BATMAN_ADV_TRACING is not set
CONFIG_OPENVSWITCH=m
CONFIG_OPENVSWITCH_GRE=m
CONFIG_OPENVSWITCH_VXLAN=m
CONFIG_OPENVSWITCH_GENEVE=m
CONFIG_VSOCKETS=m
CONFIG_VSOCKETS_DIAG=m
CONFIG_VSOCKETS_LOOPBACK=m
CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO_VSOCKETS_COMMON=m
CONFIG_NETLINK_DIAG=y
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=m
# CONFIG_MPLS_ROUTING is not set
CONFIG_NET_NSH=m
# CONFIG_HSR is not set
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=m
# CONFIG_QRTR_SMD is not set
# CONFIG_QRTR_TUN is not set
CONFIG_QRTR_MHI=m
# CONFIG_NET_NCSI is not set
CONFIG_PCPU_DEV_REFCNT=y
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_XPS=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_NET_DROP_MONITOR is not set
# end of Network testing
# end of Networking options

# CONFIG_HAMRADIO is not set
CONFIG_CAN=m
CONFIG_CAN_RAW=m
CONFIG_CAN_BCM=m
CONFIG_CAN_GW=m
# CONFIG_CAN_J1939 is not set
# CONFIG_CAN_ISOTP is not set
CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=m
CONFIG_BT_LE=y
CONFIG_BT_LE_L2CAP_ECRED=y
CONFIG_BT_6LOWPAN=m
CONFIG_BT_LEDS=y
CONFIG_BT_MSFTEXT=y
# CONFIG_BT_AOSPEXT is not set
CONFIG_BT_DEBUGFS=y
# CONFIG_BT_SELFTEST is not set

#
# Bluetooth device drivers
#
CONFIG_AIC8800_BTSDIO_SUPPORT=m
CONFIG_AIC8800_BTUSB_SUPPORT=m
CONFIG_BT_INTEL=m
CONFIG_BT_BCM=m
CONFIG_BT_RTL=m
CONFIG_BT_QCA=m
CONFIG_BT_MTK=m
CONFIG_BT_HCIBTUSB=m
CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y
CONFIG_BT_HCIBTUSB_POLL_SYNC=y
CONFIG_BT_HCIBTUSB_BCM=y
CONFIG_BT_HCIBTUSB_MTK=y
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
# CONFIG_BT_HCIUART_NOKIA is not set
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_RTL=y
CONFIG_BT_HCIUART_QCA=y
CONFIG_BT_HCIUART_AG6XX=y
CONFIG_BT_HCIUART_MRVL=y
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBCM4377=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
CONFIG_BT_MTKSDIO=m
CONFIG_BT_MTKUART=m
CONFIG_BT_VIRTIO=m
CONFIG_BT_HCIBTUSB_RTLBTUSB=m
CONFIG_BT_INTEL_PCIE=m
# end of Bluetooth device drivers

CONFIG_AF_RXRPC=m
# CONFIG_AF_RXRPC_IPV6 is not set
# CONFIG_AF_RXRPC_INJECT_LOSS is not set
# CONFIG_AF_RXRPC_DEBUG is not set
# CONFIG_RXKAD is not set
# CONFIG_AF_KCM is not set
CONFIG_STREAM_PARSER=y
# CONFIG_MCTP is not set
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_SPY=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
CONFIG_CFG80211_HEADERS=y
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_CFG80211_WEXT_EXPORT=y
CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
CONFIG_LIB80211_CRYPT_TKIP=m
# CONFIG_LIB80211_DEBUG is not set
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
# CONFIG_MAC80211_MESH is not set
CONFIG_MAC80211_LEDS=y
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_MESSAGE_TRACING is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_RFKILL=y
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=y
CONFIG_RFKILL_RK=y
CONFIG_NET_9P=m
CONFIG_NET_9P_FD=m
CONFIG_NET_9P_VIRTIO=m
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
CONFIG_CEPH_LIB=m
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
# CONFIG_NFC is not set
# CONFIG_PSAMPLE is not set
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_SOCK_VALIDATE_XMIT=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
# CONFIG_PAGE_POOL_STATS is not set
CONFIG_FAILOVER=m
CONFIG_SHORTCUT_FE=y
CONFIG_ETHTOOL_NETLINK=y

#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIEAER is not set
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIEASPM_EXT is not set
CONFIG_PCIE_PME=y
# CONFIG_PCIE_PTM is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_STUB is not set
# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set
CONFIG_PCI_ECAM=y
# CONFIG_PCI_IOV is not set
# CONFIG_PCI_PRI is not set
# CONFIG_PCI_PASID is not set
CONFIG_PCI_LABEL=y
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
# CONFIG_VGA_ARB is not set
# CONFIG_HOTPLUG_PCI is not set

#
# PCI controller drivers
#
# CONFIG_PCI_FTPCI100 is not set
# CONFIG_PCI_HOST_GENERIC is not set
# CONFIG_PCIE_XILINX is not set
# CONFIG_PCI_XGENE is not set
# CONFIG_PCIE_ALTERA is not set
# CONFIG_PCI_HOST_THUNDER_PEM is not set
# CONFIG_PCI_HOST_THUNDER_ECAM is not set
CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_HOST=y
CONFIG_PCIE_ROCKCHIP_EP=y
CONFIG_ROCKCHIP_PCIE_DMA_OBJ=y
# CONFIG_PCIE_MICROCHIP_HOST is not set
# CONFIG_PCIE_HISI_ERR is not set

#
# DesignWare PCI Core Support
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_EP=y
CONFIG_PCIE_DW_PLAT=y
CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCIE_DW_PLAT_EP=y
CONFIG_PCIE_DW_ROCKCHIP=y
# CONFIG_PCIE_RK_THREADED_INIT is not set
CONFIG_PCIE_DW_ROCKCHIP_EP=y
# CONFIG_PCI_HISI is not set
# CONFIG_PCIE_KIRIN is not set
# CONFIG_PCI_MESON is not set
# CONFIG_PCIE_AL is not set
# end of DesignWare PCI Core Support

#
# Mobiveil PCIe Core Support
#
# end of Mobiveil PCIe Core Support

#
# Cadence PCIe controllers support
#
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCIE_CADENCE_PLAT_EP is not set
# CONFIG_PCI_J721E_HOST is not set
# CONFIG_PCI_J721E_EP is not set
# end of Cadence PCIe controllers support
# end of PCI controller drivers

#
# PCI Endpoint
#
CONFIG_PCI_ENDPOINT=y
# CONFIG_PCI_ENDPOINT_CONFIGFS is not set
# CONFIG_PCI_EPF_TEST is not set
# CONFIG_PCI_EPF_NTB is not set
# end of PCI Endpoint

#
# PCI switch controller drivers
#
CONFIG_PCI_SW_SWITCHTEC=m
# end of PCI switch controller drivers

# CONFIG_CXL_BUS is not set
# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
CONFIG_AUXILIARY_BUS=y
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_DEVTMPFS_SAFE is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
CONFIG_FW_LOADER_COMPRESS=y
CONFIG_FW_LOADER_COMPRESS_XZ=y
CONFIG_FW_LOADER_COMPRESS_ZSTD=y
CONFIG_FW_CACHE=y
# CONFIG_FW_UPLOAD is not set
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
CONFIG_DEBUG_DEVRES=y
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SCCB=m
CONFIG_MALI_BASE_MODULES=y
CONFIG_DMA_SHARED_BUFFER_TEST_EXPORTER=y
CONFIG_MALI_MEMORY_GROUP_MANAGER=y
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
# CONFIG_BRCMSTB_GISB_ARB is not set
# CONFIG_MOXTET is not set
# CONFIG_VEXPRESS_CONFIG is not set
CONFIG_MHI_BUS=m
# CONFIG_MHI_BUS_DEBUG is not set
CONFIG_MHI_BUS_PCI_GENERIC=m
CONFIG_MHI_BUS_EP=m
# end of Bus devices

CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y

#
# Firmware Drivers
#

#
# ARM System Control and Management Interface Protocol
#
CONFIG_ARM_SCMI_PROTOCOL=y
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
CONFIG_ARM_SCMI_HAVE_SHMEM=y
CONFIG_ARM_SCMI_HAVE_MSG=y
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set
CONFIG_ARM_SCMI_POWER_DOMAIN=y
CONFIG_ARM_SCMI_POWER_CONTROL=y
# end of ARM System Control and Management Interface Protocol

CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
CONFIG_ARM_SDE_INTERFACE=y
CONFIG_FIRMWARE_MEMMAP=y
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=y
# CONFIG_ISCSI_IBFT is not set
CONFIG_FW_CFG_SYSFS=m
CONFIG_FW_CFG_SYSFS_CMDLINE=y
CONFIG_ROCKCHIP_SIP=y
# CONFIG_SYSFB_SIMPLEFB is not set
# CONFIG_ARM_FFA_TRANSPORT is not set
CONFIG_CS_DSP=m
# CONFIG_GOOGLE_FIRMWARE is not set

#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_VARS_PSTORE=y
# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_GENERIC_STUB=y
# CONFIG_EFI_ZBOOT is not set
CONFIG_EFI_ARMSTUB_DTB_LOADER=y
CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
# CONFIG_EFI_BOOTLOADER_CONTROL is not set
# CONFIG_EFI_CAPSULE_LOADER is not set
# CONFIG_EFI_TEST is not set
# CONFIG_RESET_ATTACK_MITIGATION is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
# CONFIG_EFI_DISABLE_RUNTIME is not set
# CONFIG_EFI_COCO_SECRET is not set
# end of EFI (Extensible Firmware Interface) Support

CONFIG_UEFI_CPER=y
CONFIG_UEFI_CPER_ARM=y
CONFIG_ARM_PSCI_FW=y
CONFIG_ARM_PSCI_CHECKER=y
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_ARM_SMCCC_SOC_ID=y

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_GNSS=m
CONFIG_GNSS_SERIAL=m
CONFIG_GNSS_MTK_SERIAL=m
CONFIG_GNSS_SIRF_SERIAL=m
CONFIG_GNSS_UBX_SERIAL=m
CONFIG_GNSS_USB=m
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_OF_PARTS=y
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y

#
# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
#
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_MCHP48L640 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
CONFIG_MTD_BLOCK2MTD=m

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
CONFIG_MTD_NAND_CORE=y
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NAND_DEVICE_AUTOSELECT=y
CONFIG_MTD_SPI_NAND_ATO=y
CONFIG_MTD_SPI_NAND_BIWIN=y
CONFIG_MTD_SPI_NAND_DOSILICON=y
CONFIG_MTD_SPI_NAND_ESMT=y
CONFIG_MTD_SPI_NAND_ETRON=y
CONFIG_MTD_SPI_NAND_FMSH=y
CONFIG_MTD_SPI_NAND_FORESEE=y
CONFIG_MTD_SPI_NAND_GIGADEVICE=y
CONFIG_MTD_SPI_NAND_GSTO=y
CONFIG_MTD_SPI_NAND_HIKSEMI=y
CONFIG_MTD_SPI_NAND_HYF=y
CONFIG_MTD_SPI_NAND_JSC=y
CONFIG_MTD_SPI_NAND_MACRONIX=y
CONFIG_MTD_SPI_NAND_MICRON=y
CONFIG_MTD_SPI_NAND_PARAGON=y
CONFIG_MTD_SPI_NAND_SILICONGO=y
CONFIG_MTD_SPI_NAND_SKYHIGH=y
CONFIG_MTD_SPI_NAND_TOSHIBA=y
CONFIG_MTD_SPI_NAND_UNIM=y
CONFIG_MTD_SPI_NAND_WINBOND=y
CONFIG_MTD_SPI_NAND_XINCUN=y
CONFIG_MTD_SPI_NAND_XTX=y
CONFIG_MTD_SPI_NAND_ZBIT=y

#
# ECC engine support
#
CONFIG_MTD_NAND_ECC=y
# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
# CONFIG_MTD_NAND_ECC_MXIC is not set
CONFIG_MTD_NAND_BBT_USING_FLASH=y
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
CONFIG_MTD_SPI_NOR_MISC=y
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
CONFIG_MTD_SPI_NOR_DEVICE_AUTOSELECT=y
CONFIG_MTD_SPI_NOR_ATMEL=y
CONFIG_MTD_SPI_NOR_BOYA=y
CONFIG_MTD_SPI_NOR_CATALYST=y
CONFIG_MTD_SPI_NOR_DOSILICON=y
CONFIG_MTD_SPI_NOR_EON=y
CONFIG_MTD_SPI_NOR_ESMT=y
CONFIG_MTD_SPI_NOR_EVERSPIN=y
CONFIG_MTD_SPI_NOR_FMSH=y
CONFIG_MTD_SPI_NOR_FUJITSU=y
CONFIG_MTD_SPI_NOR_GIGADEVICE=y
CONFIG_MTD_SPI_NOR_INTEL=y
CONFIG_MTD_SPI_NOR_ISSI=y
CONFIG_MTD_SPI_NOR_MACRONIX=y
CONFIG_MTD_SPI_NOR_NORMEM=y
CONFIG_MTD_SPI_NOR_PUYA=y
CONFIG_MTD_SPI_NOR_SPANSION=y
CONFIG_MTD_SPI_NOR_STMICRO=y
CONFIG_MTD_SPI_NOR_SST=y
CONFIG_MTD_SPI_NOR_WINBOND=y
CONFIG_MTD_SPI_NOR_XILINX=y
CONFIG_MTD_SPI_NOR_XMC=y
CONFIG_MTD_SPI_NOR_XTX=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
# CONFIG_MTD_UBI_BLOCK is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_DTC_SYMBOLS is not set
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_NULL_BLK is not set
CONFIG_CDROM=m
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
CONFIG_ZRAM=y
CONFIG_ZRAM_DEF_COMP_LZORLE=y
# CONFIG_ZRAM_DEF_COMP_ZSTD is not set
# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
# CONFIG_ZRAM_DEF_COMP_LZO is not set
# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
# CONFIG_ZRAM_DEF_COMP_842 is not set
CONFIG_ZRAM_DEF_COMP="lzo-rle"
# CONFIG_ZRAM_WRITEBACK is not set
# CONFIG_ZRAM_MEMORY_TRACKING is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
CONFIG_BLK_DEV_DRBD=m
# CONFIG_DRBD_FAULT_INJECTION is not set
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_VIRTIO_BLK=m
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_UBLK is not set

#
# NVME Support
#
CONFIG_NVME_COMMON=y
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
CONFIG_NVME_MULTIPATH=y
CONFIG_NVME_VERBOSE_ERRORS=y
CONFIG_NVME_HWMON=y
CONFIG_NVME_FABRICS=m
CONFIG_NVME_FC=m
CONFIG_NVME_TCP=m
CONFIG_NVME_AUTH=y
CONFIG_NVME_TARGET=m
CONFIG_NVME_TARGET_PASSTHRU=y
CONFIG_NVME_TARGET_LOOP=m
CONFIG_NVME_TARGET_FC=m
CONFIG_NVME_TARGET_FCLOOP=m
CONFIG_NVME_TARGET_TCP=m
CONFIG_NVME_TARGET_AUTH=y
# end of NVME Support

#
# Misc devices
#

#
# RK628 misc driver
#
CONFIG_RK628_MISC=y
CONFIG_RK628_MISC_HDMITX=y
CONFIG_RK628_MISC_GPIO_TEST=y
# CONFIG_ROCKCHIP_THUNDER_BOOT_RK628 is not set
# end of RK628 misc driver

CONFIG_RK803=m
# CONFIG_CONFIG_ROCKPI_MCU is not set
# CONFIG_PCIE_FUNC_RKEP is not set

#
# misc vehicle setting
#
# CONFIG_VEHICLE_CORE is not set
# CONFIG_VEHICLE_GPIO_MCU_EXPANDER is not set
# CONFIG_VEHICLE_DRIVER_OREO is not set
# end of misc vehicle setting

# CONFIG_LT7911D_FB_NOTIFIER is not set
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
CONFIG_TIFM_CORE=m
CONFIG_TIFM_7XX1=m
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
# CONFIG_DW_XDATA_PCIE is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_XILINX_SDFEC is not set
CONFIG_MISC_RTSX=m
# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_OPEN_DICE is not set
# CONFIG_VCPU_STALL_DETECTOR is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
CONFIG_EEPROM_AT24=m
CONFIG_EEPROM_AT25=m
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
CONFIG_EEPROM_93CX6=m
CONFIG_EEPROM_93XX46=m
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

# CONFIG_CB710_CORE is not set

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline

# CONFIG_SENSORS_LIS3_I2C is not set
CONFIG_ALTERA_STAPL=m
# CONFIG_VMWARE_VMCI is not set
# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_BCM_VK is not set
# CONFIG_MISC_ALCOR_PCI is not set
CONFIG_MISC_RTSX_PCI=m
CONFIG_MISC_RTSX_USB=m
# CONFIG_HABANA_AI is not set
# CONFIG_UACCE is not set
# CONFIG_PVPANIC is not set
# CONFIG_GP_PCI1XXXX is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
CONFIG_RAID_ATTRS=m
CONFIG_SCSI_COMMON=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=m
# CONFIG_CHR_DEV_ST is not set
CONFIG_BLK_DEV_SR=m
# CONFIG_CHR_DEV_SG is not set
CONFIG_BLK_DEV_BSG=y
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
CONFIG_SCSI_SCAN_ASYNC=y

#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=m
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=m
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_ISCSI_BOOT_SYSFS=m
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_MPI3MR is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_FDOMAIN_PCI is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
CONFIG_SCSI_VIRTIO=m
# CONFIG_SCSI_DH is not set
# end of SCSI device support

CONFIG_ATA=y
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_ARCH_WANT_LIBATA_LEDS=y
CONFIG_ATA_LEDS=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_AHCI_DWC=y
CONFIG_AHCI_CEVA=m
CONFIG_AHCI_QORIQ=m
CONFIG_SATA_INIC162X=m
CONFIG_SATA_ACARD_AHCI=m
CONFIG_SATA_SIL24=m
# CONFIG_ATA_SFF is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
# CONFIG_MD_CLUSTER is not set
CONFIG_BCACHE=m
# CONFIG_BCACHE_DEBUG is not set
# CONFIG_BCACHE_CLOSURES_DEBUG is not set
# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=m
# CONFIG_DM_DEBUG is not set
CONFIG_DM_BUFIO=m
# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
# CONFIG_DM_UNSTRIPED is not set
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
CONFIG_DM_CACHE=m
CONFIG_DM_CACHE_SMQ=m
CONFIG_DM_WRITECACHE=m
# CONFIG_DM_EBS is not set
CONFIG_DM_ERA=m
# CONFIG_DM_CLONE is not set
CONFIG_DM_MIRROR=m
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
# CONFIG_DM_MULTIPATH_HST is not set
# CONFIG_DM_MULTIPATH_IOA is not set
CONFIG_DM_DELAY=m
# CONFIG_DM_DUST is not set
# CONFIG_DM_UEVENT is not set
CONFIG_DM_FLAKEY=m
CONFIG_DM_VERITY=m
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
# CONFIG_DM_VERITY_FEC is not set
CONFIG_DM_SWITCH=m
CONFIG_DM_LOG_WRITES=m
# CONFIG_DM_INTEGRITY is not set
# CONFIG_DM_ZONED is not set
# CONFIG_DM_AUDIT is not set
# CONFIG_TARGET_CORE is not set
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
# end of IEEE 1394 (FireWire) support

CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_WIREGUARD=m
# CONFIG_WIREGUARD_DEBUG is not set
CONFIG_EQUALIZER=m
# CONFIG_NET_FC is not set
CONFIG_IFB=m
CONFIG_NET_TEAM=m
CONFIG_NET_TEAM_MODE_BROADCAST=m
CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
CONFIG_NET_TEAM_MODE_RANDOM=m
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
CONFIG_NET_TEAM_MODE_LOADBALANCE=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=m
CONFIG_IPVTAP=m
CONFIG_VXLAN=m
CONFIG_GENEVE=m
CONFIG_BAREUDP=m
CONFIG_GTP=m
CONFIG_AMT=m
CONFIG_MACSEC=m
CONFIG_NETCONSOLE=m
# CONFIG_NETCONSOLE_DYNAMIC is not set
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=m
CONFIG_TAP=m
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_NLMON=m
CONFIG_NET_VRF=m
CONFIG_VSOCKMON=m
CONFIG_MHI_NET=m
# CONFIG_ARCNET is not set

#
# Distributed Switch Architecture drivers
#
CONFIG_B53=m
# CONFIG_B53_SPI_DRIVER is not set
# CONFIG_B53_MDIO_DRIVER is not set
# CONFIG_B53_MMAP_DRIVER is not set
# CONFIG_B53_SRAB_DRIVER is not set
# CONFIG_B53_SERDES is not set
CONFIG_NET_DSA_BCM_SF2=m
CONFIG_NET_DSA_LOOP=m
CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
CONFIG_NET_DSA_LANTIQ_GSWIP=m
CONFIG_NET_DSA_MT7530=m
CONFIG_NET_DSA_MT7530_MDIO=m
CONFIG_NET_DSA_MT7530_MMIO=m
CONFIG_NET_DSA_MV88E6060=m
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
# CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C is not set
# CONFIG_NET_DSA_MICROCHIP_KSZ_SPI is not set
# CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI is not set
CONFIG_NET_DSA_MV88E6XXX=m
CONFIG_NET_DSA_MV88E6XXX_PTP=y
CONFIG_NET_DSA_AR9331=m
CONFIG_NET_DSA_QCA8K=m
# CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT is not set
CONFIG_NET_DSA_SJA1105=m
CONFIG_NET_DSA_SJA1105_PTP=y
CONFIG_NET_DSA_SJA1105_TAS=y
CONFIG_NET_DSA_SJA1105_VL=y
CONFIG_NET_DSA_XRS700X=m
CONFIG_NET_DSA_XRS700X_I2C=m
CONFIG_NET_DSA_XRS700X_MDIO=m
CONFIG_NET_DSA_REALTEK=m
CONFIG_NET_DSA_REALTEK_MDIO=m
CONFIG_NET_DSA_REALTEK_SMI=m
CONFIG_NET_DSA_REALTEK_RTL8365MB=m
CONFIG_NET_DSA_REALTEK_RTL8366RB=m
CONFIG_NET_DSA_SMSC_LAN9303=m
CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
CONFIG_NET_DSA_VITESSE_VSC73XX=m
CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
# end of Distributed Switch Architecture drivers

CONFIG_ETHERNET=y
CONFIG_MDIO=m
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_ALTERA_TSE is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
CONFIG_NET_VENDOR_ASIX=y
# CONFIG_SPI_AX88796C is not set
# CONFIG_NET_VENDOR_ATHEROS is not set
CONFIG_NET_VENDOR_MOTORCOMM=y
# CONFIG_FUXI is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_CORTINA is not set
CONFIG_NET_VENDOR_DAVICOM=y
# CONFIG_DM9051 is not set
# CONFIG_DNET is not set
# CONFIG_NET_VENDOR_DEC is not set
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
CONFIG_NET_VENDOR_ENGLEDER=y
# CONFIG_TSNEP is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
CONFIG_NET_VENDOR_FUNGIBLE=y
# CONFIG_FUN_ETH is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_I825XX is not set
CONFIG_NET_VENDOR_INTEL=y
# CONFIG_E100 is not set
CONFIG_E1000=m
CONFIG_E1000E=m
CONFIG_IGB=m
# CONFIG_IGB_HWMON is not set
CONFIG_IGBVF=m
CONFIG_IXGB=m
CONFIG_IXGBE=m
CONFIG_IXGBE_HWMON=y
CONFIG_IXGBE_IPSEC=y
CONFIG_IXGBEVF=m
CONFIG_IXGBEVF_IPSEC=y
CONFIG_I40E=m
# CONFIG_I40EVF is not set
# CONFIG_ICE is not set
# CONFIG_FM10K is not set
CONFIG_IGC=m
# CONFIG_JME is not set
CONFIG_NET_VENDOR_ADI=y
# CONFIG_ADIN1110 is not set
CONFIG_NET_VENDOR_LITEX=y
# CONFIG_LITEX_LITEETH is not set
# CONFIG_NET_VENDOR_MARVELL is not set
CONFIG_NET_VENDOR_MELLANOX=y
CONFIG_MLX4_EN=m
CONFIG_MLX4_CORE=m
CONFIG_MLX4_DEBUG=y
CONFIG_MLX4_CORE_GEN2=y
CONFIG_MLX5_CORE=m
CONFIG_MLX5_FPGA=y
CONFIG_MLX5_CORE_EN=y
CONFIG_MLX5_EN_ARFS=y
CONFIG_MLX5_EN_RXNFC=y
CONFIG_MLX5_MPFS=y
CONFIG_MLX5_ESWITCH=y
CONFIG_MLX5_BRIDGE=y
CONFIG_MLX5_CLS_ACT=y
CONFIG_MLX5_TC_SAMPLE=y
CONFIG_MLX5_CORE_IPOIB=y
# CONFIG_MLX5_EN_MACSEC is not set
CONFIG_MLX5_EN_IPSEC=y
# CONFIG_MLX5_EN_TLS is not set
CONFIG_MLX5_SW_STEERING=y
# CONFIG_MLX5_SF is not set
CONFIG_MLXSW_CORE=m
CONFIG_MLXSW_CORE_HWMON=y
CONFIG_MLXSW_CORE_THERMAL=y
CONFIG_MLXSW_PCI=m
CONFIG_MLXSW_I2C=m
CONFIG_MLXSW_SPECTRUM=m
CONFIG_MLXSW_MINIMAL=m
CONFIG_MLXFW=m
# CONFIG_MLXBF_GIGE is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
CONFIG_NET_VENDOR_MICROSOFT=y
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_FEALNX is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETERION is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_BROCADE is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCA7000_UART is not set
# CONFIG_QCOM_EMAC is not set
CONFIG_SFE_SUPPORT_IPV6=y
CONFIG_SFE_ECM=y
CONFIG_FAST_CLASSIFIER=y
# CONFIG_RMNET is not set
# CONFIG_NET_VENDOR_RDC is not set
CONFIG_NET_VENDOR_REALTEK=y
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
CONFIG_R8125=m
CONFIG_R8125_SOC_LAN=y
# CONFIG_R8125_REALWOW_SUPPORT is not set
# CONFIG_R8125_DASH_SUPPORT is not set
# CONFIG_R8125_DOWN_SPEED_100 is not set
# CONFIG_R8125_ASPM is not set
CONFIG_R8125_WOL_SUPPORT=y
CONFIG_R8125_S5WOL=y
# CONFIG_R8125_S5_KEEP_CURR_MAC is not set
# CONFIG_R8125_EEE is not set
# CONFIG_R8125_S0_MAGIC_PACKET is not set
CONFIG_R8125_TX_NO_CLOSE=y
CONFIG_R8125_MULTI_MSIX_VECTOR=y
CONFIG_R8125_MULTIPLE_TX_QUEUE=y
CONFIG_R8125_RSS_SUPPORT=y
# CONFIG_R8125_PTP_SUPPORT is not set
CONFIG_R8125_FIBER_SUPPORT=y
CONFIG_R8125_USE_FIRMWARE_FILE=y
# CONFIG_R8125_DOUBLE_VLAN is not set
# CONFIG_R8125_PAGE_REUSE is not set
CONFIG_R8125_GIGA_LITE=y
CONFIG_R8126=m
CONFIG_R8126_SOC_LAN=y
# CONFIG_R8126_REALWOW_SUPPORT is not set
# CONFIG_R8126_DASH_SUPPORT is not set
# CONFIG_R8126_DOWN_SPEED_100 is not set
# CONFIG_R8126_ASPM is not set
CONFIG_R8126_WOL_SUPPORT=y
CONFIG_R8126_S5WOL=y
# CONFIG_R8126_S5_KEEP_CURR_MAC is not set
# CONFIG_R8126_EEE is not set
# CONFIG_R8126_S0_MAGIC_PACKET is not set
CONFIG_R8126_TX_NO_CLOSE=y
CONFIG_R8126_MULTI_MSIX_VECTOR=y
CONFIG_R8126_MULTIPLE_TX_QUEUE=y
CONFIG_R8126_RSS_SUPPORT=y
CONFIG_R8126_PTP_SUPPORT=y
CONFIG_R8126_FIBER_SUPPORT=y
CONFIG_R8126_USE_FIRMWARE_FILE=y
# CONFIG_R8126_DOUBLE_VLAN is not set
# CONFIG_R8126_PAGE_REUSE is not set
CONFIG_R8126_GIGA_LITE=y
CONFIG_R8168=m
CONFIG_R8168_SOC_LAN=y
# CONFIG_R8168_FIBER_SUPPORT is not set
# CONFIG_R8168_REALWOW_SUPPORT is not set
# CONFIG_R8168_DASH_SUPPORT is not set
# CONFIG_R8168_DOWN_SPEED_100 is not set
# CONFIG_R8168_ASPM is not set
CONFIG_R8168_WOL_SUPPORT=y
CONFIG_R8168_S5WOL=y
# CONFIG_R8168_S5_KEEP_CURR_MAC is not set
# CONFIG_R8168_EEE is not set
# CONFIG_R8168_S0_MAGIC_PACKET is not set
CONFIG_R8168_USE_FIRMWARE_FILE=y
# CONFIG_R8168_CTAP_SHORT_OFF is not set
# CONFIG_R8168_MULTIPLE_TX_QUEUE is not set
# CONFIG_R8168_RSS_SUPPORT is not set
CONFIG_R8168_GIGA_LITE=y
# CONFIG_R8169 is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
# CONFIG_STMMAC_SELFTESTS is not set
# CONFIG_STMMAC_UIO is not set
CONFIG_STMMAC_ETHTOOL=y
CONFIG_STMMAC_FULL=y
CONFIG_STMMAC_PLATFORM=y
# CONFIG_DWMAC_DWC_QOS_ETH is not set
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_ROCKCHIP=y
CONFIG_DWMAC_ROCKCHIP_TOOL=y
# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
CONFIG_NET_VENDOR_VERTEXCOM=y
# CONFIG_MSE102X is not set
# CONFIG_NET_VENDOR_VIA is not set
CONFIG_NET_VENDOR_WANGXUN=y
# CONFIG_NGBE is not set
# CONFIG_TXGBE is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_NET_SB1000 is not set
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_PHYLIB_LEDS=y
CONFIG_FIXED_PHY=y
# CONFIG_SFP is not set

#
# Switch configuration API + drivers
#
CONFIG_SWCONFIG=m
CONFIG_SWCONFIG_LEDS=y
CONFIG_RTL8306_PHY=m
CONFIG_RTL8366_SMI=m
CONFIG_RTL8366_SMI_DEBUG_FS=y
CONFIG_RTL8366S_PHY=m
CONFIG_RTL8366RB_PHY=m
CONFIG_RTL8367_PHY=m
CONFIG_RTL8367B_PHY=m

#
# MII PHY device drivers
#
# CONFIG_AIR_EN8811H_PHY is not set
# CONFIG_AMD_PHY is not set
# CONFIG_ADIN_PHY is not set
# CONFIG_ADIN1100_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
CONFIG_AX88796B_PHY=m
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM54140_PHY is not set
CONFIG_BCM7XXX_PHY=m
# CONFIG_BCM84881_PHY is not set
# CONFIG_BCM87XX_PHY is not set
CONFIG_BCM_NET_PHYLIB=m
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
CONFIG_ICPLUS_PHY=y
# CONFIG_LXT_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MARVELL_88X2222_PHY is not set
# CONFIG_MAXLINEAR_GPHY is not set
CONFIG_MEDIATEK_GE_PHY=m
# CONFIG_MICREL_PHY is not set
CONFIG_MICROCHIP_PHY=m
# CONFIG_MICROCHIP_T1_PHY is not set
CONFIG_MICROSEMI_PHY=m
CONFIG_MOTORCOMM_PHY=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_NXP_C45_TJA11XX_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
# CONFIG_AT803X_PHY is not set
# CONFIG_QCA83XX_PHY is not set
# CONFIG_QCA808X_PHY is not set
# CONFIG_QCA807X_PHY is not set
# CONFIG_QSEMI_PHY is not set
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_FEPHY=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_RK630_PHY=y
CONFIG_SMSC_PHY=m
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
# CONFIG_DP83869_PHY is not set
# CONFIG_DP83TD510_PHY is not set
CONFIG_VITESSE_PHY=m
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_PSE_CONTROLLER is not set
CONFIG_CAN_DEV=m
CONFIG_CAN_VCAN=m
CONFIG_CAN_VXCAN=m
CONFIG_CAN_NETLINK=y
CONFIG_CAN_CALC_BITTIMING=y
CONFIG_CAN_RX_OFFLOAD=y
CONFIG_CAN_CAN327=m
# CONFIG_CAN_FLEXCAN is not set
# CONFIG_CAN_GRCAN is not set
# CONFIG_CAN_KVASER_PCIEFD is not set
CONFIG_CAN_SLCAN=m
# CONFIG_CAN_XILINXCAN is not set
# CONFIG_CAN_C_CAN is not set
# CONFIG_CAN_CC770 is not set
# CONFIG_CAN_CTUCANFD_PCI is not set
# CONFIG_CAN_CTUCANFD_PLATFORM is not set
# CONFIG_CAN_IFI_CANFD is not set
# CONFIG_CAN_M_CAN is not set
# CONFIG_CAN_PEAK_PCIEFD is not set
CONFIG_CAN_ROCKCHIP=m
CONFIG_CANFD_ROCKCHIP=m
CONFIG_CAN_RK3562=m
CONFIG_CANFD_RK3576=m
# CONFIG_CAN_SJA1000 is not set
# CONFIG_CAN_SOFTING is not set

#
# CAN SPI interfaces
#
CONFIG_CAN_HI311X=m
CONFIG_CAN_MCP251X=m
CONFIG_CAN_MCP251XFD=m
CONFIG_CAN_MCP251XFD_SANITY=y
# end of CAN SPI interfaces

#
# CAN USB interfaces
#
CONFIG_CAN_8DEV_USB=m
CONFIG_CAN_EMS_USB=m
CONFIG_CAN_ESD_USB=m
CONFIG_CAN_ETAS_ES58X=m
CONFIG_CAN_GS_USB=m
CONFIG_CAN_KVASER_USB=m
CONFIG_CAN_MCBA_USB=m
CONFIG_CAN_PEAK_USB=m
CONFIG_CAN_UCAN=m
# end of CAN USB interfaces

CONFIG_CAN_DEBUG_DEVICES=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_FWNODE_MDIO=y
CONFIG_OF_MDIO=y
CONFIG_ACPI_MDIO=y
CONFIG_MDIO_DEVRES=y
# CONFIG_MDIO_BITBANG is not set
CONFIG_MDIO_BCM_UNIMAC=m
# CONFIG_MDIO_HISI_FEMAC is not set
# CONFIG_MDIO_MVUSB is not set
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_OCTEON is not set
# CONFIG_MDIO_IPQ4019 is not set
# CONFIG_MDIO_IPQ8064 is not set
# CONFIG_MDIO_THUNDER is not set

#
# MDIO Multiplexers
#
# CONFIG_MDIO_BUS_MUX_GPIO is not set
# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
# CONFIG_MDIO_BUS_MUX_MMIOREG is not set

#
# PCS device drivers
#
CONFIG_PCS_XPCS=y
# CONFIG_PCS_MTK_USXGMII is not set
CONFIG_PCS_MTK_LYNXI=m
# end of PCS device drivers

CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
# CONFIG_PPP_FILTER is not set
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=m
CONFIG_PPTP=m
CONFIG_PPPOL2TP=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
# CONFIG_SLIP is not set
CONFIG_SLHC=m
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_AX8817X=m
CONFIG_USB_NET_AX88179_178A=m
CONFIG_USB_NET_CDCETHER=m
CONFIG_USB_NET_CDC_EEM=m
CONFIG_USB_NET_CDC_NCM=m
CONFIG_USB_NET_HUAWEI_CDC_NCM=m
CONFIG_USB_NET_CDC_MBIM=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9700=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
CONFIG_USB_NET_CDC_SUBSET=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
# CONFIG_USB_ARMLINUX is not set
# CONFIG_USB_EPSON2888 is not set
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=m
CONFIG_USB_NET_CX82310_ETH=m
CONFIG_USB_NET_KALMIA=m
CONFIG_USB_NET_QMI_WWAN=m
CONFIG_USB_HSO=m
CONFIG_USB_NET_INT51X1=m
CONFIG_USB_IPHETH=m
CONFIG_USB_SIERRA_NET=m
CONFIG_USB_VL600=m
CONFIG_USB_NET_CH9200=m
CONFIG_USB_NET_AQC111=m
CONFIG_USB_RTL8153_ECM=m
CONFIG_WLAN=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
CONFIG_WLAN_VENDOR_AIC=y
CONFIG_AIC8800_SUPPORT=y
CONFIG_AIC8800_SDIO_WLAN=y
CONFIG_AIC8800_SDIO_FW_PATH="/lib/firmware/aic8800_sdio"
CONFIG_AIC8800_USB_WLAN=y
CONFIG_AIC8800_USB_FW_PATH="/lib/firmware/aic8800_usb"
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
CONFIG_ATH_USER_REGD=y
# CONFIG_ATH_DEBUG is not set
CONFIG_ATH5K=m
# CONFIG_ATH5K_DEBUG is not set
# CONFIG_ATH5K_TRACER is not set
CONFIG_ATH5K_PCI=y
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=m
CONFIG_ATH9K_PCI=y
# CONFIG_ATH9K_AHB is not set
# CONFIG_ATH9K_DEBUGFS is not set
# CONFIG_ATH9K_DYNACK is not set
# CONFIG_ATH9K_WOW is not set
CONFIG_ATH9K_RFKILL=y
# CONFIG_ATH9K_CHANNEL_CONTEXT is not set
CONFIG_ATH9K_PCOEM=y
CONFIG_ATH9K_PCI_NO_EEPROM=y
# CONFIG_ATH9K_HTC is not set
CONFIG_ATH9K_HWRNG=y
CONFIG_CARL9170=m
CONFIG_CARL9170_LEDS=y
CONFIG_CARL9170_WPC=y
CONFIG_CARL9170_HWRNG=y
CONFIG_ATH6KL=m
# CONFIG_ATH6KL_SDIO is not set
CONFIG_ATH6KL_USB=m
# CONFIG_ATH6KL_DEBUG is not set
# CONFIG_ATH6KL_TRACING is not set
CONFIG_AR5523=m
# CONFIG_WIL6210 is not set
CONFIG_ATH10K=m
CONFIG_ATH10K_CE=y
CONFIG_ATH10K_PCI=m
# CONFIG_ATH10K_AHB is not set
# CONFIG_ATH10K_SDIO is not set
CONFIG_ATH10K_USB=m
# CONFIG_ATH10K_DEBUG is not set
# CONFIG_ATH10K_DEBUGFS is not set
CONFIG_ATH10K_LEDS=y
# CONFIG_ATH10K_TRACING is not set
CONFIG_ATH10K_THERMAL=y
CONFIG_WCN36XX=m
# CONFIG_WCN36XX_DEBUGFS is not set
CONFIG_ATH11K=m
CONFIG_ATH11K_PCI=m
# CONFIG_ATH11K_DEBUG is not set
# CONFIG_ATH11K_TRACING is not set
CONFIG_ATH11K_THERMAL=y
# CONFIG_WLAN_VENDOR_ATMEL is not set
CONFIG_WLAN_VENDOR_BROADCOM=y
# CONFIG_B43 is not set
# CONFIG_B43LEGACY is not set
CONFIG_BRCMUTIL=m
# CONFIG_BRCMSMAC is not set
CONFIG_BRCMFMAC=m
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_PROTO_MSGBUF=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
CONFIG_BRCMFMAC_PCIE=y
CONFIG_BRCM_TRACING=y
# CONFIG_BRCMDBG is not set
# CONFIG_WLAN_VENDOR_CISCO is not set
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_IPW2100=m
# CONFIG_IPW2100_MONITOR is not set
# CONFIG_IPW2100_DEBUG is not set
CONFIG_IPW2200=m
# CONFIG_IPW2200_MONITOR is not set
# CONFIG_IPW2200_QOS is not set
# CONFIG_IPW2200_DEBUG is not set
CONFIG_LIBIPW=m
# CONFIG_LIBIPW_DEBUG is not set
CONFIG_IWLEGACY=m
CONFIG_IWL4965=m
CONFIG_IWL3945=m

#
# iwl3945 / iwl4965 Debugging Options
#
# CONFIG_IWLEGACY_DEBUG is not set
# end of iwl3945 / iwl4965 Debugging Options

CONFIG_IWLWIFI=m
CONFIG_IWLWIFI_LEDS=y
CONFIG_IWLDVM=m
CONFIG_IWLMVM=m
CONFIG_IWLWIFI_OPMODE_MODULAR=y

#
# Debugging Options
#
# CONFIG_IWLWIFI_DEBUG is not set
# CONFIG_IWLWIFI_DEVICE_TRACING is not set
# end of Debugging Options

# CONFIG_WLAN_VENDOR_INTERSIL is not set
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_USB=m
CONFIG_LIBERTAS_SDIO=m
CONFIG_LIBERTAS_SPI=m
# CONFIG_LIBERTAS_DEBUG is not set
# CONFIG_LIBERTAS_MESH is not set
CONFIG_LIBERTAS_THINFIRM=m
# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
CONFIG_LIBERTAS_THINFIRM_USB=m
# CONFIG_MWIFIEX is not set
CONFIG_MWL8K=m
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=m
CONFIG_MT76_CORE=m
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=m
CONFIG_MT76_SDIO=m
CONFIG_MT76x02_LIB=m
CONFIG_MT76x02_USB=m
CONFIG_MT76_CONNAC_LIB=m
CONFIG_MT792x_LIB=m
CONFIG_MT792x_USB=m
CONFIG_MT76x0_COMMON=m
CONFIG_MT76x0U=m
CONFIG_MT76x0E=m
CONFIG_MT76x2_COMMON=m
CONFIG_MT76x2E=m
CONFIG_MT76x2U=m
CONFIG_MT7603E=m
CONFIG_MT7615_COMMON=m
CONFIG_MT7615E=m
CONFIG_MT7663_USB_SDIO_COMMON=m
CONFIG_MT7663U=m
CONFIG_MT7663S=m
CONFIG_MT7915E=m
CONFIG_MT7921_COMMON=m
CONFIG_MT7921E=m
CONFIG_MT7921S=m
CONFIG_MT7921U=m
CONFIG_MT7996E=m
CONFIG_WLAN_VENDOR_MICROCHIP=y
CONFIG_WILC1000=m
CONFIG_WILC1000_SDIO=m
CONFIG_WILC1000_SPI=m
CONFIG_WILC1000_HW_OOB_INTR=y
CONFIG_WLAN_VENDOR_PURELIFI=y
# CONFIG_PLFXLC is not set
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=m
CONFIG_RT2400PCI=m
CONFIG_RT2500PCI=m
CONFIG_RT61PCI=m
CONFIG_RT2800PCI=m
CONFIG_RT2800PCI_RT33XX=y
CONFIG_RT2800PCI_RT35XX=y
CONFIG_RT2800PCI_RT53XX=y
CONFIG_RT2800PCI_RT3290=y
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
CONFIG_RT2800USB_RT33XX=y
CONFIG_RT2800USB_RT35XX=y
CONFIG_RT2800USB_RT3573=y
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
# CONFIG_RT2800USB_UNKNOWN is not set
CONFIG_RT2800_LIB=m
CONFIG_RT2800_LIB_MMIO=m
CONFIG_RT2X00_LIB_MMIO=m
CONFIG_RT2X00_LIB_PCI=m
CONFIG_RT2X00_LIB_USB=m
CONFIG_RT2X00_LIB=m
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
# CONFIG_RT2X00_DEBUG is not set
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_RTL8180=m
CONFIG_RTL8187=m
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=m
CONFIG_RTL8192CE=m
CONFIG_RTL8192SE=m
CONFIG_RTL8192DE=m
CONFIG_RTL8723AE=m
CONFIG_RTL8723BE=m
CONFIG_RTL8188EE=m
CONFIG_RTL8192EE=m
CONFIG_RTL8821AE=m
CONFIG_RTL8192CU=m
CONFIG_RTLWIFI=m
CONFIG_RTLWIFI_PCI=m
CONFIG_RTLWIFI_USB=m
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8723_COMMON=m
CONFIG_RTLBTCOEXIST=m
CONFIG_RTL8XXXU=m
# CONFIG_RTL8XXXU_UNTESTED is not set
CONFIG_RTW88=m
CONFIG_RTW88_CORE=m
CONFIG_RTW88_PCI=m
CONFIG_RTW88_SDIO=m
CONFIG_RTW88_USB=m
CONFIG_RTW88_8822B=m
CONFIG_RTW88_8822C=m
CONFIG_RTW88_8723X=m
CONFIG_RTW88_8703B=m
CONFIG_RTW88_8723D=m
CONFIG_RTW88_8821C=m
CONFIG_RTW88_8822BE=m
CONFIG_RTW88_8822BS=m
CONFIG_RTW88_8822BU=m
CONFIG_RTW88_8822CE=m
CONFIG_RTW88_8822CS=m
CONFIG_RTW88_8822CU=m
CONFIG_RTW88_8723DE=m
CONFIG_RTW88_8723DS=m
CONFIG_RTW88_8723CS=m
CONFIG_RTW88_8723DU=m
CONFIG_RTW88_8821CE=m
CONFIG_RTW88_8821CS=m
CONFIG_RTW88_8821CU=m
# CONFIG_RTW88_DEBUG is not set
# CONFIG_RTW88_DEBUGFS is not set
CONFIG_RTW89=m
CONFIG_RTW89_CORE=m
CONFIG_RTW89_PCI=m
CONFIG_RTW89_8851B=m
CONFIG_RTW89_8852A=m
CONFIG_RTW89_8852B=m
CONFIG_RTW89_8852C=m
CONFIG_RTW89_8851BE=m
CONFIG_RTW89_8852AE=m
CONFIG_RTW89_8852BE=m
CONFIG_RTW89_8852CE=m
# CONFIG_RTW89_DEBUGMSG is not set
# CONFIG_RTW89_DEBUGFS is not set
CONFIG_WL_ROCKCHIP=m
CONFIG_WIFI_BUILD_MODULE=y
# CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP is not set
# CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR is not set
CONFIG_BCMDHD=y
CONFIG_AP6XXX=m
# CONFIG_BCMDHD_SDIO is not set
CONFIG_BCMDHD_PCIE=y
CONFIG_BCMDHD_FW_PATH="/vendor/etc/firmware/fw_bcmdhd.bin"
CONFIG_BCMDHD_NVRAM_PATH="/vendor/etc/firmware/nvram.txt"
# CONFIG_BCMDHD_STATIC_IF is not set
# CONFIG_WLAN_VENDOR_RSI is not set
CONFIG_WLAN_VENDOR_SILABS=y
# CONFIG_WFX is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
# CONFIG_WLAN_VENDOR_ZYDAS is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
# CONFIG_MAC80211_HWSIM is not set
CONFIG_USB_NET_RNDIS_WLAN=m
CONFIG_VIRT_WIFI=m
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
CONFIG_IEEE802154_AT86RF230=m
CONFIG_IEEE802154_MRF24J40=m
CONFIG_IEEE802154_CC2520=m
CONFIG_IEEE802154_ATUSB=m
CONFIG_IEEE802154_ADF7242=m
CONFIG_IEEE802154_CA8210=m
# CONFIG_IEEE802154_CA8210_DEBUGFS is not set
CONFIG_IEEE802154_MCR20A=m
CONFIG_IEEE802154_HWSIM=m

#
# Wireless WAN
#
CONFIG_WWAN=m
CONFIG_WWAN_DEBUGFS=y
CONFIG_WWAN_HWSIM=m
CONFIG_MHI_WWAN_CTRL=m
CONFIG_MHI_WWAN_MBIM=m
CONFIG_RPMSG_WWAN_CTRL=m
CONFIG_IOSM=m
CONFIG_MTK_T7XX=m
# end of Wireless WAN

# CONFIG_VMXNET3 is not set
# CONFIG_FUJITSU_ES is not set
CONFIG_LTE=y
CONFIG_LTE_RM310=y
CONFIG_LTE_EM05=y
CONFIG_NETDEVSIM=m
CONFIG_NET_FAILOVER=m
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_SPARSEKMAP is not set
CONFIG_INPUT_MATRIXKMAP=m
CONFIG_INPUT_VIVALDIFMAP=m

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=m
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=m
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ADC=y
CONFIG_KEYBOARD_ADP5588=m
CONFIG_KEYBOARD_ADP5589=m
CONFIG_KEYBOARD_ATKBD=m
CONFIG_KEYBOARD_QT1050=m
CONFIG_KEYBOARD_QT1070=m
CONFIG_KEYBOARD_QT2160=m
CONFIG_KEYBOARD_DLINK_DIR685=m
CONFIG_KEYBOARD_LKKBD=m
CONFIG_KEYBOARD_GPIO_DISABLED=y
CONFIG_KEYBOARD_GPIO_BUTTON_HOTPLUG=m
CONFIG_KEYBOARD_TCA6416=m
CONFIG_KEYBOARD_TCA8418=m
CONFIG_KEYBOARD_MATRIX=m
CONFIG_KEYBOARD_LM8323=m
CONFIG_KEYBOARD_LM8333=m
CONFIG_KEYBOARD_MAX7359=m
CONFIG_KEYBOARD_MCS=m
CONFIG_KEYBOARD_MPR121=m
CONFIG_KEYBOARD_NEWTON=m
CONFIG_KEYBOARD_OPENCORES=m
CONFIG_KEYBOARD_PINEPHONE=m
CONFIG_KEYBOARD_SAMSUNG=m
CONFIG_KEYBOARD_STOWAWAY=m
CONFIG_KEYBOARD_SUNKBD=m
CONFIG_KEYBOARD_OMAP4=m
CONFIG_KEYBOARD_TM2_TOUCHKEY=m
CONFIG_KEYBOARD_XTKBD=m
CONFIG_KEYBOARD_CAP11XX=m
CONFIG_KEYBOARD_BCM=m
CONFIG_KEYBOARD_CYPRESS_SF=m
CONFIG_INPUT_MOUSE=y
# CONFIG_MOUSE_PS2 is not set
CONFIG_MOUSE_SERIAL=m
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=m
CONFIG_MOUSE_ELAN_I2C=m
CONFIG_MOUSE_ELAN_I2C_I2C=y
CONFIG_MOUSE_ELAN_I2C_SMBUS=y
# CONFIG_MOUSE_VSXXXAA is not set
CONFIG_MOUSE_GPIO=m
CONFIG_MOUSE_SYNAPTICS_I2C=m
CONFIG_MOUSE_SYNAPTICS_USB=m
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_ANALOG=m
CONFIG_JOYSTICK_A3D=m
CONFIG_JOYSTICK_ADC=m
CONFIG_JOYSTICK_ADI=m
CONFIG_JOYSTICK_COBRA=m
CONFIG_JOYSTICK_GF2K=m
CONFIG_JOYSTICK_GRIP=m
CONFIG_JOYSTICK_GRIP_MP=m
CONFIG_JOYSTICK_GUILLEMOT=m
CONFIG_JOYSTICK_INTERACT=m
CONFIG_JOYSTICK_SIDEWINDER=m
CONFIG_JOYSTICK_TMDC=m
CONFIG_JOYSTICK_IFORCE=m
CONFIG_JOYSTICK_IFORCE_USB=m
CONFIG_JOYSTICK_IFORCE_232=m
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
CONFIG_JOYSTICK_STINGER=m
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
CONFIG_JOYSTICK_AS5011=m
CONFIG_JOYSTICK_JOYDUMP=m
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_JOYSTICK_PSXPAD_SPI=m
CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
CONFIG_JOYSTICK_PXRC=m
CONFIG_JOYSTICK_QWIIC=m
CONFIG_JOYSTICK_FSIA6B=m
CONFIG_JOYSTICK_SENSEHAT=m
CONFIG_INPUT_TABLET=y
CONFIG_TABLET_USB_ACECAD=m
CONFIG_TABLET_USB_AIPTEK=m
CONFIG_TABLET_USB_HANWANG=m
CONFIG_TABLET_USB_KBTAB=m
CONFIG_TABLET_USB_PEGASUS=m
CONFIG_TABLET_SERIAL_WACOM4=m
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=m
CONFIG_TOUCHSCREEN_AD7877=m
CONFIG_TOUCHSCREEN_AD7879=m
CONFIG_TOUCHSCREEN_AD7879_I2C=m
CONFIG_TOUCHSCREEN_AD7879_SPI=m
CONFIG_TOUCHSCREEN_ADC=m
CONFIG_TOUCHSCREEN_AR1021_I2C=m
CONFIG_TOUCHSCREEN_ATMEL_MXT=m
# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set
CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
CONFIG_TOUCHSCREEN_BU21013=m
CONFIG_TOUCHSCREEN_BU21029=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
# CONFIG_TOUCHSCREEN_CHIPONE_9551R is not set
CONFIG_TOUCHSCREEN_CY8CTMA140=m
CONFIG_TOUCHSCREEN_CY8CTMG110=m
CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
# CONFIG_TOUCHSCREEN_CYPRESS_CYTTSP5 is not set
CONFIG_TOUCHSCREEN_DYNAPRO=m
CONFIG_TOUCHSCREEN_HAMPSHIRE=m
CONFIG_TOUCHSCREEN_EETI=m
CONFIG_TOUCHSCREEN_EGALAX=m
CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
CONFIG_TOUCHSCREEN_EXC3000=m
CONFIG_TOUCHSCREEN_FTS=m
CONFIG_TOUCHSCREEN_FT5726=m
CONFIG_TOUCHSCREEN_FUJITSU=m
CONFIG_TOUCHSCREEN_GOODIX=m
CONFIG_TOUCHSCREEN_GSL3673=m
CONFIG_TOUCHSCREEN_GSL3673_800X1280=m
CONFIG_TOUCHSCREEN_GSLX680_PAD=m
CONFIG_TOUCHSCREEN_GT1X=m
CONFIG_TOUCHSCREEN_GT9XX=m
# CONFIG_TOUCHSCREEN_GOODIX_GTX8 is not set
CONFIG_TOUCHSCREEN_HIDEEP=m
CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
CONFIG_TOUCHSCREEN_HYN=m
CONFIG_TOUCHSCREEN_ILI210X=m
CONFIG_TOUCHSCREEN_ILITEK=m
CONFIG_TOUCHSCREEN_S6SY761=m
CONFIG_TOUCHSCREEN_GUNZE=m
CONFIG_TOUCHSCREEN_EKTF2127=m
CONFIG_TOUCHSCREEN_ELAN=m
CONFIG_TOUCHSCREEN_ELAN5515=m
CONFIG_TOUCHSCREEN_ELO=m
CONFIG_TOUCHSCREEN_WACOM_W8001=m
CONFIG_TOUCHSCREEN_WACOM_W9013=m
CONFIG_TOUCHSCREEN_WACOM_I2C=m
CONFIG_TOUCHSCREEN_MAX11801=m
CONFIG_TOUCHSCREEN_MCS5000=m
CONFIG_TOUCHSCREEN_MMS114=m
CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
CONFIG_TOUCHSCREEN_MSG2638=m
CONFIG_TOUCHSCREEN_MTOUCH=m
CONFIG_TOUCHSCREEN_IMAGIS=m
CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
CONFIG_TOUCHSCREEN_INEXIO=m
CONFIG_TOUCHSCREEN_MK712=m
# CONFIG_TOUCHSCREEN_PARADE is not set
CONFIG_TOUCHSCREEN_PENMOUNT=m
CONFIG_TOUCHSCREEN_EDT_FT5X06=m
CONFIG_TOUCHSCREEN_RASPITS_FT5426=m
CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
CONFIG_TOUCHSCREEN_TOUCHWIN=m
CONFIG_TOUCHSCREEN_PIXCIR=m
CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
CONFIG_TOUCHSCREEN_WM97XX=m
CONFIG_TOUCHSCREEN_WM9705=y
CONFIG_TOUCHSCREEN_WM9712=y
CONFIG_TOUCHSCREEN_WM9713=y
CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
CONFIG_TOUCHSCREEN_TOUCHIT213=m
CONFIG_TOUCHSCREEN_TSC_SERIO=m
CONFIG_TOUCHSCREEN_TSC200X_CORE=m
CONFIG_TOUCHSCREEN_TSC2004=m
CONFIG_TOUCHSCREEN_TSC2005=m
CONFIG_TOUCHSCREEN_TSC2007=m
CONFIG_TOUCHSCREEN_TSC2007_IIO=y
CONFIG_TOUCHSCREEN_RM_TS=m
CONFIG_TOUCHSCREEN_SILEAD=m
CONFIG_TOUCHSCREEN_SIS_I2C=m
CONFIG_TOUCHSCREEN_ST1232=m
CONFIG_TOUCHSCREEN_STMFTS=m
CONFIG_TOUCHSCREEN_SUR40=m
CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
CONFIG_TOUCHSCREEN_SX8654=m
CONFIG_TOUCHSCREEN_TPS6507X=m
CONFIG_TOUCHSCREEN_ZET6223=m
CONFIG_TOUCHSCREEN_ZFORCE=m
CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
CONFIG_TOUCHSCREEN_ROHM_BU21023=m
CONFIG_TOUCHSCREEN_IQS5XX=m
CONFIG_TOUCHSCREEN_ZINITIX=m
# CONFIG_TOUCHSCREEN_HIMAX_CHIPSET is not set
CONFIG_ROCKCHIP_REMOTECTL=y
CONFIG_ROCKCHIP_REMOTECTL_PWM=y

#
# handle all sensors
#
# CONFIG_SENSOR_DEVICE is not set
CONFIG_INPUT_MISC=y
CONFIG_INPUT_AD714X=m
CONFIG_INPUT_AD714X_I2C=m
CONFIG_INPUT_AD714X_SPI=m
CONFIG_INPUT_ATMEL_CAPTOUCH=m
CONFIG_INPUT_BMA150=m
CONFIG_INPUT_E3X0_BUTTON=m
CONFIG_INPUT_MMA8450=m
CONFIG_INPUT_GPIO_BEEPER=m
CONFIG_INPUT_GPIO_DECODER=m
CONFIG_INPUT_GPIO_VIBRA=m
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
CONFIG_INPUT_KXTJ9=m
CONFIG_INPUT_POWERMATE=m
CONFIG_INPUT_YEALINK=m
CONFIG_INPUT_CM109=m
CONFIG_INPUT_REGULATOR_HAPTIC=m
CONFIG_INPUT_UINPUT=y
CONFIG_INPUT_PCF8574=m
CONFIG_INPUT_PWM_BEEPER=m
CONFIG_INPUT_PWM_VIBRA=m
CONFIG_INPUT_RK805_PWRKEY=y
CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
# CONFIG_INPUT_DA7280_HAPTICS is not set
CONFIG_INPUT_ADXL34X=m
CONFIG_INPUT_ADXL34X_I2C=m
CONFIG_INPUT_ADXL34X_SPI=m
# CONFIG_INPUT_IBM_PANEL is not set
CONFIG_INPUT_IMS_PCU=m
CONFIG_INPUT_IQS269A=m
# CONFIG_INPUT_IQS626A is not set
# CONFIG_INPUT_IQS7222 is not set
CONFIG_INPUT_CMA3000=m
CONFIG_INPUT_CMA3000_I2C=m
CONFIG_INPUT_DRV260X_HAPTICS=m
CONFIG_INPUT_DRV2665_HAPTICS=m
CONFIG_INPUT_DRV2667_HAPTICS=m
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=m
CONFIG_RMI4_SPI=m
CONFIG_RMI4_SMB=m
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=y
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
CONFIG_RMI4_F3A=y
CONFIG_RMI4_F54=y
CONFIG_RMI4_F55=y

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=m
CONFIG_SERIO_AMBAKMI=m
CONFIG_SERIO_PCIPS2=m
CONFIG_SERIO_LIBPS2=m
CONFIG_SERIO_RAW=m
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
CONFIG_GAMEPORT=m
# CONFIG_GAMEPORT_NS558 is not set
# CONFIG_GAMEPORT_L4 is not set
# CONFIG_GAMEPORT_EMU10K1 is not set
# CONFIG_GAMEPORT_FM801 is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_PNP=y
CONFIG_SERIAL_8250_16550A_VARIANTS=y
CONFIG_SERIAL_8250_FINTEK=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=10
CONFIG_SERIAL_8250_RUNTIME_UARTS=10
# CONFIG_SERIAL_8250_EXTENDED is not set
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_8250_PERICOM=y
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
CONFIG_SERIAL_AMBA_PL010=m
CONFIG_SERIAL_AMBA_PL011=m
# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_NOZOMI is not set
# CONFIG_NULL_TTY is not set
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
# CONFIG_RPMSG_TTY is not set
CONFIG_SERIAL_DEV_BUS=m
# CONFIG_TTY_PRINTK is not set
CONFIG_VIRTIO_CONSOLE=m
# CONFIG_IPMI_HANDLER is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
# CONFIG_HW_RANDOM_BA431 is not set
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_OPTEE=y
# CONFIG_HW_RANDOM_CCTRNG is not set
# CONFIG_HW_RANDOM_XIPHERA is not set
CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
CONFIG_HW_RANDOM_CN10K=y
CONFIG_HW_RANDOM_ROCKCHIP=y
# CONFIG_APPLICOM is not set
CONFIG_DEVMEM=y
CONFIG_DEVPORT=y
CONFIG_TCG_TPM=m
CONFIG_HW_RANDOM_TPM=y
CONFIG_TCG_TIS_CORE=m
CONFIG_TCG_TIS=m
CONFIG_TCG_TIS_SPI=m
CONFIG_TCG_TIS_SPI_CR50=y
CONFIG_TCG_TIS_I2C=m
CONFIG_TCG_TIS_I2C_CR50=m
CONFIG_TCG_TIS_I2C_ATMEL=m
CONFIG_TCG_TIS_I2C_INFINEON=m
CONFIG_TCG_TIS_I2C_NUVOTON=m
CONFIG_TCG_ATMEL=m
CONFIG_TCG_INFINEON=m
CONFIG_TCG_CRB=m
CONFIG_TCG_VTPM_PROXY=m
CONFIG_TCG_FTPM_TEE=m
CONFIG_TCG_TIS_ST33ZP24=m
CONFIG_TCG_TIS_ST33ZP24_I2C=m
CONFIG_TCG_TIS_ST33ZP24_SPI=m
# CONFIG_XILLYBUS is not set
# CONFIG_XILLYUSB is not set
CONFIG_RANDOM_TRUST_CPU=y
CONFIG_RANDOM_TRUST_BOOTLOADER=y
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=m
CONFIG_I2C_MUX_GPIO=m
CONFIG_I2C_MUX_GPMUX=m
CONFIG_I2C_MUX_LTC4306=m
CONFIG_I2C_MUX_PCA9541=m
CONFIG_I2C_MUX_PCA954x=m
CONFIG_I2C_MUX_PINCTRL=m
CONFIG_I2C_MUX_REG=m
CONFIG_I2C_DEMUX_PINCTRL=m
CONFIG_I2C_MUX_MLXCPLD=m
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_ALGOBIT=y

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
CONFIG_I2C_CCGX_UCSI=m
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set

#
# ACPI drivers
#
CONFIG_I2C_SCMI=m

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CADENCE is not set
# CONFIG_I2C_CBUS_GPIO is not set
CONFIG_I2C_DESIGNWARE_CORE=m
CONFIG_I2C_DESIGNWARE_SLAVE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=m
CONFIG_I2C_DESIGNWARE_PCI=m
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=m
# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
# CONFIG_I2C_HISI is not set
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
CONFIG_I2C_RK3X=y
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_THUNDERX is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_CP2615 is not set
# CONFIG_I2C_PCI1XXXX is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
CONFIG_I2C_TINY_USB=m

#
# Other I2C/SMBus bus drivers
#
CONFIG_I2C_VIRTIO=m
# end of I2C Hardware Bus support

CONFIG_I2C_STUB=m
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=m
CONFIG_I2C_SLAVE_TESTUNIT=m
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

# CONFIG_I3C is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y

#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
CONFIG_SPI_BITBANG=y
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_CADENCE_XSPI is not set
CONFIG_SPI_DESIGNWARE=m
CONFIG_SPI_DW_DMA=y
# CONFIG_SPI_DW_PCI is not set
# CONFIG_SPI_DW_MMIO is not set
# CONFIG_SPI_HISI_KUNPENG is not set
# CONFIG_SPI_HISI_SFC_V3XX is not set
# CONFIG_SPI_NXP_FLEXSPI is not set
CONFIG_SPI_GPIO=m
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_MICROCHIP_CORE is not set
# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
# CONFIG_SPI_OC_TINY is not set
CONFIG_SPI_PL022=m
# CONFIG_SPI_PXA2XX is not set
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_ROCKCHIP_MISCDEV=y
CONFIG_SPI_ROCKCHIP_FLEXBUS_FSPI=y
CONFIG_SPI_ROCKCHIP_FLEXBUS_SPI=y
CONFIG_SPI_ROCKCHIP_SFC=y
CONFIG_SPI_ROCKCHIP_SLAVE=y
CONFIG_SPI_ROCKCHIP_SLAVE_MISCDEV=y
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_THUNDERX is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_SPI_AMD is not set

#
# SPI Multiplexer support
#
# CONFIG_SPI_MUX is not set

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_LOOPBACK_TEST is not set
# CONFIG_SPI_TLE62X0 is not set
CONFIG_SPI_SLAVE=y
CONFIG_SPI_SLAVE_TIME=y
CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y
CONFIG_SPI_SLAVE_ROCKCHIP_OBJ=y
CONFIG_SPI_DYNAMIC=y
# CONFIG_SPMI is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set

#
# PPS clients support
#
CONFIG_PPS_CLIENT_KTIMER=m
# CONFIG_PPS_CLIENT_LDISC is not set
CONFIG_PPS_CLIENT_GPIO=m

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
# CONFIG_DP83640_PHY is not set
# CONFIG_PTP_1588_CLOCK_INES is not set
CONFIG_PTP_1588_CLOCK_KVM=y
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
# CONFIG_PTP_1588_CLOCK_OCP is not set
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_PINCTRL_AMD is not set
# CONFIG_PINCTRL_CY8C95X0 is not set
# CONFIG_PINCTRL_MCP23S08 is not set
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
# CONFIG_PINCTRL_OCELOT is not set
CONFIG_PINCTRL_RK805=y
CONFIG_PINCTRL_RK806=y
CONFIG_PINCTRL_ROCKCHIP=y
# CONFIG_PINCTRL_SINGLE is not set
# CONFIG_PINCTRL_STMFX is not set
# CONFIG_PINCTRL_SX150X is not set

#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers

CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_FTGPIO010 is not set
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HISI is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_LOGICVC is not set
# CONFIG_GPIO_MB86S7X is not set
# CONFIG_GPIO_PL061 is not set
CONFIG_GPIO_ROCKCHIP=y
# CONFIG_GPIO_SIFIVE is not set
# CONFIG_GPIO_SYSCON is not set
# CONFIG_GPIO_XGENE is not set
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
# CONFIG_GPIO_ADNP is not set
# CONFIG_GPIO_AW9110 is not set
# CONFIG_GPIO_GW_PLD is not set
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_NCA9539 is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCA9570 is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_TPIC2810 is not set
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set
# end of PCI GPIO expanders

#
# SPI GPIO expanders
#
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
# end of USB GPIO expanders

#
# Virtual GPIO drivers
#
# CONFIG_GPIO_AGGREGATOR is not set
# CONFIG_GPIO_MOCKUP is not set
# CONFIG_GPIO_VIRTIO is not set
# CONFIG_GPIO_SIM is not set
# end of Virtual GPIO drivers

#
# Other GPIO expanders
#
# CONFIG_GPIO_CASCADE is not set
CONFIG_W1=m
CONFIG_W1_CON=y

#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_MATROX=m
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
CONFIG_W1_MASTER_DS1WM=m
CONFIG_W1_MASTER_GPIO=m
CONFIG_W1_MASTER_SGI=m
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
CONFIG_W1_SLAVE_DS2405=m
CONFIG_W1_SLAVE_DS2408=m
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
CONFIG_W1_SLAVE_DS2805=m
CONFIG_W1_SLAVE_DS2430=m
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
CONFIG_W1_SLAVE_DS2438=m
CONFIG_W1_SLAVE_DS250X=m
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
CONFIG_W1_SLAVE_DS28E17=m
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_BRCMSTB is not set
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
# CONFIG_POWER_RESET_LTC2952 is not set
CONFIG_POWER_RESET_REGULATOR=y
# CONFIG_POWER_RESET_RESTART is not set
# CONFIG_POWER_RESET_XGENE is not set
# CONFIG_POWER_RESET_SYSCON is not set
# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
CONFIG_NVMEM_REBOOT_MODE=y
# CONFIG_POWER_SEQUENCING is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_PDA_POWER is not set
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_IP5XXX_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_CW2017 is not set
# CONFIG_BATTERY_CW221X is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SAMSUNG_SDI is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_BATTERY_MAX1721X is not set
CONFIG_CHARGER_CPS5601X=m
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
CONFIG_CHARGER_GPIO=m
# CONFIG_CHARGER_MANAGER is not set
CONFIG_ROCKCHIP_CHARGER_MANAGER=m
CONFIG_ROCKCHIP_CHARGER_MANAGER_CHARGE_PUMP=y
# CONFIG_CHARGER_LT3651 is not set
# CONFIG_CHARGER_LTC4162L is not set
# CONFIG_CHARGER_SC8551 is not set
CONFIG_CHARGER_SC89601=m
# CONFIG_CHARGER_SC89890 is not set
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_MAX77976 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25700 is not set
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_BQ25980 is not set
# CONFIG_CHARGER_BQ256XX is not set
CONFIG_BATTERY_RK816=m
CONFIG_BATTERY_RK817=m
CONFIG_CHARGER_RK817=m
CONFIG_BATTERY_RK818=m
CONFIG_CHARGER_RK818=m
# CONFIG_CHARGER_SGM41542 is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_BATTERY_GOLDFISH is not set
# CONFIG_BATTERY_RT5033 is not set
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
# CONFIG_BATTERY_UG3105 is not set
# CONFIG_NANOPI_ADC_POWER is not set
CONFIG_HWMON=y
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM1177 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7310 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_AHT10 is not set
# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
# CONFIG_SENSORS_AS370 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
CONFIG_SENSORS_ARM_SCMI=y
CONFIG_SENSORS_ARM_SCPI=y
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_CORSAIR_CPRO is not set
# CONFIG_SENSORS_CORSAIR_PSU is not set
# CONFIG_SENSORS_DRIVETEMP is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_I5K_AMB is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_FTSTEUTATES is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_G762 is not set
CONFIG_SENSORS_GPIO_FAN=m
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_IIO_HWMON is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_POWR1220 is not set
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LTC2945 is not set
# CONFIG_SENSORS_LTC2947_I2C is not set
# CONFIG_SENSORS_LTC2947_SPI is not set
# CONFIG_SENSORS_LTC2990 is not set
# CONFIG_SENSORS_LTC2992 is not set
# CONFIG_SENSORS_LTC4151 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4222 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LTC4260 is not set
# CONFIG_SENSORS_LTC4261 is not set
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX127 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX197 is not set
# CONFIG_SENSORS_MAX31722 is not set
# CONFIG_SENSORS_MAX31730 is not set
# CONFIG_SENSORS_MAX31760 is not set
# CONFIG_SENSORS_MAX6620 is not set
# CONFIG_SENSORS_MAX6621 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MAX6697 is not set
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_TPS23861 is not set
# CONFIG_SENSORS_MR75203 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LM95234 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_NCT6683 is not set
# CONFIG_SENSORS_NCT6775 is not set
# CONFIG_SENSORS_NCT6775_I2C is not set
# CONFIG_SENSORS_NCT7802 is not set
# CONFIG_SENSORS_NCT7904 is not set
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
# CONFIG_SENSORS_NZXT_SMART2 is not set
# CONFIG_SENSORS_OCC_P8_I2C is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_PMBUS is not set
CONFIG_SENSORS_PWM_FAN=m
# CONFIG_SENSORS_SBTSI is not set
# CONFIG_SENSORS_SBRMI is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHT4x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC2305 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA238 is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_TMP464 is not set
# CONFIG_SENSORS_TMP513 is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_XGENE is not set

#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
# CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE is not set
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR=y
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
# CONFIG_THERMAL_EMULATION is not set
# CONFIG_THERMAL_MMIO is not set
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_RK_VIRTUAL_THERMAL=y
CONFIG_GENERIC_ADC_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set
# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=m
CONFIG_GPIO_WATCHDOG=m
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
# CONFIG_ARM_SP805_WATCHDOG is not set
# CONFIG_ARM_SBSA_WATCHDOG is not set
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=y
# CONFIG_MAX63XX_WATCHDOG is not set
CONFIG_KHADAS_WATCHDOG=y
# CONFIG_ARM_SMC_WATCHDOG is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_HP_WATCHDOG is not set
# CONFIG_MEN_A21_WDT is not set

#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
CONFIG_BCMA_HOST_PCI=y
# CONFIG_BCMA_HOST_SOC is not set
CONFIG_BCMA_DRIVER_PCI=y
# CONFIG_BCMA_DRIVER_GMAC_CMN is not set
# CONFIG_BCMA_DRIVER_GPIO is not set
# CONFIG_BCMA_DEBUG is not set

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AXP20X_I2C is not set
# CONFIG_MFD_MADERA is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77714 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MAX96745 is not set
# CONFIG_MFD_MAX96755F is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6370 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_MFD_OCELOT is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_NTXEC is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_UCB1400_CORE is not set
# CONFIG_MFD_SY7636A is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT4831 is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RT5120 is not set
# CONFIG_MFD_RC5T583 is not set
CONFIG_MFD_RK618=y
CONFIG_MFD_RK630=m
CONFIG_MFD_RK630_I2C=m
CONFIG_MFD_RK630_SPI=m
CONFIG_MFD_RK806=y
CONFIG_MFD_RK806_I2C=y
CONFIG_MFD_RK806_SPI=y
CONFIG_MFD_RK808=y
CONFIG_MFD_RK1000=y

#
# driver for different display serdes
#
CONFIG_MFD_SERDES_DISPLAY=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96745=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96749=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96752=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96755=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96772=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96789=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18TL82=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18RL82=y
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP=y
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP_RKX111=y
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP_RKX121=y
CONFIG_SERDES_DISPLAY_CHIP_NOVO=y
CONFIG_SERDES_DISPLAY_CHIP_NOVO_NCA9539=y
CONFIG_MFD_RKX110_X120=m
CONFIG_PWM_RKX120=m
CONFIG_ROCKCHIP_SERDES_DRM_PANEL=m
CONFIG_MFD_ROCKCHIP_FLEXBUS=y
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
CONFIG_MFD_SIMPLE_MFD_I2C=m
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TQMX86 is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
# CONFIG_MFD_ROHM_BD71828 is not set
# CONFIG_MFD_ROHM_BD957XMUF is not set
# CONFIG_MFD_STPMIC1 is not set
# CONFIG_MFD_STMFX is not set
# CONFIG_MFD_ATC260X_I2C is not set
# CONFIG_MFD_KHADAS_MCU is not set
# CONFIG_MFD_QCOM_PM8008 is not set
# CONFIG_RAVE_SP_CORE is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# CONFIG_MFD_RSMU_I2C is not set
# CONFIG_MFD_RSMU_SPI is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
CONFIG_REGULATOR_USERSPACE_CONSUMER=m
CONFIG_REGULATOR_88PG86X=m
CONFIG_REGULATOR_ACT8865=m
CONFIG_REGULATOR_AD5398=m
CONFIG_REGULATOR_ARM_SCMI=y
CONFIG_REGULATOR_DA9121=m
CONFIG_REGULATOR_DA9210=m
CONFIG_REGULATOR_DA9211=m
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_FAN53880=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_ISL9305=m
CONFIG_REGULATOR_ISL6271A=m
CONFIG_REGULATOR_LP3971=m
CONFIG_REGULATOR_LP3972=m
CONFIG_REGULATOR_LP872X=m
CONFIG_REGULATOR_LP8752=m
CONFIG_REGULATOR_LP8755=m
CONFIG_REGULATOR_LTC3589=m
CONFIG_REGULATOR_LTC3676=m
CONFIG_REGULATOR_MAX1586=m
CONFIG_REGULATOR_MAX8649=m
CONFIG_REGULATOR_MAX8660=m
CONFIG_REGULATOR_MAX8893=m
CONFIG_REGULATOR_MAX8952=m
CONFIG_REGULATOR_MAX8973=m
CONFIG_REGULATOR_MAX20086=m
CONFIG_REGULATOR_MAX77826=m
CONFIG_REGULATOR_MCP16502=m
CONFIG_REGULATOR_MP5416=m
CONFIG_REGULATOR_MP8859=m
CONFIG_REGULATOR_MP8865=m
CONFIG_REGULATOR_MP886X=m
CONFIG_REGULATOR_MPQ7920=m
CONFIG_REGULATOR_MT6311=m
CONFIG_REGULATOR_PCA9450=m
CONFIG_REGULATOR_PF8X00=m
CONFIG_REGULATOR_PFUZE100=m
CONFIG_REGULATOR_PV88060=m
CONFIG_REGULATOR_PV88080=m
CONFIG_REGULATOR_PV88090=m
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
CONFIG_REGULATOR_RK801=y
CONFIG_REGULATOR_RK806=y
CONFIG_REGULATOR_RK808=y
CONFIG_REGULATOR_RK860X=y
CONFIG_REGULATOR_RT4801=m
CONFIG_REGULATOR_RT5190A=m
CONFIG_REGULATOR_RT5759=m
CONFIG_REGULATOR_RT6160=m
CONFIG_REGULATOR_RT6245=m
CONFIG_REGULATOR_RTQ2134=m
CONFIG_REGULATOR_RTMV20=m
CONFIG_REGULATOR_RTQ6752=m
CONFIG_REGULATOR_SLG51000=m
CONFIG_REGULATOR_SY8106A=m
CONFIG_REGULATOR_SY8824X=m
CONFIG_REGULATOR_SY8827N=m
CONFIG_REGULATOR_TPS51632=m
CONFIG_REGULATOR_TPS62360=m
CONFIG_REGULATOR_TPS6286X=m
CONFIG_REGULATOR_TPS65023=m
CONFIG_REGULATOR_TPS6507X=m
CONFIG_REGULATOR_TPS65132=m
CONFIG_REGULATOR_TPS6524X=m
CONFIG_REGULATOR_VCTRL=m
CONFIG_REGULATOR_WL2868C=m
CONFIG_REGULATOR_XZ3216=m
CONFIG_RC_CORE=y
# CONFIG_LIRC is not set
CONFIG_RC_MAP=m
CONFIG_RC_DECODERS=y
CONFIG_IR_IMON_DECODER=m
CONFIG_IR_JVC_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
CONFIG_IR_RCMM_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_XMP_DECODER=m
CONFIG_RC_DEVICES=y
CONFIG_IR_ENE=m
CONFIG_IR_FINTEK=m
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_HIX5HD2=m
CONFIG_IR_IGORPLUGUSB=m
CONFIG_IR_IGUANA=m
CONFIG_IR_IMON=m
CONFIG_IR_IMON_RAW=m
CONFIG_IR_ITE_CIR=m
CONFIG_IR_MCEUSB=m
CONFIG_IR_NUVOTON=m
CONFIG_IR_REDRAT3=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_STREAMZAP=m
CONFIG_IR_TOY=m
CONFIG_IR_TTUSBIR=m
CONFIG_RC_ATI_REMOTE=m
CONFIG_RC_LOOPBACK=m
CONFIG_RC_XBOX_DVD=m
CONFIG_CEC_CORE=y

#
# CEC support
#
CONFIG_MEDIA_CEC_RC=y
CONFIG_MEDIA_CEC_SUPPORT=y
CONFIG_CEC_CH7322=m
CONFIG_USB_PULSE8_CEC=m
CONFIG_USB_RAINSHADOW_CEC=m
# end of CEC support

CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_SUPPORT_FILTER=y
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_SDR_SUPPORT is not set
CONFIG_MEDIA_PLATFORM_SUPPORT=y
# CONFIG_MEDIA_TEST_SUPPORT is not set
# end of Media device types

CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CONTROLLER=y

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_H264=y
CONFIG_V4L2_VP9=y
CONFIG_V4L2_MEM2MEM_DEV=y
# CONFIG_V4L2_FLASH_LED_CLASS is not set
CONFIG_V4L2_FWNODE=y
CONFIG_V4L2_ASYNC=y
# end of Video4Linux options

#
# Media controller options
#
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
# end of Media controller options

#
# Media drivers
#

#
# Drivers filtered as selected at 'Filter media drivers'
#

#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_GSPCA=m
CONFIG_USB_GSPCA_BENQ=m
CONFIG_USB_GSPCA_CONEX=m
CONFIG_USB_GSPCA_CPIA1=m
CONFIG_USB_GSPCA_DTCS033=m
CONFIG_USB_GSPCA_ETOMS=m
CONFIG_USB_GSPCA_FINEPIX=m
CONFIG_USB_GSPCA_JEILINJ=m
CONFIG_USB_GSPCA_JL2005BCD=m
CONFIG_USB_GSPCA_KINECT=m
CONFIG_USB_GSPCA_KONICA=m
CONFIG_USB_GSPCA_MARS=m
CONFIG_USB_GSPCA_MR97310A=m
CONFIG_USB_GSPCA_NW80X=m
CONFIG_USB_GSPCA_OV519=m
CONFIG_USB_GSPCA_OV534=m
CONFIG_USB_GSPCA_OV534_9=m
CONFIG_USB_GSPCA_PAC207=m
CONFIG_USB_GSPCA_PAC7302=m
CONFIG_USB_GSPCA_PAC7311=m
CONFIG_USB_GSPCA_SE401=m
CONFIG_USB_GSPCA_SN9C2028=m
CONFIG_USB_GSPCA_SN9C20X=m
CONFIG_USB_GSPCA_SONIXB=m
CONFIG_USB_GSPCA_SONIXJ=m
CONFIG_USB_GSPCA_SPCA1528=m
CONFIG_USB_GSPCA_SPCA500=m
CONFIG_USB_GSPCA_SPCA501=m
CONFIG_USB_GSPCA_SPCA505=m
CONFIG_USB_GSPCA_SPCA506=m
CONFIG_USB_GSPCA_SPCA508=m
CONFIG_USB_GSPCA_SPCA561=m
CONFIG_USB_GSPCA_SQ905=m
CONFIG_USB_GSPCA_SQ905C=m
CONFIG_USB_GSPCA_SQ930X=m
CONFIG_USB_GSPCA_STK014=m
CONFIG_USB_GSPCA_STK1135=m
CONFIG_USB_GSPCA_STV0680=m
CONFIG_USB_GSPCA_SUNPLUS=m
CONFIG_USB_GSPCA_T613=m
CONFIG_USB_GSPCA_TOPRO=m
CONFIG_USB_GSPCA_TOUPTEK=m
CONFIG_USB_GSPCA_TV8532=m
CONFIG_USB_GSPCA_VC032X=m
CONFIG_USB_GSPCA_VICAM=m
CONFIG_USB_GSPCA_XIRLINK_CIT=m
CONFIG_USB_GSPCA_ZC3XX=m
CONFIG_USB_GL860=m
CONFIG_USB_M5602=m
CONFIG_USB_STV06XX=m
CONFIG_USB_PWC=m
# CONFIG_USB_PWC_DEBUG is not set
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_USB_S2255=m
CONFIG_VIDEO_USBTV=m
CONFIG_USB_VIDEO_CLASS=m
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y

#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=m
CONFIG_VIDEO_EM28XX_V4L2=m
CONFIG_VIDEO_EM28XX_ALSA=m
CONFIG_VIDEO_EM28XX_RC=m
CONFIG_MEDIA_PCI_SUPPORT=y

#
# Media capture support
#
CONFIG_VIDEO_SOLO6X10=m
CONFIG_VIDEO_TW5864=m
CONFIG_VIDEO_TW68=m
CONFIG_VIDEO_TW686X=m
CONFIG_VIDEO_ZORAN=m
CONFIG_VIDEO_ZORAN_DC30=y
CONFIG_VIDEO_ZORAN_ZR36060=y
CONFIG_VIDEO_ZORAN_BUZ=y
CONFIG_VIDEO_ZORAN_DC10=y
CONFIG_VIDEO_ZORAN_LML33=y
CONFIG_VIDEO_ZORAN_LML33R10=y
CONFIG_VIDEO_ZORAN_AVS6EYES=y
CONFIG_MEDIA_PLATFORM_DRIVERS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
CONFIG_VIDEO_MUX=m

#
# Allegro DVT media platform drivers
#

#
# Amlogic media platform drivers
#

#
# Amphion drivers
#

#
# Aspeed media platform drivers
#
# CONFIG_VIDEO_ASPEED is not set

#
# Atmel media platform drivers
#

#
# Cadence media platform drivers
#
# CONFIG_VIDEO_CADENCE_CSI2RX is not set
# CONFIG_VIDEO_CADENCE_CSI2TX is not set

#
# Chips&Media media platform drivers
#

#
# Intel media platform drivers
#

#
# Marvell media platform drivers
#
# CONFIG_VIDEO_CAFE_CCIC is not set

#
# Mediatek media platform drivers
#

#
# NVidia media platform drivers
#

#
# NXP media platform drivers
#

#
# Qualcomm media platform drivers
#

#
# Renesas media platform drivers
#

#
# Rockchip media platform drivers
#
CONFIG_VIDEO_ROCKCHIP_AIISP=y
CONFIG_VIDEO_ROCKCHIP_AVSP=y
CONFIG_VIDEO_ROCKCHIP_CIF=y
CONFIG_ROCKCHIP_CIF_WORKMODE_PINGPONG=y
# CONFIG_ROCKCHIP_CIF_WORKMODE_ONEFRAME is not set
CONFIG_ROCKCHIP_CIF_USE_DUMMY_BUF=y
# CONFIG_ROCKCHIP_CIF_USE_NONE_DUMMY_BUF is not set
CONFIG_ROCKCHIP_CIF_USE_MONITOR=y
CONFIG_ROCKCHIP_CIF_MONITOR_MODE=0x1
CONFIG_ROCKCHIP_CIF_MONITOR_START_FRAME=0
CONFIG_ROCKCHIP_CIF_MONITOR_CYCLE=0x8
CONFIG_ROCKCHIP_CIF_MONITOR_KEEP_TIME=0x3e8
CONFIG_ROCKCHIP_CIF_MONITOR_ERR_CNT=0x5
CONFIG_ROCKCHIP_CIF_RESET_BY_USER=y
CONFIG_VIDEO_ROCKCHIP_FEC=y
CONFIG_ROCKCHIP_FLEXBUS_CIF=y
CONFIG_ROCKCHIP_FLEXBUS_CIF_USE_DUMMY_BUF=y
# CONFIG_ROCKCHIP_FLEXBUS_CIF_USE_NONE_DUMMY_BUF is not set
CONFIG_VIDEO_ROCKCHIP_RKISP1=m
CONFIG_VIDEO_ROCKCHIP_ISP=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V1X=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V21=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V30=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32=y
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35=y
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35_DBG is not set
CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39=y
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39_DBG is not set
CONFIG_VIDEO_ROCKCHIP_ISPP=y
CONFIG_VIDEO_ROCKCHIP_ISPP_FEC=y
CONFIG_VIDEO_ROCKCHIP_ISPP_VERSION_V20=y
CONFIG_VIDEO_ROCKCHIP_HDMIRX_CLASS=y
CONFIG_VIDEO_ROCKCHIP_HDMIRX=y
CONFIG_VIDEO_ROCKCHIP_RGA=y
CONFIG_VIDEO_ROCKCHIP_ISP1=m
CONFIG_VIDEO_ROCKCHIP_VPSS=y
CONFIG_VIDEO_ROCKCHIP_VPSS_V10=y
CONFIG_VIDEO_ROCKCHIP_VPSS_V20=y

#
# Samsung media platform drivers
#

#
# STMicroelectronics media platform drivers
#

#
# Sunxi media platform drivers
#

#
# Texas Instruments drivers
#

#
# Verisilicon media platform drivers
#
CONFIG_VIDEO_HANTRO=y
CONFIG_VIDEO_HANTRO_ROCKCHIP=y

#
# VIA media platform drivers
#

#
# Xilinx media platform drivers
#
# CONFIG_VIDEO_XILINX is not set
CONFIG_VIDEO_TVEEPROM=m
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_CMA_SG=y
CONFIG_VIDEOBUF2_DMA_CONTIG=y
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_VIDEOBUF2_DMA_SG=y
# end of Media drivers

#
# Media ancillary drivers
#
CONFIG_VIDEO_CAM_SLEEP_WAKEUP=m

#
# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
#
CONFIG_VIDEO_IR_I2C=m
CONFIG_VIDEO_CAMERA_SENSOR=y
CONFIG_VIDEO_APTINA_PLL=m
CONFIG_VIDEO_CCS_PLL=m
CONFIG_VIDEO_AR0230=m
CONFIG_VIDEO_AR0521=m
# CONFIG_VIDEO_AR0822 is not set
# CONFIG_VIDEO_AR2020 is not set
CONFIG_VIDEO_BF3925=m
CONFIG_VIDEO_GC02M2=m
CONFIG_VIDEO_GC0312=m
CONFIG_VIDEO_GC0329=m
CONFIG_VIDEO_GC0403=m
CONFIG_VIDEO_GC05A2=m
CONFIG_VIDEO_GC08A3=m
CONFIG_VIDEO_GC1084=m
CONFIG_VIDEO_GC16B3C=m
CONFIG_VIDEO_GC2035=m
CONFIG_VIDEO_GC2053=m
CONFIG_VIDEO_GC2093=m
CONFIG_VIDEO_GC2145=m
CONFIG_VIDEO_GC2155=m
CONFIG_VIDEO_GC2355=m
CONFIG_VIDEO_GC2375H=m
CONFIG_VIDEO_GC2385=m
CONFIG_VIDEO_GC3003=m
CONFIG_VIDEO_GC32E1=m
CONFIG_VIDEO_GC4023=m
CONFIG_VIDEO_GC4653=m
CONFIG_VIDEO_GC4663=m
CONFIG_VIDEO_GC4C33=m
CONFIG_VIDEO_GC5024=m
CONFIG_VIDEO_GC5025=m
CONFIG_VIDEO_GC5035=m
CONFIG_VIDEO_GC6603=m
CONFIG_VIDEO_GC8034=m
CONFIG_VIDEO_GC8613=m
CONFIG_VIDEO_HI556=m
CONFIG_VIDEO_HI846=m
CONFIG_VIDEO_HI847=m
CONFIG_VIDEO_IMX208=m
CONFIG_VIDEO_IMX214=m
CONFIG_VIDEO_IMX214_EEPROM=m
CONFIG_VIDEO_IMX219=m
CONFIG_VIDEO_IMX258=m
CONFIG_VIDEO_IMX258_EEPROM=m
CONFIG_VIDEO_IMX274=m
CONFIG_VIDEO_IMX290=m
CONFIG_VIDEO_IMX307=m
CONFIG_VIDEO_IMX317=m
CONFIG_VIDEO_IMX319=m
CONFIG_VIDEO_IMX323=m
CONFIG_VIDEO_IMX327=m
CONFIG_VIDEO_IMX334=m
CONFIG_VIDEO_IMX335=m
CONFIG_VIDEO_IMX347=m
CONFIG_VIDEO_IMX355=m
CONFIG_VIDEO_IMX378=m
CONFIG_VIDEO_IMX386=m
CONFIG_VIDEO_IMX412=m
CONFIG_VIDEO_IMX415=m
CONFIG_VIDEO_IMX464=m
CONFIG_VIDEO_IMX492=m
CONFIG_VIDEO_IMX498=m
CONFIG_VIDEO_IMX577=m
CONFIG_VIDEO_IMX582=m
CONFIG_VIDEO_IMX586=m
CONFIG_VIDEO_IMX678=m
CONFIG_VIDEO_IMX766=m
CONFIG_VIDEO_JX_F37=m
CONFIG_VIDEO_JX_H62=m
CONFIG_VIDEO_JX_H65=m
CONFIG_VIDEO_JX_K17=m
CONFIG_VIDEO_MAX9271_LIB=m
# CONFIG_VIDEO_MIS2031 is not set
# CONFIG_VIDEO_MIS4001 is not set
CONFIG_VIDEO_MT9M001=m
CONFIG_VIDEO_MT9M032=m
CONFIG_VIDEO_MT9M111=m
CONFIG_VIDEO_MT9P031=m
CONFIG_VIDEO_MT9T001=m
CONFIG_VIDEO_MT9T112=m
CONFIG_VIDEO_MT9V011=m
CONFIG_VIDEO_MT9V032=m
CONFIG_VIDEO_MT9V111=m
CONFIG_VIDEO_NOON010PC30=m
# CONFIG_VIDEO_OG01A10 is not set
CONFIG_VIDEO_OG01A1B=m
# CONFIG_VIDEO_OG02B10 is not set
CONFIG_VIDEO_OS02G10=m
# CONFIG_VIDEO_OS02K10 is not set
CONFIG_VIDEO_OS03B10=m
CONFIG_VIDEO_OS04A10=m
CONFIG_VIDEO_OS04D10=m
CONFIG_VIDEO_OS04E10=m
CONFIG_VIDEO_OS05A20=m
CONFIG_VIDEO_OS05L10=m
CONFIG_VIDEO_OS08A20=m
CONFIG_VIDEO_OS12D40=m
CONFIG_VIDEO_OV02A10=m
CONFIG_VIDEO_OV02B10=m
CONFIG_VIDEO_OV02K10=m
CONFIG_VIDEO_OV08D10=m
CONFIG_VIDEO_OV12D2Q=m
CONFIG_VIDEO_OV13850=m
CONFIG_VIDEO_OV13855=m
CONFIG_VIDEO_OV13858=m
CONFIG_VIDEO_OV13B10=m
CONFIG_VIDEO_OV16880=m
CONFIG_VIDEO_OV16885=m
CONFIG_VIDEO_OV16A10=m
CONFIG_VIDEO_OV16A1Q=m
CONFIG_VIDEO_OV2640=m
CONFIG_VIDEO_OV2659=m
CONFIG_VIDEO_OV2680=m
CONFIG_VIDEO_OV2685=m
CONFIG_VIDEO_OV2718=m
CONFIG_VIDEO_OV2740=m
CONFIG_VIDEO_OV4686=m
CONFIG_VIDEO_OV4688=m
CONFIG_VIDEO_OV4689=m
CONFIG_VIDEO_OV50C40=m
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_OV5647=m
CONFIG_VIDEO_OV5648=m
CONFIG_VIDEO_OV5670=m
CONFIG_VIDEO_OV5675=m
CONFIG_VIDEO_OV5693=m
CONFIG_VIDEO_OV5695=m
CONFIG_VIDEO_OV6650=m
CONFIG_VIDEO_OV7251=m
CONFIG_VIDEO_OV7640=m
CONFIG_VIDEO_OV7670=m
CONFIG_VIDEO_OV772X=m
CONFIG_VIDEO_OV7740=m
CONFIG_VIDEO_OV8856=m
CONFIG_VIDEO_OV8858=m
CONFIG_VIDEO_OV8865=m
CONFIG_VIDEO_OV9281=m
CONFIG_VIDEO_OV9282=m
CONFIG_VIDEO_OV9640=m
CONFIG_VIDEO_OV9650=m
CONFIG_VIDEO_OV9734=m
CONFIG_VIDEO_OX03C10=m
CONFIG_VIDEO_PREISP_DUMMY_SENSOR=m
CONFIG_VIDEO_PS5458=m
CONFIG_VIDEO_RDACM20=m
CONFIG_VIDEO_RDACM21=m
CONFIG_VIDEO_RJ54N1=m
CONFIG_VIDEO_S5C73M3=m
CONFIG_VIDEO_S5K3L6XX=m
CONFIG_VIDEO_S5K3L8XX=m
CONFIG_VIDEO_S5K4ECGX=m
CONFIG_VIDEO_S5K5BAF=m
CONFIG_VIDEO_S5K6A3=m
CONFIG_VIDEO_S5K6AA=m
CONFIG_VIDEO_S5KJN1=m
CONFIG_VIDEO_SC031GS=m
CONFIG_VIDEO_SC035GS=m
CONFIG_VIDEO_SC132GS=m
# CONFIG_VIDEO_SC1346 is not set
CONFIG_VIDEO_SC200AI=m
CONFIG_VIDEO_SC210IOT=m
CONFIG_VIDEO_SC2232=m
CONFIG_VIDEO_SC2239=m
# CONFIG_VIDEO_SC223A is not set
CONFIG_VIDEO_SC230AI=m
CONFIG_VIDEO_SC2310=m
CONFIG_VIDEO_SC231HAI=m
CONFIG_VIDEO_SC2336=m
# CONFIG_VIDEO_SC2355 is not set
CONFIG_VIDEO_SC235HAI=m
CONFIG_VIDEO_SC301IOT=m
CONFIG_VIDEO_SC3336=m
# CONFIG_VIDEO_SC3336P is not set
CONFIG_VIDEO_SC3338=m
CONFIG_VIDEO_SC401AI=m
CONFIG_VIDEO_SC4210=m
CONFIG_VIDEO_SC4238=m
CONFIG_VIDEO_SC430CS=m
CONFIG_VIDEO_SC4336=m
# CONFIG_VIDEO_SC4336P is not set
CONFIG_VIDEO_SC450AI=m
CONFIG_VIDEO_SC485SL=m
CONFIG_VIDEO_SC500AI=m
CONFIG_VIDEO_SC501AI=m
CONFIG_VIDEO_SC530AI=m
# CONFIG_VIDEO_SC5336 is not set
CONFIG_VIDEO_SC635HAI=m
# CONFIG_VIDEO_SC830AI is not set
# CONFIG_VIDEO_SC831AI is not set
CONFIG_VIDEO_SC850SL=m
CONFIG_VIDEO_SENSOR_ADAPTER=y
CONFIG_VIDEO_SR030PC30=m
CONFIG_VIDEO_VS6624=m
CONFIG_VIDEO_CCS=m
CONFIG_VIDEO_ET8EK8=m
CONFIG_VIDEO_M5MOLS=m

#
# Lens drivers
#
CONFIG_VIDEO_AD5820=m
CONFIG_VIDEO_AK7375=m
CONFIG_VIDEO_AW8601=m
CONFIG_VIDEO_CES6301=m
CONFIG_VIDEO_CN3927V=m
CONFIG_VIDEO_DW9714=m
CONFIG_VIDEO_DW9763=m
CONFIG_VIDEO_DW9768=m
CONFIG_VIDEO_DW9800V=m
CONFIG_VIDEO_DW9800W=m
CONFIG_VIDEO_DW9807_VCM=m
CONFIG_VIDEO_FP5510=m
CONFIG_VIDEO_VM149C=m
# end of Lens drivers

#
# Flash devices
#
CONFIG_VIDEO_ADP1653=m
CONFIG_VIDEO_AW36518=m
CONFIG_VIDEO_LM3560=m
CONFIG_VIDEO_LM3646=m
CONFIG_VIDEO_SGM3784=m
# end of Flash devices

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_CS3308=m
CONFIG_VIDEO_CS5345=m
CONFIG_VIDEO_CS53L32A=m
CONFIG_VIDEO_MSP3400=m
CONFIG_VIDEO_SONY_BTF_MPX=m
CONFIG_VIDEO_TDA1997X=m
CONFIG_VIDEO_TDA7432=m
CONFIG_VIDEO_TDA9840=m
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
CONFIG_VIDEO_TLV320AIC23B=m
CONFIG_VIDEO_TVAUDIO=m
CONFIG_VIDEO_UDA1342=m
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_WM8739=m
CONFIG_VIDEO_WM8775=m
# end of Audio decoders, processors and mixers

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders

#
# Video decoders
#
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_ADV7183=m
CONFIG_VIDEO_ADV748X=m
CONFIG_VIDEO_ADV7604=m
# CONFIG_VIDEO_ADV7604_CEC is not set
CONFIG_VIDEO_ADV7842=m
# CONFIG_VIDEO_ADV7842_CEC is not set
CONFIG_VIDEO_BT819=m
CONFIG_VIDEO_BT856=m
CONFIG_VIDEO_BT866=m
CONFIG_VIDEO_EP9461E=m
CONFIG_VIDEO_ISL7998X=m
CONFIG_VIDEO_IT6616=m
CONFIG_VIDEO_KS0127=m
CONFIG_VIDEO_LT6911C=m
CONFIG_VIDEO_LT6911UXC=m
CONFIG_VIDEO_LT6911UXE=m
CONFIG_VIDEO_LT7911D=m
CONFIG_VIDEO_LT7911UXC=m
CONFIG_VIDEO_LT8619C=m
CONFIG_VIDEO_LT8668SX=m
CONFIG_VIDEO_MAX9286=m
# CONFIG_VIDEO_MAX96712 is not set
# CONFIG_VIDEO_MAX96714 is not set
# CONFIG_VIDEO_MAX96722 is not set
# CONFIG_VIDEO_MAX96756 is not set
CONFIG_VIDEO_ML86V7667=m
CONFIG_VIDEO_NVP6158=m
CONFIG_VIDEO_NVP6188=m
CONFIG_VIDEO_NVP6324=m
CONFIG_VIDEO_OTP_EEPROM=m
CONFIG_VIDEO_SAA7110=m
CONFIG_VIDEO_SAA711X=m
CONFIG_VIDEO_TC358743=m
# CONFIG_VIDEO_TC358743_CEC is not set
CONFIG_VIDEO_TC35874X=m
CONFIG_VIDEO_TECHPOINT=m
CONFIG_VIDEO_THCV244=m
CONFIG_VIDEO_TP2855=m
CONFIG_VIDEO_TVP514X=m
CONFIG_VIDEO_TVP5150=m
CONFIG_VIDEO_TVP7002=m
CONFIG_VIDEO_TW2804=m
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=m
CONFIG_VIDEO_TW9910=m
CONFIG_VIDEO_VPX3220=m
CONFIG_VIDEO_RK628=y
CONFIG_VIDEO_RK628_CSI=y
CONFIG_VIDEO_RK628_BT1120=y
CONFIG_VIDEO_MAXIM_SERDES=m

#
# Maxim Deserializer devices support
#
CONFIG_VIDEO_MAXIM_DES_MAXIM2C=m
CONFIG_VIDEO_MAXIM_DES_MAXIM4C=m
# end of Maxim Deserializer devices support

#
# Maxim GMSL Remote Serializer devices support
#
CONFIG_VIDEO_MAXIM_SER_MAX9295=m
CONFIG_VIDEO_MAXIM_SER_MAX96715=m
CONFIG_VIDEO_MAXIM_SER_MAX96717=m
# end of Maxim GMSL Remote Serializer devices support

#
# Maxim GMSL Remote Sensor devices support
#
CONFIG_VIDEO_MAXIM_CAM_DUMMY=m
CONFIG_VIDEO_MAXIM_CAM_SC320AT=m
CONFIG_VIDEO_MAXIM_CAM_OX01F10=m
CONFIG_VIDEO_MAXIM_CAM_OV231X=m
CONFIG_VIDEO_MAXIM_CAM_OX03C10=m
CONFIG_VIDEO_MAXIM_CAM_OX03J10=m
CONFIG_VIDEO_MAXIM_CAM_OS04A10=m
# end of Maxim GMSL Remote Sensor devices support

#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=m
CONFIG_VIDEO_CX25840=m
CONFIG_VIDEO_IT66353=m
# end of Video decoders

#
# Video encoders
#
CONFIG_VIDEO_AD9389B=m
CONFIG_VIDEO_ADV7170=m
CONFIG_VIDEO_ADV7175=m
CONFIG_VIDEO_ADV7343=m
CONFIG_VIDEO_ADV7393=m
CONFIG_VIDEO_ADV7511=m
# CONFIG_VIDEO_ADV7511_CEC is not set
CONFIG_VIDEO_AK881X=m
CONFIG_VIDEO_SAA7127=m
CONFIG_VIDEO_SAA7185=m
CONFIG_VIDEO_THS8200=m
# end of Video encoders

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
CONFIG_VIDEO_UPD64083=m
# end of Video improvement chips

#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips

#
# SDR tuner chips
#
# end of SDR tuner chips

#
# Miscellaneous helper chips
#
CONFIG_VIDEO_I2C=m
CONFIG_VIDEO_M52790=m
CONFIG_VIDEO_RK_IRCUT=y
CONFIG_VIDEO_ST_MIPID02=m
CONFIG_VIDEO_THS7303=m
# end of Miscellaneous helper chips

#
# Media SPI Adapters
#
CONFIG_VIDEO_GS1662=m
# CONFIG_VIDEO_ROCKCHIP_PREISP is not set
# CONFIG_VIDEO_MS41908 is not set
# CONFIG_VIDEO_MS41968 is not set
# end of Media SPI Adapters
# end of Media ancillary drivers

#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
CONFIG_DRM=y
CONFIG_DRM_MIPI_DBI=m
CONFIG_DRM_EDID=y
# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_DEBUG_MM is not set
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
CONFIG_DRM_LOAD_EDID_FIRMWARE=y
CONFIG_DRM_DP=y
CONFIG_DRM_DP_AUX_BUS=m
CONFIG_DRM_DISPLAY_HELPER=y
CONFIG_DRM_DISPLAY_DP_HELPER=y
CONFIG_DRM_DISPLAY_HDCP_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
CONFIG_DRM_DP_AUX_CHARDEV=y
CONFIG_DRM_DP_CEC=y
CONFIG_DRM_TTM=m
CONFIG_DRM_EXEC=m
CONFIG_DRM_GPUVM=m
CONFIG_DRM_TTM_HELPER=m
CONFIG_DRM_GEM_DMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=m
CONFIG_DRM_SCHED=m

#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips

#
# ARM devices
#
# CONFIG_DRM_HDLCD is not set
# CONFIG_DRM_MALI_DISPLAY is not set
# CONFIG_DRM_KOMEDA is not set
# end of ARM devices

# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
CONFIG_DRM_ROCKCHIP=y
# CONFIG_ROCKCHIP_DRM_DEBUG is not set
CONFIG_ROCKCHIP_DRM_DIRECT_SHOW=y
# CONFIG_ROCKCHIP_DRM_SELF_TEST is not set
CONFIG_ROCKCHIP_VOP=y
CONFIG_ROCKCHIP_VOP2=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DIMMING_PANEL=y
CONFIG_ROCKCHIP_DRM_TVE=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI2=y
CONFIG_ROCKCHIP_DW_DP=y
CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_ROCKCHIP_LVDS=y
CONFIG_ROCKCHIP_PANEL_NOTIFIER=y
CONFIG_ROCKCHIP_RGB=y
CONFIG_ROCKCHIP_RK3066_HDMI=y
# CONFIG_ROCKCHIP_VCONN is not set
# CONFIG_DRM_ROCKCHIP_VKMS is not set
CONFIG_ROCKCHIP_DW_HDCP2=y
# CONFIG_ROCKCHIP_DP_MST_AUX_CLIENT is not set
CONFIG_DRM_ROCKCHIP_RK618=m
# CONFIG_DRM_VMWGFX is not set
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_USE_LVDS is not set
# CONFIG_DRM_RCAR_USE_MIPI_DSI is not set
CONFIG_DRM_QXL=m
CONFIG_DRM_VIRTIO_GPU=m
CONFIG_DRM_PANEL=y

#
# Display Panels
#
CONFIG_DRM_PANEL_ABT_Y030XX067A=m
CONFIG_DRM_PANEL_ARM_VERSATILE=m
CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
CONFIG_DRM_PANEL_DSI_CM=m
CONFIG_DRM_PANEL_LVDS=m
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_EDP=m
CONFIG_DRM_PANEL_EBBG_FT8719=m
CONFIG_DRM_PANEL_ELIDA_KD35T133=m
CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
CONFIG_DRM_PANEL_ILITEK_IL9322=m
CONFIG_DRM_PANEL_ILITEK_ILI9341=m
CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=m
CONFIG_DRM_PANEL_JDI_LT070ME05000=m
CONFIG_DRM_PANEL_JDI_R63452=m
CONFIG_DRM_PANEL_KHADAS_TS050=m
CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
CONFIG_DRM_PANEL_LG_LB035Q02=m
CONFIG_DRM_PANEL_LG_LG4573=m
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
CONFIG_DRM_PANEL_NOVATEK_NT35510=m
CONFIG_DRM_PANEL_NOVATEK_NT35560=m
CONFIG_DRM_PANEL_NOVATEK_NT35950=m
CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
CONFIG_DRM_PANEL_NOVATEK_NT39016=m
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
CONFIG_DRM_PANEL_MAXIM_MAX96752F=m
CONFIG_DRM_PANEL_MAXIM_MAX96772=m
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
CONFIG_DRM_PANEL_RADXA_DISPLAY_8HD=m
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
CONFIG_DRM_PANEL_RASPITS_TC358762=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
CONFIG_DRM_PANEL_RONBO_RB070D30=m
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
CONFIG_DRM_PANEL_TDO_TL070WSH30=m
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
CONFIG_DRM_PANEL_TPO_TPG110=m
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
CONFIG_DRM_PANEL_VISIONOX_RM69299=m
CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
# CONFIG_DRM_PANEL_INNOLUX_AFJ101_BA2131 is not set
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CHIPONE_ICN6211 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
CONFIG_DRM_DISPLAY_CONNECTOR=m
# CONFIG_DRM_ITE_IT6161 is not set
# CONFIG_DRM_ITE_IT6505 is not set
# CONFIG_DRM_LONTIUM_LT8912B is not set
# CONFIG_DRM_LONTIUM_LT9211 is not set
CONFIG_DRM_LONTIUM_LT9611=m
CONFIG_DRM_LONTIUM_LT9611UXC=m
# CONFIG_DRM_ITE_IT66121 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MAXIM_MAX96745 is not set
# CONFIG_DRM_MAXIM_MAX96755F is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
CONFIG_DRM_RK630_TVE=m
CONFIG_DRM_RK1000_TVE=m
# CONFIG_DRM_ROHM_BU18XL82 is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_DLPC3433 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI83 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
CONFIG_DRM_ANALOGIX_DP=y
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=y
# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
# CONFIG_DRM_DW_HDMI_CEC is not set
CONFIG_DRM_DW_MIPI_DSI=y
# end of Display Interface Bridges

# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
# CONFIG_DRM_LOGICVC is not set
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_BOCHS is not set
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_GM12U320 is not set
# CONFIG_DRM_PANEL_MIPI_DBI is not set
# CONFIG_DRM_SIMPLEDRM is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9163 is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_DRM_PL111 is not set
CONFIG_DRM_LIMA=m
CONFIG_DRM_PANFROST=m
CONFIG_DRM_PANTHOR=m
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_GUD is not set
# CONFIG_DRM_SSD130X is not set
# CONFIG_DRM_LEGACY is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_DRM_NOMODESET=y
# CONFIG_MALI400 is not set
# CONFIG_MALI_MIDGARD is not set
# CONFIG_MALI_KUTF is not set
# CONFIG_MALI_BIFROST is not set
# CONFIG_MALI_VALHALL is not set

#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_BACKLIGHT=m
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
CONFIG_FB_ARMCLCD=m
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
CONFIG_FB_UVESA=m
# CONFIG_FB_EFI is not set
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
CONFIG_FB_SIMPLE=y
# CONFIG_FB_SSD1307 is not set
# CONFIG_FB_SM712 is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_L4F00242T03 is not set
# CONFIG_LCD_LMS283GF05 is not set
# CONFIG_LCD_LTV350QV is not set
# CONFIG_LCD_ILI922X is not set
# CONFIG_LCD_ILI9320 is not set
# CONFIG_LCD_TDO24M is not set
# CONFIG_LCD_VGG2432A4 is not set
# CONFIG_LCD_PLATFORM is not set
# CONFIG_LCD_AMS369FG06 is not set
# CONFIG_LCD_LMS501KF03 is not set
# CONFIG_LCD_HX8357 is not set
# CONFIG_LCD_OTM3225A is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_KTD253 is not set
CONFIG_BACKLIGHT_PWM=m
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
CONFIG_BACKLIGHT_GPIO=m
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
CONFIG_BACKLIGHT_LED=m
# end of Backlight & LCD device support

#
# Rockchip Misc Video driver
#

#
# RGA
#
# CONFIG_ROCKCHIP_RGA is not set
# end of RGA

CONFIG_ROCKCHIP_MULTI_RGA=y
CONFIG_ROCKCHIP_RGA_ASYNC=y
CONFIG_ROCKCHIP_RGA_PROC_FS=y
CONFIG_ROCKCHIP_RGA_DEBUG_FS=y
CONFIG_ROCKCHIP_RGA_DEBUGGER=y
# CONFIG_ROCKCHIP_RGA_GENPOOL is not set
CONFIG_ROCKCHIP_RVE=y
CONFIG_ROCKCHIP_RVE_PROC_FS=y
CONFIG_ROCKCHIP_RVE_DEBUG_FS=y
CONFIG_ROCKCHIP_RVE_DEBUGGER=y

#
# IEP
#
CONFIG_IEP=y
# end of IEP

CONFIG_ROCKCHIP_MPP_SERVICE=y
CONFIG_ROCKCHIP_MPP_PROC_FS=y
CONFIG_ROCKCHIP_MPP_RKVDEC=y
CONFIG_ROCKCHIP_MPP_RKVDEC2=y
CONFIG_ROCKCHIP_MPP_RKVENC=y
CONFIG_ROCKCHIP_MPP_RKVENC2=y
CONFIG_ROCKCHIP_MPP_VDPU1=y
CONFIG_ROCKCHIP_MPP_VEPU1=y
CONFIG_ROCKCHIP_MPP_VDPU2=y
CONFIG_ROCKCHIP_MPP_VEPU2=y
CONFIG_ROCKCHIP_MPP_IEP2=y
CONFIG_ROCKCHIP_MPP_JPGDEC=y
CONFIG_ROCKCHIP_MPP_JPGENC=y
CONFIG_ROCKCHIP_MPP_AV1DEC=y
CONFIG_ROCKCHIP_MPP_VDPP=y
CONFIG_ROCKCHIP_MPP_OSAL=y
# CONFIG_ROCKCHIP_DVBM is not set
# CONFIG_VIDEO_REVERSE_IMAGE is not set

#
# Rockchip video tunnel support
#
CONFIG_ROCKCHIP_VIDEO_TUNNEL=m
# end of Rockchip video tunnel support
# end of Rockchip Misc Video driver

CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
# end of Console display driver support

CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
# end of Graphics support

CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=m
CONFIG_SND_SEQ_DEVICE=y
CONFIG_SND_RAWMIDI=y
CONFIG_SND_COMPRESS_OFFLOAD=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_OSSEMUL is not set
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_VERBOSE_PRINTK is not set
CONFIG_SND_CTL_FAST_LOOKUP=y
# CONFIG_SND_DEBUG is not set
# CONFIG_SND_CTL_INPUT_VALIDATION is not set
CONFIG_SND_VMASTER=y
CONFIG_SND_SEQUENCER=m
CONFIG_SND_SEQ_DUMMY=m
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
CONFIG_SND_SEQ_MIDI_EVENT=m
CONFIG_SND_SEQ_MIDI=m
CONFIG_SND_SEQ_VIRMIDI=m
CONFIG_SND_MPU401_UART=m
CONFIG_SND_AC97_CODEC=m
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
CONFIG_SND_VIRMIDI=m
CONFIG_SND_MTPAV=m
CONFIG_SND_SERIAL_U16550=m
# CONFIG_SND_SERIAL_GENERIC is not set
CONFIG_SND_MPU401=m
# CONFIG_SND_AC97_POWER_SAVE is not set
# CONFIG_SND_PCI is not set

#
# HD-Audio
#
CONFIG_SND_HDA=m
# CONFIG_SND_HDA_HWDEP is not set
# CONFIG_SND_HDA_RECONFIG is not set
# CONFIG_SND_HDA_INPUT_BEEP is not set
# CONFIG_SND_HDA_PATCH_LOADER is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
# CONFIG_SND_HDA_CODEC_REALTEK is not set
# CONFIG_SND_HDA_CODEC_ANALOG is not set
# CONFIG_SND_HDA_CODEC_SIGMATEL is not set
# CONFIG_SND_HDA_CODEC_VIA is not set
# CONFIG_SND_HDA_CODEC_HDMI is not set
# CONFIG_SND_HDA_CODEC_CIRRUS is not set
# CONFIG_SND_HDA_CODEC_CS8409 is not set
# CONFIG_SND_HDA_CODEC_CONEXANT is not set
# CONFIG_SND_HDA_CODEC_CA0110 is not set
# CONFIG_SND_HDA_CODEC_CA0132 is not set
# CONFIG_SND_HDA_CODEC_CMEDIA is not set
# CONFIG_SND_HDA_CODEC_SI3054 is not set
# CONFIG_SND_HDA_GENERIC is not set
CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
# end of HD-Audio

CONFIG_SND_HDA_CORE=m
CONFIG_SND_HDA_EXT_CORE=m
CONFIG_SND_HDA_PREALLOC_SIZE=64
# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
CONFIG_SND_BCD2000=m
CONFIG_SND_USB_LINE6=m
CONFIG_SND_USB_POD=m
CONFIG_SND_USB_PODHD=m
CONFIG_SND_USB_TONEPORT=m
CONFIG_SND_USB_VARIAX=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
# CONFIG_SND_SOC_DYNAMIC_DMA_CHAN is not set
CONFIG_SND_SOC_COMPRESS=y
# CONFIG_SND_SOC_ADI is not set
# CONFIG_SND_SOC_AMD_ACP is not set
# CONFIG_SND_AMD_ACP_CONFIG is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
CONFIG_SND_DESIGNWARE_I2S=m
# CONFIG_SND_DESIGNWARE_PCM is not set

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
# CONFIG_SND_SOC_FSL_SAI is not set
# CONFIG_SND_SOC_FSL_AUDMIX is not set
# CONFIG_SND_SOC_FSL_SSI is not set
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
# CONFIG_SND_SOC_FSL_MICFIL is not set
# CONFIG_SND_SOC_FSL_XCVR is not set
# CONFIG_SND_SOC_FSL_RPMSG is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs

# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set
CONFIG_SND_SOC_ROCKCHIP=y
CONFIG_SND_SOC_ROCKCHIP_ASRC=y
CONFIG_SND_SOC_ROCKCHIP_DLP=y
CONFIG_SND_SOC_ROCKCHIP_DLP_PCM=y
CONFIG_SND_SOC_ROCKCHIP_DUMMY_DAI=y
CONFIG_SND_SOC_ROCKCHIP_I2S=y
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES=y
CONFIG_SND_SOC_ROCKCHIP_MULTI_DAIS=y
CONFIG_SND_SOC_ROCKCHIP_PDM=y
CONFIG_SND_SOC_ROCKCHIP_PDM_V2=y
CONFIG_SND_SOC_ROCKCHIP_SAI=y
CONFIG_SND_SOC_ROCKCHIP_SAI_VERBOSE=y
CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
CONFIG_SND_SOC_ROCKCHIP_SPDIFRX=y
CONFIG_SND_SOC_ROCKCHIP_TRCM=y
CONFIG_SND_SOC_ROCKCHIP_VAD=y
CONFIG_SND_SOC_ROCKCHIP_MAX98090=y
CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
CONFIG_SND_SOC_ROCKCHIP_RT5645=y
CONFIG_SND_SOC_ROCKCHIP_HDMI=y
CONFIG_SND_SOC_RK3288_HDMI_ANALOG=y
CONFIG_SND_SOC_RK3399_GRU_SOUND=y
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set

#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support

# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# CONFIG_SND_SOC_XTFPGA_I2S is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
CONFIG_SND_SOC_WM_ADSP=m
CONFIG_SND_SOC_AC97_CODEC=m
CONFIG_SND_SOC_ADAU_UTILS=m
CONFIG_SND_SOC_ADAU1372=m
CONFIG_SND_SOC_ADAU1372_I2C=m
CONFIG_SND_SOC_ADAU1372_SPI=m
CONFIG_SND_SOC_ADAU1701=m
CONFIG_SND_SOC_ADAU17X1=m
CONFIG_SND_SOC_ADAU1761=m
CONFIG_SND_SOC_ADAU1761_I2C=m
CONFIG_SND_SOC_ADAU1761_SPI=m
CONFIG_SND_SOC_ADAU7002=m
CONFIG_SND_SOC_ADAU7118=m
CONFIG_SND_SOC_ADAU7118_HW=m
CONFIG_SND_SOC_ADAU7118_I2C=m
CONFIG_SND_SOC_AK4104=m
CONFIG_SND_SOC_AK4118=m
CONFIG_SND_SOC_AK4375=m
CONFIG_SND_SOC_AK4458=m
CONFIG_SND_SOC_AK4554=m
CONFIG_SND_SOC_AK4613=m
CONFIG_SND_SOC_AK4642=m
CONFIG_SND_SOC_AK5386=m
CONFIG_SND_SOC_AK5558=m
CONFIG_SND_SOC_ALC5623=m
CONFIG_SND_SOC_AW8738=m
CONFIG_SND_SOC_BD28623=m
CONFIG_SND_SOC_BT_SCO=m
CONFIG_SND_SOC_CS35L32=m
CONFIG_SND_SOC_CS35L33=m
CONFIG_SND_SOC_CS35L34=m
CONFIG_SND_SOC_CS35L35=m
CONFIG_SND_SOC_CS35L36=m
CONFIG_SND_SOC_CS35L41_LIB=m
CONFIG_SND_SOC_CS35L41=m
CONFIG_SND_SOC_CS35L41_SPI=m
CONFIG_SND_SOC_CS35L41_I2C=m
CONFIG_SND_SOC_CS35L45_TABLES=m
CONFIG_SND_SOC_CS35L45=m
CONFIG_SND_SOC_CS35L45_SPI=m
CONFIG_SND_SOC_CS35L45_I2C=m
CONFIG_SND_SOC_CS42L42_CORE=m
CONFIG_SND_SOC_CS42L42=m
CONFIG_SND_SOC_CS42L51=m
CONFIG_SND_SOC_CS42L51_I2C=m
CONFIG_SND_SOC_CS42L52=m
CONFIG_SND_SOC_CS42L56=m
CONFIG_SND_SOC_CS42L73=m
CONFIG_SND_SOC_CS42L83=m
CONFIG_SND_SOC_CS4234=m
CONFIG_SND_SOC_CS4265=m
CONFIG_SND_SOC_CS4270=m
CONFIG_SND_SOC_CS4271=m
CONFIG_SND_SOC_CS4271_I2C=m
CONFIG_SND_SOC_CS4271_SPI=m
CONFIG_SND_SOC_CS42XX8=m
CONFIG_SND_SOC_CS42XX8_I2C=m
CONFIG_SND_SOC_CS43130=m
CONFIG_SND_SOC_CS4341=m
CONFIG_SND_SOC_CS4349=m
CONFIG_SND_SOC_CS53L30=m
CONFIG_SND_SOC_CX2072X=m
CONFIG_SND_SOC_DA7213=m
CONFIG_SND_SOC_DA7219=y
CONFIG_SND_SOC_DMIC=y
CONFIG_SND_SOC_DUMMY_CODEC=y
CONFIG_SND_SOC_HDMI_CODEC=y
CONFIG_SND_SOC_ES7134=m
CONFIG_SND_SOC_ES7202=m
CONFIG_SND_SOC_ES7202_MIC_MAX_CHANNELS=2
CONFIG_SND_SOC_ES7202_I2C_BUS=1
CONFIG_SND_SOC_ES7210=m
CONFIG_SND_SOC_ES7241=m
CONFIG_SND_SOC_ES7243E=m
CONFIG_SND_SOC_ES8311=m
CONFIG_SND_SOC_ES8316=m
CONFIG_SND_SOC_ES8323=m
CONFIG_SND_SOC_ES8326=m
CONFIG_SND_SOC_ES8328=y
CONFIG_SND_SOC_ES8328_I2C=y
CONFIG_SND_SOC_ES8328_SPI=y
CONFIG_SND_SOC_ES8389=m
CONFIG_SND_SOC_ES8396=m
CONFIG_SND_SOC_GTM601=m
CONFIG_SND_SOC_HDA=m
CONFIG_SND_SOC_ICS43432=m
CONFIG_SND_SOC_INNO_RK3036=m
CONFIG_SND_SOC_MAX98088=m
CONFIG_SND_SOC_MAX98090=y
CONFIG_SND_SOC_MAX98357A=y
CONFIG_SND_SOC_MAX98504=m
CONFIG_SND_SOC_MAX9867=m
CONFIG_SND_SOC_MAX98927=m
CONFIG_SND_SOC_MAX98520=m
CONFIG_SND_SOC_MAX98373=m
CONFIG_SND_SOC_MAX98373_I2C=m
CONFIG_SND_SOC_MAX98390=m
CONFIG_SND_SOC_MAX98396=m
CONFIG_SND_SOC_MAX9860=m
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
CONFIG_SND_SOC_PCM1681=m
CONFIG_SND_SOC_PCM1789=m
CONFIG_SND_SOC_PCM1789_I2C=m
CONFIG_SND_SOC_PCM179X=m
CONFIG_SND_SOC_PCM179X_I2C=m
CONFIG_SND_SOC_PCM179X_SPI=m
CONFIG_SND_SOC_PCM186X=m
CONFIG_SND_SOC_PCM186X_I2C=m
CONFIG_SND_SOC_PCM186X_SPI=m
CONFIG_SND_SOC_PCM3060=m
CONFIG_SND_SOC_PCM3060_I2C=m
CONFIG_SND_SOC_PCM3060_SPI=m
CONFIG_SND_SOC_PCM3168A=m
CONFIG_SND_SOC_PCM3168A_I2C=m
CONFIG_SND_SOC_PCM3168A_SPI=m
CONFIG_SND_SOC_PCM5102A=m
CONFIG_SND_SOC_PCM512x=m
CONFIG_SND_SOC_PCM512x_I2C=m
CONFIG_SND_SOC_PCM512x_SPI=m
CONFIG_SND_SOC_RK1000=y
CONFIG_SND_SOC_RK312X=y
CONFIG_SND_SOC_RK3228=y
CONFIG_SND_SOC_RK3308=y
CONFIG_SND_SOC_RK3328=y
CONFIG_SND_SOC_RK3506=y
CONFIG_SND_SOC_RK3528=y
CONFIG_SND_SOC_RK730=y
CONFIG_SND_SOC_RK817=y
CONFIG_SND_SOC_RK_CODEC_DIGITAL=y
CONFIG_SND_SOC_RK_DSM=y
CONFIG_SND_SOC_RL6231=y
CONFIG_SND_SOC_ROCKCHIP_SPI_CODEC=y
CONFIG_SND_SOC_RT5514=y
CONFIG_SND_SOC_RT5514_SPI=y
CONFIG_SND_SOC_RT5616=m
CONFIG_SND_SOC_RT5631=m
CONFIG_SND_SOC_RT5640=m
CONFIG_SND_SOC_RT5645=y
CONFIG_SND_SOC_RT5651=m
CONFIG_SND_SOC_RT5659=m
CONFIG_SND_SOC_RT9120=m
CONFIG_SND_SOC_RV1106=y
CONFIG_SND_SOC_SGTL5000=m
CONFIG_SND_SOC_SIGMADSP=m
CONFIG_SND_SOC_SIGMADSP_I2C=m
CONFIG_SND_SOC_SIGMADSP_REGMAP=m
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
CONFIG_SND_SOC_SIMPLE_MUX=y
CONFIG_SND_SOC_SPDIF=y
CONFIG_SND_SOC_SRC4XXX_I2C=m
CONFIG_SND_SOC_SRC4XXX=m
CONFIG_SND_SOC_SSM2305=m
CONFIG_SND_SOC_SSM2518=m
CONFIG_SND_SOC_SSM2602=m
CONFIG_SND_SOC_SSM2602_SPI=m
CONFIG_SND_SOC_SSM2602_I2C=m
CONFIG_SND_SOC_SSM4567=m
CONFIG_SND_SOC_STA32X=m
CONFIG_SND_SOC_STA350=m
CONFIG_SND_SOC_STI_SAS=m
CONFIG_SND_SOC_TAS2552=m
CONFIG_SND_SOC_TAS2562=m
CONFIG_SND_SOC_TAS2764=m
CONFIG_SND_SOC_TAS2770=m
CONFIG_SND_SOC_TAS2780=m
CONFIG_SND_SOC_TAS5086=m
CONFIG_SND_SOC_TAS571X=m
CONFIG_SND_SOC_TAS5720=m
CONFIG_SND_SOC_TAS5805M=m
CONFIG_SND_SOC_TAS6424=m
CONFIG_SND_SOC_TDA7419=m
CONFIG_SND_SOC_TDA7803=m
CONFIG_SND_SOC_TFA9879=m
CONFIG_SND_SOC_TFA989X=m
CONFIG_SND_SOC_TLV320ADC3XXX=m
CONFIG_SND_SOC_TLV320AIC23=m
CONFIG_SND_SOC_TLV320AIC23_I2C=m
CONFIG_SND_SOC_TLV320AIC23_SPI=m
CONFIG_SND_SOC_TLV320AIC31XX=m
CONFIG_SND_SOC_TLV320AIC32X4=m
CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
CONFIG_SND_SOC_TLV320AIC3X=m
CONFIG_SND_SOC_TLV320AIC3X_I2C=m
CONFIG_SND_SOC_TLV320AIC3X_SPI=m
CONFIG_SND_SOC_TLV320ADCX140=m
CONFIG_SND_SOC_TS3A227E=y
CONFIG_SND_SOC_TSCS42XX=m
CONFIG_SND_SOC_TSCS454=m
CONFIG_SND_SOC_UDA1334=m
CONFIG_SND_SOC_WM8510=m
CONFIG_SND_SOC_WM8523=m
CONFIG_SND_SOC_WM8524=m
CONFIG_SND_SOC_WM8580=m
CONFIG_SND_SOC_WM8711=m
CONFIG_SND_SOC_WM8728=m
CONFIG_SND_SOC_WM8731=m
CONFIG_SND_SOC_WM8731_I2C=m
CONFIG_SND_SOC_WM8731_SPI=m
CONFIG_SND_SOC_WM8737=m
CONFIG_SND_SOC_WM8741=m
CONFIG_SND_SOC_WM8750=m
CONFIG_SND_SOC_WM8753=m
CONFIG_SND_SOC_WM8770=m
CONFIG_SND_SOC_WM8776=m
CONFIG_SND_SOC_WM8782=m
CONFIG_SND_SOC_WM8804=m
CONFIG_SND_SOC_WM8804_I2C=m
CONFIG_SND_SOC_WM8804_SPI=m
CONFIG_SND_SOC_WM8903=m
CONFIG_SND_SOC_WM8904=m
CONFIG_SND_SOC_WM8940=m
CONFIG_SND_SOC_WM8960=m
CONFIG_SND_SOC_WM8962=m
CONFIG_SND_SOC_WM8974=m
CONFIG_SND_SOC_WM8978=m
CONFIG_SND_SOC_WM8985=m
CONFIG_SND_SOC_ZL38060=m
CONFIG_SND_SOC_MAX9759=m
CONFIG_SND_SOC_MT6351=m
CONFIG_SND_SOC_MT6358=m
CONFIG_SND_SOC_MT6660=m
CONFIG_SND_SOC_NAU8315=m
CONFIG_SND_SOC_NAU8540=m
CONFIG_SND_SOC_NAU8810=m
CONFIG_SND_SOC_NAU8821=m
CONFIG_SND_SOC_NAU8822=m
CONFIG_SND_SOC_NAU8824=m
CONFIG_SND_SOC_TPA6130A2=m
CONFIG_SND_SOC_LPASS_MACRO_COMMON=m
CONFIG_SND_SOC_LPASS_WSA_MACRO=m
CONFIG_SND_SOC_LPASS_VA_MACRO=m
CONFIG_SND_SOC_LPASS_RX_MACRO=m
CONFIG_SND_SOC_LPASS_TX_MACRO=m
CONFIG_SND_SOC_AW87XXX=m
CONFIG_SND_SOC_AW882XX=m
CONFIG_SND_SOC_AW883XX=m
CONFIG_SND_SOC_IT6621=m
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD2=y
CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=y
# CONFIG_SND_TEST_COMPONENT is not set
CONFIG_SND_VIRTIO=y
CONFIG_AC97_BUS=y

#
# HID support
#
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=y
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
CONFIG_HID_A4TECH=m
CONFIG_HID_ACCUTOUCH=m
CONFIG_HID_ACRUX=m
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=m
CONFIG_HID_APPLEIR=m
CONFIG_HID_ASUS=m
CONFIG_HID_AUREAL=m
CONFIG_HID_BELKIN=m
CONFIG_HID_BETOP_FF=m
CONFIG_HID_BIGBEN_FF=m
CONFIG_HID_CHERRY=m
CONFIG_HID_CHICONY=m
CONFIG_HID_CORSAIR=m
CONFIG_HID_COUGAR=m
CONFIG_HID_MACALLY=m
CONFIG_HID_PRODIKEYS=m
CONFIG_HID_CMEDIA=m
CONFIG_HID_CP2112=m
CONFIG_HID_CREATIVE_SB0540=m
CONFIG_HID_CYPRESS=m
CONFIG_HID_DRAGONRISE=m
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=m
CONFIG_HID_ELAN=m
CONFIG_HID_ELECOM=m
CONFIG_HID_ELO=m
CONFIG_HID_EZKEY=m
CONFIG_HID_FT260=m
CONFIG_HID_GEMBIRD=m
CONFIG_HID_GFRM=m
CONFIG_HID_GLORIOUS=m
CONFIG_HID_HOLTEK=m
CONFIG_HOLTEK_FF=y
CONFIG_HID_VIVALDI_COMMON=m
CONFIG_HID_VIVALDI=m
CONFIG_HID_GT683R=m
CONFIG_HID_KEYTOUCH=m
CONFIG_HID_KYE=m
CONFIG_HID_UCLOGIC=m
CONFIG_HID_WALTOP=m
CONFIG_HID_VIEWSONIC=m
CONFIG_HID_VRC2=m
CONFIG_HID_XIAOMI=m
CONFIG_HID_GYRATION=m
CONFIG_HID_ICADE=m
CONFIG_HID_ITE=m
CONFIG_HID_JABRA=m
CONFIG_HID_TWINHAN=m
CONFIG_HID_KENSINGTON=m
CONFIG_HID_LCPOWER=m
CONFIG_HID_LED=m
CONFIG_HID_LENOVO=m
CONFIG_HID_LETSKETCH=m
CONFIG_HID_LOGITECH=m
CONFIG_HID_LOGITECH_DJ=m
CONFIG_HID_LOGITECH_HIDPP=m
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
CONFIG_HID_MAGICMOUSE=m
CONFIG_HID_MALTRON=m
CONFIG_HID_MAYFLASH=m
CONFIG_HID_MEGAWORLD_FF=m
CONFIG_HID_REDRAGON=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
CONFIG_HID_MULTITOUCH=m
CONFIG_HID_NINTENDO=m
# CONFIG_NINTENDO_FF is not set
CONFIG_HID_NTI=m
CONFIG_HID_NTRIG=m
CONFIG_HID_ORTEK=m
CONFIG_HID_PANTHERLORD=m
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PENMOUNT=m
CONFIG_HID_PETALYNX=m
CONFIG_HID_PICOLCD=m
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
CONFIG_HID_PICOLCD_LCD=y
CONFIG_HID_PICOLCD_LEDS=y
CONFIG_HID_PICOLCD_CIR=y
CONFIG_HID_PLANTRONICS=m
CONFIG_HID_PLAYSTATION=m
CONFIG_PLAYSTATION_FF=y
CONFIG_HID_PXRC=m
CONFIG_HID_RAZER=m
CONFIG_HID_PRIMAX=m
CONFIG_HID_RETRODE=m
CONFIG_HID_ROCCAT=m
CONFIG_HID_SAITEK=m
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SEMITEK=m
CONFIG_HID_SIGMAMICRO=m
CONFIG_HID_SONY=m
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=m
CONFIG_HID_STEAM=m
CONFIG_HID_STEELSERIES=m
CONFIG_HID_SUNPLUS=m
CONFIG_HID_RMI=m
CONFIG_HID_GREENASIA=m
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=m
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TIVO=m
CONFIG_HID_TOPSEED=m
CONFIG_HID_TOPRE=m
CONFIG_HID_THINGM=m
CONFIG_HID_THRUSTMASTER=m
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_UDRAW_PS3=m
CONFIG_HID_U2FZERO=m
CONFIG_HID_WACOM=m
CONFIG_HID_WIIMOTE=m
CONFIG_HID_XINMO=m
CONFIG_HID_ZEROPLUS=m
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=m
CONFIG_HID_SENSOR_HUB=m
CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
CONFIG_HID_ALPS=m
CONFIG_HID_MCP2221=m
# end of Special HID drivers

#
# USB HID support
#
CONFIG_USB_HID=y
# CONFIG_HID_PID is not set
CONFIG_USB_HIDDEV=y
# end of USB HID support

#
# I2C HID support
#
CONFIG_I2C_HID_ACPI=m
CONFIG_I2C_HID_OF=m
CONFIG_I2C_HID_OF_ELAN=m
CONFIG_I2C_HID_OF_GOODIX=m
# end of I2C HID support

CONFIG_I2C_HID_CORE=m
# end of HID support

CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_LED_TRIG=y
CONFIG_USB_ULPI_BUS=m
CONFIG_USB_CONN_GPIO=m
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
CONFIG_USB_OTG_FSM=y
CONFIG_USB_LEDS_TRIGGER_USBPORT=y
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=m

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=m
CONFIG_USB_XHCI_PCI_RENESAS=m
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_EHCI_FSL=m
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OXU210HP_HCD=m
CONFIG_USB_ISP116X_HCD=m
CONFIG_USB_FOTG210_HCD=m
CONFIG_USB_MAX3421_HCD=m
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PCI=m
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_UHCI_HCD=m
CONFIG_USB_U132_HCD=m
CONFIG_USB_SL811_HCD=m
# CONFIG_USB_SL811_HCD_ISO is not set
CONFIG_USB_R8A66597_HCD=m
CONFIG_USB_HCD_BCMA=m
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=y
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=m
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
CONFIG_USB_STORAGE_REALTEK=m
CONFIG_REALTEK_AUTOPM=y
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_FREECOM=m
CONFIG_USB_STORAGE_ISD200=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_STORAGE_ALAUDA=m
CONFIG_USB_STORAGE_ONETOUCH=m
CONFIG_USB_STORAGE_KARMA=m
CONFIG_USB_STORAGE_CYPRESS_ATACB=m
CONFIG_USB_STORAGE_ENE_UB6250=m
# CONFIG_USB_UAS is not set

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
CONFIG_USB_MICROTEK=m
CONFIG_USBIP_CORE=m
CONFIG_USBIP_VHCI_HCD=m
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=m
CONFIG_USBIP_VUDC=m
CONFIG_USBIP_DEBUG=y
# CONFIG_USB_CDNS_SUPPORT is not set
CONFIG_USB_MUSB_HDRC=m
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y

#
# Platform Glue Layer
#

#
# MUSB DMA mode
#
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y

#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=m
CONFIG_USB_DWC3_HAPS=m
CONFIG_USB_DWC3_OF_SIMPLE=m
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
CONFIG_USB_DWC2_PCI=m
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
CONFIG_USB_CHIPIDEA=m
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_CHIPIDEA_PCI=m
CONFIG_USB_CHIPIDEA_MSM=m
CONFIG_USB_CHIPIDEA_IMX=m
CONFIG_USB_CHIPIDEA_GENERIC=m
CONFIG_USB_CHIPIDEA_TEGRA=m
# CONFIG_USB_ISP1760 is not set

#
# USB port drivers
#
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=y
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=y
CONFIG_USB_SERIAL_CH348=y
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=y
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=y
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=m
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_F81232=m
CONFIG_USB_SERIAL_F8153X=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=m
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_METRO=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MXUPORT=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=y
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=m
CONFIG_USB_SERIAL_QUALCOMM=m
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
CONFIG_USB_SERIAL_SAFE_PADDED=y
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
CONFIG_USB_SERIAL_SYMBOL=m
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_WWAN=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=m
CONFIG_USB_SERIAL_XSENS_MT=m
CONFIG_USB_SERIAL_WISHBONE=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_SERIAL_QT2=m
CONFIG_USB_SERIAL_UPD78F0730=m
CONFIG_USB_SERIAL_XR=m
CONFIG_USB_SERIAL_DEBUG=m

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
CONFIG_USB_CYPRESS_CY7C63=m
CONFIG_USB_CYTHERM=m
CONFIG_USB_IDMOUSE=m
CONFIG_USB_FTDI_ELAN=m
CONFIG_USB_APPLEDISPLAY=m
CONFIG_APPLE_MFI_FASTCHARGE=m
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
CONFIG_USB_TEST=m
CONFIG_USB_EHSET_TEST_FIXTURE=m
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=y
CONFIG_USB_HUB_USB251XB=m
CONFIG_USB_HSIC_USB3503=m
CONFIG_USB_HSIC_USB4604=m
CONFIG_USB_LINK_LAYER_TEST=m
CONFIG_USB_CHAOSKEY=m
CONFIG_USB_ONBOARD_HUB=y

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=m
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_ULPI is not set
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
CONFIG_USB_GADGET_DEBUG_FILES=y
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
CONFIG_U_SERIAL_CONSOLE=y

#
# USB Peripheral Controller
#
# CONFIG_USB_FOTG210_UDC is not set
# CONFIG_USB_GR_UDC is not set
# CONFIG_USB_R8A66597 is not set
# CONFIG_USB_PXA27X is not set
# CONFIG_USB_MV_UDC is not set
# CONFIG_USB_MV_U3D is not set
CONFIG_USB_SNP_CORE=y
CONFIG_USB_SNP_UDC_PLAT=y
# CONFIG_USB_M66592 is not set
# CONFIG_USB_BDC_UDC is not set
# CONFIG_USB_AMD5536UDC is not set
# CONFIG_USB_NET2272 is not set
# CONFIG_USB_NET2280 is not set
# CONFIG_USB_GOKU is not set
# CONFIG_USB_EG20T is not set
# CONFIG_USB_GADGET_XILINX is not set
# CONFIG_USB_MAX3420_UDC is not set
# CONFIG_USB_DUMMY_HCD is not set
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_F_ACM=y
CONFIG_USB_F_SS_LB=y
CONFIG_USB_U_SERIAL=y
CONFIG_USB_U_ETHER=y
CONFIG_USB_U_AUDIO=y
CONFIG_USB_F_SERIAL=y
CONFIG_USB_F_OBEX=y
CONFIG_USB_F_NCM=y
CONFIG_USB_F_ECM=y
CONFIG_USB_F_EEM=y
CONFIG_USB_F_SUBSET=y
CONFIG_USB_F_RNDIS=y
CONFIG_USB_F_MASS_STORAGE=y
CONFIG_USB_F_FS=y
CONFIG_USB_F_UAC1=y
CONFIG_USB_F_UAC1_LEGACY=y
CONFIG_USB_F_UAC2=y
CONFIG_USB_F_UVC=y
CONFIG_USB_F_MIDI=y
CONFIG_USB_F_HID=y
CONFIG_USB_F_PRINTER=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_UEVENT=y
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_LB_SS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y

#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=m
# CONFIG_USB_ZERO_HNPTEST is not set
CONFIG_USB_AUDIO=m
# CONFIG_GADGET_UAC1 is not set
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
CONFIG_USB_FUNCTIONFS_ETH=y
CONFIG_USB_FUNCTIONFS_RNDIS=y
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_G_HID=m
CONFIG_USB_G_DBGP=m
# CONFIG_USB_G_DBGP_PRINTK is not set
CONFIG_USB_G_DBGP_SERIAL=y
CONFIG_USB_G_WEBCAM=m
CONFIG_USB_RAW_GADGET=m
# end of USB Gadget precomposed configurations

CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
CONFIG_TYPEC_ET7303=y
CONFIG_TYPEC_HUSB311=y
CONFIG_TYPEC_RT1711H=y
CONFIG_TYPEC_TCPCI_MAXIM=y
CONFIG_TYPEC_FUSB302=y
CONFIG_TYPEC_UCSI=m
CONFIG_UCSI_CCG=m
CONFIG_UCSI_ACPI=m
CONFIG_UCSI_STM32G0=m
CONFIG_TYPEC_TPS6598X=m
CONFIG_TYPEC_ANX7411=m
CONFIG_TYPEC_RT1719=m
CONFIG_TYPEC_HD3SS3220=m
CONFIG_TYPEC_STUSB160X=m
CONFIG_TYPEC_WUSB3801=m

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
CONFIG_TYPEC_MUX_FSA4480=m
CONFIG_TYPEC_MUX_PI3USB30532=m
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
CONFIG_TYPEC_DP_ALTMODE=y
# CONFIG_TYPEC_NVIDIA_ALTMODE is not set
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
# CONFIG_PWRSEQ_SD8787 is not set
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_SDIO_UART is not set
CONFIG_MMC_TEST=y

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_ARMMMCI is not set
CONFIG_MMC_SDHCI=y
# CONFIG_MMC_SDHCI_PCI is not set
# CONFIG_MMC_SDHCI_ACPI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
CONFIG_MMC_SDHCI_OF_AT91=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_MMC_SDHCI_CADENCE=y
# CONFIG_MMC_SDHCI_F_SDH30 is not set
# CONFIG_MMC_SDHCI_MILBEAUT is not set
CONFIG_MMC_TIFM_SD=m
CONFIG_MMC_SPI=m
# CONFIG_MMC_CB710 is not set
CONFIG_MMC_VIA_SDMMC=m
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
# CONFIG_MMC_DW_BLUEFIELD is not set
# CONFIG_MMC_DW_EXYNOS is not set
# CONFIG_MMC_DW_HI3798CV200 is not set
# CONFIG_MMC_DW_K3 is not set
# CONFIG_MMC_DW_PCI is not set
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_VUB300=m
CONFIG_MMC_USHC=m
CONFIG_MMC_USDHI6ROL0=m
CONFIG_MMC_REALTEK_PCI=m
CONFIG_MMC_REALTEK_USB=m
CONFIG_MMC_CQHCI=y
CONFIG_MMC_HSQ=y
CONFIG_MMC_TOSHIBA_PCI=m
CONFIG_MMC_MTK=m
# CONFIG_MMC_SDHCI_XENON is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
CONFIG_LEDS_CLASS_MULTICOLOR=y
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y

#
# LED drivers
#
CONFIG_LEDS_AN30259A=m
CONFIG_LEDS_AW2013=m
CONFIG_LEDS_BCM6328=m
CONFIG_LEDS_BCM6358=m
CONFIG_LEDS_CR0014114=m
CONFIG_LEDS_EL15203000=m
CONFIG_LEDS_LM3530=m
CONFIG_LEDS_LM3532=m
CONFIG_LEDS_LM3642=m
CONFIG_LEDS_LM3692X=y
CONFIG_LEDS_PCA9532=m
CONFIG_LEDS_PCA9532_GPIO=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=m
CONFIG_LEDS_LP3952=m
CONFIG_LEDS_LP50XX=m
CONFIG_LEDS_LP55XX_COMMON=m
CONFIG_LEDS_LP5521=m
CONFIG_LEDS_LP5523=m
CONFIG_LEDS_LP5562=m
CONFIG_LEDS_LP8501=m
CONFIG_LEDS_LP8860=m
CONFIG_LEDS_PCA955X=m
CONFIG_LEDS_PCA955X_GPIO=y
CONFIG_LEDS_PCA963X=m
CONFIG_LEDS_DAC124S085=m
CONFIG_LEDS_PWM=y
CONFIG_LEDS_REGULATOR=y
CONFIG_LEDS_BD2802=m
CONFIG_LEDS_LT3593=m
CONFIG_LEDS_TCA6507=m
CONFIG_LEDS_TLC591XX=m
CONFIG_LEDS_LM355x=m
CONFIG_LEDS_IS31FL319X=m
CONFIG_LEDS_IS31FL32XX=m
CONFIG_LEDS_RGB13H=m

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=m
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_MLXREG=m
CONFIG_LEDS_USER=y
CONFIG_LEDS_SPI_BYTE=m
CONFIG_LEDS_TI_LMU_COMMON=m
CONFIG_LEDS_LM3697=m

#
# Flash and Torch LED drivers
#
CONFIG_LEDS_AAT1290=m
CONFIG_LEDS_AS3645A=m
CONFIG_LEDS_KTD2692=m
CONFIG_LEDS_LM3601X=y
CONFIG_LEDS_RT4505=m
CONFIG_LEDS_RT8515=m
CONFIG_LEDS_SGM3140=y

#
# RGB LED drivers
#
CONFIG_LEDS_PWM_MULTICOLOR=m

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_ACTIVITY=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=y
CONFIG_LEDS_TRIGGER_PATTERN=y
CONFIG_LEDS_TRIGGER_AUDIO=y
CONFIG_LEDS_TRIGGER_TTY=y

#
# Simple LED drivers
#
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
CONFIG_RTC_DRV_TEST=m

#
# I2C RTC drivers
#
CONFIG_RTC_DRV_ABB5ZES3=m
CONFIG_RTC_DRV_ABEOZ9=m
CONFIG_RTC_DRV_ABX80X=m
CONFIG_RTC_DRV_DS1307=m
CONFIG_RTC_DRV_DS1307_CENTURY=y
CONFIG_RTC_DRV_DS1374=m
CONFIG_RTC_DRV_DS1374_WDT=y
CONFIG_RTC_DRV_DS1672=m
CONFIG_RTC_DRV_HYM8563=y
CONFIG_RTC_DRV_MAX6900=m
CONFIG_RTC_DRV_NCT3018Y=m
# CONFIG_RTC_DRV_RK630 is not set
CONFIG_RTC_DRV_RK808=m
CONFIG_RTC_DRV_ROCKCHIP=m
CONFIG_RTC_DRV_RS5C372=m
CONFIG_RTC_DRV_ISL1208=m
CONFIG_RTC_DRV_ISL12022=m
CONFIG_RTC_DRV_ISL12026=m
CONFIG_RTC_DRV_X1205=m
CONFIG_RTC_DRV_PCF8523=m
CONFIG_RTC_DRV_PCF85063=m
CONFIG_RTC_DRV_PCF85363=m
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_PCF8583=y
CONFIG_RTC_DRV_M41T80=m
CONFIG_RTC_DRV_M41T80_WDT=y
CONFIG_RTC_DRV_BQ32K=m
CONFIG_RTC_DRV_S35390A=m
CONFIG_RTC_DRV_FM3130=m
CONFIG_RTC_DRV_RX8010=m
CONFIG_RTC_DRV_RX8581=m
CONFIG_RTC_DRV_RX8025=m
CONFIG_RTC_DRV_EM3027=m
CONFIG_RTC_DRV_RV3028=m
CONFIG_RTC_DRV_RV3032=m
CONFIG_RTC_DRV_RV8803=m
CONFIG_RTC_DRV_SD3078=m

#
# SPI RTC drivers
#
CONFIG_RTC_DRV_M41T93=m
CONFIG_RTC_DRV_M41T94=m
CONFIG_RTC_DRV_DS1302=m
CONFIG_RTC_DRV_DS1305=m
CONFIG_RTC_DRV_DS1343=m
CONFIG_RTC_DRV_DS1347=m
CONFIG_RTC_DRV_DS1390=m
CONFIG_RTC_DRV_MAX6916=m
CONFIG_RTC_DRV_R9701=m
CONFIG_RTC_DRV_RX4581=m
CONFIG_RTC_DRV_RS5C348=m
CONFIG_RTC_DRV_MAX6902=m
CONFIG_RTC_DRV_PCF2123=m
CONFIG_RTC_DRV_MCP795=m
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
CONFIG_RTC_DRV_DS3232=m
CONFIG_RTC_DRV_DS3232_HWMON=y
CONFIG_RTC_DRV_PCF2127=m
CONFIG_RTC_DRV_RV3029C2=m
CONFIG_RTC_DRV_RV3029_HWMON=y
CONFIG_RTC_DRV_RX6110=m

#
# Platform RTC drivers
#
CONFIG_RTC_DRV_DS1286=m
CONFIG_RTC_DRV_DS1511=m
CONFIG_RTC_DRV_DS1553=m
CONFIG_RTC_DRV_DS1685_FAMILY=m
CONFIG_RTC_DRV_DS1685=y
# CONFIG_RTC_DRV_DS1689 is not set
# CONFIG_RTC_DRV_DS17285 is not set
# CONFIG_RTC_DRV_DS17485 is not set
# CONFIG_RTC_DRV_DS17885 is not set
CONFIG_RTC_DRV_DS1742=m
CONFIG_RTC_DRV_DS2404=m
CONFIG_RTC_DRV_EFI=m
CONFIG_RTC_DRV_STK17TA8=m
CONFIG_RTC_DRV_M48T86=m
CONFIG_RTC_DRV_M48T35=m
CONFIG_RTC_DRV_M48T59=m
CONFIG_RTC_DRV_MSM6242=m
CONFIG_RTC_DRV_BQ4802=m
CONFIG_RTC_DRV_RP5C01=m
CONFIG_RTC_DRV_V3020=m
CONFIG_RTC_DRV_OPTEE=m
CONFIG_RTC_DRV_ZYNQMP=m

#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_PL030=m
CONFIG_RTC_DRV_PL031=m
CONFIG_RTC_DRV_CADENCE=m
CONFIG_RTC_DRV_FTRTC010=m
CONFIG_RTC_DRV_R7301=m

#
# HID Sensor RTC drivers
#
CONFIG_RTC_DRV_HID_SENSOR_TIME=m
CONFIG_RTC_DRV_GOLDFISH=m
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
CONFIG_AMBA_PL08X=y
# CONFIG_BCM_SBA_RAID is not set
CONFIG_DW_AXI_DMAC=m
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_MV_XOR_V2 is not set
CONFIG_PL330_DMA=y
# CONFIG_PLX_DMA is not set
CONFIG_ROCKCHIP_DMA=y
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
# CONFIG_XILINX_ZYNQMP_DPDMA is not set
# CONFIG_QCOM_HIDMA_MGMT is not set
# CONFIG_QCOM_HIDMA is not set
CONFIG_DW_DMAC_CORE=m
CONFIG_DW_DMAC=m
CONFIG_DW_DMAC_PCI=m
CONFIG_DW_EDMA=m
CONFIG_DW_EDMA_PCIE=m
# CONFIG_SF_PDMA is not set

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set

#
# DMABUF options
#
CONFIG_DMABUF_CACHE=y
# CONFIG_RK_DMABUF_DEBUG is not set
CONFIG_DMABUF_PARTIAL=y
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_SW_SYNC_DEBUG=y
# CONFIG_UDMABUF is not set
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_DEBUG is not set
# CONFIG_DMABUF_SELFTESTS is not set
CONFIG_DMABUF_HEAPS=y
CONFIG_DMABUF_SYSFS_STATS=y
CONFIG_DMABUF_HEAPS_SYSTEM=y
CONFIG_DMABUF_HEAPS_CMA=y
# CONFIG_DMABUF_HEAPS_SRAM is not set
CONFIG_DMABUF_HEAPS_ROCKCHIP=y
CONFIG_DMABUF_HEAPS_ROCKCHIP_CMA_HEAP=y
CONFIG_DMABUF_HEAPS_ROCKCHIP_CMA_ALIGNMENT=8
CONFIG_DMABUF_HEAPS_ROCKCHIP_SYSTEM_HEAP=y
# CONFIG_DMABUF_RK_HEAPS_DEBUG is not set
# CONFIG_DMABUF_RK_HEAPS_DEBUG_PRINT is not set
# end of DMABUF options

CONFIG_AUXDISPLAY=y
CONFIG_CHARLCD=m
CONFIG_LINEDISP=m
CONFIG_HD44780_COMMON=m
CONFIG_HD44780=m
CONFIG_IMG_ASCII_LCD=m
CONFIG_HT16K33=m
CONFIG_LCD2S=m
# CONFIG_PANEL_CHANGE_MESSAGE is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_UIO=m
# CONFIG_UIO_CIF is not set
# CONFIG_UIO_PDRV_GENIRQ is not set
# CONFIG_UIO_DMEM_GENIRQ is not set
# CONFIG_UIO_AEC is not set
# CONFIG_UIO_SERCOS3 is not set
# CONFIG_UIO_PCI_GENERIC is not set
# CONFIG_UIO_NETX is not set
# CONFIG_UIO_PRUSS is not set
# CONFIG_UIO_MF624 is not set
# CONFIG_VFIO is not set
CONFIG_VIRT_DRIVERS=y
CONFIG_VMGENID=y
# CONFIG_NITRO_ENCLAVES is not set
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_PCI_LIB=m
CONFIG_VIRTIO_PCI_LIB_LEGACY=m
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=m
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
# CONFIG_VDPA is not set
CONFIG_VHOST_IOTLB=m
CONFIG_VHOST=m
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_VSOCK=m
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set

#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
# CONFIG_COMEDI is not set
CONFIG_STAGING=y
CONFIG_PRISM2_USB=m
CONFIG_RTL8192U=m
CONFIG_RTLLIB=m
CONFIG_RTLLIB_CRYPTO_CCMP=m
CONFIG_RTLLIB_CRYPTO_TKIP=m
CONFIG_RTLLIB_CRYPTO_WEP=m
CONFIG_RTL8192E=m
CONFIG_RTL8723BS=m
CONFIG_R8712U=m
CONFIG_RTS5208=m
CONFIG_VT6655=m
CONFIG_VT6656=m

#
# IIO staging drivers
#

#
# Accelerometers
#
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16240 is not set
# end of Accelerometers

#
# Analog to digital converters
#
# CONFIG_AD7816 is not set
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
# CONFIG_ADT7316 is not set
# end of Analog digital bi-direction converters

#
# Direct Digital Synthesis
#
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
# CONFIG_AD5933 is not set
# end of Network Analyzer, Impedance Converters

#
# Active energy metering IC
#
# CONFIG_ADE7854 is not set
# end of Active energy metering IC

#
# Resolver to digital converters
#
# CONFIG_AD2S1210 is not set
# end of Resolver to digital converters
# end of IIO staging drivers

# CONFIG_FB_SM750 is not set
CONFIG_STAGING_MEDIA=y
CONFIG_VIDEO_ROCKCHIP_VDEC=y
# CONFIG_STAGING_MEDIA_DEPRECATED is not set
# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
CONFIG_FB_TFT=m
CONFIG_FB_TFT_AGM1264K_FL=m
CONFIG_FB_TFT_BD663474=m
CONFIG_FB_TFT_HX8340BN=m
CONFIG_FB_TFT_HX8347D=m
CONFIG_FB_TFT_HX8353D=m
CONFIG_FB_TFT_HX8357D=m
CONFIG_FB_TFT_ILI9163=m
CONFIG_FB_TFT_ILI9320=m
CONFIG_FB_TFT_ILI9325=m
CONFIG_FB_TFT_ILI9340=m
CONFIG_FB_TFT_ILI9341=m
CONFIG_FB_TFT_ILI9481=m
CONFIG_FB_TFT_ILI9486=m
CONFIG_FB_TFT_PCD8544=m
CONFIG_FB_TFT_RA8875=m
CONFIG_FB_TFT_S6D02A1=m
CONFIG_FB_TFT_S6D1121=m
CONFIG_FB_TFT_SEPS525=m
CONFIG_FB_TFT_SH1106=m
CONFIG_FB_TFT_SSD1289=m
CONFIG_FB_TFT_SSD1305=m
CONFIG_FB_TFT_SSD1306=m
CONFIG_FB_TFT_SSD1331=m
CONFIG_FB_TFT_SSD1351=m
CONFIG_FB_TFT_ST7735R=m
CONFIG_FB_TFT_ST7789V=m
CONFIG_FB_TFT_TINYLCD=m
CONFIG_FB_TFT_TLS8204=m
CONFIG_FB_TFT_UC1611=m
CONFIG_FB_TFT_UC1701=m
CONFIG_FB_TFT_UPD161704=m
# CONFIG_KS7010 is not set
# CONFIG_PI433 is not set
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_QLGE is not set
# CONFIG_VME_BUS is not set
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
# CONFIG_SURFACE_PLATFORMS is not set
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
# CONFIG_COMMON_CLK_PROCFS is not set

#
# Clock driver for ARM Reference designs
#
# CONFIG_CLK_ICST is not set
# CONFIG_CLK_SP810 is not set
# end of Clock driver for ARM Reference designs

# CONFIG_LMK04832 is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
# CONFIG_COMMON_CLK_SCPI is not set
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
# CONFIG_COMMON_CLK_XGENE is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_RS9_PCIE is not set
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_VC7 is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
CONFIG_COMMON_CLK_ROCKCHIP=y
CONFIG_CLK_PX30=y
CONFIG_CLK_RV1126B=y
CONFIG_CLK_RK1808=y
CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
CONFIG_CLK_RK3399=y
CONFIG_CLK_RK3506=y
CONFIG_CLK_RK3528=y
CONFIG_CLK_RK3562=y
CONFIG_CLK_RK3568=y
CONFIG_CLK_RK3576=y
CONFIG_CLK_RK3588=y
CONFIG_ROCKCHIP_CLK_COMPENSATION=y
CONFIG_ROCKCHIP_CLK_LINK=y
CONFIG_ROCKCHIP_CLK_BOOST=y
CONFIG_ROCKCHIP_CLK_INV=y
CONFIG_ROCKCHIP_CLK_OUT=y
CONFIG_ROCKCHIP_CLK_PVTM=y
CONFIG_ROCKCHIP_CLK_PVTPLL=y
CONFIG_ROCKCHIP_DDRCLK=y
CONFIG_ROCKCHIP_DDRCLK_SIP=y
CONFIG_ROCKCHIP_DDRCLK_SIP_V2=y
CONFIG_ROCKCHIP_PLL_RK3066=y
CONFIG_ROCKCHIP_PLL_RK3399=y
CONFIG_ROCKCHIP_PLL_RK3588=y
CONFIG_COMMON_CLK_ROCKCHIP_REGMAP=m
CONFIG_CLK_RK618=m
# CONFIG_XILINX_VCU is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_ROCKCHIP=y

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_ACPI=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
# CONFIG_ARM_TIMER_SP804 is not set
# CONFIG_MICROCHIP_PIT64B is not set
# end of Clock Source drivers

CONFIG_MAILBOX=y
CONFIG_MAILBOX_POLL_PERIOD_US=y
CONFIG_ARM_MHU=m
CONFIG_ARM_MHU_V2=m
CONFIG_PLATFORM_MHU=m
CONFIG_PL320_MBOX=y
CONFIG_ROCKCHIP_MBOX=y
CONFIG_ROCKCHIP_MBOX_DEMO=y
CONFIG_PCC=y
CONFIG_ALTERA_MBOX=m
CONFIG_MAILBOX_TEST=m
CONFIG_IOMMU_IOVA=y
CONFIG_IOASID=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_DART is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
CONFIG_IOMMU_SVA=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set
CONFIG_ARM_SMMU_V3=y
CONFIG_ARM_SMMU_V3_SVA=y
CONFIG_VIRTIO_IOMMU=m

#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=y
CONFIG_RPMSG_CHAR=m
CONFIG_RPMSG_CTRL=m
CONFIG_RPMSG_NS=m
CONFIG_RPMSG_QCOM_GLINK=m
CONFIG_RPMSG_QCOM_GLINK_RPM=m
CONFIG_RPMSG_ROCKCHIP_MBOX=y
CONFIG_RPMSG_ROCKCHIP_SOFTIRQ=y
CONFIG_RPMSG_ROCKCHIP_TEST=y
CONFIG_RPMSG_VIRTIO=m
# end of Rpmsg drivers

# CONFIG_SOUNDWIRE is not set

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
# end of Amlogic SoC drivers

#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
# CONFIG_QUICC_ENGINE is not set
# CONFIG_FSL_RCPM is not set
# end of NXP/Freescale QorIQ SoC drivers

#
# fujitsu SoC drivers
#
# CONFIG_A64FX_DIAG is not set
# end of fujitsu SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Enable LiteX SoC Builder specific drivers
#
# CONFIG_LITEX_SOC_CONTROLLER is not set
# end of Enable LiteX SoC Builder specific drivers

#
# Qualcomm SoC drivers
#
CONFIG_QCOM_QMI_HELPERS=m
# end of Qualcomm SoC drivers

#
# Rockchip SoC drivers
#

#
# Rockchip CPU selection
#
CONFIG_CPU_RV1126B=y
CONFIG_CPU_PX30=y
CONFIG_CPU_RK1808=y
CONFIG_CPU_RK3308=y
CONFIG_CPU_RK3328=y
CONFIG_CPU_RK3368=y
CONFIG_CPU_RK3399=y
CONFIG_CPU_RK3506=y
CONFIG_CPU_RK3528=y
CONFIG_CPU_RK3562=y
CONFIG_CPU_RK3568=y
CONFIG_CPU_RK3576=y
CONFIG_CPU_RK3588=y
# end of Rockchip CPU selection

CONFIG_NO_GKI=y
# CONFIG_ROCKCHIP_DISABLE_UNUSED is not set
CONFIG_ROCKCHIP_AMP=y
# CONFIG_ROCKCHIP_ARM64_ALIGN_FAULT_FIX is not set
CONFIG_ROCKCHIP_CPUINFO=y
CONFIG_ROCKCHIP_CSU=y
# CONFIG_ROCKCHIP_DMC_DEBUG is not set
CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
# CONFIG_ROCKCHIP_HW_DECOMPRESS_TEST is not set
CONFIG_ROCKCHIP_HW_DECOMPRESS_USER=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_IOMUX=y
CONFIG_ROCKCHIP_IPA=y
CONFIG_ROCKCHIP_OPP=y
# CONFIG_ROCKCHIP_OPTIMIZE_RT_PRIO is not set
CONFIG_ROCKCHIP_PERFORMANCE=y
CONFIG_ROCKCHIP_PERFORMANCE_LEVEL=2
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ROCKCHIP_PVTM=y
CONFIG_ROCKCHIP_RAMDISK=y
# CONFIG_ROCKCHIP_LITE_ULTRA_SUSPEND is not set
CONFIG_ROCKCHIP_SUSPEND_MODE=y
# CONFIG_ROCKCHIP_SUSPEND_DEBUG is not set
CONFIG_ROCKCHIP_SYSTEM_MONITOR=y
CONFIG_ROCKCHIP_VENDOR_STORAGE=y
CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE=y
# CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE is not set
# CONFIG_ROCKCHIP_RAM_VENDOR_STORAGE is not set
CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER=y

#
# FIQ Debugger
#
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
# CONFIG_FIQ_DEBUGGER_WAKEUP_IRQ_ALWAYS_ON is not set
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y
# CONFIG_FIQ_DEBUGGER_UART_OVERLAY is not set
CONFIG_RK_CONSOLE_THREAD=y
CONFIG_ROCKCHIP_FIQ_DEBUGGER=y
# end of FIQ Debugger

CONFIG_ROCKCHIP_DEBUG=y
# CONFIG_ROCKCHIP_MINI_KERNEL is not set
# CONFIG_ROCKCHIP_THUNDER_BOOT is not set
CONFIG_ROCKCHIP_NPOR_POWERGOOD=y
# CONFIG_RK_CMA_PROCFS is not set
# CONFIG_RK_DMABUF_PROCFS is not set
CONFIG_RK_MEMBLOCK_PROCFS=y
# CONFIG_RK_ZONEINFO_PROCFS is not set
CONFIG_ROCKCHIP_AOA_MIDDLEWARE=m

#
# Rockchip Minidump drivers
#
# CONFIG_ROCKCHIP_MINIDUMP is not set
# end of Rockchip Minidump drivers
# end of Rockchip SoC drivers

# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEVFREQ_GOV_PASSIVE=y

#
# DEVFREQ Drivers
#
CONFIG_ARM_ROCKCHIP_BUS_DEVFREQ=y
CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_NOCP=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
CONFIG_EXTCON_ADC_JACK=m
# CONFIG_EXTCON_FSA9480 is not set
CONFIG_EXTCON_GPIO=m
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_PTN5150 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
# CONFIG_EXTCON_USB_GPIO is not set
# CONFIG_EXTCON_USBC_TUSB320 is not set
CONFIG_EXTCON_USBC_VIRTUAL_PD=y
# CONFIG_MEMORY is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
CONFIG_IIO_BUFFER_DMA=m
CONFIG_IIO_BUFFER_DMAENGINE=m
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
CONFIG_IIO_TRIGGERED_EVENT=m

#
# Accelerometers
#
CONFIG_ADIS16201=m
CONFIG_ADIS16209=m
CONFIG_ADXL313=m
CONFIG_ADXL313_I2C=m
CONFIG_ADXL313_SPI=m
CONFIG_ADXL355=m
CONFIG_ADXL355_I2C=m
CONFIG_ADXL355_SPI=m
CONFIG_ADXL367=m
CONFIG_ADXL367_SPI=m
CONFIG_ADXL367_I2C=m
CONFIG_ADXL372=m
CONFIG_ADXL372_SPI=m
CONFIG_ADXL372_I2C=m
CONFIG_BMA220=m
CONFIG_BMA400=m
CONFIG_BMA400_I2C=m
CONFIG_BMA400_SPI=m
CONFIG_BMC150_ACCEL=m
CONFIG_BMC150_ACCEL_I2C=m
CONFIG_BMC150_ACCEL_SPI=m
CONFIG_BMI088_ACCEL=m
CONFIG_BMI088_ACCEL_SPI=m
CONFIG_DA280=m
CONFIG_DA311=m
CONFIG_DMARD06=m
CONFIG_DMARD09=m
CONFIG_DMARD10=m
CONFIG_FXLS8962AF=m
CONFIG_FXLS8962AF_I2C=m
CONFIG_FXLS8962AF_SPI=m
CONFIG_HID_SENSOR_ACCEL_3D=m
CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
CONFIG_KXSD9=m
CONFIG_KXSD9_SPI=m
CONFIG_KXSD9_I2C=m
CONFIG_KXCJK1013=m
CONFIG_MC3230=m
CONFIG_MMA7455=m
CONFIG_MMA7455_I2C=m
CONFIG_MMA7455_SPI=m
CONFIG_MMA7660=m
CONFIG_MMA8452=m
CONFIG_MMA9551_CORE=m
CONFIG_MMA9551=m
CONFIG_MMA9553=m
CONFIG_MSA311=m
CONFIG_MXC4005=m
CONFIG_MXC6255=m
CONFIG_SCA3000=m
CONFIG_SCA3300=m
CONFIG_STK8312=m
CONFIG_STK8BA50=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=m
CONFIG_AD7091R5=m
CONFIG_AD7124=m
CONFIG_AD7192=m
CONFIG_AD7266=m
CONFIG_AD7280=m
CONFIG_AD7291=m
CONFIG_AD7292=m
CONFIG_AD7298=m
CONFIG_AD7476=m
CONFIG_AD7606=m
CONFIG_AD7606_IFACE_PARALLEL=m
CONFIG_AD7606_IFACE_SPI=m
CONFIG_AD7766=m
CONFIG_AD7768_1=m
CONFIG_AD7780=m
CONFIG_AD7791=m
CONFIG_AD7793=m
CONFIG_AD7887=m
CONFIG_AD7923=m
CONFIG_AD7949=m
CONFIG_AD799X=m
CONFIG_AD9467=m
CONFIG_ADI_AXI_ADC=m
CONFIG_CC10001_ADC=m
CONFIG_ENVELOPE_DETECTOR=m
CONFIG_HI8435=m
CONFIG_HX711=m
CONFIG_INA2XX_ADC=m
CONFIG_LTC2471=m
CONFIG_LTC2485=m
CONFIG_LTC2496=m
CONFIG_LTC2497=m
CONFIG_MAX1027=m
CONFIG_MAX11100=m
CONFIG_MAX1118=m
CONFIG_MAX11205=m
CONFIG_MAX1241=m
CONFIG_MAX1363=m
CONFIG_MAX9611=m
CONFIG_MCP320X=m
CONFIG_MCP3422=m
CONFIG_MCP3911=m
CONFIG_NAU7802=m
CONFIG_ROCKCHIP_FLEXBUS_ADC=m
CONFIG_ROCKCHIP_SARADC=y
CONFIG_ROCKCHIP_SARADC_TEST_CHN=y
CONFIG_RICHTEK_RTQ6056=m
CONFIG_SD_ADC_MODULATOR=m
CONFIG_TI_ADC081C=m
CONFIG_TI_ADC0832=m
CONFIG_TI_ADC084S021=m
CONFIG_TI_ADC12138=m
CONFIG_TI_ADC108S102=m
CONFIG_TI_ADC128S052=m
CONFIG_TI_ADC161S626=m
CONFIG_TI_ADS1015=m
CONFIG_TI_ADS7950=m
CONFIG_TI_ADS8344=m
CONFIG_TI_ADS8688=m
CONFIG_TI_ADS124S08=m
CONFIG_TI_ADS131E08=m
CONFIG_TI_TLC4541=m
CONFIG_TI_TSC2046=m
CONFIG_VF610_ADC=m
CONFIG_XILINX_XADC=m
# end of Analog to digital converters

#
# Analog to digital and digital to analog converters
#
CONFIG_AD74413R=m
# end of Analog to digital and digital to analog converters

#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=m
# end of Analog Front Ends

#
# Amplifiers
#
CONFIG_AD8366=m
CONFIG_ADA4250=m
CONFIG_HMC425=m
# end of Amplifiers

#
# Capacitance to digital converters
#
CONFIG_AD7150=m
CONFIG_AD7746=m
# end of Capacitance to digital converters

#
# Chemical Sensors
#
CONFIG_ATLAS_PH_SENSOR=m
CONFIG_ATLAS_EZO_SENSOR=m
CONFIG_BME680=m
CONFIG_BME680_I2C=m
CONFIG_BME680_SPI=m
CONFIG_CCS811=m
CONFIG_IAQCORE=m
# CONFIG_PMS7003 is not set
CONFIG_SCD30_CORE=m
CONFIG_SCD30_I2C=m
# CONFIG_SCD30_SERIAL is not set
CONFIG_SCD4X=m
CONFIG_SENSIRION_SGP30=m
CONFIG_SENSIRION_SGP40=m
CONFIG_SPS30=m
CONFIG_SPS30_I2C=m
# CONFIG_SPS30_SERIAL is not set
CONFIG_SENSEAIR_SUNRISE_CO2=m
CONFIG_VZ89X=m
# end of Chemical Sensors

#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
# end of Hid Sensor IIO Common

CONFIG_IIO_MS_SENSORS_I2C=m

#
# IIO SCMI Sensors
#
CONFIG_IIO_SCMI=m
# end of IIO SCMI Sensors

#
# SSP Sensor Common
#
CONFIG_IIO_SSP_SENSORS_COMMONS=m
CONFIG_IIO_SSP_SENSORHUB=m
# end of SSP Sensor Common

CONFIG_IIO_ST_SENSORS_I2C=m
CONFIG_IIO_ST_SENSORS_SPI=m
CONFIG_IIO_ST_SENSORS_CORE=m

#
# Digital to analog converters
#
# CONFIG_AD3552R is not set
CONFIG_AD5064=m
CONFIG_AD5360=m
CONFIG_AD5380=m
CONFIG_AD5421=m
CONFIG_AD5446=m
CONFIG_AD5449=m
CONFIG_AD5592R_BASE=m
CONFIG_AD5592R=m
CONFIG_AD5593R=m
CONFIG_AD5504=m
CONFIG_AD5624R_SPI=m
CONFIG_LTC2688=m
CONFIG_AD5686=m
CONFIG_AD5686_SPI=m
CONFIG_AD5696_I2C=m
CONFIG_AD5755=m
CONFIG_AD5758=m
CONFIG_AD5761=m
CONFIG_AD5764=m
CONFIG_AD5766=m
CONFIG_AD5770R=m
CONFIG_AD5791=m
CONFIG_AD7293=m
CONFIG_AD7303=m
CONFIG_AD8801=m
CONFIG_DPOT_DAC=m
CONFIG_DS4424=m
CONFIG_LTC1660=m
CONFIG_LTC2632=m
CONFIG_M62332=m
CONFIG_MAX517=m
CONFIG_MAX5821=m
CONFIG_MCP4725=m
CONFIG_MCP4922=m
CONFIG_ROCKCHIP_FLEXBUS_DAC=m
CONFIG_TI_DAC082S085=m
CONFIG_TI_DAC5571=m
CONFIG_TI_DAC7311=m
CONFIG_TI_DAC7612=m
CONFIG_VF610_DAC=m
# end of Digital to analog converters

#
# IIO dummy driver
#
CONFIG_IIO_DUMMY_EVGEN=m
CONFIG_IIO_SIMPLE_DUMMY=m
CONFIG_IIO_SIMPLE_DUMMY_EVENTS=y
CONFIG_IIO_SIMPLE_DUMMY_BUFFER=y
# end of IIO dummy driver

#
# Filters
#
CONFIG_ADMV8818=m
# end of Filters

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
CONFIG_AD9523=m
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4350=m
CONFIG_ADF4371=m
CONFIG_ADMV1013=m
CONFIG_ADMV1014=m
CONFIG_ADMV4420=m
CONFIG_ADRF6780=m
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=m
CONFIG_ADIS16130=m
CONFIG_ADIS16136=m
CONFIG_ADIS16260=m
CONFIG_ADXRS290=m
CONFIG_ADXRS450=m
CONFIG_BMG160=m
CONFIG_BMG160_I2C=m
CONFIG_BMG160_SPI=m
CONFIG_FXAS21002C=m
CONFIG_FXAS21002C_I2C=m
CONFIG_FXAS21002C_SPI=m
CONFIG_HID_SENSOR_GYRO_3D=m
CONFIG_MPU3050=m
CONFIG_MPU3050_I2C=m
CONFIG_IIO_ST_GYRO_3AXIS=m
CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
CONFIG_ITG3200=m
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
CONFIG_AFE4403=m
CONFIG_AFE4404=m
CONFIG_MAX30100=m
CONFIG_MAX30102=m
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
CONFIG_AM2315=m
CONFIG_DHT11=m
CONFIG_HDC100X=m
CONFIG_HDC2010=m
CONFIG_HID_SENSOR_HUMIDITY=m
CONFIG_HTS221=m
CONFIG_HTS221_I2C=m
CONFIG_HTS221_SPI=m
CONFIG_HTU21=m
CONFIG_SI7005=m
CONFIG_SI7020=m
# end of Humidity sensors

#
# Inertial measurement units
#
CONFIG_ADIS16400=m
CONFIG_ADIS16460=m
CONFIG_ADIS16475=m
CONFIG_ADIS16480=m
CONFIG_BMI160=m
CONFIG_BMI160_I2C=m
CONFIG_BMI160_SPI=m
CONFIG_BOSCH_BNO055=m
# CONFIG_BOSCH_BNO055_SERIAL is not set
CONFIG_BOSCH_BNO055_I2C=m
CONFIG_FXOS8700=m
CONFIG_FXOS8700_I2C=m
CONFIG_FXOS8700_SPI=m
CONFIG_KMX61=m
CONFIG_INV_ICM42600=m
CONFIG_INV_ICM42600_I2C=m
CONFIG_INV_ICM42600_SPI=m
# CONFIG_IIO_INV_ICM42607 is not set
CONFIG_INV_ICM42670=m
CONFIG_INV_ICM42670_I2C=m
CONFIG_INV_ICM42670_SPI=m
CONFIG_INV_MPU6050_IIO=m
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_SPI=m
CONFIG_IIO_ST_LSM6DSR=m
CONFIG_IIO_ST_LSM6DSR_I2C=m
CONFIG_IIO_ST_LSM6DSR_SPI=m
CONFIG_IIO_ST_LSM6DSR_MAY_WAKEUP=y
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_LSM6DSX_I2C=m
CONFIG_IIO_ST_LSM6DSX_SPI=m
CONFIG_IIO_ST_LSM9DS0=m
CONFIG_IIO_ST_LSM9DS0_I2C=m
CONFIG_IIO_ST_LSM9DS0_SPI=m
# end of Inertial measurement units

CONFIG_IIO_ADIS_LIB=m
CONFIG_IIO_ADIS_LIB_BUFFER=y

#
# Light sensors
#
CONFIG_ACPI_ALS=m
CONFIG_ADJD_S311=m
CONFIG_ADUX1020=m
CONFIG_AL3010=m
CONFIG_AL3320A=m
CONFIG_APDS9300=m
CONFIG_APDS9960=m
CONFIG_AS73211=m
CONFIG_BH1750=m
CONFIG_BH1780=m
CONFIG_CM32181=m
CONFIG_CM3232=m
CONFIG_CM3323=m
CONFIG_CM3605=m
CONFIG_CM36651=m
CONFIG_GP2AP002=m
CONFIG_GP2AP020A00F=m
CONFIG_SENSORS_ISL29018=m
CONFIG_SENSORS_ISL29028=m
CONFIG_ISL29125=m
CONFIG_HID_SENSOR_ALS=m
CONFIG_HID_SENSOR_PROX=m
CONFIG_JSA1212=m
CONFIG_RPR0521=m
CONFIG_LTR501=m
CONFIG_LTRF216A=m
CONFIG_LV0104CS=m
CONFIG_MAX44000=m
CONFIG_MAX44009=m
CONFIG_NOA1305=m
CONFIG_OPT3001=m
CONFIG_PA12203001=m
CONFIG_SI1133=m
CONFIG_SI1145=m
CONFIG_STK3310=m
CONFIG_ST_UVIS25=m
CONFIG_ST_UVIS25_I2C=m
CONFIG_ST_UVIS25_SPI=m
CONFIG_TCS3414=m
CONFIG_TCS3472=m
CONFIG_SENSORS_TSL2563=m
CONFIG_TSL2583=m
CONFIG_TSL2591=m
CONFIG_TSL2772=m
CONFIG_TSL4531=m
CONFIG_UCS12CM0=m
CONFIG_US5182D=m
CONFIG_VCNL4000=m
CONFIG_VCNL4035=m
CONFIG_VEML6030=m
CONFIG_VEML6070=m
CONFIG_VL6180=m
CONFIG_ZOPT2201=m
# end of Light sensors

#
# Magnetometer sensors
#
CONFIG_AK8974=m
CONFIG_AK8975=m
CONFIG_AK09911=m
CONFIG_BMC150_MAGN=m
CONFIG_BMC150_MAGN_I2C=m
CONFIG_BMC150_MAGN_SPI=m
CONFIG_MAG3110=m
CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
CONFIG_MMC35240=m
CONFIG_IIO_ST_MAGN_3AXIS=m
CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
CONFIG_SENSORS_HMC5843=m
CONFIG_SENSORS_HMC5843_I2C=m
CONFIG_SENSORS_HMC5843_SPI=m
CONFIG_SENSORS_RM3100=m
CONFIG_SENSORS_RM3100_I2C=m
CONFIG_SENSORS_RM3100_SPI=m
CONFIG_YAMAHA_YAS530=m
# end of Magnetometer sensors

#
# Multiplexers
#
CONFIG_IIO_MUX=m
# end of Multiplexers

#
# Inclinometer sensors
#
CONFIG_HID_SENSOR_INCLINOMETER_3D=m
CONFIG_HID_SENSOR_DEVICE_ROTATION=m
# end of Inclinometer sensors

#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=m
CONFIG_IIO_INTERRUPT_TRIGGER=m
CONFIG_IIO_TIGHTLOOP_TRIGGER=m
CONFIG_IIO_SYSFS_TRIGGER=m
# end of Triggers - standalone

#
# Linear and angular position sensors
#
CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
# end of Linear and angular position sensors

#
# Digital potentiometers
#
CONFIG_AD5110=m
CONFIG_AD5272=m
CONFIG_DS1803=m
CONFIG_MAX5432=m
CONFIG_MAX5481=m
CONFIG_MAX5487=m
CONFIG_MCP4018=m
CONFIG_MCP4131=m
CONFIG_MCP4531=m
CONFIG_MCP41010=m
CONFIG_TPL0102=m
# end of Digital potentiometers

#
# Digital potentiostats
#
CONFIG_LMP91000=m
# end of Digital potentiostats

#
# Pressure sensors
#
CONFIG_ABP060MG=m
CONFIG_BMP280=m
CONFIG_BMP280_I2C=m
CONFIG_BMP280_SPI=m
CONFIG_DLHL60D=m
CONFIG_DPS310=m
CONFIG_HID_SENSOR_PRESS=m
CONFIG_HP03=m
CONFIG_ICP10100=m
CONFIG_MPL115=m
CONFIG_MPL115_I2C=m
CONFIG_MPL115_SPI=m
CONFIG_MPL3115=m
CONFIG_MS5611=m
CONFIG_MS5611_I2C=m
CONFIG_MS5611_SPI=m
CONFIG_MS5637=m
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_PRESS_I2C=m
CONFIG_IIO_ST_PRESS_SPI=m
CONFIG_T5403=m
CONFIG_HP206C=m
CONFIG_ZPA2326=m
CONFIG_ZPA2326_I2C=m
CONFIG_ZPA2326_SPI=m
# end of Pressure sensors

#
# Lightning sensors
#
CONFIG_AS3935=m
# end of Lightning sensors

#
# Proximity and distance sensors
#
# CONFIG_DTOF_NDS03 is not set
CONFIG_ISL29501=m
CONFIG_LIDAR_LITE_V2=m
CONFIG_MB1232=m
CONFIG_PING=m
CONFIG_RFD77402=m
CONFIG_SRF04=m
CONFIG_SX_COMMON=m
CONFIG_SX9310=m
CONFIG_SX9324=m
CONFIG_SX9360=m
CONFIG_SX9500=m
CONFIG_SRF08=m
CONFIG_VCNL3020=m
CONFIG_VL53L0X_I2C=m
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
CONFIG_AD2S90=m
CONFIG_AD2S1200=m
# end of Resolver to digital converters

#
# Temperature sensors
#
CONFIG_LTC2983=m
CONFIG_MAXIM_THERMOCOUPLE=m
CONFIG_HID_SENSOR_TEMP=m
CONFIG_MLX90614=m
CONFIG_MLX90632=m
CONFIG_TMP006=m
CONFIG_TMP007=m
CONFIG_TMP117=m
CONFIG_TSYS01=m
CONFIG_TSYS02D=m
CONFIG_MAX31856=m
CONFIG_MAX31865=m
# end of Temperature sensors

# CONFIG_NTB is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_ATMEL_TCB is not set
# CONFIG_PWM_CLK is not set
# CONFIG_PWM_DWC is not set
# CONFIG_PWM_FSL_FTM is not set
CONFIG_PWM_GPIO=m
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_ROCKCHIP=y
# CONFIG_PWM_ROCKCHIP_ONESHOT is not set
# CONFIG_PWM_ROCKCHIP_TEST is not set
# CONFIG_PWM_R7F701 is not set
# CONFIG_PWM_XILINX is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_AL_FIC is not set
# CONFIG_XILINX_INTC is not set
CONFIG_PARTITION_PERCPU=y
# end of IRQ chip support

# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_SCMI=y
# CONFIG_RESET_SIMPLE is not set
# CONFIG_RESET_TI_SYSCON is not set
# CONFIG_RESET_TI_TPS380X is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_PHY_XGENE is not set
# CONFIG_PHY_CAN_TRANSCEIVER is not set

#
# PHY drivers for Broadcom platforms
#
# CONFIG_BCM_KONA_USB2_PHY is not set
# end of PHY drivers for Broadcom platforms

# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_DPHY_RX is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_LAN966X_SERDES is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
# CONFIG_PHY_QCOM_USB_HS is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y
CONFIG_PHY_ROCKCHIP_DP=y
CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_USB3=y
CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
CONFIG_PHY_ROCKCHIP_MIPI_RX=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
CONFIG_PHY_ROCKCHIP_NANENG_EDP=y
CONFIG_PHY_ROCKCHIP_NANENG_USB2=y
CONFIG_PHY_ROCKCHIP_PCIE=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PHY_ROCKCHIP_USB=y
CONFIG_PHY_ROCKCHIP_USBDP=y
# CONFIG_PHY_SAMSUNG_USB2 is not set
# CONFIG_PHY_TUSB1210 is not set
# end of PHY Subsystem

# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCI400_PMU=y
CONFIG_ARM_CCI5xx_PMU=y
CONFIG_ARM_CCN=m
CONFIG_ARM_CMN=m
CONFIG_ARM_PMU=y
CONFIG_ARM_PMU_ACPI=y
CONFIG_ARM_SMMU_V3_PMU=m
CONFIG_ARM_DSU_PMU=m
CONFIG_ARM_SPE_PMU=m
# CONFIG_ARM_DMC620_PMU is not set
# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set
# CONFIG_HISI_PMU is not set
# CONFIG_HISI_PCIE_PMU is not set
# CONFIG_HNS3_PMU is not set
# CONFIG_DWC_PCIE_PMU is not set
# end of Performance monitor support

# CONFIG_RAS is not set
# CONFIG_USB4 is not set

#
# Android
#
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_BINDERFS=y
CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder,anbox-binder,anbox-hwbinder,anbox-vndbinder"
# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
# end of Android

# CONFIG_LIBNVDIMM is not set
CONFIG_DAX=y
CONFIG_DEV_DAX=y
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
# CONFIG_NVMEM_RMEM is not set
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
CONFIG_NVMEM_ROCKCHIP_OTP=y
CONFIG_NVMEM_ROCKCHIP_SEC_OTP=y
CONFIG_NVMEM_U_BOOT_ENV=y

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# CONFIG_HISI_PTT is not set
# end of HW tracing support

# CONFIG_FPGA is not set
# CONFIG_FSI is not set
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_MULTIPLEXER=m

#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
# CONFIG_MUX_ADGS1408 is not set
# CONFIG_MUX_GPIO is not set
# CONFIG_MUX_MMIO is not set
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set
# CONFIG_INTERCONNECT is not set
# CONFIG_COUNTER is not set
# CONFIG_MOST is not set
# CONFIG_PECI is not set
# CONFIG_HTE is not set
# CONFIG_RK_FLASH is not set
# CONFIG_RK_NAND is not set

#
# Headset device support
#
CONFIG_RK_HEADSET=y
# end of Headset device support

#
# RKNPU
#
CONFIG_ROCKCHIP_RKNPU=y
CONFIG_ROCKCHIP_RKNPU_DEBUG_FS=y
CONFIG_ROCKCHIP_RKNPU_PROC_FS=y
CONFIG_ROCKCHIP_RKNPU_FENCE=y
CONFIG_ROCKCHIP_RKNPU_SRAM=y
# CONFIG_ROCKCHIP_RKNPU_DRM_GEM is not set
CONFIG_ROCKCHIP_RKNPU_DMA_HEAP=y
# end of RKNPU
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
# CONFIG_VALIDATE_FS_PARSER is not set
CONFIG_FS_IOMAP=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=m
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
# CONFIG_REISERFS_FS_XATTR is not set
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
# CONFIG_JFS_DEBUG is not set
# CONFIG_JFS_STATISTICS is not set
CONFIG_XFS_FS=y
# CONFIG_XFS_SUPPORT_V4 is not set
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
# CONFIG_XFS_RT is not set
# CONFIG_XFS_ONLINE_SCRUB is not set
# CONFIG_XFS_WARN is not set
# CONFIG_XFS_DEBUG is not set
CONFIG_GFS2_FS=m
# CONFIG_GFS2_FS_LOCKING_DLM is not set
CONFIG_OCFS2_FS=m
CONFIG_OCFS2_FS_O2CB=m
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
CONFIG_OCFS2_FS_STATS=y
CONFIG_OCFS2_DEBUG_MASKLOG=y
# CONFIG_OCFS2_DEBUG_FS is not set
CONFIG_BTRFS_FS=y
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
# CONFIG_BTRFS_FS_REF_VERIFY is not set
# CONFIG_NILFS2_FS is not set
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
# CONFIG_F2FS_FAULT_INJECTION is not set
CONFIG_F2FS_FS_COMPRESSION=y
CONFIG_F2FS_FS_LZO=y
CONFIG_F2FS_FS_LZORLE=y
CONFIG_F2FS_FS_LZ4=y
CONFIG_F2FS_FS_LZ4HC=y
CONFIG_F2FS_FS_ZSTD=y
CONFIG_F2FS_IOSTAT=y
# CONFIG_F2FS_UNFAIR_RWSEM is not set
# CONFIG_ZONEFS_FS is not set
# CONFIG_FS_DAX is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_PRINT_QUOTA_WARNING is not set
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
# CONFIG_AUTOFS4_FS is not set
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=m
CONFIG_CUSE=m
CONFIG_VIRTIO_FS=m
CONFIG_OVERLAY_FS=m
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set

#
# Caches
#
CONFIG_NETFS_SUPPORT=m
# CONFIG_NETFS_STATS is not set
CONFIG_FSCACHE=m
# CONFIG_FSCACHE_STATS is not set
# CONFIG_FSCACHE_DEBUG is not set
CONFIG_CACHEFILES=m
# CONFIG_CACHEFILES_DEBUG is not set
# CONFIG_CACHEFILES_ERROR_INJECTION is not set
# CONFIG_CACHEFILES_ONDEMAND is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=936
CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_EXFAT_FS=y
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_NTFS_FS is not set
CONFIG_NTFS3_FS=m
CONFIG_NTFS3_64BIT_CLUSTER=y
CONFIG_NTFS3_LZX_XPRESS=y
CONFIG_NTFS3_FS_POSIX_ACL=y
# end of DOS/FAT/EXFAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_TMPFS_INODE64 is not set
CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
# CONFIG_HUGETLBFS is not set
CONFIG_MEMFD_CREATE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=y
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
CONFIG_ECRYPT_FS=m
# CONFIG_ECRYPT_FS_MESSAGING is not set
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
CONFIG_JFFS2_SUMMARY=y
# CONFIG_JFFS2_FS_XATTR is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
CONFIG_UBIFS_FS=m
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
# CONFIG_CRAMFS is not set
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_FILE_CACHE=y
# CONFIG_SQUASHFS_FILE_DIRECT is not set
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_ZSTD=y
CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
# CONFIG_SQUASHFS_EMBEDDED is not set
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
CONFIG_PSTORE_DEFLATE_COMPRESS=y
CONFIG_PSTORE_LZO_COMPRESS=y
CONFIG_PSTORE_LZ4_COMPRESS=y
CONFIG_PSTORE_LZ4HC_COMPRESS=y
CONFIG_PSTORE_842_COMPRESS=y
CONFIG_PSTORE_ZSTD_COMPRESS=y
CONFIG_PSTORE_COMPRESS=y
# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT=y
CONFIG_PSTORE_COMPRESS_DEFAULT="zstd"
CONFIG_PSTORE_CONSOLE=y
# CONFIG_PSTORE_PMSG is not set
CONFIG_PSTORE_RAM=y
# CONFIG_PSTORE_BLK is not set
# CONFIG_PSTORE_BOOT_LOG is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_EROFS_FS=m
# CONFIG_EROFS_FS_DEBUG is not set
CONFIG_EROFS_FS_XATTR=y
CONFIG_EROFS_FS_POSIX_ACL=y
CONFIG_EROFS_FS_SECURITY=y
CONFIG_EROFS_FS_ZIP=y
# CONFIG_EROFS_FS_ZIP_LZMA is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V2=m
CONFIG_NFS_V3=m
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=m
CONFIG_NFS_SWAP=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=m
CONFIG_PNFS_BLOCK=m
CONFIG_PNFS_FLEXFILE_LAYOUT=m
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
CONFIG_NFS_V4_1_MIGRATION=y
CONFIG_NFS_V4_SECURITY_LABEL=y
CONFIG_NFS_FSCACHE=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
CONFIG_NFS_V4_2_READ_PLUS=y
CONFIG_NFSD=m
# CONFIG_NFSD_V2 is not set
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
CONFIG_NFSD_PNFS=y
CONFIG_NFSD_BLOCKLAYOUT=y
CONFIG_NFSD_SCSILAYOUT=y
CONFIG_NFSD_FLEXFILELAYOUT=y
CONFIG_NFSD_V4_2_INTER_SSC=y
# CONFIG_NFSD_V4_SECURITY_LABEL is not set
CONFIG_GRACE_PERIOD=m
CONFIG_LOCKD=m
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=m
CONFIG_NFS_COMMON=y
CONFIG_NFS_V4_2_SSC_HELPER=y
CONFIG_SUNRPC=m
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_BACKCHANNEL=y
CONFIG_SUNRPC_SWAP=y
CONFIG_RPCSEC_GSS_KRB5=m
# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
# CONFIG_SUNRPC_DEBUG is not set
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
# CONFIG_CEPH_FS_SECURITY_LABEL is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
# CONFIG_CIFS_DEBUG is not set
CONFIG_CIFS_DFS_UPCALL=y
# CONFIG_CIFS_SWN_UPCALL is not set
# CONFIG_CIFS_FSCACHE is not set
# CONFIG_SMB_SERVER is not set
CONFIG_SMBFS=m
CONFIG_CODA_FS=m
CONFIG_AFS_FS=m
# CONFIG_AFS_DEBUG is not set
# CONFIG_AFS_FSCACHE is not set
# CONFIG_AFS_DEBUG_CURSOR is not set
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
# CONFIG_9P_FS_SECURITY is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=m
CONFIG_NLS_MAC_GAELIC=m
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=y
CONFIG_DLM=m
# CONFIG_DLM_DEPRECATED_API is not set
# CONFIG_DLM_DEBUG is not set
CONFIG_UNICODE=y
# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_TRUSTED_KEYS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_PROC_MEM_ALWAYS_FORCE=y
# CONFIG_PROC_MEM_FORCE_PTRACE is not set
# CONFIG_PROC_MEM_NO_FORCE is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
# CONFIG_SECURITY_NETWORK_XFRM is not set
CONFIG_SECURITY_PATH=y
CONFIG_LSM_MMAP_MIN_ADDR=32768
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_SECURITY_SELINUX=y
# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set
# CONFIG_SECURITY_SELINUX_DISABLE is not set
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
CONFIG_SECURITY_APPARMOR=y
# CONFIG_SECURITY_APPARMOR_DEBUG is not set
CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y
CONFIG_SECURITY_APPARMOR_HASH=y
CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y
CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
# CONFIG_SECURITY_LANDLOCK is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
CONFIG_INTEGRITY_AUDIT=y
# CONFIG_IMA is not set
# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
# CONFIG_EVM is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor "

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
CONFIG_INIT_STACK_NONE=y
# CONFIG_INIT_STACK_ALL_PATTERN is not set
# CONFIG_INIT_STACK_ALL_ZERO is not set
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
# CONFIG_ZERO_CALL_USED_REGS is not set
# end of Memory initialization

CONFIG_RANDSTRUCT_NONE=y
# CONFIG_RANDSTRUCT_FULL is not set
# CONFIG_RANDSTRUCT_PERFORMANCE is not set
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=y
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
# CONFIG_CRYPTO_USER is not set
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_CRYPTD=m
CONFIG_CRYPTO_AUTHENC=m
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_ENGINE=m
# end of Crypto core or helper

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
CONFIG_CRYPTO_ECC=m
CONFIG_CRYPTO_ECDH=m
CONFIG_CRYPTO_ECDSA=m
CONFIG_CRYPTO_ECRDSA=m
CONFIG_CRYPTO_SM2=y
CONFIG_CRYPTO_CURVE25519=y
# end of Public-key cryptography

#
# Block ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_ARIA=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_BLOWFISH_COMMON=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST_COMMON=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_GENERIC=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y
# end of Block ciphers

#
# Length-preserving ciphers and modes
#
CONFIG_CRYPTO_ADIANTUM=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HCTR2=m
CONFIG_CRYPTO_KEYWRAP=m
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XCTR=m
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_NHPOLY1305=y
# end of Length-preserving ciphers and modes

#
# AEAD (authenticated encryption with associated data) ciphers
#
CONFIG_CRYPTO_AEGIS128=y
CONFIG_CRYPTO_AEGIS128_SIMD=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_SEQIV=m
CONFIG_CRYPTO_ECHAINIV=m
CONFIG_CRYPTO_ESSIV=m
# end of AEAD (authenticated encryption with associated data) ciphers

#
# Hashes, digests, and MACs
#
CONFIG_CRYPTO_BLAKE2B=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_POLYVAL=m
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_SM3_GENERIC=y
CONFIG_CRYPTO_STREEBOG=m
CONFIG_CRYPTO_VMAC=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_XXHASH=y
# end of Hashes, digests, and MACs

#
# CRCs (cyclic redundancy checks)
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
# end of CRCs (cyclic redundancy checks)

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=y
CONFIG_CRYPTO_ZSTD=y
# end of Compression

#
# Random number generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
# CONFIG_CRYPTO_DRBG_HASH is not set
# CONFIG_CRYPTO_DRBG_CTR is not set
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
# end of Random number generation

#
# Userspace interface
#
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=m
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
# end of Userspace interface

CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_NHPOLY1305_NEON=y
CONFIG_CRYPTO_CHACHA20_NEON=y

#
# Accelerated Cryptographic Algorithms for CPU (arm64)
#
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_POLY1305_NEON=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA512_ARM64_CE=y
CONFIG_CRYPTO_SHA3_ARM64=y
# CONFIG_CRYPTO_SM3_NEON is not set
CONFIG_CRYPTO_SM3_ARM64_CE=y
# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CRYPTO_SM4_ARM64_CE=y
# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
# end of Accelerated Cryptographic Algorithms for CPU (arm64)

CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_CCP is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set
# CONFIG_CRYPTO_DEV_QAT_C62X is not set
# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set
# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_ROCKCHIP=m
CONFIG_CRYPTO_DEV_ROCKCHIP_V1=y
CONFIG_CRYPTO_DEV_ROCKCHIP_V2=y
CONFIG_CRYPTO_DEV_ROCKCHIP_V3=y
CONFIG_CRYPTO_DEV_ROCKCHIP_CRYPTO=m
CONFIG_CRYPTO_DEV_ROCKCHIP_CE=y
# CONFIG_CRYPTO_DEV_ROCKCHIP_DEV is not set
CONFIG_CRYPTO_DEV_VIRTIO=m
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
# CONFIG_CRYPTO_DEV_CCREE is not set
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
# CONFIG_CRYPTO_DEV_HISI_TRNG is not set
# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_PKCS7_TEST_KEY is not set
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
# CONFIG_FIPS_SIGNATURE_SELFTEST is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_RAID6_PQ=y
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=m
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
# CONFIG_INDIRECT_PIO is not set
# CONFIG_TRACE_MMIO_ACCESS is not set

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=m
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=m
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
CONFIG_CRYPTO_LIB_CURVE25519=m
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=m
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines

CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC64_ROCKSOFT=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=y
CONFIG_CRC4=m
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=m
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
# CONFIG_XZ_DEC_SPARC is not set
# CONFIG_XZ_DEC_MICROLZMA is not set
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_INTERVAL_TREE=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_SWIOTLB=y
# CONFIG_DMA_RESTRICTED_POOL is not set
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y
# CONFIG_DMA_PERNUMA_CMA is not set

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=256
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_DMA_MAP_BENCHMARK is not set
CONFIG_SGL_ALLOC=y
# CONFIG_FORCE_NR_CPUS is not set
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
CONFIG_IRQ_POLL=y
CONFIG_MPILIB=y
CONFIG_DIMLIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_ARCH_STACKWALK=y
CONFIG_STACKDEPOT=y
CONFIG_SBITMAP=y
CONFIG_PARMAN=m
CONFIG_OBJAGG=m
# end of Library routines

CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER=y
# CONFIG_PRINTK_CALLER is not set
# CONFIG_STACKTRACE_BUILD_ID is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
CONFIG_AS_HAS_NON_CONST_LEB128=y
# CONFIG_DEBUG_INFO_NONE is not set
# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
CONFIG_DEBUG_INFO_DWARF5=y
# CONFIG_DEBUG_INFO_REDUCED is not set
CONFIG_DEBUG_INFO_COMPRESSED=y
# CONFIG_DEBUG_INFO_SPLIT is not set
CONFIG_DEBUG_INFO_BTF=y
CONFIG_PAHOLE_HAS_SPLIT_BTF=y
CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
CONFIG_DEBUG_INFO_BTF_MODULES=y
CONFIG_MODULE_ALLOW_BTF_MISMATCH=y
# CONFIG_GDB_SCRIPTS is not set
CONFIG_FRAME_WARN=2048
CONFIG_STRIP_ASM_SYMS=y
CONFIG_READABLE_ASM=y
CONFIG_HEADERS_INSTALL=y
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_VMLINUX_MAP is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_ARCH_KCSAN=y
CONFIG_HAVE_KCSAN_COMPILER=y
# CONFIG_KCSAN is not set
# end of Generic Kernel Debugging Instruments

#
# Networking Debugging
#
# CONFIG_NET_DEV_REFCNT_TRACKER is not set
# CONFIG_NET_NS_REFCNT_TRACKER is not set
# CONFIG_DEBUG_NET is not set
# end of Networking Debugging

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_SLUB_DEBUG=y
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SHRINKER_DEBUG is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
# end of Memory Debugging

# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SOFTLOCKUP_DETECTOR is not set
CONFIG_HAVE_HARDLOCKUP_DETECTOR_OTHER_CPU=y
# CONFIG_HARDLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
CONFIG_SCHED_DEBUG=y
CONFIG_SCHED_INFO=y
CONFIG_SCHEDSTATS=y
# end of Scheduler Debugging

# CONFIG_DEBUG_TIMEKEEPING is not set

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

# CONFIG_DEBUG_IRQFLAGS is not set
CONFIG_STACKTRACE=y
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set

#
# Debug kernel data structures
#
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# CONFIG_DEBUG_MAPLE_TREE is not set
# end of Debug kernel data structures

# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
# CONFIG_RCU_SCALE_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=60
# CONFIG_BOOTPARAM_RCU_STALL_PANIC is not set
CONFIG_BOOTPARAM_RCU_STALL_PANIC_VALUE=0
CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
CONFIG_RCU_TRACE=y
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
# CONFIG_LATENCYTOP is not set
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_TRACING=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_BOOTTIME_TRACING is not set
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_HWLAT_TRACER is not set
# CONFIG_OSNOISE_TRACER is not set
# CONFIG_TIMERLAT_TRACER is not set
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
# CONFIG_FTRACE_SYSCALLS is not set
# CONFIG_TRACER_SNAPSHOT is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_KPROBE_EVENTS=y
CONFIG_UPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_DYNAMIC_EVENTS=y
CONFIG_PROBE_EVENTS=y
# CONFIG_SYNTH_EVENTS is not set
# CONFIG_HIST_TRIGGERS is not set
# CONFIG_TRACE_EVENT_INJECT is not set
# CONFIG_TRACEPOINT_BENCHMARK is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_TRACE_EVAL_MAP_FILE is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
# CONFIG_KPROBE_EVENT_GEN_TEST is not set
# CONFIG_RV is not set
# CONFIG_SAMPLES is not set
# CONFIG_STRICT_DEVMEM is not set

#
# arm64 Debugging
#
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_DEBUG_EFI is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
# end of arm64 Debugging

#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FUNCTION_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_LKDTM is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_DIV64 is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TEST_REF_TRACKER is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_ASYNC_RAID6_TEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_STRING_SELFTEST is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_STRSCPY is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_SCANF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_MAPLE_TREE is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_SIPHASH is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_PARMAN is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_VMALLOC is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_BPF is not set
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_DYNAMIC_DEBUG is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_OBJAGG is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_FREE_PAGES is not set
CONFIG_ARCH_USE_MEMTEST=y
CONFIG_MEMTEST=y
# end of Kernel Testing and Coverage

#
# Rust hacking
#
# end of Rust hacking
# end of Kernel hacking


================================================
FILE: kernel-config/release/stable/config-5.10
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 5.10.252 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 15.2.Rel1 (Build arm-15.86)) 15.2.1 20251203"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=150201
CONFIG_LD_VERSION=245010000
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=24501
CONFIG_LLD_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_UAPI_HEADER_TEST is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
# CONFIG_WATCH_QUEUE is not set
# CONFIG_CROSS_MEMORY_ATTACH is not set
# CONFIG_USELIB is not set
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem

CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_HZ_PERIODIC=y
# CONFIG_NO_HZ_IDLE is not set
# CONFIG_NO_HZ_FULL is not set
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_PREEMPTION=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_SCHED_THERMAL_PRESSURE=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
CONFIG_PREEMPT_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_TASKS_RCU=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
# CONFIG_UCLAMP_TASK is not set
# end of Scheduler features

CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_CC_HAS_INT128=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
CONFIG_MEMCG=y
CONFIG_MEMCG_SWAP=y
CONFIG_MEMCG_KMEM=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
# CONFIG_CHECKPOINT_RESTORE is not set
CONFIG_SCHED_AUTOGROUP=y
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_BPF=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_PRINTK_NMI=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_HAVE_FUTEX_CMPXCHG=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_BPF_SYSCALL=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
CONFIG_BPF_JIT_DEFAULT_ON=y
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
# CONFIG_BPF_PRELOAD is not set
# CONFIG_USERFAULTFD is not set
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
CONFIG_SLUB_MEMCG_SYSFS_ON=y
# CONFIG_COMPAT_BRK is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
CONFIG_SLAB_FREELIST_RANDOM=y
CONFIG_SLAB_FREELIST_HARDENED=y
CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
CONFIG_SLUB_CPU_PARTIAL=y
CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
# end of General setup

CONFIG_ARM64=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_CONT_PTE_SHIFT=4
CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ZONE_DMA=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y

#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
# CONFIG_ARCH_AGILEX is not set
CONFIG_ARCH_SUNXI=y
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_BCM2835 is not set
# CONFIG_ARCH_BCM_IPROC is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
# CONFIG_ARCH_BRCMSTB is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SPARX5 is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LAYERSCAPE is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_KEEMBAY is not set
# CONFIG_ARCH_MEDIATEK is not set
CONFIG_ARCH_MESON=y
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_RENESAS is not set
CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_S32 is not set
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_STRATIX10 is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZX is not set
# CONFIG_ARCH_ZYNQMP is not set
# end of Platform selection

#
# Kernel Features
#

#
# ARM errata workarounds via the alternatives framework
#
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_834220=y
CONFIG_ARM64_ERRATUM_1742098=y
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1319367=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_ARM64_ERRATUM_2457168=y
CONFIG_ARM64_ERRATUM_3194386=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
CONFIG_QCOM_FALKOR_ERRATUM_1009=y
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
# end of ARM errata workarounds via the alternatives framework

CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
CONFIG_ARM64_VA_BITS_39=y
# CONFIG_ARM64_VA_BITS_48 is not set
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SCHED_MC=y
# CONFIG_SCHED_SMT is not set
CONFIG_NR_CPUS=8
# CONFIG_HOTPLUG_CPU is not set
# CONFIG_NUMA is not set
CONFIG_HOLES_IN_ZONE=y
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
CONFIG_HZ_300=y
# CONFIG_HZ_1000 is not set
CONFIG_HZ=300
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_KEXEC_FILE is not set
# CONFIG_CRASH_DUMP is not set
# CONFIG_XEN is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y

#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
CONFIG_AS_HAS_LSE_ATOMICS=y
# CONFIG_ARM64_USE_LSE_ATOMICS is not set
CONFIG_ARM64_VHE=y
# end of ARMv8.1 architectural features

#
# ARMv8.2 architectural features
#
CONFIG_ARM64_UAO=y
# CONFIG_ARM64_PMEM is not set
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features

#
# ARMv8.3 architectural features
#
CONFIG_ARM64_PTR_AUTH=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
CONFIG_AS_HAS_PAC=y
CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
# end of ARMv8.3 architectural features

#
# ARMv8.4 architectural features
#
CONFIG_ARM64_AMU_EXTN=y
CONFIG_AS_HAS_ARMV8_4=y
CONFIG_ARM64_TLB_RANGE=y
# end of ARMv8.4 architectural features

#
# ARMv8.5 architectural features
#
CONFIG_ARM64_BTI=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARCH_RANDOM=y
CONFIG_ARM64_AS_HAS_MTE=y
CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features

CONFIG_ARM64_SVE=y
CONFIG_ARM64_MODULE_PLTS=y
CONFIG_ARM64_PSEUDO_NMI=y
# CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
# end of Kernel Features

#
# Boot options
#
CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
CONFIG_CMDLINE=""
CONFIG_EFI_STUB=y
CONFIG_EFI=y
CONFIG_DMI=y
# end of Boot options

CONFIG_SYSVIPC_COMPAT=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
CONFIG_ARCH_ENABLE_THP_MIGRATION=y

#
# Power management options
#
# CONFIG_SUSPEND is not set
# CONFIG_HIBERNATION is not set
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options

#
# CPU Power Management
#

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_IDLE_GOV_LADDER=y
# CONFIG_CPU_IDLE_GOV_MENU is not set
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_DT_IDLE_STATES=y

#
# ARM CPU Idle Drivers
#
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
# end of ARM CPU Idle Drivers
# end of CPU Idle

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_STAT is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_USERSPACE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
# CONFIG_ACPI_CPPC_CPUFREQ is not set
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_SCMI_CPUFREQ=y
# end of CPU Frequency scaling
# end of CPU Power Management

#
# Firmware Drivers
#
CONFIG_ARM_SCMI_PROTOCOL=y
CONFIG_ARM_SCMI_POWER_DOMAIN=y
CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
CONFIG_ARM_SDE_INTERFACE=y
# CONFIG_FIRMWARE_MEMMAP is not set
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=m
# CONFIG_ISCSI_IBFT is not set
# CONFIG_FW_CFG_SYSFS is not set
# CONFIG_GOOGLE_FIRMWARE is not set

#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_VARS_PSTORE=y
# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_GENERIC_STUB=y
CONFIG_EFI_ARMSTUB_DTB_LOADER=y
CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
CONFIG_EFI_BOOTLOADER_CONTROL=m
CONFIG_EFI_CAPSULE_LOADER=m
CONFIG_EFI_TEST=m
# CONFIG_RESET_ATTACK_MITIGATION is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
# end of EFI (Extensible Firmware Interface) Support

CONFIG_UEFI_CPER=y
CONFIG_UEFI_CPER_ARM=y
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
CONFIG_MESON_SM=y
CONFIG_ARM_PSCI_FW=y
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_ARM_SMCCC_SOC_ID=y

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_GENERIC_GSI=y
CONFIG_ACPI_CCA_REQUIRED=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
# CONFIG_ACPI_EC_DEBUGFS is not set
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_MCFG=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_THERMAL=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_PCI_SLOT=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_CUSTOM_METHOD=y
CONFIG_ACPI_BGRT=y
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
CONFIG_HAVE_ACPI_APEI=y
CONFIG_ACPI_APEI=y
CONFIG_ACPI_APEI_GHES=y
CONFIG_ACPI_APEI_SEA=y
CONFIG_ACPI_APEI_MEMORY_FAILURE=y
CONFIG_ACPI_APEI_EINJ=m
CONFIG_ACPI_APEI_ERST_DEBUG=m
CONFIG_ACPI_CONFIGFS=m
CONFIG_ACPI_IORT=y
CONFIG_ACPI_GTDT=y
CONFIG_ACPI_PPTT=y
CONFIG_PMIC_OPREGION=y
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_MMIO=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_KVM_ARM_PMU=y
CONFIG_ARM64_CRYPTO=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64_CE=y
CONFIG_CRYPTO_SHA3_ARM64=y
CONFIG_CRYPTO_SM3_ARM64_CE=y
CONFIG_CRYPTO_SM4_ARM64_CE=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_CHACHA20_NEON=y
CONFIG_CRYPTO_POLY1305_NEON=y
CONFIG_CRYPTO_NHPOLY1305_NEON=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CPU_MITIGATIONS=y

#
# General architecture-dependent options
#
CONFIG_SET_FS=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BLK_CGROUP_RWSTAT=y
CONFIG_BLK_DEV_BSG=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=y
# CONFIG_BLK_DEV_ZONED is not set
CONFIG_BLK_DEV_THROTTLING=y
# CONFIG_BLK_DEV_THROTTLING_LOW is not set
CONFIG_BLK_CMDLINE_PARSER=y
CONFIG_BLK_WBT=y
# CONFIG_BLK_CGROUP_IOLATENCY is not set
# CONFIG_BLK_CGROUP_IOCOST is not set
CONFIG_BLK_WBT_MQ=y
# CONFIG_BLK_DEBUG_FS is not set
# CONFIG_BLK_SED_OPAL is not set
# CONFIG_BLK_INLINE_ENCRYPTION is not set

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_AIX_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
CONFIG_CMDLINE_PARTITION=y
# end of Partition Types

CONFIG_BLOCK_COMPAT=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
# CONFIG_BFQ_CGROUP_DEBUG is not set
# end of IO Schedulers

CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_HAVE_ELF_PROT=y
CONFIG_ARCH_USE_GNU_PROPERTY=y
CONFIG_ELFCORE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=m
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_SELECT_MEMORY_MODEL=y
# CONFIG_FLATMEM_MANUAL is not set
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_BOUNCE=y
CONFIG_MMU_NOTIFIER=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
CONFIG_MEMORY_FAILURE=y
# CONFIG_HWPOISON_INJECT is not set
CONFIG_TRANSPARENT_HUGEPAGE=y
# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set
CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
CONFIG_CLEANCACHE=y
CONFIG_FRONTSWAP=y
CONFIG_CMA=y
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
CONFIG_CMA_AREAS=7
CONFIG_ZSWAP=y
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
CONFIG_ZSWAP_DEFAULT_ON=y
CONFIG_ZPOOL=y
CONFIG_ZBUD=y
CONFIG_Z3FOLD=y
CONFIG_ZSMALLOC=y
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_FRAME_VECTOR=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_BENCHMARK is not set
# CONFIG_READ_ONLY_THP_FOR_FS is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
# end of Memory Management options

CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_EXTENSIONS=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_UNIX_SCM=y
CONFIG_UNIX_DIAG=y
CONFIG_TLS=m
# CONFIG_TLS_DEVICE is not set
# CONFIG_TLS_TOE is not set
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
CONFIG_XFRM_INTERFACE=m
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_AH=y
CONFIG_XFRM_ESP=y
CONFIG_XFRM_IPCOMP=y
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_XFRM_ESPINTCP=y
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
# CONFIG_IP_FIB_TRIE_STATS is not set
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_ROUTE_CLASSID=y
# CONFIG_IP_PNP is not set
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=y
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=y
CONFIG_NET_FOU=y
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
CONFIG_INET_ESP_OFFLOAD=m
# CONFIG_INET_ESPINTCP is not set
CONFIG_INET_IPCOMP=y
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=y
CONFIG_INET_TUNNEL=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
CONFIG_INET_UDP_DIAG=y
CONFIG_INET_RAW_DIAG=y
# CONFIG_INET_DIAG_DESTROY is not set
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_NV=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_CONG_DCTCP=m
CONFIG_TCP_CONG_CDG=m
CONFIG_TCP_CONG_BBR=m
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_ESP_OFFLOAD=m
CONFIG_INET6_ESPINTCP=y
CONFIG_INET6_IPCOMP=y
CONFIG_IPV6_MIP6=m
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=y
CONFIG_INET6_TUNNEL=y
CONFIG_IPV6_VTI=m
CONFIG_IPV6_SIT=y
# CONFIG_IPV6_SIT_6RD is not set
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=y
CONFIG_IPV6_GRE=m
CONFIG_IPV6_FOU=y
CONFIG_IPV6_FOU_TUNNEL=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
CONFIG_IPV6_SEG6_LWTUNNEL=y
CONFIG_IPV6_SEG6_HMAC=y
CONFIG_IPV6_SEG6_BPF=y
CONFIG_IPV6_RPL_LWTUNNEL=y
# CONFIG_NETLABEL is not set
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=y
CONFIG_MPTCP_IPV6=y
CONFIG_NETWORK_SECMARK=y
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_NETLINK=m
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
CONFIG_NETFILTER_NETLINK_ACCT=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NETFILTER_NETLINK_OSF=m
CONFIG_NF_CONNTRACK=y
CONFIG_NF_LOG_COMMON=m
CONFIG_NF_LOG_NETDEV=m
CONFIG_NETFILTER_CONNCOUNT=m
CONFIG_NF_CONNTRACK_MARK=y
# CONFIG_NF_CONNTRACK_SECMARK is not set
CONFIG_NF_CONNTRACK_ZONES=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y
CONFIG_NF_CONNTRACK_TIMEOUT=y
CONFIG_NF_CONNTRACK_TIMESTAMP=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_CT_NETLINK_TIMEOUT=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=m
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=m
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_COUNTER=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_OBJREF=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
CONFIG_NFT_OSF=m
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NF_DUP_NETDEV=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XTABLES=m

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=m
CONFIG_NETFILTER_XT_CONNMARK=m
CONFIG_NETFILTER_XT_SET=m

#
# Xtables targets
#
# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LED=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=m
CONFIG_NETFILTER_XT_TARGET_NETMAP=m
CONFIG_NETFILTER_XT_TARGET_FULLCONENAT=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD=m
CONFIG_NETFILTER_XT_TARGET_RATEEST=m
CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=m
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# end of Core Netfilter Configuration

CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
# CONFIG_IP_VS_DEBUG is not set
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_SOCKET_IPV4=m
CONFIG_NF_TPROXY_IPV4=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=m
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_FULLCONENAT=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
# CONFIG_IP_NF_SECURITY is not set
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
# CONFIG_IP6_NF_SECURITY is not set
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=y
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_NFT_BRIDGE_META=m
CONFIG_NFT_BRIDGE_REJECT=m
# CONFIG_NF_LOG_BRIDGE is not set
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
# CONFIG_BPFILTER is not set
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m

#
# DCCP CCIDs Configuration
#
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
CONFIG_IP_DCCP_CCID3=y
# CONFIG_IP_DCCP_CCID3_DEBUG is not set
CONFIG_IP_DCCP_TFRC_LIB=y
# end of DCCP CCIDs Configuration

#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
# end of DCCP Kernel Hacking

CONFIG_IP_SCTP=m
CONFIG_SCTP_DBG_OBJCNT=y
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=m
CONFIG_RDS=m
CONFIG_RDS_TCP=m
# CONFIG_RDS_DEBUG is not set
CONFIG_TIPC=m
CONFIG_TIPC_MEDIA_UDP=y
CONFIG_TIPC_CRYPTO=y
CONFIG_TIPC_DIAG=m
# CONFIG_ATM is not set
CONFIG_L2TP=m
CONFIG_L2TP_DEBUGFS=m
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=m
CONFIG_L2TP_ETH=m
CONFIG_STP=y
CONFIG_GARP=y
CONFIG_MRP=y
CONFIG_BRIDGE=m
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
# CONFIG_BRIDGE_MRP is not set
CONFIG_HAVE_NET_DSA=y
# CONFIG_NET_DSA is not set
CONFIG_VLAN_8021Q=y
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q_MVRP=y
CONFIG_LLC=y
CONFIG_LLC2=m
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
CONFIG_6LOWPAN=m
# CONFIG_6LOWPAN_DEBUGFS is not set
CONFIG_6LOWPAN_NHC=m
CONFIG_6LOWPAN_NHC_DEST=m
CONFIG_6LOWPAN_NHC_FRAGMENT=m
CONFIG_6LOWPAN_NHC_HOP=m
CONFIG_6LOWPAN_NHC_IPV6=m
CONFIG_6LOWPAN_NHC_MOBILITY=m
CONFIG_6LOWPAN_NHC_ROUTING=m
CONFIG_6LOWPAN_NHC_UDP=m
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
CONFIG_6LOWPAN_GHC_UDP=m
CONFIG_6LOWPAN_GHC_ICMPV6=m
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
CONFIG_IEEE802154=m
CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_MAC802154=m
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFB=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_SKBPRIO=m
CONFIG_NET_SCH_CHOKE=m
CONFIG_NET_SCH_QFQ=m
CONFIG_NET_SCH_CODEL=m
CONFIG_NET_SCH_FQ_CODEL=y
CONFIG_NET_SCH_CAKE=m
CONFIG_NET_SCH_FQ=m
CONFIG_NET_SCH_HHF=m
CONFIG_NET_SCH_PIE=m
# CONFIG_NET_SCH_FQ_PIE is not set
CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_SCH_PLUG=m
# CONFIG_NET_SCH_ETS is not set
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_PERF=y
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=y
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_EMATCH_IPSET=m
CONFIG_NET_EMATCH_IPT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_SAMPLE=m
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
CONFIG_NET_ACT_MPLS=m
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_NET_ACT_CONNMARK=m
CONFIG_NET_ACT_CTINFO=m
CONFIG_NET_ACT_SKBMOD=m
CONFIG_NET_ACT_IFE=m
CONFIG_NET_ACT_TUNNEL_KEY=m
CONFIG_NET_ACT_CT=m
# CONFIG_NET_ACT_GATE is not set
CONFIG_NET_IFE_SKBMARK=m
CONFIG_NET_IFE_SKBPRIO=m
CONFIG_NET_IFE_SKBTCINDEX=m
# CONFIG_NET_TC_SKB_EXT is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=m
CONFIG_BATMAN_ADV=m
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
CONFIG_BATMAN_ADV_NC=y
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUGFS is not set
# CONFIG_BATMAN_ADV_DEBUG is not set
# CONFIG_BATMAN_ADV_SYSFS is not set
# CONFIG_OPENVSWITCH is not set
# CONFIG_VSOCKETS is not set
CONFIG_NETLINK_DIAG=y
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=m
CONFIG_MPLS_ROUTING=m
CONFIG_MPLS_IPTUNNEL=m
CONFIG_NET_NSH=m
CONFIG_HSR=m
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=m
# CONFIG_QRTR_SMD is not set
# CONFIG_QRTR_TUN is not set
CONFIG_QRTR_MHI=m
# CONFIG_NET_NCSI is not set
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_XPS=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_JIT=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
CONFIG_NET_PKTGEN=m
# end of Network testing
# end of Networking options

# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=m
CONFIG_BT_HS=y
CONFIG_BT_LE=y
CONFIG_BT_6LOWPAN=m
CONFIG_BT_LEDS=y
CONFIG_BT_MSFTEXT=y
# CONFIG_BT_DEBUGFS is not set
CONFIG_BT_SELFTEST=y
CONFIG_BT_SELFTEST_ECDH=y
CONFIG_BT_SELFTEST_SMP=y

#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=m
CONFIG_BT_BCM=m
CONFIG_BT_RTL=m
CONFIG_BT_QCA=m
CONFIG_BT_HCIBTUSB=m
# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
CONFIG_BT_HCIBTUSB_BCM=y
CONFIG_BT_HCIBTUSB_MTK=y
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_NOKIA=m
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_BCM=y
CONFIG_BT_HCIUART_RTL=y
CONFIG_BT_HCIUART_QCA=y
CONFIG_BT_HCIUART_AG6XX=y
CONFIG_BT_HCIUART_MRVL=y
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
CONFIG_BT_MTKSDIO=m
CONFIG_BT_MTKUART=m
CONFIG_BT_HCIRSI=m
# end of Bluetooth device drivers

CONFIG_AF_RXRPC=m
# CONFIG_AF_RXRPC_IPV6 is not set
# CONFIG_AF_RXRPC_INJECT_LOSS is not set
# CONFIG_AF_RXRPC_DEBUG is not set
# CONFIG_RXKAD is not set
CONFIG_AF_KCM=m
CONFIG_STREAM_PARSER=y
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
CONFIG_CFG80211_CERTIFICATION_ONUS=y
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_EXTRA_REGDB_KEYDIR=""
CONFIG_CFG80211_REG_CELLULAR_HINTS=y
CONFIG_CFG80211_REG_RELAX_NO_IR=y
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
# CONFIG_CFG80211_WEXT is not set
CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
CONFIG_LIB80211_DEBUG=y
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
# CONFIG_WIMAX is not set
CONFIG_RFKILL=m
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=m
CONFIG_NET_9P=m
CONFIG_NET_9P_VIRTIO=m
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
CONFIG_CEPH_LIB=m
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
# CONFIG_NFC is not set
CONFIG_PSAMPLE=m
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
CONFIG_FAILOVER=y
CONFIG_ETHTOOL_NETLINK=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_SHORTCUT_FE=y

#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
# CONFIG_PCIEPORTBUS is not set
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIE_PTM is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_STUB is not set
CONFIG_PCI_ECAM=y
# CONFIG_PCI_IOV is not set
# CONFIG_PCI_PRI is not set
# CONFIG_PCI_PASID is not set
CONFIG_PCI_LABEL=y
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
# CONFIG_HOTPLUG_PCI is not set

#
# PCI controller drivers
#
# CONFIG_PCI_FTPCI100 is not set
# CONFIG_PCI_HOST_GENERIC is not set
# CONFIG_PCIE_XILINX is not set
# CONFIG_PCI_XGENE is not set
# CONFIG_PCIE_ALTERA is not set
# CONFIG_PCI_HOST_THUNDER_PEM is not set
# CONFIG_PCI_HOST_THUNDER_ECAM is not set
CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_HOST=y
# CONFIG_PCIE_HISI_ERR is not set

#
# DesignWare PCI Core Support
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
# CONFIG_PCI_HISI is not set
# CONFIG_PCIE_KIRIN is not set
CONFIG_PCI_MESON=y
# CONFIG_PCIE_AL is not set
# end of DesignWare PCI Core Support

#
# Mobiveil PCIe Core Support
#
# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set
# end of Mobiveil PCIe Core Support

#
# Cadence PCIe controllers support
#
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCI_J721E_HOST is not set
# end of Cadence PCIe controllers support
# end of PCI controller drivers

#
# PCI Endpoint
#
# CONFIG_PCI_ENDPOINT is not set
# end of PCI Endpoint

#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set
# end of PCI switch controller drivers

# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_FW_LOADER_USER_HELPER is not set
# CONFIG_FW_LOADER_COMPRESS is not set
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SCCB=m
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
CONFIG_BRCMSTB_GISB_ARB=y
# CONFIG_MOXTET is not set
CONFIG_SIMPLE_PM_BUS=y
CONFIG_SUN50I_DE2_BUS=y
CONFIG_SUNXI_RSB=y
CONFIG_VEXPRESS_CONFIG=y
CONFIG_MHI_BUS=m
# CONFIG_MHI_BUS_DEBUG is not set
CONFIG_MHI_BUS_PCI_GENERIC=m
# end of Bus devices

CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
CONFIG_GNSS=m
CONFIG_GNSS_SERIAL=m
CONFIG_GNSS_MTK_SERIAL=m
CONFIG_GNSS_SIRF_SERIAL=m
CONFIG_GNSS_UBX_SERIAL=m
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_AFS_PARTS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_DATAFLASH is not set
CONFIG_MTD_MCHP23K256=m
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
# CONFIG_MTD_SPI_NAND is not set

#
# ECC engine support
#
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
# CONFIG_MTD_UBI_BLOCK is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_NET=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_NULL_BLK is not set
CONFIG_CDROM=m
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
CONFIG_ZRAM=m
CONFIG_ZRAM_WRITEBACK=y
CONFIG_ZRAM_MEMORY_TRACKING=y
# CONFIG_BLK_DEV_UMEM is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=128
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
CONFIG_BLK_DEV_DRBD=m
CONFIG_DRBD_FAULT_INJECTION=y
CONFIG_BLK_DEV_NBD=m
# CONFIG_BLK_DEV_SKD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_VIRTIO_BLK=m
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_RSXX is not set

#
# NVME Support
#
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
# CONFIG_NVME_MULTIPATH is not set
CONFIG_NVME_HWMON=y
CONFIG_NVME_FABRICS=m
# CONFIG_NVME_FC is not set
CONFIG_NVME_TCP=m
CONFIG_NVME_TARGET=m
# CONFIG_NVME_TARGET_PASSTHRU is not set
CONFIG_NVME_TARGET_LOOP=m
# CONFIG_NVME_TARGET_FC is not set
CONFIG_NVME_TARGET_TCP=m
# end of NVME Support

#
# Misc devices
#
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
CONFIG_TIFM_CORE=m
CONFIG_TIFM_7XX1=m
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_XILINX_SDFEC is not set
CONFIG_MISC_RTSX=m
# CONFIG_PVPANIC is not set
# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
CONFIG_EEPROM_AT25=m
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
CONFIG_EEPROM_93CX6=m
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

CONFIG_CB710_CORE=m
# CONFIG_CB710_DEBUG is not set
CONFIG_CB710_DEBUG_ASSUMPTIONS=y

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline

# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_MISC_ALCOR_PCI is not set
# CONFIG_MISC_RTSX_PCI is not set
CONFIG_MISC_RTSX_USB=m
# CONFIG_HABANA_AI is not set
# CONFIG_UACCE is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=m
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=m
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_ISCSI_BOOT_SYSFS=m
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_FDOMAIN_PCI is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
CONFIG_SCSI_VIRTIO=m
# CONFIG_SCSI_DH is not set
# end of SCSI device support

CONFIG_HAVE_PATA_PLATFORM=y
CONFIG_ATA=m
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=m
CONFIG_SATA_MOBILE_LPM_POLICY=0
# CONFIG_SATA_AHCI_PLATFORM is not set
# CONFIG_AHCI_CEVA is not set
CONFIG_AHCI_SUNXI=m
# CONFIG_AHCI_QORIQ is not set
# CONFIG_SATA_INIC162X is not set
# CONFIG_SATA_ACARD_AHCI is not set
# CONFIG_SATA_SIL24 is not set
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#
# CONFIG_PDC_ADMA is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_SATA_SX4 is not set
CONFIG_ATA_BMDMA=y

#
# SATA SFF controllers with BMDMA
#
# CONFIG_ATA_PIIX is not set
# CONFIG_SATA_DWC is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_NV is not set
# CONFIG_SATA_PROMISE is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIS is not set
# CONFIG_SATA_SVW is not set
# CONFIG_SATA_ULI is not set
# CONFIG_SATA_VIA is not set
# CONFIG_SATA_VITESSE is not set

#
# PATA SFF controllers with BMDMA
#
# CONFIG_PATA_ALI is not set
# CONFIG_PATA_AMD is not set
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_ATP867X is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CYPRESS is not set
# CONFIG_PATA_EFAR is not set
# CONFIG_PATA_HPT366 is not set
# CONFIG_PATA_HPT37X is not set
# CONFIG_PATA_HPT3X2N is not set
# CONFIG_PATA_HPT3X3 is not set
# CONFIG_PATA_IT8213 is not set
# CONFIG_PATA_IT821X is not set
# CONFIG_PATA_JMICRON is not set
# CONFIG_PATA_MARVELL is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_OPTIDMA is not set
# CONFIG_PATA_PDC2027X is not set
# CONFIG_PATA_PDC_OLD is not set
# CONFIG_PATA_RADISYS is not set
# CONFIG_PATA_RDC is not set
# CONFIG_PATA_SCH is not set
# CONFIG_PATA_SERVERWORKS is not set
# CONFIG_PATA_SIL680 is not set
# CONFIG_PATA_SIS is not set
# CONFIG_PATA_TOSHIBA is not set
# CONFIG_PATA_TRIFLEX is not set
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set

#
# PIO-only SFF controllers
#
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_PLATFORM is not set
# CONFIG_PATA_RZ1000 is not set

#
# Generic fallback / legacy drivers
#
# CONFIG_PATA_ACPI is not set
# CONFIG_ATA_GENERIC is not set
# CONFIG_PATA_LEGACY is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
CONFIG_MD_CLUSTER=m
CONFIG_BCACHE=m
# CONFIG_BCACHE_DEBUG is not set
# CONFIG_BCACHE_CLOSURES_DEBUG is not set
# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=m
# CONFIG_DM_DEBUG is not set
CONFIG_DM_BUFIO=m
# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
CONFIG_DM_CACHE=m
CONFIG_DM_CACHE_SMQ=m
CONFIG_DM_WRITECACHE=m
# CONFIG_DM_EBS is not set
# CONFIG_DM_ERA is not set
# CONFIG_DM_CLONE is not set
CONFIG_DM_MIRROR=m
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
# CONFIG_DM_MULTIPATH_HST is not set
CONFIG_DM_DELAY=m
# CONFIG_DM_DUST is not set
# CONFIG_DM_UEVENT is not set
CONFIG_DM_FLAKEY=m
CONFIG_DM_VERITY=m
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
# CONFIG_DM_VERITY_FEC is not set
# CONFIG_DM_SWITCH is not set
CONFIG_DM_LOG_WRITES=m
CONFIG_DM_INTEGRITY=m
CONFIG_TARGET_CORE=m
CONFIG_TCM_IBLOCK=m
CONFIG_TCM_FILEIO=m
CONFIG_TCM_PSCSI=m
# CONFIG_LOOPBACK_TARGET is not set
CONFIG_ISCSI_TARGET=m
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
# end of IEEE 1394 (FireWire) support

CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_WIREGUARD=m
# CONFIG_WIREGUARD_DEBUG is not set
CONFIG_EQUALIZER=m
# CONFIG_NET_FC is not set
CONFIG_IFB=m
CONFIG_NET_TEAM=m
CONFIG_NET_TEAM_MODE_BROADCAST=m
CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
CONFIG_NET_TEAM_MODE_RANDOM=m
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
CONFIG_NET_TEAM_MODE_LOADBALANCE=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=m
CONFIG_IPVTAP=m
CONFIG_VXLAN=m
CONFIG_GENEVE=m
CONFIG_BAREUDP=m
CONFIG_GTP=m
CONFIG_MACSEC=m
CONFIG_NETCONSOLE=m
CONFIG_NETCONSOLE_DYNAMIC=y
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=m
CONFIG_TAP=m
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_NLMON=m
CONFIG_NET_VRF=m
# CONFIG_ARCNET is not set

#
# Distributed Switch Architecture drivers
#
# end of Distributed Switch Architecture drivers

CONFIG_ETHERNET=y
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
CONFIG_NET_VENDOR_ALLWINNER=y
CONFIG_SUN4I_EMAC=y
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_ALTERA_TSE is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_ATHEROS is not set
# CONFIG_NET_VENDOR_AURORA is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_BROCADE is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_DNET is not set
# CONFIG_NET_VENDOR_DEC is not set
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_FREESCALE is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_JME is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_FEALNX is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETERION is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCA7000_UART is not set
# CONFIG_QCOM_EMAC is not set
CONFIG_SFE_SUPPORT_IPV6=y
CONFIG_FAST_CLASSIFIER=y
CONFIG_SFE_ECM=y
# CONFIG_RMNET is not set
# CONFIG_NET_VENDOR_RDC is not set
# CONFIG_NET_VENDOR_REALTEK is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_SELFTESTS=y
CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_MESON=y
CONFIG_DWMAC_ROCKCHIP=y
CONFIG_DWMAC_SUNXI=y
CONFIG_DWMAC_SUN8I=y
# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_NET_SB1000 is not set
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_FIXED_PHY=y
# CONFIG_SFP is not set

#
# MII PHY device drivers
#
# CONFIG_AMD_PHY is not set
CONFIG_MESON_GXL_PHY=y
# CONFIG_ADIN_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
# CONFIG_AX88796B_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM54140_PHY is not set
# CONFIG_BCM7XXX_PHY is not set
# CONFIG_BCM84881_PHY is not set
# CONFIG_BCM87XX_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
CONFIG_ICPLUS_PHY=m
CONFIG_JLSEMI_PHY=y
# CONFIG_LXT_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MICREL_PHY is not set
CONFIG_MICROCHIP_PHY=m
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
# CONFIG_NATIONAL_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
# CONFIG_AT803X_PHY is not set
# CONFIG_QSEMI_PHY is not set
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
CONFIG_SMSC_PHY=m
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
# CONFIG_DP83869_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_XILINX_GMII2RGMII is not set
CONFIG_MICREL_KS8995MA=m
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_OF_MDIO=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_SUN4I=y
CONFIG_MDIO_BITBANG=m
CONFIG_MDIO_BCM_UNIMAC=m
CONFIG_MDIO_CAVIUM=m
CONFIG_MDIO_GPIO=m
CONFIG_MDIO_HISI_FEMAC=m
CONFIG_MDIO_MVUSB=m
CONFIG_MDIO_MSCC_MIIM=m
CONFIG_MDIO_OCTEON=m
CONFIG_MDIO_IPQ4019=m
CONFIG_MDIO_IPQ8064=m
CONFIG_MDIO_THUNDER=m

#
# MDIO Multiplexers
#
CONFIG_MDIO_BUS_MUX=y
CONFIG_MDIO_BUS_MUX_MESON_G12A=y
CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y

#
# PCS device drivers
#
CONFIG_PCS_XPCS=y
# end of PCS device drivers

CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=m
# CONFIG_PPTP is not set
# CONFIG_PPPOL2TP is not set
CONFIG_PPP_ASYNC=m
# CONFIG_PPP_SYNC_TTY is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=m
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_AX8817X=m
CONFIG_USB_NET_AX88179_178A=m
CONFIG_USB_NET_CDCETHER=m
CONFIG_USB_NET_CDC_EEM=m
CONFIG_USB_NET_CDC_NCM=m
CONFIG_USB_NET_HUAWEI_CDC_NCM=m
CONFIG_USB_NET_CDC_MBIM=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9700=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
CONFIG_USB_NET_CDC_SUBSET=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
CONFIG_USB_EPSON2888=y
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=m
CONFIG_USB_NET_CX82310_ETH=m
CONFIG_USB_NET_KALMIA=m
CONFIG_USB_NET_QMI_WWAN=m
CONFIG_USB_HSO=m
CONFIG_USB_NET_INT51X1=m
CONFIG_USB_IPHETH=m
CONFIG_USB_SIERRA_NET=m
CONFIG_USB_VL600=m
CONFIG_USB_NET_CH9200=m
CONFIG_USB_NET_AQC111=m
CONFIG_WLAN=y
# CONFIG_WIRELESS_WDS is not set
# CONFIG_WLAN_VENDOR_ADMTEK is not set
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
# CONFIG_ATH_DEBUG is not set
# CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS is not set
# CONFIG_ATH5K is not set
# CONFIG_ATH5K_PCI is not set
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=m
CONFIG_ATH9K_PCI=y
CONFIG_ATH9K_AHB=y
# CONFIG_ATH9K_DEBUGFS is not set
CONFIG_ATH9K_DFS_CERTIFIED=y
CONFIG_ATH9K_DYNACK=y
# CONFIG_ATH9K_WOW is not set
CONFIG_ATH9K_RFKILL=y
CONFIG_ATH9K_CHANNEL_CONTEXT=y
# CONFIG_ATH9K_PCOEM is not set
# CONFIG_ATH9K_PCI_NO_EEPROM is not set
CONFIG_ATH9K_HTC=m
# CONFIG_ATH9K_HTC_DEBUGFS is not set
CONFIG_ATH9K_HWRNG=y
CONFIG_CARL9170=m
CONFIG_CARL9170_LEDS=y
CONFIG_CARL9170_WPC=y
CONFIG_CARL9170_HWRNG=y
CONFIG_ATH6KL=m
CONFIG_ATH6KL_SDIO=m
CONFIG_ATH6KL_USB=m
# CONFIG_ATH6KL_DEBUG is not set
CONFIG_ATH6KL_REGDOMAIN=y
CONFIG_AR5523=m
# CONFIG_WIL6210 is not set
CONFIG_ATH10K=m
CONFIG_ATH10K_CE=y
# CONFIG_ATH10K_PCI is not set
CONFIG_ATH10K_SDIO=m
CONFIG_ATH10K_USB=m
# CONFIG_ATH10K_DEBUG is not set
# CONFIG_ATH10K_DEBUGFS is not set
CONFIG_ATH10K_DFS_CERTIFIED=y
# CONFIG_WCN36XX is not set
# CONFIG_ATH11K is not set
CONFIG_WLAN_VENDOR_ATMEL=y
# CONFIG_ATMEL is not set
CONFIG_AT76C50X_USB=m
CONFIG_WLAN_VENDOR_BROADCOM=y
# CONFIG_B43 is not set
# CONFIG_B43LEGACY is not set
CONFIG_BRCMUTIL=m
# CONFIG_BRCMSMAC is not set
CONFIG_BRCMFMAC=m
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
# CONFIG_BRCMFMAC_PCIE is not set
CONFIG_BRCMDBG=y
# CONFIG_WLAN_VENDOR_CISCO is not set
# CONFIG_WLAN_VENDOR_INTEL is not set
# CONFIG_WLAN_VENDOR_INTERSIL is not set
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_USB=m
CONFIG_LIBERTAS_SDIO=m
CONFIG_LIBERTAS_SPI=m
# CONFIG_LIBERTAS_DEBUG is not set
CONFIG_LIBERTAS_MESH=y
CONFIG_LIBERTAS_THINFIRM=m
# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
CONFIG_LIBERTAS_THINFIRM_USB=m
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_SDIO=m
# CONFIG_MWIFIEX_PCIE is not set
CONFIG_MWIFIEX_USB=m
# CONFIG_MWL8K is not set
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=m
CONFIG_MT76_CORE=m
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=m
CONFIG_MT76_SDIO=m
CONFIG_MT76x02_LIB=m
CONFIG_MT76x02_USB=m
CONFIG_MT76x0_COMMON=m
CONFIG_MT76x0U=m
# CONFIG_MT76x0E is not set
CONFIG_MT76x2_COMMON=m
# CONFIG_MT76x2E is not set
CONFIG_MT76x2U=m
# CONFIG_MT7603E is not set
CONFIG_MT7615_COMMON=m
# CONFIG_MT7615E is not set
CONFIG_MT7663_USB_SDIO_COMMON=m
CONFIG_MT7663U=m
CONFIG_MT7663S=m
# CONFIG_MT7915E is not set
CONFIG_WLAN_VENDOR_MICROCHIP=y
CONFIG_WILC1000=m
CONFIG_WILC1000_SDIO=m
# CONFIG_WILC1000_SPI is not set
# CONFIG_WILC1000_HW_OOB_INTR is not set
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=m
# CONFIG_RT2400PCI is not set
# CONFIG_RT2500PCI is not set
# CONFIG_RT61PCI is not set
# CONFIG_RT2800PCI is not set
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
CONFIG_RT2800USB_RT33XX=y
CONFIG_RT2800USB_RT35XX=y
CONFIG_RT2800USB_RT3573=y
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
CONFIG_RT2800USB_UNKNOWN=y
CONFIG_RT2800_LIB=m
CONFIG_RT2X00_LIB_USB=m
CONFIG_RT2X00_LIB=m
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
# CONFIG_RT2X00_DEBUG is not set
CONFIG_WLAN_VENDOR_REALTEK=y
# CONFIG_RTL8180 is not set
CONFIG_RTL8187=m
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=m
# CONFIG_RTL8192CE is not set
# CONFIG_RTL8192SE is not set
# CONFIG_RTL8192DE is not set
# CONFIG_RTL8723AE is not set
# CONFIG_RTL8723BE is not set
# CONFIG_RTL8188EE is not set
# CONFIG_RTL8192EE is not set
# CONFIG_RTL8821AE is not set
CONFIG_RTL8192CU=m
CONFIG_RTLWIFI=m
CONFIG_RTLWIFI_USB=m
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8XXXU=m
# CONFIG_RTL8XXXU_UNTESTED is not set
# CONFIG_RTW88 is not set
CONFIG_RTL8188FU=m
CONFIG_RTL8189FS=m
CONFIG_RTL8821CU=m
CONFIG_RTL8822CS=m
CONFIG_WLAN_VENDOR_RSI=y
CONFIG_RSI_91X=m
CONFIG_RSI_DEBUGFS=y
CONFIG_RSI_SDIO=m
CONFIG_RSI_USB=m
CONFIG_RSI_COEX=y
CONFIG_WLAN_VENDOR_ST=y
CONFIG_CW1200=m
CONFIG_CW1200_WLAN_SDIO=m
# CONFIG_CW1200_WLAN_SPI is not set
CONFIG_WLAN_VENDOR_TI=y
CONFIG_WL1251=m
# CONFIG_WL1251_SPI is not set
CONFIG_WL1251_SDIO=m
# CONFIG_WL12XX is not set
# CONFIG_WL18XX is not set
CONFIG_WLCORE=m
CONFIG_WLCORE_SPI=m
CONFIG_WLCORE_SDIO=m
CONFIG_WILINK_PLATFORM_DATA=y
CONFIG_WLAN_VENDOR_ZYDAS=y
CONFIG_USB_ZD1201=m
CONFIG_ZD1211RW=m
# CONFIG_ZD1211RW_DEBUG is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
CONFIG_SPARD_WLAN_SUPPORT=y

#
# UNISOC WCN Device Drivers(for new chip...)
#
# CONFIG_SC23XX is not set
# CONFIG_WCN_BSP_DRIVER_BUILDIN is not set
# CONFIG_RK_WIFI_DEVICE_UWE5621 is not set
# CONFIG_RK_WIFI_DEVICE_UWE5622 is not set
CONFIG_AW_WIFI_DEVICE_UWE5622=y
CONFIG_AW_BIND_VERIFY=y
# end of UNISOC WCN Device Drivers(for new chip...)

CONFIG_WLAN_UWE5622=m
# CONFIG_SPRDWL_NG is not set
CONFIG_UNISOC_WIFI_PS=y
# CONFIG_TTY_OVERY_SDIO is not set
CONFIG_MAC80211_HWSIM=m
CONFIG_USB_NET_RNDIS_WLAN=m
CONFIG_VIRT_WIFI=m

#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
CONFIG_IEEE802154_AT86RF230=m
CONFIG_IEEE802154_AT86RF230_DEBUGFS=y
CONFIG_IEEE802154_MRF24J40=m
CONFIG_IEEE802154_CC2520=m
CONFIG_IEEE802154_ATUSB=m
CONFIG_IEEE802154_ADF7242=m
CONFIG_IEEE802154_CA8210=m
CONFIG_IEEE802154_CA8210_DEBUGFS=y
CONFIG_IEEE802154_MCR20A=m
CONFIG_IEEE802154_HWSIM=m
CONFIG_VMXNET3=m
# CONFIG_FUJITSU_ES is not set
CONFIG_NETDEVSIM=m
CONFIG_NET_FAILOVER=m
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
CONFIG_INPUT_MATRIXKMAP=m

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADC is not set
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_GPIO_BUTTON_HOTPLUG is not set
CONFIG_KEYBOARD_GPIO_POLLED=y
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
CONFIG_KEYBOARD_SUN4I_LRADC=y
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=m
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_SMBUS=y
# CONFIG_MOUSE_SERIAL is not set
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=m
# CONFIG_MOUSE_ELAN_I2C is not set
# CONFIG_MOUSE_VSXXXAA is not set
CONFIG_MOUSE_GPIO=m
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
CONFIG_MOUSE_SYNAPTICS_USB=m
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_ANALOG=m
CONFIG_JOYSTICK_A3D=m
CONFIG_JOYSTICK_ADC=m
CONFIG_JOYSTICK_ADI=m
CONFIG_JOYSTICK_COBRA=m
CONFIG_JOYSTICK_GF2K=m
CONFIG_JOYSTICK_GRIP=m
CONFIG_JOYSTICK_GRIP_MP=m
CONFIG_JOYSTICK_GUILLEMOT=m
CONFIG_JOYSTICK_INTERACT=m
CONFIG_JOYSTICK_SIDEWINDER=m
CONFIG_JOYSTICK_TMDC=m
CONFIG_JOYSTICK_IFORCE=m
CONFIG_JOYSTICK_IFORCE_USB=m
CONFIG_JOYSTICK_IFORCE_232=m
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
CONFIG_JOYSTICK_STINGER=m
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
CONFIG_JOYSTICK_AS5011=m
CONFIG_JOYSTICK_JOYDUMP=m
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_JOYSTICK_PSXPAD_SPI=m
CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
CONFIG_JOYSTICK_PXRC=m
CONFIG_JOYSTICK_FSIA6B=m
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_PROPERTIES=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_AD7877 is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ADC is not set
# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_BU21029 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 is not set
# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_EGALAX is not set
# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
# CONFIG_TOUCHSCREEN_EXC3000 is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GOODIX is not set
# CONFIG_TOUCHSCREEN_HIDEEP is not set
# CONFIG_TOUCHSCREEN_ILI210X is not set
# CONFIG_TOUCHSCREEN_S6SY761 is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_EKTF2127 is not set
# CONFIG_TOUCHSCREEN_ELAN is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
# CONFIG_TOUCHSCREEN_MAX11801 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MMS114 is not set
# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_PIXCIR is not set
# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
# CONFIG_TOUCHSCREEN_WM97XX is not set
CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
# CONFIG_TOUCHSCREEN_TSC2004 is not set
# CONFIG_TOUCHSCREEN_TSC2005 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_RM_TS is not set
# CONFIG_TOUCHSCREEN_SILEAD is not set
# CONFIG_TOUCHSCREEN_SIS_I2C is not set
# CONFIG_TOUCHSCREEN_ST1232 is not set
# CONFIG_TOUCHSCREEN_STMFTS is not set
CONFIG_TOUCHSCREEN_SUN4I=y
# CONFIG_TOUCHSCREEN_SUR40 is not set
# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
# CONFIG_TOUCHSCREEN_SX8654 is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_TOUCHSCREEN_ZET6223 is not set
# CONFIG_TOUCHSCREEN_ZFORCE is not set
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
# CONFIG_TOUCHSCREEN_IQS5XX is not set
# CONFIG_TOUCHSCREEN_ZINITIX is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
# CONFIG_INPUT_BMA150 is not set
# CONFIG_INPUT_E3X0_BUTTON is not set
# CONFIG_INPUT_MMA8450 is not set
CONFIG_INPUT_GPIO_BEEPER=m
# CONFIG_INPUT_GPIO_DECODER is not set
# CONFIG_INPUT_GPIO_VIBRA is not set
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
# CONFIG_INPUT_KXTJ9 is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
CONFIG_INPUT_CM109=m
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
CONFIG_INPUT_AXP20X_PEK=y
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_PWM_BEEPER is not set
# CONFIG_INPUT_PWM_VIBRA is not set
CONFIG_INPUT_RK805_PWRKEY=y
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_INPUT_IQS269A is not set
# CONFIG_INPUT_CMA3000 is not set
# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
# CONFIG_INPUT_DRV260X_HAPTICS is not set
# CONFIG_INPUT_DRV2665_HAPTICS is not set
# CONFIG_INPUT_DRV2667_HAPTICS is not set
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=y
CONFIG_RMI4_SPI=y
CONFIG_RMI4_SMB=y
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=y
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
CONFIG_RMI4_F3A=y
CONFIG_RMI4_F54=y
CONFIG_RMI4_F55=y

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=m
# CONFIG_SERIO_AMBAKMI is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=m
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
CONFIG_SERIO_SUN4I_PS2=y
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
CONFIG_GAMEPORT=m
# CONFIG_GAMEPORT_NS558 is not set
# CONFIG_GAMEPORT_L4 is not set
# CONFIG_GAMEPORT_EMU10K1 is not set
# CONFIG_GAMEPORT_FM801 is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=5
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_RSA is not set
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
CONFIG_SERIAL_AMBA_PL010=y
CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y
CONFIG_SERIAL_MESON=y
CONFIG_SERIAL_MESON_CONSOLE=y
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_QE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_IFX6X60 is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_NOZOMI is not set
# CONFIG_NULL_TTY is not set
# CONFIG_TRACE_SINK is not set
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_TTY_PRINTK is not set
CONFIG_VIRTIO_CONSOLE=m
# CONFIG_IPMI_HANDLER is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=y
# CONFIG_HW_RANDOM_BA431 is not set
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_HISI_V2=y
CONFIG_HW_RANDOM_ROCKCHIP=y
CONFIG_HW_RANDOM_MESON=y
CONFIG_HW_RANDOM_OPTEE=m
# CONFIG_HW_RANDOM_CCTRNG is not set
# CONFIG_HW_RANDOM_XIPHERA is not set
# CONFIG_APPLICOM is not set
CONFIG_DEVMEM=y
CONFIG_RAW_DRIVER=m
CONFIG_MAX_RAW_DEVS=256
CONFIG_DEVPORT=y
# CONFIG_TCG_TPM is not set
# CONFIG_XILLYBUS is not set
# CONFIG_RANDOM_TRUST_CPU is not set
CONFIG_RANDOM_TRUST_BOOTLOADER=y
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_I2C_MUX_GPIO=y
CONFIG_I2C_MUX_GPMUX=y
CONFIG_I2C_MUX_LTC4306=m
CONFIG_I2C_MUX_PCA9541=m
CONFIG_I2C_MUX_PCA954x=m
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_MUX_REG=y
CONFIG_I2C_DEMUX_PINCTRL=y
CONFIG_I2C_MUX_MLXCPLD=m
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_ALGOBIT=y

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set

#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CADENCE is not set
# CONFIG_I2C_CBUS_GPIO is not set
CONFIG_I2C_DESIGNWARE_CORE=y
CONFIG_I2C_DESIGNWARE_SLAVE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_DESIGNWARE_PCI=m
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=y
CONFIG_I2C_GPIO_FAULT_INJECTOR=y
CONFIG_I2C_MESON=y
CONFIG_I2C_MV64XXX=y
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
CONFIG_I2C_RK3X=y
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_THUNDERX is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
# end of I2C Hardware Bus support

# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=m
CONFIG_I2C_SLAVE_TESTUNIT=m
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

# CONFIG_I3C is not set
CONFIG_SPI=y
CONFIG_SPI_DEBUG=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y

#
# SPI Master Controller Drivers
#
CONFIG_SPI_ALTERA=m
CONFIG_SPI_AXI_SPI_ENGINE=m
CONFIG_SPI_BITBANG=m
CONFIG_SPI_CADENCE=m
CONFIG_SPI_CADENCE_QUADSPI=m
CONFIG_SPI_DESIGNWARE=m
CONFIG_SPI_DW_DMA=y
# CONFIG_SPI_DW_PCI is not set
CONFIG_SPI_DW_MMIO=m
# CONFIG_SPI_HISI_SFC_V3XX is not set
CONFIG_SPI_NXP_FLEXSPI=m
CONFIG_SPI_GPIO=m
CONFIG_SPI_FSL_LIB=m
CONFIG_SPI_FSL_SPI=m
CONFIG_SPI_MESON_SPICC=y
CONFIG_SPI_MESON_SPIFC=y
CONFIG_SPI_OC_TINY=m
CONFIG_SPI_PL022=m
CONFIG_SPI_PXA2XX=m
CONFIG_SPI_PXA2XX_PCI=m
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_SC18IS602=m
CONFIG_SPI_SIFIVE=m
CONFIG_SPI_SUN4I=y
CONFIG_SPI_SUN6I=y
CONFIG_SPI_MXIC=m
CONFIG_SPI_THUNDERX=m
CONFIG_SPI_XCOMM=m
CONFIG_SPI_XILINX=m
CONFIG_SPI_ZYNQMP_GQSPI=m
CONFIG_SPI_AMD=m

#
# SPI Multiplexer support
#
CONFIG_SPI_MUX=m

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=m
CONFIG_SPI_LOOPBACK_TEST=m
CONFIG_SPI_TLE62X0=m
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_DYNAMIC=y
CONFIG_SPMI=y
# CONFIG_HSI is not set
# CONFIG_PPS is not set

#
# PTP clock support
#
# CONFIG_PTP_1588_CLOCK is not set

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
CONFIG_PINCTRL_AXP209=y
# CONFIG_PINCTRL_AMD is not set
CONFIG_PINCTRL_MCP23S08_I2C=m
CONFIG_PINCTRL_MCP23S08_SPI=m
CONFIG_PINCTRL_MCP23S08=m
CONFIG_PINCTRL_ROCKCHIP=y
CONFIG_PINCTRL_SINGLE=y
# CONFIG_PINCTRL_SX150X is not set
CONFIG_PINCTRL_STMFX=m
CONFIG_PINCTRL_RK805=y
# CONFIG_PINCTRL_OCELOT is not set

#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers

CONFIG_PINCTRL_SUNXI=y
CONFIG_PINCTRL_SUN4I_A10=y
CONFIG_PINCTRL_SUN5I=y
CONFIG_PINCTRL_SUN6I_A31=y
CONFIG_PINCTRL_SUN6I_A31_R=y
CONFIG_PINCTRL_SUN8I_A23=y
CONFIG_PINCTRL_SUN8I_A33=y
CONFIG_PINCTRL_SUN8I_A83T=y
CONFIG_PINCTRL_SUN8I_A83T_R=y
CONFIG_PINCTRL_SUN8I_A23_R=y
CONFIG_PINCTRL_SUN8I_H3=y
CONFIG_PINCTRL_SUN8I_H3_R=y
CONFIG_PINCTRL_SUN8I_V3S=y
CONFIG_PINCTRL_SUN9I_A80=y
CONFIG_PINCTRL_SUN9I_A80_R=y
CONFIG_PINCTRL_SUN50I_A64=y
CONFIG_PINCTRL_SUN50I_A64_R=y
CONFIG_PINCTRL_SUN50I_A100=y
CONFIG_PINCTRL_SUN50I_A100_R=y
CONFIG_PINCTRL_SUN50I_H5=y
CONFIG_PINCTRL_SUN50I_H6=y
CONFIG_PINCTRL_SUN50I_H6_R=y
CONFIG_PINCTRL_MESON=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_PINCTRL_MESON8_PMX=y
CONFIG_PINCTRL_MESON_AXG=y
CONFIG_PINCTRL_MESON_AXG_PMX=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_PINCTRL_MESON_A1=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_MAX730X=m

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_FTGPIO010 is not set
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_LOGICVC is not set
# CONFIG_GPIO_MB86S7X is not set
CONFIG_GPIO_PL061=y
# CONFIG_GPIO_SAMA5D2_PIOBU is not set
# CONFIG_GPIO_SIFIVE is not set
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_XGENE=y
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
CONFIG_GPIO_ADP5588=m
CONFIG_GPIO_ADNP=m
CONFIG_GPIO_GW_PLD=m
CONFIG_GPIO_MAX7300=m
CONFIG_GPIO_MAX732X=m
CONFIG_GPIO_PCA953X=m
# CONFIG_GPIO_PCA953X_IRQ is not set
# CONFIG_GPIO_PCA9570 is not set
CONFIG_GPIO_PCF857X=m
CONFIG_GPIO_TPIC2810=m
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set
# end of PCI GPIO expanders

#
# SPI GPIO expanders
#
CONFIG_GPIO_74X164=m
CONFIG_GPIO_MAX3191X=m
CONFIG_GPIO_MAX7301=m
CONFIG_GPIO_MC33880=m
CONFIG_GPIO_PISOSR=m
CONFIG_GPIO_XRA1403=m
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
# end of USB GPIO expanders

# CONFIG_GPIO_AGGREGATOR is not set
# CONFIG_GPIO_MOCKUP is not set
CONFIG_W1=m
CONFIG_W1_CON=y

#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_MATROX=m
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
CONFIG_W1_MASTER_DS1WM=m
CONFIG_W1_MASTER_GPIO=m
CONFIG_W1_MASTER_SGI=m
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
CONFIG_W1_SLAVE_DS2405=m
CONFIG_W1_SLAVE_DS2408=m
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
# CONFIG_W1_SLAVE_DS2805 is not set
# CONFIG_W1_SLAVE_DS2430 is not set
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
CONFIG_W1_SLAVE_DS2438=m
CONFIG_W1_SLAVE_DS250X=m
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
CONFIG_W1_SLAVE_DS28E17=m
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_BRCMSTB=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
# CONFIG_POWER_RESET_LTC2952 is not set
CONFIG_POWER_RESET_RESTART=y
# CONFIG_POWER_RESET_VEXPRESS is not set
# CONFIG_POWER_RESET_XGENE is not set
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
# CONFIG_NVMEM_REBOOT_MODE is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_PDA_POWER is not set
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_CHARGER_AXP20X is not set
# CONFIG_BATTERY_AXP20X is not set
CONFIG_AXP20X_POWER=y
# CONFIG_AXP288_FUEL_GAUGE is not set
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_BATTERY_MAX1721X is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
# CONFIG_CHARGER_GPIO is not set
# CONFIG_CHARGER_MANAGER is not set
# CONFIG_CHARGER_LT3651 is not set
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_BQ25980 is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_BATTERY_RT5033 is not set
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
CONFIG_HWMON=y
CONFIG_HWMON_VID=m
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM1177 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7310 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_AS370 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
CONFIG_SENSORS_ARM_SCMI=m
CONFIG_SENSORS_ARM_SCPI=y
CONFIG_SENSORS_ASPEED=m
CONFIG_SENSORS_ATXP1=m
CONFIG_SENSORS_CORSAIR_CPRO=m
CONFIG_SENSORS_DRIVETEMP=m
CONFIG_SENSORS_DS620=m
CONFIG_SENSORS_DS1621=m
CONFIG_SENSORS_I5K_AMB=m
CONFIG_SENSORS_F71805F=m
CONFIG_SENSORS_F71882FG=m
CONFIG_SENSORS_F75375S=m
CONFIG_SENSORS_FTSTEUTATES=m
CONFIG_SENSORS_GL518SM=m
CONFIG_SENSORS_GL520SM=m
CONFIG_SENSORS_G760A=m
CONFIG_SENSORS_G762=m
CONFIG_SENSORS_GPIO_FAN=m
CONFIG_SENSORS_HIH6130=m
CONFIG_SENSORS_IIO_HWMON=m
CONFIG_SENSORS_IT87=m
CONFIG_SENSORS_JC42=m
CONFIG_SENSORS_POWR1220=m
CONFIG_SENSORS_LINEAGE=m
CONFIG_SENSORS_LTC2945=m
CONFIG_SENSORS_LTC2947=m
CONFIG_SENSORS_LTC2947_I2C=m
CONFIG_SENSORS_LTC2947_SPI=m
CONFIG_SENSORS_LTC2990=m
CONFIG_SENSORS_LTC4151=m
CONFIG_SENSORS_LTC4215=m
CONFIG_SENSORS_LTC4222=m
CONFIG_SENSORS_LTC4245=m
CONFIG_SENSORS_LTC4260=m
CONFIG_SENSORS_LTC4261=m
# CONFIG_SENSORS_MAX1111 is not set
CONFIG_SENSORS_MAX16065=m
CONFIG_SENSORS_MAX1619=m
CONFIG_SENSORS_MAX1668=m
CONFIG_SENSORS_MAX197=m
CONFIG_SENSORS_MAX31722=m
CONFIG_SENSORS_MAX31730=m
CONFIG_SENSORS_MAX6621=m
CONFIG_SENSORS_MAX6639=m
CONFIG_SENSORS_MAX6642=m
CONFIG_SENSORS_MAX6650=m
CONFIG_SENSORS_MAX6697=m
CONFIG_SENSORS_MAX31790=m
CONFIG_SENSORS_MCP3021=m
CONFIG_SENSORS_TC654=m
CONFIG_SENSORS_MR75203=m
CONFIG_SENSORS_ADCXX=m
CONFIG_SENSORS_LM63=m
CONFIG_SENSORS_LM70=m
CONFIG_SENSORS_LM73=m
CONFIG_SENSORS_LM75=m
CONFIG_SENSORS_LM77=m
CONFIG_SENSORS_LM78=m
CONFIG_SENSORS_LM80=m
CONFIG_SENSORS_LM83=m
CONFIG_SENSORS_LM85=m
CONFIG_SENSORS_LM87=m
CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_LM92=m
CONFIG_SENSORS_LM93=m
CONFIG_SENSORS_LM95234=m
CONFIG_SENSORS_LM95241=m
CONFIG_SENSORS_LM95245=m
CONFIG_SENSORS_PC87360=m
CONFIG_SENSORS_PC87427=m
CONFIG_SENSORS_NTC_THERMISTOR=m
CONFIG_SENSORS_NCT6683=m
CONFIG_SENSORS_NCT6775=m
CONFIG_SENSORS_NCT7802=m
CONFIG_SENSORS_NCT7904=m
CONFIG_SENSORS_NPCM7XX=m
CONFIG_SENSORS_OCC_P8_I2C=m
CONFIG_SENSORS_OCC=m
CONFIG_SENSORS_PCF8591=m
CONFIG_PMBUS=m
CONFIG_SENSORS_PMBUS=m
# CONFIG_SENSORS_ADM1266 is not set
# CONFIG_SENSORS_ADM1275 is not set
# CONFIG_SENSORS_BEL_PFE is not set
# CONFIG_SENSORS_IBM_CFFPS is not set
# CONFIG_SENSORS_INSPUR_IPSPS is not set
# CONFIG_SENSORS_IR35221 is not set
# CONFIG_SENSORS_IR38064 is not set
# CONFIG_SENSORS_IRPS5401 is not set
# CONFIG_SENSORS_ISL68137 is not set
# CONFIG_SENSORS_LM25066 is not set
# CONFIG_SENSORS_LTC2978 is not set
# CONFIG_SENSORS_LTC3815 is not set
# CONFIG_SENSORS_MAX16064 is not set
# CONFIG_SENSORS_MAX16601 is not set
# CONFIG_SENSORS_MAX20730 is not set
# CONFIG_SENSORS_MAX20751 is not set
# CONFIG_SENSORS_MAX31785 is not set
# CONFIG_SENSORS_MAX34440 is not set
# CONFIG_SENSORS_MAX8688 is not set
# CONFIG_SENSORS_MP2975 is not set
# CONFIG_SENSORS_PXE1610 is not set
# CONFIG_SENSORS_TPS40422 is not set
# CONFIG_SENSORS_TPS53679 is not set
# CONFIG_SENSORS_UCD9000 is not set
# CONFIG_SENSORS_UCD9200 is not set
# CONFIG_SENSORS_XDPE122 is not set
# CONFIG_SENSORS_ZL6100 is not set
CONFIG_SENSORS_PWM_FAN=m
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_TMP513 is not set
# CONFIG_SENSORS_VEXPRESS is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set

#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
# CONFIG_THERMAL_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
# CONFIG_THERMAL_EMULATION is not set
CONFIG_THERMAL_MMIO=y
CONFIG_SUN8I_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_AMLOGIC_THERMAL=y
CONFIG_GENERIC_ADC_THERMAL=m
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=m
# CONFIG_GPIO_WATCHDOG is not set
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
CONFIG_ARM_SP805_WATCHDOG=m
CONFIG_ARM_SBSA_WATCHDOG=m
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=m
CONFIG_SUNXI_WATCHDOG=m
# CONFIG_MAX63XX_WATCHDOG is not set
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_WATCHDOG=m
# CONFIG_ARM_SMC_WATCHDOG is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_MEN_A21_WDT is not set

#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB=m
CONFIG_SSB_SPROM=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_PCIHOST=y
CONFIG_SSB_SDIOHOST_POSSIBLE=y
CONFIG_SSB_SDIOHOST=y
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
CONFIG_SSB_DRIVER_PCICORE=y
# CONFIG_SSB_DRIVER_GPIO is not set
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
# CONFIG_BCMA_HOST_PCI is not set
CONFIG_BCMA_HOST_SOC=y
# CONFIG_BCMA_DRIVER_PCI is not set
CONFIG_BCMA_SFLASH=y
CONFIG_BCMA_DRIVER_GMAC_CMN=y
CONFIG_BCMA_DRIVER_GPIO=y
CONFIG_BCMA_DEBUG=y

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
CONFIG_MFD_AC100=y
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
# CONFIG_MFD_MADERA is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_LPC_ICH is not set
CONFIG_LPC_SCH=m
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_UCB1400_CORE is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RC5T583 is not set
CONFIG_MFD_RK808=y
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SUN6I_PRCM=y
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TPS68470 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS80031 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TQMX86 is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
# CONFIG_MFD_ROHM_BD70528 is not set
# CONFIG_MFD_ROHM_BD71828 is not set
# CONFIG_MFD_STPMIC1 is not set
CONFIG_MFD_STMFX=m
# CONFIG_MFD_KHADAS_MCU is not set
# CONFIG_MFD_VEXPRESS_SYSREG is not set
# CONFIG_RAVE_SP_CORE is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_88PG86X is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_AD5398 is not set
CONFIG_REGULATOR_AXP20X=y
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
# CONFIG_REGULATOR_FAN53555 is not set
# CONFIG_REGULATOR_FAN53880 is not set
CONFIG_REGULATOR_GPIO=y
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_LP8755 is not set
# CONFIG_REGULATOR_LTC3589 is not set
# CONFIG_REGULATOR_LTC3676 is not set
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_MAX8973 is not set
# CONFIG_REGULATOR_MAX77826 is not set
# CONFIG_REGULATOR_MCP16502 is not set
# CONFIG_REGULATOR_MP5416 is not set
# CONFIG_REGULATOR_MP8859 is not set
# CONFIG_REGULATOR_MP886X is not set
# CONFIG_REGULATOR_MPQ7920 is not set
# CONFIG_REGULATOR_MT6311 is not set
# CONFIG_REGULATOR_PCA9450 is not set
# CONFIG_REGULATOR_PFUZE100 is not set
# CONFIG_REGULATOR_PV88060 is not set
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
CONFIG_REGULATOR_PWM=y
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
CONFIG_REGULATOR_RK808=y
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RTMV20 is not set
# CONFIG_REGULATOR_SLG51000 is not set
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
# CONFIG_REGULATOR_SY8827N is not set
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_TPS6524X is not set
CONFIG_REGULATOR_VCTRL=y
# CONFIG_REGULATOR_VEXPRESS is not set
# CONFIG_REGULATOR_QCOM_LABIBB is not set
CONFIG_RC_CORE=y
CONFIG_RC_MAP=y
CONFIG_LIRC=y
# CONFIG_BPF_LIRC_MODE2 is not set
CONFIG_RC_DECODERS=y
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
CONFIG_IR_JVC_DECODER=m
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_XMP_DECODER=m
CONFIG_IR_IMON_DECODER=m
CONFIG_IR_RCMM_DECODER=m
CONFIG_RC_DEVICES=y
CONFIG_RC_ATI_REMOTE=m
# CONFIG_IR_ENE is not set
CONFIG_IR_HIX5HD2=m
CONFIG_IR_IMON=m
CONFIG_IR_IMON_RAW=m
CONFIG_IR_MCEUSB=m
# CONFIG_IR_ITE_CIR is not set
# CONFIG_IR_FINTEK is not set
CONFIG_IR_MESON=m
# CONFIG_IR_NUVOTON is not set
CONFIG_IR_REDRAT3=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m
CONFIG_IR_IGORPLUGUSB=m
CONFIG_IR_IGUANA=m
CONFIG_IR_TTUSBIR=m
CONFIG_RC_LOOPBACK=m
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_GPIO_TX=m
CONFIG_IR_PWM_TX=m
CONFIG_IR_SUNXI=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SIR=m
CONFIG_RC_XBOX_DVD=m
CONFIG_IR_TOY=m
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y
CONFIG_CEC_PIN=y
CONFIG_MEDIA_CEC_RC=y
CONFIG_CEC_PIN_ERROR_INJ=y
CONFIG_MEDIA_CEC_SUPPORT=y
# CONFIG_CEC_CH7322 is not set
CONFIG_CEC_MESON_AO=y
CONFIG_CEC_MESON_G12A_AO=y
# CONFIG_CEC_GPIO is not set
CONFIG_USB_PULSE8_CEC=m
CONFIG_USB_RAINSHADOW_CEC=m
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_SUPPORT_FILTER=y
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
CONFIG_MEDIA_RADIO_SUPPORT=y
CONFIG_MEDIA_SDR_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_TEST_SUPPORT=y
# end of Media device types

CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_DVB_CORE=y

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2=y
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_ADV_DEBUG=y
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_H264=m
CONFIG_V4L2_MEM2MEM_DEV=m
CONFIG_V4L2_FWNODE=m
CONFIG_VIDEOBUF_GEN=m
CONFIG_VIDEOBUF_VMALLOC=m
# end of Video4Linux options

#
# Media controller options
#
CONFIG_MEDIA_CONTROLLER_DVB=y
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y

#
# Please notice that the enabled Media controller Request API is EXPERIMENTAL
#
# end of Media controller options

#
# Digital TV options
#
CONFIG_DVB_MMAP=y
CONFIG_DVB_NET=y
CONFIG_DVB_MAX_ADAPTERS=8
CONFIG_DVB_DYNAMIC_MINORS=y
# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
# CONFIG_DVB_ULE_DEBUG is not set
# end of Digital TV options

#
# Media drivers
#

#
# Drivers filtered as selected at 'Filter media drivers'
#
CONFIG_TTPCI_EEPROM=m
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_VIDEO_CLASS=m
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
CONFIG_USB_GSPCA=m
CONFIG_USB_M5602=m
CONFIG_USB_STV06XX=m
CONFIG_USB_GL860=m
CONFIG_USB_GSPCA_BENQ=m
CONFIG_USB_GSPCA_CONEX=m
CONFIG_USB_GSPCA_CPIA1=m
CONFIG_USB_GSPCA_DTCS033=m
CONFIG_USB_GSPCA_ETOMS=m
CONFIG_USB_GSPCA_FINEPIX=m
CONFIG_USB_GSPCA_JEILINJ=m
CONFIG_USB_GSPCA_JL2005BCD=m
CONFIG_USB_GSPCA_KINECT=m
CONFIG_USB_GSPCA_KONICA=m
CONFIG_USB_GSPCA_MARS=m
CONFIG_USB_GSPCA_MR97310A=m
CONFIG_USB_GSPCA_NW80X=m
CONFIG_USB_GSPCA_OV519=m
CONFIG_USB_GSPCA_OV534=m
CONFIG_USB_GSPCA_OV534_9=m
CONFIG_USB_GSPCA_PAC207=m
CONFIG_USB_GSPCA_PAC7302=m
CONFIG_USB_GSPCA_PAC7311=m
CONFIG_USB_GSPCA_SE401=m
CONFIG_USB_GSPCA_SN9C2028=m
CONFIG_USB_GSPCA_SN9C20X=m
CONFIG_USB_GSPCA_SONIXB=m
CONFIG_USB_GSPCA_SONIXJ=m
CONFIG_USB_GSPCA_SPCA500=m
CONFIG_USB_GSPCA_SPCA501=m
CONFIG_USB_GSPCA_SPCA505=m
CONFIG_USB_GSPCA_SPCA506=m
CONFIG_USB_GSPCA_SPCA508=m
CONFIG_USB_GSPCA_SPCA561=m
CONFIG_USB_GSPCA_SPCA1528=m
CONFIG_USB_GSPCA_SQ905=m
CONFIG_USB_GSPCA_SQ905C=m
CONFIG_USB_GSPCA_SQ930X=m
CONFIG_USB_GSPCA_STK014=m
CONFIG_USB_GSPCA_STK1135=m
CONFIG_USB_GSPCA_STV0680=m
CONFIG_USB_GSPCA_SUNPLUS=m
CONFIG_USB_GSPCA_T613=m
CONFIG_USB_GSPCA_TOPRO=m
CONFIG_USB_GSPCA_TOUPTEK=m
CONFIG_USB_GSPCA_TV8532=m
CONFIG_USB_GSPCA_VC032X=m
CONFIG_USB_GSPCA_VICAM=m
CONFIG_USB_GSPCA_XIRLINK_CIT=m
CONFIG_USB_GSPCA_ZC3XX=m
CONFIG_USB_PWC=m
# CONFIG_USB_PWC_DEBUG is not set
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_VIDEO_CPIA2=m
CONFIG_USB_ZR364XX=m
CONFIG_USB_STKWEBCAM=m
CONFIG_USB_S2255=m
CONFIG_VIDEO_USBTV=m

#
# Analog TV USB devices
#
CONFIG_VIDEO_PVRUSB2=m
CONFIG_VIDEO_PVRUSB2_SYSFS=y
CONFIG_VIDEO_PVRUSB2_DVB=y
# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
CONFIG_VIDEO_HDPVR=m
CONFIG_VIDEO_STK1160_COMMON=m
CONFIG_VIDEO_STK1160=m
CONFIG_VIDEO_GO7007=m
CONFIG_VIDEO_GO7007_USB=m
CONFIG_VIDEO_GO7007_LOADER=m
CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m

#
# Analog/digital TV USB devices
#
CONFIG_VIDEO_AU0828=m
CONFIG_VIDEO_AU0828_V4L2=y
CONFIG_VIDEO_AU0828_RC=y
CONFIG_VIDEO_CX231XX=m
CONFIG_VIDEO_CX231XX_RC=y
CONFIG_VIDEO_CX231XX_ALSA=m
CONFIG_VIDEO_CX231XX_DVB=m
CONFIG_VIDEO_TM6000=m
CONFIG_VIDEO_TM6000_ALSA=m
CONFIG_VIDEO_TM6000_DVB=m

#
# Digital TV USB devices
#
CONFIG_DVB_USB=m
# CONFIG_DVB_USB_DEBUG is not set
CONFIG_DVB_USB_DIB3000MC=m
CONFIG_DVB_USB_A800=m
CONFIG_DVB_USB_DIBUSB_MB=m
CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
CONFIG_DVB_USB_DIBUSB_MC=m
CONFIG_DVB_USB_DIB0700=m
CONFIG_DVB_USB_UMT_010=m
CONFIG_DVB_USB_CXUSB=m
# CONFIG_DVB_USB_CXUSB_ANALOG is not set
CONFIG_DVB_USB_M920X=m
CONFIG_DVB_USB_DIGITV=m
CONFIG_DVB_USB_VP7045=m
CONFIG_DVB_USB_VP702X=m
CONFIG_DVB_USB_GP8PSK=m
CONFIG_DVB_USB_NOVA_T_USB2=m
CONFIG_DVB_USB_TTUSB2=m
CONFIG_DVB_USB_DTT200U=m
CONFIG_DVB_USB_OPERA1=m
CONFIG_DVB_USB_AF9005=m
CONFIG_DVB_USB_AF9005_REMOTE=m
CONFIG_DVB_USB_PCTV452E=m
CONFIG_DVB_USB_DW2102=m
CONFIG_DVB_USB_CINERGY_T2=m
CONFIG_DVB_USB_DTV5100=m
CONFIG_DVB_USB_AZ6027=m
CONFIG_DVB_USB_TECHNISAT_USB2=m
CONFIG_DVB_USB_V2=m
CONFIG_DVB_USB_AF9015=m
CONFIG_DVB_USB_AF9035=m
CONFIG_DVB_USB_ANYSEE=m
CONFIG_DVB_USB_AU6610=m
CONFIG_DVB_USB_AZ6007=m
CONFIG_DVB_USB_CE6230=m
CONFIG_DVB_USB_EC168=m
CONFIG_DVB_USB_GL861=m
CONFIG_DVB_USB_LME2510=m
CONFIG_DVB_USB_MXL111SF=m
CONFIG_DVB_USB_RTL28XXU=m
CONFIG_DVB_USB_DVBSKY=m
CONFIG_DVB_USB_ZD1301=m
CONFIG_DVB_TTUSB_BUDGET=m
CONFIG_DVB_TTUSB_DEC=m
CONFIG_SMS_USB_DRV=m
CONFIG_DVB_B2C2_FLEXCOP_USB=m
# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
CONFIG_DVB_AS102=m

#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=m
CONFIG_VIDEO_EM28XX_V4L2=m
CONFIG_VIDEO_EM28XX_ALSA=m
CONFIG_VIDEO_EM28XX_DVB=m
CONFIG_VIDEO_EM28XX_RC=m

#
# Software defined radio USB devices
#
# CONFIG_USB_AIRSPY is not set
# CONFIG_USB_HACKRF is not set
# CONFIG_USB_MSI2500 is not set
# CONFIG_MEDIA_PCI_SUPPORT is not set
CONFIG_RADIO_ADAPTERS=y
CONFIG_RADIO_TEA575X=m
CONFIG_RADIO_SI470X=m
CONFIG_USB_SI470X=m
CONFIG_I2C_SI470X=m
CONFIG_RADIO_SI4713=m
CONFIG_USB_SI4713=m
CONFIG_PLATFORM_SI4713=m
CONFIG_I2C_SI4713=m
CONFIG_USB_MR800=m
CONFIG_USB_DSBR=m
CONFIG_RADIO_MAXIRADIO=m
CONFIG_RADIO_SHARK=m
CONFIG_RADIO_SHARK2=m
CONFIG_USB_KEENE=m
CONFIG_USB_RAREMONO=m
CONFIG_USB_MA901=m
CONFIG_RADIO_TEA5764=m
CONFIG_RADIO_SAA7706H=m
CONFIG_RADIO_TEF6862=m
CONFIG_RADIO_WL1273=m
CONFIG_MEDIA_COMMON_OPTIONS=y

#
# common driver options
#
CONFIG_VIDEO_CX2341X=m
CONFIG_VIDEO_TVEEPROM=m
CONFIG_CYPRESS_FIRMWARE=m
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_DVB_B2C2_FLEXCOP=m
CONFIG_SMS_SIANO_MDTV=m
CONFIG_SMS_SIANO_RC=y
# CONFIG_V4L_PLATFORM_DRIVERS is not set
# CONFIG_V4L_MEM2MEM_DRIVERS is not set
# CONFIG_DVB_PLATFORM_DRIVERS is not set
# CONFIG_SDR_PLATFORM_DRIVERS is not set

#
# MMC/SDIO DVB adapters
#
# CONFIG_SMS_SDIO_DRV is not set
# CONFIG_V4L_TEST_DRIVERS is not set
# CONFIG_DVB_TEST_DRIVERS is not set
# end of Media drivers

#
# Media ancillary drivers
#
CONFIG_MEDIA_ATTACH=y

#
# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
#
CONFIG_VIDEO_IR_I2C=m

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_TVAUDIO=m
CONFIG_VIDEO_TDA7432=m
CONFIG_VIDEO_TDA9840=m
CONFIG_VIDEO_TDA1997X=m
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
CONFIG_VIDEO_MSP3400=m
CONFIG_VIDEO_CS3308=m
CONFIG_VIDEO_CS5345=m
CONFIG_VIDEO_CS53L32A=m
CONFIG_VIDEO_TLV320AIC23B=m
CONFIG_VIDEO_UDA1342=m
CONFIG_VIDEO_WM8775=m
CONFIG_VIDEO_WM8739=m
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_SONY_BTF_MPX=m
# end of Audio decoders, processors and mixers

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders

#
# Video decoders
#
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_ADV7183=m
CONFIG_VIDEO_ADV748X=m
CONFIG_VIDEO_ADV7604=m
# CONFIG_VIDEO_ADV7604_CEC is not set
CONFIG_VIDEO_ADV7842=m
# CONFIG_VIDEO_ADV7842_CEC is not set
CONFIG_VIDEO_BT819=m
CONFIG_VIDEO_BT856=m
CONFIG_VIDEO_BT866=m
CONFIG_VIDEO_KS0127=m
CONFIG_VIDEO_ML86V7667=m
CONFIG_VIDEO_SAA7110=m
CONFIG_VIDEO_SAA711X=m
CONFIG_VIDEO_TC358743=m
# CONFIG_VIDEO_TC358743_CEC is not set
CONFIG_VIDEO_TVP514X=m
CONFIG_VIDEO_TVP5150=m
CONFIG_VIDEO_TVP7002=m
CONFIG_VIDEO_TW2804=m
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=m
CONFIG_VIDEO_TW9910=m
CONFIG_VIDEO_VPX3220=m
# CONFIG_VIDEO_MAX9286 is not set

#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=m
CONFIG_VIDEO_CX25840=m
# end of Video decoders

#
# Video encoders
#
CONFIG_VIDEO_SAA7127=m
CONFIG_VIDEO_SAA7185=m
CONFIG_VIDEO_ADV7170=m
CONFIG_VIDEO_ADV7175=m
CONFIG_VIDEO_ADV7343=m
CONFIG_VIDEO_ADV7393=m
# CONFIG_VIDEO_ADV7511 is not set
CONFIG_VIDEO_AD9389B=m
CONFIG_VIDEO_AK881X=m
CONFIG_VIDEO_THS8200=m
# end of Video encoders

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
CONFIG_VIDEO_UPD64083=m
# end of Video improvement chips

#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips

#
# SDR tuner chips
#
# CONFIG_SDR_MAX2175 is not set
# end of SDR tuner chips

#
# Miscellaneous helper chips
#
CONFIG_VIDEO_THS7303=m
CONFIG_VIDEO_M52790=m
CONFIG_VIDEO_I2C=m
CONFIG_VIDEO_ST_MIPID02=m
# end of Miscellaneous helper chips

#
# Camera sensor devices
#
CONFIG_VIDEO_APTINA_PLL=m
CONFIG_VIDEO_HI556=m
CONFIG_VIDEO_IMX214=m
CONFIG_VIDEO_IMX219=m
CONFIG_VIDEO_IMX258=m
CONFIG_VIDEO_IMX274=m
CONFIG_VIDEO_IMX290=m
CONFIG_VIDEO_IMX319=m
CONFIG_VIDEO_IMX355=m
CONFIG_VIDEO_OV2640=m
CONFIG_VIDEO_OV2659=m
CONFIG_VIDEO_OV2680=m
CONFIG_VIDEO_OV2685=m
# CONFIG_VIDEO_OV2740 is not set
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_OV5647=m
CONFIG_VIDEO_OV6650=m
CONFIG_VIDEO_OV5670=m
CONFIG_VIDEO_OV5675=m
CONFIG_VIDEO_OV5695=m
CONFIG_VIDEO_OV7251=m
CONFIG_VIDEO_OV772X=m
CONFIG_VIDEO_OV7640=m
CONFIG_VIDEO_OV7670=m
CONFIG_VIDEO_OV7740=m
CONFIG_VIDEO_OV8856=m
CONFIG_VIDEO_OV9640=m
CONFIG_VIDEO_OV9650=m
CONFIG_VIDEO_OV13858=m
CONFIG_VIDEO_VS6624=m
CONFIG_VIDEO_MT9M001=m
CONFIG_VIDEO_MT9M032=m
CONFIG_VIDEO_MT9M111=m
CONFIG_VIDEO_MT9P031=m
CONFIG_VIDEO_MT9T001=m
CONFIG_VIDEO_MT9T112=m
CONFIG_VIDEO_MT9V011=m
CONFIG_VIDEO_MT9V032=m
CONFIG_VIDEO_MT9V111=m
CONFIG_VIDEO_SR030PC30=m
CONFIG_VIDEO_NOON010PC30=m
CONFIG_VIDEO_M5MOLS=m
# CONFIG_VIDEO_RDACM20 is not set
CONFIG_VIDEO_RJ54N1=m
CONFIG_VIDEO_S5K6AA=m
CONFIG_VIDEO_S5K6A3=m
CONFIG_VIDEO_S5K4ECGX=m
CONFIG_VIDEO_S5K5BAF=m
# CONFIG_VIDEO_SMIAPP is not set
CONFIG_VIDEO_ET8EK8=m
CONFIG_VIDEO_S5C73M3=m
# end of Camera sensor devices

#
# Lens drivers
#
CONFIG_VIDEO_AD5820=m
CONFIG_VIDEO_AK7375=m
CONFIG_VIDEO_DW9714=m
# CONFIG_VIDEO_DW9768 is not set
CONFIG_VIDEO_DW9807_VCM=m
# end of Lens drivers

#
# Flash devices
#
CONFIG_VIDEO_ADP1653=m
CONFIG_VIDEO_LM3560=m
CONFIG_VIDEO_LM3646=m
# end of Flash devices

#
# SPI helper chips
#
CONFIG_VIDEO_GS1662=m
# end of SPI helper chips

#
# Media SPI Adapters
#
CONFIG_CXD2880_SPI_DRV=m
# end of Media SPI Adapters

CONFIG_MEDIA_TUNER=y

#
# Customize TV tuners
#
CONFIG_MEDIA_TUNER_SIMPLE=y
CONFIG_MEDIA_TUNER_TDA18250=m
CONFIG_MEDIA_TUNER_TDA8290=y
CONFIG_MEDIA_TUNER_TDA827X=y
CONFIG_MEDIA_TUNER_TDA18271=y
CONFIG_MEDIA_TUNER_TDA9887=y
CONFIG_MEDIA_TUNER_TEA5761=y
CONFIG_MEDIA_TUNER_TEA5767=y
CONFIG_MEDIA_TUNER_MSI001=m
CONFIG_MEDIA_TUNER_MT20XX=y
CONFIG_MEDIA_TUNER_MT2060=m
CONFIG_MEDIA_TUNER_MT2063=m
CONFIG_MEDIA_TUNER_MT2266=m
CONFIG_MEDIA_TUNER_MT2131=m
CONFIG_MEDIA_TUNER_QT1010=m
CONFIG_MEDIA_TUNER_XC2028=y
CONFIG_MEDIA_TUNER_XC5000=y
CONFIG_MEDIA_TUNER_XC4000=y
CONFIG_MEDIA_TUNER_MXL5005S=m
CONFIG_MEDIA_TUNER_MXL5007T=m
CONFIG_MEDIA_TUNER_MC44S803=y
CONFIG_MEDIA_TUNER_MAX2165=m
CONFIG_MEDIA_TUNER_TDA18218=m
CONFIG_MEDIA_TUNER_FC0011=m
CONFIG_MEDIA_TUNER_FC0012=m
CONFIG_MEDIA_TUNER_FC0013=m
CONFIG_MEDIA_TUNER_TDA18212=m
CONFIG_MEDIA_TUNER_E4000=m
CONFIG_MEDIA_TUNER_FC2580=m
CONFIG_MEDIA_TUNER_M88RS6000T=m
CONFIG_MEDIA_TUNER_TUA9001=m
CONFIG_MEDIA_TUNER_SI2157=m
CONFIG_MEDIA_TUNER_IT913X=m
CONFIG_MEDIA_TUNER_R820T=m
CONFIG_MEDIA_TUNER_MXL301RF=m
CONFIG_MEDIA_TUNER_QM1D1C0042=m
CONFIG_MEDIA_TUNER_QM1D1B0004=m
# end of Customize TV tuners

#
# Customise DVB Frontends
#

#
# Multistandard (satellite) frontends
#
CONFIG_DVB_STB0899=m
CONFIG_DVB_STB6100=m
CONFIG_DVB_STV090x=m
CONFIG_DVB_STV0910=m
CONFIG_DVB_STV6110x=m
CONFIG_DVB_STV6111=m
CONFIG_DVB_MXL5XX=m
CONFIG_DVB_M88DS3103=m

#
# Multistandard (cable + terrestrial) frontends
#
CONFIG_DVB_DRXK=m
CONFIG_DVB_TDA18271C2DD=m
CONFIG_DVB_SI2165=m
CONFIG_DVB_MN88472=m
CONFIG_DVB_MN88473=m

#
# DVB-S (satellite) frontends
#
CONFIG_DVB_CX24110=m
CONFIG_DVB_CX24123=m
CONFIG_DVB_MT312=m
CONFIG_DVB_ZL10036=m
CONFIG_DVB_ZL10039=m
CONFIG_DVB_S5H1420=m
CONFIG_DVB_STV0288=m
CONFIG_DVB_STB6000=m
CONFIG_DVB_STV0299=m
CONFIG_DVB_STV6110=m
CONFIG_DVB_STV0900=m
CONFIG_DVB_TDA8083=m
CONFIG_DVB_TDA10086=m
CONFIG_DVB_TDA8261=m
CONFIG_DVB_VES1X93=m
CONFIG_DVB_TUNER_ITD1000=m
CONFIG_DVB_TUNER_CX24113=m
CONFIG_DVB_TDA826X=m
CONFIG_DVB_TUA6100=m
CONFIG_DVB_CX24116=m
CONFIG_DVB_CX24117=m
CONFIG_DVB_CX24120=m
CONFIG_DVB_SI21XX=m
CONFIG_DVB_TS2020=m
CONFIG_DVB_DS3000=m
CONFIG_DVB_MB86A16=m
CONFIG_DVB_TDA10071=m

#
# DVB-T (terrestrial) frontends
#
CONFIG_DVB_SP8870=m
CONFIG_DVB_SP887X=m
CONFIG_DVB_CX22700=m
CONFIG_DVB_CX22702=m
CONFIG_DVB_S5H1432=m
CONFIG_DVB_DRXD=m
CONFIG_DVB_L64781=m
CONFIG_DVB_TDA1004X=m
CONFIG_DVB_NXT6000=m
CONFIG_DVB_MT352=m
CONFIG_DVB_ZL10353=m
CONFIG_DVB_DIB3000MB=m
CONFIG_DVB_DIB3000MC=m
CONFIG_DVB_DIB7000M=m
CONFIG_DVB_DIB7000P=m
CONFIG_DVB_DIB9000=m
CONFIG_DVB_TDA10048=m
CONFIG_DVB_AF9013=m
CONFIG_DVB_EC100=m
CONFIG_DVB_STV0367=m
CONFIG_DVB_CXD2820R=m
CONFIG_DVB_CXD2841ER=m
CONFIG_DVB_RTL2830=m
CONFIG_DVB_RTL2832=m
CONFIG_DVB_RTL2832_SDR=m
CONFIG_DVB_SI2168=m
CONFIG_DVB_AS102_FE=m
CONFIG_DVB_ZD1301_DEMOD=m
CONFIG_DVB_GP8PSK_FE=m
CONFIG_DVB_CXD2880=m

#
# DVB-C (cable) frontends
#
CONFIG_DVB_VES1820=m
CONFIG_DVB_TDA10021=m
CONFIG_DVB_TDA10023=m
CONFIG_DVB_STV0297=m

#
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
#
CONFIG_DVB_NXT200X=m
CONFIG_DVB_OR51211=m
CONFIG_DVB_OR51132=m
CONFIG_DVB_BCM3510=m
CONFIG_DVB_LGDT330X=m
CONFIG_DVB_LGDT3305=m
CONFIG_DVB_LGDT3306A=m
CONFIG_DVB_LG2160=m
CONFIG_DVB_S5H1409=m
CONFIG_DVB_AU8522=m
CONFIG_DVB_AU8522_DTV=m
CONFIG_DVB_AU8522_V4L=m
CONFIG_DVB_S5H1411=m

#
# ISDB-T (terrestrial) frontends
#
CONFIG_DVB_S921=m
CONFIG_DVB_DIB8000=m
CONFIG_DVB_MB86A20S=m

#
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
#
CONFIG_DVB_TC90522=m
CONFIG_DVB_MN88443X=m

#
# Digital terrestrial only tuners/PLL
#
CONFIG_DVB_PLL=m
CONFIG_DVB_TUNER_DIB0070=m
CONFIG_DVB_TUNER_DIB0090=m

#
# SEC control devices for DVB-S
#
CONFIG_DVB_DRX39XYJ=m
CONFIG_DVB_LNBH25=m
CONFIG_DVB_LNBH29=m
CONFIG_DVB_LNBP21=m
CONFIG_DVB_LNBP22=m
CONFIG_DVB_ISL6405=m
CONFIG_DVB_ISL6421=m
CONFIG_DVB_ISL6423=m
CONFIG_DVB_A8293=m
CONFIG_DVB_LGS8GL5=m
CONFIG_DVB_LGS8GXX=m
CONFIG_DVB_ATBM8830=m
CONFIG_DVB_TDA665x=m
CONFIG_DVB_IX2505V=m
CONFIG_DVB_M88RS2000=m
CONFIG_DVB_AF9033=m
CONFIG_DVB_HORUS3A=m
CONFIG_DVB_ASCOT2E=m
CONFIG_DVB_HELENE=m

#
# Common Interface (EN50221) controller drivers
#
CONFIG_DVB_CXD2099=m
CONFIG_DVB_SP2=m
# end of Customise DVB Frontends

#
# Tools to develop new frontends
#
CONFIG_DVB_DUMMY_FE=m
# end of Media ancillary drivers

#
# Graphics support
#
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
CONFIG_DRM=y
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_KMS_FB_HELPER=y
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_TTM=m
CONFIG_DRM_TTM_DMA_PAGE_POOL=y
CONFIG_DRM_TTM_HELPER=m
CONFIG_DRM_GEM_CMA_HELPER=y
CONFIG_DRM_KMS_CMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=y
CONFIG_DRM_SCHED=m

#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips

#
# ARM devices
#
CONFIG_DRM_HDLCD=m
CONFIG_DRM_HDLCD_SHOW_UNDERRUN=y
CONFIG_DRM_MALI_DISPLAY=m
CONFIG_DRM_KOMEDA=m
# end of ARM devices

# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
CONFIG_DRM_ROCKCHIP=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_ROCKCHIP_LVDS=y
CONFIG_ROCKCHIP_RGB=y
CONFIG_ROCKCHIP_RK3066_HDMI=y
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_USE_LVDS is not set
CONFIG_DRM_SUN4I=y
CONFIG_DRM_SUN4I_HDMI=y
CONFIG_DRM_SUN4I_HDMI_CEC=y
CONFIG_DRM_SUN4I_BACKEND=y
CONFIG_DRM_SUN6I_DSI=y
CONFIG_DRM_SUN8I_DW_HDMI=y
CONFIG_DRM_SUN8I_MIXER=y
CONFIG_DRM_SUN8I_TCON_TOP=y
CONFIG_DRM_QXL=m
# CONFIG_DRM_BOCHS is not set
CONFIG_DRM_VIRTIO_GPU=m
CONFIG_DRM_PANEL=y

#
# Display Panels
#
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
# CONFIG_DRM_PANEL_LVDS is not set
# CONFIG_DRM_PANEL_SIMPLE is not set
# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
# CONFIG_DRM_PANEL_LG_LG4573 is not set
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set
# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
# CONFIG_DRM_DISPLAY_CONNECTOR is not set
# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
CONFIG_DRM_ANALOGIX_DP=y
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=y
CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
CONFIG_DRM_DW_HDMI_CEC=m
CONFIG_DRM_DW_MIPI_DSI=y
# end of Display Interface Bridges

# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
CONFIG_DRM_MESON=y
CONFIG_DRM_MESON_DW_HDMI=y
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_GM12U320 is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_DRM_PL111 is not set
CONFIG_DRM_LIMA=m
CONFIG_DRM_PANFROST=m
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_LEGACY is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y

#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_BACKLIGHT=m
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
CONFIG_FB_ARMCLCD=y
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_UVESA is not set
CONFIG_FB_EFI=y
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
CONFIG_FB_SIMPLE=y
# CONFIG_FB_SSD1307 is not set
# CONFIG_FB_SM712 is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_L4F00242T03 is not set
# CONFIG_LCD_LMS283GF05 is not set
# CONFIG_LCD_LTV350QV is not set
# CONFIG_LCD_ILI922X is not set
# CONFIG_LCD_ILI9320 is not set
# CONFIG_LCD_TDO24M is not set
# CONFIG_LCD_VGG2432A4 is not set
# CONFIG_LCD_PLATFORM is not set
# CONFIG_LCD_AMS369FG06 is not set
# CONFIG_LCD_LMS501KF03 is not set
# CONFIG_LCD_HX8357 is not set
# CONFIG_LCD_OTM3225A is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_KTD253 is not set
CONFIG_BACKLIGHT_PWM=m
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
CONFIG_BACKLIGHT_GPIO=m
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
CONFIG_BACKLIGHT_LED=m
# end of Backlight & LCD device support

CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
# end of Console display driver support

CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
# end of Graphics support

CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=m
CONFIG_SND_SEQ_DEVICE=m
CONFIG_SND_RAWMIDI=m
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_OSSEMUL is not set
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
CONFIG_SND_VMASTER=y
CONFIG_SND_SEQUENCER=m
CONFIG_SND_SEQ_DUMMY=m
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
CONFIG_SND_SEQ_MIDI_EVENT=m
CONFIG_SND_SEQ_MIDI=m
CONFIG_SND_SEQ_VIRMIDI=m
CONFIG_SND_MPU401_UART=m
CONFIG_SND_AC97_CODEC=m
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
CONFIG_SND_VIRMIDI=m
CONFIG_SND_MTPAV=m
CONFIG_SND_SERIAL_U16550=m
CONFIG_SND_MPU401=m
# CONFIG_SND_AC97_POWER_SAVE is not set
# CONFIG_SND_PCI is not set

#
# HD-Audio
#
# end of HD-Audio

CONFIG_SND_HDA_PREALLOC_SIZE=2048
# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
CONFIG_SND_BCD2000=m
CONFIG_SND_USB_LINE6=m
CONFIG_SND_USB_POD=m
CONFIG_SND_USB_PODHD=m
CONFIG_SND_USB_TONEPORT=m
CONFIG_SND_USB_VARIAX=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
# CONFIG_SND_SOC_AMD_ACP is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
CONFIG_SND_DESIGNWARE_I2S=m
# CONFIG_SND_DESIGNWARE_PCM is not set

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
# CONFIG_SND_SOC_FSL_SAI is not set
# CONFIG_SND_SOC_FSL_AUDMIX is not set
# CONFIG_SND_SOC_FSL_SSI is not set
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
# CONFIG_SND_SOC_FSL_MICFIL is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs

# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set

#
# ASoC support for Amlogic platforms
#
CONFIG_SND_MESON_AIU=m
CONFIG_SND_MESON_AXG_FIFO=m
CONFIG_SND_MESON_AXG_FRDDR=m
CONFIG_SND_MESON_AXG_TODDR=m
CONFIG_SND_MESON_AXG_TDM_FORMATTER=m
CONFIG_SND_MESON_AXG_TDM_INTERFACE=m
CONFIG_SND_MESON_AXG_TDMIN=m
CONFIG_SND_MESON_AXG_TDMOUT=m
CONFIG_SND_MESON_AXG_SOUND_CARD=m
CONFIG_SND_MESON_AXG_SPDIFOUT=m
CONFIG_SND_MESON_AXG_SPDIFIN=m
CONFIG_SND_MESON_AXG_PDM=m
CONFIG_SND_MESON_CARD_UTILS=m
CONFIG_SND_MESON_CODEC_GLUE=m
CONFIG_SND_MESON_GX_SOUND_CARD=m
CONFIG_SND_MESON_G12A_TOACODEC=m
CONFIG_SND_MESON_G12A_TOHDMITX=m
CONFIG_SND_SOC_MESON_T9015=m
# end of ASoC support for Amlogic platforms

CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_ROCKCHIP_I2S=m
CONFIG_SND_SOC_ROCKCHIP_PDM=m
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
CONFIG_SND_SOC_ROCKCHIP_RT5645=m
CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m
CONFIG_SND_SOC_RK3399_GRU_SOUND=m
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set

#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support

#
# Allwinner SoC Audio support
#
CONFIG_SND_SUN4I_CODEC=m
CONFIG_SND_SUN8I_CODEC=m
CONFIG_SND_SUN8I_CODEC_ANALOG=m
CONFIG_SND_SUN50I_CODEC_ANALOG=m
CONFIG_SND_SUN4I_I2S=m
CONFIG_SND_SUN4I_SPDIF=m
CONFIG_SND_SUN8I_ADDA_PR_REGMAP=m
# end of Allwinner SoC Audio support

# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# CONFIG_SND_SOC_XTFPGA_I2S is not set
# CONFIG_ZX_TDM is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
CONFIG_SND_SOC_AC97_CODEC=m
# CONFIG_SND_SOC_ADAU1701 is not set
# CONFIG_SND_SOC_ADAU1761_I2C is not set
# CONFIG_SND_SOC_ADAU1761_SPI is not set
# CONFIG_SND_SOC_ADAU7002 is not set
# CONFIG_SND_SOC_ADAU7118_HW is not set
# CONFIG_SND_SOC_ADAU7118_I2C is not set
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_AK4118 is not set
# CONFIG_SND_SOC_AK4458 is not set
# CONFIG_SND_SOC_AK4554 is not set
# CONFIG_SND_SOC_AK4613 is not set
# CONFIG_SND_SOC_AK4642 is not set
# CONFIG_SND_SOC_AK5386 is not set
# CONFIG_SND_SOC_AK5558 is not set
# CONFIG_SND_SOC_ALC5623 is not set
# CONFIG_SND_SOC_BD28623 is not set
# CONFIG_SND_SOC_BT_SCO is not set
# CONFIG_SND_SOC_CS35L32 is not set
# CONFIG_SND_SOC_CS35L33 is not set
# CONFIG_SND_SOC_CS35L34 is not set
# CONFIG_SND_SOC_CS35L35 is not set
# CONFIG_SND_SOC_CS35L36 is not set
# CONFIG_SND_SOC_CS42L42 is not set
# CONFIG_SND_SOC_CS42L51_I2C is not set
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_CS42L73 is not set
# CONFIG_SND_SOC_CS4234 is not set
# CONFIG_SND_SOC_CS4265 is not set
# CONFIG_SND_SOC_CS4270 is not set
# CONFIG_SND_SOC_CS4271_I2C is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_CS42XX8_I2C is not set
# CONFIG_SND_SOC_CS43130 is not set
# CONFIG_SND_SOC_CS4341 is not set
# CONFIG_SND_SOC_CS4349 is not set
# CONFIG_SND_SOC_CS53L30 is not set
# CONFIG_SND_SOC_CX2072X is not set
# CONFIG_SND_SOC_DA7213 is not set
CONFIG_SND_SOC_DA7219=m
CONFIG_SND_SOC_DMIC=m
CONFIG_SND_SOC_HDMI_CODEC=y
# CONFIG_SND_SOC_ES7134 is not set
# CONFIG_SND_SOC_ES7241 is not set
# CONFIG_SND_SOC_ES8316 is not set
CONFIG_SND_SOC_ES8328=m
CONFIG_SND_SOC_ES8328_I2C=m
CONFIG_SND_SOC_ES8328_SPI=m
# CONFIG_SND_SOC_GTM601 is not set
CONFIG_SND_SOC_INNO_RK3036=m
# CONFIG_SND_SOC_MAX98088 is not set
CONFIG_SND_SOC_MAX98090=m
CONFIG_SND_SOC_MAX98357A=m
# CONFIG_SND_SOC_MAX98504 is not set
# CONFIG_SND_SOC_MAX9867 is not set
# CONFIG_SND_SOC_MAX98927 is not set
# CONFIG_SND_SOC_MAX98373_I2C is not set
# CONFIG_SND_SOC_MAX98390 is not set
# CONFIG_SND_SOC_MAX9860 is not set
# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set
# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
# CONFIG_SND_SOC_PCM1681 is not set
# CONFIG_SND_SOC_PCM1789_I2C is not set
# CONFIG_SND_SOC_PCM179X_I2C is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_I2C is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3060_I2C is not set
# CONFIG_SND_SOC_PCM3060_SPI is not set
# CONFIG_SND_SOC_PCM3168A_I2C is not set
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM512x_I2C is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
CONFIG_SND_SOC_RK3328=m
CONFIG_SND_SOC_RL6231=m
CONFIG_SND_SOC_RT5514=m
CONFIG_SND_SOC_RT5514_SPI=m
# CONFIG_SND_SOC_RT5616 is not set
# CONFIG_SND_SOC_RT5631 is not set
CONFIG_SND_SOC_RT5645=m
# CONFIG_SND_SOC_SGTL5000 is not set
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set
CONFIG_SND_SOC_SPDIF=m
# CONFIG_SND_SOC_SSM2305 is not set
# CONFIG_SND_SOC_SSM2602_SPI is not set
# CONFIG_SND_SOC_SSM2602_I2C is not set
# CONFIG_SND_SOC_SSM4567 is not set
# CONFIG_SND_SOC_STA32X is not set
# CONFIG_SND_SOC_STA350 is not set
# CONFIG_SND_SOC_STI_SAS is not set
# CONFIG_SND_SOC_TAS2552 is not set
# CONFIG_SND_SOC_TAS2562 is not set
# CONFIG_SND_SOC_TAS2764 is not set
# CONFIG_SND_SOC_TAS2770 is not set
# CONFIG_SND_SOC_TAS5086 is not set
# CONFIG_SND_SOC_TAS571X is not set
# CONFIG_SND_SOC_TAS5720 is not set
# CONFIG_SND_SOC_TAS6424 is not set
# CONFIG_SND_SOC_TDA7419 is not set
# CONFIG_SND_SOC_TFA9879 is not set
# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC31XX is not set
# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_TLV320AIC3X is not set
# CONFIG_SND_SOC_TLV320ADCX140 is not set
CONFIG_SND_SOC_TS3A227E=m
# CONFIG_SND_SOC_TSCS42XX is not set
# CONFIG_SND_SOC_TSCS454 is not set
# CONFIG_SND_SOC_UDA1334 is not set
# CONFIG_SND_SOC_WM8510 is not set
# CONFIG_SND_SOC_WM8523 is not set
# CONFIG_SND_SOC_WM8524 is not set
# CONFIG_SND_SOC_WM8580 is not set
# CONFIG_SND_SOC_WM8711 is not set
# CONFIG_SND_SOC_WM8728 is not set
# CONFIG_SND_SOC_WM8731 is not set
# CONFIG_SND_SOC_WM8737 is not set
# CONFIG_SND_SOC_WM8741 is not set
# CONFIG_SND_SOC_WM8750 is not set
# CONFIG_SND_SOC_WM8753 is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8776 is not set
# CONFIG_SND_SOC_WM8782 is not set
# CONFIG_SND_SOC_WM8804_I2C is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_WM8903 is not set
# CONFIG_SND_SOC_WM8904 is not set
# CONFIG_SND_SOC_WM8960 is not set
# CONFIG_SND_SOC_WM8962 is not set
# CONFIG_SND_SOC_WM8974 is not set
# CONFIG_SND_SOC_WM8978 is not set
# CONFIG_SND_SOC_WM8985 is not set
# CONFIG_SND_SOC_ZL38060 is not set
# CONFIG_SND_SOC_ZX_AUD96P22 is not set
# CONFIG_SND_SOC_MAX9759 is not set
# CONFIG_SND_SOC_MT6351 is not set
# CONFIG_SND_SOC_MT6358 is not set
# CONFIG_SND_SOC_MT6660 is not set
# CONFIG_SND_SOC_NAU8540 is not set
# CONFIG_SND_SOC_NAU8810 is not set
# CONFIG_SND_SOC_NAU8822 is not set
# CONFIG_SND_SOC_NAU8824 is not set
# CONFIG_SND_SOC_TPA6130A2 is not set
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_AC97_BUS=y

#
# HID support
#
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=m
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
CONFIG_HID_A4TECH=m
CONFIG_HID_ACCUTOUCH=m
CONFIG_HID_ACRUX=m
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=m
CONFIG_HID_APPLEIR=m
CONFIG_HID_ASUS=m
CONFIG_HID_AUREAL=m
CONFIG_HID_BELKIN=m
CONFIG_HID_BETOP_FF=m
CONFIG_HID_BIGBEN_FF=m
CONFIG_HID_CHERRY=m
CONFIG_HID_CHICONY=m
CONFIG_HID_CORSAIR=m
CONFIG_HID_COUGAR=m
CONFIG_HID_MACALLY=m
CONFIG_HID_PRODIKEYS=m
CONFIG_HID_CMEDIA=m
CONFIG_HID_CP2112=m
CONFIG_HID_CREATIVE_SB0540=m
CONFIG_HID_CYPRESS=m
CONFIG_HID_DRAGONRISE=m
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=m
CONFIG_HID_ELAN=m
CONFIG_HID_ELECOM=m
CONFIG_HID_ELO=m
CONFIG_HID_EZKEY=m
CONFIG_HID_GEMBIRD=m
CONFIG_HID_GFRM=m
CONFIG_HID_GLORIOUS=m
CONFIG_HID_HOLTEK=m
CONFIG_HOLTEK_FF=y
CONFIG_HID_VIVALDI=m
CONFIG_HID_GT683R=m
CONFIG_HID_KEYTOUCH=m
CONFIG_HID_KYE=m
CONFIG_HID_UCLOGIC=m
CONFIG_HID_WALTOP=m
CONFIG_HID_VIEWSONIC=m
CONFIG_HID_GYRATION=m
CONFIG_HID_ICADE=m
CONFIG_HID_ITE=m
CONFIG_HID_JABRA=m
CONFIG_HID_TWINHAN=m
CONFIG_HID_KENSINGTON=m
CONFIG_HID_LCPOWER=m
CONFIG_HID_LED=m
CONFIG_HID_LENOVO=m
CONFIG_HID_LOGITECH=m
CONFIG_HID_LOGITECH_DJ=m
CONFIG_HID_LOGITECH_HIDPP=m
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
CONFIG_HID_MAGICMOUSE=m
CONFIG_HID_MALTRON=m
CONFIG_HID_MAYFLASH=m
CONFIG_HID_REDRAGON=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
CONFIG_HID_MULTITOUCH=m
CONFIG_HID_NTI=m
CONFIG_HID_NTRIG=m
CONFIG_HID_ORTEK=m
CONFIG_HID_PANTHERLORD=m
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PENMOUNT=m
CONFIG_HID_PETALYNX=m
CONFIG_HID_PICOLCD=m
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
# CONFIG_HID_PICOLCD_LCD is not set
CONFIG_HID_PICOLCD_LEDS=y
CONFIG_HID_PICOLCD_CIR=y
CONFIG_HID_PLANTRONICS=m
CONFIG_HID_PRIMAX=m
CONFIG_HID_RETRODE=m
CONFIG_HID_ROCCAT=m
CONFIG_HID_SAITEK=m
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SONY=m
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=m
CONFIG_HID_STEAM=m
CONFIG_HID_STEELSERIES=m
CONFIG_HID_SUNPLUS=m
CONFIG_HID_RMI=m
CONFIG_HID_GREENASIA=m
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=m
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TIVO=m
CONFIG_HID_TOPSEED=m
CONFIG_HID_THINGM=m
CONFIG_HID_THRUSTMASTER=m
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_UDRAW_PS3=m
CONFIG_HID_U2FZERO=m
CONFIG_HID_WACOM=m
CONFIG_HID_WIIMOTE=m
CONFIG_HID_XINMO=m
CONFIG_HID_ZEROPLUS=m
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=m
CONFIG_HID_SENSOR_HUB=m
CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
CONFIG_HID_ALPS=m
CONFIG_HID_MCP2221=m
# end of Special HID drivers

#
# USB HID support
#
CONFIG_USB_HID=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
# end of USB HID support

#
# I2C HID support
#
# CONFIG_I2C_HID is not set
# end of I2C HID support
# end of HID support

CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_LED_TRIG=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_CONN_GPIO=m
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
CONFIG_USB_OTG_FSM=m
CONFIG_USB_LEDS_TRIGGER_USBPORT=m
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=y

#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=m
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=m
CONFIG_USB_XHCI_PCI_RENESAS=m
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_XHCI_SUNXI=m
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_EHCI_FSL=m
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OXU210HP_HCD=m
CONFIG_USB_ISP116X_HCD=m
CONFIG_USB_FOTG210_HCD=m
CONFIG_USB_MAX3421_HCD=m
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_OHCI_HCD_PCI=m
# CONFIG_USB_OHCI_HCD_SSB is not set
CONFIG_USB_OHCI_HCD_PLATFORM=m
CONFIG_USB_UHCI_HCD=m
CONFIG_USB_U132_HCD=m
CONFIG_USB_SL811_HCD=m
CONFIG_USB_SL811_HCD_ISO=y
CONFIG_USB_R8A66597_HCD=m
CONFIG_USB_HCD_BCMA=m
CONFIG_USB_HCD_SSB=m
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=y
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
CONFIG_USB_STORAGE_REALTEK=m
CONFIG_REALTEK_AUTOPM=y
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_FREECOM=m
CONFIG_USB_STORAGE_ISD200=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_STORAGE_ALAUDA=m
CONFIG_USB_STORAGE_ONETOUCH=m
CONFIG_USB_STORAGE_KARMA=m
CONFIG_USB_STORAGE_CYPRESS_ATACB=m
CONFIG_USB_STORAGE_ENE_UB6250=m
# CONFIG_USB_UAS is not set

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
CONFIG_USB_MICROTEK=m
CONFIG_USBIP_CORE=m
CONFIG_USBIP_VHCI_HCD=m
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=m
CONFIG_USBIP_VUDC=m
# CONFIG_USBIP_DEBUG is not set
# CONFIG_USB_CDNS3 is not set
CONFIG_USB_MUSB_HDRC=y
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y

#
# Platform Glue Layer
#

#
# MUSB DMA mode
#
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_ULPI=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y

#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=y
# CONFIG_USB_DWC3_HAPS is not set
CONFIG_USB_DWC3_MESON_G12A=y
CONFIG_USB_DWC3_OF_SIMPLE=m
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
# CONFIG_USB_DWC2_PCI is not set
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
CONFIG_USB_CHIPIDEA=m
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_CHIPIDEA_MSM=m
CONFIG_USB_CHIPIDEA_IMX=m
CONFIG_USB_CHIPIDEA_GENERIC=m
CONFIG_USB_CHIPIDEA_TEGRA=m
CONFIG_USB_ISP1760=m
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_ISP1761_UDC=y
# CONFIG_USB_ISP1760_HOST_ROLE is not set
# CONFIG_USB_ISP1760_GADGET_ROLE is not set
CONFIG_USB_ISP1760_DUAL_ROLE=y

#
# USB port drivers
#
CONFIG_USB_SERIAL=m
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=m
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=m
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=m
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=m
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_F81232=m
CONFIG_USB_SERIAL_F8153X=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=m
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_METRO=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MXUPORT=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=m
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=m
CONFIG_USB_SERIAL_QUALCOMM=m
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
# CONFIG_USB_SERIAL_SAFE_PADDED is not set
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
CONFIG_USB_SERIAL_SYMBOL=m
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
# CONFIG_USB_SERIAL_XIRCOM is not set
CONFIG_USB_SERIAL_WWAN=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=m
CONFIG_USB_SERIAL_XSENS_MT=m
CONFIG_USB_SERIAL_WISHBONE=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_SERIAL_QT2=m
CONFIG_USB_SERIAL_UPD78F0730=m
CONFIG_USB_SERIAL_DEBUG=m

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
CONFIG_USB_CYPRESS_CY7C63=m
CONFIG_USB_CYTHERM=m
CONFIG_USB_IDMOUSE=m
CONFIG_USB_FTDI_ELAN=m
CONFIG_USB_APPLEDISPLAY=m
# CONFIG_APPLE_MFI_FASTCHARGE is not set
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
CONFIG_USB_TEST=m
CONFIG_USB_EHSET_TEST_FIXTURE=m
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=m
CONFIG_USB_HUB_USB251XB=m
CONFIG_USB_HSIC_USB3503=m
CONFIG_USB_HSIC_USB4604=m
CONFIG_USB_LINK_LAYER_TEST=m
CONFIG_USB_CHAOSKEY=m

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
# CONFIG_NOP_USB_XCEIV is not set
CONFIG_USB_GPIO_VBUS=m
# CONFIG_USB_ISP1301 is not set
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set

#
# USB Peripheral Controller
#
CONFIG_USB_FOTG210_UDC=m
CONFIG_USB_GR_UDC=m
CONFIG_USB_R8A66597=m
CONFIG_USB_PXA27X=m
CONFIG_USB_MV_UDC=m
CONFIG_USB_MV_U3D=m
CONFIG_USB_SNP_CORE=m
CONFIG_USB_SNP_UDC_PLAT=m
CONFIG_USB_M66592=m
CONFIG_USB_BDC_UDC=m

#
# Platform Support
#
CONFIG_USB_AMD5536UDC=m
CONFIG_USB_NET2272=m
CONFIG_USB_NET2272_DMA=y
CONFIG_USB_NET2280=m
CONFIG_USB_GOKU=m
CONFIG_USB_EG20T=m
CONFIG_USB_GADGET_XILINX=m
# CONFIG_USB_MAX3420_UDC is not set
CONFIG_USB_DUMMY_HCD=m
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=m
CONFIG_USB_F_ACM=m
CONFIG_USB_F_SS_LB=m
CONFIG_USB_U_SERIAL=m
CONFIG_USB_U_ETHER=m
CONFIG_USB_U_AUDIO=m
CONFIG_USB_F_SERIAL=m
CONFIG_USB_F_OBEX=m
CONFIG_USB_F_NCM=m
CONFIG_USB_F_ECM=m
CONFIG_USB_F_EEM=m
CONFIG_USB_F_SUBSET=m
CONFIG_USB_F_RNDIS=m
CONFIG_USB_F_MASS_STORAGE=m
CONFIG_USB_F_FS=m
CONFIG_USB_F_UAC1=m
CONFIG_USB_F_UAC1_LEGACY=m
CONFIG_USB_F_UAC2=m
CONFIG_USB_F_UVC=m
CONFIG_USB_F_MIDI=m
CONFIG_USB_F_HID=m
CONFIG_USB_F_PRINTER=m
CONFIG_USB_F_TCM=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_LB_SS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y
CONFIG_USB_CONFIGFS_F_TCM=y

#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=m
CONFIG_USB_ZERO_HNPTEST=y
CONFIG_USB_AUDIO=m
CONFIG_GADGET_UAC1=y
CONFIG_GADGET_UAC1_LEGACY=y
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
CONFIG_USB_FUNCTIONFS_ETH=y
CONFIG_USB_FUNCTIONFS_RNDIS=y
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_GADGET_TARGET=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_G_HID=m
CONFIG_USB_G_DBGP=m
# CONFIG_USB_G_DBGP_PRINTK is not set
CONFIG_USB_G_DBGP_SERIAL=y
CONFIG_USB_G_WEBCAM=m
CONFIG_USB_RAW_GADGET=m
# end of USB Gadget precomposed configurations

CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=m
CONFIG_TYPEC_TCPCI=m
CONFIG_TYPEC_RT1711H=m
# CONFIG_TYPEC_TCPCI_MAXIM is not set
CONFIG_TYPEC_FUSB302=m
CONFIG_TYPEC_UCSI=m
CONFIG_UCSI_CCG=m
# CONFIG_UCSI_ACPI is not set
CONFIG_TYPEC_HD3SS3220=m
CONFIG_TYPEC_TPS6598X=m
CONFIG_TYPEC_STUSB160X=m

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
CONFIG_TYPEC_MUX_PI3USB30532=m
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
CONFIG_TYPEC_DP_ALTMODE=m
CONFIG_TYPEC_NVIDIA_ALTMODE=m
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
# CONFIG_PWRSEQ_SD8787 is not set
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_ARMMMCI is not set
# CONFIG_MMC_SDHCI is not set
CONFIG_MMC_MESON_GX=y
# CONFIG_MMC_MESON_MX_SDIO is not set
# CONFIG_MMC_TIFM_SD is not set
# CONFIG_MMC_SPI is not set
# CONFIG_MMC_CB710 is not set
# CONFIG_MMC_VIA_SDMMC is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
# CONFIG_MMC_DW_BLUEFIELD is not set
# CONFIG_MMC_DW_EXYNOS is not set
# CONFIG_MMC_DW_HI3798CV200 is not set
# CONFIG_MMC_DW_K3 is not set
# CONFIG_MMC_DW_PCI is not set
CONFIG_MMC_DW_ROCKCHIP=y
# CONFIG_MMC_VUB300 is not set
CONFIG_MMC_USHC=m
# CONFIG_MMC_USDHI6ROL0 is not set
CONFIG_MMC_REALTEK_USB=m
CONFIG_MMC_SUNXI=y
# CONFIG_MMC_CQHCI is not set
CONFIG_MMC_HSQ=y
# CONFIG_MMC_TOSHIBA_PCI is not set
# CONFIG_MMC_MTK is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
# CONFIG_LEDS_CLASS_FLASH is not set
# CONFIG_LEDS_CLASS_MULTICOLOR is not set
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set

#
# LED drivers
#
# CONFIG_LEDS_AN30259A is not set
# CONFIG_LEDS_AW2013 is not set
# CONFIG_LEDS_BCM6328 is not set
# CONFIG_LEDS_BCM6358 is not set
# CONFIG_LEDS_CR0014114 is not set
# CONFIG_LEDS_EL15203000 is not set
# CONFIG_LEDS_LM3530 is not set
# CONFIG_LEDS_LM3532 is not set
# CONFIG_LEDS_LM3642 is not set
# CONFIG_LEDS_LM3692X is not set
# CONFIG_LEDS_PCA9532 is not set
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP3952 is not set
# CONFIG_LEDS_LP50XX is not set
# CONFIG_LEDS_LP55XX_COMMON is not set
# CONFIG_LEDS_LP8860 is not set
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_PCA963X is not set
# CONFIG_LEDS_DAC124S085 is not set
CONFIG_LEDS_PWM=y
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_LT3593 is not set
CONFIG_LEDS_TCA6507=y
# CONFIG_LEDS_TLC591XX is not set
# CONFIG_LEDS_LM355x is not set
# CONFIG_LEDS_IS31FL319X is not set
# CONFIG_LEDS_IS31FL32XX is not set

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
# CONFIG_LEDS_BLINKM is not set
CONFIG_LEDS_SYSCON=y
# CONFIG_LEDS_MLXREG is not set
CONFIG_LEDS_USER=y
# CONFIG_LEDS_SPI_BYTE is not set
# CONFIG_LEDS_TI_LMU_COMMON is not set

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=m
# CONFIG_LEDS_TRIGGER_CPU is not set
CONFIG_LEDS_TRIGGER_ACTIVITY=m
CONFIG_LEDS_TRIGGER_GPIO=m
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=m
CONFIG_LEDS_TRIGGER_CAMERA=m
# CONFIG_LEDS_TRIGGER_PANIC is not set
CONFIG_LEDS_TRIGGER_NETDEV=m
CONFIG_LEDS_TRIGGER_PATTERN=m
CONFIG_LEDS_TRIGGER_AUDIO=m
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
# CONFIG_EDAC_DEBUG is not set
# CONFIG_EDAC_GHES is not set
# CONFIG_EDAC_THUNDERX is not set
# CONFIG_EDAC_XGENE is not set
CONFIG_EDAC_DMC520=m
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_ABB5ZES3 is not set
# CONFIG_RTC_DRV_ABEOZ9 is not set
# CONFIG_RTC_DRV_ABX80X is not set
CONFIG_RTC_DRV_AC100=y
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
CONFIG_RTC_DRV_HYM8563=m
# CONFIG_RTC_DRV_MAX6900 is not set
CONFIG_RTC_DRV_RK808=y
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_ISL12026 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8523 is not set
# CONFIG_RTC_DRV_PCF85063 is not set
# CONFIG_RTC_DRV_PCF85363 is not set
CONFIG_RTC_DRV_PCF8563=m
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8010 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV3028 is not set
# CONFIG_RTC_DRV_RV3032 is not set
# CONFIG_RTC_DRV_RV8803 is not set
# CONFIG_RTC_DRV_SD3078 is not set

#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RX6110 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_MCP795 is not set
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_PCF2127 is not set
# CONFIG_RTC_DRV_RV3029C2 is not set

#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1685_FAMILY is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_DS2404 is not set
CONFIG_RTC_DRV_EFI=y
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
# CONFIG_RTC_DRV_ZYNQMP is not set

#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_MESON_VRTC=y
CONFIG_RTC_DRV_PL030=m
CONFIG_RTC_DRV_PL031=m
CONFIG_RTC_DRV_SUN6I=y
# CONFIG_RTC_DRV_CADENCE is not set
# CONFIG_RTC_DRV_FTRTC010 is not set
# CONFIG_RTC_DRV_R7301 is not set

#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
CONFIG_AMBA_PL08X=y
# CONFIG_BCM_SBA_RAID is not set
CONFIG_DMA_SUN6I=y
CONFIG_DW_AXI_DMAC=y
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_HISI_DMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_MV_XOR_V2 is not set
CONFIG_PL330_DMA=y
# CONFIG_PLX_DMA is not set
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
# CONFIG_XILINX_ZYNQMP_DPDMA is not set
# CONFIG_QCOM_HIDMA_MGMT is not set
# CONFIG_QCOM_HIDMA is not set
CONFIG_DW_DMAC_CORE=y
CONFIG_DW_DMAC=y
# CONFIG_DW_DMAC_PCI is not set
CONFIG_DW_EDMA=y
# CONFIG_DW_EDMA_PCIE is not set
# CONFIG_SF_PDMA is not set

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_SELFTESTS is not set
# CONFIG_DMABUF_HEAPS is not set
# end of DMABUF options

CONFIG_AUXDISPLAY=y
CONFIG_HD44780=m
CONFIG_IMG_ASCII_LCD=m
CONFIG_HT16K33=m
CONFIG_TM1628=m
CONFIG_OPENVFD=m
# CONFIG_PANEL_CHANGE_MESSAGE is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_CHARLCD=m
# CONFIG_UIO is not set
# CONFIG_VFIO is not set
CONFIG_VIRT_DRIVERS=y
CONFIG_VIRTIO=m
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=m
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
# CONFIG_VDPA is not set
CONFIG_VHOST_IOTLB=m
CONFIG_VHOST=m
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_SCSI=m
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set

#
# Microsoft Hyper-V guest support
#
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
CONFIG_STAGING=y
CONFIG_PRISM2_USB=m
# CONFIG_COMEDI is not set
CONFIG_RTL8192U=m
CONFIG_RTLLIB=m
CONFIG_RTLLIB_CRYPTO_CCMP=m
CONFIG_RTLLIB_CRYPTO_TKIP=m
CONFIG_RTLLIB_CRYPTO_WEP=m
# CONFIG_RTL8192E is not set
CONFIG_RTL8723BS=m
CONFIG_R8712U=m
CONFIG_R8188EU=m
CONFIG_88EU_AP_MODE=y
# CONFIG_RTS5208 is not set
CONFIG_VT6655=m
CONFIG_VT6656=m

#
# IIO staging drivers
#

#
# Accelerometers
#
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16240 is not set
# end of Accelerometers

#
# Analog to digital converters
#
# CONFIG_AD7816 is not set
# CONFIG_AD7280 is not set
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
# CONFIG_ADT7316 is not set
# end of Analog digital bi-direction converters

#
# Capacitance to digital converters
#
# CONFIG_AD7150 is not set
# CONFIG_AD7746 is not set
# end of Capacitance to digital converters

#
# Direct Digital Synthesis
#
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
# CONFIG_AD5933 is not set
# end of Network Analyzer, Impedance Converters

#
# Active energy metering IC
#
# CONFIG_ADE7854 is not set
# end of Active energy metering IC

#
# Resolver to digital converters
#
# CONFIG_AD2S1210 is not set
# end of Resolver to digital converters
# end of IIO staging drivers

# CONFIG_FB_SM750 is not set
CONFIG_STAGING_MEDIA=y
# CONFIG_VIDEO_HANTRO is not set
CONFIG_VIDEO_MESON_VDEC=m
CONFIG_VIDEO_ROCKCHIP_VDEC=m
CONFIG_VIDEO_SUNXI=y
CONFIG_VIDEO_SUNXI_CEDRUS=m
# CONFIG_VIDEO_ZORAN is not set
# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set

#
# Android
#
# end of Android

# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
# CONFIG_GS_FPGABOOT is not set
# CONFIG_UNISYSSPAR is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
# CONFIG_FB_TFT is not set
# CONFIG_FUSB_30X is not set
# CONFIG_KS7010 is not set
CONFIG_PI433=m

#
# Gasket devices
#
# CONFIG_STAGING_GASKET_FRAMEWORK is not set
# end of Gasket devices

# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_QLGE is not set
# CONFIG_WFX is not set
# CONFIG_SPMI_HISI3670 is not set
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
CONFIG_SURFACE_PLATFORMS=y
CONFIG_HAVE_CLK=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
CONFIG_COMMON_CLK_CS2000_CP=y
# CONFIG_CLK_QORIQ is not set
# CONFIG_COMMON_CLK_XGENE is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set

#
# Clock support for Amlogic platforms
#
CONFIG_COMMON_CLK_MESON_REGMAP=y
CONFIG_COMMON_CLK_MESON_DUALDIV=y
CONFIG_COMMON_CLK_MESON_MPLL=y
CONFIG_COMMON_CLK_MESON_PHASE=y
CONFIG_COMMON_CLK_MESON_PLL=y
CONFIG_COMMON_CLK_MESON_SCLK_DIV=y
CONFIG_COMMON_CLK_MESON_VID_PLL_DIV=y
CONFIG_COMMON_CLK_MESON_AO_CLKC=y
CONFIG_COMMON_CLK_MESON_EE_CLKC=y
CONFIG_COMMON_CLK_MESON_CPU_DYNDIV=y
CONFIG_COMMON_CLK_GXBB=y
CONFIG_COMMON_CLK_AXG=y
CONFIG_COMMON_CLK_AXG_AUDIO=y
CONFIG_COMMON_CLK_G12A=y
# end of Clock support for Amlogic platforms

CONFIG_COMMON_CLK_ROCKCHIP=y
CONFIG_CLK_PX30=y
CONFIG_CLK_RV110X=y
CONFIG_CLK_RK3036=y
CONFIG_CLK_RK312X=y
CONFIG_CLK_RK3188=y
CONFIG_CLK_RK322X=y
CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
CONFIG_CLK_RK3399=y
CONFIG_CLK_SUNXI=y
CONFIG_CLK_SUNXI_CLOCKS=y
CONFIG_CLK_SUNXI_PRCM_SUN6I=y
CONFIG_CLK_SUNXI_PRCM_SUN8I=y
CONFIG_CLK_SUNXI_PRCM_SUN9I=y
CONFIG_SUNXI_CCU=y
CONFIG_SUN50I_A64_CCU=y
CONFIG_SUN50I_A100_CCU=y
CONFIG_SUN50I_A100_R_CCU=y
CONFIG_SUN50I_H6_CCU=y
CONFIG_SUN50I_H6_R_CCU=y
CONFIG_SUN8I_A83T_CCU=y
CONFIG_SUN8I_H3_CCU=y
CONFIG_SUN8I_DE2_CCU=y
CONFIG_SUN8I_R_CCU=y
CONFIG_HWSPINLOCK=y

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_ACPI=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
CONFIG_MICROCHIP_PIT64B=y
# end of Clock Source drivers

CONFIG_MAILBOX=y
CONFIG_ARM_MHU=y
CONFIG_PLATFORM_MHU=y
CONFIG_PL320_MBOX=y
CONFIG_ROCKCHIP_MBOX=y
# CONFIG_PCC is not set
CONFIG_ALTERA_MBOX=m
# CONFIG_MAILBOX_TEST is not set
CONFIG_SUN6I_MSGBOX=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_SUN50I_IOMMU=y
CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
CONFIG_ARM_SMMU_V3=y
CONFIG_ARM_SMMU_V3_SVA=y
CONFIG_VIRTIO_IOMMU=m

#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=m
CONFIG_RPMSG_CHAR=m
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
CONFIG_RPMSG_VIRTIO=m
# end of Rpmsg drivers

# CONFIG_SOUNDWIRE is not set

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
CONFIG_MESON_CANVAS=y
CONFIG_MESON_CLK_MEASURE=y
CONFIG_MESON_GX_SOCINFO=y
CONFIG_MESON_GX_PM_DOMAINS=y
CONFIG_MESON_EE_PM_DOMAINS=y
CONFIG_MESON_SECURE_PM_DOMAINS=y
# CONFIG_MESON_MX_SOCINFO is not set
# end of Amlogic SoC drivers

#
# Aspeed SoC drivers
#
# end of Aspeed SoC drivers

#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
CONFIG_QUICC_ENGINE=y
# end of NXP/Freescale QorIQ SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Qualcomm SoC drivers
#
# end of Qualcomm SoC drivers

CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_SUNXI_SRAM=y
# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# CONFIG_XILINX_VCU is not set
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=m
CONFIG_DEVFREQ_GOV_USERSPACE=m
CONFIG_DEVFREQ_GOV_PASSIVE=m

#
# DEVFREQ Drivers
#
CONFIG_ARM_RK3328_DMC_DEVFREQ=y
CONFIG_ARM_RK3399_DMC_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
# CONFIG_EXTCON_ADC_JACK is not set
# CONFIG_EXTCON_FSA9480 is not set
CONFIG_EXTCON_GPIO=m
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_PTN5150 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
CONFIG_EXTCON_USB_GPIO=m
CONFIG_MEMORY=y
CONFIG_ARM_PL172_MPMC=m
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
# CONFIG_IIO_BUFFER_DMA is not set
# CONFIG_IIO_BUFFER_DMAENGINE is not set
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
# CONFIG_IIO_TRIGGERED_EVENT is not set

#
# Accelerometers
#
# CONFIG_ADIS16201 is not set
# CONFIG_ADIS16209 is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
# CONFIG_ADXL372_SPI is not set
# CONFIG_ADXL372_I2C is not set
# CONFIG_BMA180 is not set
# CONFIG_BMA220 is not set
# CONFIG_BMA400 is not set
# CONFIG_BMC150_ACCEL is not set
# CONFIG_DA280 is not set
# CONFIG_DA311 is not set
# CONFIG_DMARD06 is not set
# CONFIG_DMARD09 is not set
# CONFIG_DMARD10 is not set
# CONFIG_HID_SENSOR_ACCEL_3D is not set
# CONFIG_IIO_ST_ACCEL_3AXIS is not set
# CONFIG_KXSD9 is not set
# CONFIG_KXCJK1013 is not set
# CONFIG_MC3230 is not set
# CONFIG_MMA7455_I2C is not set
# CONFIG_MMA7455_SPI is not set
# CONFIG_MMA7660 is not set
# CONFIG_MMA8452 is not set
# CONFIG_MMA9551 is not set
# CONFIG_MMA9553 is not set
# CONFIG_MXC4005 is not set
# CONFIG_MXC6255 is not set
# CONFIG_SCA3000 is not set
# CONFIG_STK8312 is not set
# CONFIG_STK8BA50 is not set
# end of Accelerometers

#
# Analog to digital converters
#
# CONFIG_AD7091R5 is not set
# CONFIG_AD7124 is not set
# CONFIG_AD7192 is not set
# CONFIG_AD7266 is not set
# CONFIG_AD7291 is not set
# CONFIG_AD7292 is not set
# CONFIG_AD7298 is not set
# CONFIG_AD7476 is not set
# CONFIG_AD7606_IFACE_PARALLEL is not set
# CONFIG_AD7606_IFACE_SPI is not set
# CONFIG_AD7766 is not set
# CONFIG_AD7768_1 is not set
# CONFIG_AD7780 is not set
# CONFIG_AD7791 is not set
# CONFIG_AD7793 is not set
# CONFIG_AD7887 is not set
# CONFIG_AD7923 is not set
# CONFIG_AD7949 is not set
# CONFIG_AD799X is not set
# CONFIG_ADI_AXI_ADC is not set
CONFIG_AXP20X_ADC=y
CONFIG_AXP288_ADC=y
# CONFIG_CC10001_ADC is not set
# CONFIG_ENVELOPE_DETECTOR is not set
# CONFIG_HI8435 is not set
# CONFIG_HX711 is not set
# CONFIG_INA2XX_ADC is not set
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2496 is not set
# CONFIG_LTC2497 is not set
# CONFIG_MAX1027 is not set
# CONFIG_MAX11100 is not set
# CONFIG_MAX1118 is not set
# CONFIG_MAX1241 is not set
# CONFIG_MAX1363 is not set
# CONFIG_MAX9611 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
# CONFIG_MCP3911 is not set
CONFIG_MESON_SARADC=y
# CONFIG_NAU7802 is not set
# CONFIG_QCOM_SPMI_IADC is not set
# CONFIG_QCOM_SPMI_VADC is not set
# CONFIG_QCOM_SPMI_ADC5 is not set
CONFIG_ROCKCHIP_SARADC=y
# CONFIG_SD_ADC_MODULATOR is not set
# CONFIG_TI_ADC081C is not set
# CONFIG_TI_ADC0832 is not set
# CONFIG_TI_ADC084S021 is not set
# CONFIG_TI_ADC12138 is not set
# CONFIG_TI_ADC108S102 is not set
# CONFIG_TI_ADC128S052 is not set
# CONFIG_TI_ADC161S626 is not set
# CONFIG_TI_ADS1015 is not set
# CONFIG_TI_ADS7950 is not set
# CONFIG_TI_ADS8344 is not set
# CONFIG_TI_ADS8688 is not set
# CONFIG_TI_ADS124S08 is not set
# CONFIG_TI_TLC4541 is not set
# CONFIG_VF610_ADC is not set
# CONFIG_XILINX_XADC is not set
# end of Analog to digital converters

#
# Analog to digital and digital to analog converters
#

#
# Analog Front Ends
#
# CONFIG_IIO_RESCALE is not set
# end of Analog Front Ends

#
# Amplifiers
#
# CONFIG_AD8366 is not set
# CONFIG_HMC425 is not set
# end of Amplifiers

#
# Chemical Sensors
#
# CONFIG_ATLAS_PH_SENSOR is not set
# CONFIG_ATLAS_EZO_SENSOR is not set
# CONFIG_BME680 is not set
# CONFIG_CCS811 is not set
# CONFIG_IAQCORE is not set
# CONFIG_PMS7003 is not set
# CONFIG_SCD30_CORE is not set
# CONFIG_SENSIRION_SGP30 is not set
# CONFIG_SPS30 is not set
# CONFIG_VZ89X is not set
# end of Chemical Sensors

#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
# end of Hid Sensor IIO Common

#
# SSP Sensor Common
#
# CONFIG_IIO_SSP_SENSORHUB is not set
# end of SSP Sensor Common

#
# Digital to analog converters
#
# CONFIG_AD5064 is not set
# CONFIG_AD5360 is not set
# CONFIG_AD5380 is not set
# CONFIG_AD5421 is not set
# CONFIG_AD5446 is not set
# CONFIG_AD5449 is not set
# CONFIG_AD5592R is not set
# CONFIG_AD5593R is not set
# CONFIG_AD5504 is not set
# CONFIG_AD5624R_SPI is not set
# CONFIG_AD5686_SPI is not set
# CONFIG_AD5696_I2C is not set
# CONFIG_AD5755 is not set
# CONFIG_AD5758 is not set
# CONFIG_AD5761 is not set
# CONFIG_AD5764 is not set
# CONFIG_AD5770R is not set
# CONFIG_AD5791 is not set
# CONFIG_AD7303 is not set
# CONFIG_AD8801 is not set
# CONFIG_DPOT_DAC is not set
# CONFIG_DS4424 is not set
# CONFIG_LTC1660 is not set
# CONFIG_LTC2632 is not set
# CONFIG_M62332 is not set
# CONFIG_MAX517 is not set
# CONFIG_MAX5821 is not set
# CONFIG_MCP4725 is not set
# CONFIG_MCP4922 is not set
# CONFIG_TI_DAC082S085 is not set
# CONFIG_TI_DAC5571 is not set
# CONFIG_TI_DAC7311 is not set
# CONFIG_TI_DAC7612 is not set
# CONFIG_VF610_DAC is not set
# end of Digital to analog converters

#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
# CONFIG_AD9523 is not set
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
# CONFIG_ADF4350 is not set
# CONFIG_ADF4371 is not set
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
# CONFIG_ADIS16080 is not set
# CONFIG_ADIS16130 is not set
# CONFIG_ADIS16136 is not set
# CONFIG_ADIS16260 is not set
# CONFIG_ADXRS290 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_BMG160 is not set
# CONFIG_FXAS21002C is not set
# CONFIG_HID_SENSOR_GYRO_3D is not set
# CONFIG_MPU3050_I2C is not set
# CONFIG_IIO_ST_GYRO_3AXIS is not set
# CONFIG_ITG3200 is not set
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
# CONFIG_MAX30100 is not set
# CONFIG_MAX30102 is not set
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
# CONFIG_AM2315 is not set
# CONFIG_DHT11 is not set
# CONFIG_HDC100X is not set
# CONFIG_HDC2010 is not set
# CONFIG_HID_SENSOR_HUMIDITY is not set
# CONFIG_HTS221 is not set
# CONFIG_HTU21 is not set
# CONFIG_SI7005 is not set
# CONFIG_SI7020 is not set
# end of Humidity sensors

#
# Inertial measurement units
#
# CONFIG_ADIS16400 is not set
# CONFIG_ADIS16460 is not set
# CONFIG_ADIS16475 is not set
# CONFIG_ADIS16480 is not set
# CONFIG_BMI160_I2C is not set
# CONFIG_BMI160_SPI is not set
# CONFIG_FXOS8700_I2C is not set
# CONFIG_FXOS8700_SPI is not set
# CONFIG_KMX61 is not set
# CONFIG_INV_ICM42600_I2C is not set
# CONFIG_INV_ICM42600_SPI is not set
# CONFIG_INV_MPU6050_I2C is not set
# CONFIG_INV_MPU6050_SPI is not set
# CONFIG_IIO_ST_LSM6DSX is not set
# end of Inertial measurement units

#
# Light sensors
#
# CONFIG_ACPI_ALS is not set
# CONFIG_ADJD_S311 is not set
# CONFIG_ADUX1020 is not set
# CONFIG_AL3010 is not set
# CONFIG_AL3320A is not set
# CONFIG_APDS9300 is not set
# CONFIG_APDS9960 is not set
# CONFIG_AS73211 is not set
# CONFIG_BH1750 is not set
# CONFIG_BH1780 is not set
# CONFIG_CM32181 is not set
# CONFIG_CM3232 is not set
# CONFIG_CM3323 is not set
# CONFIG_CM3605 is not set
# CONFIG_CM36651 is not set
# CONFIG_GP2AP002 is not set
# CONFIG_GP2AP020A00F is not set
# CONFIG_SENSORS_ISL29018 is not set
# CONFIG_SENSORS_ISL29028 is not set
# CONFIG_ISL29125 is not set
# CONFIG_HID_SENSOR_ALS is not set
# CONFIG_HID_SENSOR_PROX is not set
# CONFIG_JSA1212 is not set
# CONFIG_RPR0521 is not set
# CONFIG_LTR501 is not set
# CONFIG_LV0104CS is not set
# CONFIG_MAX44000 is not set
# CONFIG_MAX44009 is not set
# CONFIG_NOA1305 is not set
# CONFIG_OPT3001 is not set
# CONFIG_PA12203001 is not set
# CONFIG_SI1133 is not set
# CONFIG_SI1145 is not set
# CONFIG_STK3310 is not set
# CONFIG_ST_UVIS25 is not set
# CONFIG_TCS3414 is not set
# CONFIG_TCS3472 is not set
# CONFIG_SENSORS_TSL2563 is not set
# CONFIG_TSL2583 is not set
# CONFIG_TSL2772 is not set
# CONFIG_TSL4531 is not set
# CONFIG_US5182D is not set
# CONFIG_VCNL4000 is not set
# CONFIG_VCNL4035 is not set
# CONFIG_VEML6030 is not set
# CONFIG_VEML6070 is not set
# CONFIG_VL6180 is not set
# CONFIG_ZOPT2201 is not set
# end of Light sensors

#
# Magnetometer sensors
#
# CONFIG_AK8974 is not set
# CONFIG_AK8975 is not set
# CONFIG_AK09911 is not set
# CONFIG_BMC150_MAGN_I2C is not set
# CONFIG_BMC150_MAGN_SPI is not set
# CONFIG_MAG3110 is not set
# CONFIG_HID_SENSOR_MAGNETOMETER_3D is not set
# CONFIG_MMC35240 is not set
# CONFIG_IIO_ST_MAGN_3AXIS is not set
# CONFIG_SENSORS_HMC5843_I2C is not set
# CONFIG_SENSORS_HMC5843_SPI is not set
# CONFIG_SENSORS_RM3100_I2C is not set
# CONFIG_SENSORS_RM3100_SPI is not set
# end of Magnetometer sensors

#
# Multiplexers
#
# CONFIG_IIO_MUX is not set
# end of Multiplexers

#
# Inclinometer sensors
#
# CONFIG_HID_SENSOR_INCLINOMETER_3D is not set
# CONFIG_HID_SENSOR_DEVICE_ROTATION is not set
# end of Inclinometer sensors

#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=m
CONFIG_IIO_INTERRUPT_TRIGGER=m
CONFIG_IIO_TIGHTLOOP_TRIGGER=m
CONFIG_IIO_SYSFS_TRIGGER=y
# end of Triggers - standalone

#
# Linear and angular position sensors
#
# end of Linear and angular position sensors

#
# Digital potentiometers
#
# CONFIG_AD5272 is not set
# CONFIG_DS1803 is not set
# CONFIG_MAX5432 is not set
# CONFIG_MAX5481 is not set
# CONFIG_MAX5487 is not set
# CONFIG_MCP4018 is not set
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
# CONFIG_MCP41010 is not set
# CONFIG_TPL0102 is not set
# end of Digital potentiometers

#
# Digital potentiostats
#
# CONFIG_LMP91000 is not set
# end of Digital potentiostats

#
# Pressure sensors
#
# CONFIG_ABP060MG is not set
# CONFIG_BMP280 is not set
# CONFIG_DLHL60D is not set
# CONFIG_DPS310 is not set
# CONFIG_HID_SENSOR_PRESS is not set
# CONFIG_HP03 is not set
# CONFIG_ICP10100 is not set
# CONFIG_MPL115_I2C is not set
# CONFIG_MPL115_SPI is not set
# CONFIG_MPL3115 is not set
# CONFIG_MS5611 is not set
# CONFIG_MS5637 is not set
# CONFIG_IIO_ST_PRESS is not set
# CONFIG_T5403 is not set
# CONFIG_HP206C is not set
# CONFIG_ZPA2326 is not set
# end of Pressure sensors

#
# Lightning sensors
#
# CONFIG_AS3935 is not set
# end of Lightning sensors

#
# Proximity and distance sensors
#
# CONFIG_ISL29501 is not set
# CONFIG_LIDAR_LITE_V2 is not set
# CONFIG_MB1232 is not set
# CONFIG_PING is not set
# CONFIG_RFD77402 is not set
# CONFIG_SRF04 is not set
# CONFIG_SX9310 is not set
# CONFIG_SX9500 is not set
# CONFIG_SRF08 is not set
# CONFIG_VCNL3020 is not set
# CONFIG_VL53L0X_I2C is not set
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
# CONFIG_AD2S90 is not set
# CONFIG_AD2S1200 is not set
# end of Resolver to digital converters

#
# Temperature sensors
#
# CONFIG_LTC2983 is not set
# CONFIG_MAXIM_THERMOCOUPLE is not set
# CONFIG_HID_SENSOR_TEMP is not set
# CONFIG_MLX90614 is not set
# CONFIG_MLX90632 is not set
# CONFIG_TMP006 is not set
# CONFIG_TMP007 is not set
# CONFIG_TSYS01 is not set
# CONFIG_TSYS02D is not set
# CONFIG_MAX31856 is not set
# end of Temperature sensors

# CONFIG_NTB is not set
# CONFIG_VME_BUS is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_FSL_FTM is not set
CONFIG_PWM_MESON=y
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_SUN4I=y

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_AL_FIC is not set
CONFIG_PARTITION_PERCPU=y
CONFIG_MESON_IRQ_GPIO=y
# end of IRQ chip support

# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_MESON=y
CONFIG_RESET_MESON_AUDIO_ARB=y
CONFIG_RESET_SCMI=y
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SUNXI=y
# CONFIG_RESET_TI_SYSCON is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_PHY_XGENE is not set
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_SUN6I_MIPI_DPHY=y
CONFIG_PHY_SUN9I_USB=y
CONFIG_PHY_SUN50I_USB3=y
CONFIG_PHY_MESON8B_USB2=y
CONFIG_PHY_MESON_GXL_USB2=y
CONFIG_PHY_MESON_G12A_USB2=y
CONFIG_PHY_MESON_G12A_USB3_PCIE=y
CONFIG_PHY_MESON_AXG_PCIE=y
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_FSL_IMX8MQ_USB is not set
# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
# CONFIG_PHY_QCOM_USB_HS is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
CONFIG_PHY_ROCKCHIP_DP=y
CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
CONFIG_PHY_ROCKCHIP_INNO_USB3=y
CONFIG_PHY_ROCKCHIP_PCIE=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PHY_ROCKCHIP_USB=y
# CONFIG_PHY_SAMSUNG_USB2 is not set
# CONFIG_PHY_TUSB1210 is not set
# end of PHY Subsystem

# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCI400_PMU=y
CONFIG_ARM_CCI5xx_PMU=y
CONFIG_ARM_CCN=m
CONFIG_ARM_CMN=m
CONFIG_ARM_PMU=y
CONFIG_ARM_PMU_ACPI=y
# CONFIG_ARM_SMMU_V3_PMU is not set
CONFIG_ARM_DSU_PMU=m
CONFIG_ARM_SPE_PMU=m
# CONFIG_HISI_PMU is not set
# end of Performance monitor support

CONFIG_RAS=y
# CONFIG_USB4 is not set

#
# Android
#
# CONFIG_ANDROID is not set
# end of Android

# CONFIG_LIBNVDIMM is not set
CONFIG_DAX=y
CONFIG_DEV_DAX=m
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_MESON_EFUSE=y
# CONFIG_MESON_MX_EFUSE is not set

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# end of HW tracing support

# CONFIG_FPGA is not set
# CONFIG_FSI is not set
CONFIG_TEE=y

#
# TEE drivers
#
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
# end of TEE drivers

CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
# CONFIG_MUX_ADGS1408 is not set
CONFIG_MUX_GPIO=m
CONFIG_MUX_MMIO=m
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set
# CONFIG_INTERCONNECT is not set
CONFIG_COUNTER=m
# CONFIG_FTM_QUADDEC is not set
# CONFIG_MICROCHIP_TCB_CAPTURE is not set
# CONFIG_MOST is not set
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_IOMAP=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=m
# CONFIG_REISERFS_CHECK is not set
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
# CONFIG_JFS_DEBUG is not set
# CONFIG_JFS_STATISTICS is not set
CONFIG_XFS_FS=y
CONFIG_XFS_SUPPORT_V4=y
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
# CONFIG_XFS_RT is not set
# CONFIG_XFS_ONLINE_SCRUB is not set
# CONFIG_XFS_WARN is not set
# CONFIG_XFS_DEBUG is not set
CONFIG_GFS2_FS=m
CONFIG_GFS2_FS_LOCKING_DLM=y
CONFIG_OCFS2_FS=m
CONFIG_OCFS2_FS_O2CB=m
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
CONFIG_OCFS2_FS_STATS=y
CONFIG_OCFS2_DEBUG_MASKLOG=y
# CONFIG_OCFS2_DEBUG_FS is not set
CONFIG_BTRFS_FS=y
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
# CONFIG_BTRFS_FS_REF_VERIFY is not set
CONFIG_NILFS2_FS=m
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
# CONFIG_F2FS_FAULT_INJECTION is not set
CONFIG_F2FS_FS_COMPRESSION=y
CONFIG_F2FS_FS_LZO=y
CONFIG_F2FS_FS_LZ4=y
CONFIG_F2FS_FS_ZSTD=y
CONFIG_F2FS_FS_LZORLE=y
CONFIG_FS_DAX=y
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_MANDATORY_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
CONFIG_PRINT_QUOTA_WARNING=y
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
CONFIG_AUTOFS4_FS=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_VIRTIO_FS=m
CONFIG_OVERLAY_FS=y
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set

#
# Caches
#
CONFIG_FSCACHE=y
# CONFIG_FSCACHE_STATS is not set
# CONFIG_FSCACHE_HISTOGRAM is not set
# CONFIG_FSCACHE_DEBUG is not set
# CONFIG_FSCACHE_OBJECT_LIST is not set
CONFIG_CACHEFILES=m
# CONFIG_CACHEFILES_DEBUG is not set
# CONFIG_CACHEFILES_HISTOGRAM is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_EXFAT_FS=y
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_NTFS_FS is not set
CONFIG_NTFS3_FS=m
# CONFIG_NTFS3_64BIT_CLUSTER is not set
CONFIG_NTFS3_LZX_XPRESS=y
# CONFIG_NTFS3_FS_POSIX_ACL is not set
# end of DOS/FAT/EXFAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_TMPFS_INODE64 is not set
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_MEMFD_CREATE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=m
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
CONFIG_ECRYPT_FS=m
# CONFIG_ECRYPT_FS_MESSAGING is not set
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
CONFIG_UBIFS_FS=m
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
CONFIG_CRAMFS=m
CONFIG_CRAMFS_BLOCKDEV=y
# CONFIG_CRAMFS_MTD is not set
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_FILE_CACHE is not set
CONFIG_SQUASHFS_FILE_DIRECT=y
# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_ZSTD=y
CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFLATE_COMPRESS=y
CONFIG_PSTORE_LZO_COMPRESS=y
CONFIG_PSTORE_LZ4_COMPRESS=y
CONFIG_PSTORE_LZ4HC_COMPRESS=y
CONFIG_PSTORE_842_COMPRESS=y
CONFIG_PSTORE_ZSTD_COMPRESS=y
CONFIG_PSTORE_COMPRESS=y
CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set
CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
# CONFIG_PSTORE_CONSOLE is not set
# CONFIG_PSTORE_PMSG is not set
# CONFIG_PSTORE_RAM is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_EROFS_FS=m
# CONFIG_EROFS_FS_DEBUG is not set
CONFIG_EROFS_FS_XATTR=y
CONFIG_EROFS_FS_POSIX_ACL=y
# CONFIG_EROFS_FS_SECURITY is not set
CONFIG_EROFS_FS_ZIP=y
CONFIG_EROFS_FS_CLUSTER_PAGE_LIMIT=1
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V2=m
CONFIG_NFS_V3=m
# CONFIG_NFS_V3_ACL is not set
CONFIG_NFS_V4=m
# CONFIG_NFS_SWAP is not set
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=m
CONFIG_PNFS_BLOCK=m
CONFIG_PNFS_FLEXFILE_LAYOUT=m
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
# CONFIG_NFS_V4_1_MIGRATION is not set
CONFIG_NFS_V4_SECURITY_LABEL=y
CONFIG_NFS_FSCACHE=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DEBUG=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
# CONFIG_NFS_V4_2_READ_PLUS is not set
CONFIG_NFSD=m
# CONFIG_NFSD_V2 is not set
# CONFIG_NFSD_V3_ACL is not set
CONFIG_NFSD_V4=y
# CONFIG_NFSD_BLOCKLAYOUT is not set
# CONFIG_NFSD_SCSILAYOUT is not set
# CONFIG_NFSD_FLEXFILELAYOUT is not set
CONFIG_NFSD_V4_2_INTER_SSC=y
# CONFIG_NFSD_V4_SECURITY_LABEL is not set
CONFIG_GRACE_PERIOD=m
CONFIG_LOCKD=m
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_NFS_V4_2_SSC_HELPER=y
CONFIG_SUNRPC=m
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_BACKCHANNEL=y
CONFIG_RPCSEC_GSS_KRB5=m
# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
CONFIG_SUNRPC_DEBUG=y
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
# CONFIG_CEPH_FS_SECURITY_LABEL is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
# CONFIG_CIFS_WEAK_PW_HASH is not set
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CIFS_DEBUG=y
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
CONFIG_CIFS_DFS_UPCALL=y
# CONFIG_CIFS_FSCACHE is not set
CONFIG_CODA_FS=m
CONFIG_AFS_FS=m
# CONFIG_AFS_DEBUG is not set
CONFIG_AFS_FSCACHE=y
# CONFIG_AFS_DEBUG_CURSOR is not set
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
CONFIG_9P_FS_SECURITY=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf-8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=m
CONFIG_NLS_MAC_GAELIC=m
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=y
CONFIG_DLM=m
# CONFIG_DLM_DEBUG is not set
# CONFIG_UNICODE is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_BIG_KEYS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_PROC_MEM_ALWAYS_FORCE=y
# CONFIG_PROC_MEM_FORCE_PTRACE is not set
# CONFIG_PROC_MEM_NO_FORCE is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
# CONFIG_SECURITY_NETWORK_XFRM is not set
CONFIG_SECURITY_PATH=y
CONFIG_LSM_MMAP_MIN_ADDR=32768
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
# CONFIG_SECURITY_SELINUX_DISABLE is not set
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
CONFIG_SECURITY_APPARMOR=y
CONFIG_SECURITY_APPARMOR_HASH=y
CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
# CONFIG_SECURITY_APPARMOR_DEBUG is not set
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
CONFIG_INTEGRITY_AUDIT=y
# CONFIG_IMA is not set
# CONFIG_EVM is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
CONFIG_INIT_STACK_NONE=y
# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
# CONFIG_INIT_STACK_ALL_PATTERN is not set
# CONFIG_INIT_STACK_ALL_ZERO is not set
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
# end of Memory initialization
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=y
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=y
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_ENGINE=y

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
CONFIG_CRYPTO_ECRDSA=y
CONFIG_CRYPTO_SM2=y
CONFIG_CRYPTO_CURVE25519=y

#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_AEGIS128=y
CONFIG_CRYPTO_AEGIS128_SIMD=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=y

#
# Block modes
#
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_KEYWRAP=y
CONFIG_CRYPTO_NHPOLY1305=y
CONFIG_CRYPTO_ADIANTUM=y
CONFIG_CRYPTO_ESSIV=y

#
# Hash modes
#
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_VMAC=y

#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_XXHASH=y
CONFIG_CRYPTO_BLAKE2B=y
CONFIG_CRYPTO_BLAKE2S=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=y
# CONFIG_CRYPTO_RMD128 is not set
CONFIG_CRYPTO_RMD160=y
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_STREEBOG=y
# CONFIG_CRYPTO_TGR192 is not set
CONFIG_CRYPTO_WP512=y

#
# Ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
CONFIG_CRYPTO_ANUBIS=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_BLOWFISH_COMMON=y
CONFIG_CRYPTO_CAMELLIA=y
CONFIG_CRYPTO_CAST_COMMON=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=y
CONFIG_CRYPTO_KHAZAD=y
# CONFIG_CRYPTO_SALSA20 is not set
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_SEED=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=y
CONFIG_CRYPTO_ZSTD=y

#
# Random Number Generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
CONFIG_CRYPTO_STATS=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_ALLWINNER=y
CONFIG_CRYPTO_DEV_SUN4I_SS=y
CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_CE=y
CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG=y
CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
CONFIG_CRYPTO_DEV_SUN8I_SS=y
CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG=y
CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_CCP is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_ROCKCHIP=y
CONFIG_CRYPTO_DEV_VIRTIO=m
CONFIG_CRYPTO_DEV_CRYPTODEV_LINUX=m
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
CONFIG_CRYPTO_DEV_CCREE=y
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG=y
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
CONFIG_PKCS7_MESSAGE_PARSER=y
CONFIG_PKCS7_TEST_KEY=m
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

#
# Library routines
#
CONFIG_RAID6_PQ=y
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=m
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
CONFIG_INDIRECT_PIO=y

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
CONFIG_CRYPTO_LIB_CURVE25519=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines

CONFIG_LIB_MEMNEQ=y
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=m
CONFIG_CRC4=m
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=m
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
CONFIG_RANDOM32_SELFTEST=y
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
# CONFIG_XZ_DEC_SPARC is not set
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_INTERVAL_TREE=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_SWIOTLB=y
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y
# CONFIG_DMA_PERNUMA_CMA is not set

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=256
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
CONFIG_SGL_ALLOC=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_ARCH_STACKWALK=y
CONFIG_SBITMAP=y
# CONFIG_STRING_SELFTEST is not set
# end of Library routines

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_CALLER is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

#
# Compile-time checks and compiler options
#
# CONFIG_DEBUG_INFO is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=2048
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_READABLE_ASM is not set
CONFIG_HEADERS_INSTALL=y
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_KCSAN_COMPILER=y
# end of Generic Kernel Debugging Instruments

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
# end of Memory Debugging

# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SOFTLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHED_INFO=y
# CONFIG_SCHEDSTATS is not set
# end of Scheduler Debugging

# CONFIG_DEBUG_TIMEKEEPING is not set
CONFIG_DEBUG_PREEMPT=y

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

# CONFIG_STACKTRACE is not set
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_HAVE_DEBUG_BUGVERBOSE=y

#
# Debug kernel data structures
#
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# end of Debug kernel data structures

# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
# CONFIG_RCU_SCALE_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_LATENCYTOP is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_SAMPLES is not set
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
# CONFIG_STRICT_DEVMEM is not set

#
# arm64 Debugging
#
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
# end of arm64 Debugging

#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
CONFIG_FUNCTION_ERROR_INJECTION=y
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_LKDTM is not set
# CONFIG_TEST_LIST_SORT is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_SORT is not set
# CONFIG_KPROBES_SANITY_TEST is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_ASYNC_RAID6_TEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_STRSCPY is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_OVERFLOW is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_HASH is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_VMALLOC is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_BPF is not set
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_STACKINIT is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_FREE_PAGES is not set
CONFIG_MEMTEST=y
# end of Kernel Testing and Coverage
# end of Kernel hacking


================================================
FILE: kernel-config/release/stable/config-5.15
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 5.15.202 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 15.2.Rel1 (Build arm-15.86)) 15.2.1 20251203"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=150201
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=24501
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=24501
CONFIG_LLD_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_PAHOLE_VERSION=130
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
# CONFIG_UAPI_HEADER_TEST is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
# CONFIG_WATCH_QUEUE is not set
# CONFIG_CROSS_MEMORY_ATTACH is not set
# CONFIG_USELIB is not set
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_INJECTION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem

CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_HZ_PERIODIC=y
# CONFIG_NO_HZ_IDLE is not set
# CONFIG_NO_HZ_FULL is not set
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y

#
# BPF subsystem
#
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_JIT=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
CONFIG_BPF_JIT_DEFAULT_ON=y
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
# CONFIG_BPF_PRELOAD is not set
# CONFIG_BPF_LSM is not set
# end of BPF subsystem

# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_PREEMPTION=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_SCHED_THERMAL_PRESSURE=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_PSI=y
# CONFIG_PSI_DEFAULT_DISABLED is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
CONFIG_PREEMPT_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_TASKS_RCU=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
# CONFIG_PRINTK_INDEX is not set
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
# CONFIG_UCLAMP_TASK is not set
# end of Scheduler features

CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_CC_HAS_INT128=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
CONFIG_MEMCG=y
CONFIG_MEMCG_SWAP=y
CONFIG_MEMCG_KMEM=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
CONFIG_CGROUP_MISC=y
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
# CONFIG_CHECKPOINT_RESTORE is not set
CONFIG_SCHED_AUTOGROUP=y
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_HAVE_FUTEX_CMPXCHG=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
CONFIG_KALLSYMS_BASE_RELATIVE=y
# CONFIG_USERFAULTFD is not set
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
# CONFIG_COMPAT_BRK is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
CONFIG_SLAB_FREELIST_RANDOM=y
CONFIG_SLAB_FREELIST_HARDENED=y
CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
CONFIG_SLUB_CPU_PARTIAL=y
CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
# end of General setup

CONFIG_ARM64=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_CONT_PTE_SHIFT=4
CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y

#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
CONFIG_ARCH_SUNXI=y
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_APPLE is not set
# CONFIG_ARCH_BCM2835 is not set
# CONFIG_ARCH_BCM4908 is not set
# CONFIG_ARCH_BCM_IPROC is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
# CONFIG_ARCH_BRCMSTB is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SPARX5 is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LAYERSCAPE is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_KEEMBAY is not set
# CONFIG_ARCH_MEDIATEK is not set
CONFIG_ARCH_MESON=y
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_RENESAS is not set
CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_S32 is not set
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_INTEL_SOCFPGA is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZYNQMP is not set
# end of Platform selection

#
# Kernel Features
#

#
# ARM errata workarounds via the alternatives framework
#
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_834220=y
CONFIG_ARM64_ERRATUM_1742098=y
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1319367=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_ERRATUM_2441007=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_ARM64_ERRATUM_2441009=y
CONFIG_ARM64_ERRATUM_2457168=y
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
CONFIG_ARM64_ERRATUM_2054223=y
CONFIG_ARM64_ERRATUM_2067961=y
CONFIG_ARM64_ERRATUM_3194386=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
CONFIG_QCOM_FALKOR_ERRATUM_1009=y
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
# end of ARM errata workarounds via the alternatives framework

CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
CONFIG_ARM64_VA_BITS_39=y
# CONFIG_ARM64_VA_BITS_48 is not set
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SCHED_MC=y
# CONFIG_SCHED_SMT is not set
CONFIG_NR_CPUS=8
# CONFIG_HOTPLUG_CPU is not set
# CONFIG_NUMA is not set
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
CONFIG_HZ_300=y
# CONFIG_HZ_1000 is not set
CONFIG_HZ=300
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_PARAVIRT=y
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_KEXEC_FILE is not set
# CONFIG_CRASH_DUMP is not set
# CONFIG_XEN is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y

#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
CONFIG_AS_HAS_LDAPR=y
CONFIG_AS_HAS_LSE_ATOMICS=y
# CONFIG_ARM64_USE_LSE_ATOMICS is not set
# end of ARMv8.1 architectural features

#
# ARMv8.2 architectural features
#
# CONFIG_ARM64_PMEM is not set
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features

#
# ARMv8.3 architectural features
#
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
CONFIG_AS_HAS_PAC=y
CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
# end of ARMv8.3 architectural features

#
# ARMv8.4 architectural features
#
CONFIG_ARM64_AMU_EXTN=y
CONFIG_AS_HAS_ARMV8_4=y
CONFIG_ARM64_TLB_RANGE=y
# end of ARMv8.4 architectural features

#
# ARMv8.5 architectural features
#
CONFIG_AS_HAS_ARMV8_5=y
CONFIG_ARM64_BTI=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARCH_RANDOM=y
CONFIG_ARM64_AS_HAS_MTE=y
CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features

#
# ARMv8.7 architectural features
#
CONFIG_ARM64_EPAN=y
# end of ARMv8.7 architectural features

CONFIG_ARM64_SVE=y
CONFIG_ARM64_MODULE_PLTS=y
CONFIG_ARM64_PSEUDO_NMI=y
# CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
# end of Kernel Features

#
# Boot options
#
CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
CONFIG_CMDLINE=""
CONFIG_EFI_STUB=y
CONFIG_EFI=y
CONFIG_DMI=y
# end of Boot options

CONFIG_SYSVIPC_COMPAT=y

#
# Power management options
#
# CONFIG_SUSPEND is not set
# CONFIG_HIBERNATION is not set
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options

#
# CPU Power Management
#

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_IDLE_GOV_LADDER=y
# CONFIG_CPU_IDLE_GOV_MENU is not set
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_DT_IDLE_STATES=y

#
# ARM CPU Idle Drivers
#
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
# end of ARM CPU Idle Drivers
# end of CPU Idle

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_STAT is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_USERSPACE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
# CONFIG_ACPI_CPPC_CPUFREQ is not set
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_SCMI_CPUFREQ=y
# end of CPU Frequency scaling
# end of CPU Power Management

CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_GENERIC_GSI=y
CONFIG_ACPI_CCA_REQUIRED=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
# CONFIG_ACPI_EC_DEBUGFS is not set
CONFIG_ACPI_AC=m
CONFIG_ACPI_BATTERY=m
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_MCFG=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_THERMAL=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_PCI_SLOT=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_CUSTOM_METHOD=m
CONFIG_ACPI_BGRT=y
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
CONFIG_HAVE_ACPI_APEI=y
CONFIG_ACPI_APEI=y
CONFIG_ACPI_APEI_GHES=y
CONFIG_ACPI_APEI_PCIEAER=y
CONFIG_ACPI_APEI_SEA=y
CONFIG_ACPI_APEI_MEMORY_FAILURE=y
CONFIG_ACPI_APEI_EINJ=m
CONFIG_ACPI_APEI_ERST_DEBUG=m
CONFIG_ACPI_CONFIGFS=m
CONFIG_ACPI_IORT=y
CONFIG_ACPI_GTDT=y
CONFIG_ACPI_PPTT=y
CONFIG_PMIC_OPREGION=y
CONFIG_ACPI_VIOT=y
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_MMIO=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_KVM_XFER_TO_GUEST_WORK=y
# CONFIG_NVHE_EL2_DEBUG is not set
CONFIG_ARM64_CRYPTO=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64_CE=y
CONFIG_CRYPTO_SHA3_ARM64=y
CONFIG_CRYPTO_SM3_ARM64_CE=y
CONFIG_CRYPTO_SM4_ARM64_CE=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_CHACHA20_NEON=y
CONFIG_CRYPTO_POLY1305_NEON=y
CONFIG_CRYPTO_NHPOLY1305_NEON=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CPU_MITIGATIONS=y

#
# General architecture-dependent options
#
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
CONFIG_UPROBES=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
# CONFIG_SECCOMP_CACHE_DEBUG is not set
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
CONFIG_FUNCTION_ALIGNMENT=0
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
CONFIG_MODULE_COMPRESS_NONE=y
# CONFIG_MODULE_COMPRESS_GZIP is not set
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BLK_CGROUP_RWSTAT=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=y
# CONFIG_BLK_DEV_ZONED is not set
CONFIG_BLK_DEV_THROTTLING=y
# CONFIG_BLK_DEV_THROTTLING_LOW is not set
CONFIG_BLK_WBT=y
CONFIG_BLK_WBT_MQ=y
# CONFIG_BLK_CGROUP_IOLATENCY is not set
# CONFIG_BLK_CGROUP_IOCOST is not set
# CONFIG_BLK_CGROUP_IOPRIO is not set
# CONFIG_BLK_DEBUG_FS is not set
# CONFIG_BLK_SED_OPAL is not set
# CONFIG_BLK_INLINE_ENCRYPTION is not set

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_AIX_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
CONFIG_CMDLINE_PARTITION=y
# end of Partition Types

CONFIG_BLOCK_COMPAT=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_HOLDER_DEPRECATED=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
# CONFIG_BFQ_CGROUP_DEBUG is not set
# end of IO Schedulers

CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_HAVE_ELF_PROT=y
CONFIG_ARCH_USE_GNU_PROPERTY=y
CONFIG_ELFCORE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=m
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
CONFIG_ARCH_ENABLE_THP_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_MMU_NOTIFIER=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
CONFIG_MEMORY_FAILURE=y
# CONFIG_HWPOISON_INJECT is not set
CONFIG_TRANSPARENT_HUGEPAGE=y
# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set
CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
CONFIG_CLEANCACHE=y
CONFIG_FRONTSWAP=y
CONFIG_CMA=y
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_CMA_AREAS=7
CONFIG_ZSWAP=y
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
CONFIG_ZSWAP_DEFAULT_ON=y
CONFIG_ZPOOL=y
CONFIG_ZBUD=y
CONFIG_Z3FOLD=y
CONFIG_ZSMALLOC=y
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_ARCH_HAS_ZONE_DMA_SET=y
CONFIG_ZONE_DMA=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_TEST is not set
# CONFIG_READ_ONLY_THP_FOR_FS is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_SECRETMEM=y
# CONFIG_LRU_GEN is not set

#
# Data Access Monitoring
#
# CONFIG_DAMON is not set
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_EXTENSIONS=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_UNIX_SCM=y
CONFIG_AF_UNIX_OOB=y
CONFIG_UNIX_DIAG=y
CONFIG_TLS=m
# CONFIG_TLS_DEVICE is not set
# CONFIG_TLS_TOE is not set
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
CONFIG_XFRM_INTERFACE=m
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_AH=y
CONFIG_XFRM_ESP=y
CONFIG_XFRM_IPCOMP=y
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_XFRM_ESPINTCP=y
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
# CONFIG_IP_FIB_TRIE_STATS is not set
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_ROUTE_CLASSID=y
# CONFIG_IP_PNP is not set
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=y
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=y
CONFIG_NET_FOU=y
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
CONFIG_INET_ESP_OFFLOAD=m
# CONFIG_INET_ESPINTCP is not set
CONFIG_INET_IPCOMP=y
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=y
CONFIG_INET_TUNNEL=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
CONFIG_INET_UDP_DIAG=y
CONFIG_INET_RAW_DIAG=y
# CONFIG_INET_DIAG_DESTROY is not set
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_NV=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_CONG_DCTCP=m
CONFIG_TCP_CONG_CDG=m
CONFIG_TCP_CONG_BBR=m
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_ESP_OFFLOAD=m
CONFIG_INET6_ESPINTCP=y
CONFIG_INET6_IPCOMP=y
CONFIG_IPV6_MIP6=m
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=y
CONFIG_INET6_TUNNEL=y
CONFIG_IPV6_VTI=m
CONFIG_IPV6_SIT=y
# CONFIG_IPV6_SIT_6RD is not set
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=y
CONFIG_IPV6_GRE=m
CONFIG_IPV6_FOU=y
CONFIG_IPV6_FOU_TUNNEL=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
CONFIG_IPV6_SEG6_LWTUNNEL=y
CONFIG_IPV6_SEG6_HMAC=y
CONFIG_IPV6_SEG6_BPF=y
CONFIG_IPV6_RPL_LWTUNNEL=y
# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
# CONFIG_NETLABEL is not set
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=y
CONFIG_MPTCP_IPV6=y
CONFIG_NETWORK_SECMARK=y
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_NETLINK=m
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
# CONFIG_NETFILTER_NETLINK_HOOK is not set
CONFIG_NETFILTER_NETLINK_ACCT=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NETFILTER_NETLINK_OSF=m
CONFIG_NF_CONNTRACK=y
CONFIG_NF_LOG_SYSLOG=m
CONFIG_NETFILTER_CONNCOUNT=m
CONFIG_NF_CONNTRACK_MARK=y
# CONFIG_NF_CONNTRACK_SECMARK is not set
CONFIG_NF_CONNTRACK_ZONES=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y
CONFIG_NF_CONNTRACK_TIMEOUT=y
CONFIG_NF_CONNTRACK_TIMESTAMP=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_CT_NETLINK_TIMEOUT=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=m
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=m
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_COUNTER=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_OBJREF=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
CONFIG_NFT_OSF=m
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NF_DUP_NETDEV=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NFT_REJECT_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
CONFIG_NF_FLOW_TABLE_PROCFS=y
CONFIG_NETFILTER_XTABLES=m
# CONFIG_NETFILTER_XTABLES_COMPAT is not set

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=m
CONFIG_NETFILTER_XT_CONNMARK=m
CONFIG_NETFILTER_XT_SET=m

#
# Xtables targets
#
# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LED=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=m
CONFIG_NETFILTER_XT_TARGET_NETMAP=m
CONFIG_NETFILTER_XT_TARGET_FULLCONENAT=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD=m
CONFIG_NETFILTER_XT_TARGET_RATEEST=m
CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=m
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# end of Core Netfilter Configuration

CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
# CONFIG_IP_VS_DEBUG is not set
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m
# CONFIG_IP_VS_TWOS is not set

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_SOCKET_IPV4=m
CONFIG_NF_TPROXY_IPV4=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=m
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_FULLCONENAT=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
# CONFIG_IP_NF_SECURITY is not set
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
# CONFIG_IP6_NF_SECURITY is not set
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=y
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_NFT_BRIDGE_META=m
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
# CONFIG_BPFILTER is not set
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m

#
# DCCP CCIDs Configuration
#
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
CONFIG_IP_DCCP_CCID3=y
# CONFIG_IP_DCCP_CCID3_DEBUG is not set
CONFIG_IP_DCCP_TFRC_LIB=y
# end of DCCP CCIDs Configuration

#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
# end of DCCP Kernel Hacking

CONFIG_IP_SCTP=m
CONFIG_SCTP_DBG_OBJCNT=y
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=m
CONFIG_RDS=m
CONFIG_RDS_TCP=m
# CONFIG_RDS_DEBUG is not set
CONFIG_TIPC=m
CONFIG_TIPC_MEDIA_UDP=y
CONFIG_TIPC_CRYPTO=y
CONFIG_TIPC_DIAG=m
# CONFIG_ATM is not set
CONFIG_L2TP=m
CONFIG_L2TP_DEBUGFS=m
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=m
CONFIG_L2TP_ETH=m
CONFIG_STP=y
CONFIG_GARP=y
CONFIG_MRP=y
CONFIG_BRIDGE=m
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
# CONFIG_BRIDGE_MRP is not set
# CONFIG_BRIDGE_CFM is not set
# CONFIG_NET_DSA is not set
CONFIG_VLAN_8021Q=y
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q_MVRP=y
CONFIG_LLC=y
CONFIG_LLC2=m
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
CONFIG_6LOWPAN=m
# CONFIG_6LOWPAN_DEBUGFS is not set
CONFIG_6LOWPAN_NHC=m
CONFIG_6LOWPAN_NHC_DEST=m
CONFIG_6LOWPAN_NHC_FRAGMENT=m
CONFIG_6LOWPAN_NHC_HOP=m
CONFIG_6LOWPAN_NHC_IPV6=m
CONFIG_6LOWPAN_NHC_MOBILITY=m
CONFIG_6LOWPAN_NHC_ROUTING=m
CONFIG_6LOWPAN_NHC_UDP=m
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
CONFIG_6LOWPAN_GHC_UDP=m
CONFIG_6LOWPAN_GHC_ICMPV6=m
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
CONFIG_IEEE802154=m
CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_MAC802154=m
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFB=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_SKBPRIO=m
CONFIG_NET_SCH_CHOKE=m
CONFIG_NET_SCH_QFQ=m
CONFIG_NET_SCH_CODEL=m
CONFIG_NET_SCH_FQ_CODEL=y
CONFIG_NET_SCH_CAKE=m
CONFIG_NET_SCH_FQ=m
CONFIG_NET_SCH_HHF=m
CONFIG_NET_SCH_PIE=m
# CONFIG_NET_SCH_FQ_PIE is not set
CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_SCH_PLUG=m
# CONFIG_NET_SCH_ETS is not set
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_PERF=y
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=y
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
# CONFIG_NET_EMATCH_CANID is not set
CONFIG_NET_EMATCH_IPSET=m
CONFIG_NET_EMATCH_IPT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_SAMPLE=m
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
CONFIG_NET_ACT_MPLS=m
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_NET_ACT_CONNMARK=m
CONFIG_NET_ACT_CTINFO=m
CONFIG_NET_ACT_SKBMOD=m
CONFIG_NET_ACT_IFE=m
CONFIG_NET_ACT_TUNNEL_KEY=m
CONFIG_NET_ACT_CT=m
# CONFIG_NET_ACT_GATE is not set
CONFIG_NET_IFE_SKBMARK=m
CONFIG_NET_IFE_SKBPRIO=m
CONFIG_NET_IFE_SKBTCINDEX=m
# CONFIG_NET_TC_SKB_EXT is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=m
CONFIG_BATMAN_ADV=m
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
CONFIG_BATMAN_ADV_NC=y
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUG is not set
# CONFIG_BATMAN_ADV_TRACING is not set
# CONFIG_OPENVSWITCH is not set
# CONFIG_VSOCKETS is not set
CONFIG_NETLINK_DIAG=y
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=m
CONFIG_MPLS_ROUTING=m
CONFIG_MPLS_IPTUNNEL=m
CONFIG_NET_NSH=m
CONFIG_HSR=m
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=m
# CONFIG_QRTR_SMD is not set
# CONFIG_QRTR_TUN is not set
CONFIG_QRTR_MHI=m
# CONFIG_NET_NCSI is not set
CONFIG_PCPU_DEV_REFCNT=y
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_XPS=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
CONFIG_NET_PKTGEN=m
# CONFIG_NET_DROP_MONITOR is not set
# end of Network testing
# end of Networking options

# CONFIG_HAMRADIO is not set
CONFIG_CAN=m
CONFIG_CAN_RAW=m
CONFIG_CAN_BCM=m
CONFIG_CAN_GW=m
CONFIG_CAN_J1939=m
CONFIG_CAN_ISOTP=m

#
# CAN Device Drivers
#
CONFIG_CAN_VCAN=m
CONFIG_CAN_VXCAN=m
CONFIG_CAN_SLCAN=m
CONFIG_CAN_DEV=m
CONFIG_CAN_CALC_BITTIMING=y
CONFIG_CAN_FLEXCAN=m
CONFIG_CAN_GRCAN=m
CONFIG_CAN_KVASER_PCIEFD=m
CONFIG_CAN_XILINXCAN=m
CONFIG_CAN_C_CAN=m
CONFIG_CAN_C_CAN_PLATFORM=m
CONFIG_CAN_C_CAN_PCI=m
CONFIG_CAN_CC770=m
CONFIG_CAN_CC770_ISA=m
CONFIG_CAN_CC770_PLATFORM=m
CONFIG_CAN_IFI_CANFD=m
CONFIG_CAN_M_CAN=m
CONFIG_CAN_M_CAN_PCI=m
CONFIG_CAN_M_CAN_PLATFORM=m
CONFIG_CAN_M_CAN_TCAN4X5X=m
CONFIG_CAN_PEAK_PCIEFD=m
CONFIG_CAN_SJA1000=m
# CONFIG_CAN_EMS_PCI is not set
# CONFIG_CAN_EMS_PCMCIA is not set
# CONFIG_CAN_F81601 is not set
# CONFIG_CAN_KVASER_PCI is not set
# CONFIG_CAN_PEAK_PCI is not set
# CONFIG_CAN_PEAK_PCMCIA is not set
# CONFIG_CAN_PLX_PCI is not set
# CONFIG_CAN_SJA1000_ISA is not set
# CONFIG_CAN_SJA1000_PLATFORM is not set
CONFIG_CAN_SOFTING=m
# CONFIG_CAN_SOFTING_CS is not set

#
# CAN SPI interfaces
#
CONFIG_CAN_HI311X=m
CONFIG_CAN_MCP251X=m
CONFIG_CAN_MCP251XFD=m
# CONFIG_CAN_MCP251XFD_SANITY is not set
# end of CAN SPI interfaces

#
# CAN USB interfaces
#
CONFIG_CAN_8DEV_USB=m
CONFIG_CAN_EMS_USB=m
CONFIG_CAN_ESD_USB2=m
CONFIG_CAN_ETAS_ES58X=m
CONFIG_CAN_GS_USB=m
CONFIG_CAN_KVASER_USB=m
CONFIG_CAN_MCBA_USB=m
CONFIG_CAN_PEAK_USB=m
CONFIG_CAN_UCAN=m
# end of CAN USB interfaces

# CONFIG_CAN_DEBUG_DEVICES is not set
# end of CAN Device Drivers

CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=m
CONFIG_BT_HS=y
CONFIG_BT_LE=y
CONFIG_BT_6LOWPAN=m
CONFIG_BT_LEDS=y
CONFIG_BT_MSFTEXT=y
# CONFIG_BT_AOSPEXT is not set
# CONFIG_BT_DEBUGFS is not set
CONFIG_BT_SELFTEST=y
CONFIG_BT_SELFTEST_ECDH=y
CONFIG_BT_SELFTEST_SMP=y

#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=m
CONFIG_BT_BCM=m
CONFIG_BT_RTL=m
CONFIG_BT_QCA=m
CONFIG_BT_HCIBTUSB=m
# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
CONFIG_BT_HCIBTUSB_BCM=y
CONFIG_BT_HCIBTUSB_MTK=y
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_NOKIA=m
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_BCM=y
CONFIG_BT_HCIUART_RTL=y
CONFIG_BT_HCIUART_QCA=y
CONFIG_BT_HCIUART_AG6XX=y
CONFIG_BT_HCIUART_MRVL=y
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIDTL1=m
CONFIG_BT_HCIBT3C=m
CONFIG_BT_HCIBLUECARD=m
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
CONFIG_BT_MTKSDIO=m
CONFIG_BT_MTKUART=m
CONFIG_BT_HCIRSI=m
CONFIG_BT_VIRTIO=m
# end of Bluetooth device drivers

CONFIG_AF_RXRPC=m
# CONFIG_AF_RXRPC_IPV6 is not set
# CONFIG_AF_RXRPC_INJECT_LOSS is not set
# CONFIG_AF_RXRPC_DEBUG is not set
# CONFIG_RXKAD is not set
CONFIG_AF_KCM=m
CONFIG_STREAM_PARSER=y
# CONFIG_MCTP is not set
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_SPY=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
CONFIG_CFG80211_CERTIFICATION_ONUS=y
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_EXTRA_REGDB_KEYDIR=""
CONFIG_CFG80211_REG_CELLULAR_HINTS=y
CONFIG_CFG80211_REG_RELAX_NO_IR=y
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_CFG80211_WEXT_EXPORT=y
CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
CONFIG_LIB80211_CRYPT_TKIP=m
CONFIG_LIB80211_DEBUG=y
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_MESSAGE_TRACING is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_RFKILL=m
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=m
CONFIG_NET_9P=m
CONFIG_NET_9P_VIRTIO=m
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
CONFIG_CEPH_LIB=m
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
# CONFIG_NFC is not set
CONFIG_PSAMPLE=m
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_FAILOVER=y
CONFIG_SHORTCUT_FE=y
CONFIG_ETHTOOL_NETLINK=y

#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
CONFIG_PCIEPORTBUS=y
CONFIG_HOTPLUG_PCI_PCIE=y
CONFIG_PCIEAER=y
CONFIG_PCIEAER_INJECT=m
CONFIG_PCIE_ECRC=y
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
# CONFIG_PCIEASPM_PERFORMANCE is not set
CONFIG_PCIE_PME=y
CONFIG_PCIE_DPC=y
CONFIG_PCIE_PTM=y
CONFIG_PCIE_EDR=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
CONFIG_PCI_REALLOC_ENABLE_AUTO=y
CONFIG_PCI_STUB=m
CONFIG_PCI_PF_STUB=m
CONFIG_PCI_ATS=y
CONFIG_PCI_ECAM=y
CONFIG_PCI_IOV=y
CONFIG_PCI_PRI=y
CONFIG_PCI_PASID=y
CONFIG_PCI_LABEL=y
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
CONFIG_HOTPLUG_PCI=y
CONFIG_HOTPLUG_PCI_ACPI=y
CONFIG_HOTPLUG_PCI_ACPI_IBM=m
CONFIG_HOTPLUG_PCI_CPCI=y
# CONFIG_HOTPLUG_PCI_SHPC is not set

#
# PCI controller drivers
#
# CONFIG_PCI_FTPCI100 is not set
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
# CONFIG_PCIE_XILINX is not set
CONFIG_PCI_XGENE=y
CONFIG_PCI_XGENE_MSI=y
CONFIG_PCIE_ALTERA=y
CONFIG_PCIE_ALTERA_MSI=y
CONFIG_PCI_HOST_THUNDER_PEM=y
CONFIG_PCI_HOST_THUNDER_ECAM=y
CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_HOST=y
CONFIG_PCIE_ROCKCHIP_EP=y
# CONFIG_PCIE_MICROCHIP_HOST is not set
# CONFIG_PCIE_HISI_ERR is not set

#
# DesignWare PCI Core Support
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_EP=y
CONFIG_PCIE_DW_PLAT=y
CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCIE_DW_PLAT_EP=y
CONFIG_PCI_HISI=y
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
# CONFIG_PCIE_KIRIN is not set
CONFIG_PCI_MESON=y
# CONFIG_PCIE_AL is not set
# end of DesignWare PCI Core Support

#
# Mobiveil PCIe Core Support
#
# end of Mobiveil PCIe Core Support

#
# Cadence PCIe controllers support
#
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCIE_CADENCE_PLAT_EP is not set
# CONFIG_PCI_J721E_HOST is not set
# CONFIG_PCI_J721E_EP is not set
# end of Cadence PCIe controllers support
# end of PCI controller drivers

#
# PCI Endpoint
#
CONFIG_PCI_ENDPOINT=y
CONFIG_PCI_ENDPOINT_CONFIGFS=y
CONFIG_PCI_EPF_TEST=m
CONFIG_PCI_EPF_NTB=m
# CONFIG_PCI_EPF_VNTB is not set
# end of PCI Endpoint

#
# PCI switch controller drivers
#
CONFIG_PCI_SW_SWITCHTEC=m
# end of PCI switch controller drivers

CONFIG_CXL_BUS=m
CONFIG_CXL_MEM=m
# CONFIG_CXL_MEM_RAW_COMMANDS is not set
CONFIG_CXL_ACPI=m
CONFIG_PCCARD=m
CONFIG_PCMCIA=m
CONFIG_PCMCIA_LOAD_CIS=y
CONFIG_CARDBUS=y

#
# PC-card bridges
#
CONFIG_YENTA=m
CONFIG_YENTA_O2=y
CONFIG_YENTA_RICOH=y
CONFIG_YENTA_TI=y
CONFIG_YENTA_ENE_TUNE=y
CONFIG_YENTA_TOSHIBA=y
CONFIG_PD6729=m
CONFIG_I82092=m
CONFIG_PCCARD_NONSTATIC=y
CONFIG_RAPIDIO=y
CONFIG_RAPIDIO_TSI721=y
CONFIG_RAPIDIO_DISC_TIMEOUT=30
CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y
CONFIG_RAPIDIO_DMA_ENGINE=y
CONFIG_RAPIDIO_DEBUG=y
CONFIG_RAPIDIO_ENUM_BASIC=m
CONFIG_RAPIDIO_CHMAN=m
# CONFIG_RAPIDIO_MPORT_CDEV is not set

#
# RapidIO Switch drivers
#
# CONFIG_RAPIDIO_TSI57X is not set
CONFIG_RAPIDIO_CPS_XX=y
# CONFIG_RAPIDIO_TSI568 is not set
CONFIG_RAPIDIO_CPS_GEN2=y
# CONFIG_RAPIDIO_RXS_GEN3 is not set
# end of RapidIO Switch drivers

#
# Generic Driver Options
#
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_FW_LOADER_USER_HELPER is not set
# CONFIG_FW_LOADER_COMPRESS is not set
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SCCB=m
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
CONFIG_BRCMSTB_GISB_ARB=y
# CONFIG_MOXTET is not set
CONFIG_SUN50I_DE2_BUS=y
CONFIG_SUNXI_RSB=y
CONFIG_VEXPRESS_CONFIG=y
CONFIG_MHI_BUS=m
# CONFIG_MHI_BUS_DEBUG is not set
# CONFIG_MHI_BUS_PCI_GENERIC is not set
# end of Bus devices

CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y

#
# Firmware Drivers
#

#
# ARM System Control and Management Interface Protocol
#
CONFIG_ARM_SCMI_PROTOCOL=y
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
CONFIG_ARM_SCMI_HAVE_SHMEM=y
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
CONFIG_ARM_SCMI_POWER_DOMAIN=y
# end of ARM System Control and Management Interface Protocol

CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
CONFIG_ARM_SDE_INTERFACE=y
# CONFIG_FIRMWARE_MEMMAP is not set
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=y
# CONFIG_ISCSI_IBFT is not set
CONFIG_FW_CFG_SYSFS=y
CONFIG_FW_CFG_SYSFS_CMDLINE=y
CONFIG_SYSFB=y
# CONFIG_SYSFB_SIMPLEFB is not set
CONFIG_ROCKCHIP_SIP=y
# CONFIG_ARM_FFA_TRANSPORT is not set
# CONFIG_GOOGLE_FIRMWARE is not set

#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_VARS_PSTORE=y
# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_GENERIC_STUB=y
CONFIG_EFI_ARMSTUB_DTB_LOADER=y
CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
CONFIG_EFI_BOOTLOADER_CONTROL=m
CONFIG_EFI_CAPSULE_LOADER=m
CONFIG_EFI_TEST=m
# CONFIG_RESET_ATTACK_MITIGATION is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
# end of EFI (Extensible Firmware Interface) Support

CONFIG_UEFI_CPER=y
CONFIG_UEFI_CPER_ARM=y
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
CONFIG_MESON_SM=y
CONFIG_MESON_GX_PM=y
CONFIG_ARM_PSCI_FW=y
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_ARM_SMCCC_SOC_ID=y

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_GNSS=m
CONFIG_GNSS_SERIAL=m
CONFIG_GNSS_MTK_SERIAL=m
CONFIG_GNSS_SIRF_SERIAL=m
CONFIG_GNSS_UBX_SERIAL=m
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_AFS_PARTS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y

#
# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
#
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_DATAFLASH is not set
CONFIG_MTD_MCHP23K256=m
# CONFIG_MTD_MCHP48L640 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
# CONFIG_MTD_SPI_NAND is not set

#
# ECC engine support
#
# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
# CONFIG_MTD_UBI_BLOCK is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_NULL_BLK=m
CONFIG_CDROM=m
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
CONFIG_ZRAM=m
# CONFIG_ZRAM_DEF_COMP_LZORLE is not set
CONFIG_ZRAM_DEF_COMP_ZSTD=y
# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
# CONFIG_ZRAM_DEF_COMP_LZO is not set
# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
# CONFIG_ZRAM_DEF_COMP_842 is not set
CONFIG_ZRAM_DEF_COMP="zstd"
CONFIG_ZRAM_WRITEBACK=y
CONFIG_ZRAM_MEMORY_TRACKING=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=128
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
CONFIG_BLK_DEV_DRBD=m
CONFIG_DRBD_FAULT_INJECTION=y
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_VIRTIO_BLK=m
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_RSXX is not set

#
# NVME Support
#
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
# CONFIG_NVME_MULTIPATH is not set
CONFIG_NVME_HWMON=y
CONFIG_NVME_FABRICS=m
# CONFIG_NVME_FC is not set
CONFIG_NVME_TCP=m
CONFIG_NVME_TARGET=m
# CONFIG_NVME_TARGET_PASSTHRU is not set
CONFIG_NVME_TARGET_LOOP=m
# CONFIG_NVME_TARGET_FC is not set
CONFIG_NVME_TARGET_TCP=m
# end of NVME Support

#
# Misc devices
#
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
CONFIG_TIFM_CORE=m
CONFIG_TIFM_7XX1=m
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HI6421V600_IRQ is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
# CONFIG_DW_XDATA_PCIE is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_XILINX_SDFEC is not set
CONFIG_MISC_RTSX=m
# CONFIG_HISI_HIKEY_USB is not set
CONFIG_KHADAS_FAN=y
# CONFIG_KHADAS_MCU is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
CONFIG_EEPROM_AT25=m
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
CONFIG_EEPROM_93CX6=m
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

CONFIG_CB710_CORE=m
# CONFIG_CB710_DEBUG is not set
CONFIG_CB710_DEBUG_ASSUMPTIONS=y

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline

# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_BCM_VK is not set
# CONFIG_MISC_ALCOR_PCI is not set
# CONFIG_MISC_RTSX_PCI is not set
CONFIG_MISC_RTSX_USB=m
# CONFIG_HABANA_AI is not set
# CONFIG_UACCE is not set
# CONFIG_PVPANIC is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI_COMMON=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=m
CONFIG_BLK_DEV_BSG=y
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=m
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_ISCSI_BOOT_SYSFS=m
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_MPI3MR is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_FDOMAIN_PCI is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
CONFIG_SCSI_VIRTIO=m
# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
# CONFIG_SCSI_DH is not set
# end of SCSI device support

CONFIG_HAVE_PATA_PLATFORM=y
CONFIG_ATA=m
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_ATA_LEDS=y
CONFIG_ATA_ACPI=y
CONFIG_SATA_ZPODD=y
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=m
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=m
CONFIG_AHCI_CEVA=m
CONFIG_AHCI_SUNXI=m
CONFIG_AHCI_QORIQ=m
CONFIG_SATA_INIC162X=m
CONFIG_SATA_ACARD_AHCI=m
CONFIG_SATA_SIL24=m
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#
# CONFIG_PDC_ADMA is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_SATA_SX4 is not set
CONFIG_ATA_BMDMA=y

#
# SATA SFF controllers with BMDMA
#
# CONFIG_ATA_PIIX is not set
CONFIG_SATA_DWC=m
CONFIG_SATA_DWC_OLD_DMA=y
# CONFIG_SATA_DWC_DEBUG is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_NV is not set
CONFIG_SATA_PROMISE=m
CONFIG_SATA_SIL=m
# CONFIG_SATA_SIS is not set
# CONFIG_SATA_SVW is not set
# CONFIG_SATA_ULI is not set
CONFIG_SATA_VIA=m
# CONFIG_SATA_VITESSE is not set

#
# PATA SFF controllers with BMDMA
#
CONFIG_PATA_ALI=m
# CONFIG_PATA_AMD is not set
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_ATP867X is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CYPRESS is not set
# CONFIG_PATA_EFAR is not set
# CONFIG_PATA_HPT366 is not set
# CONFIG_PATA_HPT37X is not set
# CONFIG_PATA_HPT3X2N is not set
# CONFIG_PATA_HPT3X3 is not set
# CONFIG_PATA_IT8213 is not set
# CONFIG_PATA_IT821X is not set
# CONFIG_PATA_JMICRON is not set
# CONFIG_PATA_MARVELL is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_OPTIDMA is not set
# CONFIG_PATA_PDC2027X is not set
# CONFIG_PATA_PDC_OLD is not set
# CONFIG_PATA_RADISYS is not set
# CONFIG_PATA_RDC is not set
# CONFIG_PATA_SCH is not set
# CONFIG_PATA_SERVERWORKS is not set
# CONFIG_PATA_SIL680 is not set
# CONFIG_PATA_SIS is not set
# CONFIG_PATA_TOSHIBA is not set
# CONFIG_PATA_TRIFLEX is not set
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set

#
# PIO-only SFF controllers
#
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_PCMCIA is not set
# CONFIG_PATA_PLATFORM is not set
# CONFIG_PATA_RZ1000 is not set

#
# Generic fallback / legacy drivers
#
# CONFIG_PATA_ACPI is not set
CONFIG_ATA_GENERIC=m
# CONFIG_PATA_LEGACY is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
CONFIG_MD_CLUSTER=m
CONFIG_BCACHE=m
# CONFIG_BCACHE_DEBUG is not set
# CONFIG_BCACHE_CLOSURES_DEBUG is not set
# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=m
# CONFIG_DM_DEBUG is not set
CONFIG_DM_BUFIO=m
# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
CONFIG_DM_CACHE=m
CONFIG_DM_CACHE_SMQ=m
CONFIG_DM_WRITECACHE=m
# CONFIG_DM_EBS is not set
# CONFIG_DM_ERA is not set
# CONFIG_DM_CLONE is not set
CONFIG_DM_MIRROR=m
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
# CONFIG_DM_MULTIPATH_HST is not set
# CONFIG_DM_MULTIPATH_IOA is not set
CONFIG_DM_DELAY=m
# CONFIG_DM_DUST is not set
# CONFIG_DM_UEVENT is not set
CONFIG_DM_FLAKEY=m
CONFIG_DM_VERITY=m
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
# CONFIG_DM_VERITY_FEC is not set
# CONFIG_DM_SWITCH is not set
CONFIG_DM_LOG_WRITES=m
CONFIG_DM_INTEGRITY=m
CONFIG_TARGET_CORE=m
CONFIG_TCM_IBLOCK=m
CONFIG_TCM_FILEIO=m
CONFIG_TCM_PSCSI=m
# CONFIG_LOOPBACK_TARGET is not set
CONFIG_ISCSI_TARGET=m
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
# end of IEEE 1394 (FireWire) support

CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_WIREGUARD=m
# CONFIG_WIREGUARD_DEBUG is not set
CONFIG_EQUALIZER=m
# CONFIG_NET_FC is not set
CONFIG_IFB=m
CONFIG_NET_TEAM=m
CONFIG_NET_TEAM_MODE_BROADCAST=m
CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
CONFIG_NET_TEAM_MODE_RANDOM=m
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
CONFIG_NET_TEAM_MODE_LOADBALANCE=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=m
CONFIG_IPVTAP=m
CONFIG_VXLAN=m
CONFIG_GENEVE=m
CONFIG_BAREUDP=m
CONFIG_GTP=m
CONFIG_MACSEC=m
CONFIG_NETCONSOLE=m
CONFIG_NETCONSOLE_DYNAMIC=y
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
# CONFIG_RIONET is not set
CONFIG_TUN=m
CONFIG_TAP=m
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_NLMON=m
CONFIG_NET_VRF=m
# CONFIG_MHI_NET is not set
# CONFIG_ARCNET is not set
CONFIG_ETHERNET=y
CONFIG_MDIO=m
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
CONFIG_NET_VENDOR_ALLWINNER=y
CONFIG_SUN4I_EMAC=y
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_ALTERA_TSE is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
CONFIG_NET_VENDOR_ATHEROS=y
# CONFIG_ATL2 is not set
# CONFIG_ATL1 is not set
# CONFIG_ATL1E is not set
# CONFIG_ATL1C is not set
CONFIG_ALX=m
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_DNET is not set
# CONFIG_NET_VENDOR_DEC is not set
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_FREESCALE is not set
# CONFIG_NET_VENDOR_FUJITSU is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
CONFIG_NET_VENDOR_I825XX=y
CONFIG_NET_VENDOR_INTEL=y
# CONFIG_E100 is not set
CONFIG_E1000=m
CONFIG_E1000E=m
CONFIG_IGB=m
CONFIG_IGB_HWMON=y
CONFIG_IGBVF=m
# CONFIG_IXGB is not set
# CONFIG_IXGBE is not set
# CONFIG_IXGBEVF is not set
# CONFIG_I40E is not set
# CONFIG_I40EVF is not set
# CONFIG_ICE is not set
# CONFIG_FM10K is not set
CONFIG_IGC=m
# CONFIG_JME is not set
CONFIG_NET_VENDOR_LITEX=y
# CONFIG_LITEX_LITEETH is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_MICROSOFT is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_FEALNX is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETERION is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_BROCADE is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCA7000_UART is not set
CONFIG_QCOM_EMAC=m
CONFIG_SFE_SUPPORT_IPV6=y
CONFIG_FAST_CLASSIFIER=y
CONFIG_SFE_ECM=y
# CONFIG_RMNET is not set
# CONFIG_NET_VENDOR_RDC is not set
CONFIG_NET_VENDOR_REALTEK=y
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
# CONFIG_R8126 is not set
CONFIG_R8168=m
# CONFIG_R8168_SOC_LAN is not set
# CONFIG_R8168_FIBER_SUPPORT is not set
# CONFIG_R8168_REALWOW_SUPPORT is not set
# CONFIG_R8168_DASH_SUPPORT is not set
# CONFIG_R8168_DOWN_SPEED_100 is not set
CONFIG_R8168_ASPM=y
CONFIG_R8168_DYNAMIC_ASPM=y
CONFIG_R8168_WOL_SUPPORT=y
CONFIG_R8168_S5WOL=y
# CONFIG_R8168_S5_KEEP_CURR_MAC is not set
CONFIG_R8168_EEE=y
# CONFIG_R8168_S0_MAGIC_PACKET is not set
# CONFIG_R8168_USE_FIRMWARE_FILE is not set
# CONFIG_R8168_CTAP_SHORT_OFF is not set
# CONFIG_R8168_MULTIPLE_TX_QUEUE is not set
# CONFIG_R8168_RSS_SUPPORT is not set
CONFIG_R8168_GIGA_LITE=y
# CONFIG_R8169 is not set
CONFIG_R8125=m
# CONFIG_R8125_SOC_LAN is not set
# CONFIG_R8125_REALWOW_SUPPORT is not set
# CONFIG_R8125_DASH_SUPPORT is not set
# CONFIG_R8125_DOWN_SPEED_100 is not set
CONFIG_R8125_ASPM=y
CONFIG_R8125_WOL_SUPPORT=y
CONFIG_R8125_S5WOL=y
# CONFIG_R8125_S5_KEEP_CURR_MAC is not set
CONFIG_R8125_EEE=y
# CONFIG_R8125_S0_MAGIC_PACKET is not set
CONFIG_R8125_TX_NO_CLOSE=y
CONFIG_R8125_MULTI_MSIX_VECTOR=y
CONFIG_R8125_MULTIPLE_TX_QUEUE=y
CONFIG_R8125_RSS_SUPPORT=y
CONFIG_R8125_FIBER_SUPPORT=y
# CONFIG_R8125_USE_FIRMWARE_FILE is not set
# CONFIG_R8125_DOUBLE_VLAN is not set
# CONFIG_R8125_PAGE_REUSE is not set
CONFIG_R8125_GIGA_LITE=y
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_SELFTESTS=y
CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_MESON=y
CONFIG_DWMAC_ROCKCHIP=y
CONFIG_DWMAC_SUNXI=y
CONFIG_DWMAC_SUN8I=y
# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
# CONFIG_NET_VENDOR_XIRCOM is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_NET_SB1000 is not set
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_FIXED_PHY=y
# CONFIG_SFP is not set

#
# MII PHY device drivers
#
CONFIG_AC200_PHY=m
# CONFIG_AMD_PHY is not set
CONFIG_MESON_GXL_PHY=y
# CONFIG_ADIN_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
CONFIG_AX88796B_PHY=m
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM54140_PHY is not set
# CONFIG_BCM7XXX_PHY is not set
# CONFIG_BCM84881_PHY is not set
# CONFIG_BCM87XX_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
CONFIG_ICPLUS_PHY=y
CONFIG_JLSEMI_PHY=y
# CONFIG_LXT_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MARVELL_88X2222_PHY is not set
# CONFIG_MAXLINEAR_GPHY is not set
# CONFIG_MEDIATEK_GE_PHY is not set
# CONFIG_MICREL_PHY is not set
CONFIG_MICROCHIP_PHY=m
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
CONFIG_MOTORCOMM_PHY=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_NXP_C45_TJA11XX_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
# CONFIG_AT803X_PHY is not set
# CONFIG_QSEMI_PHY is not set
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
CONFIG_SMSC_PHY=m
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
# CONFIG_DP83869_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_FWNODE_MDIO=y
CONFIG_OF_MDIO=y
CONFIG_ACPI_MDIO=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_SUN4I=y
CONFIG_MDIO_BITBANG=m
# CONFIG_MDIO_BCM_UNIMAC is not set
CONFIG_MDIO_GPIO=m
# CONFIG_MDIO_HISI_FEMAC is not set
CONFIG_MDIO_MVUSB=m
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_OCTEON is not set
CONFIG_MDIO_IPQ4019=m
CONFIG_MDIO_IPQ8064=m
# CONFIG_MDIO_THUNDER is not set

#
# MDIO Multiplexers
#
CONFIG_MDIO_BUS_MUX=y
CONFIG_MDIO_BUS_MUX_MESON_G12A=y
CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y

#
# PCS device drivers
#
CONFIG_PCS_XPCS=y
# end of PCS device drivers

CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=m
# CONFIG_PPTP is not set
# CONFIG_PPPOL2TP is not set
CONFIG_PPP_ASYNC=m
# CONFIG_PPP_SYNC_TTY is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=m
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_AX8817X=m
CONFIG_USB_NET_AX88179_178A=m
CONFIG_USB_NET_CDCETHER=m
CONFIG_USB_NET_CDC_EEM=m
CONFIG_USB_NET_CDC_NCM=m
CONFIG_USB_NET_HUAWEI_CDC_NCM=m
CONFIG_USB_NET_CDC_MBIM=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9700=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
CONFIG_USB_NET_CDC_SUBSET=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
CONFIG_USB_EPSON2888=y
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=m
CONFIG_USB_NET_CX82310_ETH=m
CONFIG_USB_NET_KALMIA=m
CONFIG_USB_NET_QMI_WWAN=m
CONFIG_USB_HSO=m
CONFIG_USB_NET_INT51X1=m
CONFIG_USB_IPHETH=m
CONFIG_USB_SIERRA_NET=m
CONFIG_USB_VL600=m
CONFIG_USB_NET_CH9200=m
CONFIG_USB_NET_AQC111=m
CONFIG_USB_RTL8153_ECM=m
CONFIG_WLAN=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
# CONFIG_ATH_DEBUG is not set
# CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS is not set
# CONFIG_ATH5K is not set
# CONFIG_ATH5K_PCI is not set
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=m
CONFIG_ATH9K_PCI=y
CONFIG_ATH9K_AHB=y
# CONFIG_ATH9K_DEBUGFS is not set
CONFIG_ATH9K_DFS_CERTIFIED=y
CONFIG_ATH9K_DYNACK=y
# CONFIG_ATH9K_WOW is not set
CONFIG_ATH9K_RFKILL=y
CONFIG_ATH9K_CHANNEL_CONTEXT=y
# CONFIG_ATH9K_PCOEM is not set
CONFIG_ATH9K_PCI_NO_EEPROM=m
CONFIG_ATH9K_HTC=m
# CONFIG_ATH9K_HTC_DEBUGFS is not set
CONFIG_ATH9K_HWRNG=y
CONFIG_CARL9170=m
CONFIG_CARL9170_LEDS=y
CONFIG_CARL9170_WPC=y
CONFIG_CARL9170_HWRNG=y
CONFIG_ATH6KL=m
CONFIG_ATH6KL_SDIO=m
CONFIG_ATH6KL_USB=m
# CONFIG_ATH6KL_DEBUG is not set
# CONFIG_ATH6KL_TRACING is not set
# CONFIG_ATH6KL_REGDOMAIN is not set
CONFIG_AR5523=m
# CONFIG_WIL6210 is not set
CONFIG_ATH10K=m
CONFIG_ATH10K_CE=y
CONFIG_ATH10K_PCI=m
# CONFIG_ATH10K_AHB is not set
CONFIG_ATH10K_SDIO=m
CONFIG_ATH10K_USB=m
# CONFIG_ATH10K_DEBUG is not set
# CONFIG_ATH10K_DEBUGFS is not set
# CONFIG_ATH10K_TRACING is not set
CONFIG_ATH10K_DFS_CERTIFIED=y
# CONFIG_WCN36XX is not set
CONFIG_ATH11K=m
CONFIG_ATH11K_PCI=m
# CONFIG_ATH11K_DEBUG is not set
# CONFIG_ATH11K_TRACING is not set
CONFIG_WLAN_VENDOR_ATMEL=y
# CONFIG_ATMEL is not set
CONFIG_AT76C50X_USB=m
CONFIG_WLAN_VENDOR_BROADCOM=y
# CONFIG_B43 is not set
# CONFIG_B43LEGACY is not set
CONFIG_BRCMUTIL=m
# CONFIG_BRCMSMAC is not set
CONFIG_BRCMFMAC=m
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_PROTO_MSGBUF=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
CONFIG_BRCMFMAC_PCIE=y
CONFIG_BRCM_TRACING=y
CONFIG_BRCMDBG=y
# CONFIG_WLAN_VENDOR_CISCO is not set
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_IPW2100=m
# CONFIG_IPW2100_MONITOR is not set
# CONFIG_IPW2100_DEBUG is not set
CONFIG_IPW2200=m
# CONFIG_IPW2200_MONITOR is not set
# CONFIG_IPW2200_QOS is not set
# CONFIG_IPW2200_DEBUG is not set
CONFIG_LIBIPW=m
# CONFIG_LIBIPW_DEBUG is not set
CONFIG_IWLEGACY=m
CONFIG_IWL4965=m
CONFIG_IWL3945=m

#
# iwl3945 / iwl4965 Debugging Options
#
# CONFIG_IWLEGACY_DEBUG is not set
# end of iwl3945 / iwl4965 Debugging Options

CONFIG_IWLWIFI=m
CONFIG_IWLWIFI_LEDS=y
CONFIG_IWLDVM=m
CONFIG_IWLMVM=m
CONFIG_IWLWIFI_OPMODE_MODULAR=y
# CONFIG_IWLWIFI_BCAST_FILTERING is not set

#
# Debugging Options
#
# CONFIG_IWLWIFI_DEBUG is not set
# CONFIG_IWLWIFI_DEVICE_TRACING is not set
# end of Debugging Options

# CONFIG_WLAN_VENDOR_INTERSIL is not set
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_USB=m
# CONFIG_LIBERTAS_CS is not set
CONFIG_LIBERTAS_SDIO=m
CONFIG_LIBERTAS_SPI=m
# CONFIG_LIBERTAS_DEBUG is not set
CONFIG_LIBERTAS_MESH=y
CONFIG_LIBERTAS_THINFIRM=m
# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
CONFIG_LIBERTAS_THINFIRM_USB=m
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_SDIO=m
CONFIG_MWIFIEX_PCIE=m
CONFIG_MWIFIEX_USB=m
CONFIG_MWL8K=m
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=m
CONFIG_MT76_CORE=m
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=m
CONFIG_MT76_SDIO=m
CONFIG_MT76x02_LIB=m
CONFIG_MT76x02_USB=m
CONFIG_MT76_CONNAC_LIB=m
CONFIG_MT76x0_COMMON=m
CONFIG_MT76x0U=m
CONFIG_MT76x0E=m
CONFIG_MT76x2_COMMON=m
CONFIG_MT76x2E=m
CONFIG_MT76x2U=m
CONFIG_MT7603E=m
CONFIG_MT7615_COMMON=m
CONFIG_MT7615E=m
CONFIG_MT7663_USB_SDIO_COMMON=m
CONFIG_MT7663U=m
CONFIG_MT7663S=m
CONFIG_MT7915E=m
CONFIG_MT7921E=m
CONFIG_WLAN_VENDOR_MICROCHIP=y
CONFIG_WILC1000=m
CONFIG_WILC1000_SDIO=m
# CONFIG_WILC1000_SPI is not set
# CONFIG_WILC1000_HW_OOB_INTR is not set
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=m
# CONFIG_RT2400PCI is not set
# CONFIG_RT2500PCI is not set
# CONFIG_RT61PCI is not set
CONFIG_RT2800PCI=m
CONFIG_RT2800PCI_RT33XX=y
CONFIG_RT2800PCI_RT35XX=y
CONFIG_RT2800PCI_RT53XX=y
CONFIG_RT2800PCI_RT3290=y
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
CONFIG_RT2800USB_RT33XX=y
CONFIG_RT2800USB_RT35XX=y
CONFIG_RT2800USB_RT3573=y
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
CONFIG_RT2800USB_UNKNOWN=y
CONFIG_RT2800_LIB=m
CONFIG_RT2800_LIB_MMIO=m
CONFIG_RT2X00_LIB_MMIO=m
CONFIG_RT2X00_LIB_PCI=m
CONFIG_RT2X00_LIB_USB=m
CONFIG_RT2X00_LIB=m
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
# CONFIG_RT2X00_DEBUG is not set
CONFIG_WLAN_VENDOR_REALTEK=y
# CONFIG_RTL8180 is not set
CONFIG_RTL8187=m
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=m
CONFIG_RTL8192CE=m
CONFIG_RTL8192SE=m
CONFIG_RTL8192DE=m
CONFIG_RTL8723AE=m
CONFIG_RTL8723BE=m
CONFIG_RTL8188EE=m
CONFIG_RTL8192EE=m
CONFIG_RTL8821AE=m
CONFIG_RTL8192CU=m
CONFIG_RTLWIFI=m
CONFIG_RTLWIFI_PCI=m
CONFIG_RTLWIFI_USB=m
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8723_COMMON=m
CONFIG_RTLBTCOEXIST=m
CONFIG_RTL8XXXU=m
# CONFIG_RTL8XXXU_UNTESTED is not set
CONFIG_RTW88=m
CONFIG_RTW88_CORE=m
CONFIG_RTW88_PCI=m
CONFIG_RTW88_8822B=m
CONFIG_RTW88_8822C=m
CONFIG_RTW88_8723D=m
CONFIG_RTW88_8821C=m
CONFIG_RTW88_8822BE=m
CONFIG_RTW88_8822CE=m
CONFIG_RTW88_8723DE=m
CONFIG_RTW88_8821CE=m
# CONFIG_RTW88_DEBUG is not set
# CONFIG_RTW88_DEBUGFS is not set
CONFIG_RTL8188FU=m
CONFIG_RTL8189FS=m
CONFIG_RTL8822CS=m
CONFIG_WLAN_VENDOR_RSI=y
CONFIG_RSI_91X=m
CONFIG_RSI_DEBUGFS=y
CONFIG_RSI_SDIO=m
CONFIG_RSI_USB=m
CONFIG_RSI_COEX=y
CONFIG_WLAN_VENDOR_ST=y
CONFIG_CW1200=m
CONFIG_CW1200_WLAN_SDIO=m
CONFIG_CW1200_WLAN_SPI=m
CONFIG_WLAN_VENDOR_TI=y
CONFIG_WL1251=m
# CONFIG_WL1251_SPI is not set
CONFIG_WL1251_SDIO=m
# CONFIG_WL12XX is not set
# CONFIG_WL18XX is not set
CONFIG_WLCORE=m
# CONFIG_WLCORE_SPI is not set
CONFIG_WLCORE_SDIO=m
CONFIG_WILINK_PLATFORM_DATA=y
CONFIG_WLAN_VENDOR_ZYDAS=y
CONFIG_USB_ZD1201=m
CONFIG_ZD1211RW=m
# CONFIG_ZD1211RW_DEBUG is not set
CONFIG_WLAN_VENDOR_QUANTENNA=y
# CONFIG_QTNFMAC_PCIE is not set
# CONFIG_SPARD_WLAN_SUPPORT is not set
# CONFIG_PCMCIA_RAYCS is not set
# CONFIG_PCMCIA_WL3501 is not set
CONFIG_MAC80211_HWSIM=m
CONFIG_USB_NET_RNDIS_WLAN=m
CONFIG_VIRT_WIFI=m
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
CONFIG_IEEE802154_AT86RF230=m
CONFIG_IEEE802154_AT86RF230_DEBUGFS=y
CONFIG_IEEE802154_MRF24J40=m
CONFIG_IEEE802154_CC2520=m
CONFIG_IEEE802154_ATUSB=m
CONFIG_IEEE802154_ADF7242=m
CONFIG_IEEE802154_CA8210=m
CONFIG_IEEE802154_CA8210_DEBUGFS=y
CONFIG_IEEE802154_MCR20A=m
CONFIG_IEEE802154_HWSIM=m

#
# Wireless WAN
#
# CONFIG_WWAN is not set
# end of Wireless WAN

CONFIG_VMXNET3=m
# CONFIG_FUJITSU_ES is not set
CONFIG_NETDEVSIM=m
CONFIG_NET_FAILOVER=m
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_SPARSEKMAP is not set
CONFIG_INPUT_MATRIXKMAP=m

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADC is not set
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_GPIO_BUTTON_HOTPLUG is not set
CONFIG_KEYBOARD_GPIO_POLLED=y
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
CONFIG_KEYBOARD_SUN4I_LRADC=y
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=m
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_SMBUS=y
# CONFIG_MOUSE_SERIAL is not set
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=m
# CONFIG_MOUSE_ELAN_I2C is not set
# CONFIG_MOUSE_VSXXXAA is not set
CONFIG_MOUSE_GPIO=m
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
CONFIG_MOUSE_SYNAPTICS_USB=m
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_ANALOG=m
CONFIG_JOYSTICK_A3D=m
CONFIG_JOYSTICK_ADC=m
CONFIG_JOYSTICK_ADI=m
CONFIG_JOYSTICK_COBRA=m
CONFIG_JOYSTICK_GF2K=m
CONFIG_JOYSTICK_GRIP=m
CONFIG_JOYSTICK_GRIP_MP=m
CONFIG_JOYSTICK_GUILLEMOT=m
CONFIG_JOYSTICK_INTERACT=m
CONFIG_JOYSTICK_SIDEWINDER=m
CONFIG_JOYSTICK_TMDC=m
CONFIG_JOYSTICK_IFORCE=m
CONFIG_JOYSTICK_IFORCE_USB=m
CONFIG_JOYSTICK_IFORCE_232=m
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
CONFIG_JOYSTICK_STINGER=m
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
CONFIG_JOYSTICK_AS5011=m
CONFIG_JOYSTICK_JOYDUMP=m
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_JOYSTICK_PSXPAD_SPI=m
CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
CONFIG_JOYSTICK_PXRC=m
# CONFIG_JOYSTICK_QWIIC is not set
CONFIG_JOYSTICK_FSIA6B=m
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_AD7877 is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ADC is not set
# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_BU21029 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 is not set
# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_EGALAX is not set
# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
# CONFIG_TOUCHSCREEN_EXC3000 is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GOODIX is not set
# CONFIG_TOUCHSCREEN_HIDEEP is not set
# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set
# CONFIG_TOUCHSCREEN_ILI210X is not set
# CONFIG_TOUCHSCREEN_ILITEK is not set
# CONFIG_TOUCHSCREEN_S6SY761 is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_EKTF2127 is not set
# CONFIG_TOUCHSCREEN_ELAN is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
# CONFIG_TOUCHSCREEN_MAX11801 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MMS114 is not set
# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
# CONFIG_TOUCHSCREEN_MSG2638 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_PIXCIR is not set
# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
# CONFIG_TOUCHSCREEN_WM97XX is not set
CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
# CONFIG_TOUCHSCREEN_TSC2004 is not set
# CONFIG_TOUCHSCREEN_TSC2005 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_RM_TS is not set
# CONFIG_TOUCHSCREEN_SILEAD is not set
# CONFIG_TOUCHSCREEN_SIS_I2C is not set
# CONFIG_TOUCHSCREEN_ST1232 is not set
# CONFIG_TOUCHSCREEN_STMFTS is not set
CONFIG_TOUCHSCREEN_SUN4I=y
# CONFIG_TOUCHSCREEN_SUR40 is not set
# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
# CONFIG_TOUCHSCREEN_SX8654 is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_TOUCHSCREEN_ZET6223 is not set
# CONFIG_TOUCHSCREEN_ZFORCE is not set
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
# CONFIG_TOUCHSCREEN_IQS5XX is not set
# CONFIG_TOUCHSCREEN_ZINITIX is not set
# CONFIG_TOUCHSCREEN_DWAV_USB_MT is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
# CONFIG_INPUT_BMA150 is not set
# CONFIG_INPUT_E3X0_BUTTON is not set
# CONFIG_INPUT_MMA8450 is not set
CONFIG_INPUT_GPIO_BEEPER=m
# CONFIG_INPUT_GPIO_DECODER is not set
# CONFIG_INPUT_GPIO_VIBRA is not set
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
# CONFIG_INPUT_KXTJ9 is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
CONFIG_INPUT_CM109=m
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
CONFIG_INPUT_AXP20X_PEK=y
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_PWM_BEEPER is not set
# CONFIG_INPUT_PWM_VIBRA is not set
CONFIG_INPUT_RK805_PWRKEY=y
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_DA7280_HAPTICS is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_INPUT_IQS269A is not set
# CONFIG_INPUT_IQS626A is not set
# CONFIG_INPUT_CMA3000 is not set
# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
# CONFIG_INPUT_DRV260X_HAPTICS is not set
# CONFIG_INPUT_DRV2665_HAPTICS is not set
# CONFIG_INPUT_DRV2667_HAPTICS is not set
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=y
CONFIG_RMI4_SPI=y
CONFIG_RMI4_SMB=y
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=y
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
CONFIG_RMI4_F3A=y
CONFIG_RMI4_F54=y
CONFIG_RMI4_F55=y

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=m
# CONFIG_SERIO_AMBAKMI is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=m
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
CONFIG_SERIO_SUN4I_PS2=y
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
CONFIG_GAMEPORT=m
# CONFIG_GAMEPORT_NS558 is not set
# CONFIG_GAMEPORT_L4 is not set
# CONFIG_GAMEPORT_EMU10K1 is not set
# CONFIG_GAMEPORT_FM801 is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
# CONFIG_SERIAL_8250_PCI is not set
# CONFIG_SERIAL_8250_CS is not set
CONFIG_SERIAL_8250_NR_UARTS=5
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_RSA is not set
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
CONFIG_SERIAL_AMBA_PL010=y
CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y
CONFIG_SERIAL_MESON=y
CONFIG_SERIAL_MESON_CONSOLE=y
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_QE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_BCM63XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_NOZOMI is not set
# CONFIG_NULL_TTY is not set
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_TTY_PRINTK is not set
CONFIG_VIRTIO_CONSOLE=m
# CONFIG_IPMI_HANDLER is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=y
# CONFIG_HW_RANDOM_BA431 is not set
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_MESON=y
CONFIG_HW_RANDOM_ROCKCHIP=y
CONFIG_HW_RANDOM_OPTEE=m
# CONFIG_HW_RANDOM_CCTRNG is not set
# CONFIG_HW_RANDOM_XIPHERA is not set
CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
# CONFIG_APPLICOM is not set

#
# PCMCIA character devices
#
# CONFIG_SYNCLINK_CS is not set
# CONFIG_CARDMAN_4000 is not set
# CONFIG_CARDMAN_4040 is not set
# CONFIG_SCR24X is not set
# CONFIG_IPWIRELESS is not set
# end of PCMCIA character devices

CONFIG_DEVMEM=y
CONFIG_DEVPORT=y
# CONFIG_TCG_TPM is not set
# CONFIG_XILLYBUS is not set
# CONFIG_XILLYUSB is not set
# CONFIG_RANDOM_TRUST_CPU is not set
CONFIG_RANDOM_TRUST_BOOTLOADER=y
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_I2C_MUX_GPIO=y
CONFIG_I2C_MUX_GPMUX=y
CONFIG_I2C_MUX_LTC4306=m
CONFIG_I2C_MUX_PCA9541=m
CONFIG_I2C_MUX_PCA954x=m
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_MUX_REG=y
CONFIG_I2C_DEMUX_PINCTRL=y
CONFIG_I2C_MUX_MLXCPLD=m
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_ALGOBIT=y

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set

#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CADENCE is not set
# CONFIG_I2C_CBUS_GPIO is not set
CONFIG_I2C_DESIGNWARE_CORE=y
CONFIG_I2C_DESIGNWARE_SLAVE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_DESIGNWARE_PCI=m
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=y
CONFIG_I2C_GPIO_FAULT_INJECTOR=y
# CONFIG_I2C_HISI is not set
CONFIG_I2C_MESON=y
CONFIG_I2C_MV64XXX=y
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
CONFIG_I2C_RK3X=y
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_THUNDERX is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_CP2615 is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
CONFIG_I2C_VIRTIO=m
# end of I2C Hardware Bus support

# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=m
CONFIG_I2C_SLAVE_TESTUNIT=m
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

# CONFIG_I3C is not set
CONFIG_SPI=y
CONFIG_SPI_DEBUG=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y

#
# SPI Master Controller Drivers
#
CONFIG_SPI_ALTERA=m
CONFIG_SPI_ALTERA_CORE=m
CONFIG_SPI_AXI_SPI_ENGINE=m
CONFIG_SPI_BITBANG=m
CONFIG_SPI_CADENCE=m
CONFIG_SPI_CADENCE_QUADSPI=m
CONFIG_SPI_DESIGNWARE=m
CONFIG_SPI_DW_DMA=y
# CONFIG_SPI_DW_PCI is not set
CONFIG_SPI_DW_MMIO=m
# CONFIG_SPI_HISI_KUNPENG is not set
# CONFIG_SPI_HISI_SFC_V3XX is not set
CONFIG_SPI_NXP_FLEXSPI=m
CONFIG_SPI_GPIO=m
CONFIG_SPI_FSL_LIB=m
CONFIG_SPI_FSL_SPI=m
CONFIG_SPI_MESON_SPICC=y
CONFIG_SPI_MESON_SPIFC=y
CONFIG_SPI_OC_TINY=m
CONFIG_SPI_PL022=m
CONFIG_SPI_PXA2XX=m
CONFIG_SPI_PXA2XX_PCI=m
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_ROCKCHIP_SFC=m
CONFIG_SPI_SC18IS602=m
CONFIG_SPI_SIFIVE=m
CONFIG_SPI_SUN4I=y
CONFIG_SPI_SUN6I=y
CONFIG_SPI_MXIC=m
CONFIG_SPI_THUNDERX=m
CONFIG_SPI_XCOMM=m
CONFIG_SPI_XILINX=m
CONFIG_SPI_ZYNQMP_GQSPI=m
CONFIG_SPI_AMD=m

#
# SPI Multiplexer support
#
CONFIG_SPI_MUX=m

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=m
CONFIG_SPI_LOOPBACK_TEST=m
CONFIG_SPI_TLE62X0=m
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_DYNAMIC=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
# CONFIG_HSI is not set
# CONFIG_PPS is not set

#
# PTP clock support
#
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_PTP_1588_CLOCK_OPTIONAL=y

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
CONFIG_PINCTRL_AXP209=y
# CONFIG_PINCTRL_AMD is not set
CONFIG_PINCTRL_MCP23S08_I2C=m
CONFIG_PINCTRL_MCP23S08_SPI=m
CONFIG_PINCTRL_MCP23S08=m
CONFIG_PINCTRL_ROCKCHIP=y
CONFIG_PINCTRL_SINGLE=y
# CONFIG_PINCTRL_SX150X is not set
CONFIG_PINCTRL_STMFX=m
CONFIG_PINCTRL_RK805=y
# CONFIG_PINCTRL_OCELOT is not set
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set

#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers

CONFIG_PINCTRL_SUNXI=y
CONFIG_PINCTRL_SUN4I_A10=y
CONFIG_PINCTRL_SUN5I=y
CONFIG_PINCTRL_SUN6I_A31=y
CONFIG_PINCTRL_SUN6I_A31_R=y
CONFIG_PINCTRL_SUN8I_A23=y
CONFIG_PINCTRL_SUN8I_A33=y
CONFIG_PINCTRL_SUN8I_A83T=y
CONFIG_PINCTRL_SUN8I_A83T_R=y
CONFIG_PINCTRL_SUN8I_A23_R=y
CONFIG_PINCTRL_SUN8I_H3=y
CONFIG_PINCTRL_SUN8I_H3_R=y
CONFIG_PINCTRL_SUN8I_V3S=y
CONFIG_PINCTRL_SUN9I_A80=y
CONFIG_PINCTRL_SUN9I_A80_R=y
CONFIG_PINCTRL_SUN50I_A64=y
CONFIG_PINCTRL_SUN50I_A64_R=y
CONFIG_PINCTRL_SUN50I_A100=y
CONFIG_PINCTRL_SUN50I_A100_R=y
CONFIG_PINCTRL_SUN50I_H5=y
CONFIG_PINCTRL_SUN50I_H6=y
CONFIG_PINCTRL_SUN50I_H6_R=y
CONFIG_PINCTRL_SUN50I_H616=y
CONFIG_PINCTRL_SUN50I_H616_R=y
CONFIG_PINCTRL_MESON=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_PINCTRL_MESON8_PMX=y
CONFIG_PINCTRL_MESON_AXG=y
CONFIG_PINCTRL_MESON_AXG_PMX=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_PINCTRL_MESON_A1=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_MAX730X=m

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_FTGPIO010 is not set
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HISI is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_LOGICVC is not set
# CONFIG_GPIO_MB86S7X is not set
CONFIG_GPIO_PL061=y
CONFIG_GPIO_ROCKCHIP=y
# CONFIG_GPIO_SAMA5D2_PIOBU is not set
# CONFIG_GPIO_SIFIVE is not set
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_XGENE=y
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
CONFIG_GPIO_ADP5588=m
CONFIG_GPIO_ADNP=m
CONFIG_GPIO_GW_PLD=m
CONFIG_GPIO_MAX7300=m
CONFIG_GPIO_MAX732X=m
CONFIG_GPIO_PCA953X=m
# CONFIG_GPIO_PCA953X_IRQ is not set
# CONFIG_GPIO_PCA9570 is not set
CONFIG_GPIO_PCF857X=m
CONFIG_GPIO_TPIC2810=m
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set
# end of PCI GPIO expanders

#
# SPI GPIO expanders
#
CONFIG_GPIO_74X164=m
CONFIG_GPIO_MAX3191X=m
CONFIG_GPIO_MAX7301=m
CONFIG_GPIO_MC33880=m
CONFIG_GPIO_PISOSR=m
CONFIG_GPIO_XRA1403=m
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
# end of USB GPIO expanders

#
# Virtual GPIO drivers
#
# CONFIG_GPIO_AGGREGATOR is not set
# CONFIG_GPIO_MOCKUP is not set
CONFIG_GPIO_VIRTIO=m
# end of Virtual GPIO drivers

CONFIG_W1=m
CONFIG_W1_CON=y

#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_MATROX=m
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
CONFIG_W1_MASTER_DS1WM=m
CONFIG_W1_MASTER_GPIO=m
CONFIG_W1_MASTER_SGI=m
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
CONFIG_W1_SLAVE_DS2405=m
CONFIG_W1_SLAVE_DS2408=m
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
# CONFIG_W1_SLAVE_DS2805 is not set
# CONFIG_W1_SLAVE_DS2430 is not set
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
CONFIG_W1_SLAVE_DS2438=m
CONFIG_W1_SLAVE_DS250X=m
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
CONFIG_W1_SLAVE_DS28E17=m
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_BRCMSTB=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
# CONFIG_POWER_RESET_LTC2952 is not set
# CONFIG_POWER_RESET_REGULATOR is not set
CONFIG_POWER_RESET_RESTART=y
# CONFIG_POWER_RESET_VEXPRESS is not set
# CONFIG_POWER_RESET_XGENE is not set
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
# CONFIG_NVMEM_REBOOT_MODE is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_PDA_POWER is not set
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_CHARGER_AXP20X is not set
# CONFIG_BATTERY_AXP20X is not set
CONFIG_AXP20X_POWER=y
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_BATTERY_MAX1721X is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
# CONFIG_CHARGER_GPIO is not set
# CONFIG_CHARGER_MANAGER is not set
# CONFIG_CHARGER_LT3651 is not set
# CONFIG_CHARGER_LTC4162L is not set
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_BQ25980 is not set
# CONFIG_CHARGER_BQ256XX is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_BATTERY_GOLDFISH is not set
# CONFIG_BATTERY_RT5033 is not set
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
CONFIG_HWMON=y
CONFIG_HWMON_VID=m
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM1177 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7310 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_AHT10 is not set
# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
# CONFIG_SENSORS_AS370 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
CONFIG_SENSORS_ARM_SCMI=m
CONFIG_SENSORS_ARM_SCPI=y
# CONFIG_SENSORS_ASPEED is not set
CONFIG_SENSORS_ATXP1=m
CONFIG_SENSORS_CORSAIR_CPRO=m
# CONFIG_SENSORS_CORSAIR_PSU is not set
CONFIG_SENSORS_DRIVETEMP=m
CONFIG_SENSORS_DS620=m
CONFIG_SENSORS_DS1621=m
CONFIG_SENSORS_I5K_AMB=m
CONFIG_SENSORS_F71805F=m
CONFIG_SENSORS_F71882FG=m
CONFIG_SENSORS_F75375S=m
CONFIG_SENSORS_FTSTEUTATES=m
CONFIG_SENSORS_GL518SM=m
CONFIG_SENSORS_GL520SM=m
CONFIG_SENSORS_G760A=m
CONFIG_SENSORS_G762=m
CONFIG_SENSORS_GPIO_FAN=m
CONFIG_SENSORS_HIH6130=m
CONFIG_SENSORS_IIO_HWMON=m
CONFIG_SENSORS_IT87=m
CONFIG_SENSORS_JC42=m
CONFIG_SENSORS_POWR1220=m
CONFIG_SENSORS_LINEAGE=m
CONFIG_SENSORS_LTC2945=m
CONFIG_SENSORS_LTC2947=m
CONFIG_SENSORS_LTC2947_I2C=m
CONFIG_SENSORS_LTC2947_SPI=m
CONFIG_SENSORS_LTC2990=m
# CONFIG_SENSORS_LTC2992 is not set
CONFIG_SENSORS_LTC4151=m
CONFIG_SENSORS_LTC4215=m
CONFIG_SENSORS_LTC4222=m
CONFIG_SENSORS_LTC4245=m
CONFIG_SENSORS_LTC4260=m
CONFIG_SENSORS_LTC4261=m
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX127 is not set
CONFIG_SENSORS_MAX16065=m
CONFIG_SENSORS_MAX1619=m
CONFIG_SENSORS_MAX1668=m
CONFIG_SENSORS_MAX197=m
CONFIG_SENSORS_MAX31722=m
CONFIG_SENSORS_MAX31730=m
CONFIG_SENSORS_MAX6621=m
CONFIG_SENSORS_MAX6639=m
CONFIG_SENSORS_MAX6642=m
CONFIG_SENSORS_MAX6650=m
CONFIG_SENSORS_MAX6697=m
CONFIG_SENSORS_MAX31790=m
CONFIG_SENSORS_MCP3021=m
CONFIG_SENSORS_TC654=m
# CONFIG_SENSORS_TPS23861 is not set
CONFIG_SENSORS_MR75203=m
CONFIG_SENSORS_ADCXX=m
CONFIG_SENSORS_LM63=m
CONFIG_SENSORS_LM70=m
CONFIG_SENSORS_LM73=m
CONFIG_SENSORS_LM75=m
CONFIG_SENSORS_LM77=m
CONFIG_SENSORS_LM78=m
CONFIG_SENSORS_LM80=m
CONFIG_SENSORS_LM83=m
CONFIG_SENSORS_LM85=m
CONFIG_SENSORS_LM87=m
CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_LM92=m
CONFIG_SENSORS_LM93=m
CONFIG_SENSORS_LM95234=m
CONFIG_SENSORS_LM95241=m
CONFIG_SENSORS_LM95245=m
CONFIG_SENSORS_PC87360=m
CONFIG_SENSORS_PC87427=m
CONFIG_SENSORS_NTC_THERMISTOR=m
CONFIG_SENSORS_NCT6683=m
CONFIG_SENSORS_NCT6775=m
CONFIG_SENSORS_NCT7802=m
CONFIG_SENSORS_NCT7904=m
CONFIG_SENSORS_NPCM7XX=m
# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
CONFIG_SENSORS_OCC_P8_I2C=m
CONFIG_SENSORS_OCC=m
CONFIG_SENSORS_PCF8591=m
# CONFIG_PMBUS is not set
CONFIG_SENSORS_PWM_FAN=m
# CONFIG_SENSORS_SBTSI is not set
# CONFIG_SENSORS_SBRMI is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHT4x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_TMP513 is not set
# CONFIG_SENSORS_VEXPRESS is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set

#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
# CONFIG_THERMAL_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
# CONFIG_THERMAL_EMULATION is not set
CONFIG_THERMAL_MMIO=y
CONFIG_SUN8I_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_AMLOGIC_THERMAL=y
CONFIG_GENERIC_ADC_THERMAL=m
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set
# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=m
# CONFIG_GPIO_WATCHDOG is not set
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
CONFIG_ARM_SP805_WATCHDOG=m
CONFIG_ARM_SBSA_WATCHDOG=y
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=m
CONFIG_SUNXI_WATCHDOG=m
# CONFIG_MAX63XX_WATCHDOG is not set
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_WATCHDOG=m
# CONFIG_ARM_SMC_WATCHDOG is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_MEN_A21_WDT is not set

#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB=m
CONFIG_SSB_SPROM=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_PCIHOST=y
CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
# CONFIG_SSB_PCMCIAHOST is not set
CONFIG_SSB_SDIOHOST_POSSIBLE=y
CONFIG_SSB_SDIOHOST=y
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
CONFIG_SSB_DRIVER_PCICORE=y
# CONFIG_SSB_DRIVER_GPIO is not set
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
# CONFIG_BCMA_HOST_PCI is not set
CONFIG_BCMA_HOST_SOC=y
# CONFIG_BCMA_DRIVER_PCI is not set
CONFIG_BCMA_SFLASH=y
CONFIG_BCMA_DRIVER_GMAC_CMN=y
CONFIG_BCMA_DRIVER_GPIO=y
CONFIG_BCMA_DEBUG=y

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
CONFIG_MFD_AC100=y
CONFIG_MFD_AC200=y
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
# CONFIG_MFD_MADERA is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_LPC_ICH is not set
CONFIG_LPC_SCH=m
# CONFIG_MFD_INTEL_PMT is not set
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_NTXEC is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_UCB1400_CORE is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT4831 is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RC5T583 is not set
CONFIG_MFD_RK808=y
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SUN6I_PRCM=y
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS80031 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TQMX86 is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
# CONFIG_MFD_ROHM_BD70528 is not set
# CONFIG_MFD_ROHM_BD71828 is not set
# CONFIG_MFD_ROHM_BD957XMUF is not set
# CONFIG_MFD_STPMIC1 is not set
CONFIG_MFD_STMFX=m
# CONFIG_MFD_ATC260X_I2C is not set
# CONFIG_MFD_KHADAS_MCU is not set
# CONFIG_MFD_QCOM_PM8008 is not set
# CONFIG_MFD_VEXPRESS_SYSREG is not set
# CONFIG_RAVE_SP_CORE is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# CONFIG_MFD_RSMU_I2C is not set
# CONFIG_MFD_RSMU_SPI is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_88PG86X is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_AD5398 is not set
# CONFIG_REGULATOR_ARM_SCMI is not set
CONFIG_REGULATOR_AXP20X=y
# CONFIG_REGULATOR_DA9121 is not set
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
CONFIG_REGULATOR_FAN53555=y
# CONFIG_REGULATOR_FAN53880 is not set
CONFIG_REGULATOR_GPIO=y
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_LP8755 is not set
# CONFIG_REGULATOR_LTC3589 is not set
# CONFIG_REGULATOR_LTC3676 is not set
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8893 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_MAX8973 is not set
# CONFIG_REGULATOR_MAX77826 is not set
# CONFIG_REGULATOR_MCP16502 is not set
# CONFIG_REGULATOR_MP5416 is not set
# CONFIG_REGULATOR_MP8859 is not set
# CONFIG_REGULATOR_MP886X is not set
# CONFIG_REGULATOR_MPQ7920 is not set
# CONFIG_REGULATOR_MT6311 is not set
# CONFIG_REGULATOR_MT6315 is not set
# CONFIG_REGULATOR_PCA9450 is not set
# CONFIG_REGULATOR_PF8X00 is not set
# CONFIG_REGULATOR_PFUZE100 is not set
# CONFIG_REGULATOR_PV88060 is not set
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
CONFIG_REGULATOR_PWM=y
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
CONFIG_REGULATOR_RK808=y
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RT6160 is not set
# CONFIG_REGULATOR_RT6245 is not set
# CONFIG_REGULATOR_RTQ2134 is not set
# CONFIG_REGULATOR_RTMV20 is not set
# CONFIG_REGULATOR_RTQ6752 is not set
# CONFIG_REGULATOR_SLG51000 is not set
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
# CONFIG_REGULATOR_SY8827N is not set
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_TPS6524X is not set
CONFIG_REGULATOR_VCTRL=y
# CONFIG_REGULATOR_VEXPRESS is not set
# CONFIG_REGULATOR_QCOM_LABIBB is not set
CONFIG_RC_CORE=y
CONFIG_RC_MAP=y
CONFIG_LIRC=y
# CONFIG_BPF_LIRC_MODE2 is not set
CONFIG_RC_DECODERS=y
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
CONFIG_IR_JVC_DECODER=m
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_XMP_DECODER=m
CONFIG_IR_IMON_DECODER=m
CONFIG_IR_RCMM_DECODER=m
CONFIG_RC_DEVICES=y
CONFIG_RC_ATI_REMOTE=m
# CONFIG_IR_ENE is not set
CONFIG_IR_HIX5HD2=m
CONFIG_IR_IMON=m
CONFIG_IR_IMON_RAW=m
CONFIG_IR_MCEUSB=m
# CONFIG_IR_ITE_CIR is not set
# CONFIG_IR_FINTEK is not set
CONFIG_IR_MESON=m
CONFIG_IR_MESON_TX=m
# CONFIG_IR_NUVOTON is not set
CONFIG_IR_REDRAT3=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m
CONFIG_IR_IGORPLUGUSB=m
CONFIG_IR_IGUANA=m
CONFIG_IR_TTUSBIR=m
CONFIG_RC_LOOPBACK=m
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_GPIO_TX=m
CONFIG_IR_PWM_TX=m
CONFIG_IR_SUNXI=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
# CONFIG_IR_SIR is not set
CONFIG_RC_XBOX_DVD=m
CONFIG_IR_TOY=m
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y
CONFIG_CEC_PIN=y
CONFIG_MEDIA_CEC_RC=y
CONFIG_CEC_PIN_ERROR_INJ=y
CONFIG_MEDIA_CEC_SUPPORT=y
# CONFIG_CEC_CH7322 is not set
CONFIG_CEC_MESON_AO=y
CONFIG_CEC_MESON_G12A_AO=y
# CONFIG_CEC_GPIO is not set
CONFIG_USB_PULSE8_CEC=m
CONFIG_USB_RAINSHADOW_CEC=m
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_SUPPORT_FILTER=y
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
CONFIG_MEDIA_RADIO_SUPPORT=y
CONFIG_MEDIA_SDR_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_TEST_SUPPORT=y
# end of Media device types

CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_DVB_CORE=y

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2=y
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_ADV_DEBUG=y
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_H264=m
CONFIG_V4L2_MEM2MEM_DEV=m
CONFIG_V4L2_FWNODE=m
CONFIG_V4L2_ASYNC=m
CONFIG_VIDEOBUF_GEN=m
CONFIG_VIDEOBUF_DMA_SG=m
CONFIG_VIDEOBUF_VMALLOC=m
# end of Video4Linux options

#
# Media controller options
#
CONFIG_MEDIA_CONTROLLER_DVB=y
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y

#
# Please notice that the enabled Media controller Request API is EXPERIMENTAL
#
# end of Media controller options

#
# Digital TV options
#
CONFIG_DVB_MMAP=y
CONFIG_DVB_NET=y
CONFIG_DVB_MAX_ADAPTERS=8
CONFIG_DVB_DYNAMIC_MINORS=y
# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
# CONFIG_DVB_ULE_DEBUG is not set
# end of Digital TV options

#
# Media drivers
#

#
# Drivers filtered as selected at 'Filter media drivers'
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_VIDEO_CLASS=m
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
CONFIG_USB_GSPCA=m
CONFIG_USB_M5602=m
CONFIG_USB_STV06XX=m
CONFIG_USB_GL860=m
CONFIG_USB_GSPCA_BENQ=m
CONFIG_USB_GSPCA_CONEX=m
CONFIG_USB_GSPCA_CPIA1=m
CONFIG_USB_GSPCA_DTCS033=m
CONFIG_USB_GSPCA_ETOMS=m
CONFIG_USB_GSPCA_FINEPIX=m
CONFIG_USB_GSPCA_JEILINJ=m
CONFIG_USB_GSPCA_JL2005BCD=m
CONFIG_USB_GSPCA_KINECT=m
CONFIG_USB_GSPCA_KONICA=m
CONFIG_USB_GSPCA_MARS=m
CONFIG_USB_GSPCA_MR97310A=m
CONFIG_USB_GSPCA_NW80X=m
CONFIG_USB_GSPCA_OV519=m
CONFIG_USB_GSPCA_OV534=m
CONFIG_USB_GSPCA_OV534_9=m
CONFIG_USB_GSPCA_PAC207=m
CONFIG_USB_GSPCA_PAC7302=m
CONFIG_USB_GSPCA_PAC7311=m
CONFIG_USB_GSPCA_SE401=m
CONFIG_USB_GSPCA_SN9C2028=m
CONFIG_USB_GSPCA_SN9C20X=m
CONFIG_USB_GSPCA_SONIXB=m
CONFIG_USB_GSPCA_SONIXJ=m
CONFIG_USB_GSPCA_SPCA500=m
CONFIG_USB_GSPCA_SPCA501=m
CONFIG_USB_GSPCA_SPCA505=m
CONFIG_USB_GSPCA_SPCA506=m
CONFIG_USB_GSPCA_SPCA508=m
CONFIG_USB_GSPCA_SPCA561=m
CONFIG_USB_GSPCA_SPCA1528=m
CONFIG_USB_GSPCA_SQ905=m
CONFIG_USB_GSPCA_SQ905C=m
CONFIG_USB_GSPCA_SQ930X=m
CONFIG_USB_GSPCA_STK014=m
CONFIG_USB_GSPCA_STK1135=m
CONFIG_USB_GSPCA_STV0680=m
CONFIG_USB_GSPCA_SUNPLUS=m
CONFIG_USB_GSPCA_T613=m
CONFIG_USB_GSPCA_TOPRO=m
CONFIG_USB_GSPCA_TOUPTEK=m
CONFIG_USB_GSPCA_TV8532=m
CONFIG_USB_GSPCA_VC032X=m
CONFIG_USB_GSPCA_VICAM=m
CONFIG_USB_GSPCA_XIRLINK_CIT=m
CONFIG_USB_GSPCA_ZC3XX=m
CONFIG_USB_PWC=m
# CONFIG_USB_PWC_DEBUG is not set
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_VIDEO_CPIA2=m
CONFIG_USB_ZR364XX=m
CONFIG_USB_STKWEBCAM=m
CONFIG_USB_S2255=m
CONFIG_VIDEO_USBTV=m

#
# Analog TV USB devices
#
CONFIG_VIDEO_PVRUSB2=m
CONFIG_VIDEO_PVRUSB2_SYSFS=y
CONFIG_VIDEO_PVRUSB2_DVB=y
# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
CONFIG_VIDEO_HDPVR=m
CONFIG_VIDEO_STK1160_COMMON=m
CONFIG_VIDEO_STK1160=m
CONFIG_VIDEO_GO7007=m
CONFIG_VIDEO_GO7007_USB=m
CONFIG_VIDEO_GO7007_LOADER=m
CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m

#
# Analog/digital TV USB devices
#
CONFIG_VIDEO_AU0828=m
CONFIG_VIDEO_AU0828_V4L2=y
CONFIG_VIDEO_AU0828_RC=y
CONFIG_VIDEO_CX231XX=m
CONFIG_VIDEO_CX231XX_RC=y
CONFIG_VIDEO_CX231XX_ALSA=m
CONFIG_VIDEO_CX231XX_DVB=m
CONFIG_VIDEO_TM6000=m
CONFIG_VIDEO_TM6000_ALSA=m
CONFIG_VIDEO_TM6000_DVB=m

#
# Digital TV USB devices
#
CONFIG_DVB_USB=m
# CONFIG_DVB_USB_DEBUG is not set
CONFIG_DVB_USB_DIB3000MC=m
CONFIG_DVB_USB_A800=m
CONFIG_DVB_USB_DIBUSB_MB=m
CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
CONFIG_DVB_USB_DIBUSB_MC=m
CONFIG_DVB_USB_DIB0700=m
CONFIG_DVB_USB_UMT_010=m
CONFIG_DVB_USB_CXUSB=m
# CONFIG_DVB_USB_CXUSB_ANALOG is not set
CONFIG_DVB_USB_M920X=m
CONFIG_DVB_USB_DIGITV=m
CONFIG_DVB_USB_VP7045=m
CONFIG_DVB_USB_VP702X=m
CONFIG_DVB_USB_GP8PSK=m
CONFIG_DVB_USB_NOVA_T_USB2=m
CONFIG_DVB_USB_TTUSB2=m
CONFIG_DVB_USB_DTT200U=m
CONFIG_DVB_USB_OPERA1=m
CONFIG_DVB_USB_AF9005=m
CONFIG_DVB_USB_AF9005_REMOTE=m
CONFIG_DVB_USB_PCTV452E=m
CONFIG_DVB_USB_DW2102=m
CONFIG_DVB_USB_CINERGY_T2=m
CONFIG_DVB_USB_DTV5100=m
CONFIG_DVB_USB_AZ6027=m
CONFIG_DVB_USB_TECHNISAT_USB2=m
CONFIG_DVB_USB_V2=m
CONFIG_DVB_USB_AF9015=m
CONFIG_DVB_USB_AF9035=m
CONFIG_DVB_USB_ANYSEE=m
CONFIG_DVB_USB_AU6610=m
CONFIG_DVB_USB_AZ6007=m
CONFIG_DVB_USB_CE6230=m
CONFIG_DVB_USB_EC168=m
CONFIG_DVB_USB_GL861=m
CONFIG_DVB_USB_LME2510=m
CONFIG_DVB_USB_MXL111SF=m
CONFIG_DVB_USB_RTL28XXU=m
CONFIG_DVB_USB_DVBSKY=m
CONFIG_DVB_USB_ZD1301=m
CONFIG_DVB_TTUSB_BUDGET=m
CONFIG_DVB_TTUSB_DEC=m
CONFIG_SMS_USB_DRV=m
CONFIG_DVB_B2C2_FLEXCOP_USB=m
# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
CONFIG_DVB_AS102=m

#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=m
CONFIG_VIDEO_EM28XX_V4L2=m
CONFIG_VIDEO_EM28XX_ALSA=m
CONFIG_VIDEO_EM28XX_DVB=m
CONFIG_VIDEO_EM28XX_RC=m

#
# Software defined radio USB devices
#
# CONFIG_USB_AIRSPY is not set
# CONFIG_USB_HACKRF is not set
# CONFIG_USB_MSI2500 is not set
# CONFIG_MEDIA_PCI_SUPPORT is not set
CONFIG_RADIO_ADAPTERS=y
CONFIG_RADIO_TEA575X=m
CONFIG_RADIO_SI470X=m
CONFIG_USB_SI470X=m
CONFIG_I2C_SI470X=m
CONFIG_RADIO_SI4713=m
CONFIG_USB_SI4713=m
CONFIG_PLATFORM_SI4713=m
CONFIG_I2C_SI4713=m
CONFIG_USB_MR800=m
CONFIG_USB_DSBR=m
CONFIG_RADIO_MAXIRADIO=m
CONFIG_RADIO_SHARK=m
CONFIG_RADIO_SHARK2=m
CONFIG_USB_KEENE=m
CONFIG_USB_RAREMONO=m
CONFIG_USB_MA901=m
CONFIG_RADIO_TEA5764=m
CONFIG_RADIO_SAA7706H=m
CONFIG_RADIO_TEF6862=m
CONFIG_RADIO_WL1273=m
CONFIG_MEDIA_COMMON_OPTIONS=y

#
# common driver options
#
CONFIG_VIDEO_CX2341X=m
CONFIG_VIDEO_TVEEPROM=m
CONFIG_TTPCI_EEPROM=m
CONFIG_CYPRESS_FIRMWARE=m
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_VIDEOBUF2_DMA_SG=m
CONFIG_DVB_B2C2_FLEXCOP=m
CONFIG_VIDEO_SAA7146=m
CONFIG_VIDEO_SAA7146_VV=m
CONFIG_SMS_SIANO_MDTV=m
CONFIG_SMS_SIANO_RC=y
# CONFIG_V4L_PLATFORM_DRIVERS is not set
# CONFIG_V4L_MEM2MEM_DRIVERS is not set
# CONFIG_DVB_PLATFORM_DRIVERS is not set
# CONFIG_SDR_PLATFORM_DRIVERS is not set

#
# MMC/SDIO DVB adapters
#
# CONFIG_SMS_SDIO_DRV is not set
# CONFIG_V4L_TEST_DRIVERS is not set
# CONFIG_DVB_TEST_DRIVERS is not set
# end of Media drivers

#
# Media ancillary drivers
#
CONFIG_MEDIA_ATTACH=y

#
# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
#
CONFIG_VIDEO_IR_I2C=m

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_TVAUDIO=m
CONFIG_VIDEO_TDA7432=m
CONFIG_VIDEO_TDA9840=m
CONFIG_VIDEO_TDA1997X=m
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
CONFIG_VIDEO_MSP3400=m
CONFIG_VIDEO_CS3308=m
CONFIG_VIDEO_CS5345=m
CONFIG_VIDEO_CS53L32A=m
CONFIG_VIDEO_TLV320AIC23B=m
CONFIG_VIDEO_UDA1342=m
CONFIG_VIDEO_WM8775=m
CONFIG_VIDEO_WM8739=m
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_SONY_BTF_MPX=m
# end of Audio decoders, processors and mixers

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders

#
# Video decoders
#
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_ADV7183=m
CONFIG_VIDEO_ADV748X=m
CONFIG_VIDEO_ADV7604=m
# CONFIG_VIDEO_ADV7604_CEC is not set
CONFIG_VIDEO_ADV7842=m
# CONFIG_VIDEO_ADV7842_CEC is not set
CONFIG_VIDEO_BT819=m
CONFIG_VIDEO_BT856=m
CONFIG_VIDEO_BT866=m
CONFIG_VIDEO_KS0127=m
CONFIG_VIDEO_ML86V7667=m
CONFIG_VIDEO_SAA7110=m
CONFIG_VIDEO_SAA711X=m
CONFIG_VIDEO_TC358743=m
# CONFIG_VIDEO_TC358743_CEC is not set
CONFIG_VIDEO_TVP514X=m
CONFIG_VIDEO_TVP5150=m
CONFIG_VIDEO_TVP7002=m
CONFIG_VIDEO_TW2804=m
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=m
CONFIG_VIDEO_TW9910=m
CONFIG_VIDEO_VPX3220=m
# CONFIG_VIDEO_MAX9286 is not set

#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=m
CONFIG_VIDEO_CX25840=m
# end of Video decoders

#
# Video encoders
#
CONFIG_VIDEO_SAA7127=m
CONFIG_VIDEO_SAA7185=m
CONFIG_VIDEO_ADV7170=m
CONFIG_VIDEO_ADV7175=m
CONFIG_VIDEO_ADV7343=m
CONFIG_VIDEO_ADV7393=m
# CONFIG_VIDEO_ADV7511 is not set
CONFIG_VIDEO_AD9389B=m
CONFIG_VIDEO_AK881X=m
CONFIG_VIDEO_THS8200=m
# end of Video encoders

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
CONFIG_VIDEO_UPD64083=m
# end of Video improvement chips

#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips

#
# SDR tuner chips
#
# CONFIG_SDR_MAX2175 is not set
# end of SDR tuner chips

#
# Miscellaneous helper chips
#
CONFIG_VIDEO_THS7303=m
CONFIG_VIDEO_M52790=m
CONFIG_VIDEO_I2C=m
CONFIG_VIDEO_ST_MIPID02=m
# end of Miscellaneous helper chips

#
# Camera sensor devices
#
CONFIG_VIDEO_APTINA_PLL=m
CONFIG_VIDEO_HI556=m
# CONFIG_VIDEO_IMX208 is not set
CONFIG_VIDEO_IMX214=m
CONFIG_VIDEO_IMX219=m
CONFIG_VIDEO_IMX258=m
CONFIG_VIDEO_IMX274=m
CONFIG_VIDEO_IMX290=m
CONFIG_VIDEO_IMX319=m
# CONFIG_VIDEO_IMX334 is not set
# CONFIG_VIDEO_IMX335 is not set
CONFIG_VIDEO_IMX355=m
# CONFIG_VIDEO_IMX412 is not set
# CONFIG_VIDEO_OV02A10 is not set
CONFIG_VIDEO_OV2640=m
CONFIG_VIDEO_OV2659=m
CONFIG_VIDEO_OV2680=m
CONFIG_VIDEO_OV2685=m
# CONFIG_VIDEO_OV2740 is not set
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_OV5647=m
# CONFIG_VIDEO_OV5648 is not set
CONFIG_VIDEO_OV6650=m
CONFIG_VIDEO_OV5670=m
CONFIG_VIDEO_OV5675=m
CONFIG_VIDEO_OV5695=m
CONFIG_VIDEO_OV7251=m
CONFIG_VIDEO_OV772X=m
CONFIG_VIDEO_OV7640=m
CONFIG_VIDEO_OV7670=m
CONFIG_VIDEO_OV7740=m
CONFIG_VIDEO_OV8856=m
# CONFIG_VIDEO_OV8865 is not set
# CONFIG_VIDEO_OV9282 is not set
CONFIG_VIDEO_OV9640=m
CONFIG_VIDEO_OV9650=m
# CONFIG_VIDEO_OV9734 is not set
CONFIG_VIDEO_OV13858=m
CONFIG_VIDEO_VS6624=m
CONFIG_VIDEO_MT9M001=m
CONFIG_VIDEO_MT9M032=m
CONFIG_VIDEO_MT9M111=m
CONFIG_VIDEO_MT9P031=m
CONFIG_VIDEO_MT9T001=m
CONFIG_VIDEO_MT9T112=m
CONFIG_VIDEO_MT9V011=m
CONFIG_VIDEO_MT9V032=m
CONFIG_VIDEO_MT9V111=m
CONFIG_VIDEO_SR030PC30=m
CONFIG_VIDEO_NOON010PC30=m
CONFIG_VIDEO_M5MOLS=m
# CONFIG_VIDEO_RDACM20 is not set
# CONFIG_VIDEO_RDACM21 is not set
CONFIG_VIDEO_RJ54N1=m
CONFIG_VIDEO_S5K6AA=m
CONFIG_VIDEO_S5K6A3=m
CONFIG_VIDEO_S5K4ECGX=m
CONFIG_VIDEO_S5K5BAF=m
# CONFIG_VIDEO_CCS is not set
CONFIG_VIDEO_ET8EK8=m
CONFIG_VIDEO_S5C73M3=m
# end of Camera sensor devices

#
# Lens drivers
#
CONFIG_VIDEO_AD5820=m
CONFIG_VIDEO_AK7375=m
CONFIG_VIDEO_DW9714=m
# CONFIG_VIDEO_DW9768 is not set
CONFIG_VIDEO_DW9807_VCM=m
# end of Lens drivers

#
# Flash devices
#
CONFIG_VIDEO_ADP1653=m
CONFIG_VIDEO_LM3560=m
CONFIG_VIDEO_LM3646=m
# end of Flash devices

#
# SPI helper chips
#
CONFIG_VIDEO_GS1662=m
# end of SPI helper chips

#
# Media SPI Adapters
#
CONFIG_CXD2880_SPI_DRV=m
# end of Media SPI Adapters

CONFIG_MEDIA_TUNER=y

#
# Customize TV tuners
#
CONFIG_MEDIA_TUNER_SIMPLE=y
CONFIG_MEDIA_TUNER_TDA18250=m
CONFIG_MEDIA_TUNER_TDA8290=y
CONFIG_MEDIA_TUNER_TDA827X=y
CONFIG_MEDIA_TUNER_TDA18271=y
CONFIG_MEDIA_TUNER_TDA9887=y
CONFIG_MEDIA_TUNER_TEA5761=y
CONFIG_MEDIA_TUNER_TEA5767=y
CONFIG_MEDIA_TUNER_MSI001=m
CONFIG_MEDIA_TUNER_MT20XX=y
CONFIG_MEDIA_TUNER_MT2060=m
CONFIG_MEDIA_TUNER_MT2063=m
CONFIG_MEDIA_TUNER_MT2266=m
CONFIG_MEDIA_TUNER_MT2131=m
CONFIG_MEDIA_TUNER_QT1010=m
CONFIG_MEDIA_TUNER_XC2028=y
CONFIG_MEDIA_TUNER_XC5000=y
CONFIG_MEDIA_TUNER_XC4000=y
CONFIG_MEDIA_TUNER_MXL5005S=m
CONFIG_MEDIA_TUNER_MXL5007T=m
CONFIG_MEDIA_TUNER_MC44S803=y
CONFIG_MEDIA_TUNER_MAX2165=m
CONFIG_MEDIA_TUNER_TDA18218=m
CONFIG_MEDIA_TUNER_FC0011=m
CONFIG_MEDIA_TUNER_FC0012=m
CONFIG_MEDIA_TUNER_FC0013=m
CONFIG_MEDIA_TUNER_TDA18212=m
CONFIG_MEDIA_TUNER_E4000=m
CONFIG_MEDIA_TUNER_FC2580=m
CONFIG_MEDIA_TUNER_M88RS6000T=m
CONFIG_MEDIA_TUNER_TUA9001=m
CONFIG_MEDIA_TUNER_SI2157=m
CONFIG_MEDIA_TUNER_IT913X=m
CONFIG_MEDIA_TUNER_R820T=m
CONFIG_MEDIA_TUNER_MXL301RF=m
CONFIG_MEDIA_TUNER_QM1D1C0042=m
CONFIG_MEDIA_TUNER_QM1D1B0004=m
# end of Customize TV tuners

#
# Customise DVB Frontends
#

#
# Multistandard (satellite) frontends
#
CONFIG_DVB_STB0899=m
CONFIG_DVB_STB6100=m
CONFIG_DVB_STV090x=m
CONFIG_DVB_STV0910=m
CONFIG_DVB_STV6110x=m
CONFIG_DVB_STV6111=m
CONFIG_DVB_MXL5XX=m
CONFIG_DVB_M88DS3103=m

#
# Multistandard (cable + terrestrial) frontends
#
CONFIG_DVB_DRXK=m
CONFIG_DVB_TDA18271C2DD=m
CONFIG_DVB_SI2165=m
CONFIG_DVB_MN88472=m
CONFIG_DVB_MN88473=m

#
# DVB-S (satellite) frontends
#
CONFIG_DVB_CX24110=m
CONFIG_DVB_CX24123=m
CONFIG_DVB_MT312=m
CONFIG_DVB_ZL10036=m
CONFIG_DVB_ZL10039=m
CONFIG_DVB_S5H1420=m
CONFIG_DVB_STV0288=m
CONFIG_DVB_STB6000=m
CONFIG_DVB_STV0299=m
CONFIG_DVB_STV6110=m
CONFIG_DVB_STV0900=m
CONFIG_DVB_TDA8083=m
CONFIG_DVB_TDA10086=m
CONFIG_DVB_TDA8261=m
CONFIG_DVB_VES1X93=m
CONFIG_DVB_TUNER_ITD1000=m
CONFIG_DVB_TUNER_CX24113=m
CONFIG_DVB_TDA826X=m
CONFIG_DVB_TUA6100=m
CONFIG_DVB_CX24116=m
CONFIG_DVB_CX24117=m
CONFIG_DVB_CX24120=m
CONFIG_DVB_SI21XX=m
CONFIG_DVB_TS2020=m
CONFIG_DVB_DS3000=m
CONFIG_DVB_MB86A16=m
CONFIG_DVB_TDA10071=m

#
# DVB-T (terrestrial) frontends
#
CONFIG_DVB_SP887X=m
CONFIG_DVB_CX22700=m
CONFIG_DVB_CX22702=m
CONFIG_DVB_S5H1432=m
CONFIG_DVB_DRXD=m
CONFIG_DVB_L64781=m
CONFIG_DVB_TDA1004X=m
CONFIG_DVB_NXT6000=m
CONFIG_DVB_MT352=m
CONFIG_DVB_ZL10353=m
CONFIG_DVB_DIB3000MB=m
CONFIG_DVB_DIB3000MC=m
CONFIG_DVB_DIB7000M=m
CONFIG_DVB_DIB7000P=m
CONFIG_DVB_DIB9000=m
CONFIG_DVB_TDA10048=m
CONFIG_DVB_AF9013=m
CONFIG_DVB_EC100=m
CONFIG_DVB_STV0367=m
CONFIG_DVB_CXD2820R=m
CONFIG_DVB_CXD2841ER=m
CONFIG_DVB_RTL2830=m
CONFIG_DVB_RTL2832=m
CONFIG_DVB_RTL2832_SDR=m
CONFIG_DVB_SI2168=m
CONFIG_DVB_AS102_FE=m
CONFIG_DVB_ZD1301_DEMOD=m
CONFIG_DVB_GP8PSK_FE=m
CONFIG_DVB_CXD2880=m

#
# DVB-C (cable) frontends
#
CONFIG_DVB_VES1820=m
CONFIG_DVB_TDA10021=m
CONFIG_DVB_TDA10023=m
CONFIG_DVB_STV0297=m

#
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
#
CONFIG_DVB_NXT200X=m
CONFIG_DVB_OR51211=m
CONFIG_DVB_OR51132=m
CONFIG_DVB_BCM3510=m
CONFIG_DVB_LGDT330X=m
CONFIG_DVB_LGDT3305=m
CONFIG_DVB_LGDT3306A=m
CONFIG_DVB_LG2160=m
CONFIG_DVB_S5H1409=m
CONFIG_DVB_AU8522=m
CONFIG_DVB_AU8522_DTV=m
CONFIG_DVB_AU8522_V4L=m
CONFIG_DVB_S5H1411=m
CONFIG_DVB_MXL692=m

#
# ISDB-T (terrestrial) frontends
#
CONFIG_DVB_S921=m
CONFIG_DVB_DIB8000=m
CONFIG_DVB_MB86A20S=m

#
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
#
CONFIG_DVB_TC90522=m
CONFIG_DVB_MN88443X=m

#
# Digital terrestrial only tuners/PLL
#
CONFIG_DVB_PLL=m
CONFIG_DVB_TUNER_DIB0070=m
CONFIG_DVB_TUNER_DIB0090=m

#
# SEC control devices for DVB-S
#
CONFIG_DVB_DRX39XYJ=m
CONFIG_DVB_LNBH25=m
CONFIG_DVB_LNBH29=m
CONFIG_DVB_LNBP21=m
CONFIG_DVB_LNBP22=m
CONFIG_DVB_ISL6405=m
CONFIG_DVB_ISL6421=m
CONFIG_DVB_ISL6423=m
CONFIG_DVB_A8293=m
CONFIG_DVB_LGS8GL5=m
CONFIG_DVB_LGS8GXX=m
CONFIG_DVB_ATBM8830=m
CONFIG_DVB_TDA665x=m
CONFIG_DVB_IX2505V=m
CONFIG_DVB_M88RS2000=m
CONFIG_DVB_AF9033=m
CONFIG_DVB_HORUS3A=m
CONFIG_DVB_ASCOT2E=m
CONFIG_DVB_HELENE=m

#
# Common Interface (EN50221) controller drivers
#
CONFIG_DVB_CXD2099=m
CONFIG_DVB_SP2=m
# end of Customise DVB Frontends

#
# Tools to develop new frontends
#
CONFIG_DVB_DUMMY_FE=m
# end of Media ancillary drivers

#
# Graphics support
#
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
CONFIG_DRM=y
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_TTM=m
CONFIG_DRM_TTM_HELPER=m
CONFIG_DRM_GEM_CMA_HELPER=y
CONFIG_DRM_KMS_CMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=y
CONFIG_DRM_SCHED=m

#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips

#
# ARM devices
#
CONFIG_DRM_HDLCD=m
CONFIG_DRM_HDLCD_SHOW_UNDERRUN=y
CONFIG_DRM_MALI_DISPLAY=m
CONFIG_DRM_KOMEDA=m
# end of ARM devices

# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
CONFIG_DRM_ROCKCHIP=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_ROCKCHIP_LVDS=y
CONFIG_ROCKCHIP_RGB=y
CONFIG_ROCKCHIP_RK3066_HDMI=y
# CONFIG_DRM_VMWGFX is not set
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_USE_LVDS is not set
CONFIG_DRM_SUN4I=y
CONFIG_DRM_SUN4I_HDMI=y
CONFIG_DRM_SUN4I_HDMI_AUDIO=y
CONFIG_DRM_SUN4I_HDMI_CEC=y
CONFIG_DRM_SUN4I_BACKEND=y
CONFIG_DRM_SUN6I_DSI=y
CONFIG_DRM_SUN8I_DW_HDMI=y
CONFIG_DRM_SUN8I_MIXER=y
CONFIG_DRM_SUN8I_TCON_TOP=y
CONFIG_DRM_QXL=m
CONFIG_DRM_VIRTIO_GPU=m
CONFIG_DRM_PANEL=y

#
# Display Panels
#
# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
# CONFIG_DRM_PANEL_DSI_CM is not set
# CONFIG_DRM_PANEL_LVDS is not set
# CONFIG_DRM_PANEL_SIMPLE is not set
# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
# CONFIG_DRM_PANEL_KHADAS_TS050 is not set
# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
# CONFIG_DRM_PANEL_LG_LG4573 is not set
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set
# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CHIPONE_ICN6211 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
CONFIG_DRM_DISPLAY_CONNECTOR=y
# CONFIG_DRM_LONTIUM_LT8912B is not set
# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LONTIUM_LT9611UXC is not set
# CONFIG_DRM_ITE_IT66121 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI83 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
CONFIG_DRM_ANALOGIX_DP=y
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=y
CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
CONFIG_DRM_DW_HDMI_CEC=y
CONFIG_DRM_DW_MIPI_DSI=y
# end of Display Interface Bridges

# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
CONFIG_DRM_MESON=y
CONFIG_DRM_MESON_DW_HDMI=y
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_BOCHS is not set
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_GM12U320 is not set
# CONFIG_DRM_SIMPLEDRM is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_DRM_PL111 is not set
CONFIG_DRM_LIMA=m
CONFIG_DRM_PANFROST=m
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_GUD is not set
# CONFIG_DRM_LEGACY is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y

#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_BACKLIGHT=m
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
CONFIG_FB_ARMCLCD=y
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_UVESA is not set
CONFIG_FB_EFI=y
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
CONFIG_FB_SIMPLE=y
# CONFIG_FB_SSD1307 is not set
# CONFIG_FB_SM712 is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_L4F00242T03 is not set
# CONFIG_LCD_LMS283GF05 is not set
# CONFIG_LCD_LTV350QV is not set
# CONFIG_LCD_ILI922X is not set
# CONFIG_LCD_ILI9320 is not set
# CONFIG_LCD_TDO24M is not set
# CONFIG_LCD_VGG2432A4 is not set
# CONFIG_LCD_PLATFORM is not set
# CONFIG_LCD_AMS369FG06 is not set
# CONFIG_LCD_LMS501KF03 is not set
# CONFIG_LCD_HX8357 is not set
# CONFIG_LCD_OTM3225A is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_KTD253 is not set
CONFIG_BACKLIGHT_PWM=m
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
CONFIG_BACKLIGHT_GPIO=m
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
CONFIG_BACKLIGHT_LED=m
# end of Backlight & LCD device support

CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
# end of Console display driver support

CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
# end of Graphics support

CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=m
CONFIG_SND_SEQ_DEVICE=m
CONFIG_SND_RAWMIDI=m
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_OSSEMUL is not set
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
CONFIG_SND_VMASTER=y
CONFIG_SND_SEQUENCER=m
CONFIG_SND_SEQ_DUMMY=m
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
CONFIG_SND_SEQ_MIDI_EVENT=m
CONFIG_SND_SEQ_MIDI=m
CONFIG_SND_MPU401_UART=m
CONFIG_SND_AC97_CODEC=m
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
# CONFIG_SND_VIRMIDI is not set
CONFIG_SND_MTPAV=m
CONFIG_SND_SERIAL_U16550=m
CONFIG_SND_MPU401=m
# CONFIG_SND_AC97_POWER_SAVE is not set
# CONFIG_SND_PCI is not set

#
# HD-Audio
#
# end of HD-Audio

CONFIG_SND_HDA_PREALLOC_SIZE=2048
# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
CONFIG_SND_BCD2000=m
CONFIG_SND_USB_LINE6=m
CONFIG_SND_USB_POD=m
CONFIG_SND_USB_PODHD=m
CONFIG_SND_USB_TONEPORT=m
CONFIG_SND_USB_VARIAX=m
CONFIG_SND_PCMCIA=y
# CONFIG_SND_VXPOCKET is not set
# CONFIG_SND_PDAUDIOCF is not set
CONFIG_SND_SOC=y
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
# CONFIG_SND_SOC_ADI is not set
# CONFIG_SND_SOC_AMD_ACP is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
CONFIG_SND_DESIGNWARE_I2S=m
CONFIG_SND_DESIGNWARE_PCM=y

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
# CONFIG_SND_SOC_FSL_SAI is not set
# CONFIG_SND_SOC_FSL_AUDMIX is not set
# CONFIG_SND_SOC_FSL_SSI is not set
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
# CONFIG_SND_SOC_FSL_MICFIL is not set
# CONFIG_SND_SOC_FSL_XCVR is not set
# CONFIG_SND_SOC_FSL_RPMSG is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs

# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set

#
# ASoC support for Amlogic platforms
#
CONFIG_SND_MESON_AIU=m
CONFIG_SND_MESON_AXG_FIFO=m
CONFIG_SND_MESON_AXG_FRDDR=m
CONFIG_SND_MESON_AXG_TODDR=m
CONFIG_SND_MESON_AXG_TDM_FORMATTER=m
CONFIG_SND_MESON_AXG_TDM_INTERFACE=m
CONFIG_SND_MESON_AXG_TDMIN=m
CONFIG_SND_MESON_AXG_TDMOUT=m
CONFIG_SND_MESON_AXG_SOUND_CARD=m
CONFIG_SND_MESON_AXG_SPDIFOUT=m
CONFIG_SND_MESON_AXG_SPDIFIN=m
CONFIG_SND_MESON_AXG_PDM=m
CONFIG_SND_MESON_CARD_UTILS=m
CONFIG_SND_MESON_CODEC_GLUE=m
CONFIG_SND_MESON_GX_SOUND_CARD=m
CONFIG_SND_MESON_G12A_TOACODEC=m
CONFIG_SND_MESON_G12A_TOHDMITX=m
CONFIG_SND_SOC_MESON_T9015=m
# end of ASoC support for Amlogic platforms

CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_ROCKCHIP_I2S=m
CONFIG_SND_SOC_ROCKCHIP_PDM=m
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
CONFIG_SND_SOC_ROCKCHIP_RT5645=m
CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m
CONFIG_SND_SOC_RK3399_GRU_SOUND=m
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set

#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support

#
# Allwinner SoC Audio support
#
CONFIG_SND_SUN4I_CODEC=m
CONFIG_SND_SUN8I_CODEC=m
CONFIG_SND_SUN8I_CODEC_ANALOG=m
CONFIG_SND_SUN50I_CODEC_ANALOG=m
CONFIG_SND_SUN4I_I2S=m
CONFIG_SND_SUN4I_SPDIF=m
CONFIG_SND_SUN8I_ADDA_PR_REGMAP=m
# end of Allwinner SoC Audio support

# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# CONFIG_SND_SOC_XTFPGA_I2S is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
CONFIG_SND_SOC_AC97_CODEC=m
# CONFIG_SND_SOC_ADAU1372_I2C is not set
# CONFIG_SND_SOC_ADAU1372_SPI is not set
# CONFIG_SND_SOC_ADAU1701 is not set
# CONFIG_SND_SOC_ADAU1761_I2C is not set
# CONFIG_SND_SOC_ADAU1761_SPI is not set
# CONFIG_SND_SOC_ADAU7002 is not set
# CONFIG_SND_SOC_ADAU7118_HW is not set
# CONFIG_SND_SOC_ADAU7118_I2C is not set
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_AK4118 is not set
# CONFIG_SND_SOC_AK4458 is not set
# CONFIG_SND_SOC_AK4554 is not set
# CONFIG_SND_SOC_AK4613 is not set
# CONFIG_SND_SOC_AK4642 is not set
# CONFIG_SND_SOC_AK5386 is not set
# CONFIG_SND_SOC_AK5558 is not set
# CONFIG_SND_SOC_ALC5623 is not set
# CONFIG_SND_SOC_BD28623 is not set
# CONFIG_SND_SOC_BT_SCO is not set
# CONFIG_SND_SOC_CS35L32 is not set
# CONFIG_SND_SOC_CS35L33 is not set
# CONFIG_SND_SOC_CS35L34 is not set
# CONFIG_SND_SOC_CS35L35 is not set
# CONFIG_SND_SOC_CS35L36 is not set
# CONFIG_SND_SOC_CS42L42 is not set
# CONFIG_SND_SOC_CS42L51_I2C is not set
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_CS42L73 is not set
# CONFIG_SND_SOC_CS4234 is not set
# CONFIG_SND_SOC_CS4265 is not set
# CONFIG_SND_SOC_CS4270 is not set
# CONFIG_SND_SOC_CS4271_I2C is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_CS42XX8_I2C is not set
# CONFIG_SND_SOC_CS43130 is not set
# CONFIG_SND_SOC_CS4341 is not set
# CONFIG_SND_SOC_CS4349 is not set
# CONFIG_SND_SOC_CS53L30 is not set
# CONFIG_SND_SOC_CX2072X is not set
# CONFIG_SND_SOC_DA7213 is not set
CONFIG_SND_SOC_DA7219=m
CONFIG_SND_SOC_DMIC=m
CONFIG_SND_SOC_HDMI_CODEC=y
# CONFIG_SND_SOC_ES7134 is not set
# CONFIG_SND_SOC_ES7241 is not set
# CONFIG_SND_SOC_ES8316 is not set
CONFIG_SND_SOC_ES8328=m
CONFIG_SND_SOC_ES8328_I2C=m
CONFIG_SND_SOC_ES8328_SPI=m
# CONFIG_SND_SOC_GTM601 is not set
# CONFIG_SND_SOC_ICS43432 is not set
CONFIG_SND_SOC_INNO_RK3036=m
# CONFIG_SND_SOC_MAX98088 is not set
CONFIG_SND_SOC_MAX98090=m
CONFIG_SND_SOC_MAX98357A=m
# CONFIG_SND_SOC_MAX98504 is not set
# CONFIG_SND_SOC_MAX9867 is not set
# CONFIG_SND_SOC_MAX98927 is not set
# CONFIG_SND_SOC_MAX98373_I2C is not set
# CONFIG_SND_SOC_MAX98390 is not set
# CONFIG_SND_SOC_MAX9860 is not set
# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set
# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
# CONFIG_SND_SOC_PCM1681 is not set
# CONFIG_SND_SOC_PCM1789_I2C is not set
# CONFIG_SND_SOC_PCM179X_I2C is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_I2C is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3060_I2C is not set
# CONFIG_SND_SOC_PCM3060_SPI is not set
# CONFIG_SND_SOC_PCM3168A_I2C is not set
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM5102A is not set
# CONFIG_SND_SOC_PCM512x_I2C is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
CONFIG_SND_SOC_RK3328=m
CONFIG_SND_SOC_RK817=m
CONFIG_SND_SOC_RL6231=m
CONFIG_SND_SOC_RT5514=m
CONFIG_SND_SOC_RT5514_SPI=m
# CONFIG_SND_SOC_RT5616 is not set
# CONFIG_SND_SOC_RT5631 is not set
# CONFIG_SND_SOC_RT5640 is not set
CONFIG_SND_SOC_RT5645=m
# CONFIG_SND_SOC_RT5659 is not set
# CONFIG_SND_SOC_SGTL5000 is not set
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
# CONFIG_SND_SOC_SIMPLE_MUX is not set
CONFIG_SND_SOC_SPDIF=m
# CONFIG_SND_SOC_SSM2305 is not set
# CONFIG_SND_SOC_SSM2518 is not set
# CONFIG_SND_SOC_SSM2602_SPI is not set
# CONFIG_SND_SOC_SSM2602_I2C is not set
# CONFIG_SND_SOC_SSM4567 is not set
# CONFIG_SND_SOC_STA32X is not set
# CONFIG_SND_SOC_STA350 is not set
# CONFIG_SND_SOC_STI_SAS is not set
# CONFIG_SND_SOC_TAS2552 is not set
# CONFIG_SND_SOC_TAS2562 is not set
# CONFIG_SND_SOC_TAS2764 is not set
# CONFIG_SND_SOC_TAS2770 is not set
# CONFIG_SND_SOC_TAS5086 is not set
# CONFIG_SND_SOC_TAS571X is not set
# CONFIG_SND_SOC_TAS5720 is not set
# CONFIG_SND_SOC_TAS6424 is not set
# CONFIG_SND_SOC_TDA7419 is not set
# CONFIG_SND_SOC_TFA9879 is not set
# CONFIG_SND_SOC_TFA989X is not set
# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC31XX is not set
# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set
# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set
# CONFIG_SND_SOC_TLV320ADCX140 is not set
CONFIG_SND_SOC_TS3A227E=m
# CONFIG_SND_SOC_TSCS42XX is not set
# CONFIG_SND_SOC_TSCS454 is not set
# CONFIG_SND_SOC_UDA1334 is not set
# CONFIG_SND_SOC_WM8510 is not set
# CONFIG_SND_SOC_WM8523 is not set
# CONFIG_SND_SOC_WM8524 is not set
# CONFIG_SND_SOC_WM8580 is not set
# CONFIG_SND_SOC_WM8711 is not set
# CONFIG_SND_SOC_WM8728 is not set
# CONFIG_SND_SOC_WM8731 is not set
# CONFIG_SND_SOC_WM8737 is not set
# CONFIG_SND_SOC_WM8741 is not set
# CONFIG_SND_SOC_WM8750 is not set
# CONFIG_SND_SOC_WM8753 is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8776 is not set
# CONFIG_SND_SOC_WM8782 is not set
# CONFIG_SND_SOC_WM8804_I2C is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_WM8903 is not set
# CONFIG_SND_SOC_WM8904 is not set
# CONFIG_SND_SOC_WM8960 is not set
# CONFIG_SND_SOC_WM8962 is not set
# CONFIG_SND_SOC_WM8974 is not set
# CONFIG_SND_SOC_WM8978 is not set
# CONFIG_SND_SOC_WM8985 is not set
# CONFIG_SND_SOC_ZL38060 is not set
# CONFIG_SND_SOC_MAX9759 is not set
# CONFIG_SND_SOC_MT6351 is not set
# CONFIG_SND_SOC_MT6358 is not set
# CONFIG_SND_SOC_MT6660 is not set
# CONFIG_SND_SOC_NAU8315 is not set
# CONFIG_SND_SOC_NAU8540 is not set
# CONFIG_SND_SOC_NAU8810 is not set
# CONFIG_SND_SOC_NAU8822 is not set
# CONFIG_SND_SOC_NAU8824 is not set
# CONFIG_SND_SOC_TPA6130A2 is not set
# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set
# CONFIG_SND_SOC_LPASS_VA_MACRO is not set
# CONFIG_SND_SOC_LPASS_RX_MACRO is not set
# CONFIG_SND_SOC_LPASS_TX_MACRO is not set
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_SND_VIRTIO=m
CONFIG_AC97_BUS=y

#
# HID support
#
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=m
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
CONFIG_HID_A4TECH=m
CONFIG_HID_ACCUTOUCH=m
CONFIG_HID_ACRUX=m
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=m
CONFIG_HID_APPLEIR=m
CONFIG_HID_ASUS=m
CONFIG_HID_AUREAL=m
CONFIG_HID_BELKIN=m
CONFIG_HID_BETOP_FF=m
CONFIG_HID_BIGBEN_FF=m
CONFIG_HID_CHERRY=m
CONFIG_HID_CHICONY=m
CONFIG_HID_CORSAIR=m
CONFIG_HID_COUGAR=m
CONFIG_HID_MACALLY=m
CONFIG_HID_PRODIKEYS=m
CONFIG_HID_CMEDIA=m
CONFIG_HID_CP2112=m
CONFIG_HID_CREATIVE_SB0540=m
CONFIG_HID_CYPRESS=m
CONFIG_HID_DRAGONRISE=m
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=m
CONFIG_HID_ELAN=m
CONFIG_HID_ELECOM=m
CONFIG_HID_ELO=m
CONFIG_HID_EZKEY=m
CONFIG_HID_FT260=m
CONFIG_HID_GEMBIRD=m
CONFIG_HID_GFRM=m
CONFIG_HID_GLORIOUS=m
CONFIG_HID_HOLTEK=m
CONFIG_HOLTEK_FF=y
CONFIG_HID_VIVALDI=m
CONFIG_HID_GT683R=m
CONFIG_HID_KEYTOUCH=m
CONFIG_HID_KYE=m
CONFIG_HID_UCLOGIC=m
CONFIG_HID_WALTOP=m
CONFIG_HID_VIEWSONIC=m
CONFIG_HID_GYRATION=m
CONFIG_HID_ICADE=m
CONFIG_HID_ITE=m
CONFIG_HID_JABRA=m
CONFIG_HID_TWINHAN=m
CONFIG_HID_KENSINGTON=m
CONFIG_HID_LCPOWER=m
CONFIG_HID_LED=m
CONFIG_HID_LENOVO=m
CONFIG_HID_LOGITECH=m
CONFIG_HID_LOGITECH_DJ=m
CONFIG_HID_LOGITECH_HIDPP=m
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
CONFIG_HID_MAGICMOUSE=m
CONFIG_HID_MALTRON=m
CONFIG_HID_MAYFLASH=m
CONFIG_HID_REDRAGON=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
CONFIG_HID_MULTITOUCH=m
CONFIG_HID_NTI=m
CONFIG_HID_NTRIG=m
CONFIG_HID_ORTEK=m
CONFIG_HID_PANTHERLORD=m
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PENMOUNT=m
CONFIG_HID_PETALYNX=m
CONFIG_HID_PICOLCD=m
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
CONFIG_HID_PICOLCD_LCD=y
CONFIG_HID_PICOLCD_LEDS=y
CONFIG_HID_PICOLCD_CIR=y
CONFIG_HID_PLANTRONICS=m
# CONFIG_HID_PLAYSTATION is not set
CONFIG_HID_PRIMAX=m
CONFIG_HID_RETRODE=m
CONFIG_HID_ROCCAT=m
CONFIG_HID_SAITEK=m
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SEMITEK=m
CONFIG_HID_SONY=m
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=m
CONFIG_HID_STEAM=m
CONFIG_HID_STEELSERIES=m
CONFIG_HID_SUNPLUS=m
CONFIG_HID_RMI=m
CONFIG_HID_GREENASIA=m
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=m
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TIVO=m
CONFIG_HID_TOPSEED=m
CONFIG_HID_THINGM=m
CONFIG_HID_THRUSTMASTER=m
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_UDRAW_PS3=m
CONFIG_HID_U2FZERO=m
CONFIG_HID_WACOM=m
CONFIG_HID_WIIMOTE=m
CONFIG_HID_XINMO=m
CONFIG_HID_ZEROPLUS=m
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=m
CONFIG_HID_SENSOR_HUB=m
CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
CONFIG_HID_ALPS=m
CONFIG_HID_MCP2221=m
# end of Special HID drivers

#
# USB HID support
#
CONFIG_USB_HID=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
# end of USB HID support

#
# I2C HID support
#
# CONFIG_I2C_HID_ACPI is not set
# CONFIG_I2C_HID_OF is not set
# CONFIG_I2C_HID_OF_GOODIX is not set
# end of I2C HID support
# end of HID support

CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_LED_TRIG=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_CONN_GPIO=m
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
CONFIG_USB_OTG_FSM=m
CONFIG_USB_LEDS_TRIGGER_USBPORT=m
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=y

#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=m
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=m
CONFIG_USB_XHCI_PCI_RENESAS=m
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_XHCI_SUNXI=m
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_EHCI_FSL=m
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OXU210HP_HCD=m
CONFIG_USB_ISP116X_HCD=m
CONFIG_USB_FOTG210_HCD=m
CONFIG_USB_MAX3421_HCD=m
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_OHCI_HCD_PCI=m
# CONFIG_USB_OHCI_HCD_SSB is not set
CONFIG_USB_OHCI_HCD_PLATFORM=m
CONFIG_USB_UHCI_HCD=m
CONFIG_USB_U132_HCD=m
CONFIG_USB_SL811_HCD=m
CONFIG_USB_SL811_HCD_ISO=y
# CONFIG_USB_SL811_CS is not set
CONFIG_USB_R8A66597_HCD=m
CONFIG_USB_HCD_BCMA=m
CONFIG_USB_HCD_SSB=m
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=y
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
CONFIG_USB_STORAGE_REALTEK=m
CONFIG_REALTEK_AUTOPM=y
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_FREECOM=m
CONFIG_USB_STORAGE_ISD200=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_STORAGE_ALAUDA=m
CONFIG_USB_STORAGE_ONETOUCH=m
CONFIG_USB_STORAGE_KARMA=m
CONFIG_USB_STORAGE_CYPRESS_ATACB=m
CONFIG_USB_STORAGE_ENE_UB6250=m
# CONFIG_USB_UAS is not set

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
CONFIG_USB_MICROTEK=m
CONFIG_USBIP_CORE=m
CONFIG_USBIP_VHCI_HCD=m
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=m
CONFIG_USBIP_VUDC=m
# CONFIG_USBIP_DEBUG is not set
# CONFIG_USB_CDNS_SUPPORT is not set
CONFIG_USB_MUSB_HDRC=y
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y

#
# Platform Glue Layer
#

#
# MUSB DMA mode
#
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_ULPI=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y

#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=y
# CONFIG_USB_DWC3_HAPS is not set
CONFIG_USB_DWC3_MESON_G12A=y
CONFIG_USB_DWC3_OF_SIMPLE=m
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
# CONFIG_USB_DWC2_PCI is not set
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
CONFIG_USB_CHIPIDEA=m
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_CHIPIDEA_MSM=m
CONFIG_USB_CHIPIDEA_IMX=m
CONFIG_USB_CHIPIDEA_GENERIC=m
CONFIG_USB_CHIPIDEA_TEGRA=m
CONFIG_USB_ISP1760=m
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_ISP1761_UDC=y
# CONFIG_USB_ISP1760_HOST_ROLE is not set
# CONFIG_USB_ISP1760_GADGET_ROLE is not set
CONFIG_USB_ISP1760_DUAL_ROLE=y

#
# USB port drivers
#
CONFIG_USB_SERIAL=m
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=m
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=m
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=m
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=m
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_F81232=m
CONFIG_USB_SERIAL_F8153X=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=m
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_METRO=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MXUPORT=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=m
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=m
CONFIG_USB_SERIAL_QUALCOMM=m
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
# CONFIG_USB_SERIAL_SAFE_PADDED is not set
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
CONFIG_USB_SERIAL_SYMBOL=m
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_WWAN=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=m
CONFIG_USB_SERIAL_XSENS_MT=m
CONFIG_USB_SERIAL_WISHBONE=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_SERIAL_QT2=m
CONFIG_USB_SERIAL_UPD78F0730=m
CONFIG_USB_SERIAL_XR=m
CONFIG_USB_SERIAL_DEBUG=m

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
CONFIG_USB_CYPRESS_CY7C63=m
CONFIG_USB_CYTHERM=m
CONFIG_USB_IDMOUSE=m
CONFIG_USB_FTDI_ELAN=m
CONFIG_USB_APPLEDISPLAY=m
# CONFIG_APPLE_MFI_FASTCHARGE is not set
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
CONFIG_USB_TEST=m
CONFIG_USB_EHSET_TEST_FIXTURE=m
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=m
CONFIG_USB_HUB_USB251XB=m
CONFIG_USB_HSIC_USB3503=m
CONFIG_USB_HSIC_USB4604=m
CONFIG_USB_LINK_LAYER_TEST=m
CONFIG_USB_CHAOSKEY=m

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
# CONFIG_NOP_USB_XCEIV is not set
CONFIG_USB_GPIO_VBUS=m
# CONFIG_USB_ISP1301 is not set
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set

#
# USB Peripheral Controller
#
CONFIG_USB_FOTG210_UDC=m
CONFIG_USB_GR_UDC=m
CONFIG_USB_R8A66597=m
CONFIG_USB_PXA27X=m
CONFIG_USB_MV_UDC=m
CONFIG_USB_MV_U3D=m
CONFIG_USB_SNP_CORE=m
CONFIG_USB_SNP_UDC_PLAT=m
CONFIG_USB_M66592=m
CONFIG_USB_BDC_UDC=m
CONFIG_USB_AMD5536UDC=m
CONFIG_USB_NET2272=m
CONFIG_USB_NET2272_DMA=y
CONFIG_USB_NET2280=m
CONFIG_USB_GOKU=m
CONFIG_USB_EG20T=m
CONFIG_USB_GADGET_XILINX=m
# CONFIG_USB_MAX3420_UDC is not set
CONFIG_USB_DUMMY_HCD=m
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=m
CONFIG_USB_F_ACM=m
CONFIG_USB_F_SS_LB=m
CONFIG_USB_U_SERIAL=m
CONFIG_USB_U_ETHER=m
CONFIG_USB_U_AUDIO=m
CONFIG_USB_F_SERIAL=m
CONFIG_USB_F_OBEX=m
CONFIG_USB_F_NCM=m
CONFIG_USB_F_ECM=m
CONFIG_USB_F_EEM=m
CONFIG_USB_F_SUBSET=m
CONFIG_USB_F_RNDIS=m
CONFIG_USB_F_MASS_STORAGE=m
CONFIG_USB_F_FS=m
CONFIG_USB_F_UAC1=m
CONFIG_USB_F_UAC1_LEGACY=m
CONFIG_USB_F_UAC2=m
CONFIG_USB_F_UVC=m
CONFIG_USB_F_MIDI=m
CONFIG_USB_F_HID=m
CONFIG_USB_F_PRINTER=m
CONFIG_USB_F_TCM=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_LB_SS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y
CONFIG_USB_CONFIGFS_F_TCM=y

#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=m
CONFIG_USB_ZERO_HNPTEST=y
CONFIG_USB_AUDIO=m
CONFIG_GADGET_UAC1=y
CONFIG_GADGET_UAC1_LEGACY=y
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
CONFIG_USB_FUNCTIONFS_ETH=y
CONFIG_USB_FUNCTIONFS_RNDIS=y
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_GADGET_TARGET=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_G_HID=m
CONFIG_USB_G_DBGP=m
# CONFIG_USB_G_DBGP_PRINTK is not set
CONFIG_USB_G_DBGP_SERIAL=y
CONFIG_USB_G_WEBCAM=m
CONFIG_USB_RAW_GADGET=m
# end of USB Gadget precomposed configurations

CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=m
CONFIG_TYPEC_TCPCI=m
CONFIG_TYPEC_RT1711H=m
# CONFIG_TYPEC_TCPCI_MAXIM is not set
CONFIG_TYPEC_FUSB302=m
CONFIG_TYPEC_UCSI=m
CONFIG_UCSI_CCG=m
# CONFIG_UCSI_ACPI is not set
CONFIG_TYPEC_TPS6598X=m
CONFIG_TYPEC_HD3SS3220=m
CONFIG_TYPEC_STUSB160X=m

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
CONFIG_TYPEC_MUX_PI3USB30532=m
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
CONFIG_TYPEC_DP_ALTMODE=m
CONFIG_TYPEC_NVIDIA_ALTMODE=m
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
# CONFIG_PWRSEQ_SD8787 is not set
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_ARMMMCI is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_PCI=m
CONFIG_MMC_RICOH_MMC=y
CONFIG_MMC_SDHCI_ACPI=m
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=m
CONFIG_MMC_SDHCI_OF_ASPEED=m
CONFIG_MMC_SDHCI_OF_AT91=m
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_MMC_SDHCI_CADENCE=m
CONFIG_MMC_SDHCI_F_SDH30=m
CONFIG_MMC_SDHCI_MILBEAUT=m
CONFIG_MMC_MESON_GX=y
# CONFIG_MMC_MESON_MX_SDIO is not set
# CONFIG_MMC_TIFM_SD is not set
CONFIG_MMC_SPI=m
# CONFIG_MMC_SDRICOH_CS is not set
# CONFIG_MMC_CB710 is not set
# CONFIG_MMC_VIA_SDMMC is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
# CONFIG_MMC_DW_BLUEFIELD is not set
# CONFIG_MMC_DW_EXYNOS is not set
# CONFIG_MMC_DW_HI3798CV200 is not set
# CONFIG_MMC_DW_K3 is not set
# CONFIG_MMC_DW_PCI is not set
CONFIG_MMC_DW_ROCKCHIP=y
# CONFIG_MMC_VUB300 is not set
CONFIG_MMC_USHC=m
# CONFIG_MMC_USDHI6ROL0 is not set
CONFIG_MMC_REALTEK_USB=m
CONFIG_MMC_SUNXI=y
CONFIG_MMC_CQHCI=m
CONFIG_MMC_HSQ=y
# CONFIG_MMC_TOSHIBA_PCI is not set
# CONFIG_MMC_MTK is not set
CONFIG_MMC_SDHCI_XENON=m
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
# CONFIG_LEDS_CLASS_FLASH is not set
# CONFIG_LEDS_CLASS_MULTICOLOR is not set
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set

#
# LED drivers
#
# CONFIG_LEDS_AN30259A is not set
# CONFIG_LEDS_AW2013 is not set
# CONFIG_LEDS_BCM6328 is not set
# CONFIG_LEDS_BCM6358 is not set
# CONFIG_LEDS_CR0014114 is not set
# CONFIG_LEDS_EL15203000 is not set
# CONFIG_LEDS_LM3530 is not set
# CONFIG_LEDS_LM3532 is not set
# CONFIG_LEDS_LM3642 is not set
# CONFIG_LEDS_LM3692X is not set
# CONFIG_LEDS_PCA9532 is not set
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP3952 is not set
# CONFIG_LEDS_LP50XX is not set
# CONFIG_LEDS_LP55XX_COMMON is not set
# CONFIG_LEDS_LP8860 is not set
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_PCA963X is not set
# CONFIG_LEDS_DAC124S085 is not set
CONFIG_LEDS_PWM=y
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_LT3593 is not set
CONFIG_LEDS_TCA6507=y
# CONFIG_LEDS_TLC591XX is not set
# CONFIG_LEDS_LM355x is not set
# CONFIG_LEDS_IS31FL319X is not set
# CONFIG_LEDS_IS31FL32XX is not set

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
# CONFIG_LEDS_BLINKM is not set
CONFIG_LEDS_SYSCON=y
# CONFIG_LEDS_MLXREG is not set
CONFIG_LEDS_USER=y
# CONFIG_LEDS_SPI_BYTE is not set
# CONFIG_LEDS_TI_LMU_COMMON is not set

#
# Flash and Torch LED drivers
#

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=m
# CONFIG_LEDS_TRIGGER_CPU is not set
CONFIG_LEDS_TRIGGER_ACTIVITY=m
CONFIG_LEDS_TRIGGER_GPIO=m
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=m
CONFIG_LEDS_TRIGGER_CAMERA=m
# CONFIG_LEDS_TRIGGER_PANIC is not set
CONFIG_LEDS_TRIGGER_NETDEV=m
CONFIG_LEDS_TRIGGER_PATTERN=m
CONFIG_LEDS_TRIGGER_AUDIO=m
CONFIG_LEDS_TRIGGER_TTY=m
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
# CONFIG_EDAC_DEBUG is not set
# CONFIG_EDAC_GHES is not set
# CONFIG_EDAC_THUNDERX is not set
# CONFIG_EDAC_XGENE is not set
CONFIG_EDAC_DMC520=m
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_ABB5ZES3 is not set
# CONFIG_RTC_DRV_ABEOZ9 is not set
# CONFIG_RTC_DRV_ABX80X is not set
CONFIG_RTC_DRV_AC100=y
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
CONFIG_RTC_DRV_HYM8563=m
# CONFIG_RTC_DRV_MAX6900 is not set
CONFIG_RTC_DRV_RK808=y
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_ISL12026 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8523 is not set
# CONFIG_RTC_DRV_PCF85063 is not set
# CONFIG_RTC_DRV_PCF85363 is not set
CONFIG_RTC_DRV_PCF8563=m
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8010 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV3028 is not set
# CONFIG_RTC_DRV_RV3032 is not set
# CONFIG_RTC_DRV_RV8803 is not set
# CONFIG_RTC_DRV_SD3078 is not set

#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_MCP795 is not set
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_PCF2127 is not set
# CONFIG_RTC_DRV_RV3029C2 is not set
# CONFIG_RTC_DRV_RX6110 is not set

#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1685_FAMILY is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_DS2404 is not set
CONFIG_RTC_DRV_EFI=y
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
# CONFIG_RTC_DRV_ZYNQMP is not set

#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_MESON_VRTC=y
CONFIG_RTC_DRV_PL030=m
CONFIG_RTC_DRV_PL031=m
CONFIG_RTC_DRV_SUN6I=y
# CONFIG_RTC_DRV_CADENCE is not set
# CONFIG_RTC_DRV_FTRTC010 is not set
# CONFIG_RTC_DRV_R7301 is not set

#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
# CONFIG_RTC_DRV_GOLDFISH is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
CONFIG_AMBA_PL08X=y
# CONFIG_BCM_SBA_RAID is not set
CONFIG_DMA_SUN6I=y
CONFIG_DW_AXI_DMAC=y
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_MV_XOR_V2 is not set
CONFIG_PL330_DMA=y
# CONFIG_PLX_DMA is not set
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
# CONFIG_XILINX_ZYNQMP_DPDMA is not set
# CONFIG_QCOM_HIDMA_MGMT is not set
# CONFIG_QCOM_HIDMA is not set
CONFIG_DW_DMAC_CORE=y
CONFIG_DW_DMAC=y
# CONFIG_DW_DMAC_PCI is not set
CONFIG_DW_EDMA=y
# CONFIG_DW_EDMA_PCIE is not set
# CONFIG_SF_PDMA is not set

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_DEBUG is not set
# CONFIG_DMABUF_SELFTESTS is not set
# CONFIG_DMABUF_HEAPS is not set
# CONFIG_DMABUF_SYSFS_STATS is not set
# end of DMABUF options

CONFIG_AUXDISPLAY=y
CONFIG_CHARLCD=m
CONFIG_HD44780_COMMON=m
CONFIG_HD44780=m
CONFIG_IMG_ASCII_LCD=m
CONFIG_HT16K33=m
CONFIG_LCD2S=m
CONFIG_TM1628=m
CONFIG_OPENVFD=m
# CONFIG_PANEL_CHANGE_MESSAGE is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
# CONFIG_UIO is not set
# CONFIG_VFIO is not set
CONFIG_VIRT_DRIVERS=y
CONFIG_VIRTIO=m
CONFIG_VIRTIO_PCI_LIB=m
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=m
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
# CONFIG_VDPA is not set
CONFIG_VHOST_IOTLB=m
CONFIG_VHOST=m
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_SCSI=m
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set

#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
# CONFIG_COMEDI is not set
CONFIG_STAGING=y
CONFIG_PRISM2_USB=m
CONFIG_RTL8192U=m
CONFIG_RTLLIB=m
CONFIG_RTLLIB_CRYPTO_CCMP=m
CONFIG_RTLLIB_CRYPTO_TKIP=m
CONFIG_RTLLIB_CRYPTO_WEP=m
# CONFIG_RTL8192E is not set
CONFIG_RTL8723BS=m
CONFIG_RTL8723CS=m
CONFIG_R8188EU=m
CONFIG_88EU_AP_MODE=y
# CONFIG_RTS5208 is not set
CONFIG_VT6655=m
CONFIG_VT6656=m

#
# IIO staging drivers
#

#
# Accelerometers
#
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16240 is not set
# end of Accelerometers

#
# Analog to digital converters
#
# CONFIG_AD7816 is not set
# CONFIG_AD7280 is not set
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
# CONFIG_ADT7316 is not set
# end of Analog digital bi-direction converters

#
# Capacitance to digital converters
#
# CONFIG_AD7746 is not set
# end of Capacitance to digital converters

#
# Direct Digital Synthesis
#
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
# CONFIG_AD5933 is not set
# end of Network Analyzer, Impedance Converters

#
# Active energy metering IC
#
# CONFIG_ADE7854 is not set
# end of Active energy metering IC

#
# Resolver to digital converters
#
# CONFIG_AD2S1210 is not set
# end of Resolver to digital converters
# end of IIO staging drivers

# CONFIG_FB_SM750 is not set
CONFIG_STAGING_MEDIA=y
# CONFIG_VIDEO_HANTRO is not set
CONFIG_VIDEO_MESON_VDEC=m
CONFIG_VIDEO_ROCKCHIP_VDEC=m
CONFIG_VIDEO_SUNXI=y
CONFIG_VIDEO_SUNXI_CEDRUS=m
# CONFIG_VIDEO_ZORAN is not set
CONFIG_DVB_AV7110_IR=y
CONFIG_DVB_AV7110=m
CONFIG_DVB_AV7110_OSD=y
CONFIG_DVB_SP8870=m

#
# Android
#
# CONFIG_ASHMEM is not set
# end of Android

# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
# CONFIG_GS_FPGABOOT is not set
# CONFIG_UNISYSSPAR is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
# CONFIG_FB_TFT is not set
CONFIG_FUSB_30X=m
# CONFIG_KS7010 is not set
CONFIG_PI433=m
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_QLGE is not set
# CONFIG_WFX is not set
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
CONFIG_SURFACE_PLATFORMS=y
# CONFIG_SURFACE_3_BUTTON is not set
# CONFIG_SURFACE_3_POWER_OPREGION is not set
# CONFIG_SURFACE_GPE is not set
# CONFIG_SURFACE_HOTPLUG is not set
# CONFIG_SURFACE_PRO3_BUTTON is not set
# CONFIG_SURFACE_AGGREGATOR is not set
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Clock driver for ARM Reference designs
#
# CONFIG_ICST is not set
# CONFIG_CLK_SP810 is not set
# CONFIG_CLK_VEXPRESS_OSC is not set
# end of Clock driver for ARM Reference designs

# CONFIG_LMK04832 is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
CONFIG_COMMON_CLK_CS2000_CP=y
# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
# CONFIG_COMMON_CLK_XGENE is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set

#
# Clock support for Amlogic platforms
#
CONFIG_COMMON_CLK_MESON_REGMAP=y
CONFIG_COMMON_CLK_MESON_DUALDIV=y
CONFIG_COMMON_CLK_MESON_MPLL=y
CONFIG_COMMON_CLK_MESON_PHASE=y
CONFIG_COMMON_CLK_MESON_PLL=y
CONFIG_COMMON_CLK_MESON_SCLK_DIV=y
CONFIG_COMMON_CLK_MESON_VID_PLL_DIV=y
CONFIG_COMMON_CLK_MESON_AO_CLKC=y
CONFIG_COMMON_CLK_MESON_EE_CLKC=y
CONFIG_COMMON_CLK_MESON_CPU_DYNDIV=y
CONFIG_COMMON_CLK_GXBB=y
CONFIG_COMMON_CLK_AXG=y
CONFIG_COMMON_CLK_AXG_AUDIO=y
CONFIG_COMMON_CLK_G12A=y
# end of Clock support for Amlogic platforms

CONFIG_COMMON_CLK_ROCKCHIP=y
CONFIG_CLK_PX30=y
CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
CONFIG_CLK_RK3399=y
CONFIG_CLK_RK3568=y
CONFIG_CLK_SUNXI=y
CONFIG_CLK_SUNXI_CLOCKS=y
CONFIG_CLK_SUNXI_PRCM_SUN6I=y
CONFIG_CLK_SUNXI_PRCM_SUN8I=y
CONFIG_CLK_SUNXI_PRCM_SUN9I=y
CONFIG_SUNXI_CCU=y
CONFIG_SUN50I_A64_CCU=y
CONFIG_SUN50I_A100_CCU=y
CONFIG_SUN50I_A100_R_CCU=y
CONFIG_SUN50I_H6_CCU=y
CONFIG_SUN50I_H616_CCU=y
CONFIG_SUN50I_H6_R_CCU=y
CONFIG_SUN8I_A83T_CCU=y
CONFIG_SUN8I_H3_CCU=y
CONFIG_SUN8I_DE2_CCU=y
CONFIG_SUN8I_R_CCU=y
# CONFIG_XILINX_VCU is not set
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_SUN6I=y

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_ACPI=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_SUN4I_TIMER=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
# CONFIG_ARM_TIMER_SP804 is not set
CONFIG_MICROCHIP_PIT64B=y
# end of Clock Source drivers

CONFIG_MAILBOX=y
CONFIG_ARM_MHU=y
CONFIG_ARM_MHU_V2=m
CONFIG_PLATFORM_MHU=y
CONFIG_PL320_MBOX=y
CONFIG_ROCKCHIP_MBOX=y
# CONFIG_PCC is not set
CONFIG_ALTERA_MBOX=m
# CONFIG_MAILBOX_TEST is not set
CONFIG_SUN6I_MSGBOX=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOASID=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
CONFIG_IOMMU_SVA_LIB=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_SUN50I_IOMMU=y
CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
CONFIG_ARM_SMMU_V3=y
CONFIG_ARM_SMMU_V3_SVA=y
CONFIG_VIRTIO_IOMMU=m

#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=m
CONFIG_RPMSG_CHAR=m
CONFIG_RPMSG_NS=m
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
CONFIG_RPMSG_VIRTIO=m
# end of Rpmsg drivers

# CONFIG_SOUNDWIRE is not set

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
CONFIG_MESON_CANVAS=y
CONFIG_MESON_CLK_MEASURE=y
CONFIG_MESON_GX_SOCINFO=y
CONFIG_MESON_GX_PM_DOMAINS=y
CONFIG_MESON_EE_PM_DOMAINS=y
CONFIG_MESON_SECURE_PM_DOMAINS=y
# end of Amlogic SoC drivers

#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
CONFIG_QUICC_ENGINE=y
# end of NXP/Freescale QorIQ SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Enable LiteX SoC Builder specific drivers
#
# CONFIG_LITEX_SOC_CONTROLLER is not set
# end of Enable LiteX SoC Builder specific drivers

#
# Qualcomm SoC drivers
#
CONFIG_QCOM_QMI_HELPERS=m
# end of Qualcomm SoC drivers

CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
# CONFIG_ROCKCHIP_SUSPEND_MODE is not set
CONFIG_SUNXI_MBUS=y
CONFIG_SUNXI_SRAM=y
# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers

CONFIG_VENDOR_FRIENDLYELEC=y
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=m
CONFIG_DEVFREQ_GOV_USERSPACE=m
CONFIG_DEVFREQ_GOV_PASSIVE=m

#
# DEVFREQ Drivers
#
CONFIG_ARM_RK3328_DMC_DEVFREQ=y
CONFIG_ARM_RK3399_DMC_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
# CONFIG_EXTCON_ADC_JACK is not set
# CONFIG_EXTCON_FSA9480 is not set
CONFIG_EXTCON_GPIO=m
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_PTN5150 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
CONFIG_EXTCON_USB_GPIO=m
# CONFIG_EXTCON_USBC_TUSB320 is not set
CONFIG_MEMORY=y
CONFIG_ARM_PL172_MPMC=m
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
# CONFIG_IIO_BUFFER_DMA is not set
# CONFIG_IIO_BUFFER_DMAENGINE is not set
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
# CONFIG_IIO_TRIGGERED_EVENT is not set

#
# Accelerometers
#
# CONFIG_ADIS16201 is not set
# CONFIG_ADIS16209 is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
# CONFIG_ADXL372_SPI is not set
# CONFIG_ADXL372_I2C is not set
# CONFIG_BMA180 is not set
# CONFIG_BMA220 is not set
# CONFIG_BMA400 is not set
# CONFIG_BMC150_ACCEL is not set
# CONFIG_BMI088_ACCEL is not set
# CONFIG_DA280 is not set
# CONFIG_DA311 is not set
# CONFIG_DMARD06 is not set
# CONFIG_DMARD09 is not set
# CONFIG_DMARD10 is not set
# CONFIG_FXLS8962AF_I2C is not set
# CONFIG_FXLS8962AF_SPI is not set
# CONFIG_HID_SENSOR_ACCEL_3D is not set
# CONFIG_IIO_ST_ACCEL_3AXIS is not set
# CONFIG_KXSD9 is not set
# CONFIG_KXCJK1013 is not set
# CONFIG_MC3230 is not set
# CONFIG_MMA7455_I2C is not set
# CONFIG_MMA7455_SPI is not set
# CONFIG_MMA7660 is not set
# CONFIG_MMA8452 is not set
# CONFIG_MMA9551 is not set
# CONFIG_MMA9553 is not set
# CONFIG_MXC4005 is not set
# CONFIG_MXC6255 is not set
# CONFIG_SCA3000 is not set
# CONFIG_SCA3300 is not set
# CONFIG_STK8312 is not set
# CONFIG_STK8BA50 is not set
# end of Accelerometers

#
# Analog to digital converters
#
# CONFIG_AD7091R5 is not set
# CONFIG_AD7124 is not set
# CONFIG_AD7192 is not set
# CONFIG_AD7266 is not set
# CONFIG_AD7291 is not set
# CONFIG_AD7292 is not set
# CONFIG_AD7298 is not set
# CONFIG_AD7476 is not set
# CONFIG_AD7606_IFACE_PARALLEL is not set
# CONFIG_AD7606_IFACE_SPI is not set
# CONFIG_AD7766 is not set
# CONFIG_AD7768_1 is not set
# CONFIG_AD7780 is not set
# CONFIG_AD7791 is not set
# CONFIG_AD7793 is not set
# CONFIG_AD7887 is not set
# CONFIG_AD7923 is not set
# CONFIG_AD7949 is not set
# CONFIG_AD799X is not set
# CONFIG_ADI_AXI_ADC is not set
CONFIG_AXP20X_ADC=y
CONFIG_AXP288_ADC=y
# CONFIG_CC10001_ADC is not set
# CONFIG_ENVELOPE_DETECTOR is not set
# CONFIG_HI8435 is not set
# CONFIG_HX711 is not set
# CONFIG_INA2XX_ADC is not set
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2496 is not set
# CONFIG_LTC2497 is not set
# CONFIG_MAX1027 is not set
# CONFIG_MAX11100 is not set
# CONFIG_MAX1118 is not set
# CONFIG_MAX1241 is not set
# CONFIG_MAX1363 is not set
# CONFIG_MAX9611 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
# CONFIG_MCP3911 is not set
CONFIG_MESON_SARADC=y
# CONFIG_NAU7802 is not set
# CONFIG_QCOM_SPMI_IADC is not set
# CONFIG_QCOM_SPMI_VADC is not set
# CONFIG_QCOM_SPMI_ADC5 is not set
CONFIG_ROCKCHIP_SARADC=y
# CONFIG_SD_ADC_MODULATOR is not set
# CONFIG_TI_ADC081C is not set
# CONFIG_TI_ADC0832 is not set
# CONFIG_TI_ADC084S021 is not set
# CONFIG_TI_ADC12138 is not set
# CONFIG_TI_ADC108S102 is not set
# CONFIG_TI_ADC128S052 is not set
# CONFIG_TI_ADC161S626 is not set
# CONFIG_TI_ADS1015 is not set
# CONFIG_TI_ADS7950 is not set
# CONFIG_TI_ADS8344 is not set
# CONFIG_TI_ADS8688 is not set
# CONFIG_TI_ADS124S08 is not set
# CONFIG_TI_ADS131E08 is not set
# CONFIG_TI_TLC4541 is not set
# CONFIG_TI_TSC2046 is not set
# CONFIG_VF610_ADC is not set
# CONFIG_XILINX_XADC is not set
# end of Analog to digital converters

#
# Analog to digital and digital to analog converters
#
# end of Analog to digital and digital to analog converters

#
# Analog Front Ends
#
# CONFIG_IIO_RESCALE is not set
# end of Analog Front Ends

#
# Amplifiers
#
# CONFIG_AD8366 is not set
# CONFIG_HMC425 is not set
# end of Amplifiers

#
# Capacitance to digital converters
#
# CONFIG_AD7150 is not set
# end of Capacitance to digital converters

#
# Chemical Sensors
#
# CONFIG_ATLAS_PH_SENSOR is not set
# CONFIG_ATLAS_EZO_SENSOR is not set
# CONFIG_BME680 is not set
# CONFIG_CCS811 is not set
# CONFIG_IAQCORE is not set
# CONFIG_PMS7003 is not set
# CONFIG_SCD30_CORE is not set
# CONFIG_SENSIRION_SGP30 is not set
# CONFIG_SENSIRION_SGP40 is not set
# CONFIG_SPS30_I2C is not set
# CONFIG_SPS30_SERIAL is not set
# CONFIG_VZ89X is not set
# end of Chemical Sensors

#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
# end of Hid Sensor IIO Common

#
# IIO SCMI Sensors
#
# CONFIG_IIO_SCMI is not set
# end of IIO SCMI Sensors

#
# SSP Sensor Common
#
# CONFIG_IIO_SSP_SENSORHUB is not set
# end of SSP Sensor Common

#
# Digital to analog converters
#
# CONFIG_AD5064 is not set
# CONFIG_AD5360 is not set
# CONFIG_AD5380 is not set
# CONFIG_AD5421 is not set
# CONFIG_AD5446 is not set
# CONFIG_AD5449 is not set
# CONFIG_AD5592R is not set
# CONFIG_AD5593R is not set
# CONFIG_AD5504 is not set
# CONFIG_AD5624R_SPI is not set
# CONFIG_AD5686_SPI is not set
# CONFIG_AD5696_I2C is not set
# CONFIG_AD5755 is not set
# CONFIG_AD5758 is not set
# CONFIG_AD5761 is not set
# CONFIG_AD5764 is not set
# CONFIG_AD5766 is not set
# CONFIG_AD5770R is not set
# CONFIG_AD5791 is not set
# CONFIG_AD7303 is not set
# CONFIG_AD8801 is not set
# CONFIG_DPOT_DAC is not set
# CONFIG_DS4424 is not set
# CONFIG_LTC1660 is not set
# CONFIG_LTC2632 is not set
# CONFIG_M62332 is not set
# CONFIG_MAX517 is not set
# CONFIG_MAX5821 is not set
# CONFIG_MCP4725 is not set
# CONFIG_MCP4922 is not set
# CONFIG_TI_DAC082S085 is not set
# CONFIG_TI_DAC5571 is not set
# CONFIG_TI_DAC7311 is not set
# CONFIG_TI_DAC7612 is not set
# CONFIG_VF610_DAC is not set
# end of Digital to analog converters

#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
# CONFIG_AD9523 is not set
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
# CONFIG_ADF4350 is not set
# CONFIG_ADF4371 is not set
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
# CONFIG_ADIS16080 is not set
# CONFIG_ADIS16130 is not set
# CONFIG_ADIS16136 is not set
# CONFIG_ADIS16260 is not set
# CONFIG_ADXRS290 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_BMG160 is not set
# CONFIG_FXAS21002C is not set
# CONFIG_HID_SENSOR_GYRO_3D is not set
# CONFIG_MPU3050_I2C is not set
# CONFIG_IIO_ST_GYRO_3AXIS is not set
# CONFIG_ITG3200 is not set
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
# CONFIG_MAX30100 is not set
# CONFIG_MAX30102 is not set
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
# CONFIG_AM2315 is not set
# CONFIG_DHT11 is not set
# CONFIG_HDC100X is not set
# CONFIG_HDC2010 is not set
# CONFIG_HID_SENSOR_HUMIDITY is not set
# CONFIG_HTS221 is not set
# CONFIG_HTU21 is not set
# CONFIG_SI7005 is not set
# CONFIG_SI7020 is not set
# end of Humidity sensors

#
# Inertial measurement units
#
# CONFIG_ADIS16400 is not set
# CONFIG_ADIS16460 is not set
# CONFIG_ADIS16475 is not set
# CONFIG_ADIS16480 is not set
# CONFIG_BMI160_I2C is not set
# CONFIG_BMI160_SPI is not set
# CONFIG_FXOS8700_I2C is not set
# CONFIG_FXOS8700_SPI is not set
# CONFIG_KMX61 is not set
# CONFIG_INV_ICM42600_I2C is not set
# CONFIG_INV_ICM42600_SPI is not set
# CONFIG_INV_MPU6050_I2C is not set
# CONFIG_INV_MPU6050_SPI is not set
# CONFIG_IIO_ST_LSM6DSX is not set
# CONFIG_IIO_ST_LSM9DS0 is not set
# end of Inertial measurement units

#
# Light sensors
#
# CONFIG_ACPI_ALS is not set
# CONFIG_ADJD_S311 is not set
# CONFIG_ADUX1020 is not set
# CONFIG_AL3010 is not set
# CONFIG_AL3320A is not set
# CONFIG_APDS9300 is not set
# CONFIG_APDS9960 is not set
# CONFIG_AS73211 is not set
# CONFIG_BH1750 is not set
# CONFIG_BH1780 is not set
# CONFIG_CM32181 is not set
# CONFIG_CM3232 is not set
# CONFIG_CM3323 is not set
# CONFIG_CM3605 is not set
# CONFIG_CM36651 is not set
# CONFIG_GP2AP002 is not set
# CONFIG_GP2AP020A00F is not set
# CONFIG_SENSORS_ISL29018 is not set
# CONFIG_SENSORS_ISL29028 is not set
# CONFIG_ISL29125 is not set
# CONFIG_HID_SENSOR_ALS is not set
# CONFIG_HID_SENSOR_PROX is not set
# CONFIG_JSA1212 is not set
# CONFIG_RPR0521 is not set
# CONFIG_LTR501 is not set
# CONFIG_LV0104CS is not set
# CONFIG_MAX44000 is not set
# CONFIG_MAX44009 is not set
# CONFIG_NOA1305 is not set
# CONFIG_OPT3001 is not set
# CONFIG_PA12203001 is not set
# CONFIG_SI1133 is not set
# CONFIG_SI1145 is not set
# CONFIG_STK3310 is not set
# CONFIG_ST_UVIS25 is not set
# CONFIG_TCS3414 is not set
# CONFIG_TCS3472 is not set
# CONFIG_SENSORS_TSL2563 is not set
# CONFIG_TSL2583 is not set
# CONFIG_TSL2591 is not set
# CONFIG_TSL2772 is not set
# CONFIG_TSL4531 is not set
# CONFIG_US5182D is not set
# CONFIG_VCNL4000 is not set
# CONFIG_VCNL4035 is not set
# CONFIG_VEML6030 is not set
# CONFIG_VEML6070 is not set
# CONFIG_VL6180 is not set
# CONFIG_ZOPT2201 is not set
# end of Light sensors

#
# Magnetometer sensors
#
# CONFIG_AK8974 is not set
# CONFIG_AK8975 is not set
# CONFIG_AK09911 is not set
# CONFIG_BMC150_MAGN_I2C is not set
# CONFIG_BMC150_MAGN_SPI is not set
# CONFIG_MAG3110 is not set
# CONFIG_HID_SENSOR_MAGNETOMETER_3D is not set
# CONFIG_MMC35240 is not set
# CONFIG_IIO_ST_MAGN_3AXIS is not set
# CONFIG_SENSORS_HMC5843_I2C is not set
# CONFIG_SENSORS_HMC5843_SPI is not set
# CONFIG_SENSORS_RM3100_I2C is not set
# CONFIG_SENSORS_RM3100_SPI is not set
# CONFIG_YAMAHA_YAS530 is not set
# end of Magnetometer sensors

#
# Multiplexers
#
# CONFIG_IIO_MUX is not set
# end of Multiplexers

#
# Inclinometer sensors
#
# CONFIG_HID_SENSOR_INCLINOMETER_3D is not set
# CONFIG_HID_SENSOR_DEVICE_ROTATION is not set
# end of Inclinometer sensors

#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=m
CONFIG_IIO_INTERRUPT_TRIGGER=m
CONFIG_IIO_TIGHTLOOP_TRIGGER=m
CONFIG_IIO_SYSFS_TRIGGER=y
# end of Triggers - standalone

#
# Linear and angular position sensors
#
# CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE is not set
# end of Linear and angular position sensors

#
# Digital potentiometers
#
# CONFIG_AD5110 is not set
# CONFIG_AD5272 is not set
# CONFIG_DS1803 is not set
# CONFIG_MAX5432 is not set
# CONFIG_MAX5481 is not set
# CONFIG_MAX5487 is not set
# CONFIG_MCP4018 is not set
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
# CONFIG_MCP41010 is not set
# CONFIG_TPL0102 is not set
# end of Digital potentiometers

#
# Digital potentiostats
#
# CONFIG_LMP91000 is not set
# end of Digital potentiostats

#
# Pressure sensors
#
# CONFIG_ABP060MG is not set
# CONFIG_BMP280 is not set
# CONFIG_DLHL60D is not set
# CONFIG_DPS310 is not set
# CONFIG_HID_SENSOR_PRESS is not set
# CONFIG_HP03 is not set
# CONFIG_ICP10100 is not set
# CONFIG_MPL115_I2C is not set
# CONFIG_MPL115_SPI is not set
# CONFIG_MPL3115 is not set
# CONFIG_MS5611 is not set
# CONFIG_MS5637 is not set
# CONFIG_IIO_ST_PRESS is not set
# CONFIG_T5403 is not set
# CONFIG_HP206C is not set
# CONFIG_ZPA2326 is not set
# end of Pressure sensors

#
# Lightning sensors
#
# CONFIG_AS3935 is not set
# end of Lightning sensors

#
# Proximity and distance sensors
#
# CONFIG_ISL29501 is not set
# CONFIG_LIDAR_LITE_V2 is not set
# CONFIG_MB1232 is not set
# CONFIG_PING is not set
# CONFIG_RFD77402 is not set
# CONFIG_SRF04 is not set
# CONFIG_SX9310 is not set
# CONFIG_SX9500 is not set
# CONFIG_SRF08 is not set
# CONFIG_VCNL3020 is not set
# CONFIG_VL53L0X_I2C is not set
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
# CONFIG_AD2S90 is not set
# CONFIG_AD2S1200 is not set
# end of Resolver to digital converters

#
# Temperature sensors
#
# CONFIG_LTC2983 is not set
# CONFIG_MAXIM_THERMOCOUPLE is not set
# CONFIG_HID_SENSOR_TEMP is not set
# CONFIG_MLX90614 is not set
# CONFIG_MLX90632 is not set
# CONFIG_TMP006 is not set
# CONFIG_TMP007 is not set
# CONFIG_TMP117 is not set
# CONFIG_TSYS01 is not set
# CONFIG_TSYS02D is not set
# CONFIG_MAX31856 is not set
# end of Temperature sensors

# CONFIG_NTB is not set
# CONFIG_VME_BUS is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_ATMEL_TCB is not set
# CONFIG_PWM_DWC is not set
# CONFIG_PWM_FSL_FTM is not set
# CONFIG_PWM_GPIO is not set
CONFIG_PWM_MESON=y
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_SUN4I=y

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_AL_FIC is not set
CONFIG_PARTITION_PERCPU=y
CONFIG_MESON_IRQ_GPIO=y
# end of IRQ chip support

# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_MESON=y
CONFIG_RESET_MESON_AUDIO_ARB=y
CONFIG_RESET_SCMI=y
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SUNXI=y
# CONFIG_RESET_TI_SYSCON is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_PHY_XGENE is not set
# CONFIG_PHY_CAN_TRANSCEIVER is not set
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_SUN6I_MIPI_DPHY=y
CONFIG_PHY_SUN9I_USB=y
CONFIG_PHY_SUN50I_USB3=y
CONFIG_PHY_MESON8B_USB2=y
CONFIG_PHY_MESON_GXL_USB2=y
CONFIG_PHY_MESON_G12A_USB2=y
CONFIG_PHY_MESON_G12A_USB3_PCIE=y
CONFIG_PHY_MESON_AXG_PCIE=y
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
CONFIG_PHY_MESON_AXG_MIPI_DPHY=y
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_FSL_IMX8MQ_USB is not set
# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
# CONFIG_PHY_QCOM_USB_HS is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
CONFIG_PHY_ROCKCHIP_DP=y
CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
CONFIG_PHY_ROCKCHIP_INNO_USB3=y
CONFIG_PHY_ROCKCHIP_PCIE=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PHY_ROCKCHIP_USB=y
# CONFIG_PHY_SAMSUNG_USB2 is not set
# CONFIG_PHY_TUSB1210 is not set
# end of PHY Subsystem

# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCI400_PMU=y
CONFIG_ARM_CCI5xx_PMU=y
CONFIG_ARM_CCN=m
CONFIG_ARM_CMN=m
CONFIG_ARM_PMU=y
CONFIG_ARM_PMU_ACPI=y
CONFIG_ARM_SMMU_V3_PMU=y
CONFIG_ARM_DSU_PMU=m
CONFIG_ARM_SPE_PMU=m
# CONFIG_ARM_DMC620_PMU is not set
# CONFIG_HISI_PMU is not set
# end of Performance monitor support

CONFIG_RAS=y
# CONFIG_USB4 is not set

#
# Android
#
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_BINDERFS=y
CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder,anbox-binder,anbox-hwbinder,anbox-vndbinder"
# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
# end of Android

# CONFIG_LIBNVDIMM is not set
CONFIG_DAX=y
CONFIG_DEV_DAX=m
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_MESON_EFUSE=y
# CONFIG_MESON_MX_EFUSE is not set
CONFIG_NVMEM_RMEM=y

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# end of HW tracing support

# CONFIG_FPGA is not set
# CONFIG_FSI is not set
CONFIG_TEE=y

#
# TEE drivers
#
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
# end of TEE drivers

CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
# CONFIG_MUX_ADGS1408 is not set
CONFIG_MUX_GPIO=m
CONFIG_MUX_MMIO=m
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set
# CONFIG_INTERCONNECT is not set
CONFIG_COUNTER=m
CONFIG_INTERRUPT_CNT=m
# CONFIG_FTM_QUADDEC is not set
# CONFIG_MICROCHIP_TCB_CAPTURE is not set
# CONFIG_INTEL_QEP is not set
# CONFIG_MOST is not set
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_IOMAP=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=m
# CONFIG_REISERFS_CHECK is not set
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
# CONFIG_JFS_DEBUG is not set
# CONFIG_JFS_STATISTICS is not set
CONFIG_XFS_FS=y
CONFIG_XFS_SUPPORT_V4=y
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
# CONFIG_XFS_RT is not set
# CONFIG_XFS_ONLINE_SCRUB is not set
# CONFIG_XFS_WARN is not set
# CONFIG_XFS_DEBUG is not set
CONFIG_GFS2_FS=m
CONFIG_GFS2_FS_LOCKING_DLM=y
CONFIG_OCFS2_FS=m
CONFIG_OCFS2_FS_O2CB=m
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
CONFIG_OCFS2_FS_STATS=y
CONFIG_OCFS2_DEBUG_MASKLOG=y
# CONFIG_OCFS2_DEBUG_FS is not set
CONFIG_BTRFS_FS=y
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
# CONFIG_BTRFS_FS_REF_VERIFY is not set
CONFIG_NILFS2_FS=m
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
# CONFIG_F2FS_FAULT_INJECTION is not set
CONFIG_F2FS_FS_COMPRESSION=y
CONFIG_F2FS_FS_LZO=y
CONFIG_F2FS_FS_LZORLE=y
CONFIG_F2FS_FS_LZ4=y
CONFIG_F2FS_FS_LZ4HC=y
CONFIG_F2FS_FS_ZSTD=y
CONFIG_F2FS_IOSTAT=y
CONFIG_FS_DAX=y
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
CONFIG_PRINT_QUOTA_WARNING=y
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
CONFIG_AUTOFS4_FS=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_VIRTIO_FS=m
CONFIG_OVERLAY_FS=y
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set

#
# Caches
#
CONFIG_NETFS_SUPPORT=y
# CONFIG_NETFS_STATS is not set
CONFIG_FSCACHE=y
# CONFIG_FSCACHE_STATS is not set
# CONFIG_FSCACHE_DEBUG is not set
CONFIG_CACHEFILES=m
# CONFIG_CACHEFILES_DEBUG is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_EXFAT_FS=y
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_NTFS_FS is not set
CONFIG_NTFS3_FS=m
# CONFIG_NTFS3_64BIT_CLUSTER is not set
CONFIG_NTFS3_LZX_XPRESS=y
# CONFIG_NTFS3_FS_POSIX_ACL is not set
# end of DOS/FAT/EXFAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_TMPFS_INODE64 is not set
CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_MEMFD_CREATE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=m
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
CONFIG_ECRYPT_FS=m
# CONFIG_ECRYPT_FS_MESSAGING is not set
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
CONFIG_UBIFS_FS=m
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
CONFIG_CRAMFS=m
CONFIG_CRAMFS_BLOCKDEV=y
# CONFIG_CRAMFS_MTD is not set
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_FILE_CACHE is not set
CONFIG_SQUASHFS_FILE_DIRECT=y
# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
# CONFIG_SQUASHFS_XATTR is not set
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_ZSTD=y
# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
CONFIG_PSTORE_DEFLATE_COMPRESS=y
CONFIG_PSTORE_LZO_COMPRESS=y
CONFIG_PSTORE_LZ4_COMPRESS=y
CONFIG_PSTORE_LZ4HC_COMPRESS=y
CONFIG_PSTORE_842_COMPRESS=y
CONFIG_PSTORE_ZSTD_COMPRESS=y
CONFIG_PSTORE_COMPRESS=y
CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set
CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
# CONFIG_PSTORE_CONSOLE is not set
# CONFIG_PSTORE_PMSG is not set
# CONFIG_PSTORE_RAM is not set
# CONFIG_PSTORE_BLK is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_EROFS_FS=m
# CONFIG_EROFS_FS_DEBUG is not set
CONFIG_EROFS_FS_XATTR=y
CONFIG_EROFS_FS_POSIX_ACL=y
# CONFIG_EROFS_FS_SECURITY is not set
CONFIG_EROFS_FS_ZIP=y
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V2=m
CONFIG_NFS_V3=m
# CONFIG_NFS_V3_ACL is not set
CONFIG_NFS_V4=m
# CONFIG_NFS_SWAP is not set
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=m
CONFIG_PNFS_BLOCK=m
CONFIG_PNFS_FLEXFILE_LAYOUT=m
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
# CONFIG_NFS_V4_1_MIGRATION is not set
CONFIG_NFS_V4_SECURITY_LABEL=y
CONFIG_NFS_FSCACHE=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DEBUG=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
# CONFIG_NFS_V4_2_READ_PLUS is not set
CONFIG_NFSD=m
# CONFIG_NFSD_V2 is not set
# CONFIG_NFSD_V3_ACL is not set
CONFIG_NFSD_V4=y
# CONFIG_NFSD_BLOCKLAYOUT is not set
# CONFIG_NFSD_SCSILAYOUT is not set
# CONFIG_NFSD_FLEXFILELAYOUT is not set
CONFIG_NFSD_V4_2_INTER_SSC=y
# CONFIG_NFSD_V4_SECURITY_LABEL is not set
CONFIG_GRACE_PERIOD=m
CONFIG_LOCKD=m
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_NFS_V4_2_SSC_HELPER=y
CONFIG_SUNRPC=m
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_BACKCHANNEL=y
CONFIG_RPCSEC_GSS_KRB5=m
# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
CONFIG_SUNRPC_DEBUG=y
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
# CONFIG_CEPH_FS_SECURITY_LABEL is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CIFS_DEBUG=y
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
CONFIG_CIFS_DFS_UPCALL=y
# CONFIG_CIFS_SWN_UPCALL is not set
# CONFIG_CIFS_FSCACHE is not set
CONFIG_SMB_SERVER=m
CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
CONFIG_SMB_SERVER_KERBEROS5=y
CONFIG_SMBFS_COMMON=m
CONFIG_CODA_FS=m
CONFIG_AFS_FS=m
# CONFIG_AFS_DEBUG is not set
CONFIG_AFS_FSCACHE=y
# CONFIG_AFS_DEBUG_CURSOR is not set
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
CONFIG_9P_FS_SECURITY=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf-8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=m
CONFIG_NLS_MAC_GAELIC=m
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=y
CONFIG_DLM=m
# CONFIG_DLM_DEBUG is not set
# CONFIG_UNICODE is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_PROC_MEM_ALWAYS_FORCE=y
# CONFIG_PROC_MEM_FORCE_PTRACE is not set
# CONFIG_PROC_MEM_NO_FORCE is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
# CONFIG_SECURITY_NETWORK_XFRM is not set
CONFIG_SECURITY_PATH=y
CONFIG_LSM_MMAP_MIN_ADDR=32768
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
# CONFIG_SECURITY_SELINUX_DISABLE is not set
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
CONFIG_SECURITY_APPARMOR=y
CONFIG_SECURITY_APPARMOR_HASH=y
CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
# CONFIG_SECURITY_APPARMOR_DEBUG is not set
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
# CONFIG_SECURITY_LANDLOCK is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
CONFIG_INTEGRITY_AUDIT=y
# CONFIG_IMA is not set
# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
# CONFIG_EVM is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
CONFIG_INIT_STACK_NONE=y
# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
# CONFIG_INIT_STACK_ALL_PATTERN is not set
# CONFIG_INIT_STACK_ALL_ZERO is not set
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
# CONFIG_ZERO_CALL_USED_REGS is not set
# end of Memory initialization
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=y
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=y
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_ENGINE=y

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
# CONFIG_CRYPTO_ECDSA is not set
CONFIG_CRYPTO_ECRDSA=y
CONFIG_CRYPTO_SM2=y
CONFIG_CRYPTO_CURVE25519=y

#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_AEGIS128=y
CONFIG_CRYPTO_AEGIS128_SIMD=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=y

#
# Block modes
#
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_KEYWRAP=y
CONFIG_CRYPTO_NHPOLY1305=y
CONFIG_CRYPTO_ADIANTUM=y
CONFIG_CRYPTO_ESSIV=y

#
# Hash modes
#
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_VMAC=y

#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_XXHASH=y
CONFIG_CRYPTO_BLAKE2B=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_RMD160=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_STREEBOG=y
CONFIG_CRYPTO_WP512=y

#
# Ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
CONFIG_CRYPTO_ANUBIS=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_BLOWFISH_COMMON=y
CONFIG_CRYPTO_CAMELLIA=y
CONFIG_CRYPTO_CAST_COMMON=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=y
CONFIG_CRYPTO_KHAZAD=y
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_SEED=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=y
CONFIG_CRYPTO_ZSTD=y

#
# Random Number Generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
CONFIG_CRYPTO_STATS=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_ALLWINNER=y
CONFIG_CRYPTO_DEV_SUN4I_SS=y
CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set
CONFIG_CRYPTO_DEV_SUN8I_CE=y
CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG=y
CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
CONFIG_CRYPTO_DEV_SUN8I_SS=y
CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG=y
CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_CCP is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_ROCKCHIP=y
CONFIG_CRYPTO_DEV_VIRTIO=m
CONFIG_CRYPTO_DEV_CRYPTODEV_LINUX=m
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
CONFIG_CRYPTO_DEV_CCREE=y
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
# CONFIG_CRYPTO_DEV_HISI_TRNG is not set
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG=y
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
CONFIG_PKCS7_MESSAGE_PARSER=y
CONFIG_PKCS7_TEST_KEY=m
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_RAID6_PQ=y
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_CORDIC=m
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
CONFIG_INDIRECT_PIO=y

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=m
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
CONFIG_CRYPTO_LIB_CURVE25519=m
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=m
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LIB_SM4=y
# end of Crypto library routines

CONFIG_LIB_MEMNEQ=y
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=m
CONFIG_CRC4=m
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=m
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
CONFIG_RANDOM32_SELFTEST=y
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
# CONFIG_XZ_DEC_SPARC is not set
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_INTERVAL_TREE=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_SWIOTLB=y
# CONFIG_DMA_RESTRICTED_POOL is not set
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y
# CONFIG_DMA_PERNUMA_CMA is not set

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=256
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_DMA_MAP_BENCHMARK is not set
CONFIG_SGL_ALLOC=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_ARCH_STACKWALK=y
CONFIG_SBITMAP=y
# end of Library routines

CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_CALLER is not set
# CONFIG_STACKTRACE_BUILD_ID is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

CONFIG_AS_HAS_NON_CONST_LEB128=y

#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_INFO_REDUCED is not set
CONFIG_DEBUG_INFO_COMPRESSED=y
# CONFIG_DEBUG_INFO_SPLIT is not set
# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
CONFIG_DEBUG_INFO_DWARF4=y
# CONFIG_DEBUG_INFO_DWARF5 is not set
CONFIG_DEBUG_INFO_BTF=y
CONFIG_PAHOLE_HAS_SPLIT_BTF=y
CONFIG_DEBUG_INFO_BTF_MODULES=y
# CONFIG_GDB_SCRIPTS is not set
CONFIG_FRAME_WARN=2048
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_READABLE_ASM is not set
CONFIG_HEADERS_INSTALL=y
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_VMLINUX_MAP is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_KCSAN_COMPILER=y
# end of Generic Kernel Debugging Instruments

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
# end of Memory Debugging

# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SOFTLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHED_INFO=y
# CONFIG_SCHEDSTATS is not set
# end of Scheduler Debugging

# CONFIG_DEBUG_TIMEKEEPING is not set
CONFIG_DEBUG_PREEMPT=y

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

# CONFIG_DEBUG_IRQFLAGS is not set
CONFIG_STACKTRACE=y
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set

#
# Debug kernel data structures
#
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# end of Debug kernel data structures

# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
# CONFIG_RCU_SCALE_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_LATENCYTOP is not set
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_TRACING=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_BOOTTIME_TRACING is not set
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_PREEMPT_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_HWLAT_TRACER is not set
# CONFIG_OSNOISE_TRACER is not set
# CONFIG_TIMERLAT_TRACER is not set
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
# CONFIG_FTRACE_SYSCALLS is not set
# CONFIG_TRACER_SNAPSHOT is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_KPROBE_EVENTS=y
CONFIG_UPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_DYNAMIC_EVENTS=y
CONFIG_PROBE_EVENTS=y
# CONFIG_SYNTH_EVENTS is not set
# CONFIG_HIST_TRIGGERS is not set
# CONFIG_TRACE_EVENT_INJECT is not set
# CONFIG_TRACEPOINT_BENCHMARK is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_TRACE_EVAL_MAP_FILE is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
# CONFIG_KPROBE_EVENT_GEN_TEST is not set
# CONFIG_SAMPLES is not set
# CONFIG_STRICT_DEVMEM is not set

#
# arm64 Debugging
#
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_DEBUG_EFI is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
# end of arm64 Debugging

#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FUNCTION_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_LKDTM is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_DIV64 is not set
# CONFIG_KPROBES_SANITY_TEST is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_ASYNC_RAID6_TEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_STRING_SELFTEST is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_STRSCPY is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_SCANF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_OVERFLOW is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_HASH is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_VMALLOC is not set
# CONFIG_TEST_USER_COPY is not set
CONFIG_TEST_BPF=m
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_STACKINIT is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_FREE_PAGES is not set
CONFIG_ARCH_USE_MEMTEST=y
CONFIG_MEMTEST=y
# end of Kernel Testing and Coverage
# end of Kernel hacking


================================================
FILE: kernel-config/release/stable/config-5.4
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 5.4.302 Kernel Configuration
#

#
# Compiler: aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 14.3.Rel1 (Build arm-14.174)) 14.3.1 20250623
#
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=140301
CONFIG_CLANG_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_HAS_ASM_GOTO=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_EXTABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_UAPI_HEADER_TEST is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_USELIB is not set
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem

CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_HZ_PERIODIC=y
# CONFIG_NO_HZ_IDLE is not set
# CONFIG_NO_HZ_FULL is not set
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_PREEMPTION=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_PREEMPT_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
# CONFIG_UCLAMP_TASK is not set
# end of Scheduler features

CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
CONFIG_MEMCG=y
CONFIG_MEMCG_SWAP=y
CONFIG_MEMCG_SWAP_ENABLED=y
CONFIG_MEMCG_KMEM=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
# CONFIG_CHECKPOINT_RESTORE is not set
CONFIG_SCHED_AUTOGROUP=y
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_BPF=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
CONFIG_SYSFS_SYSCALL=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_PRINTK_NMI=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_BPF_SYSCALL=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
# CONFIG_USERFAULTFD is not set
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
CONFIG_SLUB_MEMCG_SYSFS_ON=y
# CONFIG_COMPAT_BRK is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
CONFIG_SLAB_FREELIST_RANDOM=y
CONFIG_SLAB_FREELIST_HARDENED=y
CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
CONFIG_SLUB_CPU_PARTIAL=y
CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
# end of General setup

CONFIG_ARM64=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_CONT_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y

#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
# CONFIG_ARCH_AGILEX is not set
CONFIG_ARCH_SUNXI=y
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_BCM2835 is not set
# CONFIG_ARCH_BCM_IPROC is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
# CONFIG_ARCH_BRCMSTB is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LAYERSCAPE is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_MEDIATEK is not set
CONFIG_ARCH_MESON=y
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_RENESAS is not set
CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_STRATIX10 is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZX is not set
# CONFIG_ARCH_ZYNQMP is not set
# end of Platform selection

#
# Kernel Features
#

#
# ARM errata workarounds via the alternatives framework
#
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_834220=y
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1742098=y
CONFIG_ARM64_ERRATUM_3194386=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_QCOM_FALKOR_ERRATUM_1009=y
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_FUJITSU_ERRATUM_010001=y
# end of ARM errata workarounds via the alternatives framework

CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
CONFIG_ARM64_VA_BITS_39=y
# CONFIG_ARM64_VA_BITS_48 is not set
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_SCHED_MC=y
# CONFIG_SCHED_SMT is not set
CONFIG_NR_CPUS=8
# CONFIG_HOTPLUG_CPU is not set
# CONFIG_NUMA is not set
CONFIG_HOLES_IN_ZONE=y
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
CONFIG_HZ_300=y
# CONFIG_HZ_1000 is not set
CONFIG_HZ=300
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_SECCOMP=y
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_KEXEC_FILE is not set
# CONFIG_CRASH_DUMP is not set
# CONFIG_XEN is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDEN_EL2_VECTORS=y
CONFIG_ARM64_SSBD=y
CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y

#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
# CONFIG_ARM64_LSE_ATOMICS is not set
CONFIG_ARM64_VHE=y
# end of ARMv8.1 architectural features

#
# ARMv8.2 architectural features
#
CONFIG_ARM64_UAO=y
# CONFIG_ARM64_PMEM is not set
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features

#
# ARMv8.3 architectural features
#
CONFIG_ARM64_PTR_AUTH=y
# end of ARMv8.3 architectural features

CONFIG_ARM64_SVE=y
CONFIG_ARM64_MODULE_PLTS=y
CONFIG_ARM64_PSEUDO_NMI=y
# CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
# end of Kernel Features

#
# Boot options
#
CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
CONFIG_CMDLINE=""
# CONFIG_CMDLINE_FORCE is not set
CONFIG_EFI_STUB=y
CONFIG_EFI=y
CONFIG_DMI=y
# end of Boot options

CONFIG_SYSVIPC_COMPAT=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y

#
# Power management options
#
# CONFIG_SUSPEND is not set
# CONFIG_HIBERNATION is not set
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options

#
# CPU Power Management
#

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_IDLE_GOV_LADDER=y
# CONFIG_CPU_IDLE_GOV_MENU is not set
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_DT_IDLE_STATES=y

#
# ARM CPU Idle Drivers
#
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE=y
# end of ARM CPU Idle Drivers
# end of CPU Idle

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_STAT is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_USERSPACE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
# CONFIG_ACPI_CPPC_CPUFREQ is not set
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_SCMI_CPUFREQ=y
# CONFIG_QORIQ_CPUFREQ is not set
# end of CPU Frequency scaling
# end of CPU Power Management

#
# Firmware Drivers
#
CONFIG_ARM_SCMI_PROTOCOL=y
CONFIG_ARM_SCMI_POWER_DOMAIN=y
CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
CONFIG_ARM_SDE_INTERFACE=y
CONFIG_FIRMWARE_MEMMAP=y
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=y
# CONFIG_ISCSI_IBFT is not set
CONFIG_FW_CFG_SYSFS=m
CONFIG_FW_CFG_SYSFS_CMDLINE=y
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_ARM_PSCI_FW=y
# CONFIG_GOOGLE_FIRMWARE is not set

#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_VARS=m
CONFIG_EFI_ESRT=y
CONFIG_EFI_VARS_PSTORE=m
# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_ARMSTUB=y
CONFIG_EFI_ARMSTUB_DTB_LOADER=y
CONFIG_EFI_BOOTLOADER_CONTROL=m
CONFIG_EFI_CAPSULE_LOADER=m
CONFIG_EFI_TEST=m
# CONFIG_RESET_ATTACK_MITIGATION is not set
# end of EFI (Extensible Firmware Interface) Support

CONFIG_UEFI_CPER=y
CONFIG_UEFI_CPER_ARM=y
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
CONFIG_MESON_SM=y

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_GENERIC_GSI=y
CONFIG_ACPI_CCA_REQUIRED=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
# CONFIG_ACPI_EC_DEBUGFS is not set
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_MCFG=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_THERMAL=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_PCI_SLOT=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_CUSTOM_METHOD=y
CONFIG_ACPI_BGRT=y
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
CONFIG_HAVE_ACPI_APEI=y
CONFIG_ACPI_APEI=y
CONFIG_ACPI_APEI_GHES=y
CONFIG_ACPI_APEI_SEA=y
CONFIG_ACPI_APEI_MEMORY_FAILURE=y
CONFIG_ACPI_APEI_EINJ=m
CONFIG_ACPI_APEI_ERST_DEBUG=m
CONFIG_PMIC_OPREGION=y
CONFIG_ACPI_CONFIGFS=m
CONFIG_ACPI_IORT=y
CONFIG_ACPI_GTDT=y
CONFIG_ACPI_PPTT=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_MMIO=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
CONFIG_KVM_ARM_HOST=y
CONFIG_KVM_ARM_PMU=y
CONFIG_KVM_INDIRECT_VECTORS=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_SCSI=m
CONFIG_VHOST_VSOCK=m
CONFIG_VHOST=m
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
CONFIG_ARM64_CRYPTO=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64_CE=y
CONFIG_CRYPTO_SHA3_ARM64=y
CONFIG_CRYPTO_SM3_ARM64_CE=y
CONFIG_CRYPTO_SM4_ARM64_CE=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_CHACHA20_NEON=y
CONFIG_CRYPTO_NHPOLY1305_NEON=y
CONFIG_CRYPTO_AES_ARM64_BS=y

#
# General architecture-dependent options
#
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_HAVE_RCU_TABLE_FREE=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_CC_HAS_STACKPROTECTOR_NONE=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_HAVE_COPY_THREAD_TLS=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_64BIT_TIME=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_PLUGIN_HOSTCC=""
CONFIG_HAVE_GCC_PLUGINS=y
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BLK_DEV_BSG=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
# CONFIG_BLK_DEV_ZONED is not set
CONFIG_BLK_DEV_THROTTLING=y
# CONFIG_BLK_DEV_THROTTLING_LOW is not set
CONFIG_BLK_CMDLINE_PARSER=y
CONFIG_BLK_WBT=y
# CONFIG_BLK_CGROUP_IOLATENCY is not set
# CONFIG_BLK_CGROUP_IOCOST is not set
CONFIG_BLK_WBT_MQ=y
# CONFIG_BLK_DEBUG_FS is not set
# CONFIG_BLK_SED_OPAL is not set

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_AIX_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
CONFIG_CMDLINE_PARTITION=y
# end of Partition Types

CONFIG_BLOCK_COMPAT=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
# CONFIG_BFQ_CGROUP_DEBUG is not set
# end of IO Schedulers

CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ELFCORE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=m
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_SELECT_MEMORY_MODEL=y
# CONFIG_FLATMEM_MANUAL is not set
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM=y
CONFIG_HAVE_MEMORY_PRESENT=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_MMU_NOTIFIER=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
CONFIG_MEMORY_FAILURE=y
# CONFIG_HWPOISON_INJECT is not set
CONFIG_TRANSPARENT_HUGEPAGE=y
# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set
CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
CONFIG_TRANSPARENT_HUGE_PAGECACHE=y
CONFIG_CLEANCACHE=y
CONFIG_FRONTSWAP=y
CONFIG_CMA=y
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
CONFIG_CMA_AREAS=7
CONFIG_ZSWAP=y
CONFIG_ZPOOL=y
CONFIG_ZBUD=y
CONFIG_Z3FOLD=y
CONFIG_ZSMALLOC=y
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_FRAME_VECTOR=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_BENCHMARK is not set
# CONFIG_READ_ONLY_THP_FOR_FS is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
# end of Memory Management options

CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_EXTENSIONS=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_UNIX_SCM=y
CONFIG_UNIX_DIAG=y
CONFIG_TLS=m
# CONFIG_TLS_DEVICE is not set
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
CONFIG_XFRM_INTERFACE=m
CONFIG_XFRM_SUB_POLICY=y
CONFIG_XFRM_MIGRATE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_XFRM_IPCOMP=y
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=y
CONFIG_INET=y
CONFIG_WIREGUARD=m
# CONFIG_WIREGUARD_DEBUG is not set
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_FIB_TRIE_STATS=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_ROUTE_CLASSID=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=y
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=y
CONFIG_NET_FOU=y
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
CONFIG_INET_ESP_OFFLOAD=m
CONFIG_INET_IPCOMP=y
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=y
CONFIG_INET_TUNNEL=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
CONFIG_INET_UDP_DIAG=y
CONFIG_INET_RAW_DIAG=y
CONFIG_INET_DIAG_DESTROY=y
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_NV=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_CONG_DCTCP=m
CONFIG_TCP_CONG_CDG=m
CONFIG_TCP_CONG_BBR=m
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_TCP_MD5SIG=y
CONFIG_IPV6=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_ESP_OFFLOAD=m
CONFIG_INET6_IPCOMP=y
CONFIG_IPV6_MIP6=m
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=y
CONFIG_INET6_TUNNEL=y
CONFIG_IPV6_VTI=m
CONFIG_IPV6_SIT=y
# CONFIG_IPV6_SIT_6RD is not set
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=y
CONFIG_IPV6_GRE=m
CONFIG_IPV6_FOU=y
CONFIG_IPV6_FOU_TUNNEL=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
CONFIG_IPV6_SEG6_LWTUNNEL=y
CONFIG_IPV6_SEG6_HMAC=y
CONFIG_IPV6_SEG6_BPF=y
# CONFIG_NETLABEL is not set
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NETWORK_PHY_TIMESTAMPING=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_NETLINK=m
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
# CONFIG_NETFILTER_NETLINK_ACCT is not set
# CONFIG_NETFILTER_NETLINK_QUEUE is not set
# CONFIG_NETFILTER_NETLINK_LOG is not set
# CONFIG_NETFILTER_NETLINK_OSF is not set
CONFIG_NF_CONNTRACK=y
CONFIG_NF_LOG_COMMON=m
CONFIG_NF_LOG_NETDEV=m
CONFIG_NETFILTER_CONNCOUNT=m
CONFIG_NF_CONNTRACK_MARK=y
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_ZONES=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y
# CONFIG_NF_CONNTRACK_TIMEOUT is not set
# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_NAT=m
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=m
CONFIG_NF_TABLES_SET=m
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_COUNTER=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_OBJREF=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
# CONFIG_NFT_OSF is not set
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NF_DUP_NETDEV=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
CONFIG_NF_FLOW_TABLE_HW=m
CONFIG_NETFILTER_XTABLES=m

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=m
CONFIG_NETFILTER_XT_CONNMARK=m
CONFIG_NETFILTER_XT_SET=m

#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_AUDIT=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LED=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=m
CONFIG_NETFILTER_XT_TARGET_NETMAP=m
CONFIG_NETFILTER_XT_TARGET_FULLCONENAT=m
# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD=m
CONFIG_NETFILTER_XT_TARGET_RATEEST=m
CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
CONFIG_NETFILTER_XT_TARGET_SECMARK=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=m
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set
# CONFIG_NETFILTER_XT_MATCH_OSF is not set
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# end of Core Netfilter Configuration

CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
# CONFIG_IP_VS_DEBUG is not set
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_SOCKET_IPV4=m
CONFIG_NF_TPROXY_IPV4=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=m
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_FULLCONENAT=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
# CONFIG_IP_NF_SECURITY is not set
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
# CONFIG_IP6_NF_SECURITY is not set
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=y
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_NFT_BRIDGE_META=m
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NF_LOG_BRIDGE=m
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
# CONFIG_BPFILTER is not set
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m

#
# DCCP CCIDs Configuration
#
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
CONFIG_IP_DCCP_CCID3=y
# CONFIG_IP_DCCP_CCID3_DEBUG is not set
CONFIG_IP_DCCP_TFRC_LIB=y
# end of DCCP CCIDs Configuration

#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
# end of DCCP Kernel Hacking

CONFIG_IP_SCTP=m
CONFIG_SCTP_DBG_OBJCNT=y
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=m
CONFIG_RDS=m
CONFIG_RDS_TCP=m
# CONFIG_RDS_DEBUG is not set
CONFIG_TIPC=m
CONFIG_TIPC_MEDIA_UDP=y
CONFIG_TIPC_DIAG=m
# CONFIG_ATM is not set
CONFIG_L2TP=m
CONFIG_L2TP_DEBUGFS=m
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=m
CONFIG_L2TP_ETH=m
CONFIG_STP=m
CONFIG_BRIDGE=m
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_HAVE_NET_DSA=y
CONFIG_NET_DSA=m
CONFIG_NET_DSA_TAG_8021Q=m
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
CONFIG_NET_DSA_TAG_BRCM=m
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
CONFIG_NET_DSA_TAG_GSWIP=m
CONFIG_NET_DSA_TAG_DSA=m
CONFIG_NET_DSA_TAG_EDSA=m
CONFIG_NET_DSA_TAG_MTK=m
CONFIG_NET_DSA_TAG_KSZ=m
CONFIG_NET_DSA_TAG_QCA=m
CONFIG_NET_DSA_TAG_LAN9303=m
CONFIG_NET_DSA_TAG_SJA1105=m
CONFIG_NET_DSA_TAG_TRAILER=m
CONFIG_VLAN_8021Q=y
# CONFIG_VLAN_8021Q_GVRP is not set
# CONFIG_VLAN_8021Q_MVRP is not set
CONFIG_LLC=m
CONFIG_LLC2=m
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
# CONFIG_X25 is not set
CONFIG_LAPB=m
CONFIG_PHONET=m
CONFIG_6LOWPAN=m
# CONFIG_6LOWPAN_DEBUGFS is not set
CONFIG_6LOWPAN_NHC=m
CONFIG_6LOWPAN_NHC_DEST=m
CONFIG_6LOWPAN_NHC_FRAGMENT=m
CONFIG_6LOWPAN_NHC_HOP=m
CONFIG_6LOWPAN_NHC_IPV6=m
CONFIG_6LOWPAN_NHC_MOBILITY=m
CONFIG_6LOWPAN_NHC_ROUTING=m
CONFIG_6LOWPAN_NHC_UDP=m
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
CONFIG_6LOWPAN_GHC_UDP=m
CONFIG_6LOWPAN_GHC_ICMPV6=m
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
CONFIG_IEEE802154=m
CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_MAC802154=m
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFB=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_SKBPRIO=m
CONFIG_NET_SCH_CHOKE=m
CONFIG_NET_SCH_QFQ=m
CONFIG_NET_SCH_CODEL=m
CONFIG_NET_SCH_FQ_CODEL=y
CONFIG_NET_SCH_CAKE=m
CONFIG_NET_SCH_FQ=m
CONFIG_NET_SCH_HHF=m
CONFIG_NET_SCH_PIE=m
CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_SCH_PLUG=m
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_PERF=y
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=y
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
# CONFIG_NET_EMATCH_CANID is not set
CONFIG_NET_EMATCH_IPSET=m
CONFIG_NET_EMATCH_IPT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_SAMPLE=m
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
CONFIG_NET_ACT_MPLS=m
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_NET_ACT_CONNMARK=m
CONFIG_NET_ACT_CTINFO=m
CONFIG_NET_ACT_SKBMOD=m
CONFIG_NET_ACT_IFE=m
CONFIG_NET_ACT_TUNNEL_KEY=m
CONFIG_NET_ACT_CT=m
CONFIG_NET_IFE_SKBMARK=m
CONFIG_NET_IFE_SKBPRIO=m
CONFIG_NET_IFE_SKBTCINDEX=m
# CONFIG_NET_TC_SKB_EXT is not set
CONFIG_NET_SCH_FIFO=y
CONFIG_DCB=y
CONFIG_DNS_RESOLVER=y
CONFIG_BATMAN_ADV=m
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
CONFIG_BATMAN_ADV_NC=y
CONFIG_BATMAN_ADV_MCAST=y
CONFIG_BATMAN_ADV_DEBUGFS=y
# CONFIG_BATMAN_ADV_DEBUG is not set
CONFIG_BATMAN_ADV_SYSFS=y
CONFIG_OPENVSWITCH=m
CONFIG_OPENVSWITCH_GRE=m
CONFIG_OPENVSWITCH_VXLAN=m
CONFIG_OPENVSWITCH_GENEVE=m
CONFIG_VSOCKETS=m
CONFIG_VSOCKETS_DIAG=m
CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO_VSOCKETS_COMMON=m
CONFIG_NETLINK_DIAG=y
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=m
CONFIG_MPLS_ROUTING=m
CONFIG_MPLS_IPTUNNEL=m
CONFIG_NET_NSH=m
CONFIG_HSR=m
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
# CONFIG_NET_NCSI is not set
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_XPS=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_JIT=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
CONFIG_NET_PKTGEN=m
# end of Network testing
# end of Networking options

CONFIG_HAMRADIO=y

#
# Packet Radio protocols
#
CONFIG_AX25=m
CONFIG_AX25_DAMA_SLAVE=y
CONFIG_NETROM=m
CONFIG_ROSE=m

#
# AX.25 network device drivers
#
CONFIG_MKISS=m
CONFIG_6PACK=m
CONFIG_BPQETHER=m
CONFIG_BAYCOM_SER_FDX=m
CONFIG_BAYCOM_SER_HDX=m
CONFIG_YAM=m
# end of AX.25 network device drivers

CONFIG_CAN=m
CONFIG_CAN_RAW=m
CONFIG_CAN_BCM=m
CONFIG_CAN_GW=m
# CONFIG_CAN_J1939 is not set

#
# CAN Device Drivers
#
CONFIG_CAN_VCAN=m
CONFIG_CAN_VXCAN=m
CONFIG_CAN_SLCAN=m
CONFIG_CAN_DEV=m
CONFIG_CAN_CALC_BITTIMING=y
# CONFIG_CAN_FLEXCAN is not set
CONFIG_CAN_GRCAN=m
# CONFIG_CAN_KVASER_PCIEFD is not set
CONFIG_CAN_XILINXCAN=m
CONFIG_CAN_C_CAN=m
CONFIG_CAN_C_CAN_PLATFORM=m
# CONFIG_CAN_C_CAN_PCI is not set
CONFIG_CAN_CC770=m
CONFIG_CAN_CC770_ISA=m
CONFIG_CAN_CC770_PLATFORM=m
# CONFIG_CAN_IFI_CANFD is not set
CONFIG_CAN_M_CAN=m
# CONFIG_CAN_M_CAN_PLATFORM is not set
# CONFIG_CAN_M_CAN_TCAN4X5X is not set
# CONFIG_CAN_PEAK_PCIEFD is not set
CONFIG_CAN_SJA1000=m
# CONFIG_CAN_EMS_PCI is not set
# CONFIG_CAN_F81601 is not set
# CONFIG_CAN_KVASER_PCI is not set
# CONFIG_CAN_PEAK_PCI is not set
# CONFIG_CAN_PLX_PCI is not set
CONFIG_CAN_SJA1000_ISA=m
CONFIG_CAN_SJA1000_PLATFORM=m
CONFIG_CAN_SOFTING=m

#
# CAN SPI interfaces
#
CONFIG_CAN_HI311X=m
CONFIG_CAN_MCP251X=m
# end of CAN SPI interfaces

#
# CAN USB interfaces
#
CONFIG_CAN_8DEV_USB=m
CONFIG_CAN_EMS_USB=m
CONFIG_CAN_ESD_USB2=m
CONFIG_CAN_GS_USB=m
CONFIG_CAN_KVASER_USB=m
CONFIG_CAN_MCBA_USB=m
CONFIG_CAN_PEAK_USB=m
# CONFIG_CAN_UCAN is not set
# end of CAN USB interfaces

# CONFIG_CAN_DEBUG_DEVICES is not set
# end of CAN Device Drivers

CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=m
CONFIG_BT_HS=y
CONFIG_BT_LE=y
CONFIG_BT_6LOWPAN=m
CONFIG_BT_LEDS=y
CONFIG_BT_SELFTEST=y
CONFIG_BT_SELFTEST_ECDH=y
CONFIG_BT_SELFTEST_SMP=y
# CONFIG_BT_DEBUGFS is not set

#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=m
CONFIG_BT_BCM=m
CONFIG_BT_RTL=m
CONFIG_BT_QCA=m
CONFIG_BT_HCIBTUSB=m
# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
CONFIG_BT_HCIBTUSB_BCM=y
CONFIG_BT_HCIBTUSB_MTK=y
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_NOKIA=m
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_BCM=y
CONFIG_BT_HCIUART_RTL=y
CONFIG_BT_HCIUART_QCA=y
CONFIG_BT_HCIUART_AG6XX=y
CONFIG_BT_HCIUART_MRVL=y
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
CONFIG_BT_MTKSDIO=m
CONFIG_BT_MTKUART=m
CONFIG_BT_HCIRSI=m
# end of Bluetooth device drivers

CONFIG_AF_RXRPC=m
CONFIG_AF_RXRPC_IPV6=y
CONFIG_AF_RXRPC_INJECT_LOSS=y
CONFIG_AF_RXRPC_DEBUG=y
CONFIG_RXKAD=y
CONFIG_AF_KCM=m
CONFIG_STREAM_PARSER=y
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
CONFIG_CFG80211_CERTIFICATION_ONUS=y
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_EXTRA_REGDB_KEYDIR=""
CONFIG_CFG80211_REG_CELLULAR_HINTS=y
CONFIG_CFG80211_REG_RELAX_NO_IR=y
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
# CONFIG_CFG80211_WEXT is not set
CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
CONFIG_LIB80211_DEBUG=y
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_MESSAGE_TRACING is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
# CONFIG_WIMAX is not set
CONFIG_RFKILL=m
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=m
CONFIG_NET_9P=m
CONFIG_NET_9P_VIRTIO=m
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
CONFIG_CEPH_LIB=m
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
# CONFIG_NFC is not set
CONFIG_PSAMPLE=m
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
CONFIG_FAILOVER=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_SHORTCUT_FE=y

#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
# CONFIG_PCIEPORTBUS is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_STUB is not set
CONFIG_PCI_ECAM=y
# CONFIG_PCI_IOV is not set
# CONFIG_PCI_PRI is not set
# CONFIG_PCI_PASID is not set
CONFIG_PCI_LABEL=y
# CONFIG_HOTPLUG_PCI is not set

#
# PCI controller drivers
#

#
# Cadence PCIe controllers support
#
# CONFIG_PCIE_CADENCE_HOST is not set
# end of Cadence PCIe controllers support

# CONFIG_PCI_FTPCI100 is not set
# CONFIG_PCI_HOST_GENERIC is not set
# CONFIG_PCIE_XILINX is not set
# CONFIG_PCI_XGENE is not set
# CONFIG_PCIE_ALTERA is not set
# CONFIG_PCI_HOST_THUNDER_PEM is not set
# CONFIG_PCI_HOST_THUNDER_ECAM is not set
CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_HOST=y

#
# DesignWare PCI Core Support
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
# CONFIG_PCI_HISI is not set
# CONFIG_PCIE_KIRIN is not set
CONFIG_PCI_MESON=y
# CONFIG_PCIE_AL is not set
# end of DesignWare PCI Core Support
# end of PCI controller drivers

#
# PCI Endpoint
#
# CONFIG_PCI_ENDPOINT is not set
# end of PCI Endpoint

#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set
# end of PCI switch controller drivers

# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_FW_LOADER_USER_HELPER is not set
# CONFIG_FW_LOADER_COMPRESS is not set
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SCCB=m
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
CONFIG_BRCMSTB_GISB_ARB=y
# CONFIG_MOXTET is not set
CONFIG_SIMPLE_PM_BUS=y
CONFIG_SUN50I_DE2_BUS=y
CONFIG_SUNXI_RSB=y
CONFIG_VEXPRESS_CONFIG=y
# end of Bus devices

CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
CONFIG_GNSS=m
CONFIG_GNSS_SERIAL=m
CONFIG_GNSS_MTK_SERIAL=m
CONFIG_GNSS_SIRF_SERIAL=m
CONFIG_GNSS_UBX_SERIAL=m
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_AFS_PARTS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_DATAFLASH is not set
CONFIG_MTD_MCHP23K256=m
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
# CONFIG_MTD_SPI_NAND is not set

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_MTK_QUADSPI is not set
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
# CONFIG_MTD_UBI_BLOCK is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_NET=y
CONFIG_OF_MDIO=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_NULL_BLK is not set
CONFIG_CDROM=m
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
CONFIG_ZRAM=m
CONFIG_ZRAM_WRITEBACK=y
CONFIG_ZRAM_MEMORY_TRACKING=y
# CONFIG_BLK_DEV_UMEM is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=128
CONFIG_BLK_DEV_CRYPTOLOOP=m
CONFIG_BLK_DEV_DRBD=m
CONFIG_DRBD_FAULT_INJECTION=y
CONFIG_BLK_DEV_NBD=m
# CONFIG_BLK_DEV_SKD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_VIRTIO_BLK=m
CONFIG_VIRTIO_BLK_SCSI=y
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_RSXX is not set

#
# NVME Support
#
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
# CONFIG_NVME_MULTIPATH is not set
CONFIG_NVME_FABRICS=m
# CONFIG_NVME_FC is not set
CONFIG_NVME_TCP=m
CONFIG_NVME_TARGET=m
CONFIG_NVME_TARGET_LOOP=m
# CONFIG_NVME_TARGET_FC is not set
CONFIG_NVME_TARGET_TCP=m
# end of NVME Support

#
# Misc devices
#
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
CONFIG_TIFM_CORE=m
CONFIG_TIFM_7XX1=m
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
CONFIG_VEXPRESS_SYSCFG=y
# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_XILINX_SDFEC is not set
CONFIG_MISC_RTSX=m
# CONFIG_PVPANIC is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
CONFIG_EEPROM_AT25=m
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
CONFIG_EEPROM_93CX6=m
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

CONFIG_CB710_CORE=m
# CONFIG_CB710_DEBUG is not set
CONFIG_CB710_DEBUG_ASSUMPTIONS=y

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline

# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set

#
# Intel MIC & related support
#

#
# Intel MIC Bus Driver
#

#
# SCIF Bus Driver
#

#
# VOP Bus Driver
#
# CONFIG_VOP_BUS is not set

#
# Intel MIC Host Driver
#

#
# Intel MIC Card Driver
#

#
# SCIF Driver
#

#
# Intel MIC Coprocessor State Management (COSM) Drivers
#

#
# VOP Driver
#
# end of Intel MIC & related support

# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_MISC_ALCOR_PCI is not set
# CONFIG_MISC_RTSX_PCI is not set
CONFIG_MISC_RTSX_USB=m
# CONFIG_HABANA_AI is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=m
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=m
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_ISCSI_BOOT_SYSFS=m
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_FDOMAIN_PCI is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
CONFIG_SCSI_VIRTIO=m
# CONFIG_SCSI_DH is not set
# end of SCSI device support

CONFIG_HAVE_PATA_PLATFORM=y
CONFIG_ATA=m
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=m
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=m
# CONFIG_AHCI_CEVA is not set
CONFIG_AHCI_SUNXI=m
# CONFIG_AHCI_QORIQ is not set
# CONFIG_SATA_INIC162X is not set
# CONFIG_SATA_ACARD_AHCI is not set
# CONFIG_SATA_SIL24 is not set
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#
# CONFIG_PDC_ADMA is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_SATA_SX4 is not set
CONFIG_ATA_BMDMA=y

#
# SATA SFF controllers with BMDMA
#
# CONFIG_ATA_PIIX is not set
# CONFIG_SATA_DWC is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_NV is not set
# CONFIG_SATA_PROMISE is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIS is not set
# CONFIG_SATA_SVW is not set
# CONFIG_SATA_ULI is not set
# CONFIG_SATA_VIA is not set
# CONFIG_SATA_VITESSE is not set

#
# PATA SFF controllers with BMDMA
#
# CONFIG_PATA_ALI is not set
# CONFIG_PATA_AMD is not set
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_ATP867X is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CYPRESS is not set
# CONFIG_PATA_EFAR is not set
# CONFIG_PATA_HPT366 is not set
# CONFIG_PATA_HPT37X is not set
# CONFIG_PATA_HPT3X2N is not set
# CONFIG_PATA_HPT3X3 is not set
# CONFIG_PATA_IT8213 is not set
# CONFIG_PATA_IT821X is not set
# CONFIG_PATA_JMICRON is not set
# CONFIG_PATA_MARVELL is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_OPTIDMA is not set
# CONFIG_PATA_PDC2027X is not set
# CONFIG_PATA_PDC_OLD is not set
# CONFIG_PATA_RADISYS is not set
# CONFIG_PATA_RDC is not set
# CONFIG_PATA_SCH is not set
# CONFIG_PATA_SERVERWORKS is not set
# CONFIG_PATA_SIL680 is not set
# CONFIG_PATA_SIS is not set
# CONFIG_PATA_TOSHIBA is not set
# CONFIG_PATA_TRIFLEX is not set
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set

#
# PIO-only SFF controllers
#
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_PLATFORM is not set
# CONFIG_PATA_RZ1000 is not set

#
# Generic fallback / legacy drivers
#
# CONFIG_PATA_ACPI is not set
# CONFIG_ATA_GENERIC is not set
# CONFIG_PATA_LEGACY is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
CONFIG_MD_CLUSTER=m
CONFIG_BCACHE=m
# CONFIG_BCACHE_DEBUG is not set
# CONFIG_BCACHE_CLOSURES_DEBUG is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=m
# CONFIG_DM_DEBUG is not set
CONFIG_DM_BUFIO=m
# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
CONFIG_DM_CACHE=m
CONFIG_DM_CACHE_SMQ=m
CONFIG_DM_WRITECACHE=m
# CONFIG_DM_ERA is not set
# CONFIG_DM_CLONE is not set
CONFIG_DM_MIRROR=m
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
CONFIG_DM_DELAY=m
# CONFIG_DM_DUST is not set
# CONFIG_DM_UEVENT is not set
CONFIG_DM_FLAKEY=m
CONFIG_DM_VERITY=m
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
# CONFIG_DM_VERITY_FEC is not set
# CONFIG_DM_SWITCH is not set
CONFIG_DM_LOG_WRITES=m
CONFIG_DM_INTEGRITY=m
CONFIG_TARGET_CORE=m
CONFIG_TCM_IBLOCK=m
CONFIG_TCM_FILEIO=m
CONFIG_TCM_PSCSI=m
# CONFIG_LOOPBACK_TARGET is not set
CONFIG_ISCSI_TARGET=m
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
# end of IEEE 1394 (FireWire) support

CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_EQUALIZER=m
# CONFIG_NET_FC is not set
CONFIG_IFB=m
CONFIG_NET_TEAM=m
CONFIG_NET_TEAM_MODE_BROADCAST=m
CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
CONFIG_NET_TEAM_MODE_RANDOM=m
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
CONFIG_NET_TEAM_MODE_LOADBALANCE=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=m
CONFIG_IPVTAP=m
CONFIG_VXLAN=m
CONFIG_GENEVE=m
CONFIG_GTP=m
CONFIG_MACSEC=m
CONFIG_NETCONSOLE=m
CONFIG_NETCONSOLE_DYNAMIC=y
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=m
CONFIG_TAP=m
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_NLMON=m
CONFIG_NET_VRF=m
CONFIG_VSOCKMON=m
# CONFIG_ARCNET is not set

#
# CAIF transport drivers
#

#
# Distributed Switch Architecture drivers
#
CONFIG_B53=m
CONFIG_B53_SPI_DRIVER=m
CONFIG_B53_MDIO_DRIVER=m
CONFIG_B53_MMAP_DRIVER=m
CONFIG_B53_SRAB_DRIVER=m
CONFIG_B53_SERDES=m
CONFIG_NET_DSA_BCM_SF2=m
CONFIG_NET_DSA_LOOP=m
CONFIG_NET_DSA_LANTIQ_GSWIP=m
CONFIG_NET_DSA_MT7530=m
CONFIG_NET_DSA_MV88E6060=m
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m
CONFIG_NET_DSA_MICROCHIP_KSZ8795=m
CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m
CONFIG_NET_DSA_MV88E6XXX=m
CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
CONFIG_NET_DSA_MV88E6XXX_PTP=y
CONFIG_NET_DSA_SJA1105=m
CONFIG_NET_DSA_SJA1105_PTP=y
# CONFIG_NET_DSA_SJA1105_TAS is not set
CONFIG_NET_DSA_QCA8K=m
CONFIG_NET_DSA_REALTEK_SMI=m
CONFIG_NET_DSA_SMSC_LAN9303=m
CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
CONFIG_NET_DSA_VITESSE_VSC73XX=m
CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
# end of Distributed Switch Architecture drivers

CONFIG_ETHERNET=y
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
CONFIG_NET_VENDOR_ALLWINNER=y
CONFIG_SUN4I_EMAC=y
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_ALTERA_TSE is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_ATHEROS is not set
# CONFIG_NET_VENDOR_AURORA is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_BROCADE is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_DNET is not set
# CONFIG_NET_VENDOR_DEC is not set
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_JME is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_FEALNX is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETERION is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCA7000_UART is not set
# CONFIG_QCOM_EMAC is not set
CONFIG_SFE_SUPPORT_IPV6=y
CONFIG_FAST_CLASSIFIER=y
CONFIG_SFE_ECM=y
# CONFIG_RMNET is not set
# CONFIG_NET_VENDOR_RDC is not set
# CONFIG_NET_VENDOR_REALTEK is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_SELFTESTS=y
CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_MESON=y
CONFIG_DWMAC_ROCKCHIP=y
CONFIG_DWMAC_SUNXI=y
CONFIG_DWMAC_SUN8I=y
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_NET_SB1000 is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_BCM_UNIMAC=m
CONFIG_MDIO_BITBANG=m
CONFIG_MDIO_BUS_MUX=y
CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_MDIO_BUS_MUX_MESON_G12A=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y
CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
CONFIG_MDIO_CAVIUM=m
CONFIG_MDIO_GPIO=m
CONFIG_MDIO_HISI_FEMAC=m
CONFIG_MDIO_MSCC_MIIM=m
CONFIG_MDIO_OCTEON=m
CONFIG_MDIO_SUN4I=y
CONFIG_MDIO_THUNDER=m
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_LED_TRIGGER_PHY=y

#
# MII PHY device drivers
#
# CONFIG_SFP is not set
# CONFIG_ADIN_PHY is not set
# CONFIG_AMD_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
# CONFIG_AX88796B_PHY is not set
# CONFIG_AT803X_PHY is not set
CONFIG_BCM7XXX_PHY=m
# CONFIG_BCM87XX_PHY is not set
CONFIG_BCM_NET_PHYLIB=m
# CONFIG_BROADCOM_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
CONFIG_FIXED_PHY=y
CONFIG_ICPLUS_PHY=m
CONFIG_JLSEMI_PHY=y
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
CONFIG_MESON_GXL_PHY=y
# CONFIG_MICREL_PHY is not set
CONFIG_MICROCHIP_PHY=m
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
# CONFIG_NATIONAL_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
# CONFIG_QSEMI_PHY is not set
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
# CONFIG_SMSC_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
CONFIG_VITESSE_PHY=m
# CONFIG_XILINX_GMII2RGMII is not set
CONFIG_MICREL_KS8995MA=m
CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=m
# CONFIG_PPTP is not set
# CONFIG_PPPOL2TP is not set
CONFIG_PPP_ASYNC=m
# CONFIG_PPP_SYNC_TTY is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=m
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_AX8817X=m
CONFIG_USB_NET_AX88179_178A=m
CONFIG_USB_NET_CDCETHER=m
CONFIG_USB_NET_CDC_EEM=m
CONFIG_USB_NET_CDC_NCM=m
CONFIG_USB_NET_HUAWEI_CDC_NCM=m
CONFIG_USB_NET_CDC_MBIM=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9700=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
CONFIG_USB_NET_CDC_SUBSET=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
CONFIG_USB_EPSON2888=y
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=m
CONFIG_USB_NET_CX82310_ETH=m
CONFIG_USB_NET_KALMIA=m
CONFIG_USB_NET_QMI_WWAN=m
CONFIG_USB_HSO=m
CONFIG_USB_NET_INT51X1=m
CONFIG_USB_CDC_PHONET=m
CONFIG_USB_IPHETH=m
CONFIG_USB_SIERRA_NET=m
CONFIG_USB_VL600=m
CONFIG_USB_NET_CH9200=m
CONFIG_USB_NET_AQC111=m
CONFIG_WLAN=y
CONFIG_WIRELESS_WDS=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
# CONFIG_ATH_DEBUG is not set
CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS=y
CONFIG_ATH_REG_DYNAMIC_USER_CERT_TESTING=y
# CONFIG_ATH5K is not set
# CONFIG_ATH5K_PCI is not set
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=m
# CONFIG_ATH9K_PCI is not set
CONFIG_ATH9K_AHB=y
# CONFIG_ATH9K_DEBUGFS is not set
CONFIG_ATH9K_DFS_CERTIFIED=y
CONFIG_ATH9K_DYNACK=y
# CONFIG_ATH9K_WOW is not set
CONFIG_ATH9K_RFKILL=y
CONFIG_ATH9K_CHANNEL_CONTEXT=y
CONFIG_ATH9K_PCOEM=y
CONFIG_ATH9K_HTC=m
# CONFIG_ATH9K_HTC_DEBUGFS is not set
CONFIG_ATH9K_HWRNG=y
CONFIG_CARL9170=m
# CONFIG_CARL9170_LEDS is not set
CONFIG_CARL9170_WPC=y
CONFIG_CARL9170_HWRNG=y
CONFIG_ATH6KL=m
CONFIG_ATH6KL_SDIO=m
CONFIG_ATH6KL_USB=m
# CONFIG_ATH6KL_DEBUG is not set
CONFIG_ATH6KL_REGDOMAIN=y
CONFIG_AR5523=m
# CONFIG_WIL6210 is not set
CONFIG_ATH10K=m
CONFIG_ATH10K_CE=y
# CONFIG_ATH10K_PCI is not set
CONFIG_ATH10K_SDIO=m
CONFIG_ATH10K_USB=m
# CONFIG_ATH10K_DEBUG is not set
# CONFIG_ATH10K_DEBUGFS is not set
CONFIG_ATH10K_DFS_CERTIFIED=y
# CONFIG_WCN36XX is not set
CONFIG_WLAN_VENDOR_ATMEL=y
# CONFIG_ATMEL is not set
CONFIG_AT76C50X_USB=m
CONFIG_WLAN_VENDOR_BROADCOM=y
CONFIG_B43=m
CONFIG_B43_BCMA=y
CONFIG_B43_SSB=y
CONFIG_B43_BUSES_BCMA_AND_SSB=y
# CONFIG_B43_BUSES_BCMA is not set
# CONFIG_B43_BUSES_SSB is not set
CONFIG_B43_PCI_AUTOSELECT=y
CONFIG_B43_PCICORE_AUTOSELECT=y
CONFIG_B43_SDIO=y
CONFIG_B43_BCMA_PIO=y
CONFIG_B43_PIO=y
CONFIG_B43_PHY_G=y
CONFIG_B43_PHY_N=y
CONFIG_B43_PHY_LP=y
CONFIG_B43_PHY_HT=y
CONFIG_B43_LEDS=y
CONFIG_B43_HWRNG=y
CONFIG_B43_DEBUG=y
CONFIG_B43LEGACY=m
CONFIG_B43LEGACY_PCI_AUTOSELECT=y
CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
CONFIG_B43LEGACY_LEDS=y
CONFIG_B43LEGACY_HWRNG=y
CONFIG_B43LEGACY_DEBUG=y
CONFIG_B43LEGACY_DMA=y
CONFIG_B43LEGACY_PIO=y
CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
# CONFIG_B43LEGACY_DMA_MODE is not set
# CONFIG_B43LEGACY_PIO_MODE is not set
CONFIG_BRCMUTIL=m
# CONFIG_BRCMSMAC is not set
CONFIG_BRCMFMAC=m
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
# CONFIG_BRCMFMAC_PCIE is not set
CONFIG_BRCM_TRACING=y
CONFIG_BRCMDBG=y
# CONFIG_WLAN_VENDOR_CISCO is not set
# CONFIG_WLAN_VENDOR_INTEL is not set
# CONFIG_WLAN_VENDOR_INTERSIL is not set
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_USB=m
CONFIG_LIBERTAS_SDIO=m
CONFIG_LIBERTAS_SPI=m
# CONFIG_LIBERTAS_DEBUG is not set
CONFIG_LIBERTAS_MESH=y
CONFIG_LIBERTAS_THINFIRM=m
# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
CONFIG_LIBERTAS_THINFIRM_USB=m
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_SDIO=m
# CONFIG_MWIFIEX_PCIE is not set
CONFIG_MWIFIEX_USB=m
# CONFIG_MWL8K is not set
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=m
CONFIG_MT76_CORE=m
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=m
CONFIG_MT76x02_LIB=m
CONFIG_MT76x02_USB=m
CONFIG_MT76x0_COMMON=m
CONFIG_MT76x0U=m
# CONFIG_MT76x0E is not set
CONFIG_MT76x2_COMMON=m
# CONFIG_MT76x2E is not set
CONFIG_MT76x2U=m
# CONFIG_MT7603E is not set
# CONFIG_MT7615E is not set
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=m
# CONFIG_RT2400PCI is not set
# CONFIG_RT2500PCI is not set
# CONFIG_RT61PCI is not set
# CONFIG_RT2800PCI is not set
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
CONFIG_RT2800USB_RT33XX=y
CONFIG_RT2800USB_RT35XX=y
CONFIG_RT2800USB_RT3573=y
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
CONFIG_RT2800USB_UNKNOWN=y
CONFIG_RT2800_LIB=m
CONFIG_RT2X00_LIB_USB=m
CONFIG_RT2X00_LIB=m
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
# CONFIG_RT2X00_DEBUG is not set
CONFIG_WLAN_VENDOR_REALTEK=y
# CONFIG_RTL8180 is not set
CONFIG_RTL8187=m
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=m
# CONFIG_RTL8192CE is not set
# CONFIG_RTL8192SE is not set
# CONFIG_RTL8192DE is not set
# CONFIG_RTL8723AE is not set
# CONFIG_RTL8723BE is not set
# CONFIG_RTL8188EE is not set
# CONFIG_RTL8192EE is not set
# CONFIG_RTL8821AE is not set
# CONFIG_RTL8192CU is not set
CONFIG_RTL8XXXU=m
# CONFIG_RTL8XXXU_UNTESTED is not set
# CONFIG_RTW88 is not set
# CONFIG_RTL8822BU is not set
# CONFIG_RTL8188EU is not set
CONFIG_RTL8188FU=m
CONFIG_RTL8189FS=m
# CONFIG_RTL8821CU is not set
CONFIG_88XXAU=m
# CONFIG_RTL8192EU is not set
CONFIG_RTL8822CS=m
CONFIG_WLAN_VENDOR_RSI=y
CONFIG_RSI_91X=m
CONFIG_RSI_DEBUGFS=y
CONFIG_RSI_SDIO=m
CONFIG_RSI_USB=m
CONFIG_RSI_COEX=y
CONFIG_WLAN_VENDOR_ST=y
CONFIG_CW1200=m
CONFIG_CW1200_WLAN_SDIO=m
# CONFIG_CW1200_WLAN_SPI is not set
CONFIG_WLAN_VENDOR_TI=y
CONFIG_WL1251=m
# CONFIG_WL1251_SPI is not set
CONFIG_WL1251_SDIO=m
CONFIG_WL12XX=m
CONFIG_WL18XX=m
CONFIG_WLCORE=m
# CONFIG_WLCORE_SPI is not set
CONFIG_WLCORE_SDIO=m
CONFIG_WILINK_PLATFORM_DATA=y
CONFIG_WLAN_VENDOR_ZYDAS=y
CONFIG_USB_ZD1201=m
CONFIG_ZD1211RW=m
# CONFIG_ZD1211RW_DEBUG is not set
CONFIG_WLAN_VENDOR_QUANTENNA=y
# CONFIG_QTNFMAC_PCIE is not set
CONFIG_MAC80211_HWSIM=m
CONFIG_USB_NET_RNDIS_WLAN=m
CONFIG_VIRT_WIFI=m

#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
CONFIG_IEEE802154_AT86RF230=m
CONFIG_IEEE802154_AT86RF230_DEBUGFS=y
CONFIG_IEEE802154_MRF24J40=m
CONFIG_IEEE802154_CC2520=m
CONFIG_IEEE802154_ATUSB=m
CONFIG_IEEE802154_ADF7242=m
CONFIG_IEEE802154_CA8210=m
CONFIG_IEEE802154_CA8210_DEBUGFS=y
CONFIG_IEEE802154_MCR20A=m
CONFIG_IEEE802154_HWSIM=m
CONFIG_VMXNET3=m
# CONFIG_FUJITSU_ES is not set
CONFIG_NETDEVSIM=m
CONFIG_NET_FAILOVER=m
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_POLLDEV=y
# CONFIG_INPUT_SPARSEKMAP is not set
CONFIG_INPUT_MATRIXKMAP=m

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=y
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADC is not set
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_GPIO_POLLED=m
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
CONFIG_KEYBOARD_SUN4I_LRADC=y
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=m
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_SMBUS=y
# CONFIG_MOUSE_SERIAL is not set
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=m
CONFIG_MOUSE_ELAN_I2C=m
CONFIG_MOUSE_ELAN_I2C_I2C=y
# CONFIG_MOUSE_ELAN_I2C_SMBUS is not set
# CONFIG_MOUSE_VSXXXAA is not set
CONFIG_MOUSE_GPIO=m
CONFIG_MOUSE_SYNAPTICS_I2C=m
CONFIG_MOUSE_SYNAPTICS_USB=m
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_ANALOG=m
CONFIG_JOYSTICK_A3D=m
CONFIG_JOYSTICK_ADI=m
CONFIG_JOYSTICK_COBRA=m
CONFIG_JOYSTICK_GF2K=m
CONFIG_JOYSTICK_GRIP=m
CONFIG_JOYSTICK_GRIP_MP=m
CONFIG_JOYSTICK_GUILLEMOT=m
CONFIG_JOYSTICK_INTERACT=m
CONFIG_JOYSTICK_SIDEWINDER=m
CONFIG_JOYSTICK_TMDC=m
CONFIG_JOYSTICK_IFORCE=m
CONFIG_JOYSTICK_IFORCE_USB=m
CONFIG_JOYSTICK_IFORCE_232=m
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
CONFIG_JOYSTICK_STINGER=m
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
CONFIG_JOYSTICK_AS5011=m
CONFIG_JOYSTICK_JOYDUMP=m
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_JOYSTICK_PSXPAD_SPI=m
CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
CONFIG_JOYSTICK_PXRC=m
CONFIG_JOYSTICK_FSIA6B=m
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
# CONFIG_INPUT_BMA150 is not set
# CONFIG_INPUT_E3X0_BUTTON is not set
# CONFIG_INPUT_MSM_VIBRATOR is not set
# CONFIG_INPUT_MMA8450 is not set
# CONFIG_INPUT_GP2A is not set
CONFIG_INPUT_GPIO_BEEPER=m
# CONFIG_INPUT_GPIO_DECODER is not set
# CONFIG_INPUT_GPIO_VIBRA is not set
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
# CONFIG_INPUT_KXTJ9 is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
CONFIG_INPUT_CM109=m
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
CONFIG_INPUT_AXP20X_PEK=y
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_PWM_BEEPER is not set
# CONFIG_INPUT_PWM_VIBRA is not set
CONFIG_INPUT_RK805_PWRKEY=y
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_INPUT_CMA3000 is not set
# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
# CONFIG_INPUT_DRV260X_HAPTICS is not set
# CONFIG_INPUT_DRV2665_HAPTICS is not set
# CONFIG_INPUT_DRV2667_HAPTICS is not set
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=m
CONFIG_RMI4_SPI=m
CONFIG_RMI4_SMB=m
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=y
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
CONFIG_RMI4_F54=y
CONFIG_RMI4_F55=y

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=m
# CONFIG_SERIO_AMBAKMI is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=m
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
CONFIG_SERIO_SUN4I_PS2=y
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
CONFIG_GAMEPORT=m
# CONFIG_GAMEPORT_NS558 is not set
# CONFIG_GAMEPORT_L4 is not set
# CONFIG_GAMEPORT_EMU10K1 is not set
# CONFIG_GAMEPORT_FM801 is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_NOZOMI is not set
# CONFIG_N_GSM is not set
# CONFIG_TRACE_SINK is not set
# CONFIG_NULL_TTY is not set
CONFIG_LDISC_AUTOLOAD=y
CONFIG_DEVMEM=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=5
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
# CONFIG_SERIAL_8250_ASPEED_VUART is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_RSA is not set
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
CONFIG_SERIAL_AMBA_PL010=y
CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y
CONFIG_SERIAL_MESON=y
CONFIG_SERIAL_MESON_CONSOLE=y
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_IFX6X60 is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_TTY_PRINTK is not set
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
CONFIG_VIRTIO_CONSOLE=m
# CONFIG_IPMI_HANDLER is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=y
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_ROCKCHIP=y
CONFIG_HW_RANDOM_MESON=y
CONFIG_HW_RANDOM_CAVIUM=m
CONFIG_HW_RANDOM_OPTEE=m
# CONFIG_APPLICOM is not set
CONFIG_RAW_DRIVER=m
CONFIG_MAX_RAW_DEVS=256
# CONFIG_TCG_TPM is not set
CONFIG_DEVPORT=y
# CONFIG_XILLYBUS is not set
CONFIG_RANDOM_TRUST_BOOTLOADER=y
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_I2C_MUX_GPIO=y
CONFIG_I2C_MUX_GPMUX=y
CONFIG_I2C_MUX_LTC4306=m
CONFIG_I2C_MUX_PCA9541=m
CONFIG_I2C_MUX_PCA954x=m
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_MUX_REG=y
CONFIG_I2C_DEMUX_PINCTRL=y
CONFIG_I2C_MUX_MLXCPLD=m
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_ALGOBIT=y

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set

#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CADENCE is not set
# CONFIG_I2C_CBUS_GPIO is not set
CONFIG_I2C_DESIGNWARE_CORE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_DESIGNWARE_SLAVE=y
# CONFIG_I2C_DESIGNWARE_PCI is not set
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=y
CONFIG_I2C_GPIO_FAULT_INJECTOR=y
CONFIG_I2C_MESON=y
CONFIG_I2C_MV64XXX=y
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
CONFIG_I2C_RK3X=y
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_THUNDERX is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
# end of I2C Hardware Bus support

# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=m
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

# CONFIG_I3C is not set
CONFIG_SPI=y
CONFIG_SPI_DEBUG=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y

#
# SPI Master Controller Drivers
#
CONFIG_SPI_ALTERA=m
CONFIG_SPI_AXI_SPI_ENGINE=m
CONFIG_SPI_BITBANG=m
CONFIG_SPI_CADENCE=m
CONFIG_SPI_DESIGNWARE=m
# CONFIG_SPI_DW_PCI is not set
CONFIG_SPI_DW_MMIO=m
CONFIG_SPI_NXP_FLEXSPI=m
CONFIG_SPI_GPIO=m
CONFIG_SPI_FSL_LIB=m
CONFIG_SPI_FSL_SPI=m
CONFIG_SPI_MESON_SPICC=y
CONFIG_SPI_MESON_SPIFC=y
CONFIG_SPI_OC_TINY=m
CONFIG_SPI_PL022=m
CONFIG_SPI_PXA2XX=m
CONFIG_SPI_PXA2XX_PCI=m
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_SC18IS602=m
CONFIG_SPI_SIFIVE=m
CONFIG_SPI_SUN4I=y
CONFIG_SPI_SUN6I=y
CONFIG_SPI_MXIC=m
CONFIG_SPI_THUNDERX=m
CONFIG_SPI_XCOMM=m
CONFIG_SPI_XILINX=m
CONFIG_SPI_ZYNQMP_GQSPI=m

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=m
CONFIG_SPI_LOOPBACK_TEST=m
CONFIG_SPI_TLE62X0=m
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_DYNAMIC=y
CONFIG_SPMI=y
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set
# CONFIG_NTP_PPS is not set

#
# PPS clients support
#
CONFIG_PPS_CLIENT_KTIMER=m
CONFIG_PPS_CLIENT_LDISC=m
CONFIG_PPS_CLIENT_GPIO=m

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_DP83640_PHY=y
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
CONFIG_PINCTRL_AXP209=y
CONFIG_PINCTRL_AMD=m
CONFIG_PINCTRL_MCP23S08=m
CONFIG_PINCTRL_ROCKCHIP=y
CONFIG_PINCTRL_SINGLE=y
# CONFIG_PINCTRL_SX150X is not set
CONFIG_PINCTRL_STMFX=m
CONFIG_PINCTRL_RK805=y
# CONFIG_PINCTRL_OCELOT is not set
CONFIG_PINCTRL_SUNXI=y
CONFIG_PINCTRL_SUN4I_A10=y
CONFIG_PINCTRL_SUN5I=y
CONFIG_PINCTRL_SUN6I_A31=y
CONFIG_PINCTRL_SUN6I_A31_R=y
CONFIG_PINCTRL_SUN8I_A23=y
CONFIG_PINCTRL_SUN8I_A33=y
CONFIG_PINCTRL_SUN8I_A83T=y
CONFIG_PINCTRL_SUN8I_A83T_R=y
CONFIG_PINCTRL_SUN8I_A23_R=y
CONFIG_PINCTRL_SUN8I_H3=y
CONFIG_PINCTRL_SUN8I_H3_R=y
CONFIG_PINCTRL_SUN8I_V3S=y
CONFIG_PINCTRL_SUN9I_A80=y
CONFIG_PINCTRL_SUN9I_A80_R=y
CONFIG_PINCTRL_SUN50I_A64=y
CONFIG_PINCTRL_SUN50I_A64_R=y
CONFIG_PINCTRL_SUN50I_H5=y
CONFIG_PINCTRL_SUN50I_H6=y
CONFIG_PINCTRL_SUN50I_H6_R=y
CONFIG_PINCTRL_MESON=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_PINCTRL_MESON8_PMX=y
CONFIG_PINCTRL_MESON_AXG=y
CONFIG_PINCTRL_MESON_AXG_PMX=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_MAX730X=m

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_FTGPIO010 is not set
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_MB86S7X is not set
CONFIG_GPIO_PL061=y
# CONFIG_GPIO_SAMA5D2_PIOBU is not set
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_XGENE=y
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
CONFIG_GPIO_ADP5588=m
CONFIG_GPIO_ADNP=m
CONFIG_GPIO_GW_PLD=m
CONFIG_GPIO_MAX7300=m
CONFIG_GPIO_MAX732X=m
CONFIG_GPIO_PCA953X=m
CONFIG_GPIO_PCF857X=m
CONFIG_GPIO_TPIC2810=m
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set
# end of PCI GPIO expanders

#
# SPI GPIO expanders
#
CONFIG_GPIO_74X164=m
CONFIG_GPIO_MAX3191X=m
CONFIG_GPIO_MAX7301=m
CONFIG_GPIO_MC33880=m
CONFIG_GPIO_PISOSR=m
CONFIG_GPIO_XRA1403=m
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
# end of USB GPIO expanders

# CONFIG_GPIO_MOCKUP is not set
CONFIG_W1=m
CONFIG_W1_CON=y

#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_MATROX=m
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
CONFIG_W1_MASTER_DS1WM=m
CONFIG_W1_MASTER_GPIO=m
CONFIG_W1_MASTER_SGI=m
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
CONFIG_W1_SLAVE_DS2405=m
CONFIG_W1_SLAVE_DS2408=m
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
# CONFIG_W1_SLAVE_DS2805 is not set
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
CONFIG_W1_SLAVE_DS2438=m
CONFIG_W1_SLAVE_DS250X=m
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
CONFIG_W1_SLAVE_DS28E17=m
# end of 1-wire Slaves

CONFIG_POWER_AVS=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_BRCMSTB=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
# CONFIG_POWER_RESET_LTC2952 is not set
CONFIG_POWER_RESET_RESTART=y
# CONFIG_POWER_RESET_VEXPRESS is not set
# CONFIG_POWER_RESET_XGENE is not set
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
# CONFIG_NVMEM_REBOOT_MODE is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_PDA_POWER is not set
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_LEGO_EV3 is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
CONFIG_CHARGER_AXP20X=y
CONFIG_BATTERY_AXP20X=y
CONFIG_AXP20X_POWER=y
CONFIG_AXP288_FUEL_GAUGE=y
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_BATTERY_MAX1721X is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
# CONFIG_CHARGER_GPIO is not set
# CONFIG_CHARGER_MANAGER is not set
# CONFIG_CHARGER_LT3651 is not set
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_BATTERY_RT5033 is not set
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_UCS1002 is not set
CONFIG_HWMON=y
CONFIG_HWMON_VID=m
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7310 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_AS370 is not set
# CONFIG_SENSORS_ASC7621 is not set
CONFIG_SENSORS_ARM_SCMI=m
CONFIG_SENSORS_ARM_SCPI=y
CONFIG_SENSORS_ASPEED=m
CONFIG_SENSORS_ATXP1=m
CONFIG_SENSORS_DS620=m
CONFIG_SENSORS_DS1621=m
CONFIG_SENSORS_I5K_AMB=m
CONFIG_SENSORS_F71805F=m
CONFIG_SENSORS_F71882FG=m
CONFIG_SENSORS_F75375S=m
CONFIG_SENSORS_FTSTEUTATES=m
CONFIG_SENSORS_GL518SM=m
CONFIG_SENSORS_GL520SM=m
CONFIG_SENSORS_G760A=m
CONFIG_SENSORS_G762=m
CONFIG_SENSORS_GPIO_FAN=m
CONFIG_SENSORS_HIH6130=m
CONFIG_SENSORS_IIO_HWMON=m
CONFIG_SENSORS_IT87=m
CONFIG_SENSORS_JC42=m
CONFIG_SENSORS_POWR1220=m
CONFIG_SENSORS_LINEAGE=m
CONFIG_SENSORS_LTC2945=m
CONFIG_SENSORS_LTC2990=m
CONFIG_SENSORS_LTC4151=m
CONFIG_SENSORS_LTC4215=m
CONFIG_SENSORS_LTC4222=m
CONFIG_SENSORS_LTC4245=m
CONFIG_SENSORS_LTC4260=m
CONFIG_SENSORS_LTC4261=m
# CONFIG_SENSORS_MAX1111 is not set
CONFIG_SENSORS_MAX16065=m
CONFIG_SENSORS_MAX1619=m
CONFIG_SENSORS_MAX1668=m
CONFIG_SENSORS_MAX197=m
CONFIG_SENSORS_MAX31722=m
CONFIG_SENSORS_MAX6621=m
CONFIG_SENSORS_MAX6639=m
CONFIG_SENSORS_MAX6642=m
CONFIG_SENSORS_MAX6650=m
CONFIG_SENSORS_MAX6697=m
CONFIG_SENSORS_MAX31790=m
CONFIG_SENSORS_MCP3021=m
CONFIG_SENSORS_TC654=m
CONFIG_SENSORS_ADCXX=m
CONFIG_SENSORS_LM63=m
CONFIG_SENSORS_LM70=m
CONFIG_SENSORS_LM73=m
CONFIG_SENSORS_LM75=m
CONFIG_SENSORS_LM77=m
CONFIG_SENSORS_LM78=m
CONFIG_SENSORS_LM80=m
CONFIG_SENSORS_LM83=m
CONFIG_SENSORS_LM85=m
CONFIG_SENSORS_LM87=m
CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_LM92=m
CONFIG_SENSORS_LM93=m
CONFIG_SENSORS_LM95234=m
CONFIG_SENSORS_LM95241=m
CONFIG_SENSORS_LM95245=m
CONFIG_SENSORS_PC87360=m
CONFIG_SENSORS_PC87427=m
CONFIG_SENSORS_NTC_THERMISTOR=m
CONFIG_SENSORS_NCT6683=m
CONFIG_SENSORS_NCT6775=m
CONFIG_SENSORS_NCT7802=m
CONFIG_SENSORS_NCT7904=m
CONFIG_SENSORS_NPCM7XX=m
CONFIG_SENSORS_OCC_P8_I2C=m
CONFIG_SENSORS_OCC=m
CONFIG_SENSORS_PCF8591=m
CONFIG_PMBUS=m
CONFIG_SENSORS_PMBUS=m
CONFIG_SENSORS_ADM1275=m
CONFIG_SENSORS_IBM_CFFPS=m
CONFIG_SENSORS_INSPUR_IPSPS=m
CONFIG_SENSORS_IR35221=m
CONFIG_SENSORS_IR38064=m
CONFIG_SENSORS_IRPS5401=m
CONFIG_SENSORS_ISL68137=m
CONFIG_SENSORS_LM25066=m
CONFIG_SENSORS_LTC2978=m
# CONFIG_SENSORS_LTC2978_REGULATOR is not set
# CONFIG_SENSORS_LTC3815 is not set
# CONFIG_SENSORS_MAX16064 is not set
# CONFIG_SENSORS_MAX20751 is not set
# CONFIG_SENSORS_MAX31785 is not set
# CONFIG_SENSORS_MAX34440 is not set
# CONFIG_SENSORS_MAX8688 is not set
# CONFIG_SENSORS_PXE1610 is not set
# CONFIG_SENSORS_TPS40422 is not set
# CONFIG_SENSORS_TPS53679 is not set
# CONFIG_SENSORS_UCD9000 is not set
# CONFIG_SENSORS_UCD9200 is not set
# CONFIG_SENSORS_ZL6100 is not set
CONFIG_SENSORS_PWM_FAN=m
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_VEXPRESS is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set

#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
# CONFIG_THERMAL_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set
CONFIG_CPU_THERMAL=y
CONFIG_CLOCK_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
# CONFIG_THERMAL_EMULATION is not set
CONFIG_THERMAL_MMIO=y
CONFIG_QORIQ_THERMAL=m
CONFIG_SUN8I_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_AMLOGIC_THERMAL=y
CONFIG_GENERIC_ADC_THERMAL=m
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=m
# CONFIG_GPIO_WATCHDOG is not set
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
CONFIG_ARM_SP805_WATCHDOG=m
CONFIG_ARM_SBSA_WATCHDOG=m
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=m
CONFIG_SUNXI_WATCHDOG=m
# CONFIG_MAX63XX_WATCHDOG is not set
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_WATCHDOG=m
# CONFIG_ALIM7101_WDT is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_MEN_A21_WDT is not set

#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB=m
CONFIG_SSB_SPROM=y
CONFIG_SSB_BLOCKIO=y
CONFIG_SSB_PCIHOST_POSSIBLE=y
CONFIG_SSB_PCIHOST=y
CONFIG_SSB_B43_PCI_BRIDGE=y
CONFIG_SSB_SDIOHOST_POSSIBLE=y
CONFIG_SSB_SDIOHOST=y
CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
CONFIG_SSB_DRIVER_PCICORE=y
# CONFIG_SSB_DRIVER_GPIO is not set
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_BLOCKIO=y
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
# CONFIG_BCMA_HOST_PCI is not set
CONFIG_BCMA_HOST_SOC=y
# CONFIG_BCMA_DRIVER_PCI is not set
CONFIG_BCMA_SFLASH=y
CONFIG_BCMA_DRIVER_GMAC_CMN=y
CONFIG_BCMA_DRIVER_GPIO=y
CONFIG_BCMA_DEBUG=y

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_SUN4I_GPADC is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
CONFIG_MFD_AC100=y
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
# CONFIG_MFD_MADERA is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_LPC_ICH is not set
CONFIG_LPC_SCH=m
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_UCB1400_CORE is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RC5T583 is not set
CONFIG_MFD_RK808=y
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_SMSC is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SUN6I_PRCM=y
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TPS68470 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS80031 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TQMX86 is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
# CONFIG_MFD_ROHM_BD70528 is not set
# CONFIG_MFD_STPMIC1 is not set
CONFIG_MFD_STMFX=m
# CONFIG_MFD_VEXPRESS_SYSREG is not set
# CONFIG_RAVE_SP_CORE is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_88PG86X is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_AD5398 is not set
# CONFIG_REGULATOR_ANATOP is not set
CONFIG_REGULATOR_AXP20X=y
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
# CONFIG_REGULATOR_FAN53555 is not set
CONFIG_REGULATOR_GPIO=y
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_LP8755 is not set
# CONFIG_REGULATOR_LTC3589 is not set
# CONFIG_REGULATOR_LTC3676 is not set
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_MAX8973 is not set
# CONFIG_REGULATOR_MCP16502 is not set
# CONFIG_REGULATOR_MT6311 is not set
# CONFIG_REGULATOR_PFUZE100 is not set
# CONFIG_REGULATOR_PV88060 is not set
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
CONFIG_REGULATOR_PWM=y
# CONFIG_REGULATOR_QCOM_SPMI is not set
CONFIG_REGULATOR_RK808=y
# CONFIG_REGULATOR_SLG51000 is not set
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_TPS6524X is not set
CONFIG_REGULATOR_VCTRL=y
# CONFIG_REGULATOR_VEXPRESS is not set
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y
CONFIG_CEC_PIN=y
CONFIG_RC_CORE=y
CONFIG_RC_MAP=y
CONFIG_LIRC=y
# CONFIG_BPF_LIRC_MODE2 is not set
CONFIG_RC_DECODERS=y
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
CONFIG_IR_JVC_DECODER=m
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_XMP_DECODER=m
CONFIG_IR_IMON_DECODER=m
CONFIG_IR_RCMM_DECODER=m
CONFIG_RC_DEVICES=y
CONFIG_RC_ATI_REMOTE=m
# CONFIG_IR_ENE is not set
CONFIG_IR_HIX5HD2=m
CONFIG_IR_IMON=m
CONFIG_IR_IMON_RAW=m
CONFIG_IR_MCEUSB=m
# CONFIG_IR_ITE_CIR is not set
# CONFIG_IR_FINTEK is not set
CONFIG_IR_MESON=m
# CONFIG_IR_NUVOTON is not set
CONFIG_IR_REDRAT3=m
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m
CONFIG_IR_IGORPLUGUSB=m
CONFIG_IR_IGUANA=m
CONFIG_IR_TTUSBIR=m
CONFIG_RC_LOOPBACK=m
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_GPIO_TX=m
CONFIG_IR_PWM_TX=m
CONFIG_IR_SUNXI=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SIR=m
CONFIG_RC_XBOX_DVD=m
CONFIG_MEDIA_SUPPORT=y

#
# Multimedia core support
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
CONFIG_MEDIA_RADIO_SUPPORT=y
CONFIG_MEDIA_SDR_SUPPORT=y
# CONFIG_MEDIA_CEC_SUPPORT is not set
# CONFIG_MEDIA_CEC_RC is not set
# CONFIG_CEC_PIN_ERROR_INJ is not set
CONFIG_MEDIA_CONTROLLER=y
CONFIG_MEDIA_CONTROLLER_DVB=y
# CONFIG_MEDIA_CONTROLLER_REQUEST_API is not set
CONFIG_VIDEO_DEV=y
# CONFIG_VIDEO_V4L2_SUBDEV_API is not set
CONFIG_VIDEO_V4L2=y
CONFIG_VIDEO_V4L2_I2C=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_MEM2MEM_DEV=m
CONFIG_V4L2_FWNODE=m
CONFIG_VIDEOBUF_GEN=m
CONFIG_VIDEOBUF_VMALLOC=m
CONFIG_DVB_CORE=y
CONFIG_DVB_MMAP=y
CONFIG_DVB_NET=y
CONFIG_TTPCI_EEPROM=m
CONFIG_DVB_MAX_ADAPTERS=8
CONFIG_DVB_DYNAMIC_MINORS=y
# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
# CONFIG_DVB_ULE_DEBUG is not set

#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_VIDEO_CLASS=m
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
CONFIG_USB_GSPCA=m
CONFIG_USB_M5602=m
CONFIG_USB_STV06XX=m
CONFIG_USB_GL860=m
CONFIG_USB_GSPCA_BENQ=m
CONFIG_USB_GSPCA_CONEX=m
CONFIG_USB_GSPCA_CPIA1=m
CONFIG_USB_GSPCA_DTCS033=m
CONFIG_USB_GSPCA_ETOMS=m
CONFIG_USB_GSPCA_FINEPIX=m
CONFIG_USB_GSPCA_JEILINJ=m
CONFIG_USB_GSPCA_JL2005BCD=m
CONFIG_USB_GSPCA_KINECT=m
CONFIG_USB_GSPCA_KONICA=m
CONFIG_USB_GSPCA_MARS=m
CONFIG_USB_GSPCA_MR97310A=m
CONFIG_USB_GSPCA_NW80X=m
CONFIG_USB_GSPCA_OV519=m
CONFIG_USB_GSPCA_OV534=m
CONFIG_USB_GSPCA_OV534_9=m
CONFIG_USB_GSPCA_PAC207=m
CONFIG_USB_GSPCA_PAC7302=m
CONFIG_USB_GSPCA_PAC7311=m
CONFIG_USB_GSPCA_SE401=m
CONFIG_USB_GSPCA_SN9C2028=m
CONFIG_USB_GSPCA_SN9C20X=m
CONFIG_USB_GSPCA_SONIXB=m
CONFIG_USB_GSPCA_SONIXJ=m
CONFIG_USB_GSPCA_SPCA500=m
CONFIG_USB_GSPCA_SPCA501=m
CONFIG_USB_GSPCA_SPCA505=m
CONFIG_USB_GSPCA_SPCA506=m
CONFIG_USB_GSPCA_SPCA508=m
CONFIG_USB_GSPCA_SPCA561=m
CONFIG_USB_GSPCA_SPCA1528=m
CONFIG_USB_GSPCA_SQ905=m
CONFIG_USB_GSPCA_SQ905C=m
CONFIG_USB_GSPCA_SQ930X=m
CONFIG_USB_GSPCA_STK014=m
CONFIG_USB_GSPCA_STK1135=m
CONFIG_USB_GSPCA_STV0680=m
CONFIG_USB_GSPCA_SUNPLUS=m
CONFIG_USB_GSPCA_T613=m
CONFIG_USB_GSPCA_TOPRO=m
CONFIG_USB_GSPCA_TOUPTEK=m
CONFIG_USB_GSPCA_TV8532=m
CONFIG_USB_GSPCA_VC032X=m
CONFIG_USB_GSPCA_VICAM=m
CONFIG_USB_GSPCA_XIRLINK_CIT=m
CONFIG_USB_GSPCA_ZC3XX=m
CONFIG_USB_PWC=m
# CONFIG_USB_PWC_DEBUG is not set
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_VIDEO_CPIA2=m
CONFIG_USB_ZR364XX=m
CONFIG_USB_STKWEBCAM=m
CONFIG_USB_S2255=m
CONFIG_VIDEO_USBTV=m

#
# Analog TV USB devices
#
CONFIG_VIDEO_PVRUSB2=m
CONFIG_VIDEO_PVRUSB2_SYSFS=y
CONFIG_VIDEO_PVRUSB2_DVB=y
# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
CONFIG_VIDEO_HDPVR=m
# CONFIG_VIDEO_USBVISION is not set
CONFIG_VIDEO_STK1160_COMMON=m
CONFIG_VIDEO_STK1160=m
CONFIG_VIDEO_GO7007=m
CONFIG_VIDEO_GO7007_USB=m
CONFIG_VIDEO_GO7007_LOADER=m
CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m

#
# Analog/digital TV USB devices
#
CONFIG_VIDEO_AU0828=m
CONFIG_VIDEO_AU0828_V4L2=y
CONFIG_VIDEO_AU0828_RC=y
CONFIG_VIDEO_CX231XX=m
CONFIG_VIDEO_CX231XX_RC=y
CONFIG_VIDEO_CX231XX_ALSA=m
CONFIG_VIDEO_CX231XX_DVB=m
CONFIG_VIDEO_TM6000=m
CONFIG_VIDEO_TM6000_ALSA=m
CONFIG_VIDEO_TM6000_DVB=m

#
# Digital TV USB devices
#
CONFIG_DVB_USB=m
# CONFIG_DVB_USB_DEBUG is not set
CONFIG_DVB_USB_DIB3000MC=m
CONFIG_DVB_USB_A800=m
CONFIG_DVB_USB_DIBUSB_MB=m
CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
CONFIG_DVB_USB_DIBUSB_MC=m
CONFIG_DVB_USB_DIB0700=m
CONFIG_DVB_USB_UMT_010=m
CONFIG_DVB_USB_CXUSB=m
# CONFIG_DVB_USB_CXUSB_ANALOG is not set
CONFIG_DVB_USB_M920X=m
CONFIG_DVB_USB_DIGITV=m
CONFIG_DVB_USB_VP7045=m
CONFIG_DVB_USB_VP702X=m
CONFIG_DVB_USB_GP8PSK=m
CONFIG_DVB_USB_NOVA_T_USB2=m
CONFIG_DVB_USB_TTUSB2=m
CONFIG_DVB_USB_DTT200U=m
CONFIG_DVB_USB_OPERA1=m
CONFIG_DVB_USB_AF9005=m
CONFIG_DVB_USB_AF9005_REMOTE=m
CONFIG_DVB_USB_PCTV452E=m
CONFIG_DVB_USB_DW2102=m
CONFIG_DVB_USB_CINERGY_T2=m
CONFIG_DVB_USB_DTV5100=m
CONFIG_DVB_USB_AZ6027=m
CONFIG_DVB_USB_TECHNISAT_USB2=m
CONFIG_DVB_USB_V2=m
CONFIG_DVB_USB_AF9015=m
CONFIG_DVB_USB_AF9035=m
CONFIG_DVB_USB_ANYSEE=m
CONFIG_DVB_USB_AU6610=m
CONFIG_DVB_USB_AZ6007=m
CONFIG_DVB_USB_CE6230=m
CONFIG_DVB_USB_EC168=m
CONFIG_DVB_USB_GL861=m
CONFIG_DVB_USB_LME2510=m
CONFIG_DVB_USB_MXL111SF=m
CONFIG_DVB_USB_RTL28XXU=m
CONFIG_DVB_USB_DVBSKY=m
CONFIG_DVB_USB_ZD1301=m
CONFIG_DVB_TTUSB_BUDGET=m
CONFIG_DVB_TTUSB_DEC=m
CONFIG_SMS_USB_DRV=m
CONFIG_DVB_B2C2_FLEXCOP_USB=m
# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
CONFIG_DVB_AS102=m

#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=m
CONFIG_VIDEO_EM28XX_V4L2=m
CONFIG_VIDEO_EM28XX_ALSA=m
CONFIG_VIDEO_EM28XX_DVB=m
CONFIG_VIDEO_EM28XX_RC=m

#
# Software defined radio USB devices
#
# CONFIG_USB_AIRSPY is not set
# CONFIG_USB_HACKRF is not set
# CONFIG_USB_MSI2500 is not set
# CONFIG_MEDIA_PCI_SUPPORT is not set
# CONFIG_V4L_PLATFORM_DRIVERS is not set
# CONFIG_V4L_MEM2MEM_DRIVERS is not set
# CONFIG_V4L_TEST_DRIVERS is not set
# CONFIG_DVB_PLATFORM_DRIVERS is not set
# CONFIG_SDR_PLATFORM_DRIVERS is not set

#
# Supported MMC/SDIO adapters
#
# CONFIG_SMS_SDIO_DRV is not set
CONFIG_RADIO_ADAPTERS=y
CONFIG_RADIO_TEA575X=m
CONFIG_RADIO_SI470X=m
CONFIG_USB_SI470X=m
CONFIG_I2C_SI470X=m
CONFIG_RADIO_SI4713=m
CONFIG_USB_SI4713=m
CONFIG_PLATFORM_SI4713=m
CONFIG_I2C_SI4713=m
CONFIG_USB_MR800=m
CONFIG_USB_DSBR=m
CONFIG_RADIO_MAXIRADIO=m
CONFIG_RADIO_SHARK=m
CONFIG_RADIO_SHARK2=m
CONFIG_USB_KEENE=m
CONFIG_USB_RAREMONO=m
CONFIG_USB_MA901=m
CONFIG_RADIO_TEA5764=m
CONFIG_RADIO_SAA7706H=m
CONFIG_RADIO_TEF6862=m
CONFIG_RADIO_WL1273=m

#
# Texas Instruments WL128x FM driver (ST based)
#
# end of Texas Instruments WL128x FM driver (ST based)

CONFIG_MEDIA_COMMON_OPTIONS=y

#
# common driver options
#
CONFIG_VIDEO_CX2341X=m
CONFIG_VIDEO_TVEEPROM=m
CONFIG_CYPRESS_FIRMWARE=m
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_DVB_B2C2_FLEXCOP=m
CONFIG_SMS_SIANO_MDTV=m
CONFIG_SMS_SIANO_RC=y

#
# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
#
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
CONFIG_MEDIA_ATTACH=y
CONFIG_VIDEO_IR_I2C=m

#
# I2C Encoders, decoders, sensors and other helper chips
#

#
# Audio decoders, processors and mixers
#
# CONFIG_VIDEO_TVAUDIO is not set
# CONFIG_VIDEO_TDA7432 is not set
# CONFIG_VIDEO_TDA9840 is not set
# CONFIG_VIDEO_TEA6415C is not set
# CONFIG_VIDEO_TEA6420 is not set
CONFIG_VIDEO_MSP3400=m
# CONFIG_VIDEO_CS3308 is not set
# CONFIG_VIDEO_CS5345 is not set
CONFIG_VIDEO_CS53L32A=m
# CONFIG_VIDEO_TLV320AIC23B is not set
CONFIG_VIDEO_UDA1342=m
CONFIG_VIDEO_WM8775=m
# CONFIG_VIDEO_WM8739 is not set
# CONFIG_VIDEO_VP27SMPX is not set
CONFIG_VIDEO_SONY_BTF_MPX=m

#
# RDS decoders
#
# CONFIG_VIDEO_SAA6588 is not set

#
# Video decoders
#
# CONFIG_VIDEO_ADV7183 is not set
# CONFIG_VIDEO_BT819 is not set
# CONFIG_VIDEO_BT856 is not set
# CONFIG_VIDEO_BT866 is not set
# CONFIG_VIDEO_KS0127 is not set
# CONFIG_VIDEO_ML86V7667 is not set
# CONFIG_VIDEO_SAA7110 is not set
CONFIG_VIDEO_SAA711X=m
# CONFIG_VIDEO_TVP514X is not set
CONFIG_VIDEO_TVP5150=m
# CONFIG_VIDEO_TVP7002 is not set
CONFIG_VIDEO_TW2804=m
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=m
# CONFIG_VIDEO_TW9910 is not set
# CONFIG_VIDEO_VPX3220 is not set

#
# Video and audio decoders
#
# CONFIG_VIDEO_SAA717X is not set
CONFIG_VIDEO_CX25840=m

#
# Video encoders
#
# CONFIG_VIDEO_SAA7127 is not set
# CONFIG_VIDEO_SAA7185 is not set
# CONFIG_VIDEO_ADV7170 is not set
# CONFIG_VIDEO_ADV7175 is not set
# CONFIG_VIDEO_ADV7343 is not set
# CONFIG_VIDEO_ADV7393 is not set
# CONFIG_VIDEO_AK881X is not set
# CONFIG_VIDEO_THS8200 is not set

#
# Camera sensor devices
#
CONFIG_VIDEO_OV2640=m
CONFIG_VIDEO_OV2659=m
CONFIG_VIDEO_OV2680=m
CONFIG_VIDEO_OV2685=m
CONFIG_VIDEO_OV6650=m
CONFIG_VIDEO_OV5695=m
CONFIG_VIDEO_OV772X=m
CONFIG_VIDEO_OV7640=m
CONFIG_VIDEO_OV7670=m
CONFIG_VIDEO_OV7740=m
CONFIG_VIDEO_OV9640=m
CONFIG_VIDEO_VS6624=m
CONFIG_VIDEO_MT9M111=m
CONFIG_VIDEO_MT9T112=m
CONFIG_VIDEO_MT9V011=m
CONFIG_VIDEO_MT9V111=m
CONFIG_VIDEO_SR030PC30=m
CONFIG_VIDEO_RJ54N1=m

#
# Lens drivers
#
CONFIG_VIDEO_AD5820=m

#
# Flash devices
#
CONFIG_VIDEO_ADP1653=m
CONFIG_VIDEO_LM3560=m
CONFIG_VIDEO_LM3646=m

#
# Video improvement chips
#
# CONFIG_VIDEO_UPD64031A is not set
# CONFIG_VIDEO_UPD64083 is not set

#
# Audio/Video compression chips
#
# CONFIG_VIDEO_SAA6752HS is not set

#
# SDR tuner chips
#
# CONFIG_SDR_MAX2175 is not set

#
# Miscellaneous helper chips
#
# CONFIG_VIDEO_THS7303 is not set
# CONFIG_VIDEO_M52790 is not set
# CONFIG_VIDEO_I2C is not set
# end of I2C Encoders, decoders, sensors and other helper chips

#
# SPI helper chips
#
# end of SPI helper chips

#
# Media SPI Adapters
#
CONFIG_CXD2880_SPI_DRV=m
# end of Media SPI Adapters

CONFIG_MEDIA_TUNER=y

#
# Customize TV tuners
#
CONFIG_MEDIA_TUNER_SIMPLE=y
CONFIG_MEDIA_TUNER_TDA18250=m
CONFIG_MEDIA_TUNER_TDA8290=y
CONFIG_MEDIA_TUNER_TDA827X=y
CONFIG_MEDIA_TUNER_TDA18271=y
CONFIG_MEDIA_TUNER_TDA9887=y
CONFIG_MEDIA_TUNER_TEA5761=y
CONFIG_MEDIA_TUNER_TEA5767=y
CONFIG_MEDIA_TUNER_MSI001=m
CONFIG_MEDIA_TUNER_MT20XX=y
CONFIG_MEDIA_TUNER_MT2060=m
CONFIG_MEDIA_TUNER_MT2063=m
CONFIG_MEDIA_TUNER_MT2266=m
CONFIG_MEDIA_TUNER_MT2131=m
CONFIG_MEDIA_TUNER_QT1010=m
CONFIG_MEDIA_TUNER_XC2028=y
CONFIG_MEDIA_TUNER_XC5000=y
CONFIG_MEDIA_TUNER_XC4000=y
CONFIG_MEDIA_TUNER_MXL5005S=m
CONFIG_MEDIA_TUNER_MXL5007T=m
CONFIG_MEDIA_TUNER_MC44S803=y
CONFIG_MEDIA_TUNER_MAX2165=m
CONFIG_MEDIA_TUNER_TDA18218=m
CONFIG_MEDIA_TUNER_FC0011=m
CONFIG_MEDIA_TUNER_FC0012=m
CONFIG_MEDIA_TUNER_FC0013=m
CONFIG_MEDIA_TUNER_TDA18212=m
CONFIG_MEDIA_TUNER_E4000=m
CONFIG_MEDIA_TUNER_FC2580=m
CONFIG_MEDIA_TUNER_M88RS6000T=m
CONFIG_MEDIA_TUNER_TUA9001=m
CONFIG_MEDIA_TUNER_SI2157=m
CONFIG_MEDIA_TUNER_IT913X=m
CONFIG_MEDIA_TUNER_R820T=m
CONFIG_MEDIA_TUNER_MXL301RF=m
CONFIG_MEDIA_TUNER_QM1D1C0042=m
CONFIG_MEDIA_TUNER_QM1D1B0004=m
# end of Customize TV tuners

#
# Customise DVB Frontends
#

#
# Multistandard (satellite) frontends
#
CONFIG_DVB_STB0899=m
CONFIG_DVB_STB6100=m
CONFIG_DVB_STV090x=m
CONFIG_DVB_STV0910=m
CONFIG_DVB_STV6110x=m
CONFIG_DVB_STV6111=m
CONFIG_DVB_MXL5XX=m
CONFIG_DVB_M88DS3103=m

#
# Multistandard (cable + terrestrial) frontends
#
CONFIG_DVB_DRXK=m
CONFIG_DVB_TDA18271C2DD=m
CONFIG_DVB_SI2165=m
CONFIG_DVB_MN88472=m
CONFIG_DVB_MN88473=m

#
# DVB-S (satellite) frontends
#
CONFIG_DVB_CX24110=m
CONFIG_DVB_CX24123=m
CONFIG_DVB_MT312=m
CONFIG_DVB_ZL10036=m
CONFIG_DVB_ZL10039=m
CONFIG_DVB_S5H1420=m
CONFIG_DVB_STV0288=m
CONFIG_DVB_STB6000=m
CONFIG_DVB_STV0299=m
CONFIG_DVB_STV6110=m
CONFIG_DVB_STV0900=m
CONFIG_DVB_TDA8083=m
CONFIG_DVB_TDA10086=m
CONFIG_DVB_TDA8261=m
CONFIG_DVB_VES1X93=m
CONFIG_DVB_TUNER_ITD1000=m
CONFIG_DVB_TUNER_CX24113=m
CONFIG_DVB_TDA826X=m
CONFIG_DVB_TUA6100=m
CONFIG_DVB_CX24116=m
CONFIG_DVB_CX24117=m
CONFIG_DVB_CX24120=m
CONFIG_DVB_SI21XX=m
CONFIG_DVB_TS2020=m
CONFIG_DVB_DS3000=m
CONFIG_DVB_MB86A16=m
CONFIG_DVB_TDA10071=m

#
# DVB-T (terrestrial) frontends
#
CONFIG_DVB_SP8870=m
CONFIG_DVB_SP887X=m
CONFIG_DVB_CX22700=m
CONFIG_DVB_CX22702=m
CONFIG_DVB_S5H1432=m
CONFIG_DVB_DRXD=m
CONFIG_DVB_L64781=m
CONFIG_DVB_TDA1004X=m
CONFIG_DVB_NXT6000=m
CONFIG_DVB_MT352=m
CONFIG_DVB_ZL10353=m
CONFIG_DVB_DIB3000MB=m
CONFIG_DVB_DIB3000MC=m
CONFIG_DVB_DIB7000M=m
CONFIG_DVB_DIB7000P=m
CONFIG_DVB_DIB9000=m
CONFIG_DVB_TDA10048=m
CONFIG_DVB_AF9013=m
CONFIG_DVB_EC100=m
CONFIG_DVB_STV0367=m
CONFIG_DVB_CXD2820R=m
CONFIG_DVB_CXD2841ER=m
CONFIG_DVB_RTL2830=m
CONFIG_DVB_RTL2832=m
CONFIG_DVB_RTL2832_SDR=m
CONFIG_DVB_SI2168=m
CONFIG_DVB_AS102_FE=m
CONFIG_DVB_ZD1301_DEMOD=m
CONFIG_DVB_GP8PSK_FE=m
CONFIG_DVB_CXD2880=m

#
# DVB-C (cable) frontends
#
CONFIG_DVB_VES1820=m
CONFIG_DVB_TDA10021=m
CONFIG_DVB_TDA10023=m
CONFIG_DVB_STV0297=m

#
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
#
CONFIG_DVB_NXT200X=m
CONFIG_DVB_OR51211=m
CONFIG_DVB_OR51132=m
CONFIG_DVB_BCM3510=m
CONFIG_DVB_LGDT330X=m
CONFIG_DVB_LGDT3305=m
CONFIG_DVB_LGDT3306A=m
CONFIG_DVB_LG2160=m
CONFIG_DVB_S5H1409=m
CONFIG_DVB_AU8522=m
CONFIG_DVB_AU8522_DTV=m
CONFIG_DVB_AU8522_V4L=m
CONFIG_DVB_S5H1411=m

#
# ISDB-T (terrestrial) frontends
#
CONFIG_DVB_S921=m
CONFIG_DVB_DIB8000=m
CONFIG_DVB_MB86A20S=m

#
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
#
CONFIG_DVB_TC90522=m
CONFIG_DVB_MN88443X=m

#
# Digital terrestrial only tuners/PLL
#
CONFIG_DVB_PLL=m
CONFIG_DVB_TUNER_DIB0070=m
CONFIG_DVB_TUNER_DIB0090=m

#
# SEC control devices for DVB-S
#
CONFIG_DVB_DRX39XYJ=m
CONFIG_DVB_LNBH25=m
CONFIG_DVB_LNBH29=m
CONFIG_DVB_LNBP21=m
CONFIG_DVB_LNBP22=m
CONFIG_DVB_ISL6405=m
CONFIG_DVB_ISL6421=m
CONFIG_DVB_ISL6423=m
CONFIG_DVB_A8293=m
CONFIG_DVB_LGS8GL5=m
CONFIG_DVB_LGS8GXX=m
CONFIG_DVB_ATBM8830=m
CONFIG_DVB_TDA665x=m
CONFIG_DVB_IX2505V=m
CONFIG_DVB_M88RS2000=m
CONFIG_DVB_AF9033=m
CONFIG_DVB_HORUS3A=m
CONFIG_DVB_ASCOT2E=m
CONFIG_DVB_HELENE=m

#
# Common Interface (EN50221) controller drivers
#
CONFIG_DVB_CXD2099=m
CONFIG_DVB_SP2=m

#
# Tools to develop new frontends
#
CONFIG_DVB_DUMMY_FE=m
# end of Customise DVB Frontends

#
# Graphics support
#
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
CONFIG_DRM=y
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_KMS_FB_HELPER=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_TTM=m
CONFIG_DRM_GEM_CMA_HELPER=y
CONFIG_DRM_KMS_CMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=y
CONFIG_DRM_SCHED=m

#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips

#
# ARM devices
#
CONFIG_DRM_HDLCD=m
CONFIG_DRM_HDLCD_SHOW_UNDERRUN=y
CONFIG_DRM_MALI_DISPLAY=m
CONFIG_DRM_KOMEDA=m
# end of ARM devices

# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set

#
# ACP (Audio CoProcessor) Configuration
#
# end of ACP (Audio CoProcessor) Configuration

# CONFIG_DRM_NOUVEAU is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
CONFIG_DRM_ROCKCHIP=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_ROCKCHIP_LVDS=y
CONFIG_ROCKCHIP_RGB=y
CONFIG_ROCKCHIP_RK3066_HDMI=y
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_LVDS is not set
CONFIG_DRM_RCAR_WRITEBACK=y
CONFIG_DRM_SUN4I=y
CONFIG_DRM_SUN4I_HDMI=y
CONFIG_DRM_SUN4I_HDMI_CEC=y
CONFIG_DRM_SUN4I_BACKEND=y
CONFIG_DRM_SUN6I_DSI=y
CONFIG_DRM_SUN8I_DW_HDMI=y
CONFIG_DRM_SUN8I_MIXER=y
CONFIG_DRM_SUN8I_TCON_TOP=y
CONFIG_DRM_QXL=m
# CONFIG_DRM_BOCHS is not set
CONFIG_DRM_VIRTIO_GPU=m
CONFIG_DRM_PANEL=y

#
# Display Panels
#
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
# CONFIG_DRM_PANEL_LVDS is not set
# CONFIG_DRM_PANEL_SIMPLE is not set
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
# CONFIG_DRM_PANEL_LG_LG4573 is not set
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
# CONFIG_DRM_PANEL_ROCKTECH_JH057N00900 is not set
# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_DUMB_VGA_DAC is not set
# CONFIG_DRM_LVDS_ENCODER is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
CONFIG_DRM_ANALOGIX_DP=y
# CONFIG_DRM_I2C_ADV7511 is not set
CONFIG_DRM_DW_HDMI=y
CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
CONFIG_DRM_DW_HDMI_CEC=m
CONFIG_DRM_DW_MIPI_DSI=y
# end of Display Interface Bridges

# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
CONFIG_DRM_MESON=y
CONFIG_DRM_MESON_DW_HDMI=y
# CONFIG_DRM_GM12U320 is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_DRM_PL111 is not set
CONFIG_DRM_LIMA=m
CONFIG_DRM_PANFROST=m
# CONFIG_DRM_LEGACY is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y

#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_BACKLIGHT=m
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
CONFIG_FB_ARMCLCD=y
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_UVESA is not set
CONFIG_FB_EFI=y
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
CONFIG_FB_SIMPLE=y
# CONFIG_FB_SSD1307 is not set
# CONFIG_FB_SM712 is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_L4F00242T03 is not set
# CONFIG_LCD_LMS283GF05 is not set
# CONFIG_LCD_LTV350QV is not set
# CONFIG_LCD_ILI922X is not set
# CONFIG_LCD_ILI9320 is not set
# CONFIG_LCD_TDO24M is not set
# CONFIG_LCD_VGG2432A4 is not set
CONFIG_LCD_PLATFORM=m
# CONFIG_LCD_AMS369FG06 is not set
# CONFIG_LCD_LMS501KF03 is not set
# CONFIG_LCD_HX8357 is not set
# CONFIG_LCD_OTM3225A is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_BACKLIGHT_PWM=m
# CONFIG_BACKLIGHT_PM8941_WLED is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
CONFIG_BACKLIGHT_GPIO=m
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# end of Backlight & LCD device support

CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
# end of Console display driver support

CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
# end of Graphics support

CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=m
CONFIG_SND_SEQ_DEVICE=m
CONFIG_SND_RAWMIDI=m
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_OSSEMUL is not set
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
# CONFIG_SND_DYNAMIC_MINORS is not set
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
CONFIG_SND_VMASTER=y
CONFIG_SND_SEQUENCER=m
CONFIG_SND_SEQ_DUMMY=m
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
CONFIG_SND_SEQ_MIDI_EVENT=m
CONFIG_SND_SEQ_MIDI=m
CONFIG_SND_SEQ_VIRMIDI=m
CONFIG_SND_MPU401_UART=m
CONFIG_SND_AC97_CODEC=m
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
CONFIG_SND_VIRMIDI=m
CONFIG_SND_MTPAV=m
CONFIG_SND_SERIAL_U16550=m
CONFIG_SND_MPU401=m
# CONFIG_SND_AC97_POWER_SAVE is not set
# CONFIG_SND_PCI is not set

#
# HD-Audio
#
# end of HD-Audio

CONFIG_SND_HDA_PREALLOC_SIZE=2048
# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
CONFIG_SND_BCD2000=m
CONFIG_SND_USB_LINE6=m
CONFIG_SND_USB_POD=m
CONFIG_SND_USB_PODHD=m
CONFIG_SND_USB_TONEPORT=m
CONFIG_SND_USB_VARIAX=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
# CONFIG_SND_SOC_AMD_ACP is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_DESIGNWARE_I2S is not set

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
# CONFIG_SND_SOC_FSL_SAI is not set
# CONFIG_SND_SOC_FSL_AUDMIX is not set
# CONFIG_SND_SOC_FSL_SSI is not set
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
# CONFIG_SND_SOC_FSL_MICFIL is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs

# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set

#
# ASoC support for Amlogic platforms
#
CONFIG_SND_MESON_AXG_FIFO=m
CONFIG_SND_MESON_AXG_FRDDR=m
CONFIG_SND_MESON_AXG_TODDR=m
CONFIG_SND_MESON_AXG_TDM_FORMATTER=m
CONFIG_SND_MESON_AXG_TDM_INTERFACE=m
CONFIG_SND_MESON_AXG_TDMIN=m
CONFIG_SND_MESON_AXG_TDMOUT=m
CONFIG_SND_MESON_AXG_SOUND_CARD=m
CONFIG_SND_MESON_AXG_SPDIFOUT=m
CONFIG_SND_MESON_AXG_SPDIFIN=m
CONFIG_SND_MESON_AXG_PDM=m
CONFIG_SND_MESON_CARD_UTILS=m
CONFIG_SND_MESON_CODEC_GLUE=m
CONFIG_SND_MESON_G12A_TOHDMITX=m
# end of ASoC support for Amlogic platforms

CONFIG_SND_SOC_MESON_GX=m
CONFIG_SND_SOC_MESON_GX_I2S=m
CONFIG_SND_SOC_MESON_GX_SPDIF=m
CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_ROCKCHIP_I2S=m
CONFIG_SND_SOC_ROCKCHIP_PDM=m
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
CONFIG_SND_SOC_ROCKCHIP_RT5645=m
CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m
CONFIG_SND_SOC_RK3399_GRU_SOUND=m
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set

#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support

#
# Allwinner SoC Audio support
#
CONFIG_SND_SUN4I_CODEC=m
CONFIG_SND_SUN8I_CODEC=m
CONFIG_SND_SUN8I_CODEC_ANALOG=m
CONFIG_SND_SUN50I_CODEC_ANALOG=m
CONFIG_SND_SUN4I_I2S=m
CONFIG_SND_SUN4I_SPDIF=m
CONFIG_SND_SUN8I_ADDA_PR_REGMAP=m
# end of Allwinner SoC Audio support

# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# CONFIG_SND_SOC_XTFPGA_I2S is not set
# CONFIG_ZX_TDM is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
CONFIG_SND_SOC_AC97_CODEC=m
# CONFIG_SND_SOC_ADAU1701 is not set
# CONFIG_SND_SOC_ADAU1761_I2C is not set
# CONFIG_SND_SOC_ADAU1761_SPI is not set
# CONFIG_SND_SOC_ADAU7002 is not set
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_AK4118 is not set
# CONFIG_SND_SOC_AK4458 is not set
# CONFIG_SND_SOC_AK4554 is not set
# CONFIG_SND_SOC_AK4613 is not set
# CONFIG_SND_SOC_AK4642 is not set
# CONFIG_SND_SOC_AK5386 is not set
# CONFIG_SND_SOC_AK5558 is not set
# CONFIG_SND_SOC_ALC5623 is not set
# CONFIG_SND_SOC_BD28623 is not set
# CONFIG_SND_SOC_BT_SCO is not set
# CONFIG_SND_SOC_CS35L32 is not set
# CONFIG_SND_SOC_CS35L33 is not set
# CONFIG_SND_SOC_CS35L34 is not set
# CONFIG_SND_SOC_CS35L35 is not set
# CONFIG_SND_SOC_CS35L36 is not set
# CONFIG_SND_SOC_CS42L42 is not set
# CONFIG_SND_SOC_CS42L51_I2C is not set
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_CS42L73 is not set
# CONFIG_SND_SOC_CS4265 is not set
# CONFIG_SND_SOC_CS4270 is not set
# CONFIG_SND_SOC_CS4271_I2C is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_CS42XX8_I2C is not set
# CONFIG_SND_SOC_CS43130 is not set
# CONFIG_SND_SOC_CS4341 is not set
# CONFIG_SND_SOC_CS4349 is not set
# CONFIG_SND_SOC_CS53L30 is not set
# CONFIG_SND_SOC_CX2072X is not set
CONFIG_SND_SOC_DA7219=m
CONFIG_SND_SOC_DMIC=m
CONFIG_SND_SOC_HDMI_CODEC=y
# CONFIG_SND_SOC_ES7134 is not set
# CONFIG_SND_SOC_ES7241 is not set
# CONFIG_SND_SOC_ES8316 is not set
CONFIG_SND_SOC_ES8328=m
CONFIG_SND_SOC_ES8328_I2C=m
CONFIG_SND_SOC_ES8328_SPI=m
# CONFIG_SND_SOC_GTM601 is not set
CONFIG_SND_SOC_INNO_RK3036=m
# CONFIG_SND_SOC_MAX98088 is not set
CONFIG_SND_SOC_MAX98090=m
CONFIG_SND_SOC_MAX98357A=m
# CONFIG_SND_SOC_MAX98504 is not set
# CONFIG_SND_SOC_MAX9867 is not set
# CONFIG_SND_SOC_MAX98927 is not set
# CONFIG_SND_SOC_MAX98373 is not set
# CONFIG_SND_SOC_MAX9860 is not set
# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set
# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
# CONFIG_SND_SOC_PCM1681 is not set
# CONFIG_SND_SOC_PCM1789_I2C is not set
# CONFIG_SND_SOC_PCM179X_I2C is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_I2C is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3060_I2C is not set
# CONFIG_SND_SOC_PCM3060_SPI is not set
# CONFIG_SND_SOC_PCM3168A_I2C is not set
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM512x_I2C is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
CONFIG_SND_SOC_RK3328=m
CONFIG_SND_SOC_RL6231=m
CONFIG_SND_SOC_RT5514=m
CONFIG_SND_SOC_RT5514_SPI=m
# CONFIG_SND_SOC_RT5616 is not set
# CONFIG_SND_SOC_RT5631 is not set
CONFIG_SND_SOC_RT5645=m
# CONFIG_SND_SOC_SGTL5000 is not set
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set
CONFIG_SND_SOC_SPDIF=m
# CONFIG_SND_SOC_SSM2305 is not set
# CONFIG_SND_SOC_SSM2602_SPI is not set
# CONFIG_SND_SOC_SSM2602_I2C is not set
# CONFIG_SND_SOC_SSM4567 is not set
# CONFIG_SND_SOC_STA32X is not set
# CONFIG_SND_SOC_STA350 is not set
# CONFIG_SND_SOC_STI_SAS is not set
# CONFIG_SND_SOC_TAS2552 is not set
# CONFIG_SND_SOC_TAS5086 is not set
# CONFIG_SND_SOC_TAS571X is not set
# CONFIG_SND_SOC_TAS5720 is not set
# CONFIG_SND_SOC_TAS6424 is not set
# CONFIG_SND_SOC_TDA7419 is not set
# CONFIG_SND_SOC_TFA9879 is not set
# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC31XX is not set
# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_TLV320AIC3X is not set
CONFIG_SND_SOC_TS3A227E=m
# CONFIG_SND_SOC_TSCS42XX is not set
# CONFIG_SND_SOC_TSCS454 is not set
# CONFIG_SND_SOC_UDA1334 is not set
# CONFIG_SND_SOC_WM8510 is not set
# CONFIG_SND_SOC_WM8523 is not set
# CONFIG_SND_SOC_WM8524 is not set
# CONFIG_SND_SOC_WM8580 is not set
# CONFIG_SND_SOC_WM8711 is not set
# CONFIG_SND_SOC_WM8728 is not set
# CONFIG_SND_SOC_WM8731 is not set
# CONFIG_SND_SOC_WM8737 is not set
# CONFIG_SND_SOC_WM8741 is not set
# CONFIG_SND_SOC_WM8750 is not set
# CONFIG_SND_SOC_WM8753 is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8776 is not set
# CONFIG_SND_SOC_WM8782 is not set
# CONFIG_SND_SOC_WM8804_I2C is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_WM8903 is not set
# CONFIG_SND_SOC_WM8904 is not set
# CONFIG_SND_SOC_WM8960 is not set
# CONFIG_SND_SOC_WM8962 is not set
# CONFIG_SND_SOC_WM8974 is not set
# CONFIG_SND_SOC_WM8978 is not set
# CONFIG_SND_SOC_WM8985 is not set
# CONFIG_SND_SOC_ZX_AUD96P22 is not set
# CONFIG_SND_SOC_MAX9759 is not set
# CONFIG_SND_SOC_MT6351 is not set
# CONFIG_SND_SOC_MT6358 is not set
# CONFIG_SND_SOC_NAU8540 is not set
# CONFIG_SND_SOC_NAU8810 is not set
# CONFIG_SND_SOC_NAU8822 is not set
# CONFIG_SND_SOC_NAU8824 is not set
# CONFIG_SND_SOC_TPA6130A2 is not set
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_AC97_BUS=y

#
# HID support
#
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=m
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
CONFIG_HID_A4TECH=m
CONFIG_HID_ACCUTOUCH=m
CONFIG_HID_ACRUX=m
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=m
CONFIG_HID_APPLEIR=m
CONFIG_HID_ASUS=m
CONFIG_HID_AUREAL=m
CONFIG_HID_BELKIN=m
CONFIG_HID_BETOP_FF=m
CONFIG_HID_BIGBEN_FF=m
CONFIG_HID_CHERRY=m
CONFIG_HID_CHICONY=m
CONFIG_HID_CORSAIR=m
CONFIG_HID_COUGAR=m
CONFIG_HID_MACALLY=m
CONFIG_HID_PRODIKEYS=m
CONFIG_HID_CMEDIA=m
CONFIG_HID_CP2112=m
CONFIG_HID_CREATIVE_SB0540=m
CONFIG_HID_CYPRESS=m
CONFIG_HID_DRAGONRISE=m
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=m
CONFIG_HID_ELAN=m
CONFIG_HID_ELECOM=m
CONFIG_HID_ELO=m
CONFIG_HID_EZKEY=m
CONFIG_HID_GEMBIRD=m
CONFIG_HID_GFRM=m
CONFIG_HID_HOLTEK=m
CONFIG_HOLTEK_FF=y
CONFIG_HID_GT683R=m
CONFIG_HID_KEYTOUCH=m
CONFIG_HID_KYE=m
CONFIG_HID_UCLOGIC=m
CONFIG_HID_WALTOP=m
CONFIG_HID_VIEWSONIC=m
CONFIG_HID_GYRATION=m
CONFIG_HID_ICADE=m
CONFIG_HID_ITE=m
CONFIG_HID_JABRA=m
CONFIG_HID_TWINHAN=m
CONFIG_HID_KENSINGTON=m
CONFIG_HID_LCPOWER=m
CONFIG_HID_LED=m
CONFIG_HID_LENOVO=m
CONFIG_HID_LOGITECH=m
CONFIG_HID_LOGITECH_DJ=m
CONFIG_HID_LOGITECH_HIDPP=m
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
CONFIG_HID_MAGICMOUSE=m
CONFIG_HID_MALTRON=m
CONFIG_HID_MAYFLASH=m
CONFIG_HID_REDRAGON=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
CONFIG_HID_MULTITOUCH=m
CONFIG_HID_NTI=m
CONFIG_HID_NTRIG=m
CONFIG_HID_ORTEK=m
CONFIG_HID_PANTHERLORD=m
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PENMOUNT=m
CONFIG_HID_PETALYNX=m
CONFIG_HID_PICOLCD=m
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
CONFIG_HID_PICOLCD_LCD=y
CONFIG_HID_PICOLCD_LEDS=y
# CONFIG_HID_PICOLCD_CIR is not set
CONFIG_HID_PLANTRONICS=m
CONFIG_HID_PRIMAX=m
CONFIG_HID_RETRODE=m
CONFIG_HID_ROCCAT=m
CONFIG_HID_SAITEK=m
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SONY=y
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=m
CONFIG_HID_STEAM=m
CONFIG_HID_STEELSERIES=m
CONFIG_HID_SUNPLUS=m
CONFIG_HID_RMI=m
CONFIG_HID_GREENASIA=m
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=m
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TIVO=m
CONFIG_HID_TOPSEED=m
CONFIG_HID_THINGM=m
CONFIG_HID_THRUSTMASTER=m
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_UDRAW_PS3=m
CONFIG_HID_U2FZERO=m
CONFIG_HID_WACOM=m
CONFIG_HID_WIIMOTE=m
CONFIG_HID_XINMO=m
CONFIG_HID_ZEROPLUS=m
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=m
CONFIG_HID_SENSOR_HUB=m
CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
CONFIG_HID_ALPS=m
# end of Special HID drivers

#
# USB HID support
#
CONFIG_USB_HID=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
# end of USB HID support

#
# I2C HID support
#
CONFIG_I2C_HID=m
# end of I2C HID support
# end of HID support

CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_LED_TRIG=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_CONN_GPIO=m
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
CONFIG_USB_OTG_FSM=m
CONFIG_USB_LEDS_TRIGGER_USBPORT=m
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=y

#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=m
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_XHCI_SUNXI=m
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_EHCI_FSL=m
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OXU210HP_HCD=m
CONFIG_USB_ISP116X_HCD=m
CONFIG_USB_FOTG210_HCD=m
CONFIG_USB_MAX3421_HCD=m
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PCI=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_UHCI_HCD=m
CONFIG_USB_U132_HCD=m
CONFIG_USB_SL811_HCD=m
CONFIG_USB_SL811_HCD_ISO=y
CONFIG_USB_R8A66597_HCD=m
CONFIG_USB_HCD_BCMA=m
CONFIG_USB_HCD_SSB=m
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=y
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
CONFIG_USB_STORAGE_REALTEK=m
CONFIG_REALTEK_AUTOPM=y
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_FREECOM=m
CONFIG_USB_STORAGE_ISD200=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_STORAGE_ALAUDA=m
CONFIG_USB_STORAGE_ONETOUCH=m
CONFIG_USB_STORAGE_KARMA=m
CONFIG_USB_STORAGE_CYPRESS_ATACB=m
CONFIG_USB_STORAGE_ENE_UB6250=m
# CONFIG_USB_UAS is not set

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
CONFIG_USB_MICROTEK=m
CONFIG_USBIP_CORE=m
CONFIG_USBIP_VHCI_HCD=m
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=m
CONFIG_USBIP_VUDC=m
# CONFIG_USBIP_DEBUG is not set
CONFIG_USB_CDNS3=m
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_USB_CDNS3_PCI_WRAP=m
CONFIG_USB_MUSB_HDRC=m
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y

#
# Platform Glue Layer
#

#
# MUSB DMA mode
#
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_ULPI=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y

#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=y
# CONFIG_USB_DWC3_HAPS is not set
CONFIG_USB_DWC3_MESON_G12A=y
CONFIG_USB_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
# CONFIG_USB_DWC2_PCI is not set
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
CONFIG_USB_CHIPIDEA=m
CONFIG_USB_CHIPIDEA_OF=m
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_ISP1760=m
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_ISP1761_UDC=y
# CONFIG_USB_ISP1760_HOST_ROLE is not set
# CONFIG_USB_ISP1760_GADGET_ROLE is not set
CONFIG_USB_ISP1760_DUAL_ROLE=y

#
# USB port drivers
#
CONFIG_USB_SERIAL=m
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=m
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=m
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=m
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=m
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_F81232=m
CONFIG_USB_SERIAL_F8153X=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=m
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_METRO=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MXUPORT=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=m
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=m
CONFIG_USB_SERIAL_QUALCOMM=m
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
# CONFIG_USB_SERIAL_SAFE_PADDED is not set
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
CONFIG_USB_SERIAL_SYMBOL=m
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_XIRCOM=m
CONFIG_USB_SERIAL_WWAN=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=m
CONFIG_USB_SERIAL_XSENS_MT=m
CONFIG_USB_SERIAL_WISHBONE=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_SERIAL_QT2=m
CONFIG_USB_SERIAL_UPD78F0730=m
CONFIG_USB_SERIAL_DEBUG=m

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
CONFIG_USB_CYPRESS_CY7C63=m
CONFIG_USB_CYTHERM=m
CONFIG_USB_IDMOUSE=m
CONFIG_USB_FTDI_ELAN=m
CONFIG_USB_APPLEDISPLAY=m
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
CONFIG_USB_TEST=m
CONFIG_USB_EHSET_TEST_FIXTURE=m
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=m
CONFIG_USB_HUB_USB251XB=m
CONFIG_USB_HSIC_USB3503=m
CONFIG_USB_HSIC_USB4604=m
CONFIG_USB_LINK_LAYER_TEST=m
CONFIG_USB_CHAOSKEY=m

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
# CONFIG_NOP_USB_XCEIV is not set
CONFIG_USB_GPIO_VBUS=m
# CONFIG_USB_ISP1301 is not set
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set

#
# USB Peripheral Controller
#
CONFIG_USB_FOTG210_UDC=m
CONFIG_USB_GR_UDC=m
CONFIG_USB_R8A66597=m
CONFIG_USB_PXA27X=m
CONFIG_USB_MV_UDC=m
CONFIG_USB_MV_U3D=m
CONFIG_USB_SNP_CORE=m
CONFIG_USB_SNP_UDC_PLAT=m
CONFIG_USB_M66592=m
CONFIG_USB_BDC_UDC=m

#
# Platform Support
#
CONFIG_USB_AMD5536UDC=m
CONFIG_USB_NET2272=m
CONFIG_USB_NET2272_DMA=y
CONFIG_USB_NET2280=m
CONFIG_USB_GOKU=m
CONFIG_USB_EG20T=m
CONFIG_USB_GADGET_XILINX=m
CONFIG_USB_DUMMY_HCD=m
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=m
CONFIG_USB_F_ACM=m
CONFIG_USB_F_SS_LB=m
CONFIG_USB_U_SERIAL=m
CONFIG_USB_U_ETHER=m
CONFIG_USB_U_AUDIO=m
CONFIG_USB_F_SERIAL=m
CONFIG_USB_F_OBEX=m
CONFIG_USB_F_NCM=m
CONFIG_USB_F_ECM=m
CONFIG_USB_F_PHONET=m
CONFIG_USB_F_EEM=m
CONFIG_USB_F_SUBSET=m
CONFIG_USB_F_RNDIS=m
CONFIG_USB_F_MASS_STORAGE=m
CONFIG_USB_F_FS=m
CONFIG_USB_F_UAC1=m
CONFIG_USB_F_UAC1_LEGACY=m
CONFIG_USB_F_UAC2=m
CONFIG_USB_F_UVC=m
CONFIG_USB_F_MIDI=m
CONFIG_USB_F_HID=m
CONFIG_USB_F_PRINTER=m
CONFIG_USB_F_TCM=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_PHONET=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_LB_SS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y
CONFIG_USB_CONFIGFS_F_TCM=y
CONFIG_USB_ZERO=m
CONFIG_USB_ZERO_HNPTEST=y
CONFIG_USB_AUDIO=m
CONFIG_GADGET_UAC1=y
CONFIG_GADGET_UAC1_LEGACY=y
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
CONFIG_USB_FUNCTIONFS_ETH=y
CONFIG_USB_FUNCTIONFS_RNDIS=y
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_GADGET_TARGET=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_NOKIA=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_G_HID=m
CONFIG_USB_G_DBGP=m
# CONFIG_USB_G_DBGP_PRINTK is not set
CONFIG_USB_G_DBGP_SERIAL=y
CONFIG_USB_G_WEBCAM=m
CONFIG_TYPEC=m
CONFIG_TYPEC_TCPM=m
CONFIG_TYPEC_TCPCI=m
CONFIG_TYPEC_RT1711H=m
CONFIG_TYPEC_FUSB302=m
CONFIG_TYPEC_UCSI=m
CONFIG_UCSI_CCG=m
# CONFIG_UCSI_ACPI is not set
CONFIG_TYPEC_TPS6598X=m

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
CONFIG_TYPEC_MUX_PI3USB30532=m
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
CONFIG_TYPEC_DP_ALTMODE=m
CONFIG_TYPEC_NVIDIA_ALTMODE=m
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
# CONFIG_PWRSEQ_SD8787 is not set
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_ARMMMCI is not set
# CONFIG_MMC_SDHCI is not set
CONFIG_MMC_MESON_GX=y
# CONFIG_MMC_MESON_MX_SDIO is not set
# CONFIG_MMC_TIFM_SD is not set
# CONFIG_MMC_SPI is not set
# CONFIG_MMC_CB710 is not set
# CONFIG_MMC_VIA_SDMMC is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
# CONFIG_MMC_DW_BLUEFIELD is not set
# CONFIG_MMC_DW_EXYNOS is not set
# CONFIG_MMC_DW_HI3798CV200 is not set
# CONFIG_MMC_DW_K3 is not set
# CONFIG_MMC_DW_PCI is not set
CONFIG_MMC_DW_ROCKCHIP=y
# CONFIG_MMC_VUB300 is not set
# CONFIG_MMC_USHC is not set
# CONFIG_MMC_USDHI6ROL0 is not set
# CONFIG_MMC_REALTEK_USB is not set
CONFIG_MMC_SUNXI=y
# CONFIG_MMC_CQHCI is not set
# CONFIG_MMC_TOSHIBA_PCI is not set
# CONFIG_MMC_MTK is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
# CONFIG_LEDS_CLASS_FLASH is not set
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set

#
# LED drivers
#
# CONFIG_LEDS_AN30259A is not set
# CONFIG_LEDS_BCM6328 is not set
# CONFIG_LEDS_BCM6358 is not set
# CONFIG_LEDS_CR0014114 is not set
# CONFIG_LEDS_LM3530 is not set
# CONFIG_LEDS_LM3532 is not set
# CONFIG_LEDS_LM3642 is not set
# CONFIG_LEDS_LM3692X is not set
# CONFIG_LEDS_PCA9532 is not set
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP3952 is not set
# CONFIG_LEDS_LP5521 is not set
# CONFIG_LEDS_LP5523 is not set
# CONFIG_LEDS_LP5562 is not set
# CONFIG_LEDS_LP8501 is not set
# CONFIG_LEDS_LP8860 is not set
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_PCA963X is not set
# CONFIG_LEDS_DAC124S085 is not set
CONFIG_LEDS_PWM=y
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_LT3593 is not set
CONFIG_LEDS_TCA6507=y
# CONFIG_LEDS_TLC591XX is not set
# CONFIG_LEDS_LM355x is not set
# CONFIG_LEDS_IS31FL319X is not set
# CONFIG_LEDS_IS31FL32XX is not set

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
# CONFIG_LEDS_BLINKM is not set
CONFIG_LEDS_SYSCON=y
# CONFIG_LEDS_MLXREG is not set
CONFIG_LEDS_USER=y
# CONFIG_LEDS_SPI_BYTE is not set
# CONFIG_LEDS_TI_LMU_COMMON is not set

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=m
# CONFIG_LEDS_TRIGGER_CPU is not set
CONFIG_LEDS_TRIGGER_ACTIVITY=m
CONFIG_LEDS_TRIGGER_GPIO=m
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=m
CONFIG_LEDS_TRIGGER_CAMERA=m
# CONFIG_LEDS_TRIGGER_PANIC is not set
CONFIG_LEDS_TRIGGER_NETDEV=m
CONFIG_LEDS_TRIGGER_PATTERN=m
CONFIG_LEDS_TRIGGER_AUDIO=m
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
# CONFIG_EDAC_DEBUG is not set
# CONFIG_EDAC_GHES is not set
# CONFIG_EDAC_THUNDERX is not set
# CONFIG_EDAC_XGENE is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
CONFIG_RTC_DRV_TEST=m

#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_ABB5ZES3 is not set
# CONFIG_RTC_DRV_ABEOZ9 is not set
# CONFIG_RTC_DRV_ABX80X is not set
CONFIG_RTC_DRV_AC100=y
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
CONFIG_RTC_DRV_HYM8563=m
# CONFIG_RTC_DRV_MAX6900 is not set
CONFIG_RTC_DRV_MESON_VRTC=y
CONFIG_RTC_DRV_RK808=y
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_ISL12026 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8523 is not set
# CONFIG_RTC_DRV_PCF85063 is not set
# CONFIG_RTC_DRV_PCF85363 is not set
CONFIG_RTC_DRV_PCF8563=m
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8010 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV3028 is not set
# CONFIG_RTC_DRV_RV8803 is not set
# CONFIG_RTC_DRV_SD3078 is not set

#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RX6110 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_MCP795 is not set
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_PCF2127 is not set
# CONFIG_RTC_DRV_RV3029C2 is not set

#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1685_FAMILY is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_DS2404 is not set
# CONFIG_RTC_DRV_EFI is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
# CONFIG_RTC_DRV_ZYNQMP is not set

#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_PL030=y
CONFIG_RTC_DRV_PL031=y
CONFIG_RTC_DRV_SUN6I=y
# CONFIG_RTC_DRV_CADENCE is not set
# CONFIG_RTC_DRV_FTRTC010 is not set
# CONFIG_RTC_DRV_SNVS is not set
# CONFIG_RTC_DRV_R7301 is not set

#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
CONFIG_AMBA_PL08X=y
# CONFIG_BCM_SBA_RAID is not set
CONFIG_DMA_SUN6I=y
# CONFIG_DW_AXI_DMAC is not set
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_MV_XOR_V2 is not set
CONFIG_PL330_DMA=y
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
# CONFIG_QCOM_HIDMA_MGMT is not set
# CONFIG_QCOM_HIDMA is not set
CONFIG_DW_DMAC_CORE=y
CONFIG_DW_DMAC=y
# CONFIG_DW_DMAC_PCI is not set
CONFIG_DW_EDMA=y
# CONFIG_DW_EDMA_PCIE is not set

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
# CONFIG_DMABUF_SELFTESTS is not set
# end of DMABUF options

CONFIG_AUXDISPLAY=y
CONFIG_HD44780=m
CONFIG_IMG_ASCII_LCD=m
CONFIG_HT16K33=m
CONFIG_OPENVFD=m
# CONFIG_PANEL_CHANGE_MESSAGE is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_CHARLCD=m
# CONFIG_UIO is not set
# CONFIG_VFIO is not set
CONFIG_VIRT_DRIVERS=y
CONFIG_VIRTIO=m
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=m
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set

#
# Microsoft Hyper-V guest support
#
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
CONFIG_STAGING=y
CONFIG_PRISM2_USB=m
# CONFIG_COMEDI is not set
CONFIG_RTL8192U=m
CONFIG_RTLLIB=m
CONFIG_RTLLIB_CRYPTO_CCMP=m
CONFIG_RTLLIB_CRYPTO_TKIP=m
CONFIG_RTLLIB_CRYPTO_WEP=m
# CONFIG_RTL8192E is not set
CONFIG_RTL8723BS=m
CONFIG_R8712U=m
CONFIG_R8188EU=m
CONFIG_88EU_AP_MODE=y
# CONFIG_RTS5208 is not set
CONFIG_VT6655=m
CONFIG_VT6656=m

#
# IIO staging drivers
#

#
# Accelerometers
#
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16240 is not set
# end of Accelerometers

#
# Analog to digital converters
#
# CONFIG_AD7816 is not set
# CONFIG_AD7192 is not set
# CONFIG_AD7280 is not set
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
# CONFIG_ADT7316 is not set
# end of Analog digital bi-direction converters

#
# Capacitance to digital converters
#
# CONFIG_AD7150 is not set
# CONFIG_AD7746 is not set
# end of Capacitance to digital converters

#
# Direct Digital Synthesis
#
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
# CONFIG_AD5933 is not set
# end of Network Analyzer, Impedance Converters

#
# Active energy metering IC
#
# CONFIG_ADE7854 is not set
# end of Active energy metering IC

#
# Resolver to digital converters
#
# CONFIG_AD2S1210 is not set
# end of Resolver to digital converters
# end of IIO staging drivers

# CONFIG_FB_SM750 is not set

#
# Speakup console speech
#
# CONFIG_SPEAKUP is not set
# end of Speakup console speech

CONFIG_STAGING_MEDIA=y
CONFIG_VIDEO_MESON_VDEC=m
CONFIG_VIDEO_SUNXI=y

#
# soc_camera sensor drivers
#

#
# Android
#
# end of Android

# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
# CONFIG_GS_FPGABOOT is not set
# CONFIG_UNISYSSPAR is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
# CONFIG_FB_TFT is not set
# CONFIG_WILC1000_SDIO is not set
# CONFIG_WILC1000_SPI is not set
# CONFIG_MOST is not set
# CONFIG_KS7010 is not set
# CONFIG_PI433 is not set

#
# Gasket devices
#
# CONFIG_STAGING_GASKET_FRAMEWORK is not set
# end of Gasket devices

# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_USB_WUSB_CBAF is not set
# CONFIG_UWB is not set
CONFIG_EXFAT_FS=y
CONFIG_EXFAT_DONT_MOUNT_VFAT=y
CONFIG_EXFAT_DISCARD=y
# CONFIG_EXFAT_DELAYED_SYNC is not set
# CONFIG_EXFAT_KERNEL_DEBUG is not set
# CONFIG_EXFAT_DEBUG_MSG is not set
CONFIG_EXFAT_DEFAULT_CODEPAGE=437
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_QLGE is not set
# CONFIG_GOLDFISH is not set
# CONFIG_MFD_CROS_EC is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
CONFIG_SURFACE_PLATFORMS=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Common Clock Framework
#
CONFIG_COMMON_CLK_VERSATILE=y
CONFIG_CLK_SP810=y
CONFIG_CLK_VEXPRESS_OSC=y
# CONFIG_CLK_HSDK is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
# CONFIG_CLK_QORIQ is not set
# CONFIG_COMMON_CLK_XGENE is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_VC5 is not set
CONFIG_COMMON_CLK_FIXED_MMIO=y

#
# Clock support for Amlogic platforms
#
CONFIG_COMMON_CLK_MESON_REGMAP=y
CONFIG_COMMON_CLK_MESON_DUALDIV=y
CONFIG_COMMON_CLK_MESON_MPLL=y
CONFIG_COMMON_CLK_MESON_PHASE=y
CONFIG_COMMON_CLK_MESON_PLL=y
CONFIG_COMMON_CLK_MESON_SCLK_DIV=y
CONFIG_COMMON_CLK_MESON_VID_PLL_DIV=y
CONFIG_COMMON_CLK_MESON_AO_CLKC=y
CONFIG_COMMON_CLK_MESON_EE_CLKC=y
CONFIG_COMMON_CLK_MESON_CPU_DYNDIV=y
CONFIG_COMMON_CLK_GXBB=y
CONFIG_COMMON_CLK_AXG=y
CONFIG_COMMON_CLK_AXG_AUDIO=y
CONFIG_COMMON_CLK_G12A=y
# end of Clock support for Amlogic platforms

CONFIG_CLK_SUNXI=y
CONFIG_CLK_SUNXI_CLOCKS=y
CONFIG_CLK_SUNXI_PRCM_SUN6I=y
CONFIG_CLK_SUNXI_PRCM_SUN8I=y
CONFIG_CLK_SUNXI_PRCM_SUN9I=y
CONFIG_SUNXI_CCU=y
CONFIG_SUN50I_A64_CCU=y
CONFIG_SUN50I_H6_CCU=y
CONFIG_SUN50I_H6_R_CCU=y
CONFIG_SUN8I_A83T_CCU=y
CONFIG_SUN8I_H3_CCU=y
CONFIG_SUN8I_DE2_CCU=y
CONFIG_SUN8I_R_CCU=y
# end of Common Clock Framework

CONFIG_HWSPINLOCK=y

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_ACPI=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
# end of Clock Source drivers

CONFIG_MAILBOX=y
CONFIG_ARM_MHU=y
CONFIG_PLATFORM_MHU=y
CONFIG_PL320_MBOX=y
CONFIG_ROCKCHIP_MBOX=y
# CONFIG_PCC is not set
CONFIG_ALTERA_MBOX=m
# CONFIG_MAILBOX_TEST is not set
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_ARM_SMMU=y
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
CONFIG_ARM_SMMU_V3=y

#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=m
# CONFIG_RPMSG_CHAR is not set
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
CONFIG_RPMSG_VIRTIO=m
# end of Rpmsg drivers

# CONFIG_SOUNDWIRE is not set

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
CONFIG_MESON_CANVAS=y
CONFIG_MESON_CLK_MEASURE=y
CONFIG_MESON_GX_SOCINFO=y
CONFIG_MESON_GX_PM_DOMAINS=y
CONFIG_MESON_EE_PM_DOMAINS=y
# CONFIG_MESON_MX_SOCINFO is not set
# end of Amlogic SoC drivers

#
# Aspeed SoC drivers
#
# end of Aspeed SoC drivers

#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
# end of NXP/Freescale QorIQ SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Qualcomm SoC drivers
#
# end of Qualcomm SoC drivers

CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_SUNXI_SRAM=y
# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# CONFIG_XILINX_VCU is not set
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=m
CONFIG_DEVFREQ_GOV_USERSPACE=m
CONFIG_DEVFREQ_GOV_PASSIVE=m

#
# DEVFREQ Drivers
#
CONFIG_ARM_RK3399_DMC_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
# CONFIG_EXTCON_ADC_JACK is not set
# CONFIG_EXTCON_FSA9480 is not set
CONFIG_EXTCON_GPIO=m
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_PTN5150 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
CONFIG_EXTCON_USB_GPIO=m
CONFIG_MEMORY=y
CONFIG_ARM_PL172_MPMC=m
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m

#
# Accelerometers
#
# CONFIG_ADIS16201 is not set
# CONFIG_ADIS16209 is not set
# CONFIG_ADXL345_I2C is not set
# CONFIG_ADXL345_SPI is not set
# CONFIG_ADXL372_SPI is not set
# CONFIG_ADXL372_I2C is not set
# CONFIG_BMA180 is not set
# CONFIG_BMA220 is not set
# CONFIG_BMC150_ACCEL is not set
# CONFIG_DA280 is not set
# CONFIG_DA311 is not set
# CONFIG_DMARD06 is not set
# CONFIG_DMARD09 is not set
# CONFIG_DMARD10 is not set
# CONFIG_HID_SENSOR_ACCEL_3D is not set
# CONFIG_IIO_ST_ACCEL_3AXIS is not set
# CONFIG_KXSD9 is not set
# CONFIG_KXCJK1013 is not set
# CONFIG_MC3230 is not set
# CONFIG_MMA7455_I2C is not set
# CONFIG_MMA7455_SPI is not set
# CONFIG_MMA7660 is not set
# CONFIG_MMA8452 is not set
# CONFIG_MMA9551 is not set
# CONFIG_MMA9553 is not set
# CONFIG_MXC4005 is not set
# CONFIG_MXC6255 is not set
# CONFIG_SCA3000 is not set
# CONFIG_STK8312 is not set
# CONFIG_STK8BA50 is not set
# end of Accelerometers

#
# Analog to digital converters
#
# CONFIG_AD7124 is not set
# CONFIG_AD7266 is not set
# CONFIG_AD7291 is not set
# CONFIG_AD7298 is not set
# CONFIG_AD7476 is not set
# CONFIG_AD7606_IFACE_PARALLEL is not set
# CONFIG_AD7606_IFACE_SPI is not set
# CONFIG_AD7766 is not set
# CONFIG_AD7768_1 is not set
# CONFIG_AD7780 is not set
# CONFIG_AD7791 is not set
# CONFIG_AD7793 is not set
# CONFIG_AD7887 is not set
# CONFIG_AD7923 is not set
# CONFIG_AD7949 is not set
# CONFIG_AD799X is not set
CONFIG_AXP20X_ADC=y
CONFIG_AXP288_ADC=y
# CONFIG_CC10001_ADC is not set
# CONFIG_ENVELOPE_DETECTOR is not set
# CONFIG_HI8435 is not set
# CONFIG_HX711 is not set
# CONFIG_INA2XX_ADC is not set
# CONFIG_LTC2471 is not set
# CONFIG_LTC2485 is not set
# CONFIG_LTC2497 is not set
# CONFIG_MAX1027 is not set
# CONFIG_MAX11100 is not set
# CONFIG_MAX1118 is not set
# CONFIG_MAX1363 is not set
# CONFIG_MAX9611 is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
# CONFIG_MCP3911 is not set
CONFIG_MESON_SARADC=y
# CONFIG_NAU7802 is not set
# CONFIG_QCOM_SPMI_IADC is not set
# CONFIG_QCOM_SPMI_VADC is not set
# CONFIG_QCOM_SPMI_ADC5 is not set
CONFIG_ROCKCHIP_SARADC=y
# CONFIG_SD_ADC_MODULATOR is not set
# CONFIG_TI_ADC081C is not set
# CONFIG_TI_ADC0832 is not set
# CONFIG_TI_ADC084S021 is not set
# CONFIG_TI_ADC12138 is not set
# CONFIG_TI_ADC108S102 is not set
# CONFIG_TI_ADC128S052 is not set
# CONFIG_TI_ADC161S626 is not set
# CONFIG_TI_ADS1015 is not set
# CONFIG_TI_ADS7950 is not set
# CONFIG_TI_ADS8344 is not set
# CONFIG_TI_ADS8688 is not set
# CONFIG_TI_ADS124S08 is not set
# CONFIG_TI_TLC4541 is not set
# CONFIG_VF610_ADC is not set
# CONFIG_XILINX_XADC is not set
# end of Analog to digital converters

#
# Analog to digital and digital to analog converters
#
# end of Analog to digital and digital to analog converters

#
# Analog Front Ends
#
# CONFIG_IIO_RESCALE is not set
# end of Analog Front Ends

#
# Amplifiers
#
# CONFIG_AD8366 is not set
# end of Amplifiers

#
# Chemical Sensors
#
# CONFIG_ATLAS_PH_SENSOR is not set
# CONFIG_BME680 is not set
# CONFIG_CCS811 is not set
# CONFIG_IAQCORE is not set
# CONFIG_PMS7003 is not set
# CONFIG_SENSIRION_SGP30 is not set
# CONFIG_SPS30 is not set
# CONFIG_VZ89X is not set
# end of Chemical Sensors

#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
# end of Hid Sensor IIO Common

#
# SSP Sensor Common
#
# CONFIG_IIO_SSP_SENSORHUB is not set
# end of SSP Sensor Common

#
# Digital to analog converters
#
# CONFIG_AD5064 is not set
# CONFIG_AD5360 is not set
# CONFIG_AD5380 is not set
# CONFIG_AD5421 is not set
# CONFIG_AD5446 is not set
# CONFIG_AD5449 is not set
# CONFIG_AD5592R is not set
# CONFIG_AD5593R is not set
# CONFIG_AD5504 is not set
# CONFIG_AD5624R_SPI is not set
# CONFIG_LTC1660 is not set
# CONFIG_LTC2632 is not set
# CONFIG_AD5686_SPI is not set
# CONFIG_AD5696_I2C is not set
# CONFIG_AD5755 is not set
# CONFIG_AD5758 is not set
# CONFIG_AD5761 is not set
# CONFIG_AD5764 is not set
# CONFIG_AD5791 is not set
# CONFIG_AD7303 is not set
# CONFIG_AD8801 is not set
# CONFIG_DPOT_DAC is not set
# CONFIG_DS4424 is not set
# CONFIG_M62332 is not set
# CONFIG_MAX517 is not set
# CONFIG_MAX5821 is not set
# CONFIG_MCP4725 is not set
# CONFIG_MCP4922 is not set
# CONFIG_TI_DAC082S085 is not set
# CONFIG_TI_DAC5571 is not set
# CONFIG_TI_DAC7311 is not set
# CONFIG_TI_DAC7612 is not set
# CONFIG_VF610_DAC is not set
# end of Digital to analog converters

#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
# CONFIG_AD9523 is not set
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
# CONFIG_ADF4350 is not set
# CONFIG_ADF4371 is not set
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
# CONFIG_ADIS16080 is not set
# CONFIG_ADIS16130 is not set
# CONFIG_ADIS16136 is not set
# CONFIG_ADIS16260 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_BMG160 is not set
# CONFIG_FXAS21002C is not set
# CONFIG_HID_SENSOR_GYRO_3D is not set
# CONFIG_MPU3050_I2C is not set
# CONFIG_IIO_ST_GYRO_3AXIS is not set
# CONFIG_ITG3200 is not set
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
# CONFIG_AFE4403 is not set
# CONFIG_AFE4404 is not set
# CONFIG_MAX30100 is not set
# CONFIG_MAX30102 is not set
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
# CONFIG_AM2315 is not set
# CONFIG_DHT11 is not set
# CONFIG_HDC100X is not set
# CONFIG_HID_SENSOR_HUMIDITY is not set
# CONFIG_HTS221 is not set
# CONFIG_HTU21 is not set
# CONFIG_SI7005 is not set
# CONFIG_SI7020 is not set
# end of Humidity sensors

#
# Inertial measurement units
#
# CONFIG_ADIS16400 is not set
# CONFIG_ADIS16460 is not set
# CONFIG_ADIS16480 is not set
# CONFIG_BMI160_I2C is not set
# CONFIG_BMI160_SPI is not set
# CONFIG_KMX61 is not set
# CONFIG_INV_MPU6050_I2C is not set
# CONFIG_INV_MPU6050_SPI is not set
# CONFIG_IIO_ST_LSM6DSX is not set
# end of Inertial measurement units

#
# Light sensors
#
# CONFIG_ACPI_ALS is not set
# CONFIG_ADJD_S311 is not set
# CONFIG_AL3320A is not set
# CONFIG_APDS9300 is not set
# CONFIG_APDS9960 is not set
# CONFIG_BH1750 is not set
# CONFIG_BH1780 is not set
# CONFIG_CM32181 is not set
# CONFIG_CM3232 is not set
# CONFIG_CM3323 is not set
# CONFIG_CM3605 is not set
# CONFIG_CM36651 is not set
# CONFIG_GP2AP020A00F is not set
# CONFIG_SENSORS_ISL29018 is not set
# CONFIG_SENSORS_ISL29028 is not set
# CONFIG_ISL29125 is not set
# CONFIG_HID_SENSOR_ALS is not set
# CONFIG_HID_SENSOR_PROX is not set
# CONFIG_JSA1212 is not set
# CONFIG_RPR0521 is not set
# CONFIG_LTR501 is not set
# CONFIG_LV0104CS is not set
# CONFIG_MAX44000 is not set
# CONFIG_MAX44009 is not set
# CONFIG_NOA1305 is not set
# CONFIG_OPT3001 is not set
# CONFIG_PA12203001 is not set
# CONFIG_SI1133 is not set
# CONFIG_SI1145 is not set
# CONFIG_STK3310 is not set
# CONFIG_ST_UVIS25 is not set
# CONFIG_TCS3414 is not set
# CONFIG_TCS3472 is not set
# CONFIG_SENSORS_TSL2563 is not set
# CONFIG_TSL2583 is not set
# CONFIG_TSL2772 is not set
# CONFIG_TSL4531 is not set
# CONFIG_US5182D is not set
# CONFIG_VCNL4000 is not set
# CONFIG_VCNL4035 is not set
# CONFIG_VEML6070 is not set
# CONFIG_VL6180 is not set
# CONFIG_ZOPT2201 is not set
# end of Light sensors

#
# Magnetometer sensors
#
# CONFIG_AK8974 is not set
# CONFIG_AK8975 is not set
# CONFIG_AK09911 is not set
# CONFIG_BMC150_MAGN_I2C is not set
# CONFIG_BMC150_MAGN_SPI is not set
# CONFIG_MAG3110 is not set
# CONFIG_HID_SENSOR_MAGNETOMETER_3D is not set
# CONFIG_MMC35240 is not set
# CONFIG_IIO_ST_MAGN_3AXIS is not set
# CONFIG_SENSORS_HMC5843_I2C is not set
# CONFIG_SENSORS_HMC5843_SPI is not set
# CONFIG_SENSORS_RM3100_I2C is not set
# CONFIG_SENSORS_RM3100_SPI is not set
# end of Magnetometer sensors

#
# Multiplexers
#
# CONFIG_IIO_MUX is not set
# end of Multiplexers

#
# Inclinometer sensors
#
# CONFIG_HID_SENSOR_INCLINOMETER_3D is not set
# CONFIG_HID_SENSOR_DEVICE_ROTATION is not set
# end of Inclinometer sensors

#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=m
CONFIG_IIO_INTERRUPT_TRIGGER=m
CONFIG_IIO_TIGHTLOOP_TRIGGER=m
CONFIG_IIO_SYSFS_TRIGGER=y
# end of Triggers - standalone

#
# Digital potentiometers
#
# CONFIG_AD5272 is not set
# CONFIG_DS1803 is not set
# CONFIG_MAX5432 is not set
# CONFIG_MAX5481 is not set
# CONFIG_MAX5487 is not set
# CONFIG_MCP4018 is not set
# CONFIG_MCP4131 is not set
# CONFIG_MCP4531 is not set
# CONFIG_MCP41010 is not set
# CONFIG_TPL0102 is not set
# end of Digital potentiometers

#
# Digital potentiostats
#
# CONFIG_LMP91000 is not set
# end of Digital potentiostats

#
# Pressure sensors
#
# CONFIG_ABP060MG is not set
# CONFIG_BMP280 is not set
# CONFIG_DPS310 is not set
# CONFIG_HID_SENSOR_PRESS is not set
# CONFIG_HP03 is not set
# CONFIG_MPL115_I2C is not set
# CONFIG_MPL115_SPI is not set
# CONFIG_MPL3115 is not set
# CONFIG_MS5611 is not set
# CONFIG_MS5637 is not set
# CONFIG_IIO_ST_PRESS is not set
# CONFIG_T5403 is not set
# CONFIG_HP206C is not set
# CONFIG_ZPA2326 is not set
# end of Pressure sensors

#
# Lightning sensors
#
# CONFIG_AS3935 is not set
# end of Lightning sensors

#
# Proximity and distance sensors
#
# CONFIG_ISL29501 is not set
# CONFIG_LIDAR_LITE_V2 is not set
# CONFIG_MB1232 is not set
# CONFIG_RFD77402 is not set
# CONFIG_SRF04 is not set
# CONFIG_SX9500 is not set
# CONFIG_SRF08 is not set
# CONFIG_VL53L0X_I2C is not set
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
# CONFIG_AD2S90 is not set
# CONFIG_AD2S1200 is not set
# end of Resolver to digital converters

#
# Temperature sensors
#
# CONFIG_MAXIM_THERMOCOUPLE is not set
# CONFIG_HID_SENSOR_TEMP is not set
# CONFIG_MLX90614 is not set
# CONFIG_MLX90632 is not set
# CONFIG_TMP006 is not set
# CONFIG_TMP007 is not set
# CONFIG_TSYS01 is not set
# CONFIG_TSYS02D is not set
# CONFIG_MAX31856 is not set
# end of Temperature sensors

# CONFIG_NTB is not set
# CONFIG_VME_BUS is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_FSL_FTM is not set
CONFIG_PWM_MESON=y
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_SUN4I=y

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_AL_FIC is not set
CONFIG_PARTITION_PERCPU=y
CONFIG_MESON_IRQ_GPIO=y
# end of IRQ chip support

# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_MESON=y
CONFIG_RESET_MESON_AUDIO_ARB=y
CONFIG_RESET_SCMI=y
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SUNXI=y
# CONFIG_RESET_TI_SYSCON is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_PHY_XGENE is not set
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_SUN6I_MIPI_DPHY=y
CONFIG_PHY_SUN9I_USB=y
CONFIG_PHY_SUN50I_USB3=y
CONFIG_PHY_MESON8B_USB2=y
CONFIG_PHY_MESON_GXL_USB2=y
CONFIG_PHY_MESON_GXL_USB3=y
CONFIG_PHY_MESON_G12A_USB2=y
CONFIG_PHY_MESON_G12A_USB3_PCIE=y
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_CADENCE_DP is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_FSL_IMX8MQ_USB is not set
# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
# CONFIG_PHY_QCOM_USB_HS is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
CONFIG_PHY_ROCKCHIP_DP=y
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_USB3=y
CONFIG_PHY_ROCKCHIP_PCIE=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PHY_ROCKCHIP_USB=y
# CONFIG_PHY_SAMSUNG_USB2 is not set
# CONFIG_PHY_TUSB1210 is not set
# end of PHY Subsystem

# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCI400_PMU=y
CONFIG_ARM_CCI5xx_PMU=y
CONFIG_ARM_CCN=m
CONFIG_ARM_PMU=y
CONFIG_ARM_PMU_ACPI=y
# CONFIG_ARM_SMMU_V3_PMU is not set
CONFIG_ARM_DSU_PMU=m
# CONFIG_HISI_PMU is not set
CONFIG_ARM_SPE_PMU=m
# end of Performance monitor support

CONFIG_RAS=y

#
# Android
#
# CONFIG_ANDROID is not set
# end of Android

# CONFIG_LIBNVDIMM is not set
CONFIG_DAX=y
CONFIG_DEV_DAX=m
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_MESON_EFUSE=y
# CONFIG_MESON_MX_EFUSE is not set

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# end of HW tracing support

# CONFIG_FPGA is not set
# CONFIG_FSI is not set
CONFIG_TEE=y

#
# TEE drivers
#
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
# end of TEE drivers

CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
# CONFIG_MUX_ADGS1408 is not set
CONFIG_MUX_GPIO=m
CONFIG_MUX_MMIO=m
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set
# CONFIG_INTERCONNECT is not set
# CONFIG_COUNTER is not set
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_IOMAP=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=m
# CONFIG_REISERFS_CHECK is not set
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
# CONFIG_JFS_DEBUG is not set
# CONFIG_JFS_STATISTICS is not set
CONFIG_XFS_FS=y
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
# CONFIG_XFS_RT is not set
# CONFIG_XFS_ONLINE_SCRUB is not set
# CONFIG_XFS_WARN is not set
# CONFIG_XFS_DEBUG is not set
CONFIG_GFS2_FS=m
CONFIG_GFS2_FS_LOCKING_DLM=y
CONFIG_OCFS2_FS=m
CONFIG_OCFS2_FS_O2CB=m
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
CONFIG_OCFS2_FS_STATS=y
CONFIG_OCFS2_DEBUG_MASKLOG=y
# CONFIG_OCFS2_DEBUG_FS is not set
CONFIG_BTRFS_FS=y
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
# CONFIG_BTRFS_FS_REF_VERIFY is not set
CONFIG_NILFS2_FS=m
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
# CONFIG_F2FS_FAULT_INJECTION is not set
CONFIG_FS_DAX=y
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_MANDATORY_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
CONFIG_PRINT_QUOTA_WARNING=y
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
CONFIG_AUTOFS4_FS=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_VIRTIO_FS=m
CONFIG_OVERLAY_FS=y
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set

#
# Caches
#
CONFIG_FSCACHE=y
# CONFIG_FSCACHE_STATS is not set
# CONFIG_FSCACHE_HISTOGRAM is not set
# CONFIG_FSCACHE_DEBUG is not set
# CONFIG_FSCACHE_OBJECT_LIST is not set
CONFIG_CACHEFILES=m
# CONFIG_CACHEFILES_DEBUG is not set
# CONFIG_CACHEFILES_HISTOGRAM is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
CONFIG_FAT_DEFAULT_UTF8=y
# CONFIG_NTFS_FS is not set
CONFIG_NTFS3_FS=m
# CONFIG_NTFS3_64BIT_CLUSTER is not set
CONFIG_NTFS3_LZX_XPRESS=y
# CONFIG_NTFS3_FS_POSIX_ACL is not set
# end of DOS/FAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_MEMFD_CREATE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=m
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
CONFIG_ECRYPT_FS=m
# CONFIG_ECRYPT_FS_MESSAGING is not set
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
CONFIG_UBIFS_FS=m
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
CONFIG_CRAMFS=m
CONFIG_CRAMFS_BLOCKDEV=y
# CONFIG_CRAMFS_MTD is not set
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_FILE_CACHE is not set
CONFIG_SQUASHFS_FILE_DIRECT=y
# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_ZSTD=y
CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFLATE_COMPRESS=y
CONFIG_PSTORE_LZO_COMPRESS=y
CONFIG_PSTORE_LZ4_COMPRESS=y
CONFIG_PSTORE_LZ4HC_COMPRESS=y
CONFIG_PSTORE_842_COMPRESS=y
CONFIG_PSTORE_ZSTD_COMPRESS=y
CONFIG_PSTORE_COMPRESS=y
CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set
CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
# CONFIG_PSTORE_CONSOLE is not set
# CONFIG_PSTORE_PMSG is not set
# CONFIG_PSTORE_RAM is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_EROFS_FS=m
# CONFIG_EROFS_FS_DEBUG is not set
CONFIG_EROFS_FS_XATTR=y
CONFIG_EROFS_FS_POSIX_ACL=y
# CONFIG_EROFS_FS_SECURITY is not set
CONFIG_EROFS_FS_ZIP=y
CONFIG_EROFS_FS_CLUSTER_PAGE_LIMIT=1
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V2=m
CONFIG_NFS_V3=m
# CONFIG_NFS_V3_ACL is not set
CONFIG_NFS_V4=m
CONFIG_NFS_SWAP=y
# CONFIG_NFS_V4_1 is not set
CONFIG_NFS_FSCACHE=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFSD=m
CONFIG_NFSD_V3=y
# CONFIG_NFSD_V3_ACL is not set
CONFIG_NFSD_V4=y
# CONFIG_NFSD_BLOCKLAYOUT is not set
# CONFIG_NFSD_SCSILAYOUT is not set
# CONFIG_NFSD_FLEXFILELAYOUT is not set
# CONFIG_NFSD_V4_SECURITY_LABEL is not set
CONFIG_GRACE_PERIOD=m
CONFIG_LOCKD=m
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=m
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_SWAP=y
CONFIG_RPCSEC_GSS_KRB5=m
# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
# CONFIG_SUNRPC_DEBUG is not set
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
# CONFIG_CEPH_FS_SECURITY_LABEL is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
# CONFIG_CIFS_WEAK_PW_HASH is not set
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CIFS_DEBUG=y
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
CONFIG_CIFS_DFS_UPCALL=y
# CONFIG_CIFS_FSCACHE is not set
CONFIG_CODA_FS=m
CONFIG_AFS_FS=m
# CONFIG_AFS_DEBUG is not set
CONFIG_AFS_FSCACHE=y
# CONFIG_AFS_DEBUG_CURSOR is not set
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
# CONFIG_9P_FS_POSIX_ACL is not set
# CONFIG_9P_FS_SECURITY is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf-8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=m
CONFIG_NLS_MAC_GAELIC=m
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=y
CONFIG_DLM=m
# CONFIG_DLM_DEBUG is not set
# CONFIG_UNICODE is not set
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
CONFIG_KEYS_COMPAT=y
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_BIG_KEYS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_PROC_MEM_ALWAYS_FORCE=y
# CONFIG_PROC_MEM_FORCE_PTRACE is not set
# CONFIG_PROC_MEM_NO_FORCE is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
# CONFIG_SECURITY_NETWORK_XFRM is not set
CONFIG_SECURITY_PATH=y
CONFIG_LSM_MMAP_MIN_ADDR=32768
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
# CONFIG_SECURITY_SELINUX_DISABLE is not set
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
CONFIG_SECURITY_APPARMOR=y
CONFIG_SECURITY_APPARMOR_HASH=y
CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
# CONFIG_SECURITY_APPARMOR_DEBUG is not set
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
CONFIG_INTEGRITY_AUDIT=y
# CONFIG_IMA is not set
# CONFIG_EVM is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT=y
CONFIG_INIT_STACK_NONE=y
# CONFIG_INIT_STACK_ALL is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
# end of Memory initialization
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=y
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=m
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=m
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=y
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_ENGINE=y

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=m
CONFIG_CRYPTO_ECC=m
CONFIG_CRYPTO_ECDH=m
CONFIG_CRYPTO_ECRDSA=m

#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_AEGIS128=m
CONFIG_CRYPTO_AEGIS128_SIMD=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=y

#
# Block modes
#
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=m
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_OFB=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_KEYWRAP=m
CONFIG_CRYPTO_NHPOLY1305=y
CONFIG_CRYPTO_ADIANTUM=m
CONFIG_CRYPTO_ESSIV=m

#
# Hash modes
#
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_VMAC=m

#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_XXHASH=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_RMD128=m
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_RMD256=m
CONFIG_CRYPTO_RMD320=m
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_STREEBOG=m
CONFIG_CRYPTO_TGR192=m
CONFIG_CRYPTO_WP512=m

#
# Ciphers
#
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_LIB_ARC4=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_BLOWFISH_COMMON=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST_COMMON=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SALSA20=m
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_TWOFISH_COMMON=m

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=y
CONFIG_CRYPTO_ZSTD=y

#
# Random Number Generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_USER_API=m
CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
CONFIG_CRYPTO_USER_API_RNG=m
CONFIG_CRYPTO_USER_API_AEAD=m
# CONFIG_CRYPTO_STATS is not set
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_ALLWINNER=y
CONFIG_CRYPTO_DEV_SUN8I_CE=y
CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG=y
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_CCP is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_ROCKCHIP=y
CONFIG_CRYPTO_DEV_VIRTIO=m
CONFIG_CRYPTO_DEV_CRYPTODEV_LINUX=y
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
CONFIG_CRYPTO_DEV_CCREE=m
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG=y
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
CONFIG_PKCS7_MESSAGE_PARSER=y
CONFIG_PKCS7_TEST_KEY=m
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

#
# Library routines
#
CONFIG_RAID6_PQ=y
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=m
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_INDIRECT_PIO=y
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=m
CONFIG_CRC4=m
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=m
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
# CONFIG_XZ_DEC_SPARC is not set
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y
CONFIG_SWIOTLB=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=256
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
CONFIG_SGL_ALLOC=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_SBITMAP=y
# CONFIG_STRING_SELFTEST is not set
# end of Library routines

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_CALLER is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
CONFIG_DYNAMIC_DEBUG=y
# end of printk and dmesg options

#
# Compile-time checks and compiler options
#
# CONFIG_DEBUG_INFO is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=2048
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_READABLE_ASM is not set
CONFIG_DEBUG_FS=y
CONFIG_HEADERS_INSTALL=y
CONFIG_OPTIMIZE_INLINING=y
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_RODATA_TEST is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_VM is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
# CONFIG_KASAN is not set
CONFIG_KASAN_STACK=1
# end of Memory Debugging

CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Lockups and Hangs
#
# CONFIG_SOFTLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
# CONFIG_WQ_WATCHDOG is not set
# end of Debug Lockups and Hangs

# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHED_INFO=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
# CONFIG_DEBUG_TIMEKEEPING is not set
CONFIG_DEBUG_PREEMPT=y

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

# CONFIG_STACKTRACE is not set
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_HAVE_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
# CONFIG_RCU_PERF_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
CONFIG_FUNCTION_ERROR_INJECTION=y
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_LKDTM is not set
# CONFIG_TEST_LIST_SORT is not set
# CONFIG_TEST_SORT is not set
# CONFIG_KPROBES_SANITY_TEST is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_ASYNC_RAID6_TEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_STRSCPY is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_BITFIELD is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_OVERFLOW is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_HASH is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_VMALLOC is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_BPF is not set
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_STACKINIT is not set
# CONFIG_TEST_MEMINIT is not set
CONFIG_MEMTEST=y
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_UBSAN is not set
CONFIG_UBSAN_ALIGNMENT=y
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
# CONFIG_STRICT_DEVMEM is not set
# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
# CONFIG_DEBUG_WX is not set
# CONFIG_DEBUG_ALIGN_RODATA is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
# end of Kernel hacking


================================================
FILE: kernel-config/release/stable/config-6.1
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 6.1.167 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 15.2.Rel1 (Build arm-15.86)) 15.2.1 20251203"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=150201
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=24501
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=24501
CONFIG_LLD_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_PAHOLE_VERSION=130
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
# CONFIG_UAPI_HEADER_TEST is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
# CONFIG_WATCH_QUEUE is not set
# CONFIG_CROSS_MEMORY_ATTACH is not set
# CONFIG_USELIB is not set
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_SIM=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem

CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_HZ_PERIODIC=y
# CONFIG_NO_HZ_IDLE is not set
# CONFIG_NO_HZ_FULL is not set
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y

#
# BPF subsystem
#
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_JIT=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
CONFIG_BPF_JIT_DEFAULT_ON=y
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
# CONFIG_BPF_PRELOAD is not set
# CONFIG_BPF_LSM is not set
# end of BPF subsystem

CONFIG_PREEMPT_VOLUNTARY_BUILD=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
# CONFIG_PREEMPT_DYNAMIC is not set

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_SCHED_THERMAL_PRESSURE=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
# CONFIG_PRINTK_INDEX is not set
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
# CONFIG_UCLAMP_TASK is not set
# end of Scheduler features

CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_CC_HAS_INT128=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_GCC10_NO_ARRAY_BOUNDS=y
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
CONFIG_CGROUP_MISC=y
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
# CONFIG_CHECKPOINT_RESTORE is not set
CONFIG_SCHED_AUTOGROUP=y
# CONFIG_SYSFS_DEPRECATED is not set
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
# CONFIG_BOOT_CONFIG_EMBED is not set
CONFIG_INITRAMFS_PRESERVE_MTIME=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_GUEST_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
# end of General setup

CONFIG_ARM64=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_CONT_PTE_SHIFT=4
CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y

#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
CONFIG_ARCH_SUNXI=y
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_APPLE is not set
# CONFIG_ARCH_BCM is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SPARX5 is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_KEEMBAY is not set
# CONFIG_ARCH_MEDIATEK is not set
CONFIG_ARCH_MESON=y
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_NXP is not set
# CONFIG_ARCH_NPCM is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_RENESAS is not set
CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_INTEL_SOCFPGA is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZYNQMP is not set
# end of Platform selection

#
# Kernel Features
#

#
# ARM errata workarounds via the alternatives framework
#
CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_834220=y
CONFIG_ARM64_ERRATUM_1742098=y
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1319367=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_ERRATUM_2441007=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_ARM64_ERRATUM_2051678=y
CONFIG_ARM64_ERRATUM_2077057=y
CONFIG_ARM64_ERRATUM_2658417=y
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
CONFIG_ARM64_ERRATUM_2054223=y
CONFIG_ARM64_ERRATUM_2067961=y
CONFIG_ARM64_ERRATUM_2441009=y
CONFIG_ARM64_ERRATUM_2457168=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y
CONFIG_ARM64_ERRATUM_2966298=y
CONFIG_ARM64_ERRATUM_3194386=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
CONFIG_QCOM_FALKOR_ERRATUM_1009=y
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
CONFIG_ROCKCHIP_ERRATUM_114514=y
# end of ARM errata workarounds via the alternatives framework

CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
CONFIG_ARM64_VA_BITS_39=y
# CONFIG_ARM64_VA_BITS_48 is not set
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SCHED_MC=y
CONFIG_SCHED_CLUSTER=y
# CONFIG_SCHED_SMT is not set
CONFIG_NR_CPUS=8
# CONFIG_HOTPLUG_CPU is not set
# CONFIG_NUMA is not set
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_KEXEC_FILE is not set
# CONFIG_CRASH_DUMP is not set
# CONFIG_XEN is not set
CONFIG_ARCH_FORCE_MAX_ORDER=11
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y
# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y

#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
CONFIG_AS_HAS_LDAPR=y
CONFIG_AS_HAS_LSE_ATOMICS=y
# CONFIG_ARM64_USE_LSE_ATOMICS is not set
# end of ARMv8.1 architectural features

#
# ARMv8.2 architectural features
#
CONFIG_AS_HAS_ARMV8_2=y
CONFIG_AS_HAS_SHA3=y
# CONFIG_ARM64_PMEM is not set
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features

#
# ARMv8.3 architectural features
#
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
CONFIG_AS_HAS_PAC=y
CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
# end of ARMv8.3 architectural features

#
# ARMv8.4 architectural features
#
CONFIG_ARM64_AMU_EXTN=y
CONFIG_AS_HAS_ARMV8_4=y
CONFIG_ARM64_TLB_RANGE=y
# end of ARMv8.4 architectural features

#
# ARMv8.5 architectural features
#
CONFIG_AS_HAS_ARMV8_5=y
CONFIG_ARM64_BTI=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARM64_AS_HAS_MTE=y
CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features

#
# ARMv8.7 architectural features
#
CONFIG_ARM64_EPAN=y
# end of ARMv8.7 architectural features

CONFIG_ARM64_SVE=y
CONFIG_ARM64_MODULE_PLTS=y
CONFIG_ARM64_PSEUDO_NMI=y
# CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
CONFIG_ARCH_NR_GPIO=0
# end of Kernel Features

#
# Boot options
#
CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
CONFIG_CMDLINE=""
CONFIG_EFI_STUB=y
CONFIG_EFI=y
CONFIG_DMI=y
# end of Boot options

#
# Power management options
#
# CONFIG_SUSPEND is not set
# CONFIG_HIBERNATION is not set
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options

#
# CPU Power Management
#

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_IDLE_GOV_LADDER=y
# CONFIG_CPU_IDLE_GOV_MENU is not set
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_DT_IDLE_STATES=y
CONFIG_DT_IDLE_GENPD=y

#
# ARM CPU Idle Drivers
#
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
# end of ARM CPU Idle Drivers
# end of CPU Idle

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_STAT is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_USERSPACE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
# CONFIG_ACPI_CPPC_CPUFREQ is not set
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_SCMI_CPUFREQ=y
# end of CPU Frequency scaling
# end of CPU Power Management

CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_GENERIC_GSI=y
CONFIG_ACPI_CCA_REQUIRED=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
CONFIG_ACPI_EC_DEBUGFS=m
CONFIG_ACPI_AC=m
CONFIG_ACPI_BATTERY=m
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_VIDEO=m
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_MCFG=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_THERMAL=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_PCI_SLOT=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_CUSTOM_METHOD=m
CONFIG_ACPI_BGRT=y
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
CONFIG_HAVE_ACPI_APEI=y
CONFIG_ACPI_APEI=y
CONFIG_ACPI_APEI_GHES=y
CONFIG_ACPI_APEI_SEA=y
CONFIG_ACPI_APEI_MEMORY_FAILURE=y
CONFIG_ACPI_APEI_EINJ=m
CONFIG_ACPI_APEI_ERST_DEBUG=m
CONFIG_ACPI_CONFIGFS=m
CONFIG_ACPI_PFRUT=m
CONFIG_ACPI_IORT=y
CONFIG_ACPI_GTDT=y
# CONFIG_ACPI_AGDI is not set
CONFIG_ACPI_PPTT=y
CONFIG_PMIC_OPREGION=y
CONFIG_ACPI_VIOT=y
CONFIG_ACPI_PRMT=y
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_HAVE_KVM=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_MMIO=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_KVM_XFER_TO_GUEST_WORK=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
# CONFIG_NVHE_EL2_DEBUG is not set
CONFIG_CPU_MITIGATIONS=y

#
# General architecture-dependent options
#
CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
CONFIG_UPROBES=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
# CONFIG_SECCOMP_CACHE_DEBUG is not set
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
# CONFIG_SHADOW_CALL_STACK is not set
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
CONFIG_HAVE_CONTEXT_TRACKING_USER=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_ARCH_HUGE_VMALLOC=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET=y
# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
CONFIG_HAVE_PREEMPT_DYNAMIC=y
CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
CONFIG_MODULE_COMPRESS_NONE=y
# CONFIG_MODULE_COMPRESS_GZIP is not set
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BLK_RQ_ALLOC_TIME=y
CONFIG_BLK_CGROUP_RWSTAT=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_ICQ=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=y
# CONFIG_BLK_DEV_ZONED is not set
CONFIG_BLK_DEV_THROTTLING=y
# CONFIG_BLK_DEV_THROTTLING_LOW is not set
CONFIG_BLK_WBT=y
CONFIG_BLK_WBT_MQ=y
CONFIG_BLK_CGROUP_IOLATENCY=y
CONFIG_BLK_CGROUP_IOCOST=y
CONFIG_BLK_CGROUP_IOPRIO=y
# CONFIG_BLK_DEBUG_FS is not set
CONFIG_BLK_SED_OPAL=y
CONFIG_BLK_INLINE_ENCRYPTION=y
CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_AIX_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
# CONFIG_CMDLINE_PARTITION is not set
CONFIG_AMLOGIC_PARTITION=y
# end of Partition Types

CONFIG_BLOCK_COMPAT=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_HOLDER_DEPRECATED=y
CONFIG_BLK_MQ_STACKING=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
# CONFIG_BFQ_CGROUP_DEBUG is not set
# end of IO Schedulers

CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK=y
CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_READ_LOCK=y
CONFIG_ARCH_INLINE_READ_LOCK_BH=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_READ_UNLOCK=y
CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_WRITE_LOCK=y
CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_SPIN_TRYLOCK=y
CONFIG_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_INLINE_SPIN_LOCK=y
CONFIG_INLINE_SPIN_LOCK_BH=y
CONFIG_INLINE_SPIN_LOCK_IRQ=y
CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_INLINE_SPIN_UNLOCK_BH=y
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_READ_LOCK=y
CONFIG_INLINE_READ_LOCK_BH=y
CONFIG_INLINE_READ_LOCK_IRQ=y
CONFIG_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_INLINE_READ_UNLOCK=y
CONFIG_INLINE_READ_UNLOCK_BH=y
CONFIG_INLINE_READ_UNLOCK_IRQ=y
CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_WRITE_LOCK=y
CONFIG_INLINE_WRITE_LOCK_BH=y
CONFIG_INLINE_WRITE_LOCK_IRQ=y
CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_INLINE_WRITE_UNLOCK=y
CONFIG_INLINE_WRITE_UNLOCK_BH=y
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_HAVE_ELF_PROT=y
CONFIG_ARCH_USE_GNU_PROPERTY=y
CONFIG_ELFCORE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=m
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_ZPOOL=y
CONFIG_SWAP=y
CONFIG_ZSWAP=y
CONFIG_ZSWAP_DEFAULT_ON=y
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD_DEPRECATED is not set
# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
CONFIG_ZBUD=y
# CONFIG_Z3FOLD_DEPRECATED is not set
CONFIG_ZSMALLOC=y
# CONFIG_ZSMALLOC_STAT is not set

#
# SLAB allocator options
#
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
CONFIG_SLAB_FREELIST_RANDOM=y
CONFIG_SLAB_FREELIST_HARDENED=y
# CONFIG_SLUB_STATS is not set
CONFIG_SLUB_CPU_PARTIAL=y
# end of SLAB allocator options

CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
CONFIG_ARCH_ENABLE_THP_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PCP_BATCH_SCALE_MAX=5
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_MMU_NOTIFIER=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
CONFIG_MEMORY_FAILURE=y
# CONFIG_HWPOISON_INJECT is not set
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_TRANSPARENT_HUGEPAGE=y
# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set
CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
CONFIG_THP_SWAP=y
# CONFIG_READ_ONLY_THP_FOR_FS is not set
CONFIG_FRONTSWAP=y
CONFIG_CMA=y
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_CMA_AREAS=7
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_ARCH_HAS_ZONE_DMA_SET=y
CONFIG_ZONE_DMA=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_TEST is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_SECRETMEM=y
# CONFIG_ANON_VMA_NAME is not set
# CONFIG_USERFAULTFD is not set
CONFIG_LRU_GEN=y
CONFIG_LRU_GEN_ENABLED=y
# CONFIG_LRU_GEN_STATS is not set
CONFIG_LOCK_MM_AND_FIND_VMA=y

#
# Data Access Monitoring
#
# CONFIG_DAMON is not set
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_EXTENSIONS=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_AF_UNIX_OOB=y
CONFIG_UNIX_DIAG=y
CONFIG_TLS=m
# CONFIG_TLS_DEVICE is not set
# CONFIG_TLS_TOE is not set
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
CONFIG_XFRM_INTERFACE=m
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_AH=y
CONFIG_XFRM_ESP=y
CONFIG_XFRM_IPCOMP=y
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_XFRM_ESPINTCP=y
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
# CONFIG_IP_FIB_TRIE_STATS is not set
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_ROUTE_CLASSID=y
# CONFIG_IP_PNP is not set
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=y
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=y
CONFIG_NET_FOU=y
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
CONFIG_INET_ESP_OFFLOAD=m
# CONFIG_INET_ESPINTCP is not set
CONFIG_INET_IPCOMP=y
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=y
CONFIG_INET_TUNNEL=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
CONFIG_INET_UDP_DIAG=y
CONFIG_INET_RAW_DIAG=y
# CONFIG_INET_DIAG_DESTROY is not set
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_NV=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_CONG_DCTCP=m
CONFIG_TCP_CONG_CDG=m
CONFIG_TCP_CONG_BBR=m
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_ESP_OFFLOAD=m
CONFIG_INET6_ESPINTCP=y
CONFIG_INET6_IPCOMP=y
CONFIG_IPV6_MIP6=m
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=y
CONFIG_INET6_TUNNEL=y
CONFIG_IPV6_VTI=m
CONFIG_IPV6_SIT=y
# CONFIG_IPV6_SIT_6RD is not set
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=y
CONFIG_IPV6_GRE=m
CONFIG_IPV6_FOU=y
CONFIG_IPV6_FOU_TUNNEL=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
CONFIG_IPV6_SEG6_LWTUNNEL=y
CONFIG_IPV6_SEG6_HMAC=y
CONFIG_IPV6_SEG6_BPF=y
CONFIG_IPV6_RPL_LWTUNNEL=y
# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
# CONFIG_NETLABEL is not set
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=y
CONFIG_MPTCP_IPV6=y
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_EGRESS=y
CONFIG_NETFILTER_SKIP_EGRESS=y
CONFIG_NETFILTER_NETLINK=m
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
# CONFIG_NETFILTER_NETLINK_HOOK is not set
CONFIG_NETFILTER_NETLINK_ACCT=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NETFILTER_NETLINK_OSF=m
CONFIG_NF_CONNTRACK=y
CONFIG_NF_LOG_SYSLOG=m
CONFIG_NETFILTER_CONNCOUNT=m
CONFIG_NF_CONNTRACK_MARK=y
# CONFIG_NF_CONNTRACK_SECMARK is not set
CONFIG_NF_CONNTRACK_ZONES=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y
CONFIG_NF_CONNTRACK_TIMEOUT=y
CONFIG_NF_CONNTRACK_TIMESTAMP=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_CT_NETLINK_TIMEOUT=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=m
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=m
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_FULLCONE=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_OBJREF=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
CONFIG_NFT_OSF=m
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NF_DUP_NETDEV=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NFT_REJECT_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
# CONFIG_NF_FLOW_TABLE_PROCFS is not set
CONFIG_NETFILTER_XTABLES=m
# CONFIG_NETFILTER_XTABLES_COMPAT is not set

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=m
CONFIG_NETFILTER_XT_CONNMARK=m
CONFIG_NETFILTER_XT_SET=m

#
# Xtables targets
#
# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LED=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=m
CONFIG_NETFILTER_XT_TARGET_NETMAP=m
CONFIG_NETFILTER_XT_TARGET_FULLCONENAT=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD=m
CONFIG_NETFILTER_XT_TARGET_RATEEST=m
CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=m
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# end of Core Netfilter Configuration

CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
# CONFIG_IP_VS_DEBUG is not set
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m
# CONFIG_IP_VS_TWOS is not set

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_SOCKET_IPV4=m
CONFIG_NF_TPROXY_IPV4=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=m
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_FULLCONENAT=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
# CONFIG_IP_NF_SECURITY is not set
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
# CONFIG_IP6_NF_SECURITY is not set
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=y
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_NFT_BRIDGE_META=m
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
# CONFIG_BPFILTER is not set
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m

#
# DCCP CCIDs Configuration
#
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
CONFIG_IP_DCCP_CCID3=y
# CONFIG_IP_DCCP_CCID3_DEBUG is not set
CONFIG_IP_DCCP_TFRC_LIB=y
# end of DCCP CCIDs Configuration

#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
# end of DCCP Kernel Hacking

CONFIG_IP_SCTP=m
CONFIG_SCTP_DBG_OBJCNT=y
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=m
CONFIG_RDS=m
CONFIG_RDS_TCP=m
# CONFIG_RDS_DEBUG is not set
CONFIG_TIPC=m
CONFIG_TIPC_MEDIA_UDP=y
CONFIG_TIPC_CRYPTO=y
CONFIG_TIPC_DIAG=m
# CONFIG_ATM is not set
CONFIG_L2TP=m
CONFIG_L2TP_DEBUGFS=m
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=m
CONFIG_L2TP_ETH=m
CONFIG_STP=y
CONFIG_GARP=m
CONFIG_MRP=m
CONFIG_BRIDGE=y
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_BRIDGE_MRP=y
CONFIG_BRIDGE_CFM=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_TAG_AR9331=m
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
CONFIG_NET_DSA_TAG_BRCM=m
CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
CONFIG_NET_DSA_TAG_HELLCREEK=m
CONFIG_NET_DSA_TAG_GSWIP=m
CONFIG_NET_DSA_TAG_DSA_COMMON=m
CONFIG_NET_DSA_TAG_DSA=m
CONFIG_NET_DSA_TAG_EDSA=m
CONFIG_NET_DSA_TAG_MTK=m
CONFIG_NET_DSA_TAG_KSZ=m
CONFIG_NET_DSA_TAG_OCELOT=m
CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
CONFIG_NET_DSA_TAG_QCA=m
CONFIG_NET_DSA_TAG_RTL4_A=m
CONFIG_NET_DSA_TAG_RTL8_4=m
CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
CONFIG_NET_DSA_TAG_LAN9303=m
CONFIG_NET_DSA_TAG_SJA1105=m
CONFIG_NET_DSA_TAG_TRAILER=m
CONFIG_NET_DSA_TAG_XRS700X=m
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q_MVRP=y
CONFIG_LLC=y
CONFIG_LLC2=y
CONFIG_ATALK=m
# CONFIG_DEV_APPLETALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
CONFIG_6LOWPAN=m
# CONFIG_6LOWPAN_DEBUGFS is not set
CONFIG_6LOWPAN_NHC=m
CONFIG_6LOWPAN_NHC_DEST=m
CONFIG_6LOWPAN_NHC_FRAGMENT=m
CONFIG_6LOWPAN_NHC_HOP=m
CONFIG_6LOWPAN_NHC_IPV6=m
CONFIG_6LOWPAN_NHC_MOBILITY=m
CONFIG_6LOWPAN_NHC_ROUTING=m
CONFIG_6LOWPAN_NHC_UDP=m
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
CONFIG_6LOWPAN_GHC_UDP=m
CONFIG_6LOWPAN_GHC_ICMPV6=m
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
CONFIG_IEEE802154=m
CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_MAC802154=m
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFB=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_SKBPRIO=m
CONFIG_NET_SCH_CHOKE=m
CONFIG_NET_SCH_QFQ=m
CONFIG_NET_SCH_CODEL=m
CONFIG_NET_SCH_FQ_CODEL=y
CONFIG_NET_SCH_CAKE=y
CONFIG_NET_SCH_FQ=m
CONFIG_NET_SCH_HHF=m
CONFIG_NET_SCH_PIE=m
CONFIG_NET_SCH_FQ_PIE=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_SCH_PLUG=m
CONFIG_NET_SCH_ETS=m
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_PERF=y
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=y
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_EMATCH_IPSET=m
CONFIG_NET_EMATCH_IPT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_SAMPLE=m
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
CONFIG_NET_ACT_MPLS=m
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_NET_ACT_CONNMARK=m
CONFIG_NET_ACT_CTINFO=m
CONFIG_NET_ACT_SKBMOD=m
CONFIG_NET_ACT_IFE=m
CONFIG_NET_ACT_TUNNEL_KEY=m
CONFIG_NET_ACT_CT=m
CONFIG_NET_ACT_GATE=m
CONFIG_NET_IFE_SKBMARK=m
CONFIG_NET_IFE_SKBPRIO=m
CONFIG_NET_IFE_SKBTCINDEX=m
# CONFIG_NET_TC_SKB_EXT is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=m
CONFIG_BATMAN_ADV=m
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
CONFIG_BATMAN_ADV_NC=y
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUG is not set
# CONFIG_BATMAN_ADV_TRACING is not set
# CONFIG_OPENVSWITCH is not set
# CONFIG_VSOCKETS is not set
CONFIG_NETLINK_DIAG=y
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=m
CONFIG_MPLS_ROUTING=m
CONFIG_MPLS_IPTUNNEL=m
CONFIG_NET_NSH=m
# CONFIG_HSR is not set
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=m
# CONFIG_QRTR_SMD is not set
# CONFIG_QRTR_TUN is not set
CONFIG_QRTR_MHI=m
# CONFIG_NET_NCSI is not set
CONFIG_PCPU_DEV_REFCNT=y
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_XPS=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
CONFIG_NET_PKTGEN=m
# CONFIG_NET_DROP_MONITOR is not set
# end of Network testing
# end of Networking options

# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=m
CONFIG_BT_HS=y
CONFIG_BT_LE=y
CONFIG_BT_6LOWPAN=m
CONFIG_BT_LEDS=y
CONFIG_BT_MSFTEXT=y
# CONFIG_BT_AOSPEXT is not set
# CONFIG_BT_DEBUGFS is not set
CONFIG_BT_SELFTEST=y
CONFIG_BT_SELFTEST_ECDH=y
CONFIG_BT_SELFTEST_SMP=y

#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=m
CONFIG_BT_BCM=m
CONFIG_BT_RTL=m
CONFIG_BT_QCA=m
CONFIG_BT_MTK=m
CONFIG_BT_HCIBTUSB=m
# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
CONFIG_BT_HCIBTUSB_BCM=y
CONFIG_BT_HCIBTUSB_MTK=y
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_NOKIA=m
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_BCM=y
CONFIG_BT_HCIUART_RTL=y
CONFIG_BT_HCIUART_QCA=y
CONFIG_BT_HCIUART_AG6XX=y
CONFIG_BT_HCIUART_MRVL=y
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
CONFIG_BT_MTKSDIO=m
CONFIG_BT_MTKUART=m
CONFIG_BT_HCIRSI=m
CONFIG_BT_VIRTIO=m
# end of Bluetooth device drivers

CONFIG_AF_RXRPC=m
# CONFIG_AF_RXRPC_IPV6 is not set
# CONFIG_AF_RXRPC_INJECT_LOSS is not set
# CONFIG_AF_RXRPC_DEBUG is not set
# CONFIG_RXKAD is not set
CONFIG_AF_KCM=m
CONFIG_STREAM_PARSER=y
# CONFIG_MCTP is not set
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_SPY=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
CONFIG_CFG80211_HEADERS=y
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
CONFIG_CFG80211_CERTIFICATION_ONUS=y
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_EXTRA_REGDB_KEYDIR=""
CONFIG_CFG80211_REG_CELLULAR_HINTS=y
CONFIG_CFG80211_REG_RELAX_NO_IR=y
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_CFG80211_WEXT_EXPORT=y
CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
CONFIG_LIB80211_CRYPT_TKIP=m
CONFIG_LIB80211_DEBUG=y
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_MESSAGE_TRACING is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_RFKILL=m
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=m
CONFIG_RFKILL_GPIO_NEO=m
CONFIG_NET_9P=m
CONFIG_NET_9P_FD=m
CONFIG_NET_9P_VIRTIO=m
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
CONFIG_CEPH_LIB=m
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
# CONFIG_NFC is not set
CONFIG_PSAMPLE=m
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
# CONFIG_PAGE_POOL_STATS is not set
CONFIG_FAILOVER=y
CONFIG_SHORTCUT_FE=y
CONFIG_ETHTOOL_NETLINK=y

#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIEAER is not set
CONFIG_PCIEASPM=y
# CONFIG_PCIEASPM_DEFAULT is not set
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEASPM_PERFORMANCE=y
CONFIG_PCIE_PME=y
CONFIG_PCIE_PTM=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_STUB is not set
# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set
CONFIG_PCI_ECAM=y
# CONFIG_PCI_IOV is not set
# CONFIG_PCI_PRI is not set
# CONFIG_PCI_PASID is not set
CONFIG_PCI_LABEL=y
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
# CONFIG_HOTPLUG_PCI is not set

#
# PCI controller drivers
#
# CONFIG_PCI_FTPCI100 is not set
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
# CONFIG_PCIE_XILINX is not set
# CONFIG_PCI_XGENE is not set
# CONFIG_PCIE_ALTERA is not set
# CONFIG_PCI_HOST_THUNDER_PEM is not set
# CONFIG_PCI_HOST_THUNDER_ECAM is not set
CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_HOST=y
# CONFIG_PCIE_MICROCHIP_HOST is not set
# CONFIG_PCIE_HISI_ERR is not set

#
# DesignWare PCI Core Support
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_PLAT=y
CONFIG_PCIE_DW_PLAT_HOST=y
# CONFIG_PCI_HISI is not set
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
# CONFIG_PCIE_KIRIN is not set
CONFIG_PCI_MESON=y
# CONFIG_PCIE_AL is not set
# end of DesignWare PCI Core Support

#
# Mobiveil PCIe Core Support
#
# end of Mobiveil PCIe Core Support

#
# Cadence PCIe controllers support
#
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCI_J721E_HOST is not set
# end of Cadence PCIe controllers support
# end of PCI controller drivers

#
# PCI Endpoint
#
# CONFIG_PCI_ENDPOINT is not set
# end of PCI Endpoint

#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set
# end of PCI switch controller drivers

# CONFIG_CXL_BUS is not set
# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_DEVTMPFS_SAFE is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
CONFIG_FW_LOADER_COMPRESS=y
CONFIG_FW_LOADER_COMPRESS_XZ=y
CONFIG_FW_LOADER_COMPRESS_ZSTD=y
# CONFIG_FW_UPLOAD is not set
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_SPMI=m
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SCCB=m
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
CONFIG_BRCMSTB_GISB_ARB=y
# CONFIG_MOXTET is not set
CONFIG_SUN50I_DE2_BUS=y
CONFIG_SUNXI_RSB=y
CONFIG_VEXPRESS_CONFIG=y
CONFIG_MHI_BUS=m
# CONFIG_MHI_BUS_DEBUG is not set
# CONFIG_MHI_BUS_PCI_GENERIC is not set
# CONFIG_MHI_BUS_EP is not set
# end of Bus devices

CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y

#
# Firmware Drivers
#

#
# ARM System Control and Management Interface Protocol
#
CONFIG_ARM_SCMI_PROTOCOL=y
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
CONFIG_ARM_SCMI_HAVE_SHMEM=y
CONFIG_ARM_SCMI_HAVE_MSG=y
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set
CONFIG_ARM_SCMI_POWER_DOMAIN=y
# CONFIG_ARM_SCMI_POWER_CONTROL is not set
# end of ARM System Control and Management Interface Protocol

CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
CONFIG_ARM_SDE_INTERFACE=y
# CONFIG_FIRMWARE_MEMMAP is not set
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=y
# CONFIG_ISCSI_IBFT is not set
CONFIG_FW_CFG_SYSFS=y
CONFIG_FW_CFG_SYSFS_CMDLINE=y
CONFIG_SYSFB=y
# CONFIG_SYSFB_SIMPLEFB is not set
# CONFIG_ARM_FFA_TRANSPORT is not set
CONFIG_CS_DSP=y
# CONFIG_GOOGLE_FIRMWARE is not set

#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_VARS_PSTORE=y
# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_GENERIC_STUB=y
# CONFIG_EFI_ZBOOT is not set
CONFIG_EFI_ARMSTUB_DTB_LOADER=y
CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
CONFIG_EFI_BOOTLOADER_CONTROL=m
CONFIG_EFI_CAPSULE_LOADER=m
CONFIG_EFI_TEST=m
# CONFIG_RESET_ATTACK_MITIGATION is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
# CONFIG_EFI_DISABLE_RUNTIME is not set
# CONFIG_EFI_COCO_SECRET is not set
# end of EFI (Extensible Firmware Interface) Support

CONFIG_UEFI_CPER=y
CONFIG_UEFI_CPER_ARM=y
CONFIG_MESON_SM=y
CONFIG_MESON_GX_PM=y
CONFIG_ARM_PSCI_FW=y
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_ARM_SMCCC_SOC_ID=y

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_GNSS=m
CONFIG_GNSS_SERIAL=m
CONFIG_GNSS_MTK_SERIAL=m
CONFIG_GNSS_SIRF_SERIAL=m
CONFIG_GNSS_UBX_SERIAL=m
CONFIG_GNSS_USB=m
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_AFS_PARTS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y

#
# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
#
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_DATAFLASH is not set
CONFIG_MTD_MCHP23K256=m
# CONFIG_MTD_MCHP48L640 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
CONFIG_MTD_NAND_CORE=y
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
# CONFIG_MTD_SPI_NAND is not set

#
# ECC engine support
#
CONFIG_MTD_NAND_ECC=y
# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
CONFIG_MTD_NAND_ECC_MXIC=y
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
# CONFIG_MTD_UBI_BLOCK is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
# CONFIG_OF_CONFIGFS is not set
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_NULL_BLK=m
CONFIG_CDROM=m
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
CONFIG_ZRAM=m
# CONFIG_ZRAM_DEF_COMP_LZORLE is not set
CONFIG_ZRAM_DEF_COMP_ZSTD=y
# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
# CONFIG_ZRAM_DEF_COMP_LZO is not set
# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
# CONFIG_ZRAM_DEF_COMP_842 is not set
CONFIG_ZRAM_DEF_COMP="zstd"
# CONFIG_ZRAM_WRITEBACK is not set
# CONFIG_ZRAM_MEMORY_TRACKING is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
CONFIG_BLK_DEV_DRBD=m
CONFIG_DRBD_FAULT_INJECTION=y
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_VIRTIO_BLK=m
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_UBLK is not set

#
# NVME Support
#
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
# CONFIG_NVME_MULTIPATH is not set
# CONFIG_NVME_VERBOSE_ERRORS is not set
CONFIG_NVME_HWMON=y
CONFIG_NVME_FABRICS=m
# CONFIG_NVME_FC is not set
CONFIG_NVME_TCP=m
# CONFIG_NVME_AUTH is not set
CONFIG_NVME_TARGET=m
# CONFIG_NVME_TARGET_PASSTHRU is not set
CONFIG_NVME_TARGET_LOOP=m
# CONFIG_NVME_TARGET_FC is not set
CONFIG_NVME_TARGET_TCP=m
# CONFIG_NVME_TARGET_AUTH is not set
# end of NVME Support

#
# Misc devices
#
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
CONFIG_TIFM_CORE=m
CONFIG_TIFM_7XX1=m
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HI6421V600_IRQ is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
# CONFIG_DW_XDATA_PCIE is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_XILINX_SDFEC is not set
CONFIG_MISC_RTSX=m
# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_OPEN_DICE is not set
# CONFIG_VCPU_STALL_DETECTOR is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
CONFIG_EEPROM_AT25=m
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
CONFIG_EEPROM_93CX6=m
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

CONFIG_CB710_CORE=m
# CONFIG_CB710_DEBUG is not set
CONFIG_CB710_DEBUG_ASSUMPTIONS=y

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline

# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
# CONFIG_VMWARE_VMCI is not set
# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_BCM_VK is not set
# CONFIG_MISC_ALCOR_PCI is not set
# CONFIG_MISC_RTSX_PCI is not set
CONFIG_MISC_RTSX_USB=m
# CONFIG_HABANA_AI is not set
# CONFIG_UACCE is not set
# CONFIG_PVPANIC is not set
# CONFIG_GP_PCI1XXXX is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI_COMMON=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=m
CONFIG_BLK_DEV_BSG=y
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=m
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_ISCSI_BOOT_SYSFS=m
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_MPI3MR is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_FDOMAIN_PCI is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
CONFIG_SCSI_VIRTIO=m
# CONFIG_SCSI_DH is not set
# end of SCSI device support

CONFIG_ATA=y
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_ARCH_WANT_LIBATA_LEDS=y
CONFIG_ATA_LEDS=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_AHCI_DWC=y
CONFIG_AHCI_CEVA=m
CONFIG_AHCI_SUNXI=y
CONFIG_AHCI_QORIQ=m
CONFIG_SATA_INIC162X=m
CONFIG_SATA_ACARD_AHCI=m
CONFIG_SATA_SIL24=m
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#
# CONFIG_PDC_ADMA is not set
CONFIG_SATA_QSTOR=m
CONFIG_SATA_SX4=m
CONFIG_ATA_BMDMA=y

#
# SATA SFF controllers with BMDMA
#
# CONFIG_ATA_PIIX is not set
CONFIG_SATA_DWC=m
CONFIG_SATA_DWC_OLD_DMA=y
CONFIG_SATA_MV=m
CONFIG_SATA_NV=m
CONFIG_SATA_PROMISE=m
CONFIG_SATA_SIL=m
CONFIG_SATA_SIS=m
CONFIG_SATA_SVW=m
CONFIG_SATA_ULI=m
CONFIG_SATA_VIA=m
CONFIG_SATA_VITESSE=m

#
# PATA SFF controllers with BMDMA
#
# CONFIG_PATA_ALI is not set
# CONFIG_PATA_AMD is not set
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_ATP867X is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CYPRESS is not set
# CONFIG_PATA_EFAR is not set
# CONFIG_PATA_HPT366 is not set
# CONFIG_PATA_HPT37X is not set
# CONFIG_PATA_HPT3X2N is not set
# CONFIG_PATA_HPT3X3 is not set
# CONFIG_PATA_IT8213 is not set
# CONFIG_PATA_IT821X is not set
# CONFIG_PATA_JMICRON is not set
# CONFIG_PATA_MARVELL is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_OPTIDMA is not set
# CONFIG_PATA_PDC2027X is not set
# CONFIG_PATA_PDC_OLD is not set
# CONFIG_PATA_RADISYS is not set
# CONFIG_PATA_RDC is not set
# CONFIG_PATA_SCH is not set
# CONFIG_PATA_SERVERWORKS is not set
# CONFIG_PATA_SIL680 is not set
CONFIG_PATA_SIS=m
# CONFIG_PATA_TOSHIBA is not set
# CONFIG_PATA_TRIFLEX is not set
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set

#
# PIO-only SFF controllers
#
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_OF_PLATFORM is not set
# CONFIG_PATA_RZ1000 is not set

#
# Generic fallback / legacy drivers
#
# CONFIG_PATA_ACPI is not set
# CONFIG_ATA_GENERIC is not set
# CONFIG_PATA_LEGACY is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
CONFIG_MD_CLUSTER=m
CONFIG_BCACHE=m
# CONFIG_BCACHE_DEBUG is not set
# CONFIG_BCACHE_CLOSURES_DEBUG is not set
# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=m
# CONFIG_DM_DEBUG is not set
CONFIG_DM_BUFIO=m
# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
# CONFIG_DM_CACHE is not set
CONFIG_DM_WRITECACHE=m
# CONFIG_DM_EBS is not set
# CONFIG_DM_ERA is not set
# CONFIG_DM_CLONE is not set
CONFIG_DM_MIRROR=m
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
# CONFIG_DM_MULTIPATH_HST is not set
# CONFIG_DM_MULTIPATH_IOA is not set
CONFIG_DM_DELAY=m
# CONFIG_DM_DUST is not set
# CONFIG_DM_UEVENT is not set
CONFIG_DM_FLAKEY=m
CONFIG_DM_VERITY=m
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
# CONFIG_DM_VERITY_FEC is not set
# CONFIG_DM_SWITCH is not set
CONFIG_DM_LOG_WRITES=m
CONFIG_DM_INTEGRITY=m
CONFIG_DM_AUDIT=y
CONFIG_TARGET_CORE=m
# CONFIG_TCM_IBLOCK is not set
# CONFIG_TCM_FILEIO is not set
# CONFIG_TCM_PSCSI is not set
# CONFIG_LOOPBACK_TARGET is not set
CONFIG_ISCSI_TARGET=m
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
# end of IEEE 1394 (FireWire) support

CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_WIREGUARD=m
# CONFIG_WIREGUARD_DEBUG is not set
CONFIG_EQUALIZER=m
# CONFIG_NET_FC is not set
CONFIG_IFB=m
CONFIG_NET_TEAM=m
CONFIG_NET_TEAM_MODE_BROADCAST=m
CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
CONFIG_NET_TEAM_MODE_RANDOM=m
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
CONFIG_NET_TEAM_MODE_LOADBALANCE=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=m
CONFIG_IPVTAP=m
CONFIG_VXLAN=m
CONFIG_GENEVE=m
CONFIG_BAREUDP=m
CONFIG_GTP=m
CONFIG_AMT=m
CONFIG_MACSEC=m
CONFIG_NETCONSOLE=m
CONFIG_NETCONSOLE_DYNAMIC=y
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=m
CONFIG_TAP=m
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_NLMON=m
CONFIG_NET_VRF=m
# CONFIG_MHI_NET is not set
# CONFIG_ARCNET is not set

#
# Distributed Switch Architecture drivers
#
CONFIG_B53=m
CONFIG_B53_SPI_DRIVER=m
CONFIG_B53_MDIO_DRIVER=m
CONFIG_B53_MMAP_DRIVER=m
CONFIG_B53_SRAB_DRIVER=m
CONFIG_B53_SERDES=m
CONFIG_NET_DSA_BCM_SF2=m
CONFIG_NET_DSA_LOOP=m
CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
CONFIG_NET_DSA_LANTIQ_GSWIP=m
CONFIG_NET_DSA_MT7530=m
CONFIG_NET_DSA_MT7530_MDIO=m
CONFIG_NET_DSA_MT7530_MMIO=m
CONFIG_NET_DSA_MV88E6060=m
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
CONFIG_NET_DSA_MV88E6XXX=m
CONFIG_NET_DSA_MV88E6XXX_PTP=y
CONFIG_NET_DSA_AR9331=m
CONFIG_NET_DSA_QCA8K=m
CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y
CONFIG_NET_DSA_SJA1105=m
CONFIG_NET_DSA_SJA1105_PTP=y
CONFIG_NET_DSA_SJA1105_TAS=y
CONFIG_NET_DSA_SJA1105_VL=y
CONFIG_NET_DSA_XRS700X=m
CONFIG_NET_DSA_XRS700X_I2C=m
CONFIG_NET_DSA_XRS700X_MDIO=m
CONFIG_NET_DSA_REALTEK=m
CONFIG_NET_DSA_REALTEK_MDIO=m
CONFIG_NET_DSA_REALTEK_SMI=m
CONFIG_NET_DSA_REALTEK_RTL8365MB=m
CONFIG_NET_DSA_REALTEK_RTL8366RB=m
CONFIG_NET_DSA_SMSC_LAN9303=m
CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
CONFIG_NET_DSA_VITESSE_VSC73XX=m
CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
# end of Distributed Switch Architecture drivers

CONFIG_ETHERNET=y
CONFIG_MDIO=m
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
CONFIG_NET_VENDOR_ALLWINNER=y
CONFIG_SUN4I_EMAC=y
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_ALTERA_TSE is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
CONFIG_NET_VENDOR_ASIX=y
# CONFIG_SPI_AX88796C is not set
CONFIG_NET_VENDOR_ATHEROS=y
# CONFIG_ATL2 is not set
# CONFIG_ATL1 is not set
# CONFIG_ATL1E is not set
# CONFIG_ATL1C is not set
CONFIG_ALX=m
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_CORTINA is not set
CONFIG_NET_VENDOR_DAVICOM=y
# CONFIG_DM9051 is not set
# CONFIG_DNET is not set
# CONFIG_NET_VENDOR_DEC is not set
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
CONFIG_NET_VENDOR_ENGLEDER=y
# CONFIG_TSNEP is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_FREESCALE is not set
CONFIG_NET_VENDOR_FUNGIBLE=y
# CONFIG_FUN_ETH is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
CONFIG_NET_VENDOR_I825XX=y
CONFIG_NET_VENDOR_INTEL=y
# CONFIG_E100 is not set
CONFIG_E1000=m
CONFIG_E1000E=m
CONFIG_IGB=m
CONFIG_IGB_HWMON=y
CONFIG_IGBVF=m
# CONFIG_IXGB is not set
# CONFIG_IXGBE is not set
# CONFIG_IXGBEVF is not set
# CONFIG_I40E is not set
# CONFIG_I40EVF is not set
# CONFIG_ICE is not set
# CONFIG_FM10K is not set
CONFIG_IGC=m
# CONFIG_JME is not set
CONFIG_NET_VENDOR_ADI=y
# CONFIG_ADIN1110 is not set
CONFIG_NET_VENDOR_LITEX=y
# CONFIG_LITEX_LITEETH is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_MICROSOFT is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_FEALNX is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETERION is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_BROCADE is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCA7000_UART is not set
CONFIG_QCOM_EMAC=m
CONFIG_SFE_SUPPORT_IPV6=y
CONFIG_SFE_ECM=y
CONFIG_FAST_CLASSIFIER=y
# CONFIG_RMNET is not set
# CONFIG_NET_VENDOR_RDC is not set
CONFIG_NET_VENDOR_REALTEK=y
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
# CONFIG_R8169 is not set
CONFIG_R8125=m
CONFIG_R8125_SOC_LAN=y
# CONFIG_R8125_REALWOW_SUPPORT is not set
# CONFIG_R8125_DASH_SUPPORT is not set
# CONFIG_R8125_DOWN_SPEED_100 is not set
# CONFIG_R8125_ASPM is not set
CONFIG_R8125_WOL_SUPPORT=y
CONFIG_R8125_S5WOL=y
# CONFIG_R8125_S5_KEEP_CURR_MAC is not set
# CONFIG_R8125_EEE is not set
# CONFIG_R8125_S0_MAGIC_PACKET is not set
CONFIG_R8125_TX_NO_CLOSE=y
CONFIG_R8125_MULTI_MSIX_VECTOR=y
CONFIG_R8125_MULTIPLE_TX_QUEUE=y
CONFIG_R8125_RSS_SUPPORT=y
# CONFIG_R8125_PTP_SUPPORT is not set
CONFIG_R8125_FIBER_SUPPORT=y
CONFIG_R8125_USE_FIRMWARE_FILE=y
# CONFIG_R8125_DOUBLE_VLAN is not set
# CONFIG_R8125_PAGE_REUSE is not set
CONFIG_R8125_GIGA_LITE=y
CONFIG_R8126=m
CONFIG_R8126_SOC_LAN=y
# CONFIG_R8126_REALWOW_SUPPORT is not set
# CONFIG_R8126_DASH_SUPPORT is not set
# CONFIG_R8126_DOWN_SPEED_100 is not set
# CONFIG_R8126_ASPM is not set
CONFIG_R8126_WOL_SUPPORT=y
CONFIG_R8126_S5WOL=y
# CONFIG_R8126_S5_KEEP_CURR_MAC is not set
# CONFIG_R8126_EEE is not set
# CONFIG_R8126_S0_MAGIC_PACKET is not set
CONFIG_R8126_TX_NO_CLOSE=y
CONFIG_R8126_MULTI_MSIX_VECTOR=y
CONFIG_R8126_MULTIPLE_TX_QUEUE=y
CONFIG_R8126_RSS_SUPPORT=y
CONFIG_R8126_PTP_SUPPORT=y
CONFIG_R8126_FIBER_SUPPORT=y
CONFIG_R8126_USE_FIRMWARE_FILE=y
# CONFIG_R8126_DOUBLE_VLAN is not set
# CONFIG_R8126_PAGE_REUSE is not set
CONFIG_R8126_GIGA_LITE=y
CONFIG_R8168=m
# CONFIG_R8168_SOC_LAN is not set
# CONFIG_R8168_FIBER_SUPPORT is not set
# CONFIG_R8168_REALWOW_SUPPORT is not set
# CONFIG_R8168_DASH_SUPPORT is not set
# CONFIG_R8168_DOWN_SPEED_100 is not set
CONFIG_R8168_ASPM=y
CONFIG_R8168_DYNAMIC_ASPM=y
CONFIG_R8168_WOL_SUPPORT=y
CONFIG_R8168_S5WOL=y
# CONFIG_R8168_S5_KEEP_CURR_MAC is not set
CONFIG_R8168_EEE=y
# CONFIG_R8168_S0_MAGIC_PACKET is not set
CONFIG_R8168_USE_FIRMWARE_FILE=y
# CONFIG_R8168_CTAP_SHORT_OFF is not set
CONFIG_R8168_MULTIPLE_TX_QUEUE=y
CONFIG_R8168_RSS_SUPPORT=y
CONFIG_R8168_GIGA_LITE=y
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_SELFTESTS=y
CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_MESON=y
CONFIG_DWMAC_ROCKCHIP=y
CONFIG_DWMAC_SUNXI=y
CONFIG_DWMAC_SUN8I=y
# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
CONFIG_NET_VENDOR_VERTEXCOM=y
# CONFIG_MSE102X is not set
# CONFIG_NET_VENDOR_VIA is not set
CONFIG_NET_VENDOR_WANGXUN=y
# CONFIG_NGBE is not set
# CONFIG_TXGBE is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_NET_SB1000 is not set
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_PHYLIB_LEDS=y
CONFIG_FIXED_PHY=y
# CONFIG_SFP is not set

#
# MII PHY device drivers
#
CONFIG_AIR_EN8811H_PHY=m
# CONFIG_AMD_PHY is not set
CONFIG_MESON_GXL_PHY=y
# CONFIG_ADIN_PHY is not set
# CONFIG_ADIN1100_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
CONFIG_AX88796B_PHY=m
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM54140_PHY is not set
CONFIG_BCM7XXX_PHY=m
# CONFIG_BCM84881_PHY is not set
# CONFIG_BCM87XX_PHY is not set
CONFIG_BCM_NET_PHYLIB=m
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
CONFIG_ICPLUS_PHY=y
CONFIG_JLSEMI_PHY=y
# CONFIG_LXT_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MARVELL_88X2222_PHY is not set
# CONFIG_MAXLINEAR_GPHY is not set
CONFIG_MEDIATEK_GE_PHY=m
# CONFIG_MICREL_PHY is not set
CONFIG_MICROCHIP_PHY=m
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
CONFIG_MOTORCOMM_PHY=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_NXP_C45_TJA11XX_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
CONFIG_QCOM_NET_PHYLIB=m
# CONFIG_AT803X_PHY is not set
CONFIG_QCA83XX_PHY=m
CONFIG_QCA808X_PHY=m
CONFIG_QCA807X_PHY=m
# CONFIG_QSEMI_PHY is not set
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
CONFIG_SMSC_PHY=m
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
# CONFIG_DP83869_PHY is not set
# CONFIG_DP83TD510_PHY is not set
CONFIG_VITESSE_PHY=m
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_PSE_CONTROLLER is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_FWNODE_MDIO=y
CONFIG_OF_MDIO=y
CONFIG_ACPI_MDIO=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_SUN4I=y
CONFIG_MDIO_BITBANG=m
CONFIG_MDIO_BCM_UNIMAC=m
CONFIG_MDIO_GPIO=m
# CONFIG_MDIO_HISI_FEMAC is not set
CONFIG_MDIO_MVUSB=m
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_OCTEON is not set
CONFIG_MDIO_IPQ4019=m
CONFIG_MDIO_IPQ8064=m
# CONFIG_MDIO_THUNDER is not set

#
# MDIO Multiplexers
#
CONFIG_MDIO_BUS_MUX=y
CONFIG_MDIO_BUS_MUX_MESON_G12A=y
CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y

#
# PCS device drivers
#
CONFIG_PCS_XPCS=y
CONFIG_PCS_MTK_USXGMII=m
CONFIG_PCS_MTK_LYNXI=m
# end of PCS device drivers

CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=m
CONFIG_PPTP=m
CONFIG_PPPOL2TP=m
CONFIG_PPP_ASYNC=m
# CONFIG_PPP_SYNC_TTY is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=m
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_AX8817X=m
CONFIG_USB_NET_AX88179_178A=m
CONFIG_USB_NET_CDCETHER=m
CONFIG_USB_NET_CDC_EEM=m
CONFIG_USB_NET_CDC_NCM=m
CONFIG_USB_NET_HUAWEI_CDC_NCM=m
CONFIG_USB_NET_CDC_MBIM=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9700=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
CONFIG_USB_NET_CDC_SUBSET=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
CONFIG_USB_EPSON2888=y
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=m
CONFIG_USB_NET_CX82310_ETH=m
CONFIG_USB_NET_KALMIA=m
CONFIG_USB_NET_QMI_WWAN=m
CONFIG_USB_HSO=m
CONFIG_USB_NET_INT51X1=m
CONFIG_USB_IPHETH=m
CONFIG_USB_SIERRA_NET=m
CONFIG_USB_VL600=m
CONFIG_USB_NET_CH9200=m
CONFIG_USB_NET_AQC111=m
CONFIG_USB_RTL8153_ECM=m
CONFIG_WLAN=y
CONFIG_WLAN_VENDOR_ADMTEK=y
CONFIG_ADM8211=m
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
CONFIG_ATH_USER_REGD=y
# CONFIG_ATH_DEBUG is not set
CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS=y
# CONFIG_ATH_REG_DYNAMIC_USER_CERT_TESTING is not set
CONFIG_ATH5K=m
# CONFIG_ATH5K_DEBUG is not set
# CONFIG_ATH5K_TRACER is not set
CONFIG_ATH5K_PCI=y
# CONFIG_ATH5K_TEST_CHANNELS is not set
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=m
CONFIG_ATH9K_PCI=y
CONFIG_ATH9K_AHB=y
# CONFIG_ATH9K_DEBUGFS is not set
CONFIG_ATH9K_DFS_CERTIFIED=y
CONFIG_ATH9K_DYNACK=y
# CONFIG_ATH9K_WOW is not set
CONFIG_ATH9K_RFKILL=y
CONFIG_ATH9K_CHANNEL_CONTEXT=y
# CONFIG_ATH9K_PCOEM is not set
CONFIG_ATH9K_PCI_NO_EEPROM=m
CONFIG_ATH9K_HTC=m
# CONFIG_ATH9K_HTC_DEBUGFS is not set
CONFIG_ATH9K_HWRNG=y
CONFIG_CARL9170=m
CONFIG_CARL9170_LEDS=y
CONFIG_CARL9170_WPC=y
CONFIG_CARL9170_HWRNG=y
CONFIG_ATH6KL=m
CONFIG_ATH6KL_SDIO=m
CONFIG_ATH6KL_USB=m
# CONFIG_ATH6KL_DEBUG is not set
# CONFIG_ATH6KL_TRACING is not set
# CONFIG_ATH6KL_REGDOMAIN is not set
CONFIG_AR5523=m
# CONFIG_WIL6210 is not set
CONFIG_ATH10K=m
CONFIG_ATH10K_CE=y
CONFIG_ATH10K_PCI=m
# CONFIG_ATH10K_AHB is not set
CONFIG_ATH10K_SDIO=m
CONFIG_ATH10K_USB=m
# CONFIG_ATH10K_DEBUG is not set
# CONFIG_ATH10K_DEBUGFS is not set
# CONFIG_ATH10K_TRACING is not set
CONFIG_ATH10K_DFS_CERTIFIED=y
CONFIG_WCN36XX=m
# CONFIG_WCN36XX_DEBUGFS is not set
CONFIG_ATH11K=m
# CONFIG_ATH11K_AHB is not set
CONFIG_ATH11K_PCI=m
# CONFIG_ATH11K_DEBUG is not set
# CONFIG_ATH11K_TRACING is not set
CONFIG_WLAN_VENDOR_ATMEL=y
# CONFIG_ATMEL is not set
CONFIG_AT76C50X_USB=m
CONFIG_WLAN_VENDOR_BROADCOM=y
# CONFIG_B43 is not set
# CONFIG_B43LEGACY is not set
CONFIG_BRCMUTIL=m
# CONFIG_BRCMSMAC is not set
CONFIG_BRCMFMAC=m
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
# CONFIG_BRCMFMAC_PCIE is not set
CONFIG_BRCM_TRACING=y
CONFIG_BRCMDBG=y
# CONFIG_WLAN_VENDOR_CISCO is not set
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_IPW2100=m
# CONFIG_IPW2100_MONITOR is not set
# CONFIG_IPW2100_DEBUG is not set
CONFIG_IPW2200=m
# CONFIG_IPW2200_MONITOR is not set
# CONFIG_IPW2200_QOS is not set
# CONFIG_IPW2200_DEBUG is not set
CONFIG_LIBIPW=m
# CONFIG_LIBIPW_DEBUG is not set
CONFIG_IWLEGACY=m
CONFIG_IWL4965=m
CONFIG_IWL3945=m

#
# iwl3945 / iwl4965 Debugging Options
#
# CONFIG_IWLEGACY_DEBUG is not set
# end of iwl3945 / iwl4965 Debugging Options

CONFIG_IWLWIFI=m
CONFIG_IWLWIFI_LEDS=y
CONFIG_IWLDVM=m
CONFIG_IWLMVM=m
CONFIG_IWLWIFI_OPMODE_MODULAR=y

#
# Debugging Options
#
# CONFIG_IWLWIFI_DEBUG is not set
# CONFIG_IWLWIFI_DEVICE_TRACING is not set
# end of Debugging Options

CONFIG_WLAN_VENDOR_INTERSIL=y
CONFIG_HOSTAP=m
# CONFIG_HOSTAP_FIRMWARE is not set
CONFIG_HOSTAP_PLX=m
CONFIG_HOSTAP_PCI=m
CONFIG_HERMES=m
CONFIG_HERMES_PRISM=y
CONFIG_HERMES_CACHE_FW_ON_INIT=y
CONFIG_PLX_HERMES=m
CONFIG_TMD_HERMES=m
CONFIG_NORTEL_HERMES=m
CONFIG_PCI_HERMES=m
CONFIG_ORINOCO_USB=m
CONFIG_P54_COMMON=m
CONFIG_P54_USB=m
CONFIG_P54_PCI=m
CONFIG_P54_SPI=m
# CONFIG_P54_SPI_DEFAULT_EEPROM is not set
CONFIG_P54_LEDS=y
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_USB=m
CONFIG_LIBERTAS_SDIO=m
CONFIG_LIBERTAS_SPI=m
# CONFIG_LIBERTAS_DEBUG is not set
CONFIG_LIBERTAS_MESH=y
CONFIG_LIBERTAS_THINFIRM=m
# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
CONFIG_LIBERTAS_THINFIRM_USB=m
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_SDIO=m
CONFIG_MWIFIEX_PCIE=m
CONFIG_MWIFIEX_USB=m
CONFIG_MWL8K=m
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=m
CONFIG_MT76_CORE=m
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=m
CONFIG_MT76_SDIO=m
CONFIG_MT76x02_LIB=m
CONFIG_MT76x02_USB=m
CONFIG_MT76_CONNAC_LIB=m
CONFIG_MT76x0_COMMON=m
CONFIG_MT76x0U=m
CONFIG_MT76x0E=m
CONFIG_MT76x2_COMMON=m
CONFIG_MT76x2E=m
CONFIG_MT76x2U=m
CONFIG_MT7603E=m
CONFIG_MT7615_COMMON=m
CONFIG_MT7615E=m
CONFIG_MT7663_USB_SDIO_COMMON=m
CONFIG_MT7663U=m
CONFIG_MT7663S=m
CONFIG_MT7915E=m
CONFIG_MT7921_COMMON=m
CONFIG_MT7921E=m
CONFIG_MT7921S=m
CONFIG_MT7921U=m
CONFIG_WLAN_VENDOR_MICROCHIP=y
CONFIG_WILC1000=m
CONFIG_WILC1000_SDIO=m
# CONFIG_WILC1000_SPI is not set
# CONFIG_WILC1000_HW_OOB_INTR is not set
CONFIG_WLAN_VENDOR_PURELIFI=y
# CONFIG_PLFXLC is not set
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=m
# CONFIG_RT2400PCI is not set
# CONFIG_RT2500PCI is not set
# CONFIG_RT61PCI is not set
CONFIG_RT2800PCI=m
CONFIG_RT2800PCI_RT33XX=y
CONFIG_RT2800PCI_RT35XX=y
CONFIG_RT2800PCI_RT53XX=y
CONFIG_RT2800PCI_RT3290=y
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
CONFIG_RT2800USB_RT33XX=y
CONFIG_RT2800USB_RT35XX=y
CONFIG_RT2800USB_RT3573=y
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
CONFIG_RT2800USB_UNKNOWN=y
CONFIG_RT2800_LIB=m
CONFIG_RT2800_LIB_MMIO=m
CONFIG_RT2X00_LIB_MMIO=m
CONFIG_RT2X00_LIB_PCI=m
CONFIG_RT2X00_LIB_USB=m
CONFIG_RT2X00_LIB=m
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
# CONFIG_RT2X00_DEBUG is not set
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_RTL8180=m
CONFIG_RTL8187=m
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=m
CONFIG_RTL8192CE=m
CONFIG_RTL8192SE=m
CONFIG_RTL8192DE=m
CONFIG_RTL8723AE=m
CONFIG_RTL8723BE=m
CONFIG_RTL8188EE=m
CONFIG_RTL8192EE=m
CONFIG_RTL8821AE=m
CONFIG_RTL8192CU=m
CONFIG_RTLWIFI=m
CONFIG_RTLWIFI_PCI=m
CONFIG_RTLWIFI_USB=m
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8723_COMMON=m
CONFIG_RTLBTCOEXIST=m
CONFIG_RTL8XXXU=m
# CONFIG_RTL8XXXU_UNTESTED is not set
CONFIG_RTW88=m
CONFIG_RTW88_CORE=m
CONFIG_RTW88_PCI=m
CONFIG_RTW88_SDIO=m
CONFIG_RTW88_USB=m
CONFIG_RTW88_8822B=m
CONFIG_RTW88_8822C=m
CONFIG_RTW88_8723D=m
CONFIG_RTW88_8821C=m
CONFIG_RTW88_8822BE=m
CONFIG_RTW88_8822BS=m
CONFIG_RTW88_8822BU=m
CONFIG_RTW88_8822CE=m
CONFIG_RTW88_8822CS=m
CONFIG_RTW88_8822CU=m
CONFIG_RTW88_8723DE=m
CONFIG_RTW88_8723DU=m
CONFIG_RTW88_8821CE=m
CONFIG_RTW88_8821CS=m
CONFIG_RTW88_8821CU=m
# CONFIG_RTW88_DEBUG is not set
# CONFIG_RTW88_DEBUGFS is not set
CONFIG_RTW89=m
CONFIG_RTW89_CORE=m
CONFIG_RTW89_PCI=m
CONFIG_RTW89_8851B=m
CONFIG_RTW89_8852A=m
CONFIG_RTW89_8852B=m
CONFIG_RTW89_8852C=m
CONFIG_RTW89_8851BE=m
CONFIG_RTW89_8852AE=m
CONFIG_RTW89_8852BE=m
CONFIG_RTW89_8852CE=m
# CONFIG_RTW89_DEBUGMSG is not set
# CONFIG_RTW89_DEBUGFS is not set
CONFIG_WLAN_VENDOR_RSI=y
CONFIG_RSI_91X=m
CONFIG_RSI_DEBUGFS=y
CONFIG_RSI_SDIO=m
CONFIG_RSI_USB=m
CONFIG_RSI_COEX=y
CONFIG_WLAN_VENDOR_SILABS=y
# CONFIG_WFX is not set
CONFIG_WLAN_VENDOR_ST=y
CONFIG_CW1200=m
CONFIG_CW1200_WLAN_SDIO=m
CONFIG_CW1200_WLAN_SPI=m
CONFIG_WLAN_VENDOR_TI=y
CONFIG_WL1251=m
# CONFIG_WL1251_SPI is not set
CONFIG_WL1251_SDIO=m
# CONFIG_WL12XX is not set
# CONFIG_WL18XX is not set
CONFIG_WLCORE=m
# CONFIG_WLCORE_SPI is not set
CONFIG_WLCORE_SDIO=m
CONFIG_WILINK_PLATFORM_DATA=y
CONFIG_WLAN_VENDOR_ZYDAS=y
CONFIG_USB_ZD1201=m
CONFIG_ZD1211RW=m
# CONFIG_ZD1211RW_DEBUG is not set
CONFIG_WLAN_VENDOR_QUANTENNA=y
CONFIG_QTNFMAC=m
CONFIG_QTNFMAC_PCIE=m
CONFIG_MAC80211_HWSIM=m
CONFIG_USB_NET_RNDIS_WLAN=m
CONFIG_VIRT_WIFI=m
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
CONFIG_IEEE802154_AT86RF230=m
CONFIG_IEEE802154_MRF24J40=m
CONFIG_IEEE802154_CC2520=m
CONFIG_IEEE802154_ATUSB=m
CONFIG_IEEE802154_ADF7242=m
CONFIG_IEEE802154_CA8210=m
CONFIG_IEEE802154_CA8210_DEBUGFS=y
CONFIG_IEEE802154_MCR20A=m
CONFIG_IEEE802154_HWSIM=m

#
# Wireless WAN
#
CONFIG_WWAN=m
CONFIG_WWAN_DEBUGFS=y
CONFIG_WWAN_HWSIM=m
CONFIG_MHI_WWAN_CTRL=m
CONFIG_MHI_WWAN_MBIM=m
CONFIG_RPMSG_WWAN_CTRL=m
CONFIG_IOSM=m
CONFIG_MTK_T7XX=m
# end of Wireless WAN

CONFIG_VMXNET3=m
# CONFIG_FUJITSU_ES is not set
CONFIG_NETDEVSIM=m
CONFIG_NET_FAILOVER=m
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_SPARSEKMAP is not set
CONFIG_INPUT_MATRIXKMAP=m
CONFIG_INPUT_VIVALDIFMAP=m

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADC is not set
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_GPIO_BUTTON_HOTPLUG is not set
CONFIG_KEYBOARD_GPIO_POLLED=y
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_PINEPHONE is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
CONFIG_KEYBOARD_SUN4I_LRADC=y
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_KEYBOARD_CYPRESS_SF is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=m
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
CONFIG_MOUSE_PS2_SENTELIC=y
CONFIG_MOUSE_PS2_TOUCHKIT=y
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_SMBUS=y
CONFIG_MOUSE_SERIAL=m
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=m
CONFIG_MOUSE_ELAN_I2C=m
CONFIG_MOUSE_ELAN_I2C_I2C=y
CONFIG_MOUSE_ELAN_I2C_SMBUS=y
CONFIG_MOUSE_VSXXXAA=m
CONFIG_MOUSE_GPIO=m
CONFIG_MOUSE_SYNAPTICS_I2C=m
CONFIG_MOUSE_SYNAPTICS_USB=m
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_ANALOG=m
CONFIG_JOYSTICK_A3D=m
CONFIG_JOYSTICK_ADC=m
CONFIG_JOYSTICK_ADI=m
CONFIG_JOYSTICK_COBRA=m
CONFIG_JOYSTICK_GF2K=m
CONFIG_JOYSTICK_GRIP=m
CONFIG_JOYSTICK_GRIP_MP=m
CONFIG_JOYSTICK_GUILLEMOT=m
CONFIG_JOYSTICK_INTERACT=m
CONFIG_JOYSTICK_SIDEWINDER=m
CONFIG_JOYSTICK_TMDC=m
CONFIG_JOYSTICK_IFORCE=m
CONFIG_JOYSTICK_IFORCE_USB=m
CONFIG_JOYSTICK_IFORCE_232=m
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
CONFIG_JOYSTICK_STINGER=m
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
CONFIG_JOYSTICK_AS5011=m
CONFIG_JOYSTICK_JOYDUMP=m
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_JOYSTICK_PSXPAD_SPI=m
CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
CONFIG_JOYSTICK_PXRC=m
CONFIG_JOYSTICK_QWIIC=m
CONFIG_JOYSTICK_FSIA6B=m
CONFIG_JOYSTICK_SENSEHAT=m
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=m
CONFIG_TOUCHSCREEN_AD7877=m
CONFIG_TOUCHSCREEN_AD7879=m
CONFIG_TOUCHSCREEN_AD7879_I2C=m
CONFIG_TOUCHSCREEN_AD7879_SPI=m
CONFIG_TOUCHSCREEN_ADC=m
CONFIG_TOUCHSCREEN_AR1021_I2C=m
CONFIG_TOUCHSCREEN_ATMEL_MXT=m
CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y
CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
CONFIG_TOUCHSCREEN_BU21013=m
CONFIG_TOUCHSCREEN_BU21029=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
CONFIG_TOUCHSCREEN_CY8CTMA140=m
CONFIG_TOUCHSCREEN_CY8CTMG110=m
CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
CONFIG_TOUCHSCREEN_DYNAPRO=m
CONFIG_TOUCHSCREEN_HAMPSHIRE=m
CONFIG_TOUCHSCREEN_EETI=m
CONFIG_TOUCHSCREEN_EGALAX=m
CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
CONFIG_TOUCHSCREEN_EXC3000=m
CONFIG_TOUCHSCREEN_FUJITSU=m
CONFIG_TOUCHSCREEN_GOODIX=m
CONFIG_TOUCHSCREEN_HIDEEP=m
CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
CONFIG_TOUCHSCREEN_ILI210X=m
CONFIG_TOUCHSCREEN_ILITEK=m
CONFIG_TOUCHSCREEN_S6SY761=m
CONFIG_TOUCHSCREEN_GUNZE=m
CONFIG_TOUCHSCREEN_EKTF2127=m
CONFIG_TOUCHSCREEN_ELAN=m
CONFIG_TOUCHSCREEN_ELO=m
CONFIG_TOUCHSCREEN_WACOM_W8001=m
CONFIG_TOUCHSCREEN_WACOM_I2C=m
CONFIG_TOUCHSCREEN_MAX11801=m
CONFIG_TOUCHSCREEN_MCS5000=m
CONFIG_TOUCHSCREEN_MMS114=m
CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
CONFIG_TOUCHSCREEN_MSG2638=m
CONFIG_TOUCHSCREEN_MTOUCH=m
CONFIG_TOUCHSCREEN_IMAGIS=m
CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
CONFIG_TOUCHSCREEN_INEXIO=m
CONFIG_TOUCHSCREEN_MK712=m
CONFIG_TOUCHSCREEN_PENMOUNT=m
CONFIG_TOUCHSCREEN_EDT_FT5X06=m
CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
CONFIG_TOUCHSCREEN_TOUCHWIN=m
CONFIG_TOUCHSCREEN_PIXCIR=m
CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
CONFIG_TOUCHSCREEN_WM97XX=m
CONFIG_TOUCHSCREEN_WM9705=y
CONFIG_TOUCHSCREEN_WM9712=y
CONFIG_TOUCHSCREEN_WM9713=y
CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
CONFIG_TOUCHSCREEN_TOUCHIT213=m
CONFIG_TOUCHSCREEN_TSC_SERIO=m
CONFIG_TOUCHSCREEN_TSC200X_CORE=m
CONFIG_TOUCHSCREEN_TSC2004=m
CONFIG_TOUCHSCREEN_TSC2005=m
CONFIG_TOUCHSCREEN_TSC2007=m
CONFIG_TOUCHSCREEN_TSC2007_IIO=y
CONFIG_TOUCHSCREEN_RM_TS=m
CONFIG_TOUCHSCREEN_SILEAD=m
CONFIG_TOUCHSCREEN_SIS_I2C=m
CONFIG_TOUCHSCREEN_ST1232=m
CONFIG_TOUCHSCREEN_STMFTS=m
CONFIG_TOUCHSCREEN_SUN4I=y
CONFIG_TOUCHSCREEN_SUR40=m
CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
CONFIG_TOUCHSCREEN_SX8654=m
CONFIG_TOUCHSCREEN_TPS6507X=m
CONFIG_TOUCHSCREEN_ZET6223=m
CONFIG_TOUCHSCREEN_ZFORCE=m
CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
CONFIG_TOUCHSCREEN_ROHM_BU21023=m
CONFIG_TOUCHSCREEN_IQS5XX=m
CONFIG_TOUCHSCREEN_ZINITIX=m
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
# CONFIG_INPUT_BMA150 is not set
# CONFIG_INPUT_E3X0_BUTTON is not set
# CONFIG_INPUT_MMA8450 is not set
CONFIG_INPUT_GPIO_BEEPER=m
CONFIG_INPUT_GPIO_DECODER=m
CONFIG_INPUT_GPIO_VIBRA=m
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
# CONFIG_INPUT_KXTJ9 is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
CONFIG_INPUT_CM109=m
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
CONFIG_INPUT_AXP20X_PEK=y
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_PCF8574 is not set
CONFIG_INPUT_PWM_BEEPER=m
CONFIG_INPUT_PWM_VIBRA=m
CONFIG_INPUT_RK805_PWRKEY=y
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_DA7280_HAPTICS is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_IBM_PANEL is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_INPUT_IQS269A is not set
# CONFIG_INPUT_IQS626A is not set
# CONFIG_INPUT_IQS7222 is not set
# CONFIG_INPUT_CMA3000 is not set
# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
# CONFIG_INPUT_DRV260X_HAPTICS is not set
# CONFIG_INPUT_DRV2665_HAPTICS is not set
# CONFIG_INPUT_DRV2667_HAPTICS is not set
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=y
CONFIG_RMI4_SPI=y
CONFIG_RMI4_SMB=y
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=y
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
CONFIG_RMI4_F3A=y
CONFIG_RMI4_F54=y
CONFIG_RMI4_F55=y

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=m
# CONFIG_SERIO_AMBAKMI is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=m
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
CONFIG_SERIO_SUN4I_PS2=y
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
CONFIG_GAMEPORT=m
# CONFIG_GAMEPORT_NS558 is not set
# CONFIG_GAMEPORT_L4 is not set
# CONFIG_GAMEPORT_EMU10K1 is not set
# CONFIG_GAMEPORT_FM801 is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=5
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_RSA is not set
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_8250_PERICOM=y
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
CONFIG_SERIAL_AMBA_PL010=y
CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y
CONFIG_SERIAL_MESON=y
CONFIG_SERIAL_MESON_CONSOLE=y
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_QE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_NOZOMI is not set
# CONFIG_NULL_TTY is not set
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
# CONFIG_RPMSG_TTY is not set
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_TTY_PRINTK is not set
CONFIG_VIRTIO_CONSOLE=m
# CONFIG_IPMI_HANDLER is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=y
# CONFIG_HW_RANDOM_BA431 is not set
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_ROCKCHIP=y
CONFIG_HW_RANDOM_ROCKCHIP_RK3568=y
CONFIG_HW_RANDOM_MESON=y
CONFIG_HW_RANDOM_OPTEE=y
# CONFIG_HW_RANDOM_CCTRNG is not set
# CONFIG_HW_RANDOM_XIPHERA is not set
CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
CONFIG_HW_RANDOM_CN10K=y
# CONFIG_APPLICOM is not set
CONFIG_DEVMEM=y
CONFIG_DEVPORT=y
# CONFIG_TCG_TPM is not set
# CONFIG_XILLYBUS is not set
# CONFIG_XILLYUSB is not set
CONFIG_RANDOM_TRUST_CPU=y
CONFIG_RANDOM_TRUST_BOOTLOADER=y
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_I2C_MUX_GPIO=y
CONFIG_I2C_MUX_GPMUX=y
CONFIG_I2C_MUX_LTC4306=m
CONFIG_I2C_MUX_PCA9541=m
CONFIG_I2C_MUX_PCA954x=m
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_MUX_REG=y
CONFIG_I2C_DEMUX_PINCTRL=y
CONFIG_I2C_MUX_MLXCPLD=m
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_ALGOBIT=y

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
CONFIG_I2C_CCGX_UCSI=m
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set

#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CADENCE is not set
# CONFIG_I2C_CBUS_GPIO is not set
CONFIG_I2C_DESIGNWARE_CORE=y
CONFIG_I2C_DESIGNWARE_SLAVE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_DESIGNWARE_PCI=m
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=y
CONFIG_I2C_GPIO_FAULT_INJECTOR=y
# CONFIG_I2C_HISI is not set
CONFIG_I2C_MESON=y
CONFIG_I2C_MV64XXX=y
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
CONFIG_I2C_RK3X=y
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_THUNDERX is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_CP2615 is not set
# CONFIG_I2C_PCI1XXXX is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
CONFIG_I2C_VIRTIO=m
# end of I2C Hardware Bus support

# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=m
CONFIG_I2C_SLAVE_TESTUNIT=m
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

# CONFIG_I3C is not set
CONFIG_SPI=y
CONFIG_SPI_DEBUG=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y

#
# SPI Master Controller Drivers
#
CONFIG_SPI_ALTERA=m
CONFIG_SPI_ALTERA_CORE=m
# CONFIG_SPI_ALTERA_DFL is not set
CONFIG_SPI_AXI_SPI_ENGINE=m
CONFIG_SPI_BITBANG=m
CONFIG_SPI_CADENCE=m
CONFIG_SPI_CADENCE_QUADSPI=m
CONFIG_SPI_CADENCE_XSPI=m
CONFIG_SPI_DESIGNWARE=m
CONFIG_SPI_DW_DMA=y
# CONFIG_SPI_DW_PCI is not set
CONFIG_SPI_DW_MMIO=m
# CONFIG_SPI_HISI_KUNPENG is not set
# CONFIG_SPI_HISI_SFC_V3XX is not set
CONFIG_SPI_NXP_FLEXSPI=m
CONFIG_SPI_GPIO=m
CONFIG_SPI_FSL_LIB=m
CONFIG_SPI_FSL_SPI=m
CONFIG_SPI_MESON_SPICC=y
CONFIG_SPI_MESON_SPIFC=y
# CONFIG_SPI_MICROCHIP_CORE is not set
# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
CONFIG_SPI_OC_TINY=m
CONFIG_SPI_PL022=m
CONFIG_SPI_PXA2XX=m
CONFIG_SPI_PXA2XX_PCI=m
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_ROCKCHIP_SFC=m
CONFIG_SPI_SC18IS602=m
CONFIG_SPI_SIFIVE=m
CONFIG_SPI_SUN4I=y
CONFIG_SPI_SUN6I=y
CONFIG_SPI_MXIC=m
CONFIG_SPI_THUNDERX=m
CONFIG_SPI_XCOMM=m
CONFIG_SPI_XILINX=m
CONFIG_SPI_ZYNQMP_GQSPI=m
CONFIG_SPI_AMD=m

#
# SPI Multiplexer support
#
CONFIG_SPI_MUX=m

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=m
CONFIG_SPI_LOOPBACK_TEST=m
CONFIG_SPI_TLE62X0=m
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_DYNAMIC=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set
# CONFIG_NTP_PPS is not set

#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
# CONFIG_PPS_CLIENT_LDISC is not set
# CONFIG_PPS_CLIENT_GPIO is not set

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
CONFIG_PTP_1588_CLOCK_KVM=m
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
# CONFIG_PTP_1588_CLOCK_OCP is not set
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_PINCTRL_AMD is not set
CONFIG_PINCTRL_AXP209=y
# CONFIG_PINCTRL_CY8C95X0 is not set
CONFIG_PINCTRL_MCP23S08_I2C=m
CONFIG_PINCTRL_MCP23S08_SPI=m
CONFIG_PINCTRL_MCP23S08=m
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
# CONFIG_PINCTRL_OCELOT is not set
CONFIG_PINCTRL_RK805=y
CONFIG_PINCTRL_ROCKCHIP=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_PINCTRL_STMFX=m
# CONFIG_PINCTRL_SX150X is not set
CONFIG_PINCTRL_MESON=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_PINCTRL_MESON8_PMX=y
CONFIG_PINCTRL_MESON_AXG=y
CONFIG_PINCTRL_MESON_AXG_PMX=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_PINCTRL_MESON_A1=y
CONFIG_PINCTRL_MESON_S4=y

#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers

CONFIG_PINCTRL_SUNXI=y
CONFIG_PINCTRL_SUN4I_A10=y
CONFIG_PINCTRL_SUN5I=y
CONFIG_PINCTRL_SUN6I_A31=y
CONFIG_PINCTRL_SUN6I_A31_R=y
CONFIG_PINCTRL_SUN8I_A23=y
CONFIG_PINCTRL_SUN8I_A33=y
CONFIG_PINCTRL_SUN8I_A83T=y
CONFIG_PINCTRL_SUN8I_A83T_R=y
CONFIG_PINCTRL_SUN8I_A23_R=y
CONFIG_PINCTRL_SUN8I_H3=y
CONFIG_PINCTRL_SUN8I_H3_R=y
CONFIG_PINCTRL_SUN8I_V3S=y
CONFIG_PINCTRL_SUN9I_A80=y
CONFIG_PINCTRL_SUN9I_A80_R=y
CONFIG_PINCTRL_SUN20I_D1=y
CONFIG_PINCTRL_SUN50I_A64=y
CONFIG_PINCTRL_SUN50I_A64_R=y
CONFIG_PINCTRL_SUN50I_A100=y
CONFIG_PINCTRL_SUN50I_A100_R=y
CONFIG_PINCTRL_SUN50I_H5=y
CONFIG_PINCTRL_SUN50I_H6=y
CONFIG_PINCTRL_SUN50I_H6_R=y
CONFIG_PINCTRL_SUN50I_H616=y
CONFIG_PINCTRL_SUN50I_H616_R=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_MAX730X=m

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_FTGPIO010 is not set
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HISI is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_LOGICVC is not set
# CONFIG_GPIO_MB86S7X is not set
CONFIG_GPIO_PL061=y
CONFIG_GPIO_ROCKCHIP=y
# CONFIG_GPIO_SIFIVE is not set
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_XGENE=y
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
CONFIG_GPIO_ADNP=m
CONFIG_GPIO_GW_PLD=m
CONFIG_GPIO_MAX7300=m
CONFIG_GPIO_MAX732X=m
CONFIG_GPIO_PCA953X=m
# CONFIG_GPIO_PCA953X_IRQ is not set
CONFIG_GPIO_PCA9570=m
CONFIG_GPIO_PCF857X=m
CONFIG_GPIO_TPIC2810=m
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set
# end of PCI GPIO expanders

#
# SPI GPIO expanders
#
CONFIG_GPIO_74X164=m
CONFIG_GPIO_MAX3191X=m
CONFIG_GPIO_MAX7301=m
CONFIG_GPIO_MC33880=m
CONFIG_GPIO_PISOSR=m
CONFIG_GPIO_XRA1403=m
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
# end of USB GPIO expanders

#
# Virtual GPIO drivers
#
CONFIG_GPIO_AGGREGATOR=m
CONFIG_GPIO_MOCKUP=m
CONFIG_GPIO_VIRTIO=m
CONFIG_GPIO_SIM=m
# end of Virtual GPIO drivers

#
# Other GPIO expanders
#
# CONFIG_GPIO_CASCADE is not set
CONFIG_W1=m
CONFIG_W1_CON=y

#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_MATROX=m
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
CONFIG_W1_MASTER_DS1WM=m
CONFIG_W1_MASTER_GPIO=m
CONFIG_W1_MASTER_SGI=m
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
CONFIG_W1_SLAVE_DS2405=m
CONFIG_W1_SLAVE_DS2408=m
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
CONFIG_W1_SLAVE_DS2805=m
CONFIG_W1_SLAVE_DS2430=m
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
CONFIG_W1_SLAVE_DS2438=m
CONFIG_W1_SLAVE_DS250X=m
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
CONFIG_W1_SLAVE_DS28E17=m
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_BRCMSTB=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
CONFIG_POWER_RESET_LTC2952=y
CONFIG_POWER_RESET_REGULATOR=y
CONFIG_POWER_RESET_RESTART=y
CONFIG_POWER_RESET_VEXPRESS=y
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
CONFIG_NVMEM_REBOOT_MODE=y
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_PDA_POWER is not set
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_IP5XXX_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SAMSUNG_SDI is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_CHARGER_AXP20X is not set
# CONFIG_BATTERY_AXP20X is not set
CONFIG_AXP20X_POWER=y
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_BATTERY_MAX1721X is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
CONFIG_CHARGER_GPIO=m
CONFIG_CHARGER_MANAGER=m
CONFIG_CHARGER_LT3651=m
CONFIG_CHARGER_LTC4162L=m
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_MAX77976 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_BQ25980 is not set
# CONFIG_CHARGER_BQ256XX is not set
CONFIG_CHARGER_RK817=y
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_BATTERY_GOLDFISH is not set
# CONFIG_BATTERY_RT5033 is not set
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
# CONFIG_BATTERY_UG3105 is not set
CONFIG_HWMON=y
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM1177 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7310 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_AHT10 is not set
# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
# CONFIG_SENSORS_AS370 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
CONFIG_SENSORS_ARM_SCMI=m
CONFIG_SENSORS_ARM_SCPI=y
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_CORSAIR_CPRO is not set
# CONFIG_SENSORS_CORSAIR_PSU is not set
# CONFIG_SENSORS_DRIVETEMP is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_I5K_AMB is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_FTSTEUTATES is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_G762 is not set
CONFIG_SENSORS_GPIO_FAN=m
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_IIO_HWMON is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_POWR1220 is not set
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LTC2945 is not set
# CONFIG_SENSORS_LTC2947_I2C is not set
# CONFIG_SENSORS_LTC2947_SPI is not set
# CONFIG_SENSORS_LTC2990 is not set
# CONFIG_SENSORS_LTC2992 is not set
# CONFIG_SENSORS_LTC4151 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4222 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LTC4260 is not set
# CONFIG_SENSORS_LTC4261 is not set
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX127 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX197 is not set
# CONFIG_SENSORS_MAX31722 is not set
# CONFIG_SENSORS_MAX31730 is not set
# CONFIG_SENSORS_MAX31760 is not set
# CONFIG_SENSORS_MAX6620 is not set
# CONFIG_SENSORS_MAX6621 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MAX6697 is not set
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_TPS23861 is not set
# CONFIG_SENSORS_MR75203 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LM95234 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_NCT6683 is not set
# CONFIG_SENSORS_NCT6775 is not set
# CONFIG_SENSORS_NCT6775_I2C is not set
# CONFIG_SENSORS_NCT7802 is not set
# CONFIG_SENSORS_NCT7904 is not set
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
# CONFIG_SENSORS_NZXT_SMART2 is not set
# CONFIG_SENSORS_OCC_P8_I2C is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_PMBUS is not set
CONFIG_SENSORS_PWM_FAN=m
# CONFIG_SENSORS_SBTSI is not set
# CONFIG_SENSORS_SBRMI is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHT4x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC2305 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA238 is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_TMP464 is not set
# CONFIG_SENSORS_TMP513 is not set
# CONFIG_SENSORS_VEXPRESS is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set

#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
# CONFIG_THERMAL_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
# CONFIG_THERMAL_EMULATION is not set
CONFIG_THERMAL_MMIO=y
CONFIG_SUN8I_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_AMLOGIC_THERMAL=y
CONFIG_GENERIC_ADC_THERMAL=m
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set
# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=m
# CONFIG_GPIO_WATCHDOG is not set
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
CONFIG_ARM_SP805_WATCHDOG=m
CONFIG_ARM_SBSA_WATCHDOG=y
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=m
CONFIG_SUNXI_WATCHDOG=m
# CONFIG_MAX63XX_WATCHDOG is not set
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_WATCHDOG=m
# CONFIG_ARM_SMC_WATCHDOG is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_HP_WATCHDOG is not set
# CONFIG_MEN_A21_WDT is not set

#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
CONFIG_BCMA_HOST_PCI=y
CONFIG_BCMA_HOST_SOC=y
CONFIG_BCMA_DRIVER_PCI=y
CONFIG_BCMA_SFLASH=y
CONFIG_BCMA_DRIVER_GMAC_CMN=y
CONFIG_BCMA_DRIVER_GPIO=y
CONFIG_BCMA_DEBUG=y

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
CONFIG_MFD_AC100=y
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
# CONFIG_MFD_MADERA is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77714 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6370 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_MFD_OCELOT is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_NTXEC is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_UCB1400_CORE is not set
# CONFIG_MFD_SY7636A is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT4831 is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RT5120 is not set
# CONFIG_MFD_RC5T583 is not set
CONFIG_MFD_RK808=y
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
CONFIG_MFD_SIMPLE_MFD_I2C=m
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SUN6I_PRCM=y
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TQMX86 is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
# CONFIG_MFD_ROHM_BD71828 is not set
# CONFIG_MFD_ROHM_BD957XMUF is not set
# CONFIG_MFD_STPMIC1 is not set
CONFIG_MFD_STMFX=m
# CONFIG_MFD_ATC260X_I2C is not set
# CONFIG_MFD_KHADAS_MCU is not set
# CONFIG_MFD_QCOM_PM8008 is not set
# CONFIG_MFD_VEXPRESS_SYSREG is not set
# CONFIG_RAVE_SP_CORE is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# CONFIG_MFD_RSMU_I2C is not set
# CONFIG_MFD_RSMU_SPI is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_88PG86X is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_AD5398 is not set
CONFIG_REGULATOR_ARM_SCMI=y
CONFIG_REGULATOR_AXP20X=y
# CONFIG_REGULATOR_DA9121 is not set
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_FAN53880=y
CONFIG_REGULATOR_GPIO=y
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_LP8755 is not set
# CONFIG_REGULATOR_LTC3589 is not set
# CONFIG_REGULATOR_LTC3676 is not set
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8893 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_MAX8973 is not set
# CONFIG_REGULATOR_MAX20086 is not set
# CONFIG_REGULATOR_MAX77826 is not set
# CONFIG_REGULATOR_MCP16502 is not set
# CONFIG_REGULATOR_MP5416 is not set
# CONFIG_REGULATOR_MP8859 is not set
# CONFIG_REGULATOR_MP886X is not set
# CONFIG_REGULATOR_MPQ7920 is not set
# CONFIG_REGULATOR_MT6311 is not set
# CONFIG_REGULATOR_MT6315 is not set
# CONFIG_REGULATOR_PCA9450 is not set
# CONFIG_REGULATOR_PF8X00 is not set
# CONFIG_REGULATOR_PFUZE100 is not set
# CONFIG_REGULATOR_PV88060 is not set
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
CONFIG_REGULATOR_PWM=y
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
CONFIG_REGULATOR_RK808=y
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RT5190A is not set
# CONFIG_REGULATOR_RT5759 is not set
# CONFIG_REGULATOR_RT6160 is not set
# CONFIG_REGULATOR_RT6245 is not set
# CONFIG_REGULATOR_RTQ2134 is not set
# CONFIG_REGULATOR_RTMV20 is not set
# CONFIG_REGULATOR_RTQ6752 is not set
# CONFIG_REGULATOR_SLG51000 is not set
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
# CONFIG_REGULATOR_SY8827N is not set
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS6286X is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_TPS6524X is not set
CONFIG_REGULATOR_VCTRL=y
# CONFIG_REGULATOR_VEXPRESS is not set
# CONFIG_REGULATOR_QCOM_LABIBB is not set
CONFIG_RC_CORE=y
# CONFIG_BPF_LIRC_MODE2 is not set
CONFIG_LIRC=y
CONFIG_RC_MAP=y
CONFIG_RC_DECODERS=y
CONFIG_IR_IMON_DECODER=m
CONFIG_IR_JVC_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
CONFIG_IR_RCMM_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_XMP_DECODER=m
CONFIG_RC_DEVICES=y
# CONFIG_IR_ENE is not set
# CONFIG_IR_FINTEK is not set
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_GPIO_TX=m
CONFIG_IR_HIX5HD2=m
CONFIG_IR_IGORPLUGUSB=m
CONFIG_IR_IGUANA=m
CONFIG_IR_IMON=m
CONFIG_IR_IMON_RAW=m
# CONFIG_IR_ITE_CIR is not set
CONFIG_IR_MCEUSB=m
CONFIG_IR_MESON=m
CONFIG_IR_MESON_TX=m
# CONFIG_IR_NUVOTON is not set
CONFIG_IR_PWM_TX=m
CONFIG_IR_REDRAT3=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m
CONFIG_IR_SUNXI=m
CONFIG_IR_TOY=m
CONFIG_IR_TTUSBIR=m
CONFIG_RC_ATI_REMOTE=m
CONFIG_RC_LOOPBACK=m
CONFIG_RC_XBOX_DVD=m
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y

#
# CEC support
#
CONFIG_MEDIA_CEC_RC=y
CONFIG_MEDIA_CEC_SUPPORT=y
CONFIG_CEC_CH7322=m
CONFIG_CEC_MESON_AO=y
CONFIG_CEC_MESON_G12A_AO=y
CONFIG_USB_PULSE8_CEC=m
CONFIG_USB_RAINSHADOW_CEC=m
# end of CEC support

CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_SUPPORT_FILTER=y
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_SDR_SUPPORT is not set
CONFIG_MEDIA_PLATFORM_SUPPORT=y
# CONFIG_MEDIA_TEST_SUPPORT is not set
# end of Media device types

CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CONTROLLER=y

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_ADV_DEBUG=y
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_H264=m
CONFIG_V4L2_VP9=m
CONFIG_V4L2_MEM2MEM_DEV=m
# CONFIG_V4L2_FLASH_LED_CLASS is not set
CONFIG_V4L2_FWNODE=y
CONFIG_V4L2_ASYNC=y
# end of Video4Linux options

#
# Media controller options
#
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
# end of Media controller options

#
# Media drivers
#

#
# Drivers filtered as selected at 'Filter media drivers'
#

#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_GSPCA=m
CONFIG_USB_GSPCA_BENQ=m
CONFIG_USB_GSPCA_CONEX=m
CONFIG_USB_GSPCA_CPIA1=m
CONFIG_USB_GSPCA_DTCS033=m
CONFIG_USB_GSPCA_ETOMS=m
CONFIG_USB_GSPCA_FINEPIX=m
CONFIG_USB_GSPCA_JEILINJ=m
CONFIG_USB_GSPCA_JL2005BCD=m
CONFIG_USB_GSPCA_KINECT=m
CONFIG_USB_GSPCA_KONICA=m
CONFIG_USB_GSPCA_MARS=m
CONFIG_USB_GSPCA_MR97310A=m
CONFIG_USB_GSPCA_NW80X=m
CONFIG_USB_GSPCA_OV519=m
CONFIG_USB_GSPCA_OV534=m
CONFIG_USB_GSPCA_OV534_9=m
CONFIG_USB_GSPCA_PAC207=m
CONFIG_USB_GSPCA_PAC7302=m
CONFIG_USB_GSPCA_PAC7311=m
CONFIG_USB_GSPCA_SE401=m
CONFIG_USB_GSPCA_SN9C2028=m
CONFIG_USB_GSPCA_SN9C20X=m
CONFIG_USB_GSPCA_SONIXB=m
CONFIG_USB_GSPCA_SONIXJ=m
CONFIG_USB_GSPCA_SPCA1528=m
CONFIG_USB_GSPCA_SPCA500=m
CONFIG_USB_GSPCA_SPCA501=m
CONFIG_USB_GSPCA_SPCA505=m
CONFIG_USB_GSPCA_SPCA506=m
CONFIG_USB_GSPCA_SPCA508=m
CONFIG_USB_GSPCA_SPCA561=m
CONFIG_USB_GSPCA_SQ905=m
CONFIG_USB_GSPCA_SQ905C=m
CONFIG_USB_GSPCA_SQ930X=m
CONFIG_USB_GSPCA_STK014=m
CONFIG_USB_GSPCA_STK1135=m
CONFIG_USB_GSPCA_STV0680=m
CONFIG_USB_GSPCA_SUNPLUS=m
CONFIG_USB_GSPCA_T613=m
CONFIG_USB_GSPCA_TOPRO=m
CONFIG_USB_GSPCA_TOUPTEK=m
CONFIG_USB_GSPCA_TV8532=m
CONFIG_USB_GSPCA_VC032X=m
CONFIG_USB_GSPCA_VICAM=m
CONFIG_USB_GSPCA_XIRLINK_CIT=m
CONFIG_USB_GSPCA_ZC3XX=m
CONFIG_USB_GL860=m
CONFIG_USB_M5602=m
CONFIG_USB_STV06XX=m
CONFIG_USB_PWC=m
# CONFIG_USB_PWC_DEBUG is not set
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_USB_S2255=m
CONFIG_VIDEO_USBTV=m
CONFIG_USB_VIDEO_CLASS=m
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y

#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=m
CONFIG_VIDEO_EM28XX_V4L2=m
CONFIG_VIDEO_EM28XX_ALSA=m
CONFIG_VIDEO_EM28XX_RC=m
# CONFIG_MEDIA_PCI_SUPPORT is not set
CONFIG_MEDIA_PLATFORM_DRIVERS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
CONFIG_VIDEO_MUX=m

#
# Allegro DVT media platform drivers
#

#
# Amlogic media platform drivers
#
CONFIG_VIDEO_MESON_GE2D=m

#
# Amphion drivers
#

#
# Aspeed media platform drivers
#
# CONFIG_VIDEO_ASPEED is not set

#
# Atmel media platform drivers
#

#
# Cadence media platform drivers
#
# CONFIG_VIDEO_CADENCE_CSI2RX is not set
# CONFIG_VIDEO_CADENCE_CSI2TX is not set

#
# Chips&Media media platform drivers
#

#
# Intel media platform drivers
#

#
# Marvell media platform drivers
#
# CONFIG_VIDEO_CAFE_CCIC is not set

#
# Mediatek media platform drivers
#

#
# NVidia media platform drivers
#

#
# NXP media platform drivers
#

#
# Qualcomm media platform drivers
#

#
# Renesas media platform drivers
#

#
# Rockchip media platform drivers
#
CONFIG_VIDEO_ROCKCHIP_RGA=m
CONFIG_VIDEO_ROCKCHIP_ISP1=m

#
# Samsung media platform drivers
#

#
# STMicroelectronics media platform drivers
#

#
# Sunxi media platform drivers
#
CONFIG_VIDEO_SUN4I_CSI=m
CONFIG_VIDEO_SUN6I_CSI=m
CONFIG_VIDEO_SUN6I_MIPI_CSI2=m
CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m
CONFIG_VIDEO_SUN8I_DEINTERLACE=m
CONFIG_VIDEO_SUN8I_ROTATE=m

#
# Texas Instruments drivers
#

#
# Verisilicon media platform drivers
#
# CONFIG_VIDEO_HANTRO is not set

#
# VIA media platform drivers
#

#
# Xilinx media platform drivers
#
# CONFIG_VIDEO_XILINX is not set
CONFIG_VIDEO_TVEEPROM=m
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_VIDEOBUF2_DMA_SG=m
# end of Media drivers

#
# Media ancillary drivers
#

#
# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
#
CONFIG_VIDEO_IR_I2C=m
CONFIG_VIDEO_CAMERA_SENSOR=y
CONFIG_VIDEO_APTINA_PLL=m
CONFIG_VIDEO_CCS_PLL=m
CONFIG_VIDEO_AR0521=m
CONFIG_VIDEO_HI556=m
CONFIG_VIDEO_HI846=m
CONFIG_VIDEO_HI847=m
CONFIG_VIDEO_IMX208=m
CONFIG_VIDEO_IMX214=m
CONFIG_VIDEO_IMX219=m
CONFIG_VIDEO_IMX258=m
CONFIG_VIDEO_IMX274=m
CONFIG_VIDEO_IMX290=m
CONFIG_VIDEO_IMX319=m
CONFIG_VIDEO_IMX334=m
CONFIG_VIDEO_IMX335=m
CONFIG_VIDEO_IMX355=m
CONFIG_VIDEO_IMX412=m
CONFIG_VIDEO_MAX9271_LIB=m
CONFIG_VIDEO_MT9M001=m
CONFIG_VIDEO_MT9M032=m
CONFIG_VIDEO_MT9M111=m
CONFIG_VIDEO_MT9P031=m
CONFIG_VIDEO_MT9T001=m
CONFIG_VIDEO_MT9T112=m
CONFIG_VIDEO_MT9V011=m
CONFIG_VIDEO_MT9V032=m
CONFIG_VIDEO_MT9V111=m
CONFIG_VIDEO_NOON010PC30=m
CONFIG_VIDEO_OG01A1B=m
CONFIG_VIDEO_OV02A10=m
CONFIG_VIDEO_OV08D10=m
CONFIG_VIDEO_OV13858=m
CONFIG_VIDEO_OV13B10=m
CONFIG_VIDEO_OV2640=m
CONFIG_VIDEO_OV2659=m
CONFIG_VIDEO_OV2680=m
CONFIG_VIDEO_OV2685=m
CONFIG_VIDEO_OV2740=m
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_OV5647=m
CONFIG_VIDEO_OV5648=m
CONFIG_VIDEO_OV5670=m
CONFIG_VIDEO_OV5675=m
CONFIG_VIDEO_OV5693=m
CONFIG_VIDEO_OV5695=m
CONFIG_VIDEO_OV6650=m
CONFIG_VIDEO_OV7251=m
CONFIG_VIDEO_OV7640=m
CONFIG_VIDEO_OV7670=m
CONFIG_VIDEO_OV772X=m
CONFIG_VIDEO_OV7740=m
CONFIG_VIDEO_OV8856=m
CONFIG_VIDEO_OV8865=m
CONFIG_VIDEO_OV9282=m
CONFIG_VIDEO_OV9640=m
CONFIG_VIDEO_OV9650=m
CONFIG_VIDEO_OV9734=m
CONFIG_VIDEO_RDACM20=m
CONFIG_VIDEO_RDACM21=m
CONFIG_VIDEO_RJ54N1=m
CONFIG_VIDEO_S5C73M3=m
CONFIG_VIDEO_S5K4ECGX=m
CONFIG_VIDEO_S5K5BAF=m
CONFIG_VIDEO_S5K6A3=m
CONFIG_VIDEO_S5K6AA=m
CONFIG_VIDEO_SR030PC30=m
CONFIG_VIDEO_VS6624=m
CONFIG_VIDEO_CCS=m
CONFIG_VIDEO_ET8EK8=m
CONFIG_VIDEO_M5MOLS=m

#
# Lens drivers
#
CONFIG_VIDEO_AD5820=m
CONFIG_VIDEO_AK7375=m
CONFIG_VIDEO_DW9714=m
CONFIG_VIDEO_DW9768=m
CONFIG_VIDEO_DW9807_VCM=m
# end of Lens drivers

#
# Flash devices
#
CONFIG_VIDEO_ADP1653=m
CONFIG_VIDEO_LM3560=m
CONFIG_VIDEO_LM3646=m
# end of Flash devices

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_CS3308=m
CONFIG_VIDEO_CS5345=m
CONFIG_VIDEO_CS53L32A=m
CONFIG_VIDEO_MSP3400=m
CONFIG_VIDEO_SONY_BTF_MPX=m
CONFIG_VIDEO_TDA1997X=m
CONFIG_VIDEO_TDA7432=m
CONFIG_VIDEO_TDA9840=m
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
CONFIG_VIDEO_TLV320AIC23B=m
CONFIG_VIDEO_TVAUDIO=m
CONFIG_VIDEO_UDA1342=m
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_WM8739=m
CONFIG_VIDEO_WM8775=m
# end of Audio decoders, processors and mixers

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders

#
# Video decoders
#
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_ADV7183=m
CONFIG_VIDEO_ADV748X=m
CONFIG_VIDEO_ADV7604=m
CONFIG_VIDEO_ADV7604_CEC=y
CONFIG_VIDEO_ADV7842=m
CONFIG_VIDEO_ADV7842_CEC=y
CONFIG_VIDEO_BT819=m
CONFIG_VIDEO_BT856=m
CONFIG_VIDEO_BT866=m
CONFIG_VIDEO_ISL7998X=m
CONFIG_VIDEO_KS0127=m
CONFIG_VIDEO_MAX9286=m
CONFIG_VIDEO_ML86V7667=m
CONFIG_VIDEO_SAA7110=m
CONFIG_VIDEO_SAA711X=m
CONFIG_VIDEO_TC358743=m
CONFIG_VIDEO_TC358743_CEC=y
CONFIG_VIDEO_TVP514X=m
CONFIG_VIDEO_TVP5150=m
CONFIG_VIDEO_TVP7002=m
CONFIG_VIDEO_TW2804=m
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=m
CONFIG_VIDEO_TW9910=m
CONFIG_VIDEO_VPX3220=m

#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=m
CONFIG_VIDEO_CX25840=m
# end of Video decoders

#
# Video encoders
#
CONFIG_VIDEO_AD9389B=m
CONFIG_VIDEO_ADV7170=m
CONFIG_VIDEO_ADV7175=m
CONFIG_VIDEO_ADV7343=m
CONFIG_VIDEO_ADV7393=m
CONFIG_VIDEO_ADV7511=m
CONFIG_VIDEO_ADV7511_CEC=y
CONFIG_VIDEO_AK881X=m
CONFIG_VIDEO_SAA7127=m
CONFIG_VIDEO_SAA7185=m
CONFIG_VIDEO_THS8200=m
# end of Video encoders

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
CONFIG_VIDEO_UPD64083=m
# end of Video improvement chips

#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips

#
# SDR tuner chips
#
# end of SDR tuner chips

#
# Miscellaneous helper chips
#
CONFIG_VIDEO_I2C=m
CONFIG_VIDEO_M52790=m
CONFIG_VIDEO_ST_MIPID02=m
CONFIG_VIDEO_THS7303=m
# end of Miscellaneous helper chips

#
# Media SPI Adapters
#
CONFIG_VIDEO_GS1662=m
# end of Media SPI Adapters
# end of Media ancillary drivers

#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
CONFIG_DRM=y
CONFIG_DRM_MIPI_DBI=m
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_DEBUG_MM is not set
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=300
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
CONFIG_DRM_DP_AUX_BUS=m
CONFIG_DRM_DISPLAY_HELPER=y
CONFIG_DRM_DISPLAY_DP_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_TTM=m
CONFIG_DRM_TTM_HELPER=m
CONFIG_DRM_GEM_DMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=m
CONFIG_DRM_SCHED=m

#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips

#
# ARM devices
#
CONFIG_DRM_HDLCD=m
CONFIG_DRM_HDLCD_SHOW_UNDERRUN=y
CONFIG_DRM_MALI_DISPLAY=m
CONFIG_DRM_KOMEDA=m
# end of ARM devices

# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
CONFIG_DRM_ROCKCHIP=m
CONFIG_ROCKCHIP_VOP=y
CONFIG_ROCKCHIP_VOP2=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_ROCKCHIP_LVDS=y
CONFIG_ROCKCHIP_RGB=y
CONFIG_ROCKCHIP_RK3066_HDMI=y
# CONFIG_DRM_VMWGFX is not set
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_USE_LVDS is not set
# CONFIG_DRM_RCAR_USE_MIPI_DSI is not set
CONFIG_DRM_SUN4I=y
CONFIG_DRM_SUN6I_DSI=y
CONFIG_DRM_SUN8I_DW_HDMI=y
CONFIG_DRM_SUN8I_MIXER=y
CONFIG_DRM_SUN8I_TCON_TOP=y
CONFIG_DRM_QXL=m
CONFIG_DRM_VIRTIO_GPU=m
CONFIG_DRM_PANEL=y

#
# Display Panels
#
CONFIG_DRM_PANEL_ABT_Y030XX067A=m
CONFIG_DRM_PANEL_ARM_VERSATILE=m
CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
CONFIG_DRM_PANEL_DSI_CM=m
CONFIG_DRM_PANEL_LVDS=m
CONFIG_DRM_PANEL_SIMPLE=m
CONFIG_DRM_PANEL_EDP=m
CONFIG_DRM_PANEL_EBBG_FT8719=m
CONFIG_DRM_PANEL_ELIDA_KD35T133=m
CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
CONFIG_DRM_PANEL_ILITEK_IL9322=m
CONFIG_DRM_PANEL_ILITEK_ILI9341=m
CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
CONFIG_DRM_PANEL_JDI_LT070ME05000=m
CONFIG_DRM_PANEL_JDI_R63452=m
CONFIG_DRM_PANEL_KHADAS_TS050=m
CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
CONFIG_DRM_PANEL_LG_LB035Q02=m
CONFIG_DRM_PANEL_LG_LG4573=m
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
CONFIG_DRM_PANEL_NOVATEK_NT35510=m
CONFIG_DRM_PANEL_NOVATEK_NT35560=m
CONFIG_DRM_PANEL_NOVATEK_NT35950=m
CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
CONFIG_DRM_PANEL_NOVATEK_NT39016=m
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
CONFIG_DRM_PANEL_RONBO_RB070D30=m
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
CONFIG_DRM_PANEL_SITRONIX_ST7789V=m
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
CONFIG_DRM_PANEL_TDO_TL070WSH30=m
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
CONFIG_DRM_PANEL_TPO_TPG110=m
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
CONFIG_DRM_PANEL_VISIONOX_RM69299=m
CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CHIPONE_ICN6211 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
CONFIG_DRM_DISPLAY_CONNECTOR=y
# CONFIG_DRM_ITE_IT6505 is not set
# CONFIG_DRM_LONTIUM_LT8912B is not set
# CONFIG_DRM_LONTIUM_LT9211 is not set
# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LONTIUM_LT9611UXC is not set
# CONFIG_DRM_ITE_IT66121 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
CONFIG_DRM_SIMPLE_BRIDGE=m
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_DLPC3433 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI83 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
CONFIG_DRM_ANALOGIX_DP=m
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=y
CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
CONFIG_DRM_DW_HDMI_CEC=m
CONFIG_DRM_DW_MIPI_DSI=m
# end of Display Interface Bridges

# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
# CONFIG_DRM_LOGICVC is not set
CONFIG_DRM_MESON=y
CONFIG_DRM_MESON_DW_HDMI=y
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_BOCHS is not set
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_GM12U320 is not set
# CONFIG_DRM_PANEL_MIPI_DBI is not set
# CONFIG_DRM_SIMPLEDRM is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9163 is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_DRM_PL111 is not set
CONFIG_DRM_LIMA=m
CONFIG_DRM_PANFROST=m
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_GUD is not set
CONFIG_DRM_SSD130X=m
CONFIG_DRM_SSD130X_I2C=m
CONFIG_DRM_SSD130X_SPI=m
# CONFIG_DRM_LEGACY is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_DRM_NOMODESET=y

#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_BACKLIGHT=m
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
CONFIG_FB_ARMCLCD=y
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_UVESA is not set
CONFIG_FB_EFI=y
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
CONFIG_FB_SIMPLE=y
# CONFIG_FB_SSD1307 is not set
# CONFIG_FB_SM712 is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=m
CONFIG_LCD_L4F00242T03=m
CONFIG_LCD_LMS283GF05=m
CONFIG_LCD_LTV350QV=m
CONFIG_LCD_ILI922X=m
CONFIG_LCD_ILI9320=m
CONFIG_LCD_TDO24M=m
CONFIG_LCD_VGG2432A4=m
CONFIG_LCD_PLATFORM=m
CONFIG_LCD_AMS369FG06=m
CONFIG_LCD_LMS501KF03=m
CONFIG_LCD_HX8357=m
CONFIG_LCD_OTM3225A=m
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_KTD253=m
CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_QCOM_WLED=m
CONFIG_BACKLIGHT_ADP8860=m
CONFIG_BACKLIGHT_ADP8870=m
CONFIG_BACKLIGHT_LM3630A=m
CONFIG_BACKLIGHT_LM3639=m
CONFIG_BACKLIGHT_LP855X=m
CONFIG_BACKLIGHT_GPIO=y
CONFIG_BACKLIGHT_LV5207LP=m
CONFIG_BACKLIGHT_BD6107=m
CONFIG_BACKLIGHT_ARCXCNN=m
CONFIG_BACKLIGHT_LED=y
# end of Backlight & LCD device support

CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
# end of Console display driver support

CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
# end of Graphics support

CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=m
CONFIG_SND_RAWMIDI=m
CONFIG_SND_COMPRESS_OFFLOAD=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_OSSEMUL is not set
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_VERBOSE_PRINTK is not set
CONFIG_SND_CTL_FAST_LOOKUP=y
# CONFIG_SND_DEBUG is not set
# CONFIG_SND_CTL_INPUT_VALIDATION is not set
CONFIG_SND_VMASTER=y
# CONFIG_SND_SEQUENCER is not set
CONFIG_SND_MPU401_UART=m
CONFIG_SND_AC97_CODEC=y
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
CONFIG_SND_MTPAV=m
CONFIG_SND_SERIAL_U16550=m
CONFIG_SND_SERIAL_GENERIC=m
CONFIG_SND_MPU401=m
# CONFIG_SND_AC97_POWER_SAVE is not set
CONFIG_SND_PCI=y
# CONFIG_SND_AD1889 is not set
# CONFIG_SND_ALS300 is not set
# CONFIG_SND_ALI5451 is not set
# CONFIG_SND_ATIIXP is not set
# CONFIG_SND_ATIIXP_MODEM is not set
# CONFIG_SND_AU8810 is not set
# CONFIG_SND_AU8820 is not set
# CONFIG_SND_AU8830 is not set
# CONFIG_SND_AW2 is not set
# CONFIG_SND_AZT3328 is not set
# CONFIG_SND_BT87X is not set
# CONFIG_SND_CA0106 is not set
# CONFIG_SND_CMIPCI is not set
# CONFIG_SND_OXYGEN is not set
# CONFIG_SND_CS4281 is not set
# CONFIG_SND_CS46XX is not set
# CONFIG_SND_CTXFI is not set
# CONFIG_SND_DARLA20 is not set
# CONFIG_SND_GINA20 is not set
# CONFIG_SND_LAYLA20 is not set
# CONFIG_SND_DARLA24 is not set
# CONFIG_SND_GINA24 is not set
# CONFIG_SND_LAYLA24 is not set
# CONFIG_SND_MONA is not set
# CONFIG_SND_MIA is not set
# CONFIG_SND_ECHO3G is not set
# CONFIG_SND_INDIGO is not set
# CONFIG_SND_INDIGOIO is not set
# CONFIG_SND_INDIGODJ is not set
# CONFIG_SND_INDIGOIOX is not set
# CONFIG_SND_INDIGODJX is not set
# CONFIG_SND_EMU10K1 is not set
# CONFIG_SND_EMU10K1X is not set
# CONFIG_SND_ENS1370 is not set
# CONFIG_SND_ENS1371 is not set
# CONFIG_SND_ES1938 is not set
# CONFIG_SND_ES1968 is not set
# CONFIG_SND_FM801 is not set
# CONFIG_SND_HDSP is not set
# CONFIG_SND_HDSPM is not set
# CONFIG_SND_ICE1712 is not set
# CONFIG_SND_ICE1724 is not set
# CONFIG_SND_INTEL8X0 is not set
# CONFIG_SND_INTEL8X0M is not set
# CONFIG_SND_KORG1212 is not set
# CONFIG_SND_LOLA is not set
# CONFIG_SND_LX6464ES is not set
# CONFIG_SND_MAESTRO3 is not set
# CONFIG_SND_MIXART is not set
# CONFIG_SND_NM256 is not set
# CONFIG_SND_PCXHR is not set
# CONFIG_SND_RIPTIDE is not set
# CONFIG_SND_RME32 is not set
# CONFIG_SND_RME96 is not set
# CONFIG_SND_RME9652 is not set
# CONFIG_SND_SE6X is not set
# CONFIG_SND_SONICVIBES is not set
# CONFIG_SND_TRIDENT is not set
# CONFIG_SND_VIA82XX is not set
# CONFIG_SND_VIA82XX_MODEM is not set
# CONFIG_SND_VIRTUOSO is not set
# CONFIG_SND_VX222 is not set
# CONFIG_SND_YMFPCI is not set

#
# HD-Audio
#
CONFIG_SND_HDA=y
# CONFIG_SND_HDA_INTEL is not set
# CONFIG_SND_HDA_HWDEP is not set
# CONFIG_SND_HDA_RECONFIG is not set
# CONFIG_SND_HDA_INPUT_BEEP is not set
# CONFIG_SND_HDA_PATCH_LOADER is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
# CONFIG_SND_HDA_CODEC_REALTEK is not set
# CONFIG_SND_HDA_CODEC_ANALOG is not set
# CONFIG_SND_HDA_CODEC_SIGMATEL is not set
# CONFIG_SND_HDA_CODEC_VIA is not set
CONFIG_SND_HDA_CODEC_HDMI=y
# CONFIG_SND_HDA_CODEC_CIRRUS is not set
# CONFIG_SND_HDA_CODEC_CS8409 is not set
# CONFIG_SND_HDA_CODEC_CONEXANT is not set
# CONFIG_SND_HDA_CODEC_CA0110 is not set
# CONFIG_SND_HDA_CODEC_CA0132 is not set
# CONFIG_SND_HDA_CODEC_CMEDIA is not set
# CONFIG_SND_HDA_CODEC_SI3054 is not set
# CONFIG_SND_HDA_GENERIC is not set
CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
# end of HD-Audio

CONFIG_SND_HDA_CORE=y
CONFIG_SND_HDA_EXT_CORE=y
CONFIG_SND_HDA_PREALLOC_SIZE=2048
# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
CONFIG_SND_BCD2000=m
CONFIG_SND_USB_LINE6=m
CONFIG_SND_USB_POD=m
CONFIG_SND_USB_PODHD=m
CONFIG_SND_USB_TONEPORT=m
CONFIG_SND_USB_VARIAX=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
CONFIG_SND_SOC_COMPRESS=y
# CONFIG_SND_SOC_ADI is not set
# CONFIG_SND_SOC_AMD_ACP is not set
# CONFIG_SND_AMD_ACP_CONFIG is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
CONFIG_SND_DESIGNWARE_I2S=m
CONFIG_SND_DESIGNWARE_PCM=y

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
# CONFIG_SND_SOC_FSL_SAI is not set
# CONFIG_SND_SOC_FSL_AUDMIX is not set
# CONFIG_SND_SOC_FSL_SSI is not set
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
# CONFIG_SND_SOC_FSL_MICFIL is not set
# CONFIG_SND_SOC_FSL_XCVR is not set
# CONFIG_SND_SOC_FSL_RPMSG is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs

# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set

#
# ASoC support for Amlogic platforms
#
CONFIG_SND_MESON_AIU=m
CONFIG_SND_MESON_AXG_FIFO=m
CONFIG_SND_MESON_AXG_FRDDR=m
CONFIG_SND_MESON_AXG_TODDR=m
CONFIG_SND_MESON_AXG_TDM_FORMATTER=m
CONFIG_SND_MESON_AXG_TDM_INTERFACE=m
CONFIG_SND_MESON_AXG_TDMIN=m
CONFIG_SND_MESON_AXG_TDMOUT=m
CONFIG_SND_MESON_AXG_SOUND_CARD=m
CONFIG_SND_MESON_AXG_SPDIFOUT=m
CONFIG_SND_MESON_AXG_SPDIFIN=m
CONFIG_SND_MESON_AXG_PDM=m
CONFIG_SND_MESON_CARD_UTILS=m
CONFIG_SND_MESON_CODEC_GLUE=m
CONFIG_SND_MESON_GX_SOUND_CARD=m
CONFIG_SND_MESON_G12A_TOACODEC=m
CONFIG_SND_MESON_G12A_TOHDMITX=m
CONFIG_SND_SOC_MESON_T9015=m
# end of ASoC support for Amlogic platforms

CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_ROCKCHIP_I2S=m
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
CONFIG_SND_SOC_ROCKCHIP_PDM=m
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
CONFIG_SND_SOC_ROCKCHIP_RT5645=m
CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m
CONFIG_SND_SOC_RK3399_GRU_SOUND=m
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set

#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support

#
# Allwinner SoC Audio support
#
CONFIG_SND_SUN4I_CODEC=m
CONFIG_SND_SUN8I_CODEC=m
CONFIG_SND_SUN8I_CODEC_ANALOG=m
CONFIG_SND_SUN50I_CODEC_ANALOG=m
CONFIG_SND_SUN4I_I2S=m
CONFIG_SND_SUN4I_SPDIF=m
CONFIG_SND_SUN50I_DMIC=m
CONFIG_SND_SUN8I_ADDA_PR_REGMAP=m
# end of Allwinner SoC Audio support

# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# CONFIG_SND_SOC_XTFPGA_I2S is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
CONFIG_SND_SOC_WM_ADSP=y
CONFIG_SND_SOC_AC97_CODEC=y
CONFIG_SND_SOC_ADAU_UTILS=m
CONFIG_SND_SOC_ADAU1372=m
CONFIG_SND_SOC_ADAU1372_I2C=m
CONFIG_SND_SOC_ADAU1372_SPI=m
CONFIG_SND_SOC_ADAU1701=m
CONFIG_SND_SOC_ADAU17X1=m
CONFIG_SND_SOC_ADAU1761=m
CONFIG_SND_SOC_ADAU1761_I2C=m
CONFIG_SND_SOC_ADAU1761_SPI=m
CONFIG_SND_SOC_ADAU7002=m
CONFIG_SND_SOC_ADAU7118=m
CONFIG_SND_SOC_ADAU7118_HW=m
CONFIG_SND_SOC_ADAU7118_I2C=m
CONFIG_SND_SOC_AK4104=y
CONFIG_SND_SOC_AK4118=y
CONFIG_SND_SOC_AK4375=y
CONFIG_SND_SOC_AK4458=y
CONFIG_SND_SOC_AK4554=y
CONFIG_SND_SOC_AK4613=y
CONFIG_SND_SOC_AK4642=y
CONFIG_SND_SOC_AK5386=y
CONFIG_SND_SOC_AK5558=y
CONFIG_SND_SOC_ALC5623=y
CONFIG_SND_SOC_AW8738=m
CONFIG_SND_SOC_BD28623=m
CONFIG_SND_SOC_BT_SCO=m
CONFIG_SND_SOC_CS35L32=y
CONFIG_SND_SOC_CS35L33=y
CONFIG_SND_SOC_CS35L34=y
CONFIG_SND_SOC_CS35L35=y
CONFIG_SND_SOC_CS35L36=y
CONFIG_SND_SOC_CS35L41_LIB=y
CONFIG_SND_SOC_CS35L41=y
CONFIG_SND_SOC_CS35L41_SPI=y
CONFIG_SND_SOC_CS35L41_I2C=y
CONFIG_SND_SOC_CS35L45_TABLES=y
CONFIG_SND_SOC_CS35L45=y
CONFIG_SND_SOC_CS35L45_SPI=y
CONFIG_SND_SOC_CS35L45_I2C=y
CONFIG_SND_SOC_CS42L42_CORE=y
CONFIG_SND_SOC_CS42L42=y
CONFIG_SND_SOC_CS42L51=y
CONFIG_SND_SOC_CS42L51_I2C=y
CONFIG_SND_SOC_CS42L52=y
CONFIG_SND_SOC_CS42L56=y
CONFIG_SND_SOC_CS42L73=y
CONFIG_SND_SOC_CS42L83=y
CONFIG_SND_SOC_CS4234=y
CONFIG_SND_SOC_CS4265=y
CONFIG_SND_SOC_CS4270=y
CONFIG_SND_SOC_CS4271=y
CONFIG_SND_SOC_CS4271_I2C=y
CONFIG_SND_SOC_CS4271_SPI=y
CONFIG_SND_SOC_CS42XX8=y
CONFIG_SND_SOC_CS42XX8_I2C=y
CONFIG_SND_SOC_CS43130=y
CONFIG_SND_SOC_CS4341=y
CONFIG_SND_SOC_CS4349=y
CONFIG_SND_SOC_CS53L30=y
CONFIG_SND_SOC_CX2072X=m
CONFIG_SND_SOC_DA7213=m
CONFIG_SND_SOC_DA7219=m
CONFIG_SND_SOC_DMIC=m
CONFIG_SND_SOC_HDMI_CODEC=y
CONFIG_SND_SOC_ES7134=y
CONFIG_SND_SOC_ES7241=y
CONFIG_SND_SOC_ES8316=y
CONFIG_SND_SOC_ES8326=y
CONFIG_SND_SOC_ES8328=y
CONFIG_SND_SOC_ES8328_I2C=y
CONFIG_SND_SOC_ES8328_SPI=y
CONFIG_SND_SOC_GTM601=m
CONFIG_SND_SOC_HDA=y
CONFIG_SND_SOC_ICS43432=y
CONFIG_SND_SOC_INNO_RK3036=y
CONFIG_SND_SOC_MAX98088=y
CONFIG_SND_SOC_MAX98090=m
CONFIG_SND_SOC_MAX98357A=y
CONFIG_SND_SOC_MAX98504=y
CONFIG_SND_SOC_MAX9867=y
CONFIG_SND_SOC_MAX98927=y
CONFIG_SND_SOC_MAX98520=y
CONFIG_SND_SOC_MAX98373=y
CONFIG_SND_SOC_MAX98373_I2C=y
CONFIG_SND_SOC_MAX98390=y
CONFIG_SND_SOC_MAX98396=y
CONFIG_SND_SOC_MAX9860=y
CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
CONFIG_SND_SOC_PCM1681=y
CONFIG_SND_SOC_PCM1789=y
CONFIG_SND_SOC_PCM1789_I2C=y
CONFIG_SND_SOC_PCM179X=y
CONFIG_SND_SOC_PCM179X_I2C=y
CONFIG_SND_SOC_PCM179X_SPI=y
CONFIG_SND_SOC_PCM186X=y
CONFIG_SND_SOC_PCM186X_I2C=y
CONFIG_SND_SOC_PCM186X_SPI=y
CONFIG_SND_SOC_PCM3060=y
CONFIG_SND_SOC_PCM3060_I2C=y
CONFIG_SND_SOC_PCM3060_SPI=y
CONFIG_SND_SOC_PCM3168A=y
CONFIG_SND_SOC_PCM3168A_I2C=y
CONFIG_SND_SOC_PCM3168A_SPI=y
CONFIG_SND_SOC_PCM5102A=y
CONFIG_SND_SOC_PCM512x=y
CONFIG_SND_SOC_PCM512x_I2C=y
CONFIG_SND_SOC_PCM512x_SPI=y
CONFIG_SND_SOC_RK3328=y
CONFIG_SND_SOC_RK817=y
CONFIG_SND_SOC_RL6231=y
CONFIG_SND_SOC_RT5514=m
CONFIG_SND_SOC_RT5514_SPI=m
CONFIG_SND_SOC_RT5616=y
CONFIG_SND_SOC_RT5631=y
CONFIG_SND_SOC_RT5640=y
CONFIG_SND_SOC_RT5645=m
CONFIG_SND_SOC_RT5659=y
CONFIG_SND_SOC_RT9120=y
CONFIG_SND_SOC_SGTL5000=m
CONFIG_SND_SOC_SIGMADSP=m
CONFIG_SND_SOC_SIGMADSP_I2C=m
CONFIG_SND_SOC_SIGMADSP_REGMAP=m
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
CONFIG_SND_SOC_SIMPLE_MUX=y
CONFIG_SND_SOC_SPDIF=y
CONFIG_SND_SOC_SRC4XXX_I2C=m
CONFIG_SND_SOC_SRC4XXX=m
CONFIG_SND_SOC_SSM2305=y
CONFIG_SND_SOC_SSM2518=y
CONFIG_SND_SOC_SSM2602=y
CONFIG_SND_SOC_SSM2602_SPI=y
CONFIG_SND_SOC_SSM2602_I2C=y
CONFIG_SND_SOC_SSM4567=y
CONFIG_SND_SOC_STA32X=m
CONFIG_SND_SOC_STA350=m
CONFIG_SND_SOC_STI_SAS=m
CONFIG_SND_SOC_TAS2552=y
CONFIG_SND_SOC_TAS2562=y
CONFIG_SND_SOC_TAS2764=y
CONFIG_SND_SOC_TAS2770=y
CONFIG_SND_SOC_TAS2780=y
CONFIG_SND_SOC_TAS5086=y
CONFIG_SND_SOC_TAS571X=y
CONFIG_SND_SOC_TAS5720=y
CONFIG_SND_SOC_TAS5805M=y
CONFIG_SND_SOC_TAS6424=y
CONFIG_SND_SOC_TDA7419=m
CONFIG_SND_SOC_TFA9879=m
CONFIG_SND_SOC_TFA989X=m
CONFIG_SND_SOC_TLV320ADC3XXX=y
CONFIG_SND_SOC_TLV320AIC23=y
CONFIG_SND_SOC_TLV320AIC23_I2C=y
CONFIG_SND_SOC_TLV320AIC23_SPI=y
CONFIG_SND_SOC_TLV320AIC31XX=y
CONFIG_SND_SOC_TLV320AIC32X4=y
CONFIG_SND_SOC_TLV320AIC32X4_I2C=y
CONFIG_SND_SOC_TLV320AIC32X4_SPI=y
CONFIG_SND_SOC_TLV320AIC3X=y
CONFIG_SND_SOC_TLV320AIC3X_I2C=y
CONFIG_SND_SOC_TLV320AIC3X_SPI=y
CONFIG_SND_SOC_TLV320ADCX140=y
CONFIG_SND_SOC_TS3A227E=m
CONFIG_SND_SOC_TSCS42XX=m
CONFIG_SND_SOC_TSCS454=m
CONFIG_SND_SOC_UDA1334=m
CONFIG_SND_SOC_WM8510=m
CONFIG_SND_SOC_WM8523=m
CONFIG_SND_SOC_WM8524=m
CONFIG_SND_SOC_WM8580=m
CONFIG_SND_SOC_WM8711=m
CONFIG_SND_SOC_WM8728=m
CONFIG_SND_SOC_WM8731=m
CONFIG_SND_SOC_WM8731_I2C=m
CONFIG_SND_SOC_WM8731_SPI=m
CONFIG_SND_SOC_WM8737=m
CONFIG_SND_SOC_WM8741=m
CONFIG_SND_SOC_WM8750=m
CONFIG_SND_SOC_WM8753=m
CONFIG_SND_SOC_WM8770=m
CONFIG_SND_SOC_WM8776=m
CONFIG_SND_SOC_WM8782=m
CONFIG_SND_SOC_WM8804=m
CONFIG_SND_SOC_WM8804_I2C=m
CONFIG_SND_SOC_WM8804_SPI=m
CONFIG_SND_SOC_WM8903=m
CONFIG_SND_SOC_WM8904=m
CONFIG_SND_SOC_WM8940=m
CONFIG_SND_SOC_WM8960=m
CONFIG_SND_SOC_WM8962=m
CONFIG_SND_SOC_WM8974=m
CONFIG_SND_SOC_WM8978=m
CONFIG_SND_SOC_WM8985=m
CONFIG_SND_SOC_ZL38060=m
CONFIG_SND_SOC_MAX9759=y
CONFIG_SND_SOC_MT6351=y
CONFIG_SND_SOC_MT6358=y
CONFIG_SND_SOC_MT6660=y
CONFIG_SND_SOC_NAU8315=m
CONFIG_SND_SOC_NAU8540=m
CONFIG_SND_SOC_NAU8810=m
CONFIG_SND_SOC_NAU8821=m
CONFIG_SND_SOC_NAU8822=m
CONFIG_SND_SOC_NAU8824=m
CONFIG_SND_SOC_TPA6130A2=y
CONFIG_SND_SOC_LPASS_MACRO_COMMON=m
CONFIG_SND_SOC_LPASS_WSA_MACRO=m
CONFIG_SND_SOC_LPASS_VA_MACRO=m
CONFIG_SND_SOC_LPASS_RX_MACRO=m
CONFIG_SND_SOC_LPASS_TX_MACRO=m
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD2=m
CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
# CONFIG_SND_TEST_COMPONENT is not set
CONFIG_SND_VIRTIO=m
CONFIG_AC97_BUS=y

#
# HID support
#
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=m
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
CONFIG_HID_A4TECH=m
CONFIG_HID_ACCUTOUCH=m
CONFIG_HID_ACRUX=m
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=m
CONFIG_HID_APPLEIR=m
CONFIG_HID_ASUS=m
CONFIG_HID_AUREAL=m
CONFIG_HID_BELKIN=m
CONFIG_HID_BETOP_FF=m
CONFIG_HID_BIGBEN_FF=m
CONFIG_HID_CHERRY=m
CONFIG_HID_CHICONY=m
CONFIG_HID_CORSAIR=m
CONFIG_HID_COUGAR=m
CONFIG_HID_MACALLY=m
CONFIG_HID_PRODIKEYS=m
CONFIG_HID_CMEDIA=m
CONFIG_HID_CP2112=m
CONFIG_HID_CREATIVE_SB0540=m
CONFIG_HID_CYPRESS=m
CONFIG_HID_DRAGONRISE=m
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=m
CONFIG_HID_ELAN=m
CONFIG_HID_ELECOM=m
CONFIG_HID_ELO=m
CONFIG_HID_EZKEY=m
CONFIG_HID_FT260=m
CONFIG_HID_GEMBIRD=m
CONFIG_HID_GFRM=m
CONFIG_HID_GLORIOUS=m
CONFIG_HID_HOLTEK=m
CONFIG_HOLTEK_FF=y
CONFIG_HID_VIVALDI_COMMON=m
CONFIG_HID_VIVALDI=m
CONFIG_HID_GT683R=m
CONFIG_HID_KEYTOUCH=m
CONFIG_HID_KYE=m
CONFIG_HID_UCLOGIC=m
CONFIG_HID_WALTOP=m
CONFIG_HID_VIEWSONIC=m
CONFIG_HID_VRC2=m
CONFIG_HID_XIAOMI=m
CONFIG_HID_GYRATION=m
CONFIG_HID_ICADE=m
CONFIG_HID_ITE=m
CONFIG_HID_JABRA=m
CONFIG_HID_TWINHAN=m
CONFIG_HID_KENSINGTON=m
CONFIG_HID_LCPOWER=m
CONFIG_HID_LED=m
CONFIG_HID_LENOVO=m
CONFIG_HID_LETSKETCH=m
CONFIG_HID_LOGITECH=m
CONFIG_HID_LOGITECH_DJ=m
CONFIG_HID_LOGITECH_HIDPP=m
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
CONFIG_HID_MAGICMOUSE=m
CONFIG_HID_MALTRON=m
CONFIG_HID_MAYFLASH=m
CONFIG_HID_MEGAWORLD_FF=m
CONFIG_HID_REDRAGON=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
CONFIG_HID_MULTITOUCH=m
CONFIG_HID_NINTENDO=m
CONFIG_NINTENDO_FF=y
CONFIG_HID_NTI=m
CONFIG_HID_NTRIG=m
CONFIG_HID_ORTEK=m
CONFIG_HID_PANTHERLORD=m
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PENMOUNT=m
CONFIG_HID_PETALYNX=m
CONFIG_HID_PICOLCD=m
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
CONFIG_HID_PICOLCD_LCD=y
CONFIG_HID_PICOLCD_LEDS=y
CONFIG_HID_PICOLCD_CIR=y
CONFIG_HID_PLANTRONICS=m
CONFIG_HID_PLAYSTATION=m
CONFIG_PLAYSTATION_FF=y
CONFIG_HID_PXRC=m
CONFIG_HID_RAZER=m
CONFIG_HID_PRIMAX=m
CONFIG_HID_RETRODE=m
CONFIG_HID_ROCCAT=m
CONFIG_HID_SAITEK=m
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SEMITEK=m
CONFIG_HID_SIGMAMICRO=m
CONFIG_HID_SONY=m
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=m
CONFIG_HID_STEAM=m
CONFIG_HID_STEELSERIES=m
CONFIG_HID_SUNPLUS=m
CONFIG_HID_RMI=m
CONFIG_HID_GREENASIA=m
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=m
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TIVO=m
CONFIG_HID_TOPSEED=m
CONFIG_HID_TOPRE=m
CONFIG_HID_THINGM=m
CONFIG_HID_THRUSTMASTER=m
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_UDRAW_PS3=m
CONFIG_HID_U2FZERO=m
CONFIG_HID_WACOM=m
CONFIG_HID_WIIMOTE=m
CONFIG_HID_XINMO=m
CONFIG_HID_ZEROPLUS=m
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=m
CONFIG_HID_SENSOR_HUB=m
CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
CONFIG_HID_ALPS=m
CONFIG_HID_MCP2221=m
# end of Special HID drivers

#
# USB HID support
#
CONFIG_USB_HID=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
# end of USB HID support

#
# I2C HID support
#
CONFIG_I2C_HID_ACPI=m
CONFIG_I2C_HID_OF=m
CONFIG_I2C_HID_OF_ELAN=m
CONFIG_I2C_HID_OF_GOODIX=m
# end of I2C HID support

CONFIG_I2C_HID_CORE=m
# end of HID support

CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_LED_TRIG=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_CONN_GPIO=m
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
CONFIG_USB_OTG_FSM=m
CONFIG_USB_LEDS_TRIGGER_USBPORT=m
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=y

#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=m
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=m
CONFIG_USB_XHCI_PCI_RENESAS=m
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_XHCI_SUNXI=m
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_EHCI_FSL=m
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OXU210HP_HCD=m
CONFIG_USB_ISP116X_HCD=m
CONFIG_USB_FOTG210_HCD=m
CONFIG_USB_MAX3421_HCD=m
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_OHCI_HCD_PCI=m
CONFIG_USB_OHCI_HCD_PLATFORM=m
CONFIG_USB_UHCI_HCD=m
CONFIG_USB_U132_HCD=m
CONFIG_USB_SL811_HCD=m
CONFIG_USB_SL811_HCD_ISO=y
CONFIG_USB_R8A66597_HCD=m
CONFIG_USB_HCD_BCMA=m
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=y
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
CONFIG_USB_STORAGE_REALTEK=m
CONFIG_REALTEK_AUTOPM=y
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_FREECOM=m
CONFIG_USB_STORAGE_ISD200=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_STORAGE_ALAUDA=m
CONFIG_USB_STORAGE_ONETOUCH=m
CONFIG_USB_STORAGE_KARMA=m
CONFIG_USB_STORAGE_CYPRESS_ATACB=m
CONFIG_USB_STORAGE_ENE_UB6250=m
CONFIG_USB_UAS=y

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
CONFIG_USB_MICROTEK=m
CONFIG_USBIP_CORE=m
CONFIG_USBIP_VHCI_HCD=m
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=m
CONFIG_USBIP_VUDC=m
# CONFIG_USBIP_DEBUG is not set
# CONFIG_USB_CDNS_SUPPORT is not set
CONFIG_USB_MUSB_HDRC=y
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y

#
# Platform Glue Layer
#
CONFIG_USB_MUSB_SUNXI=m

#
# MUSB DMA mode
#
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_ULPI=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y

#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=y
# CONFIG_USB_DWC3_HAPS is not set
CONFIG_USB_DWC3_MESON_G12A=y
CONFIG_USB_DWC3_OF_SIMPLE=m
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
# CONFIG_USB_DWC2_PCI is not set
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
CONFIG_USB_CHIPIDEA=m
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_CHIPIDEA_PCI=m
CONFIG_USB_CHIPIDEA_MSM=m
CONFIG_USB_CHIPIDEA_IMX=m
CONFIG_USB_CHIPIDEA_GENERIC=m
CONFIG_USB_CHIPIDEA_TEGRA=m
CONFIG_USB_ISP1760=m
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_ISP1761_UDC=y
# CONFIG_USB_ISP1760_HOST_ROLE is not set
# CONFIG_USB_ISP1760_GADGET_ROLE is not set
CONFIG_USB_ISP1760_DUAL_ROLE=y

#
# USB port drivers
#
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=m
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=y
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=y
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=y
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=m
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_F81232=m
CONFIG_USB_SERIAL_F8153X=m
CONFIG_USB_SERIAL_GARMIN=y
CONFIG_USB_SERIAL_IPW=y
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_METRO=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MXUPORT=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=y
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=y
CONFIG_USB_SERIAL_QUALCOMM=y
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
# CONFIG_USB_SERIAL_SAFE_PADDED is not set
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
CONFIG_USB_SERIAL_SYMBOL=y
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_WWAN=y
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=y
CONFIG_USB_SERIAL_XSENS_MT=m
CONFIG_USB_SERIAL_WISHBONE=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_SERIAL_QT2=m
CONFIG_USB_SERIAL_UPD78F0730=m
CONFIG_USB_SERIAL_XR=m
CONFIG_USB_SERIAL_DEBUG=m

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
CONFIG_USB_CYPRESS_CY7C63=m
CONFIG_USB_CYTHERM=m
CONFIG_USB_IDMOUSE=m
CONFIG_USB_FTDI_ELAN=m
CONFIG_USB_APPLEDISPLAY=m
# CONFIG_APPLE_MFI_FASTCHARGE is not set
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
CONFIG_USB_TEST=m
CONFIG_USB_EHSET_TEST_FIXTURE=m
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=m
CONFIG_USB_HUB_USB251XB=m
CONFIG_USB_HSIC_USB3503=m
CONFIG_USB_HSIC_USB4604=m
CONFIG_USB_LINK_LAYER_TEST=m
CONFIG_USB_CHAOSKEY=m
CONFIG_USB_ONBOARD_HUB=y

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=m
CONFIG_USB_GPIO_VBUS=m
CONFIG_USB_ISP1301=m
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set

#
# USB Peripheral Controller
#
CONFIG_USB_FOTG210_UDC=m
CONFIG_USB_GR_UDC=m
CONFIG_USB_R8A66597=m
CONFIG_USB_PXA27X=m
CONFIG_USB_MV_UDC=m
CONFIG_USB_MV_U3D=m
CONFIG_USB_SNP_CORE=m
CONFIG_USB_SNP_UDC_PLAT=m
CONFIG_USB_M66592=m
CONFIG_USB_BDC_UDC=m
CONFIG_USB_AMD5536UDC=m
CONFIG_USB_NET2272=m
CONFIG_USB_NET2272_DMA=y
CONFIG_USB_NET2280=m
CONFIG_USB_GOKU=m
CONFIG_USB_EG20T=m
CONFIG_USB_GADGET_XILINX=m
CONFIG_USB_MAX3420_UDC=m
CONFIG_USB_DUMMY_HCD=m
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=m
CONFIG_USB_F_ACM=m
CONFIG_USB_F_SS_LB=m
CONFIG_USB_U_SERIAL=m
CONFIG_USB_U_ETHER=m
CONFIG_USB_U_AUDIO=m
CONFIG_USB_F_SERIAL=m
CONFIG_USB_F_OBEX=m
CONFIG_USB_F_NCM=m
CONFIG_USB_F_ECM=m
CONFIG_USB_F_EEM=m
CONFIG_USB_F_SUBSET=m
CONFIG_USB_F_RNDIS=m
CONFIG_USB_F_MASS_STORAGE=m
CONFIG_USB_F_FS=m
CONFIG_USB_F_UAC1=m
CONFIG_USB_F_UAC1_LEGACY=m
CONFIG_USB_F_UAC2=m
CONFIG_USB_F_UVC=m
CONFIG_USB_F_MIDI=m
CONFIG_USB_F_HID=m
CONFIG_USB_F_PRINTER=m
CONFIG_USB_F_TCM=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_LB_SS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y
CONFIG_USB_CONFIGFS_F_TCM=y

#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=m
CONFIG_USB_ZERO_HNPTEST=y
CONFIG_USB_AUDIO=m
CONFIG_GADGET_UAC1=y
CONFIG_GADGET_UAC1_LEGACY=y
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
CONFIG_USB_FUNCTIONFS_ETH=y
CONFIG_USB_FUNCTIONFS_RNDIS=y
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_GADGET_TARGET=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_G_HID=m
CONFIG_USB_G_DBGP=m
# CONFIG_USB_G_DBGP_PRINTK is not set
CONFIG_USB_G_DBGP_SERIAL=y
CONFIG_USB_G_WEBCAM=m
CONFIG_USB_RAW_GADGET=m
# end of USB Gadget precomposed configurations

CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
CONFIG_TYPEC_ET7303=m
CONFIG_TYPEC_HUSB311=m
CONFIG_TYPEC_RT1711H=m
CONFIG_TYPEC_TCPCI_MAXIM=m
CONFIG_TYPEC_FUSB302=m
CONFIG_TYPEC_UCSI=y
CONFIG_UCSI_CCG=m
CONFIG_UCSI_ACPI=m
CONFIG_UCSI_STM32G0=m
CONFIG_TYPEC_TPS6598X=m
CONFIG_TYPEC_ANX7411=m
CONFIG_TYPEC_RT1719=m
CONFIG_TYPEC_HD3SS3220=m
CONFIG_TYPEC_STUSB160X=m
CONFIG_TYPEC_WUSB3801=m

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
CONFIG_TYPEC_MUX_FSA4480=m
CONFIG_TYPEC_MUX_PI3USB30532=m
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
CONFIG_TYPEC_DP_ALTMODE=m
CONFIG_TYPEC_NVIDIA_ALTMODE=m
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
# CONFIG_PWRSEQ_SD8787 is not set
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set
# CONFIG_MMC_CRYPTO is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_ARMMMCI=m
CONFIG_MMC_STM32_SDMMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_PCI=m
CONFIG_MMC_RICOH_MMC=y
CONFIG_MMC_SDHCI_ACPI=m
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=m
CONFIG_MMC_SDHCI_OF_AT91=m
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_MMC_SDHCI_CADENCE=m
CONFIG_MMC_SDHCI_F_SDH30=m
CONFIG_MMC_SDHCI_MILBEAUT=m
CONFIG_MMC_MESON_GX=y
CONFIG_MMC_MESON_MX_SDIO=y
CONFIG_MMC_TIFM_SD=m
CONFIG_MMC_SPI=m
CONFIG_MMC_CB710=m
CONFIG_MMC_VIA_SDMMC=m
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
CONFIG_MMC_DW_BLUEFIELD=m
CONFIG_MMC_DW_EXYNOS=m
CONFIG_MMC_DW_HI3798CV200=m
CONFIG_MMC_DW_K3=m
CONFIG_MMC_DW_PCI=m
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_VUB300=m
CONFIG_MMC_USHC=m
CONFIG_MMC_USDHI6ROL0=m
CONFIG_MMC_REALTEK_USB=m
CONFIG_MMC_SUNXI=y
CONFIG_MMC_CQHCI=m
CONFIG_MMC_HSQ=y
CONFIG_MMC_TOSHIBA_PCI=m
CONFIG_MMC_MTK=m
CONFIG_MMC_SDHCI_XENON=m
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
CONFIG_LEDS_CLASS_MULTICOLOR=y
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y

#
# LED drivers
#
CONFIG_LEDS_AN30259A=m
CONFIG_LEDS_AW2013=m
CONFIG_LEDS_BCM6328=m
CONFIG_LEDS_BCM6358=m
CONFIG_LEDS_CR0014114=m
CONFIG_LEDS_EL15203000=m
CONFIG_LEDS_LM3530=m
CONFIG_LEDS_LM3532=m
CONFIG_LEDS_LM3642=m
CONFIG_LEDS_LM3692X=m
CONFIG_LEDS_PCA9532=m
CONFIG_LEDS_PCA9532_GPIO=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=m
CONFIG_LEDS_LP3952=m
CONFIG_LEDS_LP50XX=m
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LEDS_LP5521=m
CONFIG_LEDS_LP5523=m
CONFIG_LEDS_LP5562=m
CONFIG_LEDS_LP8501=m
CONFIG_LEDS_LP8860=m
CONFIG_LEDS_PCA955X=m
CONFIG_LEDS_PCA955X_GPIO=y
CONFIG_LEDS_PCA963X=m
CONFIG_LEDS_DAC124S085=m
CONFIG_LEDS_PWM=y
CONFIG_LEDS_REGULATOR=y
CONFIG_LEDS_BD2802=m
CONFIG_LEDS_LT3593=m
CONFIG_LEDS_TCA6507=y
CONFIG_LEDS_TLC591XX=m
CONFIG_LEDS_LM355x=m
CONFIG_LEDS_IS31FL319X=m
CONFIG_LEDS_IS31FL32XX=m

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=m
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_MLXREG=m
CONFIG_LEDS_USER=y
CONFIG_LEDS_SPI_BYTE=m
CONFIG_LEDS_TI_LMU_COMMON=m
CONFIG_LEDS_LM3697=m

#
# Flash and Torch LED drivers
#
CONFIG_LEDS_AAT1290=m
CONFIG_LEDS_AS3645A=m
CONFIG_LEDS_KTD2692=m
CONFIG_LEDS_LM3601X=m
CONFIG_LEDS_RT4505=m
CONFIG_LEDS_RT8515=m
CONFIG_LEDS_SGM3140=m

#
# RGB LED drivers
#
CONFIG_LEDS_PWM_MULTICOLOR=y
CONFIG_LEDS_QCOM_LPG=m

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_ACTIVITY=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=y
CONFIG_LEDS_TRIGGER_PATTERN=y
CONFIG_LEDS_TRIGGER_AUDIO=y
CONFIG_LEDS_TRIGGER_TTY=y
# CONFIG_LEDS_TRIGGER_BLKDEV is not set

#
# Simple LED drivers
#
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
# CONFIG_EDAC_DEBUG is not set
# CONFIG_EDAC_GHES is not set
# CONFIG_EDAC_THUNDERX is not set
# CONFIG_EDAC_XGENE is not set
CONFIG_EDAC_DMC520=m
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_ABB5ZES3 is not set
# CONFIG_RTC_DRV_ABEOZ9 is not set
# CONFIG_RTC_DRV_ABX80X is not set
CONFIG_RTC_DRV_AC100=y
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
CONFIG_RTC_DRV_HYM8563=y
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_NCT3018Y is not set
CONFIG_RTC_DRV_RK808=y
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_ISL12026 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8523 is not set
# CONFIG_RTC_DRV_PCF85063 is not set
# CONFIG_RTC_DRV_PCF85363 is not set
CONFIG_RTC_DRV_PCF8563=y
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8010 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV3028 is not set
# CONFIG_RTC_DRV_RV3032 is not set
# CONFIG_RTC_DRV_RV8803 is not set
# CONFIG_RTC_DRV_SD3078 is not set

#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_MCP795 is not set
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_PCF2127 is not set
# CONFIG_RTC_DRV_RV3029C2 is not set
# CONFIG_RTC_DRV_RX6110 is not set

#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1685_FAMILY is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_DS2404 is not set
CONFIG_RTC_DRV_EFI=y
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
# CONFIG_RTC_DRV_OPTEE is not set
# CONFIG_RTC_DRV_ZYNQMP is not set

#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_MESON_VRTC=y
CONFIG_RTC_DRV_PL030=m
CONFIG_RTC_DRV_PL031=m
CONFIG_RTC_DRV_SUN6I=y
# CONFIG_RTC_DRV_CADENCE is not set
# CONFIG_RTC_DRV_FTRTC010 is not set
# CONFIG_RTC_DRV_R7301 is not set

#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
# CONFIG_RTC_DRV_GOLDFISH is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
CONFIG_AMBA_PL08X=y
# CONFIG_BCM_SBA_RAID is not set
CONFIG_DMA_SUN6I=y
CONFIG_DW_AXI_DMAC=y
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_MV_XOR_V2 is not set
CONFIG_PL330_DMA=y
# CONFIG_PLX_DMA is not set
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
# CONFIG_XILINX_ZYNQMP_DPDMA is not set
# CONFIG_QCOM_HIDMA_MGMT is not set
# CONFIG_QCOM_HIDMA is not set
CONFIG_DW_DMAC_CORE=y
CONFIG_DW_DMAC=y
# CONFIG_DW_DMAC_PCI is not set
CONFIG_DW_EDMA=y
# CONFIG_DW_EDMA_PCIE is not set
# CONFIG_SF_PDMA is not set

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_DEBUG is not set
# CONFIG_DMABUF_SELFTESTS is not set
# CONFIG_DMABUF_HEAPS is not set
# CONFIG_DMABUF_SYSFS_STATS is not set
# end of DMABUF options

CONFIG_AUXDISPLAY=y
CONFIG_CHARLCD=m
CONFIG_LINEDISP=m
CONFIG_HD44780_COMMON=m
CONFIG_HD44780=m
CONFIG_IMG_ASCII_LCD=m
CONFIG_HT16K33=m
CONFIG_LCD2S=m
CONFIG_TM1628=m
CONFIG_OPENVFD=m
# CONFIG_PANEL_CHANGE_MESSAGE is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
# CONFIG_UIO is not set
# CONFIG_VFIO is not set
CONFIG_VIRT_DRIVERS=y
CONFIG_VMGENID=y
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_PCI_LIB=m
CONFIG_VIRTIO_PCI_LIB_LEGACY=m
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=m
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
# CONFIG_VDPA is not set
CONFIG_VHOST_IOTLB=m
CONFIG_VHOST=m
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_SCSI=m
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set

#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
# CONFIG_COMEDI is not set
CONFIG_STAGING=y
# CONFIG_PRISM2_USB is not set
CONFIG_RTL8192U=m
CONFIG_RTLLIB=m
CONFIG_RTLLIB_CRYPTO_CCMP=m
CONFIG_RTLLIB_CRYPTO_TKIP=m
CONFIG_RTLLIB_CRYPTO_WEP=m
CONFIG_RTL8192E=m
CONFIG_RTL8723BS=m
CONFIG_RTS5208=m
CONFIG_VT6655=m
CONFIG_VT6656=m

#
# IIO staging drivers
#

#
# Accelerometers
#
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16240 is not set
# end of Accelerometers

#
# Analog to digital converters
#
# CONFIG_AD7816 is not set
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
# CONFIG_ADT7316 is not set
# end of Analog digital bi-direction converters

#
# Direct Digital Synthesis
#
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
# CONFIG_AD5933 is not set
# end of Network Analyzer, Impedance Converters

#
# Active energy metering IC
#
# CONFIG_ADE7854 is not set
# end of Active energy metering IC

#
# Resolver to digital converters
#
# CONFIG_AD2S1210 is not set
# end of Resolver to digital converters
# end of IIO staging drivers

# CONFIG_FB_SM750 is not set
CONFIG_STAGING_MEDIA=y
# CONFIG_VIDEO_MAX96712 is not set
CONFIG_VIDEO_MESON_VDEC=m
CONFIG_VIDEO_ROCKCHIP_VDEC=m
CONFIG_VIDEO_SUNXI=y
CONFIG_VIDEO_SUNXI_CEDRUS=m
# CONFIG_STAGING_MEDIA_DEPRECATED is not set
# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
CONFIG_FB_TFT=m
# CONFIG_FB_TFT_AGM1264K_FL is not set
# CONFIG_FB_TFT_BD663474 is not set
# CONFIG_FB_TFT_HX8340BN is not set
# CONFIG_FB_TFT_HX8347D is not set
# CONFIG_FB_TFT_HX8353D is not set
# CONFIG_FB_TFT_HX8357D is not set
# CONFIG_FB_TFT_ILI9163 is not set
# CONFIG_FB_TFT_ILI9320 is not set
# CONFIG_FB_TFT_ILI9325 is not set
# CONFIG_FB_TFT_ILI9340 is not set
# CONFIG_FB_TFT_ILI9341 is not set
# CONFIG_FB_TFT_ILI9481 is not set
# CONFIG_FB_TFT_ILI9486 is not set
# CONFIG_FB_TFT_PCD8544 is not set
# CONFIG_FB_TFT_RA8875 is not set
# CONFIG_FB_TFT_S6D02A1 is not set
# CONFIG_FB_TFT_S6D1121 is not set
# CONFIG_FB_TFT_SEPS525 is not set
# CONFIG_FB_TFT_SH1106 is not set
# CONFIG_FB_TFT_SSD1289 is not set
# CONFIG_FB_TFT_SSD1305 is not set
# CONFIG_FB_TFT_SSD1306 is not set
# CONFIG_FB_TFT_SSD1331 is not set
# CONFIG_FB_TFT_SSD1351 is not set
CONFIG_FB_TFT_ST7735R=m
CONFIG_FB_TFT_ST7735S=m
# CONFIG_FB_TFT_ST7789V is not set
# CONFIG_FB_TFT_TINYLCD is not set
# CONFIG_FB_TFT_TLS8204 is not set
# CONFIG_FB_TFT_UC1611 is not set
# CONFIG_FB_TFT_UC1701 is not set
# CONFIG_FB_TFT_UPD161704 is not set
# CONFIG_KS7010 is not set
# CONFIG_PI433 is not set
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_QLGE is not set
# CONFIG_VME_BUS is not set
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
CONFIG_SURFACE_PLATFORMS=y
# CONFIG_SURFACE_3_POWER_OPREGION is not set
# CONFIG_SURFACE_GPE is not set
# CONFIG_SURFACE_HOTPLUG is not set
# CONFIG_SURFACE_PRO3_BUTTON is not set
# CONFIG_SURFACE_AGGREGATOR is not set
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Clock driver for ARM Reference designs
#
# CONFIG_CLK_ICST is not set
# CONFIG_CLK_SP810 is not set
# CONFIG_CLK_VEXPRESS_OSC is not set
# end of Clock driver for ARM Reference designs

# CONFIG_LMK04832 is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
CONFIG_COMMON_CLK_CS2000_CP=y
# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
# CONFIG_COMMON_CLK_XGENE is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_RS9_PCIE is not set
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_VC7 is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set

#
# Clock support for Amlogic platforms
#
CONFIG_COMMON_CLK_MESON_REGMAP=y
CONFIG_COMMON_CLK_MESON_DUALDIV=y
CONFIG_COMMON_CLK_MESON_MPLL=y
CONFIG_COMMON_CLK_MESON_PHASE=y
CONFIG_COMMON_CLK_MESON_PLL=y
CONFIG_COMMON_CLK_MESON_SCLK_DIV=y
CONFIG_COMMON_CLK_MESON_VID_PLL_DIV=y
CONFIG_COMMON_CLK_MESON_AO_CLKC=y
CONFIG_COMMON_CLK_MESON_EE_CLKC=y
CONFIG_COMMON_CLK_MESON_CPU_DYNDIV=y
CONFIG_COMMON_CLK_GXBB=y
CONFIG_COMMON_CLK_AXG=y
CONFIG_COMMON_CLK_AXG_AUDIO=y
CONFIG_COMMON_CLK_G12A=y
# end of Clock support for Amlogic platforms

CONFIG_COMMON_CLK_ROCKCHIP=y
CONFIG_CLK_PX30=y
CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
CONFIG_CLK_RK3399=y
CONFIG_CLK_RK3568=y
CONFIG_SUNXI_CCU=y
CONFIG_SUN50I_A64_CCU=y
CONFIG_SUN50I_A100_CCU=y
CONFIG_SUN50I_A100_R_CCU=y
CONFIG_SUN50I_H6_CCU=y
CONFIG_SUN50I_H616_CCU=y
CONFIG_SUN50I_H6_R_CCU=y
CONFIG_SUN6I_RTC_CCU=y
CONFIG_SUN8I_H3_CCU=y
CONFIG_SUN8I_DE2_CCU=y
CONFIG_SUN8I_R_CCU=y
# CONFIG_XILINX_VCU is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_SUN6I=y

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_ACPI=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_SUN4I_TIMER=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
CONFIG_ARM_TIMER_SP804=y
CONFIG_MICROCHIP_PIT64B=y
# end of Clock Source drivers

CONFIG_MAILBOX=y
CONFIG_ARM_MHU=y
CONFIG_ARM_MHU_V2=m
CONFIG_PLATFORM_MHU=y
CONFIG_PL320_MBOX=y
CONFIG_ROCKCHIP_MBOX=y
# CONFIG_PCC is not set
CONFIG_ALTERA_MBOX=m
# CONFIG_MAILBOX_TEST is not set
CONFIG_SUN6I_MSGBOX=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOASID=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_DART is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
CONFIG_IOMMU_SVA=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_SUN50I_IOMMU=y
CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
CONFIG_ARM_SMMU_V3=y
CONFIG_ARM_SMMU_V3_SVA=y
CONFIG_VIRTIO_IOMMU=m

#
# Remoteproc drivers
#
CONFIG_REMOTEPROC=y
CONFIG_REMOTEPROC_CDEV=y
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=m
CONFIG_RPMSG_CHAR=m
# CONFIG_RPMSG_CTRL is not set
CONFIG_RPMSG_NS=m
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
CONFIG_RPMSG_VIRTIO=m
# end of Rpmsg drivers

# CONFIG_SOUNDWIRE is not set

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
CONFIG_MESON_CANVAS=y
CONFIG_MESON_CLK_MEASURE=y
CONFIG_MESON_GX_SOCINFO=y
CONFIG_MESON_GX_PM_DOMAINS=y
CONFIG_MESON_EE_PM_DOMAINS=y
CONFIG_MESON_SECURE_PM_DOMAINS=y
# end of Amlogic SoC drivers

#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
CONFIG_QUICC_ENGINE=y
# end of NXP/Freescale QorIQ SoC drivers

#
# fujitsu SoC drivers
#
# CONFIG_A64FX_DIAG is not set
# end of fujitsu SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Enable LiteX SoC Builder specific drivers
#
# CONFIG_LITEX_SOC_CONTROLLER is not set
# end of Enable LiteX SoC Builder specific drivers

#
# Qualcomm SoC drivers
#
CONFIG_QCOM_QMI_HELPERS=m
# end of Qualcomm SoC drivers

CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_SUNXI_MBUS=y
CONFIG_SUNXI_SRAM=y
# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=m
CONFIG_DEVFREQ_GOV_USERSPACE=m
CONFIG_DEVFREQ_GOV_PASSIVE=m

#
# DEVFREQ Drivers
#
CONFIG_ARM_RK3399_DMC_DEVFREQ=y
CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
CONFIG_EXTCON_ADC_JACK=m
CONFIG_EXTCON_FSA9480=m
CONFIG_EXTCON_GPIO=m
CONFIG_EXTCON_MAX3355=m
CONFIG_EXTCON_PTN5150=m
CONFIG_EXTCON_RT8973A=m
CONFIG_EXTCON_SM5502=m
CONFIG_EXTCON_USB_GPIO=m
CONFIG_EXTCON_USBC_TUSB320=m
CONFIG_MEMORY=y
CONFIG_ARM_PL172_MPMC=m
# CONFIG_FPGA_DFL_EMIF is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
CONFIG_IIO_BUFFER_DMA=m
CONFIG_IIO_BUFFER_DMAENGINE=m
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
CONFIG_IIO_TRIGGERED_EVENT=m

#
# Accelerometers
#
CONFIG_ADIS16201=m
CONFIG_ADIS16209=m
CONFIG_ADXL313=m
CONFIG_ADXL313_I2C=m
CONFIG_ADXL313_SPI=m
CONFIG_ADXL345=m
CONFIG_ADXL345_I2C=m
CONFIG_ADXL345_SPI=m
CONFIG_ADXL355=m
CONFIG_ADXL355_I2C=m
CONFIG_ADXL355_SPI=m
CONFIG_ADXL367=m
CONFIG_ADXL367_SPI=m
CONFIG_ADXL367_I2C=m
CONFIG_ADXL372=m
CONFIG_ADXL372_SPI=m
CONFIG_ADXL372_I2C=m
CONFIG_BMA180=m
CONFIG_BMA220=m
CONFIG_BMA400=m
CONFIG_BMA400_I2C=m
CONFIG_BMA400_SPI=m
CONFIG_BMC150_ACCEL=m
CONFIG_BMC150_ACCEL_I2C=m
CONFIG_BMC150_ACCEL_SPI=m
CONFIG_BMI088_ACCEL=m
CONFIG_BMI088_ACCEL_SPI=m
CONFIG_DA280=m
CONFIG_DA311=m
CONFIG_DMARD06=m
CONFIG_DMARD09=m
CONFIG_DMARD10=m
CONFIG_FXLS8962AF=m
CONFIG_FXLS8962AF_I2C=m
CONFIG_FXLS8962AF_SPI=m
CONFIG_HID_SENSOR_ACCEL_3D=m
CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
CONFIG_KXSD9=m
CONFIG_KXSD9_SPI=m
CONFIG_KXSD9_I2C=m
CONFIG_KXCJK1013=m
CONFIG_MC3230=m
CONFIG_MMA7455=m
CONFIG_MMA7455_I2C=m
CONFIG_MMA7455_SPI=m
CONFIG_MMA7660=m
CONFIG_MMA8452=m
CONFIG_MMA9551_CORE=m
CONFIG_MMA9551=m
CONFIG_MMA9553=m
CONFIG_MSA311=m
CONFIG_MXC4005=m
CONFIG_MXC6255=m
CONFIG_SCA3000=m
CONFIG_SCA3300=m
CONFIG_STK8312=m
CONFIG_STK8BA50=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=m
CONFIG_AD7091R5=m
CONFIG_AD7124=m
CONFIG_AD7192=m
CONFIG_AD7266=m
CONFIG_AD7280=m
CONFIG_AD7291=m
CONFIG_AD7292=m
CONFIG_AD7298=m
CONFIG_AD7476=m
CONFIG_AD7606=m
CONFIG_AD7606_IFACE_PARALLEL=m
CONFIG_AD7606_IFACE_SPI=m
CONFIG_AD7766=m
CONFIG_AD7768_1=m
CONFIG_AD7780=m
CONFIG_AD7791=m
CONFIG_AD7793=m
CONFIG_AD7887=m
CONFIG_AD7923=m
CONFIG_AD7949=m
CONFIG_AD799X=m
CONFIG_AD9467=m
CONFIG_ADI_AXI_ADC=m
CONFIG_AXP20X_ADC=y
CONFIG_AXP288_ADC=y
CONFIG_CC10001_ADC=m
CONFIG_ENVELOPE_DETECTOR=m
CONFIG_HI8435=m
CONFIG_HX711=m
CONFIG_INA2XX_ADC=m
CONFIG_LTC2471=m
CONFIG_LTC2485=m
CONFIG_LTC2496=m
CONFIG_LTC2497=m
CONFIG_MAX1027=m
CONFIG_MAX11100=m
CONFIG_MAX1118=m
CONFIG_MAX11205=m
CONFIG_MAX1241=m
CONFIG_MAX1363=m
CONFIG_MAX9611=m
CONFIG_MCP320X=m
CONFIG_MCP3422=m
CONFIG_MCP3911=m
CONFIG_MESON_SARADC=y
CONFIG_NAU7802=m
CONFIG_QCOM_VADC_COMMON=m
CONFIG_QCOM_SPMI_IADC=m
CONFIG_QCOM_SPMI_VADC=m
CONFIG_QCOM_SPMI_ADC5=m
CONFIG_ROCKCHIP_SARADC=y
CONFIG_RICHTEK_RTQ6056=m
CONFIG_SD_ADC_MODULATOR=m
CONFIG_TI_ADC081C=m
CONFIG_TI_ADC0832=m
CONFIG_TI_ADC084S021=m
CONFIG_TI_ADC12138=m
CONFIG_TI_ADC108S102=m
CONFIG_TI_ADC128S052=m
CONFIG_TI_ADC161S626=m
CONFIG_TI_ADS1015=m
CONFIG_TI_ADS7950=m
CONFIG_TI_ADS8344=m
CONFIG_TI_ADS8688=m
CONFIG_TI_ADS124S08=m
CONFIG_TI_ADS131E08=m
CONFIG_TI_TLC4541=m
CONFIG_TI_TSC2046=m
CONFIG_VF610_ADC=m
CONFIG_XILINX_XADC=m
# end of Analog to digital converters

#
# Analog to digital and digital to analog converters
#
CONFIG_AD74413R=m
# end of Analog to digital and digital to analog converters

#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=m
# end of Analog Front Ends

#
# Amplifiers
#
CONFIG_AD8366=m
CONFIG_ADA4250=m
CONFIG_HMC425=m
# end of Amplifiers

#
# Capacitance to digital converters
#
CONFIG_AD7150=m
CONFIG_AD7746=m
# end of Capacitance to digital converters

#
# Chemical Sensors
#
CONFIG_ATLAS_PH_SENSOR=m
CONFIG_ATLAS_EZO_SENSOR=m
CONFIG_BME680=m
CONFIG_BME680_I2C=m
CONFIG_BME680_SPI=m
CONFIG_CCS811=m
CONFIG_IAQCORE=m
CONFIG_PMS7003=m
CONFIG_SCD30_CORE=m
CONFIG_SCD30_I2C=m
CONFIG_SCD30_SERIAL=m
CONFIG_SCD4X=m
CONFIG_SENSIRION_SGP30=m
CONFIG_SENSIRION_SGP40=m
CONFIG_SPS30=m
CONFIG_SPS30_I2C=m
CONFIG_SPS30_SERIAL=m
CONFIG_SENSEAIR_SUNRISE_CO2=m
CONFIG_VZ89X=m
# end of Chemical Sensors

#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
# end of Hid Sensor IIO Common

CONFIG_IIO_MS_SENSORS_I2C=m

#
# IIO SCMI Sensors
#
CONFIG_IIO_SCMI=m
# end of IIO SCMI Sensors

#
# SSP Sensor Common
#
CONFIG_IIO_SSP_SENSORS_COMMONS=m
CONFIG_IIO_SSP_SENSORHUB=m
# end of SSP Sensor Common

CONFIG_IIO_ST_SENSORS_I2C=m
CONFIG_IIO_ST_SENSORS_SPI=m
CONFIG_IIO_ST_SENSORS_CORE=m

#
# Digital to analog converters
#
CONFIG_AD3552R=m
CONFIG_AD5064=m
CONFIG_AD5360=m
CONFIG_AD5380=m
CONFIG_AD5421=m
CONFIG_AD5446=m
CONFIG_AD5449=m
CONFIG_AD5592R_BASE=m
CONFIG_AD5592R=m
CONFIG_AD5593R=m
CONFIG_AD5504=m
CONFIG_AD5624R_SPI=m
CONFIG_LTC2688=m
CONFIG_AD5686=m
CONFIG_AD5686_SPI=m
CONFIG_AD5696_I2C=m
CONFIG_AD5755=m
CONFIG_AD5758=m
CONFIG_AD5761=m
CONFIG_AD5764=m
CONFIG_AD5766=m
CONFIG_AD5770R=m
CONFIG_AD5791=m
CONFIG_AD7293=m
CONFIG_AD7303=m
CONFIG_AD8801=m
CONFIG_DPOT_DAC=m
CONFIG_DS4424=m
CONFIG_LTC1660=m
CONFIG_LTC2632=m
CONFIG_M62332=m
CONFIG_MAX517=m
CONFIG_MAX5821=m
CONFIG_MCP4725=m
CONFIG_MCP4922=m
CONFIG_TI_DAC082S085=m
CONFIG_TI_DAC5571=m
CONFIG_TI_DAC7311=m
CONFIG_TI_DAC7612=m
CONFIG_VF610_DAC=m
# end of Digital to analog converters

#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver

#
# Filters
#
CONFIG_ADMV8818=m
# end of Filters

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
CONFIG_AD9523=m
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4350=m
CONFIG_ADF4371=m
CONFIG_ADMV1013=m
CONFIG_ADMV1014=m
CONFIG_ADMV4420=m
CONFIG_ADRF6780=m
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=m
CONFIG_ADIS16130=m
CONFIG_ADIS16136=m
CONFIG_ADIS16260=m
CONFIG_ADXRS290=m
CONFIG_ADXRS450=m
CONFIG_BMG160=m
CONFIG_BMG160_I2C=m
CONFIG_BMG160_SPI=m
CONFIG_FXAS21002C=m
CONFIG_FXAS21002C_I2C=m
CONFIG_FXAS21002C_SPI=m
CONFIG_HID_SENSOR_GYRO_3D=m
CONFIG_MPU3050=m
CONFIG_MPU3050_I2C=m
CONFIG_IIO_ST_GYRO_3AXIS=m
CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
CONFIG_ITG3200=m
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
CONFIG_AFE4403=m
CONFIG_AFE4404=m
CONFIG_MAX30100=m
CONFIG_MAX30102=m
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
CONFIG_AM2315=m
CONFIG_DHT11=m
CONFIG_HDC100X=m
CONFIG_HDC2010=m
CONFIG_HID_SENSOR_HUMIDITY=m
CONFIG_HTS221=m
CONFIG_HTS221_I2C=m
CONFIG_HTS221_SPI=m
CONFIG_HTU21=m
CONFIG_SI7005=m
CONFIG_SI7020=m
# end of Humidity sensors

#
# Inertial measurement units
#
CONFIG_ADIS16400=m
CONFIG_ADIS16460=m
CONFIG_ADIS16475=m
CONFIG_ADIS16480=m
CONFIG_BMI160=m
CONFIG_BMI160_I2C=m
CONFIG_BMI160_SPI=m
CONFIG_BOSCH_BNO055=m
CONFIG_BOSCH_BNO055_SERIAL=m
CONFIG_BOSCH_BNO055_I2C=m
CONFIG_FXOS8700=m
CONFIG_FXOS8700_I2C=m
CONFIG_FXOS8700_SPI=m
CONFIG_KMX61=m
CONFIG_INV_ICM42600=m
CONFIG_INV_ICM42600_I2C=m
CONFIG_INV_ICM42600_SPI=m
CONFIG_INV_MPU6050_IIO=m
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_SPI=m
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_LSM6DSX_I2C=m
CONFIG_IIO_ST_LSM6DSX_SPI=m
CONFIG_IIO_ST_LSM9DS0=m
CONFIG_IIO_ST_LSM9DS0_I2C=m
CONFIG_IIO_ST_LSM9DS0_SPI=m
# end of Inertial measurement units

CONFIG_IIO_ADIS_LIB=m
CONFIG_IIO_ADIS_LIB_BUFFER=y

#
# Light sensors
#
CONFIG_ACPI_ALS=m
CONFIG_ADJD_S311=m
CONFIG_ADUX1020=m
CONFIG_AL3010=m
CONFIG_AL3320A=m
CONFIG_APDS9300=m
CONFIG_APDS9960=m
CONFIG_AS73211=m
CONFIG_BH1750=m
CONFIG_BH1780=m
CONFIG_CM32181=m
CONFIG_CM3232=m
CONFIG_CM3323=m
CONFIG_CM3605=m
CONFIG_CM36651=m
CONFIG_GP2AP002=m
CONFIG_GP2AP020A00F=m
CONFIG_SENSORS_ISL29018=m
CONFIG_SENSORS_ISL29028=m
CONFIG_ISL29125=m
CONFIG_HID_SENSOR_ALS=m
CONFIG_HID_SENSOR_PROX=m
CONFIG_JSA1212=m
CONFIG_RPR0521=m
CONFIG_LTR501=m
CONFIG_LTRF216A=m
CONFIG_LV0104CS=m
CONFIG_MAX44000=m
CONFIG_MAX44009=m
CONFIG_NOA1305=m
CONFIG_OPT3001=m
CONFIG_PA12203001=m
CONFIG_SI1133=m
CONFIG_SI1145=m
CONFIG_STK3310=m
CONFIG_ST_UVIS25=m
CONFIG_ST_UVIS25_I2C=m
CONFIG_ST_UVIS25_SPI=m
CONFIG_TCS3414=m
CONFIG_TCS3472=m
CONFIG_SENSORS_TSL2563=m
CONFIG_TSL2583=m
CONFIG_TSL2591=m
CONFIG_TSL2772=m
CONFIG_TSL4531=m
CONFIG_US5182D=m
CONFIG_VCNL4000=m
CONFIG_VCNL4035=m
CONFIG_VEML6030=m
CONFIG_VEML6070=m
CONFIG_VL6180=m
CONFIG_ZOPT2201=m
# end of Light sensors

#
# Magnetometer sensors
#
CONFIG_AK8974=m
CONFIG_AK8975=m
CONFIG_AK09911=m
CONFIG_BMC150_MAGN=m
CONFIG_BMC150_MAGN_I2C=m
CONFIG_BMC150_MAGN_SPI=m
CONFIG_MAG3110=m
CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
CONFIG_MMC35240=m
CONFIG_IIO_ST_MAGN_3AXIS=m
CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
CONFIG_SENSORS_HMC5843=m
CONFIG_SENSORS_HMC5843_I2C=m
CONFIG_SENSORS_HMC5843_SPI=m
CONFIG_SENSORS_RM3100=m
CONFIG_SENSORS_RM3100_I2C=m
CONFIG_SENSORS_RM3100_SPI=m
CONFIG_YAMAHA_YAS530=m
# end of Magnetometer sensors

#
# Multiplexers
#
CONFIG_IIO_MUX=m
# end of Multiplexers

#
# Inclinometer sensors
#
CONFIG_HID_SENSOR_INCLINOMETER_3D=m
CONFIG_HID_SENSOR_DEVICE_ROTATION=m
# end of Inclinometer sensors

#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=m
CONFIG_IIO_INTERRUPT_TRIGGER=m
CONFIG_IIO_TIGHTLOOP_TRIGGER=m
CONFIG_IIO_SYSFS_TRIGGER=y
# end of Triggers - standalone

#
# Linear and angular position sensors
#
CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
# end of Linear and angular position sensors

#
# Digital potentiometers
#
CONFIG_AD5110=m
CONFIG_AD5272=m
CONFIG_DS1803=m
CONFIG_MAX5432=m
CONFIG_MAX5481=m
CONFIG_MAX5487=m
CONFIG_MCP4018=m
CONFIG_MCP4131=m
CONFIG_MCP4531=m
CONFIG_MCP41010=m
CONFIG_TPL0102=m
# end of Digital potentiometers

#
# Digital potentiostats
#
CONFIG_LMP91000=m
# end of Digital potentiostats

#
# Pressure sensors
#
CONFIG_ABP060MG=m
CONFIG_BMP280=m
CONFIG_BMP280_I2C=m
CONFIG_BMP280_SPI=m
CONFIG_DLHL60D=m
CONFIG_DPS310=m
CONFIG_HID_SENSOR_PRESS=m
CONFIG_HP03=m
CONFIG_ICP10100=m
CONFIG_MPL115=m
CONFIG_MPL115_I2C=m
CONFIG_MPL115_SPI=m
CONFIG_MPL3115=m
CONFIG_MS5611=m
CONFIG_MS5611_I2C=m
CONFIG_MS5611_SPI=m
CONFIG_MS5637=m
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_PRESS_I2C=m
CONFIG_IIO_ST_PRESS_SPI=m
CONFIG_T5403=m
CONFIG_HP206C=m
CONFIG_ZPA2326=m
CONFIG_ZPA2326_I2C=m
CONFIG_ZPA2326_SPI=m
# end of Pressure sensors

#
# Lightning sensors
#
CONFIG_AS3935=m
# end of Lightning sensors

#
# Proximity and distance sensors
#
CONFIG_ISL29501=m
CONFIG_LIDAR_LITE_V2=m
CONFIG_MB1232=m
CONFIG_PING=m
CONFIG_RFD77402=m
CONFIG_SRF04=m
CONFIG_SX_COMMON=m
CONFIG_SX9310=m
CONFIG_SX9324=m
CONFIG_SX9360=m
CONFIG_SX9500=m
CONFIG_SRF08=m
CONFIG_VCNL3020=m
CONFIG_VL53L0X_I2C=m
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
CONFIG_AD2S90=m
CONFIG_AD2S1200=m
# end of Resolver to digital converters

#
# Temperature sensors
#
CONFIG_LTC2983=m
CONFIG_MAXIM_THERMOCOUPLE=m
CONFIG_HID_SENSOR_TEMP=m
CONFIG_MLX90614=m
CONFIG_MLX90632=m
CONFIG_TMP006=m
CONFIG_TMP007=m
CONFIG_TMP117=m
CONFIG_TSYS01=m
CONFIG_TSYS02D=m
CONFIG_MAX31856=m
CONFIG_MAX31865=m
# end of Temperature sensors

# CONFIG_NTB is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_ATMEL_TCB is not set
CONFIG_PWM_CLK=y
CONFIG_PWM_DWC=y
# CONFIG_PWM_FSL_FTM is not set
# CONFIG_PWM_GPIO is not set
CONFIG_PWM_MESON=y
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_SUN4I=y
# CONFIG_PWM_XILINX is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_AL_FIC is not set
CONFIG_SUN6I_R_INTC=y
CONFIG_SUNXI_NMI_INTC=y
# CONFIG_XILINX_INTC is not set
CONFIG_PARTITION_PERCPU=y
CONFIG_MESON_IRQ_GPIO=y
# end of IRQ chip support

# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_MESON=y
CONFIG_RESET_MESON_AUDIO_ARB=y
CONFIG_RESET_SCMI=y
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SUNXI=y
# CONFIG_RESET_TI_SYSCON is not set
# CONFIG_RESET_TI_TPS380X is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_PHY_XGENE is not set
# CONFIG_PHY_CAN_TRANSCEIVER is not set
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_SUN6I_MIPI_DPHY=y
CONFIG_PHY_SUN9I_USB=y
CONFIG_PHY_SUN50I_USB3=y
CONFIG_PHY_MESON8B_USB2=y
CONFIG_PHY_MESON_GXL_USB2=y
CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=y
CONFIG_PHY_MESON_G12A_USB2=y
CONFIG_PHY_MESON_G12A_USB3_PCIE=y
CONFIG_PHY_MESON_AXG_PCIE=y
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
CONFIG_PHY_MESON_AXG_MIPI_DPHY=y

#
# PHY drivers for Broadcom platforms
#
# CONFIG_BCM_KONA_USB2_PHY is not set
# end of PHY drivers for Broadcom platforms

# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_DPHY_RX is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_LAN966X_SERDES is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
# CONFIG_PHY_QCOM_USB_HS is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
CONFIG_PHY_ROCKCHIP_DP=y
CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
CONFIG_PHY_ROCKCHIP_PCIE=y
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
CONFIG_PHY_ROCKCHIP_TYPEC=m
CONFIG_PHY_ROCKCHIP_USB=y
# CONFIG_PHY_SAMSUNG_USB2 is not set
# CONFIG_PHY_TUSB1210 is not set
# end of PHY Subsystem

# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCI400_PMU=y
CONFIG_ARM_CCI5xx_PMU=y
CONFIG_ARM_CCN=m
CONFIG_ARM_CMN=m
CONFIG_ARM_PMU=y
CONFIG_ARM_PMU_ACPI=y
CONFIG_ARM_SMMU_V3_PMU=y
CONFIG_ARM_DSU_PMU=m
CONFIG_ARM_SPE_PMU=m
# CONFIG_ARM_DMC620_PMU is not set
# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set
# CONFIG_HISI_PMU is not set
# CONFIG_HISI_PCIE_PMU is not set
# CONFIG_HNS3_PMU is not set
# end of Performance monitor support

CONFIG_RAS=y
# CONFIG_USB4 is not set

#
# Android
#
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_BINDERFS=y
CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
# end of Android

# CONFIG_LIBNVDIMM is not set
CONFIG_DAX=y
CONFIG_DEV_DAX=m
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_NVMEM_LAYOUTS=y

#
# Layout Types
#
CONFIG_NVMEM_LAYOUT_SL28_VPD=m
CONFIG_NVMEM_LAYOUT_ONIE_TLV=m
# end of Layout Types

CONFIG_NVMEM_MESON_EFUSE=y
CONFIG_NVMEM_MESON_MX_EFUSE=y
CONFIG_NVMEM_RMEM=y
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
CONFIG_NVMEM_ROCKCHIP_OTP=y
CONFIG_NVMEM_SPMI_SDAM=y
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_NVMEM_U_BOOT_ENV=y

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# CONFIG_HISI_PTT is not set
# end of HW tracing support

CONFIG_FPGA=m
CONFIG_ALTERA_PR_IP_CORE=m
CONFIG_ALTERA_PR_IP_CORE_PLAT=m
CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
CONFIG_FPGA_MGR_ALTERA_CVP=m
CONFIG_FPGA_MGR_XILINX_SPI=m
CONFIG_FPGA_MGR_ICE40_SPI=m
CONFIG_FPGA_MGR_MACHXO2_SPI=m
CONFIG_FPGA_BRIDGE=m
CONFIG_ALTERA_FREEZE_BRIDGE=m
CONFIG_XILINX_PR_DECOUPLER=m
CONFIG_FPGA_REGION=m
CONFIG_OF_FPGA_REGION=m
CONFIG_FPGA_DFL=m
CONFIG_FPGA_DFL_FME=m
CONFIG_FPGA_DFL_FME_MGR=m
CONFIG_FPGA_DFL_FME_BRIDGE=m
CONFIG_FPGA_DFL_FME_REGION=m
CONFIG_FPGA_DFL_AFU=m
CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m
CONFIG_FPGA_DFL_PCI=m
CONFIG_FPGA_MGR_MICROCHIP_SPI=m
# CONFIG_FSI is not set
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
# CONFIG_MUX_ADGS1408 is not set
CONFIG_MUX_GPIO=m
CONFIG_MUX_MMIO=m
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set
# CONFIG_INTERCONNECT is not set
CONFIG_COUNTER=m
CONFIG_INTERRUPT_CNT=m
# CONFIG_FTM_QUADDEC is not set
# CONFIG_MICROCHIP_TCB_CAPTURE is not set
# CONFIG_INTEL_QEP is not set
# CONFIG_MOST is not set
# CONFIG_PECI is not set
# CONFIG_HTE is not set
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_IOMAP=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=m
# CONFIG_REISERFS_CHECK is not set
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
# CONFIG_JFS_DEBUG is not set
# CONFIG_JFS_STATISTICS is not set
CONFIG_XFS_FS=y
CONFIG_XFS_SUPPORT_V4=y
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
# CONFIG_XFS_RT is not set
# CONFIG_XFS_ONLINE_SCRUB is not set
# CONFIG_XFS_WARN is not set
# CONFIG_XFS_DEBUG is not set
CONFIG_GFS2_FS=m
CONFIG_GFS2_FS_LOCKING_DLM=y
CONFIG_OCFS2_FS=m
CONFIG_OCFS2_FS_O2CB=m
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
CONFIG_OCFS2_FS_STATS=y
CONFIG_OCFS2_DEBUG_MASKLOG=y
# CONFIG_OCFS2_DEBUG_FS is not set
CONFIG_BTRFS_FS=y
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
# CONFIG_BTRFS_FS_REF_VERIFY is not set
CONFIG_NILFS2_FS=m
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
# CONFIG_F2FS_FAULT_INJECTION is not set
CONFIG_F2FS_FS_COMPRESSION=y
CONFIG_F2FS_FS_LZO=y
CONFIG_F2FS_FS_LZORLE=y
CONFIG_F2FS_FS_LZ4=y
CONFIG_F2FS_FS_LZ4HC=y
CONFIG_F2FS_FS_ZSTD=y
CONFIG_F2FS_IOSTAT=y
# CONFIG_F2FS_UNFAIR_RWSEM is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
# CONFIG_FS_ENCRYPTION_INLINE_CRYPT is not set
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
CONFIG_PRINT_QUOTA_WARNING=y
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=m
# CONFIG_QFMT_V1 is not set
# CONFIG_QFMT_V2 is not set
CONFIG_QUOTACTL=y
CONFIG_AUTOFS4_FS=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_VIRTIO_FS=m
CONFIG_OVERLAY_FS=y
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set

#
# Caches
#
CONFIG_NETFS_SUPPORT=y
# CONFIG_NETFS_STATS is not set
CONFIG_FSCACHE=y
# CONFIG_FSCACHE_STATS is not set
# CONFIG_FSCACHE_DEBUG is not set
CONFIG_CACHEFILES=m
# CONFIG_CACHEFILES_DEBUG is not set
# CONFIG_CACHEFILES_ERROR_INJECTION is not set
# CONFIG_CACHEFILES_ONDEMAND is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
# CONFIG_FAT_DEFAULT_UTF8 is not set
CONFIG_EXFAT_FS=y
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_NTFS_FS is not set
CONFIG_NTFS3_FS=m
# CONFIG_NTFS3_64BIT_CLUSTER is not set
CONFIG_NTFS3_LZX_XPRESS=y
CONFIG_NTFS3_FS_POSIX_ACL=y
# end of DOS/FAT/EXFAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_TMPFS_INODE64 is not set
CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_MEMFD_CREATE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=m
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
CONFIG_ECRYPT_FS=m
# CONFIG_ECRYPT_FS_MESSAGING is not set
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
CONFIG_UBIFS_FS=m
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
CONFIG_CRAMFS=m
CONFIG_CRAMFS_BLOCKDEV=y
# CONFIG_CRAMFS_MTD is not set
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_FILE_CACHE is not set
CONFIG_SQUASHFS_FILE_DIRECT=y
# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
# CONFIG_SQUASHFS_XATTR is not set
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_ZSTD=y
# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
CONFIG_PSTORE_DEFLATE_COMPRESS=y
CONFIG_PSTORE_LZO_COMPRESS=y
CONFIG_PSTORE_LZ4_COMPRESS=y
CONFIG_PSTORE_LZ4HC_COMPRESS=y
CONFIG_PSTORE_842_COMPRESS=y
CONFIG_PSTORE_ZSTD_COMPRESS=y
CONFIG_PSTORE_COMPRESS=y
CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set
CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
# CONFIG_PSTORE_CONSOLE is not set
# CONFIG_PSTORE_PMSG is not set
# CONFIG_PSTORE_RAM is not set
# CONFIG_PSTORE_BLK is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_EROFS_FS=m
# CONFIG_EROFS_FS_DEBUG is not set
CONFIG_EROFS_FS_XATTR=y
CONFIG_EROFS_FS_POSIX_ACL=y
# CONFIG_EROFS_FS_SECURITY is not set
CONFIG_EROFS_FS_ZIP=y
CONFIG_EROFS_FS_ZIP_LZMA=y
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V2=m
CONFIG_NFS_V3=m
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=m
# CONFIG_NFS_SWAP is not set
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=m
CONFIG_PNFS_BLOCK=m
CONFIG_PNFS_FLEXFILE_LAYOUT=m
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
# CONFIG_NFS_V4_1_MIGRATION is not set
CONFIG_NFS_V4_SECURITY_LABEL=y
CONFIG_NFS_FSCACHE=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DEBUG=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
# CONFIG_NFS_V4_2_READ_PLUS is not set
CONFIG_NFSD=m
# CONFIG_NFSD_V2 is not set
# CONFIG_NFSD_V3_ACL is not set
CONFIG_NFSD_V4=y
# CONFIG_NFSD_BLOCKLAYOUT is not set
# CONFIG_NFSD_SCSILAYOUT is not set
# CONFIG_NFSD_FLEXFILELAYOUT is not set
CONFIG_NFSD_V4_2_INTER_SSC=y
# CONFIG_NFSD_V4_SECURITY_LABEL is not set
CONFIG_GRACE_PERIOD=m
CONFIG_LOCKD=m
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=m
CONFIG_NFS_COMMON=y
CONFIG_NFS_V4_2_SSC_HELPER=y
CONFIG_SUNRPC=m
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_BACKCHANNEL=y
CONFIG_RPCSEC_GSS_KRB5=m
# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
CONFIG_SUNRPC_DEBUG=y
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
# CONFIG_CEPH_FS_SECURITY_LABEL is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CIFS_DEBUG=y
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
CONFIG_CIFS_DFS_UPCALL=y
# CONFIG_CIFS_SWN_UPCALL is not set
# CONFIG_CIFS_FSCACHE is not set
CONFIG_SMB_SERVER=m
CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
CONFIG_SMB_SERVER_KERBEROS5=y
CONFIG_SMBFS=m
CONFIG_CODA_FS=m
CONFIG_AFS_FS=m
# CONFIG_AFS_DEBUG is not set
CONFIG_AFS_FSCACHE=y
# CONFIG_AFS_DEBUG_CURSOR is not set
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
CONFIG_9P_FS_SECURITY=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf-8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=m
CONFIG_NLS_MAC_GAELIC=m
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=y
CONFIG_DLM=m
# CONFIG_DLM_DEPRECATED_API is not set
# CONFIG_DLM_DEBUG is not set
# CONFIG_UNICODE is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_BIG_KEYS is not set
# CONFIG_TRUSTED_KEYS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_PROC_MEM_ALWAYS_FORCE=y
# CONFIG_PROC_MEM_FORCE_PTRACE is not set
# CONFIG_PROC_MEM_NO_FORCE is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
# CONFIG_SECURITY_NETWORK_XFRM is not set
CONFIG_SECURITY_PATH=y
CONFIG_LSM_MMAP_MIN_ADDR=32768
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
# CONFIG_SECURITY_SELINUX_DISABLE is not set
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
CONFIG_SECURITY_APPARMOR=y
# CONFIG_SECURITY_APPARMOR_DEBUG is not set
CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y
CONFIG_SECURITY_APPARMOR_HASH=y
CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y
CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
# CONFIG_SECURITY_LANDLOCK is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
CONFIG_INTEGRITY_AUDIT=y
# CONFIG_IMA is not set
# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
# CONFIG_EVM is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
CONFIG_INIT_STACK_NONE=y
# CONFIG_INIT_STACK_ALL_PATTERN is not set
# CONFIG_INIT_STACK_ALL_ZERO is not set
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
# CONFIG_ZERO_CALL_USED_REGS is not set
# end of Memory initialization

CONFIG_RANDSTRUCT_NONE=y
# CONFIG_RANDSTRUCT_FULL is not set
# CONFIG_RANDSTRUCT_PERFORMANCE is not set
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=y
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=y
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_ENGINE=y
# end of Crypto core or helper

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=y
# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
# CONFIG_CRYPTO_ECDSA is not set
CONFIG_CRYPTO_ECRDSA=y
CONFIG_CRYPTO_SM2=y
CONFIG_CRYPTO_CURVE25519=y
# end of Public-key cryptography

#
# Block ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
CONFIG_CRYPTO_ANUBIS=y
# CONFIG_CRYPTO_ARIA is not set
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_BLOWFISH_COMMON=y
CONFIG_CRYPTO_CAMELLIA=y
CONFIG_CRYPTO_CAST_COMMON=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=y
CONFIG_CRYPTO_KHAZAD=y
CONFIG_CRYPTO_SEED=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_GENERIC=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y
# end of Block ciphers

#
# Length-preserving ciphers and modes
#
CONFIG_CRYPTO_ADIANTUM=y
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_HCTR2 is not set
CONFIG_CRYPTO_KEYWRAP=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_NHPOLY1305=y
# end of Length-preserving ciphers and modes

#
# AEAD (authenticated encryption with associated data) ciphers
#
CONFIG_CRYPTO_AEGIS128=y
CONFIG_CRYPTO_AEGIS128_SIMD=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_ESSIV=y
# end of AEAD (authenticated encryption with associated data) ciphers

#
# Hashes, digests, and MACs
#
CONFIG_CRYPTO_BLAKE2B=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_RMD160=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_SM3_GENERIC=y
CONFIG_CRYPTO_STREEBOG=y
CONFIG_CRYPTO_VMAC=y
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_XXHASH=y
# end of Hashes, digests, and MACs

#
# CRCs (cyclic redundancy checks)
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
# end of CRCs (cyclic redundancy checks)

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=y
CONFIG_CRYPTO_ZSTD=y
# end of Compression

#
# Random number generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
# end of Random number generation

#
# Userspace interface
#
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
CONFIG_CRYPTO_STATS=y
# end of Userspace interface

CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_NHPOLY1305_NEON=y
CONFIG_CRYPTO_CHACHA20_NEON=y

#
# Accelerated Cryptographic Algorithms for CPU (arm64)
#
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_POLY1305_NEON=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA512_ARM64_CE=y
CONFIG_CRYPTO_SHA3_ARM64=y
CONFIG_CRYPTO_SM3_NEON=y
CONFIG_CRYPTO_SM3_ARM64_CE=y
# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CRYPTO_SM4_ARM64_CE=y
CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
# end of Accelerated Cryptographic Algorithms for CPU (arm64)

CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_ALLWINNER=y
CONFIG_CRYPTO_DEV_SUN4I_SS=y
CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set
CONFIG_CRYPTO_DEV_SUN8I_CE=y
CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG=y
CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
CONFIG_CRYPTO_DEV_SUN8I_SS=y
CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG=y
CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_CCP is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set
# CONFIG_CRYPTO_DEV_QAT_C62X is not set
# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set
# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_ROCKCHIP=m
# CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG is not set
CONFIG_CRYPTO_DEV_ROCKCHIP2=m
# CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG is not set
CONFIG_CRYPTO_DEV_VIRTIO=m
CONFIG_CRYPTO_DEV_CRYPTODEV_LINUX=m
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
CONFIG_CRYPTO_DEV_CCREE=y
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
# CONFIG_CRYPTO_DEV_HISI_TRNG is not set
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG=y
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
CONFIG_PKCS7_MESSAGE_PARSER=y
CONFIG_PKCS7_TEST_KEY=m
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
# CONFIG_FIPS_SIGNATURE_SELFTEST is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_RAID6_PQ=y
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=m
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
CONFIG_INDIRECT_PIO=y
# CONFIG_TRACE_MMIO_ACCESS is not set

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=m
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
CONFIG_CRYPTO_LIB_CURVE25519=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines

CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC64_ROCKSOFT=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=y
CONFIG_CRC4=m
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=m
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
CONFIG_RANDOM32_SELFTEST=y
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
# CONFIG_XZ_DEC_SPARC is not set
CONFIG_XZ_DEC_MICROLZMA=y
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_INTERVAL_TREE=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_SWIOTLB=y
# CONFIG_DMA_RESTRICTED_POOL is not set
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y
# CONFIG_DMA_PERNUMA_CMA is not set

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=256
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_DMA_MAP_BENCHMARK is not set
CONFIG_SGL_ALLOC=y
# CONFIG_FORCE_NR_CPUS is not set
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_ARCH_STACKWALK=y
CONFIG_STACKDEPOT=y
CONFIG_SBITMAP=y
# end of Library routines

CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_CALLER is not set
# CONFIG_STACKTRACE_BUILD_ID is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Compile-time checks and compiler options
#
CONFIG_AS_HAS_NON_CONST_LEB128=y
CONFIG_DEBUG_INFO_NONE=y
# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_DEBUG_INFO_DWARF5 is not set
CONFIG_FRAME_WARN=2048
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_READABLE_ASM is not set
CONFIG_HEADERS_INSTALL=y
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_VMLINUX_MAP is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_ARCH_KCSAN=y
CONFIG_HAVE_KCSAN_COMPILER=y
# CONFIG_KCSAN is not set
# end of Generic Kernel Debugging Instruments

#
# Networking Debugging
#
# CONFIG_NET_DEV_REFCNT_TRACKER is not set
# CONFIG_NET_NS_REFCNT_TRACKER is not set
# CONFIG_DEBUG_NET is not set
# end of Networking Debugging

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_SLUB_DEBUG=y
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SHRINKER_DEBUG is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
# end of Memory Debugging

# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SOFTLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHED_INFO=y
# CONFIG_SCHEDSTATS is not set
# end of Scheduler Debugging

# CONFIG_DEBUG_TIMEKEEPING is not set

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

# CONFIG_DEBUG_IRQFLAGS is not set
CONFIG_STACKTRACE=y
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set

#
# Debug kernel data structures
#
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# CONFIG_DEBUG_MAPLE_TREE is not set
# end of Debug kernel data structures

# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
# CONFIG_RCU_SCALE_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_LATENCYTOP is not set
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_TRACING=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_BOOTTIME_TRACING is not set
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_HWLAT_TRACER is not set
# CONFIG_OSNOISE_TRACER is not set
# CONFIG_TIMERLAT_TRACER is not set
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
# CONFIG_FTRACE_SYSCALLS is not set
# CONFIG_TRACER_SNAPSHOT is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_KPROBE_EVENTS=y
CONFIG_UPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_DYNAMIC_EVENTS=y
CONFIG_PROBE_EVENTS=y
# CONFIG_SYNTH_EVENTS is not set
# CONFIG_HIST_TRIGGERS is not set
# CONFIG_TRACE_EVENT_INJECT is not set
# CONFIG_TRACEPOINT_BENCHMARK is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_TRACE_EVAL_MAP_FILE is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
# CONFIG_KPROBE_EVENT_GEN_TEST is not set
# CONFIG_RV is not set
# CONFIG_SAMPLES is not set
# CONFIG_STRICT_DEVMEM is not set

#
# arm64 Debugging
#
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
# end of arm64 Debugging

#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FUNCTION_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_LKDTM is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_DIV64 is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TEST_REF_TRACKER is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_ASYNC_RAID6_TEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_STRING_SELFTEST is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_STRSCPY is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_SCANF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_MAPLE_TREE is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_SIPHASH is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_VMALLOC is not set
# CONFIG_TEST_USER_COPY is not set
CONFIG_TEST_BPF=m
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_DYNAMIC_DEBUG is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_FREE_PAGES is not set
CONFIG_ARCH_USE_MEMTEST=y
CONFIG_MEMTEST=y
# end of Kernel Testing and Coverage

#
# Rust hacking
#
# end of Rust hacking
# end of Kernel hacking


================================================
FILE: kernel-config/release/stable/config-6.12
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 6.12.78 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 15.2.Rel1 (Build arm-15.86)) 15.2.1 20251203"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=150201
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=24501
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=24501
CONFIG_LLD_VERSION=0
CONFIG_RUSTC_VERSION=0
CONFIG_RUSTC_LLVM_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_TOOLS_SUPPORT_RELR=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_CC_HAS_COUNTED_BY=y
CONFIG_LD_CAN_USE_KEEP_IN_OVERLAY=y
CONFIG_PAHOLE_VERSION=130
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
# CONFIG_UAPI_HEADER_TEST is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
# CONFIG_WATCH_QUEUE is not set
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_USELIB is not set
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_SIM=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
CONFIG_GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD=y
# end of IRQ subsystem

CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_HZ_PERIODIC=y
# CONFIG_NO_HZ_IDLE is not set
# CONFIG_NO_HZ_FULL is not set
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y

#
# BPF subsystem
#
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_JIT=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
CONFIG_BPF_JIT_DEFAULT_ON=y
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
# CONFIG_BPF_PRELOAD is not set
# CONFIG_BPF_LSM is not set
# end of BPF subsystem

CONFIG_PREEMPT_BUILD=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
# CONFIG_PREEMPT_RT is not set
CONFIG_PREEMPT_COUNT=y
CONFIG_PREEMPTION=y
CONFIG_PREEMPT_DYNAMIC=y
CONFIG_SCHED_CLASS_EXT=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_SCHED_HW_PRESSURE=y
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
CONFIG_PREEMPT_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_NEED_TASKS_RCU=y
CONFIG_TASKS_RCU=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
# CONFIG_PRINTK_INDEX is not set
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
# CONFIG_UCLAMP_TASK is not set
# end of Scheduler features

CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
CONFIG_CC_HAS_INT128=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_GCC10_NO_ARRAY_BOUNDS=y
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_GCC_NO_STRINGOP_OVERFLOW=y
CONFIG_CC_NO_STRINGOP_OVERFLOW=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_SLAB_OBJ_EXT=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
CONFIG_MEMCG=y
CONFIG_MEMCG_V1=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_GROUP_SCHED_WEIGHT=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_EXT_GROUP_SCHED=y
CONFIG_SCHED_MM_CID=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CPUSETS=y
CONFIG_CPUSETS_V1=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
CONFIG_CGROUP_MISC=y
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
# CONFIG_CHECKPOINT_RESTORE is not set
CONFIG_SCHED_AUTOGROUP=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
# CONFIG_BOOT_CONFIG_FORCE is not set
# CONFIG_BOOT_CONFIG_EMBED is not set
CONFIG_INITRAMFS_PRESERVE_MTIME=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
# CONFIG_BASE_SMALL is not set
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
CONFIG_CACHESTAT_SYSCALL=y
# CONFIG_PC104 is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_SELFTEST is not set
# CONFIG_KALLSYMS_ALL is not set
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_GUEST_PERF_EVENTS=y

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y

#
# Kexec and crash features
#
# CONFIG_KEXEC_FILE is not set
# end of Kexec and crash features
# end of General setup

CONFIG_ARM64=y
CONFIG_RUSTC_SUPPORTS_ARM64=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_CONT_PTE_SHIFT=4
CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y

#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
# CONFIG_ARCH_AIROHA is not set
CONFIG_ARCH_SUNXI=y
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_APPLE is not set
# CONFIG_ARCH_BCM is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SPARX5 is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_KEEMBAY is not set
# CONFIG_ARCH_MEDIATEK is not set
CONFIG_ARCH_MESON=y
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_NXP is not set
# CONFIG_ARCH_MA35 is not set
# CONFIG_ARCH_NPCM is not set
# CONFIG_ARCH_PENSANDO is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_RENESAS is not set
CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_INTEL_SOCFPGA is not set
# CONFIG_ARCH_STM32 is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZYNQMP is not set
# end of Platform selection

#
# Kernel Features
#

#
# ARM errata workarounds via the alternatives framework
#
CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_834220=y
CONFIG_ARM64_ERRATUM_1742098=y
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1319367=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_ERRATUM_2441007=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_ARM64_ERRATUM_2051678=y
CONFIG_ARM64_ERRATUM_2077057=y
CONFIG_ARM64_ERRATUM_2658417=y
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
CONFIG_ARM64_ERRATUM_2054223=y
CONFIG_ARM64_ERRATUM_2067961=y
CONFIG_ARM64_ERRATUM_2441009=y
CONFIG_ARM64_ERRATUM_2457168=y
CONFIG_ARM64_ERRATUM_2645198=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y
CONFIG_ARM64_ERRATUM_2966298=y
CONFIG_ARM64_ERRATUM_3117295=y
CONFIG_ARM64_ERRATUM_3194386=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_HISILICON_ERRATUM_162100801=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
CONFIG_QCOM_FALKOR_ERRATUM_1009=y
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
CONFIG_ROCKCHIP_ERRATUM_3568002=y
CONFIG_ROCKCHIP_ERRATUM_3588001=y
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
# end of ARM errata workarounds via the alternatives framework

CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
# CONFIG_ARM64_VA_BITS_39 is not set
CONFIG_ARM64_VA_BITS_48=y
# CONFIG_ARM64_VA_BITS_52 is not set
CONFIG_ARM64_VA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SCHED_MC=y
CONFIG_SCHED_CLUSTER=y
# CONFIG_SCHED_SMT is not set
CONFIG_NR_CPUS=8
# CONFIG_HOTPLUG_CPU is not set
# CONFIG_NUMA is not set
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
CONFIG_HZ_300=y
# CONFIG_HZ_1000 is not set
CONFIG_HZ=300
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_PARAVIRT=y
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y
CONFIG_ARCH_SUPPORTS_KEXEC_SIG=y
CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG=y
CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y
CONFIG_ARCH_DEFAULT_CRASH_DUMP=y
# CONFIG_XEN is not set
CONFIG_ARCH_FORCE_MAX_ORDER=10
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y
CONFIG_COMPAT_ALIGNMENT_FIXUPS=y
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y

#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
CONFIG_AS_HAS_LSE_ATOMICS=y
CONFIG_ARM64_LSE_ATOMICS=y
CONFIG_ARM64_USE_LSE_ATOMICS=y
# end of ARMv8.1 architectural features

#
# ARMv8.2 architectural features
#
CONFIG_AS_HAS_ARMV8_2=y
CONFIG_AS_HAS_SHA3=y
CONFIG_ARM64_PMEM=y
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features

#
# ARMv8.3 architectural features
#
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
CONFIG_AS_HAS_ARMV8_3=y
CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
CONFIG_AS_HAS_LDAPR=y
# end of ARMv8.3 architectural features

#
# ARMv8.4 architectural features
#
CONFIG_ARM64_AMU_EXTN=y
CONFIG_AS_HAS_ARMV8_4=y
CONFIG_ARM64_TLB_RANGE=y
# end of ARMv8.4 architectural features

#
# ARMv8.5 architectural features
#
CONFIG_AS_HAS_ARMV8_5=y
CONFIG_ARM64_BTI=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARM64_AS_HAS_MTE=y
CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features

#
# ARMv8.7 architectural features
#
CONFIG_ARM64_EPAN=y
# end of ARMv8.7 architectural features

#
# ARMv8.9 architectural features
#
CONFIG_ARM64_POE=y
CONFIG_ARCH_PKEY_BITS=3
# end of ARMv8.9 architectural features

CONFIG_ARM64_SVE=y
CONFIG_ARM64_PSEUDO_NMI=y
# CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
CONFIG_ARM64_CONTPTE=y
# end of Kernel Features

#
# Boot options
#
CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
CONFIG_CMDLINE=""
CONFIG_EFI_STUB=y
CONFIG_EFI=y
CONFIG_COMPRESSED_INSTALL=y
CONFIG_DMI=y
# end of Boot options

#
# Power management options
#
# CONFIG_SUSPEND is not set
# CONFIG_HIBERNATION is not set
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options

#
# CPU Power Management
#

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_IDLE_GOV_LADDER=y
# CONFIG_CPU_IDLE_GOV_MENU is not set
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_DT_IDLE_STATES=y
CONFIG_DT_IDLE_GENPD=y

#
# ARM CPU Idle Drivers
#
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
# end of ARM CPU Idle Drivers
# end of CPU Idle

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_SCMI_CPUFREQ=y
# CONFIG_ACPI_CPPC_CPUFREQ is not set
# end of CPU Frequency scaling
# end of CPU Power Management

CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_GENERIC_GSI=y
CONFIG_ACPI_CCA_REQUIRED=y
CONFIG_ACPI_THERMAL_LIB=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
# CONFIG_ACPI_FPDT is not set
CONFIG_ACPI_EC_DEBUGFS=m
CONFIG_ACPI_AC=m
CONFIG_ACPI_BATTERY=m
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_VIDEO=m
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_MCFG=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_THERMAL=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_PCI_SLOT=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_BGRT=y
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
# CONFIG_ACPI_NFIT is not set
CONFIG_HAVE_ACPI_APEI=y
CONFIG_ACPI_APEI=y
CONFIG_ACPI_APEI_GHES=y
CONFIG_ACPI_APEI_SEA=y
CONFIG_ACPI_APEI_MEMORY_FAILURE=y
CONFIG_ACPI_APEI_EINJ=m
CONFIG_ACPI_APEI_ERST_DEBUG=m
CONFIG_ACPI_CONFIGFS=m
CONFIG_ACPI_PFRUT=m
CONFIG_ACPI_IORT=y
CONFIG_ACPI_GTDT=y
# CONFIG_ACPI_AGDI is not set
CONFIG_ACPI_APMT=y
CONFIG_ACPI_PPTT=y
CONFIG_ACPI_PCC=y
# CONFIG_ACPI_FFH is not set
CONFIG_PMIC_OPREGION=y
CONFIG_ACPI_VIOT=y
CONFIG_ACPI_PRMT=y
CONFIG_KVM_COMMON=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_DIRTY_RING=y
CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y
CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP=y
CONFIG_KVM_MMIO=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_READONLY_MEM=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_KVM_XFER_TO_GUEST_WORK=y
CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y
CONFIG_KVM_GENERIC_MMU_NOTIFIER=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
# CONFIG_NVHE_EL2_DEBUG is not set
# CONFIG_PTDUMP_STAGE2_DEBUGFS is not set
CONFIG_CPU_MITIGATIONS=y

#
# General architecture-dependent options
#
CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
CONFIG_UPROBES=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_RUST=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_EVENTS_NMI=y
CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
# CONFIG_SECCOMP_CACHE_DEBUG is not set
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
# CONFIG_SHADOW_CALL_STACK is not set
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
CONFIG_HAVE_CONTEXT_TRACKING_USER=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_ARCH_HUGE_VMALLOC=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_WANT_PMD_MKWRITE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_ARCH_WANTS_EXECMEM_LATE=y
CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_HAVE_PAGE_SIZE_4KB=y
CONFIG_PAGE_SIZE_4KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SHIFT=12
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_ARCH_SUPPORTS_RT=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET=y
# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
CONFIG_RELR=y
CONFIG_ARCH_HAS_MEM_ENCRYPT=y
CONFIG_HAVE_PREEMPT_DYNAMIC=y
CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y
CONFIG_ARCH_HAS_HW_PTE_YOUNG=y
CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FUNCTION_ALIGNMENT=4
CONFIG_CC_HAS_MIN_FUNCTION_ALIGNMENT=y
CONFIG_CC_HAS_SANE_FUNCTION_ALIGNMENT=y
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_MODULES=y
# CONFIG_MODULE_DEBUG is not set
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BLK_RQ_ALLOC_TIME=y
CONFIG_BLK_CGROUP_RWSTAT=y
CONFIG_BLK_CGROUP_PUNT_BIO=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_ICQ=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_WRITE_MOUNTED=y
# CONFIG_BLK_DEV_ZONED is not set
CONFIG_BLK_DEV_THROTTLING=y
CONFIG_BLK_WBT=y
CONFIG_BLK_WBT_MQ=y
CONFIG_BLK_CGROUP_IOLATENCY=y
CONFIG_BLK_CGROUP_IOCOST=y
CONFIG_BLK_CGROUP_IOPRIO=y
# CONFIG_BLK_DEBUG_FS is not set
CONFIG_BLK_SED_OPAL=y
CONFIG_BLK_INLINE_ENCRYPTION=y
CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_AIX_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
# CONFIG_CMDLINE_PARTITION is not set
# CONFIG_OF_PARTITION is not set
# end of Partition Types

CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_HOLDER_DEPRECATED=y
CONFIG_BLK_MQ_STACKING=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
# CONFIG_BFQ_CGROUP_DEBUG is not set
# end of IO Schedulers

CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_HAVE_ELF_PROT=y
CONFIG_ARCH_USE_GNU_PROPERTY=y
CONFIG_ELFCORE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=m
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_ZPOOL=y
CONFIG_SWAP=y
CONFIG_ZSWAP=y
CONFIG_ZSWAP_DEFAULT_ON=y
# CONFIG_ZSWAP_SHRINKER_DEFAULT_ON is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD_DEPRECATED is not set
# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
CONFIG_ZBUD=y
# CONFIG_Z3FOLD_DEPRECATED is not set
CONFIG_ZSMALLOC=y
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_ZSMALLOC_CHAIN_SIZE=8

#
# Slab allocator options
#
CONFIG_SLUB=y
# CONFIG_SLUB_TINY is not set
CONFIG_SLAB_MERGE_DEFAULT=y
CONFIG_SLAB_FREELIST_RANDOM=y
CONFIG_SLAB_FREELIST_HARDENED=y
CONFIG_SLAB_BUCKETS=y
# CONFIG_SLUB_STATS is not set
CONFIG_SLUB_CPU_PARTIAL=y
# CONFIG_RANDOM_KMALLOC_CACHES is not set
# end of Slab allocator options

CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_GUP_FAST=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_SPLIT_PTE_PTLOCKS=y
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_SPLIT_PMD_PTLOCKS=y
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
CONFIG_ARCH_ENABLE_THP_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PCP_BATCH_SCALE_MAX=5
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_MMU_NOTIFIER=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
CONFIG_MEMORY_FAILURE=y
# CONFIG_HWPOISON_INJECT is not set
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_TRANSPARENT_HUGEPAGE=y
# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set
CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
# CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set
CONFIG_THP_SWAP=y
# CONFIG_READ_ONLY_THP_FOR_FS is not set
CONFIG_PGTABLE_HAS_HUGE_LEAVES=y
CONFIG_ARCH_SUPPORTS_HUGE_PFNMAP=y
CONFIG_ARCH_SUPPORTS_PMD_PFNMAP=y
CONFIG_CMA=y
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_CMA_AREAS=7
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
CONFIG_PAGE_IDLE_FLAG=y
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_ARCH_HAS_ZONE_DMA_SET=y
CONFIG_ZONE_DMA=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
CONFIG_ARCH_HAS_PKEYS=y
CONFIG_ARCH_USES_PG_ARCH_2=y
CONFIG_ARCH_USES_PG_ARCH_3=y
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_TEST is not set
# CONFIG_DMAPOOL_TEST is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_MEMFD_CREATE=y
CONFIG_SECRETMEM=y
# CONFIG_ANON_VMA_NAME is not set
# CONFIG_USERFAULTFD is not set
CONFIG_LRU_GEN=y
CONFIG_LRU_GEN_ENABLED=y
# CONFIG_LRU_GEN_STATS is not set
CONFIG_LRU_GEN_WALKS_MMU=y
CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y
CONFIG_PER_VMA_LOCK=y
CONFIG_LOCK_MM_AND_FIND_VMA=y
CONFIG_IOMMU_MM_DATA=y
CONFIG_EXECMEM=y

#
# Data Access Monitoring
#
CONFIG_DAMON=y
CONFIG_DAMON_VADDR=y
CONFIG_DAMON_PADDR=y
CONFIG_DAMON_SYSFS=y
# CONFIG_DAMON_DBGFS_DEPRECATED is not set
CONFIG_DAMON_RECLAIM=y
CONFIG_DAMON_LRU_SORT=y
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_XGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_DECRYPTED=y
CONFIG_SKB_EXTENSIONS=y
CONFIG_NET_DEVMEM=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_AF_UNIX_OOB=y
CONFIG_UNIX_DIAG=y
CONFIG_TLS=m
CONFIG_TLS_DEVICE=y
CONFIG_TLS_TOE=y
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
CONFIG_XFRM_INTERFACE=m
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_AH=y
CONFIG_XFRM_ESP=y
CONFIG_XFRM_IPCOMP=y
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_XFRM_ESPINTCP=y
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=y
CONFIG_NET_HANDSHAKE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
# CONFIG_IP_FIB_TRIE_STATS is not set
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_ROUTE_CLASSID=y
# CONFIG_IP_PNP is not set
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=y
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=y
CONFIG_NET_FOU=y
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
CONFIG_INET_ESP_OFFLOAD=m
# CONFIG_INET_ESPINTCP is not set
CONFIG_INET_IPCOMP=y
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=y
CONFIG_INET_TUNNEL=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
CONFIG_INET_UDP_DIAG=y
CONFIG_INET_RAW_DIAG=y
# CONFIG_INET_DIAG_DESTROY is not set
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_NV=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_CONG_DCTCP=m
CONFIG_TCP_CONG_CDG=m
CONFIG_TCP_CONG_BBR=m
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_AO is not set
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_ESP_OFFLOAD=m
CONFIG_INET6_ESPINTCP=y
CONFIG_INET6_IPCOMP=y
CONFIG_IPV6_MIP6=m
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=y
CONFIG_INET6_TUNNEL=y
CONFIG_IPV6_VTI=m
CONFIG_IPV6_SIT=y
CONFIG_IPV6_SIT_6RD=y
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=y
CONFIG_IPV6_GRE=m
CONFIG_IPV6_FOU=y
CONFIG_IPV6_FOU_TUNNEL=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
CONFIG_IPV6_SEG6_LWTUNNEL=y
CONFIG_IPV6_SEG6_HMAC=y
CONFIG_IPV6_SEG6_BPF=y
CONFIG_IPV6_RPL_LWTUNNEL=y
CONFIG_IPV6_IOAM6_LWTUNNEL=y
# CONFIG_NETLABEL is not set
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=y
CONFIG_MPTCP_IPV6=y
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_EGRESS=y
CONFIG_NETFILTER_SKIP_EGRESS=y
CONFIG_NETFILTER_NETLINK=m
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
CONFIG_NETFILTER_BPF_LINK=y
# CONFIG_NETFILTER_NETLINK_HOOK is not set
CONFIG_NETFILTER_NETLINK_ACCT=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NETFILTER_NETLINK_OSF=m
CONFIG_NF_CONNTRACK=y
CONFIG_NF_LOG_SYSLOG=m
CONFIG_NETFILTER_CONNCOUNT=m
CONFIG_NF_CONNTRACK_MARK=y
# CONFIG_NF_CONNTRACK_SECMARK is not set
CONFIG_NF_CONNTRACK_ZONES=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y
CONFIG_NF_CONNTRACK_TIMEOUT=y
CONFIG_NF_CONNTRACK_TIMESTAMP=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CONNTRACK_OVS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_CT_NETLINK_TIMEOUT=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=m
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NF_NAT_OVS=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=m
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_FULLCONE=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
CONFIG_NFT_OSF=m
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NF_DUP_NETDEV=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NFT_REJECT_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
# CONFIG_NF_FLOW_TABLE_PROCFS is not set
CONFIG_NETFILTER_XTABLES=m
# CONFIG_NETFILTER_XTABLES_COMPAT is not set

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=m
CONFIG_NETFILTER_XT_CONNMARK=m
CONFIG_NETFILTER_XT_SET=m

#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_AUDIT=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LED=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=m
CONFIG_NETFILTER_XT_TARGET_NETMAP=m
CONFIG_NETFILTER_XT_TARGET_FULLCONENAT=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD=m
CONFIG_NETFILTER_XT_TARGET_RATEEST=m
CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
CONFIG_NETFILTER_XT_TARGET_SECMARK=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=m
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# end of Core Netfilter Configuration

CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
# CONFIG_IP_VS_DEBUG is not set
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m
# CONFIG_IP_VS_TWOS is not set

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_IP_NF_IPTABLES_LEGACY=m
CONFIG_NF_SOCKET_IPV4=m
CONFIG_NF_TPROXY_IPV4=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=m
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_SECURITY=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_NFT_COMPAT_ARP=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_IP6_NF_IPTABLES_LEGACY=m
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP6_NF_SECURITY=m
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=y
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_NFT_BRIDGE_META=m
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES_LEGACY=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m

#
# DCCP CCIDs Configuration
#
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
CONFIG_IP_DCCP_CCID3=y
# CONFIG_IP_DCCP_CCID3_DEBUG is not set
CONFIG_IP_DCCP_TFRC_LIB=y
# end of DCCP CCIDs Configuration

#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
# end of DCCP Kernel Hacking

CONFIG_IP_SCTP=m
CONFIG_SCTP_DBG_OBJCNT=y
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=m
CONFIG_RDS=m
CONFIG_RDS_TCP=m
# CONFIG_RDS_DEBUG is not set
CONFIG_TIPC=m
CONFIG_TIPC_MEDIA_UDP=y
CONFIG_TIPC_CRYPTO=y
CONFIG_TIPC_DIAG=m
# CONFIG_ATM is not set
CONFIG_L2TP=m
CONFIG_L2TP_DEBUGFS=m
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=m
CONFIG_L2TP_ETH=m
CONFIG_STP=y
CONFIG_GARP=m
CONFIG_MRP=m
CONFIG_BRIDGE=y
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_BRIDGE_MRP=y
CONFIG_BRIDGE_CFM=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_TAG_NONE=m
CONFIG_NET_DSA_TAG_AR9331=m
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
CONFIG_NET_DSA_TAG_BRCM=m
CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
CONFIG_NET_DSA_TAG_HELLCREEK=m
CONFIG_NET_DSA_TAG_GSWIP=m
CONFIG_NET_DSA_TAG_DSA_COMMON=m
CONFIG_NET_DSA_TAG_DSA=m
CONFIG_NET_DSA_TAG_EDSA=m
CONFIG_NET_DSA_TAG_MTK=m
CONFIG_NET_DSA_TAG_KSZ=m
CONFIG_NET_DSA_TAG_OCELOT=m
CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
CONFIG_NET_DSA_TAG_QCA=m
CONFIG_NET_DSA_TAG_RTL4_A=m
CONFIG_NET_DSA_TAG_RTL8_4=m
CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
CONFIG_NET_DSA_TAG_LAN9303=m
CONFIG_NET_DSA_TAG_SJA1105=m
CONFIG_NET_DSA_TAG_TRAILER=m
CONFIG_NET_DSA_TAG_VSC73XX_8021Q=m
CONFIG_NET_DSA_TAG_XRS700X=m
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q_MVRP=y
CONFIG_LLC=y
CONFIG_LLC2=y
CONFIG_ATALK=m
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
CONFIG_6LOWPAN=m
# CONFIG_6LOWPAN_DEBUGFS is not set
CONFIG_6LOWPAN_NHC=m
CONFIG_6LOWPAN_NHC_DEST=m
CONFIG_6LOWPAN_NHC_FRAGMENT=m
CONFIG_6LOWPAN_NHC_HOP=m
CONFIG_6LOWPAN_NHC_IPV6=m
CONFIG_6LOWPAN_NHC_MOBILITY=m
CONFIG_6LOWPAN_NHC_ROUTING=m
CONFIG_6LOWPAN_NHC_UDP=m
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
CONFIG_6LOWPAN_GHC_UDP=m
CONFIG_6LOWPAN_GHC_ICMPV6=m
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
CONFIG_IEEE802154=m
CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_MAC802154=m
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFB=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_MQPRIO_LIB=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_SKBPRIO=m
CONFIG_NET_SCH_CHOKE=m
CONFIG_NET_SCH_QFQ=m
CONFIG_NET_SCH_CODEL=m
CONFIG_NET_SCH_FQ_CODEL=y
CONFIG_NET_SCH_CAKE=y
CONFIG_NET_SCH_FQ=m
CONFIG_NET_SCH_HHF=m
CONFIG_NET_SCH_PIE=m
CONFIG_NET_SCH_FQ_PIE=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_SCH_PLUG=m
CONFIG_NET_SCH_ETS=m
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_PERF=y
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=y
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
# CONFIG_NET_EMATCH_CANID is not set
CONFIG_NET_EMATCH_IPSET=m
CONFIG_NET_EMATCH_IPT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_SAMPLE=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
CONFIG_NET_ACT_MPLS=m
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_NET_ACT_CONNMARK=m
CONFIG_NET_ACT_CTINFO=m
CONFIG_NET_ACT_SKBMOD=m
CONFIG_NET_ACT_IFE=m
CONFIG_NET_ACT_TUNNEL_KEY=m
CONFIG_NET_ACT_CT=m
CONFIG_NET_ACT_GATE=m
CONFIG_NET_IFE_SKBMARK=m
CONFIG_NET_IFE_SKBPRIO=m
CONFIG_NET_IFE_SKBTCINDEX=m
# CONFIG_NET_TC_SKB_EXT is not set
CONFIG_NET_SCH_FIFO=y
CONFIG_DCB=y
CONFIG_DNS_RESOLVER=m
CONFIG_BATMAN_ADV=m
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
CONFIG_BATMAN_ADV_NC=y
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUG is not set
# CONFIG_BATMAN_ADV_TRACING is not set
CONFIG_OPENVSWITCH=m
CONFIG_OPENVSWITCH_GRE=m
CONFIG_OPENVSWITCH_VXLAN=m
CONFIG_OPENVSWITCH_GENEVE=m
CONFIG_VSOCKETS=m
CONFIG_VSOCKETS_DIAG=m
CONFIG_VSOCKETS_LOOPBACK=m
CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO_VSOCKETS_COMMON=m
CONFIG_NETLINK_DIAG=y
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=m
CONFIG_MPLS_ROUTING=m
CONFIG_MPLS_IPTUNNEL=m
CONFIG_NET_NSH=m
# CONFIG_HSR is not set
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=m
# CONFIG_QRTR_SMD is not set
# CONFIG_QRTR_TUN is not set
CONFIG_QRTR_MHI=m
# CONFIG_NET_NCSI is not set
CONFIG_PCPU_DEV_REFCNT=y
CONFIG_MAX_SKB_FRAGS=17
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_XPS=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
CONFIG_NET_PKTGEN=m
# CONFIG_NET_DROP_MONITOR is not set
# end of Network testing
# end of Networking options

# CONFIG_HAMRADIO is not set
CONFIG_CAN=m
CONFIG_CAN_RAW=m
CONFIG_CAN_BCM=m
CONFIG_CAN_GW=m
CONFIG_CAN_J1939=m
CONFIG_CAN_ISOTP=m
CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=m
CONFIG_BT_LE=y
CONFIG_BT_LE_L2CAP_ECRED=y
CONFIG_BT_6LOWPAN=m
CONFIG_BT_LEDS=y
CONFIG_BT_MSFTEXT=y
# CONFIG_BT_AOSPEXT is not set
# CONFIG_BT_DEBUGFS is not set
CONFIG_BT_SELFTEST=y
CONFIG_BT_SELFTEST_ECDH=y
CONFIG_BT_SELFTEST_SMP=y

#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=m
CONFIG_BT_BCM=m
CONFIG_BT_RTL=m
CONFIG_BT_QCA=m
CONFIG_BT_MTK=m
CONFIG_BT_HCIBTUSB=m
# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
CONFIG_BT_HCIBTUSB_POLL_SYNC=y
# CONFIG_BT_HCIBTUSB_AUTO_ISOC_ALT is not set
CONFIG_BT_HCIBTUSB_BCM=y
CONFIG_BT_HCIBTUSB_MTK=y
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_NOKIA=m
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_BCM=y
CONFIG_BT_HCIUART_RTL=y
CONFIG_BT_HCIUART_QCA=y
CONFIG_BT_HCIUART_AG6XX=y
CONFIG_BT_HCIUART_MRVL=y
# CONFIG_BT_HCIUART_AML is not set
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBCM4377=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
CONFIG_BT_MTKSDIO=m
CONFIG_BT_MTKUART=m
CONFIG_BT_HCIRSI=m
CONFIG_BT_VIRTIO=m
CONFIG_BT_NXPUART=m
# CONFIG_BT_INTEL_PCIE is not set
# end of Bluetooth device drivers

CONFIG_AF_RXRPC=m
# CONFIG_AF_RXRPC_IPV6 is not set
# CONFIG_AF_RXRPC_INJECT_LOSS is not set
# CONFIG_AF_RXRPC_INJECT_RX_DELAY is not set
# CONFIG_AF_RXRPC_DEBUG is not set
# CONFIG_RXKAD is not set
# CONFIG_RXPERF is not set
CONFIG_AF_KCM=m
CONFIG_STREAM_PARSER=y
# CONFIG_MCTP is not set
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_SPY=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
CONFIG_CFG80211_CERTIFICATION_ONUS=y
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_EXTRA_REGDB_KEYDIR=""
CONFIG_CFG80211_REG_CELLULAR_HINTS=y
CONFIG_CFG80211_REG_RELAX_NO_IR=y
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_CFG80211_WEXT_EXPORT=y
CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
CONFIG_LIB80211_CRYPT_TKIP=m
CONFIG_LIB80211_DEBUG=y
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
# CONFIG_MAC80211_MESSAGE_TRACING is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_RFKILL=m
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=m
CONFIG_NET_9P=m
CONFIG_NET_9P_FD=m
CONFIG_NET_9P_VIRTIO=m
# CONFIG_NET_9P_USBG is not set
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
CONFIG_CEPH_LIB=m
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
# CONFIG_NFC is not set
CONFIG_PSAMPLE=m
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_SOCK_VALIDATE_XMIT=y
CONFIG_NET_IEEE8021Q_HELPERS=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
# CONFIG_PAGE_POOL_STATS is not set
CONFIG_FAILOVER=y
CONFIG_SHORTCUT_FE=y
CONFIG_ETHTOOL_NETLINK=y

#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIEAER is not set
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
# CONFIG_PCIEASPM_PERFORMANCE is not set
CONFIG_PCIE_PME=y
CONFIG_PCIE_PTM=y
CONFIG_PCI_MSI=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_STUB is not set
# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set
CONFIG_PCI_ECAM=y
# CONFIG_PCI_IOV is not set
# CONFIG_PCI_NPEM is not set
# CONFIG_PCI_PRI is not set
# CONFIG_PCI_PASID is not set
CONFIG_PCI_LABEL=y
# CONFIG_PCI_DYNAMIC_OF_NODES is not set
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
# CONFIG_HOTPLUG_PCI is not set

#
# PCI controller drivers
#
# CONFIG_PCIE_ALTERA is not set
# CONFIG_PCI_HOST_THUNDER_PEM is not set
# CONFIG_PCI_HOST_THUNDER_ECAM is not set
# CONFIG_PCI_FTPCI100 is not set
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
# CONFIG_PCIE_HISI_ERR is not set
CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_HOST=y
CONFIG_PCIE_ROCKCHIP_EP=y
# CONFIG_PCI_XGENE is not set
# CONFIG_PCIE_XILINX is not set

#
# Cadence-based PCIe controllers
#
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCIE_CADENCE_PLAT_EP is not set
# end of Cadence-based PCIe controllers

#
# DesignWare-based PCIe controllers
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_EP=y
# CONFIG_PCIE_AL is not set
CONFIG_PCI_MESON=y
# CONFIG_PCI_HISI is not set
# CONFIG_PCIE_KIRIN is not set
CONFIG_PCIE_DW_PLAT=y
CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCIE_DW_PLAT_EP=y
CONFIG_PCIE_ROCKCHIP_DW=y
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
CONFIG_PCIE_ROCKCHIP_DW_EP=y
# end of DesignWare-based PCIe controllers

#
# Mobiveil-based PCIe controllers
#
# end of Mobiveil-based PCIe controllers

#
# PLDA-based PCIe controllers
#
# CONFIG_PCIE_MICROCHIP_HOST is not set
# end of PLDA-based PCIe controllers
# end of PCI controller drivers

#
# PCI Endpoint
#
CONFIG_PCI_ENDPOINT=y
# CONFIG_PCI_ENDPOINT_CONFIGFS is not set
# CONFIG_PCI_EPF_TEST is not set
CONFIG_PCI_EPF_NTB=m
CONFIG_PCI_EPF_MHI=m
# end of PCI Endpoint

#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set
# end of PCI switch controller drivers

# CONFIG_CXL_BUS is not set
# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
CONFIG_AUXILIARY_BUS=y
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_DEVTMPFS_SAFE is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_DEBUG=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
CONFIG_FW_LOADER_COMPRESS=y
CONFIG_FW_LOADER_COMPRESS_XZ=y
CONFIG_FW_LOADER_COMPRESS_ZSTD=y
# CONFIG_FW_UPLOAD is not set
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_DEVICES=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_SPMI=m
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SCCB=m
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
# CONFIG_MOXTET is not set
CONFIG_SUN50I_DE2_BUS=y
CONFIG_SUNXI_RSB=y
CONFIG_VEXPRESS_CONFIG=y
CONFIG_MHI_BUS=m
# CONFIG_MHI_BUS_DEBUG is not set
CONFIG_MHI_BUS_PCI_GENERIC=m
CONFIG_MHI_BUS_EP=m
# end of Bus devices

#
# Cache Drivers
#
# end of Cache Drivers

CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y

#
# Firmware Drivers
#

#
# ARM System Control and Management Interface Protocol
#
CONFIG_ARM_SCMI_PROTOCOL=y
# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
# CONFIG_ARM_SCMI_DEBUG_COUNTERS is not set

#
# SCMI Transport Drivers
#
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
CONFIG_ARM_SCMI_HAVE_SHMEM=y
CONFIG_ARM_SCMI_HAVE_MSG=y
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y
CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y
CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y
# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE is not set
# end of SCMI Transport Drivers

#
# ARM SCMI NXP i.MX Vendor Protocols
#
# CONFIG_IMX_SCMI_BBM_EXT is not set
# end of ARM SCMI NXP i.MX Vendor Protocols

CONFIG_ARM_SCMI_POWER_CONTROL=y
# end of ARM System Control and Management Interface Protocol

CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SDE_INTERFACE=y
# CONFIG_FIRMWARE_MEMMAP is not set
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=y
# CONFIG_ISCSI_IBFT is not set
CONFIG_FW_CFG_SYSFS=y
CONFIG_FW_CFG_SYSFS_CMDLINE=y
CONFIG_SYSFB=y
# CONFIG_SYSFB_SIMPLEFB is not set
CONFIG_ARM_FFA_TRANSPORT=y
CONFIG_ARM_FFA_SMCCC=y
CONFIG_FW_CS_DSP=m
# CONFIG_GOOGLE_FIRMWARE is not set

#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_VARS_PSTORE=y
# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_GENERIC_STUB=y
# CONFIG_EFI_ZBOOT is not set
CONFIG_EFI_ARMSTUB_DTB_LOADER=y
CONFIG_EFI_BOOTLOADER_CONTROL=m
CONFIG_EFI_CAPSULE_LOADER=m
CONFIG_EFI_TEST=m
# CONFIG_RESET_ATTACK_MITIGATION is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
# CONFIG_EFI_DISABLE_RUNTIME is not set
# CONFIG_EFI_COCO_SECRET is not set
# end of EFI (Extensible Firmware Interface) Support

CONFIG_UEFI_CPER=y
CONFIG_UEFI_CPER_ARM=y
# CONFIG_TEE_STMM_EFI is not set
CONFIG_MESON_SM=y
CONFIG_MESON_GX_PM=y
CONFIG_ARM_PSCI_FW=y

#
# Qualcomm firmware drivers
#
# end of Qualcomm firmware drivers

CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_ARM_SMCCC_SOC_ID=y

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_GNSS=m
CONFIG_GNSS_SERIAL=m
CONFIG_GNSS_MTK_SERIAL=m
CONFIG_GNSS_SIRF_SERIAL=m
CONFIG_GNSS_UBX_SERIAL=m
CONFIG_GNSS_USB=m
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_AFS_PARTS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y

#
# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
#
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_DATAFLASH is not set
CONFIG_MTD_MCHP23K256=m
# CONFIG_MTD_MCHP48L640 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
CONFIG_MTD_NAND_CORE=y
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
# CONFIG_MTD_SPI_NAND is not set

#
# ECC engine support
#
CONFIG_MTD_NAND_ECC=y
# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
CONFIG_MTD_NAND_ECC_MXIC=y
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
# CONFIG_MTD_UBI_BLOCK is not set
# CONFIG_MTD_UBI_NVMEM is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_NULL_BLK=m
CONFIG_CDROM=m
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
CONFIG_ZRAM=m
CONFIG_ZRAM_BACKEND_LZ4=y
CONFIG_ZRAM_BACKEND_LZ4HC=y
CONFIG_ZRAM_BACKEND_ZSTD=y
CONFIG_ZRAM_BACKEND_DEFLATE=y
CONFIG_ZRAM_BACKEND_842=y
CONFIG_ZRAM_BACKEND_LZO=y
# CONFIG_ZRAM_DEF_COMP_LZORLE is not set
# CONFIG_ZRAM_DEF_COMP_LZO is not set
# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
CONFIG_ZRAM_DEF_COMP_ZSTD=y
# CONFIG_ZRAM_DEF_COMP_DEFLATE is not set
# CONFIG_ZRAM_DEF_COMP_842 is not set
CONFIG_ZRAM_DEF_COMP="zstd"
CONFIG_ZRAM_WRITEBACK=y
CONFIG_ZRAM_TRACK_ENTRY_ACTIME=y
# CONFIG_ZRAM_MEMORY_TRACKING is not set
CONFIG_ZRAM_MULTI_COMP=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=64
CONFIG_BLK_DEV_DRBD=m
CONFIG_DRBD_FAULT_INJECTION=y
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_VIRTIO_BLK=m
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_UBLK is not set

#
# NVME Support
#
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
# CONFIG_NVME_MULTIPATH is not set
# CONFIG_NVME_VERBOSE_ERRORS is not set
CONFIG_NVME_HWMON=y
CONFIG_NVME_FABRICS=m
# CONFIG_NVME_FC is not set
CONFIG_NVME_TCP=m
# CONFIG_NVME_TCP_TLS is not set
# CONFIG_NVME_HOST_AUTH is not set
CONFIG_NVME_TARGET=m
# CONFIG_NVME_TARGET_DEBUGFS is not set
# CONFIG_NVME_TARGET_PASSTHRU is not set
CONFIG_NVME_TARGET_LOOP=m
# CONFIG_NVME_TARGET_FC is not set
CONFIG_NVME_TARGET_TCP=m
# CONFIG_NVME_TARGET_TCP_TLS is not set
# CONFIG_NVME_TARGET_AUTH is not set
# end of NVME Support

#
# Misc devices
#
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
# CONFIG_RPMB is not set
CONFIG_TIFM_CORE=m
CONFIG_TIFM_7XX1=m
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HI6421V600_IRQ is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
# CONFIG_DW_XDATA_PCIE is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_XILINX_SDFEC is not set
CONFIG_MISC_RTSX=m
# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_OPEN_DICE is not set
# CONFIG_VCPU_STALL_DETECTOR is not set
# CONFIG_NSM is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
CONFIG_EEPROM_AT25=m
# CONFIG_EEPROM_MAX6875 is not set
CONFIG_EEPROM_93CX6=m
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

CONFIG_CB710_CORE=m
# CONFIG_CB710_DEBUG is not set
CONFIG_CB710_DEBUG_ASSUMPTIONS=y

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline

# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
# CONFIG_VMWARE_VMCI is not set
# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_BCM_VK is not set
# CONFIG_MISC_ALCOR_PCI is not set
# CONFIG_MISC_RTSX_PCI is not set
CONFIG_MISC_RTSX_USB=m
# CONFIG_UACCE is not set
# CONFIG_PVPANIC is not set
# CONFIG_GP_PCI1XXXX is not set
# CONFIG_KEBA_CP500 is not set
CONFIG_SUNXI_ADDR_MGT=m
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI_COMMON=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=m
CONFIG_BLK_DEV_BSG=y
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=m
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_ISCSI_BOOT_SYSFS=m
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_MPI3MR is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_FDOMAIN_PCI is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
CONFIG_SCSI_VIRTIO=m
# CONFIG_SCSI_DH is not set
# end of SCSI device support

CONFIG_ATA=y
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_ATA_LEDS=y
CONFIG_ARCH_WANT_LIBATA_LEDS=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_AHCI_DWC=y
CONFIG_AHCI_CEVA=m
CONFIG_AHCI_SUNXI=y
CONFIG_SATA_INIC162X=m
CONFIG_SATA_ACARD_AHCI=m
CONFIG_SATA_SIL24=m
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#
# CONFIG_PDC_ADMA is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_SATA_SX4 is not set
CONFIG_ATA_BMDMA=y

#
# SATA SFF controllers with BMDMA
#
# CONFIG_ATA_PIIX is not set
# CONFIG_SATA_DWC is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_NV is not set
# CONFIG_SATA_PROMISE is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIS is not set
# CONFIG_SATA_SVW is not set
# CONFIG_SATA_ULI is not set
# CONFIG_SATA_VIA is not set
# CONFIG_SATA_VITESSE is not set

#
# PATA SFF controllers with BMDMA
#
# CONFIG_PATA_ALI is not set
# CONFIG_PATA_AMD is not set
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_ATP867X is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CYPRESS is not set
# CONFIG_PATA_EFAR is not set
# CONFIG_PATA_HPT366 is not set
# CONFIG_PATA_HPT37X is not set
# CONFIG_PATA_HPT3X2N is not set
# CONFIG_PATA_HPT3X3 is not set
# CONFIG_PATA_IT8213 is not set
# CONFIG_PATA_IT821X is not set
# CONFIG_PATA_JMICRON is not set
# CONFIG_PATA_MARVELL is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_OPTIDMA is not set
# CONFIG_PATA_PDC2027X is not set
# CONFIG_PATA_PDC_OLD is not set
# CONFIG_PATA_RADISYS is not set
# CONFIG_PATA_RDC is not set
# CONFIG_PATA_SCH is not set
# CONFIG_PATA_SERVERWORKS is not set
# CONFIG_PATA_SIL680 is not set
# CONFIG_PATA_SIS is not set
# CONFIG_PATA_TOSHIBA is not set
# CONFIG_PATA_TRIFLEX is not set
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set

#
# PIO-only SFF controllers
#
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_OF_PLATFORM is not set
# CONFIG_PATA_RZ1000 is not set

#
# Generic fallback / legacy drivers
#
# CONFIG_PATA_ACPI is not set
# CONFIG_ATA_GENERIC is not set
# CONFIG_PATA_LEGACY is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_BITMAP_FILE=y
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_CLUSTER=m
CONFIG_BCACHE=m
# CONFIG_BCACHE_DEBUG is not set
# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=m
# CONFIG_DM_DEBUG is not set
CONFIG_DM_BUFIO=m
# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
# CONFIG_DM_CACHE is not set
CONFIG_DM_WRITECACHE=m
# CONFIG_DM_EBS is not set
# CONFIG_DM_ERA is not set
# CONFIG_DM_CLONE is not set
CONFIG_DM_MIRROR=m
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
# CONFIG_DM_MULTIPATH_HST is not set
# CONFIG_DM_MULTIPATH_IOA is not set
CONFIG_DM_DELAY=m
# CONFIG_DM_DUST is not set
# CONFIG_DM_UEVENT is not set
CONFIG_DM_FLAKEY=m
CONFIG_DM_VERITY=m
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
# CONFIG_DM_VERITY_FEC is not set
# CONFIG_DM_SWITCH is not set
CONFIG_DM_LOG_WRITES=m
CONFIG_DM_INTEGRITY=m
CONFIG_DM_AUDIT=y
# CONFIG_DM_VDO is not set
CONFIG_TARGET_CORE=m
# CONFIG_TCM_IBLOCK is not set
# CONFIG_TCM_FILEIO is not set
# CONFIG_TCM_PSCSI is not set
# CONFIG_LOOPBACK_TARGET is not set
CONFIG_ISCSI_TARGET=m
# CONFIG_REMOTE_TARGET is not set
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
# end of IEEE 1394 (FireWire) support

CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_WIREGUARD=m
# CONFIG_WIREGUARD_DEBUG is not set
CONFIG_EQUALIZER=m
# CONFIG_NET_FC is not set
CONFIG_IFB=m
CONFIG_NET_TEAM=m
CONFIG_NET_TEAM_MODE_BROADCAST=m
CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
CONFIG_NET_TEAM_MODE_RANDOM=m
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
CONFIG_NET_TEAM_MODE_LOADBALANCE=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=m
CONFIG_IPVTAP=m
CONFIG_VXLAN=m
CONFIG_GENEVE=m
CONFIG_BAREUDP=m
CONFIG_GTP=m
CONFIG_PFCP=m
CONFIG_AMT=m
CONFIG_MACSEC=m
CONFIG_NETCONSOLE=m
CONFIG_NETCONSOLE_DYNAMIC=y
# CONFIG_NETCONSOLE_EXTENDED_LOG is not set
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=m
CONFIG_TAP=m
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_NLMON=m
# CONFIG_NETKIT is not set
CONFIG_NET_VRF=m
CONFIG_MHI_NET=m
# CONFIG_ARCNET is not set

#
# Distributed Switch Architecture drivers
#
CONFIG_B53=m
CONFIG_B53_SPI_DRIVER=m
CONFIG_B53_MDIO_DRIVER=m
CONFIG_B53_MMAP_DRIVER=m
CONFIG_B53_SRAB_DRIVER=m
CONFIG_B53_SERDES=m
CONFIG_NET_DSA_BCM_SF2=m
CONFIG_NET_DSA_LOOP=m
CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
CONFIG_NET_DSA_LANTIQ_GSWIP=m
CONFIG_NET_DSA_MT7530=m
CONFIG_NET_DSA_MT7530_MDIO=m
CONFIG_NET_DSA_MT7530_MMIO=m
CONFIG_NET_DSA_MV88E6060=m
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
CONFIG_NET_DSA_MICROCHIP_KSZ_PTP=y
CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
CONFIG_NET_DSA_MV88E6XXX=m
CONFIG_NET_DSA_MV88E6XXX_PTP=y
CONFIG_NET_DSA_MV88E6XXX_LEDS=y
CONFIG_NET_DSA_AR9331=m
CONFIG_NET_DSA_QCA8K=m
CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y
CONFIG_NET_DSA_SJA1105=m
CONFIG_NET_DSA_SJA1105_PTP=y
CONFIG_NET_DSA_SJA1105_TAS=y
CONFIG_NET_DSA_SJA1105_VL=y
CONFIG_NET_DSA_XRS700X=m
CONFIG_NET_DSA_XRS700X_I2C=m
CONFIG_NET_DSA_XRS700X_MDIO=m
CONFIG_NET_DSA_REALTEK=m
CONFIG_NET_DSA_REALTEK_MDIO=y
CONFIG_NET_DSA_REALTEK_SMI=y
CONFIG_NET_DSA_REALTEK_RTL8365MB=m
CONFIG_NET_DSA_REALTEK_RTL8366RB=m
CONFIG_NET_DSA_REALTEK_RTL8366RB_LEDS=y
CONFIG_NET_DSA_SMSC_LAN9303=m
CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
CONFIG_NET_DSA_VITESSE_VSC73XX=m
CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
# end of Distributed Switch Architecture drivers

CONFIG_ETHERNET=y
CONFIG_MDIO=m
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
CONFIG_NET_VENDOR_ALLWINNER=y
CONFIG_SUN4I_EMAC=y
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_ALTERA_TSE is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
CONFIG_NET_VENDOR_ASIX=y
# CONFIG_SPI_AX88796C is not set
CONFIG_NET_VENDOR_ATHEROS=y
# CONFIG_ATL2 is not set
# CONFIG_ATL1 is not set
# CONFIG_ATL1E is not set
# CONFIG_ATL1C is not set
CONFIG_ALX=m
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_CORTINA is not set
CONFIG_NET_VENDOR_DAVICOM=y
# CONFIG_DM9051 is not set
# CONFIG_DNET is not set
# CONFIG_NET_VENDOR_DEC is not set
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
CONFIG_NET_VENDOR_ENGLEDER=y
# CONFIG_TSNEP is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_FREESCALE is not set
CONFIG_NET_VENDOR_FUNGIBLE=y
# CONFIG_FUN_ETH is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
CONFIG_NET_VENDOR_I825XX=y
CONFIG_NET_VENDOR_INTEL=y
# CONFIG_E100 is not set
CONFIG_E1000=m
CONFIG_E1000E=m
CONFIG_IGB=m
CONFIG_IGB_HWMON=y
CONFIG_IGBVF=m
# CONFIG_IXGBE is not set
# CONFIG_IXGBEVF is not set
# CONFIG_I40E is not set
# CONFIG_I40EVF is not set
# CONFIG_ICE is not set
# CONFIG_FM10K is not set
CONFIG_IGC=m
CONFIG_IGC_LEDS=y
# CONFIG_IDPF is not set
CONFIG_JME=m
CONFIG_NET_VENDOR_ADI=y
# CONFIG_ADIN1110 is not set
CONFIG_NET_VENDOR_LITEX=y
# CONFIG_LITEX_LITEETH is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
CONFIG_NET_VENDOR_META=y
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_MICROSOFT is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_FEALNX is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETERION is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_ETHOC is not set
# CONFIG_OA_TC6 is not set
# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_BROCADE is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCA7000_UART is not set
CONFIG_QCOM_EMAC=m
CONFIG_SFE_SUPPORT_IPV6=y
CONFIG_SFE_ECM=y
CONFIG_FAST_CLASSIFIER=y
# CONFIG_RMNET is not set
# CONFIG_NET_VENDOR_RDC is not set
CONFIG_NET_VENDOR_REALTEK=y
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
CONFIG_R8125=m
CONFIG_R8125_SOC_LAN=y
# CONFIG_R8125_REALWOW_SUPPORT is not set
# CONFIG_R8125_DASH_SUPPORT is not set
# CONFIG_R8125_DOWN_SPEED_100 is not set
# CONFIG_R8125_ASPM is not set
CONFIG_R8125_WOL_SUPPORT=y
CONFIG_R8125_S5WOL=y
# CONFIG_R8125_S5_KEEP_CURR_MAC is not set
# CONFIG_R8125_EEE is not set
# CONFIG_R8125_S0_MAGIC_PACKET is not set
CONFIG_R8125_TX_NO_CLOSE=y
CONFIG_R8125_MULTI_MSIX_VECTOR=y
CONFIG_R8125_MULTIPLE_TX_QUEUE=y
CONFIG_R8125_RSS_SUPPORT=y
# CONFIG_R8125_PTP_SUPPORT is not set
CONFIG_R8125_FIBER_SUPPORT=y
CONFIG_R8125_USE_FIRMWARE_FILE=y
# CONFIG_R8125_DOUBLE_VLAN is not set
# CONFIG_R8125_PAGE_REUSE is not set
CONFIG_R8125_GIGA_LITE=y
CONFIG_R8126=m
CONFIG_R8126_SOC_LAN=y
# CONFIG_R8126_REALWOW_SUPPORT is not set
# CONFIG_R8126_DASH_SUPPORT is not set
# CONFIG_R8126_DOWN_SPEED_100 is not set
# CONFIG_R8126_ASPM is not set
CONFIG_R8126_WOL_SUPPORT=y
CONFIG_R8126_S5WOL=y
# CONFIG_R8126_S5_KEEP_CURR_MAC is not set
# CONFIG_R8126_EEE is not set
# CONFIG_R8126_S0_MAGIC_PACKET is not set
CONFIG_R8126_TX_NO_CLOSE=y
CONFIG_R8126_MULTI_MSIX_VECTOR=y
CONFIG_R8126_MULTIPLE_TX_QUEUE=y
CONFIG_R8126_RSS_SUPPORT=y
CONFIG_R8126_PTP_SUPPORT=y
CONFIG_R8126_FIBER_SUPPORT=y
CONFIG_R8126_USE_FIRMWARE_FILE=y
# CONFIG_R8126_DOUBLE_VLAN is not set
# CONFIG_R8126_PAGE_REUSE is not set
CONFIG_R8126_GIGA_LITE=y
CONFIG_R8168=m
CONFIG_R8168_SOC_LAN=y
# CONFIG_R8168_FIBER_SUPPORT is not set
# CONFIG_R8168_REALWOW_SUPPORT is not set
# CONFIG_R8168_DASH_SUPPORT is not set
# CONFIG_R8168_DOWN_SPEED_100 is not set
CONFIG_R8168_ASPM=y
CONFIG_R8168_DYNAMIC_ASPM=y
CONFIG_R8168_WOL_SUPPORT=y
CONFIG_R8168_S5WOL=y
# CONFIG_R8168_S5_KEEP_CURR_MAC is not set
CONFIG_R8168_EEE=y
# CONFIG_R8168_S0_MAGIC_PACKET is not set
# CONFIG_R8168_USE_FIRMWARE_FILE is not set
# CONFIG_R8168_CTAP_SHORT_OFF is not set
# CONFIG_R8168_MULTIPLE_TX_QUEUE is not set
# CONFIG_R8168_RSS_SUPPORT is not set
CONFIG_R8168_GIGA_LITE=y
# CONFIG_R8169 is not set
# CONFIG_RTASE is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_SELFTESTS=y
CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_MESON=y
CONFIG_DWMAC_ROCKCHIP=y
CONFIG_DWMAC_SUNXI=y
CONFIG_DWMAC_SUN8I=y
# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
CONFIG_NET_VENDOR_VERTEXCOM=y
# CONFIG_MSE102X is not set
# CONFIG_NET_VENDOR_VIA is not set
CONFIG_NET_VENDOR_WANGXUN=y
# CONFIG_NGBE is not set
# CONFIG_TXGBE is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_PHYLIB_LEDS=y
CONFIG_FIXED_PHY=y
# CONFIG_SFP is not set

#
# Switch configuration API + drivers
#
CONFIG_SWCONFIG=m
CONFIG_SWCONFIG_LEDS=y
CONFIG_RTL8306_PHY=m
CONFIG_RTL8366_SMI=m
CONFIG_RTL8366_SMI_DEBUG_FS=y
CONFIG_RTL8366S_PHY=m
CONFIG_RTL8366RB_PHY=m
CONFIG_RTL8367_PHY=m
CONFIG_RTL8367B_PHY=m

#
# MII PHY device drivers
#
# CONFIG_AIR_EN8811H_PHY is not set
CONFIG_AC200_PHY=m
# CONFIG_AMD_PHY is not set
CONFIG_MESON_GXL_PHY=y
# CONFIG_ADIN_PHY is not set
# CONFIG_ADIN1100_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
CONFIG_AX88796B_PHY=m
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM54140_PHY is not set
CONFIG_BCM7XXX_PHY=m
# CONFIG_BCM84881_PHY is not set
# CONFIG_BCM87XX_PHY is not set
CONFIG_BCM_NET_PHYLIB=m
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
CONFIG_ICPLUS_PHY=y
CONFIG_JLSEMI_PHY=y
# CONFIG_LXT_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MARVELL_88Q2XXX_PHY is not set
# CONFIG_MARVELL_88X2222_PHY is not set
# CONFIG_MAXLINEAR_GPHY is not set
CONFIG_MEDIATEK_GE_PHY=m
# CONFIG_MEDIATEK_GE_SOC_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_MICROCHIP_T1S_PHY is not set
CONFIG_MICROCHIP_PHY=m
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
CONFIG_MOTORCOMM_PHY=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_NXP_CBTX_PHY is not set
# CONFIG_NXP_C45_TJA11XX_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
# CONFIG_NCN26000_PHY is not set
# CONFIG_AT803X_PHY is not set
# CONFIG_QCA83XX_PHY is not set
# CONFIG_QCA808X_PHY is not set
# CONFIG_QCA807X_PHY is not set
# CONFIG_QSEMI_PHY is not set
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
CONFIG_SMSC_PHY=y
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
# CONFIG_DP83869_PHY is not set
# CONFIG_DP83TD510_PHY is not set
# CONFIG_DP83TG720_PHY is not set
CONFIG_VITESSE_PHY=m
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_PSE_CONTROLLER is not set
CONFIG_CAN_DEV=m
CONFIG_CAN_VCAN=m
CONFIG_CAN_VXCAN=m
CONFIG_CAN_NETLINK=y
CONFIG_CAN_CALC_BITTIMING=y
CONFIG_CAN_RX_OFFLOAD=y
# CONFIG_CAN_CAN327 is not set
# CONFIG_CAN_FLEXCAN is not set
# CONFIG_CAN_GRCAN is not set
# CONFIG_CAN_KVASER_PCIEFD is not set
# CONFIG_CAN_SLCAN is not set
# CONFIG_CAN_XILINXCAN is not set
# CONFIG_CAN_C_CAN is not set
# CONFIG_CAN_CC770 is not set
# CONFIG_CAN_CTUCANFD_PCI is not set
# CONFIG_CAN_CTUCANFD_PLATFORM is not set
# CONFIG_CAN_ESD_402_PCI is not set
# CONFIG_CAN_IFI_CANFD is not set
# CONFIG_CAN_M_CAN is not set
# CONFIG_CAN_PEAK_PCIEFD is not set
CONFIG_CAN_ROCKCHIP_CANFD=m
# CONFIG_CAN_SJA1000 is not set
# CONFIG_CAN_SOFTING is not set

#
# CAN SPI interfaces
#
# CONFIG_CAN_HI311X is not set
# CONFIG_CAN_MCP251X is not set
# CONFIG_CAN_MCP251XFD is not set
# end of CAN SPI interfaces

#
# CAN USB interfaces
#
# CONFIG_CAN_8DEV_USB is not set
# CONFIG_CAN_EMS_USB is not set
# CONFIG_CAN_ESD_USB is not set
# CONFIG_CAN_ETAS_ES58X is not set
# CONFIG_CAN_F81604 is not set
# CONFIG_CAN_GS_USB is not set
# CONFIG_CAN_KVASER_USB is not set
# CONFIG_CAN_MCBA_USB is not set
# CONFIG_CAN_PEAK_USB is not set
# CONFIG_CAN_UCAN is not set
# end of CAN USB interfaces

# CONFIG_CAN_DEBUG_DEVICES is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_FWNODE_MDIO=y
CONFIG_OF_MDIO=y
CONFIG_ACPI_MDIO=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_SUN4I=y
CONFIG_MDIO_BITBANG=m
CONFIG_MDIO_BCM_UNIMAC=m
CONFIG_MDIO_GPIO=m
# CONFIG_MDIO_HISI_FEMAC is not set
CONFIG_MDIO_MVUSB=m
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_OCTEON is not set
CONFIG_MDIO_IPQ4019=m
CONFIG_MDIO_IPQ8064=m
# CONFIG_MDIO_THUNDER is not set

#
# MDIO Multiplexers
#
CONFIG_MDIO_BUS_MUX=y
CONFIG_MDIO_BUS_MUX_MESON_G12A=y
CONFIG_MDIO_BUS_MUX_MESON_GXL=m
CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y

#
# PCS device drivers
#
CONFIG_PCS_XPCS=y
CONFIG_PCS_MTK_LYNXI=m
# end of PCS device drivers

CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=m
# CONFIG_PPPOE_HASH_BITS_1 is not set
# CONFIG_PPPOE_HASH_BITS_2 is not set
CONFIG_PPPOE_HASH_BITS_4=y
# CONFIG_PPPOE_HASH_BITS_8 is not set
CONFIG_PPPOE_HASH_BITS=4
CONFIG_PPTP=m
CONFIG_PPPOL2TP=m
CONFIG_PPP_ASYNC=m
# CONFIG_PPP_SYNC_TTY is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=m
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_AX8817X=m
CONFIG_USB_NET_AX88179_178A=m
CONFIG_USB_NET_CDCETHER=m
CONFIG_USB_NET_CDC_EEM=m
CONFIG_USB_NET_CDC_NCM=m
CONFIG_USB_NET_HUAWEI_CDC_NCM=m
CONFIG_USB_NET_CDC_MBIM=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9700=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
CONFIG_USB_NET_CDC_SUBSET=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
CONFIG_USB_EPSON2888=y
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=m
CONFIG_USB_NET_CX82310_ETH=m
CONFIG_USB_NET_KALMIA=m
CONFIG_USB_NET_QMI_WWAN=m
CONFIG_USB_HSO=m
CONFIG_USB_NET_INT51X1=m
CONFIG_USB_IPHETH=m
CONFIG_USB_SIERRA_NET=m
CONFIG_USB_VL600=m
CONFIG_USB_NET_CH9200=m
CONFIG_USB_NET_AQC111=m
CONFIG_USB_RTL8153_ECM=m
CONFIG_WLAN=y
CONFIG_WLAN_VENDOR_ADMTEK=y
CONFIG_ADM8211=m
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
CONFIG_ATH_USER_REGD=y
# CONFIG_ATH_DEBUG is not set
CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS=y
# CONFIG_ATH_REG_DYNAMIC_USER_CERT_TESTING is not set
CONFIG_ATH5K=m
# CONFIG_ATH5K_DEBUG is not set
# CONFIG_ATH5K_TRACER is not set
CONFIG_ATH5K_PCI=y
# CONFIG_ATH5K_TEST_CHANNELS is not set
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=m
CONFIG_ATH9K_PCI=y
CONFIG_ATH9K_AHB=y
CONFIG_ATH9K_DFS_CERTIFIED=y
CONFIG_ATH9K_DYNACK=y
# CONFIG_ATH9K_WOW is not set
CONFIG_ATH9K_RFKILL=y
CONFIG_ATH9K_CHANNEL_CONTEXT=y
# CONFIG_ATH9K_PCOEM is not set
CONFIG_ATH9K_PCI_NO_EEPROM=m
CONFIG_ATH9K_HTC=m
# CONFIG_ATH9K_HTC_DEBUGFS is not set
CONFIG_ATH9K_HWRNG=y
CONFIG_CARL9170=m
CONFIG_CARL9170_LEDS=y
CONFIG_CARL9170_WPC=y
CONFIG_CARL9170_HWRNG=y
CONFIG_ATH6KL=m
CONFIG_ATH6KL_SDIO=m
CONFIG_ATH6KL_USB=m
# CONFIG_ATH6KL_DEBUG is not set
# CONFIG_ATH6KL_TRACING is not set
# CONFIG_ATH6KL_REGDOMAIN is not set
CONFIG_AR5523=m
# CONFIG_WIL6210 is not set
CONFIG_ATH10K=m
CONFIG_ATH10K_CE=y
CONFIG_ATH10K_PCI=m
# CONFIG_ATH10K_AHB is not set
CONFIG_ATH10K_SDIO=m
CONFIG_ATH10K_USB=m
# CONFIG_ATH10K_DEBUG is not set
# CONFIG_ATH10K_DEBUGFS is not set
CONFIG_ATH10K_LEDS=y
# CONFIG_ATH10K_TRACING is not set
CONFIG_ATH10K_DFS_CERTIFIED=y
CONFIG_WCN36XX=m
# CONFIG_WCN36XX_DEBUGFS is not set
CONFIG_ATH11K=m
# CONFIG_ATH11K_AHB is not set
CONFIG_ATH11K_PCI=m
# CONFIG_ATH11K_DEBUG is not set
# CONFIG_ATH11K_TRACING is not set
CONFIG_ATH12K=m
# CONFIG_ATH12K_DEBUG is not set
# CONFIG_ATH12K_TRACING is not set
CONFIG_WLAN_VENDOR_ATMEL=y
CONFIG_AT76C50X_USB=m
CONFIG_WLAN_VENDOR_BROADCOM=y
# CONFIG_B43 is not set
# CONFIG_B43LEGACY is not set
CONFIG_BRCMUTIL=m
# CONFIG_BRCMSMAC is not set
CONFIG_BRCMFMAC=m
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
# CONFIG_BRCMFMAC_PCIE is not set
CONFIG_BRCM_TRACING=y
CONFIG_BRCMDBG=y
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_IPW2100=m
# CONFIG_IPW2100_MONITOR is not set
# CONFIG_IPW2100_DEBUG is not set
CONFIG_IPW2200=m
# CONFIG_IPW2200_MONITOR is not set
# CONFIG_IPW2200_QOS is not set
# CONFIG_IPW2200_DEBUG is not set
CONFIG_LIBIPW=m
# CONFIG_LIBIPW_DEBUG is not set
CONFIG_IWLEGACY=m
CONFIG_IWL4965=m
CONFIG_IWL3945=m

#
# iwl3945 / iwl4965 Debugging Options
#
# CONFIG_IWLEGACY_DEBUG is not set
# end of iwl3945 / iwl4965 Debugging Options

CONFIG_IWLWIFI=m
CONFIG_IWLWIFI_LEDS=y
CONFIG_IWLDVM=m
CONFIG_IWLMVM=m
CONFIG_IWLWIFI_OPMODE_MODULAR=y

#
# Debugging Options
#
# CONFIG_IWLWIFI_DEBUG is not set
# CONFIG_IWLWIFI_DEVICE_TRACING is not set
# end of Debugging Options

CONFIG_WLAN_VENDOR_INTERSIL=y
CONFIG_P54_COMMON=m
CONFIG_P54_USB=m
CONFIG_P54_PCI=m
CONFIG_P54_SPI=m
# CONFIG_P54_SPI_DEFAULT_EEPROM is not set
CONFIG_P54_LEDS=y
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_USB=m
CONFIG_LIBERTAS_SDIO=m
CONFIG_LIBERTAS_SPI=m
# CONFIG_LIBERTAS_DEBUG is not set
CONFIG_LIBERTAS_MESH=y
CONFIG_LIBERTAS_THINFIRM=m
# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
CONFIG_LIBERTAS_THINFIRM_USB=m
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_SDIO=m
CONFIG_MWIFIEX_PCIE=m
CONFIG_MWIFIEX_USB=m
CONFIG_MWL8K=m
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=m
CONFIG_MT76_CORE=m
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=m
CONFIG_MT76_SDIO=m
CONFIG_MT76x02_LIB=m
CONFIG_MT76x02_USB=m
CONFIG_MT76_CONNAC_LIB=m
CONFIG_MT792x_LIB=m
CONFIG_MT792x_USB=m
CONFIG_MT76x0_COMMON=m
CONFIG_MT76x0U=m
CONFIG_MT76x0E=m
CONFIG_MT76x2_COMMON=m
CONFIG_MT76x2E=m
CONFIG_MT76x2U=m
CONFIG_MT7603E=m
CONFIG_MT7615_COMMON=m
CONFIG_MT7615E=m
CONFIG_MT7663_USB_SDIO_COMMON=m
CONFIG_MT7663U=m
CONFIG_MT7663S=m
CONFIG_MT7915E=m
CONFIG_MT7921_COMMON=m
CONFIG_MT7921E=m
CONFIG_MT7921S=m
CONFIG_MT7921U=m
CONFIG_MT7996E=m
CONFIG_MT7925_COMMON=m
CONFIG_MT7925E=m
CONFIG_MT7925U=m
CONFIG_WLAN_VENDOR_MICROCHIP=y
CONFIG_WILC1000=m
CONFIG_WILC1000_SDIO=m
# CONFIG_WILC1000_SPI is not set
# CONFIG_WILC1000_HW_OOB_INTR is not set
CONFIG_WLAN_VENDOR_PURELIFI=y
# CONFIG_PLFXLC is not set
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=m
# CONFIG_RT2400PCI is not set
# CONFIG_RT2500PCI is not set
# CONFIG_RT61PCI is not set
CONFIG_RT2800PCI=m
CONFIG_RT2800PCI_RT33XX=y
CONFIG_RT2800PCI_RT35XX=y
CONFIG_RT2800PCI_RT53XX=y
CONFIG_RT2800PCI_RT3290=y
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
CONFIG_RT2800USB_RT33XX=y
CONFIG_RT2800USB_RT35XX=y
CONFIG_RT2800USB_RT3573=y
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
CONFIG_RT2800USB_UNKNOWN=y
CONFIG_RT2800_LIB=m
CONFIG_RT2800_LIB_MMIO=m
CONFIG_RT2X00_LIB_MMIO=m
CONFIG_RT2X00_LIB_PCI=m
CONFIG_RT2X00_LIB_USB=m
CONFIG_RT2X00_LIB=m
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
# CONFIG_RT2X00_DEBUG is not set
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_RTL8180=m
CONFIG_RTL8187=m
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=m
CONFIG_RTL8192CE=m
CONFIG_RTL8192SE=m
CONFIG_RTL8192DE=m
CONFIG_RTL8723AE=m
CONFIG_RTL8723BE=m
CONFIG_RTL8188EE=m
CONFIG_RTL8192EE=m
CONFIG_RTL8821AE=m
CONFIG_RTL8192CU=m
CONFIG_RTL8192DU=m
CONFIG_RTLWIFI=m
CONFIG_RTLWIFI_PCI=m
CONFIG_RTLWIFI_USB=m
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8192D_COMMON=m
CONFIG_RTL8723_COMMON=m
CONFIG_RTLBTCOEXIST=m
CONFIG_RTL8XXXU=m
# CONFIG_RTL8XXXU_UNTESTED is not set
CONFIG_RTW88=m
CONFIG_RTW88_CORE=m
CONFIG_RTW88_PCI=m
CONFIG_RTW88_SDIO=m
CONFIG_RTW88_USB=m
CONFIG_RTW88_8822B=m
CONFIG_RTW88_8822C=m
CONFIG_RTW88_8723X=m
CONFIG_RTW88_8703B=m
CONFIG_RTW88_8723D=m
CONFIG_RTW88_8821C=m
CONFIG_RTW88_8822BE=m
CONFIG_RTW88_8822BS=m
CONFIG_RTW88_8822BU=m
CONFIG_RTW88_8822CE=m
CONFIG_RTW88_8822CS=m
CONFIG_RTW88_8822CU=m
CONFIG_RTW88_8723DE=m
CONFIG_RTW88_8723DS=m
CONFIG_RTW88_8723CS=m
CONFIG_RTW88_8723DU=m
CONFIG_RTW88_8821CE=m
CONFIG_RTW88_8821CS=m
CONFIG_RTW88_8821CU=m
# CONFIG_RTW88_DEBUG is not set
# CONFIG_RTW88_DEBUGFS is not set
CONFIG_RTW89=m
CONFIG_RTW89_CORE=m
CONFIG_RTW89_PCI=m
CONFIG_RTW89_8851B=m
CONFIG_RTW89_8852A=m
CONFIG_RTW89_8852B_COMMON=m
CONFIG_RTW89_8852B=m
CONFIG_RTW89_8852BT=m
CONFIG_RTW89_8852C=m
CONFIG_RTW89_8922A=m
CONFIG_RTW89_8851BE=m
CONFIG_RTW89_8852AE=m
CONFIG_RTW89_8852BE=m
CONFIG_RTW89_8852BTE=m
CONFIG_RTW89_8852CE=m
CONFIG_RTW89_8922AE=m
# CONFIG_RTW89_DEBUGMSG is not set
# CONFIG_RTW89_DEBUGFS is not set
CONFIG_WLAN_VENDOR_RSI=y
CONFIG_RSI_91X=m
CONFIG_RSI_DEBUGFS=y
CONFIG_RSI_SDIO=m
CONFIG_RSI_USB=m
CONFIG_RSI_COEX=y
CONFIG_WLAN_VENDOR_SILABS=y
# CONFIG_WFX is not set
CONFIG_WLAN_VENDOR_ST=y
CONFIG_CW1200=m
CONFIG_CW1200_WLAN_SDIO=m
CONFIG_CW1200_WLAN_SPI=m
CONFIG_WLAN_VENDOR_TI=y
CONFIG_WL1251=m
# CONFIG_WL1251_SPI is not set
CONFIG_WL1251_SDIO=m
# CONFIG_WL12XX is not set
# CONFIG_WL18XX is not set
CONFIG_WLCORE=m
# CONFIG_WLCORE_SPI is not set
CONFIG_WLCORE_SDIO=m
CONFIG_WLAN_VENDOR_ZYDAS=y
CONFIG_ZD1211RW=m
# CONFIG_ZD1211RW_DEBUG is not set
CONFIG_WLAN_VENDOR_QUANTENNA=y
CONFIG_QTNFMAC=m
CONFIG_QTNFMAC_PCIE=m
CONFIG_MAC80211_HWSIM=m
CONFIG_VIRT_WIFI=m
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
CONFIG_IEEE802154_AT86RF230=m
CONFIG_IEEE802154_MRF24J40=m
CONFIG_IEEE802154_CC2520=m
CONFIG_IEEE802154_ATUSB=m
CONFIG_IEEE802154_ADF7242=m
CONFIG_IEEE802154_CA8210=m
CONFIG_IEEE802154_CA8210_DEBUGFS=y
CONFIG_IEEE802154_MCR20A=m
CONFIG_IEEE802154_HWSIM=m

#
# Wireless WAN
#
CONFIG_WWAN=m
CONFIG_WWAN_DEBUGFS=y
CONFIG_WWAN_HWSIM=m
CONFIG_MHI_WWAN_CTRL=m
CONFIG_MHI_WWAN_MBIM=m
CONFIG_RPMSG_WWAN_CTRL=m
CONFIG_IOSM=m
CONFIG_MTK_T7XX=m
# end of Wireless WAN

CONFIG_VMXNET3=m
# CONFIG_FUJITSU_ES is not set
CONFIG_NETDEVSIM=m
CONFIG_NET_FAILOVER=m
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_SPARSEKMAP is not set
CONFIG_INPUT_MATRIXKMAP=m
CONFIG_INPUT_VIVALDIFMAP=m

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=m
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=m
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADC is not set
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_GPIO_BUTTON_HOTPLUG is not set
CONFIG_KEYBOARD_GPIO_POLLED=y
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_PINEPHONE is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
CONFIG_KEYBOARD_SUN4I_LRADC=m
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_KEYBOARD_CYPRESS_SF is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=m
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
CONFIG_MOUSE_PS2_SENTELIC=y
CONFIG_MOUSE_PS2_TOUCHKIT=y
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_SMBUS=y
CONFIG_MOUSE_SERIAL=m
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=m
CONFIG_MOUSE_ELAN_I2C=m
CONFIG_MOUSE_ELAN_I2C_I2C=y
CONFIG_MOUSE_ELAN_I2C_SMBUS=y
CONFIG_MOUSE_VSXXXAA=m
CONFIG_MOUSE_GPIO=m
CONFIG_MOUSE_SYNAPTICS_I2C=m
CONFIG_MOUSE_SYNAPTICS_USB=m
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_ANALOG=m
CONFIG_JOYSTICK_A3D=m
CONFIG_JOYSTICK_ADC=m
CONFIG_JOYSTICK_ADI=m
CONFIG_JOYSTICK_COBRA=m
CONFIG_JOYSTICK_GF2K=m
CONFIG_JOYSTICK_GRIP=m
CONFIG_JOYSTICK_GRIP_MP=m
CONFIG_JOYSTICK_GUILLEMOT=m
CONFIG_JOYSTICK_INTERACT=m
CONFIG_JOYSTICK_SIDEWINDER=m
CONFIG_JOYSTICK_TMDC=m
CONFIG_JOYSTICK_IFORCE=m
CONFIG_JOYSTICK_IFORCE_USB=m
CONFIG_JOYSTICK_IFORCE_232=m
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
CONFIG_JOYSTICK_STINGER=m
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
CONFIG_JOYSTICK_AS5011=m
CONFIG_JOYSTICK_JOYDUMP=m
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_JOYSTICK_PSXPAD_SPI=m
CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
CONFIG_JOYSTICK_PXRC=m
CONFIG_JOYSTICK_QWIIC=m
CONFIG_JOYSTICK_FSIA6B=m
CONFIG_JOYSTICK_SENSEHAT=m
# CONFIG_JOYSTICK_SEESAW is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=m
CONFIG_TOUCHSCREEN_AD7877=m
CONFIG_TOUCHSCREEN_AD7879=m
CONFIG_TOUCHSCREEN_AD7879_I2C=m
CONFIG_TOUCHSCREEN_AD7879_SPI=m
CONFIG_TOUCHSCREEN_ADC=m
CONFIG_TOUCHSCREEN_AR1021_I2C=m
CONFIG_TOUCHSCREEN_ATMEL_MXT=m
CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y
CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
CONFIG_TOUCHSCREEN_BU21013=m
CONFIG_TOUCHSCREEN_BU21029=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
CONFIG_TOUCHSCREEN_CY8CTMA140=m
CONFIG_TOUCHSCREEN_CY8CTMG110=m
CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
# CONFIG_TOUCHSCREEN_CYTTSP5 is not set
CONFIG_TOUCHSCREEN_DYNAPRO=m
CONFIG_TOUCHSCREEN_HAMPSHIRE=m
CONFIG_TOUCHSCREEN_EETI=m
CONFIG_TOUCHSCREEN_EGALAX=m
CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
CONFIG_TOUCHSCREEN_EXC3000=m
CONFIG_TOUCHSCREEN_FUJITSU=m
CONFIG_TOUCHSCREEN_GOODIX=m
# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C is not set
# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI is not set
CONFIG_TOUCHSCREEN_HIDEEP=m
CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
# CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set
CONFIG_TOUCHSCREEN_ILI210X=m
CONFIG_TOUCHSCREEN_ILITEK=m
CONFIG_TOUCHSCREEN_S6SY761=m
CONFIG_TOUCHSCREEN_GUNZE=m
CONFIG_TOUCHSCREEN_EKTF2127=m
CONFIG_TOUCHSCREEN_ELAN=m
CONFIG_TOUCHSCREEN_ELO=m
CONFIG_TOUCHSCREEN_WACOM_W8001=m
CONFIG_TOUCHSCREEN_WACOM_I2C=m
CONFIG_TOUCHSCREEN_MAX11801=m
CONFIG_TOUCHSCREEN_MMS114=m
CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
CONFIG_TOUCHSCREEN_MSG2638=m
CONFIG_TOUCHSCREEN_MTOUCH=m
# CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS is not set
CONFIG_TOUCHSCREEN_IMAGIS=m
CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
CONFIG_TOUCHSCREEN_INEXIO=m
CONFIG_TOUCHSCREEN_PENMOUNT=m
CONFIG_TOUCHSCREEN_EDT_FT5X06=m
CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
CONFIG_TOUCHSCREEN_TOUCHWIN=m
CONFIG_TOUCHSCREEN_PIXCIR=m
CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
CONFIG_TOUCHSCREEN_WM97XX=m
CONFIG_TOUCHSCREEN_WM9705=y
CONFIG_TOUCHSCREEN_WM9712=y
CONFIG_TOUCHSCREEN_WM9713=y
CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
CONFIG_TOUCHSCREEN_TOUCHIT213=m
CONFIG_TOUCHSCREEN_TSC_SERIO=m
CONFIG_TOUCHSCREEN_TSC200X_CORE=m
CONFIG_TOUCHSCREEN_TSC2004=m
CONFIG_TOUCHSCREEN_TSC2005=m
CONFIG_TOUCHSCREEN_TSC2007=m
CONFIG_TOUCHSCREEN_TSC2007_IIO=y
CONFIG_TOUCHSCREEN_RM_TS=m
CONFIG_TOUCHSCREEN_SILEAD=m
CONFIG_TOUCHSCREEN_SIS_I2C=m
CONFIG_TOUCHSCREEN_ST1232=m
CONFIG_TOUCHSCREEN_STMFTS=m
CONFIG_TOUCHSCREEN_SUN4I=y
CONFIG_TOUCHSCREEN_SUR40=m
CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
CONFIG_TOUCHSCREEN_SX8654=m
CONFIG_TOUCHSCREEN_TPS6507X=m
CONFIG_TOUCHSCREEN_ZET6223=m
CONFIG_TOUCHSCREEN_ZFORCE=m
CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
CONFIG_TOUCHSCREEN_ROHM_BU21023=m
CONFIG_TOUCHSCREEN_IQS5XX=m
# CONFIG_TOUCHSCREEN_IQS7211 is not set
CONFIG_TOUCHSCREEN_ZINITIX=m
# CONFIG_TOUCHSCREEN_HIMAX_HX83112B is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
# CONFIG_INPUT_BMA150 is not set
# CONFIG_INPUT_E3X0_BUTTON is not set
# CONFIG_INPUT_MMA8450 is not set
CONFIG_INPUT_GPIO_BEEPER=m
CONFIG_INPUT_GPIO_DECODER=m
CONFIG_INPUT_GPIO_VIBRA=m
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
# CONFIG_INPUT_KXTJ9 is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
CONFIG_INPUT_CM109=m
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
CONFIG_INPUT_AXP20X_PEK=y
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_PCF8574 is not set
CONFIG_INPUT_PWM_BEEPER=m
CONFIG_INPUT_PWM_VIBRA=m
CONFIG_INPUT_RK805_PWRKEY=y
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_DA7280_HAPTICS is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_IBM_PANEL is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_INPUT_IQS269A is not set
# CONFIG_INPUT_IQS626A is not set
# CONFIG_INPUT_IQS7222 is not set
# CONFIG_INPUT_CMA3000 is not set
# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
# CONFIG_INPUT_DRV260X_HAPTICS is not set
# CONFIG_INPUT_DRV2665_HAPTICS is not set
# CONFIG_INPUT_DRV2667_HAPTICS is not set
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=y
CONFIG_RMI4_SPI=y
CONFIG_RMI4_SMB=y
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=y
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
CONFIG_RMI4_F3A=y
CONFIG_RMI4_F54=y
CONFIG_RMI4_F55=y

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=m
# CONFIG_SERIO_AMBAKMI is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=m
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
CONFIG_SERIO_SUN4I_PS2=y
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
CONFIG_GAMEPORT=m
# CONFIG_GAMEPORT_EMU10K1 is not set
# CONFIG_GAMEPORT_FM801 is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_LEGACY_TIOCSTI=y
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
# CONFIG_SERIAL_8250_PCI is not set
# CONFIG_SERIAL_8250_EXAR is not set
CONFIG_SERIAL_8250_NR_UARTS=5
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
# CONFIG_SERIAL_8250_EXTENDED is not set
# CONFIG_SERIAL_8250_PCI1XXXX is not set
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
# CONFIG_SERIAL_8250_DFL is not set
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_8250_PERICOM=m
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
CONFIG_SERIAL_AMBA_PL010=y
CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set
CONFIG_SERIAL_MESON=y
CONFIG_SERIAL_MESON_CONSOLE=y
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_QE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_NOZOMI is not set
# CONFIG_NULL_TTY is not set
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
# CONFIG_RPMSG_TTY is not set
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_TTY_PRINTK is not set
CONFIG_VIRTIO_CONSOLE=m
# CONFIG_IPMI_HANDLER is not set
# CONFIG_SSIF_IPMI_BMC is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=y
CONFIG_HW_RANDOM_BA431=m
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_MESON=y
CONFIG_HW_RANDOM_OPTEE=m
CONFIG_HW_RANDOM_CCTRNG=m
CONFIG_HW_RANDOM_XIPHERA=m
CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
CONFIG_HW_RANDOM_CN10K=m
CONFIG_HW_RANDOM_ROCKCHIP=m
CONFIG_HW_RANDOM_ROCKCHIP_BSP=m
# CONFIG_APPLICOM is not set
CONFIG_DEVMEM=y
CONFIG_DEVPORT=y
# CONFIG_TCG_TPM is not set
# CONFIG_XILLYBUS is not set
# CONFIG_XILLYUSB is not set
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_I2C_MUX_GPIO=y
CONFIG_I2C_MUX_GPMUX=y
CONFIG_I2C_MUX_LTC4306=m
CONFIG_I2C_MUX_PCA9541=m
CONFIG_I2C_MUX_PCA954x=m
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_MUX_REG=y
CONFIG_I2C_DEMUX_PINCTRL=y
CONFIG_I2C_MUX_MLXCPLD=m
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_ALGOBIT=y

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
CONFIG_I2C_CCGX_UCSI=m
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set
# CONFIG_I2C_ZHAOXIN is not set

#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CADENCE is not set
# CONFIG_I2C_CBUS_GPIO is not set
CONFIG_I2C_DESIGNWARE_CORE=y
CONFIG_I2C_DESIGNWARE_SLAVE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_DESIGNWARE_PCI=m
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=y
CONFIG_I2C_GPIO_FAULT_INJECTOR=y
# CONFIG_I2C_HISI is not set
CONFIG_I2C_MESON=y
CONFIG_I2C_MV64XXX=y
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
CONFIG_I2C_RK3X=y
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_THUNDERX is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_CP2615 is not set
# CONFIG_I2C_PCI1XXXX is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_MLXCPLD is not set
CONFIG_I2C_VIRTIO=m
# end of I2C Hardware Bus support

# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=m
CONFIG_I2C_SLAVE_TESTUNIT=m
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

# CONFIG_I3C is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y

#
# SPI Master Controller Drivers
#
CONFIG_SPI_ALTERA=m
CONFIG_SPI_ALTERA_CORE=m
CONFIG_SPI_ALTERA_DFL=m
CONFIG_SPI_AMLOGIC_SPIFC_A1=y
CONFIG_SPI_AXI_SPI_ENGINE=m
CONFIG_SPI_BITBANG=m
CONFIG_SPI_CADENCE=m
CONFIG_SPI_CADENCE_QUADSPI=m
CONFIG_SPI_CADENCE_XSPI=m
CONFIG_SPI_CH341=m
CONFIG_SPI_DESIGNWARE=y
CONFIG_SPI_DW_DMA=y
CONFIG_SPI_DW_PCI=y
CONFIG_SPI_DW_MMIO=m
# CONFIG_SPI_HISI_KUNPENG is not set
# CONFIG_SPI_HISI_SFC_V3XX is not set
CONFIG_SPI_GPIO=m
CONFIG_SPI_FSL_LIB=m
CONFIG_SPI_FSL_SPI=m
CONFIG_SPI_MESON_SPICC=y
CONFIG_SPI_MESON_SPIFC=y
# CONFIG_SPI_MICROCHIP_CORE is not set
# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
CONFIG_SPI_OC_TINY=m
# CONFIG_SPI_PCI1XXXX is not set
CONFIG_SPI_PL022=m
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_ROCKCHIP_SFC=y
CONFIG_SPI_SC18IS602=m
CONFIG_SPI_SIFIVE=m
# CONFIG_SPI_SN_F_OSPI is not set
CONFIG_SPI_SUN4I=y
CONFIG_SPI_SUN6I=y
CONFIG_SPI_MXIC=m
CONFIG_SPI_THUNDERX=m
CONFIG_SPI_XCOMM=m
CONFIG_SPI_XILINX=m
CONFIG_SPI_ZYNQMP_GQSPI=m
CONFIG_SPI_AMD=m

#
# SPI Multiplexer support
#
CONFIG_SPI_MUX=m

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=m
CONFIG_SPI_LOOPBACK_TEST=m
CONFIG_SPI_TLE62X0=m
CONFIG_SPI_SLAVE=y
CONFIG_SPI_SLAVE_TIME=m
CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
CONFIG_SPI_DYNAMIC=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set
CONFIG_NTP_PPS=y

#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
# CONFIG_PPS_CLIENT_LDISC is not set
# CONFIG_PPS_CLIENT_GPIO is not set

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
CONFIG_PTP_1588_CLOCK_KVM=m
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
# CONFIG_PTP_1588_CLOCK_FC3W is not set
# CONFIG_PTP_1588_CLOCK_MOCK is not set
# CONFIG_PTP_1588_CLOCK_OCP is not set
# CONFIG_PTP_DFL_TOD is not set
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_PINCTRL_AMD is not set
CONFIG_PINCTRL_AXP209=y
# CONFIG_PINCTRL_AW9523 is not set
# CONFIG_PINCTRL_CY8C95X0 is not set
CONFIG_PINCTRL_MCP23S08_I2C=m
CONFIG_PINCTRL_MCP23S08_SPI=m
CONFIG_PINCTRL_MCP23S08=m
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
# CONFIG_PINCTRL_OCELOT is not set
CONFIG_PINCTRL_RK805=y
CONFIG_PINCTRL_ROCKCHIP=y
# CONFIG_PINCTRL_SCMI is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_PINCTRL_STMFX=m
# CONFIG_PINCTRL_SX150X is not set
# CONFIG_PINCTRL_IMX_SCMI is not set
CONFIG_PINCTRL_MESON=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_PINCTRL_MESON8_PMX=y
CONFIG_PINCTRL_MESON_AXG=y
CONFIG_PINCTRL_MESON_AXG_PMX=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_PINCTRL_MESON_A1=y
CONFIG_PINCTRL_MESON_S4=y
CONFIG_PINCTRL_AMLOGIC_A4=y
CONFIG_PINCTRL_AMLOGIC_C3=y
CONFIG_PINCTRL_AMLOGIC_T7=y

#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers

CONFIG_PINCTRL_SUNXI=y
CONFIG_PINCTRL_SUN4I_A10=y
CONFIG_PINCTRL_SUN5I=y
CONFIG_PINCTRL_SUN6I_A31=y
CONFIG_PINCTRL_SUN6I_A31_R=y
CONFIG_PINCTRL_SUN8I_A23=y
CONFIG_PINCTRL_SUN8I_A33=y
CONFIG_PINCTRL_SUN8I_A83T=y
CONFIG_PINCTRL_SUN8I_A83T_R=y
CONFIG_PINCTRL_SUN8I_A23_R=y
CONFIG_PINCTRL_SUN8I_H3=y
CONFIG_PINCTRL_SUN8I_H3_R=y
CONFIG_PINCTRL_SUN8I_V3S=y
CONFIG_PINCTRL_SUN9I_A80=y
CONFIG_PINCTRL_SUN9I_A80_R=y
CONFIG_PINCTRL_SUN20I_D1=y
CONFIG_PINCTRL_SUN50I_A64=y
CONFIG_PINCTRL_SUN50I_A64_R=y
CONFIG_PINCTRL_SUN50I_A100=y
CONFIG_PINCTRL_SUN50I_A100_R=y
CONFIG_PINCTRL_SUN50I_H5=y
CONFIG_PINCTRL_SUN50I_H6=y
CONFIG_PINCTRL_SUN50I_H6_R=y
CONFIG_PINCTRL_SUN50I_H616=y
CONFIG_PINCTRL_SUN50I_H616_R=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_MAX730X=m

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_FTGPIO010 is not set
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HISI is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_LOGICVC is not set
# CONFIG_GPIO_MB86S7X is not set
CONFIG_GPIO_PL061=y
CONFIG_GPIO_ROCKCHIP=y
# CONFIG_GPIO_SIFIVE is not set
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_XGENE=y
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
CONFIG_GPIO_ADNP=m
# CONFIG_GPIO_FXL6408 is not set
# CONFIG_GPIO_DS4520 is not set
CONFIG_GPIO_GW_PLD=m
CONFIG_GPIO_MAX7300=m
CONFIG_GPIO_MAX732X=m
CONFIG_GPIO_PCA953X=m
# CONFIG_GPIO_PCA953X_IRQ is not set
CONFIG_GPIO_PCA9570=m
CONFIG_GPIO_PCF857X=m
CONFIG_GPIO_TPIC2810=m
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set
# end of PCI GPIO expanders

#
# SPI GPIO expanders
#
CONFIG_GPIO_74X164=m
CONFIG_GPIO_MAX3191X=m
CONFIG_GPIO_MAX7301=m
CONFIG_GPIO_MC33880=m
CONFIG_GPIO_PISOSR=m
CONFIG_GPIO_XRA1403=m
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
# end of USB GPIO expanders

#
# Virtual GPIO drivers
#
CONFIG_GPIO_AGGREGATOR=m
# CONFIG_GPIO_LATCH is not set
CONFIG_GPIO_MOCKUP=m
CONFIG_GPIO_VIRTIO=m
CONFIG_GPIO_SIM=m
# end of Virtual GPIO drivers

#
# GPIO Debugging utilities
#
# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set
# CONFIG_GPIO_VIRTUSER is not set
# end of GPIO Debugging utilities

#
# Other GPIO expanders
#
CONFIG_GPIO_CASCADE=m
CONFIG_W1=m
CONFIG_W1_CON=y

#
# 1-wire Bus Masters
#
# CONFIG_W1_MASTER_AMD_AXI is not set
CONFIG_W1_MASTER_MATROX=m
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
CONFIG_W1_MASTER_GPIO=m
CONFIG_W1_MASTER_SGI=m
# CONFIG_W1_MASTER_UART is not set
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
CONFIG_W1_SLAVE_DS2405=m
CONFIG_W1_SLAVE_DS2408=m
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
CONFIG_W1_SLAVE_DS2805=m
CONFIG_W1_SLAVE_DS2430=m
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
CONFIG_W1_SLAVE_DS2438=m
CONFIG_W1_SLAVE_DS250X=m
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
CONFIG_W1_SLAVE_DS28E17=m
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
# CONFIG_POWER_RESET_ODROID_GO_ULTRA_POWEROFF is not set
CONFIG_POWER_RESET_LTC2952=y
CONFIG_POWER_RESET_REGULATOR=y
CONFIG_POWER_RESET_RESTART=y
CONFIG_POWER_RESET_VEXPRESS=y
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
CONFIG_NVMEM_REBOOT_MODE=y
# CONFIG_POWER_SEQUENCING is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_IP5XXX_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SAMSUNG_SDI is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_CHARGER_AXP20X is not set
# CONFIG_BATTERY_AXP20X is not set
CONFIG_AXP20X_POWER=y
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_BATTERY_MAX1720X is not set
# CONFIG_BATTERY_MAX1721X is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
CONFIG_CHARGER_GPIO=m
CONFIG_CHARGER_MANAGER=m
CONFIG_CHARGER_LT3651=m
CONFIG_CHARGER_LTC4162L=m
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_MAX77976 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_BQ25980 is not set
# CONFIG_CHARGER_BQ256XX is not set
CONFIG_CHARGER_RK817=y
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_BATTERY_GOLDFISH is not set
# CONFIG_BATTERY_RT5033 is not set
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_RT9467 is not set
# CONFIG_CHARGER_RT9471 is not set
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
# CONFIG_BATTERY_UG3105 is not set
# CONFIG_FUEL_GAUGE_MM8013 is not set
CONFIG_HWMON=y
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM1177 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7310 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_AHT10 is not set
# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
# CONFIG_SENSORS_AS370 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set
# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
CONFIG_SENSORS_ARM_SCMI=y
CONFIG_SENSORS_ARM_SCPI=y
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_CHIPCAP2 is not set
# CONFIG_SENSORS_CORSAIR_CPRO is not set
# CONFIG_SENSORS_CORSAIR_PSU is not set
# CONFIG_SENSORS_DRIVETEMP is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_I5K_AMB is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_FTSTEUTATES is not set
# CONFIG_SENSORS_GIGABYTE_WATERFORCE is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_G762 is not set
CONFIG_SENSORS_GPIO_FAN=m
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_HS3001 is not set
# CONFIG_SENSORS_IIO_HWMON is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_POWERZ is not set
# CONFIG_SENSORS_POWR1220 is not set
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LTC2945 is not set
# CONFIG_SENSORS_LTC2947_I2C is not set
# CONFIG_SENSORS_LTC2947_SPI is not set
# CONFIG_SENSORS_LTC2990 is not set
# CONFIG_SENSORS_LTC2991 is not set
# CONFIG_SENSORS_LTC2992 is not set
# CONFIG_SENSORS_LTC4151 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4222 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LTC4260 is not set
# CONFIG_SENSORS_LTC4261 is not set
# CONFIG_SENSORS_LTC4282 is not set
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX127 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX197 is not set
# CONFIG_SENSORS_MAX31722 is not set
# CONFIG_SENSORS_MAX31730 is not set
# CONFIG_SENSORS_MAX31760 is not set
# CONFIG_MAX31827 is not set
# CONFIG_SENSORS_MAX6620 is not set
# CONFIG_SENSORS_MAX6621 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MAX6697 is not set
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MC34VR500 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_TPS23861 is not set
# CONFIG_SENSORS_MR75203 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LM95234 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_NCT6683 is not set
# CONFIG_SENSORS_NCT6775 is not set
# CONFIG_SENSORS_NCT6775_I2C is not set
# CONFIG_SENSORS_NCT7802 is not set
# CONFIG_SENSORS_NCT7904 is not set
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
# CONFIG_SENSORS_NZXT_KRAKEN3 is not set
# CONFIG_SENSORS_NZXT_SMART2 is not set
# CONFIG_SENSORS_OCC_P8_I2C is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_PMBUS is not set
# CONFIG_SENSORS_PT5161L is not set
CONFIG_SENSORS_PWM_FAN=m
# CONFIG_SENSORS_SBTSI is not set
# CONFIG_SENSORS_SBRMI is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHT4x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC2305 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA238 is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_SPD5118 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_TMP464 is not set
# CONFIG_SENSORS_TMP513 is not set
# CONFIG_SENSORS_VEXPRESS is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_XGENE is not set

#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
# CONFIG_THERMAL_DEBUGFS is not set
# CONFIG_THERMAL_CORE_TESTING is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
# CONFIG_THERMAL_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
# CONFIG_THERMAL_EMULATION is not set
CONFIG_THERMAL_MMIO=y
CONFIG_SUN8I_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_AMLOGIC_THERMAL=y
CONFIG_GENERIC_ADC_THERMAL=m
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set
# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=m
# CONFIG_GPIO_WATCHDOG is not set
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_XILINX_WINDOW_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
CONFIG_ARM_SP805_WATCHDOG=m
CONFIG_ARM_SBSA_WATCHDOG=y
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=m
CONFIG_SUNXI_WATCHDOG=m
# CONFIG_MAX63XX_WATCHDOG is not set
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_WATCHDOG=m
# CONFIG_ARM_SMC_WATCHDOG is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_HP_WATCHDOG is not set
# CONFIG_MEN_A21_WDT is not set

#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
CONFIG_BCMA_HOST_PCI=y
CONFIG_BCMA_HOST_SOC=y
CONFIG_BCMA_DRIVER_PCI=y
CONFIG_BCMA_SFLASH=y
CONFIG_BCMA_DRIVER_GMAC_CMN=y
CONFIG_BCMA_DRIVER_GPIO=y
CONFIG_BCMA_DEBUG=y

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ADP5585 is not set
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_SMPRO is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
CONFIG_MFD_AC100=y
CONFIG_MFD_AC200=m
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
# CONFIG_MFD_CS42L43_I2C is not set
# CONFIG_MFD_MADERA is not set
# CONFIG_MFD_MAX5970 is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_88PM886_PMIC is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77541 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77714 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6370 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_MFD_OCELOT is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_NTXEC is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_SY7636A is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT4831 is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RT5120 is not set
# CONFIG_MFD_RC5T583 is not set
CONFIG_MFD_RK8XX=y
CONFIG_MFD_RK8XX_I2C=y
CONFIG_MFD_RK8XX_SPI=y
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
CONFIG_MFD_SIMPLE_MFD_I2C=m
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SUN6I_PRCM=y
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS65219 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS6594_I2C is not set
# CONFIG_MFD_TPS6594_SPI is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TQMX86 is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
# CONFIG_MFD_ROHM_BD71828 is not set
# CONFIG_MFD_ROHM_BD957XMUF is not set
# CONFIG_MFD_ROHM_BD96801 is not set
# CONFIG_MFD_STPMIC1 is not set
CONFIG_MFD_STMFX=m
# CONFIG_MFD_ATC260X_I2C is not set
# CONFIG_MFD_KHADAS_MCU is not set
# CONFIG_MFD_QCOM_PM8008 is not set
# CONFIG_MFD_CS40L50_I2C is not set
# CONFIG_MFD_CS40L50_SPI is not set
# CONFIG_MFD_VEXPRESS_SYSREG is not set
# CONFIG_RAVE_SP_CORE is not set
# CONFIG_MFD_INTEL_M10_BMC_SPI is not set
# CONFIG_MFD_INTEL_M10_BMC_PMCI is not set
# CONFIG_MFD_RSMU_I2C is not set
# CONFIG_MFD_RSMU_SPI is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_NETLINK_EVENTS is not set
# CONFIG_REGULATOR_88PG86X is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_AD5398 is not set
CONFIG_REGULATOR_ARM_SCMI=y
# CONFIG_REGULATOR_AW37503 is not set
CONFIG_REGULATOR_AXP20X=y
# CONFIG_REGULATOR_DA9121 is not set
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_FAN53880=y
CONFIG_REGULATOR_GPIO=y
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_LP8755 is not set
# CONFIG_REGULATOR_LTC3589 is not set
# CONFIG_REGULATOR_LTC3676 is not set
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX77503 is not set
# CONFIG_REGULATOR_MAX77857 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8893 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_MAX8973 is not set
# CONFIG_REGULATOR_MAX20086 is not set
# CONFIG_REGULATOR_MAX20411 is not set
# CONFIG_REGULATOR_MAX77826 is not set
# CONFIG_REGULATOR_MCP16502 is not set
# CONFIG_REGULATOR_MP5416 is not set
# CONFIG_REGULATOR_MP8859 is not set
# CONFIG_REGULATOR_MP886X is not set
# CONFIG_REGULATOR_MPQ7920 is not set
# CONFIG_REGULATOR_MT6311 is not set
# CONFIG_REGULATOR_MT6315 is not set
# CONFIG_REGULATOR_PCA9450 is not set
# CONFIG_REGULATOR_PF8X00 is not set
# CONFIG_REGULATOR_PFUZE100 is not set
# CONFIG_REGULATOR_PV88060 is not set
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
CONFIG_REGULATOR_PWM=y
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
# CONFIG_REGULATOR_RAA215300 is not set
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
CONFIG_REGULATOR_RK808=y
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RT4803 is not set
# CONFIG_REGULATOR_RT5190A is not set
# CONFIG_REGULATOR_RT5739 is not set
# CONFIG_REGULATOR_RT5759 is not set
# CONFIG_REGULATOR_RT6160 is not set
# CONFIG_REGULATOR_RT6190 is not set
# CONFIG_REGULATOR_RT6245 is not set
# CONFIG_REGULATOR_RTQ2134 is not set
# CONFIG_REGULATOR_RTMV20 is not set
# CONFIG_REGULATOR_RTQ6752 is not set
# CONFIG_REGULATOR_RTQ2208 is not set
# CONFIG_REGULATOR_SLG51000 is not set
CONFIG_REGULATOR_SUN20I=y
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
# CONFIG_REGULATOR_SY8827N is not set
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS6286X is not set
# CONFIG_REGULATOR_TPS6287X is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_TPS6524X is not set
CONFIG_REGULATOR_VCTRL=y
# CONFIG_REGULATOR_VEXPRESS is not set
# CONFIG_REGULATOR_QCOM_LABIBB is not set
CONFIG_RC_CORE=y
# CONFIG_BPF_LIRC_MODE2 is not set
CONFIG_LIRC=y
CONFIG_RC_MAP=y
CONFIG_RC_DECODERS=y
CONFIG_IR_IMON_DECODER=m
CONFIG_IR_JVC_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
CONFIG_IR_RCMM_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_XMP_DECODER=m
CONFIG_RC_DEVICES=y
# CONFIG_IR_ENE is not set
# CONFIG_IR_FINTEK is not set
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_GPIO_TX=m
CONFIG_IR_HIX5HD2=m
CONFIG_IR_IGORPLUGUSB=m
CONFIG_IR_IGUANA=m
CONFIG_IR_IMON=m
CONFIG_IR_IMON_RAW=m
# CONFIG_IR_ITE_CIR is not set
CONFIG_IR_MCEUSB=m
CONFIG_IR_MESON=m
CONFIG_IR_MESON_TX=m
# CONFIG_IR_NUVOTON is not set
CONFIG_IR_PWM_TX=m
CONFIG_IR_REDRAT3=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m
CONFIG_IR_SUNXI=m
CONFIG_IR_TOY=m
CONFIG_IR_TTUSBIR=m
CONFIG_RC_ATI_REMOTE=m
CONFIG_RC_LOOPBACK=m
CONFIG_RC_XBOX_DVD=m
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y

#
# CEC support
#
CONFIG_MEDIA_CEC_RC=y
CONFIG_MEDIA_CEC_SUPPORT=y
CONFIG_CEC_CH7322=m
CONFIG_CEC_MESON_AO=y
CONFIG_CEC_MESON_G12A_AO=y
# CONFIG_CEC_GPIO is not set
# CONFIG_USB_EXTRON_DA_HD_4K_PLUS_CEC is not set
CONFIG_USB_PULSE8_CEC=m
CONFIG_USB_RAINSHADOW_CEC=m
# end of CEC support

CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_SUPPORT_FILTER=y
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_SDR_SUPPORT is not set
CONFIG_MEDIA_PLATFORM_SUPPORT=y
# CONFIG_MEDIA_TEST_SUPPORT is not set
# end of Media device types

CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CONTROLLER=y

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_ADV_DEBUG=y
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_H264=m
CONFIG_V4L2_VP9=m
CONFIG_V4L2_MEM2MEM_DEV=m
# CONFIG_V4L2_FLASH_LED_CLASS is not set
CONFIG_V4L2_FWNODE=y
CONFIG_V4L2_ASYNC=y
CONFIG_V4L2_CCI=m
CONFIG_V4L2_CCI_I2C=m
# end of Video4Linux options

#
# Media controller options
#
# end of Media controller options

#
# Media drivers
#

#
# Drivers filtered as selected at 'Filter media drivers'
#

#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_GSPCA=m
CONFIG_USB_GSPCA_BENQ=m
CONFIG_USB_GSPCA_CONEX=m
CONFIG_USB_GSPCA_CPIA1=m
CONFIG_USB_GSPCA_DTCS033=m
CONFIG_USB_GSPCA_ETOMS=m
CONFIG_USB_GSPCA_FINEPIX=m
CONFIG_USB_GSPCA_JEILINJ=m
CONFIG_USB_GSPCA_JL2005BCD=m
CONFIG_USB_GSPCA_KINECT=m
CONFIG_USB_GSPCA_KONICA=m
CONFIG_USB_GSPCA_MARS=m
CONFIG_USB_GSPCA_MR97310A=m
CONFIG_USB_GSPCA_NW80X=m
CONFIG_USB_GSPCA_OV519=m
CONFIG_USB_GSPCA_OV534=m
CONFIG_USB_GSPCA_OV534_9=m
CONFIG_USB_GSPCA_PAC207=m
CONFIG_USB_GSPCA_PAC7302=m
CONFIG_USB_GSPCA_PAC7311=m
CONFIG_USB_GSPCA_SE401=m
CONFIG_USB_GSPCA_SN9C2028=m
CONFIG_USB_GSPCA_SN9C20X=m
CONFIG_USB_GSPCA_SONIXB=m
CONFIG_USB_GSPCA_SONIXJ=m
CONFIG_USB_GSPCA_SPCA1528=m
CONFIG_USB_GSPCA_SPCA500=m
CONFIG_USB_GSPCA_SPCA501=m
CONFIG_USB_GSPCA_SPCA505=m
CONFIG_USB_GSPCA_SPCA506=m
CONFIG_USB_GSPCA_SPCA508=m
CONFIG_USB_GSPCA_SPCA561=m
CONFIG_USB_GSPCA_SQ905=m
CONFIG_USB_GSPCA_SQ905C=m
CONFIG_USB_GSPCA_SQ930X=m
CONFIG_USB_GSPCA_STK014=m
CONFIG_USB_GSPCA_STK1135=m
CONFIG_USB_GSPCA_STV0680=m
CONFIG_USB_GSPCA_SUNPLUS=m
CONFIG_USB_GSPCA_T613=m
CONFIG_USB_GSPCA_TOPRO=m
CONFIG_USB_GSPCA_TOUPTEK=m
CONFIG_USB_GSPCA_TV8532=m
CONFIG_USB_GSPCA_VC032X=m
CONFIG_USB_GSPCA_VICAM=m
CONFIG_USB_GSPCA_XIRLINK_CIT=m
CONFIG_USB_GSPCA_ZC3XX=m
CONFIG_USB_GL860=m
CONFIG_USB_M5602=m
CONFIG_USB_STV06XX=m
CONFIG_USB_PWC=m
# CONFIG_USB_PWC_DEBUG is not set
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_USB_S2255=m
CONFIG_VIDEO_USBTV=m
CONFIG_USB_VIDEO_CLASS=m
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y

#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=m
CONFIG_VIDEO_EM28XX_V4L2=m
CONFIG_VIDEO_EM28XX_ALSA=m
CONFIG_VIDEO_EM28XX_RC=m
# CONFIG_MEDIA_PCI_SUPPORT is not set
CONFIG_MEDIA_PLATFORM_DRIVERS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
CONFIG_VIDEO_MUX=m

#
# Allegro DVT media platform drivers
#

#
# Amlogic media platform drivers
#
# CONFIG_VIDEO_C3_ISP is not set
# CONFIG_VIDEO_C3_MIPI_ADAPTER is not set
# CONFIG_VIDEO_C3_MIPI_CSI2 is not set
CONFIG_VIDEO_MESON_GE2D=m

#
# Amphion drivers
#

#
# Aspeed media platform drivers
#

#
# Atmel media platform drivers
#

#
# Cadence media platform drivers
#
# CONFIG_VIDEO_CADENCE_CSI2RX is not set
# CONFIG_VIDEO_CADENCE_CSI2TX is not set

#
# Chips&Media media platform drivers
#

#
# Intel media platform drivers
#

#
# Marvell media platform drivers
#
# CONFIG_VIDEO_CAFE_CCIC is not set

#
# Mediatek media platform drivers
#

#
# Microchip Technology, Inc. media platform drivers
#

#
# Nuvoton media platform drivers
#

#
# NVidia media platform drivers
#

#
# NXP media platform drivers
#

#
# Qualcomm media platform drivers
#

#
# Raspberry Pi media platform drivers
#

#
# Renesas media platform drivers
#

#
# Rockchip media platform drivers
#
CONFIG_VIDEO_ROCKCHIP_RGA=m
CONFIG_VIDEO_ROCKCHIP_ISP1=m
CONFIG_VIDEO_ROCKCHIP_VDEC=m

#
# Samsung media platform drivers
#

#
# STMicroelectronics media platform drivers
#

#
# Sunxi media platform drivers
#
CONFIG_VIDEO_SUN4I_CSI=m
CONFIG_VIDEO_SUN6I_CSI=m
CONFIG_VIDEO_SUN6I_MIPI_CSI2=m
CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m
CONFIG_VIDEO_SUN8I_DEINTERLACE=m
CONFIG_VIDEO_SUN8I_ROTATE=m
CONFIG_VIDEO_SYNOPSYS_HDMIRX=m
# CONFIG_VIDEO_SYNOPSYS_HDMIRX_LOAD_DEFAULT_EDID is not set

#
# Texas Instruments drivers
#

#
# Verisilicon media platform drivers
#
# CONFIG_VIDEO_HANTRO is not set

#
# VIA media platform drivers
#

#
# Xilinx media platform drivers
#
# CONFIG_VIDEO_XILINX is not set
CONFIG_UVC_COMMON=m
CONFIG_VIDEO_TVEEPROM=m
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_VIDEOBUF2_DMA_SG=m
# end of Media drivers

#
# Media ancillary drivers
#

#
# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
#
CONFIG_VIDEO_IR_I2C=m
CONFIG_VIDEO_CAMERA_SENSOR=y
CONFIG_VIDEO_APTINA_PLL=m
CONFIG_VIDEO_CCS_PLL=m
# CONFIG_VIDEO_ALVIUM_CSI2 is not set
CONFIG_VIDEO_AR0521=m
# CONFIG_VIDEO_GC0308 is not set
# CONFIG_VIDEO_GC05A2 is not set
# CONFIG_VIDEO_GC08A3 is not set
# CONFIG_VIDEO_GC2145 is not set
CONFIG_VIDEO_HI556=m
CONFIG_VIDEO_HI846=m
CONFIG_VIDEO_HI847=m
CONFIG_VIDEO_IMX208=m
CONFIG_VIDEO_IMX214=m
CONFIG_VIDEO_IMX219=m
CONFIG_VIDEO_IMX258=m
CONFIG_VIDEO_IMX274=m
# CONFIG_VIDEO_IMX283 is not set
CONFIG_VIDEO_IMX290=m
# CONFIG_VIDEO_IMX296 is not set
CONFIG_VIDEO_IMX319=m
CONFIG_VIDEO_IMX334=m
CONFIG_VIDEO_IMX335=m
CONFIG_VIDEO_IMX355=m
CONFIG_VIDEO_IMX412=m
# CONFIG_VIDEO_IMX415 is not set
CONFIG_VIDEO_MAX9271_LIB=m
CONFIG_VIDEO_MT9M001=m
CONFIG_VIDEO_MT9M111=m
# CONFIG_VIDEO_MT9M114 is not set
CONFIG_VIDEO_MT9P031=m
CONFIG_VIDEO_MT9T112=m
CONFIG_VIDEO_MT9V011=m
CONFIG_VIDEO_MT9V032=m
CONFIG_VIDEO_MT9V111=m
CONFIG_VIDEO_OG01A1B=m
# CONFIG_VIDEO_OV01A10 is not set
CONFIG_VIDEO_OV02A10=m
CONFIG_VIDEO_OV08D10=m
# CONFIG_VIDEO_OV08X40 is not set
CONFIG_VIDEO_OV13858=m
CONFIG_VIDEO_OV13B10=m
CONFIG_VIDEO_OV2640=m
CONFIG_VIDEO_OV2659=m
CONFIG_VIDEO_OV2680=m
CONFIG_VIDEO_OV2685=m
CONFIG_VIDEO_OV2740=m
# CONFIG_VIDEO_OV4689 is not set
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_OV5647=m
CONFIG_VIDEO_OV5648=m
CONFIG_VIDEO_OV5670=m
CONFIG_VIDEO_OV5675=m
CONFIG_VIDEO_OV5693=m
CONFIG_VIDEO_OV5695=m
# CONFIG_VIDEO_OV64A40 is not set
CONFIG_VIDEO_OV6650=m
CONFIG_VIDEO_OV7251=m
CONFIG_VIDEO_OV7640=m
CONFIG_VIDEO_OV7670=m
CONFIG_VIDEO_OV772X=m
CONFIG_VIDEO_OV7740=m
CONFIG_VIDEO_OV8856=m
# CONFIG_VIDEO_OV8858 is not set
CONFIG_VIDEO_OV8865=m
CONFIG_VIDEO_OV9282=m
CONFIG_VIDEO_OV9640=m
CONFIG_VIDEO_OV9650=m
CONFIG_VIDEO_OV9734=m
CONFIG_VIDEO_RDACM20=m
CONFIG_VIDEO_RDACM21=m
CONFIG_VIDEO_RJ54N1=m
CONFIG_VIDEO_S5C73M3=m
CONFIG_VIDEO_S5K5BAF=m
CONFIG_VIDEO_S5K6A3=m
# CONFIG_VIDEO_VGXY61 is not set
CONFIG_VIDEO_CCS=m
CONFIG_VIDEO_ET8EK8=m

#
# Camera ISPs
#
# CONFIG_VIDEO_THP7312 is not set
# end of Camera ISPs

#
# Lens drivers
#
CONFIG_VIDEO_AD5820=m
CONFIG_VIDEO_AK7375=m
CONFIG_VIDEO_DW9714=m
# CONFIG_VIDEO_DW9719 is not set
CONFIG_VIDEO_DW9768=m
CONFIG_VIDEO_DW9807_VCM=m
# end of Lens drivers

#
# Flash devices
#
CONFIG_VIDEO_ADP1653=m
CONFIG_VIDEO_LM3560=m
CONFIG_VIDEO_LM3646=m
# end of Flash devices

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_CS3308=m
CONFIG_VIDEO_CS5345=m
CONFIG_VIDEO_CS53L32A=m
CONFIG_VIDEO_MSP3400=m
CONFIG_VIDEO_SONY_BTF_MPX=m
CONFIG_VIDEO_TDA1997X=m
CONFIG_VIDEO_TDA7432=m
CONFIG_VIDEO_TDA9840=m
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
CONFIG_VIDEO_TLV320AIC23B=m
CONFIG_VIDEO_TVAUDIO=m
CONFIG_VIDEO_UDA1342=m
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_WM8739=m
CONFIG_VIDEO_WM8775=m
# end of Audio decoders, processors and mixers

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders

#
# Video decoders
#
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_ADV7183=m
CONFIG_VIDEO_ADV748X=m
CONFIG_VIDEO_ADV7604=m
CONFIG_VIDEO_ADV7604_CEC=y
CONFIG_VIDEO_ADV7842=m
CONFIG_VIDEO_ADV7842_CEC=y
CONFIG_VIDEO_BT819=m
CONFIG_VIDEO_BT856=m
CONFIG_VIDEO_BT866=m
CONFIG_VIDEO_ISL7998X=m
CONFIG_VIDEO_KS0127=m
CONFIG_VIDEO_MAX9286=m
CONFIG_VIDEO_ML86V7667=m
CONFIG_VIDEO_SAA7110=m
CONFIG_VIDEO_SAA711X=m
CONFIG_VIDEO_TC358743=m
CONFIG_VIDEO_TC358743_CEC=y
# CONFIG_VIDEO_TC358746 is not set
CONFIG_VIDEO_TVP514X=m
CONFIG_VIDEO_TVP5150=m
CONFIG_VIDEO_TVP7002=m
CONFIG_VIDEO_TW2804=m
# CONFIG_VIDEO_TW9900 is not set
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=m
CONFIG_VIDEO_TW9910=m
CONFIG_VIDEO_VPX3220=m

#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=m
CONFIG_VIDEO_CX25840=m
# end of Video decoders

#
# Video encoders
#
CONFIG_VIDEO_ADV7170=m
CONFIG_VIDEO_ADV7175=m
CONFIG_VIDEO_ADV7343=m
CONFIG_VIDEO_ADV7393=m
CONFIG_VIDEO_ADV7511=m
CONFIG_VIDEO_ADV7511_CEC=y
CONFIG_VIDEO_AK881X=m
CONFIG_VIDEO_SAA7127=m
CONFIG_VIDEO_SAA7185=m
CONFIG_VIDEO_THS8200=m
# end of Video encoders

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
CONFIG_VIDEO_UPD64083=m
# end of Video improvement chips

#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips

#
# SDR tuner chips
#
# end of SDR tuner chips

#
# Miscellaneous helper chips
#
CONFIG_VIDEO_I2C=m
CONFIG_VIDEO_M52790=m
CONFIG_VIDEO_ST_MIPID02=m
CONFIG_VIDEO_THS7303=m
# end of Miscellaneous helper chips

#
# Video serializers and deserializers
#
# CONFIG_VIDEO_DS90UB913 is not set
# CONFIG_VIDEO_DS90UB953 is not set
# CONFIG_VIDEO_DS90UB960 is not set
# CONFIG_VIDEO_MAX96714 is not set
# CONFIG_VIDEO_MAX96717 is not set
# end of Video serializers and deserializers

#
# Media SPI Adapters
#
CONFIG_VIDEO_GS1662=m
# end of Media SPI Adapters
# end of Media ancillary drivers

#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
CONFIG_SCREEN_INFO=y
CONFIG_VIDEO=y
CONFIG_AUXDISPLAY=y
CONFIG_CHARLCD=m
CONFIG_HD44780_COMMON=m
CONFIG_HD44780=m
CONFIG_LCD2S=m
# CONFIG_PANEL_CHANGE_MESSAGE is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_LINEDISP=m
CONFIG_IMG_ASCII_LCD=m
CONFIG_HT16K33=m
# CONFIG_MAX6959 is not set
# CONFIG_SEG_LED_GPIO is not set
CONFIG_TM1628=m
CONFIG_OPENVFD=m
CONFIG_DRM=y
CONFIG_DRM_MIPI_DBI=m
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_DEBUG_MM is not set
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_PANIC is not set
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
CONFIG_DRM_CLIENT_SELECTION=y
CONFIG_DRM_CLIENT_SETUP=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=300
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
CONFIG_DRM_DISPLAY_DP_AUX_BUS=m
CONFIG_DRM_DISPLAY_HELPER=y
CONFIG_DRM_BRIDGE_CONNECTOR=y
# CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set
# CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set
CONFIG_DRM_DISPLAY_DP_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER=y
CONFIG_DRM_TTM=m
CONFIG_DRM_EXEC=m
CONFIG_DRM_GPUVM=m
CONFIG_DRM_TTM_HELPER=m
CONFIG_DRM_GEM_DMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=m
CONFIG_DRM_SCHED=m

#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips

#
# ARM devices
#
CONFIG_DRM_HDLCD=m
CONFIG_DRM_HDLCD_SHOW_UNDERRUN=y
CONFIG_DRM_MALI_DISPLAY=m
CONFIG_DRM_KOMEDA=m
# end of ARM devices

# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
# CONFIG_DRM_XE is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
CONFIG_DRM_ROCKCHIP=m
CONFIG_ROCKCHIP_VOP=y
CONFIG_ROCKCHIP_VOP2=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_HDMI_QP=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI2=y
CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_ROCKCHIP_LVDS=y
CONFIG_ROCKCHIP_RGB=y
CONFIG_ROCKCHIP_RK3066_HDMI=y
# CONFIG_DRM_VMWGFX is not set
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
CONFIG_DRM_SUN4I=y
CONFIG_DRM_SUN6I_DSI=y
CONFIG_DRM_SUN8I_DW_HDMI=y
CONFIG_DRM_SUN8I_MIXER=y
CONFIG_DRM_SUN8I_TCON_TOP=y
CONFIG_DRM_QXL=m
CONFIG_DRM_VIRTIO_GPU=m
CONFIG_DRM_VIRTIO_GPU_KMS=y
CONFIG_DRM_PANEL=y

#
# Display Panels
#
CONFIG_DRM_PANEL_ABT_Y030XX067A=m
CONFIG_DRM_PANEL_ARM_VERSATILE=m
CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set
CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
# CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 is not set
CONFIG_DRM_PANEL_EBBG_FT8719=m
CONFIG_DRM_PANEL_ELIDA_KD35T133=m
CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
CONFIG_DRM_PANEL_DSI_CM=m
CONFIG_DRM_PANEL_LVDS=m
# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set
# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set
# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set
CONFIG_DRM_PANEL_ILITEK_IL9322=m
CONFIG_DRM_PANEL_ILITEK_ILI9341=m
# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set
CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set
CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set
CONFIG_DRM_PANEL_JDI_LT070ME05000=m
CONFIG_DRM_PANEL_JDI_R63452=m
CONFIG_DRM_PANEL_KHADAS_TS050=m
CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set
CONFIG_DRM_PANEL_LG_LB035Q02=m
CONFIG_DRM_PANEL_LG_LG4573=m
# CONFIG_DRM_PANEL_LG_SW43408 is not set
# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set
CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
CONFIG_DRM_PANEL_NOVATEK_NT35510=m
CONFIG_DRM_PANEL_NOVATEK_NT35560=m
CONFIG_DRM_PANEL_NOVATEK_NT35950=m
# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set
CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set
CONFIG_DRM_PANEL_NOVATEK_NT39016=m
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set
CONFIG_DRM_PANEL_RONBO_RB070D30=m
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set
CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set
CONFIG_DRM_PANEL_EDP=m
CONFIG_DRM_PANEL_SIMPLE=m
# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set
CONFIG_DRM_PANEL_TDO_TL070WSH30=m
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
CONFIG_DRM_PANEL_TPO_TPG110=m
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set
CONFIG_DRM_PANEL_VISIONOX_RM69299=m
# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set
CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y
CONFIG_DRM_AUX_BRIDGE=m

#
# Display Interface Bridges
#
# CONFIG_DRM_CHIPONE_ICN6211 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
CONFIG_DRM_DISPLAY_CONNECTOR=y
# CONFIG_DRM_ITE_IT6505 is not set
# CONFIG_DRM_LONTIUM_LT8912B is not set
# CONFIG_DRM_LONTIUM_LT9211 is not set
# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LONTIUM_LT9611UXC is not set
# CONFIG_DRM_ITE_IT66121 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_SAMSUNG_DSIM is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
CONFIG_DRM_SIMPLE_BRIDGE=m
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_DLPC3433 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI83 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
CONFIG_DRM_ANALOGIX_DP=m
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=y
CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
CONFIG_DRM_DW_HDMI_CEC=m
CONFIG_DRM_DW_HDMI_QP=m
CONFIG_DRM_DW_MIPI_DSI=y
CONFIG_DRM_DW_MIPI_DSI2=m
# end of Display Interface Bridges

CONFIG_DRM_ETNAVIV=m
CONFIG_DRM_ETNAVIV_THERMAL=y
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
# CONFIG_DRM_LOGICVC is not set
CONFIG_DRM_MESON=y
CONFIG_DRM_MESON_DW_HDMI=y
CONFIG_DRM_MESON_DW_MIPI_DSI=y
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_BOCHS is not set
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_GM12U320 is not set
# CONFIG_DRM_PANEL_MIPI_DBI is not set
# CONFIG_DRM_SIMPLEDRM is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9163 is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_DRM_PL111 is not set
CONFIG_DRM_LIMA=m
CONFIG_DRM_PANFROST=m
CONFIG_DRM_PANTHOR=m
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_GUD is not set
CONFIG_DRM_SSD130X=m
CONFIG_DRM_SSD130X_I2C=m
CONFIG_DRM_SSD130X_SPI=m
# CONFIG_DRM_POWERVR is not set
# CONFIG_DRM_WERROR is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y

#
# Frame buffer Devices
#
CONFIG_FB=y
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_UVESA is not set
CONFIG_FB_EFI=y
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
CONFIG_FB_SIMPLE=y
# CONFIG_FB_SSD1307 is not set
# CONFIG_FB_SM712 is not set
CONFIG_FB_CORE=y
CONFIG_FB_NOTIFY=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_DEVICE=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYSMEM_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_DMAMEM_HELPERS=y
CONFIG_FB_DMAMEM_HELPERS_DEFERRED=y
CONFIG_FB_IOMEM_FOPS=y
CONFIG_FB_IOMEM_HELPERS=y
CONFIG_FB_SYSMEM_HELPERS=y
CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
CONFIG_FB_BACKLIGHT=m
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=m
CONFIG_LCD_L4F00242T03=m
CONFIG_LCD_LMS283GF05=m
CONFIG_LCD_LTV350QV=m
CONFIG_LCD_ILI922X=m
CONFIG_LCD_ILI9320=m
CONFIG_LCD_TDO24M=m
CONFIG_LCD_VGG2432A4=m
CONFIG_LCD_PLATFORM=m
CONFIG_LCD_AMS369FG06=m
CONFIG_LCD_LMS501KF03=m
CONFIG_LCD_HX8357=m
CONFIG_LCD_OTM3225A=m
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_KTD253=m
# CONFIG_BACKLIGHT_KTD2801 is not set
# CONFIG_BACKLIGHT_KTZ8866 is not set
CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_QCOM_WLED=m
CONFIG_BACKLIGHT_ADP8860=m
CONFIG_BACKLIGHT_ADP8870=m
# CONFIG_BACKLIGHT_LM3509 is not set
CONFIG_BACKLIGHT_LM3630A=m
CONFIG_BACKLIGHT_LM3639=m
CONFIG_BACKLIGHT_LP855X=m
# CONFIG_BACKLIGHT_MP3309C is not set
CONFIG_BACKLIGHT_GPIO=y
CONFIG_BACKLIGHT_LV5207LP=m
CONFIG_BACKLIGHT_BD6107=m
CONFIG_BACKLIGHT_ARCXCNN=m
CONFIG_BACKLIGHT_LED=y
# end of Backlight & LCD device support

CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
# end of Console display driver support

CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
# end of Graphics support

CONFIG_DRM_ACCEL=y
CONFIG_DRM_ACCEL_QAIC=m
CONFIG_DRM_ACCEL_ROCKET=m
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=m
CONFIG_SND_RAWMIDI=m
CONFIG_SND_UMP=m
CONFIG_SND_UMP_LEGACY_RAWMIDI=y
CONFIG_SND_COMPRESS_OFFLOAD=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_OSSEMUL is not set
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
# CONFIG_SND_VERBOSE_PROCFS is not set
CONFIG_SND_CTL_FAST_LOOKUP=y
# CONFIG_SND_DEBUG is not set
# CONFIG_SND_CTL_INPUT_VALIDATION is not set
# CONFIG_SND_UTIMER is not set
CONFIG_SND_VMASTER=y
# CONFIG_SND_SEQUENCER is not set
CONFIG_SND_MPU401_UART=m
CONFIG_SND_AC97_CODEC=m
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
# CONFIG_SND_PCMTEST is not set
CONFIG_SND_MTPAV=m
CONFIG_SND_SERIAL_U16550=m
CONFIG_SND_SERIAL_GENERIC=m
CONFIG_SND_MPU401=m
# CONFIG_SND_AC97_POWER_SAVE is not set
CONFIG_SND_PCI=y
# CONFIG_SND_AD1889 is not set
# CONFIG_SND_ALS300 is not set
# CONFIG_SND_ALI5451 is not set
# CONFIG_SND_ATIIXP is not set
# CONFIG_SND_ATIIXP_MODEM is not set
# CONFIG_SND_AU8810 is not set
# CONFIG_SND_AU8820 is not set
# CONFIG_SND_AU8830 is not set
# CONFIG_SND_AW2 is not set
# CONFIG_SND_AZT3328 is not set
# CONFIG_SND_BT87X is not set
# CONFIG_SND_CA0106 is not set
# CONFIG_SND_CMIPCI is not set
# CONFIG_SND_OXYGEN is not set
# CONFIG_SND_CS4281 is not set
# CONFIG_SND_CS46XX is not set
# CONFIG_SND_CTXFI is not set
# CONFIG_SND_DARLA20 is not set
# CONFIG_SND_GINA20 is not set
# CONFIG_SND_LAYLA20 is not set
# CONFIG_SND_DARLA24 is not set
# CONFIG_SND_GINA24 is not set
# CONFIG_SND_LAYLA24 is not set
# CONFIG_SND_MONA is not set
# CONFIG_SND_MIA is not set
# CONFIG_SND_ECHO3G is not set
# CONFIG_SND_INDIGO is not set
# CONFIG_SND_INDIGOIO is not set
# CONFIG_SND_INDIGODJ is not set
# CONFIG_SND_INDIGOIOX is not set
# CONFIG_SND_INDIGODJX is not set
# CONFIG_SND_EMU10K1 is not set
# CONFIG_SND_EMU10K1X is not set
# CONFIG_SND_ENS1370 is not set
# CONFIG_SND_ENS1371 is not set
# CONFIG_SND_ES1938 is not set
# CONFIG_SND_ES1968 is not set
# CONFIG_SND_FM801 is not set
# CONFIG_SND_HDSP is not set
# CONFIG_SND_HDSPM is not set
# CONFIG_SND_ICE1712 is not set
# CONFIG_SND_ICE1724 is not set
# CONFIG_SND_INTEL8X0 is not set
# CONFIG_SND_INTEL8X0M is not set
# CONFIG_SND_KORG1212 is not set
# CONFIG_SND_LOLA is not set
# CONFIG_SND_LX6464ES is not set
# CONFIG_SND_MAESTRO3 is not set
# CONFIG_SND_MIXART is not set
# CONFIG_SND_NM256 is not set
# CONFIG_SND_PCXHR is not set
# CONFIG_SND_RIPTIDE is not set
# CONFIG_SND_RME32 is not set
# CONFIG_SND_RME96 is not set
# CONFIG_SND_RME9652 is not set
# CONFIG_SND_SE6X is not set
# CONFIG_SND_SONICVIBES is not set
# CONFIG_SND_TRIDENT is not set
# CONFIG_SND_VIA82XX is not set
# CONFIG_SND_VIA82XX_MODEM is not set
# CONFIG_SND_VIRTUOSO is not set
# CONFIG_SND_VX222 is not set
# CONFIG_SND_YMFPCI is not set

#
# HD-Audio
#
CONFIG_SND_HDA=m
# CONFIG_SND_HDA_INTEL is not set
# CONFIG_SND_HDA_HWDEP is not set
# CONFIG_SND_HDA_RECONFIG is not set
# CONFIG_SND_HDA_INPUT_BEEP is not set
# CONFIG_SND_HDA_PATCH_LOADER is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
# CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set
# CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set
# CONFIG_SND_HDA_CODEC_REALTEK is not set
# CONFIG_SND_HDA_CODEC_ANALOG is not set
# CONFIG_SND_HDA_CODEC_SIGMATEL is not set
# CONFIG_SND_HDA_CODEC_VIA is not set
CONFIG_SND_HDA_CODEC_HDMI=m
# CONFIG_SND_HDA_CODEC_CIRRUS is not set
# CONFIG_SND_HDA_CODEC_CS8409 is not set
# CONFIG_SND_HDA_CODEC_CONEXANT is not set
# CONFIG_SND_HDA_CODEC_SENARYTECH is not set
# CONFIG_SND_HDA_CODEC_CA0110 is not set
# CONFIG_SND_HDA_CODEC_CA0132 is not set
# CONFIG_SND_HDA_CODEC_CMEDIA is not set
# CONFIG_SND_HDA_CODEC_SI3054 is not set
# CONFIG_SND_HDA_GENERIC is not set
CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
# end of HD-Audio

CONFIG_SND_HDA_CORE=m
CONFIG_SND_HDA_EXT_CORE=m
CONFIG_SND_HDA_PREALLOC_SIZE=2048
# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
# CONFIG_SND_USB_AUDIO_MIDI_V2 is not set
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
CONFIG_SND_BCD2000=m
CONFIG_SND_USB_LINE6=m
CONFIG_SND_USB_POD=m
CONFIG_SND_USB_PODHD=m
CONFIG_SND_USB_TONEPORT=m
CONFIG_SND_USB_VARIAX=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
CONFIG_SND_SOC_COMPRESS=y
# CONFIG_SND_SOC_ADI is not set
# CONFIG_SND_SOC_AMD_ACP is not set
# CONFIG_SND_AMD_ACP_CONFIG is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
CONFIG_SND_DESIGNWARE_I2S=m
# CONFIG_SND_DESIGNWARE_PCM is not set

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
# CONFIG_SND_SOC_FSL_SAI is not set
# CONFIG_SND_SOC_FSL_AUDMIX is not set
# CONFIG_SND_SOC_FSL_SSI is not set
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
# CONFIG_SND_SOC_FSL_MICFIL is not set
# CONFIG_SND_SOC_FSL_XCVR is not set
# CONFIG_SND_SOC_FSL_RPMSG is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs

# CONFIG_SND_SOC_CHV3_I2S is not set
# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set

#
# Amlogic
#
CONFIG_SND_MESON_AIU=m
CONFIG_SND_MESON_AXG_FIFO=m
CONFIG_SND_MESON_AXG_FRDDR=m
CONFIG_SND_MESON_AXG_TODDR=m
CONFIG_SND_MESON_AXG_TDM_FORMATTER=m
CONFIG_SND_MESON_AXG_TDM_INTERFACE=m
CONFIG_SND_MESON_AXG_TDMIN=m
CONFIG_SND_MESON_AXG_TDMOUT=m
CONFIG_SND_MESON_AXG_SOUND_CARD=m
CONFIG_SND_MESON_AXG_SPDIFOUT=m
CONFIG_SND_MESON_AXG_SPDIFIN=m
CONFIG_SND_MESON_AXG_PDM=m
CONFIG_SND_MESON_CARD_UTILS=m
CONFIG_SND_MESON_CODEC_GLUE=m
CONFIG_SND_MESON_GX_SOUND_CARD=m
CONFIG_SND_MESON_G12A_TOACODEC=m
CONFIG_SND_MESON_G12A_TOHDMITX=m
CONFIG_SND_SOC_MESON_T9015=m
# end of Amlogic

CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_ROCKCHIP_I2S=m
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
CONFIG_SND_SOC_ROCKCHIP_PDM=m
CONFIG_SND_SOC_ROCKCHIP_SAI=m
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
CONFIG_SND_SOC_ROCKCHIP_RT5645=m
CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m
CONFIG_SND_SOC_RK3399_GRU_SOUND=m
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set

#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support

#
# Allwinner SoC Audio support
#
CONFIG_SND_SUN4I_CODEC=m
CONFIG_SND_SUN50IW9_CODEC=m
CONFIG_SND_SUN8I_CODEC=m
CONFIG_SND_SUN8I_CODEC_ANALOG=m
CONFIG_SND_SUN50I_CODEC_ANALOG=m
CONFIG_SND_SUN4I_I2S=m
CONFIG_SND_SUN4I_SPDIF=m
CONFIG_SND_SUN50I_DMIC=m
CONFIG_SND_SUN8I_ADDA_PR_REGMAP=m
# end of Allwinner SoC Audio support

CONFIG_SND_SOC_SUNXI_MACH=m
CONFIG_SND_SOC_SUNXI_AHUB_DAM=m
CONFIG_SND_SOC_SUNXI_INTERNALCODEC=m
CONFIG_SND_SOC_SUNXI_SUN50IW9_CODEC=m

#
# Allwinner SoC Audio support V2
#
CONFIG_SND_SOC_SUNXI_AAUDIO=m
CONFIG_SND_SOC_SUNXI_AHUB=m
# end of Allwinner SoC Audio support V2

# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# CONFIG_SND_SOC_XTFPGA_I2S is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
CONFIG_SND_SOC_WM_ADSP=m
CONFIG_SND_SOC_AC97_CODEC=m
CONFIG_SND_SOC_ADAU_UTILS=m
CONFIG_SND_SOC_ADAU1372=m
CONFIG_SND_SOC_ADAU1372_I2C=m
CONFIG_SND_SOC_ADAU1372_SPI=m
CONFIG_SND_SOC_ADAU1701=m
CONFIG_SND_SOC_ADAU17X1=m
CONFIG_SND_SOC_ADAU1761=m
CONFIG_SND_SOC_ADAU1761_I2C=m
CONFIG_SND_SOC_ADAU1761_SPI=m
CONFIG_SND_SOC_ADAU7002=m
CONFIG_SND_SOC_ADAU7118=m
CONFIG_SND_SOC_ADAU7118_HW=m
CONFIG_SND_SOC_ADAU7118_I2C=m
CONFIG_SND_SOC_AK4104=m
CONFIG_SND_SOC_AK4118=m
CONFIG_SND_SOC_AK4375=m
CONFIG_SND_SOC_AK4458=m
CONFIG_SND_SOC_AK4554=m
CONFIG_SND_SOC_AK4613=m
CONFIG_SND_SOC_AK4619=m
CONFIG_SND_SOC_AK4642=m
CONFIG_SND_SOC_AK5386=m
CONFIG_SND_SOC_AK5558=m
CONFIG_SND_SOC_ALC5623=m
CONFIG_SND_SOC_AUDIO_IIO_AUX=m
CONFIG_SND_SOC_AW8738=m
CONFIG_SND_SOC_AW88395_LIB=m
CONFIG_SND_SOC_AW88395=m
CONFIG_SND_SOC_AW88261=m
CONFIG_SND_SOC_AW87390=m
CONFIG_SND_SOC_AW88399=m
CONFIG_SND_SOC_BD28623=m
CONFIG_SND_SOC_BT_SCO=m
CONFIG_SND_SOC_CHV3_CODEC=m
CONFIG_SND_SOC_CS_AMP_LIB=m
CONFIG_SND_SOC_CS35L32=m
CONFIG_SND_SOC_CS35L33=m
CONFIG_SND_SOC_CS35L34=m
CONFIG_SND_SOC_CS35L35=m
CONFIG_SND_SOC_CS35L36=m
CONFIG_SND_SOC_CS35L41_LIB=m
CONFIG_SND_SOC_CS35L41=m
CONFIG_SND_SOC_CS35L41_SPI=m
CONFIG_SND_SOC_CS35L41_I2C=m
CONFIG_SND_SOC_CS35L45=m
CONFIG_SND_SOC_CS35L45_SPI=m
CONFIG_SND_SOC_CS35L45_I2C=m
CONFIG_SND_SOC_CS35L56=m
CONFIG_SND_SOC_CS35L56_SHARED=m
CONFIG_SND_SOC_CS35L56_I2C=m
CONFIG_SND_SOC_CS35L56_SPI=m
CONFIG_SND_SOC_CS42L42_CORE=m
CONFIG_SND_SOC_CS42L42=m
CONFIG_SND_SOC_CS42L51=m
CONFIG_SND_SOC_CS42L51_I2C=m
CONFIG_SND_SOC_CS42L52=m
CONFIG_SND_SOC_CS42L56=m
CONFIG_SND_SOC_CS42L73=m
CONFIG_SND_SOC_CS42L83=m
CONFIG_SND_SOC_CS4234=m
CONFIG_SND_SOC_CS4265=m
CONFIG_SND_SOC_CS4270=m
CONFIG_SND_SOC_CS4271=m
CONFIG_SND_SOC_CS4271_I2C=m
CONFIG_SND_SOC_CS4271_SPI=m
CONFIG_SND_SOC_CS42XX8=m
CONFIG_SND_SOC_CS42XX8_I2C=m
CONFIG_SND_SOC_CS43130=m
CONFIG_SND_SOC_CS4341=m
CONFIG_SND_SOC_CS4349=m
CONFIG_SND_SOC_CS53L30=m
CONFIG_SND_SOC_CS530X=m
CONFIG_SND_SOC_CS530X_I2C=m
CONFIG_SND_SOC_CX2072X=m
CONFIG_SND_SOC_DA7213=m
CONFIG_SND_SOC_DA7219=m
CONFIG_SND_SOC_DMIC=m
CONFIG_SND_SOC_HDMI_CODEC=y
CONFIG_SND_SOC_ES7134=m
CONFIG_SND_SOC_ES7241=m
CONFIG_SND_SOC_ES8311=m
CONFIG_SND_SOC_ES8316=m
CONFIG_SND_SOC_ES8323=m
CONFIG_SND_SOC_ES8326=m
CONFIG_SND_SOC_ES8328=m
CONFIG_SND_SOC_ES8328_I2C=m
CONFIG_SND_SOC_ES8328_SPI=m
CONFIG_SND_SOC_GTM601=m
CONFIG_SND_SOC_HDA=m
CONFIG_SND_SOC_ICS43432=m
CONFIG_SND_SOC_IDT821034=m
CONFIG_SND_SOC_INNO_RK3036=m
CONFIG_SND_SOC_MAX98088=m
CONFIG_SND_SOC_MAX98090=m
CONFIG_SND_SOC_MAX98357A=m
CONFIG_SND_SOC_MAX98504=m
CONFIG_SND_SOC_MAX9867=m
CONFIG_SND_SOC_MAX98927=m
CONFIG_SND_SOC_MAX98520=m
CONFIG_SND_SOC_MAX98373=m
CONFIG_SND_SOC_MAX98373_I2C=m
CONFIG_SND_SOC_MAX98388=m
CONFIG_SND_SOC_MAX98390=m
CONFIG_SND_SOC_MAX98396=m
CONFIG_SND_SOC_MAX9860=m
CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
CONFIG_SND_SOC_PCM1681=m
CONFIG_SND_SOC_PCM1789=m
CONFIG_SND_SOC_PCM1789_I2C=m
CONFIG_SND_SOC_PCM179X=m
CONFIG_SND_SOC_PCM179X_I2C=m
CONFIG_SND_SOC_PCM179X_SPI=m
CONFIG_SND_SOC_PCM186X=m
CONFIG_SND_SOC_PCM186X_I2C=m
CONFIG_SND_SOC_PCM186X_SPI=m
CONFIG_SND_SOC_PCM3060=m
CONFIG_SND_SOC_PCM3060_I2C=m
CONFIG_SND_SOC_PCM3060_SPI=m
CONFIG_SND_SOC_PCM3168A=m
CONFIG_SND_SOC_PCM3168A_I2C=m
CONFIG_SND_SOC_PCM3168A_SPI=m
CONFIG_SND_SOC_PCM5102A=m
CONFIG_SND_SOC_PCM512x=m
CONFIG_SND_SOC_PCM512x_I2C=m
CONFIG_SND_SOC_PCM512x_SPI=m
CONFIG_SND_SOC_PCM6240=m
CONFIG_SND_SOC_PEB2466=m
CONFIG_SND_SOC_RK3308=m
CONFIG_SND_SOC_RK3328=m
CONFIG_SND_SOC_RK817=m
CONFIG_SND_SOC_RL6231=m
CONFIG_SND_SOC_RT5514=m
CONFIG_SND_SOC_RT5514_SPI=m
CONFIG_SND_SOC_RT5616=m
CONFIG_SND_SOC_RT5631=m
CONFIG_SND_SOC_RT5640=m
CONFIG_SND_SOC_RT5645=m
CONFIG_SND_SOC_RT5659=m
CONFIG_SND_SOC_RT9120=m
CONFIG_SND_SOC_RTQ9128=m
CONFIG_SND_SOC_SGTL5000=m
CONFIG_SND_SOC_SIGMADSP=m
CONFIG_SND_SOC_SIGMADSP_I2C=m
CONFIG_SND_SOC_SIGMADSP_REGMAP=m
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
CONFIG_SND_SOC_SIMPLE_MUX=m
CONFIG_SND_SOC_SMA1303=m
CONFIG_SND_SOC_SPDIF=m
CONFIG_SND_SOC_SRC4XXX_I2C=m
CONFIG_SND_SOC_SRC4XXX=m
CONFIG_SND_SOC_SSM2305=m
CONFIG_SND_SOC_SSM2518=m
CONFIG_SND_SOC_SSM2602=m
CONFIG_SND_SOC_SSM2602_SPI=m
CONFIG_SND_SOC_SSM2602_I2C=m
CONFIG_SND_SOC_SSM3515=m
CONFIG_SND_SOC_SSM4567=m
CONFIG_SND_SOC_STA32X=m
CONFIG_SND_SOC_STA350=m
CONFIG_SND_SOC_STI_SAS=m
CONFIG_SND_SOC_TAS2552=m
CONFIG_SND_SOC_TAS2562=m
CONFIG_SND_SOC_TAS2764=m
CONFIG_SND_SOC_TAS2770=m
CONFIG_SND_SOC_TAS2780=m
CONFIG_SND_SOC_TAS2781_COMLIB=m
CONFIG_SND_SOC_TAS2781_FMWLIB=m
CONFIG_SND_SOC_TAS2781_I2C=m
CONFIG_SND_SOC_TAS5086=m
CONFIG_SND_SOC_TAS571X=m
CONFIG_SND_SOC_TAS5720=m
CONFIG_SND_SOC_TAS5805M=m
CONFIG_SND_SOC_TAS6424=m
CONFIG_SND_SOC_TDA7419=m
CONFIG_SND_SOC_TFA9879=m
CONFIG_SND_SOC_TFA989X=m
CONFIG_SND_SOC_TLV320ADC3XXX=m
CONFIG_SND_SOC_TLV320AIC23=m
CONFIG_SND_SOC_TLV320AIC23_I2C=m
CONFIG_SND_SOC_TLV320AIC23_SPI=m
CONFIG_SND_SOC_TLV320AIC31XX=m
CONFIG_SND_SOC_TLV320AIC32X4=m
CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
CONFIG_SND_SOC_TLV320AIC3X=m
CONFIG_SND_SOC_TLV320AIC3X_I2C=m
CONFIG_SND_SOC_TLV320AIC3X_SPI=m
CONFIG_SND_SOC_TLV320ADCX140=m
CONFIG_SND_SOC_TS3A227E=m
CONFIG_SND_SOC_TSCS42XX=m
CONFIG_SND_SOC_TSCS454=m
CONFIG_SND_SOC_UDA1334=m
CONFIG_SND_SOC_WM8510=m
CONFIG_SND_SOC_WM8523=m
CONFIG_SND_SOC_WM8524=m
CONFIG_SND_SOC_WM8580=m
CONFIG_SND_SOC_WM8711=m
CONFIG_SND_SOC_WM8728=m
CONFIG_SND_SOC_WM8731=m
CONFIG_SND_SOC_WM8731_I2C=m
CONFIG_SND_SOC_WM8731_SPI=m
CONFIG_SND_SOC_WM8737=m
CONFIG_SND_SOC_WM8741=m
CONFIG_SND_SOC_WM8750=m
CONFIG_SND_SOC_WM8753=m
CONFIG_SND_SOC_WM8770=m
CONFIG_SND_SOC_WM8776=m
CONFIG_SND_SOC_WM8782=m
CONFIG_SND_SOC_WM8804=m
CONFIG_SND_SOC_WM8804_I2C=m
CONFIG_SND_SOC_WM8804_SPI=m
CONFIG_SND_SOC_WM8903=m
CONFIG_SND_SOC_WM8904=m
CONFIG_SND_SOC_WM8940=m
CONFIG_SND_SOC_WM8960=m
CONFIG_SND_SOC_WM8961=m
CONFIG_SND_SOC_WM8962=m
CONFIG_SND_SOC_WM8974=m
CONFIG_SND_SOC_WM8978=m
CONFIG_SND_SOC_WM8985=m
CONFIG_SND_SOC_ZL38060=m
CONFIG_SND_SOC_MAX9759=m
CONFIG_SND_SOC_MT6351=m
CONFIG_SND_SOC_MT6357=m
CONFIG_SND_SOC_MT6358=m
CONFIG_SND_SOC_MT6660=m
CONFIG_SND_SOC_NAU8315=m
CONFIG_SND_SOC_NAU8325=m
CONFIG_SND_SOC_NAU8540=m
CONFIG_SND_SOC_NAU8810=m
CONFIG_SND_SOC_NAU8821=m
CONFIG_SND_SOC_NAU8822=m
CONFIG_SND_SOC_NAU8824=m
CONFIG_SND_SOC_TPA6130A2=m
CONFIG_SND_SOC_LPASS_MACRO_COMMON=m
CONFIG_SND_SOC_LPASS_WSA_MACRO=m
CONFIG_SND_SOC_LPASS_VA_MACRO=m
CONFIG_SND_SOC_LPASS_RX_MACRO=m
CONFIG_SND_SOC_LPASS_TX_MACRO=m
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD2=m
CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
# CONFIG_SND_TEST_COMPONENT is not set
CONFIG_SND_VIRTIO=m
CONFIG_AC97_BUS=y
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=m
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
CONFIG_HID_A4TECH=m
CONFIG_HID_ACCUTOUCH=m
CONFIG_HID_ACRUX=m
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=m
CONFIG_HID_APPLEIR=m
CONFIG_HID_ASUS=m
CONFIG_HID_AUREAL=m
CONFIG_HID_BELKIN=m
CONFIG_HID_BETOP_FF=m
CONFIG_HID_BIGBEN_FF=m
CONFIG_HID_CHERRY=m
CONFIG_HID_CHICONY=m
CONFIG_HID_CORSAIR=m
CONFIG_HID_COUGAR=m
CONFIG_HID_MACALLY=m
CONFIG_HID_PRODIKEYS=m
CONFIG_HID_CMEDIA=m
CONFIG_HID_CP2112=m
CONFIG_HID_CREATIVE_SB0540=m
CONFIG_HID_CYPRESS=m
CONFIG_HID_DRAGONRISE=m
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=m
CONFIG_HID_ELAN=m
CONFIG_HID_ELECOM=m
CONFIG_HID_ELO=m
CONFIG_HID_EVISION=m
CONFIG_HID_EZKEY=m
CONFIG_HID_FT260=m
CONFIG_HID_GEMBIRD=m
CONFIG_HID_GFRM=m
CONFIG_HID_GLORIOUS=m
CONFIG_HID_HOLTEK=m
CONFIG_HOLTEK_FF=y
CONFIG_HID_VIVALDI_COMMON=m
# CONFIG_HID_GOODIX_SPI is not set
CONFIG_HID_GOOGLE_STADIA_FF=m
CONFIG_HID_VIVALDI=m
CONFIG_HID_GT683R=m
CONFIG_HID_KEYTOUCH=m
CONFIG_HID_KYE=m
CONFIG_HID_UCLOGIC=m
CONFIG_HID_WALTOP=m
CONFIG_HID_VIEWSONIC=m
CONFIG_HID_VRC2=m
CONFIG_HID_XIAOMI=m
CONFIG_HID_GYRATION=m
CONFIG_HID_ICADE=m
CONFIG_HID_ITE=m
CONFIG_HID_JABRA=m
CONFIG_HID_TWINHAN=m
CONFIG_HID_KENSINGTON=m
CONFIG_HID_LCPOWER=m
CONFIG_HID_LED=m
CONFIG_HID_LENOVO=m
CONFIG_HID_LETSKETCH=m
CONFIG_HID_LOGITECH=m
CONFIG_HID_LOGITECH_DJ=m
CONFIG_HID_LOGITECH_HIDPP=m
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
CONFIG_HID_MAGICMOUSE=m
CONFIG_HID_MALTRON=m
CONFIG_HID_MAYFLASH=m
CONFIG_HID_MEGAWORLD_FF=m
CONFIG_HID_REDRAGON=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
CONFIG_HID_MULTITOUCH=m
CONFIG_HID_NINTENDO=m
CONFIG_NINTENDO_FF=y
CONFIG_HID_NTI=m
CONFIG_HID_NTRIG=m
CONFIG_HID_NVIDIA_SHIELD=m
# CONFIG_NVIDIA_SHIELD_FF is not set
CONFIG_HID_ORTEK=m
CONFIG_HID_PANTHERLORD=m
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PENMOUNT=m
CONFIG_HID_PETALYNX=m
CONFIG_HID_PICOLCD=m
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
CONFIG_HID_PICOLCD_LCD=y
CONFIG_HID_PICOLCD_LEDS=y
CONFIG_HID_PICOLCD_CIR=y
CONFIG_HID_PLANTRONICS=m
CONFIG_HID_PLAYSTATION=m
CONFIG_PLAYSTATION_FF=y
CONFIG_HID_PXRC=m
CONFIG_HID_RAZER=m
CONFIG_HID_PRIMAX=m
CONFIG_HID_RETRODE=m
CONFIG_HID_ROCCAT=m
CONFIG_HID_SAITEK=m
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SEMITEK=m
CONFIG_HID_SIGMAMICRO=m
CONFIG_HID_SONY=m
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=m
CONFIG_HID_STEAM=m
# CONFIG_STEAM_FF is not set
CONFIG_HID_STEELSERIES=m
CONFIG_HID_SUNPLUS=m
CONFIG_HID_RMI=m
CONFIG_HID_GREENASIA=m
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=m
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TIVO=m
CONFIG_HID_TOPSEED=m
CONFIG_HID_TOPRE=m
CONFIG_HID_THINGM=m
CONFIG_HID_THRUSTMASTER=m
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_UDRAW_PS3=m
CONFIG_HID_U2FZERO=m
CONFIG_HID_UNIVERSAL_PIDFF=m
CONFIG_HID_WACOM=m
CONFIG_HID_WIIMOTE=m
# CONFIG_HID_WINWING is not set
CONFIG_HID_XINMO=m
CONFIG_HID_ZEROPLUS=m
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=m
CONFIG_HID_SENSOR_HUB=m
CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
CONFIG_HID_ALPS=m
CONFIG_HID_MCP2200=m
CONFIG_HID_MCP2221=m
# end of Special HID drivers

#
# HID-BPF support
#
# end of HID-BPF support

#
# USB HID support
#
CONFIG_USB_HID=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
# end of USB HID support

CONFIG_I2C_HID=y
CONFIG_I2C_HID_ACPI=m
CONFIG_I2C_HID_OF=m
CONFIG_I2C_HID_OF_ELAN=m
CONFIG_I2C_HID_OF_GOODIX=m
CONFIG_I2C_HID_CORE=m
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_LED_TRIG=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_CONN_GPIO=m
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
# CONFIG_USB_PCI_AMD is not set
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
CONFIG_USB_OTG_FSM=m
CONFIG_USB_LEDS_TRIGGER_USBPORT=m
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1
CONFIG_USB_MON=y

#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=m
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_XHCI_PCI_RENESAS=m
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_XHCI_SUNXI=m
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_EHCI_FSL=m
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OXU210HP_HCD=m
CONFIG_USB_ISP116X_HCD=m
CONFIG_USB_MAX3421_HCD=m
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_OHCI_HCD_PCI=m
CONFIG_USB_OHCI_HCD_PLATFORM=m
CONFIG_USB_UHCI_HCD=m
CONFIG_USB_SL811_HCD=m
CONFIG_USB_SL811_HCD_ISO=y
CONFIG_USB_R8A66597_HCD=m
CONFIG_USB_HCD_BCMA=m
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=y
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
CONFIG_USB_STORAGE_REALTEK=m
CONFIG_REALTEK_AUTOPM=y
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_FREECOM=m
CONFIG_USB_STORAGE_ISD200=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_STORAGE_ALAUDA=m
CONFIG_USB_STORAGE_ONETOUCH=m
CONFIG_USB_STORAGE_KARMA=m
CONFIG_USB_STORAGE_CYPRESS_ATACB=m
CONFIG_USB_STORAGE_ENE_UB6250=m
CONFIG_USB_UAS=y

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
CONFIG_USB_MICROTEK=m
CONFIG_USBIP_CORE=m
CONFIG_USBIP_VHCI_HCD=m
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=m
CONFIG_USBIP_VUDC=m
# CONFIG_USBIP_DEBUG is not set

#
# USB dual-mode controller drivers
#
# CONFIG_USB_CDNS_SUPPORT is not set
CONFIG_USB_MUSB_HDRC=y
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y

#
# Platform Glue Layer
#
CONFIG_USB_MUSB_SUNXI=m

#
# MUSB DMA mode
#
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_ULPI=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y

#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=y
CONFIG_USB_DWC3_HAPS=m
CONFIG_USB_DWC3_MESON_G12A=y
CONFIG_USB_DWC3_OF_SIMPLE=m
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
CONFIG_USB_DWC2_PCI=m
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
CONFIG_USB_CHIPIDEA=m
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_CHIPIDEA_PCI=m
CONFIG_USB_CHIPIDEA_MSM=m
CONFIG_USB_CHIPIDEA_NPCM=m
CONFIG_USB_CHIPIDEA_IMX=m
CONFIG_USB_CHIPIDEA_GENERIC=m
CONFIG_USB_CHIPIDEA_TEGRA=m
CONFIG_USB_ISP1760=m
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_ISP1761_UDC=y
# CONFIG_USB_ISP1760_HOST_ROLE is not set
# CONFIG_USB_ISP1760_GADGET_ROLE is not set
CONFIG_USB_ISP1760_DUAL_ROLE=y

#
# USB port drivers
#
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=m
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=y
CONFIG_USB_SERIAL_CH348=m
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=y
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=y
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=m
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_F81232=m
CONFIG_USB_SERIAL_F8153X=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=m
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_METRO=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MXUPORT=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=y
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=m
CONFIG_USB_SERIAL_QUALCOMM=m
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
# CONFIG_USB_SERIAL_SAFE_PADDED is not set
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
CONFIG_USB_SERIAL_SYMBOL=m
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_WWAN=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=m
CONFIG_USB_SERIAL_XSENS_MT=m
CONFIG_USB_SERIAL_WISHBONE=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_SERIAL_QT2=m
CONFIG_USB_SERIAL_UPD78F0730=m
CONFIG_USB_SERIAL_XR=m
CONFIG_USB_SERIAL_DEBUG=m

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
CONFIG_USB_CYPRESS_CY7C63=m
CONFIG_USB_CYTHERM=m
CONFIG_USB_IDMOUSE=m
CONFIG_USB_APPLEDISPLAY=m
CONFIG_APPLE_MFI_FASTCHARGE=m
# CONFIG_USB_LJCA is not set
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
CONFIG_USB_TEST=m
CONFIG_USB_EHSET_TEST_FIXTURE=m
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=m
CONFIG_USB_HUB_USB251XB=m
CONFIG_USB_HSIC_USB3503=m
CONFIG_USB_HSIC_USB4604=m
CONFIG_USB_LINK_LAYER_TEST=m
CONFIG_USB_CHAOSKEY=m
CONFIG_USB_ONBOARD_DEV=y
CONFIG_USB_ONBOARD_DEV_USB5744=y

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=m
CONFIG_USB_GPIO_VBUS=m
CONFIG_USB_ISP1301=m
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set

#
# USB Peripheral Controller
#
CONFIG_USB_GR_UDC=m
CONFIG_USB_R8A66597=m
CONFIG_USB_PXA27X=m
CONFIG_USB_MV_UDC=m
CONFIG_USB_MV_U3D=m
CONFIG_USB_SNP_CORE=m
CONFIG_USB_SNP_UDC_PLAT=m
CONFIG_USB_M66592=m
CONFIG_USB_BDC_UDC=m
CONFIG_USB_AMD5536UDC=m
CONFIG_USB_NET2272=m
CONFIG_USB_NET2272_DMA=y
CONFIG_USB_NET2280=m
CONFIG_USB_GOKU=m
CONFIG_USB_EG20T=m
CONFIG_USB_GADGET_XILINX=m
CONFIG_USB_MAX3420_UDC=m
CONFIG_USB_CDNS2_UDC=m
CONFIG_USB_DUMMY_HCD=m
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=m
CONFIG_USB_F_ACM=m
CONFIG_USB_F_SS_LB=m
CONFIG_USB_U_SERIAL=m
CONFIG_USB_U_ETHER=m
CONFIG_USB_U_AUDIO=m
CONFIG_USB_F_SERIAL=m
CONFIG_USB_F_OBEX=m
CONFIG_USB_F_NCM=m
CONFIG_USB_F_ECM=m
CONFIG_USB_F_EEM=m
CONFIG_USB_F_SUBSET=m
CONFIG_USB_F_RNDIS=m
CONFIG_USB_F_MASS_STORAGE=m
CONFIG_USB_F_FS=m
CONFIG_USB_F_UAC1=m
CONFIG_USB_F_UAC1_LEGACY=m
CONFIG_USB_F_UAC2=m
CONFIG_USB_F_UVC=m
CONFIG_USB_F_MIDI=m
CONFIG_USB_F_MIDI2=m
CONFIG_USB_F_HID=m
CONFIG_USB_F_PRINTER=m
CONFIG_USB_F_TCM=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_LB_SS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_MIDI2=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y
CONFIG_USB_CONFIGFS_F_TCM=y

#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=m
CONFIG_USB_ZERO_HNPTEST=y
CONFIG_USB_AUDIO=m
CONFIG_GADGET_UAC1=y
CONFIG_GADGET_UAC1_LEGACY=y
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
CONFIG_USB_FUNCTIONFS_ETH=y
CONFIG_USB_FUNCTIONFS_RNDIS=y
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_GADGET_TARGET=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_G_HID=m
CONFIG_USB_G_DBGP=m
# CONFIG_USB_G_DBGP_PRINTK is not set
CONFIG_USB_G_DBGP_SERIAL=y
CONFIG_USB_G_WEBCAM=m
CONFIG_USB_RAW_GADGET=m
# end of USB Gadget precomposed configurations

CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
CONFIG_TYPEC_HUSB311=y
CONFIG_TYPEC_RT1711H=y
CONFIG_TYPEC_TCPCI_MAXIM=y
CONFIG_TYPEC_FUSB302=y
CONFIG_TYPEC_UCSI=y
CONFIG_UCSI_CCG=y
CONFIG_UCSI_ACPI=y
CONFIG_UCSI_STM32G0=y
CONFIG_TYPEC_TPS6598X=y
CONFIG_TYPEC_ANX7411=y
CONFIG_TYPEC_RT1719=y
CONFIG_TYPEC_HD3SS3220=y
CONFIG_TYPEC_STUSB160X=y
CONFIG_TYPEC_WUSB3801=y

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
CONFIG_TYPEC_MUX_FSA4480=m
CONFIG_TYPEC_MUX_GPIO_SBU=m
CONFIG_TYPEC_MUX_PI3USB30532=m
CONFIG_TYPEC_MUX_IT5205=m
CONFIG_TYPEC_MUX_NB7VPQ904M=m
CONFIG_TYPEC_MUX_PTN36502=m
CONFIG_TYPEC_MUX_WCD939X_USBSS=m
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
CONFIG_TYPEC_DP_ALTMODE=m
CONFIG_TYPEC_NVIDIA_ALTMODE=m
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
# CONFIG_PWRSEQ_SD8787 is not set
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set
# CONFIG_MMC_CRYPTO is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_ARMMMCI=m
CONFIG_MMC_STM32_SDMMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_PCI=m
CONFIG_MMC_RICOH_MMC=y
CONFIG_MMC_SDHCI_ACPI=m
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
CONFIG_MMC_SDHCI_OF_AT91=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MMC_SDHCI_F_SDH30=m
CONFIG_MMC_SDHCI_MILBEAUT=m
CONFIG_MMC_MESON_GX=y
CONFIG_MMC_MESON_MX_SDIO=y
CONFIG_MMC_TIFM_SD=m
CONFIG_MMC_SPI=m
CONFIG_MMC_CB710=m
CONFIG_MMC_VIA_SDMMC=m
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
CONFIG_MMC_DW_BLUEFIELD=m
CONFIG_MMC_DW_EXYNOS=m
CONFIG_MMC_DW_HI3798CV200=m
CONFIG_MMC_DW_HI3798MV200=m
CONFIG_MMC_DW_K3=m
CONFIG_MMC_DW_PCI=m
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_VUB300=m
CONFIG_MMC_USHC=m
CONFIG_MMC_USDHI6ROL0=m
CONFIG_MMC_REALTEK_USB=m
CONFIG_MMC_SUNXI=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_HSQ=y
CONFIG_MMC_TOSHIBA_PCI=m
CONFIG_MMC_MTK=y
CONFIG_MMC_SDHCI_XENON=m
CONFIG_SCSI_UFSHCD=y
CONFIG_SCSI_UFS_BSG=y
CONFIG_SCSI_UFS_CRYPTO=y
CONFIG_SCSI_UFS_HWMON=y
CONFIG_SCSI_UFSHCD_PCI=m
CONFIG_SCSI_UFS_DWC_TC_PCI=m
CONFIG_SCSI_UFSHCD_PLATFORM=y
CONFIG_SCSI_UFS_CDNS_PLATFORM=y
CONFIG_SCSI_UFS_DWC_TC_PLATFORM=y
CONFIG_SCSI_UFS_ROCKCHIP=y
# CONFIG_MEMSTICK is not set
CONFIG_LEDS_EXPRESSWIRE=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
CONFIG_LEDS_CLASS_MULTICOLOR=y
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y

#
# LED drivers
#
CONFIG_LEDS_AN30259A=m
CONFIG_LEDS_AW200XX=m
CONFIG_LEDS_AW2013=m
CONFIG_LEDS_BCM6328=m
CONFIG_LEDS_BCM6358=m
CONFIG_LEDS_CR0014114=m
CONFIG_LEDS_EL15203000=m
CONFIG_LEDS_LM3530=m
CONFIG_LEDS_LM3532=m
CONFIG_LEDS_LM3642=m
CONFIG_LEDS_LM3692X=m
# CONFIG_LEDS_SUN50I_A100 is not set
CONFIG_LEDS_PCA9532=m
CONFIG_LEDS_PCA9532_GPIO=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=m
CONFIG_LEDS_LP3952=m
CONFIG_LEDS_LP50XX=m
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LEDS_LP5521=m
CONFIG_LEDS_LP5523=m
CONFIG_LEDS_LP5562=m
# CONFIG_LEDS_LP5569 is not set
CONFIG_LEDS_LP8501=m
CONFIG_LEDS_LP8860=m
CONFIG_LEDS_PCA955X=m
CONFIG_LEDS_PCA955X_GPIO=y
CONFIG_LEDS_PCA963X=m
CONFIG_LEDS_PCA995X=m
CONFIG_LEDS_DAC124S085=m
CONFIG_LEDS_PWM=y
CONFIG_LEDS_REGULATOR=y
CONFIG_LEDS_BD2606MVV=m
CONFIG_LEDS_BD2802=m
CONFIG_LEDS_LT3593=m
CONFIG_LEDS_TCA6507=y
CONFIG_LEDS_TLC591XX=m
CONFIG_LEDS_LM355x=m
CONFIG_LEDS_IS31FL319X=m
CONFIG_LEDS_IS31FL32XX=m

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=m
# CONFIG_LEDS_BLINKM_MULTICOLOR is not set
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_MLXREG=m
CONFIG_LEDS_USER=y
CONFIG_LEDS_SPI_BYTE=m
CONFIG_LEDS_TI_LMU_COMMON=m
CONFIG_LEDS_LM3697=m
CONFIG_LEDS_ST1202=m

#
# Flash and Torch LED drivers
#
CONFIG_LEDS_AAT1290=m
CONFIG_LEDS_AS3645A=m
CONFIG_LEDS_KTD2692=m
CONFIG_LEDS_LM3601X=m
CONFIG_LEDS_RT4505=m
CONFIG_LEDS_RT8515=m
CONFIG_LEDS_SGM3140=m
# CONFIG_LEDS_SY7802 is not set

#
# RGB LED drivers
#
CONFIG_LEDS_GROUP_MULTICOLOR=m
# CONFIG_LEDS_KTD202X is not set
# CONFIG_LEDS_NCP5623 is not set
CONFIG_LEDS_PWM_MULTICOLOR=y
CONFIG_LEDS_QCOM_LPG=m

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_ACTIVITY=y
# CONFIG_LEDS_TRIGGER_GPIO is not set
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=y
CONFIG_LEDS_TRIGGER_PATTERN=y
CONFIG_LEDS_TRIGGER_TTY=y
# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set

#
# Simple LED drivers
#
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
# CONFIG_EDAC_DEBUG is not set
# CONFIG_EDAC_GHES is not set
# CONFIG_EDAC_THUNDERX is not set
# CONFIG_EDAC_XGENE is not set
CONFIG_EDAC_DMC520=m
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_ABB5ZES3 is not set
# CONFIG_RTC_DRV_ABEOZ9 is not set
# CONFIG_RTC_DRV_ABX80X is not set
CONFIG_RTC_DRV_AC100=m
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
CONFIG_RTC_DRV_HYM8563=m
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_MAX31335 is not set
# CONFIG_RTC_DRV_NCT3018Y is not set
CONFIG_RTC_DRV_RK808=m
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_ISL12026 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8523 is not set
# CONFIG_RTC_DRV_PCF85063 is not set
# CONFIG_RTC_DRV_PCF85363 is not set
CONFIG_RTC_DRV_PCF8563=m
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8010 is not set
# CONFIG_RTC_DRV_RX8111 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV3028 is not set
# CONFIG_RTC_DRV_RV3032 is not set
# CONFIG_RTC_DRV_RV8803 is not set
# CONFIG_RTC_DRV_SD2405AL is not set
# CONFIG_RTC_DRV_SD3078 is not set

#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_MCP795 is not set
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_PCF2127 is not set
# CONFIG_RTC_DRV_RV3029C2 is not set
# CONFIG_RTC_DRV_RX6110 is not set

#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1685_FAMILY is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_DS2404 is not set
CONFIG_RTC_DRV_EFI=m
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_OPTEE is not set
# CONFIG_RTC_DRV_ZYNQMP is not set

#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_MESON_VRTC=m
CONFIG_RTC_DRV_PL030=m
CONFIG_RTC_DRV_PL031=m
CONFIG_RTC_DRV_SUN6I=y
# CONFIG_RTC_DRV_CADENCE is not set
# CONFIG_RTC_DRV_FTRTC010 is not set
# CONFIG_RTC_DRV_R7301 is not set

#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
# CONFIG_RTC_DRV_GOLDFISH is not set
CONFIG_RTC_DRV_AMLOGIC_A4=y
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
CONFIG_AMBA_PL08X=y
# CONFIG_BCM_SBA_RAID is not set
CONFIG_DMA_SUN6I=y
CONFIG_DW_AXI_DMAC=y
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_MV_XOR_V2 is not set
CONFIG_PL330_DMA=y
# CONFIG_PLX_DMA is not set
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_XDMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
# CONFIG_XILINX_ZYNQMP_DPDMA is not set
# CONFIG_AMD_QDMA is not set
CONFIG_QCOM_HIDMA_MGMT=y
CONFIG_QCOM_HIDMA=y
CONFIG_DW_DMAC_CORE=y
CONFIG_DW_DMAC=y
CONFIG_DW_DMAC_PCI=y
CONFIG_DW_EDMA=y
CONFIG_DW_EDMA_PCIE=y
# CONFIG_SF_PDMA is not set

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_DEBUG is not set
# CONFIG_DMABUF_SELFTESTS is not set
CONFIG_DMABUF_HEAPS=y
# CONFIG_DMABUF_SYSFS_STATS is not set
CONFIG_DMABUF_HEAPS_SYSTEM=y
CONFIG_DMABUF_HEAPS_CMA=y
# end of DMABUF options

# CONFIG_UIO is not set
# CONFIG_VFIO is not set
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_VIRT_DRIVERS=y
CONFIG_VMGENID=y
# CONFIG_ARM_PKVM_GUEST is not set
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_PCI_LIB=m
CONFIG_VIRTIO_PCI_LIB_LEGACY=m
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=m
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
# CONFIG_VIRTIO_DEBUG is not set
# CONFIG_VDPA is not set
CONFIG_VHOST_IOTLB=m
CONFIG_VHOST_TASK=y
CONFIG_VHOST=m
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_SCSI=m
# CONFIG_VHOST_VSOCK is not set
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
CONFIG_VHOST_ENABLE_FORK_OWNER_CONTROL=y

#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
# CONFIG_COMEDI is not set
CONFIG_STAGING=y
CONFIG_RTLLIB=m
CONFIG_RTLLIB_CRYPTO_CCMP=m
CONFIG_RTLLIB_CRYPTO_TKIP=m
CONFIG_RTLLIB_CRYPTO_WEP=m
CONFIG_RTL8192E=m
CONFIG_RTL8723BS=m
CONFIG_RTS5208=m
CONFIG_VT6655=m
CONFIG_VT6656=m

#
# IIO staging drivers
#

#
# Accelerometers
#
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16240 is not set
# end of Accelerometers

#
# Analog to digital converters
#
# CONFIG_AD7816 is not set
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
# CONFIG_ADT7316 is not set
# end of Analog digital bi-direction converters

#
# Direct Digital Synthesis
#
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
# CONFIG_AD5933 is not set
# end of Network Analyzer, Impedance Converters
# end of IIO staging drivers

# CONFIG_FB_SM750 is not set
CONFIG_STAGING_MEDIA=y
# CONFIG_VIDEO_MAX96712 is not set
CONFIG_VIDEO_MESON_VDEC=m

#
# StarFive media platform drivers
#
CONFIG_VIDEO_SUNXI=y
CONFIG_VIDEO_SUNXI_CEDRUS=m
CONFIG_VIDEO_SUN6I_ISP=m
# CONFIG_STAGING_MEDIA_DEPRECATED is not set
# CONFIG_LTE_GDM724X is not set
CONFIG_FB_TFT=m
CONFIG_FB_TFT_AGM1264K_FL=m
CONFIG_FB_TFT_BD663474=m
CONFIG_FB_TFT_HX8340BN=m
CONFIG_FB_TFT_HX8347D=m
CONFIG_FB_TFT_HX8353D=m
CONFIG_FB_TFT_HX8357D=m
CONFIG_FB_TFT_ILI9163=m
CONFIG_FB_TFT_ILI9320=m
CONFIG_FB_TFT_ILI9325=m
CONFIG_FB_TFT_ILI9340=m
CONFIG_FB_TFT_ILI9341=m
CONFIG_FB_TFT_ILI9481=m
CONFIG_FB_TFT_ILI9486=m
CONFIG_FB_TFT_PCD8544=m
CONFIG_FB_TFT_RA8875=m
CONFIG_FB_TFT_S6D02A1=m
CONFIG_FB_TFT_S6D1121=m
CONFIG_FB_TFT_SEPS525=m
CONFIG_FB_TFT_SH1106=m
CONFIG_FB_TFT_SSD1289=m
CONFIG_FB_TFT_SSD1305=m
CONFIG_FB_TFT_SSD1306=m
CONFIG_FB_TFT_SSD1331=m
CONFIG_FB_TFT_SSD1351=m
CONFIG_FB_TFT_ST7735R=m
CONFIG_FB_TFT_ST7789V=m
CONFIG_FB_TFT_TINYLCD=m
CONFIG_FB_TFT_TLS8204=m
CONFIG_FB_TFT_UC1611=m
CONFIG_FB_TFT_UC1701=m
CONFIG_FB_TFT_UPD161704=m
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_VME_BUS is not set
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
CONFIG_SURFACE_PLATFORMS=y
# CONFIG_SURFACE_3_POWER_OPREGION is not set
# CONFIG_SURFACE_GPE is not set
# CONFIG_SURFACE_HOTPLUG is not set
# CONFIG_SURFACE_PRO3_BUTTON is not set
# CONFIG_SURFACE_AGGREGATOR is not set
CONFIG_ARM64_PLATFORM_DEVICES=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Clock driver for ARM Reference designs
#
# CONFIG_CLK_ICST is not set
# CONFIG_CLK_SP810 is not set
# CONFIG_CLK_VEXPRESS_OSC is not set
# end of Clock driver for ARM Reference designs

# CONFIG_LMK04832 is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
CONFIG_COMMON_CLK_CS2000_CP=y
# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
# CONFIG_COMMON_CLK_XGENE is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_RS9_PCIE is not set
# CONFIG_COMMON_CLK_SI521XX is not set
# CONFIG_COMMON_CLK_VC3 is not set
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_VC7 is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set

#
# Clock support for Amlogic platforms
#
CONFIG_COMMON_CLK_MESON_REGMAP=y
CONFIG_COMMON_CLK_MESON_DUALDIV=y
CONFIG_COMMON_CLK_MESON_MPLL=y
CONFIG_COMMON_CLK_MESON_PHASE=y
CONFIG_COMMON_CLK_MESON_PLL=y
CONFIG_COMMON_CLK_MESON_SCLK_DIV=y
CONFIG_COMMON_CLK_MESON_VID_PLL_DIV=y
CONFIG_COMMON_CLK_MESON_VCLK=y
CONFIG_COMMON_CLK_MESON_CLKC_UTILS=y
CONFIG_COMMON_CLK_MESON_AO_CLKC=y
CONFIG_COMMON_CLK_MESON_EE_CLKC=y
CONFIG_COMMON_CLK_MESON_CPU_DYNDIV=y
CONFIG_COMMON_CLK_GXBB=y
CONFIG_COMMON_CLK_AXG=y
CONFIG_COMMON_CLK_AXG_AUDIO=y
CONFIG_COMMON_CLK_A1_PLL=y
CONFIG_COMMON_CLK_A1_PERIPHERALS=y
CONFIG_COMMON_CLK_C3_PLL=y
CONFIG_COMMON_CLK_C3_PERIPHERALS=y
CONFIG_COMMON_CLK_G12A=y
CONFIG_COMMON_CLK_S4_PLL=y
CONFIG_COMMON_CLK_S4_PERIPHERALS=y
# end of Clock support for Amlogic platforms

CONFIG_COMMON_CLK_ROCKCHIP=y
CONFIG_CLK_PX30=y
CONFIG_CLK_RV1126B=y
CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
CONFIG_CLK_RK3399=y
CONFIG_CLK_RK3528=y
CONFIG_CLK_RK3562=y
CONFIG_CLK_RK3568=y
CONFIG_CLK_RK3576=y
CONFIG_CLK_RK3588=y
CONFIG_SUNXI_CCU=y
CONFIG_SUN50I_A64_CCU=y
CONFIG_SUN50I_A100_CCU=y
CONFIG_SUN50I_A100_R_CCU=y
CONFIG_SUN50I_H6_CCU=y
CONFIG_SUN50I_H616_CCU=y
CONFIG_SUN50I_H6_R_CCU=y
CONFIG_SUN6I_RTC_CCU=y
CONFIG_SUN8I_H3_CCU=y
CONFIG_SUN8I_DE2_CCU=y
CONFIG_SUN8I_R_CCU=y
# CONFIG_XILINX_VCU is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_SUN6I=y

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_ACPI=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_SUN4I_TIMER=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
CONFIG_ARM_TIMER_SP804=y
# end of Clock Source drivers

CONFIG_MAILBOX=y
CONFIG_ARM_MHU=y
CONFIG_ARM_MHU_V2=y
CONFIG_ARM_MHU_V3=y
CONFIG_PLATFORM_MHU=y
CONFIG_PL320_MBOX=y
CONFIG_ROCKCHIP_MBOX=y
CONFIG_PCC=y
CONFIG_ALTERA_MBOX=m
# CONFIG_MAILBOX_TEST is not set
CONFIG_SUN6I_MSGBOX=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_DART is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
CONFIG_IOMMU_SVA=y
CONFIG_IOMMU_IOPF=y
# CONFIG_IOMMUFD is not set
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_SUN50I_IOMMU=y
CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
CONFIG_ARM_SMMU_V3=y
CONFIG_ARM_SMMU_V3_SVA=y
# CONFIG_TEGRA241_CMDQV is not set
CONFIG_VIRTIO_IOMMU=m

#
# Remoteproc drivers
#
CONFIG_REMOTEPROC=y
CONFIG_REMOTEPROC_CDEV=y
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=m
CONFIG_RPMSG_CHAR=m
# CONFIG_RPMSG_CTRL is not set
CONFIG_RPMSG_NS=m
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
CONFIG_RPMSG_VIRTIO=m
# end of Rpmsg drivers

# CONFIG_SOUNDWIRE is not set

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
CONFIG_MESON_CANVAS=y
CONFIG_MESON_CLK_MEASURE=y
CONFIG_MESON_GX_SOCINFO=y
# end of Amlogic SoC drivers

#
# Broadcom SoC drivers
#
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
CONFIG_QUICC_ENGINE=y
# CONFIG_CPM_TSA is not set
# end of NXP/Freescale QorIQ SoC drivers

#
# fujitsu SoC drivers
#
# CONFIG_A64FX_DIAG is not set
# end of fujitsu SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Enable LiteX SoC Builder specific drivers
#
# CONFIG_LITEX_SOC_CONTROLLER is not set
# end of Enable LiteX SoC Builder specific drivers

# CONFIG_WPCM450_SOC is not set

#
# Qualcomm SoC drivers
#
# CONFIG_QCOM_PMIC_PDCHARGER_ULOG is not set
# CONFIG_QCOM_PMIC_GLINK is not set
CONFIG_QCOM_QMI_HELPERS=m
# CONFIG_QCOM_PBS is not set
# end of Qualcomm SoC drivers

CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_SUNXI_MBUS=y
CONFIG_SUNXI_SRAM=y
# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

#
# PM Domains
#

#
# Amlogic PM Domains
#
CONFIG_MESON_EE_PM_DOMAINS=y
CONFIG_MESON_SECURE_PM_DOMAINS=y
# end of Amlogic PM Domains

CONFIG_ARM_SCMI_PERF_DOMAIN=y
CONFIG_ARM_SCMI_POWER_DOMAIN=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y

#
# Broadcom PM Domains
#
# end of Broadcom PM Domains

#
# i.MX PM Domains
#
# end of i.MX PM Domains

#
# Qualcomm PM Domains
#
# end of Qualcomm PM Domains

CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_SUN20I_PPU=y
# end of PM Domains

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=m
CONFIG_DEVFREQ_GOV_USERSPACE=m
CONFIG_DEVFREQ_GOV_PASSIVE=m

#
# DEVFREQ Drivers
#
CONFIG_ARM_RK3328_DMC_DEVFREQ=y
CONFIG_ARM_RK3399_DMC_DEVFREQ=y
CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
CONFIG_EXTCON_ADC_JACK=m
CONFIG_EXTCON_FSA9480=m
CONFIG_EXTCON_GPIO=m
# CONFIG_EXTCON_LC824206XA is not set
CONFIG_EXTCON_MAX3355=m
CONFIG_EXTCON_PTN5150=m
CONFIG_EXTCON_RT8973A=m
CONFIG_EXTCON_SM5502=m
CONFIG_EXTCON_USB_GPIO=m
CONFIG_EXTCON_USBC_TUSB320=m
CONFIG_EXTCON_USBC_VIRTUAL_PD=m
CONFIG_MEMORY=y
CONFIG_ARM_PL172_MPMC=m
# CONFIG_FPGA_DFL_EMIF is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
CONFIG_IIO_BUFFER_DMA=m
CONFIG_IIO_BUFFER_DMAENGINE=m
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
CONFIG_IIO_TRIGGERED_EVENT=m
CONFIG_IIO_BACKEND=m

#
# Accelerometers
#
CONFIG_ADIS16201=m
CONFIG_ADIS16209=m
CONFIG_ADXL313=m
CONFIG_ADXL313_I2C=m
CONFIG_ADXL313_SPI=m
CONFIG_ADXL345=m
CONFIG_ADXL345_I2C=m
CONFIG_ADXL345_SPI=m
CONFIG_ADXL355=m
CONFIG_ADXL355_I2C=m
CONFIG_ADXL355_SPI=m
CONFIG_ADXL367=m
CONFIG_ADXL367_SPI=m
CONFIG_ADXL367_I2C=m
CONFIG_ADXL372=m
CONFIG_ADXL372_SPI=m
CONFIG_ADXL372_I2C=m
# CONFIG_ADXL380_SPI is not set
# CONFIG_ADXL380_I2C is not set
CONFIG_BMA180=m
CONFIG_BMA220=m
CONFIG_BMA400=m
CONFIG_BMA400_I2C=m
CONFIG_BMA400_SPI=m
CONFIG_BMC150_ACCEL=m
CONFIG_BMC150_ACCEL_I2C=m
CONFIG_BMC150_ACCEL_SPI=m
CONFIG_BMI088_ACCEL=m
CONFIG_BMI088_ACCEL_I2C=m
CONFIG_BMI088_ACCEL_SPI=m
CONFIG_DA280=m
CONFIG_DA311=m
CONFIG_DMARD06=m
CONFIG_DMARD09=m
CONFIG_DMARD10=m
CONFIG_FXLS8962AF=m
CONFIG_FXLS8962AF_I2C=m
CONFIG_FXLS8962AF_SPI=m
CONFIG_HID_SENSOR_ACCEL_3D=m
CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
# CONFIG_IIO_KX022A_SPI is not set
# CONFIG_IIO_KX022A_I2C is not set
CONFIG_KXSD9=m
CONFIG_KXSD9_SPI=m
CONFIG_KXSD9_I2C=m
CONFIG_KXCJK1013=m
CONFIG_MC3230=m
CONFIG_MMA7455=m
CONFIG_MMA7455_I2C=m
CONFIG_MMA7455_SPI=m
CONFIG_MMA7660=m
CONFIG_MMA8452=m
CONFIG_MMA9551_CORE=m
CONFIG_MMA9551=m
CONFIG_MMA9553=m
CONFIG_MSA311=m
CONFIG_MXC4005=m
CONFIG_MXC6255=m
CONFIG_SCA3000=m
CONFIG_SCA3300=m
CONFIG_STK8312=m
CONFIG_STK8BA50=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=m
# CONFIG_AD4000 is not set
# CONFIG_AD4130 is not set
# CONFIG_AD4695 is not set
CONFIG_AD7091R=m
CONFIG_AD7091R5=m
# CONFIG_AD7091R8 is not set
CONFIG_AD7124=m
# CONFIG_AD7173 is not set
CONFIG_AD7192=m
CONFIG_AD7266=m
CONFIG_AD7280=m
CONFIG_AD7291=m
CONFIG_AD7292=m
CONFIG_AD7298=m
# CONFIG_AD7380 is not set
CONFIG_AD7476=m
CONFIG_AD7606=m
CONFIG_AD7606_IFACE_PARALLEL=m
CONFIG_AD7606_IFACE_SPI=m
CONFIG_AD7766=m
CONFIG_AD7768_1=m
CONFIG_AD7780=m
CONFIG_AD7791=m
CONFIG_AD7793=m
CONFIG_AD7887=m
CONFIG_AD7923=m
# CONFIG_AD7944 is not set
CONFIG_AD7949=m
CONFIG_AD799X=m
CONFIG_AD9467=m
CONFIG_AXP20X_ADC=y
CONFIG_AXP288_ADC=y
CONFIG_CC10001_ADC=m
CONFIG_ENVELOPE_DETECTOR=m
CONFIG_HI8435=m
CONFIG_HX711=m
CONFIG_INA2XX_ADC=m
# CONFIG_LTC2309 is not set
CONFIG_LTC2471=m
CONFIG_LTC2485=m
CONFIG_LTC2496=m
CONFIG_LTC2497=m
CONFIG_MAX1027=m
CONFIG_MAX11100=m
CONFIG_MAX1118=m
CONFIG_MAX11205=m
# CONFIG_MAX11410 is not set
CONFIG_MAX1241=m
CONFIG_MAX1363=m
# CONFIG_MAX34408 is not set
CONFIG_MAX9611=m
CONFIG_MCP320X=m
CONFIG_MCP3422=m
# CONFIG_MCP3564 is not set
CONFIG_MCP3911=m
CONFIG_MESON_SARADC=y
CONFIG_NAU7802=m
# CONFIG_PAC1921 is not set
# CONFIG_PAC1934 is not set
CONFIG_QCOM_VADC_COMMON=m
CONFIG_QCOM_SPMI_IADC=m
CONFIG_QCOM_SPMI_VADC=m
CONFIG_QCOM_SPMI_ADC5=m
CONFIG_ROCKCHIP_SARADC=y
CONFIG_RICHTEK_RTQ6056=m
CONFIG_SD_ADC_MODULATOR=m
# CONFIG_SUN20I_GPADC is not set
CONFIG_TI_ADC081C=m
CONFIG_TI_ADC0832=m
CONFIG_TI_ADC084S021=m
CONFIG_TI_ADC12138=m
CONFIG_TI_ADC108S102=m
CONFIG_TI_ADC128S052=m
CONFIG_TI_ADC161S626=m
CONFIG_TI_ADS1015=m
# CONFIG_TI_ADS1119 is not set
# CONFIG_TI_ADS7924 is not set
# CONFIG_TI_ADS1100 is not set
# CONFIG_TI_ADS1298 is not set
CONFIG_TI_ADS7950=m
CONFIG_TI_ADS8344=m
CONFIG_TI_ADS8688=m
CONFIG_TI_ADS124S08=m
CONFIG_TI_ADS131E08=m
# CONFIG_TI_LMP92064 is not set
CONFIG_TI_TLC4541=m
CONFIG_TI_TSC2046=m
CONFIG_VF610_ADC=m
CONFIG_XILINX_XADC=m
# end of Analog to digital converters

#
# Analog to digital and digital to analog converters
#
# CONFIG_AD74115 is not set
CONFIG_AD74413R=m
# end of Analog to digital and digital to analog converters

#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=m
# end of Analog Front Ends

#
# Amplifiers
#
CONFIG_AD8366=m
CONFIG_ADA4250=m
CONFIG_HMC425=m
# end of Amplifiers

#
# Capacitance to digital converters
#
CONFIG_AD7150=m
CONFIG_AD7746=m
# end of Capacitance to digital converters

#
# Chemical Sensors
#
# CONFIG_AOSONG_AGS02MA is not set
CONFIG_ATLAS_PH_SENSOR=m
CONFIG_ATLAS_EZO_SENSOR=m
CONFIG_BME680=m
CONFIG_BME680_I2C=m
CONFIG_BME680_SPI=m
CONFIG_CCS811=m
# CONFIG_ENS160 is not set
CONFIG_IAQCORE=m
CONFIG_PMS7003=m
CONFIG_SCD30_CORE=m
CONFIG_SCD30_I2C=m
CONFIG_SCD30_SERIAL=m
CONFIG_SCD4X=m
CONFIG_SENSIRION_SGP30=m
CONFIG_SENSIRION_SGP40=m
CONFIG_SPS30=m
CONFIG_SPS30_I2C=m
CONFIG_SPS30_SERIAL=m
CONFIG_SENSEAIR_SUNRISE_CO2=m
CONFIG_VZ89X=m
# end of Chemical Sensors

#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
# end of Hid Sensor IIO Common

CONFIG_IIO_INV_SENSORS_TIMESTAMP=m
CONFIG_IIO_MS_SENSORS_I2C=m

#
# IIO SCMI Sensors
#
CONFIG_IIO_SCMI=m
# end of IIO SCMI Sensors

#
# SSP Sensor Common
#
CONFIG_IIO_SSP_SENSORS_COMMONS=m
CONFIG_IIO_SSP_SENSORHUB=m
# end of SSP Sensor Common

CONFIG_IIO_ST_SENSORS_I2C=m
CONFIG_IIO_ST_SENSORS_SPI=m
CONFIG_IIO_ST_SENSORS_CORE=m

#
# Digital to analog converters
#
CONFIG_AD3552R=m
CONFIG_AD5064=m
CONFIG_AD5360=m
CONFIG_AD5380=m
CONFIG_AD5421=m
CONFIG_AD5446=m
CONFIG_AD5449=m
CONFIG_AD5592R_BASE=m
CONFIG_AD5592R=m
CONFIG_AD5593R=m
CONFIG_AD5504=m
CONFIG_AD5624R_SPI=m
# CONFIG_AD9739A is not set
CONFIG_LTC2688=m
CONFIG_AD5686=m
CONFIG_AD5686_SPI=m
CONFIG_AD5696_I2C=m
CONFIG_AD5755=m
CONFIG_AD5758=m
CONFIG_AD5761=m
CONFIG_AD5764=m
CONFIG_AD5766=m
CONFIG_AD5770R=m
CONFIG_AD5791=m
CONFIG_AD7293=m
CONFIG_AD7303=m
CONFIG_AD8801=m
CONFIG_DPOT_DAC=m
CONFIG_DS4424=m
CONFIG_LTC1660=m
CONFIG_LTC2632=m
# CONFIG_LTC2664 is not set
CONFIG_M62332=m
CONFIG_MAX517=m
# CONFIG_MAX5522 is not set
CONFIG_MAX5821=m
CONFIG_MCP4725=m
# CONFIG_MCP4728 is not set
# CONFIG_MCP4821 is not set
CONFIG_MCP4922=m
CONFIG_TI_DAC082S085=m
CONFIG_TI_DAC5571=m
CONFIG_TI_DAC7311=m
CONFIG_TI_DAC7612=m
CONFIG_VF610_DAC=m
# end of Digital to analog converters

#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver

#
# Filters
#
CONFIG_ADMV8818=m
# end of Filters

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
CONFIG_AD9523=m
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4350=m
CONFIG_ADF4371=m
# CONFIG_ADF4377 is not set
# CONFIG_ADMFM2000 is not set
CONFIG_ADMV1013=m
CONFIG_ADMV1014=m
CONFIG_ADMV4420=m
CONFIG_ADRF6780=m
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=m
CONFIG_ADIS16130=m
CONFIG_ADIS16136=m
CONFIG_ADIS16260=m
CONFIG_ADXRS290=m
CONFIG_ADXRS450=m
CONFIG_BMG160=m
CONFIG_BMG160_I2C=m
CONFIG_BMG160_SPI=m
CONFIG_FXAS21002C=m
CONFIG_FXAS21002C_I2C=m
CONFIG_FXAS21002C_SPI=m
CONFIG_HID_SENSOR_GYRO_3D=m
CONFIG_MPU3050=m
CONFIG_MPU3050_I2C=m
CONFIG_IIO_ST_GYRO_3AXIS=m
CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
CONFIG_ITG3200=m
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
CONFIG_AFE4403=m
CONFIG_AFE4404=m
CONFIG_MAX30100=m
CONFIG_MAX30102=m
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
CONFIG_AM2315=m
CONFIG_DHT11=m
# CONFIG_ENS210 is not set
CONFIG_HDC100X=m
CONFIG_HDC2010=m
# CONFIG_HDC3020 is not set
CONFIG_HID_SENSOR_HUMIDITY=m
CONFIG_HTS221=m
CONFIG_HTS221_I2C=m
CONFIG_HTS221_SPI=m
CONFIG_HTU21=m
CONFIG_SI7005=m
CONFIG_SI7020=m
# end of Humidity sensors

#
# Inertial measurement units
#
CONFIG_ADIS16400=m
CONFIG_ADIS16460=m
CONFIG_ADIS16475=m
CONFIG_ADIS16480=m
CONFIG_BMI160=m
CONFIG_BMI160_I2C=m
CONFIG_BMI160_SPI=m
# CONFIG_BMI323_I2C is not set
# CONFIG_BMI323_SPI is not set
CONFIG_BOSCH_BNO055=m
CONFIG_BOSCH_BNO055_SERIAL=m
CONFIG_BOSCH_BNO055_I2C=m
CONFIG_FXOS8700=m
CONFIG_FXOS8700_I2C=m
CONFIG_FXOS8700_SPI=m
CONFIG_KMX61=m
CONFIG_INV_ICM42600=m
CONFIG_INV_ICM42600_I2C=m
CONFIG_INV_ICM42600_SPI=m
CONFIG_INV_MPU6050_IIO=m
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_SPI=m
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_LSM6DSX_I2C=m
CONFIG_IIO_ST_LSM6DSX_SPI=m
CONFIG_IIO_ST_LSM9DS0=m
CONFIG_IIO_ST_LSM9DS0_I2C=m
CONFIG_IIO_ST_LSM9DS0_SPI=m
# end of Inertial measurement units

CONFIG_IIO_ADIS_LIB=m
CONFIG_IIO_ADIS_LIB_BUFFER=y

#
# Light sensors
#
CONFIG_ACPI_ALS=m
CONFIG_ADJD_S311=m
CONFIG_ADUX1020=m
CONFIG_AL3010=m
CONFIG_AL3320A=m
CONFIG_APDS9300=m
# CONFIG_APDS9306 is not set
CONFIG_APDS9960=m
CONFIG_AS73211=m
# CONFIG_BH1745 is not set
CONFIG_BH1750=m
CONFIG_BH1780=m
CONFIG_CM32181=m
CONFIG_CM3232=m
CONFIG_CM3323=m
CONFIG_CM3605=m
CONFIG_CM36651=m
CONFIG_GP2AP002=m
CONFIG_GP2AP020A00F=m
CONFIG_SENSORS_ISL29018=m
CONFIG_SENSORS_ISL29028=m
CONFIG_ISL29125=m
# CONFIG_ISL76682 is not set
CONFIG_HID_SENSOR_ALS=m
CONFIG_HID_SENSOR_PROX=m
CONFIG_JSA1212=m
# CONFIG_ROHM_BU27008 is not set
# CONFIG_ROHM_BU27034 is not set
CONFIG_RPR0521=m
# CONFIG_LTR390 is not set
CONFIG_LTR501=m
CONFIG_LTRF216A=m
CONFIG_LV0104CS=m
CONFIG_MAX44000=m
CONFIG_MAX44009=m
CONFIG_NOA1305=m
CONFIG_OPT3001=m
# CONFIG_OPT4001 is not set
CONFIG_PA12203001=m
CONFIG_SI1133=m
CONFIG_SI1145=m
CONFIG_STK3310=m
CONFIG_ST_UVIS25=m
CONFIG_ST_UVIS25_I2C=m
CONFIG_ST_UVIS25_SPI=m
CONFIG_TCS3414=m
CONFIG_TCS3472=m
CONFIG_SENSORS_TSL2563=m
CONFIG_TSL2583=m
CONFIG_TSL2591=m
CONFIG_TSL2772=m
CONFIG_TSL4531=m
CONFIG_US5182D=m
CONFIG_VCNL4000=m
CONFIG_VCNL4035=m
CONFIG_VEML6030=m
# CONFIG_VEML6040 is not set
CONFIG_VEML6070=m
# CONFIG_VEML6075 is not set
CONFIG_VL6180=m
CONFIG_ZOPT2201=m
# end of Light sensors

#
# Magnetometer sensors
#
# CONFIG_AF8133J is not set
CONFIG_AK8974=m
CONFIG_AK8975=m
CONFIG_AK09911=m
CONFIG_BMC150_MAGN=m
CONFIG_BMC150_MAGN_I2C=m
CONFIG_BMC150_MAGN_SPI=m
CONFIG_MAG3110=m
CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
CONFIG_MMC35240=m
CONFIG_IIO_ST_MAGN_3AXIS=m
CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
CONFIG_SENSORS_HMC5843=m
CONFIG_SENSORS_HMC5843_I2C=m
CONFIG_SENSORS_HMC5843_SPI=m
CONFIG_SENSORS_RM3100=m
CONFIG_SENSORS_RM3100_I2C=m
CONFIG_SENSORS_RM3100_SPI=m
# CONFIG_TI_TMAG5273 is not set
CONFIG_YAMAHA_YAS530=m
# end of Magnetometer sensors

#
# Multiplexers
#
CONFIG_IIO_MUX=m
# end of Multiplexers

#
# Inclinometer sensors
#
CONFIG_HID_SENSOR_INCLINOMETER_3D=m
CONFIG_HID_SENSOR_DEVICE_ROTATION=m
# end of Inclinometer sensors

#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=m
CONFIG_IIO_INTERRUPT_TRIGGER=m
CONFIG_IIO_TIGHTLOOP_TRIGGER=m
CONFIG_IIO_SYSFS_TRIGGER=y
# end of Triggers - standalone

#
# Linear and angular position sensors
#
CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
# end of Linear and angular position sensors

#
# Digital potentiometers
#
CONFIG_AD5110=m
CONFIG_AD5272=m
CONFIG_DS1803=m
CONFIG_MAX5432=m
CONFIG_MAX5481=m
CONFIG_MAX5487=m
CONFIG_MCP4018=m
CONFIG_MCP4131=m
CONFIG_MCP4531=m
CONFIG_MCP41010=m
CONFIG_TPL0102=m
# CONFIG_X9250 is not set
# end of Digital potentiometers

#
# Digital potentiostats
#
CONFIG_LMP91000=m
# end of Digital potentiostats

#
# Pressure sensors
#
CONFIG_ABP060MG=m
# CONFIG_ROHM_BM1390 is not set
CONFIG_BMP280=m
CONFIG_BMP280_I2C=m
CONFIG_BMP280_SPI=m
CONFIG_DLHL60D=m
CONFIG_DPS310=m
CONFIG_HID_SENSOR_PRESS=m
CONFIG_HP03=m
# CONFIG_HSC030PA is not set
CONFIG_ICP10100=m
CONFIG_MPL115=m
CONFIG_MPL115_I2C=m
CONFIG_MPL115_SPI=m
CONFIG_MPL3115=m
# CONFIG_MPRLS0025PA is not set
CONFIG_MS5611=m
CONFIG_MS5611_I2C=m
CONFIG_MS5611_SPI=m
CONFIG_MS5637=m
# CONFIG_SDP500 is not set
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_PRESS_I2C=m
CONFIG_IIO_ST_PRESS_SPI=m
CONFIG_T5403=m
CONFIG_HP206C=m
CONFIG_ZPA2326=m
CONFIG_ZPA2326_I2C=m
CONFIG_ZPA2326_SPI=m
# end of Pressure sensors

#
# Lightning sensors
#
CONFIG_AS3935=m
# end of Lightning sensors

#
# Proximity and distance sensors
#
# CONFIG_HX9023S is not set
# CONFIG_IRSD200 is not set
CONFIG_ISL29501=m
CONFIG_LIDAR_LITE_V2=m
CONFIG_MB1232=m
CONFIG_PING=m
CONFIG_RFD77402=m
CONFIG_SRF04=m
CONFIG_SX_COMMON=m
CONFIG_SX9310=m
CONFIG_SX9324=m
CONFIG_SX9360=m
CONFIG_SX9500=m
CONFIG_SRF08=m
CONFIG_VCNL3020=m
CONFIG_VL53L0X_I2C=m
# CONFIG_AW96103 is not set
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
CONFIG_AD2S90=m
CONFIG_AD2S1200=m
# CONFIG_AD2S1210 is not set
# end of Resolver to digital converters

#
# Temperature sensors
#
CONFIG_LTC2983=m
CONFIG_MAXIM_THERMOCOUPLE=m
CONFIG_HID_SENSOR_TEMP=m
CONFIG_MLX90614=m
CONFIG_MLX90632=m
# CONFIG_MLX90635 is not set
CONFIG_TMP006=m
CONFIG_TMP007=m
CONFIG_TMP117=m
CONFIG_TSYS01=m
CONFIG_TSYS02D=m
# CONFIG_MAX30208 is not set
CONFIG_MAX31856=m
CONFIG_MAX31865=m
# CONFIG_MCP9600 is not set
# end of Temperature sensors

# CONFIG_NTB is not set
CONFIG_PWM=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_ATMEL_TCB is not set
CONFIG_PWM_CLK=y
CONFIG_PWM_DWC_CORE=y
CONFIG_PWM_DWC=y
# CONFIG_PWM_FSL_FTM is not set
# CONFIG_PWM_GPIO is not set
CONFIG_PWM_MESON=y
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_SUN4I=y
CONFIG_PWM_SUNXI_ENHANCE=m
# CONFIG_PWM_XILINX is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_IRQ_MSI_LIB=y
# CONFIG_AL_FIC is not set
CONFIG_SUN6I_R_INTC=y
CONFIG_SUNXI_NMI_INTC=y
# CONFIG_XILINX_INTC is not set
CONFIG_PARTITION_PERCPU=y
CONFIG_MESON_IRQ_GPIO=y
# end of IRQ chip support

# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_GPIO=y
CONFIG_RESET_SCMI=y
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SUNXI=y
# CONFIG_RESET_TI_SYSCON is not set
# CONFIG_RESET_TI_TPS380X is not set
CONFIG_RESET_MESON_COMMON=y
CONFIG_RESET_MESON=y
CONFIG_RESET_MESON_AUX=y
CONFIG_RESET_MESON_AUDIO_ARB=y

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_PHY_CAN_TRANSCEIVER is not set
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_SUN6I_MIPI_DPHY=y
CONFIG_PHY_SUN9I_USB=y
CONFIG_PHY_SUN50I_USB3=y
CONFIG_AC200_PHY_CTL=m
CONFIG_PHY_MESON8B_USB2=y
CONFIG_PHY_MESON_GXL_USB2=y
CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=y
CONFIG_PHY_MESON_G12A_USB2=y
CONFIG_PHY_MESON_G12A_USB3_PCIE=y
CONFIG_PHY_MESON_AXG_PCIE=y
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
CONFIG_PHY_MESON_AXG_MIPI_DPHY=y

#
# PHY drivers for Broadcom platforms
#
# CONFIG_BCM_KONA_USB2_PHY is not set
# end of PHY drivers for Broadcom platforms

# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_DPHY_RX is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_LAN966X_SERDES is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
# CONFIG_PHY_QCOM_USB_HS is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
CONFIG_PHY_ROCKCHIP_DP=y
CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
CONFIG_PHY_ROCKCHIP_PCIE=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY=m
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=m
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
CONFIG_PHY_ROCKCHIP_TYPEC=m
CONFIG_PHY_ROCKCHIP_USB=y
CONFIG_PHY_ROCKCHIP_USBDP=m
# CONFIG_PHY_SAMSUNG_USB2 is not set
# CONFIG_PHY_TUSB1210 is not set
# end of PHY Subsystem

# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCI400_PMU=y
CONFIG_ARM_CCI5xx_PMU=y
CONFIG_ARM_CCN=m
CONFIG_ARM_CMN=m
CONFIG_ARM_NI=m
CONFIG_ARM_PMU=y
CONFIG_ARM_PMU_ACPI=y
CONFIG_ARM_SMMU_V3_PMU=y
CONFIG_ARM_PMUV3=y
CONFIG_ARM_DSU_PMU=m
CONFIG_ARM_SPE_PMU=m
# CONFIG_ARM_DMC620_PMU is not set
# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set
# CONFIG_HISI_PMU is not set
# CONFIG_HISI_PCIE_PMU is not set
# CONFIG_HNS3_PMU is not set
# CONFIG_DWC_PCIE_PMU is not set
# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set
# CONFIG_MESON_DDR_PMU is not set
# end of Performance monitor support

CONFIG_RAS=y
# CONFIG_USB4 is not set

#
# Android
#
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_BINDERFS=y
CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
# end of Android

# CONFIG_LIBNVDIMM is not set
CONFIG_DAX=y
CONFIG_DEV_DAX=m
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_NVMEM_LAYOUTS=y

#
# Layout Types
#
CONFIG_NVMEM_LAYOUT_SL28_VPD=m
CONFIG_NVMEM_LAYOUT_ONIE_TLV=m
CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y
# end of Layout Types

CONFIG_NVMEM_MESON_EFUSE=y
CONFIG_NVMEM_MESON_MX_EFUSE=y
CONFIG_NVMEM_RMEM=y
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
CONFIG_NVMEM_ROCKCHIP_OTP=y
CONFIG_NVMEM_SPMI_SDAM=y
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_NVMEM_U_BOOT_ENV=y

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# CONFIG_HISI_PTT is not set
# end of HW tracing support

CONFIG_FPGA=m
CONFIG_ALTERA_PR_IP_CORE=m
CONFIG_ALTERA_PR_IP_CORE_PLAT=m
CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
CONFIG_FPGA_MGR_ALTERA_CVP=m
CONFIG_FPGA_MGR_XILINX_CORE=m
# CONFIG_FPGA_MGR_XILINX_SELECTMAP is not set
CONFIG_FPGA_MGR_XILINX_SPI=m
CONFIG_FPGA_MGR_ICE40_SPI=m
CONFIG_FPGA_MGR_MACHXO2_SPI=m
CONFIG_FPGA_BRIDGE=m
CONFIG_ALTERA_FREEZE_BRIDGE=m
CONFIG_XILINX_PR_DECOUPLER=m
CONFIG_FPGA_REGION=m
CONFIG_OF_FPGA_REGION=m
CONFIG_FPGA_DFL=m
CONFIG_FPGA_DFL_FME=m
CONFIG_FPGA_DFL_FME_MGR=m
CONFIG_FPGA_DFL_FME_BRIDGE=m
CONFIG_FPGA_DFL_FME_REGION=m
CONFIG_FPGA_DFL_AFU=m
CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m
CONFIG_FPGA_DFL_PCI=m
CONFIG_FPGA_MGR_MICROCHIP_SPI=m
# CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI is not set
# CONFIG_FSI is not set
CONFIG_TEE=y
CONFIG_OPTEE=y
# CONFIG_OPTEE_INSECURE_LOAD_IMAGE is not set
# CONFIG_ARM_TSTEE is not set
CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
# CONFIG_MUX_ADGS1408 is not set
CONFIG_MUX_GPIO=m
CONFIG_MUX_MMIO=m
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set
# CONFIG_INTERCONNECT is not set
CONFIG_COUNTER=m
CONFIG_INTERRUPT_CNT=m
# CONFIG_MOST is not set
# CONFIG_PECI is not set
# CONFIG_HTE is not set
# CONFIG_CDX_BUS is not set
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_IOMAP=y
CONFIG_FS_STACK=y
CONFIG_BUFFER_HEAD=y
CONFIG_LEGACY_DIRECT_IO=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=m
# CONFIG_REISERFS_CHECK is not set
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
# CONFIG_JFS_DEBUG is not set
# CONFIG_JFS_STATISTICS is not set
CONFIG_XFS_FS=y
CONFIG_XFS_SUPPORT_V4=y
CONFIG_XFS_SUPPORT_ASCII_CI=y
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
# CONFIG_XFS_RT is not set
# CONFIG_XFS_ONLINE_SCRUB is not set
# CONFIG_XFS_WARN is not set
# CONFIG_XFS_DEBUG is not set
CONFIG_GFS2_FS=m
CONFIG_GFS2_FS_LOCKING_DLM=y
CONFIG_OCFS2_FS=m
CONFIG_OCFS2_FS_O2CB=m
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
CONFIG_OCFS2_FS_STATS=y
CONFIG_OCFS2_DEBUG_MASKLOG=y
# CONFIG_OCFS2_DEBUG_FS is not set
CONFIG_BTRFS_FS=y
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
# CONFIG_BTRFS_FS_REF_VERIFY is not set
CONFIG_NILFS2_FS=m
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
# CONFIG_F2FS_FAULT_INJECTION is not set
CONFIG_F2FS_FS_COMPRESSION=y
CONFIG_F2FS_FS_LZO=y
CONFIG_F2FS_FS_LZORLE=y
CONFIG_F2FS_FS_LZ4=y
CONFIG_F2FS_FS_LZ4HC=y
CONFIG_F2FS_FS_ZSTD=y
CONFIG_F2FS_IOSTAT=y
# CONFIG_F2FS_UNFAIR_RWSEM is not set
CONFIG_BCACHEFS_FS=m
CONFIG_BCACHEFS_QUOTA=y
# CONFIG_BCACHEFS_ERASURE_CODING is not set
CONFIG_BCACHEFS_POSIX_ACL=y
# CONFIG_BCACHEFS_DEBUG is not set
# CONFIG_BCACHEFS_TESTS is not set
CONFIG_BCACHEFS_LOCK_TIME_STATS=y
# CONFIG_BCACHEFS_NO_LATENCY_ACCT is not set
CONFIG_BCACHEFS_SIX_OPTIMISTIC_SPIN=y
# CONFIG_BCACHEFS_PATH_TRACEPOINTS is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
# CONFIG_FS_ENCRYPTION_INLINE_CRYPT is not set
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=m
# CONFIG_QFMT_V1 is not set
# CONFIG_QFMT_V2 is not set
CONFIG_QUOTACTL=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_VIRTIO_FS=m
CONFIG_FUSE_PASSTHROUGH=y
CONFIG_OVERLAY_FS=y
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set
# CONFIG_OVERLAY_FS_DEBUG is not set

#
# Caches
#
CONFIG_NETFS_SUPPORT=m
# CONFIG_NETFS_STATS is not set
# CONFIG_NETFS_DEBUG is not set
CONFIG_FSCACHE=y
# CONFIG_FSCACHE_STATS is not set
CONFIG_CACHEFILES=m
# CONFIG_CACHEFILES_DEBUG is not set
# CONFIG_CACHEFILES_ERROR_INJECTION is not set
# CONFIG_CACHEFILES_ONDEMAND is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
# CONFIG_FAT_DEFAULT_UTF8 is not set
CONFIG_EXFAT_FS=y
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_NTFS3_FS=m
# CONFIG_NTFS3_64BIT_CLUSTER is not set
CONFIG_NTFS3_LZX_XPRESS=y
CONFIG_NTFS3_FS_POSIX_ACL=y
# CONFIG_NTFS_FS is not set
# end of DOS/FAT/EXFAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_TMPFS_INODE64 is not set
# CONFIG_TMPFS_QUOTA is not set
CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_HUGETLB_PMD_PAGE_TABLE_SHARING=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=m
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
CONFIG_ECRYPT_FS=m
# CONFIG_ECRYPT_FS_MESSAGING is not set
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
CONFIG_UBIFS_FS=m
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
CONFIG_CRAMFS=m
CONFIG_CRAMFS_BLOCKDEV=y
# CONFIG_CRAMFS_MTD is not set
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_FILE_CACHE is not set
CONFIG_SQUASHFS_FILE_DIRECT=y
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set
CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_ZSTD=y
# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
CONFIG_PSTORE_COMPRESS=y
# CONFIG_PSTORE_CONSOLE is not set
# CONFIG_PSTORE_PMSG is not set
# CONFIG_PSTORE_RAM is not set
# CONFIG_PSTORE_BLK is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_EROFS_FS=m
# CONFIG_EROFS_FS_DEBUG is not set
CONFIG_EROFS_FS_XATTR=y
CONFIG_EROFS_FS_POSIX_ACL=y
# CONFIG_EROFS_FS_SECURITY is not set
CONFIG_EROFS_FS_BACKED_BY_FILE=y
CONFIG_EROFS_FS_ZIP=y
CONFIG_EROFS_FS_ZIP_LZMA=y
# CONFIG_EROFS_FS_ZIP_DEFLATE is not set
# CONFIG_EROFS_FS_ZIP_ZSTD is not set
# CONFIG_EROFS_FS_ONDEMAND is not set
# CONFIG_EROFS_FS_PCPU_KTHREAD is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V2=m
CONFIG_NFS_V3=m
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=m
# CONFIG_NFS_SWAP is not set
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=m
CONFIG_PNFS_BLOCK=m
CONFIG_PNFS_FLEXFILE_LAYOUT=m
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
# CONFIG_NFS_V4_1_MIGRATION is not set
CONFIG_NFS_V4_SECURITY_LABEL=y
CONFIG_NFS_FSCACHE=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DEBUG=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
CONFIG_NFS_V4_2_READ_PLUS=y
CONFIG_NFSD=m
# CONFIG_NFSD_V2 is not set
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
CONFIG_NFSD_PNFS=y
CONFIG_NFSD_BLOCKLAYOUT=y
CONFIG_NFSD_SCSILAYOUT=y
CONFIG_NFSD_FLEXFILELAYOUT=y
CONFIG_NFSD_V4_2_INTER_SSC=y
CONFIG_NFSD_V4_SECURITY_LABEL=y
# CONFIG_NFSD_LEGACY_CLIENT_TRACKING is not set
CONFIG_GRACE_PERIOD=m
CONFIG_LOCKD=m
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=m
CONFIG_NFS_COMMON=y
# CONFIG_NFS_LOCALIO is not set
CONFIG_NFS_V4_2_SSC_HELPER=y
CONFIG_SUNRPC=m
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_BACKCHANNEL=y
CONFIG_RPCSEC_GSS_KRB5=m
CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y
CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA=y
CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y
CONFIG_SUNRPC_DEBUG=y
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
# CONFIG_CEPH_FS_SECURITY_LABEL is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CIFS_DEBUG=y
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
CONFIG_CIFS_DFS_UPCALL=y
# CONFIG_CIFS_SWN_UPCALL is not set
# CONFIG_CIFS_FSCACHE is not set
# CONFIG_CIFS_COMPRESSION is not set
CONFIG_SMB_SERVER=m
CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
CONFIG_SMB_SERVER_KERBEROS5=y
CONFIG_SMBFS=m
CONFIG_CODA_FS=m
CONFIG_AFS_FS=m
# CONFIG_AFS_DEBUG is not set
CONFIG_AFS_FSCACHE=y
# CONFIG_AFS_DEBUG_CURSOR is not set
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
CONFIG_9P_FS_SECURITY=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf-8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=m
CONFIG_NLS_MAC_GAELIC=m
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=y
CONFIG_NLS_UCS2_UTILS=m
CONFIG_DLM=m
# CONFIG_DLM_DEBUG is not set
# CONFIG_UNICODE is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_BIG_KEYS is not set
# CONFIG_TRUSTED_KEYS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_PROC_MEM_ALWAYS_FORCE=y
# CONFIG_PROC_MEM_FORCE_PTRACE is not set
# CONFIG_PROC_MEM_NO_FORCE is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
# CONFIG_SECURITY_NETWORK_XFRM is not set
CONFIG_SECURITY_PATH=y
CONFIG_LSM_MMAP_MIN_ADDR=32768
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
# CONFIG_SECURITY_SELINUX_DEBUG is not set
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
CONFIG_SECURITY_APPARMOR=y
# CONFIG_SECURITY_APPARMOR_DEBUG is not set
CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y
CONFIG_SECURITY_APPARMOR_HASH=y
CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y
CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
# CONFIG_SECURITY_LANDLOCK is not set
# CONFIG_SECURITY_IPE is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
CONFIG_INTEGRITY_AUDIT=y
# CONFIG_IMA is not set
# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
# CONFIG_EVM is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
CONFIG_INIT_STACK_NONE=y
# CONFIG_INIT_STACK_ALL_PATTERN is not set
# CONFIG_INIT_STACK_ALL_ZERO is not set
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
# CONFIG_ZERO_CALL_USED_REGS is not set
# end of Memory initialization

#
# Hardening of kernel data structures
#
# CONFIG_LIST_HARDENED is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# end of Hardening of kernel data structures

CONFIG_RANDSTRUCT_NONE=y
# CONFIG_RANDSTRUCT_FULL is not set
# CONFIG_RANDSTRUCT_PERFORMANCE is not set
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=y
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SIG=y
CONFIG_CRYPTO_SIG2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=y
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_ENGINE=y
# end of Crypto core or helper

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=y
# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
CONFIG_CRYPTO_ECDSA=y
CONFIG_CRYPTO_ECRDSA=y
CONFIG_CRYPTO_CURVE25519=y
# end of Public-key cryptography

#
# Block ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
CONFIG_CRYPTO_ANUBIS=y
CONFIG_CRYPTO_ARIA=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_BLOWFISH_COMMON=y
CONFIG_CRYPTO_CAMELLIA=y
CONFIG_CRYPTO_CAST_COMMON=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=y
CONFIG_CRYPTO_KHAZAD=y
CONFIG_CRYPTO_SEED=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_GENERIC=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y
# end of Block ciphers

#
# Length-preserving ciphers and modes
#
CONFIG_CRYPTO_ADIANTUM=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HCTR2=y
CONFIG_CRYPTO_KEYWRAP=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XCTR=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_NHPOLY1305=y
# end of Length-preserving ciphers and modes

#
# AEAD (authenticated encryption with associated data) ciphers
#
CONFIG_CRYPTO_AEGIS128=y
CONFIG_CRYPTO_AEGIS128_SIMD=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_GENIV=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_ESSIV=y
# end of AEAD (authenticated encryption with associated data) ciphers

#
# Hashes, digests, and MACs
#
CONFIG_CRYPTO_BLAKE2B=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_POLYVAL=y
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_RMD160=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_SM3_GENERIC=y
CONFIG_CRYPTO_STREEBOG=y
CONFIG_CRYPTO_VMAC=y
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_XXHASH=y
# end of Hashes, digests, and MACs

#
# CRCs (cyclic redundancy checks)
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
# end of CRCs (cyclic redundancy checks)

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=y
CONFIG_CRYPTO_ZSTD=y
# end of Compression

#
# Random number generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32
CONFIG_CRYPTO_JITTERENTROPY_OSR=1
# end of Random number generation

#
# Userspace interface
#
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
# end of Userspace interface

CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_NHPOLY1305_NEON=y
CONFIG_CRYPTO_CHACHA20_NEON=y

#
# Accelerated Cryptographic Algorithms for CPU (arm64)
#
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_POLY1305_NEON=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA512_ARM64_CE=y
CONFIG_CRYPTO_SHA3_ARM64=y
CONFIG_CRYPTO_SM3_NEON=y
CONFIG_CRYPTO_SM3_ARM64_CE=y
CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CRYPTO_SM4_ARM64_CE=y
CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y
CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
# end of Accelerated Cryptographic Algorithms for CPU (arm64)

CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_ALLWINNER=y
CONFIG_CRYPTO_DEV_SUN4I_SS=y
CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set
CONFIG_CRYPTO_DEV_SUN8I_CE=y
CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG=y
CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
CONFIG_CRYPTO_DEV_SUN8I_SS=y
CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG=y
CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_CCP is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set
# CONFIG_CRYPTO_DEV_QAT_C62X is not set
# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
# CONFIG_CRYPTO_DEV_QAT_420XX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set
# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_ROCKCHIP=m
# CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG is not set
CONFIG_CRYPTO_DEV_VIRTIO=m
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
CONFIG_CRYPTO_DEV_CCREE=y
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
# CONFIG_CRYPTO_DEV_HISI_TRNG is not set
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG=y
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
CONFIG_PKCS7_MESSAGE_PARSER=y
CONFIG_PKCS7_TEST_KEY=m
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
# CONFIG_FIPS_SIGNATURE_SELFTEST is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_RAID6_PQ=y
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=m
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
CONFIG_INDIRECT_PIO=y
# CONFIG_TRACE_MMIO_ACCESS is not set

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA_INTERNAL=y
CONFIG_CRYPTO_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
CONFIG_CRYPTO_LIB_CURVE25519_INTERNAL=y
CONFIG_CRYPTO_LIB_CURVE25519=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305_INTERNAL=y
CONFIG_CRYPTO_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines

CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC64_ROCKSOFT=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=y
CONFIG_CRC4=m
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=y
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
CONFIG_RANDOM32_SELFTEST=y
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_ARM64=y
# CONFIG_XZ_DEC_SPARC is not set
CONFIG_XZ_DEC_RISCV=y
CONFIG_XZ_DEC_MICROLZMA=y
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_INTERVAL_TREE=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_CLOSURES=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS_HELPERS=y
CONFIG_NEED_SG_DMA_FLAGS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_SWIOTLB=y
# CONFIG_SWIOTLB_DYNAMIC is not set
CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
CONFIG_DMA_NEED_SYNC=y
# CONFIG_DMA_RESTRICTED_POOL is not set
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=256
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_DMA_MAP_BENCHMARK is not set
CONFIG_SGL_ALLOC=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_DIMLIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_VDSO_GETRANDOM=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_ARCH_HAS_PMEM_API=y
CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_STACKDEPOT=y
CONFIG_STACKDEPOT_MAX_FRAMES=64
CONFIG_SBITMAP=y
# CONFIG_LWQ_TEST is not set
# end of Library routines

CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_FIRMWARE_TABLE=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_CALLER is not set
# CONFIG_STACKTRACE_BUILD_ID is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
CONFIG_AS_HAS_NON_CONST_ULEB128=y
# CONFIG_DEBUG_INFO_NONE is not set
# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
CONFIG_DEBUG_INFO_DWARF5=y
# CONFIG_DEBUG_INFO_REDUCED is not set
CONFIG_DEBUG_INFO_COMPRESSED_NONE=y
# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set
# CONFIG_DEBUG_INFO_COMPRESSED_ZSTD is not set
# CONFIG_DEBUG_INFO_SPLIT is not set
CONFIG_DEBUG_INFO_BTF=y
CONFIG_PAHOLE_HAS_SPLIT_BTF=y
CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
CONFIG_DEBUG_INFO_BTF_MODULES=y
CONFIG_MODULE_ALLOW_BTF_MISMATCH=y
# CONFIG_GDB_SCRIPTS is not set
CONFIG_FRAME_WARN=2048
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_READABLE_ASM is not set
CONFIG_HEADERS_INSTALL=y
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_VMLINUX_MAP is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_ARCH_KCSAN=y
CONFIG_HAVE_KCSAN_COMPILER=y
# CONFIG_KCSAN is not set
# end of Generic Kernel Debugging Instruments

#
# Networking Debugging
#
# CONFIG_NET_DEV_REFCNT_TRACKER is not set
# CONFIG_NET_NS_REFCNT_TRACKER is not set
# CONFIG_DEBUG_NET is not set
# end of Networking Debugging

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_SLUB_DEBUG=y
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_PER_VMA_LOCK_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SHRINKER_DEBUG is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
# CONFIG_MEM_ALLOC_PROFILING is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
# end of Memory Debugging

# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SOFTLOCKUP_DETECTOR is not set
CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y
# CONFIG_HARDLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHED_INFO=y
# CONFIG_SCHEDSTATS is not set
# end of Scheduler Debugging

# CONFIG_DEBUG_PREEMPT is not set

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

# CONFIG_DEBUG_IRQFLAGS is not set
CONFIG_STACKTRACE=y
# CONFIG_DEBUG_KOBJECT is not set

#
# Debug kernel data structures
#
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CLOSURES is not set
# CONFIG_DEBUG_MAPLE_TREE is not set
# end of Debug kernel data structures

#
# RCU Debugging
#
# CONFIG_RCU_SCALE_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
# CONFIG_RCU_CPU_STALL_CPUTIME is not set
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_LATENCYTOP is not set
# CONFIG_DEBUG_CGROUP_REF is not set
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_FREGS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_TRACING=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_BOOTTIME_TRACING is not set
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_PREEMPT_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_HWLAT_TRACER is not set
# CONFIG_OSNOISE_TRACER is not set
# CONFIG_TIMERLAT_TRACER is not set
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
# CONFIG_FTRACE_SYSCALLS is not set
# CONFIG_TRACER_SNAPSHOT is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_PROBE_EVENTS_BTF_ARGS=y
CONFIG_KPROBE_EVENTS=y
CONFIG_UPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_DYNAMIC_EVENTS=y
CONFIG_PROBE_EVENTS=y
# CONFIG_SYNTH_EVENTS is not set
# CONFIG_USER_EVENTS is not set
# CONFIG_HIST_TRIGGERS is not set
# CONFIG_TRACE_EVENT_INJECT is not set
# CONFIG_TRACEPOINT_BENCHMARK is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_TRACE_EVAL_MAP_FILE is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
# CONFIG_KPROBE_EVENT_GEN_TEST is not set
# CONFIG_RV is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y
CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y
# CONFIG_STRICT_DEVMEM is not set

#
# arm64 Debugging
#
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_DEBUG_EFI is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
# end of arm64 Debugging

#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FUNCTION_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_TEST_DHRY is not set
# CONFIG_LKDTM is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_DIV64 is not set
# CONFIG_TEST_MULDIV64 is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TEST_REF_TRACKER is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_ASYNC_RAID6_TEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_SCANF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_MAPLE_TREE is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_VMALLOC is not set
CONFIG_TEST_BPF=m
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_DYNAMIC_DEBUG is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_FREE_PAGES is not set
# CONFIG_TEST_FPU is not set
# CONFIG_TEST_OBJPOOL is not set
CONFIG_ARCH_USE_MEMTEST=y
CONFIG_MEMTEST=y
# end of Kernel Testing and Coverage

#
# Rust hacking
#
# end of Rust hacking
# end of Kernel hacking


================================================
FILE: kernel-config/release/stable/config-6.18
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 6.18.20 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 15.2.Rel1 (Build arm-15.86)) 15.2.1 20251203"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=150201
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=24501
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=24501
CONFIG_LLD_VERSION=0
CONFIG_RUSTC_VERSION=0
CONFIG_RUSTC_LLVM_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_TOOLS_SUPPORT_RELR=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_ASSUME=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_CC_HAS_COUNTED_BY=y
CONFIG_CC_HAS_MULTIDIMENSIONAL_NONSTRING=y
CONFIG_LD_CAN_USE_KEEP_IN_OVERLAY=y
CONFIG_PAHOLE_VERSION=130
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
# CONFIG_UAPI_HEADER_TEST is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
# CONFIG_WATCH_QUEUE is not set
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_SIM=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
CONFIG_GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD=y
# end of IRQ subsystem

CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_HZ_PERIODIC=y
# CONFIG_NO_HZ_IDLE is not set
# CONFIG_NO_HZ_FULL is not set
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
# CONFIG_POSIX_AUX_CLOCKS is not set
# end of Timers subsystem

CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y

#
# BPF subsystem
#
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_JIT=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
CONFIG_BPF_JIT_DEFAULT_ON=y
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
# CONFIG_BPF_PRELOAD is not set
# CONFIG_BPF_LSM is not set
# end of BPF subsystem

CONFIG_PREEMPT_BUILD=y
CONFIG_ARCH_HAS_PREEMPT_LAZY=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
# CONFIG_PREEMPT_LAZY is not set
# CONFIG_PREEMPT_RT is not set
CONFIG_PREEMPT_COUNT=y
CONFIG_PREEMPTION=y
CONFIG_PREEMPT_DYNAMIC=y
CONFIG_SCHED_CLASS_EXT=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_SCHED_HW_PRESSURE=y
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
CONFIG_PREEMPT_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_NEED_TASKS_RCU=y
CONFIG_TASKS_RCU=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
# CONFIG_PRINTK_INDEX is not set
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
# CONFIG_UCLAMP_TASK is not set
# end of Scheduler features

CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
CONFIG_CC_HAS_INT128=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_GCC10_NO_ARRAY_BOUNDS=y
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_GCC_NO_STRINGOP_OVERFLOW=y
CONFIG_CC_NO_STRINGOP_OVERFLOW=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_SLAB_OBJ_EXT=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
CONFIG_MEMCG=y
CONFIG_MEMCG_V1=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_GROUP_SCHED_WEIGHT=y
CONFIG_GROUP_SCHED_BANDWIDTH=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
# CONFIG_RT_GROUP_SCHED_DEFAULT_DISABLED is not set
CONFIG_EXT_GROUP_SCHED=y
CONFIG_SCHED_MM_CID=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
# CONFIG_CGROUP_DMEM is not set
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CPUSETS=y
CONFIG_CPUSETS_V1=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
CONFIG_CGROUP_MISC=y
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
# CONFIG_CHECKPOINT_RESTORE is not set
CONFIG_SCHED_AUTOGROUP=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
# CONFIG_BOOT_CONFIG_FORCE is not set
# CONFIG_BOOT_CONFIG_EMBED is not set
CONFIG_INITRAMFS_PRESERVE_MTIME=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
# CONFIG_BASE_SMALL is not set
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_FUTEX_PRIVATE_HASH=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
# CONFIG_IO_URING_MOCK_FILE is not set
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
# CONFIG_DEBUG_RSEQ is not set
CONFIG_CACHESTAT_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_SELFTEST is not set
# CONFIG_KALLSYMS_ALL is not set
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_GUEST_PERF_EVENTS=y

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y

#
# Kexec and crash features
#
# CONFIG_KEXEC_FILE is not set
# CONFIG_KEXEC_HANDOVER is not set
# end of Kexec and crash features
# end of General setup

CONFIG_ARM64=y
CONFIG_RUSTC_SUPPORTS_ARM64=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_CONT_PTE_SHIFT=4
CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y

#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
# CONFIG_ARCH_AIROHA is not set
CONFIG_ARCH_SUNXI=y
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_APPLE is not set
# CONFIG_ARCH_AXIADO is not set
# CONFIG_ARCH_BCM is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
# CONFIG_ARCH_BLAIZE is not set
# CONFIG_ARCH_CIX is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_KEEMBAY is not set
# CONFIG_ARCH_MEDIATEK is not set
CONFIG_ARCH_MESON=y

#
# Microchip SoC support
#
# CONFIG_ARCH_LAN969X is not set
# CONFIG_ARCH_SPARX5 is not set
# end of Microchip SoC support

# CONFIG_ARCH_MMP is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_NXP is not set
# CONFIG_ARCH_MA35 is not set
# CONFIG_ARCH_NPCM is not set
# CONFIG_ARCH_PENSANDO is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_RENESAS is not set
CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_INTEL_SOCFPGA is not set
# CONFIG_ARCH_SOPHGO is not set
# CONFIG_ARCH_STM32 is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZYNQMP is not set
# end of Platform selection

#
# Kernel Features
#

#
# ARM errata workarounds via the alternatives framework
#
CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y
CONFIG_AMPERE_ERRATUM_AC04_CPU_23=y
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_834220=y
CONFIG_ARM64_ERRATUM_1742098=y
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1319367=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_ERRATUM_2441007=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_ARM64_ERRATUM_2051678=y
CONFIG_ARM64_ERRATUM_2077057=y
CONFIG_ARM64_ERRATUM_2658417=y
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
CONFIG_ARM64_ERRATUM_2054223=y
CONFIG_ARM64_ERRATUM_2067961=y
CONFIG_ARM64_ERRATUM_2441009=y
CONFIG_ARM64_ERRATUM_2457168=y
CONFIG_ARM64_ERRATUM_2645198=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y
CONFIG_ARM64_ERRATUM_2966298=y
CONFIG_ARM64_ERRATUM_3117295=y
CONFIG_ARM64_ERRATUM_3194386=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_HISILICON_ERRATUM_162100801=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
CONFIG_QCOM_FALKOR_ERRATUM_1009=y
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
CONFIG_ROCKCHIP_ERRATUM_3568002=y
CONFIG_ROCKCHIP_ERRATUM_3588001=y
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
# end of ARM errata workarounds via the alternatives framework

CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
# CONFIG_ARM64_VA_BITS_39 is not set
CONFIG_ARM64_VA_BITS_48=y
# CONFIG_ARM64_VA_BITS_52 is not set
CONFIG_ARM64_VA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_NR_CPUS=8
# CONFIG_HOTPLUG_CPU is not set
# CONFIG_NUMA is not set
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
CONFIG_HZ_300=y
# CONFIG_HZ_1000 is not set
CONFIG_HZ=300
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_PARAVIRT=y
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y
CONFIG_ARCH_SUPPORTS_KEXEC_SIG=y
CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG=y
CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
CONFIG_ARCH_SUPPORTS_KEXEC_HANDOVER=y
CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y
CONFIG_ARCH_DEFAULT_CRASH_DUMP=y
# CONFIG_XEN is not set
CONFIG_ARCH_FORCE_MAX_ORDER=10
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y
CONFIG_COMPAT_ALIGNMENT_FIXUPS=y
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y

#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
CONFIG_ARM64_LSE_ATOMICS=y
CONFIG_ARM64_USE_LSE_ATOMICS=y
# end of ARMv8.1 architectural features

#
# ARMv8.2 architectural features
#
CONFIG_ARM64_PMEM=y
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features

#
# ARMv8.3 architectural features
#
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
# end of ARMv8.3 architectural features

#
# ARMv8.4 architectural features
#
CONFIG_ARM64_AMU_EXTN=y
CONFIG_ARM64_TLB_RANGE=y
# end of ARMv8.4 architectural features

#
# ARMv8.5 architectural features
#
CONFIG_AS_HAS_ARMV8_5=y
CONFIG_ARM64_BTI=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARM64_AS_HAS_MTE=y
CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features

#
# ARMv8.7 architectural features
#
CONFIG_ARM64_EPAN=y
# end of ARMv8.7 architectural features

CONFIG_AS_HAS_MOPS=y

#
# ARMv8.9 architectural features
#
CONFIG_ARM64_POE=y
CONFIG_ARCH_PKEY_BITS=3
CONFIG_ARM64_HAFT=y
# end of ARMv8.9 architectural features

#
# ARMv9.4 architectural features
#
CONFIG_ARM64_GCS=y
# end of ARMv9.4 architectural features

CONFIG_ARM64_SVE=y
CONFIG_ARM64_SME=y
CONFIG_ARM64_PSEUDO_NMI=y
# CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
CONFIG_ARM64_CONTPTE=y
# end of Kernel Features

#
# Boot options
#
CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
CONFIG_CMDLINE=""
CONFIG_EFI_STUB=y
CONFIG_EFI=y
CONFIG_COMPRESSED_INSTALL=y
CONFIG_DMI=y
# end of Boot options

#
# Power management options
#
# CONFIG_SUSPEND is not set
# CONFIG_HIBERNATION is not set
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options

#
# CPU Power Management
#

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_IDLE_GOV_LADDER=y
# CONFIG_CPU_IDLE_GOV_MENU is not set
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_DT_IDLE_STATES=y
CONFIG_DT_IDLE_GENPD=y

#
# ARM CPU Idle Drivers
#
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
# end of ARM CPU Idle Drivers
# end of CPU Idle

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
# CONFIG_CPUFREQ_VIRT is not set
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_SCMI_CPUFREQ=y
# CONFIG_ACPI_CPPC_CPUFREQ is not set
# end of CPU Frequency scaling
# end of CPU Power Management

CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_GENERIC_GSI=y
CONFIG_ACPI_CCA_REQUIRED=y
CONFIG_ACPI_THERMAL_LIB=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
# CONFIG_ACPI_FPDT is not set
# CONFIG_ACPI_EC is not set
CONFIG_ACPI_AC=m
CONFIG_ACPI_BATTERY=m
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_VIDEO=m
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_MCFG=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_THERMAL=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_PCI_SLOT=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_BGRT=y
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
# CONFIG_ACPI_NFIT is not set
CONFIG_HAVE_ACPI_APEI=y
CONFIG_ACPI_APEI=y
CONFIG_ACPI_APEI_GHES=y
CONFIG_ACPI_APEI_SEA=y
CONFIG_ACPI_APEI_MEMORY_FAILURE=y
CONFIG_ACPI_APEI_EINJ=m
CONFIG_ACPI_APEI_ERST_DEBUG=m
CONFIG_ACPI_CONFIGFS=m
CONFIG_ACPI_PFRUT=m
CONFIG_ACPI_IORT=y
CONFIG_ACPI_GTDT=y
# CONFIG_ACPI_AGDI is not set
CONFIG_ACPI_APMT=y
CONFIG_ACPI_PPTT=y
CONFIG_ACPI_PCC=y
# CONFIG_ACPI_FFH is not set
CONFIG_PMIC_OPREGION=y
CONFIG_ACPI_VIOT=y
CONFIG_ACPI_PRMT=y
CONFIG_KVM_COMMON=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_DIRTY_RING=y
CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y
CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP=y
CONFIG_KVM_MMIO=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_READONLY_MEM=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_VIRT_XFER_TO_GUEST_WORK=y
CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y
CONFIG_KVM_GENERIC_MMU_NOTIFIER=y
CONFIG_KVM_GUEST_MEMFD=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
# CONFIG_NVHE_EL2_DEBUG is not set
# CONFIG_PTDUMP_STAGE2_DEBUGFS is not set
CONFIG_HAVE_LIVEPATCH=y
CONFIG_CPU_MITIGATIONS=y

#
# General architecture-dependent options
#
CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y
CONFIG_ARCH_SUPPORTS_SCHED_SMT=y
CONFIG_ARCH_SUPPORTS_SCHED_CLUSTER=y
CONFIG_ARCH_SUPPORTS_SCHED_MC=y
# CONFIG_SCHED_SMT is not set
CONFIG_SCHED_CLUSTER=y
CONFIG_SCHED_MC=y
CONFIG_GENERIC_IRQ_ENTRY=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
CONFIG_UPROBES=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_RUST=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_EVENTS_NMI=y
CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
# CONFIG_SECCOMP_CACHE_DEBUG is not set
CONFIG_HAVE_ARCH_KSTACK_ERASE=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
# CONFIG_SHADOW_CALL_STACK is not set
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_ARCH_SUPPORTS_CFI=y
CONFIG_HAVE_CONTEXT_TRACKING_USER=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_ARCH_HUGE_VMALLOC=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_WANT_PMD_MKWRITE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_ARCH_WANTS_EXECMEM_LATE=y
CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_HAVE_PAGE_SIZE_4KB=y
CONFIG_PAGE_SIZE_4KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SHIFT=12
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_HAVE_RELIABLE_STACKTRACE=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_ARCH_SUPPORTS_RT=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET=y
# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
CONFIG_RELR=y
CONFIG_ARCH_HAS_MEM_ENCRYPT=y
CONFIG_ARCH_HAS_CC_PLATFORM=y
CONFIG_HAVE_PREEMPT_DYNAMIC=y
CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y
CONFIG_ARCH_HAS_HW_PTE_YOUNG=y
CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG=y
CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FUNCTION_ALIGNMENT=4
CONFIG_CC_HAS_MIN_FUNCTION_ALIGNMENT=y
CONFIG_CC_HAS_SANE_FUNCTION_ALIGNMENT=y
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_MODULES=y
# CONFIG_MODULE_DEBUG is not set
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BLK_RQ_ALLOC_TIME=y
CONFIG_BLK_CGROUP_RWSTAT=y
CONFIG_BLK_CGROUP_PUNT_BIO=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_ICQ=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_WRITE_MOUNTED=y
# CONFIG_BLK_DEV_ZONED is not set
CONFIG_BLK_DEV_THROTTLING=y
CONFIG_BLK_WBT=y
CONFIG_BLK_WBT_MQ=y
CONFIG_BLK_CGROUP_IOLATENCY=y
CONFIG_BLK_CGROUP_IOCOST=y
CONFIG_BLK_CGROUP_IOPRIO=y
# CONFIG_BLK_DEBUG_FS is not set
CONFIG_BLK_SED_OPAL=y
CONFIG_BLK_INLINE_ENCRYPTION=y
CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_AIX_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
# CONFIG_CMDLINE_PARTITION is not set
# CONFIG_OF_PARTITION is not set
# end of Partition Types

CONFIG_BLK_PM=y
CONFIG_BLOCK_HOLDER_DEPRECATED=y
CONFIG_BLK_MQ_STACKING=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
# CONFIG_BFQ_CGROUP_DEBUG is not set
# end of IO Schedulers

CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_HAVE_ELF_PROT=y
CONFIG_ARCH_USE_GNU_PROPERTY=y
CONFIG_ELFCORE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=m
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_SWAP=y
CONFIG_ZSWAP=y
CONFIG_ZSWAP_DEFAULT_ON=y
# CONFIG_ZSWAP_SHRINKER_DEFAULT_ON is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
CONFIG_ZSMALLOC=y

#
# Zsmalloc allocator options
#

#
# Zsmalloc is a common backend allocator for zswap & zram
#
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_ZSMALLOC_CHAIN_SIZE=8
# end of Zsmalloc allocator options

#
# Slab allocator options
#
CONFIG_SLUB=y
CONFIG_KVFREE_RCU_BATCHED=y
# CONFIG_SLUB_TINY is not set
CONFIG_SLAB_MERGE_DEFAULT=y
CONFIG_SLAB_FREELIST_RANDOM=y
CONFIG_SLAB_FREELIST_HARDENED=y
CONFIG_SLAB_BUCKETS=y
# CONFIG_SLUB_STATS is not set
CONFIG_SLUB_CPU_PARTIAL=y
# CONFIG_RANDOM_KMALLOC_CACHES is not set
# end of Slab allocator options

CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_GUP_FAST=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_SPLIT_PTE_PTLOCKS=y
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_SPLIT_PMD_PTLOCKS=y
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
CONFIG_ARCH_ENABLE_THP_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PCP_BATCH_SCALE_MAX=5
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_MMU_NOTIFIER=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
CONFIG_MEMORY_FAILURE=y
# CONFIG_HWPOISON_INJECT is not set
CONFIG_ARCH_WANTS_THP_SWAP=y
# CONFIG_PERSISTENT_HUGE_ZERO_FOLIO is not set
CONFIG_MM_ID=y
CONFIG_TRANSPARENT_HUGEPAGE=y
# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set
CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
# CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set
CONFIG_THP_SWAP=y
# CONFIG_READ_ONLY_THP_FOR_FS is not set
# CONFIG_NO_PAGE_MAPCOUNT is not set
CONFIG_PAGE_MAPCOUNT=y
CONFIG_PGTABLE_HAS_HUGE_LEAVES=y
CONFIG_HAVE_GIGANTIC_FOLIOS=y
CONFIG_ARCH_SUPPORTS_HUGE_PFNMAP=y
CONFIG_ARCH_SUPPORTS_PMD_PFNMAP=y
CONFIG_CMA=y
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_CMA_AREAS=7
CONFIG_PAGE_BLOCK_MAX_ORDER=10
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
CONFIG_PAGE_IDLE_FLAG=y
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ARCH_HAS_ZONE_DMA_SET=y
CONFIG_ZONE_DMA=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
CONFIG_ARCH_HAS_PKEYS=y
CONFIG_ARCH_USES_PG_ARCH_2=y
CONFIG_ARCH_USES_PG_ARCH_3=y
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_TEST is not set
# CONFIG_DMAPOOL_TEST is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_MEMFD_CREATE=y
CONFIG_SECRETMEM=y
# CONFIG_ANON_VMA_NAME is not set
# CONFIG_USERFAULTFD is not set
CONFIG_LRU_GEN=y
CONFIG_LRU_GEN_ENABLED=y
# CONFIG_LRU_GEN_STATS is not set
CONFIG_LRU_GEN_WALKS_MMU=y
CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y
CONFIG_PER_VMA_LOCK=y
CONFIG_LOCK_MM_AND_FIND_VMA=y
CONFIG_IOMMU_MM_DATA=y
CONFIG_EXECMEM=y
CONFIG_ARCH_HAS_USER_SHADOW_STACK=y

#
# Data Access Monitoring
#
CONFIG_DAMON=y
CONFIG_DAMON_VADDR=y
CONFIG_DAMON_PADDR=y
CONFIG_DAMON_SYSFS=y
CONFIG_DAMON_RECLAIM=y
CONFIG_DAMON_LRU_SORT=y
# CONFIG_DAMON_STAT is not set
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_XGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_DECRYPTED=y
CONFIG_SKB_EXTENSIONS=y
CONFIG_NET_DEVMEM=y
CONFIG_NET_SHAPER=y
CONFIG_NET_CRC32C=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
# CONFIG_INET_PSP is not set
CONFIG_UNIX=y
CONFIG_AF_UNIX_OOB=y
CONFIG_UNIX_DIAG=y
CONFIG_TLS=m
CONFIG_TLS_DEVICE=y
CONFIG_TLS_TOE=y
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
CONFIG_XFRM_INTERFACE=m
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_AH=y
CONFIG_XFRM_ESP=y
CONFIG_XFRM_IPCOMP=y
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
# CONFIG_XFRM_IPTFS is not set
CONFIG_XFRM_ESPINTCP=y
# CONFIG_DIBS is not set
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=y
CONFIG_NET_HANDSHAKE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
# CONFIG_IP_FIB_TRIE_STATS is not set
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_ROUTE_CLASSID=y
# CONFIG_IP_PNP is not set
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=y
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=y
CONFIG_NET_FOU=y
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
CONFIG_INET_ESP_OFFLOAD=m
# CONFIG_INET_ESPINTCP is not set
CONFIG_INET_IPCOMP=y
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=y
CONFIG_INET_TUNNEL=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
CONFIG_INET_UDP_DIAG=y
CONFIG_INET_RAW_DIAG=y
# CONFIG_INET_DIAG_DESTROY is not set
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_NV=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_CONG_DCTCP=m
CONFIG_TCP_CONG_CDG=m
CONFIG_TCP_CONG_BBR=m
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_AO is not set
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_ESP_OFFLOAD=m
CONFIG_INET6_ESPINTCP=y
CONFIG_INET6_IPCOMP=y
CONFIG_IPV6_MIP6=m
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=y
CONFIG_INET6_TUNNEL=y
CONFIG_IPV6_VTI=m
CONFIG_IPV6_SIT=y
CONFIG_IPV6_SIT_6RD=y
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=y
CONFIG_IPV6_GRE=m
CONFIG_IPV6_FOU=y
CONFIG_IPV6_FOU_TUNNEL=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
CONFIG_IPV6_SEG6_LWTUNNEL=y
CONFIG_IPV6_SEG6_HMAC=y
CONFIG_IPV6_SEG6_BPF=y
CONFIG_IPV6_RPL_LWTUNNEL=y
CONFIG_IPV6_IOAM6_LWTUNNEL=y
# CONFIG_NETLABEL is not set
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=y
CONFIG_MPTCP_IPV6=y
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_EGRESS=y
CONFIG_NETFILTER_SKIP_EGRESS=y
CONFIG_NETFILTER_NETLINK=m
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
CONFIG_NETFILTER_BPF_LINK=y
# CONFIG_NETFILTER_NETLINK_HOOK is not set
CONFIG_NETFILTER_NETLINK_ACCT=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NETFILTER_NETLINK_OSF=m
CONFIG_NF_CONNTRACK=y
CONFIG_NF_LOG_SYSLOG=m
CONFIG_NETFILTER_CONNCOUNT=m
CONFIG_NF_CONNTRACK_MARK=y
# CONFIG_NF_CONNTRACK_SECMARK is not set
CONFIG_NF_CONNTRACK_ZONES=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y
CONFIG_NF_CONNTRACK_TIMEOUT=y
CONFIG_NF_CONNTRACK_TIMESTAMP=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CONNTRACK_OVS=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_CT_NETLINK_TIMEOUT=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=m
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NF_NAT_OVS=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=m
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
# CONFIG_NFT_EXTHDR_DCCP is not set
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_FULLCONE=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
CONFIG_NFT_OSF=m
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NF_DUP_NETDEV=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NFT_REJECT_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
# CONFIG_NF_FLOW_TABLE_PROCFS is not set
CONFIG_NETFILTER_XTABLES=m
# CONFIG_NETFILTER_XTABLES_COMPAT is not set
CONFIG_NETFILTER_XTABLES_LEGACY=y

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=m
CONFIG_NETFILTER_XT_CONNMARK=m
CONFIG_NETFILTER_XT_SET=m

#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_AUDIT=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LED=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=m
CONFIG_NETFILTER_XT_TARGET_NETMAP=m
CONFIG_NETFILTER_XT_TARGET_FULLCONENAT=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD=m
CONFIG_NETFILTER_XT_TARGET_RATEEST=m
CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
CONFIG_NETFILTER_XT_TARGET_SECMARK=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=m
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# end of Core Netfilter Configuration

CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
# CONFIG_IP_VS_DEBUG is not set
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m
# CONFIG_IP_VS_TWOS is not set

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_IP_NF_IPTABLES_LEGACY=m
CONFIG_NF_SOCKET_IPV4=m
CONFIG_NF_TPROXY_IPV4=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=m
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_SECURITY=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_NFT_COMPAT_ARP=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_IP6_NF_IPTABLES_LEGACY=m
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP6_NF_SECURITY=m
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=y
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_NFT_BRIDGE_META=m
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES_LEGACY=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
CONFIG_IP_SCTP=m
CONFIG_SCTP_DBG_OBJCNT=y
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA256=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_INET_SCTP_DIAG=m
CONFIG_RDS=m
CONFIG_RDS_TCP=m
# CONFIG_RDS_DEBUG is not set
CONFIG_TIPC=m
CONFIG_TIPC_MEDIA_UDP=y
CONFIG_TIPC_CRYPTO=y
CONFIG_TIPC_DIAG=m
# CONFIG_ATM is not set
CONFIG_L2TP=m
CONFIG_L2TP_DEBUGFS=m
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=m
CONFIG_L2TP_ETH=m
CONFIG_STP=y
CONFIG_GARP=m
CONFIG_MRP=m
CONFIG_BRIDGE=y
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_BRIDGE_MRP=y
CONFIG_BRIDGE_CFM=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_TAG_NONE=m
CONFIG_NET_DSA_TAG_AR9331=m
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
CONFIG_NET_DSA_TAG_BRCM=m
CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
CONFIG_NET_DSA_TAG_BRCM_LEGACY_FCS=m
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
CONFIG_NET_DSA_TAG_HELLCREEK=m
CONFIG_NET_DSA_TAG_GSWIP=m
CONFIG_NET_DSA_TAG_DSA_COMMON=m
CONFIG_NET_DSA_TAG_DSA=m
CONFIG_NET_DSA_TAG_EDSA=m
CONFIG_NET_DSA_TAG_MTK=m
CONFIG_NET_DSA_TAG_KSZ=m
CONFIG_NET_DSA_TAG_OCELOT=m
CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
CONFIG_NET_DSA_TAG_QCA=m
CONFIG_NET_DSA_TAG_RTL4_A=m
CONFIG_NET_DSA_TAG_RTL8_4=m
CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
CONFIG_NET_DSA_TAG_LAN9303=m
CONFIG_NET_DSA_TAG_SJA1105=m
CONFIG_NET_DSA_TAG_TRAILER=m
CONFIG_NET_DSA_TAG_VSC73XX_8021Q=m
CONFIG_NET_DSA_TAG_XRS700X=m
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q_MVRP=y
CONFIG_LLC=y
CONFIG_LLC2=y
CONFIG_ATALK=m
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
CONFIG_6LOWPAN=m
# CONFIG_6LOWPAN_DEBUGFS is not set
CONFIG_6LOWPAN_NHC=m
CONFIG_6LOWPAN_NHC_DEST=m
CONFIG_6LOWPAN_NHC_FRAGMENT=m
CONFIG_6LOWPAN_NHC_HOP=m
CONFIG_6LOWPAN_NHC_IPV6=m
CONFIG_6LOWPAN_NHC_MOBILITY=m
CONFIG_6LOWPAN_NHC_ROUTING=m
CONFIG_6LOWPAN_NHC_UDP=m
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
CONFIG_6LOWPAN_GHC_UDP=m
CONFIG_6LOWPAN_GHC_ICMPV6=m
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
CONFIG_IEEE802154=m
CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_MAC802154=m
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFB=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_MQPRIO_LIB=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_SKBPRIO=m
CONFIG_NET_SCH_CHOKE=m
CONFIG_NET_SCH_QFQ=m
CONFIG_NET_SCH_CODEL=m
CONFIG_NET_SCH_FQ_CODEL=y
CONFIG_NET_SCH_CAKE=y
CONFIG_NET_SCH_FQ=m
CONFIG_NET_SCH_HHF=m
CONFIG_NET_SCH_PIE=m
CONFIG_NET_SCH_FQ_PIE=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_SCH_PLUG=m
CONFIG_NET_SCH_ETS=m
# CONFIG_NET_SCH_BPF is not set
# CONFIG_NET_SCH_DUALPI2 is not set
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_PERF=y
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=y
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
# CONFIG_NET_EMATCH_CANID is not set
CONFIG_NET_EMATCH_IPSET=m
CONFIG_NET_EMATCH_IPT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_SAMPLE=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
CONFIG_NET_ACT_MPLS=m
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_NET_ACT_CONNMARK=m
CONFIG_NET_ACT_CTINFO=m
CONFIG_NET_ACT_SKBMOD=m
CONFIG_NET_ACT_IFE=m
CONFIG_NET_ACT_TUNNEL_KEY=m
CONFIG_NET_ACT_CT=m
CONFIG_NET_ACT_GATE=m
CONFIG_NET_IFE_SKBMARK=m
CONFIG_NET_IFE_SKBPRIO=m
CONFIG_NET_IFE_SKBTCINDEX=m
# CONFIG_NET_TC_SKB_EXT is not set
CONFIG_NET_SCH_FIFO=y
CONFIG_DCB=y
CONFIG_DNS_RESOLVER=m
CONFIG_BATMAN_ADV=m
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUG is not set
# CONFIG_BATMAN_ADV_TRACING is not set
CONFIG_OPENVSWITCH=m
CONFIG_OPENVSWITCH_GRE=m
CONFIG_OPENVSWITCH_VXLAN=m
CONFIG_OPENVSWITCH_GENEVE=m
CONFIG_VSOCKETS=m
CONFIG_VSOCKETS_DIAG=m
CONFIG_VSOCKETS_LOOPBACK=m
CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO_VSOCKETS_COMMON=m
CONFIG_NETLINK_DIAG=y
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=m
CONFIG_MPLS_ROUTING=m
CONFIG_MPLS_IPTUNNEL=m
CONFIG_NET_NSH=m
# CONFIG_HSR is not set
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=m
# CONFIG_QRTR_SMD is not set
# CONFIG_QRTR_TUN is not set
CONFIG_QRTR_MHI=m
# CONFIG_NET_NCSI is not set
CONFIG_PCPU_DEV_REFCNT=y
CONFIG_MAX_SKB_FRAGS=17
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_XPS=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
CONFIG_NET_PKTGEN=m
# CONFIG_NET_DROP_MONITOR is not set
# end of Network testing
# end of Networking options

# CONFIG_HAMRADIO is not set
CONFIG_CAN=m
CONFIG_CAN_RAW=m
CONFIG_CAN_BCM=m
CONFIG_CAN_GW=m
CONFIG_CAN_J1939=m
CONFIG_CAN_ISOTP=m
CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=m
CONFIG_BT_LE=y
CONFIG_BT_LE_L2CAP_ECRED=y
CONFIG_BT_6LOWPAN=m
CONFIG_BT_LEDS=y
CONFIG_BT_MSFTEXT=y
# CONFIG_BT_AOSPEXT is not set
# CONFIG_BT_DEBUGFS is not set
CONFIG_BT_SELFTEST=y
CONFIG_BT_SELFTEST_ECDH=y
CONFIG_BT_SELFTEST_SMP=y

#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=m
CONFIG_BT_BCM=m
CONFIG_BT_RTL=m
CONFIG_BT_QCA=m
CONFIG_BT_MTK=m
CONFIG_BT_HCIBTUSB=m
# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
CONFIG_BT_HCIBTUSB_POLL_SYNC=y
CONFIG_BT_HCIBTUSB_BCM=y
CONFIG_BT_HCIBTUSB_MTK=y
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_NOKIA=m
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_BCM=y
CONFIG_BT_HCIUART_RTL=y
CONFIG_BT_HCIUART_QCA=y
CONFIG_BT_HCIUART_AG6XX=y
CONFIG_BT_HCIUART_MRVL=y
# CONFIG_BT_HCIUART_AML is not set
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBCM4377=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
CONFIG_BT_MTKSDIO=m
CONFIG_BT_MTKUART=m
CONFIG_BT_HCIRSI=m
CONFIG_BT_VIRTIO=m
CONFIG_BT_NXPUART=m
# CONFIG_BT_INTEL_PCIE is not set
# end of Bluetooth device drivers

CONFIG_AF_RXRPC=m
# CONFIG_AF_RXRPC_IPV6 is not set
# CONFIG_AF_RXRPC_INJECT_LOSS is not set
# CONFIG_AF_RXRPC_INJECT_RX_DELAY is not set
# CONFIG_AF_RXRPC_DEBUG is not set
# CONFIG_RXKAD is not set
# CONFIG_RXGK is not set
# CONFIG_RXPERF is not set
CONFIG_AF_KCM=m
CONFIG_STREAM_PARSER=y
# CONFIG_MCTP is not set
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
CONFIG_CFG80211_CERTIFICATION_ONUS=y
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_EXTRA_REGDB_KEYDIR=""
CONFIG_CFG80211_REG_CELLULAR_HINTS=y
CONFIG_CFG80211_REG_RELAX_NO_IR=y
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
# CONFIG_MAC80211_MESSAGE_TRACING is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_RFKILL=m
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=m
CONFIG_NET_9P=m
CONFIG_NET_9P_FD=m
CONFIG_NET_9P_VIRTIO=m
# CONFIG_NET_9P_USBG is not set
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
CONFIG_CEPH_LIB=m
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
# CONFIG_NFC is not set
CONFIG_PSAMPLE=m
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_SOCK_VALIDATE_XMIT=y
CONFIG_NET_IEEE8021Q_HELPERS=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
# CONFIG_PAGE_POOL_STATS is not set
CONFIG_FAILOVER=y
CONFIG_SHORTCUT_FE=y
CONFIG_ETHTOOL_NETLINK=y

#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIEAER is not set
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
# CONFIG_PCIEASPM_PERFORMANCE is not set
CONFIG_PCIE_PME=y
CONFIG_PCIE_PTM=y
CONFIG_PCI_MSI=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_STUB is not set
# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set
# CONFIG_PCI_DOE is not set
CONFIG_PCI_ECAM=y
# CONFIG_PCI_IOV is not set
# CONFIG_PCI_NPEM is not set
# CONFIG_PCI_PRI is not set
# CONFIG_PCI_PASID is not set
# CONFIG_PCIE_TPH is not set
CONFIG_PCI_LABEL=y
# CONFIG_PCI_DYNAMIC_OF_NODES is not set
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
# CONFIG_HOTPLUG_PCI is not set

#
# PCI controller drivers
#
CONFIG_PCI_HOST_COMMON=y
# CONFIG_PCIE_ALTERA is not set
# CONFIG_PCI_HOST_THUNDER_PEM is not set
# CONFIG_PCI_HOST_THUNDER_ECAM is not set
# CONFIG_PCI_FTPCI100 is not set
CONFIG_PCI_HOST_GENERIC=y
# CONFIG_PCIE_HISI_ERR is not set
CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_HOST=y
CONFIG_PCIE_ROCKCHIP_EP=y
# CONFIG_PCI_XGENE is not set
# CONFIG_PCIE_XILINX is not set

#
# Cadence-based PCIe controllers
#
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCIE_CADENCE_PLAT_EP is not set
# end of Cadence-based PCIe controllers

#
# DesignWare-based PCIe controllers
#
CONFIG_PCIE_DW=y
# CONFIG_PCIE_DW_DEBUGFS is not set
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_EP=y
# CONFIG_PCIE_AL is not set
# CONFIG_PCIE_AMD_MDB is not set
CONFIG_PCI_MESON=y
# CONFIG_PCI_HISI is not set
# CONFIG_PCIE_KIRIN is not set
CONFIG_PCIE_DW_PLAT=y
CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCIE_DW_PLAT_EP=y
CONFIG_PCIE_ROCKCHIP_DW=y
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
CONFIG_PCIE_ROCKCHIP_DW_EP=y
# end of DesignWare-based PCIe controllers

#
# Mobiveil-based PCIe controllers
#
# end of Mobiveil-based PCIe controllers

#
# PLDA-based PCIe controllers
#
# CONFIG_PCIE_MICROCHIP_HOST is not set
# end of PLDA-based PCIe controllers
# end of PCI controller drivers

#
# PCI Endpoint
#
CONFIG_PCI_ENDPOINT=y
# CONFIG_PCI_ENDPOINT_CONFIGFS is not set
# CONFIG_PCI_ENDPOINT_MSI_DOORBELL is not set
# CONFIG_PCI_EPF_TEST is not set
CONFIG_PCI_EPF_NTB=m
CONFIG_PCI_EPF_MHI=m
# end of PCI Endpoint

#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set
# end of PCI switch controller drivers

# CONFIG_PCI_PWRCTRL_SLOT is not set
# CONFIG_CXL_BUS is not set
# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set
# CONFIG_PC104 is not set

#
# Generic Driver Options
#
CONFIG_AUXILIARY_BUS=y
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_DEVTMPFS_SAFE is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_DEBUG=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
CONFIG_FW_LOADER_COMPRESS=y
CONFIG_FW_LOADER_COMPRESS_XZ=y
CONFIG_FW_LOADER_COMPRESS_ZSTD=y
# CONFIG_FW_UPLOAD is not set
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_DEVICES=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_SPMI=m
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SCCB=m
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
# CONFIG_MOXTET is not set
CONFIG_SUN50I_DE2_BUS=y
CONFIG_SUNXI_RSB=y
CONFIG_VEXPRESS_CONFIG=y
CONFIG_MHI_BUS=m
# CONFIG_MHI_BUS_DEBUG is not set
CONFIG_MHI_BUS_PCI_GENERIC=m
CONFIG_MHI_BUS_EP=m
# end of Bus devices

#
# Cache Drivers
#
# end of Cache Drivers

CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y

#
# Firmware Drivers
#

#
# ARM System Control and Management Interface Protocol
#
CONFIG_ARM_SCMI_PROTOCOL=y
# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
# CONFIG_ARM_SCMI_DEBUG_COUNTERS is not set
CONFIG_ARM_SCMI_QUIRKS=y

#
# SCMI Transport Drivers
#
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
CONFIG_ARM_SCMI_HAVE_SHMEM=y
CONFIG_ARM_SCMI_HAVE_MSG=y
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y
CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y
CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y
# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE is not set
# end of SCMI Transport Drivers

#
# ARM SCMI NXP i.MX Vendor Protocols
#
# CONFIG_IMX_SCMI_BBM_EXT is not set
# end of ARM SCMI NXP i.MX Vendor Protocols

CONFIG_ARM_SCMI_POWER_CONTROL=y
# end of ARM System Control and Management Interface Protocol

CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SDE_INTERFACE=y
# CONFIG_FIRMWARE_MEMMAP is not set
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=y
# CONFIG_ISCSI_IBFT is not set
CONFIG_FW_CFG_SYSFS=y
CONFIG_FW_CFG_SYSFS_CMDLINE=y
CONFIG_SYSFB=y
# CONFIG_SYSFB_SIMPLEFB is not set
CONFIG_ARM_FFA_TRANSPORT=y
CONFIG_ARM_FFA_SMCCC=y
CONFIG_FW_CS_DSP=m
# CONFIG_GOOGLE_FIRMWARE is not set

#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_VARS_PSTORE=y
# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_GENERIC_STUB=y
# CONFIG_EFI_ZBOOT is not set
CONFIG_EFI_ARMSTUB_DTB_LOADER=y
CONFIG_EFI_BOOTLOADER_CONTROL=m
CONFIG_EFI_CAPSULE_LOADER=m
CONFIG_EFI_TEST=m
# CONFIG_RESET_ATTACK_MITIGATION is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
# CONFIG_EFI_DISABLE_RUNTIME is not set
# CONFIG_EFI_COCO_SECRET is not set
# CONFIG_OVMF_DEBUG_LOG is not set
# end of EFI (Extensible Firmware Interface) Support

CONFIG_UEFI_CPER=y
CONFIG_UEFI_CPER_ARM=y
# CONFIG_TEE_STMM_EFI is not set
CONFIG_MESON_SM=y
CONFIG_MESON_GX_PM=y
CONFIG_ARM_PSCI_FW=y

#
# Qualcomm firmware drivers
#
# end of Qualcomm firmware drivers

CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_ARM_SMCCC_SOC_ID=y

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

# CONFIG_FWCTL is not set
CONFIG_GNSS=m
CONFIG_GNSS_SERIAL=m
CONFIG_GNSS_MTK_SERIAL=m
CONFIG_GNSS_SIRF_SERIAL=m
CONFIG_GNSS_UBX_SERIAL=m
CONFIG_GNSS_USB=m
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_AFS_PARTS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y

#
# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
#
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_DATAFLASH is not set
CONFIG_MTD_MCHP23K256=m
# CONFIG_MTD_MCHP48L640 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
CONFIG_MTD_NAND_CORE=y
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
# CONFIG_MTD_SPI_NAND is not set

#
# ECC engine support
#
CONFIG_MTD_NAND_ECC=y
# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
CONFIG_MTD_NAND_ECC_MXIC=y
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
# CONFIG_MTD_UBI_BLOCK is not set
# CONFIG_MTD_UBI_NVMEM is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_NULL_BLK=m
CONFIG_CDROM=m
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
CONFIG_ZRAM=m
CONFIG_ZRAM_BACKEND_LZ4=y
CONFIG_ZRAM_BACKEND_LZ4HC=y
CONFIG_ZRAM_BACKEND_ZSTD=y
CONFIG_ZRAM_BACKEND_DEFLATE=y
CONFIG_ZRAM_BACKEND_842=y
CONFIG_ZRAM_BACKEND_LZO=y
# CONFIG_ZRAM_DEF_COMP_LZORLE is not set
# CONFIG_ZRAM_DEF_COMP_LZO is not set
# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
CONFIG_ZRAM_DEF_COMP_ZSTD=y
# CONFIG_ZRAM_DEF_COMP_DEFLATE is not set
# CONFIG_ZRAM_DEF_COMP_842 is not set
CONFIG_ZRAM_DEF_COMP="zstd"
CONFIG_ZRAM_WRITEBACK=y
CONFIG_ZRAM_TRACK_ENTRY_ACTIME=y
# CONFIG_ZRAM_MEMORY_TRACKING is not set
CONFIG_ZRAM_MULTI_COMP=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=64
CONFIG_BLK_DEV_DRBD=m
CONFIG_DRBD_FAULT_INJECTION=y
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_ATA_OVER_ETH is not set
CONFIG_VIRTIO_BLK=m
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_UBLK is not set

#
# NVME Support
#
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
# CONFIG_NVME_MULTIPATH is not set
# CONFIG_NVME_VERBOSE_ERRORS is not set
CONFIG_NVME_HWMON=y
CONFIG_NVME_FABRICS=m
# CONFIG_NVME_FC is not set
CONFIG_NVME_TCP=m
# CONFIG_NVME_TCP_TLS is not set
# CONFIG_NVME_HOST_AUTH is not set
CONFIG_NVME_TARGET=m
# CONFIG_NVME_TARGET_DEBUGFS is not set
# CONFIG_NVME_TARGET_PASSTHRU is not set
CONFIG_NVME_TARGET_LOOP=m
# CONFIG_NVME_TARGET_FC is not set
CONFIG_NVME_TARGET_TCP=m
# CONFIG_NVME_TARGET_TCP_TLS is not set
# CONFIG_NVME_TARGET_AUTH is not set
# CONFIG_NVME_TARGET_PCI_EPF is not set
# end of NVME Support

#
# Misc devices
#
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
# CONFIG_RPMB is not set
# CONFIG_TI_FPC202 is not set
CONFIG_TIFM_CORE=m
CONFIG_TIFM_7XX1=m
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HI6421V600_IRQ is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
# CONFIG_DW_XDATA_PCIE is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_XILINX_SDFEC is not set
CONFIG_MISC_RTSX=m
# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_OPEN_DICE is not set
# CONFIG_NTSYNC is not set
# CONFIG_VCPU_STALL_DETECTOR is not set
# CONFIG_NSM is not set
# CONFIG_MCHP_LAN966X_PCI is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
CONFIG_EEPROM_AT25=m
# CONFIG_EEPROM_MAX6875 is not set
CONFIG_EEPROM_93CX6=m
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# CONFIG_EEPROM_M24LR is not set
# end of EEPROM support

CONFIG_CB710_CORE=m
# CONFIG_CB710_DEBUG is not set
CONFIG_CB710_DEBUG_ASSUMPTIONS=y
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
# CONFIG_VMWARE_VMCI is not set
# CONFIG_GENWQE is not set
# CONFIG_BCM_VK is not set
# CONFIG_MISC_ALCOR_PCI is not set
# CONFIG_MISC_RTSX_PCI is not set
CONFIG_MISC_RTSX_USB=m
# CONFIG_UACCE is not set
# CONFIG_PVPANIC is not set
# CONFIG_GP_PCI1XXXX is not set
# CONFIG_KEBA_CP500 is not set
# CONFIG_AMD_SBRMI_I2C is not set
# CONFIG_MISC_RP1 is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI_COMMON=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=m
CONFIG_BLK_DEV_BSG=y
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=m
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_ISCSI_BOOT_SYSFS=m
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_MPI3MR is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_FDOMAIN_PCI is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
CONFIG_SCSI_VIRTIO=m
# CONFIG_SCSI_DH is not set
# end of SCSI device support

CONFIG_ATA=y
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_ARCH_WANT_LIBATA_LEDS=y
CONFIG_ATA_LEDS=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_AHCI_DWC=y
CONFIG_AHCI_CEVA=m
CONFIG_AHCI_SUNXI=y
CONFIG_SATA_INIC162X=m
CONFIG_SATA_ACARD_AHCI=m
CONFIG_SATA_SIL24=m
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#
# CONFIG_PDC_ADMA is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_SATA_SX4 is not set
CONFIG_ATA_BMDMA=y

#
# SATA SFF controllers with BMDMA
#
# CONFIG_ATA_PIIX is not set
# CONFIG_SATA_DWC is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_NV is not set
# CONFIG_SATA_PROMISE is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIS is not set
# CONFIG_SATA_SVW is not set
# CONFIG_SATA_ULI is not set
# CONFIG_SATA_VIA is not set
# CONFIG_SATA_VITESSE is not set

#
# PATA SFF controllers with BMDMA
#
# CONFIG_PATA_ALI is not set
# CONFIG_PATA_AMD is not set
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_ATP867X is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CYPRESS is not set
# CONFIG_PATA_EFAR is not set
# CONFIG_PATA_HPT366 is not set
# CONFIG_PATA_HPT37X is not set
# CONFIG_PATA_HPT3X2N is not set
# CONFIG_PATA_HPT3X3 is not set
# CONFIG_PATA_IT8213 is not set
# CONFIG_PATA_IT821X is not set
# CONFIG_PATA_JMICRON is not set
# CONFIG_PATA_MARVELL is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_OPTIDMA is not set
# CONFIG_PATA_PDC2027X is not set
# CONFIG_PATA_PDC_OLD is not set
# CONFIG_PATA_RADISYS is not set
# CONFIG_PATA_RDC is not set
# CONFIG_PATA_SCH is not set
# CONFIG_PATA_SERVERWORKS is not set
# CONFIG_PATA_SIL680 is not set
# CONFIG_PATA_SIS is not set
# CONFIG_PATA_TOSHIBA is not set
# CONFIG_PATA_TRIFLEX is not set
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set

#
# PIO-only SFF controllers
#
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_OF_PLATFORM is not set
# CONFIG_PATA_RZ1000 is not set

#
# Generic fallback / legacy drivers
#
# CONFIG_PATA_ACPI is not set
# CONFIG_ATA_GENERIC is not set
# CONFIG_PATA_LEGACY is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_BITMAP=y
# CONFIG_MD_LLBITMAP is not set
CONFIG_MD_BITMAP_FILE=y
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_CLUSTER=m
CONFIG_BCACHE=m
# CONFIG_BCACHE_DEBUG is not set
# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=m
# CONFIG_DM_DEBUG is not set
CONFIG_DM_BUFIO=m
# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
# CONFIG_DM_CACHE is not set
CONFIG_DM_WRITECACHE=m
# CONFIG_DM_EBS is not set
# CONFIG_DM_ERA is not set
# CONFIG_DM_CLONE is not set
CONFIG_DM_MIRROR=m
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
# CONFIG_DM_MULTIPATH_HST is not set
# CONFIG_DM_MULTIPATH_IOA is not set
CONFIG_DM_DELAY=m
# CONFIG_DM_DUST is not set
# CONFIG_DM_UEVENT is not set
CONFIG_DM_FLAKEY=m
CONFIG_DM_VERITY=m
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
# CONFIG_DM_VERITY_FEC is not set
# CONFIG_DM_SWITCH is not set
CONFIG_DM_LOG_WRITES=m
CONFIG_DM_INTEGRITY=m
CONFIG_DM_AUDIT=y
# CONFIG_DM_VDO is not set
# CONFIG_DM_PCACHE is not set
CONFIG_TARGET_CORE=m
# CONFIG_TCM_IBLOCK is not set
# CONFIG_TCM_FILEIO is not set
# CONFIG_TCM_PSCSI is not set
# CONFIG_LOOPBACK_TARGET is not set
CONFIG_ISCSI_TARGET=m
# CONFIG_REMOTE_TARGET is not set
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
# end of IEEE 1394 (FireWire) support

CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_WIREGUARD=m
# CONFIG_WIREGUARD_DEBUG is not set
# CONFIG_OVPN is not set
CONFIG_EQUALIZER=m
# CONFIG_NET_FC is not set
CONFIG_IFB=m
CONFIG_NET_TEAM=m
CONFIG_NET_TEAM_MODE_BROADCAST=m
CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
CONFIG_NET_TEAM_MODE_RANDOM=m
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
CONFIG_NET_TEAM_MODE_LOADBALANCE=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=m
CONFIG_IPVTAP=m
CONFIG_VXLAN=m
CONFIG_GENEVE=m
CONFIG_BAREUDP=m
CONFIG_GTP=m
CONFIG_PFCP=m
CONFIG_AMT=m
CONFIG_MACSEC=m
CONFIG_NETCONSOLE=m
CONFIG_NETCONSOLE_DYNAMIC=y
# CONFIG_NETCONSOLE_EXTENDED_LOG is not set
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=m
CONFIG_TAP=m
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_NLMON=m
# CONFIG_NETKIT is not set
CONFIG_NET_VRF=m
CONFIG_MHI_NET=m
# CONFIG_ARCNET is not set

#
# Distributed Switch Architecture drivers
#
CONFIG_B53=m
CONFIG_B53_SPI_DRIVER=m
CONFIG_B53_MDIO_DRIVER=m
CONFIG_B53_MMAP_DRIVER=m
CONFIG_B53_SRAB_DRIVER=m
CONFIG_B53_SERDES=m
CONFIG_NET_DSA_BCM_SF2=m
CONFIG_NET_DSA_LOOP=m
CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
CONFIG_NET_DSA_LANTIQ_GSWIP=m
CONFIG_NET_DSA_MT7530=m
CONFIG_NET_DSA_MT7530_MDIO=m
CONFIG_NET_DSA_MT7530_MMIO=m
CONFIG_NET_DSA_MV88E6060=m
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
CONFIG_NET_DSA_MICROCHIP_KSZ_PTP=y
CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
CONFIG_NET_DSA_MV88E6XXX=m
CONFIG_NET_DSA_MV88E6XXX_PTP=y
CONFIG_NET_DSA_MV88E6XXX_LEDS=y
CONFIG_NET_DSA_AR9331=m
CONFIG_NET_DSA_QCA8K=m
CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y
CONFIG_NET_DSA_SJA1105=m
CONFIG_NET_DSA_SJA1105_PTP=y
CONFIG_NET_DSA_SJA1105_TAS=y
CONFIG_NET_DSA_SJA1105_VL=y
CONFIG_NET_DSA_XRS700X=m
CONFIG_NET_DSA_XRS700X_I2C=m
CONFIG_NET_DSA_XRS700X_MDIO=m
CONFIG_NET_DSA_REALTEK=m
CONFIG_NET_DSA_REALTEK_MDIO=y
CONFIG_NET_DSA_REALTEK_SMI=y
CONFIG_NET_DSA_REALTEK_RTL8365MB=m
CONFIG_NET_DSA_REALTEK_RTL8366RB=m
CONFIG_NET_DSA_REALTEK_RTL8366RB_LEDS=y
# CONFIG_NET_DSA_KS8995 is not set
CONFIG_NET_DSA_SMSC_LAN9303=m
CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
CONFIG_NET_DSA_VITESSE_VSC73XX=m
CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
# end of Distributed Switch Architecture drivers

CONFIG_ETHERNET=y
CONFIG_MDIO=m
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
CONFIG_NET_VENDOR_ALLWINNER=y
CONFIG_SUN4I_EMAC=y
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_ALTERA_TSE is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
CONFIG_NET_VENDOR_ASIX=y
# CONFIG_SPI_AX88796C is not set
CONFIG_NET_VENDOR_ATHEROS=y
# CONFIG_ATL2 is not set
# CONFIG_ATL1 is not set
# CONFIG_ATL1E is not set
# CONFIG_ATL1C is not set
CONFIG_ALX=m
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_CORTINA is not set
CONFIG_NET_VENDOR_DAVICOM=y
# CONFIG_DM9051 is not set
# CONFIG_DNET is not set
# CONFIG_NET_VENDOR_DEC is not set
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
CONFIG_NET_VENDOR_ENGLEDER=y
# CONFIG_TSNEP is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_FREESCALE is not set
CONFIG_NET_VENDOR_FUNGIBLE=y
# CONFIG_FUN_ETH is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
CONFIG_NET_VENDOR_I825XX=y
CONFIG_NET_VENDOR_INTEL=y
# CONFIG_E100 is not set
CONFIG_E1000=m
CONFIG_E1000E=m
CONFIG_IGB=m
CONFIG_IGB_HWMON=y
CONFIG_IGBVF=m
# CONFIG_IXGBE is not set
# CONFIG_IXGBEVF is not set
# CONFIG_I40E is not set
# CONFIG_I40EVF is not set
# CONFIG_ICE is not set
# CONFIG_FM10K is not set
CONFIG_IGC=m
CONFIG_IGC_LEDS=y
# CONFIG_IDPF is not set
CONFIG_JME=m
CONFIG_NET_VENDOR_ADI=y
# CONFIG_ADIN1110 is not set
CONFIG_NET_VENDOR_LITEX=y
# CONFIG_LITEX_LITEETH is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
CONFIG_NET_VENDOR_META=y
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_MICROSOFT is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_FEALNX is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETERION is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_BROCADE is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCA7000_UART is not set
CONFIG_QCOM_EMAC=m
CONFIG_SFE_SUPPORT_IPV6=y
CONFIG_SFE_ECM=y
CONFIG_FAST_CLASSIFIER=y
# CONFIG_RMNET is not set
# CONFIG_NET_VENDOR_RDC is not set
CONFIG_NET_VENDOR_REALTEK=y
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
CONFIG_R8125=m
CONFIG_R8125_SOC_LAN=y
# CONFIG_R8125_REALWOW_SUPPORT is not set
# CONFIG_R8125_DASH_SUPPORT is not set
# CONFIG_R8125_DOWN_SPEED_100 is not set
# CONFIG_R8125_ASPM is not set
CONFIG_R8125_WOL_SUPPORT=y
CONFIG_R8125_S5WOL=y
# CONFIG_R8125_S5_KEEP_CURR_MAC is not set
# CONFIG_R8125_EEE is not set
# CONFIG_R8125_S0_MAGIC_PACKET is not set
CONFIG_R8125_TX_NO_CLOSE=y
CONFIG_R8125_MULTI_MSIX_VECTOR=y
CONFIG_R8125_MULTIPLE_TX_QUEUE=y
CONFIG_R8125_RSS_SUPPORT=y
# CONFIG_R8125_PTP_SUPPORT is not set
CONFIG_R8125_FIBER_SUPPORT=y
CONFIG_R8125_USE_FIRMWARE_FILE=y
# CONFIG_R8125_DOUBLE_VLAN is not set
# CONFIG_R8125_PAGE_REUSE is not set
CONFIG_R8125_GIGA_LITE=y
CONFIG_R8126=m
CONFIG_R8126_SOC_LAN=y
# CONFIG_R8126_REALWOW_SUPPORT is not set
# CONFIG_R8126_DASH_SUPPORT is not set
# CONFIG_R8126_DOWN_SPEED_100 is not set
# CONFIG_R8126_ASPM is not set
CONFIG_R8126_WOL_SUPPORT=y
CONFIG_R8126_S5WOL=y
# CONFIG_R8126_S5_KEEP_CURR_MAC is not set
# CONFIG_R8126_EEE is not set
# CONFIG_R8126_S0_MAGIC_PACKET is not set
CONFIG_R8126_TX_NO_CLOSE=y
CONFIG_R8126_MULTI_MSIX_VECTOR=y
CONFIG_R8126_MULTIPLE_TX_QUEUE=y
CONFIG_R8126_RSS_SUPPORT=y
CONFIG_R8126_PTP_SUPPORT=y
CONFIG_R8126_FIBER_SUPPORT=y
CONFIG_R8126_USE_FIRMWARE_FILE=y
# CONFIG_R8126_DOUBLE_VLAN is not set
# CONFIG_R8126_PAGE_REUSE is not set
CONFIG_R8126_GIGA_LITE=y
CONFIG_R8168=m
CONFIG_R8168_SOC_LAN=y
# CONFIG_R8168_FIBER_SUPPORT is not set
# CONFIG_R8168_REALWOW_SUPPORT is not set
# CONFIG_R8168_DASH_SUPPORT is not set
# CONFIG_R8168_DOWN_SPEED_100 is not set
CONFIG_R8168_ASPM=y
CONFIG_R8168_DYNAMIC_ASPM=y
CONFIG_R8168_WOL_SUPPORT=y
CONFIG_R8168_S5WOL=y
# CONFIG_R8168_S5_KEEP_CURR_MAC is not set
CONFIG_R8168_EEE=y
# CONFIG_R8168_S0_MAGIC_PACKET is not set
# CONFIG_R8168_USE_FIRMWARE_FILE is not set
# CONFIG_R8168_CTAP_SHORT_OFF is not set
# CONFIG_R8168_MULTIPLE_TX_QUEUE is not set
# CONFIG_R8168_RSS_SUPPORT is not set
CONFIG_R8168_GIGA_LITE=y
# CONFIG_R8169 is not set
# CONFIG_RTASE is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_SELFTESTS=y
CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_MESON=y
CONFIG_DWMAC_ROCKCHIP=y
CONFIG_DWMAC_SUNXI=y
CONFIG_DWMAC_SUN8I=y
CONFIG_DWMAC_SUN55I=y
# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_DWMAC_MOTORCOMM is not set
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
CONFIG_NET_VENDOR_VERTEXCOM=y
# CONFIG_MSE102X is not set
# CONFIG_NET_VENDOR_VIA is not set
CONFIG_NET_VENDOR_WANGXUN=y
# CONFIG_NGBE is not set
# CONFIG_TXGBE is not set
# CONFIG_TXGBEVF is not set
# CONFIG_NGBEVF is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
CONFIG_MDIO_BUS=y
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_PHYLIB_LEDS=y
CONFIG_FIXED_PHY=y
# CONFIG_SFP is not set

#
# Switch configuration API + drivers
#
CONFIG_SWCONFIG=m
CONFIG_SWCONFIG_LEDS=y
CONFIG_RTL8306_PHY=m
CONFIG_RTL8366_SMI=m
CONFIG_RTL8366_SMI_DEBUG_FS=y
CONFIG_RTL8366S_PHY=m
CONFIG_RTL8366RB_PHY=m
CONFIG_RTL8367_PHY=m
CONFIG_RTL8367B_PHY=m

#
# MII PHY device drivers
#
# CONFIG_AS21XXX_PHY is not set
# CONFIG_AIR_EN8811H_PHY is not set
# CONFIG_AMD_PHY is not set
CONFIG_MESON_GXL_PHY=y
# CONFIG_ADIN_PHY is not set
# CONFIG_ADIN1100_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
CONFIG_AX88796B_PHY=m
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM54140_PHY is not set
CONFIG_BCM7XXX_PHY=m
# CONFIG_BCM84881_PHY is not set
# CONFIG_BCM87XX_PHY is not set
CONFIG_BCM_NET_PHYLIB=m
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
CONFIG_ICPLUS_PHY=y
CONFIG_JLSEMI_PHY=y
# CONFIG_LXT_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MARVELL_88Q2XXX_PHY is not set
# CONFIG_MARVELL_88X2222_PHY is not set
# CONFIG_MAXLINEAR_GPHY is not set
# CONFIG_MAXLINEAR_86110_PHY is not set
CONFIG_MEDIATEK_GE_PHY=m
# CONFIG_MEDIATEK_GE_SOC_PHY is not set
CONFIG_MTK_NET_PHYLIB=m
# CONFIG_MICREL_PHY is not set
# CONFIG_MICROCHIP_T1S_PHY is not set
CONFIG_MICROCHIP_PHY=m
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
CONFIG_MOTORCOMM_PHY=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_NXP_CBTX_PHY is not set
# CONFIG_NXP_C45_TJA11XX_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
# CONFIG_NCN26000_PHY is not set
# CONFIG_AT803X_PHY is not set
# CONFIG_QCA83XX_PHY is not set
# CONFIG_QCA808X_PHY is not set
# CONFIG_QCA807X_PHY is not set
# CONFIG_QSEMI_PHY is not set
CONFIG_REALTEK_PHY=y
# CONFIG_REALTEK_PHY_HWMON is not set
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
CONFIG_SMSC_PHY=y
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
# CONFIG_DP83869_PHY is not set
# CONFIG_DP83TD510_PHY is not set
# CONFIG_DP83TG720_PHY is not set
CONFIG_VITESSE_PHY=m
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_PSE_CONTROLLER is not set
CONFIG_CAN_DEV=m
CONFIG_CAN_VCAN=m
CONFIG_CAN_VXCAN=m
CONFIG_CAN_NETLINK=y
CONFIG_CAN_CALC_BITTIMING=y
CONFIG_CAN_RX_OFFLOAD=y
# CONFIG_CAN_CAN327 is not set
# CONFIG_CAN_FLEXCAN is not set
# CONFIG_CAN_GRCAN is not set
# CONFIG_CAN_KVASER_PCIEFD is not set
# CONFIG_CAN_SLCAN is not set
# CONFIG_CAN_XILINXCAN is not set
# CONFIG_CAN_C_CAN is not set
# CONFIG_CAN_CC770 is not set
# CONFIG_CAN_CTUCANFD_PCI is not set
# CONFIG_CAN_CTUCANFD_PLATFORM is not set
# CONFIG_CAN_ESD_402_PCI is not set
# CONFIG_CAN_IFI_CANFD is not set
# CONFIG_CAN_M_CAN is not set
# CONFIG_CAN_PEAK_PCIEFD is not set
CONFIG_CAN_ROCKCHIP_CANFD=m
# CONFIG_CAN_SJA1000 is not set
# CONFIG_CAN_SOFTING is not set

#
# CAN SPI interfaces
#
# CONFIG_CAN_HI311X is not set
# CONFIG_CAN_MCP251X is not set
# CONFIG_CAN_MCP251XFD is not set
# end of CAN SPI interfaces

#
# CAN USB interfaces
#
# CONFIG_CAN_8DEV_USB is not set
# CONFIG_CAN_EMS_USB is not set
# CONFIG_CAN_ESD_USB is not set
# CONFIG_CAN_ETAS_ES58X is not set
# CONFIG_CAN_F81604 is not set
# CONFIG_CAN_GS_USB is not set
# CONFIG_CAN_KVASER_USB is not set
# CONFIG_CAN_MCBA_USB is not set
# CONFIG_CAN_PEAK_USB is not set
# CONFIG_CAN_UCAN is not set
# end of CAN USB interfaces

# CONFIG_CAN_DEBUG_DEVICES is not set
CONFIG_FWNODE_MDIO=y
CONFIG_OF_MDIO=y
CONFIG_ACPI_MDIO=y
CONFIG_MDIO_SUN4I=y
CONFIG_MDIO_BITBANG=m
CONFIG_MDIO_BCM_UNIMAC=m
CONFIG_MDIO_GPIO=m
# CONFIG_MDIO_HISI_FEMAC is not set
CONFIG_MDIO_MVUSB=m
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_OCTEON is not set
CONFIG_MDIO_IPQ4019=m
CONFIG_MDIO_IPQ8064=m
# CONFIG_MDIO_THUNDER is not set

#
# MDIO Multiplexers
#
CONFIG_MDIO_BUS_MUX=y
CONFIG_MDIO_BUS_MUX_MESON_G12A=y
CONFIG_MDIO_BUS_MUX_MESON_GXL=m
CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y

#
# PCS device drivers
#
CONFIG_PCS_XPCS=y
CONFIG_PCS_MTK_LYNXI=m
# end of PCS device drivers

CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=m
# CONFIG_PPPOE_HASH_BITS_1 is not set
# CONFIG_PPPOE_HASH_BITS_2 is not set
CONFIG_PPPOE_HASH_BITS_4=y
# CONFIG_PPPOE_HASH_BITS_8 is not set
CONFIG_PPPOE_HASH_BITS=4
CONFIG_PPTP=m
CONFIG_PPPOL2TP=m
CONFIG_PPP_ASYNC=m
# CONFIG_PPP_SYNC_TTY is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=m
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_AX8817X=m
CONFIG_USB_NET_AX88179_178A=m
CONFIG_USB_NET_CDCETHER=m
CONFIG_USB_NET_CDC_EEM=m
CONFIG_USB_NET_CDC_NCM=m
CONFIG_USB_NET_HUAWEI_CDC_NCM=m
CONFIG_USB_NET_CDC_MBIM=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9700=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
CONFIG_USB_NET_CDC_SUBSET=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
CONFIG_USB_EPSON2888=y
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=m
CONFIG_USB_NET_CX82310_ETH=m
CONFIG_USB_NET_KALMIA=m
CONFIG_USB_NET_QMI_WWAN=m
CONFIG_USB_HSO=m
CONFIG_USB_NET_INT51X1=m
CONFIG_USB_IPHETH=m
CONFIG_USB_SIERRA_NET=m
CONFIG_USB_VL600=m
CONFIG_USB_NET_CH9200=m
CONFIG_USB_NET_AQC111=m
CONFIG_WLAN=y
CONFIG_WLAN_VENDOR_ADMTEK=y
CONFIG_ADM8211=m
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
# CONFIG_ATH_USER_REGD is not set
# CONFIG_ATH_DEBUG is not set
CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS=y
# CONFIG_ATH_REG_DYNAMIC_USER_CERT_TESTING is not set
CONFIG_ATH5K=m
# CONFIG_ATH5K_DEBUG is not set
# CONFIG_ATH5K_TRACER is not set
CONFIG_ATH5K_PCI=y
# CONFIG_ATH5K_TEST_CHANNELS is not set
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=m
CONFIG_ATH9K_PCI=y
CONFIG_ATH9K_AHB=y
CONFIG_ATH9K_DFS_CERTIFIED=y
CONFIG_ATH9K_DYNACK=y
# CONFIG_ATH9K_WOW is not set
CONFIG_ATH9K_RFKILL=y
CONFIG_ATH9K_CHANNEL_CONTEXT=y
# CONFIG_ATH9K_PCOEM is not set
CONFIG_ATH9K_PCI_NO_EEPROM=m
CONFIG_ATH9K_HTC=m
# CONFIG_ATH9K_HTC_DEBUGFS is not set
CONFIG_ATH9K_HWRNG=y
CONFIG_CARL9170=m
CONFIG_CARL9170_LEDS=y
CONFIG_CARL9170_WPC=y
CONFIG_CARL9170_HWRNG=y
CONFIG_ATH6KL=m
CONFIG_ATH6KL_SDIO=m
CONFIG_ATH6KL_USB=m
# CONFIG_ATH6KL_DEBUG is not set
# CONFIG_ATH6KL_TRACING is not set
# CONFIG_ATH6KL_REGDOMAIN is not set
CONFIG_AR5523=m
# CONFIG_WIL6210 is not set
CONFIG_ATH10K=m
CONFIG_ATH10K_CE=y
CONFIG_ATH10K_PCI=m
# CONFIG_ATH10K_AHB is not set
CONFIG_ATH10K_SDIO=m
CONFIG_ATH10K_USB=m
# CONFIG_ATH10K_DEBUG is not set
# CONFIG_ATH10K_DEBUGFS is not set
CONFIG_ATH10K_LEDS=y
# CONFIG_ATH10K_TRACING is not set
CONFIG_ATH10K_DFS_CERTIFIED=y
CONFIG_WCN36XX=m
# CONFIG_WCN36XX_DEBUGFS is not set
CONFIG_ATH11K=m
# CONFIG_ATH11K_AHB is not set
CONFIG_ATH11K_PCI=m
# CONFIG_ATH11K_DEBUG is not set
# CONFIG_ATH11K_TRACING is not set
CONFIG_ATH12K=m
# CONFIG_ATH12K_AHB is not set
# CONFIG_ATH12K_DEBUG is not set
# CONFIG_ATH12K_TRACING is not set
# CONFIG_ATH12K_COREDUMP is not set
CONFIG_WLAN_VENDOR_ATMEL=y
CONFIG_AT76C50X_USB=m
CONFIG_WLAN_VENDOR_BROADCOM=y
# CONFIG_B43 is not set
# CONFIG_B43LEGACY is not set
CONFIG_BRCMUTIL=m
# CONFIG_BRCMSMAC is not set
CONFIG_BRCMFMAC=m
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
# CONFIG_BRCMFMAC_PCIE is not set
CONFIG_BRCM_TRACING=y
CONFIG_BRCMDBG=y
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_IPW2100=m
# CONFIG_IPW2100_MONITOR is not set
# CONFIG_IPW2100_DEBUG is not set
CONFIG_IPW2200=m
# CONFIG_IPW2200_MONITOR is not set
# CONFIG_IPW2200_QOS is not set
# CONFIG_IPW2200_DEBUG is not set
CONFIG_LIBIPW=m
# CONFIG_LIBIPW_DEBUG is not set
CONFIG_IWLEGACY=m
CONFIG_IWL4965=m
CONFIG_IWL3945=m

#
# iwl3945 / iwl4965 Debugging Options
#
# CONFIG_IWLEGACY_DEBUG is not set
# end of iwl3945 / iwl4965 Debugging Options

CONFIG_IWLWIFI=m
CONFIG_IWLWIFI_LEDS=y
CONFIG_IWLDVM=m
CONFIG_IWLMVM=m
# CONFIG_IWLMLD is not set
CONFIG_IWLWIFI_OPMODE_MODULAR=y

#
# Debugging Options
#
# CONFIG_IWLWIFI_DEBUG is not set
# CONFIG_IWLWIFI_DEVICE_TRACING is not set
# end of Debugging Options

CONFIG_WLAN_VENDOR_INTERSIL=y
CONFIG_P54_COMMON=m
CONFIG_P54_USB=m
CONFIG_P54_PCI=m
CONFIG_P54_SPI=m
# CONFIG_P54_SPI_DEFAULT_EEPROM is not set
CONFIG_P54_LEDS=y
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_USB=m
CONFIG_LIBERTAS_SDIO=m
CONFIG_LIBERTAS_SPI=m
# CONFIG_LIBERTAS_DEBUG is not set
CONFIG_LIBERTAS_MESH=y
CONFIG_LIBERTAS_THINFIRM=m
# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
CONFIG_LIBERTAS_THINFIRM_USB=m
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_SDIO=m
CONFIG_MWIFIEX_PCIE=m
CONFIG_MWIFIEX_USB=m
CONFIG_MWL8K=m
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=m
CONFIG_MT76_CORE=m
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=m
CONFIG_MT76_SDIO=m
CONFIG_MT76x02_LIB=m
CONFIG_MT76x02_USB=m
CONFIG_MT76_CONNAC_LIB=m
CONFIG_MT792x_LIB=m
CONFIG_MT792x_USB=m
CONFIG_MT76x0_COMMON=m
CONFIG_MT76x0U=m
CONFIG_MT76x0E=m
CONFIG_MT76x2_COMMON=m
CONFIG_MT76x2E=m
CONFIG_MT76x2U=m
CONFIG_MT7603E=m
CONFIG_MT7615_COMMON=m
CONFIG_MT7615E=m
CONFIG_MT7663_USB_SDIO_COMMON=m
CONFIG_MT7663U=m
CONFIG_MT7663S=m
CONFIG_MT7915E=m
CONFIG_MT7921_COMMON=m
CONFIG_MT7921E=m
CONFIG_MT7921S=m
CONFIG_MT7921U=m
CONFIG_MT7996E=m
CONFIG_MT7925_COMMON=m
CONFIG_MT7925E=m
CONFIG_MT7925U=m
CONFIG_WLAN_VENDOR_MICROCHIP=y
CONFIG_WILC1000=m
CONFIG_WILC1000_SDIO=m
# CONFIG_WILC1000_SPI is not set
# CONFIG_WILC1000_HW_OOB_INTR is not set
CONFIG_WLAN_VENDOR_PURELIFI=y
# CONFIG_PLFXLC is not set
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=m
# CONFIG_RT2400PCI is not set
# CONFIG_RT2500PCI is not set
# CONFIG_RT61PCI is not set
CONFIG_RT2800PCI=m
CONFIG_RT2800PCI_RT33XX=y
CONFIG_RT2800PCI_RT35XX=y
CONFIG_RT2800PCI_RT53XX=y
CONFIG_RT2800PCI_RT3290=y
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
CONFIG_RT2800USB_RT33XX=y
CONFIG_RT2800USB_RT35XX=y
CONFIG_RT2800USB_RT3573=y
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
CONFIG_RT2800USB_UNKNOWN=y
CONFIG_RT2800_LIB=m
CONFIG_RT2800_LIB_MMIO=m
CONFIG_RT2X00_LIB_MMIO=m
CONFIG_RT2X00_LIB_PCI=m
CONFIG_RT2X00_LIB_USB=m
CONFIG_RT2X00_LIB=m
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
# CONFIG_RT2X00_DEBUG is not set
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_RTL8180=m
CONFIG_RTL8187=m
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=m
CONFIG_RTL8192CE=m
CONFIG_RTL8192SE=m
CONFIG_RTL8192DE=m
CONFIG_RTL8723AE=m
CONFIG_RTL8723BE=m
CONFIG_RTL8188EE=m
CONFIG_RTL8192EE=m
CONFIG_RTL8821AE=m
CONFIG_RTL8192CU=m
CONFIG_RTL8192DU=m
CONFIG_RTLWIFI=m
CONFIG_RTLWIFI_PCI=m
CONFIG_RTLWIFI_USB=m
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8192D_COMMON=m
CONFIG_RTL8723_COMMON=m
CONFIG_RTLBTCOEXIST=m
CONFIG_RTL8XXXU=m
# CONFIG_RTL8XXXU_UNTESTED is not set
CONFIG_RTW88=m
CONFIG_RTW88_CORE=m
CONFIG_RTW88_PCI=m
CONFIG_RTW88_SDIO=m
CONFIG_RTW88_USB=m
CONFIG_RTW88_8822B=m
CONFIG_RTW88_8822C=m
CONFIG_RTW88_8723X=m
CONFIG_RTW88_8703B=m
CONFIG_RTW88_8723D=m
CONFIG_RTW88_8821C=m
CONFIG_RTW88_8822BE=m
CONFIG_RTW88_8822BS=m
CONFIG_RTW88_8822BU=m
CONFIG_RTW88_8822CE=m
CONFIG_RTW88_8822CS=m
CONFIG_RTW88_8822CU=m
CONFIG_RTW88_8723DE=m
CONFIG_RTW88_8723DS=m
CONFIG_RTW88_8723CS=m
CONFIG_RTW88_8723DU=m
CONFIG_RTW88_8821CE=m
CONFIG_RTW88_8821CS=m
CONFIG_RTW88_8821CU=m
# CONFIG_RTW88_8821AU is not set
# CONFIG_RTW88_8812AU is not set
# CONFIG_RTW88_8814AE is not set
# CONFIG_RTW88_8814AU is not set
# CONFIG_RTW88_DEBUG is not set
# CONFIG_RTW88_DEBUGFS is not set
CONFIG_RTW88_LEDS=y
CONFIG_RTW89=m
CONFIG_RTW89_CORE=m
CONFIG_RTW89_PCI=m
CONFIG_RTW89_USB=m
CONFIG_RTW89_8851B=m
CONFIG_RTW89_8852A=m
CONFIG_RTW89_8852B_COMMON=m
CONFIG_RTW89_8852B=m
CONFIG_RTW89_8852BT=m
CONFIG_RTW89_8852C=m
CONFIG_RTW89_8922A=m
CONFIG_RTW89_8851BE=m
CONFIG_RTW89_8851BU=m
CONFIG_RTW89_8852AE=m
CONFIG_RTW89_8852AU=m
CONFIG_RTW89_8852BE=m
CONFIG_RTW89_8852BU=m
CONFIG_RTW89_8852BTE=m
CONFIG_RTW89_8852CE=m
CONFIG_RTW89_8852CU=m
CONFIG_RTW89_8922AE=m
# CONFIG_RTW89_DEBUGMSG is not set
CONFIG_WLAN_VENDOR_RSI=y
CONFIG_RSI_91X=m
CONFIG_RSI_DEBUGFS=y
CONFIG_RSI_SDIO=m
CONFIG_RSI_USB=m
CONFIG_RSI_COEX=y
CONFIG_WLAN_VENDOR_SILABS=y
# CONFIG_WFX is not set
CONFIG_WLAN_VENDOR_ST=y
CONFIG_CW1200=m
CONFIG_CW1200_WLAN_SDIO=m
CONFIG_CW1200_WLAN_SPI=m
CONFIG_WLAN_VENDOR_TI=y
CONFIG_WL1251=m
# CONFIG_WL1251_SPI is not set
CONFIG_WL1251_SDIO=m
# CONFIG_WL12XX is not set
# CONFIG_WL18XX is not set
CONFIG_WLCORE=m
# CONFIG_WLCORE_SPI is not set
CONFIG_WLCORE_SDIO=m
CONFIG_WLAN_VENDOR_ZYDAS=y
CONFIG_ZD1211RW=m
# CONFIG_ZD1211RW_DEBUG is not set
CONFIG_WLAN_VENDOR_QUANTENNA=y
CONFIG_QTNFMAC=m
CONFIG_QTNFMAC_PCIE=m
CONFIG_MAC80211_HWSIM=m
CONFIG_VIRT_WIFI=m
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
CONFIG_IEEE802154_AT86RF230=m
CONFIG_IEEE802154_MRF24J40=m
CONFIG_IEEE802154_CC2520=m
CONFIG_IEEE802154_ATUSB=m
CONFIG_IEEE802154_ADF7242=m
CONFIG_IEEE802154_CA8210=m
CONFIG_IEEE802154_CA8210_DEBUGFS=y
CONFIG_IEEE802154_MCR20A=m
CONFIG_IEEE802154_HWSIM=m

#
# Wireless WAN
#
CONFIG_WWAN=m
CONFIG_WWAN_DEBUGFS=y
CONFIG_WWAN_HWSIM=m
CONFIG_MHI_WWAN_CTRL=m
CONFIG_MHI_WWAN_MBIM=m
CONFIG_RPMSG_WWAN_CTRL=m
CONFIG_IOSM=m
CONFIG_MTK_T7XX=m
# end of Wireless WAN

CONFIG_VMXNET3=m
# CONFIG_FUJITSU_ES is not set
CONFIG_NETDEVSIM=m
CONFIG_NET_FAILOVER=m
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_SPARSEKMAP is not set
CONFIG_INPUT_MATRIXKMAP=m
CONFIG_INPUT_VIVALDIFMAP=m

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=m
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=m
CONFIG_INPUT_EVDEV=y

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADC is not set
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_GPIO_BUTTON_HOTPLUG is not set
CONFIG_KEYBOARD_GPIO_POLLED=y
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_PINEPHONE is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
CONFIG_KEYBOARD_SUN4I_LRADC=m
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_KEYBOARD_CYPRESS_SF is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=m
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
CONFIG_MOUSE_PS2_SENTELIC=y
CONFIG_MOUSE_PS2_TOUCHKIT=y
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_SMBUS=y
CONFIG_MOUSE_SERIAL=m
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=m
CONFIG_MOUSE_ELAN_I2C=m
CONFIG_MOUSE_ELAN_I2C_I2C=y
CONFIG_MOUSE_ELAN_I2C_SMBUS=y
CONFIG_MOUSE_VSXXXAA=m
CONFIG_MOUSE_GPIO=m
CONFIG_MOUSE_SYNAPTICS_I2C=m
CONFIG_MOUSE_SYNAPTICS_USB=m
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_ANALOG=m
CONFIG_JOYSTICK_A3D=m
CONFIG_JOYSTICK_ADC=m
CONFIG_JOYSTICK_ADI=m
CONFIG_JOYSTICK_COBRA=m
CONFIG_JOYSTICK_GF2K=m
CONFIG_JOYSTICK_GRIP=m
CONFIG_JOYSTICK_GRIP_MP=m
CONFIG_JOYSTICK_GUILLEMOT=m
CONFIG_JOYSTICK_INTERACT=m
CONFIG_JOYSTICK_SIDEWINDER=m
CONFIG_JOYSTICK_TMDC=m
CONFIG_JOYSTICK_IFORCE=m
CONFIG_JOYSTICK_IFORCE_USB=m
CONFIG_JOYSTICK_IFORCE_232=m
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
CONFIG_JOYSTICK_STINGER=m
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
CONFIG_JOYSTICK_AS5011=m
CONFIG_JOYSTICK_JOYDUMP=m
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_JOYSTICK_PSXPAD_SPI=m
CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
CONFIG_JOYSTICK_PXRC=m
CONFIG_JOYSTICK_QWIIC=m
CONFIG_JOYSTICK_FSIA6B=m
CONFIG_JOYSTICK_SENSEHAT=m
# CONFIG_JOYSTICK_SEESAW is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=m
CONFIG_TOUCHSCREEN_AD7877=m
CONFIG_TOUCHSCREEN_AD7879=m
CONFIG_TOUCHSCREEN_AD7879_I2C=m
CONFIG_TOUCHSCREEN_AD7879_SPI=m
CONFIG_TOUCHSCREEN_ADC=m
CONFIG_TOUCHSCREEN_AR1021_I2C=m
CONFIG_TOUCHSCREEN_ATMEL_MXT=m
CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y
CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
CONFIG_TOUCHSCREEN_BU21013=m
CONFIG_TOUCHSCREEN_BU21029=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
CONFIG_TOUCHSCREEN_CY8CTMA140=m
CONFIG_TOUCHSCREEN_CY8CTMG110=m
CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
# CONFIG_TOUCHSCREEN_CYTTSP5 is not set
CONFIG_TOUCHSCREEN_DYNAPRO=m
CONFIG_TOUCHSCREEN_HAMPSHIRE=m
CONFIG_TOUCHSCREEN_EETI=m
CONFIG_TOUCHSCREEN_EGALAX=m
CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
CONFIG_TOUCHSCREEN_EXC3000=m
CONFIG_TOUCHSCREEN_FUJITSU=m
CONFIG_TOUCHSCREEN_GOODIX=m
# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C is not set
# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI is not set
CONFIG_TOUCHSCREEN_HIDEEP=m
# CONFIG_TOUCHSCREEN_HIMAX_HX852X is not set
CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
# CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set
# CONFIG_TOUCHSCREEN_HYNITRON_CST816X is not set
CONFIG_TOUCHSCREEN_ILI210X=m
CONFIG_TOUCHSCREEN_ILITEK=m
CONFIG_TOUCHSCREEN_S6SY761=m
CONFIG_TOUCHSCREEN_GUNZE=m
CONFIG_TOUCHSCREEN_EKTF2127=m
CONFIG_TOUCHSCREEN_ELAN=m
CONFIG_TOUCHSCREEN_ELO=m
CONFIG_TOUCHSCREEN_WACOM_W8001=m
CONFIG_TOUCHSCREEN_WACOM_I2C=m
CONFIG_TOUCHSCREEN_MAX11801=m
CONFIG_TOUCHSCREEN_MMS114=m
CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
CONFIG_TOUCHSCREEN_MSG2638=m
CONFIG_TOUCHSCREEN_MTOUCH=m
# CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS is not set
CONFIG_TOUCHSCREEN_IMAGIS=m
CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
CONFIG_TOUCHSCREEN_INEXIO=m
CONFIG_TOUCHSCREEN_PENMOUNT=m
CONFIG_TOUCHSCREEN_EDT_FT5X06=m
CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
CONFIG_TOUCHSCREEN_TOUCHWIN=m
CONFIG_TOUCHSCREEN_PIXCIR=m
CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
CONFIG_TOUCHSCREEN_WM97XX=m
CONFIG_TOUCHSCREEN_WM9705=y
CONFIG_TOUCHSCREEN_WM9712=y
CONFIG_TOUCHSCREEN_WM9713=y
CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
CONFIG_TOUCHSCREEN_TOUCHIT213=m
CONFIG_TOUCHSCREEN_TSC_SERIO=m
CONFIG_TOUCHSCREEN_TSC200X_CORE=m
CONFIG_TOUCHSCREEN_TSC2004=m
CONFIG_TOUCHSCREEN_TSC2005=m
CONFIG_TOUCHSCREEN_TSC2007=m
CONFIG_TOUCHSCREEN_TSC2007_IIO=y
CONFIG_TOUCHSCREEN_RM_TS=m
CONFIG_TOUCHSCREEN_SILEAD=m
CONFIG_TOUCHSCREEN_SIS_I2C=m
CONFIG_TOUCHSCREEN_ST1232=m
CONFIG_TOUCHSCREEN_STMFTS=m
CONFIG_TOUCHSCREEN_SUN4I=y
CONFIG_TOUCHSCREEN_SUR40=m
CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
CONFIG_TOUCHSCREEN_SX8654=m
CONFIG_TOUCHSCREEN_TPS6507X=m
CONFIG_TOUCHSCREEN_ZET6223=m
CONFIG_TOUCHSCREEN_ZFORCE=m
CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
CONFIG_TOUCHSCREEN_ROHM_BU21023=m
CONFIG_TOUCHSCREEN_IQS5XX=m
# CONFIG_TOUCHSCREEN_IQS7211 is not set
CONFIG_TOUCHSCREEN_ZINITIX=m
# CONFIG_TOUCHSCREEN_HIMAX_HX83112B is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
# CONFIG_INPUT_AW86927 is not set
# CONFIG_INPUT_BMA150 is not set
# CONFIG_INPUT_E3X0_BUTTON is not set
# CONFIG_INPUT_MMA8450 is not set
CONFIG_INPUT_GPIO_BEEPER=m
CONFIG_INPUT_GPIO_DECODER=m
CONFIG_INPUT_GPIO_VIBRA=m
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
# CONFIG_INPUT_KXTJ9 is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
CONFIG_INPUT_CM109=m
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
CONFIG_INPUT_AXP20X_PEK=y
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_PCF8574 is not set
CONFIG_INPUT_PWM_BEEPER=m
CONFIG_INPUT_PWM_VIBRA=m
CONFIG_INPUT_RK805_PWRKEY=y
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_DA7280_HAPTICS is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_IBM_PANEL is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_INPUT_IQS269A is not set
# CONFIG_INPUT_IQS626A is not set
# CONFIG_INPUT_IQS7222 is not set
# CONFIG_INPUT_CMA3000 is not set
# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
# CONFIG_INPUT_DRV260X_HAPTICS is not set
# CONFIG_INPUT_DRV2665_HAPTICS is not set
# CONFIG_INPUT_DRV2667_HAPTICS is not set
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=y
CONFIG_RMI4_SPI=y
CONFIG_RMI4_SMB=y
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=y
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
# CONFIG_RMI4_F1A is not set
# CONFIG_RMI4_F21 is not set
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
CONFIG_RMI4_F3A=y
CONFIG_RMI4_F54=y
CONFIG_RMI4_F55=y

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=m
# CONFIG_SERIO_AMBAKMI is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=m
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
CONFIG_SERIO_SUN4I_PS2=y
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
CONFIG_GAMEPORT=m
# CONFIG_GAMEPORT_EMU10K1 is not set
# CONFIG_GAMEPORT_FM801 is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_LEGACY_TIOCSTI=y
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
# CONFIG_SERIAL_8250_PCI is not set
# CONFIG_SERIAL_8250_EXAR is not set
CONFIG_SERIAL_8250_NR_UARTS=5
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
# CONFIG_SERIAL_8250_EXTENDED is not set
# CONFIG_SERIAL_8250_PCI1XXXX is not set
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
# CONFIG_SERIAL_8250_DFL is not set
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_8250_PERICOM=m
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
CONFIG_SERIAL_AMBA_PL010=y
CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set
CONFIG_SERIAL_MESON=y
CONFIG_SERIAL_MESON_CONSOLE=y
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_QE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_NOZOMI is not set
# CONFIG_NULL_TTY is not set
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
# CONFIG_RPMSG_TTY is not set
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_TTY_PRINTK is not set
CONFIG_VIRTIO_CONSOLE=m
# CONFIG_IPMI_HANDLER is not set
# CONFIG_SSIF_IPMI_BMC is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=y
CONFIG_HW_RANDOM_BA431=m
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_MESON=y
CONFIG_HW_RANDOM_OPTEE=m
CONFIG_HW_RANDOM_CCTRNG=m
CONFIG_HW_RANDOM_XIPHERA=m
CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
CONFIG_HW_RANDOM_CN10K=m
CONFIG_HW_RANDOM_ROCKCHIP=m
# CONFIG_APPLICOM is not set
CONFIG_DEVMEM=y
CONFIG_DEVPORT=y
# CONFIG_TCG_TPM is not set
# CONFIG_XILLYBUS is not set
# CONFIG_XILLYUSB is not set
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_I2C_MUX_GPIO=y
CONFIG_I2C_MUX_GPMUX=y
CONFIG_I2C_MUX_LTC4306=m
CONFIG_I2C_MUX_PCA9541=m
CONFIG_I2C_MUX_PCA954x=m
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_MUX_REG=y
CONFIG_I2C_DEMUX_PINCTRL=y
CONFIG_I2C_MUX_MLXCPLD=m
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_ALGOBIT=y

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
CONFIG_I2C_CCGX_UCSI=m
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set
# CONFIG_I2C_ZHAOXIN is not set

#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CADENCE is not set
# CONFIG_I2C_CBUS_GPIO is not set
CONFIG_I2C_DESIGNWARE_CORE=y
CONFIG_I2C_DESIGNWARE_SLAVE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_DESIGNWARE_PCI=m
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=y
CONFIG_I2C_GPIO_FAULT_INJECTOR=y
# CONFIG_I2C_HISI is not set
CONFIG_I2C_MESON=y
CONFIG_I2C_MV64XXX=y
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
CONFIG_I2C_RK3X=y
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_THUNDERX is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_CP2615 is not set
# CONFIG_I2C_PCI1XXXX is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_MLXCPLD is not set
CONFIG_I2C_VIRTIO=m
# end of I2C Hardware Bus support

# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=m
CONFIG_I2C_SLAVE_TESTUNIT=m
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

# CONFIG_I3C is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_OFFLOAD=y

#
# SPI Master Controller Drivers
#
CONFIG_SPI_ALTERA=m
CONFIG_SPI_ALTERA_CORE=m
CONFIG_SPI_ALTERA_DFL=m
CONFIG_SPI_AMLOGIC_SPIFC_A1=y
# CONFIG_SPI_AMLOGIC_SPIFC_A4 is not set
# CONFIG_SPI_AMLOGIC_SPISG is not set
CONFIG_SPI_AXI_SPI_ENGINE=m
CONFIG_SPI_BITBANG=m
CONFIG_SPI_CADENCE=m
CONFIG_SPI_CADENCE_QUADSPI=m
CONFIG_SPI_CADENCE_XSPI=m
CONFIG_SPI_CH341=m
CONFIG_SPI_DESIGNWARE=y
CONFIG_SPI_DW_DMA=y
CONFIG_SPI_DW_PCI=y
CONFIG_SPI_DW_MMIO=m
# CONFIG_SPI_HISI_KUNPENG is not set
# CONFIG_SPI_HISI_SFC_V3XX is not set
CONFIG_SPI_GPIO=m
CONFIG_SPI_FSL_LIB=m
CONFIG_SPI_FSL_SPI=m
CONFIG_SPI_MESON_SPICC=y
CONFIG_SPI_MESON_SPIFC=y
# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
CONFIG_SPI_OC_TINY=m
# CONFIG_SPI_PCI1XXXX is not set
CONFIG_SPI_PL022=m
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_ROCKCHIP_SFC=y
CONFIG_SPI_SC18IS602=m
CONFIG_SPI_SIFIVE=m
# CONFIG_SPI_SN_F_OSPI is not set
CONFIG_SPI_SUN4I=y
CONFIG_SPI_SUN6I=y
CONFIG_SPI_MXIC=m
CONFIG_SPI_THUNDERX=m
# CONFIG_SPI_VIRTIO is not set
CONFIG_SPI_XCOMM=m
CONFIG_SPI_XILINX=m
CONFIG_SPI_ZYNQMP_GQSPI=m
CONFIG_SPI_AMD=m

#
# SPI Multiplexer support
#
CONFIG_SPI_MUX=m

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=m
CONFIG_SPI_LOOPBACK_TEST=m
CONFIG_SPI_TLE62X0=m
CONFIG_SPI_SLAVE=y
CONFIG_SPI_SLAVE_TIME=m
CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
CONFIG_SPI_DYNAMIC=y

#
# SPI Offload triggers
#
# CONFIG_SPI_OFFLOAD_TRIGGER_ADI_UTIL_SD is not set
# CONFIG_SPI_OFFLOAD_TRIGGER_PWM is not set
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set
CONFIG_NTP_PPS=y

#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
# CONFIG_PPS_CLIENT_LDISC is not set
# CONFIG_PPS_CLIENT_GPIO is not set
# CONFIG_PPS_GENERATOR is not set

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
CONFIG_PTP_1588_CLOCK_KVM=m
CONFIG_PTP_1588_CLOCK_VMCLOCK=m
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
# CONFIG_PTP_1588_CLOCK_FC3W is not set
# CONFIG_PTP_1588_CLOCK_MOCK is not set
# CONFIG_PTP_1588_CLOCK_OCP is not set
# CONFIG_PTP_DFL_TOD is not set
# CONFIG_PTP_NETC_V4_TIMER is not set
# end of PTP clock support

#
# DPLL device support
#
# CONFIG_ZL3073X_I2C is not set
# CONFIG_ZL3073X_SPI is not set
# end of DPLL device support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_PINCTRL_AMD is not set
CONFIG_PINCTRL_AXP209=y
# CONFIG_PINCTRL_AW9523 is not set
# CONFIG_PINCTRL_CY8C95X0 is not set
CONFIG_PINCTRL_MCP23S08_I2C=m
CONFIG_PINCTRL_MCP23S08_SPI=m
CONFIG_PINCTRL_MCP23S08=m
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
# CONFIG_PINCTRL_OCELOT is not set
CONFIG_PINCTRL_RK805=y
CONFIG_PINCTRL_ROCKCHIP=y
# CONFIG_PINCTRL_SCMI is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_PINCTRL_STMFX=m
# CONFIG_PINCTRL_SX150X is not set
# CONFIG_PINCTRL_IMX_SCMI is not set
CONFIG_PINCTRL_MESON=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_PINCTRL_MESON8_PMX=y
CONFIG_PINCTRL_MESON_AXG=y
CONFIG_PINCTRL_MESON_AXG_PMX=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_PINCTRL_MESON_A1=y
CONFIG_PINCTRL_MESON_S4=y
CONFIG_PINCTRL_AMLOGIC_A4=y
CONFIG_PINCTRL_AMLOGIC_C3=y
CONFIG_PINCTRL_AMLOGIC_T7=y

#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers

CONFIG_PINCTRL_SUNXI=y
CONFIG_PINCTRL_SUN4I_A10=y
CONFIG_PINCTRL_SUN5I=y
CONFIG_PINCTRL_SUN6I_A31=y
CONFIG_PINCTRL_SUN6I_A31_R=y
CONFIG_PINCTRL_SUN8I_A23=y
CONFIG_PINCTRL_SUN8I_A33=y
CONFIG_PINCTRL_SUN8I_A83T=y
CONFIG_PINCTRL_SUN8I_A83T_R=y
CONFIG_PINCTRL_SUN8I_A23_R=y
CONFIG_PINCTRL_SUN8I_H3=y
CONFIG_PINCTRL_SUN8I_H3_R=y
CONFIG_PINCTRL_SUN8I_V3S=y
CONFIG_PINCTRL_SUN9I_A80=y
CONFIG_PINCTRL_SUN9I_A80_R=y
CONFIG_PINCTRL_SUN20I_D1=y
CONFIG_PINCTRL_SUN50I_A64=y
CONFIG_PINCTRL_SUN50I_A64_R=y
CONFIG_PINCTRL_SUN50I_A100=y
CONFIG_PINCTRL_SUN50I_A100_R=y
CONFIG_PINCTRL_SUN50I_H5=y
CONFIG_PINCTRL_SUN50I_H6=y
CONFIG_PINCTRL_SUN50I_H6_R=y
CONFIG_PINCTRL_SUN50I_H616=y
CONFIG_PINCTRL_SUN50I_H616_R=y
CONFIG_PINCTRL_SUN55I_A523=y
CONFIG_PINCTRL_SUN55I_A523_R=y
CONFIG_GPIOLIB_LEGACY=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_SYSFS_LEGACY=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_MAX730X=m

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_FTGPIO010 is not set
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HISI is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_LOGICVC is not set
# CONFIG_GPIO_MB86S7X is not set
CONFIG_GPIO_PL061=y
# CONFIG_GPIO_POLARFIRE_SOC is not set
CONFIG_GPIO_ROCKCHIP=y
# CONFIG_GPIO_SIFIVE is not set
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_XGENE=y
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
CONFIG_GPIO_ADNP=m
# CONFIG_GPIO_FXL6408 is not set
# CONFIG_GPIO_DS4520 is not set
CONFIG_GPIO_GW_PLD=m
CONFIG_GPIO_MAX7300=m
CONFIG_GPIO_MAX732X=m
CONFIG_GPIO_PCA953X=m
# CONFIG_GPIO_PCA953X_IRQ is not set
CONFIG_GPIO_PCA9570=m
CONFIG_GPIO_PCF857X=m
CONFIG_GPIO_TPIC2810=m
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set
# end of PCI GPIO expanders

#
# SPI GPIO expanders
#
CONFIG_GPIO_74X164=m
CONFIG_GPIO_MAX3191X=m
CONFIG_GPIO_MAX7301=m
CONFIG_GPIO_MC33880=m
CONFIG_GPIO_PISOSR=m
CONFIG_GPIO_XRA1403=m
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
# CONFIG_GPIO_MPSSE is not set
# end of USB GPIO expanders

#
# Virtual GPIO drivers
#
CONFIG_GPIO_AGGREGATOR=m
# CONFIG_GPIO_LATCH is not set
CONFIG_GPIO_MOCKUP=m
CONFIG_GPIO_VIRTIO=m
CONFIG_GPIO_SIM=m
# end of Virtual GPIO drivers

#
# GPIO Debugging utilities
#
# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set
# CONFIG_GPIO_VIRTUSER is not set
# end of GPIO Debugging utilities

CONFIG_DEV_SYNC_PROBE=m
CONFIG_W1=m
CONFIG_W1_CON=y

#
# 1-wire Bus Masters
#
# CONFIG_W1_MASTER_AMD_AXI is not set
CONFIG_W1_MASTER_MATROX=m
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
CONFIG_W1_MASTER_GPIO=m
CONFIG_W1_MASTER_SGI=m
# CONFIG_W1_MASTER_UART is not set
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
CONFIG_W1_SLAVE_DS2405=m
CONFIG_W1_SLAVE_DS2408=m
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
CONFIG_W1_SLAVE_DS2805=m
CONFIG_W1_SLAVE_DS2430=m
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
CONFIG_W1_SLAVE_DS2438=m
CONFIG_W1_SLAVE_DS250X=m
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
CONFIG_W1_SLAVE_DS28E17=m
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
# CONFIG_POWER_RESET_ODROID_GO_ULTRA_POWEROFF is not set
CONFIG_POWER_RESET_LTC2952=y
CONFIG_POWER_RESET_REGULATOR=y
CONFIG_POWER_RESET_RESTART=y
CONFIG_POWER_RESET_VEXPRESS=y
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
CONFIG_NVMEM_REBOOT_MODE=y
# CONFIG_POWER_SEQUENCING is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_IP5XXX_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_CHAGALL is not set
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SAMSUNG_SDI is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_CHARGER_AXP20X is not set
# CONFIG_BATTERY_AXP20X is not set
CONFIG_AXP20X_POWER=y
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_BATTERY_MAX1720X is not set
# CONFIG_BATTERY_MAX1721X is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
CONFIG_CHARGER_GPIO=m
CONFIG_CHARGER_MANAGER=m
CONFIG_CHARGER_LT3651=m
CONFIG_CHARGER_LTC4162L=m
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_MAX77976 is not set
# CONFIG_CHARGER_MAX8971 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_BQ25980 is not set
# CONFIG_CHARGER_BQ256XX is not set
CONFIG_CHARGER_RK817=y
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_BATTERY_GOLDFISH is not set
# CONFIG_BATTERY_RT5033 is not set
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_RT9467 is not set
# CONFIG_CHARGER_RT9471 is not set
# CONFIG_FUEL_GAUGE_STC3117 is not set
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
# CONFIG_BATTERY_UG3105 is not set
# CONFIG_FUEL_GAUGE_MM8013 is not set
CONFIG_HWMON=y
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM1177 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7310 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_AHT10 is not set
# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
# CONFIG_SENSORS_AS370 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set
# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
CONFIG_SENSORS_ARM_SCMI=y
CONFIG_SENSORS_ARM_SCPI=y
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_CHIPCAP2 is not set
# CONFIG_SENSORS_CORSAIR_CPRO is not set
# CONFIG_SENSORS_CORSAIR_PSU is not set
# CONFIG_SENSORS_DRIVETEMP is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_I5K_AMB is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_FTSTEUTATES is not set
# CONFIG_SENSORS_GIGABYTE_WATERFORCE is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_G762 is not set
CONFIG_SENSORS_GPIO_FAN=m
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_HS3001 is not set
# CONFIG_SENSORS_HTU31 is not set
# CONFIG_SENSORS_IIO_HWMON is not set
# CONFIG_SENSORS_ISL28022 is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_POWERZ is not set
# CONFIG_SENSORS_POWR1220 is not set
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LTC2945 is not set
# CONFIG_SENSORS_LTC2947_I2C is not set
# CONFIG_SENSORS_LTC2947_SPI is not set
# CONFIG_SENSORS_LTC2990 is not set
# CONFIG_SENSORS_LTC2991 is not set
# CONFIG_SENSORS_LTC2992 is not set
# CONFIG_SENSORS_LTC4151 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4222 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LTC4260 is not set
# CONFIG_SENSORS_LTC4261 is not set
# CONFIG_SENSORS_LTC4282 is not set
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX127 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX197 is not set
# CONFIG_SENSORS_MAX31722 is not set
# CONFIG_SENSORS_MAX31730 is not set
# CONFIG_SENSORS_MAX31760 is not set
# CONFIG_MAX31827 is not set
# CONFIG_SENSORS_MAX6620 is not set
# CONFIG_SENSORS_MAX6621 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MAX6697 is not set
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MC34VR500 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_TPS23861 is not set
# CONFIG_SENSORS_MR75203 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LM95234 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_NCT6683 is not set
# CONFIG_SENSORS_NCT6775 is not set
# CONFIG_SENSORS_NCT6775_I2C is not set
# CONFIG_SENSORS_NCT7363 is not set
# CONFIG_SENSORS_NCT7802 is not set
# CONFIG_SENSORS_NCT7904 is not set
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
# CONFIG_SENSORS_NZXT_KRAKEN3 is not set
# CONFIG_SENSORS_NZXT_SMART2 is not set
# CONFIG_SENSORS_OCC_P8_I2C is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_PMBUS is not set
# CONFIG_SENSORS_PT5161L is not set
CONFIG_SENSORS_PWM_FAN=m
# CONFIG_SENSORS_SBTSI is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHT4x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC2305 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA238 is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_SPD5118 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_TMP464 is not set
# CONFIG_SENSORS_TMP513 is not set
# CONFIG_SENSORS_VEXPRESS is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_XGENE is not set

#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
# CONFIG_THERMAL_DEBUGFS is not set
# CONFIG_THERMAL_CORE_TESTING is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
# CONFIG_THERMAL_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
# CONFIG_PCIE_THERMAL is not set
# CONFIG_THERMAL_EMULATION is not set
CONFIG_THERMAL_MMIO=y
CONFIG_SUN8I_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_AMLOGIC_THERMAL=y
CONFIG_GENERIC_ADC_THERMAL=m
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set
# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=m
# CONFIG_GPIO_WATCHDOG is not set
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_XILINX_WINDOW_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
CONFIG_ARM_SP805_WATCHDOG=m
CONFIG_ARM_SBSA_WATCHDOG=y
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=m
CONFIG_SUNXI_WATCHDOG=m
# CONFIG_MAX63XX_WATCHDOG is not set
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_WATCHDOG=m
# CONFIG_ARM_SMC_WATCHDOG is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_HP_WATCHDOG is not set
# CONFIG_NIC7018_WDT is not set
# CONFIG_MEN_A21_WDT is not set

#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
CONFIG_BCMA_HOST_PCI=y
CONFIG_BCMA_HOST_SOC=y
CONFIG_BCMA_DRIVER_PCI=y
CONFIG_BCMA_SFLASH=y
CONFIG_BCMA_DRIVER_GMAC_CMN=y
CONFIG_BCMA_DRIVER_GPIO=y
CONFIG_BCMA_DEBUG=y

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ADP5585 is not set
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_SMPRO is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
CONFIG_MFD_AC100=y
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
# CONFIG_MFD_CS40L50_I2C is not set
# CONFIG_MFD_CS40L50_SPI is not set
# CONFIG_MFD_CS42L43_I2C is not set
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_MADERA is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_88PM886_PMIC is not set
# CONFIG_MFD_MAX5970 is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77541 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77705 is not set
# CONFIG_MFD_MAX77714 is not set
# CONFIG_MFD_MAX77759 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6370 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_MFD_NCT6694 is not set
# CONFIG_MFD_OCELOT is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_NTXEC is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_SY7636A is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT4831 is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RT5120 is not set
# CONFIG_MFD_RC5T583 is not set
CONFIG_MFD_RK8XX=y
CONFIG_MFD_RK8XX_I2C=y
CONFIG_MFD_RK8XX_SPI=y
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_I2C is not set
# CONFIG_MFD_SI476X_CORE is not set
CONFIG_MFD_SIMPLE_MFD_I2C=m
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SUN6I_PRCM=y
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_BQ257XX is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS65219 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS6594_I2C is not set
# CONFIG_MFD_TPS6594_SPI is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TQMX86 is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
# CONFIG_MFD_ROHM_BD71828 is not set
# CONFIG_MFD_ROHM_BD957XMUF is not set
# CONFIG_MFD_ROHM_BD96801 is not set
# CONFIG_MFD_STPMIC1 is not set
CONFIG_MFD_STMFX=m
# CONFIG_MFD_ATC260X_I2C is not set
# CONFIG_MFD_KHADAS_MCU is not set
# CONFIG_MFD_QCOM_PM8008 is not set
# CONFIG_MFD_VEXPRESS_SYSREG is not set
# CONFIG_RAVE_SP_CORE is not set
# CONFIG_MFD_INTEL_M10_BMC_SPI is not set
# CONFIG_MFD_INTEL_M10_BMC_PMCI is not set
# CONFIG_MFD_LS2K_BMC_CORE is not set
# CONFIG_MFD_QNAP_MCU is not set
# CONFIG_MFD_RSMU_I2C is not set
# CONFIG_MFD_RSMU_SPI is not set
# CONFIG_MFD_MAX7360 is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_NETLINK_EVENTS is not set
# CONFIG_REGULATOR_88PG86X is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_AD5398 is not set
# CONFIG_REGULATOR_ADP5055 is not set
CONFIG_REGULATOR_ARM_SCMI=y
# CONFIG_REGULATOR_AW37503 is not set
CONFIG_REGULATOR_AXP20X=y
# CONFIG_REGULATOR_DA9121 is not set
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_FAN53880=y
CONFIG_REGULATOR_GPIO=y
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_LP8755 is not set
# CONFIG_REGULATOR_LTC3589 is not set
# CONFIG_REGULATOR_LTC3676 is not set
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX77503 is not set
# CONFIG_REGULATOR_MAX77857 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8893 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_MAX8973 is not set
# CONFIG_REGULATOR_MAX20086 is not set
# CONFIG_REGULATOR_MAX20411 is not set
# CONFIG_REGULATOR_MAX77826 is not set
# CONFIG_REGULATOR_MAX77838 is not set
# CONFIG_REGULATOR_MCP16502 is not set
# CONFIG_REGULATOR_MP5416 is not set
# CONFIG_REGULATOR_MP8859 is not set
# CONFIG_REGULATOR_MP886X is not set
# CONFIG_REGULATOR_MPQ7920 is not set
# CONFIG_REGULATOR_MT6311 is not set
# CONFIG_REGULATOR_MT6315 is not set
# CONFIG_REGULATOR_PCA9450 is not set
# CONFIG_REGULATOR_PF9453 is not set
# CONFIG_REGULATOR_PF0900 is not set
# CONFIG_REGULATOR_PF530X is not set
# CONFIG_REGULATOR_PF8X00 is not set
# CONFIG_REGULATOR_PFUZE100 is not set
# CONFIG_REGULATOR_PV88060 is not set
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
CONFIG_REGULATOR_PWM=y
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
# CONFIG_REGULATOR_RAA215300 is not set
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2 is not set
CONFIG_REGULATOR_RK808=y
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RT4803 is not set
# CONFIG_REGULATOR_RT5133 is not set
# CONFIG_REGULATOR_RT5190A is not set
# CONFIG_REGULATOR_RT5739 is not set
# CONFIG_REGULATOR_RT5759 is not set
# CONFIG_REGULATOR_RT6160 is not set
# CONFIG_REGULATOR_RT6190 is not set
# CONFIG_REGULATOR_RT6245 is not set
# CONFIG_REGULATOR_RTQ2134 is not set
# CONFIG_REGULATOR_RTMV20 is not set
# CONFIG_REGULATOR_RTQ6752 is not set
# CONFIG_REGULATOR_RTQ2208 is not set
# CONFIG_REGULATOR_SLG51000 is not set
CONFIG_REGULATOR_SUN20I=y
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
# CONFIG_REGULATOR_SY8827N is not set
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS6286X is not set
# CONFIG_REGULATOR_TPS6287X is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_TPS6524X is not set
CONFIG_REGULATOR_VCTRL=y
# CONFIG_REGULATOR_VEXPRESS is not set
# CONFIG_REGULATOR_QCOM_LABIBB is not set
CONFIG_RC_CORE=y
# CONFIG_BPF_LIRC_MODE2 is not set
CONFIG_LIRC=y
CONFIG_RC_MAP=y
CONFIG_RC_DECODERS=y
CONFIG_IR_IMON_DECODER=m
CONFIG_IR_JVC_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
CONFIG_IR_RCMM_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_XMP_DECODER=m
CONFIG_RC_DEVICES=y
# CONFIG_IR_ENE is not set
# CONFIG_IR_FINTEK is not set
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_GPIO_TX=m
CONFIG_IR_HIX5HD2=m
CONFIG_IR_IGORPLUGUSB=m
CONFIG_IR_IGUANA=m
CONFIG_IR_IMON=m
CONFIG_IR_IMON_RAW=m
# CONFIG_IR_ITE_CIR is not set
CONFIG_IR_MCEUSB=m
CONFIG_IR_MESON=m
CONFIG_IR_MESON_TX=m
# CONFIG_IR_NUVOTON is not set
CONFIG_IR_PWM_TX=m
CONFIG_IR_REDRAT3=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m
CONFIG_IR_SUNXI=m
CONFIG_IR_TOY=m
CONFIG_IR_TTUSBIR=m
CONFIG_RC_ATI_REMOTE=m
CONFIG_RC_LOOPBACK=m
CONFIG_RC_XBOX_DVD=m
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y

#
# CEC support
#
CONFIG_MEDIA_CEC_RC=y
CONFIG_MEDIA_CEC_SUPPORT=y
CONFIG_CEC_CH7322=m
# CONFIG_CEC_NXP_TDA9950 is not set
CONFIG_CEC_MESON_AO=y
CONFIG_CEC_MESON_G12A_AO=y
# CONFIG_CEC_GPIO is not set
# CONFIG_USB_EXTRON_DA_HD_4K_PLUS_CEC is not set
CONFIG_USB_PULSE8_CEC=m
CONFIG_USB_RAINSHADOW_CEC=m
# end of CEC support

CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_SUPPORT_FILTER=y
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_SDR_SUPPORT is not set
CONFIG_MEDIA_PLATFORM_SUPPORT=y
# CONFIG_MEDIA_TEST_SUPPORT is not set
# end of Media device types

CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CONTROLLER=y

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_ADV_DEBUG=y
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_H264=m
CONFIG_V4L2_VP9=m
CONFIG_V4L2_MEM2MEM_DEV=m
# CONFIG_V4L2_FLASH_LED_CLASS is not set
CONFIG_V4L2_FWNODE=y
CONFIG_V4L2_ASYNC=y
CONFIG_V4L2_CCI=m
CONFIG_V4L2_CCI_I2C=m
CONFIG_V4L2_ISP=m
# end of Video4Linux options

#
# Media controller options
#
# end of Media controller options

#
# Media drivers
#

#
# Drivers filtered as selected at 'Filter media drivers'
#

#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_GSPCA=m
CONFIG_USB_GSPCA_BENQ=m
CONFIG_USB_GSPCA_CONEX=m
CONFIG_USB_GSPCA_CPIA1=m
CONFIG_USB_GSPCA_DTCS033=m
CONFIG_USB_GSPCA_ETOMS=m
CONFIG_USB_GSPCA_FINEPIX=m
CONFIG_USB_GSPCA_JEILINJ=m
CONFIG_USB_GSPCA_JL2005BCD=m
CONFIG_USB_GSPCA_KINECT=m
CONFIG_USB_GSPCA_KONICA=m
CONFIG_USB_GSPCA_MARS=m
CONFIG_USB_GSPCA_MR97310A=m
CONFIG_USB_GSPCA_NW80X=m
CONFIG_USB_GSPCA_OV519=m
CONFIG_USB_GSPCA_OV534=m
CONFIG_USB_GSPCA_OV534_9=m
CONFIG_USB_GSPCA_PAC207=m
CONFIG_USB_GSPCA_PAC7302=m
CONFIG_USB_GSPCA_PAC7311=m
CONFIG_USB_GSPCA_SE401=m
CONFIG_USB_GSPCA_SN9C2028=m
CONFIG_USB_GSPCA_SN9C20X=m
CONFIG_USB_GSPCA_SONIXB=m
CONFIG_USB_GSPCA_SONIXJ=m
CONFIG_USB_GSPCA_SPCA1528=m
CONFIG_USB_GSPCA_SPCA500=m
CONFIG_USB_GSPCA_SPCA501=m
CONFIG_USB_GSPCA_SPCA505=m
CONFIG_USB_GSPCA_SPCA506=m
CONFIG_USB_GSPCA_SPCA508=m
CONFIG_USB_GSPCA_SPCA561=m
CONFIG_USB_GSPCA_SQ905=m
CONFIG_USB_GSPCA_SQ905C=m
CONFIG_USB_GSPCA_SQ930X=m
CONFIG_USB_GSPCA_STK014=m
CONFIG_USB_GSPCA_STK1135=m
CONFIG_USB_GSPCA_STV0680=m
CONFIG_USB_GSPCA_SUNPLUS=m
CONFIG_USB_GSPCA_T613=m
CONFIG_USB_GSPCA_TOPRO=m
CONFIG_USB_GSPCA_TOUPTEK=m
CONFIG_USB_GSPCA_TV8532=m
CONFIG_USB_GSPCA_VC032X=m
CONFIG_USB_GSPCA_VICAM=m
CONFIG_USB_GSPCA_XIRLINK_CIT=m
CONFIG_USB_GSPCA_ZC3XX=m
CONFIG_USB_GL860=m
CONFIG_USB_M5602=m
CONFIG_USB_STV06XX=m
CONFIG_USB_PWC=m
# CONFIG_USB_PWC_DEBUG is not set
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_USB_S2255=m
CONFIG_VIDEO_USBTV=m
CONFIG_USB_VIDEO_CLASS=m
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y

#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=m
CONFIG_VIDEO_EM28XX_V4L2=m
CONFIG_VIDEO_EM28XX_ALSA=m
CONFIG_VIDEO_EM28XX_RC=m
# CONFIG_MEDIA_PCI_SUPPORT is not set
CONFIG_MEDIA_PLATFORM_DRIVERS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
CONFIG_VIDEO_MUX=m

#
# Allegro DVT media platform drivers
#

#
# Amlogic media platform drivers
#
# CONFIG_VIDEO_C3_ISP is not set
# CONFIG_VIDEO_C3_MIPI_ADAPTER is not set
# CONFIG_VIDEO_C3_MIPI_CSI2 is not set
CONFIG_VIDEO_MESON_GE2D=m

#
# Amphion drivers
#

#
# ARM media platform drivers
#

#
# Aspeed media platform drivers
#

#
# Atmel media platform drivers
#

#
# Cadence media platform drivers
#
# CONFIG_VIDEO_CADENCE_CSI2RX is not set
# CONFIG_VIDEO_CADENCE_CSI2TX is not set

#
# Chips&Media media platform drivers
#

#
# Intel media platform drivers
#

#
# Marvell media platform drivers
#
# CONFIG_VIDEO_CAFE_CCIC is not set

#
# Mediatek media platform drivers
#

#
# Microchip Technology, Inc. media platform drivers
#

#
# Nuvoton media platform drivers
#

#
# NVidia media platform drivers
#

#
# NXP media platform drivers
#

#
# Qualcomm media platform drivers
#

#
# Raspberry Pi media platform drivers
#
# CONFIG_VIDEO_RP1_CFE is not set

#
# Renesas media platform drivers
#

#
# Rockchip media platform drivers
#
CONFIG_VIDEO_ROCKCHIP_RGA=m
# CONFIG_VIDEO_ROCKCHIP_CIF is not set
CONFIG_VIDEO_ROCKCHIP_ISP1=m
CONFIG_VIDEO_ROCKCHIP_VDEC=m

#
# Samsung media platform drivers
#

#
# STMicroelectronics media platform drivers
#

#
# Sunxi media platform drivers
#
CONFIG_VIDEO_SUN4I_CSI=m
CONFIG_VIDEO_SUN6I_CSI=m
CONFIG_VIDEO_SUN6I_MIPI_CSI2=m
CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m
CONFIG_VIDEO_SUN8I_DEINTERLACE=m
CONFIG_VIDEO_SUN8I_ROTATE=m
CONFIG_VIDEO_SYNOPSYS_HDMIRX=m
# CONFIG_VIDEO_SYNOPSYS_HDMIRX_LOAD_DEFAULT_EDID is not set
# CONFIG_VIDEO_DW_MIPI_CSI2RX is not set

#
# Texas Instruments drivers
#

#
# Verisilicon media platform drivers
#
# CONFIG_VIDEO_HANTRO is not set

#
# VIA media platform drivers
#

#
# Xilinx media platform drivers
#
# CONFIG_VIDEO_XILINX is not set
CONFIG_UVC_COMMON=m
CONFIG_VIDEO_TVEEPROM=m
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_VIDEOBUF2_DMA_SG=m
# end of Media drivers

#
# Media ancillary drivers
#

#
# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
#
CONFIG_VIDEO_IR_I2C=m
CONFIG_VIDEO_CAMERA_SENSOR=y
CONFIG_VIDEO_APTINA_PLL=m
CONFIG_VIDEO_CCS_PLL=m
# CONFIG_VIDEO_ALVIUM_CSI2 is not set
CONFIG_VIDEO_AR0521=m
# CONFIG_VIDEO_GC0308 is not set
# CONFIG_VIDEO_GC0310 is not set
# CONFIG_VIDEO_GC05A2 is not set
# CONFIG_VIDEO_GC08A3 is not set
# CONFIG_VIDEO_GC2145 is not set
CONFIG_VIDEO_HI556=m
CONFIG_VIDEO_HI846=m
CONFIG_VIDEO_HI847=m
CONFIG_VIDEO_IMX208=m
CONFIG_VIDEO_IMX214=m
CONFIG_VIDEO_IMX219=m
CONFIG_VIDEO_IMX258=m
CONFIG_VIDEO_IMX274=m
# CONFIG_VIDEO_IMX283 is not set
CONFIG_VIDEO_IMX290=m
# CONFIG_VIDEO_IMX296 is not set
CONFIG_VIDEO_IMX319=m
CONFIG_VIDEO_IMX334=m
CONFIG_VIDEO_IMX335=m
CONFIG_VIDEO_IMX355=m
CONFIG_VIDEO_IMX412=m
# CONFIG_VIDEO_IMX415 is not set
CONFIG_VIDEO_MAX9271_LIB=m
CONFIG_VIDEO_MT9M001=m
CONFIG_VIDEO_MT9M111=m
# CONFIG_VIDEO_MT9M114 is not set
CONFIG_VIDEO_MT9P031=m
CONFIG_VIDEO_MT9T112=m
CONFIG_VIDEO_MT9V011=m
CONFIG_VIDEO_MT9V032=m
CONFIG_VIDEO_MT9V111=m
CONFIG_VIDEO_OG01A1B=m
# CONFIG_VIDEO_OG0VE1B is not set
# CONFIG_VIDEO_OV01A10 is not set
CONFIG_VIDEO_OV02A10=m
# CONFIG_VIDEO_OV02E10 is not set
# CONFIG_VIDEO_OV02C10 is not set
CONFIG_VIDEO_OV08D10=m
# CONFIG_VIDEO_OV08X40 is not set
CONFIG_VIDEO_OV13858=m
CONFIG_VIDEO_OV13B10=m
CONFIG_VIDEO_OV2640=m
CONFIG_VIDEO_OV2659=m
CONFIG_VIDEO_OV2680=m
CONFIG_VIDEO_OV2685=m
# CONFIG_VIDEO_OV2735 is not set
CONFIG_VIDEO_OV2740=m
# CONFIG_VIDEO_OV4689 is not set
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_OV5647=m
CONFIG_VIDEO_OV5648=m
CONFIG_VIDEO_OV5670=m
CONFIG_VIDEO_OV5675=m
CONFIG_VIDEO_OV5693=m
CONFIG_VIDEO_OV5695=m
# CONFIG_VIDEO_OV6211 is not set
# CONFIG_VIDEO_OV64A40 is not set
CONFIG_VIDEO_OV7251=m
CONFIG_VIDEO_OV7640=m
CONFIG_VIDEO_OV7670=m
CONFIG_VIDEO_OV772X=m
CONFIG_VIDEO_OV7740=m
CONFIG_VIDEO_OV8856=m
# CONFIG_VIDEO_OV8858 is not set
CONFIG_VIDEO_OV8865=m
CONFIG_VIDEO_OV9282=m
CONFIG_VIDEO_OV9640=m
CONFIG_VIDEO_OV9650=m
CONFIG_VIDEO_OV9734=m
CONFIG_VIDEO_RDACM20=m
CONFIG_VIDEO_RDACM21=m
CONFIG_VIDEO_RJ54N1=m
CONFIG_VIDEO_S5C73M3=m
CONFIG_VIDEO_S5K5BAF=m
CONFIG_VIDEO_S5K6A3=m
# CONFIG_VIDEO_VD55G1 is not set
# CONFIG_VIDEO_VD56G3 is not set
# CONFIG_VIDEO_VGXY61 is not set
CONFIG_VIDEO_CCS=m
CONFIG_VIDEO_ET8EK8=m

#
# Camera ISPs
#
# CONFIG_VIDEO_THP7312 is not set
# end of Camera ISPs

CONFIG_VIDEO_CAMERA_LENS=y
CONFIG_VIDEO_AD5820=m
CONFIG_VIDEO_AK7375=m
CONFIG_VIDEO_DW9714=m
# CONFIG_VIDEO_DW9719 is not set
CONFIG_VIDEO_DW9768=m
CONFIG_VIDEO_DW9807_VCM=m

#
# Flash devices
#
CONFIG_VIDEO_ADP1653=m
CONFIG_VIDEO_LM3560=m
CONFIG_VIDEO_LM3646=m
# end of Flash devices

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_CS3308=m
CONFIG_VIDEO_CS5345=m
CONFIG_VIDEO_CS53L32A=m
CONFIG_VIDEO_MSP3400=m
CONFIG_VIDEO_SONY_BTF_MPX=m
CONFIG_VIDEO_TDA1997X=m
CONFIG_VIDEO_TDA7432=m
CONFIG_VIDEO_TDA9840=m
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
CONFIG_VIDEO_TLV320AIC23B=m
CONFIG_VIDEO_TVAUDIO=m
CONFIG_VIDEO_UDA1342=m
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_WM8739=m
CONFIG_VIDEO_WM8775=m
# end of Audio decoders, processors and mixers

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders

#
# Video decoders
#
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_ADV7183=m
CONFIG_VIDEO_ADV748X=m
CONFIG_VIDEO_ADV7604=m
CONFIG_VIDEO_ADV7604_CEC=y
CONFIG_VIDEO_ADV7842=m
CONFIG_VIDEO_ADV7842_CEC=y
CONFIG_VIDEO_BT819=m
CONFIG_VIDEO_BT856=m
CONFIG_VIDEO_BT866=m
CONFIG_VIDEO_ISL7998X=m
# CONFIG_VIDEO_LT6911UXE is not set
CONFIG_VIDEO_KS0127=m
CONFIG_VIDEO_MAX9286=m
CONFIG_VIDEO_ML86V7667=m
CONFIG_VIDEO_SAA7110=m
CONFIG_VIDEO_SAA711X=m
CONFIG_VIDEO_TC358743=m
CONFIG_VIDEO_TC358743_CEC=y
# CONFIG_VIDEO_TC358746 is not set
CONFIG_VIDEO_TVP514X=m
CONFIG_VIDEO_TVP5150=m
CONFIG_VIDEO_TVP7002=m
CONFIG_VIDEO_TW2804=m
# CONFIG_VIDEO_TW9900 is not set
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=m
CONFIG_VIDEO_TW9910=m
CONFIG_VIDEO_VPX3220=m

#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=m
CONFIG_VIDEO_CX25840=m
# end of Video decoders

#
# Video encoders
#
CONFIG_VIDEO_ADV7170=m
CONFIG_VIDEO_ADV7175=m
CONFIG_VIDEO_ADV7343=m
CONFIG_VIDEO_ADV7393=m
CONFIG_VIDEO_ADV7511=m
CONFIG_VIDEO_ADV7511_CEC=y
CONFIG_VIDEO_AK881X=m
CONFIG_VIDEO_SAA7127=m
CONFIG_VIDEO_SAA7185=m
CONFIG_VIDEO_THS8200=m
# end of Video encoders

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
CONFIG_VIDEO_UPD64083=m
# end of Video improvement chips

#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips

#
# SDR tuner chips
#
# end of SDR tuner chips

#
# Miscellaneous helper chips
#
CONFIG_VIDEO_I2C=m
CONFIG_VIDEO_M52790=m
CONFIG_VIDEO_ST_MIPID02=m
CONFIG_VIDEO_THS7303=m
# end of Miscellaneous helper chips

#
# Video serializers and deserializers
#
# CONFIG_VIDEO_DS90UB913 is not set
# CONFIG_VIDEO_DS90UB953 is not set
# CONFIG_VIDEO_DS90UB960 is not set
# CONFIG_VIDEO_MAX96714 is not set
# CONFIG_VIDEO_MAX96717 is not set
# end of Video serializers and deserializers

#
# Media SPI Adapters
#
CONFIG_VIDEO_GS1662=m
# end of Media SPI Adapters
# end of Media ancillary drivers

#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
CONFIG_SCREEN_INFO=y
CONFIG_VIDEO=y
CONFIG_AUXDISPLAY=y
CONFIG_CHARLCD=m
CONFIG_HD44780_COMMON=m
CONFIG_HD44780=m
CONFIG_LCD2S=m
# CONFIG_PANEL_CHANGE_MESSAGE is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_LINEDISP=m
CONFIG_IMG_ASCII_LCD=m
CONFIG_HT16K33=m
# CONFIG_MAX6959 is not set
# CONFIG_SEG_LED_GPIO is not set
# CONFIG_TM16XX_I2C is not set
# CONFIG_TM16XX_SPI is not set
CONFIG_OPENVFD=m
CONFIG_DRM=y

#
# DRM debugging options
#
# CONFIG_DRM_WERROR is not set
# CONFIG_DRM_DEBUG_MM is not set
# end of DRM debugging options

CONFIG_DRM_MIPI_DBI=m
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_PANIC is not set
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
CONFIG_DRM_CLIENT=y
CONFIG_DRM_CLIENT_LIB=y
CONFIG_DRM_CLIENT_SELECTION=y
CONFIG_DRM_CLIENT_SETUP=y

#
# Supported DRM clients
#
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=300
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
# CONFIG_DRM_CLIENT_LOG is not set
CONFIG_DRM_CLIENT_DEFAULT_FBDEV=y
CONFIG_DRM_CLIENT_DEFAULT="fbdev"
# end of Supported DRM clients

# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
CONFIG_DRM_DISPLAY_DP_AUX_BUS=m
CONFIG_DRM_DISPLAY_HELPER=y
CONFIG_DRM_BRIDGE_CONNECTOR=y
# CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set
# CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set
CONFIG_DRM_DISPLAY_DP_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_AUDIO_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_CEC_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_CEC_NOTIFIER_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER=y
CONFIG_DRM_TTM=m
CONFIG_DRM_EXEC=m
CONFIG_DRM_GPUVM=m
CONFIG_DRM_TTM_HELPER=m
CONFIG_DRM_GEM_DMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=m
CONFIG_DRM_SCHED=m

#
# Drivers for system framebuffers
#
# CONFIG_DRM_EFIDRM is not set
# CONFIG_DRM_SIMPLEDRM is not set
# end of Drivers for system framebuffers

#
# ARM devices
#
CONFIG_DRM_HDLCD=m
CONFIG_DRM_HDLCD_SHOW_UNDERRUN=y
CONFIG_DRM_MALI_DISPLAY=m
CONFIG_DRM_KOMEDA=m
# end of ARM devices

# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
# CONFIG_DRM_XE is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
CONFIG_DRM_ROCKCHIP=m
CONFIG_ROCKCHIP_VOP=y
CONFIG_ROCKCHIP_VOP2=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
# CONFIG_ROCKCHIP_DW_DP is not set
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_HDMI_QP=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI2=y
CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_ROCKCHIP_LVDS=y
CONFIG_ROCKCHIP_RGB=y
CONFIG_ROCKCHIP_RK3066_HDMI=y
# CONFIG_DRM_VMWGFX is not set
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
CONFIG_DRM_SUN4I=y
CONFIG_DRM_SUN6I_DSI=y
CONFIG_DRM_SUN8I_DW_HDMI=y
CONFIG_DRM_SUN8I_MIXER=y
CONFIG_DRM_SUN8I_TCON_TOP=y
CONFIG_DRM_QXL=m
CONFIG_DRM_VIRTIO_GPU=m
CONFIG_DRM_VIRTIO_GPU_KMS=y
CONFIG_DRM_PANEL=y

#
# Display Panels
#
CONFIG_DRM_PANEL_ABT_Y030XX067A=m
CONFIG_DRM_PANEL_ARM_VERSATILE=m
CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set
CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
# CONFIG_DRM_PANEL_BOE_TD4320 is not set
# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
# CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 is not set
CONFIG_DRM_PANEL_EBBG_FT8719=m
CONFIG_DRM_PANEL_ELIDA_KD35T133=m
CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
CONFIG_DRM_PANEL_DSI_CM=m
CONFIG_DRM_PANEL_LVDS=m
# CONFIG_DRM_PANEL_HIMAX_HX8279 is not set
# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set
# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set
# CONFIG_DRM_PANEL_HIMAX_HX83112B is not set
# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set
# CONFIG_DRM_PANEL_HYDIS_HV101HD1 is not set
CONFIG_DRM_PANEL_ILITEK_IL9322=m
CONFIG_DRM_PANEL_ILITEK_ILI9341=m
# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set
CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set
CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set
CONFIG_DRM_PANEL_JDI_LT070ME05000=m
CONFIG_DRM_PANEL_JDI_R63452=m
CONFIG_DRM_PANEL_KHADAS_TS050=m
CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set
CONFIG_DRM_PANEL_LG_LB035Q02=m
CONFIG_DRM_PANEL_LG_LG4573=m
# CONFIG_DRM_PANEL_LG_SW43408 is not set
# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set
CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
CONFIG_DRM_PANEL_NOVATEK_NT35510=m
CONFIG_DRM_PANEL_NOVATEK_NT35560=m
CONFIG_DRM_PANEL_NOVATEK_NT35950=m
# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set
CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set
# CONFIG_DRM_PANEL_NOVATEK_NT37801 is not set
CONFIG_DRM_PANEL_NOVATEK_NT39016=m
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
# CONFIG_DRM_PANEL_RAYDIUM_RM67200 is not set
CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set
# CONFIG_DRM_PANEL_RENESAS_R61307 is not set
# CONFIG_DRM_PANEL_RENESAS_R69328 is not set
CONFIG_DRM_PANEL_RONBO_RB070D30=m
# CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01 is not set
# CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS427AP24 is not set
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA8 is not set
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01 is not set
CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set
CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set
CONFIG_DRM_PANEL_EDP=m
CONFIG_DRM_PANEL_SIMPLE=m
# CONFIG_DRM_PANEL_SUMMIT is not set
# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set
CONFIG_DRM_PANEL_TDO_TL070WSH30=m
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
CONFIG_DRM_PANEL_TPO_TPG110=m
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
# CONFIG_DRM_PANEL_VISIONOX_G2647FB105 is not set
# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set
CONFIG_DRM_PANEL_VISIONOX_RM69299=m
# CONFIG_DRM_PANEL_VISIONOX_RM692E5 is not set
# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set
CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y
CONFIG_DRM_AUX_BRIDGE=m

#
# Display Interface Bridges
#
# CONFIG_DRM_CHIPONE_ICN6211 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
CONFIG_DRM_DISPLAY_CONNECTOR=y
# CONFIG_DRM_I2C_NXP_TDA998X is not set
CONFIG_DRM_INNO_HDMI=m
# CONFIG_DRM_ITE_IT6263 is not set
# CONFIG_DRM_ITE_IT6505 is not set
# CONFIG_DRM_LONTIUM_LT8912B is not set
# CONFIG_DRM_LONTIUM_LT9211 is not set
# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LONTIUM_LT9611UXC is not set
# CONFIG_DRM_ITE_IT66121 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_SAMSUNG_DSIM is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
CONFIG_DRM_SIMPLE_BRIDGE=m
# CONFIG_DRM_SOLOMON_SSD2825 is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_DLPC3433 is not set
# CONFIG_DRM_TI_TDP158 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI83 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_WAVESHARE_BRIDGE is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
CONFIG_DRM_ANALOGIX_DP=m
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=y
CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
CONFIG_DRM_DW_HDMI_CEC=m
CONFIG_DRM_DW_HDMI_QP=m
# CONFIG_DRM_DW_HDMI_QP_CEC is not set
CONFIG_DRM_DW_MIPI_DSI=y
CONFIG_DRM_DW_MIPI_DSI2=m
# end of Display Interface Bridges

CONFIG_DRM_ETNAVIV=m
CONFIG_DRM_ETNAVIV_THERMAL=y
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
# CONFIG_DRM_LOGICVC is not set
CONFIG_DRM_MESON=y
CONFIG_DRM_MESON_DW_HDMI=y
CONFIG_DRM_MESON_DW_MIPI_DSI=y
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_BOCHS is not set
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_GM12U320 is not set
# CONFIG_DRM_PANEL_MIPI_DBI is not set
# CONFIG_DRM_PIXPAPER is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9163 is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_SHARP_MEMORY is not set
# CONFIG_DRM_PL111 is not set
CONFIG_DRM_LIMA=m
CONFIG_DRM_PANFROST=m
CONFIG_DRM_PANTHOR=m
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_GUD is not set
# CONFIG_DRM_ST7571_I2C is not set
# CONFIG_DRM_ST7586 is not set
# CONFIG_DRM_ST7735R is not set
CONFIG_DRM_SSD130X=m
CONFIG_DRM_SSD130X_I2C=m
CONFIG_DRM_SSD130X_SPI=m
# CONFIG_DRM_POWERVR is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y

#
# Frame buffer Devices
#
CONFIG_FB=y
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_UVESA is not set
CONFIG_FB_EFI=y
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
CONFIG_FB_SIMPLE=y
# CONFIG_FB_SSD1307 is not set
# CONFIG_FB_SM712 is not set
CONFIG_FB_CORE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB_DEVICE=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYSMEM_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_DMAMEM_HELPERS=y
CONFIG_FB_DMAMEM_HELPERS_DEFERRED=y
CONFIG_FB_IOMEM_FOPS=y
CONFIG_FB_IOMEM_HELPERS=y
CONFIG_FB_SYSMEM_HELPERS=y
CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
CONFIG_FB_BACKLIGHT=y
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=m
CONFIG_LCD_L4F00242T03=m
CONFIG_LCD_LMS283GF05=m
CONFIG_LCD_LTV350QV=m
CONFIG_LCD_ILI922X=m
CONFIG_LCD_ILI9320=m
CONFIG_LCD_TDO24M=m
CONFIG_LCD_VGG2432A4=m
CONFIG_LCD_PLATFORM=m
CONFIG_LCD_AMS369FG06=m
CONFIG_LCD_LMS501KF03=m
CONFIG_LCD_HX8357=m
CONFIG_LCD_OTM3225A=m
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_KTD253=m
# CONFIG_BACKLIGHT_KTD2801 is not set
# CONFIG_BACKLIGHT_KTZ8866 is not set
CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_QCOM_WLED=m
CONFIG_BACKLIGHT_ADP8860=m
CONFIG_BACKLIGHT_ADP8870=m
# CONFIG_BACKLIGHT_LM3509 is not set
CONFIG_BACKLIGHT_LM3630A=m
CONFIG_BACKLIGHT_LM3639=m
CONFIG_BACKLIGHT_LP855X=m
# CONFIG_BACKLIGHT_MP3309C is not set
CONFIG_BACKLIGHT_GPIO=y
CONFIG_BACKLIGHT_LV5207LP=m
CONFIG_BACKLIGHT_BD6107=m
CONFIG_BACKLIGHT_ARCXCNN=m
CONFIG_BACKLIGHT_LED=y
# end of Backlight & LCD device support

CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
# end of Console display driver support

CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
# CONFIG_TRACE_GPU_MEM is not set
# end of Graphics support

CONFIG_DRM_ACCEL=y
CONFIG_DRM_ACCEL_QAIC=m
CONFIG_DRM_ACCEL_ROCKET=m
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=m
CONFIG_SND_RAWMIDI=m
CONFIG_SND_UMP=m
CONFIG_SND_UMP_LEGACY_RAWMIDI=y
CONFIG_SND_COMPRESS_OFFLOAD=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_OSSEMUL is not set
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
# CONFIG_SND_VERBOSE_PROCFS is not set
CONFIG_SND_CTL_FAST_LOOKUP=y
# CONFIG_SND_DEBUG is not set
# CONFIG_SND_CTL_INPUT_VALIDATION is not set
# CONFIG_SND_UTIMER is not set
CONFIG_SND_VMASTER=y
# CONFIG_SND_SEQUENCER is not set
CONFIG_SND_MPU401_UART=m
CONFIG_SND_AC97_CODEC=m
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
# CONFIG_SND_PCMTEST is not set
CONFIG_SND_MTPAV=m
CONFIG_SND_SERIAL_U16550=m
CONFIG_SND_SERIAL_GENERIC=m
CONFIG_SND_MPU401=m
# CONFIG_SND_AC97_POWER_SAVE is not set
CONFIG_SND_PCI=y
# CONFIG_SND_AD1889 is not set
# CONFIG_SND_ALS300 is not set
# CONFIG_SND_ALI5451 is not set
# CONFIG_SND_ATIIXP is not set
# CONFIG_SND_ATIIXP_MODEM is not set
# CONFIG_SND_AU8810 is not set
# CONFIG_SND_AU8820 is not set
# CONFIG_SND_AU8830 is not set
# CONFIG_SND_AW2 is not set
# CONFIG_SND_AZT3328 is not set
# CONFIG_SND_BT87X is not set
# CONFIG_SND_CA0106 is not set
# CONFIG_SND_CMIPCI is not set
# CONFIG_SND_OXYGEN is not set
# CONFIG_SND_CS4281 is not set
# CONFIG_SND_CS46XX is not set
# CONFIG_SND_CTXFI is not set
# CONFIG_SND_DARLA20 is not set
# CONFIG_SND_GINA20 is not set
# CONFIG_SND_LAYLA20 is not set
# CONFIG_SND_DARLA24 is not set
# CONFIG_SND_GINA24 is not set
# CONFIG_SND_LAYLA24 is not set
# CONFIG_SND_MONA is not set
# CONFIG_SND_MIA is not set
# CONFIG_SND_ECHO3G is not set
# CONFIG_SND_INDIGO is not set
# CONFIG_SND_INDIGOIO is not set
# CONFIG_SND_INDIGODJ is not set
# CONFIG_SND_INDIGOIOX is not set
# CONFIG_SND_INDIGODJX is not set
# CONFIG_SND_EMU10K1 is not set
# CONFIG_SND_EMU10K1X is not set
# CONFIG_SND_ENS1370 is not set
# CONFIG_SND_ENS1371 is not set
# CONFIG_SND_ES1938 is not set
# CONFIG_SND_ES1968 is not set
# CONFIG_SND_FM801 is not set
# CONFIG_SND_HDSP is not set
# CONFIG_SND_HDSPM is not set
# CONFIG_SND_ICE1712 is not set
# CONFIG_SND_ICE1724 is not set
# CONFIG_SND_INTEL8X0 is not set
# CONFIG_SND_INTEL8X0M is not set
# CONFIG_SND_KORG1212 is not set
# CONFIG_SND_LOLA is not set
# CONFIG_SND_LX6464ES is not set
# CONFIG_SND_MAESTRO3 is not set
# CONFIG_SND_MIXART is not set
# CONFIG_SND_NM256 is not set
# CONFIG_SND_PCXHR is not set
# CONFIG_SND_RIPTIDE is not set
# CONFIG_SND_RME32 is not set
# CONFIG_SND_RME96 is not set
# CONFIG_SND_RME9652 is not set
# CONFIG_SND_SE6X is not set
# CONFIG_SND_SONICVIBES is not set
# CONFIG_SND_TRIDENT is not set
# CONFIG_SND_VIA82XX is not set
# CONFIG_SND_VIA82XX_MODEM is not set
# CONFIG_SND_VIRTUOSO is not set
# CONFIG_SND_VX222 is not set
# CONFIG_SND_YMFPCI is not set

#
# HD-Audio
#
CONFIG_SND_HDA=m
# CONFIG_SND_HDA_HWDEP is not set
# CONFIG_SND_HDA_RECONFIG is not set
# CONFIG_SND_HDA_INPUT_BEEP is not set
# CONFIG_SND_HDA_PATCH_LOADER is not set
CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
CONFIG_SND_HDA_PREALLOC_SIZE=2048
# CONFIG_SND_HDA_INTEL is not set
# CONFIG_SND_HDA_ACPI is not set
# CONFIG_SND_HDA_CODEC_ANALOG is not set
# CONFIG_SND_HDA_CODEC_SIGMATEL is not set
# CONFIG_SND_HDA_CODEC_VIA is not set
# CONFIG_SND_HDA_CODEC_CONEXANT is not set
# CONFIG_SND_HDA_CODEC_SENARYTECH is not set
# CONFIG_SND_HDA_CODEC_CA0110 is not set
# CONFIG_SND_HDA_CODEC_CA0132 is not set
# CONFIG_SND_HDA_CODEC_CMEDIA is not set
# CONFIG_SND_HDA_CODEC_CM9825 is not set
# CONFIG_SND_HDA_CODEC_SI3054 is not set
# CONFIG_SND_HDA_GENERIC is not set
# CONFIG_SND_HDA_CODEC_REALTEK is not set
# CONFIG_SND_HDA_CODEC_CIRRUS is not set
CONFIG_SND_HDA_CODEC_HDMI=m
CONFIG_SND_HDA_CODEC_HDMI_GENERIC=m
CONFIG_SND_HDA_CODEC_HDMI_SIMPLE=m
CONFIG_SND_HDA_CODEC_HDMI_INTEL=m
# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
CONFIG_SND_HDA_CODEC_HDMI_ATI=m
CONFIG_SND_HDA_CODEC_HDMI_NVIDIA=m
CONFIG_SND_HDA_CODEC_HDMI_NVIDIA_MCP=m
CONFIG_SND_HDA_CODEC_HDMI_TEGRA=m
# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
# CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set
# CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set
# CONFIG_SND_HDA_SCODEC_TAS2781_SPI is not set
CONFIG_SND_HDA_CORE=m
CONFIG_SND_HDA_EXT_CORE=m
# end of HD-Audio

# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
# CONFIG_SND_USB_AUDIO_MIDI_V2 is not set
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
CONFIG_SND_BCD2000=m
CONFIG_SND_USB_LINE6=m
CONFIG_SND_USB_POD=m
CONFIG_SND_USB_PODHD=m
CONFIG_SND_USB_TONEPORT=m
CONFIG_SND_USB_VARIAX=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
CONFIG_SND_SOC_COMPRESS=y
# CONFIG_SND_SOC_USB is not set

#
# Analog Devices
#
# CONFIG_SND_SOC_ADI_AXI_I2S is not set
# CONFIG_SND_SOC_ADI_AXI_SPDIF is not set
# end of Analog Devices

#
# AMD
#
# CONFIG_SND_SOC_AMD_ACP is not set
# CONFIG_SND_AMD_ACP_CONFIG is not set
# end of AMD

#
# Apple
#
# end of Apple

#
# Atmel
#
# CONFIG_SND_SOC_MIKROE_PROTO is not set
# end of Atmel

#
# Au1x
#
# end of Au1x

#
# Broadcom
#
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
# end of Broadcom

#
# Cirrus Logic
#
# end of Cirrus Logic

#
# DesignWare
#
CONFIG_SND_DESIGNWARE_I2S=m
# CONFIG_SND_DESIGNWARE_PCM is not set
# end of DesignWare

#
# Freescale
#

#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
# CONFIG_SND_SOC_FSL_SAI is not set
# CONFIG_SND_SOC_FSL_AUDMIX is not set
# CONFIG_SND_SOC_FSL_SSI is not set
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
# CONFIG_SND_SOC_FSL_MICFIL is not set
# CONFIG_SND_SOC_FSL_XCVR is not set
# CONFIG_SND_SOC_FSL_RPMSG is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of Freescale

#
# Google
#
# CONFIG_SND_SOC_CHV3_I2S is not set
# end of Google

#
# Hisilicon
#
# CONFIG_SND_I2S_HI6210_I2S is not set
# end of Hisilicon

#
# JZ4740
#
# end of JZ4740

#
# Kirkwood
#
# end of Kirkwood

#
# Loongson
#
# end of Loongson

#
# Intel
#
# end of Intel

#
# Mediatek
#
# CONFIG_SND_SOC_MTK_BTCVSD is not set
# end of Mediatek

#
# Amlogic
#
CONFIG_SND_MESON_AIU=m
CONFIG_SND_MESON_AXG_FIFO=m
CONFIG_SND_MESON_AXG_FRDDR=m
CONFIG_SND_MESON_AXG_TODDR=m
CONFIG_SND_MESON_AXG_TDM_FORMATTER=m
CONFIG_SND_MESON_AXG_TDM_INTERFACE=m
CONFIG_SND_MESON_AXG_TDMIN=m
CONFIG_SND_MESON_AXG_TDMOUT=m
CONFIG_SND_MESON_AXG_SOUND_CARD=m
CONFIG_SND_MESON_AXG_SPDIFOUT=m
CONFIG_SND_MESON_AXG_SPDIFIN=m
CONFIG_SND_MESON_AXG_PDM=m
CONFIG_SND_MESON_CARD_UTILS=m
CONFIG_SND_MESON_CODEC_GLUE=m
CONFIG_SND_MESON_GX_SOUND_CARD=m
CONFIG_SND_MESON_G12A_TOACODEC=m
CONFIG_SND_MESON_G12A_TOHDMITX=m
CONFIG_SND_SOC_MESON_T9015=m
# end of Amlogic

#
# PXA
#
# end of PXA

#
# Rockchip
#
CONFIG_SND_SOC_ROCKCHIP_I2S=m
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
CONFIG_SND_SOC_ROCKCHIP_PDM=m
CONFIG_SND_SOC_ROCKCHIP_SAI=m
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
CONFIG_SND_SOC_ROCKCHIP_RT5645=m
CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m
CONFIG_SND_SOC_RK3399_GRU_SOUND=m
# end of Rockchip

#
# SoundWire (SDCA)
#
CONFIG_SND_SOC_SDCA_OPTIONAL=y
# end of SoundWire (SDCA)

#
# ST SPEAr
#
# end of ST SPEAr

#
# Spreadtrum
#
# end of Spreadtrum

#
# STMicroelectronics STM32
#
# end of STMicroelectronics STM32

#
# Allwinner
#
CONFIG_SND_SUN4I_CODEC=m
CONFIG_SND_SUN8I_CODEC=m
CONFIG_SND_SUN8I_CODEC_ANALOG=m
CONFIG_SND_SUN50I_CODEC_ANALOG=m
CONFIG_SND_SUN4I_I2S=m
CONFIG_SND_SUN4I_SPDIF=m
CONFIG_SND_SUN50I_DMIC=m
CONFIG_SND_SUN8I_ADDA_PR_REGMAP=m
# end of Allwinner

#
# Tegra
#
# end of Tegra

#
# Xilinx
#
# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# end of Xilinx

#
# Xtensa
#
# CONFIG_SND_SOC_XTFPGA_I2S is not set
# end of Xtensa

# CONFIG_SND_SOC_SOF_TOPLEVEL is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
CONFIG_SND_SOC_WM_ADSP=m
CONFIG_SND_SOC_AC97_CODEC=m
CONFIG_SND_SOC_ADAU_UTILS=m
CONFIG_SND_SOC_ADAU1372=m
CONFIG_SND_SOC_ADAU1372_I2C=m
CONFIG_SND_SOC_ADAU1372_SPI=m
# CONFIG_SND_SOC_ADAU1373 is not set
CONFIG_SND_SOC_ADAU1701=m
CONFIG_SND_SOC_ADAU17X1=m
CONFIG_SND_SOC_ADAU1761=m
CONFIG_SND_SOC_ADAU1761_I2C=m
CONFIG_SND_SOC_ADAU1761_SPI=m
CONFIG_SND_SOC_ADAU7002=m
CONFIG_SND_SOC_ADAU7118=m
CONFIG_SND_SOC_ADAU7118_HW=m
CONFIG_SND_SOC_ADAU7118_I2C=m
CONFIG_SND_SOC_AK4104=m
CONFIG_SND_SOC_AK4118=m
CONFIG_SND_SOC_AK4375=m
CONFIG_SND_SOC_AK4458=m
CONFIG_SND_SOC_AK4554=m
CONFIG_SND_SOC_AK4613=m
CONFIG_SND_SOC_AK4619=m
CONFIG_SND_SOC_AK4642=m
CONFIG_SND_SOC_AK5386=m
CONFIG_SND_SOC_AK5558=m
CONFIG_SND_SOC_ALC5623=m
CONFIG_SND_SOC_AUDIO_IIO_AUX=m
CONFIG_SND_SOC_AW8738=m
CONFIG_SND_SOC_AW88395_LIB=m
CONFIG_SND_SOC_AW88395=m
# CONFIG_SND_SOC_AW88166 is not set
CONFIG_SND_SOC_AW88261=m
# CONFIG_SND_SOC_AW88081 is not set
CONFIG_SND_SOC_AW87390=m
CONFIG_SND_SOC_AW88399=m
CONFIG_SND_SOC_BD28623=m
CONFIG_SND_SOC_BT_SCO=m
CONFIG_SND_SOC_CHV3_CODEC=m
CONFIG_SND_SOC_CS_AMP_LIB=m
CONFIG_SND_SOC_CS35L32=m
CONFIG_SND_SOC_CS35L33=m
CONFIG_SND_SOC_CS35L34=m
CONFIG_SND_SOC_CS35L35=m
CONFIG_SND_SOC_CS35L36=m
CONFIG_SND_SOC_CS35L41_LIB=m
CONFIG_SND_SOC_CS35L41=m
CONFIG_SND_SOC_CS35L41_SPI=m
CONFIG_SND_SOC_CS35L41_I2C=m
CONFIG_SND_SOC_CS35L45=m
CONFIG_SND_SOC_CS35L45_SPI=m
CONFIG_SND_SOC_CS35L45_I2C=m
CONFIG_SND_SOC_CS35L56=m
CONFIG_SND_SOC_CS35L56_SHARED=m
CONFIG_SND_SOC_CS35L56_I2C=m
CONFIG_SND_SOC_CS35L56_SPI=m
CONFIG_SND_SOC_CS42L42_CORE=m
CONFIG_SND_SOC_CS42L42=m
CONFIG_SND_SOC_CS42L51=m
CONFIG_SND_SOC_CS42L51_I2C=m
CONFIG_SND_SOC_CS42L52=m
CONFIG_SND_SOC_CS42L56=m
CONFIG_SND_SOC_CS42L73=m
CONFIG_SND_SOC_CS42L83=m
# CONFIG_SND_SOC_CS42L84 is not set
CONFIG_SND_SOC_CS4234=m
CONFIG_SND_SOC_CS4265=m
CONFIG_SND_SOC_CS4270=m
CONFIG_SND_SOC_CS4271=m
CONFIG_SND_SOC_CS4271_I2C=m
CONFIG_SND_SOC_CS4271_SPI=m
CONFIG_SND_SOC_CS42XX8=m
CONFIG_SND_SOC_CS42XX8_I2C=m
CONFIG_SND_SOC_CS43130=m
CONFIG_SND_SOC_CS4341=m
CONFIG_SND_SOC_CS4349=m
# CONFIG_SND_SOC_CS48L32 is not set
CONFIG_SND_SOC_CS53L30=m
CONFIG_SND_SOC_CS530X=m
CONFIG_SND_SOC_CS530X_I2C=m
CONFIG_SND_SOC_CX2072X=m
CONFIG_SND_SOC_DA7213=m
CONFIG_SND_SOC_DA7219=m
CONFIG_SND_SOC_DMIC=m
CONFIG_SND_SOC_HDMI_CODEC=y
CONFIG_SND_SOC_ES7134=m
CONFIG_SND_SOC_ES7241=m
CONFIG_SND_SOC_ES8311=m
CONFIG_SND_SOC_ES8316=m
CONFIG_SND_SOC_ES8323=m
CONFIG_SND_SOC_ES8326=m
CONFIG_SND_SOC_ES8328=m
CONFIG_SND_SOC_ES8328_I2C=m
CONFIG_SND_SOC_ES8328_SPI=m
# CONFIG_SND_SOC_ES8375 is not set
# CONFIG_SND_SOC_ES8389 is not set
# CONFIG_SND_SOC_FS210X is not set
CONFIG_SND_SOC_GTM601=m
CONFIG_SND_SOC_HDA=m
CONFIG_SND_SOC_ICS43432=m
CONFIG_SND_SOC_IDT821034=m
CONFIG_SND_SOC_INNO_RK3036=m
CONFIG_SND_SOC_MAX98088=m
CONFIG_SND_SOC_MAX98090=m
CONFIG_SND_SOC_MAX98357A=m
CONFIG_SND_SOC_MAX98504=m
CONFIG_SND_SOC_MAX9867=m
CONFIG_SND_SOC_MAX98927=m
CONFIG_SND_SOC_MAX98520=m
CONFIG_SND_SOC_MAX98373=m
CONFIG_SND_SOC_MAX98373_I2C=m
CONFIG_SND_SOC_MAX98388=m
CONFIG_SND_SOC_MAX98390=m
CONFIG_SND_SOC_MAX98396=m
CONFIG_SND_SOC_MAX9860=m
CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
CONFIG_SND_SOC_PCM1681=m
# CONFIG_SND_SOC_PCM1754 is not set
CONFIG_SND_SOC_PCM1789=m
CONFIG_SND_SOC_PCM1789_I2C=m
CONFIG_SND_SOC_PCM179X=m
CONFIG_SND_SOC_PCM179X_I2C=m
CONFIG_SND_SOC_PCM179X_SPI=m
CONFIG_SND_SOC_PCM186X=m
CONFIG_SND_SOC_PCM186X_I2C=m
CONFIG_SND_SOC_PCM186X_SPI=m
CONFIG_SND_SOC_PCM3060=m
CONFIG_SND_SOC_PCM3060_I2C=m
CONFIG_SND_SOC_PCM3060_SPI=m
CONFIG_SND_SOC_PCM3168A=m
CONFIG_SND_SOC_PCM3168A_I2C=m
CONFIG_SND_SOC_PCM3168A_SPI=m
CONFIG_SND_SOC_PCM5102A=m
CONFIG_SND_SOC_PCM512x=m
CONFIG_SND_SOC_PCM512x_I2C=m
CONFIG_SND_SOC_PCM512x_SPI=m
CONFIG_SND_SOC_PCM6240=m
CONFIG_SND_SOC_PEB2466=m
CONFIG_SND_SOC_RK3308=m
CONFIG_SND_SOC_RK3328=m
CONFIG_SND_SOC_RK817=m
CONFIG_SND_SOC_RL6231=m
CONFIG_SND_SOC_RT5514=m
CONFIG_SND_SOC_RT5514_SPI=m
CONFIG_SND_SOC_RT5616=m
CONFIG_SND_SOC_RT5631=m
CONFIG_SND_SOC_RT5640=m
CONFIG_SND_SOC_RT5645=m
CONFIG_SND_SOC_RT5659=m
CONFIG_SND_SOC_RT9120=m
# CONFIG_SND_SOC_RT9123 is not set
# CONFIG_SND_SOC_RT9123P is not set
# CONFIG_SND_SOC_RTQ9124 is not set
CONFIG_SND_SOC_RTQ9128=m
CONFIG_SND_SOC_SGTL5000=m
CONFIG_SND_SOC_SIGMADSP=m
CONFIG_SND_SOC_SIGMADSP_I2C=m
CONFIG_SND_SOC_SIGMADSP_REGMAP=m
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
CONFIG_SND_SOC_SIMPLE_MUX=m
CONFIG_SND_SOC_SMA1303=m
# CONFIG_SND_SOC_SMA1307 is not set
CONFIG_SND_SOC_SPDIF=m
CONFIG_SND_SOC_SRC4XXX_I2C=m
CONFIG_SND_SOC_SRC4XXX=m
CONFIG_SND_SOC_SSM2305=m
CONFIG_SND_SOC_SSM2518=m
CONFIG_SND_SOC_SSM2602=m
CONFIG_SND_SOC_SSM2602_SPI=m
CONFIG_SND_SOC_SSM2602_I2C=m
CONFIG_SND_SOC_SSM3515=m
CONFIG_SND_SOC_SSM4567=m
CONFIG_SND_SOC_STA32X=m
CONFIG_SND_SOC_STA350=m
CONFIG_SND_SOC_STI_SAS=m
CONFIG_SND_SOC_TAS2552=m
CONFIG_SND_SOC_TAS2562=m
CONFIG_SND_SOC_TAS2764=m
CONFIG_SND_SOC_TAS2770=m
CONFIG_SND_SOC_TAS2780=m
CONFIG_SND_SOC_TAS2781_COMLIB=m
CONFIG_SND_SOC_TAS2781_COMLIB_I2C=m
CONFIG_SND_SOC_TAS2781_FMWLIB=m
CONFIG_SND_SOC_TAS2781_I2C=m
CONFIG_SND_SOC_TAS5086=m
CONFIG_SND_SOC_TAS571X=m
CONFIG_SND_SOC_TAS5720=m
CONFIG_SND_SOC_TAS5805M=m
CONFIG_SND_SOC_TAS6424=m
CONFIG_SND_SOC_TDA7419=m
CONFIG_SND_SOC_TFA9879=m
CONFIG_SND_SOC_TFA989X=m
CONFIG_SND_SOC_TLV320ADC3XXX=m
CONFIG_SND_SOC_TLV320AIC23=m
CONFIG_SND_SOC_TLV320AIC23_I2C=m
CONFIG_SND_SOC_TLV320AIC23_SPI=m
CONFIG_SND_SOC_TLV320AIC31XX=m
CONFIG_SND_SOC_TLV320AIC32X4=m
CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
CONFIG_SND_SOC_TLV320AIC3X=m
CONFIG_SND_SOC_TLV320AIC3X_I2C=m
CONFIG_SND_SOC_TLV320AIC3X_SPI=m
CONFIG_SND_SOC_TLV320ADCX140=m
CONFIG_SND_SOC_TS3A227E=m
CONFIG_SND_SOC_TSCS42XX=m
CONFIG_SND_SOC_TSCS454=m
CONFIG_SND_SOC_UDA1334=m
# CONFIG_SND_SOC_UDA1342 is not set
CONFIG_SND_SOC_WM8510=m
CONFIG_SND_SOC_WM8523=m
CONFIG_SND_SOC_WM8524=m
CONFIG_SND_SOC_WM8580=m
CONFIG_SND_SOC_WM8711=m
CONFIG_SND_SOC_WM8728=m
CONFIG_SND_SOC_WM8731=m
CONFIG_SND_SOC_WM8731_I2C=m
CONFIG_SND_SOC_WM8731_SPI=m
CONFIG_SND_SOC_WM8737=m
CONFIG_SND_SOC_WM8741=m
CONFIG_SND_SOC_WM8750=m
CONFIG_SND_SOC_WM8753=m
CONFIG_SND_SOC_WM8770=m
CONFIG_SND_SOC_WM8776=m
CONFIG_SND_SOC_WM8782=m
CONFIG_SND_SOC_WM8804=m
CONFIG_SND_SOC_WM8804_I2C=m
CONFIG_SND_SOC_WM8804_SPI=m
CONFIG_SND_SOC_WM8903=m
CONFIG_SND_SOC_WM8904=m
CONFIG_SND_SOC_WM8940=m
CONFIG_SND_SOC_WM8960=m
CONFIG_SND_SOC_WM8961=m
CONFIG_SND_SOC_WM8962=m
CONFIG_SND_SOC_WM8974=m
CONFIG_SND_SOC_WM8978=m
CONFIG_SND_SOC_WM8985=m
CONFIG_SND_SOC_ZL38060=m
CONFIG_SND_SOC_MAX9759=m
CONFIG_SND_SOC_MT6351=m
CONFIG_SND_SOC_MT6357=m
CONFIG_SND_SOC_MT6358=m
CONFIG_SND_SOC_MT6660=m
CONFIG_SND_SOC_NAU8315=m
CONFIG_SND_SOC_NAU8325=m
CONFIG_SND_SOC_NAU8540=m
CONFIG_SND_SOC_NAU8810=m
CONFIG_SND_SOC_NAU8821=m
CONFIG_SND_SOC_NAU8822=m
CONFIG_SND_SOC_NAU8824=m
# CONFIG_SND_SOC_NTP8918 is not set
# CONFIG_SND_SOC_NTP8835 is not set
CONFIG_SND_SOC_TPA6130A2=m
CONFIG_SND_SOC_LPASS_MACRO_COMMON=m
CONFIG_SND_SOC_LPASS_WSA_MACRO=m
CONFIG_SND_SOC_LPASS_VA_MACRO=m
CONFIG_SND_SOC_LPASS_RX_MACRO=m
CONFIG_SND_SOC_LPASS_TX_MACRO=m
# end of CODEC drivers

#
# Generic drivers
#
CONFIG_SND_SIMPLE_CARD_UTILS=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD2=m
CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
# CONFIG_SND_TEST_COMPONENT is not set
# end of Generic drivers

CONFIG_SND_VIRTIO=m
CONFIG_AC97_BUS=y
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=m
CONFIG_HID_GENERIC=y
# CONFIG_HID_HAPTIC is not set

#
# Special HID drivers
#
CONFIG_HID_A4TECH=m
CONFIG_HID_ACCUTOUCH=m
CONFIG_HID_ACRUX=m
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=m
CONFIG_HID_APPLEIR=m
CONFIG_HID_ASUS=m
CONFIG_HID_AUREAL=m
CONFIG_HID_BELKIN=m
CONFIG_HID_BETOP_FF=m
CONFIG_HID_BIGBEN_FF=m
CONFIG_HID_CHERRY=m
CONFIG_HID_CHICONY=m
CONFIG_HID_CORSAIR=m
CONFIG_HID_COUGAR=m
CONFIG_HID_MACALLY=m
CONFIG_HID_PRODIKEYS=m
CONFIG_HID_CMEDIA=m
CONFIG_HID_CP2112=m
CONFIG_HID_CREATIVE_SB0540=m
CONFIG_HID_CYPRESS=m
CONFIG_HID_DRAGONRISE=m
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=m
CONFIG_HID_ELAN=m
CONFIG_HID_ELECOM=m
CONFIG_HID_ELO=m
CONFIG_HID_EVISION=m
CONFIG_HID_EZKEY=m
CONFIG_HID_FT260=m
CONFIG_HID_GEMBIRD=m
CONFIG_HID_GFRM=m
CONFIG_HID_GLORIOUS=m
CONFIG_HID_HOLTEK=m
CONFIG_HOLTEK_FF=y
CONFIG_HID_VIVALDI_COMMON=m
# CONFIG_HID_GOODIX_SPI is not set
CONFIG_HID_GOOGLE_STADIA_FF=m
CONFIG_HID_VIVALDI=m
CONFIG_HID_GT683R=m
CONFIG_HID_KEYTOUCH=m
CONFIG_HID_KYE=m
# CONFIG_HID_KYSONA is not set
CONFIG_HID_UCLOGIC=m
CONFIG_HID_WALTOP=m
CONFIG_HID_VIEWSONIC=m
CONFIG_HID_VRC2=m
CONFIG_HID_XIAOMI=m
CONFIG_HID_GYRATION=m
CONFIG_HID_ICADE=m
CONFIG_HID_ITE=m
CONFIG_HID_JABRA=m
CONFIG_HID_TWINHAN=m
CONFIG_HID_KENSINGTON=m
CONFIG_HID_LCPOWER=m
CONFIG_HID_LED=m
CONFIG_HID_LENOVO=m
CONFIG_HID_LETSKETCH=m
CONFIG_HID_LOGITECH=m
CONFIG_HID_LOGITECH_DJ=m
CONFIG_HID_LOGITECH_HIDPP=m
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
CONFIG_HID_MAGICMOUSE=m
CONFIG_HID_MALTRON=m
CONFIG_HID_MAYFLASH=m
CONFIG_HID_MEGAWORLD_FF=m
CONFIG_HID_REDRAGON=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
CONFIG_HID_MULTITOUCH=m
CONFIG_HID_NINTENDO=m
CONFIG_NINTENDO_FF=y
CONFIG_HID_NTI=m
CONFIG_HID_NTRIG=m
CONFIG_HID_NVIDIA_SHIELD=m
# CONFIG_NVIDIA_SHIELD_FF is not set
CONFIG_HID_ORTEK=m
CONFIG_HID_PANTHERLORD=m
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PENMOUNT=m
CONFIG_HID_PETALYNX=m
CONFIG_HID_PICOLCD=m
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
CONFIG_HID_PICOLCD_LCD=y
CONFIG_HID_PICOLCD_LEDS=y
CONFIG_HID_PICOLCD_CIR=y
CONFIG_HID_PLANTRONICS=m
CONFIG_HID_PLAYSTATION=m
CONFIG_PLAYSTATION_FF=y
CONFIG_HID_PXRC=m
CONFIG_HID_RAZER=m
CONFIG_HID_PRIMAX=m
CONFIG_HID_RETRODE=m
CONFIG_HID_ROCCAT=m
CONFIG_HID_SAITEK=m
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SEMITEK=m
CONFIG_HID_SIGMAMICRO=m
CONFIG_HID_SONY=m
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=m
CONFIG_HID_STEAM=m
# CONFIG_STEAM_FF is not set
CONFIG_HID_STEELSERIES=m
CONFIG_HID_SUNPLUS=m
CONFIG_HID_RMI=m
CONFIG_HID_GREENASIA=m
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=m
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TIVO=m
CONFIG_HID_TOPSEED=m
CONFIG_HID_TOPRE=m
CONFIG_HID_THINGM=m
CONFIG_HID_THRUSTMASTER=m
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_UDRAW_PS3=m
CONFIG_HID_U2FZERO=m
CONFIG_HID_UNIVERSAL_PIDFF=m
CONFIG_HID_WACOM=m
CONFIG_HID_WIIMOTE=m
# CONFIG_HID_WINWING is not set
CONFIG_HID_XINMO=m
CONFIG_HID_ZEROPLUS=m
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=m
CONFIG_HID_SENSOR_HUB=m
CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
CONFIG_HID_ALPS=m
CONFIG_HID_MCP2200=m
CONFIG_HID_MCP2221=m
# end of Special HID drivers

#
# HID-BPF support
#
# end of HID-BPF support

CONFIG_I2C_HID=y
CONFIG_I2C_HID_ACPI=m
CONFIG_I2C_HID_OF=m
CONFIG_I2C_HID_OF_ELAN=m
CONFIG_I2C_HID_OF_GOODIX=m
CONFIG_I2C_HID_CORE=m

#
# USB HID support
#
CONFIG_USB_HID=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
# end of USB HID support

CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_LED_TRIG=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_CONN_GPIO=m
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
# CONFIG_USB_PCI_AMD is not set
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
CONFIG_USB_OTG_FSM=m
CONFIG_USB_LEDS_TRIGGER_USBPORT=m
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1
CONFIG_USB_MON=y

#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=m
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_XHCI_PCI_RENESAS=m
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_XHCI_SUNXI=m
# CONFIG_USB_XHCI_SIDEBAND is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_EHCI_FSL=m
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OXU210HP_HCD=m
CONFIG_USB_ISP116X_HCD=m
CONFIG_USB_MAX3421_HCD=m
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_OHCI_HCD_PCI=m
CONFIG_USB_OHCI_HCD_PLATFORM=m
CONFIG_USB_UHCI_HCD=m
CONFIG_USB_SL811_HCD=m
CONFIG_USB_SL811_HCD_ISO=y
CONFIG_USB_R8A66597_HCD=m
CONFIG_USB_HCD_BCMA=m
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=y
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
CONFIG_USB_STORAGE_REALTEK=m
CONFIG_REALTEK_AUTOPM=y
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_FREECOM=m
CONFIG_USB_STORAGE_ISD200=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_STORAGE_ALAUDA=m
CONFIG_USB_STORAGE_ONETOUCH=m
CONFIG_USB_STORAGE_KARMA=m
CONFIG_USB_STORAGE_CYPRESS_ATACB=m
CONFIG_USB_STORAGE_ENE_UB6250=m
CONFIG_USB_UAS=y

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
CONFIG_USB_MICROTEK=m
CONFIG_USBIP_CORE=m
CONFIG_USBIP_VHCI_HCD=m
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=m
CONFIG_USBIP_VUDC=m
# CONFIG_USBIP_DEBUG is not set

#
# USB dual-mode controller drivers
#
# CONFIG_USB_CDNS_SUPPORT is not set
CONFIG_USB_MUSB_HDRC=y
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y

#
# Platform Glue Layer
#
CONFIG_USB_MUSB_SUNXI=m

#
# MUSB DMA mode
#
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_ULPI=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y

#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=y
CONFIG_USB_DWC3_HAPS=m
CONFIG_USB_DWC3_MESON_G12A=y
CONFIG_USB_DWC3_OF_SIMPLE=m
CONFIG_USB_DWC3_GENERIC_PLAT=y
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
CONFIG_USB_DWC2_PCI=m
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
CONFIG_USB_CHIPIDEA=m
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_CHIPIDEA_PCI=m
CONFIG_USB_CHIPIDEA_MSM=m
CONFIG_USB_CHIPIDEA_NPCM=m
CONFIG_USB_CHIPIDEA_IMX=m
CONFIG_USB_CHIPIDEA_GENERIC=m
CONFIG_USB_CHIPIDEA_TEGRA=m
CONFIG_USB_ISP1760=m
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_ISP1761_UDC=y
# CONFIG_USB_ISP1760_HOST_ROLE is not set
# CONFIG_USB_ISP1760_GADGET_ROLE is not set
CONFIG_USB_ISP1760_DUAL_ROLE=y

#
# USB port drivers
#
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=m
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=y
CONFIG_USB_SERIAL_CH348=m
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=y
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=y
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=m
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_F81232=m
CONFIG_USB_SERIAL_F8153X=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=m
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_METRO=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MXUPORT=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=y
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=m
CONFIG_USB_SERIAL_QUALCOMM=m
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
# CONFIG_USB_SERIAL_SAFE_PADDED is not set
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
CONFIG_USB_SERIAL_SYMBOL=m
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_WWAN=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=m
CONFIG_USB_SERIAL_XSENS_MT=m
CONFIG_USB_SERIAL_WISHBONE=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_SERIAL_QT2=m
CONFIG_USB_SERIAL_UPD78F0730=m
CONFIG_USB_SERIAL_XR=m
CONFIG_USB_SERIAL_DEBUG=m

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
CONFIG_USB_CYPRESS_CY7C63=m
CONFIG_USB_CYTHERM=m
CONFIG_USB_IDMOUSE=m
CONFIG_USB_APPLEDISPLAY=m
CONFIG_APPLE_MFI_FASTCHARGE=m
# CONFIG_USB_LJCA is not set
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
CONFIG_USB_TEST=m
CONFIG_USB_EHSET_TEST_FIXTURE=m
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=m
CONFIG_USB_HUB_USB251XB=m
CONFIG_USB_HSIC_USB3503=m
CONFIG_USB_HSIC_USB4604=m
CONFIG_USB_LINK_LAYER_TEST=m
CONFIG_USB_CHAOSKEY=m
CONFIG_USB_ONBOARD_DEV=y
CONFIG_USB_ONBOARD_DEV_USB5744=y

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=m
CONFIG_USB_GPIO_VBUS=m
CONFIG_USB_ISP1301=m
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set

#
# USB Peripheral Controller
#
CONFIG_USB_GR_UDC=m
CONFIG_USB_R8A66597=m
CONFIG_USB_PXA27X=m
CONFIG_USB_SNP_CORE=m
CONFIG_USB_SNP_UDC_PLAT=m
CONFIG_USB_M66592=m
CONFIG_USB_BDC_UDC=m
CONFIG_USB_AMD5536UDC=m
CONFIG_USB_NET2280=m
CONFIG_USB_GOKU=m
CONFIG_USB_EG20T=m
CONFIG_USB_GADGET_XILINX=m
CONFIG_USB_MAX3420_UDC=m
CONFIG_USB_CDNS2_UDC=m
CONFIG_USB_DUMMY_HCD=m
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=m
CONFIG_USB_F_ACM=m
CONFIG_USB_F_SS_LB=m
CONFIG_USB_U_SERIAL=m
CONFIG_USB_U_ETHER=m
CONFIG_USB_U_AUDIO=m
CONFIG_USB_F_SERIAL=m
CONFIG_USB_F_OBEX=m
CONFIG_USB_F_NCM=m
CONFIG_USB_F_ECM=m
CONFIG_USB_F_EEM=m
CONFIG_USB_F_SUBSET=m
CONFIG_USB_F_RNDIS=m
CONFIG_USB_F_MASS_STORAGE=m
CONFIG_USB_F_FS=m
CONFIG_USB_F_UAC1=m
CONFIG_USB_F_UAC1_LEGACY=m
CONFIG_USB_F_UAC2=m
CONFIG_USB_F_UVC=m
CONFIG_USB_F_MIDI=m
CONFIG_USB_F_MIDI2=m
CONFIG_USB_F_HID=m
CONFIG_USB_F_PRINTER=m
CONFIG_USB_F_TCM=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_LB_SS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_MIDI2=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y
CONFIG_USB_CONFIGFS_F_TCM=y

#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=m
CONFIG_USB_ZERO_HNPTEST=y
CONFIG_USB_AUDIO=m
CONFIG_GADGET_UAC1=y
CONFIG_GADGET_UAC1_LEGACY=y
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
CONFIG_USB_FUNCTIONFS_ETH=y
CONFIG_USB_FUNCTIONFS_RNDIS=y
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_GADGET_TARGET=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_G_HID=m
CONFIG_USB_G_DBGP=m
# CONFIG_USB_G_DBGP_PRINTK is not set
CONFIG_USB_G_DBGP_SERIAL=y
CONFIG_USB_G_WEBCAM=m
CONFIG_USB_RAW_GADGET=m
# end of USB Gadget precomposed configurations

CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
CONFIG_TYPEC_HUSB311=y
CONFIG_TYPEC_RT1711H=y
CONFIG_TYPEC_TCPCI_MAXIM=y
CONFIG_TYPEC_FUSB302=y
CONFIG_TYPEC_UCSI=y
CONFIG_UCSI_CCG=y
CONFIG_UCSI_ACPI=y
CONFIG_UCSI_STM32G0=y
CONFIG_TYPEC_TPS6598X=y
CONFIG_TYPEC_ANX7411=y
CONFIG_TYPEC_RT1719=y
CONFIG_TYPEC_HD3SS3220=y
CONFIG_TYPEC_STUSB160X=y
CONFIG_TYPEC_WUSB3801=y

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
CONFIG_TYPEC_MUX_FSA4480=m
CONFIG_TYPEC_MUX_GPIO_SBU=m
CONFIG_TYPEC_MUX_PI3USB30532=m
CONFIG_TYPEC_MUX_IT5205=m
CONFIG_TYPEC_MUX_NB7VPQ904M=m
# CONFIG_TYPEC_MUX_PS883X is not set
CONFIG_TYPEC_MUX_PTN36502=m
# CONFIG_TYPEC_MUX_TUSB1046 is not set
CONFIG_TYPEC_MUX_WCD939X_USBSS=m
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
CONFIG_TYPEC_DP_ALTMODE=m
CONFIG_TYPEC_NVIDIA_ALTMODE=m
# CONFIG_TYPEC_TBT_ALTMODE is not set
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
# CONFIG_PWRSEQ_SD8787 is not set
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set
# CONFIG_MMC_CRYPTO is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_ARMMMCI=m
CONFIG_MMC_STM32_SDMMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_UHS2=m
CONFIG_MMC_SDHCI_PCI=m
CONFIG_MMC_RICOH_MMC=y
CONFIG_MMC_SDHCI_ACPI=m
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
CONFIG_MMC_SDHCI_OF_AT91=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MMC_SDHCI_F_SDH30=m
CONFIG_MMC_SDHCI_MILBEAUT=m
CONFIG_MMC_MESON_GX=y
CONFIG_MMC_MESON_MX_SDIO=y
CONFIG_MMC_TIFM_SD=m
CONFIG_MMC_SPI=m
CONFIG_MMC_CB710=m
CONFIG_MMC_VIA_SDMMC=m
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
CONFIG_MMC_DW_BLUEFIELD=m
CONFIG_MMC_DW_EXYNOS=m
CONFIG_MMC_DW_HI3798CV200=m
CONFIG_MMC_DW_HI3798MV200=m
CONFIG_MMC_DW_K3=m
CONFIG_MMC_DW_PCI=m
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_VUB300=m
CONFIG_MMC_USHC=m
CONFIG_MMC_USDHI6ROL0=m
CONFIG_MMC_REALTEK_USB=m
CONFIG_MMC_SUNXI=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_HSQ=y
CONFIG_MMC_TOSHIBA_PCI=m
CONFIG_MMC_MTK=y
CONFIG_MMC_SDHCI_XENON=m
CONFIG_SCSI_UFSHCD=y
CONFIG_SCSI_UFS_BSG=y
CONFIG_SCSI_UFS_CRYPTO=y
CONFIG_SCSI_UFS_HWMON=y
CONFIG_SCSI_UFSHCD_PCI=m
CONFIG_SCSI_UFS_DWC_TC_PCI=m
CONFIG_SCSI_UFSHCD_PLATFORM=y
CONFIG_SCSI_UFS_CDNS_PLATFORM=y
CONFIG_SCSI_UFS_DWC_TC_PLATFORM=y
CONFIG_SCSI_UFS_ROCKCHIP=y
# CONFIG_MEMSTICK is not set
CONFIG_LEDS_EXPRESSWIRE=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
CONFIG_LEDS_CLASS_MULTICOLOR=y
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y

#
# LED drivers
#
CONFIG_LEDS_AN30259A=m
CONFIG_LEDS_AW200XX=m
CONFIG_LEDS_AW2013=m
CONFIG_LEDS_BCM6328=m
CONFIG_LEDS_BCM6358=m
CONFIG_LEDS_CR0014114=m
CONFIG_LEDS_EL15203000=m
CONFIG_LEDS_LM3530=m
CONFIG_LEDS_LM3532=m
CONFIG_LEDS_LM3642=m
CONFIG_LEDS_LM3692X=m
# CONFIG_LEDS_SUN50I_A100 is not set
CONFIG_LEDS_PCA9532=m
CONFIG_LEDS_PCA9532_GPIO=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=m
CONFIG_LEDS_LP3952=m
CONFIG_LEDS_LP50XX=m
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LEDS_LP5521=m
CONFIG_LEDS_LP5523=m
CONFIG_LEDS_LP5562=m
# CONFIG_LEDS_LP5569 is not set
CONFIG_LEDS_LP8501=m
CONFIG_LEDS_LP8860=m
# CONFIG_LEDS_LP8864 is not set
CONFIG_LEDS_PCA955X=m
CONFIG_LEDS_PCA955X_GPIO=y
CONFIG_LEDS_PCA963X=m
CONFIG_LEDS_PCA995X=m
CONFIG_LEDS_DAC124S085=m
CONFIG_LEDS_PWM=y
CONFIG_LEDS_REGULATOR=y
CONFIG_LEDS_BD2606MVV=m
CONFIG_LEDS_BD2802=m
CONFIG_LEDS_LT3593=m
CONFIG_LEDS_TCA6507=y
CONFIG_LEDS_TLC591XX=m
CONFIG_LEDS_LM355x=m
CONFIG_LEDS_IS31FL319X=m
CONFIG_LEDS_IS31FL32XX=m

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=m
# CONFIG_LEDS_BLINKM_MULTICOLOR is not set
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_MLXREG=m
CONFIG_LEDS_USER=y
CONFIG_LEDS_SPI_BYTE=m
CONFIG_LEDS_TI_LMU_COMMON=m
CONFIG_LEDS_LM3697=m
CONFIG_LEDS_ST1202=m

#
# Flash and Torch LED drivers
#
CONFIG_LEDS_AAT1290=m
CONFIG_LEDS_AS3645A=m
CONFIG_LEDS_KTD2692=m
CONFIG_LEDS_LM3601X=m
CONFIG_LEDS_RT4505=m
CONFIG_LEDS_RT8515=m
CONFIG_LEDS_SGM3140=m
# CONFIG_LEDS_SY7802 is not set
# CONFIG_LEDS_TPS6131X is not set

#
# RGB LED drivers
#
CONFIG_LEDS_GROUP_MULTICOLOR=m
# CONFIG_LEDS_KTD202X is not set
# CONFIG_LEDS_NCP5623 is not set
CONFIG_LEDS_PWM_MULTICOLOR=y
CONFIG_LEDS_QCOM_LPG=m

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_ACTIVITY=y
# CONFIG_LEDS_TRIGGER_GPIO is not set
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=y
CONFIG_LEDS_TRIGGER_PATTERN=y
CONFIG_LEDS_TRIGGER_TTY=y
# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set

#
# Simatic LED drivers
#
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
# CONFIG_EDAC_DEBUG is not set
# CONFIG_EDAC_GHES is not set
# CONFIG_EDAC_SCRUB is not set
# CONFIG_EDAC_ECS is not set
# CONFIG_EDAC_MEM_REPAIR is not set
# CONFIG_EDAC_THUNDERX is not set
# CONFIG_EDAC_XGENE is not set
CONFIG_EDAC_DMC520=m
# CONFIG_EDAC_CORTEX_A72 is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_ABB5ZES3 is not set
# CONFIG_RTC_DRV_ABEOZ9 is not set
# CONFIG_RTC_DRV_ABX80X is not set
CONFIG_RTC_DRV_AC100=m
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
CONFIG_RTC_DRV_HYM8563=m
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_MAX31335 is not set
# CONFIG_RTC_DRV_NCT3018Y is not set
CONFIG_RTC_DRV_RK808=m
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_ISL12026 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8523 is not set
# CONFIG_RTC_DRV_PCF85363 is not set
CONFIG_RTC_DRV_PCF8563=m
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8010 is not set
# CONFIG_RTC_DRV_RX8111 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV3028 is not set
# CONFIG_RTC_DRV_RV3032 is not set
# CONFIG_RTC_DRV_RV8803 is not set
# CONFIG_RTC_DRV_SD2405AL is not set
# CONFIG_RTC_DRV_SD3078 is not set

#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_MCP795 is not set
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_PCF2127 is not set
# CONFIG_RTC_DRV_PCF85063 is not set
# CONFIG_RTC_DRV_RV3029C2 is not set
# CONFIG_RTC_DRV_RX6110 is not set

#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1685_FAMILY is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_DS2404 is not set
CONFIG_RTC_DRV_EFI=m
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_OPTEE is not set
# CONFIG_RTC_DRV_ZYNQMP is not set

#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_MESON_VRTC=m
CONFIG_RTC_DRV_PL030=m
CONFIG_RTC_DRV_PL031=m
CONFIG_RTC_DRV_SUN6I=y
# CONFIG_RTC_DRV_CADENCE is not set
# CONFIG_RTC_DRV_FTRTC010 is not set
# CONFIG_RTC_DRV_R7301 is not set
# CONFIG_RTC_DRV_GOLDFISH is not set
CONFIG_RTC_DRV_AMLOGIC_A4=y

#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
CONFIG_AMBA_PL08X=y
# CONFIG_ARM_DMA350 is not set
# CONFIG_BCM_SBA_RAID is not set
CONFIG_DMA_SUN6I=y
CONFIG_DW_AXI_DMAC=y
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_MV_XOR_V2 is not set
CONFIG_PL330_DMA=y
# CONFIG_PLX_DMA is not set
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_XDMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
# CONFIG_XILINX_ZYNQMP_DPDMA is not set
# CONFIG_AMD_QDMA is not set
CONFIG_QCOM_HIDMA_MGMT=y
CONFIG_QCOM_HIDMA=y
CONFIG_DW_DMAC_CORE=y
CONFIG_DW_DMAC=y
CONFIG_DW_DMAC_PCI=y
CONFIG_DW_EDMA=y
CONFIG_DW_EDMA_PCIE=y
# CONFIG_SF_PDMA is not set

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_DEBUG is not set
# CONFIG_DMABUF_SELFTESTS is not set
CONFIG_DMABUF_HEAPS=y
# CONFIG_DMABUF_SYSFS_STATS is not set
CONFIG_DMABUF_HEAPS_SYSTEM=y
CONFIG_DMABUF_HEAPS_CMA=y
CONFIG_DMABUF_HEAPS_CMA_LEGACY=y
# end of DMABUF options

# CONFIG_UIO is not set
# CONFIG_VFIO is not set
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_VIRT_DRIVERS=y
CONFIG_VMGENID=y
# CONFIG_VBOXGUEST is not set
# CONFIG_EFI_SECRET is not set
# CONFIG_ARM_PKVM_GUEST is not set
# CONFIG_ARM_CCA_GUEST is not set
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_PCI_LIB=m
CONFIG_VIRTIO_PCI_LIB_LEGACY=m
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=m
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
# CONFIG_VIRTIO_DEBUG is not set
# CONFIG_VIRTIO_RTC is not set
# CONFIG_VDPA is not set
CONFIG_VHOST_IOTLB=m
CONFIG_VHOST_TASK=y
CONFIG_VHOST=m
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_SCSI=m
# CONFIG_VHOST_VSOCK is not set
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
CONFIG_VHOST_ENABLE_FORK_OWNER_CONTROL=y

#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
# CONFIG_COMEDI is not set
CONFIG_STAGING=y
CONFIG_RTL8723BS=m

#
# IIO staging drivers
#

#
# Accelerometers
#
# CONFIG_ADIS16203 is not set
# end of Accelerometers

#
# Analog to digital converters
#
# CONFIG_AD7816 is not set
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
# CONFIG_ADT7316 is not set
# end of Analog digital bi-direction converters

#
# Direct Digital Synthesis
#
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
# CONFIG_AD5933 is not set
# end of Network Analyzer, Impedance Converters
# end of IIO staging drivers

# CONFIG_FB_SM750 is not set
CONFIG_STAGING_MEDIA=y
# CONFIG_VIDEO_MAX96712 is not set
CONFIG_VIDEO_MESON_VDEC=m

#
# StarFive media platform drivers
#
CONFIG_VIDEO_SUNXI=y
CONFIG_VIDEO_SUNXI_CEDRUS=m
CONFIG_VIDEO_SUN6I_ISP=m
# CONFIG_STAGING_MEDIA_DEPRECATED is not set
CONFIG_FB_TFT=m
CONFIG_FB_TFT_AGM1264K_FL=m
CONFIG_FB_TFT_BD663474=m
CONFIG_FB_TFT_HX8340BN=m
CONFIG_FB_TFT_HX8347D=m
CONFIG_FB_TFT_HX8353D=m
CONFIG_FB_TFT_HX8357D=m
CONFIG_FB_TFT_ILI9163=m
CONFIG_FB_TFT_ILI9320=m
CONFIG_FB_TFT_ILI9325=m
CONFIG_FB_TFT_ILI9340=m
CONFIG_FB_TFT_ILI9341=m
CONFIG_FB_TFT_ILI9481=m
CONFIG_FB_TFT_ILI9486=m
CONFIG_FB_TFT_PCD8544=m
CONFIG_FB_TFT_RA8875=m
CONFIG_FB_TFT_S6D02A1=m
CONFIG_FB_TFT_S6D1121=m
CONFIG_FB_TFT_SEPS525=m
CONFIG_FB_TFT_SH1106=m
CONFIG_FB_TFT_SSD1289=m
CONFIG_FB_TFT_SSD1305=m
CONFIG_FB_TFT_SSD1306=m
CONFIG_FB_TFT_SSD1331=m
CONFIG_FB_TFT_SSD1351=m
CONFIG_FB_TFT_ST7735R=m
CONFIG_FB_TFT_ST7789V=m
CONFIG_FB_TFT_TINYLCD=m
CONFIG_FB_TFT_TLS8204=m
CONFIG_FB_TFT_UC1611=m
CONFIG_FB_TFT_UC1701=m
CONFIG_FB_TFT_UPD161704=m
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_VME_BUS is not set
# CONFIG_GPIB is not set
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
CONFIG_SURFACE_PLATFORMS=y
# CONFIG_SURFACE_3_POWER_OPREGION is not set
# CONFIG_SURFACE_GPE is not set
# CONFIG_SURFACE_HOTPLUG is not set
# CONFIG_SURFACE_PRO3_BUTTON is not set
# CONFIG_SURFACE_AGGREGATOR is not set
CONFIG_ARM64_PLATFORM_DEVICES=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Clock driver for ARM Reference designs
#
# CONFIG_CLK_ICST is not set
# CONFIG_CLK_SP810 is not set
# CONFIG_CLK_VEXPRESS_OSC is not set
# end of Clock driver for ARM Reference designs

# CONFIG_LMK04832 is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
CONFIG_COMMON_CLK_CS2000_CP=y
# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
# CONFIG_COMMON_CLK_XGENE is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_RS9_PCIE is not set
# CONFIG_COMMON_CLK_SI521XX is not set
# CONFIG_COMMON_CLK_VC3 is not set
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_VC7 is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set

#
# Clock support for Amlogic platforms
#
CONFIG_COMMON_CLK_MESON_REGMAP=y
CONFIG_COMMON_CLK_MESON_DUALDIV=y
CONFIG_COMMON_CLK_MESON_MPLL=y
CONFIG_COMMON_CLK_MESON_PHASE=y
CONFIG_COMMON_CLK_MESON_PLL=y
CONFIG_COMMON_CLK_MESON_SCLK_DIV=y
CONFIG_COMMON_CLK_MESON_VID_PLL_DIV=y
CONFIG_COMMON_CLK_MESON_VCLK=y
CONFIG_COMMON_CLK_MESON_CLKC_UTILS=y
CONFIG_COMMON_CLK_MESON_AO_CLKC=y
CONFIG_COMMON_CLK_MESON_CPU_DYNDIV=y
CONFIG_COMMON_CLK_GXBB=y
CONFIG_COMMON_CLK_AXG=y
CONFIG_COMMON_CLK_AXG_AUDIO=y
CONFIG_COMMON_CLK_A1_PLL=y
CONFIG_COMMON_CLK_A1_PERIPHERALS=y
CONFIG_COMMON_CLK_C3_PLL=y
CONFIG_COMMON_CLK_C3_PERIPHERALS=y
CONFIG_COMMON_CLK_G12A=y
CONFIG_COMMON_CLK_S4_PLL=y
CONFIG_COMMON_CLK_S4_PERIPHERALS=y
CONFIG_COMMON_CLK_T7_PLL=y
CONFIG_COMMON_CLK_T7_PERIPHERALS=y
# end of Clock support for Amlogic platforms

CONFIG_COMMON_CLK_ROCKCHIP=y
CONFIG_CLK_PX30=y
CONFIG_CLK_RV1126B=y
CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
CONFIG_CLK_RK3399=y
CONFIG_CLK_RK3528=y
CONFIG_CLK_RK3562=y
CONFIG_CLK_RK3568=y
CONFIG_CLK_RK3576=y
CONFIG_CLK_RK3588=y
CONFIG_SUNXI_CCU=y
CONFIG_SUN50I_A64_CCU=y
CONFIG_SUN50I_A100_CCU=y
CONFIG_SUN50I_A100_R_CCU=y
CONFIG_SUN50I_H6_CCU=y
CONFIG_SUN50I_H616_CCU=y
CONFIG_SUN50I_H6_R_CCU=y
CONFIG_SUN55I_A523_CCU=y
CONFIG_SUN55I_A523_MCU_CCU=y
CONFIG_SUN55I_A523_R_CCU=y
CONFIG_SUN6I_RTC_CCU=y
CONFIG_SUN8I_H3_CCU=y
CONFIG_SUN8I_DE2_CCU=y
CONFIG_SUN8I_R_CCU=y
# CONFIG_XILINX_VCU is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_SUN6I=y

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_ACPI=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_SUN4I_TIMER=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
CONFIG_ARM_TIMER_SP804=y
# end of Clock Source drivers

CONFIG_MAILBOX=y
CONFIG_ARM_MHU=y
CONFIG_ARM_MHU_V2=y
CONFIG_ARM_MHU_V3=y
CONFIG_PLATFORM_MHU=y
CONFIG_PL320_MBOX=y
CONFIG_ROCKCHIP_MBOX=y
CONFIG_PCC=y
CONFIG_ALTERA_MBOX=m
# CONFIG_MAILBOX_TEST is not set
CONFIG_SUN6I_MSGBOX=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_DART is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
CONFIG_IOMMU_SVA=y
CONFIG_IOMMU_IOPF=y
CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
CONFIG_ARM_SMMU_MMU_500_CPRE_ERRATA=y
CONFIG_ARM_SMMU_V3=y
CONFIG_ARM_SMMU_V3_SVA=y
# CONFIG_TEGRA241_CMDQV is not set
# CONFIG_IOMMUFD is not set
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_SUN50I_IOMMU=y
CONFIG_VIRTIO_IOMMU=m
# CONFIG_VSI_IOMMU is not set

#
# Remoteproc drivers
#
CONFIG_REMOTEPROC=y
CONFIG_REMOTEPROC_CDEV=y
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=m
CONFIG_RPMSG_CHAR=m
# CONFIG_RPMSG_CTRL is not set
CONFIG_RPMSG_NS=m
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
CONFIG_RPMSG_VIRTIO=m
# end of Rpmsg drivers

# CONFIG_SOUNDWIRE is not set

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
CONFIG_MESON_CANVAS=y
CONFIG_MESON_CLK_MEASURE=y
CONFIG_MESON_GX_SOCINFO=y
# end of Amlogic SoC drivers

#
# Broadcom SoC drivers
#
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
CONFIG_QUICC_ENGINE=y
# CONFIG_CPM_TSA is not set
# end of NXP/Freescale QorIQ SoC drivers

#
# fujitsu SoC drivers
#
# CONFIG_A64FX_DIAG is not set
# end of fujitsu SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Enable LiteX SoC Builder specific drivers
#
# CONFIG_LITEX_SOC_CONTROLLER is not set
# end of Enable LiteX SoC Builder specific drivers

# CONFIG_WPCM450_SOC is not set

#
# Qualcomm SoC drivers
#
# CONFIG_QCOM_PMIC_PDCHARGER_ULOG is not set
# CONFIG_QCOM_PMIC_GLINK is not set
CONFIG_QCOM_QMI_HELPERS=m
# CONFIG_QCOM_PBS is not set
# end of Qualcomm SoC drivers

CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_SUNXI_MBUS=y
CONFIG_SUNXI_SRAM=y
# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

#
# PM Domains
#

#
# Amlogic PM Domains
#
CONFIG_MESON_EE_PM_DOMAINS=y
CONFIG_MESON_SECURE_PM_DOMAINS=y
# end of Amlogic PM Domains

CONFIG_ARM_SCMI_PERF_DOMAIN=y
CONFIG_ARM_SCMI_POWER_DOMAIN=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y

#
# Broadcom PM Domains
#
# end of Broadcom PM Domains

#
# i.MX PM Domains
#
# end of i.MX PM Domains

#
# Qualcomm PM Domains
#
# end of Qualcomm PM Domains

CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_SUN20I_PPU=y
# CONFIG_SUN50I_H6_PRCM_PPU is not set
CONFIG_SUN55I_PCK600=y
# end of PM Domains

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=m
CONFIG_DEVFREQ_GOV_USERSPACE=m
CONFIG_DEVFREQ_GOV_PASSIVE=m

#
# DEVFREQ Drivers
#
# CONFIG_ARM_HISI_UNCORE_DEVFREQ is not set
CONFIG_ARM_RK3399_DMC_DEVFREQ=y
CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
CONFIG_EXTCON_ADC_JACK=m
CONFIG_EXTCON_FSA9480=m
CONFIG_EXTCON_GPIO=m
# CONFIG_EXTCON_LC824206XA is not set
CONFIG_EXTCON_MAX3355=m
# CONFIG_EXTCON_MAX14526 is not set
CONFIG_EXTCON_PTN5150=m
CONFIG_EXTCON_RT8973A=m
CONFIG_EXTCON_SM5502=m
CONFIG_EXTCON_USB_GPIO=m
CONFIG_EXTCON_USBC_TUSB320=m
CONFIG_MEMORY=y
CONFIG_ARM_PL172_MPMC=m
# CONFIG_FPGA_DFL_EMIF is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
CONFIG_IIO_BUFFER_DMA=m
CONFIG_IIO_BUFFER_DMAENGINE=m
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_GTS_HELPER=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
CONFIG_IIO_TRIGGERED_EVENT=m
CONFIG_IIO_BACKEND=m

#
# Accelerometers
#
CONFIG_ADIS16201=m
CONFIG_ADIS16209=m
CONFIG_ADXL313=m
CONFIG_ADXL313_I2C=m
CONFIG_ADXL313_SPI=m
CONFIG_ADXL345=m
CONFIG_ADXL345_I2C=m
CONFIG_ADXL345_SPI=m
CONFIG_ADXL355=m
CONFIG_ADXL355_I2C=m
CONFIG_ADXL355_SPI=m
CONFIG_ADXL367=m
CONFIG_ADXL367_SPI=m
CONFIG_ADXL367_I2C=m
CONFIG_ADXL372=m
CONFIG_ADXL372_SPI=m
CONFIG_ADXL372_I2C=m
# CONFIG_ADXL380_SPI is not set
# CONFIG_ADXL380_I2C is not set
CONFIG_BMA180=m
CONFIG_BMA220=m
CONFIG_BMA400=m
CONFIG_BMA400_I2C=m
CONFIG_BMA400_SPI=m
CONFIG_BMC150_ACCEL=m
CONFIG_BMC150_ACCEL_I2C=m
CONFIG_BMC150_ACCEL_SPI=m
CONFIG_BMI088_ACCEL=m
CONFIG_BMI088_ACCEL_I2C=m
CONFIG_BMI088_ACCEL_SPI=m
CONFIG_DA280=m
CONFIG_DA311=m
CONFIG_DMARD06=m
CONFIG_DMARD09=m
CONFIG_DMARD10=m
CONFIG_FXLS8962AF=m
CONFIG_FXLS8962AF_I2C=m
CONFIG_FXLS8962AF_SPI=m
CONFIG_HID_SENSOR_ACCEL_3D=m
CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
# CONFIG_IIO_KX022A_SPI is not set
# CONFIG_IIO_KX022A_I2C is not set
CONFIG_KXSD9=m
CONFIG_KXSD9_SPI=m
CONFIG_KXSD9_I2C=m
CONFIG_KXCJK1013=m
CONFIG_MC3230=m
CONFIG_MMA7455=m
CONFIG_MMA7455_I2C=m
CONFIG_MMA7455_SPI=m
CONFIG_MMA7660=m
CONFIG_MMA8452=m
CONFIG_MMA9551_CORE=m
CONFIG_MMA9551=m
CONFIG_MMA9553=m
CONFIG_MSA311=m
CONFIG_MXC4005=m
CONFIG_MXC6255=m
CONFIG_SCA3000=m
CONFIG_SCA3300=m
CONFIG_STK8312=m
CONFIG_STK8BA50=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=m
# CONFIG_AD4000 is not set
# CONFIG_AD4030 is not set
# CONFIG_AD4080 is not set
# CONFIG_AD4130 is not set
# CONFIG_AD4170_4 is not set
# CONFIG_AD4695 is not set
# CONFIG_AD4851 is not set
CONFIG_AD7091R=m
CONFIG_AD7091R5=m
# CONFIG_AD7091R8 is not set
CONFIG_AD7124=m
# CONFIG_AD7173 is not set
# CONFIG_AD7191 is not set
CONFIG_AD7192=m
CONFIG_AD7266=m
CONFIG_AD7280=m
CONFIG_AD7291=m
CONFIG_AD7292=m
CONFIG_AD7298=m
# CONFIG_AD7380 is not set
# CONFIG_AD7405 is not set
CONFIG_AD7476=m
CONFIG_AD7606=m
CONFIG_AD7606_IFACE_PARALLEL=m
CONFIG_AD7606_IFACE_SPI=m
# CONFIG_AD7625 is not set
CONFIG_AD7766=m
CONFIG_AD7768_1=m
# CONFIG_AD7779 is not set
CONFIG_AD7780=m
CONFIG_AD7791=m
CONFIG_AD7793=m
CONFIG_AD7887=m
CONFIG_AD7923=m
# CONFIG_AD7944 is not set
CONFIG_AD7949=m
CONFIG_AD799X=m
CONFIG_AD9467=m
# CONFIG_ADE9000 is not set
CONFIG_AXP20X_ADC=y
CONFIG_AXP288_ADC=y
CONFIG_CC10001_ADC=m
CONFIG_ENVELOPE_DETECTOR=m
# CONFIG_GEHC_PMC_ADC is not set
CONFIG_HI8435=m
CONFIG_HX711=m
CONFIG_INA2XX_ADC=m
# CONFIG_LTC2309 is not set
CONFIG_LTC2471=m
CONFIG_LTC2485=m
CONFIG_LTC2496=m
CONFIG_LTC2497=m
CONFIG_MAX1027=m
CONFIG_MAX11100=m
CONFIG_MAX1118=m
CONFIG_MAX11205=m
# CONFIG_MAX11410 is not set
CONFIG_MAX1241=m
CONFIG_MAX1363=m
# CONFIG_MAX34408 is not set
CONFIG_MAX9611=m
CONFIG_MCP320X=m
CONFIG_MCP3422=m
# CONFIG_MCP3564 is not set
CONFIG_MCP3911=m
CONFIG_MESON_SARADC=y
CONFIG_NAU7802=m
# CONFIG_NCT7201 is not set
# CONFIG_PAC1921 is not set
# CONFIG_PAC1934 is not set
CONFIG_QCOM_VADC_COMMON=m
CONFIG_QCOM_SPMI_IADC=m
CONFIG_QCOM_SPMI_VADC=m
CONFIG_QCOM_SPMI_ADC5=m
# CONFIG_ROHM_BD79112 is not set
# CONFIG_ROHM_BD79124 is not set
CONFIG_ROCKCHIP_SARADC=y
CONFIG_RICHTEK_RTQ6056=m
CONFIG_SD_ADC_MODULATOR=m
# CONFIG_SUN20I_GPADC is not set
CONFIG_TI_ADC081C=m
CONFIG_TI_ADC0832=m
CONFIG_TI_ADC084S021=m
CONFIG_TI_ADC108S102=m
CONFIG_TI_ADC12138=m
CONFIG_TI_ADC128S052=m
CONFIG_TI_ADC161S626=m
CONFIG_TI_ADS1015=m
# CONFIG_TI_ADS1100 is not set
# CONFIG_TI_ADS1119 is not set
CONFIG_TI_ADS124S08=m
# CONFIG_TI_ADS1298 is not set
CONFIG_TI_ADS131E08=m
# CONFIG_TI_ADS7138 is not set
# CONFIG_TI_ADS7924 is not set
CONFIG_TI_ADS7950=m
CONFIG_TI_ADS8344=m
CONFIG_TI_ADS8688=m
# CONFIG_TI_LMP92064 is not set
CONFIG_TI_TLC4541=m
CONFIG_TI_TSC2046=m
CONFIG_VF610_ADC=m
CONFIG_XILINX_XADC=m
# end of Analog to digital converters

#
# Analog to digital and digital to analog converters
#
# CONFIG_AD74115 is not set
CONFIG_AD74413R=m
# end of Analog to digital and digital to analog converters

#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=m
# end of Analog Front Ends

#
# Amplifiers
#
CONFIG_AD8366=m
CONFIG_ADA4250=m
CONFIG_HMC425=m
# end of Amplifiers

#
# Capacitance to digital converters
#
CONFIG_AD7150=m
CONFIG_AD7746=m
# end of Capacitance to digital converters

#
# Chemical Sensors
#
# CONFIG_AOSONG_AGS02MA is not set
CONFIG_ATLAS_PH_SENSOR=m
CONFIG_ATLAS_EZO_SENSOR=m
CONFIG_BME680=m
CONFIG_BME680_I2C=m
CONFIG_BME680_SPI=m
CONFIG_CCS811=m
# CONFIG_ENS160 is not set
CONFIG_IAQCORE=m
# CONFIG_MHZ19B is not set
CONFIG_PMS7003=m
CONFIG_SCD30_CORE=m
CONFIG_SCD30_I2C=m
CONFIG_SCD30_SERIAL=m
CONFIG_SCD4X=m
# CONFIG_SEN0322 is not set
CONFIG_SENSIRION_SGP30=m
CONFIG_SENSIRION_SGP40=m
CONFIG_SPS30=m
CONFIG_SPS30_I2C=m
CONFIG_SPS30_SERIAL=m
CONFIG_SENSEAIR_SUNRISE_CO2=m
CONFIG_VZ89X=m
# end of Chemical Sensors

#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
# end of Hid Sensor IIO Common

CONFIG_IIO_INV_SENSORS_TIMESTAMP=m
CONFIG_IIO_MS_SENSORS_I2C=m

#
# IIO SCMI Sensors
#
CONFIG_IIO_SCMI=m
# end of IIO SCMI Sensors

#
# SSP Sensor Common
#
CONFIG_IIO_SSP_SENSORS_COMMONS=m
CONFIG_IIO_SSP_SENSORHUB=m
# end of SSP Sensor Common

CONFIG_IIO_ST_SENSORS_I2C=m
CONFIG_IIO_ST_SENSORS_SPI=m
CONFIG_IIO_ST_SENSORS_CORE=m

#
# Digital to analog converters
#
# CONFIG_AD3530R is not set
# CONFIG_AD3552R_HS is not set
CONFIG_AD3552R_LIB=m
CONFIG_AD3552R=m
CONFIG_AD5064=m
CONFIG_AD5360=m
CONFIG_AD5380=m
CONFIG_AD5421=m
CONFIG_AD5446=m
CONFIG_AD5449=m
CONFIG_AD5592R_BASE=m
CONFIG_AD5592R=m
CONFIG_AD5593R=m
CONFIG_AD5504=m
CONFIG_AD5624R_SPI=m
# CONFIG_AD9739A is not set
CONFIG_LTC2688=m
CONFIG_AD5686=m
CONFIG_AD5686_SPI=m
CONFIG_AD5696_I2C=m
CONFIG_AD5755=m
CONFIG_AD5758=m
CONFIG_AD5761=m
CONFIG_AD5764=m
CONFIG_AD5766=m
CONFIG_AD5770R=m
CONFIG_AD5791=m
CONFIG_AD7293=m
CONFIG_AD7303=m
# CONFIG_AD8460 is not set
CONFIG_AD8801=m
# CONFIG_BD79703 is not set
CONFIG_DPOT_DAC=m
CONFIG_DS4424=m
CONFIG_LTC1660=m
CONFIG_LTC2632=m
# CONFIG_LTC2664 is not set
CONFIG_M62332=m
CONFIG_MAX517=m
# CONFIG_MAX5522 is not set
CONFIG_MAX5821=m
CONFIG_MCP4725=m
# CONFIG_MCP4728 is not set
# CONFIG_MCP4821 is not set
CONFIG_MCP4922=m
CONFIG_TI_DAC082S085=m
CONFIG_TI_DAC5571=m
CONFIG_TI_DAC7311=m
CONFIG_TI_DAC7612=m
CONFIG_VF610_DAC=m
# end of Digital to analog converters

#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver

#
# Filters
#
CONFIG_ADMV8818=m
# end of Filters

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
CONFIG_AD9523=m
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4350=m
CONFIG_ADF4371=m
# CONFIG_ADF4377 is not set
# CONFIG_ADMFM2000 is not set
CONFIG_ADMV1013=m
CONFIG_ADMV1014=m
CONFIG_ADMV4420=m
CONFIG_ADRF6780=m
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=m
CONFIG_ADIS16130=m
CONFIG_ADIS16136=m
CONFIG_ADIS16260=m
CONFIG_ADXRS290=m
CONFIG_ADXRS450=m
CONFIG_BMG160=m
CONFIG_BMG160_I2C=m
CONFIG_BMG160_SPI=m
CONFIG_FXAS21002C=m
CONFIG_FXAS21002C_I2C=m
CONFIG_FXAS21002C_SPI=m
CONFIG_HID_SENSOR_GYRO_3D=m
CONFIG_MPU3050=m
CONFIG_MPU3050_I2C=m
CONFIG_IIO_ST_GYRO_3AXIS=m
CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
CONFIG_ITG3200=m
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
CONFIG_AFE4403=m
CONFIG_AFE4404=m
CONFIG_MAX30100=m
CONFIG_MAX30102=m
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
CONFIG_AM2315=m
CONFIG_DHT11=m
# CONFIG_ENS210 is not set
CONFIG_HDC100X=m
CONFIG_HDC2010=m
# CONFIG_HDC3020 is not set
CONFIG_HID_SENSOR_HUMIDITY=m
CONFIG_HTS221=m
CONFIG_HTS221_I2C=m
CONFIG_HTS221_SPI=m
CONFIG_HTU21=m
CONFIG_SI7005=m
CONFIG_SI7020=m
# end of Humidity sensors

#
# Inertial measurement units
#
CONFIG_ADIS16400=m
CONFIG_ADIS16460=m
CONFIG_ADIS16475=m
CONFIG_ADIS16480=m
# CONFIG_ADIS16550 is not set
CONFIG_BMI160=m
CONFIG_BMI160_I2C=m
CONFIG_BMI160_SPI=m
# CONFIG_BMI270_I2C is not set
# CONFIG_BMI270_SPI is not set
# CONFIG_BMI323_I2C is not set
# CONFIG_BMI323_SPI is not set
CONFIG_BOSCH_BNO055=m
CONFIG_BOSCH_BNO055_SERIAL=m
CONFIG_BOSCH_BNO055_I2C=m
CONFIG_FXOS8700=m
CONFIG_FXOS8700_I2C=m
CONFIG_FXOS8700_SPI=m
CONFIG_KMX61=m
CONFIG_INV_ICM42600=m
CONFIG_INV_ICM42600_I2C=m
CONFIG_INV_ICM42600_SPI=m
CONFIG_INV_MPU6050_IIO=m
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_SPI=m
# CONFIG_SMI240 is not set
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_LSM6DSX_I2C=m
CONFIG_IIO_ST_LSM6DSX_SPI=m
CONFIG_IIO_ST_LSM9DS0=m
CONFIG_IIO_ST_LSM9DS0_I2C=m
CONFIG_IIO_ST_LSM9DS0_SPI=m
# end of Inertial measurement units

CONFIG_IIO_ADIS_LIB=m
CONFIG_IIO_ADIS_LIB_BUFFER=y

#
# Light sensors
#
CONFIG_ACPI_ALS=m
CONFIG_ADJD_S311=m
CONFIG_ADUX1020=m
# CONFIG_AL3000A is not set
CONFIG_AL3010=m
CONFIG_AL3320A=m
# CONFIG_APDS9160 is not set
CONFIG_APDS9300=m
# CONFIG_APDS9306 is not set
CONFIG_APDS9960=m
CONFIG_AS73211=m
# CONFIG_BH1745 is not set
CONFIG_BH1750=m
CONFIG_BH1780=m
CONFIG_CM32181=m
CONFIG_CM3232=m
CONFIG_CM3323=m
CONFIG_CM3605=m
CONFIG_CM36651=m
CONFIG_GP2AP002=m
CONFIG_GP2AP020A00F=m
CONFIG_SENSORS_ISL29018=m
CONFIG_SENSORS_ISL29028=m
CONFIG_ISL29125=m
# CONFIG_ISL76682 is not set
CONFIG_HID_SENSOR_ALS=m
CONFIG_HID_SENSOR_PROX=m
CONFIG_JSA1212=m
# CONFIG_ROHM_BU27034 is not set
CONFIG_RPR0521=m
# CONFIG_LTR390 is not set
CONFIG_LTR501=m
CONFIG_LTRF216A=m
CONFIG_LV0104CS=m
CONFIG_MAX44000=m
CONFIG_MAX44009=m
CONFIG_NOA1305=m
CONFIG_OPT3001=m
# CONFIG_OPT4001 is not set
# CONFIG_OPT4060 is not set
CONFIG_PA12203001=m
CONFIG_SI1133=m
CONFIG_SI1145=m
CONFIG_STK3310=m
CONFIG_ST_UVIS25=m
CONFIG_ST_UVIS25_I2C=m
CONFIG_ST_UVIS25_SPI=m
CONFIG_TCS3414=m
CONFIG_TCS3472=m
CONFIG_SENSORS_TSL2563=m
CONFIG_TSL2583=m
CONFIG_TSL2591=m
CONFIG_TSL2772=m
CONFIG_TSL4531=m
CONFIG_US5182D=m
CONFIG_VCNL4000=m
CONFIG_VCNL4035=m
# CONFIG_VEML3235 is not set
CONFIG_VEML6030=m
# CONFIG_VEML6040 is not set
# CONFIG_VEML6046X00 is not set
CONFIG_VEML6070=m
# CONFIG_VEML6075 is not set
CONFIG_VL6180=m
CONFIG_ZOPT2201=m
# end of Light sensors

#
# Magnetometer sensors
#
# CONFIG_AF8133J is not set
CONFIG_AK8974=m
CONFIG_AK8975=m
CONFIG_AK09911=m
# CONFIG_ALS31300 is not set
CONFIG_BMC150_MAGN=m
CONFIG_BMC150_MAGN_I2C=m
CONFIG_BMC150_MAGN_SPI=m
CONFIG_MAG3110=m
CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
CONFIG_MMC35240=m
CONFIG_IIO_ST_MAGN_3AXIS=m
CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
# CONFIG_INFINEON_TLV493D is not set
CONFIG_SENSORS_HMC5843=m
CONFIG_SENSORS_HMC5843_I2C=m
CONFIG_SENSORS_HMC5843_SPI=m
CONFIG_SENSORS_RM3100=m
CONFIG_SENSORS_RM3100_I2C=m
CONFIG_SENSORS_RM3100_SPI=m
# CONFIG_SI7210 is not set
# CONFIG_TI_TMAG5273 is not set
CONFIG_YAMAHA_YAS530=m
# end of Magnetometer sensors

#
# Multiplexers
#
CONFIG_IIO_MUX=m
# end of Multiplexers

#
# Inclinometer sensors
#
CONFIG_HID_SENSOR_INCLINOMETER_3D=m
CONFIG_HID_SENSOR_DEVICE_ROTATION=m
# end of Inclinometer sensors

#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=m
CONFIG_IIO_INTERRUPT_TRIGGER=m
CONFIG_IIO_TIGHTLOOP_TRIGGER=m
CONFIG_IIO_SYSFS_TRIGGER=y
# end of Triggers - standalone

#
# Linear and angular position sensors
#
CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
# end of Linear and angular position sensors

#
# Digital potentiometers
#
CONFIG_AD5110=m
CONFIG_AD5272=m
CONFIG_DS1803=m
CONFIG_MAX5432=m
CONFIG_MAX5481=m
CONFIG_MAX5487=m
CONFIG_MCP4018=m
CONFIG_MCP4131=m
CONFIG_MCP4531=m
CONFIG_MCP41010=m
CONFIG_TPL0102=m
# CONFIG_X9250 is not set
# end of Digital potentiometers

#
# Digital potentiostats
#
CONFIG_LMP91000=m
# end of Digital potentiostats

#
# Pressure sensors
#
CONFIG_ABP060MG=m
# CONFIG_ROHM_BM1390 is not set
CONFIG_BMP280=m
CONFIG_BMP280_I2C=m
CONFIG_BMP280_SPI=m
CONFIG_DLHL60D=m
CONFIG_DPS310=m
CONFIG_HID_SENSOR_PRESS=m
CONFIG_HP03=m
# CONFIG_HSC030PA is not set
CONFIG_ICP10100=m
CONFIG_MPL115=m
CONFIG_MPL115_I2C=m
CONFIG_MPL115_SPI=m
CONFIG_MPL3115=m
# CONFIG_MPRLS0025PA is not set
CONFIG_MS5611=m
CONFIG_MS5611_I2C=m
CONFIG_MS5611_SPI=m
CONFIG_MS5637=m
# CONFIG_SDP500 is not set
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_PRESS_I2C=m
CONFIG_IIO_ST_PRESS_SPI=m
CONFIG_T5403=m
CONFIG_HP206C=m
CONFIG_ZPA2326=m
CONFIG_ZPA2326_I2C=m
CONFIG_ZPA2326_SPI=m
# end of Pressure sensors

#
# Lightning sensors
#
CONFIG_AS3935=m
# end of Lightning sensors

#
# Proximity and distance sensors
#
# CONFIG_D3323AA is not set
# CONFIG_HX9023S is not set
# CONFIG_IRSD200 is not set
CONFIG_ISL29501=m
CONFIG_LIDAR_LITE_V2=m
CONFIG_MB1232=m
CONFIG_PING=m
CONFIG_RFD77402=m
CONFIG_SRF04=m
CONFIG_SX_COMMON=m
CONFIG_SX9310=m
CONFIG_SX9324=m
CONFIG_SX9360=m
CONFIG_SX9500=m
CONFIG_SRF08=m
CONFIG_VCNL3020=m
CONFIG_VL53L0X_I2C=m
# CONFIG_AW96103 is not set
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
CONFIG_AD2S90=m
CONFIG_AD2S1200=m
# CONFIG_AD2S1210 is not set
# end of Resolver to digital converters

#
# Temperature sensors
#
CONFIG_LTC2983=m
CONFIG_MAXIM_THERMOCOUPLE=m
CONFIG_HID_SENSOR_TEMP=m
CONFIG_MLX90614=m
CONFIG_MLX90632=m
# CONFIG_MLX90635 is not set
CONFIG_TMP006=m
CONFIG_TMP007=m
CONFIG_TMP117=m
CONFIG_TSYS01=m
CONFIG_TSYS02D=m
# CONFIG_MAX30208 is not set
CONFIG_MAX31856=m
CONFIG_MAX31865=m
# CONFIG_MCP9600 is not set
# end of Temperature sensors

# CONFIG_NTB is not set
CONFIG_PWM=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_PROVIDE_GPIO is not set
# CONFIG_PWM_ARGON_FAN_HAT is not set
# CONFIG_PWM_ATMEL_TCB is not set
CONFIG_PWM_CLK=y
CONFIG_PWM_DWC_CORE=y
CONFIG_PWM_DWC=y
# CONFIG_PWM_FSL_FTM is not set
# CONFIG_PWM_GPIO is not set
# CONFIG_PWM_MC33XS2410 is not set
CONFIG_PWM_MESON=y
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_SUN4I=y
# CONFIG_PWM_XILINX is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_ITS_PARENT=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V5=y
CONFIG_IRQ_MSI_LIB=y
# CONFIG_AL_FIC is not set
CONFIG_SUN6I_R_INTC=y
CONFIG_SUNXI_NMI_INTC=y
# CONFIG_XILINX_INTC is not set
CONFIG_MESON_IRQ_GPIO=y
# end of IRQ chip support

# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_GPIO=y
CONFIG_RESET_SCMI=y
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SUNXI=y
# CONFIG_RESET_TI_SYSCON is not set
# CONFIG_RESET_TI_TPS380X is not set
CONFIG_RESET_MESON_COMMON=y
CONFIG_RESET_MESON=y
CONFIG_RESET_MESON_AUX=y
CONFIG_RESET_MESON_AUDIO_ARB=y

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_PHY_CAN_TRANSCEIVER is not set
# CONFIG_PHY_NXP_PTN3222 is not set
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_SUN6I_MIPI_DPHY=y
CONFIG_PHY_SUN9I_USB=y
CONFIG_PHY_SUN50I_USB3=y
CONFIG_PHY_MESON8B_USB2=y
CONFIG_PHY_MESON_GXL_USB2=y
CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=y
CONFIG_PHY_MESON_G12A_USB2=y
CONFIG_PHY_MESON_G12A_USB3_PCIE=y
CONFIG_PHY_MESON_AXG_PCIE=y
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
CONFIG_PHY_MESON_AXG_MIPI_DPHY=y

#
# PHY drivers for Broadcom platforms
#
# CONFIG_BCM_KONA_USB2_PHY is not set
# end of PHY drivers for Broadcom platforms

# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_DPHY_RX is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
# CONFIG_PHY_QCOM_USB_HS is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
CONFIG_PHY_ROCKCHIP_DP=y
CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
CONFIG_PHY_ROCKCHIP_PCIE=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY=m
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=m
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
CONFIG_PHY_ROCKCHIP_TYPEC=m
CONFIG_PHY_ROCKCHIP_USB=y
CONFIG_PHY_ROCKCHIP_USBDP=m
# CONFIG_PHY_SAMSUNG_USB2 is not set
# CONFIG_PHY_TUSB1210 is not set
# end of PHY Subsystem

# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCI400_PMU=y
CONFIG_ARM_CCI5xx_PMU=y
CONFIG_ARM_CCN=m
CONFIG_ARM_CMN=m
CONFIG_ARM_NI=m
CONFIG_ARM_PMU=y
CONFIG_ARM_PMU_ACPI=y
CONFIG_ARM_SMMU_V3_PMU=y
CONFIG_ARM_PMUV3=y
CONFIG_ARM_DSU_PMU=m
# CONFIG_FUJITSU_UNCORE_PMU is not set
CONFIG_ARM_SPE_PMU=m
CONFIG_ARM64_BRBE=y
# CONFIG_ARM_DMC620_PMU is not set
# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set
# CONFIG_HISI_PMU is not set
# CONFIG_HISI_PCIE_PMU is not set
# CONFIG_HNS3_PMU is not set
# CONFIG_DWC_PCIE_PMU is not set
# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set
# CONFIG_MESON_DDR_PMU is not set
# end of Performance monitor support

CONFIG_RAS=y
# CONFIG_USB4 is not set

#
# Android
#
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_BINDERFS=y
CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
# end of Android

# CONFIG_LIBNVDIMM is not set
CONFIG_DAX=y
CONFIG_DEV_DAX=m
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_NVMEM_LAYOUTS=y

#
# Layout Types
#
CONFIG_NVMEM_LAYOUT_SL28_VPD=m
CONFIG_NVMEM_LAYOUT_ONIE_TLV=m
CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y
# end of Layout Types

CONFIG_NVMEM_MESON_EFUSE=y
CONFIG_NVMEM_MESON_MX_EFUSE=y
CONFIG_NVMEM_RMEM=y
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
CONFIG_NVMEM_ROCKCHIP_OTP=y
CONFIG_NVMEM_SPMI_SDAM=y
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_NVMEM_U_BOOT_ENV=y

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# CONFIG_HISI_PTT is not set
# end of HW tracing support

CONFIG_FPGA=m
CONFIG_ALTERA_PR_IP_CORE=m
CONFIG_ALTERA_PR_IP_CORE_PLAT=m
CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
CONFIG_FPGA_MGR_ALTERA_CVP=m
CONFIG_FPGA_MGR_XILINX_CORE=m
# CONFIG_FPGA_MGR_XILINX_SELECTMAP is not set
CONFIG_FPGA_MGR_XILINX_SPI=m
CONFIG_FPGA_MGR_ICE40_SPI=m
CONFIG_FPGA_MGR_MACHXO2_SPI=m
CONFIG_FPGA_BRIDGE=m
CONFIG_ALTERA_FREEZE_BRIDGE=m
CONFIG_XILINX_PR_DECOUPLER=m
CONFIG_FPGA_REGION=m
CONFIG_OF_FPGA_REGION=m
CONFIG_FPGA_DFL=m
CONFIG_FPGA_DFL_FME=m
CONFIG_FPGA_DFL_FME_MGR=m
CONFIG_FPGA_DFL_FME_BRIDGE=m
CONFIG_FPGA_DFL_FME_REGION=m
CONFIG_FPGA_DFL_AFU=m
CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m
CONFIG_FPGA_DFL_PCI=m
CONFIG_FPGA_MGR_MICROCHIP_SPI=m
# CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI is not set
# CONFIG_FSI is not set
CONFIG_TEE=y
CONFIG_TEE_DMABUF_HEAPS=y
CONFIG_OPTEE=y
# CONFIG_OPTEE_INSECURE_LOAD_IMAGE is not set
CONFIG_OPTEE_STATIC_PROTMEM_POOL=y
# CONFIG_ARM_TSTEE is not set
CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
# CONFIG_MUX_ADGS1408 is not set
CONFIG_MUX_GPIO=m
CONFIG_MUX_MMIO=m
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set
# CONFIG_INTERCONNECT is not set
CONFIG_COUNTER=m
CONFIG_INTERRUPT_CNT=m
# CONFIG_MOST is not set
# CONFIG_PECI is not set
# CONFIG_HTE is not set
# CONFIG_CDX_BUS is not set
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_IOMAP=y
CONFIG_FS_STACK=y
CONFIG_BUFFER_HEAD=y
CONFIG_LEGACY_DIRECT_IO=y
# CONFIG_EXT2_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
# CONFIG_JFS_DEBUG is not set
# CONFIG_JFS_STATISTICS is not set
CONFIG_XFS_FS=y
CONFIG_XFS_SUPPORT_V4=y
CONFIG_XFS_SUPPORT_ASCII_CI=y
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
# CONFIG_XFS_RT is not set
# CONFIG_XFS_ONLINE_SCRUB is not set
# CONFIG_XFS_WARN is not set
# CONFIG_XFS_DEBUG is not set
CONFIG_GFS2_FS=m
CONFIG_GFS2_FS_LOCKING_DLM=y
CONFIG_OCFS2_FS=m
CONFIG_OCFS2_FS_O2CB=m
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
CONFIG_OCFS2_FS_STATS=y
CONFIG_OCFS2_DEBUG_MASKLOG=y
# CONFIG_OCFS2_DEBUG_FS is not set
CONFIG_BTRFS_FS=y
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
# CONFIG_BTRFS_EXPERIMENTAL is not set
CONFIG_NILFS2_FS=m
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
# CONFIG_F2FS_FAULT_INJECTION is not set
CONFIG_F2FS_FS_COMPRESSION=y
CONFIG_F2FS_FS_LZO=y
CONFIG_F2FS_FS_LZORLE=y
CONFIG_F2FS_FS_LZ4=y
CONFIG_F2FS_FS_LZ4HC=y
CONFIG_F2FS_FS_ZSTD=y
CONFIG_F2FS_IOSTAT=y
# CONFIG_F2FS_UNFAIR_RWSEM is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
# CONFIG_FS_ENCRYPTION_INLINE_CRYPT is not set
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=m
# CONFIG_QFMT_V1 is not set
# CONFIG_QFMT_V2 is not set
CONFIG_QUOTACTL=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_VIRTIO_FS=m
CONFIG_FUSE_PASSTHROUGH=y
CONFIG_FUSE_IO_URING=y
CONFIG_OVERLAY_FS=y
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set
# CONFIG_OVERLAY_FS_DEBUG is not set

#
# Caches
#
CONFIG_NETFS_SUPPORT=m
# CONFIG_NETFS_STATS is not set
# CONFIG_NETFS_DEBUG is not set
CONFIG_FSCACHE=y
# CONFIG_FSCACHE_STATS is not set
CONFIG_CACHEFILES=m
# CONFIG_CACHEFILES_DEBUG is not set
# CONFIG_CACHEFILES_ERROR_INJECTION is not set
# CONFIG_CACHEFILES_ONDEMAND is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
# CONFIG_FAT_DEFAULT_UTF8 is not set
CONFIG_EXFAT_FS=y
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_NTFS3_FS=m
# CONFIG_NTFS3_64BIT_CLUSTER is not set
CONFIG_NTFS3_LZX_XPRESS=y
CONFIG_NTFS3_FS_POSIX_ACL=y
# CONFIG_NTFS_FS is not set
# end of DOS/FAT/EXFAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_TMPFS_INODE64 is not set
# CONFIG_TMPFS_QUOTA is not set
CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_HUGETLB_PMD_PAGE_TABLE_SHARING=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=m
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
CONFIG_ECRYPT_FS=m
# CONFIG_ECRYPT_FS_MESSAGING is not set
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
CONFIG_UBIFS_FS=m
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
CONFIG_CRAMFS=m
CONFIG_CRAMFS_BLOCKDEV=y
# CONFIG_CRAMFS_MTD is not set
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_FILE_CACHE is not set
CONFIG_SQUASHFS_FILE_DIRECT=y
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set
CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
CONFIG_SQUASHFS_XATTR=y
# CONFIG_SQUASHFS_COMP_CACHE_FULL is not set
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_ZSTD=y
# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
CONFIG_PSTORE_COMPRESS=y
# CONFIG_PSTORE_CONSOLE is not set
# CONFIG_PSTORE_PMSG is not set
# CONFIG_PSTORE_RAM is not set
# CONFIG_PSTORE_BLK is not set
# CONFIG_UFS_FS is not set
CONFIG_EROFS_FS=m
# CONFIG_EROFS_FS_DEBUG is not set
CONFIG_EROFS_FS_XATTR=y
CONFIG_EROFS_FS_POSIX_ACL=y
# CONFIG_EROFS_FS_SECURITY is not set
CONFIG_EROFS_FS_BACKED_BY_FILE=y
CONFIG_EROFS_FS_ZIP=y
CONFIG_EROFS_FS_ZIP_LZMA=y
# CONFIG_EROFS_FS_ZIP_DEFLATE is not set
# CONFIG_EROFS_FS_ZIP_ZSTD is not set
# CONFIG_EROFS_FS_ZIP_ACCEL is not set
# CONFIG_EROFS_FS_ONDEMAND is not set
# CONFIG_EROFS_FS_PCPU_KTHREAD is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V2=m
CONFIG_NFS_V3=m
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=m
# CONFIG_NFS_SWAP is not set
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=m
CONFIG_PNFS_BLOCK=m
CONFIG_PNFS_FLEXFILE_LAYOUT=m
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
# CONFIG_NFS_V4_1_MIGRATION is not set
CONFIG_NFS_V4_SECURITY_LABEL=y
CONFIG_NFS_FSCACHE=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DEBUG=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
CONFIG_NFS_V4_2_READ_PLUS=y
CONFIG_NFSD=m
# CONFIG_NFSD_V2 is not set
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
CONFIG_NFSD_PNFS=y
CONFIG_NFSD_BLOCKLAYOUT=y
CONFIG_NFSD_SCSILAYOUT=y
CONFIG_NFSD_FLEXFILELAYOUT=y
CONFIG_NFSD_V4_2_INTER_SSC=y
CONFIG_NFSD_V4_SECURITY_LABEL=y
# CONFIG_NFSD_LEGACY_CLIENT_TRACKING is not set
# CONFIG_NFSD_V4_DELEG_TIMESTAMPS is not set
CONFIG_GRACE_PERIOD=m
CONFIG_LOCKD=m
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=m
CONFIG_NFS_COMMON=y
# CONFIG_NFS_LOCALIO is not set
CONFIG_NFS_V4_2_SSC_HELPER=y
CONFIG_SUNRPC=m
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_BACKCHANNEL=y
CONFIG_RPCSEC_GSS_KRB5=m
CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y
CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA=y
CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y
CONFIG_SUNRPC_DEBUG=y
# CONFIG_SUNRPC_DEBUG_TRACE is not set
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
# CONFIG_CEPH_FS_SECURITY_LABEL is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CIFS_DEBUG=y
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
CONFIG_CIFS_DFS_UPCALL=y
# CONFIG_CIFS_SWN_UPCALL is not set
# CONFIG_CIFS_FSCACHE is not set
# CONFIG_CIFS_COMPRESSION is not set
CONFIG_SMB_SERVER=m
CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
CONFIG_SMB_SERVER_KERBEROS5=y
CONFIG_SMBFS=m
CONFIG_CODA_FS=m
CONFIG_AFS_FS=m
# CONFIG_AFS_DEBUG is not set
CONFIG_AFS_FSCACHE=y
# CONFIG_AFS_DEBUG_CURSOR is not set
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
CONFIG_9P_FS_SECURITY=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf-8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=m
CONFIG_NLS_MAC_GAELIC=m
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=y
CONFIG_NLS_UCS2_UTILS=m
CONFIG_DLM=m
# CONFIG_DLM_DEBUG is not set
# CONFIG_UNICODE is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_BIG_KEYS is not set
# CONFIG_TRUSTED_KEYS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_PROC_MEM_ALWAYS_FORCE=y
# CONFIG_PROC_MEM_FORCE_PTRACE is not set
# CONFIG_PROC_MEM_NO_FORCE is not set
# CONFIG_MSEAL_SYSTEM_MAPPINGS is not set
CONFIG_SECURITY=y
CONFIG_HAS_SECURITY_AUDIT=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
# CONFIG_SECURITY_NETWORK_XFRM is not set
CONFIG_SECURITY_PATH=y
CONFIG_LSM_MMAP_MIN_ADDR=32768
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
# CONFIG_SECURITY_SELINUX_DEBUG is not set
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
CONFIG_SECURITY_APPARMOR=y
# CONFIG_SECURITY_APPARMOR_DEBUG is not set
CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y
CONFIG_SECURITY_APPARMOR_HASH=y
CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y
CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
# CONFIG_SECURITY_LANDLOCK is not set
# CONFIG_SECURITY_IPE is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
CONFIG_INTEGRITY_AUDIT=y
# CONFIG_IMA is not set
# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
# CONFIG_EVM is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
CONFIG_INIT_STACK_NONE=y
# CONFIG_INIT_STACK_ALL_PATTERN is not set
# CONFIG_INIT_STACK_ALL_ZERO is not set
# CONFIG_KSTACK_ERASE is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
# CONFIG_ZERO_CALL_USED_REGS is not set
# end of Memory initialization

#
# Bounds checking
#
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_HARDENED_USERCOPY is not set
# end of Bounds checking

#
# Hardening of kernel data structures
#
# CONFIG_LIST_HARDENED is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# end of Hardening of kernel data structures

CONFIG_RANDSTRUCT_NONE=y
# CONFIG_RANDSTRUCT_FULL is not set
# CONFIG_RANDSTRUCT_PERFORMANCE is not set
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=y
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SIG=y
CONFIG_CRYPTO_SIG2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=y
# CONFIG_CRYPTO_SELFTESTS is not set
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_KRB5ENC=m
# CONFIG_CRYPTO_BENCHMARK is not set
CONFIG_CRYPTO_ENGINE=y
# end of Crypto core or helper

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=y
# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
CONFIG_CRYPTO_ECDSA=y
CONFIG_CRYPTO_ECRDSA=y
# end of Public-key cryptography

#
# Block ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
CONFIG_CRYPTO_ANUBIS=y
CONFIG_CRYPTO_ARIA=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_BLOWFISH_COMMON=y
CONFIG_CRYPTO_CAMELLIA=y
CONFIG_CRYPTO_CAST_COMMON=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=y
CONFIG_CRYPTO_KHAZAD=y
CONFIG_CRYPTO_SEED=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_GENERIC=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y
# end of Block ciphers

#
# Length-preserving ciphers and modes
#
CONFIG_CRYPTO_ADIANTUM=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HCTR2=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XCTR=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_NHPOLY1305=y
# end of Length-preserving ciphers and modes

#
# AEAD (authenticated encryption with associated data) ciphers
#
CONFIG_CRYPTO_AEGIS128=y
CONFIG_CRYPTO_AEGIS128_SIMD=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_GENIV=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_ESSIV=y
# end of AEAD (authenticated encryption with associated data) ciphers

#
# Hashes, digests, and MACs
#
CONFIG_CRYPTO_BLAKE2B=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_POLYVAL=y
CONFIG_CRYPTO_RMD160=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3_GENERIC=y
CONFIG_CRYPTO_STREEBOG=y
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_XXHASH=y
# end of Hashes, digests, and MACs

#
# CRCs (cyclic redundancy checks)
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
# end of CRCs (cyclic redundancy checks)

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=y
CONFIG_CRYPTO_ZSTD=y
# end of Compression

#
# Random number generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32
CONFIG_CRYPTO_JITTERENTROPY_OSR=1
# end of Random number generation

#
# Userspace interface
#
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
# end of Userspace interface

CONFIG_CRYPTO_NHPOLY1305_NEON=y

#
# Accelerated Cryptographic Algorithms for CPU (arm64)
#
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_SHA3_ARM64=y
CONFIG_CRYPTO_SM3_NEON=y
CONFIG_CRYPTO_SM3_ARM64_CE=y
CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CRYPTO_SM4_ARM64_CE=y
CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y
CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y
# end of Accelerated Cryptographic Algorithms for CPU (arm64)

CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_ALLWINNER=y
CONFIG_CRYPTO_DEV_SUN4I_SS=y
CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set
CONFIG_CRYPTO_DEV_SUN8I_CE=y
CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG=y
CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
CONFIG_CRYPTO_DEV_SUN8I_SS=y
CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG=y
CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_CCP is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set
# CONFIG_CRYPTO_DEV_QAT_C62X is not set
# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
# CONFIG_CRYPTO_DEV_QAT_420XX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set
# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set
CONFIG_CRYPTO_DEV_ROCKCHIP=m
# CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG is not set
CONFIG_CRYPTO_DEV_VIRTIO=m
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
CONFIG_CRYPTO_DEV_CCREE=y
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
# CONFIG_CRYPTO_DEV_HISI_TRNG is not set
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG=y
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
CONFIG_PKCS7_MESSAGE_PARSER=y
CONFIG_PKCS7_TEST_KEY=m
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
# CONFIG_FIPS_SIGNATURE_SELFTEST is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

CONFIG_CRYPTO_KRB5=m
# CONFIG_CRYPTO_KRB5_SELFTESTS is not set
CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_RAID6_PQ=y
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=m
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
CONFIG_INDIRECT_PIO=y
# CONFIG_TRACE_MMIO_ACCESS is not set
CONFIG_CRC7=m
CONFIG_CRC8=m
CONFIG_CRC16=y
CONFIG_CRC_CCITT=y
CONFIG_CRC_ITU_T=m
CONFIG_CRC_T10DIF=y
CONFIG_CRC_T10DIF_ARCH=y
CONFIG_CRC32=y
CONFIG_CRC32_ARCH=y
CONFIG_CRC64=y
CONFIG_CRC_OPTIMIZATIONS=y

#
# Crypto library routines
#
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CHACHA_ARCH=y
CONFIG_CRYPTO_LIB_CURVE25519=m
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_MD5=y
CONFIG_CRYPTO_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_POLY1305_ARCH=y
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA1_ARCH=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LIB_SHA256_ARCH=y
CONFIG_CRYPTO_LIB_SHA512=y
CONFIG_CRYPTO_LIB_SHA512_ARCH=y
CONFIG_CRYPTO_LIB_SM3=y
# end of Crypto library routines

CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
CONFIG_RANDOM32_SELFTEST=y
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_ARM64=y
# CONFIG_XZ_DEC_SPARC is not set
CONFIG_XZ_DEC_RISCV=y
CONFIG_XZ_DEC_MICROLZMA=y
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_INTERVAL_TREE=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_CLOSURES=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS_HELPERS=y
CONFIG_NEED_SG_DMA_FLAGS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED=y
CONFIG_SWIOTLB=y
# CONFIG_SWIOTLB_DYNAMIC is not set
CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
CONFIG_DMA_NEED_SYNC=y
# CONFIG_DMA_RESTRICTED_POOL is not set
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=256
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_DMA_MAP_BENCHMARK is not set
CONFIG_SGL_ALLOC=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_DIMLIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_VDSO_GETRANDOM=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_ARCH_HAS_PMEM_API=y
CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_STACKDEPOT=y
CONFIG_STACKDEPOT_MAX_FRAMES=64
CONFIG_SBITMAP=y
# CONFIG_LWQ_TEST is not set
# end of Library routines

CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_FIRMWARE_TABLE=y
CONFIG_UNION_FIND=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_CALLER is not set
# CONFIG_STACKTRACE_BUILD_ID is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
CONFIG_AS_HAS_NON_CONST_ULEB128=y
# CONFIG_DEBUG_INFO_NONE is not set
# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
CONFIG_DEBUG_INFO_DWARF5=y
# CONFIG_DEBUG_INFO_REDUCED is not set
CONFIG_DEBUG_INFO_COMPRESSED_NONE=y
# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set
# CONFIG_DEBUG_INFO_COMPRESSED_ZSTD is not set
# CONFIG_DEBUG_INFO_SPLIT is not set
CONFIG_DEBUG_INFO_BTF=y
CONFIG_PAHOLE_HAS_SPLIT_BTF=y
CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
CONFIG_DEBUG_INFO_BTF_MODULES=y
CONFIG_MODULE_ALLOW_BTF_MISMATCH=y
# CONFIG_GDB_SCRIPTS is not set
CONFIG_FRAME_WARN=2048
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_READABLE_ASM is not set
CONFIG_HEADERS_INSTALL=y
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_VMLINUX_MAP is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_ARCH_KCSAN=y
CONFIG_HAVE_KCSAN_COMPILER=y
# CONFIG_KCSAN is not set
# end of Generic Kernel Debugging Instruments

#
# Networking Debugging
#
# CONFIG_NET_DEV_REFCNT_TRACKER is not set
# CONFIG_NET_NS_REFCNT_TRACKER is not set
# CONFIG_DEBUG_NET is not set
# CONFIG_DEBUG_NET_SMALL_RTNL is not set
# end of Networking Debugging

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_SLUB_DEBUG=y
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_ARCH_HAS_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_PER_VMA_LOCK_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SHRINKER_DEBUG is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
# CONFIG_DEBUG_VFS is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
# CONFIG_MEM_ALLOC_PROFILING is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
# end of Memory Debugging

# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SOFTLOCKUP_DETECTOR is not set
CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y
# CONFIG_HARDLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_DETECT_HUNG_TASK_BLOCKER=y
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
CONFIG_SCHED_INFO=y
# CONFIG_SCHEDSTATS is not set
# end of Scheduler Debugging

# CONFIG_DEBUG_PREEMPT is not set

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

# CONFIG_DEBUG_IRQFLAGS is not set
CONFIG_STACKTRACE=y
# CONFIG_DEBUG_KOBJECT is not set

#
# Debug kernel data structures
#
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CLOSURES is not set
# CONFIG_DEBUG_MAPLE_TREE is not set
# end of Debug kernel data structures

#
# RCU Debugging
#
# CONFIG_RCU_SCALE_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
# CONFIG_RCU_CPU_STALL_CPUTIME is not set
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_LATENCYTOP is not set
# CONFIG_DEBUG_CGROUP_REF is not set
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_FREGS=y
CONFIG_HAVE_FTRACE_GRAPH_FUNC=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_EXTRA_IPI_TRACEPOINTS=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_TRACING=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
CONFIG_TRACEFS_AUTOMOUNT_DEPRECATED=y
# CONFIG_BOOTTIME_TRACING is not set
# CONFIG_FUNCTION_TRACER is not set
CONFIG_FUNCTION_TRACE_ARGS=y
# CONFIG_STACK_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_PREEMPT_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_HWLAT_TRACER is not set
# CONFIG_OSNOISE_TRACER is not set
# CONFIG_TIMERLAT_TRACER is not set
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
# CONFIG_FTRACE_SYSCALLS is not set
# CONFIG_TRACER_SNAPSHOT is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_PROBE_EVENTS_BTF_ARGS=y
CONFIG_KPROBE_EVENTS=y
CONFIG_UPROBE_EVENTS=y
CONFIG_EPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_DYNAMIC_EVENTS=y
CONFIG_PROBE_EVENTS=y
# CONFIG_SYNTH_EVENTS is not set
# CONFIG_USER_EVENTS is not set
# CONFIG_HIST_TRIGGERS is not set
# CONFIG_TRACE_EVENT_INJECT is not set
# CONFIG_TRACEPOINT_BENCHMARK is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_TRACE_EVAL_MAP_FILE is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
# CONFIG_KPROBE_EVENT_GEN_TEST is not set
# CONFIG_RV is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y
CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y
# CONFIG_STRICT_DEVMEM is not set

#
# arm64 Debugging
#
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_DEBUG_EFI is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
# end of arm64 Debugging

#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FUNCTION_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
# CONFIG_KCOV is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_TEST_DHRY is not set
# CONFIG_LKDTM is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_DIV64 is not set
# CONFIG_TEST_MULDIV64 is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TEST_REF_TRACKER is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_ASYNC_RAID6_TEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_MAPLE_TREE is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_VMALLOC is not set
CONFIG_TEST_BPF=m
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_DYNAMIC_DEBUG is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_KALLSYMS is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_FREE_PAGES is not set
# CONFIG_TEST_FPU is not set
# CONFIG_TEST_OBJPOOL is not set
CONFIG_ARCH_USE_MEMTEST=y
CONFIG_MEMTEST=y
# end of Kernel Testing and Coverage

#
# Rust hacking
#
# end of Rust hacking
# end of Kernel hacking

CONFIG_IO_URING_ZCRX=y


================================================
FILE: kernel-config/release/stable/config-6.6
================================================
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 6.6.130 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc (Arm GNU Toolchain 15.2.Rel1 (Build arm-15.86)) 15.2.1 20251203"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=150201
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=24501
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=24501
CONFIG_LLD_VERSION=0
CONFIG_CC_CAN_LINK=y
CONFIG_CC_CAN_LINK_STATIC=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
CONFIG_TOOLS_SUPPORT_RELR=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_CC_HAS_COUNTED_BY=y
CONFIG_PAHOLE_VERSION=130
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
# CONFIG_COMPILE_TEST is not set
# CONFIG_WERROR is not set
# CONFIG_UAPI_HEADER_TEST is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
# CONFIG_WATCH_QUEUE is not set
# CONFIG_CROSS_MEMORY_ATTACH is not set
# CONFIG_USELIB is not set
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_SIM=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem

CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_HZ_PERIODIC=y
# CONFIG_NO_HZ_IDLE is not set
# CONFIG_NO_HZ_FULL is not set
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

CONFIG_BPF=y
CONFIG_HAVE_EBPF_JIT=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y

#
# BPF subsystem
#
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_JIT=y
# CONFIG_BPF_JIT_ALWAYS_ON is not set
CONFIG_BPF_JIT_DEFAULT_ON=y
# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
# CONFIG_BPF_PRELOAD is not set
# CONFIG_BPF_LSM is not set
# end of BPF subsystem

CONFIG_PREEMPT_VOLUNTARY_BUILD=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
# CONFIG_PREEMPT_DYNAMIC is not set

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_SCHED_THERMAL_PRESSURE=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
# CONFIG_PRINTK_INDEX is not set
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
# CONFIG_UCLAMP_TASK is not set
# end of Scheduler features

CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
CONFIG_CC_HAS_INT128=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_GCC10_NO_ARRAY_BOUNDS=y
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_SCHED_MM_CID=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
CONFIG_CGROUP_MISC=y
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_TIME_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
# CONFIG_CHECKPOINT_RESTORE is not set
CONFIG_SCHED_AUTOGROUP=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
# CONFIG_BOOT_CONFIG_FORCE is not set
# CONFIG_BOOT_CONFIG_EMBED is not set
CONFIG_INITRAMFS_PRESERVE_MTIME=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_SELFTEST is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
CONFIG_CACHESTAT_SYSCALL=y
# CONFIG_DEBUG_RSEQ is not set
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_GUEST_PERF_EVENTS=y
# CONFIG_PC104 is not set

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y

#
# Kexec and crash features
#
# CONFIG_KEXEC_FILE is not set
# CONFIG_CRASH_DUMP is not set
# end of Kexec and crash features
# end of General setup

CONFIG_ARM64=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_CONT_PTE_SHIFT=4
CONFIG_ARM64_CONT_PMD_SHIFT=4
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y

#
# Platform selection
#
# CONFIG_ARCH_ACTIONS is not set
CONFIG_ARCH_SUNXI=y
# CONFIG_ARCH_ALPINE is not set
# CONFIG_ARCH_APPLE is not set
# CONFIG_ARCH_BCM is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SPARX5 is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_LG1K is not set
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_KEEMBAY is not set
# CONFIG_ARCH_MEDIATEK is not set
CONFIG_ARCH_MESON=y
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_NXP is not set
# CONFIG_ARCH_MA35 is not set
# CONFIG_ARCH_NPCM is not set
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
# CONFIG_ARCH_RENESAS is not set
CONFIG_ARCH_ROCKCHIP=y
# CONFIG_ARCH_SEATTLE is not set
# CONFIG_ARCH_INTEL_SOCFPGA is not set
# CONFIG_ARCH_STM32 is not set
# CONFIG_ARCH_SYNQUACER is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_VISCONTI is not set
# CONFIG_ARCH_XGENE is not set
# CONFIG_ARCH_ZYNQMP is not set
# end of Platform selection

#
# Kernel Features
#

#
# ARM errata workarounds via the alternatives framework
#
CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_834220=y
CONFIG_ARM64_ERRATUM_1742098=y
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1319367=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_ERRATUM_2441007=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_ARM64_ERRATUM_2051678=y
CONFIG_ARM64_ERRATUM_2077057=y
CONFIG_ARM64_ERRATUM_2658417=y
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
CONFIG_ARM64_ERRATUM_2054223=y
CONFIG_ARM64_ERRATUM_2067961=y
CONFIG_ARM64_ERRATUM_2441009=y
CONFIG_ARM64_ERRATUM_2457168=y
CONFIG_ARM64_ERRATUM_2645198=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y
CONFIG_ARM64_ERRATUM_2966298=y
CONFIG_ARM64_ERRATUM_3117295=y
CONFIG_ARM64_ERRATUM_3194386=y
CONFIG_CAVIUM_ERRATUM_22375=y
CONFIG_CAVIUM_ERRATUM_23154=y
CONFIG_CAVIUM_ERRATUM_27456=y
CONFIG_CAVIUM_ERRATUM_30115=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
CONFIG_QCOM_FALKOR_ERRATUM_1009=y
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
CONFIG_ROCKCHIP_ERRATUM_3588001=y
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
CONFIG_ROCKCHIP_ERRATUM_114514=y
# end of ARM errata workarounds via the alternatives framework

CONFIG_ARM64_4K_PAGES=y
# CONFIG_ARM64_16K_PAGES is not set
# CONFIG_ARM64_64K_PAGES is not set
CONFIG_ARM64_VA_BITS_39=y
# CONFIG_ARM64_VA_BITS_48 is not set
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SCHED_MC=y
CONFIG_SCHED_CLUSTER=y
# CONFIG_SCHED_SMT is not set
CONFIG_NR_CPUS=8
# CONFIG_HOTPLUG_CPU is not set
# CONFIG_NUMA is not set
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
CONFIG_SCHED_HRTICK=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y
CONFIG_ARCH_SUPPORTS_KEXEC_SIG=y
CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG=y
CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y
# CONFIG_XEN is not set
CONFIG_ARCH_FORCE_MAX_ORDER=10
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
CONFIG_KUSER_HELPERS=y
# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
CONFIG_ARMV8_DEPRECATED=y
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y

#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_PAN=y
CONFIG_AS_HAS_LSE_ATOMICS=y
# CONFIG_ARM64_USE_LSE_ATOMICS is not set
# end of ARMv8.1 architectural features

#
# ARMv8.2 architectural features
#
CONFIG_AS_HAS_ARMV8_2=y
CONFIG_AS_HAS_SHA3=y
# CONFIG_ARM64_PMEM is not set
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features

#
# ARMv8.3 architectural features
#
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
CONFIG_AS_HAS_ARMV8_3=y
CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
CONFIG_AS_HAS_LDAPR=y
# end of ARMv8.3 architectural features

#
# ARMv8.4 architectural features
#
CONFIG_ARM64_AMU_EXTN=y
CONFIG_AS_HAS_ARMV8_4=y
CONFIG_ARM64_TLB_RANGE=y
# end of ARMv8.4 architectural features

#
# ARMv8.5 architectural features
#
CONFIG_AS_HAS_ARMV8_5=y
CONFIG_ARM64_BTI=y
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARM64_AS_HAS_MTE=y
CONFIG_ARM64_MTE=y
# end of ARMv8.5 architectural features

#
# ARMv8.7 architectural features
#
CONFIG_ARM64_EPAN=y
# end of ARMv8.7 architectural features

CONFIG_ARM64_SVE=y
CONFIG_ARM64_PSEUDO_NMI=y
# CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
# end of Kernel Features

#
# Boot options
#
CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
CONFIG_CMDLINE=""
CONFIG_EFI_STUB=y
CONFIG_EFI=y
CONFIG_DMI=y
# end of Boot options

#
# Power management options
#
# CONFIG_SUSPEND is not set
# CONFIG_HIBERNATION is not set
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ENERGY_MODEL=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options

#
# CPU Power Management
#

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_IDLE_GOV_LADDER=y
# CONFIG_CPU_IDLE_GOV_MENU is not set
# CONFIG_CPU_IDLE_GOV_TEO is not set
CONFIG_DT_IDLE_STATES=y
CONFIG_DT_IDLE_GENPD=y

#
# ARM CPU Idle Drivers
#
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
# end of ARM CPU Idle Drivers
# end of CPU Idle

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_STAT is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_USERSPACE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
# CONFIG_ACPI_CPPC_CPUFREQ is not set
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_SCMI_CPUFREQ=y
# end of CPU Frequency scaling
# end of CPU Power Management

CONFIG_ARCH_SUPPORTS_ACPI=y
CONFIG_ACPI=y
CONFIG_ACPI_GENERIC_GSI=y
CONFIG_ACPI_CCA_REQUIRED=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_SPCR_TABLE=y
# CONFIG_ACPI_FPDT is not set
CONFIG_ACPI_EC_DEBUGFS=m
CONFIG_ACPI_AC=m
CONFIG_ACPI_BATTERY=m
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_VIDEO=m
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_MCFG=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_THERMAL=y
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_PCI_SLOT=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_CUSTOM_METHOD=m
CONFIG_ACPI_BGRT=y
CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
CONFIG_HAVE_ACPI_APEI=y
CONFIG_ACPI_APEI=y
CONFIG_ACPI_APEI_GHES=y
CONFIG_ACPI_APEI_SEA=y
CONFIG_ACPI_APEI_MEMORY_FAILURE=y
CONFIG_ACPI_APEI_EINJ=m
CONFIG_ACPI_APEI_ERST_DEBUG=m
CONFIG_ACPI_CONFIGFS=m
CONFIG_ACPI_PFRUT=m
CONFIG_ACPI_IORT=y
CONFIG_ACPI_GTDT=y
# CONFIG_ACPI_AGDI is not set
CONFIG_ACPI_APMT=y
CONFIG_ACPI_PPTT=y
# CONFIG_ACPI_FFH is not set
CONFIG_PMIC_OPREGION=y
CONFIG_ACPI_VIOT=y
CONFIG_ACPI_PRMT=y
CONFIG_IRQ_BYPASS_MANAGER=y
CONFIG_HAVE_KVM=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_DIRTY_RING=y
CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y
CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_MMIO=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_KVM_XFER_TO_GUEST_WORK=y
CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
# CONFIG_NVHE_EL2_DEBUG is not set
CONFIG_CPU_MITIGATIONS=y

#
# General architecture-dependent options
#
CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
CONFIG_UPROBES=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_EVENTS_NMI=y
CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
# CONFIG_SECCOMP_CACHE_DEBUG is not set
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
# CONFIG_SHADOW_CALL_STACK is not set
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
CONFIG_HAVE_CONTEXT_TRACKING_USER=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_ARCH_HUGE_VMALLOC=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_WANT_PMD_MKWRITE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_HAVE_ARCH_VMAP_STACK=y
CONFIG_VMAP_STACK=y
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET=y
# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
CONFIG_RELR=y
CONFIG_HAVE_PREEMPT_DYNAMIC=y
CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FUNCTION_ALIGNMENT=4
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_DEBUG is not set
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
CONFIG_MODULE_COMPRESS_NONE=y
# CONFIG_MODULE_COMPRESS_GZIP is not set
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BLK_RQ_ALLOC_TIME=y
CONFIG_BLK_CGROUP_RWSTAT=y
CONFIG_BLK_CGROUP_PUNT_BIO=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_ICQ=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=y
# CONFIG_BLK_DEV_ZONED is not set
CONFIG_BLK_DEV_THROTTLING=y
# CONFIG_BLK_DEV_THROTTLING_LOW is not set
CONFIG_BLK_WBT=y
CONFIG_BLK_WBT_MQ=y
CONFIG_BLK_CGROUP_IOLATENCY=y
CONFIG_BLK_CGROUP_IOCOST=y
CONFIG_BLK_CGROUP_IOPRIO=y
# CONFIG_BLK_DEBUG_FS is not set
CONFIG_BLK_SED_OPAL=y
CONFIG_BLK_INLINE_ENCRYPTION=y
CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_AIX_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
# CONFIG_CMDLINE_PARTITION is not set
CONFIG_AMLOGIC_PARTITION=y
# end of Partition Types

CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_HOLDER_DEPRECATED=y
CONFIG_BLK_MQ_STACKING=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
# CONFIG_BFQ_CGROUP_DEBUG is not set
# end of IO Schedulers

CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y
CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK=y
CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_READ_LOCK=y
CONFIG_ARCH_INLINE_READ_LOCK_BH=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_READ_UNLOCK=y
CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_INLINE_WRITE_LOCK=y
CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_SPIN_TRYLOCK=y
CONFIG_INLINE_SPIN_TRYLOCK_BH=y
CONFIG_INLINE_SPIN_LOCK=y
CONFIG_INLINE_SPIN_LOCK_BH=y
CONFIG_INLINE_SPIN_LOCK_IRQ=y
CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y
CONFIG_INLINE_SPIN_UNLOCK_BH=y
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_READ_LOCK=y
CONFIG_INLINE_READ_LOCK_BH=y
CONFIG_INLINE_READ_LOCK_IRQ=y
CONFIG_INLINE_READ_LOCK_IRQSAVE=y
CONFIG_INLINE_READ_UNLOCK=y
CONFIG_INLINE_READ_UNLOCK_BH=y
CONFIG_INLINE_READ_UNLOCK_IRQ=y
CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y
CONFIG_INLINE_WRITE_LOCK=y
CONFIG_INLINE_WRITE_LOCK_BH=y
CONFIG_INLINE_WRITE_LOCK_IRQ=y
CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y
CONFIG_INLINE_WRITE_UNLOCK=y
CONFIG_INLINE_WRITE_UNLOCK_BH=y
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_HAVE_ELF_PROT=y
CONFIG_ARCH_USE_GNU_PROPERTY=y
CONFIG_ELFCORE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_BINFMT_SCRIPT=y
CONFIG_BINFMT_MISC=m
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#
CONFIG_ZPOOL=y
CONFIG_SWAP=y
CONFIG_ZSWAP=y
CONFIG_ZSWAP_DEFAULT_ON=y
# CONFIG_ZSWAP_EXCLUSIVE_LOADS_DEFAULT_ON is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD_DEPRECATED is not set
# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
CONFIG_ZBUD=y
# CONFIG_Z3FOLD_DEPRECATED is not set
CONFIG_ZSMALLOC=y
# CONFIG_ZSMALLOC_STAT is not set
CONFIG_ZSMALLOC_CHAIN_SIZE=8

#
# SLAB allocator options
#
# CONFIG_SLAB_DEPRECATED is not set
CONFIG_SLUB=y
# CONFIG_SLUB_TINY is not set
CONFIG_SLAB_MERGE_DEFAULT=y
CONFIG_SLAB_FREELIST_RANDOM=y
CONFIG_SLAB_FREELIST_HARDENED=y
# CONFIG_SLUB_STATS is not set
CONFIG_SLUB_CPU_PARTIAL=y
# CONFIG_RANDOM_KMALLOC_CACHES is not set
# end of SLAB allocator options

CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
CONFIG_ARCH_ENABLE_THP_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PCP_BATCH_SCALE_MAX=5
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_MMU_NOTIFIER=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
CONFIG_MEMORY_FAILURE=y
# CONFIG_HWPOISON_INJECT is not set
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_TRANSPARENT_HUGEPAGE=y
# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set
CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
CONFIG_THP_SWAP=y
# CONFIG_READ_ONLY_THP_FOR_FS is not set
CONFIG_CMA=y
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_CMA_AREAS=7
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_ARCH_HAS_ZONE_DMA_SET=y
CONFIG_ZONE_DMA=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
CONFIG_ARCH_USES_PG_ARCH_X=y
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_TEST is not set
# CONFIG_DMAPOOL_TEST is not set
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_MEMFD_CREATE=y
CONFIG_SECRETMEM=y
# CONFIG_ANON_VMA_NAME is not set
# CONFIG_USERFAULTFD is not set
CONFIG_LRU_GEN=y
CONFIG_LRU_GEN_ENABLED=y
# CONFIG_LRU_GEN_STATS is not set
CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y
CONFIG_PER_VMA_LOCK=y
CONFIG_LOCK_MM_AND_FIND_VMA=y

#
# Data Access Monitoring
#
# CONFIG_DAMON is not set
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_XGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_EXTENSIONS=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_AF_UNIX_OOB=y
CONFIG_UNIX_DIAG=y
CONFIG_TLS=m
CONFIG_TLS_DEVICE=y
CONFIG_TLS_TOE=y
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
CONFIG_XFRM_INTERFACE=m
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_AH=y
CONFIG_XFRM_ESP=y
CONFIG_XFRM_IPCOMP=y
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_XFRM_ESPINTCP=y
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=y
CONFIG_NET_HANDSHAKE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
# CONFIG_IP_FIB_TRIE_STATS is not set
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_ROUTE_CLASSID=y
# CONFIG_IP_PNP is not set
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=y
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=y
CONFIG_NET_FOU=y
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
CONFIG_INET_ESP_OFFLOAD=m
# CONFIG_INET_ESPINTCP is not set
CONFIG_INET_IPCOMP=y
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=y
CONFIG_INET_TUNNEL=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
CONFIG_INET_UDP_DIAG=y
CONFIG_INET_RAW_DIAG=y
# CONFIG_INET_DIAG_DESTROY is not set
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_NV=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_CONG_DCTCP=m
CONFIG_TCP_CONG_CDG=m
CONFIG_TCP_CONG_BBR=m
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_ESP_OFFLOAD=m
CONFIG_INET6_ESPINTCP=y
CONFIG_INET6_IPCOMP=y
CONFIG_IPV6_MIP6=m
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=y
CONFIG_INET6_TUNNEL=y
CONFIG_IPV6_VTI=m
CONFIG_IPV6_SIT=y
# CONFIG_IPV6_SIT_6RD is not set
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=y
CONFIG_IPV6_GRE=m
CONFIG_IPV6_FOU=y
CONFIG_IPV6_FOU_TUNNEL=y
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
CONFIG_IPV6_SEG6_LWTUNNEL=y
CONFIG_IPV6_SEG6_HMAC=y
CONFIG_IPV6_SEG6_BPF=y
CONFIG_IPV6_RPL_LWTUNNEL=y
# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
# CONFIG_NETLABEL is not set
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=y
CONFIG_MPTCP_IPV6=y
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_EGRESS=y
CONFIG_NETFILTER_SKIP_EGRESS=y
CONFIG_NETFILTER_NETLINK=m
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
CONFIG_NETFILTER_BPF_LINK=y
# CONFIG_NETFILTER_NETLINK_HOOK is not set
CONFIG_NETFILTER_NETLINK_ACCT=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NETFILTER_NETLINK_OSF=m
CONFIG_NF_CONNTRACK=y
CONFIG_NF_LOG_SYSLOG=m
CONFIG_NETFILTER_CONNCOUNT=m
CONFIG_NF_CONNTRACK_MARK=y
# CONFIG_NF_CONNTRACK_SECMARK is not set
CONFIG_NF_CONNTRACK_ZONES=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_CHAIN_EVENTS=y
CONFIG_NF_CONNTRACK_TIMEOUT=y
CONFIG_NF_CONNTRACK_TIMESTAMP=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CONNTRACK_OVS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_CT_NETLINK_TIMEOUT=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=m
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NF_NAT_OVS=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=m
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_FULLCONE=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
CONFIG_NFT_OSF=m
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NF_DUP_NETDEV=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NFT_REJECT_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
# CONFIG_NF_FLOW_TABLE_PROCFS is not set
CONFIG_NETFILTER_XTABLES=m
# CONFIG_NETFILTER_XTABLES_COMPAT is not set

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=m
CONFIG_NETFILTER_XT_CONNMARK=m
CONFIG_NETFILTER_XT_SET=m

#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_AUDIT=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LED=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=m
CONFIG_NETFILTER_XT_TARGET_NETMAP=m
CONFIG_NETFILTER_XT_TARGET_FULLCONENAT=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD=m
CONFIG_NETFILTER_XT_TARGET_RATEEST=m
CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
CONFIG_NETFILTER_XT_TARGET_SECMARK=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=m
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# end of Core Netfilter Configuration

CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
# CONFIG_IP_VS_DEBUG is not set
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m
# CONFIG_IP_VS_TWOS is not set

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_SOCKET_IPV4=m
CONFIG_NF_TPROXY_IPV4=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=m
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_FULLCONENAT=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
# CONFIG_IP_NF_SECURITY is not set
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
# CONFIG_IP6_NF_SECURITY is not set
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=y
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_NFT_BRIDGE_META=m
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
# CONFIG_BPFILTER is not set
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m

#
# DCCP CCIDs Configuration
#
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
CONFIG_IP_DCCP_CCID3=y
# CONFIG_IP_DCCP_CCID3_DEBUG is not set
CONFIG_IP_DCCP_TFRC_LIB=y
# end of DCCP CCIDs Configuration

#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
# end of DCCP Kernel Hacking

CONFIG_IP_SCTP=m
CONFIG_SCTP_DBG_OBJCNT=y
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=m
CONFIG_RDS=m
CONFIG_RDS_TCP=m
# CONFIG_RDS_DEBUG is not set
CONFIG_TIPC=m
CONFIG_TIPC_MEDIA_UDP=y
CONFIG_TIPC_CRYPTO=y
CONFIG_TIPC_DIAG=m
# CONFIG_ATM is not set
CONFIG_L2TP=m
CONFIG_L2TP_DEBUGFS=m
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=m
CONFIG_L2TP_ETH=m
CONFIG_STP=y
CONFIG_GARP=m
CONFIG_MRP=m
CONFIG_BRIDGE=y
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_BRIDGE_MRP=y
CONFIG_BRIDGE_CFM=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_TAG_NONE=m
CONFIG_NET_DSA_TAG_AR9331=m
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
CONFIG_NET_DSA_TAG_BRCM=m
CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
CONFIG_NET_DSA_TAG_HELLCREEK=m
CONFIG_NET_DSA_TAG_GSWIP=m
CONFIG_NET_DSA_TAG_DSA_COMMON=m
CONFIG_NET_DSA_TAG_DSA=m
CONFIG_NET_DSA_TAG_EDSA=m
CONFIG_NET_DSA_TAG_MTK=m
CONFIG_NET_DSA_TAG_KSZ=m
CONFIG_NET_DSA_TAG_OCELOT=m
CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
CONFIG_NET_DSA_TAG_QCA=m
CONFIG_NET_DSA_TAG_RTL4_A=m
CONFIG_NET_DSA_TAG_RTL8_4=m
CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
CONFIG_NET_DSA_TAG_LAN9303=m
CONFIG_NET_DSA_TAG_SJA1105=m
CONFIG_NET_DSA_TAG_TRAILER=m
CONFIG_NET_DSA_TAG_XRS700X=m
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q_MVRP=y
CONFIG_LLC=y
CONFIG_LLC2=y
CONFIG_ATALK=m
# CONFIG_DEV_APPLETALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
CONFIG_6LOWPAN=m
# CONFIG_6LOWPAN_DEBUGFS is not set
CONFIG_6LOWPAN_NHC=m
CONFIG_6LOWPAN_NHC_DEST=m
CONFIG_6LOWPAN_NHC_FRAGMENT=m
CONFIG_6LOWPAN_NHC_HOP=m
CONFIG_6LOWPAN_NHC_IPV6=m
CONFIG_6LOWPAN_NHC_MOBILITY=m
CONFIG_6LOWPAN_NHC_ROUTING=m
CONFIG_6LOWPAN_NHC_UDP=m
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
CONFIG_6LOWPAN_GHC_UDP=m
CONFIG_6LOWPAN_GHC_ICMPV6=m
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
CONFIG_IEEE802154=m
CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_MAC802154=m
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFB=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_MQPRIO_LIB=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_SKBPRIO=m
CONFIG_NET_SCH_CHOKE=m
CONFIG_NET_SCH_QFQ=m
CONFIG_NET_SCH_CODEL=m
CONFIG_NET_SCH_FQ_CODEL=y
CONFIG_NET_SCH_CAKE=y
CONFIG_NET_SCH_FQ=m
CONFIG_NET_SCH_HHF=m
CONFIG_NET_SCH_PIE=m
CONFIG_NET_SCH_FQ_PIE=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_SCH_PLUG=m
CONFIG_NET_SCH_ETS=m
# CONFIG_NET_SCH_DEFAULT is not set

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_PERF=y
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=y
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_EMATCH_IPSET=m
CONFIG_NET_EMATCH_IPT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_SAMPLE=m
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
CONFIG_NET_ACT_MPLS=m
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_NET_ACT_CONNMARK=m
CONFIG_NET_ACT_CTINFO=m
CONFIG_NET_ACT_SKBMOD=m
CONFIG_NET_ACT_IFE=m
CONFIG_NET_ACT_TUNNEL_KEY=m
CONFIG_NET_ACT_CT=m
CONFIG_NET_ACT_GATE=m
CONFIG_NET_IFE_SKBMARK=m
CONFIG_NET_IFE_SKBPRIO=m
CONFIG_NET_IFE_SKBTCINDEX=m
# CONFIG_NET_TC_SKB_EXT is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=m
CONFIG_BATMAN_ADV=m
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
CONFIG_BATMAN_ADV_NC=y
CONFIG_BATMAN_ADV_MCAST=y
# CONFIG_BATMAN_ADV_DEBUG is not set
# CONFIG_BATMAN_ADV_TRACING is not set
# CONFIG_OPENVSWITCH is not set
# CONFIG_VSOCKETS is not set
CONFIG_NETLINK_DIAG=y
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=m
CONFIG_MPLS_ROUTING=m
CONFIG_MPLS_IPTUNNEL=m
CONFIG_NET_NSH=m
# CONFIG_HSR is not set
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=m
# CONFIG_QRTR_SMD is not set
# CONFIG_QRTR_TUN is not set
CONFIG_QRTR_MHI=m
# CONFIG_NET_NCSI is not set
CONFIG_PCPU_DEV_REFCNT=y
CONFIG_MAX_SKB_FRAGS=17
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_XPS=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y

#
# Network testing
#
CONFIG_NET_PKTGEN=m
# CONFIG_NET_DROP_MONITOR is not set
# end of Network testing
# end of Networking options

# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=m
CONFIG_BT_LE=y
CONFIG_BT_LE_L2CAP_ECRED=y
CONFIG_BT_6LOWPAN=m
CONFIG_BT_LEDS=y
CONFIG_BT_MSFTEXT=y
# CONFIG_BT_AOSPEXT is not set
# CONFIG_BT_DEBUGFS is not set
CONFIG_BT_SELFTEST=y
CONFIG_BT_SELFTEST_ECDH=y
CONFIG_BT_SELFTEST_SMP=y

#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=m
CONFIG_BT_BCM=m
CONFIG_BT_RTL=m
CONFIG_BT_QCA=m
CONFIG_BT_MTK=m
CONFIG_BT_HCIBTUSB=m
# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
CONFIG_BT_HCIBTUSB_POLL_SYNC=y
CONFIG_BT_HCIBTUSB_BCM=y
CONFIG_BT_HCIBTUSB_MTK=y
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_NOKIA=m
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_BCM=y
CONFIG_BT_HCIUART_RTL=y
CONFIG_BT_HCIUART_QCA=y
CONFIG_BT_HCIUART_AG6XX=y
CONFIG_BT_HCIUART_MRVL=y
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBCM4377=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
CONFIG_BT_MTKSDIO=m
CONFIG_BT_MTKUART=m
CONFIG_BT_HCIRSI=m
CONFIG_BT_VIRTIO=m
CONFIG_BT_NXPUART=m
# end of Bluetooth device drivers

CONFIG_AF_RXRPC=m
# CONFIG_AF_RXRPC_IPV6 is not set
# CONFIG_AF_RXRPC_INJECT_LOSS is not set
# CONFIG_AF_RXRPC_INJECT_RX_DELAY is not set
# CONFIG_AF_RXRPC_DEBUG is not set
# CONFIG_RXKAD is not set
# CONFIG_RXPERF is not set
CONFIG_AF_KCM=m
CONFIG_STREAM_PARSER=y
# CONFIG_MCTP is not set
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_SPY=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
CONFIG_CFG80211_HEADERS=y
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
CONFIG_CFG80211_CERTIFICATION_ONUS=y
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_EXTRA_REGDB_KEYDIR=""
CONFIG_CFG80211_REG_CELLULAR_HINTS=y
CONFIG_CFG80211_REG_RELAX_NO_IR=y
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_CFG80211_WEXT_EXPORT=y
CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
CONFIG_LIB80211_CRYPT_TKIP=m
CONFIG_LIB80211_DEBUG=y
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_MESSAGE_TRACING is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_RFKILL=m
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=m
CONFIG_NET_9P=m
CONFIG_NET_9P_FD=m
CONFIG_NET_9P_VIRTIO=m
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
CONFIG_CEPH_LIB=m
# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
# CONFIG_NFC is not set
CONFIG_PSAMPLE=m
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_SOCK_VALIDATE_XMIT=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
# CONFIG_PAGE_POOL_STATS is not set
CONFIG_FAILOVER=y
CONFIG_SHORTCUT_FE=y
CONFIG_ETHTOOL_NETLINK=y

#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIEAER is not set
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
# CONFIG_PCIEASPM_PERFORMANCE is not set
CONFIG_PCIE_PME=y
CONFIG_PCIE_PTM=y
CONFIG_PCI_MSI=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_STUB is not set
# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set
CONFIG_PCI_ECAM=y
# CONFIG_PCI_IOV is not set
# CONFIG_PCI_PRI is not set
# CONFIG_PCI_PASID is not set
CONFIG_PCI_LABEL=y
# CONFIG_PCI_DYNAMIC_OF_NODES is not set
# CONFIG_PCIE_BUS_TUNE_OFF is not set
CONFIG_PCIE_BUS_DEFAULT=y
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
# CONFIG_HOTPLUG_PCI is not set

#
# PCI controller drivers
#
# CONFIG_PCIE_ALTERA is not set
# CONFIG_PCI_HOST_THUNDER_PEM is not set
# CONFIG_PCI_HOST_THUNDER_ECAM is not set
# CONFIG_PCI_FTPCI100 is not set
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
# CONFIG_PCIE_HISI_ERR is not set
# CONFIG_PCIE_MICROCHIP_HOST is not set
CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_HOST=y
CONFIG_PCIE_ROCKCHIP_EP=y
# CONFIG_PCI_XGENE is not set
# CONFIG_PCIE_XILINX is not set

#
# Cadence-based PCIe controllers
#
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
# CONFIG_PCIE_CADENCE_PLAT_EP is not set
# CONFIG_PCI_J721E_HOST is not set
# CONFIG_PCI_J721E_EP is not set
# end of Cadence-based PCIe controllers

#
# DesignWare-based PCIe controllers
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_EP=y
# CONFIG_PCIE_AL is not set
CONFIG_PCI_MESON=y
# CONFIG_PCI_HISI is not set
# CONFIG_PCIE_KIRIN is not set
CONFIG_PCIE_DW_PLAT=y
CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCIE_DW_PLAT_EP=y
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
# end of DesignWare-based PCIe controllers

#
# Mobiveil-based PCIe controllers
#
# end of Mobiveil-based PCIe controllers
# end of PCI controller drivers

#
# PCI Endpoint
#
CONFIG_PCI_ENDPOINT=y
# CONFIG_PCI_ENDPOINT_CONFIGFS is not set
# CONFIG_PCI_EPF_TEST is not set
CONFIG_PCI_EPF_NTB=m
CONFIG_PCI_EPF_MHI=m
# end of PCI Endpoint

#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set
# end of PCI switch controller drivers

# CONFIG_CXL_BUS is not set
# CONFIG_PCCARD is not set
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_DEVTMPFS_SAFE is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_DEBUG=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
CONFIG_FW_LOADER_COMPRESS=y
CONFIG_FW_LOADER_COMPRESS_XZ=y
CONFIG_FW_LOADER_COMPRESS_ZSTD=y
# CONFIG_FW_UPLOAD is not set
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_SPMI=m
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SCCB=m
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
CONFIG_BRCMSTB_GISB_ARB=y
# CONFIG_MOXTET is not set
CONFIG_SUN50I_DE2_BUS=y
CONFIG_SUNXI_RSB=y
CONFIG_VEXPRESS_CONFIG=y
CONFIG_MHI_BUS=m
# CONFIG_MHI_BUS_DEBUG is not set
CONFIG_MHI_BUS_PCI_GENERIC=m
CONFIG_MHI_BUS_EP=m
# end of Bus devices

#
# Cache Drivers
#
# end of Cache Drivers

CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y

#
# Firmware Drivers
#

#
# ARM System Control and Management Interface Protocol
#
CONFIG_ARM_SCMI_PROTOCOL=y
# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
# CONFIG_ARM_SCMI_DEBUG_COUNTERS is not set
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
CONFIG_ARM_SCMI_HAVE_SHMEM=y
CONFIG_ARM_SCMI_HAVE_MSG=y
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y
CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y
# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE is not set
CONFIG_ARM_SCMI_POWER_DOMAIN=y
CONFIG_ARM_SCMI_POWER_CONTROL=y
# end of ARM System Control and Management Interface Protocol

CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
CONFIG_ARM_SDE_INTERFACE=y
# CONFIG_FIRMWARE_MEMMAP is not set
CONFIG_DMIID=y
CONFIG_DMI_SYSFS=y
# CONFIG_ISCSI_IBFT is not set
CONFIG_FW_CFG_SYSFS=y
CONFIG_FW_CFG_SYSFS_CMDLINE=y
CONFIG_SYSFB=y
# CONFIG_SYSFB_SIMPLEFB is not set
CONFIG_ARM_FFA_TRANSPORT=y
CONFIG_ARM_FFA_SMCCC=y
CONFIG_FW_CS_DSP=y
# CONFIG_GOOGLE_FIRMWARE is not set

#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_ESRT=y
CONFIG_EFI_VARS_PSTORE=y
# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_GENERIC_STUB=y
# CONFIG_EFI_ZBOOT is not set
CONFIG_EFI_ARMSTUB_DTB_LOADER=y
CONFIG_EFI_BOOTLOADER_CONTROL=m
CONFIG_EFI_CAPSULE_LOADER=m
CONFIG_EFI_TEST=m
# CONFIG_RESET_ATTACK_MITIGATION is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
# CONFIG_EFI_DISABLE_RUNTIME is not set
# CONFIG_EFI_COCO_SECRET is not set
# end of EFI (Extensible Firmware Interface) Support

CONFIG_UEFI_CPER=y
CONFIG_UEFI_CPER_ARM=y
CONFIG_MESON_SM=y
CONFIG_MESON_GX_PM=y
CONFIG_ARM_PSCI_FW=y
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_ARM_SMCCC_SOC_ID=y

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_GNSS=m
CONFIG_GNSS_SERIAL=m
CONFIG_GNSS_MTK_SERIAL=m
CONFIG_GNSS_SIRF_SERIAL=m
CONFIG_GNSS_UBX_SERIAL=m
CONFIG_GNSS_USB=m
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set

#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_AFS_PARTS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y

#
# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
#
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_PARTITIONED_MASTER is not set

#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_DATAFLASH is not set
CONFIG_MTD_MCHP23K256=m
# CONFIG_MTD_MCHP48L640 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOCG3 is not set
# end of Self-contained MTD device drivers

#
# NAND
#
CONFIG_MTD_NAND_CORE=y
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_RAW_NAND is not set
# CONFIG_MTD_SPI_NAND is not set

#
# ECC engine support
#
CONFIG_MTD_NAND_ECC=y
# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
CONFIG_MTD_NAND_ECC_MXIC=y
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
# CONFIG_MTD_UBI_BLOCK is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_NULL_BLK=m
CONFIG_CDROM=m
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
CONFIG_ZRAM=m
# CONFIG_ZRAM_DEF_COMP_LZORLE is not set
CONFIG_ZRAM_DEF_COMP_ZSTD=y
# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
# CONFIG_ZRAM_DEF_COMP_LZO is not set
# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
# CONFIG_ZRAM_DEF_COMP_842 is not set
CONFIG_ZRAM_DEF_COMP="zstd"
# CONFIG_ZRAM_WRITEBACK is not set
CONFIG_ZRAM_TRACK_ENTRY_ACTIME=y
# CONFIG_ZRAM_MEMORY_TRACKING is not set
CONFIG_ZRAM_MULTI_COMP=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
CONFIG_BLK_DEV_DRBD=m
CONFIG_DRBD_FAULT_INJECTION=y
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_VIRTIO_BLK=m
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_UBLK is not set

#
# NVME Support
#
CONFIG_NVME_CORE=y
CONFIG_BLK_DEV_NVME=y
# CONFIG_NVME_MULTIPATH is not set
# CONFIG_NVME_VERBOSE_ERRORS is not set
CONFIG_NVME_HWMON=y
CONFIG_NVME_FABRICS=m
# CONFIG_NVME_FC is not set
CONFIG_NVME_TCP=m
# CONFIG_NVME_AUTH is not set
CONFIG_NVME_TARGET=m
# CONFIG_NVME_TARGET_PASSTHRU is not set
CONFIG_NVME_TARGET_LOOP=m
# CONFIG_NVME_TARGET_FC is not set
CONFIG_NVME_TARGET_TCP=m
# CONFIG_NVME_TARGET_AUTH is not set
# end of NVME Support

#
# Misc devices
#
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_PHANTOM is not set
CONFIG_TIFM_CORE=m
CONFIG_TIFM_7XX1=m
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HI6421V600_IRQ is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_SRAM=y
# CONFIG_DW_XDATA_PCIE is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_XILINX_SDFEC is not set
CONFIG_MISC_RTSX=m
# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_OPEN_DICE is not set
# CONFIG_VCPU_STALL_DETECTOR is not set
# CONFIG_C2PORT is not set

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
CONFIG_EEPROM_AT25=m
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
CONFIG_EEPROM_93CX6=m
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

CONFIG_CB710_CORE=m
# CONFIG_CB710_DEBUG is not set
CONFIG_CB710_DEBUG_ASSUMPTIONS=y

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# end of Texas Instruments shared transport line discipline

# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
# CONFIG_VMWARE_VMCI is not set
# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_BCM_VK is not set
# CONFIG_MISC_ALCOR_PCI is not set
# CONFIG_MISC_RTSX_PCI is not set
CONFIG_MISC_RTSX_USB=m
# CONFIG_UACCE is not set
# CONFIG_PVPANIC is not set
# CONFIG_GP_PCI1XXXX is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI_COMMON=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=m
CONFIG_BLK_DEV_BSG=y
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set

#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=m
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_ISCSI_BOOT_SYSFS=m
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_HISI_SAS is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_MPI3MR is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_MYRB is not set
# CONFIG_SCSI_MYRS is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_FDOMAIN_PCI is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
CONFIG_SCSI_VIRTIO=m
# CONFIG_SCSI_DH is not set
# end of SCSI device support

CONFIG_ATA=y
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_ATA_LEDS=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_AHCI_DWC=y
CONFIG_AHCI_CEVA=m
CONFIG_AHCI_SUNXI=y
CONFIG_SATA_INIC162X=m
CONFIG_SATA_ACARD_AHCI=m
CONFIG_SATA_SIL24=m
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#
# CONFIG_PDC_ADMA is not set
CONFIG_SATA_QSTOR=m
CONFIG_SATA_SX4=m
CONFIG_ATA_BMDMA=y

#
# SATA SFF controllers with BMDMA
#
# CONFIG_ATA_PIIX is not set
CONFIG_SATA_DWC=m
CONFIG_SATA_DWC_OLD_DMA=y
CONFIG_SATA_MV=m
CONFIG_SATA_NV=m
CONFIG_SATA_PROMISE=m
CONFIG_SATA_SIL=m
CONFIG_SATA_SIS=m
CONFIG_SATA_SVW=m
CONFIG_SATA_ULI=m
CONFIG_SATA_VIA=m
CONFIG_SATA_VITESSE=m

#
# PATA SFF controllers with BMDMA
#
# CONFIG_PATA_ALI is not set
# CONFIG_PATA_AMD is not set
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_ATP867X is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CYPRESS is not set
# CONFIG_PATA_EFAR is not set
# CONFIG_PATA_HPT366 is not set
# CONFIG_PATA_HPT37X is not set
# CONFIG_PATA_HPT3X2N is not set
# CONFIG_PATA_HPT3X3 is not set
# CONFIG_PATA_IT8213 is not set
# CONFIG_PATA_IT821X is not set
# CONFIG_PATA_JMICRON is not set
# CONFIG_PATA_MARVELL is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_OPTIDMA is not set
# CONFIG_PATA_PDC2027X is not set
# CONFIG_PATA_PDC_OLD is not set
# CONFIG_PATA_RADISYS is not set
# CONFIG_PATA_RDC is not set
# CONFIG_PATA_SCH is not set
# CONFIG_PATA_SERVERWORKS is not set
# CONFIG_PATA_SIL680 is not set
CONFIG_PATA_SIS=m
# CONFIG_PATA_TOSHIBA is not set
# CONFIG_PATA_TRIFLEX is not set
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set

#
# PIO-only SFF controllers
#
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_OF_PLATFORM is not set
# CONFIG_PATA_RZ1000 is not set

#
# Generic fallback / legacy drivers
#
# CONFIG_PATA_ACPI is not set
# CONFIG_ATA_GENERIC is not set
# CONFIG_PATA_LEGACY is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_BITMAP_FILE=y
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
CONFIG_MD_CLUSTER=m
CONFIG_BCACHE=m
# CONFIG_BCACHE_DEBUG is not set
# CONFIG_BCACHE_CLOSURES_DEBUG is not set
# CONFIG_BCACHE_ASYNC_REGISTRATION is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=m
# CONFIG_DM_DEBUG is not set
CONFIG_DM_BUFIO=m
# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
# CONFIG_DM_CACHE is not set
CONFIG_DM_WRITECACHE=m
# CONFIG_DM_EBS is not set
# CONFIG_DM_ERA is not set
# CONFIG_DM_CLONE is not set
CONFIG_DM_MIRROR=m
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
# CONFIG_DM_MULTIPATH_HST is not set
# CONFIG_DM_MULTIPATH_IOA is not set
CONFIG_DM_DELAY=m
# CONFIG_DM_DUST is not set
# CONFIG_DM_UEVENT is not set
CONFIG_DM_FLAKEY=m
CONFIG_DM_VERITY=m
# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set
# CONFIG_DM_VERITY_FEC is not set
# CONFIG_DM_SWITCH is not set
CONFIG_DM_LOG_WRITES=m
CONFIG_DM_INTEGRITY=m
CONFIG_DM_AUDIT=y
CONFIG_TARGET_CORE=m
# CONFIG_TCM_IBLOCK is not set
# CONFIG_TCM_FILEIO is not set
# CONFIG_TCM_PSCSI is not set
# CONFIG_LOOPBACK_TARGET is not set
CONFIG_ISCSI_TARGET=m
# CONFIG_REMOTE_TARGET is not set
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
# end of IEEE 1394 (FireWire) support

CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_WIREGUARD=m
# CONFIG_WIREGUARD_DEBUG is not set
CONFIG_EQUALIZER=m
# CONFIG_NET_FC is not set
CONFIG_IFB=m
CONFIG_NET_TEAM=m
CONFIG_NET_TEAM_MODE_BROADCAST=m
CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
CONFIG_NET_TEAM_MODE_RANDOM=m
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
CONFIG_NET_TEAM_MODE_LOADBALANCE=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=m
CONFIG_IPVTAP=m
CONFIG_VXLAN=m
CONFIG_GENEVE=m
CONFIG_BAREUDP=m
CONFIG_GTP=m
CONFIG_AMT=m
CONFIG_MACSEC=m
CONFIG_NETCONSOLE=m
CONFIG_NETCONSOLE_DYNAMIC=y
# CONFIG_NETCONSOLE_EXTENDED_LOG is not set
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=m
CONFIG_TAP=m
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_NLMON=m
CONFIG_NET_VRF=m
# CONFIG_MHI_NET is not set
# CONFIG_ARCNET is not set

#
# Distributed Switch Architecture drivers
#
CONFIG_B53=m
CONFIG_B53_SPI_DRIVER=m
CONFIG_B53_MDIO_DRIVER=m
CONFIG_B53_MMAP_DRIVER=m
CONFIG_B53_SRAB_DRIVER=m
CONFIG_B53_SERDES=m
CONFIG_NET_DSA_BCM_SF2=m
CONFIG_NET_DSA_LOOP=m
CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
CONFIG_NET_DSA_LANTIQ_GSWIP=m
CONFIG_NET_DSA_MT7530=m
CONFIG_NET_DSA_MT7530_MDIO=m
CONFIG_NET_DSA_MT7530_MMIO=m
CONFIG_NET_DSA_MV88E6060=m
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
CONFIG_NET_DSA_MICROCHIP_KSZ_PTP=y
CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
CONFIG_NET_DSA_MV88E6XXX=m
CONFIG_NET_DSA_MV88E6XXX_PTP=y
CONFIG_NET_DSA_AR9331=m
CONFIG_NET_DSA_QCA8K=m
CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y
CONFIG_NET_DSA_SJA1105=m
CONFIG_NET_DSA_SJA1105_PTP=y
CONFIG_NET_DSA_SJA1105_TAS=y
CONFIG_NET_DSA_SJA1105_VL=y
CONFIG_NET_DSA_XRS700X=m
CONFIG_NET_DSA_XRS700X_I2C=m
CONFIG_NET_DSA_XRS700X_MDIO=m
CONFIG_NET_DSA_REALTEK=m
CONFIG_NET_DSA_REALTEK_MDIO=m
CONFIG_NET_DSA_REALTEK_SMI=m
CONFIG_NET_DSA_REALTEK_RTL8365MB=m
CONFIG_NET_DSA_REALTEK_RTL8366RB=m
CONFIG_NET_DSA_SMSC_LAN9303=m
CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
CONFIG_NET_DSA_VITESSE_VSC73XX=m
CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
# end of Distributed Switch Architecture drivers

CONFIG_ETHERNET=y
CONFIG_MDIO=m
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
CONFIG_NET_VENDOR_ALLWINNER=y
CONFIG_SUN4I_EMAC=y
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_ALTERA_TSE is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
CONFIG_NET_VENDOR_ASIX=y
# CONFIG_SPI_AX88796C is not set
CONFIG_NET_VENDOR_ATHEROS=y
# CONFIG_ATL2 is not set
# CONFIG_ATL1 is not set
# CONFIG_ATL1E is not set
# CONFIG_ATL1C is not set
CONFIG_ALX=m
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_CORTINA is not set
CONFIG_NET_VENDOR_DAVICOM=y
# CONFIG_DM9051 is not set
# CONFIG_DNET is not set
# CONFIG_NET_VENDOR_DEC is not set
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
CONFIG_NET_VENDOR_ENGLEDER=y
# CONFIG_TSNEP is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_FREESCALE is not set
CONFIG_NET_VENDOR_FUNGIBLE=y
# CONFIG_FUN_ETH is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
CONFIG_NET_VENDOR_I825XX=y
CONFIG_NET_VENDOR_INTEL=y
# CONFIG_E100 is not set
CONFIG_E1000=m
CONFIG_E1000E=m
CONFIG_IGB=m
CONFIG_IGB_HWMON=y
CONFIG_IGBVF=m
# CONFIG_IXGBE is not set
# CONFIG_IXGBEVF is not set
# CONFIG_I40E is not set
# CONFIG_I40EVF is not set
# CONFIG_ICE is not set
# CONFIG_FM10K is not set
CONFIG_IGC=m
# CONFIG_JME is not set
CONFIG_NET_VENDOR_ADI=y
# CONFIG_ADIN1110 is not set
CONFIG_NET_VENDOR_LITEX=y
# CONFIG_LITEX_LITEETH is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_MICROSOFT is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_FEALNX is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETERION is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_BROCADE is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCA7000_UART is not set
CONFIG_QCOM_EMAC=m
CONFIG_SFE_SUPPORT_IPV6=y
CONFIG_SFE_ECM=y
CONFIG_FAST_CLASSIFIER=y
# CONFIG_RMNET is not set
# CONFIG_NET_VENDOR_RDC is not set
CONFIG_NET_VENDOR_REALTEK=y
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
CONFIG_R8125=m
CONFIG_R8125_SOC_LAN=y
# CONFIG_R8125_REALWOW_SUPPORT is not set
# CONFIG_R8125_DASH_SUPPORT is not set
# CONFIG_R8125_DOWN_SPEED_100 is not set
# CONFIG_R8125_ASPM is not set
CONFIG_R8125_WOL_SUPPORT=y
CONFIG_R8125_S5WOL=y
# CONFIG_R8125_S5_KEEP_CURR_MAC is not set
# CONFIG_R8125_EEE is not set
# CONFIG_R8125_S0_MAGIC_PACKET is not set
CONFIG_R8125_TX_NO_CLOSE=y
CONFIG_R8125_MULTI_MSIX_VECTOR=y
CONFIG_R8125_MULTIPLE_TX_QUEUE=y
CONFIG_R8125_RSS_SUPPORT=y
# CONFIG_R8125_PTP_SUPPORT is not set
CONFIG_R8125_FIBER_SUPPORT=y
CONFIG_R8125_USE_FIRMWARE_FILE=y
# CONFIG_R8125_DOUBLE_VLAN is not set
# CONFIG_R8125_PAGE_REUSE is not set
CONFIG_R8125_GIGA_LITE=y
CONFIG_R8126=m
CONFIG_R8126_SOC_LAN=y
# CONFIG_R8126_REALWOW_SUPPORT is not set
# CONFIG_R8126_DASH_SUPPORT is not set
# CONFIG_R8126_DOWN_SPEED_100 is not set
# CONFIG_R8126_ASPM is not set
CONFIG_R8126_WOL_SUPPORT=y
CONFIG_R8126_S5WOL=y
# CONFIG_R8126_S5_KEEP_CURR_MAC is not set
# CONFIG_R8126_EEE is not set
# CONFIG_R8126_S0_MAGIC_PACKET is not set
CONFIG_R8126_TX_NO_CLOSE=y
CONFIG_R8126_MULTI_MSIX_VECTOR=y
CONFIG_R8126_MULTIPLE_TX_QUEUE=y
CONFIG_R8126_RSS_SUPPORT=y
CONFIG_R8126_PTP_SUPPORT=y
CONFIG_R8126_FIBER_SUPPORT=y
CONFIG_R8126_USE_FIRMWARE_FILE=y
# CONFIG_R8126_DOUBLE_VLAN is not set
# CONFIG_R8126_PAGE_REUSE is not set
CONFIG_R8126_GIGA_LITE=y
CONFIG_R8168=m
# CONFIG_R8168_SOC_LAN is not set
# CONFIG_R8168_FIBER_SUPPORT is not set
# CONFIG_R8168_REALWOW_SUPPORT is not set
# CONFIG_R8168_DASH_SUPPORT is not set
# CONFIG_R8168_DOWN_SPEED_100 is not set
CONFIG_R8168_ASPM=y
CONFIG_R8168_DYNAMIC_ASPM=y
CONFIG_R8168_WOL_SUPPORT=y
CONFIG_R8168_S5WOL=y
# CONFIG_R8168_S5_KEEP_CURR_MAC is not set
CONFIG_R8168_EEE=y
# CONFIG_R8168_S0_MAGIC_PACKET is not set
# CONFIG_R8168_USE_FIRMWARE_FILE is not set
# CONFIG_R8168_CTAP_SHORT_OFF is not set
# CONFIG_R8168_MULTIPLE_TX_QUEUE is not set
# CONFIG_R8168_RSS_SUPPORT is not set
CONFIG_R8168_GIGA_LITE=y
# CONFIG_R8169 is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_SELFTESTS=y
CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_MESON=y
CONFIG_DWMAC_ROCKCHIP=y
CONFIG_DWMAC_SUNXI=y
CONFIG_DWMAC_SUN8I=y
# CONFIG_DWMAC_INTEL_PLAT is not set
# CONFIG_STMMAC_PCI is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
CONFIG_NET_VENDOR_VERTEXCOM=y
# CONFIG_MSE102X is not set
# CONFIG_NET_VENDOR_VIA is not set
CONFIG_NET_VENDOR_WANGXUN=y
# CONFIG_NGBE is not set
# CONFIG_TXGBE is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_NET_SB1000 is not set
CONFIG_PHYLINK=y
CONFIG_PHYLIB=y
CONFIG_SWPHY=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_PHYLIB_LEDS=y
CONFIG_FIXED_PHY=y
# CONFIG_SFP is not set

#
# MII PHY device drivers
#
# CONFIG_AMD_PHY is not set
CONFIG_MESON_GXL_PHY=y
# CONFIG_ADIN_PHY is not set
# CONFIG_ADIN1100_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
CONFIG_AX88796B_PHY=m
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM54140_PHY is not set
CONFIG_BCM7XXX_PHY=m
# CONFIG_BCM84881_PHY is not set
# CONFIG_BCM87XX_PHY is not set
CONFIG_BCM_NET_PHYLIB=m
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
CONFIG_ICPLUS_PHY=y
CONFIG_JLSEMI_PHY=y
# CONFIG_LXT_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MARVELL_88Q2XXX_PHY is not set
# CONFIG_MARVELL_88X2222_PHY is not set
# CONFIG_MAXLINEAR_GPHY is not set
# CONFIG_MEDIATEK_GE_PHY is not set
# CONFIG_MEDIATEK_GE_SOC_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_MICROCHIP_T1S_PHY is not set
CONFIG_MICROCHIP_PHY=m
# CONFIG_MICROCHIP_T1_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
CONFIG_MOTORCOMM_PHY=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_NXP_CBTX_PHY is not set
# CONFIG_NXP_C45_TJA11XX_PHY is not set
# CONFIG_NXP_TJA11XX_PHY is not set
# CONFIG_NCN26000_PHY is not set
# CONFIG_AT803X_PHY is not set
# CONFIG_QSEMI_PHY is not set
CONFIG_REALTEK_PHY=y
# CONFIG_RENESAS_PHY is not set
CONFIG_ROCKCHIP_PHY=y
CONFIG_SMSC_PHY=y
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83TC811_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
# CONFIG_DP83869_PHY is not set
# CONFIG_DP83TD510_PHY is not set
CONFIG_VITESSE_PHY=m
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_PSE_CONTROLLER is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
CONFIG_FWNODE_MDIO=y
CONFIG_OF_MDIO=y
CONFIG_ACPI_MDIO=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_SUN4I=y
CONFIG_MDIO_BITBANG=m
CONFIG_MDIO_BCM_UNIMAC=m
CONFIG_MDIO_GPIO=m
# CONFIG_MDIO_HISI_FEMAC is not set
CONFIG_MDIO_MVUSB=m
# CONFIG_MDIO_MSCC_MIIM is not set
# CONFIG_MDIO_OCTEON is not set
CONFIG_MDIO_IPQ4019=m
CONFIG_MDIO_IPQ8064=m
# CONFIG_MDIO_THUNDER is not set

#
# MDIO Multiplexers
#
CONFIG_MDIO_BUS_MUX=y
CONFIG_MDIO_BUS_MUX_MESON_G12A=y
CONFIG_MDIO_BUS_MUX_MESON_GXL=m
CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y

#
# PCS device drivers
#
CONFIG_PCS_XPCS=y
CONFIG_PCS_MTK_LYNXI=m
# end of PCS device drivers

CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=m
# CONFIG_PPPOE_HASH_BITS_1 is not set
# CONFIG_PPPOE_HASH_BITS_2 is not set
CONFIG_PPPOE_HASH_BITS_4=y
# CONFIG_PPPOE_HASH_BITS_8 is not set
CONFIG_PPPOE_HASH_BITS=4
CONFIG_PPTP=m
CONFIG_PPPOL2TP=m
CONFIG_PPP_ASYNC=m
# CONFIG_PPP_SYNC_TTY is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=m
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_AX8817X=m
CONFIG_USB_NET_AX88179_178A=m
CONFIG_USB_NET_CDCETHER=m
CONFIG_USB_NET_CDC_EEM=m
CONFIG_USB_NET_CDC_NCM=m
CONFIG_USB_NET_HUAWEI_CDC_NCM=m
CONFIG_USB_NET_CDC_MBIM=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9700=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
CONFIG_USB_NET_CDC_SUBSET=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
CONFIG_USB_EPSON2888=y
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=m
CONFIG_USB_NET_CX82310_ETH=m
CONFIG_USB_NET_KALMIA=m
CONFIG_USB_NET_QMI_WWAN=m
CONFIG_USB_HSO=m
CONFIG_USB_NET_INT51X1=m
CONFIG_USB_IPHETH=m
CONFIG_USB_SIERRA_NET=m
CONFIG_USB_VL600=m
CONFIG_USB_NET_CH9200=m
CONFIG_USB_NET_AQC111=m
CONFIG_WLAN=y
CONFIG_WLAN_VENDOR_ADMTEK=y
CONFIG_ADM8211=m
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
CONFIG_ATH_USER_REGD=y
# CONFIG_ATH_DEBUG is not set
CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS=y
# CONFIG_ATH_REG_DYNAMIC_USER_CERT_TESTING is not set
CONFIG_ATH5K=m
# CONFIG_ATH5K_DEBUG is not set
# CONFIG_ATH5K_TRACER is not set
CONFIG_ATH5K_PCI=y
# CONFIG_ATH5K_TEST_CHANNELS is not set
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K=m
CONFIG_ATH9K_PCI=y
CONFIG_ATH9K_AHB=y
# CONFIG_ATH9K_DEBUGFS is not set
CONFIG_ATH9K_DFS_CERTIFIED=y
CONFIG_ATH9K_DYNACK=y
# CONFIG_ATH9K_WOW is not set
CONFIG_ATH9K_RFKILL=y
CONFIG_ATH9K_CHANNEL_CONTEXT=y
# CONFIG_ATH9K_PCOEM is not set
CONFIG_ATH9K_PCI_NO_EEPROM=m
CONFIG_ATH9K_HTC=m
# CONFIG_ATH9K_HTC_DEBUGFS is not set
CONFIG_ATH9K_HWRNG=y
CONFIG_CARL9170=m
CONFIG_CARL9170_LEDS=y
CONFIG_CARL9170_WPC=y
CONFIG_CARL9170_HWRNG=y
CONFIG_ATH6KL=m
CONFIG_ATH6KL_SDIO=m
CONFIG_ATH6KL_USB=m
# CONFIG_ATH6KL_DEBUG is not set
# CONFIG_ATH6KL_TRACING is not set
# CONFIG_ATH6KL_REGDOMAIN is not set
CONFIG_AR5523=m
# CONFIG_WIL6210 is not set
CONFIG_ATH10K=m
CONFIG_ATH10K_CE=y
CONFIG_ATH10K_PCI=m
# CONFIG_ATH10K_AHB is not set
CONFIG_ATH10K_SDIO=m
CONFIG_ATH10K_USB=m
# CONFIG_ATH10K_DEBUG is not set
# CONFIG_ATH10K_DEBUGFS is not set
# CONFIG_ATH10K_TRACING is not set
CONFIG_ATH10K_DFS_CERTIFIED=y
CONFIG_WCN36XX=m
# CONFIG_WCN36XX_DEBUGFS is not set
CONFIG_ATH11K=m
# CONFIG_ATH11K_AHB is not set
CONFIG_ATH11K_PCI=m
# CONFIG_ATH11K_DEBUG is not set
# CONFIG_ATH11K_TRACING is not set
CONFIG_ATH12K=m
# CONFIG_ATH12K_DEBUG is not set
# CONFIG_ATH12K_TRACING is not set
CONFIG_WLAN_VENDOR_ATMEL=y
# CONFIG_ATMEL is not set
CONFIG_AT76C50X_USB=m
CONFIG_WLAN_VENDOR_BROADCOM=y
# CONFIG_B43 is not set
# CONFIG_B43LEGACY is not set
CONFIG_BRCMUTIL=m
# CONFIG_BRCMSMAC is not set
CONFIG_BRCMFMAC=m
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
# CONFIG_BRCMFMAC_PCIE is not set
CONFIG_BRCM_TRACING=y
CONFIG_BRCMDBG=y
# CONFIG_WLAN_VENDOR_CISCO is not set
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_IPW2100=m
# CONFIG_IPW2100_MONITOR is not set
# CONFIG_IPW2100_DEBUG is not set
CONFIG_IPW2200=m
# CONFIG_IPW2200_MONITOR is not set
# CONFIG_IPW2200_QOS is not set
# CONFIG_IPW2200_DEBUG is not set
CONFIG_LIBIPW=m
# CONFIG_LIBIPW_DEBUG is not set
CONFIG_IWLEGACY=m
CONFIG_IWL4965=m
CONFIG_IWL3945=m

#
# iwl3945 / iwl4965 Debugging Options
#
# CONFIG_IWLEGACY_DEBUG is not set
# end of iwl3945 / iwl4965 Debugging Options

CONFIG_IWLWIFI=m
CONFIG_IWLWIFI_LEDS=y
CONFIG_IWLDVM=m
CONFIG_IWLMVM=m
CONFIG_IWLWIFI_OPMODE_MODULAR=y

#
# Debugging Options
#
# CONFIG_IWLWIFI_DEBUG is not set
# CONFIG_IWLWIFI_DEVICE_TRACING is not set
# end of Debugging Options

CONFIG_WLAN_VENDOR_INTERSIL=y
CONFIG_HOSTAP=m
# CONFIG_HOSTAP_FIRMWARE is not set
CONFIG_HOSTAP_PLX=m
CONFIG_HOSTAP_PCI=m
CONFIG_HERMES=m
CONFIG_HERMES_PRISM=y
CONFIG_HERMES_CACHE_FW_ON_INIT=y
CONFIG_PLX_HERMES=m
CONFIG_TMD_HERMES=m
CONFIG_NORTEL_HERMES=m
CONFIG_PCI_HERMES=m
CONFIG_ORINOCO_USB=m
CONFIG_P54_COMMON=m
CONFIG_P54_USB=m
CONFIG_P54_PCI=m
CONFIG_P54_SPI=m
# CONFIG_P54_SPI_DEFAULT_EEPROM is not set
CONFIG_P54_LEDS=y
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_USB=m
CONFIG_LIBERTAS_SDIO=m
CONFIG_LIBERTAS_SPI=m
# CONFIG_LIBERTAS_DEBUG is not set
CONFIG_LIBERTAS_MESH=y
CONFIG_LIBERTAS_THINFIRM=m
# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
CONFIG_LIBERTAS_THINFIRM_USB=m
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_SDIO=m
CONFIG_MWIFIEX_PCIE=m
CONFIG_MWIFIEX_USB=m
CONFIG_MWL8K=m
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=m
CONFIG_MT76_CORE=m
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=m
CONFIG_MT76_SDIO=m
CONFIG_MT76x02_LIB=m
CONFIG_MT76x02_USB=m
CONFIG_MT76_CONNAC_LIB=m
CONFIG_MT792x_LIB=m
CONFIG_MT792x_USB=m
CONFIG_MT76x0_COMMON=m
CONFIG_MT76x0U=m
CONFIG_MT76x0E=m
CONFIG_MT76x2_COMMON=m
CONFIG_MT76x2E=m
CONFIG_MT76x2U=m
CONFIG_MT7603E=m
CONFIG_MT7615_COMMON=m
CONFIG_MT7615E=m
CONFIG_MT7663_USB_SDIO_COMMON=m
CONFIG_MT7663U=m
CONFIG_MT7663S=m
CONFIG_MT7915E=m
CONFIG_MT7921_COMMON=m
CONFIG_MT7921E=m
CONFIG_MT7921S=m
CONFIG_MT7921U=m
CONFIG_MT7996E=m
CONFIG_WLAN_VENDOR_MICROCHIP=y
CONFIG_WILC1000=m
CONFIG_WILC1000_SDIO=m
# CONFIG_WILC1000_SPI is not set
# CONFIG_WILC1000_HW_OOB_INTR is not set
CONFIG_WLAN_VENDOR_PURELIFI=y
# CONFIG_PLFXLC is not set
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_RT2X00=m
# CONFIG_RT2400PCI is not set
# CONFIG_RT2500PCI is not set
# CONFIG_RT61PCI is not set
CONFIG_RT2800PCI=m
CONFIG_RT2800PCI_RT33XX=y
CONFIG_RT2800PCI_RT35XX=y
CONFIG_RT2800PCI_RT53XX=y
CONFIG_RT2800PCI_RT3290=y
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
CONFIG_RT2800USB_RT33XX=y
CONFIG_RT2800USB_RT35XX=y
CONFIG_RT2800USB_RT3573=y
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
CONFIG_RT2800USB_UNKNOWN=y
CONFIG_RT2800_LIB=m
CONFIG_RT2800_LIB_MMIO=m
CONFIG_RT2X00_LIB_MMIO=m
CONFIG_RT2X00_LIB_PCI=m
CONFIG_RT2X00_LIB_USB=m
CONFIG_RT2X00_LIB=m
CONFIG_RT2X00_LIB_FIRMWARE=y
CONFIG_RT2X00_LIB_CRYPTO=y
CONFIG_RT2X00_LIB_LEDS=y
# CONFIG_RT2X00_DEBUG is not set
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_RTL8180=m
CONFIG_RTL8187=m
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=m
CONFIG_RTL8192CE=m
CONFIG_RTL8192SE=m
CONFIG_RTL8192DE=m
CONFIG_RTL8723AE=m
CONFIG_RTL8723BE=m
CONFIG_RTL8188EE=m
CONFIG_RTL8192EE=m
CONFIG_RTL8821AE=m
CONFIG_RTL8192CU=m
CONFIG_RTLWIFI=m
CONFIG_RTLWIFI_PCI=m
CONFIG_RTLWIFI_USB=m
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8723_COMMON=m
CONFIG_RTLBTCOEXIST=m
CONFIG_RTL8XXXU=m
# CONFIG_RTL8XXXU_UNTESTED is not set
CONFIG_RTW88=m
CONFIG_RTW88_CORE=m
CONFIG_RTW88_PCI=m
CONFIG_RTW88_SDIO=m
CONFIG_RTW88_USB=m
CONFIG_RTW88_8822B=m
CONFIG_RTW88_8822C=m
CONFIG_RTW88_8723D=m
CONFIG_RTW88_8821C=m
CONFIG_RTW88_8822BE=m
CONFIG_RTW88_8822BS=m
CONFIG_RTW88_8822BU=m
CONFIG_RTW88_8822CE=m
CONFIG_RTW88_8822CS=m
CONFIG_RTW88_8822CU=m
CONFIG_RTW88_8723DE=m
CONFIG_RTW88_8723DS=m
CONFIG_RTW88_8723DU=m
CONFIG_RTW88_8821CE=m
CONFIG_RTW88_8821CS=m
CONFIG_RTW88_8821CU=m
# CONFIG_RTW88_DEBUG is not set
# CONFIG_RTW88_DEBUGFS is not set
CONFIG_RTW89=m
CONFIG_RTW89_CORE=m
CONFIG_RTW89_PCI=m
CONFIG_RTW89_8851B=m
CONFIG_RTW89_8852A=m
CONFIG_RTW89_8852B=m
CONFIG_RTW89_8852C=m
CONFIG_RTW89_8851BE=m
CONFIG_RTW89_8852AE=m
CONFIG_RTW89_8852BE=m
CONFIG_RTW89_8852CE=m
# CONFIG_RTW89_DEBUGMSG is not set
# CONFIG_RTW89_DEBUGFS is not set
CONFIG_WLAN_VENDOR_RSI=y
CONFIG_RSI_91X=m
CONFIG_RSI_DEBUGFS=y
CONFIG_RSI_SDIO=m
CONFIG_RSI_USB=m
CONFIG_RSI_COEX=y
CONFIG_WLAN_VENDOR_SILABS=y
# CONFIG_WFX is not set
CONFIG_WLAN_VENDOR_ST=y
CONFIG_CW1200=m
CONFIG_CW1200_WLAN_SDIO=m
CONFIG_CW1200_WLAN_SPI=m
CONFIG_WLAN_VENDOR_TI=y
CONFIG_WL1251=m
# CONFIG_WL1251_SPI is not set
CONFIG_WL1251_SDIO=m
# CONFIG_WL12XX is not set
# CONFIG_WL18XX is not set
CONFIG_WLCORE=m
# CONFIG_WLCORE_SPI is not set
CONFIG_WLCORE_SDIO=m
CONFIG_WLAN_VENDOR_ZYDAS=y
CONFIG_USB_ZD1201=m
CONFIG_ZD1211RW=m
# CONFIG_ZD1211RW_DEBUG is not set
CONFIG_WLAN_VENDOR_QUANTENNA=y
CONFIG_QTNFMAC=m
CONFIG_QTNFMAC_PCIE=m
CONFIG_USB_NET_RNDIS_WLAN=m
CONFIG_MAC80211_HWSIM=m
CONFIG_VIRT_WIFI=m
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
CONFIG_IEEE802154_AT86RF230=m
CONFIG_IEEE802154_MRF24J40=m
CONFIG_IEEE802154_CC2520=m
CONFIG_IEEE802154_ATUSB=m
CONFIG_IEEE802154_ADF7242=m
CONFIG_IEEE802154_CA8210=m
CONFIG_IEEE802154_CA8210_DEBUGFS=y
CONFIG_IEEE802154_MCR20A=m
CONFIG_IEEE802154_HWSIM=m

#
# Wireless WAN
#
CONFIG_WWAN=m
CONFIG_WWAN_DEBUGFS=y
CONFIG_WWAN_HWSIM=m
CONFIG_MHI_WWAN_CTRL=m
CONFIG_MHI_WWAN_MBIM=m
CONFIG_RPMSG_WWAN_CTRL=m
CONFIG_IOSM=m
CONFIG_MTK_T7XX=m
# end of Wireless WAN

CONFIG_VMXNET3=m
# CONFIG_FUJITSU_ES is not set
CONFIG_NETDEVSIM=m
CONFIG_NET_FAILOVER=m
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_SPARSEKMAP is not set
CONFIG_INPUT_MATRIXKMAP=m
CONFIG_INPUT_VIVALDIFMAP=m

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADC is not set
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_GPIO_BUTTON_HOTPLUG is not set
CONFIG_KEYBOARD_GPIO_POLLED=y
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_PINEPHONE is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
CONFIG_KEYBOARD_SUN4I_LRADC=y
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_KEYBOARD_CYPRESS_SF is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=m
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
CONFIG_MOUSE_PS2_SENTELIC=y
CONFIG_MOUSE_PS2_TOUCHKIT=y
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_SMBUS=y
CONFIG_MOUSE_SERIAL=m
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=m
CONFIG_MOUSE_ELAN_I2C=m
CONFIG_MOUSE_ELAN_I2C_I2C=y
CONFIG_MOUSE_ELAN_I2C_SMBUS=y
CONFIG_MOUSE_VSXXXAA=m
CONFIG_MOUSE_GPIO=m
CONFIG_MOUSE_SYNAPTICS_I2C=m
CONFIG_MOUSE_SYNAPTICS_USB=m
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_ANALOG=m
CONFIG_JOYSTICK_A3D=m
CONFIG_JOYSTICK_ADC=m
CONFIG_JOYSTICK_ADI=m
CONFIG_JOYSTICK_COBRA=m
CONFIG_JOYSTICK_GF2K=m
CONFIG_JOYSTICK_GRIP=m
CONFIG_JOYSTICK_GRIP_MP=m
CONFIG_JOYSTICK_GUILLEMOT=m
CONFIG_JOYSTICK_INTERACT=m
CONFIG_JOYSTICK_SIDEWINDER=m
CONFIG_JOYSTICK_TMDC=m
CONFIG_JOYSTICK_IFORCE=m
CONFIG_JOYSTICK_IFORCE_USB=m
CONFIG_JOYSTICK_IFORCE_232=m
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
CONFIG_JOYSTICK_STINGER=m
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
CONFIG_JOYSTICK_AS5011=m
CONFIG_JOYSTICK_JOYDUMP=m
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_JOYSTICK_PSXPAD_SPI=m
CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
CONFIG_JOYSTICK_PXRC=m
CONFIG_JOYSTICK_QWIIC=m
CONFIG_JOYSTICK_FSIA6B=m
CONFIG_JOYSTICK_SENSEHAT=m
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=m
CONFIG_TOUCHSCREEN_AD7877=m
CONFIG_TOUCHSCREEN_AD7879=m
CONFIG_TOUCHSCREEN_AD7879_I2C=m
CONFIG_TOUCHSCREEN_AD7879_SPI=m
CONFIG_TOUCHSCREEN_ADC=m
CONFIG_TOUCHSCREEN_AR1021_I2C=m
CONFIG_TOUCHSCREEN_ATMEL_MXT=m
CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y
CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
CONFIG_TOUCHSCREEN_BU21013=m
CONFIG_TOUCHSCREEN_BU21029=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
CONFIG_TOUCHSCREEN_CY8CTMA140=m
CONFIG_TOUCHSCREEN_CY8CTMG110=m
CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
# CONFIG_TOUCHSCREEN_CYTTSP5 is not set
CONFIG_TOUCHSCREEN_DYNAPRO=m
CONFIG_TOUCHSCREEN_HAMPSHIRE=m
CONFIG_TOUCHSCREEN_EETI=m
CONFIG_TOUCHSCREEN_EGALAX=m
CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
CONFIG_TOUCHSCREEN_EXC3000=m
CONFIG_TOUCHSCREEN_FUJITSU=m
CONFIG_TOUCHSCREEN_GOODIX=m
CONFIG_TOUCHSCREEN_HIDEEP=m
CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
# CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set
CONFIG_TOUCHSCREEN_ILI210X=m
CONFIG_TOUCHSCREEN_ILITEK=m
CONFIG_TOUCHSCREEN_S6SY761=m
CONFIG_TOUCHSCREEN_GUNZE=m
CONFIG_TOUCHSCREEN_EKTF2127=m
CONFIG_TOUCHSCREEN_ELAN=m
CONFIG_TOUCHSCREEN_ELO=m
CONFIG_TOUCHSCREEN_WACOM_W8001=m
CONFIG_TOUCHSCREEN_WACOM_I2C=m
CONFIG_TOUCHSCREEN_MAX11801=m
CONFIG_TOUCHSCREEN_MCS5000=m
CONFIG_TOUCHSCREEN_MMS114=m
CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
CONFIG_TOUCHSCREEN_MSG2638=m
CONFIG_TOUCHSCREEN_MTOUCH=m
# CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS is not set
CONFIG_TOUCHSCREEN_IMAGIS=m
CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
CONFIG_TOUCHSCREEN_INEXIO=m
CONFIG_TOUCHSCREEN_PENMOUNT=m
CONFIG_TOUCHSCREEN_EDT_FT5X06=m
CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
CONFIG_TOUCHSCREEN_TOUCHWIN=m
CONFIG_TOUCHSCREEN_PIXCIR=m
CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
CONFIG_TOUCHSCREEN_WM97XX=m
CONFIG_TOUCHSCREEN_WM9705=y
CONFIG_TOUCHSCREEN_WM9712=y
CONFIG_TOUCHSCREEN_WM9713=y
CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
CONFIG_TOUCHSCREEN_TOUCHIT213=m
CONFIG_TOUCHSCREEN_TSC_SERIO=m
CONFIG_TOUCHSCREEN_TSC200X_CORE=m
CONFIG_TOUCHSCREEN_TSC2004=m
CONFIG_TOUCHSCREEN_TSC2005=m
CONFIG_TOUCHSCREEN_TSC2007=m
CONFIG_TOUCHSCREEN_TSC2007_IIO=y
CONFIG_TOUCHSCREEN_RM_TS=m
CONFIG_TOUCHSCREEN_SILEAD=m
CONFIG_TOUCHSCREEN_SIS_I2C=m
CONFIG_TOUCHSCREEN_ST1232=m
CONFIG_TOUCHSCREEN_STMFTS=m
CONFIG_TOUCHSCREEN_SUN4I=y
CONFIG_TOUCHSCREEN_SUR40=m
CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
CONFIG_TOUCHSCREEN_SX8654=m
CONFIG_TOUCHSCREEN_TPS6507X=m
CONFIG_TOUCHSCREEN_ZET6223=m
CONFIG_TOUCHSCREEN_ZFORCE=m
CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
CONFIG_TOUCHSCREEN_ROHM_BU21023=m
CONFIG_TOUCHSCREEN_IQS5XX=m
# CONFIG_TOUCHSCREEN_IQS7211 is not set
CONFIG_TOUCHSCREEN_ZINITIX=m
# CONFIG_TOUCHSCREEN_HIMAX_HX83112B is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
# CONFIG_INPUT_BMA150 is not set
# CONFIG_INPUT_E3X0_BUTTON is not set
# CONFIG_INPUT_MMA8450 is not set
CONFIG_INPUT_GPIO_BEEPER=m
CONFIG_INPUT_GPIO_DECODER=m
CONFIG_INPUT_GPIO_VIBRA=m
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
# CONFIG_INPUT_KXTJ9 is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
CONFIG_INPUT_CM109=m
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
CONFIG_INPUT_AXP20X_PEK=y
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_PCF8574 is not set
CONFIG_INPUT_PWM_BEEPER=m
CONFIG_INPUT_PWM_VIBRA=m
CONFIG_INPUT_RK805_PWRKEY=y
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_DA7280_HAPTICS is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_IBM_PANEL is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_INPUT_IQS269A is not set
# CONFIG_INPUT_IQS626A is not set
# CONFIG_INPUT_IQS7222 is not set
# CONFIG_INPUT_CMA3000 is not set
# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
# CONFIG_INPUT_DRV260X_HAPTICS is not set
# CONFIG_INPUT_DRV2665_HAPTICS is not set
# CONFIG_INPUT_DRV2667_HAPTICS is not set
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=y
CONFIG_RMI4_SPI=y
CONFIG_RMI4_SMB=y
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=y
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
CONFIG_RMI4_F3A=y
CONFIG_RMI4_F54=y
CONFIG_RMI4_F55=y

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=m
# CONFIG_SERIO_AMBAKMI is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=m
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
CONFIG_SERIO_SUN4I_PS2=y
# CONFIG_SERIO_GPIO_PS2 is not set
# CONFIG_USERIO is not set
CONFIG_GAMEPORT=m
# CONFIG_GAMEPORT_EMU10K1 is not set
# CONFIG_GAMEPORT_FM801 is not set
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_LEGACY_TIOCSTI=y
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=5
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
# CONFIG_SERIAL_8250_PCI1XXXX is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_RSA is not set
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
# CONFIG_SERIAL_8250_DFL is not set
CONFIG_SERIAL_8250_DW=y
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_8250_PERICOM=y
CONFIG_SERIAL_OF_PLATFORM=y

#
# Non-8250 serial port support
#
CONFIG_SERIAL_AMBA_PL010=y
CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set
CONFIG_SERIAL_MESON=y
CONFIG_SERIAL_MESON_CONSOLE=y
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_SIFIVE is not set
# CONFIG_SERIAL_QE is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
# CONFIG_SERIAL_FSL_LINFLEXUART is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_SPRD is not set
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_NOZOMI is not set
# CONFIG_NULL_TTY is not set
CONFIG_HVC_DRIVER=y
# CONFIG_HVC_DCC is not set
# CONFIG_RPMSG_TTY is not set
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_TTY_PRINTK is not set
CONFIG_VIRTIO_CONSOLE=m
# CONFIG_IPMI_HANDLER is not set
# CONFIG_SSIF_IPMI_BMC is not set
# CONFIG_IPMB_DEVICE_INTERFACE is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=y
# CONFIG_HW_RANDOM_BA431 is not set
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_ROCKCHIP=y
CONFIG_HW_RANDOM_ROCKCHIP_RK3568=y
CONFIG_HW_RANDOM_MESON=y
CONFIG_HW_RANDOM_OPTEE=y
# CONFIG_HW_RANDOM_CCTRNG is not set
# CONFIG_HW_RANDOM_XIPHERA is not set
CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
CONFIG_HW_RANDOM_CN10K=y
# CONFIG_APPLICOM is not set
CONFIG_DEVMEM=y
CONFIG_DEVPORT=y
# CONFIG_TCG_TPM is not set
# CONFIG_XILLYBUS is not set
# CONFIG_XILLYUSB is not set
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_I2C_MUX_GPIO=y
CONFIG_I2C_MUX_GPMUX=y
CONFIG_I2C_MUX_LTC4306=m
CONFIG_I2C_MUX_PCA9541=m
CONFIG_I2C_MUX_PCA954x=m
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_MUX_REG=y
CONFIG_I2C_DEMUX_PINCTRL=y
CONFIG_I2C_MUX_MLXCPLD=m
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_ALGOBIT=y

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
CONFIG_I2C_CCGX_UCSI=m
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_AMD_MP2 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_NVIDIA_GPU is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set

#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_CADENCE is not set
# CONFIG_I2C_CBUS_GPIO is not set
CONFIG_I2C_DESIGNWARE_CORE=y
CONFIG_I2C_DESIGNWARE_SLAVE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_DESIGNWARE_PCI=m
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_GPIO=y
CONFIG_I2C_GPIO_FAULT_INJECTOR=y
# CONFIG_I2C_HISI is not set
CONFIG_I2C_MESON=y
CONFIG_I2C_MV64XXX=y
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
CONFIG_I2C_RK3X=y
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_THUNDERX is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_CP2615 is not set
# CONFIG_I2C_PCI1XXXX is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_MLXCPLD is not set
CONFIG_I2C_VIRTIO=m
# end of I2C Hardware Bus support

# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=m
CONFIG_I2C_SLAVE_TESTUNIT=m
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# end of I2C support

# CONFIG_I3C is not set
CONFIG_SPI=y
CONFIG_SPI_DEBUG=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y

#
# SPI Master Controller Drivers
#
CONFIG_SPI_ALTERA=m
CONFIG_SPI_ALTERA_CORE=m
# CONFIG_SPI_ALTERA_DFL is not set
CONFIG_SPI_AMLOGIC_SPIFC_A1=m
CONFIG_SPI_AXI_SPI_ENGINE=m
CONFIG_SPI_BITBANG=m
CONFIG_SPI_CADENCE=m
CONFIG_SPI_CADENCE_QUADSPI=m
CONFIG_SPI_CADENCE_XSPI=m
CONFIG_SPI_DESIGNWARE=m
CONFIG_SPI_DW_DMA=y
# CONFIG_SPI_DW_PCI is not set
CONFIG_SPI_DW_MMIO=m
# CONFIG_SPI_HISI_KUNPENG is not set
# CONFIG_SPI_HISI_SFC_V3XX is not set
CONFIG_SPI_GPIO=m
CONFIG_SPI_FSL_LIB=m
CONFIG_SPI_FSL_SPI=m
CONFIG_SPI_MESON_SPICC=y
CONFIG_SPI_MESON_SPIFC=y
# CONFIG_SPI_MICROCHIP_CORE is not set
# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
CONFIG_SPI_OC_TINY=m
# CONFIG_SPI_PCI1XXXX is not set
CONFIG_SPI_PL022=m
CONFIG_SPI_PXA2XX=m
CONFIG_SPI_PXA2XX_PCI=m
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_ROCKCHIP_SFC=m
CONFIG_SPI_SC18IS602=m
CONFIG_SPI_SIFIVE=m
# CONFIG_SPI_SN_F_OSPI is not set
CONFIG_SPI_SUN4I=y
CONFIG_SPI_SUN6I=y
CONFIG_SPI_MXIC=m
CONFIG_SPI_THUNDERX=m
CONFIG_SPI_XCOMM=m
CONFIG_SPI_XILINX=m
CONFIG_SPI_ZYNQMP_GQSPI=m
CONFIG_SPI_AMD=m

#
# SPI Multiplexer support
#
CONFIG_SPI_MUX=m

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=m
CONFIG_SPI_LOOPBACK_TEST=m
CONFIG_SPI_TLE62X0=m
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_DYNAMIC=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set
# CONFIG_NTP_PPS is not set

#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
# CONFIG_PPS_CLIENT_LDISC is not set
# CONFIG_PPS_CLIENT_GPIO is not set

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
CONFIG_PTP_1588_CLOCK_KVM=m
# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
# CONFIG_PTP_1588_CLOCK_IDTCM is not set
# CONFIG_PTP_1588_CLOCK_MOCK is not set
# CONFIG_PTP_1588_CLOCK_OCP is not set
# CONFIG_PTP_DFL_TOD is not set
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
# CONFIG_PINCTRL_AMD is not set
CONFIG_PINCTRL_AXP209=y
# CONFIG_PINCTRL_CY8C95X0 is not set
CONFIG_PINCTRL_MCP23S08_I2C=m
CONFIG_PINCTRL_MCP23S08_SPI=m
CONFIG_PINCTRL_MCP23S08=m
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
# CONFIG_PINCTRL_OCELOT is not set
CONFIG_PINCTRL_RK805=y
CONFIG_PINCTRL_ROCKCHIP=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_PINCTRL_STMFX=m
# CONFIG_PINCTRL_SX150X is not set
CONFIG_PINCTRL_MESON=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_PINCTRL_MESON8_PMX=y
CONFIG_PINCTRL_MESON_AXG=y
CONFIG_PINCTRL_MESON_AXG_PMX=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_PINCTRL_MESON_A1=y
CONFIG_PINCTRL_MESON_S4=y
CONFIG_PINCTRL_AMLOGIC_C3=y

#
# Renesas pinctrl drivers
#
# end of Renesas pinctrl drivers

CONFIG_PINCTRL_SUNXI=y
CONFIG_PINCTRL_SUN4I_A10=y
CONFIG_PINCTRL_SUN5I=y
CONFIG_PINCTRL_SUN6I_A31=y
CONFIG_PINCTRL_SUN6I_A31_R=y
CONFIG_PINCTRL_SUN8I_A23=y
CONFIG_PINCTRL_SUN8I_A33=y
CONFIG_PINCTRL_SUN8I_A83T=y
CONFIG_PINCTRL_SUN8I_A83T_R=y
CONFIG_PINCTRL_SUN8I_A23_R=y
CONFIG_PINCTRL_SUN8I_H3=y
CONFIG_PINCTRL_SUN8I_H3_R=y
CONFIG_PINCTRL_SUN8I_V3S=y
CONFIG_PINCTRL_SUN9I_A80=y
CONFIG_PINCTRL_SUN9I_A80_R=y
CONFIG_PINCTRL_SUN20I_D1=y
CONFIG_PINCTRL_SUN50I_A64=y
CONFIG_PINCTRL_SUN50I_A64_R=y
CONFIG_PINCTRL_SUN50I_A100=y
CONFIG_PINCTRL_SUN50I_A100_R=y
CONFIG_PINCTRL_SUN50I_H5=y
CONFIG_PINCTRL_SUN50I_H6=y
CONFIG_PINCTRL_SUN50I_H6_R=y
CONFIG_PINCTRL_SUN50I_H616=y
CONFIG_PINCTRL_SUN50I_H616_R=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIO_ACPI=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_MAX730X=m

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
# CONFIG_GPIO_ALTERA is not set
# CONFIG_GPIO_AMDPT is not set
# CONFIG_GPIO_CADENCE is not set
# CONFIG_GPIO_DWAPB is not set
# CONFIG_GPIO_FTGPIO010 is not set
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_GPIO_GRGPIO is not set
# CONFIG_GPIO_HISI is not set
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_LOGICVC is not set
# CONFIG_GPIO_MB86S7X is not set
CONFIG_GPIO_PL061=y
CONFIG_GPIO_ROCKCHIP=y
# CONFIG_GPIO_SIFIVE is not set
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_XGENE=y
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
CONFIG_GPIO_ADNP=m
# CONFIG_GPIO_FXL6408 is not set
# CONFIG_GPIO_DS4520 is not set
CONFIG_GPIO_GW_PLD=m
CONFIG_GPIO_MAX7300=m
CONFIG_GPIO_MAX732X=m
CONFIG_GPIO_PCA953X=m
# CONFIG_GPIO_PCA953X_IRQ is not set
CONFIG_GPIO_PCA9570=m
CONFIG_GPIO_PCF857X=m
CONFIG_GPIO_TPIC2810=m
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
# CONFIG_GPIO_BT8XX is not set
# CONFIG_GPIO_PCI_IDIO_16 is not set
# CONFIG_GPIO_PCIE_IDIO_24 is not set
# CONFIG_GPIO_RDC321X is not set
# end of PCI GPIO expanders

#
# SPI GPIO expanders
#
CONFIG_GPIO_74X164=m
CONFIG_GPIO_MAX3191X=m
CONFIG_GPIO_MAX7301=m
CONFIG_GPIO_MC33880=m
CONFIG_GPIO_PISOSR=m
CONFIG_GPIO_XRA1403=m
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
# end of USB GPIO expanders

#
# Virtual GPIO drivers
#
CONFIG_GPIO_AGGREGATOR=m
# CONFIG_GPIO_LATCH is not set
CONFIG_GPIO_MOCKUP=m
CONFIG_GPIO_VIRTIO=m
CONFIG_GPIO_SIM=m
# end of Virtual GPIO drivers

#
# Other GPIO expanders
#
# CONFIG_GPIO_CASCADE is not set
CONFIG_W1=m
CONFIG_W1_CON=y

#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_MATROX=m
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
CONFIG_W1_MASTER_GPIO=m
CONFIG_W1_MASTER_SGI=m
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
CONFIG_W1_SLAVE_DS2405=m
CONFIG_W1_SLAVE_DS2408=m
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
CONFIG_W1_SLAVE_DS2805=m
CONFIG_W1_SLAVE_DS2430=m
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
CONFIG_W1_SLAVE_DS2438=m
CONFIG_W1_SLAVE_DS250X=m
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
CONFIG_W1_SLAVE_DS28E17=m
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_BRCMSTB=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
# CONFIG_POWER_RESET_ODROID_GO_ULTRA_POWEROFF is not set
CONFIG_POWER_RESET_LTC2952=y
CONFIG_POWER_RESET_REGULATOR=y
CONFIG_POWER_RESET_RESTART=y
CONFIG_POWER_RESET_VEXPRESS=y
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_REBOOT_MODE=y
CONFIG_SYSCON_REBOOT_MODE=y
CONFIG_NVMEM_REBOOT_MODE=y
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_POWER_SUPPLY_HWMON=y
# CONFIG_GENERIC_ADC_BATTERY is not set
# CONFIG_IP5XXX_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SAMSUNG_SDI is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_MANAGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_CHARGER_AXP20X is not set
# CONFIG_BATTERY_AXP20X is not set
CONFIG_AXP20X_POWER=y
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_BATTERY_MAX1721X is not set
# CONFIG_CHARGER_ISP1704 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
CONFIG_CHARGER_GPIO=m
CONFIG_CHARGER_MANAGER=m
CONFIG_CHARGER_LT3651=m
CONFIG_CHARGER_LTC4162L=m
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
# CONFIG_CHARGER_MAX77976 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_BQ2515X is not set
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_BQ25980 is not set
# CONFIG_CHARGER_BQ256XX is not set
CONFIG_CHARGER_RK817=y
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
# CONFIG_BATTERY_GOLDFISH is not set
# CONFIG_BATTERY_RT5033 is not set
# CONFIG_CHARGER_RT9455 is not set
# CONFIG_CHARGER_RT9467 is not set
# CONFIG_CHARGER_RT9471 is not set
# CONFIG_CHARGER_UCS1002 is not set
# CONFIG_CHARGER_BD99954 is not set
# CONFIG_BATTERY_UG3105 is not set
CONFIG_HWMON=y
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7314 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM1177 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7310 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_AHT10 is not set
# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
# CONFIG_SENSORS_AS370 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
CONFIG_SENSORS_ARM_SCMI=m
CONFIG_SENSORS_ARM_SCPI=y
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_CORSAIR_CPRO is not set
# CONFIG_SENSORS_CORSAIR_PSU is not set
# CONFIG_SENSORS_DRIVETEMP is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_I5K_AMB is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_FTSTEUTATES is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_G762 is not set
CONFIG_SENSORS_GPIO_FAN=m
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_HS3001 is not set
# CONFIG_SENSORS_IIO_HWMON is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_POWR1220 is not set
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LTC2945 is not set
# CONFIG_SENSORS_LTC2947_I2C is not set
# CONFIG_SENSORS_LTC2947_SPI is not set
# CONFIG_SENSORS_LTC2990 is not set
# CONFIG_SENSORS_LTC2992 is not set
# CONFIG_SENSORS_LTC4151 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4222 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LTC4260 is not set
# CONFIG_SENSORS_LTC4261 is not set
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX127 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX197 is not set
# CONFIG_SENSORS_MAX31722 is not set
# CONFIG_SENSORS_MAX31730 is not set
# CONFIG_SENSORS_MAX31760 is not set
# CONFIG_MAX31827 is not set
# CONFIG_SENSORS_MAX6620 is not set
# CONFIG_SENSORS_MAX6621 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MAX6697 is not set
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MC34VR500 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_TPS23861 is not set
# CONFIG_SENSORS_MR75203 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LM95234 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_NCT6683 is not set
# CONFIG_SENSORS_NCT6775 is not set
# CONFIG_SENSORS_NCT6775_I2C is not set
# CONFIG_SENSORS_NCT7802 is not set
# CONFIG_SENSORS_NCT7904 is not set
# CONFIG_SENSORS_NPCM7XX is not set
# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
# CONFIG_SENSORS_NZXT_SMART2 is not set
# CONFIG_SENSORS_OCC_P8_I2C is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_PMBUS is not set
CONFIG_SENSORS_PWM_FAN=m
# CONFIG_SENSORS_SBTSI is not set
# CONFIG_SENSORS_SBRMI is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHT4x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC2305 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_ADS7871 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA238 is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_TMP464 is not set
# CONFIG_SENSORS_TMP513 is not set
# CONFIG_SENSORS_VEXPRESS is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83773G is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set

#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
# CONFIG_THERMAL_GOV_USER_SPACE is not set
# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
# CONFIG_THERMAL_EMULATION is not set
CONFIG_THERMAL_MMIO=y
CONFIG_SUN8I_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_AMLOGIC_THERMAL=y
CONFIG_GENERIC_ADC_THERMAL=m
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set
# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=m
# CONFIG_GPIO_WATCHDOG is not set
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_XILINX_WINDOW_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
CONFIG_ARM_SP805_WATCHDOG=m
CONFIG_ARM_SBSA_WATCHDOG=y
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_DW_WATCHDOG=m
CONFIG_SUNXI_WATCHDOG=m
# CONFIG_MAX63XX_WATCHDOG is not set
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_WATCHDOG=m
# CONFIG_ARM_SMC_WATCHDOG is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_HP_WATCHDOG is not set
# CONFIG_MEN_A21_WDT is not set

#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
CONFIG_BCMA_HOST_PCI=y
CONFIG_BCMA_HOST_SOC=y
CONFIG_BCMA_DRIVER_PCI=y
CONFIG_BCMA_SFLASH=y
CONFIG_BCMA_DRIVER_GMAC_CMN=y
CONFIG_BCMA_DRIVER_GPIO=y
CONFIG_BCMA_DEBUG=y

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_SMPRO is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
CONFIG_MFD_AC100=y
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
# CONFIG_MFD_CS42L43_I2C is not set
# CONFIG_MFD_MADERA is not set
# CONFIG_MFD_MAX5970 is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_GATEWORKS_GSC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_MFD_MP2629 is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_MFD_IQS62X is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77541 is not set
# CONFIG_MFD_MAX77620 is not set
# CONFIG_MFD_MAX77650 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77714 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6360 is not set
# CONFIG_MFD_MT6370 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_MFD_OCELOT is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_NTXEC is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_SY7636A is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RT4831 is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RT5120 is not set
# CONFIG_MFD_RC5T583 is not set
CONFIG_MFD_RK8XX=y
CONFIG_MFD_RK8XX_I2C=y
CONFIG_MFD_RK8XX_SPI=y
# CONFIG_MFD_RN5T618 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
CONFIG_MFD_SIMPLE_MFD_I2C=m
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_STMPE is not set
CONFIG_MFD_SUN6I_PRCM=y
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TI_LP87565 is not set
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS65219 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS6594_I2C is not set
# CONFIG_MFD_TPS6594_SPI is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TQMX86 is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_LOCHNAGAR is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_ROHM_BD718XX is not set
# CONFIG_MFD_ROHM_BD71828 is not set
# CONFIG_MFD_ROHM_BD957XMUF is not set
# CONFIG_MFD_STPMIC1 is not set
CONFIG_MFD_STMFX=m
# CONFIG_MFD_ATC260X_I2C is not set
# CONFIG_MFD_KHADAS_MCU is not set
# CONFIG_MFD_QCOM_PM8008 is not set
# CONFIG_MFD_VEXPRESS_SYSREG is not set
# CONFIG_RAVE_SP_CORE is not set
# CONFIG_MFD_INTEL_M10_BMC_SPI is not set
# CONFIG_MFD_INTEL_M10_BMC_PMCI is not set
# CONFIG_MFD_RSMU_I2C is not set
# CONFIG_MFD_RSMU_SPI is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_88PG86X is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_AD5398 is not set
CONFIG_REGULATOR_ARM_SCMI=y
# CONFIG_REGULATOR_AW37503 is not set
CONFIG_REGULATOR_AXP20X=y
# CONFIG_REGULATOR_DA9121 is not set
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_FAN53880=y
CONFIG_REGULATOR_GPIO=y
# CONFIG_REGULATOR_ISL9305 is not set
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_LP8755 is not set
# CONFIG_REGULATOR_LTC3589 is not set
# CONFIG_REGULATOR_LTC3676 is not set
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX77857 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8893 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_MAX8973 is not set
# CONFIG_REGULATOR_MAX20086 is not set
# CONFIG_REGULATOR_MAX20411 is not set
# CONFIG_REGULATOR_MAX77826 is not set
# CONFIG_REGULATOR_MCP16502 is not set
# CONFIG_REGULATOR_MP5416 is not set
# CONFIG_REGULATOR_MP8859 is not set
# CONFIG_REGULATOR_MP886X is not set
# CONFIG_REGULATOR_MPQ7920 is not set
# CONFIG_REGULATOR_MT6311 is not set
# CONFIG_REGULATOR_MT6315 is not set
# CONFIG_REGULATOR_PCA9450 is not set
# CONFIG_REGULATOR_PF8X00 is not set
# CONFIG_REGULATOR_PFUZE100 is not set
# CONFIG_REGULATOR_PV88060 is not set
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
CONFIG_REGULATOR_PWM=y
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
# CONFIG_REGULATOR_RAA215300 is not set
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
CONFIG_REGULATOR_RK808=y
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RT4803 is not set
# CONFIG_REGULATOR_RT5190A is not set
# CONFIG_REGULATOR_RT5739 is not set
# CONFIG_REGULATOR_RT5759 is not set
# CONFIG_REGULATOR_RT6160 is not set
# CONFIG_REGULATOR_RT6190 is not set
# CONFIG_REGULATOR_RT6245 is not set
# CONFIG_REGULATOR_RTQ2134 is not set
# CONFIG_REGULATOR_RTMV20 is not set
# CONFIG_REGULATOR_RTQ6752 is not set
# CONFIG_REGULATOR_RTQ2208 is not set
# CONFIG_REGULATOR_SLG51000 is not set
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
# CONFIG_REGULATOR_SY8827N is not set
# CONFIG_REGULATOR_TPS51632 is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS6286X is not set
# CONFIG_REGULATOR_TPS6287X is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_TPS6524X is not set
CONFIG_REGULATOR_VCTRL=y
# CONFIG_REGULATOR_VEXPRESS is not set
# CONFIG_REGULATOR_QCOM_LABIBB is not set
CONFIG_RC_CORE=y
# CONFIG_BPF_LIRC_MODE2 is not set
CONFIG_LIRC=y
CONFIG_RC_MAP=y
CONFIG_RC_DECODERS=y
CONFIG_IR_IMON_DECODER=m
CONFIG_IR_JVC_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
CONFIG_IR_RCMM_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_XMP_DECODER=m
CONFIG_RC_DEVICES=y
# CONFIG_IR_ENE is not set
# CONFIG_IR_FINTEK is not set
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_GPIO_TX=m
CONFIG_IR_HIX5HD2=m
CONFIG_IR_IGORPLUGUSB=m
CONFIG_IR_IGUANA=m
CONFIG_IR_IMON=m
CONFIG_IR_IMON_RAW=m
# CONFIG_IR_ITE_CIR is not set
CONFIG_IR_MCEUSB=m
CONFIG_IR_MESON=m
CONFIG_IR_MESON_TX=m
# CONFIG_IR_NUVOTON is not set
CONFIG_IR_PWM_TX=m
CONFIG_IR_REDRAT3=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m
CONFIG_IR_SUNXI=m
CONFIG_IR_TOY=m
CONFIG_IR_TTUSBIR=m
CONFIG_RC_ATI_REMOTE=m
CONFIG_RC_LOOPBACK=m
CONFIG_RC_XBOX_DVD=m
CONFIG_CEC_CORE=y
CONFIG_CEC_NOTIFIER=y

#
# CEC support
#
CONFIG_MEDIA_CEC_RC=y
CONFIG_MEDIA_CEC_SUPPORT=y
CONFIG_CEC_CH7322=m
CONFIG_CEC_MESON_AO=y
CONFIG_CEC_MESON_G12A_AO=y
CONFIG_USB_PULSE8_CEC=m
CONFIG_USB_RAINSHADOW_CEC=m
# end of CEC support

CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_SUPPORT_FILTER=y
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_SDR_SUPPORT is not set
CONFIG_MEDIA_PLATFORM_SUPPORT=y
# CONFIG_MEDIA_TEST_SUPPORT is not set
# end of Media device types

CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CONTROLLER=y

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_ADV_DEBUG=y
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_H264=m
CONFIG_V4L2_VP9=m
CONFIG_V4L2_MEM2MEM_DEV=m
# CONFIG_V4L2_FLASH_LED_CLASS is not set
CONFIG_V4L2_FWNODE=y
CONFIG_V4L2_ASYNC=y
CONFIG_V4L2_CCI=m
CONFIG_V4L2_CCI_I2C=m
# end of Video4Linux options

#
# Media controller options
#
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
# end of Media controller options

#
# Media drivers
#

#
# Drivers filtered as selected at 'Filter media drivers'
#

#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_GSPCA=m
CONFIG_USB_GSPCA_BENQ=m
CONFIG_USB_GSPCA_CONEX=m
CONFIG_USB_GSPCA_CPIA1=m
CONFIG_USB_GSPCA_DTCS033=m
CONFIG_USB_GSPCA_ETOMS=m
CONFIG_USB_GSPCA_FINEPIX=m
CONFIG_USB_GSPCA_JEILINJ=m
CONFIG_USB_GSPCA_JL2005BCD=m
CONFIG_USB_GSPCA_KINECT=m
CONFIG_USB_GSPCA_KONICA=m
CONFIG_USB_GSPCA_MARS=m
CONFIG_USB_GSPCA_MR97310A=m
CONFIG_USB_GSPCA_NW80X=m
CONFIG_USB_GSPCA_OV519=m
CONFIG_USB_GSPCA_OV534=m
CONFIG_USB_GSPCA_OV534_9=m
CONFIG_USB_GSPCA_PAC207=m
CONFIG_USB_GSPCA_PAC7302=m
CONFIG_USB_GSPCA_PAC7311=m
CONFIG_USB_GSPCA_SE401=m
CONFIG_USB_GSPCA_SN9C2028=m
CONFIG_USB_GSPCA_SN9C20X=m
CONFIG_USB_GSPCA_SONIXB=m
CONFIG_USB_GSPCA_SONIXJ=m
CONFIG_USB_GSPCA_SPCA1528=m
CONFIG_USB_GSPCA_SPCA500=m
CONFIG_USB_GSPCA_SPCA501=m
CONFIG_USB_GSPCA_SPCA505=m
CONFIG_USB_GSPCA_SPCA506=m
CONFIG_USB_GSPCA_SPCA508=m
CONFIG_USB_GSPCA_SPCA561=m
CONFIG_USB_GSPCA_SQ905=m
CONFIG_USB_GSPCA_SQ905C=m
CONFIG_USB_GSPCA_SQ930X=m
CONFIG_USB_GSPCA_STK014=m
CONFIG_USB_GSPCA_STK1135=m
CONFIG_USB_GSPCA_STV0680=m
CONFIG_USB_GSPCA_SUNPLUS=m
CONFIG_USB_GSPCA_T613=m
CONFIG_USB_GSPCA_TOPRO=m
CONFIG_USB_GSPCA_TOUPTEK=m
CONFIG_USB_GSPCA_TV8532=m
CONFIG_USB_GSPCA_VC032X=m
CONFIG_USB_GSPCA_VICAM=m
CONFIG_USB_GSPCA_XIRLINK_CIT=m
CONFIG_USB_GSPCA_ZC3XX=m
CONFIG_USB_GL860=m
CONFIG_USB_M5602=m
CONFIG_USB_STV06XX=m
CONFIG_USB_PWC=m
# CONFIG_USB_PWC_DEBUG is not set
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_USB_S2255=m
CONFIG_VIDEO_USBTV=m
CONFIG_USB_VIDEO_CLASS=m
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y

#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=m
CONFIG_VIDEO_EM28XX_V4L2=m
CONFIG_VIDEO_EM28XX_ALSA=m
CONFIG_VIDEO_EM28XX_RC=m
# CONFIG_MEDIA_PCI_SUPPORT is not set
CONFIG_MEDIA_PLATFORM_DRIVERS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
CONFIG_VIDEO_MUX=m

#
# Allegro DVT media platform drivers
#

#
# Amlogic media platform drivers
#
CONFIG_VIDEO_MESON_GE2D=m

#
# Amphion drivers
#

#
# Aspeed media platform drivers
#

#
# Atmel media platform drivers
#

#
# Cadence media platform drivers
#
# CONFIG_VIDEO_CADENCE_CSI2RX is not set
# CONFIG_VIDEO_CADENCE_CSI2TX is not set

#
# Chips&Media media platform drivers
#

#
# Intel media platform drivers
#

#
# Marvell media platform drivers
#
# CONFIG_VIDEO_CAFE_CCIC is not set

#
# Mediatek media platform drivers
#

#
# Microchip Technology, Inc. media platform drivers
#

#
# NVidia media platform drivers
#

#
# NXP media platform drivers
#

#
# Qualcomm media platform drivers
#

#
# Renesas media platform drivers
#

#
# Rockchip media platform drivers
#
CONFIG_VIDEO_ROCKCHIP_RGA=m
CONFIG_VIDEO_ROCKCHIP_ISP1=m

#
# Samsung media platform drivers
#

#
# STMicroelectronics media platform drivers
#

#
# Sunxi media platform drivers
#
CONFIG_VIDEO_SUN4I_CSI=m
CONFIG_VIDEO_SUN6I_CSI=m
CONFIG_VIDEO_SUN6I_MIPI_CSI2=m
CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m
CONFIG_VIDEO_SUN8I_DEINTERLACE=m
CONFIG_VIDEO_SUN8I_ROTATE=m

#
# Texas Instruments drivers
#

#
# Verisilicon media platform drivers
#
# CONFIG_VIDEO_HANTRO is not set

#
# VIA media platform drivers
#

#
# Xilinx media platform drivers
#
# CONFIG_VIDEO_XILINX is not set
CONFIG_UVC_COMMON=m
CONFIG_VIDEO_TVEEPROM=m
CONFIG_VIDEOBUF2_CORE=y
CONFIG_VIDEOBUF2_V4L2=y
CONFIG_VIDEOBUF2_MEMOPS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=y
CONFIG_VIDEOBUF2_DMA_SG=m
# end of Media drivers

#
# Media ancillary drivers
#

#
# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
#
CONFIG_VIDEO_IR_I2C=m
CONFIG_VIDEO_CAMERA_SENSOR=y
CONFIG_VIDEO_APTINA_PLL=m
CONFIG_VIDEO_CCS_PLL=m
CONFIG_VIDEO_AR0521=m
CONFIG_VIDEO_HI556=m
CONFIG_VIDEO_HI846=m
CONFIG_VIDEO_HI847=m
CONFIG_VIDEO_IMX208=m
CONFIG_VIDEO_IMX214=m
CONFIG_VIDEO_IMX219=m
CONFIG_VIDEO_IMX258=m
CONFIG_VIDEO_IMX274=m
CONFIG_VIDEO_IMX290=m
# CONFIG_VIDEO_IMX296 is not set
CONFIG_VIDEO_IMX319=m
CONFIG_VIDEO_IMX334=m
CONFIG_VIDEO_IMX335=m
CONFIG_VIDEO_IMX355=m
CONFIG_VIDEO_IMX412=m
# CONFIG_VIDEO_IMX415 is not set
CONFIG_VIDEO_MAX9271_LIB=m
CONFIG_VIDEO_MT9M001=m
CONFIG_VIDEO_MT9M111=m
CONFIG_VIDEO_MT9P031=m
CONFIG_VIDEO_MT9T112=m
CONFIG_VIDEO_MT9V011=m
CONFIG_VIDEO_MT9V032=m
CONFIG_VIDEO_MT9V111=m
CONFIG_VIDEO_OG01A1B=m
# CONFIG_VIDEO_OV01A10 is not set
CONFIG_VIDEO_OV02A10=m
CONFIG_VIDEO_OV08D10=m
# CONFIG_VIDEO_OV08X40 is not set
CONFIG_VIDEO_OV13858=m
CONFIG_VIDEO_OV13B10=m
CONFIG_VIDEO_OV2640=m
CONFIG_VIDEO_OV2659=m
CONFIG_VIDEO_OV2680=m
CONFIG_VIDEO_OV2685=m
CONFIG_VIDEO_OV2740=m
# CONFIG_VIDEO_OV4689 is not set
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_OV5647=m
CONFIG_VIDEO_OV5648=m
CONFIG_VIDEO_OV5670=m
CONFIG_VIDEO_OV5675=m
CONFIG_VIDEO_OV5693=m
CONFIG_VIDEO_OV5695=m
CONFIG_VIDEO_OV6650=m
CONFIG_VIDEO_OV7251=m
CONFIG_VIDEO_OV7640=m
CONFIG_VIDEO_OV7670=m
CONFIG_VIDEO_OV772X=m
CONFIG_VIDEO_OV7740=m
CONFIG_VIDEO_OV8856=m
# CONFIG_VIDEO_OV8858 is not set
CONFIG_VIDEO_OV8865=m
CONFIG_VIDEO_OV9282=m
CONFIG_VIDEO_OV9640=m
CONFIG_VIDEO_OV9650=m
CONFIG_VIDEO_OV9734=m
CONFIG_VIDEO_RDACM20=m
CONFIG_VIDEO_RDACM21=m
CONFIG_VIDEO_RJ54N1=m
CONFIG_VIDEO_S5C73M3=m
CONFIG_VIDEO_S5K5BAF=m
CONFIG_VIDEO_S5K6A3=m
# CONFIG_VIDEO_ST_VGXY61 is not set
CONFIG_VIDEO_CCS=m
CONFIG_VIDEO_ET8EK8=m

#
# Lens drivers
#
CONFIG_VIDEO_AD5820=m
CONFIG_VIDEO_AK7375=m
CONFIG_VIDEO_DW9714=m
# CONFIG_VIDEO_DW9719 is not set
CONFIG_VIDEO_DW9768=m
CONFIG_VIDEO_DW9807_VCM=m
# end of Lens drivers

#
# Flash devices
#
CONFIG_VIDEO_ADP1653=m
CONFIG_VIDEO_LM3560=m
CONFIG_VIDEO_LM3646=m
# end of Flash devices

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_CS3308=m
CONFIG_VIDEO_CS5345=m
CONFIG_VIDEO_CS53L32A=m
CONFIG_VIDEO_MSP3400=m
CONFIG_VIDEO_SONY_BTF_MPX=m
CONFIG_VIDEO_TDA1997X=m
CONFIG_VIDEO_TDA7432=m
CONFIG_VIDEO_TDA9840=m
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
CONFIG_VIDEO_TLV320AIC23B=m
CONFIG_VIDEO_TVAUDIO=m
CONFIG_VIDEO_UDA1342=m
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_WM8739=m
CONFIG_VIDEO_WM8775=m
# end of Audio decoders, processors and mixers

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders

#
# Video decoders
#
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_ADV7183=m
CONFIG_VIDEO_ADV748X=m
CONFIG_VIDEO_ADV7604=m
CONFIG_VIDEO_ADV7604_CEC=y
CONFIG_VIDEO_ADV7842=m
CONFIG_VIDEO_ADV7842_CEC=y
CONFIG_VIDEO_BT819=m
CONFIG_VIDEO_BT856=m
CONFIG_VIDEO_BT866=m
CONFIG_VIDEO_ISL7998X=m
CONFIG_VIDEO_KS0127=m
CONFIG_VIDEO_MAX9286=m
CONFIG_VIDEO_ML86V7667=m
CONFIG_VIDEO_SAA7110=m
CONFIG_VIDEO_SAA711X=m
CONFIG_VIDEO_TC358743=m
CONFIG_VIDEO_TC358743_CEC=y
# CONFIG_VIDEO_TC358746 is not set
CONFIG_VIDEO_TVP514X=m
CONFIG_VIDEO_TVP5150=m
CONFIG_VIDEO_TVP7002=m
CONFIG_VIDEO_TW2804=m
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=m
CONFIG_VIDEO_TW9910=m
CONFIG_VIDEO_VPX3220=m

#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=m
CONFIG_VIDEO_CX25840=m
# end of Video decoders

#
# Video encoders
#
CONFIG_VIDEO_ADV7170=m
CONFIG_VIDEO_ADV7175=m
CONFIG_VIDEO_ADV7343=m
CONFIG_VIDEO_ADV7393=m
CONFIG_VIDEO_ADV7511=m
CONFIG_VIDEO_ADV7511_CEC=y
CONFIG_VIDEO_AK881X=m
CONFIG_VIDEO_SAA7127=m
CONFIG_VIDEO_SAA7185=m
CONFIG_VIDEO_THS8200=m
# end of Video encoders

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
CONFIG_VIDEO_UPD64083=m
# end of Video improvement chips

#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips

#
# SDR tuner chips
#
# end of SDR tuner chips

#
# Miscellaneous helper chips
#
CONFIG_VIDEO_I2C=m
CONFIG_VIDEO_M52790=m
CONFIG_VIDEO_ST_MIPID02=m
CONFIG_VIDEO_THS7303=m
# end of Miscellaneous helper chips

#
# Video serializers and deserializers
#
# CONFIG_VIDEO_DS90UB913 is not set
# CONFIG_VIDEO_DS90UB953 is not set
# CONFIG_VIDEO_DS90UB960 is not set
# end of Video serializers and deserializers

#
# Media SPI Adapters
#
CONFIG_VIDEO_GS1662=m
# end of Media SPI Adapters
# end of Media ancillary drivers

#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
CONFIG_SCREEN_INFO=y
CONFIG_VIDEO_CMDLINE=y
CONFIG_VIDEO_NOMODESET=y
CONFIG_AUXDISPLAY=y
CONFIG_CHARLCD=m
CONFIG_LINEDISP=m
CONFIG_HD44780_COMMON=m
CONFIG_HD44780=m
CONFIG_IMG_ASCII_LCD=m
CONFIG_HT16K33=m
CONFIG_LCD2S=m
CONFIG_TM1628=m
CONFIG_OPENVFD=m
# CONFIG_PANEL_CHANGE_MESSAGE is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_DRM=y
CONFIG_DRM_MIPI_DBI=m
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_DEBUG_MM is not set
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=300
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
CONFIG_DRM_DP_AUX_BUS=m
CONFIG_DRM_DISPLAY_HELPER=y
CONFIG_DRM_DISPLAY_DP_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_TTM=m
CONFIG_DRM_TTM_HELPER=m
CONFIG_DRM_GEM_DMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=m
CONFIG_DRM_SCHED=m

#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# end of I2C encoder or helper chips

#
# ARM devices
#
CONFIG_DRM_HDLCD=m
CONFIG_DRM_HDLCD_SHOW_UNDERRUN=y
CONFIG_DRM_MALI_DISPLAY=m
CONFIG_DRM_KOMEDA=m
# end of ARM devices

# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_AMDGPU is not set
# CONFIG_DRM_NOUVEAU is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
CONFIG_DRM_ROCKCHIP=m
CONFIG_ROCKCHIP_VOP=y
CONFIG_ROCKCHIP_VOP2=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_INNO_HDMI=y
CONFIG_ROCKCHIP_LVDS=y
CONFIG_ROCKCHIP_RGB=y
CONFIG_ROCKCHIP_RK3066_HDMI=y
# CONFIG_DRM_VMWGFX is not set
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
CONFIG_DRM_SUN4I=y
CONFIG_DRM_SUN6I_DSI=y
CONFIG_DRM_SUN8I_DW_HDMI=y
CONFIG_DRM_SUN8I_MIXER=y
CONFIG_DRM_SUN8I_TCON_TOP=y
CONFIG_DRM_QXL=m
CONFIG_DRM_VIRTIO_GPU=m
CONFIG_DRM_VIRTIO_GPU_KMS=y
CONFIG_DRM_PANEL=y

#
# Display Panels
#
CONFIG_DRM_PANEL_ABT_Y030XX067A=m
CONFIG_DRM_PANEL_ARM_VERSATILE=m
CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set
CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
CONFIG_DRM_PANEL_DSI_CM=m
CONFIG_DRM_PANEL_LVDS=m
CONFIG_DRM_PANEL_SIMPLE=m
CONFIG_DRM_PANEL_EDP=m
CONFIG_DRM_PANEL_EBBG_FT8719=m
CONFIG_DRM_PANEL_ELIDA_KD35T133=m
CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set
CONFIG_DRM_PANEL_ILITEK_IL9322=m
CONFIG_DRM_PANEL_ILITEK_ILI9341=m
CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
CONFIG_DRM_PANEL_JDI_LT070ME05000=m
CONFIG_DRM_PANEL_JDI_R63452=m
CONFIG_DRM_PANEL_KHADAS_TS050=m
CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
CONFIG_DRM_PANEL_LG_LB035Q02=m
CONFIG_DRM_PANEL_LG_LG4573=m
# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set
CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
CONFIG_DRM_PANEL_NOVATEK_NT35510=m
CONFIG_DRM_PANEL_NOVATEK_NT35560=m
CONFIG_DRM_PANEL_NOVATEK_NT35950=m
# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set
CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
CONFIG_DRM_PANEL_NOVATEK_NT39016=m
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
CONFIG_DRM_PANEL_RONBO_RB070D30=m
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
CONFIG_DRM_PANEL_SITRONIX_ST7789V=m
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set
CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set
CONFIG_DRM_PANEL_TDO_TL070WSH30=m
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
CONFIG_DRM_PANEL_TPO_TPG110=m
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
CONFIG_DRM_PANEL_VISIONOX_RM69299=m
# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set
# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set
CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
# end of Display Panels

CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y

#
# Display Interface Bridges
#
# CONFIG_DRM_CHIPONE_ICN6211 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
CONFIG_DRM_DISPLAY_CONNECTOR=y
# CONFIG_DRM_ITE_IT6505 is not set
# CONFIG_DRM_LONTIUM_LT8912B is not set
# CONFIG_DRM_LONTIUM_LT9211 is not set
# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LONTIUM_LT9611UXC is not set
# CONFIG_DRM_ITE_IT66121 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_SAMSUNG_DSIM is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
CONFIG_DRM_SIMPLE_BRIDGE=m
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TI_DLPC3433 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_SN65DSI83 is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
CONFIG_DRM_ANALOGIX_DP=m
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
CONFIG_DRM_DW_HDMI=y
CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
CONFIG_DRM_DW_HDMI_CEC=m
CONFIG_DRM_DW_MIPI_DSI=y
# end of Display Interface Bridges

# CONFIG_DRM_LOONGSON is not set
# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_HISI_HIBMC is not set
# CONFIG_DRM_HISI_KIRIN is not set
# CONFIG_DRM_LOGICVC is not set
CONFIG_DRM_MESON=y
CONFIG_DRM_MESON_DW_HDMI=y
CONFIG_DRM_MESON_DW_MIPI_DSI=y
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_BOCHS is not set
# CONFIG_DRM_CIRRUS_QEMU is not set
# CONFIG_DRM_GM12U320 is not set
# CONFIG_DRM_PANEL_MIPI_DBI is not set
# CONFIG_DRM_SIMPLEDRM is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9163 is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_DRM_PL111 is not set
CONFIG_DRM_LIMA=m
CONFIG_DRM_PANFROST=m
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_GUD is not set
CONFIG_DRM_SSD130X=m
CONFIG_DRM_SSD130X_I2C=m
CONFIG_DRM_SSD130X_SPI=m
# CONFIG_DRM_LEGACY is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y

#
# Frame buffer Devices
#
CONFIG_FB=y
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
CONFIG_FB_ARMCLCD=y
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_UVESA is not set
CONFIG_FB_EFI=y
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
CONFIG_FB_SIMPLE=y
# CONFIG_FB_SSD1307 is not set
# CONFIG_FB_SM712 is not set
CONFIG_FB_CORE=y
CONFIG_FB_NOTIFY=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_DEVICE=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_DMAMEM_HELPERS=y
CONFIG_FB_IOMEM_FOPS=y
CONFIG_FB_IOMEM_HELPERS=y
CONFIG_FB_SYSMEM_HELPERS=y
CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
CONFIG_FB_BACKLIGHT=m
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=m
CONFIG_LCD_L4F00242T03=m
CONFIG_LCD_LMS283GF05=m
CONFIG_LCD_LTV350QV=m
CONFIG_LCD_ILI922X=m
CONFIG_LCD_ILI9320=m
CONFIG_LCD_TDO24M=m
CONFIG_LCD_VGG2432A4=m
CONFIG_LCD_PLATFORM=m
CONFIG_LCD_AMS369FG06=m
CONFIG_LCD_LMS501KF03=m
CONFIG_LCD_HX8357=m
CONFIG_LCD_OTM3225A=m
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_KTD253=m
# CONFIG_BACKLIGHT_KTZ8866 is not set
CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_QCOM_WLED=m
CONFIG_BACKLIGHT_ADP8860=m
CONFIG_BACKLIGHT_ADP8870=m
CONFIG_BACKLIGHT_LM3630A=m
CONFIG_BACKLIGHT_LM3639=m
CONFIG_BACKLIGHT_LP855X=m
CONFIG_BACKLIGHT_GPIO=y
CONFIG_BACKLIGHT_LV5207LP=m
CONFIG_BACKLIGHT_BD6107=m
CONFIG_BACKLIGHT_ARCXCNN=m
CONFIG_BACKLIGHT_LED=y
# end of Backlight & LCD device support

CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
# end of Console display driver support

CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
# end of Graphics support

CONFIG_DRM_ACCEL=y
# CONFIG_DRM_ACCEL_QAIC is not set
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=y
CONFIG_SND_HWDEP=m
CONFIG_SND_RAWMIDI=m
CONFIG_SND_UMP=m
CONFIG_SND_UMP_LEGACY_RAWMIDI=y
CONFIG_SND_COMPRESS_OFFLOAD=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_OSSEMUL is not set
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_PROC_FS=y
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_VERBOSE_PRINTK is not set
CONFIG_SND_CTL_FAST_LOOKUP=y
# CONFIG_SND_DEBUG is not set
# CONFIG_SND_CTL_INPUT_VALIDATION is not set
CONFIG_SND_VMASTER=y
# CONFIG_SND_SEQUENCER is not set
CONFIG_SND_MPU401_UART=m
CONFIG_SND_AC97_CODEC=y
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
# CONFIG_SND_PCMTEST is not set
CONFIG_SND_MTPAV=m
CONFIG_SND_SERIAL_U16550=m
CONFIG_SND_SERIAL_GENERIC=m
CONFIG_SND_MPU401=m
# CONFIG_SND_AC97_POWER_SAVE is not set
CONFIG_SND_PCI=y
# CONFIG_SND_AD1889 is not set
# CONFIG_SND_ALS300 is not set
# CONFIG_SND_ALI5451 is not set
# CONFIG_SND_ATIIXP is not set
# CONFIG_SND_ATIIXP_MODEM is not set
# CONFIG_SND_AU8810 is not set
# CONFIG_SND_AU8820 is not set
# CONFIG_SND_AU8830 is not set
# CONFIG_SND_AW2 is not set
# CONFIG_SND_AZT3328 is not set
# CONFIG_SND_BT87X is not set
# CONFIG_SND_CA0106 is not set
# CONFIG_SND_CMIPCI is not set
# CONFIG_SND_OXYGEN is not set
# CONFIG_SND_CS4281 is not set
# CONFIG_SND_CS46XX is not set
# CONFIG_SND_CTXFI is not set
# CONFIG_SND_DARLA20 is not set
# CONFIG_SND_GINA20 is not set
# CONFIG_SND_LAYLA20 is not set
# CONFIG_SND_DARLA24 is not set
# CONFIG_SND_GINA24 is not set
# CONFIG_SND_LAYLA24 is not set
# CONFIG_SND_MONA is not set
# CONFIG_SND_MIA is not set
# CONFIG_SND_ECHO3G is not set
# CONFIG_SND_INDIGO is not set
# CONFIG_SND_INDIGOIO is not set
# CONFIG_SND_INDIGODJ is not set
# CONFIG_SND_INDIGOIOX is not set
# CONFIG_SND_INDIGODJX is not set
# CONFIG_SND_EMU10K1 is not set
# CONFIG_SND_EMU10K1X is not set
# CONFIG_SND_ENS1370 is not set
# CONFIG_SND_ENS1371 is not set
# CONFIG_SND_ES1938 is not set
# CONFIG_SND_ES1968 is not set
# CONFIG_SND_FM801 is not set
# CONFIG_SND_HDSP is not set
# CONFIG_SND_HDSPM is not set
# CONFIG_SND_ICE1712 is not set
# CONFIG_SND_ICE1724 is not set
# CONFIG_SND_INTEL8X0 is not set
# CONFIG_SND_INTEL8X0M is not set
# CONFIG_SND_KORG1212 is not set
# CONFIG_SND_LOLA is not set
# CONFIG_SND_LX6464ES is not set
# CONFIG_SND_MAESTRO3 is not set
# CONFIG_SND_MIXART is not set
# CONFIG_SND_NM256 is not set
# CONFIG_SND_PCXHR is not set
# CONFIG_SND_RIPTIDE is not set
# CONFIG_SND_RME32 is not set
# CONFIG_SND_RME96 is not set
# CONFIG_SND_RME9652 is not set
# CONFIG_SND_SE6X is not set
# CONFIG_SND_SONICVIBES is not set
# CONFIG_SND_TRIDENT is not set
# CONFIG_SND_VIA82XX is not set
# CONFIG_SND_VIA82XX_MODEM is not set
# CONFIG_SND_VIRTUOSO is not set
# CONFIG_SND_VX222 is not set
# CONFIG_SND_YMFPCI is not set

#
# HD-Audio
#
CONFIG_SND_HDA=y
# CONFIG_SND_HDA_INTEL is not set
# CONFIG_SND_HDA_HWDEP is not set
# CONFIG_SND_HDA_RECONFIG is not set
# CONFIG_SND_HDA_INPUT_BEEP is not set
# CONFIG_SND_HDA_PATCH_LOADER is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
# CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set
# CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set
# CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set
# CONFIG_SND_HDA_CODEC_REALTEK is not set
# CONFIG_SND_HDA_CODEC_ANALOG is not set
# CONFIG_SND_HDA_CODEC_SIGMATEL is not set
# CONFIG_SND_HDA_CODEC_VIA is not set
CONFIG_SND_HDA_CODEC_HDMI=y
# CONFIG_SND_HDA_CODEC_CIRRUS is not set
# CONFIG_SND_HDA_CODEC_CS8409 is not set
# CONFIG_SND_HDA_CODEC_CONEXANT is not set
# CONFIG_SND_HDA_CODEC_CA0110 is not set
# CONFIG_SND_HDA_CODEC_CA0132 is not set
# CONFIG_SND_HDA_CODEC_CMEDIA is not set
# CONFIG_SND_HDA_CODEC_SI3054 is not set
# CONFIG_SND_HDA_GENERIC is not set
CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
# end of HD-Audio

CONFIG_SND_HDA_CORE=y
CONFIG_SND_HDA_EXT_CORE=y
CONFIG_SND_HDA_PREALLOC_SIZE=2048
# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
# CONFIG_SND_USB_AUDIO_MIDI_V2 is not set
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
CONFIG_SND_BCD2000=m
CONFIG_SND_USB_LINE6=m
CONFIG_SND_USB_POD=m
CONFIG_SND_USB_PODHD=m
CONFIG_SND_USB_TONEPORT=m
CONFIG_SND_USB_VARIAX=m
CONFIG_SND_SOC=y
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
CONFIG_SND_SOC_COMPRESS=y
# CONFIG_SND_SOC_ADI is not set
# CONFIG_SND_SOC_AMD_ACP is not set
# CONFIG_SND_AMD_ACP_CONFIG is not set
# CONFIG_SND_ATMEL_SOC is not set
# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
CONFIG_SND_DESIGNWARE_I2S=m
# CONFIG_SND_DESIGNWARE_PCM is not set

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
# CONFIG_SND_SOC_FSL_ASRC is not set
# CONFIG_SND_SOC_FSL_SAI is not set
# CONFIG_SND_SOC_FSL_AUDMIX is not set
# CONFIG_SND_SOC_FSL_SSI is not set
# CONFIG_SND_SOC_FSL_SPDIF is not set
# CONFIG_SND_SOC_FSL_ESAI is not set
# CONFIG_SND_SOC_FSL_MICFIL is not set
# CONFIG_SND_SOC_FSL_XCVR is not set
# CONFIG_SND_SOC_FSL_RPMSG is not set
# CONFIG_SND_SOC_IMX_AUDMUX is not set
# end of SoC Audio for Freescale CPUs

# CONFIG_SND_SOC_CHV3_I2S is not set
# CONFIG_SND_I2S_HI6210_I2S is not set
# CONFIG_SND_SOC_IMG is not set
# CONFIG_SND_SOC_MTK_BTCVSD is not set

#
# ASoC support for Amlogic platforms
#
CONFIG_SND_MESON_AIU=m
CONFIG_SND_MESON_AXG_FIFO=m
CONFIG_SND_MESON_AXG_FRDDR=m
CONFIG_SND_MESON_AXG_TODDR=m
CONFIG_SND_MESON_AXG_TDM_FORMATTER=m
CONFIG_SND_MESON_AXG_TDM_INTERFACE=m
CONFIG_SND_MESON_AXG_TDMIN=m
CONFIG_SND_MESON_AXG_TDMOUT=m
CONFIG_SND_MESON_AXG_SOUND_CARD=m
CONFIG_SND_MESON_AXG_SPDIFOUT=m
CONFIG_SND_MESON_AXG_SPDIFIN=m
CONFIG_SND_MESON_AXG_PDM=m
CONFIG_SND_MESON_CARD_UTILS=m
CONFIG_SND_MESON_CODEC_GLUE=m
CONFIG_SND_MESON_GX_SOUND_CARD=m
CONFIG_SND_MESON_G12A_TOACODEC=m
CONFIG_SND_MESON_G12A_TOHDMITX=m
CONFIG_SND_SOC_MESON_T9015=m
# end of ASoC support for Amlogic platforms

CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_ROCKCHIP_I2S=m
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
CONFIG_SND_SOC_ROCKCHIP_PDM=m
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
CONFIG_SND_SOC_ROCKCHIP_RT5645=m
CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m
CONFIG_SND_SOC_RK3399_GRU_SOUND=m
# CONFIG_SND_SOC_SOF_TOPLEVEL is not set

#
# STMicroelectronics STM32 SOC audio support
#
# end of STMicroelectronics STM32 SOC audio support

#
# Allwinner SoC Audio support
#
CONFIG_SND_SUN4I_CODEC=m
CONFIG_SND_SUN8I_CODEC=m
CONFIG_SND_SUN8I_CODEC_ANALOG=m
CONFIG_SND_SUN50I_CODEC_ANALOG=m
CONFIG_SND_SUN4I_I2S=m
CONFIG_SND_SUN4I_SPDIF=m
CONFIG_SND_SUN50I_DMIC=m
CONFIG_SND_SUN8I_ADDA_PR_REGMAP=m
# end of Allwinner SoC Audio support

# CONFIG_SND_SOC_XILINX_I2S is not set
# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
# CONFIG_SND_SOC_XILINX_SPDIF is not set
# CONFIG_SND_SOC_XTFPGA_I2S is not set
CONFIG_SND_SOC_I2C_AND_SPI=y

#
# CODEC drivers
#
CONFIG_SND_SOC_WM_ADSP=y
CONFIG_SND_SOC_AC97_CODEC=y
CONFIG_SND_SOC_ADAU_UTILS=m
CONFIG_SND_SOC_ADAU1372=m
CONFIG_SND_SOC_ADAU1372_I2C=m
CONFIG_SND_SOC_ADAU1372_SPI=m
CONFIG_SND_SOC_ADAU1701=m
CONFIG_SND_SOC_ADAU17X1=m
CONFIG_SND_SOC_ADAU1761=m
CONFIG_SND_SOC_ADAU1761_I2C=m
CONFIG_SND_SOC_ADAU1761_SPI=m
CONFIG_SND_SOC_ADAU7002=m
CONFIG_SND_SOC_ADAU7118=m
CONFIG_SND_SOC_ADAU7118_HW=m
CONFIG_SND_SOC_ADAU7118_I2C=m
CONFIG_SND_SOC_AK4104=y
CONFIG_SND_SOC_AK4118=y
CONFIG_SND_SOC_AK4375=y
CONFIG_SND_SOC_AK4458=y
CONFIG_SND_SOC_AK4554=y
CONFIG_SND_SOC_AK4613=y
CONFIG_SND_SOC_AK4642=y
CONFIG_SND_SOC_AK5386=y
CONFIG_SND_SOC_AK5558=y
CONFIG_SND_SOC_ALC5623=y
CONFIG_SND_SOC_AUDIO_IIO_AUX=m
CONFIG_SND_SOC_AW8738=m
CONFIG_SND_SOC_AW88395_LIB=m
CONFIG_SND_SOC_AW88395=m
CONFIG_SND_SOC_AW88261=m
CONFIG_SND_SOC_BD28623=m
CONFIG_SND_SOC_BT_SCO=m
CONFIG_SND_SOC_CHV3_CODEC=m
CONFIG_SND_SOC_CS35L32=y
CONFIG_SND_SOC_CS35L33=y
CONFIG_SND_SOC_CS35L34=y
CONFIG_SND_SOC_CS35L35=y
CONFIG_SND_SOC_CS35L36=y
CONFIG_SND_SOC_CS35L41_LIB=y
CONFIG_SND_SOC_CS35L41=y
CONFIG_SND_SOC_CS35L41_SPI=y
CONFIG_SND_SOC_CS35L41_I2C=y
CONFIG_SND_SOC_CS35L45=y
CONFIG_SND_SOC_CS35L45_SPI=y
CONFIG_SND_SOC_CS35L45_I2C=y
CONFIG_SND_SOC_CS35L56=y
CONFIG_SND_SOC_CS35L56_SHARED=y
CONFIG_SND_SOC_CS35L56_I2C=y
CONFIG_SND_SOC_CS35L56_SPI=y
CONFIG_SND_SOC_CS42L42_CORE=y
CONFIG_SND_SOC_CS42L42=y
CONFIG_SND_SOC_CS42L51=y
CONFIG_SND_SOC_CS42L51_I2C=y
CONFIG_SND_SOC_CS42L52=y
CONFIG_SND_SOC_CS42L56=y
CONFIG_SND_SOC_CS42L73=y
CONFIG_SND_SOC_CS42L83=y
CONFIG_SND_SOC_CS4234=y
CONFIG_SND_SOC_CS4265=y
CONFIG_SND_SOC_CS4270=y
CONFIG_SND_SOC_CS4271=y
CONFIG_SND_SOC_CS4271_I2C=y
CONFIG_SND_SOC_CS4271_SPI=y
CONFIG_SND_SOC_CS42XX8=y
CONFIG_SND_SOC_CS42XX8_I2C=y
CONFIG_SND_SOC_CS43130=y
CONFIG_SND_SOC_CS4341=y
CONFIG_SND_SOC_CS4349=y
CONFIG_SND_SOC_CS53L30=y
CONFIG_SND_SOC_CX2072X=m
CONFIG_SND_SOC_DA7213=m
CONFIG_SND_SOC_DA7219=m
CONFIG_SND_SOC_DMIC=m
CONFIG_SND_SOC_HDMI_CODEC=y
CONFIG_SND_SOC_ES7134=y
CONFIG_SND_SOC_ES7241=y
CONFIG_SND_SOC_ES8316=y
CONFIG_SND_SOC_ES8326=y
CONFIG_SND_SOC_ES8328=y
CONFIG_SND_SOC_ES8328_I2C=y
CONFIG_SND_SOC_ES8328_SPI=y
CONFIG_SND_SOC_GTM601=m
CONFIG_SND_SOC_HDA=y
CONFIG_SND_SOC_ICS43432=y
CONFIG_SND_SOC_IDT821034=m
CONFIG_SND_SOC_INNO_RK3036=y
CONFIG_SND_SOC_MAX98088=y
CONFIG_SND_SOC_MAX98090=m
CONFIG_SND_SOC_MAX98357A=y
CONFIG_SND_SOC_MAX98504=y
CONFIG_SND_SOC_MAX9867=y
CONFIG_SND_SOC_MAX98927=y
CONFIG_SND_SOC_MAX98520=y
CONFIG_SND_SOC_MAX98373=y
CONFIG_SND_SOC_MAX98373_I2C=y
CONFIG_SND_SOC_MAX98388=y
CONFIG_SND_SOC_MAX98390=y
CONFIG_SND_SOC_MAX98396=y
CONFIG_SND_SOC_MAX9860=y
CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
CONFIG_SND_SOC_PCM1681=y
CONFIG_SND_SOC_PCM1789=y
CONFIG_SND_SOC_PCM1789_I2C=y
CONFIG_SND_SOC_PCM179X=y
CONFIG_SND_SOC_PCM179X_I2C=y
CONFIG_SND_SOC_PCM179X_SPI=y
CONFIG_SND_SOC_PCM186X=y
CONFIG_SND_SOC_PCM186X_I2C=y
CONFIG_SND_SOC_PCM186X_SPI=y
CONFIG_SND_SOC_PCM3060=y
CONFIG_SND_SOC_PCM3060_I2C=y
CONFIG_SND_SOC_PCM3060_SPI=y
CONFIG_SND_SOC_PCM3168A=y
CONFIG_SND_SOC_PCM3168A_I2C=y
CONFIG_SND_SOC_PCM3168A_SPI=y
CONFIG_SND_SOC_PCM5102A=y
CONFIG_SND_SOC_PCM512x=y
CONFIG_SND_SOC_PCM512x_I2C=y
CONFIG_SND_SOC_PCM512x_SPI=y
CONFIG_SND_SOC_PEB2466=m
CONFIG_SND_SOC_RK3328=y
CONFIG_SND_SOC_RK817=y
CONFIG_SND_SOC_RL6231=y
CONFIG_SND_SOC_RT5514=m
CONFIG_SND_SOC_RT5514_SPI=m
CONFIG_SND_SOC_RT5616=y
CONFIG_SND_SOC_RT5631=y
CONFIG_SND_SOC_RT5640=y
CONFIG_SND_SOC_RT5645=m
CONFIG_SND_SOC_RT5659=y
CONFIG_SND_SOC_RT9120=y
CONFIG_SND_SOC_SGTL5000=m
CONFIG_SND_SOC_SIGMADSP=m
CONFIG_SND_SOC_SIGMADSP_I2C=m
CONFIG_SND_SOC_SIGMADSP_REGMAP=m
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
CONFIG_SND_SOC_SIMPLE_MUX=y
CONFIG_SND_SOC_SMA1303=m
CONFIG_SND_SOC_SPDIF=y
CONFIG_SND_SOC_SRC4XXX_I2C=m
CONFIG_SND_SOC_SRC4XXX=m
CONFIG_SND_SOC_SSM2305=y
CONFIG_SND_SOC_SSM2518=y
CONFIG_SND_SOC_SSM2602=y
CONFIG_SND_SOC_SSM2602_SPI=y
CONFIG_SND_SOC_SSM2602_I2C=y
CONFIG_SND_SOC_SSM3515=y
CONFIG_SND_SOC_SSM4567=y
CONFIG_SND_SOC_STA32X=m
CONFIG_SND_SOC_STA350=m
CONFIG_SND_SOC_STI_SAS=m
CONFIG_SND_SOC_TAS2552=y
CONFIG_SND_SOC_TAS2562=y
CONFIG_SND_SOC_TAS2764=y
CONFIG_SND_SOC_TAS2770=y
CONFIG_SND_SOC_TAS2780=y
CONFIG_SND_SOC_TAS2781_COMLIB=y
CONFIG_SND_SOC_TAS2781_FMWLIB=y
CONFIG_SND_SOC_TAS2781_I2C=y
CONFIG_SND_SOC_TAS5086=y
CONFIG_SND_SOC_TAS571X=y
CONFIG_SND_SOC_TAS5720=y
CONFIG_SND_SOC_TAS5805M=y
CONFIG_SND_SOC_TAS6424=y
CONFIG_SND_SOC_TDA7419=m
CONFIG_SND_SOC_TFA9879=m
CONFIG_SND_SOC_TFA989X=m
CONFIG_SND_SOC_TLV320ADC3XXX=y
CONFIG_SND_SOC_TLV320AIC23=y
CONFIG_SND_SOC_TLV320AIC23_I2C=y
CONFIG_SND_SOC_TLV320AIC23_SPI=y
CONFIG_SND_SOC_TLV320AIC31XX=y
CONFIG_SND_SOC_TLV320AIC32X4=y
CONFIG_SND_SOC_TLV320AIC32X4_I2C=y
CONFIG_SND_SOC_TLV320AIC32X4_SPI=y
CONFIG_SND_SOC_TLV320AIC3X=y
CONFIG_SND_SOC_TLV320AIC3X_I2C=y
CONFIG_SND_SOC_TLV320AIC3X_SPI=y
CONFIG_SND_SOC_TLV320ADCX140=y
CONFIG_SND_SOC_TS3A227E=m
CONFIG_SND_SOC_TSCS42XX=m
CONFIG_SND_SOC_TSCS454=m
CONFIG_SND_SOC_UDA1334=m
CONFIG_SND_SOC_WM8510=m
CONFIG_SND_SOC_WM8523=m
CONFIG_SND_SOC_WM8524=m
CONFIG_SND_SOC_WM8580=m
CONFIG_SND_SOC_WM8711=m
CONFIG_SND_SOC_WM8728=m
CONFIG_SND_SOC_WM8731=m
CONFIG_SND_SOC_WM8731_I2C=m
CONFIG_SND_SOC_WM8731_SPI=m
CONFIG_SND_SOC_WM8737=m
CONFIG_SND_SOC_WM8741=m
CONFIG_SND_SOC_WM8750=m
CONFIG_SND_SOC_WM8753=m
CONFIG_SND_SOC_WM8770=m
CONFIG_SND_SOC_WM8776=m
CONFIG_SND_SOC_WM8782=m
CONFIG_SND_SOC_WM8804=m
CONFIG_SND_SOC_WM8804_I2C=m
CONFIG_SND_SOC_WM8804_SPI=m
CONFIG_SND_SOC_WM8903=m
CONFIG_SND_SOC_WM8904=m
CONFIG_SND_SOC_WM8940=m
CONFIG_SND_SOC_WM8960=m
CONFIG_SND_SOC_WM8961=m
CONFIG_SND_SOC_WM8962=m
CONFIG_SND_SOC_WM8974=m
CONFIG_SND_SOC_WM8978=m
CONFIG_SND_SOC_WM8985=m
CONFIG_SND_SOC_ZL38060=m
CONFIG_SND_SOC_MAX9759=y
CONFIG_SND_SOC_MT6351=y
CONFIG_SND_SOC_MT6358=y
CONFIG_SND_SOC_MT6660=y
CONFIG_SND_SOC_NAU8315=m
CONFIG_SND_SOC_NAU8540=m
CONFIG_SND_SOC_NAU8810=m
CONFIG_SND_SOC_NAU8821=m
CONFIG_SND_SOC_NAU8822=m
CONFIG_SND_SOC_NAU8824=m
CONFIG_SND_SOC_TPA6130A2=y
CONFIG_SND_SOC_LPASS_MACRO_COMMON=m
CONFIG_SND_SOC_LPASS_WSA_MACRO=m
CONFIG_SND_SOC_LPASS_VA_MACRO=m
CONFIG_SND_SOC_LPASS_RX_MACRO=m
CONFIG_SND_SOC_LPASS_TX_MACRO=m
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD2=m
CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
# CONFIG_SND_TEST_COMPONENT is not set
CONFIG_SND_VIRTIO=m
CONFIG_AC97_BUS=y
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=m
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
CONFIG_HID_A4TECH=m
CONFIG_HID_ACCUTOUCH=m
CONFIG_HID_ACRUX=m
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=m
CONFIG_HID_APPLEIR=m
CONFIG_HID_ASUS=m
CONFIG_HID_AUREAL=m
CONFIG_HID_BELKIN=m
CONFIG_HID_BETOP_FF=m
CONFIG_HID_BIGBEN_FF=m
CONFIG_HID_CHERRY=m
CONFIG_HID_CHICONY=m
CONFIG_HID_CORSAIR=m
CONFIG_HID_COUGAR=m
CONFIG_HID_MACALLY=m
CONFIG_HID_PRODIKEYS=m
CONFIG_HID_CMEDIA=m
CONFIG_HID_CP2112=m
CONFIG_HID_CREATIVE_SB0540=m
CONFIG_HID_CYPRESS=m
CONFIG_HID_DRAGONRISE=m
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=m
CONFIG_HID_ELAN=m
CONFIG_HID_ELECOM=m
CONFIG_HID_ELO=m
CONFIG_HID_EVISION=m
CONFIG_HID_EZKEY=m
CONFIG_HID_FT260=m
CONFIG_HID_GEMBIRD=m
CONFIG_HID_GFRM=m
CONFIG_HID_GLORIOUS=m
CONFIG_HID_HOLTEK=m
CONFIG_HOLTEK_FF=y
CONFIG_HID_VIVALDI_COMMON=m
CONFIG_HID_GOOGLE_STADIA_FF=m
CONFIG_HID_VIVALDI=m
CONFIG_HID_GT683R=m
CONFIG_HID_KEYTOUCH=m
CONFIG_HID_KYE=m
CONFIG_HID_UCLOGIC=m
CONFIG_HID_WALTOP=m
CONFIG_HID_VIEWSONIC=m
CONFIG_HID_VRC2=m
CONFIG_HID_XIAOMI=m
CONFIG_HID_GYRATION=m
CONFIG_HID_ICADE=m
CONFIG_HID_ITE=m
CONFIG_HID_JABRA=m
CONFIG_HID_TWINHAN=m
CONFIG_HID_KENSINGTON=m
CONFIG_HID_LCPOWER=m
CONFIG_HID_LED=m
CONFIG_HID_LENOVO=m
CONFIG_HID_LETSKETCH=m
CONFIG_HID_LOGITECH=m
CONFIG_HID_LOGITECH_DJ=m
CONFIG_HID_LOGITECH_HIDPP=m
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
CONFIG_HID_MAGICMOUSE=m
CONFIG_HID_MALTRON=m
CONFIG_HID_MAYFLASH=m
CONFIG_HID_MEGAWORLD_FF=m
CONFIG_HID_REDRAGON=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
CONFIG_HID_MULTITOUCH=m
CONFIG_HID_NINTENDO=m
CONFIG_NINTENDO_FF=y
CONFIG_HID_NTI=m
CONFIG_HID_NTRIG=m
CONFIG_HID_NVIDIA_SHIELD=m
# CONFIG_NVIDIA_SHIELD_FF is not set
CONFIG_HID_ORTEK=m
CONFIG_HID_PANTHERLORD=m
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PENMOUNT=m
CONFIG_HID_PETALYNX=m
CONFIG_HID_PICOLCD=m
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
CONFIG_HID_PICOLCD_LCD=y
CONFIG_HID_PICOLCD_LEDS=y
CONFIG_HID_PICOLCD_CIR=y
CONFIG_HID_PLANTRONICS=m
CONFIG_HID_PLAYSTATION=m
CONFIG_PLAYSTATION_FF=y
CONFIG_HID_PXRC=m
CONFIG_HID_RAZER=m
CONFIG_HID_PRIMAX=m
CONFIG_HID_RETRODE=m
CONFIG_HID_ROCCAT=m
CONFIG_HID_SAITEK=m
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SEMITEK=m
CONFIG_HID_SIGMAMICRO=m
CONFIG_HID_SONY=m
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=m
CONFIG_HID_STEAM=m
# CONFIG_STEAM_FF is not set
CONFIG_HID_STEELSERIES=m
CONFIG_HID_SUNPLUS=m
CONFIG_HID_RMI=m
CONFIG_HID_GREENASIA=m
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=m
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TIVO=m
CONFIG_HID_TOPSEED=m
CONFIG_HID_TOPRE=m
CONFIG_HID_THINGM=m
CONFIG_HID_THRUSTMASTER=m
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_UDRAW_PS3=m
CONFIG_HID_U2FZERO=m
CONFIG_HID_UNIVERSAL_PIDFF=m
CONFIG_HID_WACOM=m
CONFIG_HID_WIIMOTE=m
CONFIG_HID_XINMO=m
CONFIG_HID_ZEROPLUS=m
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=m
CONFIG_HID_SENSOR_HUB=m
CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
CONFIG_HID_ALPS=m
CONFIG_HID_MCP2200=m
CONFIG_HID_MCP2221=m
# end of Special HID drivers

#
# HID-BPF support
#
# end of HID-BPF support

#
# USB HID support
#
CONFIG_USB_HID=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
# end of USB HID support

CONFIG_I2C_HID=y
CONFIG_I2C_HID_ACPI=m
CONFIG_I2C_HID_OF=m
CONFIG_I2C_HID_OF_ELAN=m
CONFIG_I2C_HID_OF_GOODIX=m
CONFIG_I2C_HID_CORE=m
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_LED_TRIG=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_CONN_GPIO=m
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
CONFIG_USB_OTG_FSM=m
CONFIG_USB_LEDS_TRIGGER_USBPORT=m
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=y

#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=m
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_PCI=m
CONFIG_USB_XHCI_PCI_RENESAS=m
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_XHCI_SUNXI=m
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_EHCI_FSL=m
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OXU210HP_HCD=m
CONFIG_USB_ISP116X_HCD=m
CONFIG_USB_MAX3421_HCD=m
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_OHCI_HCD_PCI=m
CONFIG_USB_OHCI_HCD_PLATFORM=m
CONFIG_USB_UHCI_HCD=m
CONFIG_USB_SL811_HCD=m
CONFIG_USB_SL811_HCD_ISO=y
CONFIG_USB_R8A66597_HCD=m
CONFIG_USB_HCD_BCMA=m
# CONFIG_USB_HCD_TEST_MODE is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=y
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
CONFIG_USB_STORAGE_REALTEK=m
CONFIG_REALTEK_AUTOPM=y
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_FREECOM=m
CONFIG_USB_STORAGE_ISD200=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_STORAGE_ALAUDA=m
CONFIG_USB_STORAGE_ONETOUCH=m
CONFIG_USB_STORAGE_KARMA=m
CONFIG_USB_STORAGE_CYPRESS_ATACB=m
CONFIG_USB_STORAGE_ENE_UB6250=m
CONFIG_USB_UAS=y

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
CONFIG_USB_MICROTEK=m
CONFIG_USBIP_CORE=m
CONFIG_USBIP_VHCI_HCD=m
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=m
CONFIG_USBIP_VUDC=m
# CONFIG_USBIP_DEBUG is not set

#
# USB dual-mode controller drivers
#
# CONFIG_USB_CDNS_SUPPORT is not set
CONFIG_USB_MUSB_HDRC=y
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
CONFIG_USB_MUSB_DUAL_ROLE=y

#
# Platform Glue Layer
#
CONFIG_USB_MUSB_SUNXI=m

#
# MUSB DMA mode
#
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_ULPI=y
# CONFIG_USB_DWC3_HOST is not set
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_DUAL_ROLE=y

#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_PCI=y
# CONFIG_USB_DWC3_HAPS is not set
CONFIG_USB_DWC3_MESON_G12A=y
CONFIG_USB_DWC3_OF_SIMPLE=m
CONFIG_USB_DWC2=y
# CONFIG_USB_DWC2_HOST is not set

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
CONFIG_USB_DWC2_DUAL_ROLE=y
# CONFIG_USB_DWC2_PCI is not set
# CONFIG_USB_DWC2_DEBUG is not set
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
CONFIG_USB_CHIPIDEA=m
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_USB_CHIPIDEA_PCI=m
CONFIG_USB_CHIPIDEA_MSM=m
CONFIG_USB_CHIPIDEA_IMX=m
CONFIG_USB_CHIPIDEA_GENERIC=m
CONFIG_USB_CHIPIDEA_TEGRA=m
CONFIG_USB_ISP1760=m
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_ISP1761_UDC=y
# CONFIG_USB_ISP1760_HOST_ROLE is not set
# CONFIG_USB_ISP1760_GADGET_ROLE is not set
CONFIG_USB_ISP1760_DUAL_ROLE=y

#
# USB port drivers
#
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=m
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=y
CONFIG_USB_SERIAL_CH348=y
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=y
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=y
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=m
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_F81232=m
CONFIG_USB_SERIAL_F8153X=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=m
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_METRO=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MXUPORT=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=y
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=m
CONFIG_USB_SERIAL_QUALCOMM=m
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
# CONFIG_USB_SERIAL_SAFE_PADDED is not set
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
CONFIG_USB_SERIAL_SYMBOL=m
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_WWAN=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=m
CONFIG_USB_SERIAL_XSENS_MT=m
CONFIG_USB_SERIAL_WISHBONE=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_SERIAL_QT2=m
CONFIG_USB_SERIAL_UPD78F0730=m
CONFIG_USB_SERIAL_XR=m
CONFIG_USB_SERIAL_DEBUG=m

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
CONFIG_USB_CYPRESS_CY7C63=m
CONFIG_USB_CYTHERM=m
CONFIG_USB_IDMOUSE=m
CONFIG_USB_APPLEDISPLAY=m
CONFIG_APPLE_MFI_FASTCHARGE=m
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
CONFIG_USB_TEST=m
CONFIG_USB_EHSET_TEST_FIXTURE=m
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=m
CONFIG_USB_HUB_USB251XB=m
CONFIG_USB_HSIC_USB3503=m
CONFIG_USB_HSIC_USB4604=m
CONFIG_USB_LINK_LAYER_TEST=m
CONFIG_USB_CHAOSKEY=m
CONFIG_USB_ONBOARD_HUB=y

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_NOP_USB_XCEIV=m
CONFIG_USB_GPIO_VBUS=m
CONFIG_USB_ISP1301=m
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set

#
# USB Peripheral Controller
#
CONFIG_USB_GR_UDC=m
CONFIG_USB_R8A66597=m
CONFIG_USB_PXA27X=m
CONFIG_USB_MV_UDC=m
CONFIG_USB_MV_U3D=m
CONFIG_USB_SNP_CORE=m
CONFIG_USB_SNP_UDC_PLAT=m
CONFIG_USB_M66592=m
CONFIG_USB_BDC_UDC=m
CONFIG_USB_AMD5536UDC=m
CONFIG_USB_NET2272=m
CONFIG_USB_NET2272_DMA=y
CONFIG_USB_NET2280=m
CONFIG_USB_GOKU=m
CONFIG_USB_EG20T=m
CONFIG_USB_GADGET_XILINX=m
CONFIG_USB_MAX3420_UDC=m
# CONFIG_USB_CDNS2_UDC is not set
CONFIG_USB_DUMMY_HCD=m
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=m
CONFIG_USB_F_ACM=m
CONFIG_USB_F_SS_LB=m
CONFIG_USB_U_SERIAL=m
CONFIG_USB_U_ETHER=m
CONFIG_USB_U_AUDIO=m
CONFIG_USB_F_SERIAL=m
CONFIG_USB_F_OBEX=m
CONFIG_USB_F_NCM=m
CONFIG_USB_F_ECM=m
CONFIG_USB_F_EEM=m
CONFIG_USB_F_SUBSET=m
CONFIG_USB_F_RNDIS=m
CONFIG_USB_F_MASS_STORAGE=m
CONFIG_USB_F_FS=m
CONFIG_USB_F_UAC1=m
CONFIG_USB_F_UAC1_LEGACY=m
CONFIG_USB_F_UAC2=m
CONFIG_USB_F_UVC=m
CONFIG_USB_F_MIDI=m
CONFIG_USB_F_MIDI2=m
CONFIG_USB_F_HID=m
CONFIG_USB_F_PRINTER=m
CONFIG_USB_F_TCM=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_LB_SS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_MIDI2=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y
CONFIG_USB_CONFIGFS_F_TCM=y

#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=m
CONFIG_USB_ZERO_HNPTEST=y
CONFIG_USB_AUDIO=m
CONFIG_GADGET_UAC1=y
CONFIG_GADGET_UAC1_LEGACY=y
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
CONFIG_USB_FUNCTIONFS_ETH=y
CONFIG_USB_FUNCTIONFS_RNDIS=y
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_GADGET_TARGET=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_G_HID=m
CONFIG_USB_G_DBGP=m
# CONFIG_USB_G_DBGP_PRINTK is not set
CONFIG_USB_G_DBGP_SERIAL=y
CONFIG_USB_G_WEBCAM=m
CONFIG_USB_RAW_GADGET=m
# end of USB Gadget precomposed configurations

CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
CONFIG_TYPEC_HUSB311=y
CONFIG_TYPEC_RT1711H=y
CONFIG_TYPEC_TCPCI_MAXIM=y
CONFIG_TYPEC_FUSB302=y
CONFIG_TYPEC_UCSI=y
CONFIG_UCSI_CCG=y
CONFIG_UCSI_ACPI=y
CONFIG_UCSI_STM32G0=y
CONFIG_TYPEC_TPS6598X=y
CONFIG_TYPEC_ANX7411=y
CONFIG_TYPEC_RT1719=y
CONFIG_TYPEC_HD3SS3220=y
CONFIG_TYPEC_STUSB160X=y
CONFIG_TYPEC_WUSB3801=y

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
CONFIG_TYPEC_MUX_FSA4480=m
CONFIG_TYPEC_MUX_GPIO_SBU=m
CONFIG_TYPEC_MUX_PI3USB30532=m
CONFIG_TYPEC_MUX_NB7VPQ904M=m
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
CONFIG_TYPEC_DP_ALTMODE=m
CONFIG_TYPEC_NVIDIA_ALTMODE=m
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=y
# CONFIG_PWRSEQ_SD8787 is not set
CONFIG_PWRSEQ_SIMPLE=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set
# CONFIG_MMC_CRYPTO is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_ARMMMCI=m
CONFIG_MMC_STM32_SDMMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_PCI=m
CONFIG_MMC_RICOH_MMC=y
CONFIG_MMC_SDHCI_ACPI=m
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ARASAN=m
CONFIG_MMC_SDHCI_OF_AT91=m
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
CONFIG_MMC_SDHCI_CADENCE=m
CONFIG_MMC_SDHCI_F_SDH30=m
CONFIG_MMC_SDHCI_MILBEAUT=m
CONFIG_MMC_MESON_GX=y
CONFIG_MMC_MESON_MX_SDIO=y
CONFIG_MMC_TIFM_SD=m
CONFIG_MMC_SPI=m
CONFIG_MMC_CB710=m
CONFIG_MMC_VIA_SDMMC=m
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
CONFIG_MMC_DW_BLUEFIELD=m
CONFIG_MMC_DW_EXYNOS=m
CONFIG_MMC_DW_HI3798CV200=m
CONFIG_MMC_DW_K3=m
CONFIG_MMC_DW_PCI=m
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_VUB300=m
CONFIG_MMC_USHC=m
CONFIG_MMC_USDHI6ROL0=m
CONFIG_MMC_REALTEK_USB=m
CONFIG_MMC_SUNXI=y
CONFIG_MMC_CQHCI=m
CONFIG_MMC_HSQ=y
CONFIG_MMC_TOSHIBA_PCI=m
CONFIG_MMC_MTK=m
CONFIG_MMC_SDHCI_XENON=m
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
CONFIG_LEDS_CLASS_MULTICOLOR=y
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y

#
# LED drivers
#
CONFIG_LEDS_AN30259A=m
CONFIG_LEDS_AW200XX=m
CONFIG_LEDS_AW2013=m
CONFIG_LEDS_BCM6328=m
CONFIG_LEDS_BCM6358=m
CONFIG_LEDS_CR0014114=m
CONFIG_LEDS_EL15203000=m
CONFIG_LEDS_LM3530=m
CONFIG_LEDS_LM3532=m
CONFIG_LEDS_LM3642=m
CONFIG_LEDS_LM3692X=m
CONFIG_LEDS_PCA9532=m
CONFIG_LEDS_PCA9532_GPIO=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=m
CONFIG_LEDS_LP3952=m
CONFIG_LEDS_LP50XX=m
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LEDS_LP5521=m
CONFIG_LEDS_LP5523=m
CONFIG_LEDS_LP5562=m
CONFIG_LEDS_LP8501=m
CONFIG_LEDS_LP8860=m
CONFIG_LEDS_PCA955X=m
CONFIG_LEDS_PCA955X_GPIO=y
CONFIG_LEDS_PCA963X=m
CONFIG_LEDS_PCA995X=m
CONFIG_LEDS_DAC124S085=m
CONFIG_LEDS_PWM=y
CONFIG_LEDS_REGULATOR=y
CONFIG_LEDS_BD2606MVV=m
CONFIG_LEDS_BD2802=m
CONFIG_LEDS_LT3593=m
CONFIG_LEDS_TCA6507=y
CONFIG_LEDS_TLC591XX=m
CONFIG_LEDS_LM355x=m
CONFIG_LEDS_IS31FL319X=m
CONFIG_LEDS_IS31FL32XX=m

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=m
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_MLXREG=m
CONFIG_LEDS_USER=y
CONFIG_LEDS_SPI_BYTE=m
CONFIG_LEDS_TI_LMU_COMMON=m
CONFIG_LEDS_LM3697=m

#
# Flash and Torch LED drivers
#
CONFIG_LEDS_AAT1290=m
CONFIG_LEDS_AS3645A=m
CONFIG_LEDS_KTD2692=m
CONFIG_LEDS_LM3601X=m
CONFIG_LEDS_RT4505=m
CONFIG_LEDS_RT8515=m
CONFIG_LEDS_SGM3140=m

#
# RGB LED drivers
#
CONFIG_LEDS_GROUP_MULTICOLOR=m
CONFIG_LEDS_PWM_MULTICOLOR=y
CONFIG_LEDS_QCOM_LPG=m

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_ACTIVITY=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=y
CONFIG_LEDS_TRIGGER_PATTERN=y
CONFIG_LEDS_TRIGGER_AUDIO=y
CONFIG_LEDS_TRIGGER_TTY=y

#
# Simple LED drivers
#
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
# CONFIG_EDAC_DEBUG is not set
# CONFIG_EDAC_GHES is not set
# CONFIG_EDAC_THUNDERX is not set
# CONFIG_EDAC_XGENE is not set
CONFIG_EDAC_DMC520=m
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_ABB5ZES3 is not set
# CONFIG_RTC_DRV_ABEOZ9 is not set
# CONFIG_RTC_DRV_ABX80X is not set
CONFIG_RTC_DRV_AC100=m
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
CONFIG_RTC_DRV_HYM8563=m
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_NCT3018Y is not set
CONFIG_RTC_DRV_RK808=m
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_ISL12026 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8523 is not set
# CONFIG_RTC_DRV_PCF85063 is not set
# CONFIG_RTC_DRV_PCF85363 is not set
CONFIG_RTC_DRV_PCF8563=m
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8010 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV3028 is not set
# CONFIG_RTC_DRV_RV3032 is not set
# CONFIG_RTC_DRV_RV8803 is not set
# CONFIG_RTC_DRV_SD3078 is not set

#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_MCP795 is not set
CONFIG_RTC_I2C_AND_SPI=y

#
# SPI and I2C RTC drivers
#
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_PCF2127 is not set
# CONFIG_RTC_DRV_RV3029C2 is not set
# CONFIG_RTC_DRV_RX6110 is not set

#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1685_FAMILY is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_DS2404 is not set
CONFIG_RTC_DRV_EFI=m
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_OPTEE is not set
# CONFIG_RTC_DRV_ZYNQMP is not set

#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_MESON_VRTC=m
CONFIG_RTC_DRV_PL030=m
CONFIG_RTC_DRV_PL031=m
CONFIG_RTC_DRV_SUN6I=y
# CONFIG_RTC_DRV_CADENCE is not set
# CONFIG_RTC_DRV_FTRTC010 is not set
# CONFIG_RTC_DRV_R7301 is not set

#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
# CONFIG_RTC_DRV_GOLDFISH is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
CONFIG_DMA_OF=y
# CONFIG_ALTERA_MSGDMA is not set
CONFIG_AMBA_PL08X=y
# CONFIG_BCM_SBA_RAID is not set
CONFIG_DMA_SUN6I=y
CONFIG_DW_AXI_DMAC=y
# CONFIG_FSL_EDMA is not set
# CONFIG_FSL_QDMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_MV_XOR_V2 is not set
CONFIG_PL330_DMA=y
# CONFIG_PLX_DMA is not set
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_XDMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
# CONFIG_XILINX_ZYNQMP_DPDMA is not set
# CONFIG_QCOM_HIDMA_MGMT is not set
# CONFIG_QCOM_HIDMA is not set
CONFIG_DW_DMAC_CORE=y
CONFIG_DW_DMAC=y
# CONFIG_DW_DMAC_PCI is not set
CONFIG_DW_EDMA=y
# CONFIG_DW_EDMA_PCIE is not set
# CONFIG_SF_PDMA is not set

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_DEBUG is not set
# CONFIG_DMABUF_SELFTESTS is not set
CONFIG_DMABUF_HEAPS=y
# CONFIG_DMABUF_SYSFS_STATS is not set
CONFIG_DMABUF_HEAPS_SYSTEM=y
CONFIG_DMABUF_HEAPS_CMA=y
# end of DMABUF options

# CONFIG_UIO is not set
# CONFIG_VFIO is not set
CONFIG_VIRT_DRIVERS=y
CONFIG_VMGENID=y
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_PCI_LIB=m
CONFIG_VIRTIO_PCI_LIB_LEGACY=m
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_PCI=m
CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
# CONFIG_VDPA is not set
CONFIG_VHOST_IOTLB=m
CONFIG_VHOST_TASK=y
CONFIG_VHOST=m
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_SCSI=m
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set

#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# end of Microsoft Hyper-V guest support

# CONFIG_GREYBUS is not set
# CONFIG_COMEDI is not set
CONFIG_STAGING=y
CONFIG_PRISM2_USB=m
CONFIG_RTL8192U=m
CONFIG_RTLLIB=m
CONFIG_RTLLIB_CRYPTO_CCMP=m
CONFIG_RTLLIB_CRYPTO_TKIP=m
CONFIG_RTLLIB_CRYPTO_WEP=m
CONFIG_RTL8192E=m
CONFIG_RTL8723BS=m
CONFIG_RTS5208=m
CONFIG_VT6655=m
CONFIG_VT6656=m

#
# IIO staging drivers
#

#
# Accelerometers
#
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16240 is not set
# end of Accelerometers

#
# Analog to digital converters
#
# CONFIG_AD7816 is not set
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
# CONFIG_ADT7316 is not set
# end of Analog digital bi-direction converters

#
# Direct Digital Synthesis
#
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
# CONFIG_AD5933 is not set
# end of Network Analyzer, Impedance Converters

#
# Resolver to digital converters
#
# CONFIG_AD2S1210 is not set
# end of Resolver to digital converters
# end of IIO staging drivers

# CONFIG_FB_SM750 is not set
CONFIG_STAGING_MEDIA=y
# CONFIG_VIDEO_MAX96712 is not set
CONFIG_VIDEO_MESON_VDEC=m
CONFIG_VIDEO_ROCKCHIP_VDEC=m
CONFIG_VIDEO_SUNXI=y
CONFIG_VIDEO_SUNXI_CEDRUS=m
CONFIG_VIDEO_SUN6I_ISP=m
# CONFIG_STAGING_MEDIA_DEPRECATED is not set
# CONFIG_STAGING_BOARD is not set
# CONFIG_LTE_GDM724X is not set
CONFIG_FB_TFT=m
# CONFIG_FB_TFT_AGM1264K_FL is not set
# CONFIG_FB_TFT_BD663474 is not set
# CONFIG_FB_TFT_HX8340BN is not set
# CONFIG_FB_TFT_HX8347D is not set
# CONFIG_FB_TFT_HX8353D is not set
# CONFIG_FB_TFT_HX8357D is not set
# CONFIG_FB_TFT_ILI9163 is not set
# CONFIG_FB_TFT_ILI9320 is not set
# CONFIG_FB_TFT_ILI9325 is not set
# CONFIG_FB_TFT_ILI9340 is not set
# CONFIG_FB_TFT_ILI9341 is not set
# CONFIG_FB_TFT_ILI9481 is not set
# CONFIG_FB_TFT_ILI9486 is not set
# CONFIG_FB_TFT_PCD8544 is not set
# CONFIG_FB_TFT_RA8875 is not set
# CONFIG_FB_TFT_S6D02A1 is not set
# CONFIG_FB_TFT_S6D1121 is not set
# CONFIG_FB_TFT_SEPS525 is not set
# CONFIG_FB_TFT_SH1106 is not set
# CONFIG_FB_TFT_SSD1289 is not set
# CONFIG_FB_TFT_SSD1305 is not set
# CONFIG_FB_TFT_SSD1306 is not set
# CONFIG_FB_TFT_SSD1331 is not set
# CONFIG_FB_TFT_SSD1351 is not set
CONFIG_FB_TFT_ST7735R=m
# CONFIG_FB_TFT_ST7789V is not set
# CONFIG_FB_TFT_TINYLCD is not set
# CONFIG_FB_TFT_TLS8204 is not set
# CONFIG_FB_TFT_UC1611 is not set
# CONFIG_FB_TFT_UC1701 is not set
# CONFIG_FB_TFT_UPD161704 is not set
# CONFIG_KS7010 is not set
CONFIG_PI433=m
# CONFIG_XIL_AXIS_FIFO is not set
# CONFIG_FIELDBUS_DEV is not set
# CONFIG_QLGE is not set
# CONFIG_VME_BUS is not set
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
CONFIG_SURFACE_PLATFORMS=y
# CONFIG_SURFACE_3_POWER_OPREGION is not set
# CONFIG_SURFACE_GPE is not set
# CONFIG_SURFACE_HOTPLUG is not set
# CONFIG_SURFACE_PRO3_BUTTON is not set
# CONFIG_SURFACE_AGGREGATOR is not set
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Clock driver for ARM Reference designs
#
# CONFIG_CLK_ICST is not set
# CONFIG_CLK_SP810 is not set
# CONFIG_CLK_VEXPRESS_OSC is not set
# end of Clock driver for ARM Reference designs

# CONFIG_LMK04832 is not set
# CONFIG_COMMON_CLK_MAX9485 is not set
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI544 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
CONFIG_COMMON_CLK_CS2000_CP=y
# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
# CONFIG_COMMON_CLK_XGENE is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_RS9_PCIE is not set
# CONFIG_COMMON_CLK_SI521XX is not set
# CONFIG_COMMON_CLK_VC3 is not set
# CONFIG_COMMON_CLK_VC5 is not set
# CONFIG_COMMON_CLK_VC7 is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set

#
# Clock support for Amlogic platforms
#
CONFIG_COMMON_CLK_MESON_REGMAP=y
CONFIG_COMMON_CLK_MESON_DUALDIV=y
CONFIG_COMMON_CLK_MESON_MPLL=y
CONFIG_COMMON_CLK_MESON_PHASE=y
CONFIG_COMMON_CLK_MESON_PLL=y
CONFIG_COMMON_CLK_MESON_SCLK_DIV=y
CONFIG_COMMON_CLK_MESON_VID_PLL_DIV=y
CONFIG_COMMON_CLK_MESON_CLKC_UTILS=y
CONFIG_COMMON_CLK_MESON_AO_CLKC=y
CONFIG_COMMON_CLK_MESON_EE_CLKC=y
CONFIG_COMMON_CLK_MESON_CPU_DYNDIV=y
CONFIG_COMMON_CLK_GXBB=y
CONFIG_COMMON_CLK_AXG=y
CONFIG_COMMON_CLK_AXG_AUDIO=y
CONFIG_COMMON_CLK_A1_PLL=y
CONFIG_COMMON_CLK_A1_PERIPHERALS=y
CONFIG_COMMON_CLK_G12A=y
# end of Clock support for Amlogic platforms

CONFIG_COMMON_CLK_ROCKCHIP=y
CONFIG_CLK_PX30=y
CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
CONFIG_CLK_RK3399=y
CONFIG_CLK_RK3568=y
CONFIG_CLK_RK3588=y
CONFIG_SUNXI_CCU=y
CONFIG_SUN50I_A64_CCU=y
CONFIG_SUN50I_A100_CCU=y
CONFIG_SUN50I_A100_R_CCU=y
CONFIG_SUN50I_H6_CCU=y
CONFIG_SUN50I_H616_CCU=y
CONFIG_SUN50I_H6_R_CCU=y
CONFIG_SUN6I_RTC_CCU=y
CONFIG_SUN8I_H3_CCU=y
CONFIG_SUN8I_DE2_CCU=y
CONFIG_SUN8I_R_CCU=y
# CONFIG_XILINX_VCU is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_SUN6I=y

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_ACPI=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_SUN4I_TIMER=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
CONFIG_ARM_TIMER_SP804=y
# end of Clock Source drivers

CONFIG_MAILBOX=y
CONFIG_ARM_MHU=y
CONFIG_ARM_MHU_V2=m
CONFIG_PLATFORM_MHU=y
CONFIG_PL320_MBOX=y
CONFIG_ROCKCHIP_MBOX=y
# CONFIG_PCC is not set
CONFIG_ALTERA_MBOX=m
# CONFIG_MAILBOX_TEST is not set
CONFIG_SUN6I_MSGBOX=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_DART is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
CONFIG_IOMMU_SVA=y
# CONFIG_IOMMUFD is not set
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_SUN50I_IOMMU=y
CONFIG_ARM_SMMU=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
CONFIG_ARM_SMMU_V3=y
CONFIG_ARM_SMMU_V3_SVA=y
CONFIG_VIRTIO_IOMMU=m

#
# Remoteproc drivers
#
CONFIG_REMOTEPROC=y
CONFIG_REMOTEPROC_CDEV=y
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=m
CONFIG_RPMSG_CHAR=m
# CONFIG_RPMSG_CTRL is not set
CONFIG_RPMSG_NS=m
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
CONFIG_RPMSG_VIRTIO=m
# end of Rpmsg drivers

# CONFIG_SOUNDWIRE is not set

#
# SOC (System On Chip) specific Drivers
#

#
# Amlogic SoC drivers
#
CONFIG_MESON_CANVAS=y
CONFIG_MESON_CLK_MEASURE=y
CONFIG_MESON_GX_SOCINFO=y
CONFIG_MESON_GX_PM_DOMAINS=y
CONFIG_MESON_EE_PM_DOMAINS=y
CONFIG_MESON_SECURE_PM_DOMAINS=y
# end of Amlogic SoC drivers

#
# Broadcom SoC drivers
#
# CONFIG_SOC_BRCMSTB is not set
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
CONFIG_QUICC_ENGINE=y
# end of NXP/Freescale QorIQ SoC drivers

#
# fujitsu SoC drivers
#
# CONFIG_A64FX_DIAG is not set
# end of fujitsu SoC drivers

#
# i.MX SoC drivers
#
# end of i.MX SoC drivers

#
# Enable LiteX SoC Builder specific drivers
#
# CONFIG_LITEX_SOC_CONTROLLER is not set
# end of Enable LiteX SoC Builder specific drivers

# CONFIG_WPCM450_SOC is not set

#
# Qualcomm SoC drivers
#
# CONFIG_QCOM_PMIC_GLINK is not set
CONFIG_QCOM_QMI_HELPERS=m
# end of Qualcomm SoC drivers

CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_SUNXI_MBUS=y
CONFIG_SUNXI_SRAM=y
CONFIG_SUN20I_PPU=y
# CONFIG_SOC_TI is not set

#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=m
CONFIG_DEVFREQ_GOV_USERSPACE=m
CONFIG_DEVFREQ_GOV_PASSIVE=m

#
# DEVFREQ Drivers
#
CONFIG_ARM_RK3328_DMC_DEVFREQ=m
CONFIG_ARM_RK3399_DMC_DEVFREQ=y
CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
CONFIG_EXTCON_ADC_JACK=m
CONFIG_EXTCON_FSA9480=m
CONFIG_EXTCON_GPIO=m
CONFIG_EXTCON_MAX3355=m
CONFIG_EXTCON_PTN5150=m
CONFIG_EXTCON_RT8973A=m
CONFIG_EXTCON_SM5502=m
CONFIG_EXTCON_USB_GPIO=m
CONFIG_EXTCON_USBC_TUSB320=m
CONFIG_EXTCON_USBC_VIRTUAL_PD=m
CONFIG_MEMORY=y
CONFIG_ARM_PL172_MPMC=m
# CONFIG_FPGA_DFL_EMIF is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
CONFIG_IIO_BUFFER_DMA=m
CONFIG_IIO_BUFFER_DMAENGINE=m
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
CONFIG_IIO_TRIGGERED_EVENT=m
CONFIG_IIO_BACKEND=m

#
# Accelerometers
#
CONFIG_ADIS16201=m
CONFIG_ADIS16209=m
CONFIG_ADXL313=m
CONFIG_ADXL313_I2C=m
CONFIG_ADXL313_SPI=m
CONFIG_ADXL345=m
CONFIG_ADXL345_I2C=m
CONFIG_ADXL345_SPI=m
CONFIG_ADXL355=m
CONFIG_ADXL355_I2C=m
CONFIG_ADXL355_SPI=m
CONFIG_ADXL367=m
CONFIG_ADXL367_SPI=m
CONFIG_ADXL367_I2C=m
CONFIG_ADXL372=m
CONFIG_ADXL372_SPI=m
CONFIG_ADXL372_I2C=m
CONFIG_BMA180=m
CONFIG_BMA220=m
CONFIG_BMA400=m
CONFIG_BMA400_I2C=m
CONFIG_BMA400_SPI=m
CONFIG_BMC150_ACCEL=m
CONFIG_BMC150_ACCEL_I2C=m
CONFIG_BMC150_ACCEL_SPI=m
CONFIG_BMI088_ACCEL=m
CONFIG_BMI088_ACCEL_SPI=m
CONFIG_DA280=m
CONFIG_DA311=m
CONFIG_DMARD06=m
CONFIG_DMARD09=m
CONFIG_DMARD10=m
CONFIG_FXLS8962AF=m
CONFIG_FXLS8962AF_I2C=m
CONFIG_FXLS8962AF_SPI=m
CONFIG_HID_SENSOR_ACCEL_3D=m
CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
# CONFIG_IIO_KX022A_SPI is not set
# CONFIG_IIO_KX022A_I2C is not set
CONFIG_KXSD9=m
CONFIG_KXSD9_SPI=m
CONFIG_KXSD9_I2C=m
CONFIG_KXCJK1013=m
CONFIG_MC3230=m
CONFIG_MMA7455=m
CONFIG_MMA7455_I2C=m
CONFIG_MMA7455_SPI=m
CONFIG_MMA7660=m
CONFIG_MMA8452=m
CONFIG_MMA9551_CORE=m
CONFIG_MMA9551=m
CONFIG_MMA9553=m
CONFIG_MSA311=m
CONFIG_MXC4005=m
CONFIG_MXC6255=m
CONFIG_SCA3000=m
CONFIG_SCA3300=m
CONFIG_STK8312=m
CONFIG_STK8BA50=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=m
# CONFIG_AD4130 is not set
CONFIG_AD7091R5=m
CONFIG_AD7124=m
CONFIG_AD7192=m
CONFIG_AD7266=m
CONFIG_AD7280=m
CONFIG_AD7291=m
CONFIG_AD7292=m
CONFIG_AD7298=m
CONFIG_AD7476=m
CONFIG_AD7606=m
CONFIG_AD7606_IFACE_PARALLEL=m
CONFIG_AD7606_IFACE_SPI=m
CONFIG_AD7766=m
CONFIG_AD7768_1=m
CONFIG_AD7780=m
CONFIG_AD7791=m
CONFIG_AD7793=m
CONFIG_AD7887=m
CONFIG_AD7923=m
CONFIG_AD7949=m
CONFIG_AD799X=m
CONFIG_AD9467=m
CONFIG_ADI_AXI_ADC=m
CONFIG_AXP20X_ADC=y
CONFIG_AXP288_ADC=y
CONFIG_CC10001_ADC=m
CONFIG_ENVELOPE_DETECTOR=m
CONFIG_HI8435=m
CONFIG_HX711=m
CONFIG_INA2XX_ADC=m
CONFIG_LTC2471=m
CONFIG_LTC2485=m
CONFIG_LTC2496=m
CONFIG_LTC2497=m
CONFIG_MAX1027=m
CONFIG_MAX11100=m
CONFIG_MAX1118=m
CONFIG_MAX11205=m
# CONFIG_MAX11410 is not set
CONFIG_MAX1241=m
CONFIG_MAX1363=m
CONFIG_MAX9611=m
CONFIG_MCP320X=m
CONFIG_MCP3422=m
CONFIG_MCP3911=m
CONFIG_MESON_SARADC=y
CONFIG_NAU7802=m
CONFIG_QCOM_VADC_COMMON=m
CONFIG_QCOM_SPMI_IADC=m
CONFIG_QCOM_SPMI_VADC=m
CONFIG_QCOM_SPMI_ADC5=m
CONFIG_ROCKCHIP_SARADC=y
CONFIG_RICHTEK_RTQ6056=m
CONFIG_SD_ADC_MODULATOR=m
# CONFIG_SUN20I_GPADC is not set
CONFIG_TI_ADC081C=m
CONFIG_TI_ADC0832=m
CONFIG_TI_ADC084S021=m
CONFIG_TI_ADC12138=m
CONFIG_TI_ADC108S102=m
CONFIG_TI_ADC128S052=m
CONFIG_TI_ADC161S626=m
CONFIG_TI_ADS1015=m
# CONFIG_TI_ADS7924 is not set
# CONFIG_TI_ADS1100 is not set
CONFIG_TI_ADS7950=m
CONFIG_TI_ADS8344=m
CONFIG_TI_ADS8688=m
CONFIG_TI_ADS124S08=m
CONFIG_TI_ADS131E08=m
# CONFIG_TI_LMP92064 is not set
CONFIG_TI_TLC4541=m
CONFIG_TI_TSC2046=m
CONFIG_VF610_ADC=m
CONFIG_XILINX_XADC=m
# end of Analog to digital converters

#
# Analog to digital and digital to analog converters
#
# CONFIG_AD74115 is not set
CONFIG_AD74413R=m
# end of Analog to digital and digital to analog converters

#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=m
# end of Analog Front Ends

#
# Amplifiers
#
CONFIG_AD8366=m
CONFIG_ADA4250=m
CONFIG_HMC425=m
# end of Amplifiers

#
# Capacitance to digital converters
#
CONFIG_AD7150=m
CONFIG_AD7746=m
# end of Capacitance to digital converters

#
# Chemical Sensors
#
CONFIG_ATLAS_PH_SENSOR=m
CONFIG_ATLAS_EZO_SENSOR=m
CONFIG_BME680=m
CONFIG_BME680_I2C=m
CONFIG_BME680_SPI=m
CONFIG_CCS811=m
CONFIG_IAQCORE=m
CONFIG_PMS7003=m
CONFIG_SCD30_CORE=m
CONFIG_SCD30_I2C=m
CONFIG_SCD30_SERIAL=m
CONFIG_SCD4X=m
CONFIG_SENSIRION_SGP30=m
CONFIG_SENSIRION_SGP40=m
CONFIG_SPS30=m
CONFIG_SPS30_I2C=m
CONFIG_SPS30_SERIAL=m
CONFIG_SENSEAIR_SUNRISE_CO2=m
CONFIG_VZ89X=m
# end of Chemical Sensors

#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
# end of Hid Sensor IIO Common

CONFIG_IIO_INV_SENSORS_TIMESTAMP=m
CONFIG_IIO_MS_SENSORS_I2C=m

#
# IIO SCMI Sensors
#
CONFIG_IIO_SCMI=m
# end of IIO SCMI Sensors

#
# SSP Sensor Common
#
CONFIG_IIO_SSP_SENSORS_COMMONS=m
CONFIG_IIO_SSP_SENSORHUB=m
# end of SSP Sensor Common

CONFIG_IIO_ST_SENSORS_I2C=m
CONFIG_IIO_ST_SENSORS_SPI=m
CONFIG_IIO_ST_SENSORS_CORE=m

#
# Digital to analog converters
#
CONFIG_AD3552R=m
CONFIG_AD5064=m
CONFIG_AD5360=m
CONFIG_AD5380=m
CONFIG_AD5421=m
CONFIG_AD5446=m
CONFIG_AD5449=m
CONFIG_AD5592R_BASE=m
CONFIG_AD5592R=m
CONFIG_AD5593R=m
CONFIG_AD5504=m
CONFIG_AD5624R_SPI=m
CONFIG_LTC2688=m
CONFIG_AD5686=m
CONFIG_AD5686_SPI=m
CONFIG_AD5696_I2C=m
CONFIG_AD5755=m
CONFIG_AD5758=m
CONFIG_AD5761=m
CONFIG_AD5764=m
CONFIG_AD5766=m
CONFIG_AD5770R=m
CONFIG_AD5791=m
CONFIG_AD7293=m
CONFIG_AD7303=m
CONFIG_AD8801=m
CONFIG_DPOT_DAC=m
CONFIG_DS4424=m
CONFIG_LTC1660=m
CONFIG_LTC2632=m
CONFIG_M62332=m
CONFIG_MAX517=m
# CONFIG_MAX5522 is not set
CONFIG_MAX5821=m
CONFIG_MCP4725=m
# CONFIG_MCP4728 is not set
CONFIG_MCP4922=m
CONFIG_TI_DAC082S085=m
CONFIG_TI_DAC5571=m
CONFIG_TI_DAC7311=m
CONFIG_TI_DAC7612=m
CONFIG_VF610_DAC=m
# end of Digital to analog converters

#
# IIO dummy driver
#
# CONFIG_IIO_SIMPLE_DUMMY is not set
# end of IIO dummy driver

#
# Filters
#
CONFIG_ADMV8818=m
# end of Filters

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
CONFIG_AD9523=m
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4350=m
CONFIG_ADF4371=m
# CONFIG_ADF4377 is not set
CONFIG_ADMV1013=m
CONFIG_ADMV1014=m
CONFIG_ADMV4420=m
CONFIG_ADRF6780=m
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=m
CONFIG_ADIS16130=m
CONFIG_ADIS16136=m
CONFIG_ADIS16260=m
CONFIG_ADXRS290=m
CONFIG_ADXRS450=m
CONFIG_BMG160=m
CONFIG_BMG160_I2C=m
CONFIG_BMG160_SPI=m
CONFIG_FXAS21002C=m
CONFIG_FXAS21002C_I2C=m
CONFIG_FXAS21002C_SPI=m
CONFIG_HID_SENSOR_GYRO_3D=m
CONFIG_MPU3050=m
CONFIG_MPU3050_I2C=m
CONFIG_IIO_ST_GYRO_3AXIS=m
CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
CONFIG_ITG3200=m
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
CONFIG_AFE4403=m
CONFIG_AFE4404=m
CONFIG_MAX30100=m
CONFIG_MAX30102=m
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
CONFIG_AM2315=m
CONFIG_DHT11=m
CONFIG_HDC100X=m
CONFIG_HDC2010=m
CONFIG_HID_SENSOR_HUMIDITY=m
CONFIG_HTS221=m
CONFIG_HTS221_I2C=m
CONFIG_HTS221_SPI=m
CONFIG_HTU21=m
CONFIG_SI7005=m
CONFIG_SI7020=m
# end of Humidity sensors

#
# Inertial measurement units
#
CONFIG_ADIS16400=m
CONFIG_ADIS16460=m
CONFIG_ADIS16475=m
CONFIG_ADIS16480=m
CONFIG_BMI160=m
CONFIG_BMI160_I2C=m
CONFIG_BMI160_SPI=m
CONFIG_BOSCH_BNO055=m
CONFIG_BOSCH_BNO055_SERIAL=m
CONFIG_BOSCH_BNO055_I2C=m
CONFIG_FXOS8700=m
CONFIG_FXOS8700_I2C=m
CONFIG_FXOS8700_SPI=m
CONFIG_KMX61=m
CONFIG_INV_ICM42600=m
CONFIG_INV_ICM42600_I2C=m
CONFIG_INV_ICM42600_SPI=m
CONFIG_INV_MPU6050_IIO=m
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_SPI=m
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_LSM6DSX_I2C=m
CONFIG_IIO_ST_LSM6DSX_SPI=m
CONFIG_IIO_ST_LSM9DS0=m
CONFIG_IIO_ST_LSM9DS0_I2C=m
CONFIG_IIO_ST_LSM9DS0_SPI=m
# end of Inertial measurement units

CONFIG_IIO_ADIS_LIB=m
CONFIG_IIO_ADIS_LIB_BUFFER=y

#
# Light sensors
#
CONFIG_ACPI_ALS=m
CONFIG_ADJD_S311=m
CONFIG_ADUX1020=m
CONFIG_AL3010=m
CONFIG_AL3320A=m
CONFIG_APDS9300=m
CONFIG_APDS9960=m
CONFIG_AS73211=m
CONFIG_BH1750=m
CONFIG_BH1780=m
CONFIG_CM32181=m
CONFIG_CM3232=m
CONFIG_CM3323=m
CONFIG_CM3605=m
CONFIG_CM36651=m
CONFIG_GP2AP002=m
CONFIG_GP2AP020A00F=m
CONFIG_SENSORS_ISL29018=m
CONFIG_SENSORS_ISL29028=m
CONFIG_ISL29125=m
CONFIG_HID_SENSOR_ALS=m
CONFIG_HID_SENSOR_PROX=m
CONFIG_JSA1212=m
# CONFIG_ROHM_BU27008 is not set
# CONFIG_ROHM_BU27034 is not set
CONFIG_RPR0521=m
CONFIG_LTR501=m
CONFIG_LTRF216A=m
CONFIG_LV0104CS=m
CONFIG_MAX44000=m
CONFIG_MAX44009=m
CONFIG_NOA1305=m
CONFIG_OPT3001=m
# CONFIG_OPT4001 is not set
CONFIG_PA12203001=m
CONFIG_SI1133=m
CONFIG_SI1145=m
CONFIG_STK3310=m
CONFIG_ST_UVIS25=m
CONFIG_ST_UVIS25_I2C=m
CONFIG_ST_UVIS25_SPI=m
CONFIG_TCS3414=m
CONFIG_TCS3472=m
CONFIG_SENSORS_TSL2563=m
CONFIG_TSL2583=m
CONFIG_TSL2591=m
CONFIG_TSL2772=m
CONFIG_TSL4531=m
CONFIG_US5182D=m
CONFIG_VCNL4000=m
CONFIG_VCNL4035=m
CONFIG_VEML6030=m
CONFIG_VEML6070=m
CONFIG_VL6180=m
CONFIG_ZOPT2201=m
# end of Light sensors

#
# Magnetometer sensors
#
CONFIG_AK8974=m
CONFIG_AK8975=m
CONFIG_AK09911=m
CONFIG_BMC150_MAGN=m
CONFIG_BMC150_MAGN_I2C=m
CONFIG_BMC150_MAGN_SPI=m
CONFIG_MAG3110=m
CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
CONFIG_MMC35240=m
CONFIG_IIO_ST_MAGN_3AXIS=m
CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
CONFIG_SENSORS_HMC5843=m
CONFIG_SENSORS_HMC5843_I2C=m
CONFIG_SENSORS_HMC5843_SPI=m
CONFIG_SENSORS_RM3100=m
CONFIG_SENSORS_RM3100_I2C=m
CONFIG_SENSORS_RM3100_SPI=m
# CONFIG_TI_TMAG5273 is not set
CONFIG_YAMAHA_YAS530=m
# end of Magnetometer sensors

#
# Multiplexers
#
CONFIG_IIO_MUX=m
# end of Multiplexers

#
# Inclinometer sensors
#
CONFIG_HID_SENSOR_INCLINOMETER_3D=m
CONFIG_HID_SENSOR_DEVICE_ROTATION=m
# end of Inclinometer sensors

#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=m
CONFIG_IIO_INTERRUPT_TRIGGER=m
CONFIG_IIO_TIGHTLOOP_TRIGGER=m
CONFIG_IIO_SYSFS_TRIGGER=y
# end of Triggers - standalone

#
# Linear and angular position sensors
#
CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
# end of Linear and angular position sensors

#
# Digital potentiometers
#
CONFIG_AD5110=m
CONFIG_AD5272=m
CONFIG_DS1803=m
CONFIG_MAX5432=m
CONFIG_MAX5481=m
CONFIG_MAX5487=m
CONFIG_MCP4018=m
CONFIG_MCP4131=m
CONFIG_MCP4531=m
CONFIG_MCP41010=m
CONFIG_TPL0102=m
# CONFIG_X9250 is not set
# end of Digital potentiometers

#
# Digital potentiostats
#
CONFIG_LMP91000=m
# end of Digital potentiostats

#
# Pressure sensors
#
CONFIG_ABP060MG=m
CONFIG_BMP280=m
CONFIG_BMP280_I2C=m
CONFIG_BMP280_SPI=m
CONFIG_DLHL60D=m
CONFIG_DPS310=m
CONFIG_HID_SENSOR_PRESS=m
CONFIG_HP03=m
CONFIG_ICP10100=m
CONFIG_MPL115=m
CONFIG_MPL115_I2C=m
CONFIG_MPL115_SPI=m
CONFIG_MPL3115=m
# CONFIG_MPRLS0025PA is not set
CONFIG_MS5611=m
CONFIG_MS5611_I2C=m
CONFIG_MS5611_SPI=m
CONFIG_MS5637=m
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_PRESS_I2C=m
CONFIG_IIO_ST_PRESS_SPI=m
CONFIG_T5403=m
CONFIG_HP206C=m
CONFIG_ZPA2326=m
CONFIG_ZPA2326_I2C=m
CONFIG_ZPA2326_SPI=m
# end of Pressure sensors

#
# Lightning sensors
#
CONFIG_AS3935=m
# end of Lightning sensors

#
# Proximity and distance sensors
#
# CONFIG_IRSD200 is not set
CONFIG_ISL29501=m
CONFIG_LIDAR_LITE_V2=m
CONFIG_MB1232=m
CONFIG_PING=m
CONFIG_RFD77402=m
CONFIG_SRF04=m
CONFIG_SX_COMMON=m
CONFIG_SX9310=m
CONFIG_SX9324=m
CONFIG_SX9360=m
CONFIG_SX9500=m
CONFIG_SRF08=m
CONFIG_VCNL3020=m
CONFIG_VL53L0X_I2C=m
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
CONFIG_AD2S90=m
CONFIG_AD2S1200=m
# end of Resolver to digital converters

#
# Temperature sensors
#
CONFIG_LTC2983=m
CONFIG_MAXIM_THERMOCOUPLE=m
CONFIG_HID_SENSOR_TEMP=m
CONFIG_MLX90614=m
CONFIG_MLX90632=m
CONFIG_TMP006=m
CONFIG_TMP007=m
CONFIG_TMP117=m
CONFIG_TSYS01=m
CONFIG_TSYS02D=m
# CONFIG_MAX30208 is not set
CONFIG_MAX31856=m
CONFIG_MAX31865=m
# end of Temperature sensors

# CONFIG_NTB is not set
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_DEBUG is not set
# CONFIG_PWM_ATMEL_TCB is not set
CONFIG_PWM_CLK=y
CONFIG_PWM_DWC=y
# CONFIG_PWM_FSL_FTM is not set
CONFIG_PWM_MESON=y
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_SUN4I=y
# CONFIG_PWM_XILINX is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_AL_FIC is not set
CONFIG_SUN6I_R_INTC=y
CONFIG_SUNXI_NMI_INTC=y
# CONFIG_XILINX_INTC is not set
CONFIG_PARTITION_PERCPU=y
CONFIG_MESON_IRQ_GPIO=y
# end of IRQ chip support

# CONFIG_IPACK_BUS is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_MESON=y
CONFIG_RESET_MESON_AUDIO_ARB=y
CONFIG_RESET_SCMI=y
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SUNXI=y
# CONFIG_RESET_TI_SYSCON is not set
# CONFIG_RESET_TI_TPS380X is not set

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_PHY_CAN_TRANSCEIVER is not set
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_SUN6I_MIPI_DPHY=y
CONFIG_PHY_SUN9I_USB=y
CONFIG_PHY_SUN50I_USB3=y
CONFIG_PHY_MESON8B_USB2=y
CONFIG_PHY_MESON_GXL_USB2=y
CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=y
CONFIG_PHY_MESON_G12A_USB2=y
CONFIG_PHY_MESON_G12A_USB3_PCIE=y
CONFIG_PHY_MESON_AXG_PCIE=y
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
CONFIG_PHY_MESON_AXG_MIPI_DPHY=y

#
# PHY drivers for Broadcom platforms
#
# CONFIG_BCM_KONA_USB2_PHY is not set
# end of PHY drivers for Broadcom platforms

# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
# CONFIG_PHY_CADENCE_DPHY_RX is not set
# CONFIG_PHY_CADENCE_SIERRA is not set
# CONFIG_PHY_CADENCE_SALVO is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_PHY_LAN966X_SERDES is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
# CONFIG_PHY_QCOM_USB_HS is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
CONFIG_PHY_ROCKCHIP_DP=y
CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
CONFIG_PHY_ROCKCHIP_PCIE=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=m
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
CONFIG_PHY_ROCKCHIP_TYPEC=m
CONFIG_PHY_ROCKCHIP_USB=y
CONFIG_PHY_ROCKCHIP_USBDP=m
# CONFIG_PHY_SAMSUNG_USB2 is not set
# CONFIG_PHY_TUSB1210 is not set
# end of PHY Subsystem

# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set

#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCI400_PMU=y
CONFIG_ARM_CCI5xx_PMU=y
CONFIG_ARM_CCN=m
CONFIG_ARM_CMN=m
CONFIG_ARM_PMU=y
CONFIG_ARM_PMU_ACPI=y
CONFIG_ARM_SMMU_V3_PMU=y
CONFIG_ARM_PMUV3=y
CONFIG_ARM_DSU_PMU=m
CONFIG_ARM_SPE_PMU=m
# CONFIG_ARM_DMC620_PMU is not set
# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set
# CONFIG_HISI_PMU is not set
# CONFIG_HISI_PCIE_PMU is not set
# CONFIG_HNS3_PMU is not set
# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set
# CONFIG_MESON_DDR_PMU is not set
# end of Performance monitor support

CONFIG_RAS=y
# CONFIG_USB4 is not set

#
# Android
#
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_BINDERFS=y
CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
# end of Android

# CONFIG_LIBNVDIMM is not set
CONFIG_DAX=y
CONFIG_DEV_DAX=m
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y

#
# Layout Types
#
CONFIG_NVMEM_LAYOUT_SL28_VPD=m
CONFIG_NVMEM_LAYOUT_ONIE_TLV=m
# end of Layout Types

CONFIG_NVMEM_MESON_EFUSE=y
CONFIG_NVMEM_MESON_MX_EFUSE=y
CONFIG_NVMEM_RMEM=y
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
CONFIG_NVMEM_ROCKCHIP_OTP=y
CONFIG_NVMEM_SPMI_SDAM=y
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_NVMEM_U_BOOT_ENV=y

#
# HW tracing support
#
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# CONFIG_HISI_PTT is not set
# end of HW tracing support

CONFIG_FPGA=m
CONFIG_ALTERA_PR_IP_CORE=m
CONFIG_ALTERA_PR_IP_CORE_PLAT=m
CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
CONFIG_FPGA_MGR_ALTERA_CVP=m
CONFIG_FPGA_MGR_XILINX_SPI=m
CONFIG_FPGA_MGR_ICE40_SPI=m
CONFIG_FPGA_MGR_MACHXO2_SPI=m
CONFIG_FPGA_BRIDGE=m
CONFIG_ALTERA_FREEZE_BRIDGE=m
CONFIG_XILINX_PR_DECOUPLER=m
CONFIG_FPGA_REGION=m
CONFIG_OF_FPGA_REGION=m
CONFIG_FPGA_DFL=m
CONFIG_FPGA_DFL_FME=m
CONFIG_FPGA_DFL_FME_MGR=m
CONFIG_FPGA_DFL_FME_BRIDGE=m
CONFIG_FPGA_DFL_FME_REGION=m
CONFIG_FPGA_DFL_AFU=m
CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m
CONFIG_FPGA_DFL_PCI=m
CONFIG_FPGA_MGR_MICROCHIP_SPI=m
# CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI is not set
# CONFIG_FSI is not set
CONFIG_TEE=y
CONFIG_OPTEE=y
# CONFIG_OPTEE_INSECURE_LOAD_IMAGE is not set
CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
# CONFIG_MUX_ADGS1408 is not set
CONFIG_MUX_GPIO=m
CONFIG_MUX_MMIO=m
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
# CONFIG_SLIMBUS is not set
# CONFIG_INTERCONNECT is not set
CONFIG_COUNTER=m
CONFIG_INTERRUPT_CNT=m
# CONFIG_MOST is not set
# CONFIG_PECI is not set
# CONFIG_HTE is not set
# CONFIG_CDX_BUS is not set
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_IOMAP=y
CONFIG_BUFFER_HEAD=y
CONFIG_LEGACY_DIRECT_IO=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=m
# CONFIG_REISERFS_CHECK is not set
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
# CONFIG_JFS_DEBUG is not set
# CONFIG_JFS_STATISTICS is not set
CONFIG_XFS_FS=y
CONFIG_XFS_SUPPORT_V4=y
CONFIG_XFS_SUPPORT_ASCII_CI=y
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
# CONFIG_XFS_RT is not set
# CONFIG_XFS_ONLINE_SCRUB is not set
# CONFIG_XFS_WARN is not set
# CONFIG_XFS_DEBUG is not set
CONFIG_GFS2_FS=m
CONFIG_GFS2_FS_LOCKING_DLM=y
CONFIG_OCFS2_FS=m
CONFIG_OCFS2_FS_O2CB=m
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
CONFIG_OCFS2_FS_STATS=y
CONFIG_OCFS2_DEBUG_MASKLOG=y
# CONFIG_OCFS2_DEBUG_FS is not set
CONFIG_BTRFS_FS=y
CONFIG_BTRFS_FS_POSIX_ACL=y
# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
# CONFIG_BTRFS_DEBUG is not set
# CONFIG_BTRFS_ASSERT is not set
# CONFIG_BTRFS_FS_REF_VERIFY is not set
CONFIG_NILFS2_FS=m
CONFIG_F2FS_FS=y
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
# CONFIG_F2FS_FAULT_INJECTION is not set
CONFIG_F2FS_FS_COMPRESSION=y
CONFIG_F2FS_FS_LZO=y
CONFIG_F2FS_FS_LZORLE=y
CONFIG_F2FS_FS_LZ4=y
CONFIG_F2FS_FS_LZ4HC=y
CONFIG_F2FS_FS_ZSTD=y
CONFIG_F2FS_IOSTAT=y
# CONFIG_F2FS_UNFAIR_RWSEM is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=y
# CONFIG_FS_ENCRYPTION_INLINE_CRYPT is not set
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=m
# CONFIG_QFMT_V1 is not set
# CONFIG_QFMT_V2 is not set
CONFIG_QUOTACTL=y
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_VIRTIO_FS=m
CONFIG_OVERLAY_FS=y
# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
# CONFIG_OVERLAY_FS_METACOPY is not set
# CONFIG_OVERLAY_FS_DEBUG is not set

#
# Caches
#
CONFIG_NETFS_SUPPORT=y
# CONFIG_NETFS_STATS is not set
CONFIG_FSCACHE=y
# CONFIG_FSCACHE_STATS is not set
# CONFIG_FSCACHE_DEBUG is not set
CONFIG_CACHEFILES=m
# CONFIG_CACHEFILES_DEBUG is not set
# CONFIG_CACHEFILES_ERROR_INJECTION is not set
# CONFIG_CACHEFILES_ONDEMAND is not set
# end of Caches

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
# CONFIG_FAT_DEFAULT_UTF8 is not set
CONFIG_EXFAT_FS=y
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_NTFS_FS is not set
CONFIG_NTFS3_FS=m
# CONFIG_NTFS3_64BIT_CLUSTER is not set
CONFIG_NTFS3_LZX_XPRESS=y
CONFIG_NTFS3_FS_POSIX_ACL=y
# end of DOS/FAT/EXFAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_TMPFS_INODE64 is not set
# CONFIG_TMPFS_QUOTA is not set
CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=m
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
CONFIG_ECRYPT_FS=m
# CONFIG_ECRYPT_FS_MESSAGING is not set
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
CONFIG_UBIFS_FS=m
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
CONFIG_CRAMFS=m
CONFIG_CRAMFS_BLOCKDEV=y
# CONFIG_CRAMFS_MTD is not set
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_FILE_CACHE is not set
CONFIG_SQUASHFS_FILE_DIRECT=y
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set
CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
# CONFIG_SQUASHFS_XATTR is not set
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_ZSTD=y
# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
CONFIG_PSTORE_COMPRESS=y
# CONFIG_PSTORE_CONSOLE is not set
# CONFIG_PSTORE_PMSG is not set
# CONFIG_PSTORE_RAM is not set
# CONFIG_PSTORE_BLK is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_EROFS_FS=m
# CONFIG_EROFS_FS_DEBUG is not set
CONFIG_EROFS_FS_XATTR=y
CONFIG_EROFS_FS_POSIX_ACL=y
# CONFIG_EROFS_FS_SECURITY is not set
CONFIG_EROFS_FS_ZIP=y
CONFIG_EROFS_FS_ZIP_LZMA=y
# CONFIG_EROFS_FS_ZIP_DEFLATE is not set
# CONFIG_EROFS_FS_PCPU_KTHREAD is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V2=m
CONFIG_NFS_V3=m
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=m
# CONFIG_NFS_SWAP is not set
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=m
CONFIG_PNFS_BLOCK=m
CONFIG_PNFS_FLEXFILE_LAYOUT=m
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
# CONFIG_NFS_V4_1_MIGRATION is not set
CONFIG_NFS_V4_SECURITY_LABEL=y
CONFIG_NFS_FSCACHE=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
CONFIG_NFS_DEBUG=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
CONFIG_NFS_V4_2_READ_PLUS=y
CONFIG_NFSD=m
# CONFIG_NFSD_V2 is not set
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
CONFIG_NFSD_PNFS=y
CONFIG_NFSD_BLOCKLAYOUT=y
CONFIG_NFSD_SCSILAYOUT=y
CONFIG_NFSD_FLEXFILELAYOUT=y
CONFIG_NFSD_V4_2_INTER_SSC=y
CONFIG_NFSD_V4_SECURITY_LABEL=y
CONFIG_GRACE_PERIOD=m
CONFIG_LOCKD=m
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=m
CONFIG_NFS_COMMON=y
CONFIG_NFS_V4_2_SSC_HELPER=y
CONFIG_SUNRPC=m
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_BACKCHANNEL=y
CONFIG_RPCSEC_GSS_KRB5=m
CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y
CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA=y
CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y
CONFIG_SUNRPC_DEBUG=y
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
# CONFIG_CEPH_FS_SECURITY_LABEL is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CIFS_DEBUG=y
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set
CONFIG_CIFS_DFS_UPCALL=y
# CONFIG_CIFS_SWN_UPCALL is not set
# CONFIG_CIFS_FSCACHE is not set
CONFIG_SMB_SERVER=m
CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
CONFIG_SMB_SERVER_KERBEROS5=y
CONFIG_SMBFS=m
CONFIG_CODA_FS=m
CONFIG_AFS_FS=m
# CONFIG_AFS_DEBUG is not set
CONFIG_AFS_FSCACHE=y
# CONFIG_AFS_DEBUG_CURSOR is not set
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
CONFIG_9P_FS_SECURITY=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf-8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=m
CONFIG_NLS_MAC_GAELIC=m
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=y
CONFIG_NLS_UCS2_UTILS=m
CONFIG_DLM=m
# CONFIG_DLM_DEBUG is not set
# CONFIG_UNICODE is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_BIG_KEYS is not set
# CONFIG_TRUSTED_KEYS is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_PROC_MEM_ALWAYS_FORCE=y
# CONFIG_PROC_MEM_FORCE_PTRACE is not set
# CONFIG_PROC_MEM_NO_FORCE is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
# CONFIG_SECURITY_NETWORK_XFRM is not set
CONFIG_SECURITY_PATH=y
CONFIG_LSM_MMAP_MIN_ADDR=32768
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
# CONFIG_SECURITY_SELINUX_DEBUG is not set
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
CONFIG_SECURITY_APPARMOR=y
# CONFIG_SECURITY_APPARMOR_DEBUG is not set
CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y
CONFIG_SECURITY_APPARMOR_HASH=y
CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y
CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
# CONFIG_SECURITY_SAFESETID is not set
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
# CONFIG_SECURITY_LANDLOCK is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
CONFIG_INTEGRITY_AUDIT=y
# CONFIG_IMA is not set
# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
# CONFIG_EVM is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
CONFIG_INIT_STACK_NONE=y
# CONFIG_INIT_STACK_ALL_PATTERN is not set
# CONFIG_INIT_STACK_ALL_ZERO is not set
# CONFIG_GCC_PLUGIN_STACKLEAK is not set
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
# CONFIG_ZERO_CALL_USED_REGS is not set
# end of Memory initialization

#
# Hardening of kernel data structures
#
# CONFIG_LIST_HARDENED is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# end of Hardening of kernel data structures

CONFIG_RANDSTRUCT_NONE=y
# CONFIG_RANDSTRUCT_FULL is not set
# CONFIG_RANDSTRUCT_PERFORMANCE is not set
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=y
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SIG=y
CONFIG_CRYPTO_SIG2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=y
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_ENGINE=y
# end of Crypto core or helper

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=y
# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
CONFIG_CRYPTO_ECDSA=y
CONFIG_CRYPTO_ECRDSA=y
CONFIG_CRYPTO_SM2=y
CONFIG_CRYPTO_CURVE25519=y
# end of Public-key cryptography

#
# Block ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
CONFIG_CRYPTO_ANUBIS=y
CONFIG_CRYPTO_ARIA=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_BLOWFISH_COMMON=y
CONFIG_CRYPTO_CAMELLIA=y
CONFIG_CRYPTO_CAST_COMMON=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=y
CONFIG_CRYPTO_KHAZAD=y
CONFIG_CRYPTO_SEED=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_GENERIC=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y
# end of Block ciphers

#
# Length-preserving ciphers and modes
#
CONFIG_CRYPTO_ADIANTUM=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HCTR2=y
CONFIG_CRYPTO_KEYWRAP=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XCTR=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_NHPOLY1305=y
# end of Length-preserving ciphers and modes

#
# AEAD (authenticated encryption with associated data) ciphers
#
CONFIG_CRYPTO_AEGIS128=y
CONFIG_CRYPTO_AEGIS128_SIMD=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_GENIV=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_ESSIV=y
# end of AEAD (authenticated encryption with associated data) ciphers

#
# Hashes, digests, and MACs
#
CONFIG_CRYPTO_BLAKE2B=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_POLYVAL=y
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_RMD160=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_SM3_GENERIC=y
CONFIG_CRYPTO_STREEBOG=y
CONFIG_CRYPTO_VMAC=y
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_XXHASH=y
# end of Hashes, digests, and MACs

#
# CRCs (cyclic redundancy checks)
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
# end of CRCs (cyclic redundancy checks)

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=y
CONFIG_CRYPTO_ZSTD=y
# end of Compression

#
# Random number generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
# CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE is not set
# end of Random number generation

#
# Userspace interface
#
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
CONFIG_CRYPTO_STATS=y
# end of Userspace interface

CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_NHPOLY1305_NEON=y
CONFIG_CRYPTO_CHACHA20_NEON=y

#
# Accelerated Cryptographic Algorithms for CPU (arm64)
#
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_POLY1305_NEON=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA512_ARM64_CE=y
CONFIG_CRYPTO_SHA3_ARM64=y
CONFIG_CRYPTO_SM3_NEON=y
CONFIG_CRYPTO_SM3_ARM64_CE=y
CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CRYPTO_SM4_ARM64_CE=y
CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y
CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
# end of Accelerated Cryptographic Algorithms for CPU (arm64)

CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_ALLWINNER=y
CONFIG_CRYPTO_DEV_SUN4I_SS=y
CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set
CONFIG_CRYPTO_DEV_SUN8I_CE=y
CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG=y
CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
CONFIG_CRYPTO_DEV_SUN8I_SS=y
CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG=y
CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_CCP is not set
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set
# CONFIG_CRYPTO_DEV_QAT_C62X is not set
# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set
# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set
# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set
# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
CONFIG_CRYPTO_DEV_ROCKCHIP=m
# CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG is not set
CONFIG_CRYPTO_DEV_ROCKCHIP2=m
# CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG is not set
CONFIG_CRYPTO_DEV_VIRTIO=m
CONFIG_CRYPTO_DEV_CRYPTODEV_LINUX=m
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
CONFIG_CRYPTO_DEV_CCREE=y
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
# CONFIG_CRYPTO_DEV_HISI_TRNG is not set
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG=y
# CONFIG_CRYPTO_DEV_JH7110 is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
CONFIG_PKCS7_MESSAGE_PARSER=y
CONFIG_PKCS7_TEST_KEY=m
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
# CONFIG_FIPS_SIGNATURE_SELFTEST is not set

#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_RAID6_PQ=y
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=m
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
CONFIG_INDIRECT_PIO=y
# CONFIG_TRACE_MMIO_ACCESS is not set

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
CONFIG_CRYPTO_LIB_CURVE25519=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines

CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC64_ROCKSOFT=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=y
CONFIG_CRC4=m
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=y
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
CONFIG_RANDOM32_SELFTEST=y
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
# CONFIG_XZ_DEC_SPARC is not set
CONFIG_XZ_DEC_MICROLZMA=y
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_INTERVAL_TREE=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_FLAGS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_SWIOTLB=y
# CONFIG_SWIOTLB_DYNAMIC is not set
CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
# CONFIG_DMA_RESTRICTED_POOL is not set
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y

#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=256
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_DMA_MAP_BENCHMARK is not set
CONFIG_SGL_ALLOC=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_SG_POOL=y
CONFIG_ARCH_STACKWALK=y
CONFIG_STACKDEPOT=y
CONFIG_SBITMAP=y
# end of Library routines

CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_CALLER is not set
# CONFIG_STACKTRACE_BUILD_ID is not set
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Compile-time checks and compiler options
#
CONFIG_AS_HAS_NON_CONST_LEB128=y
CONFIG_DEBUG_INFO_NONE=y
# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_DEBUG_INFO_DWARF5 is not set
CONFIG_FRAME_WARN=2048
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_READABLE_ASM is not set
CONFIG_HEADERS_INSTALL=y
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_VMLINUX_MAP is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_ARCH_KCSAN=y
CONFIG_HAVE_KCSAN_COMPILER=y
# CONFIG_KCSAN is not set
# end of Generic Kernel Debugging Instruments

#
# Networking Debugging
#
# CONFIG_NET_DEV_REFCNT_TRACKER is not set
# CONFIG_NET_NS_REFCNT_TRACKER is not set
# CONFIG_DEBUG_NET is not set
# end of Networking Debugging

#
# Memory Debugging
#
# CONFIG_PAGE_EXTENSION is not set
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_SLUB_DEBUG=y
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_PAGE_OWNER is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
# CONFIG_DEBUG_WX is not set
CONFIG_GENERIC_PTDUMP=y
# CONFIG_PTDUMP_DEBUGFS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_PER_VMA_LOCK_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SHRINKER_DEBUG is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
CONFIG_HAVE_ARCH_KFENCE=y
# CONFIG_KFENCE is not set
# end of Memory Debugging

# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SOFTLOCKUP_DETECTOR is not set
CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y
# CONFIG_HARDLOCKUP_DETECTOR is not set
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
# CONFIG_WQ_WATCHDOG is not set
# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set
# CONFIG_TEST_LOCKUP is not set
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHED_INFO=y
# CONFIG_SCHEDSTATS is not set
# end of Scheduler Debugging

# CONFIG_DEBUG_TIMEKEEPING is not set

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
# CONFIG_DEBUG_RWSEMS is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
# end of Lock Debugging (spinlocks, mutexes, etc...)

# CONFIG_DEBUG_IRQFLAGS is not set
CONFIG_STACKTRACE=y
# CONFIG_DEBUG_KOBJECT is not set

#
# Debug kernel data structures
#
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_MAPLE_TREE is not set
# end of Debug kernel data structures

#
# RCU Debugging
#
# CONFIG_RCU_SCALE_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
# CONFIG_RCU_CPU_STALL_CPUTIME is not set
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# end of RCU Debugging

# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_LATENCYTOP is not set
# CONFIG_DEBUG_CGROUP_REF is not set
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_TRACING=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_BOOTTIME_TRACING is not set
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_HWLAT_TRACER is not set
# CONFIG_OSNOISE_TRACER is not set
# CONFIG_TIMERLAT_TRACER is not set
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
# CONFIG_FTRACE_SYSCALLS is not set
# CONFIG_TRACER_SNAPSHOT is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_KPROBE_EVENTS=y
CONFIG_UPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_DYNAMIC_EVENTS=y
CONFIG_PROBE_EVENTS=y
# CONFIG_SYNTH_EVENTS is not set
# CONFIG_USER_EVENTS is not set
# CONFIG_HIST_TRIGGERS is not set
# CONFIG_TRACE_EVENT_INJECT is not set
# CONFIG_TRACEPOINT_BENCHMARK is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_TRACE_EVAL_MAP_FILE is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
# CONFIG_KPROBE_EVENT_GEN_TEST is not set
# CONFIG_RV is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y
CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y
# CONFIG_STRICT_DEVMEM is not set

#
# arm64 Debugging
#
# CONFIG_PID_IN_CONTEXTIDR is not set
# CONFIG_ARM64_RELOC_TEST is not set
# CONFIG_CORESIGHT is not set
# end of arm64 Debugging

#
# Kernel Testing and Coverage
#
# CONFIG_KUNIT is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
# CONFIG_FUNCTION_ERROR_INJECTION is not set
# CONFIG_FAULT_INJECTION is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
# CONFIG_KCOV is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_TEST_DHRY is not set
# CONFIG_LKDTM is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_DIV64 is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TEST_REF_TRACKER is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_ASYNC_RAID6_TEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_STRING_SELFTEST is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_SCANF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_TEST_MAPLE_TREE is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_VMALLOC is not set
# CONFIG_TEST_USER_COPY is not set
CONFIG_TEST_BPF=m
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_DYNAMIC_DEBUG is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_FREE_PAGES is not set
CONFIG_ARCH_USE_MEMTEST=y
CONFIG_MEMTEST=y
# end of Kernel Testing and Coverage

#
# Rust hacking
#
# end of Rust hacking
# end of Kernel hacking


================================================
FILE: kernel-patch/README.md
================================================
# Kernel Patch Usage Guide

When performing cloud compilation using GitHub Actions, you can use the `kernel_patch` parameter to specify the directory containing kernel patches in your repository. Common kernel patches applicable to all kernel series use a fixed directory name (`common-kernel-patches`). Patches specific to a particular series, such as [linux-5.15.y](https://github.com/unifreq/linux-5.15.y), use a directory name `matching the kernel source repository name`. Directories with other custom names (such as the `deprecated-patches` directory for storing obsolete patches) will be skipped during kernel compilation and will not be applied.

```shell
~/kernel
    └── <your-kernel-patches>
        ├── common-kernel-patches  # Fixed directory name: Stores kernel patches common to all versions
        ├── linux-5.15.y           # Same as the kernel source library: stores dedicated patches
        ├── linux-6.1.y
        ├── linux-5.10.y-rk35xx
        └── more kernel directory...
```

The usage in the kernel compilation script can be found in the settings of [compile-mainline-beta-kernel.yml](../.github/workflows/compile-mainline-beta-kernel.yml):

```yaml
- name: Compile the kernel
  uses: ophub/amlogic-s9xxx-armbian@main
  with:
    build_target: kernel
    kernel_version: 5.15.1_6.1.1
    kernel_auto: true
    kernel_config: kernel-config/release/stable
    kernel_patch: kernel-patch/beta
    auto_patch: true
```

During kernel compilation, all patches with the `.patch` suffix under `common-kernel-patches` are enumerated and applied first, followed by the dedicated patches for the currently compiled kernel (e.g., linux-6.1.y). For more details, please refer to [Kernel Compilation Guide](https://github.com/ophub/amlogic-s9xxx-armbian/tree/main/compile-kernel) and [Kernel Patch Addition Guide](https://github.com/ophub/amlogic-s9xxx-armbian/tree/main/documents/README.md#9-compiling-armbian-kernel).

# 内核补丁使用说明

在 GitHub Actions 云编译时，可以使用 `kernel_patch` 参数指定内核补丁在仓库中的目录。其中适用于所有系列内核的通用补丁，采用固定目录名称（`common-kernel-patches`）；仅适用于指定系列的补丁，例如 [linux-5.15.y](https://github.com/unifreq/linux-5.15.y)，使用`与内核源码仓库同名`的目录名称。使用其他自定义名称的目录（例如存放已弃用补丁的 `deprecated-patches` 目录）在内核编译时将被跳过，不会被应用。

```shell
~/kernel
    └── <your-kernel-patches>
        ├── common-kernel-patches  # 固定目录名：存放各版本都通用的内核补丁
        ├── linux-5.15.y           # 与内核源码库同名：存放专用补丁
        ├── linux-6.1.y
        ├── linux-5.10.y-rk35xx
        └── more kernel directory...
```

在内核编译脚本中的使用方法可参考 [compile-mainline-beta-kernel.yml](../.github/workflows/compile-mainline-beta-kernel.yml) 中的设置：

```yaml
- name: Compile the kernel
  uses: ophub/amlogic-s9xxx-armbian@main
  with:
    build_target: kernel
    kernel_version: 5.15.1_6.1.1
    kernel_auto: true
    kernel_config: kernel-config/release/stable
    kernel_patch: kernel-patch/beta
    auto_patch: true
```

在编译内核时，会先遍历 `common-kernel-patches` 下后缀为 `.patch` 的全部补丁并应用，然后再遍历当前编译内核（如：linux-6.1.y）的专用补丁并应用。更多详情请参考[内核编译方法](https://github.com/ophub/amlogic-s9xxx-armbian/tree/main/compile-kernel)和[内核补丁添加方法](https://github.com/ophub/amlogic-s9xxx-armbian/tree/main/documents/README.cn.md#9-编译-armbian-内核)中的详细介绍。


================================================
FILE: kernel-patch/beta/common-kernel-patches/301-dts-add-rockchip-rk3399-mpc1903-dtb.patch
================================================
From d738ec5df78c21fc22fb2860af9a8cc7481d2c9d Mon Sep 17 00:00:00 2001
From: xxxxx <67037522+xxxxx@users.noreply.github.com>
Date: Mon, 18 Sep 2023 03:09:25 +0000
Subject: [PATCH] Add rk3399-mpc1903

---
 arch/arm64/boot/dts/rockchip/Makefile         |   1 +
 .../boot/dts/rockchip/rk3399-mpc1903.dts      | 814 ++++++++++++++++++
 2 files changed, 815 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-mpc1903.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index f97cf4c32..ff70c1b4d 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -37,6 +37,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-dlfr100.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-mpc1903.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-dumo.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-mpc1903.dts b/arch/arm64/boot/dts/rockchip/rk3399-mpc1903.dts
new file mode 100644
index 000000000..7cac536bb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-mpc1903.dts
@@ -0,0 +1,814 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+	model = "Rocktech MPC1903";
+	compatible = "rocktech,mpc1903", "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdhci;
+		mmc2 = &sdio0;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc12v_dcin: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_hub: vcc5v0-hub {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_hub_en>;
+		regulator-name = "vcc5v0_hub";
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	/*vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_drv>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-name = "vcc3v3_pcie";
+		vin-supply = <&vcc5v0_sys>;
+	};*/
+
+	vcc3v3_gsm: vcc3v3-gsm {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_gsm_en>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-name = "vcc3v3_gsm";
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_host: vcc5v0-host {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host";
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_typec: vcc5v0-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec_en>;
+		regulator-name = "vcc5v0_typec";
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_lan: vcc-phy {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_lan";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&status_led_pin>;
+
+		status_led: status-led {
+			label = "status_led";
+			linux,default-trigger = "heartbeat";
+			gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	wireless_wlan: wireless-wlan {
+		compatible = "wlan-platdata";
+		rockchip,grf = <&grf>;
+		wifi_chip_type = "rtl8723bu";
+		sdio_vref = <1800>;
+		WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	wireless_bluetooth: wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default", "rts_gpio";
+		pinctrl-0 = <&uart0_rts>;
+		pinctrl-1 = <&uart0_gpios>;
+		BT,reset_gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
+		BT,wake_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+		BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_lan>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_i2c_xfer>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc5v0_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_3v0>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			gen_1v8: LDO_REG1 {
+				regulator-name = "gen_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			gen_3v0: LDO_REG2 {
+				regulator-name = "gen_gen";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_codec: LDO_REG7 {
+				regulator-name = "vcc1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_s3";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel1_pin>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel2_pin>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rtc: pcf85263@51 {
+		compatible = "nxp,pcf85263";
+		reg = <0x51>;
+		pinctrl-0 = <&rtc_int>;
+		rtc_int_gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	clock-frequency = <200000>;
+
+	/*rt5651: rt5651@1a {
+		#sound-dai-cells = <0>;
+		compatible = "realtek,rt5651";
+		reg = <0x1a>;
+		clocks = <&cru SCLK_I2S_8CH_OUT>;
+		clock-names = "mclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s_8ch_mclk>;
+		spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+		hp-det-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+		status = "okay";
+	};*/
+
+	es8323: es8323@10 {
+		#sound-dai-cells = <0x0>;
+		compatible = "everest,es8323";
+		reg = <0x10>;
+		clocks = <&cru SCLK_I2S_8CH_OUT>;
+		clock-names = "mclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&spk_con &spk_pwr &amp_pwr &i2s_8ch_mclk>;
+		spk-con-gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
+		amp-pwr-en = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
+		spk-pwr = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c6 {
+	status = "okay";
+};
+
+&i2s0 {
+	rockchip,i2s-broken-burst-len;
+	rockchip,playback-channels = <8>;
+	rockchip,capture-channels = <8>;
+	status = "okay";
+};
+
+&i2s2 {
+	rockchip,bclk-fs = <128>;
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+
+	bt656-supply = <&vcc_3v0>;
+	audio-supply = <&vcc1v8_codec>;
+	sdmmc-supply = <&vcc_sdio>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+	status = "okay";
+
+	pmu1830-supply = <&vcc_3v0>;
+};
+
+/*&pcie_phy {
+	status = "okay";
+};
+
+&pcie0 {
+	ep-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>;
+	num-lanes = <4>;
+	pinctrl-0 = <&pcie_clkreqnb_cpm>;
+	pinctrl-names = "default";
+	status = "okay";
+};*/
+
+&pinctrl {
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vsel1_pin: vsel1-pin {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		vsel2_pin: vsel2-pin {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	usb2 {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_hub_en: vcc5v0-hub-en {
+			rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vcc3v3_gsm_en: vcc3v3-gsm-en {
+			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb-typec {
+		vcc5v0_typec_en: vcc5v0-typec-en {
+			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rtc {
+		rtc_int: rtc-int {
+			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	led {
+		status_led_pin: status-led-pin {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	rockchip-key {
+		power_key: power-key {
+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	es8323 {
+		spk_con: spk-con {
+			rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		spk_pwr: spk-pwr {
+			rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		amp_pwr: amp-pwr {
+			rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+   i2s0 {
+       i2s_8ch_mclk: i2s-8ch-mclk {
+           ockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
+       };
+   };
+
+	fusb30x {
+		fusb0_int: fusb0-int {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	wireless-bluetooth {
+		uart0_gpios: uart0-gpios {
+			rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+/*	pcie {
+		pcie_drv: pcie-drv {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};*/
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&saradc {
+	status = "okay";
+
+	vref-supply = <&vcc_1v8>;
+};
+
+&sdio0 {
+	max-frequency = <200000000>;
+	bus-width = <4>;
+	clock-frequency = <50000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
+	status = "okay";
+};
+
+&sdhci {
+	max-frequency = <150000000>;
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+	rockchip,hw-tshut-temp = <120000>;
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy0_host {
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
+&u2phy1_host {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};


================================================
FILE: kernel-patch/beta/deprecated-patches/5.10.y-101-arm64-add-text_offset.patch
================================================
From d1aeee50b5d43042c7c71ec101953349e350f3cf Mon Sep 17 00:00:00 2001
From: xxxxx <67037522+xxxxx@users.noreply.github.com>
Date: Sun, 23 Apr 2023 02:02:44 +0000
Subject: [PATCH] Add text_offset

---
 arch/arm64/Makefile                       |  5 +++++
 arch/arm64/include/asm/boot.h             |  3 ++-
 arch/arm64/include/asm/kernel-pgtable.h   |  2 +-
 arch/arm64/include/asm/memory.h           |  2 +-
 arch/arm64/kernel/Makefile                |  3 +++
 arch/arm64/kernel/head.S                  | 10 +++++-----
 arch/arm64/kernel/image.h                 |  1 +
 arch/arm64/kernel/setup.c                 |  3 ---
 arch/arm64/kernel/vmlinux.lds.S           |  4 ++--
 drivers/firmware/efi/libstub/Makefile     |  1 +
 drivers/firmware/efi/libstub/arm64-stub.c |  6 +++---
 11 files changed, 24 insertions(+), 16 deletions(-)

diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index 96dcddc358..4abbcdc974 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -11,6 +11,7 @@
 # Copyright (C) 1995-2001 by Russell King
 
 LDFLAGS_vmlinux	:=--no-undefined -X --pic-veneer
+CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET)
 
 ifeq ($(CONFIG_RELOCATABLE), y)
 # Pass --no-apply-dynamic-relocs to restore pre-binutils-2.27 behaviour
@@ -134,6 +135,10 @@ endif
 # Default value
 head-y		:= arch/arm64/kernel/head.o
 
+# The byte offset of the kernel image in RAM from the start of RAM.
+TEXT_OFFSET := 0x01080000
+export TEXT_OFFSET
+
 ifeq ($(CONFIG_KASAN_SW_TAGS), y)
 KASAN_SHADOW_SCALE_SHIFT := 4
 else
diff --git a/arch/arm64/include/asm/boot.h b/arch/arm64/include/asm/boot.h
index 3e7943fd17..c7f67da13c 100644
--- a/arch/arm64/include/asm/boot.h
+++ b/arch/arm64/include/asm/boot.h
@@ -13,7 +13,8 @@
 #define MAX_FDT_SIZE		SZ_2M
 
 /*
- * arm64 requires the kernel image to placed at a 2 MB aligned base address
+ * arm64 requires the kernel image to placed
+ * TEXT_OFFSET bytes beyond a 2 MB aligned base
  */
 #define MIN_KIMG_ALIGN		SZ_2M
 
diff --git a/arch/arm64/include/asm/kernel-pgtable.h b/arch/arm64/include/asm/kernel-pgtable.h
index 4b06cf9a8c..8aa453127a 100644
--- a/arch/arm64/include/asm/kernel-pgtable.h
+++ b/arch/arm64/include/asm/kernel-pgtable.h
@@ -86,7 +86,7 @@
 			+ EARLY_PGDS((vstart), (vend)) 	/* each PGDIR needs a next level page table */	\
 			+ EARLY_PUDS((vstart), (vend))	/* each PUD needs a next level page table */	\
 			+ EARLY_PMDS((vstart), (vend)))	/* each PMD needs a next level page table */
-#define INIT_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR, _end))
+#define INIT_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR + TEXT_OFFSET, _end))
 #define IDMAP_DIR_SIZE		(IDMAP_PGTABLE_LEVELS * PAGE_SIZE)
 
 /* Initial memory map size */
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index 505bdd75b5..ebc750ca8e 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -173,7 +173,7 @@ extern s64			memstart_addr;
 /* PHYS_OFFSET - the physical address of the start of memory. */
 #define PHYS_OFFSET		({ VM_BUG_ON(memstart_addr & 1); memstart_addr; })
 
-/* the virtual base of the kernel image */
+/* the virtual base of the kernel image (minus TEXT_OFFSET) */
 extern u64			kimage_vaddr;
 
 /* the offset between the kernel virtual and physical mappings */
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index bbaf0bc4ad..8ac70422a0 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -3,6 +3,9 @@
 # Makefile for the linux kernel.
 #
 
+
+CPPFLAGS_vmlinux.lds	:= -DTEXT_OFFSET=$(TEXT_OFFSET)
+AFLAGS_head.o		:= -DTEXT_OFFSET=$(TEXT_OFFSET)
 CFLAGS_armv8_deprecated.o := -I$(src)
 
 CFLAGS_REMOVE_ftrace.o = $(CC_FLAGS_FTRACE)
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 351ee64c7d..834030aa6c 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -36,7 +36,7 @@
 
 #include "efi-header.S"
 
-#define __PHYS_OFFSET	KERNEL_START
+#define __PHYS_OFFSET  (KERNEL_START - TEXT_OFFSET)
 
 #if (PAGE_OFFSET & 0x1fffff) != 0
 #error PAGE_OFFSET must be at least 2MB aligned
@@ -51,7 +51,7 @@
  *   x0 = physical address to the FDT blob.
  *
  * This code is mostly position independent so you call this at
- * __pa(PAGE_OFFSET).
+ * __pa(PAGE_OFFSET + TEXT_OFFSET).
  *
  * Note that the callee-saved registers are used for storing variables
  * that are useful before the MMU is enabled. The allocations are described
@@ -73,7 +73,7 @@ _head:
 	b	primary_entry			// branch to kernel start, magic
 	.long	0				// reserved
 #endif
-	.quad	0				// Image load offset from start of RAM, little-endian
+	le64sym	_kernel_offset_le		// Image load offset from start of RAM, little-endian
 	le64sym	_kernel_size_le			// Effective size of kernel image, little-endian
 	le64sym	_kernel_flags_le		// Informative flags, little-endian
 	.quad	0				// reserved
@@ -379,7 +379,7 @@ SYM_FUNC_START_LOCAL(__create_page_tables)
 	 * Map the kernel image (starting with PHYS_OFFSET).
 	 */
 	adrp	x0, init_pg_dir
-	mov_q	x5, KIMAGE_VADDR		// compile time __va(_text)
+	mov_q	x5, KIMAGE_VADDR + TEXT_OFFSET		// compile time __va(_text)
 	add	x5, x5, x23			// add KASLR displacement
 	mov	x4, PTRS_PER_PGD
 	adrp	x6, _end			// runtime __pa(_end)
@@ -471,7 +471,7 @@ SYM_FUNC_END(__primary_switched)
 
 	.pushsection ".rodata", "a"
 SYM_DATA_START(kimage_vaddr)
-	.quad		_text
+	.quad		_text - TEXT_OFFSET
 SYM_DATA_END(kimage_vaddr)
 EXPORT_SYMBOL(kimage_vaddr)
 	.popsection
diff --git a/arch/arm64/kernel/image.h b/arch/arm64/kernel/image.h
index 7bc3ba8979..c7d38c6603 100644
--- a/arch/arm64/kernel/image.h
+++ b/arch/arm64/kernel/image.h
@@ -62,6 +62,7 @@
  */
 #define HEAD_SYMBOLS						\
 	DEFINE_IMAGE_LE64(_kernel_size_le, _end - _text);	\
+	DEFINE_IMAGE_LE64(_kernel_offset_le, TEXT_OFFSET);	\
 	DEFINE_IMAGE_LE64(_kernel_flags_le, __HEAD_FLAGS);
 
 #endif /* __ARM64_KERNEL_IMAGE_H */
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index eb4b24652c..3dbfbac471 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -325,9 +325,6 @@ void __init __no_sanitize_address setup_arch(char **cmdline_p)
 	xen_early_init();
 	efi_init();
 
-	if (!efi_enabled(EFI_BOOT) && ((u64)_text % MIN_KIMG_ALIGN) != 0)
-	     pr_warn(FW_BUG "Kernel image misaligned at boot, please fix your bootloader!");
-
 	arm64_memblock_init();
 
 	paging_init();
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 44c6dece97..4b1b1b4ca9 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -116,7 +116,7 @@ SECTIONS
 		*(.ARM.attributes)
 	}
 
-	. = KIMAGE_VADDR;
+	. = KIMAGE_VADDR + TEXT_OFFSET;
 
 	.head.text : {
 		_text = .;
@@ -306,4 +306,4 @@ ASSERT((__entry_tramp_text_end - __entry_tramp_text_start) <= 3*PAGE_SIZE,
 /*
  * If padding is applied before .head.text, virt<->phys conversions will fail.
  */
-ASSERT(_text == KIMAGE_VADDR, "HEAD is misaligned")
+ASSERT(_text == (KIMAGE_VADDR + TEXT_OFFSET), "HEAD is misaligned")
diff --git a/drivers/firmware/efi/libstub/Makefile b/drivers/firmware/efi/libstub/Makefile
index d7bcfe0d50..fe0978778d 100644
--- a/drivers/firmware/efi/libstub/Makefile
+++ b/drivers/firmware/efi/libstub/Makefile
@@ -76,6 +76,7 @@ lib-$(CONFIG_ARM64)		+= arm64-stub.o
 lib-$(CONFIG_X86)		+= x86-stub.o
 lib-$(CONFIG_RISCV)		+= riscv-stub.o
 CFLAGS_arm32-stub.o		:= -DTEXT_OFFSET=$(TEXT_OFFSET)
+CFLAGS_arm64-stub.o		:= -DTEXT_OFFSET=$(TEXT_OFFSET)
 
 # Even when -mbranch-protection=none is set, Clang will generate a
 # .note.gnu.property for code-less object files (like lib/ctype.c),
diff --git a/drivers/firmware/efi/libstub/arm64-stub.c b/drivers/firmware/efi/libstub/arm64-stub.c
index 7f4bafcd9d..ac51ff5288 100644
--- a/drivers/firmware/efi/libstub/arm64-stub.c
+++ b/drivers/firmware/efi/libstub/arm64-stub.c
@@ -125,7 +125,7 @@ efi_status_t handle_kernel_image(unsigned long *image_addr,
 
 	kernel_size = _edata - _text;
 	kernel_memsize = kernel_size + (_end - _edata);
-	*reserve_size = kernel_memsize;
+	*reserve_size = kernel_memsize + TEXT_OFFSET % min_kimg_align;
 
 	if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && phys_seed != 0) {
 		/*
@@ -141,7 +141,7 @@ efi_status_t handle_kernel_image(unsigned long *image_addr,
 	if (status != EFI_SUCCESS) {
 		if (!check_image_region((u64)_text, kernel_memsize)) {
 			efi_err("FIRMWARE BUG: Image BSS overlaps adjacent EFI memory region\n");
-		} else if (IS_ALIGNED((u64)_text, min_kimg_align)) {
+		} else if (IS_ALIGNED((u64)_text - TEXT_OFFSET, min_kimg_align)) {
 			/*
 			 * Just execute from wherever we were loaded by the
 			 * UEFI PE/COFF loader if the alignment is suitable.
@@ -161,7 +161,7 @@ efi_status_t handle_kernel_image(unsigned long *image_addr,
 		}
 	}
 
-	*image_addr = *reserve_addr;
+	*image_addr = *reserve_addr + TEXT_OFFSET % min_kimg_align;
 	memcpy((void *)*image_addr, _text, kernel_size);
 
 	return EFI_SUCCESS;


================================================
FILE: kernel-patch/beta/deprecated-patches/5.10.y-201-wifi-add-ssv6051-driver.patch
================================================
From 9842560da0c5f333db86b9caeff9b6dfbede1022 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Thu, 6 Jan 2022 17:46:23 +0000
Subject: [PATCH] SSV6051 mainline kernel driver

---
 drivers/net/wireless/Kconfig                  |     1 +
 drivers/net/wireless/Makefile                 |     1 +
 drivers/net/wireless/ssv6051/Kconfig          |    11 +
 drivers/net/wireless/ssv6051/Makefile         |    26 +
 drivers/net/wireless/ssv6051/Makefile.bak     |   107 +
 .../ssv6051/firmware/ssv6051-wifi.cfg         |    91 +
 drivers/net/wireless/ssv6051/hci/hctrl.h      |   178 +
 drivers/net/wireless/ssv6051/hci/ssv_hci.c    |   967 +
 drivers/net/wireless/ssv6051/hci/ssv_hci.h    |    77 +
 drivers/net/wireless/ssv6051/hwif/hwif.h      |    84 +
 drivers/net/wireless/ssv6051/hwif/sdio/sdio.c |  1254 ++
 .../net/wireless/ssv6051/hwif/sdio/sdio_def.h |    80 +
 drivers/net/wireless/ssv6051/include/cabrio.h |    28 +
 .../net/wireless/ssv6051/include/ssv6200.h    |    76 +
 .../wireless/ssv6051/include/ssv6200_aux.h    | 18221 ++++++++++++++++
 .../wireless/ssv6051/include/ssv6200_common.h |   452 +
 .../ssv6051/include/ssv6200_configuration.h   |   317 +
 .../wireless/ssv6051/include/ssv6200_reg.h    |  9694 ++++++++
 .../ssv6051/include/ssv6200_reg_sim.h         |   176 +
 .../net/wireless/ssv6051/include/ssv_cfg.h    |    60 +
 .../ssv6051/include/ssv_firmware_version.h    |    25 +
 .../wireless/ssv6051/include/ssv_version.h    |    12 +
 .../net/wireless/ssv6051/platform-config.mak  |    93 +
 drivers/net/wireless/ssv6051/rules.mak        |    19 +
 drivers/net/wireless/ssv6051/smac/ampdu.c     |  2111 ++
 drivers/net/wireless/ssv6051/smac/ampdu.h     |   215 +
 drivers/net/wireless/ssv6051/smac/ap.c        |   598 +
 drivers/net/wireless/ssv6051/smac/ap.h        |    41 +
 drivers/net/wireless/ssv6051/smac/dev.c       |  3880 ++++
 drivers/net/wireless/ssv6051/smac/dev.h       |   445 +
 drivers/net/wireless/ssv6051/smac/dev_tbl.h   |   141 +
 drivers/net/wireless/ssv6051/smac/drv_comm.h  |    61 +
 drivers/net/wireless/ssv6051/smac/efuse.c     |   334 +
 drivers/net/wireless/ssv6051/smac/efuse.h     |    40 +
 drivers/net/wireless/ssv6051/smac/init.c      |  1347 ++
 drivers/net/wireless/ssv6051/smac/init.h      |    23 +
 drivers/net/wireless/ssv6051/smac/lib.c       |    33 +
 drivers/net/wireless/ssv6051/smac/lib.h       |    23 +
 .../net/wireless/ssv6051/smac/linux_80211.h   |    24 +
 drivers/net/wireless/ssv6051/smac/p2p.c       |   305 +
 drivers/net/wireless/ssv6051/smac/p2p.h       |    58 +
 drivers/net/wireless/ssv6051/smac/sar.c       |   208 +
 drivers/net/wireless/ssv6051/smac/sar.h       |    63 +
 drivers/net/wireless/ssv6051/smac/sec.h       |    52 +
 drivers/net/wireless/ssv6051/smac/smartlink.c |   340 +
 .../wireless/ssv6051/smac/ssv6xxx_debugfs.c   |   223 +
 .../wireless/ssv6051/smac/ssv6xxx_debugfs.h   |    27 +
 .../net/wireless/ssv6051/smac/ssv_cfgvendor.c |  1384 ++
 .../net/wireless/ssv6051/smac/ssv_cfgvendor.h |   247 +
 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c |   546 +
 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h |    31 +
 drivers/net/wireless/ssv6051/smac/ssv_pm.c    |    19 +
 drivers/net/wireless/ssv6051/smac/ssv_pm.h    |    20 +
 drivers/net/wireless/ssv6051/smac/ssv_rc.c    |  1716 ++
 drivers/net/wireless/ssv6051/smac/ssv_rc.h    |    50 +
 .../net/wireless/ssv6051/smac/ssv_rc_common.h |   175 +
 .../wireless/ssv6051/ssv6051-generic-wlan.c   |    76 +
 .../net/wireless/ssv6051/ssvdevice/ssv_cmd.c  |  1765 ++
 .../net/wireless/ssv6051/ssvdevice/ssv_cmd.h  |    50 +
 .../wireless/ssv6051/ssvdevice/ssvdevice.c    |   256 +
 60 files changed, 48977 insertions(+)
 create mode 100644 drivers/net/wireless/ssv6051/Kconfig
 create mode 100644 drivers/net/wireless/ssv6051/Makefile
 create mode 100644 drivers/net/wireless/ssv6051/Makefile.bak
 create mode 100644 drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
 create mode 100644 drivers/net/wireless/ssv6051/hci/hctrl.h
 create mode 100644 drivers/net/wireless/ssv6051/hci/ssv_hci.c
 create mode 100644 drivers/net/wireless/ssv6051/hci/ssv_hci.h
 create mode 100644 drivers/net/wireless/ssv6051/hwif/hwif.h
 create mode 100644 drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
 create mode 100644 drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
 create mode 100644 drivers/net/wireless/ssv6051/include/cabrio.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_aux.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_common.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_reg.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv_cfg.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv_version.h
 create mode 100644 drivers/net/wireless/ssv6051/platform-config.mak
 create mode 100644 drivers/net/wireless/ssv6051/rules.mak
 create mode 100644 drivers/net/wireless/ssv6051/smac/ampdu.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ampdu.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/ap.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ap.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/dev.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/dev.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/dev_tbl.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/drv_comm.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/efuse.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/efuse.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/init.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/init.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/lib.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/lib.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/linux_80211.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/p2p.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/p2p.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/sar.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/sar.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/sec.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/smartlink.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_pm.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_pm.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
 create mode 100644 drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
 create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
 create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
 create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c

diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
index 7add2002ff4..af63f332433 100644
--- a/drivers/net/wireless/Kconfig
+++ b/drivers/net/wireless/Kconfig
@@ -18,6 +18,7 @@ menuconfig WLAN
 
 if WLAN
 
+source "drivers/net/wireless/ssv6051/Kconfig"
 source "drivers/net/wireless/admtek/Kconfig"
 source "drivers/net/wireless/ath/Kconfig"
 source "drivers/net/wireless/atmel/Kconfig"
diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
index 80b32449978..e6440af4062 100644
--- a/drivers/net/wireless/Makefile
+++ b/drivers/net/wireless/Makefile
@@ -3,6 +3,7 @@
 # Makefile for the Linux Wireless network device drivers.
 #
 
+obj-$(CONFIG_SSV6051) += ssv6051/
 obj-$(CONFIG_WLAN_VENDOR_ADMTEK) += admtek/
 obj-$(CONFIG_WLAN_VENDOR_ATH) += ath/
 obj-$(CONFIG_WLAN_VENDOR_ATMEL) += atmel/
diff --git a/drivers/net/wireless/ssv6051/Kconfig b/drivers/net/wireless/ssv6051/Kconfig
new file mode 100644
index 00000000000..7706ad52ed7
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config SSV6051
+        tristate "South Silicon Valley (ssv) 6051 family WLAN support"
+	depends on MAC80211
+	depends on (MMC = y)
+        default n
+	select FW_LOADER
+        help
+		Enable South Silicon Valley (SSV) 6051 family support.
+
+
diff --git a/drivers/net/wireless/ssv6051/Makefile b/drivers/net/wireless/ssv6051/Makefile
new file mode 100644
index 00000000000..985d730f3d5
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/Makefile
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: ISC
+
+include $(src)/platform-config.mak
+
+ccflags-y += \
+	-I $(srctree)/$(src) \
+        -I $(srctree)/$(src)/include
+
+obj-$(CONFIG_SSV6051) += ssv6051.o
+ssv6051-objs += \
+	ssv6051-generic-wlan.o \
+	ssvdevice/ssvdevice.o \
+	ssvdevice/ssv_cmd.o \
+	hci/ssv_hci.o \
+	smac/init.o \
+	smac/dev.o \
+	smac/ssv_rc.o \
+	smac/ssv_ht_rc.o \
+	smac/ap.o \
+	smac/ampdu.o \
+	smac/efuse.o \
+	smac/ssv_pm.o \
+	smac/sar.o \
+	smac/ssv_cfgvendor.o \
+	hwif/sdio/sdio.o
+
diff --git a/drivers/net/wireless/ssv6051/Makefile.bak b/drivers/net/wireless/ssv6051/Makefile.bak
new file mode 100644
index 00000000000..2733fa4dd3b
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/Makefile.bak
@@ -0,0 +1,107 @@
+KMODULE_NAME=ssv6051
+
+KBUILD_TOP := $(PWD)
+
+ifeq ($(KERNELRELEASE),)
+
+KVERS_UNAME ?= $(shell uname -r)
+KVERS_ARCH ?= $(shell arch)
+
+KBUILD ?= $(shell readlink -f /lib/modules/$(KVERS_UNAME)/build)
+
+ifeq (,$(KBUILD))
+$(error kernel build tree not found - set KBUILD to configured kernel)
+endif
+
+#KCONFIG := $(KBUILD)/config
+#ifeq (,$(wildcard $(KCONFIG)))
+#$(error No .config found in $(KBUILD), set KBUILD to configured kernel)
+#endif
+
+ifneq (,$(wildcard $(KBUILD)/include/linux/version.h))
+ifneq (,$(wildcard $(KBUILD)/include/generated/uapi/linux/version.h))
+$(error Multiple copied of version.h found, clean build tree)
+endif
+endif
+
+# Kernel Makefile doesn't always know the exact kernel version, so we
+# get it from the kernel headers instead and pass it to make.
+VERSION_H := $(KBUILD)/include/generated/utsrelease.h
+ifeq (,$(wildcard $(VERSION_H)))
+VERSION_H := $(KBUILD)/include/linux/utsrelease.h
+endif
+ifeq (,$(wildcard $(VERSION_H)))
+VERSION_H := $(KBUILD)/include/linux/version.h
+endif
+ifeq (,$(wildcard $(VERSION_H)))
+$(error Please run 'make modules_prepare' in $(KBUILD))
+endif
+
+KVERS := $(shell sed -ne 's/"//g;s/^\#define UTS_RELEASE //p' $(VERSION_H))
+
+ifeq (,$(KVERS))
+$(error Cannot find UTS_RELEASE in $(VERSION_H), please report)
+endif
+
+INST_DIR = /lib/modules/$(KVERS)/misc
+
+#include $(KCONFIG)
+
+endif
+
+include $(KBUILD_TOP)/platform-config.mak
+
+EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include #-Wno-error=missing-attributes
+DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h
+
+OBJS := ssvdevice/ssvdevice.c \
+	ssvdevice/ssv_cmd.c \
+	hci/ssv_hci.c \
+	smac/init.c \
+	smac/dev.c \
+	smac/ssv_rc.c \
+	smac/ssv_ht_rc.c \
+	smac/ap.c \
+	smac/ampdu.c \
+	smac/efuse.c \
+	smac/ssv_pm.c \
+	smac/sar.c \
+	hwif/sdio/sdio.c \
+	ssv6051-generic-wlan.c
+
+ifeq ($(findstring -DCONFIG_SSV6XXX_DEBUGFS, $(ccflags-y)), -DCONFIG_SSV6XXX_DEBUGFS)
+OBJS +=	smac/ssv6xxx_debugfs.c
+endif
+
+ifeq ($(findstring -DCONFIG_SSV_VENDOR_EXT_SUPPORT, $(ccflags-y)), -DCONFIG_SSV_VENDOR_EXT_SUPPORT)
+OBJS +=	smac/ssv_cfgvendor.c
+endif
+
+ifeq ($(findstring -DCONFIG_SSV_SMARTLINK, $(ccflags-y)), -DCONFIG_SSV_SMARTLINK)
+OBJS += smac/smartlink.c
+endif
+
+$(KMODULE_NAME)-y += $(ASMS:.S=.o)
+$(KMODULE_NAME)-y += $(OBJS:.c=.o)
+
+obj-$(CONFIG_SSV6200_CORE) += $(KMODULE_NAME).o
+
+all: modules
+
+modules:
+	ARCH=arm $(MAKE) -C $(KBUILD) M=$(KBUILD_TOP)
+
+clean:
+	find -type f -iname '*.o' -exec rm {} \;
+	find -type f -iname '*.o.cmd' -exec rm {} \;
+	rm -f *.o *.ko .*.cmd *.mod.c *.symvers modules.order
+	rm -rf .tmp_versions
+
+install: modules
+	mkdir -p -m 755 $(DESTDIR)$(INST_DIR)
+	install -m 0644 $(KMODULE_NAME).ko $(DESTDIR)$(INST_DIR)
+ifndef DESTDIR
+	-/sbin/depmod -a $(KVERS)
+endif
+
+.PHONY: all modules clean install
diff --git a/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg b/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
new file mode 100644
index 00000000000..c072960f6de
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
@@ -0,0 +1,91 @@
+############################################################
+# ROCKCHIP RK3X28 & RK322X
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /vendor/etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+xtal_clock = 24
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ht = on
+hw_cap_gf = off
+hw_cap_2ghz = on
+hw_cap_5ghz = off
+hw_cap_security = on
+hw_cap_sgi_20 = on
+hw_cap_sgi_40 = off
+hw_cap_ap = on
+hw_cap_p2p = on
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+################################################
+# Signal strength control
+# rssi control
+#rssi_ctl = 10
+
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
diff --git a/drivers/net/wireless/ssv6051/hci/hctrl.h b/drivers/net/wireless/ssv6051/hci/hctrl.h
new file mode 100644
index 00000000000..95218c8040e
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hci/hctrl.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _HCTRL_H_
+#define _HCTRL_H_
+#define MAX_FRAME_SIZE 4096
+#define SSV6XXX_INT_RX 0x00000001
+#define SSV6XXX_INT_TX 0x00000002
+#define SSV6XXX_INT_SOC 0x00000004
+#define SSV6XXX_INT_LOW_EDCA_0 0x00000008
+#define SSV6XXX_INT_LOW_EDCA_1 0x00000010
+#define SSV6XXX_INT_LOW_EDCA_2 0x00000020
+#define SSV6XXX_INT_LOW_EDCA_3 0x00000040
+#define SSV6XXX_INT_RESOURCE_LOW 0x00000080
+#define IFDEV(_ct) ((_ct)->shi->dev)
+#define IFOPS(_ct) ((_ct)->shi->if_ops)
+#define HCI_REG_READ(_ct,_adr,_val) IFOPS(_ct)->readreg(IFDEV(_ct), _adr, _val)
+#define HCI_REG_WRITE(_ct,_adr,_val) IFOPS(_ct)->writereg(IFDEV(_ct), _adr, _val)
+#define HCI_REG_SET_BITS(_ct,_reg,_set,_clr) \
+{ \
+    u32 _regval; \
+    if(HCI_REG_READ(_ct, _reg, &_regval)); \
+    _regval &= ~(_clr); \
+    _regval |= (_set); \
+    if(HCI_REG_WRITE(_ct, _reg, _regval)); \
+}
+#define IF_SEND(_ct,_bf,_len,_qid) IFOPS(_ct)->write(IFDEV(_ct), _bf, _len, _qid)
+#define IF_RECV(ct,bf,len) IFOPS(ct)->read(IFDEV(ct), bf, len)
+#define HCI_LOAD_FW(ct,_bf,open) IFOPS(ct)->load_fw(IFDEV(ct), _bf, open)
+#define HCI_IFC_RESET(ct) IFOPS(ct)->interface_reset(IFDEV(ct))
+struct ssv6xxx_hci_ctrl {
+	struct ssv6xxx_hci_info *shi;
+	spinlock_t int_lock;
+	u32 int_status;
+	u32 int_mask;
+	struct mutex txq_mask_lock;
+	u32 txq_mask;
+	struct ssv_hw_txq hw_txq[SSV_HW_TXQ_NUM];
+	struct mutex hci_mutex;
+	bool hci_start;
+	struct sk_buff *rx_buf;
+	u32 rx_pkt;
+	struct workqueue_struct *hci_work_queue;
+	struct work_struct hci_rx_work;
+	struct work_struct hci_tx_work;
+	u32 read_rs0_info_fail;
+	u32 read_rs1_info_fail;
+	u32 rx_work_running;
+	u32 isr_running;
+	u32 xmit_running;
+	u32 isr_summary_eable;
+	u32 isr_routine_time;
+	u32 isr_tx_time;
+	u32 isr_rx_time;
+	u32 isr_idle_time;
+	u32 isr_rx_idle_time;
+	u32 isr_miss_cnt;
+	unsigned long prev_isr_jiffes;
+	unsigned long prev_rx_isr_jiffes;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct dentry *debugfs_dir;
+	u32 isr_mib_enable;
+	u32 isr_mib_reset;
+	long long isr_total_time;
+	long long isr_tx_io_time;
+	long long isr_rx_io_time;
+	u32 isr_rx_io_count;
+	u32 isr_tx_io_count;
+	long long isr_rx_proc_time;
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+	bool irq_enable;
+	u32 irq_count;
+	u32 invalid_irq_count;
+	u32 tx_irq_count;
+	u32 real_tx_irq_count;
+	u32 rx_irq_count;
+	u32 irq_rx_pkt_count;
+	u32 irq_tx_pkt_count;
+#endif
+#endif
+};
+struct ssv6xxx_hci_txq_info {
+	u32 tx_use_page:8;
+	u32 tx_use_id:6;
+	u32 txq0_size:4;
+	u32 txq1_size:4;
+	u32 txq2_size:5;
+	u32 txq3_size:5;
+};
+struct ssv6xxx_hci_txq_info2 {
+	u32 tx_use_page:9;
+	u32 tx_use_id:8;
+	u32 txq4_size:4;
+	u32 rsvd:11;
+};
+struct ssv6xxx_hw_resource {
+	u32 free_tx_page;
+	u32 free_tx_id;
+	int max_tx_frame[SSV_HW_TXQ_NUM];
+};
+static inline void ssv6xxx_hwif_irq_request(struct ssv6xxx_hci_ctrl *hctrl,
+					    irq_handler_t irq_handler)
+{
+	if (hctrl->shi->if_ops->irq_request)
+		hctrl->shi->if_ops->irq_request(IFDEV(hctrl), irq_handler,
+						hctrl);
+}
+
+static inline void ssv6xxx_hwif_irq_enable(struct ssv6xxx_hci_ctrl *hctrl)
+{
+	if (hctrl->shi->if_ops->irq_enable)
+		hctrl->shi->if_ops->irq_enable(IFDEV(hctrl));
+}
+
+static inline void ssv6xxx_hwif_irq_disable(struct ssv6xxx_hci_ctrl *hctrl)
+{
+	if (hctrl->shi->if_ops->irq_disable)
+		hctrl->shi->if_ops->irq_disable(IFDEV(hctrl), false);
+}
+
+static inline int ssv6xxx_hwif_irq_getstatus(struct ssv6xxx_hci_ctrl *hctrl,
+					     int *status)
+{
+	if (hctrl->shi->if_ops->irq_getstatus)
+		return hctrl->shi->if_ops->irq_getstatus(IFDEV(hctrl), status);
+	return 0;
+}
+
+static inline void ssv6xxx_hwif_irq_setmask(struct ssv6xxx_hci_ctrl *hctrl,
+					    int mask)
+{
+	if (hctrl->shi->if_ops->irq_setmask)
+		hctrl->shi->if_ops->irq_setmask(IFDEV(hctrl), mask);
+}
+
+static inline void ssv6xxx_hwif_irq_trigger(struct ssv6xxx_hci_ctrl *hctrl)
+{
+	if (hctrl->shi->if_ops->irq_trigger)
+		hctrl->shi->if_ops->irq_trigger(IFDEV(hctrl));
+}
+
+static inline void ssv6xxx_hwif_pmu_wakeup(struct ssv6xxx_hci_ctrl *hctrl)
+{
+	if (hctrl->shi->if_ops->pmu_wakeup)
+		hctrl->shi->if_ops->pmu_wakeup(IFDEV(hctrl));
+}
+
+static inline int ssv6xxx_hwif_write_sram(struct ssv6xxx_hci_ctrl *hctrl,
+					  u32 addr, u8 * data, u32 size)
+{
+	if (hctrl->shi->if_ops->write_sram)
+		return hctrl->shi->if_ops->write_sram(IFDEV(hctrl), addr, data,
+						      size);
+	return 0;
+}
+
+#define HCI_IRQ_REQUEST(ct,hdle) ssv6xxx_hwif_irq_request(ct, hdle)
+#define HCI_IRQ_ENABLE(ct) ssv6xxx_hwif_irq_enable(ct)
+#define HCI_IRQ_DISABLE(ct) ssv6xxx_hwif_irq_disable(ct)
+#define HCI_IRQ_STATUS(ct,sts) ssv6xxx_hwif_irq_getstatus(ct, sts)
+#define HCI_IRQ_SET_MASK(ct,mk) ssv6xxx_hwif_irq_setmask(ct, mk)
+#define HCI_IRQ_TRIGGER(ct) ssv6xxx_hwif_irq_trigger(ct)
+#define HCI_PMU_WAKEUP(ct) ssv6xxx_hwif_pmu_wakeup(ct)
+#define HCI_SRAM_WRITE(_ct,_adr,_dat,_size) ssv6xxx_hwif_write_sram(_ct, _adr, _dat, _size);
+#endif
diff --git a/drivers/net/wireless/ssv6051/hci/ssv_hci.c b/drivers/net/wireless/ssv6051/hci/ssv_hci.c
new file mode 100644
index 00000000000..9fedbeb5575
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hci/ssv_hci.c
@@ -0,0 +1,967 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/jiffies.h>
+#include <ssv6200.h>
+#include "hctrl.h"
+
+static struct ssv6xxx_hci_ctrl *ctrl_hci = NULL;
+
+struct sk_buff *ssv_skb_alloc(s32 len)
+{
+	struct sk_buff *skb;
+	skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL);
+	if (skb != NULL) {
+		skb_reserve(skb, SSV_SKB_info_size);
+	}
+	return skb;
+}
+
+void ssv_skb_free(struct sk_buff *skb)
+{
+	dev_kfree_skb_any(skb);
+}
+
+static int ssv6xxx_hci_irq_enable(void)
+{
+	HCI_IRQ_SET_MASK(ctrl_hci, ~(ctrl_hci->int_mask));
+	HCI_IRQ_ENABLE(ctrl_hci);
+	return 0;
+}
+
+static int ssv6xxx_hci_irq_disable(void)
+{
+	HCI_IRQ_SET_MASK(ctrl_hci, 0xffffffff);
+	HCI_IRQ_DISABLE(ctrl_hci);
+	return 0;
+}
+
+static void ssv6xxx_hci_irq_register(u32 irq_mask)
+{
+	unsigned long flags;
+	u32 regval;
+	mutex_lock(&ctrl_hci->hci_mutex);
+	spin_lock_irqsave(&ctrl_hci->int_lock, flags);
+	ctrl_hci->int_mask |= irq_mask;
+	regval = ~ctrl_hci->int_mask;
+	spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+	smp_mb();
+	HCI_IRQ_SET_MASK(ctrl_hci, regval);
+	mutex_unlock(&ctrl_hci->hci_mutex);
+}
+
+static inline u32 ssv6xxx_hci_get_int_bitno(int txqid)
+{
+	if (txqid == SSV_HW_TXQ_NUM - 1)
+		return 1;
+	else
+		return txqid + 3;
+}
+
+static int ssv6xxx_hci_start(void)
+{
+	ssv6xxx_hci_irq_enable();
+	ctrl_hci->hci_start = true;
+	HCI_IRQ_TRIGGER(ctrl_hci);
+	return 0;
+}
+
+static int ssv6xxx_hci_stop(void)
+{
+	ssv6xxx_hci_irq_disable();
+	ctrl_hci->hci_start = false;
+	return 0;
+}
+
+static int ssv6xxx_hci_read_word(u32 addr, u32 * regval)
+{
+	int ret = HCI_REG_READ(ctrl_hci, addr, regval);
+	return ret;
+}
+
+static int ssv6xxx_hci_write_word(u32 addr, u32 regval)
+{
+	return HCI_REG_WRITE(ctrl_hci, addr, regval);
+}
+
+static int ssv6xxx_hci_load_fw(u8 * firmware_name, u8 openfile)
+{
+	return HCI_LOAD_FW(ctrl_hci, firmware_name, openfile);
+}
+
+static int ssv6xxx_hci_write_sram(u32 addr, u8 * data, u32 size)
+{
+	return HCI_SRAM_WRITE(ctrl_hci, addr, data, size);
+}
+
+static int ssv6xxx_hci_pmu_wakeup(void)
+{
+	HCI_PMU_WAKEUP(ctrl_hci);
+	return 0;
+}
+
+static int ssv6xxx_hci_interface_reset(void)
+{
+	HCI_IFC_RESET(ctrl_hci);
+	return 0;
+}
+
+static int ssv6xxx_hci_send_cmd(struct sk_buff *skb)
+{
+	int ret;
+	ret = IF_SEND(ctrl_hci, (void *)skb->data, skb->len, 0);
+
+	if (ret < 0)
+		pr_warn("ssv6xxx_hci_send_cmd failed, ret=%d\n", ret);
+
+	return ret;
+}
+
+static int ssv6xxx_hci_enqueue(struct sk_buff *skb, int txqid, u32 tx_flags)
+{
+	struct ssv_hw_txq *hw_txq;
+	unsigned long flags;
+	u32 status;
+	int qlen = 0;
+	BUG_ON(txqid >= SSV_HW_TXQ_NUM || txqid < 0);
+	if (txqid >= SSV_HW_TXQ_NUM || txqid < 0)
+		return -1;
+	hw_txq = &ctrl_hci->hw_txq[txqid];
+	hw_txq->tx_flags = tx_flags;
+	if (tx_flags & HCI_FLAGS_ENQUEUE_HEAD)
+		skb_queue_head(&hw_txq->qhead, skb);
+	else
+		skb_queue_tail(&hw_txq->qhead, skb);
+	qlen = (int)skb_queue_len(&hw_txq->qhead);
+	if (!(tx_flags & HCI_FLAGS_NO_FLOWCTRL)) {
+		if (skb_queue_len(&hw_txq->qhead) >= hw_txq->max_qsize) {
+			ctrl_hci->shi->hci_tx_flow_ctrl_cb(ctrl_hci->
+							   shi->tx_fctrl_cb_args,
+							   hw_txq->txq_no, true,
+							   2000);
+		}
+	}
+
+	mutex_lock(&ctrl_hci->hci_mutex);
+	spin_lock_irqsave(&ctrl_hci->int_lock, flags);
+	status = ctrl_hci->int_mask;
+
+	if ((ctrl_hci->int_mask & SSV6XXX_INT_RESOURCE_LOW) == 0) {
+		if (ctrl_hci->shi->if_ops->trigger_tx_rx == NULL) {
+			u32 regval;
+			ctrl_hci->int_mask |= SSV6XXX_INT_RESOURCE_LOW;
+			regval = ~ctrl_hci->int_mask;
+			spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+			HCI_IRQ_SET_MASK(ctrl_hci, regval);
+			mutex_unlock(&ctrl_hci->hci_mutex);
+		} else {
+			ctrl_hci->int_status |= SSV6XXX_INT_RESOURCE_LOW;
+			smp_mb();
+			spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+			mutex_unlock(&ctrl_hci->hci_mutex);
+			ctrl_hci->shi->if_ops->trigger_tx_rx(ctrl_hci->
+							     shi->dev);
+		}
+	} else {
+		spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+		mutex_unlock(&ctrl_hci->hci_mutex);
+	}
+
+	return qlen;
+}
+
+static bool ssv6xxx_hci_is_txq_empty(int txqid)
+{
+	struct ssv_hw_txq *hw_txq;
+	BUG_ON(txqid >= SSV_HW_TXQ_NUM);
+	if (txqid >= SSV_HW_TXQ_NUM)
+		return false;
+	hw_txq = &ctrl_hci->hw_txq[txqid];
+	if (skb_queue_len(&hw_txq->qhead) <= 0)
+		return true;
+	return false;
+}
+
+static int ssv6xxx_hci_txq_flush(u32 txq_mask)
+{
+	struct ssv_hw_txq *hw_txq;
+	struct sk_buff *skb = NULL;
+	int txqid;
+	for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
+		if ((txq_mask & (1 << txqid)) != 0)
+			continue;
+		hw_txq = &ctrl_hci->hw_txq[txqid];
+		while ((skb = skb_dequeue(&hw_txq->qhead))) {
+			ctrl_hci->shi->hci_tx_buf_free_cb(skb,
+							  ctrl_hci->
+							  shi->tx_buf_free_args);
+		}
+	}
+	return 0;
+}
+
+static int ssv6xxx_hci_txq_flush_by_sta(int aid)
+{
+	return 0;
+}
+
+static int ssv6xxx_hci_txq_pause(u32 txq_mask)
+{
+	struct ssv_hw_txq *hw_txq;
+	int txqid;
+	mutex_lock(&ctrl_hci->txq_mask_lock);
+	ctrl_hci->txq_mask |= (txq_mask & 0x1F);
+	for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
+		if ((ctrl_hci->txq_mask & (1 << txqid)) == 0)
+			continue;
+		hw_txq = &ctrl_hci->hw_txq[txqid];
+		hw_txq->paused = true;
+	}
+	HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN,
+			 (ctrl_hci->txq_mask << 16), (0x1F << 16));
+	mutex_unlock(&ctrl_hci->txq_mask_lock);
+	return 0;
+}
+
+static int ssv6xxx_hci_txq_resume(u32 txq_mask)
+{
+	struct ssv_hw_txq *hw_txq;
+	int txqid;
+	mutex_lock(&ctrl_hci->txq_mask_lock);
+	ctrl_hci->txq_mask &= ~(txq_mask & 0x1F);
+	for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
+		if ((ctrl_hci->txq_mask & (1 << txqid)) != 0)
+			continue;
+		hw_txq = &ctrl_hci->hw_txq[txqid];
+		hw_txq->paused = false;
+	}
+	HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN,
+			 (ctrl_hci->txq_mask << 16), (0x1F << 16));
+	mutex_unlock(&ctrl_hci->txq_mask_lock);
+	return 0;
+}
+
+static int ssv6xxx_hci_xmit(struct ssv_hw_txq *hw_txq, int max_count,
+			    struct ssv6xxx_hw_resource *phw_resource)
+{
+	struct sk_buff_head tx_cb_list;
+	struct sk_buff *skb = NULL;
+	int tx_count, ret, page_count;
+	struct ssv6200_tx_desc *tx_desc = NULL;
+	ctrl_hci->xmit_running = 1;
+	skb_queue_head_init(&tx_cb_list);
+	for (tx_count = 0; tx_count < max_count; tx_count++) {
+		if (ctrl_hci->hci_start == false) {
+			pr_debug("ssv6xxx_hci_xmit - hci_start = false\n");
+			goto xmit_out;
+		}
+		skb = skb_dequeue(&hw_txq->qhead);
+		if (!skb) {
+			pr_debug("ssv6xxx_hci_xmit - queue empty\n");
+			goto xmit_out;
+		}
+		page_count = (skb->len + SSV6200_ALLOC_RSVD);
+		if (page_count & HW_MMU_PAGE_MASK)
+			page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
+		else
+			page_count = page_count >> HW_MMU_PAGE_SHIFT;
+		if (page_count > (SSV6200_PAGE_TX_THRESHOLD / 2))
+			pr_err("Asking page %d(%d) exceeds resource limit %d.\n",
+			       page_count, skb->len,
+			       (SSV6200_PAGE_TX_THRESHOLD / 2));
+		if ((phw_resource->free_tx_page < page_count)
+		    || (phw_resource->free_tx_id <= 0)
+		    || (phw_resource->max_tx_frame[hw_txq->txq_no] <= 0)) {
+			skb_queue_head(&hw_txq->qhead, skb);
+			break;
+		}
+		phw_resource->free_tx_page -= page_count;
+		phw_resource->free_tx_id--;
+		phw_resource->max_tx_frame[hw_txq->txq_no]--;
+		tx_desc = (struct ssv6200_tx_desc *)skb->data;
+
+		if (ctrl_hci->shi->hci_skb_update_cb != NULL
+		    && tx_desc->reason != ID_TRAP_SW_TXTPUT) {
+			ctrl_hci->shi->hci_skb_update_cb(skb,
+							 ctrl_hci->
+							 shi->skb_update_args);
+		}
+
+		ret =
+		    IF_SEND(ctrl_hci, (void *)skb->data, skb->len,
+			    hw_txq->txq_no);
+		if (ret < 0) {
+			pr_err("ssv6xxx_hci_xmit failure\n");
+			skb_queue_head(&hw_txq->qhead, skb);
+			break;
+		}
+		if (tx_desc->reason != ID_TRAP_SW_TXTPUT)
+			skb_queue_tail(&tx_cb_list, skb);
+		else
+			ssv_skb_free(skb);
+		hw_txq->tx_pkt++;
+
+		if (!(hw_txq->tx_flags & HCI_FLAGS_NO_FLOWCTRL)) {
+			if (skb_queue_len(&hw_txq->qhead) < hw_txq->resum_thres) {
+				ctrl_hci->shi->
+				    hci_tx_flow_ctrl_cb
+				    (ctrl_hci->shi->tx_fctrl_cb_args,
+				     hw_txq->txq_no, false, 2000);
+			}
+		}
+	}
+ xmit_out:
+	if (ctrl_hci->shi->hci_tx_cb && tx_desc
+	    && tx_desc->reason != ID_TRAP_SW_TXTPUT) {
+		ctrl_hci->shi->hci_tx_cb(&tx_cb_list,
+					 ctrl_hci->shi->tx_cb_args);
+	}
+	ctrl_hci->xmit_running = 0;
+	return tx_count;
+}
+
+static int ssv6xxx_hci_tx_handler(void *dev, int max_count)
+{
+	struct ssv6xxx_hci_txq_info txq_info;
+	struct ssv6xxx_hci_txq_info2 txq_info2;
+	struct ssv6xxx_hw_resource hw_resource;
+	struct ssv_hw_txq *hw_txq = dev;
+	int ret, tx_count = 0;
+	max_count = skb_queue_len(&hw_txq->qhead);
+	if (max_count == 0)
+		return 0;
+	if (hw_txq->txq_no == 4) {
+		ret =
+		    HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO2,
+				 (u32 *) & txq_info2);
+		if (ret < 0) {
+			ctrl_hci->read_rs1_info_fail++;
+			return 0;
+		}
+		//BUG_ON(SSV6200_PAGE_TX_THRESHOLD < txq_info2.tx_use_page);
+		//BUG_ON(SSV6200_ID_TX_THRESHOLD < txq_info2.tx_use_id);
+		if (SSV6200_PAGE_TX_THRESHOLD < txq_info2.tx_use_page)
+			return 0;
+		if (SSV6200_ID_TX_THRESHOLD < txq_info2.tx_use_page)
+			return 0;
+		hw_resource.free_tx_page =
+		    SSV6200_PAGE_TX_THRESHOLD - txq_info2.tx_use_page;
+		hw_resource.free_tx_id =
+		    SSV6200_ID_TX_THRESHOLD - txq_info2.tx_use_id;
+		hw_resource.max_tx_frame[4] =
+		    SSV6200_ID_MANAGER_QUEUE - txq_info2.txq4_size;
+	} else {
+		ret =
+		    HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO,
+				 (u32 *) & txq_info);
+		if (ret < 0) {
+			ctrl_hci->read_rs0_info_fail++;
+			return 0;
+		}
+		//BUG_ON(SSV6200_PAGE_TX_THRESHOLD < txq_info.tx_use_page);
+		//BUG_ON(SSV6200_ID_TX_THRESHOLD < txq_info.tx_use_id);
+		if (SSV6200_PAGE_TX_THRESHOLD < txq_info.tx_use_page)
+			return 0;
+		if (SSV6200_ID_TX_THRESHOLD < txq_info.tx_use_page)
+			return 0;
+		hw_resource.free_tx_page =
+		    SSV6200_PAGE_TX_THRESHOLD - txq_info.tx_use_page;
+		hw_resource.free_tx_id =
+		    SSV6200_ID_TX_THRESHOLD - txq_info.tx_use_id;
+		hw_resource.max_tx_frame[0] =
+		    SSV6200_ID_AC_BK_OUT_QUEUE - txq_info.txq0_size;
+		hw_resource.max_tx_frame[1] =
+		    SSV6200_ID_AC_BE_OUT_QUEUE - txq_info.txq1_size;
+		hw_resource.max_tx_frame[2] =
+		    SSV6200_ID_AC_VI_OUT_QUEUE - txq_info.txq2_size;
+		hw_resource.max_tx_frame[3] =
+		    SSV6200_ID_AC_VO_OUT_QUEUE - txq_info.txq3_size;
+		BUG_ON(hw_resource.max_tx_frame[3] < 0);
+		BUG_ON(hw_resource.max_tx_frame[2] < 0);
+		BUG_ON(hw_resource.max_tx_frame[1] < 0);
+		BUG_ON(hw_resource.max_tx_frame[0] < 0);
+	}
+	{
+		tx_count = ssv6xxx_hci_xmit(hw_txq, max_count, &hw_resource);
+	}
+	if ((ctrl_hci->shi->hci_tx_q_empty_cb != NULL)
+	    && (skb_queue_len(&hw_txq->qhead) == 0)) {
+		ctrl_hci->shi->hci_tx_q_empty_cb(hw_txq->txq_no,
+						 ctrl_hci->
+						 shi->tx_q_empty_args);
+	}
+	return tx_count;
+}
+
+void ssv6xxx_hci_tx_work(struct work_struct *work)
+{
+	ssv6xxx_hci_irq_register(SSV6XXX_INT_RESOURCE_LOW);
+}
+
+static int _do_rx(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
+{
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+	struct sk_buff_head rx_list;
+#endif
+	struct sk_buff *rx_mpdu;
+	int rx_cnt, ret = 0;
+	size_t dlen;
+	u32 status = isr_status;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
+	struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+	skb_queue_head_init(&rx_list);
+#endif
+	for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32); rx_cnt++) {
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (hctl->isr_mib_enable)
+			getnstimeofday(&rx_io_start_time);
+#endif
+		ret = IF_RECV(hctl, hctl->rx_buf->data, &dlen);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (hctl->isr_mib_enable)
+			getnstimeofday(&rx_io_end_time);
+#endif
+		if (ret < 0 || dlen <= 0) {
+			pr_warn("%s(): IF_RECV() retruns %d (dlen=%d)\n",
+			       __FUNCTION__, ret, (int)dlen);
+			if (ret != -84 || dlen > MAX_FRAME_SIZE)
+				break;
+		}
+		rx_mpdu = hctl->rx_buf;
+		hctl->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
+		if (hctl->rx_buf == NULL) {
+			pr_err("RX buffer allocation failure!\n");
+			hctl->rx_buf = rx_mpdu;
+			break;
+		}
+		hctl->rx_pkt++;
+		skb_put(rx_mpdu, dlen);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (hctl->isr_mib_enable)
+			getnstimeofday(&rx_proc_start_time);
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+		__skb_queue_tail(&rx_list, rx_mpdu);
+#else
+		hctl->shi->hci_rx_cb(rx_mpdu, hctl->shi->rx_cb_args);
+#endif
+		HCI_IRQ_STATUS(hctl, &status);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (hctl->isr_mib_enable) {
+			getnstimeofday(&rx_proc_end_time);
+			hctl->isr_rx_io_count++;
+			rx_io_diff_time =
+			    timespec_sub(rx_io_end_time, rx_io_start_time);
+			hctl->isr_rx_io_time +=
+			    timespec_to_ns(&rx_io_diff_time);
+			rx_proc_diff_time =
+			    timespec_sub(rx_proc_end_time, rx_proc_start_time);
+			hctl->isr_rx_proc_time +=
+			    timespec_to_ns(&rx_proc_diff_time);
+		}
+#endif
+	}
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	if (hctl->isr_mib_enable)
+		getnstimeofday(&rx_proc_start_time);
+#endif
+	hctl->shi->hci_rx_cb(&rx_list, hctl->shi->rx_cb_args);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	if (hctl->isr_mib_enable) {
+		getnstimeofday(&rx_proc_end_time);
+		rx_proc_diff_time =
+		    timespec_sub(rx_proc_end_time, rx_proc_start_time);
+		hctl->isr_rx_proc_time += timespec_to_ns(&rx_proc_diff_time);
+	}
+#endif
+#endif
+	return ret;
+}
+
+static void ssv6xxx_hci_rx_work(struct work_struct *work)
+{
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+	struct sk_buff_head rx_list;
+#endif
+	struct sk_buff *rx_mpdu;
+	int rx_cnt, ret;
+	size_t dlen;
+	u32 status;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
+	struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
+#endif
+	ctrl_hci->rx_work_running = 1;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+	skb_queue_head_init(&rx_list);
+#endif
+	status = SSV6XXX_INT_RX;
+	for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32); rx_cnt++) {
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (ctrl_hci->isr_mib_enable)
+			getnstimeofday(&rx_io_start_time);
+#endif
+		ret = IF_RECV(ctrl_hci, ctrl_hci->rx_buf->data, &dlen);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (ctrl_hci->isr_mib_enable)
+			getnstimeofday(&rx_io_end_time);
+#endif
+		if (ret < 0 || dlen <= 0) {
+			pr_warn("%s(): IF_RECV() retruns %d (dlen=%d)\n",
+			       __FUNCTION__, ret, (int)dlen);
+			if (ret != -84 || dlen > MAX_FRAME_SIZE)
+				break;
+		}
+		rx_mpdu = ctrl_hci->rx_buf;
+		ctrl_hci->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
+		if (ctrl_hci->rx_buf == NULL) {
+			pr_err("RX buffer allocation failure!\n");
+			ctrl_hci->rx_buf = rx_mpdu;
+			break;
+		}
+		ctrl_hci->rx_pkt++;
+		skb_put(rx_mpdu, dlen);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (ctrl_hci->isr_mib_enable)
+			getnstimeofday(&rx_proc_start_time);
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+		__skb_queue_tail(&rx_list, rx_mpdu);
+#else
+		ctrl_hci->shi->hci_rx_cb(rx_mpdu, ctrl_hci->shi->rx_cb_args);
+#endif
+		HCI_IRQ_STATUS(ctrl_hci, &status);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (ctrl_hci->isr_mib_enable) {
+			getnstimeofday(&rx_proc_end_time);
+			ctrl_hci->isr_rx_io_count++;
+			rx_io_diff_time =
+			    timespec_sub(rx_io_end_time, rx_io_start_time);
+			ctrl_hci->isr_rx_io_time +=
+			    timespec_to_ns(&rx_io_diff_time);
+			rx_proc_diff_time =
+			    timespec_sub(rx_proc_end_time, rx_proc_start_time);
+			ctrl_hci->isr_rx_proc_time +=
+			    timespec_to_ns(&rx_proc_diff_time);
+		}
+#endif
+	}
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	if (ctrl_hci->isr_mib_enable)
+		getnstimeofday(&rx_proc_start_time);
+#endif
+	ctrl_hci->shi->hci_rx_cb(&rx_list, ctrl_hci->shi->rx_cb_args);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	if (ctrl_hci->isr_mib_enable) {
+		getnstimeofday(&rx_proc_end_time);
+		rx_proc_diff_time =
+		    timespec_sub(rx_proc_end_time, rx_proc_start_time);
+		ctrl_hci->isr_rx_proc_time +=
+		    timespec_to_ns(&rx_proc_diff_time);
+	}
+#endif
+#endif
+	ctrl_hci->rx_work_running = 0;
+}
+
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+static void ssv6xxx_isr_mib_reset(void)
+{
+	ctrl_hci->isr_mib_reset = 0;
+	ctrl_hci->isr_total_time = 0;
+	ctrl_hci->isr_rx_io_time = 0;
+	ctrl_hci->isr_tx_io_time = 0;
+	ctrl_hci->isr_rx_io_count = 0;
+	ctrl_hci->isr_tx_io_count = 0;
+	ctrl_hci->isr_rx_proc_time = 0;
+}
+
+static int hw_txq_len_open(struct inode *inode, struct file *filp)
+{
+	filp->private_data = inode->i_private;
+	return 0;
+}
+
+static ssize_t hw_txq_len_read(struct file *filp, char __user * buffer,
+			       size_t count, loff_t * ppos)
+{
+	ssize_t ret;
+	struct ssv6xxx_hci_ctrl *hctl =
+	    (struct ssv6xxx_hci_ctrl *)filp->private_data;
+	char *summary_buf = kzalloc(1024, GFP_KERNEL);
+	char *prn_ptr = summary_buf;
+	int prt_size;
+	int buf_size = 1024;
+	int i = 0;
+	if (!summary_buf)
+		return -ENOMEM;
+	for (i = 0; i < SSV_HW_TXQ_NUM; i++) {
+		prt_size =
+		    snprintf(prn_ptr, buf_size, "\n\rhw_txq%d_len: %d", i,
+			     skb_queue_len(&hctl->hw_txq[i].qhead));
+		prn_ptr += prt_size;
+		buf_size -= prt_size;
+	}
+	buf_size = 1024 - buf_size;
+	ret =
+	    simple_read_from_buffer(buffer, count, ppos, summary_buf, buf_size);
+	kfree(summary_buf);
+	return ret;
+}
+
+struct file_operations hw_txq_len_fops = {
+	.owner = THIS_MODULE,
+	.open = hw_txq_len_open,
+	.read = hw_txq_len_read,
+};
+
+bool ssv6xxx_hci_init_debugfs(struct dentry *dev_deugfs_dir)
+{
+	ctrl_hci->debugfs_dir = debugfs_create_dir("hci", dev_deugfs_dir);
+	if (ctrl_hci->debugfs_dir == NULL) {
+		dev_err(ctrl_hci->shi->dev,
+			"Failed to create HCI debugfs directory.\n");
+		return false;
+	}
+	debugfs_create_u32("TXQ_mask", 00444, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->txq_mask);
+	debugfs_create_u32("hci_isr_mib_enable", 00644, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_mib_enable);
+	debugfs_create_u32("hci_isr_mib_reset", 00644, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_mib_reset);
+	debugfs_create_u64("isr_total_time", 00444, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_total_time);
+	debugfs_create_u64("tx_io_time", 00444, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_tx_io_time);
+	debugfs_create_u64("rx_io_time", 00444, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_rx_io_time);
+	debugfs_create_u32("tx_io_count", 00444, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_tx_io_count);
+	debugfs_create_u32("rx_io_count", 00444, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_rx_io_count);
+	debugfs_create_u64("rx_proc_time", 00444, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_rx_proc_time);
+	debugfs_create_file("hw_txq_len", 00444, ctrl_hci->debugfs_dir,
+			    ctrl_hci, &hw_txq_len_fops);
+	return true;
+}
+
+void ssv6xxx_hci_deinit_debugfs(void)
+{
+	if (ctrl_hci->debugfs_dir == NULL)
+		return;
+	ctrl_hci->debugfs_dir = NULL;
+}
+#endif
+static int _isr_do_rx(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
+{
+	int status;
+	u32 before = jiffies;
+
+	if (hctl->isr_summary_eable && hctl->prev_rx_isr_jiffes) {
+		if (hctl->isr_rx_idle_time) {
+			hctl->isr_rx_idle_time +=
+			    (jiffies - hctl->prev_rx_isr_jiffes);
+			hctl->isr_rx_idle_time = hctl->isr_rx_idle_time >> 1;
+		} else {
+			hctl->isr_rx_idle_time +=
+			    (jiffies - hctl->prev_rx_isr_jiffes);
+		}
+	}
+	status = _do_rx(hctl, isr_status);
+	if (hctl->isr_summary_eable) {
+		if (hctl->isr_rx_time) {
+			hctl->isr_rx_time += (jiffies - before);
+			hctl->isr_rx_time = hctl->isr_rx_time >> 1;
+		} else {
+			hctl->isr_rx_time += (jiffies - before);
+		}
+		hctl->prev_rx_isr_jiffes = jiffies;
+	}
+	return status;
+}
+
+static int _do_tx(struct ssv6xxx_hci_ctrl *hctl, u32 status)
+{
+	int q_num;
+	int tx_count = 0;
+	u32 to_disable_int = 1;
+	unsigned long flags;
+	struct ssv_hw_txq *hw_txq;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct timespec tx_io_start_time, tx_io_end_time, tx_io_diff_time;
+#endif
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+	if ((!(status & SSV6XXX_INT_RX)) && htcl->irq_enable)
+		hctl->tx_irq_count++;
+#endif
+	if ((status & SSV6XXX_INT_RESOURCE_LOW) == 0)
+		return 0;
+	for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
+		u32 before = jiffies;
+		hw_txq = &hctl->hw_txq[q_num];
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (hctl->isr_mib_enable)
+			getnstimeofday(&tx_io_start_time);
+#endif
+		tx_count += ssv6xxx_hci_tx_handler(hw_txq, 999);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (hctl->isr_mib_enable) {
+			getnstimeofday(&tx_io_end_time);
+			tx_io_diff_time =
+			    timespec_sub(tx_io_end_time, tx_io_start_time);
+			hctl->isr_tx_io_time +=
+			    timespec_to_ns(&tx_io_diff_time);
+		}
+#endif
+		if (hctl->isr_summary_eable) {
+			if (hctl->isr_tx_time) {
+				hctl->isr_tx_time += (jiffies - before);
+				hctl->isr_tx_time = hctl->isr_tx_time >> 1;
+			} else {
+				hctl->isr_tx_time += (jiffies - before);
+			}
+		}
+	}
+	mutex_lock(&hctl->hci_mutex);
+	spin_lock_irqsave(&hctl->int_lock, flags);
+	for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
+		hw_txq = &hctl->hw_txq[q_num];
+		if (skb_queue_len(&hw_txq->qhead) > 0) {
+			to_disable_int = 0;
+			break;
+		}
+	}
+	if (to_disable_int) {
+		u32 reg_val;
+		hctl->int_mask &= ~(SSV6XXX_INT_RESOURCE_LOW | SSV6XXX_INT_TX);
+		reg_val = ~hctl->int_mask;
+		spin_unlock_irqrestore(&hctl->int_lock, flags);
+		HCI_IRQ_SET_MASK(hctl, reg_val);
+	} else {
+		spin_unlock_irqrestore(&hctl->int_lock, flags);
+	}
+	mutex_unlock(&hctl->hci_mutex);
+	return tx_count;
+}
+
+irqreturn_t ssv6xxx_hci_isr(int irq, void *args)
+{
+	struct ssv6xxx_hci_ctrl *hctl = args;
+	u32 status;
+	unsigned long flags;
+	int ret = IRQ_HANDLED;
+	bool dbg_isr_miss = true;
+	if (ctrl_hci->isr_summary_eable && ctrl_hci->prev_isr_jiffes) {
+		if (ctrl_hci->isr_idle_time) {
+			ctrl_hci->isr_idle_time +=
+			    (jiffies - ctrl_hci->prev_isr_jiffes);
+			ctrl_hci->isr_idle_time = ctrl_hci->isr_idle_time >> 1;
+		} else {
+			ctrl_hci->isr_idle_time +=
+			    (jiffies - ctrl_hci->prev_isr_jiffes);
+		}
+	}
+	BUG_ON(!args);
+	do {
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		struct timespec start_time, end_time, diff_time;
+		if (hctl->isr_mib_reset)
+			ssv6xxx_isr_mib_reset();
+		if (hctl->isr_mib_enable)
+			getnstimeofday(&start_time);
+#endif
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+		if (ctrl_hci->irq_enable)
+			ctrl_hci->irq_count++;
+#endif
+		mutex_lock(&hctl->hci_mutex);
+		if (hctl->int_status) {
+			u32 regval;
+			spin_lock_irqsave(&hctl->int_lock, flags);
+			hctl->int_mask |= hctl->int_status;
+			hctl->int_status = 0;
+			regval = ~ctrl_hci->int_mask;
+			smp_mb();
+			spin_unlock_irqrestore(&hctl->int_lock, flags);
+			HCI_IRQ_SET_MASK(hctl, regval);
+		}
+		ret = HCI_IRQ_STATUS(hctl, &status);
+		if ((ret < 0) || ((status & hctl->int_mask) == 0)) {
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+			if (ctrl_hci->irq_enable)
+				ctrl_hci->invalid_irq_count++;
+#endif
+			mutex_unlock(&hctl->hci_mutex);
+			ret = IRQ_NONE;
+			break;
+		}
+		spin_lock_irqsave(&hctl->int_lock, flags);
+		status &= hctl->int_mask;
+		spin_unlock_irqrestore(&hctl->int_lock, flags);
+		mutex_unlock(&hctl->hci_mutex);
+		ctrl_hci->isr_running = 1;
+		if (status & SSV6XXX_INT_RX) {
+			ret = _isr_do_rx(hctl, status);
+			if (ret < 0) {
+				ret = IRQ_NONE;
+				break;
+			}
+			dbg_isr_miss = false;
+		}
+		if (_do_tx(hctl, status)) {
+			dbg_isr_miss = false;
+		}
+		ctrl_hci->isr_running = 0;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (ctrl_hci->isr_mib_enable) {
+			getnstimeofday(&end_time);
+			diff_time = timespec_sub(end_time, start_time);
+			ctrl_hci->isr_total_time += timespec_to_ns(&diff_time);
+		}
+#endif
+	} while (1);
+	if (ctrl_hci->isr_summary_eable) {
+		if (dbg_isr_miss)
+			ctrl_hci->isr_miss_cnt++;
+		ctrl_hci->prev_isr_jiffes = jiffies;
+	}
+	return ret;
+}
+
+static struct ssv6xxx_hci_ops hci_ops = {
+	.hci_start = ssv6xxx_hci_start,
+	.hci_stop = ssv6xxx_hci_stop,
+	.hci_read_word = ssv6xxx_hci_read_word,
+	.hci_write_word = ssv6xxx_hci_write_word,
+	.hci_tx = ssv6xxx_hci_enqueue,
+	.hci_tx_pause = ssv6xxx_hci_txq_pause,
+	.hci_tx_resume = ssv6xxx_hci_txq_resume,
+	.hci_txq_flush = ssv6xxx_hci_txq_flush,
+	.hci_txq_flush_by_sta = ssv6xxx_hci_txq_flush_by_sta,
+	.hci_txq_empty = ssv6xxx_hci_is_txq_empty,
+	.hci_load_fw = ssv6xxx_hci_load_fw,
+	.hci_pmu_wakeup = ssv6xxx_hci_pmu_wakeup,
+	.hci_send_cmd = ssv6xxx_hci_send_cmd,
+	.hci_write_sram = ssv6xxx_hci_write_sram,
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	.hci_init_debugfs = ssv6xxx_hci_init_debugfs,
+	.hci_deinit_debugfs = ssv6xxx_hci_deinit_debugfs,
+#endif
+	.hci_interface_reset = ssv6xxx_hci_interface_reset,
+};
+
+int ssv6xxx_hci_deregister(void)
+{
+	u32 regval;
+	pr_debug("%s(): \n", __FUNCTION__);
+	if (ctrl_hci->shi == NULL)
+		return -1;
+	regval = 1;
+	ssv6xxx_hci_irq_disable();
+	flush_workqueue(ctrl_hci->hci_work_queue);
+	destroy_workqueue(ctrl_hci->hci_work_queue);
+	ctrl_hci->shi = NULL;
+	return 0;
+}
+
+EXPORT_SYMBOL(ssv6xxx_hci_deregister);
+int ssv6xxx_hci_register(struct ssv6xxx_hci_info *shi)
+{
+	int i;
+	if (shi == NULL || ctrl_hci->shi)
+		return -1;
+	shi->hci_ops = &hci_ops;
+	ctrl_hci->shi = shi;
+	ctrl_hci->txq_mask = 0;
+	mutex_init(&ctrl_hci->txq_mask_lock);
+	mutex_init(&ctrl_hci->hci_mutex);
+	spin_lock_init(&ctrl_hci->int_lock);
+
+	for (i = 0; i < SSV_HW_TXQ_NUM; i++) {
+		memset(&ctrl_hci->hw_txq[i], 0, sizeof(struct ssv_hw_txq));
+		skb_queue_head_init(&ctrl_hci->hw_txq[i].qhead);
+		ctrl_hci->hw_txq[i].txq_no = (u32) i;
+		ctrl_hci->hw_txq[i].max_qsize = SSV_HW_TXQ_MAX_SIZE;
+		ctrl_hci->hw_txq[i].resum_thres = SSV_HW_TXQ_RESUME_THRES;
+	}
+	ctrl_hci->hci_work_queue =
+	    create_singlethread_workqueue("ssv6xxx_hci_wq");
+	INIT_WORK(&ctrl_hci->hci_rx_work, ssv6xxx_hci_rx_work);
+	INIT_WORK(&ctrl_hci->hci_tx_work, ssv6xxx_hci_tx_work);
+	ctrl_hci->int_mask = SSV6XXX_INT_RX | SSV6XXX_INT_RESOURCE_LOW;
+	ctrl_hci->int_status = 0;
+	HCI_IRQ_SET_MASK(ctrl_hci, 0xFFFFFFFF);
+	ssv6xxx_hci_irq_disable();
+	HCI_IRQ_REQUEST(ctrl_hci, ssv6xxx_hci_isr);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	ctrl_hci->debugfs_dir = NULL;
+	ctrl_hci->isr_mib_enable = false;
+	ctrl_hci->isr_mib_reset = 0;
+	ctrl_hci->isr_total_time = 0;
+	ctrl_hci->isr_rx_io_time = 0;
+	ctrl_hci->isr_tx_io_time = 0;
+	ctrl_hci->isr_rx_io_count = 0;
+	ctrl_hci->isr_tx_io_count = 0;
+	ctrl_hci->isr_rx_proc_time = 0;
+#endif
+	return 0;
+}
+
+EXPORT_SYMBOL(ssv6xxx_hci_register);
+int ssv6xxx_hci_init(void)
+{
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+	extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
+#endif
+	ctrl_hci = kzalloc(sizeof(*ctrl_hci), GFP_KERNEL);
+	if (ctrl_hci == NULL)
+		return -ENOMEM;
+	memset((void *)ctrl_hci, 0, sizeof(*ctrl_hci));
+	ctrl_hci->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
+	if (ctrl_hci->rx_buf == NULL) {
+		kfree(ctrl_hci);
+		return -ENOMEM;
+	}
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+	ssv_dbg_ctrl_hci = ctrl_hci;
+#endif
+	return 0;
+}
+
+void ssv6xxx_hci_exit(void)
+{
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+	extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
+#endif
+	kfree(ctrl_hci);
+	ctrl_hci = NULL;
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+	ssv_dbg_ctrl_hci = NULL;
+#endif
+}
+
+EXPORT_SYMBOL(ssv6xxx_hci_init);
+EXPORT_SYMBOL(ssv6xxx_hci_exit);
diff --git a/drivers/net/wireless/ssv6051/hci/ssv_hci.h b/drivers/net/wireless/ssv6051/hci/ssv_hci.h
new file mode 100644
index 00000000000..dd166c607d5
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hci/ssv_hci.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_HCI_H_
+#define _SSV_HCI_H_
+#define SSV_HW_TXQ_NUM 5
+#define SSV_HW_TXQ_MAX_SIZE 64
+#define SSV_HW_TXQ_RESUME_THRES ((SSV_HW_TXQ_MAX_SIZE >> 2) *3)
+#define HCI_FLAGS_ENQUEUE_HEAD 0x00000001
+#define HCI_FLAGS_NO_FLOWCTRL 0x00000002
+struct ssv_hw_txq {
+	u32 txq_no;
+	struct sk_buff_head qhead;
+	int max_qsize;
+	int resum_thres;
+	bool paused;
+	u32 tx_pkt;
+	u32 tx_flags;
+};
+struct ssv6xxx_hci_ops {
+	int (*hci_start)(void);
+	int (*hci_stop)(void);
+	int (*hci_read_word)(u32 addr, u32 * regval);
+	int (*hci_write_word)(u32 addr, u32 regval);
+	int (*hci_load_fw)(u8 * firmware_name, u8 openfile);
+	int (*hci_tx)(struct sk_buff *, int, u32);
+	int (*hci_tx_pause)(u32 txq_mask);
+	int (*hci_tx_resume)(u32 txq_mask);
+	int (*hci_txq_flush)(u32 txq_mask);
+	int (*hci_txq_flush_by_sta)(int aid);
+	bool (*hci_txq_empty)(int txqid);
+	int (*hci_pmu_wakeup)(void);
+	int (*hci_send_cmd)(struct sk_buff *);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	bool (*hci_init_debugfs)(struct dentry * dev_deugfs_dir);
+	void (*hci_deinit_debugfs)(void);
+#endif
+	int (*hci_write_sram)(u32 addr, u8 * data, u32 size);
+	int (*hci_interface_reset)(void);
+};
+struct ssv6xxx_hci_info {
+	struct device *dev;
+	struct ssv6xxx_hwif_ops *if_ops;
+	struct ssv6xxx_hci_ops *hci_ops;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+	int (*hci_rx_cb)(struct sk_buff_head *, void *);
+#else
+	int (*hci_rx_cb)(struct sk_buff *, void *);
+#endif
+	void *rx_cb_args;
+	void (*hci_tx_cb)(struct sk_buff_head *, void *);
+	void *tx_cb_args;
+	int (*hci_tx_flow_ctrl_cb)(void *, int, bool, int debug);
+	void *tx_fctrl_cb_args;
+	void (*hci_tx_buf_free_cb)(struct sk_buff *, void *);
+	void *tx_buf_free_args;
+	void (*hci_skb_update_cb)(struct sk_buff *, void *);
+	void *skb_update_args;
+	void (*hci_tx_q_empty_cb)(u32 txq_no, void *);
+	void *tx_q_empty_args;
+};
+int ssv6xxx_hci_deregister(void);
+int ssv6xxx_hci_register(struct ssv6xxx_hci_info *);
+#endif
diff --git a/drivers/net/wireless/ssv6051/hwif/hwif.h b/drivers/net/wireless/ssv6051/hwif/hwif.h
new file mode 100644
index 00000000000..6b5263d157d
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hwif/hwif.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _LINUX_SSVCABRIO_PLATFORM_H
+#define _LINUX_SSVCABRIO_PLATFORM_H 
+#include <linux/mmc/host.h>
+#include <hwif/sdio/sdio_def.h>
+#define SSVCABRIO_PLAT_EEP_MAX_WORDS 2048
+#define SSV_REG_WRITE(dev,reg,val) \
+        (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
+#define SSV_REG_READ(dev,reg,buf) \
+        (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
+#if 0
+#define SSV_REG_WRITE(sh,reg,val) \
+        (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
+#define SSV_REG_READ(sh,reg,buf) \
+        (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
+#define SSV_REG_CONFIRM(sh,reg,val) \
+{ \
+    u32 regval; \
+    SSV_REG_READ(sh, reg, &regval); \
+    if (regval != (val)) { \
+        printk("[0x%08x]: 0x%08x!=0x%08x\n",\
+        (reg), (val), regval); \
+        return -1; \
+    } \
+}
+#define SSV_REG_SET_BITS(sh,reg,set,clr) \
+{ \
+    u32 reg_val; \
+    SSV_REG_READ(sh, reg, &reg_val); \
+    reg_val &= ~(clr); \
+    reg_val |= (set); \
+    SSV_REG_WRITE(sh, reg, reg_val); \
+}
+#endif
+struct ssv6xxx_hwif_ops {
+    int __must_check (*read)(struct device *child, void *buf,size_t *size);
+    int __must_check (*write)(struct device *child, void *buf, size_t len,u8 queue_num);
+    int __must_check (*readreg)(struct device *child, u32 addr, u32 *buf);
+    int __must_check (*writereg)(struct device *child, u32 addr, u32 buf);
+    int (*trigger_tx_rx)(struct device *child);
+    int (*irq_getmask)(struct device *child, u32 *mask);
+    void (*irq_setmask)(struct device *child,int mask);
+    void (*irq_enable)(struct device *child);
+    void (*irq_disable)(struct device *child,bool iswaitirq);
+    int (*irq_getstatus)(struct device *child,int *status);
+    void (*irq_request)(struct device *child,irq_handler_t irq_handler,void *irq_dev);
+    void (*irq_trigger)(struct device *child);
+    void (*pmu_wakeup)(struct device *child);
+    int __must_check (*load_fw)(struct device *child, u8 *firmware_name, u8 openfile);
+    int (*cmd52_read)(struct device *child, u32 addr, u32 *value);
+    int (*cmd52_write)(struct device *child, u32 addr, u32 value);
+    bool (*support_scatter)(struct device *child);
+    int (*rw_scatter)(struct device *child, struct sdio_scatter_req *scat_req);
+    bool (*is_ready)(struct device *child);
+    int (*write_sram)(struct device *child, u32 addr, u8 *data, u32 size);
+    void (*interface_reset)(struct device *child);
+};
+struct ssv6xxx_if_debug {
+    struct device *dev;
+    struct platform_device *pdev;
+};
+struct ssv6xxx_platform_data {
+    atomic_t irq_handling;
+    bool is_enabled;
+    unsigned short vendor;
+    unsigned short device;
+    struct ssv6xxx_hwif_ops *ops;
+};
+#endif
diff --git a/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c b/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
new file mode 100644
index 00000000000..273777cd048
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
@@ -0,0 +1,1254 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/sdio.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include "sdio_def.h"
+#include <linux/pm_runtime.h>
+#include <linux/version.h>
+#include <linux/firmware.h>
+#include <linux/reboot.h>
+#include <ssv6200.h>
+#include <linux/skbuff.h>
+
+#define LOW_SPEED_SDIO_CLOCK (25000000)
+#define HIGH_SPEED_SDIO_CLOCK (37500000)
+#define MAX_RX_FRAME_SIZE 0x900
+#define SSV_VENDOR_ID 0x3030
+#define SSV_CABRIO_DEVID 0x3030
+#define ENABLE_FW_SELF_CHECK 1
+#define FW_BLOCK_SIZE 0x8000
+#define CHECKSUM_BLOCK_SIZE 1024
+#define FW_CHECKSUM_INIT (0x12345678)
+#define FW_STATUS_REG ADR_TX_SEG
+#define FW_STATUS_MASK (0x00FF0000)
+
+#define ret_if_not_ready(value) \
+    do { \
+    if ((wlan_data.is_enabled == false) || \
+        (glue == NULL) || (glue->dev_ready == false)) { \
+        pr_warn("ret_if_not_ready() called when not ready"); \
+        return value; }\
+    } while(0)
+
+static int ssv6xxx_sdio_trigger_pmu(struct device *dev);
+static void ssv6xxx_sdio_reset(struct device *child);
+
+static void ssv6xxx_high_sdio_clk(struct sdio_func *func);
+static void ssv6xxx_low_sdio_clk(struct sdio_func *func);
+extern void *ssv6xxx_ifdebug_info[];
+extern int ssv_devicetype;
+extern void ssv6xxx_deinit_prepare(void);
+
+static struct ssv6xxx_platform_data wlan_data;
+
+static int ssv6xxx_sdio_status = 0;
+u32 sdio_sr_bhvr = SUSPEND_RESUME_0;
+EXPORT_SYMBOL(sdio_sr_bhvr);
+
+u32 shutdown_flags = SSV_SYS_REBOOT;
+
+struct ssv6xxx_sdio_glue {
+	struct device *dev;
+	struct platform_device *core;
+	struct sk_buff *dma_skb;
+#ifdef CONFIG_PM
+	struct sk_buff *cmd_skb;
+#endif
+	unsigned int ioport_data;
+	unsigned int ioport_reg;
+	irq_handler_t irq_handler;
+	void *irq_dev;
+	bool dev_ready;
+};
+
+static const struct sdio_device_id ssv6xxx_sdio_devices[] = {
+	{SDIO_DEVICE(SSV_VENDOR_ID, SSV_CABRIO_DEVID)},
+	{}
+};
+
+MODULE_DEVICE_TABLE(sdio, ssv6xxx_sdio_devices);
+
+static bool ssv6xxx_is_ready(struct device *child)
+{
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+
+	ret_if_not_ready(false);
+
+	return true;
+}
+
+static int ssv6xxx_sdio_cmd52_read(struct device *child, u32 addr, u32 * value)
+{
+	int ret;
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+	ret_if_not_ready(-1);
+
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    *value = sdio_readb(func, addr, &ret);
+    sdio_release_host(func);
+
+	return ret;
+}
+
+static int ssv6xxx_sdio_cmd52_write(struct device *child, u32 addr, u32 value)
+{
+	int ret;
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+    ret_if_not_ready(-1);
+
+	func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    sdio_writeb(func, value, addr, &ret);
+    sdio_release_host(func);
+
+	return ret;
+}
+
+static int __must_check
+ssv6xxx_sdio_read_reg(struct device *child, u32 addr, u32 * buf)
+{
+	int ret;
+
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+	u32 data;
+
+    ret_if_not_ready(-1);
+
+    func = dev_to_sdio_func(glue->dev);
+
+    sdio_claim_host(func);
+
+    data = addr;
+
+    ret = sdio_memcpy_toio(func, glue->ioport_reg, &data, sizeof(data));
+
+    if (unlikely(ret)) {
+        dev_err(child->parent, "sdio read reg write address failed (%d)\n", ret);
+        goto io_err;
+    }
+
+    ret = sdio_memcpy_fromio(func, &data, glue->ioport_reg, sizeof(data));
+
+    if (unlikely(ret)) {
+        *buf = 0xffffffff;
+        dev_err(child->parent, "sdio read reg from I/O failed (%d)\n", ret);
+        goto io_err;
+    }
+
+    *buf = data;
+
+io_err:
+    sdio_release_host(func);
+
+	return ret;
+}
+
+#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
+static int ssv6xxx_sdio_trigger_tx_rx(struct device *child)
+{
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+	struct mmc_host *host;
+
+	if (glue == NULL)
+		return -1;
+
+	func = dev_to_sdio_func(glue->dev);
+	host = func->card->host;
+	mmc_signal_sdio_irq(host);
+
+	return 0;
+
+}
+#endif
+
+static int __must_check
+ssv6xxx_sdio_write_reg(struct device *child, u32 addr, u32 buf)
+{
+	int ret;
+
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+    u32 data[2];
+
+    ret_if_not_ready(-1);
+
+    func = dev_to_sdio_func(glue->dev);
+
+    sdio_claim_host(func);
+    data[0] = addr;
+    data[1] = buf;
+
+    ret = sdio_memcpy_toio(func, glue->ioport_reg, data, sizeof(data));
+    sdio_release_host(func);
+
+	return ret;
+}
+
+static int
+ssv6xxx_sdio_write_sram(struct device *child, u32 addr, u8 * data, u32 size)
+{
+	int ret = 0;
+	struct ssv6xxx_sdio_glue *glue;
+	struct sdio_func *func = NULL;
+	glue = dev_get_drvdata(child->parent);
+
+    ret_if_not_ready(-1);
+
+	func = dev_to_sdio_func(glue->dev);
+	sdio_claim_host(func);
+
+    ret |= ssv6xxx_sdio_write_reg(child, 0xc0000860, addr);
+    if (unlikely(ret))
+        goto out;
+
+    sdio_writeb(func, 0x2, REG_Fn1_STATUS, &ret);
+    if (unlikely(ret))
+        goto out;
+
+    ret = sdio_memcpy_toio(func, glue->ioport_data, data, size);
+    if (unlikely(ret))
+        goto out;
+
+    sdio_writeb(func, 0, REG_Fn1_STATUS, &ret);
+    if (unlikely(ret))
+        goto out;
+
+out:
+	sdio_release_host(func);
+	return ret;
+
+}
+
+struct file *ssv6xxx_open_firmware(char *user_mainfw)
+{
+	struct file *fp;
+	fp = filp_open(user_mainfw, O_RDONLY, 0);
+
+	if (IS_ERR(fp))
+		fp = NULL;
+
+	return fp;
+}
+
+int ssv6xxx_read_fw_block(char *buf, int len, struct file *fp)
+{
+
+	int read;
+	loff_t pos;
+
+	pos = fp->f_pos;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
+	read = kernel_read(fp, (void *)buf, len, &pos);
+#else
+	read = kernel_read(fp, pos, buf, len);
+#endif
+
+	if (read > 0)
+		fp->f_pos += read;
+
+	return read;
+
+}
+
+void ssv6xxx_close_firmware(struct file *fp)
+{
+	if (fp)
+		filp_close(fp, NULL);
+}
+
+static int
+ssv6xxx_sdio_upload_firmware(struct device *child, const u8 *firmware, u32 firmware_length)
+{
+	int ret;
+    u32 clk_en;
+	u32 word_count, i;
+    u32 block_size;
+	u8 *buffer;
+	u32 sram_ptr = 0;
+	u32 block_count = 0;
+    u32 firmware_ptr = 0;
+
+	u32 checksum = FW_CHECKSUM_INIT;
+	u32 fw_checksum, fw_blkcnt;
+
+	struct ssv6xxx_sdio_glue *glue;
+
+	glue = dev_get_drvdata(child->parent);
+
+    if ((wlan_data.is_enabled == false) &&
+        (glue == NULL) &&
+        (glue->dev_ready == false))
+        goto out;
+
+    buffer = (u8 *)kzalloc(FW_BLOCK_SIZE, GFP_KERNEL);
+    if (buffer == NULL) {
+        dev_err(child, "Failed to allocate buffer for firmware.\n");
+        ret = -ENOMEM;
+        goto out;
+    }
+
+    dev_dbg(child, "preparing registers and clock for firmware upload\n");
+
+    ret = ssv6xxx_sdio_write_reg(child, ADR_BRG_SW_RST, 0x0);
+    if (unlikely(ret))
+        goto out;
+
+    ret = ssv6xxx_sdio_write_reg(child, ADR_BOOT, 0x01);
+    if (unlikely(ret))
+        goto out;
+
+    ret = ssv6xxx_sdio_read_reg(child, ADR_PLATFORM_CLOCK_ENABLE, &clk_en);
+    if (unlikely(ret))
+        goto out;
+
+    ret = ssv6xxx_sdio_write_reg(child, ADR_PLATFORM_CLOCK_ENABLE, clk_en | (1 << 2));
+    if (unlikely(ret))
+        goto out;
+
+    dev_dbg(child, "begin writing firmware\n");
+
+    while (firmware_length > 0) {
+
+        memset(buffer, 0xA5, FW_BLOCK_SIZE);
+
+        block_size = firmware_length;
+        if (block_size > FW_BLOCK_SIZE)
+            block_size = FW_BLOCK_SIZE;
+
+        memcpy(buffer, &firmware[firmware_ptr], block_size);
+
+        firmware_ptr += block_size;
+        firmware_length -= block_size;
+
+        /*
+         * Uploading to chip sram and checksumming happens in chunks of CHECKSUM_BLOCK_SIZE,
+         * so we round the block size accordingly and use that valueù
+         */
+        block_size = DIV_ROUND_UP(block_size, CHECKSUM_BLOCK_SIZE) * CHECKSUM_BLOCK_SIZE;
+        ret = ssv6xxx_sdio_write_sram(child, sram_ptr, (u8 *)buffer, block_size);
+
+        if (ret) {
+            dev_err(child, "firmware upload failed\n");
+            goto out;
+        }
+
+        sram_ptr += block_size;
+
+        word_count = block_size / sizeof(u32);
+        for (i = 0; i < word_count; i++)
+            checksum += ((u32 *)buffer)[i];
+
+    }
+
+    checksum = ((checksum >> 24) +
+                (checksum >> 16) +
+                (checksum >> 8) +
+                checksum) & 0x0FF;
+    checksum <<= 16;
+
+    block_count = DIV_ROUND_UP(sram_ptr, CHECKSUM_BLOCK_SIZE);
+    ret = ssv6xxx_sdio_write_reg(child, FW_STATUS_REG, (block_count << 16));
+    if (unlikely(ret))
+        goto out;
+
+    ret = ssv6xxx_sdio_read_reg(child, FW_STATUS_REG, &fw_blkcnt);
+    if (unlikely(ret))
+        goto out;
+
+    ret = ssv6xxx_sdio_write_reg(child, ADR_BRG_SW_RST, 0x1);
+    if (unlikely(ret))
+        goto out;
+
+    dev_info(child, "firmware upload complete (wrote %d blocks, verified %d blocks)\n", block_count, fw_blkcnt >> 16);
+
+    msleep(50);
+
+    ret = ssv6xxx_sdio_read_reg(child, FW_STATUS_REG, &fw_checksum);
+    fw_checksum = fw_checksum & FW_STATUS_MASK;
+
+    if (fw_checksum == checksum) {
+        dev_dbg(child, "firmware check ok, checksum=0x%x\n", checksum);
+        ret = ssv6xxx_sdio_write_reg(child, FW_STATUS_REG, (~checksum & FW_STATUS_MASK));
+        if (unlikely(ret))
+            dev_warn(child, "could not clear checksum condition");
+    } else {
+        dev_err(child, "firmware checksum mismatch, local=0x%x, sram=0x%x\n", checksum, fw_checksum);
+    }
+
+    msleep(50);
+
+    ret = 0;
+
+ out:
+
+	if (buffer)
+		kfree(buffer);
+
+	return ret;
+
+}
+
+static int
+ssv6xxx_sdio_load_firmware(struct device *child, u8 *firmware_name, u8 openfile)
+{
+
+    int ret;
+    const struct firmware *firmware = NULL;
+    struct sdio_func *func;
+   	struct ssv6xxx_sdio_glue *glue;
+
+    glue = dev_get_drvdata(child->parent);
+
+    ret = request_firmware(&firmware, firmware_name, glue->dev);
+
+    if (ret) {
+        dev_err(child, "could not find firmware file %s, err=%d\n", firmware_name, ret);
+        goto out;
+    }
+
+    ret = ssv6xxx_sdio_upload_firmware(child, firmware->data, firmware->size);
+
+    if (ret) {
+        dev_err(child, "could not upload firmware to device, err=%d\n", ret);
+        goto out;
+    }
+
+    if (glue != NULL) {
+		func = dev_to_sdio_func(glue->dev);
+		ssv6xxx_high_sdio_clk(func);
+	}
+
+out:
+    if (firmware != NULL)
+        release_firmware(firmware);
+
+    return ret;
+
+}
+
+static int ssv6xxx_sdio_irq_getstatus(struct device *child, int *status)
+{
+	int ret = (-1);
+	struct ssv6xxx_sdio_glue *glue;
+	struct sdio_func *func;
+	glue = dev_get_drvdata(child->parent);
+
+    ret_if_not_ready(-1);
+
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    *status = sdio_readb(func, REG_INT_STATUS, &ret);
+    sdio_release_host(func);
+
+    return ret;
+
+}
+
+static int __must_check
+ssv6xxx_sdio_read(struct device *child, void *buf, size_t *size)
+{
+
+	int ret;
+    u32 data_size;
+
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+    ret_if_not_ready(-1);
+
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+
+    data_size = sdio_readb(func, REG_CARD_PKT_LEN_0, &ret);
+
+    if (unlikely(ret)) {
+        dev_err(child->parent, "sdio read high byte len failed, ret=%d\n", ret);
+        goto out;
+    }
+
+    data_size = data_size | (sdio_readb(func, REG_CARD_PKT_LEN_1, &ret) << 0x8);
+
+    if (unlikely(ret)) {
+        dev_err(child->parent, "sdio read low len failed ret[%d]\n", ret);
+        goto out;
+    }
+
+    ret = sdio_memcpy_fromio(func, buf, glue->ioport_data, sdio_align_size(func, data_size));
+
+    if (unlikely(ret)) {
+        dev_err(child->parent, "sdio read failed size ret[%d]\n", ret);
+        goto out;
+    }
+    
+    *size = data_size;
+
+out:
+
+    sdio_release_host(func);
+
+	return ret;
+}
+
+static int __must_check
+ssv6xxx_sdio_write(struct device *child, void *buf, size_t len, u8 queue_num)
+{
+	int ret;
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+	void *ptr;
+
+    ret_if_not_ready(-1);
+
+#ifdef CONFIG_ARM64
+    if (((u64) buf) & 3) {
+#else
+    if (((u32) buf) & 3) {
+#endif
+        memcpy(glue->dma_skb->data, buf, len);
+        ptr = glue->dma_skb->data;
+    } else
+        ptr = buf;
+
+    func = dev_to_sdio_func(glue->dev);
+
+    sdio_claim_host(func);
+
+    len = sdio_align_size(func, len);
+    ret = sdio_memcpy_toio(func, glue->ioport_data, ptr, len);
+
+    if (unlikely(ret))
+        dev_err(glue->dev, "sdio write failed, ret=%d\n", ret);
+
+    sdio_release_host(func);
+
+    return ret;
+
+}
+
+static void ssv6xxx_sdio_irq_handler(struct sdio_func *func)
+{
+	int status;
+	struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
+
+    ret_if_not_ready();
+
+    if (glue->irq_handler == NULL)
+        return;
+
+    atomic_set(&pwlan_data->irq_handling, 1);
+    sdio_release_host(func);
+    if (glue->irq_handler != NULL)
+        status = glue->irq_handler(0, glue->irq_dev);
+    sdio_claim_host(func);
+    atomic_set(&pwlan_data->irq_handling, 0);
+
+}
+
+static void ssv6xxx_sdio_irq_setmask(struct device *child, int mask)
+{
+	int err_ret;
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+    ret_if_not_ready();
+
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    sdio_writeb(func, mask, REG_INT_MASK, &err_ret);
+    sdio_release_host(func);
+
+}
+
+static void ssv6xxx_sdio_irq_trigger(struct device *child)
+{
+	int err_ret;
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+    ret_if_not_ready();
+
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    sdio_writeb(func, 0x2, REG_INT_TRIGGER, &err_ret);
+    sdio_release_host(func);
+
+}
+
+static int ssv6xxx_sdio_irq_getmask(struct device *child, u32 * mask)
+{
+	u8 imask = 0;
+	int ret = (-1);
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+    ret_if_not_ready(-1);
+
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    imask = sdio_readb(func, REG_INT_MASK, &ret);
+    *mask = imask;
+    sdio_release_host(func);
+
+	return ret;
+
+}
+
+static void ssv6xxx_sdio_irq_enable(struct device *child)
+{
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+	int ret;
+	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
+	if ((pwlan_data->is_enabled == false)
+	    || (glue == NULL) || (glue->dev_ready == false))
+		return;
+
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    ret = sdio_claim_irq(func, ssv6xxx_sdio_irq_handler);
+    if (ret)
+        dev_err(child->parent, "Failed to claim sdio irq: %d\n",
+            ret);
+    sdio_release_host(func);
+
+	dev_dbg(child, "ssv6xxx_sdio_irq_enable\n");
+
+}
+
+static void ssv6xxx_sdio_irq_disable(struct device *child, bool iswaitirq)
+{
+	struct ssv6xxx_sdio_glue *glue = NULL;
+	struct sdio_func *func;
+	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
+	int ret;
+
+	dev_dbg(child, "ssv6xxx_sdio_irq_disable\n");
+
+	if ((wlan_data.is_enabled == false) || (child->parent == NULL))
+		return;
+
+	glue = dev_get_drvdata(child->parent);
+
+
+	if ((glue == NULL) || (glue->dev_ready == false)
+	    || (glue->dev == NULL))
+		return;
+
+    func = dev_to_sdio_func(glue->dev);
+
+    if (func == NULL) {
+        dev_dbg(child, "sdio func == NULL\n");
+        return;
+    }
+
+    sdio_claim_host(func);
+    while (atomic_read(&pwlan_data->irq_handling)) {
+        sdio_release_host(func);
+        schedule_timeout(HZ / 10);
+        sdio_claim_host(func);
+    }
+    ret = sdio_release_irq(func);
+
+    if (ret)
+        dev_err(child->parent,
+            "Failed to release sdio irq: %d\n", ret);
+
+    sdio_release_host(func);
+
+}
+
+static void
+ssv6xxx_sdio_irq_request(struct device *child, irq_handler_t irq_handler,
+			 void *irq_dev)
+{
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+	bool isIrqEn = false;
+
+    ret_if_not_ready();
+
+    func = dev_to_sdio_func(glue->dev);
+    glue->irq_handler = irq_handler;
+    glue->irq_dev = irq_dev;
+    if (isIrqEn) {
+        ssv6xxx_sdio_irq_enable(child);
+    }
+
+}
+
+static void
+ssv6xxx_sdio_read_parameter(struct sdio_func *func,
+			    struct ssv6xxx_sdio_glue *glue)
+{
+	int err_ret;
+	sdio_claim_host(func);
+	glue->ioport_data = 0;
+	glue->ioport_data =
+	    glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_0, &err_ret)
+				<< (8 * 0));
+	glue->ioport_data =
+	    glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_1, &err_ret)
+				<< (8 * 1));
+	glue->ioport_data =
+	    glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_2, &err_ret)
+				<< (8 * 2));
+	glue->ioport_reg = 0;
+	glue->ioport_reg =
+	    glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_0, &err_ret) <<
+			       (8 * 0));
+	glue->ioport_reg =
+	    glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_1, &err_ret) <<
+			       (8 * 1));
+	glue->ioport_reg =
+	    glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_2, &err_ret) <<
+			       (8 * 2));
+	dev_dbg(&func->dev, "ioport_data=0x%x ioport_reg=0x%x\n",
+		glue->ioport_data, glue->ioport_reg);
+	err_ret = sdio_set_block_size(func, CONFIG_PLATFORM_SDIO_BLOCK_SIZE);
+	if (err_ret != 0) {
+		dev_warn(&func->dev, "SDIO setting SDIO_DEF_BLOCK_SIZE fail!!\n");
+	}
+	sdio_writeb(func, CONFIG_PLATFORM_SDIO_OUTPUT_TIMING,
+		    REG_OUTPUT_TIMING_REG, &err_ret);
+	sdio_writeb(func, 0x00, REG_Fn1_STATUS, &err_ret);
+	sdio_release_host(func);
+}
+
+static void ssv6xxx_do_sdio_wakeup(struct sdio_func *func)
+{
+	int err_ret;
+	if (func != NULL) {
+		sdio_claim_host(func);
+		sdio_writeb(func, 0x01, REG_PMU_WAKEUP, &err_ret);
+		mdelay(10);
+		sdio_writeb(func, 0x00, REG_PMU_WAKEUP, &err_ret);
+		sdio_release_host(func);
+	}
+}
+
+static void ssv6xxx_sdio_pmu_wakeup(struct device *child)
+{
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+	if (glue != NULL) {
+		func = dev_to_sdio_func(glue->dev);
+		ssv6xxx_do_sdio_wakeup(func);
+	}
+}
+
+static bool ssv6xxx_sdio_support_scatter(struct device *child)
+{
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+    if (!glue) {
+        dev_err(child->parent, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
+        return false;
+    }
+
+    func = dev_to_sdio_func(glue->dev);
+
+    if (func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
+        dev_err(child->parent,
+            "host controller only supports scatter of :%d entries, driver need: %d\n",
+            func->card->host->max_segs,
+            MAX_SCATTER_ENTRIES_PER_REQ);
+        return false;
+    }
+
+    return true;
+
+}
+
+static void
+ssv6xxx_sdio_setup_scat_data(struct sdio_scatter_req *scat_req,
+			     struct mmc_data *data)
+{
+	struct scatterlist *sg;
+	int i;
+	data->blksz = SDIO_DEF_BLOCK_SIZE;
+	data->blocks = scat_req->len / SDIO_DEF_BLOCK_SIZE;
+	pr_debug
+	    ("scatter: (%s)  (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
+	     (scat_req->req & SDIO_WRITE) ? "WR" : "RD", data->blksz,
+	     data->blocks, scat_req->len, scat_req->scat_entries);
+	data->flags =
+	    (scat_req->req & SDIO_WRITE) ? MMC_DATA_WRITE : MMC_DATA_READ;
+	sg = scat_req->sgentries;
+	sg_init_table(sg, scat_req->scat_entries);
+	for (i = 0; i < scat_req->scat_entries; i++, sg++) {
+		pr_debug("%d: addr:0x%p, len:%d\n",
+		       i, scat_req->scat_list[i].buf,
+		       scat_req->scat_list[i].len);
+		sg_set_buf(sg, scat_req->scat_list[i].buf,
+			   scat_req->scat_list[i].len);
+	}
+	data->sg = scat_req->sgentries;
+	data->sg_len = scat_req->scat_entries;
+}
+
+static inline void
+ssv6xxx_sdio_set_cmd53_arg(u32 * arg, u8 rw, u8 func,
+			   u8 mode, u8 opcode, u32 addr, u16 blksz)
+{
+	*arg = (((rw & 1) << 31) |
+		((func & 0x7) << 28) |
+		((mode & 1) << 27) |
+		((opcode & 1) << 26) | ((addr & 0x1FFFF) << 9) | (blksz &
+								  0x1FF));
+}
+
+static int
+ssv6xxx_sdio_rw_scatter(struct device *child, struct sdio_scatter_req *scat_req)
+{
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+	struct mmc_request mmc_req;
+	struct mmc_command cmd;
+	struct mmc_data data;
+	u8 opcode, rw;
+	int status = 1;
+
+    if (!glue) {
+        dev_err(child->parent, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
+        return 1;
+    }
+
+    func = dev_to_sdio_func(glue->dev);
+    memset(&mmc_req, 0, sizeof(struct mmc_request));
+    memset(&cmd, 0, sizeof(struct mmc_command));
+    memset(&data, 0, sizeof(struct mmc_data));
+    ssv6xxx_sdio_setup_scat_data(scat_req, &data);
+    opcode = 0;
+    rw = (scat_req->req & SDIO_WRITE) ? CMD53_ARG_WRITE :
+        CMD53_ARG_READ;
+    ssv6xxx_sdio_set_cmd53_arg(&cmd.arg, rw, func->num,
+                    CMD53_ARG_BLOCK_BASIS, opcode,
+                    glue->ioport_data, data.blocks);
+    cmd.opcode = SD_IO_RW_EXTENDED;
+    cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
+    mmc_req.cmd = &cmd;
+    mmc_req.data = &data;
+    mmc_set_data_timeout(&data, func->card);
+    mmc_wait_for_req(func->card->host, &mmc_req);
+
+    status = cmd.error ? cmd.error : data.error;
+
+    if (cmd.error)
+        return cmd.error;
+
+    if (data.error)
+        return data.error;
+
+    return status;
+
+}
+
+static void ssv6xxx_set_sdio_clk(struct sdio_func *func, u32 sdio_hz)
+{
+	struct mmc_host *host;
+	host = func->card->host;
+	if (sdio_hz < host->f_min)
+		sdio_hz = host->f_min;
+	else if (sdio_hz > host->f_max)
+		sdio_hz = host->f_max;
+	dev_dbg(&func->dev, "%s:set sdio clk %dHz\n", __FUNCTION__, sdio_hz);
+	sdio_claim_host(func);
+	host->ios.clock = sdio_hz;
+	host->ops->set_ios(host, &host->ios);
+	mdelay(20);
+	sdio_release_host(func);
+}
+
+static void ssv6xxx_low_sdio_clk(struct sdio_func *func)
+{
+	ssv6xxx_set_sdio_clk(func, LOW_SPEED_SDIO_CLOCK);
+}
+
+static void ssv6xxx_high_sdio_clk(struct sdio_func *func)
+{
+#ifndef SDIO_USE_SLOW_CLOCK
+	ssv6xxx_set_sdio_clk(func, HIGH_SPEED_SDIO_CLOCK);
+#endif
+}
+
+static struct ssv6xxx_hwif_ops sdio_ops = {
+	.read = ssv6xxx_sdio_read,
+	.write = ssv6xxx_sdio_write,
+	.readreg = ssv6xxx_sdio_read_reg,
+	.writereg = ssv6xxx_sdio_write_reg,
+#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
+	.trigger_tx_rx = ssv6xxx_sdio_trigger_tx_rx,
+#endif
+	.irq_getmask = ssv6xxx_sdio_irq_getmask,
+	.irq_setmask = ssv6xxx_sdio_irq_setmask,
+	.irq_enable = ssv6xxx_sdio_irq_enable,
+	.irq_disable = ssv6xxx_sdio_irq_disable,
+	.irq_getstatus = ssv6xxx_sdio_irq_getstatus,
+	.irq_request = ssv6xxx_sdio_irq_request,
+	.irq_trigger = ssv6xxx_sdio_irq_trigger,
+	.pmu_wakeup = ssv6xxx_sdio_pmu_wakeup,
+	.load_fw = ssv6xxx_sdio_load_firmware,
+	.cmd52_read = ssv6xxx_sdio_cmd52_read,
+	.cmd52_write = ssv6xxx_sdio_cmd52_write,
+	.support_scatter = ssv6xxx_sdio_support_scatter,
+	.rw_scatter = ssv6xxx_sdio_rw_scatter,
+	.is_ready = ssv6xxx_is_ready,
+	.write_sram = ssv6xxx_sdio_write_sram,
+	.interface_reset = ssv6xxx_sdio_reset,
+};
+
+static int
+ssv6xxx_sdio_power_on(struct ssv6xxx_platform_data *pdata,
+		      struct sdio_func *func)
+{
+	int ret = 0;
+	if (pdata->is_enabled == true)
+		return 0;
+
+	dev_dbg(&func->dev, "ssv6xxx_sdio_power_on\n");
+
+	sdio_claim_host(func);
+	ret = sdio_enable_func(func);
+	sdio_release_host(func);
+
+	if (ret) {
+		dev_err(&func->dev, "Unable to enable sdio func: %d)\n", ret);
+		return ret;
+	}
+
+	msleep(10);
+	pdata->is_enabled = true;
+
+	return ret;
+}
+
+static int
+ssv6xxx_sdio_power_off(struct ssv6xxx_platform_data *pdata,
+		       struct sdio_func *func)
+{
+	int ret;
+	if (pdata->is_enabled == false)
+		return 0;
+	dev_dbg(&func->dev, "ssv6xxx_sdio_power_off\n");
+	sdio_claim_host(func);
+	ret = sdio_disable_func(func);
+	sdio_release_host(func);
+	if (ret)
+		return ret;
+	pdata->is_enabled = false;
+	return ret;
+}
+
+int ssv6xxx_get_dev_status(void)
+{
+	return ssv6xxx_sdio_status;
+}
+
+EXPORT_SYMBOL(ssv6xxx_get_dev_status);
+
+static int
+ssv6xxx_sdio_probe(struct sdio_func *func, const struct sdio_device_id *id)
+{
+	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
+	struct ssv6xxx_sdio_glue *glue;
+	int ret;
+	const char *chip_family = "ssv6200";
+
+	if (ssv_devicetype != 0) {
+		dev_info(&func->dev, "Not using SSV6200 normal SDIO driver.\n");
+		return -ENODEV;
+	}
+
+	if (func->num != 0x01)
+		return -ENODEV;
+
+	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
+
+	if (!glue) {
+		dev_err(&func->dev, "can't allocate glue\n");
+		return -ENOMEM;
+	}
+
+	ssv6xxx_sdio_status = 1;
+	ssv6xxx_low_sdio_clk(func);
+
+	glue->dma_skb = __dev_alloc_skb(SDIO_DMA_BUFFER_LEN, GFP_KERNEL);
+
+#ifdef CONFIG_PM
+	glue->cmd_skb = __dev_alloc_skb(SDIO_COMMAND_BUFFER_LEN, GFP_KERNEL);
+#endif
+	memset(pwlan_data, 0, sizeof(struct ssv6xxx_platform_data));
+	atomic_set(&pwlan_data->irq_handling, 0);
+	glue->dev = &func->dev;
+	func->card->quirks |= MMC_QUIRK_LENIENT_FN0;
+	func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
+	glue->dev_ready = true;
+	pwlan_data->vendor = func->vendor;
+	pwlan_data->device = func->device;
+	dev_info(glue->dev, "device id: %x:%x\n", pwlan_data->vendor,
+		pwlan_data->device);
+	pwlan_data->ops = &sdio_ops;
+	sdio_set_drvdata(func, glue);
+#ifdef CONFIG_PM
+	ssv6xxx_do_sdio_wakeup(func);
+#endif
+	ssv6xxx_sdio_power_on(pwlan_data, func);
+	ssv6xxx_sdio_read_parameter(func, glue);
+	glue->core = platform_device_alloc(chip_family, -1);
+
+	if (!glue->core) {
+		dev_err(glue->dev, "can't allocate platform_device");
+		ret = -ENOMEM;
+		goto out_free_glue;
+	}
+
+	glue->core->dev.parent = &func->dev;
+
+	ret = platform_device_add_data(glue->core, pwlan_data,
+				       sizeof(*pwlan_data));
+
+	if (ret) {
+		dev_err(glue->dev, "can't add platform data\n");
+		goto out_dev_put;
+	}
+
+	ret = platform_device_add(glue->core);
+
+	if (ret) {
+		dev_err(glue->dev, "can't add platform device\n");
+		goto out_dev_put;
+	}
+
+	ssv6xxx_sdio_irq_setmask(&glue->core->dev, 0xff);
+
+	ssv6xxx_ifdebug_info[0] = (void *)&glue->core->dev;
+	ssv6xxx_ifdebug_info[1] = (void *)glue->core;
+	ssv6xxx_ifdebug_info[2] = (void *)&sdio_ops;
+	return 0;
+
+ out_dev_put:
+	platform_device_put(glue->core);
+ out_free_glue:
+	kfree(glue);
+
+	return ret;
+
+}
+
+static void ssv6xxx_sdio_remove(struct sdio_func *func)
+{
+	struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
+
+	dev_dbg(&func->dev, "ssv6xxx_sdio_remove enter\n");
+
+	ssv6xxx_sdio_status = 0;
+
+	if (glue) {
+		dev_dbg(&func->dev, "ssv6xxx_sdio_remove - ssv6xxx_sdio_irq_disable\n");
+		ssv6xxx_sdio_irq_disable(&glue->core->dev, false);
+		glue->dev_ready = false;
+		ssv6xxx_low_sdio_clk(func);
+
+		if (glue->dma_skb != NULL)
+			dev_kfree_skb(glue->dma_skb);
+
+		dev_dbg(&func->dev, "ssv6xxx_sdio_remove - disable mask\n");
+		ssv6xxx_sdio_irq_setmask(&glue->core->dev, 0xff);
+#ifdef CONFIG_PM
+		ssv6xxx_sdio_trigger_pmu(glue->dev);
+		if (glue->cmd_skb != NULL)
+			dev_kfree_skb(glue->cmd_skb);
+#endif
+		ssv6xxx_sdio_power_off(pwlan_data, func);
+		dev_dbg(&func->dev, "platform_device_del \n");
+		platform_device_del(glue->core);
+		dev_dbg(&func->dev, "platform_device_put \n");
+		platform_device_put(glue->core);
+		kfree(glue);
+	}
+
+	sdio_set_drvdata(func, NULL);
+	dev_dbg(&func->dev, "ssv6xxx_sdio_remove leave\n");
+
+}
+
+static int ssv6xxx_sdio_trigger_pmu(struct device *dev)
+{
+
+	int ret = 0;
+
+#ifdef CONFIG_PM
+	struct sdio_func *func = dev_to_sdio_func(dev);
+	struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+	struct cfg_host_cmd *host_cmd;
+	int writesize;
+	void *tempPointer;
+
+	if (ssv6xxx_sdio_write_reg
+	    (dev, ADR_RX_FLOW_MNG, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
+	if (ssv6xxx_sdio_write_reg
+	    (dev, ADR_RX_FLOW_DATA, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
+	if (ssv6xxx_sdio_write_reg
+	    (dev, ADR_RX_FLOW_CTRL, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
+
+	host_cmd = (struct cfg_host_cmd *)glue->cmd_skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->RSVD0 = 0;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_PS;
+	host_cmd->len = sizeof(struct cfg_host_cmd);
+
+	host_cmd->dummy = 0;
+
+	{
+		tempPointer = glue->cmd_skb->data;
+		sdio_claim_host(func);
+		writesize = sdio_align_size(func, sizeof(struct cfg_host_cmd));
+		do {
+			ret =
+			    sdio_memcpy_toio(func, glue->ioport_data,
+					     tempPointer, writesize);
+			if (ret == -EILSEQ || ret == -ETIMEDOUT) {
+				ret = -1;
+				break;
+			} else {
+				if (ret)
+					dev_err(glue->dev,
+						"Unexpected return value ret=[%d]\n",
+						ret);
+			}
+		}
+		while (ret == -EILSEQ || ret == -ETIMEDOUT);
+		sdio_release_host(func);
+		if (ret)
+			dev_err(glue->dev, "sdio write failed (%d)\n", ret);
+	}
+
+#endif
+
+	return ret;
+
+}
+
+static void ssv6xxx_sdio_reset(struct device *child)
+{
+
+#ifdef CONFIG_PM
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func = dev_to_sdio_func(glue->dev);
+	dev_dbg(child, "%s\n", __FUNCTION__);
+	if (glue == NULL || glue->dev == NULL || func == NULL)
+		return;
+	ssv6xxx_sdio_trigger_pmu(glue->dev);
+	ssv6xxx_do_sdio_wakeup(func);
+#endif
+
+	return;
+
+}
+
+#ifdef CONFIG_PM
+static int ssv6xxx_sdio_suspend(struct device *dev)
+{
+	struct sdio_func *func = dev_to_sdio_func(dev);
+	mmc_pm_flag_t flags = sdio_get_host_pm_caps(func);
+	{
+		int ret = 0;
+		dev_info(dev, "%s: suspend: PM flags = 0x%x\n",
+			 sdio_func_id(func), flags);
+		ssv6xxx_low_sdio_clk(func);
+		ret = ssv6xxx_sdio_trigger_pmu(dev);
+		if (ret)
+			dev_warn(dev, "ssv6xxx_sdio_trigger_pmu fail!!\n");
+		if (!(flags & MMC_PM_KEEP_POWER)) {
+			dev_err(dev,
+				"%s: cannot remain alive while host is suspended\n",
+				sdio_func_id(func));
+		}
+		ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
+		if (ret)
+			return ret;
+		mdelay(10);
+		return ret;
+	}
+}
+
+static int ssv6xxx_sdio_resume(struct device *dev)
+{
+	struct sdio_func *func = dev_to_sdio_func(dev);
+	{
+		dev_dbg(dev, "ssv6xxx_sdio_resume\n");
+		{
+			ssv6xxx_do_sdio_wakeup(func);
+			mdelay(10);
+			ssv6xxx_high_sdio_clk(func);
+			mdelay(10);
+		}
+	}
+	return 0;
+}
+
+static const struct dev_pm_ops ssv6xxx_sdio_pm_ops = {
+	.suspend = ssv6xxx_sdio_suspend,
+	.resume = ssv6xxx_sdio_resume,
+};
+#endif
+
+struct sdio_driver ssv6xxx_sdio_driver = {
+	.name = "ssv6051",
+	.id_table = ssv6xxx_sdio_devices,
+	.probe = ssv6xxx_sdio_probe,
+	.remove = ssv6xxx_sdio_remove,
+#ifdef CONFIG_PM
+	.drv = {
+		.pm = &ssv6xxx_sdio_pm_ops,
+		},
+#endif
+};
+
+EXPORT_SYMBOL(ssv6xxx_sdio_driver);
+
+int ssv6xxx_sdio_init(void)
+{
+	return sdio_register_driver(&ssv6xxx_sdio_driver);
+}
+
+void ssv6xxx_sdio_exit(void)
+{
+	pr_info("ssv6xxx_sdio_exit\n");
+	sdio_unregister_driver(&ssv6xxx_sdio_driver);
+}
+
+EXPORT_SYMBOL(ssv6xxx_sdio_init);
+EXPORT_SYMBOL(ssv6xxx_sdio_exit);
diff --git a/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h b/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
new file mode 100644
index 00000000000..57aefd3bf9f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SDIO_DEF_H_
+#define _SDIO_DEF_H_
+#include <linux/scatterlist.h>
+#define BASE_SDIO 0
+#define REG_DATA_IO_PORT_0 (BASE_SDIO + 0x00)
+#define REG_DATA_IO_PORT_1 (BASE_SDIO + 0x01)
+#define REG_DATA_IO_PORT_2 (BASE_SDIO + 0x02)
+#define REG_INT_MASK (BASE_SDIO + 0x04)
+#define REG_INT_STATUS (BASE_SDIO + 0x08)
+#define REG_INT_TRIGGER (BASE_SDIO + 0x09)
+#define REG_Fn1_STATUS (BASE_SDIO + 0x0c)
+#define REG_CARD_PKT_LEN_0 (BASE_SDIO + 0x10)
+#define REG_CARD_PKT_LEN_1 (BASE_SDIO + 0x11)
+#define REG_CARD_FW_DL_STATUS (BASE_SDIO + 0x12)
+#define REG_CARD_SELF_TEST (BASE_SDIO + 0x13)
+#define REG_CARD_RCA_0 (BASE_SDIO + 0x20)
+#define REG_CARD_RCA_1 (BASE_SDIO + 0x21)
+#define REG_SDIO_FIFO_WR_THLD_0 (BASE_SDIO + 0x24)
+#define REG_SDIO_FIFO_WR_THLD_1 (BASE_SDIO + 0x25)
+#define REG_OUTPUT_TIMING_REG (BASE_SDIO + 0x55)
+#define REG_PMU_WAKEUP (BASE_SDIO + 0x67)
+#define REG_REG_IO_PORT_0 (BASE_SDIO + 0x70)
+#define REG_REG_IO_PORT_1 (BASE_SDIO + 0x71)
+#define REG_REG_IO_PORT_2 (BASE_SDIO + 0x72)
+#define REG_SDIO_TX_ALLOC_SIZE (BASE_SDIO + 0x98)
+#define REG_SDIO_TX_ALLOC_SHIFT (BASE_SDIO + 0x99)
+#define REG_SDIO_TX_ALLOC_STATE (BASE_SDIO + 0x9a)
+#define REG_SDIO_TX_INFORM_0 (BASE_SDIO + 0x9c)
+#define REG_SDIO_TX_INFORM_1 (BASE_SDIO + 0x9d)
+#define REG_SDIO_TX_INFORM_2 (BASE_SDIO + 0x9e)
+#define SDIO_DEF_BLOCK_SIZE 0x80
+#if (SDIO_DEF_BLOCK_SIZE % 8)
+#error Wrong SDIO_DEF_BLOCK_SIZE value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
+#endif
+#define SDIO_DEF_OUTPUT_TIMING 0
+#define SDIO_DEF_BLOCK_MODE_THRD 128
+#if (SDIO_DEF_BLOCK_MODE_THRD % 8)
+#error Wrong SDIO_DEF_BLOCK_MODE_THRD value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
+#endif
+#define SDIO_DEF_FORCE_BLOCK_MODE 0
+#define MAX_SCATTER_ENTRIES_PER_REQ 8
+struct sdio_scatter_item {
+	u8 *buf;
+	int len;
+};
+struct sdio_scatter_req {
+	u32 req;
+	u32 len;
+	int scat_entries;
+	struct sdio_scatter_item scat_list[MAX_SCATTER_ENTRIES_PER_REQ];
+	struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];
+};
+#define SDIO_READ 0x00000001
+#define SDIO_WRITE 0x00000002
+#define CMD53_ARG_READ 0
+#define CMD53_ARG_WRITE 1
+#define CMD53_ARG_BLOCK_BASIS 1
+#define CMD53_ARG_FIXED_ADDRESS 0
+#define CMD53_ARG_INCR_ADDRESS 1
+#define SDIO_DMA_BUFFER_LEN 2048
+#ifdef CONFIG_PM
+#define SDIO_COMMAND_BUFFER_LEN 256
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/cabrio.h b/drivers/net/wireless/ssv6051/include/cabrio.h
new file mode 100644
index 00000000000..0b1327865c6
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/cabrio.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CABRIO_H
+#define CABRIO_H
+#define SSV_VENDOR_ID 0x3030
+#define SSV_CABRIO_DEVID 0x3030
+#define SSV_SUBVENDOR_ID_NOG 0x0e11
+#define SSV_SUBVENDOR_ID_NEW_A 0x7065
+#define SSV_CABRIO_MAGIC 0x19641014
+#define SSV_AMPDU_LIMIT_MAX (64 * 1024 - 1)
+#define SSV_DEFAULT_NOISE_FLOOR -95
+#define SSVCABRIO_RSSI_BAD -128
+#define SSVCABRIO_NUM_CHANNELS 38
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200.h b/drivers/net/wireless/ssv6051/include/ssv6200.h
new file mode 100644
index 00000000000..22eaceaf285
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV6200_H_
+#define _SSV6200_H_
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <net/mac80211.h>
+#ifdef ECLIPSE
+#include <ssv_mod_conf.h>
+#endif
+#include <ssv6200_reg.h>
+#include <ssv6200_aux.h>
+#include <hwif/hwif.h>
+#include <hci/ssv_hci.h>
+#include "ssv6200_common.h"
+#define SSV6200_TOTAL_ID 128
+#ifndef HUW_DRV
+#define SSV6200_ID_TX_THRESHOLD 19
+#define SSV6200_ID_RX_THRESHOLD 60
+#define SSV6200_PAGE_TX_THRESHOLD 115
+#define SSV6200_PAGE_RX_THRESHOLD 115
+#define SSV6XXX_AMPDU_DIVIDER (2)
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6200_PAGE_TX_THRESHOLD - (SSV6200_PAGE_TX_THRESHOLD/SSV6XXX_AMPDU_DIVIDER))
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#else
+#undef SSV6200_ID_TX_THRESHOLD
+#undef SSV6200_ID_RX_THRESHOLD
+#undef SSV6200_PAGE_TX_THRESHOLD
+#undef SSV6200_PAGE_RX_THRESHOLD
+#undef SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER
+#undef SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER
+#define SSV6200_ID_TX_THRESHOLD 31
+#define SSV6200_ID_RX_THRESHOLD 31
+#define SSV6200_PAGE_TX_THRESHOLD 61
+#define SSV6200_PAGE_RX_THRESHOLD 61
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER 45
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#endif
+#define SSV6200_ID_NUMBER (128)
+#define PACKET_ADDR_2_ID(addr) ((addr >> 16) & 0x7F)
+#define SSV6200_ID_AC_RESERVED 1
+#define SSV6200_ID_AC_BK_OUT_QUEUE 8
+#define SSV6200_ID_AC_BE_OUT_QUEUE 15
+#define SSV6200_ID_AC_VI_OUT_QUEUE 16
+#define SSV6200_ID_AC_VO_OUT_QUEUE 16
+#define SSV6200_ID_MANAGER_QUEUE 8
+#define HW_MMU_PAGE_SHIFT 0x8
+#define HW_MMU_PAGE_MASK 0xff
+#define SSV6200_BT_PRI_SMP_TIME 0
+#define SSV6200_BT_STA_SMP_TIME (SSV6200_BT_PRI_SMP_TIME+0)
+#define SSV6200_WLAN_REMAIN_TIME 0
+#define BT_2WIRE_EN_MSK 0x00000400
+struct txResourceControl {
+	u32 txUsePage:8;
+	u32 txUseID:6;
+	u32 edca0:4;
+	u32 edca1:4;
+	u32 edca2:5;
+	u32 edca3:5;
+};
+#include <ssv_cfg.h>
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_aux.h b/drivers/net/wireless/ssv6051/include/ssv6200_aux.h
new file mode 100644
index 00000000000..03ec3f07d33
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200_aux.h
@@ -0,0 +1,18221 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define MCU_ENABLE_MSK 0x00000001
+#define MCU_ENABLE_I_MSK 0xfffffffe
+#define MCU_ENABLE_SFT 0
+#define MCU_ENABLE_HI 0
+#define MCU_ENABLE_SZ 1
+#define MAC_SW_RST_MSK 0x00000002
+#define MAC_SW_RST_I_MSK 0xfffffffd
+#define MAC_SW_RST_SFT 1
+#define MAC_SW_RST_HI 1
+#define MAC_SW_RST_SZ 1
+#define MCU_SW_RST_MSK 0x00000004
+#define MCU_SW_RST_I_MSK 0xfffffffb
+#define MCU_SW_RST_SFT 2
+#define MCU_SW_RST_HI 2
+#define MCU_SW_RST_SZ 1
+#define SDIO_SW_RST_MSK 0x00000008
+#define SDIO_SW_RST_I_MSK 0xfffffff7
+#define SDIO_SW_RST_SFT 3
+#define SDIO_SW_RST_HI 3
+#define SDIO_SW_RST_SZ 1
+#define SPI_SLV_SW_RST_MSK 0x00000010
+#define SPI_SLV_SW_RST_I_MSK 0xffffffef
+#define SPI_SLV_SW_RST_SFT 4
+#define SPI_SLV_SW_RST_HI 4
+#define SPI_SLV_SW_RST_SZ 1
+#define UART_SW_RST_MSK 0x00000020
+#define UART_SW_RST_I_MSK 0xffffffdf
+#define UART_SW_RST_SFT 5
+#define UART_SW_RST_HI 5
+#define UART_SW_RST_SZ 1
+#define DMA_SW_RST_MSK 0x00000040
+#define DMA_SW_RST_I_MSK 0xffffffbf
+#define DMA_SW_RST_SFT 6
+#define DMA_SW_RST_HI 6
+#define DMA_SW_RST_SZ 1
+#define WDT_SW_RST_MSK 0x00000080
+#define WDT_SW_RST_I_MSK 0xffffff7f
+#define WDT_SW_RST_SFT 7
+#define WDT_SW_RST_HI 7
+#define WDT_SW_RST_SZ 1
+#define I2C_SLV_SW_RST_MSK 0x00000100
+#define I2C_SLV_SW_RST_I_MSK 0xfffffeff
+#define I2C_SLV_SW_RST_SFT 8
+#define I2C_SLV_SW_RST_HI 8
+#define I2C_SLV_SW_RST_SZ 1
+#define INT_CTL_SW_RST_MSK 0x00000200
+#define INT_CTL_SW_RST_I_MSK 0xfffffdff
+#define INT_CTL_SW_RST_SFT 9
+#define INT_CTL_SW_RST_HI 9
+#define INT_CTL_SW_RST_SZ 1
+#define BTCX_SW_RST_MSK 0x00000400
+#define BTCX_SW_RST_I_MSK 0xfffffbff
+#define BTCX_SW_RST_SFT 10
+#define BTCX_SW_RST_HI 10
+#define BTCX_SW_RST_SZ 1
+#define GPIO_SW_RST_MSK 0x00000800
+#define GPIO_SW_RST_I_MSK 0xfffff7ff
+#define GPIO_SW_RST_SFT 11
+#define GPIO_SW_RST_HI 11
+#define GPIO_SW_RST_SZ 1
+#define US0TMR_SW_RST_MSK 0x00001000
+#define US0TMR_SW_RST_I_MSK 0xffffefff
+#define US0TMR_SW_RST_SFT 12
+#define US0TMR_SW_RST_HI 12
+#define US0TMR_SW_RST_SZ 1
+#define US1TMR_SW_RST_MSK 0x00002000
+#define US1TMR_SW_RST_I_MSK 0xffffdfff
+#define US1TMR_SW_RST_SFT 13
+#define US1TMR_SW_RST_HI 13
+#define US1TMR_SW_RST_SZ 1
+#define US2TMR_SW_RST_MSK 0x00004000
+#define US2TMR_SW_RST_I_MSK 0xffffbfff
+#define US2TMR_SW_RST_SFT 14
+#define US2TMR_SW_RST_HI 14
+#define US2TMR_SW_RST_SZ 1
+#define US3TMR_SW_RST_MSK 0x00008000
+#define US3TMR_SW_RST_I_MSK 0xffff7fff
+#define US3TMR_SW_RST_SFT 15
+#define US3TMR_SW_RST_HI 15
+#define US3TMR_SW_RST_SZ 1
+#define MS0TMR_SW_RST_MSK 0x00010000
+#define MS0TMR_SW_RST_I_MSK 0xfffeffff
+#define MS0TMR_SW_RST_SFT 16
+#define MS0TMR_SW_RST_HI 16
+#define MS0TMR_SW_RST_SZ 1
+#define MS1TMR_SW_RST_MSK 0x00020000
+#define MS1TMR_SW_RST_I_MSK 0xfffdffff
+#define MS1TMR_SW_RST_SFT 17
+#define MS1TMR_SW_RST_HI 17
+#define MS1TMR_SW_RST_SZ 1
+#define MS2TMR_SW_RST_MSK 0x00040000
+#define MS2TMR_SW_RST_I_MSK 0xfffbffff
+#define MS2TMR_SW_RST_SFT 18
+#define MS2TMR_SW_RST_HI 18
+#define MS2TMR_SW_RST_SZ 1
+#define MS3TMR_SW_RST_MSK 0x00080000
+#define MS3TMR_SW_RST_I_MSK 0xfff7ffff
+#define MS3TMR_SW_RST_SFT 19
+#define MS3TMR_SW_RST_HI 19
+#define MS3TMR_SW_RST_SZ 1
+#define RF_BB_SW_RST_MSK 0x00100000
+#define RF_BB_SW_RST_I_MSK 0xffefffff
+#define RF_BB_SW_RST_SFT 20
+#define RF_BB_SW_RST_HI 20
+#define RF_BB_SW_RST_SZ 1
+#define SYS_ALL_RST_MSK 0x00200000
+#define SYS_ALL_RST_I_MSK 0xffdfffff
+#define SYS_ALL_RST_SFT 21
+#define SYS_ALL_RST_HI 21
+#define SYS_ALL_RST_SZ 1
+#define DAT_UART_SW_RST_MSK 0x00400000
+#define DAT_UART_SW_RST_I_MSK 0xffbfffff
+#define DAT_UART_SW_RST_SFT 22
+#define DAT_UART_SW_RST_HI 22
+#define DAT_UART_SW_RST_SZ 1
+#define I2C_MST_SW_RST_MSK 0x00800000
+#define I2C_MST_SW_RST_I_MSK 0xff7fffff
+#define I2C_MST_SW_RST_SFT 23
+#define I2C_MST_SW_RST_HI 23
+#define I2C_MST_SW_RST_SZ 1
+#define RG_REBOOT_MSK 0x00000001
+#define RG_REBOOT_I_MSK 0xfffffffe
+#define RG_REBOOT_SFT 0
+#define RG_REBOOT_HI 0
+#define RG_REBOOT_SZ 1
+#define TRAP_IMG_FLS_MSK 0x00010000
+#define TRAP_IMG_FLS_I_MSK 0xfffeffff
+#define TRAP_IMG_FLS_SFT 16
+#define TRAP_IMG_FLS_HI 16
+#define TRAP_IMG_FLS_SZ 1
+#define TRAP_REBOOT_MSK 0x00020000
+#define TRAP_REBOOT_I_MSK 0xfffdffff
+#define TRAP_REBOOT_SFT 17
+#define TRAP_REBOOT_HI 17
+#define TRAP_REBOOT_SZ 1
+#define TRAP_BOOT_FLS_MSK 0x00040000
+#define TRAP_BOOT_FLS_I_MSK 0xfffbffff
+#define TRAP_BOOT_FLS_SFT 18
+#define TRAP_BOOT_FLS_HI 18
+#define TRAP_BOOT_FLS_SZ 1
+#define CHIP_ID_31_0_MSK 0xffffffff
+#define CHIP_ID_31_0_I_MSK 0x00000000
+#define CHIP_ID_31_0_SFT 0
+#define CHIP_ID_31_0_HI 31
+#define CHIP_ID_31_0_SZ 32
+#define CHIP_ID_63_32_MSK 0xffffffff
+#define CHIP_ID_63_32_I_MSK 0x00000000
+#define CHIP_ID_63_32_SFT 0
+#define CHIP_ID_63_32_HI 31
+#define CHIP_ID_63_32_SZ 32
+#define CHIP_ID_95_64_MSK 0xffffffff
+#define CHIP_ID_95_64_I_MSK 0x00000000
+#define CHIP_ID_95_64_SFT 0
+#define CHIP_ID_95_64_HI 31
+#define CHIP_ID_95_64_SZ 32
+#define CHIP_ID_127_96_MSK 0xffffffff
+#define CHIP_ID_127_96_I_MSK 0x00000000
+#define CHIP_ID_127_96_SFT 0
+#define CHIP_ID_127_96_HI 31
+#define CHIP_ID_127_96_SZ 32
+#define CK_SEL_1_0_MSK 0x00000003
+#define CK_SEL_1_0_I_MSK 0xfffffffc
+#define CK_SEL_1_0_SFT 0
+#define CK_SEL_1_0_HI 1
+#define CK_SEL_1_0_SZ 2
+#define CK_SEL_2_MSK 0x00000004
+#define CK_SEL_2_I_MSK 0xfffffffb
+#define CK_SEL_2_SFT 2
+#define CK_SEL_2_HI 2
+#define CK_SEL_2_SZ 1
+#define SYS_CLK_EN_MSK 0x00000001
+#define SYS_CLK_EN_I_MSK 0xfffffffe
+#define SYS_CLK_EN_SFT 0
+#define SYS_CLK_EN_HI 0
+#define SYS_CLK_EN_SZ 1
+#define MAC_CLK_EN_MSK 0x00000002
+#define MAC_CLK_EN_I_MSK 0xfffffffd
+#define MAC_CLK_EN_SFT 1
+#define MAC_CLK_EN_HI 1
+#define MAC_CLK_EN_SZ 1
+#define MCU_CLK_EN_MSK 0x00000004
+#define MCU_CLK_EN_I_MSK 0xfffffffb
+#define MCU_CLK_EN_SFT 2
+#define MCU_CLK_EN_HI 2
+#define MCU_CLK_EN_SZ 1
+#define SDIO_CLK_EN_MSK 0x00000008
+#define SDIO_CLK_EN_I_MSK 0xfffffff7
+#define SDIO_CLK_EN_SFT 3
+#define SDIO_CLK_EN_HI 3
+#define SDIO_CLK_EN_SZ 1
+#define SPI_SLV_CLK_EN_MSK 0x00000010
+#define SPI_SLV_CLK_EN_I_MSK 0xffffffef
+#define SPI_SLV_CLK_EN_SFT 4
+#define SPI_SLV_CLK_EN_HI 4
+#define SPI_SLV_CLK_EN_SZ 1
+#define UART_CLK_EN_MSK 0x00000020
+#define UART_CLK_EN_I_MSK 0xffffffdf
+#define UART_CLK_EN_SFT 5
+#define UART_CLK_EN_HI 5
+#define UART_CLK_EN_SZ 1
+#define DMA_CLK_EN_MSK 0x00000040
+#define DMA_CLK_EN_I_MSK 0xffffffbf
+#define DMA_CLK_EN_SFT 6
+#define DMA_CLK_EN_HI 6
+#define DMA_CLK_EN_SZ 1
+#define WDT_CLK_EN_MSK 0x00000080
+#define WDT_CLK_EN_I_MSK 0xffffff7f
+#define WDT_CLK_EN_SFT 7
+#define WDT_CLK_EN_HI 7
+#define WDT_CLK_EN_SZ 1
+#define I2C_SLV_CLK_EN_MSK 0x00000100
+#define I2C_SLV_CLK_EN_I_MSK 0xfffffeff
+#define I2C_SLV_CLK_EN_SFT 8
+#define I2C_SLV_CLK_EN_HI 8
+#define I2C_SLV_CLK_EN_SZ 1
+#define INT_CTL_CLK_EN_MSK 0x00000200
+#define INT_CTL_CLK_EN_I_MSK 0xfffffdff
+#define INT_CTL_CLK_EN_SFT 9
+#define INT_CTL_CLK_EN_HI 9
+#define INT_CTL_CLK_EN_SZ 1
+#define BTCX_CLK_EN_MSK 0x00000400
+#define BTCX_CLK_EN_I_MSK 0xfffffbff
+#define BTCX_CLK_EN_SFT 10
+#define BTCX_CLK_EN_HI 10
+#define BTCX_CLK_EN_SZ 1
+#define GPIO_CLK_EN_MSK 0x00000800
+#define GPIO_CLK_EN_I_MSK 0xfffff7ff
+#define GPIO_CLK_EN_SFT 11
+#define GPIO_CLK_EN_HI 11
+#define GPIO_CLK_EN_SZ 1
+#define US0TMR_CLK_EN_MSK 0x00001000
+#define US0TMR_CLK_EN_I_MSK 0xffffefff
+#define US0TMR_CLK_EN_SFT 12
+#define US0TMR_CLK_EN_HI 12
+#define US0TMR_CLK_EN_SZ 1
+#define US1TMR_CLK_EN_MSK 0x00002000
+#define US1TMR_CLK_EN_I_MSK 0xffffdfff
+#define US1TMR_CLK_EN_SFT 13
+#define US1TMR_CLK_EN_HI 13
+#define US1TMR_CLK_EN_SZ 1
+#define US2TMR_CLK_EN_MSK 0x00004000
+#define US2TMR_CLK_EN_I_MSK 0xffffbfff
+#define US2TMR_CLK_EN_SFT 14
+#define US2TMR_CLK_EN_HI 14
+#define US2TMR_CLK_EN_SZ 1
+#define US3TMR_CLK_EN_MSK 0x00008000
+#define US3TMR_CLK_EN_I_MSK 0xffff7fff
+#define US3TMR_CLK_EN_SFT 15
+#define US3TMR_CLK_EN_HI 15
+#define US3TMR_CLK_EN_SZ 1
+#define MS0TMR_CLK_EN_MSK 0x00010000
+#define MS0TMR_CLK_EN_I_MSK 0xfffeffff
+#define MS0TMR_CLK_EN_SFT 16
+#define MS0TMR_CLK_EN_HI 16
+#define MS0TMR_CLK_EN_SZ 1
+#define MS1TMR_CLK_EN_MSK 0x00020000
+#define MS1TMR_CLK_EN_I_MSK 0xfffdffff
+#define MS1TMR_CLK_EN_SFT 17
+#define MS1TMR_CLK_EN_HI 17
+#define MS1TMR_CLK_EN_SZ 1
+#define MS2TMR_CLK_EN_MSK 0x00040000
+#define MS2TMR_CLK_EN_I_MSK 0xfffbffff
+#define MS2TMR_CLK_EN_SFT 18
+#define MS2TMR_CLK_EN_HI 18
+#define MS2TMR_CLK_EN_SZ 1
+#define MS3TMR_CLK_EN_MSK 0x00080000
+#define MS3TMR_CLK_EN_I_MSK 0xfff7ffff
+#define MS3TMR_CLK_EN_SFT 19
+#define MS3TMR_CLK_EN_HI 19
+#define MS3TMR_CLK_EN_SZ 1
+#define BIST_CLK_EN_MSK 0x00100000
+#define BIST_CLK_EN_I_MSK 0xffefffff
+#define BIST_CLK_EN_SFT 20
+#define BIST_CLK_EN_HI 20
+#define BIST_CLK_EN_SZ 1
+#define I2C_MST_CLK_EN_MSK 0x00800000
+#define I2C_MST_CLK_EN_I_MSK 0xff7fffff
+#define I2C_MST_CLK_EN_SFT 23
+#define I2C_MST_CLK_EN_HI 23
+#define I2C_MST_CLK_EN_SZ 1
+#define BTCX_CSR_CLK_EN_MSK 0x00000400
+#define BTCX_CSR_CLK_EN_I_MSK 0xfffffbff
+#define BTCX_CSR_CLK_EN_SFT 10
+#define BTCX_CSR_CLK_EN_HI 10
+#define BTCX_CSR_CLK_EN_SZ 1
+#define MCU_DBG_SEL_MSK 0x0000003f
+#define MCU_DBG_SEL_I_MSK 0xffffffc0
+#define MCU_DBG_SEL_SFT 0
+#define MCU_DBG_SEL_HI 5
+#define MCU_DBG_SEL_SZ 6
+#define MCU_STOP_NOGRANT_MSK 0x00000100
+#define MCU_STOP_NOGRANT_I_MSK 0xfffffeff
+#define MCU_STOP_NOGRANT_SFT 8
+#define MCU_STOP_NOGRANT_HI 8
+#define MCU_STOP_NOGRANT_SZ 1
+#define MCU_STOP_ANYTIME_MSK 0x00000200
+#define MCU_STOP_ANYTIME_I_MSK 0xfffffdff
+#define MCU_STOP_ANYTIME_SFT 9
+#define MCU_STOP_ANYTIME_HI 9
+#define MCU_STOP_ANYTIME_SZ 1
+#define MCU_DBG_DATA_MSK 0xffffffff
+#define MCU_DBG_DATA_I_MSK 0x00000000
+#define MCU_DBG_DATA_SFT 0
+#define MCU_DBG_DATA_HI 31
+#define MCU_DBG_DATA_SZ 32
+#define AHB_SW_RST_MSK 0x00000001
+#define AHB_SW_RST_I_MSK 0xfffffffe
+#define AHB_SW_RST_SFT 0
+#define AHB_SW_RST_HI 0
+#define AHB_SW_RST_SZ 1
+#define AHB_ERR_RST_MSK 0x00000002
+#define AHB_ERR_RST_I_MSK 0xfffffffd
+#define AHB_ERR_RST_SFT 1
+#define AHB_ERR_RST_HI 1
+#define AHB_ERR_RST_SZ 1
+#define REG_AHB_DEBUG_MX_MSK 0x00000030
+#define REG_AHB_DEBUG_MX_I_MSK 0xffffffcf
+#define REG_AHB_DEBUG_MX_SFT 4
+#define REG_AHB_DEBUG_MX_HI 5
+#define REG_AHB_DEBUG_MX_SZ 2
+#define REG_PKT_W_NBRT_MSK 0x00000100
+#define REG_PKT_W_NBRT_I_MSK 0xfffffeff
+#define REG_PKT_W_NBRT_SFT 8
+#define REG_PKT_W_NBRT_HI 8
+#define REG_PKT_W_NBRT_SZ 1
+#define REG_PKT_R_NBRT_MSK 0x00000200
+#define REG_PKT_R_NBRT_I_MSK 0xfffffdff
+#define REG_PKT_R_NBRT_SFT 9
+#define REG_PKT_R_NBRT_HI 9
+#define REG_PKT_R_NBRT_SZ 1
+#define IQ_SRAM_SEL_0_MSK 0x00001000
+#define IQ_SRAM_SEL_0_I_MSK 0xffffefff
+#define IQ_SRAM_SEL_0_SFT 12
+#define IQ_SRAM_SEL_0_HI 12
+#define IQ_SRAM_SEL_0_SZ 1
+#define IQ_SRAM_SEL_1_MSK 0x00002000
+#define IQ_SRAM_SEL_1_I_MSK 0xffffdfff
+#define IQ_SRAM_SEL_1_SFT 13
+#define IQ_SRAM_SEL_1_HI 13
+#define IQ_SRAM_SEL_1_SZ 1
+#define IQ_SRAM_SEL_2_MSK 0x00004000
+#define IQ_SRAM_SEL_2_I_MSK 0xffffbfff
+#define IQ_SRAM_SEL_2_SFT 14
+#define IQ_SRAM_SEL_2_HI 14
+#define IQ_SRAM_SEL_2_SZ 1
+#define AHB_STATUS_MSK 0xffff0000
+#define AHB_STATUS_I_MSK 0x0000ffff
+#define AHB_STATUS_SFT 16
+#define AHB_STATUS_HI 31
+#define AHB_STATUS_SZ 16
+#define PARALLEL_DR_MSK 0x00000001
+#define PARALLEL_DR_I_MSK 0xfffffffe
+#define PARALLEL_DR_SFT 0
+#define PARALLEL_DR_HI 0
+#define PARALLEL_DR_SZ 1
+#define MBRUN_MSK 0x00000010
+#define MBRUN_I_MSK 0xffffffef
+#define MBRUN_SFT 4
+#define MBRUN_HI 4
+#define MBRUN_SZ 1
+#define SHIFT_DR_MSK 0x00000100
+#define SHIFT_DR_I_MSK 0xfffffeff
+#define SHIFT_DR_SFT 8
+#define SHIFT_DR_HI 8
+#define SHIFT_DR_SZ 1
+#define MODE_REG_SI_MSK 0x00000200
+#define MODE_REG_SI_I_MSK 0xfffffdff
+#define MODE_REG_SI_SFT 9
+#define MODE_REG_SI_HI 9
+#define MODE_REG_SI_SZ 1
+#define SIMULATION_MODE_MSK 0x00000400
+#define SIMULATION_MODE_I_MSK 0xfffffbff
+#define SIMULATION_MODE_SFT 10
+#define SIMULATION_MODE_HI 10
+#define SIMULATION_MODE_SZ 1
+#define DBIST_MODE_MSK 0x00000800
+#define DBIST_MODE_I_MSK 0xfffff7ff
+#define DBIST_MODE_SFT 11
+#define DBIST_MODE_HI 11
+#define DBIST_MODE_SZ 1
+#define MODE_REG_IN_MSK 0x001fffff
+#define MODE_REG_IN_I_MSK 0xffe00000
+#define MODE_REG_IN_SFT 0
+#define MODE_REG_IN_HI 20
+#define MODE_REG_IN_SZ 21
+#define MODE_REG_OUT_MCU_MSK 0x001fffff
+#define MODE_REG_OUT_MCU_I_MSK 0xffe00000
+#define MODE_REG_OUT_MCU_SFT 0
+#define MODE_REG_OUT_MCU_HI 20
+#define MODE_REG_OUT_MCU_SZ 21
+#define MODE_REG_SO_MCU_MSK 0x80000000
+#define MODE_REG_SO_MCU_I_MSK 0x7fffffff
+#define MODE_REG_SO_MCU_SFT 31
+#define MODE_REG_SO_MCU_HI 31
+#define MODE_REG_SO_MCU_SZ 1
+#define MONITOR_BUS_MCU_31_0_MSK 0xffffffff
+#define MONITOR_BUS_MCU_31_0_I_MSK 0x00000000
+#define MONITOR_BUS_MCU_31_0_SFT 0
+#define MONITOR_BUS_MCU_31_0_HI 31
+#define MONITOR_BUS_MCU_31_0_SZ 32
+#define MONITOR_BUS_MCU_33_32_MSK 0x00000003
+#define MONITOR_BUS_MCU_33_32_I_MSK 0xfffffffc
+#define MONITOR_BUS_MCU_33_32_SFT 0
+#define MONITOR_BUS_MCU_33_32_HI 1
+#define MONITOR_BUS_MCU_33_32_SZ 2
+#define TB_ADR_SEL_MSK 0x0000ffff
+#define TB_ADR_SEL_I_MSK 0xffff0000
+#define TB_ADR_SEL_SFT 0
+#define TB_ADR_SEL_HI 15
+#define TB_ADR_SEL_SZ 16
+#define TB_CS_MSK 0x80000000
+#define TB_CS_I_MSK 0x7fffffff
+#define TB_CS_SFT 31
+#define TB_CS_HI 31
+#define TB_CS_SZ 1
+#define TB_RDATA_MSK 0xffffffff
+#define TB_RDATA_I_MSK 0x00000000
+#define TB_RDATA_SFT 0
+#define TB_RDATA_HI 31
+#define TB_RDATA_SZ 32
+#define UART_W2B_EN_MSK 0x00000001
+#define UART_W2B_EN_I_MSK 0xfffffffe
+#define UART_W2B_EN_SFT 0
+#define UART_W2B_EN_HI 0
+#define UART_W2B_EN_SZ 1
+#define DATA_UART_W2B_EN_MSK 0x00000010
+#define DATA_UART_W2B_EN_I_MSK 0xffffffef
+#define DATA_UART_W2B_EN_SFT 4
+#define DATA_UART_W2B_EN_HI 4
+#define DATA_UART_W2B_EN_SZ 1
+#define AHB_ILL_ADDR_MSK 0xffffffff
+#define AHB_ILL_ADDR_I_MSK 0x00000000
+#define AHB_ILL_ADDR_SFT 0
+#define AHB_ILL_ADDR_HI 31
+#define AHB_ILL_ADDR_SZ 32
+#define AHB_FEN_ADDR_MSK 0xffffffff
+#define AHB_FEN_ADDR_I_MSK 0x00000000
+#define AHB_FEN_ADDR_SFT 0
+#define AHB_FEN_ADDR_HI 31
+#define AHB_FEN_ADDR_SZ 32
+#define ILL_ADDR_CLR_MSK 0x00000001
+#define ILL_ADDR_CLR_I_MSK 0xfffffffe
+#define ILL_ADDR_CLR_SFT 0
+#define ILL_ADDR_CLR_HI 0
+#define ILL_ADDR_CLR_SZ 1
+#define FENCE_HIT_CLR_MSK 0x00000002
+#define FENCE_HIT_CLR_I_MSK 0xfffffffd
+#define FENCE_HIT_CLR_SFT 1
+#define FENCE_HIT_CLR_HI 1
+#define FENCE_HIT_CLR_SZ 1
+#define ILL_ADDR_INT_MSK 0x00000010
+#define ILL_ADDR_INT_I_MSK 0xffffffef
+#define ILL_ADDR_INT_SFT 4
+#define ILL_ADDR_INT_HI 4
+#define ILL_ADDR_INT_SZ 1
+#define FENCE_HIT_INT_MSK 0x00000020
+#define FENCE_HIT_INT_I_MSK 0xffffffdf
+#define FENCE_HIT_INT_SFT 5
+#define FENCE_HIT_INT_HI 5
+#define FENCE_HIT_INT_SZ 1
+#define PWM_INI_VALUE_P_A_MSK 0x000000ff
+#define PWM_INI_VALUE_P_A_I_MSK 0xffffff00
+#define PWM_INI_VALUE_P_A_SFT 0
+#define PWM_INI_VALUE_P_A_HI 7
+#define PWM_INI_VALUE_P_A_SZ 8
+#define PWM_INI_VALUE_N_A_MSK 0x0000ff00
+#define PWM_INI_VALUE_N_A_I_MSK 0xffff00ff
+#define PWM_INI_VALUE_N_A_SFT 8
+#define PWM_INI_VALUE_N_A_HI 15
+#define PWM_INI_VALUE_N_A_SZ 8
+#define PWM_POST_SCALER_A_MSK 0x000f0000
+#define PWM_POST_SCALER_A_I_MSK 0xfff0ffff
+#define PWM_POST_SCALER_A_SFT 16
+#define PWM_POST_SCALER_A_HI 19
+#define PWM_POST_SCALER_A_SZ 4
+#define PWM_ALWAYSON_A_MSK 0x20000000
+#define PWM_ALWAYSON_A_I_MSK 0xdfffffff
+#define PWM_ALWAYSON_A_SFT 29
+#define PWM_ALWAYSON_A_HI 29
+#define PWM_ALWAYSON_A_SZ 1
+#define PWM_INVERT_A_MSK 0x40000000
+#define PWM_INVERT_A_I_MSK 0xbfffffff
+#define PWM_INVERT_A_SFT 30
+#define PWM_INVERT_A_HI 30
+#define PWM_INVERT_A_SZ 1
+#define PWM_ENABLE_A_MSK 0x80000000
+#define PWM_ENABLE_A_I_MSK 0x7fffffff
+#define PWM_ENABLE_A_SFT 31
+#define PWM_ENABLE_A_HI 31
+#define PWM_ENABLE_A_SZ 1
+#define PWM_INI_VALUE_P_B_MSK 0x000000ff
+#define PWM_INI_VALUE_P_B_I_MSK 0xffffff00
+#define PWM_INI_VALUE_P_B_SFT 0
+#define PWM_INI_VALUE_P_B_HI 7
+#define PWM_INI_VALUE_P_B_SZ 8
+#define PWM_INI_VALUE_N_B_MSK 0x0000ff00
+#define PWM_INI_VALUE_N_B_I_MSK 0xffff00ff
+#define PWM_INI_VALUE_N_B_SFT 8
+#define PWM_INI_VALUE_N_B_HI 15
+#define PWM_INI_VALUE_N_B_SZ 8
+#define PWM_POST_SCALER_B_MSK 0x000f0000
+#define PWM_POST_SCALER_B_I_MSK 0xfff0ffff
+#define PWM_POST_SCALER_B_SFT 16
+#define PWM_POST_SCALER_B_HI 19
+#define PWM_POST_SCALER_B_SZ 4
+#define PWM_ALWAYSON_B_MSK 0x20000000
+#define PWM_ALWAYSON_B_I_MSK 0xdfffffff
+#define PWM_ALWAYSON_B_SFT 29
+#define PWM_ALWAYSON_B_HI 29
+#define PWM_ALWAYSON_B_SZ 1
+#define PWM_INVERT_B_MSK 0x40000000
+#define PWM_INVERT_B_I_MSK 0xbfffffff
+#define PWM_INVERT_B_SFT 30
+#define PWM_INVERT_B_HI 30
+#define PWM_INVERT_B_SZ 1
+#define PWM_ENABLE_B_MSK 0x80000000
+#define PWM_ENABLE_B_I_MSK 0x7fffffff
+#define PWM_ENABLE_B_SFT 31
+#define PWM_ENABLE_B_HI 31
+#define PWM_ENABLE_B_SZ 1
+#define HBUSREQ_LOCK_MSK 0x00001fff
+#define HBUSREQ_LOCK_I_MSK 0xffffe000
+#define HBUSREQ_LOCK_SFT 0
+#define HBUSREQ_LOCK_HI 12
+#define HBUSREQ_LOCK_SZ 13
+#define HBURST_LOCK_MSK 0x00001fff
+#define HBURST_LOCK_I_MSK 0xffffe000
+#define HBURST_LOCK_SFT 0
+#define HBURST_LOCK_HI 12
+#define HBURST_LOCK_SZ 13
+#define PRESCALER_USTIMER_MSK 0x000001ff
+#define PRESCALER_USTIMER_I_MSK 0xfffffe00
+#define PRESCALER_USTIMER_SFT 0
+#define PRESCALER_USTIMER_HI 8
+#define PRESCALER_USTIMER_SZ 9
+#define MODE_REG_IN_MMU_MSK 0x0000ffff
+#define MODE_REG_IN_MMU_I_MSK 0xffff0000
+#define MODE_REG_IN_MMU_SFT 0
+#define MODE_REG_IN_MMU_HI 15
+#define MODE_REG_IN_MMU_SZ 16
+#define MODE_REG_OUT_MMU_MSK 0x0000ffff
+#define MODE_REG_OUT_MMU_I_MSK 0xffff0000
+#define MODE_REG_OUT_MMU_SFT 0
+#define MODE_REG_OUT_MMU_HI 15
+#define MODE_REG_OUT_MMU_SZ 16
+#define MODE_REG_SO_MMU_MSK 0x80000000
+#define MODE_REG_SO_MMU_I_MSK 0x7fffffff
+#define MODE_REG_SO_MMU_SFT 31
+#define MODE_REG_SO_MMU_HI 31
+#define MODE_REG_SO_MMU_SZ 1
+#define MONITOR_BUS_MMU_MSK 0x0007ffff
+#define MONITOR_BUS_MMU_I_MSK 0xfff80000
+#define MONITOR_BUS_MMU_SFT 0
+#define MONITOR_BUS_MMU_HI 18
+#define MONITOR_BUS_MMU_SZ 19
+#define TEST_MODE0_MSK 0x00000001
+#define TEST_MODE0_I_MSK 0xfffffffe
+#define TEST_MODE0_SFT 0
+#define TEST_MODE0_HI 0
+#define TEST_MODE0_SZ 1
+#define TEST_MODE1_MSK 0x00000002
+#define TEST_MODE1_I_MSK 0xfffffffd
+#define TEST_MODE1_SFT 1
+#define TEST_MODE1_HI 1
+#define TEST_MODE1_SZ 1
+#define TEST_MODE2_MSK 0x00000004
+#define TEST_MODE2_I_MSK 0xfffffffb
+#define TEST_MODE2_SFT 2
+#define TEST_MODE2_HI 2
+#define TEST_MODE2_SZ 1
+#define TEST_MODE3_MSK 0x00000008
+#define TEST_MODE3_I_MSK 0xfffffff7
+#define TEST_MODE3_SFT 3
+#define TEST_MODE3_HI 3
+#define TEST_MODE3_SZ 1
+#define TEST_MODE4_MSK 0x00000010
+#define TEST_MODE4_I_MSK 0xffffffef
+#define TEST_MODE4_SFT 4
+#define TEST_MODE4_HI 4
+#define TEST_MODE4_SZ 1
+#define TEST_MODE_ALL_MSK 0x00000020
+#define TEST_MODE_ALL_I_MSK 0xffffffdf
+#define TEST_MODE_ALL_SFT 5
+#define TEST_MODE_ALL_HI 5
+#define TEST_MODE_ALL_SZ 1
+#define WDT_INIT_MSK 0x00000001
+#define WDT_INIT_I_MSK 0xfffffffe
+#define WDT_INIT_SFT 0
+#define WDT_INIT_HI 0
+#define WDT_INIT_SZ 1
+#define SD_HOST_INIT_MSK 0x00000002
+#define SD_HOST_INIT_I_MSK 0xfffffffd
+#define SD_HOST_INIT_SFT 1
+#define SD_HOST_INIT_HI 1
+#define SD_HOST_INIT_SZ 1
+#define ALLOW_SD_RESET_MSK 0x00000001
+#define ALLOW_SD_RESET_I_MSK 0xfffffffe
+#define ALLOW_SD_RESET_SFT 0
+#define ALLOW_SD_RESET_HI 0
+#define ALLOW_SD_RESET_SZ 1
+#define UART_NRTS_MSK 0x00000001
+#define UART_NRTS_I_MSK 0xfffffffe
+#define UART_NRTS_SFT 0
+#define UART_NRTS_HI 0
+#define UART_NRTS_SZ 1
+#define UART_NCTS_MSK 0x00000002
+#define UART_NCTS_I_MSK 0xfffffffd
+#define UART_NCTS_SFT 1
+#define UART_NCTS_HI 1
+#define UART_NCTS_SZ 1
+#define TU0_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU0_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU0_TM_INIT_VALUE_SFT 0
+#define TU0_TM_INIT_VALUE_HI 15
+#define TU0_TM_INIT_VALUE_SZ 16
+#define TU0_TM_MODE_MSK 0x00010000
+#define TU0_TM_MODE_I_MSK 0xfffeffff
+#define TU0_TM_MODE_SFT 16
+#define TU0_TM_MODE_HI 16
+#define TU0_TM_MODE_SZ 1
+#define TU0_TM_INT_STS_DONE_MSK 0x00020000
+#define TU0_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU0_TM_INT_STS_DONE_SFT 17
+#define TU0_TM_INT_STS_DONE_HI 17
+#define TU0_TM_INT_STS_DONE_SZ 1
+#define TU0_TM_INT_MASK_MSK 0x00040000
+#define TU0_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU0_TM_INT_MASK_SFT 18
+#define TU0_TM_INT_MASK_HI 18
+#define TU0_TM_INT_MASK_SZ 1
+#define TU0_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU0_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU0_TM_CUR_VALUE_SFT 0
+#define TU0_TM_CUR_VALUE_HI 15
+#define TU0_TM_CUR_VALUE_SZ 16
+#define TU1_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU1_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU1_TM_INIT_VALUE_SFT 0
+#define TU1_TM_INIT_VALUE_HI 15
+#define TU1_TM_INIT_VALUE_SZ 16
+#define TU1_TM_MODE_MSK 0x00010000
+#define TU1_TM_MODE_I_MSK 0xfffeffff
+#define TU1_TM_MODE_SFT 16
+#define TU1_TM_MODE_HI 16
+#define TU1_TM_MODE_SZ 1
+#define TU1_TM_INT_STS_DONE_MSK 0x00020000
+#define TU1_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU1_TM_INT_STS_DONE_SFT 17
+#define TU1_TM_INT_STS_DONE_HI 17
+#define TU1_TM_INT_STS_DONE_SZ 1
+#define TU1_TM_INT_MASK_MSK 0x00040000
+#define TU1_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU1_TM_INT_MASK_SFT 18
+#define TU1_TM_INT_MASK_HI 18
+#define TU1_TM_INT_MASK_SZ 1
+#define TU1_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU1_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU1_TM_CUR_VALUE_SFT 0
+#define TU1_TM_CUR_VALUE_HI 15
+#define TU1_TM_CUR_VALUE_SZ 16
+#define TU2_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU2_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU2_TM_INIT_VALUE_SFT 0
+#define TU2_TM_INIT_VALUE_HI 15
+#define TU2_TM_INIT_VALUE_SZ 16
+#define TU2_TM_MODE_MSK 0x00010000
+#define TU2_TM_MODE_I_MSK 0xfffeffff
+#define TU2_TM_MODE_SFT 16
+#define TU2_TM_MODE_HI 16
+#define TU2_TM_MODE_SZ 1
+#define TU2_TM_INT_STS_DONE_MSK 0x00020000
+#define TU2_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU2_TM_INT_STS_DONE_SFT 17
+#define TU2_TM_INT_STS_DONE_HI 17
+#define TU2_TM_INT_STS_DONE_SZ 1
+#define TU2_TM_INT_MASK_MSK 0x00040000
+#define TU2_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU2_TM_INT_MASK_SFT 18
+#define TU2_TM_INT_MASK_HI 18
+#define TU2_TM_INT_MASK_SZ 1
+#define TU2_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU2_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU2_TM_CUR_VALUE_SFT 0
+#define TU2_TM_CUR_VALUE_HI 15
+#define TU2_TM_CUR_VALUE_SZ 16
+#define TU3_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU3_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU3_TM_INIT_VALUE_SFT 0
+#define TU3_TM_INIT_VALUE_HI 15
+#define TU3_TM_INIT_VALUE_SZ 16
+#define TU3_TM_MODE_MSK 0x00010000
+#define TU3_TM_MODE_I_MSK 0xfffeffff
+#define TU3_TM_MODE_SFT 16
+#define TU3_TM_MODE_HI 16
+#define TU3_TM_MODE_SZ 1
+#define TU3_TM_INT_STS_DONE_MSK 0x00020000
+#define TU3_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU3_TM_INT_STS_DONE_SFT 17
+#define TU3_TM_INT_STS_DONE_HI 17
+#define TU3_TM_INT_STS_DONE_SZ 1
+#define TU3_TM_INT_MASK_MSK 0x00040000
+#define TU3_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU3_TM_INT_MASK_SFT 18
+#define TU3_TM_INT_MASK_HI 18
+#define TU3_TM_INT_MASK_SZ 1
+#define TU3_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU3_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU3_TM_CUR_VALUE_SFT 0
+#define TU3_TM_CUR_VALUE_HI 15
+#define TU3_TM_CUR_VALUE_SZ 16
+#define TM0_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM0_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM0_TM_INIT_VALUE_SFT 0
+#define TM0_TM_INIT_VALUE_HI 15
+#define TM0_TM_INIT_VALUE_SZ 16
+#define TM0_TM_MODE_MSK 0x00010000
+#define TM0_TM_MODE_I_MSK 0xfffeffff
+#define TM0_TM_MODE_SFT 16
+#define TM0_TM_MODE_HI 16
+#define TM0_TM_MODE_SZ 1
+#define TM0_TM_INT_STS_DONE_MSK 0x00020000
+#define TM0_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM0_TM_INT_STS_DONE_SFT 17
+#define TM0_TM_INT_STS_DONE_HI 17
+#define TM0_TM_INT_STS_DONE_SZ 1
+#define TM0_TM_INT_MASK_MSK 0x00040000
+#define TM0_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM0_TM_INT_MASK_SFT 18
+#define TM0_TM_INT_MASK_HI 18
+#define TM0_TM_INT_MASK_SZ 1
+#define TM0_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM0_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM0_TM_CUR_VALUE_SFT 0
+#define TM0_TM_CUR_VALUE_HI 15
+#define TM0_TM_CUR_VALUE_SZ 16
+#define TM1_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM1_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM1_TM_INIT_VALUE_SFT 0
+#define TM1_TM_INIT_VALUE_HI 15
+#define TM1_TM_INIT_VALUE_SZ 16
+#define TM1_TM_MODE_MSK 0x00010000
+#define TM1_TM_MODE_I_MSK 0xfffeffff
+#define TM1_TM_MODE_SFT 16
+#define TM1_TM_MODE_HI 16
+#define TM1_TM_MODE_SZ 1
+#define TM1_TM_INT_STS_DONE_MSK 0x00020000
+#define TM1_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM1_TM_INT_STS_DONE_SFT 17
+#define TM1_TM_INT_STS_DONE_HI 17
+#define TM1_TM_INT_STS_DONE_SZ 1
+#define TM1_TM_INT_MASK_MSK 0x00040000
+#define TM1_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM1_TM_INT_MASK_SFT 18
+#define TM1_TM_INT_MASK_HI 18
+#define TM1_TM_INT_MASK_SZ 1
+#define TM1_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM1_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM1_TM_CUR_VALUE_SFT 0
+#define TM1_TM_CUR_VALUE_HI 15
+#define TM1_TM_CUR_VALUE_SZ 16
+#define TM2_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM2_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM2_TM_INIT_VALUE_SFT 0
+#define TM2_TM_INIT_VALUE_HI 15
+#define TM2_TM_INIT_VALUE_SZ 16
+#define TM2_TM_MODE_MSK 0x00010000
+#define TM2_TM_MODE_I_MSK 0xfffeffff
+#define TM2_TM_MODE_SFT 16
+#define TM2_TM_MODE_HI 16
+#define TM2_TM_MODE_SZ 1
+#define TM2_TM_INT_STS_DONE_MSK 0x00020000
+#define TM2_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM2_TM_INT_STS_DONE_SFT 17
+#define TM2_TM_INT_STS_DONE_HI 17
+#define TM2_TM_INT_STS_DONE_SZ 1
+#define TM2_TM_INT_MASK_MSK 0x00040000
+#define TM2_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM2_TM_INT_MASK_SFT 18
+#define TM2_TM_INT_MASK_HI 18
+#define TM2_TM_INT_MASK_SZ 1
+#define TM2_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM2_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM2_TM_CUR_VALUE_SFT 0
+#define TM2_TM_CUR_VALUE_HI 15
+#define TM2_TM_CUR_VALUE_SZ 16
+#define TM3_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM3_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM3_TM_INIT_VALUE_SFT 0
+#define TM3_TM_INIT_VALUE_HI 15
+#define TM3_TM_INIT_VALUE_SZ 16
+#define TM3_TM_MODE_MSK 0x00010000
+#define TM3_TM_MODE_I_MSK 0xfffeffff
+#define TM3_TM_MODE_SFT 16
+#define TM3_TM_MODE_HI 16
+#define TM3_TM_MODE_SZ 1
+#define TM3_TM_INT_STS_DONE_MSK 0x00020000
+#define TM3_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM3_TM_INT_STS_DONE_SFT 17
+#define TM3_TM_INT_STS_DONE_HI 17
+#define TM3_TM_INT_STS_DONE_SZ 1
+#define TM3_TM_INT_MASK_MSK 0x00040000
+#define TM3_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM3_TM_INT_MASK_SFT 18
+#define TM3_TM_INT_MASK_HI 18
+#define TM3_TM_INT_MASK_SZ 1
+#define TM3_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM3_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM3_TM_CUR_VALUE_SFT 0
+#define TM3_TM_CUR_VALUE_HI 15
+#define TM3_TM_CUR_VALUE_SZ 16
+#define MCU_WDT_TIME_CNT_MSK 0x0000ffff
+#define MCU_WDT_TIME_CNT_I_MSK 0xffff0000
+#define MCU_WDT_TIME_CNT_SFT 0
+#define MCU_WDT_TIME_CNT_HI 15
+#define MCU_WDT_TIME_CNT_SZ 16
+#define MCU_WDT_STATUS_MSK 0x00020000
+#define MCU_WDT_STATUS_I_MSK 0xfffdffff
+#define MCU_WDT_STATUS_SFT 17
+#define MCU_WDT_STATUS_HI 17
+#define MCU_WDT_STATUS_SZ 1
+#define MCU_WDOG_ENA_MSK 0x80000000
+#define MCU_WDOG_ENA_I_MSK 0x7fffffff
+#define MCU_WDOG_ENA_SFT 31
+#define MCU_WDOG_ENA_HI 31
+#define MCU_WDOG_ENA_SZ 1
+#define SYS_WDT_TIME_CNT_MSK 0x0000ffff
+#define SYS_WDT_TIME_CNT_I_MSK 0xffff0000
+#define SYS_WDT_TIME_CNT_SFT 0
+#define SYS_WDT_TIME_CNT_HI 15
+#define SYS_WDT_TIME_CNT_SZ 16
+#define SYS_WDT_STATUS_MSK 0x00020000
+#define SYS_WDT_STATUS_I_MSK 0xfffdffff
+#define SYS_WDT_STATUS_SFT 17
+#define SYS_WDT_STATUS_HI 17
+#define SYS_WDT_STATUS_SZ 1
+#define SYS_WDOG_ENA_MSK 0x80000000
+#define SYS_WDOG_ENA_I_MSK 0x7fffffff
+#define SYS_WDOG_ENA_SFT 31
+#define SYS_WDOG_ENA_HI 31
+#define SYS_WDOG_ENA_SZ 1
+#define XLNA_EN_O_OE_MSK 0x00000001
+#define XLNA_EN_O_OE_I_MSK 0xfffffffe
+#define XLNA_EN_O_OE_SFT 0
+#define XLNA_EN_O_OE_HI 0
+#define XLNA_EN_O_OE_SZ 1
+#define XLNA_EN_O_PE_MSK 0x00000002
+#define XLNA_EN_O_PE_I_MSK 0xfffffffd
+#define XLNA_EN_O_PE_SFT 1
+#define XLNA_EN_O_PE_HI 1
+#define XLNA_EN_O_PE_SZ 1
+#define PAD6_IE_MSK 0x00000008
+#define PAD6_IE_I_MSK 0xfffffff7
+#define PAD6_IE_SFT 3
+#define PAD6_IE_HI 3
+#define PAD6_IE_SZ 1
+#define PAD6_SEL_I_MSK 0x00000030
+#define PAD6_SEL_I_I_MSK 0xffffffcf
+#define PAD6_SEL_I_SFT 4
+#define PAD6_SEL_I_HI 5
+#define PAD6_SEL_I_SZ 2
+#define PAD6_OD_MSK 0x00000100
+#define PAD6_OD_I_MSK 0xfffffeff
+#define PAD6_OD_SFT 8
+#define PAD6_OD_HI 8
+#define PAD6_OD_SZ 1
+#define PAD6_SEL_O_MSK 0x00001000
+#define PAD6_SEL_O_I_MSK 0xffffefff
+#define PAD6_SEL_O_SFT 12
+#define PAD6_SEL_O_HI 12
+#define PAD6_SEL_O_SZ 1
+#define XLNA_EN_O_C_MSK 0x10000000
+#define XLNA_EN_O_C_I_MSK 0xefffffff
+#define XLNA_EN_O_C_SFT 28
+#define XLNA_EN_O_C_HI 28
+#define XLNA_EN_O_C_SZ 1
+#define WIFI_TX_SW_O_OE_MSK 0x00000001
+#define WIFI_TX_SW_O_OE_I_MSK 0xfffffffe
+#define WIFI_TX_SW_O_OE_SFT 0
+#define WIFI_TX_SW_O_OE_HI 0
+#define WIFI_TX_SW_O_OE_SZ 1
+#define WIFI_TX_SW_O_PE_MSK 0x00000002
+#define WIFI_TX_SW_O_PE_I_MSK 0xfffffffd
+#define WIFI_TX_SW_O_PE_SFT 1
+#define WIFI_TX_SW_O_PE_HI 1
+#define WIFI_TX_SW_O_PE_SZ 1
+#define PAD7_IE_MSK 0x00000008
+#define PAD7_IE_I_MSK 0xfffffff7
+#define PAD7_IE_SFT 3
+#define PAD7_IE_HI 3
+#define PAD7_IE_SZ 1
+#define PAD7_SEL_I_MSK 0x00000030
+#define PAD7_SEL_I_I_MSK 0xffffffcf
+#define PAD7_SEL_I_SFT 4
+#define PAD7_SEL_I_HI 5
+#define PAD7_SEL_I_SZ 2
+#define PAD7_OD_MSK 0x00000100
+#define PAD7_OD_I_MSK 0xfffffeff
+#define PAD7_OD_SFT 8
+#define PAD7_OD_HI 8
+#define PAD7_OD_SZ 1
+#define PAD7_SEL_O_MSK 0x00001000
+#define PAD7_SEL_O_I_MSK 0xffffefff
+#define PAD7_SEL_O_SFT 12
+#define PAD7_SEL_O_HI 12
+#define PAD7_SEL_O_SZ 1
+#define WIFI_TX_SW_O_C_MSK 0x10000000
+#define WIFI_TX_SW_O_C_I_MSK 0xefffffff
+#define WIFI_TX_SW_O_C_SFT 28
+#define WIFI_TX_SW_O_C_HI 28
+#define WIFI_TX_SW_O_C_SZ 1
+#define WIFI_RX_SW_O_OE_MSK 0x00000001
+#define WIFI_RX_SW_O_OE_I_MSK 0xfffffffe
+#define WIFI_RX_SW_O_OE_SFT 0
+#define WIFI_RX_SW_O_OE_HI 0
+#define WIFI_RX_SW_O_OE_SZ 1
+#define WIFI_RX_SW_O_PE_MSK 0x00000002
+#define WIFI_RX_SW_O_PE_I_MSK 0xfffffffd
+#define WIFI_RX_SW_O_PE_SFT 1
+#define WIFI_RX_SW_O_PE_HI 1
+#define WIFI_RX_SW_O_PE_SZ 1
+#define PAD8_IE_MSK 0x00000008
+#define PAD8_IE_I_MSK 0xfffffff7
+#define PAD8_IE_SFT 3
+#define PAD8_IE_HI 3
+#define PAD8_IE_SZ 1
+#define PAD8_SEL_I_MSK 0x00000030
+#define PAD8_SEL_I_I_MSK 0xffffffcf
+#define PAD8_SEL_I_SFT 4
+#define PAD8_SEL_I_HI 5
+#define PAD8_SEL_I_SZ 2
+#define PAD8_OD_MSK 0x00000100
+#define PAD8_OD_I_MSK 0xfffffeff
+#define PAD8_OD_SFT 8
+#define PAD8_OD_HI 8
+#define PAD8_OD_SZ 1
+#define WIFI_RX_SW_O_C_MSK 0x10000000
+#define WIFI_RX_SW_O_C_I_MSK 0xefffffff
+#define WIFI_RX_SW_O_C_SFT 28
+#define WIFI_RX_SW_O_C_HI 28
+#define WIFI_RX_SW_O_C_SZ 1
+#define BT_SW_O_OE_MSK 0x00000001
+#define BT_SW_O_OE_I_MSK 0xfffffffe
+#define BT_SW_O_OE_SFT 0
+#define BT_SW_O_OE_HI 0
+#define BT_SW_O_OE_SZ 1
+#define BT_SW_O_PE_MSK 0x00000002
+#define BT_SW_O_PE_I_MSK 0xfffffffd
+#define BT_SW_O_PE_SFT 1
+#define BT_SW_O_PE_HI 1
+#define BT_SW_O_PE_SZ 1
+#define PAD9_IE_MSK 0x00000008
+#define PAD9_IE_I_MSK 0xfffffff7
+#define PAD9_IE_SFT 3
+#define PAD9_IE_HI 3
+#define PAD9_IE_SZ 1
+#define PAD9_SEL_I_MSK 0x00000030
+#define PAD9_SEL_I_I_MSK 0xffffffcf
+#define PAD9_SEL_I_SFT 4
+#define PAD9_SEL_I_HI 5
+#define PAD9_SEL_I_SZ 2
+#define PAD9_OD_MSK 0x00000100
+#define PAD9_OD_I_MSK 0xfffffeff
+#define PAD9_OD_SFT 8
+#define PAD9_OD_HI 8
+#define PAD9_OD_SZ 1
+#define PAD9_SEL_O_MSK 0x00001000
+#define PAD9_SEL_O_I_MSK 0xffffefff
+#define PAD9_SEL_O_SFT 12
+#define PAD9_SEL_O_HI 12
+#define PAD9_SEL_O_SZ 1
+#define BT_SW_O_C_MSK 0x10000000
+#define BT_SW_O_C_I_MSK 0xefffffff
+#define BT_SW_O_C_SFT 28
+#define BT_SW_O_C_HI 28
+#define BT_SW_O_C_SZ 1
+#define XPA_EN_O_OE_MSK 0x00000001
+#define XPA_EN_O_OE_I_MSK 0xfffffffe
+#define XPA_EN_O_OE_SFT 0
+#define XPA_EN_O_OE_HI 0
+#define XPA_EN_O_OE_SZ 1
+#define XPA_EN_O_PE_MSK 0x00000002
+#define XPA_EN_O_PE_I_MSK 0xfffffffd
+#define XPA_EN_O_PE_SFT 1
+#define XPA_EN_O_PE_HI 1
+#define XPA_EN_O_PE_SZ 1
+#define PAD11_IE_MSK 0x00000008
+#define PAD11_IE_I_MSK 0xfffffff7
+#define PAD11_IE_SFT 3
+#define PAD11_IE_HI 3
+#define PAD11_IE_SZ 1
+#define PAD11_SEL_I_MSK 0x00000030
+#define PAD11_SEL_I_I_MSK 0xffffffcf
+#define PAD11_SEL_I_SFT 4
+#define PAD11_SEL_I_HI 5
+#define PAD11_SEL_I_SZ 2
+#define PAD11_OD_MSK 0x00000100
+#define PAD11_OD_I_MSK 0xfffffeff
+#define PAD11_OD_SFT 8
+#define PAD11_OD_HI 8
+#define PAD11_OD_SZ 1
+#define PAD11_SEL_O_MSK 0x00001000
+#define PAD11_SEL_O_I_MSK 0xffffefff
+#define PAD11_SEL_O_SFT 12
+#define PAD11_SEL_O_HI 12
+#define PAD11_SEL_O_SZ 1
+#define XPA_EN_O_C_MSK 0x10000000
+#define XPA_EN_O_C_I_MSK 0xefffffff
+#define XPA_EN_O_C_SFT 28
+#define XPA_EN_O_C_HI 28
+#define XPA_EN_O_C_SZ 1
+#define PAD15_OE_MSK 0x00000001
+#define PAD15_OE_I_MSK 0xfffffffe
+#define PAD15_OE_SFT 0
+#define PAD15_OE_HI 0
+#define PAD15_OE_SZ 1
+#define PAD15_PE_MSK 0x00000002
+#define PAD15_PE_I_MSK 0xfffffffd
+#define PAD15_PE_SFT 1
+#define PAD15_PE_HI 1
+#define PAD15_PE_SZ 1
+#define PAD15_DS_MSK 0x00000004
+#define PAD15_DS_I_MSK 0xfffffffb
+#define PAD15_DS_SFT 2
+#define PAD15_DS_HI 2
+#define PAD15_DS_SZ 1
+#define PAD15_IE_MSK 0x00000008
+#define PAD15_IE_I_MSK 0xfffffff7
+#define PAD15_IE_SFT 3
+#define PAD15_IE_HI 3
+#define PAD15_IE_SZ 1
+#define PAD15_SEL_I_MSK 0x00000030
+#define PAD15_SEL_I_I_MSK 0xffffffcf
+#define PAD15_SEL_I_SFT 4
+#define PAD15_SEL_I_HI 5
+#define PAD15_SEL_I_SZ 2
+#define PAD15_OD_MSK 0x00000100
+#define PAD15_OD_I_MSK 0xfffffeff
+#define PAD15_OD_SFT 8
+#define PAD15_OD_HI 8
+#define PAD15_OD_SZ 1
+#define PAD15_SEL_O_MSK 0x00001000
+#define PAD15_SEL_O_I_MSK 0xffffefff
+#define PAD15_SEL_O_SFT 12
+#define PAD15_SEL_O_HI 12
+#define PAD15_SEL_O_SZ 1
+#define TEST_1_ID_MSK 0x10000000
+#define TEST_1_ID_I_MSK 0xefffffff
+#define TEST_1_ID_SFT 28
+#define TEST_1_ID_HI 28
+#define TEST_1_ID_SZ 1
+#define PAD16_OE_MSK 0x00000001
+#define PAD16_OE_I_MSK 0xfffffffe
+#define PAD16_OE_SFT 0
+#define PAD16_OE_HI 0
+#define PAD16_OE_SZ 1
+#define PAD16_PE_MSK 0x00000002
+#define PAD16_PE_I_MSK 0xfffffffd
+#define PAD16_PE_SFT 1
+#define PAD16_PE_HI 1
+#define PAD16_PE_SZ 1
+#define PAD16_DS_MSK 0x00000004
+#define PAD16_DS_I_MSK 0xfffffffb
+#define PAD16_DS_SFT 2
+#define PAD16_DS_HI 2
+#define PAD16_DS_SZ 1
+#define PAD16_IE_MSK 0x00000008
+#define PAD16_IE_I_MSK 0xfffffff7
+#define PAD16_IE_SFT 3
+#define PAD16_IE_HI 3
+#define PAD16_IE_SZ 1
+#define PAD16_SEL_I_MSK 0x00000030
+#define PAD16_SEL_I_I_MSK 0xffffffcf
+#define PAD16_SEL_I_SFT 4
+#define PAD16_SEL_I_HI 5
+#define PAD16_SEL_I_SZ 2
+#define PAD16_OD_MSK 0x00000100
+#define PAD16_OD_I_MSK 0xfffffeff
+#define PAD16_OD_SFT 8
+#define PAD16_OD_HI 8
+#define PAD16_OD_SZ 1
+#define PAD16_SEL_O_MSK 0x00001000
+#define PAD16_SEL_O_I_MSK 0xffffefff
+#define PAD16_SEL_O_SFT 12
+#define PAD16_SEL_O_HI 12
+#define PAD16_SEL_O_SZ 1
+#define TEST_2_ID_MSK 0x10000000
+#define TEST_2_ID_I_MSK 0xefffffff
+#define TEST_2_ID_SFT 28
+#define TEST_2_ID_HI 28
+#define TEST_2_ID_SZ 1
+#define PAD17_OE_MSK 0x00000001
+#define PAD17_OE_I_MSK 0xfffffffe
+#define PAD17_OE_SFT 0
+#define PAD17_OE_HI 0
+#define PAD17_OE_SZ 1
+#define PAD17_PE_MSK 0x00000002
+#define PAD17_PE_I_MSK 0xfffffffd
+#define PAD17_PE_SFT 1
+#define PAD17_PE_HI 1
+#define PAD17_PE_SZ 1
+#define PAD17_DS_MSK 0x00000004
+#define PAD17_DS_I_MSK 0xfffffffb
+#define PAD17_DS_SFT 2
+#define PAD17_DS_HI 2
+#define PAD17_DS_SZ 1
+#define PAD17_IE_MSK 0x00000008
+#define PAD17_IE_I_MSK 0xfffffff7
+#define PAD17_IE_SFT 3
+#define PAD17_IE_HI 3
+#define PAD17_IE_SZ 1
+#define PAD17_SEL_I_MSK 0x00000030
+#define PAD17_SEL_I_I_MSK 0xffffffcf
+#define PAD17_SEL_I_SFT 4
+#define PAD17_SEL_I_HI 5
+#define PAD17_SEL_I_SZ 2
+#define PAD17_OD_MSK 0x00000100
+#define PAD17_OD_I_MSK 0xfffffeff
+#define PAD17_OD_SFT 8
+#define PAD17_OD_HI 8
+#define PAD17_OD_SZ 1
+#define PAD17_SEL_O_MSK 0x00001000
+#define PAD17_SEL_O_I_MSK 0xffffefff
+#define PAD17_SEL_O_SFT 12
+#define PAD17_SEL_O_HI 12
+#define PAD17_SEL_O_SZ 1
+#define TEST_3_ID_MSK 0x10000000
+#define TEST_3_ID_I_MSK 0xefffffff
+#define TEST_3_ID_SFT 28
+#define TEST_3_ID_HI 28
+#define TEST_3_ID_SZ 1
+#define PAD18_OE_MSK 0x00000001
+#define PAD18_OE_I_MSK 0xfffffffe
+#define PAD18_OE_SFT 0
+#define PAD18_OE_HI 0
+#define PAD18_OE_SZ 1
+#define PAD18_PE_MSK 0x00000002
+#define PAD18_PE_I_MSK 0xfffffffd
+#define PAD18_PE_SFT 1
+#define PAD18_PE_HI 1
+#define PAD18_PE_SZ 1
+#define PAD18_DS_MSK 0x00000004
+#define PAD18_DS_I_MSK 0xfffffffb
+#define PAD18_DS_SFT 2
+#define PAD18_DS_HI 2
+#define PAD18_DS_SZ 1
+#define PAD18_IE_MSK 0x00000008
+#define PAD18_IE_I_MSK 0xfffffff7
+#define PAD18_IE_SFT 3
+#define PAD18_IE_HI 3
+#define PAD18_IE_SZ 1
+#define PAD18_SEL_I_MSK 0x00000030
+#define PAD18_SEL_I_I_MSK 0xffffffcf
+#define PAD18_SEL_I_SFT 4
+#define PAD18_SEL_I_HI 5
+#define PAD18_SEL_I_SZ 2
+#define PAD18_OD_MSK 0x00000100
+#define PAD18_OD_I_MSK 0xfffffeff
+#define PAD18_OD_SFT 8
+#define PAD18_OD_HI 8
+#define PAD18_OD_SZ 1
+#define PAD18_SEL_O_MSK 0x00003000
+#define PAD18_SEL_O_I_MSK 0xffffcfff
+#define PAD18_SEL_O_SFT 12
+#define PAD18_SEL_O_HI 13
+#define PAD18_SEL_O_SZ 2
+#define TEST_4_ID_MSK 0x10000000
+#define TEST_4_ID_I_MSK 0xefffffff
+#define TEST_4_ID_SFT 28
+#define TEST_4_ID_HI 28
+#define TEST_4_ID_SZ 1
+#define PAD19_OE_MSK 0x00000001
+#define PAD19_OE_I_MSK 0xfffffffe
+#define PAD19_OE_SFT 0
+#define PAD19_OE_HI 0
+#define PAD19_OE_SZ 1
+#define PAD19_PE_MSK 0x00000002
+#define PAD19_PE_I_MSK 0xfffffffd
+#define PAD19_PE_SFT 1
+#define PAD19_PE_HI 1
+#define PAD19_PE_SZ 1
+#define PAD19_DS_MSK 0x00000004
+#define PAD19_DS_I_MSK 0xfffffffb
+#define PAD19_DS_SFT 2
+#define PAD19_DS_HI 2
+#define PAD19_DS_SZ 1
+#define PAD19_IE_MSK 0x00000008
+#define PAD19_IE_I_MSK 0xfffffff7
+#define PAD19_IE_SFT 3
+#define PAD19_IE_HI 3
+#define PAD19_IE_SZ 1
+#define PAD19_SEL_I_MSK 0x00000030
+#define PAD19_SEL_I_I_MSK 0xffffffcf
+#define PAD19_SEL_I_SFT 4
+#define PAD19_SEL_I_HI 5
+#define PAD19_SEL_I_SZ 2
+#define PAD19_OD_MSK 0x00000100
+#define PAD19_OD_I_MSK 0xfffffeff
+#define PAD19_OD_SFT 8
+#define PAD19_OD_HI 8
+#define PAD19_OD_SZ 1
+#define PAD19_SEL_O_MSK 0x00007000
+#define PAD19_SEL_O_I_MSK 0xffff8fff
+#define PAD19_SEL_O_SFT 12
+#define PAD19_SEL_O_HI 14
+#define PAD19_SEL_O_SZ 3
+#define SHORT_TO_20_ID_MSK 0x10000000
+#define SHORT_TO_20_ID_I_MSK 0xefffffff
+#define SHORT_TO_20_ID_SFT 28
+#define SHORT_TO_20_ID_HI 28
+#define SHORT_TO_20_ID_SZ 1
+#define PAD20_OE_MSK 0x00000001
+#define PAD20_OE_I_MSK 0xfffffffe
+#define PAD20_OE_SFT 0
+#define PAD20_OE_HI 0
+#define PAD20_OE_SZ 1
+#define PAD20_PE_MSK 0x00000002
+#define PAD20_PE_I_MSK 0xfffffffd
+#define PAD20_PE_SFT 1
+#define PAD20_PE_HI 1
+#define PAD20_PE_SZ 1
+#define PAD20_DS_MSK 0x00000004
+#define PAD20_DS_I_MSK 0xfffffffb
+#define PAD20_DS_SFT 2
+#define PAD20_DS_HI 2
+#define PAD20_DS_SZ 1
+#define PAD20_IE_MSK 0x00000008
+#define PAD20_IE_I_MSK 0xfffffff7
+#define PAD20_IE_SFT 3
+#define PAD20_IE_HI 3
+#define PAD20_IE_SZ 1
+#define PAD20_SEL_I_MSK 0x000000f0
+#define PAD20_SEL_I_I_MSK 0xffffff0f
+#define PAD20_SEL_I_SFT 4
+#define PAD20_SEL_I_HI 7
+#define PAD20_SEL_I_SZ 4
+#define PAD20_OD_MSK 0x00000100
+#define PAD20_OD_I_MSK 0xfffffeff
+#define PAD20_OD_SFT 8
+#define PAD20_OD_HI 8
+#define PAD20_OD_SZ 1
+#define PAD20_SEL_O_MSK 0x00003000
+#define PAD20_SEL_O_I_MSK 0xffffcfff
+#define PAD20_SEL_O_SFT 12
+#define PAD20_SEL_O_HI 13
+#define PAD20_SEL_O_SZ 2
+#define STRAP0_MSK 0x08000000
+#define STRAP0_I_MSK 0xf7ffffff
+#define STRAP0_SFT 27
+#define STRAP0_HI 27
+#define STRAP0_SZ 1
+#define GPIO_TEST_1_ID_MSK 0x10000000
+#define GPIO_TEST_1_ID_I_MSK 0xefffffff
+#define GPIO_TEST_1_ID_SFT 28
+#define GPIO_TEST_1_ID_HI 28
+#define GPIO_TEST_1_ID_SZ 1
+#define PAD21_OE_MSK 0x00000001
+#define PAD21_OE_I_MSK 0xfffffffe
+#define PAD21_OE_SFT 0
+#define PAD21_OE_HI 0
+#define PAD21_OE_SZ 1
+#define PAD21_PE_MSK 0x00000002
+#define PAD21_PE_I_MSK 0xfffffffd
+#define PAD21_PE_SFT 1
+#define PAD21_PE_HI 1
+#define PAD21_PE_SZ 1
+#define PAD21_DS_MSK 0x00000004
+#define PAD21_DS_I_MSK 0xfffffffb
+#define PAD21_DS_SFT 2
+#define PAD21_DS_HI 2
+#define PAD21_DS_SZ 1
+#define PAD21_IE_MSK 0x00000008
+#define PAD21_IE_I_MSK 0xfffffff7
+#define PAD21_IE_SFT 3
+#define PAD21_IE_HI 3
+#define PAD21_IE_SZ 1
+#define PAD21_SEL_I_MSK 0x00000070
+#define PAD21_SEL_I_I_MSK 0xffffff8f
+#define PAD21_SEL_I_SFT 4
+#define PAD21_SEL_I_HI 6
+#define PAD21_SEL_I_SZ 3
+#define PAD21_OD_MSK 0x00000100
+#define PAD21_OD_I_MSK 0xfffffeff
+#define PAD21_OD_SFT 8
+#define PAD21_OD_HI 8
+#define PAD21_OD_SZ 1
+#define PAD21_SEL_O_MSK 0x00003000
+#define PAD21_SEL_O_I_MSK 0xffffcfff
+#define PAD21_SEL_O_SFT 12
+#define PAD21_SEL_O_HI 13
+#define PAD21_SEL_O_SZ 2
+#define STRAP3_MSK 0x08000000
+#define STRAP3_I_MSK 0xf7ffffff
+#define STRAP3_SFT 27
+#define STRAP3_HI 27
+#define STRAP3_SZ 1
+#define GPIO_TEST_2_ID_MSK 0x10000000
+#define GPIO_TEST_2_ID_I_MSK 0xefffffff
+#define GPIO_TEST_2_ID_SFT 28
+#define GPIO_TEST_2_ID_HI 28
+#define GPIO_TEST_2_ID_SZ 1
+#define PAD22_OE_MSK 0x00000001
+#define PAD22_OE_I_MSK 0xfffffffe
+#define PAD22_OE_SFT 0
+#define PAD22_OE_HI 0
+#define PAD22_OE_SZ 1
+#define PAD22_PE_MSK 0x00000002
+#define PAD22_PE_I_MSK 0xfffffffd
+#define PAD22_PE_SFT 1
+#define PAD22_PE_HI 1
+#define PAD22_PE_SZ 1
+#define PAD22_DS_MSK 0x00000004
+#define PAD22_DS_I_MSK 0xfffffffb
+#define PAD22_DS_SFT 2
+#define PAD22_DS_HI 2
+#define PAD22_DS_SZ 1
+#define PAD22_IE_MSK 0x00000008
+#define PAD22_IE_I_MSK 0xfffffff7
+#define PAD22_IE_SFT 3
+#define PAD22_IE_HI 3
+#define PAD22_IE_SZ 1
+#define PAD22_SEL_I_MSK 0x00000070
+#define PAD22_SEL_I_I_MSK 0xffffff8f
+#define PAD22_SEL_I_SFT 4
+#define PAD22_SEL_I_HI 6
+#define PAD22_SEL_I_SZ 3
+#define PAD22_OD_MSK 0x00000100
+#define PAD22_OD_I_MSK 0xfffffeff
+#define PAD22_OD_SFT 8
+#define PAD22_OD_HI 8
+#define PAD22_OD_SZ 1
+#define PAD22_SEL_O_MSK 0x00007000
+#define PAD22_SEL_O_I_MSK 0xffff8fff
+#define PAD22_SEL_O_SFT 12
+#define PAD22_SEL_O_HI 14
+#define PAD22_SEL_O_SZ 3
+#define PAD22_SEL_OE_MSK 0x00100000
+#define PAD22_SEL_OE_I_MSK 0xffefffff
+#define PAD22_SEL_OE_SFT 20
+#define PAD22_SEL_OE_HI 20
+#define PAD22_SEL_OE_SZ 1
+#define GPIO_TEST_3_ID_MSK 0x10000000
+#define GPIO_TEST_3_ID_I_MSK 0xefffffff
+#define GPIO_TEST_3_ID_SFT 28
+#define GPIO_TEST_3_ID_HI 28
+#define GPIO_TEST_3_ID_SZ 1
+#define PAD24_OE_MSK 0x00000001
+#define PAD24_OE_I_MSK 0xfffffffe
+#define PAD24_OE_SFT 0
+#define PAD24_OE_HI 0
+#define PAD24_OE_SZ 1
+#define PAD24_PE_MSK 0x00000002
+#define PAD24_PE_I_MSK 0xfffffffd
+#define PAD24_PE_SFT 1
+#define PAD24_PE_HI 1
+#define PAD24_PE_SZ 1
+#define PAD24_DS_MSK 0x00000004
+#define PAD24_DS_I_MSK 0xfffffffb
+#define PAD24_DS_SFT 2
+#define PAD24_DS_HI 2
+#define PAD24_DS_SZ 1
+#define PAD24_IE_MSK 0x00000008
+#define PAD24_IE_I_MSK 0xfffffff7
+#define PAD24_IE_SFT 3
+#define PAD24_IE_HI 3
+#define PAD24_IE_SZ 1
+#define PAD24_SEL_I_MSK 0x00000030
+#define PAD24_SEL_I_I_MSK 0xffffffcf
+#define PAD24_SEL_I_SFT 4
+#define PAD24_SEL_I_HI 5
+#define PAD24_SEL_I_SZ 2
+#define PAD24_OD_MSK 0x00000100
+#define PAD24_OD_I_MSK 0xfffffeff
+#define PAD24_OD_SFT 8
+#define PAD24_OD_HI 8
+#define PAD24_OD_SZ 1
+#define PAD24_SEL_O_MSK 0x00007000
+#define PAD24_SEL_O_I_MSK 0xffff8fff
+#define PAD24_SEL_O_SFT 12
+#define PAD24_SEL_O_HI 14
+#define PAD24_SEL_O_SZ 3
+#define GPIO_TEST_4_ID_MSK 0x10000000
+#define GPIO_TEST_4_ID_I_MSK 0xefffffff
+#define GPIO_TEST_4_ID_SFT 28
+#define GPIO_TEST_4_ID_HI 28
+#define GPIO_TEST_4_ID_SZ 1
+#define PAD25_OE_MSK 0x00000001
+#define PAD25_OE_I_MSK 0xfffffffe
+#define PAD25_OE_SFT 0
+#define PAD25_OE_HI 0
+#define PAD25_OE_SZ 1
+#define PAD25_PE_MSK 0x00000002
+#define PAD25_PE_I_MSK 0xfffffffd
+#define PAD25_PE_SFT 1
+#define PAD25_PE_HI 1
+#define PAD25_PE_SZ 1
+#define PAD25_DS_MSK 0x00000004
+#define PAD25_DS_I_MSK 0xfffffffb
+#define PAD25_DS_SFT 2
+#define PAD25_DS_HI 2
+#define PAD25_DS_SZ 1
+#define PAD25_IE_MSK 0x00000008
+#define PAD25_IE_I_MSK 0xfffffff7
+#define PAD25_IE_SFT 3
+#define PAD25_IE_HI 3
+#define PAD25_IE_SZ 1
+#define PAD25_SEL_I_MSK 0x00000070
+#define PAD25_SEL_I_I_MSK 0xffffff8f
+#define PAD25_SEL_I_SFT 4
+#define PAD25_SEL_I_HI 6
+#define PAD25_SEL_I_SZ 3
+#define PAD25_OD_MSK 0x00000100
+#define PAD25_OD_I_MSK 0xfffffeff
+#define PAD25_OD_SFT 8
+#define PAD25_OD_HI 8
+#define PAD25_OD_SZ 1
+#define PAD25_SEL_O_MSK 0x00007000
+#define PAD25_SEL_O_I_MSK 0xffff8fff
+#define PAD25_SEL_O_SFT 12
+#define PAD25_SEL_O_HI 14
+#define PAD25_SEL_O_SZ 3
+#define PAD25_SEL_OE_MSK 0x00100000
+#define PAD25_SEL_OE_I_MSK 0xffefffff
+#define PAD25_SEL_OE_SFT 20
+#define PAD25_SEL_OE_HI 20
+#define PAD25_SEL_OE_SZ 1
+#define STRAP1_MSK 0x08000000
+#define STRAP1_I_MSK 0xf7ffffff
+#define STRAP1_SFT 27
+#define STRAP1_HI 27
+#define STRAP1_SZ 1
+#define GPIO_1_ID_MSK 0x10000000
+#define GPIO_1_ID_I_MSK 0xefffffff
+#define GPIO_1_ID_SFT 28
+#define GPIO_1_ID_HI 28
+#define GPIO_1_ID_SZ 1
+#define PAD27_OE_MSK 0x00000001
+#define PAD27_OE_I_MSK 0xfffffffe
+#define PAD27_OE_SFT 0
+#define PAD27_OE_HI 0
+#define PAD27_OE_SZ 1
+#define PAD27_PE_MSK 0x00000002
+#define PAD27_PE_I_MSK 0xfffffffd
+#define PAD27_PE_SFT 1
+#define PAD27_PE_HI 1
+#define PAD27_PE_SZ 1
+#define PAD27_DS_MSK 0x00000004
+#define PAD27_DS_I_MSK 0xfffffffb
+#define PAD27_DS_SFT 2
+#define PAD27_DS_HI 2
+#define PAD27_DS_SZ 1
+#define PAD27_IE_MSK 0x00000008
+#define PAD27_IE_I_MSK 0xfffffff7
+#define PAD27_IE_SFT 3
+#define PAD27_IE_HI 3
+#define PAD27_IE_SZ 1
+#define PAD27_SEL_I_MSK 0x00000070
+#define PAD27_SEL_I_I_MSK 0xffffff8f
+#define PAD27_SEL_I_SFT 4
+#define PAD27_SEL_I_HI 6
+#define PAD27_SEL_I_SZ 3
+#define PAD27_OD_MSK 0x00000100
+#define PAD27_OD_I_MSK 0xfffffeff
+#define PAD27_OD_SFT 8
+#define PAD27_OD_HI 8
+#define PAD27_OD_SZ 1
+#define PAD27_SEL_O_MSK 0x00007000
+#define PAD27_SEL_O_I_MSK 0xffff8fff
+#define PAD27_SEL_O_SFT 12
+#define PAD27_SEL_O_HI 14
+#define PAD27_SEL_O_SZ 3
+#define GPIO_2_ID_MSK 0x10000000
+#define GPIO_2_ID_I_MSK 0xefffffff
+#define GPIO_2_ID_SFT 28
+#define GPIO_2_ID_HI 28
+#define GPIO_2_ID_SZ 1
+#define PAD28_OE_MSK 0x00000001
+#define PAD28_OE_I_MSK 0xfffffffe
+#define PAD28_OE_SFT 0
+#define PAD28_OE_HI 0
+#define PAD28_OE_SZ 1
+#define PAD28_PE_MSK 0x00000002
+#define PAD28_PE_I_MSK 0xfffffffd
+#define PAD28_PE_SFT 1
+#define PAD28_PE_HI 1
+#define PAD28_PE_SZ 1
+#define PAD28_DS_MSK 0x00000004
+#define PAD28_DS_I_MSK 0xfffffffb
+#define PAD28_DS_SFT 2
+#define PAD28_DS_HI 2
+#define PAD28_DS_SZ 1
+#define PAD28_IE_MSK 0x00000008
+#define PAD28_IE_I_MSK 0xfffffff7
+#define PAD28_IE_SFT 3
+#define PAD28_IE_HI 3
+#define PAD28_IE_SZ 1
+#define PAD28_SEL_I_MSK 0x00000070
+#define PAD28_SEL_I_I_MSK 0xffffff8f
+#define PAD28_SEL_I_SFT 4
+#define PAD28_SEL_I_HI 6
+#define PAD28_SEL_I_SZ 3
+#define PAD28_OD_MSK 0x00000100
+#define PAD28_OD_I_MSK 0xfffffeff
+#define PAD28_OD_SFT 8
+#define PAD28_OD_HI 8
+#define PAD28_OD_SZ 1
+#define PAD28_SEL_O_MSK 0x0000f000
+#define PAD28_SEL_O_I_MSK 0xffff0fff
+#define PAD28_SEL_O_SFT 12
+#define PAD28_SEL_O_HI 15
+#define PAD28_SEL_O_SZ 4
+#define PAD28_SEL_OE_MSK 0x00100000
+#define PAD28_SEL_OE_I_MSK 0xffefffff
+#define PAD28_SEL_OE_SFT 20
+#define PAD28_SEL_OE_HI 20
+#define PAD28_SEL_OE_SZ 1
+#define GPIO_3_ID_MSK 0x10000000
+#define GPIO_3_ID_I_MSK 0xefffffff
+#define GPIO_3_ID_SFT 28
+#define GPIO_3_ID_HI 28
+#define GPIO_3_ID_SZ 1
+#define PAD29_OE_MSK 0x00000001
+#define PAD29_OE_I_MSK 0xfffffffe
+#define PAD29_OE_SFT 0
+#define PAD29_OE_HI 0
+#define PAD29_OE_SZ 1
+#define PAD29_PE_MSK 0x00000002
+#define PAD29_PE_I_MSK 0xfffffffd
+#define PAD29_PE_SFT 1
+#define PAD29_PE_HI 1
+#define PAD29_PE_SZ 1
+#define PAD29_DS_MSK 0x00000004
+#define PAD29_DS_I_MSK 0xfffffffb
+#define PAD29_DS_SFT 2
+#define PAD29_DS_HI 2
+#define PAD29_DS_SZ 1
+#define PAD29_IE_MSK 0x00000008
+#define PAD29_IE_I_MSK 0xfffffff7
+#define PAD29_IE_SFT 3
+#define PAD29_IE_HI 3
+#define PAD29_IE_SZ 1
+#define PAD29_SEL_I_MSK 0x00000070
+#define PAD29_SEL_I_I_MSK 0xffffff8f
+#define PAD29_SEL_I_SFT 4
+#define PAD29_SEL_I_HI 6
+#define PAD29_SEL_I_SZ 3
+#define PAD29_OD_MSK 0x00000100
+#define PAD29_OD_I_MSK 0xfffffeff
+#define PAD29_OD_SFT 8
+#define PAD29_OD_HI 8
+#define PAD29_OD_SZ 1
+#define PAD29_SEL_O_MSK 0x00007000
+#define PAD29_SEL_O_I_MSK 0xffff8fff
+#define PAD29_SEL_O_SFT 12
+#define PAD29_SEL_O_HI 14
+#define PAD29_SEL_O_SZ 3
+#define GPIO_TEST_5_ID_MSK 0x10000000
+#define GPIO_TEST_5_ID_I_MSK 0xefffffff
+#define GPIO_TEST_5_ID_SFT 28
+#define GPIO_TEST_5_ID_HI 28
+#define GPIO_TEST_5_ID_SZ 1
+#define PAD30_OE_MSK 0x00000001
+#define PAD30_OE_I_MSK 0xfffffffe
+#define PAD30_OE_SFT 0
+#define PAD30_OE_HI 0
+#define PAD30_OE_SZ 1
+#define PAD30_PE_MSK 0x00000002
+#define PAD30_PE_I_MSK 0xfffffffd
+#define PAD30_PE_SFT 1
+#define PAD30_PE_HI 1
+#define PAD30_PE_SZ 1
+#define PAD30_DS_MSK 0x00000004
+#define PAD30_DS_I_MSK 0xfffffffb
+#define PAD30_DS_SFT 2
+#define PAD30_DS_HI 2
+#define PAD30_DS_SZ 1
+#define PAD30_IE_MSK 0x00000008
+#define PAD30_IE_I_MSK 0xfffffff7
+#define PAD30_IE_SFT 3
+#define PAD30_IE_HI 3
+#define PAD30_IE_SZ 1
+#define PAD30_SEL_I_MSK 0x00000030
+#define PAD30_SEL_I_I_MSK 0xffffffcf
+#define PAD30_SEL_I_SFT 4
+#define PAD30_SEL_I_HI 5
+#define PAD30_SEL_I_SZ 2
+#define PAD30_OD_MSK 0x00000100
+#define PAD30_OD_I_MSK 0xfffffeff
+#define PAD30_OD_SFT 8
+#define PAD30_OD_HI 8
+#define PAD30_OD_SZ 1
+#define PAD30_SEL_O_MSK 0x00003000
+#define PAD30_SEL_O_I_MSK 0xffffcfff
+#define PAD30_SEL_O_SFT 12
+#define PAD30_SEL_O_HI 13
+#define PAD30_SEL_O_SZ 2
+#define TEST_6_ID_MSK 0x10000000
+#define TEST_6_ID_I_MSK 0xefffffff
+#define TEST_6_ID_SFT 28
+#define TEST_6_ID_HI 28
+#define TEST_6_ID_SZ 1
+#define PAD31_OE_MSK 0x00000001
+#define PAD31_OE_I_MSK 0xfffffffe
+#define PAD31_OE_SFT 0
+#define PAD31_OE_HI 0
+#define PAD31_OE_SZ 1
+#define PAD31_PE_MSK 0x00000002
+#define PAD31_PE_I_MSK 0xfffffffd
+#define PAD31_PE_SFT 1
+#define PAD31_PE_HI 1
+#define PAD31_PE_SZ 1
+#define PAD31_DS_MSK 0x00000004
+#define PAD31_DS_I_MSK 0xfffffffb
+#define PAD31_DS_SFT 2
+#define PAD31_DS_HI 2
+#define PAD31_DS_SZ 1
+#define PAD31_IE_MSK 0x00000008
+#define PAD31_IE_I_MSK 0xfffffff7
+#define PAD31_IE_SFT 3
+#define PAD31_IE_HI 3
+#define PAD31_IE_SZ 1
+#define PAD31_SEL_I_MSK 0x00000030
+#define PAD31_SEL_I_I_MSK 0xffffffcf
+#define PAD31_SEL_I_SFT 4
+#define PAD31_SEL_I_HI 5
+#define PAD31_SEL_I_SZ 2
+#define PAD31_OD_MSK 0x00000100
+#define PAD31_OD_I_MSK 0xfffffeff
+#define PAD31_OD_SFT 8
+#define PAD31_OD_HI 8
+#define PAD31_OD_SZ 1
+#define PAD31_SEL_O_MSK 0x00003000
+#define PAD31_SEL_O_I_MSK 0xffffcfff
+#define PAD31_SEL_O_SFT 12
+#define PAD31_SEL_O_HI 13
+#define PAD31_SEL_O_SZ 2
+#define TEST_7_ID_MSK 0x10000000
+#define TEST_7_ID_I_MSK 0xefffffff
+#define TEST_7_ID_SFT 28
+#define TEST_7_ID_HI 28
+#define TEST_7_ID_SZ 1
+#define PAD32_OE_MSK 0x00000001
+#define PAD32_OE_I_MSK 0xfffffffe
+#define PAD32_OE_SFT 0
+#define PAD32_OE_HI 0
+#define PAD32_OE_SZ 1
+#define PAD32_PE_MSK 0x00000002
+#define PAD32_PE_I_MSK 0xfffffffd
+#define PAD32_PE_SFT 1
+#define PAD32_PE_HI 1
+#define PAD32_PE_SZ 1
+#define PAD32_DS_MSK 0x00000004
+#define PAD32_DS_I_MSK 0xfffffffb
+#define PAD32_DS_SFT 2
+#define PAD32_DS_HI 2
+#define PAD32_DS_SZ 1
+#define PAD32_IE_MSK 0x00000008
+#define PAD32_IE_I_MSK 0xfffffff7
+#define PAD32_IE_SFT 3
+#define PAD32_IE_HI 3
+#define PAD32_IE_SZ 1
+#define PAD32_SEL_I_MSK 0x00000030
+#define PAD32_SEL_I_I_MSK 0xffffffcf
+#define PAD32_SEL_I_SFT 4
+#define PAD32_SEL_I_HI 5
+#define PAD32_SEL_I_SZ 2
+#define PAD32_OD_MSK 0x00000100
+#define PAD32_OD_I_MSK 0xfffffeff
+#define PAD32_OD_SFT 8
+#define PAD32_OD_HI 8
+#define PAD32_OD_SZ 1
+#define PAD32_SEL_O_MSK 0x00003000
+#define PAD32_SEL_O_I_MSK 0xffffcfff
+#define PAD32_SEL_O_SFT 12
+#define PAD32_SEL_O_HI 13
+#define PAD32_SEL_O_SZ 2
+#define TEST_8_ID_MSK 0x10000000
+#define TEST_8_ID_I_MSK 0xefffffff
+#define TEST_8_ID_SFT 28
+#define TEST_8_ID_HI 28
+#define TEST_8_ID_SZ 1
+#define PAD33_OE_MSK 0x00000001
+#define PAD33_OE_I_MSK 0xfffffffe
+#define PAD33_OE_SFT 0
+#define PAD33_OE_HI 0
+#define PAD33_OE_SZ 1
+#define PAD33_PE_MSK 0x00000002
+#define PAD33_PE_I_MSK 0xfffffffd
+#define PAD33_PE_SFT 1
+#define PAD33_PE_HI 1
+#define PAD33_PE_SZ 1
+#define PAD33_DS_MSK 0x00000004
+#define PAD33_DS_I_MSK 0xfffffffb
+#define PAD33_DS_SFT 2
+#define PAD33_DS_HI 2
+#define PAD33_DS_SZ 1
+#define PAD33_IE_MSK 0x00000008
+#define PAD33_IE_I_MSK 0xfffffff7
+#define PAD33_IE_SFT 3
+#define PAD33_IE_HI 3
+#define PAD33_IE_SZ 1
+#define PAD33_SEL_I_MSK 0x00000030
+#define PAD33_SEL_I_I_MSK 0xffffffcf
+#define PAD33_SEL_I_SFT 4
+#define PAD33_SEL_I_HI 5
+#define PAD33_SEL_I_SZ 2
+#define PAD33_OD_MSK 0x00000100
+#define PAD33_OD_I_MSK 0xfffffeff
+#define PAD33_OD_SFT 8
+#define PAD33_OD_HI 8
+#define PAD33_OD_SZ 1
+#define PAD33_SEL_O_MSK 0x00003000
+#define PAD33_SEL_O_I_MSK 0xffffcfff
+#define PAD33_SEL_O_SFT 12
+#define PAD33_SEL_O_HI 13
+#define PAD33_SEL_O_SZ 2
+#define TEST_9_ID_MSK 0x10000000
+#define TEST_9_ID_I_MSK 0xefffffff
+#define TEST_9_ID_SFT 28
+#define TEST_9_ID_HI 28
+#define TEST_9_ID_SZ 1
+#define PAD34_OE_MSK 0x00000001
+#define PAD34_OE_I_MSK 0xfffffffe
+#define PAD34_OE_SFT 0
+#define PAD34_OE_HI 0
+#define PAD34_OE_SZ 1
+#define PAD34_PE_MSK 0x00000002
+#define PAD34_PE_I_MSK 0xfffffffd
+#define PAD34_PE_SFT 1
+#define PAD34_PE_HI 1
+#define PAD34_PE_SZ 1
+#define PAD34_DS_MSK 0x00000004
+#define PAD34_DS_I_MSK 0xfffffffb
+#define PAD34_DS_SFT 2
+#define PAD34_DS_HI 2
+#define PAD34_DS_SZ 1
+#define PAD34_IE_MSK 0x00000008
+#define PAD34_IE_I_MSK 0xfffffff7
+#define PAD34_IE_SFT 3
+#define PAD34_IE_HI 3
+#define PAD34_IE_SZ 1
+#define PAD34_SEL_I_MSK 0x00000030
+#define PAD34_SEL_I_I_MSK 0xffffffcf
+#define PAD34_SEL_I_SFT 4
+#define PAD34_SEL_I_HI 5
+#define PAD34_SEL_I_SZ 2
+#define PAD34_OD_MSK 0x00000100
+#define PAD34_OD_I_MSK 0xfffffeff
+#define PAD34_OD_SFT 8
+#define PAD34_OD_HI 8
+#define PAD34_OD_SZ 1
+#define PAD34_SEL_O_MSK 0x00003000
+#define PAD34_SEL_O_I_MSK 0xffffcfff
+#define PAD34_SEL_O_SFT 12
+#define PAD34_SEL_O_HI 13
+#define PAD34_SEL_O_SZ 2
+#define TEST_10_ID_MSK 0x10000000
+#define TEST_10_ID_I_MSK 0xefffffff
+#define TEST_10_ID_SFT 28
+#define TEST_10_ID_HI 28
+#define TEST_10_ID_SZ 1
+#define PAD42_OE_MSK 0x00000001
+#define PAD42_OE_I_MSK 0xfffffffe
+#define PAD42_OE_SFT 0
+#define PAD42_OE_HI 0
+#define PAD42_OE_SZ 1
+#define PAD42_PE_MSK 0x00000002
+#define PAD42_PE_I_MSK 0xfffffffd
+#define PAD42_PE_SFT 1
+#define PAD42_PE_HI 1
+#define PAD42_PE_SZ 1
+#define PAD42_DS_MSK 0x00000004
+#define PAD42_DS_I_MSK 0xfffffffb
+#define PAD42_DS_SFT 2
+#define PAD42_DS_HI 2
+#define PAD42_DS_SZ 1
+#define PAD42_IE_MSK 0x00000008
+#define PAD42_IE_I_MSK 0xfffffff7
+#define PAD42_IE_SFT 3
+#define PAD42_IE_HI 3
+#define PAD42_IE_SZ 1
+#define PAD42_SEL_I_MSK 0x00000030
+#define PAD42_SEL_I_I_MSK 0xffffffcf
+#define PAD42_SEL_I_SFT 4
+#define PAD42_SEL_I_HI 5
+#define PAD42_SEL_I_SZ 2
+#define PAD42_OD_MSK 0x00000100
+#define PAD42_OD_I_MSK 0xfffffeff
+#define PAD42_OD_SFT 8
+#define PAD42_OD_HI 8
+#define PAD42_OD_SZ 1
+#define PAD42_SEL_O_MSK 0x00001000
+#define PAD42_SEL_O_I_MSK 0xffffefff
+#define PAD42_SEL_O_SFT 12
+#define PAD42_SEL_O_HI 12
+#define PAD42_SEL_O_SZ 1
+#define TEST_11_ID_MSK 0x10000000
+#define TEST_11_ID_I_MSK 0xefffffff
+#define TEST_11_ID_SFT 28
+#define TEST_11_ID_HI 28
+#define TEST_11_ID_SZ 1
+#define PAD43_OE_MSK 0x00000001
+#define PAD43_OE_I_MSK 0xfffffffe
+#define PAD43_OE_SFT 0
+#define PAD43_OE_HI 0
+#define PAD43_OE_SZ 1
+#define PAD43_PE_MSK 0x00000002
+#define PAD43_PE_I_MSK 0xfffffffd
+#define PAD43_PE_SFT 1
+#define PAD43_PE_HI 1
+#define PAD43_PE_SZ 1
+#define PAD43_DS_MSK 0x00000004
+#define PAD43_DS_I_MSK 0xfffffffb
+#define PAD43_DS_SFT 2
+#define PAD43_DS_HI 2
+#define PAD43_DS_SZ 1
+#define PAD43_IE_MSK 0x00000008
+#define PAD43_IE_I_MSK 0xfffffff7
+#define PAD43_IE_SFT 3
+#define PAD43_IE_HI 3
+#define PAD43_IE_SZ 1
+#define PAD43_SEL_I_MSK 0x00000030
+#define PAD43_SEL_I_I_MSK 0xffffffcf
+#define PAD43_SEL_I_SFT 4
+#define PAD43_SEL_I_HI 5
+#define PAD43_SEL_I_SZ 2
+#define PAD43_OD_MSK 0x00000100
+#define PAD43_OD_I_MSK 0xfffffeff
+#define PAD43_OD_SFT 8
+#define PAD43_OD_HI 8
+#define PAD43_OD_SZ 1
+#define PAD43_SEL_O_MSK 0x00001000
+#define PAD43_SEL_O_I_MSK 0xffffefff
+#define PAD43_SEL_O_SFT 12
+#define PAD43_SEL_O_HI 12
+#define PAD43_SEL_O_SZ 1
+#define TEST_12_ID_MSK 0x10000000
+#define TEST_12_ID_I_MSK 0xefffffff
+#define TEST_12_ID_SFT 28
+#define TEST_12_ID_HI 28
+#define TEST_12_ID_SZ 1
+#define PAD44_OE_MSK 0x00000001
+#define PAD44_OE_I_MSK 0xfffffffe
+#define PAD44_OE_SFT 0
+#define PAD44_OE_HI 0
+#define PAD44_OE_SZ 1
+#define PAD44_PE_MSK 0x00000002
+#define PAD44_PE_I_MSK 0xfffffffd
+#define PAD44_PE_SFT 1
+#define PAD44_PE_HI 1
+#define PAD44_PE_SZ 1
+#define PAD44_DS_MSK 0x00000004
+#define PAD44_DS_I_MSK 0xfffffffb
+#define PAD44_DS_SFT 2
+#define PAD44_DS_HI 2
+#define PAD44_DS_SZ 1
+#define PAD44_IE_MSK 0x00000008
+#define PAD44_IE_I_MSK 0xfffffff7
+#define PAD44_IE_SFT 3
+#define PAD44_IE_HI 3
+#define PAD44_IE_SZ 1
+#define PAD44_SEL_I_MSK 0x00000030
+#define PAD44_SEL_I_I_MSK 0xffffffcf
+#define PAD44_SEL_I_SFT 4
+#define PAD44_SEL_I_HI 5
+#define PAD44_SEL_I_SZ 2
+#define PAD44_OD_MSK 0x00000100
+#define PAD44_OD_I_MSK 0xfffffeff
+#define PAD44_OD_SFT 8
+#define PAD44_OD_HI 8
+#define PAD44_OD_SZ 1
+#define PAD44_SEL_O_MSK 0x00003000
+#define PAD44_SEL_O_I_MSK 0xffffcfff
+#define PAD44_SEL_O_SFT 12
+#define PAD44_SEL_O_HI 13
+#define PAD44_SEL_O_SZ 2
+#define TEST_13_ID_MSK 0x10000000
+#define TEST_13_ID_I_MSK 0xefffffff
+#define TEST_13_ID_SFT 28
+#define TEST_13_ID_HI 28
+#define TEST_13_ID_SZ 1
+#define PAD45_OE_MSK 0x00000001
+#define PAD45_OE_I_MSK 0xfffffffe
+#define PAD45_OE_SFT 0
+#define PAD45_OE_HI 0
+#define PAD45_OE_SZ 1
+#define PAD45_PE_MSK 0x00000002
+#define PAD45_PE_I_MSK 0xfffffffd
+#define PAD45_PE_SFT 1
+#define PAD45_PE_HI 1
+#define PAD45_PE_SZ 1
+#define PAD45_DS_MSK 0x00000004
+#define PAD45_DS_I_MSK 0xfffffffb
+#define PAD45_DS_SFT 2
+#define PAD45_DS_HI 2
+#define PAD45_DS_SZ 1
+#define PAD45_IE_MSK 0x00000008
+#define PAD45_IE_I_MSK 0xfffffff7
+#define PAD45_IE_SFT 3
+#define PAD45_IE_HI 3
+#define PAD45_IE_SZ 1
+#define PAD45_SEL_I_MSK 0x00000030
+#define PAD45_SEL_I_I_MSK 0xffffffcf
+#define PAD45_SEL_I_SFT 4
+#define PAD45_SEL_I_HI 5
+#define PAD45_SEL_I_SZ 2
+#define PAD45_OD_MSK 0x00000100
+#define PAD45_OD_I_MSK 0xfffffeff
+#define PAD45_OD_SFT 8
+#define PAD45_OD_HI 8
+#define PAD45_OD_SZ 1
+#define PAD45_SEL_O_MSK 0x00003000
+#define PAD45_SEL_O_I_MSK 0xffffcfff
+#define PAD45_SEL_O_SFT 12
+#define PAD45_SEL_O_HI 13
+#define PAD45_SEL_O_SZ 2
+#define TEST_14_ID_MSK 0x10000000
+#define TEST_14_ID_I_MSK 0xefffffff
+#define TEST_14_ID_SFT 28
+#define TEST_14_ID_HI 28
+#define TEST_14_ID_SZ 1
+#define PAD46_OE_MSK 0x00000001
+#define PAD46_OE_I_MSK 0xfffffffe
+#define PAD46_OE_SFT 0
+#define PAD46_OE_HI 0
+#define PAD46_OE_SZ 1
+#define PAD46_PE_MSK 0x00000002
+#define PAD46_PE_I_MSK 0xfffffffd
+#define PAD46_PE_SFT 1
+#define PAD46_PE_HI 1
+#define PAD46_PE_SZ 1
+#define PAD46_DS_MSK 0x00000004
+#define PAD46_DS_I_MSK 0xfffffffb
+#define PAD46_DS_SFT 2
+#define PAD46_DS_HI 2
+#define PAD46_DS_SZ 1
+#define PAD46_IE_MSK 0x00000008
+#define PAD46_IE_I_MSK 0xfffffff7
+#define PAD46_IE_SFT 3
+#define PAD46_IE_HI 3
+#define PAD46_IE_SZ 1
+#define PAD46_SEL_I_MSK 0x00000030
+#define PAD46_SEL_I_I_MSK 0xffffffcf
+#define PAD46_SEL_I_SFT 4
+#define PAD46_SEL_I_HI 5
+#define PAD46_SEL_I_SZ 2
+#define PAD46_OD_MSK 0x00000100
+#define PAD46_OD_I_MSK 0xfffffeff
+#define PAD46_OD_SFT 8
+#define PAD46_OD_HI 8
+#define PAD46_OD_SZ 1
+#define PAD46_SEL_O_MSK 0x00003000
+#define PAD46_SEL_O_I_MSK 0xffffcfff
+#define PAD46_SEL_O_SFT 12
+#define PAD46_SEL_O_HI 13
+#define PAD46_SEL_O_SZ 2
+#define TEST_15_ID_MSK 0x10000000
+#define TEST_15_ID_I_MSK 0xefffffff
+#define TEST_15_ID_SFT 28
+#define TEST_15_ID_HI 28
+#define TEST_15_ID_SZ 1
+#define PAD47_OE_MSK 0x00000001
+#define PAD47_OE_I_MSK 0xfffffffe
+#define PAD47_OE_SFT 0
+#define PAD47_OE_HI 0
+#define PAD47_OE_SZ 1
+#define PAD47_PE_MSK 0x00000002
+#define PAD47_PE_I_MSK 0xfffffffd
+#define PAD47_PE_SFT 1
+#define PAD47_PE_HI 1
+#define PAD47_PE_SZ 1
+#define PAD47_DS_MSK 0x00000004
+#define PAD47_DS_I_MSK 0xfffffffb
+#define PAD47_DS_SFT 2
+#define PAD47_DS_HI 2
+#define PAD47_DS_SZ 1
+#define PAD47_SEL_I_MSK 0x00000030
+#define PAD47_SEL_I_I_MSK 0xffffffcf
+#define PAD47_SEL_I_SFT 4
+#define PAD47_SEL_I_HI 5
+#define PAD47_SEL_I_SZ 2
+#define PAD47_OD_MSK 0x00000100
+#define PAD47_OD_I_MSK 0xfffffeff
+#define PAD47_OD_SFT 8
+#define PAD47_OD_HI 8
+#define PAD47_OD_SZ 1
+#define PAD47_SEL_O_MSK 0x00003000
+#define PAD47_SEL_O_I_MSK 0xffffcfff
+#define PAD47_SEL_O_SFT 12
+#define PAD47_SEL_O_HI 13
+#define PAD47_SEL_O_SZ 2
+#define PAD47_SEL_OE_MSK 0x00100000
+#define PAD47_SEL_OE_I_MSK 0xffefffff
+#define PAD47_SEL_OE_SFT 20
+#define PAD47_SEL_OE_HI 20
+#define PAD47_SEL_OE_SZ 1
+#define GPIO_9_ID_MSK 0x10000000
+#define GPIO_9_ID_I_MSK 0xefffffff
+#define GPIO_9_ID_SFT 28
+#define GPIO_9_ID_HI 28
+#define GPIO_9_ID_SZ 1
+#define PAD48_OE_MSK 0x00000001
+#define PAD48_OE_I_MSK 0xfffffffe
+#define PAD48_OE_SFT 0
+#define PAD48_OE_HI 0
+#define PAD48_OE_SZ 1
+#define PAD48_PE_MSK 0x00000002
+#define PAD48_PE_I_MSK 0xfffffffd
+#define PAD48_PE_SFT 1
+#define PAD48_PE_HI 1
+#define PAD48_PE_SZ 1
+#define PAD48_DS_MSK 0x00000004
+#define PAD48_DS_I_MSK 0xfffffffb
+#define PAD48_DS_SFT 2
+#define PAD48_DS_HI 2
+#define PAD48_DS_SZ 1
+#define PAD48_IE_MSK 0x00000008
+#define PAD48_IE_I_MSK 0xfffffff7
+#define PAD48_IE_SFT 3
+#define PAD48_IE_HI 3
+#define PAD48_IE_SZ 1
+#define PAD48_SEL_I_MSK 0x00000070
+#define PAD48_SEL_I_I_MSK 0xffffff8f
+#define PAD48_SEL_I_SFT 4
+#define PAD48_SEL_I_HI 6
+#define PAD48_SEL_I_SZ 3
+#define PAD48_OD_MSK 0x00000100
+#define PAD48_OD_I_MSK 0xfffffeff
+#define PAD48_OD_SFT 8
+#define PAD48_OD_HI 8
+#define PAD48_OD_SZ 1
+#define PAD48_PE_SEL_MSK 0x00000800
+#define PAD48_PE_SEL_I_MSK 0xfffff7ff
+#define PAD48_PE_SEL_SFT 11
+#define PAD48_PE_SEL_HI 11
+#define PAD48_PE_SEL_SZ 1
+#define PAD48_SEL_O_MSK 0x00003000
+#define PAD48_SEL_O_I_MSK 0xffffcfff
+#define PAD48_SEL_O_SFT 12
+#define PAD48_SEL_O_HI 13
+#define PAD48_SEL_O_SZ 2
+#define PAD48_SEL_OE_MSK 0x00100000
+#define PAD48_SEL_OE_I_MSK 0xffefffff
+#define PAD48_SEL_OE_SFT 20
+#define PAD48_SEL_OE_HI 20
+#define PAD48_SEL_OE_SZ 1
+#define GPIO_10_ID_MSK 0x10000000
+#define GPIO_10_ID_I_MSK 0xefffffff
+#define GPIO_10_ID_SFT 28
+#define GPIO_10_ID_HI 28
+#define GPIO_10_ID_SZ 1
+#define PAD49_OE_MSK 0x00000001
+#define PAD49_OE_I_MSK 0xfffffffe
+#define PAD49_OE_SFT 0
+#define PAD49_OE_HI 0
+#define PAD49_OE_SZ 1
+#define PAD49_PE_MSK 0x00000002
+#define PAD49_PE_I_MSK 0xfffffffd
+#define PAD49_PE_SFT 1
+#define PAD49_PE_HI 1
+#define PAD49_PE_SZ 1
+#define PAD49_DS_MSK 0x00000004
+#define PAD49_DS_I_MSK 0xfffffffb
+#define PAD49_DS_SFT 2
+#define PAD49_DS_HI 2
+#define PAD49_DS_SZ 1
+#define PAD49_IE_MSK 0x00000008
+#define PAD49_IE_I_MSK 0xfffffff7
+#define PAD49_IE_SFT 3
+#define PAD49_IE_HI 3
+#define PAD49_IE_SZ 1
+#define PAD49_SEL_I_MSK 0x00000070
+#define PAD49_SEL_I_I_MSK 0xffffff8f
+#define PAD49_SEL_I_SFT 4
+#define PAD49_SEL_I_HI 6
+#define PAD49_SEL_I_SZ 3
+#define PAD49_OD_MSK 0x00000100
+#define PAD49_OD_I_MSK 0xfffffeff
+#define PAD49_OD_SFT 8
+#define PAD49_OD_HI 8
+#define PAD49_OD_SZ 1
+#define PAD49_SEL_O_MSK 0x00003000
+#define PAD49_SEL_O_I_MSK 0xffffcfff
+#define PAD49_SEL_O_SFT 12
+#define PAD49_SEL_O_HI 13
+#define PAD49_SEL_O_SZ 2
+#define PAD49_SEL_OE_MSK 0x00100000
+#define PAD49_SEL_OE_I_MSK 0xffefffff
+#define PAD49_SEL_OE_SFT 20
+#define PAD49_SEL_OE_HI 20
+#define PAD49_SEL_OE_SZ 1
+#define GPIO_11_ID_MSK 0x10000000
+#define GPIO_11_ID_I_MSK 0xefffffff
+#define GPIO_11_ID_SFT 28
+#define GPIO_11_ID_HI 28
+#define GPIO_11_ID_SZ 1
+#define PAD50_OE_MSK 0x00000001
+#define PAD50_OE_I_MSK 0xfffffffe
+#define PAD50_OE_SFT 0
+#define PAD50_OE_HI 0
+#define PAD50_OE_SZ 1
+#define PAD50_PE_MSK 0x00000002
+#define PAD50_PE_I_MSK 0xfffffffd
+#define PAD50_PE_SFT 1
+#define PAD50_PE_HI 1
+#define PAD50_PE_SZ 1
+#define PAD50_DS_MSK 0x00000004
+#define PAD50_DS_I_MSK 0xfffffffb
+#define PAD50_DS_SFT 2
+#define PAD50_DS_HI 2
+#define PAD50_DS_SZ 1
+#define PAD50_IE_MSK 0x00000008
+#define PAD50_IE_I_MSK 0xfffffff7
+#define PAD50_IE_SFT 3
+#define PAD50_IE_HI 3
+#define PAD50_IE_SZ 1
+#define PAD50_SEL_I_MSK 0x00000070
+#define PAD50_SEL_I_I_MSK 0xffffff8f
+#define PAD50_SEL_I_SFT 4
+#define PAD50_SEL_I_HI 6
+#define PAD50_SEL_I_SZ 3
+#define PAD50_OD_MSK 0x00000100
+#define PAD50_OD_I_MSK 0xfffffeff
+#define PAD50_OD_SFT 8
+#define PAD50_OD_HI 8
+#define PAD50_OD_SZ 1
+#define PAD50_SEL_O_MSK 0x00003000
+#define PAD50_SEL_O_I_MSK 0xffffcfff
+#define PAD50_SEL_O_SFT 12
+#define PAD50_SEL_O_HI 13
+#define PAD50_SEL_O_SZ 2
+#define PAD50_SEL_OE_MSK 0x00100000
+#define PAD50_SEL_OE_I_MSK 0xffefffff
+#define PAD50_SEL_OE_SFT 20
+#define PAD50_SEL_OE_HI 20
+#define PAD50_SEL_OE_SZ 1
+#define GPIO_12_ID_MSK 0x10000000
+#define GPIO_12_ID_I_MSK 0xefffffff
+#define GPIO_12_ID_SFT 28
+#define GPIO_12_ID_HI 28
+#define GPIO_12_ID_SZ 1
+#define PAD51_OE_MSK 0x00000001
+#define PAD51_OE_I_MSK 0xfffffffe
+#define PAD51_OE_SFT 0
+#define PAD51_OE_HI 0
+#define PAD51_OE_SZ 1
+#define PAD51_PE_MSK 0x00000002
+#define PAD51_PE_I_MSK 0xfffffffd
+#define PAD51_PE_SFT 1
+#define PAD51_PE_HI 1
+#define PAD51_PE_SZ 1
+#define PAD51_DS_MSK 0x00000004
+#define PAD51_DS_I_MSK 0xfffffffb
+#define PAD51_DS_SFT 2
+#define PAD51_DS_HI 2
+#define PAD51_DS_SZ 1
+#define PAD51_IE_MSK 0x00000008
+#define PAD51_IE_I_MSK 0xfffffff7
+#define PAD51_IE_SFT 3
+#define PAD51_IE_HI 3
+#define PAD51_IE_SZ 1
+#define PAD51_SEL_I_MSK 0x00000030
+#define PAD51_SEL_I_I_MSK 0xffffffcf
+#define PAD51_SEL_I_SFT 4
+#define PAD51_SEL_I_HI 5
+#define PAD51_SEL_I_SZ 2
+#define PAD51_OD_MSK 0x00000100
+#define PAD51_OD_I_MSK 0xfffffeff
+#define PAD51_OD_SFT 8
+#define PAD51_OD_HI 8
+#define PAD51_OD_SZ 1
+#define PAD51_SEL_O_MSK 0x00001000
+#define PAD51_SEL_O_I_MSK 0xffffefff
+#define PAD51_SEL_O_SFT 12
+#define PAD51_SEL_O_HI 12
+#define PAD51_SEL_O_SZ 1
+#define PAD51_SEL_OE_MSK 0x00100000
+#define PAD51_SEL_OE_I_MSK 0xffefffff
+#define PAD51_SEL_OE_SFT 20
+#define PAD51_SEL_OE_HI 20
+#define PAD51_SEL_OE_SZ 1
+#define GPIO_13_ID_MSK 0x10000000
+#define GPIO_13_ID_I_MSK 0xefffffff
+#define GPIO_13_ID_SFT 28
+#define GPIO_13_ID_HI 28
+#define GPIO_13_ID_SZ 1
+#define PAD52_OE_MSK 0x00000001
+#define PAD52_OE_I_MSK 0xfffffffe
+#define PAD52_OE_SFT 0
+#define PAD52_OE_HI 0
+#define PAD52_OE_SZ 1
+#define PAD52_PE_MSK 0x00000002
+#define PAD52_PE_I_MSK 0xfffffffd
+#define PAD52_PE_SFT 1
+#define PAD52_PE_HI 1
+#define PAD52_PE_SZ 1
+#define PAD52_DS_MSK 0x00000004
+#define PAD52_DS_I_MSK 0xfffffffb
+#define PAD52_DS_SFT 2
+#define PAD52_DS_HI 2
+#define PAD52_DS_SZ 1
+#define PAD52_SEL_I_MSK 0x00000030
+#define PAD52_SEL_I_I_MSK 0xffffffcf
+#define PAD52_SEL_I_SFT 4
+#define PAD52_SEL_I_HI 5
+#define PAD52_SEL_I_SZ 2
+#define PAD52_OD_MSK 0x00000100
+#define PAD52_OD_I_MSK 0xfffffeff
+#define PAD52_OD_SFT 8
+#define PAD52_OD_HI 8
+#define PAD52_OD_SZ 1
+#define PAD52_SEL_O_MSK 0x00001000
+#define PAD52_SEL_O_I_MSK 0xffffefff
+#define PAD52_SEL_O_SFT 12
+#define PAD52_SEL_O_HI 12
+#define PAD52_SEL_O_SZ 1
+#define PAD52_SEL_OE_MSK 0x00100000
+#define PAD52_SEL_OE_I_MSK 0xffefffff
+#define PAD52_SEL_OE_SFT 20
+#define PAD52_SEL_OE_HI 20
+#define PAD52_SEL_OE_SZ 1
+#define GPIO_14_ID_MSK 0x10000000
+#define GPIO_14_ID_I_MSK 0xefffffff
+#define GPIO_14_ID_SFT 28
+#define GPIO_14_ID_HI 28
+#define GPIO_14_ID_SZ 1
+#define PAD53_OE_MSK 0x00000001
+#define PAD53_OE_I_MSK 0xfffffffe
+#define PAD53_OE_SFT 0
+#define PAD53_OE_HI 0
+#define PAD53_OE_SZ 1
+#define PAD53_PE_MSK 0x00000002
+#define PAD53_PE_I_MSK 0xfffffffd
+#define PAD53_PE_SFT 1
+#define PAD53_PE_HI 1
+#define PAD53_PE_SZ 1
+#define PAD53_DS_MSK 0x00000004
+#define PAD53_DS_I_MSK 0xfffffffb
+#define PAD53_DS_SFT 2
+#define PAD53_DS_HI 2
+#define PAD53_DS_SZ 1
+#define PAD53_IE_MSK 0x00000008
+#define PAD53_IE_I_MSK 0xfffffff7
+#define PAD53_IE_SFT 3
+#define PAD53_IE_HI 3
+#define PAD53_IE_SZ 1
+#define PAD53_SEL_I_MSK 0x00000030
+#define PAD53_SEL_I_I_MSK 0xffffffcf
+#define PAD53_SEL_I_SFT 4
+#define PAD53_SEL_I_HI 5
+#define PAD53_SEL_I_SZ 2
+#define PAD53_OD_MSK 0x00000100
+#define PAD53_OD_I_MSK 0xfffffeff
+#define PAD53_OD_SFT 8
+#define PAD53_OD_HI 8
+#define PAD53_OD_SZ 1
+#define PAD53_SEL_O_MSK 0x00001000
+#define PAD53_SEL_O_I_MSK 0xffffefff
+#define PAD53_SEL_O_SFT 12
+#define PAD53_SEL_O_HI 12
+#define PAD53_SEL_O_SZ 1
+#define JTAG_TMS_ID_MSK 0x10000000
+#define JTAG_TMS_ID_I_MSK 0xefffffff
+#define JTAG_TMS_ID_SFT 28
+#define JTAG_TMS_ID_HI 28
+#define JTAG_TMS_ID_SZ 1
+#define PAD54_OE_MSK 0x00000001
+#define PAD54_OE_I_MSK 0xfffffffe
+#define PAD54_OE_SFT 0
+#define PAD54_OE_HI 0
+#define PAD54_OE_SZ 1
+#define PAD54_PE_MSK 0x00000002
+#define PAD54_PE_I_MSK 0xfffffffd
+#define PAD54_PE_SFT 1
+#define PAD54_PE_HI 1
+#define PAD54_PE_SZ 1
+#define PAD54_DS_MSK 0x00000004
+#define PAD54_DS_I_MSK 0xfffffffb
+#define PAD54_DS_SFT 2
+#define PAD54_DS_HI 2
+#define PAD54_DS_SZ 1
+#define PAD54_OD_MSK 0x00000100
+#define PAD54_OD_I_MSK 0xfffffeff
+#define PAD54_OD_SFT 8
+#define PAD54_OD_HI 8
+#define PAD54_OD_SZ 1
+#define PAD54_SEL_O_MSK 0x00003000
+#define PAD54_SEL_O_I_MSK 0xffffcfff
+#define PAD54_SEL_O_SFT 12
+#define PAD54_SEL_O_HI 13
+#define PAD54_SEL_O_SZ 2
+#define JTAG_TCK_ID_MSK 0x10000000
+#define JTAG_TCK_ID_I_MSK 0xefffffff
+#define JTAG_TCK_ID_SFT 28
+#define JTAG_TCK_ID_HI 28
+#define JTAG_TCK_ID_SZ 1
+#define PAD56_PE_MSK 0x00000002
+#define PAD56_PE_I_MSK 0xfffffffd
+#define PAD56_PE_SFT 1
+#define PAD56_PE_HI 1
+#define PAD56_PE_SZ 1
+#define PAD56_DS_MSK 0x00000004
+#define PAD56_DS_I_MSK 0xfffffffb
+#define PAD56_DS_SFT 2
+#define PAD56_DS_HI 2
+#define PAD56_DS_SZ 1
+#define PAD56_SEL_I_MSK 0x00000010
+#define PAD56_SEL_I_I_MSK 0xffffffef
+#define PAD56_SEL_I_SFT 4
+#define PAD56_SEL_I_HI 4
+#define PAD56_SEL_I_SZ 1
+#define PAD56_OD_MSK 0x00000100
+#define PAD56_OD_I_MSK 0xfffffeff
+#define PAD56_OD_SFT 8
+#define PAD56_OD_HI 8
+#define PAD56_OD_SZ 1
+#define JTAG_TDI_ID_MSK 0x10000000
+#define JTAG_TDI_ID_I_MSK 0xefffffff
+#define JTAG_TDI_ID_SFT 28
+#define JTAG_TDI_ID_HI 28
+#define JTAG_TDI_ID_SZ 1
+#define PAD57_OE_MSK 0x00000001
+#define PAD57_OE_I_MSK 0xfffffffe
+#define PAD57_OE_SFT 0
+#define PAD57_OE_HI 0
+#define PAD57_OE_SZ 1
+#define PAD57_PE_MSK 0x00000002
+#define PAD57_PE_I_MSK 0xfffffffd
+#define PAD57_PE_SFT 1
+#define PAD57_PE_HI 1
+#define PAD57_PE_SZ 1
+#define PAD57_DS_MSK 0x00000004
+#define PAD57_DS_I_MSK 0xfffffffb
+#define PAD57_DS_SFT 2
+#define PAD57_DS_HI 2
+#define PAD57_DS_SZ 1
+#define PAD57_IE_MSK 0x00000008
+#define PAD57_IE_I_MSK 0xfffffff7
+#define PAD57_IE_SFT 3
+#define PAD57_IE_HI 3
+#define PAD57_IE_SZ 1
+#define PAD57_SEL_I_MSK 0x00000030
+#define PAD57_SEL_I_I_MSK 0xffffffcf
+#define PAD57_SEL_I_SFT 4
+#define PAD57_SEL_I_HI 5
+#define PAD57_SEL_I_SZ 2
+#define PAD57_OD_MSK 0x00000100
+#define PAD57_OD_I_MSK 0xfffffeff
+#define PAD57_OD_SFT 8
+#define PAD57_OD_HI 8
+#define PAD57_OD_SZ 1
+#define PAD57_SEL_O_MSK 0x00003000
+#define PAD57_SEL_O_I_MSK 0xffffcfff
+#define PAD57_SEL_O_SFT 12
+#define PAD57_SEL_O_HI 13
+#define PAD57_SEL_O_SZ 2
+#define PAD57_SEL_OE_MSK 0x00100000
+#define PAD57_SEL_OE_I_MSK 0xffefffff
+#define PAD57_SEL_OE_SFT 20
+#define PAD57_SEL_OE_HI 20
+#define PAD57_SEL_OE_SZ 1
+#define JTAG_TDO_ID_MSK 0x10000000
+#define JTAG_TDO_ID_I_MSK 0xefffffff
+#define JTAG_TDO_ID_SFT 28
+#define JTAG_TDO_ID_HI 28
+#define JTAG_TDO_ID_SZ 1
+#define PAD58_OE_MSK 0x00000001
+#define PAD58_OE_I_MSK 0xfffffffe
+#define PAD58_OE_SFT 0
+#define PAD58_OE_HI 0
+#define PAD58_OE_SZ 1
+#define PAD58_PE_MSK 0x00000002
+#define PAD58_PE_I_MSK 0xfffffffd
+#define PAD58_PE_SFT 1
+#define PAD58_PE_HI 1
+#define PAD58_PE_SZ 1
+#define PAD58_DS_MSK 0x00000004
+#define PAD58_DS_I_MSK 0xfffffffb
+#define PAD58_DS_SFT 2
+#define PAD58_DS_HI 2
+#define PAD58_DS_SZ 1
+#define PAD58_IE_MSK 0x00000008
+#define PAD58_IE_I_MSK 0xfffffff7
+#define PAD58_IE_SFT 3
+#define PAD58_IE_HI 3
+#define PAD58_IE_SZ 1
+#define PAD58_SEL_I_MSK 0x00000030
+#define PAD58_SEL_I_I_MSK 0xffffffcf
+#define PAD58_SEL_I_SFT 4
+#define PAD58_SEL_I_HI 5
+#define PAD58_SEL_I_SZ 2
+#define PAD58_OD_MSK 0x00000100
+#define PAD58_OD_I_MSK 0xfffffeff
+#define PAD58_OD_SFT 8
+#define PAD58_OD_HI 8
+#define PAD58_OD_SZ 1
+#define PAD58_SEL_O_MSK 0x00001000
+#define PAD58_SEL_O_I_MSK 0xffffefff
+#define PAD58_SEL_O_SFT 12
+#define PAD58_SEL_O_HI 12
+#define PAD58_SEL_O_SZ 1
+#define TEST_16_ID_MSK 0x10000000
+#define TEST_16_ID_I_MSK 0xefffffff
+#define TEST_16_ID_SFT 28
+#define TEST_16_ID_HI 28
+#define TEST_16_ID_SZ 1
+#define PAD59_OE_MSK 0x00000001
+#define PAD59_OE_I_MSK 0xfffffffe
+#define PAD59_OE_SFT 0
+#define PAD59_OE_HI 0
+#define PAD59_OE_SZ 1
+#define PAD59_PE_MSK 0x00000002
+#define PAD59_PE_I_MSK 0xfffffffd
+#define PAD59_PE_SFT 1
+#define PAD59_PE_HI 1
+#define PAD59_PE_SZ 1
+#define PAD59_DS_MSK 0x00000004
+#define PAD59_DS_I_MSK 0xfffffffb
+#define PAD59_DS_SFT 2
+#define PAD59_DS_HI 2
+#define PAD59_DS_SZ 1
+#define PAD59_IE_MSK 0x00000008
+#define PAD59_IE_I_MSK 0xfffffff7
+#define PAD59_IE_SFT 3
+#define PAD59_IE_HI 3
+#define PAD59_IE_SZ 1
+#define PAD59_SEL_I_MSK 0x00000030
+#define PAD59_SEL_I_I_MSK 0xffffffcf
+#define PAD59_SEL_I_SFT 4
+#define PAD59_SEL_I_HI 5
+#define PAD59_SEL_I_SZ 2
+#define PAD59_OD_MSK 0x00000100
+#define PAD59_OD_I_MSK 0xfffffeff
+#define PAD59_OD_SFT 8
+#define PAD59_OD_HI 8
+#define PAD59_OD_SZ 1
+#define PAD59_SEL_O_MSK 0x00001000
+#define PAD59_SEL_O_I_MSK 0xffffefff
+#define PAD59_SEL_O_SFT 12
+#define PAD59_SEL_O_HI 12
+#define PAD59_SEL_O_SZ 1
+#define TEST_17_ID_MSK 0x10000000
+#define TEST_17_ID_I_MSK 0xefffffff
+#define TEST_17_ID_SFT 28
+#define TEST_17_ID_HI 28
+#define TEST_17_ID_SZ 1
+#define PAD60_OE_MSK 0x00000001
+#define PAD60_OE_I_MSK 0xfffffffe
+#define PAD60_OE_SFT 0
+#define PAD60_OE_HI 0
+#define PAD60_OE_SZ 1
+#define PAD60_PE_MSK 0x00000002
+#define PAD60_PE_I_MSK 0xfffffffd
+#define PAD60_PE_SFT 1
+#define PAD60_PE_HI 1
+#define PAD60_PE_SZ 1
+#define PAD60_DS_MSK 0x00000004
+#define PAD60_DS_I_MSK 0xfffffffb
+#define PAD60_DS_SFT 2
+#define PAD60_DS_HI 2
+#define PAD60_DS_SZ 1
+#define PAD60_IE_MSK 0x00000008
+#define PAD60_IE_I_MSK 0xfffffff7
+#define PAD60_IE_SFT 3
+#define PAD60_IE_HI 3
+#define PAD60_IE_SZ 1
+#define PAD60_SEL_I_MSK 0x00000030
+#define PAD60_SEL_I_I_MSK 0xffffffcf
+#define PAD60_SEL_I_SFT 4
+#define PAD60_SEL_I_HI 5
+#define PAD60_SEL_I_SZ 2
+#define PAD60_OD_MSK 0x00000100
+#define PAD60_OD_I_MSK 0xfffffeff
+#define PAD60_OD_SFT 8
+#define PAD60_OD_HI 8
+#define PAD60_OD_SZ 1
+#define PAD60_SEL_O_MSK 0x00001000
+#define PAD60_SEL_O_I_MSK 0xffffefff
+#define PAD60_SEL_O_SFT 12
+#define PAD60_SEL_O_HI 12
+#define PAD60_SEL_O_SZ 1
+#define TEST_18_ID_MSK 0x10000000
+#define TEST_18_ID_I_MSK 0xefffffff
+#define TEST_18_ID_SFT 28
+#define TEST_18_ID_HI 28
+#define TEST_18_ID_SZ 1
+#define PAD61_OE_MSK 0x00000001
+#define PAD61_OE_I_MSK 0xfffffffe
+#define PAD61_OE_SFT 0
+#define PAD61_OE_HI 0
+#define PAD61_OE_SZ 1
+#define PAD61_PE_MSK 0x00000002
+#define PAD61_PE_I_MSK 0xfffffffd
+#define PAD61_PE_SFT 1
+#define PAD61_PE_HI 1
+#define PAD61_PE_SZ 1
+#define PAD61_DS_MSK 0x00000004
+#define PAD61_DS_I_MSK 0xfffffffb
+#define PAD61_DS_SFT 2
+#define PAD61_DS_HI 2
+#define PAD61_DS_SZ 1
+#define PAD61_IE_MSK 0x00000008
+#define PAD61_IE_I_MSK 0xfffffff7
+#define PAD61_IE_SFT 3
+#define PAD61_IE_HI 3
+#define PAD61_IE_SZ 1
+#define PAD61_SEL_I_MSK 0x00000010
+#define PAD61_SEL_I_I_MSK 0xffffffef
+#define PAD61_SEL_I_SFT 4
+#define PAD61_SEL_I_HI 4
+#define PAD61_SEL_I_SZ 1
+#define PAD61_OD_MSK 0x00000100
+#define PAD61_OD_I_MSK 0xfffffeff
+#define PAD61_OD_SFT 8
+#define PAD61_OD_HI 8
+#define PAD61_OD_SZ 1
+#define PAD61_SEL_O_MSK 0x00003000
+#define PAD61_SEL_O_I_MSK 0xffffcfff
+#define PAD61_SEL_O_SFT 12
+#define PAD61_SEL_O_HI 13
+#define PAD61_SEL_O_SZ 2
+#define TEST_19_ID_MSK 0x10000000
+#define TEST_19_ID_I_MSK 0xefffffff
+#define TEST_19_ID_SFT 28
+#define TEST_19_ID_HI 28
+#define TEST_19_ID_SZ 1
+#define PAD62_OE_MSK 0x00000001
+#define PAD62_OE_I_MSK 0xfffffffe
+#define PAD62_OE_SFT 0
+#define PAD62_OE_HI 0
+#define PAD62_OE_SZ 1
+#define PAD62_PE_MSK 0x00000002
+#define PAD62_PE_I_MSK 0xfffffffd
+#define PAD62_PE_SFT 1
+#define PAD62_PE_HI 1
+#define PAD62_PE_SZ 1
+#define PAD62_DS_MSK 0x00000004
+#define PAD62_DS_I_MSK 0xfffffffb
+#define PAD62_DS_SFT 2
+#define PAD62_DS_HI 2
+#define PAD62_DS_SZ 1
+#define PAD62_IE_MSK 0x00000008
+#define PAD62_IE_I_MSK 0xfffffff7
+#define PAD62_IE_SFT 3
+#define PAD62_IE_HI 3
+#define PAD62_IE_SZ 1
+#define PAD62_SEL_I_MSK 0x00000010
+#define PAD62_SEL_I_I_MSK 0xffffffef
+#define PAD62_SEL_I_SFT 4
+#define PAD62_SEL_I_HI 4
+#define PAD62_SEL_I_SZ 1
+#define PAD62_OD_MSK 0x00000100
+#define PAD62_OD_I_MSK 0xfffffeff
+#define PAD62_OD_SFT 8
+#define PAD62_OD_HI 8
+#define PAD62_OD_SZ 1
+#define PAD62_SEL_O_MSK 0x00001000
+#define PAD62_SEL_O_I_MSK 0xffffefff
+#define PAD62_SEL_O_SFT 12
+#define PAD62_SEL_O_HI 12
+#define PAD62_SEL_O_SZ 1
+#define TEST_20_ID_MSK 0x10000000
+#define TEST_20_ID_I_MSK 0xefffffff
+#define TEST_20_ID_SFT 28
+#define TEST_20_ID_HI 28
+#define TEST_20_ID_SZ 1
+#define PAD64_OE_MSK 0x00000001
+#define PAD64_OE_I_MSK 0xfffffffe
+#define PAD64_OE_SFT 0
+#define PAD64_OE_HI 0
+#define PAD64_OE_SZ 1
+#define PAD64_PE_MSK 0x00000002
+#define PAD64_PE_I_MSK 0xfffffffd
+#define PAD64_PE_SFT 1
+#define PAD64_PE_HI 1
+#define PAD64_PE_SZ 1
+#define PAD64_DS_MSK 0x00000004
+#define PAD64_DS_I_MSK 0xfffffffb
+#define PAD64_DS_SFT 2
+#define PAD64_DS_HI 2
+#define PAD64_DS_SZ 1
+#define PAD64_IE_MSK 0x00000008
+#define PAD64_IE_I_MSK 0xfffffff7
+#define PAD64_IE_SFT 3
+#define PAD64_IE_HI 3
+#define PAD64_IE_SZ 1
+#define PAD64_SEL_I_MSK 0x00000070
+#define PAD64_SEL_I_I_MSK 0xffffff8f
+#define PAD64_SEL_I_SFT 4
+#define PAD64_SEL_I_HI 6
+#define PAD64_SEL_I_SZ 3
+#define PAD64_OD_MSK 0x00000100
+#define PAD64_OD_I_MSK 0xfffffeff
+#define PAD64_OD_SFT 8
+#define PAD64_OD_HI 8
+#define PAD64_OD_SZ 1
+#define PAD64_SEL_O_MSK 0x00003000
+#define PAD64_SEL_O_I_MSK 0xffffcfff
+#define PAD64_SEL_O_SFT 12
+#define PAD64_SEL_O_HI 13
+#define PAD64_SEL_O_SZ 2
+#define PAD64_SEL_OE_MSK 0x00100000
+#define PAD64_SEL_OE_I_MSK 0xffefffff
+#define PAD64_SEL_OE_SFT 20
+#define PAD64_SEL_OE_HI 20
+#define PAD64_SEL_OE_SZ 1
+#define GPIO_15_IP_ID_MSK 0x10000000
+#define GPIO_15_IP_ID_I_MSK 0xefffffff
+#define GPIO_15_IP_ID_SFT 28
+#define GPIO_15_IP_ID_HI 28
+#define GPIO_15_IP_ID_SZ 1
+#define PAD65_OE_MSK 0x00000001
+#define PAD65_OE_I_MSK 0xfffffffe
+#define PAD65_OE_SFT 0
+#define PAD65_OE_HI 0
+#define PAD65_OE_SZ 1
+#define PAD65_PE_MSK 0x00000002
+#define PAD65_PE_I_MSK 0xfffffffd
+#define PAD65_PE_SFT 1
+#define PAD65_PE_HI 1
+#define PAD65_PE_SZ 1
+#define PAD65_DS_MSK 0x00000004
+#define PAD65_DS_I_MSK 0xfffffffb
+#define PAD65_DS_SFT 2
+#define PAD65_DS_HI 2
+#define PAD65_DS_SZ 1
+#define PAD65_IE_MSK 0x00000008
+#define PAD65_IE_I_MSK 0xfffffff7
+#define PAD65_IE_SFT 3
+#define PAD65_IE_HI 3
+#define PAD65_IE_SZ 1
+#define PAD65_SEL_I_MSK 0x00000070
+#define PAD65_SEL_I_I_MSK 0xffffff8f
+#define PAD65_SEL_I_SFT 4
+#define PAD65_SEL_I_HI 6
+#define PAD65_SEL_I_SZ 3
+#define PAD65_OD_MSK 0x00000100
+#define PAD65_OD_I_MSK 0xfffffeff
+#define PAD65_OD_SFT 8
+#define PAD65_OD_HI 8
+#define PAD65_OD_SZ 1
+#define PAD65_SEL_O_MSK 0x00001000
+#define PAD65_SEL_O_I_MSK 0xffffefff
+#define PAD65_SEL_O_SFT 12
+#define PAD65_SEL_O_HI 12
+#define PAD65_SEL_O_SZ 1
+#define GPIO_TEST_7_IN_ID_MSK 0x10000000
+#define GPIO_TEST_7_IN_ID_I_MSK 0xefffffff
+#define GPIO_TEST_7_IN_ID_SFT 28
+#define GPIO_TEST_7_IN_ID_HI 28
+#define GPIO_TEST_7_IN_ID_SZ 1
+#define PAD66_OE_MSK 0x00000001
+#define PAD66_OE_I_MSK 0xfffffffe
+#define PAD66_OE_SFT 0
+#define PAD66_OE_HI 0
+#define PAD66_OE_SZ 1
+#define PAD66_PE_MSK 0x00000002
+#define PAD66_PE_I_MSK 0xfffffffd
+#define PAD66_PE_SFT 1
+#define PAD66_PE_HI 1
+#define PAD66_PE_SZ 1
+#define PAD66_DS_MSK 0x00000004
+#define PAD66_DS_I_MSK 0xfffffffb
+#define PAD66_DS_SFT 2
+#define PAD66_DS_HI 2
+#define PAD66_DS_SZ 1
+#define PAD66_IE_MSK 0x00000008
+#define PAD66_IE_I_MSK 0xfffffff7
+#define PAD66_IE_SFT 3
+#define PAD66_IE_HI 3
+#define PAD66_IE_SZ 1
+#define PAD66_SEL_I_MSK 0x00000030
+#define PAD66_SEL_I_I_MSK 0xffffffcf
+#define PAD66_SEL_I_SFT 4
+#define PAD66_SEL_I_HI 5
+#define PAD66_SEL_I_SZ 2
+#define PAD66_OD_MSK 0x00000100
+#define PAD66_OD_I_MSK 0xfffffeff
+#define PAD66_OD_SFT 8
+#define PAD66_OD_HI 8
+#define PAD66_OD_SZ 1
+#define PAD66_SEL_O_MSK 0x00003000
+#define PAD66_SEL_O_I_MSK 0xffffcfff
+#define PAD66_SEL_O_SFT 12
+#define PAD66_SEL_O_HI 13
+#define PAD66_SEL_O_SZ 2
+#define GPIO_17_QP_ID_MSK 0x10000000
+#define GPIO_17_QP_ID_I_MSK 0xefffffff
+#define GPIO_17_QP_ID_SFT 28
+#define GPIO_17_QP_ID_HI 28
+#define GPIO_17_QP_ID_SZ 1
+#define PAD68_OE_MSK 0x00000001
+#define PAD68_OE_I_MSK 0xfffffffe
+#define PAD68_OE_SFT 0
+#define PAD68_OE_HI 0
+#define PAD68_OE_SZ 1
+#define PAD68_PE_MSK 0x00000002
+#define PAD68_PE_I_MSK 0xfffffffd
+#define PAD68_PE_SFT 1
+#define PAD68_PE_HI 1
+#define PAD68_PE_SZ 1
+#define PAD68_DS_MSK 0x00000004
+#define PAD68_DS_I_MSK 0xfffffffb
+#define PAD68_DS_SFT 2
+#define PAD68_DS_HI 2
+#define PAD68_DS_SZ 1
+#define PAD68_IE_MSK 0x00000008
+#define PAD68_IE_I_MSK 0xfffffff7
+#define PAD68_IE_SFT 3
+#define PAD68_IE_HI 3
+#define PAD68_IE_SZ 1
+#define PAD68_OD_MSK 0x00000100
+#define PAD68_OD_I_MSK 0xfffffeff
+#define PAD68_OD_SFT 8
+#define PAD68_OD_HI 8
+#define PAD68_OD_SZ 1
+#define PAD68_SEL_O_MSK 0x00001000
+#define PAD68_SEL_O_I_MSK 0xffffefff
+#define PAD68_SEL_O_SFT 12
+#define PAD68_SEL_O_HI 12
+#define PAD68_SEL_O_SZ 1
+#define GPIO_19_ID_MSK 0x10000000
+#define GPIO_19_ID_I_MSK 0xefffffff
+#define GPIO_19_ID_SFT 28
+#define GPIO_19_ID_HI 28
+#define GPIO_19_ID_SZ 1
+#define PAD67_OE_MSK 0x00000001
+#define PAD67_OE_I_MSK 0xfffffffe
+#define PAD67_OE_SFT 0
+#define PAD67_OE_HI 0
+#define PAD67_OE_SZ 1
+#define PAD67_PE_MSK 0x00000002
+#define PAD67_PE_I_MSK 0xfffffffd
+#define PAD67_PE_SFT 1
+#define PAD67_PE_HI 1
+#define PAD67_PE_SZ 1
+#define PAD67_DS_MSK 0x00000004
+#define PAD67_DS_I_MSK 0xfffffffb
+#define PAD67_DS_SFT 2
+#define PAD67_DS_HI 2
+#define PAD67_DS_SZ 1
+#define PAD67_IE_MSK 0x00000008
+#define PAD67_IE_I_MSK 0xfffffff7
+#define PAD67_IE_SFT 3
+#define PAD67_IE_HI 3
+#define PAD67_IE_SZ 1
+#define PAD67_SEL_I_MSK 0x00000070
+#define PAD67_SEL_I_I_MSK 0xffffff8f
+#define PAD67_SEL_I_SFT 4
+#define PAD67_SEL_I_HI 6
+#define PAD67_SEL_I_SZ 3
+#define PAD67_OD_MSK 0x00000100
+#define PAD67_OD_I_MSK 0xfffffeff
+#define PAD67_OD_SFT 8
+#define PAD67_OD_HI 8
+#define PAD67_OD_SZ 1
+#define PAD67_SEL_O_MSK 0x00003000
+#define PAD67_SEL_O_I_MSK 0xffffcfff
+#define PAD67_SEL_O_SFT 12
+#define PAD67_SEL_O_HI 13
+#define PAD67_SEL_O_SZ 2
+#define GPIO_TEST_8_QN_ID_MSK 0x10000000
+#define GPIO_TEST_8_QN_ID_I_MSK 0xefffffff
+#define GPIO_TEST_8_QN_ID_SFT 28
+#define GPIO_TEST_8_QN_ID_HI 28
+#define GPIO_TEST_8_QN_ID_SZ 1
+#define PAD69_OE_MSK 0x00000001
+#define PAD69_OE_I_MSK 0xfffffffe
+#define PAD69_OE_SFT 0
+#define PAD69_OE_HI 0
+#define PAD69_OE_SZ 1
+#define PAD69_PE_MSK 0x00000002
+#define PAD69_PE_I_MSK 0xfffffffd
+#define PAD69_PE_SFT 1
+#define PAD69_PE_HI 1
+#define PAD69_PE_SZ 1
+#define PAD69_DS_MSK 0x00000004
+#define PAD69_DS_I_MSK 0xfffffffb
+#define PAD69_DS_SFT 2
+#define PAD69_DS_HI 2
+#define PAD69_DS_SZ 1
+#define PAD69_IE_MSK 0x00000008
+#define PAD69_IE_I_MSK 0xfffffff7
+#define PAD69_IE_SFT 3
+#define PAD69_IE_HI 3
+#define PAD69_IE_SZ 1
+#define PAD69_SEL_I_MSK 0x00000030
+#define PAD69_SEL_I_I_MSK 0xffffffcf
+#define PAD69_SEL_I_SFT 4
+#define PAD69_SEL_I_HI 5
+#define PAD69_SEL_I_SZ 2
+#define PAD69_OD_MSK 0x00000100
+#define PAD69_OD_I_MSK 0xfffffeff
+#define PAD69_OD_SFT 8
+#define PAD69_OD_HI 8
+#define PAD69_OD_SZ 1
+#define PAD69_SEL_O_MSK 0x00001000
+#define PAD69_SEL_O_I_MSK 0xffffefff
+#define PAD69_SEL_O_SFT 12
+#define PAD69_SEL_O_HI 12
+#define PAD69_SEL_O_SZ 1
+#define STRAP2_MSK 0x08000000
+#define STRAP2_I_MSK 0xf7ffffff
+#define STRAP2_SFT 27
+#define STRAP2_HI 27
+#define STRAP2_SZ 1
+#define GPIO_20_ID_MSK 0x10000000
+#define GPIO_20_ID_I_MSK 0xefffffff
+#define GPIO_20_ID_SFT 28
+#define GPIO_20_ID_HI 28
+#define GPIO_20_ID_SZ 1
+#define PAD70_OE_MSK 0x00000001
+#define PAD70_OE_I_MSK 0xfffffffe
+#define PAD70_OE_SFT 0
+#define PAD70_OE_HI 0
+#define PAD70_OE_SZ 1
+#define PAD70_PE_MSK 0x00000002
+#define PAD70_PE_I_MSK 0xfffffffd
+#define PAD70_PE_SFT 1
+#define PAD70_PE_HI 1
+#define PAD70_PE_SZ 1
+#define PAD70_DS_MSK 0x00000004
+#define PAD70_DS_I_MSK 0xfffffffb
+#define PAD70_DS_SFT 2
+#define PAD70_DS_HI 2
+#define PAD70_DS_SZ 1
+#define PAD70_IE_MSK 0x00000008
+#define PAD70_IE_I_MSK 0xfffffff7
+#define PAD70_IE_SFT 3
+#define PAD70_IE_HI 3
+#define PAD70_IE_SZ 1
+#define PAD70_SEL_I_MSK 0x00000030
+#define PAD70_SEL_I_I_MSK 0xffffffcf
+#define PAD70_SEL_I_SFT 4
+#define PAD70_SEL_I_HI 5
+#define PAD70_SEL_I_SZ 2
+#define PAD70_OD_MSK 0x00000100
+#define PAD70_OD_I_MSK 0xfffffeff
+#define PAD70_OD_SFT 8
+#define PAD70_OD_HI 8
+#define PAD70_OD_SZ 1
+#define PAD70_SEL_O_MSK 0x00007000
+#define PAD70_SEL_O_I_MSK 0xffff8fff
+#define PAD70_SEL_O_SFT 12
+#define PAD70_SEL_O_HI 14
+#define PAD70_SEL_O_SZ 3
+#define GPIO_21_ID_MSK 0x10000000
+#define GPIO_21_ID_I_MSK 0xefffffff
+#define GPIO_21_ID_SFT 28
+#define GPIO_21_ID_HI 28
+#define GPIO_21_ID_SZ 1
+#define PAD231_OE_MSK 0x00000001
+#define PAD231_OE_I_MSK 0xfffffffe
+#define PAD231_OE_SFT 0
+#define PAD231_OE_HI 0
+#define PAD231_OE_SZ 1
+#define PAD231_PE_MSK 0x00000002
+#define PAD231_PE_I_MSK 0xfffffffd
+#define PAD231_PE_SFT 1
+#define PAD231_PE_HI 1
+#define PAD231_PE_SZ 1
+#define PAD231_DS_MSK 0x00000004
+#define PAD231_DS_I_MSK 0xfffffffb
+#define PAD231_DS_SFT 2
+#define PAD231_DS_HI 2
+#define PAD231_DS_SZ 1
+#define PAD231_IE_MSK 0x00000008
+#define PAD231_IE_I_MSK 0xfffffff7
+#define PAD231_IE_SFT 3
+#define PAD231_IE_HI 3
+#define PAD231_IE_SZ 1
+#define PAD231_OD_MSK 0x00000100
+#define PAD231_OD_I_MSK 0xfffffeff
+#define PAD231_OD_SFT 8
+#define PAD231_OD_HI 8
+#define PAD231_OD_SZ 1
+#define PIN_40_OR_56_ID_MSK 0x10000000
+#define PIN_40_OR_56_ID_I_MSK 0xefffffff
+#define PIN_40_OR_56_ID_SFT 28
+#define PIN_40_OR_56_ID_HI 28
+#define PIN_40_OR_56_ID_SZ 1
+#define MP_PHY2RX_DATA__0_SEL_MSK 0x00000001
+#define MP_PHY2RX_DATA__0_SEL_I_MSK 0xfffffffe
+#define MP_PHY2RX_DATA__0_SEL_SFT 0
+#define MP_PHY2RX_DATA__0_SEL_HI 0
+#define MP_PHY2RX_DATA__0_SEL_SZ 1
+#define MP_PHY2RX_DATA__1_SEL_MSK 0x00000002
+#define MP_PHY2RX_DATA__1_SEL_I_MSK 0xfffffffd
+#define MP_PHY2RX_DATA__1_SEL_SFT 1
+#define MP_PHY2RX_DATA__1_SEL_HI 1
+#define MP_PHY2RX_DATA__1_SEL_SZ 1
+#define MP_TX_FF_RPTR__1_SEL_MSK 0x00000004
+#define MP_TX_FF_RPTR__1_SEL_I_MSK 0xfffffffb
+#define MP_TX_FF_RPTR__1_SEL_SFT 2
+#define MP_TX_FF_RPTR__1_SEL_HI 2
+#define MP_TX_FF_RPTR__1_SEL_SZ 1
+#define MP_RX_FF_WPTR__2_SEL_MSK 0x00000008
+#define MP_RX_FF_WPTR__2_SEL_I_MSK 0xfffffff7
+#define MP_RX_FF_WPTR__2_SEL_SFT 3
+#define MP_RX_FF_WPTR__2_SEL_HI 3
+#define MP_RX_FF_WPTR__2_SEL_SZ 1
+#define MP_RX_FF_WPTR__1_SEL_MSK 0x00000010
+#define MP_RX_FF_WPTR__1_SEL_I_MSK 0xffffffef
+#define MP_RX_FF_WPTR__1_SEL_SFT 4
+#define MP_RX_FF_WPTR__1_SEL_HI 4
+#define MP_RX_FF_WPTR__1_SEL_SZ 1
+#define MP_RX_FF_WPTR__0_SEL_MSK 0x00000020
+#define MP_RX_FF_WPTR__0_SEL_I_MSK 0xffffffdf
+#define MP_RX_FF_WPTR__0_SEL_SFT 5
+#define MP_RX_FF_WPTR__0_SEL_HI 5
+#define MP_RX_FF_WPTR__0_SEL_SZ 1
+#define MP_PHY2RX_DATA__2_SEL_MSK 0x00000040
+#define MP_PHY2RX_DATA__2_SEL_I_MSK 0xffffffbf
+#define MP_PHY2RX_DATA__2_SEL_SFT 6
+#define MP_PHY2RX_DATA__2_SEL_HI 6
+#define MP_PHY2RX_DATA__2_SEL_SZ 1
+#define MP_PHY2RX_DATA__4_SEL_MSK 0x00000080
+#define MP_PHY2RX_DATA__4_SEL_I_MSK 0xffffff7f
+#define MP_PHY2RX_DATA__4_SEL_SFT 7
+#define MP_PHY2RX_DATA__4_SEL_HI 7
+#define MP_PHY2RX_DATA__4_SEL_SZ 1
+#define I2CM_SDA_ID_SEL_MSK 0x00000300
+#define I2CM_SDA_ID_SEL_I_MSK 0xfffffcff
+#define I2CM_SDA_ID_SEL_SFT 8
+#define I2CM_SDA_ID_SEL_HI 9
+#define I2CM_SDA_ID_SEL_SZ 2
+#define CRYSTAL_OUT_REQ_SEL_MSK 0x00000400
+#define CRYSTAL_OUT_REQ_SEL_I_MSK 0xfffffbff
+#define CRYSTAL_OUT_REQ_SEL_SFT 10
+#define CRYSTAL_OUT_REQ_SEL_HI 10
+#define CRYSTAL_OUT_REQ_SEL_SZ 1
+#define MP_PHY2RX_DATA__5_SEL_MSK 0x00000800
+#define MP_PHY2RX_DATA__5_SEL_I_MSK 0xfffff7ff
+#define MP_PHY2RX_DATA__5_SEL_SFT 11
+#define MP_PHY2RX_DATA__5_SEL_HI 11
+#define MP_PHY2RX_DATA__5_SEL_SZ 1
+#define MP_PHY2RX_DATA__3_SEL_MSK 0x00001000
+#define MP_PHY2RX_DATA__3_SEL_I_MSK 0xffffefff
+#define MP_PHY2RX_DATA__3_SEL_SFT 12
+#define MP_PHY2RX_DATA__3_SEL_HI 12
+#define MP_PHY2RX_DATA__3_SEL_SZ 1
+#define UART_RXD_SEL_MSK 0x00006000
+#define UART_RXD_SEL_I_MSK 0xffff9fff
+#define UART_RXD_SEL_SFT 13
+#define UART_RXD_SEL_HI 14
+#define UART_RXD_SEL_SZ 2
+#define MP_PHY2RX_DATA__6_SEL_MSK 0x00008000
+#define MP_PHY2RX_DATA__6_SEL_I_MSK 0xffff7fff
+#define MP_PHY2RX_DATA__6_SEL_SFT 15
+#define MP_PHY2RX_DATA__6_SEL_HI 15
+#define MP_PHY2RX_DATA__6_SEL_SZ 1
+#define DAT_UART_NCTS_SEL_MSK 0x00010000
+#define DAT_UART_NCTS_SEL_I_MSK 0xfffeffff
+#define DAT_UART_NCTS_SEL_SFT 16
+#define DAT_UART_NCTS_SEL_HI 16
+#define DAT_UART_NCTS_SEL_SZ 1
+#define GPIO_LOG_STOP_SEL_MSK 0x000e0000
+#define GPIO_LOG_STOP_SEL_I_MSK 0xfff1ffff
+#define GPIO_LOG_STOP_SEL_SFT 17
+#define GPIO_LOG_STOP_SEL_HI 19
+#define GPIO_LOG_STOP_SEL_SZ 3
+#define MP_TX_FF_RPTR__0_SEL_MSK 0x00100000
+#define MP_TX_FF_RPTR__0_SEL_I_MSK 0xffefffff
+#define MP_TX_FF_RPTR__0_SEL_SFT 20
+#define MP_TX_FF_RPTR__0_SEL_HI 20
+#define MP_TX_FF_RPTR__0_SEL_SZ 1
+#define MP_PHY_RX_WRST_N_SEL_MSK 0x00200000
+#define MP_PHY_RX_WRST_N_SEL_I_MSK 0xffdfffff
+#define MP_PHY_RX_WRST_N_SEL_SFT 21
+#define MP_PHY_RX_WRST_N_SEL_HI 21
+#define MP_PHY_RX_WRST_N_SEL_SZ 1
+#define EXT_32K_SEL_MSK 0x00c00000
+#define EXT_32K_SEL_I_MSK 0xff3fffff
+#define EXT_32K_SEL_SFT 22
+#define EXT_32K_SEL_HI 23
+#define EXT_32K_SEL_SZ 2
+#define MP_PHY2RX_DATA__7_SEL_MSK 0x01000000
+#define MP_PHY2RX_DATA__7_SEL_I_MSK 0xfeffffff
+#define MP_PHY2RX_DATA__7_SEL_SFT 24
+#define MP_PHY2RX_DATA__7_SEL_HI 24
+#define MP_PHY2RX_DATA__7_SEL_SZ 1
+#define MP_TX_FF_RPTR__2_SEL_MSK 0x02000000
+#define MP_TX_FF_RPTR__2_SEL_I_MSK 0xfdffffff
+#define MP_TX_FF_RPTR__2_SEL_SFT 25
+#define MP_TX_FF_RPTR__2_SEL_HI 25
+#define MP_TX_FF_RPTR__2_SEL_SZ 1
+#define PMUINT_WAKE_SEL_MSK 0x1c000000
+#define PMUINT_WAKE_SEL_I_MSK 0xe3ffffff
+#define PMUINT_WAKE_SEL_SFT 26
+#define PMUINT_WAKE_SEL_HI 28
+#define PMUINT_WAKE_SEL_SZ 3
+#define I2CM_SCL_ID_SEL_MSK 0x20000000
+#define I2CM_SCL_ID_SEL_I_MSK 0xdfffffff
+#define I2CM_SCL_ID_SEL_SFT 29
+#define I2CM_SCL_ID_SEL_HI 29
+#define I2CM_SCL_ID_SEL_SZ 1
+#define MP_MRX_RX_EN_SEL_MSK 0x40000000
+#define MP_MRX_RX_EN_SEL_I_MSK 0xbfffffff
+#define MP_MRX_RX_EN_SEL_SFT 30
+#define MP_MRX_RX_EN_SEL_HI 30
+#define MP_MRX_RX_EN_SEL_SZ 1
+#define DAT_UART_RXD_SEL_0_MSK 0x80000000
+#define DAT_UART_RXD_SEL_0_I_MSK 0x7fffffff
+#define DAT_UART_RXD_SEL_0_SFT 31
+#define DAT_UART_RXD_SEL_0_HI 31
+#define DAT_UART_RXD_SEL_0_SZ 1
+#define DAT_UART_RXD_SEL_1_MSK 0x00000001
+#define DAT_UART_RXD_SEL_1_I_MSK 0xfffffffe
+#define DAT_UART_RXD_SEL_1_SFT 0
+#define DAT_UART_RXD_SEL_1_HI 0
+#define DAT_UART_RXD_SEL_1_SZ 1
+#define SPI_DI_SEL_MSK 0x00000002
+#define SPI_DI_SEL_I_MSK 0xfffffffd
+#define SPI_DI_SEL_SFT 1
+#define SPI_DI_SEL_HI 1
+#define SPI_DI_SEL_SZ 1
+#define IO_PORT_REG_MSK 0x0001ffff
+#define IO_PORT_REG_I_MSK 0xfffe0000
+#define IO_PORT_REG_SFT 0
+#define IO_PORT_REG_HI 16
+#define IO_PORT_REG_SZ 17
+#define MASK_RX_INT_MSK 0x00000001
+#define MASK_RX_INT_I_MSK 0xfffffffe
+#define MASK_RX_INT_SFT 0
+#define MASK_RX_INT_HI 0
+#define MASK_RX_INT_SZ 1
+#define MASK_TX_INT_MSK 0x00000002
+#define MASK_TX_INT_I_MSK 0xfffffffd
+#define MASK_TX_INT_SFT 1
+#define MASK_TX_INT_HI 1
+#define MASK_TX_INT_SZ 1
+#define MASK_SOC_SYSTEM_INT_MSK 0x00000004
+#define MASK_SOC_SYSTEM_INT_I_MSK 0xfffffffb
+#define MASK_SOC_SYSTEM_INT_SFT 2
+#define MASK_SOC_SYSTEM_INT_HI 2
+#define MASK_SOC_SYSTEM_INT_SZ 1
+#define EDCA0_LOW_THR_INT_MASK_MSK 0x00000008
+#define EDCA0_LOW_THR_INT_MASK_I_MSK 0xfffffff7
+#define EDCA0_LOW_THR_INT_MASK_SFT 3
+#define EDCA0_LOW_THR_INT_MASK_HI 3
+#define EDCA0_LOW_THR_INT_MASK_SZ 1
+#define EDCA1_LOW_THR_INT_MASK_MSK 0x00000010
+#define EDCA1_LOW_THR_INT_MASK_I_MSK 0xffffffef
+#define EDCA1_LOW_THR_INT_MASK_SFT 4
+#define EDCA1_LOW_THR_INT_MASK_HI 4
+#define EDCA1_LOW_THR_INT_MASK_SZ 1
+#define EDCA2_LOW_THR_INT_MASK_MSK 0x00000020
+#define EDCA2_LOW_THR_INT_MASK_I_MSK 0xffffffdf
+#define EDCA2_LOW_THR_INT_MASK_SFT 5
+#define EDCA2_LOW_THR_INT_MASK_HI 5
+#define EDCA2_LOW_THR_INT_MASK_SZ 1
+#define EDCA3_LOW_THR_INT_MASK_MSK 0x00000040
+#define EDCA3_LOW_THR_INT_MASK_I_MSK 0xffffffbf
+#define EDCA3_LOW_THR_INT_MASK_SFT 6
+#define EDCA3_LOW_THR_INT_MASK_HI 6
+#define EDCA3_LOW_THR_INT_MASK_SZ 1
+#define TX_LIMIT_INT_MASK_MSK 0x00000080
+#define TX_LIMIT_INT_MASK_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_MASK_SFT 7
+#define TX_LIMIT_INT_MASK_HI 7
+#define TX_LIMIT_INT_MASK_SZ 1
+#define RX_INT_MSK 0x00000001
+#define RX_INT_I_MSK 0xfffffffe
+#define RX_INT_SFT 0
+#define RX_INT_HI 0
+#define RX_INT_SZ 1
+#define TX_COMPLETE_INT_MSK 0x00000002
+#define TX_COMPLETE_INT_I_MSK 0xfffffffd
+#define TX_COMPLETE_INT_SFT 1
+#define TX_COMPLETE_INT_HI 1
+#define TX_COMPLETE_INT_SZ 1
+#define SOC_SYSTEM_INT_STATUS_MSK 0x00000004
+#define SOC_SYSTEM_INT_STATUS_I_MSK 0xfffffffb
+#define SOC_SYSTEM_INT_STATUS_SFT 2
+#define SOC_SYSTEM_INT_STATUS_HI 2
+#define SOC_SYSTEM_INT_STATUS_SZ 1
+#define EDCA0_LOW_THR_INT_STS_MSK 0x00000008
+#define EDCA0_LOW_THR_INT_STS_I_MSK 0xfffffff7
+#define EDCA0_LOW_THR_INT_STS_SFT 3
+#define EDCA0_LOW_THR_INT_STS_HI 3
+#define EDCA0_LOW_THR_INT_STS_SZ 1
+#define EDCA1_LOW_THR_INT_STS_MSK 0x00000010
+#define EDCA1_LOW_THR_INT_STS_I_MSK 0xffffffef
+#define EDCA1_LOW_THR_INT_STS_SFT 4
+#define EDCA1_LOW_THR_INT_STS_HI 4
+#define EDCA1_LOW_THR_INT_STS_SZ 1
+#define EDCA2_LOW_THR_INT_STS_MSK 0x00000020
+#define EDCA2_LOW_THR_INT_STS_I_MSK 0xffffffdf
+#define EDCA2_LOW_THR_INT_STS_SFT 5
+#define EDCA2_LOW_THR_INT_STS_HI 5
+#define EDCA2_LOW_THR_INT_STS_SZ 1
+#define EDCA3_LOW_THR_INT_STS_MSK 0x00000040
+#define EDCA3_LOW_THR_INT_STS_I_MSK 0xffffffbf
+#define EDCA3_LOW_THR_INT_STS_SFT 6
+#define EDCA3_LOW_THR_INT_STS_HI 6
+#define EDCA3_LOW_THR_INT_STS_SZ 1
+#define TX_LIMIT_INT_STS_MSK 0x00000080
+#define TX_LIMIT_INT_STS_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_STS_SFT 7
+#define TX_LIMIT_INT_STS_HI 7
+#define TX_LIMIT_INT_STS_SZ 1
+#define HOST_TRIGGERED_RX_INT_MSK 0x00000100
+#define HOST_TRIGGERED_RX_INT_I_MSK 0xfffffeff
+#define HOST_TRIGGERED_RX_INT_SFT 8
+#define HOST_TRIGGERED_RX_INT_HI 8
+#define HOST_TRIGGERED_RX_INT_SZ 1
+#define HOST_TRIGGERED_TX_INT_MSK 0x00000200
+#define HOST_TRIGGERED_TX_INT_I_MSK 0xfffffdff
+#define HOST_TRIGGERED_TX_INT_SFT 9
+#define HOST_TRIGGERED_TX_INT_HI 9
+#define HOST_TRIGGERED_TX_INT_SZ 1
+#define SOC_TRIGGER_RX_INT_MSK 0x00000400
+#define SOC_TRIGGER_RX_INT_I_MSK 0xfffffbff
+#define SOC_TRIGGER_RX_INT_SFT 10
+#define SOC_TRIGGER_RX_INT_HI 10
+#define SOC_TRIGGER_RX_INT_SZ 1
+#define SOC_TRIGGER_TX_INT_MSK 0x00000800
+#define SOC_TRIGGER_TX_INT_I_MSK 0xfffff7ff
+#define SOC_TRIGGER_TX_INT_SFT 11
+#define SOC_TRIGGER_TX_INT_HI 11
+#define SOC_TRIGGER_TX_INT_SZ 1
+#define RDY_FOR_TX_RX_MSK 0x00000001
+#define RDY_FOR_TX_RX_I_MSK 0xfffffffe
+#define RDY_FOR_TX_RX_SFT 0
+#define RDY_FOR_TX_RX_HI 0
+#define RDY_FOR_TX_RX_SZ 1
+#define RDY_FOR_FW_DOWNLOAD_MSK 0x00000002
+#define RDY_FOR_FW_DOWNLOAD_I_MSK 0xfffffffd
+#define RDY_FOR_FW_DOWNLOAD_SFT 1
+#define RDY_FOR_FW_DOWNLOAD_HI 1
+#define RDY_FOR_FW_DOWNLOAD_SZ 1
+#define ILLEGAL_CMD_RESP_OPTION_MSK 0x00000004
+#define ILLEGAL_CMD_RESP_OPTION_I_MSK 0xfffffffb
+#define ILLEGAL_CMD_RESP_OPTION_SFT 2
+#define ILLEGAL_CMD_RESP_OPTION_HI 2
+#define ILLEGAL_CMD_RESP_OPTION_SZ 1
+#define SDIO_TRX_DATA_SEQUENCE_MSK 0x00000008
+#define SDIO_TRX_DATA_SEQUENCE_I_MSK 0xfffffff7
+#define SDIO_TRX_DATA_SEQUENCE_SFT 3
+#define SDIO_TRX_DATA_SEQUENCE_HI 3
+#define SDIO_TRX_DATA_SEQUENCE_SZ 1
+#define GPIO_INT_TRIGGER_OPTION_MSK 0x00000010
+#define GPIO_INT_TRIGGER_OPTION_I_MSK 0xffffffef
+#define GPIO_INT_TRIGGER_OPTION_SFT 4
+#define GPIO_INT_TRIGGER_OPTION_HI 4
+#define GPIO_INT_TRIGGER_OPTION_SZ 1
+#define TRIGGER_FUNCTION_SETTING_MSK 0x00000060
+#define TRIGGER_FUNCTION_SETTING_I_MSK 0xffffff9f
+#define TRIGGER_FUNCTION_SETTING_SFT 5
+#define TRIGGER_FUNCTION_SETTING_HI 6
+#define TRIGGER_FUNCTION_SETTING_SZ 2
+#define CMD52_ABORT_RESPONSE_MSK 0x00000080
+#define CMD52_ABORT_RESPONSE_I_MSK 0xffffff7f
+#define CMD52_ABORT_RESPONSE_SFT 7
+#define CMD52_ABORT_RESPONSE_HI 7
+#define CMD52_ABORT_RESPONSE_SZ 1
+#define RX_PACKET_LENGTH_MSK 0x0000ffff
+#define RX_PACKET_LENGTH_I_MSK 0xffff0000
+#define RX_PACKET_LENGTH_SFT 0
+#define RX_PACKET_LENGTH_HI 15
+#define RX_PACKET_LENGTH_SZ 16
+#define CARD_FW_DL_STATUS_MSK 0x00ff0000
+#define CARD_FW_DL_STATUS_I_MSK 0xff00ffff
+#define CARD_FW_DL_STATUS_SFT 16
+#define CARD_FW_DL_STATUS_HI 23
+#define CARD_FW_DL_STATUS_SZ 8
+#define TX_RX_LOOP_BACK_TEST_MSK 0x01000000
+#define TX_RX_LOOP_BACK_TEST_I_MSK 0xfeffffff
+#define TX_RX_LOOP_BACK_TEST_SFT 24
+#define TX_RX_LOOP_BACK_TEST_HI 24
+#define TX_RX_LOOP_BACK_TEST_SZ 1
+#define SDIO_LOOP_BACK_TEST_MSK 0x02000000
+#define SDIO_LOOP_BACK_TEST_I_MSK 0xfdffffff
+#define SDIO_LOOP_BACK_TEST_SFT 25
+#define SDIO_LOOP_BACK_TEST_HI 25
+#define SDIO_LOOP_BACK_TEST_SZ 1
+#define CMD52_ABORT_ACTIVE_MSK 0x10000000
+#define CMD52_ABORT_ACTIVE_I_MSK 0xefffffff
+#define CMD52_ABORT_ACTIVE_SFT 28
+#define CMD52_ABORT_ACTIVE_HI 28
+#define CMD52_ABORT_ACTIVE_SZ 1
+#define CMD52_RESET_ACTIVE_MSK 0x20000000
+#define CMD52_RESET_ACTIVE_I_MSK 0xdfffffff
+#define CMD52_RESET_ACTIVE_SFT 29
+#define CMD52_RESET_ACTIVE_HI 29
+#define CMD52_RESET_ACTIVE_SZ 1
+#define SDIO_PARTIAL_RESET_ACTIVE_MSK 0x40000000
+#define SDIO_PARTIAL_RESET_ACTIVE_I_MSK 0xbfffffff
+#define SDIO_PARTIAL_RESET_ACTIVE_SFT 30
+#define SDIO_PARTIAL_RESET_ACTIVE_HI 30
+#define SDIO_PARTIAL_RESET_ACTIVE_SZ 1
+#define SDIO_ALL_RESE_ACTIVE_MSK 0x80000000
+#define SDIO_ALL_RESE_ACTIVE_I_MSK 0x7fffffff
+#define SDIO_ALL_RESE_ACTIVE_SFT 31
+#define SDIO_ALL_RESE_ACTIVE_HI 31
+#define SDIO_ALL_RESE_ACTIVE_SZ 1
+#define RX_PACKET_LENGTH2_MSK 0x0000ffff
+#define RX_PACKET_LENGTH2_I_MSK 0xffff0000
+#define RX_PACKET_LENGTH2_SFT 0
+#define RX_PACKET_LENGTH2_HI 15
+#define RX_PACKET_LENGTH2_SZ 16
+#define RX_INT1_MSK 0x00010000
+#define RX_INT1_I_MSK 0xfffeffff
+#define RX_INT1_SFT 16
+#define RX_INT1_HI 16
+#define RX_INT1_SZ 1
+#define TX_DONE_MSK 0x00020000
+#define TX_DONE_I_MSK 0xfffdffff
+#define TX_DONE_SFT 17
+#define TX_DONE_HI 17
+#define TX_DONE_SZ 1
+#define HCI_TRX_FINISH_MSK 0x00040000
+#define HCI_TRX_FINISH_I_MSK 0xfffbffff
+#define HCI_TRX_FINISH_SFT 18
+#define HCI_TRX_FINISH_HI 18
+#define HCI_TRX_FINISH_SZ 1
+#define ALLOCATE_STATUS_MSK 0x00080000
+#define ALLOCATE_STATUS_I_MSK 0xfff7ffff
+#define ALLOCATE_STATUS_SFT 19
+#define ALLOCATE_STATUS_HI 19
+#define ALLOCATE_STATUS_SZ 1
+#define HCI_INPUT_FF_CNT_MSK 0x00f00000
+#define HCI_INPUT_FF_CNT_I_MSK 0xff0fffff
+#define HCI_INPUT_FF_CNT_SFT 20
+#define HCI_INPUT_FF_CNT_HI 23
+#define HCI_INPUT_FF_CNT_SZ 4
+#define HCI_OUTPUT_FF_CNT_MSK 0x1f000000
+#define HCI_OUTPUT_FF_CNT_I_MSK 0xe0ffffff
+#define HCI_OUTPUT_FF_CNT_SFT 24
+#define HCI_OUTPUT_FF_CNT_HI 28
+#define HCI_OUTPUT_FF_CNT_SZ 5
+#define AHB_HANG4_MSK 0x20000000
+#define AHB_HANG4_I_MSK 0xdfffffff
+#define AHB_HANG4_SFT 29
+#define AHB_HANG4_HI 29
+#define AHB_HANG4_SZ 1
+#define HCI_IN_QUE_EMPTY_MSK 0x40000000
+#define HCI_IN_QUE_EMPTY_I_MSK 0xbfffffff
+#define HCI_IN_QUE_EMPTY_SFT 30
+#define HCI_IN_QUE_EMPTY_HI 30
+#define HCI_IN_QUE_EMPTY_SZ 1
+#define SYSTEM_INT_MSK 0x80000000
+#define SYSTEM_INT_I_MSK 0x7fffffff
+#define SYSTEM_INT_SFT 31
+#define SYSTEM_INT_HI 31
+#define SYSTEM_INT_SZ 1
+#define CARD_RCA_REG_MSK 0x0000ffff
+#define CARD_RCA_REG_I_MSK 0xffff0000
+#define CARD_RCA_REG_SFT 0
+#define CARD_RCA_REG_HI 15
+#define CARD_RCA_REG_SZ 16
+#define SDIO_FIFO_WR_THLD_REG_MSK 0x000001ff
+#define SDIO_FIFO_WR_THLD_REG_I_MSK 0xfffffe00
+#define SDIO_FIFO_WR_THLD_REG_SFT 0
+#define SDIO_FIFO_WR_THLD_REG_HI 8
+#define SDIO_FIFO_WR_THLD_REG_SZ 9
+#define SDIO_FIFO_WR_LIMIT_REG_MSK 0x000001ff
+#define SDIO_FIFO_WR_LIMIT_REG_I_MSK 0xfffffe00
+#define SDIO_FIFO_WR_LIMIT_REG_SFT 0
+#define SDIO_FIFO_WR_LIMIT_REG_HI 8
+#define SDIO_FIFO_WR_LIMIT_REG_SZ 9
+#define SDIO_TX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
+#define SDIO_TX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
+#define SDIO_TX_DATA_BATCH_SIZE_REG_SFT 0
+#define SDIO_TX_DATA_BATCH_SIZE_REG_HI 8
+#define SDIO_TX_DATA_BATCH_SIZE_REG_SZ 9
+#define SDIO_THLD_FOR_CMD53RD_REG_MSK 0x000001ff
+#define SDIO_THLD_FOR_CMD53RD_REG_I_MSK 0xfffffe00
+#define SDIO_THLD_FOR_CMD53RD_REG_SFT 0
+#define SDIO_THLD_FOR_CMD53RD_REG_HI 8
+#define SDIO_THLD_FOR_CMD53RD_REG_SZ 9
+#define SDIO_RX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
+#define SDIO_RX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
+#define SDIO_RX_DATA_BATCH_SIZE_REG_SFT 0
+#define SDIO_RX_DATA_BATCH_SIZE_REG_HI 8
+#define SDIO_RX_DATA_BATCH_SIZE_REG_SZ 9
+#define START_BYTE_VALUE_MSK 0x000000ff
+#define START_BYTE_VALUE_I_MSK 0xffffff00
+#define START_BYTE_VALUE_SFT 0
+#define START_BYTE_VALUE_HI 7
+#define START_BYTE_VALUE_SZ 8
+#define END_BYTE_VALUE_MSK 0x0000ff00
+#define END_BYTE_VALUE_I_MSK 0xffff00ff
+#define END_BYTE_VALUE_SFT 8
+#define END_BYTE_VALUE_HI 15
+#define END_BYTE_VALUE_SZ 8
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_MSK 0x000000ff
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_I_MSK 0xffffff00
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SFT 0
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_HI 7
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SZ 8
+#define SDIO_LAST_CMD_INDEX_REG_MSK 0x0000003f
+#define SDIO_LAST_CMD_INDEX_REG_I_MSK 0xffffffc0
+#define SDIO_LAST_CMD_INDEX_REG_SFT 0
+#define SDIO_LAST_CMD_INDEX_REG_HI 5
+#define SDIO_LAST_CMD_INDEX_REG_SZ 6
+#define SDIO_LAST_CMD_CRC_REG_MSK 0x00007f00
+#define SDIO_LAST_CMD_CRC_REG_I_MSK 0xffff80ff
+#define SDIO_LAST_CMD_CRC_REG_SFT 8
+#define SDIO_LAST_CMD_CRC_REG_HI 14
+#define SDIO_LAST_CMD_CRC_REG_SZ 7
+#define SDIO_LAST_CMD_ARG_REG_MSK 0xffffffff
+#define SDIO_LAST_CMD_ARG_REG_I_MSK 0x00000000
+#define SDIO_LAST_CMD_ARG_REG_SFT 0
+#define SDIO_LAST_CMD_ARG_REG_HI 31
+#define SDIO_LAST_CMD_ARG_REG_SZ 32
+#define SDIO_BUS_STATE_REG_MSK 0x0000001f
+#define SDIO_BUS_STATE_REG_I_MSK 0xffffffe0
+#define SDIO_BUS_STATE_REG_SFT 0
+#define SDIO_BUS_STATE_REG_HI 4
+#define SDIO_BUS_STATE_REG_SZ 5
+#define SDIO_BUSY_LONG_CNT_MSK 0xffff0000
+#define SDIO_BUSY_LONG_CNT_I_MSK 0x0000ffff
+#define SDIO_BUSY_LONG_CNT_SFT 16
+#define SDIO_BUSY_LONG_CNT_HI 31
+#define SDIO_BUSY_LONG_CNT_SZ 16
+#define SDIO_CARD_STATUS_REG_MSK 0xffffffff
+#define SDIO_CARD_STATUS_REG_I_MSK 0x00000000
+#define SDIO_CARD_STATUS_REG_SFT 0
+#define SDIO_CARD_STATUS_REG_HI 31
+#define SDIO_CARD_STATUS_REG_SZ 32
+#define R5_RESPONSE_FLAG_MSK 0x000000ff
+#define R5_RESPONSE_FLAG_I_MSK 0xffffff00
+#define R5_RESPONSE_FLAG_SFT 0
+#define R5_RESPONSE_FLAG_HI 7
+#define R5_RESPONSE_FLAG_SZ 8
+#define RESP_OUT_EDGE_MSK 0x00000100
+#define RESP_OUT_EDGE_I_MSK 0xfffffeff
+#define RESP_OUT_EDGE_SFT 8
+#define RESP_OUT_EDGE_HI 8
+#define RESP_OUT_EDGE_SZ 1
+#define DAT_OUT_EDGE_MSK 0x00000200
+#define DAT_OUT_EDGE_I_MSK 0xfffffdff
+#define DAT_OUT_EDGE_SFT 9
+#define DAT_OUT_EDGE_HI 9
+#define DAT_OUT_EDGE_SZ 1
+#define MCU_TO_SDIO_INFO_MASK_MSK 0x00010000
+#define MCU_TO_SDIO_INFO_MASK_I_MSK 0xfffeffff
+#define MCU_TO_SDIO_INFO_MASK_SFT 16
+#define MCU_TO_SDIO_INFO_MASK_HI 16
+#define MCU_TO_SDIO_INFO_MASK_SZ 1
+#define INT_THROUGH_PIN_MSK 0x00020000
+#define INT_THROUGH_PIN_I_MSK 0xfffdffff
+#define INT_THROUGH_PIN_SFT 17
+#define INT_THROUGH_PIN_HI 17
+#define INT_THROUGH_PIN_SZ 1
+#define WRITE_DATA_MSK 0x000000ff
+#define WRITE_DATA_I_MSK 0xffffff00
+#define WRITE_DATA_SFT 0
+#define WRITE_DATA_HI 7
+#define WRITE_DATA_SZ 8
+#define WRITE_ADDRESS_MSK 0x0000ff00
+#define WRITE_ADDRESS_I_MSK 0xffff00ff
+#define WRITE_ADDRESS_SFT 8
+#define WRITE_ADDRESS_HI 15
+#define WRITE_ADDRESS_SZ 8
+#define READ_DATA_MSK 0x00ff0000
+#define READ_DATA_I_MSK 0xff00ffff
+#define READ_DATA_SFT 16
+#define READ_DATA_HI 23
+#define READ_DATA_SZ 8
+#define READ_ADDRESS_MSK 0xff000000
+#define READ_ADDRESS_I_MSK 0x00ffffff
+#define READ_ADDRESS_SFT 24
+#define READ_ADDRESS_HI 31
+#define READ_ADDRESS_SZ 8
+#define FN1_DMA_START_ADDR_REG_MSK 0xffffffff
+#define FN1_DMA_START_ADDR_REG_I_MSK 0x00000000
+#define FN1_DMA_START_ADDR_REG_SFT 0
+#define FN1_DMA_START_ADDR_REG_HI 31
+#define FN1_DMA_START_ADDR_REG_SZ 32
+#define SDIO_TO_MCU_INFO_MSK 0x000000ff
+#define SDIO_TO_MCU_INFO_I_MSK 0xffffff00
+#define SDIO_TO_MCU_INFO_SFT 0
+#define SDIO_TO_MCU_INFO_HI 7
+#define SDIO_TO_MCU_INFO_SZ 8
+#define SDIO_PARTIAL_RESET_MSK 0x00000100
+#define SDIO_PARTIAL_RESET_I_MSK 0xfffffeff
+#define SDIO_PARTIAL_RESET_SFT 8
+#define SDIO_PARTIAL_RESET_HI 8
+#define SDIO_PARTIAL_RESET_SZ 1
+#define SDIO_ALL_RESET_MSK 0x00000200
+#define SDIO_ALL_RESET_I_MSK 0xfffffdff
+#define SDIO_ALL_RESET_SFT 9
+#define SDIO_ALL_RESET_HI 9
+#define SDIO_ALL_RESET_SZ 1
+#define PERI_MAC_ALL_RESET_MSK 0x00000400
+#define PERI_MAC_ALL_RESET_I_MSK 0xfffffbff
+#define PERI_MAC_ALL_RESET_SFT 10
+#define PERI_MAC_ALL_RESET_HI 10
+#define PERI_MAC_ALL_RESET_SZ 1
+#define MAC_ALL_RESET_MSK 0x00000800
+#define MAC_ALL_RESET_I_MSK 0xfffff7ff
+#define MAC_ALL_RESET_SFT 11
+#define MAC_ALL_RESET_HI 11
+#define MAC_ALL_RESET_SZ 1
+#define AHB_BRIDGE_RESET_MSK 0x00001000
+#define AHB_BRIDGE_RESET_I_MSK 0xffffefff
+#define AHB_BRIDGE_RESET_SFT 12
+#define AHB_BRIDGE_RESET_HI 12
+#define AHB_BRIDGE_RESET_SZ 1
+#define IO_REG_PORT_REG_MSK 0x0001ffff
+#define IO_REG_PORT_REG_I_MSK 0xfffe0000
+#define IO_REG_PORT_REG_SFT 0
+#define IO_REG_PORT_REG_HI 16
+#define IO_REG_PORT_REG_SZ 17
+#define SDIO_FIFO_EMPTY_CNT_MSK 0x0000ffff
+#define SDIO_FIFO_EMPTY_CNT_I_MSK 0xffff0000
+#define SDIO_FIFO_EMPTY_CNT_SFT 0
+#define SDIO_FIFO_EMPTY_CNT_HI 15
+#define SDIO_FIFO_EMPTY_CNT_SZ 16
+#define SDIO_FIFO_FULL_CNT_MSK 0xffff0000
+#define SDIO_FIFO_FULL_CNT_I_MSK 0x0000ffff
+#define SDIO_FIFO_FULL_CNT_SFT 16
+#define SDIO_FIFO_FULL_CNT_HI 31
+#define SDIO_FIFO_FULL_CNT_SZ 16
+#define SDIO_CRC7_ERROR_CNT_MSK 0x0000ffff
+#define SDIO_CRC7_ERROR_CNT_I_MSK 0xffff0000
+#define SDIO_CRC7_ERROR_CNT_SFT 0
+#define SDIO_CRC7_ERROR_CNT_HI 15
+#define SDIO_CRC7_ERROR_CNT_SZ 16
+#define SDIO_CRC16_ERROR_CNT_MSK 0xffff0000
+#define SDIO_CRC16_ERROR_CNT_I_MSK 0x0000ffff
+#define SDIO_CRC16_ERROR_CNT_SFT 16
+#define SDIO_CRC16_ERROR_CNT_HI 31
+#define SDIO_CRC16_ERROR_CNT_SZ 16
+#define SDIO_RD_BLOCK_CNT_MSK 0x000001ff
+#define SDIO_RD_BLOCK_CNT_I_MSK 0xfffffe00
+#define SDIO_RD_BLOCK_CNT_SFT 0
+#define SDIO_RD_BLOCK_CNT_HI 8
+#define SDIO_RD_BLOCK_CNT_SZ 9
+#define SDIO_WR_BLOCK_CNT_MSK 0x01ff0000
+#define SDIO_WR_BLOCK_CNT_I_MSK 0xfe00ffff
+#define SDIO_WR_BLOCK_CNT_SFT 16
+#define SDIO_WR_BLOCK_CNT_HI 24
+#define SDIO_WR_BLOCK_CNT_SZ 9
+#define CMD52_RD_ABORT_CNT_MSK 0x000f0000
+#define CMD52_RD_ABORT_CNT_I_MSK 0xfff0ffff
+#define CMD52_RD_ABORT_CNT_SFT 16
+#define CMD52_RD_ABORT_CNT_HI 19
+#define CMD52_RD_ABORT_CNT_SZ 4
+#define CMD52_WR_ABORT_CNT_MSK 0x00f00000
+#define CMD52_WR_ABORT_CNT_I_MSK 0xff0fffff
+#define CMD52_WR_ABORT_CNT_SFT 20
+#define CMD52_WR_ABORT_CNT_HI 23
+#define CMD52_WR_ABORT_CNT_SZ 4
+#define SDIO_FIFO_WR_PTR_REG_MSK 0x000000ff
+#define SDIO_FIFO_WR_PTR_REG_I_MSK 0xffffff00
+#define SDIO_FIFO_WR_PTR_REG_SFT 0
+#define SDIO_FIFO_WR_PTR_REG_HI 7
+#define SDIO_FIFO_WR_PTR_REG_SZ 8
+#define SDIO_FIFO_RD_PTR_REG_MSK 0x0000ff00
+#define SDIO_FIFO_RD_PTR_REG_I_MSK 0xffff00ff
+#define SDIO_FIFO_RD_PTR_REG_SFT 8
+#define SDIO_FIFO_RD_PTR_REG_HI 15
+#define SDIO_FIFO_RD_PTR_REG_SZ 8
+#define SDIO_READ_DATA_CTRL_MSK 0x00010000
+#define SDIO_READ_DATA_CTRL_I_MSK 0xfffeffff
+#define SDIO_READ_DATA_CTRL_SFT 16
+#define SDIO_READ_DATA_CTRL_HI 16
+#define SDIO_READ_DATA_CTRL_SZ 1
+#define TX_SIZE_BEFORE_SHIFT_MSK 0x000000ff
+#define TX_SIZE_BEFORE_SHIFT_I_MSK 0xffffff00
+#define TX_SIZE_BEFORE_SHIFT_SFT 0
+#define TX_SIZE_BEFORE_SHIFT_HI 7
+#define TX_SIZE_BEFORE_SHIFT_SZ 8
+#define TX_SIZE_SHIFT_BITS_MSK 0x00000700
+#define TX_SIZE_SHIFT_BITS_I_MSK 0xfffff8ff
+#define TX_SIZE_SHIFT_BITS_SFT 8
+#define TX_SIZE_SHIFT_BITS_HI 10
+#define TX_SIZE_SHIFT_BITS_SZ 3
+#define SDIO_TX_ALLOC_STATE_MSK 0x00001000
+#define SDIO_TX_ALLOC_STATE_I_MSK 0xffffefff
+#define SDIO_TX_ALLOC_STATE_SFT 12
+#define SDIO_TX_ALLOC_STATE_HI 12
+#define SDIO_TX_ALLOC_STATE_SZ 1
+#define ALLOCATE_STATUS2_MSK 0x00010000
+#define ALLOCATE_STATUS2_I_MSK 0xfffeffff
+#define ALLOCATE_STATUS2_SFT 16
+#define ALLOCATE_STATUS2_HI 16
+#define ALLOCATE_STATUS2_SZ 1
+#define NO_ALLOCATE_SEND_ERROR_MSK 0x00020000
+#define NO_ALLOCATE_SEND_ERROR_I_MSK 0xfffdffff
+#define NO_ALLOCATE_SEND_ERROR_SFT 17
+#define NO_ALLOCATE_SEND_ERROR_HI 17
+#define NO_ALLOCATE_SEND_ERROR_SZ 1
+#define DOUBLE_ALLOCATE_ERROR_MSK 0x00040000
+#define DOUBLE_ALLOCATE_ERROR_I_MSK 0xfffbffff
+#define DOUBLE_ALLOCATE_ERROR_SFT 18
+#define DOUBLE_ALLOCATE_ERROR_HI 18
+#define DOUBLE_ALLOCATE_ERROR_SZ 1
+#define TX_DONE_STATUS_MSK 0x00080000
+#define TX_DONE_STATUS_I_MSK 0xfff7ffff
+#define TX_DONE_STATUS_SFT 19
+#define TX_DONE_STATUS_HI 19
+#define TX_DONE_STATUS_SZ 1
+#define AHB_HANG2_MSK 0x00100000
+#define AHB_HANG2_I_MSK 0xffefffff
+#define AHB_HANG2_SFT 20
+#define AHB_HANG2_HI 20
+#define AHB_HANG2_SZ 1
+#define HCI_TRX_FINISH2_MSK 0x00200000
+#define HCI_TRX_FINISH2_I_MSK 0xffdfffff
+#define HCI_TRX_FINISH2_SFT 21
+#define HCI_TRX_FINISH2_HI 21
+#define HCI_TRX_FINISH2_SZ 1
+#define INTR_RX_MSK 0x00400000
+#define INTR_RX_I_MSK 0xffbfffff
+#define INTR_RX_SFT 22
+#define INTR_RX_HI 22
+#define INTR_RX_SZ 1
+#define HCI_INPUT_QUEUE_FULL_MSK 0x00800000
+#define HCI_INPUT_QUEUE_FULL_I_MSK 0xff7fffff
+#define HCI_INPUT_QUEUE_FULL_SFT 23
+#define HCI_INPUT_QUEUE_FULL_HI 23
+#define HCI_INPUT_QUEUE_FULL_SZ 1
+#define ALLOCATESTATUS_MSK 0x00000001
+#define ALLOCATESTATUS_I_MSK 0xfffffffe
+#define ALLOCATESTATUS_SFT 0
+#define ALLOCATESTATUS_HI 0
+#define ALLOCATESTATUS_SZ 1
+#define HCI_TRX_FINISH3_MSK 0x00000002
+#define HCI_TRX_FINISH3_I_MSK 0xfffffffd
+#define HCI_TRX_FINISH3_SFT 1
+#define HCI_TRX_FINISH3_HI 1
+#define HCI_TRX_FINISH3_SZ 1
+#define HCI_IN_QUE_EMPTY2_MSK 0x00000004
+#define HCI_IN_QUE_EMPTY2_I_MSK 0xfffffffb
+#define HCI_IN_QUE_EMPTY2_SFT 2
+#define HCI_IN_QUE_EMPTY2_HI 2
+#define HCI_IN_QUE_EMPTY2_SZ 1
+#define MTX_MNG_UPTHOLD_INT_MSK 0x00000008
+#define MTX_MNG_UPTHOLD_INT_I_MSK 0xfffffff7
+#define MTX_MNG_UPTHOLD_INT_SFT 3
+#define MTX_MNG_UPTHOLD_INT_HI 3
+#define MTX_MNG_UPTHOLD_INT_SZ 1
+#define EDCA0_UPTHOLD_INT_MSK 0x00000010
+#define EDCA0_UPTHOLD_INT_I_MSK 0xffffffef
+#define EDCA0_UPTHOLD_INT_SFT 4
+#define EDCA0_UPTHOLD_INT_HI 4
+#define EDCA0_UPTHOLD_INT_SZ 1
+#define EDCA1_UPTHOLD_INT_MSK 0x00000020
+#define EDCA1_UPTHOLD_INT_I_MSK 0xffffffdf
+#define EDCA1_UPTHOLD_INT_SFT 5
+#define EDCA1_UPTHOLD_INT_HI 5
+#define EDCA1_UPTHOLD_INT_SZ 1
+#define EDCA2_UPTHOLD_INT_MSK 0x00000040
+#define EDCA2_UPTHOLD_INT_I_MSK 0xffffffbf
+#define EDCA2_UPTHOLD_INT_SFT 6
+#define EDCA2_UPTHOLD_INT_HI 6
+#define EDCA2_UPTHOLD_INT_SZ 1
+#define EDCA3_UPTHOLD_INT_MSK 0x00000080
+#define EDCA3_UPTHOLD_INT_I_MSK 0xffffff7f
+#define EDCA3_UPTHOLD_INT_SFT 7
+#define EDCA3_UPTHOLD_INT_HI 7
+#define EDCA3_UPTHOLD_INT_SZ 1
+#define TX_PAGE_REMAIN2_MSK 0x0000ff00
+#define TX_PAGE_REMAIN2_I_MSK 0xffff00ff
+#define TX_PAGE_REMAIN2_SFT 8
+#define TX_PAGE_REMAIN2_HI 15
+#define TX_PAGE_REMAIN2_SZ 8
+#define TX_ID_REMAIN3_MSK 0x007f0000
+#define TX_ID_REMAIN3_I_MSK 0xff80ffff
+#define TX_ID_REMAIN3_SFT 16
+#define TX_ID_REMAIN3_HI 22
+#define TX_ID_REMAIN3_SZ 7
+#define HCI_OUTPUT_FF_CNT_0_MSK 0x00800000
+#define HCI_OUTPUT_FF_CNT_0_I_MSK 0xff7fffff
+#define HCI_OUTPUT_FF_CNT_0_SFT 23
+#define HCI_OUTPUT_FF_CNT_0_HI 23
+#define HCI_OUTPUT_FF_CNT_0_SZ 1
+#define HCI_OUTPUT_FF_CNT2_MSK 0x0f000000
+#define HCI_OUTPUT_FF_CNT2_I_MSK 0xf0ffffff
+#define HCI_OUTPUT_FF_CNT2_SFT 24
+#define HCI_OUTPUT_FF_CNT2_HI 27
+#define HCI_OUTPUT_FF_CNT2_SZ 4
+#define HCI_INPUT_FF_CNT2_MSK 0xf0000000
+#define HCI_INPUT_FF_CNT2_I_MSK 0x0fffffff
+#define HCI_INPUT_FF_CNT2_SFT 28
+#define HCI_INPUT_FF_CNT2_HI 31
+#define HCI_INPUT_FF_CNT2_SZ 4
+#define F1_BLOCK_SIZE_0_REG_MSK 0x00000fff
+#define F1_BLOCK_SIZE_0_REG_I_MSK 0xfffff000
+#define F1_BLOCK_SIZE_0_REG_SFT 0
+#define F1_BLOCK_SIZE_0_REG_HI 11
+#define F1_BLOCK_SIZE_0_REG_SZ 12
+#define START_BYTE_VALUE2_MSK 0x000000ff
+#define START_BYTE_VALUE2_I_MSK 0xffffff00
+#define START_BYTE_VALUE2_SFT 0
+#define START_BYTE_VALUE2_HI 7
+#define START_BYTE_VALUE2_SZ 8
+#define COMMAND_COUNTER_MSK 0x0000ff00
+#define COMMAND_COUNTER_I_MSK 0xffff00ff
+#define COMMAND_COUNTER_SFT 8
+#define COMMAND_COUNTER_HI 15
+#define COMMAND_COUNTER_SZ 8
+#define CMD_LOG_PART1_MSK 0xffff0000
+#define CMD_LOG_PART1_I_MSK 0x0000ffff
+#define CMD_LOG_PART1_SFT 16
+#define CMD_LOG_PART1_HI 31
+#define CMD_LOG_PART1_SZ 16
+#define CMD_LOG_PART2_MSK 0x00ffffff
+#define CMD_LOG_PART2_I_MSK 0xff000000
+#define CMD_LOG_PART2_SFT 0
+#define CMD_LOG_PART2_HI 23
+#define CMD_LOG_PART2_SZ 24
+#define END_BYTE_VALUE2_MSK 0xff000000
+#define END_BYTE_VALUE2_I_MSK 0x00ffffff
+#define END_BYTE_VALUE2_SFT 24
+#define END_BYTE_VALUE2_HI 31
+#define END_BYTE_VALUE2_SZ 8
+#define RX_PACKET_LENGTH3_MSK 0x0000ffff
+#define RX_PACKET_LENGTH3_I_MSK 0xffff0000
+#define RX_PACKET_LENGTH3_SFT 0
+#define RX_PACKET_LENGTH3_HI 15
+#define RX_PACKET_LENGTH3_SZ 16
+#define RX_INT3_MSK 0x00010000
+#define RX_INT3_I_MSK 0xfffeffff
+#define RX_INT3_SFT 16
+#define RX_INT3_HI 16
+#define RX_INT3_SZ 1
+#define TX_ID_REMAIN2_MSK 0x00fe0000
+#define TX_ID_REMAIN2_I_MSK 0xff01ffff
+#define TX_ID_REMAIN2_SFT 17
+#define TX_ID_REMAIN2_HI 23
+#define TX_ID_REMAIN2_SZ 7
+#define TX_PAGE_REMAIN3_MSK 0xff000000
+#define TX_PAGE_REMAIN3_I_MSK 0x00ffffff
+#define TX_PAGE_REMAIN3_SFT 24
+#define TX_PAGE_REMAIN3_HI 31
+#define TX_PAGE_REMAIN3_SZ 8
+#define CCCR_00H_REG_MSK 0x000000ff
+#define CCCR_00H_REG_I_MSK 0xffffff00
+#define CCCR_00H_REG_SFT 0
+#define CCCR_00H_REG_HI 7
+#define CCCR_00H_REG_SZ 8
+#define CCCR_02H_REG_MSK 0x00ff0000
+#define CCCR_02H_REG_I_MSK 0xff00ffff
+#define CCCR_02H_REG_SFT 16
+#define CCCR_02H_REG_HI 23
+#define CCCR_02H_REG_SZ 8
+#define CCCR_03H_REG_MSK 0xff000000
+#define CCCR_03H_REG_I_MSK 0x00ffffff
+#define CCCR_03H_REG_SFT 24
+#define CCCR_03H_REG_HI 31
+#define CCCR_03H_REG_SZ 8
+#define CCCR_04H_REG_MSK 0x000000ff
+#define CCCR_04H_REG_I_MSK 0xffffff00
+#define CCCR_04H_REG_SFT 0
+#define CCCR_04H_REG_HI 7
+#define CCCR_04H_REG_SZ 8
+#define CCCR_05H_REG_MSK 0x0000ff00
+#define CCCR_05H_REG_I_MSK 0xffff00ff
+#define CCCR_05H_REG_SFT 8
+#define CCCR_05H_REG_HI 15
+#define CCCR_05H_REG_SZ 8
+#define CCCR_06H_REG_MSK 0x000f0000
+#define CCCR_06H_REG_I_MSK 0xfff0ffff
+#define CCCR_06H_REG_SFT 16
+#define CCCR_06H_REG_HI 19
+#define CCCR_06H_REG_SZ 4
+#define CCCR_07H_REG_MSK 0xff000000
+#define CCCR_07H_REG_I_MSK 0x00ffffff
+#define CCCR_07H_REG_SFT 24
+#define CCCR_07H_REG_HI 31
+#define CCCR_07H_REG_SZ 8
+#define SUPPORT_DIRECT_COMMAND_SDIO_MSK 0x00000001
+#define SUPPORT_DIRECT_COMMAND_SDIO_I_MSK 0xfffffffe
+#define SUPPORT_DIRECT_COMMAND_SDIO_SFT 0
+#define SUPPORT_DIRECT_COMMAND_SDIO_HI 0
+#define SUPPORT_DIRECT_COMMAND_SDIO_SZ 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_MSK 0x00000002
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_I_MSK 0xfffffffd
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SFT 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_HI 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SZ 1
+#define SUPPORT_READ_WAIT_MSK 0x00000004
+#define SUPPORT_READ_WAIT_I_MSK 0xfffffffb
+#define SUPPORT_READ_WAIT_SFT 2
+#define SUPPORT_READ_WAIT_HI 2
+#define SUPPORT_READ_WAIT_SZ 1
+#define SUPPORT_BUS_CONTROL_MSK 0x00000008
+#define SUPPORT_BUS_CONTROL_I_MSK 0xfffffff7
+#define SUPPORT_BUS_CONTROL_SFT 3
+#define SUPPORT_BUS_CONTROL_HI 3
+#define SUPPORT_BUS_CONTROL_SZ 1
+#define SUPPORT_BLOCK_GAP_INTERRUPT_MSK 0x00000010
+#define SUPPORT_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffef
+#define SUPPORT_BLOCK_GAP_INTERRUPT_SFT 4
+#define SUPPORT_BLOCK_GAP_INTERRUPT_HI 4
+#define SUPPORT_BLOCK_GAP_INTERRUPT_SZ 1
+#define ENABLE_BLOCK_GAP_INTERRUPT_MSK 0x00000020
+#define ENABLE_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffdf
+#define ENABLE_BLOCK_GAP_INTERRUPT_SFT 5
+#define ENABLE_BLOCK_GAP_INTERRUPT_HI 5
+#define ENABLE_BLOCK_GAP_INTERRUPT_SZ 1
+#define LOW_SPEED_CARD_MSK 0x00000040
+#define LOW_SPEED_CARD_I_MSK 0xffffffbf
+#define LOW_SPEED_CARD_SFT 6
+#define LOW_SPEED_CARD_HI 6
+#define LOW_SPEED_CARD_SZ 1
+#define LOW_SPEED_CARD_4BIT_MSK 0x00000080
+#define LOW_SPEED_CARD_4BIT_I_MSK 0xffffff7f
+#define LOW_SPEED_CARD_4BIT_SFT 7
+#define LOW_SPEED_CARD_4BIT_HI 7
+#define LOW_SPEED_CARD_4BIT_SZ 1
+#define COMMON_CIS_PONTER_MSK 0x01ffff00
+#define COMMON_CIS_PONTER_I_MSK 0xfe0000ff
+#define COMMON_CIS_PONTER_SFT 8
+#define COMMON_CIS_PONTER_HI 24
+#define COMMON_CIS_PONTER_SZ 17
+#define SUPPORT_HIGH_SPEED_MSK 0x01000000
+#define SUPPORT_HIGH_SPEED_I_MSK 0xfeffffff
+#define SUPPORT_HIGH_SPEED_SFT 24
+#define SUPPORT_HIGH_SPEED_HI 24
+#define SUPPORT_HIGH_SPEED_SZ 1
+#define BSS_MSK 0x0e000000
+#define BSS_I_MSK 0xf1ffffff
+#define BSS_SFT 25
+#define BSS_HI 27
+#define BSS_SZ 3
+#define FBR_100H_REG_MSK 0x0000000f
+#define FBR_100H_REG_I_MSK 0xfffffff0
+#define FBR_100H_REG_SFT 0
+#define FBR_100H_REG_HI 3
+#define FBR_100H_REG_SZ 4
+#define CSASUPPORT_MSK 0x00000040
+#define CSASUPPORT_I_MSK 0xffffffbf
+#define CSASUPPORT_SFT 6
+#define CSASUPPORT_HI 6
+#define CSASUPPORT_SZ 1
+#define ENABLECSA_MSK 0x00000080
+#define ENABLECSA_I_MSK 0xffffff7f
+#define ENABLECSA_SFT 7
+#define ENABLECSA_HI 7
+#define ENABLECSA_SZ 1
+#define FBR_101H_REG_MSK 0x0000ff00
+#define FBR_101H_REG_I_MSK 0xffff00ff
+#define FBR_101H_REG_SFT 8
+#define FBR_101H_REG_HI 15
+#define FBR_101H_REG_SZ 8
+#define FBR_109H_REG_MSK 0x01ffff00
+#define FBR_109H_REG_I_MSK 0xfe0000ff
+#define FBR_109H_REG_SFT 8
+#define FBR_109H_REG_HI 24
+#define FBR_109H_REG_SZ 17
+#define F0_CIS_CONTENT_REG_31_0_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_31_0_SFT 0
+#define F0_CIS_CONTENT_REG_31_0_HI 31
+#define F0_CIS_CONTENT_REG_31_0_SZ 32
+#define F0_CIS_CONTENT_REG_63_32_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_63_32_SFT 0
+#define F0_CIS_CONTENT_REG_63_32_HI 31
+#define F0_CIS_CONTENT_REG_63_32_SZ 32
+#define F0_CIS_CONTENT_REG_95_64_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_95_64_SFT 0
+#define F0_CIS_CONTENT_REG_95_64_HI 31
+#define F0_CIS_CONTENT_REG_95_64_SZ 32
+#define F0_CIS_CONTENT_REG_127_96_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_127_96_SFT 0
+#define F0_CIS_CONTENT_REG_127_96_HI 31
+#define F0_CIS_CONTENT_REG_127_96_SZ 32
+#define F0_CIS_CONTENT_REG_159_128_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_159_128_SFT 0
+#define F0_CIS_CONTENT_REG_159_128_HI 31
+#define F0_CIS_CONTENT_REG_159_128_SZ 32
+#define F0_CIS_CONTENT_REG_191_160_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_191_160_SFT 0
+#define F0_CIS_CONTENT_REG_191_160_HI 31
+#define F0_CIS_CONTENT_REG_191_160_SZ 32
+#define F0_CIS_CONTENT_REG_223_192_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_223_192_SFT 0
+#define F0_CIS_CONTENT_REG_223_192_HI 31
+#define F0_CIS_CONTENT_REG_223_192_SZ 32
+#define F0_CIS_CONTENT_REG_255_224_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_255_224_SFT 0
+#define F0_CIS_CONTENT_REG_255_224_HI 31
+#define F0_CIS_CONTENT_REG_255_224_SZ 32
+#define F0_CIS_CONTENT_REG_287_256_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_287_256_SFT 0
+#define F0_CIS_CONTENT_REG_287_256_HI 31
+#define F0_CIS_CONTENT_REG_287_256_SZ 32
+#define F0_CIS_CONTENT_REG_319_288_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_319_288_SFT 0
+#define F0_CIS_CONTENT_REG_319_288_HI 31
+#define F0_CIS_CONTENT_REG_319_288_SZ 32
+#define F0_CIS_CONTENT_REG_351_320_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_351_320_SFT 0
+#define F0_CIS_CONTENT_REG_351_320_HI 31
+#define F0_CIS_CONTENT_REG_351_320_SZ 32
+#define F0_CIS_CONTENT_REG_383_352_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_383_352_SFT 0
+#define F0_CIS_CONTENT_REG_383_352_HI 31
+#define F0_CIS_CONTENT_REG_383_352_SZ 32
+#define F0_CIS_CONTENT_REG_415_384_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_415_384_SFT 0
+#define F0_CIS_CONTENT_REG_415_384_HI 31
+#define F0_CIS_CONTENT_REG_415_384_SZ 32
+#define F0_CIS_CONTENT_REG_447_416_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_447_416_SFT 0
+#define F0_CIS_CONTENT_REG_447_416_HI 31
+#define F0_CIS_CONTENT_REG_447_416_SZ 32
+#define F0_CIS_CONTENT_REG_479_448_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_479_448_SFT 0
+#define F0_CIS_CONTENT_REG_479_448_HI 31
+#define F0_CIS_CONTENT_REG_479_448_SZ 32
+#define F0_CIS_CONTENT_REG_511_480_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_511_480_SFT 0
+#define F0_CIS_CONTENT_REG_511_480_HI 31
+#define F0_CIS_CONTENT_REG_511_480_SZ 32
+#define F1_CIS_CONTENT_REG_31_0_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_31_0_SFT 0
+#define F1_CIS_CONTENT_REG_31_0_HI 31
+#define F1_CIS_CONTENT_REG_31_0_SZ 32
+#define F1_CIS_CONTENT_REG_63_32_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_63_32_SFT 0
+#define F1_CIS_CONTENT_REG_63_32_HI 31
+#define F1_CIS_CONTENT_REG_63_32_SZ 32
+#define F1_CIS_CONTENT_REG_95_64_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_95_64_SFT 0
+#define F1_CIS_CONTENT_REG_95_64_HI 31
+#define F1_CIS_CONTENT_REG_95_64_SZ 32
+#define F1_CIS_CONTENT_REG_127_96_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_127_96_SFT 0
+#define F1_CIS_CONTENT_REG_127_96_HI 31
+#define F1_CIS_CONTENT_REG_127_96_SZ 32
+#define F1_CIS_CONTENT_REG_159_128_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_159_128_SFT 0
+#define F1_CIS_CONTENT_REG_159_128_HI 31
+#define F1_CIS_CONTENT_REG_159_128_SZ 32
+#define F1_CIS_CONTENT_REG_191_160_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_191_160_SFT 0
+#define F1_CIS_CONTENT_REG_191_160_HI 31
+#define F1_CIS_CONTENT_REG_191_160_SZ 32
+#define F1_CIS_CONTENT_REG_223_192_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_223_192_SFT 0
+#define F1_CIS_CONTENT_REG_223_192_HI 31
+#define F1_CIS_CONTENT_REG_223_192_SZ 32
+#define F1_CIS_CONTENT_REG_255_224_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_255_224_SFT 0
+#define F1_CIS_CONTENT_REG_255_224_HI 31
+#define F1_CIS_CONTENT_REG_255_224_SZ 32
+#define F1_CIS_CONTENT_REG_287_256_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_287_256_SFT 0
+#define F1_CIS_CONTENT_REG_287_256_HI 31
+#define F1_CIS_CONTENT_REG_287_256_SZ 32
+#define F1_CIS_CONTENT_REG_319_288_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_319_288_SFT 0
+#define F1_CIS_CONTENT_REG_319_288_HI 31
+#define F1_CIS_CONTENT_REG_319_288_SZ 32
+#define F1_CIS_CONTENT_REG_351_320_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_351_320_SFT 0
+#define F1_CIS_CONTENT_REG_351_320_HI 31
+#define F1_CIS_CONTENT_REG_351_320_SZ 32
+#define F1_CIS_CONTENT_REG_383_352_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_383_352_SFT 0
+#define F1_CIS_CONTENT_REG_383_352_HI 31
+#define F1_CIS_CONTENT_REG_383_352_SZ 32
+#define F1_CIS_CONTENT_REG_415_384_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_415_384_SFT 0
+#define F1_CIS_CONTENT_REG_415_384_HI 31
+#define F1_CIS_CONTENT_REG_415_384_SZ 32
+#define F1_CIS_CONTENT_REG_447_416_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_447_416_SFT 0
+#define F1_CIS_CONTENT_REG_447_416_HI 31
+#define F1_CIS_CONTENT_REG_447_416_SZ 32
+#define F1_CIS_CONTENT_REG_479_448_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_479_448_SFT 0
+#define F1_CIS_CONTENT_REG_479_448_HI 31
+#define F1_CIS_CONTENT_REG_479_448_SZ 32
+#define F1_CIS_CONTENT_REG_511_480_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_511_480_SFT 0
+#define F1_CIS_CONTENT_REG_511_480_HI 31
+#define F1_CIS_CONTENT_REG_511_480_SZ 32
+#define SPI_MODE_MSK 0xffffffff
+#define SPI_MODE_I_MSK 0x00000000
+#define SPI_MODE_SFT 0
+#define SPI_MODE_HI 31
+#define SPI_MODE_SZ 32
+#define RX_QUOTA_MSK 0x0000ffff
+#define RX_QUOTA_I_MSK 0xffff0000
+#define RX_QUOTA_SFT 0
+#define RX_QUOTA_HI 15
+#define RX_QUOTA_SZ 16
+#define CONDI_NUM_MSK 0x000000ff
+#define CONDI_NUM_I_MSK 0xffffff00
+#define CONDI_NUM_SFT 0
+#define CONDI_NUM_HI 7
+#define CONDI_NUM_SZ 8
+#define HOST_PATH_MSK 0x00000001
+#define HOST_PATH_I_MSK 0xfffffffe
+#define HOST_PATH_SFT 0
+#define HOST_PATH_HI 0
+#define HOST_PATH_SZ 1
+#define TX_SEG_MSK 0xffffffff
+#define TX_SEG_I_MSK 0x00000000
+#define TX_SEG_SFT 0
+#define TX_SEG_HI 31
+#define TX_SEG_SZ 32
+#define BRST_MODE_MSK 0x00000001
+#define BRST_MODE_I_MSK 0xfffffffe
+#define BRST_MODE_SFT 0
+#define BRST_MODE_HI 0
+#define BRST_MODE_SZ 1
+#define CLK_WIDTH_MSK 0x0000ffff
+#define CLK_WIDTH_I_MSK 0xffff0000
+#define CLK_WIDTH_SFT 0
+#define CLK_WIDTH_HI 15
+#define CLK_WIDTH_SZ 16
+#define CSN_INTER_MSK 0xffff0000
+#define CSN_INTER_I_MSK 0x0000ffff
+#define CSN_INTER_SFT 16
+#define CSN_INTER_HI 31
+#define CSN_INTER_SZ 16
+#define BACK_DLY_MSK 0x0000ffff
+#define BACK_DLY_I_MSK 0xffff0000
+#define BACK_DLY_SFT 0
+#define BACK_DLY_HI 15
+#define BACK_DLY_SZ 16
+#define FRONT_DLY_MSK 0xffff0000
+#define FRONT_DLY_I_MSK 0x0000ffff
+#define FRONT_DLY_SFT 16
+#define FRONT_DLY_HI 31
+#define FRONT_DLY_SZ 16
+#define RX_FIFO_FAIL_MSK 0x00000002
+#define RX_FIFO_FAIL_I_MSK 0xfffffffd
+#define RX_FIFO_FAIL_SFT 1
+#define RX_FIFO_FAIL_HI 1
+#define RX_FIFO_FAIL_SZ 1
+#define RX_HOST_FAIL_MSK 0x00000004
+#define RX_HOST_FAIL_I_MSK 0xfffffffb
+#define RX_HOST_FAIL_SFT 2
+#define RX_HOST_FAIL_HI 2
+#define RX_HOST_FAIL_SZ 1
+#define TX_FIFO_FAIL_MSK 0x00000008
+#define TX_FIFO_FAIL_I_MSK 0xfffffff7
+#define TX_FIFO_FAIL_SFT 3
+#define TX_FIFO_FAIL_HI 3
+#define TX_FIFO_FAIL_SZ 1
+#define TX_HOST_FAIL_MSK 0x00000010
+#define TX_HOST_FAIL_I_MSK 0xffffffef
+#define TX_HOST_FAIL_SFT 4
+#define TX_HOST_FAIL_HI 4
+#define TX_HOST_FAIL_SZ 1
+#define SPI_DOUBLE_ALLOC_MSK 0x00000020
+#define SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
+#define SPI_DOUBLE_ALLOC_SFT 5
+#define SPI_DOUBLE_ALLOC_HI 5
+#define SPI_DOUBLE_ALLOC_SZ 1
+#define SPI_TX_NO_ALLOC_MSK 0x00000040
+#define SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
+#define SPI_TX_NO_ALLOC_SFT 6
+#define SPI_TX_NO_ALLOC_HI 6
+#define SPI_TX_NO_ALLOC_SZ 1
+#define RDATA_RDY_MSK 0x00000080
+#define RDATA_RDY_I_MSK 0xffffff7f
+#define RDATA_RDY_SFT 7
+#define RDATA_RDY_HI 7
+#define RDATA_RDY_SZ 1
+#define SPI_ALLOC_STATUS_MSK 0x00000100
+#define SPI_ALLOC_STATUS_I_MSK 0xfffffeff
+#define SPI_ALLOC_STATUS_SFT 8
+#define SPI_ALLOC_STATUS_HI 8
+#define SPI_ALLOC_STATUS_SZ 1
+#define SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
+#define SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
+#define SPI_DBG_WR_FIFO_FULL_SFT 9
+#define SPI_DBG_WR_FIFO_FULL_HI 9
+#define SPI_DBG_WR_FIFO_FULL_SZ 1
+#define RX_LEN_MSK 0xffff0000
+#define RX_LEN_I_MSK 0x0000ffff
+#define RX_LEN_SFT 16
+#define RX_LEN_HI 31
+#define RX_LEN_SZ 16
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
+#define SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
+#define SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
+#define SPI_HOST_TX_ALLOC_PKBUF_SFT 8
+#define SPI_HOST_TX_ALLOC_PKBUF_HI 8
+#define SPI_HOST_TX_ALLOC_PKBUF_SZ 1
+#define SPI_TX_ALLOC_SIZE_MSK 0x000000ff
+#define SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
+#define SPI_TX_ALLOC_SIZE_SFT 0
+#define SPI_TX_ALLOC_SIZE_HI 7
+#define SPI_TX_ALLOC_SIZE_SZ 8
+#define RD_DAT_CNT_MSK 0x0000ffff
+#define RD_DAT_CNT_I_MSK 0xffff0000
+#define RD_DAT_CNT_SFT 0
+#define RD_DAT_CNT_HI 15
+#define RD_DAT_CNT_SZ 16
+#define RD_STS_CNT_MSK 0xffff0000
+#define RD_STS_CNT_I_MSK 0x0000ffff
+#define RD_STS_CNT_SFT 16
+#define RD_STS_CNT_HI 31
+#define RD_STS_CNT_SZ 16
+#define JUDGE_CNT_MSK 0x0000ffff
+#define JUDGE_CNT_I_MSK 0xffff0000
+#define JUDGE_CNT_SFT 0
+#define JUDGE_CNT_HI 15
+#define JUDGE_CNT_SZ 16
+#define RD_STS_CNT_CLR_MSK 0x00010000
+#define RD_STS_CNT_CLR_I_MSK 0xfffeffff
+#define RD_STS_CNT_CLR_SFT 16
+#define RD_STS_CNT_CLR_HI 16
+#define RD_STS_CNT_CLR_SZ 1
+#define RD_DAT_CNT_CLR_MSK 0x00020000
+#define RD_DAT_CNT_CLR_I_MSK 0xfffdffff
+#define RD_DAT_CNT_CLR_SFT 17
+#define RD_DAT_CNT_CLR_HI 17
+#define RD_DAT_CNT_CLR_SZ 1
+#define JUDGE_CNT_CLR_MSK 0x00040000
+#define JUDGE_CNT_CLR_I_MSK 0xfffbffff
+#define JUDGE_CNT_CLR_SFT 18
+#define JUDGE_CNT_CLR_HI 18
+#define JUDGE_CNT_CLR_SZ 1
+#define TX_DONE_CNT_MSK 0x0000ffff
+#define TX_DONE_CNT_I_MSK 0xffff0000
+#define TX_DONE_CNT_SFT 0
+#define TX_DONE_CNT_HI 15
+#define TX_DONE_CNT_SZ 16
+#define TX_DISCARD_CNT_MSK 0xffff0000
+#define TX_DISCARD_CNT_I_MSK 0x0000ffff
+#define TX_DISCARD_CNT_SFT 16
+#define TX_DISCARD_CNT_HI 31
+#define TX_DISCARD_CNT_SZ 16
+#define TX_SET_CNT_MSK 0x0000ffff
+#define TX_SET_CNT_I_MSK 0xffff0000
+#define TX_SET_CNT_SFT 0
+#define TX_SET_CNT_HI 15
+#define TX_SET_CNT_SZ 16
+#define TX_DISCARD_CNT_CLR_MSK 0x00010000
+#define TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
+#define TX_DISCARD_CNT_CLR_SFT 16
+#define TX_DISCARD_CNT_CLR_HI 16
+#define TX_DISCARD_CNT_CLR_SZ 1
+#define TX_DONE_CNT_CLR_MSK 0x00020000
+#define TX_DONE_CNT_CLR_I_MSK 0xfffdffff
+#define TX_DONE_CNT_CLR_SFT 17
+#define TX_DONE_CNT_CLR_HI 17
+#define TX_DONE_CNT_CLR_SZ 1
+#define TX_SET_CNT_CLR_MSK 0x00040000
+#define TX_SET_CNT_CLR_I_MSK 0xfffbffff
+#define TX_SET_CNT_CLR_SFT 18
+#define TX_SET_CNT_CLR_HI 18
+#define TX_SET_CNT_CLR_SZ 1
+#define DAT_MODE_OFF_MSK 0x00080000
+#define DAT_MODE_OFF_I_MSK 0xfff7ffff
+#define DAT_MODE_OFF_SFT 19
+#define DAT_MODE_OFF_HI 19
+#define DAT_MODE_OFF_SZ 1
+#define TX_FIFO_RESIDUE_MSK 0x00700000
+#define TX_FIFO_RESIDUE_I_MSK 0xff8fffff
+#define TX_FIFO_RESIDUE_SFT 20
+#define TX_FIFO_RESIDUE_HI 22
+#define TX_FIFO_RESIDUE_SZ 3
+#define RX_FIFO_RESIDUE_MSK 0x07000000
+#define RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
+#define RX_FIFO_RESIDUE_SFT 24
+#define RX_FIFO_RESIDUE_HI 26
+#define RX_FIFO_RESIDUE_SZ 3
+#define RX_RDY_MSK 0x00000001
+#define RX_RDY_I_MSK 0xfffffffe
+#define RX_RDY_SFT 0
+#define RX_RDY_HI 0
+#define RX_RDY_SZ 1
+#define SDIO_SYS_INT_MSK 0x00000004
+#define SDIO_SYS_INT_I_MSK 0xfffffffb
+#define SDIO_SYS_INT_SFT 2
+#define SDIO_SYS_INT_HI 2
+#define SDIO_SYS_INT_SZ 1
+#define EDCA0_LOWTHOLD_INT_MSK 0x00000008
+#define EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define EDCA0_LOWTHOLD_INT_SFT 3
+#define EDCA0_LOWTHOLD_INT_HI 3
+#define EDCA0_LOWTHOLD_INT_SZ 1
+#define EDCA1_LOWTHOLD_INT_MSK 0x00000010
+#define EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
+#define EDCA1_LOWTHOLD_INT_SFT 4
+#define EDCA1_LOWTHOLD_INT_HI 4
+#define EDCA1_LOWTHOLD_INT_SZ 1
+#define EDCA2_LOWTHOLD_INT_MSK 0x00000020
+#define EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define EDCA2_LOWTHOLD_INT_SFT 5
+#define EDCA2_LOWTHOLD_INT_HI 5
+#define EDCA2_LOWTHOLD_INT_SZ 1
+#define EDCA3_LOWTHOLD_INT_MSK 0x00000040
+#define EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define EDCA3_LOWTHOLD_INT_SFT 6
+#define EDCA3_LOWTHOLD_INT_HI 6
+#define EDCA3_LOWTHOLD_INT_SZ 1
+#define TX_LIMIT_INT_IN_MSK 0x00000080
+#define TX_LIMIT_INT_IN_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_IN_SFT 7
+#define TX_LIMIT_INT_IN_HI 7
+#define TX_LIMIT_INT_IN_SZ 1
+#define SPI_FN1_MSK 0x00007f00
+#define SPI_FN1_I_MSK 0xffff80ff
+#define SPI_FN1_SFT 8
+#define SPI_FN1_HI 14
+#define SPI_FN1_SZ 7
+#define SPI_CLK_EN_INT_MSK 0x00008000
+#define SPI_CLK_EN_INT_I_MSK 0xffff7fff
+#define SPI_CLK_EN_INT_SFT 15
+#define SPI_CLK_EN_INT_HI 15
+#define SPI_CLK_EN_INT_SZ 1
+#define SPI_HOST_MASK_MSK 0x00ff0000
+#define SPI_HOST_MASK_I_MSK 0xff00ffff
+#define SPI_HOST_MASK_SFT 16
+#define SPI_HOST_MASK_HI 23
+#define SPI_HOST_MASK_SZ 8
+#define I2CM_INT_WDONE_MSK 0x00000001
+#define I2CM_INT_WDONE_I_MSK 0xfffffffe
+#define I2CM_INT_WDONE_SFT 0
+#define I2CM_INT_WDONE_HI 0
+#define I2CM_INT_WDONE_SZ 1
+#define I2CM_INT_RDONE_MSK 0x00000002
+#define I2CM_INT_RDONE_I_MSK 0xfffffffd
+#define I2CM_INT_RDONE_SFT 1
+#define I2CM_INT_RDONE_HI 1
+#define I2CM_INT_RDONE_SZ 1
+#define I2CM_IDLE_MSK 0x00000004
+#define I2CM_IDLE_I_MSK 0xfffffffb
+#define I2CM_IDLE_SFT 2
+#define I2CM_IDLE_HI 2
+#define I2CM_IDLE_SZ 1
+#define I2CM_INT_MISMATCH_MSK 0x00000008
+#define I2CM_INT_MISMATCH_I_MSK 0xfffffff7
+#define I2CM_INT_MISMATCH_SFT 3
+#define I2CM_INT_MISMATCH_HI 3
+#define I2CM_INT_MISMATCH_SZ 1
+#define I2CM_PSCL_MSK 0x00003ff0
+#define I2CM_PSCL_I_MSK 0xffffc00f
+#define I2CM_PSCL_SFT 4
+#define I2CM_PSCL_HI 13
+#define I2CM_PSCL_SZ 10
+#define I2CM_MANUAL_MODE_MSK 0x00010000
+#define I2CM_MANUAL_MODE_I_MSK 0xfffeffff
+#define I2CM_MANUAL_MODE_SFT 16
+#define I2CM_MANUAL_MODE_HI 16
+#define I2CM_MANUAL_MODE_SZ 1
+#define I2CM_INT_WDATA_NEED_MSK 0x00020000
+#define I2CM_INT_WDATA_NEED_I_MSK 0xfffdffff
+#define I2CM_INT_WDATA_NEED_SFT 17
+#define I2CM_INT_WDATA_NEED_HI 17
+#define I2CM_INT_WDATA_NEED_SZ 1
+#define I2CM_INT_RDATA_NEED_MSK 0x00040000
+#define I2CM_INT_RDATA_NEED_I_MSK 0xfffbffff
+#define I2CM_INT_RDATA_NEED_SFT 18
+#define I2CM_INT_RDATA_NEED_HI 18
+#define I2CM_INT_RDATA_NEED_SZ 1
+#define I2CM_DEV_A_MSK 0x000003ff
+#define I2CM_DEV_A_I_MSK 0xfffffc00
+#define I2CM_DEV_A_SFT 0
+#define I2CM_DEV_A_HI 9
+#define I2CM_DEV_A_SZ 10
+#define I2CM_DEV_A10B_MSK 0x00004000
+#define I2CM_DEV_A10B_I_MSK 0xffffbfff
+#define I2CM_DEV_A10B_SFT 14
+#define I2CM_DEV_A10B_HI 14
+#define I2CM_DEV_A10B_SZ 1
+#define I2CM_RX_MSK 0x00008000
+#define I2CM_RX_I_MSK 0xffff7fff
+#define I2CM_RX_SFT 15
+#define I2CM_RX_HI 15
+#define I2CM_RX_SZ 1
+#define I2CM_LEN_MSK 0x0000ffff
+#define I2CM_LEN_I_MSK 0xffff0000
+#define I2CM_LEN_SFT 0
+#define I2CM_LEN_HI 15
+#define I2CM_LEN_SZ 16
+#define I2CM_T_LEFT_MSK 0x00070000
+#define I2CM_T_LEFT_I_MSK 0xfff8ffff
+#define I2CM_T_LEFT_SFT 16
+#define I2CM_T_LEFT_HI 18
+#define I2CM_T_LEFT_SZ 3
+#define I2CM_R_GET_MSK 0x07000000
+#define I2CM_R_GET_I_MSK 0xf8ffffff
+#define I2CM_R_GET_SFT 24
+#define I2CM_R_GET_HI 26
+#define I2CM_R_GET_SZ 3
+#define I2CM_WDAT_MSK 0xffffffff
+#define I2CM_WDAT_I_MSK 0x00000000
+#define I2CM_WDAT_SFT 0
+#define I2CM_WDAT_HI 31
+#define I2CM_WDAT_SZ 32
+#define I2CM_RDAT_MSK 0xffffffff
+#define I2CM_RDAT_I_MSK 0x00000000
+#define I2CM_RDAT_SFT 0
+#define I2CM_RDAT_HI 31
+#define I2CM_RDAT_SZ 32
+#define I2CM_SR_LEN_MSK 0x0000ffff
+#define I2CM_SR_LEN_I_MSK 0xffff0000
+#define I2CM_SR_LEN_SFT 0
+#define I2CM_SR_LEN_HI 15
+#define I2CM_SR_LEN_SZ 16
+#define I2CM_SR_RX_MSK 0x00010000
+#define I2CM_SR_RX_I_MSK 0xfffeffff
+#define I2CM_SR_RX_SFT 16
+#define I2CM_SR_RX_HI 16
+#define I2CM_SR_RX_SZ 1
+#define I2CM_REPEAT_START_MSK 0x00020000
+#define I2CM_REPEAT_START_I_MSK 0xfffdffff
+#define I2CM_REPEAT_START_SFT 17
+#define I2CM_REPEAT_START_HI 17
+#define I2CM_REPEAT_START_SZ 1
+#define UART_DATA_MSK 0x000000ff
+#define UART_DATA_I_MSK 0xffffff00
+#define UART_DATA_SFT 0
+#define UART_DATA_HI 7
+#define UART_DATA_SZ 8
+#define DATA_RDY_IE_MSK 0x00000001
+#define DATA_RDY_IE_I_MSK 0xfffffffe
+#define DATA_RDY_IE_SFT 0
+#define DATA_RDY_IE_HI 0
+#define DATA_RDY_IE_SZ 1
+#define THR_EMPTY_IE_MSK 0x00000002
+#define THR_EMPTY_IE_I_MSK 0xfffffffd
+#define THR_EMPTY_IE_SFT 1
+#define THR_EMPTY_IE_HI 1
+#define THR_EMPTY_IE_SZ 1
+#define RX_LINESTS_IE_MSK 0x00000004
+#define RX_LINESTS_IE_I_MSK 0xfffffffb
+#define RX_LINESTS_IE_SFT 2
+#define RX_LINESTS_IE_HI 2
+#define RX_LINESTS_IE_SZ 1
+#define MDM_STS_IE_MSK 0x00000008
+#define MDM_STS_IE_I_MSK 0xfffffff7
+#define MDM_STS_IE_SFT 3
+#define MDM_STS_IE_HI 3
+#define MDM_STS_IE_SZ 1
+#define DMA_RXEND_IE_MSK 0x00000040
+#define DMA_RXEND_IE_I_MSK 0xffffffbf
+#define DMA_RXEND_IE_SFT 6
+#define DMA_RXEND_IE_HI 6
+#define DMA_RXEND_IE_SZ 1
+#define DMA_TXEND_IE_MSK 0x00000080
+#define DMA_TXEND_IE_I_MSK 0xffffff7f
+#define DMA_TXEND_IE_SFT 7
+#define DMA_TXEND_IE_HI 7
+#define DMA_TXEND_IE_SZ 1
+#define FIFO_EN_MSK 0x00000001
+#define FIFO_EN_I_MSK 0xfffffffe
+#define FIFO_EN_SFT 0
+#define FIFO_EN_HI 0
+#define FIFO_EN_SZ 1
+#define RXFIFO_RST_MSK 0x00000002
+#define RXFIFO_RST_I_MSK 0xfffffffd
+#define RXFIFO_RST_SFT 1
+#define RXFIFO_RST_HI 1
+#define RXFIFO_RST_SZ 1
+#define TXFIFO_RST_MSK 0x00000004
+#define TXFIFO_RST_I_MSK 0xfffffffb
+#define TXFIFO_RST_SFT 2
+#define TXFIFO_RST_HI 2
+#define TXFIFO_RST_SZ 1
+#define DMA_MODE_MSK 0x00000008
+#define DMA_MODE_I_MSK 0xfffffff7
+#define DMA_MODE_SFT 3
+#define DMA_MODE_HI 3
+#define DMA_MODE_SZ 1
+#define EN_AUTO_RTS_MSK 0x00000010
+#define EN_AUTO_RTS_I_MSK 0xffffffef
+#define EN_AUTO_RTS_SFT 4
+#define EN_AUTO_RTS_HI 4
+#define EN_AUTO_RTS_SZ 1
+#define EN_AUTO_CTS_MSK 0x00000020
+#define EN_AUTO_CTS_I_MSK 0xffffffdf
+#define EN_AUTO_CTS_SFT 5
+#define EN_AUTO_CTS_HI 5
+#define EN_AUTO_CTS_SZ 1
+#define RXFIFO_TRGLVL_MSK 0x000000c0
+#define RXFIFO_TRGLVL_I_MSK 0xffffff3f
+#define RXFIFO_TRGLVL_SFT 6
+#define RXFIFO_TRGLVL_HI 7
+#define RXFIFO_TRGLVL_SZ 2
+#define WORD_LEN_MSK 0x00000003
+#define WORD_LEN_I_MSK 0xfffffffc
+#define WORD_LEN_SFT 0
+#define WORD_LEN_HI 1
+#define WORD_LEN_SZ 2
+#define STOP_BIT_MSK 0x00000004
+#define STOP_BIT_I_MSK 0xfffffffb
+#define STOP_BIT_SFT 2
+#define STOP_BIT_HI 2
+#define STOP_BIT_SZ 1
+#define PARITY_EN_MSK 0x00000008
+#define PARITY_EN_I_MSK 0xfffffff7
+#define PARITY_EN_SFT 3
+#define PARITY_EN_HI 3
+#define PARITY_EN_SZ 1
+#define EVEN_PARITY_MSK 0x00000010
+#define EVEN_PARITY_I_MSK 0xffffffef
+#define EVEN_PARITY_SFT 4
+#define EVEN_PARITY_HI 4
+#define EVEN_PARITY_SZ 1
+#define FORCE_PARITY_MSK 0x00000020
+#define FORCE_PARITY_I_MSK 0xffffffdf
+#define FORCE_PARITY_SFT 5
+#define FORCE_PARITY_HI 5
+#define FORCE_PARITY_SZ 1
+#define SET_BREAK_MSK 0x00000040
+#define SET_BREAK_I_MSK 0xffffffbf
+#define SET_BREAK_SFT 6
+#define SET_BREAK_HI 6
+#define SET_BREAK_SZ 1
+#define DLAB_MSK 0x00000080
+#define DLAB_I_MSK 0xffffff7f
+#define DLAB_SFT 7
+#define DLAB_HI 7
+#define DLAB_SZ 1
+#define DTR_MSK 0x00000001
+#define DTR_I_MSK 0xfffffffe
+#define DTR_SFT 0
+#define DTR_HI 0
+#define DTR_SZ 1
+#define RTS_MSK 0x00000002
+#define RTS_I_MSK 0xfffffffd
+#define RTS_SFT 1
+#define RTS_HI 1
+#define RTS_SZ 1
+#define OUT_1_MSK 0x00000004
+#define OUT_1_I_MSK 0xfffffffb
+#define OUT_1_SFT 2
+#define OUT_1_HI 2
+#define OUT_1_SZ 1
+#define OUT_2_MSK 0x00000008
+#define OUT_2_I_MSK 0xfffffff7
+#define OUT_2_SFT 3
+#define OUT_2_HI 3
+#define OUT_2_SZ 1
+#define LOOP_BACK_MSK 0x00000010
+#define LOOP_BACK_I_MSK 0xffffffef
+#define LOOP_BACK_SFT 4
+#define LOOP_BACK_HI 4
+#define LOOP_BACK_SZ 1
+#define DATA_RDY_MSK 0x00000001
+#define DATA_RDY_I_MSK 0xfffffffe
+#define DATA_RDY_SFT 0
+#define DATA_RDY_HI 0
+#define DATA_RDY_SZ 1
+#define OVERRUN_ERR_MSK 0x00000002
+#define OVERRUN_ERR_I_MSK 0xfffffffd
+#define OVERRUN_ERR_SFT 1
+#define OVERRUN_ERR_HI 1
+#define OVERRUN_ERR_SZ 1
+#define PARITY_ERR_MSK 0x00000004
+#define PARITY_ERR_I_MSK 0xfffffffb
+#define PARITY_ERR_SFT 2
+#define PARITY_ERR_HI 2
+#define PARITY_ERR_SZ 1
+#define FRAMING_ERR_MSK 0x00000008
+#define FRAMING_ERR_I_MSK 0xfffffff7
+#define FRAMING_ERR_SFT 3
+#define FRAMING_ERR_HI 3
+#define FRAMING_ERR_SZ 1
+#define BREAK_INT_MSK 0x00000010
+#define BREAK_INT_I_MSK 0xffffffef
+#define BREAK_INT_SFT 4
+#define BREAK_INT_HI 4
+#define BREAK_INT_SZ 1
+#define THR_EMPTY_MSK 0x00000020
+#define THR_EMPTY_I_MSK 0xffffffdf
+#define THR_EMPTY_SFT 5
+#define THR_EMPTY_HI 5
+#define THR_EMPTY_SZ 1
+#define TX_EMPTY_MSK 0x00000040
+#define TX_EMPTY_I_MSK 0xffffffbf
+#define TX_EMPTY_SFT 6
+#define TX_EMPTY_HI 6
+#define TX_EMPTY_SZ 1
+#define FIFODATA_ERR_MSK 0x00000080
+#define FIFODATA_ERR_I_MSK 0xffffff7f
+#define FIFODATA_ERR_SFT 7
+#define FIFODATA_ERR_HI 7
+#define FIFODATA_ERR_SZ 1
+#define DELTA_CTS_MSK 0x00000001
+#define DELTA_CTS_I_MSK 0xfffffffe
+#define DELTA_CTS_SFT 0
+#define DELTA_CTS_HI 0
+#define DELTA_CTS_SZ 1
+#define DELTA_DSR_MSK 0x00000002
+#define DELTA_DSR_I_MSK 0xfffffffd
+#define DELTA_DSR_SFT 1
+#define DELTA_DSR_HI 1
+#define DELTA_DSR_SZ 1
+#define TRAILEDGE_RI_MSK 0x00000004
+#define TRAILEDGE_RI_I_MSK 0xfffffffb
+#define TRAILEDGE_RI_SFT 2
+#define TRAILEDGE_RI_HI 2
+#define TRAILEDGE_RI_SZ 1
+#define DELTA_CD_MSK 0x00000008
+#define DELTA_CD_I_MSK 0xfffffff7
+#define DELTA_CD_SFT 3
+#define DELTA_CD_HI 3
+#define DELTA_CD_SZ 1
+#define CTS_MSK 0x00000010
+#define CTS_I_MSK 0xffffffef
+#define CTS_SFT 4
+#define CTS_HI 4
+#define CTS_SZ 1
+#define DSR_MSK 0x00000020
+#define DSR_I_MSK 0xffffffdf
+#define DSR_SFT 5
+#define DSR_HI 5
+#define DSR_SZ 1
+#define RI_MSK 0x00000040
+#define RI_I_MSK 0xffffffbf
+#define RI_SFT 6
+#define RI_HI 6
+#define RI_SZ 1
+#define CD_MSK 0x00000080
+#define CD_I_MSK 0xffffff7f
+#define CD_SFT 7
+#define CD_HI 7
+#define CD_SZ 1
+#define BRDC_DIV_MSK 0x0000ffff
+#define BRDC_DIV_I_MSK 0xffff0000
+#define BRDC_DIV_SFT 0
+#define BRDC_DIV_HI 15
+#define BRDC_DIV_SZ 16
+#define RTHR_L_MSK 0x0000000f
+#define RTHR_L_I_MSK 0xfffffff0
+#define RTHR_L_SFT 0
+#define RTHR_L_HI 3
+#define RTHR_L_SZ 4
+#define RTHR_H_MSK 0x000000f0
+#define RTHR_H_I_MSK 0xffffff0f
+#define RTHR_H_SFT 4
+#define RTHR_H_HI 7
+#define RTHR_H_SZ 4
+#define INT_IDCODE_MSK 0x0000000f
+#define INT_IDCODE_I_MSK 0xfffffff0
+#define INT_IDCODE_SFT 0
+#define INT_IDCODE_HI 3
+#define INT_IDCODE_SZ 4
+#define FIFOS_ENABLED_MSK 0x000000c0
+#define FIFOS_ENABLED_I_MSK 0xffffff3f
+#define FIFOS_ENABLED_SFT 6
+#define FIFOS_ENABLED_HI 7
+#define FIFOS_ENABLED_SZ 2
+#define DAT_UART_DATA_MSK 0x000000ff
+#define DAT_UART_DATA_I_MSK 0xffffff00
+#define DAT_UART_DATA_SFT 0
+#define DAT_UART_DATA_HI 7
+#define DAT_UART_DATA_SZ 8
+#define DAT_DATA_RDY_IE_MSK 0x00000001
+#define DAT_DATA_RDY_IE_I_MSK 0xfffffffe
+#define DAT_DATA_RDY_IE_SFT 0
+#define DAT_DATA_RDY_IE_HI 0
+#define DAT_DATA_RDY_IE_SZ 1
+#define DAT_THR_EMPTY_IE_MSK 0x00000002
+#define DAT_THR_EMPTY_IE_I_MSK 0xfffffffd
+#define DAT_THR_EMPTY_IE_SFT 1
+#define DAT_THR_EMPTY_IE_HI 1
+#define DAT_THR_EMPTY_IE_SZ 1
+#define DAT_RX_LINESTS_IE_MSK 0x00000004
+#define DAT_RX_LINESTS_IE_I_MSK 0xfffffffb
+#define DAT_RX_LINESTS_IE_SFT 2
+#define DAT_RX_LINESTS_IE_HI 2
+#define DAT_RX_LINESTS_IE_SZ 1
+#define DAT_MDM_STS_IE_MSK 0x00000008
+#define DAT_MDM_STS_IE_I_MSK 0xfffffff7
+#define DAT_MDM_STS_IE_SFT 3
+#define DAT_MDM_STS_IE_HI 3
+#define DAT_MDM_STS_IE_SZ 1
+#define DAT_DMA_RXEND_IE_MSK 0x00000040
+#define DAT_DMA_RXEND_IE_I_MSK 0xffffffbf
+#define DAT_DMA_RXEND_IE_SFT 6
+#define DAT_DMA_RXEND_IE_HI 6
+#define DAT_DMA_RXEND_IE_SZ 1
+#define DAT_DMA_TXEND_IE_MSK 0x00000080
+#define DAT_DMA_TXEND_IE_I_MSK 0xffffff7f
+#define DAT_DMA_TXEND_IE_SFT 7
+#define DAT_DMA_TXEND_IE_HI 7
+#define DAT_DMA_TXEND_IE_SZ 1
+#define DAT_FIFO_EN_MSK 0x00000001
+#define DAT_FIFO_EN_I_MSK 0xfffffffe
+#define DAT_FIFO_EN_SFT 0
+#define DAT_FIFO_EN_HI 0
+#define DAT_FIFO_EN_SZ 1
+#define DAT_RXFIFO_RST_MSK 0x00000002
+#define DAT_RXFIFO_RST_I_MSK 0xfffffffd
+#define DAT_RXFIFO_RST_SFT 1
+#define DAT_RXFIFO_RST_HI 1
+#define DAT_RXFIFO_RST_SZ 1
+#define DAT_TXFIFO_RST_MSK 0x00000004
+#define DAT_TXFIFO_RST_I_MSK 0xfffffffb
+#define DAT_TXFIFO_RST_SFT 2
+#define DAT_TXFIFO_RST_HI 2
+#define DAT_TXFIFO_RST_SZ 1
+#define DAT_DMA_MODE_MSK 0x00000008
+#define DAT_DMA_MODE_I_MSK 0xfffffff7
+#define DAT_DMA_MODE_SFT 3
+#define DAT_DMA_MODE_HI 3
+#define DAT_DMA_MODE_SZ 1
+#define DAT_EN_AUTO_RTS_MSK 0x00000010
+#define DAT_EN_AUTO_RTS_I_MSK 0xffffffef
+#define DAT_EN_AUTO_RTS_SFT 4
+#define DAT_EN_AUTO_RTS_HI 4
+#define DAT_EN_AUTO_RTS_SZ 1
+#define DAT_EN_AUTO_CTS_MSK 0x00000020
+#define DAT_EN_AUTO_CTS_I_MSK 0xffffffdf
+#define DAT_EN_AUTO_CTS_SFT 5
+#define DAT_EN_AUTO_CTS_HI 5
+#define DAT_EN_AUTO_CTS_SZ 1
+#define DAT_RXFIFO_TRGLVL_MSK 0x000000c0
+#define DAT_RXFIFO_TRGLVL_I_MSK 0xffffff3f
+#define DAT_RXFIFO_TRGLVL_SFT 6
+#define DAT_RXFIFO_TRGLVL_HI 7
+#define DAT_RXFIFO_TRGLVL_SZ 2
+#define DAT_WORD_LEN_MSK 0x00000003
+#define DAT_WORD_LEN_I_MSK 0xfffffffc
+#define DAT_WORD_LEN_SFT 0
+#define DAT_WORD_LEN_HI 1
+#define DAT_WORD_LEN_SZ 2
+#define DAT_STOP_BIT_MSK 0x00000004
+#define DAT_STOP_BIT_I_MSK 0xfffffffb
+#define DAT_STOP_BIT_SFT 2
+#define DAT_STOP_BIT_HI 2
+#define DAT_STOP_BIT_SZ 1
+#define DAT_PARITY_EN_MSK 0x00000008
+#define DAT_PARITY_EN_I_MSK 0xfffffff7
+#define DAT_PARITY_EN_SFT 3
+#define DAT_PARITY_EN_HI 3
+#define DAT_PARITY_EN_SZ 1
+#define DAT_EVEN_PARITY_MSK 0x00000010
+#define DAT_EVEN_PARITY_I_MSK 0xffffffef
+#define DAT_EVEN_PARITY_SFT 4
+#define DAT_EVEN_PARITY_HI 4
+#define DAT_EVEN_PARITY_SZ 1
+#define DAT_FORCE_PARITY_MSK 0x00000020
+#define DAT_FORCE_PARITY_I_MSK 0xffffffdf
+#define DAT_FORCE_PARITY_SFT 5
+#define DAT_FORCE_PARITY_HI 5
+#define DAT_FORCE_PARITY_SZ 1
+#define DAT_SET_BREAK_MSK 0x00000040
+#define DAT_SET_BREAK_I_MSK 0xffffffbf
+#define DAT_SET_BREAK_SFT 6
+#define DAT_SET_BREAK_HI 6
+#define DAT_SET_BREAK_SZ 1
+#define DAT_DLAB_MSK 0x00000080
+#define DAT_DLAB_I_MSK 0xffffff7f
+#define DAT_DLAB_SFT 7
+#define DAT_DLAB_HI 7
+#define DAT_DLAB_SZ 1
+#define DAT_DTR_MSK 0x00000001
+#define DAT_DTR_I_MSK 0xfffffffe
+#define DAT_DTR_SFT 0
+#define DAT_DTR_HI 0
+#define DAT_DTR_SZ 1
+#define DAT_RTS_MSK 0x00000002
+#define DAT_RTS_I_MSK 0xfffffffd
+#define DAT_RTS_SFT 1
+#define DAT_RTS_HI 1
+#define DAT_RTS_SZ 1
+#define DAT_OUT_1_MSK 0x00000004
+#define DAT_OUT_1_I_MSK 0xfffffffb
+#define DAT_OUT_1_SFT 2
+#define DAT_OUT_1_HI 2
+#define DAT_OUT_1_SZ 1
+#define DAT_OUT_2_MSK 0x00000008
+#define DAT_OUT_2_I_MSK 0xfffffff7
+#define DAT_OUT_2_SFT 3
+#define DAT_OUT_2_HI 3
+#define DAT_OUT_2_SZ 1
+#define DAT_LOOP_BACK_MSK 0x00000010
+#define DAT_LOOP_BACK_I_MSK 0xffffffef
+#define DAT_LOOP_BACK_SFT 4
+#define DAT_LOOP_BACK_HI 4
+#define DAT_LOOP_BACK_SZ 1
+#define DAT_DATA_RDY_MSK 0x00000001
+#define DAT_DATA_RDY_I_MSK 0xfffffffe
+#define DAT_DATA_RDY_SFT 0
+#define DAT_DATA_RDY_HI 0
+#define DAT_DATA_RDY_SZ 1
+#define DAT_OVERRUN_ERR_MSK 0x00000002
+#define DAT_OVERRUN_ERR_I_MSK 0xfffffffd
+#define DAT_OVERRUN_ERR_SFT 1
+#define DAT_OVERRUN_ERR_HI 1
+#define DAT_OVERRUN_ERR_SZ 1
+#define DAT_PARITY_ERR_MSK 0x00000004
+#define DAT_PARITY_ERR_I_MSK 0xfffffffb
+#define DAT_PARITY_ERR_SFT 2
+#define DAT_PARITY_ERR_HI 2
+#define DAT_PARITY_ERR_SZ 1
+#define DAT_FRAMING_ERR_MSK 0x00000008
+#define DAT_FRAMING_ERR_I_MSK 0xfffffff7
+#define DAT_FRAMING_ERR_SFT 3
+#define DAT_FRAMING_ERR_HI 3
+#define DAT_FRAMING_ERR_SZ 1
+#define DAT_BREAK_INT_MSK 0x00000010
+#define DAT_BREAK_INT_I_MSK 0xffffffef
+#define DAT_BREAK_INT_SFT 4
+#define DAT_BREAK_INT_HI 4
+#define DAT_BREAK_INT_SZ 1
+#define DAT_THR_EMPTY_MSK 0x00000020
+#define DAT_THR_EMPTY_I_MSK 0xffffffdf
+#define DAT_THR_EMPTY_SFT 5
+#define DAT_THR_EMPTY_HI 5
+#define DAT_THR_EMPTY_SZ 1
+#define DAT_TX_EMPTY_MSK 0x00000040
+#define DAT_TX_EMPTY_I_MSK 0xffffffbf
+#define DAT_TX_EMPTY_SFT 6
+#define DAT_TX_EMPTY_HI 6
+#define DAT_TX_EMPTY_SZ 1
+#define DAT_FIFODATA_ERR_MSK 0x00000080
+#define DAT_FIFODATA_ERR_I_MSK 0xffffff7f
+#define DAT_FIFODATA_ERR_SFT 7
+#define DAT_FIFODATA_ERR_HI 7
+#define DAT_FIFODATA_ERR_SZ 1
+#define DAT_DELTA_CTS_MSK 0x00000001
+#define DAT_DELTA_CTS_I_MSK 0xfffffffe
+#define DAT_DELTA_CTS_SFT 0
+#define DAT_DELTA_CTS_HI 0
+#define DAT_DELTA_CTS_SZ 1
+#define DAT_DELTA_DSR_MSK 0x00000002
+#define DAT_DELTA_DSR_I_MSK 0xfffffffd
+#define DAT_DELTA_DSR_SFT 1
+#define DAT_DELTA_DSR_HI 1
+#define DAT_DELTA_DSR_SZ 1
+#define DAT_TRAILEDGE_RI_MSK 0x00000004
+#define DAT_TRAILEDGE_RI_I_MSK 0xfffffffb
+#define DAT_TRAILEDGE_RI_SFT 2
+#define DAT_TRAILEDGE_RI_HI 2
+#define DAT_TRAILEDGE_RI_SZ 1
+#define DAT_DELTA_CD_MSK 0x00000008
+#define DAT_DELTA_CD_I_MSK 0xfffffff7
+#define DAT_DELTA_CD_SFT 3
+#define DAT_DELTA_CD_HI 3
+#define DAT_DELTA_CD_SZ 1
+#define DAT_CTS_MSK 0x00000010
+#define DAT_CTS_I_MSK 0xffffffef
+#define DAT_CTS_SFT 4
+#define DAT_CTS_HI 4
+#define DAT_CTS_SZ 1
+#define DAT_DSR_MSK 0x00000020
+#define DAT_DSR_I_MSK 0xffffffdf
+#define DAT_DSR_SFT 5
+#define DAT_DSR_HI 5
+#define DAT_DSR_SZ 1
+#define DAT_RI_MSK 0x00000040
+#define DAT_RI_I_MSK 0xffffffbf
+#define DAT_RI_SFT 6
+#define DAT_RI_HI 6
+#define DAT_RI_SZ 1
+#define DAT_CD_MSK 0x00000080
+#define DAT_CD_I_MSK 0xffffff7f
+#define DAT_CD_SFT 7
+#define DAT_CD_HI 7
+#define DAT_CD_SZ 1
+#define DAT_BRDC_DIV_MSK 0x0000ffff
+#define DAT_BRDC_DIV_I_MSK 0xffff0000
+#define DAT_BRDC_DIV_SFT 0
+#define DAT_BRDC_DIV_HI 15
+#define DAT_BRDC_DIV_SZ 16
+#define DAT_RTHR_L_MSK 0x0000000f
+#define DAT_RTHR_L_I_MSK 0xfffffff0
+#define DAT_RTHR_L_SFT 0
+#define DAT_RTHR_L_HI 3
+#define DAT_RTHR_L_SZ 4
+#define DAT_RTHR_H_MSK 0x000000f0
+#define DAT_RTHR_H_I_MSK 0xffffff0f
+#define DAT_RTHR_H_SFT 4
+#define DAT_RTHR_H_HI 7
+#define DAT_RTHR_H_SZ 4
+#define DAT_INT_IDCODE_MSK 0x0000000f
+#define DAT_INT_IDCODE_I_MSK 0xfffffff0
+#define DAT_INT_IDCODE_SFT 0
+#define DAT_INT_IDCODE_HI 3
+#define DAT_INT_IDCODE_SZ 4
+#define DAT_FIFOS_ENABLED_MSK 0x000000c0
+#define DAT_FIFOS_ENABLED_I_MSK 0xffffff3f
+#define DAT_FIFOS_ENABLED_SFT 6
+#define DAT_FIFOS_ENABLED_HI 7
+#define DAT_FIFOS_ENABLED_SZ 2
+#define MASK_TOP_MSK 0xffffffff
+#define MASK_TOP_I_MSK 0x00000000
+#define MASK_TOP_SFT 0
+#define MASK_TOP_HI 31
+#define MASK_TOP_SZ 32
+#define INT_MODE_MSK 0xffffffff
+#define INT_MODE_I_MSK 0x00000000
+#define INT_MODE_SFT 0
+#define INT_MODE_HI 31
+#define INT_MODE_SZ 32
+#define IRQ_PHY_0_MSK 0x00000001
+#define IRQ_PHY_0_I_MSK 0xfffffffe
+#define IRQ_PHY_0_SFT 0
+#define IRQ_PHY_0_HI 0
+#define IRQ_PHY_0_SZ 1
+#define IRQ_PHY_1_MSK 0x00000002
+#define IRQ_PHY_1_I_MSK 0xfffffffd
+#define IRQ_PHY_1_SFT 1
+#define IRQ_PHY_1_HI 1
+#define IRQ_PHY_1_SZ 1
+#define IRQ_SDIO_MSK 0x00000004
+#define IRQ_SDIO_I_MSK 0xfffffffb
+#define IRQ_SDIO_SFT 2
+#define IRQ_SDIO_HI 2
+#define IRQ_SDIO_SZ 1
+#define IRQ_BEACON_DONE_MSK 0x00000008
+#define IRQ_BEACON_DONE_I_MSK 0xfffffff7
+#define IRQ_BEACON_DONE_SFT 3
+#define IRQ_BEACON_DONE_HI 3
+#define IRQ_BEACON_DONE_SZ 1
+#define IRQ_BEACON_MSK 0x00000010
+#define IRQ_BEACON_I_MSK 0xffffffef
+#define IRQ_BEACON_SFT 4
+#define IRQ_BEACON_HI 4
+#define IRQ_BEACON_SZ 1
+#define IRQ_PRE_BEACON_MSK 0x00000020
+#define IRQ_PRE_BEACON_I_MSK 0xffffffdf
+#define IRQ_PRE_BEACON_SFT 5
+#define IRQ_PRE_BEACON_HI 5
+#define IRQ_PRE_BEACON_SZ 1
+#define IRQ_EDCA0_TX_DONE_MSK 0x00000040
+#define IRQ_EDCA0_TX_DONE_I_MSK 0xffffffbf
+#define IRQ_EDCA0_TX_DONE_SFT 6
+#define IRQ_EDCA0_TX_DONE_HI 6
+#define IRQ_EDCA0_TX_DONE_SZ 1
+#define IRQ_EDCA1_TX_DONE_MSK 0x00000080
+#define IRQ_EDCA1_TX_DONE_I_MSK 0xffffff7f
+#define IRQ_EDCA1_TX_DONE_SFT 7
+#define IRQ_EDCA1_TX_DONE_HI 7
+#define IRQ_EDCA1_TX_DONE_SZ 1
+#define IRQ_EDCA2_TX_DONE_MSK 0x00000100
+#define IRQ_EDCA2_TX_DONE_I_MSK 0xfffffeff
+#define IRQ_EDCA2_TX_DONE_SFT 8
+#define IRQ_EDCA2_TX_DONE_HI 8
+#define IRQ_EDCA2_TX_DONE_SZ 1
+#define IRQ_EDCA3_TX_DONE_MSK 0x00000200
+#define IRQ_EDCA3_TX_DONE_I_MSK 0xfffffdff
+#define IRQ_EDCA3_TX_DONE_SFT 9
+#define IRQ_EDCA3_TX_DONE_HI 9
+#define IRQ_EDCA3_TX_DONE_SZ 1
+#define IRQ_EDCA4_TX_DONE_MSK 0x00000400
+#define IRQ_EDCA4_TX_DONE_I_MSK 0xfffffbff
+#define IRQ_EDCA4_TX_DONE_SFT 10
+#define IRQ_EDCA4_TX_DONE_HI 10
+#define IRQ_EDCA4_TX_DONE_SZ 1
+#define IRQ_BEACON_DTIM_MSK 0x00001000
+#define IRQ_BEACON_DTIM_I_MSK 0xffffefff
+#define IRQ_BEACON_DTIM_SFT 12
+#define IRQ_BEACON_DTIM_HI 12
+#define IRQ_BEACON_DTIM_SZ 1
+#define IRQ_EDCA0_LOWTHOLD_INT_MSK 0x00002000
+#define IRQ_EDCA0_LOWTHOLD_INT_I_MSK 0xffffdfff
+#define IRQ_EDCA0_LOWTHOLD_INT_SFT 13
+#define IRQ_EDCA0_LOWTHOLD_INT_HI 13
+#define IRQ_EDCA0_LOWTHOLD_INT_SZ 1
+#define IRQ_EDCA1_LOWTHOLD_INT_MSK 0x00004000
+#define IRQ_EDCA1_LOWTHOLD_INT_I_MSK 0xffffbfff
+#define IRQ_EDCA1_LOWTHOLD_INT_SFT 14
+#define IRQ_EDCA1_LOWTHOLD_INT_HI 14
+#define IRQ_EDCA1_LOWTHOLD_INT_SZ 1
+#define IRQ_EDCA2_LOWTHOLD_INT_MSK 0x00008000
+#define IRQ_EDCA2_LOWTHOLD_INT_I_MSK 0xffff7fff
+#define IRQ_EDCA2_LOWTHOLD_INT_SFT 15
+#define IRQ_EDCA2_LOWTHOLD_INT_HI 15
+#define IRQ_EDCA2_LOWTHOLD_INT_SZ 1
+#define IRQ_EDCA3_LOWTHOLD_INT_MSK 0x00010000
+#define IRQ_EDCA3_LOWTHOLD_INT_I_MSK 0xfffeffff
+#define IRQ_EDCA3_LOWTHOLD_INT_SFT 16
+#define IRQ_EDCA3_LOWTHOLD_INT_HI 16
+#define IRQ_EDCA3_LOWTHOLD_INT_SZ 1
+#define IRQ_FENCE_HIT_INT_MSK 0x00020000
+#define IRQ_FENCE_HIT_INT_I_MSK 0xfffdffff
+#define IRQ_FENCE_HIT_INT_SFT 17
+#define IRQ_FENCE_HIT_INT_HI 17
+#define IRQ_FENCE_HIT_INT_SZ 1
+#define IRQ_ILL_ADDR_INT_MSK 0x00040000
+#define IRQ_ILL_ADDR_INT_I_MSK 0xfffbffff
+#define IRQ_ILL_ADDR_INT_SFT 18
+#define IRQ_ILL_ADDR_INT_HI 18
+#define IRQ_ILL_ADDR_INT_SZ 1
+#define IRQ_MBOX_MSK 0x00080000
+#define IRQ_MBOX_I_MSK 0xfff7ffff
+#define IRQ_MBOX_SFT 19
+#define IRQ_MBOX_HI 19
+#define IRQ_MBOX_SZ 1
+#define IRQ_US_TIMER0_MSK 0x00100000
+#define IRQ_US_TIMER0_I_MSK 0xffefffff
+#define IRQ_US_TIMER0_SFT 20
+#define IRQ_US_TIMER0_HI 20
+#define IRQ_US_TIMER0_SZ 1
+#define IRQ_US_TIMER1_MSK 0x00200000
+#define IRQ_US_TIMER1_I_MSK 0xffdfffff
+#define IRQ_US_TIMER1_SFT 21
+#define IRQ_US_TIMER1_HI 21
+#define IRQ_US_TIMER1_SZ 1
+#define IRQ_US_TIMER2_MSK 0x00400000
+#define IRQ_US_TIMER2_I_MSK 0xffbfffff
+#define IRQ_US_TIMER2_SFT 22
+#define IRQ_US_TIMER2_HI 22
+#define IRQ_US_TIMER2_SZ 1
+#define IRQ_US_TIMER3_MSK 0x00800000
+#define IRQ_US_TIMER3_I_MSK 0xff7fffff
+#define IRQ_US_TIMER3_SFT 23
+#define IRQ_US_TIMER3_HI 23
+#define IRQ_US_TIMER3_SZ 1
+#define IRQ_MS_TIMER0_MSK 0x01000000
+#define IRQ_MS_TIMER0_I_MSK 0xfeffffff
+#define IRQ_MS_TIMER0_SFT 24
+#define IRQ_MS_TIMER0_HI 24
+#define IRQ_MS_TIMER0_SZ 1
+#define IRQ_MS_TIMER1_MSK 0x02000000
+#define IRQ_MS_TIMER1_I_MSK 0xfdffffff
+#define IRQ_MS_TIMER1_SFT 25
+#define IRQ_MS_TIMER1_HI 25
+#define IRQ_MS_TIMER1_SZ 1
+#define IRQ_MS_TIMER2_MSK 0x04000000
+#define IRQ_MS_TIMER2_I_MSK 0xfbffffff
+#define IRQ_MS_TIMER2_SFT 26
+#define IRQ_MS_TIMER2_HI 26
+#define IRQ_MS_TIMER2_SZ 1
+#define IRQ_MS_TIMER3_MSK 0x08000000
+#define IRQ_MS_TIMER3_I_MSK 0xf7ffffff
+#define IRQ_MS_TIMER3_SFT 27
+#define IRQ_MS_TIMER3_HI 27
+#define IRQ_MS_TIMER3_SZ 1
+#define IRQ_TX_LIMIT_INT_MSK 0x10000000
+#define IRQ_TX_LIMIT_INT_I_MSK 0xefffffff
+#define IRQ_TX_LIMIT_INT_SFT 28
+#define IRQ_TX_LIMIT_INT_HI 28
+#define IRQ_TX_LIMIT_INT_SZ 1
+#define IRQ_DMA0_MSK 0x20000000
+#define IRQ_DMA0_I_MSK 0xdfffffff
+#define IRQ_DMA0_SFT 29
+#define IRQ_DMA0_HI 29
+#define IRQ_DMA0_SZ 1
+#define IRQ_CO_DMA_MSK 0x40000000
+#define IRQ_CO_DMA_I_MSK 0xbfffffff
+#define IRQ_CO_DMA_SFT 30
+#define IRQ_CO_DMA_HI 30
+#define IRQ_CO_DMA_SZ 1
+#define IRQ_PERI_GROUP_MSK 0x80000000
+#define IRQ_PERI_GROUP_I_MSK 0x7fffffff
+#define IRQ_PERI_GROUP_SFT 31
+#define IRQ_PERI_GROUP_HI 31
+#define IRQ_PERI_GROUP_SZ 1
+#define FIQ_STATUS_MSK 0xffffffff
+#define FIQ_STATUS_I_MSK 0x00000000
+#define FIQ_STATUS_SFT 0
+#define FIQ_STATUS_HI 31
+#define FIQ_STATUS_SZ 32
+#define IRQ_RAW_MSK 0xffffffff
+#define IRQ_RAW_I_MSK 0x00000000
+#define IRQ_RAW_SFT 0
+#define IRQ_RAW_HI 31
+#define IRQ_RAW_SZ 32
+#define FIQ_RAW_MSK 0xffffffff
+#define FIQ_RAW_I_MSK 0x00000000
+#define FIQ_RAW_SFT 0
+#define FIQ_RAW_HI 31
+#define FIQ_RAW_SZ 32
+#define INT_PERI_MASK_MSK 0xffffffff
+#define INT_PERI_MASK_I_MSK 0x00000000
+#define INT_PERI_MASK_SFT 0
+#define INT_PERI_MASK_HI 31
+#define INT_PERI_MASK_SZ 32
+#define PERI_RTC_MSK 0x00000001
+#define PERI_RTC_I_MSK 0xfffffffe
+#define PERI_RTC_SFT 0
+#define PERI_RTC_HI 0
+#define PERI_RTC_SZ 1
+#define IRQ_UART0_TX_MSK 0x00000002
+#define IRQ_UART0_TX_I_MSK 0xfffffffd
+#define IRQ_UART0_TX_SFT 1
+#define IRQ_UART0_TX_HI 1
+#define IRQ_UART0_TX_SZ 1
+#define IRQ_UART0_RX_MSK 0x00000004
+#define IRQ_UART0_RX_I_MSK 0xfffffffb
+#define IRQ_UART0_RX_SFT 2
+#define IRQ_UART0_RX_HI 2
+#define IRQ_UART0_RX_SZ 1
+#define PERI_GPI_2_MSK 0x00000008
+#define PERI_GPI_2_I_MSK 0xfffffff7
+#define PERI_GPI_2_SFT 3
+#define PERI_GPI_2_HI 3
+#define PERI_GPI_2_SZ 1
+#define IRQ_SPI_IPC_MSK 0x00000010
+#define IRQ_SPI_IPC_I_MSK 0xffffffef
+#define IRQ_SPI_IPC_SFT 4
+#define IRQ_SPI_IPC_HI 4
+#define IRQ_SPI_IPC_SZ 1
+#define PERI_GPI_1_0_MSK 0x00000060
+#define PERI_GPI_1_0_I_MSK 0xffffff9f
+#define PERI_GPI_1_0_SFT 5
+#define PERI_GPI_1_0_HI 6
+#define PERI_GPI_1_0_SZ 2
+#define SCRT_INT_1_MSK 0x00000080
+#define SCRT_INT_1_I_MSK 0xffffff7f
+#define SCRT_INT_1_SFT 7
+#define SCRT_INT_1_HI 7
+#define SCRT_INT_1_SZ 1
+#define MMU_ALC_ERR_MSK 0x00000100
+#define MMU_ALC_ERR_I_MSK 0xfffffeff
+#define MMU_ALC_ERR_SFT 8
+#define MMU_ALC_ERR_HI 8
+#define MMU_ALC_ERR_SZ 1
+#define MMU_RLS_ERR_MSK 0x00000200
+#define MMU_RLS_ERR_I_MSK 0xfffffdff
+#define MMU_RLS_ERR_SFT 9
+#define MMU_RLS_ERR_HI 9
+#define MMU_RLS_ERR_SZ 1
+#define ID_MNG_INT_1_MSK 0x00000400
+#define ID_MNG_INT_1_I_MSK 0xfffffbff
+#define ID_MNG_INT_1_SFT 10
+#define ID_MNG_INT_1_HI 10
+#define ID_MNG_INT_1_SZ 1
+#define MBOX_INT_1_MSK 0x00000800
+#define MBOX_INT_1_I_MSK 0xfffff7ff
+#define MBOX_INT_1_SFT 11
+#define MBOX_INT_1_HI 11
+#define MBOX_INT_1_SZ 1
+#define MBOX_INT_2_MSK 0x00001000
+#define MBOX_INT_2_I_MSK 0xffffefff
+#define MBOX_INT_2_SFT 12
+#define MBOX_INT_2_HI 12
+#define MBOX_INT_2_SZ 1
+#define MBOX_INT_3_MSK 0x00002000
+#define MBOX_INT_3_I_MSK 0xffffdfff
+#define MBOX_INT_3_SFT 13
+#define MBOX_INT_3_HI 13
+#define MBOX_INT_3_SZ 1
+#define HCI_INT_1_MSK 0x00004000
+#define HCI_INT_1_I_MSK 0xffffbfff
+#define HCI_INT_1_SFT 14
+#define HCI_INT_1_HI 14
+#define HCI_INT_1_SZ 1
+#define UART_RX_TIMEOUT_MSK 0x00008000
+#define UART_RX_TIMEOUT_I_MSK 0xffff7fff
+#define UART_RX_TIMEOUT_SFT 15
+#define UART_RX_TIMEOUT_HI 15
+#define UART_RX_TIMEOUT_SZ 1
+#define UART_MULTI_IRQ_MSK 0x00010000
+#define UART_MULTI_IRQ_I_MSK 0xfffeffff
+#define UART_MULTI_IRQ_SFT 16
+#define UART_MULTI_IRQ_HI 16
+#define UART_MULTI_IRQ_SZ 1
+#define ID_MNG_INT_2_MSK 0x00020000
+#define ID_MNG_INT_2_I_MSK 0xfffdffff
+#define ID_MNG_INT_2_SFT 17
+#define ID_MNG_INT_2_HI 17
+#define ID_MNG_INT_2_SZ 1
+#define DMN_NOHIT_INT_MSK 0x00040000
+#define DMN_NOHIT_INT_I_MSK 0xfffbffff
+#define DMN_NOHIT_INT_SFT 18
+#define DMN_NOHIT_INT_HI 18
+#define DMN_NOHIT_INT_SZ 1
+#define ID_THOLD_RX_MSK 0x00080000
+#define ID_THOLD_RX_I_MSK 0xfff7ffff
+#define ID_THOLD_RX_SFT 19
+#define ID_THOLD_RX_HI 19
+#define ID_THOLD_RX_SZ 1
+#define ID_THOLD_TX_MSK 0x00100000
+#define ID_THOLD_TX_I_MSK 0xffefffff
+#define ID_THOLD_TX_SFT 20
+#define ID_THOLD_TX_HI 20
+#define ID_THOLD_TX_SZ 1
+#define ID_DOUBLE_RLS_MSK 0x00200000
+#define ID_DOUBLE_RLS_I_MSK 0xffdfffff
+#define ID_DOUBLE_RLS_SFT 21
+#define ID_DOUBLE_RLS_HI 21
+#define ID_DOUBLE_RLS_SZ 1
+#define RX_ID_LEN_THOLD_MSK 0x00400000
+#define RX_ID_LEN_THOLD_I_MSK 0xffbfffff
+#define RX_ID_LEN_THOLD_SFT 22
+#define RX_ID_LEN_THOLD_HI 22
+#define RX_ID_LEN_THOLD_SZ 1
+#define TX_ID_LEN_THOLD_MSK 0x00800000
+#define TX_ID_LEN_THOLD_I_MSK 0xff7fffff
+#define TX_ID_LEN_THOLD_SFT 23
+#define TX_ID_LEN_THOLD_HI 23
+#define TX_ID_LEN_THOLD_SZ 1
+#define ALL_ID_LEN_THOLD_MSK 0x01000000
+#define ALL_ID_LEN_THOLD_I_MSK 0xfeffffff
+#define ALL_ID_LEN_THOLD_SFT 24
+#define ALL_ID_LEN_THOLD_HI 24
+#define ALL_ID_LEN_THOLD_SZ 1
+#define DMN_MCU_INT_MSK 0x02000000
+#define DMN_MCU_INT_I_MSK 0xfdffffff
+#define DMN_MCU_INT_SFT 25
+#define DMN_MCU_INT_HI 25
+#define DMN_MCU_INT_SZ 1
+#define IRQ_DAT_UART_TX_MSK 0x04000000
+#define IRQ_DAT_UART_TX_I_MSK 0xfbffffff
+#define IRQ_DAT_UART_TX_SFT 26
+#define IRQ_DAT_UART_TX_HI 26
+#define IRQ_DAT_UART_TX_SZ 1
+#define IRQ_DAT_UART_RX_MSK 0x08000000
+#define IRQ_DAT_UART_RX_I_MSK 0xf7ffffff
+#define IRQ_DAT_UART_RX_SFT 27
+#define IRQ_DAT_UART_RX_HI 27
+#define IRQ_DAT_UART_RX_SZ 1
+#define DAT_UART_RX_TIMEOUT_MSK 0x10000000
+#define DAT_UART_RX_TIMEOUT_I_MSK 0xefffffff
+#define DAT_UART_RX_TIMEOUT_SFT 28
+#define DAT_UART_RX_TIMEOUT_HI 28
+#define DAT_UART_RX_TIMEOUT_SZ 1
+#define DAT_UART_MULTI_IRQ_MSK 0x20000000
+#define DAT_UART_MULTI_IRQ_I_MSK 0xdfffffff
+#define DAT_UART_MULTI_IRQ_SFT 29
+#define DAT_UART_MULTI_IRQ_HI 29
+#define DAT_UART_MULTI_IRQ_SZ 1
+#define ALR_ABT_NOCHG_INT_IRQ_MSK 0x40000000
+#define ALR_ABT_NOCHG_INT_IRQ_I_MSK 0xbfffffff
+#define ALR_ABT_NOCHG_INT_IRQ_SFT 30
+#define ALR_ABT_NOCHG_INT_IRQ_HI 30
+#define ALR_ABT_NOCHG_INT_IRQ_SZ 1
+#define TBLNEQ_MNGPKT_INT_IRQ_MSK 0x80000000
+#define TBLNEQ_MNGPKT_INT_IRQ_I_MSK 0x7fffffff
+#define TBLNEQ_MNGPKT_INT_IRQ_SFT 31
+#define TBLNEQ_MNGPKT_INT_IRQ_HI 31
+#define TBLNEQ_MNGPKT_INT_IRQ_SZ 1
+#define INTR_PERI_RAW_MSK 0xffffffff
+#define INTR_PERI_RAW_I_MSK 0x00000000
+#define INTR_PERI_RAW_SFT 0
+#define INTR_PERI_RAW_HI 31
+#define INTR_PERI_RAW_SZ 32
+#define INTR_GPI00_CFG_MSK 0x00000003
+#define INTR_GPI00_CFG_I_MSK 0xfffffffc
+#define INTR_GPI00_CFG_SFT 0
+#define INTR_GPI00_CFG_HI 1
+#define INTR_GPI00_CFG_SZ 2
+#define INTR_GPI01_CFG_MSK 0x0000000c
+#define INTR_GPI01_CFG_I_MSK 0xfffffff3
+#define INTR_GPI01_CFG_SFT 2
+#define INTR_GPI01_CFG_HI 3
+#define INTR_GPI01_CFG_SZ 2
+#define SYS_RST_INT_MSK 0x00000001
+#define SYS_RST_INT_I_MSK 0xfffffffe
+#define SYS_RST_INT_SFT 0
+#define SYS_RST_INT_HI 0
+#define SYS_RST_INT_SZ 1
+#define SPI_IPC_ADDR_MSK 0xffffffff
+#define SPI_IPC_ADDR_I_MSK 0x00000000
+#define SPI_IPC_ADDR_SFT 0
+#define SPI_IPC_ADDR_HI 31
+#define SPI_IPC_ADDR_SZ 32
+#define SD_MASK_TOP_MSK 0xffffffff
+#define SD_MASK_TOP_I_MSK 0x00000000
+#define SD_MASK_TOP_SFT 0
+#define SD_MASK_TOP_HI 31
+#define SD_MASK_TOP_SZ 32
+#define IRQ_PHY_0_SD_MSK 0x00000001
+#define IRQ_PHY_0_SD_I_MSK 0xfffffffe
+#define IRQ_PHY_0_SD_SFT 0
+#define IRQ_PHY_0_SD_HI 0
+#define IRQ_PHY_0_SD_SZ 1
+#define IRQ_PHY_1_SD_MSK 0x00000002
+#define IRQ_PHY_1_SD_I_MSK 0xfffffffd
+#define IRQ_PHY_1_SD_SFT 1
+#define IRQ_PHY_1_SD_HI 1
+#define IRQ_PHY_1_SD_SZ 1
+#define IRQ_SDIO_SD_MSK 0x00000004
+#define IRQ_SDIO_SD_I_MSK 0xfffffffb
+#define IRQ_SDIO_SD_SFT 2
+#define IRQ_SDIO_SD_HI 2
+#define IRQ_SDIO_SD_SZ 1
+#define IRQ_BEACON_DONE_SD_MSK 0x00000008
+#define IRQ_BEACON_DONE_SD_I_MSK 0xfffffff7
+#define IRQ_BEACON_DONE_SD_SFT 3
+#define IRQ_BEACON_DONE_SD_HI 3
+#define IRQ_BEACON_DONE_SD_SZ 1
+#define IRQ_BEACON_SD_MSK 0x00000010
+#define IRQ_BEACON_SD_I_MSK 0xffffffef
+#define IRQ_BEACON_SD_SFT 4
+#define IRQ_BEACON_SD_HI 4
+#define IRQ_BEACON_SD_SZ 1
+#define IRQ_PRE_BEACON_SD_MSK 0x00000020
+#define IRQ_PRE_BEACON_SD_I_MSK 0xffffffdf
+#define IRQ_PRE_BEACON_SD_SFT 5
+#define IRQ_PRE_BEACON_SD_HI 5
+#define IRQ_PRE_BEACON_SD_SZ 1
+#define IRQ_EDCA0_TX_DONE_SD_MSK 0x00000040
+#define IRQ_EDCA0_TX_DONE_SD_I_MSK 0xffffffbf
+#define IRQ_EDCA0_TX_DONE_SD_SFT 6
+#define IRQ_EDCA0_TX_DONE_SD_HI 6
+#define IRQ_EDCA0_TX_DONE_SD_SZ 1
+#define IRQ_EDCA1_TX_DONE_SD_MSK 0x00000080
+#define IRQ_EDCA1_TX_DONE_SD_I_MSK 0xffffff7f
+#define IRQ_EDCA1_TX_DONE_SD_SFT 7
+#define IRQ_EDCA1_TX_DONE_SD_HI 7
+#define IRQ_EDCA1_TX_DONE_SD_SZ 1
+#define IRQ_EDCA2_TX_DONE_SD_MSK 0x00000100
+#define IRQ_EDCA2_TX_DONE_SD_I_MSK 0xfffffeff
+#define IRQ_EDCA2_TX_DONE_SD_SFT 8
+#define IRQ_EDCA2_TX_DONE_SD_HI 8
+#define IRQ_EDCA2_TX_DONE_SD_SZ 1
+#define IRQ_EDCA3_TX_DONE_SD_MSK 0x00000200
+#define IRQ_EDCA3_TX_DONE_SD_I_MSK 0xfffffdff
+#define IRQ_EDCA3_TX_DONE_SD_SFT 9
+#define IRQ_EDCA3_TX_DONE_SD_HI 9
+#define IRQ_EDCA3_TX_DONE_SD_SZ 1
+#define IRQ_EDCA4_TX_DONE_SD_MSK 0x00000400
+#define IRQ_EDCA4_TX_DONE_SD_I_MSK 0xfffffbff
+#define IRQ_EDCA4_TX_DONE_SD_SFT 10
+#define IRQ_EDCA4_TX_DONE_SD_HI 10
+#define IRQ_EDCA4_TX_DONE_SD_SZ 1
+#define IRQ_BEACON_DTIM_SD_MSK 0x00001000
+#define IRQ_BEACON_DTIM_SD_I_MSK 0xffffefff
+#define IRQ_BEACON_DTIM_SD_SFT 12
+#define IRQ_BEACON_DTIM_SD_HI 12
+#define IRQ_BEACON_DTIM_SD_SZ 1
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_MSK 0x00002000
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_I_MSK 0xffffdfff
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_SFT 13
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_HI 13
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_MSK 0x00004000
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_I_MSK 0xffffbfff
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_SFT 14
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_HI 14
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_MSK 0x00008000
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_I_MSK 0xffff7fff
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_SFT 15
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_HI 15
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_MSK 0x00010000
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_I_MSK 0xfffeffff
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_SFT 16
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_HI 16
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_FENCE_HIT_INT_SD_MSK 0x00020000
+#define IRQ_FENCE_HIT_INT_SD_I_MSK 0xfffdffff
+#define IRQ_FENCE_HIT_INT_SD_SFT 17
+#define IRQ_FENCE_HIT_INT_SD_HI 17
+#define IRQ_FENCE_HIT_INT_SD_SZ 1
+#define IRQ_ILL_ADDR_INT_SD_MSK 0x00040000
+#define IRQ_ILL_ADDR_INT_SD_I_MSK 0xfffbffff
+#define IRQ_ILL_ADDR_INT_SD_SFT 18
+#define IRQ_ILL_ADDR_INT_SD_HI 18
+#define IRQ_ILL_ADDR_INT_SD_SZ 1
+#define IRQ_MBOX_SD_MSK 0x00080000
+#define IRQ_MBOX_SD_I_MSK 0xfff7ffff
+#define IRQ_MBOX_SD_SFT 19
+#define IRQ_MBOX_SD_HI 19
+#define IRQ_MBOX_SD_SZ 1
+#define IRQ_US_TIMER0_SD_MSK 0x00100000
+#define IRQ_US_TIMER0_SD_I_MSK 0xffefffff
+#define IRQ_US_TIMER0_SD_SFT 20
+#define IRQ_US_TIMER0_SD_HI 20
+#define IRQ_US_TIMER0_SD_SZ 1
+#define IRQ_US_TIMER1_SD_MSK 0x00200000
+#define IRQ_US_TIMER1_SD_I_MSK 0xffdfffff
+#define IRQ_US_TIMER1_SD_SFT 21
+#define IRQ_US_TIMER1_SD_HI 21
+#define IRQ_US_TIMER1_SD_SZ 1
+#define IRQ_US_TIMER2_SD_MSK 0x00400000
+#define IRQ_US_TIMER2_SD_I_MSK 0xffbfffff
+#define IRQ_US_TIMER2_SD_SFT 22
+#define IRQ_US_TIMER2_SD_HI 22
+#define IRQ_US_TIMER2_SD_SZ 1
+#define IRQ_US_TIMER3_SD_MSK 0x00800000
+#define IRQ_US_TIMER3_SD_I_MSK 0xff7fffff
+#define IRQ_US_TIMER3_SD_SFT 23
+#define IRQ_US_TIMER3_SD_HI 23
+#define IRQ_US_TIMER3_SD_SZ 1
+#define IRQ_MS_TIMER0_SD_MSK 0x01000000
+#define IRQ_MS_TIMER0_SD_I_MSK 0xfeffffff
+#define IRQ_MS_TIMER0_SD_SFT 24
+#define IRQ_MS_TIMER0_SD_HI 24
+#define IRQ_MS_TIMER0_SD_SZ 1
+#define IRQ_MS_TIMER1_SD_MSK 0x02000000
+#define IRQ_MS_TIMER1_SD_I_MSK 0xfdffffff
+#define IRQ_MS_TIMER1_SD_SFT 25
+#define IRQ_MS_TIMER1_SD_HI 25
+#define IRQ_MS_TIMER1_SD_SZ 1
+#define IRQ_MS_TIMER2_SD_MSK 0x04000000
+#define IRQ_MS_TIMER2_SD_I_MSK 0xfbffffff
+#define IRQ_MS_TIMER2_SD_SFT 26
+#define IRQ_MS_TIMER2_SD_HI 26
+#define IRQ_MS_TIMER2_SD_SZ 1
+#define IRQ_MS_TIMER3_SD_MSK 0x08000000
+#define IRQ_MS_TIMER3_SD_I_MSK 0xf7ffffff
+#define IRQ_MS_TIMER3_SD_SFT 27
+#define IRQ_MS_TIMER3_SD_HI 27
+#define IRQ_MS_TIMER3_SD_SZ 1
+#define IRQ_TX_LIMIT_INT_SD_MSK 0x10000000
+#define IRQ_TX_LIMIT_INT_SD_I_MSK 0xefffffff
+#define IRQ_TX_LIMIT_INT_SD_SFT 28
+#define IRQ_TX_LIMIT_INT_SD_HI 28
+#define IRQ_TX_LIMIT_INT_SD_SZ 1
+#define IRQ_DMA0_SD_MSK 0x20000000
+#define IRQ_DMA0_SD_I_MSK 0xdfffffff
+#define IRQ_DMA0_SD_SFT 29
+#define IRQ_DMA0_SD_HI 29
+#define IRQ_DMA0_SD_SZ 1
+#define IRQ_CO_DMA_SD_MSK 0x40000000
+#define IRQ_CO_DMA_SD_I_MSK 0xbfffffff
+#define IRQ_CO_DMA_SD_SFT 30
+#define IRQ_CO_DMA_SD_HI 30
+#define IRQ_CO_DMA_SD_SZ 1
+#define IRQ_PERI_GROUP_SD_MSK 0x80000000
+#define IRQ_PERI_GROUP_SD_I_MSK 0x7fffffff
+#define IRQ_PERI_GROUP_SD_SFT 31
+#define IRQ_PERI_GROUP_SD_HI 31
+#define IRQ_PERI_GROUP_SD_SZ 1
+#define INT_PERI_MASK_SD_MSK 0xffffffff
+#define INT_PERI_MASK_SD_I_MSK 0x00000000
+#define INT_PERI_MASK_SD_SFT 0
+#define INT_PERI_MASK_SD_HI 31
+#define INT_PERI_MASK_SD_SZ 32
+#define PERI_RTC_SD_MSK 0x00000001
+#define PERI_RTC_SD_I_MSK 0xfffffffe
+#define PERI_RTC_SD_SFT 0
+#define PERI_RTC_SD_HI 0
+#define PERI_RTC_SD_SZ 1
+#define IRQ_UART0_TX_SD_MSK 0x00000002
+#define IRQ_UART0_TX_SD_I_MSK 0xfffffffd
+#define IRQ_UART0_TX_SD_SFT 1
+#define IRQ_UART0_TX_SD_HI 1
+#define IRQ_UART0_TX_SD_SZ 1
+#define IRQ_UART0_RX_SD_MSK 0x00000004
+#define IRQ_UART0_RX_SD_I_MSK 0xfffffffb
+#define IRQ_UART0_RX_SD_SFT 2
+#define IRQ_UART0_RX_SD_HI 2
+#define IRQ_UART0_RX_SD_SZ 1
+#define PERI_GPI_SD_2_MSK 0x00000008
+#define PERI_GPI_SD_2_I_MSK 0xfffffff7
+#define PERI_GPI_SD_2_SFT 3
+#define PERI_GPI_SD_2_HI 3
+#define PERI_GPI_SD_2_SZ 1
+#define IRQ_SPI_IPC_SD_MSK 0x00000010
+#define IRQ_SPI_IPC_SD_I_MSK 0xffffffef
+#define IRQ_SPI_IPC_SD_SFT 4
+#define IRQ_SPI_IPC_SD_HI 4
+#define IRQ_SPI_IPC_SD_SZ 1
+#define PERI_GPI_SD_1_0_MSK 0x00000060
+#define PERI_GPI_SD_1_0_I_MSK 0xffffff9f
+#define PERI_GPI_SD_1_0_SFT 5
+#define PERI_GPI_SD_1_0_HI 6
+#define PERI_GPI_SD_1_0_SZ 2
+#define SCRT_INT_1_SD_MSK 0x00000080
+#define SCRT_INT_1_SD_I_MSK 0xffffff7f
+#define SCRT_INT_1_SD_SFT 7
+#define SCRT_INT_1_SD_HI 7
+#define SCRT_INT_1_SD_SZ 1
+#define MMU_ALC_ERR_SD_MSK 0x00000100
+#define MMU_ALC_ERR_SD_I_MSK 0xfffffeff
+#define MMU_ALC_ERR_SD_SFT 8
+#define MMU_ALC_ERR_SD_HI 8
+#define MMU_ALC_ERR_SD_SZ 1
+#define MMU_RLS_ERR_SD_MSK 0x00000200
+#define MMU_RLS_ERR_SD_I_MSK 0xfffffdff
+#define MMU_RLS_ERR_SD_SFT 9
+#define MMU_RLS_ERR_SD_HI 9
+#define MMU_RLS_ERR_SD_SZ 1
+#define ID_MNG_INT_1_SD_MSK 0x00000400
+#define ID_MNG_INT_1_SD_I_MSK 0xfffffbff
+#define ID_MNG_INT_1_SD_SFT 10
+#define ID_MNG_INT_1_SD_HI 10
+#define ID_MNG_INT_1_SD_SZ 1
+#define MBOX_INT_1_SD_MSK 0x00000800
+#define MBOX_INT_1_SD_I_MSK 0xfffff7ff
+#define MBOX_INT_1_SD_SFT 11
+#define MBOX_INT_1_SD_HI 11
+#define MBOX_INT_1_SD_SZ 1
+#define MBOX_INT_2_SD_MSK 0x00001000
+#define MBOX_INT_2_SD_I_MSK 0xffffefff
+#define MBOX_INT_2_SD_SFT 12
+#define MBOX_INT_2_SD_HI 12
+#define MBOX_INT_2_SD_SZ 1
+#define MBOX_INT_3_SD_MSK 0x00002000
+#define MBOX_INT_3_SD_I_MSK 0xffffdfff
+#define MBOX_INT_3_SD_SFT 13
+#define MBOX_INT_3_SD_HI 13
+#define MBOX_INT_3_SD_SZ 1
+#define HCI_INT_1_SD_MSK 0x00004000
+#define HCI_INT_1_SD_I_MSK 0xffffbfff
+#define HCI_INT_1_SD_SFT 14
+#define HCI_INT_1_SD_HI 14
+#define HCI_INT_1_SD_SZ 1
+#define UART_RX_TIMEOUT_SD_MSK 0x00008000
+#define UART_RX_TIMEOUT_SD_I_MSK 0xffff7fff
+#define UART_RX_TIMEOUT_SD_SFT 15
+#define UART_RX_TIMEOUT_SD_HI 15
+#define UART_RX_TIMEOUT_SD_SZ 1
+#define UART_MULTI_IRQ_SD_MSK 0x00010000
+#define UART_MULTI_IRQ_SD_I_MSK 0xfffeffff
+#define UART_MULTI_IRQ_SD_SFT 16
+#define UART_MULTI_IRQ_SD_HI 16
+#define UART_MULTI_IRQ_SD_SZ 1
+#define ID_MNG_INT_2_SD_MSK 0x00020000
+#define ID_MNG_INT_2_SD_I_MSK 0xfffdffff
+#define ID_MNG_INT_2_SD_SFT 17
+#define ID_MNG_INT_2_SD_HI 17
+#define ID_MNG_INT_2_SD_SZ 1
+#define DMN_NOHIT_INT_SD_MSK 0x00040000
+#define DMN_NOHIT_INT_SD_I_MSK 0xfffbffff
+#define DMN_NOHIT_INT_SD_SFT 18
+#define DMN_NOHIT_INT_SD_HI 18
+#define DMN_NOHIT_INT_SD_SZ 1
+#define ID_THOLD_RX_SD_MSK 0x00080000
+#define ID_THOLD_RX_SD_I_MSK 0xfff7ffff
+#define ID_THOLD_RX_SD_SFT 19
+#define ID_THOLD_RX_SD_HI 19
+#define ID_THOLD_RX_SD_SZ 1
+#define ID_THOLD_TX_SD_MSK 0x00100000
+#define ID_THOLD_TX_SD_I_MSK 0xffefffff
+#define ID_THOLD_TX_SD_SFT 20
+#define ID_THOLD_TX_SD_HI 20
+#define ID_THOLD_TX_SD_SZ 1
+#define ID_DOUBLE_RLS_SD_MSK 0x00200000
+#define ID_DOUBLE_RLS_SD_I_MSK 0xffdfffff
+#define ID_DOUBLE_RLS_SD_SFT 21
+#define ID_DOUBLE_RLS_SD_HI 21
+#define ID_DOUBLE_RLS_SD_SZ 1
+#define RX_ID_LEN_THOLD_SD_MSK 0x00400000
+#define RX_ID_LEN_THOLD_SD_I_MSK 0xffbfffff
+#define RX_ID_LEN_THOLD_SD_SFT 22
+#define RX_ID_LEN_THOLD_SD_HI 22
+#define RX_ID_LEN_THOLD_SD_SZ 1
+#define TX_ID_LEN_THOLD_SD_MSK 0x00800000
+#define TX_ID_LEN_THOLD_SD_I_MSK 0xff7fffff
+#define TX_ID_LEN_THOLD_SD_SFT 23
+#define TX_ID_LEN_THOLD_SD_HI 23
+#define TX_ID_LEN_THOLD_SD_SZ 1
+#define ALL_ID_LEN_THOLD_SD_MSK 0x01000000
+#define ALL_ID_LEN_THOLD_SD_I_MSK 0xfeffffff
+#define ALL_ID_LEN_THOLD_SD_SFT 24
+#define ALL_ID_LEN_THOLD_SD_HI 24
+#define ALL_ID_LEN_THOLD_SD_SZ 1
+#define DMN_MCU_INT_SD_MSK 0x02000000
+#define DMN_MCU_INT_SD_I_MSK 0xfdffffff
+#define DMN_MCU_INT_SD_SFT 25
+#define DMN_MCU_INT_SD_HI 25
+#define DMN_MCU_INT_SD_SZ 1
+#define IRQ_DAT_UART_TX_SD_MSK 0x04000000
+#define IRQ_DAT_UART_TX_SD_I_MSK 0xfbffffff
+#define IRQ_DAT_UART_TX_SD_SFT 26
+#define IRQ_DAT_UART_TX_SD_HI 26
+#define IRQ_DAT_UART_TX_SD_SZ 1
+#define IRQ_DAT_UART_RX_SD_MSK 0x08000000
+#define IRQ_DAT_UART_RX_SD_I_MSK 0xf7ffffff
+#define IRQ_DAT_UART_RX_SD_SFT 27
+#define IRQ_DAT_UART_RX_SD_HI 27
+#define IRQ_DAT_UART_RX_SD_SZ 1
+#define DAT_UART_RX_TIMEOUT_SD_MSK 0x10000000
+#define DAT_UART_RX_TIMEOUT_SD_I_MSK 0xefffffff
+#define DAT_UART_RX_TIMEOUT_SD_SFT 28
+#define DAT_UART_RX_TIMEOUT_SD_HI 28
+#define DAT_UART_RX_TIMEOUT_SD_SZ 1
+#define DAT_UART_MULTI_IRQ_SD_MSK 0x20000000
+#define DAT_UART_MULTI_IRQ_SD_I_MSK 0xdfffffff
+#define DAT_UART_MULTI_IRQ_SD_SFT 29
+#define DAT_UART_MULTI_IRQ_SD_HI 29
+#define DAT_UART_MULTI_IRQ_SD_SZ 1
+#define ALR_ABT_NOCHG_INT_IRQ_SD_MSK 0x40000000
+#define ALR_ABT_NOCHG_INT_IRQ_SD_I_MSK 0xbfffffff
+#define ALR_ABT_NOCHG_INT_IRQ_SD_SFT 30
+#define ALR_ABT_NOCHG_INT_IRQ_SD_HI 30
+#define ALR_ABT_NOCHG_INT_IRQ_SD_SZ 1
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_MSK 0x80000000
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_I_MSK 0x7fffffff
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_SFT 31
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_HI 31
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_SZ 1
+#define DBG_SPI_MODE_MSK 0xffffffff
+#define DBG_SPI_MODE_I_MSK 0x00000000
+#define DBG_SPI_MODE_SFT 0
+#define DBG_SPI_MODE_HI 31
+#define DBG_SPI_MODE_SZ 32
+#define DBG_RX_QUOTA_MSK 0x0000ffff
+#define DBG_RX_QUOTA_I_MSK 0xffff0000
+#define DBG_RX_QUOTA_SFT 0
+#define DBG_RX_QUOTA_HI 15
+#define DBG_RX_QUOTA_SZ 16
+#define DBG_CONDI_NUM_MSK 0x000000ff
+#define DBG_CONDI_NUM_I_MSK 0xffffff00
+#define DBG_CONDI_NUM_SFT 0
+#define DBG_CONDI_NUM_HI 7
+#define DBG_CONDI_NUM_SZ 8
+#define DBG_HOST_PATH_MSK 0x00000001
+#define DBG_HOST_PATH_I_MSK 0xfffffffe
+#define DBG_HOST_PATH_SFT 0
+#define DBG_HOST_PATH_HI 0
+#define DBG_HOST_PATH_SZ 1
+#define DBG_TX_SEG_MSK 0xffffffff
+#define DBG_TX_SEG_I_MSK 0x00000000
+#define DBG_TX_SEG_SFT 0
+#define DBG_TX_SEG_HI 31
+#define DBG_TX_SEG_SZ 32
+#define DBG_BRST_MODE_MSK 0x00000001
+#define DBG_BRST_MODE_I_MSK 0xfffffffe
+#define DBG_BRST_MODE_SFT 0
+#define DBG_BRST_MODE_HI 0
+#define DBG_BRST_MODE_SZ 1
+#define DBG_CLK_WIDTH_MSK 0x0000ffff
+#define DBG_CLK_WIDTH_I_MSK 0xffff0000
+#define DBG_CLK_WIDTH_SFT 0
+#define DBG_CLK_WIDTH_HI 15
+#define DBG_CLK_WIDTH_SZ 16
+#define DBG_CSN_INTER_MSK 0xffff0000
+#define DBG_CSN_INTER_I_MSK 0x0000ffff
+#define DBG_CSN_INTER_SFT 16
+#define DBG_CSN_INTER_HI 31
+#define DBG_CSN_INTER_SZ 16
+#define DBG_BACK_DLY_MSK 0x0000ffff
+#define DBG_BACK_DLY_I_MSK 0xffff0000
+#define DBG_BACK_DLY_SFT 0
+#define DBG_BACK_DLY_HI 15
+#define DBG_BACK_DLY_SZ 16
+#define DBG_FRONT_DLY_MSK 0xffff0000
+#define DBG_FRONT_DLY_I_MSK 0x0000ffff
+#define DBG_FRONT_DLY_SFT 16
+#define DBG_FRONT_DLY_HI 31
+#define DBG_FRONT_DLY_SZ 16
+#define DBG_RX_FIFO_FAIL_MSK 0x00000002
+#define DBG_RX_FIFO_FAIL_I_MSK 0xfffffffd
+#define DBG_RX_FIFO_FAIL_SFT 1
+#define DBG_RX_FIFO_FAIL_HI 1
+#define DBG_RX_FIFO_FAIL_SZ 1
+#define DBG_RX_HOST_FAIL_MSK 0x00000004
+#define DBG_RX_HOST_FAIL_I_MSK 0xfffffffb
+#define DBG_RX_HOST_FAIL_SFT 2
+#define DBG_RX_HOST_FAIL_HI 2
+#define DBG_RX_HOST_FAIL_SZ 1
+#define DBG_TX_FIFO_FAIL_MSK 0x00000008
+#define DBG_TX_FIFO_FAIL_I_MSK 0xfffffff7
+#define DBG_TX_FIFO_FAIL_SFT 3
+#define DBG_TX_FIFO_FAIL_HI 3
+#define DBG_TX_FIFO_FAIL_SZ 1
+#define DBG_TX_HOST_FAIL_MSK 0x00000010
+#define DBG_TX_HOST_FAIL_I_MSK 0xffffffef
+#define DBG_TX_HOST_FAIL_SFT 4
+#define DBG_TX_HOST_FAIL_HI 4
+#define DBG_TX_HOST_FAIL_SZ 1
+#define DBG_SPI_DOUBLE_ALLOC_MSK 0x00000020
+#define DBG_SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
+#define DBG_SPI_DOUBLE_ALLOC_SFT 5
+#define DBG_SPI_DOUBLE_ALLOC_HI 5
+#define DBG_SPI_DOUBLE_ALLOC_SZ 1
+#define DBG_SPI_TX_NO_ALLOC_MSK 0x00000040
+#define DBG_SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
+#define DBG_SPI_TX_NO_ALLOC_SFT 6
+#define DBG_SPI_TX_NO_ALLOC_HI 6
+#define DBG_SPI_TX_NO_ALLOC_SZ 1
+#define DBG_RDATA_RDY_MSK 0x00000080
+#define DBG_RDATA_RDY_I_MSK 0xffffff7f
+#define DBG_RDATA_RDY_SFT 7
+#define DBG_RDATA_RDY_HI 7
+#define DBG_RDATA_RDY_SZ 1
+#define DBG_SPI_ALLOC_STATUS_MSK 0x00000100
+#define DBG_SPI_ALLOC_STATUS_I_MSK 0xfffffeff
+#define DBG_SPI_ALLOC_STATUS_SFT 8
+#define DBG_SPI_ALLOC_STATUS_HI 8
+#define DBG_SPI_ALLOC_STATUS_SZ 1
+#define DBG_SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
+#define DBG_SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
+#define DBG_SPI_DBG_WR_FIFO_FULL_SFT 9
+#define DBG_SPI_DBG_WR_FIFO_FULL_HI 9
+#define DBG_SPI_DBG_WR_FIFO_FULL_SZ 1
+#define DBG_RX_LEN_MSK 0xffff0000
+#define DBG_RX_LEN_I_MSK 0x0000ffff
+#define DBG_RX_LEN_SFT 16
+#define DBG_RX_LEN_HI 31
+#define DBG_RX_LEN_SZ 16
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SFT 8
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_HI 8
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SZ 1
+#define DBG_SPI_TX_ALLOC_SIZE_MSK 0x000000ff
+#define DBG_SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
+#define DBG_SPI_TX_ALLOC_SIZE_SFT 0
+#define DBG_SPI_TX_ALLOC_SIZE_HI 7
+#define DBG_SPI_TX_ALLOC_SIZE_SZ 8
+#define DBG_RD_DAT_CNT_MSK 0x0000ffff
+#define DBG_RD_DAT_CNT_I_MSK 0xffff0000
+#define DBG_RD_DAT_CNT_SFT 0
+#define DBG_RD_DAT_CNT_HI 15
+#define DBG_RD_DAT_CNT_SZ 16
+#define DBG_RD_STS_CNT_MSK 0xffff0000
+#define DBG_RD_STS_CNT_I_MSK 0x0000ffff
+#define DBG_RD_STS_CNT_SFT 16
+#define DBG_RD_STS_CNT_HI 31
+#define DBG_RD_STS_CNT_SZ 16
+#define DBG_JUDGE_CNT_MSK 0x0000ffff
+#define DBG_JUDGE_CNT_I_MSK 0xffff0000
+#define DBG_JUDGE_CNT_SFT 0
+#define DBG_JUDGE_CNT_HI 15
+#define DBG_JUDGE_CNT_SZ 16
+#define DBG_RD_STS_CNT_CLR_MSK 0x00010000
+#define DBG_RD_STS_CNT_CLR_I_MSK 0xfffeffff
+#define DBG_RD_STS_CNT_CLR_SFT 16
+#define DBG_RD_STS_CNT_CLR_HI 16
+#define DBG_RD_STS_CNT_CLR_SZ 1
+#define DBG_RD_DAT_CNT_CLR_MSK 0x00020000
+#define DBG_RD_DAT_CNT_CLR_I_MSK 0xfffdffff
+#define DBG_RD_DAT_CNT_CLR_SFT 17
+#define DBG_RD_DAT_CNT_CLR_HI 17
+#define DBG_RD_DAT_CNT_CLR_SZ 1
+#define DBG_JUDGE_CNT_CLR_MSK 0x00040000
+#define DBG_JUDGE_CNT_CLR_I_MSK 0xfffbffff
+#define DBG_JUDGE_CNT_CLR_SFT 18
+#define DBG_JUDGE_CNT_CLR_HI 18
+#define DBG_JUDGE_CNT_CLR_SZ 1
+#define DBG_TX_DONE_CNT_MSK 0x0000ffff
+#define DBG_TX_DONE_CNT_I_MSK 0xffff0000
+#define DBG_TX_DONE_CNT_SFT 0
+#define DBG_TX_DONE_CNT_HI 15
+#define DBG_TX_DONE_CNT_SZ 16
+#define DBG_TX_DISCARD_CNT_MSK 0xffff0000
+#define DBG_TX_DISCARD_CNT_I_MSK 0x0000ffff
+#define DBG_TX_DISCARD_CNT_SFT 16
+#define DBG_TX_DISCARD_CNT_HI 31
+#define DBG_TX_DISCARD_CNT_SZ 16
+#define DBG_TX_SET_CNT_MSK 0x0000ffff
+#define DBG_TX_SET_CNT_I_MSK 0xffff0000
+#define DBG_TX_SET_CNT_SFT 0
+#define DBG_TX_SET_CNT_HI 15
+#define DBG_TX_SET_CNT_SZ 16
+#define DBG_TX_DISCARD_CNT_CLR_MSK 0x00010000
+#define DBG_TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
+#define DBG_TX_DISCARD_CNT_CLR_SFT 16
+#define DBG_TX_DISCARD_CNT_CLR_HI 16
+#define DBG_TX_DISCARD_CNT_CLR_SZ 1
+#define DBG_TX_DONE_CNT_CLR_MSK 0x00020000
+#define DBG_TX_DONE_CNT_CLR_I_MSK 0xfffdffff
+#define DBG_TX_DONE_CNT_CLR_SFT 17
+#define DBG_TX_DONE_CNT_CLR_HI 17
+#define DBG_TX_DONE_CNT_CLR_SZ 1
+#define DBG_TX_SET_CNT_CLR_MSK 0x00040000
+#define DBG_TX_SET_CNT_CLR_I_MSK 0xfffbffff
+#define DBG_TX_SET_CNT_CLR_SFT 18
+#define DBG_TX_SET_CNT_CLR_HI 18
+#define DBG_TX_SET_CNT_CLR_SZ 1
+#define DBG_DAT_MODE_OFF_MSK 0x00080000
+#define DBG_DAT_MODE_OFF_I_MSK 0xfff7ffff
+#define DBG_DAT_MODE_OFF_SFT 19
+#define DBG_DAT_MODE_OFF_HI 19
+#define DBG_DAT_MODE_OFF_SZ 1
+#define DBG_TX_FIFO_RESIDUE_MSK 0x00700000
+#define DBG_TX_FIFO_RESIDUE_I_MSK 0xff8fffff
+#define DBG_TX_FIFO_RESIDUE_SFT 20
+#define DBG_TX_FIFO_RESIDUE_HI 22
+#define DBG_TX_FIFO_RESIDUE_SZ 3
+#define DBG_RX_FIFO_RESIDUE_MSK 0x07000000
+#define DBG_RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
+#define DBG_RX_FIFO_RESIDUE_SFT 24
+#define DBG_RX_FIFO_RESIDUE_HI 26
+#define DBG_RX_FIFO_RESIDUE_SZ 3
+#define DBG_RX_RDY_MSK 0x00000001
+#define DBG_RX_RDY_I_MSK 0xfffffffe
+#define DBG_RX_RDY_SFT 0
+#define DBG_RX_RDY_HI 0
+#define DBG_RX_RDY_SZ 1
+#define DBG_SDIO_SYS_INT_MSK 0x00000004
+#define DBG_SDIO_SYS_INT_I_MSK 0xfffffffb
+#define DBG_SDIO_SYS_INT_SFT 2
+#define DBG_SDIO_SYS_INT_HI 2
+#define DBG_SDIO_SYS_INT_SZ 1
+#define DBG_EDCA0_LOWTHOLD_INT_MSK 0x00000008
+#define DBG_EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define DBG_EDCA0_LOWTHOLD_INT_SFT 3
+#define DBG_EDCA0_LOWTHOLD_INT_HI 3
+#define DBG_EDCA0_LOWTHOLD_INT_SZ 1
+#define DBG_EDCA1_LOWTHOLD_INT_MSK 0x00000010
+#define DBG_EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
+#define DBG_EDCA1_LOWTHOLD_INT_SFT 4
+#define DBG_EDCA1_LOWTHOLD_INT_HI 4
+#define DBG_EDCA1_LOWTHOLD_INT_SZ 1
+#define DBG_EDCA2_LOWTHOLD_INT_MSK 0x00000020
+#define DBG_EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define DBG_EDCA2_LOWTHOLD_INT_SFT 5
+#define DBG_EDCA2_LOWTHOLD_INT_HI 5
+#define DBG_EDCA2_LOWTHOLD_INT_SZ 1
+#define DBG_EDCA3_LOWTHOLD_INT_MSK 0x00000040
+#define DBG_EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define DBG_EDCA3_LOWTHOLD_INT_SFT 6
+#define DBG_EDCA3_LOWTHOLD_INT_HI 6
+#define DBG_EDCA3_LOWTHOLD_INT_SZ 1
+#define DBG_TX_LIMIT_INT_IN_MSK 0x00000080
+#define DBG_TX_LIMIT_INT_IN_I_MSK 0xffffff7f
+#define DBG_TX_LIMIT_INT_IN_SFT 7
+#define DBG_TX_LIMIT_INT_IN_HI 7
+#define DBG_TX_LIMIT_INT_IN_SZ 1
+#define DBG_SPI_FN1_MSK 0x00007f00
+#define DBG_SPI_FN1_I_MSK 0xffff80ff
+#define DBG_SPI_FN1_SFT 8
+#define DBG_SPI_FN1_HI 14
+#define DBG_SPI_FN1_SZ 7
+#define DBG_SPI_CLK_EN_INT_MSK 0x00008000
+#define DBG_SPI_CLK_EN_INT_I_MSK 0xffff7fff
+#define DBG_SPI_CLK_EN_INT_SFT 15
+#define DBG_SPI_CLK_EN_INT_HI 15
+#define DBG_SPI_CLK_EN_INT_SZ 1
+#define DBG_SPI_HOST_MASK_MSK 0x00ff0000
+#define DBG_SPI_HOST_MASK_I_MSK 0xff00ffff
+#define DBG_SPI_HOST_MASK_SFT 16
+#define DBG_SPI_HOST_MASK_HI 23
+#define DBG_SPI_HOST_MASK_SZ 8
+#define BOOT_ADDR_MSK 0x00ffffff
+#define BOOT_ADDR_I_MSK 0xff000000
+#define BOOT_ADDR_SFT 0
+#define BOOT_ADDR_HI 23
+#define BOOT_ADDR_SZ 24
+#define CHECK_SUM_FAIL_MSK 0x80000000
+#define CHECK_SUM_FAIL_I_MSK 0x7fffffff
+#define CHECK_SUM_FAIL_SFT 31
+#define CHECK_SUM_FAIL_HI 31
+#define CHECK_SUM_FAIL_SZ 1
+#define VERIFY_DATA_MSK 0xffffffff
+#define VERIFY_DATA_I_MSK 0x00000000
+#define VERIFY_DATA_SFT 0
+#define VERIFY_DATA_HI 31
+#define VERIFY_DATA_SZ 32
+#define FLASH_ADDR_MSK 0x00ffffff
+#define FLASH_ADDR_I_MSK 0xff000000
+#define FLASH_ADDR_SFT 0
+#define FLASH_ADDR_HI 23
+#define FLASH_ADDR_SZ 24
+#define FLASH_CMD_CLR_MSK 0x10000000
+#define FLASH_CMD_CLR_I_MSK 0xefffffff
+#define FLASH_CMD_CLR_SFT 28
+#define FLASH_CMD_CLR_HI 28
+#define FLASH_CMD_CLR_SZ 1
+#define FLASH_DMA_CLR_MSK 0x20000000
+#define FLASH_DMA_CLR_I_MSK 0xdfffffff
+#define FLASH_DMA_CLR_SFT 29
+#define FLASH_DMA_CLR_HI 29
+#define FLASH_DMA_CLR_SZ 1
+#define DMA_EN_MSK 0x40000000
+#define DMA_EN_I_MSK 0xbfffffff
+#define DMA_EN_SFT 30
+#define DMA_EN_HI 30
+#define DMA_EN_SZ 1
+#define DMA_BUSY_MSK 0x80000000
+#define DMA_BUSY_I_MSK 0x7fffffff
+#define DMA_BUSY_SFT 31
+#define DMA_BUSY_HI 31
+#define DMA_BUSY_SZ 1
+#define SRAM_ADDR_MSK 0xffffffff
+#define SRAM_ADDR_I_MSK 0x00000000
+#define SRAM_ADDR_SFT 0
+#define SRAM_ADDR_HI 31
+#define SRAM_ADDR_SZ 32
+#define FLASH_DMA_LEN_MSK 0xffffffff
+#define FLASH_DMA_LEN_I_MSK 0x00000000
+#define FLASH_DMA_LEN_SFT 0
+#define FLASH_DMA_LEN_HI 31
+#define FLASH_DMA_LEN_SZ 32
+#define FLASH_FRONT_DLY_MSK 0x0000ffff
+#define FLASH_FRONT_DLY_I_MSK 0xffff0000
+#define FLASH_FRONT_DLY_SFT 0
+#define FLASH_FRONT_DLY_HI 15
+#define FLASH_FRONT_DLY_SZ 16
+#define FLASH_BACK_DLY_MSK 0xffff0000
+#define FLASH_BACK_DLY_I_MSK 0x0000ffff
+#define FLASH_BACK_DLY_SFT 16
+#define FLASH_BACK_DLY_HI 31
+#define FLASH_BACK_DLY_SZ 16
+#define FLASH_CLK_WIDTH_MSK 0x0000ffff
+#define FLASH_CLK_WIDTH_I_MSK 0xffff0000
+#define FLASH_CLK_WIDTH_SFT 0
+#define FLASH_CLK_WIDTH_HI 15
+#define FLASH_CLK_WIDTH_SZ 16
+#define SPI_BUSY_MSK 0x00010000
+#define SPI_BUSY_I_MSK 0xfffeffff
+#define SPI_BUSY_SFT 16
+#define SPI_BUSY_HI 16
+#define SPI_BUSY_SZ 1
+#define FLS_REMAP_MSK 0x00020000
+#define FLS_REMAP_I_MSK 0xfffdffff
+#define FLS_REMAP_SFT 17
+#define FLS_REMAP_HI 17
+#define FLS_REMAP_SZ 1
+#define PBUS_SWP_MSK 0x00040000
+#define PBUS_SWP_I_MSK 0xfffbffff
+#define PBUS_SWP_SFT 18
+#define PBUS_SWP_HI 18
+#define PBUS_SWP_SZ 1
+#define BIT_MODE1_MSK 0x00080000
+#define BIT_MODE1_I_MSK 0xfff7ffff
+#define BIT_MODE1_SFT 19
+#define BIT_MODE1_HI 19
+#define BIT_MODE1_SZ 1
+#define BIT_MODE2_MSK 0x00100000
+#define BIT_MODE2_I_MSK 0xffefffff
+#define BIT_MODE2_SFT 20
+#define BIT_MODE2_HI 20
+#define BIT_MODE2_SZ 1
+#define BIT_MODE4_MSK 0x00200000
+#define BIT_MODE4_I_MSK 0xffdfffff
+#define BIT_MODE4_SFT 21
+#define BIT_MODE4_HI 21
+#define BIT_MODE4_SZ 1
+#define BOOT_CHECK_SUM_MSK 0xffffffff
+#define BOOT_CHECK_SUM_I_MSK 0x00000000
+#define BOOT_CHECK_SUM_SFT 0
+#define BOOT_CHECK_SUM_HI 31
+#define BOOT_CHECK_SUM_SZ 32
+#define CHECK_SUM_TAG_MSK 0xffffffff
+#define CHECK_SUM_TAG_I_MSK 0x00000000
+#define CHECK_SUM_TAG_SFT 0
+#define CHECK_SUM_TAG_HI 31
+#define CHECK_SUM_TAG_SZ 32
+#define CMD_LEN_MSK 0x0000ffff
+#define CMD_LEN_I_MSK 0xffff0000
+#define CMD_LEN_SFT 0
+#define CMD_LEN_HI 15
+#define CMD_LEN_SZ 16
+#define CMD_ADDR_MSK 0xffffffff
+#define CMD_ADDR_I_MSK 0x00000000
+#define CMD_ADDR_SFT 0
+#define CMD_ADDR_HI 31
+#define CMD_ADDR_SZ 32
+#define DMA_ADR_SRC_MSK 0xffffffff
+#define DMA_ADR_SRC_I_MSK 0x00000000
+#define DMA_ADR_SRC_SFT 0
+#define DMA_ADR_SRC_HI 31
+#define DMA_ADR_SRC_SZ 32
+#define DMA_ADR_DST_MSK 0xffffffff
+#define DMA_ADR_DST_I_MSK 0x00000000
+#define DMA_ADR_DST_SFT 0
+#define DMA_ADR_DST_HI 31
+#define DMA_ADR_DST_SZ 32
+#define DMA_SRC_SIZE_MSK 0x00000007
+#define DMA_SRC_SIZE_I_MSK 0xfffffff8
+#define DMA_SRC_SIZE_SFT 0
+#define DMA_SRC_SIZE_HI 2
+#define DMA_SRC_SIZE_SZ 3
+#define DMA_SRC_INC_MSK 0x00000008
+#define DMA_SRC_INC_I_MSK 0xfffffff7
+#define DMA_SRC_INC_SFT 3
+#define DMA_SRC_INC_HI 3
+#define DMA_SRC_INC_SZ 1
+#define DMA_DST_SIZE_MSK 0x00000070
+#define DMA_DST_SIZE_I_MSK 0xffffff8f
+#define DMA_DST_SIZE_SFT 4
+#define DMA_DST_SIZE_HI 6
+#define DMA_DST_SIZE_SZ 3
+#define DMA_DST_INC_MSK 0x00000080
+#define DMA_DST_INC_I_MSK 0xffffff7f
+#define DMA_DST_INC_SFT 7
+#define DMA_DST_INC_HI 7
+#define DMA_DST_INC_SZ 1
+#define DMA_FAST_FILL_MSK 0x00000100
+#define DMA_FAST_FILL_I_MSK 0xfffffeff
+#define DMA_FAST_FILL_SFT 8
+#define DMA_FAST_FILL_HI 8
+#define DMA_FAST_FILL_SZ 1
+#define DMA_SDIO_KICK_MSK 0x00001000
+#define DMA_SDIO_KICK_I_MSK 0xffffefff
+#define DMA_SDIO_KICK_SFT 12
+#define DMA_SDIO_KICK_HI 12
+#define DMA_SDIO_KICK_SZ 1
+#define DMA_BADR_EN_MSK 0x00002000
+#define DMA_BADR_EN_I_MSK 0xffffdfff
+#define DMA_BADR_EN_SFT 13
+#define DMA_BADR_EN_HI 13
+#define DMA_BADR_EN_SZ 1
+#define DMA_LEN_MSK 0xffff0000
+#define DMA_LEN_I_MSK 0x0000ffff
+#define DMA_LEN_SFT 16
+#define DMA_LEN_HI 31
+#define DMA_LEN_SZ 16
+#define DMA_INT_MASK_MSK 0x00000001
+#define DMA_INT_MASK_I_MSK 0xfffffffe
+#define DMA_INT_MASK_SFT 0
+#define DMA_INT_MASK_HI 0
+#define DMA_INT_MASK_SZ 1
+#define DMA_STS_MSK 0x00000100
+#define DMA_STS_I_MSK 0xfffffeff
+#define DMA_STS_SFT 8
+#define DMA_STS_HI 8
+#define DMA_STS_SZ 1
+#define DMA_FINISH_MSK 0x80000000
+#define DMA_FINISH_I_MSK 0x7fffffff
+#define DMA_FINISH_SFT 31
+#define DMA_FINISH_HI 31
+#define DMA_FINISH_SZ 1
+#define DMA_CONST_MSK 0xffffffff
+#define DMA_CONST_I_MSK 0x00000000
+#define DMA_CONST_SFT 0
+#define DMA_CONST_HI 31
+#define DMA_CONST_SZ 32
+#define SLEEP_WAKE_CNT_MSK 0x00ffffff
+#define SLEEP_WAKE_CNT_I_MSK 0xff000000
+#define SLEEP_WAKE_CNT_SFT 0
+#define SLEEP_WAKE_CNT_HI 23
+#define SLEEP_WAKE_CNT_SZ 24
+#define RG_DLDO_LEVEL_MSK 0x07000000
+#define RG_DLDO_LEVEL_I_MSK 0xf8ffffff
+#define RG_DLDO_LEVEL_SFT 24
+#define RG_DLDO_LEVEL_HI 26
+#define RG_DLDO_LEVEL_SZ 3
+#define RG_DLDO_BOOST_IQ_MSK 0x08000000
+#define RG_DLDO_BOOST_IQ_I_MSK 0xf7ffffff
+#define RG_DLDO_BOOST_IQ_SFT 27
+#define RG_DLDO_BOOST_IQ_HI 27
+#define RG_DLDO_BOOST_IQ_SZ 1
+#define RG_BUCK_LEVEL_MSK 0x70000000
+#define RG_BUCK_LEVEL_I_MSK 0x8fffffff
+#define RG_BUCK_LEVEL_SFT 28
+#define RG_BUCK_LEVEL_HI 30
+#define RG_BUCK_LEVEL_SZ 3
+#define RG_BUCK_VREF_SEL_MSK 0x80000000
+#define RG_BUCK_VREF_SEL_I_MSK 0x7fffffff
+#define RG_BUCK_VREF_SEL_SFT 31
+#define RG_BUCK_VREF_SEL_HI 31
+#define RG_BUCK_VREF_SEL_SZ 1
+#define RG_RTC_OSC_RES_SW_MANUAL_MSK 0x000003ff
+#define RG_RTC_OSC_RES_SW_MANUAL_I_MSK 0xfffffc00
+#define RG_RTC_OSC_RES_SW_MANUAL_SFT 0
+#define RG_RTC_OSC_RES_SW_MANUAL_HI 9
+#define RG_RTC_OSC_RES_SW_MANUAL_SZ 10
+#define RG_RTC_OSC_RES_SW_MSK 0x03ff0000
+#define RG_RTC_OSC_RES_SW_I_MSK 0xfc00ffff
+#define RG_RTC_OSC_RES_SW_SFT 16
+#define RG_RTC_OSC_RES_SW_HI 25
+#define RG_RTC_OSC_RES_SW_SZ 10
+#define RTC_OSC_CAL_RES_RDY_MSK 0x80000000
+#define RTC_OSC_CAL_RES_RDY_I_MSK 0x7fffffff
+#define RTC_OSC_CAL_RES_RDY_SFT 31
+#define RTC_OSC_CAL_RES_RDY_HI 31
+#define RTC_OSC_CAL_RES_RDY_SZ 1
+#define RG_DCDC_MODE_MSK 0x00000001
+#define RG_DCDC_MODE_I_MSK 0xfffffffe
+#define RG_DCDC_MODE_SFT 0
+#define RG_DCDC_MODE_HI 0
+#define RG_DCDC_MODE_SZ 1
+#define RG_BUCK_EN_PSM_MSK 0x00000010
+#define RG_BUCK_EN_PSM_I_MSK 0xffffffef
+#define RG_BUCK_EN_PSM_SFT 4
+#define RG_BUCK_EN_PSM_HI 4
+#define RG_BUCK_EN_PSM_SZ 1
+#define RG_BUCK_PSM_VTH_MSK 0x00000100
+#define RG_BUCK_PSM_VTH_I_MSK 0xfffffeff
+#define RG_BUCK_PSM_VTH_SFT 8
+#define RG_BUCK_PSM_VTH_HI 8
+#define RG_BUCK_PSM_VTH_SZ 1
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_MSK 0x00001000
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_I_MSK 0xffffefff
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_SFT 12
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_HI 12
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_SZ 1
+#define RG_RTC_RDY_DEGLITCH_TIMER_MSK 0x00006000
+#define RG_RTC_RDY_DEGLITCH_TIMER_I_MSK 0xffff9fff
+#define RG_RTC_RDY_DEGLITCH_TIMER_SFT 13
+#define RG_RTC_RDY_DEGLITCH_TIMER_HI 14
+#define RG_RTC_RDY_DEGLITCH_TIMER_SZ 2
+#define RTC_CAL_ENA_MSK 0x00010000
+#define RTC_CAL_ENA_I_MSK 0xfffeffff
+#define RTC_CAL_ENA_SFT 16
+#define RTC_CAL_ENA_HI 16
+#define RTC_CAL_ENA_SZ 1
+#define PMU_WAKE_TRIG_EVENT_MSK 0x00000003
+#define PMU_WAKE_TRIG_EVENT_I_MSK 0xfffffffc
+#define PMU_WAKE_TRIG_EVENT_SFT 0
+#define PMU_WAKE_TRIG_EVENT_HI 1
+#define PMU_WAKE_TRIG_EVENT_SZ 2
+#define DIGI_TOP_POR_MASK_MSK 0x00000010
+#define DIGI_TOP_POR_MASK_I_MSK 0xffffffef
+#define DIGI_TOP_POR_MASK_SFT 4
+#define DIGI_TOP_POR_MASK_HI 4
+#define DIGI_TOP_POR_MASK_SZ 1
+#define PMU_ENTER_SLEEP_MODE_MSK 0x00000100
+#define PMU_ENTER_SLEEP_MODE_I_MSK 0xfffffeff
+#define PMU_ENTER_SLEEP_MODE_SFT 8
+#define PMU_ENTER_SLEEP_MODE_HI 8
+#define PMU_ENTER_SLEEP_MODE_SZ 1
+#define RG_RTC_DUMMIES_MSK 0xffff0000
+#define RG_RTC_DUMMIES_I_MSK 0x0000ffff
+#define RG_RTC_DUMMIES_SFT 16
+#define RG_RTC_DUMMIES_HI 31
+#define RG_RTC_DUMMIES_SZ 16
+#define RTC_EN_MSK 0x00000001
+#define RTC_EN_I_MSK 0xfffffffe
+#define RTC_EN_SFT 0
+#define RTC_EN_HI 0
+#define RTC_EN_SZ 1
+#define RTC_SRC_MSK 0x00000002
+#define RTC_SRC_I_MSK 0xfffffffd
+#define RTC_SRC_SFT 1
+#define RTC_SRC_HI 1
+#define RTC_SRC_SZ 1
+#define RTC_TICK_CNT_MSK 0x7fff0000
+#define RTC_TICK_CNT_I_MSK 0x8000ffff
+#define RTC_TICK_CNT_SFT 16
+#define RTC_TICK_CNT_HI 30
+#define RTC_TICK_CNT_SZ 15
+#define RTC_INT_SEC_MASK_MSK 0x00000001
+#define RTC_INT_SEC_MASK_I_MSK 0xfffffffe
+#define RTC_INT_SEC_MASK_SFT 0
+#define RTC_INT_SEC_MASK_HI 0
+#define RTC_INT_SEC_MASK_SZ 1
+#define RTC_INT_ALARM_MASK_MSK 0x00000002
+#define RTC_INT_ALARM_MASK_I_MSK 0xfffffffd
+#define RTC_INT_ALARM_MASK_SFT 1
+#define RTC_INT_ALARM_MASK_HI 1
+#define RTC_INT_ALARM_MASK_SZ 1
+#define RTC_INT_SEC_MSK 0x00010000
+#define RTC_INT_SEC_I_MSK 0xfffeffff
+#define RTC_INT_SEC_SFT 16
+#define RTC_INT_SEC_HI 16
+#define RTC_INT_SEC_SZ 1
+#define RTC_INT_ALARM_MSK 0x00020000
+#define RTC_INT_ALARM_I_MSK 0xfffdffff
+#define RTC_INT_ALARM_SFT 17
+#define RTC_INT_ALARM_HI 17
+#define RTC_INT_ALARM_SZ 1
+#define RTC_SEC_START_CNT_MSK 0xffffffff
+#define RTC_SEC_START_CNT_I_MSK 0x00000000
+#define RTC_SEC_START_CNT_SFT 0
+#define RTC_SEC_START_CNT_HI 31
+#define RTC_SEC_START_CNT_SZ 32
+#define RTC_SEC_CNT_MSK 0xffffffff
+#define RTC_SEC_CNT_I_MSK 0x00000000
+#define RTC_SEC_CNT_SFT 0
+#define RTC_SEC_CNT_HI 31
+#define RTC_SEC_CNT_SZ 32
+#define RTC_SEC_ALARM_VALUE_MSK 0xffffffff
+#define RTC_SEC_ALARM_VALUE_I_MSK 0x00000000
+#define RTC_SEC_ALARM_VALUE_SFT 0
+#define RTC_SEC_ALARM_VALUE_HI 31
+#define RTC_SEC_ALARM_VALUE_SZ 32
+#define D2_DMA_ADR_SRC_MSK 0xffffffff
+#define D2_DMA_ADR_SRC_I_MSK 0x00000000
+#define D2_DMA_ADR_SRC_SFT 0
+#define D2_DMA_ADR_SRC_HI 31
+#define D2_DMA_ADR_SRC_SZ 32
+#define D2_DMA_ADR_DST_MSK 0xffffffff
+#define D2_DMA_ADR_DST_I_MSK 0x00000000
+#define D2_DMA_ADR_DST_SFT 0
+#define D2_DMA_ADR_DST_HI 31
+#define D2_DMA_ADR_DST_SZ 32
+#define D2_DMA_SRC_SIZE_MSK 0x00000007
+#define D2_DMA_SRC_SIZE_I_MSK 0xfffffff8
+#define D2_DMA_SRC_SIZE_SFT 0
+#define D2_DMA_SRC_SIZE_HI 2
+#define D2_DMA_SRC_SIZE_SZ 3
+#define D2_DMA_SRC_INC_MSK 0x00000008
+#define D2_DMA_SRC_INC_I_MSK 0xfffffff7
+#define D2_DMA_SRC_INC_SFT 3
+#define D2_DMA_SRC_INC_HI 3
+#define D2_DMA_SRC_INC_SZ 1
+#define D2_DMA_DST_SIZE_MSK 0x00000070
+#define D2_DMA_DST_SIZE_I_MSK 0xffffff8f
+#define D2_DMA_DST_SIZE_SFT 4
+#define D2_DMA_DST_SIZE_HI 6
+#define D2_DMA_DST_SIZE_SZ 3
+#define D2_DMA_DST_INC_MSK 0x00000080
+#define D2_DMA_DST_INC_I_MSK 0xffffff7f
+#define D2_DMA_DST_INC_SFT 7
+#define D2_DMA_DST_INC_HI 7
+#define D2_DMA_DST_INC_SZ 1
+#define D2_DMA_FAST_FILL_MSK 0x00000100
+#define D2_DMA_FAST_FILL_I_MSK 0xfffffeff
+#define D2_DMA_FAST_FILL_SFT 8
+#define D2_DMA_FAST_FILL_HI 8
+#define D2_DMA_FAST_FILL_SZ 1
+#define D2_DMA_SDIO_KICK_MSK 0x00001000
+#define D2_DMA_SDIO_KICK_I_MSK 0xffffefff
+#define D2_DMA_SDIO_KICK_SFT 12
+#define D2_DMA_SDIO_KICK_HI 12
+#define D2_DMA_SDIO_KICK_SZ 1
+#define D2_DMA_BADR_EN_MSK 0x00002000
+#define D2_DMA_BADR_EN_I_MSK 0xffffdfff
+#define D2_DMA_BADR_EN_SFT 13
+#define D2_DMA_BADR_EN_HI 13
+#define D2_DMA_BADR_EN_SZ 1
+#define D2_DMA_LEN_MSK 0xffff0000
+#define D2_DMA_LEN_I_MSK 0x0000ffff
+#define D2_DMA_LEN_SFT 16
+#define D2_DMA_LEN_HI 31
+#define D2_DMA_LEN_SZ 16
+#define D2_DMA_INT_MASK_MSK 0x00000001
+#define D2_DMA_INT_MASK_I_MSK 0xfffffffe
+#define D2_DMA_INT_MASK_SFT 0
+#define D2_DMA_INT_MASK_HI 0
+#define D2_DMA_INT_MASK_SZ 1
+#define D2_DMA_STS_MSK 0x00000100
+#define D2_DMA_STS_I_MSK 0xfffffeff
+#define D2_DMA_STS_SFT 8
+#define D2_DMA_STS_HI 8
+#define D2_DMA_STS_SZ 1
+#define D2_DMA_FINISH_MSK 0x80000000
+#define D2_DMA_FINISH_I_MSK 0x7fffffff
+#define D2_DMA_FINISH_SFT 31
+#define D2_DMA_FINISH_HI 31
+#define D2_DMA_FINISH_SZ 1
+#define D2_DMA_CONST_MSK 0xffffffff
+#define D2_DMA_CONST_I_MSK 0x00000000
+#define D2_DMA_CONST_SFT 0
+#define D2_DMA_CONST_HI 31
+#define D2_DMA_CONST_SZ 32
+#define TRAP_UNKNOWN_TYPE_MSK 0x00000001
+#define TRAP_UNKNOWN_TYPE_I_MSK 0xfffffffe
+#define TRAP_UNKNOWN_TYPE_SFT 0
+#define TRAP_UNKNOWN_TYPE_HI 0
+#define TRAP_UNKNOWN_TYPE_SZ 1
+#define TX_ON_DEMAND_ENA_MSK 0x00000002
+#define TX_ON_DEMAND_ENA_I_MSK 0xfffffffd
+#define TX_ON_DEMAND_ENA_SFT 1
+#define TX_ON_DEMAND_ENA_HI 1
+#define TX_ON_DEMAND_ENA_SZ 1
+#define RX_2_HOST_MSK 0x00000004
+#define RX_2_HOST_I_MSK 0xfffffffb
+#define RX_2_HOST_SFT 2
+#define RX_2_HOST_HI 2
+#define RX_2_HOST_SZ 1
+#define AUTO_SEQNO_MSK 0x00000008
+#define AUTO_SEQNO_I_MSK 0xfffffff7
+#define AUTO_SEQNO_SFT 3
+#define AUTO_SEQNO_HI 3
+#define AUTO_SEQNO_SZ 1
+#define BYPASSS_TX_PARSER_ENCAP_MSK 0x00000010
+#define BYPASSS_TX_PARSER_ENCAP_I_MSK 0xffffffef
+#define BYPASSS_TX_PARSER_ENCAP_SFT 4
+#define BYPASSS_TX_PARSER_ENCAP_HI 4
+#define BYPASSS_TX_PARSER_ENCAP_SZ 1
+#define HDR_STRIP_MSK 0x00000020
+#define HDR_STRIP_I_MSK 0xffffffdf
+#define HDR_STRIP_SFT 5
+#define HDR_STRIP_HI 5
+#define HDR_STRIP_SZ 1
+#define ERP_PROTECT_MSK 0x000000c0
+#define ERP_PROTECT_I_MSK 0xffffff3f
+#define ERP_PROTECT_SFT 6
+#define ERP_PROTECT_HI 7
+#define ERP_PROTECT_SZ 2
+#define PRO_VER_MSK 0x00000300
+#define PRO_VER_I_MSK 0xfffffcff
+#define PRO_VER_SFT 8
+#define PRO_VER_HI 9
+#define PRO_VER_SZ 2
+#define TXQ_ID0_MSK 0x00007000
+#define TXQ_ID0_I_MSK 0xffff8fff
+#define TXQ_ID0_SFT 12
+#define TXQ_ID0_HI 14
+#define TXQ_ID0_SZ 3
+#define TXQ_ID1_MSK 0x00070000
+#define TXQ_ID1_I_MSK 0xfff8ffff
+#define TXQ_ID1_SFT 16
+#define TXQ_ID1_HI 18
+#define TXQ_ID1_SZ 3
+#define TX_ETHER_TRAP_EN_MSK 0x00100000
+#define TX_ETHER_TRAP_EN_I_MSK 0xffefffff
+#define TX_ETHER_TRAP_EN_SFT 20
+#define TX_ETHER_TRAP_EN_HI 20
+#define TX_ETHER_TRAP_EN_SZ 1
+#define RX_ETHER_TRAP_EN_MSK 0x00200000
+#define RX_ETHER_TRAP_EN_I_MSK 0xffdfffff
+#define RX_ETHER_TRAP_EN_SFT 21
+#define RX_ETHER_TRAP_EN_HI 21
+#define RX_ETHER_TRAP_EN_SZ 1
+#define RX_NULL_TRAP_EN_MSK 0x00400000
+#define RX_NULL_TRAP_EN_I_MSK 0xffbfffff
+#define RX_NULL_TRAP_EN_SFT 22
+#define RX_NULL_TRAP_EN_HI 22
+#define RX_NULL_TRAP_EN_SZ 1
+#define RX_GET_TX_QUEUE_EN_MSK 0x02000000
+#define RX_GET_TX_QUEUE_EN_I_MSK 0xfdffffff
+#define RX_GET_TX_QUEUE_EN_SFT 25
+#define RX_GET_TX_QUEUE_EN_HI 25
+#define RX_GET_TX_QUEUE_EN_SZ 1
+#define HCI_INQ_SEL_MSK 0x04000000
+#define HCI_INQ_SEL_I_MSK 0xfbffffff
+#define HCI_INQ_SEL_SFT 26
+#define HCI_INQ_SEL_HI 26
+#define HCI_INQ_SEL_SZ 1
+#define TRX_DEBUG_CNT_ENA_MSK 0x10000000
+#define TRX_DEBUG_CNT_ENA_I_MSK 0xefffffff
+#define TRX_DEBUG_CNT_ENA_SFT 28
+#define TRX_DEBUG_CNT_ENA_HI 28
+#define TRX_DEBUG_CNT_ENA_SZ 1
+#define WAKE_SOON_WITH_SCK_MSK 0x00000001
+#define WAKE_SOON_WITH_SCK_I_MSK 0xfffffffe
+#define WAKE_SOON_WITH_SCK_SFT 0
+#define WAKE_SOON_WITH_SCK_HI 0
+#define WAKE_SOON_WITH_SCK_SZ 1
+#define TX_FLOW_CTRL_MSK 0x0000ffff
+#define TX_FLOW_CTRL_I_MSK 0xffff0000
+#define TX_FLOW_CTRL_SFT 0
+#define TX_FLOW_CTRL_HI 15
+#define TX_FLOW_CTRL_SZ 16
+#define TX_FLOW_MGMT_MSK 0xffff0000
+#define TX_FLOW_MGMT_I_MSK 0x0000ffff
+#define TX_FLOW_MGMT_SFT 16
+#define TX_FLOW_MGMT_HI 31
+#define TX_FLOW_MGMT_SZ 16
+#define TX_FLOW_DATA_MSK 0xffffffff
+#define TX_FLOW_DATA_I_MSK 0x00000000
+#define TX_FLOW_DATA_SFT 0
+#define TX_FLOW_DATA_HI 31
+#define TX_FLOW_DATA_SZ 32
+#define DOT11RTSTHRESHOLD_MSK 0xffff0000
+#define DOT11RTSTHRESHOLD_I_MSK 0x0000ffff
+#define DOT11RTSTHRESHOLD_SFT 16
+#define DOT11RTSTHRESHOLD_HI 31
+#define DOT11RTSTHRESHOLD_SZ 16
+#define TXF_ID_MSK 0x0000003f
+#define TXF_ID_I_MSK 0xffffffc0
+#define TXF_ID_SFT 0
+#define TXF_ID_HI 5
+#define TXF_ID_SZ 6
+#define SEQ_CTRL_MSK 0x0000ffff
+#define SEQ_CTRL_I_MSK 0xffff0000
+#define SEQ_CTRL_SFT 0
+#define SEQ_CTRL_HI 15
+#define SEQ_CTRL_SZ 16
+#define TX_PBOFFSET_MSK 0x000000ff
+#define TX_PBOFFSET_I_MSK 0xffffff00
+#define TX_PBOFFSET_SFT 0
+#define TX_PBOFFSET_HI 7
+#define TX_PBOFFSET_SZ 8
+#define TX_INFO_SIZE_MSK 0x0000ff00
+#define TX_INFO_SIZE_I_MSK 0xffff00ff
+#define TX_INFO_SIZE_SFT 8
+#define TX_INFO_SIZE_HI 15
+#define TX_INFO_SIZE_SZ 8
+#define RX_INFO_SIZE_MSK 0x00ff0000
+#define RX_INFO_SIZE_I_MSK 0xff00ffff
+#define RX_INFO_SIZE_SFT 16
+#define RX_INFO_SIZE_HI 23
+#define RX_INFO_SIZE_SZ 8
+#define RX_LAST_PHY_SIZE_MSK 0xff000000
+#define RX_LAST_PHY_SIZE_I_MSK 0x00ffffff
+#define RX_LAST_PHY_SIZE_SFT 24
+#define RX_LAST_PHY_SIZE_HI 31
+#define RX_LAST_PHY_SIZE_SZ 8
+#define TX_INFO_CLEAR_SIZE_MSK 0x0000003f
+#define TX_INFO_CLEAR_SIZE_I_MSK 0xffffffc0
+#define TX_INFO_CLEAR_SIZE_SFT 0
+#define TX_INFO_CLEAR_SIZE_HI 5
+#define TX_INFO_CLEAR_SIZE_SZ 6
+#define TX_INFO_CLEAR_ENABLE_MSK 0x00000100
+#define TX_INFO_CLEAR_ENABLE_I_MSK 0xfffffeff
+#define TX_INFO_CLEAR_ENABLE_SFT 8
+#define TX_INFO_CLEAR_ENABLE_HI 8
+#define TX_INFO_CLEAR_ENABLE_SZ 1
+#define TXTRAP_ETHTYPE1_MSK 0x0000ffff
+#define TXTRAP_ETHTYPE1_I_MSK 0xffff0000
+#define TXTRAP_ETHTYPE1_SFT 0
+#define TXTRAP_ETHTYPE1_HI 15
+#define TXTRAP_ETHTYPE1_SZ 16
+#define TXTRAP_ETHTYPE0_MSK 0xffff0000
+#define TXTRAP_ETHTYPE0_I_MSK 0x0000ffff
+#define TXTRAP_ETHTYPE0_SFT 16
+#define TXTRAP_ETHTYPE0_HI 31
+#define TXTRAP_ETHTYPE0_SZ 16
+#define RXTRAP_ETHTYPE1_MSK 0x0000ffff
+#define RXTRAP_ETHTYPE1_I_MSK 0xffff0000
+#define RXTRAP_ETHTYPE1_SFT 0
+#define RXTRAP_ETHTYPE1_HI 15
+#define RXTRAP_ETHTYPE1_SZ 16
+#define RXTRAP_ETHTYPE0_MSK 0xffff0000
+#define RXTRAP_ETHTYPE0_I_MSK 0x0000ffff
+#define RXTRAP_ETHTYPE0_SFT 16
+#define RXTRAP_ETHTYPE0_HI 31
+#define RXTRAP_ETHTYPE0_SZ 16
+#define TX_PKT_COUNTER_MSK 0xffffffff
+#define TX_PKT_COUNTER_I_MSK 0x00000000
+#define TX_PKT_COUNTER_SFT 0
+#define TX_PKT_COUNTER_HI 31
+#define TX_PKT_COUNTER_SZ 32
+#define RX_PKT_COUNTER_MSK 0xffffffff
+#define RX_PKT_COUNTER_I_MSK 0x00000000
+#define RX_PKT_COUNTER_SFT 0
+#define RX_PKT_COUNTER_HI 31
+#define RX_PKT_COUNTER_SZ 32
+#define HOST_CMD_COUNTER_MSK 0x000000ff
+#define HOST_CMD_COUNTER_I_MSK 0xffffff00
+#define HOST_CMD_COUNTER_SFT 0
+#define HOST_CMD_COUNTER_HI 7
+#define HOST_CMD_COUNTER_SZ 8
+#define HOST_EVENT_COUNTER_MSK 0x000000ff
+#define HOST_EVENT_COUNTER_I_MSK 0xffffff00
+#define HOST_EVENT_COUNTER_SFT 0
+#define HOST_EVENT_COUNTER_HI 7
+#define HOST_EVENT_COUNTER_SZ 8
+#define TX_PKT_DROP_COUNTER_MSK 0x000000ff
+#define TX_PKT_DROP_COUNTER_I_MSK 0xffffff00
+#define TX_PKT_DROP_COUNTER_SFT 0
+#define TX_PKT_DROP_COUNTER_HI 7
+#define TX_PKT_DROP_COUNTER_SZ 8
+#define RX_PKT_DROP_COUNTER_MSK 0x000000ff
+#define RX_PKT_DROP_COUNTER_I_MSK 0xffffff00
+#define RX_PKT_DROP_COUNTER_SFT 0
+#define RX_PKT_DROP_COUNTER_HI 7
+#define RX_PKT_DROP_COUNTER_SZ 8
+#define TX_PKT_TRAP_COUNTER_MSK 0x000000ff
+#define TX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
+#define TX_PKT_TRAP_COUNTER_SFT 0
+#define TX_PKT_TRAP_COUNTER_HI 7
+#define TX_PKT_TRAP_COUNTER_SZ 8
+#define RX_PKT_TRAP_COUNTER_MSK 0x000000ff
+#define RX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
+#define RX_PKT_TRAP_COUNTER_SFT 0
+#define RX_PKT_TRAP_COUNTER_HI 7
+#define RX_PKT_TRAP_COUNTER_SZ 8
+#define HOST_TX_FAIL_COUNTER_MSK 0x000000ff
+#define HOST_TX_FAIL_COUNTER_I_MSK 0xffffff00
+#define HOST_TX_FAIL_COUNTER_SFT 0
+#define HOST_TX_FAIL_COUNTER_HI 7
+#define HOST_TX_FAIL_COUNTER_SZ 8
+#define HOST_RX_FAIL_COUNTER_MSK 0x000000ff
+#define HOST_RX_FAIL_COUNTER_I_MSK 0xffffff00
+#define HOST_RX_FAIL_COUNTER_SFT 0
+#define HOST_RX_FAIL_COUNTER_HI 7
+#define HOST_RX_FAIL_COUNTER_SZ 8
+#define HCI_STATE_MONITOR_MSK 0xffffffff
+#define HCI_STATE_MONITOR_I_MSK 0x00000000
+#define HCI_STATE_MONITOR_SFT 0
+#define HCI_STATE_MONITOR_HI 31
+#define HCI_STATE_MONITOR_SZ 32
+#define HCI_ST_TIMEOUT_MONITOR_MSK 0xffffffff
+#define HCI_ST_TIMEOUT_MONITOR_I_MSK 0x00000000
+#define HCI_ST_TIMEOUT_MONITOR_SFT 0
+#define HCI_ST_TIMEOUT_MONITOR_HI 31
+#define HCI_ST_TIMEOUT_MONITOR_SZ 32
+#define TX_ON_DEMAND_LENGTH_MSK 0xffffffff
+#define TX_ON_DEMAND_LENGTH_I_MSK 0x00000000
+#define TX_ON_DEMAND_LENGTH_SFT 0
+#define TX_ON_DEMAND_LENGTH_HI 31
+#define TX_ON_DEMAND_LENGTH_SZ 32
+#define HCI_MONITOR_REG1_MSK 0xffffffff
+#define HCI_MONITOR_REG1_I_MSK 0x00000000
+#define HCI_MONITOR_REG1_SFT 0
+#define HCI_MONITOR_REG1_HI 31
+#define HCI_MONITOR_REG1_SZ 32
+#define HCI_MONITOR_REG2_MSK 0xffffffff
+#define HCI_MONITOR_REG2_I_MSK 0x00000000
+#define HCI_MONITOR_REG2_SFT 0
+#define HCI_MONITOR_REG2_HI 31
+#define HCI_MONITOR_REG2_SZ 32
+#define HCI_TX_ALLOC_TIME_31_0_MSK 0xffffffff
+#define HCI_TX_ALLOC_TIME_31_0_I_MSK 0x00000000
+#define HCI_TX_ALLOC_TIME_31_0_SFT 0
+#define HCI_TX_ALLOC_TIME_31_0_HI 31
+#define HCI_TX_ALLOC_TIME_31_0_SZ 32
+#define HCI_TX_ALLOC_TIME_47_32_MSK 0x0000ffff
+#define HCI_TX_ALLOC_TIME_47_32_I_MSK 0xffff0000
+#define HCI_TX_ALLOC_TIME_47_32_SFT 0
+#define HCI_TX_ALLOC_TIME_47_32_HI 15
+#define HCI_TX_ALLOC_TIME_47_32_SZ 16
+#define HCI_MB_MAX_CNT_MSK 0x00ff0000
+#define HCI_MB_MAX_CNT_I_MSK 0xff00ffff
+#define HCI_MB_MAX_CNT_SFT 16
+#define HCI_MB_MAX_CNT_HI 23
+#define HCI_MB_MAX_CNT_SZ 8
+#define HCI_TX_ALLOC_CNT_31_0_MSK 0xffffffff
+#define HCI_TX_ALLOC_CNT_31_0_I_MSK 0x00000000
+#define HCI_TX_ALLOC_CNT_31_0_SFT 0
+#define HCI_TX_ALLOC_CNT_31_0_HI 31
+#define HCI_TX_ALLOC_CNT_31_0_SZ 32
+#define HCI_TX_ALLOC_CNT_47_32_MSK 0x0000ffff
+#define HCI_TX_ALLOC_CNT_47_32_I_MSK 0xffff0000
+#define HCI_TX_ALLOC_CNT_47_32_SFT 0
+#define HCI_TX_ALLOC_CNT_47_32_HI 15
+#define HCI_TX_ALLOC_CNT_47_32_SZ 16
+#define HCI_PROC_CNT_MSK 0x00ff0000
+#define HCI_PROC_CNT_I_MSK 0xff00ffff
+#define HCI_PROC_CNT_SFT 16
+#define HCI_PROC_CNT_HI 23
+#define HCI_PROC_CNT_SZ 8
+#define SDIO_TRANS_CNT_MSK 0xff000000
+#define SDIO_TRANS_CNT_I_MSK 0x00ffffff
+#define SDIO_TRANS_CNT_SFT 24
+#define SDIO_TRANS_CNT_HI 31
+#define SDIO_TRANS_CNT_SZ 8
+#define SDIO_TX_INVALID_CNT_31_0_MSK 0xffffffff
+#define SDIO_TX_INVALID_CNT_31_0_I_MSK 0x00000000
+#define SDIO_TX_INVALID_CNT_31_0_SFT 0
+#define SDIO_TX_INVALID_CNT_31_0_HI 31
+#define SDIO_TX_INVALID_CNT_31_0_SZ 32
+#define SDIO_TX_INVALID_CNT_47_32_MSK 0x0000ffff
+#define SDIO_TX_INVALID_CNT_47_32_I_MSK 0xffff0000
+#define SDIO_TX_INVALID_CNT_47_32_SFT 0
+#define SDIO_TX_INVALID_CNT_47_32_HI 15
+#define SDIO_TX_INVALID_CNT_47_32_SZ 16
+#define CS_START_ADDR_MSK 0x0000ffff
+#define CS_START_ADDR_I_MSK 0xffff0000
+#define CS_START_ADDR_SFT 0
+#define CS_START_ADDR_HI 15
+#define CS_START_ADDR_SZ 16
+#define CS_PKT_ID_MSK 0x007f0000
+#define CS_PKT_ID_I_MSK 0xff80ffff
+#define CS_PKT_ID_SFT 16
+#define CS_PKT_ID_HI 22
+#define CS_PKT_ID_SZ 7
+#define ADD_LEN_MSK 0x0000ffff
+#define ADD_LEN_I_MSK 0xffff0000
+#define ADD_LEN_SFT 0
+#define ADD_LEN_HI 15
+#define ADD_LEN_SZ 16
+#define CS_ADDER_EN_MSK 0x00000001
+#define CS_ADDER_EN_I_MSK 0xfffffffe
+#define CS_ADDER_EN_SFT 0
+#define CS_ADDER_EN_HI 0
+#define CS_ADDER_EN_SZ 1
+#define PSEUDO_MSK 0x00000002
+#define PSEUDO_I_MSK 0xfffffffd
+#define PSEUDO_SFT 1
+#define PSEUDO_HI 1
+#define PSEUDO_SZ 1
+#define CALCULATE_MSK 0xffffffff
+#define CALCULATE_I_MSK 0x00000000
+#define CALCULATE_SFT 0
+#define CALCULATE_HI 31
+#define CALCULATE_SZ 32
+#define L4_LEN_MSK 0x0000ffff
+#define L4_LEN_I_MSK 0xffff0000
+#define L4_LEN_SFT 0
+#define L4_LEN_HI 15
+#define L4_LEN_SZ 16
+#define L4_PROTOL_MSK 0x00ff0000
+#define L4_PROTOL_I_MSK 0xff00ffff
+#define L4_PROTOL_SFT 16
+#define L4_PROTOL_HI 23
+#define L4_PROTOL_SZ 8
+#define CHECK_SUM_MSK 0x0000ffff
+#define CHECK_SUM_I_MSK 0xffff0000
+#define CHECK_SUM_SFT 0
+#define CHECK_SUM_HI 15
+#define CHECK_SUM_SZ 16
+#define RAND_EN_MSK 0x00000001
+#define RAND_EN_I_MSK 0xfffffffe
+#define RAND_EN_SFT 0
+#define RAND_EN_HI 0
+#define RAND_EN_SZ 1
+#define RAND_NUM_MSK 0xffffffff
+#define RAND_NUM_I_MSK 0x00000000
+#define RAND_NUM_SFT 0
+#define RAND_NUM_HI 31
+#define RAND_NUM_SZ 32
+#define MUL_OP1_MSK 0xffffffff
+#define MUL_OP1_I_MSK 0x00000000
+#define MUL_OP1_SFT 0
+#define MUL_OP1_HI 31
+#define MUL_OP1_SZ 32
+#define MUL_OP2_MSK 0xffffffff
+#define MUL_OP2_I_MSK 0x00000000
+#define MUL_OP2_SFT 0
+#define MUL_OP2_HI 31
+#define MUL_OP2_SZ 32
+#define MUL_ANS0_MSK 0xffffffff
+#define MUL_ANS0_I_MSK 0x00000000
+#define MUL_ANS0_SFT 0
+#define MUL_ANS0_HI 31
+#define MUL_ANS0_SZ 32
+#define MUL_ANS1_MSK 0xffffffff
+#define MUL_ANS1_I_MSK 0x00000000
+#define MUL_ANS1_SFT 0
+#define MUL_ANS1_HI 31
+#define MUL_ANS1_SZ 32
+#define RD_ADDR_MSK 0x0000ffff
+#define RD_ADDR_I_MSK 0xffff0000
+#define RD_ADDR_SFT 0
+#define RD_ADDR_HI 15
+#define RD_ADDR_SZ 16
+#define RD_ID_MSK 0x007f0000
+#define RD_ID_I_MSK 0xff80ffff
+#define RD_ID_SFT 16
+#define RD_ID_HI 22
+#define RD_ID_SZ 7
+#define WR_ADDR_MSK 0x0000ffff
+#define WR_ADDR_I_MSK 0xffff0000
+#define WR_ADDR_SFT 0
+#define WR_ADDR_HI 15
+#define WR_ADDR_SZ 16
+#define WR_ID_MSK 0x007f0000
+#define WR_ID_I_MSK 0xff80ffff
+#define WR_ID_SFT 16
+#define WR_ID_HI 22
+#define WR_ID_SZ 7
+#define LEN_MSK 0x0000ffff
+#define LEN_I_MSK 0xffff0000
+#define LEN_SFT 0
+#define LEN_HI 15
+#define LEN_SZ 16
+#define CLR_MSK 0x00000001
+#define CLR_I_MSK 0xfffffffe
+#define CLR_SFT 0
+#define CLR_HI 0
+#define CLR_SZ 1
+#define PHY_MODE_MSK 0x00000003
+#define PHY_MODE_I_MSK 0xfffffffc
+#define PHY_MODE_SFT 0
+#define PHY_MODE_HI 1
+#define PHY_MODE_SZ 2
+#define SHRT_PREAM_MSK 0x00000004
+#define SHRT_PREAM_I_MSK 0xfffffffb
+#define SHRT_PREAM_SFT 2
+#define SHRT_PREAM_HI 2
+#define SHRT_PREAM_SZ 1
+#define SHRT_GI_MSK 0x00000008
+#define SHRT_GI_I_MSK 0xfffffff7
+#define SHRT_GI_SFT 3
+#define SHRT_GI_HI 3
+#define SHRT_GI_SZ 1
+#define DATA_RATE_MSK 0x000007f0
+#define DATA_RATE_I_MSK 0xfffff80f
+#define DATA_RATE_SFT 4
+#define DATA_RATE_HI 10
+#define DATA_RATE_SZ 7
+#define MCS_MSK 0x00007000
+#define MCS_I_MSK 0xffff8fff
+#define MCS_SFT 12
+#define MCS_HI 14
+#define MCS_SZ 3
+#define FRAME_LEN_MSK 0xffff0000
+#define FRAME_LEN_I_MSK 0x0000ffff
+#define FRAME_LEN_SFT 16
+#define FRAME_LEN_HI 31
+#define FRAME_LEN_SZ 16
+#define DURATION_MSK 0x0000ffff
+#define DURATION_I_MSK 0xffff0000
+#define DURATION_SFT 0
+#define DURATION_HI 15
+#define DURATION_SZ 16
+#define SHA_DST_ADDR_MSK 0xffffffff
+#define SHA_DST_ADDR_I_MSK 0x00000000
+#define SHA_DST_ADDR_SFT 0
+#define SHA_DST_ADDR_HI 31
+#define SHA_DST_ADDR_SZ 32
+#define SHA_SRC_ADDR_MSK 0xffffffff
+#define SHA_SRC_ADDR_I_MSK 0x00000000
+#define SHA_SRC_ADDR_SFT 0
+#define SHA_SRC_ADDR_HI 31
+#define SHA_SRC_ADDR_SZ 32
+#define SHA_BUSY_MSK 0x00000001
+#define SHA_BUSY_I_MSK 0xfffffffe
+#define SHA_BUSY_SFT 0
+#define SHA_BUSY_HI 0
+#define SHA_BUSY_SZ 1
+#define SHA_ENDIAN_MSK 0x00000002
+#define SHA_ENDIAN_I_MSK 0xfffffffd
+#define SHA_ENDIAN_SFT 1
+#define SHA_ENDIAN_HI 1
+#define SHA_ENDIAN_SZ 1
+#define EFS_CLKFREQ_MSK 0x00000fff
+#define EFS_CLKFREQ_I_MSK 0xfffff000
+#define EFS_CLKFREQ_SFT 0
+#define EFS_CLKFREQ_HI 11
+#define EFS_CLKFREQ_SZ 12
+#define LOW_ACTIVE_MSK 0x00010000
+#define LOW_ACTIVE_I_MSK 0xfffeffff
+#define LOW_ACTIVE_SFT 16
+#define LOW_ACTIVE_HI 16
+#define LOW_ACTIVE_SZ 1
+#define EFS_CLKFREQ_RD_MSK 0x0ff00000
+#define EFS_CLKFREQ_RD_I_MSK 0xf00fffff
+#define EFS_CLKFREQ_RD_SFT 20
+#define EFS_CLKFREQ_RD_HI 27
+#define EFS_CLKFREQ_RD_SZ 8
+#define EFS_PRE_RD_MSK 0xf0000000
+#define EFS_PRE_RD_I_MSK 0x0fffffff
+#define EFS_PRE_RD_SFT 28
+#define EFS_PRE_RD_HI 31
+#define EFS_PRE_RD_SZ 4
+#define EFS_LDO_ON_MSK 0x0000ffff
+#define EFS_LDO_ON_I_MSK 0xffff0000
+#define EFS_LDO_ON_SFT 0
+#define EFS_LDO_ON_HI 15
+#define EFS_LDO_ON_SZ 16
+#define EFS_LDO_OFF_MSK 0xffff0000
+#define EFS_LDO_OFF_I_MSK 0x0000ffff
+#define EFS_LDO_OFF_SFT 16
+#define EFS_LDO_OFF_HI 31
+#define EFS_LDO_OFF_SZ 16
+#define EFS_RDATA_0_MSK 0xffffffff
+#define EFS_RDATA_0_I_MSK 0x00000000
+#define EFS_RDATA_0_SFT 0
+#define EFS_RDATA_0_HI 31
+#define EFS_RDATA_0_SZ 32
+#define EFS_WDATA_0_MSK 0xffffffff
+#define EFS_WDATA_0_I_MSK 0x00000000
+#define EFS_WDATA_0_SFT 0
+#define EFS_WDATA_0_HI 31
+#define EFS_WDATA_0_SZ 32
+#define EFS_RDATA_1_MSK 0xffffffff
+#define EFS_RDATA_1_I_MSK 0x00000000
+#define EFS_RDATA_1_SFT 0
+#define EFS_RDATA_1_HI 31
+#define EFS_RDATA_1_SZ 32
+#define EFS_WDATA_1_MSK 0xffffffff
+#define EFS_WDATA_1_I_MSK 0x00000000
+#define EFS_WDATA_1_SFT 0
+#define EFS_WDATA_1_HI 31
+#define EFS_WDATA_1_SZ 32
+#define EFS_RDATA_2_MSK 0xffffffff
+#define EFS_RDATA_2_I_MSK 0x00000000
+#define EFS_RDATA_2_SFT 0
+#define EFS_RDATA_2_HI 31
+#define EFS_RDATA_2_SZ 32
+#define EFS_WDATA_2_MSK 0xffffffff
+#define EFS_WDATA_2_I_MSK 0x00000000
+#define EFS_WDATA_2_SFT 0
+#define EFS_WDATA_2_HI 31
+#define EFS_WDATA_2_SZ 32
+#define EFS_RDATA_3_MSK 0xffffffff
+#define EFS_RDATA_3_I_MSK 0x00000000
+#define EFS_RDATA_3_SFT 0
+#define EFS_RDATA_3_HI 31
+#define EFS_RDATA_3_SZ 32
+#define EFS_WDATA_3_MSK 0xffffffff
+#define EFS_WDATA_3_I_MSK 0x00000000
+#define EFS_WDATA_3_SFT 0
+#define EFS_WDATA_3_HI 31
+#define EFS_WDATA_3_SZ 32
+#define EFS_RDATA_4_MSK 0xffffffff
+#define EFS_RDATA_4_I_MSK 0x00000000
+#define EFS_RDATA_4_SFT 0
+#define EFS_RDATA_4_HI 31
+#define EFS_RDATA_4_SZ 32
+#define EFS_WDATA_4_MSK 0xffffffff
+#define EFS_WDATA_4_I_MSK 0x00000000
+#define EFS_WDATA_4_SFT 0
+#define EFS_WDATA_4_HI 31
+#define EFS_WDATA_4_SZ 32
+#define EFS_RDATA_5_MSK 0xffffffff
+#define EFS_RDATA_5_I_MSK 0x00000000
+#define EFS_RDATA_5_SFT 0
+#define EFS_RDATA_5_HI 31
+#define EFS_RDATA_5_SZ 32
+#define EFS_WDATA_5_MSK 0xffffffff
+#define EFS_WDATA_5_I_MSK 0x00000000
+#define EFS_WDATA_5_SFT 0
+#define EFS_WDATA_5_HI 31
+#define EFS_WDATA_5_SZ 32
+#define EFS_RDATA_6_MSK 0xffffffff
+#define EFS_RDATA_6_I_MSK 0x00000000
+#define EFS_RDATA_6_SFT 0
+#define EFS_RDATA_6_HI 31
+#define EFS_RDATA_6_SZ 32
+#define EFS_WDATA_6_MSK 0xffffffff
+#define EFS_WDATA_6_I_MSK 0x00000000
+#define EFS_WDATA_6_SFT 0
+#define EFS_WDATA_6_HI 31
+#define EFS_WDATA_6_SZ 32
+#define EFS_RDATA_7_MSK 0xffffffff
+#define EFS_RDATA_7_I_MSK 0x00000000
+#define EFS_RDATA_7_SFT 0
+#define EFS_RDATA_7_HI 31
+#define EFS_RDATA_7_SZ 32
+#define EFS_WDATA_7_MSK 0xffffffff
+#define EFS_WDATA_7_I_MSK 0x00000000
+#define EFS_WDATA_7_SFT 0
+#define EFS_WDATA_7_HI 31
+#define EFS_WDATA_7_SZ 32
+#define EFS_SPI_RD0_EN_MSK 0x00000001
+#define EFS_SPI_RD0_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD0_EN_SFT 0
+#define EFS_SPI_RD0_EN_HI 0
+#define EFS_SPI_RD0_EN_SZ 1
+#define EFS_SPI_RD1_EN_MSK 0x00000001
+#define EFS_SPI_RD1_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD1_EN_SFT 0
+#define EFS_SPI_RD1_EN_HI 0
+#define EFS_SPI_RD1_EN_SZ 1
+#define EFS_SPI_RD2_EN_MSK 0x00000001
+#define EFS_SPI_RD2_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD2_EN_SFT 0
+#define EFS_SPI_RD2_EN_HI 0
+#define EFS_SPI_RD2_EN_SZ 1
+#define EFS_SPI_RD3_EN_MSK 0x00000001
+#define EFS_SPI_RD3_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD3_EN_SFT 0
+#define EFS_SPI_RD3_EN_HI 0
+#define EFS_SPI_RD3_EN_SZ 1
+#define EFS_SPI_RD4_EN_MSK 0x00000001
+#define EFS_SPI_RD4_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD4_EN_SFT 0
+#define EFS_SPI_RD4_EN_HI 0
+#define EFS_SPI_RD4_EN_SZ 1
+#define EFS_SPI_RD5_EN_MSK 0x00000001
+#define EFS_SPI_RD5_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD5_EN_SFT 0
+#define EFS_SPI_RD5_EN_HI 0
+#define EFS_SPI_RD5_EN_SZ 1
+#define EFS_SPI_RD6_EN_MSK 0x00000001
+#define EFS_SPI_RD6_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD6_EN_SFT 0
+#define EFS_SPI_RD6_EN_HI 0
+#define EFS_SPI_RD6_EN_SZ 1
+#define EFS_SPI_RD7_EN_MSK 0x00000001
+#define EFS_SPI_RD7_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD7_EN_SFT 0
+#define EFS_SPI_RD7_EN_HI 0
+#define EFS_SPI_RD7_EN_SZ 1
+#define EFS_SPI_RBUSY_MSK 0x00000001
+#define EFS_SPI_RBUSY_I_MSK 0xfffffffe
+#define EFS_SPI_RBUSY_SFT 0
+#define EFS_SPI_RBUSY_HI 0
+#define EFS_SPI_RBUSY_SZ 1
+#define EFS_SPI_RDATA_0_MSK 0xffffffff
+#define EFS_SPI_RDATA_0_I_MSK 0x00000000
+#define EFS_SPI_RDATA_0_SFT 0
+#define EFS_SPI_RDATA_0_HI 31
+#define EFS_SPI_RDATA_0_SZ 32
+#define EFS_SPI_RDATA_1_MSK 0xffffffff
+#define EFS_SPI_RDATA_1_I_MSK 0x00000000
+#define EFS_SPI_RDATA_1_SFT 0
+#define EFS_SPI_RDATA_1_HI 31
+#define EFS_SPI_RDATA_1_SZ 32
+#define EFS_SPI_RDATA_2_MSK 0xffffffff
+#define EFS_SPI_RDATA_2_I_MSK 0x00000000
+#define EFS_SPI_RDATA_2_SFT 0
+#define EFS_SPI_RDATA_2_HI 31
+#define EFS_SPI_RDATA_2_SZ 32
+#define EFS_SPI_RDATA_3_MSK 0xffffffff
+#define EFS_SPI_RDATA_3_I_MSK 0x00000000
+#define EFS_SPI_RDATA_3_SFT 0
+#define EFS_SPI_RDATA_3_HI 31
+#define EFS_SPI_RDATA_3_SZ 32
+#define EFS_SPI_RDATA_4_MSK 0xffffffff
+#define EFS_SPI_RDATA_4_I_MSK 0x00000000
+#define EFS_SPI_RDATA_4_SFT 0
+#define EFS_SPI_RDATA_4_HI 31
+#define EFS_SPI_RDATA_4_SZ 32
+#define EFS_SPI_RDATA_5_MSK 0xffffffff
+#define EFS_SPI_RDATA_5_I_MSK 0x00000000
+#define EFS_SPI_RDATA_5_SFT 0
+#define EFS_SPI_RDATA_5_HI 31
+#define EFS_SPI_RDATA_5_SZ 32
+#define EFS_SPI_RDATA_6_MSK 0xffffffff
+#define EFS_SPI_RDATA_6_I_MSK 0x00000000
+#define EFS_SPI_RDATA_6_SFT 0
+#define EFS_SPI_RDATA_6_HI 31
+#define EFS_SPI_RDATA_6_SZ 32
+#define EFS_SPI_RDATA_7_MSK 0xffffffff
+#define EFS_SPI_RDATA_7_I_MSK 0x00000000
+#define EFS_SPI_RDATA_7_SFT 0
+#define EFS_SPI_RDATA_7_HI 31
+#define EFS_SPI_RDATA_7_SZ 32
+#define GET_RK_MSK 0x00000001
+#define GET_RK_I_MSK 0xfffffffe
+#define GET_RK_SFT 0
+#define GET_RK_HI 0
+#define GET_RK_SZ 1
+#define FORCE_GET_RK_MSK 0x00000002
+#define FORCE_GET_RK_I_MSK 0xfffffffd
+#define FORCE_GET_RK_SFT 1
+#define FORCE_GET_RK_HI 1
+#define FORCE_GET_RK_SZ 1
+#define SMS4_DESCRY_EN_MSK 0x00000010
+#define SMS4_DESCRY_EN_I_MSK 0xffffffef
+#define SMS4_DESCRY_EN_SFT 4
+#define SMS4_DESCRY_EN_HI 4
+#define SMS4_DESCRY_EN_SZ 1
+#define DEC_DOUT_MSB_MSK 0x00000001
+#define DEC_DOUT_MSB_I_MSK 0xfffffffe
+#define DEC_DOUT_MSB_SFT 0
+#define DEC_DOUT_MSB_HI 0
+#define DEC_DOUT_MSB_SZ 1
+#define DEC_DIN_MSB_MSK 0x00000002
+#define DEC_DIN_MSB_I_MSK 0xfffffffd
+#define DEC_DIN_MSB_SFT 1
+#define DEC_DIN_MSB_HI 1
+#define DEC_DIN_MSB_SZ 1
+#define ENC_DOUT_MSB_MSK 0x00000004
+#define ENC_DOUT_MSB_I_MSK 0xfffffffb
+#define ENC_DOUT_MSB_SFT 2
+#define ENC_DOUT_MSB_HI 2
+#define ENC_DOUT_MSB_SZ 1
+#define ENC_DIN_MSB_MSK 0x00000008
+#define ENC_DIN_MSB_I_MSK 0xfffffff7
+#define ENC_DIN_MSB_SFT 3
+#define ENC_DIN_MSB_HI 3
+#define ENC_DIN_MSB_SZ 1
+#define KEY_DIN_MSB_MSK 0x00000010
+#define KEY_DIN_MSB_I_MSK 0xffffffef
+#define KEY_DIN_MSB_SFT 4
+#define KEY_DIN_MSB_HI 4
+#define KEY_DIN_MSB_SZ 1
+#define SMS4_CBC_EN_MSK 0x00000001
+#define SMS4_CBC_EN_I_MSK 0xfffffffe
+#define SMS4_CBC_EN_SFT 0
+#define SMS4_CBC_EN_HI 0
+#define SMS4_CBC_EN_SZ 1
+#define SMS4_CFB_EN_MSK 0x00000002
+#define SMS4_CFB_EN_I_MSK 0xfffffffd
+#define SMS4_CFB_EN_SFT 1
+#define SMS4_CFB_EN_HI 1
+#define SMS4_CFB_EN_SZ 1
+#define SMS4_OFB_EN_MSK 0x00000004
+#define SMS4_OFB_EN_I_MSK 0xfffffffb
+#define SMS4_OFB_EN_SFT 2
+#define SMS4_OFB_EN_HI 2
+#define SMS4_OFB_EN_SZ 1
+#define SMS4_START_TRIG_MSK 0x00000001
+#define SMS4_START_TRIG_I_MSK 0xfffffffe
+#define SMS4_START_TRIG_SFT 0
+#define SMS4_START_TRIG_HI 0
+#define SMS4_START_TRIG_SZ 1
+#define SMS4_BUSY_MSK 0x00000001
+#define SMS4_BUSY_I_MSK 0xfffffffe
+#define SMS4_BUSY_SFT 0
+#define SMS4_BUSY_HI 0
+#define SMS4_BUSY_SZ 1
+#define SMS4_DONE_MSK 0x00000001
+#define SMS4_DONE_I_MSK 0xfffffffe
+#define SMS4_DONE_SFT 0
+#define SMS4_DONE_HI 0
+#define SMS4_DONE_SZ 1
+#define SMS4_DATAIN_0_MSK 0xffffffff
+#define SMS4_DATAIN_0_I_MSK 0x00000000
+#define SMS4_DATAIN_0_SFT 0
+#define SMS4_DATAIN_0_HI 31
+#define SMS4_DATAIN_0_SZ 32
+#define SMS4_DATAIN_1_MSK 0xffffffff
+#define SMS4_DATAIN_1_I_MSK 0x00000000
+#define SMS4_DATAIN_1_SFT 0
+#define SMS4_DATAIN_1_HI 31
+#define SMS4_DATAIN_1_SZ 32
+#define SMS4_DATAIN_2_MSK 0xffffffff
+#define SMS4_DATAIN_2_I_MSK 0x00000000
+#define SMS4_DATAIN_2_SFT 0
+#define SMS4_DATAIN_2_HI 31
+#define SMS4_DATAIN_2_SZ 32
+#define SMS4_DATAIN_3_MSK 0xffffffff
+#define SMS4_DATAIN_3_I_MSK 0x00000000
+#define SMS4_DATAIN_3_SFT 0
+#define SMS4_DATAIN_3_HI 31
+#define SMS4_DATAIN_3_SZ 32
+#define SMS4_DATAOUT_0_MSK 0xffffffff
+#define SMS4_DATAOUT_0_I_MSK 0x00000000
+#define SMS4_DATAOUT_0_SFT 0
+#define SMS4_DATAOUT_0_HI 31
+#define SMS4_DATAOUT_0_SZ 32
+#define SMS4_DATAOUT_1_MSK 0xffffffff
+#define SMS4_DATAOUT_1_I_MSK 0x00000000
+#define SMS4_DATAOUT_1_SFT 0
+#define SMS4_DATAOUT_1_HI 31
+#define SMS4_DATAOUT_1_SZ 32
+#define SMS4_DATAOUT_2_MSK 0xffffffff
+#define SMS4_DATAOUT_2_I_MSK 0x00000000
+#define SMS4_DATAOUT_2_SFT 0
+#define SMS4_DATAOUT_2_HI 31
+#define SMS4_DATAOUT_2_SZ 32
+#define SMS4_DATAOUT_3_MSK 0xffffffff
+#define SMS4_DATAOUT_3_I_MSK 0x00000000
+#define SMS4_DATAOUT_3_SFT 0
+#define SMS4_DATAOUT_3_HI 31
+#define SMS4_DATAOUT_3_SZ 32
+#define SMS4_KEY_0_MSK 0xffffffff
+#define SMS4_KEY_0_I_MSK 0x00000000
+#define SMS4_KEY_0_SFT 0
+#define SMS4_KEY_0_HI 31
+#define SMS4_KEY_0_SZ 32
+#define SMS4_KEY_1_MSK 0xffffffff
+#define SMS4_KEY_1_I_MSK 0x00000000
+#define SMS4_KEY_1_SFT 0
+#define SMS4_KEY_1_HI 31
+#define SMS4_KEY_1_SZ 32
+#define SMS4_KEY_2_MSK 0xffffffff
+#define SMS4_KEY_2_I_MSK 0x00000000
+#define SMS4_KEY_2_SFT 0
+#define SMS4_KEY_2_HI 31
+#define SMS4_KEY_2_SZ 32
+#define SMS4_KEY_3_MSK 0xffffffff
+#define SMS4_KEY_3_I_MSK 0x00000000
+#define SMS4_KEY_3_SFT 0
+#define SMS4_KEY_3_HI 31
+#define SMS4_KEY_3_SZ 32
+#define SMS4_MODE_IV0_MSK 0xffffffff
+#define SMS4_MODE_IV0_I_MSK 0x00000000
+#define SMS4_MODE_IV0_SFT 0
+#define SMS4_MODE_IV0_HI 31
+#define SMS4_MODE_IV0_SZ 32
+#define SMS4_MODE_IV1_MSK 0xffffffff
+#define SMS4_MODE_IV1_I_MSK 0x00000000
+#define SMS4_MODE_IV1_SFT 0
+#define SMS4_MODE_IV1_HI 31
+#define SMS4_MODE_IV1_SZ 32
+#define SMS4_MODE_IV2_MSK 0xffffffff
+#define SMS4_MODE_IV2_I_MSK 0x00000000
+#define SMS4_MODE_IV2_SFT 0
+#define SMS4_MODE_IV2_HI 31
+#define SMS4_MODE_IV2_SZ 32
+#define SMS4_MODE_IV3_MSK 0xffffffff
+#define SMS4_MODE_IV3_I_MSK 0x00000000
+#define SMS4_MODE_IV3_SFT 0
+#define SMS4_MODE_IV3_HI 31
+#define SMS4_MODE_IV3_SZ 32
+#define SMS4_OFB_ENC0_MSK 0xffffffff
+#define SMS4_OFB_ENC0_I_MSK 0x00000000
+#define SMS4_OFB_ENC0_SFT 0
+#define SMS4_OFB_ENC0_HI 31
+#define SMS4_OFB_ENC0_SZ 32
+#define SMS4_OFB_ENC1_MSK 0xffffffff
+#define SMS4_OFB_ENC1_I_MSK 0x00000000
+#define SMS4_OFB_ENC1_SFT 0
+#define SMS4_OFB_ENC1_HI 31
+#define SMS4_OFB_ENC1_SZ 32
+#define SMS4_OFB_ENC2_MSK 0xffffffff
+#define SMS4_OFB_ENC2_I_MSK 0x00000000
+#define SMS4_OFB_ENC2_SFT 0
+#define SMS4_OFB_ENC2_HI 31
+#define SMS4_OFB_ENC2_SZ 32
+#define SMS4_OFB_ENC3_MSK 0xffffffff
+#define SMS4_OFB_ENC3_I_MSK 0x00000000
+#define SMS4_OFB_ENC3_SFT 0
+#define SMS4_OFB_ENC3_HI 31
+#define SMS4_OFB_ENC3_SZ 32
+#define MRX_MCAST_TB0_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB0_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB0_31_0_SFT 0
+#define MRX_MCAST_TB0_31_0_HI 31
+#define MRX_MCAST_TB0_31_0_SZ 32
+#define MRX_MCAST_TB0_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB0_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB0_47_32_SFT 0
+#define MRX_MCAST_TB0_47_32_HI 15
+#define MRX_MCAST_TB0_47_32_SZ 16
+#define MRX_MCAST_MASK0_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK0_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK0_31_0_SFT 0
+#define MRX_MCAST_MASK0_31_0_HI 31
+#define MRX_MCAST_MASK0_31_0_SZ 32
+#define MRX_MCAST_MASK0_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK0_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK0_47_32_SFT 0
+#define MRX_MCAST_MASK0_47_32_HI 15
+#define MRX_MCAST_MASK0_47_32_SZ 16
+#define MRX_MCAST_CTRL_0_MSK 0x00000003
+#define MRX_MCAST_CTRL_0_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_0_SFT 0
+#define MRX_MCAST_CTRL_0_HI 1
+#define MRX_MCAST_CTRL_0_SZ 2
+#define MRX_MCAST_TB1_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB1_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB1_31_0_SFT 0
+#define MRX_MCAST_TB1_31_0_HI 31
+#define MRX_MCAST_TB1_31_0_SZ 32
+#define MRX_MCAST_TB1_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB1_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB1_47_32_SFT 0
+#define MRX_MCAST_TB1_47_32_HI 15
+#define MRX_MCAST_TB1_47_32_SZ 16
+#define MRX_MCAST_MASK1_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK1_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK1_31_0_SFT 0
+#define MRX_MCAST_MASK1_31_0_HI 31
+#define MRX_MCAST_MASK1_31_0_SZ 32
+#define MRX_MCAST_MASK1_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK1_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK1_47_32_SFT 0
+#define MRX_MCAST_MASK1_47_32_HI 15
+#define MRX_MCAST_MASK1_47_32_SZ 16
+#define MRX_MCAST_CTRL_1_MSK 0x00000003
+#define MRX_MCAST_CTRL_1_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_1_SFT 0
+#define MRX_MCAST_CTRL_1_HI 1
+#define MRX_MCAST_CTRL_1_SZ 2
+#define MRX_MCAST_TB2_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB2_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB2_31_0_SFT 0
+#define MRX_MCAST_TB2_31_0_HI 31
+#define MRX_MCAST_TB2_31_0_SZ 32
+#define MRX_MCAST_TB2_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB2_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB2_47_32_SFT 0
+#define MRX_MCAST_TB2_47_32_HI 15
+#define MRX_MCAST_TB2_47_32_SZ 16
+#define MRX_MCAST_MASK2_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK2_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK2_31_0_SFT 0
+#define MRX_MCAST_MASK2_31_0_HI 31
+#define MRX_MCAST_MASK2_31_0_SZ 32
+#define MRX_MCAST_MASK2_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK2_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK2_47_32_SFT 0
+#define MRX_MCAST_MASK2_47_32_HI 15
+#define MRX_MCAST_MASK2_47_32_SZ 16
+#define MRX_MCAST_CTRL_2_MSK 0x00000003
+#define MRX_MCAST_CTRL_2_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_2_SFT 0
+#define MRX_MCAST_CTRL_2_HI 1
+#define MRX_MCAST_CTRL_2_SZ 2
+#define MRX_MCAST_TB3_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB3_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB3_31_0_SFT 0
+#define MRX_MCAST_TB3_31_0_HI 31
+#define MRX_MCAST_TB3_31_0_SZ 32
+#define MRX_MCAST_TB3_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB3_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB3_47_32_SFT 0
+#define MRX_MCAST_TB3_47_32_HI 15
+#define MRX_MCAST_TB3_47_32_SZ 16
+#define MRX_MCAST_MASK3_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK3_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK3_31_0_SFT 0
+#define MRX_MCAST_MASK3_31_0_HI 31
+#define MRX_MCAST_MASK3_31_0_SZ 32
+#define MRX_MCAST_MASK3_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK3_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK3_47_32_SFT 0
+#define MRX_MCAST_MASK3_47_32_HI 15
+#define MRX_MCAST_MASK3_47_32_SZ 16
+#define MRX_MCAST_CTRL_3_MSK 0x00000003
+#define MRX_MCAST_CTRL_3_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_3_SFT 0
+#define MRX_MCAST_CTRL_3_HI 1
+#define MRX_MCAST_CTRL_3_SZ 2
+#define MRX_PHY_INFO_MSK 0xffffffff
+#define MRX_PHY_INFO_I_MSK 0x00000000
+#define MRX_PHY_INFO_SFT 0
+#define MRX_PHY_INFO_HI 31
+#define MRX_PHY_INFO_SZ 32
+#define DBG_BA_TYPE_MSK 0x0000003f
+#define DBG_BA_TYPE_I_MSK 0xffffffc0
+#define DBG_BA_TYPE_SFT 0
+#define DBG_BA_TYPE_HI 5
+#define DBG_BA_TYPE_SZ 6
+#define DBG_BA_SEQ_MSK 0x000fff00
+#define DBG_BA_SEQ_I_MSK 0xfff000ff
+#define DBG_BA_SEQ_SFT 8
+#define DBG_BA_SEQ_HI 19
+#define DBG_BA_SEQ_SZ 12
+#define MRX_FLT_TB0_MSK 0x00007fff
+#define MRX_FLT_TB0_I_MSK 0xffff8000
+#define MRX_FLT_TB0_SFT 0
+#define MRX_FLT_TB0_HI 14
+#define MRX_FLT_TB0_SZ 15
+#define MRX_FLT_TB1_MSK 0x00007fff
+#define MRX_FLT_TB1_I_MSK 0xffff8000
+#define MRX_FLT_TB1_SFT 0
+#define MRX_FLT_TB1_HI 14
+#define MRX_FLT_TB1_SZ 15
+#define MRX_FLT_TB2_MSK 0x00007fff
+#define MRX_FLT_TB2_I_MSK 0xffff8000
+#define MRX_FLT_TB2_SFT 0
+#define MRX_FLT_TB2_HI 14
+#define MRX_FLT_TB2_SZ 15
+#define MRX_FLT_TB3_MSK 0x00007fff
+#define MRX_FLT_TB3_I_MSK 0xffff8000
+#define MRX_FLT_TB3_SFT 0
+#define MRX_FLT_TB3_HI 14
+#define MRX_FLT_TB3_SZ 15
+#define MRX_FLT_TB4_MSK 0x00007fff
+#define MRX_FLT_TB4_I_MSK 0xffff8000
+#define MRX_FLT_TB4_SFT 0
+#define MRX_FLT_TB4_HI 14
+#define MRX_FLT_TB4_SZ 15
+#define MRX_FLT_TB5_MSK 0x00007fff
+#define MRX_FLT_TB5_I_MSK 0xffff8000
+#define MRX_FLT_TB5_SFT 0
+#define MRX_FLT_TB5_HI 14
+#define MRX_FLT_TB5_SZ 15
+#define MRX_FLT_TB6_MSK 0x00007fff
+#define MRX_FLT_TB6_I_MSK 0xffff8000
+#define MRX_FLT_TB6_SFT 0
+#define MRX_FLT_TB6_HI 14
+#define MRX_FLT_TB6_SZ 15
+#define MRX_FLT_TB7_MSK 0x00007fff
+#define MRX_FLT_TB7_I_MSK 0xffff8000
+#define MRX_FLT_TB7_SFT 0
+#define MRX_FLT_TB7_HI 14
+#define MRX_FLT_TB7_SZ 15
+#define MRX_FLT_TB8_MSK 0x00007fff
+#define MRX_FLT_TB8_I_MSK 0xffff8000
+#define MRX_FLT_TB8_SFT 0
+#define MRX_FLT_TB8_HI 14
+#define MRX_FLT_TB8_SZ 15
+#define MRX_FLT_TB9_MSK 0x00007fff
+#define MRX_FLT_TB9_I_MSK 0xffff8000
+#define MRX_FLT_TB9_SFT 0
+#define MRX_FLT_TB9_HI 14
+#define MRX_FLT_TB9_SZ 15
+#define MRX_FLT_TB10_MSK 0x00007fff
+#define MRX_FLT_TB10_I_MSK 0xffff8000
+#define MRX_FLT_TB10_SFT 0
+#define MRX_FLT_TB10_HI 14
+#define MRX_FLT_TB10_SZ 15
+#define MRX_FLT_TB11_MSK 0x00007fff
+#define MRX_FLT_TB11_I_MSK 0xffff8000
+#define MRX_FLT_TB11_SFT 0
+#define MRX_FLT_TB11_HI 14
+#define MRX_FLT_TB11_SZ 15
+#define MRX_FLT_TB12_MSK 0x00007fff
+#define MRX_FLT_TB12_I_MSK 0xffff8000
+#define MRX_FLT_TB12_SFT 0
+#define MRX_FLT_TB12_HI 14
+#define MRX_FLT_TB12_SZ 15
+#define MRX_FLT_TB13_MSK 0x00007fff
+#define MRX_FLT_TB13_I_MSK 0xffff8000
+#define MRX_FLT_TB13_SFT 0
+#define MRX_FLT_TB13_HI 14
+#define MRX_FLT_TB13_SZ 15
+#define MRX_FLT_TB14_MSK 0x00007fff
+#define MRX_FLT_TB14_I_MSK 0xffff8000
+#define MRX_FLT_TB14_SFT 0
+#define MRX_FLT_TB14_HI 14
+#define MRX_FLT_TB14_SZ 15
+#define MRX_FLT_TB15_MSK 0x00007fff
+#define MRX_FLT_TB15_I_MSK 0xffff8000
+#define MRX_FLT_TB15_SFT 0
+#define MRX_FLT_TB15_HI 14
+#define MRX_FLT_TB15_SZ 15
+#define MRX_FLT_EN0_MSK 0x0000ffff
+#define MRX_FLT_EN0_I_MSK 0xffff0000
+#define MRX_FLT_EN0_SFT 0
+#define MRX_FLT_EN0_HI 15
+#define MRX_FLT_EN0_SZ 16
+#define MRX_FLT_EN1_MSK 0x0000ffff
+#define MRX_FLT_EN1_I_MSK 0xffff0000
+#define MRX_FLT_EN1_SFT 0
+#define MRX_FLT_EN1_HI 15
+#define MRX_FLT_EN1_SZ 16
+#define MRX_FLT_EN2_MSK 0x0000ffff
+#define MRX_FLT_EN2_I_MSK 0xffff0000
+#define MRX_FLT_EN2_SFT 0
+#define MRX_FLT_EN2_HI 15
+#define MRX_FLT_EN2_SZ 16
+#define MRX_FLT_EN3_MSK 0x0000ffff
+#define MRX_FLT_EN3_I_MSK 0xffff0000
+#define MRX_FLT_EN3_SFT 0
+#define MRX_FLT_EN3_HI 15
+#define MRX_FLT_EN3_SZ 16
+#define MRX_FLT_EN4_MSK 0x0000ffff
+#define MRX_FLT_EN4_I_MSK 0xffff0000
+#define MRX_FLT_EN4_SFT 0
+#define MRX_FLT_EN4_HI 15
+#define MRX_FLT_EN4_SZ 16
+#define MRX_FLT_EN5_MSK 0x0000ffff
+#define MRX_FLT_EN5_I_MSK 0xffff0000
+#define MRX_FLT_EN5_SFT 0
+#define MRX_FLT_EN5_HI 15
+#define MRX_FLT_EN5_SZ 16
+#define MRX_FLT_EN6_MSK 0x0000ffff
+#define MRX_FLT_EN6_I_MSK 0xffff0000
+#define MRX_FLT_EN6_SFT 0
+#define MRX_FLT_EN6_HI 15
+#define MRX_FLT_EN6_SZ 16
+#define MRX_FLT_EN7_MSK 0x0000ffff
+#define MRX_FLT_EN7_I_MSK 0xffff0000
+#define MRX_FLT_EN7_SFT 0
+#define MRX_FLT_EN7_HI 15
+#define MRX_FLT_EN7_SZ 16
+#define MRX_FLT_EN8_MSK 0x0000ffff
+#define MRX_FLT_EN8_I_MSK 0xffff0000
+#define MRX_FLT_EN8_SFT 0
+#define MRX_FLT_EN8_HI 15
+#define MRX_FLT_EN8_SZ 16
+#define MRX_LEN_FLT_MSK 0x0000ffff
+#define MRX_LEN_FLT_I_MSK 0xffff0000
+#define MRX_LEN_FLT_SFT 0
+#define MRX_LEN_FLT_HI 15
+#define MRX_LEN_FLT_SZ 16
+#define RX_FLOW_DATA_MSK 0xffffffff
+#define RX_FLOW_DATA_I_MSK 0x00000000
+#define RX_FLOW_DATA_SFT 0
+#define RX_FLOW_DATA_HI 31
+#define RX_FLOW_DATA_SZ 32
+#define RX_FLOW_MNG_MSK 0x0000ffff
+#define RX_FLOW_MNG_I_MSK 0xffff0000
+#define RX_FLOW_MNG_SFT 0
+#define RX_FLOW_MNG_HI 15
+#define RX_FLOW_MNG_SZ 16
+#define RX_FLOW_CTRL_MSK 0x0000ffff
+#define RX_FLOW_CTRL_I_MSK 0xffff0000
+#define RX_FLOW_CTRL_SFT 0
+#define RX_FLOW_CTRL_HI 15
+#define RX_FLOW_CTRL_SZ 16
+#define MRX_STP_EN_MSK 0x00000001
+#define MRX_STP_EN_I_MSK 0xfffffffe
+#define MRX_STP_EN_SFT 0
+#define MRX_STP_EN_HI 0
+#define MRX_STP_EN_SZ 1
+#define MRX_STP_OFST_MSK 0x0000ff00
+#define MRX_STP_OFST_I_MSK 0xffff00ff
+#define MRX_STP_OFST_SFT 8
+#define MRX_STP_OFST_HI 15
+#define MRX_STP_OFST_SZ 8
+#define DBG_FF_FULL_MSK 0x0000ffff
+#define DBG_FF_FULL_I_MSK 0xffff0000
+#define DBG_FF_FULL_SFT 0
+#define DBG_FF_FULL_HI 15
+#define DBG_FF_FULL_SZ 16
+#define DBG_FF_FULL_CLR_MSK 0x80000000
+#define DBG_FF_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_FF_FULL_CLR_SFT 31
+#define DBG_FF_FULL_CLR_HI 31
+#define DBG_FF_FULL_CLR_SZ 1
+#define DBG_WFF_FULL_MSK 0x0000ffff
+#define DBG_WFF_FULL_I_MSK 0xffff0000
+#define DBG_WFF_FULL_SFT 0
+#define DBG_WFF_FULL_HI 15
+#define DBG_WFF_FULL_SZ 16
+#define DBG_WFF_FULL_CLR_MSK 0x80000000
+#define DBG_WFF_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_WFF_FULL_CLR_SFT 31
+#define DBG_WFF_FULL_CLR_HI 31
+#define DBG_WFF_FULL_CLR_SZ 1
+#define DBG_MB_FULL_MSK 0x0000ffff
+#define DBG_MB_FULL_I_MSK 0xffff0000
+#define DBG_MB_FULL_SFT 0
+#define DBG_MB_FULL_HI 15
+#define DBG_MB_FULL_SZ 16
+#define DBG_MB_FULL_CLR_MSK 0x80000000
+#define DBG_MB_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_MB_FULL_CLR_SFT 31
+#define DBG_MB_FULL_CLR_HI 31
+#define DBG_MB_FULL_CLR_SZ 1
+#define BA_CTRL_MSK 0x00000003
+#define BA_CTRL_I_MSK 0xfffffffc
+#define BA_CTRL_SFT 0
+#define BA_CTRL_HI 1
+#define BA_CTRL_SZ 2
+#define BA_DBG_EN_MSK 0x00000004
+#define BA_DBG_EN_I_MSK 0xfffffffb
+#define BA_DBG_EN_SFT 2
+#define BA_DBG_EN_HI 2
+#define BA_DBG_EN_SZ 1
+#define BA_AGRE_EN_MSK 0x00000008
+#define BA_AGRE_EN_I_MSK 0xfffffff7
+#define BA_AGRE_EN_SFT 3
+#define BA_AGRE_EN_HI 3
+#define BA_AGRE_EN_SZ 1
+#define BA_TA_31_0_MSK 0xffffffff
+#define BA_TA_31_0_I_MSK 0x00000000
+#define BA_TA_31_0_SFT 0
+#define BA_TA_31_0_HI 31
+#define BA_TA_31_0_SZ 32
+#define BA_TA_47_32_MSK 0x0000ffff
+#define BA_TA_47_32_I_MSK 0xffff0000
+#define BA_TA_47_32_SFT 0
+#define BA_TA_47_32_HI 15
+#define BA_TA_47_32_SZ 16
+#define BA_TID_MSK 0x0000000f
+#define BA_TID_I_MSK 0xfffffff0
+#define BA_TID_SFT 0
+#define BA_TID_HI 3
+#define BA_TID_SZ 4
+#define BA_ST_SEQ_MSK 0x00000fff
+#define BA_ST_SEQ_I_MSK 0xfffff000
+#define BA_ST_SEQ_SFT 0
+#define BA_ST_SEQ_HI 11
+#define BA_ST_SEQ_SZ 12
+#define BA_SB0_MSK 0xffffffff
+#define BA_SB0_I_MSK 0x00000000
+#define BA_SB0_SFT 0
+#define BA_SB0_HI 31
+#define BA_SB0_SZ 32
+#define BA_SB1_MSK 0xffffffff
+#define BA_SB1_I_MSK 0x00000000
+#define BA_SB1_SFT 0
+#define BA_SB1_HI 31
+#define BA_SB1_SZ 32
+#define MRX_WD_MSK 0x0001ffff
+#define MRX_WD_I_MSK 0xfffe0000
+#define MRX_WD_SFT 0
+#define MRX_WD_HI 16
+#define MRX_WD_SZ 17
+#define ACK_GEN_EN_MSK 0x00000001
+#define ACK_GEN_EN_I_MSK 0xfffffffe
+#define ACK_GEN_EN_SFT 0
+#define ACK_GEN_EN_HI 0
+#define ACK_GEN_EN_SZ 1
+#define BA_GEN_EN_MSK 0x00000002
+#define BA_GEN_EN_I_MSK 0xfffffffd
+#define BA_GEN_EN_SFT 1
+#define BA_GEN_EN_HI 1
+#define BA_GEN_EN_SZ 1
+#define ACK_GEN_DUR_MSK 0x0000ffff
+#define ACK_GEN_DUR_I_MSK 0xffff0000
+#define ACK_GEN_DUR_SFT 0
+#define ACK_GEN_DUR_HI 15
+#define ACK_GEN_DUR_SZ 16
+#define ACK_GEN_INFO_MSK 0x003f0000
+#define ACK_GEN_INFO_I_MSK 0xffc0ffff
+#define ACK_GEN_INFO_SFT 16
+#define ACK_GEN_INFO_HI 21
+#define ACK_GEN_INFO_SZ 6
+#define ACK_GEN_RA_31_0_MSK 0xffffffff
+#define ACK_GEN_RA_31_0_I_MSK 0x00000000
+#define ACK_GEN_RA_31_0_SFT 0
+#define ACK_GEN_RA_31_0_HI 31
+#define ACK_GEN_RA_31_0_SZ 32
+#define ACK_GEN_RA_47_32_MSK 0x0000ffff
+#define ACK_GEN_RA_47_32_I_MSK 0xffff0000
+#define ACK_GEN_RA_47_32_SFT 0
+#define ACK_GEN_RA_47_32_HI 15
+#define ACK_GEN_RA_47_32_SZ 16
+#define MIB_LEN_FAIL_MSK 0x0000ffff
+#define MIB_LEN_FAIL_I_MSK 0xffff0000
+#define MIB_LEN_FAIL_SFT 0
+#define MIB_LEN_FAIL_HI 15
+#define MIB_LEN_FAIL_SZ 16
+#define TRAP_HW_ID_MSK 0x0000000f
+#define TRAP_HW_ID_I_MSK 0xfffffff0
+#define TRAP_HW_ID_SFT 0
+#define TRAP_HW_ID_HI 3
+#define TRAP_HW_ID_SZ 4
+#define ID_IN_USE_MSK 0x000000ff
+#define ID_IN_USE_I_MSK 0xffffff00
+#define ID_IN_USE_SFT 0
+#define ID_IN_USE_HI 7
+#define ID_IN_USE_SZ 8
+#define MRX_ERR_MSK 0xffffffff
+#define MRX_ERR_I_MSK 0x00000000
+#define MRX_ERR_SFT 0
+#define MRX_ERR_HI 31
+#define MRX_ERR_SZ 32
+#define W0_T0_SEQ_MSK 0x0000ffff
+#define W0_T0_SEQ_I_MSK 0xffff0000
+#define W0_T0_SEQ_SFT 0
+#define W0_T0_SEQ_HI 15
+#define W0_T0_SEQ_SZ 16
+#define W0_T1_SEQ_MSK 0x0000ffff
+#define W0_T1_SEQ_I_MSK 0xffff0000
+#define W0_T1_SEQ_SFT 0
+#define W0_T1_SEQ_HI 15
+#define W0_T1_SEQ_SZ 16
+#define W0_T2_SEQ_MSK 0x0000ffff
+#define W0_T2_SEQ_I_MSK 0xffff0000
+#define W0_T2_SEQ_SFT 0
+#define W0_T2_SEQ_HI 15
+#define W0_T2_SEQ_SZ 16
+#define W0_T3_SEQ_MSK 0x0000ffff
+#define W0_T3_SEQ_I_MSK 0xffff0000
+#define W0_T3_SEQ_SFT 0
+#define W0_T3_SEQ_HI 15
+#define W0_T3_SEQ_SZ 16
+#define W0_T4_SEQ_MSK 0x0000ffff
+#define W0_T4_SEQ_I_MSK 0xffff0000
+#define W0_T4_SEQ_SFT 0
+#define W0_T4_SEQ_HI 15
+#define W0_T4_SEQ_SZ 16
+#define W0_T5_SEQ_MSK 0x0000ffff
+#define W0_T5_SEQ_I_MSK 0xffff0000
+#define W0_T5_SEQ_SFT 0
+#define W0_T5_SEQ_HI 15
+#define W0_T5_SEQ_SZ 16
+#define W0_T6_SEQ_MSK 0x0000ffff
+#define W0_T6_SEQ_I_MSK 0xffff0000
+#define W0_T6_SEQ_SFT 0
+#define W0_T6_SEQ_HI 15
+#define W0_T6_SEQ_SZ 16
+#define W0_T7_SEQ_MSK 0x0000ffff
+#define W0_T7_SEQ_I_MSK 0xffff0000
+#define W0_T7_SEQ_SFT 0
+#define W0_T7_SEQ_HI 15
+#define W0_T7_SEQ_SZ 16
+#define W1_T0_SEQ_MSK 0x0000ffff
+#define W1_T0_SEQ_I_MSK 0xffff0000
+#define W1_T0_SEQ_SFT 0
+#define W1_T0_SEQ_HI 15
+#define W1_T0_SEQ_SZ 16
+#define W1_T1_SEQ_MSK 0x0000ffff
+#define W1_T1_SEQ_I_MSK 0xffff0000
+#define W1_T1_SEQ_SFT 0
+#define W1_T1_SEQ_HI 15
+#define W1_T1_SEQ_SZ 16
+#define W1_T2_SEQ_MSK 0x0000ffff
+#define W1_T2_SEQ_I_MSK 0xffff0000
+#define W1_T2_SEQ_SFT 0
+#define W1_T2_SEQ_HI 15
+#define W1_T2_SEQ_SZ 16
+#define W1_T3_SEQ_MSK 0x0000ffff
+#define W1_T3_SEQ_I_MSK 0xffff0000
+#define W1_T3_SEQ_SFT 0
+#define W1_T3_SEQ_HI 15
+#define W1_T3_SEQ_SZ 16
+#define W1_T4_SEQ_MSK 0x0000ffff
+#define W1_T4_SEQ_I_MSK 0xffff0000
+#define W1_T4_SEQ_SFT 0
+#define W1_T4_SEQ_HI 15
+#define W1_T4_SEQ_SZ 16
+#define W1_T5_SEQ_MSK 0x0000ffff
+#define W1_T5_SEQ_I_MSK 0xffff0000
+#define W1_T5_SEQ_SFT 0
+#define W1_T5_SEQ_HI 15
+#define W1_T5_SEQ_SZ 16
+#define W1_T6_SEQ_MSK 0x0000ffff
+#define W1_T6_SEQ_I_MSK 0xffff0000
+#define W1_T6_SEQ_SFT 0
+#define W1_T6_SEQ_HI 15
+#define W1_T6_SEQ_SZ 16
+#define W1_T7_SEQ_MSK 0x0000ffff
+#define W1_T7_SEQ_I_MSK 0xffff0000
+#define W1_T7_SEQ_SFT 0
+#define W1_T7_SEQ_HI 15
+#define W1_T7_SEQ_SZ 16
+#define ADDR1A_SEL_MSK 0x00000003
+#define ADDR1A_SEL_I_MSK 0xfffffffc
+#define ADDR1A_SEL_SFT 0
+#define ADDR1A_SEL_HI 1
+#define ADDR1A_SEL_SZ 2
+#define ADDR2A_SEL_MSK 0x0000000c
+#define ADDR2A_SEL_I_MSK 0xfffffff3
+#define ADDR2A_SEL_SFT 2
+#define ADDR2A_SEL_HI 3
+#define ADDR2A_SEL_SZ 2
+#define ADDR3A_SEL_MSK 0x00000030
+#define ADDR3A_SEL_I_MSK 0xffffffcf
+#define ADDR3A_SEL_SFT 4
+#define ADDR3A_SEL_HI 5
+#define ADDR3A_SEL_SZ 2
+#define ADDR1B_SEL_MSK 0x000000c0
+#define ADDR1B_SEL_I_MSK 0xffffff3f
+#define ADDR1B_SEL_SFT 6
+#define ADDR1B_SEL_HI 7
+#define ADDR1B_SEL_SZ 2
+#define ADDR2B_SEL_MSK 0x00000300
+#define ADDR2B_SEL_I_MSK 0xfffffcff
+#define ADDR2B_SEL_SFT 8
+#define ADDR2B_SEL_HI 9
+#define ADDR2B_SEL_SZ 2
+#define ADDR3B_SEL_MSK 0x00000c00
+#define ADDR3B_SEL_I_MSK 0xfffff3ff
+#define ADDR3B_SEL_SFT 10
+#define ADDR3B_SEL_HI 11
+#define ADDR3B_SEL_SZ 2
+#define ADDR3C_SEL_MSK 0x00003000
+#define ADDR3C_SEL_I_MSK 0xffffcfff
+#define ADDR3C_SEL_SFT 12
+#define ADDR3C_SEL_HI 13
+#define ADDR3C_SEL_SZ 2
+#define FRM_CTRL_MSK 0x0000003f
+#define FRM_CTRL_I_MSK 0xffffffc0
+#define FRM_CTRL_SFT 0
+#define FRM_CTRL_HI 5
+#define FRM_CTRL_SZ 6
+#define CSR_PHY_INFO_MSK 0x00007fff
+#define CSR_PHY_INFO_I_MSK 0xffff8000
+#define CSR_PHY_INFO_SFT 0
+#define CSR_PHY_INFO_HI 14
+#define CSR_PHY_INFO_SZ 15
+#define AMPDU_SIG_MSK 0x000000ff
+#define AMPDU_SIG_I_MSK 0xffffff00
+#define AMPDU_SIG_SFT 0
+#define AMPDU_SIG_HI 7
+#define AMPDU_SIG_SZ 8
+#define MIB_AMPDU_MSK 0xffffffff
+#define MIB_AMPDU_I_MSK 0x00000000
+#define MIB_AMPDU_SFT 0
+#define MIB_AMPDU_HI 31
+#define MIB_AMPDU_SZ 32
+#define LEN_FLT_MSK 0x0000ffff
+#define LEN_FLT_I_MSK 0xffff0000
+#define LEN_FLT_SFT 0
+#define LEN_FLT_HI 15
+#define LEN_FLT_SZ 16
+#define MIB_DELIMITER_MSK 0x0000ffff
+#define MIB_DELIMITER_I_MSK 0xffff0000
+#define MIB_DELIMITER_SFT 0
+#define MIB_DELIMITER_HI 15
+#define MIB_DELIMITER_SZ 16
+#define MTX_INT_Q0_Q_EMPTY_MSK 0x00010000
+#define MTX_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
+#define MTX_INT_Q0_Q_EMPTY_SFT 16
+#define MTX_INT_Q0_Q_EMPTY_HI 16
+#define MTX_INT_Q0_Q_EMPTY_SZ 1
+#define MTX_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
+#define MTX_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
+#define MTX_INT_Q0_TXOP_RUNOUT_SFT 17
+#define MTX_INT_Q0_TXOP_RUNOUT_HI 17
+#define MTX_INT_Q0_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q1_Q_EMPTY_MSK 0x00040000
+#define MTX_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
+#define MTX_INT_Q1_Q_EMPTY_SFT 18
+#define MTX_INT_Q1_Q_EMPTY_HI 18
+#define MTX_INT_Q1_Q_EMPTY_SZ 1
+#define MTX_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
+#define MTX_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
+#define MTX_INT_Q1_TXOP_RUNOUT_SFT 19
+#define MTX_INT_Q1_TXOP_RUNOUT_HI 19
+#define MTX_INT_Q1_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q2_Q_EMPTY_MSK 0x00100000
+#define MTX_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
+#define MTX_INT_Q2_Q_EMPTY_SFT 20
+#define MTX_INT_Q2_Q_EMPTY_HI 20
+#define MTX_INT_Q2_Q_EMPTY_SZ 1
+#define MTX_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
+#define MTX_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
+#define MTX_INT_Q2_TXOP_RUNOUT_SFT 21
+#define MTX_INT_Q2_TXOP_RUNOUT_HI 21
+#define MTX_INT_Q2_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q3_Q_EMPTY_MSK 0x00400000
+#define MTX_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
+#define MTX_INT_Q3_Q_EMPTY_SFT 22
+#define MTX_INT_Q3_Q_EMPTY_HI 22
+#define MTX_INT_Q3_Q_EMPTY_SZ 1
+#define MTX_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
+#define MTX_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
+#define MTX_INT_Q3_TXOP_RUNOUT_SFT 23
+#define MTX_INT_Q3_TXOP_RUNOUT_HI 23
+#define MTX_INT_Q3_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q4_Q_EMPTY_MSK 0x01000000
+#define MTX_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
+#define MTX_INT_Q4_Q_EMPTY_SFT 24
+#define MTX_INT_Q4_Q_EMPTY_HI 24
+#define MTX_INT_Q4_Q_EMPTY_SZ 1
+#define MTX_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
+#define MTX_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
+#define MTX_INT_Q4_TXOP_RUNOUT_SFT 25
+#define MTX_INT_Q4_TXOP_RUNOUT_HI 25
+#define MTX_INT_Q4_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q0_Q_EMPTY_MSK 0x00010000
+#define MTX_EN_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
+#define MTX_EN_INT_Q0_Q_EMPTY_SFT 16
+#define MTX_EN_INT_Q0_Q_EMPTY_HI 16
+#define MTX_EN_INT_Q0_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_SFT 17
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_HI 17
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q1_Q_EMPTY_MSK 0x00040000
+#define MTX_EN_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
+#define MTX_EN_INT_Q1_Q_EMPTY_SFT 18
+#define MTX_EN_INT_Q1_Q_EMPTY_HI 18
+#define MTX_EN_INT_Q1_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_SFT 19
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_HI 19
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q2_Q_EMPTY_MSK 0x00100000
+#define MTX_EN_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
+#define MTX_EN_INT_Q2_Q_EMPTY_SFT 20
+#define MTX_EN_INT_Q2_Q_EMPTY_HI 20
+#define MTX_EN_INT_Q2_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_SFT 21
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_HI 21
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q3_Q_EMPTY_MSK 0x00400000
+#define MTX_EN_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
+#define MTX_EN_INT_Q3_Q_EMPTY_SFT 22
+#define MTX_EN_INT_Q3_Q_EMPTY_HI 22
+#define MTX_EN_INT_Q3_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_SFT 23
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_HI 23
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q4_Q_EMPTY_MSK 0x01000000
+#define MTX_EN_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
+#define MTX_EN_INT_Q4_Q_EMPTY_SFT 24
+#define MTX_EN_INT_Q4_Q_EMPTY_HI 24
+#define MTX_EN_INT_Q4_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_SFT 25
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_HI 25
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_SZ 1
+#define MTX_MTX2PHY_SLOW_MSK 0x00000001
+#define MTX_MTX2PHY_SLOW_I_MSK 0xfffffffe
+#define MTX_MTX2PHY_SLOW_SFT 0
+#define MTX_MTX2PHY_SLOW_HI 0
+#define MTX_MTX2PHY_SLOW_SZ 1
+#define MTX_M2M_SLOW_PRD_MSK 0x0000000e
+#define MTX_M2M_SLOW_PRD_I_MSK 0xfffffff1
+#define MTX_M2M_SLOW_PRD_SFT 1
+#define MTX_M2M_SLOW_PRD_HI 3
+#define MTX_M2M_SLOW_PRD_SZ 3
+#define MTX_AMPDU_CRC_AUTO_MSK 0x00000020
+#define MTX_AMPDU_CRC_AUTO_I_MSK 0xffffffdf
+#define MTX_AMPDU_CRC_AUTO_SFT 5
+#define MTX_AMPDU_CRC_AUTO_HI 5
+#define MTX_AMPDU_CRC_AUTO_SZ 1
+#define MTX_FAST_RSP_MODE_MSK 0x00000040
+#define MTX_FAST_RSP_MODE_I_MSK 0xffffffbf
+#define MTX_FAST_RSP_MODE_SFT 6
+#define MTX_FAST_RSP_MODE_HI 6
+#define MTX_FAST_RSP_MODE_SZ 1
+#define MTX_RAW_DATA_MODE_MSK 0x00000080
+#define MTX_RAW_DATA_MODE_I_MSK 0xffffff7f
+#define MTX_RAW_DATA_MODE_SFT 7
+#define MTX_RAW_DATA_MODE_HI 7
+#define MTX_RAW_DATA_MODE_SZ 1
+#define MTX_ACK_DUR0_MSK 0x00000100
+#define MTX_ACK_DUR0_I_MSK 0xfffffeff
+#define MTX_ACK_DUR0_SFT 8
+#define MTX_ACK_DUR0_HI 8
+#define MTX_ACK_DUR0_SZ 1
+#define MTX_TSF_AUTO_BCN_MSK 0x00000400
+#define MTX_TSF_AUTO_BCN_I_MSK 0xfffffbff
+#define MTX_TSF_AUTO_BCN_SFT 10
+#define MTX_TSF_AUTO_BCN_HI 10
+#define MTX_TSF_AUTO_BCN_SZ 1
+#define MTX_TSF_AUTO_MISC_MSK 0x00000800
+#define MTX_TSF_AUTO_MISC_I_MSK 0xfffff7ff
+#define MTX_TSF_AUTO_MISC_SFT 11
+#define MTX_TSF_AUTO_MISC_HI 11
+#define MTX_TSF_AUTO_MISC_SZ 1
+#define MTX_FORCE_CS_IDLE_MSK 0x00001000
+#define MTX_FORCE_CS_IDLE_I_MSK 0xffffefff
+#define MTX_FORCE_CS_IDLE_SFT 12
+#define MTX_FORCE_CS_IDLE_HI 12
+#define MTX_FORCE_CS_IDLE_SZ 1
+#define MTX_FORCE_BKF_RXEN0_MSK 0x00002000
+#define MTX_FORCE_BKF_RXEN0_I_MSK 0xffffdfff
+#define MTX_FORCE_BKF_RXEN0_SFT 13
+#define MTX_FORCE_BKF_RXEN0_HI 13
+#define MTX_FORCE_BKF_RXEN0_SZ 1
+#define MTX_FORCE_DMA_RXEN0_MSK 0x00004000
+#define MTX_FORCE_DMA_RXEN0_I_MSK 0xffffbfff
+#define MTX_FORCE_DMA_RXEN0_SFT 14
+#define MTX_FORCE_DMA_RXEN0_HI 14
+#define MTX_FORCE_DMA_RXEN0_SZ 1
+#define MTX_FORCE_RXEN0_MSK 0x00008000
+#define MTX_FORCE_RXEN0_I_MSK 0xffff7fff
+#define MTX_FORCE_RXEN0_SFT 15
+#define MTX_FORCE_RXEN0_HI 15
+#define MTX_FORCE_RXEN0_SZ 1
+#define MTX_HALT_Q_MB_MSK 0x003f0000
+#define MTX_HALT_Q_MB_I_MSK 0xffc0ffff
+#define MTX_HALT_Q_MB_SFT 16
+#define MTX_HALT_Q_MB_HI 21
+#define MTX_HALT_Q_MB_SZ 6
+#define MTX_CTS_SET_DIF_MSK 0x00400000
+#define MTX_CTS_SET_DIF_I_MSK 0xffbfffff
+#define MTX_CTS_SET_DIF_SFT 22
+#define MTX_CTS_SET_DIF_HI 22
+#define MTX_CTS_SET_DIF_SZ 1
+#define MTX_AMPDU_SET_DIF_MSK 0x00800000
+#define MTX_AMPDU_SET_DIF_I_MSK 0xff7fffff
+#define MTX_AMPDU_SET_DIF_SFT 23
+#define MTX_AMPDU_SET_DIF_HI 23
+#define MTX_AMPDU_SET_DIF_SZ 1
+#define MTX_EDCCA_TOUT_MSK 0x000003ff
+#define MTX_EDCCA_TOUT_I_MSK 0xfffffc00
+#define MTX_EDCCA_TOUT_SFT 0
+#define MTX_EDCCA_TOUT_HI 9
+#define MTX_EDCCA_TOUT_SZ 10
+#define MTX_INT_BCN_MSK 0x00000002
+#define MTX_INT_BCN_I_MSK 0xfffffffd
+#define MTX_INT_BCN_SFT 1
+#define MTX_INT_BCN_HI 1
+#define MTX_INT_BCN_SZ 1
+#define MTX_INT_DTIM_MSK 0x00000008
+#define MTX_INT_DTIM_I_MSK 0xfffffff7
+#define MTX_INT_DTIM_SFT 3
+#define MTX_INT_DTIM_HI 3
+#define MTX_INT_DTIM_SZ 1
+#define MTX_EN_INT_BCN_MSK 0x00000002
+#define MTX_EN_INT_BCN_I_MSK 0xfffffffd
+#define MTX_EN_INT_BCN_SFT 1
+#define MTX_EN_INT_BCN_HI 1
+#define MTX_EN_INT_BCN_SZ 1
+#define MTX_EN_INT_DTIM_MSK 0x00000008
+#define MTX_EN_INT_DTIM_I_MSK 0xfffffff7
+#define MTX_EN_INT_DTIM_SFT 3
+#define MTX_EN_INT_DTIM_HI 3
+#define MTX_EN_INT_DTIM_SZ 1
+#define MTX_BCN_TIMER_EN_MSK 0x00000001
+#define MTX_BCN_TIMER_EN_I_MSK 0xfffffffe
+#define MTX_BCN_TIMER_EN_SFT 0
+#define MTX_BCN_TIMER_EN_HI 0
+#define MTX_BCN_TIMER_EN_SZ 1
+#define MTX_TIME_STAMP_AUTO_FILL_MSK 0x00000002
+#define MTX_TIME_STAMP_AUTO_FILL_I_MSK 0xfffffffd
+#define MTX_TIME_STAMP_AUTO_FILL_SFT 1
+#define MTX_TIME_STAMP_AUTO_FILL_HI 1
+#define MTX_TIME_STAMP_AUTO_FILL_SZ 1
+#define MTX_TSF_TIMER_EN_MSK 0x00000020
+#define MTX_TSF_TIMER_EN_I_MSK 0xffffffdf
+#define MTX_TSF_TIMER_EN_SFT 5
+#define MTX_TSF_TIMER_EN_HI 5
+#define MTX_TSF_TIMER_EN_SZ 1
+#define MTX_HALT_MNG_UNTIL_DTIM_MSK 0x00000040
+#define MTX_HALT_MNG_UNTIL_DTIM_I_MSK 0xffffffbf
+#define MTX_HALT_MNG_UNTIL_DTIM_SFT 6
+#define MTX_HALT_MNG_UNTIL_DTIM_HI 6
+#define MTX_HALT_MNG_UNTIL_DTIM_SZ 1
+#define MTX_INT_DTIM_NUM_MSK 0x0000ff00
+#define MTX_INT_DTIM_NUM_I_MSK 0xffff00ff
+#define MTX_INT_DTIM_NUM_SFT 8
+#define MTX_INT_DTIM_NUM_HI 15
+#define MTX_INT_DTIM_NUM_SZ 8
+#define MTX_AUTO_FLUSH_Q4_MSK 0x00010000
+#define MTX_AUTO_FLUSH_Q4_I_MSK 0xfffeffff
+#define MTX_AUTO_FLUSH_Q4_SFT 16
+#define MTX_AUTO_FLUSH_Q4_HI 16
+#define MTX_AUTO_FLUSH_Q4_SZ 1
+#define MTX_BCN_PKTID_CH_LOCK_MSK 0x00000001
+#define MTX_BCN_PKTID_CH_LOCK_I_MSK 0xfffffffe
+#define MTX_BCN_PKTID_CH_LOCK_SFT 0
+#define MTX_BCN_PKTID_CH_LOCK_HI 0
+#define MTX_BCN_PKTID_CH_LOCK_SZ 1
+#define MTX_BCN_CFG_VLD_MSK 0x00000006
+#define MTX_BCN_CFG_VLD_I_MSK 0xfffffff9
+#define MTX_BCN_CFG_VLD_SFT 1
+#define MTX_BCN_CFG_VLD_HI 2
+#define MTX_BCN_CFG_VLD_SZ 2
+#define MTX_AUTO_BCN_ONGOING_MSK 0x00000008
+#define MTX_AUTO_BCN_ONGOING_I_MSK 0xfffffff7
+#define MTX_AUTO_BCN_ONGOING_SFT 3
+#define MTX_AUTO_BCN_ONGOING_HI 3
+#define MTX_AUTO_BCN_ONGOING_SZ 1
+#define MTX_BCN_TIMER_MSK 0xffff0000
+#define MTX_BCN_TIMER_I_MSK 0x0000ffff
+#define MTX_BCN_TIMER_SFT 16
+#define MTX_BCN_TIMER_HI 31
+#define MTX_BCN_TIMER_SZ 16
+#define MTX_BCN_PERIOD_MSK 0x0000ffff
+#define MTX_BCN_PERIOD_I_MSK 0xffff0000
+#define MTX_BCN_PERIOD_SFT 0
+#define MTX_BCN_PERIOD_HI 15
+#define MTX_BCN_PERIOD_SZ 16
+#define MTX_DTIM_NUM_MSK 0xff000000
+#define MTX_DTIM_NUM_I_MSK 0x00ffffff
+#define MTX_DTIM_NUM_SFT 24
+#define MTX_DTIM_NUM_HI 31
+#define MTX_DTIM_NUM_SZ 8
+#define MTX_BCN_TSF_L_MSK 0xffffffff
+#define MTX_BCN_TSF_L_I_MSK 0x00000000
+#define MTX_BCN_TSF_L_SFT 0
+#define MTX_BCN_TSF_L_HI 31
+#define MTX_BCN_TSF_L_SZ 32
+#define MTX_BCN_TSF_U_MSK 0xffffffff
+#define MTX_BCN_TSF_U_I_MSK 0x00000000
+#define MTX_BCN_TSF_U_SFT 0
+#define MTX_BCN_TSF_U_HI 31
+#define MTX_BCN_TSF_U_SZ 32
+#define MTX_BCN_PKT_ID0_MSK 0x0000007f
+#define MTX_BCN_PKT_ID0_I_MSK 0xffffff80
+#define MTX_BCN_PKT_ID0_SFT 0
+#define MTX_BCN_PKT_ID0_HI 6
+#define MTX_BCN_PKT_ID0_SZ 7
+#define MTX_DTIM_OFST0_MSK 0x03ff0000
+#define MTX_DTIM_OFST0_I_MSK 0xfc00ffff
+#define MTX_DTIM_OFST0_SFT 16
+#define MTX_DTIM_OFST0_HI 25
+#define MTX_DTIM_OFST0_SZ 10
+#define MTX_BCN_PKT_ID1_MSK 0x0000007f
+#define MTX_BCN_PKT_ID1_I_MSK 0xffffff80
+#define MTX_BCN_PKT_ID1_SFT 0
+#define MTX_BCN_PKT_ID1_HI 6
+#define MTX_BCN_PKT_ID1_SZ 7
+#define MTX_DTIM_OFST1_MSK 0x03ff0000
+#define MTX_DTIM_OFST1_I_MSK 0xfc00ffff
+#define MTX_DTIM_OFST1_SFT 16
+#define MTX_DTIM_OFST1_HI 25
+#define MTX_DTIM_OFST1_SZ 10
+#define MTX_CCA_MSK 0x00000001
+#define MTX_CCA_I_MSK 0xfffffffe
+#define MTX_CCA_SFT 0
+#define MTX_CCA_HI 0
+#define MTX_CCA_SZ 1
+#define MRX_CCA_MSK 0x00000002
+#define MRX_CCA_I_MSK 0xfffffffd
+#define MRX_CCA_SFT 1
+#define MRX_CCA_HI 1
+#define MRX_CCA_SZ 1
+#define MTX_DMA_FSM_MSK 0x0000001c
+#define MTX_DMA_FSM_I_MSK 0xffffffe3
+#define MTX_DMA_FSM_SFT 2
+#define MTX_DMA_FSM_HI 4
+#define MTX_DMA_FSM_SZ 3
+#define CH_ST_FSM_MSK 0x000000e0
+#define CH_ST_FSM_I_MSK 0xffffff1f
+#define CH_ST_FSM_SFT 5
+#define CH_ST_FSM_HI 7
+#define CH_ST_FSM_SZ 3
+#define MTX_GNT_LOCK_MSK 0x00000100
+#define MTX_GNT_LOCK_I_MSK 0xfffffeff
+#define MTX_GNT_LOCK_SFT 8
+#define MTX_GNT_LOCK_HI 8
+#define MTX_GNT_LOCK_SZ 1
+#define MTX_DMA_REQ_MSK 0x00000200
+#define MTX_DMA_REQ_I_MSK 0xfffffdff
+#define MTX_DMA_REQ_SFT 9
+#define MTX_DMA_REQ_HI 9
+#define MTX_DMA_REQ_SZ 1
+#define MTX_Q_REQ_MSK 0x00000400
+#define MTX_Q_REQ_I_MSK 0xfffffbff
+#define MTX_Q_REQ_SFT 10
+#define MTX_Q_REQ_HI 10
+#define MTX_Q_REQ_SZ 1
+#define MTX_TX_EN_MSK 0x00000800
+#define MTX_TX_EN_I_MSK 0xfffff7ff
+#define MTX_TX_EN_SFT 11
+#define MTX_TX_EN_HI 11
+#define MTX_TX_EN_SZ 1
+#define MRX_RX_EN_MSK 0x00001000
+#define MRX_RX_EN_I_MSK 0xffffefff
+#define MRX_RX_EN_SFT 12
+#define MRX_RX_EN_HI 12
+#define MRX_RX_EN_SZ 1
+#define DBG_PRTC_PRD_MSK 0x00002000
+#define DBG_PRTC_PRD_I_MSK 0xffffdfff
+#define DBG_PRTC_PRD_SFT 13
+#define DBG_PRTC_PRD_HI 13
+#define DBG_PRTC_PRD_SZ 1
+#define DBG_DMA_RDY_MSK 0x00004000
+#define DBG_DMA_RDY_I_MSK 0xffffbfff
+#define DBG_DMA_RDY_SFT 14
+#define DBG_DMA_RDY_HI 14
+#define DBG_DMA_RDY_SZ 1
+#define DBG_WAIT_RSP_MSK 0x00008000
+#define DBG_WAIT_RSP_I_MSK 0xffff7fff
+#define DBG_WAIT_RSP_SFT 15
+#define DBG_WAIT_RSP_HI 15
+#define DBG_WAIT_RSP_SZ 1
+#define DBG_CFRM_BUSY_MSK 0x00010000
+#define DBG_CFRM_BUSY_I_MSK 0xfffeffff
+#define DBG_CFRM_BUSY_SFT 16
+#define DBG_CFRM_BUSY_HI 16
+#define DBG_CFRM_BUSY_SZ 1
+#define DBG_RST_MSK 0x00000001
+#define DBG_RST_I_MSK 0xfffffffe
+#define DBG_RST_SFT 0
+#define DBG_RST_HI 0
+#define DBG_RST_SZ 1
+#define DBG_MODE_MSK 0x00000002
+#define DBG_MODE_I_MSK 0xfffffffd
+#define DBG_MODE_SFT 1
+#define DBG_MODE_HI 1
+#define DBG_MODE_SZ 1
+#define MB_REQ_DUR_MSK 0x0000ffff
+#define MB_REQ_DUR_I_MSK 0xffff0000
+#define MB_REQ_DUR_SFT 0
+#define MB_REQ_DUR_HI 15
+#define MB_REQ_DUR_SZ 16
+#define RX_EN_DUR_MSK 0xffff0000
+#define RX_EN_DUR_I_MSK 0x0000ffff
+#define RX_EN_DUR_SFT 16
+#define RX_EN_DUR_HI 31
+#define RX_EN_DUR_SZ 16
+#define RX_CS_DUR_MSK 0x0000ffff
+#define RX_CS_DUR_I_MSK 0xffff0000
+#define RX_CS_DUR_SFT 0
+#define RX_CS_DUR_HI 15
+#define RX_CS_DUR_SZ 16
+#define TX_CCA_DUR_MSK 0xffff0000
+#define TX_CCA_DUR_I_MSK 0x0000ffff
+#define TX_CCA_DUR_SFT 16
+#define TX_CCA_DUR_HI 31
+#define TX_CCA_DUR_SZ 16
+#define Q_REQ_DUR_MSK 0x0000ffff
+#define Q_REQ_DUR_I_MSK 0xffff0000
+#define Q_REQ_DUR_SFT 0
+#define Q_REQ_DUR_HI 15
+#define Q_REQ_DUR_SZ 16
+#define CH_STA0_DUR_MSK 0xffff0000
+#define CH_STA0_DUR_I_MSK 0x0000ffff
+#define CH_STA0_DUR_SFT 16
+#define CH_STA0_DUR_HI 31
+#define CH_STA0_DUR_SZ 16
+#define MTX_DUR_RSP_TOUT_B_MSK 0x000000ff
+#define MTX_DUR_RSP_TOUT_B_I_MSK 0xffffff00
+#define MTX_DUR_RSP_TOUT_B_SFT 0
+#define MTX_DUR_RSP_TOUT_B_HI 7
+#define MTX_DUR_RSP_TOUT_B_SZ 8
+#define MTX_DUR_RSP_TOUT_G_MSK 0x0000ff00
+#define MTX_DUR_RSP_TOUT_G_I_MSK 0xffff00ff
+#define MTX_DUR_RSP_TOUT_G_SFT 8
+#define MTX_DUR_RSP_TOUT_G_HI 15
+#define MTX_DUR_RSP_TOUT_G_SZ 8
+#define MTX_DUR_RSP_SIFS_MSK 0x000000ff
+#define MTX_DUR_RSP_SIFS_I_MSK 0xffffff00
+#define MTX_DUR_RSP_SIFS_SFT 0
+#define MTX_DUR_RSP_SIFS_HI 7
+#define MTX_DUR_RSP_SIFS_SZ 8
+#define MTX_DUR_BURST_SIFS_MSK 0x0000ff00
+#define MTX_DUR_BURST_SIFS_I_MSK 0xffff00ff
+#define MTX_DUR_BURST_SIFS_SFT 8
+#define MTX_DUR_BURST_SIFS_HI 15
+#define MTX_DUR_BURST_SIFS_SZ 8
+#define MTX_DUR_SLOT_MSK 0x003f0000
+#define MTX_DUR_SLOT_I_MSK 0xffc0ffff
+#define MTX_DUR_SLOT_SFT 16
+#define MTX_DUR_SLOT_HI 21
+#define MTX_DUR_SLOT_SZ 6
+#define MTX_DUR_RSP_EIFS_MSK 0xffc00000
+#define MTX_DUR_RSP_EIFS_I_MSK 0x003fffff
+#define MTX_DUR_RSP_EIFS_SFT 22
+#define MTX_DUR_RSP_EIFS_HI 31
+#define MTX_DUR_RSP_EIFS_SZ 10
+#define MTX_DUR_RSP_SIFS_G_MSK 0x000000ff
+#define MTX_DUR_RSP_SIFS_G_I_MSK 0xffffff00
+#define MTX_DUR_RSP_SIFS_G_SFT 0
+#define MTX_DUR_RSP_SIFS_G_HI 7
+#define MTX_DUR_RSP_SIFS_G_SZ 8
+#define MTX_DUR_BURST_SIFS_G_MSK 0x0000ff00
+#define MTX_DUR_BURST_SIFS_G_I_MSK 0xffff00ff
+#define MTX_DUR_BURST_SIFS_G_SFT 8
+#define MTX_DUR_BURST_SIFS_G_HI 15
+#define MTX_DUR_BURST_SIFS_G_SZ 8
+#define MTX_DUR_SLOT_G_MSK 0x003f0000
+#define MTX_DUR_SLOT_G_I_MSK 0xffc0ffff
+#define MTX_DUR_SLOT_G_SFT 16
+#define MTX_DUR_SLOT_G_HI 21
+#define MTX_DUR_SLOT_G_SZ 6
+#define MTX_DUR_RSP_EIFS_G_MSK 0xffc00000
+#define MTX_DUR_RSP_EIFS_G_I_MSK 0x003fffff
+#define MTX_DUR_RSP_EIFS_G_SFT 22
+#define MTX_DUR_RSP_EIFS_G_HI 31
+#define MTX_DUR_RSP_EIFS_G_SZ 10
+#define CH_STA1_DUR_MSK 0x0000ffff
+#define CH_STA1_DUR_I_MSK 0xffff0000
+#define CH_STA1_DUR_SFT 0
+#define CH_STA1_DUR_HI 15
+#define CH_STA1_DUR_SZ 16
+#define CH_STA2_DUR_MSK 0xffff0000
+#define CH_STA2_DUR_I_MSK 0x0000ffff
+#define CH_STA2_DUR_SFT 16
+#define CH_STA2_DUR_HI 31
+#define CH_STA2_DUR_SZ 16
+#define MTX_NAV_MSK 0x0000ffff
+#define MTX_NAV_I_MSK 0xffff0000
+#define MTX_NAV_SFT 0
+#define MTX_NAV_HI 15
+#define MTX_NAV_SZ 16
+#define MTX_MIB_CNT0_MSK 0x3fffffff
+#define MTX_MIB_CNT0_I_MSK 0xc0000000
+#define MTX_MIB_CNT0_SFT 0
+#define MTX_MIB_CNT0_HI 29
+#define MTX_MIB_CNT0_SZ 30
+#define MTX_MIB_EN0_MSK 0x40000000
+#define MTX_MIB_EN0_I_MSK 0xbfffffff
+#define MTX_MIB_EN0_SFT 30
+#define MTX_MIB_EN0_HI 30
+#define MTX_MIB_EN0_SZ 1
+#define MTX_MIB_CNT1_MSK 0x3fffffff
+#define MTX_MIB_CNT1_I_MSK 0xc0000000
+#define MTX_MIB_CNT1_SFT 0
+#define MTX_MIB_CNT1_HI 29
+#define MTX_MIB_CNT1_SZ 30
+#define MTX_MIB_EN1_MSK 0x40000000
+#define MTX_MIB_EN1_I_MSK 0xbfffffff
+#define MTX_MIB_EN1_SFT 30
+#define MTX_MIB_EN1_HI 30
+#define MTX_MIB_EN1_SZ 1
+#define CH_STA3_DUR_MSK 0x0000ffff
+#define CH_STA3_DUR_I_MSK 0xffff0000
+#define CH_STA3_DUR_SFT 0
+#define CH_STA3_DUR_HI 15
+#define CH_STA3_DUR_SZ 16
+#define CH_STA4_DUR_MSK 0xffff0000
+#define CH_STA4_DUR_I_MSK 0x0000ffff
+#define CH_STA4_DUR_SFT 16
+#define CH_STA4_DUR_HI 31
+#define CH_STA4_DUR_SZ 16
+#define TXQ0_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ0_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ0_MTX_Q_PRE_LD_SFT 1
+#define TXQ0_MTX_Q_PRE_LD_HI 1
+#define TXQ0_MTX_Q_PRE_LD_SZ 1
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ0_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ0_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ0_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ0_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ0_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ0_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ0_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ0_MTX_Q_RND_MODE_SFT 6
+#define TXQ0_MTX_Q_RND_MODE_HI 7
+#define TXQ0_MTX_Q_RND_MODE_SZ 2
+#define TXQ0_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ0_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ0_MTX_Q_AIFSN_SFT 0
+#define TXQ0_MTX_Q_AIFSN_HI 3
+#define TXQ0_MTX_Q_AIFSN_SZ 4
+#define TXQ0_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ0_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ0_MTX_Q_ECWMIN_SFT 8
+#define TXQ0_MTX_Q_ECWMIN_HI 11
+#define TXQ0_MTX_Q_ECWMIN_SZ 4
+#define TXQ0_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ0_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ0_MTX_Q_ECWMAX_SFT 12
+#define TXQ0_MTX_Q_ECWMAX_HI 15
+#define TXQ0_MTX_Q_ECWMAX_SZ 4
+#define TXQ0_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ0_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ0_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ0_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ0_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_BKF_CNT_SFT 0
+#define TXQ0_MTX_Q_BKF_CNT_HI 15
+#define TXQ0_MTX_Q_BKF_CNT_SZ 16
+#define TXQ0_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ0_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ0_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ0_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ0_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ0_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ0_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ0_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ0_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ0_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ0_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ0_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ0_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ0_MTX_Q_ID_MAP_L_HI 31
+#define TXQ0_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ0_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ0_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ0_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ0_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ0_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ0_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ1_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ1_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ1_MTX_Q_PRE_LD_SFT 1
+#define TXQ1_MTX_Q_PRE_LD_HI 1
+#define TXQ1_MTX_Q_PRE_LD_SZ 1
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ1_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ1_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ1_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ1_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ1_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ1_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ1_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ1_MTX_Q_RND_MODE_SFT 6
+#define TXQ1_MTX_Q_RND_MODE_HI 7
+#define TXQ1_MTX_Q_RND_MODE_SZ 2
+#define TXQ1_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ1_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ1_MTX_Q_AIFSN_SFT 0
+#define TXQ1_MTX_Q_AIFSN_HI 3
+#define TXQ1_MTX_Q_AIFSN_SZ 4
+#define TXQ1_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ1_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ1_MTX_Q_ECWMIN_SFT 8
+#define TXQ1_MTX_Q_ECWMIN_HI 11
+#define TXQ1_MTX_Q_ECWMIN_SZ 4
+#define TXQ1_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ1_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ1_MTX_Q_ECWMAX_SFT 12
+#define TXQ1_MTX_Q_ECWMAX_HI 15
+#define TXQ1_MTX_Q_ECWMAX_SZ 4
+#define TXQ1_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ1_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ1_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ1_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ1_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_BKF_CNT_SFT 0
+#define TXQ1_MTX_Q_BKF_CNT_HI 15
+#define TXQ1_MTX_Q_BKF_CNT_SZ 16
+#define TXQ1_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ1_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ1_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ1_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ1_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ1_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ1_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ1_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ1_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ1_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ1_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ1_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ1_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ1_MTX_Q_ID_MAP_L_HI 31
+#define TXQ1_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ1_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ1_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ1_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ1_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ1_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ1_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ2_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ2_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ2_MTX_Q_PRE_LD_SFT 1
+#define TXQ2_MTX_Q_PRE_LD_HI 1
+#define TXQ2_MTX_Q_PRE_LD_SZ 1
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ2_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ2_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ2_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ2_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ2_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ2_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ2_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ2_MTX_Q_RND_MODE_SFT 6
+#define TXQ2_MTX_Q_RND_MODE_HI 7
+#define TXQ2_MTX_Q_RND_MODE_SZ 2
+#define TXQ2_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ2_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ2_MTX_Q_AIFSN_SFT 0
+#define TXQ2_MTX_Q_AIFSN_HI 3
+#define TXQ2_MTX_Q_AIFSN_SZ 4
+#define TXQ2_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ2_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ2_MTX_Q_ECWMIN_SFT 8
+#define TXQ2_MTX_Q_ECWMIN_HI 11
+#define TXQ2_MTX_Q_ECWMIN_SZ 4
+#define TXQ2_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ2_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ2_MTX_Q_ECWMAX_SFT 12
+#define TXQ2_MTX_Q_ECWMAX_HI 15
+#define TXQ2_MTX_Q_ECWMAX_SZ 4
+#define TXQ2_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ2_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ2_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ2_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ2_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_BKF_CNT_SFT 0
+#define TXQ2_MTX_Q_BKF_CNT_HI 15
+#define TXQ2_MTX_Q_BKF_CNT_SZ 16
+#define TXQ2_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ2_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ2_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ2_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ2_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ2_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ2_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ2_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ2_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ2_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ2_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ2_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ2_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ2_MTX_Q_ID_MAP_L_HI 31
+#define TXQ2_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ2_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ2_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ2_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ2_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ2_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ2_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ3_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ3_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ3_MTX_Q_PRE_LD_SFT 1
+#define TXQ3_MTX_Q_PRE_LD_HI 1
+#define TXQ3_MTX_Q_PRE_LD_SZ 1
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ3_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ3_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ3_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ3_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ3_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ3_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ3_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ3_MTX_Q_RND_MODE_SFT 6
+#define TXQ3_MTX_Q_RND_MODE_HI 7
+#define TXQ3_MTX_Q_RND_MODE_SZ 2
+#define TXQ3_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ3_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ3_MTX_Q_AIFSN_SFT 0
+#define TXQ3_MTX_Q_AIFSN_HI 3
+#define TXQ3_MTX_Q_AIFSN_SZ 4
+#define TXQ3_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ3_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ3_MTX_Q_ECWMIN_SFT 8
+#define TXQ3_MTX_Q_ECWMIN_HI 11
+#define TXQ3_MTX_Q_ECWMIN_SZ 4
+#define TXQ3_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ3_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ3_MTX_Q_ECWMAX_SFT 12
+#define TXQ3_MTX_Q_ECWMAX_HI 15
+#define TXQ3_MTX_Q_ECWMAX_SZ 4
+#define TXQ3_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ3_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ3_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ3_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ3_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_BKF_CNT_SFT 0
+#define TXQ3_MTX_Q_BKF_CNT_HI 15
+#define TXQ3_MTX_Q_BKF_CNT_SZ 16
+#define TXQ3_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ3_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ3_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ3_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ3_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ3_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ3_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ3_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ3_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ3_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ3_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ3_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ3_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ3_MTX_Q_ID_MAP_L_HI 31
+#define TXQ3_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ3_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ3_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ3_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ3_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ3_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ3_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ4_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ4_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ4_MTX_Q_PRE_LD_SFT 1
+#define TXQ4_MTX_Q_PRE_LD_HI 1
+#define TXQ4_MTX_Q_PRE_LD_SZ 1
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ4_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ4_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ4_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ4_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ4_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ4_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ4_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ4_MTX_Q_RND_MODE_SFT 6
+#define TXQ4_MTX_Q_RND_MODE_HI 7
+#define TXQ4_MTX_Q_RND_MODE_SZ 2
+#define TXQ4_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ4_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ4_MTX_Q_AIFSN_SFT 0
+#define TXQ4_MTX_Q_AIFSN_HI 3
+#define TXQ4_MTX_Q_AIFSN_SZ 4
+#define TXQ4_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ4_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ4_MTX_Q_ECWMIN_SFT 8
+#define TXQ4_MTX_Q_ECWMIN_HI 11
+#define TXQ4_MTX_Q_ECWMIN_SZ 4
+#define TXQ4_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ4_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ4_MTX_Q_ECWMAX_SFT 12
+#define TXQ4_MTX_Q_ECWMAX_HI 15
+#define TXQ4_MTX_Q_ECWMAX_SZ 4
+#define TXQ4_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ4_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ4_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ4_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ4_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_BKF_CNT_SFT 0
+#define TXQ4_MTX_Q_BKF_CNT_HI 15
+#define TXQ4_MTX_Q_BKF_CNT_SZ 16
+#define TXQ4_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ4_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ4_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ4_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ4_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ4_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ4_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ4_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ4_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ4_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ4_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ4_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ4_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ4_MTX_Q_ID_MAP_L_HI 31
+#define TXQ4_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ4_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ4_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ4_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ4_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ4_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ4_MTX_Q_TXOP_OV_THD_SZ 16
+#define VALID0_MSK 0x00000001
+#define VALID0_I_MSK 0xfffffffe
+#define VALID0_SFT 0
+#define VALID0_HI 0
+#define VALID0_SZ 1
+#define PEER_QOS_EN0_MSK 0x00000002
+#define PEER_QOS_EN0_I_MSK 0xfffffffd
+#define PEER_QOS_EN0_SFT 1
+#define PEER_QOS_EN0_HI 1
+#define PEER_QOS_EN0_SZ 1
+#define PEER_OP_MODE0_MSK 0x0000000c
+#define PEER_OP_MODE0_I_MSK 0xfffffff3
+#define PEER_OP_MODE0_SFT 2
+#define PEER_OP_MODE0_HI 3
+#define PEER_OP_MODE0_SZ 2
+#define PEER_HT_MODE0_MSK 0x00000030
+#define PEER_HT_MODE0_I_MSK 0xffffffcf
+#define PEER_HT_MODE0_SFT 4
+#define PEER_HT_MODE0_HI 5
+#define PEER_HT_MODE0_SZ 2
+#define PEER_MAC0_31_0_MSK 0xffffffff
+#define PEER_MAC0_31_0_I_MSK 0x00000000
+#define PEER_MAC0_31_0_SFT 0
+#define PEER_MAC0_31_0_HI 31
+#define PEER_MAC0_31_0_SZ 32
+#define PEER_MAC0_47_32_MSK 0x0000ffff
+#define PEER_MAC0_47_32_I_MSK 0xffff0000
+#define PEER_MAC0_47_32_SFT 0
+#define PEER_MAC0_47_32_HI 15
+#define PEER_MAC0_47_32_SZ 16
+#define TX_ACK_POLICY_0_0_MSK 0x00000003
+#define TX_ACK_POLICY_0_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_0_SFT 0
+#define TX_ACK_POLICY_0_0_HI 1
+#define TX_ACK_POLICY_0_0_SZ 2
+#define TX_SEQ_CTRL_0_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_0_SFT 0
+#define TX_SEQ_CTRL_0_0_HI 11
+#define TX_SEQ_CTRL_0_0_SZ 12
+#define TX_ACK_POLICY_0_1_MSK 0x00000003
+#define TX_ACK_POLICY_0_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_1_SFT 0
+#define TX_ACK_POLICY_0_1_HI 1
+#define TX_ACK_POLICY_0_1_SZ 2
+#define TX_SEQ_CTRL_0_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_1_SFT 0
+#define TX_SEQ_CTRL_0_1_HI 11
+#define TX_SEQ_CTRL_0_1_SZ 12
+#define TX_ACK_POLICY_0_2_MSK 0x00000003
+#define TX_ACK_POLICY_0_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_2_SFT 0
+#define TX_ACK_POLICY_0_2_HI 1
+#define TX_ACK_POLICY_0_2_SZ 2
+#define TX_SEQ_CTRL_0_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_2_SFT 0
+#define TX_SEQ_CTRL_0_2_HI 11
+#define TX_SEQ_CTRL_0_2_SZ 12
+#define TX_ACK_POLICY_0_3_MSK 0x00000003
+#define TX_ACK_POLICY_0_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_3_SFT 0
+#define TX_ACK_POLICY_0_3_HI 1
+#define TX_ACK_POLICY_0_3_SZ 2
+#define TX_SEQ_CTRL_0_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_3_SFT 0
+#define TX_SEQ_CTRL_0_3_HI 11
+#define TX_SEQ_CTRL_0_3_SZ 12
+#define TX_ACK_POLICY_0_4_MSK 0x00000003
+#define TX_ACK_POLICY_0_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_4_SFT 0
+#define TX_ACK_POLICY_0_4_HI 1
+#define TX_ACK_POLICY_0_4_SZ 2
+#define TX_SEQ_CTRL_0_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_4_SFT 0
+#define TX_SEQ_CTRL_0_4_HI 11
+#define TX_SEQ_CTRL_0_4_SZ 12
+#define TX_ACK_POLICY_0_5_MSK 0x00000003
+#define TX_ACK_POLICY_0_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_5_SFT 0
+#define TX_ACK_POLICY_0_5_HI 1
+#define TX_ACK_POLICY_0_5_SZ 2
+#define TX_SEQ_CTRL_0_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_5_SFT 0
+#define TX_SEQ_CTRL_0_5_HI 11
+#define TX_SEQ_CTRL_0_5_SZ 12
+#define TX_ACK_POLICY_0_6_MSK 0x00000003
+#define TX_ACK_POLICY_0_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_6_SFT 0
+#define TX_ACK_POLICY_0_6_HI 1
+#define TX_ACK_POLICY_0_6_SZ 2
+#define TX_SEQ_CTRL_0_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_6_SFT 0
+#define TX_SEQ_CTRL_0_6_HI 11
+#define TX_SEQ_CTRL_0_6_SZ 12
+#define TX_ACK_POLICY_0_7_MSK 0x00000003
+#define TX_ACK_POLICY_0_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_7_SFT 0
+#define TX_ACK_POLICY_0_7_HI 1
+#define TX_ACK_POLICY_0_7_SZ 2
+#define TX_SEQ_CTRL_0_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_7_SFT 0
+#define TX_SEQ_CTRL_0_7_HI 11
+#define TX_SEQ_CTRL_0_7_SZ 12
+#define VALID1_MSK 0x00000001
+#define VALID1_I_MSK 0xfffffffe
+#define VALID1_SFT 0
+#define VALID1_HI 0
+#define VALID1_SZ 1
+#define PEER_QOS_EN1_MSK 0x00000002
+#define PEER_QOS_EN1_I_MSK 0xfffffffd
+#define PEER_QOS_EN1_SFT 1
+#define PEER_QOS_EN1_HI 1
+#define PEER_QOS_EN1_SZ 1
+#define PEER_OP_MODE1_MSK 0x0000000c
+#define PEER_OP_MODE1_I_MSK 0xfffffff3
+#define PEER_OP_MODE1_SFT 2
+#define PEER_OP_MODE1_HI 3
+#define PEER_OP_MODE1_SZ 2
+#define PEER_HT_MODE1_MSK 0x00000030
+#define PEER_HT_MODE1_I_MSK 0xffffffcf
+#define PEER_HT_MODE1_SFT 4
+#define PEER_HT_MODE1_HI 5
+#define PEER_HT_MODE1_SZ 2
+#define PEER_MAC1_31_0_MSK 0xffffffff
+#define PEER_MAC1_31_0_I_MSK 0x00000000
+#define PEER_MAC1_31_0_SFT 0
+#define PEER_MAC1_31_0_HI 31
+#define PEER_MAC1_31_0_SZ 32
+#define PEER_MAC1_47_32_MSK 0x0000ffff
+#define PEER_MAC1_47_32_I_MSK 0xffff0000
+#define PEER_MAC1_47_32_SFT 0
+#define PEER_MAC1_47_32_HI 15
+#define PEER_MAC1_47_32_SZ 16
+#define TX_ACK_POLICY_1_0_MSK 0x00000003
+#define TX_ACK_POLICY_1_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_0_SFT 0
+#define TX_ACK_POLICY_1_0_HI 1
+#define TX_ACK_POLICY_1_0_SZ 2
+#define TX_SEQ_CTRL_1_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_0_SFT 0
+#define TX_SEQ_CTRL_1_0_HI 11
+#define TX_SEQ_CTRL_1_0_SZ 12
+#define TX_ACK_POLICY_1_1_MSK 0x00000003
+#define TX_ACK_POLICY_1_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_1_SFT 0
+#define TX_ACK_POLICY_1_1_HI 1
+#define TX_ACK_POLICY_1_1_SZ 2
+#define TX_SEQ_CTRL_1_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_1_SFT 0
+#define TX_SEQ_CTRL_1_1_HI 11
+#define TX_SEQ_CTRL_1_1_SZ 12
+#define TX_ACK_POLICY_1_2_MSK 0x00000003
+#define TX_ACK_POLICY_1_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_2_SFT 0
+#define TX_ACK_POLICY_1_2_HI 1
+#define TX_ACK_POLICY_1_2_SZ 2
+#define TX_SEQ_CTRL_1_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_2_SFT 0
+#define TX_SEQ_CTRL_1_2_HI 11
+#define TX_SEQ_CTRL_1_2_SZ 12
+#define TX_ACK_POLICY_1_3_MSK 0x00000003
+#define TX_ACK_POLICY_1_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_3_SFT 0
+#define TX_ACK_POLICY_1_3_HI 1
+#define TX_ACK_POLICY_1_3_SZ 2
+#define TX_SEQ_CTRL_1_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_3_SFT 0
+#define TX_SEQ_CTRL_1_3_HI 11
+#define TX_SEQ_CTRL_1_3_SZ 12
+#define TX_ACK_POLICY_1_4_MSK 0x00000003
+#define TX_ACK_POLICY_1_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_4_SFT 0
+#define TX_ACK_POLICY_1_4_HI 1
+#define TX_ACK_POLICY_1_4_SZ 2
+#define TX_SEQ_CTRL_1_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_4_SFT 0
+#define TX_SEQ_CTRL_1_4_HI 11
+#define TX_SEQ_CTRL_1_4_SZ 12
+#define TX_ACK_POLICY_1_5_MSK 0x00000003
+#define TX_ACK_POLICY_1_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_5_SFT 0
+#define TX_ACK_POLICY_1_5_HI 1
+#define TX_ACK_POLICY_1_5_SZ 2
+#define TX_SEQ_CTRL_1_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_5_SFT 0
+#define TX_SEQ_CTRL_1_5_HI 11
+#define TX_SEQ_CTRL_1_5_SZ 12
+#define TX_ACK_POLICY_1_6_MSK 0x00000003
+#define TX_ACK_POLICY_1_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_6_SFT 0
+#define TX_ACK_POLICY_1_6_HI 1
+#define TX_ACK_POLICY_1_6_SZ 2
+#define TX_SEQ_CTRL_1_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_6_SFT 0
+#define TX_SEQ_CTRL_1_6_HI 11
+#define TX_SEQ_CTRL_1_6_SZ 12
+#define TX_ACK_POLICY_1_7_MSK 0x00000003
+#define TX_ACK_POLICY_1_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_7_SFT 0
+#define TX_ACK_POLICY_1_7_HI 1
+#define TX_ACK_POLICY_1_7_SZ 2
+#define TX_SEQ_CTRL_1_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_7_SFT 0
+#define TX_SEQ_CTRL_1_7_HI 11
+#define TX_SEQ_CTRL_1_7_SZ 12
+#define INFO0_MSK 0xffffffff
+#define INFO0_I_MSK 0x00000000
+#define INFO0_SFT 0
+#define INFO0_HI 31
+#define INFO0_SZ 32
+#define INFO1_MSK 0xffffffff
+#define INFO1_I_MSK 0x00000000
+#define INFO1_SFT 0
+#define INFO1_HI 31
+#define INFO1_SZ 32
+#define INFO2_MSK 0xffffffff
+#define INFO2_I_MSK 0x00000000
+#define INFO2_SFT 0
+#define INFO2_HI 31
+#define INFO2_SZ 32
+#define INFO3_MSK 0xffffffff
+#define INFO3_I_MSK 0x00000000
+#define INFO3_SFT 0
+#define INFO3_HI 31
+#define INFO3_SZ 32
+#define INFO4_MSK 0xffffffff
+#define INFO4_I_MSK 0x00000000
+#define INFO4_SFT 0
+#define INFO4_HI 31
+#define INFO4_SZ 32
+#define INFO5_MSK 0xffffffff
+#define INFO5_I_MSK 0x00000000
+#define INFO5_SFT 0
+#define INFO5_HI 31
+#define INFO5_SZ 32
+#define INFO6_MSK 0xffffffff
+#define INFO6_I_MSK 0x00000000
+#define INFO6_SFT 0
+#define INFO6_HI 31
+#define INFO6_SZ 32
+#define INFO7_MSK 0xffffffff
+#define INFO7_I_MSK 0x00000000
+#define INFO7_SFT 0
+#define INFO7_HI 31
+#define INFO7_SZ 32
+#define INFO8_MSK 0xffffffff
+#define INFO8_I_MSK 0x00000000
+#define INFO8_SFT 0
+#define INFO8_HI 31
+#define INFO8_SZ 32
+#define INFO9_MSK 0xffffffff
+#define INFO9_I_MSK 0x00000000
+#define INFO9_SFT 0
+#define INFO9_HI 31
+#define INFO9_SZ 32
+#define INFO10_MSK 0xffffffff
+#define INFO10_I_MSK 0x00000000
+#define INFO10_SFT 0
+#define INFO10_HI 31
+#define INFO10_SZ 32
+#define INFO11_MSK 0xffffffff
+#define INFO11_I_MSK 0x00000000
+#define INFO11_SFT 0
+#define INFO11_HI 31
+#define INFO11_SZ 32
+#define INFO12_MSK 0xffffffff
+#define INFO12_I_MSK 0x00000000
+#define INFO12_SFT 0
+#define INFO12_HI 31
+#define INFO12_SZ 32
+#define INFO13_MSK 0xffffffff
+#define INFO13_I_MSK 0x00000000
+#define INFO13_SFT 0
+#define INFO13_HI 31
+#define INFO13_SZ 32
+#define INFO14_MSK 0xffffffff
+#define INFO14_I_MSK 0x00000000
+#define INFO14_SFT 0
+#define INFO14_HI 31
+#define INFO14_SZ 32
+#define INFO15_MSK 0xffffffff
+#define INFO15_I_MSK 0x00000000
+#define INFO15_SFT 0
+#define INFO15_HI 31
+#define INFO15_SZ 32
+#define INFO16_MSK 0xffffffff
+#define INFO16_I_MSK 0x00000000
+#define INFO16_SFT 0
+#define INFO16_HI 31
+#define INFO16_SZ 32
+#define INFO17_MSK 0xffffffff
+#define INFO17_I_MSK 0x00000000
+#define INFO17_SFT 0
+#define INFO17_HI 31
+#define INFO17_SZ 32
+#define INFO18_MSK 0xffffffff
+#define INFO18_I_MSK 0x00000000
+#define INFO18_SFT 0
+#define INFO18_HI 31
+#define INFO18_SZ 32
+#define INFO19_MSK 0xffffffff
+#define INFO19_I_MSK 0x00000000
+#define INFO19_SFT 0
+#define INFO19_HI 31
+#define INFO19_SZ 32
+#define INFO20_MSK 0xffffffff
+#define INFO20_I_MSK 0x00000000
+#define INFO20_SFT 0
+#define INFO20_HI 31
+#define INFO20_SZ 32
+#define INFO21_MSK 0xffffffff
+#define INFO21_I_MSK 0x00000000
+#define INFO21_SFT 0
+#define INFO21_HI 31
+#define INFO21_SZ 32
+#define INFO22_MSK 0xffffffff
+#define INFO22_I_MSK 0x00000000
+#define INFO22_SFT 0
+#define INFO22_HI 31
+#define INFO22_SZ 32
+#define INFO23_MSK 0xffffffff
+#define INFO23_I_MSK 0x00000000
+#define INFO23_SFT 0
+#define INFO23_HI 31
+#define INFO23_SZ 32
+#define INFO24_MSK 0xffffffff
+#define INFO24_I_MSK 0x00000000
+#define INFO24_SFT 0
+#define INFO24_HI 31
+#define INFO24_SZ 32
+#define INFO25_MSK 0xffffffff
+#define INFO25_I_MSK 0x00000000
+#define INFO25_SFT 0
+#define INFO25_HI 31
+#define INFO25_SZ 32
+#define INFO26_MSK 0xffffffff
+#define INFO26_I_MSK 0x00000000
+#define INFO26_SFT 0
+#define INFO26_HI 31
+#define INFO26_SZ 32
+#define INFO27_MSK 0xffffffff
+#define INFO27_I_MSK 0x00000000
+#define INFO27_SFT 0
+#define INFO27_HI 31
+#define INFO27_SZ 32
+#define INFO28_MSK 0xffffffff
+#define INFO28_I_MSK 0x00000000
+#define INFO28_SFT 0
+#define INFO28_HI 31
+#define INFO28_SZ 32
+#define INFO29_MSK 0xffffffff
+#define INFO29_I_MSK 0x00000000
+#define INFO29_SFT 0
+#define INFO29_HI 31
+#define INFO29_SZ 32
+#define INFO30_MSK 0xffffffff
+#define INFO30_I_MSK 0x00000000
+#define INFO30_SFT 0
+#define INFO30_HI 31
+#define INFO30_SZ 32
+#define INFO31_MSK 0xffffffff
+#define INFO31_I_MSK 0x00000000
+#define INFO31_SFT 0
+#define INFO31_HI 31
+#define INFO31_SZ 32
+#define INFO32_MSK 0xffffffff
+#define INFO32_I_MSK 0x00000000
+#define INFO32_SFT 0
+#define INFO32_HI 31
+#define INFO32_SZ 32
+#define INFO33_MSK 0xffffffff
+#define INFO33_I_MSK 0x00000000
+#define INFO33_SFT 0
+#define INFO33_HI 31
+#define INFO33_SZ 32
+#define INFO34_MSK 0xffffffff
+#define INFO34_I_MSK 0x00000000
+#define INFO34_SFT 0
+#define INFO34_HI 31
+#define INFO34_SZ 32
+#define INFO35_MSK 0xffffffff
+#define INFO35_I_MSK 0x00000000
+#define INFO35_SFT 0
+#define INFO35_HI 31
+#define INFO35_SZ 32
+#define INFO36_MSK 0xffffffff
+#define INFO36_I_MSK 0x00000000
+#define INFO36_SFT 0
+#define INFO36_HI 31
+#define INFO36_SZ 32
+#define INFO37_MSK 0xffffffff
+#define INFO37_I_MSK 0x00000000
+#define INFO37_SFT 0
+#define INFO37_HI 31
+#define INFO37_SZ 32
+#define INFO38_MSK 0xffffffff
+#define INFO38_I_MSK 0x00000000
+#define INFO38_SFT 0
+#define INFO38_HI 31
+#define INFO38_SZ 32
+#define INFO_MASK_MSK 0xffffffff
+#define INFO_MASK_I_MSK 0x00000000
+#define INFO_MASK_SFT 0
+#define INFO_MASK_HI 31
+#define INFO_MASK_SZ 32
+#define INFO_DEF_RATE_MSK 0x0000003f
+#define INFO_DEF_RATE_I_MSK 0xffffffc0
+#define INFO_DEF_RATE_SFT 0
+#define INFO_DEF_RATE_HI 5
+#define INFO_DEF_RATE_SZ 6
+#define INFO_MRX_OFFSET_MSK 0x000f0000
+#define INFO_MRX_OFFSET_I_MSK 0xfff0ffff
+#define INFO_MRX_OFFSET_SFT 16
+#define INFO_MRX_OFFSET_HI 19
+#define INFO_MRX_OFFSET_SZ 4
+#define BCAST_RATEUNKNOW_MSK 0x3f000000
+#define BCAST_RATEUNKNOW_I_MSK 0xc0ffffff
+#define BCAST_RATEUNKNOW_SFT 24
+#define BCAST_RATEUNKNOW_HI 29
+#define BCAST_RATEUNKNOW_SZ 6
+#define INFO_IDX_TBL_ADDR_MSK 0xffffffff
+#define INFO_IDX_TBL_ADDR_I_MSK 0x00000000
+#define INFO_IDX_TBL_ADDR_SFT 0
+#define INFO_IDX_TBL_ADDR_HI 31
+#define INFO_IDX_TBL_ADDR_SZ 32
+#define INFO_LEN_TBL_ADDR_MSK 0xffffffff
+#define INFO_LEN_TBL_ADDR_I_MSK 0x00000000
+#define INFO_LEN_TBL_ADDR_SFT 0
+#define INFO_LEN_TBL_ADDR_HI 31
+#define INFO_LEN_TBL_ADDR_SZ 32
+#define IC_TAG_31_0_MSK 0xffffffff
+#define IC_TAG_31_0_I_MSK 0x00000000
+#define IC_TAG_31_0_SFT 0
+#define IC_TAG_31_0_HI 31
+#define IC_TAG_31_0_SZ 32
+#define IC_TAG_63_32_MSK 0xffffffff
+#define IC_TAG_63_32_I_MSK 0x00000000
+#define IC_TAG_63_32_SFT 0
+#define IC_TAG_63_32_HI 31
+#define IC_TAG_63_32_SZ 32
+#define CH1_PRI_MSK 0x00000003
+#define CH1_PRI_I_MSK 0xfffffffc
+#define CH1_PRI_SFT 0
+#define CH1_PRI_HI 1
+#define CH1_PRI_SZ 2
+#define CH2_PRI_MSK 0x00000300
+#define CH2_PRI_I_MSK 0xfffffcff
+#define CH2_PRI_SFT 8
+#define CH2_PRI_HI 9
+#define CH2_PRI_SZ 2
+#define CH3_PRI_MSK 0x00030000
+#define CH3_PRI_I_MSK 0xfffcffff
+#define CH3_PRI_SFT 16
+#define CH3_PRI_HI 17
+#define CH3_PRI_SZ 2
+#define RG_MAC_LPBK_MSK 0x00000001
+#define RG_MAC_LPBK_I_MSK 0xfffffffe
+#define RG_MAC_LPBK_SFT 0
+#define RG_MAC_LPBK_HI 0
+#define RG_MAC_LPBK_SZ 1
+#define RG_MAC_M2M_MSK 0x00000002
+#define RG_MAC_M2M_I_MSK 0xfffffffd
+#define RG_MAC_M2M_SFT 1
+#define RG_MAC_M2M_HI 1
+#define RG_MAC_M2M_SZ 1
+#define RG_PHY_LPBK_MSK 0x00000004
+#define RG_PHY_LPBK_I_MSK 0xfffffffb
+#define RG_PHY_LPBK_SFT 2
+#define RG_PHY_LPBK_HI 2
+#define RG_PHY_LPBK_SZ 1
+#define RG_LPBK_RX_EN_MSK 0x00000008
+#define RG_LPBK_RX_EN_I_MSK 0xfffffff7
+#define RG_LPBK_RX_EN_SFT 3
+#define RG_LPBK_RX_EN_HI 3
+#define RG_LPBK_RX_EN_SZ 1
+#define EXT_MAC_MODE_MSK 0x00000010
+#define EXT_MAC_MODE_I_MSK 0xffffffef
+#define EXT_MAC_MODE_SFT 4
+#define EXT_MAC_MODE_HI 4
+#define EXT_MAC_MODE_SZ 1
+#define EXT_PHY_MODE_MSK 0x00000020
+#define EXT_PHY_MODE_I_MSK 0xffffffdf
+#define EXT_PHY_MODE_SFT 5
+#define EXT_PHY_MODE_HI 5
+#define EXT_PHY_MODE_SZ 1
+#define ASIC_TAG_MSK 0xff000000
+#define ASIC_TAG_I_MSK 0x00ffffff
+#define ASIC_TAG_SFT 24
+#define ASIC_TAG_HI 31
+#define ASIC_TAG_SZ 8
+#define HCI_SW_RST_MSK 0x00000001
+#define HCI_SW_RST_I_MSK 0xfffffffe
+#define HCI_SW_RST_SFT 0
+#define HCI_SW_RST_HI 0
+#define HCI_SW_RST_SZ 1
+#define CO_PROC_SW_RST_MSK 0x00000002
+#define CO_PROC_SW_RST_I_MSK 0xfffffffd
+#define CO_PROC_SW_RST_SFT 1
+#define CO_PROC_SW_RST_HI 1
+#define CO_PROC_SW_RST_SZ 1
+#define MTX_MISC_SW_RST_MSK 0x00000008
+#define MTX_MISC_SW_RST_I_MSK 0xfffffff7
+#define MTX_MISC_SW_RST_SFT 3
+#define MTX_MISC_SW_RST_HI 3
+#define MTX_MISC_SW_RST_SZ 1
+#define MTX_QUE_SW_RST_MSK 0x00000010
+#define MTX_QUE_SW_RST_I_MSK 0xffffffef
+#define MTX_QUE_SW_RST_SFT 4
+#define MTX_QUE_SW_RST_HI 4
+#define MTX_QUE_SW_RST_SZ 1
+#define MTX_CHST_SW_RST_MSK 0x00000020
+#define MTX_CHST_SW_RST_I_MSK 0xffffffdf
+#define MTX_CHST_SW_RST_SFT 5
+#define MTX_CHST_SW_RST_HI 5
+#define MTX_CHST_SW_RST_SZ 1
+#define MTX_BCN_SW_RST_MSK 0x00000040
+#define MTX_BCN_SW_RST_I_MSK 0xffffffbf
+#define MTX_BCN_SW_RST_SFT 6
+#define MTX_BCN_SW_RST_HI 6
+#define MTX_BCN_SW_RST_SZ 1
+#define MRX_SW_RST_MSK 0x00000080
+#define MRX_SW_RST_I_MSK 0xffffff7f
+#define MRX_SW_RST_SFT 7
+#define MRX_SW_RST_HI 7
+#define MRX_SW_RST_SZ 1
+#define AMPDU_SW_RST_MSK 0x00000100
+#define AMPDU_SW_RST_I_MSK 0xfffffeff
+#define AMPDU_SW_RST_SFT 8
+#define AMPDU_SW_RST_HI 8
+#define AMPDU_SW_RST_SZ 1
+#define MMU_SW_RST_MSK 0x00000200
+#define MMU_SW_RST_I_MSK 0xfffffdff
+#define MMU_SW_RST_SFT 9
+#define MMU_SW_RST_HI 9
+#define MMU_SW_RST_SZ 1
+#define ID_MNG_SW_RST_MSK 0x00000800
+#define ID_MNG_SW_RST_I_MSK 0xfffff7ff
+#define ID_MNG_SW_RST_SFT 11
+#define ID_MNG_SW_RST_HI 11
+#define ID_MNG_SW_RST_SZ 1
+#define MBOX_SW_RST_MSK 0x00001000
+#define MBOX_SW_RST_I_MSK 0xffffefff
+#define MBOX_SW_RST_SFT 12
+#define MBOX_SW_RST_HI 12
+#define MBOX_SW_RST_SZ 1
+#define SCRT_SW_RST_MSK 0x00002000
+#define SCRT_SW_RST_I_MSK 0xffffdfff
+#define SCRT_SW_RST_SFT 13
+#define SCRT_SW_RST_HI 13
+#define SCRT_SW_RST_SZ 1
+#define MIC_SW_RST_MSK 0x00004000
+#define MIC_SW_RST_I_MSK 0xffffbfff
+#define MIC_SW_RST_SFT 14
+#define MIC_SW_RST_HI 14
+#define MIC_SW_RST_SZ 1
+#define CO_PROC_ENG_RST_MSK 0x00000002
+#define CO_PROC_ENG_RST_I_MSK 0xfffffffd
+#define CO_PROC_ENG_RST_SFT 1
+#define CO_PROC_ENG_RST_HI 1
+#define CO_PROC_ENG_RST_SZ 1
+#define MTX_MISC_ENG_RST_MSK 0x00000008
+#define MTX_MISC_ENG_RST_I_MSK 0xfffffff7
+#define MTX_MISC_ENG_RST_SFT 3
+#define MTX_MISC_ENG_RST_HI 3
+#define MTX_MISC_ENG_RST_SZ 1
+#define MTX_QUE_ENG_RST_MSK 0x00000010
+#define MTX_QUE_ENG_RST_I_MSK 0xffffffef
+#define MTX_QUE_ENG_RST_SFT 4
+#define MTX_QUE_ENG_RST_HI 4
+#define MTX_QUE_ENG_RST_SZ 1
+#define MTX_CHST_ENG_RST_MSK 0x00000020
+#define MTX_CHST_ENG_RST_I_MSK 0xffffffdf
+#define MTX_CHST_ENG_RST_SFT 5
+#define MTX_CHST_ENG_RST_HI 5
+#define MTX_CHST_ENG_RST_SZ 1
+#define MTX_BCN_ENG_RST_MSK 0x00000040
+#define MTX_BCN_ENG_RST_I_MSK 0xffffffbf
+#define MTX_BCN_ENG_RST_SFT 6
+#define MTX_BCN_ENG_RST_HI 6
+#define MTX_BCN_ENG_RST_SZ 1
+#define MRX_ENG_RST_MSK 0x00000080
+#define MRX_ENG_RST_I_MSK 0xffffff7f
+#define MRX_ENG_RST_SFT 7
+#define MRX_ENG_RST_HI 7
+#define MRX_ENG_RST_SZ 1
+#define AMPDU_ENG_RST_MSK 0x00000100
+#define AMPDU_ENG_RST_I_MSK 0xfffffeff
+#define AMPDU_ENG_RST_SFT 8
+#define AMPDU_ENG_RST_HI 8
+#define AMPDU_ENG_RST_SZ 1
+#define ID_MNG_ENG_RST_MSK 0x00004000
+#define ID_MNG_ENG_RST_I_MSK 0xffffbfff
+#define ID_MNG_ENG_RST_SFT 14
+#define ID_MNG_ENG_RST_HI 14
+#define ID_MNG_ENG_RST_SZ 1
+#define MBOX_ENG_RST_MSK 0x00008000
+#define MBOX_ENG_RST_I_MSK 0xffff7fff
+#define MBOX_ENG_RST_SFT 15
+#define MBOX_ENG_RST_HI 15
+#define MBOX_ENG_RST_SZ 1
+#define SCRT_ENG_RST_MSK 0x00010000
+#define SCRT_ENG_RST_I_MSK 0xfffeffff
+#define SCRT_ENG_RST_SFT 16
+#define SCRT_ENG_RST_HI 16
+#define SCRT_ENG_RST_SZ 1
+#define MIC_ENG_RST_MSK 0x00020000
+#define MIC_ENG_RST_I_MSK 0xfffdffff
+#define MIC_ENG_RST_SFT 17
+#define MIC_ENG_RST_HI 17
+#define MIC_ENG_RST_SZ 1
+#define CO_PROC_CSR_RST_MSK 0x00000002
+#define CO_PROC_CSR_RST_I_MSK 0xfffffffd
+#define CO_PROC_CSR_RST_SFT 1
+#define CO_PROC_CSR_RST_HI 1
+#define CO_PROC_CSR_RST_SZ 1
+#define MTX_MISC_CSR_RST_MSK 0x00000008
+#define MTX_MISC_CSR_RST_I_MSK 0xfffffff7
+#define MTX_MISC_CSR_RST_SFT 3
+#define MTX_MISC_CSR_RST_HI 3
+#define MTX_MISC_CSR_RST_SZ 1
+#define MTX_QUE0_CSR_RST_MSK 0x00000010
+#define MTX_QUE0_CSR_RST_I_MSK 0xffffffef
+#define MTX_QUE0_CSR_RST_SFT 4
+#define MTX_QUE0_CSR_RST_HI 4
+#define MTX_QUE0_CSR_RST_SZ 1
+#define MTX_QUE1_CSR_RST_MSK 0x00000020
+#define MTX_QUE1_CSR_RST_I_MSK 0xffffffdf
+#define MTX_QUE1_CSR_RST_SFT 5
+#define MTX_QUE1_CSR_RST_HI 5
+#define MTX_QUE1_CSR_RST_SZ 1
+#define MTX_QUE2_CSR_RST_MSK 0x00000040
+#define MTX_QUE2_CSR_RST_I_MSK 0xffffffbf
+#define MTX_QUE2_CSR_RST_SFT 6
+#define MTX_QUE2_CSR_RST_HI 6
+#define MTX_QUE2_CSR_RST_SZ 1
+#define MTX_QUE3_CSR_RST_MSK 0x00000080
+#define MTX_QUE3_CSR_RST_I_MSK 0xffffff7f
+#define MTX_QUE3_CSR_RST_SFT 7
+#define MTX_QUE3_CSR_RST_HI 7
+#define MTX_QUE3_CSR_RST_SZ 1
+#define MTX_QUE4_CSR_RST_MSK 0x00000100
+#define MTX_QUE4_CSR_RST_I_MSK 0xfffffeff
+#define MTX_QUE4_CSR_RST_SFT 8
+#define MTX_QUE4_CSR_RST_HI 8
+#define MTX_QUE4_CSR_RST_SZ 1
+#define MTX_QUE5_CSR_RST_MSK 0x00000200
+#define MTX_QUE5_CSR_RST_I_MSK 0xfffffdff
+#define MTX_QUE5_CSR_RST_SFT 9
+#define MTX_QUE5_CSR_RST_HI 9
+#define MTX_QUE5_CSR_RST_SZ 1
+#define MRX_CSR_RST_MSK 0x00000400
+#define MRX_CSR_RST_I_MSK 0xfffffbff
+#define MRX_CSR_RST_SFT 10
+#define MRX_CSR_RST_HI 10
+#define MRX_CSR_RST_SZ 1
+#define AMPDU_CSR_RST_MSK 0x00000800
+#define AMPDU_CSR_RST_I_MSK 0xfffff7ff
+#define AMPDU_CSR_RST_SFT 11
+#define AMPDU_CSR_RST_HI 11
+#define AMPDU_CSR_RST_SZ 1
+#define SCRT_CSR_RST_MSK 0x00002000
+#define SCRT_CSR_RST_I_MSK 0xffffdfff
+#define SCRT_CSR_RST_SFT 13
+#define SCRT_CSR_RST_HI 13
+#define SCRT_CSR_RST_SZ 1
+#define ID_MNG_CSR_RST_MSK 0x00004000
+#define ID_MNG_CSR_RST_I_MSK 0xffffbfff
+#define ID_MNG_CSR_RST_SFT 14
+#define ID_MNG_CSR_RST_HI 14
+#define ID_MNG_CSR_RST_SZ 1
+#define MBOX_CSR_RST_MSK 0x00008000
+#define MBOX_CSR_RST_I_MSK 0xffff7fff
+#define MBOX_CSR_RST_SFT 15
+#define MBOX_CSR_RST_HI 15
+#define MBOX_CSR_RST_SZ 1
+#define HCI_CLK_EN_MSK 0x00000001
+#define HCI_CLK_EN_I_MSK 0xfffffffe
+#define HCI_CLK_EN_SFT 0
+#define HCI_CLK_EN_HI 0
+#define HCI_CLK_EN_SZ 1
+#define CO_PROC_CLK_EN_MSK 0x00000002
+#define CO_PROC_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_CLK_EN_SFT 1
+#define CO_PROC_CLK_EN_HI 1
+#define CO_PROC_CLK_EN_SZ 1
+#define MTX_MISC_CLK_EN_MSK 0x00000008
+#define MTX_MISC_CLK_EN_I_MSK 0xfffffff7
+#define MTX_MISC_CLK_EN_SFT 3
+#define MTX_MISC_CLK_EN_HI 3
+#define MTX_MISC_CLK_EN_SZ 1
+#define MTX_QUE_CLK_EN_MSK 0x00000010
+#define MTX_QUE_CLK_EN_I_MSK 0xffffffef
+#define MTX_QUE_CLK_EN_SFT 4
+#define MTX_QUE_CLK_EN_HI 4
+#define MTX_QUE_CLK_EN_SZ 1
+#define MRX_CLK_EN_MSK 0x00000020
+#define MRX_CLK_EN_I_MSK 0xffffffdf
+#define MRX_CLK_EN_SFT 5
+#define MRX_CLK_EN_HI 5
+#define MRX_CLK_EN_SZ 1
+#define AMPDU_CLK_EN_MSK 0x00000040
+#define AMPDU_CLK_EN_I_MSK 0xffffffbf
+#define AMPDU_CLK_EN_SFT 6
+#define AMPDU_CLK_EN_HI 6
+#define AMPDU_CLK_EN_SZ 1
+#define MMU_CLK_EN_MSK 0x00000080
+#define MMU_CLK_EN_I_MSK 0xffffff7f
+#define MMU_CLK_EN_SFT 7
+#define MMU_CLK_EN_HI 7
+#define MMU_CLK_EN_SZ 1
+#define ID_MNG_CLK_EN_MSK 0x00000200
+#define ID_MNG_CLK_EN_I_MSK 0xfffffdff
+#define ID_MNG_CLK_EN_SFT 9
+#define ID_MNG_CLK_EN_HI 9
+#define ID_MNG_CLK_EN_SZ 1
+#define MBOX_CLK_EN_MSK 0x00000400
+#define MBOX_CLK_EN_I_MSK 0xfffffbff
+#define MBOX_CLK_EN_SFT 10
+#define MBOX_CLK_EN_HI 10
+#define MBOX_CLK_EN_SZ 1
+#define SCRT_CLK_EN_MSK 0x00000800
+#define SCRT_CLK_EN_I_MSK 0xfffff7ff
+#define SCRT_CLK_EN_SFT 11
+#define SCRT_CLK_EN_HI 11
+#define SCRT_CLK_EN_SZ 1
+#define MIC_CLK_EN_MSK 0x00001000
+#define MIC_CLK_EN_I_MSK 0xffffefff
+#define MIC_CLK_EN_SFT 12
+#define MIC_CLK_EN_HI 12
+#define MIC_CLK_EN_SZ 1
+#define MIB_CLK_EN_MSK 0x00002000
+#define MIB_CLK_EN_I_MSK 0xffffdfff
+#define MIB_CLK_EN_SFT 13
+#define MIB_CLK_EN_HI 13
+#define MIB_CLK_EN_SZ 1
+#define HCI_ENG_CLK_EN_MSK 0x00000001
+#define HCI_ENG_CLK_EN_I_MSK 0xfffffffe
+#define HCI_ENG_CLK_EN_SFT 0
+#define HCI_ENG_CLK_EN_HI 0
+#define HCI_ENG_CLK_EN_SZ 1
+#define CO_PROC_ENG_CLK_EN_MSK 0x00000002
+#define CO_PROC_ENG_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_ENG_CLK_EN_SFT 1
+#define CO_PROC_ENG_CLK_EN_HI 1
+#define CO_PROC_ENG_CLK_EN_SZ 1
+#define MTX_MISC_ENG_CLK_EN_MSK 0x00000008
+#define MTX_MISC_ENG_CLK_EN_I_MSK 0xfffffff7
+#define MTX_MISC_ENG_CLK_EN_SFT 3
+#define MTX_MISC_ENG_CLK_EN_HI 3
+#define MTX_MISC_ENG_CLK_EN_SZ 1
+#define MTX_QUE_ENG_CLK_EN_MSK 0x00000010
+#define MTX_QUE_ENG_CLK_EN_I_MSK 0xffffffef
+#define MTX_QUE_ENG_CLK_EN_SFT 4
+#define MTX_QUE_ENG_CLK_EN_HI 4
+#define MTX_QUE_ENG_CLK_EN_SZ 1
+#define MRX_ENG_CLK_EN_MSK 0x00000020
+#define MRX_ENG_CLK_EN_I_MSK 0xffffffdf
+#define MRX_ENG_CLK_EN_SFT 5
+#define MRX_ENG_CLK_EN_HI 5
+#define MRX_ENG_CLK_EN_SZ 1
+#define AMPDU_ENG_CLK_EN_MSK 0x00000040
+#define AMPDU_ENG_CLK_EN_I_MSK 0xffffffbf
+#define AMPDU_ENG_CLK_EN_SFT 6
+#define AMPDU_ENG_CLK_EN_HI 6
+#define AMPDU_ENG_CLK_EN_SZ 1
+#define ID_MNG_ENG_CLK_EN_MSK 0x00001000
+#define ID_MNG_ENG_CLK_EN_I_MSK 0xffffefff
+#define ID_MNG_ENG_CLK_EN_SFT 12
+#define ID_MNG_ENG_CLK_EN_HI 12
+#define ID_MNG_ENG_CLK_EN_SZ 1
+#define MBOX_ENG_CLK_EN_MSK 0x00002000
+#define MBOX_ENG_CLK_EN_I_MSK 0xffffdfff
+#define MBOX_ENG_CLK_EN_SFT 13
+#define MBOX_ENG_CLK_EN_HI 13
+#define MBOX_ENG_CLK_EN_SZ 1
+#define SCRT_ENG_CLK_EN_MSK 0x00004000
+#define SCRT_ENG_CLK_EN_I_MSK 0xffffbfff
+#define SCRT_ENG_CLK_EN_SFT 14
+#define SCRT_ENG_CLK_EN_HI 14
+#define SCRT_ENG_CLK_EN_SZ 1
+#define MIC_ENG_CLK_EN_MSK 0x00008000
+#define MIC_ENG_CLK_EN_I_MSK 0xffff7fff
+#define MIC_ENG_CLK_EN_SFT 15
+#define MIC_ENG_CLK_EN_HI 15
+#define MIC_ENG_CLK_EN_SZ 1
+#define CO_PROC_CSR_CLK_EN_MSK 0x00000002
+#define CO_PROC_CSR_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_CSR_CLK_EN_SFT 1
+#define CO_PROC_CSR_CLK_EN_HI 1
+#define CO_PROC_CSR_CLK_EN_SZ 1
+#define MRX_CSR_CLK_EN_MSK 0x00000400
+#define MRX_CSR_CLK_EN_I_MSK 0xfffffbff
+#define MRX_CSR_CLK_EN_SFT 10
+#define MRX_CSR_CLK_EN_HI 10
+#define MRX_CSR_CLK_EN_SZ 1
+#define AMPDU_CSR_CLK_EN_MSK 0x00000800
+#define AMPDU_CSR_CLK_EN_I_MSK 0xfffff7ff
+#define AMPDU_CSR_CLK_EN_SFT 11
+#define AMPDU_CSR_CLK_EN_HI 11
+#define AMPDU_CSR_CLK_EN_SZ 1
+#define SCRT_CSR_CLK_EN_MSK 0x00002000
+#define SCRT_CSR_CLK_EN_I_MSK 0xffffdfff
+#define SCRT_CSR_CLK_EN_SFT 13
+#define SCRT_CSR_CLK_EN_HI 13
+#define SCRT_CSR_CLK_EN_SZ 1
+#define ID_MNG_CSR_CLK_EN_MSK 0x00004000
+#define ID_MNG_CSR_CLK_EN_I_MSK 0xffffbfff
+#define ID_MNG_CSR_CLK_EN_SFT 14
+#define ID_MNG_CSR_CLK_EN_HI 14
+#define ID_MNG_CSR_CLK_EN_SZ 1
+#define MBOX_CSR_CLK_EN_MSK 0x00008000
+#define MBOX_CSR_CLK_EN_I_MSK 0xffff7fff
+#define MBOX_CSR_CLK_EN_SFT 15
+#define MBOX_CSR_CLK_EN_HI 15
+#define MBOX_CSR_CLK_EN_SZ 1
+#define OP_MODE_MSK 0x00000003
+#define OP_MODE_I_MSK 0xfffffffc
+#define OP_MODE_SFT 0
+#define OP_MODE_HI 1
+#define OP_MODE_SZ 2
+#define HT_MODE_MSK 0x0000000c
+#define HT_MODE_I_MSK 0xfffffff3
+#define HT_MODE_SFT 2
+#define HT_MODE_HI 3
+#define HT_MODE_SZ 2
+#define QOS_EN_MSK 0x00000010
+#define QOS_EN_I_MSK 0xffffffef
+#define QOS_EN_SFT 4
+#define QOS_EN_HI 4
+#define QOS_EN_SZ 1
+#define PB_OFFSET_MSK 0x0000ff00
+#define PB_OFFSET_I_MSK 0xffff00ff
+#define PB_OFFSET_SFT 8
+#define PB_OFFSET_HI 15
+#define PB_OFFSET_SZ 8
+#define SNIFFER_MODE_MSK 0x00010000
+#define SNIFFER_MODE_I_MSK 0xfffeffff
+#define SNIFFER_MODE_SFT 16
+#define SNIFFER_MODE_HI 16
+#define SNIFFER_MODE_SZ 1
+#define DUP_FLT_MSK 0x00020000
+#define DUP_FLT_I_MSK 0xfffdffff
+#define DUP_FLT_SFT 17
+#define DUP_FLT_HI 17
+#define DUP_FLT_SZ 1
+#define TX_PKT_RSVD_MSK 0x001c0000
+#define TX_PKT_RSVD_I_MSK 0xffe3ffff
+#define TX_PKT_RSVD_SFT 18
+#define TX_PKT_RSVD_HI 20
+#define TX_PKT_RSVD_SZ 3
+#define AMPDU_SNIFFER_MSK 0x00200000
+#define AMPDU_SNIFFER_I_MSK 0xffdfffff
+#define AMPDU_SNIFFER_SFT 21
+#define AMPDU_SNIFFER_HI 21
+#define AMPDU_SNIFFER_SZ 1
+#define REASON_TRAP0_MSK 0xffffffff
+#define REASON_TRAP0_I_MSK 0x00000000
+#define REASON_TRAP0_SFT 0
+#define REASON_TRAP0_HI 31
+#define REASON_TRAP0_SZ 32
+#define REASON_TRAP1_MSK 0xffffffff
+#define REASON_TRAP1_I_MSK 0x00000000
+#define REASON_TRAP1_SFT 0
+#define REASON_TRAP1_HI 31
+#define REASON_TRAP1_SZ 32
+#define BSSID_31_0_MSK 0xffffffff
+#define BSSID_31_0_I_MSK 0x00000000
+#define BSSID_31_0_SFT 0
+#define BSSID_31_0_HI 31
+#define BSSID_31_0_SZ 32
+#define BSSID_47_32_MSK 0x0000ffff
+#define BSSID_47_32_I_MSK 0xffff0000
+#define BSSID_47_32_SFT 0
+#define BSSID_47_32_HI 15
+#define BSSID_47_32_SZ 16
+#define SCRT_STATE_MSK 0x0000000f
+#define SCRT_STATE_I_MSK 0xfffffff0
+#define SCRT_STATE_SFT 0
+#define SCRT_STATE_HI 3
+#define SCRT_STATE_SZ 4
+#define STA_MAC_31_0_MSK 0xffffffff
+#define STA_MAC_31_0_I_MSK 0x00000000
+#define STA_MAC_31_0_SFT 0
+#define STA_MAC_31_0_HI 31
+#define STA_MAC_31_0_SZ 32
+#define STA_MAC_47_32_MSK 0x0000ffff
+#define STA_MAC_47_32_I_MSK 0xffff0000
+#define STA_MAC_47_32_SFT 0
+#define STA_MAC_47_32_HI 15
+#define STA_MAC_47_32_SZ 16
+#define PAIR_SCRT_MSK 0x00000007
+#define PAIR_SCRT_I_MSK 0xfffffff8
+#define PAIR_SCRT_SFT 0
+#define PAIR_SCRT_HI 2
+#define PAIR_SCRT_SZ 3
+#define GRP_SCRT_MSK 0x00000038
+#define GRP_SCRT_I_MSK 0xffffffc7
+#define GRP_SCRT_SFT 3
+#define GRP_SCRT_HI 5
+#define GRP_SCRT_SZ 3
+#define SCRT_PKT_ID_MSK 0x00001fc0
+#define SCRT_PKT_ID_I_MSK 0xffffe03f
+#define SCRT_PKT_ID_SFT 6
+#define SCRT_PKT_ID_HI 12
+#define SCRT_PKT_ID_SZ 7
+#define SCRT_RPLY_IGNORE_MSK 0x00010000
+#define SCRT_RPLY_IGNORE_I_MSK 0xfffeffff
+#define SCRT_RPLY_IGNORE_SFT 16
+#define SCRT_RPLY_IGNORE_HI 16
+#define SCRT_RPLY_IGNORE_SZ 1
+#define COEXIST_EN_MSK 0x00000001
+#define COEXIST_EN_I_MSK 0xfffffffe
+#define COEXIST_EN_SFT 0
+#define COEXIST_EN_HI 0
+#define COEXIST_EN_SZ 1
+#define WIRE_MODE_MSK 0x0000000e
+#define WIRE_MODE_I_MSK 0xfffffff1
+#define WIRE_MODE_SFT 1
+#define WIRE_MODE_HI 3
+#define WIRE_MODE_SZ 3
+#define WL_RX_PRI_MSK 0x00000010
+#define WL_RX_PRI_I_MSK 0xffffffef
+#define WL_RX_PRI_SFT 4
+#define WL_RX_PRI_HI 4
+#define WL_RX_PRI_SZ 1
+#define WL_TX_PRI_MSK 0x00000020
+#define WL_TX_PRI_I_MSK 0xffffffdf
+#define WL_TX_PRI_SFT 5
+#define WL_TX_PRI_HI 5
+#define WL_TX_PRI_SZ 1
+#define GURAN_USE_EN_MSK 0x00000100
+#define GURAN_USE_EN_I_MSK 0xfffffeff
+#define GURAN_USE_EN_SFT 8
+#define GURAN_USE_EN_HI 8
+#define GURAN_USE_EN_SZ 1
+#define GURAN_USE_CTRL_MSK 0x00000200
+#define GURAN_USE_CTRL_I_MSK 0xfffffdff
+#define GURAN_USE_CTRL_SFT 9
+#define GURAN_USE_CTRL_HI 9
+#define GURAN_USE_CTRL_SZ 1
+#define BEACON_TIMEOUT_EN_MSK 0x00000400
+#define BEACON_TIMEOUT_EN_I_MSK 0xfffffbff
+#define BEACON_TIMEOUT_EN_SFT 10
+#define BEACON_TIMEOUT_EN_HI 10
+#define BEACON_TIMEOUT_EN_SZ 1
+#define WLAN_ACT_POL_MSK 0x00000800
+#define WLAN_ACT_POL_I_MSK 0xfffff7ff
+#define WLAN_ACT_POL_SFT 11
+#define WLAN_ACT_POL_HI 11
+#define WLAN_ACT_POL_SZ 1
+#define DUAL_ANT_EN_MSK 0x00001000
+#define DUAL_ANT_EN_I_MSK 0xffffefff
+#define DUAL_ANT_EN_SFT 12
+#define DUAL_ANT_EN_HI 12
+#define DUAL_ANT_EN_SZ 1
+#define TRSW_PHY_POL_MSK 0x00010000
+#define TRSW_PHY_POL_I_MSK 0xfffeffff
+#define TRSW_PHY_POL_SFT 16
+#define TRSW_PHY_POL_HI 16
+#define TRSW_PHY_POL_SZ 1
+#define WIFI_TX_SW_POL_MSK 0x00020000
+#define WIFI_TX_SW_POL_I_MSK 0xfffdffff
+#define WIFI_TX_SW_POL_SFT 17
+#define WIFI_TX_SW_POL_HI 17
+#define WIFI_TX_SW_POL_SZ 1
+#define WIFI_RX_SW_POL_MSK 0x00040000
+#define WIFI_RX_SW_POL_I_MSK 0xfffbffff
+#define WIFI_RX_SW_POL_SFT 18
+#define WIFI_RX_SW_POL_HI 18
+#define WIFI_RX_SW_POL_SZ 1
+#define BT_SW_POL_MSK 0x00080000
+#define BT_SW_POL_I_MSK 0xfff7ffff
+#define BT_SW_POL_SFT 19
+#define BT_SW_POL_HI 19
+#define BT_SW_POL_SZ 1
+#define BT_PRI_SMP_TIME_MSK 0x000000ff
+#define BT_PRI_SMP_TIME_I_MSK 0xffffff00
+#define BT_PRI_SMP_TIME_SFT 0
+#define BT_PRI_SMP_TIME_HI 7
+#define BT_PRI_SMP_TIME_SZ 8
+#define BT_STA_SMP_TIME_MSK 0x0000ff00
+#define BT_STA_SMP_TIME_I_MSK 0xffff00ff
+#define BT_STA_SMP_TIME_SFT 8
+#define BT_STA_SMP_TIME_HI 15
+#define BT_STA_SMP_TIME_SZ 8
+#define BEACON_TIMEOUT_MSK 0x00ff0000
+#define BEACON_TIMEOUT_I_MSK 0xff00ffff
+#define BEACON_TIMEOUT_SFT 16
+#define BEACON_TIMEOUT_HI 23
+#define BEACON_TIMEOUT_SZ 8
+#define WLAN_REMAIN_TIME_MSK 0xff000000
+#define WLAN_REMAIN_TIME_I_MSK 0x00ffffff
+#define WLAN_REMAIN_TIME_SFT 24
+#define WLAN_REMAIN_TIME_HI 31
+#define WLAN_REMAIN_TIME_SZ 8
+#define SW_MANUAL_EN_MSK 0x00000001
+#define SW_MANUAL_EN_I_MSK 0xfffffffe
+#define SW_MANUAL_EN_SFT 0
+#define SW_MANUAL_EN_HI 0
+#define SW_MANUAL_EN_SZ 1
+#define SW_WL_TX_MSK 0x00000002
+#define SW_WL_TX_I_MSK 0xfffffffd
+#define SW_WL_TX_SFT 1
+#define SW_WL_TX_HI 1
+#define SW_WL_TX_SZ 1
+#define SW_WL_RX_MSK 0x00000004
+#define SW_WL_RX_I_MSK 0xfffffffb
+#define SW_WL_RX_SFT 2
+#define SW_WL_RX_HI 2
+#define SW_WL_RX_SZ 1
+#define SW_BT_TRX_MSK 0x00000008
+#define SW_BT_TRX_I_MSK 0xfffffff7
+#define SW_BT_TRX_SFT 3
+#define SW_BT_TRX_HI 3
+#define SW_BT_TRX_SZ 1
+#define BT_TXBAR_MANUAL_EN_MSK 0x00000010
+#define BT_TXBAR_MANUAL_EN_I_MSK 0xffffffef
+#define BT_TXBAR_MANUAL_EN_SFT 4
+#define BT_TXBAR_MANUAL_EN_HI 4
+#define BT_TXBAR_MANUAL_EN_SZ 1
+#define BT_TXBAR_SET_MSK 0x00000020
+#define BT_TXBAR_SET_I_MSK 0xffffffdf
+#define BT_TXBAR_SET_SFT 5
+#define BT_TXBAR_SET_HI 5
+#define BT_TXBAR_SET_SZ 1
+#define BT_BUSY_MANUAL_EN_MSK 0x00000100
+#define BT_BUSY_MANUAL_EN_I_MSK 0xfffffeff
+#define BT_BUSY_MANUAL_EN_SFT 8
+#define BT_BUSY_MANUAL_EN_HI 8
+#define BT_BUSY_MANUAL_EN_SZ 1
+#define BT_BUSY_SET_MSK 0x00000200
+#define BT_BUSY_SET_I_MSK 0xfffffdff
+#define BT_BUSY_SET_SFT 9
+#define BT_BUSY_SET_HI 9
+#define BT_BUSY_SET_SZ 1
+#define G0_PKT_CLS_MIB_EN_MSK 0x00000004
+#define G0_PKT_CLS_MIB_EN_I_MSK 0xfffffffb
+#define G0_PKT_CLS_MIB_EN_SFT 2
+#define G0_PKT_CLS_MIB_EN_HI 2
+#define G0_PKT_CLS_MIB_EN_SZ 1
+#define G0_PKT_CLS_ONGOING_MSK 0x00000008
+#define G0_PKT_CLS_ONGOING_I_MSK 0xfffffff7
+#define G0_PKT_CLS_ONGOING_SFT 3
+#define G0_PKT_CLS_ONGOING_HI 3
+#define G0_PKT_CLS_ONGOING_SZ 1
+#define G1_PKT_CLS_MIB_EN_MSK 0x00000010
+#define G1_PKT_CLS_MIB_EN_I_MSK 0xffffffef
+#define G1_PKT_CLS_MIB_EN_SFT 4
+#define G1_PKT_CLS_MIB_EN_HI 4
+#define G1_PKT_CLS_MIB_EN_SZ 1
+#define G1_PKT_CLS_ONGOING_MSK 0x00000020
+#define G1_PKT_CLS_ONGOING_I_MSK 0xffffffdf
+#define G1_PKT_CLS_ONGOING_SFT 5
+#define G1_PKT_CLS_ONGOING_HI 5
+#define G1_PKT_CLS_ONGOING_SZ 1
+#define Q0_PKT_CLS_MIB_EN_MSK 0x00000040
+#define Q0_PKT_CLS_MIB_EN_I_MSK 0xffffffbf
+#define Q0_PKT_CLS_MIB_EN_SFT 6
+#define Q0_PKT_CLS_MIB_EN_HI 6
+#define Q0_PKT_CLS_MIB_EN_SZ 1
+#define Q0_PKT_CLS_ONGOING_MSK 0x00000080
+#define Q0_PKT_CLS_ONGOING_I_MSK 0xffffff7f
+#define Q0_PKT_CLS_ONGOING_SFT 7
+#define Q0_PKT_CLS_ONGOING_HI 7
+#define Q0_PKT_CLS_ONGOING_SZ 1
+#define Q1_PKT_CLS_MIB_EN_MSK 0x00000100
+#define Q1_PKT_CLS_MIB_EN_I_MSK 0xfffffeff
+#define Q1_PKT_CLS_MIB_EN_SFT 8
+#define Q1_PKT_CLS_MIB_EN_HI 8
+#define Q1_PKT_CLS_MIB_EN_SZ 1
+#define Q1_PKT_CLS_ONGOING_MSK 0x00000200
+#define Q1_PKT_CLS_ONGOING_I_MSK 0xfffffdff
+#define Q1_PKT_CLS_ONGOING_SFT 9
+#define Q1_PKT_CLS_ONGOING_HI 9
+#define Q1_PKT_CLS_ONGOING_SZ 1
+#define Q2_PKT_CLS_MIB_EN_MSK 0x00000400
+#define Q2_PKT_CLS_MIB_EN_I_MSK 0xfffffbff
+#define Q2_PKT_CLS_MIB_EN_SFT 10
+#define Q2_PKT_CLS_MIB_EN_HI 10
+#define Q2_PKT_CLS_MIB_EN_SZ 1
+#define Q2_PKT_CLS_ONGOING_MSK 0x00000800
+#define Q2_PKT_CLS_ONGOING_I_MSK 0xfffff7ff
+#define Q2_PKT_CLS_ONGOING_SFT 11
+#define Q2_PKT_CLS_ONGOING_HI 11
+#define Q2_PKT_CLS_ONGOING_SZ 1
+#define Q3_PKT_CLS_MIB_EN_MSK 0x00001000
+#define Q3_PKT_CLS_MIB_EN_I_MSK 0xffffefff
+#define Q3_PKT_CLS_MIB_EN_SFT 12
+#define Q3_PKT_CLS_MIB_EN_HI 12
+#define Q3_PKT_CLS_MIB_EN_SZ 1
+#define Q3_PKT_CLS_ONGOING_MSK 0x00002000
+#define Q3_PKT_CLS_ONGOING_I_MSK 0xffffdfff
+#define Q3_PKT_CLS_ONGOING_SFT 13
+#define Q3_PKT_CLS_ONGOING_HI 13
+#define Q3_PKT_CLS_ONGOING_SZ 1
+#define SCRT_PKT_CLS_MIB_EN_MSK 0x00004000
+#define SCRT_PKT_CLS_MIB_EN_I_MSK 0xffffbfff
+#define SCRT_PKT_CLS_MIB_EN_SFT 14
+#define SCRT_PKT_CLS_MIB_EN_HI 14
+#define SCRT_PKT_CLS_MIB_EN_SZ 1
+#define SCRT_PKT_CLS_ONGOING_MSK 0x00008000
+#define SCRT_PKT_CLS_ONGOING_I_MSK 0xffff7fff
+#define SCRT_PKT_CLS_ONGOING_SFT 15
+#define SCRT_PKT_CLS_ONGOING_HI 15
+#define SCRT_PKT_CLS_ONGOING_SZ 1
+#define MISC_PKT_CLS_MIB_EN_MSK 0x00010000
+#define MISC_PKT_CLS_MIB_EN_I_MSK 0xfffeffff
+#define MISC_PKT_CLS_MIB_EN_SFT 16
+#define MISC_PKT_CLS_MIB_EN_HI 16
+#define MISC_PKT_CLS_MIB_EN_SZ 1
+#define MISC_PKT_CLS_ONGOING_MSK 0x00020000
+#define MISC_PKT_CLS_ONGOING_I_MSK 0xfffdffff
+#define MISC_PKT_CLS_ONGOING_SFT 17
+#define MISC_PKT_CLS_ONGOING_HI 17
+#define MISC_PKT_CLS_ONGOING_SZ 1
+#define MTX_WSID0_SUCC_MSK 0x0000ffff
+#define MTX_WSID0_SUCC_I_MSK 0xffff0000
+#define MTX_WSID0_SUCC_SFT 0
+#define MTX_WSID0_SUCC_HI 15
+#define MTX_WSID0_SUCC_SZ 16
+#define MTX_WSID0_FRM_MSK 0x0000ffff
+#define MTX_WSID0_FRM_I_MSK 0xffff0000
+#define MTX_WSID0_FRM_SFT 0
+#define MTX_WSID0_FRM_HI 15
+#define MTX_WSID0_FRM_SZ 16
+#define MTX_WSID0_RETRY_MSK 0x0000ffff
+#define MTX_WSID0_RETRY_I_MSK 0xffff0000
+#define MTX_WSID0_RETRY_SFT 0
+#define MTX_WSID0_RETRY_HI 15
+#define MTX_WSID0_RETRY_SZ 16
+#define MTX_WSID0_TOTAL_MSK 0x0000ffff
+#define MTX_WSID0_TOTAL_I_MSK 0xffff0000
+#define MTX_WSID0_TOTAL_SFT 0
+#define MTX_WSID0_TOTAL_HI 15
+#define MTX_WSID0_TOTAL_SZ 16
+#define MTX_GRP_MSK 0x000fffff
+#define MTX_GRP_I_MSK 0xfff00000
+#define MTX_GRP_SFT 0
+#define MTX_GRP_HI 19
+#define MTX_GRP_SZ 20
+#define MTX_FAIL_MSK 0x0000ffff
+#define MTX_FAIL_I_MSK 0xffff0000
+#define MTX_FAIL_SFT 0
+#define MTX_FAIL_HI 15
+#define MTX_FAIL_SZ 16
+#define MTX_RETRY_MSK 0x000fffff
+#define MTX_RETRY_I_MSK 0xfff00000
+#define MTX_RETRY_SFT 0
+#define MTX_RETRY_HI 19
+#define MTX_RETRY_SZ 20
+#define MTX_MULTI_RETRY_MSK 0x000fffff
+#define MTX_MULTI_RETRY_I_MSK 0xfff00000
+#define MTX_MULTI_RETRY_SFT 0
+#define MTX_MULTI_RETRY_HI 19
+#define MTX_MULTI_RETRY_SZ 20
+#define MTX_RTS_SUCC_MSK 0x0000ffff
+#define MTX_RTS_SUCC_I_MSK 0xffff0000
+#define MTX_RTS_SUCC_SFT 0
+#define MTX_RTS_SUCC_HI 15
+#define MTX_RTS_SUCC_SZ 16
+#define MTX_RTS_FAIL_MSK 0x0000ffff
+#define MTX_RTS_FAIL_I_MSK 0xffff0000
+#define MTX_RTS_FAIL_SFT 0
+#define MTX_RTS_FAIL_HI 15
+#define MTX_RTS_FAIL_SZ 16
+#define MTX_ACK_FAIL_MSK 0x0000ffff
+#define MTX_ACK_FAIL_I_MSK 0xffff0000
+#define MTX_ACK_FAIL_SFT 0
+#define MTX_ACK_FAIL_HI 15
+#define MTX_ACK_FAIL_SZ 16
+#define MTX_FRM_MSK 0x000fffff
+#define MTX_FRM_I_MSK 0xfff00000
+#define MTX_FRM_SFT 0
+#define MTX_FRM_HI 19
+#define MTX_FRM_SZ 20
+#define MTX_ACK_TX_MSK 0x0000ffff
+#define MTX_ACK_TX_I_MSK 0xffff0000
+#define MTX_ACK_TX_SFT 0
+#define MTX_ACK_TX_HI 15
+#define MTX_ACK_TX_SZ 16
+#define MTX_CTS_TX_MSK 0x0000ffff
+#define MTX_CTS_TX_I_MSK 0xffff0000
+#define MTX_CTS_TX_SFT 0
+#define MTX_CTS_TX_HI 15
+#define MTX_CTS_TX_SZ 16
+#define MRX_DUP_MSK 0x0000ffff
+#define MRX_DUP_I_MSK 0xffff0000
+#define MRX_DUP_SFT 0
+#define MRX_DUP_HI 15
+#define MRX_DUP_SZ 16
+#define MRX_FRG_MSK 0x000fffff
+#define MRX_FRG_I_MSK 0xfff00000
+#define MRX_FRG_SFT 0
+#define MRX_FRG_HI 19
+#define MRX_FRG_SZ 20
+#define MRX_GRP_MSK 0x000fffff
+#define MRX_GRP_I_MSK 0xfff00000
+#define MRX_GRP_SFT 0
+#define MRX_GRP_HI 19
+#define MRX_GRP_SZ 20
+#define MRX_FCS_ERR_MSK 0x0000ffff
+#define MRX_FCS_ERR_I_MSK 0xffff0000
+#define MRX_FCS_ERR_SFT 0
+#define MRX_FCS_ERR_HI 15
+#define MRX_FCS_ERR_SZ 16
+#define MRX_FCS_SUC_MSK 0x0000ffff
+#define MRX_FCS_SUC_I_MSK 0xffff0000
+#define MRX_FCS_SUC_SFT 0
+#define MRX_FCS_SUC_HI 15
+#define MRX_FCS_SUC_SZ 16
+#define MRX_MISS_MSK 0x0000ffff
+#define MRX_MISS_I_MSK 0xffff0000
+#define MRX_MISS_SFT 0
+#define MRX_MISS_HI 15
+#define MRX_MISS_SZ 16
+#define MRX_ALC_FAIL_MSK 0x0000ffff
+#define MRX_ALC_FAIL_I_MSK 0xffff0000
+#define MRX_ALC_FAIL_SFT 0
+#define MRX_ALC_FAIL_HI 15
+#define MRX_ALC_FAIL_SZ 16
+#define MRX_DAT_NTF_MSK 0x0000ffff
+#define MRX_DAT_NTF_I_MSK 0xffff0000
+#define MRX_DAT_NTF_SFT 0
+#define MRX_DAT_NTF_HI 15
+#define MRX_DAT_NTF_SZ 16
+#define MRX_RTS_NTF_MSK 0x0000ffff
+#define MRX_RTS_NTF_I_MSK 0xffff0000
+#define MRX_RTS_NTF_SFT 0
+#define MRX_RTS_NTF_HI 15
+#define MRX_RTS_NTF_SZ 16
+#define MRX_CTS_NTF_MSK 0x0000ffff
+#define MRX_CTS_NTF_I_MSK 0xffff0000
+#define MRX_CTS_NTF_SFT 0
+#define MRX_CTS_NTF_HI 15
+#define MRX_CTS_NTF_SZ 16
+#define MRX_ACK_NTF_MSK 0x0000ffff
+#define MRX_ACK_NTF_I_MSK 0xffff0000
+#define MRX_ACK_NTF_SFT 0
+#define MRX_ACK_NTF_HI 15
+#define MRX_ACK_NTF_SZ 16
+#define MRX_BA_NTF_MSK 0x0000ffff
+#define MRX_BA_NTF_I_MSK 0xffff0000
+#define MRX_BA_NTF_SFT 0
+#define MRX_BA_NTF_HI 15
+#define MRX_BA_NTF_SZ 16
+#define MRX_DATA_NTF_MSK 0x0000ffff
+#define MRX_DATA_NTF_I_MSK 0xffff0000
+#define MRX_DATA_NTF_SFT 0
+#define MRX_DATA_NTF_HI 15
+#define MRX_DATA_NTF_SZ 16
+#define MRX_MNG_NTF_MSK 0x0000ffff
+#define MRX_MNG_NTF_I_MSK 0xffff0000
+#define MRX_MNG_NTF_SFT 0
+#define MRX_MNG_NTF_HI 15
+#define MRX_MNG_NTF_SZ 16
+#define MRX_DAT_CRC_NTF_MSK 0x0000ffff
+#define MRX_DAT_CRC_NTF_I_MSK 0xffff0000
+#define MRX_DAT_CRC_NTF_SFT 0
+#define MRX_DAT_CRC_NTF_HI 15
+#define MRX_DAT_CRC_NTF_SZ 16
+#define MRX_BAR_NTF_MSK 0x0000ffff
+#define MRX_BAR_NTF_I_MSK 0xffff0000
+#define MRX_BAR_NTF_SFT 0
+#define MRX_BAR_NTF_HI 15
+#define MRX_BAR_NTF_SZ 16
+#define MRX_MB_MISS_MSK 0x0000ffff
+#define MRX_MB_MISS_I_MSK 0xffff0000
+#define MRX_MB_MISS_SFT 0
+#define MRX_MB_MISS_HI 15
+#define MRX_MB_MISS_SZ 16
+#define MRX_NIDLE_MISS_MSK 0x0000ffff
+#define MRX_NIDLE_MISS_I_MSK 0xffff0000
+#define MRX_NIDLE_MISS_SFT 0
+#define MRX_NIDLE_MISS_HI 15
+#define MRX_NIDLE_MISS_SZ 16
+#define MRX_CSR_NTF_MSK 0x0000ffff
+#define MRX_CSR_NTF_I_MSK 0xffff0000
+#define MRX_CSR_NTF_SFT 0
+#define MRX_CSR_NTF_HI 15
+#define MRX_CSR_NTF_SZ 16
+#define DBG_Q0_SUCC_MSK 0x0000ffff
+#define DBG_Q0_SUCC_I_MSK 0xffff0000
+#define DBG_Q0_SUCC_SFT 0
+#define DBG_Q0_SUCC_HI 15
+#define DBG_Q0_SUCC_SZ 16
+#define DBG_Q0_FAIL_MSK 0x0000ffff
+#define DBG_Q0_FAIL_I_MSK 0xffff0000
+#define DBG_Q0_FAIL_SFT 0
+#define DBG_Q0_FAIL_HI 15
+#define DBG_Q0_FAIL_SZ 16
+#define DBG_Q0_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q0_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q0_ACK_SUCC_SFT 0
+#define DBG_Q0_ACK_SUCC_HI 15
+#define DBG_Q0_ACK_SUCC_SZ 16
+#define DBG_Q0_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q0_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q0_ACK_FAIL_SFT 0
+#define DBG_Q0_ACK_FAIL_HI 15
+#define DBG_Q0_ACK_FAIL_SZ 16
+#define DBG_Q1_SUCC_MSK 0x0000ffff
+#define DBG_Q1_SUCC_I_MSK 0xffff0000
+#define DBG_Q1_SUCC_SFT 0
+#define DBG_Q1_SUCC_HI 15
+#define DBG_Q1_SUCC_SZ 16
+#define DBG_Q1_FAIL_MSK 0x0000ffff
+#define DBG_Q1_FAIL_I_MSK 0xffff0000
+#define DBG_Q1_FAIL_SFT 0
+#define DBG_Q1_FAIL_HI 15
+#define DBG_Q1_FAIL_SZ 16
+#define DBG_Q1_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q1_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q1_ACK_SUCC_SFT 0
+#define DBG_Q1_ACK_SUCC_HI 15
+#define DBG_Q1_ACK_SUCC_SZ 16
+#define DBG_Q1_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q1_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q1_ACK_FAIL_SFT 0
+#define DBG_Q1_ACK_FAIL_HI 15
+#define DBG_Q1_ACK_FAIL_SZ 16
+#define DBG_Q2_SUCC_MSK 0x0000ffff
+#define DBG_Q2_SUCC_I_MSK 0xffff0000
+#define DBG_Q2_SUCC_SFT 0
+#define DBG_Q2_SUCC_HI 15
+#define DBG_Q2_SUCC_SZ 16
+#define DBG_Q2_FAIL_MSK 0x0000ffff
+#define DBG_Q2_FAIL_I_MSK 0xffff0000
+#define DBG_Q2_FAIL_SFT 0
+#define DBG_Q2_FAIL_HI 15
+#define DBG_Q2_FAIL_SZ 16
+#define DBG_Q2_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q2_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q2_ACK_SUCC_SFT 0
+#define DBG_Q2_ACK_SUCC_HI 15
+#define DBG_Q2_ACK_SUCC_SZ 16
+#define DBG_Q2_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q2_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q2_ACK_FAIL_SFT 0
+#define DBG_Q2_ACK_FAIL_HI 15
+#define DBG_Q2_ACK_FAIL_SZ 16
+#define DBG_Q3_SUCC_MSK 0x0000ffff
+#define DBG_Q3_SUCC_I_MSK 0xffff0000
+#define DBG_Q3_SUCC_SFT 0
+#define DBG_Q3_SUCC_HI 15
+#define DBG_Q3_SUCC_SZ 16
+#define DBG_Q3_FAIL_MSK 0x0000ffff
+#define DBG_Q3_FAIL_I_MSK 0xffff0000
+#define DBG_Q3_FAIL_SFT 0
+#define DBG_Q3_FAIL_HI 15
+#define DBG_Q3_FAIL_SZ 16
+#define DBG_Q3_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q3_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q3_ACK_SUCC_SFT 0
+#define DBG_Q3_ACK_SUCC_HI 15
+#define DBG_Q3_ACK_SUCC_SZ 16
+#define DBG_Q3_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q3_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q3_ACK_FAIL_SFT 0
+#define DBG_Q3_ACK_FAIL_HI 15
+#define DBG_Q3_ACK_FAIL_SZ 16
+#define SCRT_TKIP_CERR_MSK 0x000fffff
+#define SCRT_TKIP_CERR_I_MSK 0xfff00000
+#define SCRT_TKIP_CERR_SFT 0
+#define SCRT_TKIP_CERR_HI 19
+#define SCRT_TKIP_CERR_SZ 20
+#define SCRT_TKIP_MIC_ERR_MSK 0x000fffff
+#define SCRT_TKIP_MIC_ERR_I_MSK 0xfff00000
+#define SCRT_TKIP_MIC_ERR_SFT 0
+#define SCRT_TKIP_MIC_ERR_HI 19
+#define SCRT_TKIP_MIC_ERR_SZ 20
+#define SCRT_TKIP_RPLY_MSK 0x000fffff
+#define SCRT_TKIP_RPLY_I_MSK 0xfff00000
+#define SCRT_TKIP_RPLY_SFT 0
+#define SCRT_TKIP_RPLY_HI 19
+#define SCRT_TKIP_RPLY_SZ 20
+#define SCRT_CCMP_RPLY_MSK 0x000fffff
+#define SCRT_CCMP_RPLY_I_MSK 0xfff00000
+#define SCRT_CCMP_RPLY_SFT 0
+#define SCRT_CCMP_RPLY_HI 19
+#define SCRT_CCMP_RPLY_SZ 20
+#define SCRT_CCMP_CERR_MSK 0x000fffff
+#define SCRT_CCMP_CERR_I_MSK 0xfff00000
+#define SCRT_CCMP_CERR_SFT 0
+#define SCRT_CCMP_CERR_HI 19
+#define SCRT_CCMP_CERR_SZ 20
+#define DBG_LEN_CRC_FAIL_MSK 0x0000ffff
+#define DBG_LEN_CRC_FAIL_I_MSK 0xffff0000
+#define DBG_LEN_CRC_FAIL_SFT 0
+#define DBG_LEN_CRC_FAIL_HI 15
+#define DBG_LEN_CRC_FAIL_SZ 16
+#define DBG_LEN_ALC_FAIL_MSK 0x0000ffff
+#define DBG_LEN_ALC_FAIL_I_MSK 0xffff0000
+#define DBG_LEN_ALC_FAIL_SFT 0
+#define DBG_LEN_ALC_FAIL_HI 15
+#define DBG_LEN_ALC_FAIL_SZ 16
+#define DBG_AMPDU_PASS_MSK 0x0000ffff
+#define DBG_AMPDU_PASS_I_MSK 0xffff0000
+#define DBG_AMPDU_PASS_SFT 0
+#define DBG_AMPDU_PASS_HI 15
+#define DBG_AMPDU_PASS_SZ 16
+#define DBG_AMPDU_FAIL_MSK 0x0000ffff
+#define DBG_AMPDU_FAIL_I_MSK 0xffff0000
+#define DBG_AMPDU_FAIL_SFT 0
+#define DBG_AMPDU_FAIL_HI 15
+#define DBG_AMPDU_FAIL_SZ 16
+#define RXID_ALC_CNT_FAIL_MSK 0x0000ffff
+#define RXID_ALC_CNT_FAIL_I_MSK 0xffff0000
+#define RXID_ALC_CNT_FAIL_SFT 0
+#define RXID_ALC_CNT_FAIL_HI 15
+#define RXID_ALC_CNT_FAIL_SZ 16
+#define RXID_ALC_LEN_FAIL_MSK 0x0000ffff
+#define RXID_ALC_LEN_FAIL_I_MSK 0xffff0000
+#define RXID_ALC_LEN_FAIL_SFT 0
+#define RXID_ALC_LEN_FAIL_HI 15
+#define RXID_ALC_LEN_FAIL_SZ 16
+#define CBR_RG_EN_MANUAL_MSK 0x00000001
+#define CBR_RG_EN_MANUAL_I_MSK 0xfffffffe
+#define CBR_RG_EN_MANUAL_SFT 0
+#define CBR_RG_EN_MANUAL_HI 0
+#define CBR_RG_EN_MANUAL_SZ 1
+#define CBR_RG_TX_EN_MSK 0x00000002
+#define CBR_RG_TX_EN_I_MSK 0xfffffffd
+#define CBR_RG_TX_EN_SFT 1
+#define CBR_RG_TX_EN_HI 1
+#define CBR_RG_TX_EN_SZ 1
+#define CBR_RG_TX_PA_EN_MSK 0x00000004
+#define CBR_RG_TX_PA_EN_I_MSK 0xfffffffb
+#define CBR_RG_TX_PA_EN_SFT 2
+#define CBR_RG_TX_PA_EN_HI 2
+#define CBR_RG_TX_PA_EN_SZ 1
+#define CBR_RG_TX_DAC_EN_MSK 0x00000008
+#define CBR_RG_TX_DAC_EN_I_MSK 0xfffffff7
+#define CBR_RG_TX_DAC_EN_SFT 3
+#define CBR_RG_TX_DAC_EN_HI 3
+#define CBR_RG_TX_DAC_EN_SZ 1
+#define CBR_RG_RX_AGC_MSK 0x00000010
+#define CBR_RG_RX_AGC_I_MSK 0xffffffef
+#define CBR_RG_RX_AGC_SFT 4
+#define CBR_RG_RX_AGC_HI 4
+#define CBR_RG_RX_AGC_SZ 1
+#define CBR_RG_RX_GAIN_MANUAL_MSK 0x00000020
+#define CBR_RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
+#define CBR_RG_RX_GAIN_MANUAL_SFT 5
+#define CBR_RG_RX_GAIN_MANUAL_HI 5
+#define CBR_RG_RX_GAIN_MANUAL_SZ 1
+#define CBR_RG_RFG_MSK 0x000000c0
+#define CBR_RG_RFG_I_MSK 0xffffff3f
+#define CBR_RG_RFG_SFT 6
+#define CBR_RG_RFG_HI 7
+#define CBR_RG_RFG_SZ 2
+#define CBR_RG_PGAG_MSK 0x00000f00
+#define CBR_RG_PGAG_I_MSK 0xfffff0ff
+#define CBR_RG_PGAG_SFT 8
+#define CBR_RG_PGAG_HI 11
+#define CBR_RG_PGAG_SZ 4
+#define CBR_RG_MODE_MSK 0x00003000
+#define CBR_RG_MODE_I_MSK 0xffffcfff
+#define CBR_RG_MODE_SFT 12
+#define CBR_RG_MODE_HI 13
+#define CBR_RG_MODE_SZ 2
+#define CBR_RG_EN_TX_TRSW_MSK 0x00004000
+#define CBR_RG_EN_TX_TRSW_I_MSK 0xffffbfff
+#define CBR_RG_EN_TX_TRSW_SFT 14
+#define CBR_RG_EN_TX_TRSW_HI 14
+#define CBR_RG_EN_TX_TRSW_SZ 1
+#define CBR_RG_EN_SX_MSK 0x00008000
+#define CBR_RG_EN_SX_I_MSK 0xffff7fff
+#define CBR_RG_EN_SX_SFT 15
+#define CBR_RG_EN_SX_HI 15
+#define CBR_RG_EN_SX_SZ 1
+#define CBR_RG_EN_RX_LNA_MSK 0x00010000
+#define CBR_RG_EN_RX_LNA_I_MSK 0xfffeffff
+#define CBR_RG_EN_RX_LNA_SFT 16
+#define CBR_RG_EN_RX_LNA_HI 16
+#define CBR_RG_EN_RX_LNA_SZ 1
+#define CBR_RG_EN_RX_MIXER_MSK 0x00020000
+#define CBR_RG_EN_RX_MIXER_I_MSK 0xfffdffff
+#define CBR_RG_EN_RX_MIXER_SFT 17
+#define CBR_RG_EN_RX_MIXER_HI 17
+#define CBR_RG_EN_RX_MIXER_SZ 1
+#define CBR_RG_EN_RX_DIV2_MSK 0x00040000
+#define CBR_RG_EN_RX_DIV2_I_MSK 0xfffbffff
+#define CBR_RG_EN_RX_DIV2_SFT 18
+#define CBR_RG_EN_RX_DIV2_HI 18
+#define CBR_RG_EN_RX_DIV2_SZ 1
+#define CBR_RG_EN_RX_LOBUF_MSK 0x00080000
+#define CBR_RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
+#define CBR_RG_EN_RX_LOBUF_SFT 19
+#define CBR_RG_EN_RX_LOBUF_HI 19
+#define CBR_RG_EN_RX_LOBUF_SZ 1
+#define CBR_RG_EN_RX_TZ_MSK 0x00100000
+#define CBR_RG_EN_RX_TZ_I_MSK 0xffefffff
+#define CBR_RG_EN_RX_TZ_SFT 20
+#define CBR_RG_EN_RX_TZ_HI 20
+#define CBR_RG_EN_RX_TZ_SZ 1
+#define CBR_RG_EN_RX_FILTER_MSK 0x00200000
+#define CBR_RG_EN_RX_FILTER_I_MSK 0xffdfffff
+#define CBR_RG_EN_RX_FILTER_SFT 21
+#define CBR_RG_EN_RX_FILTER_HI 21
+#define CBR_RG_EN_RX_FILTER_SZ 1
+#define CBR_RG_EN_RX_HPF_MSK 0x00400000
+#define CBR_RG_EN_RX_HPF_I_MSK 0xffbfffff
+#define CBR_RG_EN_RX_HPF_SFT 22
+#define CBR_RG_EN_RX_HPF_HI 22
+#define CBR_RG_EN_RX_HPF_SZ 1
+#define CBR_RG_EN_RX_RSSI_MSK 0x00800000
+#define CBR_RG_EN_RX_RSSI_I_MSK 0xff7fffff
+#define CBR_RG_EN_RX_RSSI_SFT 23
+#define CBR_RG_EN_RX_RSSI_HI 23
+#define CBR_RG_EN_RX_RSSI_SZ 1
+#define CBR_RG_EN_ADC_MSK 0x01000000
+#define CBR_RG_EN_ADC_I_MSK 0xfeffffff
+#define CBR_RG_EN_ADC_SFT 24
+#define CBR_RG_EN_ADC_HI 24
+#define CBR_RG_EN_ADC_SZ 1
+#define CBR_RG_EN_TX_MOD_MSK 0x02000000
+#define CBR_RG_EN_TX_MOD_I_MSK 0xfdffffff
+#define CBR_RG_EN_TX_MOD_SFT 25
+#define CBR_RG_EN_TX_MOD_HI 25
+#define CBR_RG_EN_TX_MOD_SZ 1
+#define CBR_RG_EN_TX_DIV2_MSK 0x04000000
+#define CBR_RG_EN_TX_DIV2_I_MSK 0xfbffffff
+#define CBR_RG_EN_TX_DIV2_SFT 26
+#define CBR_RG_EN_TX_DIV2_HI 26
+#define CBR_RG_EN_TX_DIV2_SZ 1
+#define CBR_RG_EN_TX_DIV2_BUF_MSK 0x08000000
+#define CBR_RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
+#define CBR_RG_EN_TX_DIV2_BUF_SFT 27
+#define CBR_RG_EN_TX_DIV2_BUF_HI 27
+#define CBR_RG_EN_TX_DIV2_BUF_SZ 1
+#define CBR_RG_EN_TX_LOBF_MSK 0x10000000
+#define CBR_RG_EN_TX_LOBF_I_MSK 0xefffffff
+#define CBR_RG_EN_TX_LOBF_SFT 28
+#define CBR_RG_EN_TX_LOBF_HI 28
+#define CBR_RG_EN_TX_LOBF_SZ 1
+#define CBR_RG_EN_RX_LOBF_MSK 0x20000000
+#define CBR_RG_EN_RX_LOBF_I_MSK 0xdfffffff
+#define CBR_RG_EN_RX_LOBF_SFT 29
+#define CBR_RG_EN_RX_LOBF_HI 29
+#define CBR_RG_EN_RX_LOBF_SZ 1
+#define CBR_RG_SEL_DPLL_CLK_MSK 0x40000000
+#define CBR_RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
+#define CBR_RG_SEL_DPLL_CLK_SFT 30
+#define CBR_RG_SEL_DPLL_CLK_HI 30
+#define CBR_RG_SEL_DPLL_CLK_SZ 1
+#define CBR_RG_EN_TX_DPD_MSK 0x00000001
+#define CBR_RG_EN_TX_DPD_I_MSK 0xfffffffe
+#define CBR_RG_EN_TX_DPD_SFT 0
+#define CBR_RG_EN_TX_DPD_HI 0
+#define CBR_RG_EN_TX_DPD_SZ 1
+#define CBR_RG_EN_TX_TSSI_MSK 0x00000002
+#define CBR_RG_EN_TX_TSSI_I_MSK 0xfffffffd
+#define CBR_RG_EN_TX_TSSI_SFT 1
+#define CBR_RG_EN_TX_TSSI_HI 1
+#define CBR_RG_EN_TX_TSSI_SZ 1
+#define CBR_RG_EN_RX_IQCAL_MSK 0x00000004
+#define CBR_RG_EN_RX_IQCAL_I_MSK 0xfffffffb
+#define CBR_RG_EN_RX_IQCAL_SFT 2
+#define CBR_RG_EN_RX_IQCAL_HI 2
+#define CBR_RG_EN_RX_IQCAL_SZ 1
+#define CBR_RG_EN_TX_DAC_CAL_MSK 0x00000008
+#define CBR_RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
+#define CBR_RG_EN_TX_DAC_CAL_SFT 3
+#define CBR_RG_EN_TX_DAC_CAL_HI 3
+#define CBR_RG_EN_TX_DAC_CAL_SZ 1
+#define CBR_RG_EN_TX_SELF_MIXER_MSK 0x00000010
+#define CBR_RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
+#define CBR_RG_EN_TX_SELF_MIXER_SFT 4
+#define CBR_RG_EN_TX_SELF_MIXER_HI 4
+#define CBR_RG_EN_TX_SELF_MIXER_SZ 1
+#define CBR_RG_EN_TX_DAC_OUT_MSK 0x00000020
+#define CBR_RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
+#define CBR_RG_EN_TX_DAC_OUT_SFT 5
+#define CBR_RG_EN_TX_DAC_OUT_HI 5
+#define CBR_RG_EN_TX_DAC_OUT_SZ 1
+#define CBR_RG_EN_LDO_RX_FE_MSK 0x00000040
+#define CBR_RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
+#define CBR_RG_EN_LDO_RX_FE_SFT 6
+#define CBR_RG_EN_LDO_RX_FE_HI 6
+#define CBR_RG_EN_LDO_RX_FE_SZ 1
+#define CBR_RG_EN_LDO_ABB_MSK 0x00000080
+#define CBR_RG_EN_LDO_ABB_I_MSK 0xffffff7f
+#define CBR_RG_EN_LDO_ABB_SFT 7
+#define CBR_RG_EN_LDO_ABB_HI 7
+#define CBR_RG_EN_LDO_ABB_SZ 1
+#define CBR_RG_EN_LDO_AFE_MSK 0x00000100
+#define CBR_RG_EN_LDO_AFE_I_MSK 0xfffffeff
+#define CBR_RG_EN_LDO_AFE_SFT 8
+#define CBR_RG_EN_LDO_AFE_HI 8
+#define CBR_RG_EN_LDO_AFE_SZ 1
+#define CBR_RG_EN_SX_CHPLDO_MSK 0x00000200
+#define CBR_RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
+#define CBR_RG_EN_SX_CHPLDO_SFT 9
+#define CBR_RG_EN_SX_CHPLDO_HI 9
+#define CBR_RG_EN_SX_CHPLDO_SZ 1
+#define CBR_RG_EN_SX_LOBFLDO_MSK 0x00000400
+#define CBR_RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
+#define CBR_RG_EN_SX_LOBFLDO_SFT 10
+#define CBR_RG_EN_SX_LOBFLDO_HI 10
+#define CBR_RG_EN_SX_LOBFLDO_SZ 1
+#define CBR_RG_EN_IREF_RX_MSK 0x00000800
+#define CBR_RG_EN_IREF_RX_I_MSK 0xfffff7ff
+#define CBR_RG_EN_IREF_RX_SFT 11
+#define CBR_RG_EN_IREF_RX_HI 11
+#define CBR_RG_EN_IREF_RX_SZ 1
+#define CBR_RG_DCDC_MODE_MSK 0x00001000
+#define CBR_RG_DCDC_MODE_I_MSK 0xffffefff
+#define CBR_RG_DCDC_MODE_SFT 12
+#define CBR_RG_DCDC_MODE_HI 12
+#define CBR_RG_DCDC_MODE_SZ 1
+#define CBR_RG_LDO_LEVEL_RX_FE_MSK 0x00000007
+#define CBR_RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
+#define CBR_RG_LDO_LEVEL_RX_FE_SFT 0
+#define CBR_RG_LDO_LEVEL_RX_FE_HI 2
+#define CBR_RG_LDO_LEVEL_RX_FE_SZ 3
+#define CBR_RG_LDO_LEVEL_ABB_MSK 0x00000038
+#define CBR_RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
+#define CBR_RG_LDO_LEVEL_ABB_SFT 3
+#define CBR_RG_LDO_LEVEL_ABB_HI 5
+#define CBR_RG_LDO_LEVEL_ABB_SZ 3
+#define CBR_RG_LDO_LEVEL_AFE_MSK 0x000001c0
+#define CBR_RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
+#define CBR_RG_LDO_LEVEL_AFE_SFT 6
+#define CBR_RG_LDO_LEVEL_AFE_HI 8
+#define CBR_RG_LDO_LEVEL_AFE_SZ 3
+#define CBR_RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
+#define CBR_RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
+#define CBR_RG_SX_LDO_CHP_LEVEL_SFT 9
+#define CBR_RG_SX_LDO_CHP_LEVEL_HI 11
+#define CBR_RG_SX_LDO_CHP_LEVEL_SZ 3
+#define CBR_RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
+#define CBR_RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
+#define CBR_RG_SX_LDO_LOBF_LEVEL_SFT 12
+#define CBR_RG_SX_LDO_LOBF_LEVEL_HI 14
+#define CBR_RG_SX_LDO_LOBF_LEVEL_SZ 3
+#define CBR_RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
+#define CBR_RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
+#define CBR_RG_SX_LDO_XOSC_LEVEL_SFT 15
+#define CBR_RG_SX_LDO_XOSC_LEVEL_HI 17
+#define CBR_RG_SX_LDO_XOSC_LEVEL_SZ 3
+#define CBR_RG_DP_LDO_LEVEL_MSK 0x001c0000
+#define CBR_RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
+#define CBR_RG_DP_LDO_LEVEL_SFT 18
+#define CBR_RG_DP_LDO_LEVEL_HI 20
+#define CBR_RG_DP_LDO_LEVEL_SZ 3
+#define CBR_RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
+#define CBR_RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
+#define CBR_RG_SX_LDO_VCO_LEVEL_SFT 21
+#define CBR_RG_SX_LDO_VCO_LEVEL_HI 23
+#define CBR_RG_SX_LDO_VCO_LEVEL_SZ 3
+#define CBR_RG_TX_LDO_TX_LEVEL_MSK 0x07000000
+#define CBR_RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
+#define CBR_RG_TX_LDO_TX_LEVEL_SFT 24
+#define CBR_RG_TX_LDO_TX_LEVEL_HI 26
+#define CBR_RG_TX_LDO_TX_LEVEL_SZ 3
+#define CBR_RG_BUCK_LEVEL_MSK 0x38000000
+#define CBR_RG_BUCK_LEVEL_I_MSK 0xc7ffffff
+#define CBR_RG_BUCK_LEVEL_SFT 27
+#define CBR_RG_BUCK_LEVEL_HI 29
+#define CBR_RG_BUCK_LEVEL_SZ 3
+#define CBR_RG_EN_RX_PADSW_MSK 0x00000001
+#define CBR_RG_EN_RX_PADSW_I_MSK 0xfffffffe
+#define CBR_RG_EN_RX_PADSW_SFT 0
+#define CBR_RG_EN_RX_PADSW_HI 0
+#define CBR_RG_EN_RX_PADSW_SZ 1
+#define CBR_RG_EN_RX_TESTNODE_MSK 0x00000002
+#define CBR_RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
+#define CBR_RG_EN_RX_TESTNODE_SFT 1
+#define CBR_RG_EN_RX_TESTNODE_HI 1
+#define CBR_RG_EN_RX_TESTNODE_SZ 1
+#define CBR_RG_RX_ABBCFIX_MSK 0x00000004
+#define CBR_RG_RX_ABBCFIX_I_MSK 0xfffffffb
+#define CBR_RG_RX_ABBCFIX_SFT 2
+#define CBR_RG_RX_ABBCFIX_HI 2
+#define CBR_RG_RX_ABBCFIX_SZ 1
+#define CBR_RG_RX_ABBCTUNE_MSK 0x000001f8
+#define CBR_RG_RX_ABBCTUNE_I_MSK 0xfffffe07
+#define CBR_RG_RX_ABBCTUNE_SFT 3
+#define CBR_RG_RX_ABBCTUNE_HI 8
+#define CBR_RG_RX_ABBCTUNE_SZ 6
+#define CBR_RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
+#define CBR_RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
+#define CBR_RG_RX_ABBOUT_TRI_STATE_SFT 9
+#define CBR_RG_RX_ABBOUT_TRI_STATE_HI 9
+#define CBR_RG_RX_ABBOUT_TRI_STATE_SZ 1
+#define CBR_RG_RX_ABB_N_MODE_MSK 0x00000400
+#define CBR_RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
+#define CBR_RG_RX_ABB_N_MODE_SFT 10
+#define CBR_RG_RX_ABB_N_MODE_HI 10
+#define CBR_RG_RX_ABB_N_MODE_SZ 1
+#define CBR_RG_RX_EN_LOOPA_MSK 0x00000800
+#define CBR_RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
+#define CBR_RG_RX_EN_LOOPA_SFT 11
+#define CBR_RG_RX_EN_LOOPA_HI 11
+#define CBR_RG_RX_EN_LOOPA_SZ 1
+#define CBR_RG_RX_FILTERI1ST_MSK 0x00003000
+#define CBR_RG_RX_FILTERI1ST_I_MSK 0xffffcfff
+#define CBR_RG_RX_FILTERI1ST_SFT 12
+#define CBR_RG_RX_FILTERI1ST_HI 13
+#define CBR_RG_RX_FILTERI1ST_SZ 2
+#define CBR_RG_RX_FILTERI2ND_MSK 0x0000c000
+#define CBR_RG_RX_FILTERI2ND_I_MSK 0xffff3fff
+#define CBR_RG_RX_FILTERI2ND_SFT 14
+#define CBR_RG_RX_FILTERI2ND_HI 15
+#define CBR_RG_RX_FILTERI2ND_SZ 2
+#define CBR_RG_RX_FILTERI3RD_MSK 0x00030000
+#define CBR_RG_RX_FILTERI3RD_I_MSK 0xfffcffff
+#define CBR_RG_RX_FILTERI3RD_SFT 16
+#define CBR_RG_RX_FILTERI3RD_HI 17
+#define CBR_RG_RX_FILTERI3RD_SZ 2
+#define CBR_RG_RX_FILTERI_COURSE_MSK 0x000c0000
+#define CBR_RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
+#define CBR_RG_RX_FILTERI_COURSE_SFT 18
+#define CBR_RG_RX_FILTERI_COURSE_HI 19
+#define CBR_RG_RX_FILTERI_COURSE_SZ 2
+#define CBR_RG_RX_FILTERVCM_MSK 0x00300000
+#define CBR_RG_RX_FILTERVCM_I_MSK 0xffcfffff
+#define CBR_RG_RX_FILTERVCM_SFT 20
+#define CBR_RG_RX_FILTERVCM_HI 21
+#define CBR_RG_RX_FILTERVCM_SZ 2
+#define CBR_RG_RX_HPF3M_MSK 0x00400000
+#define CBR_RG_RX_HPF3M_I_MSK 0xffbfffff
+#define CBR_RG_RX_HPF3M_SFT 22
+#define CBR_RG_RX_HPF3M_HI 22
+#define CBR_RG_RX_HPF3M_SZ 1
+#define CBR_RG_RX_HPF300K_MSK 0x00800000
+#define CBR_RG_RX_HPF300K_I_MSK 0xff7fffff
+#define CBR_RG_RX_HPF300K_SFT 23
+#define CBR_RG_RX_HPF300K_HI 23
+#define CBR_RG_RX_HPF300K_SZ 1
+#define CBR_RG_RX_HPFI_MSK 0x03000000
+#define CBR_RG_RX_HPFI_I_MSK 0xfcffffff
+#define CBR_RG_RX_HPFI_SFT 24
+#define CBR_RG_RX_HPFI_HI 25
+#define CBR_RG_RX_HPFI_SZ 2
+#define CBR_RG_RX_HPF_FINALCORNER_MSK 0x0c000000
+#define CBR_RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
+#define CBR_RG_RX_HPF_FINALCORNER_SFT 26
+#define CBR_RG_RX_HPF_FINALCORNER_HI 27
+#define CBR_RG_RX_HPF_FINALCORNER_SZ 2
+#define CBR_RG_RX_HPF_SETTLE1_C_MSK 0x30000000
+#define CBR_RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
+#define CBR_RG_RX_HPF_SETTLE1_C_SFT 28
+#define CBR_RG_RX_HPF_SETTLE1_C_HI 29
+#define CBR_RG_RX_HPF_SETTLE1_C_SZ 2
+#define CBR_RG_RX_HPF_SETTLE1_R_MSK 0x00000003
+#define CBR_RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
+#define CBR_RG_RX_HPF_SETTLE1_R_SFT 0
+#define CBR_RG_RX_HPF_SETTLE1_R_HI 1
+#define CBR_RG_RX_HPF_SETTLE1_R_SZ 2
+#define CBR_RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
+#define CBR_RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
+#define CBR_RG_RX_HPF_SETTLE2_C_SFT 2
+#define CBR_RG_RX_HPF_SETTLE2_C_HI 3
+#define CBR_RG_RX_HPF_SETTLE2_C_SZ 2
+#define CBR_RG_RX_HPF_SETTLE2_R_MSK 0x00000030
+#define CBR_RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
+#define CBR_RG_RX_HPF_SETTLE2_R_SFT 4
+#define CBR_RG_RX_HPF_SETTLE2_R_HI 5
+#define CBR_RG_RX_HPF_SETTLE2_R_SZ 2
+#define CBR_RG_RX_HPF_VCMCON2_MSK 0x000000c0
+#define CBR_RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
+#define CBR_RG_RX_HPF_VCMCON2_SFT 6
+#define CBR_RG_RX_HPF_VCMCON2_HI 7
+#define CBR_RG_RX_HPF_VCMCON2_SZ 2
+#define CBR_RG_RX_HPF_VCMCON_MSK 0x00000300
+#define CBR_RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
+#define CBR_RG_RX_HPF_VCMCON_SFT 8
+#define CBR_RG_RX_HPF_VCMCON_HI 9
+#define CBR_RG_RX_HPF_VCMCON_SZ 2
+#define CBR_RG_RX_OUTVCM_MSK 0x00000c00
+#define CBR_RG_RX_OUTVCM_I_MSK 0xfffff3ff
+#define CBR_RG_RX_OUTVCM_SFT 10
+#define CBR_RG_RX_OUTVCM_HI 11
+#define CBR_RG_RX_OUTVCM_SZ 2
+#define CBR_RG_RX_TZI_MSK 0x00003000
+#define CBR_RG_RX_TZI_I_MSK 0xffffcfff
+#define CBR_RG_RX_TZI_SFT 12
+#define CBR_RG_RX_TZI_HI 13
+#define CBR_RG_RX_TZI_SZ 2
+#define CBR_RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
+#define CBR_RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
+#define CBR_RG_RX_TZ_OUT_TRISTATE_SFT 14
+#define CBR_RG_RX_TZ_OUT_TRISTATE_HI 14
+#define CBR_RG_RX_TZ_OUT_TRISTATE_SZ 1
+#define CBR_RG_RX_TZ_VCM_MSK 0x00018000
+#define CBR_RG_RX_TZ_VCM_I_MSK 0xfffe7fff
+#define CBR_RG_RX_TZ_VCM_SFT 15
+#define CBR_RG_RX_TZ_VCM_HI 16
+#define CBR_RG_RX_TZ_VCM_SZ 2
+#define CBR_RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
+#define CBR_RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
+#define CBR_RG_EN_RX_RSSI_TESTNODE_SFT 17
+#define CBR_RG_EN_RX_RSSI_TESTNODE_HI 19
+#define CBR_RG_EN_RX_RSSI_TESTNODE_SZ 3
+#define CBR_RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
+#define CBR_RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
+#define CBR_RG_RX_ADCRSSI_CLKSEL_SFT 20
+#define CBR_RG_RX_ADCRSSI_CLKSEL_HI 20
+#define CBR_RG_RX_ADCRSSI_CLKSEL_SZ 1
+#define CBR_RG_RX_ADCRSSI_VCM_MSK 0x00600000
+#define CBR_RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
+#define CBR_RG_RX_ADCRSSI_VCM_SFT 21
+#define CBR_RG_RX_ADCRSSI_VCM_HI 22
+#define CBR_RG_RX_ADCRSSI_VCM_SZ 2
+#define CBR_RG_RX_REC_LPFCORNER_MSK 0x01800000
+#define CBR_RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
+#define CBR_RG_RX_REC_LPFCORNER_SFT 23
+#define CBR_RG_RX_REC_LPFCORNER_HI 24
+#define CBR_RG_RX_REC_LPFCORNER_SZ 2
+#define CBR_RG_RSSI_CLOCK_GATING_MSK 0x02000000
+#define CBR_RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
+#define CBR_RG_RSSI_CLOCK_GATING_SFT 25
+#define CBR_RG_RSSI_CLOCK_GATING_HI 25
+#define CBR_RG_RSSI_CLOCK_GATING_SZ 1
+#define CBR_RG_TXPGA_CAPSW_MSK 0x00000003
+#define CBR_RG_TXPGA_CAPSW_I_MSK 0xfffffffc
+#define CBR_RG_TXPGA_CAPSW_SFT 0
+#define CBR_RG_TXPGA_CAPSW_HI 1
+#define CBR_RG_TXPGA_CAPSW_SZ 2
+#define CBR_RG_TXPGA_MAIN_MSK 0x000000fc
+#define CBR_RG_TXPGA_MAIN_I_MSK 0xffffff03
+#define CBR_RG_TXPGA_MAIN_SFT 2
+#define CBR_RG_TXPGA_MAIN_HI 7
+#define CBR_RG_TXPGA_MAIN_SZ 6
+#define CBR_RG_TXPGA_STEER_MSK 0x00003f00
+#define CBR_RG_TXPGA_STEER_I_MSK 0xffffc0ff
+#define CBR_RG_TXPGA_STEER_SFT 8
+#define CBR_RG_TXPGA_STEER_HI 13
+#define CBR_RG_TXPGA_STEER_SZ 6
+#define CBR_RG_TXMOD_GMCELL_MSK 0x0000c000
+#define CBR_RG_TXMOD_GMCELL_I_MSK 0xffff3fff
+#define CBR_RG_TXMOD_GMCELL_SFT 14
+#define CBR_RG_TXMOD_GMCELL_HI 15
+#define CBR_RG_TXMOD_GMCELL_SZ 2
+#define CBR_RG_TXLPF_GMCELL_MSK 0x00030000
+#define CBR_RG_TXLPF_GMCELL_I_MSK 0xfffcffff
+#define CBR_RG_TXLPF_GMCELL_SFT 16
+#define CBR_RG_TXLPF_GMCELL_HI 17
+#define CBR_RG_TXLPF_GMCELL_SZ 2
+#define CBR_RG_PACELL_EN_MSK 0x001c0000
+#define CBR_RG_PACELL_EN_I_MSK 0xffe3ffff
+#define CBR_RG_PACELL_EN_SFT 18
+#define CBR_RG_PACELL_EN_HI 20
+#define CBR_RG_PACELL_EN_SZ 3
+#define CBR_RG_PABIAS_CTRL_MSK 0x01e00000
+#define CBR_RG_PABIAS_CTRL_I_MSK 0xfe1fffff
+#define CBR_RG_PABIAS_CTRL_SFT 21
+#define CBR_RG_PABIAS_CTRL_HI 24
+#define CBR_RG_PABIAS_CTRL_SZ 4
+#define CBR_RG_PABIAS_AB_MSK 0x02000000
+#define CBR_RG_PABIAS_AB_I_MSK 0xfdffffff
+#define CBR_RG_PABIAS_AB_SFT 25
+#define CBR_RG_PABIAS_AB_HI 25
+#define CBR_RG_PABIAS_AB_SZ 1
+#define CBR_RG_TX_DIV_VSET_MSK 0x0c000000
+#define CBR_RG_TX_DIV_VSET_I_MSK 0xf3ffffff
+#define CBR_RG_TX_DIV_VSET_SFT 26
+#define CBR_RG_TX_DIV_VSET_HI 27
+#define CBR_RG_TX_DIV_VSET_SZ 2
+#define CBR_RG_TX_LOBUF_VSET_MSK 0x30000000
+#define CBR_RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
+#define CBR_RG_TX_LOBUF_VSET_SFT 28
+#define CBR_RG_TX_LOBUF_VSET_HI 29
+#define CBR_RG_TX_LOBUF_VSET_SZ 2
+#define CBR_RG_RX_SQDC_MSK 0x00000007
+#define CBR_RG_RX_SQDC_I_MSK 0xfffffff8
+#define CBR_RG_RX_SQDC_SFT 0
+#define CBR_RG_RX_SQDC_HI 2
+#define CBR_RG_RX_SQDC_SZ 3
+#define CBR_RG_RX_DIV2_CORE_MSK 0x00000018
+#define CBR_RG_RX_DIV2_CORE_I_MSK 0xffffffe7
+#define CBR_RG_RX_DIV2_CORE_SFT 3
+#define CBR_RG_RX_DIV2_CORE_HI 4
+#define CBR_RG_RX_DIV2_CORE_SZ 2
+#define CBR_RG_RX_LOBUF_MSK 0x00000060
+#define CBR_RG_RX_LOBUF_I_MSK 0xffffff9f
+#define CBR_RG_RX_LOBUF_SFT 5
+#define CBR_RG_RX_LOBUF_HI 6
+#define CBR_RG_RX_LOBUF_SZ 2
+#define CBR_RG_TX_DPDGM_BIAS_MSK 0x00000780
+#define CBR_RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
+#define CBR_RG_TX_DPDGM_BIAS_SFT 7
+#define CBR_RG_TX_DPDGM_BIAS_HI 10
+#define CBR_RG_TX_DPDGM_BIAS_SZ 4
+#define CBR_RG_TX_DPD_DIV_MSK 0x00007800
+#define CBR_RG_TX_DPD_DIV_I_MSK 0xffff87ff
+#define CBR_RG_TX_DPD_DIV_SFT 11
+#define CBR_RG_TX_DPD_DIV_HI 14
+#define CBR_RG_TX_DPD_DIV_SZ 4
+#define CBR_RG_TX_TSSI_BIAS_MSK 0x00038000
+#define CBR_RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
+#define CBR_RG_TX_TSSI_BIAS_SFT 15
+#define CBR_RG_TX_TSSI_BIAS_HI 17
+#define CBR_RG_TX_TSSI_BIAS_SZ 3
+#define CBR_RG_TX_TSSI_DIV_MSK 0x001c0000
+#define CBR_RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
+#define CBR_RG_TX_TSSI_DIV_SFT 18
+#define CBR_RG_TX_TSSI_DIV_HI 20
+#define CBR_RG_TX_TSSI_DIV_SZ 3
+#define CBR_RG_TX_TSSI_TESTMODE_MSK 0x00200000
+#define CBR_RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
+#define CBR_RG_TX_TSSI_TESTMODE_SFT 21
+#define CBR_RG_TX_TSSI_TESTMODE_HI 21
+#define CBR_RG_TX_TSSI_TESTMODE_SZ 1
+#define CBR_RG_TX_TSSI_TEST_MSK 0x00c00000
+#define CBR_RG_TX_TSSI_TEST_I_MSK 0xff3fffff
+#define CBR_RG_TX_TSSI_TEST_SFT 22
+#define CBR_RG_TX_TSSI_TEST_HI 23
+#define CBR_RG_TX_TSSI_TEST_SZ 2
+#define CBR_RG_RX_HG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_HG_LNA_GC_SFT 0
+#define CBR_RG_RX_HG_LNA_GC_HI 1
+#define CBR_RG_RX_HG_LNA_GC_SZ 2
+#define CBR_RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_HG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_HG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_HG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_HG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_HG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_HG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_HG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_HG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_HG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_HG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_HG_TZ_GC_SFT 14
+#define CBR_RG_RX_HG_TZ_GC_HI 15
+#define CBR_RG_RX_HG_TZ_GC_SZ 2
+#define CBR_RG_RX_HG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_HG_TZ_CAP_SFT 16
+#define CBR_RG_RX_HG_TZ_CAP_HI 18
+#define CBR_RG_RX_HG_TZ_CAP_SZ 3
+#define CBR_RG_RX_MG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_MG_LNA_GC_SFT 0
+#define CBR_RG_RX_MG_LNA_GC_HI 1
+#define CBR_RG_RX_MG_LNA_GC_SZ 2
+#define CBR_RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_MG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_MG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_MG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_MG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_MG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_MG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_MG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_MG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_MG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_MG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_MG_TZ_GC_SFT 14
+#define CBR_RG_RX_MG_TZ_GC_HI 15
+#define CBR_RG_RX_MG_TZ_GC_SZ 2
+#define CBR_RG_RX_MG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_MG_TZ_CAP_SFT 16
+#define CBR_RG_RX_MG_TZ_CAP_HI 18
+#define CBR_RG_RX_MG_TZ_CAP_SZ 3
+#define CBR_RG_RX_LG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_LG_LNA_GC_SFT 0
+#define CBR_RG_RX_LG_LNA_GC_HI 1
+#define CBR_RG_RX_LG_LNA_GC_SZ 2
+#define CBR_RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_LG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_LG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_LG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_LG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_LG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_LG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_LG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_LG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_LG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_LG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_LG_TZ_GC_SFT 14
+#define CBR_RG_RX_LG_TZ_GC_HI 15
+#define CBR_RG_RX_LG_TZ_GC_SZ 2
+#define CBR_RG_RX_LG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_LG_TZ_CAP_SFT 16
+#define CBR_RG_RX_LG_TZ_CAP_HI 18
+#define CBR_RG_RX_LG_TZ_CAP_SZ 3
+#define CBR_RG_RX_ULG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_ULG_LNA_GC_SFT 0
+#define CBR_RG_RX_ULG_LNA_GC_HI 1
+#define CBR_RG_RX_ULG_LNA_GC_SZ 2
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_ULG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_ULG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_ULG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_ULG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_ULG_TZ_GC_SFT 14
+#define CBR_RG_RX_ULG_TZ_GC_HI 15
+#define CBR_RG_RX_ULG_TZ_GC_SZ 2
+#define CBR_RG_RX_ULG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_ULG_TZ_CAP_SFT 16
+#define CBR_RG_RX_ULG_TZ_CAP_HI 18
+#define CBR_RG_RX_ULG_TZ_CAP_SZ 3
+#define CBR_RG_HPF1_FAST_SET_X_MSK 0x00000001
+#define CBR_RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
+#define CBR_RG_HPF1_FAST_SET_X_SFT 0
+#define CBR_RG_HPF1_FAST_SET_X_HI 0
+#define CBR_RG_HPF1_FAST_SET_X_SZ 1
+#define CBR_RG_HPF1_FAST_SET_Y_MSK 0x00000002
+#define CBR_RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
+#define CBR_RG_HPF1_FAST_SET_Y_SFT 1
+#define CBR_RG_HPF1_FAST_SET_Y_HI 1
+#define CBR_RG_HPF1_FAST_SET_Y_SZ 1
+#define CBR_RG_HPF1_FAST_SET_Z_MSK 0x00000004
+#define CBR_RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
+#define CBR_RG_HPF1_FAST_SET_Z_SFT 2
+#define CBR_RG_HPF1_FAST_SET_Z_HI 2
+#define CBR_RG_HPF1_FAST_SET_Z_SZ 1
+#define CBR_RG_HPF_T1A_MSK 0x00000018
+#define CBR_RG_HPF_T1A_I_MSK 0xffffffe7
+#define CBR_RG_HPF_T1A_SFT 3
+#define CBR_RG_HPF_T1A_HI 4
+#define CBR_RG_HPF_T1A_SZ 2
+#define CBR_RG_HPF_T1B_MSK 0x00000060
+#define CBR_RG_HPF_T1B_I_MSK 0xffffff9f
+#define CBR_RG_HPF_T1B_SFT 5
+#define CBR_RG_HPF_T1B_HI 6
+#define CBR_RG_HPF_T1B_SZ 2
+#define CBR_RG_HPF_T1C_MSK 0x00000180
+#define CBR_RG_HPF_T1C_I_MSK 0xfffffe7f
+#define CBR_RG_HPF_T1C_SFT 7
+#define CBR_RG_HPF_T1C_HI 8
+#define CBR_RG_HPF_T1C_SZ 2
+#define CBR_RG_RX_LNA_TRI_SEL_MSK 0x00000600
+#define CBR_RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
+#define CBR_RG_RX_LNA_TRI_SEL_SFT 9
+#define CBR_RG_RX_LNA_TRI_SEL_HI 10
+#define CBR_RG_RX_LNA_TRI_SEL_SZ 2
+#define CBR_RG_RX_LNA_SETTLE_MSK 0x00001800
+#define CBR_RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
+#define CBR_RG_RX_LNA_SETTLE_SFT 11
+#define CBR_RG_RX_LNA_SETTLE_HI 12
+#define CBR_RG_RX_LNA_SETTLE_SZ 2
+#define CBR_RG_ADC_CLKSEL_MSK 0x00000001
+#define CBR_RG_ADC_CLKSEL_I_MSK 0xfffffffe
+#define CBR_RG_ADC_CLKSEL_SFT 0
+#define CBR_RG_ADC_CLKSEL_HI 0
+#define CBR_RG_ADC_CLKSEL_SZ 1
+#define CBR_RG_ADC_DIBIAS_MSK 0x00000006
+#define CBR_RG_ADC_DIBIAS_I_MSK 0xfffffff9
+#define CBR_RG_ADC_DIBIAS_SFT 1
+#define CBR_RG_ADC_DIBIAS_HI 2
+#define CBR_RG_ADC_DIBIAS_SZ 2
+#define CBR_RG_ADC_DIVR_MSK 0x00000008
+#define CBR_RG_ADC_DIVR_I_MSK 0xfffffff7
+#define CBR_RG_ADC_DIVR_SFT 3
+#define CBR_RG_ADC_DIVR_HI 3
+#define CBR_RG_ADC_DIVR_SZ 1
+#define CBR_RG_ADC_DVCMI_MSK 0x00000030
+#define CBR_RG_ADC_DVCMI_I_MSK 0xffffffcf
+#define CBR_RG_ADC_DVCMI_SFT 4
+#define CBR_RG_ADC_DVCMI_HI 5
+#define CBR_RG_ADC_DVCMI_SZ 2
+#define CBR_RG_ADC_SAMSEL_MSK 0x000003c0
+#define CBR_RG_ADC_SAMSEL_I_MSK 0xfffffc3f
+#define CBR_RG_ADC_SAMSEL_SFT 6
+#define CBR_RG_ADC_SAMSEL_HI 9
+#define CBR_RG_ADC_SAMSEL_SZ 4
+#define CBR_RG_ADC_STNBY_MSK 0x00000400
+#define CBR_RG_ADC_STNBY_I_MSK 0xfffffbff
+#define CBR_RG_ADC_STNBY_SFT 10
+#define CBR_RG_ADC_STNBY_HI 10
+#define CBR_RG_ADC_STNBY_SZ 1
+#define CBR_RG_ADC_TESTMODE_MSK 0x00000800
+#define CBR_RG_ADC_TESTMODE_I_MSK 0xfffff7ff
+#define CBR_RG_ADC_TESTMODE_SFT 11
+#define CBR_RG_ADC_TESTMODE_HI 11
+#define CBR_RG_ADC_TESTMODE_SZ 1
+#define CBR_RG_ADC_TSEL_MSK 0x0000f000
+#define CBR_RG_ADC_TSEL_I_MSK 0xffff0fff
+#define CBR_RG_ADC_TSEL_SFT 12
+#define CBR_RG_ADC_TSEL_HI 15
+#define CBR_RG_ADC_TSEL_SZ 4
+#define CBR_RG_ADC_VRSEL_MSK 0x00030000
+#define CBR_RG_ADC_VRSEL_I_MSK 0xfffcffff
+#define CBR_RG_ADC_VRSEL_SFT 16
+#define CBR_RG_ADC_VRSEL_HI 17
+#define CBR_RG_ADC_VRSEL_SZ 2
+#define CBR_RG_DICMP_MSK 0x000c0000
+#define CBR_RG_DICMP_I_MSK 0xfff3ffff
+#define CBR_RG_DICMP_SFT 18
+#define CBR_RG_DICMP_HI 19
+#define CBR_RG_DICMP_SZ 2
+#define CBR_RG_DIOP_MSK 0x00300000
+#define CBR_RG_DIOP_I_MSK 0xffcfffff
+#define CBR_RG_DIOP_SFT 20
+#define CBR_RG_DIOP_HI 21
+#define CBR_RG_DIOP_SZ 2
+#define CBR_RG_DACI1ST_MSK 0x00000003
+#define CBR_RG_DACI1ST_I_MSK 0xfffffffc
+#define CBR_RG_DACI1ST_SFT 0
+#define CBR_RG_DACI1ST_HI 1
+#define CBR_RG_DACI1ST_SZ 2
+#define CBR_RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
+#define CBR_RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
+#define CBR_RG_TX_DACLPF_ICOURSE_SFT 2
+#define CBR_RG_TX_DACLPF_ICOURSE_HI 3
+#define CBR_RG_TX_DACLPF_ICOURSE_SZ 2
+#define CBR_RG_TX_DACLPF_IFINE_MSK 0x00000030
+#define CBR_RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define CBR_RG_TX_DACLPF_IFINE_SFT 4
+#define CBR_RG_TX_DACLPF_IFINE_HI 5
+#define CBR_RG_TX_DACLPF_IFINE_SZ 2
+#define CBR_RG_TX_DACLPF_VCM_MSK 0x000000c0
+#define CBR_RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define CBR_RG_TX_DACLPF_VCM_SFT 6
+#define CBR_RG_TX_DACLPF_VCM_HI 7
+#define CBR_RG_TX_DACLPF_VCM_SZ 2
+#define CBR_RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
+#define CBR_RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
+#define CBR_RG_TX_DAC_CKEDGE_SEL_SFT 8
+#define CBR_RG_TX_DAC_CKEDGE_SEL_HI 8
+#define CBR_RG_TX_DAC_CKEDGE_SEL_SZ 1
+#define CBR_RG_TX_DAC_IBIAS_MSK 0x00000600
+#define CBR_RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
+#define CBR_RG_TX_DAC_IBIAS_SFT 9
+#define CBR_RG_TX_DAC_IBIAS_HI 10
+#define CBR_RG_TX_DAC_IBIAS_SZ 2
+#define CBR_RG_TX_DAC_OS_MSK 0x00003800
+#define CBR_RG_TX_DAC_OS_I_MSK 0xffffc7ff
+#define CBR_RG_TX_DAC_OS_SFT 11
+#define CBR_RG_TX_DAC_OS_HI 13
+#define CBR_RG_TX_DAC_OS_SZ 3
+#define CBR_RG_TX_DAC_RCAL_MSK 0x0000c000
+#define CBR_RG_TX_DAC_RCAL_I_MSK 0xffff3fff
+#define CBR_RG_TX_DAC_RCAL_SFT 14
+#define CBR_RG_TX_DAC_RCAL_HI 15
+#define CBR_RG_TX_DAC_RCAL_SZ 2
+#define CBR_RG_TX_DAC_TSEL_MSK 0x000f0000
+#define CBR_RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
+#define CBR_RG_TX_DAC_TSEL_SFT 16
+#define CBR_RG_TX_DAC_TSEL_HI 19
+#define CBR_RG_TX_DAC_TSEL_SZ 4
+#define CBR_RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
+#define CBR_RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
+#define CBR_RG_TX_EN_VOLTAGE_IN_SFT 20
+#define CBR_RG_TX_EN_VOLTAGE_IN_HI 20
+#define CBR_RG_TX_EN_VOLTAGE_IN_SZ 1
+#define CBR_RG_TXLPF_BYPASS_MSK 0x00200000
+#define CBR_RG_TXLPF_BYPASS_I_MSK 0xffdfffff
+#define CBR_RG_TXLPF_BYPASS_SFT 21
+#define CBR_RG_TXLPF_BYPASS_HI 21
+#define CBR_RG_TXLPF_BYPASS_SZ 1
+#define CBR_RG_TXLPF_BOOSTI_MSK 0x00400000
+#define CBR_RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
+#define CBR_RG_TXLPF_BOOSTI_SFT 22
+#define CBR_RG_TXLPF_BOOSTI_HI 22
+#define CBR_RG_TXLPF_BOOSTI_SZ 1
+#define CBR_RG_EN_SX_R3_MSK 0x00000001
+#define CBR_RG_EN_SX_R3_I_MSK 0xfffffffe
+#define CBR_RG_EN_SX_R3_SFT 0
+#define CBR_RG_EN_SX_R3_HI 0
+#define CBR_RG_EN_SX_R3_SZ 1
+#define CBR_RG_EN_SX_CH_MSK 0x00000002
+#define CBR_RG_EN_SX_CH_I_MSK 0xfffffffd
+#define CBR_RG_EN_SX_CH_SFT 1
+#define CBR_RG_EN_SX_CH_HI 1
+#define CBR_RG_EN_SX_CH_SZ 1
+#define CBR_RG_EN_SX_CHP_MSK 0x00000004
+#define CBR_RG_EN_SX_CHP_I_MSK 0xfffffffb
+#define CBR_RG_EN_SX_CHP_SFT 2
+#define CBR_RG_EN_SX_CHP_HI 2
+#define CBR_RG_EN_SX_CHP_SZ 1
+#define CBR_RG_EN_SX_DIVCK_MSK 0x00000008
+#define CBR_RG_EN_SX_DIVCK_I_MSK 0xfffffff7
+#define CBR_RG_EN_SX_DIVCK_SFT 3
+#define CBR_RG_EN_SX_DIVCK_HI 3
+#define CBR_RG_EN_SX_DIVCK_SZ 1
+#define CBR_RG_EN_SX_VCOBF_MSK 0x00000010
+#define CBR_RG_EN_SX_VCOBF_I_MSK 0xffffffef
+#define CBR_RG_EN_SX_VCOBF_SFT 4
+#define CBR_RG_EN_SX_VCOBF_HI 4
+#define CBR_RG_EN_SX_VCOBF_SZ 1
+#define CBR_RG_EN_SX_VCO_MSK 0x00000020
+#define CBR_RG_EN_SX_VCO_I_MSK 0xffffffdf
+#define CBR_RG_EN_SX_VCO_SFT 5
+#define CBR_RG_EN_SX_VCO_HI 5
+#define CBR_RG_EN_SX_VCO_SZ 1
+#define CBR_RG_EN_SX_MOD_MSK 0x00000040
+#define CBR_RG_EN_SX_MOD_I_MSK 0xffffffbf
+#define CBR_RG_EN_SX_MOD_SFT 6
+#define CBR_RG_EN_SX_MOD_HI 6
+#define CBR_RG_EN_SX_MOD_SZ 1
+#define CBR_RG_EN_SX_LCK_MSK 0x00000080
+#define CBR_RG_EN_SX_LCK_I_MSK 0xffffff7f
+#define CBR_RG_EN_SX_LCK_SFT 7
+#define CBR_RG_EN_SX_LCK_HI 7
+#define CBR_RG_EN_SX_LCK_SZ 1
+#define CBR_RG_EN_SX_DITHER_MSK 0x00000100
+#define CBR_RG_EN_SX_DITHER_I_MSK 0xfffffeff
+#define CBR_RG_EN_SX_DITHER_SFT 8
+#define CBR_RG_EN_SX_DITHER_HI 8
+#define CBR_RG_EN_SX_DITHER_SZ 1
+#define CBR_RG_EN_SX_DELCAL_MSK 0x00000200
+#define CBR_RG_EN_SX_DELCAL_I_MSK 0xfffffdff
+#define CBR_RG_EN_SX_DELCAL_SFT 9
+#define CBR_RG_EN_SX_DELCAL_HI 9
+#define CBR_RG_EN_SX_DELCAL_SZ 1
+#define CBR_RG_EN_SX_PC_BYPASS_MSK 0x00000400
+#define CBR_RG_EN_SX_PC_BYPASS_I_MSK 0xfffffbff
+#define CBR_RG_EN_SX_PC_BYPASS_SFT 10
+#define CBR_RG_EN_SX_PC_BYPASS_HI 10
+#define CBR_RG_EN_SX_PC_BYPASS_SZ 1
+#define CBR_RG_EN_SX_VT_MON_MSK 0x00000800
+#define CBR_RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
+#define CBR_RG_EN_SX_VT_MON_SFT 11
+#define CBR_RG_EN_SX_VT_MON_HI 11
+#define CBR_RG_EN_SX_VT_MON_SZ 1
+#define CBR_RG_EN_SX_VT_MON_DG_MSK 0x00001000
+#define CBR_RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
+#define CBR_RG_EN_SX_VT_MON_DG_SFT 12
+#define CBR_RG_EN_SX_VT_MON_DG_HI 12
+#define CBR_RG_EN_SX_VT_MON_DG_SZ 1
+#define CBR_RG_EN_SX_DIV_MSK 0x00002000
+#define CBR_RG_EN_SX_DIV_I_MSK 0xffffdfff
+#define CBR_RG_EN_SX_DIV_SFT 13
+#define CBR_RG_EN_SX_DIV_HI 13
+#define CBR_RG_EN_SX_DIV_SZ 1
+#define CBR_RG_EN_SX_LPF_MSK 0x00004000
+#define CBR_RG_EN_SX_LPF_I_MSK 0xffffbfff
+#define CBR_RG_EN_SX_LPF_SFT 14
+#define CBR_RG_EN_SX_LPF_HI 14
+#define CBR_RG_EN_SX_LPF_SZ 1
+#define CBR_RG_SX_RFCTRL_F_MSK 0x00ffffff
+#define CBR_RG_SX_RFCTRL_F_I_MSK 0xff000000
+#define CBR_RG_SX_RFCTRL_F_SFT 0
+#define CBR_RG_SX_RFCTRL_F_HI 23
+#define CBR_RG_SX_RFCTRL_F_SZ 24
+#define CBR_RG_SX_SEL_CP_MSK 0x0f000000
+#define CBR_RG_SX_SEL_CP_I_MSK 0xf0ffffff
+#define CBR_RG_SX_SEL_CP_SFT 24
+#define CBR_RG_SX_SEL_CP_HI 27
+#define CBR_RG_SX_SEL_CP_SZ 4
+#define CBR_RG_SX_SEL_CS_MSK 0xf0000000
+#define CBR_RG_SX_SEL_CS_I_MSK 0x0fffffff
+#define CBR_RG_SX_SEL_CS_SFT 28
+#define CBR_RG_SX_SEL_CS_HI 31
+#define CBR_RG_SX_SEL_CS_SZ 4
+#define CBR_RG_SX_RFCTRL_CH_MSK 0x000007ff
+#define CBR_RG_SX_RFCTRL_CH_I_MSK 0xfffff800
+#define CBR_RG_SX_RFCTRL_CH_SFT 0
+#define CBR_RG_SX_RFCTRL_CH_HI 10
+#define CBR_RG_SX_RFCTRL_CH_SZ 11
+#define CBR_RG_SX_SEL_C3_MSK 0x00007800
+#define CBR_RG_SX_SEL_C3_I_MSK 0xffff87ff
+#define CBR_RG_SX_SEL_C3_SFT 11
+#define CBR_RG_SX_SEL_C3_HI 14
+#define CBR_RG_SX_SEL_C3_SZ 4
+#define CBR_RG_SX_SEL_RS_MSK 0x000f8000
+#define CBR_RG_SX_SEL_RS_I_MSK 0xfff07fff
+#define CBR_RG_SX_SEL_RS_SFT 15
+#define CBR_RG_SX_SEL_RS_HI 19
+#define CBR_RG_SX_SEL_RS_SZ 5
+#define CBR_RG_SX_SEL_R3_MSK 0x01f00000
+#define CBR_RG_SX_SEL_R3_I_MSK 0xfe0fffff
+#define CBR_RG_SX_SEL_R3_SFT 20
+#define CBR_RG_SX_SEL_R3_HI 24
+#define CBR_RG_SX_SEL_R3_SZ 5
+#define CBR_RG_SX_SEL_ICHP_MSK 0x0000001f
+#define CBR_RG_SX_SEL_ICHP_I_MSK 0xffffffe0
+#define CBR_RG_SX_SEL_ICHP_SFT 0
+#define CBR_RG_SX_SEL_ICHP_HI 4
+#define CBR_RG_SX_SEL_ICHP_SZ 5
+#define CBR_RG_SX_SEL_PCHP_MSK 0x000003e0
+#define CBR_RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
+#define CBR_RG_SX_SEL_PCHP_SFT 5
+#define CBR_RG_SX_SEL_PCHP_HI 9
+#define CBR_RG_SX_SEL_PCHP_SZ 5
+#define CBR_RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
+#define CBR_RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
+#define CBR_RG_SX_SEL_CHP_REGOP_SFT 10
+#define CBR_RG_SX_SEL_CHP_REGOP_HI 13
+#define CBR_RG_SX_SEL_CHP_REGOP_SZ 4
+#define CBR_RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
+#define CBR_RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
+#define CBR_RG_SX_SEL_CHP_UNIOP_SFT 14
+#define CBR_RG_SX_SEL_CHP_UNIOP_HI 17
+#define CBR_RG_SX_SEL_CHP_UNIOP_SZ 4
+#define CBR_RG_SX_CHP_IOST_POL_MSK 0x00040000
+#define CBR_RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
+#define CBR_RG_SX_CHP_IOST_POL_SFT 18
+#define CBR_RG_SX_CHP_IOST_POL_HI 18
+#define CBR_RG_SX_CHP_IOST_POL_SZ 1
+#define CBR_RG_SX_CHP_IOST_MSK 0x00380000
+#define CBR_RG_SX_CHP_IOST_I_MSK 0xffc7ffff
+#define CBR_RG_SX_CHP_IOST_SFT 19
+#define CBR_RG_SX_CHP_IOST_HI 21
+#define CBR_RG_SX_CHP_IOST_SZ 3
+#define CBR_RG_SX_PFDSEL_MSK 0x00400000
+#define CBR_RG_SX_PFDSEL_I_MSK 0xffbfffff
+#define CBR_RG_SX_PFDSEL_SFT 22
+#define CBR_RG_SX_PFDSEL_HI 22
+#define CBR_RG_SX_PFDSEL_SZ 1
+#define CBR_RG_SX_PFD_SET_MSK 0x00800000
+#define CBR_RG_SX_PFD_SET_I_MSK 0xff7fffff
+#define CBR_RG_SX_PFD_SET_SFT 23
+#define CBR_RG_SX_PFD_SET_HI 23
+#define CBR_RG_SX_PFD_SET_SZ 1
+#define CBR_RG_SX_PFD_SET1_MSK 0x01000000
+#define CBR_RG_SX_PFD_SET1_I_MSK 0xfeffffff
+#define CBR_RG_SX_PFD_SET1_SFT 24
+#define CBR_RG_SX_PFD_SET1_HI 24
+#define CBR_RG_SX_PFD_SET1_SZ 1
+#define CBR_RG_SX_PFD_SET2_MSK 0x02000000
+#define CBR_RG_SX_PFD_SET2_I_MSK 0xfdffffff
+#define CBR_RG_SX_PFD_SET2_SFT 25
+#define CBR_RG_SX_PFD_SET2_HI 25
+#define CBR_RG_SX_PFD_SET2_SZ 1
+#define CBR_RG_SX_VBNCAS_SEL_MSK 0x04000000
+#define CBR_RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
+#define CBR_RG_SX_VBNCAS_SEL_SFT 26
+#define CBR_RG_SX_VBNCAS_SEL_HI 26
+#define CBR_RG_SX_VBNCAS_SEL_SZ 1
+#define CBR_RG_SX_PFD_RST_H_MSK 0x08000000
+#define CBR_RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
+#define CBR_RG_SX_PFD_RST_H_SFT 27
+#define CBR_RG_SX_PFD_RST_H_HI 27
+#define CBR_RG_SX_PFD_RST_H_SZ 1
+#define CBR_RG_SX_PFD_TRUP_MSK 0x10000000
+#define CBR_RG_SX_PFD_TRUP_I_MSK 0xefffffff
+#define CBR_RG_SX_PFD_TRUP_SFT 28
+#define CBR_RG_SX_PFD_TRUP_HI 28
+#define CBR_RG_SX_PFD_TRUP_SZ 1
+#define CBR_RG_SX_PFD_TRDN_MSK 0x20000000
+#define CBR_RG_SX_PFD_TRDN_I_MSK 0xdfffffff
+#define CBR_RG_SX_PFD_TRDN_SFT 29
+#define CBR_RG_SX_PFD_TRDN_HI 29
+#define CBR_RG_SX_PFD_TRDN_SZ 1
+#define CBR_RG_SX_PFD_TRSEL_MSK 0x40000000
+#define CBR_RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
+#define CBR_RG_SX_PFD_TRSEL_SFT 30
+#define CBR_RG_SX_PFD_TRSEL_HI 30
+#define CBR_RG_SX_PFD_TRSEL_SZ 1
+#define CBR_RG_SX_VCOBA_R_MSK 0x00000007
+#define CBR_RG_SX_VCOBA_R_I_MSK 0xfffffff8
+#define CBR_RG_SX_VCOBA_R_SFT 0
+#define CBR_RG_SX_VCOBA_R_HI 2
+#define CBR_RG_SX_VCOBA_R_SZ 3
+#define CBR_RG_SX_VCORSEL_MSK 0x000000f8
+#define CBR_RG_SX_VCORSEL_I_MSK 0xffffff07
+#define CBR_RG_SX_VCORSEL_SFT 3
+#define CBR_RG_SX_VCORSEL_HI 7
+#define CBR_RG_SX_VCORSEL_SZ 5
+#define CBR_RG_SX_VCOCUSEL_MSK 0x00000f00
+#define CBR_RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
+#define CBR_RG_SX_VCOCUSEL_SFT 8
+#define CBR_RG_SX_VCOCUSEL_HI 11
+#define CBR_RG_SX_VCOCUSEL_SZ 4
+#define CBR_RG_SX_RXBFSEL_MSK 0x0000f000
+#define CBR_RG_SX_RXBFSEL_I_MSK 0xffff0fff
+#define CBR_RG_SX_RXBFSEL_SFT 12
+#define CBR_RG_SX_RXBFSEL_HI 15
+#define CBR_RG_SX_RXBFSEL_SZ 4
+#define CBR_RG_SX_TXBFSEL_MSK 0x000f0000
+#define CBR_RG_SX_TXBFSEL_I_MSK 0xfff0ffff
+#define CBR_RG_SX_TXBFSEL_SFT 16
+#define CBR_RG_SX_TXBFSEL_HI 19
+#define CBR_RG_SX_TXBFSEL_SZ 4
+#define CBR_RG_SX_VCOBFSEL_MSK 0x00f00000
+#define CBR_RG_SX_VCOBFSEL_I_MSK 0xff0fffff
+#define CBR_RG_SX_VCOBFSEL_SFT 20
+#define CBR_RG_SX_VCOBFSEL_HI 23
+#define CBR_RG_SX_VCOBFSEL_SZ 4
+#define CBR_RG_SX_DIVBFSEL_MSK 0x0f000000
+#define CBR_RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
+#define CBR_RG_SX_DIVBFSEL_SFT 24
+#define CBR_RG_SX_DIVBFSEL_HI 27
+#define CBR_RG_SX_DIVBFSEL_SZ 4
+#define CBR_RG_SX_GNDR_SEL_MSK 0xf0000000
+#define CBR_RG_SX_GNDR_SEL_I_MSK 0x0fffffff
+#define CBR_RG_SX_GNDR_SEL_SFT 28
+#define CBR_RG_SX_GNDR_SEL_HI 31
+#define CBR_RG_SX_GNDR_SEL_SZ 4
+#define CBR_RG_SX_DITHER_WEIGHT_MSK 0x00000003
+#define CBR_RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
+#define CBR_RG_SX_DITHER_WEIGHT_SFT 0
+#define CBR_RG_SX_DITHER_WEIGHT_HI 1
+#define CBR_RG_SX_DITHER_WEIGHT_SZ 2
+#define CBR_RG_SX_MOD_ERRCMP_MSK 0x0000000c
+#define CBR_RG_SX_MOD_ERRCMP_I_MSK 0xfffffff3
+#define CBR_RG_SX_MOD_ERRCMP_SFT 2
+#define CBR_RG_SX_MOD_ERRCMP_HI 3
+#define CBR_RG_SX_MOD_ERRCMP_SZ 2
+#define CBR_RG_SX_MOD_ORDER_MSK 0x00000030
+#define CBR_RG_SX_MOD_ORDER_I_MSK 0xffffffcf
+#define CBR_RG_SX_MOD_ORDER_SFT 4
+#define CBR_RG_SX_MOD_ORDER_HI 5
+#define CBR_RG_SX_MOD_ORDER_SZ 2
+#define CBR_RG_SX_SDM_D1_MSK 0x00000040
+#define CBR_RG_SX_SDM_D1_I_MSK 0xffffffbf
+#define CBR_RG_SX_SDM_D1_SFT 6
+#define CBR_RG_SX_SDM_D1_HI 6
+#define CBR_RG_SX_SDM_D1_SZ 1
+#define CBR_RG_SX_SDM_D2_MSK 0x00000080
+#define CBR_RG_SX_SDM_D2_I_MSK 0xffffff7f
+#define CBR_RG_SX_SDM_D2_SFT 7
+#define CBR_RG_SX_SDM_D2_HI 7
+#define CBR_RG_SX_SDM_D2_SZ 1
+#define CBR_RG_SDM_PASS_MSK 0x00000100
+#define CBR_RG_SDM_PASS_I_MSK 0xfffffeff
+#define CBR_RG_SDM_PASS_SFT 8
+#define CBR_RG_SDM_PASS_HI 8
+#define CBR_RG_SDM_PASS_SZ 1
+#define CBR_RG_SX_RST_H_DIV_MSK 0x00000200
+#define CBR_RG_SX_RST_H_DIV_I_MSK 0xfffffdff
+#define CBR_RG_SX_RST_H_DIV_SFT 9
+#define CBR_RG_SX_RST_H_DIV_HI 9
+#define CBR_RG_SX_RST_H_DIV_SZ 1
+#define CBR_RG_SX_SDM_EDGE_MSK 0x00000400
+#define CBR_RG_SX_SDM_EDGE_I_MSK 0xfffffbff
+#define CBR_RG_SX_SDM_EDGE_SFT 10
+#define CBR_RG_SX_SDM_EDGE_HI 10
+#define CBR_RG_SX_SDM_EDGE_SZ 1
+#define CBR_RG_SX_XO_GM_MSK 0x00001800
+#define CBR_RG_SX_XO_GM_I_MSK 0xffffe7ff
+#define CBR_RG_SX_XO_GM_SFT 11
+#define CBR_RG_SX_XO_GM_HI 12
+#define CBR_RG_SX_XO_GM_SZ 2
+#define CBR_RG_SX_REFBYTWO_MSK 0x00002000
+#define CBR_RG_SX_REFBYTWO_I_MSK 0xffffdfff
+#define CBR_RG_SX_REFBYTWO_SFT 13
+#define CBR_RG_SX_REFBYTWO_HI 13
+#define CBR_RG_SX_REFBYTWO_SZ 1
+#define CBR_RG_SX_XO_SWCAP_MSK 0x0003c000
+#define CBR_RG_SX_XO_SWCAP_I_MSK 0xfffc3fff
+#define CBR_RG_SX_XO_SWCAP_SFT 14
+#define CBR_RG_SX_XO_SWCAP_HI 17
+#define CBR_RG_SX_XO_SWCAP_SZ 4
+#define CBR_RG_SX_SDMLUT_INV_MSK 0x00040000
+#define CBR_RG_SX_SDMLUT_INV_I_MSK 0xfffbffff
+#define CBR_RG_SX_SDMLUT_INV_SFT 18
+#define CBR_RG_SX_SDMLUT_INV_HI 18
+#define CBR_RG_SX_SDMLUT_INV_SZ 1
+#define CBR_RG_SX_LCKEN_MSK 0x00080000
+#define CBR_RG_SX_LCKEN_I_MSK 0xfff7ffff
+#define CBR_RG_SX_LCKEN_SFT 19
+#define CBR_RG_SX_LCKEN_HI 19
+#define CBR_RG_SX_LCKEN_SZ 1
+#define CBR_RG_SX_PREVDD_MSK 0x00f00000
+#define CBR_RG_SX_PREVDD_I_MSK 0xff0fffff
+#define CBR_RG_SX_PREVDD_SFT 20
+#define CBR_RG_SX_PREVDD_HI 23
+#define CBR_RG_SX_PREVDD_SZ 4
+#define CBR_RG_SX_PSCONTERVDD_MSK 0x0f000000
+#define CBR_RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
+#define CBR_RG_SX_PSCONTERVDD_SFT 24
+#define CBR_RG_SX_PSCONTERVDD_HI 27
+#define CBR_RG_SX_PSCONTERVDD_SZ 4
+#define CBR_RG_SX_MOD_ERR_DELAY_MSK 0x30000000
+#define CBR_RG_SX_MOD_ERR_DELAY_I_MSK 0xcfffffff
+#define CBR_RG_SX_MOD_ERR_DELAY_SFT 28
+#define CBR_RG_SX_MOD_ERR_DELAY_HI 29
+#define CBR_RG_SX_MOD_ERR_DELAY_SZ 2
+#define CBR_RG_SX_MODDB_MSK 0x40000000
+#define CBR_RG_SX_MODDB_I_MSK 0xbfffffff
+#define CBR_RG_SX_MODDB_SFT 30
+#define CBR_RG_SX_MODDB_HI 30
+#define CBR_RG_SX_MODDB_SZ 1
+#define CBR_RG_SX_CV_CURVE_SEL_MSK 0x00000003
+#define CBR_RG_SX_CV_CURVE_SEL_I_MSK 0xfffffffc
+#define CBR_RG_SX_CV_CURVE_SEL_SFT 0
+#define CBR_RG_SX_CV_CURVE_SEL_HI 1
+#define CBR_RG_SX_CV_CURVE_SEL_SZ 2
+#define CBR_RG_SX_SEL_DELAY_MSK 0x0000007c
+#define CBR_RG_SX_SEL_DELAY_I_MSK 0xffffff83
+#define CBR_RG_SX_SEL_DELAY_SFT 2
+#define CBR_RG_SX_SEL_DELAY_HI 6
+#define CBR_RG_SX_SEL_DELAY_SZ 5
+#define CBR_RG_SX_REF_CYCLE_MSK 0x00000780
+#define CBR_RG_SX_REF_CYCLE_I_MSK 0xfffff87f
+#define CBR_RG_SX_REF_CYCLE_SFT 7
+#define CBR_RG_SX_REF_CYCLE_HI 10
+#define CBR_RG_SX_REF_CYCLE_SZ 4
+#define CBR_RG_SX_VCOBY16_MSK 0x00000800
+#define CBR_RG_SX_VCOBY16_I_MSK 0xfffff7ff
+#define CBR_RG_SX_VCOBY16_SFT 11
+#define CBR_RG_SX_VCOBY16_HI 11
+#define CBR_RG_SX_VCOBY16_SZ 1
+#define CBR_RG_SX_VCOBY32_MSK 0x00001000
+#define CBR_RG_SX_VCOBY32_I_MSK 0xffffefff
+#define CBR_RG_SX_VCOBY32_SFT 12
+#define CBR_RG_SX_VCOBY32_HI 12
+#define CBR_RG_SX_VCOBY32_SZ 1
+#define CBR_RG_SX_PH_MSK 0x00002000
+#define CBR_RG_SX_PH_I_MSK 0xffffdfff
+#define CBR_RG_SX_PH_SFT 13
+#define CBR_RG_SX_PH_HI 13
+#define CBR_RG_SX_PH_SZ 1
+#define CBR_RG_SX_PL_MSK 0x00004000
+#define CBR_RG_SX_PL_I_MSK 0xffffbfff
+#define CBR_RG_SX_PL_SFT 14
+#define CBR_RG_SX_PL_HI 14
+#define CBR_RG_SX_PL_SZ 1
+#define CBR_RG_SX_VT_MON_MODE_MSK 0x00000001
+#define CBR_RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
+#define CBR_RG_SX_VT_MON_MODE_SFT 0
+#define CBR_RG_SX_VT_MON_MODE_HI 0
+#define CBR_RG_SX_VT_MON_MODE_SZ 1
+#define CBR_RG_SX_VT_TH_HI_MSK 0x00000006
+#define CBR_RG_SX_VT_TH_HI_I_MSK 0xfffffff9
+#define CBR_RG_SX_VT_TH_HI_SFT 1
+#define CBR_RG_SX_VT_TH_HI_HI 2
+#define CBR_RG_SX_VT_TH_HI_SZ 2
+#define CBR_RG_SX_VT_TH_LO_MSK 0x00000018
+#define CBR_RG_SX_VT_TH_LO_I_MSK 0xffffffe7
+#define CBR_RG_SX_VT_TH_LO_SFT 3
+#define CBR_RG_SX_VT_TH_LO_HI 4
+#define CBR_RG_SX_VT_TH_LO_SZ 2
+#define CBR_RG_SX_VT_SET_MSK 0x00000020
+#define CBR_RG_SX_VT_SET_I_MSK 0xffffffdf
+#define CBR_RG_SX_VT_SET_SFT 5
+#define CBR_RG_SX_VT_SET_HI 5
+#define CBR_RG_SX_VT_SET_SZ 1
+#define CBR_RG_SX_VT_MON_TMR_MSK 0x00007fc0
+#define CBR_RG_SX_VT_MON_TMR_I_MSK 0xffff803f
+#define CBR_RG_SX_VT_MON_TMR_SFT 6
+#define CBR_RG_SX_VT_MON_TMR_HI 14
+#define CBR_RG_SX_VT_MON_TMR_SZ 9
+#define CBR_RG_IDEAL_CYCLE_MSK 0x0fff8000
+#define CBR_RG_IDEAL_CYCLE_I_MSK 0xf0007fff
+#define CBR_RG_IDEAL_CYCLE_SFT 15
+#define CBR_RG_IDEAL_CYCLE_HI 27
+#define CBR_RG_IDEAL_CYCLE_SZ 13
+#define CBR_RG_EN_DP_VT_MON_MSK 0x00000001
+#define CBR_RG_EN_DP_VT_MON_I_MSK 0xfffffffe
+#define CBR_RG_EN_DP_VT_MON_SFT 0
+#define CBR_RG_EN_DP_VT_MON_HI 0
+#define CBR_RG_EN_DP_VT_MON_SZ 1
+#define CBR_RG_DP_VT_TH_HI_MSK 0x00000006
+#define CBR_RG_DP_VT_TH_HI_I_MSK 0xfffffff9
+#define CBR_RG_DP_VT_TH_HI_SFT 1
+#define CBR_RG_DP_VT_TH_HI_HI 2
+#define CBR_RG_DP_VT_TH_HI_SZ 2
+#define CBR_RG_DP_VT_TH_LO_MSK 0x00000018
+#define CBR_RG_DP_VT_TH_LO_I_MSK 0xffffffe7
+#define CBR_RG_DP_VT_TH_LO_SFT 3
+#define CBR_RG_DP_VT_TH_LO_HI 4
+#define CBR_RG_DP_VT_TH_LO_SZ 2
+#define CBR_RG_DP_VT_MON_TMR_MSK 0x00003fe0
+#define CBR_RG_DP_VT_MON_TMR_I_MSK 0xffffc01f
+#define CBR_RG_DP_VT_MON_TMR_SFT 5
+#define CBR_RG_DP_VT_MON_TMR_HI 13
+#define CBR_RG_DP_VT_MON_TMR_SZ 9
+#define CBR_RG_DP_CK320BY2_MSK 0x00004000
+#define CBR_RG_DP_CK320BY2_I_MSK 0xffffbfff
+#define CBR_RG_DP_CK320BY2_SFT 14
+#define CBR_RG_DP_CK320BY2_HI 14
+#define CBR_RG_DP_CK320BY2_SZ 1
+#define CBR_RG_SX_DELCTRL_MSK 0x001f8000
+#define CBR_RG_SX_DELCTRL_I_MSK 0xffe07fff
+#define CBR_RG_SX_DELCTRL_SFT 15
+#define CBR_RG_SX_DELCTRL_HI 20
+#define CBR_RG_SX_DELCTRL_SZ 6
+#define CBR_RG_DP_OD_TEST_MSK 0x00200000
+#define CBR_RG_DP_OD_TEST_I_MSK 0xffdfffff
+#define CBR_RG_DP_OD_TEST_SFT 21
+#define CBR_RG_DP_OD_TEST_HI 21
+#define CBR_RG_DP_OD_TEST_SZ 1
+#define CBR_RG_DP_BBPLL_BP_MSK 0x00000001
+#define CBR_RG_DP_BBPLL_BP_I_MSK 0xfffffffe
+#define CBR_RG_DP_BBPLL_BP_SFT 0
+#define CBR_RG_DP_BBPLL_BP_HI 0
+#define CBR_RG_DP_BBPLL_BP_SZ 1
+#define CBR_RG_DP_BBPLL_ICP_MSK 0x00000006
+#define CBR_RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
+#define CBR_RG_DP_BBPLL_ICP_SFT 1
+#define CBR_RG_DP_BBPLL_ICP_HI 2
+#define CBR_RG_DP_BBPLL_ICP_SZ 2
+#define CBR_RG_DP_BBPLL_IDUAL_MSK 0x00000018
+#define CBR_RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
+#define CBR_RG_DP_BBPLL_IDUAL_SFT 3
+#define CBR_RG_DP_BBPLL_IDUAL_HI 4
+#define CBR_RG_DP_BBPLL_IDUAL_SZ 2
+#define CBR_RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
+#define CBR_RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
+#define CBR_RG_DP_BBPLL_OD_TEST_SFT 5
+#define CBR_RG_DP_BBPLL_OD_TEST_HI 8
+#define CBR_RG_DP_BBPLL_OD_TEST_SZ 4
+#define CBR_RG_DP_BBPLL_PD_MSK 0x00000200
+#define CBR_RG_DP_BBPLL_PD_I_MSK 0xfffffdff
+#define CBR_RG_DP_BBPLL_PD_SFT 9
+#define CBR_RG_DP_BBPLL_PD_HI 9
+#define CBR_RG_DP_BBPLL_PD_SZ 1
+#define CBR_RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
+#define CBR_RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
+#define CBR_RG_DP_BBPLL_TESTSEL_SFT 10
+#define CBR_RG_DP_BBPLL_TESTSEL_HI 12
+#define CBR_RG_DP_BBPLL_TESTSEL_SZ 3
+#define CBR_RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
+#define CBR_RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
+#define CBR_RG_DP_BBPLL_PFD_DLY_SFT 13
+#define CBR_RG_DP_BBPLL_PFD_DLY_HI 14
+#define CBR_RG_DP_BBPLL_PFD_DLY_SZ 2
+#define CBR_RG_DP_RP_MSK 0x00038000
+#define CBR_RG_DP_RP_I_MSK 0xfffc7fff
+#define CBR_RG_DP_RP_SFT 15
+#define CBR_RG_DP_RP_HI 17
+#define CBR_RG_DP_RP_SZ 3
+#define CBR_RG_DP_RHP_MSK 0x000c0000
+#define CBR_RG_DP_RHP_I_MSK 0xfff3ffff
+#define CBR_RG_DP_RHP_SFT 18
+#define CBR_RG_DP_RHP_HI 19
+#define CBR_RG_DP_RHP_SZ 2
+#define CBR_RG_DP_DR3_MSK 0x00700000
+#define CBR_RG_DP_DR3_I_MSK 0xff8fffff
+#define CBR_RG_DP_DR3_SFT 20
+#define CBR_RG_DP_DR3_HI 22
+#define CBR_RG_DP_DR3_SZ 3
+#define CBR_RG_DP_DCP_MSK 0x07800000
+#define CBR_RG_DP_DCP_I_MSK 0xf87fffff
+#define CBR_RG_DP_DCP_SFT 23
+#define CBR_RG_DP_DCP_HI 26
+#define CBR_RG_DP_DCP_SZ 4
+#define CBR_RG_DP_DCS_MSK 0x78000000
+#define CBR_RG_DP_DCS_I_MSK 0x87ffffff
+#define CBR_RG_DP_DCS_SFT 27
+#define CBR_RG_DP_DCS_HI 30
+#define CBR_RG_DP_DCS_SZ 4
+#define CBR_RG_DP_FBDIV_MSK 0x00000fff
+#define CBR_RG_DP_FBDIV_I_MSK 0xfffff000
+#define CBR_RG_DP_FBDIV_SFT 0
+#define CBR_RG_DP_FBDIV_HI 11
+#define CBR_RG_DP_FBDIV_SZ 12
+#define CBR_RG_DP_FODIV_MSK 0x003ff000
+#define CBR_RG_DP_FODIV_I_MSK 0xffc00fff
+#define CBR_RG_DP_FODIV_SFT 12
+#define CBR_RG_DP_FODIV_HI 21
+#define CBR_RG_DP_FODIV_SZ 10
+#define CBR_RG_DP_REFDIV_MSK 0xffc00000
+#define CBR_RG_DP_REFDIV_I_MSK 0x003fffff
+#define CBR_RG_DP_REFDIV_SFT 22
+#define CBR_RG_DP_REFDIV_HI 31
+#define CBR_RG_DP_REFDIV_SZ 10
+#define CBR_RG_IDACAI_PGAG15_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG15_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG15_SFT 0
+#define CBR_RG_IDACAI_PGAG15_HI 5
+#define CBR_RG_IDACAI_PGAG15_SZ 6
+#define CBR_RG_IDACAQ_PGAG15_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG15_SFT 6
+#define CBR_RG_IDACAQ_PGAG15_HI 11
+#define CBR_RG_IDACAQ_PGAG15_SZ 6
+#define CBR_RG_IDACAI_PGAG14_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG14_SFT 12
+#define CBR_RG_IDACAI_PGAG14_HI 17
+#define CBR_RG_IDACAI_PGAG14_SZ 6
+#define CBR_RG_IDACAQ_PGAG14_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG14_SFT 18
+#define CBR_RG_IDACAQ_PGAG14_HI 23
+#define CBR_RG_IDACAQ_PGAG14_SZ 6
+#define CBR_RG_IDACAI_PGAG13_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG13_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG13_SFT 0
+#define CBR_RG_IDACAI_PGAG13_HI 5
+#define CBR_RG_IDACAI_PGAG13_SZ 6
+#define CBR_RG_IDACAQ_PGAG13_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG13_SFT 6
+#define CBR_RG_IDACAQ_PGAG13_HI 11
+#define CBR_RG_IDACAQ_PGAG13_SZ 6
+#define CBR_RG_IDACAI_PGAG12_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG12_SFT 12
+#define CBR_RG_IDACAI_PGAG12_HI 17
+#define CBR_RG_IDACAI_PGAG12_SZ 6
+#define CBR_RG_IDACAQ_PGAG12_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG12_SFT 18
+#define CBR_RG_IDACAQ_PGAG12_HI 23
+#define CBR_RG_IDACAQ_PGAG12_SZ 6
+#define CBR_RG_IDACAI_PGAG11_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG11_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG11_SFT 0
+#define CBR_RG_IDACAI_PGAG11_HI 5
+#define CBR_RG_IDACAI_PGAG11_SZ 6
+#define CBR_RG_IDACAQ_PGAG11_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG11_SFT 6
+#define CBR_RG_IDACAQ_PGAG11_HI 11
+#define CBR_RG_IDACAQ_PGAG11_SZ 6
+#define CBR_RG_IDACAI_PGAG10_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG10_SFT 12
+#define CBR_RG_IDACAI_PGAG10_HI 17
+#define CBR_RG_IDACAI_PGAG10_SZ 6
+#define CBR_RG_IDACAQ_PGAG10_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG10_SFT 18
+#define CBR_RG_IDACAQ_PGAG10_HI 23
+#define CBR_RG_IDACAQ_PGAG10_SZ 6
+#define CBR_RG_IDACAI_PGAG9_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG9_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG9_SFT 0
+#define CBR_RG_IDACAI_PGAG9_HI 5
+#define CBR_RG_IDACAI_PGAG9_SZ 6
+#define CBR_RG_IDACAQ_PGAG9_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG9_SFT 6
+#define CBR_RG_IDACAQ_PGAG9_HI 11
+#define CBR_RG_IDACAQ_PGAG9_SZ 6
+#define CBR_RG_IDACAI_PGAG8_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG8_SFT 12
+#define CBR_RG_IDACAI_PGAG8_HI 17
+#define CBR_RG_IDACAI_PGAG8_SZ 6
+#define CBR_RG_IDACAQ_PGAG8_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG8_SFT 18
+#define CBR_RG_IDACAQ_PGAG8_HI 23
+#define CBR_RG_IDACAQ_PGAG8_SZ 6
+#define CBR_RG_IDACAI_PGAG7_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG7_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG7_SFT 0
+#define CBR_RG_IDACAI_PGAG7_HI 5
+#define CBR_RG_IDACAI_PGAG7_SZ 6
+#define CBR_RG_IDACAQ_PGAG7_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG7_SFT 6
+#define CBR_RG_IDACAQ_PGAG7_HI 11
+#define CBR_RG_IDACAQ_PGAG7_SZ 6
+#define CBR_RG_IDACAI_PGAG6_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG6_SFT 12
+#define CBR_RG_IDACAI_PGAG6_HI 17
+#define CBR_RG_IDACAI_PGAG6_SZ 6
+#define CBR_RG_IDACAQ_PGAG6_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG6_SFT 18
+#define CBR_RG_IDACAQ_PGAG6_HI 23
+#define CBR_RG_IDACAQ_PGAG6_SZ 6
+#define CBR_RG_IDACAI_PGAG5_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG5_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG5_SFT 0
+#define CBR_RG_IDACAI_PGAG5_HI 5
+#define CBR_RG_IDACAI_PGAG5_SZ 6
+#define CBR_RG_IDACAQ_PGAG5_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG5_SFT 6
+#define CBR_RG_IDACAQ_PGAG5_HI 11
+#define CBR_RG_IDACAQ_PGAG5_SZ 6
+#define CBR_RG_IDACAI_PGAG4_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG4_SFT 12
+#define CBR_RG_IDACAI_PGAG4_HI 17
+#define CBR_RG_IDACAI_PGAG4_SZ 6
+#define CBR_RG_IDACAQ_PGAG4_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG4_SFT 18
+#define CBR_RG_IDACAQ_PGAG4_HI 23
+#define CBR_RG_IDACAQ_PGAG4_SZ 6
+#define CBR_RG_IDACAI_PGAG3_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG3_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG3_SFT 0
+#define CBR_RG_IDACAI_PGAG3_HI 5
+#define CBR_RG_IDACAI_PGAG3_SZ 6
+#define CBR_RG_IDACAQ_PGAG3_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG3_SFT 6
+#define CBR_RG_IDACAQ_PGAG3_HI 11
+#define CBR_RG_IDACAQ_PGAG3_SZ 6
+#define CBR_RG_IDACAI_PGAG2_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG2_SFT 12
+#define CBR_RG_IDACAI_PGAG2_HI 17
+#define CBR_RG_IDACAI_PGAG2_SZ 6
+#define CBR_RG_IDACAQ_PGAG2_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG2_SFT 18
+#define CBR_RG_IDACAQ_PGAG2_HI 23
+#define CBR_RG_IDACAQ_PGAG2_SZ 6
+#define CBR_RG_IDACAI_PGAG1_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG1_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG1_SFT 0
+#define CBR_RG_IDACAI_PGAG1_HI 5
+#define CBR_RG_IDACAI_PGAG1_SZ 6
+#define CBR_RG_IDACAQ_PGAG1_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG1_SFT 6
+#define CBR_RG_IDACAQ_PGAG1_HI 11
+#define CBR_RG_IDACAQ_PGAG1_SZ 6
+#define CBR_RG_IDACAI_PGAG0_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG0_SFT 12
+#define CBR_RG_IDACAI_PGAG0_HI 17
+#define CBR_RG_IDACAI_PGAG0_SZ 6
+#define CBR_RG_IDACAQ_PGAG0_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG0_SFT 18
+#define CBR_RG_IDACAQ_PGAG0_HI 23
+#define CBR_RG_IDACAQ_PGAG0_SZ 6
+#define CBR_RG_EN_RCAL_MSK 0x00000001
+#define CBR_RG_EN_RCAL_I_MSK 0xfffffffe
+#define CBR_RG_EN_RCAL_SFT 0
+#define CBR_RG_EN_RCAL_HI 0
+#define CBR_RG_EN_RCAL_SZ 1
+#define CBR_RG_RCAL_SPD_MSK 0x00000002
+#define CBR_RG_RCAL_SPD_I_MSK 0xfffffffd
+#define CBR_RG_RCAL_SPD_SFT 1
+#define CBR_RG_RCAL_SPD_HI 1
+#define CBR_RG_RCAL_SPD_SZ 1
+#define CBR_RG_RCAL_TMR_MSK 0x000001fc
+#define CBR_RG_RCAL_TMR_I_MSK 0xfffffe03
+#define CBR_RG_RCAL_TMR_SFT 2
+#define CBR_RG_RCAL_TMR_HI 8
+#define CBR_RG_RCAL_TMR_SZ 7
+#define CBR_RG_RCAL_CODE_CWR_MSK 0x00000200
+#define CBR_RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
+#define CBR_RG_RCAL_CODE_CWR_SFT 9
+#define CBR_RG_RCAL_CODE_CWR_HI 9
+#define CBR_RG_RCAL_CODE_CWR_SZ 1
+#define CBR_RG_RCAL_CODE_CWD_MSK 0x00007c00
+#define CBR_RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
+#define CBR_RG_RCAL_CODE_CWD_SFT 10
+#define CBR_RG_RCAL_CODE_CWD_HI 14
+#define CBR_RG_RCAL_CODE_CWD_SZ 5
+#define CBR_RG_SX_SUB_SEL_CWR_MSK 0x00000001
+#define CBR_RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
+#define CBR_RG_SX_SUB_SEL_CWR_SFT 0
+#define CBR_RG_SX_SUB_SEL_CWR_HI 0
+#define CBR_RG_SX_SUB_SEL_CWR_SZ 1
+#define CBR_RG_SX_SUB_SEL_CWD_MSK 0x000000fe
+#define CBR_RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
+#define CBR_RG_SX_SUB_SEL_CWD_SFT 1
+#define CBR_RG_SX_SUB_SEL_CWD_HI 7
+#define CBR_RG_SX_SUB_SEL_CWD_SZ 7
+#define CBR_RG_DP_BBPLL_BS_CWR_MSK 0x00000100
+#define CBR_RG_DP_BBPLL_BS_CWR_I_MSK 0xfffffeff
+#define CBR_RG_DP_BBPLL_BS_CWR_SFT 8
+#define CBR_RG_DP_BBPLL_BS_CWR_HI 8
+#define CBR_RG_DP_BBPLL_BS_CWR_SZ 1
+#define CBR_RG_DP_BBPLL_BS_CWD_MSK 0x00007e00
+#define CBR_RG_DP_BBPLL_BS_CWD_I_MSK 0xffff81ff
+#define CBR_RG_DP_BBPLL_BS_CWD_SFT 9
+#define CBR_RG_DP_BBPLL_BS_CWD_HI 14
+#define CBR_RG_DP_BBPLL_BS_CWD_SZ 6
+#define CBR_RCAL_RDY_MSK 0x00000001
+#define CBR_RCAL_RDY_I_MSK 0xfffffffe
+#define CBR_RCAL_RDY_SFT 0
+#define CBR_RCAL_RDY_HI 0
+#define CBR_RCAL_RDY_SZ 1
+#define CBR_DA_LCK_RDY_MSK 0x00000002
+#define CBR_DA_LCK_RDY_I_MSK 0xfffffffd
+#define CBR_DA_LCK_RDY_SFT 1
+#define CBR_DA_LCK_RDY_HI 1
+#define CBR_DA_LCK_RDY_SZ 1
+#define CBR_VT_MON_RDY_MSK 0x00000004
+#define CBR_VT_MON_RDY_I_MSK 0xfffffffb
+#define CBR_VT_MON_RDY_SFT 2
+#define CBR_VT_MON_RDY_HI 2
+#define CBR_VT_MON_RDY_SZ 1
+#define CBR_DP_VT_MON_RDY_MSK 0x00000008
+#define CBR_DP_VT_MON_RDY_I_MSK 0xfffffff7
+#define CBR_DP_VT_MON_RDY_SFT 3
+#define CBR_DP_VT_MON_RDY_HI 3
+#define CBR_DP_VT_MON_RDY_SZ 1
+#define CBR_CH_RDY_MSK 0x00000010
+#define CBR_CH_RDY_I_MSK 0xffffffef
+#define CBR_CH_RDY_SFT 4
+#define CBR_CH_RDY_HI 4
+#define CBR_CH_RDY_SZ 1
+#define CBR_DA_R_CODE_LUT_MSK 0x000007c0
+#define CBR_DA_R_CODE_LUT_I_MSK 0xfffff83f
+#define CBR_DA_R_CODE_LUT_SFT 6
+#define CBR_DA_R_CODE_LUT_HI 10
+#define CBR_DA_R_CODE_LUT_SZ 5
+#define CBR_AD_SX_VT_MON_Q_MSK 0x00001800
+#define CBR_AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
+#define CBR_AD_SX_VT_MON_Q_SFT 11
+#define CBR_AD_SX_VT_MON_Q_HI 12
+#define CBR_AD_SX_VT_MON_Q_SZ 2
+#define CBR_AD_DP_VT_MON_Q_MSK 0x00006000
+#define CBR_AD_DP_VT_MON_Q_I_MSK 0xffff9fff
+#define CBR_AD_DP_VT_MON_Q_SFT 13
+#define CBR_AD_DP_VT_MON_Q_HI 14
+#define CBR_AD_DP_VT_MON_Q_SZ 2
+#define CBR_DA_R_CAL_CODE_MSK 0x0000001f
+#define CBR_DA_R_CAL_CODE_I_MSK 0xffffffe0
+#define CBR_DA_R_CAL_CODE_SFT 0
+#define CBR_DA_R_CAL_CODE_HI 4
+#define CBR_DA_R_CAL_CODE_SZ 5
+#define CBR_DA_SX_SUB_SEL_MSK 0x00000fe0
+#define CBR_DA_SX_SUB_SEL_I_MSK 0xfffff01f
+#define CBR_DA_SX_SUB_SEL_SFT 5
+#define CBR_DA_SX_SUB_SEL_HI 11
+#define CBR_DA_SX_SUB_SEL_SZ 7
+#define CBR_DA_DP_BBPLL_BS_MSK 0x0003f000
+#define CBR_DA_DP_BBPLL_BS_I_MSK 0xfffc0fff
+#define CBR_DA_DP_BBPLL_BS_SFT 12
+#define CBR_DA_DP_BBPLL_BS_HI 17
+#define CBR_DA_DP_BBPLL_BS_SZ 6
+#define CBR_TX_EN_MSK 0x00000001
+#define CBR_TX_EN_I_MSK 0xfffffffe
+#define CBR_TX_EN_SFT 0
+#define CBR_TX_EN_HI 0
+#define CBR_TX_EN_SZ 1
+#define CBR_TX_CNT_RST_MSK 0x00000002
+#define CBR_TX_CNT_RST_I_MSK 0xfffffffd
+#define CBR_TX_CNT_RST_SFT 1
+#define CBR_TX_CNT_RST_HI 1
+#define CBR_TX_CNT_RST_SZ 1
+#define CBR_IFS_TIME_MSK 0x000000fc
+#define CBR_IFS_TIME_I_MSK 0xffffff03
+#define CBR_IFS_TIME_SFT 2
+#define CBR_IFS_TIME_HI 7
+#define CBR_IFS_TIME_SZ 6
+#define CBR_LENGTH_TARGET_MSK 0x000fff00
+#define CBR_LENGTH_TARGET_I_MSK 0xfff000ff
+#define CBR_LENGTH_TARGET_SFT 8
+#define CBR_LENGTH_TARGET_HI 19
+#define CBR_LENGTH_TARGET_SZ 12
+#define CBR_TX_CNT_TARGET_MSK 0xff000000
+#define CBR_TX_CNT_TARGET_I_MSK 0x00ffffff
+#define CBR_TX_CNT_TARGET_SFT 24
+#define CBR_TX_CNT_TARGET_HI 31
+#define CBR_TX_CNT_TARGET_SZ 8
+#define CBR_TC_CNT_TARGET_MSK 0x00ffffff
+#define CBR_TC_CNT_TARGET_I_MSK 0xff000000
+#define CBR_TC_CNT_TARGET_SFT 0
+#define CBR_TC_CNT_TARGET_HI 23
+#define CBR_TC_CNT_TARGET_SZ 24
+#define CBR_PLCP_PSDU_DATA_MEM_MSK 0x000000ff
+#define CBR_PLCP_PSDU_DATA_MEM_I_MSK 0xffffff00
+#define CBR_PLCP_PSDU_DATA_MEM_SFT 0
+#define CBR_PLCP_PSDU_DATA_MEM_HI 7
+#define CBR_PLCP_PSDU_DATA_MEM_SZ 8
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_MSK 0x00000100
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_I_MSK 0xfffffeff
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SFT 8
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_HI 8
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SZ 1
+#define CBR_PLCP_BYTE_LENGTH_MSK 0x001ffe00
+#define CBR_PLCP_BYTE_LENGTH_I_MSK 0xffe001ff
+#define CBR_PLCP_BYTE_LENGTH_SFT 9
+#define CBR_PLCP_BYTE_LENGTH_HI 20
+#define CBR_PLCP_BYTE_LENGTH_SZ 12
+#define CBR_PLCP_PSDU_RATE_MSK 0x00600000
+#define CBR_PLCP_PSDU_RATE_I_MSK 0xff9fffff
+#define CBR_PLCP_PSDU_RATE_SFT 21
+#define CBR_PLCP_PSDU_RATE_HI 22
+#define CBR_PLCP_PSDU_RATE_SZ 2
+#define CBR_TAIL_TIME_MSK 0x1f800000
+#define CBR_TAIL_TIME_I_MSK 0xe07fffff
+#define CBR_TAIL_TIME_SFT 23
+#define CBR_TAIL_TIME_HI 28
+#define CBR_TAIL_TIME_SZ 6
+#define CBR_RG_O_PAD_PD_MSK 0x00000001
+#define CBR_RG_O_PAD_PD_I_MSK 0xfffffffe
+#define CBR_RG_O_PAD_PD_SFT 0
+#define CBR_RG_O_PAD_PD_HI 0
+#define CBR_RG_O_PAD_PD_SZ 1
+#define CBR_RG_I_PAD_PD_MSK 0x00000002
+#define CBR_RG_I_PAD_PD_I_MSK 0xfffffffd
+#define CBR_RG_I_PAD_PD_SFT 1
+#define CBR_RG_I_PAD_PD_HI 1
+#define CBR_RG_I_PAD_PD_SZ 1
+#define CBR_SEL_ADCKP_INV_MSK 0x00000004
+#define CBR_SEL_ADCKP_INV_I_MSK 0xfffffffb
+#define CBR_SEL_ADCKP_INV_SFT 2
+#define CBR_SEL_ADCKP_INV_HI 2
+#define CBR_SEL_ADCKP_INV_SZ 1
+#define CBR_RG_PAD_DS_MSK 0x00000008
+#define CBR_RG_PAD_DS_I_MSK 0xfffffff7
+#define CBR_RG_PAD_DS_SFT 3
+#define CBR_RG_PAD_DS_HI 3
+#define CBR_RG_PAD_DS_SZ 1
+#define CBR_SEL_ADCKP_MUX_MSK 0x00000010
+#define CBR_SEL_ADCKP_MUX_I_MSK 0xffffffef
+#define CBR_SEL_ADCKP_MUX_SFT 4
+#define CBR_SEL_ADCKP_MUX_HI 4
+#define CBR_SEL_ADCKP_MUX_SZ 1
+#define CBR_RG_PAD_DS_CLK_MSK 0x00000020
+#define CBR_RG_PAD_DS_CLK_I_MSK 0xffffffdf
+#define CBR_RG_PAD_DS_CLK_SFT 5
+#define CBR_RG_PAD_DS_CLK_HI 5
+#define CBR_RG_PAD_DS_CLK_SZ 1
+#define CBR_INTP_SEL_MSK 0x00000200
+#define CBR_INTP_SEL_I_MSK 0xfffffdff
+#define CBR_INTP_SEL_SFT 9
+#define CBR_INTP_SEL_HI 9
+#define CBR_INTP_SEL_SZ 1
+#define CBR_IQ_SWP_MSK 0x00000400
+#define CBR_IQ_SWP_I_MSK 0xfffffbff
+#define CBR_IQ_SWP_SFT 10
+#define CBR_IQ_SWP_HI 10
+#define CBR_IQ_SWP_SZ 1
+#define CBR_RG_EN_EXT_DA_MSK 0x00000800
+#define CBR_RG_EN_EXT_DA_I_MSK 0xfffff7ff
+#define CBR_RG_EN_EXT_DA_SFT 11
+#define CBR_RG_EN_EXT_DA_HI 11
+#define CBR_RG_EN_EXT_DA_SZ 1
+#define CBR_RG_DIS_DA_OFFSET_MSK 0x00001000
+#define CBR_RG_DIS_DA_OFFSET_I_MSK 0xffffefff
+#define CBR_RG_DIS_DA_OFFSET_SFT 12
+#define CBR_RG_DIS_DA_OFFSET_HI 12
+#define CBR_RG_DIS_DA_OFFSET_SZ 1
+#define CBR_DBG_SEL_MSK 0x000f0000
+#define CBR_DBG_SEL_I_MSK 0xfff0ffff
+#define CBR_DBG_SEL_SFT 16
+#define CBR_DBG_SEL_HI 19
+#define CBR_DBG_SEL_SZ 4
+#define CBR_DBG_EN_MSK 0x00100000
+#define CBR_DBG_EN_I_MSK 0xffefffff
+#define CBR_DBG_EN_SFT 20
+#define CBR_DBG_EN_HI 20
+#define CBR_DBG_EN_SZ 1
+#define CBR_RG_PKT_GEN_TX_CNT_MSK 0xffffffff
+#define CBR_RG_PKT_GEN_TX_CNT_I_MSK 0x00000000
+#define CBR_RG_PKT_GEN_TX_CNT_SFT 0
+#define CBR_RG_PKT_GEN_TX_CNT_HI 31
+#define CBR_RG_PKT_GEN_TX_CNT_SZ 32
+#define CBR_TP_SEL_MSK 0x0000001f
+#define CBR_TP_SEL_I_MSK 0xffffffe0
+#define CBR_TP_SEL_SFT 0
+#define CBR_TP_SEL_HI 4
+#define CBR_TP_SEL_SZ 5
+#define CBR_IDEAL_IQ_EN_MSK 0x00000020
+#define CBR_IDEAL_IQ_EN_I_MSK 0xffffffdf
+#define CBR_IDEAL_IQ_EN_SFT 5
+#define CBR_IDEAL_IQ_EN_HI 5
+#define CBR_IDEAL_IQ_EN_SZ 1
+#define CBR_DATA_OUT_SEL_MSK 0x000001c0
+#define CBR_DATA_OUT_SEL_I_MSK 0xfffffe3f
+#define CBR_DATA_OUT_SEL_SFT 6
+#define CBR_DATA_OUT_SEL_HI 8
+#define CBR_DATA_OUT_SEL_SZ 3
+#define CBR_TWO_TONE_EN_MSK 0x00000200
+#define CBR_TWO_TONE_EN_I_MSK 0xfffffdff
+#define CBR_TWO_TONE_EN_SFT 9
+#define CBR_TWO_TONE_EN_HI 9
+#define CBR_TWO_TONE_EN_SZ 1
+#define CBR_FREQ_SEL_MSK 0x00ff0000
+#define CBR_FREQ_SEL_I_MSK 0xff00ffff
+#define CBR_FREQ_SEL_SFT 16
+#define CBR_FREQ_SEL_HI 23
+#define CBR_FREQ_SEL_SZ 8
+#define CBR_IQ_SCALE_MSK 0xff000000
+#define CBR_IQ_SCALE_I_MSK 0x00ffffff
+#define CBR_IQ_SCALE_SFT 24
+#define CBR_IQ_SCALE_HI 31
+#define CBR_IQ_SCALE_SZ 8
+#define CPU_QUE_POP_MSK 0x00000001
+#define CPU_QUE_POP_I_MSK 0xfffffffe
+#define CPU_QUE_POP_SFT 0
+#define CPU_QUE_POP_HI 0
+#define CPU_QUE_POP_SZ 1
+#define CPU_INT_MSK 0x00000004
+#define CPU_INT_I_MSK 0xfffffffb
+#define CPU_INT_SFT 2
+#define CPU_INT_HI 2
+#define CPU_INT_SZ 1
+#define CPU_ID_TB0_MSK 0xffffffff
+#define CPU_ID_TB0_I_MSK 0x00000000
+#define CPU_ID_TB0_SFT 0
+#define CPU_ID_TB0_HI 31
+#define CPU_ID_TB0_SZ 32
+#define CPU_ID_TB1_MSK 0xffffffff
+#define CPU_ID_TB1_I_MSK 0x00000000
+#define CPU_ID_TB1_SFT 0
+#define CPU_ID_TB1_HI 31
+#define CPU_ID_TB1_SZ 32
+#define HW_PKTID_MSK 0x000007ff
+#define HW_PKTID_I_MSK 0xfffff800
+#define HW_PKTID_SFT 0
+#define HW_PKTID_HI 10
+#define HW_PKTID_SZ 11
+#define CH0_INT_ADDR_MSK 0xffffffff
+#define CH0_INT_ADDR_I_MSK 0x00000000
+#define CH0_INT_ADDR_SFT 0
+#define CH0_INT_ADDR_HI 31
+#define CH0_INT_ADDR_SZ 32
+#define PRI_HW_PKTID_MSK 0x000007ff
+#define PRI_HW_PKTID_I_MSK 0xfffff800
+#define PRI_HW_PKTID_SFT 0
+#define PRI_HW_PKTID_HI 10
+#define PRI_HW_PKTID_SZ 11
+#define CH0_FULL_MSK 0x00000001
+#define CH0_FULL_I_MSK 0xfffffffe
+#define CH0_FULL_SFT 0
+#define CH0_FULL_HI 0
+#define CH0_FULL_SZ 1
+#define FF0_EMPTY_MSK 0x00000002
+#define FF0_EMPTY_I_MSK 0xfffffffd
+#define FF0_EMPTY_SFT 1
+#define FF0_EMPTY_HI 1
+#define FF0_EMPTY_SZ 1
+#define RLS_BUSY_MSK 0x00000200
+#define RLS_BUSY_I_MSK 0xfffffdff
+#define RLS_BUSY_SFT 9
+#define RLS_BUSY_HI 9
+#define RLS_BUSY_SZ 1
+#define RLS_COUNT_CLR_MSK 0x00000400
+#define RLS_COUNT_CLR_I_MSK 0xfffffbff
+#define RLS_COUNT_CLR_SFT 10
+#define RLS_COUNT_CLR_HI 10
+#define RLS_COUNT_CLR_SZ 1
+#define RTN_COUNT_CLR_MSK 0x00000800
+#define RTN_COUNT_CLR_I_MSK 0xfffff7ff
+#define RTN_COUNT_CLR_SFT 11
+#define RTN_COUNT_CLR_HI 11
+#define RTN_COUNT_CLR_SZ 1
+#define RLS_COUNT_MSK 0x00ff0000
+#define RLS_COUNT_I_MSK 0xff00ffff
+#define RLS_COUNT_SFT 16
+#define RLS_COUNT_HI 23
+#define RLS_COUNT_SZ 8
+#define RTN_COUNT_MSK 0xff000000
+#define RTN_COUNT_I_MSK 0x00ffffff
+#define RTN_COUNT_SFT 24
+#define RTN_COUNT_HI 31
+#define RTN_COUNT_SZ 8
+#define FF0_CNT_MSK 0x0000001f
+#define FF0_CNT_I_MSK 0xffffffe0
+#define FF0_CNT_SFT 0
+#define FF0_CNT_HI 4
+#define FF0_CNT_SZ 5
+#define FF1_CNT_MSK 0x000001e0
+#define FF1_CNT_I_MSK 0xfffffe1f
+#define FF1_CNT_SFT 5
+#define FF1_CNT_HI 8
+#define FF1_CNT_SZ 4
+#define FF3_CNT_MSK 0x00003800
+#define FF3_CNT_I_MSK 0xffffc7ff
+#define FF3_CNT_SFT 11
+#define FF3_CNT_HI 13
+#define FF3_CNT_SZ 3
+#define FF5_CNT_MSK 0x000e0000
+#define FF5_CNT_I_MSK 0xfff1ffff
+#define FF5_CNT_SFT 17
+#define FF5_CNT_HI 19
+#define FF5_CNT_SZ 3
+#define FF6_CNT_MSK 0x00700000
+#define FF6_CNT_I_MSK 0xff8fffff
+#define FF6_CNT_SFT 20
+#define FF6_CNT_HI 22
+#define FF6_CNT_SZ 3
+#define FF7_CNT_MSK 0x03800000
+#define FF7_CNT_I_MSK 0xfc7fffff
+#define FF7_CNT_SFT 23
+#define FF7_CNT_HI 25
+#define FF7_CNT_SZ 3
+#define FF8_CNT_MSK 0x1c000000
+#define FF8_CNT_I_MSK 0xe3ffffff
+#define FF8_CNT_SFT 26
+#define FF8_CNT_HI 28
+#define FF8_CNT_SZ 3
+#define FF9_CNT_MSK 0xe0000000
+#define FF9_CNT_I_MSK 0x1fffffff
+#define FF9_CNT_SFT 29
+#define FF9_CNT_HI 31
+#define FF9_CNT_SZ 3
+#define FF10_CNT_MSK 0x00000007
+#define FF10_CNT_I_MSK 0xfffffff8
+#define FF10_CNT_SFT 0
+#define FF10_CNT_HI 2
+#define FF10_CNT_SZ 3
+#define FF11_CNT_MSK 0x00000038
+#define FF11_CNT_I_MSK 0xffffffc7
+#define FF11_CNT_SFT 3
+#define FF11_CNT_HI 5
+#define FF11_CNT_SZ 3
+#define FF12_CNT_MSK 0x000001c0
+#define FF12_CNT_I_MSK 0xfffffe3f
+#define FF12_CNT_SFT 6
+#define FF12_CNT_HI 8
+#define FF12_CNT_SZ 3
+#define FF13_CNT_MSK 0x00000600
+#define FF13_CNT_I_MSK 0xfffff9ff
+#define FF13_CNT_SFT 9
+#define FF13_CNT_HI 10
+#define FF13_CNT_SZ 2
+#define FF14_CNT_MSK 0x00001800
+#define FF14_CNT_I_MSK 0xffffe7ff
+#define FF14_CNT_SFT 11
+#define FF14_CNT_HI 12
+#define FF14_CNT_SZ 2
+#define FF15_CNT_MSK 0x00006000
+#define FF15_CNT_I_MSK 0xffff9fff
+#define FF15_CNT_SFT 13
+#define FF15_CNT_HI 14
+#define FF15_CNT_SZ 2
+#define FF4_CNT_MSK 0x000f8000
+#define FF4_CNT_I_MSK 0xfff07fff
+#define FF4_CNT_SFT 15
+#define FF4_CNT_HI 19
+#define FF4_CNT_SZ 5
+#define FF2_CNT_MSK 0x00700000
+#define FF2_CNT_I_MSK 0xff8fffff
+#define FF2_CNT_SFT 20
+#define FF2_CNT_HI 22
+#define FF2_CNT_SZ 3
+#define CH1_FULL_MSK 0x00000002
+#define CH1_FULL_I_MSK 0xfffffffd
+#define CH1_FULL_SFT 1
+#define CH1_FULL_HI 1
+#define CH1_FULL_SZ 1
+#define CH2_FULL_MSK 0x00000004
+#define CH2_FULL_I_MSK 0xfffffffb
+#define CH2_FULL_SFT 2
+#define CH2_FULL_HI 2
+#define CH2_FULL_SZ 1
+#define CH3_FULL_MSK 0x00000008
+#define CH3_FULL_I_MSK 0xfffffff7
+#define CH3_FULL_SFT 3
+#define CH3_FULL_HI 3
+#define CH3_FULL_SZ 1
+#define CH4_FULL_MSK 0x00000010
+#define CH4_FULL_I_MSK 0xffffffef
+#define CH4_FULL_SFT 4
+#define CH4_FULL_HI 4
+#define CH4_FULL_SZ 1
+#define CH5_FULL_MSK 0x00000020
+#define CH5_FULL_I_MSK 0xffffffdf
+#define CH5_FULL_SFT 5
+#define CH5_FULL_HI 5
+#define CH5_FULL_SZ 1
+#define CH6_FULL_MSK 0x00000040
+#define CH6_FULL_I_MSK 0xffffffbf
+#define CH6_FULL_SFT 6
+#define CH6_FULL_HI 6
+#define CH6_FULL_SZ 1
+#define CH7_FULL_MSK 0x00000080
+#define CH7_FULL_I_MSK 0xffffff7f
+#define CH7_FULL_SFT 7
+#define CH7_FULL_HI 7
+#define CH7_FULL_SZ 1
+#define CH8_FULL_MSK 0x00000100
+#define CH8_FULL_I_MSK 0xfffffeff
+#define CH8_FULL_SFT 8
+#define CH8_FULL_HI 8
+#define CH8_FULL_SZ 1
+#define CH9_FULL_MSK 0x00000200
+#define CH9_FULL_I_MSK 0xfffffdff
+#define CH9_FULL_SFT 9
+#define CH9_FULL_HI 9
+#define CH9_FULL_SZ 1
+#define CH10_FULL_MSK 0x00000400
+#define CH10_FULL_I_MSK 0xfffffbff
+#define CH10_FULL_SFT 10
+#define CH10_FULL_HI 10
+#define CH10_FULL_SZ 1
+#define CH11_FULL_MSK 0x00000800
+#define CH11_FULL_I_MSK 0xfffff7ff
+#define CH11_FULL_SFT 11
+#define CH11_FULL_HI 11
+#define CH11_FULL_SZ 1
+#define CH12_FULL_MSK 0x00001000
+#define CH12_FULL_I_MSK 0xffffefff
+#define CH12_FULL_SFT 12
+#define CH12_FULL_HI 12
+#define CH12_FULL_SZ 1
+#define CH13_FULL_MSK 0x00002000
+#define CH13_FULL_I_MSK 0xffffdfff
+#define CH13_FULL_SFT 13
+#define CH13_FULL_HI 13
+#define CH13_FULL_SZ 1
+#define CH14_FULL_MSK 0x00004000
+#define CH14_FULL_I_MSK 0xffffbfff
+#define CH14_FULL_SFT 14
+#define CH14_FULL_HI 14
+#define CH14_FULL_SZ 1
+#define CH15_FULL_MSK 0x00008000
+#define CH15_FULL_I_MSK 0xffff7fff
+#define CH15_FULL_SFT 15
+#define CH15_FULL_HI 15
+#define CH15_FULL_SZ 1
+#define HALT_CH0_MSK 0x00000001
+#define HALT_CH0_I_MSK 0xfffffffe
+#define HALT_CH0_SFT 0
+#define HALT_CH0_HI 0
+#define HALT_CH0_SZ 1
+#define HALT_CH1_MSK 0x00000002
+#define HALT_CH1_I_MSK 0xfffffffd
+#define HALT_CH1_SFT 1
+#define HALT_CH1_HI 1
+#define HALT_CH1_SZ 1
+#define HALT_CH2_MSK 0x00000004
+#define HALT_CH2_I_MSK 0xfffffffb
+#define HALT_CH2_SFT 2
+#define HALT_CH2_HI 2
+#define HALT_CH2_SZ 1
+#define HALT_CH3_MSK 0x00000008
+#define HALT_CH3_I_MSK 0xfffffff7
+#define HALT_CH3_SFT 3
+#define HALT_CH3_HI 3
+#define HALT_CH3_SZ 1
+#define HALT_CH4_MSK 0x00000010
+#define HALT_CH4_I_MSK 0xffffffef
+#define HALT_CH4_SFT 4
+#define HALT_CH4_HI 4
+#define HALT_CH4_SZ 1
+#define HALT_CH5_MSK 0x00000020
+#define HALT_CH5_I_MSK 0xffffffdf
+#define HALT_CH5_SFT 5
+#define HALT_CH5_HI 5
+#define HALT_CH5_SZ 1
+#define HALT_CH6_MSK 0x00000040
+#define HALT_CH6_I_MSK 0xffffffbf
+#define HALT_CH6_SFT 6
+#define HALT_CH6_HI 6
+#define HALT_CH6_SZ 1
+#define HALT_CH7_MSK 0x00000080
+#define HALT_CH7_I_MSK 0xffffff7f
+#define HALT_CH7_SFT 7
+#define HALT_CH7_HI 7
+#define HALT_CH7_SZ 1
+#define HALT_CH8_MSK 0x00000100
+#define HALT_CH8_I_MSK 0xfffffeff
+#define HALT_CH8_SFT 8
+#define HALT_CH8_HI 8
+#define HALT_CH8_SZ 1
+#define HALT_CH9_MSK 0x00000200
+#define HALT_CH9_I_MSK 0xfffffdff
+#define HALT_CH9_SFT 9
+#define HALT_CH9_HI 9
+#define HALT_CH9_SZ 1
+#define HALT_CH10_MSK 0x00000400
+#define HALT_CH10_I_MSK 0xfffffbff
+#define HALT_CH10_SFT 10
+#define HALT_CH10_HI 10
+#define HALT_CH10_SZ 1
+#define HALT_CH11_MSK 0x00000800
+#define HALT_CH11_I_MSK 0xfffff7ff
+#define HALT_CH11_SFT 11
+#define HALT_CH11_HI 11
+#define HALT_CH11_SZ 1
+#define HALT_CH12_MSK 0x00001000
+#define HALT_CH12_I_MSK 0xffffefff
+#define HALT_CH12_SFT 12
+#define HALT_CH12_HI 12
+#define HALT_CH12_SZ 1
+#define HALT_CH13_MSK 0x00002000
+#define HALT_CH13_I_MSK 0xffffdfff
+#define HALT_CH13_SFT 13
+#define HALT_CH13_HI 13
+#define HALT_CH13_SZ 1
+#define HALT_CH14_MSK 0x00004000
+#define HALT_CH14_I_MSK 0xffffbfff
+#define HALT_CH14_SFT 14
+#define HALT_CH14_HI 14
+#define HALT_CH14_SZ 1
+#define HALT_CH15_MSK 0x00008000
+#define HALT_CH15_I_MSK 0xffff7fff
+#define HALT_CH15_SFT 15
+#define HALT_CH15_HI 15
+#define HALT_CH15_SZ 1
+#define STOP_MBOX_MSK 0x00010000
+#define STOP_MBOX_I_MSK 0xfffeffff
+#define STOP_MBOX_SFT 16
+#define STOP_MBOX_HI 16
+#define STOP_MBOX_SZ 1
+#define MB_ERR_AUTO_HALT_EN_MSK 0x00100000
+#define MB_ERR_AUTO_HALT_EN_I_MSK 0xffefffff
+#define MB_ERR_AUTO_HALT_EN_SFT 20
+#define MB_ERR_AUTO_HALT_EN_HI 20
+#define MB_ERR_AUTO_HALT_EN_SZ 1
+#define MB_EXCEPT_CLR_MSK 0x00200000
+#define MB_EXCEPT_CLR_I_MSK 0xffdfffff
+#define MB_EXCEPT_CLR_SFT 21
+#define MB_EXCEPT_CLR_HI 21
+#define MB_EXCEPT_CLR_SZ 1
+#define MB_EXCEPT_CASE_MSK 0xff000000
+#define MB_EXCEPT_CASE_I_MSK 0x00ffffff
+#define MB_EXCEPT_CASE_SFT 24
+#define MB_EXCEPT_CASE_HI 31
+#define MB_EXCEPT_CASE_SZ 8
+#define MB_DBG_TIME_STEP_MSK 0x0000ffff
+#define MB_DBG_TIME_STEP_I_MSK 0xffff0000
+#define MB_DBG_TIME_STEP_SFT 0
+#define MB_DBG_TIME_STEP_HI 15
+#define MB_DBG_TIME_STEP_SZ 16
+#define DBG_TYPE_MSK 0x00030000
+#define DBG_TYPE_I_MSK 0xfffcffff
+#define DBG_TYPE_SFT 16
+#define DBG_TYPE_HI 17
+#define DBG_TYPE_SZ 2
+#define MB_DBG_CLR_MSK 0x00040000
+#define MB_DBG_CLR_I_MSK 0xfffbffff
+#define MB_DBG_CLR_SFT 18
+#define MB_DBG_CLR_HI 18
+#define MB_DBG_CLR_SZ 1
+#define DBG_ALC_LOG_EN_MSK 0x00080000
+#define DBG_ALC_LOG_EN_I_MSK 0xfff7ffff
+#define DBG_ALC_LOG_EN_SFT 19
+#define DBG_ALC_LOG_EN_HI 19
+#define DBG_ALC_LOG_EN_SZ 1
+#define MB_DBG_COUNTER_EN_MSK 0x01000000
+#define MB_DBG_COUNTER_EN_I_MSK 0xfeffffff
+#define MB_DBG_COUNTER_EN_SFT 24
+#define MB_DBG_COUNTER_EN_HI 24
+#define MB_DBG_COUNTER_EN_SZ 1
+#define MB_DBG_EN_MSK 0x80000000
+#define MB_DBG_EN_I_MSK 0x7fffffff
+#define MB_DBG_EN_SFT 31
+#define MB_DBG_EN_HI 31
+#define MB_DBG_EN_SZ 1
+#define MB_DBG_RECORD_CNT_MSK 0x0000ffff
+#define MB_DBG_RECORD_CNT_I_MSK 0xffff0000
+#define MB_DBG_RECORD_CNT_SFT 0
+#define MB_DBG_RECORD_CNT_HI 15
+#define MB_DBG_RECORD_CNT_SZ 16
+#define MB_DBG_LENGTH_MSK 0xffff0000
+#define MB_DBG_LENGTH_I_MSK 0x0000ffff
+#define MB_DBG_LENGTH_SFT 16
+#define MB_DBG_LENGTH_HI 31
+#define MB_DBG_LENGTH_SZ 16
+#define MB_DBG_CFG_ADDR_MSK 0xffffffff
+#define MB_DBG_CFG_ADDR_I_MSK 0x00000000
+#define MB_DBG_CFG_ADDR_SFT 0
+#define MB_DBG_CFG_ADDR_HI 31
+#define MB_DBG_CFG_ADDR_SZ 32
+#define DBG_HWID0_WR_EN_MSK 0x00000001
+#define DBG_HWID0_WR_EN_I_MSK 0xfffffffe
+#define DBG_HWID0_WR_EN_SFT 0
+#define DBG_HWID0_WR_EN_HI 0
+#define DBG_HWID0_WR_EN_SZ 1
+#define DBG_HWID1_WR_EN_MSK 0x00000002
+#define DBG_HWID1_WR_EN_I_MSK 0xfffffffd
+#define DBG_HWID1_WR_EN_SFT 1
+#define DBG_HWID1_WR_EN_HI 1
+#define DBG_HWID1_WR_EN_SZ 1
+#define DBG_HWID2_WR_EN_MSK 0x00000004
+#define DBG_HWID2_WR_EN_I_MSK 0xfffffffb
+#define DBG_HWID2_WR_EN_SFT 2
+#define DBG_HWID2_WR_EN_HI 2
+#define DBG_HWID2_WR_EN_SZ 1
+#define DBG_HWID3_WR_EN_MSK 0x00000008
+#define DBG_HWID3_WR_EN_I_MSK 0xfffffff7
+#define DBG_HWID3_WR_EN_SFT 3
+#define DBG_HWID3_WR_EN_HI 3
+#define DBG_HWID3_WR_EN_SZ 1
+#define DBG_HWID4_WR_EN_MSK 0x00000010
+#define DBG_HWID4_WR_EN_I_MSK 0xffffffef
+#define DBG_HWID4_WR_EN_SFT 4
+#define DBG_HWID4_WR_EN_HI 4
+#define DBG_HWID4_WR_EN_SZ 1
+#define DBG_HWID5_WR_EN_MSK 0x00000020
+#define DBG_HWID5_WR_EN_I_MSK 0xffffffdf
+#define DBG_HWID5_WR_EN_SFT 5
+#define DBG_HWID5_WR_EN_HI 5
+#define DBG_HWID5_WR_EN_SZ 1
+#define DBG_HWID6_WR_EN_MSK 0x00000040
+#define DBG_HWID6_WR_EN_I_MSK 0xffffffbf
+#define DBG_HWID6_WR_EN_SFT 6
+#define DBG_HWID6_WR_EN_HI 6
+#define DBG_HWID6_WR_EN_SZ 1
+#define DBG_HWID7_WR_EN_MSK 0x00000080
+#define DBG_HWID7_WR_EN_I_MSK 0xffffff7f
+#define DBG_HWID7_WR_EN_SFT 7
+#define DBG_HWID7_WR_EN_HI 7
+#define DBG_HWID7_WR_EN_SZ 1
+#define DBG_HWID8_WR_EN_MSK 0x00000100
+#define DBG_HWID8_WR_EN_I_MSK 0xfffffeff
+#define DBG_HWID8_WR_EN_SFT 8
+#define DBG_HWID8_WR_EN_HI 8
+#define DBG_HWID8_WR_EN_SZ 1
+#define DBG_HWID9_WR_EN_MSK 0x00000200
+#define DBG_HWID9_WR_EN_I_MSK 0xfffffdff
+#define DBG_HWID9_WR_EN_SFT 9
+#define DBG_HWID9_WR_EN_HI 9
+#define DBG_HWID9_WR_EN_SZ 1
+#define DBG_HWID10_WR_EN_MSK 0x00000400
+#define DBG_HWID10_WR_EN_I_MSK 0xfffffbff
+#define DBG_HWID10_WR_EN_SFT 10
+#define DBG_HWID10_WR_EN_HI 10
+#define DBG_HWID10_WR_EN_SZ 1
+#define DBG_HWID11_WR_EN_MSK 0x00000800
+#define DBG_HWID11_WR_EN_I_MSK 0xfffff7ff
+#define DBG_HWID11_WR_EN_SFT 11
+#define DBG_HWID11_WR_EN_HI 11
+#define DBG_HWID11_WR_EN_SZ 1
+#define DBG_HWID12_WR_EN_MSK 0x00001000
+#define DBG_HWID12_WR_EN_I_MSK 0xffffefff
+#define DBG_HWID12_WR_EN_SFT 12
+#define DBG_HWID12_WR_EN_HI 12
+#define DBG_HWID12_WR_EN_SZ 1
+#define DBG_HWID13_WR_EN_MSK 0x00002000
+#define DBG_HWID13_WR_EN_I_MSK 0xffffdfff
+#define DBG_HWID13_WR_EN_SFT 13
+#define DBG_HWID13_WR_EN_HI 13
+#define DBG_HWID13_WR_EN_SZ 1
+#define DBG_HWID14_WR_EN_MSK 0x00004000
+#define DBG_HWID14_WR_EN_I_MSK 0xffffbfff
+#define DBG_HWID14_WR_EN_SFT 14
+#define DBG_HWID14_WR_EN_HI 14
+#define DBG_HWID14_WR_EN_SZ 1
+#define DBG_HWID15_WR_EN_MSK 0x00008000
+#define DBG_HWID15_WR_EN_I_MSK 0xffff7fff
+#define DBG_HWID15_WR_EN_SFT 15
+#define DBG_HWID15_WR_EN_HI 15
+#define DBG_HWID15_WR_EN_SZ 1
+#define DBG_HWID0_RD_EN_MSK 0x00010000
+#define DBG_HWID0_RD_EN_I_MSK 0xfffeffff
+#define DBG_HWID0_RD_EN_SFT 16
+#define DBG_HWID0_RD_EN_HI 16
+#define DBG_HWID0_RD_EN_SZ 1
+#define DBG_HWID1_RD_EN_MSK 0x00020000
+#define DBG_HWID1_RD_EN_I_MSK 0xfffdffff
+#define DBG_HWID1_RD_EN_SFT 17
+#define DBG_HWID1_RD_EN_HI 17
+#define DBG_HWID1_RD_EN_SZ 1
+#define DBG_HWID2_RD_EN_MSK 0x00040000
+#define DBG_HWID2_RD_EN_I_MSK 0xfffbffff
+#define DBG_HWID2_RD_EN_SFT 18
+#define DBG_HWID2_RD_EN_HI 18
+#define DBG_HWID2_RD_EN_SZ 1
+#define DBG_HWID3_RD_EN_MSK 0x00080000
+#define DBG_HWID3_RD_EN_I_MSK 0xfff7ffff
+#define DBG_HWID3_RD_EN_SFT 19
+#define DBG_HWID3_RD_EN_HI 19
+#define DBG_HWID3_RD_EN_SZ 1
+#define DBG_HWID4_RD_EN_MSK 0x00100000
+#define DBG_HWID4_RD_EN_I_MSK 0xffefffff
+#define DBG_HWID4_RD_EN_SFT 20
+#define DBG_HWID4_RD_EN_HI 20
+#define DBG_HWID4_RD_EN_SZ 1
+#define DBG_HWID5_RD_EN_MSK 0x00200000
+#define DBG_HWID5_RD_EN_I_MSK 0xffdfffff
+#define DBG_HWID5_RD_EN_SFT 21
+#define DBG_HWID5_RD_EN_HI 21
+#define DBG_HWID5_RD_EN_SZ 1
+#define DBG_HWID6_RD_EN_MSK 0x00400000
+#define DBG_HWID6_RD_EN_I_MSK 0xffbfffff
+#define DBG_HWID6_RD_EN_SFT 22
+#define DBG_HWID6_RD_EN_HI 22
+#define DBG_HWID6_RD_EN_SZ 1
+#define DBG_HWID7_RD_EN_MSK 0x00800000
+#define DBG_HWID7_RD_EN_I_MSK 0xff7fffff
+#define DBG_HWID7_RD_EN_SFT 23
+#define DBG_HWID7_RD_EN_HI 23
+#define DBG_HWID7_RD_EN_SZ 1
+#define DBG_HWID8_RD_EN_MSK 0x01000000
+#define DBG_HWID8_RD_EN_I_MSK 0xfeffffff
+#define DBG_HWID8_RD_EN_SFT 24
+#define DBG_HWID8_RD_EN_HI 24
+#define DBG_HWID8_RD_EN_SZ 1
+#define DBG_HWID9_RD_EN_MSK 0x02000000
+#define DBG_HWID9_RD_EN_I_MSK 0xfdffffff
+#define DBG_HWID9_RD_EN_SFT 25
+#define DBG_HWID9_RD_EN_HI 25
+#define DBG_HWID9_RD_EN_SZ 1
+#define DBG_HWID10_RD_EN_MSK 0x04000000
+#define DBG_HWID10_RD_EN_I_MSK 0xfbffffff
+#define DBG_HWID10_RD_EN_SFT 26
+#define DBG_HWID10_RD_EN_HI 26
+#define DBG_HWID10_RD_EN_SZ 1
+#define DBG_HWID11_RD_EN_MSK 0x08000000
+#define DBG_HWID11_RD_EN_I_MSK 0xf7ffffff
+#define DBG_HWID11_RD_EN_SFT 27
+#define DBG_HWID11_RD_EN_HI 27
+#define DBG_HWID11_RD_EN_SZ 1
+#define DBG_HWID12_RD_EN_MSK 0x10000000
+#define DBG_HWID12_RD_EN_I_MSK 0xefffffff
+#define DBG_HWID12_RD_EN_SFT 28
+#define DBG_HWID12_RD_EN_HI 28
+#define DBG_HWID12_RD_EN_SZ 1
+#define DBG_HWID13_RD_EN_MSK 0x20000000
+#define DBG_HWID13_RD_EN_I_MSK 0xdfffffff
+#define DBG_HWID13_RD_EN_SFT 29
+#define DBG_HWID13_RD_EN_HI 29
+#define DBG_HWID13_RD_EN_SZ 1
+#define DBG_HWID14_RD_EN_MSK 0x40000000
+#define DBG_HWID14_RD_EN_I_MSK 0xbfffffff
+#define DBG_HWID14_RD_EN_SFT 30
+#define DBG_HWID14_RD_EN_HI 30
+#define DBG_HWID14_RD_EN_SZ 1
+#define DBG_HWID15_RD_EN_MSK 0x80000000
+#define DBG_HWID15_RD_EN_I_MSK 0x7fffffff
+#define DBG_HWID15_RD_EN_SFT 31
+#define DBG_HWID15_RD_EN_HI 31
+#define DBG_HWID15_RD_EN_SZ 1
+#define MB_OUT_QUEUE_EN_MSK 0x00000002
+#define MB_OUT_QUEUE_EN_I_MSK 0xfffffffd
+#define MB_OUT_QUEUE_EN_SFT 1
+#define MB_OUT_QUEUE_EN_HI 1
+#define MB_OUT_QUEUE_EN_SZ 1
+#define CH0_QUEUE_FLUSH_MSK 0x00000001
+#define CH0_QUEUE_FLUSH_I_MSK 0xfffffffe
+#define CH0_QUEUE_FLUSH_SFT 0
+#define CH0_QUEUE_FLUSH_HI 0
+#define CH0_QUEUE_FLUSH_SZ 1
+#define CH1_QUEUE_FLUSH_MSK 0x00000002
+#define CH1_QUEUE_FLUSH_I_MSK 0xfffffffd
+#define CH1_QUEUE_FLUSH_SFT 1
+#define CH1_QUEUE_FLUSH_HI 1
+#define CH1_QUEUE_FLUSH_SZ 1
+#define CH2_QUEUE_FLUSH_MSK 0x00000004
+#define CH2_QUEUE_FLUSH_I_MSK 0xfffffffb
+#define CH2_QUEUE_FLUSH_SFT 2
+#define CH2_QUEUE_FLUSH_HI 2
+#define CH2_QUEUE_FLUSH_SZ 1
+#define CH3_QUEUE_FLUSH_MSK 0x00000008
+#define CH3_QUEUE_FLUSH_I_MSK 0xfffffff7
+#define CH3_QUEUE_FLUSH_SFT 3
+#define CH3_QUEUE_FLUSH_HI 3
+#define CH3_QUEUE_FLUSH_SZ 1
+#define CH4_QUEUE_FLUSH_MSK 0x00000010
+#define CH4_QUEUE_FLUSH_I_MSK 0xffffffef
+#define CH4_QUEUE_FLUSH_SFT 4
+#define CH4_QUEUE_FLUSH_HI 4
+#define CH4_QUEUE_FLUSH_SZ 1
+#define CH5_QUEUE_FLUSH_MSK 0x00000020
+#define CH5_QUEUE_FLUSH_I_MSK 0xffffffdf
+#define CH5_QUEUE_FLUSH_SFT 5
+#define CH5_QUEUE_FLUSH_HI 5
+#define CH5_QUEUE_FLUSH_SZ 1
+#define CH6_QUEUE_FLUSH_MSK 0x00000040
+#define CH6_QUEUE_FLUSH_I_MSK 0xffffffbf
+#define CH6_QUEUE_FLUSH_SFT 6
+#define CH6_QUEUE_FLUSH_HI 6
+#define CH6_QUEUE_FLUSH_SZ 1
+#define CH7_QUEUE_FLUSH_MSK 0x00000080
+#define CH7_QUEUE_FLUSH_I_MSK 0xffffff7f
+#define CH7_QUEUE_FLUSH_SFT 7
+#define CH7_QUEUE_FLUSH_HI 7
+#define CH7_QUEUE_FLUSH_SZ 1
+#define CH8_QUEUE_FLUSH_MSK 0x00000100
+#define CH8_QUEUE_FLUSH_I_MSK 0xfffffeff
+#define CH8_QUEUE_FLUSH_SFT 8
+#define CH8_QUEUE_FLUSH_HI 8
+#define CH8_QUEUE_FLUSH_SZ 1
+#define CH9_QUEUE_FLUSH_MSK 0x00000200
+#define CH9_QUEUE_FLUSH_I_MSK 0xfffffdff
+#define CH9_QUEUE_FLUSH_SFT 9
+#define CH9_QUEUE_FLUSH_HI 9
+#define CH9_QUEUE_FLUSH_SZ 1
+#define CH10_QUEUE_FLUSH_MSK 0x00000400
+#define CH10_QUEUE_FLUSH_I_MSK 0xfffffbff
+#define CH10_QUEUE_FLUSH_SFT 10
+#define CH10_QUEUE_FLUSH_HI 10
+#define CH10_QUEUE_FLUSH_SZ 1
+#define CH11_QUEUE_FLUSH_MSK 0x00000800
+#define CH11_QUEUE_FLUSH_I_MSK 0xfffff7ff
+#define CH11_QUEUE_FLUSH_SFT 11
+#define CH11_QUEUE_FLUSH_HI 11
+#define CH11_QUEUE_FLUSH_SZ 1
+#define CH12_QUEUE_FLUSH_MSK 0x00001000
+#define CH12_QUEUE_FLUSH_I_MSK 0xffffefff
+#define CH12_QUEUE_FLUSH_SFT 12
+#define CH12_QUEUE_FLUSH_HI 12
+#define CH12_QUEUE_FLUSH_SZ 1
+#define CH13_QUEUE_FLUSH_MSK 0x00002000
+#define CH13_QUEUE_FLUSH_I_MSK 0xffffdfff
+#define CH13_QUEUE_FLUSH_SFT 13
+#define CH13_QUEUE_FLUSH_HI 13
+#define CH13_QUEUE_FLUSH_SZ 1
+#define CH14_QUEUE_FLUSH_MSK 0x00004000
+#define CH14_QUEUE_FLUSH_I_MSK 0xffffbfff
+#define CH14_QUEUE_FLUSH_SFT 14
+#define CH14_QUEUE_FLUSH_HI 14
+#define CH14_QUEUE_FLUSH_SZ 1
+#define CH15_QUEUE_FLUSH_MSK 0x00008000
+#define CH15_QUEUE_FLUSH_I_MSK 0xffff7fff
+#define CH15_QUEUE_FLUSH_SFT 15
+#define CH15_QUEUE_FLUSH_HI 15
+#define CH15_QUEUE_FLUSH_SZ 1
+#define FFO0_CNT_MSK 0x0000001f
+#define FFO0_CNT_I_MSK 0xffffffe0
+#define FFO0_CNT_SFT 0
+#define FFO0_CNT_HI 4
+#define FFO0_CNT_SZ 5
+#define FFO1_CNT_MSK 0x000003e0
+#define FFO1_CNT_I_MSK 0xfffffc1f
+#define FFO1_CNT_SFT 5
+#define FFO1_CNT_HI 9
+#define FFO1_CNT_SZ 5
+#define FFO2_CNT_MSK 0x00000c00
+#define FFO2_CNT_I_MSK 0xfffff3ff
+#define FFO2_CNT_SFT 10
+#define FFO2_CNT_HI 11
+#define FFO2_CNT_SZ 2
+#define FFO3_CNT_MSK 0x000f8000
+#define FFO3_CNT_I_MSK 0xfff07fff
+#define FFO3_CNT_SFT 15
+#define FFO3_CNT_HI 19
+#define FFO3_CNT_SZ 5
+#define FFO4_CNT_MSK 0x00300000
+#define FFO4_CNT_I_MSK 0xffcfffff
+#define FFO4_CNT_SFT 20
+#define FFO4_CNT_HI 21
+#define FFO4_CNT_SZ 2
+#define FFO5_CNT_MSK 0x0e000000
+#define FFO5_CNT_I_MSK 0xf1ffffff
+#define FFO5_CNT_SFT 25
+#define FFO5_CNT_HI 27
+#define FFO5_CNT_SZ 3
+#define FFO6_CNT_MSK 0x0000000f
+#define FFO6_CNT_I_MSK 0xfffffff0
+#define FFO6_CNT_SFT 0
+#define FFO6_CNT_HI 3
+#define FFO6_CNT_SZ 4
+#define FFO7_CNT_MSK 0x000003e0
+#define FFO7_CNT_I_MSK 0xfffffc1f
+#define FFO7_CNT_SFT 5
+#define FFO7_CNT_HI 9
+#define FFO7_CNT_SZ 5
+#define FFO8_CNT_MSK 0x00007c00
+#define FFO8_CNT_I_MSK 0xffff83ff
+#define FFO8_CNT_SFT 10
+#define FFO8_CNT_HI 14
+#define FFO8_CNT_SZ 5
+#define FFO9_CNT_MSK 0x000f8000
+#define FFO9_CNT_I_MSK 0xfff07fff
+#define FFO9_CNT_SFT 15
+#define FFO9_CNT_HI 19
+#define FFO9_CNT_SZ 5
+#define FFO10_CNT_MSK 0x00f00000
+#define FFO10_CNT_I_MSK 0xff0fffff
+#define FFO10_CNT_SFT 20
+#define FFO10_CNT_HI 23
+#define FFO10_CNT_SZ 4
+#define FFO11_CNT_MSK 0x3e000000
+#define FFO11_CNT_I_MSK 0xc1ffffff
+#define FFO11_CNT_SFT 25
+#define FFO11_CNT_HI 29
+#define FFO11_CNT_SZ 5
+#define FFO12_CNT_MSK 0x00000007
+#define FFO12_CNT_I_MSK 0xfffffff8
+#define FFO12_CNT_SFT 0
+#define FFO12_CNT_HI 2
+#define FFO12_CNT_SZ 3
+#define FFO13_CNT_MSK 0x00000060
+#define FFO13_CNT_I_MSK 0xffffff9f
+#define FFO13_CNT_SFT 5
+#define FFO13_CNT_HI 6
+#define FFO13_CNT_SZ 2
+#define FFO14_CNT_MSK 0x00000c00
+#define FFO14_CNT_I_MSK 0xfffff3ff
+#define FFO14_CNT_SFT 10
+#define FFO14_CNT_HI 11
+#define FFO14_CNT_SZ 2
+#define FFO15_CNT_MSK 0x001f8000
+#define FFO15_CNT_I_MSK 0xffe07fff
+#define FFO15_CNT_SFT 15
+#define FFO15_CNT_HI 20
+#define FFO15_CNT_SZ 6
+#define CH0_FFO_FULL_MSK 0x00000001
+#define CH0_FFO_FULL_I_MSK 0xfffffffe
+#define CH0_FFO_FULL_SFT 0
+#define CH0_FFO_FULL_HI 0
+#define CH0_FFO_FULL_SZ 1
+#define CH1_FFO_FULL_MSK 0x00000002
+#define CH1_FFO_FULL_I_MSK 0xfffffffd
+#define CH1_FFO_FULL_SFT 1
+#define CH1_FFO_FULL_HI 1
+#define CH1_FFO_FULL_SZ 1
+#define CH2_FFO_FULL_MSK 0x00000004
+#define CH2_FFO_FULL_I_MSK 0xfffffffb
+#define CH2_FFO_FULL_SFT 2
+#define CH2_FFO_FULL_HI 2
+#define CH2_FFO_FULL_SZ 1
+#define CH3_FFO_FULL_MSK 0x00000008
+#define CH3_FFO_FULL_I_MSK 0xfffffff7
+#define CH3_FFO_FULL_SFT 3
+#define CH3_FFO_FULL_HI 3
+#define CH3_FFO_FULL_SZ 1
+#define CH4_FFO_FULL_MSK 0x00000010
+#define CH4_FFO_FULL_I_MSK 0xffffffef
+#define CH4_FFO_FULL_SFT 4
+#define CH4_FFO_FULL_HI 4
+#define CH4_FFO_FULL_SZ 1
+#define CH5_FFO_FULL_MSK 0x00000020
+#define CH5_FFO_FULL_I_MSK 0xffffffdf
+#define CH5_FFO_FULL_SFT 5
+#define CH5_FFO_FULL_HI 5
+#define CH5_FFO_FULL_SZ 1
+#define CH6_FFO_FULL_MSK 0x00000040
+#define CH6_FFO_FULL_I_MSK 0xffffffbf
+#define CH6_FFO_FULL_SFT 6
+#define CH6_FFO_FULL_HI 6
+#define CH6_FFO_FULL_SZ 1
+#define CH7_FFO_FULL_MSK 0x00000080
+#define CH7_FFO_FULL_I_MSK 0xffffff7f
+#define CH7_FFO_FULL_SFT 7
+#define CH7_FFO_FULL_HI 7
+#define CH7_FFO_FULL_SZ 1
+#define CH8_FFO_FULL_MSK 0x00000100
+#define CH8_FFO_FULL_I_MSK 0xfffffeff
+#define CH8_FFO_FULL_SFT 8
+#define CH8_FFO_FULL_HI 8
+#define CH8_FFO_FULL_SZ 1
+#define CH9_FFO_FULL_MSK 0x00000200
+#define CH9_FFO_FULL_I_MSK 0xfffffdff
+#define CH9_FFO_FULL_SFT 9
+#define CH9_FFO_FULL_HI 9
+#define CH9_FFO_FULL_SZ 1
+#define CH10_FFO_FULL_MSK 0x00000400
+#define CH10_FFO_FULL_I_MSK 0xfffffbff
+#define CH10_FFO_FULL_SFT 10
+#define CH10_FFO_FULL_HI 10
+#define CH10_FFO_FULL_SZ 1
+#define CH11_FFO_FULL_MSK 0x00000800
+#define CH11_FFO_FULL_I_MSK 0xfffff7ff
+#define CH11_FFO_FULL_SFT 11
+#define CH11_FFO_FULL_HI 11
+#define CH11_FFO_FULL_SZ 1
+#define CH12_FFO_FULL_MSK 0x00001000
+#define CH12_FFO_FULL_I_MSK 0xffffefff
+#define CH12_FFO_FULL_SFT 12
+#define CH12_FFO_FULL_HI 12
+#define CH12_FFO_FULL_SZ 1
+#define CH13_FFO_FULL_MSK 0x00002000
+#define CH13_FFO_FULL_I_MSK 0xffffdfff
+#define CH13_FFO_FULL_SFT 13
+#define CH13_FFO_FULL_HI 13
+#define CH13_FFO_FULL_SZ 1
+#define CH14_FFO_FULL_MSK 0x00004000
+#define CH14_FFO_FULL_I_MSK 0xffffbfff
+#define CH14_FFO_FULL_SFT 14
+#define CH14_FFO_FULL_HI 14
+#define CH14_FFO_FULL_SZ 1
+#define CH15_FFO_FULL_MSK 0x00008000
+#define CH15_FFO_FULL_I_MSK 0xffff7fff
+#define CH15_FFO_FULL_SFT 15
+#define CH15_FFO_FULL_HI 15
+#define CH15_FFO_FULL_SZ 1
+#define CH0_LOWTHOLD_INT_MSK 0x00000001
+#define CH0_LOWTHOLD_INT_I_MSK 0xfffffffe
+#define CH0_LOWTHOLD_INT_SFT 0
+#define CH0_LOWTHOLD_INT_HI 0
+#define CH0_LOWTHOLD_INT_SZ 1
+#define CH1_LOWTHOLD_INT_MSK 0x00000002
+#define CH1_LOWTHOLD_INT_I_MSK 0xfffffffd
+#define CH1_LOWTHOLD_INT_SFT 1
+#define CH1_LOWTHOLD_INT_HI 1
+#define CH1_LOWTHOLD_INT_SZ 1
+#define CH2_LOWTHOLD_INT_MSK 0x00000004
+#define CH2_LOWTHOLD_INT_I_MSK 0xfffffffb
+#define CH2_LOWTHOLD_INT_SFT 2
+#define CH2_LOWTHOLD_INT_HI 2
+#define CH2_LOWTHOLD_INT_SZ 1
+#define CH3_LOWTHOLD_INT_MSK 0x00000008
+#define CH3_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define CH3_LOWTHOLD_INT_SFT 3
+#define CH3_LOWTHOLD_INT_HI 3
+#define CH3_LOWTHOLD_INT_SZ 1
+#define CH4_LOWTHOLD_INT_MSK 0x00000010
+#define CH4_LOWTHOLD_INT_I_MSK 0xffffffef
+#define CH4_LOWTHOLD_INT_SFT 4
+#define CH4_LOWTHOLD_INT_HI 4
+#define CH4_LOWTHOLD_INT_SZ 1
+#define CH5_LOWTHOLD_INT_MSK 0x00000020
+#define CH5_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define CH5_LOWTHOLD_INT_SFT 5
+#define CH5_LOWTHOLD_INT_HI 5
+#define CH5_LOWTHOLD_INT_SZ 1
+#define CH6_LOWTHOLD_INT_MSK 0x00000040
+#define CH6_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define CH6_LOWTHOLD_INT_SFT 6
+#define CH6_LOWTHOLD_INT_HI 6
+#define CH6_LOWTHOLD_INT_SZ 1
+#define CH7_LOWTHOLD_INT_MSK 0x00000080
+#define CH7_LOWTHOLD_INT_I_MSK 0xffffff7f
+#define CH7_LOWTHOLD_INT_SFT 7
+#define CH7_LOWTHOLD_INT_HI 7
+#define CH7_LOWTHOLD_INT_SZ 1
+#define CH8_LOWTHOLD_INT_MSK 0x00000100
+#define CH8_LOWTHOLD_INT_I_MSK 0xfffffeff
+#define CH8_LOWTHOLD_INT_SFT 8
+#define CH8_LOWTHOLD_INT_HI 8
+#define CH8_LOWTHOLD_INT_SZ 1
+#define CH9_LOWTHOLD_INT_MSK 0x00000200
+#define CH9_LOWTHOLD_INT_I_MSK 0xfffffdff
+#define CH9_LOWTHOLD_INT_SFT 9
+#define CH9_LOWTHOLD_INT_HI 9
+#define CH9_LOWTHOLD_INT_SZ 1
+#define CH10_LOWTHOLD_INT_MSK 0x00000400
+#define CH10_LOWTHOLD_INT_I_MSK 0xfffffbff
+#define CH10_LOWTHOLD_INT_SFT 10
+#define CH10_LOWTHOLD_INT_HI 10
+#define CH10_LOWTHOLD_INT_SZ 1
+#define CH11_LOWTHOLD_INT_MSK 0x00000800
+#define CH11_LOWTHOLD_INT_I_MSK 0xfffff7ff
+#define CH11_LOWTHOLD_INT_SFT 11
+#define CH11_LOWTHOLD_INT_HI 11
+#define CH11_LOWTHOLD_INT_SZ 1
+#define CH12_LOWTHOLD_INT_MSK 0x00001000
+#define CH12_LOWTHOLD_INT_I_MSK 0xffffefff
+#define CH12_LOWTHOLD_INT_SFT 12
+#define CH12_LOWTHOLD_INT_HI 12
+#define CH12_LOWTHOLD_INT_SZ 1
+#define CH13_LOWTHOLD_INT_MSK 0x00002000
+#define CH13_LOWTHOLD_INT_I_MSK 0xffffdfff
+#define CH13_LOWTHOLD_INT_SFT 13
+#define CH13_LOWTHOLD_INT_HI 13
+#define CH13_LOWTHOLD_INT_SZ 1
+#define CH14_LOWTHOLD_INT_MSK 0x00004000
+#define CH14_LOWTHOLD_INT_I_MSK 0xffffbfff
+#define CH14_LOWTHOLD_INT_SFT 14
+#define CH14_LOWTHOLD_INT_HI 14
+#define CH14_LOWTHOLD_INT_SZ 1
+#define CH15_LOWTHOLD_INT_MSK 0x00008000
+#define CH15_LOWTHOLD_INT_I_MSK 0xffff7fff
+#define CH15_LOWTHOLD_INT_SFT 15
+#define CH15_LOWTHOLD_INT_HI 15
+#define CH15_LOWTHOLD_INT_SZ 1
+#define MB_LOW_THOLD_EN_MSK 0x80000000
+#define MB_LOW_THOLD_EN_I_MSK 0x7fffffff
+#define MB_LOW_THOLD_EN_SFT 31
+#define MB_LOW_THOLD_EN_HI 31
+#define MB_LOW_THOLD_EN_SZ 1
+#define CH0_LOWTHOLD_MSK 0x0000001f
+#define CH0_LOWTHOLD_I_MSK 0xffffffe0
+#define CH0_LOWTHOLD_SFT 0
+#define CH0_LOWTHOLD_HI 4
+#define CH0_LOWTHOLD_SZ 5
+#define CH1_LOWTHOLD_MSK 0x00001f00
+#define CH1_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH1_LOWTHOLD_SFT 8
+#define CH1_LOWTHOLD_HI 12
+#define CH1_LOWTHOLD_SZ 5
+#define CH2_LOWTHOLD_MSK 0x001f0000
+#define CH2_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH2_LOWTHOLD_SFT 16
+#define CH2_LOWTHOLD_HI 20
+#define CH2_LOWTHOLD_SZ 5
+#define CH3_LOWTHOLD_MSK 0x1f000000
+#define CH3_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH3_LOWTHOLD_SFT 24
+#define CH3_LOWTHOLD_HI 28
+#define CH3_LOWTHOLD_SZ 5
+#define CH4_LOWTHOLD_MSK 0x0000001f
+#define CH4_LOWTHOLD_I_MSK 0xffffffe0
+#define CH4_LOWTHOLD_SFT 0
+#define CH4_LOWTHOLD_HI 4
+#define CH4_LOWTHOLD_SZ 5
+#define CH5_LOWTHOLD_MSK 0x00001f00
+#define CH5_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH5_LOWTHOLD_SFT 8
+#define CH5_LOWTHOLD_HI 12
+#define CH5_LOWTHOLD_SZ 5
+#define CH6_LOWTHOLD_MSK 0x001f0000
+#define CH6_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH6_LOWTHOLD_SFT 16
+#define CH6_LOWTHOLD_HI 20
+#define CH6_LOWTHOLD_SZ 5
+#define CH7_LOWTHOLD_MSK 0x1f000000
+#define CH7_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH7_LOWTHOLD_SFT 24
+#define CH7_LOWTHOLD_HI 28
+#define CH7_LOWTHOLD_SZ 5
+#define CH8_LOWTHOLD_MSK 0x0000001f
+#define CH8_LOWTHOLD_I_MSK 0xffffffe0
+#define CH8_LOWTHOLD_SFT 0
+#define CH8_LOWTHOLD_HI 4
+#define CH8_LOWTHOLD_SZ 5
+#define CH9_LOWTHOLD_MSK 0x00001f00
+#define CH9_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH9_LOWTHOLD_SFT 8
+#define CH9_LOWTHOLD_HI 12
+#define CH9_LOWTHOLD_SZ 5
+#define CH10_LOWTHOLD_MSK 0x001f0000
+#define CH10_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH10_LOWTHOLD_SFT 16
+#define CH10_LOWTHOLD_HI 20
+#define CH10_LOWTHOLD_SZ 5
+#define CH11_LOWTHOLD_MSK 0x1f000000
+#define CH11_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH11_LOWTHOLD_SFT 24
+#define CH11_LOWTHOLD_HI 28
+#define CH11_LOWTHOLD_SZ 5
+#define CH12_LOWTHOLD_MSK 0x0000001f
+#define CH12_LOWTHOLD_I_MSK 0xffffffe0
+#define CH12_LOWTHOLD_SFT 0
+#define CH12_LOWTHOLD_HI 4
+#define CH12_LOWTHOLD_SZ 5
+#define CH13_LOWTHOLD_MSK 0x00001f00
+#define CH13_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH13_LOWTHOLD_SFT 8
+#define CH13_LOWTHOLD_HI 12
+#define CH13_LOWTHOLD_SZ 5
+#define CH14_LOWTHOLD_MSK 0x001f0000
+#define CH14_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH14_LOWTHOLD_SFT 16
+#define CH14_LOWTHOLD_HI 20
+#define CH14_LOWTHOLD_SZ 5
+#define CH15_LOWTHOLD_MSK 0x1f000000
+#define CH15_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH15_LOWTHOLD_SFT 24
+#define CH15_LOWTHOLD_HI 28
+#define CH15_LOWTHOLD_SZ 5
+#define TRASH_TIMEOUT_EN_MSK 0x00000001
+#define TRASH_TIMEOUT_EN_I_MSK 0xfffffffe
+#define TRASH_TIMEOUT_EN_SFT 0
+#define TRASH_TIMEOUT_EN_HI 0
+#define TRASH_TIMEOUT_EN_SZ 1
+#define TRASH_CAN_INT_MSK 0x00000002
+#define TRASH_CAN_INT_I_MSK 0xfffffffd
+#define TRASH_CAN_INT_SFT 1
+#define TRASH_CAN_INT_HI 1
+#define TRASH_CAN_INT_SZ 1
+#define TRASH_INT_ID_MSK 0x000007f0
+#define TRASH_INT_ID_I_MSK 0xfffff80f
+#define TRASH_INT_ID_SFT 4
+#define TRASH_INT_ID_HI 10
+#define TRASH_INT_ID_SZ 7
+#define TRASH_TIMEOUT_MSK 0x03ff0000
+#define TRASH_TIMEOUT_I_MSK 0xfc00ffff
+#define TRASH_TIMEOUT_SFT 16
+#define TRASH_TIMEOUT_HI 25
+#define TRASH_TIMEOUT_SZ 10
+#define CH0_WRFF_FLUSH_MSK 0x00000001
+#define CH0_WRFF_FLUSH_I_MSK 0xfffffffe
+#define CH0_WRFF_FLUSH_SFT 0
+#define CH0_WRFF_FLUSH_HI 0
+#define CH0_WRFF_FLUSH_SZ 1
+#define CH1_WRFF_FLUSH_MSK 0x00000002
+#define CH1_WRFF_FLUSH_I_MSK 0xfffffffd
+#define CH1_WRFF_FLUSH_SFT 1
+#define CH1_WRFF_FLUSH_HI 1
+#define CH1_WRFF_FLUSH_SZ 1
+#define CH2_WRFF_FLUSH_MSK 0x00000004
+#define CH2_WRFF_FLUSH_I_MSK 0xfffffffb
+#define CH2_WRFF_FLUSH_SFT 2
+#define CH2_WRFF_FLUSH_HI 2
+#define CH2_WRFF_FLUSH_SZ 1
+#define CH3_WRFF_FLUSH_MSK 0x00000008
+#define CH3_WRFF_FLUSH_I_MSK 0xfffffff7
+#define CH3_WRFF_FLUSH_SFT 3
+#define CH3_WRFF_FLUSH_HI 3
+#define CH3_WRFF_FLUSH_SZ 1
+#define CH4_WRFF_FLUSH_MSK 0x00000010
+#define CH4_WRFF_FLUSH_I_MSK 0xffffffef
+#define CH4_WRFF_FLUSH_SFT 4
+#define CH4_WRFF_FLUSH_HI 4
+#define CH4_WRFF_FLUSH_SZ 1
+#define CH5_WRFF_FLUSH_MSK 0x00000020
+#define CH5_WRFF_FLUSH_I_MSK 0xffffffdf
+#define CH5_WRFF_FLUSH_SFT 5
+#define CH5_WRFF_FLUSH_HI 5
+#define CH5_WRFF_FLUSH_SZ 1
+#define CH6_WRFF_FLUSH_MSK 0x00000040
+#define CH6_WRFF_FLUSH_I_MSK 0xffffffbf
+#define CH6_WRFF_FLUSH_SFT 6
+#define CH6_WRFF_FLUSH_HI 6
+#define CH6_WRFF_FLUSH_SZ 1
+#define CH7_WRFF_FLUSH_MSK 0x00000080
+#define CH7_WRFF_FLUSH_I_MSK 0xffffff7f
+#define CH7_WRFF_FLUSH_SFT 7
+#define CH7_WRFF_FLUSH_HI 7
+#define CH7_WRFF_FLUSH_SZ 1
+#define CH8_WRFF_FLUSH_MSK 0x00000100
+#define CH8_WRFF_FLUSH_I_MSK 0xfffffeff
+#define CH8_WRFF_FLUSH_SFT 8
+#define CH8_WRFF_FLUSH_HI 8
+#define CH8_WRFF_FLUSH_SZ 1
+#define CH9_WRFF_FLUSH_MSK 0x00000200
+#define CH9_WRFF_FLUSH_I_MSK 0xfffffdff
+#define CH9_WRFF_FLUSH_SFT 9
+#define CH9_WRFF_FLUSH_HI 9
+#define CH9_WRFF_FLUSH_SZ 1
+#define CH10_WRFF_FLUSH_MSK 0x00000400
+#define CH10_WRFF_FLUSH_I_MSK 0xfffffbff
+#define CH10_WRFF_FLUSH_SFT 10
+#define CH10_WRFF_FLUSH_HI 10
+#define CH10_WRFF_FLUSH_SZ 1
+#define CH11_WRFF_FLUSH_MSK 0x00000800
+#define CH11_WRFF_FLUSH_I_MSK 0xfffff7ff
+#define CH11_WRFF_FLUSH_SFT 11
+#define CH11_WRFF_FLUSH_HI 11
+#define CH11_WRFF_FLUSH_SZ 1
+#define CH12_WRFF_FLUSH_MSK 0x00001000
+#define CH12_WRFF_FLUSH_I_MSK 0xffffefff
+#define CH12_WRFF_FLUSH_SFT 12
+#define CH12_WRFF_FLUSH_HI 12
+#define CH12_WRFF_FLUSH_SZ 1
+#define CH13_WRFF_FLUSH_MSK 0x00002000
+#define CH13_WRFF_FLUSH_I_MSK 0xffffdfff
+#define CH13_WRFF_FLUSH_SFT 13
+#define CH13_WRFF_FLUSH_HI 13
+#define CH13_WRFF_FLUSH_SZ 1
+#define CH14_WRFF_FLUSH_MSK 0x00004000
+#define CH14_WRFF_FLUSH_I_MSK 0xffffbfff
+#define CH14_WRFF_FLUSH_SFT 14
+#define CH14_WRFF_FLUSH_HI 14
+#define CH14_WRFF_FLUSH_SZ 1
+#define CPU_ID_TB2_MSK 0xffffffff
+#define CPU_ID_TB2_I_MSK 0x00000000
+#define CPU_ID_TB2_SFT 0
+#define CPU_ID_TB2_HI 31
+#define CPU_ID_TB2_SZ 32
+#define CPU_ID_TB3_MSK 0xffffffff
+#define CPU_ID_TB3_I_MSK 0x00000000
+#define CPU_ID_TB3_SFT 0
+#define CPU_ID_TB3_HI 31
+#define CPU_ID_TB3_SZ 32
+#define IQ_LOG_EN_MSK 0x00000001
+#define IQ_LOG_EN_I_MSK 0xfffffffe
+#define IQ_LOG_EN_SFT 0
+#define IQ_LOG_EN_HI 0
+#define IQ_LOG_EN_SZ 1
+#define IQ_LOG_STOP_MODE_MSK 0x00000001
+#define IQ_LOG_STOP_MODE_I_MSK 0xfffffffe
+#define IQ_LOG_STOP_MODE_SFT 0
+#define IQ_LOG_STOP_MODE_HI 0
+#define IQ_LOG_STOP_MODE_SZ 1
+#define GPIO_STOP_EN_MSK 0x00000010
+#define GPIO_STOP_EN_I_MSK 0xffffffef
+#define GPIO_STOP_EN_SFT 4
+#define GPIO_STOP_EN_HI 4
+#define GPIO_STOP_EN_SZ 1
+#define GPIO_STOP_POL_MSK 0x00000020
+#define GPIO_STOP_POL_I_MSK 0xffffffdf
+#define GPIO_STOP_POL_SFT 5
+#define GPIO_STOP_POL_HI 5
+#define GPIO_STOP_POL_SZ 1
+#define IQ_LOG_TIMER_MSK 0xffff0000
+#define IQ_LOG_TIMER_I_MSK 0x0000ffff
+#define IQ_LOG_TIMER_SFT 16
+#define IQ_LOG_TIMER_HI 31
+#define IQ_LOG_TIMER_SZ 16
+#define IQ_LOG_LEN_MSK 0x0000ffff
+#define IQ_LOG_LEN_I_MSK 0xffff0000
+#define IQ_LOG_LEN_SFT 0
+#define IQ_LOG_LEN_HI 15
+#define IQ_LOG_LEN_SZ 16
+#define IQ_LOG_TAIL_ADR_MSK 0x0000ffff
+#define IQ_LOG_TAIL_ADR_I_MSK 0xffff0000
+#define IQ_LOG_TAIL_ADR_SFT 0
+#define IQ_LOG_TAIL_ADR_HI 15
+#define IQ_LOG_TAIL_ADR_SZ 16
+#define ALC_LENG_MSK 0x0003ffff
+#define ALC_LENG_I_MSK 0xfffc0000
+#define ALC_LENG_SFT 0
+#define ALC_LENG_HI 17
+#define ALC_LENG_SZ 18
+#define CH0_DYN_PRI_MSK 0x00300000
+#define CH0_DYN_PRI_I_MSK 0xffcfffff
+#define CH0_DYN_PRI_SFT 20
+#define CH0_DYN_PRI_HI 21
+#define CH0_DYN_PRI_SZ 2
+#define MCU_PKTID_MSK 0xffffffff
+#define MCU_PKTID_I_MSK 0x00000000
+#define MCU_PKTID_SFT 0
+#define MCU_PKTID_HI 31
+#define MCU_PKTID_SZ 32
+#define CH0_STA_PRI_MSK 0x00000003
+#define CH0_STA_PRI_I_MSK 0xfffffffc
+#define CH0_STA_PRI_SFT 0
+#define CH0_STA_PRI_HI 1
+#define CH0_STA_PRI_SZ 2
+#define CH1_STA_PRI_MSK 0x00000030
+#define CH1_STA_PRI_I_MSK 0xffffffcf
+#define CH1_STA_PRI_SFT 4
+#define CH1_STA_PRI_HI 5
+#define CH1_STA_PRI_SZ 2
+#define CH2_STA_PRI_MSK 0x00000300
+#define CH2_STA_PRI_I_MSK 0xfffffcff
+#define CH2_STA_PRI_SFT 8
+#define CH2_STA_PRI_HI 9
+#define CH2_STA_PRI_SZ 2
+#define CH3_STA_PRI_MSK 0x00003000
+#define CH3_STA_PRI_I_MSK 0xffffcfff
+#define CH3_STA_PRI_SFT 12
+#define CH3_STA_PRI_HI 13
+#define CH3_STA_PRI_SZ 2
+#define ID_TB0_MSK 0xffffffff
+#define ID_TB0_I_MSK 0x00000000
+#define ID_TB0_SFT 0
+#define ID_TB0_HI 31
+#define ID_TB0_SZ 32
+#define ID_TB1_MSK 0xffffffff
+#define ID_TB1_I_MSK 0x00000000
+#define ID_TB1_SFT 0
+#define ID_TB1_HI 31
+#define ID_TB1_SZ 32
+#define ID_MNG_HALT_MSK 0x00000010
+#define ID_MNG_HALT_I_MSK 0xffffffef
+#define ID_MNG_HALT_SFT 4
+#define ID_MNG_HALT_HI 4
+#define ID_MNG_HALT_SZ 1
+#define ID_MNG_ERR_HALT_EN_MSK 0x00000020
+#define ID_MNG_ERR_HALT_EN_I_MSK 0xffffffdf
+#define ID_MNG_ERR_HALT_EN_SFT 5
+#define ID_MNG_ERR_HALT_EN_HI 5
+#define ID_MNG_ERR_HALT_EN_SZ 1
+#define ID_EXCEPT_FLG_CLR_MSK 0x00000040
+#define ID_EXCEPT_FLG_CLR_I_MSK 0xffffffbf
+#define ID_EXCEPT_FLG_CLR_SFT 6
+#define ID_EXCEPT_FLG_CLR_HI 6
+#define ID_EXCEPT_FLG_CLR_SZ 1
+#define ID_EXCEPT_FLG_MSK 0x00000080
+#define ID_EXCEPT_FLG_I_MSK 0xffffff7f
+#define ID_EXCEPT_FLG_SFT 7
+#define ID_EXCEPT_FLG_HI 7
+#define ID_EXCEPT_FLG_SZ 1
+#define ID_FULL_MSK 0x00000001
+#define ID_FULL_I_MSK 0xfffffffe
+#define ID_FULL_SFT 0
+#define ID_FULL_HI 0
+#define ID_FULL_SZ 1
+#define ID_MNG_BUSY_MSK 0x00000002
+#define ID_MNG_BUSY_I_MSK 0xfffffffd
+#define ID_MNG_BUSY_SFT 1
+#define ID_MNG_BUSY_HI 1
+#define ID_MNG_BUSY_SZ 1
+#define REQ_LOCK_MSK 0x00000004
+#define REQ_LOCK_I_MSK 0xfffffffb
+#define REQ_LOCK_SFT 2
+#define REQ_LOCK_HI 2
+#define REQ_LOCK_SZ 1
+#define CH0_REQ_LOCK_MSK 0x00000010
+#define CH0_REQ_LOCK_I_MSK 0xffffffef
+#define CH0_REQ_LOCK_SFT 4
+#define CH0_REQ_LOCK_HI 4
+#define CH0_REQ_LOCK_SZ 1
+#define CH1_REQ_LOCK_MSK 0x00000020
+#define CH1_REQ_LOCK_I_MSK 0xffffffdf
+#define CH1_REQ_LOCK_SFT 5
+#define CH1_REQ_LOCK_HI 5
+#define CH1_REQ_LOCK_SZ 1
+#define CH2_REQ_LOCK_MSK 0x00000040
+#define CH2_REQ_LOCK_I_MSK 0xffffffbf
+#define CH2_REQ_LOCK_SFT 6
+#define CH2_REQ_LOCK_HI 6
+#define CH2_REQ_LOCK_SZ 1
+#define CH3_REQ_LOCK_MSK 0x00000080
+#define CH3_REQ_LOCK_I_MSK 0xffffff7f
+#define CH3_REQ_LOCK_SFT 7
+#define CH3_REQ_LOCK_HI 7
+#define CH3_REQ_LOCK_SZ 1
+#define REQ_LOCK_INT_EN_MSK 0x00000100
+#define REQ_LOCK_INT_EN_I_MSK 0xfffffeff
+#define REQ_LOCK_INT_EN_SFT 8
+#define REQ_LOCK_INT_EN_HI 8
+#define REQ_LOCK_INT_EN_SZ 1
+#define REQ_LOCK_INT_MSK 0x00000200
+#define REQ_LOCK_INT_I_MSK 0xfffffdff
+#define REQ_LOCK_INT_SFT 9
+#define REQ_LOCK_INT_HI 9
+#define REQ_LOCK_INT_SZ 1
+#define MCU_ALC_READY_MSK 0x00000001
+#define MCU_ALC_READY_I_MSK 0xfffffffe
+#define MCU_ALC_READY_SFT 0
+#define MCU_ALC_READY_HI 0
+#define MCU_ALC_READY_SZ 1
+#define ALC_FAIL_MSK 0x00000002
+#define ALC_FAIL_I_MSK 0xfffffffd
+#define ALC_FAIL_SFT 1
+#define ALC_FAIL_HI 1
+#define ALC_FAIL_SZ 1
+#define ALC_BUSY_MSK 0x00000004
+#define ALC_BUSY_I_MSK 0xfffffffb
+#define ALC_BUSY_SFT 2
+#define ALC_BUSY_HI 2
+#define ALC_BUSY_SZ 1
+#define CH0_NVLD_MSK 0x00000010
+#define CH0_NVLD_I_MSK 0xffffffef
+#define CH0_NVLD_SFT 4
+#define CH0_NVLD_HI 4
+#define CH0_NVLD_SZ 1
+#define CH1_NVLD_MSK 0x00000020
+#define CH1_NVLD_I_MSK 0xffffffdf
+#define CH1_NVLD_SFT 5
+#define CH1_NVLD_HI 5
+#define CH1_NVLD_SZ 1
+#define CH2_NVLD_MSK 0x00000040
+#define CH2_NVLD_I_MSK 0xffffffbf
+#define CH2_NVLD_SFT 6
+#define CH2_NVLD_HI 6
+#define CH2_NVLD_SZ 1
+#define CH3_NVLD_MSK 0x00000080
+#define CH3_NVLD_I_MSK 0xffffff7f
+#define CH3_NVLD_SFT 7
+#define CH3_NVLD_HI 7
+#define CH3_NVLD_SZ 1
+#define ALC_INT_ID_MSK 0x00007f00
+#define ALC_INT_ID_I_MSK 0xffff80ff
+#define ALC_INT_ID_SFT 8
+#define ALC_INT_ID_HI 14
+#define ALC_INT_ID_SZ 7
+#define ALC_TIMEOUT_MSK 0x03ff0000
+#define ALC_TIMEOUT_I_MSK 0xfc00ffff
+#define ALC_TIMEOUT_SFT 16
+#define ALC_TIMEOUT_HI 25
+#define ALC_TIMEOUT_SZ 10
+#define ALC_TIMEOUT_INT_EN_MSK 0x40000000
+#define ALC_TIMEOUT_INT_EN_I_MSK 0xbfffffff
+#define ALC_TIMEOUT_INT_EN_SFT 30
+#define ALC_TIMEOUT_INT_EN_HI 30
+#define ALC_TIMEOUT_INT_EN_SZ 1
+#define ALC_TIMEOUT_INT_MSK 0x80000000
+#define ALC_TIMEOUT_INT_I_MSK 0x7fffffff
+#define ALC_TIMEOUT_INT_SFT 31
+#define ALC_TIMEOUT_INT_HI 31
+#define ALC_TIMEOUT_INT_SZ 1
+#define TX_ID_COUNT_MSK 0x000000ff
+#define TX_ID_COUNT_I_MSK 0xffffff00
+#define TX_ID_COUNT_SFT 0
+#define TX_ID_COUNT_HI 7
+#define TX_ID_COUNT_SZ 8
+#define RX_ID_COUNT_MSK 0x0000ff00
+#define RX_ID_COUNT_I_MSK 0xffff00ff
+#define RX_ID_COUNT_SFT 8
+#define RX_ID_COUNT_HI 15
+#define RX_ID_COUNT_SZ 8
+#define TX_ID_THOLD_MSK 0x000000ff
+#define TX_ID_THOLD_I_MSK 0xffffff00
+#define TX_ID_THOLD_SFT 0
+#define TX_ID_THOLD_HI 7
+#define TX_ID_THOLD_SZ 8
+#define RX_ID_THOLD_MSK 0x0000ff00
+#define RX_ID_THOLD_I_MSK 0xffff00ff
+#define RX_ID_THOLD_SFT 8
+#define RX_ID_THOLD_HI 15
+#define RX_ID_THOLD_SZ 8
+#define ID_THOLD_RX_INT_MSK 0x00010000
+#define ID_THOLD_RX_INT_I_MSK 0xfffeffff
+#define ID_THOLD_RX_INT_SFT 16
+#define ID_THOLD_RX_INT_HI 16
+#define ID_THOLD_RX_INT_SZ 1
+#define RX_INT_CH_MSK 0x000e0000
+#define RX_INT_CH_I_MSK 0xfff1ffff
+#define RX_INT_CH_SFT 17
+#define RX_INT_CH_HI 19
+#define RX_INT_CH_SZ 3
+#define ID_THOLD_TX_INT_MSK 0x00100000
+#define ID_THOLD_TX_INT_I_MSK 0xffefffff
+#define ID_THOLD_TX_INT_SFT 20
+#define ID_THOLD_TX_INT_HI 20
+#define ID_THOLD_TX_INT_SZ 1
+#define TX_INT_CH_MSK 0x00e00000
+#define TX_INT_CH_I_MSK 0xff1fffff
+#define TX_INT_CH_SFT 21
+#define TX_INT_CH_HI 23
+#define TX_INT_CH_SZ 3
+#define ID_THOLD_INT_EN_MSK 0x01000000
+#define ID_THOLD_INT_EN_I_MSK 0xfeffffff
+#define ID_THOLD_INT_EN_SFT 24
+#define ID_THOLD_INT_EN_HI 24
+#define ID_THOLD_INT_EN_SZ 1
+#define TX_ID_TB0_MSK 0xffffffff
+#define TX_ID_TB0_I_MSK 0x00000000
+#define TX_ID_TB0_SFT 0
+#define TX_ID_TB0_HI 31
+#define TX_ID_TB0_SZ 32
+#define TX_ID_TB1_MSK 0xffffffff
+#define TX_ID_TB1_I_MSK 0x00000000
+#define TX_ID_TB1_SFT 0
+#define TX_ID_TB1_HI 31
+#define TX_ID_TB1_SZ 32
+#define RX_ID_TB0_MSK 0xffffffff
+#define RX_ID_TB0_I_MSK 0x00000000
+#define RX_ID_TB0_SFT 0
+#define RX_ID_TB0_HI 31
+#define RX_ID_TB0_SZ 32
+#define RX_ID_TB1_MSK 0xffffffff
+#define RX_ID_TB1_I_MSK 0x00000000
+#define RX_ID_TB1_SFT 0
+#define RX_ID_TB1_HI 31
+#define RX_ID_TB1_SZ 32
+#define DOUBLE_RLS_INT_EN_MSK 0x00000001
+#define DOUBLE_RLS_INT_EN_I_MSK 0xfffffffe
+#define DOUBLE_RLS_INT_EN_SFT 0
+#define DOUBLE_RLS_INT_EN_HI 0
+#define DOUBLE_RLS_INT_EN_SZ 1
+#define ID_DOUBLE_RLS_INT_MSK 0x00000002
+#define ID_DOUBLE_RLS_INT_I_MSK 0xfffffffd
+#define ID_DOUBLE_RLS_INT_SFT 1
+#define ID_DOUBLE_RLS_INT_HI 1
+#define ID_DOUBLE_RLS_INT_SZ 1
+#define DOUBLE_RLS_ID_MSK 0x00007f00
+#define DOUBLE_RLS_ID_I_MSK 0xffff80ff
+#define DOUBLE_RLS_ID_SFT 8
+#define DOUBLE_RLS_ID_HI 14
+#define DOUBLE_RLS_ID_SZ 7
+#define ID_LEN_THOLD_INT_EN_MSK 0x00000001
+#define ID_LEN_THOLD_INT_EN_I_MSK 0xfffffffe
+#define ID_LEN_THOLD_INT_EN_SFT 0
+#define ID_LEN_THOLD_INT_EN_HI 0
+#define ID_LEN_THOLD_INT_EN_SZ 1
+#define ALL_ID_LEN_THOLD_INT_MSK 0x00000002
+#define ALL_ID_LEN_THOLD_INT_I_MSK 0xfffffffd
+#define ALL_ID_LEN_THOLD_INT_SFT 1
+#define ALL_ID_LEN_THOLD_INT_HI 1
+#define ALL_ID_LEN_THOLD_INT_SZ 1
+#define TX_ID_LEN_THOLD_INT_MSK 0x00000004
+#define TX_ID_LEN_THOLD_INT_I_MSK 0xfffffffb
+#define TX_ID_LEN_THOLD_INT_SFT 2
+#define TX_ID_LEN_THOLD_INT_HI 2
+#define TX_ID_LEN_THOLD_INT_SZ 1
+#define RX_ID_LEN_THOLD_INT_MSK 0x00000008
+#define RX_ID_LEN_THOLD_INT_I_MSK 0xfffffff7
+#define RX_ID_LEN_THOLD_INT_SFT 3
+#define RX_ID_LEN_THOLD_INT_HI 3
+#define RX_ID_LEN_THOLD_INT_SZ 1
+#define ID_TX_LEN_THOLD_MSK 0x00001ff0
+#define ID_TX_LEN_THOLD_I_MSK 0xffffe00f
+#define ID_TX_LEN_THOLD_SFT 4
+#define ID_TX_LEN_THOLD_HI 12
+#define ID_TX_LEN_THOLD_SZ 9
+#define ID_RX_LEN_THOLD_MSK 0x003fe000
+#define ID_RX_LEN_THOLD_I_MSK 0xffc01fff
+#define ID_RX_LEN_THOLD_SFT 13
+#define ID_RX_LEN_THOLD_HI 21
+#define ID_RX_LEN_THOLD_SZ 9
+#define ID_LEN_THOLD_MSK 0x7fc00000
+#define ID_LEN_THOLD_I_MSK 0x803fffff
+#define ID_LEN_THOLD_SFT 22
+#define ID_LEN_THOLD_HI 30
+#define ID_LEN_THOLD_SZ 9
+#define ALL_ID_ALC_LEN_MSK 0x000001ff
+#define ALL_ID_ALC_LEN_I_MSK 0xfffffe00
+#define ALL_ID_ALC_LEN_SFT 0
+#define ALL_ID_ALC_LEN_HI 8
+#define ALL_ID_ALC_LEN_SZ 9
+#define TX_ID_ALC_LEN_MSK 0x0003fe00
+#define TX_ID_ALC_LEN_I_MSK 0xfffc01ff
+#define TX_ID_ALC_LEN_SFT 9
+#define TX_ID_ALC_LEN_HI 17
+#define TX_ID_ALC_LEN_SZ 9
+#define RX_ID_ALC_LEN_MSK 0x07fc0000
+#define RX_ID_ALC_LEN_I_MSK 0xf803ffff
+#define RX_ID_ALC_LEN_SFT 18
+#define RX_ID_ALC_LEN_HI 26
+#define RX_ID_ALC_LEN_SZ 9
+#define CH_ARB_EN_MSK 0x00000001
+#define CH_ARB_EN_I_MSK 0xfffffffe
+#define CH_ARB_EN_SFT 0
+#define CH_ARB_EN_HI 0
+#define CH_ARB_EN_SZ 1
+#define CH_PRI1_MSK 0x00000030
+#define CH_PRI1_I_MSK 0xffffffcf
+#define CH_PRI1_SFT 4
+#define CH_PRI1_HI 5
+#define CH_PRI1_SZ 2
+#define CH_PRI2_MSK 0x00000300
+#define CH_PRI2_I_MSK 0xfffffcff
+#define CH_PRI2_SFT 8
+#define CH_PRI2_HI 9
+#define CH_PRI2_SZ 2
+#define CH_PRI3_MSK 0x00003000
+#define CH_PRI3_I_MSK 0xffffcfff
+#define CH_PRI3_SFT 12
+#define CH_PRI3_HI 13
+#define CH_PRI3_SZ 2
+#define CH_PRI4_MSK 0x00030000
+#define CH_PRI4_I_MSK 0xfffcffff
+#define CH_PRI4_SFT 16
+#define CH_PRI4_HI 17
+#define CH_PRI4_SZ 2
+#define TX_ID_REMAIN_MSK 0x0000007f
+#define TX_ID_REMAIN_I_MSK 0xffffff80
+#define TX_ID_REMAIN_SFT 0
+#define TX_ID_REMAIN_HI 6
+#define TX_ID_REMAIN_SZ 7
+#define TX_PAGE_REMAIN_MSK 0x0001ff00
+#define TX_PAGE_REMAIN_I_MSK 0xfffe00ff
+#define TX_PAGE_REMAIN_SFT 8
+#define TX_PAGE_REMAIN_HI 16
+#define TX_PAGE_REMAIN_SZ 9
+#define ID_PAGE_MAX_SIZE_MSK 0x000001ff
+#define ID_PAGE_MAX_SIZE_I_MSK 0xfffffe00
+#define ID_PAGE_MAX_SIZE_SFT 0
+#define ID_PAGE_MAX_SIZE_HI 8
+#define ID_PAGE_MAX_SIZE_SZ 9
+#define TX_PAGE_LIMIT_MSK 0x000001ff
+#define TX_PAGE_LIMIT_I_MSK 0xfffffe00
+#define TX_PAGE_LIMIT_SFT 0
+#define TX_PAGE_LIMIT_HI 8
+#define TX_PAGE_LIMIT_SZ 9
+#define TX_COUNT_LIMIT_MSK 0x00ff0000
+#define TX_COUNT_LIMIT_I_MSK 0xff00ffff
+#define TX_COUNT_LIMIT_SFT 16
+#define TX_COUNT_LIMIT_HI 23
+#define TX_COUNT_LIMIT_SZ 8
+#define TX_LIMIT_INT_MSK 0x40000000
+#define TX_LIMIT_INT_I_MSK 0xbfffffff
+#define TX_LIMIT_INT_SFT 30
+#define TX_LIMIT_INT_HI 30
+#define TX_LIMIT_INT_SZ 1
+#define TX_LIMIT_INT_EN_MSK 0x80000000
+#define TX_LIMIT_INT_EN_I_MSK 0x7fffffff
+#define TX_LIMIT_INT_EN_SFT 31
+#define TX_LIMIT_INT_EN_HI 31
+#define TX_LIMIT_INT_EN_SZ 1
+#define TX_PAGE_USE_7_0_MSK 0x000000ff
+#define TX_PAGE_USE_7_0_I_MSK 0xffffff00
+#define TX_PAGE_USE_7_0_SFT 0
+#define TX_PAGE_USE_7_0_HI 7
+#define TX_PAGE_USE_7_0_SZ 8
+#define TX_ID_USE_5_0_MSK 0x00003f00
+#define TX_ID_USE_5_0_I_MSK 0xffffc0ff
+#define TX_ID_USE_5_0_SFT 8
+#define TX_ID_USE_5_0_HI 13
+#define TX_ID_USE_5_0_SZ 6
+#define EDCA0_FFO_CNT_MSK 0x0003c000
+#define EDCA0_FFO_CNT_I_MSK 0xfffc3fff
+#define EDCA0_FFO_CNT_SFT 14
+#define EDCA0_FFO_CNT_HI 17
+#define EDCA0_FFO_CNT_SZ 4
+#define EDCA1_FFO_CNT_3_0_MSK 0x003c0000
+#define EDCA1_FFO_CNT_3_0_I_MSK 0xffc3ffff
+#define EDCA1_FFO_CNT_3_0_SFT 18
+#define EDCA1_FFO_CNT_3_0_HI 21
+#define EDCA1_FFO_CNT_3_0_SZ 4
+#define EDCA2_FFO_CNT_MSK 0x07c00000
+#define EDCA2_FFO_CNT_I_MSK 0xf83fffff
+#define EDCA2_FFO_CNT_SFT 22
+#define EDCA2_FFO_CNT_HI 26
+#define EDCA2_FFO_CNT_SZ 5
+#define EDCA3_FFO_CNT_MSK 0xf8000000
+#define EDCA3_FFO_CNT_I_MSK 0x07ffffff
+#define EDCA3_FFO_CNT_SFT 27
+#define EDCA3_FFO_CNT_HI 31
+#define EDCA3_FFO_CNT_SZ 5
+#define ID_TB2_MSK 0xffffffff
+#define ID_TB2_I_MSK 0x00000000
+#define ID_TB2_SFT 0
+#define ID_TB2_HI 31
+#define ID_TB2_SZ 32
+#define ID_TB3_MSK 0xffffffff
+#define ID_TB3_I_MSK 0x00000000
+#define ID_TB3_SFT 0
+#define ID_TB3_HI 31
+#define ID_TB3_SZ 32
+#define TX_ID_TB2_MSK 0xffffffff
+#define TX_ID_TB2_I_MSK 0x00000000
+#define TX_ID_TB2_SFT 0
+#define TX_ID_TB2_HI 31
+#define TX_ID_TB2_SZ 32
+#define TX_ID_TB3_MSK 0xffffffff
+#define TX_ID_TB3_I_MSK 0x00000000
+#define TX_ID_TB3_SFT 0
+#define TX_ID_TB3_HI 31
+#define TX_ID_TB3_SZ 32
+#define RX_ID_TB2_MSK 0xffffffff
+#define RX_ID_TB2_I_MSK 0x00000000
+#define RX_ID_TB2_SFT 0
+#define RX_ID_TB2_HI 31
+#define RX_ID_TB2_SZ 32
+#define RX_ID_TB3_MSK 0xffffffff
+#define RX_ID_TB3_I_MSK 0x00000000
+#define RX_ID_TB3_SFT 0
+#define RX_ID_TB3_HI 31
+#define RX_ID_TB3_SZ 32
+#define TX_PAGE_USE2_MSK 0x000001ff
+#define TX_PAGE_USE2_I_MSK 0xfffffe00
+#define TX_PAGE_USE2_SFT 0
+#define TX_PAGE_USE2_HI 8
+#define TX_PAGE_USE2_SZ 9
+#define TX_ID_USE2_MSK 0x0001fe00
+#define TX_ID_USE2_I_MSK 0xfffe01ff
+#define TX_ID_USE2_SFT 9
+#define TX_ID_USE2_HI 16
+#define TX_ID_USE2_SZ 8
+#define EDCA4_FFO_CNT_MSK 0x001e0000
+#define EDCA4_FFO_CNT_I_MSK 0xffe1ffff
+#define EDCA4_FFO_CNT_SFT 17
+#define EDCA4_FFO_CNT_HI 20
+#define EDCA4_FFO_CNT_SZ 4
+#define TX_PAGE_USE3_MSK 0x000001ff
+#define TX_PAGE_USE3_I_MSK 0xfffffe00
+#define TX_PAGE_USE3_SFT 0
+#define TX_PAGE_USE3_HI 8
+#define TX_PAGE_USE3_SZ 9
+#define TX_ID_USE3_MSK 0x0001fe00
+#define TX_ID_USE3_I_MSK 0xfffe01ff
+#define TX_ID_USE3_SFT 9
+#define TX_ID_USE3_HI 16
+#define TX_ID_USE3_SZ 8
+#define EDCA1_FFO_CNT2_MSK 0x03e00000
+#define EDCA1_FFO_CNT2_I_MSK 0xfc1fffff
+#define EDCA1_FFO_CNT2_SFT 21
+#define EDCA1_FFO_CNT2_HI 25
+#define EDCA1_FFO_CNT2_SZ 5
+#define EDCA4_FFO_CNT2_MSK 0x3c000000
+#define EDCA4_FFO_CNT2_I_MSK 0xc3ffffff
+#define EDCA4_FFO_CNT2_SFT 26
+#define EDCA4_FFO_CNT2_HI 29
+#define EDCA4_FFO_CNT2_SZ 4
+#define TX_PAGE_USE4_MSK 0x000001ff
+#define TX_PAGE_USE4_I_MSK 0xfffffe00
+#define TX_PAGE_USE4_SFT 0
+#define TX_PAGE_USE4_HI 8
+#define TX_PAGE_USE4_SZ 9
+#define TX_ID_USE4_MSK 0x0001fe00
+#define TX_ID_USE4_I_MSK 0xfffe01ff
+#define TX_ID_USE4_SFT 9
+#define TX_ID_USE4_HI 16
+#define TX_ID_USE4_SZ 8
+#define EDCA2_FFO_CNT2_MSK 0x003e0000
+#define EDCA2_FFO_CNT2_I_MSK 0xffc1ffff
+#define EDCA2_FFO_CNT2_SFT 17
+#define EDCA2_FFO_CNT2_HI 21
+#define EDCA2_FFO_CNT2_SZ 5
+#define EDCA3_FFO_CNT2_MSK 0x07c00000
+#define EDCA3_FFO_CNT2_I_MSK 0xf83fffff
+#define EDCA3_FFO_CNT2_SFT 22
+#define EDCA3_FFO_CNT2_HI 26
+#define EDCA3_FFO_CNT2_SZ 5
+#define TX_ID_IFO_LEN_MSK 0x000001ff
+#define TX_ID_IFO_LEN_I_MSK 0xfffffe00
+#define TX_ID_IFO_LEN_SFT 0
+#define TX_ID_IFO_LEN_HI 8
+#define TX_ID_IFO_LEN_SZ 9
+#define RX_ID_IFO_LEN_MSK 0x01ff0000
+#define RX_ID_IFO_LEN_I_MSK 0xfe00ffff
+#define RX_ID_IFO_LEN_SFT 16
+#define RX_ID_IFO_LEN_HI 24
+#define RX_ID_IFO_LEN_SZ 9
+#define MAX_ALL_ALC_ID_CNT_MSK 0x000000ff
+#define MAX_ALL_ALC_ID_CNT_I_MSK 0xffffff00
+#define MAX_ALL_ALC_ID_CNT_SFT 0
+#define MAX_ALL_ALC_ID_CNT_HI 7
+#define MAX_ALL_ALC_ID_CNT_SZ 8
+#define MAX_TX_ALC_ID_CNT_MSK 0x0000ff00
+#define MAX_TX_ALC_ID_CNT_I_MSK 0xffff00ff
+#define MAX_TX_ALC_ID_CNT_SFT 8
+#define MAX_TX_ALC_ID_CNT_HI 15
+#define MAX_TX_ALC_ID_CNT_SZ 8
+#define MAX_RX_ALC_ID_CNT_MSK 0x00ff0000
+#define MAX_RX_ALC_ID_CNT_I_MSK 0xff00ffff
+#define MAX_RX_ALC_ID_CNT_SFT 16
+#define MAX_RX_ALC_ID_CNT_HI 23
+#define MAX_RX_ALC_ID_CNT_SZ 8
+#define MAX_ALL_ID_ALC_LEN_MSK 0x000001ff
+#define MAX_ALL_ID_ALC_LEN_I_MSK 0xfffffe00
+#define MAX_ALL_ID_ALC_LEN_SFT 0
+#define MAX_ALL_ID_ALC_LEN_HI 8
+#define MAX_ALL_ID_ALC_LEN_SZ 9
+#define MAX_TX_ID_ALC_LEN_MSK 0x0003fe00
+#define MAX_TX_ID_ALC_LEN_I_MSK 0xfffc01ff
+#define MAX_TX_ID_ALC_LEN_SFT 9
+#define MAX_TX_ID_ALC_LEN_HI 17
+#define MAX_TX_ID_ALC_LEN_SZ 9
+#define MAX_RX_ID_ALC_LEN_MSK 0x07fc0000
+#define MAX_RX_ID_ALC_LEN_I_MSK 0xf803ffff
+#define MAX_RX_ID_ALC_LEN_SFT 18
+#define MAX_RX_ID_ALC_LEN_HI 26
+#define MAX_RX_ID_ALC_LEN_SZ 9
+#define RG_PMDLBK_MSK 0x00000001
+#define RG_PMDLBK_I_MSK 0xfffffffe
+#define RG_PMDLBK_SFT 0
+#define RG_PMDLBK_HI 0
+#define RG_PMDLBK_SZ 1
+#define RG_RDYACK_SEL_MSK 0x00000006
+#define RG_RDYACK_SEL_I_MSK 0xfffffff9
+#define RG_RDYACK_SEL_SFT 1
+#define RG_RDYACK_SEL_HI 2
+#define RG_RDYACK_SEL_SZ 2
+#define RG_ADEDGE_SEL_MSK 0x00000008
+#define RG_ADEDGE_SEL_I_MSK 0xfffffff7
+#define RG_ADEDGE_SEL_SFT 3
+#define RG_ADEDGE_SEL_HI 3
+#define RG_ADEDGE_SEL_SZ 1
+#define RG_SIGN_SWAP_MSK 0x00000010
+#define RG_SIGN_SWAP_I_MSK 0xffffffef
+#define RG_SIGN_SWAP_SFT 4
+#define RG_SIGN_SWAP_HI 4
+#define RG_SIGN_SWAP_SZ 1
+#define RG_IQ_SWAP_MSK 0x00000020
+#define RG_IQ_SWAP_I_MSK 0xffffffdf
+#define RG_IQ_SWAP_SFT 5
+#define RG_IQ_SWAP_HI 5
+#define RG_IQ_SWAP_SZ 1
+#define RG_Q_INV_MSK 0x00000040
+#define RG_Q_INV_I_MSK 0xffffffbf
+#define RG_Q_INV_SFT 6
+#define RG_Q_INV_HI 6
+#define RG_Q_INV_SZ 1
+#define RG_I_INV_MSK 0x00000080
+#define RG_I_INV_I_MSK 0xffffff7f
+#define RG_I_INV_SFT 7
+#define RG_I_INV_HI 7
+#define RG_I_INV_SZ 1
+#define RG_BYPASS_ACI_MSK 0x00000100
+#define RG_BYPASS_ACI_I_MSK 0xfffffeff
+#define RG_BYPASS_ACI_SFT 8
+#define RG_BYPASS_ACI_HI 8
+#define RG_BYPASS_ACI_SZ 1
+#define RG_LBK_ANA_PATH_MSK 0x00000200
+#define RG_LBK_ANA_PATH_I_MSK 0xfffffdff
+#define RG_LBK_ANA_PATH_SFT 9
+#define RG_LBK_ANA_PATH_HI 9
+#define RG_LBK_ANA_PATH_SZ 1
+#define RG_SPECTRUM_LEAKY_FACTOR_MSK 0x00000c00
+#define RG_SPECTRUM_LEAKY_FACTOR_I_MSK 0xfffff3ff
+#define RG_SPECTRUM_LEAKY_FACTOR_SFT 10
+#define RG_SPECTRUM_LEAKY_FACTOR_HI 11
+#define RG_SPECTRUM_LEAKY_FACTOR_SZ 2
+#define RG_SPECTRUM_BW_MSK 0x00003000
+#define RG_SPECTRUM_BW_I_MSK 0xffffcfff
+#define RG_SPECTRUM_BW_SFT 12
+#define RG_SPECTRUM_BW_HI 13
+#define RG_SPECTRUM_BW_SZ 2
+#define RG_SPECTRUM_FREQ_MANUAL_MSK 0x00004000
+#define RG_SPECTRUM_FREQ_MANUAL_I_MSK 0xffffbfff
+#define RG_SPECTRUM_FREQ_MANUAL_SFT 14
+#define RG_SPECTRUM_FREQ_MANUAL_HI 14
+#define RG_SPECTRUM_FREQ_MANUAL_SZ 1
+#define RG_SPECTRUM_EN_MSK 0x00008000
+#define RG_SPECTRUM_EN_I_MSK 0xffff7fff
+#define RG_SPECTRUM_EN_SFT 15
+#define RG_SPECTRUM_EN_HI 15
+#define RG_SPECTRUM_EN_SZ 1
+#define RG_TXPWRLVL_SET_MSK 0x00ff0000
+#define RG_TXPWRLVL_SET_I_MSK 0xff00ffff
+#define RG_TXPWRLVL_SET_SFT 16
+#define RG_TXPWRLVL_SET_HI 23
+#define RG_TXPWRLVL_SET_SZ 8
+#define RG_TXPWRLVL_SEL_MSK 0x01000000
+#define RG_TXPWRLVL_SEL_I_MSK 0xfeffffff
+#define RG_TXPWRLVL_SEL_SFT 24
+#define RG_TXPWRLVL_SEL_HI 24
+#define RG_TXPWRLVL_SEL_SZ 1
+#define RG_RF_BB_CLK_SEL_MSK 0x80000000
+#define RG_RF_BB_CLK_SEL_I_MSK 0x7fffffff
+#define RG_RF_BB_CLK_SEL_SFT 31
+#define RG_RF_BB_CLK_SEL_HI 31
+#define RG_RF_BB_CLK_SEL_SZ 1
+#define RG_PHY_MD_EN_MSK 0x00000001
+#define RG_PHY_MD_EN_I_MSK 0xfffffffe
+#define RG_PHY_MD_EN_SFT 0
+#define RG_PHY_MD_EN_HI 0
+#define RG_PHY_MD_EN_SZ 1
+#define RG_PHYRX_MD_EN_MSK 0x00000002
+#define RG_PHYRX_MD_EN_I_MSK 0xfffffffd
+#define RG_PHYRX_MD_EN_SFT 1
+#define RG_PHYRX_MD_EN_HI 1
+#define RG_PHYRX_MD_EN_SZ 1
+#define RG_PHYTX_MD_EN_MSK 0x00000004
+#define RG_PHYTX_MD_EN_I_MSK 0xfffffffb
+#define RG_PHYTX_MD_EN_SFT 2
+#define RG_PHYTX_MD_EN_HI 2
+#define RG_PHYTX_MD_EN_SZ 1
+#define RG_PHY11GN_MD_EN_MSK 0x00000008
+#define RG_PHY11GN_MD_EN_I_MSK 0xfffffff7
+#define RG_PHY11GN_MD_EN_SFT 3
+#define RG_PHY11GN_MD_EN_HI 3
+#define RG_PHY11GN_MD_EN_SZ 1
+#define RG_PHY11B_MD_EN_MSK 0x00000010
+#define RG_PHY11B_MD_EN_I_MSK 0xffffffef
+#define RG_PHY11B_MD_EN_SFT 4
+#define RG_PHY11B_MD_EN_HI 4
+#define RG_PHY11B_MD_EN_SZ 1
+#define RG_PHYRXFIFO_MD_EN_MSK 0x00000020
+#define RG_PHYRXFIFO_MD_EN_I_MSK 0xffffffdf
+#define RG_PHYRXFIFO_MD_EN_SFT 5
+#define RG_PHYRXFIFO_MD_EN_HI 5
+#define RG_PHYRXFIFO_MD_EN_SZ 1
+#define RG_PHYTXFIFO_MD_EN_MSK 0x00000040
+#define RG_PHYTXFIFO_MD_EN_I_MSK 0xffffffbf
+#define RG_PHYTXFIFO_MD_EN_SFT 6
+#define RG_PHYTXFIFO_MD_EN_HI 6
+#define RG_PHYTXFIFO_MD_EN_SZ 1
+#define RG_PHY11BGN_MD_EN_MSK 0x00000100
+#define RG_PHY11BGN_MD_EN_I_MSK 0xfffffeff
+#define RG_PHY11BGN_MD_EN_SFT 8
+#define RG_PHY11BGN_MD_EN_HI 8
+#define RG_PHY11BGN_MD_EN_SZ 1
+#define RG_FORCE_11GN_EN_MSK 0x00001000
+#define RG_FORCE_11GN_EN_I_MSK 0xffffefff
+#define RG_FORCE_11GN_EN_SFT 12
+#define RG_FORCE_11GN_EN_HI 12
+#define RG_FORCE_11GN_EN_SZ 1
+#define RG_FORCE_11B_EN_MSK 0x00002000
+#define RG_FORCE_11B_EN_I_MSK 0xffffdfff
+#define RG_FORCE_11B_EN_SFT 13
+#define RG_FORCE_11B_EN_HI 13
+#define RG_FORCE_11B_EN_SZ 1
+#define RG_FFT_MEM_CLK_EN_RX_MSK 0x00004000
+#define RG_FFT_MEM_CLK_EN_RX_I_MSK 0xffffbfff
+#define RG_FFT_MEM_CLK_EN_RX_SFT 14
+#define RG_FFT_MEM_CLK_EN_RX_HI 14
+#define RG_FFT_MEM_CLK_EN_RX_SZ 1
+#define RG_FFT_MEM_CLK_EN_TX_MSK 0x00008000
+#define RG_FFT_MEM_CLK_EN_TX_I_MSK 0xffff7fff
+#define RG_FFT_MEM_CLK_EN_TX_SFT 15
+#define RG_FFT_MEM_CLK_EN_TX_HI 15
+#define RG_FFT_MEM_CLK_EN_TX_SZ 1
+#define RG_PHY_IQ_TRIG_SEL_MSK 0x000f0000
+#define RG_PHY_IQ_TRIG_SEL_I_MSK 0xfff0ffff
+#define RG_PHY_IQ_TRIG_SEL_SFT 16
+#define RG_PHY_IQ_TRIG_SEL_HI 19
+#define RG_PHY_IQ_TRIG_SEL_SZ 4
+#define RG_SPECTRUM_FREQ_MSK 0x3ff00000
+#define RG_SPECTRUM_FREQ_I_MSK 0xc00fffff
+#define RG_SPECTRUM_FREQ_SFT 20
+#define RG_SPECTRUM_FREQ_HI 29
+#define RG_SPECTRUM_FREQ_SZ 10
+#define SVN_VERSION_MSK 0xffffffff
+#define SVN_VERSION_I_MSK 0x00000000
+#define SVN_VERSION_SFT 0
+#define SVN_VERSION_HI 31
+#define SVN_VERSION_SZ 32
+#define RG_LENGTH_MSK 0x0000ffff
+#define RG_LENGTH_I_MSK 0xffff0000
+#define RG_LENGTH_SFT 0
+#define RG_LENGTH_HI 15
+#define RG_LENGTH_SZ 16
+#define RG_PKT_MODE_MSK 0x00070000
+#define RG_PKT_MODE_I_MSK 0xfff8ffff
+#define RG_PKT_MODE_SFT 16
+#define RG_PKT_MODE_HI 18
+#define RG_PKT_MODE_SZ 3
+#define RG_CH_BW_MSK 0x00380000
+#define RG_CH_BW_I_MSK 0xffc7ffff
+#define RG_CH_BW_SFT 19
+#define RG_CH_BW_HI 21
+#define RG_CH_BW_SZ 3
+#define RG_PRM_MSK 0x00400000
+#define RG_PRM_I_MSK 0xffbfffff
+#define RG_PRM_SFT 22
+#define RG_PRM_HI 22
+#define RG_PRM_SZ 1
+#define RG_SHORTGI_MSK 0x00800000
+#define RG_SHORTGI_I_MSK 0xff7fffff
+#define RG_SHORTGI_SFT 23
+#define RG_SHORTGI_HI 23
+#define RG_SHORTGI_SZ 1
+#define RG_RATE_MSK 0x7f000000
+#define RG_RATE_I_MSK 0x80ffffff
+#define RG_RATE_SFT 24
+#define RG_RATE_HI 30
+#define RG_RATE_SZ 7
+#define RG_L_LENGTH_MSK 0x00000fff
+#define RG_L_LENGTH_I_MSK 0xfffff000
+#define RG_L_LENGTH_SFT 0
+#define RG_L_LENGTH_HI 11
+#define RG_L_LENGTH_SZ 12
+#define RG_L_RATE_MSK 0x00007000
+#define RG_L_RATE_I_MSK 0xffff8fff
+#define RG_L_RATE_SFT 12
+#define RG_L_RATE_HI 14
+#define RG_L_RATE_SZ 3
+#define RG_SERVICE_MSK 0xffff0000
+#define RG_SERVICE_I_MSK 0x0000ffff
+#define RG_SERVICE_SFT 16
+#define RG_SERVICE_HI 31
+#define RG_SERVICE_SZ 16
+#define RG_SMOOTHING_MSK 0x00000001
+#define RG_SMOOTHING_I_MSK 0xfffffffe
+#define RG_SMOOTHING_SFT 0
+#define RG_SMOOTHING_HI 0
+#define RG_SMOOTHING_SZ 1
+#define RG_NO_SOUND_MSK 0x00000002
+#define RG_NO_SOUND_I_MSK 0xfffffffd
+#define RG_NO_SOUND_SFT 1
+#define RG_NO_SOUND_HI 1
+#define RG_NO_SOUND_SZ 1
+#define RG_AGGREGATE_MSK 0x00000004
+#define RG_AGGREGATE_I_MSK 0xfffffffb
+#define RG_AGGREGATE_SFT 2
+#define RG_AGGREGATE_HI 2
+#define RG_AGGREGATE_SZ 1
+#define RG_STBC_MSK 0x00000018
+#define RG_STBC_I_MSK 0xffffffe7
+#define RG_STBC_SFT 3
+#define RG_STBC_HI 4
+#define RG_STBC_SZ 2
+#define RG_FEC_MSK 0x00000020
+#define RG_FEC_I_MSK 0xffffffdf
+#define RG_FEC_SFT 5
+#define RG_FEC_HI 5
+#define RG_FEC_SZ 1
+#define RG_N_ESS_MSK 0x000000c0
+#define RG_N_ESS_I_MSK 0xffffff3f
+#define RG_N_ESS_SFT 6
+#define RG_N_ESS_HI 7
+#define RG_N_ESS_SZ 2
+#define RG_TXPWRLVL_MSK 0x0000ff00
+#define RG_TXPWRLVL_I_MSK 0xffff00ff
+#define RG_TXPWRLVL_SFT 8
+#define RG_TXPWRLVL_HI 15
+#define RG_TXPWRLVL_SZ 8
+#define RG_TX_START_MSK 0x00000001
+#define RG_TX_START_I_MSK 0xfffffffe
+#define RG_TX_START_SFT 0
+#define RG_TX_START_HI 0
+#define RG_TX_START_SZ 1
+#define RG_IFS_TIME_MSK 0x000000fc
+#define RG_IFS_TIME_I_MSK 0xffffff03
+#define RG_IFS_TIME_SFT 2
+#define RG_IFS_TIME_HI 7
+#define RG_IFS_TIME_SZ 6
+#define RG_CONTINUOUS_DATA_MSK 0x00000100
+#define RG_CONTINUOUS_DATA_I_MSK 0xfffffeff
+#define RG_CONTINUOUS_DATA_SFT 8
+#define RG_CONTINUOUS_DATA_HI 8
+#define RG_CONTINUOUS_DATA_SZ 1
+#define RG_DATA_SEL_MSK 0x00000600
+#define RG_DATA_SEL_I_MSK 0xfffff9ff
+#define RG_DATA_SEL_SFT 9
+#define RG_DATA_SEL_HI 10
+#define RG_DATA_SEL_SZ 2
+#define RG_TX_D_MSK 0x00ff0000
+#define RG_TX_D_I_MSK 0xff00ffff
+#define RG_TX_D_SFT 16
+#define RG_TX_D_HI 23
+#define RG_TX_D_SZ 8
+#define RG_TX_CNT_TARGET_MSK 0xffffffff
+#define RG_TX_CNT_TARGET_I_MSK 0x00000000
+#define RG_TX_CNT_TARGET_SFT 0
+#define RG_TX_CNT_TARGET_HI 31
+#define RG_TX_CNT_TARGET_SZ 32
+#define RG_FFT_IFFT_MODE_MSK 0x000000c0
+#define RG_FFT_IFFT_MODE_I_MSK 0xffffff3f
+#define RG_FFT_IFFT_MODE_SFT 6
+#define RG_FFT_IFFT_MODE_HI 7
+#define RG_FFT_IFFT_MODE_SZ 2
+#define RG_DAC_DBG_MODE_MSK 0x00000100
+#define RG_DAC_DBG_MODE_I_MSK 0xfffffeff
+#define RG_DAC_DBG_MODE_SFT 8
+#define RG_DAC_DBG_MODE_HI 8
+#define RG_DAC_DBG_MODE_SZ 1
+#define RG_DAC_SGN_SWAP_MSK 0x00000200
+#define RG_DAC_SGN_SWAP_I_MSK 0xfffffdff
+#define RG_DAC_SGN_SWAP_SFT 9
+#define RG_DAC_SGN_SWAP_HI 9
+#define RG_DAC_SGN_SWAP_SZ 1
+#define RG_TXD_SEL_MSK 0x00000c00
+#define RG_TXD_SEL_I_MSK 0xfffff3ff
+#define RG_TXD_SEL_SFT 10
+#define RG_TXD_SEL_HI 11
+#define RG_TXD_SEL_SZ 2
+#define RG_UP8X_MSK 0x00ff0000
+#define RG_UP8X_I_MSK 0xff00ffff
+#define RG_UP8X_SFT 16
+#define RG_UP8X_HI 23
+#define RG_UP8X_SZ 8
+#define RG_IQ_DC_BYP_MSK 0x01000000
+#define RG_IQ_DC_BYP_I_MSK 0xfeffffff
+#define RG_IQ_DC_BYP_SFT 24
+#define RG_IQ_DC_BYP_HI 24
+#define RG_IQ_DC_BYP_SZ 1
+#define RG_IQ_DC_LEAKY_FACTOR_MSK 0x30000000
+#define RG_IQ_DC_LEAKY_FACTOR_I_MSK 0xcfffffff
+#define RG_IQ_DC_LEAKY_FACTOR_SFT 28
+#define RG_IQ_DC_LEAKY_FACTOR_HI 29
+#define RG_IQ_DC_LEAKY_FACTOR_SZ 2
+#define RG_DAC_DCEN_MSK 0x00000001
+#define RG_DAC_DCEN_I_MSK 0xfffffffe
+#define RG_DAC_DCEN_SFT 0
+#define RG_DAC_DCEN_HI 0
+#define RG_DAC_DCEN_SZ 1
+#define RG_DAC_DCQ_MSK 0x00003ff0
+#define RG_DAC_DCQ_I_MSK 0xffffc00f
+#define RG_DAC_DCQ_SFT 4
+#define RG_DAC_DCQ_HI 13
+#define RG_DAC_DCQ_SZ 10
+#define RG_DAC_DCI_MSK 0x03ff0000
+#define RG_DAC_DCI_I_MSK 0xfc00ffff
+#define RG_DAC_DCI_SFT 16
+#define RG_DAC_DCI_HI 25
+#define RG_DAC_DCI_SZ 10
+#define RG_PGA_REFDB_SAT_MSK 0x0000007f
+#define RG_PGA_REFDB_SAT_I_MSK 0xffffff80
+#define RG_PGA_REFDB_SAT_SFT 0
+#define RG_PGA_REFDB_SAT_HI 6
+#define RG_PGA_REFDB_SAT_SZ 7
+#define RG_PGA_REFDB_TOP_MSK 0x00007f00
+#define RG_PGA_REFDB_TOP_I_MSK 0xffff80ff
+#define RG_PGA_REFDB_TOP_SFT 8
+#define RG_PGA_REFDB_TOP_HI 14
+#define RG_PGA_REFDB_TOP_SZ 7
+#define RG_PGA_REF_UND_MSK 0x03ff0000
+#define RG_PGA_REF_UND_I_MSK 0xfc00ffff
+#define RG_PGA_REF_UND_SFT 16
+#define RG_PGA_REF_UND_HI 25
+#define RG_PGA_REF_UND_SZ 10
+#define RG_RF_REF_SAT_MSK 0xf0000000
+#define RG_RF_REF_SAT_I_MSK 0x0fffffff
+#define RG_RF_REF_SAT_SFT 28
+#define RG_RF_REF_SAT_HI 31
+#define RG_RF_REF_SAT_SZ 4
+#define RG_PGAGC_SET_MSK 0x0000000f
+#define RG_PGAGC_SET_I_MSK 0xfffffff0
+#define RG_PGAGC_SET_SFT 0
+#define RG_PGAGC_SET_HI 3
+#define RG_PGAGC_SET_SZ 4
+#define RG_PGAGC_OW_MSK 0x00000010
+#define RG_PGAGC_OW_I_MSK 0xffffffef
+#define RG_PGAGC_OW_SFT 4
+#define RG_PGAGC_OW_HI 4
+#define RG_PGAGC_OW_SZ 1
+#define RG_RFGC_SET_MSK 0x00000060
+#define RG_RFGC_SET_I_MSK 0xffffff9f
+#define RG_RFGC_SET_SFT 5
+#define RG_RFGC_SET_HI 6
+#define RG_RFGC_SET_SZ 2
+#define RG_RFGC_OW_MSK 0x00000080
+#define RG_RFGC_OW_I_MSK 0xffffff7f
+#define RG_RFGC_OW_SFT 7
+#define RG_RFGC_OW_HI 7
+#define RG_RFGC_OW_SZ 1
+#define RG_WAIT_T_RXAGC_MSK 0x00003f00
+#define RG_WAIT_T_RXAGC_I_MSK 0xffffc0ff
+#define RG_WAIT_T_RXAGC_SFT 8
+#define RG_WAIT_T_RXAGC_HI 13
+#define RG_WAIT_T_RXAGC_SZ 6
+#define RG_RXAGC_SET_MSK 0x00004000
+#define RG_RXAGC_SET_I_MSK 0xffffbfff
+#define RG_RXAGC_SET_SFT 14
+#define RG_RXAGC_SET_HI 14
+#define RG_RXAGC_SET_SZ 1
+#define RG_RXAGC_OW_MSK 0x00008000
+#define RG_RXAGC_OW_I_MSK 0xffff7fff
+#define RG_RXAGC_OW_SFT 15
+#define RG_RXAGC_OW_HI 15
+#define RG_RXAGC_OW_SZ 1
+#define RG_WAIT_T_FINAL_MSK 0x003f0000
+#define RG_WAIT_T_FINAL_I_MSK 0xffc0ffff
+#define RG_WAIT_T_FINAL_SFT 16
+#define RG_WAIT_T_FINAL_HI 21
+#define RG_WAIT_T_FINAL_SZ 6
+#define RG_WAIT_T_MSK 0x3f000000
+#define RG_WAIT_T_I_MSK 0xc0ffffff
+#define RG_WAIT_T_SFT 24
+#define RG_WAIT_T_HI 29
+#define RG_WAIT_T_SZ 6
+#define RG_ULG_PGA_SAT_PGA_GAIN_MSK 0x0000000f
+#define RG_ULG_PGA_SAT_PGA_GAIN_I_MSK 0xfffffff0
+#define RG_ULG_PGA_SAT_PGA_GAIN_SFT 0
+#define RG_ULG_PGA_SAT_PGA_GAIN_HI 3
+#define RG_ULG_PGA_SAT_PGA_GAIN_SZ 4
+#define RG_LG_PGA_UND_PGA_GAIN_MSK 0x000000f0
+#define RG_LG_PGA_UND_PGA_GAIN_I_MSK 0xffffff0f
+#define RG_LG_PGA_UND_PGA_GAIN_SFT 4
+#define RG_LG_PGA_UND_PGA_GAIN_HI 7
+#define RG_LG_PGA_UND_PGA_GAIN_SZ 4
+#define RG_LG_PGA_SAT_PGA_GAIN_MSK 0x00000f00
+#define RG_LG_PGA_SAT_PGA_GAIN_I_MSK 0xfffff0ff
+#define RG_LG_PGA_SAT_PGA_GAIN_SFT 8
+#define RG_LG_PGA_SAT_PGA_GAIN_HI 11
+#define RG_LG_PGA_SAT_PGA_GAIN_SZ 4
+#define RG_LG_RF_SAT_PGA_GAIN_MSK 0x0000f000
+#define RG_LG_RF_SAT_PGA_GAIN_I_MSK 0xffff0fff
+#define RG_LG_RF_SAT_PGA_GAIN_SFT 12
+#define RG_LG_RF_SAT_PGA_GAIN_HI 15
+#define RG_LG_RF_SAT_PGA_GAIN_SZ 4
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_MSK 0x000f0000
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_I_MSK 0xfff0ffff
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SFT 16
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_HI 19
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SZ 4
+#define RG_HG_PGA_SAT2_PGA_GAIN_MSK 0x00f00000
+#define RG_HG_PGA_SAT2_PGA_GAIN_I_MSK 0xff0fffff
+#define RG_HG_PGA_SAT2_PGA_GAIN_SFT 20
+#define RG_HG_PGA_SAT2_PGA_GAIN_HI 23
+#define RG_HG_PGA_SAT2_PGA_GAIN_SZ 4
+#define RG_HG_PGA_SAT1_PGA_GAIN_MSK 0x0f000000
+#define RG_HG_PGA_SAT1_PGA_GAIN_I_MSK 0xf0ffffff
+#define RG_HG_PGA_SAT1_PGA_GAIN_SFT 24
+#define RG_HG_PGA_SAT1_PGA_GAIN_HI 27
+#define RG_HG_PGA_SAT1_PGA_GAIN_SZ 4
+#define RG_HG_RF_SAT_PGA_GAIN_MSK 0xf0000000
+#define RG_HG_RF_SAT_PGA_GAIN_I_MSK 0x0fffffff
+#define RG_HG_RF_SAT_PGA_GAIN_SFT 28
+#define RG_HG_RF_SAT_PGA_GAIN_HI 31
+#define RG_HG_RF_SAT_PGA_GAIN_SZ 4
+#define RG_MG_PGA_JB_TH_MSK 0x0000000f
+#define RG_MG_PGA_JB_TH_I_MSK 0xfffffff0
+#define RG_MG_PGA_JB_TH_SFT 0
+#define RG_MG_PGA_JB_TH_HI 3
+#define RG_MG_PGA_JB_TH_SZ 4
+#define RG_MA_PGA_LOW_TH_CNT_LMT_MSK 0x001f0000
+#define RG_MA_PGA_LOW_TH_CNT_LMT_I_MSK 0xffe0ffff
+#define RG_MA_PGA_LOW_TH_CNT_LMT_SFT 16
+#define RG_MA_PGA_LOW_TH_CNT_LMT_HI 20
+#define RG_MA_PGA_LOW_TH_CNT_LMT_SZ 5
+#define RG_WR_RFGC_INIT_SET_MSK 0x00600000
+#define RG_WR_RFGC_INIT_SET_I_MSK 0xff9fffff
+#define RG_WR_RFGC_INIT_SET_SFT 21
+#define RG_WR_RFGC_INIT_SET_HI 22
+#define RG_WR_RFGC_INIT_SET_SZ 2
+#define RG_WR_RFGC_INIT_EN_MSK 0x00800000
+#define RG_WR_RFGC_INIT_EN_I_MSK 0xff7fffff
+#define RG_WR_RFGC_INIT_EN_SFT 23
+#define RG_WR_RFGC_INIT_EN_HI 23
+#define RG_WR_RFGC_INIT_EN_SZ 1
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_MSK 0x1f000000
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_I_MSK 0xe0ffffff
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_SFT 24
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_HI 28
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_SZ 5
+#define RG_AGC_THRESHOLD_MSK 0x00003fff
+#define RG_AGC_THRESHOLD_I_MSK 0xffffc000
+#define RG_AGC_THRESHOLD_SFT 0
+#define RG_AGC_THRESHOLD_HI 13
+#define RG_AGC_THRESHOLD_SZ 14
+#define RG_ACI_POINT_CNT_LMT_11B_MSK 0x007f0000
+#define RG_ACI_POINT_CNT_LMT_11B_I_MSK 0xff80ffff
+#define RG_ACI_POINT_CNT_LMT_11B_SFT 16
+#define RG_ACI_POINT_CNT_LMT_11B_HI 22
+#define RG_ACI_POINT_CNT_LMT_11B_SZ 7
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_MSK 0x03000000
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_I_MSK 0xfcffffff
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SFT 24
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_HI 25
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SZ 2
+#define RG_WR_ACI_GAIN_INI_SEL_11B_MSK 0x000000ff
+#define RG_WR_ACI_GAIN_INI_SEL_11B_I_MSK 0xffffff00
+#define RG_WR_ACI_GAIN_INI_SEL_11B_SFT 0
+#define RG_WR_ACI_GAIN_INI_SEL_11B_HI 7
+#define RG_WR_ACI_GAIN_INI_SEL_11B_SZ 8
+#define RG_WR_ACI_GAIN_SEL_11B_MSK 0x0000ff00
+#define RG_WR_ACI_GAIN_SEL_11B_I_MSK 0xffff00ff
+#define RG_WR_ACI_GAIN_SEL_11B_SFT 8
+#define RG_WR_ACI_GAIN_SEL_11B_HI 15
+#define RG_WR_ACI_GAIN_SEL_11B_SZ 8
+#define RG_ACI_DAGC_SET_VALUE_11B_MSK 0x007f0000
+#define RG_ACI_DAGC_SET_VALUE_11B_I_MSK 0xff80ffff
+#define RG_ACI_DAGC_SET_VALUE_11B_SFT 16
+#define RG_ACI_DAGC_SET_VALUE_11B_HI 22
+#define RG_ACI_DAGC_SET_VALUE_11B_SZ 7
+#define RG_WR_ACI_GAIN_OW_11B_MSK 0x80000000
+#define RG_WR_ACI_GAIN_OW_11B_I_MSK 0x7fffffff
+#define RG_WR_ACI_GAIN_OW_11B_SFT 31
+#define RG_WR_ACI_GAIN_OW_11B_HI 31
+#define RG_WR_ACI_GAIN_OW_11B_SZ 1
+#define RG_ACI_POINT_CNT_LMT_11GN_MSK 0x000000ff
+#define RG_ACI_POINT_CNT_LMT_11GN_I_MSK 0xffffff00
+#define RG_ACI_POINT_CNT_LMT_11GN_SFT 0
+#define RG_ACI_POINT_CNT_LMT_11GN_HI 7
+#define RG_ACI_POINT_CNT_LMT_11GN_SZ 8
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_MSK 0x00000300
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_I_MSK 0xfffffcff
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SFT 8
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HI 9
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SZ 2
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_MSK 0xff000000
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_I_MSK 0x00ffffff
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SFT 24
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_HI 31
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SZ 8
+#define RG_ACI_DAGC_SET_VALUE_11GN_MSK 0x0000007f
+#define RG_ACI_DAGC_SET_VALUE_11GN_I_MSK 0xffffff80
+#define RG_ACI_DAGC_SET_VALUE_11GN_SFT 0
+#define RG_ACI_DAGC_SET_VALUE_11GN_HI 6
+#define RG_ACI_DAGC_SET_VALUE_11GN_SZ 7
+#define RG_ACI_GAIN_INI_VAL_11GN_MSK 0x0000ff00
+#define RG_ACI_GAIN_INI_VAL_11GN_I_MSK 0xffff00ff
+#define RG_ACI_GAIN_INI_VAL_11GN_SFT 8
+#define RG_ACI_GAIN_INI_VAL_11GN_HI 15
+#define RG_ACI_GAIN_INI_VAL_11GN_SZ 8
+#define RG_ACI_GAIN_OW_VAL_11GN_MSK 0x00ff0000
+#define RG_ACI_GAIN_OW_VAL_11GN_I_MSK 0xff00ffff
+#define RG_ACI_GAIN_OW_VAL_11GN_SFT 16
+#define RG_ACI_GAIN_OW_VAL_11GN_HI 23
+#define RG_ACI_GAIN_OW_VAL_11GN_SZ 8
+#define RG_ACI_GAIN_OW_11GN_MSK 0x80000000
+#define RG_ACI_GAIN_OW_11GN_I_MSK 0x7fffffff
+#define RG_ACI_GAIN_OW_11GN_SFT 31
+#define RG_ACI_GAIN_OW_11GN_HI 31
+#define RG_ACI_GAIN_OW_11GN_SZ 1
+#define RO_CCA_PWR_MA_11GN_MSK 0x0000007f
+#define RO_CCA_PWR_MA_11GN_I_MSK 0xffffff80
+#define RO_CCA_PWR_MA_11GN_SFT 0
+#define RO_CCA_PWR_MA_11GN_HI 6
+#define RO_CCA_PWR_MA_11GN_SZ 7
+#define RO_ED_STATE_MSK 0x00008000
+#define RO_ED_STATE_I_MSK 0xffff7fff
+#define RO_ED_STATE_SFT 15
+#define RO_ED_STATE_HI 15
+#define RO_ED_STATE_SZ 1
+#define RO_CCA_PWR_MA_11B_MSK 0x007f0000
+#define RO_CCA_PWR_MA_11B_I_MSK 0xff80ffff
+#define RO_CCA_PWR_MA_11B_SFT 16
+#define RO_CCA_PWR_MA_11B_HI 22
+#define RO_CCA_PWR_MA_11B_SZ 7
+#define RO_PGA_PWR_FF1_MSK 0x00003fff
+#define RO_PGA_PWR_FF1_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF1_SFT 0
+#define RO_PGA_PWR_FF1_HI 13
+#define RO_PGA_PWR_FF1_SZ 14
+#define RO_RF_PWR_FF1_MSK 0x000f0000
+#define RO_RF_PWR_FF1_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF1_SFT 16
+#define RO_RF_PWR_FF1_HI 19
+#define RO_RF_PWR_FF1_SZ 4
+#define RO_PGAGC_FF1_MSK 0x0f000000
+#define RO_PGAGC_FF1_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF1_SFT 24
+#define RO_PGAGC_FF1_HI 27
+#define RO_PGAGC_FF1_SZ 4
+#define RO_RFGC_FF1_MSK 0x30000000
+#define RO_RFGC_FF1_I_MSK 0xcfffffff
+#define RO_RFGC_FF1_SFT 28
+#define RO_RFGC_FF1_HI 29
+#define RO_RFGC_FF1_SZ 2
+#define RO_PGA_PWR_FF2_MSK 0x00003fff
+#define RO_PGA_PWR_FF2_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF2_SFT 0
+#define RO_PGA_PWR_FF2_HI 13
+#define RO_PGA_PWR_FF2_SZ 14
+#define RO_RF_PWR_FF2_MSK 0x000f0000
+#define RO_RF_PWR_FF2_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF2_SFT 16
+#define RO_RF_PWR_FF2_HI 19
+#define RO_RF_PWR_FF2_SZ 4
+#define RO_PGAGC_FF2_MSK 0x0f000000
+#define RO_PGAGC_FF2_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF2_SFT 24
+#define RO_PGAGC_FF2_HI 27
+#define RO_PGAGC_FF2_SZ 4
+#define RO_RFGC_FF2_MSK 0x30000000
+#define RO_RFGC_FF2_I_MSK 0xcfffffff
+#define RO_RFGC_FF2_SFT 28
+#define RO_RFGC_FF2_HI 29
+#define RO_RFGC_FF2_SZ 2
+#define RO_PGA_PWR_FF3_MSK 0x00003fff
+#define RO_PGA_PWR_FF3_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF3_SFT 0
+#define RO_PGA_PWR_FF3_HI 13
+#define RO_PGA_PWR_FF3_SZ 14
+#define RO_RF_PWR_FF3_MSK 0x000f0000
+#define RO_RF_PWR_FF3_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF3_SFT 16
+#define RO_RF_PWR_FF3_HI 19
+#define RO_RF_PWR_FF3_SZ 4
+#define RO_PGAGC_FF3_MSK 0x0f000000
+#define RO_PGAGC_FF3_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF3_SFT 24
+#define RO_PGAGC_FF3_HI 27
+#define RO_PGAGC_FF3_SZ 4
+#define RO_RFGC_FF3_MSK 0x30000000
+#define RO_RFGC_FF3_I_MSK 0xcfffffff
+#define RO_RFGC_FF3_SFT 28
+#define RO_RFGC_FF3_HI 29
+#define RO_RFGC_FF3_SZ 2
+#define RG_TX_DES_RATE_MSK 0x0000001f
+#define RG_TX_DES_RATE_I_MSK 0xffffffe0
+#define RG_TX_DES_RATE_SFT 0
+#define RG_TX_DES_RATE_HI 4
+#define RG_TX_DES_RATE_SZ 5
+#define RG_TX_DES_MODE_MSK 0x00001f00
+#define RG_TX_DES_MODE_I_MSK 0xffffe0ff
+#define RG_TX_DES_MODE_SFT 8
+#define RG_TX_DES_MODE_HI 12
+#define RG_TX_DES_MODE_SZ 5
+#define RG_TX_DES_LEN_LO_MSK 0x001f0000
+#define RG_TX_DES_LEN_LO_I_MSK 0xffe0ffff
+#define RG_TX_DES_LEN_LO_SFT 16
+#define RG_TX_DES_LEN_LO_HI 20
+#define RG_TX_DES_LEN_LO_SZ 5
+#define RG_TX_DES_LEN_UP_MSK 0x1f000000
+#define RG_TX_DES_LEN_UP_I_MSK 0xe0ffffff
+#define RG_TX_DES_LEN_UP_SFT 24
+#define RG_TX_DES_LEN_UP_HI 28
+#define RG_TX_DES_LEN_UP_SZ 5
+#define RG_TX_DES_SRVC_UP_MSK 0x0000001f
+#define RG_TX_DES_SRVC_UP_I_MSK 0xffffffe0
+#define RG_TX_DES_SRVC_UP_SFT 0
+#define RG_TX_DES_SRVC_UP_HI 4
+#define RG_TX_DES_SRVC_UP_SZ 5
+#define RG_TX_DES_L_LEN_LO_MSK 0x00001f00
+#define RG_TX_DES_L_LEN_LO_I_MSK 0xffffe0ff
+#define RG_TX_DES_L_LEN_LO_SFT 8
+#define RG_TX_DES_L_LEN_LO_HI 12
+#define RG_TX_DES_L_LEN_LO_SZ 5
+#define RG_TX_DES_L_LEN_UP_MSK 0x001f0000
+#define RG_TX_DES_L_LEN_UP_I_MSK 0xffe0ffff
+#define RG_TX_DES_L_LEN_UP_SFT 16
+#define RG_TX_DES_L_LEN_UP_HI 20
+#define RG_TX_DES_L_LEN_UP_SZ 5
+#define RG_TX_DES_TYPE_MSK 0x1f000000
+#define RG_TX_DES_TYPE_I_MSK 0xe0ffffff
+#define RG_TX_DES_TYPE_SFT 24
+#define RG_TX_DES_TYPE_HI 28
+#define RG_TX_DES_TYPE_SZ 5
+#define RG_TX_DES_L_LEN_UP_COMB_MSK 0x00000001
+#define RG_TX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
+#define RG_TX_DES_L_LEN_UP_COMB_SFT 0
+#define RG_TX_DES_L_LEN_UP_COMB_HI 0
+#define RG_TX_DES_L_LEN_UP_COMB_SZ 1
+#define RG_TX_DES_TYPE_COMB_MSK 0x00000010
+#define RG_TX_DES_TYPE_COMB_I_MSK 0xffffffef
+#define RG_TX_DES_TYPE_COMB_SFT 4
+#define RG_TX_DES_TYPE_COMB_HI 4
+#define RG_TX_DES_TYPE_COMB_SZ 1
+#define RG_TX_DES_RATE_COMB_MSK 0x00000100
+#define RG_TX_DES_RATE_COMB_I_MSK 0xfffffeff
+#define RG_TX_DES_RATE_COMB_SFT 8
+#define RG_TX_DES_RATE_COMB_HI 8
+#define RG_TX_DES_RATE_COMB_SZ 1
+#define RG_TX_DES_MODE_COMB_MSK 0x00001000
+#define RG_TX_DES_MODE_COMB_I_MSK 0xffffefff
+#define RG_TX_DES_MODE_COMB_SFT 12
+#define RG_TX_DES_MODE_COMB_HI 12
+#define RG_TX_DES_MODE_COMB_SZ 1
+#define RG_TX_DES_PWRLVL_MSK 0x001f0000
+#define RG_TX_DES_PWRLVL_I_MSK 0xffe0ffff
+#define RG_TX_DES_PWRLVL_SFT 16
+#define RG_TX_DES_PWRLVL_HI 20
+#define RG_TX_DES_PWRLVL_SZ 5
+#define RG_TX_DES_SRVC_LO_MSK 0x1f000000
+#define RG_TX_DES_SRVC_LO_I_MSK 0xe0ffffff
+#define RG_TX_DES_SRVC_LO_SFT 24
+#define RG_TX_DES_SRVC_LO_HI 28
+#define RG_TX_DES_SRVC_LO_SZ 5
+#define RG_RX_DES_RATE_MSK 0x0000003f
+#define RG_RX_DES_RATE_I_MSK 0xffffffc0
+#define RG_RX_DES_RATE_SFT 0
+#define RG_RX_DES_RATE_HI 5
+#define RG_RX_DES_RATE_SZ 6
+#define RG_RX_DES_MODE_MSK 0x00003f00
+#define RG_RX_DES_MODE_I_MSK 0xffffc0ff
+#define RG_RX_DES_MODE_SFT 8
+#define RG_RX_DES_MODE_HI 13
+#define RG_RX_DES_MODE_SZ 6
+#define RG_RX_DES_LEN_LO_MSK 0x003f0000
+#define RG_RX_DES_LEN_LO_I_MSK 0xffc0ffff
+#define RG_RX_DES_LEN_LO_SFT 16
+#define RG_RX_DES_LEN_LO_HI 21
+#define RG_RX_DES_LEN_LO_SZ 6
+#define RG_RX_DES_LEN_UP_MSK 0x3f000000
+#define RG_RX_DES_LEN_UP_I_MSK 0xc0ffffff
+#define RG_RX_DES_LEN_UP_SFT 24
+#define RG_RX_DES_LEN_UP_HI 29
+#define RG_RX_DES_LEN_UP_SZ 6
+#define RG_RX_DES_SRVC_UP_MSK 0x0000003f
+#define RG_RX_DES_SRVC_UP_I_MSK 0xffffffc0
+#define RG_RX_DES_SRVC_UP_SFT 0
+#define RG_RX_DES_SRVC_UP_HI 5
+#define RG_RX_DES_SRVC_UP_SZ 6
+#define RG_RX_DES_L_LEN_LO_MSK 0x00003f00
+#define RG_RX_DES_L_LEN_LO_I_MSK 0xffffc0ff
+#define RG_RX_DES_L_LEN_LO_SFT 8
+#define RG_RX_DES_L_LEN_LO_HI 13
+#define RG_RX_DES_L_LEN_LO_SZ 6
+#define RG_RX_DES_L_LEN_UP_MSK 0x003f0000
+#define RG_RX_DES_L_LEN_UP_I_MSK 0xffc0ffff
+#define RG_RX_DES_L_LEN_UP_SFT 16
+#define RG_RX_DES_L_LEN_UP_HI 21
+#define RG_RX_DES_L_LEN_UP_SZ 6
+#define RG_RX_DES_TYPE_MSK 0x3f000000
+#define RG_RX_DES_TYPE_I_MSK 0xc0ffffff
+#define RG_RX_DES_TYPE_SFT 24
+#define RG_RX_DES_TYPE_HI 29
+#define RG_RX_DES_TYPE_SZ 6
+#define RG_RX_DES_L_LEN_UP_COMB_MSK 0x00000001
+#define RG_RX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
+#define RG_RX_DES_L_LEN_UP_COMB_SFT 0
+#define RG_RX_DES_L_LEN_UP_COMB_HI 0
+#define RG_RX_DES_L_LEN_UP_COMB_SZ 1
+#define RG_RX_DES_TYPE_COMB_MSK 0x00000010
+#define RG_RX_DES_TYPE_COMB_I_MSK 0xffffffef
+#define RG_RX_DES_TYPE_COMB_SFT 4
+#define RG_RX_DES_TYPE_COMB_HI 4
+#define RG_RX_DES_TYPE_COMB_SZ 1
+#define RG_RX_DES_RATE_COMB_MSK 0x00000100
+#define RG_RX_DES_RATE_COMB_I_MSK 0xfffffeff
+#define RG_RX_DES_RATE_COMB_SFT 8
+#define RG_RX_DES_RATE_COMB_HI 8
+#define RG_RX_DES_RATE_COMB_SZ 1
+#define RG_RX_DES_MODE_COMB_MSK 0x00001000
+#define RG_RX_DES_MODE_COMB_I_MSK 0xffffefff
+#define RG_RX_DES_MODE_COMB_SFT 12
+#define RG_RX_DES_MODE_COMB_HI 12
+#define RG_RX_DES_MODE_COMB_SZ 1
+#define RG_RX_DES_SNR_MSK 0x000f0000
+#define RG_RX_DES_SNR_I_MSK 0xfff0ffff
+#define RG_RX_DES_SNR_SFT 16
+#define RG_RX_DES_SNR_HI 19
+#define RG_RX_DES_SNR_SZ 4
+#define RG_RX_DES_RCPI_MSK 0x00f00000
+#define RG_RX_DES_RCPI_I_MSK 0xff0fffff
+#define RG_RX_DES_RCPI_SFT 20
+#define RG_RX_DES_RCPI_HI 23
+#define RG_RX_DES_RCPI_SZ 4
+#define RG_RX_DES_SRVC_LO_MSK 0x3f000000
+#define RG_RX_DES_SRVC_LO_I_MSK 0xc0ffffff
+#define RG_RX_DES_SRVC_LO_SFT 24
+#define RG_RX_DES_SRVC_LO_HI 29
+#define RG_RX_DES_SRVC_LO_SZ 6
+#define RO_TX_DES_EXCP_RATE_CNT_MSK 0x000000ff
+#define RO_TX_DES_EXCP_RATE_CNT_I_MSK 0xffffff00
+#define RO_TX_DES_EXCP_RATE_CNT_SFT 0
+#define RO_TX_DES_EXCP_RATE_CNT_HI 7
+#define RO_TX_DES_EXCP_RATE_CNT_SZ 8
+#define RO_TX_DES_EXCP_CH_BW_CNT_MSK 0x0000ff00
+#define RO_TX_DES_EXCP_CH_BW_CNT_I_MSK 0xffff00ff
+#define RO_TX_DES_EXCP_CH_BW_CNT_SFT 8
+#define RO_TX_DES_EXCP_CH_BW_CNT_HI 15
+#define RO_TX_DES_EXCP_CH_BW_CNT_SZ 8
+#define RO_TX_DES_EXCP_MODE_CNT_MSK 0x00ff0000
+#define RO_TX_DES_EXCP_MODE_CNT_I_MSK 0xff00ffff
+#define RO_TX_DES_EXCP_MODE_CNT_SFT 16
+#define RO_TX_DES_EXCP_MODE_CNT_HI 23
+#define RO_TX_DES_EXCP_MODE_CNT_SZ 8
+#define RG_TX_DES_EXCP_RATE_DEFAULT_MSK 0x07000000
+#define RG_TX_DES_EXCP_RATE_DEFAULT_I_MSK 0xf8ffffff
+#define RG_TX_DES_EXCP_RATE_DEFAULT_SFT 24
+#define RG_TX_DES_EXCP_RATE_DEFAULT_HI 26
+#define RG_TX_DES_EXCP_RATE_DEFAULT_SZ 3
+#define RG_TX_DES_EXCP_MODE_DEFAULT_MSK 0x70000000
+#define RG_TX_DES_EXCP_MODE_DEFAULT_I_MSK 0x8fffffff
+#define RG_TX_DES_EXCP_MODE_DEFAULT_SFT 28
+#define RG_TX_DES_EXCP_MODE_DEFAULT_HI 30
+#define RG_TX_DES_EXCP_MODE_DEFAULT_SZ 3
+#define RG_TX_DES_EXCP_CLR_MSK 0x80000000
+#define RG_TX_DES_EXCP_CLR_I_MSK 0x7fffffff
+#define RG_TX_DES_EXCP_CLR_SFT 31
+#define RG_TX_DES_EXCP_CLR_HI 31
+#define RG_TX_DES_EXCP_CLR_SZ 1
+#define RG_TX_DES_ACK_WIDTH_MSK 0x00000001
+#define RG_TX_DES_ACK_WIDTH_I_MSK 0xfffffffe
+#define RG_TX_DES_ACK_WIDTH_SFT 0
+#define RG_TX_DES_ACK_WIDTH_HI 0
+#define RG_TX_DES_ACK_WIDTH_SZ 1
+#define RG_TX_DES_ACK_PRD_MSK 0x0000000e
+#define RG_TX_DES_ACK_PRD_I_MSK 0xfffffff1
+#define RG_TX_DES_ACK_PRD_SFT 1
+#define RG_TX_DES_ACK_PRD_HI 3
+#define RG_TX_DES_ACK_PRD_SZ 3
+#define RG_RX_DES_SNR_GN_MSK 0x003f0000
+#define RG_RX_DES_SNR_GN_I_MSK 0xffc0ffff
+#define RG_RX_DES_SNR_GN_SFT 16
+#define RG_RX_DES_SNR_GN_HI 21
+#define RG_RX_DES_SNR_GN_SZ 6
+#define RG_RX_DES_RCPI_GN_MSK 0x3f000000
+#define RG_RX_DES_RCPI_GN_I_MSK 0xc0ffffff
+#define RG_RX_DES_RCPI_GN_SFT 24
+#define RG_RX_DES_RCPI_GN_HI 29
+#define RG_RX_DES_RCPI_GN_SZ 6
+#define RG_TST_TBUS_SEL_MSK 0x0000000f
+#define RG_TST_TBUS_SEL_I_MSK 0xfffffff0
+#define RG_TST_TBUS_SEL_SFT 0
+#define RG_TST_TBUS_SEL_HI 3
+#define RG_TST_TBUS_SEL_SZ 4
+#define RG_RSSI_OFFSET_MSK 0x00ff0000
+#define RG_RSSI_OFFSET_I_MSK 0xff00ffff
+#define RG_RSSI_OFFSET_SFT 16
+#define RG_RSSI_OFFSET_HI 23
+#define RG_RSSI_OFFSET_SZ 8
+#define RG_RSSI_INV_MSK 0x01000000
+#define RG_RSSI_INV_I_MSK 0xfeffffff
+#define RG_RSSI_INV_SFT 24
+#define RG_RSSI_INV_HI 24
+#define RG_RSSI_INV_SZ 1
+#define RG_TST_ADC_ON_MSK 0x40000000
+#define RG_TST_ADC_ON_I_MSK 0xbfffffff
+#define RG_TST_ADC_ON_SFT 30
+#define RG_TST_ADC_ON_HI 30
+#define RG_TST_ADC_ON_SZ 1
+#define RG_TST_EXT_GAIN_MSK 0x80000000
+#define RG_TST_EXT_GAIN_I_MSK 0x7fffffff
+#define RG_TST_EXT_GAIN_SFT 31
+#define RG_TST_EXT_GAIN_HI 31
+#define RG_TST_EXT_GAIN_SZ 1
+#define RG_DAC_Q_SET_MSK 0x000003ff
+#define RG_DAC_Q_SET_I_MSK 0xfffffc00
+#define RG_DAC_Q_SET_SFT 0
+#define RG_DAC_Q_SET_HI 9
+#define RG_DAC_Q_SET_SZ 10
+#define RG_DAC_I_SET_MSK 0x003ff000
+#define RG_DAC_I_SET_I_MSK 0xffc00fff
+#define RG_DAC_I_SET_SFT 12
+#define RG_DAC_I_SET_HI 21
+#define RG_DAC_I_SET_SZ 10
+#define RG_DAC_EN_MAN_MSK 0x10000000
+#define RG_DAC_EN_MAN_I_MSK 0xefffffff
+#define RG_DAC_EN_MAN_SFT 28
+#define RG_DAC_EN_MAN_HI 28
+#define RG_DAC_EN_MAN_SZ 1
+#define RG_IQC_FFT_EN_MSK 0x20000000
+#define RG_IQC_FFT_EN_I_MSK 0xdfffffff
+#define RG_IQC_FFT_EN_SFT 29
+#define RG_IQC_FFT_EN_HI 29
+#define RG_IQC_FFT_EN_SZ 1
+#define RG_DAC_MAN_Q_EN_MSK 0x40000000
+#define RG_DAC_MAN_Q_EN_I_MSK 0xbfffffff
+#define RG_DAC_MAN_Q_EN_SFT 30
+#define RG_DAC_MAN_Q_EN_HI 30
+#define RG_DAC_MAN_Q_EN_SZ 1
+#define RG_DAC_MAN_I_EN_MSK 0x80000000
+#define RG_DAC_MAN_I_EN_I_MSK 0x7fffffff
+#define RG_DAC_MAN_I_EN_SFT 31
+#define RG_DAC_MAN_I_EN_HI 31
+#define RG_DAC_MAN_I_EN_SZ 1
+#define RO_MRX_EN_CNT_MSK 0x0000ffff
+#define RO_MRX_EN_CNT_I_MSK 0xffff0000
+#define RO_MRX_EN_CNT_SFT 0
+#define RO_MRX_EN_CNT_HI 15
+#define RO_MRX_EN_CNT_SZ 16
+#define RG_MRX_EN_CNT_RST_N_MSK 0x80000000
+#define RG_MRX_EN_CNT_RST_N_I_MSK 0x7fffffff
+#define RG_MRX_EN_CNT_RST_N_SFT 31
+#define RG_MRX_EN_CNT_RST_N_HI 31
+#define RG_MRX_EN_CNT_RST_N_SZ 1
+#define RG_PA_RISE_TIME_MSK 0x000000ff
+#define RG_PA_RISE_TIME_I_MSK 0xffffff00
+#define RG_PA_RISE_TIME_SFT 0
+#define RG_PA_RISE_TIME_HI 7
+#define RG_PA_RISE_TIME_SZ 8
+#define RG_RFTX_RISE_TIME_MSK 0x0000ff00
+#define RG_RFTX_RISE_TIME_I_MSK 0xffff00ff
+#define RG_RFTX_RISE_TIME_SFT 8
+#define RG_RFTX_RISE_TIME_HI 15
+#define RG_RFTX_RISE_TIME_SZ 8
+#define RG_DAC_RISE_TIME_MSK 0x00ff0000
+#define RG_DAC_RISE_TIME_I_MSK 0xff00ffff
+#define RG_DAC_RISE_TIME_SFT 16
+#define RG_DAC_RISE_TIME_HI 23
+#define RG_DAC_RISE_TIME_SZ 8
+#define RG_SW_RISE_TIME_MSK 0xff000000
+#define RG_SW_RISE_TIME_I_MSK 0x00ffffff
+#define RG_SW_RISE_TIME_SFT 24
+#define RG_SW_RISE_TIME_HI 31
+#define RG_SW_RISE_TIME_SZ 8
+#define RG_PA_FALL_TIME_MSK 0x000000ff
+#define RG_PA_FALL_TIME_I_MSK 0xffffff00
+#define RG_PA_FALL_TIME_SFT 0
+#define RG_PA_FALL_TIME_HI 7
+#define RG_PA_FALL_TIME_SZ 8
+#define RG_RFTX_FALL_TIME_MSK 0x0000ff00
+#define RG_RFTX_FALL_TIME_I_MSK 0xffff00ff
+#define RG_RFTX_FALL_TIME_SFT 8
+#define RG_RFTX_FALL_TIME_HI 15
+#define RG_RFTX_FALL_TIME_SZ 8
+#define RG_DAC_FALL_TIME_MSK 0x00ff0000
+#define RG_DAC_FALL_TIME_I_MSK 0xff00ffff
+#define RG_DAC_FALL_TIME_SFT 16
+#define RG_DAC_FALL_TIME_HI 23
+#define RG_DAC_FALL_TIME_SZ 8
+#define RG_SW_FALL_TIME_MSK 0xff000000
+#define RG_SW_FALL_TIME_I_MSK 0x00ffffff
+#define RG_SW_FALL_TIME_SFT 24
+#define RG_SW_FALL_TIME_HI 31
+#define RG_SW_FALL_TIME_SZ 8
+#define RG_ANT_SW_0_MSK 0x00000007
+#define RG_ANT_SW_0_I_MSK 0xfffffff8
+#define RG_ANT_SW_0_SFT 0
+#define RG_ANT_SW_0_HI 2
+#define RG_ANT_SW_0_SZ 3
+#define RG_ANT_SW_1_MSK 0x00000038
+#define RG_ANT_SW_1_I_MSK 0xffffffc7
+#define RG_ANT_SW_1_SFT 3
+#define RG_ANT_SW_1_HI 5
+#define RG_ANT_SW_1_SZ 3
+#define RG_MTX_LEN_LOWER_TH_0_MSK 0x00001fff
+#define RG_MTX_LEN_LOWER_TH_0_I_MSK 0xffffe000
+#define RG_MTX_LEN_LOWER_TH_0_SFT 0
+#define RG_MTX_LEN_LOWER_TH_0_HI 12
+#define RG_MTX_LEN_LOWER_TH_0_SZ 13
+#define RG_MTX_LEN_UPPER_TH_0_MSK 0x1fff0000
+#define RG_MTX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
+#define RG_MTX_LEN_UPPER_TH_0_SFT 16
+#define RG_MTX_LEN_UPPER_TH_0_HI 28
+#define RG_MTX_LEN_UPPER_TH_0_SZ 13
+#define RG_MTX_LEN_CNT_EN_0_MSK 0x80000000
+#define RG_MTX_LEN_CNT_EN_0_I_MSK 0x7fffffff
+#define RG_MTX_LEN_CNT_EN_0_SFT 31
+#define RG_MTX_LEN_CNT_EN_0_HI 31
+#define RG_MTX_LEN_CNT_EN_0_SZ 1
+#define RG_MTX_LEN_LOWER_TH_1_MSK 0x00001fff
+#define RG_MTX_LEN_LOWER_TH_1_I_MSK 0xffffe000
+#define RG_MTX_LEN_LOWER_TH_1_SFT 0
+#define RG_MTX_LEN_LOWER_TH_1_HI 12
+#define RG_MTX_LEN_LOWER_TH_1_SZ 13
+#define RG_MTX_LEN_UPPER_TH_1_MSK 0x1fff0000
+#define RG_MTX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
+#define RG_MTX_LEN_UPPER_TH_1_SFT 16
+#define RG_MTX_LEN_UPPER_TH_1_HI 28
+#define RG_MTX_LEN_UPPER_TH_1_SZ 13
+#define RG_MTX_LEN_CNT_EN_1_MSK 0x80000000
+#define RG_MTX_LEN_CNT_EN_1_I_MSK 0x7fffffff
+#define RG_MTX_LEN_CNT_EN_1_SFT 31
+#define RG_MTX_LEN_CNT_EN_1_HI 31
+#define RG_MTX_LEN_CNT_EN_1_SZ 1
+#define RG_MRX_LEN_LOWER_TH_0_MSK 0x00001fff
+#define RG_MRX_LEN_LOWER_TH_0_I_MSK 0xffffe000
+#define RG_MRX_LEN_LOWER_TH_0_SFT 0
+#define RG_MRX_LEN_LOWER_TH_0_HI 12
+#define RG_MRX_LEN_LOWER_TH_0_SZ 13
+#define RG_MRX_LEN_UPPER_TH_0_MSK 0x1fff0000
+#define RG_MRX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
+#define RG_MRX_LEN_UPPER_TH_0_SFT 16
+#define RG_MRX_LEN_UPPER_TH_0_HI 28
+#define RG_MRX_LEN_UPPER_TH_0_SZ 13
+#define RG_MRX_LEN_CNT_EN_0_MSK 0x80000000
+#define RG_MRX_LEN_CNT_EN_0_I_MSK 0x7fffffff
+#define RG_MRX_LEN_CNT_EN_0_SFT 31
+#define RG_MRX_LEN_CNT_EN_0_HI 31
+#define RG_MRX_LEN_CNT_EN_0_SZ 1
+#define RG_MRX_LEN_LOWER_TH_1_MSK 0x00001fff
+#define RG_MRX_LEN_LOWER_TH_1_I_MSK 0xffffe000
+#define RG_MRX_LEN_LOWER_TH_1_SFT 0
+#define RG_MRX_LEN_LOWER_TH_1_HI 12
+#define RG_MRX_LEN_LOWER_TH_1_SZ 13
+#define RG_MRX_LEN_UPPER_TH_1_MSK 0x1fff0000
+#define RG_MRX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
+#define RG_MRX_LEN_UPPER_TH_1_SFT 16
+#define RG_MRX_LEN_UPPER_TH_1_HI 28
+#define RG_MRX_LEN_UPPER_TH_1_SZ 13
+#define RG_MRX_LEN_CNT_EN_1_MSK 0x80000000
+#define RG_MRX_LEN_CNT_EN_1_I_MSK 0x7fffffff
+#define RG_MRX_LEN_CNT_EN_1_SFT 31
+#define RG_MRX_LEN_CNT_EN_1_HI 31
+#define RG_MRX_LEN_CNT_EN_1_SZ 1
+#define RO_MTX_LEN_CNT_1_MSK 0x0000ffff
+#define RO_MTX_LEN_CNT_1_I_MSK 0xffff0000
+#define RO_MTX_LEN_CNT_1_SFT 0
+#define RO_MTX_LEN_CNT_1_HI 15
+#define RO_MTX_LEN_CNT_1_SZ 16
+#define RO_MTX_LEN_CNT_0_MSK 0xffff0000
+#define RO_MTX_LEN_CNT_0_I_MSK 0x0000ffff
+#define RO_MTX_LEN_CNT_0_SFT 16
+#define RO_MTX_LEN_CNT_0_HI 31
+#define RO_MTX_LEN_CNT_0_SZ 16
+#define RO_MRX_LEN_CNT_1_MSK 0x0000ffff
+#define RO_MRX_LEN_CNT_1_I_MSK 0xffff0000
+#define RO_MRX_LEN_CNT_1_SFT 0
+#define RO_MRX_LEN_CNT_1_HI 15
+#define RO_MRX_LEN_CNT_1_SZ 16
+#define RO_MRX_LEN_CNT_0_MSK 0xffff0000
+#define RO_MRX_LEN_CNT_0_I_MSK 0x0000ffff
+#define RO_MRX_LEN_CNT_0_SFT 16
+#define RO_MRX_LEN_CNT_0_HI 31
+#define RO_MRX_LEN_CNT_0_SZ 16
+#define RG_MODE_REG_IN_16_MSK 0x0000ffff
+#define RG_MODE_REG_IN_16_I_MSK 0xffff0000
+#define RG_MODE_REG_IN_16_SFT 0
+#define RG_MODE_REG_IN_16_HI 15
+#define RG_MODE_REG_IN_16_SZ 16
+#define RG_PARALLEL_DR_16_MSK 0x00100000
+#define RG_PARALLEL_DR_16_I_MSK 0xffefffff
+#define RG_PARALLEL_DR_16_SFT 20
+#define RG_PARALLEL_DR_16_HI 20
+#define RG_PARALLEL_DR_16_SZ 1
+#define RG_MBRUN_16_MSK 0x01000000
+#define RG_MBRUN_16_I_MSK 0xfeffffff
+#define RG_MBRUN_16_SFT 24
+#define RG_MBRUN_16_HI 24
+#define RG_MBRUN_16_SZ 1
+#define RG_SHIFT_DR_16_MSK 0x10000000
+#define RG_SHIFT_DR_16_I_MSK 0xefffffff
+#define RG_SHIFT_DR_16_SFT 28
+#define RG_SHIFT_DR_16_HI 28
+#define RG_SHIFT_DR_16_SZ 1
+#define RG_MODE_REG_SI_16_MSK 0x20000000
+#define RG_MODE_REG_SI_16_I_MSK 0xdfffffff
+#define RG_MODE_REG_SI_16_SFT 29
+#define RG_MODE_REG_SI_16_HI 29
+#define RG_MODE_REG_SI_16_SZ 1
+#define RG_SIMULATION_MODE_16_MSK 0x40000000
+#define RG_SIMULATION_MODE_16_I_MSK 0xbfffffff
+#define RG_SIMULATION_MODE_16_SFT 30
+#define RG_SIMULATION_MODE_16_HI 30
+#define RG_SIMULATION_MODE_16_SZ 1
+#define RG_DBIST_MODE_16_MSK 0x80000000
+#define RG_DBIST_MODE_16_I_MSK 0x7fffffff
+#define RG_DBIST_MODE_16_SFT 31
+#define RG_DBIST_MODE_16_HI 31
+#define RG_DBIST_MODE_16_SZ 1
+#define RO_MODE_REG_OUT_16_MSK 0x0000ffff
+#define RO_MODE_REG_OUT_16_I_MSK 0xffff0000
+#define RO_MODE_REG_OUT_16_SFT 0
+#define RO_MODE_REG_OUT_16_HI 15
+#define RO_MODE_REG_OUT_16_SZ 16
+#define RO_MODE_REG_SO_16_MSK 0x01000000
+#define RO_MODE_REG_SO_16_I_MSK 0xfeffffff
+#define RO_MODE_REG_SO_16_SFT 24
+#define RO_MODE_REG_SO_16_HI 24
+#define RO_MODE_REG_SO_16_SZ 1
+#define RO_MONITOR_BUS_16_MSK 0x0007ffff
+#define RO_MONITOR_BUS_16_I_MSK 0xfff80000
+#define RO_MONITOR_BUS_16_SFT 0
+#define RO_MONITOR_BUS_16_HI 18
+#define RO_MONITOR_BUS_16_SZ 19
+#define RG_MRX_TYPE_1_MSK 0x000000ff
+#define RG_MRX_TYPE_1_I_MSK 0xffffff00
+#define RG_MRX_TYPE_1_SFT 0
+#define RG_MRX_TYPE_1_HI 7
+#define RG_MRX_TYPE_1_SZ 8
+#define RG_MRX_TYPE_0_MSK 0x0000ff00
+#define RG_MRX_TYPE_0_I_MSK 0xffff00ff
+#define RG_MRX_TYPE_0_SFT 8
+#define RG_MRX_TYPE_0_HI 15
+#define RG_MRX_TYPE_0_SZ 8
+#define RG_MTX_TYPE_1_MSK 0x00ff0000
+#define RG_MTX_TYPE_1_I_MSK 0xff00ffff
+#define RG_MTX_TYPE_1_SFT 16
+#define RG_MTX_TYPE_1_HI 23
+#define RG_MTX_TYPE_1_SZ 8
+#define RG_MTX_TYPE_0_MSK 0xff000000
+#define RG_MTX_TYPE_0_I_MSK 0x00ffffff
+#define RG_MTX_TYPE_0_SFT 24
+#define RG_MTX_TYPE_0_HI 31
+#define RG_MTX_TYPE_0_SZ 8
+#define RO_MTX_TYPE_CNT_1_MSK 0x0000ffff
+#define RO_MTX_TYPE_CNT_1_I_MSK 0xffff0000
+#define RO_MTX_TYPE_CNT_1_SFT 0
+#define RO_MTX_TYPE_CNT_1_HI 15
+#define RO_MTX_TYPE_CNT_1_SZ 16
+#define RO_MTX_TYPE_CNT_0_MSK 0xffff0000
+#define RO_MTX_TYPE_CNT_0_I_MSK 0x0000ffff
+#define RO_MTX_TYPE_CNT_0_SFT 16
+#define RO_MTX_TYPE_CNT_0_HI 31
+#define RO_MTX_TYPE_CNT_0_SZ 16
+#define RO_MRX_TYPE_CNT_1_MSK 0x0000ffff
+#define RO_MRX_TYPE_CNT_1_I_MSK 0xffff0000
+#define RO_MRX_TYPE_CNT_1_SFT 0
+#define RO_MRX_TYPE_CNT_1_HI 15
+#define RO_MRX_TYPE_CNT_1_SZ 16
+#define RO_MRX_TYPE_CNT_0_MSK 0xffff0000
+#define RO_MRX_TYPE_CNT_0_I_MSK 0x0000ffff
+#define RO_MRX_TYPE_CNT_0_SFT 16
+#define RO_MRX_TYPE_CNT_0_HI 31
+#define RO_MRX_TYPE_CNT_0_SZ 16
+#define RG_HB_COEF0_MSK 0x00000fff
+#define RG_HB_COEF0_I_MSK 0xfffff000
+#define RG_HB_COEF0_SFT 0
+#define RG_HB_COEF0_HI 11
+#define RG_HB_COEF0_SZ 12
+#define RG_HB_COEF1_MSK 0x0fff0000
+#define RG_HB_COEF1_I_MSK 0xf000ffff
+#define RG_HB_COEF1_SFT 16
+#define RG_HB_COEF1_HI 27
+#define RG_HB_COEF1_SZ 12
+#define RG_HB_COEF2_MSK 0x00000fff
+#define RG_HB_COEF2_I_MSK 0xfffff000
+#define RG_HB_COEF2_SFT 0
+#define RG_HB_COEF2_HI 11
+#define RG_HB_COEF2_SZ 12
+#define RG_HB_COEF3_MSK 0x0fff0000
+#define RG_HB_COEF3_I_MSK 0xf000ffff
+#define RG_HB_COEF3_SFT 16
+#define RG_HB_COEF3_HI 27
+#define RG_HB_COEF3_SZ 12
+#define RG_HB_COEF4_MSK 0x00000fff
+#define RG_HB_COEF4_I_MSK 0xfffff000
+#define RG_HB_COEF4_SFT 0
+#define RG_HB_COEF4_HI 11
+#define RG_HB_COEF4_SZ 12
+#define RO_TBUS_O_MSK 0x000fffff
+#define RO_TBUS_O_I_MSK 0xfff00000
+#define RO_TBUS_O_SFT 0
+#define RO_TBUS_O_HI 19
+#define RO_TBUS_O_SZ 20
+#define RG_LPF4_00_MSK 0x00001fff
+#define RG_LPF4_00_I_MSK 0xffffe000
+#define RG_LPF4_00_SFT 0
+#define RG_LPF4_00_HI 12
+#define RG_LPF4_00_SZ 13
+#define RG_LPF4_01_MSK 0x00001fff
+#define RG_LPF4_01_I_MSK 0xffffe000
+#define RG_LPF4_01_SFT 0
+#define RG_LPF4_01_HI 12
+#define RG_LPF4_01_SZ 13
+#define RG_LPF4_02_MSK 0x00001fff
+#define RG_LPF4_02_I_MSK 0xffffe000
+#define RG_LPF4_02_SFT 0
+#define RG_LPF4_02_HI 12
+#define RG_LPF4_02_SZ 13
+#define RG_LPF4_03_MSK 0x00001fff
+#define RG_LPF4_03_I_MSK 0xffffe000
+#define RG_LPF4_03_SFT 0
+#define RG_LPF4_03_HI 12
+#define RG_LPF4_03_SZ 13
+#define RG_LPF4_04_MSK 0x00001fff
+#define RG_LPF4_04_I_MSK 0xffffe000
+#define RG_LPF4_04_SFT 0
+#define RG_LPF4_04_HI 12
+#define RG_LPF4_04_SZ 13
+#define RG_LPF4_05_MSK 0x00001fff
+#define RG_LPF4_05_I_MSK 0xffffe000
+#define RG_LPF4_05_SFT 0
+#define RG_LPF4_05_HI 12
+#define RG_LPF4_05_SZ 13
+#define RG_LPF4_06_MSK 0x00001fff
+#define RG_LPF4_06_I_MSK 0xffffe000
+#define RG_LPF4_06_SFT 0
+#define RG_LPF4_06_HI 12
+#define RG_LPF4_06_SZ 13
+#define RG_LPF4_07_MSK 0x00001fff
+#define RG_LPF4_07_I_MSK 0xffffe000
+#define RG_LPF4_07_SFT 0
+#define RG_LPF4_07_HI 12
+#define RG_LPF4_07_SZ 13
+#define RG_LPF4_08_MSK 0x00001fff
+#define RG_LPF4_08_I_MSK 0xffffe000
+#define RG_LPF4_08_SFT 0
+#define RG_LPF4_08_HI 12
+#define RG_LPF4_08_SZ 13
+#define RG_LPF4_09_MSK 0x00001fff
+#define RG_LPF4_09_I_MSK 0xffffe000
+#define RG_LPF4_09_SFT 0
+#define RG_LPF4_09_HI 12
+#define RG_LPF4_09_SZ 13
+#define RG_LPF4_10_MSK 0x00001fff
+#define RG_LPF4_10_I_MSK 0xffffe000
+#define RG_LPF4_10_SFT 0
+#define RG_LPF4_10_HI 12
+#define RG_LPF4_10_SZ 13
+#define RG_LPF4_11_MSK 0x00001fff
+#define RG_LPF4_11_I_MSK 0xffffe000
+#define RG_LPF4_11_SFT 0
+#define RG_LPF4_11_HI 12
+#define RG_LPF4_11_SZ 13
+#define RG_LPF4_12_MSK 0x00001fff
+#define RG_LPF4_12_I_MSK 0xffffe000
+#define RG_LPF4_12_SFT 0
+#define RG_LPF4_12_HI 12
+#define RG_LPF4_12_SZ 13
+#define RG_LPF4_13_MSK 0x00001fff
+#define RG_LPF4_13_I_MSK 0xffffe000
+#define RG_LPF4_13_SFT 0
+#define RG_LPF4_13_HI 12
+#define RG_LPF4_13_SZ 13
+#define RG_LPF4_14_MSK 0x00001fff
+#define RG_LPF4_14_I_MSK 0xffffe000
+#define RG_LPF4_14_SFT 0
+#define RG_LPF4_14_HI 12
+#define RG_LPF4_14_SZ 13
+#define RG_LPF4_15_MSK 0x00001fff
+#define RG_LPF4_15_I_MSK 0xffffe000
+#define RG_LPF4_15_SFT 0
+#define RG_LPF4_15_HI 12
+#define RG_LPF4_15_SZ 13
+#define RG_LPF4_16_MSK 0x00001fff
+#define RG_LPF4_16_I_MSK 0xffffe000
+#define RG_LPF4_16_SFT 0
+#define RG_LPF4_16_HI 12
+#define RG_LPF4_16_SZ 13
+#define RG_LPF4_17_MSK 0x00001fff
+#define RG_LPF4_17_I_MSK 0xffffe000
+#define RG_LPF4_17_SFT 0
+#define RG_LPF4_17_HI 12
+#define RG_LPF4_17_SZ 13
+#define RG_LPF4_18_MSK 0x00001fff
+#define RG_LPF4_18_I_MSK 0xffffe000
+#define RG_LPF4_18_SFT 0
+#define RG_LPF4_18_HI 12
+#define RG_LPF4_18_SZ 13
+#define RG_LPF4_19_MSK 0x00001fff
+#define RG_LPF4_19_I_MSK 0xffffe000
+#define RG_LPF4_19_SFT 0
+#define RG_LPF4_19_HI 12
+#define RG_LPF4_19_SZ 13
+#define RG_LPF4_20_MSK 0x00001fff
+#define RG_LPF4_20_I_MSK 0xffffe000
+#define RG_LPF4_20_SFT 0
+#define RG_LPF4_20_HI 12
+#define RG_LPF4_20_SZ 13
+#define RG_LPF4_21_MSK 0x00001fff
+#define RG_LPF4_21_I_MSK 0xffffe000
+#define RG_LPF4_21_SFT 0
+#define RG_LPF4_21_HI 12
+#define RG_LPF4_21_SZ 13
+#define RG_LPF4_22_MSK 0x00001fff
+#define RG_LPF4_22_I_MSK 0xffffe000
+#define RG_LPF4_22_SFT 0
+#define RG_LPF4_22_HI 12
+#define RG_LPF4_22_SZ 13
+#define RG_LPF4_23_MSK 0x00001fff
+#define RG_LPF4_23_I_MSK 0xffffe000
+#define RG_LPF4_23_SFT 0
+#define RG_LPF4_23_HI 12
+#define RG_LPF4_23_SZ 13
+#define RG_LPF4_24_MSK 0x00001fff
+#define RG_LPF4_24_I_MSK 0xffffe000
+#define RG_LPF4_24_SFT 0
+#define RG_LPF4_24_HI 12
+#define RG_LPF4_24_SZ 13
+#define RG_LPF4_25_MSK 0x00001fff
+#define RG_LPF4_25_I_MSK 0xffffe000
+#define RG_LPF4_25_SFT 0
+#define RG_LPF4_25_HI 12
+#define RG_LPF4_25_SZ 13
+#define RG_LPF4_26_MSK 0x00001fff
+#define RG_LPF4_26_I_MSK 0xffffe000
+#define RG_LPF4_26_SFT 0
+#define RG_LPF4_26_HI 12
+#define RG_LPF4_26_SZ 13
+#define RG_LPF4_27_MSK 0x00001fff
+#define RG_LPF4_27_I_MSK 0xffffe000
+#define RG_LPF4_27_SFT 0
+#define RG_LPF4_27_HI 12
+#define RG_LPF4_27_SZ 13
+#define RG_LPF4_28_MSK 0x00001fff
+#define RG_LPF4_28_I_MSK 0xffffe000
+#define RG_LPF4_28_SFT 0
+#define RG_LPF4_28_HI 12
+#define RG_LPF4_28_SZ 13
+#define RG_LPF4_29_MSK 0x00001fff
+#define RG_LPF4_29_I_MSK 0xffffe000
+#define RG_LPF4_29_SFT 0
+#define RG_LPF4_29_HI 12
+#define RG_LPF4_29_SZ 13
+#define RG_LPF4_30_MSK 0x00001fff
+#define RG_LPF4_30_I_MSK 0xffffe000
+#define RG_LPF4_30_SFT 0
+#define RG_LPF4_30_HI 12
+#define RG_LPF4_30_SZ 13
+#define RG_LPF4_31_MSK 0x00001fff
+#define RG_LPF4_31_I_MSK 0xffffe000
+#define RG_LPF4_31_SFT 0
+#define RG_LPF4_31_HI 12
+#define RG_LPF4_31_SZ 13
+#define RG_LPF4_32_MSK 0x00001fff
+#define RG_LPF4_32_I_MSK 0xffffe000
+#define RG_LPF4_32_SFT 0
+#define RG_LPF4_32_HI 12
+#define RG_LPF4_32_SZ 13
+#define RG_LPF4_33_MSK 0x00001fff
+#define RG_LPF4_33_I_MSK 0xffffe000
+#define RG_LPF4_33_SFT 0
+#define RG_LPF4_33_HI 12
+#define RG_LPF4_33_SZ 13
+#define RG_LPF4_34_MSK 0x00001fff
+#define RG_LPF4_34_I_MSK 0xffffe000
+#define RG_LPF4_34_SFT 0
+#define RG_LPF4_34_HI 12
+#define RG_LPF4_34_SZ 13
+#define RG_LPF4_35_MSK 0x00001fff
+#define RG_LPF4_35_I_MSK 0xffffe000
+#define RG_LPF4_35_SFT 0
+#define RG_LPF4_35_HI 12
+#define RG_LPF4_35_SZ 13
+#define RG_LPF4_36_MSK 0x00001fff
+#define RG_LPF4_36_I_MSK 0xffffe000
+#define RG_LPF4_36_SFT 0
+#define RG_LPF4_36_HI 12
+#define RG_LPF4_36_SZ 13
+#define RG_LPF4_37_MSK 0x00001fff
+#define RG_LPF4_37_I_MSK 0xffffe000
+#define RG_LPF4_37_SFT 0
+#define RG_LPF4_37_HI 12
+#define RG_LPF4_37_SZ 13
+#define RG_LPF4_38_MSK 0x00001fff
+#define RG_LPF4_38_I_MSK 0xffffe000
+#define RG_LPF4_38_SFT 0
+#define RG_LPF4_38_HI 12
+#define RG_LPF4_38_SZ 13
+#define RG_LPF4_39_MSK 0x00001fff
+#define RG_LPF4_39_I_MSK 0xffffe000
+#define RG_LPF4_39_SFT 0
+#define RG_LPF4_39_HI 12
+#define RG_LPF4_39_SZ 13
+#define RG_LPF4_40_MSK 0x00001fff
+#define RG_LPF4_40_I_MSK 0xffffe000
+#define RG_LPF4_40_SFT 0
+#define RG_LPF4_40_HI 12
+#define RG_LPF4_40_SZ 13
+#define RG_BP_SMB_MSK 0x00002000
+#define RG_BP_SMB_I_MSK 0xffffdfff
+#define RG_BP_SMB_SFT 13
+#define RG_BP_SMB_HI 13
+#define RG_BP_SMB_SZ 1
+#define RG_EN_SRVC_MSK 0x00004000
+#define RG_EN_SRVC_I_MSK 0xffffbfff
+#define RG_EN_SRVC_SFT 14
+#define RG_EN_SRVC_HI 14
+#define RG_EN_SRVC_SZ 1
+#define RG_DES_SPD_MSK 0x00030000
+#define RG_DES_SPD_I_MSK 0xfffcffff
+#define RG_DES_SPD_SFT 16
+#define RG_DES_SPD_HI 17
+#define RG_DES_SPD_SZ 2
+#define RG_BB_11B_RISE_TIME_MSK 0x000000ff
+#define RG_BB_11B_RISE_TIME_I_MSK 0xffffff00
+#define RG_BB_11B_RISE_TIME_SFT 0
+#define RG_BB_11B_RISE_TIME_HI 7
+#define RG_BB_11B_RISE_TIME_SZ 8
+#define RG_BB_11B_FALL_TIME_MSK 0x0000ff00
+#define RG_BB_11B_FALL_TIME_I_MSK 0xffff00ff
+#define RG_BB_11B_FALL_TIME_SFT 8
+#define RG_BB_11B_FALL_TIME_HI 15
+#define RG_BB_11B_FALL_TIME_SZ 8
+#define RG_WR_TX_EN_CNT_RST_N_MSK 0x00000001
+#define RG_WR_TX_EN_CNT_RST_N_I_MSK 0xfffffffe
+#define RG_WR_TX_EN_CNT_RST_N_SFT 0
+#define RG_WR_TX_EN_CNT_RST_N_HI 0
+#define RG_WR_TX_EN_CNT_RST_N_SZ 1
+#define RO_TX_EN_CNT_MSK 0x0000ffff
+#define RO_TX_EN_CNT_I_MSK 0xffff0000
+#define RO_TX_EN_CNT_SFT 0
+#define RO_TX_EN_CNT_HI 15
+#define RO_TX_EN_CNT_SZ 16
+#define RO_TX_CNT_MSK 0xffffffff
+#define RO_TX_CNT_I_MSK 0x00000000
+#define RO_TX_CNT_SFT 0
+#define RO_TX_CNT_HI 31
+#define RO_TX_CNT_SZ 32
+#define RG_POS_DES_11B_L_EXT_MSK 0x0000000f
+#define RG_POS_DES_11B_L_EXT_I_MSK 0xfffffff0
+#define RG_POS_DES_11B_L_EXT_SFT 0
+#define RG_POS_DES_11B_L_EXT_HI 3
+#define RG_POS_DES_11B_L_EXT_SZ 4
+#define RG_PRE_DES_11B_DLY_MSK 0x000000f0
+#define RG_PRE_DES_11B_DLY_I_MSK 0xffffff0f
+#define RG_PRE_DES_11B_DLY_SFT 4
+#define RG_PRE_DES_11B_DLY_HI 7
+#define RG_PRE_DES_11B_DLY_SZ 4
+#define RG_CNT_CCA_LMT_MSK 0x000f0000
+#define RG_CNT_CCA_LMT_I_MSK 0xfff0ffff
+#define RG_CNT_CCA_LMT_SFT 16
+#define RG_CNT_CCA_LMT_HI 19
+#define RG_CNT_CCA_LMT_SZ 4
+#define RG_BYPASS_DESCRAMBLER_MSK 0x20000000
+#define RG_BYPASS_DESCRAMBLER_I_MSK 0xdfffffff
+#define RG_BYPASS_DESCRAMBLER_SFT 29
+#define RG_BYPASS_DESCRAMBLER_HI 29
+#define RG_BYPASS_DESCRAMBLER_SZ 1
+#define RG_BYPASS_AGC_MSK 0x80000000
+#define RG_BYPASS_AGC_I_MSK 0x7fffffff
+#define RG_BYPASS_AGC_SFT 31
+#define RG_BYPASS_AGC_HI 31
+#define RG_BYPASS_AGC_SZ 1
+#define RG_CCA_BIT_CNT_LMT_RX_MSK 0x000000f0
+#define RG_CCA_BIT_CNT_LMT_RX_I_MSK 0xffffff0f
+#define RG_CCA_BIT_CNT_LMT_RX_SFT 4
+#define RG_CCA_BIT_CNT_LMT_RX_HI 7
+#define RG_CCA_BIT_CNT_LMT_RX_SZ 4
+#define RG_CCA_SCALE_BF_MSK 0x007f0000
+#define RG_CCA_SCALE_BF_I_MSK 0xff80ffff
+#define RG_CCA_SCALE_BF_SFT 16
+#define RG_CCA_SCALE_BF_HI 22
+#define RG_CCA_SCALE_BF_SZ 7
+#define RG_PEAK_IDX_CNT_SEL_MSK 0x30000000
+#define RG_PEAK_IDX_CNT_SEL_I_MSK 0xcfffffff
+#define RG_PEAK_IDX_CNT_SEL_SFT 28
+#define RG_PEAK_IDX_CNT_SEL_HI 29
+#define RG_PEAK_IDX_CNT_SEL_SZ 2
+#define RG_TR_KI_T2_MSK 0x00000007
+#define RG_TR_KI_T2_I_MSK 0xfffffff8
+#define RG_TR_KI_T2_SFT 0
+#define RG_TR_KI_T2_HI 2
+#define RG_TR_KI_T2_SZ 3
+#define RG_TR_KP_T2_MSK 0x00000070
+#define RG_TR_KP_T2_I_MSK 0xffffff8f
+#define RG_TR_KP_T2_SFT 4
+#define RG_TR_KP_T2_HI 6
+#define RG_TR_KP_T2_SZ 3
+#define RG_TR_KI_T1_MSK 0x00000700
+#define RG_TR_KI_T1_I_MSK 0xfffff8ff
+#define RG_TR_KI_T1_SFT 8
+#define RG_TR_KI_T1_HI 10
+#define RG_TR_KI_T1_SZ 3
+#define RG_TR_KP_T1_MSK 0x00007000
+#define RG_TR_KP_T1_I_MSK 0xffff8fff
+#define RG_TR_KP_T1_SFT 12
+#define RG_TR_KP_T1_HI 14
+#define RG_TR_KP_T1_SZ 3
+#define RG_CR_KI_T1_MSK 0x00070000
+#define RG_CR_KI_T1_I_MSK 0xfff8ffff
+#define RG_CR_KI_T1_SFT 16
+#define RG_CR_KI_T1_HI 18
+#define RG_CR_KI_T1_SZ 3
+#define RG_CR_KP_T1_MSK 0x00700000
+#define RG_CR_KP_T1_I_MSK 0xff8fffff
+#define RG_CR_KP_T1_SFT 20
+#define RG_CR_KP_T1_HI 22
+#define RG_CR_KP_T1_SZ 3
+#define RG_CHIP_CNT_SLICER_MSK 0x0000001f
+#define RG_CHIP_CNT_SLICER_I_MSK 0xffffffe0
+#define RG_CHIP_CNT_SLICER_SFT 0
+#define RG_CHIP_CNT_SLICER_HI 4
+#define RG_CHIP_CNT_SLICER_SZ 5
+#define RG_CE_T4_CNT_LMT_MSK 0x0000ff00
+#define RG_CE_T4_CNT_LMT_I_MSK 0xffff00ff
+#define RG_CE_T4_CNT_LMT_SFT 8
+#define RG_CE_T4_CNT_LMT_HI 15
+#define RG_CE_T4_CNT_LMT_SZ 8
+#define RG_CE_T3_CNT_LMT_MSK 0x00ff0000
+#define RG_CE_T3_CNT_LMT_I_MSK 0xff00ffff
+#define RG_CE_T3_CNT_LMT_SFT 16
+#define RG_CE_T3_CNT_LMT_HI 23
+#define RG_CE_T3_CNT_LMT_SZ 8
+#define RG_CE_T2_CNT_LMT_MSK 0xff000000
+#define RG_CE_T2_CNT_LMT_I_MSK 0x00ffffff
+#define RG_CE_T2_CNT_LMT_SFT 24
+#define RG_CE_T2_CNT_LMT_HI 31
+#define RG_CE_T2_CNT_LMT_SZ 8
+#define RG_CE_MU_T1_MSK 0x00000007
+#define RG_CE_MU_T1_I_MSK 0xfffffff8
+#define RG_CE_MU_T1_SFT 0
+#define RG_CE_MU_T1_HI 2
+#define RG_CE_MU_T1_SZ 3
+#define RG_CE_DLY_SEL_MSK 0x003f0000
+#define RG_CE_DLY_SEL_I_MSK 0xffc0ffff
+#define RG_CE_DLY_SEL_SFT 16
+#define RG_CE_DLY_SEL_HI 21
+#define RG_CE_DLY_SEL_SZ 6
+#define RG_CE_MU_T8_MSK 0x00000007
+#define RG_CE_MU_T8_I_MSK 0xfffffff8
+#define RG_CE_MU_T8_SFT 0
+#define RG_CE_MU_T8_HI 2
+#define RG_CE_MU_T8_SZ 3
+#define RG_CE_MU_T7_MSK 0x00000070
+#define RG_CE_MU_T7_I_MSK 0xffffff8f
+#define RG_CE_MU_T7_SFT 4
+#define RG_CE_MU_T7_HI 6
+#define RG_CE_MU_T7_SZ 3
+#define RG_CE_MU_T6_MSK 0x00000700
+#define RG_CE_MU_T6_I_MSK 0xfffff8ff
+#define RG_CE_MU_T6_SFT 8
+#define RG_CE_MU_T6_HI 10
+#define RG_CE_MU_T6_SZ 3
+#define RG_CE_MU_T5_MSK 0x00007000
+#define RG_CE_MU_T5_I_MSK 0xffff8fff
+#define RG_CE_MU_T5_SFT 12
+#define RG_CE_MU_T5_HI 14
+#define RG_CE_MU_T5_SZ 3
+#define RG_CE_MU_T4_MSK 0x00070000
+#define RG_CE_MU_T4_I_MSK 0xfff8ffff
+#define RG_CE_MU_T4_SFT 16
+#define RG_CE_MU_T4_HI 18
+#define RG_CE_MU_T4_SZ 3
+#define RG_CE_MU_T3_MSK 0x00700000
+#define RG_CE_MU_T3_I_MSK 0xff8fffff
+#define RG_CE_MU_T3_SFT 20
+#define RG_CE_MU_T3_HI 22
+#define RG_CE_MU_T3_SZ 3
+#define RG_CE_MU_T2_MSK 0x07000000
+#define RG_CE_MU_T2_I_MSK 0xf8ffffff
+#define RG_CE_MU_T2_SFT 24
+#define RG_CE_MU_T2_HI 26
+#define RG_CE_MU_T2_SZ 3
+#define RG_EQ_MU_FB_T2_MSK 0x0000000f
+#define RG_EQ_MU_FB_T2_I_MSK 0xfffffff0
+#define RG_EQ_MU_FB_T2_SFT 0
+#define RG_EQ_MU_FB_T2_HI 3
+#define RG_EQ_MU_FB_T2_SZ 4
+#define RG_EQ_MU_FF_T2_MSK 0x000000f0
+#define RG_EQ_MU_FF_T2_I_MSK 0xffffff0f
+#define RG_EQ_MU_FF_T2_SFT 4
+#define RG_EQ_MU_FF_T2_HI 7
+#define RG_EQ_MU_FF_T2_SZ 4
+#define RG_EQ_MU_FB_T1_MSK 0x000f0000
+#define RG_EQ_MU_FB_T1_I_MSK 0xfff0ffff
+#define RG_EQ_MU_FB_T1_SFT 16
+#define RG_EQ_MU_FB_T1_HI 19
+#define RG_EQ_MU_FB_T1_SZ 4
+#define RG_EQ_MU_FF_T1_MSK 0x00f00000
+#define RG_EQ_MU_FF_T1_I_MSK 0xff0fffff
+#define RG_EQ_MU_FF_T1_SFT 20
+#define RG_EQ_MU_FF_T1_HI 23
+#define RG_EQ_MU_FF_T1_SZ 4
+#define RG_EQ_MU_FB_T4_MSK 0x0000000f
+#define RG_EQ_MU_FB_T4_I_MSK 0xfffffff0
+#define RG_EQ_MU_FB_T4_SFT 0
+#define RG_EQ_MU_FB_T4_HI 3
+#define RG_EQ_MU_FB_T4_SZ 4
+#define RG_EQ_MU_FF_T4_MSK 0x000000f0
+#define RG_EQ_MU_FF_T4_I_MSK 0xffffff0f
+#define RG_EQ_MU_FF_T4_SFT 4
+#define RG_EQ_MU_FF_T4_HI 7
+#define RG_EQ_MU_FF_T4_SZ 4
+#define RG_EQ_MU_FB_T3_MSK 0x000f0000
+#define RG_EQ_MU_FB_T3_I_MSK 0xfff0ffff
+#define RG_EQ_MU_FB_T3_SFT 16
+#define RG_EQ_MU_FB_T3_HI 19
+#define RG_EQ_MU_FB_T3_SZ 4
+#define RG_EQ_MU_FF_T3_MSK 0x00f00000
+#define RG_EQ_MU_FF_T3_I_MSK 0xff0fffff
+#define RG_EQ_MU_FF_T3_SFT 20
+#define RG_EQ_MU_FF_T3_HI 23
+#define RG_EQ_MU_FF_T3_SZ 4
+#define RG_EQ_KI_T2_MSK 0x00000700
+#define RG_EQ_KI_T2_I_MSK 0xfffff8ff
+#define RG_EQ_KI_T2_SFT 8
+#define RG_EQ_KI_T2_HI 10
+#define RG_EQ_KI_T2_SZ 3
+#define RG_EQ_KP_T2_MSK 0x00007000
+#define RG_EQ_KP_T2_I_MSK 0xffff8fff
+#define RG_EQ_KP_T2_SFT 12
+#define RG_EQ_KP_T2_HI 14
+#define RG_EQ_KP_T2_SZ 3
+#define RG_EQ_KI_T1_MSK 0x00070000
+#define RG_EQ_KI_T1_I_MSK 0xfff8ffff
+#define RG_EQ_KI_T1_SFT 16
+#define RG_EQ_KI_T1_HI 18
+#define RG_EQ_KI_T1_SZ 3
+#define RG_EQ_KP_T1_MSK 0x00700000
+#define RG_EQ_KP_T1_I_MSK 0xff8fffff
+#define RG_EQ_KP_T1_SFT 20
+#define RG_EQ_KP_T1_HI 22
+#define RG_EQ_KP_T1_SZ 3
+#define RG_TR_LPF_RATE_MSK 0x003fffff
+#define RG_TR_LPF_RATE_I_MSK 0xffc00000
+#define RG_TR_LPF_RATE_SFT 0
+#define RG_TR_LPF_RATE_HI 21
+#define RG_TR_LPF_RATE_SZ 22
+#define RG_CE_BIT_CNT_LMT_MSK 0x0000007f
+#define RG_CE_BIT_CNT_LMT_I_MSK 0xffffff80
+#define RG_CE_BIT_CNT_LMT_SFT 0
+#define RG_CE_BIT_CNT_LMT_HI 6
+#define RG_CE_BIT_CNT_LMT_SZ 7
+#define RG_CE_CH_MAIN_SET_MSK 0x00000080
+#define RG_CE_CH_MAIN_SET_I_MSK 0xffffff7f
+#define RG_CE_CH_MAIN_SET_SFT 7
+#define RG_CE_CH_MAIN_SET_HI 7
+#define RG_CE_CH_MAIN_SET_SZ 1
+#define RG_TC_BIT_CNT_LMT_MSK 0x00007f00
+#define RG_TC_BIT_CNT_LMT_I_MSK 0xffff80ff
+#define RG_TC_BIT_CNT_LMT_SFT 8
+#define RG_TC_BIT_CNT_LMT_HI 14
+#define RG_TC_BIT_CNT_LMT_SZ 7
+#define RG_CR_BIT_CNT_LMT_MSK 0x007f0000
+#define RG_CR_BIT_CNT_LMT_I_MSK 0xff80ffff
+#define RG_CR_BIT_CNT_LMT_SFT 16
+#define RG_CR_BIT_CNT_LMT_HI 22
+#define RG_CR_BIT_CNT_LMT_SZ 7
+#define RG_TR_BIT_CNT_LMT_MSK 0x7f000000
+#define RG_TR_BIT_CNT_LMT_I_MSK 0x80ffffff
+#define RG_TR_BIT_CNT_LMT_SFT 24
+#define RG_TR_BIT_CNT_LMT_HI 30
+#define RG_TR_BIT_CNT_LMT_SZ 7
+#define RG_EQ_MAIN_TAP_MAN_MSK 0x00000001
+#define RG_EQ_MAIN_TAP_MAN_I_MSK 0xfffffffe
+#define RG_EQ_MAIN_TAP_MAN_SFT 0
+#define RG_EQ_MAIN_TAP_MAN_HI 0
+#define RG_EQ_MAIN_TAP_MAN_SZ 1
+#define RG_EQ_MAIN_TAP_COEF_MSK 0x07ff0000
+#define RG_EQ_MAIN_TAP_COEF_I_MSK 0xf800ffff
+#define RG_EQ_MAIN_TAP_COEF_SFT 16
+#define RG_EQ_MAIN_TAP_COEF_HI 26
+#define RG_EQ_MAIN_TAP_COEF_SZ 11
+#define RG_PWRON_DLY_TH_11B_MSK 0x000000ff
+#define RG_PWRON_DLY_TH_11B_I_MSK 0xffffff00
+#define RG_PWRON_DLY_TH_11B_SFT 0
+#define RG_PWRON_DLY_TH_11B_HI 7
+#define RG_PWRON_DLY_TH_11B_SZ 8
+#define RG_SFD_BIT_CNT_LMT_MSK 0x00ff0000
+#define RG_SFD_BIT_CNT_LMT_I_MSK 0xff00ffff
+#define RG_SFD_BIT_CNT_LMT_SFT 16
+#define RG_SFD_BIT_CNT_LMT_HI 23
+#define RG_SFD_BIT_CNT_LMT_SZ 8
+#define RG_CCA_PWR_TH_RX_MSK 0x00007fff
+#define RG_CCA_PWR_TH_RX_I_MSK 0xffff8000
+#define RG_CCA_PWR_TH_RX_SFT 0
+#define RG_CCA_PWR_TH_RX_HI 14
+#define RG_CCA_PWR_TH_RX_SZ 15
+#define RG_CCA_PWR_CNT_TH_MSK 0x001f0000
+#define RG_CCA_PWR_CNT_TH_I_MSK 0xffe0ffff
+#define RG_CCA_PWR_CNT_TH_SFT 16
+#define RG_CCA_PWR_CNT_TH_HI 20
+#define RG_CCA_PWR_CNT_TH_SZ 5
+#define B_FREQ_OS_MSK 0x000007ff
+#define B_FREQ_OS_I_MSK 0xfffff800
+#define B_FREQ_OS_SFT 0
+#define B_FREQ_OS_HI 10
+#define B_FREQ_OS_SZ 11
+#define B_SNR_MSK 0x0000007f
+#define B_SNR_I_MSK 0xffffff80
+#define B_SNR_SFT 0
+#define B_SNR_HI 6
+#define B_SNR_SZ 7
+#define B_RCPI_MSK 0x007f0000
+#define B_RCPI_I_MSK 0xff80ffff
+#define B_RCPI_SFT 16
+#define B_RCPI_HI 22
+#define B_RCPI_SZ 7
+#define CRC_CNT_MSK 0x0000ffff
+#define CRC_CNT_I_MSK 0xffff0000
+#define CRC_CNT_SFT 0
+#define CRC_CNT_HI 15
+#define CRC_CNT_SZ 16
+#define SFD_CNT_MSK 0xffff0000
+#define SFD_CNT_I_MSK 0x0000ffff
+#define SFD_CNT_SFT 16
+#define SFD_CNT_HI 31
+#define SFD_CNT_SZ 16
+#define B_PACKET_ERR_CNT_MSK 0x0000ffff
+#define B_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define B_PACKET_ERR_CNT_SFT 0
+#define B_PACKET_ERR_CNT_HI 15
+#define B_PACKET_ERR_CNT_SZ 16
+#define PACKET_ERR_MSK 0x00010000
+#define PACKET_ERR_I_MSK 0xfffeffff
+#define PACKET_ERR_SFT 16
+#define PACKET_ERR_HI 16
+#define PACKET_ERR_SZ 1
+#define B_PACKET_CNT_MSK 0x0000ffff
+#define B_PACKET_CNT_I_MSK 0xffff0000
+#define B_PACKET_CNT_SFT 0
+#define B_PACKET_CNT_HI 15
+#define B_PACKET_CNT_SZ 16
+#define B_CCA_CNT_MSK 0xffff0000
+#define B_CCA_CNT_I_MSK 0x0000ffff
+#define B_CCA_CNT_SFT 16
+#define B_CCA_CNT_HI 31
+#define B_CCA_CNT_SZ 16
+#define B_LENGTH_FIELD_MSK 0x0000ffff
+#define B_LENGTH_FIELD_I_MSK 0xffff0000
+#define B_LENGTH_FIELD_SFT 0
+#define B_LENGTH_FIELD_HI 15
+#define B_LENGTH_FIELD_SZ 16
+#define SFD_FIELD_MSK 0xffff0000
+#define SFD_FIELD_I_MSK 0x0000ffff
+#define SFD_FIELD_SFT 16
+#define SFD_FIELD_HI 31
+#define SFD_FIELD_SZ 16
+#define SIGNAL_FIELD_MSK 0x000000ff
+#define SIGNAL_FIELD_I_MSK 0xffffff00
+#define SIGNAL_FIELD_SFT 0
+#define SIGNAL_FIELD_HI 7
+#define SIGNAL_FIELD_SZ 8
+#define B_SERVICE_FIELD_MSK 0x0000ff00
+#define B_SERVICE_FIELD_I_MSK 0xffff00ff
+#define B_SERVICE_FIELD_SFT 8
+#define B_SERVICE_FIELD_HI 15
+#define B_SERVICE_FIELD_SZ 8
+#define CRC_CORRECT_MSK 0x00010000
+#define CRC_CORRECT_I_MSK 0xfffeffff
+#define CRC_CORRECT_SFT 16
+#define CRC_CORRECT_HI 16
+#define CRC_CORRECT_SZ 1
+#define DEBUG_SEL_MSK 0x0000000f
+#define DEBUG_SEL_I_MSK 0xfffffff0
+#define DEBUG_SEL_SFT 0
+#define DEBUG_SEL_HI 3
+#define DEBUG_SEL_SZ 4
+#define RG_PACKET_STAT_EN_11B_MSK 0x00100000
+#define RG_PACKET_STAT_EN_11B_I_MSK 0xffefffff
+#define RG_PACKET_STAT_EN_11B_SFT 20
+#define RG_PACKET_STAT_EN_11B_HI 20
+#define RG_PACKET_STAT_EN_11B_SZ 1
+#define RG_BIT_REVERSE_MSK 0x00200000
+#define RG_BIT_REVERSE_I_MSK 0xffdfffff
+#define RG_BIT_REVERSE_SFT 21
+#define RG_BIT_REVERSE_HI 21
+#define RG_BIT_REVERSE_SZ 1
+#define RX_PHY_11B_SOFT_RST_N_MSK 0x00000001
+#define RX_PHY_11B_SOFT_RST_N_I_MSK 0xfffffffe
+#define RX_PHY_11B_SOFT_RST_N_SFT 0
+#define RX_PHY_11B_SOFT_RST_N_HI 0
+#define RX_PHY_11B_SOFT_RST_N_SZ 1
+#define RG_CE_BYPASS_TAP_MSK 0x000000f0
+#define RG_CE_BYPASS_TAP_I_MSK 0xffffff0f
+#define RG_CE_BYPASS_TAP_SFT 4
+#define RG_CE_BYPASS_TAP_HI 7
+#define RG_CE_BYPASS_TAP_SZ 4
+#define RG_EQ_BYPASS_FBW_TAP_MSK 0x00000f00
+#define RG_EQ_BYPASS_FBW_TAP_I_MSK 0xfffff0ff
+#define RG_EQ_BYPASS_FBW_TAP_SFT 8
+#define RG_EQ_BYPASS_FBW_TAP_HI 11
+#define RG_EQ_BYPASS_FBW_TAP_SZ 4
+#define RG_BB_11GN_RISE_TIME_MSK 0x000000ff
+#define RG_BB_11GN_RISE_TIME_I_MSK 0xffffff00
+#define RG_BB_11GN_RISE_TIME_SFT 0
+#define RG_BB_11GN_RISE_TIME_HI 7
+#define RG_BB_11GN_RISE_TIME_SZ 8
+#define RG_BB_11GN_FALL_TIME_MSK 0x0000ff00
+#define RG_BB_11GN_FALL_TIME_I_MSK 0xffff00ff
+#define RG_BB_11GN_FALL_TIME_SFT 8
+#define RG_BB_11GN_FALL_TIME_HI 15
+#define RG_BB_11GN_FALL_TIME_SZ 8
+#define RG_HTCARR52_FFT_SCALE_MSK 0x000003ff
+#define RG_HTCARR52_FFT_SCALE_I_MSK 0xfffffc00
+#define RG_HTCARR52_FFT_SCALE_SFT 0
+#define RG_HTCARR52_FFT_SCALE_HI 9
+#define RG_HTCARR52_FFT_SCALE_SZ 10
+#define RG_HTCARR56_FFT_SCALE_MSK 0x003ff000
+#define RG_HTCARR56_FFT_SCALE_I_MSK 0xffc00fff
+#define RG_HTCARR56_FFT_SCALE_SFT 12
+#define RG_HTCARR56_FFT_SCALE_HI 21
+#define RG_HTCARR56_FFT_SCALE_SZ 10
+#define RG_PACKET_STAT_EN_MSK 0x00800000
+#define RG_PACKET_STAT_EN_I_MSK 0xff7fffff
+#define RG_PACKET_STAT_EN_SFT 23
+#define RG_PACKET_STAT_EN_HI 23
+#define RG_PACKET_STAT_EN_SZ 1
+#define RG_SMB_DEF_MSK 0x7f000000
+#define RG_SMB_DEF_I_MSK 0x80ffffff
+#define RG_SMB_DEF_SFT 24
+#define RG_SMB_DEF_HI 30
+#define RG_SMB_DEF_SZ 7
+#define RG_CONTINUOUS_DATA_11GN_MSK 0x80000000
+#define RG_CONTINUOUS_DATA_11GN_I_MSK 0x7fffffff
+#define RG_CONTINUOUS_DATA_11GN_SFT 31
+#define RG_CONTINUOUS_DATA_11GN_HI 31
+#define RG_CONTINUOUS_DATA_11GN_SZ 1
+#define RO_TX_CNT_R_MSK 0xffffffff
+#define RO_TX_CNT_R_I_MSK 0x00000000
+#define RO_TX_CNT_R_SFT 0
+#define RO_TX_CNT_R_HI 31
+#define RO_TX_CNT_R_SZ 32
+#define RO_PACKET_ERR_CNT_MSK 0x0000ffff
+#define RO_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define RO_PACKET_ERR_CNT_SFT 0
+#define RO_PACKET_ERR_CNT_HI 15
+#define RO_PACKET_ERR_CNT_SZ 16
+#define RG_POS_DES_11GN_L_EXT_MSK 0x0000000f
+#define RG_POS_DES_11GN_L_EXT_I_MSK 0xfffffff0
+#define RG_POS_DES_11GN_L_EXT_SFT 0
+#define RG_POS_DES_11GN_L_EXT_HI 3
+#define RG_POS_DES_11GN_L_EXT_SZ 4
+#define RG_PRE_DES_11GN_DLY_MSK 0x000000f0
+#define RG_PRE_DES_11GN_DLY_I_MSK 0xffffff0f
+#define RG_PRE_DES_11GN_DLY_SFT 4
+#define RG_PRE_DES_11GN_DLY_HI 7
+#define RG_PRE_DES_11GN_DLY_SZ 4
+#define RG_TR_LPF_KI_G_T1_MSK 0x0000000f
+#define RG_TR_LPF_KI_G_T1_I_MSK 0xfffffff0
+#define RG_TR_LPF_KI_G_T1_SFT 0
+#define RG_TR_LPF_KI_G_T1_HI 3
+#define RG_TR_LPF_KI_G_T1_SZ 4
+#define RG_TR_LPF_KP_G_T1_MSK 0x000000f0
+#define RG_TR_LPF_KP_G_T1_I_MSK 0xffffff0f
+#define RG_TR_LPF_KP_G_T1_SFT 4
+#define RG_TR_LPF_KP_G_T1_HI 7
+#define RG_TR_LPF_KP_G_T1_SZ 4
+#define RG_TR_CNT_T1_MSK 0x0000ff00
+#define RG_TR_CNT_T1_I_MSK 0xffff00ff
+#define RG_TR_CNT_T1_SFT 8
+#define RG_TR_CNT_T1_HI 15
+#define RG_TR_CNT_T1_SZ 8
+#define RG_TR_LPF_KI_G_T0_MSK 0x000f0000
+#define RG_TR_LPF_KI_G_T0_I_MSK 0xfff0ffff
+#define RG_TR_LPF_KI_G_T0_SFT 16
+#define RG_TR_LPF_KI_G_T0_HI 19
+#define RG_TR_LPF_KI_G_T0_SZ 4
+#define RG_TR_LPF_KP_G_T0_MSK 0x00f00000
+#define RG_TR_LPF_KP_G_T0_I_MSK 0xff0fffff
+#define RG_TR_LPF_KP_G_T0_SFT 20
+#define RG_TR_LPF_KP_G_T0_HI 23
+#define RG_TR_LPF_KP_G_T0_SZ 4
+#define RG_TR_CNT_T0_MSK 0xff000000
+#define RG_TR_CNT_T0_I_MSK 0x00ffffff
+#define RG_TR_CNT_T0_SFT 24
+#define RG_TR_CNT_T0_HI 31
+#define RG_TR_CNT_T0_SZ 8
+#define RG_TR_LPF_KI_G_T2_MSK 0x0000000f
+#define RG_TR_LPF_KI_G_T2_I_MSK 0xfffffff0
+#define RG_TR_LPF_KI_G_T2_SFT 0
+#define RG_TR_LPF_KI_G_T2_HI 3
+#define RG_TR_LPF_KI_G_T2_SZ 4
+#define RG_TR_LPF_KP_G_T2_MSK 0x000000f0
+#define RG_TR_LPF_KP_G_T2_I_MSK 0xffffff0f
+#define RG_TR_LPF_KP_G_T2_SFT 4
+#define RG_TR_LPF_KP_G_T2_HI 7
+#define RG_TR_LPF_KP_G_T2_SZ 4
+#define RG_TR_CNT_T2_MSK 0x0000ff00
+#define RG_TR_CNT_T2_I_MSK 0xffff00ff
+#define RG_TR_CNT_T2_SFT 8
+#define RG_TR_CNT_T2_HI 15
+#define RG_TR_CNT_T2_SZ 8
+#define RG_TR_LPF_KI_G_MSK 0x0000000f
+#define RG_TR_LPF_KI_G_I_MSK 0xfffffff0
+#define RG_TR_LPF_KI_G_SFT 0
+#define RG_TR_LPF_KI_G_HI 3
+#define RG_TR_LPF_KI_G_SZ 4
+#define RG_TR_LPF_KP_G_MSK 0x000000f0
+#define RG_TR_LPF_KP_G_I_MSK 0xffffff0f
+#define RG_TR_LPF_KP_G_SFT 4
+#define RG_TR_LPF_KP_G_HI 7
+#define RG_TR_LPF_KP_G_SZ 4
+#define RG_TR_LPF_RATE_G_MSK 0x3fffff00
+#define RG_TR_LPF_RATE_G_I_MSK 0xc00000ff
+#define RG_TR_LPF_RATE_G_SFT 8
+#define RG_TR_LPF_RATE_G_HI 29
+#define RG_TR_LPF_RATE_G_SZ 22
+#define RG_CR_LPF_KI_G_MSK 0x00000007
+#define RG_CR_LPF_KI_G_I_MSK 0xfffffff8
+#define RG_CR_LPF_KI_G_SFT 0
+#define RG_CR_LPF_KI_G_HI 2
+#define RG_CR_LPF_KI_G_SZ 3
+#define RG_SYM_BOUND_CNT_MSK 0x00007f00
+#define RG_SYM_BOUND_CNT_I_MSK 0xffff80ff
+#define RG_SYM_BOUND_CNT_SFT 8
+#define RG_SYM_BOUND_CNT_HI 14
+#define RG_SYM_BOUND_CNT_SZ 7
+#define RG_XSCOR32_RATIO_MSK 0x007f0000
+#define RG_XSCOR32_RATIO_I_MSK 0xff80ffff
+#define RG_XSCOR32_RATIO_SFT 16
+#define RG_XSCOR32_RATIO_HI 22
+#define RG_XSCOR32_RATIO_SZ 7
+#define RG_ATCOR64_CNT_LMT_MSK 0x7f000000
+#define RG_ATCOR64_CNT_LMT_I_MSK 0x80ffffff
+#define RG_ATCOR64_CNT_LMT_SFT 24
+#define RG_ATCOR64_CNT_LMT_HI 30
+#define RG_ATCOR64_CNT_LMT_SZ 7
+#define RG_ATCOR16_CNT_LMT2_MSK 0x00007f00
+#define RG_ATCOR16_CNT_LMT2_I_MSK 0xffff80ff
+#define RG_ATCOR16_CNT_LMT2_SFT 8
+#define RG_ATCOR16_CNT_LMT2_HI 14
+#define RG_ATCOR16_CNT_LMT2_SZ 7
+#define RG_ATCOR16_CNT_LMT1_MSK 0x007f0000
+#define RG_ATCOR16_CNT_LMT1_I_MSK 0xff80ffff
+#define RG_ATCOR16_CNT_LMT1_SFT 16
+#define RG_ATCOR16_CNT_LMT1_HI 22
+#define RG_ATCOR16_CNT_LMT1_SZ 7
+#define RG_ATCOR16_RATIO_SB_MSK 0x7f000000
+#define RG_ATCOR16_RATIO_SB_I_MSK 0x80ffffff
+#define RG_ATCOR16_RATIO_SB_SFT 24
+#define RG_ATCOR16_RATIO_SB_HI 30
+#define RG_ATCOR16_RATIO_SB_SZ 7
+#define RG_XSCOR64_CNT_LMT2_MSK 0x007f0000
+#define RG_XSCOR64_CNT_LMT2_I_MSK 0xff80ffff
+#define RG_XSCOR64_CNT_LMT2_SFT 16
+#define RG_XSCOR64_CNT_LMT2_HI 22
+#define RG_XSCOR64_CNT_LMT2_SZ 7
+#define RG_XSCOR64_CNT_LMT1_MSK 0x7f000000
+#define RG_XSCOR64_CNT_LMT1_I_MSK 0x80ffffff
+#define RG_XSCOR64_CNT_LMT1_SFT 24
+#define RG_XSCOR64_CNT_LMT1_HI 30
+#define RG_XSCOR64_CNT_LMT1_SZ 7
+#define RG_RX_FFT_SCALE_MSK 0x000003ff
+#define RG_RX_FFT_SCALE_I_MSK 0xfffffc00
+#define RG_RX_FFT_SCALE_SFT 0
+#define RG_RX_FFT_SCALE_HI 9
+#define RG_RX_FFT_SCALE_SZ 10
+#define RG_VITERBI_AB_SWAP_MSK 0x00010000
+#define RG_VITERBI_AB_SWAP_I_MSK 0xfffeffff
+#define RG_VITERBI_AB_SWAP_SFT 16
+#define RG_VITERBI_AB_SWAP_HI 16
+#define RG_VITERBI_AB_SWAP_SZ 1
+#define RG_ATCOR16_CNT_TH_MSK 0x0f000000
+#define RG_ATCOR16_CNT_TH_I_MSK 0xf0ffffff
+#define RG_ATCOR16_CNT_TH_SFT 24
+#define RG_ATCOR16_CNT_TH_HI 27
+#define RG_ATCOR16_CNT_TH_SZ 4
+#define RG_NORMSQUARE_LOW_SNR_7_MSK 0x000000ff
+#define RG_NORMSQUARE_LOW_SNR_7_I_MSK 0xffffff00
+#define RG_NORMSQUARE_LOW_SNR_7_SFT 0
+#define RG_NORMSQUARE_LOW_SNR_7_HI 7
+#define RG_NORMSQUARE_LOW_SNR_7_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_6_MSK 0x0000ff00
+#define RG_NORMSQUARE_LOW_SNR_6_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_LOW_SNR_6_SFT 8
+#define RG_NORMSQUARE_LOW_SNR_6_HI 15
+#define RG_NORMSQUARE_LOW_SNR_6_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_5_MSK 0x00ff0000
+#define RG_NORMSQUARE_LOW_SNR_5_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_LOW_SNR_5_SFT 16
+#define RG_NORMSQUARE_LOW_SNR_5_HI 23
+#define RG_NORMSQUARE_LOW_SNR_5_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_4_MSK 0xff000000
+#define RG_NORMSQUARE_LOW_SNR_4_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_LOW_SNR_4_SFT 24
+#define RG_NORMSQUARE_LOW_SNR_4_HI 31
+#define RG_NORMSQUARE_LOW_SNR_4_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_8_MSK 0xff000000
+#define RG_NORMSQUARE_LOW_SNR_8_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_LOW_SNR_8_SFT 24
+#define RG_NORMSQUARE_LOW_SNR_8_HI 31
+#define RG_NORMSQUARE_LOW_SNR_8_SZ 8
+#define RG_NORMSQUARE_SNR_3_MSK 0x000000ff
+#define RG_NORMSQUARE_SNR_3_I_MSK 0xffffff00
+#define RG_NORMSQUARE_SNR_3_SFT 0
+#define RG_NORMSQUARE_SNR_3_HI 7
+#define RG_NORMSQUARE_SNR_3_SZ 8
+#define RG_NORMSQUARE_SNR_2_MSK 0x0000ff00
+#define RG_NORMSQUARE_SNR_2_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_SNR_2_SFT 8
+#define RG_NORMSQUARE_SNR_2_HI 15
+#define RG_NORMSQUARE_SNR_2_SZ 8
+#define RG_NORMSQUARE_SNR_1_MSK 0x00ff0000
+#define RG_NORMSQUARE_SNR_1_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_SNR_1_SFT 16
+#define RG_NORMSQUARE_SNR_1_HI 23
+#define RG_NORMSQUARE_SNR_1_SZ 8
+#define RG_NORMSQUARE_SNR_0_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_0_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_0_SFT 24
+#define RG_NORMSQUARE_SNR_0_HI 31
+#define RG_NORMSQUARE_SNR_0_SZ 8
+#define RG_NORMSQUARE_SNR_7_MSK 0x000000ff
+#define RG_NORMSQUARE_SNR_7_I_MSK 0xffffff00
+#define RG_NORMSQUARE_SNR_7_SFT 0
+#define RG_NORMSQUARE_SNR_7_HI 7
+#define RG_NORMSQUARE_SNR_7_SZ 8
+#define RG_NORMSQUARE_SNR_6_MSK 0x0000ff00
+#define RG_NORMSQUARE_SNR_6_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_SNR_6_SFT 8
+#define RG_NORMSQUARE_SNR_6_HI 15
+#define RG_NORMSQUARE_SNR_6_SZ 8
+#define RG_NORMSQUARE_SNR_5_MSK 0x00ff0000
+#define RG_NORMSQUARE_SNR_5_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_SNR_5_SFT 16
+#define RG_NORMSQUARE_SNR_5_HI 23
+#define RG_NORMSQUARE_SNR_5_SZ 8
+#define RG_NORMSQUARE_SNR_4_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_4_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_4_SFT 24
+#define RG_NORMSQUARE_SNR_4_HI 31
+#define RG_NORMSQUARE_SNR_4_SZ 8
+#define RG_NORMSQUARE_SNR_8_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_8_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_8_SFT 24
+#define RG_NORMSQUARE_SNR_8_HI 31
+#define RG_NORMSQUARE_SNR_8_SZ 8
+#define RG_SNR_TH_64QAM_MSK 0x0000007f
+#define RG_SNR_TH_64QAM_I_MSK 0xffffff80
+#define RG_SNR_TH_64QAM_SFT 0
+#define RG_SNR_TH_64QAM_HI 6
+#define RG_SNR_TH_64QAM_SZ 7
+#define RG_SNR_TH_16QAM_MSK 0x00007f00
+#define RG_SNR_TH_16QAM_I_MSK 0xffff80ff
+#define RG_SNR_TH_16QAM_SFT 8
+#define RG_SNR_TH_16QAM_HI 14
+#define RG_SNR_TH_16QAM_SZ 7
+#define RG_ATCOR16_CNT_PLUS_LMT2_MSK 0x0000007f
+#define RG_ATCOR16_CNT_PLUS_LMT2_I_MSK 0xffffff80
+#define RG_ATCOR16_CNT_PLUS_LMT2_SFT 0
+#define RG_ATCOR16_CNT_PLUS_LMT2_HI 6
+#define RG_ATCOR16_CNT_PLUS_LMT2_SZ 7
+#define RG_ATCOR16_CNT_PLUS_LMT1_MSK 0x00007f00
+#define RG_ATCOR16_CNT_PLUS_LMT1_I_MSK 0xffff80ff
+#define RG_ATCOR16_CNT_PLUS_LMT1_SFT 8
+#define RG_ATCOR16_CNT_PLUS_LMT1_HI 14
+#define RG_ATCOR16_CNT_PLUS_LMT1_SZ 7
+#define RG_SYM_BOUND_METHOD_MSK 0x00030000
+#define RG_SYM_BOUND_METHOD_I_MSK 0xfffcffff
+#define RG_SYM_BOUND_METHOD_SFT 16
+#define RG_SYM_BOUND_METHOD_HI 17
+#define RG_SYM_BOUND_METHOD_SZ 2
+#define RG_PWRON_DLY_TH_11GN_MSK 0x000000ff
+#define RG_PWRON_DLY_TH_11GN_I_MSK 0xffffff00
+#define RG_PWRON_DLY_TH_11GN_SFT 0
+#define RG_PWRON_DLY_TH_11GN_HI 7
+#define RG_PWRON_DLY_TH_11GN_SZ 8
+#define RG_SB_START_CNT_MSK 0x00007f00
+#define RG_SB_START_CNT_I_MSK 0xffff80ff
+#define RG_SB_START_CNT_SFT 8
+#define RG_SB_START_CNT_HI 14
+#define RG_SB_START_CNT_SZ 7
+#define RG_POW16_CNT_TH_MSK 0x000000f0
+#define RG_POW16_CNT_TH_I_MSK 0xffffff0f
+#define RG_POW16_CNT_TH_SFT 4
+#define RG_POW16_CNT_TH_HI 7
+#define RG_POW16_CNT_TH_SZ 4
+#define RG_POW16_SHORT_CNT_LMT_MSK 0x00000700
+#define RG_POW16_SHORT_CNT_LMT_I_MSK 0xfffff8ff
+#define RG_POW16_SHORT_CNT_LMT_SFT 8
+#define RG_POW16_SHORT_CNT_LMT_HI 10
+#define RG_POW16_SHORT_CNT_LMT_SZ 3
+#define RG_POW16_TH_L_MSK 0x7f000000
+#define RG_POW16_TH_L_I_MSK 0x80ffffff
+#define RG_POW16_TH_L_SFT 24
+#define RG_POW16_TH_L_HI 30
+#define RG_POW16_TH_L_SZ 7
+#define RG_XSCOR16_SHORT_CNT_LMT_MSK 0x00000007
+#define RG_XSCOR16_SHORT_CNT_LMT_I_MSK 0xfffffff8
+#define RG_XSCOR16_SHORT_CNT_LMT_SFT 0
+#define RG_XSCOR16_SHORT_CNT_LMT_HI 2
+#define RG_XSCOR16_SHORT_CNT_LMT_SZ 3
+#define RG_XSCOR16_RATIO_MSK 0x00007f00
+#define RG_XSCOR16_RATIO_I_MSK 0xffff80ff
+#define RG_XSCOR16_RATIO_SFT 8
+#define RG_XSCOR16_RATIO_HI 14
+#define RG_XSCOR16_RATIO_SZ 7
+#define RG_ATCOR16_SHORT_CNT_LMT_MSK 0x00070000
+#define RG_ATCOR16_SHORT_CNT_LMT_I_MSK 0xfff8ffff
+#define RG_ATCOR16_SHORT_CNT_LMT_SFT 16
+#define RG_ATCOR16_SHORT_CNT_LMT_HI 18
+#define RG_ATCOR16_SHORT_CNT_LMT_SZ 3
+#define RG_ATCOR16_RATIO_CCD_MSK 0x7f000000
+#define RG_ATCOR16_RATIO_CCD_I_MSK 0x80ffffff
+#define RG_ATCOR16_RATIO_CCD_SFT 24
+#define RG_ATCOR16_RATIO_CCD_HI 30
+#define RG_ATCOR16_RATIO_CCD_SZ 7
+#define RG_ATCOR64_ACC_LMT_MSK 0x0000007f
+#define RG_ATCOR64_ACC_LMT_I_MSK 0xffffff80
+#define RG_ATCOR64_ACC_LMT_SFT 0
+#define RG_ATCOR64_ACC_LMT_HI 6
+#define RG_ATCOR64_ACC_LMT_SZ 7
+#define RG_ATCOR16_SHORT_CNT_LMT2_MSK 0x00070000
+#define RG_ATCOR16_SHORT_CNT_LMT2_I_MSK 0xfff8ffff
+#define RG_ATCOR16_SHORT_CNT_LMT2_SFT 16
+#define RG_ATCOR16_SHORT_CNT_LMT2_HI 18
+#define RG_ATCOR16_SHORT_CNT_LMT2_SZ 3
+#define RG_VITERBI_TB_BITS_MSK 0xff000000
+#define RG_VITERBI_TB_BITS_I_MSK 0x00ffffff
+#define RG_VITERBI_TB_BITS_SFT 24
+#define RG_VITERBI_TB_BITS_HI 31
+#define RG_VITERBI_TB_BITS_SZ 8
+#define RG_CR_CNT_UPDATE_MSK 0x000000ff
+#define RG_CR_CNT_UPDATE_I_MSK 0xffffff00
+#define RG_CR_CNT_UPDATE_SFT 0
+#define RG_CR_CNT_UPDATE_HI 7
+#define RG_CR_CNT_UPDATE_SZ 8
+#define RG_TR_CNT_UPDATE_MSK 0x00ff0000
+#define RG_TR_CNT_UPDATE_I_MSK 0xff00ffff
+#define RG_TR_CNT_UPDATE_SFT 16
+#define RG_TR_CNT_UPDATE_HI 23
+#define RG_TR_CNT_UPDATE_SZ 8
+#define RG_BYPASS_CPE_MA_MSK 0x00000010
+#define RG_BYPASS_CPE_MA_I_MSK 0xffffffef
+#define RG_BYPASS_CPE_MA_SFT 4
+#define RG_BYPASS_CPE_MA_HI 4
+#define RG_BYPASS_CPE_MA_SZ 1
+#define RG_PILOT_BNDRY_SHIFT_MSK 0x00000700
+#define RG_PILOT_BNDRY_SHIFT_I_MSK 0xfffff8ff
+#define RG_PILOT_BNDRY_SHIFT_SFT 8
+#define RG_PILOT_BNDRY_SHIFT_HI 10
+#define RG_PILOT_BNDRY_SHIFT_SZ 3
+#define RG_EQ_SHORT_GI_SHIFT_MSK 0x00007000
+#define RG_EQ_SHORT_GI_SHIFT_I_MSK 0xffff8fff
+#define RG_EQ_SHORT_GI_SHIFT_SFT 12
+#define RG_EQ_SHORT_GI_SHIFT_HI 14
+#define RG_EQ_SHORT_GI_SHIFT_SZ 3
+#define RG_FFT_WDW_SHORT_SHIFT_MSK 0x00070000
+#define RG_FFT_WDW_SHORT_SHIFT_I_MSK 0xfff8ffff
+#define RG_FFT_WDW_SHORT_SHIFT_SFT 16
+#define RG_FFT_WDW_SHORT_SHIFT_HI 18
+#define RG_FFT_WDW_SHORT_SHIFT_SZ 3
+#define RG_CHSMTH_COEF_MSK 0x00030000
+#define RG_CHSMTH_COEF_I_MSK 0xfffcffff
+#define RG_CHSMTH_COEF_SFT 16
+#define RG_CHSMTH_COEF_HI 17
+#define RG_CHSMTH_COEF_SZ 2
+#define RG_CHSMTH_EN_MSK 0x00040000
+#define RG_CHSMTH_EN_I_MSK 0xfffbffff
+#define RG_CHSMTH_EN_SFT 18
+#define RG_CHSMTH_EN_HI 18
+#define RG_CHSMTH_EN_SZ 1
+#define RG_CHEST_DD_FACTOR_MSK 0x07000000
+#define RG_CHEST_DD_FACTOR_I_MSK 0xf8ffffff
+#define RG_CHEST_DD_FACTOR_SFT 24
+#define RG_CHEST_DD_FACTOR_HI 26
+#define RG_CHEST_DD_FACTOR_SZ 3
+#define RG_CH_UPDATE_MSK 0x80000000
+#define RG_CH_UPDATE_I_MSK 0x7fffffff
+#define RG_CH_UPDATE_SFT 31
+#define RG_CH_UPDATE_HI 31
+#define RG_CH_UPDATE_SZ 1
+#define RG_FMT_DET_MM_TH_MSK 0x000000ff
+#define RG_FMT_DET_MM_TH_I_MSK 0xffffff00
+#define RG_FMT_DET_MM_TH_SFT 0
+#define RG_FMT_DET_MM_TH_HI 7
+#define RG_FMT_DET_MM_TH_SZ 8
+#define RG_FMT_DET_GF_TH_MSK 0x0000ff00
+#define RG_FMT_DET_GF_TH_I_MSK 0xffff00ff
+#define RG_FMT_DET_GF_TH_SFT 8
+#define RG_FMT_DET_GF_TH_HI 15
+#define RG_FMT_DET_GF_TH_SZ 8
+#define RG_DO_NOT_CHECK_L_RATE_MSK 0x02000000
+#define RG_DO_NOT_CHECK_L_RATE_I_MSK 0xfdffffff
+#define RG_DO_NOT_CHECK_L_RATE_SFT 25
+#define RG_DO_NOT_CHECK_L_RATE_HI 25
+#define RG_DO_NOT_CHECK_L_RATE_SZ 1
+#define RG_FMT_DET_LENGTH_TH_MSK 0x0000ffff
+#define RG_FMT_DET_LENGTH_TH_I_MSK 0xffff0000
+#define RG_FMT_DET_LENGTH_TH_SFT 0
+#define RG_FMT_DET_LENGTH_TH_HI 15
+#define RG_FMT_DET_LENGTH_TH_SZ 16
+#define RG_L_LENGTH_MAX_MSK 0xffff0000
+#define RG_L_LENGTH_MAX_I_MSK 0x0000ffff
+#define RG_L_LENGTH_MAX_SFT 16
+#define RG_L_LENGTH_MAX_HI 31
+#define RG_L_LENGTH_MAX_SZ 16
+#define RG_TX_TIME_EXT_MSK 0x000000ff
+#define RG_TX_TIME_EXT_I_MSK 0xffffff00
+#define RG_TX_TIME_EXT_SFT 0
+#define RG_TX_TIME_EXT_HI 7
+#define RG_TX_TIME_EXT_SZ 8
+#define RG_MAC_DES_SPACE_MSK 0x00f00000
+#define RG_MAC_DES_SPACE_I_MSK 0xff0fffff
+#define RG_MAC_DES_SPACE_SFT 20
+#define RG_MAC_DES_SPACE_HI 23
+#define RG_MAC_DES_SPACE_SZ 4
+#define RG_TR_LPF_STBC_GF_KI_G_MSK 0x0000000f
+#define RG_TR_LPF_STBC_GF_KI_G_I_MSK 0xfffffff0
+#define RG_TR_LPF_STBC_GF_KI_G_SFT 0
+#define RG_TR_LPF_STBC_GF_KI_G_HI 3
+#define RG_TR_LPF_STBC_GF_KI_G_SZ 4
+#define RG_TR_LPF_STBC_GF_KP_G_MSK 0x000000f0
+#define RG_TR_LPF_STBC_GF_KP_G_I_MSK 0xffffff0f
+#define RG_TR_LPF_STBC_GF_KP_G_SFT 4
+#define RG_TR_LPF_STBC_GF_KP_G_HI 7
+#define RG_TR_LPF_STBC_GF_KP_G_SZ 4
+#define RG_TR_LPF_STBC_MF_KI_G_MSK 0x00000f00
+#define RG_TR_LPF_STBC_MF_KI_G_I_MSK 0xfffff0ff
+#define RG_TR_LPF_STBC_MF_KI_G_SFT 8
+#define RG_TR_LPF_STBC_MF_KI_G_HI 11
+#define RG_TR_LPF_STBC_MF_KI_G_SZ 4
+#define RG_TR_LPF_STBC_MF_KP_G_MSK 0x0000f000
+#define RG_TR_LPF_STBC_MF_KP_G_I_MSK 0xffff0fff
+#define RG_TR_LPF_STBC_MF_KP_G_SFT 12
+#define RG_TR_LPF_STBC_MF_KP_G_HI 15
+#define RG_TR_LPF_STBC_MF_KP_G_SZ 4
+#define RG_MODE_REG_IN_80_MSK 0x0001ffff
+#define RG_MODE_REG_IN_80_I_MSK 0xfffe0000
+#define RG_MODE_REG_IN_80_SFT 0
+#define RG_MODE_REG_IN_80_HI 16
+#define RG_MODE_REG_IN_80_SZ 17
+#define RG_PARALLEL_DR_80_MSK 0x00100000
+#define RG_PARALLEL_DR_80_I_MSK 0xffefffff
+#define RG_PARALLEL_DR_80_SFT 20
+#define RG_PARALLEL_DR_80_HI 20
+#define RG_PARALLEL_DR_80_SZ 1
+#define RG_MBRUN_80_MSK 0x01000000
+#define RG_MBRUN_80_I_MSK 0xfeffffff
+#define RG_MBRUN_80_SFT 24
+#define RG_MBRUN_80_HI 24
+#define RG_MBRUN_80_SZ 1
+#define RG_SHIFT_DR_80_MSK 0x10000000
+#define RG_SHIFT_DR_80_I_MSK 0xefffffff
+#define RG_SHIFT_DR_80_SFT 28
+#define RG_SHIFT_DR_80_HI 28
+#define RG_SHIFT_DR_80_SZ 1
+#define RG_MODE_REG_SI_80_MSK 0x20000000
+#define RG_MODE_REG_SI_80_I_MSK 0xdfffffff
+#define RG_MODE_REG_SI_80_SFT 29
+#define RG_MODE_REG_SI_80_HI 29
+#define RG_MODE_REG_SI_80_SZ 1
+#define RG_SIMULATION_MODE_80_MSK 0x40000000
+#define RG_SIMULATION_MODE_80_I_MSK 0xbfffffff
+#define RG_SIMULATION_MODE_80_SFT 30
+#define RG_SIMULATION_MODE_80_HI 30
+#define RG_SIMULATION_MODE_80_SZ 1
+#define RG_DBIST_MODE_80_MSK 0x80000000
+#define RG_DBIST_MODE_80_I_MSK 0x7fffffff
+#define RG_DBIST_MODE_80_SFT 31
+#define RG_DBIST_MODE_80_HI 31
+#define RG_DBIST_MODE_80_SZ 1
+#define RG_MODE_REG_IN_64_MSK 0x0000ffff
+#define RG_MODE_REG_IN_64_I_MSK 0xffff0000
+#define RG_MODE_REG_IN_64_SFT 0
+#define RG_MODE_REG_IN_64_HI 15
+#define RG_MODE_REG_IN_64_SZ 16
+#define RG_PARALLEL_DR_64_MSK 0x00100000
+#define RG_PARALLEL_DR_64_I_MSK 0xffefffff
+#define RG_PARALLEL_DR_64_SFT 20
+#define RG_PARALLEL_DR_64_HI 20
+#define RG_PARALLEL_DR_64_SZ 1
+#define RG_MBRUN_64_MSK 0x01000000
+#define RG_MBRUN_64_I_MSK 0xfeffffff
+#define RG_MBRUN_64_SFT 24
+#define RG_MBRUN_64_HI 24
+#define RG_MBRUN_64_SZ 1
+#define RG_SHIFT_DR_64_MSK 0x10000000
+#define RG_SHIFT_DR_64_I_MSK 0xefffffff
+#define RG_SHIFT_DR_64_SFT 28
+#define RG_SHIFT_DR_64_HI 28
+#define RG_SHIFT_DR_64_SZ 1
+#define RG_MODE_REG_SI_64_MSK 0x20000000
+#define RG_MODE_REG_SI_64_I_MSK 0xdfffffff
+#define RG_MODE_REG_SI_64_SFT 29
+#define RG_MODE_REG_SI_64_HI 29
+#define RG_MODE_REG_SI_64_SZ 1
+#define RG_SIMULATION_MODE_64_MSK 0x40000000
+#define RG_SIMULATION_MODE_64_I_MSK 0xbfffffff
+#define RG_SIMULATION_MODE_64_SFT 30
+#define RG_SIMULATION_MODE_64_HI 30
+#define RG_SIMULATION_MODE_64_SZ 1
+#define RG_DBIST_MODE_64_MSK 0x80000000
+#define RG_DBIST_MODE_64_I_MSK 0x7fffffff
+#define RG_DBIST_MODE_64_SFT 31
+#define RG_DBIST_MODE_64_HI 31
+#define RG_DBIST_MODE_64_SZ 1
+#define RO_MODE_REG_OUT_80_MSK 0x0001ffff
+#define RO_MODE_REG_OUT_80_I_MSK 0xfffe0000
+#define RO_MODE_REG_OUT_80_SFT 0
+#define RO_MODE_REG_OUT_80_HI 16
+#define RO_MODE_REG_OUT_80_SZ 17
+#define RO_MODE_REG_SO_80_MSK 0x01000000
+#define RO_MODE_REG_SO_80_I_MSK 0xfeffffff
+#define RO_MODE_REG_SO_80_SFT 24
+#define RO_MODE_REG_SO_80_HI 24
+#define RO_MODE_REG_SO_80_SZ 1
+#define RO_MONITOR_BUS_80_MSK 0x003fffff
+#define RO_MONITOR_BUS_80_I_MSK 0xffc00000
+#define RO_MONITOR_BUS_80_SFT 0
+#define RO_MONITOR_BUS_80_HI 21
+#define RO_MONITOR_BUS_80_SZ 22
+#define RO_MODE_REG_OUT_64_MSK 0x0000ffff
+#define RO_MODE_REG_OUT_64_I_MSK 0xffff0000
+#define RO_MODE_REG_OUT_64_SFT 0
+#define RO_MODE_REG_OUT_64_HI 15
+#define RO_MODE_REG_OUT_64_SZ 16
+#define RO_MODE_REG_SO_64_MSK 0x01000000
+#define RO_MODE_REG_SO_64_I_MSK 0xfeffffff
+#define RO_MODE_REG_SO_64_SFT 24
+#define RO_MODE_REG_SO_64_HI 24
+#define RO_MODE_REG_SO_64_SZ 1
+#define RO_MONITOR_BUS_64_MSK 0x0007ffff
+#define RO_MONITOR_BUS_64_I_MSK 0xfff80000
+#define RO_MONITOR_BUS_64_SFT 0
+#define RO_MONITOR_BUS_64_HI 18
+#define RO_MONITOR_BUS_64_SZ 19
+#define RO_SPECTRUM_DATA_MSK 0xffffffff
+#define RO_SPECTRUM_DATA_I_MSK 0x00000000
+#define RO_SPECTRUM_DATA_SFT 0
+#define RO_SPECTRUM_DATA_HI 31
+#define RO_SPECTRUM_DATA_SZ 32
+#define GN_SNR_MSK 0x0000007f
+#define GN_SNR_I_MSK 0xffffff80
+#define GN_SNR_SFT 0
+#define GN_SNR_HI 6
+#define GN_SNR_SZ 7
+#define GN_NOISE_PWR_MSK 0x00007f00
+#define GN_NOISE_PWR_I_MSK 0xffff80ff
+#define GN_NOISE_PWR_SFT 8
+#define GN_NOISE_PWR_HI 14
+#define GN_NOISE_PWR_SZ 7
+#define GN_RCPI_MSK 0x007f0000
+#define GN_RCPI_I_MSK 0xff80ffff
+#define GN_RCPI_SFT 16
+#define GN_RCPI_HI 22
+#define GN_RCPI_SZ 7
+#define GN_SIGNAL_PWR_MSK 0x7f000000
+#define GN_SIGNAL_PWR_I_MSK 0x80ffffff
+#define GN_SIGNAL_PWR_SFT 24
+#define GN_SIGNAL_PWR_HI 30
+#define GN_SIGNAL_PWR_SZ 7
+#define RO_FREQ_OS_LTS_MSK 0x00007fff
+#define RO_FREQ_OS_LTS_I_MSK 0xffff8000
+#define RO_FREQ_OS_LTS_SFT 0
+#define RO_FREQ_OS_LTS_HI 14
+#define RO_FREQ_OS_LTS_SZ 15
+#define CSTATE_MSK 0x000f0000
+#define CSTATE_I_MSK 0xfff0ffff
+#define CSTATE_SFT 16
+#define CSTATE_HI 19
+#define CSTATE_SZ 4
+#define SIGNAL_FIELD0_MSK 0x00ffffff
+#define SIGNAL_FIELD0_I_MSK 0xff000000
+#define SIGNAL_FIELD0_SFT 0
+#define SIGNAL_FIELD0_HI 23
+#define SIGNAL_FIELD0_SZ 24
+#define SIGNAL_FIELD1_MSK 0x00ffffff
+#define SIGNAL_FIELD1_I_MSK 0xff000000
+#define SIGNAL_FIELD1_SFT 0
+#define SIGNAL_FIELD1_HI 23
+#define SIGNAL_FIELD1_SZ 24
+#define GN_PACKET_ERR_CNT_MSK 0x0000ffff
+#define GN_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define GN_PACKET_ERR_CNT_SFT 0
+#define GN_PACKET_ERR_CNT_HI 15
+#define GN_PACKET_ERR_CNT_SZ 16
+#define GN_PACKET_CNT_MSK 0x0000ffff
+#define GN_PACKET_CNT_I_MSK 0xffff0000
+#define GN_PACKET_CNT_SFT 0
+#define GN_PACKET_CNT_HI 15
+#define GN_PACKET_CNT_SZ 16
+#define GN_CCA_CNT_MSK 0xffff0000
+#define GN_CCA_CNT_I_MSK 0x0000ffff
+#define GN_CCA_CNT_SFT 16
+#define GN_CCA_CNT_HI 31
+#define GN_CCA_CNT_SZ 16
+#define GN_LENGTH_FIELD_MSK 0x0000ffff
+#define GN_LENGTH_FIELD_I_MSK 0xffff0000
+#define GN_LENGTH_FIELD_SFT 0
+#define GN_LENGTH_FIELD_HI 15
+#define GN_LENGTH_FIELD_SZ 16
+#define GN_SERVICE_FIELD_MSK 0xffff0000
+#define GN_SERVICE_FIELD_I_MSK 0x0000ffff
+#define GN_SERVICE_FIELD_SFT 16
+#define GN_SERVICE_FIELD_HI 31
+#define GN_SERVICE_FIELD_SZ 16
+#define RO_HT_MCS_40M_MSK 0x0000007f
+#define RO_HT_MCS_40M_I_MSK 0xffffff80
+#define RO_HT_MCS_40M_SFT 0
+#define RO_HT_MCS_40M_HI 6
+#define RO_HT_MCS_40M_SZ 7
+#define RO_L_RATE_40M_MSK 0x00003f00
+#define RO_L_RATE_40M_I_MSK 0xffffc0ff
+#define RO_L_RATE_40M_SFT 8
+#define RO_L_RATE_40M_HI 13
+#define RO_L_RATE_40M_SZ 6
+#define RG_DAGC_CNT_TH_MSK 0x00000003
+#define RG_DAGC_CNT_TH_I_MSK 0xfffffffc
+#define RG_DAGC_CNT_TH_SFT 0
+#define RG_DAGC_CNT_TH_HI 1
+#define RG_DAGC_CNT_TH_SZ 2
+#define RG_PACKET_STAT_EN_11GN_MSK 0x00100000
+#define RG_PACKET_STAT_EN_11GN_I_MSK 0xffefffff
+#define RG_PACKET_STAT_EN_11GN_SFT 20
+#define RG_PACKET_STAT_EN_11GN_HI 20
+#define RG_PACKET_STAT_EN_11GN_SZ 1
+#define RX_PHY_11GN_SOFT_RST_N_MSK 0x00000001
+#define RX_PHY_11GN_SOFT_RST_N_I_MSK 0xfffffffe
+#define RX_PHY_11GN_SOFT_RST_N_SFT 0
+#define RX_PHY_11GN_SOFT_RST_N_HI 0
+#define RX_PHY_11GN_SOFT_RST_N_SZ 1
+#define RG_RIFS_EN_MSK 0x00000002
+#define RG_RIFS_EN_I_MSK 0xfffffffd
+#define RG_RIFS_EN_SFT 1
+#define RG_RIFS_EN_HI 1
+#define RG_RIFS_EN_SZ 1
+#define RG_STBC_EN_MSK 0x00000004
+#define RG_STBC_EN_I_MSK 0xfffffffb
+#define RG_STBC_EN_SFT 2
+#define RG_STBC_EN_HI 2
+#define RG_STBC_EN_SZ 1
+#define RG_COR_SEL_MSK 0x00000008
+#define RG_COR_SEL_I_MSK 0xfffffff7
+#define RG_COR_SEL_SFT 3
+#define RG_COR_SEL_HI 3
+#define RG_COR_SEL_SZ 1
+#define RG_INI_PHASE_MSK 0x00000030
+#define RG_INI_PHASE_I_MSK 0xffffffcf
+#define RG_INI_PHASE_SFT 4
+#define RG_INI_PHASE_HI 5
+#define RG_INI_PHASE_SZ 2
+#define RG_HT_LTF_SEL_EQ_MSK 0x00000040
+#define RG_HT_LTF_SEL_EQ_I_MSK 0xffffffbf
+#define RG_HT_LTF_SEL_EQ_SFT 6
+#define RG_HT_LTF_SEL_EQ_HI 6
+#define RG_HT_LTF_SEL_EQ_SZ 1
+#define RG_HT_LTF_SEL_PILOT_MSK 0x00000080
+#define RG_HT_LTF_SEL_PILOT_I_MSK 0xffffff7f
+#define RG_HT_LTF_SEL_PILOT_SFT 7
+#define RG_HT_LTF_SEL_PILOT_HI 7
+#define RG_HT_LTF_SEL_PILOT_SZ 1
+#define RG_CCA_PWR_SEL_MSK 0x00000200
+#define RG_CCA_PWR_SEL_I_MSK 0xfffffdff
+#define RG_CCA_PWR_SEL_SFT 9
+#define RG_CCA_PWR_SEL_HI 9
+#define RG_CCA_PWR_SEL_SZ 1
+#define RG_CCA_XSCOR_PWR_SEL_MSK 0x00000400
+#define RG_CCA_XSCOR_PWR_SEL_I_MSK 0xfffffbff
+#define RG_CCA_XSCOR_PWR_SEL_SFT 10
+#define RG_CCA_XSCOR_PWR_SEL_HI 10
+#define RG_CCA_XSCOR_PWR_SEL_SZ 1
+#define RG_CCA_XSCOR_AVGPWR_SEL_MSK 0x00000800
+#define RG_CCA_XSCOR_AVGPWR_SEL_I_MSK 0xfffff7ff
+#define RG_CCA_XSCOR_AVGPWR_SEL_SFT 11
+#define RG_CCA_XSCOR_AVGPWR_SEL_HI 11
+#define RG_CCA_XSCOR_AVGPWR_SEL_SZ 1
+#define RG_DEBUG_SEL_MSK 0x0000f000
+#define RG_DEBUG_SEL_I_MSK 0xffff0fff
+#define RG_DEBUG_SEL_SFT 12
+#define RG_DEBUG_SEL_HI 15
+#define RG_DEBUG_SEL_SZ 4
+#define RG_POST_CLK_EN_MSK 0x00010000
+#define RG_POST_CLK_EN_I_MSK 0xfffeffff
+#define RG_POST_CLK_EN_SFT 16
+#define RG_POST_CLK_EN_HI 16
+#define RG_POST_CLK_EN_SZ 1
+#define IQCAL_RF_TX_EN_MSK 0x00000001
+#define IQCAL_RF_TX_EN_I_MSK 0xfffffffe
+#define IQCAL_RF_TX_EN_SFT 0
+#define IQCAL_RF_TX_EN_HI 0
+#define IQCAL_RF_TX_EN_SZ 1
+#define IQCAL_RF_TX_PA_EN_MSK 0x00000002
+#define IQCAL_RF_TX_PA_EN_I_MSK 0xfffffffd
+#define IQCAL_RF_TX_PA_EN_SFT 1
+#define IQCAL_RF_TX_PA_EN_HI 1
+#define IQCAL_RF_TX_PA_EN_SZ 1
+#define IQCAL_RF_TX_DAC_EN_MSK 0x00000004
+#define IQCAL_RF_TX_DAC_EN_I_MSK 0xfffffffb
+#define IQCAL_RF_TX_DAC_EN_SFT 2
+#define IQCAL_RF_TX_DAC_EN_HI 2
+#define IQCAL_RF_TX_DAC_EN_SZ 1
+#define IQCAL_RF_RX_AGC_MSK 0x00000008
+#define IQCAL_RF_RX_AGC_I_MSK 0xfffffff7
+#define IQCAL_RF_RX_AGC_SFT 3
+#define IQCAL_RF_RX_AGC_HI 3
+#define IQCAL_RF_RX_AGC_SZ 1
+#define IQCAL_RF_PGAG_MSK 0x00000f00
+#define IQCAL_RF_PGAG_I_MSK 0xfffff0ff
+#define IQCAL_RF_PGAG_SFT 8
+#define IQCAL_RF_PGAG_HI 11
+#define IQCAL_RF_PGAG_SZ 4
+#define IQCAL_RF_RFG_MSK 0x00003000
+#define IQCAL_RF_RFG_I_MSK 0xffffcfff
+#define IQCAL_RF_RFG_SFT 12
+#define IQCAL_RF_RFG_HI 13
+#define IQCAL_RF_RFG_SZ 2
+#define RG_TONEGEN_FREQ_MSK 0x007f0000
+#define RG_TONEGEN_FREQ_I_MSK 0xff80ffff
+#define RG_TONEGEN_FREQ_SFT 16
+#define RG_TONEGEN_FREQ_HI 22
+#define RG_TONEGEN_FREQ_SZ 7
+#define RG_TONEGEN_EN_MSK 0x00800000
+#define RG_TONEGEN_EN_I_MSK 0xff7fffff
+#define RG_TONEGEN_EN_SFT 23
+#define RG_TONEGEN_EN_HI 23
+#define RG_TONEGEN_EN_SZ 1
+#define RG_TONEGEN_INIT_PH_MSK 0x7f000000
+#define RG_TONEGEN_INIT_PH_I_MSK 0x80ffffff
+#define RG_TONEGEN_INIT_PH_SFT 24
+#define RG_TONEGEN_INIT_PH_HI 30
+#define RG_TONEGEN_INIT_PH_SZ 7
+#define RG_TONEGEN2_FREQ_MSK 0x0000007f
+#define RG_TONEGEN2_FREQ_I_MSK 0xffffff80
+#define RG_TONEGEN2_FREQ_SFT 0
+#define RG_TONEGEN2_FREQ_HI 6
+#define RG_TONEGEN2_FREQ_SZ 7
+#define RG_TONEGEN2_EN_MSK 0x00000080
+#define RG_TONEGEN2_EN_I_MSK 0xffffff7f
+#define RG_TONEGEN2_EN_SFT 7
+#define RG_TONEGEN2_EN_HI 7
+#define RG_TONEGEN2_EN_SZ 1
+#define RG_TONEGEN2_SCALE_MSK 0x0000ff00
+#define RG_TONEGEN2_SCALE_I_MSK 0xffff00ff
+#define RG_TONEGEN2_SCALE_SFT 8
+#define RG_TONEGEN2_SCALE_HI 15
+#define RG_TONEGEN2_SCALE_SZ 8
+#define RG_TXIQ_CLP_THD_I_MSK 0x000003ff
+#define RG_TXIQ_CLP_THD_I_I_MSK 0xfffffc00
+#define RG_TXIQ_CLP_THD_I_SFT 0
+#define RG_TXIQ_CLP_THD_I_HI 9
+#define RG_TXIQ_CLP_THD_I_SZ 10
+#define RG_TXIQ_CLP_THD_Q_MSK 0x03ff0000
+#define RG_TXIQ_CLP_THD_Q_I_MSK 0xfc00ffff
+#define RG_TXIQ_CLP_THD_Q_SFT 16
+#define RG_TXIQ_CLP_THD_Q_HI 25
+#define RG_TXIQ_CLP_THD_Q_SZ 10
+#define RG_TX_I_SCALE_MSK 0x000000ff
+#define RG_TX_I_SCALE_I_MSK 0xffffff00
+#define RG_TX_I_SCALE_SFT 0
+#define RG_TX_I_SCALE_HI 7
+#define RG_TX_I_SCALE_SZ 8
+#define RG_TX_Q_SCALE_MSK 0x0000ff00
+#define RG_TX_Q_SCALE_I_MSK 0xffff00ff
+#define RG_TX_Q_SCALE_SFT 8
+#define RG_TX_Q_SCALE_HI 15
+#define RG_TX_Q_SCALE_SZ 8
+#define RG_TX_IQ_SWP_MSK 0x00010000
+#define RG_TX_IQ_SWP_I_MSK 0xfffeffff
+#define RG_TX_IQ_SWP_SFT 16
+#define RG_TX_IQ_SWP_HI 16
+#define RG_TX_IQ_SWP_SZ 1
+#define RG_TX_SGN_OUT_MSK 0x00020000
+#define RG_TX_SGN_OUT_I_MSK 0xfffdffff
+#define RG_TX_SGN_OUT_SFT 17
+#define RG_TX_SGN_OUT_HI 17
+#define RG_TX_SGN_OUT_SZ 1
+#define RG_TXIQ_EMU_IDX_MSK 0x003c0000
+#define RG_TXIQ_EMU_IDX_I_MSK 0xffc3ffff
+#define RG_TXIQ_EMU_IDX_SFT 18
+#define RG_TXIQ_EMU_IDX_HI 21
+#define RG_TXIQ_EMU_IDX_SZ 4
+#define RG_TX_IQ_SRC_MSK 0x03000000
+#define RG_TX_IQ_SRC_I_MSK 0xfcffffff
+#define RG_TX_IQ_SRC_SFT 24
+#define RG_TX_IQ_SRC_HI 25
+#define RG_TX_IQ_SRC_SZ 2
+#define RG_TX_I_DC_MSK 0x000003ff
+#define RG_TX_I_DC_I_MSK 0xfffffc00
+#define RG_TX_I_DC_SFT 0
+#define RG_TX_I_DC_HI 9
+#define RG_TX_I_DC_SZ 10
+#define RG_TX_Q_DC_MSK 0x03ff0000
+#define RG_TX_Q_DC_I_MSK 0xfc00ffff
+#define RG_TX_Q_DC_SFT 16
+#define RG_TX_Q_DC_HI 25
+#define RG_TX_Q_DC_SZ 10
+#define RG_TX_IQ_THETA_MSK 0x0000001f
+#define RG_TX_IQ_THETA_I_MSK 0xffffffe0
+#define RG_TX_IQ_THETA_SFT 0
+#define RG_TX_IQ_THETA_HI 4
+#define RG_TX_IQ_THETA_SZ 5
+#define RG_TX_IQ_ALPHA_MSK 0x00001f00
+#define RG_TX_IQ_ALPHA_I_MSK 0xffffe0ff
+#define RG_TX_IQ_ALPHA_SFT 8
+#define RG_TX_IQ_ALPHA_HI 12
+#define RG_TX_IQ_ALPHA_SZ 5
+#define RG_TXIQ_NOSHRINK_MSK 0x00002000
+#define RG_TXIQ_NOSHRINK_I_MSK 0xffffdfff
+#define RG_TXIQ_NOSHRINK_SFT 13
+#define RG_TXIQ_NOSHRINK_HI 13
+#define RG_TXIQ_NOSHRINK_SZ 1
+#define RG_TX_I_OFFSET_MSK 0x00ff0000
+#define RG_TX_I_OFFSET_I_MSK 0xff00ffff
+#define RG_TX_I_OFFSET_SFT 16
+#define RG_TX_I_OFFSET_HI 23
+#define RG_TX_I_OFFSET_SZ 8
+#define RG_TX_Q_OFFSET_MSK 0xff000000
+#define RG_TX_Q_OFFSET_I_MSK 0x00ffffff
+#define RG_TX_Q_OFFSET_SFT 24
+#define RG_TX_Q_OFFSET_HI 31
+#define RG_TX_Q_OFFSET_SZ 8
+#define RG_RX_IQ_THETA_MSK 0x0000001f
+#define RG_RX_IQ_THETA_I_MSK 0xffffffe0
+#define RG_RX_IQ_THETA_SFT 0
+#define RG_RX_IQ_THETA_HI 4
+#define RG_RX_IQ_THETA_SZ 5
+#define RG_RX_IQ_ALPHA_MSK 0x00001f00
+#define RG_RX_IQ_ALPHA_I_MSK 0xffffe0ff
+#define RG_RX_IQ_ALPHA_SFT 8
+#define RG_RX_IQ_ALPHA_HI 12
+#define RG_RX_IQ_ALPHA_SZ 5
+#define RG_RXIQ_NOSHRINK_MSK 0x00002000
+#define RG_RXIQ_NOSHRINK_I_MSK 0xffffdfff
+#define RG_RXIQ_NOSHRINK_SFT 13
+#define RG_RXIQ_NOSHRINK_HI 13
+#define RG_RXIQ_NOSHRINK_SZ 1
+#define RG_MA_DPTH_MSK 0x0000000f
+#define RG_MA_DPTH_I_MSK 0xfffffff0
+#define RG_MA_DPTH_SFT 0
+#define RG_MA_DPTH_HI 3
+#define RG_MA_DPTH_SZ 4
+#define RG_INTG_PH_MSK 0x000003f0
+#define RG_INTG_PH_I_MSK 0xfffffc0f
+#define RG_INTG_PH_SFT 4
+#define RG_INTG_PH_HI 9
+#define RG_INTG_PH_SZ 6
+#define RG_INTG_PRD_MSK 0x00001c00
+#define RG_INTG_PRD_I_MSK 0xffffe3ff
+#define RG_INTG_PRD_SFT 10
+#define RG_INTG_PRD_HI 12
+#define RG_INTG_PRD_SZ 3
+#define RG_INTG_MU_MSK 0x00006000
+#define RG_INTG_MU_I_MSK 0xffff9fff
+#define RG_INTG_MU_SFT 13
+#define RG_INTG_MU_HI 14
+#define RG_INTG_MU_SZ 2
+#define RG_IQCAL_SPRM_SELQ_MSK 0x00010000
+#define RG_IQCAL_SPRM_SELQ_I_MSK 0xfffeffff
+#define RG_IQCAL_SPRM_SELQ_SFT 16
+#define RG_IQCAL_SPRM_SELQ_HI 16
+#define RG_IQCAL_SPRM_SELQ_SZ 1
+#define RG_IQCAL_SPRM_EN_MSK 0x00020000
+#define RG_IQCAL_SPRM_EN_I_MSK 0xfffdffff
+#define RG_IQCAL_SPRM_EN_SFT 17
+#define RG_IQCAL_SPRM_EN_HI 17
+#define RG_IQCAL_SPRM_EN_SZ 1
+#define RG_IQCAL_SPRM_FREQ_MSK 0x00fc0000
+#define RG_IQCAL_SPRM_FREQ_I_MSK 0xff03ffff
+#define RG_IQCAL_SPRM_FREQ_SFT 18
+#define RG_IQCAL_SPRM_FREQ_HI 23
+#define RG_IQCAL_SPRM_FREQ_SZ 6
+#define RG_IQCAL_IQCOL_EN_MSK 0x01000000
+#define RG_IQCAL_IQCOL_EN_I_MSK 0xfeffffff
+#define RG_IQCAL_IQCOL_EN_SFT 24
+#define RG_IQCAL_IQCOL_EN_HI 24
+#define RG_IQCAL_IQCOL_EN_SZ 1
+#define RG_IQCAL_ALPHA_ESTM_EN_MSK 0x02000000
+#define RG_IQCAL_ALPHA_ESTM_EN_I_MSK 0xfdffffff
+#define RG_IQCAL_ALPHA_ESTM_EN_SFT 25
+#define RG_IQCAL_ALPHA_ESTM_EN_HI 25
+#define RG_IQCAL_ALPHA_ESTM_EN_SZ 1
+#define RG_IQCAL_DC_EN_MSK 0x04000000
+#define RG_IQCAL_DC_EN_I_MSK 0xfbffffff
+#define RG_IQCAL_DC_EN_SFT 26
+#define RG_IQCAL_DC_EN_HI 26
+#define RG_IQCAL_DC_EN_SZ 1
+#define RG_PHEST_STBY_MSK 0x08000000
+#define RG_PHEST_STBY_I_MSK 0xf7ffffff
+#define RG_PHEST_STBY_SFT 27
+#define RG_PHEST_STBY_HI 27
+#define RG_PHEST_STBY_SZ 1
+#define RG_PHEST_EN_MSK 0x10000000
+#define RG_PHEST_EN_I_MSK 0xefffffff
+#define RG_PHEST_EN_SFT 28
+#define RG_PHEST_EN_HI 28
+#define RG_PHEST_EN_SZ 1
+#define RG_GP_DIV_EN_MSK 0x20000000
+#define RG_GP_DIV_EN_I_MSK 0xdfffffff
+#define RG_GP_DIV_EN_SFT 29
+#define RG_GP_DIV_EN_HI 29
+#define RG_GP_DIV_EN_SZ 1
+#define RG_DPD_GAIN_EST_EN_MSK 0x40000000
+#define RG_DPD_GAIN_EST_EN_I_MSK 0xbfffffff
+#define RG_DPD_GAIN_EST_EN_SFT 30
+#define RG_DPD_GAIN_EST_EN_HI 30
+#define RG_DPD_GAIN_EST_EN_SZ 1
+#define RG_IQCAL_MULT_OP0_MSK 0x000003ff
+#define RG_IQCAL_MULT_OP0_I_MSK 0xfffffc00
+#define RG_IQCAL_MULT_OP0_SFT 0
+#define RG_IQCAL_MULT_OP0_HI 9
+#define RG_IQCAL_MULT_OP0_SZ 10
+#define RG_IQCAL_MULT_OP1_MSK 0x03ff0000
+#define RG_IQCAL_MULT_OP1_I_MSK 0xfc00ffff
+#define RG_IQCAL_MULT_OP1_SFT 16
+#define RG_IQCAL_MULT_OP1_HI 25
+#define RG_IQCAL_MULT_OP1_SZ 10
+#define RO_IQCAL_O_MSK 0x000fffff
+#define RO_IQCAL_O_I_MSK 0xfff00000
+#define RO_IQCAL_O_SFT 0
+#define RO_IQCAL_O_HI 19
+#define RO_IQCAL_O_SZ 20
+#define RO_IQCAL_SPRM_RDY_MSK 0x00100000
+#define RO_IQCAL_SPRM_RDY_I_MSK 0xffefffff
+#define RO_IQCAL_SPRM_RDY_SFT 20
+#define RO_IQCAL_SPRM_RDY_HI 20
+#define RO_IQCAL_SPRM_RDY_SZ 1
+#define RO_IQCAL_IQCOL_RDY_MSK 0x00200000
+#define RO_IQCAL_IQCOL_RDY_I_MSK 0xffdfffff
+#define RO_IQCAL_IQCOL_RDY_SFT 21
+#define RO_IQCAL_IQCOL_RDY_HI 21
+#define RO_IQCAL_IQCOL_RDY_SZ 1
+#define RO_IQCAL_ALPHA_ESTM_RDY_MSK 0x00400000
+#define RO_IQCAL_ALPHA_ESTM_RDY_I_MSK 0xffbfffff
+#define RO_IQCAL_ALPHA_ESTM_RDY_SFT 22
+#define RO_IQCAL_ALPHA_ESTM_RDY_HI 22
+#define RO_IQCAL_ALPHA_ESTM_RDY_SZ 1
+#define RO_IQCAL_DC_RDY_MSK 0x00800000
+#define RO_IQCAL_DC_RDY_I_MSK 0xff7fffff
+#define RO_IQCAL_DC_RDY_SFT 23
+#define RO_IQCAL_DC_RDY_HI 23
+#define RO_IQCAL_DC_RDY_SZ 1
+#define RO_IQCAL_MULT_RDY_MSK 0x01000000
+#define RO_IQCAL_MULT_RDY_I_MSK 0xfeffffff
+#define RO_IQCAL_MULT_RDY_SFT 24
+#define RO_IQCAL_MULT_RDY_HI 24
+#define RO_IQCAL_MULT_RDY_SZ 1
+#define RO_FFT_ENRG_RDY_MSK 0x02000000
+#define RO_FFT_ENRG_RDY_I_MSK 0xfdffffff
+#define RO_FFT_ENRG_RDY_SFT 25
+#define RO_FFT_ENRG_RDY_HI 25
+#define RO_FFT_ENRG_RDY_SZ 1
+#define RO_PHEST_RDY_MSK 0x04000000
+#define RO_PHEST_RDY_I_MSK 0xfbffffff
+#define RO_PHEST_RDY_SFT 26
+#define RO_PHEST_RDY_HI 26
+#define RO_PHEST_RDY_SZ 1
+#define RO_GP_DIV_RDY_MSK 0x08000000
+#define RO_GP_DIV_RDY_I_MSK 0xf7ffffff
+#define RO_GP_DIV_RDY_SFT 27
+#define RO_GP_DIV_RDY_HI 27
+#define RO_GP_DIV_RDY_SZ 1
+#define RO_GAIN_EST_RDY_MSK 0x10000000
+#define RO_GAIN_EST_RDY_I_MSK 0xefffffff
+#define RO_GAIN_EST_RDY_SFT 28
+#define RO_GAIN_EST_RDY_HI 28
+#define RO_GAIN_EST_RDY_SZ 1
+#define RO_AMP_O_MSK 0x000001ff
+#define RO_AMP_O_I_MSK 0xfffffe00
+#define RO_AMP_O_SFT 0
+#define RO_AMP_O_HI 8
+#define RO_AMP_O_SZ 9
+#define RG_RX_I_SCALE_MSK 0x000000ff
+#define RG_RX_I_SCALE_I_MSK 0xffffff00
+#define RG_RX_I_SCALE_SFT 0
+#define RG_RX_I_SCALE_HI 7
+#define RG_RX_I_SCALE_SZ 8
+#define RG_RX_Q_SCALE_MSK 0x0000ff00
+#define RG_RX_Q_SCALE_I_MSK 0xffff00ff
+#define RG_RX_Q_SCALE_SFT 8
+#define RG_RX_Q_SCALE_HI 15
+#define RG_RX_Q_SCALE_SZ 8
+#define RG_RX_I_OFFSET_MSK 0x00ff0000
+#define RG_RX_I_OFFSET_I_MSK 0xff00ffff
+#define RG_RX_I_OFFSET_SFT 16
+#define RG_RX_I_OFFSET_HI 23
+#define RG_RX_I_OFFSET_SZ 8
+#define RG_RX_Q_OFFSET_MSK 0xff000000
+#define RG_RX_Q_OFFSET_I_MSK 0x00ffffff
+#define RG_RX_Q_OFFSET_SFT 24
+#define RG_RX_Q_OFFSET_HI 31
+#define RG_RX_Q_OFFSET_SZ 8
+#define RG_RX_IQ_SWP_MSK 0x00000001
+#define RG_RX_IQ_SWP_I_MSK 0xfffffffe
+#define RG_RX_IQ_SWP_SFT 0
+#define RG_RX_IQ_SWP_HI 0
+#define RG_RX_IQ_SWP_SZ 1
+#define RG_RX_SGN_IN_MSK 0x00000002
+#define RG_RX_SGN_IN_I_MSK 0xfffffffd
+#define RG_RX_SGN_IN_SFT 1
+#define RG_RX_SGN_IN_HI 1
+#define RG_RX_SGN_IN_SZ 1
+#define RG_RX_IQ_SRC_MSK 0x0000000c
+#define RG_RX_IQ_SRC_I_MSK 0xfffffff3
+#define RG_RX_IQ_SRC_SFT 2
+#define RG_RX_IQ_SRC_HI 3
+#define RG_RX_IQ_SRC_SZ 2
+#define RG_ACI_GAIN_MSK 0x00000ff0
+#define RG_ACI_GAIN_I_MSK 0xfffff00f
+#define RG_ACI_GAIN_SFT 4
+#define RG_ACI_GAIN_HI 11
+#define RG_ACI_GAIN_SZ 8
+#define RG_FFT_EN_MSK 0x00001000
+#define RG_FFT_EN_I_MSK 0xffffefff
+#define RG_FFT_EN_SFT 12
+#define RG_FFT_EN_HI 12
+#define RG_FFT_EN_SZ 1
+#define RG_FFT_MOD_MSK 0x00002000
+#define RG_FFT_MOD_I_MSK 0xffffdfff
+#define RG_FFT_MOD_SFT 13
+#define RG_FFT_MOD_HI 13
+#define RG_FFT_MOD_SZ 1
+#define RG_FFT_SCALE_MSK 0x00ffc000
+#define RG_FFT_SCALE_I_MSK 0xff003fff
+#define RG_FFT_SCALE_SFT 14
+#define RG_FFT_SCALE_HI 23
+#define RG_FFT_SCALE_SZ 10
+#define RG_FFT_ENRG_FREQ_MSK 0x3f000000
+#define RG_FFT_ENRG_FREQ_I_MSK 0xc0ffffff
+#define RG_FFT_ENRG_FREQ_SFT 24
+#define RG_FFT_ENRG_FREQ_HI 29
+#define RG_FFT_ENRG_FREQ_SZ 6
+#define RG_FPGA_80M_PH_UP_MSK 0x40000000
+#define RG_FPGA_80M_PH_UP_I_MSK 0xbfffffff
+#define RG_FPGA_80M_PH_UP_SFT 30
+#define RG_FPGA_80M_PH_UP_HI 30
+#define RG_FPGA_80M_PH_UP_SZ 1
+#define RG_FPGA_80M_PH_STP_MSK 0x80000000
+#define RG_FPGA_80M_PH_STP_I_MSK 0x7fffffff
+#define RG_FPGA_80M_PH_STP_SFT 31
+#define RG_FPGA_80M_PH_STP_HI 31
+#define RG_FPGA_80M_PH_STP_SZ 1
+#define RG_ADC2LA_SEL_MSK 0x00000001
+#define RG_ADC2LA_SEL_I_MSK 0xfffffffe
+#define RG_ADC2LA_SEL_SFT 0
+#define RG_ADC2LA_SEL_HI 0
+#define RG_ADC2LA_SEL_SZ 1
+#define RG_ADC2LA_CLKPH_MSK 0x00000002
+#define RG_ADC2LA_CLKPH_I_MSK 0xfffffffd
+#define RG_ADC2LA_CLKPH_SFT 1
+#define RG_ADC2LA_CLKPH_HI 1
+#define RG_ADC2LA_CLKPH_SZ 1
+#define RG_RXIQ_EMU_IDX_MSK 0x0000000f
+#define RG_RXIQ_EMU_IDX_I_MSK 0xfffffff0
+#define RG_RXIQ_EMU_IDX_SFT 0
+#define RG_RXIQ_EMU_IDX_HI 3
+#define RG_RXIQ_EMU_IDX_SZ 4
+#define RG_IQCAL_BP_ACI_MSK 0x00000010
+#define RG_IQCAL_BP_ACI_I_MSK 0xffffffef
+#define RG_IQCAL_BP_ACI_SFT 4
+#define RG_IQCAL_BP_ACI_HI 4
+#define RG_IQCAL_BP_ACI_SZ 1
+#define RG_DPD_AM_EN_MSK 0x00000001
+#define RG_DPD_AM_EN_I_MSK 0xfffffffe
+#define RG_DPD_AM_EN_SFT 0
+#define RG_DPD_AM_EN_HI 0
+#define RG_DPD_AM_EN_SZ 1
+#define RG_DPD_PM_EN_MSK 0x00000002
+#define RG_DPD_PM_EN_I_MSK 0xfffffffd
+#define RG_DPD_PM_EN_SFT 1
+#define RG_DPD_PM_EN_HI 1
+#define RG_DPD_PM_EN_SZ 1
+#define RG_DPD_PM_AMSEL_MSK 0x00000004
+#define RG_DPD_PM_AMSEL_I_MSK 0xfffffffb
+#define RG_DPD_PM_AMSEL_SFT 2
+#define RG_DPD_PM_AMSEL_HI 2
+#define RG_DPD_PM_AMSEL_SZ 1
+#define RG_DPD_020_GAIN_MSK 0x000003ff
+#define RG_DPD_020_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_020_GAIN_SFT 0
+#define RG_DPD_020_GAIN_HI 9
+#define RG_DPD_020_GAIN_SZ 10
+#define RG_DPD_040_GAIN_MSK 0x03ff0000
+#define RG_DPD_040_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_040_GAIN_SFT 16
+#define RG_DPD_040_GAIN_HI 25
+#define RG_DPD_040_GAIN_SZ 10
+#define RG_DPD_060_GAIN_MSK 0x000003ff
+#define RG_DPD_060_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_060_GAIN_SFT 0
+#define RG_DPD_060_GAIN_HI 9
+#define RG_DPD_060_GAIN_SZ 10
+#define RG_DPD_080_GAIN_MSK 0x03ff0000
+#define RG_DPD_080_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_080_GAIN_SFT 16
+#define RG_DPD_080_GAIN_HI 25
+#define RG_DPD_080_GAIN_SZ 10
+#define RG_DPD_0A0_GAIN_MSK 0x000003ff
+#define RG_DPD_0A0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0A0_GAIN_SFT 0
+#define RG_DPD_0A0_GAIN_HI 9
+#define RG_DPD_0A0_GAIN_SZ 10
+#define RG_DPD_0C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_0C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_0C0_GAIN_SFT 16
+#define RG_DPD_0C0_GAIN_HI 25
+#define RG_DPD_0C0_GAIN_SZ 10
+#define RG_DPD_0D0_GAIN_MSK 0x000003ff
+#define RG_DPD_0D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0D0_GAIN_SFT 0
+#define RG_DPD_0D0_GAIN_HI 9
+#define RG_DPD_0D0_GAIN_SZ 10
+#define RG_DPD_0E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_0E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_0E0_GAIN_SFT 16
+#define RG_DPD_0E0_GAIN_HI 25
+#define RG_DPD_0E0_GAIN_SZ 10
+#define RG_DPD_0F0_GAIN_MSK 0x000003ff
+#define RG_DPD_0F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0F0_GAIN_SFT 0
+#define RG_DPD_0F0_GAIN_HI 9
+#define RG_DPD_0F0_GAIN_SZ 10
+#define RG_DPD_100_GAIN_MSK 0x03ff0000
+#define RG_DPD_100_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_100_GAIN_SFT 16
+#define RG_DPD_100_GAIN_HI 25
+#define RG_DPD_100_GAIN_SZ 10
+#define RG_DPD_110_GAIN_MSK 0x000003ff
+#define RG_DPD_110_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_110_GAIN_SFT 0
+#define RG_DPD_110_GAIN_HI 9
+#define RG_DPD_110_GAIN_SZ 10
+#define RG_DPD_120_GAIN_MSK 0x03ff0000
+#define RG_DPD_120_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_120_GAIN_SFT 16
+#define RG_DPD_120_GAIN_HI 25
+#define RG_DPD_120_GAIN_SZ 10
+#define RG_DPD_130_GAIN_MSK 0x000003ff
+#define RG_DPD_130_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_130_GAIN_SFT 0
+#define RG_DPD_130_GAIN_HI 9
+#define RG_DPD_130_GAIN_SZ 10
+#define RG_DPD_140_GAIN_MSK 0x03ff0000
+#define RG_DPD_140_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_140_GAIN_SFT 16
+#define RG_DPD_140_GAIN_HI 25
+#define RG_DPD_140_GAIN_SZ 10
+#define RG_DPD_150_GAIN_MSK 0x000003ff
+#define RG_DPD_150_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_150_GAIN_SFT 0
+#define RG_DPD_150_GAIN_HI 9
+#define RG_DPD_150_GAIN_SZ 10
+#define RG_DPD_160_GAIN_MSK 0x03ff0000
+#define RG_DPD_160_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_160_GAIN_SFT 16
+#define RG_DPD_160_GAIN_HI 25
+#define RG_DPD_160_GAIN_SZ 10
+#define RG_DPD_170_GAIN_MSK 0x000003ff
+#define RG_DPD_170_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_170_GAIN_SFT 0
+#define RG_DPD_170_GAIN_HI 9
+#define RG_DPD_170_GAIN_SZ 10
+#define RG_DPD_180_GAIN_MSK 0x03ff0000
+#define RG_DPD_180_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_180_GAIN_SFT 16
+#define RG_DPD_180_GAIN_HI 25
+#define RG_DPD_180_GAIN_SZ 10
+#define RG_DPD_190_GAIN_MSK 0x000003ff
+#define RG_DPD_190_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_190_GAIN_SFT 0
+#define RG_DPD_190_GAIN_HI 9
+#define RG_DPD_190_GAIN_SZ 10
+#define RG_DPD_1A0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1A0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1A0_GAIN_SFT 16
+#define RG_DPD_1A0_GAIN_HI 25
+#define RG_DPD_1A0_GAIN_SZ 10
+#define RG_DPD_1B0_GAIN_MSK 0x000003ff
+#define RG_DPD_1B0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1B0_GAIN_SFT 0
+#define RG_DPD_1B0_GAIN_HI 9
+#define RG_DPD_1B0_GAIN_SZ 10
+#define RG_DPD_1C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1C0_GAIN_SFT 16
+#define RG_DPD_1C0_GAIN_HI 25
+#define RG_DPD_1C0_GAIN_SZ 10
+#define RG_DPD_1D0_GAIN_MSK 0x000003ff
+#define RG_DPD_1D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1D0_GAIN_SFT 0
+#define RG_DPD_1D0_GAIN_HI 9
+#define RG_DPD_1D0_GAIN_SZ 10
+#define RG_DPD_1E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1E0_GAIN_SFT 16
+#define RG_DPD_1E0_GAIN_HI 25
+#define RG_DPD_1E0_GAIN_SZ 10
+#define RG_DPD_1F0_GAIN_MSK 0x000003ff
+#define RG_DPD_1F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1F0_GAIN_SFT 0
+#define RG_DPD_1F0_GAIN_HI 9
+#define RG_DPD_1F0_GAIN_SZ 10
+#define RG_DPD_200_GAIN_MSK 0x03ff0000
+#define RG_DPD_200_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_200_GAIN_SFT 16
+#define RG_DPD_200_GAIN_HI 25
+#define RG_DPD_200_GAIN_SZ 10
+#define RG_DPD_020_PH_MSK 0x00001fff
+#define RG_DPD_020_PH_I_MSK 0xffffe000
+#define RG_DPD_020_PH_SFT 0
+#define RG_DPD_020_PH_HI 12
+#define RG_DPD_020_PH_SZ 13
+#define RG_DPD_040_PH_MSK 0x1fff0000
+#define RG_DPD_040_PH_I_MSK 0xe000ffff
+#define RG_DPD_040_PH_SFT 16
+#define RG_DPD_040_PH_HI 28
+#define RG_DPD_040_PH_SZ 13
+#define RG_DPD_060_PH_MSK 0x00001fff
+#define RG_DPD_060_PH_I_MSK 0xffffe000
+#define RG_DPD_060_PH_SFT 0
+#define RG_DPD_060_PH_HI 12
+#define RG_DPD_060_PH_SZ 13
+#define RG_DPD_080_PH_MSK 0x1fff0000
+#define RG_DPD_080_PH_I_MSK 0xe000ffff
+#define RG_DPD_080_PH_SFT 16
+#define RG_DPD_080_PH_HI 28
+#define RG_DPD_080_PH_SZ 13
+#define RG_DPD_0A0_PH_MSK 0x00001fff
+#define RG_DPD_0A0_PH_I_MSK 0xffffe000
+#define RG_DPD_0A0_PH_SFT 0
+#define RG_DPD_0A0_PH_HI 12
+#define RG_DPD_0A0_PH_SZ 13
+#define RG_DPD_0C0_PH_MSK 0x1fff0000
+#define RG_DPD_0C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_0C0_PH_SFT 16
+#define RG_DPD_0C0_PH_HI 28
+#define RG_DPD_0C0_PH_SZ 13
+#define RG_DPD_0D0_PH_MSK 0x00001fff
+#define RG_DPD_0D0_PH_I_MSK 0xffffe000
+#define RG_DPD_0D0_PH_SFT 0
+#define RG_DPD_0D0_PH_HI 12
+#define RG_DPD_0D0_PH_SZ 13
+#define RG_DPD_0E0_PH_MSK 0x1fff0000
+#define RG_DPD_0E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_0E0_PH_SFT 16
+#define RG_DPD_0E0_PH_HI 28
+#define RG_DPD_0E0_PH_SZ 13
+#define RG_DPD_0F0_PH_MSK 0x00001fff
+#define RG_DPD_0F0_PH_I_MSK 0xffffe000
+#define RG_DPD_0F0_PH_SFT 0
+#define RG_DPD_0F0_PH_HI 12
+#define RG_DPD_0F0_PH_SZ 13
+#define RG_DPD_100_PH_MSK 0x1fff0000
+#define RG_DPD_100_PH_I_MSK 0xe000ffff
+#define RG_DPD_100_PH_SFT 16
+#define RG_DPD_100_PH_HI 28
+#define RG_DPD_100_PH_SZ 13
+#define RG_DPD_110_PH_MSK 0x00001fff
+#define RG_DPD_110_PH_I_MSK 0xffffe000
+#define RG_DPD_110_PH_SFT 0
+#define RG_DPD_110_PH_HI 12
+#define RG_DPD_110_PH_SZ 13
+#define RG_DPD_120_PH_MSK 0x1fff0000
+#define RG_DPD_120_PH_I_MSK 0xe000ffff
+#define RG_DPD_120_PH_SFT 16
+#define RG_DPD_120_PH_HI 28
+#define RG_DPD_120_PH_SZ 13
+#define RG_DPD_130_PH_MSK 0x00001fff
+#define RG_DPD_130_PH_I_MSK 0xffffe000
+#define RG_DPD_130_PH_SFT 0
+#define RG_DPD_130_PH_HI 12
+#define RG_DPD_130_PH_SZ 13
+#define RG_DPD_140_PH_MSK 0x1fff0000
+#define RG_DPD_140_PH_I_MSK 0xe000ffff
+#define RG_DPD_140_PH_SFT 16
+#define RG_DPD_140_PH_HI 28
+#define RG_DPD_140_PH_SZ 13
+#define RG_DPD_150_PH_MSK 0x00001fff
+#define RG_DPD_150_PH_I_MSK 0xffffe000
+#define RG_DPD_150_PH_SFT 0
+#define RG_DPD_150_PH_HI 12
+#define RG_DPD_150_PH_SZ 13
+#define RG_DPD_160_PH_MSK 0x1fff0000
+#define RG_DPD_160_PH_I_MSK 0xe000ffff
+#define RG_DPD_160_PH_SFT 16
+#define RG_DPD_160_PH_HI 28
+#define RG_DPD_160_PH_SZ 13
+#define RG_DPD_170_PH_MSK 0x00001fff
+#define RG_DPD_170_PH_I_MSK 0xffffe000
+#define RG_DPD_170_PH_SFT 0
+#define RG_DPD_170_PH_HI 12
+#define RG_DPD_170_PH_SZ 13
+#define RG_DPD_180_PH_MSK 0x1fff0000
+#define RG_DPD_180_PH_I_MSK 0xe000ffff
+#define RG_DPD_180_PH_SFT 16
+#define RG_DPD_180_PH_HI 28
+#define RG_DPD_180_PH_SZ 13
+#define RG_DPD_190_PH_MSK 0x00001fff
+#define RG_DPD_190_PH_I_MSK 0xffffe000
+#define RG_DPD_190_PH_SFT 0
+#define RG_DPD_190_PH_HI 12
+#define RG_DPD_190_PH_SZ 13
+#define RG_DPD_1A0_PH_MSK 0x1fff0000
+#define RG_DPD_1A0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1A0_PH_SFT 16
+#define RG_DPD_1A0_PH_HI 28
+#define RG_DPD_1A0_PH_SZ 13
+#define RG_DPD_1B0_PH_MSK 0x00001fff
+#define RG_DPD_1B0_PH_I_MSK 0xffffe000
+#define RG_DPD_1B0_PH_SFT 0
+#define RG_DPD_1B0_PH_HI 12
+#define RG_DPD_1B0_PH_SZ 13
+#define RG_DPD_1C0_PH_MSK 0x1fff0000
+#define RG_DPD_1C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1C0_PH_SFT 16
+#define RG_DPD_1C0_PH_HI 28
+#define RG_DPD_1C0_PH_SZ 13
+#define RG_DPD_1D0_PH_MSK 0x00001fff
+#define RG_DPD_1D0_PH_I_MSK 0xffffe000
+#define RG_DPD_1D0_PH_SFT 0
+#define RG_DPD_1D0_PH_HI 12
+#define RG_DPD_1D0_PH_SZ 13
+#define RG_DPD_1E0_PH_MSK 0x1fff0000
+#define RG_DPD_1E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1E0_PH_SFT 16
+#define RG_DPD_1E0_PH_HI 28
+#define RG_DPD_1E0_PH_SZ 13
+#define RG_DPD_1F0_PH_MSK 0x00001fff
+#define RG_DPD_1F0_PH_I_MSK 0xffffe000
+#define RG_DPD_1F0_PH_SFT 0
+#define RG_DPD_1F0_PH_HI 12
+#define RG_DPD_1F0_PH_SZ 13
+#define RG_DPD_200_PH_MSK 0x1fff0000
+#define RG_DPD_200_PH_I_MSK 0xe000ffff
+#define RG_DPD_200_PH_SFT 16
+#define RG_DPD_200_PH_HI 28
+#define RG_DPD_200_PH_SZ 13
+#define RG_DPD_GAIN_EST_Y0_MSK 0x000001ff
+#define RG_DPD_GAIN_EST_Y0_I_MSK 0xfffffe00
+#define RG_DPD_GAIN_EST_Y0_SFT 0
+#define RG_DPD_GAIN_EST_Y0_HI 8
+#define RG_DPD_GAIN_EST_Y0_SZ 9
+#define RG_DPD_GAIN_EST_Y1_MSK 0x01ff0000
+#define RG_DPD_GAIN_EST_Y1_I_MSK 0xfe00ffff
+#define RG_DPD_GAIN_EST_Y1_SFT 16
+#define RG_DPD_GAIN_EST_Y1_HI 24
+#define RG_DPD_GAIN_EST_Y1_SZ 9
+#define RG_DPD_LOOP_GAIN_MSK 0x000003ff
+#define RG_DPD_LOOP_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_LOOP_GAIN_SFT 0
+#define RG_DPD_LOOP_GAIN_HI 9
+#define RG_DPD_LOOP_GAIN_SZ 10
+#define RG_DPD_GAIN_EST_X0_MSK 0x000001ff
+#define RG_DPD_GAIN_EST_X0_I_MSK 0xfffffe00
+#define RG_DPD_GAIN_EST_X0_SFT 0
+#define RG_DPD_GAIN_EST_X0_HI 8
+#define RG_DPD_GAIN_EST_X0_SZ 9
+#define RO_DPD_GAIN_MSK 0x03ff0000
+#define RO_DPD_GAIN_I_MSK 0xfc00ffff
+#define RO_DPD_GAIN_SFT 16
+#define RO_DPD_GAIN_HI 25
+#define RO_DPD_GAIN_SZ 10
+#define TX_SCALE_11B_MSK 0x000000ff
+#define TX_SCALE_11B_I_MSK 0xffffff00
+#define TX_SCALE_11B_SFT 0
+#define TX_SCALE_11B_HI 7
+#define TX_SCALE_11B_SZ 8
+#define TX_SCALE_11B_P0D5_MSK 0x0000ff00
+#define TX_SCALE_11B_P0D5_I_MSK 0xffff00ff
+#define TX_SCALE_11B_P0D5_SFT 8
+#define TX_SCALE_11B_P0D5_HI 15
+#define TX_SCALE_11B_P0D5_SZ 8
+#define TX_SCALE_11G_MSK 0x00ff0000
+#define TX_SCALE_11G_I_MSK 0xff00ffff
+#define TX_SCALE_11G_SFT 16
+#define TX_SCALE_11G_HI 23
+#define TX_SCALE_11G_SZ 8
+#define TX_SCALE_11G_P0D5_MSK 0xff000000
+#define TX_SCALE_11G_P0D5_I_MSK 0x00ffffff
+#define TX_SCALE_11G_P0D5_SFT 24
+#define TX_SCALE_11G_P0D5_HI 31
+#define TX_SCALE_11G_P0D5_SZ 8
+#define RG_EN_MANUAL_MSK 0x00000001
+#define RG_EN_MANUAL_I_MSK 0xfffffffe
+#define RG_EN_MANUAL_SFT 0
+#define RG_EN_MANUAL_HI 0
+#define RG_EN_MANUAL_SZ 1
+#define RG_TX_EN_MSK 0x00000002
+#define RG_TX_EN_I_MSK 0xfffffffd
+#define RG_TX_EN_SFT 1
+#define RG_TX_EN_HI 1
+#define RG_TX_EN_SZ 1
+#define RG_TX_PA_EN_MSK 0x00000004
+#define RG_TX_PA_EN_I_MSK 0xfffffffb
+#define RG_TX_PA_EN_SFT 2
+#define RG_TX_PA_EN_HI 2
+#define RG_TX_PA_EN_SZ 1
+#define RG_TX_DAC_EN_MSK 0x00000008
+#define RG_TX_DAC_EN_I_MSK 0xfffffff7
+#define RG_TX_DAC_EN_SFT 3
+#define RG_TX_DAC_EN_HI 3
+#define RG_TX_DAC_EN_SZ 1
+#define RG_RX_AGC_MSK 0x00000010
+#define RG_RX_AGC_I_MSK 0xffffffef
+#define RG_RX_AGC_SFT 4
+#define RG_RX_AGC_HI 4
+#define RG_RX_AGC_SZ 1
+#define RG_RX_GAIN_MANUAL_MSK 0x00000020
+#define RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
+#define RG_RX_GAIN_MANUAL_SFT 5
+#define RG_RX_GAIN_MANUAL_HI 5
+#define RG_RX_GAIN_MANUAL_SZ 1
+#define RG_RFG_MSK 0x000000c0
+#define RG_RFG_I_MSK 0xffffff3f
+#define RG_RFG_SFT 6
+#define RG_RFG_HI 7
+#define RG_RFG_SZ 2
+#define RG_PGAG_MSK 0x00000f00
+#define RG_PGAG_I_MSK 0xfffff0ff
+#define RG_PGAG_SFT 8
+#define RG_PGAG_HI 11
+#define RG_PGAG_SZ 4
+#define RG_MODE_MSK 0x00003000
+#define RG_MODE_I_MSK 0xffffcfff
+#define RG_MODE_SFT 12
+#define RG_MODE_HI 13
+#define RG_MODE_SZ 2
+#define RG_EN_TX_TRSW_MSK 0x00004000
+#define RG_EN_TX_TRSW_I_MSK 0xffffbfff
+#define RG_EN_TX_TRSW_SFT 14
+#define RG_EN_TX_TRSW_HI 14
+#define RG_EN_TX_TRSW_SZ 1
+#define RG_EN_SX_MSK 0x00008000
+#define RG_EN_SX_I_MSK 0xffff7fff
+#define RG_EN_SX_SFT 15
+#define RG_EN_SX_HI 15
+#define RG_EN_SX_SZ 1
+#define RG_EN_RX_LNA_MSK 0x00010000
+#define RG_EN_RX_LNA_I_MSK 0xfffeffff
+#define RG_EN_RX_LNA_SFT 16
+#define RG_EN_RX_LNA_HI 16
+#define RG_EN_RX_LNA_SZ 1
+#define RG_EN_RX_MIXER_MSK 0x00020000
+#define RG_EN_RX_MIXER_I_MSK 0xfffdffff
+#define RG_EN_RX_MIXER_SFT 17
+#define RG_EN_RX_MIXER_HI 17
+#define RG_EN_RX_MIXER_SZ 1
+#define RG_EN_RX_DIV2_MSK 0x00040000
+#define RG_EN_RX_DIV2_I_MSK 0xfffbffff
+#define RG_EN_RX_DIV2_SFT 18
+#define RG_EN_RX_DIV2_HI 18
+#define RG_EN_RX_DIV2_SZ 1
+#define RG_EN_RX_LOBUF_MSK 0x00080000
+#define RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
+#define RG_EN_RX_LOBUF_SFT 19
+#define RG_EN_RX_LOBUF_HI 19
+#define RG_EN_RX_LOBUF_SZ 1
+#define RG_EN_RX_TZ_MSK 0x00100000
+#define RG_EN_RX_TZ_I_MSK 0xffefffff
+#define RG_EN_RX_TZ_SFT 20
+#define RG_EN_RX_TZ_HI 20
+#define RG_EN_RX_TZ_SZ 1
+#define RG_EN_RX_FILTER_MSK 0x00200000
+#define RG_EN_RX_FILTER_I_MSK 0xffdfffff
+#define RG_EN_RX_FILTER_SFT 21
+#define RG_EN_RX_FILTER_HI 21
+#define RG_EN_RX_FILTER_SZ 1
+#define RG_EN_RX_HPF_MSK 0x00400000
+#define RG_EN_RX_HPF_I_MSK 0xffbfffff
+#define RG_EN_RX_HPF_SFT 22
+#define RG_EN_RX_HPF_HI 22
+#define RG_EN_RX_HPF_SZ 1
+#define RG_EN_RX_RSSI_MSK 0x00800000
+#define RG_EN_RX_RSSI_I_MSK 0xff7fffff
+#define RG_EN_RX_RSSI_SFT 23
+#define RG_EN_RX_RSSI_HI 23
+#define RG_EN_RX_RSSI_SZ 1
+#define RG_EN_ADC_MSK 0x01000000
+#define RG_EN_ADC_I_MSK 0xfeffffff
+#define RG_EN_ADC_SFT 24
+#define RG_EN_ADC_HI 24
+#define RG_EN_ADC_SZ 1
+#define RG_EN_TX_MOD_MSK 0x02000000
+#define RG_EN_TX_MOD_I_MSK 0xfdffffff
+#define RG_EN_TX_MOD_SFT 25
+#define RG_EN_TX_MOD_HI 25
+#define RG_EN_TX_MOD_SZ 1
+#define RG_EN_TX_DIV2_MSK 0x04000000
+#define RG_EN_TX_DIV2_I_MSK 0xfbffffff
+#define RG_EN_TX_DIV2_SFT 26
+#define RG_EN_TX_DIV2_HI 26
+#define RG_EN_TX_DIV2_SZ 1
+#define RG_EN_TX_DIV2_BUF_MSK 0x08000000
+#define RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
+#define RG_EN_TX_DIV2_BUF_SFT 27
+#define RG_EN_TX_DIV2_BUF_HI 27
+#define RG_EN_TX_DIV2_BUF_SZ 1
+#define RG_EN_TX_LOBF_MSK 0x10000000
+#define RG_EN_TX_LOBF_I_MSK 0xefffffff
+#define RG_EN_TX_LOBF_SFT 28
+#define RG_EN_TX_LOBF_HI 28
+#define RG_EN_TX_LOBF_SZ 1
+#define RG_EN_RX_LOBF_MSK 0x20000000
+#define RG_EN_RX_LOBF_I_MSK 0xdfffffff
+#define RG_EN_RX_LOBF_SFT 29
+#define RG_EN_RX_LOBF_HI 29
+#define RG_EN_RX_LOBF_SZ 1
+#define RG_SEL_DPLL_CLK_MSK 0x40000000
+#define RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
+#define RG_SEL_DPLL_CLK_SFT 30
+#define RG_SEL_DPLL_CLK_HI 30
+#define RG_SEL_DPLL_CLK_SZ 1
+#define RG_EN_CLK_960MBY13_UART_MSK 0x80000000
+#define RG_EN_CLK_960MBY13_UART_I_MSK 0x7fffffff
+#define RG_EN_CLK_960MBY13_UART_SFT 31
+#define RG_EN_CLK_960MBY13_UART_HI 31
+#define RG_EN_CLK_960MBY13_UART_SZ 1
+#define RG_EN_TX_DPD_MSK 0x00000001
+#define RG_EN_TX_DPD_I_MSK 0xfffffffe
+#define RG_EN_TX_DPD_SFT 0
+#define RG_EN_TX_DPD_HI 0
+#define RG_EN_TX_DPD_SZ 1
+#define RG_EN_TX_TSSI_MSK 0x00000002
+#define RG_EN_TX_TSSI_I_MSK 0xfffffffd
+#define RG_EN_TX_TSSI_SFT 1
+#define RG_EN_TX_TSSI_HI 1
+#define RG_EN_TX_TSSI_SZ 1
+#define RG_EN_RX_IQCAL_MSK 0x00000004
+#define RG_EN_RX_IQCAL_I_MSK 0xfffffffb
+#define RG_EN_RX_IQCAL_SFT 2
+#define RG_EN_RX_IQCAL_HI 2
+#define RG_EN_RX_IQCAL_SZ 1
+#define RG_EN_TX_DAC_CAL_MSK 0x00000008
+#define RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
+#define RG_EN_TX_DAC_CAL_SFT 3
+#define RG_EN_TX_DAC_CAL_HI 3
+#define RG_EN_TX_DAC_CAL_SZ 1
+#define RG_EN_TX_SELF_MIXER_MSK 0x00000010
+#define RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
+#define RG_EN_TX_SELF_MIXER_SFT 4
+#define RG_EN_TX_SELF_MIXER_HI 4
+#define RG_EN_TX_SELF_MIXER_SZ 1
+#define RG_EN_TX_DAC_OUT_MSK 0x00000020
+#define RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
+#define RG_EN_TX_DAC_OUT_SFT 5
+#define RG_EN_TX_DAC_OUT_HI 5
+#define RG_EN_TX_DAC_OUT_SZ 1
+#define RG_EN_LDO_RX_FE_MSK 0x00000040
+#define RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
+#define RG_EN_LDO_RX_FE_SFT 6
+#define RG_EN_LDO_RX_FE_HI 6
+#define RG_EN_LDO_RX_FE_SZ 1
+#define RG_EN_LDO_ABB_MSK 0x00000080
+#define RG_EN_LDO_ABB_I_MSK 0xffffff7f
+#define RG_EN_LDO_ABB_SFT 7
+#define RG_EN_LDO_ABB_HI 7
+#define RG_EN_LDO_ABB_SZ 1
+#define RG_EN_LDO_AFE_MSK 0x00000100
+#define RG_EN_LDO_AFE_I_MSK 0xfffffeff
+#define RG_EN_LDO_AFE_SFT 8
+#define RG_EN_LDO_AFE_HI 8
+#define RG_EN_LDO_AFE_SZ 1
+#define RG_EN_SX_CHPLDO_MSK 0x00000200
+#define RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
+#define RG_EN_SX_CHPLDO_SFT 9
+#define RG_EN_SX_CHPLDO_HI 9
+#define RG_EN_SX_CHPLDO_SZ 1
+#define RG_EN_SX_LOBFLDO_MSK 0x00000400
+#define RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
+#define RG_EN_SX_LOBFLDO_SFT 10
+#define RG_EN_SX_LOBFLDO_HI 10
+#define RG_EN_SX_LOBFLDO_SZ 1
+#define RG_EN_IREF_RX_MSK 0x00000800
+#define RG_EN_IREF_RX_I_MSK 0xfffff7ff
+#define RG_EN_IREF_RX_SFT 11
+#define RG_EN_IREF_RX_HI 11
+#define RG_EN_IREF_RX_SZ 1
+#define RG_EN_TX_DAC_VOUT_MSK 0x00002000
+#define RG_EN_TX_DAC_VOUT_I_MSK 0xffffdfff
+#define RG_EN_TX_DAC_VOUT_SFT 13
+#define RG_EN_TX_DAC_VOUT_HI 13
+#define RG_EN_TX_DAC_VOUT_SZ 1
+#define RG_EN_SX_LCK_BIN_MSK 0x00004000
+#define RG_EN_SX_LCK_BIN_I_MSK 0xffffbfff
+#define RG_EN_SX_LCK_BIN_SFT 14
+#define RG_EN_SX_LCK_BIN_HI 14
+#define RG_EN_SX_LCK_BIN_SZ 1
+#define RG_RTC_CAL_MODE_MSK 0x00010000
+#define RG_RTC_CAL_MODE_I_MSK 0xfffeffff
+#define RG_RTC_CAL_MODE_SFT 16
+#define RG_RTC_CAL_MODE_HI 16
+#define RG_RTC_CAL_MODE_SZ 1
+#define RG_EN_IQPAD_IOSW_MSK 0x00020000
+#define RG_EN_IQPAD_IOSW_I_MSK 0xfffdffff
+#define RG_EN_IQPAD_IOSW_SFT 17
+#define RG_EN_IQPAD_IOSW_HI 17
+#define RG_EN_IQPAD_IOSW_SZ 1
+#define RG_EN_TESTPAD_IOSW_MSK 0x00040000
+#define RG_EN_TESTPAD_IOSW_I_MSK 0xfffbffff
+#define RG_EN_TESTPAD_IOSW_SFT 18
+#define RG_EN_TESTPAD_IOSW_HI 18
+#define RG_EN_TESTPAD_IOSW_SZ 1
+#define RG_EN_TRXBF_BYPASS_MSK 0x00080000
+#define RG_EN_TRXBF_BYPASS_I_MSK 0xfff7ffff
+#define RG_EN_TRXBF_BYPASS_SFT 19
+#define RG_EN_TRXBF_BYPASS_HI 19
+#define RG_EN_TRXBF_BYPASS_SZ 1
+#define RG_LDO_LEVEL_RX_FE_MSK 0x00000007
+#define RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
+#define RG_LDO_LEVEL_RX_FE_SFT 0
+#define RG_LDO_LEVEL_RX_FE_HI 2
+#define RG_LDO_LEVEL_RX_FE_SZ 3
+#define RG_LDO_LEVEL_ABB_MSK 0x00000038
+#define RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
+#define RG_LDO_LEVEL_ABB_SFT 3
+#define RG_LDO_LEVEL_ABB_HI 5
+#define RG_LDO_LEVEL_ABB_SZ 3
+#define RG_LDO_LEVEL_AFE_MSK 0x000001c0
+#define RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
+#define RG_LDO_LEVEL_AFE_SFT 6
+#define RG_LDO_LEVEL_AFE_HI 8
+#define RG_LDO_LEVEL_AFE_SZ 3
+#define RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
+#define RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
+#define RG_SX_LDO_CHP_LEVEL_SFT 9
+#define RG_SX_LDO_CHP_LEVEL_HI 11
+#define RG_SX_LDO_CHP_LEVEL_SZ 3
+#define RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
+#define RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
+#define RG_SX_LDO_LOBF_LEVEL_SFT 12
+#define RG_SX_LDO_LOBF_LEVEL_HI 14
+#define RG_SX_LDO_LOBF_LEVEL_SZ 3
+#define RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
+#define RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
+#define RG_SX_LDO_XOSC_LEVEL_SFT 15
+#define RG_SX_LDO_XOSC_LEVEL_HI 17
+#define RG_SX_LDO_XOSC_LEVEL_SZ 3
+#define RG_DP_LDO_LEVEL_MSK 0x001c0000
+#define RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
+#define RG_DP_LDO_LEVEL_SFT 18
+#define RG_DP_LDO_LEVEL_HI 20
+#define RG_DP_LDO_LEVEL_SZ 3
+#define RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
+#define RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
+#define RG_SX_LDO_VCO_LEVEL_SFT 21
+#define RG_SX_LDO_VCO_LEVEL_HI 23
+#define RG_SX_LDO_VCO_LEVEL_SZ 3
+#define RG_TX_LDO_TX_LEVEL_MSK 0x07000000
+#define RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
+#define RG_TX_LDO_TX_LEVEL_SFT 24
+#define RG_TX_LDO_TX_LEVEL_HI 26
+#define RG_TX_LDO_TX_LEVEL_SZ 3
+#define RG_EN_RX_PADSW_MSK 0x00000001
+#define RG_EN_RX_PADSW_I_MSK 0xfffffffe
+#define RG_EN_RX_PADSW_SFT 0
+#define RG_EN_RX_PADSW_HI 0
+#define RG_EN_RX_PADSW_SZ 1
+#define RG_EN_RX_TESTNODE_MSK 0x00000002
+#define RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
+#define RG_EN_RX_TESTNODE_SFT 1
+#define RG_EN_RX_TESTNODE_HI 1
+#define RG_EN_RX_TESTNODE_SZ 1
+#define RG_RX_ABBCFIX_MSK 0x00000004
+#define RG_RX_ABBCFIX_I_MSK 0xfffffffb
+#define RG_RX_ABBCFIX_SFT 2
+#define RG_RX_ABBCFIX_HI 2
+#define RG_RX_ABBCFIX_SZ 1
+#define RG_RX_ABBCTUNE_MSK 0x000001f8
+#define RG_RX_ABBCTUNE_I_MSK 0xfffffe07
+#define RG_RX_ABBCTUNE_SFT 3
+#define RG_RX_ABBCTUNE_HI 8
+#define RG_RX_ABBCTUNE_SZ 6
+#define RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
+#define RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
+#define RG_RX_ABBOUT_TRI_STATE_SFT 9
+#define RG_RX_ABBOUT_TRI_STATE_HI 9
+#define RG_RX_ABBOUT_TRI_STATE_SZ 1
+#define RG_RX_ABB_N_MODE_MSK 0x00000400
+#define RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
+#define RG_RX_ABB_N_MODE_SFT 10
+#define RG_RX_ABB_N_MODE_HI 10
+#define RG_RX_ABB_N_MODE_SZ 1
+#define RG_RX_EN_LOOPA_MSK 0x00000800
+#define RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
+#define RG_RX_EN_LOOPA_SFT 11
+#define RG_RX_EN_LOOPA_HI 11
+#define RG_RX_EN_LOOPA_SZ 1
+#define RG_RX_FILTERI1ST_MSK 0x00003000
+#define RG_RX_FILTERI1ST_I_MSK 0xffffcfff
+#define RG_RX_FILTERI1ST_SFT 12
+#define RG_RX_FILTERI1ST_HI 13
+#define RG_RX_FILTERI1ST_SZ 2
+#define RG_RX_FILTERI2ND_MSK 0x0000c000
+#define RG_RX_FILTERI2ND_I_MSK 0xffff3fff
+#define RG_RX_FILTERI2ND_SFT 14
+#define RG_RX_FILTERI2ND_HI 15
+#define RG_RX_FILTERI2ND_SZ 2
+#define RG_RX_FILTERI3RD_MSK 0x00030000
+#define RG_RX_FILTERI3RD_I_MSK 0xfffcffff
+#define RG_RX_FILTERI3RD_SFT 16
+#define RG_RX_FILTERI3RD_HI 17
+#define RG_RX_FILTERI3RD_SZ 2
+#define RG_RX_FILTERI_COURSE_MSK 0x000c0000
+#define RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
+#define RG_RX_FILTERI_COURSE_SFT 18
+#define RG_RX_FILTERI_COURSE_HI 19
+#define RG_RX_FILTERI_COURSE_SZ 2
+#define RG_RX_FILTERVCM_MSK 0x00300000
+#define RG_RX_FILTERVCM_I_MSK 0xffcfffff
+#define RG_RX_FILTERVCM_SFT 20
+#define RG_RX_FILTERVCM_HI 21
+#define RG_RX_FILTERVCM_SZ 2
+#define RG_RX_HPF3M_MSK 0x00400000
+#define RG_RX_HPF3M_I_MSK 0xffbfffff
+#define RG_RX_HPF3M_SFT 22
+#define RG_RX_HPF3M_HI 22
+#define RG_RX_HPF3M_SZ 1
+#define RG_RX_HPF300K_MSK 0x00800000
+#define RG_RX_HPF300K_I_MSK 0xff7fffff
+#define RG_RX_HPF300K_SFT 23
+#define RG_RX_HPF300K_HI 23
+#define RG_RX_HPF300K_SZ 1
+#define RG_RX_HPFI_MSK 0x03000000
+#define RG_RX_HPFI_I_MSK 0xfcffffff
+#define RG_RX_HPFI_SFT 24
+#define RG_RX_HPFI_HI 25
+#define RG_RX_HPFI_SZ 2
+#define RG_RX_HPF_FINALCORNER_MSK 0x0c000000
+#define RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
+#define RG_RX_HPF_FINALCORNER_SFT 26
+#define RG_RX_HPF_FINALCORNER_HI 27
+#define RG_RX_HPF_FINALCORNER_SZ 2
+#define RG_RX_HPF_SETTLE1_C_MSK 0x30000000
+#define RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
+#define RG_RX_HPF_SETTLE1_C_SFT 28
+#define RG_RX_HPF_SETTLE1_C_HI 29
+#define RG_RX_HPF_SETTLE1_C_SZ 2
+#define RG_RX_HPF_SETTLE1_R_MSK 0x00000003
+#define RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
+#define RG_RX_HPF_SETTLE1_R_SFT 0
+#define RG_RX_HPF_SETTLE1_R_HI 1
+#define RG_RX_HPF_SETTLE1_R_SZ 2
+#define RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
+#define RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
+#define RG_RX_HPF_SETTLE2_C_SFT 2
+#define RG_RX_HPF_SETTLE2_C_HI 3
+#define RG_RX_HPF_SETTLE2_C_SZ 2
+#define RG_RX_HPF_SETTLE2_R_MSK 0x00000030
+#define RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
+#define RG_RX_HPF_SETTLE2_R_SFT 4
+#define RG_RX_HPF_SETTLE2_R_HI 5
+#define RG_RX_HPF_SETTLE2_R_SZ 2
+#define RG_RX_HPF_VCMCON2_MSK 0x000000c0
+#define RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
+#define RG_RX_HPF_VCMCON2_SFT 6
+#define RG_RX_HPF_VCMCON2_HI 7
+#define RG_RX_HPF_VCMCON2_SZ 2
+#define RG_RX_HPF_VCMCON_MSK 0x00000300
+#define RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
+#define RG_RX_HPF_VCMCON_SFT 8
+#define RG_RX_HPF_VCMCON_HI 9
+#define RG_RX_HPF_VCMCON_SZ 2
+#define RG_RX_OUTVCM_MSK 0x00000c00
+#define RG_RX_OUTVCM_I_MSK 0xfffff3ff
+#define RG_RX_OUTVCM_SFT 10
+#define RG_RX_OUTVCM_HI 11
+#define RG_RX_OUTVCM_SZ 2
+#define RG_RX_TZI_MSK 0x00003000
+#define RG_RX_TZI_I_MSK 0xffffcfff
+#define RG_RX_TZI_SFT 12
+#define RG_RX_TZI_HI 13
+#define RG_RX_TZI_SZ 2
+#define RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
+#define RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
+#define RG_RX_TZ_OUT_TRISTATE_SFT 14
+#define RG_RX_TZ_OUT_TRISTATE_HI 14
+#define RG_RX_TZ_OUT_TRISTATE_SZ 1
+#define RG_RX_TZ_VCM_MSK 0x00018000
+#define RG_RX_TZ_VCM_I_MSK 0xfffe7fff
+#define RG_RX_TZ_VCM_SFT 15
+#define RG_RX_TZ_VCM_HI 16
+#define RG_RX_TZ_VCM_SZ 2
+#define RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
+#define RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
+#define RG_EN_RX_RSSI_TESTNODE_SFT 17
+#define RG_EN_RX_RSSI_TESTNODE_HI 19
+#define RG_EN_RX_RSSI_TESTNODE_SZ 3
+#define RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
+#define RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
+#define RG_RX_ADCRSSI_CLKSEL_SFT 20
+#define RG_RX_ADCRSSI_CLKSEL_HI 20
+#define RG_RX_ADCRSSI_CLKSEL_SZ 1
+#define RG_RX_ADCRSSI_VCM_MSK 0x00600000
+#define RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
+#define RG_RX_ADCRSSI_VCM_SFT 21
+#define RG_RX_ADCRSSI_VCM_HI 22
+#define RG_RX_ADCRSSI_VCM_SZ 2
+#define RG_RX_REC_LPFCORNER_MSK 0x01800000
+#define RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
+#define RG_RX_REC_LPFCORNER_SFT 23
+#define RG_RX_REC_LPFCORNER_HI 24
+#define RG_RX_REC_LPFCORNER_SZ 2
+#define RG_RSSI_CLOCK_GATING_MSK 0x02000000
+#define RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
+#define RG_RSSI_CLOCK_GATING_SFT 25
+#define RG_RSSI_CLOCK_GATING_HI 25
+#define RG_RSSI_CLOCK_GATING_SZ 1
+#define RG_TXPGA_CAPSW_MSK 0x00000003
+#define RG_TXPGA_CAPSW_I_MSK 0xfffffffc
+#define RG_TXPGA_CAPSW_SFT 0
+#define RG_TXPGA_CAPSW_HI 1
+#define RG_TXPGA_CAPSW_SZ 2
+#define RG_TXPGA_MAIN_MSK 0x000000fc
+#define RG_TXPGA_MAIN_I_MSK 0xffffff03
+#define RG_TXPGA_MAIN_SFT 2
+#define RG_TXPGA_MAIN_HI 7
+#define RG_TXPGA_MAIN_SZ 6
+#define RG_TXPGA_STEER_MSK 0x00003f00
+#define RG_TXPGA_STEER_I_MSK 0xffffc0ff
+#define RG_TXPGA_STEER_SFT 8
+#define RG_TXPGA_STEER_HI 13
+#define RG_TXPGA_STEER_SZ 6
+#define RG_TXMOD_GMCELL_MSK 0x0000c000
+#define RG_TXMOD_GMCELL_I_MSK 0xffff3fff
+#define RG_TXMOD_GMCELL_SFT 14
+#define RG_TXMOD_GMCELL_HI 15
+#define RG_TXMOD_GMCELL_SZ 2
+#define RG_TXLPF_GMCELL_MSK 0x00030000
+#define RG_TXLPF_GMCELL_I_MSK 0xfffcffff
+#define RG_TXLPF_GMCELL_SFT 16
+#define RG_TXLPF_GMCELL_HI 17
+#define RG_TXLPF_GMCELL_SZ 2
+#define RG_PACELL_EN_MSK 0x001c0000
+#define RG_PACELL_EN_I_MSK 0xffe3ffff
+#define RG_PACELL_EN_SFT 18
+#define RG_PACELL_EN_HI 20
+#define RG_PACELL_EN_SZ 3
+#define RG_PABIAS_CTRL_MSK 0x01e00000
+#define RG_PABIAS_CTRL_I_MSK 0xfe1fffff
+#define RG_PABIAS_CTRL_SFT 21
+#define RG_PABIAS_CTRL_HI 24
+#define RG_PABIAS_CTRL_SZ 4
+#define RG_TX_DIV_VSET_MSK 0x0c000000
+#define RG_TX_DIV_VSET_I_MSK 0xf3ffffff
+#define RG_TX_DIV_VSET_SFT 26
+#define RG_TX_DIV_VSET_HI 27
+#define RG_TX_DIV_VSET_SZ 2
+#define RG_TX_LOBUF_VSET_MSK 0x30000000
+#define RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
+#define RG_TX_LOBUF_VSET_SFT 28
+#define RG_TX_LOBUF_VSET_HI 29
+#define RG_TX_LOBUF_VSET_SZ 2
+#define RG_RX_SQDC_MSK 0x00000007
+#define RG_RX_SQDC_I_MSK 0xfffffff8
+#define RG_RX_SQDC_SFT 0
+#define RG_RX_SQDC_HI 2
+#define RG_RX_SQDC_SZ 3
+#define RG_RX_DIV2_CORE_MSK 0x00000018
+#define RG_RX_DIV2_CORE_I_MSK 0xffffffe7
+#define RG_RX_DIV2_CORE_SFT 3
+#define RG_RX_DIV2_CORE_HI 4
+#define RG_RX_DIV2_CORE_SZ 2
+#define RG_RX_LOBUF_MSK 0x00000060
+#define RG_RX_LOBUF_I_MSK 0xffffff9f
+#define RG_RX_LOBUF_SFT 5
+#define RG_RX_LOBUF_HI 6
+#define RG_RX_LOBUF_SZ 2
+#define RG_TX_DPDGM_BIAS_MSK 0x00000780
+#define RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
+#define RG_TX_DPDGM_BIAS_SFT 7
+#define RG_TX_DPDGM_BIAS_HI 10
+#define RG_TX_DPDGM_BIAS_SZ 4
+#define RG_TX_DPD_DIV_MSK 0x00007800
+#define RG_TX_DPD_DIV_I_MSK 0xffff87ff
+#define RG_TX_DPD_DIV_SFT 11
+#define RG_TX_DPD_DIV_HI 14
+#define RG_TX_DPD_DIV_SZ 4
+#define RG_TX_TSSI_BIAS_MSK 0x00038000
+#define RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
+#define RG_TX_TSSI_BIAS_SFT 15
+#define RG_TX_TSSI_BIAS_HI 17
+#define RG_TX_TSSI_BIAS_SZ 3
+#define RG_TX_TSSI_DIV_MSK 0x001c0000
+#define RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
+#define RG_TX_TSSI_DIV_SFT 18
+#define RG_TX_TSSI_DIV_HI 20
+#define RG_TX_TSSI_DIV_SZ 3
+#define RG_TX_TSSI_TESTMODE_MSK 0x00200000
+#define RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
+#define RG_TX_TSSI_TESTMODE_SFT 21
+#define RG_TX_TSSI_TESTMODE_HI 21
+#define RG_TX_TSSI_TESTMODE_SZ 1
+#define RG_TX_TSSI_TEST_MSK 0x00c00000
+#define RG_TX_TSSI_TEST_I_MSK 0xff3fffff
+#define RG_TX_TSSI_TEST_SFT 22
+#define RG_TX_TSSI_TEST_HI 23
+#define RG_TX_TSSI_TEST_SZ 2
+#define RG_PACASCODE_CTRL_MSK 0x07000000
+#define RG_PACASCODE_CTRL_I_MSK 0xf8ffffff
+#define RG_PACASCODE_CTRL_SFT 24
+#define RG_PACASCODE_CTRL_HI 26
+#define RG_PACASCODE_CTRL_SZ 3
+#define RG_RX_HG_LNA_GC_MSK 0x00000003
+#define RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_HG_LNA_GC_SFT 0
+#define RG_RX_HG_LNA_GC_HI 1
+#define RG_RX_HG_LNA_GC_SZ 2
+#define RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_HG_LNAHGN_BIAS_SFT 2
+#define RG_RX_HG_LNAHGN_BIAS_HI 5
+#define RG_RX_HG_LNAHGN_BIAS_SZ 4
+#define RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_HG_LNAHGP_BIAS_SFT 6
+#define RG_RX_HG_LNAHGP_BIAS_HI 9
+#define RG_RX_HG_LNAHGP_BIAS_SZ 4
+#define RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_HG_LNALG_BIAS_SFT 10
+#define RG_RX_HG_LNALG_BIAS_HI 13
+#define RG_RX_HG_LNALG_BIAS_SZ 4
+#define RG_RX_HG_TZ_GC_MSK 0x0000c000
+#define RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_HG_TZ_GC_SFT 14
+#define RG_RX_HG_TZ_GC_HI 15
+#define RG_RX_HG_TZ_GC_SZ 2
+#define RG_RX_HG_TZ_CAP_MSK 0x00070000
+#define RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_HG_TZ_CAP_SFT 16
+#define RG_RX_HG_TZ_CAP_HI 18
+#define RG_RX_HG_TZ_CAP_SZ 3
+#define RG_RX_MG_LNA_GC_MSK 0x00000003
+#define RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_MG_LNA_GC_SFT 0
+#define RG_RX_MG_LNA_GC_HI 1
+#define RG_RX_MG_LNA_GC_SZ 2
+#define RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_MG_LNAHGN_BIAS_SFT 2
+#define RG_RX_MG_LNAHGN_BIAS_HI 5
+#define RG_RX_MG_LNAHGN_BIAS_SZ 4
+#define RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_MG_LNAHGP_BIAS_SFT 6
+#define RG_RX_MG_LNAHGP_BIAS_HI 9
+#define RG_RX_MG_LNAHGP_BIAS_SZ 4
+#define RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_MG_LNALG_BIAS_SFT 10
+#define RG_RX_MG_LNALG_BIAS_HI 13
+#define RG_RX_MG_LNALG_BIAS_SZ 4
+#define RG_RX_MG_TZ_GC_MSK 0x0000c000
+#define RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_MG_TZ_GC_SFT 14
+#define RG_RX_MG_TZ_GC_HI 15
+#define RG_RX_MG_TZ_GC_SZ 2
+#define RG_RX_MG_TZ_CAP_MSK 0x00070000
+#define RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_MG_TZ_CAP_SFT 16
+#define RG_RX_MG_TZ_CAP_HI 18
+#define RG_RX_MG_TZ_CAP_SZ 3
+#define RG_RX_LG_LNA_GC_MSK 0x00000003
+#define RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_LG_LNA_GC_SFT 0
+#define RG_RX_LG_LNA_GC_HI 1
+#define RG_RX_LG_LNA_GC_SZ 2
+#define RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_LG_LNAHGN_BIAS_SFT 2
+#define RG_RX_LG_LNAHGN_BIAS_HI 5
+#define RG_RX_LG_LNAHGN_BIAS_SZ 4
+#define RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_LG_LNAHGP_BIAS_SFT 6
+#define RG_RX_LG_LNAHGP_BIAS_HI 9
+#define RG_RX_LG_LNAHGP_BIAS_SZ 4
+#define RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_LG_LNALG_BIAS_SFT 10
+#define RG_RX_LG_LNALG_BIAS_HI 13
+#define RG_RX_LG_LNALG_BIAS_SZ 4
+#define RG_RX_LG_TZ_GC_MSK 0x0000c000
+#define RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_LG_TZ_GC_SFT 14
+#define RG_RX_LG_TZ_GC_HI 15
+#define RG_RX_LG_TZ_GC_SZ 2
+#define RG_RX_LG_TZ_CAP_MSK 0x00070000
+#define RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_LG_TZ_CAP_SFT 16
+#define RG_RX_LG_TZ_CAP_HI 18
+#define RG_RX_LG_TZ_CAP_SZ 3
+#define RG_RX_ULG_LNA_GC_MSK 0x00000003
+#define RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_ULG_LNA_GC_SFT 0
+#define RG_RX_ULG_LNA_GC_HI 1
+#define RG_RX_ULG_LNA_GC_SZ 2
+#define RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_ULG_LNAHGN_BIAS_SFT 2
+#define RG_RX_ULG_LNAHGN_BIAS_HI 5
+#define RG_RX_ULG_LNAHGN_BIAS_SZ 4
+#define RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_ULG_LNAHGP_BIAS_SFT 6
+#define RG_RX_ULG_LNAHGP_BIAS_HI 9
+#define RG_RX_ULG_LNAHGP_BIAS_SZ 4
+#define RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_ULG_LNALG_BIAS_SFT 10
+#define RG_RX_ULG_LNALG_BIAS_HI 13
+#define RG_RX_ULG_LNALG_BIAS_SZ 4
+#define RG_RX_ULG_TZ_GC_MSK 0x0000c000
+#define RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_ULG_TZ_GC_SFT 14
+#define RG_RX_ULG_TZ_GC_HI 15
+#define RG_RX_ULG_TZ_GC_SZ 2
+#define RG_RX_ULG_TZ_CAP_MSK 0x00070000
+#define RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_ULG_TZ_CAP_SFT 16
+#define RG_RX_ULG_TZ_CAP_HI 18
+#define RG_RX_ULG_TZ_CAP_SZ 3
+#define RG_HPF1_FAST_SET_X_MSK 0x00000001
+#define RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
+#define RG_HPF1_FAST_SET_X_SFT 0
+#define RG_HPF1_FAST_SET_X_HI 0
+#define RG_HPF1_FAST_SET_X_SZ 1
+#define RG_HPF1_FAST_SET_Y_MSK 0x00000002
+#define RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
+#define RG_HPF1_FAST_SET_Y_SFT 1
+#define RG_HPF1_FAST_SET_Y_HI 1
+#define RG_HPF1_FAST_SET_Y_SZ 1
+#define RG_HPF1_FAST_SET_Z_MSK 0x00000004
+#define RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
+#define RG_HPF1_FAST_SET_Z_SFT 2
+#define RG_HPF1_FAST_SET_Z_HI 2
+#define RG_HPF1_FAST_SET_Z_SZ 1
+#define RG_HPF_T1A_MSK 0x00000018
+#define RG_HPF_T1A_I_MSK 0xffffffe7
+#define RG_HPF_T1A_SFT 3
+#define RG_HPF_T1A_HI 4
+#define RG_HPF_T1A_SZ 2
+#define RG_HPF_T1B_MSK 0x00000060
+#define RG_HPF_T1B_I_MSK 0xffffff9f
+#define RG_HPF_T1B_SFT 5
+#define RG_HPF_T1B_HI 6
+#define RG_HPF_T1B_SZ 2
+#define RG_HPF_T1C_MSK 0x00000180
+#define RG_HPF_T1C_I_MSK 0xfffffe7f
+#define RG_HPF_T1C_SFT 7
+#define RG_HPF_T1C_HI 8
+#define RG_HPF_T1C_SZ 2
+#define RG_RX_LNA_TRI_SEL_MSK 0x00000600
+#define RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
+#define RG_RX_LNA_TRI_SEL_SFT 9
+#define RG_RX_LNA_TRI_SEL_HI 10
+#define RG_RX_LNA_TRI_SEL_SZ 2
+#define RG_RX_LNA_SETTLE_MSK 0x00001800
+#define RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
+#define RG_RX_LNA_SETTLE_SFT 11
+#define RG_RX_LNA_SETTLE_HI 12
+#define RG_RX_LNA_SETTLE_SZ 2
+#define RG_TXGAIN_PHYCTRL_MSK 0x00002000
+#define RG_TXGAIN_PHYCTRL_I_MSK 0xffffdfff
+#define RG_TXGAIN_PHYCTRL_SFT 13
+#define RG_TXGAIN_PHYCTRL_HI 13
+#define RG_TXGAIN_PHYCTRL_SZ 1
+#define RG_TX_GAIN_MSK 0x003fc000
+#define RG_TX_GAIN_I_MSK 0xffc03fff
+#define RG_TX_GAIN_SFT 14
+#define RG_TX_GAIN_HI 21
+#define RG_TX_GAIN_SZ 8
+#define RG_TXGAIN_MANUAL_MSK 0x00400000
+#define RG_TXGAIN_MANUAL_I_MSK 0xffbfffff
+#define RG_TXGAIN_MANUAL_SFT 22
+#define RG_TXGAIN_MANUAL_HI 22
+#define RG_TXGAIN_MANUAL_SZ 1
+#define RG_TX_GAIN_OFFSET_MSK 0x07800000
+#define RG_TX_GAIN_OFFSET_I_MSK 0xf87fffff
+#define RG_TX_GAIN_OFFSET_SFT 23
+#define RG_TX_GAIN_OFFSET_HI 26
+#define RG_TX_GAIN_OFFSET_SZ 4
+#define RG_ADC_CLKSEL_MSK 0x00000001
+#define RG_ADC_CLKSEL_I_MSK 0xfffffffe
+#define RG_ADC_CLKSEL_SFT 0
+#define RG_ADC_CLKSEL_HI 0
+#define RG_ADC_CLKSEL_SZ 1
+#define RG_ADC_DIBIAS_MSK 0x00000006
+#define RG_ADC_DIBIAS_I_MSK 0xfffffff9
+#define RG_ADC_DIBIAS_SFT 1
+#define RG_ADC_DIBIAS_HI 2
+#define RG_ADC_DIBIAS_SZ 2
+#define RG_ADC_DIVR_MSK 0x00000008
+#define RG_ADC_DIVR_I_MSK 0xfffffff7
+#define RG_ADC_DIVR_SFT 3
+#define RG_ADC_DIVR_HI 3
+#define RG_ADC_DIVR_SZ 1
+#define RG_ADC_DVCMI_MSK 0x00000030
+#define RG_ADC_DVCMI_I_MSK 0xffffffcf
+#define RG_ADC_DVCMI_SFT 4
+#define RG_ADC_DVCMI_HI 5
+#define RG_ADC_DVCMI_SZ 2
+#define RG_ADC_SAMSEL_MSK 0x000003c0
+#define RG_ADC_SAMSEL_I_MSK 0xfffffc3f
+#define RG_ADC_SAMSEL_SFT 6
+#define RG_ADC_SAMSEL_HI 9
+#define RG_ADC_SAMSEL_SZ 4
+#define RG_ADC_STNBY_MSK 0x00000400
+#define RG_ADC_STNBY_I_MSK 0xfffffbff
+#define RG_ADC_STNBY_SFT 10
+#define RG_ADC_STNBY_HI 10
+#define RG_ADC_STNBY_SZ 1
+#define RG_ADC_TESTMODE_MSK 0x00000800
+#define RG_ADC_TESTMODE_I_MSK 0xfffff7ff
+#define RG_ADC_TESTMODE_SFT 11
+#define RG_ADC_TESTMODE_HI 11
+#define RG_ADC_TESTMODE_SZ 1
+#define RG_ADC_TSEL_MSK 0x0000f000
+#define RG_ADC_TSEL_I_MSK 0xffff0fff
+#define RG_ADC_TSEL_SFT 12
+#define RG_ADC_TSEL_HI 15
+#define RG_ADC_TSEL_SZ 4
+#define RG_ADC_VRSEL_MSK 0x00030000
+#define RG_ADC_VRSEL_I_MSK 0xfffcffff
+#define RG_ADC_VRSEL_SFT 16
+#define RG_ADC_VRSEL_HI 17
+#define RG_ADC_VRSEL_SZ 2
+#define RG_DICMP_MSK 0x000c0000
+#define RG_DICMP_I_MSK 0xfff3ffff
+#define RG_DICMP_SFT 18
+#define RG_DICMP_HI 19
+#define RG_DICMP_SZ 2
+#define RG_DIOP_MSK 0x00300000
+#define RG_DIOP_I_MSK 0xffcfffff
+#define RG_DIOP_SFT 20
+#define RG_DIOP_HI 21
+#define RG_DIOP_SZ 2
+#define RG_SARADC_VRSEL_MSK 0x00c00000
+#define RG_SARADC_VRSEL_I_MSK 0xff3fffff
+#define RG_SARADC_VRSEL_SFT 22
+#define RG_SARADC_VRSEL_HI 23
+#define RG_SARADC_VRSEL_SZ 2
+#define RG_EN_SAR_TEST_MSK 0x03000000
+#define RG_EN_SAR_TEST_I_MSK 0xfcffffff
+#define RG_EN_SAR_TEST_SFT 24
+#define RG_EN_SAR_TEST_HI 25
+#define RG_EN_SAR_TEST_SZ 2
+#define RG_SARADC_THERMAL_MSK 0x04000000
+#define RG_SARADC_THERMAL_I_MSK 0xfbffffff
+#define RG_SARADC_THERMAL_SFT 26
+#define RG_SARADC_THERMAL_HI 26
+#define RG_SARADC_THERMAL_SZ 1
+#define RG_SARADC_TSSI_MSK 0x08000000
+#define RG_SARADC_TSSI_I_MSK 0xf7ffffff
+#define RG_SARADC_TSSI_SFT 27
+#define RG_SARADC_TSSI_HI 27
+#define RG_SARADC_TSSI_SZ 1
+#define RG_CLK_SAR_SEL_MSK 0x30000000
+#define RG_CLK_SAR_SEL_I_MSK 0xcfffffff
+#define RG_CLK_SAR_SEL_SFT 28
+#define RG_CLK_SAR_SEL_HI 29
+#define RG_CLK_SAR_SEL_SZ 2
+#define RG_EN_SARADC_MSK 0x40000000
+#define RG_EN_SARADC_I_MSK 0xbfffffff
+#define RG_EN_SARADC_SFT 30
+#define RG_EN_SARADC_HI 30
+#define RG_EN_SARADC_SZ 1
+#define RG_DACI1ST_MSK 0x00000003
+#define RG_DACI1ST_I_MSK 0xfffffffc
+#define RG_DACI1ST_SFT 0
+#define RG_DACI1ST_HI 1
+#define RG_DACI1ST_SZ 2
+#define RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
+#define RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
+#define RG_TX_DACLPF_ICOURSE_SFT 2
+#define RG_TX_DACLPF_ICOURSE_HI 3
+#define RG_TX_DACLPF_ICOURSE_SZ 2
+#define RG_TX_DACLPF_IFINE_MSK 0x00000030
+#define RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define RG_TX_DACLPF_IFINE_SFT 4
+#define RG_TX_DACLPF_IFINE_HI 5
+#define RG_TX_DACLPF_IFINE_SZ 2
+#define RG_TX_DACLPF_VCM_MSK 0x000000c0
+#define RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define RG_TX_DACLPF_VCM_SFT 6
+#define RG_TX_DACLPF_VCM_HI 7
+#define RG_TX_DACLPF_VCM_SZ 2
+#define RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
+#define RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
+#define RG_TX_DAC_CKEDGE_SEL_SFT 8
+#define RG_TX_DAC_CKEDGE_SEL_HI 8
+#define RG_TX_DAC_CKEDGE_SEL_SZ 1
+#define RG_TX_DAC_IBIAS_MSK 0x00000600
+#define RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
+#define RG_TX_DAC_IBIAS_SFT 9
+#define RG_TX_DAC_IBIAS_HI 10
+#define RG_TX_DAC_IBIAS_SZ 2
+#define RG_TX_DAC_OS_MSK 0x00003800
+#define RG_TX_DAC_OS_I_MSK 0xffffc7ff
+#define RG_TX_DAC_OS_SFT 11
+#define RG_TX_DAC_OS_HI 13
+#define RG_TX_DAC_OS_SZ 3
+#define RG_TX_DAC_RCAL_MSK 0x0000c000
+#define RG_TX_DAC_RCAL_I_MSK 0xffff3fff
+#define RG_TX_DAC_RCAL_SFT 14
+#define RG_TX_DAC_RCAL_HI 15
+#define RG_TX_DAC_RCAL_SZ 2
+#define RG_TX_DAC_TSEL_MSK 0x000f0000
+#define RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
+#define RG_TX_DAC_TSEL_SFT 16
+#define RG_TX_DAC_TSEL_HI 19
+#define RG_TX_DAC_TSEL_SZ 4
+#define RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
+#define RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
+#define RG_TX_EN_VOLTAGE_IN_SFT 20
+#define RG_TX_EN_VOLTAGE_IN_HI 20
+#define RG_TX_EN_VOLTAGE_IN_SZ 1
+#define RG_TXLPF_BYPASS_MSK 0x00200000
+#define RG_TXLPF_BYPASS_I_MSK 0xffdfffff
+#define RG_TXLPF_BYPASS_SFT 21
+#define RG_TXLPF_BYPASS_HI 21
+#define RG_TXLPF_BYPASS_SZ 1
+#define RG_TXLPF_BOOSTI_MSK 0x00400000
+#define RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
+#define RG_TXLPF_BOOSTI_SFT 22
+#define RG_TXLPF_BOOSTI_HI 22
+#define RG_TXLPF_BOOSTI_SZ 1
+#define RG_TX_DAC_IOFFSET_MSK 0x07800000
+#define RG_TX_DAC_IOFFSET_I_MSK 0xf87fffff
+#define RG_TX_DAC_IOFFSET_SFT 23
+#define RG_TX_DAC_IOFFSET_HI 26
+#define RG_TX_DAC_IOFFSET_SZ 4
+#define RG_TX_DAC_QOFFSET_MSK 0x78000000
+#define RG_TX_DAC_QOFFSET_I_MSK 0x87ffffff
+#define RG_TX_DAC_QOFFSET_SFT 27
+#define RG_TX_DAC_QOFFSET_HI 30
+#define RG_TX_DAC_QOFFSET_SZ 4
+#define RG_EN_SX_R3_MSK 0x00000001
+#define RG_EN_SX_R3_I_MSK 0xfffffffe
+#define RG_EN_SX_R3_SFT 0
+#define RG_EN_SX_R3_HI 0
+#define RG_EN_SX_R3_SZ 1
+#define RG_EN_SX_CH_MSK 0x00000002
+#define RG_EN_SX_CH_I_MSK 0xfffffffd
+#define RG_EN_SX_CH_SFT 1
+#define RG_EN_SX_CH_HI 1
+#define RG_EN_SX_CH_SZ 1
+#define RG_EN_SX_CHP_MSK 0x00000004
+#define RG_EN_SX_CHP_I_MSK 0xfffffffb
+#define RG_EN_SX_CHP_SFT 2
+#define RG_EN_SX_CHP_HI 2
+#define RG_EN_SX_CHP_SZ 1
+#define RG_EN_SX_DIVCK_MSK 0x00000008
+#define RG_EN_SX_DIVCK_I_MSK 0xfffffff7
+#define RG_EN_SX_DIVCK_SFT 3
+#define RG_EN_SX_DIVCK_HI 3
+#define RG_EN_SX_DIVCK_SZ 1
+#define RG_EN_SX_VCOBF_MSK 0x00000010
+#define RG_EN_SX_VCOBF_I_MSK 0xffffffef
+#define RG_EN_SX_VCOBF_SFT 4
+#define RG_EN_SX_VCOBF_HI 4
+#define RG_EN_SX_VCOBF_SZ 1
+#define RG_EN_SX_VCO_MSK 0x00000020
+#define RG_EN_SX_VCO_I_MSK 0xffffffdf
+#define RG_EN_SX_VCO_SFT 5
+#define RG_EN_SX_VCO_HI 5
+#define RG_EN_SX_VCO_SZ 1
+#define RG_EN_SX_MOD_MSK 0x00000040
+#define RG_EN_SX_MOD_I_MSK 0xffffffbf
+#define RG_EN_SX_MOD_SFT 6
+#define RG_EN_SX_MOD_HI 6
+#define RG_EN_SX_MOD_SZ 1
+#define RG_EN_SX_DITHER_MSK 0x00000100
+#define RG_EN_SX_DITHER_I_MSK 0xfffffeff
+#define RG_EN_SX_DITHER_SFT 8
+#define RG_EN_SX_DITHER_HI 8
+#define RG_EN_SX_DITHER_SZ 1
+#define RG_EN_SX_VT_MON_MSK 0x00000800
+#define RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
+#define RG_EN_SX_VT_MON_SFT 11
+#define RG_EN_SX_VT_MON_HI 11
+#define RG_EN_SX_VT_MON_SZ 1
+#define RG_EN_SX_VT_MON_DG_MSK 0x00001000
+#define RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
+#define RG_EN_SX_VT_MON_DG_SFT 12
+#define RG_EN_SX_VT_MON_DG_HI 12
+#define RG_EN_SX_VT_MON_DG_SZ 1
+#define RG_EN_SX_DIV_MSK 0x00002000
+#define RG_EN_SX_DIV_I_MSK 0xffffdfff
+#define RG_EN_SX_DIV_SFT 13
+#define RG_EN_SX_DIV_HI 13
+#define RG_EN_SX_DIV_SZ 1
+#define RG_EN_SX_LPF_MSK 0x00004000
+#define RG_EN_SX_LPF_I_MSK 0xffffbfff
+#define RG_EN_SX_LPF_SFT 14
+#define RG_EN_SX_LPF_HI 14
+#define RG_EN_SX_LPF_SZ 1
+#define RG_EN_DPL_MOD_MSK 0x00008000
+#define RG_EN_DPL_MOD_I_MSK 0xffff7fff
+#define RG_EN_DPL_MOD_SFT 15
+#define RG_EN_DPL_MOD_HI 15
+#define RG_EN_DPL_MOD_SZ 1
+#define RG_DPL_MOD_ORDER_MSK 0x00030000
+#define RG_DPL_MOD_ORDER_I_MSK 0xfffcffff
+#define RG_DPL_MOD_ORDER_SFT 16
+#define RG_DPL_MOD_ORDER_HI 17
+#define RG_DPL_MOD_ORDER_SZ 2
+#define RG_SX_RFCTRL_F_MSK 0x00ffffff
+#define RG_SX_RFCTRL_F_I_MSK 0xff000000
+#define RG_SX_RFCTRL_F_SFT 0
+#define RG_SX_RFCTRL_F_HI 23
+#define RG_SX_RFCTRL_F_SZ 24
+#define RG_SX_SEL_CP_MSK 0x0f000000
+#define RG_SX_SEL_CP_I_MSK 0xf0ffffff
+#define RG_SX_SEL_CP_SFT 24
+#define RG_SX_SEL_CP_HI 27
+#define RG_SX_SEL_CP_SZ 4
+#define RG_SX_SEL_CS_MSK 0xf0000000
+#define RG_SX_SEL_CS_I_MSK 0x0fffffff
+#define RG_SX_SEL_CS_SFT 28
+#define RG_SX_SEL_CS_HI 31
+#define RG_SX_SEL_CS_SZ 4
+#define RG_SX_RFCTRL_CH_MSK 0x000007ff
+#define RG_SX_RFCTRL_CH_I_MSK 0xfffff800
+#define RG_SX_RFCTRL_CH_SFT 0
+#define RG_SX_RFCTRL_CH_HI 10
+#define RG_SX_RFCTRL_CH_SZ 11
+#define RG_SX_SEL_C3_MSK 0x00007800
+#define RG_SX_SEL_C3_I_MSK 0xffff87ff
+#define RG_SX_SEL_C3_SFT 11
+#define RG_SX_SEL_C3_HI 14
+#define RG_SX_SEL_C3_SZ 4
+#define RG_SX_SEL_RS_MSK 0x000f8000
+#define RG_SX_SEL_RS_I_MSK 0xfff07fff
+#define RG_SX_SEL_RS_SFT 15
+#define RG_SX_SEL_RS_HI 19
+#define RG_SX_SEL_RS_SZ 5
+#define RG_SX_SEL_R3_MSK 0x01f00000
+#define RG_SX_SEL_R3_I_MSK 0xfe0fffff
+#define RG_SX_SEL_R3_SFT 20
+#define RG_SX_SEL_R3_HI 24
+#define RG_SX_SEL_R3_SZ 5
+#define RG_SX_SEL_ICHP_MSK 0x0000001f
+#define RG_SX_SEL_ICHP_I_MSK 0xffffffe0
+#define RG_SX_SEL_ICHP_SFT 0
+#define RG_SX_SEL_ICHP_HI 4
+#define RG_SX_SEL_ICHP_SZ 5
+#define RG_SX_SEL_PCHP_MSK 0x000003e0
+#define RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
+#define RG_SX_SEL_PCHP_SFT 5
+#define RG_SX_SEL_PCHP_HI 9
+#define RG_SX_SEL_PCHP_SZ 5
+#define RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
+#define RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
+#define RG_SX_SEL_CHP_REGOP_SFT 10
+#define RG_SX_SEL_CHP_REGOP_HI 13
+#define RG_SX_SEL_CHP_REGOP_SZ 4
+#define RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
+#define RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
+#define RG_SX_SEL_CHP_UNIOP_SFT 14
+#define RG_SX_SEL_CHP_UNIOP_HI 17
+#define RG_SX_SEL_CHP_UNIOP_SZ 4
+#define RG_SX_CHP_IOST_POL_MSK 0x00040000
+#define RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
+#define RG_SX_CHP_IOST_POL_SFT 18
+#define RG_SX_CHP_IOST_POL_HI 18
+#define RG_SX_CHP_IOST_POL_SZ 1
+#define RG_SX_CHP_IOST_MSK 0x00380000
+#define RG_SX_CHP_IOST_I_MSK 0xffc7ffff
+#define RG_SX_CHP_IOST_SFT 19
+#define RG_SX_CHP_IOST_HI 21
+#define RG_SX_CHP_IOST_SZ 3
+#define RG_SX_PFDSEL_MSK 0x00400000
+#define RG_SX_PFDSEL_I_MSK 0xffbfffff
+#define RG_SX_PFDSEL_SFT 22
+#define RG_SX_PFDSEL_HI 22
+#define RG_SX_PFDSEL_SZ 1
+#define RG_SX_PFD_SET_MSK 0x00800000
+#define RG_SX_PFD_SET_I_MSK 0xff7fffff
+#define RG_SX_PFD_SET_SFT 23
+#define RG_SX_PFD_SET_HI 23
+#define RG_SX_PFD_SET_SZ 1
+#define RG_SX_PFD_SET1_MSK 0x01000000
+#define RG_SX_PFD_SET1_I_MSK 0xfeffffff
+#define RG_SX_PFD_SET1_SFT 24
+#define RG_SX_PFD_SET1_HI 24
+#define RG_SX_PFD_SET1_SZ 1
+#define RG_SX_PFD_SET2_MSK 0x02000000
+#define RG_SX_PFD_SET2_I_MSK 0xfdffffff
+#define RG_SX_PFD_SET2_SFT 25
+#define RG_SX_PFD_SET2_HI 25
+#define RG_SX_PFD_SET2_SZ 1
+#define RG_SX_VBNCAS_SEL_MSK 0x04000000
+#define RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
+#define RG_SX_VBNCAS_SEL_SFT 26
+#define RG_SX_VBNCAS_SEL_HI 26
+#define RG_SX_VBNCAS_SEL_SZ 1
+#define RG_SX_PFD_RST_H_MSK 0x08000000
+#define RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
+#define RG_SX_PFD_RST_H_SFT 27
+#define RG_SX_PFD_RST_H_HI 27
+#define RG_SX_PFD_RST_H_SZ 1
+#define RG_SX_PFD_TRUP_MSK 0x10000000
+#define RG_SX_PFD_TRUP_I_MSK 0xefffffff
+#define RG_SX_PFD_TRUP_SFT 28
+#define RG_SX_PFD_TRUP_HI 28
+#define RG_SX_PFD_TRUP_SZ 1
+#define RG_SX_PFD_TRDN_MSK 0x20000000
+#define RG_SX_PFD_TRDN_I_MSK 0xdfffffff
+#define RG_SX_PFD_TRDN_SFT 29
+#define RG_SX_PFD_TRDN_HI 29
+#define RG_SX_PFD_TRDN_SZ 1
+#define RG_SX_PFD_TRSEL_MSK 0x40000000
+#define RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
+#define RG_SX_PFD_TRSEL_SFT 30
+#define RG_SX_PFD_TRSEL_HI 30
+#define RG_SX_PFD_TRSEL_SZ 1
+#define RG_SX_VCOBA_R_MSK 0x00000007
+#define RG_SX_VCOBA_R_I_MSK 0xfffffff8
+#define RG_SX_VCOBA_R_SFT 0
+#define RG_SX_VCOBA_R_HI 2
+#define RG_SX_VCOBA_R_SZ 3
+#define RG_SX_VCORSEL_MSK 0x000000f8
+#define RG_SX_VCORSEL_I_MSK 0xffffff07
+#define RG_SX_VCORSEL_SFT 3
+#define RG_SX_VCORSEL_HI 7
+#define RG_SX_VCORSEL_SZ 5
+#define RG_SX_VCOCUSEL_MSK 0x00000f00
+#define RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
+#define RG_SX_VCOCUSEL_SFT 8
+#define RG_SX_VCOCUSEL_HI 11
+#define RG_SX_VCOCUSEL_SZ 4
+#define RG_SX_RXBFSEL_MSK 0x0000f000
+#define RG_SX_RXBFSEL_I_MSK 0xffff0fff
+#define RG_SX_RXBFSEL_SFT 12
+#define RG_SX_RXBFSEL_HI 15
+#define RG_SX_RXBFSEL_SZ 4
+#define RG_SX_TXBFSEL_MSK 0x000f0000
+#define RG_SX_TXBFSEL_I_MSK 0xfff0ffff
+#define RG_SX_TXBFSEL_SFT 16
+#define RG_SX_TXBFSEL_HI 19
+#define RG_SX_TXBFSEL_SZ 4
+#define RG_SX_VCOBFSEL_MSK 0x00f00000
+#define RG_SX_VCOBFSEL_I_MSK 0xff0fffff
+#define RG_SX_VCOBFSEL_SFT 20
+#define RG_SX_VCOBFSEL_HI 23
+#define RG_SX_VCOBFSEL_SZ 4
+#define RG_SX_DIVBFSEL_MSK 0x0f000000
+#define RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
+#define RG_SX_DIVBFSEL_SFT 24
+#define RG_SX_DIVBFSEL_HI 27
+#define RG_SX_DIVBFSEL_SZ 4
+#define RG_SX_GNDR_SEL_MSK 0xf0000000
+#define RG_SX_GNDR_SEL_I_MSK 0x0fffffff
+#define RG_SX_GNDR_SEL_SFT 28
+#define RG_SX_GNDR_SEL_HI 31
+#define RG_SX_GNDR_SEL_SZ 4
+#define RG_SX_DITHER_WEIGHT_MSK 0x00000003
+#define RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
+#define RG_SX_DITHER_WEIGHT_SFT 0
+#define RG_SX_DITHER_WEIGHT_HI 1
+#define RG_SX_DITHER_WEIGHT_SZ 2
+#define RG_SX_MOD_ORDER_MSK 0x00000030
+#define RG_SX_MOD_ORDER_I_MSK 0xffffffcf
+#define RG_SX_MOD_ORDER_SFT 4
+#define RG_SX_MOD_ORDER_HI 5
+#define RG_SX_MOD_ORDER_SZ 2
+#define RG_SX_RST_H_DIV_MSK 0x00000200
+#define RG_SX_RST_H_DIV_I_MSK 0xfffffdff
+#define RG_SX_RST_H_DIV_SFT 9
+#define RG_SX_RST_H_DIV_HI 9
+#define RG_SX_RST_H_DIV_SZ 1
+#define RG_SX_SDM_EDGE_MSK 0x00000400
+#define RG_SX_SDM_EDGE_I_MSK 0xfffffbff
+#define RG_SX_SDM_EDGE_SFT 10
+#define RG_SX_SDM_EDGE_HI 10
+#define RG_SX_SDM_EDGE_SZ 1
+#define RG_SX_XO_GM_MSK 0x00001800
+#define RG_SX_XO_GM_I_MSK 0xffffe7ff
+#define RG_SX_XO_GM_SFT 11
+#define RG_SX_XO_GM_HI 12
+#define RG_SX_XO_GM_SZ 2
+#define RG_SX_REFBYTWO_MSK 0x00002000
+#define RG_SX_REFBYTWO_I_MSK 0xffffdfff
+#define RG_SX_REFBYTWO_SFT 13
+#define RG_SX_REFBYTWO_HI 13
+#define RG_SX_REFBYTWO_SZ 1
+#define RG_SX_LCKEN_MSK 0x00080000
+#define RG_SX_LCKEN_I_MSK 0xfff7ffff
+#define RG_SX_LCKEN_SFT 19
+#define RG_SX_LCKEN_HI 19
+#define RG_SX_LCKEN_SZ 1
+#define RG_SX_PREVDD_MSK 0x00f00000
+#define RG_SX_PREVDD_I_MSK 0xff0fffff
+#define RG_SX_PREVDD_SFT 20
+#define RG_SX_PREVDD_HI 23
+#define RG_SX_PREVDD_SZ 4
+#define RG_SX_PSCONTERVDD_MSK 0x0f000000
+#define RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
+#define RG_SX_PSCONTERVDD_SFT 24
+#define RG_SX_PSCONTERVDD_HI 27
+#define RG_SX_PSCONTERVDD_SZ 4
+#define RG_SX_PH_MSK 0x00002000
+#define RG_SX_PH_I_MSK 0xffffdfff
+#define RG_SX_PH_SFT 13
+#define RG_SX_PH_HI 13
+#define RG_SX_PH_SZ 1
+#define RG_SX_PL_MSK 0x00004000
+#define RG_SX_PL_I_MSK 0xffffbfff
+#define RG_SX_PL_SFT 14
+#define RG_SX_PL_HI 14
+#define RG_SX_PL_SZ 1
+#define RG_XOSC_CBANK_XO_MSK 0x00078000
+#define RG_XOSC_CBANK_XO_I_MSK 0xfff87fff
+#define RG_XOSC_CBANK_XO_SFT 15
+#define RG_XOSC_CBANK_XO_HI 18
+#define RG_XOSC_CBANK_XO_SZ 4
+#define RG_XOSC_CBANK_XI_MSK 0x00780000
+#define RG_XOSC_CBANK_XI_I_MSK 0xff87ffff
+#define RG_XOSC_CBANK_XI_SFT 19
+#define RG_XOSC_CBANK_XI_HI 22
+#define RG_XOSC_CBANK_XI_SZ 4
+#define RG_SX_VT_MON_MODE_MSK 0x00000001
+#define RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
+#define RG_SX_VT_MON_MODE_SFT 0
+#define RG_SX_VT_MON_MODE_HI 0
+#define RG_SX_VT_MON_MODE_SZ 1
+#define RG_SX_VT_TH_HI_MSK 0x00000006
+#define RG_SX_VT_TH_HI_I_MSK 0xfffffff9
+#define RG_SX_VT_TH_HI_SFT 1
+#define RG_SX_VT_TH_HI_HI 2
+#define RG_SX_VT_TH_HI_SZ 2
+#define RG_SX_VT_TH_LO_MSK 0x00000018
+#define RG_SX_VT_TH_LO_I_MSK 0xffffffe7
+#define RG_SX_VT_TH_LO_SFT 3
+#define RG_SX_VT_TH_LO_HI 4
+#define RG_SX_VT_TH_LO_SZ 2
+#define RG_SX_VT_SET_MSK 0x00000020
+#define RG_SX_VT_SET_I_MSK 0xffffffdf
+#define RG_SX_VT_SET_SFT 5
+#define RG_SX_VT_SET_HI 5
+#define RG_SX_VT_SET_SZ 1
+#define RG_SX_VT_MON_TMR_MSK 0x00007fc0
+#define RG_SX_VT_MON_TMR_I_MSK 0xffff803f
+#define RG_SX_VT_MON_TMR_SFT 6
+#define RG_SX_VT_MON_TMR_HI 14
+#define RG_SX_VT_MON_TMR_SZ 9
+#define RG_EN_DP_VT_MON_MSK 0x00000001
+#define RG_EN_DP_VT_MON_I_MSK 0xfffffffe
+#define RG_EN_DP_VT_MON_SFT 0
+#define RG_EN_DP_VT_MON_HI 0
+#define RG_EN_DP_VT_MON_SZ 1
+#define RG_DP_VT_TH_HI_MSK 0x00000006
+#define RG_DP_VT_TH_HI_I_MSK 0xfffffff9
+#define RG_DP_VT_TH_HI_SFT 1
+#define RG_DP_VT_TH_HI_HI 2
+#define RG_DP_VT_TH_HI_SZ 2
+#define RG_DP_VT_TH_LO_MSK 0x00000018
+#define RG_DP_VT_TH_LO_I_MSK 0xffffffe7
+#define RG_DP_VT_TH_LO_SFT 3
+#define RG_DP_VT_TH_LO_HI 4
+#define RG_DP_VT_TH_LO_SZ 2
+#define RG_DP_CK320BY2_MSK 0x00004000
+#define RG_DP_CK320BY2_I_MSK 0xffffbfff
+#define RG_DP_CK320BY2_SFT 14
+#define RG_DP_CK320BY2_HI 14
+#define RG_DP_CK320BY2_SZ 1
+#define RG_DP_OD_TEST_MSK 0x00200000
+#define RG_DP_OD_TEST_I_MSK 0xffdfffff
+#define RG_DP_OD_TEST_SFT 21
+#define RG_DP_OD_TEST_HI 21
+#define RG_DP_OD_TEST_SZ 1
+#define RG_DP_BBPLL_BP_MSK 0x00000001
+#define RG_DP_BBPLL_BP_I_MSK 0xfffffffe
+#define RG_DP_BBPLL_BP_SFT 0
+#define RG_DP_BBPLL_BP_HI 0
+#define RG_DP_BBPLL_BP_SZ 1
+#define RG_DP_BBPLL_ICP_MSK 0x00000006
+#define RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
+#define RG_DP_BBPLL_ICP_SFT 1
+#define RG_DP_BBPLL_ICP_HI 2
+#define RG_DP_BBPLL_ICP_SZ 2
+#define RG_DP_BBPLL_IDUAL_MSK 0x00000018
+#define RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
+#define RG_DP_BBPLL_IDUAL_SFT 3
+#define RG_DP_BBPLL_IDUAL_HI 4
+#define RG_DP_BBPLL_IDUAL_SZ 2
+#define RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
+#define RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
+#define RG_DP_BBPLL_OD_TEST_SFT 5
+#define RG_DP_BBPLL_OD_TEST_HI 8
+#define RG_DP_BBPLL_OD_TEST_SZ 4
+#define RG_DP_BBPLL_PD_MSK 0x00000200
+#define RG_DP_BBPLL_PD_I_MSK 0xfffffdff
+#define RG_DP_BBPLL_PD_SFT 9
+#define RG_DP_BBPLL_PD_HI 9
+#define RG_DP_BBPLL_PD_SZ 1
+#define RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
+#define RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
+#define RG_DP_BBPLL_TESTSEL_SFT 10
+#define RG_DP_BBPLL_TESTSEL_HI 12
+#define RG_DP_BBPLL_TESTSEL_SZ 3
+#define RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
+#define RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
+#define RG_DP_BBPLL_PFD_DLY_SFT 13
+#define RG_DP_BBPLL_PFD_DLY_HI 14
+#define RG_DP_BBPLL_PFD_DLY_SZ 2
+#define RG_DP_RP_MSK 0x00038000
+#define RG_DP_RP_I_MSK 0xfffc7fff
+#define RG_DP_RP_SFT 15
+#define RG_DP_RP_HI 17
+#define RG_DP_RP_SZ 3
+#define RG_DP_RHP_MSK 0x000c0000
+#define RG_DP_RHP_I_MSK 0xfff3ffff
+#define RG_DP_RHP_SFT 18
+#define RG_DP_RHP_HI 19
+#define RG_DP_RHP_SZ 2
+#define RG_DP_BBPLL_SDM_EDGE_MSK 0x80000000
+#define RG_DP_BBPLL_SDM_EDGE_I_MSK 0x7fffffff
+#define RG_DP_BBPLL_SDM_EDGE_SFT 31
+#define RG_DP_BBPLL_SDM_EDGE_HI 31
+#define RG_DP_BBPLL_SDM_EDGE_SZ 1
+#define RG_DP_FODIV_MSK 0x0007f000
+#define RG_DP_FODIV_I_MSK 0xfff80fff
+#define RG_DP_FODIV_SFT 12
+#define RG_DP_FODIV_HI 18
+#define RG_DP_FODIV_SZ 7
+#define RG_DP_REFDIV_MSK 0x1fc00000
+#define RG_DP_REFDIV_I_MSK 0xe03fffff
+#define RG_DP_REFDIV_SFT 22
+#define RG_DP_REFDIV_HI 28
+#define RG_DP_REFDIV_SZ 7
+#define RG_IDACAI_PGAG15_MSK 0x0000003f
+#define RG_IDACAI_PGAG15_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG15_SFT 0
+#define RG_IDACAI_PGAG15_HI 5
+#define RG_IDACAI_PGAG15_SZ 6
+#define RG_IDACAQ_PGAG15_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG15_SFT 6
+#define RG_IDACAQ_PGAG15_HI 11
+#define RG_IDACAQ_PGAG15_SZ 6
+#define RG_IDACAI_PGAG14_MSK 0x0003f000
+#define RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG14_SFT 12
+#define RG_IDACAI_PGAG14_HI 17
+#define RG_IDACAI_PGAG14_SZ 6
+#define RG_IDACAQ_PGAG14_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG14_SFT 18
+#define RG_IDACAQ_PGAG14_HI 23
+#define RG_IDACAQ_PGAG14_SZ 6
+#define RG_DP_BBPLL_BS_MSK 0x3f000000
+#define RG_DP_BBPLL_BS_I_MSK 0xc0ffffff
+#define RG_DP_BBPLL_BS_SFT 24
+#define RG_DP_BBPLL_BS_HI 29
+#define RG_DP_BBPLL_BS_SZ 6
+#define RG_IDACAI_PGAG13_MSK 0x0000003f
+#define RG_IDACAI_PGAG13_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG13_SFT 0
+#define RG_IDACAI_PGAG13_HI 5
+#define RG_IDACAI_PGAG13_SZ 6
+#define RG_IDACAQ_PGAG13_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG13_SFT 6
+#define RG_IDACAQ_PGAG13_HI 11
+#define RG_IDACAQ_PGAG13_SZ 6
+#define RG_IDACAI_PGAG12_MSK 0x0003f000
+#define RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG12_SFT 12
+#define RG_IDACAI_PGAG12_HI 17
+#define RG_IDACAI_PGAG12_SZ 6
+#define RG_IDACAQ_PGAG12_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG12_SFT 18
+#define RG_IDACAQ_PGAG12_HI 23
+#define RG_IDACAQ_PGAG12_SZ 6
+#define RG_IDACAI_PGAG11_MSK 0x0000003f
+#define RG_IDACAI_PGAG11_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG11_SFT 0
+#define RG_IDACAI_PGAG11_HI 5
+#define RG_IDACAI_PGAG11_SZ 6
+#define RG_IDACAQ_PGAG11_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG11_SFT 6
+#define RG_IDACAQ_PGAG11_HI 11
+#define RG_IDACAQ_PGAG11_SZ 6
+#define RG_IDACAI_PGAG10_MSK 0x0003f000
+#define RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG10_SFT 12
+#define RG_IDACAI_PGAG10_HI 17
+#define RG_IDACAI_PGAG10_SZ 6
+#define RG_IDACAQ_PGAG10_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG10_SFT 18
+#define RG_IDACAQ_PGAG10_HI 23
+#define RG_IDACAQ_PGAG10_SZ 6
+#define RG_IDACAI_PGAG9_MSK 0x0000003f
+#define RG_IDACAI_PGAG9_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG9_SFT 0
+#define RG_IDACAI_PGAG9_HI 5
+#define RG_IDACAI_PGAG9_SZ 6
+#define RG_IDACAQ_PGAG9_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG9_SFT 6
+#define RG_IDACAQ_PGAG9_HI 11
+#define RG_IDACAQ_PGAG9_SZ 6
+#define RG_IDACAI_PGAG8_MSK 0x0003f000
+#define RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG8_SFT 12
+#define RG_IDACAI_PGAG8_HI 17
+#define RG_IDACAI_PGAG8_SZ 6
+#define RG_IDACAQ_PGAG8_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG8_SFT 18
+#define RG_IDACAQ_PGAG8_HI 23
+#define RG_IDACAQ_PGAG8_SZ 6
+#define RG_IDACAI_PGAG7_MSK 0x0000003f
+#define RG_IDACAI_PGAG7_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG7_SFT 0
+#define RG_IDACAI_PGAG7_HI 5
+#define RG_IDACAI_PGAG7_SZ 6
+#define RG_IDACAQ_PGAG7_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG7_SFT 6
+#define RG_IDACAQ_PGAG7_HI 11
+#define RG_IDACAQ_PGAG7_SZ 6
+#define RG_IDACAI_PGAG6_MSK 0x0003f000
+#define RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG6_SFT 12
+#define RG_IDACAI_PGAG6_HI 17
+#define RG_IDACAI_PGAG6_SZ 6
+#define RG_IDACAQ_PGAG6_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG6_SFT 18
+#define RG_IDACAQ_PGAG6_HI 23
+#define RG_IDACAQ_PGAG6_SZ 6
+#define RG_IDACAI_PGAG5_MSK 0x0000003f
+#define RG_IDACAI_PGAG5_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG5_SFT 0
+#define RG_IDACAI_PGAG5_HI 5
+#define RG_IDACAI_PGAG5_SZ 6
+#define RG_IDACAQ_PGAG5_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG5_SFT 6
+#define RG_IDACAQ_PGAG5_HI 11
+#define RG_IDACAQ_PGAG5_SZ 6
+#define RG_IDACAI_PGAG4_MSK 0x0003f000
+#define RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG4_SFT 12
+#define RG_IDACAI_PGAG4_HI 17
+#define RG_IDACAI_PGAG4_SZ 6
+#define RG_IDACAQ_PGAG4_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG4_SFT 18
+#define RG_IDACAQ_PGAG4_HI 23
+#define RG_IDACAQ_PGAG4_SZ 6
+#define RG_IDACAI_PGAG3_MSK 0x0000003f
+#define RG_IDACAI_PGAG3_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG3_SFT 0
+#define RG_IDACAI_PGAG3_HI 5
+#define RG_IDACAI_PGAG3_SZ 6
+#define RG_IDACAQ_PGAG3_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG3_SFT 6
+#define RG_IDACAQ_PGAG3_HI 11
+#define RG_IDACAQ_PGAG3_SZ 6
+#define RG_IDACAI_PGAG2_MSK 0x0003f000
+#define RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG2_SFT 12
+#define RG_IDACAI_PGAG2_HI 17
+#define RG_IDACAI_PGAG2_SZ 6
+#define RG_IDACAQ_PGAG2_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG2_SFT 18
+#define RG_IDACAQ_PGAG2_HI 23
+#define RG_IDACAQ_PGAG2_SZ 6
+#define RG_IDACAI_PGAG1_MSK 0x0000003f
+#define RG_IDACAI_PGAG1_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG1_SFT 0
+#define RG_IDACAI_PGAG1_HI 5
+#define RG_IDACAI_PGAG1_SZ 6
+#define RG_IDACAQ_PGAG1_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG1_SFT 6
+#define RG_IDACAQ_PGAG1_HI 11
+#define RG_IDACAQ_PGAG1_SZ 6
+#define RG_IDACAI_PGAG0_MSK 0x0003f000
+#define RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG0_SFT 12
+#define RG_IDACAI_PGAG0_HI 17
+#define RG_IDACAI_PGAG0_SZ 6
+#define RG_IDACAQ_PGAG0_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG0_SFT 18
+#define RG_IDACAQ_PGAG0_HI 23
+#define RG_IDACAQ_PGAG0_SZ 6
+#define RG_EN_RCAL_MSK 0x00000001
+#define RG_EN_RCAL_I_MSK 0xfffffffe
+#define RG_EN_RCAL_SFT 0
+#define RG_EN_RCAL_HI 0
+#define RG_EN_RCAL_SZ 1
+#define RG_RCAL_SPD_MSK 0x00000002
+#define RG_RCAL_SPD_I_MSK 0xfffffffd
+#define RG_RCAL_SPD_SFT 1
+#define RG_RCAL_SPD_HI 1
+#define RG_RCAL_SPD_SZ 1
+#define RG_RCAL_TMR_MSK 0x000001fc
+#define RG_RCAL_TMR_I_MSK 0xfffffe03
+#define RG_RCAL_TMR_SFT 2
+#define RG_RCAL_TMR_HI 8
+#define RG_RCAL_TMR_SZ 7
+#define RG_RCAL_CODE_CWR_MSK 0x00000200
+#define RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
+#define RG_RCAL_CODE_CWR_SFT 9
+#define RG_RCAL_CODE_CWR_HI 9
+#define RG_RCAL_CODE_CWR_SZ 1
+#define RG_RCAL_CODE_CWD_MSK 0x00007c00
+#define RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
+#define RG_RCAL_CODE_CWD_SFT 10
+#define RG_RCAL_CODE_CWD_HI 14
+#define RG_RCAL_CODE_CWD_SZ 5
+#define RG_SX_SUB_SEL_CWR_MSK 0x00000001
+#define RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
+#define RG_SX_SUB_SEL_CWR_SFT 0
+#define RG_SX_SUB_SEL_CWR_HI 0
+#define RG_SX_SUB_SEL_CWR_SZ 1
+#define RG_SX_SUB_SEL_CWD_MSK 0x000000fe
+#define RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
+#define RG_SX_SUB_SEL_CWD_SFT 1
+#define RG_SX_SUB_SEL_CWD_HI 7
+#define RG_SX_SUB_SEL_CWD_SZ 7
+#define RG_SX_LCK_BIN_OFFSET_MSK 0x00078000
+#define RG_SX_LCK_BIN_OFFSET_I_MSK 0xfff87fff
+#define RG_SX_LCK_BIN_OFFSET_SFT 15
+#define RG_SX_LCK_BIN_OFFSET_HI 18
+#define RG_SX_LCK_BIN_OFFSET_SZ 4
+#define RG_SX_LCK_BIN_PRECISION_MSK 0x00080000
+#define RG_SX_LCK_BIN_PRECISION_I_MSK 0xfff7ffff
+#define RG_SX_LCK_BIN_PRECISION_SFT 19
+#define RG_SX_LCK_BIN_PRECISION_HI 19
+#define RG_SX_LCK_BIN_PRECISION_SZ 1
+#define RG_SX_LOCK_EN_N_MSK 0x00100000
+#define RG_SX_LOCK_EN_N_I_MSK 0xffefffff
+#define RG_SX_LOCK_EN_N_SFT 20
+#define RG_SX_LOCK_EN_N_HI 20
+#define RG_SX_LOCK_EN_N_SZ 1
+#define RG_SX_LOCK_MANUAL_MSK 0x00200000
+#define RG_SX_LOCK_MANUAL_I_MSK 0xffdfffff
+#define RG_SX_LOCK_MANUAL_SFT 21
+#define RG_SX_LOCK_MANUAL_HI 21
+#define RG_SX_LOCK_MANUAL_SZ 1
+#define RG_SX_SUB_MANUAL_MSK 0x00400000
+#define RG_SX_SUB_MANUAL_I_MSK 0xffbfffff
+#define RG_SX_SUB_MANUAL_SFT 22
+#define RG_SX_SUB_MANUAL_HI 22
+#define RG_SX_SUB_MANUAL_SZ 1
+#define RG_SX_SUB_SEL_MSK 0x3f800000
+#define RG_SX_SUB_SEL_I_MSK 0xc07fffff
+#define RG_SX_SUB_SEL_SFT 23
+#define RG_SX_SUB_SEL_HI 29
+#define RG_SX_SUB_SEL_SZ 7
+#define RG_SX_MUX_SEL_VTH_BINL_MSK 0x40000000
+#define RG_SX_MUX_SEL_VTH_BINL_I_MSK 0xbfffffff
+#define RG_SX_MUX_SEL_VTH_BINL_SFT 30
+#define RG_SX_MUX_SEL_VTH_BINL_HI 30
+#define RG_SX_MUX_SEL_VTH_BINL_SZ 1
+#define RG_TRX_DUMMMY_MSK 0xffffffff
+#define RG_TRX_DUMMMY_I_MSK 0x00000000
+#define RG_TRX_DUMMMY_SFT 0
+#define RG_TRX_DUMMMY_HI 31
+#define RG_TRX_DUMMMY_SZ 32
+#define RG_SX_DUMMMY_MSK 0xffffffff
+#define RG_SX_DUMMMY_I_MSK 0x00000000
+#define RG_SX_DUMMMY_SFT 0
+#define RG_SX_DUMMMY_HI 31
+#define RG_SX_DUMMMY_SZ 32
+#define RCAL_RDY_MSK 0x00000001
+#define RCAL_RDY_I_MSK 0xfffffffe
+#define RCAL_RDY_SFT 0
+#define RCAL_RDY_HI 0
+#define RCAL_RDY_SZ 1
+#define LCK_BIN_RDY_MSK 0x00000002
+#define LCK_BIN_RDY_I_MSK 0xfffffffd
+#define LCK_BIN_RDY_SFT 1
+#define LCK_BIN_RDY_HI 1
+#define LCK_BIN_RDY_SZ 1
+#define VT_MON_RDY_MSK 0x00000004
+#define VT_MON_RDY_I_MSK 0xfffffffb
+#define VT_MON_RDY_SFT 2
+#define VT_MON_RDY_HI 2
+#define VT_MON_RDY_SZ 1
+#define DA_R_CODE_LUT_MSK 0x000007c0
+#define DA_R_CODE_LUT_I_MSK 0xfffff83f
+#define DA_R_CODE_LUT_SFT 6
+#define DA_R_CODE_LUT_HI 10
+#define DA_R_CODE_LUT_SZ 5
+#define AD_SX_VT_MON_Q_MSK 0x00001800
+#define AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
+#define AD_SX_VT_MON_Q_SFT 11
+#define AD_SX_VT_MON_Q_HI 12
+#define AD_SX_VT_MON_Q_SZ 2
+#define AD_DP_VT_MON_Q_MSK 0x00006000
+#define AD_DP_VT_MON_Q_I_MSK 0xffff9fff
+#define AD_DP_VT_MON_Q_SFT 13
+#define AD_DP_VT_MON_Q_HI 14
+#define AD_DP_VT_MON_Q_SZ 2
+#define RTC_CAL_RDY_MSK 0x00008000
+#define RTC_CAL_RDY_I_MSK 0xffff7fff
+#define RTC_CAL_RDY_SFT 15
+#define RTC_CAL_RDY_HI 15
+#define RTC_CAL_RDY_SZ 1
+#define RG_SARADC_BIT_MSK 0x003f0000
+#define RG_SARADC_BIT_I_MSK 0xffc0ffff
+#define RG_SARADC_BIT_SFT 16
+#define RG_SARADC_BIT_HI 21
+#define RG_SARADC_BIT_SZ 6
+#define SAR_ADC_FSM_RDY_MSK 0x00400000
+#define SAR_ADC_FSM_RDY_I_MSK 0xffbfffff
+#define SAR_ADC_FSM_RDY_SFT 22
+#define SAR_ADC_FSM_RDY_HI 22
+#define SAR_ADC_FSM_RDY_SZ 1
+#define AD_CIRCUIT_VERSION_MSK 0x07800000
+#define AD_CIRCUIT_VERSION_I_MSK 0xf87fffff
+#define AD_CIRCUIT_VERSION_SFT 23
+#define AD_CIRCUIT_VERSION_HI 26
+#define AD_CIRCUIT_VERSION_SZ 4
+#define DA_R_CAL_CODE_MSK 0x0000001f
+#define DA_R_CAL_CODE_I_MSK 0xffffffe0
+#define DA_R_CAL_CODE_SFT 0
+#define DA_R_CAL_CODE_HI 4
+#define DA_R_CAL_CODE_SZ 5
+#define DA_SX_SUB_SEL_MSK 0x00000fe0
+#define DA_SX_SUB_SEL_I_MSK 0xfffff01f
+#define DA_SX_SUB_SEL_SFT 5
+#define DA_SX_SUB_SEL_HI 11
+#define DA_SX_SUB_SEL_SZ 7
+#define RG_DPL_RFCTRL_CH_MSK 0x000007ff
+#define RG_DPL_RFCTRL_CH_I_MSK 0xfffff800
+#define RG_DPL_RFCTRL_CH_SFT 0
+#define RG_DPL_RFCTRL_CH_HI 10
+#define RG_DPL_RFCTRL_CH_SZ 11
+#define RG_RSSIADC_RO_BIT_MSK 0x00007800
+#define RG_RSSIADC_RO_BIT_I_MSK 0xffff87ff
+#define RG_RSSIADC_RO_BIT_SFT 11
+#define RG_RSSIADC_RO_BIT_HI 14
+#define RG_RSSIADC_RO_BIT_SZ 4
+#define RG_RX_ADC_I_RO_BIT_MSK 0x007f8000
+#define RG_RX_ADC_I_RO_BIT_I_MSK 0xff807fff
+#define RG_RX_ADC_I_RO_BIT_SFT 15
+#define RG_RX_ADC_I_RO_BIT_HI 22
+#define RG_RX_ADC_I_RO_BIT_SZ 8
+#define RG_RX_ADC_Q_RO_BIT_MSK 0x7f800000
+#define RG_RX_ADC_Q_RO_BIT_I_MSK 0x807fffff
+#define RG_RX_ADC_Q_RO_BIT_SFT 23
+#define RG_RX_ADC_Q_RO_BIT_HI 30
+#define RG_RX_ADC_Q_RO_BIT_SZ 8
+#define RG_DPL_RFCTRL_F_MSK 0x00ffffff
+#define RG_DPL_RFCTRL_F_I_MSK 0xff000000
+#define RG_DPL_RFCTRL_F_SFT 0
+#define RG_DPL_RFCTRL_F_HI 23
+#define RG_DPL_RFCTRL_F_SZ 24
+#define RG_SX_TARGET_CNT_MSK 0x00001fff
+#define RG_SX_TARGET_CNT_I_MSK 0xffffe000
+#define RG_SX_TARGET_CNT_SFT 0
+#define RG_SX_TARGET_CNT_HI 12
+#define RG_SX_TARGET_CNT_SZ 13
+#define RG_RTC_OFFSET_MSK 0x000000ff
+#define RG_RTC_OFFSET_I_MSK 0xffffff00
+#define RG_RTC_OFFSET_SFT 0
+#define RG_RTC_OFFSET_HI 7
+#define RG_RTC_OFFSET_SZ 8
+#define RG_RTC_CAL_TARGET_COUNT_MSK 0x000fff00
+#define RG_RTC_CAL_TARGET_COUNT_I_MSK 0xfff000ff
+#define RG_RTC_CAL_TARGET_COUNT_SFT 8
+#define RG_RTC_CAL_TARGET_COUNT_HI 19
+#define RG_RTC_CAL_TARGET_COUNT_SZ 12
+#define RG_RF_D_REG_MSK 0x0000ffff
+#define RG_RF_D_REG_I_MSK 0xffff0000
+#define RG_RF_D_REG_SFT 0
+#define RG_RF_D_REG_HI 15
+#define RG_RF_D_REG_SZ 16
+#define DIRECT_MODE_MSK 0x00000001
+#define DIRECT_MODE_I_MSK 0xfffffffe
+#define DIRECT_MODE_SFT 0
+#define DIRECT_MODE_HI 0
+#define DIRECT_MODE_SZ 1
+#define TAG_INTERLEAVE_MD_MSK 0x00000002
+#define TAG_INTERLEAVE_MD_I_MSK 0xfffffffd
+#define TAG_INTERLEAVE_MD_SFT 1
+#define TAG_INTERLEAVE_MD_HI 1
+#define TAG_INTERLEAVE_MD_SZ 1
+#define DIS_DEMAND_MSK 0x00000004
+#define DIS_DEMAND_I_MSK 0xfffffffb
+#define DIS_DEMAND_SFT 2
+#define DIS_DEMAND_HI 2
+#define DIS_DEMAND_SZ 1
+#define SAME_ID_ALLOC_MD_MSK 0x00000008
+#define SAME_ID_ALLOC_MD_I_MSK 0xfffffff7
+#define SAME_ID_ALLOC_MD_SFT 3
+#define SAME_ID_ALLOC_MD_HI 3
+#define SAME_ID_ALLOC_MD_SZ 1
+#define HS_ACCESS_MD_MSK 0x00000010
+#define HS_ACCESS_MD_I_MSK 0xffffffef
+#define HS_ACCESS_MD_SFT 4
+#define HS_ACCESS_MD_HI 4
+#define HS_ACCESS_MD_SZ 1
+#define SRAM_ACCESS_MD_MSK 0x00000020
+#define SRAM_ACCESS_MD_I_MSK 0xffffffdf
+#define SRAM_ACCESS_MD_SFT 5
+#define SRAM_ACCESS_MD_HI 5
+#define SRAM_ACCESS_MD_SZ 1
+#define NOHIT_RPASS_MD_MSK 0x00000040
+#define NOHIT_RPASS_MD_I_MSK 0xffffffbf
+#define NOHIT_RPASS_MD_SFT 6
+#define NOHIT_RPASS_MD_HI 6
+#define NOHIT_RPASS_MD_SZ 1
+#define DMN_FLAG_CLR_MSK 0x00000080
+#define DMN_FLAG_CLR_I_MSK 0xffffff7f
+#define DMN_FLAG_CLR_SFT 7
+#define DMN_FLAG_CLR_HI 7
+#define DMN_FLAG_CLR_SZ 1
+#define ERR_SW_RST_N_MSK 0x00000100
+#define ERR_SW_RST_N_I_MSK 0xfffffeff
+#define ERR_SW_RST_N_SFT 8
+#define ERR_SW_RST_N_HI 8
+#define ERR_SW_RST_N_SZ 1
+#define ALR_SW_RST_N_MSK 0x00000200
+#define ALR_SW_RST_N_I_MSK 0xfffffdff
+#define ALR_SW_RST_N_SFT 9
+#define ALR_SW_RST_N_HI 9
+#define ALR_SW_RST_N_SZ 1
+#define MCH_SW_RST_N_MSK 0x00000400
+#define MCH_SW_RST_N_I_MSK 0xfffffbff
+#define MCH_SW_RST_N_SFT 10
+#define MCH_SW_RST_N_HI 10
+#define MCH_SW_RST_N_SZ 1
+#define TAG_SW_RST_N_MSK 0x00000800
+#define TAG_SW_RST_N_I_MSK 0xfffff7ff
+#define TAG_SW_RST_N_SFT 11
+#define TAG_SW_RST_N_HI 11
+#define TAG_SW_RST_N_SZ 1
+#define ABT_SW_RST_N_MSK 0x00001000
+#define ABT_SW_RST_N_I_MSK 0xffffefff
+#define ABT_SW_RST_N_SFT 12
+#define ABT_SW_RST_N_HI 12
+#define ABT_SW_RST_N_SZ 1
+#define MMU_VER_MSK 0x0000e000
+#define MMU_VER_I_MSK 0xffff1fff
+#define MMU_VER_SFT 13
+#define MMU_VER_HI 15
+#define MMU_VER_SZ 3
+#define MMU_SHARE_MCU_MSK 0x00ff0000
+#define MMU_SHARE_MCU_I_MSK 0xff00ffff
+#define MMU_SHARE_MCU_SFT 16
+#define MMU_SHARE_MCU_HI 23
+#define MMU_SHARE_MCU_SZ 8
+#define HS_WR_MSK 0x00000001
+#define HS_WR_I_MSK 0xfffffffe
+#define HS_WR_SFT 0
+#define HS_WR_HI 0
+#define HS_WR_SZ 1
+#define HS_FLAG_MSK 0x00000010
+#define HS_FLAG_I_MSK 0xffffffef
+#define HS_FLAG_SFT 4
+#define HS_FLAG_HI 4
+#define HS_FLAG_SZ 1
+#define HS_ID_MSK 0x00007f00
+#define HS_ID_I_MSK 0xffff80ff
+#define HS_ID_SFT 8
+#define HS_ID_HI 14
+#define HS_ID_SZ 7
+#define HS_CHANNEL_MSK 0x000f0000
+#define HS_CHANNEL_I_MSK 0xfff0ffff
+#define HS_CHANNEL_SFT 16
+#define HS_CHANNEL_HI 19
+#define HS_CHANNEL_SZ 4
+#define HS_PAGE_MSK 0x00f00000
+#define HS_PAGE_I_MSK 0xff0fffff
+#define HS_PAGE_SFT 20
+#define HS_PAGE_HI 23
+#define HS_PAGE_SZ 4
+#define HS_DATA_MSK 0xff000000
+#define HS_DATA_I_MSK 0x00ffffff
+#define HS_DATA_SFT 24
+#define HS_DATA_HI 31
+#define HS_DATA_SZ 8
+#define CPU_POR0_MSK 0x0000000f
+#define CPU_POR0_I_MSK 0xfffffff0
+#define CPU_POR0_SFT 0
+#define CPU_POR0_HI 3
+#define CPU_POR0_SZ 4
+#define CPU_POR1_MSK 0x000000f0
+#define CPU_POR1_I_MSK 0xffffff0f
+#define CPU_POR1_SFT 4
+#define CPU_POR1_HI 7
+#define CPU_POR1_SZ 4
+#define CPU_POR2_MSK 0x00000f00
+#define CPU_POR2_I_MSK 0xfffff0ff
+#define CPU_POR2_SFT 8
+#define CPU_POR2_HI 11
+#define CPU_POR2_SZ 4
+#define CPU_POR3_MSK 0x0000f000
+#define CPU_POR3_I_MSK 0xffff0fff
+#define CPU_POR3_SFT 12
+#define CPU_POR3_HI 15
+#define CPU_POR3_SZ 4
+#define CPU_POR4_MSK 0x000f0000
+#define CPU_POR4_I_MSK 0xfff0ffff
+#define CPU_POR4_SFT 16
+#define CPU_POR4_HI 19
+#define CPU_POR4_SZ 4
+#define CPU_POR5_MSK 0x00f00000
+#define CPU_POR5_I_MSK 0xff0fffff
+#define CPU_POR5_SFT 20
+#define CPU_POR5_HI 23
+#define CPU_POR5_SZ 4
+#define CPU_POR6_MSK 0x0f000000
+#define CPU_POR6_I_MSK 0xf0ffffff
+#define CPU_POR6_SFT 24
+#define CPU_POR6_HI 27
+#define CPU_POR6_SZ 4
+#define CPU_POR7_MSK 0xf0000000
+#define CPU_POR7_I_MSK 0x0fffffff
+#define CPU_POR7_SFT 28
+#define CPU_POR7_HI 31
+#define CPU_POR7_SZ 4
+#define CPU_POR8_MSK 0x0000000f
+#define CPU_POR8_I_MSK 0xfffffff0
+#define CPU_POR8_SFT 0
+#define CPU_POR8_HI 3
+#define CPU_POR8_SZ 4
+#define CPU_POR9_MSK 0x000000f0
+#define CPU_POR9_I_MSK 0xffffff0f
+#define CPU_POR9_SFT 4
+#define CPU_POR9_HI 7
+#define CPU_POR9_SZ 4
+#define CPU_PORA_MSK 0x00000f00
+#define CPU_PORA_I_MSK 0xfffff0ff
+#define CPU_PORA_SFT 8
+#define CPU_PORA_HI 11
+#define CPU_PORA_SZ 4
+#define CPU_PORB_MSK 0x0000f000
+#define CPU_PORB_I_MSK 0xffff0fff
+#define CPU_PORB_SFT 12
+#define CPU_PORB_HI 15
+#define CPU_PORB_SZ 4
+#define CPU_PORC_MSK 0x000f0000
+#define CPU_PORC_I_MSK 0xfff0ffff
+#define CPU_PORC_SFT 16
+#define CPU_PORC_HI 19
+#define CPU_PORC_SZ 4
+#define CPU_PORD_MSK 0x00f00000
+#define CPU_PORD_I_MSK 0xff0fffff
+#define CPU_PORD_SFT 20
+#define CPU_PORD_HI 23
+#define CPU_PORD_SZ 4
+#define CPU_PORE_MSK 0x0f000000
+#define CPU_PORE_I_MSK 0xf0ffffff
+#define CPU_PORE_SFT 24
+#define CPU_PORE_HI 27
+#define CPU_PORE_SZ 4
+#define CPU_PORF_MSK 0xf0000000
+#define CPU_PORF_I_MSK 0x0fffffff
+#define CPU_PORF_SFT 28
+#define CPU_PORF_HI 31
+#define CPU_PORF_SZ 4
+#define ACC_WR_LEN_MSK 0x0000003f
+#define ACC_WR_LEN_I_MSK 0xffffffc0
+#define ACC_WR_LEN_SFT 0
+#define ACC_WR_LEN_HI 5
+#define ACC_WR_LEN_SZ 6
+#define ACC_RD_LEN_MSK 0x00003f00
+#define ACC_RD_LEN_I_MSK 0xffffc0ff
+#define ACC_RD_LEN_SFT 8
+#define ACC_RD_LEN_HI 13
+#define ACC_RD_LEN_SZ 6
+#define REQ_NACK_CLR_MSK 0x00008000
+#define REQ_NACK_CLR_I_MSK 0xffff7fff
+#define REQ_NACK_CLR_SFT 15
+#define REQ_NACK_CLR_HI 15
+#define REQ_NACK_CLR_SZ 1
+#define NACK_FLAG_BUS_MSK 0xffff0000
+#define NACK_FLAG_BUS_I_MSK 0x0000ffff
+#define NACK_FLAG_BUS_SFT 16
+#define NACK_FLAG_BUS_HI 31
+#define NACK_FLAG_BUS_SZ 16
+#define DMN_R_PASS_MSK 0x0000ffff
+#define DMN_R_PASS_I_MSK 0xffff0000
+#define DMN_R_PASS_SFT 0
+#define DMN_R_PASS_HI 15
+#define DMN_R_PASS_SZ 16
+#define PARA_ALC_RLS_MSK 0x00010000
+#define PARA_ALC_RLS_I_MSK 0xfffeffff
+#define PARA_ALC_RLS_SFT 16
+#define PARA_ALC_RLS_HI 16
+#define PARA_ALC_RLS_SZ 1
+#define REQ_PORNS_CHGEN_MSK 0x01000000
+#define REQ_PORNS_CHGEN_I_MSK 0xfeffffff
+#define REQ_PORNS_CHGEN_SFT 24
+#define REQ_PORNS_CHGEN_HI 24
+#define REQ_PORNS_CHGEN_SZ 1
+#define ALC_ABT_ID_MSK 0x0000007f
+#define ALC_ABT_ID_I_MSK 0xffffff80
+#define ALC_ABT_ID_SFT 0
+#define ALC_ABT_ID_HI 6
+#define ALC_ABT_ID_SZ 7
+#define ALC_ABT_INT_MSK 0x00008000
+#define ALC_ABT_INT_I_MSK 0xffff7fff
+#define ALC_ABT_INT_SFT 15
+#define ALC_ABT_INT_HI 15
+#define ALC_ABT_INT_SZ 1
+#define RLS_ABT_ID_MSK 0x007f0000
+#define RLS_ABT_ID_I_MSK 0xff80ffff
+#define RLS_ABT_ID_SFT 16
+#define RLS_ABT_ID_HI 22
+#define RLS_ABT_ID_SZ 7
+#define RLS_ABT_INT_MSK 0x80000000
+#define RLS_ABT_INT_I_MSK 0x7fffffff
+#define RLS_ABT_INT_SFT 31
+#define RLS_ABT_INT_HI 31
+#define RLS_ABT_INT_SZ 1
+#define DEBUG_CTL_MSK 0x000000ff
+#define DEBUG_CTL_I_MSK 0xffffff00
+#define DEBUG_CTL_SFT 0
+#define DEBUG_CTL_HI 7
+#define DEBUG_CTL_SZ 8
+#define DEBUG_H16_MSK 0x00000100
+#define DEBUG_H16_I_MSK 0xfffffeff
+#define DEBUG_H16_SFT 8
+#define DEBUG_H16_HI 8
+#define DEBUG_H16_SZ 1
+#define DEBUG_OUT_MSK 0xffffffff
+#define DEBUG_OUT_I_MSK 0x00000000
+#define DEBUG_OUT_SFT 0
+#define DEBUG_OUT_HI 31
+#define DEBUG_OUT_SZ 32
+#define ALC_ERR_MSK 0x00000001
+#define ALC_ERR_I_MSK 0xfffffffe
+#define ALC_ERR_SFT 0
+#define ALC_ERR_HI 0
+#define ALC_ERR_SZ 1
+#define RLS_ERR_MSK 0x00000002
+#define RLS_ERR_I_MSK 0xfffffffd
+#define RLS_ERR_SFT 1
+#define RLS_ERR_HI 1
+#define RLS_ERR_SZ 1
+#define AL_STATE_MSK 0x00000700
+#define AL_STATE_I_MSK 0xfffff8ff
+#define AL_STATE_SFT 8
+#define AL_STATE_HI 10
+#define AL_STATE_SZ 3
+#define RL_STATE_MSK 0x00007000
+#define RL_STATE_I_MSK 0xffff8fff
+#define RL_STATE_SFT 12
+#define RL_STATE_HI 14
+#define RL_STATE_SZ 3
+#define ALC_ERR_ID_MSK 0x007f0000
+#define ALC_ERR_ID_I_MSK 0xff80ffff
+#define ALC_ERR_ID_SFT 16
+#define ALC_ERR_ID_HI 22
+#define ALC_ERR_ID_SZ 7
+#define RLS_ERR_ID_MSK 0x7f000000
+#define RLS_ERR_ID_I_MSK 0x80ffffff
+#define RLS_ERR_ID_SFT 24
+#define RLS_ERR_ID_HI 30
+#define RLS_ERR_ID_SZ 7
+#define DMN_NOHIT_FLAG_MSK 0x00000001
+#define DMN_NOHIT_FLAG_I_MSK 0xfffffffe
+#define DMN_NOHIT_FLAG_SFT 0
+#define DMN_NOHIT_FLAG_HI 0
+#define DMN_NOHIT_FLAG_SZ 1
+#define DMN_FLAG_MSK 0x00000002
+#define DMN_FLAG_I_MSK 0xfffffffd
+#define DMN_FLAG_SFT 1
+#define DMN_FLAG_HI 1
+#define DMN_FLAG_SZ 1
+#define DMN_WR_MSK 0x00000008
+#define DMN_WR_I_MSK 0xfffffff7
+#define DMN_WR_SFT 3
+#define DMN_WR_HI 3
+#define DMN_WR_SZ 1
+#define DMN_PORT_MSK 0x000000f0
+#define DMN_PORT_I_MSK 0xffffff0f
+#define DMN_PORT_SFT 4
+#define DMN_PORT_HI 7
+#define DMN_PORT_SZ 4
+#define DMN_NHIT_ID_MSK 0x00007f00
+#define DMN_NHIT_ID_I_MSK 0xffff80ff
+#define DMN_NHIT_ID_SFT 8
+#define DMN_NHIT_ID_HI 14
+#define DMN_NHIT_ID_SZ 7
+#define DMN_NHIT_ADDR_MSK 0xffff0000
+#define DMN_NHIT_ADDR_I_MSK 0x0000ffff
+#define DMN_NHIT_ADDR_SFT 16
+#define DMN_NHIT_ADDR_HI 31
+#define DMN_NHIT_ADDR_SZ 16
+#define TX_MOUNT_MSK 0x000000ff
+#define TX_MOUNT_I_MSK 0xffffff00
+#define TX_MOUNT_SFT 0
+#define TX_MOUNT_HI 7
+#define TX_MOUNT_SZ 8
+#define RX_MOUNT_MSK 0x0000ff00
+#define RX_MOUNT_I_MSK 0xffff00ff
+#define RX_MOUNT_SFT 8
+#define RX_MOUNT_HI 15
+#define RX_MOUNT_SZ 8
+#define AVA_TAG_MSK 0x01ff0000
+#define AVA_TAG_I_MSK 0xfe00ffff
+#define AVA_TAG_SFT 16
+#define AVA_TAG_HI 24
+#define AVA_TAG_SZ 9
+#define PKTBUF_FULL_MSK 0x80000000
+#define PKTBUF_FULL_I_MSK 0x7fffffff
+#define PKTBUF_FULL_SFT 31
+#define PKTBUF_FULL_HI 31
+#define PKTBUF_FULL_SZ 1
+#define DMN_NOHIT_MCU_MSK 0x00000001
+#define DMN_NOHIT_MCU_I_MSK 0xfffffffe
+#define DMN_NOHIT_MCU_SFT 0
+#define DMN_NOHIT_MCU_HI 0
+#define DMN_NOHIT_MCU_SZ 1
+#define DMN_MCU_FLAG_MSK 0x00000002
+#define DMN_MCU_FLAG_I_MSK 0xfffffffd
+#define DMN_MCU_FLAG_SFT 1
+#define DMN_MCU_FLAG_HI 1
+#define DMN_MCU_FLAG_SZ 1
+#define DMN_MCU_WR_MSK 0x00000008
+#define DMN_MCU_WR_I_MSK 0xfffffff7
+#define DMN_MCU_WR_SFT 3
+#define DMN_MCU_WR_HI 3
+#define DMN_MCU_WR_SZ 1
+#define DMN_MCU_PORT_MSK 0x000000f0
+#define DMN_MCU_PORT_I_MSK 0xffffff0f
+#define DMN_MCU_PORT_SFT 4
+#define DMN_MCU_PORT_HI 7
+#define DMN_MCU_PORT_SZ 4
+#define DMN_MCU_ID_MSK 0x00007f00
+#define DMN_MCU_ID_I_MSK 0xffff80ff
+#define DMN_MCU_ID_SFT 8
+#define DMN_MCU_ID_HI 14
+#define DMN_MCU_ID_SZ 7
+#define DMN_MCU_ADDR_MSK 0xffff0000
+#define DMN_MCU_ADDR_I_MSK 0x0000ffff
+#define DMN_MCU_ADDR_SFT 16
+#define DMN_MCU_ADDR_HI 31
+#define DMN_MCU_ADDR_SZ 16
+#define MB_IDTBL_31_0_MSK 0xffffffff
+#define MB_IDTBL_31_0_I_MSK 0x00000000
+#define MB_IDTBL_31_0_SFT 0
+#define MB_IDTBL_31_0_HI 31
+#define MB_IDTBL_31_0_SZ 32
+#define MB_IDTBL_63_32_MSK 0xffffffff
+#define MB_IDTBL_63_32_I_MSK 0x00000000
+#define MB_IDTBL_63_32_SFT 0
+#define MB_IDTBL_63_32_HI 31
+#define MB_IDTBL_63_32_SZ 32
+#define MB_IDTBL_95_64_MSK 0xffffffff
+#define MB_IDTBL_95_64_I_MSK 0x00000000
+#define MB_IDTBL_95_64_SFT 0
+#define MB_IDTBL_95_64_HI 31
+#define MB_IDTBL_95_64_SZ 32
+#define MB_IDTBL_127_96_MSK 0xffffffff
+#define MB_IDTBL_127_96_I_MSK 0x00000000
+#define MB_IDTBL_127_96_SFT 0
+#define MB_IDTBL_127_96_HI 31
+#define MB_IDTBL_127_96_SZ 32
+#define PKT_IDTBL_31_0_MSK 0xffffffff
+#define PKT_IDTBL_31_0_I_MSK 0x00000000
+#define PKT_IDTBL_31_0_SFT 0
+#define PKT_IDTBL_31_0_HI 31
+#define PKT_IDTBL_31_0_SZ 32
+#define PKT_IDTBL_63_32_MSK 0xffffffff
+#define PKT_IDTBL_63_32_I_MSK 0x00000000
+#define PKT_IDTBL_63_32_SFT 0
+#define PKT_IDTBL_63_32_HI 31
+#define PKT_IDTBL_63_32_SZ 32
+#define PKT_IDTBL_95_64_MSK 0xffffffff
+#define PKT_IDTBL_95_64_I_MSK 0x00000000
+#define PKT_IDTBL_95_64_SFT 0
+#define PKT_IDTBL_95_64_HI 31
+#define PKT_IDTBL_95_64_SZ 32
+#define PKT_IDTBL_127_96_MSK 0xffffffff
+#define PKT_IDTBL_127_96_I_MSK 0x00000000
+#define PKT_IDTBL_127_96_SFT 0
+#define PKT_IDTBL_127_96_HI 31
+#define PKT_IDTBL_127_96_SZ 32
+#define DMN_IDTBL_31_0_MSK 0xffffffff
+#define DMN_IDTBL_31_0_I_MSK 0x00000000
+#define DMN_IDTBL_31_0_SFT 0
+#define DMN_IDTBL_31_0_HI 31
+#define DMN_IDTBL_31_0_SZ 32
+#define DMN_IDTBL_63_32_MSK 0xffffffff
+#define DMN_IDTBL_63_32_I_MSK 0x00000000
+#define DMN_IDTBL_63_32_SFT 0
+#define DMN_IDTBL_63_32_HI 31
+#define DMN_IDTBL_63_32_SZ 32
+#define DMN_IDTBL_95_64_MSK 0xffffffff
+#define DMN_IDTBL_95_64_I_MSK 0x00000000
+#define DMN_IDTBL_95_64_SFT 0
+#define DMN_IDTBL_95_64_HI 31
+#define DMN_IDTBL_95_64_SZ 32
+#define DMN_IDTBL_127_96_MSK 0xffffffff
+#define DMN_IDTBL_127_96_I_MSK 0x00000000
+#define DMN_IDTBL_127_96_SFT 0
+#define DMN_IDTBL_127_96_HI 31
+#define DMN_IDTBL_127_96_SZ 32
+#define NEQ_MB_ID_31_0_MSK 0xffffffff
+#define NEQ_MB_ID_31_0_I_MSK 0x00000000
+#define NEQ_MB_ID_31_0_SFT 0
+#define NEQ_MB_ID_31_0_HI 31
+#define NEQ_MB_ID_31_0_SZ 32
+#define NEQ_MB_ID_63_32_MSK 0xffffffff
+#define NEQ_MB_ID_63_32_I_MSK 0x00000000
+#define NEQ_MB_ID_63_32_SFT 0
+#define NEQ_MB_ID_63_32_HI 31
+#define NEQ_MB_ID_63_32_SZ 32
+#define NEQ_MB_ID_95_64_MSK 0xffffffff
+#define NEQ_MB_ID_95_64_I_MSK 0x00000000
+#define NEQ_MB_ID_95_64_SFT 0
+#define NEQ_MB_ID_95_64_HI 31
+#define NEQ_MB_ID_95_64_SZ 32
+#define NEQ_MB_ID_127_96_MSK 0xffffffff
+#define NEQ_MB_ID_127_96_I_MSK 0x00000000
+#define NEQ_MB_ID_127_96_SFT 0
+#define NEQ_MB_ID_127_96_HI 31
+#define NEQ_MB_ID_127_96_SZ 32
+#define NEQ_PKT_ID_31_0_MSK 0xffffffff
+#define NEQ_PKT_ID_31_0_I_MSK 0x00000000
+#define NEQ_PKT_ID_31_0_SFT 0
+#define NEQ_PKT_ID_31_0_HI 31
+#define NEQ_PKT_ID_31_0_SZ 32
+#define NEQ_PKT_ID_63_32_MSK 0xffffffff
+#define NEQ_PKT_ID_63_32_I_MSK 0x00000000
+#define NEQ_PKT_ID_63_32_SFT 0
+#define NEQ_PKT_ID_63_32_HI 31
+#define NEQ_PKT_ID_63_32_SZ 32
+#define NEQ_PKT_ID_95_64_MSK 0xffffffff
+#define NEQ_PKT_ID_95_64_I_MSK 0x00000000
+#define NEQ_PKT_ID_95_64_SFT 0
+#define NEQ_PKT_ID_95_64_HI 31
+#define NEQ_PKT_ID_95_64_SZ 32
+#define NEQ_PKT_ID_127_96_MSK 0xffffffff
+#define NEQ_PKT_ID_127_96_I_MSK 0x00000000
+#define NEQ_PKT_ID_127_96_SFT 0
+#define NEQ_PKT_ID_127_96_HI 31
+#define NEQ_PKT_ID_127_96_SZ 32
+#define ALC_NOCHG_ID_MSK 0x0000007f
+#define ALC_NOCHG_ID_I_MSK 0xffffff80
+#define ALC_NOCHG_ID_SFT 0
+#define ALC_NOCHG_ID_HI 6
+#define ALC_NOCHG_ID_SZ 7
+#define ALC_NOCHG_INT_MSK 0x00008000
+#define ALC_NOCHG_INT_I_MSK 0xffff7fff
+#define ALC_NOCHG_INT_SFT 15
+#define ALC_NOCHG_INT_HI 15
+#define ALC_NOCHG_INT_SZ 1
+#define NEQ_PKT_FLAG_MSK 0x00010000
+#define NEQ_PKT_FLAG_I_MSK 0xfffeffff
+#define NEQ_PKT_FLAG_SFT 16
+#define NEQ_PKT_FLAG_HI 16
+#define NEQ_PKT_FLAG_SZ 1
+#define NEQ_MB_FLAG_MSK 0x01000000
+#define NEQ_MB_FLAG_I_MSK 0xfeffffff
+#define NEQ_MB_FLAG_SFT 24
+#define NEQ_MB_FLAG_HI 24
+#define NEQ_MB_FLAG_SZ 1
+#define SRAM_TAG_0_MSK 0x0000ffff
+#define SRAM_TAG_0_I_MSK 0xffff0000
+#define SRAM_TAG_0_SFT 0
+#define SRAM_TAG_0_HI 15
+#define SRAM_TAG_0_SZ 16
+#define SRAM_TAG_1_MSK 0xffff0000
+#define SRAM_TAG_1_I_MSK 0x0000ffff
+#define SRAM_TAG_1_SFT 16
+#define SRAM_TAG_1_HI 31
+#define SRAM_TAG_1_SZ 16
+#define SRAM_TAG_2_MSK 0x0000ffff
+#define SRAM_TAG_2_I_MSK 0xffff0000
+#define SRAM_TAG_2_SFT 0
+#define SRAM_TAG_2_HI 15
+#define SRAM_TAG_2_SZ 16
+#define SRAM_TAG_3_MSK 0xffff0000
+#define SRAM_TAG_3_I_MSK 0x0000ffff
+#define SRAM_TAG_3_SFT 16
+#define SRAM_TAG_3_HI 31
+#define SRAM_TAG_3_SZ 16
+#define SRAM_TAG_4_MSK 0x0000ffff
+#define SRAM_TAG_4_I_MSK 0xffff0000
+#define SRAM_TAG_4_SFT 0
+#define SRAM_TAG_4_HI 15
+#define SRAM_TAG_4_SZ 16
+#define SRAM_TAG_5_MSK 0xffff0000
+#define SRAM_TAG_5_I_MSK 0x0000ffff
+#define SRAM_TAG_5_SFT 16
+#define SRAM_TAG_5_HI 31
+#define SRAM_TAG_5_SZ 16
+#define SRAM_TAG_6_MSK 0x0000ffff
+#define SRAM_TAG_6_I_MSK 0xffff0000
+#define SRAM_TAG_6_SFT 0
+#define SRAM_TAG_6_HI 15
+#define SRAM_TAG_6_SZ 16
+#define SRAM_TAG_7_MSK 0xffff0000
+#define SRAM_TAG_7_I_MSK 0x0000ffff
+#define SRAM_TAG_7_SFT 16
+#define SRAM_TAG_7_HI 31
+#define SRAM_TAG_7_SZ 16
+#define SRAM_TAG_8_MSK 0x0000ffff
+#define SRAM_TAG_8_I_MSK 0xffff0000
+#define SRAM_TAG_8_SFT 0
+#define SRAM_TAG_8_HI 15
+#define SRAM_TAG_8_SZ 16
+#define SRAM_TAG_9_MSK 0xffff0000
+#define SRAM_TAG_9_I_MSK 0x0000ffff
+#define SRAM_TAG_9_SFT 16
+#define SRAM_TAG_9_HI 31
+#define SRAM_TAG_9_SZ 16
+#define SRAM_TAG_10_MSK 0x0000ffff
+#define SRAM_TAG_10_I_MSK 0xffff0000
+#define SRAM_TAG_10_SFT 0
+#define SRAM_TAG_10_HI 15
+#define SRAM_TAG_10_SZ 16
+#define SRAM_TAG_11_MSK 0xffff0000
+#define SRAM_TAG_11_I_MSK 0x0000ffff
+#define SRAM_TAG_11_SFT 16
+#define SRAM_TAG_11_HI 31
+#define SRAM_TAG_11_SZ 16
+#define SRAM_TAG_12_MSK 0x0000ffff
+#define SRAM_TAG_12_I_MSK 0xffff0000
+#define SRAM_TAG_12_SFT 0
+#define SRAM_TAG_12_HI 15
+#define SRAM_TAG_12_SZ 16
+#define SRAM_TAG_13_MSK 0xffff0000
+#define SRAM_TAG_13_I_MSK 0x0000ffff
+#define SRAM_TAG_13_SFT 16
+#define SRAM_TAG_13_HI 31
+#define SRAM_TAG_13_SZ 16
+#define SRAM_TAG_14_MSK 0x0000ffff
+#define SRAM_TAG_14_I_MSK 0xffff0000
+#define SRAM_TAG_14_SFT 0
+#define SRAM_TAG_14_HI 15
+#define SRAM_TAG_14_SZ 16
+#define SRAM_TAG_15_MSK 0xffff0000
+#define SRAM_TAG_15_I_MSK 0x0000ffff
+#define SRAM_TAG_15_SFT 16
+#define SRAM_TAG_15_HI 31
+#define SRAM_TAG_15_SZ 16
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_common.h b/drivers/net/wireless/ssv6051/include/ssv6200_common.h
new file mode 100644
index 00000000000..e6d30f3714f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200_common.h
@@ -0,0 +1,452 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV6200_COMMON_H_
+#define _SSV6200_COMMON_H_
+#define FW_VERSION_REG ADR_TX_SEG
+#define M_ENG_CPU 0x00
+#define M_ENG_HWHCI 0x01
+#define M_ENG_EMPTY 0x02
+#define M_ENG_ENCRYPT 0x03
+#define M_ENG_MACRX 0x04
+#define M_ENG_MIC 0x05
+#define M_ENG_TX_EDCA0 0x06
+#define M_ENG_TX_EDCA1 0x07
+#define M_ENG_TX_EDCA2 0x08
+#define M_ENG_TX_EDCA3 0x09
+#define M_ENG_TX_MNG 0x0A
+#define M_ENG_ENCRYPT_SEC 0x0B
+#define M_ENG_MIC_SEC 0x0C
+#define M_ENG_RESERVED_1 0x0D
+#define M_ENG_RESERVED_2 0x0E
+#define M_ENG_TRASH_CAN 0x0F
+#define M_ENG_MAX (M_ENG_TRASH_CAN+1)
+#define M_CPU_HWENG 0x00
+#define M_CPU_TXL34CS 0x01
+#define M_CPU_RXL34CS 0x02
+#define M_CPU_DEFRAG 0x03
+#define M_CPU_EDCATX 0x04
+#define M_CPU_RXDATA 0x05
+#define M_CPU_RXMGMT 0x06
+#define M_CPU_RXCTRL 0x07
+#define M_CPU_FRAG 0x08
+#define M_CPU_TXTPUT 0x09
+#ifndef ID_TRAP_SW_TXTPUT
+#define ID_TRAP_SW_TXTPUT 50
+#endif
+#define M0_TXREQ 0
+#define M1_TXREQ 1
+#define M2_TXREQ 2
+#define M0_RXEVENT 3
+#define M2_RXEVENT 4
+#define HOST_CMD 5
+#define HOST_EVENT 6
+#define TEST_CMD 7
+#define SSV6XXX_RX_DESC_LEN \
+        (sizeof(struct ssv6200_rx_desc) + \
+         sizeof(struct ssv6200_rxphy_info))
+#define SSV6XXX_TX_DESC_LEN \
+        (sizeof(struct ssv6200_tx_desc) + 0)
+#define TXPB_OFFSET 80
+#define RXPB_OFFSET 80
+#define SSV6200_TX_PKT_RSVD_SETTING 0x3
+#define SSV6200_TX_PKT_RSVD SSV6200_TX_PKT_RSVD_SETTING*16
+#define SSV6200_ALLOC_RSVD TXPB_OFFSET+SSV6200_TX_PKT_RSVD
+#define SSV62XX_TX_MAX_RATES 3
+
+enum ssv6xxx_sr_bhvr {
+	SUSPEND_RESUME_0,
+	SUSPEND_RESUME_1,
+	SUSPEND_RESUME_MAX
+};
+
+enum ssv6xxx_reboot_bhvr {
+	SSV_SYS_REBOOT = 1,
+	SSV_SYS_HALF,
+	SSV_SYS_POWER_OFF
+};
+
+struct fw_rc_retry_params {
+	u32 count:4;
+	u32 drate:6;
+	u32 crate:6;
+	u32 rts_cts_nav:16;
+	u32 frame_consume_time:10;
+	u32 dl_length:12;
+	u32 RSVD:10;
+} __attribute__((packed));
+struct ssv6200_tx_desc {
+	u32 len:16;
+	u32 c_type:3;
+	u32 f80211:1;
+	u32 qos:1;
+	u32 ht:1;
+	u32 use_4addr:1;
+	u32 RSVD_0:3;
+	u32 bc_que:1;
+	u32 security:1;
+	u32 more_data:1;
+	u32 stype_b5b4:2;
+	u32 extra_info:1;
+	u32 fCmd;
+	u32 hdr_offset:8;
+	u32 frag:1;
+	u32 unicast:1;
+	u32 hdr_len:6;
+	u32 tx_report:1;
+	u32 tx_burst:1;
+	u32 ack_policy:2;
+	u32 aggregation:1;
+	u32 RSVD_1:3;
+	u32 do_rts_cts:2;
+	u32 reason:6;
+	u32 payload_offset:8;
+	u32 RSVD_4:7;
+	u32 RSVD_2:1;
+	u32 fCmdIdx:3;
+	u32 wsid:4;
+	u32 txq_idx:3;
+	u32 TxF_ID:6;
+	u32 rts_cts_nav:16;
+	u32 frame_consume_time:10;
+	u32 crate_idx:6;
+	u32 drate_idx:6;
+	u32 dl_length:12;
+	u32 RSVD_3:14;
+	u32 RESERVED[8];
+	struct fw_rc_retry_params rc_params[SSV62XX_TX_MAX_RATES];
+};
+struct ssv6200_rx_desc {
+	u32 len:16;
+	u32 c_type:3;
+	u32 f80211:1;
+	u32 qos:1;
+	u32 ht:1;
+	u32 use_4addr:1;
+	u32 l3cs_err:1;
+	u32 l4cs_err:1;
+	u32 align2:1;
+	u32 RSVD_0:2;
+	u32 psm:1;
+	u32 stype_b5b4:2;
+	u32 extra_info:1;
+	u32 edca0_used:4;
+	u32 edca1_used:5;
+	u32 edca2_used:5;
+	u32 edca3_used:5;
+	u32 mng_used:4;
+	u32 tx_page_used:9;
+	u32 hdr_offset:8;
+	u32 frag:1;
+	u32 unicast:1;
+	u32 hdr_len:6;
+	u32 RxResult:8;
+	u32 wildcard_bssid:1;
+	u32 RSVD_1:1;
+	u32 reason:6;
+	u32 payload_offset:8;
+	u32 tx_id_used:8;
+	u32 fCmdIdx:3;
+	u32 wsid:4;
+	u32 RSVD_3:3;
+	u32 rate_idx:6;
+};
+struct ssv6200_rxphy_info {
+	u32 len:16;
+	u32 rsvd0:16;
+	u32 mode:3;
+	u32 ch_bw:3;
+	u32 preamble:1;
+	u32 ht_short_gi:1;
+	u32 rate:7;
+	u32 rsvd1:1;
+	u32 smoothing:1;
+	u32 no_sounding:1;
+	u32 aggregate:1;
+	u32 stbc:2;
+	u32 fec:1;
+	u32 n_ess:2;
+	u32 rsvd2:8;
+	u32 l_length:12;
+	u32 l_rate:3;
+	u32 rsvd3:17;
+	u32 rsvd4;
+	u32 rpci:8;
+	u32 snr:8;
+	u32 service:16;
+};
+struct ssv6200_rxphy_info_padding {
+	u32 rpci:8;
+	u32 snr:8;
+	u32 RSVD:16;
+};
+struct ssv6200_txphy_info {
+	u32 rsvd[7];
+};
+#ifdef CONFIG_P2P_NOA
+struct ssv6xxx_p2p_noa_param {
+	u32 duration;
+	u32 interval;
+	u32 start_time;
+	u32 enable:8;
+	u32 count:8;
+	u8 addr[6];
+	u8 vif_id;
+} __attribute__((packed));
+#endif
+typedef struct cfg_host_cmd {
+	u32 len:16;
+	u32 c_type:3;
+	u32 RSVD0:5;
+	u32 h_cmd:8;
+	u32 cmd_seq_no;
+	union {
+		u32 dummy;
+		u8 dat8[0];
+		u16 dat16[0];
+		u32 dat32[0];
+	};
+} HDR_HostCmd;
+#define HOST_CMD_HDR_LEN ((size_t)(((HDR_HostCmd *)100)->dat8)-100U)
+struct sdio_rxtput_cfg {
+	u32 size_per_frame;
+	u32 total_frames;
+};
+typedef enum {
+	SSV6XXX_HOST_CMD_START = 0,
+	SSV6XXX_HOST_CMD_LOG,
+	SSV6XXX_HOST_CMD_PS,
+	SSV6XXX_HOST_CMD_INIT_CALI,
+	SSV6XXX_HOST_CMD_RX_TPUT,
+	SSV6XXX_HOST_CMD_TX_TPUT,
+	SSV6XXX_HOST_CMD_WATCHDOG_START,
+	SSV6XXX_HOST_CMD_WATCHDOG_STOP,
+	SSV6XXX_HOST_CMD_WSID_OP,
+#ifdef CONFIG_P2P_NOA
+	SSV6XXX_HOST_CMD_SET_NOA,
+#endif
+	SSV6XXX_HOST_SOC_CMD_MAXID,
+} ssv6xxx_host_cmd_id;
+#define SSV_NUM_HW_STA 2
+typedef struct cfg_host_event {
+	u32 len:16;
+	u32 c_type:3;
+	u32 RSVD0:5;
+	u32 h_event:8;
+	u32 evt_seq_no;
+	u8 dat[0];
+} HDR_HostEvent;
+typedef enum {
+#ifdef USE_CMD_RESP
+	SOC_EVT_CMD_RESP,
+	SOC_EVT_SCAN_RESULT,
+	SOC_EVT_DEAUTH,
+#else
+	SOC_EVT_GET_REG_RESP,
+#endif
+	SOC_EVT_NO_BA,
+	SOC_EVT_RC_MPDU_REPORT,
+	SOC_EVT_RC_AMPDU_REPORT,
+	SOC_EVT_LOG,
+#ifdef CONFIG_P2P_NOA
+	SOC_EVT_NOA,
+#endif
+	SOC_EVT_USER_END,
+	SOC_EVT_SDIO_TEST_COMMAND,
+	SOC_EVT_RESET_HOST,
+	SOC_EVT_SDIO_TXTPUT_RESULT,
+	SOC_EVT_WATCHDOG_TRIGGER,
+	SOC_EVT_TXLOOPBK_RESULT,
+	SOC_EVT_MAXID,
+} ssv6xxx_soc_event;
+#ifdef CONFIG_P2P_NOA
+typedef enum {
+	SSV6XXX_NOA_START = 0,
+	SSV6XXX_NOA_STOP,
+} ssv6xxx_host_noa_event;
+struct ssv62xx_noa_evt {
+	u8 evt_id;
+	u8 vif;
+} __attribute__((packed));
+#endif
+typedef enum {
+	SSV6XXX_RC_COUNTER_CLEAR = 1,
+	SSV6XXX_RC_REPORT,
+} ssv6xxx_host_rate_control_event;
+#define MAX_AGGR_NUM (24)
+struct ssv62xx_tx_rate {
+	s8 data_rate;
+	u8 count;
+} __attribute__((packed));
+struct ampdu_ba_notify_data {
+	u8 wsid;
+	struct ssv62xx_tx_rate tried_rates[SSV62XX_TX_MAX_RATES];
+	u16 seq_no[MAX_AGGR_NUM];
+} __attribute__((packed));
+struct firmware_rate_control_report_data {
+	u8 wsid;
+	struct ssv62xx_tx_rate rates[SSV62XX_TX_MAX_RATES];
+	u16 ampdu_len;
+	u16 ampdu_ack_len;
+	int ack_signal;
+} __attribute__((packed));
+#define RC_RETRY_PARAM_OFFSET ((sizeof(struct fw_rc_retry_params))*SSV62XX_TX_MAX_RATES)
+#define SSV_RC_RATE_MAX 39
+enum SSV6XXX_WSID_OPS {
+	SSV6XXX_WSID_OPS_ADD,
+	SSV6XXX_WSID_OPS_DEL,
+	SSV6XXX_WSID_OPS_RESETALL,
+	SSV6XXX_WSID_OPS_ENABLE_CAPS,
+	SSV6XXX_WSID_OPS_DISABLE_CAPS,
+	SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE,
+	SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE,
+	SSV6XXX_WSID_OPS_MAX
+};
+enum SSV6XXX_WSID_SEC {
+	SSV6XXX_WSID_SEC_NONE = 0,
+	SSV6XXX_WSID_SEC_PAIRWISE = 1 << 0,
+	SSV6XXX_WSID_SEC_GROUP = 1 << 1,
+};
+enum SSV6XXX_WSID_SEC_TYPE {
+	SSV6XXX_WSID_SEC_SW,
+	SSV6XXX_WSID_SEC_HW,
+	SSV6XXX_WSID_SEC_TYPE_MAX
+};
+enum SSV6XXX_RETURN_STATE {
+	SSV6XXX_STATE_OK,
+	SSV6XXX_STATE_NG,
+	SSV6XXX_STATE_MAX
+};
+struct ssv6xxx_wsid_params {
+	u8 cmd;
+	u8 wsid_idx;
+	u8 target_wsid[6];
+	u8 hw_security;
+};
+struct ssv6xxx_iqk_cfg {
+	u32 cfg_xtal:8;
+	u32 cfg_pa:8;
+	u32 cfg_pabias_ctrl:8;
+	u32 cfg_pacascode_ctrl:8;
+	u32 cfg_tssi_trgt:8;
+	u32 cfg_tssi_div:8;
+	u32 cfg_def_tx_scale_11b:8;
+	u32 cfg_def_tx_scale_11b_p0d5:8;
+	u32 cfg_def_tx_scale_11g:8;
+	u32 cfg_def_tx_scale_11g_p0d5:8;
+	u32 cmd_sel;
+	union {
+		u32 fx_sel;
+		u32 argv;
+	};
+	u32 phy_tbl_size;
+	u32 rf_tbl_size;
+};
+#define PHY_SETTING_SIZE sizeof(phy_setting)
+struct ssv6xxx_ch_cfg {
+	u32 reg_addr;
+	u32 ch1_12_value;
+	u32 ch13_14_value;
+};
+#define IQK_CFG_LEN (sizeof(struct ssv6xxx_iqk_cfg))
+#define RF_SETTING_SIZE (sizeof(asic_rf_setting))
+#define MAX_PHY_SETTING_TABLE_SIZE 1920
+#define MAX_RF_SETTING_TABLE_SIZE 512
+typedef enum {
+	SSV6XXX_VOLT_DCDC_CONVERT = 0,
+	SSV6XXX_VOLT_LDO_CONVERT,
+} ssv6xxx_cfg_volt;
+typedef enum {
+	SSV6XXX_VOLT_33V = 0,
+	SSV6XXX_VOLT_42V,
+} ssv6xxx_cfg_volt_value;
+typedef enum {
+	SSV6XXX_IQK_CFG_XTAL_26M = 0,
+	SSV6XXX_IQK_CFG_XTAL_40M,
+	SSV6XXX_IQK_CFG_XTAL_24M,
+	SSV6XXX_IQK_CFG_XTAL_MAX,
+} ssv6xxx_iqk_cfg_xtal;
+typedef enum {
+	SSV6XXX_IQK_CFG_PA_DEF = 0,
+	SSV6XXX_IQK_CFG_PA_LI_MPB,
+	SSV6XXX_IQK_CFG_PA_LI_EVB,
+	SSV6XXX_IQK_CFG_PA_HP,
+} ssv6xxx_iqk_cfg_pa;
+typedef enum {
+	SSV6XXX_IQK_CMD_INIT_CALI = 0,
+	SSV6XXX_IQK_CMD_RTBL_LOAD,
+	SSV6XXX_IQK_CMD_RTBL_LOAD_DEF,
+	SSV6XXX_IQK_CMD_RTBL_RESET,
+	SSV6XXX_IQK_CMD_RTBL_SET,
+	SSV6XXX_IQK_CMD_RTBL_EXPORT,
+	SSV6XXX_IQK_CMD_TK_EVM,
+	SSV6XXX_IQK_CMD_TK_TONE,
+	SSV6XXX_IQK_CMD_TK_CHCH,
+} ssv6xxx_iqk_cmd_sel;
+#define SSV6XXX_IQK_TEMPERATURE 0x00000004
+#define SSV6XXX_IQK_RXDC 0x00000008
+#define SSV6XXX_IQK_RXRC 0x00000010
+#define SSV6XXX_IQK_TXDC 0x00000020
+#define SSV6XXX_IQK_TXIQ 0x00000040
+#define SSV6XXX_IQK_RXIQ 0x00000080
+#define SSV6XXX_IQK_TSSI 0x00000100
+#define SSV6XXX_IQK_PAPD 0x00000200
+typedef struct ssv_cabrio_reg_st {
+	u32 address;
+	u32 data;
+} ssv_cabrio_reg;
+typedef enum __PBuf_Type_E {
+	NOTYPE_BUF = 0,
+	TX_BUF = 1,
+	RX_BUF = 2
+} PBuf_Type_E;
+struct SKB_info_st {
+	struct ieee80211_sta *sta;
+	u16 mpdu_retry_counter;
+	unsigned long aggr_timestamp;
+	u16 ampdu_tx_status;
+	u16 ampdu_tx_final_retry_count;
+	u16 lowest_rate;
+	struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+	ktime_t timestamp;
+#endif
+};
+typedef struct SKB_info_st SKB_info;
+typedef struct SKB_info_st *p_SKB_info;
+#define SSV_SKB_info_size (sizeof(struct SKB_info_st))
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+#define SKB_DURATION_TIMEOUT_MS 100
+enum ssv_debug_skb_timestamp {
+	SKB_DURATION_STAGE_TX_ENQ,
+	SKB_DURATION_STAGE_TO_SDIO,
+	SKB_DURATION_STAGE_IN_HWQ,
+	SKB_DURATION_STAGE_END
+};
+#endif
+#define SSV6051Q_P1 0x00000000
+#define SSV6051Q_P2 0x70000000
+#define SSV6051Z 0x71000000
+#define SSV6051Q 0x73000000
+#define SSV6051P 0x75000000
+struct ssv6xxx_tx_loopback {
+	u32 reg;
+	u32 val;
+	u32 restore_val;
+	u8 restore;
+	u8 delay_ms;
+};
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h b/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
new file mode 100644
index 00000000000..0327393de3f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static ssv_cabrio_reg phy_setting[] = {
+	{0xce0071bc, 0x565B565B},
+	{0xce000008, 0x0000006a},
+	{0xce00000c, 0x00000064},
+	{0xce000010, 0x00007FFF},
+	{0xce000014, 0x00000003},
+	{0xce000018, 0x0055003C},
+	{0xce00001c, 0x00000064},
+	{0xce000020, 0x20000000},
+	{0xce00002c, 0x00000000},
+	{0xce000030, 0x80046072},
+	{0xce000034, 0x1f300f6f},
+	{0xce000038, 0x660F36D0},
+	{0xce00003c, 0x106C0004},
+	{0xce000040, 0x01601400},
+	{0xce000044, 0x00600008},
+	{0xce000048, 0xff000160},
+	{0xce00004c, 0x00000840},
+	{0xce000060, 0x01000405},
+	{0xce000064, 0x06090813},
+	{0xce000068, 0x12070000},
+	{0xce00006c, 0x01000405},
+	{0xce000070, 0x06090813},
+	{0xce000074, 0x12010000},
+	{0xce000078, 0x00000000},
+	{0xce00007c, 0x10110003},
+	{0xce000080, 0x0110000F},
+	{0xce000084, 0x00000000},
+	{0xce000088, 0x00000000},
+	{0xce000094, 0x01012425},
+	{0xce000098, 0x01010101},
+	{0xce00009c, 0x00000011},
+	{0xce0000a0, 0x1fff0000},
+	{0xce0000a4, 0x1fff0000},
+	{0xce0000a8, 0x1fff0000},
+	{0xce0000ac, 0x1fff0000},
+	{0xce0000b8, 0x0000fe3e},
+	{0xce0000fc, 0xffffffff},
+	{0xce000108, 0x0ead04f5},
+	{0xce00010c, 0x0fd60080},
+	{0xce000110, 0x00000009},
+	{0xce0010a4, 0x0000002c},
+	{0xce0010b4, 0x00003001},
+	{0xce0010d4, 0x00000001},
+	{0xce002000, 0x00000044},
+	{0xce002004, 0x00040000},
+	{0xce002008, 0x20300050},
+	{0xce00200c, 0x00003467},
+	{0xce002010, 0x00430000},
+	{0xce002014, 0x20304015},
+	{0xce002018, 0x00390005},
+	{0xce00201c, 0x05555555},
+	{0xce002020, 0x00570057},
+	{0xce002024, 0x00570057},
+	{0xce002028, 0x00236700},
+	{0xce00202c, 0x000d1746},
+	{0xce002030, 0x05061787},
+	{0xce002034, 0x07800000},
+	{0xce00209c, 0x00900008},
+	{0xce0020a0, 0x00000000},
+	{0xce0023f8, 0x00000000},
+	{0xce0023fc, 0x00000001},
+	{0xce0030a4, 0x00001901},
+	{0xce0030b8, 0x5d08908e},
+	{0xce004000, 0x00000044},
+	{0xce004004, 0x00750075},
+	{0xce004008, 0x00000075},
+	{0xce00400c, 0x10000075},
+	{0xce004010, 0x3F384905},
+	{0xce004014, 0x40182000},
+	{0xce004018, 0x20600000},
+	{0xce00401c, 0x0C010120},
+	{0xce004020, 0x50505050},
+	{0xce004024, 0x50000000},
+	{0xce004028, 0x50505050},
+	{0xce00402c, 0x506070A0},
+	{0xce004030, 0xF0000000},
+	{0xce004034, 0x00002424},
+	{0xce004038, 0x00001420},
+	{0xce00409c, 0x0000300A},
+	{0xce0040c0, 0x20000280},
+	{0xce0040c4, 0x30023002},
+	{0xce0040c8, 0x0000003a},
+	{0xce004130, 0x40000000},
+	{0xce004164, 0x009C007E},
+	{0xce004180, 0x00044400},
+	{0xce004188, 0x82000000},
+	{0xce004190, 0x00000000},
+	{0xce004194, 0xffffffff},
+	{0xce004380, 0x00700010},
+	{0xce004384, 0x00007575},
+	{0xce004388, 0x0001fe3e},
+	{0xce00438c, 0x0000fe3e},
+	{0xce0043f8, 0x00000001},
+	{0xce007000, 0x00000000},
+	{0xce007004, 0x00008000},
+	{0xce007008, 0x00000000},
+	{0xce00700c, 0x00000000},
+	{0xce007010, 0x00000000},
+	{0xce007014, 0x00000000},
+	{0xce007018, 0x00000000},
+	{0xce00701c, 0x00000000},
+	{0xce007020, 0x00000000},
+	{0xce007024, 0x00000000},
+	{0xce007028, 0x00000000},
+	{0xce00702c, 0x00000000},
+	{0xce007030, 0x00000000},
+	{0xce007034, 0x00000000},
+	{0xce007038, 0x00000000},
+	{0xce00703c, 0x00000000},
+	{0xce007040, 0x02000200},
+	{0xce007048, 0x00000000},
+	{0xce00704c, 0x00000000},
+	{0xce007050, 0x00000000},
+	{0xce007054, 0x00000000},
+	{0xce007058, 0x000028ff},
+	{0xce00705c, 0x00000000},
+	{0xce007060, 0x00000000},
+	{0xce007064, 0x00000000},
+	{0xce007068, 0x00000000},
+	{0xce00706c, 0x00000202},
+	{0xce007070, 0x80ffc200},
+	{0xce007074, 0x00000000},
+	{0xce007078, 0x00000000},
+	{0xce00707c, 0x00000000},
+	{0xce007080, 0x00000000},
+	{0xce007084, 0x00000000},
+	{0xce007088, 0x00000000},
+	{0xce00708c, 0x00000000},
+	{0xce007090, 0x00000000},
+	{0xce007094, 0x00000000},
+	{0xce007098, 0x00000000},
+	{0xce00709c, 0x00000000},
+	{0xce0070a0, 0x00000000},
+	{0xce0070a4, 0x00000000},
+	{0xce0070a8, 0x00000000},
+	{0xce0070ac, 0x00000000},
+	{0xce0070b0, 0x00000000},
+	{0xce0070b4, 0x00000000},
+	{0xce0070b8, 0x00000000},
+	{0xce0070bc, 0x00000000},
+	{0xce0070c0, 0x00000000},
+	{0xce0070c4, 0x00000000},
+	{0xce0070c8, 0x00000000},
+	{0xce0070cc, 0x00000000},
+	{0xce0070d0, 0x00000000},
+	{0xce0070d4, 0x00000000},
+	{0xce0070d8, 0x00000000},
+	{0xce0070dc, 0x00000000},
+	{0xce0070e0, 0x00000000},
+	{0xce0070e4, 0x00000000},
+	{0xce0070e8, 0x00000000},
+	{0xce0070ec, 0x00000000},
+	{0xce0070f0, 0x00000000},
+	{0xce0070f4, 0x00000000},
+	{0xce0070f8, 0x00000000},
+	{0xce0070fc, 0x00000000},
+	{0xce007100, 0x00000000},
+	{0xce007104, 0x00000000},
+	{0xce007108, 0x00000000},
+	{0xce00710c, 0x00000000},
+	{0xce007110, 0x00000000},
+	{0xce007114, 0x00000000},
+	{0xce007118, 0x00000000},
+	{0xce00711c, 0x00000000},
+	{0xce007120, 0x02000200},
+	{0xce007124, 0x02000200},
+	{0xce007128, 0x02000200},
+	{0xce00712c, 0x02000200},
+	{0xce007130, 0x02000200},
+	{0xce007134, 0x02000200},
+	{0xce007138, 0x02000200},
+	{0xce00713c, 0x02000200},
+	{0xce007140, 0x02000200},
+	{0xce007144, 0x02000200},
+	{0xce007148, 0x02000200},
+	{0xce00714c, 0x02000200},
+	{0xce007150, 0x02000200},
+	{0xce007154, 0x02000200},
+	{0xce007158, 0x00000000},
+	{0xce00715c, 0x00000000},
+	{0xce007160, 0x00000000},
+	{0xce007164, 0x00000000},
+	{0xce007168, 0x00000000},
+	{0xce00716c, 0x00000000},
+	{0xce007170, 0x00000000},
+	{0xce007174, 0x00000000},
+	{0xce007178, 0x00000000},
+	{0xce00717c, 0x00000000},
+	{0xce007180, 0x00000000},
+	{0xce007184, 0x00000000},
+	{0xce007188, 0x00000000},
+	{0xce00718c, 0x00000000},
+	{0xce007190, 0x00000000},
+	{0xce007194, 0x00000000},
+	{0xce007198, 0x00000000},
+	{0xce00719c, 0x00000000},
+	{0xce0071a0, 0x00000000},
+	{0xce0071a4, 0x00000000},
+	{0xce0071a8, 0x00000000},
+	{0xce0071ac, 0x00000000},
+	{0xce0071b0, 0x00000000},
+	{0xce0071b4, 0x00000100},
+	{0xce0071b8, 0x00000000},
+	{0xce0071c0, 0x00000000},
+	{0xce0071c4, 0x00000000},
+	{0xce0071c8, 0x00000000},
+	{0xce0071cc, 0x00000000},
+	{0xce0071d0, 0x00000000},
+	{0xce0071d4, 0x00000000},
+	{0xce0071d8, 0x00000000},
+	{0xce0071dc, 0x00000000},
+	{0xce0071e0, 0x00000000},
+	{0xce0071e4, 0x00000000},
+	{0xce0071e8, 0x00000000},
+	{0xce0071ec, 0x00000000},
+	{0xce0071f0, 0x00000000},
+	{0xce0071f4, 0x00000000},
+	{0xce0071f8, 0x00000000},
+	{0xce0071fc, 0x00000000},
+	{0xce0043fc, 0x000104E5},
+	{0xce007044, 0x00028080},
+	{0xce000000, 0x80000016},
+};
+
+static const u32 wifi_tx_gain[] = {
+	0x79807980,
+	0x72797279,
+	0x6C726C72,
+	0x666C666C,
+	0x60666066,
+	0x5B605B60,
+	0x565B565B,
+	0x51565156,
+	0x4C514C51,
+	0x484C484C,
+	0x44484448,
+	0x40444044,
+	0x3C403C40,
+	0x3A3D3A3D,
+	0x36393639,
+};
+
+static ssv_cabrio_reg asic_rf_setting[] = {
+	{0xCE010038, 0x0003E07C},
+	{0xCE010060, 0x00406000},
+	{0xCE01009C, 0x00000024},
+	{0xCE0100A0, 0x00EC4CC5},
+	{0xCE010000, 0x40002000},
+	{0xCE010004, 0x00020FC0},
+	{0xCE010008, 0x000DF69B},
+	{0xCE010014, 0x3D3E84FE},
+	{0xCE010018, 0x01457D79},
+	{0xCE01001C, 0x000103A7},
+	{0xCE010020, 0x000103A6},
+	{0xCE01002C, 0x00032CA8},
+	{0xCE010048, 0xFCCCCF27},
+	{0xCE010050, 0x00444000},
+	{0xCE01000C, 0x151558C5},
+	{0xCE010010, 0x01011A88},
+	{0xCE010024, 0x00012001},
+	{0xCE010028, 0x00036000},
+	{0xCE010030, 0x20EA0224},
+	{0xCE010034, 0x44000755},
+	{0xCE01003C, 0x55D89D8A},
+	{0xCE010040, 0x005508BB},
+	{0xCE010044, 0x07C08BFF},
+	{0xCE01004C, 0x07700830},
+	{0xCE010054, 0x00007FF4},
+	{0xCE010058, 0x0000000E},
+	{0xCE01005C, 0x00088018},
+	{0xCE010064, 0x08820820},
+	{0xCE010068, 0x00820820},
+	{0xCE01006C, 0x00820820},
+	{0xCE010070, 0x00820820},
+	{0xCE010074, 0x00820820},
+	{0xCE010078, 0x00820820},
+	{0xCE01007C, 0x00820820},
+	{0xCE010080, 0x00820820},
+	{0xCE010084, 0x00004080},
+	{0xCE010088, 0x200800FE},
+	{0xCE01008C, 0xAAAAAAAA},
+	{0xCE010090, 0xAAAAAAAA},
+	{0xCE010094, 0x0000A487},
+	{0xCE010098, 0x0000070E},
+	{0xCE0100A4, 0x00000F43},
+	{0xCE0100A8, 0x00098900},
+	{0xCE0100AC, 0x00000000},
+	{0xC00003AC, 0x00000000},
+	{0xC00003B0, 0x00000000},
+	{0xC00003B4, 0x00000000},
+	{0xC00003BC, 0x00000000},
+	{0xC0001D00, 0x5E000040},
+	{0xC0001D04, 0x015D015D},
+	{0xC0001D08, 0x00000001},
+	{0xC0001D0C, 0x55550000},
+	{0xC0001D20, 0x7FFF0000},
+	{0xC0001D24, 0x00000003},
+	{0xC0001D28, 0x00000000},
+	{0xC0001D2C, 0x00000000},
+};
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_reg.h b/drivers/net/wireless/ssv6051/include/ssv6200_reg.h
new file mode 100644
index 00000000000..d4a99b25d61
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200_reg.h
@@ -0,0 +1,9694 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define SYS_REG_BASE 0xc0000000
+#define WBOOT_REG_BASE 0xc0000100
+#define TU0_US_REG_BASE 0xc0000200
+#define TU1_US_REG_BASE 0xc0000210
+#define TU2_US_REG_BASE 0xc0000220
+#define TU3_US_REG_BASE 0xc0000230
+#define TM0_MS_REG_BASE 0xc0000240
+#define TM1_MS_REG_BASE 0xc0000250
+#define TM2_MS_REG_BASE 0xc0000260
+#define TM3_MS_REG_BASE 0xc0000270
+#define MCU_WDT_REG_BASE 0xc0000280
+#define SYS_WDT_REG_BASE 0xc0000284
+#define GPIO_REG_BASE 0xc0000300
+#define SD_REG_BASE 0xc0000800
+#define SPI_REG_BASE 0xc0000a00
+#define CSR_I2C_MST_BASE 0xc0000b00
+#define UART_REG_BASE 0xc0000c00
+#define DAT_UART_REG_BASE 0xc0000d00
+#define INT_REG_BASE 0xc0000e00
+#define DBG_SPI_REG_BASE 0xc0000f00
+#define FLASH_SPI_REG_BASE 0xc0001000
+#define DMA_REG_BASE 0xc0001c00
+#define CSR_PMU_BASE 0xc0001d00
+#define CSR_RTC_BASE 0xc0001d20
+#define RTC_RAM_BASE 0xc0001d80
+#define D2_DMA_REG_BASE 0xc0001e00
+#define HCI_REG_BASE 0xc1000000
+#define CO_REG_BASE 0xc2000000
+#define EFS_REG_BASE 0xc2000100
+#define SMS4_REG_BASE 0xc3000000
+#define MRX_REG_BASE 0xc6000000
+#define AMPDU_REG_BASE 0xc6001000
+#define MT_REG_CSR_BASE 0xc6002000
+#define TXQ0_MT_Q_REG_CSR_BASE 0xc6002100
+#define TXQ1_MT_Q_REG_CSR_BASE 0xc6002200
+#define TXQ2_MT_Q_REG_CSR_BASE 0xc6002300
+#define TXQ3_MT_Q_REG_CSR_BASE 0xc6002400
+#define TXQ4_MT_Q_REG_CSR_BASE 0xc6002500
+#define HIF_INFO_BASE 0xca000000
+#define PHY_RATE_INFO_BASE 0xca000200
+#define MAC_GLB_SET_BASE 0xca000300
+#define BTCX_REG_BASE 0xca000400
+#define MIB_REG_BASE 0xca000800
+#define CBR_A_REG_BASE 0xcb000000
+#define MB_REG_BASE 0xcd000000
+#define ID_MNG_REG_BASE 0xcd010000
+#define CSR_PHY_BASE 0xce000000
+#define CSR_RF_BASE 0xce010000
+#define MMU_REG_BASE 0xcf000000
+#define SYS_REG_BANK_SIZE 0x000000b4
+#define WBOOT_REG_BANK_SIZE 0x0000000c
+#define TU0_US_REG_BANK_SIZE 0x00000010
+#define TU1_US_REG_BANK_SIZE 0x00000010
+#define TU2_US_REG_BANK_SIZE 0x00000010
+#define TU3_US_REG_BANK_SIZE 0x00000010
+#define TM0_MS_REG_BANK_SIZE 0x00000010
+#define TM1_MS_REG_BANK_SIZE 0x00000010
+#define TM2_MS_REG_BANK_SIZE 0x00000010
+#define TM3_MS_REG_BANK_SIZE 0x00000010
+#define MCU_WDT_REG_BANK_SIZE 0x00000004
+#define SYS_WDT_REG_BANK_SIZE 0x00000004
+#define GPIO_REG_BANK_SIZE 0x000000d4
+#define SD_REG_BANK_SIZE 0x00000180
+#define SPI_REG_BANK_SIZE 0x00000040
+#define CSR_I2C_MST_BANK_SIZE 0x00000018
+#define UART_REG_BANK_SIZE 0x00000028
+#define DAT_UART_REG_BANK_SIZE 0x00000028
+#define INT_REG_BANK_SIZE 0x0000004c
+#define DBG_SPI_REG_BANK_SIZE 0x00000040
+#define FLASH_SPI_REG_BANK_SIZE 0x0000002c
+#define DMA_REG_BANK_SIZE 0x00000014
+#define CSR_PMU_BANK_SIZE 0x00000100
+#define CSR_RTC_BANK_SIZE 0x000000e0
+#define RTC_RAM_BANK_SIZE 0x00000080
+#define D2_DMA_REG_BANK_SIZE 0x00000014
+#define HCI_REG_BANK_SIZE 0x000000cc
+#define CO_REG_BANK_SIZE 0x000000ac
+#define EFS_REG_BANK_SIZE 0x0000006c
+#define SMS4_REG_BANK_SIZE 0x00000070
+#define MRX_REG_BANK_SIZE 0x00000198
+#define AMPDU_REG_BANK_SIZE 0x00000014
+#define MT_REG_CSR_BANK_SIZE 0x00000100
+#define TXQ0_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ1_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ2_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ3_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ4_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define HIF_INFO_BANK_SIZE 0x0000009c
+#define PHY_RATE_INFO_BANK_SIZE 0x000000b8
+#define MAC_GLB_SET_BANK_SIZE 0x0000003c
+#define BTCX_REG_BANK_SIZE 0x0000000c
+#define MIB_REG_BANK_SIZE 0x00000480
+#define CBR_A_REG_BANK_SIZE 0x001203fc
+#define MB_REG_BANK_SIZE 0x000000a0
+#define ID_MNG_REG_BANK_SIZE 0x00000084
+#define CSR_PHY_BANK_SIZE 0x000071c0
+#define CSR_RF_BANK_SIZE 0x000000b0
+#define MMU_REG_BANK_SIZE 0x000000c0
+#define ADR_BRG_SW_RST (SYS_REG_BASE+0x00000000)
+#define ADR_BOOT (SYS_REG_BASE+0x00000004)
+#define ADR_CHIP_ID_0 (SYS_REG_BASE+0x00000008)
+#define ADR_CHIP_ID_1 (SYS_REG_BASE+0x0000000c)
+#define ADR_CHIP_ID_2 (SYS_REG_BASE+0x00000010)
+#define ADR_CHIP_ID_3 (SYS_REG_BASE+0x00000014)
+#define ADR_CLOCK_SELECTION (SYS_REG_BASE+0x00000018)
+#define ADR_PLATFORM_CLOCK_ENABLE (SYS_REG_BASE+0x0000001c)
+#define ADR_SYS_CSR_CLOCK_ENABLE (SYS_REG_BASE+0x00000020)
+#define ADR_MCU_DBG_SEL (SYS_REG_BASE+0x00000024)
+#define ADR_MCU_DBG_DATA (SYS_REG_BASE+0x00000028)
+#define ADR_AHB_BRG_STATUS (SYS_REG_BASE+0x0000002c)
+#define ADR_BIST_BIST_CTRL (SYS_REG_BASE+0x00000030)
+#define ADR_BIST_MODE_REG_IN (SYS_REG_BASE+0x00000034)
+#define ADR_BIST_MODE_REG_OUT (SYS_REG_BASE+0x00000038)
+#define ADR_BIST_MONITOR_BUS_LSB (SYS_REG_BASE+0x0000003c)
+#define ADR_BIST_MONITOR_BUS_MSB (SYS_REG_BASE+0x00000040)
+#define ADR_TB_ADR_SEL (SYS_REG_BASE+0x00000044)
+#define ADR_TB_RDATA (SYS_REG_BASE+0x00000048)
+#define ADR_UART_W2B (SYS_REG_BASE+0x0000004c)
+#define ADR_AHB_ILL_ADDR (SYS_REG_BASE+0x00000050)
+#define ADR_AHB_FEN_ADDR (SYS_REG_BASE+0x00000054)
+#define ADR_AHB_ILLFEN_STATUS (SYS_REG_BASE+0x00000058)
+#define ADR_PWM_A (SYS_REG_BASE+0x00000080)
+#define ADR_PWM_B (SYS_REG_BASE+0x00000084)
+#define ADR_HBUSREQ_LOCK (SYS_REG_BASE+0x00000090)
+#define ADR_HBURST_LOCK (SYS_REG_BASE+0x00000094)
+#define ADR_PRESCALER_USTIMER (SYS_REG_BASE+0x000000a0)
+#define ADR_BIST_MODE_REG_IN_MMU (SYS_REG_BASE+0x000000a4)
+#define ADR_BIST_MODE_REG_OUT_MMU (SYS_REG_BASE+0x000000a8)
+#define ADR_BIST_MONITOR_BUS_MMU (SYS_REG_BASE+0x000000ac)
+#define ADR_TEST_MODE (SYS_REG_BASE+0x000000b0)
+#define ADR_BOOT_INFO (WBOOT_REG_BASE+0x00000000)
+#define ADR_SD_INIT_CFG (WBOOT_REG_BASE+0x00000004)
+#define ADR_SPARE_UART_INFO (WBOOT_REG_BASE+0x00000008)
+#define ADR_TU0_MICROSECOND_TIMER (TU0_US_REG_BASE+0x00000000)
+#define ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE (TU0_US_REG_BASE+0x00000004)
+#define ADR_TU0_DUMMY_BIT_0 (TU0_US_REG_BASE+0x00000008)
+#define ADR_TU0_DUMMY_BIT_1 (TU0_US_REG_BASE+0x0000000c)
+#define ADR_TU1_MICROSECOND_TIMER (TU1_US_REG_BASE+0x00000000)
+#define ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE (TU1_US_REG_BASE+0x00000004)
+#define ADR_TU1_DUMMY_BIT_0 (TU1_US_REG_BASE+0x00000008)
+#define ADR_TU1_DUMMY_BIT_1 (TU1_US_REG_BASE+0x0000000c)
+#define ADR_TU2_MICROSECOND_TIMER (TU2_US_REG_BASE+0x00000000)
+#define ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE (TU2_US_REG_BASE+0x00000004)
+#define ADR_TU2_DUMMY_BIT_0 (TU2_US_REG_BASE+0x00000008)
+#define ADR_TU2_DUMMY_BIT_1 (TU2_US_REG_BASE+0x0000000c)
+#define ADR_TU3_MICROSECOND_TIMER (TU3_US_REG_BASE+0x00000000)
+#define ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE (TU3_US_REG_BASE+0x00000004)
+#define ADR_TU3_DUMMY_BIT_0 (TU3_US_REG_BASE+0x00000008)
+#define ADR_TU3_DUMMY_BIT_1 (TU3_US_REG_BASE+0x0000000c)
+#define ADR_TM0_MILISECOND_TIMER (TM0_MS_REG_BASE+0x00000000)
+#define ADR_TM0_CURRENT_MILISECOND_TIME_VALUE (TM0_MS_REG_BASE+0x00000004)
+#define ADR_TM0_DUMMY_BIT_0 (TM0_MS_REG_BASE+0x00000008)
+#define ADR_TM0_DUMMY_BIT_1 (TM0_MS_REG_BASE+0x0000000c)
+#define ADR_TM1_MILISECOND_TIMER (TM1_MS_REG_BASE+0x00000000)
+#define ADR_TM1_CURRENT_MILISECOND_TIME_VALUE (TM1_MS_REG_BASE+0x00000004)
+#define ADR_TM1_DUMMY_BIT_0 (TM1_MS_REG_BASE+0x00000008)
+#define ADR_TM1_DUMMY_BIT_1 (TM1_MS_REG_BASE+0x0000000c)
+#define ADR_TM2_MILISECOND_TIMER (TM2_MS_REG_BASE+0x00000000)
+#define ADR_TM2_CURRENT_MILISECOND_TIME_VALUE (TM2_MS_REG_BASE+0x00000004)
+#define ADR_TM2_DUMMY_BIT_0 (TM2_MS_REG_BASE+0x00000008)
+#define ADR_TM2_DUMMY_BIT_1 (TM2_MS_REG_BASE+0x0000000c)
+#define ADR_TM3_MILISECOND_TIMER (TM3_MS_REG_BASE+0x00000000)
+#define ADR_TM3_CURRENT_MILISECOND_TIME_VALUE (TM3_MS_REG_BASE+0x00000004)
+#define ADR_TM3_DUMMY_BIT_0 (TM3_MS_REG_BASE+0x00000008)
+#define ADR_TM3_DUMMY_BIT_1 (TM3_MS_REG_BASE+0x0000000c)
+#define ADR_MCU_WDOG_REG (MCU_WDT_REG_BASE+0x00000000)
+#define ADR_SYS_WDOG_REG (SYS_WDT_REG_BASE+0x00000000)
+#define ADR_PAD6 (GPIO_REG_BASE+0x00000000)
+#define ADR_PAD7 (GPIO_REG_BASE+0x00000004)
+#define ADR_PAD8 (GPIO_REG_BASE+0x00000008)
+#define ADR_PAD9 (GPIO_REG_BASE+0x0000000c)
+#define ADR_PAD11 (GPIO_REG_BASE+0x00000010)
+#define ADR_PAD15 (GPIO_REG_BASE+0x00000014)
+#define ADR_PAD16 (GPIO_REG_BASE+0x00000018)
+#define ADR_PAD17 (GPIO_REG_BASE+0x0000001c)
+#define ADR_PAD18 (GPIO_REG_BASE+0x00000020)
+#define ADR_PAD19 (GPIO_REG_BASE+0x00000024)
+#define ADR_PAD20 (GPIO_REG_BASE+0x00000028)
+#define ADR_PAD21 (GPIO_REG_BASE+0x0000002c)
+#define ADR_PAD22 (GPIO_REG_BASE+0x00000030)
+#define ADR_PAD24 (GPIO_REG_BASE+0x00000034)
+#define ADR_PAD25 (GPIO_REG_BASE+0x00000038)
+#define ADR_PAD27 (GPIO_REG_BASE+0x0000003c)
+#define ADR_PAD28 (GPIO_REG_BASE+0x00000040)
+#define ADR_PAD29 (GPIO_REG_BASE+0x00000044)
+#define ADR_PAD30 (GPIO_REG_BASE+0x00000048)
+#define ADR_PAD31 (GPIO_REG_BASE+0x0000004c)
+#define ADR_PAD32 (GPIO_REG_BASE+0x00000050)
+#define ADR_PAD33 (GPIO_REG_BASE+0x00000054)
+#define ADR_PAD34 (GPIO_REG_BASE+0x00000058)
+#define ADR_PAD42 (GPIO_REG_BASE+0x0000005c)
+#define ADR_PAD43 (GPIO_REG_BASE+0x00000060)
+#define ADR_PAD44 (GPIO_REG_BASE+0x00000064)
+#define ADR_PAD45 (GPIO_REG_BASE+0x00000068)
+#define ADR_PAD46 (GPIO_REG_BASE+0x0000006c)
+#define ADR_PAD47 (GPIO_REG_BASE+0x00000070)
+#define ADR_PAD48 (GPIO_REG_BASE+0x00000074)
+#define ADR_PAD49 (GPIO_REG_BASE+0x00000078)
+#define ADR_PAD50 (GPIO_REG_BASE+0x0000007c)
+#define ADR_PAD51 (GPIO_REG_BASE+0x00000080)
+#define ADR_PAD52 (GPIO_REG_BASE+0x00000084)
+#define ADR_PAD53 (GPIO_REG_BASE+0x00000088)
+#define ADR_PAD54 (GPIO_REG_BASE+0x0000008c)
+#define ADR_PAD56 (GPIO_REG_BASE+0x00000090)
+#define ADR_PAD57 (GPIO_REG_BASE+0x00000094)
+#define ADR_PAD58 (GPIO_REG_BASE+0x00000098)
+#define ADR_PAD59 (GPIO_REG_BASE+0x0000009c)
+#define ADR_PAD60 (GPIO_REG_BASE+0x000000a0)
+#define ADR_PAD61 (GPIO_REG_BASE+0x000000a4)
+#define ADR_PAD62 (GPIO_REG_BASE+0x000000a8)
+#define ADR_PAD64 (GPIO_REG_BASE+0x000000ac)
+#define ADR_PAD65 (GPIO_REG_BASE+0x000000b0)
+#define ADR_PAD66 (GPIO_REG_BASE+0x000000b4)
+#define ADR_PAD68 (GPIO_REG_BASE+0x000000b8)
+#define ADR_PAD67 (GPIO_REG_BASE+0x000000bc)
+#define ADR_PAD69 (GPIO_REG_BASE+0x000000c0)
+#define ADR_PAD70 (GPIO_REG_BASE+0x000000c4)
+#define ADR_PAD231 (GPIO_REG_BASE+0x000000c8)
+#define ADR_PIN_SEL_0 (GPIO_REG_BASE+0x000000cc)
+#define ADR_PIN_SEL_1 (GPIO_REG_BASE+0x000000d0)
+#define ADR_IO_PORT_REG (SD_REG_BASE+0x00000000)
+#define ADR_INT_MASK_REG (SD_REG_BASE+0x00000004)
+#define ADR_INT_STATUS_REG (SD_REG_BASE+0x00000008)
+#define ADR_FN1_STATUS_REG (SD_REG_BASE+0x0000000c)
+#define ADR_CARD_PKT_STATUS_TEST (SD_REG_BASE+0x00000010)
+#define ADR_SYSTEM_INFORMATION_REG (SD_REG_BASE+0x0000001c)
+#define ADR_CARD_RCA_REG (SD_REG_BASE+0x00000020)
+#define ADR_SDIO_FIFO_WR_THLD_REG (SD_REG_BASE+0x00000024)
+#define ADR_SDIO_FIFO_WR_LIMIT_REG (SD_REG_BASE+0x00000028)
+#define ADR_SDIO_TX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x0000002c)
+#define ADR_SDIO_THLD_FOR_CMD53RD_REG (SD_REG_BASE+0x00000030)
+#define ADR_SDIO_RX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x00000034)
+#define ADR_SDIO_LOG_START_END_DATA_REG (SD_REG_BASE+0x00000038)
+#define ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG (SD_REG_BASE+0x00000040)
+#define ADR_SDIO_LAST_CMD_INDEX_CRC_REG (SD_REG_BASE+0x00000044)
+#define ADR_SDIO_LAST_CMD_ARG_REG (SD_REG_BASE+0x00000048)
+#define ADR_SDIO_BUS_STATE_DEBUG_MONITOR (SD_REG_BASE+0x0000004c)
+#define ADR_SDIO_CARD_STATUS_REG (SD_REG_BASE+0x00000050)
+#define ADR_R5_RESP_FLAG_OUT_TIMING (SD_REG_BASE+0x00000054)
+#define ADR_CMD52_DATA_FOR_LAST_TIME (SD_REG_BASE+0x0000005c)
+#define ADR_FN1_DMA_START_ADDR_REG (SD_REG_BASE+0x00000060)
+#define ADR_FN1_INT_CTRL_RESET (SD_REG_BASE+0x00000064)
+#define ADR_IO_REG_PORT_REG (SD_REG_BASE+0x00000070)
+#define ADR_SDIO_FIFO_ERROR_CNT (SD_REG_BASE+0x0000007c)
+#define ADR_SDIO_CRC7_CRC16_ERROR_REG (SD_REG_BASE+0x00000080)
+#define ADR_SDIO_BLOCK_CNT_INFO (SD_REG_BASE+0x00000084)
+#define ADR_RX_DATA_CMD52_ABORT_COUNT (SD_REG_BASE+0x0000008c)
+#define ADR_FIFO_PTR_READ_BLOCK_CNT (SD_REG_BASE+0x00000090)
+#define ADR_TX_TIME_OUT_READ_CTRL (SD_REG_BASE+0x00000094)
+#define ADR_SDIO_TX_ALLOC_REG (SD_REG_BASE+0x00000098)
+#define ADR_SDIO_TX_INFORM (SD_REG_BASE+0x0000009c)
+#define ADR_F1_BLOCK_SIZE_0_REG (SD_REG_BASE+0x000000a0)
+#define ADR_SDIO_COMMAND_LOG_DATA_31_0 (SD_REG_BASE+0x000000b0)
+#define ADR_SDIO_COMMAND_LOG_DATA_63_32 (SD_REG_BASE+0x000000b4)
+#define ADR_SYSTEM_INFORMATION_REGISTER (SD_REG_BASE+0x000000bc)
+#define ADR_CCCR_00H_REG (SD_REG_BASE+0x000000c0)
+#define ADR_CCCR_04H_REG (SD_REG_BASE+0x000000c4)
+#define ADR_CCCR_08H_REG (SD_REG_BASE+0x000000c8)
+#define ADR_CCCR_13H_REG (SD_REG_BASE+0x000000d0)
+#define ADR_FBR_100H_REG (SD_REG_BASE+0x000000e0)
+#define ADR_FBR_109H_REG (SD_REG_BASE+0x000000e8)
+#define ADR_F0_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000100)
+#define ADR_F0_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000104)
+#define ADR_F0_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000108)
+#define ADR_F0_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000010c)
+#define ADR_F0_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000110)
+#define ADR_F0_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000114)
+#define ADR_F0_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000118)
+#define ADR_F0_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000011c)
+#define ADR_F0_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000120)
+#define ADR_F0_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000124)
+#define ADR_F0_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000128)
+#define ADR_F0_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000012c)
+#define ADR_F0_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000130)
+#define ADR_F0_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000134)
+#define ADR_F0_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000138)
+#define ADR_F0_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000013c)
+#define ADR_F1_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000140)
+#define ADR_F1_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000144)
+#define ADR_F1_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000148)
+#define ADR_F1_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000014c)
+#define ADR_F1_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000150)
+#define ADR_F1_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000154)
+#define ADR_F1_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000158)
+#define ADR_F1_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000015c)
+#define ADR_F1_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000160)
+#define ADR_F1_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000164)
+#define ADR_F1_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000168)
+#define ADR_F1_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000016c)
+#define ADR_F1_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000170)
+#define ADR_F1_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000174)
+#define ADR_F1_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000178)
+#define ADR_F1_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000017c)
+#define ADR_SPI_MODE (SPI_REG_BASE+0x00000000)
+#define ADR_RX_QUOTA (SPI_REG_BASE+0x00000004)
+#define ADR_CONDITION_NUMBER (SPI_REG_BASE+0x00000008)
+#define ADR_HOST_PATH (SPI_REG_BASE+0x0000000c)
+#define ADR_TX_SEG (SPI_REG_BASE+0x00000010)
+#define ADR_DEBUG_BURST_MODE (SPI_REG_BASE+0x00000014)
+#define ADR_SPI_TO_PHY_PARAM1 (SPI_REG_BASE+0x00000018)
+#define ADR_SPI_TO_PHY_PARAM2 (SPI_REG_BASE+0x0000001c)
+#define ADR_SPI_STS (SPI_REG_BASE+0x00000020)
+#define ADR_TX_ALLOC_SET (SPI_REG_BASE+0x00000024)
+#define ADR_TX_ALLOC (SPI_REG_BASE+0x00000028)
+#define ADR_DBG_CNT (SPI_REG_BASE+0x0000002c)
+#define ADR_DBG_CNT2 (SPI_REG_BASE+0x00000030)
+#define ADR_DBG_CNT3 (SPI_REG_BASE+0x00000034)
+#define ADR_DBG_CNT4 (SPI_REG_BASE+0x00000038)
+#define ADR_INT_TAG (SPI_REG_BASE+0x0000003c)
+#define ADR_I2CM_EN (CSR_I2C_MST_BASE+0x00000000)
+#define ADR_I2CM_DEV_A (CSR_I2C_MST_BASE+0x00000004)
+#define ADR_I2CM_LEN (CSR_I2C_MST_BASE+0x00000008)
+#define ADR_I2CM_WDAT (CSR_I2C_MST_BASE+0x0000000c)
+#define ADR_I2CM_RDAT (CSR_I2C_MST_BASE+0x00000010)
+#define ADR_I2CM_EN_2 (CSR_I2C_MST_BASE+0x00000014)
+#define ADR_UART_DATA (UART_REG_BASE+0x00000000)
+#define ADR_UART_IER (UART_REG_BASE+0x00000004)
+#define ADR_UART_FCR (UART_REG_BASE+0x00000008)
+#define ADR_UART_LCR (UART_REG_BASE+0x0000000c)
+#define ADR_UART_MCR (UART_REG_BASE+0x00000010)
+#define ADR_UART_LSR (UART_REG_BASE+0x00000014)
+#define ADR_UART_MSR (UART_REG_BASE+0x00000018)
+#define ADR_UART_SPR (UART_REG_BASE+0x0000001c)
+#define ADR_UART_RTHR (UART_REG_BASE+0x00000020)
+#define ADR_UART_ISR (UART_REG_BASE+0x00000024)
+#define ADR_DAT_UART_DATA (DAT_UART_REG_BASE+0x00000000)
+#define ADR_DAT_UART_IER (DAT_UART_REG_BASE+0x00000004)
+#define ADR_DAT_UART_FCR (DAT_UART_REG_BASE+0x00000008)
+#define ADR_DAT_UART_LCR (DAT_UART_REG_BASE+0x0000000c)
+#define ADR_DAT_UART_MCR (DAT_UART_REG_BASE+0x00000010)
+#define ADR_DAT_UART_LSR (DAT_UART_REG_BASE+0x00000014)
+#define ADR_DAT_UART_MSR (DAT_UART_REG_BASE+0x00000018)
+#define ADR_DAT_UART_SPR (DAT_UART_REG_BASE+0x0000001c)
+#define ADR_DAT_UART_RTHR (DAT_UART_REG_BASE+0x00000020)
+#define ADR_DAT_UART_ISR (DAT_UART_REG_BASE+0x00000024)
+#define ADR_INT_MASK (INT_REG_BASE+0x00000000)
+#define ADR_INT_MODE (INT_REG_BASE+0x00000004)
+#define ADR_INT_IRQ_STS (INT_REG_BASE+0x00000008)
+#define ADR_INT_FIQ_STS (INT_REG_BASE+0x0000000c)
+#define ADR_INT_IRQ_RAW (INT_REG_BASE+0x00000010)
+#define ADR_INT_FIQ_RAW (INT_REG_BASE+0x00000014)
+#define ADR_INT_PERI_MASK (INT_REG_BASE+0x00000018)
+#define ADR_INT_PERI_STS (INT_REG_BASE+0x0000001c)
+#define ADR_INT_PERI_RAW (INT_REG_BASE+0x00000020)
+#define ADR_INT_GPI_CFG (INT_REG_BASE+0x00000024)
+#define ADR_SYS_INT_FOR_HOST (INT_REG_BASE+0x00000028)
+#define ADR_SPI_IPC (INT_REG_BASE+0x00000034)
+#define ADR_SDIO_IPC (INT_REG_BASE+0x00000038)
+#define ADR_SDIO_MASK (INT_REG_BASE+0x0000003c)
+#define ADR_SDIO_IRQ_STS (INT_REG_BASE+0x00000040)
+#define ADR_SD_PERI_MASK (INT_REG_BASE+0x00000044)
+#define ADR_SD_PERI_STS (INT_REG_BASE+0x00000048)
+#define ADR_DBG_SPI_MODE (DBG_SPI_REG_BASE+0x00000000)
+#define ADR_DBG_RX_QUOTA (DBG_SPI_REG_BASE+0x00000004)
+#define ADR_DBG_CONDITION_NUMBER (DBG_SPI_REG_BASE+0x00000008)
+#define ADR_DBG_HOST_PATH (DBG_SPI_REG_BASE+0x0000000c)
+#define ADR_DBG_TX_SEG (DBG_SPI_REG_BASE+0x00000010)
+#define ADR_DBG_DEBUG_BURST_MODE (DBG_SPI_REG_BASE+0x00000014)
+#define ADR_DBG_SPI_TO_PHY_PARAM1 (DBG_SPI_REG_BASE+0x00000018)
+#define ADR_DBG_SPI_TO_PHY_PARAM2 (DBG_SPI_REG_BASE+0x0000001c)
+#define ADR_DBG_SPI_STS (DBG_SPI_REG_BASE+0x00000020)
+#define ADR_DBG_TX_ALLOC_SET (DBG_SPI_REG_BASE+0x00000024)
+#define ADR_DBG_TX_ALLOC (DBG_SPI_REG_BASE+0x00000028)
+#define ADR_DBG_DBG_CNT (DBG_SPI_REG_BASE+0x0000002c)
+#define ADR_DBG_DBG_CNT2 (DBG_SPI_REG_BASE+0x00000030)
+#define ADR_DBG_DBG_CNT3 (DBG_SPI_REG_BASE+0x00000034)
+#define ADR_DBG_DBG_CNT4 (DBG_SPI_REG_BASE+0x00000038)
+#define ADR_DBG_INT_TAG (DBG_SPI_REG_BASE+0x0000003c)
+#define ADR_BOOT_ADDR (FLASH_SPI_REG_BASE+0x00000000)
+#define ADR_VERIFY_DATA (FLASH_SPI_REG_BASE+0x00000004)
+#define ADR_FLASH_ADDR (FLASH_SPI_REG_BASE+0x00000008)
+#define ADR_SRAM_ADDR (FLASH_SPI_REG_BASE+0x0000000c)
+#define ADR_LEN (FLASH_SPI_REG_BASE+0x00000010)
+#define ADR_SPI_PARAM (FLASH_SPI_REG_BASE+0x00000014)
+#define ADR_SPI_PARAM2 (FLASH_SPI_REG_BASE+0x00000018)
+#define ADR_CHECK_SUM_RESULT (FLASH_SPI_REG_BASE+0x0000001c)
+#define ADR_CHECK_SUM_IN_FILE (FLASH_SPI_REG_BASE+0x00000020)
+#define ADR_COMMAND_LEN (FLASH_SPI_REG_BASE+0x00000024)
+#define ADR_COMMAND_ADDR (FLASH_SPI_REG_BASE+0x00000028)
+#define ADR_DMA_ADR_SRC (DMA_REG_BASE+0x00000000)
+#define ADR_DMA_ADR_DST (DMA_REG_BASE+0x00000004)
+#define ADR_DMA_CTRL (DMA_REG_BASE+0x00000008)
+#define ADR_DMA_INT (DMA_REG_BASE+0x0000000c)
+#define ADR_DMA_FILL_CONST (DMA_REG_BASE+0x00000010)
+#define ADR_PMU_0 (CSR_PMU_BASE+0x00000000)
+#define ADR_PMU_1 (CSR_PMU_BASE+0x00000004)
+#define ADR_PMU_2 (CSR_PMU_BASE+0x00000008)
+#define ADR_PMU_3 (CSR_PMU_BASE+0x0000000c)
+#define ADR_RTC_1 (CSR_RTC_BASE+0x00000000)
+#define ADR_RTC_2 (CSR_RTC_BASE+0x00000004)
+#define ADR_RTC_3W (CSR_RTC_BASE+0x00000008)
+#define ADR_RTC_3R (CSR_RTC_BASE+0x00000008)
+#define ADR_RTC_4 (CSR_RTC_BASE+0x0000000c)
+#define ADR_RTC_RAM (RTC_RAM_BASE+0x00000000)
+#define ADR_D2_DMA_ADR_SRC (D2_DMA_REG_BASE+0x00000000)
+#define ADR_D2_DMA_ADR_DST (D2_DMA_REG_BASE+0x00000004)
+#define ADR_D2_DMA_CTRL (D2_DMA_REG_BASE+0x00000008)
+#define ADR_D2_DMA_INT (D2_DMA_REG_BASE+0x0000000c)
+#define ADR_D2_DMA_FILL_CONST (D2_DMA_REG_BASE+0x00000010)
+#define ADR_CONTROL (HCI_REG_BASE+0x00000000)
+#define ADR_SDIO_WAKE_MODE (HCI_REG_BASE+0x00000004)
+#define ADR_TX_FLOW_0 (HCI_REG_BASE+0x00000008)
+#define ADR_TX_FLOW_1 (HCI_REG_BASE+0x0000000c)
+#define ADR_THREASHOLD (HCI_REG_BASE+0x00000018)
+#define ADR_TXFID_INCREASE (HCI_REG_BASE+0x00000020)
+#define ADR_GLOBAL_SEQUENCE (HCI_REG_BASE+0x00000028)
+#define ADR_HCI_TX_RX_INFO_SIZE (HCI_REG_BASE+0x00000030)
+#define ADR_HCI_TX_INFO_CLEAR (HCI_REG_BASE+0x00000034)
+#define ADR_TX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000050)
+#define ADR_TX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000054)
+#define ADR_RX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000060)
+#define ADR_RX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000064)
+#define ADR_PACKET_COUNTER_INFO_0 (HCI_REG_BASE+0x00000070)
+#define ADR_PACKET_COUNTER_INFO_1 (HCI_REG_BASE+0x00000074)
+#define ADR_PACKET_COUNTER_INFO_2 (HCI_REG_BASE+0x00000078)
+#define ADR_PACKET_COUNTER_INFO_3 (HCI_REG_BASE+0x0000007c)
+#define ADR_PACKET_COUNTER_INFO_4 (HCI_REG_BASE+0x00000080)
+#define ADR_PACKET_COUNTER_INFO_5 (HCI_REG_BASE+0x00000084)
+#define ADR_PACKET_COUNTER_INFO_6 (HCI_REG_BASE+0x00000088)
+#define ADR_PACKET_COUNTER_INFO_7 (HCI_REG_BASE+0x0000008c)
+#define ADR_SDIO_TX_RX_FAIL_COUNTER_0 (HCI_REG_BASE+0x00000090)
+#define ADR_SDIO_TX_RX_FAIL_COUNTER_1 (HCI_REG_BASE+0x00000094)
+#define ADR_HCI_STATE_DEBUG_MODE_0 (HCI_REG_BASE+0x000000a0)
+#define ADR_HCI_STATE_DEBUG_MODE_1 (HCI_REG_BASE+0x000000a4)
+#define ADR_HCI_STATE_DEBUG_MODE_2 (HCI_REG_BASE+0x000000a8)
+#define ADR_HCI_STATE_DEBUG_MODE_3 (HCI_REG_BASE+0x000000ac)
+#define ADR_HCI_STATE_DEBUG_MODE_4 (HCI_REG_BASE+0x000000b0)
+#define ADR_HCI_STATE_DEBUG_MODE_5 (HCI_REG_BASE+0x000000b4)
+#define ADR_HCI_STATE_DEBUG_MODE_6 (HCI_REG_BASE+0x000000b8)
+#define ADR_HCI_STATE_DEBUG_MODE_7 (HCI_REG_BASE+0x000000bc)
+#define ADR_HCI_STATE_DEBUG_MODE_8 (HCI_REG_BASE+0x000000c0)
+#define ADR_HCI_STATE_DEBUG_MODE_9 (HCI_REG_BASE+0x000000c4)
+#define ADR_HCI_STATE_DEBUG_MODE_10 (HCI_REG_BASE+0x000000c8)
+#define ADR_CS_START_ADDR (CO_REG_BASE+0x00000000)
+#define ADR_CS_ADD_LEN (CO_REG_BASE+0x00000004)
+#define ADR_CS_CMD (CO_REG_BASE+0x00000008)
+#define ADR_CS_INI_BUF (CO_REG_BASE+0x0000000c)
+#define ADR_CS_PSEUDO_BUF (CO_REG_BASE+0x00000010)
+#define ADR_CS_CHECK_SUM (CO_REG_BASE+0x00000014)
+#define ADR_RAND_EN (CO_REG_BASE+0x00000018)
+#define ADR_RAND_NUM (CO_REG_BASE+0x0000001c)
+#define ADR_MUL_OP1 (CO_REG_BASE+0x00000060)
+#define ADR_MUL_OP2 (CO_REG_BASE+0x00000064)
+#define ADR_MUL_ANS0 (CO_REG_BASE+0x00000068)
+#define ADR_MUL_ANS1 (CO_REG_BASE+0x0000006c)
+#define ADR_DMA_RDATA (CO_REG_BASE+0x00000070)
+#define ADR_DMA_WDATA (CO_REG_BASE+0x00000074)
+#define ADR_DMA_LEN (CO_REG_BASE+0x00000078)
+#define ADR_DMA_CLR (CO_REG_BASE+0x0000007c)
+#define ADR_NAV_DATA (CO_REG_BASE+0x00000080)
+#define ADR_CO_NAV (CO_REG_BASE+0x00000084)
+#define ADR_SHA_DST_ADDR (CO_REG_BASE+0x000000a0)
+#define ADR_SHA_SRC_ADDR (CO_REG_BASE+0x000000a4)
+#define ADR_SHA_SETTING (CO_REG_BASE+0x000000a8)
+#define ADR_EFUSE_CLK_FREQ (EFS_REG_BASE+0x00000000)
+#define ADR_EFUSE_LDO_TIME (EFS_REG_BASE+0x00000004)
+#define ADR_EFUSE_AHB_RDATA_0 (EFS_REG_BASE+0x00000008)
+#define ADR_EFUSE_WDATA_0 (EFS_REG_BASE+0x00000008)
+#define ADR_EFUSE_AHB_RDATA_1 (EFS_REG_BASE+0x0000000c)
+#define ADR_EFUSE_WDATA_1 (EFS_REG_BASE+0x0000000c)
+#define ADR_EFUSE_AHB_RDATA_2 (EFS_REG_BASE+0x00000010)
+#define ADR_EFUSE_WDATA_2 (EFS_REG_BASE+0x00000010)
+#define ADR_EFUSE_AHB_RDATA_3 (EFS_REG_BASE+0x00000014)
+#define ADR_EFUSE_WDATA_3 (EFS_REG_BASE+0x00000014)
+#define ADR_EFUSE_AHB_RDATA_4 (EFS_REG_BASE+0x00000018)
+#define ADR_EFUSE_WDATA_4 (EFS_REG_BASE+0x00000018)
+#define ADR_EFUSE_AHB_RDATA_5 (EFS_REG_BASE+0x0000001c)
+#define ADR_EFUSE_WDATA_5 (EFS_REG_BASE+0x0000001c)
+#define ADR_EFUSE_AHB_RDATA_6 (EFS_REG_BASE+0x00000020)
+#define ADR_EFUSE_WDATA_6 (EFS_REG_BASE+0x00000020)
+#define ADR_EFUSE_AHB_RDATA_7 (EFS_REG_BASE+0x00000024)
+#define ADR_EFUSE_WDATA_7 (EFS_REG_BASE+0x00000024)
+#define ADR_EFUSE_SPI_RD0_EN (EFS_REG_BASE+0x00000028)
+#define ADR_EFUSE_SPI_RD1_EN (EFS_REG_BASE+0x0000002c)
+#define ADR_EFUSE_SPI_RD2_EN (EFS_REG_BASE+0x00000030)
+#define ADR_EFUSE_SPI_RD3_EN (EFS_REG_BASE+0x00000034)
+#define ADR_EFUSE_SPI_RD4_EN (EFS_REG_BASE+0x00000038)
+#define ADR_EFUSE_SPI_RD5_EN (EFS_REG_BASE+0x0000003c)
+#define ADR_EFUSE_SPI_RD6_EN (EFS_REG_BASE+0x00000040)
+#define ADR_EFUSE_SPI_RD7_EN (EFS_REG_BASE+0x00000044)
+#define ADR_EFUSE_SPI_BUSY (EFS_REG_BASE+0x00000048)
+#define ADR_EFUSE_SPI_RDATA_0 (EFS_REG_BASE+0x0000004c)
+#define ADR_EFUSE_SPI_RDATA_1 (EFS_REG_BASE+0x00000050)
+#define ADR_EFUSE_SPI_RDATA_2 (EFS_REG_BASE+0x00000054)
+#define ADR_EFUSE_SPI_RDATA_3 (EFS_REG_BASE+0x00000058)
+#define ADR_EFUSE_SPI_RDATA_4 (EFS_REG_BASE+0x0000005c)
+#define ADR_EFUSE_SPI_RDATA_5 (EFS_REG_BASE+0x00000060)
+#define ADR_EFUSE_SPI_RDATA_6 (EFS_REG_BASE+0x00000064)
+#define ADR_EFUSE_SPI_RDATA_7 (EFS_REG_BASE+0x00000068)
+#define ADR_SMS4_CFG1 (SMS4_REG_BASE+0x00000000)
+#define ADR_SMS4_CFG2 (SMS4_REG_BASE+0x00000004)
+#define ADR_SMS4_MODE1 (SMS4_REG_BASE+0x00000008)
+#define ADR_SMS4_TRIG (SMS4_REG_BASE+0x00000010)
+#define ADR_SMS4_STATUS1 (SMS4_REG_BASE+0x00000014)
+#define ADR_SMS4_STATUS2 (SMS4_REG_BASE+0x00000018)
+#define ADR_SMS4_DATA_IN0 (SMS4_REG_BASE+0x00000020)
+#define ADR_SMS4_DATA_IN1 (SMS4_REG_BASE+0x00000024)
+#define ADR_SMS4_DATA_IN2 (SMS4_REG_BASE+0x00000028)
+#define ADR_SMS4_DATA_IN3 (SMS4_REG_BASE+0x0000002c)
+#define ADR_SMS4_DATA_OUT0 (SMS4_REG_BASE+0x00000030)
+#define ADR_SMS4_DATA_OUT1 (SMS4_REG_BASE+0x00000034)
+#define ADR_SMS4_DATA_OUT2 (SMS4_REG_BASE+0x00000038)
+#define ADR_SMS4_DATA_OUT3 (SMS4_REG_BASE+0x0000003c)
+#define ADR_SMS4_KEY_0 (SMS4_REG_BASE+0x00000040)
+#define ADR_SMS4_KEY_1 (SMS4_REG_BASE+0x00000044)
+#define ADR_SMS4_KEY_2 (SMS4_REG_BASE+0x00000048)
+#define ADR_SMS4_KEY_3 (SMS4_REG_BASE+0x0000004c)
+#define ADR_SMS4_MODE_IV0 (SMS4_REG_BASE+0x00000050)
+#define ADR_SMS4_MODE_IV1 (SMS4_REG_BASE+0x00000054)
+#define ADR_SMS4_MODE_IV2 (SMS4_REG_BASE+0x00000058)
+#define ADR_SMS4_MODE_IV3 (SMS4_REG_BASE+0x0000005c)
+#define ADR_SMS4_OFB_ENC0 (SMS4_REG_BASE+0x00000060)
+#define ADR_SMS4_OFB_ENC1 (SMS4_REG_BASE+0x00000064)
+#define ADR_SMS4_OFB_ENC2 (SMS4_REG_BASE+0x00000068)
+#define ADR_SMS4_OFB_ENC3 (SMS4_REG_BASE+0x0000006c)
+#define ADR_MRX_MCAST_TB0_0 (MRX_REG_BASE+0x00000000)
+#define ADR_MRX_MCAST_TB0_1 (MRX_REG_BASE+0x00000004)
+#define ADR_MRX_MCAST_MK0_0 (MRX_REG_BASE+0x00000008)
+#define ADR_MRX_MCAST_MK0_1 (MRX_REG_BASE+0x0000000c)
+#define ADR_MRX_MCAST_CTRL0 (MRX_REG_BASE+0x00000010)
+#define ADR_MRX_MCAST_TB1_0 (MRX_REG_BASE+0x00000014)
+#define ADR_MRX_MCAST_TB1_1 (MRX_REG_BASE+0x00000018)
+#define ADR_MRX_MCAST_MK1_0 (MRX_REG_BASE+0x0000001c)
+#define ADR_MRX_MCAST_MK1_1 (MRX_REG_BASE+0x00000020)
+#define ADR_MRX_MCAST_CTRL1 (MRX_REG_BASE+0x00000024)
+#define ADR_MRX_MCAST_TB2_0 (MRX_REG_BASE+0x00000028)
+#define ADR_MRX_MCAST_TB2_1 (MRX_REG_BASE+0x0000002c)
+#define ADR_MRX_MCAST_MK2_0 (MRX_REG_BASE+0x00000030)
+#define ADR_MRX_MCAST_MK2_1 (MRX_REG_BASE+0x00000034)
+#define ADR_MRX_MCAST_CTRL2 (MRX_REG_BASE+0x00000038)
+#define ADR_MRX_MCAST_TB3_0 (MRX_REG_BASE+0x0000003c)
+#define ADR_MRX_MCAST_TB3_1 (MRX_REG_BASE+0x00000040)
+#define ADR_MRX_MCAST_MK3_0 (MRX_REG_BASE+0x00000044)
+#define ADR_MRX_MCAST_MK3_1 (MRX_REG_BASE+0x00000048)
+#define ADR_MRX_MCAST_CTRL3 (MRX_REG_BASE+0x0000004c)
+#define ADR_MRX_PHY_INFO (MRX_REG_BASE+0x00000050)
+#define ADR_MRX_BA_DBG (MRX_REG_BASE+0x00000054)
+#define ADR_MRX_FLT_TB0 (MRX_REG_BASE+0x00000070)
+#define ADR_MRX_FLT_TB1 (MRX_REG_BASE+0x00000074)
+#define ADR_MRX_FLT_TB2 (MRX_REG_BASE+0x00000078)
+#define ADR_MRX_FLT_TB3 (MRX_REG_BASE+0x0000007c)
+#define ADR_MRX_FLT_TB4 (MRX_REG_BASE+0x00000080)
+#define ADR_MRX_FLT_TB5 (MRX_REG_BASE+0x00000084)
+#define ADR_MRX_FLT_TB6 (MRX_REG_BASE+0x00000088)
+#define ADR_MRX_FLT_TB7 (MRX_REG_BASE+0x0000008c)
+#define ADR_MRX_FLT_TB8 (MRX_REG_BASE+0x00000090)
+#define ADR_MRX_FLT_TB9 (MRX_REG_BASE+0x00000094)
+#define ADR_MRX_FLT_TB10 (MRX_REG_BASE+0x00000098)
+#define ADR_MRX_FLT_TB11 (MRX_REG_BASE+0x0000009c)
+#define ADR_MRX_FLT_TB12 (MRX_REG_BASE+0x000000a0)
+#define ADR_MRX_FLT_TB13 (MRX_REG_BASE+0x000000a4)
+#define ADR_MRX_FLT_TB14 (MRX_REG_BASE+0x000000a8)
+#define ADR_MRX_FLT_TB15 (MRX_REG_BASE+0x000000ac)
+#define ADR_MRX_FLT_EN0 (MRX_REG_BASE+0x000000b0)
+#define ADR_MRX_FLT_EN1 (MRX_REG_BASE+0x000000b4)
+#define ADR_MRX_FLT_EN2 (MRX_REG_BASE+0x000000b8)
+#define ADR_MRX_FLT_EN3 (MRX_REG_BASE+0x000000bc)
+#define ADR_MRX_FLT_EN4 (MRX_REG_BASE+0x000000c0)
+#define ADR_MRX_FLT_EN5 (MRX_REG_BASE+0x000000c4)
+#define ADR_MRX_FLT_EN6 (MRX_REG_BASE+0x000000c8)
+#define ADR_MRX_FLT_EN7 (MRX_REG_BASE+0x000000cc)
+#define ADR_MRX_FLT_EN8 (MRX_REG_BASE+0x000000d0)
+#define ADR_MRX_LEN_FLT (MRX_REG_BASE+0x000000d4)
+#define ADR_RX_FLOW_DATA (MRX_REG_BASE+0x000000e0)
+#define ADR_RX_FLOW_MNG (MRX_REG_BASE+0x000000e4)
+#define ADR_RX_FLOW_CTRL (MRX_REG_BASE+0x000000e8)
+#define ADR_RX_TIME_STAMP_CFG (MRX_REG_BASE+0x000000ec)
+#define ADR_DBG_FF_FULL (MRX_REG_BASE+0x000000f0)
+#define ADR_DBG_WFF_FULL (MRX_REG_BASE+0x000000f4)
+#define ADR_DBG_MB_FULL (MRX_REG_BASE+0x000000f8)
+#define ADR_BA_CTRL (MRX_REG_BASE+0x00000100)
+#define ADR_BA_TA_0 (MRX_REG_BASE+0x00000104)
+#define ADR_BA_TA_1 (MRX_REG_BASE+0x00000108)
+#define ADR_BA_TID (MRX_REG_BASE+0x0000010c)
+#define ADR_BA_ST_SEQ (MRX_REG_BASE+0x00000110)
+#define ADR_BA_SB0 (MRX_REG_BASE+0x00000114)
+#define ADR_BA_SB1 (MRX_REG_BASE+0x00000118)
+#define ADR_MRX_WATCH_DOG (MRX_REG_BASE+0x0000011c)
+#define ADR_ACK_GEN_EN (MRX_REG_BASE+0x00000120)
+#define ADR_ACK_GEN_PARA (MRX_REG_BASE+0x00000124)
+#define ADR_ACK_GEN_RA_0 (MRX_REG_BASE+0x00000128)
+#define ADR_ACK_GEN_RA_1 (MRX_REG_BASE+0x0000012c)
+#define ADR_MIB_LEN_FAIL (MRX_REG_BASE+0x00000130)
+#define ADR_TRAP_HW_ID (MRX_REG_BASE+0x00000134)
+#define ADR_ID_IN_USE (MRX_REG_BASE+0x00000138)
+#define ADR_MRX_ERR (MRX_REG_BASE+0x0000013c)
+#define ADR_WSID0_TID0_RX_SEQ (MRX_REG_BASE+0x00000140)
+#define ADR_WSID0_TID1_RX_SEQ (MRX_REG_BASE+0x00000144)
+#define ADR_WSID0_TID2_RX_SEQ (MRX_REG_BASE+0x00000148)
+#define ADR_WSID0_TID3_RX_SEQ (MRX_REG_BASE+0x0000014c)
+#define ADR_WSID0_TID4_RX_SEQ (MRX_REG_BASE+0x00000150)
+#define ADR_WSID0_TID5_RX_SEQ (MRX_REG_BASE+0x00000154)
+#define ADR_WSID0_TID6_RX_SEQ (MRX_REG_BASE+0x00000158)
+#define ADR_WSID0_TID7_RX_SEQ (MRX_REG_BASE+0x0000015c)
+#define ADR_WSID1_TID0_RX_SEQ (MRX_REG_BASE+0x00000170)
+#define ADR_WSID1_TID1_RX_SEQ (MRX_REG_BASE+0x00000174)
+#define ADR_WSID1_TID2_RX_SEQ (MRX_REG_BASE+0x00000178)
+#define ADR_WSID1_TID3_RX_SEQ (MRX_REG_BASE+0x0000017c)
+#define ADR_WSID1_TID4_RX_SEQ (MRX_REG_BASE+0x00000180)
+#define ADR_WSID1_TID5_RX_SEQ (MRX_REG_BASE+0x00000184)
+#define ADR_WSID1_TID6_RX_SEQ (MRX_REG_BASE+0x00000188)
+#define ADR_WSID1_TID7_RX_SEQ (MRX_REG_BASE+0x0000018c)
+#define ADR_HDR_ADDR_SEL (MRX_REG_BASE+0x00000190)
+#define ADR_FRAME_TYPE_CNTR_SET (MRX_REG_BASE+0x00000194)
+#define ADR_PHY_INFO (AMPDU_REG_BASE+0x00000000)
+#define ADR_AMPDU_SIG (AMPDU_REG_BASE+0x00000004)
+#define ADR_MIB_AMPDU (AMPDU_REG_BASE+0x00000008)
+#define ADR_LEN_FLT (AMPDU_REG_BASE+0x0000000c)
+#define ADR_MIB_DELIMITER (AMPDU_REG_BASE+0x00000010)
+#define ADR_MTX_INT_STS (MT_REG_CSR_BASE+0x00000000)
+#define ADR_MTX_INT_EN (MT_REG_CSR_BASE+0x00000004)
+#define ADR_MTX_MISC_EN (MT_REG_CSR_BASE+0x00000008)
+#define ADR_MTX_EDCCA_TOUT (MT_REG_CSR_BASE+0x00000010)
+#define ADR_MTX_BCN_INT_STS (MT_REG_CSR_BASE+0x000000a0)
+#define ADR_MTX_BCN_EN_INT (MT_REG_CSR_BASE+0x000000a4)
+#define ADR_MTX_BCN_EN_MISC (MT_REG_CSR_BASE+0x000000a8)
+#define ADR_MTX_BCN_MISC (MT_REG_CSR_BASE+0x000000ac)
+#define ADR_MTX_BCN_PRD (MT_REG_CSR_BASE+0x000000b0)
+#define ADR_MTX_BCN_TSF_L (MT_REG_CSR_BASE+0x000000b4)
+#define ADR_MTX_BCN_TSF_U (MT_REG_CSR_BASE+0x000000b8)
+#define ADR_MTX_BCN_CFG0 (MT_REG_CSR_BASE+0x000000bc)
+#define ADR_MTX_BCN_CFG1 (MT_REG_CSR_BASE+0x000000c0)
+#define ADR_MTX_STATUS (MT_REG_CSR_BASE+0x000000cc)
+#define ADR_MTX_DBG_CTRL (MT_REG_CSR_BASE+0x000000d0)
+#define ADR_MTX_DBG_DAT0 (MT_REG_CSR_BASE+0x000000d4)
+#define ADR_MTX_DBG_DAT1 (MT_REG_CSR_BASE+0x000000d8)
+#define ADR_MTX_DBG_DAT2 (MT_REG_CSR_BASE+0x000000dc)
+#define ADR_MTX_DUR_TOUT (MT_REG_CSR_BASE+0x000000e0)
+#define ADR_MTX_DUR_IFS (MT_REG_CSR_BASE+0x000000e4)
+#define ADR_MTX_DUR_SIFS_G (MT_REG_CSR_BASE+0x000000e8)
+#define ADR_MTX_DBG_DAT3 (MT_REG_CSR_BASE+0x000000ec)
+#define ADR_MTX_NAV (MT_REG_CSR_BASE+0x000000f0)
+#define ADR_MTX_MIB_WSID0 (MT_REG_CSR_BASE+0x000000f4)
+#define ADR_MTX_MIB_WSID1 (MT_REG_CSR_BASE+0x000000f8)
+#define ADR_MTX_DBG_DAT4 (MT_REG_CSR_BASE+0x000000fc)
+#define ADR_TXQ0_MTX_Q_MISC_EN (TXQ0_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ0_MTX_Q_AIFSN (TXQ0_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ0_MTX_Q_BKF_CNT (TXQ0_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ0_MTX_Q_RC_LIMIT (TXQ0_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ0_MTX_Q_ID_MAP_L (TXQ0_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ0_MTX_Q_TXOP_CH_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ0_MTX_Q_TXOP_OV_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ1_MTX_Q_MISC_EN (TXQ1_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ1_MTX_Q_AIFSN (TXQ1_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ1_MTX_Q_BKF_CNT (TXQ1_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ1_MTX_Q_RC_LIMIT (TXQ1_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ1_MTX_Q_ID_MAP_L (TXQ1_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ1_MTX_Q_TXOP_CH_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ1_MTX_Q_TXOP_OV_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ2_MTX_Q_MISC_EN (TXQ2_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ2_MTX_Q_AIFSN (TXQ2_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ2_MTX_Q_BKF_CNT (TXQ2_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ2_MTX_Q_RC_LIMIT (TXQ2_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ2_MTX_Q_ID_MAP_L (TXQ2_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ2_MTX_Q_TXOP_CH_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ2_MTX_Q_TXOP_OV_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ3_MTX_Q_MISC_EN (TXQ3_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ3_MTX_Q_AIFSN (TXQ3_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ3_MTX_Q_BKF_CNT (TXQ3_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ3_MTX_Q_RC_LIMIT (TXQ3_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ3_MTX_Q_ID_MAP_L (TXQ3_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ3_MTX_Q_TXOP_CH_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ3_MTX_Q_TXOP_OV_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ4_MTX_Q_MISC_EN (TXQ4_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ4_MTX_Q_AIFSN (TXQ4_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ4_MTX_Q_BKF_CNT (TXQ4_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ4_MTX_Q_RC_LIMIT (TXQ4_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ4_MTX_Q_ID_MAP_L (TXQ4_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ4_MTX_Q_TXOP_CH_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ4_MTX_Q_TXOP_OV_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_WSID0 (HIF_INFO_BASE+0x00000000)
+#define ADR_PEER_MAC0_0 (HIF_INFO_BASE+0x00000004)
+#define ADR_PEER_MAC0_1 (HIF_INFO_BASE+0x00000008)
+#define ADR_TX_ACK_POLICY_0_0 (HIF_INFO_BASE+0x0000000c)
+#define ADR_TX_SEQ_CTRL_0_0 (HIF_INFO_BASE+0x00000010)
+#define ADR_TX_ACK_POLICY_0_1 (HIF_INFO_BASE+0x00000014)
+#define ADR_TX_SEQ_CTRL_0_1 (HIF_INFO_BASE+0x00000018)
+#define ADR_TX_ACK_POLICY_0_2 (HIF_INFO_BASE+0x0000001c)
+#define ADR_TX_SEQ_CTRL_0_2 (HIF_INFO_BASE+0x00000020)
+#define ADR_TX_ACK_POLICY_0_3 (HIF_INFO_BASE+0x00000024)
+#define ADR_TX_SEQ_CTRL_0_3 (HIF_INFO_BASE+0x00000028)
+#define ADR_TX_ACK_POLICY_0_4 (HIF_INFO_BASE+0x0000002c)
+#define ADR_TX_SEQ_CTRL_0_4 (HIF_INFO_BASE+0x00000030)
+#define ADR_TX_ACK_POLICY_0_5 (HIF_INFO_BASE+0x00000034)
+#define ADR_TX_SEQ_CTRL_0_5 (HIF_INFO_BASE+0x00000038)
+#define ADR_TX_ACK_POLICY_0_6 (HIF_INFO_BASE+0x0000003c)
+#define ADR_TX_SEQ_CTRL_0_6 (HIF_INFO_BASE+0x00000040)
+#define ADR_TX_ACK_POLICY_0_7 (HIF_INFO_BASE+0x00000044)
+#define ADR_TX_SEQ_CTRL_0_7 (HIF_INFO_BASE+0x00000048)
+#define ADR_WSID1 (HIF_INFO_BASE+0x00000050)
+#define ADR_PEER_MAC1_0 (HIF_INFO_BASE+0x00000054)
+#define ADR_PEER_MAC1_1 (HIF_INFO_BASE+0x00000058)
+#define ADR_TX_ACK_POLICY_1_0 (HIF_INFO_BASE+0x0000005c)
+#define ADR_TX_SEQ_CTRL_1_0 (HIF_INFO_BASE+0x00000060)
+#define ADR_TX_ACK_POLICY_1_1 (HIF_INFO_BASE+0x00000064)
+#define ADR_TX_SEQ_CTRL_1_1 (HIF_INFO_BASE+0x00000068)
+#define ADR_TX_ACK_POLICY_1_2 (HIF_INFO_BASE+0x0000006c)
+#define ADR_TX_SEQ_CTRL_1_2 (HIF_INFO_BASE+0x00000070)
+#define ADR_TX_ACK_POLICY_1_3 (HIF_INFO_BASE+0x00000074)
+#define ADR_TX_SEQ_CTRL_1_3 (HIF_INFO_BASE+0x00000078)
+#define ADR_TX_ACK_POLICY_1_4 (HIF_INFO_BASE+0x0000007c)
+#define ADR_TX_SEQ_CTRL_1_4 (HIF_INFO_BASE+0x00000080)
+#define ADR_TX_ACK_POLICY_1_5 (HIF_INFO_BASE+0x00000084)
+#define ADR_TX_SEQ_CTRL_1_5 (HIF_INFO_BASE+0x00000088)
+#define ADR_TX_ACK_POLICY_1_6 (HIF_INFO_BASE+0x0000008c)
+#define ADR_TX_SEQ_CTRL_1_6 (HIF_INFO_BASE+0x00000090)
+#define ADR_TX_ACK_POLICY_1_7 (HIF_INFO_BASE+0x00000094)
+#define ADR_TX_SEQ_CTRL_1_7 (HIF_INFO_BASE+0x00000098)
+#define ADR_INFO0 (PHY_RATE_INFO_BASE+0x00000000)
+#define ADR_INFO1 (PHY_RATE_INFO_BASE+0x00000004)
+#define ADR_INFO2 (PHY_RATE_INFO_BASE+0x00000008)
+#define ADR_INFO3 (PHY_RATE_INFO_BASE+0x0000000c)
+#define ADR_INFO4 (PHY_RATE_INFO_BASE+0x00000010)
+#define ADR_INFO5 (PHY_RATE_INFO_BASE+0x00000014)
+#define ADR_INFO6 (PHY_RATE_INFO_BASE+0x00000018)
+#define ADR_INFO7 (PHY_RATE_INFO_BASE+0x0000001c)
+#define ADR_INFO8 (PHY_RATE_INFO_BASE+0x00000020)
+#define ADR_INFO9 (PHY_RATE_INFO_BASE+0x00000024)
+#define ADR_INFO10 (PHY_RATE_INFO_BASE+0x00000028)
+#define ADR_INFO11 (PHY_RATE_INFO_BASE+0x0000002c)
+#define ADR_INFO12 (PHY_RATE_INFO_BASE+0x00000030)
+#define ADR_INFO13 (PHY_RATE_INFO_BASE+0x00000034)
+#define ADR_INFO14 (PHY_RATE_INFO_BASE+0x00000038)
+#define ADR_INFO15 (PHY_RATE_INFO_BASE+0x0000003c)
+#define ADR_INFO16 (PHY_RATE_INFO_BASE+0x00000040)
+#define ADR_INFO17 (PHY_RATE_INFO_BASE+0x00000044)
+#define ADR_INFO18 (PHY_RATE_INFO_BASE+0x00000048)
+#define ADR_INFO19 (PHY_RATE_INFO_BASE+0x0000004c)
+#define ADR_INFO20 (PHY_RATE_INFO_BASE+0x00000050)
+#define ADR_INFO21 (PHY_RATE_INFO_BASE+0x00000054)
+#define ADR_INFO22 (PHY_RATE_INFO_BASE+0x00000058)
+#define ADR_INFO23 (PHY_RATE_INFO_BASE+0x0000005c)
+#define ADR_INFO24 (PHY_RATE_INFO_BASE+0x00000060)
+#define ADR_INFO25 (PHY_RATE_INFO_BASE+0x00000064)
+#define ADR_INFO26 (PHY_RATE_INFO_BASE+0x00000068)
+#define ADR_INFO27 (PHY_RATE_INFO_BASE+0x0000006c)
+#define ADR_INFO28 (PHY_RATE_INFO_BASE+0x00000070)
+#define ADR_INFO29 (PHY_RATE_INFO_BASE+0x00000074)
+#define ADR_INFO30 (PHY_RATE_INFO_BASE+0x00000078)
+#define ADR_INFO31 (PHY_RATE_INFO_BASE+0x0000007c)
+#define ADR_INFO32 (PHY_RATE_INFO_BASE+0x00000080)
+#define ADR_INFO33 (PHY_RATE_INFO_BASE+0x00000084)
+#define ADR_INFO34 (PHY_RATE_INFO_BASE+0x00000088)
+#define ADR_INFO35 (PHY_RATE_INFO_BASE+0x0000008c)
+#define ADR_INFO36 (PHY_RATE_INFO_BASE+0x00000090)
+#define ADR_INFO37 (PHY_RATE_INFO_BASE+0x00000094)
+#define ADR_INFO38 (PHY_RATE_INFO_BASE+0x00000098)
+#define ADR_INFO_MASK (PHY_RATE_INFO_BASE+0x0000009c)
+#define ADR_INFO_RATE_OFFSET (PHY_RATE_INFO_BASE+0x000000a0)
+#define ADR_INFO_IDX_ADDR (PHY_RATE_INFO_BASE+0x000000a4)
+#define ADR_INFO_LEN_ADDR (PHY_RATE_INFO_BASE+0x000000a8)
+#define ADR_IC_TIME_TAG_0 (PHY_RATE_INFO_BASE+0x000000ac)
+#define ADR_IC_TIME_TAG_1 (PHY_RATE_INFO_BASE+0x000000b0)
+#define ADR_PACKET_ID_ALLOCATION_PRIORITY (PHY_RATE_INFO_BASE+0x000000b4)
+#define ADR_MAC_MODE (MAC_GLB_SET_BASE+0x00000000)
+#define ADR_ALL_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000004)
+#define ADR_ENG_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000008)
+#define ADR_CSR_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x0000000c)
+#define ADR_MAC_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000010)
+#define ADR_MAC_ENGINE_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000014)
+#define ADR_MAC_CSR_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000018)
+#define ADR_GLBLE_SET (MAC_GLB_SET_BASE+0x0000001c)
+#define ADR_REASON_TRAP0 (MAC_GLB_SET_BASE+0x00000020)
+#define ADR_REASON_TRAP1 (MAC_GLB_SET_BASE+0x00000024)
+#define ADR_BSSID_0 (MAC_GLB_SET_BASE+0x00000028)
+#define ADR_BSSID_1 (MAC_GLB_SET_BASE+0x0000002c)
+#define ADR_SCRT_STATE (MAC_GLB_SET_BASE+0x0000002c)
+#define ADR_STA_MAC_0 (MAC_GLB_SET_BASE+0x00000030)
+#define ADR_STA_MAC_1 (MAC_GLB_SET_BASE+0x00000034)
+#define ADR_SCRT_SET (MAC_GLB_SET_BASE+0x00000038)
+#define ADR_BTCX0 (BTCX_REG_BASE+0x00000000)
+#define ADR_BTCX1 (BTCX_REG_BASE+0x00000004)
+#define ADR_SWITCH_CTL (BTCX_REG_BASE+0x00000008)
+#define ADR_MIB_EN (MIB_REG_BASE+0x00000000)
+#define ADR_MTX_WSID0_SUCC (MIB_REG_BASE+0x00000118)
+#define ADR_MTX_WSID0_FRM (MIB_REG_BASE+0x00000128)
+#define ADR_MTX_WSID0_RETRY (MIB_REG_BASE+0x00000138)
+#define ADR_MTX_WSID0_TOTAL (MIB_REG_BASE+0x00000148)
+#define ADR_MTX_GROUP (MIB_REG_BASE+0x0000016c)
+#define ADR_MTX_FAIL (MIB_REG_BASE+0x00000170)
+#define ADR_MTX_RETRY (MIB_REG_BASE+0x00000174)
+#define ADR_MTX_MULTI_RETRY (MIB_REG_BASE+0x00000178)
+#define ADR_MTX_RTS_SUCCESS (MIB_REG_BASE+0x0000017c)
+#define ADR_MTX_RTS_FAIL (MIB_REG_BASE+0x00000180)
+#define ADR_MTX_ACK_FAIL (MIB_REG_BASE+0x00000184)
+#define ADR_MTX_FRM (MIB_REG_BASE+0x00000188)
+#define ADR_MTX_ACK_TX (MIB_REG_BASE+0x0000018c)
+#define ADR_MTX_CTS_TX (MIB_REG_BASE+0x00000190)
+#define ADR_MRX_DUP_FRM (MIB_REG_BASE+0x00000194)
+#define ADR_MRX_FRG_FRM (MIB_REG_BASE+0x00000198)
+#define ADR_MRX_GROUP_FRM (MIB_REG_BASE+0x0000019c)
+#define ADR_MRX_FCS_ERR (MIB_REG_BASE+0x000001a0)
+#define ADR_MRX_FCS_SUCC (MIB_REG_BASE+0x000001a4)
+#define ADR_MRX_MISS (MIB_REG_BASE+0x000001a8)
+#define ADR_MRX_ALC_FAIL (MIB_REG_BASE+0x000001ac)
+#define ADR_MRX_DAT_NTF (MIB_REG_BASE+0x000001b0)
+#define ADR_MRX_RTS_NTF (MIB_REG_BASE+0x000001b4)
+#define ADR_MRX_CTS_NTF (MIB_REG_BASE+0x000001b8)
+#define ADR_MRX_ACK_NTF (MIB_REG_BASE+0x000001bc)
+#define ADR_MRX_BA_NTF (MIB_REG_BASE+0x000001c0)
+#define ADR_MRX_DATA_NTF (MIB_REG_BASE+0x000001c4)
+#define ADR_MRX_MNG_NTF (MIB_REG_BASE+0x000001c8)
+#define ADR_MRX_DAT_CRC_NTF (MIB_REG_BASE+0x000001cc)
+#define ADR_MRX_BAR_NTF (MIB_REG_BASE+0x000001d0)
+#define ADR_MRX_MB_MISS (MIB_REG_BASE+0x000001d4)
+#define ADR_MRX_NIDLE_MISS (MIB_REG_BASE+0x000001d8)
+#define ADR_MRX_CSR_NTF (MIB_REG_BASE+0x000001dc)
+#define ADR_DBG_Q0_FRM_SUCCESS (MIB_REG_BASE+0x00000218)
+#define ADR_DBG_Q0_FRM_FAIL (MIB_REG_BASE+0x0000021c)
+#define ADR_DBG_Q0_ACK_SUCCESS (MIB_REG_BASE+0x00000220)
+#define ADR_DBG_Q0_ACK_FAIL (MIB_REG_BASE+0x00000224)
+#define ADR_DBG_Q1_FRM_SUCCESS (MIB_REG_BASE+0x00000268)
+#define ADR_DBG_Q1_FRM_FAIL (MIB_REG_BASE+0x0000026c)
+#define ADR_DBG_Q1_ACK_SUCCESS (MIB_REG_BASE+0x00000270)
+#define ADR_DBG_Q1_ACK_FAIL (MIB_REG_BASE+0x00000274)
+#define ADR_DBG_Q2_FRM_SUCCESS (MIB_REG_BASE+0x00000318)
+#define ADR_DBG_Q2_FRM_FAIL (MIB_REG_BASE+0x0000031c)
+#define ADR_DBG_Q2_ACK_SUCCESS (MIB_REG_BASE+0x00000320)
+#define ADR_DBG_Q2_ACK_FAIL (MIB_REG_BASE+0x00000324)
+#define ADR_DBG_Q3_FRM_SUCCESS (MIB_REG_BASE+0x00000368)
+#define ADR_DBG_Q3_FRM_FAIL (MIB_REG_BASE+0x0000036c)
+#define ADR_DBG_Q3_ACK_SUCCESS (MIB_REG_BASE+0x00000370)
+#define ADR_DBG_Q3_ACK_FAIL (MIB_REG_BASE+0x00000374)
+#define ADR_MIB_SCRT_TKIP0 (MIB_REG_BASE+0x00000418)
+#define ADR_MIB_SCRT_TKIP1 (MIB_REG_BASE+0x0000041c)
+#define ADR_MIB_SCRT_TKIP2 (MIB_REG_BASE+0x00000420)
+#define ADR_MIB_SCRT_CCMP0 (MIB_REG_BASE+0x00000424)
+#define ADR_MIB_SCRT_CCMP1 (MIB_REG_BASE+0x00000428)
+#define ADR_DBG_LEN_CRC_FAIL (MIB_REG_BASE+0x00000468)
+#define ADR_DBG_LEN_ALC_FAIL (MIB_REG_BASE+0x0000046c)
+#define ADR_DBG_AMPDU_PASS (MIB_REG_BASE+0x00000470)
+#define ADR_DBG_AMPDU_FAIL (MIB_REG_BASE+0x00000474)
+#define ADR_ID_ALC_FAIL1 (MIB_REG_BASE+0x00000478)
+#define ADR_ID_ALC_FAIL2 (MIB_REG_BASE+0x0000047c)
+#define ADR_CBR_HARD_WIRE_PIN_REGISTER (CBR_A_REG_BASE+0x00110000)
+#define ADR_CBR_MANUAL_ENABLE_REGISTER (CBR_A_REG_BASE+0x00110004)
+#define ADR_CBR_LDO_REGISTER (CBR_A_REG_BASE+0x00110008)
+#define ADR_CBR_ABB_REGISTER_1 (CBR_A_REG_BASE+0x0011000c)
+#define ADR_CBR_ABB_REGISTER_2 (CBR_A_REG_BASE+0x00110010)
+#define ADR_CBR_TX_FE_REGISTER (CBR_A_REG_BASE+0x00110014)
+#define ADR_CBR_RX_FE_REGISTER_1 (CBR_A_REG_BASE+0x00110018)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1 (CBR_A_REG_BASE+0x0011001c)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2 (CBR_A_REG_BASE+0x00110020)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3 (CBR_A_REG_BASE+0x00110024)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4 (CBR_A_REG_BASE+0x00110028)
+#define ADR_CBR_RX_FSM_REGISTER (CBR_A_REG_BASE+0x0011002c)
+#define ADR_CBR_RX_ADC_REGISTER (CBR_A_REG_BASE+0x00110030)
+#define ADR_CBR_TX_DAC_REGISTER (CBR_A_REG_BASE+0x00110034)
+#define ADR_CBR_SX_ENABLE_RGISTER (CBR_A_REG_BASE+0x00110038)
+#define ADR_CBR_SYN_RGISTER_1 (CBR_A_REG_BASE+0x0011003c)
+#define ADR_CBR_SYN_RGISTER_2 (CBR_A_REG_BASE+0x00110040)
+#define ADR_CBR_SYN_PFD_CHP (CBR_A_REG_BASE+0x00110044)
+#define ADR_CBR_SYN_VCO_LOBF (CBR_A_REG_BASE+0x00110048)
+#define ADR_CBR_SYN_DIV_SDM_XOSC (CBR_A_REG_BASE+0x0011004c)
+#define ADR_CBR_SYN_LCK1 (CBR_A_REG_BASE+0x00110050)
+#define ADR_CBR_SYN_LCK2 (CBR_A_REG_BASE+0x00110054)
+#define ADR_CBR_DPLL_VCO_REGISTER (CBR_A_REG_BASE+0x00110058)
+#define ADR_CBR_DPLL_CP_PFD_REGISTER (CBR_A_REG_BASE+0x0011005c)
+#define ADR_CBR_DPLL_DIVIDER_REGISTER (CBR_A_REG_BASE+0x00110060)
+#define ADR_CBR_DCOC_IDAC_REGISTER1 (CBR_A_REG_BASE+0x00110064)
+#define ADR_CBR_DCOC_IDAC_REGISTER2 (CBR_A_REG_BASE+0x00110068)
+#define ADR_CBR_DCOC_IDAC_REGISTER3 (CBR_A_REG_BASE+0x0011006c)
+#define ADR_CBR_DCOC_IDAC_REGISTER4 (CBR_A_REG_BASE+0x00110070)
+#define ADR_CBR_DCOC_IDAC_REGISTER5 (CBR_A_REG_BASE+0x00110074)
+#define ADR_CBR_DCOC_IDAC_REGISTER6 (CBR_A_REG_BASE+0x00110078)
+#define ADR_CBR_DCOC_IDAC_REGISTER7 (CBR_A_REG_BASE+0x0011007c)
+#define ADR_CBR_DCOC_IDAC_REGISTER8 (CBR_A_REG_BASE+0x00110080)
+#define ADR_CBR_RCAL_REGISTER (CBR_A_REG_BASE+0x00110084)
+#define ADR_CBR_MANUAL_REGISTER (CBR_A_REG_BASE+0x00110088)
+#define ADR_CBR_TRX_DUMMY_REGISTER (CBR_A_REG_BASE+0x0011008c)
+#define ADR_CBR_SX_DUMMY_REGISTER (CBR_A_REG_BASE+0x00110090)
+#define ADR_CBR_READ_ONLY_FLAGS_1 (CBR_A_REG_BASE+0x00110094)
+#define ADR_CBR_READ_ONLY_FLAGS_2 (CBR_A_REG_BASE+0x00110098)
+#define ADR_CBR_RG_PKT_GEN_0 (CBR_A_REG_BASE+0x00120080)
+#define ADR_CBR_RG_PKT_GEN_1 (CBR_A_REG_BASE+0x00120084)
+#define ADR_CBR_RG_PKT_GEN_2 (CBR_A_REG_BASE+0x00120088)
+#define ADR_CBR_RG_INTEGRATION (CBR_A_REG_BASE+0x00120090)
+#define ADR_CBR_RG_PKT_GEN_TXCNT (CBR_A_REG_BASE+0x00120094)
+#define ADR_CBR_PATTERN_GEN (CBR_A_REG_BASE+0x001203f8)
+#define ADR_MB_CPU_INT (MB_REG_BASE+0x00000004)
+#define ADR_CPU_ID_TB0 (MB_REG_BASE+0x00000008)
+#define ADR_CPU_ID_TB1 (MB_REG_BASE+0x0000000c)
+#define ADR_CH0_TRIG_1 (MB_REG_BASE+0x00000010)
+#define ADR_CH0_TRIG_0 (MB_REG_BASE+0x00000010)
+#define ADR_CH0_PRI_TRIG (MB_REG_BASE+0x00000014)
+#define ADR_MCU_STATUS (MB_REG_BASE+0x00000018)
+#define ADR_RD_IN_FFCNT1 (MB_REG_BASE+0x0000001c)
+#define ADR_RD_IN_FFCNT2 (MB_REG_BASE+0x00000020)
+#define ADR_RD_FFIN_FULL (MB_REG_BASE+0x00000024)
+#define ADR_MBOX_HALT_CFG (MB_REG_BASE+0x0000002c)
+#define ADR_MB_DBG_CFG1 (MB_REG_BASE+0x00000030)
+#define ADR_MB_DBG_CFG2 (MB_REG_BASE+0x00000034)
+#define ADR_MB_DBG_CFG3 (MB_REG_BASE+0x00000038)
+#define ADR_MB_DBG_CFG4 (MB_REG_BASE+0x0000003c)
+#define ADR_MB_OUT_QUEUE_CFG (MB_REG_BASE+0x00000040)
+#define ADR_MB_OUT_QUEUE_FLUSH (MB_REG_BASE+0x00000044)
+#define ADR_RD_FFOUT_CNT1 (MB_REG_BASE+0x00000048)
+#define ADR_RD_FFOUT_CNT2 (MB_REG_BASE+0x0000004c)
+#define ADR_RD_FFOUT_CNT3 (MB_REG_BASE+0x00000050)
+#define ADR_RD_FFOUT_FULL (MB_REG_BASE+0x00000054)
+#define ADR_MB_THRESHOLD6 (MB_REG_BASE+0x0000006c)
+#define ADR_MB_THRESHOLD7 (MB_REG_BASE+0x00000070)
+#define ADR_MB_THRESHOLD8 (MB_REG_BASE+0x00000074)
+#define ADR_MB_THRESHOLD9 (MB_REG_BASE+0x00000078)
+#define ADR_MB_THRESHOLD10 (MB_REG_BASE+0x0000007c)
+#define ADR_MB_TRASH_CFG (MB_REG_BASE+0x00000080)
+#define ADR_MB_IN_FF_FLUSH (MB_REG_BASE+0x00000084)
+#define ADR_CPU_ID_TB2 (MB_REG_BASE+0x00000088)
+#define ADR_CPU_ID_TB3 (MB_REG_BASE+0x0000008c)
+#define ADR_PHY_IQ_LOG_CFG0 (MB_REG_BASE+0x00000090)
+#define ADR_PHY_IQ_LOG_CFG1 (MB_REG_BASE+0x00000094)
+#define ADR_PHY_IQ_LOG_LEN (MB_REG_BASE+0x00000098)
+#define ADR_PHY_IQ_LOG_PTR (MB_REG_BASE+0x0000009c)
+#define ADR_WR_ALC (ID_MNG_REG_BASE+0x00000000)
+#define ADR_GETID (ID_MNG_REG_BASE+0x00000000)
+#define ADR_CH_STA_PRI (ID_MNG_REG_BASE+0x00000004)
+#define ADR_RD_ID0 (ID_MNG_REG_BASE+0x00000008)
+#define ADR_RD_ID1 (ID_MNG_REG_BASE+0x0000000c)
+#define ADR_IMD_CFG (ID_MNG_REG_BASE+0x00000010)
+#define ADR_IMD_STA (ID_MNG_REG_BASE+0x00000014)
+#define ADR_ALC_STA (ID_MNG_REG_BASE+0x00000018)
+#define ADR_TRX_ID_COUNT (ID_MNG_REG_BASE+0x0000001c)
+#define ADR_TRX_ID_THRESHOLD (ID_MNG_REG_BASE+0x00000020)
+#define ADR_TX_ID0 (ID_MNG_REG_BASE+0x00000024)
+#define ADR_TX_ID1 (ID_MNG_REG_BASE+0x00000028)
+#define ADR_RX_ID0 (ID_MNG_REG_BASE+0x0000002c)
+#define ADR_RX_ID1 (ID_MNG_REG_BASE+0x00000030)
+#define ADR_RTN_STA (ID_MNG_REG_BASE+0x00000034)
+#define ADR_ID_LEN_THREADSHOLD1 (ID_MNG_REG_BASE+0x00000038)
+#define ADR_ID_LEN_THREADSHOLD2 (ID_MNG_REG_BASE+0x0000003c)
+#define ADR_CH_ARB_PRI (ID_MNG_REG_BASE+0x00000040)
+#define ADR_TX_ID_REMAIN_STATUS (ID_MNG_REG_BASE+0x00000044)
+#define ADR_ID_INFO_STA (ID_MNG_REG_BASE+0x00000048)
+#define ADR_TX_LIMIT_INTR (ID_MNG_REG_BASE+0x0000004c)
+#define ADR_TX_ID_ALL_INFO (ID_MNG_REG_BASE+0x00000050)
+#define ADR_RD_ID2 (ID_MNG_REG_BASE+0x00000054)
+#define ADR_RD_ID3 (ID_MNG_REG_BASE+0x00000058)
+#define ADR_TX_ID2 (ID_MNG_REG_BASE+0x0000005c)
+#define ADR_TX_ID3 (ID_MNG_REG_BASE+0x00000060)
+#define ADR_RX_ID2 (ID_MNG_REG_BASE+0x00000064)
+#define ADR_RX_ID3 (ID_MNG_REG_BASE+0x00000068)
+#define ADR_TX_ID_ALL_INFO2 (ID_MNG_REG_BASE+0x0000006c)
+#define ADR_TX_ID_ALL_INFO_A (ID_MNG_REG_BASE+0x00000070)
+#define ADR_TX_ID_ALL_INFO_B (ID_MNG_REG_BASE+0x00000074)
+#define ADR_TX_ID_REMAIN_STATUS2 (ID_MNG_REG_BASE+0x00000078)
+#define ADR_ALC_ID_INFO (ID_MNG_REG_BASE+0x0000007c)
+#define ADR_ALC_ID_INF1 (ID_MNG_REG_BASE+0x00000080)
+#define ADR_PHY_EN_0 (CSR_PHY_BASE+0x00000000)
+#define ADR_PHY_EN_1 (CSR_PHY_BASE+0x00000004)
+#define ADR_SVN_VERSION_REG (CSR_PHY_BASE+0x00000008)
+#define ADR_PHY_PKT_GEN_0 (CSR_PHY_BASE+0x0000000c)
+#define ADR_PHY_PKT_GEN_1 (CSR_PHY_BASE+0x00000010)
+#define ADR_PHY_PKT_GEN_2 (CSR_PHY_BASE+0x00000014)
+#define ADR_PHY_PKT_GEN_3 (CSR_PHY_BASE+0x00000018)
+#define ADR_PHY_PKT_GEN_4 (CSR_PHY_BASE+0x0000001c)
+#define ADR_PHY_REG_00 (CSR_PHY_BASE+0x00000020)
+#define ADR_PHY_REG_01 (CSR_PHY_BASE+0x0000002c)
+#define ADR_PHY_REG_02_AGC (CSR_PHY_BASE+0x00000030)
+#define ADR_PHY_REG_03_AGC (CSR_PHY_BASE+0x00000034)
+#define ADR_PHY_REG_04_AGC (CSR_PHY_BASE+0x00000038)
+#define ADR_PHY_REG_05_AGC (CSR_PHY_BASE+0x0000003c)
+#define ADR_PHY_REG_06_11B_DAGC (CSR_PHY_BASE+0x00000040)
+#define ADR_PHY_REG_07_11B_DAGC (CSR_PHY_BASE+0x00000044)
+#define ADR_PHY_REG_08_11GN_DAGC (CSR_PHY_BASE+0x00000048)
+#define ADR_PHY_REG_09_11GN_DAGC (CSR_PHY_BASE+0x0000004c)
+#define ADR_PHY_READ_REG_00_DIG_PWR (CSR_PHY_BASE+0x00000050)
+#define ADR_PHY_READ_REG_01_RF_GAIN_PWR (CSR_PHY_BASE+0x00000054)
+#define ADR_PHY_READ_REG_02_RF_GAIN_PWR (CSR_PHY_BASE+0x00000058)
+#define ADR_PHY_READ_REG_03_RF_GAIN_PWR (CSR_PHY_BASE+0x0000005c)
+#define ADR_PHY_REG_10_TX_DES (CSR_PHY_BASE+0x00000060)
+#define ADR_PHY_REG_11_TX_DES (CSR_PHY_BASE+0x00000064)
+#define ADR_PHY_REG_12_TX_DES (CSR_PHY_BASE+0x00000068)
+#define ADR_PHY_REG_13_RX_DES (CSR_PHY_BASE+0x0000006c)
+#define ADR_PHY_REG_14_RX_DES (CSR_PHY_BASE+0x00000070)
+#define ADR_PHY_REG_15_RX_DES (CSR_PHY_BASE+0x00000074)
+#define ADR_PHY_REG_16_TX_DES_EXCP (CSR_PHY_BASE+0x00000078)
+#define ADR_PHY_REG_17_TX_DES_EXCP (CSR_PHY_BASE+0x0000007c)
+#define ADR_PHY_REG_18_RSSI_SNR (CSR_PHY_BASE+0x00000080)
+#define ADR_PHY_REG_19_DAC_MANUAL (CSR_PHY_BASE+0x00000084)
+#define ADR_PHY_REG_20_MRX_CNT (CSR_PHY_BASE+0x00000088)
+#define ADR_PHY_REG_21_TRX_RAMP (CSR_PHY_BASE+0x00000094)
+#define ADR_PHY_REG_22_TRX_RAMP (CSR_PHY_BASE+0x00000098)
+#define ADR_PHY_REG_23_ANT (CSR_PHY_BASE+0x0000009c)
+#define ADR_PHY_REG_24_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a0)
+#define ADR_PHY_REG_25_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a4)
+#define ADR_PHY_REG_26_MRX_LEN_CNT (CSR_PHY_BASE+0x000000a8)
+#define ADR_PHY_REG_27_MRX_LEN_CNT (CSR_PHY_BASE+0x000000ac)
+#define ADR_PHY_READ_REG_04 (CSR_PHY_BASE+0x000000b0)
+#define ADR_PHY_READ_REG_05 (CSR_PHY_BASE+0x000000b4)
+#define ADR_PHY_REG_28_BIST (CSR_PHY_BASE+0x000000b8)
+#define ADR_PHY_READ_REG_06_BIST (CSR_PHY_BASE+0x000000d8)
+#define ADR_PHY_READ_REG_07_BIST (CSR_PHY_BASE+0x000000f0)
+#define ADR_PHY_REG_29_MTRX_MAC (CSR_PHY_BASE+0x000000fc)
+#define ADR_PHY_READ_REG_08_MTRX_MAC (CSR_PHY_BASE+0x00000100)
+#define ADR_PHY_READ_REG_09_MTRX_MAC (CSR_PHY_BASE+0x00000104)
+#define ADR_PHY_REG_30_TX_UP_FIL (CSR_PHY_BASE+0x00000108)
+#define ADR_PHY_REG_31_TX_UP_FIL (CSR_PHY_BASE+0x0000010c)
+#define ADR_PHY_REG_32_TX_UP_FIL (CSR_PHY_BASE+0x00000110)
+#define ADR_PHY_READ_TBUS (CSR_PHY_BASE+0x000003fc)
+#define ADR_TX_11B_FIL_COEF_00 (CSR_PHY_BASE+0x00001000)
+#define ADR_TX_11B_FIL_COEF_01 (CSR_PHY_BASE+0x00001004)
+#define ADR_TX_11B_FIL_COEF_02 (CSR_PHY_BASE+0x00001008)
+#define ADR_TX_11B_FIL_COEF_03 (CSR_PHY_BASE+0x0000100c)
+#define ADR_TX_11B_FIL_COEF_04 (CSR_PHY_BASE+0x00001010)
+#define ADR_TX_11B_FIL_COEF_05 (CSR_PHY_BASE+0x00001014)
+#define ADR_TX_11B_FIL_COEF_06 (CSR_PHY_BASE+0x00001018)
+#define ADR_TX_11B_FIL_COEF_07 (CSR_PHY_BASE+0x0000101c)
+#define ADR_TX_11B_FIL_COEF_08 (CSR_PHY_BASE+0x00001020)
+#define ADR_TX_11B_FIL_COEF_09 (CSR_PHY_BASE+0x00001024)
+#define ADR_TX_11B_FIL_COEF_10 (CSR_PHY_BASE+0x00001028)
+#define ADR_TX_11B_FIL_COEF_11 (CSR_PHY_BASE+0x0000102c)
+#define ADR_TX_11B_FIL_COEF_12 (CSR_PHY_BASE+0x00001030)
+#define ADR_TX_11B_FIL_COEF_13 (CSR_PHY_BASE+0x00001034)
+#define ADR_TX_11B_FIL_COEF_14 (CSR_PHY_BASE+0x00001038)
+#define ADR_TX_11B_FIL_COEF_15 (CSR_PHY_BASE+0x0000103c)
+#define ADR_TX_11B_FIL_COEF_16 (CSR_PHY_BASE+0x00001040)
+#define ADR_TX_11B_FIL_COEF_17 (CSR_PHY_BASE+0x00001044)
+#define ADR_TX_11B_FIL_COEF_18 (CSR_PHY_BASE+0x00001048)
+#define ADR_TX_11B_FIL_COEF_19 (CSR_PHY_BASE+0x0000104c)
+#define ADR_TX_11B_FIL_COEF_20 (CSR_PHY_BASE+0x00001050)
+#define ADR_TX_11B_FIL_COEF_21 (CSR_PHY_BASE+0x00001054)
+#define ADR_TX_11B_FIL_COEF_22 (CSR_PHY_BASE+0x00001058)
+#define ADR_TX_11B_FIL_COEF_23 (CSR_PHY_BASE+0x0000105c)
+#define ADR_TX_11B_FIL_COEF_24 (CSR_PHY_BASE+0x00001060)
+#define ADR_TX_11B_FIL_COEF_25 (CSR_PHY_BASE+0x00001064)
+#define ADR_TX_11B_FIL_COEF_26 (CSR_PHY_BASE+0x00001068)
+#define ADR_TX_11B_FIL_COEF_27 (CSR_PHY_BASE+0x0000106c)
+#define ADR_TX_11B_FIL_COEF_28 (CSR_PHY_BASE+0x00001070)
+#define ADR_TX_11B_FIL_COEF_29 (CSR_PHY_BASE+0x00001074)
+#define ADR_TX_11B_FIL_COEF_30 (CSR_PHY_BASE+0x00001078)
+#define ADR_TX_11B_FIL_COEF_31 (CSR_PHY_BASE+0x0000107c)
+#define ADR_TX_11B_FIL_COEF_32 (CSR_PHY_BASE+0x00001080)
+#define ADR_TX_11B_FIL_COEF_33 (CSR_PHY_BASE+0x00001084)
+#define ADR_TX_11B_FIL_COEF_34 (CSR_PHY_BASE+0x00001088)
+#define ADR_TX_11B_FIL_COEF_35 (CSR_PHY_BASE+0x0000108c)
+#define ADR_TX_11B_FIL_COEF_36 (CSR_PHY_BASE+0x00001090)
+#define ADR_TX_11B_FIL_COEF_37 (CSR_PHY_BASE+0x00001094)
+#define ADR_TX_11B_FIL_COEF_38 (CSR_PHY_BASE+0x00001098)
+#define ADR_TX_11B_FIL_COEF_39 (CSR_PHY_BASE+0x0000109c)
+#define ADR_TX_11B_FIL_COEF_40 (CSR_PHY_BASE+0x000010a0)
+#define ADR_TX_11B_PLCP (CSR_PHY_BASE+0x000010a4)
+#define ADR_TX_11B_RAMP (CSR_PHY_BASE+0x000010b4)
+#define ADR_TX_11B_EN_CNT_RST_N (CSR_PHY_BASE+0x000010d4)
+#define ADR_TX_11B_EN_CNT (CSR_PHY_BASE+0x000010d8)
+#define ADR_TX_11B_PKT_GEN_CNT (CSR_PHY_BASE+0x00001c00)
+#define ADR_RX_11B_DES_DLY (CSR_PHY_BASE+0x00002000)
+#define ADR_RX_11B_CCA_0 (CSR_PHY_BASE+0x00002004)
+#define ADR_RX_11B_CCA_1 (CSR_PHY_BASE+0x00002008)
+#define ADR_RX_11B_TR_KP_KI_0 (CSR_PHY_BASE+0x0000200c)
+#define ADR_RX_11B_TR_KP_KI_1 (CSR_PHY_BASE+0x00002010)
+#define ADR_RX_11B_CE_CNT_THRESHOLD (CSR_PHY_BASE+0x00002014)
+#define ADR_RX_11B_CE_MU_0 (CSR_PHY_BASE+0x00002018)
+#define ADR_RX_11B_CE_MU_1 (CSR_PHY_BASE+0x0000201c)
+#define ADR_RX_11B_EQ_MU_0 (CSR_PHY_BASE+0x00002020)
+#define ADR_RX_11B_EQ_MU_1 (CSR_PHY_BASE+0x00002024)
+#define ADR_RX_11B_EQ_CR_KP_KI (CSR_PHY_BASE+0x00002028)
+#define ADR_RX_11B_LPF_RATE (CSR_PHY_BASE+0x0000202c)
+#define ADR_RX_11B_CIT_CNT_THRESHOLD (CSR_PHY_BASE+0x00002030)
+#define ADR_RX_11B_EQ_CH_MAIN_TAP (CSR_PHY_BASE+0x00002034)
+#define ADR_RX_11B_SEARCH_CNT_TH (CSR_PHY_BASE+0x0000209c)
+#define ADR_RX_11B_CCA_CONTROL (CSR_PHY_BASE+0x000020a0)
+#define ADR_RX_11B_FREQUENCY_OFFSET (CSR_PHY_BASE+0x000023d4)
+#define ADR_RX_11B_SNR_RSSI (CSR_PHY_BASE+0x000023d8)
+#define ADR_RX_11B_SFD_CRC_CNT (CSR_PHY_BASE+0x000023e4)
+#define ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT (CSR_PHY_BASE+0x000023e8)
+#define ADR_RX_11B_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000023ec)
+#define ADR_RX_11B_SFD_FILED_0 (CSR_PHY_BASE+0x000023f0)
+#define ADR_RX_11B_SFD_FIELD_1 (CSR_PHY_BASE+0x000023f4)
+#define ADR_RX_11B_PKT_STAT_EN (CSR_PHY_BASE+0x000023f8)
+#define ADR_RX_11B_SOFT_RST (CSR_PHY_BASE+0x000023fc)
+#define ADR_TX_11GN_RAMP (CSR_PHY_BASE+0x000030a4)
+#define ADR_TX_11GN_PLCP (CSR_PHY_BASE+0x000030b8)
+#define ADR_TX_11GN_PKT_GEN_CNT (CSR_PHY_BASE+0x00003c00)
+#define ADR_TX_11GN_PLCP_CRC_ERR_CNT (CSR_PHY_BASE+0x00003c08)
+#define ADR_RX_11GN_DES_DLY (CSR_PHY_BASE+0x00004000)
+#define ADR_RX_11GN_TR_0 (CSR_PHY_BASE+0x00004004)
+#define ADR_RX_11GN_TR_1 (CSR_PHY_BASE+0x00004008)
+#define ADR_RX_11GN_TR_2 (CSR_PHY_BASE+0x0000400c)
+#define ADR_RX_11GN_CCA_0 (CSR_PHY_BASE+0x00004010)
+#define ADR_RX_11GN_CCA_1 (CSR_PHY_BASE+0x00004014)
+#define ADR_RX_11GN_CCA_2 (CSR_PHY_BASE+0x00004018)
+#define ADR_RX_11GN_CCA_FFT_SCALE (CSR_PHY_BASE+0x0000401c)
+#define ADR_RX_11GN_SOFT_DEMAP_0 (CSR_PHY_BASE+0x00004020)
+#define ADR_RX_11GN_SOFT_DEMAP_1 (CSR_PHY_BASE+0x00004024)
+#define ADR_RX_11GN_SOFT_DEMAP_2 (CSR_PHY_BASE+0x00004028)
+#define ADR_RX_11GN_SOFT_DEMAP_3 (CSR_PHY_BASE+0x0000402c)
+#define ADR_RX_11GN_SOFT_DEMAP_4 (CSR_PHY_BASE+0x00004030)
+#define ADR_RX_11GN_SOFT_DEMAP_5 (CSR_PHY_BASE+0x00004034)
+#define ADR_RX_11GN_SYM_BOUND_0 (CSR_PHY_BASE+0x00004038)
+#define ADR_RX_11GN_SYM_BOUND_1 (CSR_PHY_BASE+0x0000409c)
+#define ADR_RX_11GN_CCA_PWR (CSR_PHY_BASE+0x000040c0)
+#define ADR_RX_11GN_CCA_CNT (CSR_PHY_BASE+0x000040c4)
+#define ADR_RX_11GN_CCA_ATCOR_RE_CHECK (CSR_PHY_BASE+0x000040c8)
+#define ADR_RX_11GN_VTB_TB (CSR_PHY_BASE+0x00004130)
+#define ADR_RX_11GN_ERR_UPDATE (CSR_PHY_BASE+0x00004164)
+#define ADR_RX_11GN_SHORT_GI (CSR_PHY_BASE+0x00004180)
+#define ADR_RX_11GN_CHANNEL_UPDATE (CSR_PHY_BASE+0x00004188)
+#define ADR_RX_11GN_PKT_FORMAT_0 (CSR_PHY_BASE+0x00004190)
+#define ADR_RX_11GN_PKT_FORMAT_1 (CSR_PHY_BASE+0x00004194)
+#define ADR_RX_11GN_TX_TIME (CSR_PHY_BASE+0x00004380)
+#define ADR_RX_11GN_STBC_TR_KP_KI (CSR_PHY_BASE+0x00004384)
+#define ADR_RX_11GN_BIST_0 (CSR_PHY_BASE+0x00004388)
+#define ADR_RX_11GN_BIST_1 (CSR_PHY_BASE+0x0000438c)
+#define ADR_RX_11GN_BIST_2 (CSR_PHY_BASE+0x000043c0)
+#define ADR_RX_11GN_BIST_3 (CSR_PHY_BASE+0x000043c4)
+#define ADR_RX_11GN_BIST_4 (CSR_PHY_BASE+0x000043c8)
+#define ADR_RX_11GN_BIST_5 (CSR_PHY_BASE+0x000043cc)
+#define ADR_RX_11GN_SPECTRUM_ANALYZER (CSR_PHY_BASE+0x000043d4)
+#define ADR_RX_11GN_READ_0 (CSR_PHY_BASE+0x000043d8)
+#define ADR_RX_11GN_FREQ_OFFSET (CSR_PHY_BASE+0x000043dc)
+#define ADR_RX_11GN_SIGNAL_FIELD_0 (CSR_PHY_BASE+0x000043e0)
+#define ADR_RX_11GN_SIGNAL_FIELD_1 (CSR_PHY_BASE+0x000043e4)
+#define ADR_RX_11GN_PKT_ERR_CNT (CSR_PHY_BASE+0x000043e8)
+#define ADR_RX_11GN_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000043ec)
+#define ADR_RX_11GN_SERVICE_LENGTH_FIELD (CSR_PHY_BASE+0x000043f0)
+#define ADR_RX_11GN_RATE (CSR_PHY_BASE+0x000043f4)
+#define ADR_RX_11GN_STAT_EN (CSR_PHY_BASE+0x000043f8)
+#define ADR_RX_11GN_SOFT_RST (CSR_PHY_BASE+0x000043fc)
+#define ADR_RF_CONTROL_0 (CSR_PHY_BASE+0x00007000)
+#define ADR_RF_CONTROL_1 (CSR_PHY_BASE+0x00007004)
+#define ADR_TX_IQ_CONTROL_0 (CSR_PHY_BASE+0x00007040)
+#define ADR_TX_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007044)
+#define ADR_TX_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007048)
+#define ADR_TX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x0000704c)
+#define ADR_RX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x00007050)
+#define ADR_RX_OBSERVATION_CIRCUIT_0 (CSR_PHY_BASE+0x00007058)
+#define ADR_RX_OBSERVATION_CIRCUIT_1 (CSR_PHY_BASE+0x0000705c)
+#define ADR_RX_OBSERVATION_CIRCUIT_2 (CSR_PHY_BASE+0x00007060)
+#define ADR_RX_OBSERVATION_CIRCUIT_3 (CSR_PHY_BASE+0x00007064)
+#define ADR_RF_IQ_CONTROL_0 (CSR_PHY_BASE+0x0000706c)
+#define ADR_RF_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007070)
+#define ADR_RF_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007074)
+#define ADR_RF_IQ_CONTROL_3 (CSR_PHY_BASE+0x00007078)
+#define ADR_DPD_CONTROL (CSR_PHY_BASE+0x0000711c)
+#define ADR_DPD_GAIN_TABLE_0 (CSR_PHY_BASE+0x00007120)
+#define ADR_DPD_GAIN_TABLE_1 (CSR_PHY_BASE+0x00007124)
+#define ADR_DPD_GAIN_TABLE_2 (CSR_PHY_BASE+0x00007128)
+#define ADR_DPD_GAIN_TABLE_3 (CSR_PHY_BASE+0x00007130)
+#define ADR_DPD_GAIN_TABLE_4 (CSR_PHY_BASE+0x00007134)
+#define ADR_DPD_GAIN_TABLE_5 (CSR_PHY_BASE+0x00007138)
+#define ADR_DPD_GAIN_TABLE_6 (CSR_PHY_BASE+0x0000713c)
+#define ADR_DPD_GAIN_TABLE_7 (CSR_PHY_BASE+0x00007140)
+#define ADR_DPD_GAIN_TABLE_8 (CSR_PHY_BASE+0x00007144)
+#define ADR_DPD_GAIN_TABLE_9 (CSR_PHY_BASE+0x00007148)
+#define ADR_DPD_GAIN_TABLE_A (CSR_PHY_BASE+0x0000714c)
+#define ADR_DPD_GAIN_TABLE_B (CSR_PHY_BASE+0x00007150)
+#define ADR_DPD_GAIN_TABLE_C (CSR_PHY_BASE+0x00007154)
+#define ADR_DPD_PH_TABLE_0 (CSR_PHY_BASE+0x00007170)
+#define ADR_DPD_PH_TABLE_1 (CSR_PHY_BASE+0x00007174)
+#define ADR_DPD_PH_TABLE_2 (CSR_PHY_BASE+0x00007178)
+#define ADR_DPD_PH_TABLE_3 (CSR_PHY_BASE+0x00007180)
+#define ADR_DPD_PH_TABLE_4 (CSR_PHY_BASE+0x00007184)
+#define ADR_DPD_PH_TABLE_5 (CSR_PHY_BASE+0x00007188)
+#define ADR_DPD_PH_TABLE_6 (CSR_PHY_BASE+0x0000718c)
+#define ADR_DPD_PH_TABLE_7 (CSR_PHY_BASE+0x00007190)
+#define ADR_DPD_PH_TABLE_8 (CSR_PHY_BASE+0x00007194)
+#define ADR_DPD_PH_TABLE_9 (CSR_PHY_BASE+0x00007198)
+#define ADR_DPD_PH_TABLE_A (CSR_PHY_BASE+0x0000719c)
+#define ADR_DPD_PH_TABLE_B (CSR_PHY_BASE+0x000071a0)
+#define ADR_DPD_PH_TABLE_C (CSR_PHY_BASE+0x000071a4)
+#define ADR_DPD_GAIN_ESTIMATION_0 (CSR_PHY_BASE+0x000071b0)
+#define ADR_DPD_GAIN_ESTIMATION_1 (CSR_PHY_BASE+0x000071b4)
+#define ADR_DPD_GAIN_ESTIMATION_2 (CSR_PHY_BASE+0x000071b8)
+#define ADR_TX_GAIN_FACTOR (CSR_PHY_BASE+0x000071bc)
+#define ADR_HARD_WIRE_PIN_REGISTER (CSR_RF_BASE+0x00000000)
+#define ADR_MANUAL_ENABLE_REGISTER (CSR_RF_BASE+0x00000004)
+#define ADR_LDO_REGISTER (CSR_RF_BASE+0x00000008)
+#define ADR_ABB_REGISTER_1 (CSR_RF_BASE+0x0000000c)
+#define ADR_ABB_REGISTER_2 (CSR_RF_BASE+0x00000010)
+#define ADR_TX_FE_REGISTER (CSR_RF_BASE+0x00000014)
+#define ADR_RX_FE_REGISTER_1 (CSR_RF_BASE+0x00000018)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_1 (CSR_RF_BASE+0x0000001c)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_2 (CSR_RF_BASE+0x00000020)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_3 (CSR_RF_BASE+0x00000024)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_4 (CSR_RF_BASE+0x00000028)
+#define ADR_RX_TX_FSM_REGISTER (CSR_RF_BASE+0x0000002c)
+#define ADR_RX_ADC_REGISTER (CSR_RF_BASE+0x00000030)
+#define ADR_TX_DAC_REGISTER (CSR_RF_BASE+0x00000034)
+#define ADR_SX_ENABLE_REGISTER (CSR_RF_BASE+0x00000038)
+#define ADR_SYN_REGISTER_1 (CSR_RF_BASE+0x0000003c)
+#define ADR_SYN_REGISTER_2 (CSR_RF_BASE+0x00000040)
+#define ADR_SYN_PFD_CHP (CSR_RF_BASE+0x00000044)
+#define ADR_SYN_VCO_LOBF (CSR_RF_BASE+0x00000048)
+#define ADR_SYN_DIV_SDM_XOSC (CSR_RF_BASE+0x0000004c)
+#define ADR_SYN_KVCO_XO_FINE_TUNE_CBANK (CSR_RF_BASE+0x00000050)
+#define ADR_SYN_LCK_VT (CSR_RF_BASE+0x00000054)
+#define ADR_DPLL_VCO_REGISTER (CSR_RF_BASE+0x00000058)
+#define ADR_DPLL_CP_PFD_REGISTER (CSR_RF_BASE+0x0000005c)
+#define ADR_DPLL_DIVIDER_REGISTER (CSR_RF_BASE+0x00000060)
+#define ADR_DCOC_IDAC_REGISTER1 (CSR_RF_BASE+0x00000064)
+#define ADR_DCOC_IDAC_REGISTER2 (CSR_RF_BASE+0x00000068)
+#define ADR_DCOC_IDAC_REGISTER3 (CSR_RF_BASE+0x0000006c)
+#define ADR_DCOC_IDAC_REGISTER4 (CSR_RF_BASE+0x00000070)
+#define ADR_DCOC_IDAC_REGISTER5 (CSR_RF_BASE+0x00000074)
+#define ADR_DCOC_IDAC_REGISTER6 (CSR_RF_BASE+0x00000078)
+#define ADR_DCOC_IDAC_REGISTER7 (CSR_RF_BASE+0x0000007c)
+#define ADR_DCOC_IDAC_REGISTER8 (CSR_RF_BASE+0x00000080)
+#define ADR_RCAL_REGISTER (CSR_RF_BASE+0x00000084)
+#define ADR_SX_LCK_BIN_REGISTERS_I (CSR_RF_BASE+0x00000088)
+#define ADR_TRX_DUMMY_REGISTER (CSR_RF_BASE+0x0000008c)
+#define ADR_SX_DUMMY_REGISTER (CSR_RF_BASE+0x00000090)
+#define ADR_READ_ONLY_FLAGS_1 (CSR_RF_BASE+0x00000094)
+#define ADR_READ_ONLY_FLAGS_2 (CSR_RF_BASE+0x00000098)
+#define ADR_DPLL_FB_DIVIDER_REGISTERS_I (CSR_RF_BASE+0x0000009c)
+#define ADR_DPLL_FB_DIVIDER_REGISTERS_II (CSR_RF_BASE+0x000000a0)
+#define ADR_SX_LCK_BIN_REGISTERS_II (CSR_RF_BASE+0x000000a4)
+#define ADR_RC_OSC_32K_CAL_REGISTERS (CSR_RF_BASE+0x000000a8)
+#define ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER (CSR_RF_BASE+0x000000ac)
+#define ADR_MMU_CTRL (MMU_REG_BASE+0x00000000)
+#define ADR_HS_CTRL (MMU_REG_BASE+0x00000004)
+#define ADR_CPU_POR0_7 (MMU_REG_BASE+0x00000008)
+#define ADR_CPU_POR8_F (MMU_REG_BASE+0x0000000c)
+#define ADR_REG_LEN_CTRL (MMU_REG_BASE+0x00000010)
+#define ADR_DMN_READ_BYPASS (MMU_REG_BASE+0x00000014)
+#define ADR_ALC_RLS_ABORT (MMU_REG_BASE+0x00000018)
+#define ADR_DEBUG_CTL (MMU_REG_BASE+0x00000020)
+#define ADR_DEBUG_OUT (MMU_REG_BASE+0x00000024)
+#define ADR_MMU_STATUS (MMU_REG_BASE+0x00000028)
+#define ADR_DMN_STATUS (MMU_REG_BASE+0x0000002c)
+#define ADR_TAG_STATUS (MMU_REG_BASE+0x00000030)
+#define ADR_DMN_MCU_STATUS (MMU_REG_BASE+0x00000034)
+#define ADR_MB_IDTBL_0_STATUS (MMU_REG_BASE+0x00000040)
+#define ADR_MB_IDTBL_1_STATUS (MMU_REG_BASE+0x00000044)
+#define ADR_MB_IDTBL_2_STATUS (MMU_REG_BASE+0x00000048)
+#define ADR_MB_IDTBL_3_STATUS (MMU_REG_BASE+0x0000004c)
+#define ADR_PKT_IDTBL_0_STATUS (MMU_REG_BASE+0x00000050)
+#define ADR_PKT_IDTBL_1_STATUS (MMU_REG_BASE+0x00000054)
+#define ADR_PKT_IDTBL_2_STATUS (MMU_REG_BASE+0x00000058)
+#define ADR_PKT_IDTBL_3_STATUS (MMU_REG_BASE+0x0000005c)
+#define ADR_DMN_IDTBL_0_STATUS (MMU_REG_BASE+0x00000060)
+#define ADR_DMN_IDTBL_1_STATUS (MMU_REG_BASE+0x00000064)
+#define ADR_DMN_IDTBL_2_STATUS (MMU_REG_BASE+0x00000068)
+#define ADR_DMN_IDTBL_3_STATUS (MMU_REG_BASE+0x0000006c)
+#define ADR_MB_NEQID_0_STATUS (MMU_REG_BASE+0x00000070)
+#define ADR_MB_NEQID_1_STATUS (MMU_REG_BASE+0x00000074)
+#define ADR_MB_NEQID_2_STATUS (MMU_REG_BASE+0x00000078)
+#define ADR_MB_NEQID_3_STATUS (MMU_REG_BASE+0x0000007c)
+#define ADR_PKT_NEQID_0_STATUS (MMU_REG_BASE+0x00000080)
+#define ADR_PKT_NEQID_1_STATUS (MMU_REG_BASE+0x00000084)
+#define ADR_PKT_NEQID_2_STATUS (MMU_REG_BASE+0x00000088)
+#define ADR_PKT_NEQID_3_STATUS (MMU_REG_BASE+0x0000008c)
+#define ADR_ALC_NOCHG_ID_STATUS (MMU_REG_BASE+0x00000090)
+#define ADR_TAG_SRAM0_F_STATUS_0 (MMU_REG_BASE+0x000000a0)
+#define ADR_TAG_SRAM0_F_STATUS_1 (MMU_REG_BASE+0x000000a4)
+#define ADR_TAG_SRAM0_F_STATUS_2 (MMU_REG_BASE+0x000000a8)
+#define ADR_TAG_SRAM0_F_STATUS_3 (MMU_REG_BASE+0x000000ac)
+#define ADR_TAG_SRAM0_F_STATUS_4 (MMU_REG_BASE+0x000000b0)
+#define ADR_TAG_SRAM0_F_STATUS_5 (MMU_REG_BASE+0x000000b4)
+#define ADR_TAG_SRAM0_F_STATUS_6 (MMU_REG_BASE+0x000000b8)
+#define ADR_TAG_SRAM0_F_STATUS_7 (MMU_REG_BASE+0x000000bc)
+#define GET_MCU_ENABLE (((REG32(ADR_BRG_SW_RST)) & 0x00000001 ) >> 0)
+#define GET_MAC_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000002 ) >> 1)
+#define GET_MCU_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000004 ) >> 2)
+#define GET_SDIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000008 ) >> 3)
+#define GET_SPI_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000010 ) >> 4)
+#define GET_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000020 ) >> 5)
+#define GET_DMA_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000040 ) >> 6)
+#define GET_WDT_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000080 ) >> 7)
+#define GET_I2C_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000100 ) >> 8)
+#define GET_INT_CTL_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000200 ) >> 9)
+#define GET_BTCX_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000400 ) >> 10)
+#define GET_GPIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000800 ) >> 11)
+#define GET_US0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00001000 ) >> 12)
+#define GET_US1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00002000 ) >> 13)
+#define GET_US2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00004000 ) >> 14)
+#define GET_US3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00008000 ) >> 15)
+#define GET_MS0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00010000 ) >> 16)
+#define GET_MS1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00020000 ) >> 17)
+#define GET_MS2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00040000 ) >> 18)
+#define GET_MS3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00080000 ) >> 19)
+#define GET_RF_BB_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00100000 ) >> 20)
+#define GET_SYS_ALL_RST (((REG32(ADR_BRG_SW_RST)) & 0x00200000 ) >> 21)
+#define GET_DAT_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00400000 ) >> 22)
+#define GET_I2C_MST_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00800000 ) >> 23)
+#define GET_RG_REBOOT (((REG32(ADR_BOOT)) & 0x00000001 ) >> 0)
+#define GET_TRAP_IMG_FLS (((REG32(ADR_BOOT)) & 0x00010000 ) >> 16)
+#define GET_TRAP_REBOOT (((REG32(ADR_BOOT)) & 0x00020000 ) >> 17)
+#define GET_TRAP_BOOT_FLS (((REG32(ADR_BOOT)) & 0x00040000 ) >> 18)
+#define GET_CHIP_ID_31_0 (((REG32(ADR_CHIP_ID_0)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_63_32 (((REG32(ADR_CHIP_ID_1)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_95_64 (((REG32(ADR_CHIP_ID_2)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_127_96 (((REG32(ADR_CHIP_ID_3)) & 0xffffffff ) >> 0)
+#define GET_CK_SEL_1_0 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000003 ) >> 0)
+#define GET_CK_SEL_2 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000004 ) >> 2)
+#define GET_SYS_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_MAC_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MCU_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000004 ) >> 2)
+#define GET_SDIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_SPI_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_UART_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_DMA_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_WDT_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
+#define GET_I2C_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000100 ) >> 8)
+#define GET_INT_CTL_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
+#define GET_BTCX_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_GPIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_US0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_US1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_US2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_US3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_MS0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00010000 ) >> 16)
+#define GET_MS1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00020000 ) >> 17)
+#define GET_MS2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00040000 ) >> 18)
+#define GET_MS3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00080000 ) >> 19)
+#define GET_BIST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00100000 ) >> 20)
+#define GET_I2C_MST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00800000 ) >> 23)
+#define GET_BTCX_CSR_CLK_EN (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_MCU_DBG_SEL (((REG32(ADR_MCU_DBG_SEL)) & 0x0000003f ) >> 0)
+#define GET_MCU_STOP_NOGRANT (((REG32(ADR_MCU_DBG_SEL)) & 0x00000100 ) >> 8)
+#define GET_MCU_STOP_ANYTIME (((REG32(ADR_MCU_DBG_SEL)) & 0x00000200 ) >> 9)
+#define GET_MCU_DBG_DATA (((REG32(ADR_MCU_DBG_DATA)) & 0xffffffff ) >> 0)
+#define GET_AHB_SW_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000001 ) >> 0)
+#define GET_AHB_ERR_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000002 ) >> 1)
+#define GET_REG_AHB_DEBUG_MX (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000030 ) >> 4)
+#define GET_REG_PKT_W_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000100 ) >> 8)
+#define GET_REG_PKT_R_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000200 ) >> 9)
+#define GET_IQ_SRAM_SEL_0 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00001000 ) >> 12)
+#define GET_IQ_SRAM_SEL_1 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00002000 ) >> 13)
+#define GET_IQ_SRAM_SEL_2 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00004000 ) >> 14)
+#define GET_AHB_STATUS (((REG32(ADR_AHB_BRG_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_PARALLEL_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000001 ) >> 0)
+#define GET_MBRUN (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000010 ) >> 4)
+#define GET_SHIFT_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000100 ) >> 8)
+#define GET_MODE_REG_SI (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000200 ) >> 9)
+#define GET_SIMULATION_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000400 ) >> 10)
+#define GET_DBIST_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000800 ) >> 11)
+#define GET_MODE_REG_IN (((REG32(ADR_BIST_MODE_REG_IN)) & 0x001fffff ) >> 0)
+#define GET_MODE_REG_OUT_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x001fffff ) >> 0)
+#define GET_MODE_REG_SO_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x80000000 ) >> 31)
+#define GET_MONITOR_BUS_MCU_31_0 (((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0xffffffff ) >> 0)
+#define GET_MONITOR_BUS_MCU_33_32 (((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0x00000003 ) >> 0)
+#define GET_TB_ADR_SEL (((REG32(ADR_TB_ADR_SEL)) & 0x0000ffff ) >> 0)
+#define GET_TB_CS (((REG32(ADR_TB_ADR_SEL)) & 0x80000000 ) >> 31)
+#define GET_TB_RDATA (((REG32(ADR_TB_RDATA)) & 0xffffffff ) >> 0)
+#define GET_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000001 ) >> 0)
+#define GET_DATA_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000010 ) >> 4)
+#define GET_AHB_ILL_ADDR (((REG32(ADR_AHB_ILL_ADDR)) & 0xffffffff ) >> 0)
+#define GET_AHB_FEN_ADDR (((REG32(ADR_AHB_FEN_ADDR)) & 0xffffffff ) >> 0)
+#define GET_ILL_ADDR_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000001 ) >> 0)
+#define GET_FENCE_HIT_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000002 ) >> 1)
+#define GET_ILL_ADDR_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000010 ) >> 4)
+#define GET_FENCE_HIT_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000020 ) >> 5)
+#define GET_PWM_INI_VALUE_P_A (((REG32(ADR_PWM_A)) & 0x000000ff ) >> 0)
+#define GET_PWM_INI_VALUE_N_A (((REG32(ADR_PWM_A)) & 0x0000ff00 ) >> 8)
+#define GET_PWM_POST_SCALER_A (((REG32(ADR_PWM_A)) & 0x000f0000 ) >> 16)
+#define GET_PWM_ALWAYSON_A (((REG32(ADR_PWM_A)) & 0x20000000 ) >> 29)
+#define GET_PWM_INVERT_A (((REG32(ADR_PWM_A)) & 0x40000000 ) >> 30)
+#define GET_PWM_ENABLE_A (((REG32(ADR_PWM_A)) & 0x80000000 ) >> 31)
+#define GET_PWM_INI_VALUE_P_B (((REG32(ADR_PWM_B)) & 0x000000ff ) >> 0)
+#define GET_PWM_INI_VALUE_N_B (((REG32(ADR_PWM_B)) & 0x0000ff00 ) >> 8)
+#define GET_PWM_POST_SCALER_B (((REG32(ADR_PWM_B)) & 0x000f0000 ) >> 16)
+#define GET_PWM_ALWAYSON_B (((REG32(ADR_PWM_B)) & 0x20000000 ) >> 29)
+#define GET_PWM_INVERT_B (((REG32(ADR_PWM_B)) & 0x40000000 ) >> 30)
+#define GET_PWM_ENABLE_B (((REG32(ADR_PWM_B)) & 0x80000000 ) >> 31)
+#define GET_HBUSREQ_LOCK (((REG32(ADR_HBUSREQ_LOCK)) & 0x00001fff ) >> 0)
+#define GET_HBURST_LOCK (((REG32(ADR_HBURST_LOCK)) & 0x00001fff ) >> 0)
+#define GET_PRESCALER_USTIMER (((REG32(ADR_PRESCALER_USTIMER)) & 0x000001ff ) >> 0)
+#define GET_MODE_REG_IN_MMU (((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0x0000ffff ) >> 0)
+#define GET_MODE_REG_OUT_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x0000ffff ) >> 0)
+#define GET_MODE_REG_SO_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x80000000 ) >> 31)
+#define GET_MONITOR_BUS_MMU (((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0x0007ffff ) >> 0)
+#define GET_TEST_MODE0 (((REG32(ADR_TEST_MODE)) & 0x00000001 ) >> 0)
+#define GET_TEST_MODE1 (((REG32(ADR_TEST_MODE)) & 0x00000002 ) >> 1)
+#define GET_TEST_MODE2 (((REG32(ADR_TEST_MODE)) & 0x00000004 ) >> 2)
+#define GET_TEST_MODE3 (((REG32(ADR_TEST_MODE)) & 0x00000008 ) >> 3)
+#define GET_TEST_MODE4 (((REG32(ADR_TEST_MODE)) & 0x00000010 ) >> 4)
+#define GET_TEST_MODE_ALL (((REG32(ADR_TEST_MODE)) & 0x00000020 ) >> 5)
+#define GET_WDT_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000001 ) >> 0)
+#define GET_SD_HOST_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000002 ) >> 1)
+#define GET_ALLOW_SD_RESET (((REG32(ADR_SD_INIT_CFG)) & 0x00000001 ) >> 0)
+#define GET_UART_NRTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000001 ) >> 0)
+#define GET_UART_NCTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000002 ) >> 1)
+#define GET_TU0_TM_INIT_VALUE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU0_TM_MODE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU0_TM_INT_STS_DONE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU0_TM_INT_MASK (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU0_TM_CUR_VALUE (((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU1_TM_INIT_VALUE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU1_TM_MODE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU1_TM_INT_STS_DONE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU1_TM_INT_MASK (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU1_TM_CUR_VALUE (((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU2_TM_INIT_VALUE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU2_TM_MODE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU2_TM_INT_STS_DONE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU2_TM_INT_MASK (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU2_TM_CUR_VALUE (((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU3_TM_INIT_VALUE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU3_TM_MODE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU3_TM_INT_STS_DONE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU3_TM_INT_MASK (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU3_TM_CUR_VALUE (((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM0_TM_INIT_VALUE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM0_TM_MODE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM0_TM_INT_STS_DONE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM0_TM_INT_MASK (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM0_TM_CUR_VALUE (((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM1_TM_INIT_VALUE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM1_TM_MODE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM1_TM_INT_STS_DONE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM1_TM_INT_MASK (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM1_TM_CUR_VALUE (((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM2_TM_INIT_VALUE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM2_TM_MODE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM2_TM_INT_STS_DONE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM2_TM_INT_MASK (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM2_TM_CUR_VALUE (((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM3_TM_INIT_VALUE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM3_TM_MODE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM3_TM_INT_STS_DONE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM3_TM_INT_MASK (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM3_TM_CUR_VALUE (((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_MCU_WDT_TIME_CNT (((REG32(ADR_MCU_WDOG_REG)) & 0x0000ffff ) >> 0)
+#define GET_MCU_WDT_STATUS (((REG32(ADR_MCU_WDOG_REG)) & 0x00020000 ) >> 17)
+#define GET_MCU_WDOG_ENA (((REG32(ADR_MCU_WDOG_REG)) & 0x80000000 ) >> 31)
+#define GET_SYS_WDT_TIME_CNT (((REG32(ADR_SYS_WDOG_REG)) & 0x0000ffff ) >> 0)
+#define GET_SYS_WDT_STATUS (((REG32(ADR_SYS_WDOG_REG)) & 0x00020000 ) >> 17)
+#define GET_SYS_WDOG_ENA (((REG32(ADR_SYS_WDOG_REG)) & 0x80000000 ) >> 31)
+#define GET_XLNA_EN_O_OE (((REG32(ADR_PAD6)) & 0x00000001 ) >> 0)
+#define GET_XLNA_EN_O_PE (((REG32(ADR_PAD6)) & 0x00000002 ) >> 1)
+#define GET_PAD6_IE (((REG32(ADR_PAD6)) & 0x00000008 ) >> 3)
+#define GET_PAD6_SEL_I (((REG32(ADR_PAD6)) & 0x00000030 ) >> 4)
+#define GET_PAD6_OD (((REG32(ADR_PAD6)) & 0x00000100 ) >> 8)
+#define GET_PAD6_SEL_O (((REG32(ADR_PAD6)) & 0x00001000 ) >> 12)
+#define GET_XLNA_EN_O_C (((REG32(ADR_PAD6)) & 0x10000000 ) >> 28)
+#define GET_WIFI_TX_SW_O_OE (((REG32(ADR_PAD7)) & 0x00000001 ) >> 0)
+#define GET_WIFI_TX_SW_O_PE (((REG32(ADR_PAD7)) & 0x00000002 ) >> 1)
+#define GET_PAD7_IE (((REG32(ADR_PAD7)) & 0x00000008 ) >> 3)
+#define GET_PAD7_SEL_I (((REG32(ADR_PAD7)) & 0x00000030 ) >> 4)
+#define GET_PAD7_OD (((REG32(ADR_PAD7)) & 0x00000100 ) >> 8)
+#define GET_PAD7_SEL_O (((REG32(ADR_PAD7)) & 0x00001000 ) >> 12)
+#define GET_WIFI_TX_SW_O_C (((REG32(ADR_PAD7)) & 0x10000000 ) >> 28)
+#define GET_WIFI_RX_SW_O_OE (((REG32(ADR_PAD8)) & 0x00000001 ) >> 0)
+#define GET_WIFI_RX_SW_O_PE (((REG32(ADR_PAD8)) & 0x00000002 ) >> 1)
+#define GET_PAD8_IE (((REG32(ADR_PAD8)) & 0x00000008 ) >> 3)
+#define GET_PAD8_SEL_I (((REG32(ADR_PAD8)) & 0x00000030 ) >> 4)
+#define GET_PAD8_OD (((REG32(ADR_PAD8)) & 0x00000100 ) >> 8)
+#define GET_WIFI_RX_SW_O_C (((REG32(ADR_PAD8)) & 0x10000000 ) >> 28)
+#define GET_BT_SW_O_OE (((REG32(ADR_PAD9)) & 0x00000001 ) >> 0)
+#define GET_BT_SW_O_PE (((REG32(ADR_PAD9)) & 0x00000002 ) >> 1)
+#define GET_PAD9_IE (((REG32(ADR_PAD9)) & 0x00000008 ) >> 3)
+#define GET_PAD9_SEL_I (((REG32(ADR_PAD9)) & 0x00000030 ) >> 4)
+#define GET_PAD9_OD (((REG32(ADR_PAD9)) & 0x00000100 ) >> 8)
+#define GET_PAD9_SEL_O (((REG32(ADR_PAD9)) & 0x00001000 ) >> 12)
+#define GET_BT_SW_O_C (((REG32(ADR_PAD9)) & 0x10000000 ) >> 28)
+#define GET_XPA_EN_O_OE (((REG32(ADR_PAD11)) & 0x00000001 ) >> 0)
+#define GET_XPA_EN_O_PE (((REG32(ADR_PAD11)) & 0x00000002 ) >> 1)
+#define GET_PAD11_IE (((REG32(ADR_PAD11)) & 0x00000008 ) >> 3)
+#define GET_PAD11_SEL_I (((REG32(ADR_PAD11)) & 0x00000030 ) >> 4)
+#define GET_PAD11_OD (((REG32(ADR_PAD11)) & 0x00000100 ) >> 8)
+#define GET_PAD11_SEL_O (((REG32(ADR_PAD11)) & 0x00001000 ) >> 12)
+#define GET_XPA_EN_O_C (((REG32(ADR_PAD11)) & 0x10000000 ) >> 28)
+#define GET_PAD15_OE (((REG32(ADR_PAD15)) & 0x00000001 ) >> 0)
+#define GET_PAD15_PE (((REG32(ADR_PAD15)) & 0x00000002 ) >> 1)
+#define GET_PAD15_DS (((REG32(ADR_PAD15)) & 0x00000004 ) >> 2)
+#define GET_PAD15_IE (((REG32(ADR_PAD15)) & 0x00000008 ) >> 3)
+#define GET_PAD15_SEL_I (((REG32(ADR_PAD15)) & 0x00000030 ) >> 4)
+#define GET_PAD15_OD (((REG32(ADR_PAD15)) & 0x00000100 ) >> 8)
+#define GET_PAD15_SEL_O (((REG32(ADR_PAD15)) & 0x00001000 ) >> 12)
+#define GET_TEST_1_ID (((REG32(ADR_PAD15)) & 0x10000000 ) >> 28)
+#define GET_PAD16_OE (((REG32(ADR_PAD16)) & 0x00000001 ) >> 0)
+#define GET_PAD16_PE (((REG32(ADR_PAD16)) & 0x00000002 ) >> 1)
+#define GET_PAD16_DS (((REG32(ADR_PAD16)) & 0x00000004 ) >> 2)
+#define GET_PAD16_IE (((REG32(ADR_PAD16)) & 0x00000008 ) >> 3)
+#define GET_PAD16_SEL_I (((REG32(ADR_PAD16)) & 0x00000030 ) >> 4)
+#define GET_PAD16_OD (((REG32(ADR_PAD16)) & 0x00000100 ) >> 8)
+#define GET_PAD16_SEL_O (((REG32(ADR_PAD16)) & 0x00001000 ) >> 12)
+#define GET_TEST_2_ID (((REG32(ADR_PAD16)) & 0x10000000 ) >> 28)
+#define GET_PAD17_OE (((REG32(ADR_PAD17)) & 0x00000001 ) >> 0)
+#define GET_PAD17_PE (((REG32(ADR_PAD17)) & 0x00000002 ) >> 1)
+#define GET_PAD17_DS (((REG32(ADR_PAD17)) & 0x00000004 ) >> 2)
+#define GET_PAD17_IE (((REG32(ADR_PAD17)) & 0x00000008 ) >> 3)
+#define GET_PAD17_SEL_I (((REG32(ADR_PAD17)) & 0x00000030 ) >> 4)
+#define GET_PAD17_OD (((REG32(ADR_PAD17)) & 0x00000100 ) >> 8)
+#define GET_PAD17_SEL_O (((REG32(ADR_PAD17)) & 0x00001000 ) >> 12)
+#define GET_TEST_3_ID (((REG32(ADR_PAD17)) & 0x10000000 ) >> 28)
+#define GET_PAD18_OE (((REG32(ADR_PAD18)) & 0x00000001 ) >> 0)
+#define GET_PAD18_PE (((REG32(ADR_PAD18)) & 0x00000002 ) >> 1)
+#define GET_PAD18_DS (((REG32(ADR_PAD18)) & 0x00000004 ) >> 2)
+#define GET_PAD18_IE (((REG32(ADR_PAD18)) & 0x00000008 ) >> 3)
+#define GET_PAD18_SEL_I (((REG32(ADR_PAD18)) & 0x00000030 ) >> 4)
+#define GET_PAD18_OD (((REG32(ADR_PAD18)) & 0x00000100 ) >> 8)
+#define GET_PAD18_SEL_O (((REG32(ADR_PAD18)) & 0x00003000 ) >> 12)
+#define GET_TEST_4_ID (((REG32(ADR_PAD18)) & 0x10000000 ) >> 28)
+#define GET_PAD19_OE (((REG32(ADR_PAD19)) & 0x00000001 ) >> 0)
+#define GET_PAD19_PE (((REG32(ADR_PAD19)) & 0x00000002 ) >> 1)
+#define GET_PAD19_DS (((REG32(ADR_PAD19)) & 0x00000004 ) >> 2)
+#define GET_PAD19_IE (((REG32(ADR_PAD19)) & 0x00000008 ) >> 3)
+#define GET_PAD19_SEL_I (((REG32(ADR_PAD19)) & 0x00000030 ) >> 4)
+#define GET_PAD19_OD (((REG32(ADR_PAD19)) & 0x00000100 ) >> 8)
+#define GET_PAD19_SEL_O (((REG32(ADR_PAD19)) & 0x00007000 ) >> 12)
+#define GET_SHORT_TO_20_ID (((REG32(ADR_PAD19)) & 0x10000000 ) >> 28)
+#define GET_PAD20_OE (((REG32(ADR_PAD20)) & 0x00000001 ) >> 0)
+#define GET_PAD20_PE (((REG32(ADR_PAD20)) & 0x00000002 ) >> 1)
+#define GET_PAD20_DS (((REG32(ADR_PAD20)) & 0x00000004 ) >> 2)
+#define GET_PAD20_IE (((REG32(ADR_PAD20)) & 0x00000008 ) >> 3)
+#define GET_PAD20_SEL_I (((REG32(ADR_PAD20)) & 0x000000f0 ) >> 4)
+#define GET_PAD20_OD (((REG32(ADR_PAD20)) & 0x00000100 ) >> 8)
+#define GET_PAD20_SEL_O (((REG32(ADR_PAD20)) & 0x00003000 ) >> 12)
+#define GET_STRAP0 (((REG32(ADR_PAD20)) & 0x08000000 ) >> 27)
+#define GET_GPIO_TEST_1_ID (((REG32(ADR_PAD20)) & 0x10000000 ) >> 28)
+#define GET_PAD21_OE (((REG32(ADR_PAD21)) & 0x00000001 ) >> 0)
+#define GET_PAD21_PE (((REG32(ADR_PAD21)) & 0x00000002 ) >> 1)
+#define GET_PAD21_DS (((REG32(ADR_PAD21)) & 0x00000004 ) >> 2)
+#define GET_PAD21_IE (((REG32(ADR_PAD21)) & 0x00000008 ) >> 3)
+#define GET_PAD21_SEL_I (((REG32(ADR_PAD21)) & 0x00000070 ) >> 4)
+#define GET_PAD21_OD (((REG32(ADR_PAD21)) & 0x00000100 ) >> 8)
+#define GET_PAD21_SEL_O (((REG32(ADR_PAD21)) & 0x00003000 ) >> 12)
+#define GET_STRAP3 (((REG32(ADR_PAD21)) & 0x08000000 ) >> 27)
+#define GET_GPIO_TEST_2_ID (((REG32(ADR_PAD21)) & 0x10000000 ) >> 28)
+#define GET_PAD22_OE (((REG32(ADR_PAD22)) & 0x00000001 ) >> 0)
+#define GET_PAD22_PE (((REG32(ADR_PAD22)) & 0x00000002 ) >> 1)
+#define GET_PAD22_DS (((REG32(ADR_PAD22)) & 0x00000004 ) >> 2)
+#define GET_PAD22_IE (((REG32(ADR_PAD22)) & 0x00000008 ) >> 3)
+#define GET_PAD22_SEL_I (((REG32(ADR_PAD22)) & 0x00000070 ) >> 4)
+#define GET_PAD22_OD (((REG32(ADR_PAD22)) & 0x00000100 ) >> 8)
+#define GET_PAD22_SEL_O (((REG32(ADR_PAD22)) & 0x00007000 ) >> 12)
+#define GET_PAD22_SEL_OE (((REG32(ADR_PAD22)) & 0x00100000 ) >> 20)
+#define GET_GPIO_TEST_3_ID (((REG32(ADR_PAD22)) & 0x10000000 ) >> 28)
+#define GET_PAD24_OE (((REG32(ADR_PAD24)) & 0x00000001 ) >> 0)
+#define GET_PAD24_PE (((REG32(ADR_PAD24)) & 0x00000002 ) >> 1)
+#define GET_PAD24_DS (((REG32(ADR_PAD24)) & 0x00000004 ) >> 2)
+#define GET_PAD24_IE (((REG32(ADR_PAD24)) & 0x00000008 ) >> 3)
+#define GET_PAD24_SEL_I (((REG32(ADR_PAD24)) & 0x00000030 ) >> 4)
+#define GET_PAD24_OD (((REG32(ADR_PAD24)) & 0x00000100 ) >> 8)
+#define GET_PAD24_SEL_O (((REG32(ADR_PAD24)) & 0x00007000 ) >> 12)
+#define GET_GPIO_TEST_4_ID (((REG32(ADR_PAD24)) & 0x10000000 ) >> 28)
+#define GET_PAD25_OE (((REG32(ADR_PAD25)) & 0x00000001 ) >> 0)
+#define GET_PAD25_PE (((REG32(ADR_PAD25)) & 0x00000002 ) >> 1)
+#define GET_PAD25_DS (((REG32(ADR_PAD25)) & 0x00000004 ) >> 2)
+#define GET_PAD25_IE (((REG32(ADR_PAD25)) & 0x00000008 ) >> 3)
+#define GET_PAD25_SEL_I (((REG32(ADR_PAD25)) & 0x00000070 ) >> 4)
+#define GET_PAD25_OD (((REG32(ADR_PAD25)) & 0x00000100 ) >> 8)
+#define GET_PAD25_SEL_O (((REG32(ADR_PAD25)) & 0x00007000 ) >> 12)
+#define GET_PAD25_SEL_OE (((REG32(ADR_PAD25)) & 0x00100000 ) >> 20)
+#define GET_STRAP1 (((REG32(ADR_PAD25)) & 0x08000000 ) >> 27)
+#define GET_GPIO_1_ID (((REG32(ADR_PAD25)) & 0x10000000 ) >> 28)
+#define GET_PAD27_OE (((REG32(ADR_PAD27)) & 0x00000001 ) >> 0)
+#define GET_PAD27_PE (((REG32(ADR_PAD27)) & 0x00000002 ) >> 1)
+#define GET_PAD27_DS (((REG32(ADR_PAD27)) & 0x00000004 ) >> 2)
+#define GET_PAD27_IE (((REG32(ADR_PAD27)) & 0x00000008 ) >> 3)
+#define GET_PAD27_SEL_I (((REG32(ADR_PAD27)) & 0x00000070 ) >> 4)
+#define GET_PAD27_OD (((REG32(ADR_PAD27)) & 0x00000100 ) >> 8)
+#define GET_PAD27_SEL_O (((REG32(ADR_PAD27)) & 0x00007000 ) >> 12)
+#define GET_GPIO_2_ID (((REG32(ADR_PAD27)) & 0x10000000 ) >> 28)
+#define GET_PAD28_OE (((REG32(ADR_PAD28)) & 0x00000001 ) >> 0)
+#define GET_PAD28_PE (((REG32(ADR_PAD28)) & 0x00000002 ) >> 1)
+#define GET_PAD28_DS (((REG32(ADR_PAD28)) & 0x00000004 ) >> 2)
+#define GET_PAD28_IE (((REG32(ADR_PAD28)) & 0x00000008 ) >> 3)
+#define GET_PAD28_SEL_I (((REG32(ADR_PAD28)) & 0x00000070 ) >> 4)
+#define GET_PAD28_OD (((REG32(ADR_PAD28)) & 0x00000100 ) >> 8)
+#define GET_PAD28_SEL_O (((REG32(ADR_PAD28)) & 0x0000f000 ) >> 12)
+#define GET_PAD28_SEL_OE (((REG32(ADR_PAD28)) & 0x00100000 ) >> 20)
+#define GET_GPIO_3_ID (((REG32(ADR_PAD28)) & 0x10000000 ) >> 28)
+#define GET_PAD29_OE (((REG32(ADR_PAD29)) & 0x00000001 ) >> 0)
+#define GET_PAD29_PE (((REG32(ADR_PAD29)) & 0x00000002 ) >> 1)
+#define GET_PAD29_DS (((REG32(ADR_PAD29)) & 0x00000004 ) >> 2)
+#define GET_PAD29_IE (((REG32(ADR_PAD29)) & 0x00000008 ) >> 3)
+#define GET_PAD29_SEL_I (((REG32(ADR_PAD29)) & 0x00000070 ) >> 4)
+#define GET_PAD29_OD (((REG32(ADR_PAD29)) & 0x00000100 ) >> 8)
+#define GET_PAD29_SEL_O (((REG32(ADR_PAD29)) & 0x00007000 ) >> 12)
+#define GET_GPIO_TEST_5_ID (((REG32(ADR_PAD29)) & 0x10000000 ) >> 28)
+#define GET_PAD30_OE (((REG32(ADR_PAD30)) & 0x00000001 ) >> 0)
+#define GET_PAD30_PE (((REG32(ADR_PAD30)) & 0x00000002 ) >> 1)
+#define GET_PAD30_DS (((REG32(ADR_PAD30)) & 0x00000004 ) >> 2)
+#define GET_PAD30_IE (((REG32(ADR_PAD30)) & 0x00000008 ) >> 3)
+#define GET_PAD30_SEL_I (((REG32(ADR_PAD30)) & 0x00000030 ) >> 4)
+#define GET_PAD30_OD (((REG32(ADR_PAD30)) & 0x00000100 ) >> 8)
+#define GET_PAD30_SEL_O (((REG32(ADR_PAD30)) & 0x00003000 ) >> 12)
+#define GET_TEST_6_ID (((REG32(ADR_PAD30)) & 0x10000000 ) >> 28)
+#define GET_PAD31_OE (((REG32(ADR_PAD31)) & 0x00000001 ) >> 0)
+#define GET_PAD31_PE (((REG32(ADR_PAD31)) & 0x00000002 ) >> 1)
+#define GET_PAD31_DS (((REG32(ADR_PAD31)) & 0x00000004 ) >> 2)
+#define GET_PAD31_IE (((REG32(ADR_PAD31)) & 0x00000008 ) >> 3)
+#define GET_PAD31_SEL_I (((REG32(ADR_PAD31)) & 0x00000030 ) >> 4)
+#define GET_PAD31_OD (((REG32(ADR_PAD31)) & 0x00000100 ) >> 8)
+#define GET_PAD31_SEL_O (((REG32(ADR_PAD31)) & 0x00003000 ) >> 12)
+#define GET_TEST_7_ID (((REG32(ADR_PAD31)) & 0x10000000 ) >> 28)
+#define GET_PAD32_OE (((REG32(ADR_PAD32)) & 0x00000001 ) >> 0)
+#define GET_PAD32_PE (((REG32(ADR_PAD32)) & 0x00000002 ) >> 1)
+#define GET_PAD32_DS (((REG32(ADR_PAD32)) & 0x00000004 ) >> 2)
+#define GET_PAD32_IE (((REG32(ADR_PAD32)) & 0x00000008 ) >> 3)
+#define GET_PAD32_SEL_I (((REG32(ADR_PAD32)) & 0x00000030 ) >> 4)
+#define GET_PAD32_OD (((REG32(ADR_PAD32)) & 0x00000100 ) >> 8)
+#define GET_PAD32_SEL_O (((REG32(ADR_PAD32)) & 0x00003000 ) >> 12)
+#define GET_TEST_8_ID (((REG32(ADR_PAD32)) & 0x10000000 ) >> 28)
+#define GET_PAD33_OE (((REG32(ADR_PAD33)) & 0x00000001 ) >> 0)
+#define GET_PAD33_PE (((REG32(ADR_PAD33)) & 0x00000002 ) >> 1)
+#define GET_PAD33_DS (((REG32(ADR_PAD33)) & 0x00000004 ) >> 2)
+#define GET_PAD33_IE (((REG32(ADR_PAD33)) & 0x00000008 ) >> 3)
+#define GET_PAD33_SEL_I (((REG32(ADR_PAD33)) & 0x00000030 ) >> 4)
+#define GET_PAD33_OD (((REG32(ADR_PAD33)) & 0x00000100 ) >> 8)
+#define GET_PAD33_SEL_O (((REG32(ADR_PAD33)) & 0x00003000 ) >> 12)
+#define GET_TEST_9_ID (((REG32(ADR_PAD33)) & 0x10000000 ) >> 28)
+#define GET_PAD34_OE (((REG32(ADR_PAD34)) & 0x00000001 ) >> 0)
+#define GET_PAD34_PE (((REG32(ADR_PAD34)) & 0x00000002 ) >> 1)
+#define GET_PAD34_DS (((REG32(ADR_PAD34)) & 0x00000004 ) >> 2)
+#define GET_PAD34_IE (((REG32(ADR_PAD34)) & 0x00000008 ) >> 3)
+#define GET_PAD34_SEL_I (((REG32(ADR_PAD34)) & 0x00000030 ) >> 4)
+#define GET_PAD34_OD (((REG32(ADR_PAD34)) & 0x00000100 ) >> 8)
+#define GET_PAD34_SEL_O (((REG32(ADR_PAD34)) & 0x00003000 ) >> 12)
+#define GET_TEST_10_ID (((REG32(ADR_PAD34)) & 0x10000000 ) >> 28)
+#define GET_PAD42_OE (((REG32(ADR_PAD42)) & 0x00000001 ) >> 0)
+#define GET_PAD42_PE (((REG32(ADR_PAD42)) & 0x00000002 ) >> 1)
+#define GET_PAD42_DS (((REG32(ADR_PAD42)) & 0x00000004 ) >> 2)
+#define GET_PAD42_IE (((REG32(ADR_PAD42)) & 0x00000008 ) >> 3)
+#define GET_PAD42_SEL_I (((REG32(ADR_PAD42)) & 0x00000030 ) >> 4)
+#define GET_PAD42_OD (((REG32(ADR_PAD42)) & 0x00000100 ) >> 8)
+#define GET_PAD42_SEL_O (((REG32(ADR_PAD42)) & 0x00001000 ) >> 12)
+#define GET_TEST_11_ID (((REG32(ADR_PAD42)) & 0x10000000 ) >> 28)
+#define GET_PAD43_OE (((REG32(ADR_PAD43)) & 0x00000001 ) >> 0)
+#define GET_PAD43_PE (((REG32(ADR_PAD43)) & 0x00000002 ) >> 1)
+#define GET_PAD43_DS (((REG32(ADR_PAD43)) & 0x00000004 ) >> 2)
+#define GET_PAD43_IE (((REG32(ADR_PAD43)) & 0x00000008 ) >> 3)
+#define GET_PAD43_SEL_I (((REG32(ADR_PAD43)) & 0x00000030 ) >> 4)
+#define GET_PAD43_OD (((REG32(ADR_PAD43)) & 0x00000100 ) >> 8)
+#define GET_PAD43_SEL_O (((REG32(ADR_PAD43)) & 0x00001000 ) >> 12)
+#define GET_TEST_12_ID (((REG32(ADR_PAD43)) & 0x10000000 ) >> 28)
+#define GET_PAD44_OE (((REG32(ADR_PAD44)) & 0x00000001 ) >> 0)
+#define GET_PAD44_PE (((REG32(ADR_PAD44)) & 0x00000002 ) >> 1)
+#define GET_PAD44_DS (((REG32(ADR_PAD44)) & 0x00000004 ) >> 2)
+#define GET_PAD44_IE (((REG32(ADR_PAD44)) & 0x00000008 ) >> 3)
+#define GET_PAD44_SEL_I (((REG32(ADR_PAD44)) & 0x00000030 ) >> 4)
+#define GET_PAD44_OD (((REG32(ADR_PAD44)) & 0x00000100 ) >> 8)
+#define GET_PAD44_SEL_O (((REG32(ADR_PAD44)) & 0x00003000 ) >> 12)
+#define GET_TEST_13_ID (((REG32(ADR_PAD44)) & 0x10000000 ) >> 28)
+#define GET_PAD45_OE (((REG32(ADR_PAD45)) & 0x00000001 ) >> 0)
+#define GET_PAD45_PE (((REG32(ADR_PAD45)) & 0x00000002 ) >> 1)
+#define GET_PAD45_DS (((REG32(ADR_PAD45)) & 0x00000004 ) >> 2)
+#define GET_PAD45_IE (((REG32(ADR_PAD45)) & 0x00000008 ) >> 3)
+#define GET_PAD45_SEL_I (((REG32(ADR_PAD45)) & 0x00000030 ) >> 4)
+#define GET_PAD45_OD (((REG32(ADR_PAD45)) & 0x00000100 ) >> 8)
+#define GET_PAD45_SEL_O (((REG32(ADR_PAD45)) & 0x00003000 ) >> 12)
+#define GET_TEST_14_ID (((REG32(ADR_PAD45)) & 0x10000000 ) >> 28)
+#define GET_PAD46_OE (((REG32(ADR_PAD46)) & 0x00000001 ) >> 0)
+#define GET_PAD46_PE (((REG32(ADR_PAD46)) & 0x00000002 ) >> 1)
+#define GET_PAD46_DS (((REG32(ADR_PAD46)) & 0x00000004 ) >> 2)
+#define GET_PAD46_IE (((REG32(ADR_PAD46)) & 0x00000008 ) >> 3)
+#define GET_PAD46_SEL_I (((REG32(ADR_PAD46)) & 0x00000030 ) >> 4)
+#define GET_PAD46_OD (((REG32(ADR_PAD46)) & 0x00000100 ) >> 8)
+#define GET_PAD46_SEL_O (((REG32(ADR_PAD46)) & 0x00003000 ) >> 12)
+#define GET_TEST_15_ID (((REG32(ADR_PAD46)) & 0x10000000 ) >> 28)
+#define GET_PAD47_OE (((REG32(ADR_PAD47)) & 0x00000001 ) >> 0)
+#define GET_PAD47_PE (((REG32(ADR_PAD47)) & 0x00000002 ) >> 1)
+#define GET_PAD47_DS (((REG32(ADR_PAD47)) & 0x00000004 ) >> 2)
+#define GET_PAD47_SEL_I (((REG32(ADR_PAD47)) & 0x00000030 ) >> 4)
+#define GET_PAD47_OD (((REG32(ADR_PAD47)) & 0x00000100 ) >> 8)
+#define GET_PAD47_SEL_O (((REG32(ADR_PAD47)) & 0x00003000 ) >> 12)
+#define GET_PAD47_SEL_OE (((REG32(ADR_PAD47)) & 0x00100000 ) >> 20)
+#define GET_GPIO_9_ID (((REG32(ADR_PAD47)) & 0x10000000 ) >> 28)
+#define GET_PAD48_OE (((REG32(ADR_PAD48)) & 0x00000001 ) >> 0)
+#define GET_PAD48_PE (((REG32(ADR_PAD48)) & 0x00000002 ) >> 1)
+#define GET_PAD48_DS (((REG32(ADR_PAD48)) & 0x00000004 ) >> 2)
+#define GET_PAD48_IE (((REG32(ADR_PAD48)) & 0x00000008 ) >> 3)
+#define GET_PAD48_SEL_I (((REG32(ADR_PAD48)) & 0x00000070 ) >> 4)
+#define GET_PAD48_OD (((REG32(ADR_PAD48)) & 0x00000100 ) >> 8)
+#define GET_PAD48_PE_SEL (((REG32(ADR_PAD48)) & 0x00000800 ) >> 11)
+#define GET_PAD48_SEL_O (((REG32(ADR_PAD48)) & 0x00003000 ) >> 12)
+#define GET_PAD48_SEL_OE (((REG32(ADR_PAD48)) & 0x00100000 ) >> 20)
+#define GET_GPIO_10_ID (((REG32(ADR_PAD48)) & 0x10000000 ) >> 28)
+#define GET_PAD49_OE (((REG32(ADR_PAD49)) & 0x00000001 ) >> 0)
+#define GET_PAD49_PE (((REG32(ADR_PAD49)) & 0x00000002 ) >> 1)
+#define GET_PAD49_DS (((REG32(ADR_PAD49)) & 0x00000004 ) >> 2)
+#define GET_PAD49_IE (((REG32(ADR_PAD49)) & 0x00000008 ) >> 3)
+#define GET_PAD49_SEL_I (((REG32(ADR_PAD49)) & 0x00000070 ) >> 4)
+#define GET_PAD49_OD (((REG32(ADR_PAD49)) & 0x00000100 ) >> 8)
+#define GET_PAD49_SEL_O (((REG32(ADR_PAD49)) & 0x00003000 ) >> 12)
+#define GET_PAD49_SEL_OE (((REG32(ADR_PAD49)) & 0x00100000 ) >> 20)
+#define GET_GPIO_11_ID (((REG32(ADR_PAD49)) & 0x10000000 ) >> 28)
+#define GET_PAD50_OE (((REG32(ADR_PAD50)) & 0x00000001 ) >> 0)
+#define GET_PAD50_PE (((REG32(ADR_PAD50)) & 0x00000002 ) >> 1)
+#define GET_PAD50_DS (((REG32(ADR_PAD50)) & 0x00000004 ) >> 2)
+#define GET_PAD50_IE (((REG32(ADR_PAD50)) & 0x00000008 ) >> 3)
+#define GET_PAD50_SEL_I (((REG32(ADR_PAD50)) & 0x00000070 ) >> 4)
+#define GET_PAD50_OD (((REG32(ADR_PAD50)) & 0x00000100 ) >> 8)
+#define GET_PAD50_SEL_O (((REG32(ADR_PAD50)) & 0x00003000 ) >> 12)
+#define GET_PAD50_SEL_OE (((REG32(ADR_PAD50)) & 0x00100000 ) >> 20)
+#define GET_GPIO_12_ID (((REG32(ADR_PAD50)) & 0x10000000 ) >> 28)
+#define GET_PAD51_OE (((REG32(ADR_PAD51)) & 0x00000001 ) >> 0)
+#define GET_PAD51_PE (((REG32(ADR_PAD51)) & 0x00000002 ) >> 1)
+#define GET_PAD51_DS (((REG32(ADR_PAD51)) & 0x00000004 ) >> 2)
+#define GET_PAD51_IE (((REG32(ADR_PAD51)) & 0x00000008 ) >> 3)
+#define GET_PAD51_SEL_I (((REG32(ADR_PAD51)) & 0x00000030 ) >> 4)
+#define GET_PAD51_OD (((REG32(ADR_PAD51)) & 0x00000100 ) >> 8)
+#define GET_PAD51_SEL_O (((REG32(ADR_PAD51)) & 0x00001000 ) >> 12)
+#define GET_PAD51_SEL_OE (((REG32(ADR_PAD51)) & 0x00100000 ) >> 20)
+#define GET_GPIO_13_ID (((REG32(ADR_PAD51)) & 0x10000000 ) >> 28)
+#define GET_PAD52_OE (((REG32(ADR_PAD52)) & 0x00000001 ) >> 0)
+#define GET_PAD52_PE (((REG32(ADR_PAD52)) & 0x00000002 ) >> 1)
+#define GET_PAD52_DS (((REG32(ADR_PAD52)) & 0x00000004 ) >> 2)
+#define GET_PAD52_SEL_I (((REG32(ADR_PAD52)) & 0x00000030 ) >> 4)
+#define GET_PAD52_OD (((REG32(ADR_PAD52)) & 0x00000100 ) >> 8)
+#define GET_PAD52_SEL_O (((REG32(ADR_PAD52)) & 0x00001000 ) >> 12)
+#define GET_PAD52_SEL_OE (((REG32(ADR_PAD52)) & 0x00100000 ) >> 20)
+#define GET_GPIO_14_ID (((REG32(ADR_PAD52)) & 0x10000000 ) >> 28)
+#define GET_PAD53_OE (((REG32(ADR_PAD53)) & 0x00000001 ) >> 0)
+#define GET_PAD53_PE (((REG32(ADR_PAD53)) & 0x00000002 ) >> 1)
+#define GET_PAD53_DS (((REG32(ADR_PAD53)) & 0x00000004 ) >> 2)
+#define GET_PAD53_IE (((REG32(ADR_PAD53)) & 0x00000008 ) >> 3)
+#define GET_PAD53_SEL_I (((REG32(ADR_PAD53)) & 0x00000030 ) >> 4)
+#define GET_PAD53_OD (((REG32(ADR_PAD53)) & 0x00000100 ) >> 8)
+#define GET_PAD53_SEL_O (((REG32(ADR_PAD53)) & 0x00001000 ) >> 12)
+#define GET_JTAG_TMS_ID (((REG32(ADR_PAD53)) & 0x10000000 ) >> 28)
+#define GET_PAD54_OE (((REG32(ADR_PAD54)) & 0x00000001 ) >> 0)
+#define GET_PAD54_PE (((REG32(ADR_PAD54)) & 0x00000002 ) >> 1)
+#define GET_PAD54_DS (((REG32(ADR_PAD54)) & 0x00000004 ) >> 2)
+#define GET_PAD54_OD (((REG32(ADR_PAD54)) & 0x00000100 ) >> 8)
+#define GET_PAD54_SEL_O (((REG32(ADR_PAD54)) & 0x00003000 ) >> 12)
+#define GET_JTAG_TCK_ID (((REG32(ADR_PAD54)) & 0x10000000 ) >> 28)
+#define GET_PAD56_PE (((REG32(ADR_PAD56)) & 0x00000002 ) >> 1)
+#define GET_PAD56_DS (((REG32(ADR_PAD56)) & 0x00000004 ) >> 2)
+#define GET_PAD56_SEL_I (((REG32(ADR_PAD56)) & 0x00000010 ) >> 4)
+#define GET_PAD56_OD (((REG32(ADR_PAD56)) & 0x00000100 ) >> 8)
+#define GET_JTAG_TDI_ID (((REG32(ADR_PAD56)) & 0x10000000 ) >> 28)
+#define GET_PAD57_OE (((REG32(ADR_PAD57)) & 0x00000001 ) >> 0)
+#define GET_PAD57_PE (((REG32(ADR_PAD57)) & 0x00000002 ) >> 1)
+#define GET_PAD57_DS (((REG32(ADR_PAD57)) & 0x00000004 ) >> 2)
+#define GET_PAD57_IE (((REG32(ADR_PAD57)) & 0x00000008 ) >> 3)
+#define GET_PAD57_SEL_I (((REG32(ADR_PAD57)) & 0x00000030 ) >> 4)
+#define GET_PAD57_OD (((REG32(ADR_PAD57)) & 0x00000100 ) >> 8)
+#define GET_PAD57_SEL_O (((REG32(ADR_PAD57)) & 0x00003000 ) >> 12)
+#define GET_PAD57_SEL_OE (((REG32(ADR_PAD57)) & 0x00100000 ) >> 20)
+#define GET_JTAG_TDO_ID (((REG32(ADR_PAD57)) & 0x10000000 ) >> 28)
+#define GET_PAD58_OE (((REG32(ADR_PAD58)) & 0x00000001 ) >> 0)
+#define GET_PAD58_PE (((REG32(ADR_PAD58)) & 0x00000002 ) >> 1)
+#define GET_PAD58_DS (((REG32(ADR_PAD58)) & 0x00000004 ) >> 2)
+#define GET_PAD58_IE (((REG32(ADR_PAD58)) & 0x00000008 ) >> 3)
+#define GET_PAD58_SEL_I (((REG32(ADR_PAD58)) & 0x00000030 ) >> 4)
+#define GET_PAD58_OD (((REG32(ADR_PAD58)) & 0x00000100 ) >> 8)
+#define GET_PAD58_SEL_O (((REG32(ADR_PAD58)) & 0x00001000 ) >> 12)
+#define GET_TEST_16_ID (((REG32(ADR_PAD58)) & 0x10000000 ) >> 28)
+#define GET_PAD59_OE (((REG32(ADR_PAD59)) & 0x00000001 ) >> 0)
+#define GET_PAD59_PE (((REG32(ADR_PAD59)) & 0x00000002 ) >> 1)
+#define GET_PAD59_DS (((REG32(ADR_PAD59)) & 0x00000004 ) >> 2)
+#define GET_PAD59_IE (((REG32(ADR_PAD59)) & 0x00000008 ) >> 3)
+#define GET_PAD59_SEL_I (((REG32(ADR_PAD59)) & 0x00000030 ) >> 4)
+#define GET_PAD59_OD (((REG32(ADR_PAD59)) & 0x00000100 ) >> 8)
+#define GET_PAD59_SEL_O (((REG32(ADR_PAD59)) & 0x00001000 ) >> 12)
+#define GET_TEST_17_ID (((REG32(ADR_PAD59)) & 0x10000000 ) >> 28)
+#define GET_PAD60_OE (((REG32(ADR_PAD60)) & 0x00000001 ) >> 0)
+#define GET_PAD60_PE (((REG32(ADR_PAD60)) & 0x00000002 ) >> 1)
+#define GET_PAD60_DS (((REG32(ADR_PAD60)) & 0x00000004 ) >> 2)
+#define GET_PAD60_IE (((REG32(ADR_PAD60)) & 0x00000008 ) >> 3)
+#define GET_PAD60_SEL_I (((REG32(ADR_PAD60)) & 0x00000030 ) >> 4)
+#define GET_PAD60_OD (((REG32(ADR_PAD60)) & 0x00000100 ) >> 8)
+#define GET_PAD60_SEL_O (((REG32(ADR_PAD60)) & 0x00001000 ) >> 12)
+#define GET_TEST_18_ID (((REG32(ADR_PAD60)) & 0x10000000 ) >> 28)
+#define GET_PAD61_OE (((REG32(ADR_PAD61)) & 0x00000001 ) >> 0)
+#define GET_PAD61_PE (((REG32(ADR_PAD61)) & 0x00000002 ) >> 1)
+#define GET_PAD61_DS (((REG32(ADR_PAD61)) & 0x00000004 ) >> 2)
+#define GET_PAD61_IE (((REG32(ADR_PAD61)) & 0x00000008 ) >> 3)
+#define GET_PAD61_SEL_I (((REG32(ADR_PAD61)) & 0x00000010 ) >> 4)
+#define GET_PAD61_OD (((REG32(ADR_PAD61)) & 0x00000100 ) >> 8)
+#define GET_PAD61_SEL_O (((REG32(ADR_PAD61)) & 0x00003000 ) >> 12)
+#define GET_TEST_19_ID (((REG32(ADR_PAD61)) & 0x10000000 ) >> 28)
+#define GET_PAD62_OE (((REG32(ADR_PAD62)) & 0x00000001 ) >> 0)
+#define GET_PAD62_PE (((REG32(ADR_PAD62)) & 0x00000002 ) >> 1)
+#define GET_PAD62_DS (((REG32(ADR_PAD62)) & 0x00000004 ) >> 2)
+#define GET_PAD62_IE (((REG32(ADR_PAD62)) & 0x00000008 ) >> 3)
+#define GET_PAD62_SEL_I (((REG32(ADR_PAD62)) & 0x00000010 ) >> 4)
+#define GET_PAD62_OD (((REG32(ADR_PAD62)) & 0x00000100 ) >> 8)
+#define GET_PAD62_SEL_O (((REG32(ADR_PAD62)) & 0x00001000 ) >> 12)
+#define GET_TEST_20_ID (((REG32(ADR_PAD62)) & 0x10000000 ) >> 28)
+#define GET_PAD64_OE (((REG32(ADR_PAD64)) & 0x00000001 ) >> 0)
+#define GET_PAD64_PE (((REG32(ADR_PAD64)) & 0x00000002 ) >> 1)
+#define GET_PAD64_DS (((REG32(ADR_PAD64)) & 0x00000004 ) >> 2)
+#define GET_PAD64_IE (((REG32(ADR_PAD64)) & 0x00000008 ) >> 3)
+#define GET_PAD64_SEL_I (((REG32(ADR_PAD64)) & 0x00000070 ) >> 4)
+#define GET_PAD64_OD (((REG32(ADR_PAD64)) & 0x00000100 ) >> 8)
+#define GET_PAD64_SEL_O (((REG32(ADR_PAD64)) & 0x00003000 ) >> 12)
+#define GET_PAD64_SEL_OE (((REG32(ADR_PAD64)) & 0x00100000 ) >> 20)
+#define GET_GPIO_15_IP_ID (((REG32(ADR_PAD64)) & 0x10000000 ) >> 28)
+#define GET_PAD65_OE (((REG32(ADR_PAD65)) & 0x00000001 ) >> 0)
+#define GET_PAD65_PE (((REG32(ADR_PAD65)) & 0x00000002 ) >> 1)
+#define GET_PAD65_DS (((REG32(ADR_PAD65)) & 0x00000004 ) >> 2)
+#define GET_PAD65_IE (((REG32(ADR_PAD65)) & 0x00000008 ) >> 3)
+#define GET_PAD65_SEL_I (((REG32(ADR_PAD65)) & 0x00000070 ) >> 4)
+#define GET_PAD65_OD (((REG32(ADR_PAD65)) & 0x00000100 ) >> 8)
+#define GET_PAD65_SEL_O (((REG32(ADR_PAD65)) & 0x00001000 ) >> 12)
+#define GET_GPIO_TEST_7_IN_ID (((REG32(ADR_PAD65)) & 0x10000000 ) >> 28)
+#define GET_PAD66_OE (((REG32(ADR_PAD66)) & 0x00000001 ) >> 0)
+#define GET_PAD66_PE (((REG32(ADR_PAD66)) & 0x00000002 ) >> 1)
+#define GET_PAD66_DS (((REG32(ADR_PAD66)) & 0x00000004 ) >> 2)
+#define GET_PAD66_IE (((REG32(ADR_PAD66)) & 0x00000008 ) >> 3)
+#define GET_PAD66_SEL_I (((REG32(ADR_PAD66)) & 0x00000030 ) >> 4)
+#define GET_PAD66_OD (((REG32(ADR_PAD66)) & 0x00000100 ) >> 8)
+#define GET_PAD66_SEL_O (((REG32(ADR_PAD66)) & 0x00003000 ) >> 12)
+#define GET_GPIO_17_QP_ID (((REG32(ADR_PAD66)) & 0x10000000 ) >> 28)
+#define GET_PAD68_OE (((REG32(ADR_PAD68)) & 0x00000001 ) >> 0)
+#define GET_PAD68_PE (((REG32(ADR_PAD68)) & 0x00000002 ) >> 1)
+#define GET_PAD68_DS (((REG32(ADR_PAD68)) & 0x00000004 ) >> 2)
+#define GET_PAD68_IE (((REG32(ADR_PAD68)) & 0x00000008 ) >> 3)
+#define GET_PAD68_OD (((REG32(ADR_PAD68)) & 0x00000100 ) >> 8)
+#define GET_PAD68_SEL_O (((REG32(ADR_PAD68)) & 0x00001000 ) >> 12)
+#define GET_GPIO_19_ID (((REG32(ADR_PAD68)) & 0x10000000 ) >> 28)
+#define GET_PAD67_OE (((REG32(ADR_PAD67)) & 0x00000001 ) >> 0)
+#define GET_PAD67_PE (((REG32(ADR_PAD67)) & 0x00000002 ) >> 1)
+#define GET_PAD67_DS (((REG32(ADR_PAD67)) & 0x00000004 ) >> 2)
+#define GET_PAD67_IE (((REG32(ADR_PAD67)) & 0x00000008 ) >> 3)
+#define GET_PAD67_SEL_I (((REG32(ADR_PAD67)) & 0x00000070 ) >> 4)
+#define GET_PAD67_OD (((REG32(ADR_PAD67)) & 0x00000100 ) >> 8)
+#define GET_PAD67_SEL_O (((REG32(ADR_PAD67)) & 0x00003000 ) >> 12)
+#define GET_GPIO_TEST_8_QN_ID (((REG32(ADR_PAD67)) & 0x10000000 ) >> 28)
+#define GET_PAD69_OE (((REG32(ADR_PAD69)) & 0x00000001 ) >> 0)
+#define GET_PAD69_PE (((REG32(ADR_PAD69)) & 0x00000002 ) >> 1)
+#define GET_PAD69_DS (((REG32(ADR_PAD69)) & 0x00000004 ) >> 2)
+#define GET_PAD69_IE (((REG32(ADR_PAD69)) & 0x00000008 ) >> 3)
+#define GET_PAD69_SEL_I (((REG32(ADR_PAD69)) & 0x00000030 ) >> 4)
+#define GET_PAD69_OD (((REG32(ADR_PAD69)) & 0x00000100 ) >> 8)
+#define GET_PAD69_SEL_O (((REG32(ADR_PAD69)) & 0x00001000 ) >> 12)
+#define GET_STRAP2 (((REG32(ADR_PAD69)) & 0x08000000 ) >> 27)
+#define GET_GPIO_20_ID (((REG32(ADR_PAD69)) & 0x10000000 ) >> 28)
+#define GET_PAD70_OE (((REG32(ADR_PAD70)) & 0x00000001 ) >> 0)
+#define GET_PAD70_PE (((REG32(ADR_PAD70)) & 0x00000002 ) >> 1)
+#define GET_PAD70_DS (((REG32(ADR_PAD70)) & 0x00000004 ) >> 2)
+#define GET_PAD70_IE (((REG32(ADR_PAD70)) & 0x00000008 ) >> 3)
+#define GET_PAD70_SEL_I (((REG32(ADR_PAD70)) & 0x00000030 ) >> 4)
+#define GET_PAD70_OD (((REG32(ADR_PAD70)) & 0x00000100 ) >> 8)
+#define GET_PAD70_SEL_O (((REG32(ADR_PAD70)) & 0x00007000 ) >> 12)
+#define GET_GPIO_21_ID (((REG32(ADR_PAD70)) & 0x10000000 ) >> 28)
+#define GET_PAD231_OE (((REG32(ADR_PAD231)) & 0x00000001 ) >> 0)
+#define GET_PAD231_PE (((REG32(ADR_PAD231)) & 0x00000002 ) >> 1)
+#define GET_PAD231_DS (((REG32(ADR_PAD231)) & 0x00000004 ) >> 2)
+#define GET_PAD231_IE (((REG32(ADR_PAD231)) & 0x00000008 ) >> 3)
+#define GET_PAD231_OD (((REG32(ADR_PAD231)) & 0x00000100 ) >> 8)
+#define GET_PIN_40_OR_56_ID (((REG32(ADR_PAD231)) & 0x10000000 ) >> 28)
+#define GET_MP_PHY2RX_DATA__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000001 ) >> 0)
+#define GET_MP_PHY2RX_DATA__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000002 ) >> 1)
+#define GET_MP_TX_FF_RPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000004 ) >> 2)
+#define GET_MP_RX_FF_WPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000008 ) >> 3)
+#define GET_MP_RX_FF_WPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000010 ) >> 4)
+#define GET_MP_RX_FF_WPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000020 ) >> 5)
+#define GET_MP_PHY2RX_DATA__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000040 ) >> 6)
+#define GET_MP_PHY2RX_DATA__4_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000080 ) >> 7)
+#define GET_I2CM_SDA_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000300 ) >> 8)
+#define GET_CRYSTAL_OUT_REQ_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000400 ) >> 10)
+#define GET_MP_PHY2RX_DATA__5_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000800 ) >> 11)
+#define GET_MP_PHY2RX_DATA__3_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00001000 ) >> 12)
+#define GET_UART_RXD_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00006000 ) >> 13)
+#define GET_MP_PHY2RX_DATA__6_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00008000 ) >> 15)
+#define GET_DAT_UART_NCTS_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00010000 ) >> 16)
+#define GET_GPIO_LOG_STOP_SEL (((REG32(ADR_PIN_SEL_0)) & 0x000e0000 ) >> 17)
+#define GET_MP_TX_FF_RPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00100000 ) >> 20)
+#define GET_MP_PHY_RX_WRST_N_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00200000 ) >> 21)
+#define GET_EXT_32K_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00c00000 ) >> 22)
+#define GET_MP_PHY2RX_DATA__7_SEL (((REG32(ADR_PIN_SEL_0)) & 0x01000000 ) >> 24)
+#define GET_MP_TX_FF_RPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x02000000 ) >> 25)
+#define GET_PMUINT_WAKE_SEL (((REG32(ADR_PIN_SEL_0)) & 0x1c000000 ) >> 26)
+#define GET_I2CM_SCL_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x20000000 ) >> 29)
+#define GET_MP_MRX_RX_EN_SEL (((REG32(ADR_PIN_SEL_0)) & 0x40000000 ) >> 30)
+#define GET_DAT_UART_RXD_SEL_0 (((REG32(ADR_PIN_SEL_0)) & 0x80000000 ) >> 31)
+#define GET_DAT_UART_RXD_SEL_1 (((REG32(ADR_PIN_SEL_1)) & 0x00000001 ) >> 0)
+#define GET_SPI_DI_SEL (((REG32(ADR_PIN_SEL_1)) & 0x00000002 ) >> 1)
+#define GET_IO_PORT_REG (((REG32(ADR_IO_PORT_REG)) & 0x0001ffff ) >> 0)
+#define GET_MASK_RX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000001 ) >> 0)
+#define GET_MASK_TX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000002 ) >> 1)
+#define GET_MASK_SOC_SYSTEM_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000080 ) >> 7)
+#define GET_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000001 ) >> 0)
+#define GET_TX_COMPLETE_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000002 ) >> 1)
+#define GET_SOC_SYSTEM_INT_STATUS (((REG32(ADR_INT_STATUS_REG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000080 ) >> 7)
+#define GET_HOST_TRIGGERED_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000100 ) >> 8)
+#define GET_HOST_TRIGGERED_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000200 ) >> 9)
+#define GET_SOC_TRIGGER_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000400 ) >> 10)
+#define GET_SOC_TRIGGER_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000800 ) >> 11)
+#define GET_RDY_FOR_TX_RX (((REG32(ADR_FN1_STATUS_REG)) & 0x00000001 ) >> 0)
+#define GET_RDY_FOR_FW_DOWNLOAD (((REG32(ADR_FN1_STATUS_REG)) & 0x00000002 ) >> 1)
+#define GET_ILLEGAL_CMD_RESP_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000004 ) >> 2)
+#define GET_SDIO_TRX_DATA_SEQUENCE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000008 ) >> 3)
+#define GET_GPIO_INT_TRIGGER_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000010 ) >> 4)
+#define GET_TRIGGER_FUNCTION_SETTING (((REG32(ADR_FN1_STATUS_REG)) & 0x00000060 ) >> 5)
+#define GET_CMD52_ABORT_RESPONSE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000080 ) >> 7)
+#define GET_RX_PACKET_LENGTH (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x0000ffff ) >> 0)
+#define GET_CARD_FW_DL_STATUS (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x00ff0000 ) >> 16)
+#define GET_TX_RX_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x01000000 ) >> 24)
+#define GET_SDIO_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x02000000 ) >> 25)
+#define GET_CMD52_ABORT_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x10000000 ) >> 28)
+#define GET_CMD52_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x20000000 ) >> 29)
+#define GET_SDIO_PARTIAL_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x40000000 ) >> 30)
+#define GET_SDIO_ALL_RESE_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x80000000 ) >> 31)
+#define GET_RX_PACKET_LENGTH2 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x0000ffff ) >> 0)
+#define GET_RX_INT1 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00010000 ) >> 16)
+#define GET_TX_DONE (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00020000 ) >> 17)
+#define GET_HCI_TRX_FINISH (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00040000 ) >> 18)
+#define GET_ALLOCATE_STATUS (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00080000 ) >> 19)
+#define GET_HCI_INPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00f00000 ) >> 20)
+#define GET_HCI_OUTPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x1f000000 ) >> 24)
+#define GET_AHB_HANG4 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x20000000 ) >> 29)
+#define GET_HCI_IN_QUE_EMPTY (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x40000000 ) >> 30)
+#define GET_SYSTEM_INT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x80000000 ) >> 31)
+#define GET_CARD_RCA_REG (((REG32(ADR_CARD_RCA_REG)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_FIFO_WR_THLD_REG (((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_FIFO_WR_LIMIT_REG (((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_TX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_THLD_FOR_CMD53RD_REG (((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_RX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
+#define GET_START_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x000000ff ) >> 0)
+#define GET_END_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x0000ff00 ) >> 8)
+#define GET_SDIO_BYTE_MODE_BATCH_SIZE_REG (((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0x000000ff ) >> 0)
+#define GET_SDIO_LAST_CMD_INDEX_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x0000003f ) >> 0)
+#define GET_SDIO_LAST_CMD_CRC_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x00007f00 ) >> 8)
+#define GET_SDIO_LAST_CMD_ARG_REG (((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0xffffffff ) >> 0)
+#define GET_SDIO_BUS_STATE_REG (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000001f ) >> 0)
+#define GET_SDIO_BUSY_LONG_CNT (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffff0000 ) >> 16)
+#define GET_SDIO_CARD_STATUS_REG (((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0xffffffff ) >> 0)
+#define GET_R5_RESPONSE_FLAG (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x000000ff ) >> 0)
+#define GET_RESP_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000100 ) >> 8)
+#define GET_DAT_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000200 ) >> 9)
+#define GET_MCU_TO_SDIO_INFO_MASK (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00010000 ) >> 16)
+#define GET_INT_THROUGH_PIN (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00020000 ) >> 17)
+#define GET_WRITE_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x000000ff ) >> 0)
+#define GET_WRITE_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x0000ff00 ) >> 8)
+#define GET_READ_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ff0000 ) >> 16)
+#define GET_READ_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff000000 ) >> 24)
+#define GET_FN1_DMA_START_ADDR_REG (((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0xffffffff ) >> 0)
+#define GET_SDIO_TO_MCU_INFO (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x000000ff ) >> 0)
+#define GET_SDIO_PARTIAL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000100 ) >> 8)
+#define GET_SDIO_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000200 ) >> 9)
+#define GET_PERI_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000400 ) >> 10)
+#define GET_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000800 ) >> 11)
+#define GET_AHB_BRIDGE_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00001000 ) >> 12)
+#define GET_IO_REG_PORT_REG (((REG32(ADR_IO_REG_PORT_REG)) & 0x0001ffff ) >> 0)
+#define GET_SDIO_FIFO_EMPTY_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_FIFO_FULL_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000 ) >> 16)
+#define GET_SDIO_CRC7_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_CRC16_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000 ) >> 16)
+#define GET_SDIO_RD_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x000001ff ) >> 0)
+#define GET_SDIO_WR_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x01ff0000 ) >> 16)
+#define GET_CMD52_RD_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x000f0000 ) >> 16)
+#define GET_CMD52_WR_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x00f00000 ) >> 20)
+#define GET_SDIO_FIFO_WR_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x000000ff ) >> 0)
+#define GET_SDIO_FIFO_RD_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x0000ff00 ) >> 8)
+#define GET_SDIO_READ_DATA_CTRL (((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0x00010000 ) >> 16)
+#define GET_TX_SIZE_BEFORE_SHIFT (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x000000ff ) >> 0)
+#define GET_TX_SIZE_SHIFT_BITS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00000700 ) >> 8)
+#define GET_SDIO_TX_ALLOC_STATE (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00001000 ) >> 12)
+#define GET_ALLOCATE_STATUS2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00010000 ) >> 16)
+#define GET_NO_ALLOCATE_SEND_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00020000 ) >> 17)
+#define GET_DOUBLE_ALLOCATE_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00040000 ) >> 18)
+#define GET_TX_DONE_STATUS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00080000 ) >> 19)
+#define GET_AHB_HANG2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00100000 ) >> 20)
+#define GET_HCI_TRX_FINISH2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00200000 ) >> 21)
+#define GET_INTR_RX (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00400000 ) >> 22)
+#define GET_HCI_INPUT_QUEUE_FULL (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00800000 ) >> 23)
+#define GET_ALLOCATESTATUS (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000001 ) >> 0)
+#define GET_HCI_TRX_FINISH3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000002 ) >> 1)
+#define GET_HCI_IN_QUE_EMPTY2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000004 ) >> 2)
+#define GET_MTX_MNG_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000008 ) >> 3)
+#define GET_EDCA0_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000010 ) >> 4)
+#define GET_EDCA1_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000020 ) >> 5)
+#define GET_EDCA2_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000040 ) >> 6)
+#define GET_EDCA3_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000080 ) >> 7)
+#define GET_TX_PAGE_REMAIN2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0000ff00 ) >> 8)
+#define GET_TX_ID_REMAIN3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x007f0000 ) >> 16)
+#define GET_HCI_OUTPUT_FF_CNT_0 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00800000 ) >> 23)
+#define GET_HCI_OUTPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0f000000 ) >> 24)
+#define GET_HCI_INPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0xf0000000 ) >> 28)
+#define GET_F1_BLOCK_SIZE_0_REG (((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0x00000fff ) >> 0)
+#define GET_START_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x000000ff ) >> 0)
+#define GET_COMMAND_COUNTER (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ff00 ) >> 8)
+#define GET_CMD_LOG_PART1 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff0000 ) >> 16)
+#define GET_CMD_LOG_PART2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff ) >> 0)
+#define GET_END_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000 ) >> 24)
+#define GET_RX_PACKET_LENGTH3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x0000ffff ) >> 0)
+#define GET_RX_INT3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_TX_ID_REMAIN2 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00fe0000 ) >> 17)
+#define GET_TX_PAGE_REMAIN3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff000000 ) >> 24)
+#define GET_CCCR_00H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x000000ff ) >> 0)
+#define GET_CCCR_02H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x00ff0000 ) >> 16)
+#define GET_CCCR_03H_REG (((REG32(ADR_CCCR_00H_REG)) & 0xff000000 ) >> 24)
+#define GET_CCCR_04H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000000ff ) >> 0)
+#define GET_CCCR_05H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x0000ff00 ) >> 8)
+#define GET_CCCR_06H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000f0000 ) >> 16)
+#define GET_CCCR_07H_REG (((REG32(ADR_CCCR_04H_REG)) & 0xff000000 ) >> 24)
+#define GET_SUPPORT_DIRECT_COMMAND_SDIO (((REG32(ADR_CCCR_08H_REG)) & 0x00000001 ) >> 0)
+#define GET_SUPPORT_MULTIPLE_BLOCK_TRANSFER (((REG32(ADR_CCCR_08H_REG)) & 0x00000002 ) >> 1)
+#define GET_SUPPORT_READ_WAIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000004 ) >> 2)
+#define GET_SUPPORT_BUS_CONTROL (((REG32(ADR_CCCR_08H_REG)) & 0x00000008 ) >> 3)
+#define GET_SUPPORT_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000010 ) >> 4)
+#define GET_ENABLE_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000020 ) >> 5)
+#define GET_LOW_SPEED_CARD (((REG32(ADR_CCCR_08H_REG)) & 0x00000040 ) >> 6)
+#define GET_LOW_SPEED_CARD_4BIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000080 ) >> 7)
+#define GET_COMMON_CIS_PONTER (((REG32(ADR_CCCR_08H_REG)) & 0x01ffff00 ) >> 8)
+#define GET_SUPPORT_HIGH_SPEED (((REG32(ADR_CCCR_13H_REG)) & 0x01000000 ) >> 24)
+#define GET_BSS (((REG32(ADR_CCCR_13H_REG)) & 0x0e000000 ) >> 25)
+#define GET_FBR_100H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000000f ) >> 0)
+#define GET_CSASUPPORT (((REG32(ADR_FBR_100H_REG)) & 0x00000040 ) >> 6)
+#define GET_ENABLECSA (((REG32(ADR_FBR_100H_REG)) & 0x00000080 ) >> 7)
+#define GET_FBR_101H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000ff00 ) >> 8)
+#define GET_FBR_109H_REG (((REG32(ADR_FBR_109H_REG)) & 0x01ffff00 ) >> 8)
+#define GET_F0_CIS_CONTENT_REG_31_0 (((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_63_32 (((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_95_64 (((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_127_96 (((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_159_128 (((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_191_160 (((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_223_192 (((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_255_224 (((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_287_256 (((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_319_288 (((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_351_320 (((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_383_352 (((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_415_384 (((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_447_416 (((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_479_448 (((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_511_480 (((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_31_0 (((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_63_32 (((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_95_64 (((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_127_96 (((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_159_128 (((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_191_160 (((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_223_192 (((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_255_224 (((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_287_256 (((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_319_288 (((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_351_320 (((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_383_352 (((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_415_384 (((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_447_416 (((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_479_448 (((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_511_480 (((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
+#define GET_SPI_MODE (((REG32(ADR_SPI_MODE)) & 0xffffffff ) >> 0)
+#define GET_RX_QUOTA (((REG32(ADR_RX_QUOTA)) & 0x0000ffff ) >> 0)
+#define GET_CONDI_NUM (((REG32(ADR_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
+#define GET_HOST_PATH (((REG32(ADR_HOST_PATH)) & 0x00000001 ) >> 0)
+#define GET_TX_SEG (((REG32(ADR_TX_SEG)) & 0xffffffff ) >> 0)
+#define GET_BRST_MODE (((REG32(ADR_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
+#define GET_CLK_WIDTH (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
+#define GET_CSN_INTER (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
+#define GET_BACK_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_FRONT_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
+#define GET_RX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000002 ) >> 1)
+#define GET_RX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000004 ) >> 2)
+#define GET_TX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000008 ) >> 3)
+#define GET_TX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000010 ) >> 4)
+#define GET_SPI_DOUBLE_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000020 ) >> 5)
+#define GET_SPI_TX_NO_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000040 ) >> 6)
+#define GET_RDATA_RDY (((REG32(ADR_SPI_STS)) & 0x00000080 ) >> 7)
+#define GET_SPI_ALLOC_STATUS (((REG32(ADR_SPI_STS)) & 0x00000100 ) >> 8)
+#define GET_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_SPI_STS)) & 0x00000200 ) >> 9)
+#define GET_RX_LEN (((REG32(ADR_SPI_STS)) & 0xffff0000 ) >> 16)
+#define GET_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
+#define GET_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
+#define GET_SPI_TX_ALLOC_SIZE (((REG32(ADR_TX_ALLOC)) & 0x000000ff ) >> 0)
+#define GET_RD_DAT_CNT (((REG32(ADR_DBG_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RD_STS_CNT (((REG32(ADR_DBG_CNT)) & 0xffff0000 ) >> 16)
+#define GET_JUDGE_CNT (((REG32(ADR_DBG_CNT2)) & 0x0000ffff ) >> 0)
+#define GET_RD_STS_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00010000 ) >> 16)
+#define GET_RD_DAT_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00020000 ) >> 17)
+#define GET_JUDGE_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00040000 ) >> 18)
+#define GET_TX_DONE_CNT (((REG32(ADR_DBG_CNT3)) & 0x0000ffff ) >> 0)
+#define GET_TX_DISCARD_CNT (((REG32(ADR_DBG_CNT3)) & 0xffff0000 ) >> 16)
+#define GET_TX_SET_CNT (((REG32(ADR_DBG_CNT4)) & 0x0000ffff ) >> 0)
+#define GET_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00010000 ) >> 16)
+#define GET_TX_DONE_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00020000 ) >> 17)
+#define GET_TX_SET_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00040000 ) >> 18)
+#define GET_DAT_MODE_OFF (((REG32(ADR_DBG_CNT4)) & 0x00080000 ) >> 19)
+#define GET_TX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x00700000 ) >> 20)
+#define GET_RX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x07000000 ) >> 24)
+#define GET_RX_RDY (((REG32(ADR_INT_TAG)) & 0x00000001 ) >> 0)
+#define GET_SDIO_SYS_INT (((REG32(ADR_INT_TAG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_IN (((REG32(ADR_INT_TAG)) & 0x00000080 ) >> 7)
+#define GET_SPI_FN1 (((REG32(ADR_INT_TAG)) & 0x00007f00 ) >> 8)
+#define GET_SPI_CLK_EN_INT (((REG32(ADR_INT_TAG)) & 0x00008000 ) >> 15)
+#define GET_SPI_HOST_MASK (((REG32(ADR_INT_TAG)) & 0x00ff0000 ) >> 16)
+#define GET_I2CM_INT_WDONE (((REG32(ADR_I2CM_EN)) & 0x00000001 ) >> 0)
+#define GET_I2CM_INT_RDONE (((REG32(ADR_I2CM_EN)) & 0x00000002 ) >> 1)
+#define GET_I2CM_IDLE (((REG32(ADR_I2CM_EN)) & 0x00000004 ) >> 2)
+#define GET_I2CM_INT_MISMATCH (((REG32(ADR_I2CM_EN)) & 0x00000008 ) >> 3)
+#define GET_I2CM_PSCL (((REG32(ADR_I2CM_EN)) & 0x00003ff0 ) >> 4)
+#define GET_I2CM_MANUAL_MODE (((REG32(ADR_I2CM_EN)) & 0x00010000 ) >> 16)
+#define GET_I2CM_INT_WDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00020000 ) >> 17)
+#define GET_I2CM_INT_RDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00040000 ) >> 18)
+#define GET_I2CM_DEV_A (((REG32(ADR_I2CM_DEV_A)) & 0x000003ff ) >> 0)
+#define GET_I2CM_DEV_A10B (((REG32(ADR_I2CM_DEV_A)) & 0x00004000 ) >> 14)
+#define GET_I2CM_RX (((REG32(ADR_I2CM_DEV_A)) & 0x00008000 ) >> 15)
+#define GET_I2CM_LEN (((REG32(ADR_I2CM_LEN)) & 0x0000ffff ) >> 0)
+#define GET_I2CM_T_LEFT (((REG32(ADR_I2CM_LEN)) & 0x00070000 ) >> 16)
+#define GET_I2CM_R_GET (((REG32(ADR_I2CM_LEN)) & 0x07000000 ) >> 24)
+#define GET_I2CM_WDAT (((REG32(ADR_I2CM_WDAT)) & 0xffffffff ) >> 0)
+#define GET_I2CM_RDAT (((REG32(ADR_I2CM_RDAT)) & 0xffffffff ) >> 0)
+#define GET_I2CM_SR_LEN (((REG32(ADR_I2CM_EN_2)) & 0x0000ffff ) >> 0)
+#define GET_I2CM_SR_RX (((REG32(ADR_I2CM_EN_2)) & 0x00010000 ) >> 16)
+#define GET_I2CM_REPEAT_START (((REG32(ADR_I2CM_EN_2)) & 0x00020000 ) >> 17)
+#define GET_UART_DATA (((REG32(ADR_UART_DATA)) & 0x000000ff ) >> 0)
+#define GET_DATA_RDY_IE (((REG32(ADR_UART_IER)) & 0x00000001 ) >> 0)
+#define GET_THR_EMPTY_IE (((REG32(ADR_UART_IER)) & 0x00000002 ) >> 1)
+#define GET_RX_LINESTS_IE (((REG32(ADR_UART_IER)) & 0x00000004 ) >> 2)
+#define GET_MDM_STS_IE (((REG32(ADR_UART_IER)) & 0x00000008 ) >> 3)
+#define GET_DMA_RXEND_IE (((REG32(ADR_UART_IER)) & 0x00000040 ) >> 6)
+#define GET_DMA_TXEND_IE (((REG32(ADR_UART_IER)) & 0x00000080 ) >> 7)
+#define GET_FIFO_EN (((REG32(ADR_UART_FCR)) & 0x00000001 ) >> 0)
+#define GET_RXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000002 ) >> 1)
+#define GET_TXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000004 ) >> 2)
+#define GET_DMA_MODE (((REG32(ADR_UART_FCR)) & 0x00000008 ) >> 3)
+#define GET_EN_AUTO_RTS (((REG32(ADR_UART_FCR)) & 0x00000010 ) >> 4)
+#define GET_EN_AUTO_CTS (((REG32(ADR_UART_FCR)) & 0x00000020 ) >> 5)
+#define GET_RXFIFO_TRGLVL (((REG32(ADR_UART_FCR)) & 0x000000c0 ) >> 6)
+#define GET_WORD_LEN (((REG32(ADR_UART_LCR)) & 0x00000003 ) >> 0)
+#define GET_STOP_BIT (((REG32(ADR_UART_LCR)) & 0x00000004 ) >> 2)
+#define GET_PARITY_EN (((REG32(ADR_UART_LCR)) & 0x00000008 ) >> 3)
+#define GET_EVEN_PARITY (((REG32(ADR_UART_LCR)) & 0x00000010 ) >> 4)
+#define GET_FORCE_PARITY (((REG32(ADR_UART_LCR)) & 0x00000020 ) >> 5)
+#define GET_SET_BREAK (((REG32(ADR_UART_LCR)) & 0x00000040 ) >> 6)
+#define GET_DLAB (((REG32(ADR_UART_LCR)) & 0x00000080 ) >> 7)
+#define GET_DTR (((REG32(ADR_UART_MCR)) & 0x00000001 ) >> 0)
+#define GET_RTS (((REG32(ADR_UART_MCR)) & 0x00000002 ) >> 1)
+#define GET_OUT_1 (((REG32(ADR_UART_MCR)) & 0x00000004 ) >> 2)
+#define GET_OUT_2 (((REG32(ADR_UART_MCR)) & 0x00000008 ) >> 3)
+#define GET_LOOP_BACK (((REG32(ADR_UART_MCR)) & 0x00000010 ) >> 4)
+#define GET_DATA_RDY (((REG32(ADR_UART_LSR)) & 0x00000001 ) >> 0)
+#define GET_OVERRUN_ERR (((REG32(ADR_UART_LSR)) & 0x00000002 ) >> 1)
+#define GET_PARITY_ERR (((REG32(ADR_UART_LSR)) & 0x00000004 ) >> 2)
+#define GET_FRAMING_ERR (((REG32(ADR_UART_LSR)) & 0x00000008 ) >> 3)
+#define GET_BREAK_INT (((REG32(ADR_UART_LSR)) & 0x00000010 ) >> 4)
+#define GET_THR_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000020 ) >> 5)
+#define GET_TX_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000040 ) >> 6)
+#define GET_FIFODATA_ERR (((REG32(ADR_UART_LSR)) & 0x00000080 ) >> 7)
+#define GET_DELTA_CTS (((REG32(ADR_UART_MSR)) & 0x00000001 ) >> 0)
+#define GET_DELTA_DSR (((REG32(ADR_UART_MSR)) & 0x00000002 ) >> 1)
+#define GET_TRAILEDGE_RI (((REG32(ADR_UART_MSR)) & 0x00000004 ) >> 2)
+#define GET_DELTA_CD (((REG32(ADR_UART_MSR)) & 0x00000008 ) >> 3)
+#define GET_CTS (((REG32(ADR_UART_MSR)) & 0x00000010 ) >> 4)
+#define GET_DSR (((REG32(ADR_UART_MSR)) & 0x00000020 ) >> 5)
+#define GET_RI (((REG32(ADR_UART_MSR)) & 0x00000040 ) >> 6)
+#define GET_CD (((REG32(ADR_UART_MSR)) & 0x00000080 ) >> 7)
+#define GET_BRDC_DIV (((REG32(ADR_UART_SPR)) & 0x0000ffff ) >> 0)
+#define GET_RTHR_L (((REG32(ADR_UART_RTHR)) & 0x0000000f ) >> 0)
+#define GET_RTHR_H (((REG32(ADR_UART_RTHR)) & 0x000000f0 ) >> 4)
+#define GET_INT_IDCODE (((REG32(ADR_UART_ISR)) & 0x0000000f ) >> 0)
+#define GET_FIFOS_ENABLED (((REG32(ADR_UART_ISR)) & 0x000000c0 ) >> 6)
+#define GET_DAT_UART_DATA (((REG32(ADR_DAT_UART_DATA)) & 0x000000ff ) >> 0)
+#define GET_DAT_DATA_RDY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000001 ) >> 0)
+#define GET_DAT_THR_EMPTY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000002 ) >> 1)
+#define GET_DAT_RX_LINESTS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000004 ) >> 2)
+#define GET_DAT_MDM_STS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000008 ) >> 3)
+#define GET_DAT_DMA_RXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000040 ) >> 6)
+#define GET_DAT_DMA_TXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000080 ) >> 7)
+#define GET_DAT_FIFO_EN (((REG32(ADR_DAT_UART_FCR)) & 0x00000001 ) >> 0)
+#define GET_DAT_RXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000002 ) >> 1)
+#define GET_DAT_TXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000004 ) >> 2)
+#define GET_DAT_DMA_MODE (((REG32(ADR_DAT_UART_FCR)) & 0x00000008 ) >> 3)
+#define GET_DAT_EN_AUTO_RTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000010 ) >> 4)
+#define GET_DAT_EN_AUTO_CTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000020 ) >> 5)
+#define GET_DAT_RXFIFO_TRGLVL (((REG32(ADR_DAT_UART_FCR)) & 0x000000c0 ) >> 6)
+#define GET_DAT_WORD_LEN (((REG32(ADR_DAT_UART_LCR)) & 0x00000003 ) >> 0)
+#define GET_DAT_STOP_BIT (((REG32(ADR_DAT_UART_LCR)) & 0x00000004 ) >> 2)
+#define GET_DAT_PARITY_EN (((REG32(ADR_DAT_UART_LCR)) & 0x00000008 ) >> 3)
+#define GET_DAT_EVEN_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000010 ) >> 4)
+#define GET_DAT_FORCE_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000020 ) >> 5)
+#define GET_DAT_SET_BREAK (((REG32(ADR_DAT_UART_LCR)) & 0x00000040 ) >> 6)
+#define GET_DAT_DLAB (((REG32(ADR_DAT_UART_LCR)) & 0x00000080 ) >> 7)
+#define GET_DAT_DTR (((REG32(ADR_DAT_UART_MCR)) & 0x00000001 ) >> 0)
+#define GET_DAT_RTS (((REG32(ADR_DAT_UART_MCR)) & 0x00000002 ) >> 1)
+#define GET_DAT_OUT_1 (((REG32(ADR_DAT_UART_MCR)) & 0x00000004 ) >> 2)
+#define GET_DAT_OUT_2 (((REG32(ADR_DAT_UART_MCR)) & 0x00000008 ) >> 3)
+#define GET_DAT_LOOP_BACK (((REG32(ADR_DAT_UART_MCR)) & 0x00000010 ) >> 4)
+#define GET_DAT_DATA_RDY (((REG32(ADR_DAT_UART_LSR)) & 0x00000001 ) >> 0)
+#define GET_DAT_OVERRUN_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000002 ) >> 1)
+#define GET_DAT_PARITY_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000004 ) >> 2)
+#define GET_DAT_FRAMING_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000008 ) >> 3)
+#define GET_DAT_BREAK_INT (((REG32(ADR_DAT_UART_LSR)) & 0x00000010 ) >> 4)
+#define GET_DAT_THR_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000020 ) >> 5)
+#define GET_DAT_TX_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000040 ) >> 6)
+#define GET_DAT_FIFODATA_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000080 ) >> 7)
+#define GET_DAT_DELTA_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000001 ) >> 0)
+#define GET_DAT_DELTA_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000002 ) >> 1)
+#define GET_DAT_TRAILEDGE_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000004 ) >> 2)
+#define GET_DAT_DELTA_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000008 ) >> 3)
+#define GET_DAT_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000010 ) >> 4)
+#define GET_DAT_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000020 ) >> 5)
+#define GET_DAT_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000040 ) >> 6)
+#define GET_DAT_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000080 ) >> 7)
+#define GET_DAT_BRDC_DIV (((REG32(ADR_DAT_UART_SPR)) & 0x0000ffff ) >> 0)
+#define GET_DAT_RTHR_L (((REG32(ADR_DAT_UART_RTHR)) & 0x0000000f ) >> 0)
+#define GET_DAT_RTHR_H (((REG32(ADR_DAT_UART_RTHR)) & 0x000000f0 ) >> 4)
+#define GET_DAT_INT_IDCODE (((REG32(ADR_DAT_UART_ISR)) & 0x0000000f ) >> 0)
+#define GET_DAT_FIFOS_ENABLED (((REG32(ADR_DAT_UART_ISR)) & 0x000000c0 ) >> 6)
+#define GET_MASK_TOP (((REG32(ADR_INT_MASK)) & 0xffffffff ) >> 0)
+#define GET_INT_MODE (((REG32(ADR_INT_MODE)) & 0xffffffff ) >> 0)
+#define GET_IRQ_PHY_0 (((REG32(ADR_INT_IRQ_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_PHY_1 (((REG32(ADR_INT_IRQ_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_SDIO (((REG32(ADR_INT_IRQ_STS)) & 0x00000004 ) >> 2)
+#define GET_IRQ_BEACON_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000010 ) >> 4)
+#define GET_IRQ_PRE_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000020 ) >> 5)
+#define GET_IRQ_EDCA0_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000040 ) >> 6)
+#define GET_IRQ_EDCA1_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000080 ) >> 7)
+#define GET_IRQ_EDCA2_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000100 ) >> 8)
+#define GET_IRQ_EDCA3_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000200 ) >> 9)
+#define GET_IRQ_EDCA4_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000400 ) >> 10)
+#define GET_IRQ_BEACON_DTIM (((REG32(ADR_INT_IRQ_STS)) & 0x00001000 ) >> 12)
+#define GET_IRQ_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00002000 ) >> 13)
+#define GET_IRQ_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00004000 ) >> 14)
+#define GET_IRQ_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00008000 ) >> 15)
+#define GET_IRQ_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00010000 ) >> 16)
+#define GET_IRQ_FENCE_HIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00020000 ) >> 17)
+#define GET_IRQ_ILL_ADDR_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00040000 ) >> 18)
+#define GET_IRQ_MBOX (((REG32(ADR_INT_IRQ_STS)) & 0x00080000 ) >> 19)
+#define GET_IRQ_US_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x00100000 ) >> 20)
+#define GET_IRQ_US_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x00200000 ) >> 21)
+#define GET_IRQ_US_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x00400000 ) >> 22)
+#define GET_IRQ_US_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x00800000 ) >> 23)
+#define GET_IRQ_MS_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x01000000 ) >> 24)
+#define GET_IRQ_MS_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_MS_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_MS_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x08000000 ) >> 27)
+#define GET_IRQ_TX_LIMIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x10000000 ) >> 28)
+#define GET_IRQ_DMA0 (((REG32(ADR_INT_IRQ_STS)) & 0x20000000 ) >> 29)
+#define GET_IRQ_CO_DMA (((REG32(ADR_INT_IRQ_STS)) & 0x40000000 ) >> 30)
+#define GET_IRQ_PERI_GROUP (((REG32(ADR_INT_IRQ_STS)) & 0x80000000 ) >> 31)
+#define GET_FIQ_STATUS (((REG32(ADR_INT_FIQ_STS)) & 0xffffffff ) >> 0)
+#define GET_IRQ_RAW (((REG32(ADR_INT_IRQ_RAW)) & 0xffffffff ) >> 0)
+#define GET_FIQ_RAW (((REG32(ADR_INT_FIQ_RAW)) & 0xffffffff ) >> 0)
+#define GET_INT_PERI_MASK (((REG32(ADR_INT_PERI_MASK)) & 0xffffffff ) >> 0)
+#define GET_PERI_RTC (((REG32(ADR_INT_PERI_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_UART0_TX (((REG32(ADR_INT_PERI_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_UART0_RX (((REG32(ADR_INT_PERI_STS)) & 0x00000004 ) >> 2)
+#define GET_PERI_GPI_2 (((REG32(ADR_INT_PERI_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_SPI_IPC (((REG32(ADR_INT_PERI_STS)) & 0x00000010 ) >> 4)
+#define GET_PERI_GPI_1_0 (((REG32(ADR_INT_PERI_STS)) & 0x00000060 ) >> 5)
+#define GET_SCRT_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000080 ) >> 7)
+#define GET_MMU_ALC_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000100 ) >> 8)
+#define GET_MMU_RLS_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000400 ) >> 10)
+#define GET_MBOX_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000800 ) >> 11)
+#define GET_MBOX_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00001000 ) >> 12)
+#define GET_MBOX_INT_3 (((REG32(ADR_INT_PERI_STS)) & 0x00002000 ) >> 13)
+#define GET_HCI_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00004000 ) >> 14)
+#define GET_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x00008000 ) >> 15)
+#define GET_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x00010000 ) >> 16)
+#define GET_ID_MNG_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00020000 ) >> 17)
+#define GET_DMN_NOHIT_INT (((REG32(ADR_INT_PERI_STS)) & 0x00040000 ) >> 18)
+#define GET_ID_THOLD_RX (((REG32(ADR_INT_PERI_STS)) & 0x00080000 ) >> 19)
+#define GET_ID_THOLD_TX (((REG32(ADR_INT_PERI_STS)) & 0x00100000 ) >> 20)
+#define GET_ID_DOUBLE_RLS (((REG32(ADR_INT_PERI_STS)) & 0x00200000 ) >> 21)
+#define GET_RX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00400000 ) >> 22)
+#define GET_TX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00800000 ) >> 23)
+#define GET_ALL_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x01000000 ) >> 24)
+#define GET_DMN_MCU_INT (((REG32(ADR_INT_PERI_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_DAT_UART_TX (((REG32(ADR_INT_PERI_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_DAT_UART_RX (((REG32(ADR_INT_PERI_STS)) & 0x08000000 ) >> 27)
+#define GET_DAT_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x10000000 ) >> 28)
+#define GET_DAT_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x20000000 ) >> 29)
+#define GET_ALR_ABT_NOCHG_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x40000000 ) >> 30)
+#define GET_TBLNEQ_MNGPKT_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x80000000 ) >> 31)
+#define GET_INTR_PERI_RAW (((REG32(ADR_INT_PERI_RAW)) & 0xffffffff ) >> 0)
+#define GET_INTR_GPI00_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x00000003 ) >> 0)
+#define GET_INTR_GPI01_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x0000000c ) >> 2)
+#define GET_SYS_RST_INT (((REG32(ADR_SYS_INT_FOR_HOST)) & 0x00000001 ) >> 0)
+#define GET_SPI_IPC_ADDR (((REG32(ADR_SPI_IPC)) & 0xffffffff ) >> 0)
+#define GET_SD_MASK_TOP (((REG32(ADR_SDIO_MASK)) & 0xffffffff ) >> 0)
+#define GET_IRQ_PHY_0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_PHY_1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_SDIO_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000004 ) >> 2)
+#define GET_IRQ_BEACON_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000010 ) >> 4)
+#define GET_IRQ_PRE_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000020 ) >> 5)
+#define GET_IRQ_EDCA0_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000040 ) >> 6)
+#define GET_IRQ_EDCA1_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000080 ) >> 7)
+#define GET_IRQ_EDCA2_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000100 ) >> 8)
+#define GET_IRQ_EDCA3_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000200 ) >> 9)
+#define GET_IRQ_EDCA4_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000400 ) >> 10)
+#define GET_IRQ_BEACON_DTIM_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00001000 ) >> 12)
+#define GET_IRQ_EDCA0_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00002000 ) >> 13)
+#define GET_IRQ_EDCA1_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00004000 ) >> 14)
+#define GET_IRQ_EDCA2_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00008000 ) >> 15)
+#define GET_IRQ_EDCA3_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00010000 ) >> 16)
+#define GET_IRQ_FENCE_HIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00020000 ) >> 17)
+#define GET_IRQ_ILL_ADDR_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00040000 ) >> 18)
+#define GET_IRQ_MBOX_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00080000 ) >> 19)
+#define GET_IRQ_US_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00100000 ) >> 20)
+#define GET_IRQ_US_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00200000 ) >> 21)
+#define GET_IRQ_US_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00400000 ) >> 22)
+#define GET_IRQ_US_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00800000 ) >> 23)
+#define GET_IRQ_MS_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x01000000 ) >> 24)
+#define GET_IRQ_MS_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_MS_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_MS_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x08000000 ) >> 27)
+#define GET_IRQ_TX_LIMIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x10000000 ) >> 28)
+#define GET_IRQ_DMA0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x20000000 ) >> 29)
+#define GET_IRQ_CO_DMA_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x40000000 ) >> 30)
+#define GET_IRQ_PERI_GROUP_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x80000000 ) >> 31)
+#define GET_INT_PERI_MASK_SD (((REG32(ADR_SD_PERI_MASK)) & 0xffffffff ) >> 0)
+#define GET_PERI_RTC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_UART0_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_UART0_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000004 ) >> 2)
+#define GET_PERI_GPI_SD_2 (((REG32(ADR_SD_PERI_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_SPI_IPC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000010 ) >> 4)
+#define GET_PERI_GPI_SD_1_0 (((REG32(ADR_SD_PERI_STS)) & 0x00000060 ) >> 5)
+#define GET_SCRT_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000080 ) >> 7)
+#define GET_MMU_ALC_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000100 ) >> 8)
+#define GET_MMU_RLS_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000400 ) >> 10)
+#define GET_MBOX_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000800 ) >> 11)
+#define GET_MBOX_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00001000 ) >> 12)
+#define GET_MBOX_INT_3_SD (((REG32(ADR_SD_PERI_STS)) & 0x00002000 ) >> 13)
+#define GET_HCI_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00004000 ) >> 14)
+#define GET_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00008000 ) >> 15)
+#define GET_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x00010000 ) >> 16)
+#define GET_ID_MNG_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00020000 ) >> 17)
+#define GET_DMN_NOHIT_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00040000 ) >> 18)
+#define GET_ID_THOLD_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00080000 ) >> 19)
+#define GET_ID_THOLD_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00100000 ) >> 20)
+#define GET_ID_DOUBLE_RLS_SD (((REG32(ADR_SD_PERI_STS)) & 0x00200000 ) >> 21)
+#define GET_RX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00400000 ) >> 22)
+#define GET_TX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00800000 ) >> 23)
+#define GET_ALL_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x01000000 ) >> 24)
+#define GET_DMN_MCU_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_DAT_UART_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_DAT_UART_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x08000000 ) >> 27)
+#define GET_DAT_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x10000000 ) >> 28)
+#define GET_DAT_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x20000000 ) >> 29)
+#define GET_ALR_ABT_NOCHG_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x40000000 ) >> 30)
+#define GET_TBLNEQ_MNGPKT_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x80000000 ) >> 31)
+#define GET_DBG_SPI_MODE (((REG32(ADR_DBG_SPI_MODE)) & 0xffffffff ) >> 0)
+#define GET_DBG_RX_QUOTA (((REG32(ADR_DBG_RX_QUOTA)) & 0x0000ffff ) >> 0)
+#define GET_DBG_CONDI_NUM (((REG32(ADR_DBG_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
+#define GET_DBG_HOST_PATH (((REG32(ADR_DBG_HOST_PATH)) & 0x00000001 ) >> 0)
+#define GET_DBG_TX_SEG (((REG32(ADR_DBG_TX_SEG)) & 0xffffffff ) >> 0)
+#define GET_DBG_BRST_MODE (((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
+#define GET_DBG_CLK_WIDTH (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
+#define GET_DBG_CSN_INTER (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
+#define GET_DBG_BACK_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_DBG_FRONT_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
+#define GET_DBG_RX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000002 ) >> 1)
+#define GET_DBG_RX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000004 ) >> 2)
+#define GET_DBG_TX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000008 ) >> 3)
+#define GET_DBG_TX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000010 ) >> 4)
+#define GET_DBG_SPI_DOUBLE_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000020 ) >> 5)
+#define GET_DBG_SPI_TX_NO_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000040 ) >> 6)
+#define GET_DBG_RDATA_RDY (((REG32(ADR_DBG_SPI_STS)) & 0x00000080 ) >> 7)
+#define GET_DBG_SPI_ALLOC_STATUS (((REG32(ADR_DBG_SPI_STS)) & 0x00000100 ) >> 8)
+#define GET_DBG_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_DBG_SPI_STS)) & 0x00000200 ) >> 9)
+#define GET_DBG_RX_LEN (((REG32(ADR_DBG_SPI_STS)) & 0xffff0000 ) >> 16)
+#define GET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
+#define GET_DBG_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
+#define GET_DBG_SPI_TX_ALLOC_SIZE (((REG32(ADR_DBG_TX_ALLOC)) & 0x000000ff ) >> 0)
+#define GET_DBG_RD_DAT_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff ) >> 0)
+#define GET_DBG_RD_STS_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000 ) >> 16)
+#define GET_DBG_JUDGE_CNT (((REG32(ADR_DBG_DBG_CNT2)) & 0x0000ffff ) >> 0)
+#define GET_DBG_RD_STS_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00010000 ) >> 16)
+#define GET_DBG_RD_DAT_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00020000 ) >> 17)
+#define GET_DBG_JUDGE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00040000 ) >> 18)
+#define GET_DBG_TX_DONE_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TX_DISCARD_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000 ) >> 16)
+#define GET_DBG_TX_SET_CNT (((REG32(ADR_DBG_DBG_CNT4)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00010000 ) >> 16)
+#define GET_DBG_TX_DONE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00020000 ) >> 17)
+#define GET_DBG_TX_SET_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00040000 ) >> 18)
+#define GET_DBG_DAT_MODE_OFF (((REG32(ADR_DBG_DBG_CNT4)) & 0x00080000 ) >> 19)
+#define GET_DBG_TX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x00700000 ) >> 20)
+#define GET_DBG_RX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x07000000 ) >> 24)
+#define GET_DBG_RX_RDY (((REG32(ADR_DBG_INT_TAG)) & 0x00000001 ) >> 0)
+#define GET_DBG_SDIO_SYS_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000004 ) >> 2)
+#define GET_DBG_EDCA0_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000008 ) >> 3)
+#define GET_DBG_EDCA1_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000010 ) >> 4)
+#define GET_DBG_EDCA2_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000020 ) >> 5)
+#define GET_DBG_EDCA3_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000040 ) >> 6)
+#define GET_DBG_TX_LIMIT_INT_IN (((REG32(ADR_DBG_INT_TAG)) & 0x00000080 ) >> 7)
+#define GET_DBG_SPI_FN1 (((REG32(ADR_DBG_INT_TAG)) & 0x00007f00 ) >> 8)
+#define GET_DBG_SPI_CLK_EN_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00008000 ) >> 15)
+#define GET_DBG_SPI_HOST_MASK (((REG32(ADR_DBG_INT_TAG)) & 0x00ff0000 ) >> 16)
+#define GET_BOOT_ADDR (((REG32(ADR_BOOT_ADDR)) & 0x00ffffff ) >> 0)
+#define GET_CHECK_SUM_FAIL (((REG32(ADR_BOOT_ADDR)) & 0x80000000 ) >> 31)
+#define GET_VERIFY_DATA (((REG32(ADR_VERIFY_DATA)) & 0xffffffff ) >> 0)
+#define GET_FLASH_ADDR (((REG32(ADR_FLASH_ADDR)) & 0x00ffffff ) >> 0)
+#define GET_FLASH_CMD_CLR (((REG32(ADR_FLASH_ADDR)) & 0x10000000 ) >> 28)
+#define GET_FLASH_DMA_CLR (((REG32(ADR_FLASH_ADDR)) & 0x20000000 ) >> 29)
+#define GET_DMA_EN (((REG32(ADR_FLASH_ADDR)) & 0x40000000 ) >> 30)
+#define GET_DMA_BUSY (((REG32(ADR_FLASH_ADDR)) & 0x80000000 ) >> 31)
+#define GET_SRAM_ADDR (((REG32(ADR_SRAM_ADDR)) & 0xffffffff ) >> 0)
+#define GET_FLASH_DMA_LEN (((REG32(ADR_LEN)) & 0xffffffff ) >> 0)
+#define GET_FLASH_FRONT_DLY (((REG32(ADR_SPI_PARAM)) & 0x0000ffff ) >> 0)
+#define GET_FLASH_BACK_DLY (((REG32(ADR_SPI_PARAM)) & 0xffff0000 ) >> 16)
+#define GET_FLASH_CLK_WIDTH (((REG32(ADR_SPI_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_SPI_BUSY (((REG32(ADR_SPI_PARAM2)) & 0x00010000 ) >> 16)
+#define GET_FLS_REMAP (((REG32(ADR_SPI_PARAM2)) & 0x00020000 ) >> 17)
+#define GET_PBUS_SWP (((REG32(ADR_SPI_PARAM2)) & 0x00040000 ) >> 18)
+#define GET_BIT_MODE1 (((REG32(ADR_SPI_PARAM2)) & 0x00080000 ) >> 19)
+#define GET_BIT_MODE2 (((REG32(ADR_SPI_PARAM2)) & 0x00100000 ) >> 20)
+#define GET_BIT_MODE4 (((REG32(ADR_SPI_PARAM2)) & 0x00200000 ) >> 21)
+#define GET_BOOT_CHECK_SUM (((REG32(ADR_CHECK_SUM_RESULT)) & 0xffffffff ) >> 0)
+#define GET_CHECK_SUM_TAG (((REG32(ADR_CHECK_SUM_IN_FILE)) & 0xffffffff ) >> 0)
+#define GET_CMD_LEN (((REG32(ADR_COMMAND_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CMD_ADDR (((REG32(ADR_COMMAND_ADDR)) & 0xffffffff ) >> 0)
+#define GET_DMA_ADR_SRC (((REG32(ADR_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
+#define GET_DMA_ADR_DST (((REG32(ADR_DMA_ADR_DST)) & 0xffffffff ) >> 0)
+#define GET_DMA_SRC_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000007 ) >> 0)
+#define GET_DMA_SRC_INC (((REG32(ADR_DMA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_DMA_DST_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000070 ) >> 4)
+#define GET_DMA_DST_INC (((REG32(ADR_DMA_CTRL)) & 0x00000080 ) >> 7)
+#define GET_DMA_FAST_FILL (((REG32(ADR_DMA_CTRL)) & 0x00000100 ) >> 8)
+#define GET_DMA_SDIO_KICK (((REG32(ADR_DMA_CTRL)) & 0x00001000 ) >> 12)
+#define GET_DMA_BADR_EN (((REG32(ADR_DMA_CTRL)) & 0x00002000 ) >> 13)
+#define GET_DMA_LEN (((REG32(ADR_DMA_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_DMA_INT_MASK (((REG32(ADR_DMA_INT)) & 0x00000001 ) >> 0)
+#define GET_DMA_STS (((REG32(ADR_DMA_INT)) & 0x00000100 ) >> 8)
+#define GET_DMA_FINISH (((REG32(ADR_DMA_INT)) & 0x80000000 ) >> 31)
+#define GET_DMA_CONST (((REG32(ADR_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
+#define GET_SLEEP_WAKE_CNT (((REG32(ADR_PMU_0)) & 0x00ffffff ) >> 0)
+#define GET_RG_DLDO_LEVEL (((REG32(ADR_PMU_0)) & 0x07000000 ) >> 24)
+#define GET_RG_DLDO_BOOST_IQ (((REG32(ADR_PMU_0)) & 0x08000000 ) >> 27)
+#define GET_RG_BUCK_LEVEL (((REG32(ADR_PMU_0)) & 0x70000000 ) >> 28)
+#define GET_RG_BUCK_VREF_SEL (((REG32(ADR_PMU_0)) & 0x80000000 ) >> 31)
+#define GET_RG_RTC_OSC_RES_SW_MANUAL (((REG32(ADR_PMU_1)) & 0x000003ff ) >> 0)
+#define GET_RG_RTC_OSC_RES_SW (((REG32(ADR_PMU_1)) & 0x03ff0000 ) >> 16)
+#define GET_RTC_OSC_CAL_RES_RDY (((REG32(ADR_PMU_1)) & 0x80000000 ) >> 31)
+#define GET_RG_DCDC_MODE (((REG32(ADR_PMU_2)) & 0x00000001 ) >> 0)
+#define GET_RG_BUCK_EN_PSM (((REG32(ADR_PMU_2)) & 0x00000010 ) >> 4)
+#define GET_RG_BUCK_PSM_VTH (((REG32(ADR_PMU_2)) & 0x00000100 ) >> 8)
+#define GET_RG_RTC_OSC_RES_SW_MANUAL_EN (((REG32(ADR_PMU_2)) & 0x00001000 ) >> 12)
+#define GET_RG_RTC_RDY_DEGLITCH_TIMER (((REG32(ADR_PMU_2)) & 0x00006000 ) >> 13)
+#define GET_RTC_CAL_ENA (((REG32(ADR_PMU_2)) & 0x00010000 ) >> 16)
+#define GET_PMU_WAKE_TRIG_EVENT (((REG32(ADR_PMU_3)) & 0x00000003 ) >> 0)
+#define GET_DIGI_TOP_POR_MASK (((REG32(ADR_PMU_3)) & 0x00000010 ) >> 4)
+#define GET_PMU_ENTER_SLEEP_MODE (((REG32(ADR_PMU_3)) & 0x00000100 ) >> 8)
+#define GET_RG_RTC_DUMMIES (((REG32(ADR_PMU_3)) & 0xffff0000 ) >> 16)
+#define GET_RTC_EN (((REG32(ADR_RTC_1)) & 0x00000001 ) >> 0)
+#define GET_RTC_SRC (((REG32(ADR_RTC_1)) & 0x00000002 ) >> 1)
+#define GET_RTC_TICK_CNT (((REG32(ADR_RTC_1)) & 0x7fff0000 ) >> 16)
+#define GET_RTC_INT_SEC_MASK (((REG32(ADR_RTC_2)) & 0x00000001 ) >> 0)
+#define GET_RTC_INT_ALARM_MASK (((REG32(ADR_RTC_2)) & 0x00000002 ) >> 1)
+#define GET_RTC_INT_SEC (((REG32(ADR_RTC_2)) & 0x00010000 ) >> 16)
+#define GET_RTC_INT_ALARM (((REG32(ADR_RTC_2)) & 0x00020000 ) >> 17)
+#define GET_RTC_SEC_START_CNT (((REG32(ADR_RTC_3W)) & 0xffffffff ) >> 0)
+#define GET_RTC_SEC_CNT (((REG32(ADR_RTC_3R)) & 0xffffffff ) >> 0)
+#define GET_RTC_SEC_ALARM_VALUE (((REG32(ADR_RTC_4)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_ADR_SRC (((REG32(ADR_D2_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_ADR_DST (((REG32(ADR_D2_DMA_ADR_DST)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_SRC_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000007 ) >> 0)
+#define GET_D2_DMA_SRC_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_D2_DMA_DST_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000070 ) >> 4)
+#define GET_D2_DMA_DST_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000080 ) >> 7)
+#define GET_D2_DMA_FAST_FILL (((REG32(ADR_D2_DMA_CTRL)) & 0x00000100 ) >> 8)
+#define GET_D2_DMA_SDIO_KICK (((REG32(ADR_D2_DMA_CTRL)) & 0x00001000 ) >> 12)
+#define GET_D2_DMA_BADR_EN (((REG32(ADR_D2_DMA_CTRL)) & 0x00002000 ) >> 13)
+#define GET_D2_DMA_LEN (((REG32(ADR_D2_DMA_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_D2_DMA_INT_MASK (((REG32(ADR_D2_DMA_INT)) & 0x00000001 ) >> 0)
+#define GET_D2_DMA_STS (((REG32(ADR_D2_DMA_INT)) & 0x00000100 ) >> 8)
+#define GET_D2_DMA_FINISH (((REG32(ADR_D2_DMA_INT)) & 0x80000000 ) >> 31)
+#define GET_D2_DMA_CONST (((REG32(ADR_D2_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
+#define GET_TRAP_UNKNOWN_TYPE (((REG32(ADR_CONTROL)) & 0x00000001 ) >> 0)
+#define GET_TX_ON_DEMAND_ENA (((REG32(ADR_CONTROL)) & 0x00000002 ) >> 1)
+#define GET_RX_2_HOST (((REG32(ADR_CONTROL)) & 0x00000004 ) >> 2)
+#define GET_AUTO_SEQNO (((REG32(ADR_CONTROL)) & 0x00000008 ) >> 3)
+#define GET_BYPASSS_TX_PARSER_ENCAP (((REG32(ADR_CONTROL)) & 0x00000010 ) >> 4)
+#define GET_HDR_STRIP (((REG32(ADR_CONTROL)) & 0x00000020 ) >> 5)
+#define GET_ERP_PROTECT (((REG32(ADR_CONTROL)) & 0x000000c0 ) >> 6)
+#define GET_PRO_VER (((REG32(ADR_CONTROL)) & 0x00000300 ) >> 8)
+#define GET_TXQ_ID0 (((REG32(ADR_CONTROL)) & 0x00007000 ) >> 12)
+#define GET_TXQ_ID1 (((REG32(ADR_CONTROL)) & 0x00070000 ) >> 16)
+#define GET_TX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00100000 ) >> 20)
+#define GET_RX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00200000 ) >> 21)
+#define GET_RX_NULL_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00400000 ) >> 22)
+#define GET_RX_GET_TX_QUEUE_EN (((REG32(ADR_CONTROL)) & 0x02000000 ) >> 25)
+#define GET_HCI_INQ_SEL (((REG32(ADR_CONTROL)) & 0x04000000 ) >> 26)
+#define GET_TRX_DEBUG_CNT_ENA (((REG32(ADR_CONTROL)) & 0x10000000 ) >> 28)
+#define GET_WAKE_SOON_WITH_SCK (((REG32(ADR_SDIO_WAKE_MODE)) & 0x00000001 ) >> 0)
+#define GET_TX_FLOW_CTRL (((REG32(ADR_TX_FLOW_0)) & 0x0000ffff ) >> 0)
+#define GET_TX_FLOW_MGMT (((REG32(ADR_TX_FLOW_0)) & 0xffff0000 ) >> 16)
+#define GET_TX_FLOW_DATA (((REG32(ADR_TX_FLOW_1)) & 0xffffffff ) >> 0)
+#define GET_DOT11RTSTHRESHOLD (((REG32(ADR_THREASHOLD)) & 0xffff0000 ) >> 16)
+#define GET_TXF_ID (((REG32(ADR_TXFID_INCREASE)) & 0x0000003f ) >> 0)
+#define GET_SEQ_CTRL (((REG32(ADR_GLOBAL_SEQUENCE)) & 0x0000ffff ) >> 0)
+#define GET_TX_PBOFFSET (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x000000ff ) >> 0)
+#define GET_TX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x0000ff00 ) >> 8)
+#define GET_RX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ff0000 ) >> 16)
+#define GET_RX_LAST_PHY_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff000000 ) >> 24)
+#define GET_TX_INFO_CLEAR_SIZE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x0000003f ) >> 0)
+#define GET_TX_INFO_CLEAR_ENABLE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x00000100 ) >> 8)
+#define GET_TXTRAP_ETHTYPE1 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
+#define GET_TXTRAP_ETHTYPE0 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
+#define GET_RXTRAP_ETHTYPE1 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
+#define GET_RXTRAP_ETHTYPE0 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
+#define GET_TX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0xffffffff ) >> 0)
+#define GET_RX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0xffffffff ) >> 0)
+#define GET_HOST_CMD_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0x000000ff ) >> 0)
+#define GET_HOST_EVENT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0x000000ff ) >> 0)
+#define GET_TX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0x000000ff ) >> 0)
+#define GET_RX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0x000000ff ) >> 0)
+#define GET_TX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0x000000ff ) >> 0)
+#define GET_RX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0x000000ff ) >> 0)
+#define GET_HOST_TX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0x000000ff ) >> 0)
+#define GET_HOST_RX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0x000000ff ) >> 0)
+#define GET_HCI_STATE_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0xffffffff ) >> 0)
+#define GET_HCI_ST_TIMEOUT_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0xffffffff ) >> 0)
+#define GET_TX_ON_DEMAND_LENGTH (((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0xffffffff ) >> 0)
+#define GET_HCI_MONITOR_REG1 (((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0xffffffff ) >> 0)
+#define GET_HCI_MONITOR_REG2 (((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_TIME_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_TIME_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x0000ffff ) >> 0)
+#define GET_HCI_MB_MAX_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x00ff0000 ) >> 16)
+#define GET_HCI_TX_ALLOC_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x0000ffff ) >> 0)
+#define GET_HCI_PROC_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ff0000 ) >> 16)
+#define GET_SDIO_TRANS_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff000000 ) >> 24)
+#define GET_SDIO_TX_INVALID_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0xffffffff ) >> 0)
+#define GET_SDIO_TX_INVALID_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0x0000ffff ) >> 0)
+#define GET_CS_START_ADDR (((REG32(ADR_CS_START_ADDR)) & 0x0000ffff ) >> 0)
+#define GET_CS_PKT_ID (((REG32(ADR_CS_START_ADDR)) & 0x007f0000 ) >> 16)
+#define GET_ADD_LEN (((REG32(ADR_CS_ADD_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CS_ADDER_EN (((REG32(ADR_CS_CMD)) & 0x00000001 ) >> 0)
+#define GET_PSEUDO (((REG32(ADR_CS_CMD)) & 0x00000002 ) >> 1)
+#define GET_CALCULATE (((REG32(ADR_CS_INI_BUF)) & 0xffffffff ) >> 0)
+#define GET_L4_LEN (((REG32(ADR_CS_PSEUDO_BUF)) & 0x0000ffff ) >> 0)
+#define GET_L4_PROTOL (((REG32(ADR_CS_PSEUDO_BUF)) & 0x00ff0000 ) >> 16)
+#define GET_CHECK_SUM (((REG32(ADR_CS_CHECK_SUM)) & 0x0000ffff ) >> 0)
+#define GET_RAND_EN (((REG32(ADR_RAND_EN)) & 0x00000001 ) >> 0)
+#define GET_RAND_NUM (((REG32(ADR_RAND_NUM)) & 0xffffffff ) >> 0)
+#define GET_MUL_OP1 (((REG32(ADR_MUL_OP1)) & 0xffffffff ) >> 0)
+#define GET_MUL_OP2 (((REG32(ADR_MUL_OP2)) & 0xffffffff ) >> 0)
+#define GET_MUL_ANS0 (((REG32(ADR_MUL_ANS0)) & 0xffffffff ) >> 0)
+#define GET_MUL_ANS1 (((REG32(ADR_MUL_ANS1)) & 0xffffffff ) >> 0)
+#define GET_RD_ADDR (((REG32(ADR_DMA_RDATA)) & 0x0000ffff ) >> 0)
+#define GET_RD_ID (((REG32(ADR_DMA_RDATA)) & 0x007f0000 ) >> 16)
+#define GET_WR_ADDR (((REG32(ADR_DMA_WDATA)) & 0x0000ffff ) >> 0)
+#define GET_WR_ID (((REG32(ADR_DMA_WDATA)) & 0x007f0000 ) >> 16)
+#define GET_LEN (((REG32(ADR_DMA_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CLR (((REG32(ADR_DMA_CLR)) & 0x00000001 ) >> 0)
+#define GET_PHY_MODE (((REG32(ADR_NAV_DATA)) & 0x00000003 ) >> 0)
+#define GET_SHRT_PREAM (((REG32(ADR_NAV_DATA)) & 0x00000004 ) >> 2)
+#define GET_SHRT_GI (((REG32(ADR_NAV_DATA)) & 0x00000008 ) >> 3)
+#define GET_DATA_RATE (((REG32(ADR_NAV_DATA)) & 0x000007f0 ) >> 4)
+#define GET_MCS (((REG32(ADR_NAV_DATA)) & 0x00007000 ) >> 12)
+#define GET_FRAME_LEN (((REG32(ADR_NAV_DATA)) & 0xffff0000 ) >> 16)
+#define GET_DURATION (((REG32(ADR_CO_NAV)) & 0x0000ffff ) >> 0)
+#define GET_SHA_DST_ADDR (((REG32(ADR_SHA_DST_ADDR)) & 0xffffffff ) >> 0)
+#define GET_SHA_SRC_ADDR (((REG32(ADR_SHA_SRC_ADDR)) & 0xffffffff ) >> 0)
+#define GET_SHA_BUSY (((REG32(ADR_SHA_SETTING)) & 0x00000001 ) >> 0)
+#define GET_SHA_ENDIAN (((REG32(ADR_SHA_SETTING)) & 0x00000002 ) >> 1)
+#define GET_EFS_CLKFREQ (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00000fff ) >> 0)
+#define GET_LOW_ACTIVE (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00010000 ) >> 16)
+#define GET_EFS_CLKFREQ_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0ff00000 ) >> 20)
+#define GET_EFS_PRE_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf0000000 ) >> 28)
+#define GET_EFS_LDO_ON (((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff ) >> 0)
+#define GET_EFS_LDO_OFF (((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000 ) >> 16)
+#define GET_EFS_RDATA_0 (((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_0 (((REG32(ADR_EFUSE_WDATA_0)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_1 (((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_1 (((REG32(ADR_EFUSE_WDATA_1)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_2 (((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_2 (((REG32(ADR_EFUSE_WDATA_2)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_3 (((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_3 (((REG32(ADR_EFUSE_WDATA_3)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_4 (((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_4 (((REG32(ADR_EFUSE_WDATA_4)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_5 (((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_5 (((REG32(ADR_EFUSE_WDATA_5)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_6 (((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_6 (((REG32(ADR_EFUSE_WDATA_6)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_7 (((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_7 (((REG32(ADR_EFUSE_WDATA_7)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RD0_EN (((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD1_EN (((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD2_EN (((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD3_EN (((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD4_EN (((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD5_EN (((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD6_EN (((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD7_EN (((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RBUSY (((REG32(ADR_EFUSE_SPI_BUSY)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RDATA_0 (((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_1 (((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_2 (((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_3 (((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_4 (((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_5 (((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_6 (((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_7 (((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0xffffffff ) >> 0)
+#define GET_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000001 ) >> 0)
+#define GET_FORCE_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000002 ) >> 1)
+#define GET_SMS4_DESCRY_EN (((REG32(ADR_SMS4_CFG1)) & 0x00000010 ) >> 4)
+#define GET_DEC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000001 ) >> 0)
+#define GET_DEC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000002 ) >> 1)
+#define GET_ENC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000004 ) >> 2)
+#define GET_ENC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000008 ) >> 3)
+#define GET_KEY_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000010 ) >> 4)
+#define GET_SMS4_CBC_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000001 ) >> 0)
+#define GET_SMS4_CFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000002 ) >> 1)
+#define GET_SMS4_OFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000004 ) >> 2)
+#define GET_SMS4_START_TRIG (((REG32(ADR_SMS4_TRIG)) & 0x00000001 ) >> 0)
+#define GET_SMS4_BUSY (((REG32(ADR_SMS4_STATUS1)) & 0x00000001 ) >> 0)
+#define GET_SMS4_DONE (((REG32(ADR_SMS4_STATUS2)) & 0x00000001 ) >> 0)
+#define GET_SMS4_DATAIN_0 (((REG32(ADR_SMS4_DATA_IN0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAIN_1 (((REG32(ADR_SMS4_DATA_IN1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAIN_2 (((REG32(ADR_SMS4_DATA_IN2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAIN_3 (((REG32(ADR_SMS4_DATA_IN3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_0 (((REG32(ADR_SMS4_DATA_OUT0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_1 (((REG32(ADR_SMS4_DATA_OUT1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_2 (((REG32(ADR_SMS4_DATA_OUT2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_3 (((REG32(ADR_SMS4_DATA_OUT3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_0 (((REG32(ADR_SMS4_KEY_0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_1 (((REG32(ADR_SMS4_KEY_1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_2 (((REG32(ADR_SMS4_KEY_2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_3 (((REG32(ADR_SMS4_KEY_3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV0 (((REG32(ADR_SMS4_MODE_IV0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV1 (((REG32(ADR_SMS4_MODE_IV1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV2 (((REG32(ADR_SMS4_MODE_IV2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV3 (((REG32(ADR_SMS4_MODE_IV3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC0 (((REG32(ADR_SMS4_OFB_ENC0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC1 (((REG32(ADR_SMS4_OFB_ENC1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC2 (((REG32(ADR_SMS4_OFB_ENC2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC3 (((REG32(ADR_SMS4_OFB_ENC3)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB0_31_0 (((REG32(ADR_MRX_MCAST_TB0_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB0_47_32 (((REG32(ADR_MRX_MCAST_TB0_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK0_31_0 (((REG32(ADR_MRX_MCAST_MK0_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK0_47_32 (((REG32(ADR_MRX_MCAST_MK0_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_0 (((REG32(ADR_MRX_MCAST_CTRL0)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB1_31_0 (((REG32(ADR_MRX_MCAST_TB1_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB1_47_32 (((REG32(ADR_MRX_MCAST_TB1_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK1_31_0 (((REG32(ADR_MRX_MCAST_MK1_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK1_47_32 (((REG32(ADR_MRX_MCAST_MK1_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_1 (((REG32(ADR_MRX_MCAST_CTRL1)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB2_31_0 (((REG32(ADR_MRX_MCAST_TB2_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB2_47_32 (((REG32(ADR_MRX_MCAST_TB2_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK2_31_0 (((REG32(ADR_MRX_MCAST_MK2_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK2_47_32 (((REG32(ADR_MRX_MCAST_MK2_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_2 (((REG32(ADR_MRX_MCAST_CTRL2)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB3_31_0 (((REG32(ADR_MRX_MCAST_TB3_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB3_47_32 (((REG32(ADR_MRX_MCAST_TB3_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK3_31_0 (((REG32(ADR_MRX_MCAST_MK3_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK3_47_32 (((REG32(ADR_MRX_MCAST_MK3_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_3 (((REG32(ADR_MRX_MCAST_CTRL3)) & 0x00000003 ) >> 0)
+#define GET_MRX_PHY_INFO (((REG32(ADR_MRX_PHY_INFO)) & 0xffffffff ) >> 0)
+#define GET_DBG_BA_TYPE (((REG32(ADR_MRX_BA_DBG)) & 0x0000003f ) >> 0)
+#define GET_DBG_BA_SEQ (((REG32(ADR_MRX_BA_DBG)) & 0x000fff00 ) >> 8)
+#define GET_MRX_FLT_TB0 (((REG32(ADR_MRX_FLT_TB0)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB1 (((REG32(ADR_MRX_FLT_TB1)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB2 (((REG32(ADR_MRX_FLT_TB2)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB3 (((REG32(ADR_MRX_FLT_TB3)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB4 (((REG32(ADR_MRX_FLT_TB4)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB5 (((REG32(ADR_MRX_FLT_TB5)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB6 (((REG32(ADR_MRX_FLT_TB6)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB7 (((REG32(ADR_MRX_FLT_TB7)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB8 (((REG32(ADR_MRX_FLT_TB8)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB9 (((REG32(ADR_MRX_FLT_TB9)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB10 (((REG32(ADR_MRX_FLT_TB10)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB11 (((REG32(ADR_MRX_FLT_TB11)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB12 (((REG32(ADR_MRX_FLT_TB12)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB13 (((REG32(ADR_MRX_FLT_TB13)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB14 (((REG32(ADR_MRX_FLT_TB14)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB15 (((REG32(ADR_MRX_FLT_TB15)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_EN0 (((REG32(ADR_MRX_FLT_EN0)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN1 (((REG32(ADR_MRX_FLT_EN1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN2 (((REG32(ADR_MRX_FLT_EN2)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN3 (((REG32(ADR_MRX_FLT_EN3)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN4 (((REG32(ADR_MRX_FLT_EN4)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN5 (((REG32(ADR_MRX_FLT_EN5)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN6 (((REG32(ADR_MRX_FLT_EN6)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN7 (((REG32(ADR_MRX_FLT_EN7)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN8 (((REG32(ADR_MRX_FLT_EN8)) & 0x0000ffff ) >> 0)
+#define GET_MRX_LEN_FLT (((REG32(ADR_MRX_LEN_FLT)) & 0x0000ffff ) >> 0)
+#define GET_RX_FLOW_DATA (((REG32(ADR_RX_FLOW_DATA)) & 0xffffffff ) >> 0)
+#define GET_RX_FLOW_MNG (((REG32(ADR_RX_FLOW_MNG)) & 0x0000ffff ) >> 0)
+#define GET_RX_FLOW_CTRL (((REG32(ADR_RX_FLOW_CTRL)) & 0x0000ffff ) >> 0)
+#define GET_MRX_STP_EN (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x00000001 ) >> 0)
+#define GET_MRX_STP_OFST (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x0000ff00 ) >> 8)
+#define GET_DBG_FF_FULL (((REG32(ADR_DBG_FF_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_FF_FULL_CLR (((REG32(ADR_DBG_FF_FULL)) & 0x80000000 ) >> 31)
+#define GET_DBG_WFF_FULL (((REG32(ADR_DBG_WFF_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_WFF_FULL_CLR (((REG32(ADR_DBG_WFF_FULL)) & 0x80000000 ) >> 31)
+#define GET_DBG_MB_FULL (((REG32(ADR_DBG_MB_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_MB_FULL_CLR (((REG32(ADR_DBG_MB_FULL)) & 0x80000000 ) >> 31)
+#define GET_BA_CTRL (((REG32(ADR_BA_CTRL)) & 0x00000003 ) >> 0)
+#define GET_BA_DBG_EN (((REG32(ADR_BA_CTRL)) & 0x00000004 ) >> 2)
+#define GET_BA_AGRE_EN (((REG32(ADR_BA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_BA_TA_31_0 (((REG32(ADR_BA_TA_0)) & 0xffffffff ) >> 0)
+#define GET_BA_TA_47_32 (((REG32(ADR_BA_TA_1)) & 0x0000ffff ) >> 0)
+#define GET_BA_TID (((REG32(ADR_BA_TID)) & 0x0000000f ) >> 0)
+#define GET_BA_ST_SEQ (((REG32(ADR_BA_ST_SEQ)) & 0x00000fff ) >> 0)
+#define GET_BA_SB0 (((REG32(ADR_BA_SB0)) & 0xffffffff ) >> 0)
+#define GET_BA_SB1 (((REG32(ADR_BA_SB1)) & 0xffffffff ) >> 0)
+#define GET_MRX_WD (((REG32(ADR_MRX_WATCH_DOG)) & 0x0001ffff ) >> 0)
+#define GET_ACK_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000001 ) >> 0)
+#define GET_BA_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000002 ) >> 1)
+#define GET_ACK_GEN_DUR (((REG32(ADR_ACK_GEN_PARA)) & 0x0000ffff ) >> 0)
+#define GET_ACK_GEN_INFO (((REG32(ADR_ACK_GEN_PARA)) & 0x003f0000 ) >> 16)
+#define GET_ACK_GEN_RA_31_0 (((REG32(ADR_ACK_GEN_RA_0)) & 0xffffffff ) >> 0)
+#define GET_ACK_GEN_RA_47_32 (((REG32(ADR_ACK_GEN_RA_1)) & 0x0000ffff ) >> 0)
+#define GET_MIB_LEN_FAIL (((REG32(ADR_MIB_LEN_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_TRAP_HW_ID (((REG32(ADR_TRAP_HW_ID)) & 0x0000000f ) >> 0)
+#define GET_ID_IN_USE (((REG32(ADR_ID_IN_USE)) & 0x000000ff ) >> 0)
+#define GET_MRX_ERR (((REG32(ADR_MRX_ERR)) & 0xffffffff ) >> 0)
+#define GET_W0_T0_SEQ (((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T1_SEQ (((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T2_SEQ (((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T3_SEQ (((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T4_SEQ (((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T5_SEQ (((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T6_SEQ (((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T7_SEQ (((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T0_SEQ (((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T1_SEQ (((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T2_SEQ (((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T3_SEQ (((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T4_SEQ (((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T5_SEQ (((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T6_SEQ (((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T7_SEQ (((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_ADDR1A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000003 ) >> 0)
+#define GET_ADDR2A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x0000000c ) >> 2)
+#define GET_ADDR3A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000030 ) >> 4)
+#define GET_ADDR1B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x000000c0 ) >> 6)
+#define GET_ADDR2B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000300 ) >> 8)
+#define GET_ADDR3B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000c00 ) >> 10)
+#define GET_ADDR3C_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00003000 ) >> 12)
+#define GET_FRM_CTRL (((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0x0000003f ) >> 0)
+#define GET_CSR_PHY_INFO (((REG32(ADR_PHY_INFO)) & 0x00007fff ) >> 0)
+#define GET_AMPDU_SIG (((REG32(ADR_AMPDU_SIG)) & 0x000000ff ) >> 0)
+#define GET_MIB_AMPDU (((REG32(ADR_MIB_AMPDU)) & 0xffffffff ) >> 0)
+#define GET_LEN_FLT (((REG32(ADR_LEN_FLT)) & 0x0000ffff ) >> 0)
+#define GET_MIB_DELIMITER (((REG32(ADR_MIB_DELIMITER)) & 0x0000ffff ) >> 0)
+#define GET_MTX_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00010000 ) >> 16)
+#define GET_MTX_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00020000 ) >> 17)
+#define GET_MTX_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00040000 ) >> 18)
+#define GET_MTX_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00080000 ) >> 19)
+#define GET_MTX_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00100000 ) >> 20)
+#define GET_MTX_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00200000 ) >> 21)
+#define GET_MTX_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00400000 ) >> 22)
+#define GET_MTX_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00800000 ) >> 23)
+#define GET_MTX_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x01000000 ) >> 24)
+#define GET_MTX_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x02000000 ) >> 25)
+#define GET_MTX_EN_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00010000 ) >> 16)
+#define GET_MTX_EN_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00020000 ) >> 17)
+#define GET_MTX_EN_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00040000 ) >> 18)
+#define GET_MTX_EN_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00080000 ) >> 19)
+#define GET_MTX_EN_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00100000 ) >> 20)
+#define GET_MTX_EN_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00200000 ) >> 21)
+#define GET_MTX_EN_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00400000 ) >> 22)
+#define GET_MTX_EN_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00800000 ) >> 23)
+#define GET_MTX_EN_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x01000000 ) >> 24)
+#define GET_MTX_EN_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x02000000 ) >> 25)
+#define GET_MTX_MTX2PHY_SLOW (((REG32(ADR_MTX_MISC_EN)) & 0x00000001 ) >> 0)
+#define GET_MTX_M2M_SLOW_PRD (((REG32(ADR_MTX_MISC_EN)) & 0x0000000e ) >> 1)
+#define GET_MTX_AMPDU_CRC_AUTO (((REG32(ADR_MTX_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_MTX_FAST_RSP_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000040 ) >> 6)
+#define GET_MTX_RAW_DATA_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000080 ) >> 7)
+#define GET_MTX_ACK_DUR0 (((REG32(ADR_MTX_MISC_EN)) & 0x00000100 ) >> 8)
+#define GET_MTX_TSF_AUTO_BCN (((REG32(ADR_MTX_MISC_EN)) & 0x00000400 ) >> 10)
+#define GET_MTX_TSF_AUTO_MISC (((REG32(ADR_MTX_MISC_EN)) & 0x00000800 ) >> 11)
+#define GET_MTX_FORCE_CS_IDLE (((REG32(ADR_MTX_MISC_EN)) & 0x00001000 ) >> 12)
+#define GET_MTX_FORCE_BKF_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00002000 ) >> 13)
+#define GET_MTX_FORCE_DMA_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00004000 ) >> 14)
+#define GET_MTX_FORCE_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00008000 ) >> 15)
+#define GET_MTX_HALT_Q_MB (((REG32(ADR_MTX_MISC_EN)) & 0x003f0000 ) >> 16)
+#define GET_MTX_CTS_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00400000 ) >> 22)
+#define GET_MTX_AMPDU_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00800000 ) >> 23)
+#define GET_MTX_EDCCA_TOUT (((REG32(ADR_MTX_EDCCA_TOUT)) & 0x000003ff ) >> 0)
+#define GET_MTX_INT_BCN (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000002 ) >> 1)
+#define GET_MTX_INT_DTIM (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000008 ) >> 3)
+#define GET_MTX_EN_INT_BCN (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000002 ) >> 1)
+#define GET_MTX_EN_INT_DTIM (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000008 ) >> 3)
+#define GET_MTX_BCN_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000001 ) >> 0)
+#define GET_MTX_TIME_STAMP_AUTO_FILL (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000002 ) >> 1)
+#define GET_MTX_TSF_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000020 ) >> 5)
+#define GET_MTX_HALT_MNG_UNTIL_DTIM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000040 ) >> 6)
+#define GET_MTX_INT_DTIM_NUM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_AUTO_FLUSH_Q4 (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00010000 ) >> 16)
+#define GET_MTX_BCN_PKTID_CH_LOCK (((REG32(ADR_MTX_BCN_MISC)) & 0x00000001 ) >> 0)
+#define GET_MTX_BCN_CFG_VLD (((REG32(ADR_MTX_BCN_MISC)) & 0x00000006 ) >> 1)
+#define GET_MTX_AUTO_BCN_ONGOING (((REG32(ADR_MTX_BCN_MISC)) & 0x00000008 ) >> 3)
+#define GET_MTX_BCN_TIMER (((REG32(ADR_MTX_BCN_MISC)) & 0xffff0000 ) >> 16)
+#define GET_MTX_BCN_PERIOD (((REG32(ADR_MTX_BCN_PRD)) & 0x0000ffff ) >> 0)
+#define GET_MTX_DTIM_NUM (((REG32(ADR_MTX_BCN_PRD)) & 0xff000000 ) >> 24)
+#define GET_MTX_BCN_TSF_L (((REG32(ADR_MTX_BCN_TSF_L)) & 0xffffffff ) >> 0)
+#define GET_MTX_BCN_TSF_U (((REG32(ADR_MTX_BCN_TSF_U)) & 0xffffffff ) >> 0)
+#define GET_MTX_BCN_PKT_ID0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x0000007f ) >> 0)
+#define GET_MTX_DTIM_OFST0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x03ff0000 ) >> 16)
+#define GET_MTX_BCN_PKT_ID1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x0000007f ) >> 0)
+#define GET_MTX_DTIM_OFST1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x03ff0000 ) >> 16)
+#define GET_MTX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000001 ) >> 0)
+#define GET_MRX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000002 ) >> 1)
+#define GET_MTX_DMA_FSM (((REG32(ADR_MTX_STATUS)) & 0x0000001c ) >> 2)
+#define GET_CH_ST_FSM (((REG32(ADR_MTX_STATUS)) & 0x000000e0 ) >> 5)
+#define GET_MTX_GNT_LOCK (((REG32(ADR_MTX_STATUS)) & 0x00000100 ) >> 8)
+#define GET_MTX_DMA_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000200 ) >> 9)
+#define GET_MTX_Q_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000400 ) >> 10)
+#define GET_MTX_TX_EN (((REG32(ADR_MTX_STATUS)) & 0x00000800 ) >> 11)
+#define GET_MRX_RX_EN (((REG32(ADR_MTX_STATUS)) & 0x00001000 ) >> 12)
+#define GET_DBG_PRTC_PRD (((REG32(ADR_MTX_STATUS)) & 0x00002000 ) >> 13)
+#define GET_DBG_DMA_RDY (((REG32(ADR_MTX_STATUS)) & 0x00004000 ) >> 14)
+#define GET_DBG_WAIT_RSP (((REG32(ADR_MTX_STATUS)) & 0x00008000 ) >> 15)
+#define GET_DBG_CFRM_BUSY (((REG32(ADR_MTX_STATUS)) & 0x00010000 ) >> 16)
+#define GET_DBG_RST (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000001 ) >> 0)
+#define GET_DBG_MODE (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000002 ) >> 1)
+#define GET_MB_REQ_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff ) >> 0)
+#define GET_RX_EN_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000 ) >> 16)
+#define GET_RX_CS_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff ) >> 0)
+#define GET_TX_CCA_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000 ) >> 16)
+#define GET_Q_REQ_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff ) >> 0)
+#define GET_CH_STA0_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000 ) >> 16)
+#define GET_MTX_DUR_RSP_TOUT_B (((REG32(ADR_MTX_DUR_TOUT)) & 0x000000ff ) >> 0)
+#define GET_MTX_DUR_RSP_TOUT_G (((REG32(ADR_MTX_DUR_TOUT)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DUR_RSP_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x000000ff ) >> 0)
+#define GET_MTX_DUR_BURST_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DUR_SLOT (((REG32(ADR_MTX_DUR_IFS)) & 0x003f0000 ) >> 16)
+#define GET_MTX_DUR_RSP_EIFS (((REG32(ADR_MTX_DUR_IFS)) & 0xffc00000 ) >> 22)
+#define GET_MTX_DUR_RSP_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x000000ff ) >> 0)
+#define GET_MTX_DUR_BURST_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DUR_SLOT_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003f0000 ) >> 16)
+#define GET_MTX_DUR_RSP_EIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc00000 ) >> 22)
+#define GET_CH_STA1_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff ) >> 0)
+#define GET_CH_STA2_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000 ) >> 16)
+#define GET_MTX_NAV (((REG32(ADR_MTX_NAV)) & 0x0000ffff ) >> 0)
+#define GET_MTX_MIB_CNT0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x3fffffff ) >> 0)
+#define GET_MTX_MIB_EN0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x40000000 ) >> 30)
+#define GET_MTX_MIB_CNT1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x3fffffff ) >> 0)
+#define GET_MTX_MIB_EN1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x40000000 ) >> 30)
+#define GET_CH_STA3_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff ) >> 0)
+#define GET_CH_STA4_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000 ) >> 16)
+#define GET_TXQ0_MTX_Q_PRE_LD (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ0_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ0_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ0_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ0_MTX_Q_RND_MODE (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ0_MTX_Q_AIFSN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ0_MTX_Q_ECWMIN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ0_MTX_Q_ECWMAX (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ0_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ0_MTX_Q_BKF_CNT (((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ0_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ0_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ0_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ0_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ0_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_MTX_Q_PRE_LD (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ1_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ1_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ1_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ1_MTX_Q_RND_MODE (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ1_MTX_Q_AIFSN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ1_MTX_Q_ECWMIN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ1_MTX_Q_ECWMAX (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ1_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ1_MTX_Q_BKF_CNT (((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ1_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ1_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ1_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_MTX_Q_PRE_LD (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ2_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ2_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ2_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ2_MTX_Q_RND_MODE (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ2_MTX_Q_AIFSN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ2_MTX_Q_ECWMIN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ2_MTX_Q_ECWMAX (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ2_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ2_MTX_Q_BKF_CNT (((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ2_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ2_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ2_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_MTX_Q_PRE_LD (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ3_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ3_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ3_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ3_MTX_Q_RND_MODE (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ3_MTX_Q_AIFSN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ3_MTX_Q_ECWMIN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ3_MTX_Q_ECWMAX (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ3_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ3_MTX_Q_BKF_CNT (((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ3_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ3_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ3_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_MTX_Q_PRE_LD (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ4_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ4_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ4_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ4_MTX_Q_RND_MODE (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ4_MTX_Q_AIFSN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ4_MTX_Q_ECWMIN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ4_MTX_Q_ECWMAX (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ4_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ4_MTX_Q_BKF_CNT (((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ4_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ4_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ4_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_VALID0 (((REG32(ADR_WSID0)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN0 (((REG32(ADR_WSID0)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE0 (((REG32(ADR_WSID0)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE0 (((REG32(ADR_WSID0)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC0_31_0 (((REG32(ADR_PEER_MAC0_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC0_47_32 (((REG32(ADR_PEER_MAC0_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_0_0 (((REG32(ADR_TX_ACK_POLICY_0_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_0 (((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_1 (((REG32(ADR_TX_ACK_POLICY_0_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_1 (((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_2 (((REG32(ADR_TX_ACK_POLICY_0_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_2 (((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_3 (((REG32(ADR_TX_ACK_POLICY_0_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_3 (((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_4 (((REG32(ADR_TX_ACK_POLICY_0_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_4 (((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_5 (((REG32(ADR_TX_ACK_POLICY_0_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_5 (((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_6 (((REG32(ADR_TX_ACK_POLICY_0_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_6 (((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_7 (((REG32(ADR_TX_ACK_POLICY_0_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_7 (((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0x00000fff ) >> 0)
+#define GET_VALID1 (((REG32(ADR_WSID1)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN1 (((REG32(ADR_WSID1)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE1 (((REG32(ADR_WSID1)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE1 (((REG32(ADR_WSID1)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC1_31_0 (((REG32(ADR_PEER_MAC1_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC1_47_32 (((REG32(ADR_PEER_MAC1_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_1_0 (((REG32(ADR_TX_ACK_POLICY_1_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_0 (((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_1 (((REG32(ADR_TX_ACK_POLICY_1_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_1 (((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_2 (((REG32(ADR_TX_ACK_POLICY_1_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_2 (((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_3 (((REG32(ADR_TX_ACK_POLICY_1_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_3 (((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_4 (((REG32(ADR_TX_ACK_POLICY_1_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_4 (((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_5 (((REG32(ADR_TX_ACK_POLICY_1_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_5 (((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_6 (((REG32(ADR_TX_ACK_POLICY_1_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_6 (((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_7 (((REG32(ADR_TX_ACK_POLICY_1_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_7 (((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0x00000fff ) >> 0)
+#define GET_INFO0 (((REG32(ADR_INFO0)) & 0xffffffff ) >> 0)
+#define GET_INFO1 (((REG32(ADR_INFO1)) & 0xffffffff ) >> 0)
+#define GET_INFO2 (((REG32(ADR_INFO2)) & 0xffffffff ) >> 0)
+#define GET_INFO3 (((REG32(ADR_INFO3)) & 0xffffffff ) >> 0)
+#define GET_INFO4 (((REG32(ADR_INFO4)) & 0xffffffff ) >> 0)
+#define GET_INFO5 (((REG32(ADR_INFO5)) & 0xffffffff ) >> 0)
+#define GET_INFO6 (((REG32(ADR_INFO6)) & 0xffffffff ) >> 0)
+#define GET_INFO7 (((REG32(ADR_INFO7)) & 0xffffffff ) >> 0)
+#define GET_INFO8 (((REG32(ADR_INFO8)) & 0xffffffff ) >> 0)
+#define GET_INFO9 (((REG32(ADR_INFO9)) & 0xffffffff ) >> 0)
+#define GET_INFO10 (((REG32(ADR_INFO10)) & 0xffffffff ) >> 0)
+#define GET_INFO11 (((REG32(ADR_INFO11)) & 0xffffffff ) >> 0)
+#define GET_INFO12 (((REG32(ADR_INFO12)) & 0xffffffff ) >> 0)
+#define GET_INFO13 (((REG32(ADR_INFO13)) & 0xffffffff ) >> 0)
+#define GET_INFO14 (((REG32(ADR_INFO14)) & 0xffffffff ) >> 0)
+#define GET_INFO15 (((REG32(ADR_INFO15)) & 0xffffffff ) >> 0)
+#define GET_INFO16 (((REG32(ADR_INFO16)) & 0xffffffff ) >> 0)
+#define GET_INFO17 (((REG32(ADR_INFO17)) & 0xffffffff ) >> 0)
+#define GET_INFO18 (((REG32(ADR_INFO18)) & 0xffffffff ) >> 0)
+#define GET_INFO19 (((REG32(ADR_INFO19)) & 0xffffffff ) >> 0)
+#define GET_INFO20 (((REG32(ADR_INFO20)) & 0xffffffff ) >> 0)
+#define GET_INFO21 (((REG32(ADR_INFO21)) & 0xffffffff ) >> 0)
+#define GET_INFO22 (((REG32(ADR_INFO22)) & 0xffffffff ) >> 0)
+#define GET_INFO23 (((REG32(ADR_INFO23)) & 0xffffffff ) >> 0)
+#define GET_INFO24 (((REG32(ADR_INFO24)) & 0xffffffff ) >> 0)
+#define GET_INFO25 (((REG32(ADR_INFO25)) & 0xffffffff ) >> 0)
+#define GET_INFO26 (((REG32(ADR_INFO26)) & 0xffffffff ) >> 0)
+#define GET_INFO27 (((REG32(ADR_INFO27)) & 0xffffffff ) >> 0)
+#define GET_INFO28 (((REG32(ADR_INFO28)) & 0xffffffff ) >> 0)
+#define GET_INFO29 (((REG32(ADR_INFO29)) & 0xffffffff ) >> 0)
+#define GET_INFO30 (((REG32(ADR_INFO30)) & 0xffffffff ) >> 0)
+#define GET_INFO31 (((REG32(ADR_INFO31)) & 0xffffffff ) >> 0)
+#define GET_INFO32 (((REG32(ADR_INFO32)) & 0xffffffff ) >> 0)
+#define GET_INFO33 (((REG32(ADR_INFO33)) & 0xffffffff ) >> 0)
+#define GET_INFO34 (((REG32(ADR_INFO34)) & 0xffffffff ) >> 0)
+#define GET_INFO35 (((REG32(ADR_INFO35)) & 0xffffffff ) >> 0)
+#define GET_INFO36 (((REG32(ADR_INFO36)) & 0xffffffff ) >> 0)
+#define GET_INFO37 (((REG32(ADR_INFO37)) & 0xffffffff ) >> 0)
+#define GET_INFO38 (((REG32(ADR_INFO38)) & 0xffffffff ) >> 0)
+#define GET_INFO_MASK (((REG32(ADR_INFO_MASK)) & 0xffffffff ) >> 0)
+#define GET_INFO_DEF_RATE (((REG32(ADR_INFO_RATE_OFFSET)) & 0x0000003f ) >> 0)
+#define GET_INFO_MRX_OFFSET (((REG32(ADR_INFO_RATE_OFFSET)) & 0x000f0000 ) >> 16)
+#define GET_BCAST_RATEUNKNOW (((REG32(ADR_INFO_RATE_OFFSET)) & 0x3f000000 ) >> 24)
+#define GET_INFO_IDX_TBL_ADDR (((REG32(ADR_INFO_IDX_ADDR)) & 0xffffffff ) >> 0)
+#define GET_INFO_LEN_TBL_ADDR (((REG32(ADR_INFO_LEN_ADDR)) & 0xffffffff ) >> 0)
+#define GET_IC_TAG_31_0 (((REG32(ADR_IC_TIME_TAG_0)) & 0xffffffff ) >> 0)
+#define GET_IC_TAG_63_32 (((REG32(ADR_IC_TIME_TAG_1)) & 0xffffffff ) >> 0)
+#define GET_CH1_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000003 ) >> 0)
+#define GET_CH2_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000300 ) >> 8)
+#define GET_CH3_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00030000 ) >> 16)
+#define GET_RG_MAC_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000001 ) >> 0)
+#define GET_RG_MAC_M2M (((REG32(ADR_MAC_MODE)) & 0x00000002 ) >> 1)
+#define GET_RG_PHY_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000004 ) >> 2)
+#define GET_RG_LPBK_RX_EN (((REG32(ADR_MAC_MODE)) & 0x00000008 ) >> 3)
+#define GET_EXT_MAC_MODE (((REG32(ADR_MAC_MODE)) & 0x00000010 ) >> 4)
+#define GET_EXT_PHY_MODE (((REG32(ADR_MAC_MODE)) & 0x00000020 ) >> 5)
+#define GET_ASIC_TAG (((REG32(ADR_MAC_MODE)) & 0xff000000 ) >> 24)
+#define GET_HCI_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_CHST_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_BCN_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MRX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_AMPDU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_MMU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
+#define GET_MBOX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00001000 ) >> 12)
+#define GET_SCRT_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
+#define GET_MIC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_CO_PROC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_CHST_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_BCN_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MRX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_AMPDU_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_ID_MNG_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_MBOX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
+#define GET_SCRT_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00010000 ) >> 16)
+#define GET_MIC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00020000 ) >> 17)
+#define GET_CO_PROC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE0_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_QUE1_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_QUE2_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MTX_QUE3_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_MTX_QUE4_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_MTX_QUE5_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
+#define GET_MRX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000400 ) >> 10)
+#define GET_AMPDU_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
+#define GET_SCRT_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
+#define GET_ID_MNG_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_MBOX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
+#define GET_HCI_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_MRX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_AMPDU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_MMU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
+#define GET_ID_MNG_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
+#define GET_MBOX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_SCRT_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_MIC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_MIB_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_HCI_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_MRX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_AMPDU_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_ID_MNG_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_MBOX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_SCRT_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_MIC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_CO_PROC_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MRX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_AMPDU_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_SCRT_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_ID_MNG_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_MBOX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_OP_MODE (((REG32(ADR_GLBLE_SET)) & 0x00000003 ) >> 0)
+#define GET_HT_MODE (((REG32(ADR_GLBLE_SET)) & 0x0000000c ) >> 2)
+#define GET_QOS_EN (((REG32(ADR_GLBLE_SET)) & 0x00000010 ) >> 4)
+#define GET_PB_OFFSET (((REG32(ADR_GLBLE_SET)) & 0x0000ff00 ) >> 8)
+#define GET_SNIFFER_MODE (((REG32(ADR_GLBLE_SET)) & 0x00010000 ) >> 16)
+#define GET_DUP_FLT (((REG32(ADR_GLBLE_SET)) & 0x00020000 ) >> 17)
+#define GET_TX_PKT_RSVD (((REG32(ADR_GLBLE_SET)) & 0x001c0000 ) >> 18)
+#define GET_AMPDU_SNIFFER (((REG32(ADR_GLBLE_SET)) & 0x00200000 ) >> 21)
+#define GET_REASON_TRAP0 (((REG32(ADR_REASON_TRAP0)) & 0xffffffff ) >> 0)
+#define GET_REASON_TRAP1 (((REG32(ADR_REASON_TRAP1)) & 0xffffffff ) >> 0)
+#define GET_BSSID_31_0 (((REG32(ADR_BSSID_0)) & 0xffffffff ) >> 0)
+#define GET_BSSID_47_32 (((REG32(ADR_BSSID_1)) & 0x0000ffff ) >> 0)
+#define GET_SCRT_STATE (((REG32(ADR_SCRT_STATE)) & 0x0000000f ) >> 0)
+#define GET_STA_MAC_31_0 (((REG32(ADR_STA_MAC_0)) & 0xffffffff ) >> 0)
+#define GET_STA_MAC_47_32 (((REG32(ADR_STA_MAC_1)) & 0x0000ffff ) >> 0)
+#define GET_PAIR_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000007 ) >> 0)
+#define GET_GRP_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000038 ) >> 3)
+#define GET_SCRT_PKT_ID (((REG32(ADR_SCRT_SET)) & 0x00001fc0 ) >> 6)
+#define GET_SCRT_RPLY_IGNORE (((REG32(ADR_SCRT_SET)) & 0x00010000 ) >> 16)
+#define GET_COEXIST_EN (((REG32(ADR_BTCX0)) & 0x00000001 ) >> 0)
+#define GET_WIRE_MODE (((REG32(ADR_BTCX0)) & 0x0000000e ) >> 1)
+#define GET_WL_RX_PRI (((REG32(ADR_BTCX0)) & 0x00000010 ) >> 4)
+#define GET_WL_TX_PRI (((REG32(ADR_BTCX0)) & 0x00000020 ) >> 5)
+#define GET_GURAN_USE_EN (((REG32(ADR_BTCX0)) & 0x00000100 ) >> 8)
+#define GET_GURAN_USE_CTRL (((REG32(ADR_BTCX0)) & 0x00000200 ) >> 9)
+#define GET_BEACON_TIMEOUT_EN (((REG32(ADR_BTCX0)) & 0x00000400 ) >> 10)
+#define GET_WLAN_ACT_POL (((REG32(ADR_BTCX0)) & 0x00000800 ) >> 11)
+#define GET_DUAL_ANT_EN (((REG32(ADR_BTCX0)) & 0x00001000 ) >> 12)
+#define GET_TRSW_PHY_POL (((REG32(ADR_BTCX0)) & 0x00010000 ) >> 16)
+#define GET_WIFI_TX_SW_POL (((REG32(ADR_BTCX0)) & 0x00020000 ) >> 17)
+#define GET_WIFI_RX_SW_POL (((REG32(ADR_BTCX0)) & 0x00040000 ) >> 18)
+#define GET_BT_SW_POL (((REG32(ADR_BTCX0)) & 0x00080000 ) >> 19)
+#define GET_BT_PRI_SMP_TIME (((REG32(ADR_BTCX1)) & 0x000000ff ) >> 0)
+#define GET_BT_STA_SMP_TIME (((REG32(ADR_BTCX1)) & 0x0000ff00 ) >> 8)
+#define GET_BEACON_TIMEOUT (((REG32(ADR_BTCX1)) & 0x00ff0000 ) >> 16)
+#define GET_WLAN_REMAIN_TIME (((REG32(ADR_BTCX1)) & 0xff000000 ) >> 24)
+#define GET_SW_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000001 ) >> 0)
+#define GET_SW_WL_TX (((REG32(ADR_SWITCH_CTL)) & 0x00000002 ) >> 1)
+#define GET_SW_WL_RX (((REG32(ADR_SWITCH_CTL)) & 0x00000004 ) >> 2)
+#define GET_SW_BT_TRX (((REG32(ADR_SWITCH_CTL)) & 0x00000008 ) >> 3)
+#define GET_BT_TXBAR_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000010 ) >> 4)
+#define GET_BT_TXBAR_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000020 ) >> 5)
+#define GET_BT_BUSY_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000100 ) >> 8)
+#define GET_BT_BUSY_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000200 ) >> 9)
+#define GET_G0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000004 ) >> 2)
+#define GET_G0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000008 ) >> 3)
+#define GET_G1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000010 ) >> 4)
+#define GET_G1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000020 ) >> 5)
+#define GET_Q0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000040 ) >> 6)
+#define GET_Q0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000080 ) >> 7)
+#define GET_Q1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000100 ) >> 8)
+#define GET_Q1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000200 ) >> 9)
+#define GET_Q2_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000400 ) >> 10)
+#define GET_Q2_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000800 ) >> 11)
+#define GET_Q3_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00001000 ) >> 12)
+#define GET_Q3_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00002000 ) >> 13)
+#define GET_SCRT_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00004000 ) >> 14)
+#define GET_SCRT_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00008000 ) >> 15)
+#define GET_MISC_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00010000 ) >> 16)
+#define GET_MISC_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00020000 ) >> 17)
+#define GET_MTX_WSID0_SUCC (((REG32(ADR_MTX_WSID0_SUCC)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_FRM (((REG32(ADR_MTX_WSID0_FRM)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_RETRY (((REG32(ADR_MTX_WSID0_RETRY)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_TOTAL (((REG32(ADR_MTX_WSID0_TOTAL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_GRP (((REG32(ADR_MTX_GROUP)) & 0x000fffff ) >> 0)
+#define GET_MTX_FAIL (((REG32(ADR_MTX_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RETRY (((REG32(ADR_MTX_RETRY)) & 0x000fffff ) >> 0)
+#define GET_MTX_MULTI_RETRY (((REG32(ADR_MTX_MULTI_RETRY)) & 0x000fffff ) >> 0)
+#define GET_MTX_RTS_SUCC (((REG32(ADR_MTX_RTS_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RTS_FAIL (((REG32(ADR_MTX_RTS_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_ACK_FAIL (((REG32(ADR_MTX_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_FRM (((REG32(ADR_MTX_FRM)) & 0x000fffff ) >> 0)
+#define GET_MTX_ACK_TX (((REG32(ADR_MTX_ACK_TX)) & 0x0000ffff ) >> 0)
+#define GET_MTX_CTS_TX (((REG32(ADR_MTX_CTS_TX)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DUP (((REG32(ADR_MRX_DUP_FRM)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FRG (((REG32(ADR_MRX_FRG_FRM)) & 0x000fffff ) >> 0)
+#define GET_MRX_GRP (((REG32(ADR_MRX_GROUP_FRM)) & 0x000fffff ) >> 0)
+#define GET_MRX_FCS_ERR (((REG32(ADR_MRX_FCS_ERR)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FCS_SUC (((REG32(ADR_MRX_FCS_SUCC)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MISS (((REG32(ADR_MRX_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_ALC_FAIL (((REG32(ADR_MRX_ALC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DAT_NTF (((REG32(ADR_MRX_DAT_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_RTS_NTF (((REG32(ADR_MRX_RTS_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_CTS_NTF (((REG32(ADR_MRX_CTS_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_ACK_NTF (((REG32(ADR_MRX_ACK_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_BA_NTF (((REG32(ADR_MRX_BA_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DATA_NTF (((REG32(ADR_MRX_DATA_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MNG_NTF (((REG32(ADR_MRX_MNG_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DAT_CRC_NTF (((REG32(ADR_MRX_DAT_CRC_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_BAR_NTF (((REG32(ADR_MRX_BAR_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MB_MISS (((REG32(ADR_MRX_MB_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_NIDLE_MISS (((REG32(ADR_MRX_NIDLE_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_CSR_NTF (((REG32(ADR_MRX_CSR_NTF)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_SUCC (((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_FAIL (((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_ACK_SUCC (((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_ACK_FAIL (((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_SUCC (((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_FAIL (((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_ACK_SUCC (((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_ACK_FAIL (((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_SUCC (((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_FAIL (((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_ACK_SUCC (((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_ACK_FAIL (((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_SUCC (((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_FAIL (((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_ACK_SUCC (((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_ACK_FAIL (((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_SCRT_TKIP_CERR (((REG32(ADR_MIB_SCRT_TKIP0)) & 0x000fffff ) >> 0)
+#define GET_SCRT_TKIP_MIC_ERR (((REG32(ADR_MIB_SCRT_TKIP1)) & 0x000fffff ) >> 0)
+#define GET_SCRT_TKIP_RPLY (((REG32(ADR_MIB_SCRT_TKIP2)) & 0x000fffff ) >> 0)
+#define GET_SCRT_CCMP_RPLY (((REG32(ADR_MIB_SCRT_CCMP0)) & 0x000fffff ) >> 0)
+#define GET_SCRT_CCMP_CERR (((REG32(ADR_MIB_SCRT_CCMP1)) & 0x000fffff ) >> 0)
+#define GET_DBG_LEN_CRC_FAIL (((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_LEN_ALC_FAIL (((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_AMPDU_PASS (((REG32(ADR_DBG_AMPDU_PASS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_AMPDU_FAIL (((REG32(ADR_DBG_AMPDU_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_RXID_ALC_CNT_FAIL (((REG32(ADR_ID_ALC_FAIL1)) & 0x0000ffff ) >> 0)
+#define GET_RXID_ALC_LEN_FAIL (((REG32(ADR_ID_ALC_FAIL2)) & 0x0000ffff ) >> 0)
+#define GET_CBR_RG_EN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_TX_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_TX_PA_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_TX_DAC_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_RX_AGC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_RX_GAIN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_RFG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_CBR_RG_PGAG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_CBR_RG_MODE (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_CBR_RG_EN_TX_TRSW (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_EN_SX (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_CBR_RG_EN_RX_LNA (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_CBR_RG_EN_RX_MIXER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_CBR_RG_EN_RX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_CBR_RG_EN_RX_LOBUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_CBR_RG_EN_RX_TZ (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_EN_RX_FILTER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_EN_RX_HPF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_EN_RX_RSSI (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_CBR_RG_EN_ADC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_CBR_RG_EN_TX_MOD (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_EN_TX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_CBR_RG_EN_TX_DIV2_BUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_CBR_RG_EN_TX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_CBR_RG_EN_RX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_CBR_RG_SEL_DPLL_CLK (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_CBR_RG_EN_TX_DPD (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_EN_TX_TSSI (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_EN_RX_IQCAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_EN_TX_DAC_CAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_EN_TX_SELF_MIXER (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_EN_TX_DAC_OUT (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_EN_LDO_RX_FE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_CBR_RG_EN_LDO_ABB (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_CBR_RG_EN_LDO_AFE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_EN_SX_CHPLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_EN_SX_LOBFLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_EN_IREF_RX (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_DCDC_MODE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_CBR_RG_LDO_LEVEL_RX_FE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_CBR_RG_LDO_LEVEL_ABB (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000038 ) >> 3)
+#define GET_CBR_RG_LDO_LEVEL_AFE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
+#define GET_CBR_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
+#define GET_CBR_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_CBR_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_CBR_RG_DP_LDO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_CBR_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
+#define GET_CBR_RG_TX_LDO_TX_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_CBR_RG_BUCK_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x38000000 ) >> 27)
+#define GET_CBR_RG_EN_RX_PADSW (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_EN_RX_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_RX_ABBCFIX (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_RX_ABBCTUNE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
+#define GET_CBR_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_RX_ABB_N_MODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_RX_EN_LOOPA (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_RX_FILTERI1ST (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
+#define GET_CBR_RG_RX_FILTERI2ND (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_FILTERI3RD (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
+#define GET_CBR_RG_RX_FILTERI_COURSE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
+#define GET_CBR_RG_RX_FILTERVCM (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
+#define GET_CBR_RG_RX_HPF3M (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_RX_HPF300K (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
+#define GET_CBR_RG_RX_HPFI (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
+#define GET_CBR_RG_RX_HPF_FINALCORNER (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
+#define GET_CBR_RG_RX_HPF_SETTLE1_C (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
+#define GET_CBR_RG_RX_HPF_SETTLE1_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_HPF_SETTLE2_C (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
+#define GET_CBR_RG_RX_HPF_SETTLE2_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_RX_HPF_VCMCON2 (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
+#define GET_CBR_RG_RX_HPF_VCMCON (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
+#define GET_CBR_RG_RX_OUTVCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
+#define GET_CBR_RG_RX_TZI (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
+#define GET_CBR_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_RX_TZ_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
+#define GET_CBR_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
+#define GET_CBR_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_RX_ADCRSSI_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
+#define GET_CBR_RG_RX_REC_LPFCORNER (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
+#define GET_CBR_RG_RSSI_CLOCK_GATING (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_TXPGA_CAPSW (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_TXPGA_MAIN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
+#define GET_CBR_RG_TXPGA_STEER (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
+#define GET_CBR_RG_TXMOD_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_TXLPF_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_CBR_RG_PACELL_EN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_CBR_RG_PABIAS_CTRL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
+#define GET_CBR_RG_PABIAS_AB (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_TX_DIV_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_CBR_RG_TX_LOBUF_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_CBR_RG_RX_SQDC (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
+#define GET_CBR_RG_RX_DIV2_CORE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_RX_LOBUF (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
+#define GET_CBR_RG_TX_DPDGM_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
+#define GET_CBR_RG_TX_DPD_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
+#define GET_CBR_RG_TX_TSSI_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
+#define GET_CBR_RG_TX_TSSI_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
+#define GET_CBR_RG_TX_TSSI_TESTMODE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_TX_TSSI_TEST (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
+#define GET_CBR_RG_RX_HG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_HG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_HG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_HG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_RX_MG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_MG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_MG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_MG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_RX_LG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_LG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_LG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_LG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_RX_ULG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_ULG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_ULG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_HPF1_FAST_SET_X (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_HPF1_FAST_SET_Y (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_HPF1_FAST_SET_Z (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_HPF_T1A (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_HPF_T1B (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000060 ) >> 5)
+#define GET_CBR_RG_HPF_T1C (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000180 ) >> 7)
+#define GET_CBR_RG_RX_LNA_TRI_SEL (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_CBR_RG_RX_LNA_SETTLE (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00001800 ) >> 11)
+#define GET_CBR_RG_ADC_CLKSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_ADC_DIBIAS (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_ADC_DIVR (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_ADC_DVCMI (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_ADC_SAMSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_ADC_STNBY (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_ADC_TESTMODE (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_ADC_TSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_CBR_RG_ADC_VRSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_CBR_RG_DICMP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_CBR_RG_DIOP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_CBR_RG_DACI1ST (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_TX_DACLPF_ICOURSE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_CBR_RG_TX_DACLPF_IFINE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_TX_DACLPF_VCM (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_CBR_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_TX_DAC_IBIAS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_CBR_RG_TX_DAC_OS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
+#define GET_CBR_RG_TX_DAC_RCAL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_TX_DAC_TSEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
+#define GET_CBR_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_TXLPF_BYPASS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_TXLPF_BOOSTI (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_EN_SX_R3 (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_EN_SX_CH (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_EN_SX_CHP (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_EN_SX_DIVCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_EN_SX_VCOBF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_EN_SX_VCO (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_EN_SX_MOD (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000040 ) >> 6)
+#define GET_CBR_RG_EN_SX_LCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000080 ) >> 7)
+#define GET_CBR_RG_EN_SX_DITHER (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_EN_SX_DELCAL (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_EN_SX_PC_BYPASS (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_EN_SX_VT_MON (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_EN_SX_VT_MON_DG (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00001000 ) >> 12)
+#define GET_CBR_RG_EN_SX_DIV (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00002000 ) >> 13)
+#define GET_CBR_RG_EN_SX_LPF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_SX_RFCTRL_F (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x00ffffff ) >> 0)
+#define GET_CBR_RG_SX_SEL_CP (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0f000000 ) >> 24)
+#define GET_CBR_RG_SX_SEL_CS (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0000000 ) >> 28)
+#define GET_CBR_RG_SX_RFCTRL_CH (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000007ff ) >> 0)
+#define GET_CBR_RG_SX_SEL_C3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x00007800 ) >> 11)
+#define GET_CBR_RG_SX_SEL_RS (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000f8000 ) >> 15)
+#define GET_CBR_RG_SX_SEL_R3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x01f00000 ) >> 20)
+#define GET_CBR_RG_SX_SEL_ICHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
+#define GET_CBR_RG_SX_SEL_PCHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
+#define GET_CBR_RG_SX_SEL_CHP_REGOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
+#define GET_CBR_RG_SX_CHP_IOST_POL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
+#define GET_CBR_RG_SX_CHP_IOST (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
+#define GET_CBR_RG_SX_PFDSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_SX_PFD_SET (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
+#define GET_CBR_RG_SX_PFD_SET1 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
+#define GET_CBR_RG_SX_PFD_SET2 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_SX_VBNCAS_SEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
+#define GET_CBR_RG_SX_PFD_RST_H (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
+#define GET_CBR_RG_SX_PFD_TRUP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
+#define GET_CBR_RG_SX_PFD_TRDN (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
+#define GET_CBR_RG_SX_PFD_TRSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
+#define GET_CBR_RG_SX_VCOBA_R (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
+#define GET_CBR_RG_SX_VCORSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
+#define GET_CBR_RG_SX_VCOCUSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
+#define GET_CBR_RG_SX_RXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
+#define GET_CBR_RG_SX_TXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
+#define GET_CBR_RG_SX_VCOBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
+#define GET_CBR_RG_SX_DIVBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
+#define GET_CBR_RG_SX_GNDR_SEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
+#define GET_CBR_RG_SX_DITHER_WEIGHT (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_SX_MOD_ERRCMP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0000000c ) >> 2)
+#define GET_CBR_RG_SX_MOD_ORDER (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_SX_SDM_D1 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000040 ) >> 6)
+#define GET_CBR_RG_SX_SDM_D2 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000080 ) >> 7)
+#define GET_CBR_RG_SDM_PASS (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_SX_RST_H_DIV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_SX_SDM_EDGE (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_SX_XO_GM (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
+#define GET_CBR_RG_SX_REFBYTWO (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
+#define GET_CBR_RG_SX_XO_SWCAP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0003c000 ) >> 14)
+#define GET_CBR_RG_SX_SDMLUT_INV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00040000 ) >> 18)
+#define GET_CBR_RG_SX_LCKEN (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
+#define GET_CBR_RG_SX_PREVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
+#define GET_CBR_RG_SX_PSCONTERVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
+#define GET_CBR_RG_SX_MOD_ERR_DELAY (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x30000000 ) >> 28)
+#define GET_CBR_RG_SX_MODDB (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x40000000 ) >> 30)
+#define GET_CBR_RG_SX_CV_CURVE_SEL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_SX_SEL_DELAY (((REG32(ADR_CBR_SYN_LCK1)) & 0x0000007c ) >> 2)
+#define GET_CBR_RG_SX_REF_CYCLE (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000780 ) >> 7)
+#define GET_CBR_RG_SX_VCOBY16 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_SX_VCOBY32 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00001000 ) >> 12)
+#define GET_CBR_RG_SX_PH (((REG32(ADR_CBR_SYN_LCK1)) & 0x00002000 ) >> 13)
+#define GET_CBR_RG_SX_PL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_SX_VT_MON_MODE (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_SX_VT_TH_HI (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_SX_VT_TH_LO (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_SX_VT_SET (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_SX_VT_MON_TMR (((REG32(ADR_CBR_SYN_LCK2)) & 0x00007fc0 ) >> 6)
+#define GET_CBR_RG_IDEAL_CYCLE (((REG32(ADR_CBR_SYN_LCK2)) & 0x0fff8000 ) >> 15)
+#define GET_CBR_RG_EN_DP_VT_MON (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_DP_VT_TH_HI (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_DP_VT_TH_LO (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_DP_VT_MON_TMR (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00003fe0 ) >> 5)
+#define GET_CBR_RG_DP_CK320BY2 (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_SX_DELCTRL (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x001f8000 ) >> 15)
+#define GET_CBR_RG_DP_OD_TEST (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_DP_BBPLL_BP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_DP_BBPLL_ICP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_DP_BBPLL_IDUAL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_DP_BBPLL_OD_TEST (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
+#define GET_CBR_RG_DP_BBPLL_PD (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_DP_BBPLL_TESTSEL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
+#define GET_CBR_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
+#define GET_CBR_RG_DP_RP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_CBR_RG_DP_RHP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_CBR_RG_DP_DR3 (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_CBR_RG_DP_DCP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x07800000 ) >> 23)
+#define GET_CBR_RG_DP_DCS (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x78000000 ) >> 27)
+#define GET_CBR_RG_DP_FBDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x00000fff ) >> 0)
+#define GET_CBR_RG_DP_FODIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003ff000 ) >> 12)
+#define GET_CBR_RG_DP_REFDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00000 ) >> 22)
+#define GET_CBR_RG_IDACAI_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_EN_RCAL (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_RCAL_SPD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_RCAL_TMR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
+#define GET_CBR_RG_RCAL_CODE_CWR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_RCAL_CODE_CWD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
+#define GET_CBR_RG_SX_SUB_SEL_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_SX_SUB_SEL_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x000000fe ) >> 1)
+#define GET_CBR_RG_DP_BBPLL_BS_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_DP_BBPLL_BS_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00007e00 ) >> 9)
+#define GET_CBR_RCAL_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
+#define GET_CBR_DA_LCK_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
+#define GET_CBR_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
+#define GET_CBR_DP_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000008 ) >> 3)
+#define GET_CBR_CH_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000010 ) >> 4)
+#define GET_CBR_DA_R_CODE_LUT (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
+#define GET_CBR_AD_SX_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
+#define GET_CBR_AD_DP_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
+#define GET_CBR_DA_R_CAL_CODE (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
+#define GET_CBR_DA_SX_SUB_SEL (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
+#define GET_CBR_DA_DP_BBPLL_BS (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0003f000 ) >> 12)
+#define GET_CBR_TX_EN (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000001 ) >> 0)
+#define GET_CBR_TX_CNT_RST (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000002 ) >> 1)
+#define GET_CBR_IFS_TIME (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000000fc ) >> 2)
+#define GET_CBR_LENGTH_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000fff00 ) >> 8)
+#define GET_CBR_TX_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xff000000 ) >> 24)
+#define GET_CBR_TC_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0x00ffffff ) >> 0)
+#define GET_CBR_PLCP_PSDU_DATA_MEM (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x000000ff ) >> 0)
+#define GET_CBR_PLCP_PSDU_PREAMBLE_SHORT (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00000100 ) >> 8)
+#define GET_CBR_PLCP_BYTE_LENGTH (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x001ffe00 ) >> 9)
+#define GET_CBR_PLCP_PSDU_RATE (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00600000 ) >> 21)
+#define GET_CBR_TAIL_TIME (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x1f800000 ) >> 23)
+#define GET_CBR_RG_O_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_I_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000002 ) >> 1)
+#define GET_CBR_SEL_ADCKP_INV (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_PAD_DS (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000008 ) >> 3)
+#define GET_CBR_SEL_ADCKP_MUX (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_PAD_DS_CLK (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000020 ) >> 5)
+#define GET_CBR_INTP_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000200 ) >> 9)
+#define GET_CBR_IQ_SWP (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_EN_EXT_DA (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_DIS_DA_OFFSET (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00001000 ) >> 12)
+#define GET_CBR_DBG_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x000f0000 ) >> 16)
+#define GET_CBR_DBG_EN (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_PKT_GEN_TX_CNT (((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0xffffffff ) >> 0)
+#define GET_CBR_TP_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x0000001f ) >> 0)
+#define GET_CBR_IDEAL_IQ_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000020 ) >> 5)
+#define GET_CBR_DATA_OUT_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x000001c0 ) >> 6)
+#define GET_CBR_TWO_TONE_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000200 ) >> 9)
+#define GET_CBR_FREQ_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ff0000 ) >> 16)
+#define GET_CBR_IQ_SCALE (((REG32(ADR_CBR_PATTERN_GEN)) & 0xff000000 ) >> 24)
+#define GET_CPU_QUE_POP (((REG32(ADR_MB_CPU_INT)) & 0x00000001 ) >> 0)
+#define GET_CPU_INT (((REG32(ADR_MB_CPU_INT)) & 0x00000004 ) >> 2)
+#define GET_CPU_ID_TB0 (((REG32(ADR_CPU_ID_TB0)) & 0xffffffff ) >> 0)
+#define GET_CPU_ID_TB1 (((REG32(ADR_CPU_ID_TB1)) & 0xffffffff ) >> 0)
+#define GET_HW_PKTID (((REG32(ADR_CH0_TRIG_1)) & 0x000007ff ) >> 0)
+#define GET_CH0_INT_ADDR (((REG32(ADR_CH0_TRIG_0)) & 0xffffffff ) >> 0)
+#define GET_PRI_HW_PKTID (((REG32(ADR_CH0_PRI_TRIG)) & 0x000007ff ) >> 0)
+#define GET_CH0_FULL (((REG32(ADR_MCU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_FF0_EMPTY (((REG32(ADR_MCU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_RLS_BUSY (((REG32(ADR_MCU_STATUS)) & 0x00000200 ) >> 9)
+#define GET_RLS_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000400 ) >> 10)
+#define GET_RTN_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000800 ) >> 11)
+#define GET_RLS_COUNT (((REG32(ADR_MCU_STATUS)) & 0x00ff0000 ) >> 16)
+#define GET_RTN_COUNT (((REG32(ADR_MCU_STATUS)) & 0xff000000 ) >> 24)
+#define GET_FF0_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x0000001f ) >> 0)
+#define GET_FF1_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000001e0 ) >> 5)
+#define GET_FF3_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00003800 ) >> 11)
+#define GET_FF5_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000e0000 ) >> 17)
+#define GET_FF6_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00700000 ) >> 20)
+#define GET_FF7_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x03800000 ) >> 23)
+#define GET_FF8_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x1c000000 ) >> 26)
+#define GET_FF9_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0xe0000000 ) >> 29)
+#define GET_FF10_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000007 ) >> 0)
+#define GET_FF11_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000038 ) >> 3)
+#define GET_FF12_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000001c0 ) >> 6)
+#define GET_FF13_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000600 ) >> 9)
+#define GET_FF14_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00001800 ) >> 11)
+#define GET_FF15_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00006000 ) >> 13)
+#define GET_FF4_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000f8000 ) >> 15)
+#define GET_FF2_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00700000 ) >> 20)
+#define GET_CH1_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000002 ) >> 1)
+#define GET_CH2_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000004 ) >> 2)
+#define GET_CH3_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000008 ) >> 3)
+#define GET_CH4_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000010 ) >> 4)
+#define GET_CH5_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000020 ) >> 5)
+#define GET_CH6_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000040 ) >> 6)
+#define GET_CH7_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000080 ) >> 7)
+#define GET_CH8_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000100 ) >> 8)
+#define GET_CH9_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000200 ) >> 9)
+#define GET_CH10_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000400 ) >> 10)
+#define GET_CH11_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000800 ) >> 11)
+#define GET_CH12_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00001000 ) >> 12)
+#define GET_CH13_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00002000 ) >> 13)
+#define GET_CH14_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00004000 ) >> 14)
+#define GET_CH15_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00008000 ) >> 15)
+#define GET_HALT_CH0 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000001 ) >> 0)
+#define GET_HALT_CH1 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000002 ) >> 1)
+#define GET_HALT_CH2 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000004 ) >> 2)
+#define GET_HALT_CH3 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000008 ) >> 3)
+#define GET_HALT_CH4 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000010 ) >> 4)
+#define GET_HALT_CH5 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000020 ) >> 5)
+#define GET_HALT_CH6 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000040 ) >> 6)
+#define GET_HALT_CH7 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000080 ) >> 7)
+#define GET_HALT_CH8 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000100 ) >> 8)
+#define GET_HALT_CH9 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000200 ) >> 9)
+#define GET_HALT_CH10 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000400 ) >> 10)
+#define GET_HALT_CH11 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000800 ) >> 11)
+#define GET_HALT_CH12 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00001000 ) >> 12)
+#define GET_HALT_CH13 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00002000 ) >> 13)
+#define GET_HALT_CH14 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00004000 ) >> 14)
+#define GET_HALT_CH15 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00008000 ) >> 15)
+#define GET_STOP_MBOX (((REG32(ADR_MBOX_HALT_CFG)) & 0x00010000 ) >> 16)
+#define GET_MB_ERR_AUTO_HALT_EN (((REG32(ADR_MBOX_HALT_CFG)) & 0x00100000 ) >> 20)
+#define GET_MB_EXCEPT_CLR (((REG32(ADR_MBOX_HALT_CFG)) & 0x00200000 ) >> 21)
+#define GET_MB_EXCEPT_CASE (((REG32(ADR_MBOX_HALT_CFG)) & 0xff000000 ) >> 24)
+#define GET_MB_DBG_TIME_STEP (((REG32(ADR_MB_DBG_CFG1)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TYPE (((REG32(ADR_MB_DBG_CFG1)) & 0x00030000 ) >> 16)
+#define GET_MB_DBG_CLR (((REG32(ADR_MB_DBG_CFG1)) & 0x00040000 ) >> 18)
+#define GET_DBG_ALC_LOG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x00080000 ) >> 19)
+#define GET_MB_DBG_COUNTER_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x01000000 ) >> 24)
+#define GET_MB_DBG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x80000000 ) >> 31)
+#define GET_MB_DBG_RECORD_CNT (((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff ) >> 0)
+#define GET_MB_DBG_LENGTH (((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000 ) >> 16)
+#define GET_MB_DBG_CFG_ADDR (((REG32(ADR_MB_DBG_CFG3)) & 0xffffffff ) >> 0)
+#define GET_DBG_HWID0_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000001 ) >> 0)
+#define GET_DBG_HWID1_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000002 ) >> 1)
+#define GET_DBG_HWID2_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000004 ) >> 2)
+#define GET_DBG_HWID3_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000008 ) >> 3)
+#define GET_DBG_HWID4_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000010 ) >> 4)
+#define GET_DBG_HWID5_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000020 ) >> 5)
+#define GET_DBG_HWID6_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000040 ) >> 6)
+#define GET_DBG_HWID7_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000080 ) >> 7)
+#define GET_DBG_HWID8_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000100 ) >> 8)
+#define GET_DBG_HWID9_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000200 ) >> 9)
+#define GET_DBG_HWID10_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000400 ) >> 10)
+#define GET_DBG_HWID11_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000800 ) >> 11)
+#define GET_DBG_HWID12_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00001000 ) >> 12)
+#define GET_DBG_HWID13_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00002000 ) >> 13)
+#define GET_DBG_HWID14_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00004000 ) >> 14)
+#define GET_DBG_HWID15_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00008000 ) >> 15)
+#define GET_DBG_HWID0_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00010000 ) >> 16)
+#define GET_DBG_HWID1_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00020000 ) >> 17)
+#define GET_DBG_HWID2_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00040000 ) >> 18)
+#define GET_DBG_HWID3_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00080000 ) >> 19)
+#define GET_DBG_HWID4_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00100000 ) >> 20)
+#define GET_DBG_HWID5_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00200000 ) >> 21)
+#define GET_DBG_HWID6_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00400000 ) >> 22)
+#define GET_DBG_HWID7_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00800000 ) >> 23)
+#define GET_DBG_HWID8_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x01000000 ) >> 24)
+#define GET_DBG_HWID9_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x02000000 ) >> 25)
+#define GET_DBG_HWID10_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x04000000 ) >> 26)
+#define GET_DBG_HWID11_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x08000000 ) >> 27)
+#define GET_DBG_HWID12_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x10000000 ) >> 28)
+#define GET_DBG_HWID13_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x20000000 ) >> 29)
+#define GET_DBG_HWID14_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x40000000 ) >> 30)
+#define GET_DBG_HWID15_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x80000000 ) >> 31)
+#define GET_MB_OUT_QUEUE_EN (((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0x00000002 ) >> 1)
+#define GET_CH0_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000001 ) >> 0)
+#define GET_CH1_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000002 ) >> 1)
+#define GET_CH2_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000004 ) >> 2)
+#define GET_CH3_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000008 ) >> 3)
+#define GET_CH4_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000010 ) >> 4)
+#define GET_CH5_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000020 ) >> 5)
+#define GET_CH6_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000040 ) >> 6)
+#define GET_CH7_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000080 ) >> 7)
+#define GET_CH8_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000100 ) >> 8)
+#define GET_CH9_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000200 ) >> 9)
+#define GET_CH10_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000400 ) >> 10)
+#define GET_CH11_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000800 ) >> 11)
+#define GET_CH12_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00001000 ) >> 12)
+#define GET_CH13_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00002000 ) >> 13)
+#define GET_CH14_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00004000 ) >> 14)
+#define GET_CH15_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00008000 ) >> 15)
+#define GET_FFO0_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0000001f ) >> 0)
+#define GET_FFO1_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000003e0 ) >> 5)
+#define GET_FFO2_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00000c00 ) >> 10)
+#define GET_FFO3_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000f8000 ) >> 15)
+#define GET_FFO4_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00300000 ) >> 20)
+#define GET_FFO5_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0e000000 ) >> 25)
+#define GET_FFO6_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x0000000f ) >> 0)
+#define GET_FFO7_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000003e0 ) >> 5)
+#define GET_FFO8_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00007c00 ) >> 10)
+#define GET_FFO9_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000f8000 ) >> 15)
+#define GET_FFO10_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00f00000 ) >> 20)
+#define GET_FFO11_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x3e000000 ) >> 25)
+#define GET_FFO12_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000007 ) >> 0)
+#define GET_FFO13_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000060 ) >> 5)
+#define GET_FFO14_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000c00 ) >> 10)
+#define GET_FFO15_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x001f8000 ) >> 15)
+#define GET_CH0_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000001 ) >> 0)
+#define GET_CH1_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000002 ) >> 1)
+#define GET_CH2_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000004 ) >> 2)
+#define GET_CH3_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000008 ) >> 3)
+#define GET_CH4_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000010 ) >> 4)
+#define GET_CH5_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000020 ) >> 5)
+#define GET_CH6_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000040 ) >> 6)
+#define GET_CH7_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000080 ) >> 7)
+#define GET_CH8_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000100 ) >> 8)
+#define GET_CH9_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000200 ) >> 9)
+#define GET_CH10_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000400 ) >> 10)
+#define GET_CH11_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000800 ) >> 11)
+#define GET_CH12_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00001000 ) >> 12)
+#define GET_CH13_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00002000 ) >> 13)
+#define GET_CH14_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00004000 ) >> 14)
+#define GET_CH15_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00008000 ) >> 15)
+#define GET_CH0_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000001 ) >> 0)
+#define GET_CH1_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000002 ) >> 1)
+#define GET_CH2_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000004 ) >> 2)
+#define GET_CH3_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000008 ) >> 3)
+#define GET_CH4_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000010 ) >> 4)
+#define GET_CH5_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000020 ) >> 5)
+#define GET_CH6_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000040 ) >> 6)
+#define GET_CH7_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000080 ) >> 7)
+#define GET_CH8_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000100 ) >> 8)
+#define GET_CH9_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000200 ) >> 9)
+#define GET_CH10_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000400 ) >> 10)
+#define GET_CH11_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000800 ) >> 11)
+#define GET_CH12_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00001000 ) >> 12)
+#define GET_CH13_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00002000 ) >> 13)
+#define GET_CH14_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00004000 ) >> 14)
+#define GET_CH15_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00008000 ) >> 15)
+#define GET_MB_LOW_THOLD_EN (((REG32(ADR_MB_THRESHOLD6)) & 0x80000000 ) >> 31)
+#define GET_CH0_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x0000001f ) >> 0)
+#define GET_CH1_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x00001f00 ) >> 8)
+#define GET_CH2_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x001f0000 ) >> 16)
+#define GET_CH3_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x1f000000 ) >> 24)
+#define GET_CH4_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x0000001f ) >> 0)
+#define GET_CH5_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x00001f00 ) >> 8)
+#define GET_CH6_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x001f0000 ) >> 16)
+#define GET_CH7_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x1f000000 ) >> 24)
+#define GET_CH8_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x0000001f ) >> 0)
+#define GET_CH9_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x00001f00 ) >> 8)
+#define GET_CH10_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x001f0000 ) >> 16)
+#define GET_CH11_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x1f000000 ) >> 24)
+#define GET_CH12_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x0000001f ) >> 0)
+#define GET_CH13_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x00001f00 ) >> 8)
+#define GET_CH14_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x001f0000 ) >> 16)
+#define GET_CH15_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x1f000000 ) >> 24)
+#define GET_TRASH_TIMEOUT_EN (((REG32(ADR_MB_TRASH_CFG)) & 0x00000001 ) >> 0)
+#define GET_TRASH_CAN_INT (((REG32(ADR_MB_TRASH_CFG)) & 0x00000002 ) >> 1)
+#define GET_TRASH_INT_ID (((REG32(ADR_MB_TRASH_CFG)) & 0x000007f0 ) >> 4)
+#define GET_TRASH_TIMEOUT (((REG32(ADR_MB_TRASH_CFG)) & 0x03ff0000 ) >> 16)
+#define GET_CH0_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000001 ) >> 0)
+#define GET_CH1_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000002 ) >> 1)
+#define GET_CH2_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000004 ) >> 2)
+#define GET_CH3_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000008 ) >> 3)
+#define GET_CH4_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000010 ) >> 4)
+#define GET_CH5_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000020 ) >> 5)
+#define GET_CH6_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000040 ) >> 6)
+#define GET_CH7_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000080 ) >> 7)
+#define GET_CH8_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000100 ) >> 8)
+#define GET_CH9_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000200 ) >> 9)
+#define GET_CH10_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000400 ) >> 10)
+#define GET_CH11_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000800 ) >> 11)
+#define GET_CH12_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00001000 ) >> 12)
+#define GET_CH13_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00002000 ) >> 13)
+#define GET_CH14_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00004000 ) >> 14)
+#define GET_CPU_ID_TB2 (((REG32(ADR_CPU_ID_TB2)) & 0xffffffff ) >> 0)
+#define GET_CPU_ID_TB3 (((REG32(ADR_CPU_ID_TB3)) & 0xffffffff ) >> 0)
+#define GET_IQ_LOG_EN (((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0x00000001 ) >> 0)
+#define GET_IQ_LOG_STOP_MODE (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000001 ) >> 0)
+#define GET_GPIO_STOP_EN (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000010 ) >> 4)
+#define GET_GPIO_STOP_POL (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000020 ) >> 5)
+#define GET_IQ_LOG_TIMER (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffff0000 ) >> 16)
+#define GET_IQ_LOG_LEN (((REG32(ADR_PHY_IQ_LOG_LEN)) & 0x0000ffff ) >> 0)
+#define GET_IQ_LOG_TAIL_ADR (((REG32(ADR_PHY_IQ_LOG_PTR)) & 0x0000ffff ) >> 0)
+#define GET_ALC_LENG (((REG32(ADR_WR_ALC)) & 0x0003ffff ) >> 0)
+#define GET_CH0_DYN_PRI (((REG32(ADR_WR_ALC)) & 0x00300000 ) >> 20)
+#define GET_MCU_PKTID (((REG32(ADR_GETID)) & 0xffffffff ) >> 0)
+#define GET_CH0_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000003 ) >> 0)
+#define GET_CH1_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000030 ) >> 4)
+#define GET_CH2_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000300 ) >> 8)
+#define GET_CH3_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00003000 ) >> 12)
+#define GET_ID_TB0 (((REG32(ADR_RD_ID0)) & 0xffffffff ) >> 0)
+#define GET_ID_TB1 (((REG32(ADR_RD_ID1)) & 0xffffffff ) >> 0)
+#define GET_ID_MNG_HALT (((REG32(ADR_IMD_CFG)) & 0x00000010 ) >> 4)
+#define GET_ID_MNG_ERR_HALT_EN (((REG32(ADR_IMD_CFG)) & 0x00000020 ) >> 5)
+#define GET_ID_EXCEPT_FLG_CLR (((REG32(ADR_IMD_CFG)) & 0x00000040 ) >> 6)
+#define GET_ID_EXCEPT_FLG (((REG32(ADR_IMD_CFG)) & 0x00000080 ) >> 7)
+#define GET_ID_FULL (((REG32(ADR_IMD_STA)) & 0x00000001 ) >> 0)
+#define GET_ID_MNG_BUSY (((REG32(ADR_IMD_STA)) & 0x00000002 ) >> 1)
+#define GET_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000004 ) >> 2)
+#define GET_CH0_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000010 ) >> 4)
+#define GET_CH1_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000020 ) >> 5)
+#define GET_CH2_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000040 ) >> 6)
+#define GET_CH3_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000080 ) >> 7)
+#define GET_REQ_LOCK_INT_EN (((REG32(ADR_IMD_STA)) & 0x00000100 ) >> 8)
+#define GET_REQ_LOCK_INT (((REG32(ADR_IMD_STA)) & 0x00000200 ) >> 9)
+#define GET_MCU_ALC_READY (((REG32(ADR_ALC_STA)) & 0x00000001 ) >> 0)
+#define GET_ALC_FAIL (((REG32(ADR_ALC_STA)) & 0x00000002 ) >> 1)
+#define GET_ALC_BUSY (((REG32(ADR_ALC_STA)) & 0x00000004 ) >> 2)
+#define GET_CH0_NVLD (((REG32(ADR_ALC_STA)) & 0x00000010 ) >> 4)
+#define GET_CH1_NVLD (((REG32(ADR_ALC_STA)) & 0x00000020 ) >> 5)
+#define GET_CH2_NVLD (((REG32(ADR_ALC_STA)) & 0x00000040 ) >> 6)
+#define GET_CH3_NVLD (((REG32(ADR_ALC_STA)) & 0x00000080 ) >> 7)
+#define GET_ALC_INT_ID (((REG32(ADR_ALC_STA)) & 0x00007f00 ) >> 8)
+#define GET_ALC_TIMEOUT (((REG32(ADR_ALC_STA)) & 0x03ff0000 ) >> 16)
+#define GET_ALC_TIMEOUT_INT_EN (((REG32(ADR_ALC_STA)) & 0x40000000 ) >> 30)
+#define GET_ALC_TIMEOUT_INT (((REG32(ADR_ALC_STA)) & 0x80000000 ) >> 31)
+#define GET_TX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x000000ff ) >> 0)
+#define GET_RX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x0000ff00 ) >> 8)
+#define GET_TX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000000ff ) >> 0)
+#define GET_RX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x0000ff00 ) >> 8)
+#define GET_ID_THOLD_RX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00010000 ) >> 16)
+#define GET_RX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000e0000 ) >> 17)
+#define GET_ID_THOLD_TX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00100000 ) >> 20)
+#define GET_TX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00e00000 ) >> 21)
+#define GET_ID_THOLD_INT_EN (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x01000000 ) >> 24)
+#define GET_TX_ID_TB0 (((REG32(ADR_TX_ID0)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB1 (((REG32(ADR_TX_ID1)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB0 (((REG32(ADR_RX_ID0)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB1 (((REG32(ADR_RX_ID1)) & 0xffffffff ) >> 0)
+#define GET_DOUBLE_RLS_INT_EN (((REG32(ADR_RTN_STA)) & 0x00000001 ) >> 0)
+#define GET_ID_DOUBLE_RLS_INT (((REG32(ADR_RTN_STA)) & 0x00000002 ) >> 1)
+#define GET_DOUBLE_RLS_ID (((REG32(ADR_RTN_STA)) & 0x00007f00 ) >> 8)
+#define GET_ID_LEN_THOLD_INT_EN (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000001 ) >> 0)
+#define GET_ALL_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000002 ) >> 1)
+#define GET_TX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000004 ) >> 2)
+#define GET_RX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000008 ) >> 3)
+#define GET_ID_TX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00001ff0 ) >> 4)
+#define GET_ID_RX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x003fe000 ) >> 13)
+#define GET_ID_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x7fc00000 ) >> 22)
+#define GET_ALL_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x0003fe00 ) >> 9)
+#define GET_RX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x07fc0000 ) >> 18)
+#define GET_CH_ARB_EN (((REG32(ADR_CH_ARB_PRI)) & 0x00000001 ) >> 0)
+#define GET_CH_PRI1 (((REG32(ADR_CH_ARB_PRI)) & 0x00000030 ) >> 4)
+#define GET_CH_PRI2 (((REG32(ADR_CH_ARB_PRI)) & 0x00000300 ) >> 8)
+#define GET_CH_PRI3 (((REG32(ADR_CH_ARB_PRI)) & 0x00003000 ) >> 12)
+#define GET_CH_PRI4 (((REG32(ADR_CH_ARB_PRI)) & 0x00030000 ) >> 16)
+#define GET_TX_ID_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0000007f ) >> 0)
+#define GET_TX_PAGE_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0001ff00 ) >> 8)
+#define GET_ID_PAGE_MAX_SIZE (((REG32(ADR_ID_INFO_STA)) & 0x000001ff ) >> 0)
+#define GET_TX_PAGE_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x000001ff ) >> 0)
+#define GET_TX_COUNT_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x00ff0000 ) >> 16)
+#define GET_TX_LIMIT_INT (((REG32(ADR_TX_LIMIT_INTR)) & 0x40000000 ) >> 30)
+#define GET_TX_LIMIT_INT_EN (((REG32(ADR_TX_LIMIT_INTR)) & 0x80000000 ) >> 31)
+#define GET_TX_PAGE_USE_7_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x000000ff ) >> 0)
+#define GET_TX_ID_USE_5_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x00003f00 ) >> 8)
+#define GET_EDCA0_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x0003c000 ) >> 14)
+#define GET_EDCA1_FFO_CNT_3_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x003c0000 ) >> 18)
+#define GET_EDCA2_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x07c00000 ) >> 22)
+#define GET_EDCA3_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0xf8000000 ) >> 27)
+#define GET_ID_TB2 (((REG32(ADR_RD_ID2)) & 0xffffffff ) >> 0)
+#define GET_ID_TB3 (((REG32(ADR_RD_ID3)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB2 (((REG32(ADR_TX_ID2)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB3 (((REG32(ADR_TX_ID3)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB2 (((REG32(ADR_RX_ID2)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB3 (((REG32(ADR_RX_ID3)) & 0xffffffff ) >> 0)
+#define GET_TX_PAGE_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA4_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x001e0000 ) >> 17)
+#define GET_TX_PAGE_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA1_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x03e00000 ) >> 21)
+#define GET_EDCA4_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x3c000000 ) >> 26)
+#define GET_TX_PAGE_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA2_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x003e0000 ) >> 17)
+#define GET_EDCA3_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x07c00000 ) >> 22)
+#define GET_TX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x000001ff ) >> 0)
+#define GET_RX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x01ff0000 ) >> 16)
+#define GET_MAX_ALL_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x000000ff ) >> 0)
+#define GET_MAX_TX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x0000ff00 ) >> 8)
+#define GET_MAX_RX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x00ff0000 ) >> 16)
+#define GET_MAX_ALL_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x000001ff ) >> 0)
+#define GET_MAX_TX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x0003fe00 ) >> 9)
+#define GET_MAX_RX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x07fc0000 ) >> 18)
+#define GET_RG_PMDLBK (((REG32(ADR_PHY_EN_0)) & 0x00000001 ) >> 0)
+#define GET_RG_RDYACK_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000006 ) >> 1)
+#define GET_RG_ADEDGE_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000008 ) >> 3)
+#define GET_RG_SIGN_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000010 ) >> 4)
+#define GET_RG_IQ_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000020 ) >> 5)
+#define GET_RG_Q_INV (((REG32(ADR_PHY_EN_0)) & 0x00000040 ) >> 6)
+#define GET_RG_I_INV (((REG32(ADR_PHY_EN_0)) & 0x00000080 ) >> 7)
+#define GET_RG_BYPASS_ACI (((REG32(ADR_PHY_EN_0)) & 0x00000100 ) >> 8)
+#define GET_RG_LBK_ANA_PATH (((REG32(ADR_PHY_EN_0)) & 0x00000200 ) >> 9)
+#define GET_RG_SPECTRUM_LEAKY_FACTOR (((REG32(ADR_PHY_EN_0)) & 0x00000c00 ) >> 10)
+#define GET_RG_SPECTRUM_BW (((REG32(ADR_PHY_EN_0)) & 0x00003000 ) >> 12)
+#define GET_RG_SPECTRUM_FREQ_MANUAL (((REG32(ADR_PHY_EN_0)) & 0x00004000 ) >> 14)
+#define GET_RG_SPECTRUM_EN (((REG32(ADR_PHY_EN_0)) & 0x00008000 ) >> 15)
+#define GET_RG_TXPWRLVL_SET (((REG32(ADR_PHY_EN_0)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TXPWRLVL_SEL (((REG32(ADR_PHY_EN_0)) & 0x01000000 ) >> 24)
+#define GET_RG_RF_BB_CLK_SEL (((REG32(ADR_PHY_EN_0)) & 0x80000000 ) >> 31)
+#define GET_RG_PHY_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000001 ) >> 0)
+#define GET_RG_PHYRX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000002 ) >> 1)
+#define GET_RG_PHYTX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000004 ) >> 2)
+#define GET_RG_PHY11GN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000008 ) >> 3)
+#define GET_RG_PHY11B_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000010 ) >> 4)
+#define GET_RG_PHYRXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000020 ) >> 5)
+#define GET_RG_PHYTXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000040 ) >> 6)
+#define GET_RG_PHY11BGN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000100 ) >> 8)
+#define GET_RG_FORCE_11GN_EN (((REG32(ADR_PHY_EN_1)) & 0x00001000 ) >> 12)
+#define GET_RG_FORCE_11B_EN (((REG32(ADR_PHY_EN_1)) & 0x00002000 ) >> 13)
+#define GET_RG_FFT_MEM_CLK_EN_RX (((REG32(ADR_PHY_EN_1)) & 0x00004000 ) >> 14)
+#define GET_RG_FFT_MEM_CLK_EN_TX (((REG32(ADR_PHY_EN_1)) & 0x00008000 ) >> 15)
+#define GET_RG_PHY_IQ_TRIG_SEL (((REG32(ADR_PHY_EN_1)) & 0x000f0000 ) >> 16)
+#define GET_RG_SPECTRUM_FREQ (((REG32(ADR_PHY_EN_1)) & 0x3ff00000 ) >> 20)
+#define GET_SVN_VERSION (((REG32(ADR_SVN_VERSION_REG)) & 0xffffffff ) >> 0)
+#define GET_RG_LENGTH (((REG32(ADR_PHY_PKT_GEN_0)) & 0x0000ffff ) >> 0)
+#define GET_RG_PKT_MODE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00070000 ) >> 16)
+#define GET_RG_CH_BW (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00380000 ) >> 19)
+#define GET_RG_PRM (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00400000 ) >> 22)
+#define GET_RG_SHORTGI (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00800000 ) >> 23)
+#define GET_RG_RATE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x7f000000 ) >> 24)
+#define GET_RG_L_LENGTH (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00000fff ) >> 0)
+#define GET_RG_L_RATE (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00007000 ) >> 12)
+#define GET_RG_SERVICE (((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff0000 ) >> 16)
+#define GET_RG_SMOOTHING (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000001 ) >> 0)
+#define GET_RG_NO_SOUND (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000002 ) >> 1)
+#define GET_RG_AGGREGATE (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000004 ) >> 2)
+#define GET_RG_STBC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000018 ) >> 3)
+#define GET_RG_FEC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000020 ) >> 5)
+#define GET_RG_N_ESS (((REG32(ADR_PHY_PKT_GEN_2)) & 0x000000c0 ) >> 6)
+#define GET_RG_TXPWRLVL (((REG32(ADR_PHY_PKT_GEN_2)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TX_START (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000001 ) >> 0)
+#define GET_RG_IFS_TIME (((REG32(ADR_PHY_PKT_GEN_3)) & 0x000000fc ) >> 2)
+#define GET_RG_CONTINUOUS_DATA (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000100 ) >> 8)
+#define GET_RG_DATA_SEL (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000600 ) >> 9)
+#define GET_RG_TX_D (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_CNT_TARGET (((REG32(ADR_PHY_PKT_GEN_4)) & 0xffffffff ) >> 0)
+#define GET_RG_FFT_IFFT_MODE (((REG32(ADR_PHY_REG_00)) & 0x000000c0 ) >> 6)
+#define GET_RG_DAC_DBG_MODE (((REG32(ADR_PHY_REG_00)) & 0x00000100 ) >> 8)
+#define GET_RG_DAC_SGN_SWAP (((REG32(ADR_PHY_REG_00)) & 0x00000200 ) >> 9)
+#define GET_RG_TXD_SEL (((REG32(ADR_PHY_REG_00)) & 0x00000c00 ) >> 10)
+#define GET_RG_UP8X (((REG32(ADR_PHY_REG_00)) & 0x00ff0000 ) >> 16)
+#define GET_RG_IQ_DC_BYP (((REG32(ADR_PHY_REG_00)) & 0x01000000 ) >> 24)
+#define GET_RG_IQ_DC_LEAKY_FACTOR (((REG32(ADR_PHY_REG_00)) & 0x30000000 ) >> 28)
+#define GET_RG_DAC_DCEN (((REG32(ADR_PHY_REG_01)) & 0x00000001 ) >> 0)
+#define GET_RG_DAC_DCQ (((REG32(ADR_PHY_REG_01)) & 0x00003ff0 ) >> 4)
+#define GET_RG_DAC_DCI (((REG32(ADR_PHY_REG_01)) & 0x03ff0000 ) >> 16)
+#define GET_RG_PGA_REFDB_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0x0000007f ) >> 0)
+#define GET_RG_PGA_REFDB_TOP (((REG32(ADR_PHY_REG_02_AGC)) & 0x00007f00 ) >> 8)
+#define GET_RG_PGA_REF_UND (((REG32(ADR_PHY_REG_02_AGC)) & 0x03ff0000 ) >> 16)
+#define GET_RG_RF_REF_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0xf0000000 ) >> 28)
+#define GET_RG_PGAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x0000000f ) >> 0)
+#define GET_RG_PGAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000010 ) >> 4)
+#define GET_RG_RFGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000060 ) >> 5)
+#define GET_RG_RFGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000080 ) >> 7)
+#define GET_RG_WAIT_T_RXAGC (((REG32(ADR_PHY_REG_03_AGC)) & 0x00003f00 ) >> 8)
+#define GET_RG_RXAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00004000 ) >> 14)
+#define GET_RG_RXAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00008000 ) >> 15)
+#define GET_RG_WAIT_T_FINAL (((REG32(ADR_PHY_REG_03_AGC)) & 0x003f0000 ) >> 16)
+#define GET_RG_WAIT_T (((REG32(ADR_PHY_REG_03_AGC)) & 0x3f000000 ) >> 24)
+#define GET_RG_ULG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000000f ) >> 0)
+#define GET_RG_LG_PGA_UND_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000000f0 ) >> 4)
+#define GET_RG_LG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00000f00 ) >> 8)
+#define GET_RG_LG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000f000 ) >> 12)
+#define GET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000f0000 ) >> 16)
+#define GET_RG_HG_PGA_SAT2_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00f00000 ) >> 20)
+#define GET_RG_HG_PGA_SAT1_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0f000000 ) >> 24)
+#define GET_RG_HG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0xf0000000 ) >> 28)
+#define GET_RG_MG_PGA_JB_TH (((REG32(ADR_PHY_REG_05_AGC)) & 0x0000000f ) >> 0)
+#define GET_RG_MA_PGA_LOW_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x001f0000 ) >> 16)
+#define GET_RG_WR_RFGC_INIT_SET (((REG32(ADR_PHY_REG_05_AGC)) & 0x00600000 ) >> 21)
+#define GET_RG_WR_RFGC_INIT_EN (((REG32(ADR_PHY_REG_05_AGC)) & 0x00800000 ) >> 23)
+#define GET_RG_MA_PGA_HIGH_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x1f000000 ) >> 24)
+#define GET_RG_AGC_THRESHOLD (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x00003fff ) >> 0)
+#define GET_RG_ACI_POINT_CNT_LMT_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x007f0000 ) >> 16)
+#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x03000000 ) >> 24)
+#define GET_RG_WR_ACI_GAIN_INI_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x000000ff ) >> 0)
+#define GET_RG_WR_ACI_GAIN_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x0000ff00 ) >> 8)
+#define GET_RG_ACI_DAGC_SET_VALUE_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x007f0000 ) >> 16)
+#define GET_RG_WR_ACI_GAIN_OW_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x80000000 ) >> 31)
+#define GET_RG_ACI_POINT_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x000000ff ) >> 0)
+#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00000300 ) >> 8)
+#define GET_RG_ACI_DAGC_DONE_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xff000000 ) >> 24)
+#define GET_RG_ACI_DAGC_SET_VALUE_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000007f ) >> 0)
+#define GET_RG_ACI_GAIN_INI_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000ff00 ) >> 8)
+#define GET_RG_ACI_GAIN_OW_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x00ff0000 ) >> 16)
+#define GET_RG_ACI_GAIN_OW_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x80000000 ) >> 31)
+#define GET_RO_CCA_PWR_MA_11GN (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x0000007f ) >> 0)
+#define GET_RO_ED_STATE (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x00008000 ) >> 15)
+#define GET_RO_CCA_PWR_MA_11B (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x007f0000 ) >> 16)
+#define GET_RO_PGA_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
+#define GET_RO_PGA_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
+#define GET_RO_PGA_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
+#define GET_RG_TX_DES_RATE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_DES_MODE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_DES_LEN_LO (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_DES_LEN_UP (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x1f000000 ) >> 24)
+#define GET_RG_TX_DES_SRVC_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_DES_TYPE (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x1f000000 ) >> 24)
+#define GET_RG_TX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000010 ) >> 4)
+#define GET_RG_TX_DES_RATE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000100 ) >> 8)
+#define GET_RG_TX_DES_MODE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00001000 ) >> 12)
+#define GET_RG_TX_DES_PWRLVL (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_DES_SRVC_LO (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x1f000000 ) >> 24)
+#define GET_RG_RX_DES_RATE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x0000003f ) >> 0)
+#define GET_RG_RX_DES_MODE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x00003f00 ) >> 8)
+#define GET_RG_RX_DES_LEN_LO (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x003f0000 ) >> 16)
+#define GET_RG_RX_DES_LEN_UP (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x3f000000 ) >> 24)
+#define GET_RG_RX_DES_SRVC_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x0000003f ) >> 0)
+#define GET_RG_RX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x00003f00 ) >> 8)
+#define GET_RG_RX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x003f0000 ) >> 16)
+#define GET_RG_RX_DES_TYPE (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x3f000000 ) >> 24)
+#define GET_RG_RX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000001 ) >> 0)
+#define GET_RG_RX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000010 ) >> 4)
+#define GET_RG_RX_DES_RATE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000100 ) >> 8)
+#define GET_RG_RX_DES_MODE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00001000 ) >> 12)
+#define GET_RG_RX_DES_SNR (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x000f0000 ) >> 16)
+#define GET_RG_RX_DES_RCPI (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00f00000 ) >> 20)
+#define GET_RG_RX_DES_SRVC_LO (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x3f000000 ) >> 24)
+#define GET_RO_TX_DES_EXCP_RATE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x000000ff ) >> 0)
+#define GET_RO_TX_DES_EXCP_CH_BW_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x0000ff00 ) >> 8)
+#define GET_RO_TX_DES_EXCP_MODE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_DES_EXCP_RATE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x07000000 ) >> 24)
+#define GET_RG_TX_DES_EXCP_MODE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x70000000 ) >> 28)
+#define GET_RG_TX_DES_EXCP_CLR (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x80000000 ) >> 31)
+#define GET_RG_TX_DES_ACK_WIDTH (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_DES_ACK_PRD (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x0000000e ) >> 1)
+#define GET_RG_RX_DES_SNR_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x003f0000 ) >> 16)
+#define GET_RG_RX_DES_RCPI_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x3f000000 ) >> 24)
+#define GET_RG_TST_TBUS_SEL (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x0000000f ) >> 0)
+#define GET_RG_RSSI_OFFSET (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x00ff0000 ) >> 16)
+#define GET_RG_RSSI_INV (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x01000000 ) >> 24)
+#define GET_RG_TST_ADC_ON (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x40000000 ) >> 30)
+#define GET_RG_TST_EXT_GAIN (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x80000000 ) >> 31)
+#define GET_RG_DAC_Q_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x000003ff ) >> 0)
+#define GET_RG_DAC_I_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x003ff000 ) >> 12)
+#define GET_RG_DAC_EN_MAN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x10000000 ) >> 28)
+#define GET_RG_IQC_FFT_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x20000000 ) >> 29)
+#define GET_RG_DAC_MAN_Q_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x40000000 ) >> 30)
+#define GET_RG_DAC_MAN_I_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x80000000 ) >> 31)
+#define GET_RO_MRX_EN_CNT (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RG_MRX_EN_CNT_RST_N (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_PA_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_RFTX_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DAC_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ff0000 ) >> 16)
+#define GET_RG_SW_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff000000 ) >> 24)
+#define GET_RG_PA_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_RFTX_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DAC_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ff0000 ) >> 16)
+#define GET_RG_SW_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff000000 ) >> 24)
+#define GET_RG_ANT_SW_0 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000007 ) >> 0)
+#define GET_RG_ANT_SW_1 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000038 ) >> 3)
+#define GET_RG_MTX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MTX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MTX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_MTX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MTX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MTX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_MRX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MRX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MRX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_MRX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MRX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MRX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RO_MTX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff ) >> 0)
+#define GET_RO_MTX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000 ) >> 16)
+#define GET_RO_MRX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff ) >> 0)
+#define GET_RO_MRX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000 ) >> 16)
+#define GET_RG_MODE_REG_IN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x0000ffff ) >> 0)
+#define GET_RG_PARALLEL_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x00100000 ) >> 20)
+#define GET_RG_MBRUN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x01000000 ) >> 24)
+#define GET_RG_SHIFT_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x10000000 ) >> 28)
+#define GET_RG_MODE_REG_SI_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x20000000 ) >> 29)
+#define GET_RG_SIMULATION_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x40000000 ) >> 30)
+#define GET_RG_DBIST_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x80000000 ) >> 31)
+#define GET_RO_MODE_REG_OUT_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x0000ffff ) >> 0)
+#define GET_RO_MODE_REG_SO_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x01000000 ) >> 24)
+#define GET_RO_MONITOR_BUS_16 (((REG32(ADR_PHY_READ_REG_07_BIST)) & 0x0007ffff ) >> 0)
+#define GET_RG_MRX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x000000ff ) >> 0)
+#define GET_RG_MRX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x0000ff00 ) >> 8)
+#define GET_RG_MTX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ff0000 ) >> 16)
+#define GET_RG_MTX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff000000 ) >> 24)
+#define GET_RO_MTX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff ) >> 0)
+#define GET_RO_MTX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000 ) >> 16)
+#define GET_RO_MRX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff ) >> 0)
+#define GET_RO_MRX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000 ) >> 16)
+#define GET_RG_HB_COEF0 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x00000fff ) >> 0)
+#define GET_RG_HB_COEF1 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
+#define GET_RG_HB_COEF2 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x00000fff ) >> 0)
+#define GET_RG_HB_COEF3 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
+#define GET_RG_HB_COEF4 (((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0x00000fff ) >> 0)
+#define GET_RO_TBUS_O (((REG32(ADR_PHY_READ_TBUS)) & 0x000fffff ) >> 0)
+#define GET_RG_LPF4_00 (((REG32(ADR_TX_11B_FIL_COEF_00)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_01 (((REG32(ADR_TX_11B_FIL_COEF_01)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_02 (((REG32(ADR_TX_11B_FIL_COEF_02)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_03 (((REG32(ADR_TX_11B_FIL_COEF_03)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_04 (((REG32(ADR_TX_11B_FIL_COEF_04)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_05 (((REG32(ADR_TX_11B_FIL_COEF_05)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_06 (((REG32(ADR_TX_11B_FIL_COEF_06)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_07 (((REG32(ADR_TX_11B_FIL_COEF_07)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_08 (((REG32(ADR_TX_11B_FIL_COEF_08)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_09 (((REG32(ADR_TX_11B_FIL_COEF_09)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_10 (((REG32(ADR_TX_11B_FIL_COEF_10)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_11 (((REG32(ADR_TX_11B_FIL_COEF_11)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_12 (((REG32(ADR_TX_11B_FIL_COEF_12)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_13 (((REG32(ADR_TX_11B_FIL_COEF_13)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_14 (((REG32(ADR_TX_11B_FIL_COEF_14)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_15 (((REG32(ADR_TX_11B_FIL_COEF_15)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_16 (((REG32(ADR_TX_11B_FIL_COEF_16)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_17 (((REG32(ADR_TX_11B_FIL_COEF_17)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_18 (((REG32(ADR_TX_11B_FIL_COEF_18)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_19 (((REG32(ADR_TX_11B_FIL_COEF_19)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_20 (((REG32(ADR_TX_11B_FIL_COEF_20)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_21 (((REG32(ADR_TX_11B_FIL_COEF_21)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_22 (((REG32(ADR_TX_11B_FIL_COEF_22)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_23 (((REG32(ADR_TX_11B_FIL_COEF_23)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_24 (((REG32(ADR_TX_11B_FIL_COEF_24)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_25 (((REG32(ADR_TX_11B_FIL_COEF_25)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_26 (((REG32(ADR_TX_11B_FIL_COEF_26)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_27 (((REG32(ADR_TX_11B_FIL_COEF_27)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_28 (((REG32(ADR_TX_11B_FIL_COEF_28)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_29 (((REG32(ADR_TX_11B_FIL_COEF_29)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_30 (((REG32(ADR_TX_11B_FIL_COEF_30)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_31 (((REG32(ADR_TX_11B_FIL_COEF_31)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_32 (((REG32(ADR_TX_11B_FIL_COEF_32)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_33 (((REG32(ADR_TX_11B_FIL_COEF_33)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_34 (((REG32(ADR_TX_11B_FIL_COEF_34)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_35 (((REG32(ADR_TX_11B_FIL_COEF_35)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_36 (((REG32(ADR_TX_11B_FIL_COEF_36)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_37 (((REG32(ADR_TX_11B_FIL_COEF_37)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_38 (((REG32(ADR_TX_11B_FIL_COEF_38)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_39 (((REG32(ADR_TX_11B_FIL_COEF_39)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_40 (((REG32(ADR_TX_11B_FIL_COEF_40)) & 0x00001fff ) >> 0)
+#define GET_RG_BP_SMB (((REG32(ADR_TX_11B_PLCP)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_SRVC (((REG32(ADR_TX_11B_PLCP)) & 0x00004000 ) >> 14)
+#define GET_RG_DES_SPD (((REG32(ADR_TX_11B_PLCP)) & 0x00030000 ) >> 16)
+#define GET_RG_BB_11B_RISE_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_11B_FALL_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_WR_TX_EN_CNT_RST_N (((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0x00000001 ) >> 0)
+#define GET_RO_TX_EN_CNT (((REG32(ADR_TX_11B_EN_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RO_TX_CNT (((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
+#define GET_RG_POS_DES_11B_L_EXT (((REG32(ADR_RX_11B_DES_DLY)) & 0x0000000f ) >> 0)
+#define GET_RG_PRE_DES_11B_DLY (((REG32(ADR_RX_11B_DES_DLY)) & 0x000000f0 ) >> 4)
+#define GET_RG_CNT_CCA_LMT (((REG32(ADR_RX_11B_CCA_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_BYPASS_DESCRAMBLER (((REG32(ADR_RX_11B_CCA_0)) & 0x20000000 ) >> 29)
+#define GET_RG_BYPASS_AGC (((REG32(ADR_RX_11B_CCA_0)) & 0x80000000 ) >> 31)
+#define GET_RG_CCA_BIT_CNT_LMT_RX (((REG32(ADR_RX_11B_CCA_1)) & 0x000000f0 ) >> 4)
+#define GET_RG_CCA_SCALE_BF (((REG32(ADR_RX_11B_CCA_1)) & 0x007f0000 ) >> 16)
+#define GET_RG_PEAK_IDX_CNT_SEL (((REG32(ADR_RX_11B_CCA_1)) & 0x30000000 ) >> 28)
+#define GET_RG_TR_KI_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000007 ) >> 0)
+#define GET_RG_TR_KP_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000070 ) >> 4)
+#define GET_RG_TR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000700 ) >> 8)
+#define GET_RG_TR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00007000 ) >> 12)
+#define GET_RG_CR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00070000 ) >> 16)
+#define GET_RG_CR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00700000 ) >> 20)
+#define GET_RG_CHIP_CNT_SLICER (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000001f ) >> 0)
+#define GET_RG_CE_T4_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000ff00 ) >> 8)
+#define GET_RG_CE_T3_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ff0000 ) >> 16)
+#define GET_RG_CE_T2_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff000000 ) >> 24)
+#define GET_RG_CE_MU_T1 (((REG32(ADR_RX_11B_CE_MU_0)) & 0x00000007 ) >> 0)
+#define GET_RG_CE_DLY_SEL (((REG32(ADR_RX_11B_CE_MU_0)) & 0x003f0000 ) >> 16)
+#define GET_RG_CE_MU_T8 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000007 ) >> 0)
+#define GET_RG_CE_MU_T7 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000070 ) >> 4)
+#define GET_RG_CE_MU_T6 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000700 ) >> 8)
+#define GET_RG_CE_MU_T5 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00007000 ) >> 12)
+#define GET_RG_CE_MU_T4 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00070000 ) >> 16)
+#define GET_RG_CE_MU_T3 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00700000 ) >> 20)
+#define GET_RG_CE_MU_T2 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x07000000 ) >> 24)
+#define GET_RG_EQ_MU_FB_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x0000000f ) >> 0)
+#define GET_RG_EQ_MU_FF_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_MU_FB_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_EQ_MU_FF_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x00f00000 ) >> 20)
+#define GET_RG_EQ_MU_FB_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x0000000f ) >> 0)
+#define GET_RG_EQ_MU_FF_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_MU_FB_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000f0000 ) >> 16)
+#define GET_RG_EQ_MU_FF_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x00f00000 ) >> 20)
+#define GET_RG_EQ_KI_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00000700 ) >> 8)
+#define GET_RG_EQ_KP_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00007000 ) >> 12)
+#define GET_RG_EQ_KI_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00070000 ) >> 16)
+#define GET_RG_EQ_KP_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00700000 ) >> 20)
+#define GET_RG_TR_LPF_RATE (((REG32(ADR_RX_11B_LPF_RATE)) & 0x003fffff ) >> 0)
+#define GET_RG_CE_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x0000007f ) >> 0)
+#define GET_RG_CE_CH_MAIN_SET (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00000080 ) >> 7)
+#define GET_RG_TC_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00007f00 ) >> 8)
+#define GET_RG_CR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x007f0000 ) >> 16)
+#define GET_RG_TR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x7f000000 ) >> 24)
+#define GET_RG_EQ_MAIN_TAP_MAN (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x00000001 ) >> 0)
+#define GET_RG_EQ_MAIN_TAP_COEF (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x07ff0000 ) >> 16)
+#define GET_RG_PWRON_DLY_TH_11B (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x000000ff ) >> 0)
+#define GET_RG_SFD_BIT_CNT_LMT (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x00ff0000 ) >> 16)
+#define GET_RG_CCA_PWR_TH_RX (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x00007fff ) >> 0)
+#define GET_RG_CCA_PWR_CNT_TH (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x001f0000 ) >> 16)
+#define GET_B_FREQ_OS (((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0x000007ff ) >> 0)
+#define GET_B_SNR (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x0000007f ) >> 0)
+#define GET_B_RCPI (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x007f0000 ) >> 16)
+#define GET_CRC_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff ) >> 0)
+#define GET_SFD_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000 ) >> 16)
+#define GET_B_PACKET_ERR_CNT (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_PACKET_ERR (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x00010000 ) >> 16)
+#define GET_B_PACKET_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
+#define GET_B_CCA_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
+#define GET_B_LENGTH_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff ) >> 0)
+#define GET_SFD_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000 ) >> 16)
+#define GET_SIGNAL_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x000000ff ) >> 0)
+#define GET_B_SERVICE_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x0000ff00 ) >> 8)
+#define GET_CRC_CORRECT (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x00010000 ) >> 16)
+#define GET_DEBUG_SEL (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x0000000f ) >> 0)
+#define GET_RG_PACKET_STAT_EN_11B (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00100000 ) >> 20)
+#define GET_RG_BIT_REVERSE (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00200000 ) >> 21)
+#define GET_RX_PHY_11B_SOFT_RST_N (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000001 ) >> 0)
+#define GET_RG_CE_BYPASS_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_BYPASS_FBW_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000f00 ) >> 8)
+#define GET_RG_BB_11GN_RISE_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_11GN_FALL_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_HTCARR52_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x000003ff ) >> 0)
+#define GET_RG_HTCARR56_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x003ff000 ) >> 12)
+#define GET_RG_PACKET_STAT_EN (((REG32(ADR_TX_11GN_PLCP)) & 0x00800000 ) >> 23)
+#define GET_RG_SMB_DEF (((REG32(ADR_TX_11GN_PLCP)) & 0x7f000000 ) >> 24)
+#define GET_RG_CONTINUOUS_DATA_11GN (((REG32(ADR_TX_11GN_PLCP)) & 0x80000000 ) >> 31)
+#define GET_RO_TX_CNT_R (((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
+#define GET_RO_PACKET_ERR_CNT (((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RG_POS_DES_11GN_L_EXT (((REG32(ADR_RX_11GN_DES_DLY)) & 0x0000000f ) >> 0)
+#define GET_RG_PRE_DES_11GN_DLY (((REG32(ADR_RX_11GN_DES_DLY)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_KI_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_KP_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_CNT_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TR_LPF_KI_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_TR_LPF_KP_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x00f00000 ) >> 20)
+#define GET_RG_TR_CNT_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0xff000000 ) >> 24)
+#define GET_RG_TR_LPF_KI_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_KP_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_CNT_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TR_LPF_KI_G (((REG32(ADR_RX_11GN_TR_2)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_KP_G (((REG32(ADR_RX_11GN_TR_2)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_RATE_G (((REG32(ADR_RX_11GN_TR_2)) & 0x3fffff00 ) >> 8)
+#define GET_RG_CR_LPF_KI_G (((REG32(ADR_RX_11GN_CCA_0)) & 0x00000007 ) >> 0)
+#define GET_RG_SYM_BOUND_CNT (((REG32(ADR_RX_11GN_CCA_0)) & 0x00007f00 ) >> 8)
+#define GET_RG_XSCOR32_RATIO (((REG32(ADR_RX_11GN_CCA_0)) & 0x007f0000 ) >> 16)
+#define GET_RG_ATCOR64_CNT_LMT (((REG32(ADR_RX_11GN_CCA_0)) & 0x7f000000 ) >> 24)
+#define GET_RG_ATCOR16_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_1)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_1)) & 0x007f0000 ) >> 16)
+#define GET_RG_ATCOR16_RATIO_SB (((REG32(ADR_RX_11GN_CCA_1)) & 0x7f000000 ) >> 24)
+#define GET_RG_XSCOR64_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_2)) & 0x007f0000 ) >> 16)
+#define GET_RG_XSCOR64_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_2)) & 0x7f000000 ) >> 24)
+#define GET_RG_RX_FFT_SCALE (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x000003ff ) >> 0)
+#define GET_RG_VITERBI_AB_SWAP (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x00010000 ) >> 16)
+#define GET_RG_ATCOR16_CNT_TH (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x0f000000 ) >> 24)
+#define GET_RG_NORMSQUARE_LOW_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_LOW_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_LOW_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_LOW_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_LOW_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_3 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_SNR_2 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_SNR_1 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_SNR_0 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0xff000000 ) >> 24)
+#define GET_RG_SNR_TH_64QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x0000007f ) >> 0)
+#define GET_RG_SNR_TH_16QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_CNT_PLUS_LMT2 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x0000007f ) >> 0)
+#define GET_RG_ATCOR16_CNT_PLUS_LMT1 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00007f00 ) >> 8)
+#define GET_RG_SYM_BOUND_METHOD (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00030000 ) >> 16)
+#define GET_RG_PWRON_DLY_TH_11GN (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x000000ff ) >> 0)
+#define GET_RG_SB_START_CNT (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x00007f00 ) >> 8)
+#define GET_RG_POW16_CNT_TH (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x000000f0 ) >> 4)
+#define GET_RG_POW16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x00000700 ) >> 8)
+#define GET_RG_POW16_TH_L (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x7f000000 ) >> 24)
+#define GET_RG_XSCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00000007 ) >> 0)
+#define GET_RG_XSCOR16_RATIO (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00070000 ) >> 16)
+#define GET_RG_ATCOR16_RATIO_CCD (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x7f000000 ) >> 24)
+#define GET_RG_ATCOR64_ACC_LMT (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x0000007f ) >> 0)
+#define GET_RG_ATCOR16_SHORT_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x00070000 ) >> 16)
+#define GET_RG_VITERBI_TB_BITS (((REG32(ADR_RX_11GN_VTB_TB)) & 0xff000000 ) >> 24)
+#define GET_RG_CR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x000000ff ) >> 0)
+#define GET_RG_TR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x00ff0000 ) >> 16)
+#define GET_RG_BYPASS_CPE_MA (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000010 ) >> 4)
+#define GET_RG_PILOT_BNDRY_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000700 ) >> 8)
+#define GET_RG_EQ_SHORT_GI_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00007000 ) >> 12)
+#define GET_RG_FFT_WDW_SHORT_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00070000 ) >> 16)
+#define GET_RG_CHSMTH_COEF (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00030000 ) >> 16)
+#define GET_RG_CHSMTH_EN (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00040000 ) >> 18)
+#define GET_RG_CHEST_DD_FACTOR (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x07000000 ) >> 24)
+#define GET_RG_CH_UPDATE (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x80000000 ) >> 31)
+#define GET_RG_FMT_DET_MM_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x000000ff ) >> 0)
+#define GET_RG_FMT_DET_GF_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DO_NOT_CHECK_L_RATE (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x02000000 ) >> 25)
+#define GET_RG_FMT_DET_LENGTH_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff ) >> 0)
+#define GET_RG_L_LENGTH_MAX (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000 ) >> 16)
+#define GET_RG_TX_TIME_EXT (((REG32(ADR_RX_11GN_TX_TIME)) & 0x000000ff ) >> 0)
+#define GET_RG_MAC_DES_SPACE (((REG32(ADR_RX_11GN_TX_TIME)) & 0x00f00000 ) >> 20)
+#define GET_RG_TR_LPF_STBC_GF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_STBC_GF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_STBC_MF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x00000f00 ) >> 8)
+#define GET_RG_TR_LPF_STBC_MF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000f000 ) >> 12)
+#define GET_RG_MODE_REG_IN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x0001ffff ) >> 0)
+#define GET_RG_PARALLEL_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x00100000 ) >> 20)
+#define GET_RG_MBRUN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x01000000 ) >> 24)
+#define GET_RG_SHIFT_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x10000000 ) >> 28)
+#define GET_RG_MODE_REG_SI_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x20000000 ) >> 29)
+#define GET_RG_SIMULATION_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x40000000 ) >> 30)
+#define GET_RG_DBIST_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x80000000 ) >> 31)
+#define GET_RG_MODE_REG_IN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x0000ffff ) >> 0)
+#define GET_RG_PARALLEL_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x00100000 ) >> 20)
+#define GET_RG_MBRUN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x01000000 ) >> 24)
+#define GET_RG_SHIFT_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x10000000 ) >> 28)
+#define GET_RG_MODE_REG_SI_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x20000000 ) >> 29)
+#define GET_RG_SIMULATION_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x40000000 ) >> 30)
+#define GET_RG_DBIST_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x80000000 ) >> 31)
+#define GET_RO_MODE_REG_OUT_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x0001ffff ) >> 0)
+#define GET_RO_MODE_REG_SO_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x01000000 ) >> 24)
+#define GET_RO_MONITOR_BUS_80 (((REG32(ADR_RX_11GN_BIST_3)) & 0x003fffff ) >> 0)
+#define GET_RO_MODE_REG_OUT_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x0000ffff ) >> 0)
+#define GET_RO_MODE_REG_SO_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x01000000 ) >> 24)
+#define GET_RO_MONITOR_BUS_64 (((REG32(ADR_RX_11GN_BIST_5)) & 0x0007ffff ) >> 0)
+#define GET_RO_SPECTRUM_DATA (((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0xffffffff ) >> 0)
+#define GET_GN_SNR (((REG32(ADR_RX_11GN_READ_0)) & 0x0000007f ) >> 0)
+#define GET_GN_NOISE_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x00007f00 ) >> 8)
+#define GET_GN_RCPI (((REG32(ADR_RX_11GN_READ_0)) & 0x007f0000 ) >> 16)
+#define GET_GN_SIGNAL_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x7f000000 ) >> 24)
+#define GET_RO_FREQ_OS_LTS (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x00007fff ) >> 0)
+#define GET_CSTATE (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x000f0000 ) >> 16)
+#define GET_SIGNAL_FIELD0 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0x00ffffff ) >> 0)
+#define GET_SIGNAL_FIELD1 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0x00ffffff ) >> 0)
+#define GET_GN_PACKET_ERR_CNT (((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_GN_PACKET_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
+#define GET_GN_CCA_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
+#define GET_GN_LENGTH_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff ) >> 0)
+#define GET_GN_SERVICE_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000 ) >> 16)
+#define GET_RO_HT_MCS_40M (((REG32(ADR_RX_11GN_RATE)) & 0x0000007f ) >> 0)
+#define GET_RO_L_RATE_40M (((REG32(ADR_RX_11GN_RATE)) & 0x00003f00 ) >> 8)
+#define GET_RG_DAGC_CNT_TH (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00000003 ) >> 0)
+#define GET_RG_PACKET_STAT_EN_11GN (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00100000 ) >> 20)
+#define GET_RX_PHY_11GN_SOFT_RST_N (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000001 ) >> 0)
+#define GET_RG_RIFS_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000002 ) >> 1)
+#define GET_RG_STBC_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000004 ) >> 2)
+#define GET_RG_COR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000008 ) >> 3)
+#define GET_RG_INI_PHASE (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000030 ) >> 4)
+#define GET_RG_HT_LTF_SEL_EQ (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000040 ) >> 6)
+#define GET_RG_HT_LTF_SEL_PILOT (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000080 ) >> 7)
+#define GET_RG_CCA_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000200 ) >> 9)
+#define GET_RG_CCA_XSCOR_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000400 ) >> 10)
+#define GET_RG_CCA_XSCOR_AVGPWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000800 ) >> 11)
+#define GET_RG_DEBUG_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x0000f000 ) >> 12)
+#define GET_RG_POST_CLK_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00010000 ) >> 16)
+#define GET_IQCAL_RF_TX_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000001 ) >> 0)
+#define GET_IQCAL_RF_TX_PA_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000002 ) >> 1)
+#define GET_IQCAL_RF_TX_DAC_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000004 ) >> 2)
+#define GET_IQCAL_RF_RX_AGC (((REG32(ADR_RF_CONTROL_0)) & 0x00000008 ) >> 3)
+#define GET_IQCAL_RF_PGAG (((REG32(ADR_RF_CONTROL_0)) & 0x00000f00 ) >> 8)
+#define GET_IQCAL_RF_RFG (((REG32(ADR_RF_CONTROL_0)) & 0x00003000 ) >> 12)
+#define GET_RG_TONEGEN_FREQ (((REG32(ADR_RF_CONTROL_0)) & 0x007f0000 ) >> 16)
+#define GET_RG_TONEGEN_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00800000 ) >> 23)
+#define GET_RG_TONEGEN_INIT_PH (((REG32(ADR_RF_CONTROL_0)) & 0x7f000000 ) >> 24)
+#define GET_RG_TONEGEN2_FREQ (((REG32(ADR_RF_CONTROL_1)) & 0x0000007f ) >> 0)
+#define GET_RG_TONEGEN2_EN (((REG32(ADR_RF_CONTROL_1)) & 0x00000080 ) >> 7)
+#define GET_RG_TONEGEN2_SCALE (((REG32(ADR_RF_CONTROL_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TXIQ_CLP_THD_I (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x000003ff ) >> 0)
+#define GET_RG_TXIQ_CLP_THD_Q (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_TX_I_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x000000ff ) >> 0)
+#define GET_RG_TX_Q_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TX_IQ_SWP (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00010000 ) >> 16)
+#define GET_RG_TX_SGN_OUT (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00020000 ) >> 17)
+#define GET_RG_TXIQ_EMU_IDX (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x003c0000 ) >> 18)
+#define GET_RG_TX_IQ_SRC (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x03000000 ) >> 24)
+#define GET_RG_TX_I_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x000003ff ) >> 0)
+#define GET_RG_TX_Q_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x03ff0000 ) >> 16)
+#define GET_RG_TX_IQ_THETA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_IQ_ALPHA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
+#define GET_RG_TXIQ_NOSHRINK (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
+#define GET_RG_TX_I_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_Q_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff000000 ) >> 24)
+#define GET_RG_RX_IQ_THETA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
+#define GET_RG_RX_IQ_ALPHA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
+#define GET_RG_RXIQ_NOSHRINK (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
+#define GET_RG_MA_DPTH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x0000000f ) >> 0)
+#define GET_RG_INTG_PH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x000003f0 ) >> 4)
+#define GET_RG_INTG_PRD (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00001c00 ) >> 10)
+#define GET_RG_INTG_MU (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00006000 ) >> 13)
+#define GET_RG_IQCAL_SPRM_SELQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00010000 ) >> 16)
+#define GET_RG_IQCAL_SPRM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00020000 ) >> 17)
+#define GET_RG_IQCAL_SPRM_FREQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IQCAL_IQCOL_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x01000000 ) >> 24)
+#define GET_RG_IQCAL_ALPHA_ESTM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x02000000 ) >> 25)
+#define GET_RG_IQCAL_DC_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x04000000 ) >> 26)
+#define GET_RG_PHEST_STBY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x08000000 ) >> 27)
+#define GET_RG_PHEST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x10000000 ) >> 28)
+#define GET_RG_GP_DIV_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x20000000 ) >> 29)
+#define GET_RG_DPD_GAIN_EST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x40000000 ) >> 30)
+#define GET_RG_IQCAL_MULT_OP0 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x000003ff ) >> 0)
+#define GET_RG_IQCAL_MULT_OP1 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x03ff0000 ) >> 16)
+#define GET_RO_IQCAL_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x000fffff ) >> 0)
+#define GET_RO_IQCAL_SPRM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00100000 ) >> 20)
+#define GET_RO_IQCAL_IQCOL_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00200000 ) >> 21)
+#define GET_RO_IQCAL_ALPHA_ESTM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00400000 ) >> 22)
+#define GET_RO_IQCAL_DC_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00800000 ) >> 23)
+#define GET_RO_IQCAL_MULT_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x01000000 ) >> 24)
+#define GET_RO_FFT_ENRG_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x02000000 ) >> 25)
+#define GET_RO_PHEST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x04000000 ) >> 26)
+#define GET_RO_GP_DIV_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x08000000 ) >> 27)
+#define GET_RO_GAIN_EST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x10000000 ) >> 28)
+#define GET_RO_AMP_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0x000001ff ) >> 0)
+#define GET_RG_RX_I_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x000000ff ) >> 0)
+#define GET_RG_RX_Q_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_RX_I_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ff0000 ) >> 16)
+#define GET_RG_RX_Q_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff000000 ) >> 24)
+#define GET_RG_RX_IQ_SWP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000001 ) >> 0)
+#define GET_RG_RX_SGN_IN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000002 ) >> 1)
+#define GET_RG_RX_IQ_SRC (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x0000000c ) >> 2)
+#define GET_RG_ACI_GAIN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000ff0 ) >> 4)
+#define GET_RG_FFT_EN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00001000 ) >> 12)
+#define GET_RG_FFT_MOD (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00002000 ) >> 13)
+#define GET_RG_FFT_SCALE (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00ffc000 ) >> 14)
+#define GET_RG_FFT_ENRG_FREQ (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x3f000000 ) >> 24)
+#define GET_RG_FPGA_80M_PH_UP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x40000000 ) >> 30)
+#define GET_RG_FPGA_80M_PH_STP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x80000000 ) >> 31)
+#define GET_RG_ADC2LA_SEL (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000001 ) >> 0)
+#define GET_RG_ADC2LA_CLKPH (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000002 ) >> 1)
+#define GET_RG_RXIQ_EMU_IDX (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x0000000f ) >> 0)
+#define GET_RG_IQCAL_BP_ACI (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x00000010 ) >> 4)
+#define GET_RG_DPD_AM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000001 ) >> 0)
+#define GET_RG_DPD_PM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000002 ) >> 1)
+#define GET_RG_DPD_PM_AMSEL (((REG32(ADR_DPD_CONTROL)) & 0x00000004 ) >> 2)
+#define GET_RG_DPD_020_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_040_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_060_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_080_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_0C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_0E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_100_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_110_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_120_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_130_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_140_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_150_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_160_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_170_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_180_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_190_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1B0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_200_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_020_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_040_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_060_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_080_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0A0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_0C0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0D0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_0E0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0F0_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_100_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_110_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_120_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_130_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_140_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_150_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_160_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_170_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_180_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_190_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1A0_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1B0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1C0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1D0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1E0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1F0_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_200_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_GAIN_EST_Y0 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x000001ff ) >> 0)
+#define GET_RG_DPD_GAIN_EST_Y1 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x01ff0000 ) >> 16)
+#define GET_RG_DPD_LOOP_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_GAIN_EST_X0 (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x000001ff ) >> 0)
+#define GET_RO_DPD_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x03ff0000 ) >> 16)
+#define GET_TX_SCALE_11B (((REG32(ADR_TX_GAIN_FACTOR)) & 0x000000ff ) >> 0)
+#define GET_TX_SCALE_11B_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0x0000ff00 ) >> 8)
+#define GET_TX_SCALE_11G (((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ff0000 ) >> 16)
+#define GET_TX_SCALE_11G_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0xff000000 ) >> 24)
+#define GET_RG_EN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_TX_PA_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_TX_DAC_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_RX_AGC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_RX_GAIN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_RFG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_PGAG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_MODE (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_EN_TX_TRSW (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_EN_SX (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_EN_RX_LNA (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_EN_RX_MIXER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_EN_RX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_EN_RX_LOBUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_EN_RX_TZ (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_EN_RX_FILTER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_EN_RX_HPF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_EN_RX_RSSI (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_EN_ADC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_EN_TX_MOD (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_EN_TX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_EN_TX_DIV2_BUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_EN_TX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_EN_RX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_SEL_DPLL_CLK (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_EN_CLK_960MBY13_UART (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_EN_TX_DPD (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_TX_TSSI (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_RX_IQCAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_TX_DAC_CAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_EN_TX_SELF_MIXER (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_TX_DAC_OUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_EN_LDO_RX_FE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_LDO_ABB (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_EN_LDO_AFE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_EN_SX_CHPLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_EN_SX_LOBFLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_EN_IREF_RX (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_TX_DAC_VOUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_SX_LCK_BIN (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_RTC_CAL_MODE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_EN_IQPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_EN_TESTPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_EN_TRXBF_BYPASS (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_LDO_LEVEL_RX_FE (((REG32(ADR_LDO_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_LDO_LEVEL_ABB (((REG32(ADR_LDO_REGISTER)) & 0x00000038 ) >> 3)
+#define GET_RG_LDO_LEVEL_AFE (((REG32(ADR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
+#define GET_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
+#define GET_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_RG_DP_LDO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
+#define GET_RG_TX_LDO_TX_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_EN_RX_PADSW (((REG32(ADR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_RX_TESTNODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
+#define GET_RG_RX_ABBCFIX (((REG32(ADR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
+#define GET_RG_RX_ABBCTUNE (((REG32(ADR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
+#define GET_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
+#define GET_RG_RX_ABB_N_MODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
+#define GET_RG_RX_EN_LOOPA (((REG32(ADR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
+#define GET_RG_RX_FILTERI1ST (((REG32(ADR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
+#define GET_RG_RX_FILTERI2ND (((REG32(ADR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_FILTERI3RD (((REG32(ADR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
+#define GET_RG_RX_FILTERI_COURSE (((REG32(ADR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
+#define GET_RG_RX_FILTERVCM (((REG32(ADR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
+#define GET_RG_RX_HPF3M (((REG32(ADR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
+#define GET_RG_RX_HPF300K (((REG32(ADR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
+#define GET_RG_RX_HPFI (((REG32(ADR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
+#define GET_RG_RX_HPF_FINALCORNER (((REG32(ADR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
+#define GET_RG_RX_HPF_SETTLE1_C (((REG32(ADR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
+#define GET_RG_RX_HPF_SETTLE1_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_HPF_SETTLE2_C (((REG32(ADR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
+#define GET_RG_RX_HPF_SETTLE2_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
+#define GET_RG_RX_HPF_VCMCON2 (((REG32(ADR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
+#define GET_RG_RX_HPF_VCMCON (((REG32(ADR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
+#define GET_RG_RX_OUTVCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
+#define GET_RG_RX_TZI (((REG32(ADR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
+#define GET_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
+#define GET_RG_RX_TZ_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
+#define GET_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
+#define GET_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
+#define GET_RG_RX_ADCRSSI_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
+#define GET_RG_RX_REC_LPFCORNER (((REG32(ADR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
+#define GET_RG_RSSI_CLOCK_GATING (((REG32(ADR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
+#define GET_RG_TXPGA_CAPSW (((REG32(ADR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TXPGA_MAIN (((REG32(ADR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
+#define GET_RG_TXPGA_STEER (((REG32(ADR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
+#define GET_RG_TXMOD_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TXLPF_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_PACELL_EN (((REG32(ADR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_RG_PABIAS_CTRL (((REG32(ADR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
+#define GET_RG_TX_DIV_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_RG_TX_LOBUF_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_RX_SQDC (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
+#define GET_RG_RX_DIV2_CORE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
+#define GET_RG_RX_LOBUF (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
+#define GET_RG_TX_DPDGM_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
+#define GET_RG_TX_DPD_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
+#define GET_RG_TX_TSSI_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
+#define GET_RG_TX_TSSI_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
+#define GET_RG_TX_TSSI_TESTMODE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
+#define GET_RG_TX_TSSI_TEST (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
+#define GET_RG_PACASCODE_CTRL (((REG32(ADR_RX_FE_REGISTER_1)) & 0x07000000 ) >> 24)
+#define GET_RG_RX_HG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_HG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_HG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_HG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_MG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_MG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_MG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_MG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_LG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_LG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_LG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_LG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_ULG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_ULG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_ULG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
+#define GET_RG_HPF1_FAST_SET_X (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_HPF1_FAST_SET_Y (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_HPF1_FAST_SET_Z (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_HPF_T1A (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_RG_HPF_T1B (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000060 ) >> 5)
+#define GET_RG_HPF_T1C (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000180 ) >> 7)
+#define GET_RG_RX_LNA_TRI_SEL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_RG_RX_LNA_SETTLE (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00001800 ) >> 11)
+#define GET_RG_TXGAIN_PHYCTRL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_TX_GAIN (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x003fc000 ) >> 14)
+#define GET_RG_TXGAIN_MANUAL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TX_GAIN_OFFSET (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x07800000 ) >> 23)
+#define GET_RG_ADC_CLKSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_ADC_DIBIAS (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_RG_ADC_DIVR (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_ADC_DVCMI (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_ADC_SAMSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
+#define GET_RG_ADC_STNBY (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_ADC_TESTMODE (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_ADC_TSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_ADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_DICMP (((REG32(ADR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_DIOP (((REG32(ADR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_SARADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_EN_SAR_TEST (((REG32(ADR_RX_ADC_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_SARADC_THERMAL (((REG32(ADR_RX_ADC_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_SARADC_TSSI (((REG32(ADR_RX_ADC_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_CLK_SAR_SEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_EN_SARADC (((REG32(ADR_RX_ADC_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_DACI1ST (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TX_DACLPF_ICOURSE (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TX_DACLPF_IFINE (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_TX_DACLPF_VCM (((REG32(ADR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_TX_DAC_IBIAS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_RG_TX_DAC_OS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
+#define GET_RG_TX_DAC_RCAL (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TX_DAC_TSEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
+#define GET_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_TXLPF_BYPASS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_TXLPF_BOOSTI (((REG32(ADR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TX_DAC_IOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x07800000 ) >> 23)
+#define GET_RG_TX_DAC_QOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x78000000 ) >> 27)
+#define GET_RG_EN_SX_R3 (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_SX_CH (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_SX_CHP (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_SX_DIVCK (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_EN_SX_VCOBF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_SX_VCO (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_EN_SX_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_SX_DITHER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_EN_SX_VT_MON (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_SX_VT_MON_DG (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_EN_SX_DIV (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_SX_LPF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_EN_DPL_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_DPL_MOD_ORDER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_SX_RFCTRL_F (((REG32(ADR_SYN_REGISTER_1)) & 0x00ffffff ) >> 0)
+#define GET_RG_SX_SEL_CP (((REG32(ADR_SYN_REGISTER_1)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_SEL_CS (((REG32(ADR_SYN_REGISTER_1)) & 0xf0000000 ) >> 28)
+#define GET_RG_SX_RFCTRL_CH (((REG32(ADR_SYN_REGISTER_2)) & 0x000007ff ) >> 0)
+#define GET_RG_SX_SEL_C3 (((REG32(ADR_SYN_REGISTER_2)) & 0x00007800 ) >> 11)
+#define GET_RG_SX_SEL_RS (((REG32(ADR_SYN_REGISTER_2)) & 0x000f8000 ) >> 15)
+#define GET_RG_SX_SEL_R3 (((REG32(ADR_SYN_REGISTER_2)) & 0x01f00000 ) >> 20)
+#define GET_RG_SX_SEL_ICHP (((REG32(ADR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
+#define GET_RG_SX_SEL_PCHP (((REG32(ADR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
+#define GET_RG_SX_SEL_CHP_REGOP (((REG32(ADR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
+#define GET_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
+#define GET_RG_SX_CHP_IOST_POL (((REG32(ADR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
+#define GET_RG_SX_CHP_IOST (((REG32(ADR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
+#define GET_RG_SX_PFDSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
+#define GET_RG_SX_PFD_SET (((REG32(ADR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
+#define GET_RG_SX_PFD_SET1 (((REG32(ADR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
+#define GET_RG_SX_PFD_SET2 (((REG32(ADR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
+#define GET_RG_SX_VBNCAS_SEL (((REG32(ADR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
+#define GET_RG_SX_PFD_RST_H (((REG32(ADR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
+#define GET_RG_SX_PFD_TRUP (((REG32(ADR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
+#define GET_RG_SX_PFD_TRDN (((REG32(ADR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
+#define GET_RG_SX_PFD_TRSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
+#define GET_RG_SX_VCOBA_R (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
+#define GET_RG_SX_VCORSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
+#define GET_RG_SX_VCOCUSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
+#define GET_RG_SX_RXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
+#define GET_RG_SX_TXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
+#define GET_RG_SX_VCOBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
+#define GET_RG_SX_DIVBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_GNDR_SEL (((REG32(ADR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
+#define GET_RG_SX_DITHER_WEIGHT (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
+#define GET_RG_SX_MOD_ORDER (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
+#define GET_RG_SX_RST_H_DIV (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
+#define GET_RG_SX_SDM_EDGE (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
+#define GET_RG_SX_XO_GM (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
+#define GET_RG_SX_REFBYTWO (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
+#define GET_RG_SX_LCKEN (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
+#define GET_RG_SX_PREVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
+#define GET_RG_SX_PSCONTERVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_PH (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00002000 ) >> 13)
+#define GET_RG_SX_PL (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00004000 ) >> 14)
+#define GET_RG_XOSC_CBANK_XO (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00078000 ) >> 15)
+#define GET_RG_XOSC_CBANK_XI (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00780000 ) >> 19)
+#define GET_RG_SX_VT_MON_MODE (((REG32(ADR_SYN_LCK_VT)) & 0x00000001 ) >> 0)
+#define GET_RG_SX_VT_TH_HI (((REG32(ADR_SYN_LCK_VT)) & 0x00000006 ) >> 1)
+#define GET_RG_SX_VT_TH_LO (((REG32(ADR_SYN_LCK_VT)) & 0x00000018 ) >> 3)
+#define GET_RG_SX_VT_SET (((REG32(ADR_SYN_LCK_VT)) & 0x00000020 ) >> 5)
+#define GET_RG_SX_VT_MON_TMR (((REG32(ADR_SYN_LCK_VT)) & 0x00007fc0 ) >> 6)
+#define GET_RG_EN_DP_VT_MON (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_DP_VT_TH_HI (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_RG_DP_VT_TH_LO (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_RG_DP_CK320BY2 (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_DP_OD_TEST (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_DP_BBPLL_BP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_DP_BBPLL_ICP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_RG_DP_BBPLL_IDUAL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_RG_DP_BBPLL_OD_TEST (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
+#define GET_RG_DP_BBPLL_PD (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_DP_BBPLL_TESTSEL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
+#define GET_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
+#define GET_RG_DP_RP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_RG_DP_RHP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_DP_BBPLL_SDM_EDGE (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_DP_FODIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x0007f000 ) >> 12)
+#define GET_RG_DP_REFDIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x1fc00000 ) >> 22)
+#define GET_RG_IDACAI_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
+#define GET_RG_DP_BBPLL_BS (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
+#define GET_RG_IDACAI_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
+#define GET_RG_EN_RCAL (((REG32(ADR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_RCAL_SPD (((REG32(ADR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_RCAL_TMR (((REG32(ADR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
+#define GET_RG_RCAL_CODE_CWR (((REG32(ADR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_RCAL_CODE_CWD (((REG32(ADR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
+#define GET_RG_SX_SUB_SEL_CWR (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00000001 ) >> 0)
+#define GET_RG_SX_SUB_SEL_CWD (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x000000fe ) >> 1)
+#define GET_RG_SX_LCK_BIN_OFFSET (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00078000 ) >> 15)
+#define GET_RG_SX_LCK_BIN_PRECISION (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00080000 ) >> 19)
+#define GET_RG_SX_LOCK_EN_N (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00100000 ) >> 20)
+#define GET_RG_SX_LOCK_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00200000 ) >> 21)
+#define GET_RG_SX_SUB_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00400000 ) >> 22)
+#define GET_RG_SX_SUB_SEL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x3f800000 ) >> 23)
+#define GET_RG_SX_MUX_SEL_VTH_BINL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x40000000 ) >> 30)
+#define GET_RG_TRX_DUMMMY (((REG32(ADR_TRX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
+#define GET_RG_SX_DUMMMY (((REG32(ADR_SX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
+#define GET_RCAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
+#define GET_LCK_BIN_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
+#define GET_VT_MON_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
+#define GET_DA_R_CODE_LUT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
+#define GET_AD_SX_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
+#define GET_AD_DP_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
+#define GET_RTC_CAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00008000 ) >> 15)
+#define GET_RG_SARADC_BIT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x003f0000 ) >> 16)
+#define GET_SAR_ADC_FSM_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00400000 ) >> 22)
+#define GET_AD_CIRCUIT_VERSION (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x07800000 ) >> 23)
+#define GET_DA_R_CAL_CODE (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
+#define GET_DA_SX_SUB_SEL (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
+#define GET_RG_DPL_RFCTRL_CH (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x000007ff ) >> 0)
+#define GET_RG_RSSIADC_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x00007800 ) >> 11)
+#define GET_RG_RX_ADC_I_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x007f8000 ) >> 15)
+#define GET_RG_RX_ADC_Q_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x7f800000 ) >> 23)
+#define GET_RG_DPL_RFCTRL_F (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0x00ffffff ) >> 0)
+#define GET_RG_SX_TARGET_CNT (((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0x00001fff ) >> 0)
+#define GET_RG_RTC_OFFSET (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000000ff ) >> 0)
+#define GET_RG_RTC_CAL_TARGET_COUNT (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000fff00 ) >> 8)
+#define GET_RG_RF_D_REG (((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0x0000ffff ) >> 0)
+#define GET_DIRECT_MODE (((REG32(ADR_MMU_CTRL)) & 0x00000001 ) >> 0)
+#define GET_TAG_INTERLEAVE_MD (((REG32(ADR_MMU_CTRL)) & 0x00000002 ) >> 1)
+#define GET_DIS_DEMAND (((REG32(ADR_MMU_CTRL)) & 0x00000004 ) >> 2)
+#define GET_SAME_ID_ALLOC_MD (((REG32(ADR_MMU_CTRL)) & 0x00000008 ) >> 3)
+#define GET_HS_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000010 ) >> 4)
+#define GET_SRAM_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000020 ) >> 5)
+#define GET_NOHIT_RPASS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000040 ) >> 6)
+#define GET_DMN_FLAG_CLR (((REG32(ADR_MMU_CTRL)) & 0x00000080 ) >> 7)
+#define GET_ERR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000100 ) >> 8)
+#define GET_ALR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000200 ) >> 9)
+#define GET_MCH_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000400 ) >> 10)
+#define GET_TAG_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000800 ) >> 11)
+#define GET_ABT_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00001000 ) >> 12)
+#define GET_MMU_VER (((REG32(ADR_MMU_CTRL)) & 0x0000e000 ) >> 13)
+#define GET_MMU_SHARE_MCU (((REG32(ADR_MMU_CTRL)) & 0x00ff0000 ) >> 16)
+#define GET_HS_WR (((REG32(ADR_HS_CTRL)) & 0x00000001 ) >> 0)
+#define GET_HS_FLAG (((REG32(ADR_HS_CTRL)) & 0x00000010 ) >> 4)
+#define GET_HS_ID (((REG32(ADR_HS_CTRL)) & 0x00007f00 ) >> 8)
+#define GET_HS_CHANNEL (((REG32(ADR_HS_CTRL)) & 0x000f0000 ) >> 16)
+#define GET_HS_PAGE (((REG32(ADR_HS_CTRL)) & 0x00f00000 ) >> 20)
+#define GET_HS_DATA (((REG32(ADR_HS_CTRL)) & 0xff000000 ) >> 24)
+#define GET_CPU_POR0 (((REG32(ADR_CPU_POR0_7)) & 0x0000000f ) >> 0)
+#define GET_CPU_POR1 (((REG32(ADR_CPU_POR0_7)) & 0x000000f0 ) >> 4)
+#define GET_CPU_POR2 (((REG32(ADR_CPU_POR0_7)) & 0x00000f00 ) >> 8)
+#define GET_CPU_POR3 (((REG32(ADR_CPU_POR0_7)) & 0x0000f000 ) >> 12)
+#define GET_CPU_POR4 (((REG32(ADR_CPU_POR0_7)) & 0x000f0000 ) >> 16)
+#define GET_CPU_POR5 (((REG32(ADR_CPU_POR0_7)) & 0x00f00000 ) >> 20)
+#define GET_CPU_POR6 (((REG32(ADR_CPU_POR0_7)) & 0x0f000000 ) >> 24)
+#define GET_CPU_POR7 (((REG32(ADR_CPU_POR0_7)) & 0xf0000000 ) >> 28)
+#define GET_CPU_POR8 (((REG32(ADR_CPU_POR8_F)) & 0x0000000f ) >> 0)
+#define GET_CPU_POR9 (((REG32(ADR_CPU_POR8_F)) & 0x000000f0 ) >> 4)
+#define GET_CPU_PORA (((REG32(ADR_CPU_POR8_F)) & 0x00000f00 ) >> 8)
+#define GET_CPU_PORB (((REG32(ADR_CPU_POR8_F)) & 0x0000f000 ) >> 12)
+#define GET_CPU_PORC (((REG32(ADR_CPU_POR8_F)) & 0x000f0000 ) >> 16)
+#define GET_CPU_PORD (((REG32(ADR_CPU_POR8_F)) & 0x00f00000 ) >> 20)
+#define GET_CPU_PORE (((REG32(ADR_CPU_POR8_F)) & 0x0f000000 ) >> 24)
+#define GET_CPU_PORF (((REG32(ADR_CPU_POR8_F)) & 0xf0000000 ) >> 28)
+#define GET_ACC_WR_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x0000003f ) >> 0)
+#define GET_ACC_RD_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x00003f00 ) >> 8)
+#define GET_REQ_NACK_CLR (((REG32(ADR_REG_LEN_CTRL)) & 0x00008000 ) >> 15)
+#define GET_NACK_FLAG_BUS (((REG32(ADR_REG_LEN_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_DMN_R_PASS (((REG32(ADR_DMN_READ_BYPASS)) & 0x0000ffff ) >> 0)
+#define GET_PARA_ALC_RLS (((REG32(ADR_DMN_READ_BYPASS)) & 0x00010000 ) >> 16)
+#define GET_REQ_PORNS_CHGEN (((REG32(ADR_DMN_READ_BYPASS)) & 0x01000000 ) >> 24)
+#define GET_ALC_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x0000007f ) >> 0)
+#define GET_ALC_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x00008000 ) >> 15)
+#define GET_RLS_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x007f0000 ) >> 16)
+#define GET_RLS_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x80000000 ) >> 31)
+#define GET_DEBUG_CTL (((REG32(ADR_DEBUG_CTL)) & 0x000000ff ) >> 0)
+#define GET_DEBUG_H16 (((REG32(ADR_DEBUG_CTL)) & 0x00000100 ) >> 8)
+#define GET_DEBUG_OUT (((REG32(ADR_DEBUG_OUT)) & 0xffffffff ) >> 0)
+#define GET_ALC_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_RLS_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_AL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00000700 ) >> 8)
+#define GET_RL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00007000 ) >> 12)
+#define GET_ALC_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x007f0000 ) >> 16)
+#define GET_RLS_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x7f000000 ) >> 24)
+#define GET_DMN_NOHIT_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000001 ) >> 0)
+#define GET_DMN_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000002 ) >> 1)
+#define GET_DMN_WR (((REG32(ADR_DMN_STATUS)) & 0x00000008 ) >> 3)
+#define GET_DMN_PORT (((REG32(ADR_DMN_STATUS)) & 0x000000f0 ) >> 4)
+#define GET_DMN_NHIT_ID (((REG32(ADR_DMN_STATUS)) & 0x00007f00 ) >> 8)
+#define GET_DMN_NHIT_ADDR (((REG32(ADR_DMN_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_TX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x000000ff ) >> 0)
+#define GET_RX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x0000ff00 ) >> 8)
+#define GET_AVA_TAG (((REG32(ADR_TAG_STATUS)) & 0x01ff0000 ) >> 16)
+#define GET_PKTBUF_FULL (((REG32(ADR_TAG_STATUS)) & 0x80000000 ) >> 31)
+#define GET_DMN_NOHIT_MCU (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_DMN_MCU_FLAG (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_DMN_MCU_WR (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000008 ) >> 3)
+#define GET_DMN_MCU_PORT (((REG32(ADR_DMN_MCU_STATUS)) & 0x000000f0 ) >> 4)
+#define GET_DMN_MCU_ID (((REG32(ADR_DMN_MCU_STATUS)) & 0x00007f00 ) >> 8)
+#define GET_DMN_MCU_ADDR (((REG32(ADR_DMN_MCU_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_MB_IDTBL_31_0 (((REG32(ADR_MB_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_MB_IDTBL_63_32 (((REG32(ADR_MB_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_MB_IDTBL_95_64 (((REG32(ADR_MB_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_MB_IDTBL_127_96 (((REG32(ADR_MB_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_31_0 (((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_63_32 (((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_95_64 (((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_127_96 (((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_31_0 (((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_63_32 (((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_95_64 (((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_127_96 (((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_31_0 (((REG32(ADR_MB_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_63_32 (((REG32(ADR_MB_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_95_64 (((REG32(ADR_MB_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_127_96 (((REG32(ADR_MB_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_31_0 (((REG32(ADR_PKT_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_63_32 (((REG32(ADR_PKT_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_95_64 (((REG32(ADR_PKT_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_127_96 (((REG32(ADR_PKT_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_ALC_NOCHG_ID (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x0000007f ) >> 0)
+#define GET_ALC_NOCHG_INT (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00008000 ) >> 15)
+#define GET_NEQ_PKT_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00010000 ) >> 16)
+#define GET_NEQ_MB_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x01000000 ) >> 24)
+#define GET_SRAM_TAG_0 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_1 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_2 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_3 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_4 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_5 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_6 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_7 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_8 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_9 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_10 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_11 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_12 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_13 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_14 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_15 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000 ) >> 16)
+#define SET_MCU_ENABLE(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 0) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffe))
+#define SET_MAC_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 1) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffd))
+#define SET_MCU_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 2) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffb))
+#define SET_SDIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 3) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffff7))
+#define SET_SPI_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 4) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffef))
+#define SET_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 5) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffdf))
+#define SET_DMA_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 6) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffbf))
+#define SET_WDT_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 7) | ((REG32(ADR_BRG_SW_RST)) & 0xffffff7f))
+#define SET_I2C_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 8) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffeff))
+#define SET_INT_CTL_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 9) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffdff))
+#define SET_BTCX_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 10) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffbff))
+#define SET_GPIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 11) | ((REG32(ADR_BRG_SW_RST)) & 0xfffff7ff))
+#define SET_US0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 12) | ((REG32(ADR_BRG_SW_RST)) & 0xffffefff))
+#define SET_US1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 13) | ((REG32(ADR_BRG_SW_RST)) & 0xffffdfff))
+#define SET_US2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 14) | ((REG32(ADR_BRG_SW_RST)) & 0xffffbfff))
+#define SET_US3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 15) | ((REG32(ADR_BRG_SW_RST)) & 0xffff7fff))
+#define SET_MS0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 16) | ((REG32(ADR_BRG_SW_RST)) & 0xfffeffff))
+#define SET_MS1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 17) | ((REG32(ADR_BRG_SW_RST)) & 0xfffdffff))
+#define SET_MS2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 18) | ((REG32(ADR_BRG_SW_RST)) & 0xfffbffff))
+#define SET_MS3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 19) | ((REG32(ADR_BRG_SW_RST)) & 0xfff7ffff))
+#define SET_RF_BB_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 20) | ((REG32(ADR_BRG_SW_RST)) & 0xffefffff))
+#define SET_SYS_ALL_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 21) | ((REG32(ADR_BRG_SW_RST)) & 0xffdfffff))
+#define SET_DAT_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 22) | ((REG32(ADR_BRG_SW_RST)) & 0xffbfffff))
+#define SET_I2C_MST_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 23) | ((REG32(ADR_BRG_SW_RST)) & 0xff7fffff))
+#define SET_RG_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT)) & 0xfffffffe))
+#define SET_TRAP_IMG_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 16) | ((REG32(ADR_BOOT)) & 0xfffeffff))
+#define SET_TRAP_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 17) | ((REG32(ADR_BOOT)) & 0xfffdffff))
+#define SET_TRAP_BOOT_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 18) | ((REG32(ADR_BOOT)) & 0xfffbffff))
+#define SET_CHIP_ID_31_0(_VAL_) (REG32(ADR_CHIP_ID_0)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_0)) & 0x00000000))
+#define SET_CHIP_ID_63_32(_VAL_) (REG32(ADR_CHIP_ID_1)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_1)) & 0x00000000))
+#define SET_CHIP_ID_95_64(_VAL_) (REG32(ADR_CHIP_ID_2)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_2)) & 0x00000000))
+#define SET_CHIP_ID_127_96(_VAL_) (REG32(ADR_CHIP_ID_3)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_3)) & 0x00000000))
+#define SET_CK_SEL_1_0(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 0) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffc))
+#define SET_CK_SEL_2(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 2) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffb))
+#define SET_SYS_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffe))
+#define SET_MAC_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MCU_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 2) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffb))
+#define SET_SDIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffff7))
+#define SET_SPI_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffef))
+#define SET_UART_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffdf))
+#define SET_DMA_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffbf))
+#define SET_WDT_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffff7f))
+#define SET_I2C_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 8) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffeff))
+#define SET_INT_CTL_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffdff))
+#define SET_BTCX_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_GPIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffff7ff))
+#define SET_US0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffefff))
+#define SET_US1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_US2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffbfff))
+#define SET_US3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffff7fff))
+#define SET_MS0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 16) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffeffff))
+#define SET_MS1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 17) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffdffff))
+#define SET_MS2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 18) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffbffff))
+#define SET_MS3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 19) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfff7ffff))
+#define SET_BIST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 20) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffefffff))
+#define SET_I2C_MST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 23) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xff7fffff))
+#define SET_BTCX_CSR_CLK_EN(_VAL_) (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_MCU_DBG_SEL(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_SEL)) & 0xffffffc0))
+#define SET_MCU_STOP_NOGRANT(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffeff))
+#define SET_MCU_STOP_ANYTIME(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffdff))
+#define SET_MCU_DBG_DATA(_VAL_) (REG32(ADR_MCU_DBG_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_DATA)) & 0x00000000))
+#define SET_AHB_SW_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffe))
+#define SET_AHB_ERR_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffd))
+#define SET_REG_AHB_DEBUG_MX(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffffcf))
+#define SET_REG_PKT_W_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffeff))
+#define SET_REG_PKT_R_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffdff))
+#define SET_IQ_SRAM_SEL_0(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffefff))
+#define SET_IQ_SRAM_SEL_1(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffdfff))
+#define SET_IQ_SRAM_SEL_2(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffbfff))
+#define SET_AHB_STATUS(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_AHB_BRG_STATUS)) & 0x0000ffff))
+#define SET_PARALLEL_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffffe))
+#define SET_MBRUN(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xffffffef))
+#define SET_SHIFT_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffeff))
+#define SET_MODE_REG_SI(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffdff))
+#define SET_SIMULATION_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffbff))
+#define SET_DBIST_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffff7ff))
+#define SET_MODE_REG_IN(_VAL_) (REG32(ADR_BIST_MODE_REG_IN)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN)) & 0xffe00000))
+#define SET_MODE_REG_OUT_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0xffe00000))
+#define SET_MODE_REG_SO_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0x7fffffff))
+#define SET_MONITOR_BUS_MCU_31_0(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0x00000000))
+#define SET_MONITOR_BUS_MCU_33_32(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0xfffffffc))
+#define SET_TB_ADR_SEL(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_TB_ADR_SEL)) & 0xffff0000))
+#define SET_TB_CS(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 31) | ((REG32(ADR_TB_ADR_SEL)) & 0x7fffffff))
+#define SET_TB_RDATA(_VAL_) (REG32(ADR_TB_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_TB_RDATA)) & 0x00000000))
+#define SET_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 0) | ((REG32(ADR_UART_W2B)) & 0xfffffffe))
+#define SET_DATA_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 4) | ((REG32(ADR_UART_W2B)) & 0xffffffef))
+#define SET_AHB_ILL_ADDR(_VAL_) (REG32(ADR_AHB_ILL_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILL_ADDR)) & 0x00000000))
+#define SET_AHB_FEN_ADDR(_VAL_) (REG32(ADR_AHB_FEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_FEN_ADDR)) & 0x00000000))
+#define SET_ILL_ADDR_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffe))
+#define SET_FENCE_HIT_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffd))
+#define SET_ILL_ADDR_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffef))
+#define SET_FENCE_HIT_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffdf))
+#define SET_PWM_INI_VALUE_P_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_A)) & 0xffffff00))
+#define SET_PWM_INI_VALUE_N_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_A)) & 0xffff00ff))
+#define SET_PWM_POST_SCALER_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_A)) & 0xfff0ffff))
+#define SET_PWM_ALWAYSON_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_A)) & 0xdfffffff))
+#define SET_PWM_INVERT_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_A)) & 0xbfffffff))
+#define SET_PWM_ENABLE_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_A)) & 0x7fffffff))
+#define SET_PWM_INI_VALUE_P_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_B)) & 0xffffff00))
+#define SET_PWM_INI_VALUE_N_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_B)) & 0xffff00ff))
+#define SET_PWM_POST_SCALER_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_B)) & 0xfff0ffff))
+#define SET_PWM_ALWAYSON_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_B)) & 0xdfffffff))
+#define SET_PWM_INVERT_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_B)) & 0xbfffffff))
+#define SET_PWM_ENABLE_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_B)) & 0x7fffffff))
+#define SET_HBUSREQ_LOCK(_VAL_) (REG32(ADR_HBUSREQ_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBUSREQ_LOCK)) & 0xffffe000))
+#define SET_HBURST_LOCK(_VAL_) (REG32(ADR_HBURST_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBURST_LOCK)) & 0xffffe000))
+#define SET_PRESCALER_USTIMER(_VAL_) (REG32(ADR_PRESCALER_USTIMER)) = (((_VAL_) << 0) | ((REG32(ADR_PRESCALER_USTIMER)) & 0xfffffe00))
+#define SET_MODE_REG_IN_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0xffff0000))
+#define SET_MODE_REG_OUT_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0xffff0000))
+#define SET_MODE_REG_SO_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x7fffffff))
+#define SET_MONITOR_BUS_MMU(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0xfff80000))
+#define SET_TEST_MODE0(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_TEST_MODE)) & 0xfffffffe))
+#define SET_TEST_MODE1(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_TEST_MODE)) & 0xfffffffd))
+#define SET_TEST_MODE2(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_TEST_MODE)) & 0xfffffffb))
+#define SET_TEST_MODE3(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_TEST_MODE)) & 0xfffffff7))
+#define SET_TEST_MODE4(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_TEST_MODE)) & 0xffffffef))
+#define SET_TEST_MODE_ALL(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_TEST_MODE)) & 0xffffffdf))
+#define SET_WDT_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffe))
+#define SET_SD_HOST_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffd))
+#define SET_ALLOW_SD_RESET(_VAL_) (REG32(ADR_SD_INIT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_SD_INIT_CFG)) & 0xfffffffe))
+#define SET_UART_NRTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffe))
+#define SET_UART_NCTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffd))
+#define SET_TU0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU0_TM_MODE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU0_TM_INT_MASK(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TU1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU1_TM_MODE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU1_TM_INT_MASK(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TU2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU2_TM_MODE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU2_TM_INT_MASK(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TU3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU3_TM_MODE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU3_TM_INT_MASK(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM0_TM_MODE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM0_TM_INT_MASK(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM1_TM_MODE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM1_TM_INT_MASK(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM2_TM_MODE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM2_TM_INT_MASK(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM3_TM_MODE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM3_TM_INT_MASK(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_MCU_WDT_TIME_CNT(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_WDOG_REG)) & 0xffff0000))
+#define SET_MCU_WDT_STATUS(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_MCU_WDOG_REG)) & 0xfffdffff))
+#define SET_MCU_WDOG_ENA(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_MCU_WDOG_REG)) & 0x7fffffff))
+#define SET_SYS_WDT_TIME_CNT(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_WDOG_REG)) & 0xffff0000))
+#define SET_SYS_WDT_STATUS(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYS_WDOG_REG)) & 0xfffdffff))
+#define SET_SYS_WDOG_ENA(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYS_WDOG_REG)) & 0x7fffffff))
+#define SET_XLNA_EN_O_OE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 0) | ((REG32(ADR_PAD6)) & 0xfffffffe))
+#define SET_XLNA_EN_O_PE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 1) | ((REG32(ADR_PAD6)) & 0xfffffffd))
+#define SET_PAD6_IE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 3) | ((REG32(ADR_PAD6)) & 0xfffffff7))
+#define SET_PAD6_SEL_I(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 4) | ((REG32(ADR_PAD6)) & 0xffffffcf))
+#define SET_PAD6_OD(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 8) | ((REG32(ADR_PAD6)) & 0xfffffeff))
+#define SET_PAD6_SEL_O(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 12) | ((REG32(ADR_PAD6)) & 0xffffefff))
+#define SET_XLNA_EN_O_C(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 28) | ((REG32(ADR_PAD6)) & 0xefffffff))
+#define SET_WIFI_TX_SW_O_OE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 0) | ((REG32(ADR_PAD7)) & 0xfffffffe))
+#define SET_WIFI_TX_SW_O_PE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 1) | ((REG32(ADR_PAD7)) & 0xfffffffd))
+#define SET_PAD7_IE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 3) | ((REG32(ADR_PAD7)) & 0xfffffff7))
+#define SET_PAD7_SEL_I(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 4) | ((REG32(ADR_PAD7)) & 0xffffffcf))
+#define SET_PAD7_OD(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 8) | ((REG32(ADR_PAD7)) & 0xfffffeff))
+#define SET_PAD7_SEL_O(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 12) | ((REG32(ADR_PAD7)) & 0xffffefff))
+#define SET_WIFI_TX_SW_O_C(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 28) | ((REG32(ADR_PAD7)) & 0xefffffff))
+#define SET_WIFI_RX_SW_O_OE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 0) | ((REG32(ADR_PAD8)) & 0xfffffffe))
+#define SET_WIFI_RX_SW_O_PE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 1) | ((REG32(ADR_PAD8)) & 0xfffffffd))
+#define SET_PAD8_IE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 3) | ((REG32(ADR_PAD8)) & 0xfffffff7))
+#define SET_PAD8_SEL_I(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 4) | ((REG32(ADR_PAD8)) & 0xffffffcf))
+#define SET_PAD8_OD(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 8) | ((REG32(ADR_PAD8)) & 0xfffffeff))
+#define SET_WIFI_RX_SW_O_C(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 28) | ((REG32(ADR_PAD8)) & 0xefffffff))
+#define SET_BT_SW_O_OE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 0) | ((REG32(ADR_PAD9)) & 0xfffffffe))
+#define SET_BT_SW_O_PE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 1) | ((REG32(ADR_PAD9)) & 0xfffffffd))
+#define SET_PAD9_IE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 3) | ((REG32(ADR_PAD9)) & 0xfffffff7))
+#define SET_PAD9_SEL_I(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 4) | ((REG32(ADR_PAD9)) & 0xffffffcf))
+#define SET_PAD9_OD(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 8) | ((REG32(ADR_PAD9)) & 0xfffffeff))
+#define SET_PAD9_SEL_O(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 12) | ((REG32(ADR_PAD9)) & 0xffffefff))
+#define SET_BT_SW_O_C(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 28) | ((REG32(ADR_PAD9)) & 0xefffffff))
+#define SET_XPA_EN_O_OE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 0) | ((REG32(ADR_PAD11)) & 0xfffffffe))
+#define SET_XPA_EN_O_PE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 1) | ((REG32(ADR_PAD11)) & 0xfffffffd))
+#define SET_PAD11_IE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 3) | ((REG32(ADR_PAD11)) & 0xfffffff7))
+#define SET_PAD11_SEL_I(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 4) | ((REG32(ADR_PAD11)) & 0xffffffcf))
+#define SET_PAD11_OD(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 8) | ((REG32(ADR_PAD11)) & 0xfffffeff))
+#define SET_PAD11_SEL_O(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 12) | ((REG32(ADR_PAD11)) & 0xffffefff))
+#define SET_XPA_EN_O_C(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 28) | ((REG32(ADR_PAD11)) & 0xefffffff))
+#define SET_PAD15_OE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 0) | ((REG32(ADR_PAD15)) & 0xfffffffe))
+#define SET_PAD15_PE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 1) | ((REG32(ADR_PAD15)) & 0xfffffffd))
+#define SET_PAD15_DS(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 2) | ((REG32(ADR_PAD15)) & 0xfffffffb))
+#define SET_PAD15_IE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 3) | ((REG32(ADR_PAD15)) & 0xfffffff7))
+#define SET_PAD15_SEL_I(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 4) | ((REG32(ADR_PAD15)) & 0xffffffcf))
+#define SET_PAD15_OD(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 8) | ((REG32(ADR_PAD15)) & 0xfffffeff))
+#define SET_PAD15_SEL_O(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 12) | ((REG32(ADR_PAD15)) & 0xffffefff))
+#define SET_TEST_1_ID(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 28) | ((REG32(ADR_PAD15)) & 0xefffffff))
+#define SET_PAD16_OE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 0) | ((REG32(ADR_PAD16)) & 0xfffffffe))
+#define SET_PAD16_PE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 1) | ((REG32(ADR_PAD16)) & 0xfffffffd))
+#define SET_PAD16_DS(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 2) | ((REG32(ADR_PAD16)) & 0xfffffffb))
+#define SET_PAD16_IE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 3) | ((REG32(ADR_PAD16)) & 0xfffffff7))
+#define SET_PAD16_SEL_I(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 4) | ((REG32(ADR_PAD16)) & 0xffffffcf))
+#define SET_PAD16_OD(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 8) | ((REG32(ADR_PAD16)) & 0xfffffeff))
+#define SET_PAD16_SEL_O(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 12) | ((REG32(ADR_PAD16)) & 0xffffefff))
+#define SET_TEST_2_ID(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 28) | ((REG32(ADR_PAD16)) & 0xefffffff))
+#define SET_PAD17_OE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 0) | ((REG32(ADR_PAD17)) & 0xfffffffe))
+#define SET_PAD17_PE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 1) | ((REG32(ADR_PAD17)) & 0xfffffffd))
+#define SET_PAD17_DS(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 2) | ((REG32(ADR_PAD17)) & 0xfffffffb))
+#define SET_PAD17_IE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 3) | ((REG32(ADR_PAD17)) & 0xfffffff7))
+#define SET_PAD17_SEL_I(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 4) | ((REG32(ADR_PAD17)) & 0xffffffcf))
+#define SET_PAD17_OD(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 8) | ((REG32(ADR_PAD17)) & 0xfffffeff))
+#define SET_PAD17_SEL_O(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 12) | ((REG32(ADR_PAD17)) & 0xffffefff))
+#define SET_TEST_3_ID(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 28) | ((REG32(ADR_PAD17)) & 0xefffffff))
+#define SET_PAD18_OE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 0) | ((REG32(ADR_PAD18)) & 0xfffffffe))
+#define SET_PAD18_PE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 1) | ((REG32(ADR_PAD18)) & 0xfffffffd))
+#define SET_PAD18_DS(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 2) | ((REG32(ADR_PAD18)) & 0xfffffffb))
+#define SET_PAD18_IE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 3) | ((REG32(ADR_PAD18)) & 0xfffffff7))
+#define SET_PAD18_SEL_I(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 4) | ((REG32(ADR_PAD18)) & 0xffffffcf))
+#define SET_PAD18_OD(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 8) | ((REG32(ADR_PAD18)) & 0xfffffeff))
+#define SET_PAD18_SEL_O(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 12) | ((REG32(ADR_PAD18)) & 0xffffcfff))
+#define SET_TEST_4_ID(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 28) | ((REG32(ADR_PAD18)) & 0xefffffff))
+#define SET_PAD19_OE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 0) | ((REG32(ADR_PAD19)) & 0xfffffffe))
+#define SET_PAD19_PE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 1) | ((REG32(ADR_PAD19)) & 0xfffffffd))
+#define SET_PAD19_DS(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 2) | ((REG32(ADR_PAD19)) & 0xfffffffb))
+#define SET_PAD19_IE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 3) | ((REG32(ADR_PAD19)) & 0xfffffff7))
+#define SET_PAD19_SEL_I(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 4) | ((REG32(ADR_PAD19)) & 0xffffffcf))
+#define SET_PAD19_OD(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 8) | ((REG32(ADR_PAD19)) & 0xfffffeff))
+#define SET_PAD19_SEL_O(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 12) | ((REG32(ADR_PAD19)) & 0xffff8fff))
+#define SET_SHORT_TO_20_ID(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 28) | ((REG32(ADR_PAD19)) & 0xefffffff))
+#define SET_PAD20_OE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 0) | ((REG32(ADR_PAD20)) & 0xfffffffe))
+#define SET_PAD20_PE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 1) | ((REG32(ADR_PAD20)) & 0xfffffffd))
+#define SET_PAD20_DS(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 2) | ((REG32(ADR_PAD20)) & 0xfffffffb))
+#define SET_PAD20_IE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 3) | ((REG32(ADR_PAD20)) & 0xfffffff7))
+#define SET_PAD20_SEL_I(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 4) | ((REG32(ADR_PAD20)) & 0xffffff0f))
+#define SET_PAD20_OD(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 8) | ((REG32(ADR_PAD20)) & 0xfffffeff))
+#define SET_PAD20_SEL_O(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 12) | ((REG32(ADR_PAD20)) & 0xffffcfff))
+#define SET_STRAP0(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 27) | ((REG32(ADR_PAD20)) & 0xf7ffffff))
+#define SET_GPIO_TEST_1_ID(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 28) | ((REG32(ADR_PAD20)) & 0xefffffff))
+#define SET_PAD21_OE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 0) | ((REG32(ADR_PAD21)) & 0xfffffffe))
+#define SET_PAD21_PE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 1) | ((REG32(ADR_PAD21)) & 0xfffffffd))
+#define SET_PAD21_DS(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 2) | ((REG32(ADR_PAD21)) & 0xfffffffb))
+#define SET_PAD21_IE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 3) | ((REG32(ADR_PAD21)) & 0xfffffff7))
+#define SET_PAD21_SEL_I(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 4) | ((REG32(ADR_PAD21)) & 0xffffff8f))
+#define SET_PAD21_OD(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 8) | ((REG32(ADR_PAD21)) & 0xfffffeff))
+#define SET_PAD21_SEL_O(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 12) | ((REG32(ADR_PAD21)) & 0xffffcfff))
+#define SET_STRAP3(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 27) | ((REG32(ADR_PAD21)) & 0xf7ffffff))
+#define SET_GPIO_TEST_2_ID(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 28) | ((REG32(ADR_PAD21)) & 0xefffffff))
+#define SET_PAD22_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 0) | ((REG32(ADR_PAD22)) & 0xfffffffe))
+#define SET_PAD22_PE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 1) | ((REG32(ADR_PAD22)) & 0xfffffffd))
+#define SET_PAD22_DS(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 2) | ((REG32(ADR_PAD22)) & 0xfffffffb))
+#define SET_PAD22_IE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 3) | ((REG32(ADR_PAD22)) & 0xfffffff7))
+#define SET_PAD22_SEL_I(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 4) | ((REG32(ADR_PAD22)) & 0xffffff8f))
+#define SET_PAD22_OD(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 8) | ((REG32(ADR_PAD22)) & 0xfffffeff))
+#define SET_PAD22_SEL_O(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 12) | ((REG32(ADR_PAD22)) & 0xffff8fff))
+#define SET_PAD22_SEL_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 20) | ((REG32(ADR_PAD22)) & 0xffefffff))
+#define SET_GPIO_TEST_3_ID(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 28) | ((REG32(ADR_PAD22)) & 0xefffffff))
+#define SET_PAD24_OE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 0) | ((REG32(ADR_PAD24)) & 0xfffffffe))
+#define SET_PAD24_PE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 1) | ((REG32(ADR_PAD24)) & 0xfffffffd))
+#define SET_PAD24_DS(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 2) | ((REG32(ADR_PAD24)) & 0xfffffffb))
+#define SET_PAD24_IE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 3) | ((REG32(ADR_PAD24)) & 0xfffffff7))
+#define SET_PAD24_SEL_I(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 4) | ((REG32(ADR_PAD24)) & 0xffffffcf))
+#define SET_PAD24_OD(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 8) | ((REG32(ADR_PAD24)) & 0xfffffeff))
+#define SET_PAD24_SEL_O(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 12) | ((REG32(ADR_PAD24)) & 0xffff8fff))
+#define SET_GPIO_TEST_4_ID(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 28) | ((REG32(ADR_PAD24)) & 0xefffffff))
+#define SET_PAD25_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 0) | ((REG32(ADR_PAD25)) & 0xfffffffe))
+#define SET_PAD25_PE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 1) | ((REG32(ADR_PAD25)) & 0xfffffffd))
+#define SET_PAD25_DS(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 2) | ((REG32(ADR_PAD25)) & 0xfffffffb))
+#define SET_PAD25_IE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 3) | ((REG32(ADR_PAD25)) & 0xfffffff7))
+#define SET_PAD25_SEL_I(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 4) | ((REG32(ADR_PAD25)) & 0xffffff8f))
+#define SET_PAD25_OD(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 8) | ((REG32(ADR_PAD25)) & 0xfffffeff))
+#define SET_PAD25_SEL_O(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 12) | ((REG32(ADR_PAD25)) & 0xffff8fff))
+#define SET_PAD25_SEL_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 20) | ((REG32(ADR_PAD25)) & 0xffefffff))
+#define SET_STRAP1(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 27) | ((REG32(ADR_PAD25)) & 0xf7ffffff))
+#define SET_GPIO_1_ID(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 28) | ((REG32(ADR_PAD25)) & 0xefffffff))
+#define SET_PAD27_OE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 0) | ((REG32(ADR_PAD27)) & 0xfffffffe))
+#define SET_PAD27_PE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 1) | ((REG32(ADR_PAD27)) & 0xfffffffd))
+#define SET_PAD27_DS(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 2) | ((REG32(ADR_PAD27)) & 0xfffffffb))
+#define SET_PAD27_IE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 3) | ((REG32(ADR_PAD27)) & 0xfffffff7))
+#define SET_PAD27_SEL_I(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 4) | ((REG32(ADR_PAD27)) & 0xffffff8f))
+#define SET_PAD27_OD(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 8) | ((REG32(ADR_PAD27)) & 0xfffffeff))
+#define SET_PAD27_SEL_O(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 12) | ((REG32(ADR_PAD27)) & 0xffff8fff))
+#define SET_GPIO_2_ID(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 28) | ((REG32(ADR_PAD27)) & 0xefffffff))
+#define SET_PAD28_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 0) | ((REG32(ADR_PAD28)) & 0xfffffffe))
+#define SET_PAD28_PE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 1) | ((REG32(ADR_PAD28)) & 0xfffffffd))
+#define SET_PAD28_DS(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 2) | ((REG32(ADR_PAD28)) & 0xfffffffb))
+#define SET_PAD28_IE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 3) | ((REG32(ADR_PAD28)) & 0xfffffff7))
+#define SET_PAD28_SEL_I(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 4) | ((REG32(ADR_PAD28)) & 0xffffff8f))
+#define SET_PAD28_OD(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 8) | ((REG32(ADR_PAD28)) & 0xfffffeff))
+#define SET_PAD28_SEL_O(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 12) | ((REG32(ADR_PAD28)) & 0xffff0fff))
+#define SET_PAD28_SEL_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 20) | ((REG32(ADR_PAD28)) & 0xffefffff))
+#define SET_GPIO_3_ID(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 28) | ((REG32(ADR_PAD28)) & 0xefffffff))
+#define SET_PAD29_OE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 0) | ((REG32(ADR_PAD29)) & 0xfffffffe))
+#define SET_PAD29_PE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 1) | ((REG32(ADR_PAD29)) & 0xfffffffd))
+#define SET_PAD29_DS(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 2) | ((REG32(ADR_PAD29)) & 0xfffffffb))
+#define SET_PAD29_IE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 3) | ((REG32(ADR_PAD29)) & 0xfffffff7))
+#define SET_PAD29_SEL_I(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 4) | ((REG32(ADR_PAD29)) & 0xffffff8f))
+#define SET_PAD29_OD(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 8) | ((REG32(ADR_PAD29)) & 0xfffffeff))
+#define SET_PAD29_SEL_O(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 12) | ((REG32(ADR_PAD29)) & 0xffff8fff))
+#define SET_GPIO_TEST_5_ID(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 28) | ((REG32(ADR_PAD29)) & 0xefffffff))
+#define SET_PAD30_OE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 0) | ((REG32(ADR_PAD30)) & 0xfffffffe))
+#define SET_PAD30_PE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 1) | ((REG32(ADR_PAD30)) & 0xfffffffd))
+#define SET_PAD30_DS(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 2) | ((REG32(ADR_PAD30)) & 0xfffffffb))
+#define SET_PAD30_IE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 3) | ((REG32(ADR_PAD30)) & 0xfffffff7))
+#define SET_PAD30_SEL_I(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 4) | ((REG32(ADR_PAD30)) & 0xffffffcf))
+#define SET_PAD30_OD(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 8) | ((REG32(ADR_PAD30)) & 0xfffffeff))
+#define SET_PAD30_SEL_O(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 12) | ((REG32(ADR_PAD30)) & 0xffffcfff))
+#define SET_TEST_6_ID(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 28) | ((REG32(ADR_PAD30)) & 0xefffffff))
+#define SET_PAD31_OE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 0) | ((REG32(ADR_PAD31)) & 0xfffffffe))
+#define SET_PAD31_PE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 1) | ((REG32(ADR_PAD31)) & 0xfffffffd))
+#define SET_PAD31_DS(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 2) | ((REG32(ADR_PAD31)) & 0xfffffffb))
+#define SET_PAD31_IE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 3) | ((REG32(ADR_PAD31)) & 0xfffffff7))
+#define SET_PAD31_SEL_I(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 4) | ((REG32(ADR_PAD31)) & 0xffffffcf))
+#define SET_PAD31_OD(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 8) | ((REG32(ADR_PAD31)) & 0xfffffeff))
+#define SET_PAD31_SEL_O(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 12) | ((REG32(ADR_PAD31)) & 0xffffcfff))
+#define SET_TEST_7_ID(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 28) | ((REG32(ADR_PAD31)) & 0xefffffff))
+#define SET_PAD32_OE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 0) | ((REG32(ADR_PAD32)) & 0xfffffffe))
+#define SET_PAD32_PE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 1) | ((REG32(ADR_PAD32)) & 0xfffffffd))
+#define SET_PAD32_DS(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 2) | ((REG32(ADR_PAD32)) & 0xfffffffb))
+#define SET_PAD32_IE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 3) | ((REG32(ADR_PAD32)) & 0xfffffff7))
+#define SET_PAD32_SEL_I(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 4) | ((REG32(ADR_PAD32)) & 0xffffffcf))
+#define SET_PAD32_OD(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 8) | ((REG32(ADR_PAD32)) & 0xfffffeff))
+#define SET_PAD32_SEL_O(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 12) | ((REG32(ADR_PAD32)) & 0xffffcfff))
+#define SET_TEST_8_ID(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 28) | ((REG32(ADR_PAD32)) & 0xefffffff))
+#define SET_PAD33_OE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 0) | ((REG32(ADR_PAD33)) & 0xfffffffe))
+#define SET_PAD33_PE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 1) | ((REG32(ADR_PAD33)) & 0xfffffffd))
+#define SET_PAD33_DS(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 2) | ((REG32(ADR_PAD33)) & 0xfffffffb))
+#define SET_PAD33_IE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 3) | ((REG32(ADR_PAD33)) & 0xfffffff7))
+#define SET_PAD33_SEL_I(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 4) | ((REG32(ADR_PAD33)) & 0xffffffcf))
+#define SET_PAD33_OD(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 8) | ((REG32(ADR_PAD33)) & 0xfffffeff))
+#define SET_PAD33_SEL_O(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 12) | ((REG32(ADR_PAD33)) & 0xffffcfff))
+#define SET_TEST_9_ID(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 28) | ((REG32(ADR_PAD33)) & 0xefffffff))
+#define SET_PAD34_OE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 0) | ((REG32(ADR_PAD34)) & 0xfffffffe))
+#define SET_PAD34_PE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 1) | ((REG32(ADR_PAD34)) & 0xfffffffd))
+#define SET_PAD34_DS(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 2) | ((REG32(ADR_PAD34)) & 0xfffffffb))
+#define SET_PAD34_IE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 3) | ((REG32(ADR_PAD34)) & 0xfffffff7))
+#define SET_PAD34_SEL_I(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 4) | ((REG32(ADR_PAD34)) & 0xffffffcf))
+#define SET_PAD34_OD(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 8) | ((REG32(ADR_PAD34)) & 0xfffffeff))
+#define SET_PAD34_SEL_O(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 12) | ((REG32(ADR_PAD34)) & 0xffffcfff))
+#define SET_TEST_10_ID(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 28) | ((REG32(ADR_PAD34)) & 0xefffffff))
+#define SET_PAD42_OE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 0) | ((REG32(ADR_PAD42)) & 0xfffffffe))
+#define SET_PAD42_PE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 1) | ((REG32(ADR_PAD42)) & 0xfffffffd))
+#define SET_PAD42_DS(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 2) | ((REG32(ADR_PAD42)) & 0xfffffffb))
+#define SET_PAD42_IE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 3) | ((REG32(ADR_PAD42)) & 0xfffffff7))
+#define SET_PAD42_SEL_I(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 4) | ((REG32(ADR_PAD42)) & 0xffffffcf))
+#define SET_PAD42_OD(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 8) | ((REG32(ADR_PAD42)) & 0xfffffeff))
+#define SET_PAD42_SEL_O(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 12) | ((REG32(ADR_PAD42)) & 0xffffefff))
+#define SET_TEST_11_ID(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 28) | ((REG32(ADR_PAD42)) & 0xefffffff))
+#define SET_PAD43_OE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 0) | ((REG32(ADR_PAD43)) & 0xfffffffe))
+#define SET_PAD43_PE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 1) | ((REG32(ADR_PAD43)) & 0xfffffffd))
+#define SET_PAD43_DS(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 2) | ((REG32(ADR_PAD43)) & 0xfffffffb))
+#define SET_PAD43_IE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 3) | ((REG32(ADR_PAD43)) & 0xfffffff7))
+#define SET_PAD43_SEL_I(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 4) | ((REG32(ADR_PAD43)) & 0xffffffcf))
+#define SET_PAD43_OD(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 8) | ((REG32(ADR_PAD43)) & 0xfffffeff))
+#define SET_PAD43_SEL_O(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 12) | ((REG32(ADR_PAD43)) & 0xffffefff))
+#define SET_TEST_12_ID(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 28) | ((REG32(ADR_PAD43)) & 0xefffffff))
+#define SET_PAD44_OE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 0) | ((REG32(ADR_PAD44)) & 0xfffffffe))
+#define SET_PAD44_PE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 1) | ((REG32(ADR_PAD44)) & 0xfffffffd))
+#define SET_PAD44_DS(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 2) | ((REG32(ADR_PAD44)) & 0xfffffffb))
+#define SET_PAD44_IE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 3) | ((REG32(ADR_PAD44)) & 0xfffffff7))
+#define SET_PAD44_SEL_I(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 4) | ((REG32(ADR_PAD44)) & 0xffffffcf))
+#define SET_PAD44_OD(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 8) | ((REG32(ADR_PAD44)) & 0xfffffeff))
+#define SET_PAD44_SEL_O(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 12) | ((REG32(ADR_PAD44)) & 0xffffcfff))
+#define SET_TEST_13_ID(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 28) | ((REG32(ADR_PAD44)) & 0xefffffff))
+#define SET_PAD45_OE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 0) | ((REG32(ADR_PAD45)) & 0xfffffffe))
+#define SET_PAD45_PE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 1) | ((REG32(ADR_PAD45)) & 0xfffffffd))
+#define SET_PAD45_DS(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 2) | ((REG32(ADR_PAD45)) & 0xfffffffb))
+#define SET_PAD45_IE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 3) | ((REG32(ADR_PAD45)) & 0xfffffff7))
+#define SET_PAD45_SEL_I(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 4) | ((REG32(ADR_PAD45)) & 0xffffffcf))
+#define SET_PAD45_OD(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 8) | ((REG32(ADR_PAD45)) & 0xfffffeff))
+#define SET_PAD45_SEL_O(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 12) | ((REG32(ADR_PAD45)) & 0xffffcfff))
+#define SET_TEST_14_ID(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 28) | ((REG32(ADR_PAD45)) & 0xefffffff))
+#define SET_PAD46_OE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 0) | ((REG32(ADR_PAD46)) & 0xfffffffe))
+#define SET_PAD46_PE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 1) | ((REG32(ADR_PAD46)) & 0xfffffffd))
+#define SET_PAD46_DS(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 2) | ((REG32(ADR_PAD46)) & 0xfffffffb))
+#define SET_PAD46_IE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 3) | ((REG32(ADR_PAD46)) & 0xfffffff7))
+#define SET_PAD46_SEL_I(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 4) | ((REG32(ADR_PAD46)) & 0xffffffcf))
+#define SET_PAD46_OD(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 8) | ((REG32(ADR_PAD46)) & 0xfffffeff))
+#define SET_PAD46_SEL_O(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 12) | ((REG32(ADR_PAD46)) & 0xffffcfff))
+#define SET_TEST_15_ID(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 28) | ((REG32(ADR_PAD46)) & 0xefffffff))
+#define SET_PAD47_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 0) | ((REG32(ADR_PAD47)) & 0xfffffffe))
+#define SET_PAD47_PE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 1) | ((REG32(ADR_PAD47)) & 0xfffffffd))
+#define SET_PAD47_DS(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 2) | ((REG32(ADR_PAD47)) & 0xfffffffb))
+#define SET_PAD47_SEL_I(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 4) | ((REG32(ADR_PAD47)) & 0xffffffcf))
+#define SET_PAD47_OD(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 8) | ((REG32(ADR_PAD47)) & 0xfffffeff))
+#define SET_PAD47_SEL_O(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 12) | ((REG32(ADR_PAD47)) & 0xffffcfff))
+#define SET_PAD47_SEL_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 20) | ((REG32(ADR_PAD47)) & 0xffefffff))
+#define SET_GPIO_9_ID(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 28) | ((REG32(ADR_PAD47)) & 0xefffffff))
+#define SET_PAD48_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 0) | ((REG32(ADR_PAD48)) & 0xfffffffe))
+#define SET_PAD48_PE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 1) | ((REG32(ADR_PAD48)) & 0xfffffffd))
+#define SET_PAD48_DS(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 2) | ((REG32(ADR_PAD48)) & 0xfffffffb))
+#define SET_PAD48_IE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 3) | ((REG32(ADR_PAD48)) & 0xfffffff7))
+#define SET_PAD48_SEL_I(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 4) | ((REG32(ADR_PAD48)) & 0xffffff8f))
+#define SET_PAD48_OD(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 8) | ((REG32(ADR_PAD48)) & 0xfffffeff))
+#define SET_PAD48_PE_SEL(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 11) | ((REG32(ADR_PAD48)) & 0xfffff7ff))
+#define SET_PAD48_SEL_O(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 12) | ((REG32(ADR_PAD48)) & 0xffffcfff))
+#define SET_PAD48_SEL_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 20) | ((REG32(ADR_PAD48)) & 0xffefffff))
+#define SET_GPIO_10_ID(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 28) | ((REG32(ADR_PAD48)) & 0xefffffff))
+#define SET_PAD49_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 0) | ((REG32(ADR_PAD49)) & 0xfffffffe))
+#define SET_PAD49_PE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 1) | ((REG32(ADR_PAD49)) & 0xfffffffd))
+#define SET_PAD49_DS(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 2) | ((REG32(ADR_PAD49)) & 0xfffffffb))
+#define SET_PAD49_IE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 3) | ((REG32(ADR_PAD49)) & 0xfffffff7))
+#define SET_PAD49_SEL_I(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 4) | ((REG32(ADR_PAD49)) & 0xffffff8f))
+#define SET_PAD49_OD(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 8) | ((REG32(ADR_PAD49)) & 0xfffffeff))
+#define SET_PAD49_SEL_O(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 12) | ((REG32(ADR_PAD49)) & 0xffffcfff))
+#define SET_PAD49_SEL_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 20) | ((REG32(ADR_PAD49)) & 0xffefffff))
+#define SET_GPIO_11_ID(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 28) | ((REG32(ADR_PAD49)) & 0xefffffff))
+#define SET_PAD50_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 0) | ((REG32(ADR_PAD50)) & 0xfffffffe))
+#define SET_PAD50_PE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 1) | ((REG32(ADR_PAD50)) & 0xfffffffd))
+#define SET_PAD50_DS(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 2) | ((REG32(ADR_PAD50)) & 0xfffffffb))
+#define SET_PAD50_IE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 3) | ((REG32(ADR_PAD50)) & 0xfffffff7))
+#define SET_PAD50_SEL_I(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 4) | ((REG32(ADR_PAD50)) & 0xffffff8f))
+#define SET_PAD50_OD(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 8) | ((REG32(ADR_PAD50)) & 0xfffffeff))
+#define SET_PAD50_SEL_O(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 12) | ((REG32(ADR_PAD50)) & 0xffffcfff))
+#define SET_PAD50_SEL_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 20) | ((REG32(ADR_PAD50)) & 0xffefffff))
+#define SET_GPIO_12_ID(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 28) | ((REG32(ADR_PAD50)) & 0xefffffff))
+#define SET_PAD51_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 0) | ((REG32(ADR_PAD51)) & 0xfffffffe))
+#define SET_PAD51_PE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 1) | ((REG32(ADR_PAD51)) & 0xfffffffd))
+#define SET_PAD51_DS(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 2) | ((REG32(ADR_PAD51)) & 0xfffffffb))
+#define SET_PAD51_IE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 3) | ((REG32(ADR_PAD51)) & 0xfffffff7))
+#define SET_PAD51_SEL_I(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 4) | ((REG32(ADR_PAD51)) & 0xffffffcf))
+#define SET_PAD51_OD(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 8) | ((REG32(ADR_PAD51)) & 0xfffffeff))
+#define SET_PAD51_SEL_O(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 12) | ((REG32(ADR_PAD51)) & 0xffffefff))
+#define SET_PAD51_SEL_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 20) | ((REG32(ADR_PAD51)) & 0xffefffff))
+#define SET_GPIO_13_ID(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 28) | ((REG32(ADR_PAD51)) & 0xefffffff))
+#define SET_PAD52_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 0) | ((REG32(ADR_PAD52)) & 0xfffffffe))
+#define SET_PAD52_PE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 1) | ((REG32(ADR_PAD52)) & 0xfffffffd))
+#define SET_PAD52_DS(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 2) | ((REG32(ADR_PAD52)) & 0xfffffffb))
+#define SET_PAD52_SEL_I(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 4) | ((REG32(ADR_PAD52)) & 0xffffffcf))
+#define SET_PAD52_OD(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 8) | ((REG32(ADR_PAD52)) & 0xfffffeff))
+#define SET_PAD52_SEL_O(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 12) | ((REG32(ADR_PAD52)) & 0xffffefff))
+#define SET_PAD52_SEL_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 20) | ((REG32(ADR_PAD52)) & 0xffefffff))
+#define SET_GPIO_14_ID(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 28) | ((REG32(ADR_PAD52)) & 0xefffffff))
+#define SET_PAD53_OE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 0) | ((REG32(ADR_PAD53)) & 0xfffffffe))
+#define SET_PAD53_PE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 1) | ((REG32(ADR_PAD53)) & 0xfffffffd))
+#define SET_PAD53_DS(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 2) | ((REG32(ADR_PAD53)) & 0xfffffffb))
+#define SET_PAD53_IE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 3) | ((REG32(ADR_PAD53)) & 0xfffffff7))
+#define SET_PAD53_SEL_I(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 4) | ((REG32(ADR_PAD53)) & 0xffffffcf))
+#define SET_PAD53_OD(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 8) | ((REG32(ADR_PAD53)) & 0xfffffeff))
+#define SET_PAD53_SEL_O(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 12) | ((REG32(ADR_PAD53)) & 0xffffefff))
+#define SET_JTAG_TMS_ID(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 28) | ((REG32(ADR_PAD53)) & 0xefffffff))
+#define SET_PAD54_OE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 0) | ((REG32(ADR_PAD54)) & 0xfffffffe))
+#define SET_PAD54_PE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 1) | ((REG32(ADR_PAD54)) & 0xfffffffd))
+#define SET_PAD54_DS(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 2) | ((REG32(ADR_PAD54)) & 0xfffffffb))
+#define SET_PAD54_OD(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 8) | ((REG32(ADR_PAD54)) & 0xfffffeff))
+#define SET_PAD54_SEL_O(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 12) | ((REG32(ADR_PAD54)) & 0xffffcfff))
+#define SET_JTAG_TCK_ID(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 28) | ((REG32(ADR_PAD54)) & 0xefffffff))
+#define SET_PAD56_PE(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 1) | ((REG32(ADR_PAD56)) & 0xfffffffd))
+#define SET_PAD56_DS(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 2) | ((REG32(ADR_PAD56)) & 0xfffffffb))
+#define SET_PAD56_SEL_I(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 4) | ((REG32(ADR_PAD56)) & 0xffffffef))
+#define SET_PAD56_OD(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 8) | ((REG32(ADR_PAD56)) & 0xfffffeff))
+#define SET_JTAG_TDI_ID(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 28) | ((REG32(ADR_PAD56)) & 0xefffffff))
+#define SET_PAD57_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 0) | ((REG32(ADR_PAD57)) & 0xfffffffe))
+#define SET_PAD57_PE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 1) | ((REG32(ADR_PAD57)) & 0xfffffffd))
+#define SET_PAD57_DS(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 2) | ((REG32(ADR_PAD57)) & 0xfffffffb))
+#define SET_PAD57_IE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 3) | ((REG32(ADR_PAD57)) & 0xfffffff7))
+#define SET_PAD57_SEL_I(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 4) | ((REG32(ADR_PAD57)) & 0xffffffcf))
+#define SET_PAD57_OD(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 8) | ((REG32(ADR_PAD57)) & 0xfffffeff))
+#define SET_PAD57_SEL_O(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 12) | ((REG32(ADR_PAD57)) & 0xffffcfff))
+#define SET_PAD57_SEL_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 20) | ((REG32(ADR_PAD57)) & 0xffefffff))
+#define SET_JTAG_TDO_ID(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 28) | ((REG32(ADR_PAD57)) & 0xefffffff))
+#define SET_PAD58_OE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 0) | ((REG32(ADR_PAD58)) & 0xfffffffe))
+#define SET_PAD58_PE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 1) | ((REG32(ADR_PAD58)) & 0xfffffffd))
+#define SET_PAD58_DS(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 2) | ((REG32(ADR_PAD58)) & 0xfffffffb))
+#define SET_PAD58_IE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 3) | ((REG32(ADR_PAD58)) & 0xfffffff7))
+#define SET_PAD58_SEL_I(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 4) | ((REG32(ADR_PAD58)) & 0xffffffcf))
+#define SET_PAD58_OD(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 8) | ((REG32(ADR_PAD58)) & 0xfffffeff))
+#define SET_PAD58_SEL_O(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 12) | ((REG32(ADR_PAD58)) & 0xffffefff))
+#define SET_TEST_16_ID(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 28) | ((REG32(ADR_PAD58)) & 0xefffffff))
+#define SET_PAD59_OE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 0) | ((REG32(ADR_PAD59)) & 0xfffffffe))
+#define SET_PAD59_PE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 1) | ((REG32(ADR_PAD59)) & 0xfffffffd))
+#define SET_PAD59_DS(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 2) | ((REG32(ADR_PAD59)) & 0xfffffffb))
+#define SET_PAD59_IE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 3) | ((REG32(ADR_PAD59)) & 0xfffffff7))
+#define SET_PAD59_SEL_I(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 4) | ((REG32(ADR_PAD59)) & 0xffffffcf))
+#define SET_PAD59_OD(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 8) | ((REG32(ADR_PAD59)) & 0xfffffeff))
+#define SET_PAD59_SEL_O(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 12) | ((REG32(ADR_PAD59)) & 0xffffefff))
+#define SET_TEST_17_ID(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 28) | ((REG32(ADR_PAD59)) & 0xefffffff))
+#define SET_PAD60_OE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 0) | ((REG32(ADR_PAD60)) & 0xfffffffe))
+#define SET_PAD60_PE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 1) | ((REG32(ADR_PAD60)) & 0xfffffffd))
+#define SET_PAD60_DS(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 2) | ((REG32(ADR_PAD60)) & 0xfffffffb))
+#define SET_PAD60_IE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 3) | ((REG32(ADR_PAD60)) & 0xfffffff7))
+#define SET_PAD60_SEL_I(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 4) | ((REG32(ADR_PAD60)) & 0xffffffcf))
+#define SET_PAD60_OD(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 8) | ((REG32(ADR_PAD60)) & 0xfffffeff))
+#define SET_PAD60_SEL_O(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 12) | ((REG32(ADR_PAD60)) & 0xffffefff))
+#define SET_TEST_18_ID(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 28) | ((REG32(ADR_PAD60)) & 0xefffffff))
+#define SET_PAD61_OE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 0) | ((REG32(ADR_PAD61)) & 0xfffffffe))
+#define SET_PAD61_PE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 1) | ((REG32(ADR_PAD61)) & 0xfffffffd))
+#define SET_PAD61_DS(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 2) | ((REG32(ADR_PAD61)) & 0xfffffffb))
+#define SET_PAD61_IE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 3) | ((REG32(ADR_PAD61)) & 0xfffffff7))
+#define SET_PAD61_SEL_I(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 4) | ((REG32(ADR_PAD61)) & 0xffffffef))
+#define SET_PAD61_OD(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 8) | ((REG32(ADR_PAD61)) & 0xfffffeff))
+#define SET_PAD61_SEL_O(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 12) | ((REG32(ADR_PAD61)) & 0xffffcfff))
+#define SET_TEST_19_ID(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 28) | ((REG32(ADR_PAD61)) & 0xefffffff))
+#define SET_PAD62_OE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 0) | ((REG32(ADR_PAD62)) & 0xfffffffe))
+#define SET_PAD62_PE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 1) | ((REG32(ADR_PAD62)) & 0xfffffffd))
+#define SET_PAD62_DS(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 2) | ((REG32(ADR_PAD62)) & 0xfffffffb))
+#define SET_PAD62_IE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 3) | ((REG32(ADR_PAD62)) & 0xfffffff7))
+#define SET_PAD62_SEL_I(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 4) | ((REG32(ADR_PAD62)) & 0xffffffef))
+#define SET_PAD62_OD(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 8) | ((REG32(ADR_PAD62)) & 0xfffffeff))
+#define SET_PAD62_SEL_O(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 12) | ((REG32(ADR_PAD62)) & 0xffffefff))
+#define SET_TEST_20_ID(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 28) | ((REG32(ADR_PAD62)) & 0xefffffff))
+#define SET_PAD64_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 0) | ((REG32(ADR_PAD64)) & 0xfffffffe))
+#define SET_PAD64_PE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 1) | ((REG32(ADR_PAD64)) & 0xfffffffd))
+#define SET_PAD64_DS(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 2) | ((REG32(ADR_PAD64)) & 0xfffffffb))
+#define SET_PAD64_IE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 3) | ((REG32(ADR_PAD64)) & 0xfffffff7))
+#define SET_PAD64_SEL_I(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 4) | ((REG32(ADR_PAD64)) & 0xffffff8f))
+#define SET_PAD64_OD(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 8) | ((REG32(ADR_PAD64)) & 0xfffffeff))
+#define SET_PAD64_SEL_O(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 12) | ((REG32(ADR_PAD64)) & 0xffffcfff))
+#define SET_PAD64_SEL_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 20) | ((REG32(ADR_PAD64)) & 0xffefffff))
+#define SET_GPIO_15_IP_ID(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 28) | ((REG32(ADR_PAD64)) & 0xefffffff))
+#define SET_PAD65_OE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 0) | ((REG32(ADR_PAD65)) & 0xfffffffe))
+#define SET_PAD65_PE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 1) | ((REG32(ADR_PAD65)) & 0xfffffffd))
+#define SET_PAD65_DS(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 2) | ((REG32(ADR_PAD65)) & 0xfffffffb))
+#define SET_PAD65_IE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 3) | ((REG32(ADR_PAD65)) & 0xfffffff7))
+#define SET_PAD65_SEL_I(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 4) | ((REG32(ADR_PAD65)) & 0xffffff8f))
+#define SET_PAD65_OD(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 8) | ((REG32(ADR_PAD65)) & 0xfffffeff))
+#define SET_PAD65_SEL_O(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 12) | ((REG32(ADR_PAD65)) & 0xffffefff))
+#define SET_GPIO_TEST_7_IN_ID(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 28) | ((REG32(ADR_PAD65)) & 0xefffffff))
+#define SET_PAD66_OE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 0) | ((REG32(ADR_PAD66)) & 0xfffffffe))
+#define SET_PAD66_PE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 1) | ((REG32(ADR_PAD66)) & 0xfffffffd))
+#define SET_PAD66_DS(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 2) | ((REG32(ADR_PAD66)) & 0xfffffffb))
+#define SET_PAD66_IE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 3) | ((REG32(ADR_PAD66)) & 0xfffffff7))
+#define SET_PAD66_SEL_I(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 4) | ((REG32(ADR_PAD66)) & 0xffffffcf))
+#define SET_PAD66_OD(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 8) | ((REG32(ADR_PAD66)) & 0xfffffeff))
+#define SET_PAD66_SEL_O(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 12) | ((REG32(ADR_PAD66)) & 0xffffcfff))
+#define SET_GPIO_17_QP_ID(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 28) | ((REG32(ADR_PAD66)) & 0xefffffff))
+#define SET_PAD68_OE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 0) | ((REG32(ADR_PAD68)) & 0xfffffffe))
+#define SET_PAD68_PE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 1) | ((REG32(ADR_PAD68)) & 0xfffffffd))
+#define SET_PAD68_DS(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 2) | ((REG32(ADR_PAD68)) & 0xfffffffb))
+#define SET_PAD68_IE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 3) | ((REG32(ADR_PAD68)) & 0xfffffff7))
+#define SET_PAD68_OD(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 8) | ((REG32(ADR_PAD68)) & 0xfffffeff))
+#define SET_PAD68_SEL_O(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 12) | ((REG32(ADR_PAD68)) & 0xffffefff))
+#define SET_GPIO_19_ID(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 28) | ((REG32(ADR_PAD68)) & 0xefffffff))
+#define SET_PAD67_OE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 0) | ((REG32(ADR_PAD67)) & 0xfffffffe))
+#define SET_PAD67_PE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 1) | ((REG32(ADR_PAD67)) & 0xfffffffd))
+#define SET_PAD67_DS(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 2) | ((REG32(ADR_PAD67)) & 0xfffffffb))
+#define SET_PAD67_IE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 3) | ((REG32(ADR_PAD67)) & 0xfffffff7))
+#define SET_PAD67_SEL_I(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 4) | ((REG32(ADR_PAD67)) & 0xffffff8f))
+#define SET_PAD67_OD(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 8) | ((REG32(ADR_PAD67)) & 0xfffffeff))
+#define SET_PAD67_SEL_O(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 12) | ((REG32(ADR_PAD67)) & 0xffffcfff))
+#define SET_GPIO_TEST_8_QN_ID(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 28) | ((REG32(ADR_PAD67)) & 0xefffffff))
+#define SET_PAD69_OE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 0) | ((REG32(ADR_PAD69)) & 0xfffffffe))
+#define SET_PAD69_PE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 1) | ((REG32(ADR_PAD69)) & 0xfffffffd))
+#define SET_PAD69_DS(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 2) | ((REG32(ADR_PAD69)) & 0xfffffffb))
+#define SET_PAD69_IE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 3) | ((REG32(ADR_PAD69)) & 0xfffffff7))
+#define SET_PAD69_SEL_I(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 4) | ((REG32(ADR_PAD69)) & 0xffffffcf))
+#define SET_PAD69_OD(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 8) | ((REG32(ADR_PAD69)) & 0xfffffeff))
+#define SET_PAD69_SEL_O(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 12) | ((REG32(ADR_PAD69)) & 0xffffefff))
+#define SET_STRAP2(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 27) | ((REG32(ADR_PAD69)) & 0xf7ffffff))
+#define SET_GPIO_20_ID(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 28) | ((REG32(ADR_PAD69)) & 0xefffffff))
+#define SET_PAD70_OE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 0) | ((REG32(ADR_PAD70)) & 0xfffffffe))
+#define SET_PAD70_PE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 1) | ((REG32(ADR_PAD70)) & 0xfffffffd))
+#define SET_PAD70_DS(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 2) | ((REG32(ADR_PAD70)) & 0xfffffffb))
+#define SET_PAD70_IE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 3) | ((REG32(ADR_PAD70)) & 0xfffffff7))
+#define SET_PAD70_SEL_I(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 4) | ((REG32(ADR_PAD70)) & 0xffffffcf))
+#define SET_PAD70_OD(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 8) | ((REG32(ADR_PAD70)) & 0xfffffeff))
+#define SET_PAD70_SEL_O(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 12) | ((REG32(ADR_PAD70)) & 0xffff8fff))
+#define SET_GPIO_21_ID(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 28) | ((REG32(ADR_PAD70)) & 0xefffffff))
+#define SET_PAD231_OE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 0) | ((REG32(ADR_PAD231)) & 0xfffffffe))
+#define SET_PAD231_PE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 1) | ((REG32(ADR_PAD231)) & 0xfffffffd))
+#define SET_PAD231_DS(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 2) | ((REG32(ADR_PAD231)) & 0xfffffffb))
+#define SET_PAD231_IE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 3) | ((REG32(ADR_PAD231)) & 0xfffffff7))
+#define SET_PAD231_OD(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 8) | ((REG32(ADR_PAD231)) & 0xfffffeff))
+#define SET_PIN_40_OR_56_ID(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 28) | ((REG32(ADR_PAD231)) & 0xefffffff))
+#define SET_MP_PHY2RX_DATA__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffe))
+#define SET_MP_PHY2RX_DATA__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffd))
+#define SET_MP_TX_FF_RPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 2) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffb))
+#define SET_MP_RX_FF_WPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 3) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffff7))
+#define SET_MP_RX_FF_WPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 4) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffef))
+#define SET_MP_RX_FF_WPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 5) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffdf))
+#define SET_MP_PHY2RX_DATA__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 6) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffbf))
+#define SET_MP_PHY2RX_DATA__4_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 7) | ((REG32(ADR_PIN_SEL_0)) & 0xffffff7f))
+#define SET_I2CM_SDA_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 8) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffcff))
+#define SET_CRYSTAL_OUT_REQ_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 10) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffbff))
+#define SET_MP_PHY2RX_DATA__5_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 11) | ((REG32(ADR_PIN_SEL_0)) & 0xfffff7ff))
+#define SET_MP_PHY2RX_DATA__3_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 12) | ((REG32(ADR_PIN_SEL_0)) & 0xffffefff))
+#define SET_UART_RXD_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 13) | ((REG32(ADR_PIN_SEL_0)) & 0xffff9fff))
+#define SET_MP_PHY2RX_DATA__6_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 15) | ((REG32(ADR_PIN_SEL_0)) & 0xffff7fff))
+#define SET_DAT_UART_NCTS_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 16) | ((REG32(ADR_PIN_SEL_0)) & 0xfffeffff))
+#define SET_GPIO_LOG_STOP_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 17) | ((REG32(ADR_PIN_SEL_0)) & 0xfff1ffff))
+#define SET_MP_TX_FF_RPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 20) | ((REG32(ADR_PIN_SEL_0)) & 0xffefffff))
+#define SET_MP_PHY_RX_WRST_N_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 21) | ((REG32(ADR_PIN_SEL_0)) & 0xffdfffff))
+#define SET_EXT_32K_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 22) | ((REG32(ADR_PIN_SEL_0)) & 0xff3fffff))
+#define SET_MP_PHY2RX_DATA__7_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 24) | ((REG32(ADR_PIN_SEL_0)) & 0xfeffffff))
+#define SET_MP_TX_FF_RPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 25) | ((REG32(ADR_PIN_SEL_0)) & 0xfdffffff))
+#define SET_PMUINT_WAKE_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 26) | ((REG32(ADR_PIN_SEL_0)) & 0xe3ffffff))
+#define SET_I2CM_SCL_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 29) | ((REG32(ADR_PIN_SEL_0)) & 0xdfffffff))
+#define SET_MP_MRX_RX_EN_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 30) | ((REG32(ADR_PIN_SEL_0)) & 0xbfffffff))
+#define SET_DAT_UART_RXD_SEL_0(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 31) | ((REG32(ADR_PIN_SEL_0)) & 0x7fffffff))
+#define SET_DAT_UART_RXD_SEL_1(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffe))
+#define SET_SPI_DI_SEL(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffd))
+#define SET_IO_PORT_REG(_VAL_) (REG32(ADR_IO_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_PORT_REG)) & 0xfffe0000))
+#define SET_MASK_RX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffe))
+#define SET_MASK_TX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffd))
+#define SET_MASK_SOC_SYSTEM_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffb))
+#define SET_EDCA0_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffff7))
+#define SET_EDCA1_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffef))
+#define SET_EDCA2_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffdf))
+#define SET_EDCA3_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffbf))
+#define SET_TX_LIMIT_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_MASK_REG)) & 0xffffff7f))
+#define SET_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffe))
+#define SET_TX_COMPLETE_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffd))
+#define SET_SOC_SYSTEM_INT_STATUS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffb))
+#define SET_EDCA0_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffff7))
+#define SET_EDCA1_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffef))
+#define SET_EDCA2_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffdf))
+#define SET_EDCA3_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffbf))
+#define SET_TX_LIMIT_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffff7f))
+#define SET_HOST_TRIGGERED_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffeff))
+#define SET_HOST_TRIGGERED_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 9) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffdff))
+#define SET_SOC_TRIGGER_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 10) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffbff))
+#define SET_SOC_TRIGGER_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 11) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffff7ff))
+#define SET_RDY_FOR_TX_RX(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffe))
+#define SET_RDY_FOR_FW_DOWNLOAD(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffd))
+#define SET_ILLEGAL_CMD_RESP_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffb))
+#define SET_SDIO_TRX_DATA_SEQUENCE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffff7))
+#define SET_GPIO_INT_TRIGGER_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffffef))
+#define SET_TRIGGER_FUNCTION_SETTING(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff9f))
+#define SET_CMD52_ABORT_RESPONSE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff7f))
+#define SET_RX_PACKET_LENGTH(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xffff0000))
+#define SET_CARD_FW_DL_STATUS(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 16) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xff00ffff))
+#define SET_TX_RX_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 24) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfeffffff))
+#define SET_SDIO_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 25) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfdffffff))
+#define SET_CMD52_ABORT_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 28) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xefffffff))
+#define SET_CMD52_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 29) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xdfffffff))
+#define SET_SDIO_PARTIAL_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 30) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xbfffffff))
+#define SET_SDIO_ALL_RESE_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 31) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x7fffffff))
+#define SET_RX_PACKET_LENGTH2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xffff0000))
+#define SET_RX_INT1(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffeffff))
+#define SET_TX_DONE(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffdffff))
+#define SET_HCI_TRX_FINISH(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffbffff))
+#define SET_ALLOCATE_STATUS(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfff7ffff))
+#define SET_HCI_INPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xff0fffff))
+#define SET_HCI_OUTPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xe0ffffff))
+#define SET_AHB_HANG4(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 29) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xdfffffff))
+#define SET_HCI_IN_QUE_EMPTY(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 30) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xbfffffff))
+#define SET_SYSTEM_INT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x7fffffff))
+#define SET_CARD_RCA_REG(_VAL_) (REG32(ADR_CARD_RCA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_RCA_REG)) & 0xffff0000))
+#define SET_SDIO_FIFO_WR_THLD_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0xfffffe00))
+#define SET_SDIO_FIFO_WR_LIMIT_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0xfffffe00))
+#define SET_SDIO_TX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
+#define SET_SDIO_THLD_FOR_CMD53RD_REG(_VAL_) (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0xfffffe00))
+#define SET_SDIO_RX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
+#define SET_START_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffffff00))
+#define SET_END_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffff00ff))
+#define SET_SDIO_BYTE_MODE_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0xffffff00))
+#define SET_SDIO_LAST_CMD_INDEX_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffffffc0))
+#define SET_SDIO_LAST_CMD_CRC_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffff80ff))
+#define SET_SDIO_LAST_CMD_ARG_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0x00000000))
+#define SET_SDIO_BUS_STATE_REG(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffffffe0))
+#define SET_SDIO_BUSY_LONG_CNT(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000ffff))
+#define SET_SDIO_CARD_STATUS_REG(_VAL_) (REG32(ADR_SDIO_CARD_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0x00000000))
+#define SET_R5_RESPONSE_FLAG(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 0) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xffffff00))
+#define SET_RESP_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 8) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffeff))
+#define SET_DAT_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 9) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffdff))
+#define SET_MCU_TO_SDIO_INFO_MASK(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 16) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffeffff))
+#define SET_INT_THROUGH_PIN(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 17) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffdffff))
+#define SET_WRITE_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffffff00))
+#define SET_WRITE_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 8) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffff00ff))
+#define SET_READ_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff00ffff))
+#define SET_READ_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 24) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ffffff))
+#define SET_FN1_DMA_START_ADDR_REG(_VAL_) (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0x00000000))
+#define SET_SDIO_TO_MCU_INFO(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffff00))
+#define SET_SDIO_PARTIAL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffeff))
+#define SET_SDIO_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffdff))
+#define SET_PERI_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffbff))
+#define SET_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffff7ff))
+#define SET_AHB_BRIDGE_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffefff))
+#define SET_IO_REG_PORT_REG(_VAL_) (REG32(ADR_IO_REG_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_REG_PORT_REG)) & 0xfffe0000))
+#define SET_SDIO_FIFO_EMPTY_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000))
+#define SET_SDIO_FIFO_FULL_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff))
+#define SET_SDIO_CRC7_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000))
+#define SET_SDIO_CRC16_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff))
+#define SET_SDIO_RD_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfffffe00))
+#define SET_SDIO_WR_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfe00ffff))
+#define SET_CMD52_RD_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xfff0ffff))
+#define SET_CMD52_WR_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 20) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xff0fffff))
+#define SET_SDIO_FIFO_WR_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffffff00))
+#define SET_SDIO_FIFO_RD_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffff00ff))
+#define SET_SDIO_READ_DATA_CTRL(_VAL_) (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0xfffeffff))
+#define SET_TX_SIZE_BEFORE_SHIFT(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffff00))
+#define SET_TX_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffff8ff))
+#define SET_SDIO_TX_ALLOC_STATE(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffefff))
+#define SET_ALLOCATE_STATUS2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffeffff))
+#define SET_NO_ALLOCATE_SEND_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffdffff))
+#define SET_DOUBLE_ALLOCATE_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffbffff))
+#define SET_TX_DONE_STATUS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfff7ffff))
+#define SET_AHB_HANG2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffefffff))
+#define SET_HCI_TRX_FINISH2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffdfffff))
+#define SET_INTR_RX(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffbfffff))
+#define SET_HCI_INPUT_QUEUE_FULL(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xff7fffff))
+#define SET_ALLOCATESTATUS(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffe))
+#define SET_HCI_TRX_FINISH3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffd))
+#define SET_HCI_IN_QUE_EMPTY2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffb))
+#define SET_MTX_MNG_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffff7))
+#define SET_EDCA0_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffef))
+#define SET_EDCA1_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffdf))
+#define SET_EDCA2_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffbf))
+#define SET_EDCA3_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffff7f))
+#define SET_TX_PAGE_REMAIN2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffff00ff))
+#define SET_TX_ID_REMAIN3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff80ffff))
+#define SET_HCI_OUTPUT_FF_CNT_0(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff7fffff))
+#define SET_HCI_OUTPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xf0ffffff))
+#define SET_HCI_INPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_TX_INFORM)) & 0x0fffffff))
+#define SET_F1_BLOCK_SIZE_0_REG(_VAL_) (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (((_VAL_) << 0) | ((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0xfffff000))
+#define SET_START_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffffff00))
+#define SET_COMMAND_COUNTER(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff00ff))
+#define SET_CMD_LOG_PART1(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ffff))
+#define SET_CMD_LOG_PART2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000))
+#define SET_END_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff))
+#define SET_RX_PACKET_LENGTH3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xffff0000))
+#define SET_RX_INT3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xfffeffff))
+#define SET_TX_ID_REMAIN2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff01ffff))
+#define SET_TX_PAGE_REMAIN3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00ffffff))
+#define SET_CCCR_00H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_00H_REG)) & 0xffffff00))
+#define SET_CCCR_02H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_00H_REG)) & 0xff00ffff))
+#define SET_CCCR_03H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_00H_REG)) & 0x00ffffff))
+#define SET_CCCR_04H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_04H_REG)) & 0xffffff00))
+#define SET_CCCR_05H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_04H_REG)) & 0xffff00ff))
+#define SET_CCCR_06H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_04H_REG)) & 0xfff0ffff))
+#define SET_CCCR_07H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_04H_REG)) & 0x00ffffff))
+#define SET_SUPPORT_DIRECT_COMMAND_SDIO(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffe))
+#define SET_SUPPORT_MULTIPLE_BLOCK_TRANSFER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 1) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffd))
+#define SET_SUPPORT_READ_WAIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 2) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffb))
+#define SET_SUPPORT_BUS_CONTROL(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 3) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffff7))
+#define SET_SUPPORT_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 4) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffef))
+#define SET_ENABLE_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 5) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffdf))
+#define SET_LOW_SPEED_CARD(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffbf))
+#define SET_LOW_SPEED_CARD_4BIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffff7f))
+#define SET_COMMON_CIS_PONTER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_08H_REG)) & 0xfe0000ff))
+#define SET_SUPPORT_HIGH_SPEED(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_13H_REG)) & 0xfeffffff))
+#define SET_BSS(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 25) | ((REG32(ADR_CCCR_13H_REG)) & 0xf1ffffff))
+#define SET_FBR_100H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FBR_100H_REG)) & 0xfffffff0))
+#define SET_CSASUPPORT(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_FBR_100H_REG)) & 0xffffffbf))
+#define SET_ENABLECSA(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FBR_100H_REG)) & 0xffffff7f))
+#define SET_FBR_101H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_100H_REG)) & 0xffff00ff))
+#define SET_FBR_109H_REG(_VAL_) (REG32(ADR_FBR_109H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_109H_REG)) & 0xfe0000ff))
+#define SET_F0_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0x00000000))
+#define SET_SPI_MODE(_VAL_) (REG32(ADR_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_MODE)) & 0x00000000))
+#define SET_RX_QUOTA(_VAL_) (REG32(ADR_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_QUOTA)) & 0xffff0000))
+#define SET_CONDI_NUM(_VAL_) (REG32(ADR_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_CONDITION_NUMBER)) & 0xffffff00))
+#define SET_HOST_PATH(_VAL_) (REG32(ADR_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_HOST_PATH)) & 0xfffffffe))
+#define SET_TX_SEG(_VAL_) (REG32(ADR_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEG)) & 0x00000000))
+#define SET_BRST_MODE(_VAL_) (REG32(ADR_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_BURST_MODE)) & 0xfffffffe))
+#define SET_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000))
+#define SET_CSN_INTER(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
+#define SET_BACK_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000))
+#define SET_FRONT_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
+#define SET_RX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SPI_STS)) & 0xfffffffd))
+#define SET_RX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SPI_STS)) & 0xfffffffb))
+#define SET_TX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SPI_STS)) & 0xfffffff7))
+#define SET_TX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SPI_STS)) & 0xffffffef))
+#define SET_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SPI_STS)) & 0xffffffdf))
+#define SET_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SPI_STS)) & 0xffffffbf))
+#define SET_RDATA_RDY(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SPI_STS)) & 0xffffff7f))
+#define SET_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SPI_STS)) & 0xfffffeff))
+#define SET_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SPI_STS)) & 0xfffffdff))
+#define SET_RX_LEN(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_STS)) & 0x0000ffff))
+#define SET_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffff8))
+#define SET_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffeff))
+#define SET_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC)) & 0xffffff00))
+#define SET_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT)) & 0xffff0000))
+#define SET_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT)) & 0x0000ffff))
+#define SET_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT2)) & 0xffff0000))
+#define SET_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT2)) & 0xfffeffff))
+#define SET_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT2)) & 0xfffdffff))
+#define SET_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT2)) & 0xfffbffff))
+#define SET_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT3)) & 0xffff0000))
+#define SET_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT3)) & 0x0000ffff))
+#define SET_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT4)) & 0xffff0000))
+#define SET_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT4)) & 0xfffeffff))
+#define SET_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT4)) & 0xfffdffff))
+#define SET_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT4)) & 0xfffbffff))
+#define SET_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_CNT4)) & 0xfff7ffff))
+#define SET_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_CNT4)) & 0xff8fffff))
+#define SET_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_CNT4)) & 0xf8ffffff))
+#define SET_RX_RDY(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_TAG)) & 0xfffffffe))
+#define SET_SDIO_SYS_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_TAG)) & 0xfffffffb))
+#define SET_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_TAG)) & 0xfffffff7))
+#define SET_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_TAG)) & 0xffffffef))
+#define SET_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_TAG)) & 0xffffffdf))
+#define SET_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_TAG)) & 0xffffffbf))
+#define SET_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_TAG)) & 0xffffff7f))
+#define SET_SPI_FN1(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_TAG)) & 0xffff80ff))
+#define SET_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_INT_TAG)) & 0xffff7fff))
+#define SET_SPI_HOST_MASK(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_INT_TAG)) & 0xff00ffff))
+#define SET_I2CM_INT_WDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN)) & 0xfffffffe))
+#define SET_I2CM_INT_RDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 1) | ((REG32(ADR_I2CM_EN)) & 0xfffffffd))
+#define SET_I2CM_IDLE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 2) | ((REG32(ADR_I2CM_EN)) & 0xfffffffb))
+#define SET_I2CM_INT_MISMATCH(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 3) | ((REG32(ADR_I2CM_EN)) & 0xfffffff7))
+#define SET_I2CM_PSCL(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 4) | ((REG32(ADR_I2CM_EN)) & 0xffffc00f))
+#define SET_I2CM_MANUAL_MODE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN)) & 0xfffeffff))
+#define SET_I2CM_INT_WDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN)) & 0xfffdffff))
+#define SET_I2CM_INT_RDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 18) | ((REG32(ADR_I2CM_EN)) & 0xfffbffff))
+#define SET_I2CM_DEV_A(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_DEV_A)) & 0xfffffc00))
+#define SET_I2CM_DEV_A10B(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 14) | ((REG32(ADR_I2CM_DEV_A)) & 0xffffbfff))
+#define SET_I2CM_RX(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 15) | ((REG32(ADR_I2CM_DEV_A)) & 0xffff7fff))
+#define SET_I2CM_LEN(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_LEN)) & 0xffff0000))
+#define SET_I2CM_T_LEFT(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_LEN)) & 0xfff8ffff))
+#define SET_I2CM_R_GET(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 24) | ((REG32(ADR_I2CM_LEN)) & 0xf8ffffff))
+#define SET_I2CM_WDAT(_VAL_) (REG32(ADR_I2CM_WDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_WDAT)) & 0x00000000))
+#define SET_I2CM_RDAT(_VAL_) (REG32(ADR_I2CM_RDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_RDAT)) & 0x00000000))
+#define SET_I2CM_SR_LEN(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN_2)) & 0xffff0000))
+#define SET_I2CM_SR_RX(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN_2)) & 0xfffeffff))
+#define SET_I2CM_REPEAT_START(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN_2)) & 0xfffdffff))
+#define SET_UART_DATA(_VAL_) (REG32(ADR_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_UART_DATA)) & 0xffffff00))
+#define SET_DATA_RDY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_UART_IER)) & 0xfffffffe))
+#define SET_THR_EMPTY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_UART_IER)) & 0xfffffffd))
+#define SET_RX_LINESTS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_UART_IER)) & 0xfffffffb))
+#define SET_MDM_STS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_UART_IER)) & 0xfffffff7))
+#define SET_DMA_RXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_UART_IER)) & 0xffffffbf))
+#define SET_DMA_TXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_UART_IER)) & 0xffffff7f))
+#define SET_FIFO_EN(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_FCR)) & 0xfffffffe))
+#define SET_RXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_FCR)) & 0xfffffffd))
+#define SET_TXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_FCR)) & 0xfffffffb))
+#define SET_DMA_MODE(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_FCR)) & 0xfffffff7))
+#define SET_EN_AUTO_RTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_FCR)) & 0xffffffef))
+#define SET_EN_AUTO_CTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_FCR)) & 0xffffffdf))
+#define SET_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_FCR)) & 0xffffff3f))
+#define SET_WORD_LEN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LCR)) & 0xfffffffc))
+#define SET_STOP_BIT(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LCR)) & 0xfffffffb))
+#define SET_PARITY_EN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LCR)) & 0xfffffff7))
+#define SET_EVEN_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LCR)) & 0xffffffef))
+#define SET_FORCE_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LCR)) & 0xffffffdf))
+#define SET_SET_BREAK(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LCR)) & 0xffffffbf))
+#define SET_DLAB(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LCR)) & 0xffffff7f))
+#define SET_DTR(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MCR)) & 0xfffffffe))
+#define SET_RTS(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MCR)) & 0xfffffffd))
+#define SET_OUT_1(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MCR)) & 0xfffffffb))
+#define SET_OUT_2(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MCR)) & 0xfffffff7))
+#define SET_LOOP_BACK(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MCR)) & 0xffffffef))
+#define SET_DATA_RDY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LSR)) & 0xfffffffe))
+#define SET_OVERRUN_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_LSR)) & 0xfffffffd))
+#define SET_PARITY_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LSR)) & 0xfffffffb))
+#define SET_FRAMING_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LSR)) & 0xfffffff7))
+#define SET_BREAK_INT(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LSR)) & 0xffffffef))
+#define SET_THR_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LSR)) & 0xffffffdf))
+#define SET_TX_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LSR)) & 0xffffffbf))
+#define SET_FIFODATA_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LSR)) & 0xffffff7f))
+#define SET_DELTA_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MSR)) & 0xfffffffe))
+#define SET_DELTA_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MSR)) & 0xfffffffd))
+#define SET_TRAILEDGE_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MSR)) & 0xfffffffb))
+#define SET_DELTA_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MSR)) & 0xfffffff7))
+#define SET_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MSR)) & 0xffffffef))
+#define SET_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_MSR)) & 0xffffffdf))
+#define SET_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_MSR)) & 0xffffffbf))
+#define SET_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_MSR)) & 0xffffff7f))
+#define SET_BRDC_DIV(_VAL_) (REG32(ADR_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_SPR)) & 0xffff0000))
+#define SET_RTHR_L(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_RTHR)) & 0xfffffff0))
+#define SET_RTHR_H(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_RTHR)) & 0xffffff0f))
+#define SET_INT_IDCODE(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_ISR)) & 0xfffffff0))
+#define SET_FIFOS_ENABLED(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_ISR)) & 0xffffff3f))
+#define SET_DAT_UART_DATA(_VAL_) (REG32(ADR_DAT_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_DATA)) & 0xffffff00))
+#define SET_DAT_DATA_RDY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffe))
+#define SET_DAT_THR_EMPTY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffd))
+#define SET_DAT_RX_LINESTS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffb))
+#define SET_DAT_MDM_STS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffff7))
+#define SET_DAT_DMA_RXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_IER)) & 0xffffffbf))
+#define SET_DAT_DMA_TXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_IER)) & 0xffffff7f))
+#define SET_DAT_FIFO_EN(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffe))
+#define SET_DAT_RXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffd))
+#define SET_DAT_TXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffb))
+#define SET_DAT_DMA_MODE(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffff7))
+#define SET_DAT_EN_AUTO_RTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffef))
+#define SET_DAT_EN_AUTO_CTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffdf))
+#define SET_DAT_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffff3f))
+#define SET_DAT_WORD_LEN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffc))
+#define SET_DAT_STOP_BIT(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffb))
+#define SET_DAT_PARITY_EN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffff7))
+#define SET_DAT_EVEN_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffef))
+#define SET_DAT_FORCE_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffdf))
+#define SET_DAT_SET_BREAK(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffbf))
+#define SET_DAT_DLAB(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffff7f))
+#define SET_DAT_DTR(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffe))
+#define SET_DAT_RTS(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffd))
+#define SET_DAT_OUT_1(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffb))
+#define SET_DAT_OUT_2(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffff7))
+#define SET_DAT_LOOP_BACK(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MCR)) & 0xffffffef))
+#define SET_DAT_DATA_RDY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffe))
+#define SET_DAT_OVERRUN_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffd))
+#define SET_DAT_PARITY_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffb))
+#define SET_DAT_FRAMING_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffff7))
+#define SET_DAT_BREAK_INT(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffef))
+#define SET_DAT_THR_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffdf))
+#define SET_DAT_TX_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffbf))
+#define SET_DAT_FIFODATA_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffff7f))
+#define SET_DAT_DELTA_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffe))
+#define SET_DAT_DELTA_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffd))
+#define SET_DAT_TRAILEDGE_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffb))
+#define SET_DAT_DELTA_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffff7))
+#define SET_DAT_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffef))
+#define SET_DAT_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffdf))
+#define SET_DAT_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffbf))
+#define SET_DAT_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffff7f))
+#define SET_DAT_BRDC_DIV(_VAL_) (REG32(ADR_DAT_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_SPR)) & 0xffff0000))
+#define SET_DAT_RTHR_L(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_RTHR)) & 0xfffffff0))
+#define SET_DAT_RTHR_H(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_RTHR)) & 0xffffff0f))
+#define SET_DAT_INT_IDCODE(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_ISR)) & 0xfffffff0))
+#define SET_DAT_FIFOS_ENABLED(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_ISR)) & 0xffffff3f))
+#define SET_MASK_TOP(_VAL_) (REG32(ADR_INT_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK)) & 0x00000000))
+#define SET_INT_MODE(_VAL_) (REG32(ADR_INT_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MODE)) & 0x00000000))
+#define SET_IRQ_PHY_0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffe))
+#define SET_IRQ_PHY_1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffd))
+#define SET_IRQ_SDIO(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffb))
+#define SET_IRQ_BEACON_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffff7))
+#define SET_IRQ_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffef))
+#define SET_IRQ_PRE_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffdf))
+#define SET_IRQ_EDCA0_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffbf))
+#define SET_IRQ_EDCA1_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffff7f))
+#define SET_IRQ_EDCA2_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffeff))
+#define SET_IRQ_EDCA3_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffdff))
+#define SET_IRQ_EDCA4_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffbff))
+#define SET_IRQ_BEACON_DTIM(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffefff))
+#define SET_IRQ_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffdfff))
+#define SET_IRQ_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffbfff))
+#define SET_IRQ_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_IRQ_STS)) & 0xffff7fff))
+#define SET_IRQ_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffeffff))
+#define SET_IRQ_FENCE_HIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffdffff))
+#define SET_IRQ_ILL_ADDR_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffbffff))
+#define SET_IRQ_MBOX(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_IRQ_STS)) & 0xfff7ffff))
+#define SET_IRQ_US_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_IRQ_STS)) & 0xffefffff))
+#define SET_IRQ_US_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_IRQ_STS)) & 0xffdfffff))
+#define SET_IRQ_US_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_IRQ_STS)) & 0xffbfffff))
+#define SET_IRQ_US_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_IRQ_STS)) & 0xff7fffff))
+#define SET_IRQ_MS_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_IRQ_STS)) & 0xfeffffff))
+#define SET_IRQ_MS_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_IRQ_STS)) & 0xfdffffff))
+#define SET_IRQ_MS_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_IRQ_STS)) & 0xfbffffff))
+#define SET_IRQ_MS_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_IRQ_STS)) & 0xf7ffffff))
+#define SET_IRQ_TX_LIMIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_IRQ_STS)) & 0xefffffff))
+#define SET_IRQ_DMA0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_IRQ_STS)) & 0xdfffffff))
+#define SET_IRQ_CO_DMA(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_IRQ_STS)) & 0xbfffffff))
+#define SET_IRQ_PERI_GROUP(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_IRQ_STS)) & 0x7fffffff))
+#define SET_FIQ_STATUS(_VAL_) (REG32(ADR_INT_FIQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_STS)) & 0x00000000))
+#define SET_IRQ_RAW(_VAL_) (REG32(ADR_INT_IRQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_RAW)) & 0x00000000))
+#define SET_FIQ_RAW(_VAL_) (REG32(ADR_INT_FIQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_RAW)) & 0x00000000))
+#define SET_INT_PERI_MASK(_VAL_) (REG32(ADR_INT_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_MASK)) & 0x00000000))
+#define SET_PERI_RTC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffe))
+#define SET_IRQ_UART0_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffd))
+#define SET_IRQ_UART0_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffb))
+#define SET_PERI_GPI_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffff7))
+#define SET_IRQ_SPI_IPC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_PERI_STS)) & 0xffffffef))
+#define SET_PERI_GPI_1_0(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff9f))
+#define SET_SCRT_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff7f))
+#define SET_MMU_ALC_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffeff))
+#define SET_MMU_RLS_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffdff))
+#define SET_ID_MNG_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffbff))
+#define SET_MBOX_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_INT_PERI_STS)) & 0xfffff7ff))
+#define SET_MBOX_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_PERI_STS)) & 0xffffefff))
+#define SET_MBOX_INT_3(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_PERI_STS)) & 0xffffdfff))
+#define SET_HCI_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_PERI_STS)) & 0xffffbfff))
+#define SET_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_PERI_STS)) & 0xffff7fff))
+#define SET_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_PERI_STS)) & 0xfffeffff))
+#define SET_ID_MNG_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_PERI_STS)) & 0xfffdffff))
+#define SET_DMN_NOHIT_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_PERI_STS)) & 0xfffbffff))
+#define SET_ID_THOLD_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_PERI_STS)) & 0xfff7ffff))
+#define SET_ID_THOLD_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_PERI_STS)) & 0xffefffff))
+#define SET_ID_DOUBLE_RLS(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_PERI_STS)) & 0xffdfffff))
+#define SET_RX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_PERI_STS)) & 0xffbfffff))
+#define SET_TX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_PERI_STS)) & 0xff7fffff))
+#define SET_ALL_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_PERI_STS)) & 0xfeffffff))
+#define SET_DMN_MCU_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_PERI_STS)) & 0xfdffffff))
+#define SET_IRQ_DAT_UART_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_PERI_STS)) & 0xfbffffff))
+#define SET_IRQ_DAT_UART_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_PERI_STS)) & 0xf7ffffff))
+#define SET_DAT_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_PERI_STS)) & 0xefffffff))
+#define SET_DAT_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_PERI_STS)) & 0xdfffffff))
+#define SET_ALR_ABT_NOCHG_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_PERI_STS)) & 0xbfffffff))
+#define SET_TBLNEQ_MNGPKT_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_PERI_STS)) & 0x7fffffff))
+#define SET_INTR_PERI_RAW(_VAL_) (REG32(ADR_INT_PERI_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_RAW)) & 0x00000000))
+#define SET_INTR_GPI00_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffffc))
+#define SET_INTR_GPI01_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffff3))
+#define SET_SYS_RST_INT(_VAL_) (REG32(ADR_SYS_INT_FOR_HOST)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_INT_FOR_HOST)) & 0xfffffffe))
+#define SET_SPI_IPC_ADDR(_VAL_) (REG32(ADR_SPI_IPC)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_IPC)) & 0x00000000))
+#define SET_SD_MASK_TOP(_VAL_) (REG32(ADR_SDIO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_MASK)) & 0x00000000))
+#define SET_IRQ_PHY_0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffe))
+#define SET_IRQ_PHY_1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffd))
+#define SET_IRQ_SDIO_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffb))
+#define SET_IRQ_BEACON_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffff7))
+#define SET_IRQ_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffef))
+#define SET_IRQ_PRE_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffdf))
+#define SET_IRQ_EDCA0_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffbf))
+#define SET_IRQ_EDCA1_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffff7f))
+#define SET_IRQ_EDCA2_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffeff))
+#define SET_IRQ_EDCA3_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffdff))
+#define SET_IRQ_EDCA4_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffbff))
+#define SET_IRQ_BEACON_DTIM_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffefff))
+#define SET_IRQ_EDCA0_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffdfff))
+#define SET_IRQ_EDCA1_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffbfff))
+#define SET_IRQ_EDCA2_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffff7fff))
+#define SET_IRQ_EDCA3_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffeffff))
+#define SET_IRQ_FENCE_HIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffdffff))
+#define SET_IRQ_ILL_ADDR_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffbffff))
+#define SET_IRQ_MBOX_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfff7ffff))
+#define SET_IRQ_US_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffefffff))
+#define SET_IRQ_US_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffdfffff))
+#define SET_IRQ_US_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffbfffff))
+#define SET_IRQ_US_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xff7fffff))
+#define SET_IRQ_MS_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfeffffff))
+#define SET_IRQ_MS_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfdffffff))
+#define SET_IRQ_MS_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfbffffff))
+#define SET_IRQ_MS_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xf7ffffff))
+#define SET_IRQ_TX_LIMIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xefffffff))
+#define SET_IRQ_DMA0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xdfffffff))
+#define SET_IRQ_CO_DMA_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xbfffffff))
+#define SET_IRQ_PERI_GROUP_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SDIO_IRQ_STS)) & 0x7fffffff))
+#define SET_INT_PERI_MASK_SD(_VAL_) (REG32(ADR_SD_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_MASK)) & 0x00000000))
+#define SET_PERI_RTC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffe))
+#define SET_IRQ_UART0_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffd))
+#define SET_IRQ_UART0_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffb))
+#define SET_PERI_GPI_SD_2(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffff7))
+#define SET_IRQ_SPI_IPC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SD_PERI_STS)) & 0xffffffef))
+#define SET_PERI_GPI_SD_1_0(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff9f))
+#define SET_SCRT_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff7f))
+#define SET_MMU_ALC_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffeff))
+#define SET_MMU_RLS_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffdff))
+#define SET_ID_MNG_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffbff))
+#define SET_MBOX_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_SD_PERI_STS)) & 0xfffff7ff))
+#define SET_MBOX_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SD_PERI_STS)) & 0xffffefff))
+#define SET_MBOX_INT_3_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SD_PERI_STS)) & 0xffffdfff))
+#define SET_HCI_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SD_PERI_STS)) & 0xffffbfff))
+#define SET_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SD_PERI_STS)) & 0xffff7fff))
+#define SET_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SD_PERI_STS)) & 0xfffeffff))
+#define SET_ID_MNG_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SD_PERI_STS)) & 0xfffdffff))
+#define SET_DMN_NOHIT_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SD_PERI_STS)) & 0xfffbffff))
+#define SET_ID_THOLD_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SD_PERI_STS)) & 0xfff7ffff))
+#define SET_ID_THOLD_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SD_PERI_STS)) & 0xffefffff))
+#define SET_ID_DOUBLE_RLS_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SD_PERI_STS)) & 0xffdfffff))
+#define SET_RX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SD_PERI_STS)) & 0xffbfffff))
+#define SET_TX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SD_PERI_STS)) & 0xff7fffff))
+#define SET_ALL_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SD_PERI_STS)) & 0xfeffffff))
+#define SET_DMN_MCU_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SD_PERI_STS)) & 0xfdffffff))
+#define SET_IRQ_DAT_UART_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SD_PERI_STS)) & 0xfbffffff))
+#define SET_IRQ_DAT_UART_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SD_PERI_STS)) & 0xf7ffffff))
+#define SET_DAT_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SD_PERI_STS)) & 0xefffffff))
+#define SET_DAT_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SD_PERI_STS)) & 0xdfffffff))
+#define SET_ALR_ABT_NOCHG_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SD_PERI_STS)) & 0xbfffffff))
+#define SET_TBLNEQ_MNGPKT_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SD_PERI_STS)) & 0x7fffffff))
+#define SET_DBG_SPI_MODE(_VAL_) (REG32(ADR_DBG_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_MODE)) & 0x00000000))
+#define SET_DBG_RX_QUOTA(_VAL_) (REG32(ADR_DBG_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_RX_QUOTA)) & 0xffff0000))
+#define SET_DBG_CONDI_NUM(_VAL_) (REG32(ADR_DBG_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CONDITION_NUMBER)) & 0xffffff00))
+#define SET_DBG_HOST_PATH(_VAL_) (REG32(ADR_DBG_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_HOST_PATH)) & 0xfffffffe))
+#define SET_DBG_TX_SEG(_VAL_) (REG32(ADR_DBG_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_SEG)) & 0x00000000))
+#define SET_DBG_BRST_MODE(_VAL_) (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0xfffffffe))
+#define SET_DBG_CLK_WIDTH(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000))
+#define SET_DBG_CSN_INTER(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
+#define SET_DBG_BACK_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000))
+#define SET_DBG_FRONT_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
+#define SET_DBG_RX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffd))
+#define SET_DBG_RX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffb))
+#define SET_DBG_TX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffff7))
+#define SET_DBG_TX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffef))
+#define SET_DBG_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffdf))
+#define SET_DBG_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffbf))
+#define SET_DBG_RDATA_RDY(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffff7f))
+#define SET_DBG_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffeff))
+#define SET_DBG_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffdff))
+#define SET_DBG_RX_LEN(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_STS)) & 0x0000ffff))
+#define SET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffff8))
+#define SET_DBG_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffeff))
+#define SET_DBG_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_DBG_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC)) & 0xffffff00))
+#define SET_DBG_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000))
+#define SET_DBG_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff))
+#define SET_DBG_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xffff0000))
+#define SET_DBG_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffeffff))
+#define SET_DBG_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffdffff))
+#define SET_DBG_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffbffff))
+#define SET_DBG_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000))
+#define SET_DBG_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff))
+#define SET_DBG_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xffff0000))
+#define SET_DBG_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffeffff))
+#define SET_DBG_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffdffff))
+#define SET_DBG_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffbffff))
+#define SET_DBG_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfff7ffff))
+#define SET_DBG_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xff8fffff))
+#define SET_DBG_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xf8ffffff))
+#define SET_DBG_RX_RDY(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffe))
+#define SET_DBG_SDIO_SYS_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffb))
+#define SET_DBG_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffff7))
+#define SET_DBG_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffef))
+#define SET_DBG_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffdf))
+#define SET_DBG_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffbf))
+#define SET_DBG_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffff7f))
+#define SET_DBG_SPI_FN1(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff80ff))
+#define SET_DBG_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff7fff))
+#define SET_DBG_SPI_HOST_MASK(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_INT_TAG)) & 0xff00ffff))
+#define SET_BOOT_ADDR(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_ADDR)) & 0xff000000))
+#define SET_CHECK_SUM_FAIL(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_BOOT_ADDR)) & 0x7fffffff))
+#define SET_VERIFY_DATA(_VAL_) (REG32(ADR_VERIFY_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_VERIFY_DATA)) & 0x00000000))
+#define SET_FLASH_ADDR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_FLASH_ADDR)) & 0xff000000))
+#define SET_FLASH_CMD_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 28) | ((REG32(ADR_FLASH_ADDR)) & 0xefffffff))
+#define SET_FLASH_DMA_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 29) | ((REG32(ADR_FLASH_ADDR)) & 0xdfffffff))
+#define SET_DMA_EN(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 30) | ((REG32(ADR_FLASH_ADDR)) & 0xbfffffff))
+#define SET_DMA_BUSY(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_FLASH_ADDR)) & 0x7fffffff))
+#define SET_SRAM_ADDR(_VAL_) (REG32(ADR_SRAM_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SRAM_ADDR)) & 0x00000000))
+#define SET_FLASH_DMA_LEN(_VAL_) (REG32(ADR_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_LEN)) & 0x00000000))
+#define SET_FLASH_FRONT_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM)) & 0xffff0000))
+#define SET_FLASH_BACK_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM)) & 0x0000ffff))
+#define SET_FLASH_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM2)) & 0xffff0000))
+#define SET_SPI_BUSY(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM2)) & 0xfffeffff))
+#define SET_FLS_REMAP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 17) | ((REG32(ADR_SPI_PARAM2)) & 0xfffdffff))
+#define SET_PBUS_SWP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 18) | ((REG32(ADR_SPI_PARAM2)) & 0xfffbffff))
+#define SET_BIT_MODE1(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 19) | ((REG32(ADR_SPI_PARAM2)) & 0xfff7ffff))
+#define SET_BIT_MODE2(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 20) | ((REG32(ADR_SPI_PARAM2)) & 0xffefffff))
+#define SET_BIT_MODE4(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 21) | ((REG32(ADR_SPI_PARAM2)) & 0xffdfffff))
+#define SET_BOOT_CHECK_SUM(_VAL_) (REG32(ADR_CHECK_SUM_RESULT)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_RESULT)) & 0x00000000))
+#define SET_CHECK_SUM_TAG(_VAL_) (REG32(ADR_CHECK_SUM_IN_FILE)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_IN_FILE)) & 0x00000000))
+#define SET_CMD_LEN(_VAL_) (REG32(ADR_COMMAND_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_LEN)) & 0xffff0000))
+#define SET_CMD_ADDR(_VAL_) (REG32(ADR_COMMAND_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_ADDR)) & 0x00000000))
+#define SET_DMA_ADR_SRC(_VAL_) (REG32(ADR_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_SRC)) & 0x00000000))
+#define SET_DMA_ADR_DST(_VAL_) (REG32(ADR_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_DST)) & 0x00000000))
+#define SET_DMA_SRC_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff8))
+#define SET_DMA_SRC_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff7))
+#define SET_DMA_DST_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_DMA_CTRL)) & 0xffffff8f))
+#define SET_DMA_DST_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_DMA_CTRL)) & 0xffffff7f))
+#define SET_DMA_FAST_FILL(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_CTRL)) & 0xfffffeff))
+#define SET_DMA_SDIO_KICK(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_DMA_CTRL)) & 0xffffefff))
+#define SET_DMA_BADR_EN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_DMA_CTRL)) & 0xffffdfff))
+#define SET_DMA_LEN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_CTRL)) & 0x0000ffff))
+#define SET_DMA_INT_MASK(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_INT)) & 0xfffffffe))
+#define SET_DMA_STS(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_INT)) & 0xfffffeff))
+#define SET_DMA_FINISH(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_DMA_INT)) & 0x7fffffff))
+#define SET_DMA_CONST(_VAL_) (REG32(ADR_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_FILL_CONST)) & 0x00000000))
+#define SET_SLEEP_WAKE_CNT(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_0)) & 0xff000000))
+#define SET_RG_DLDO_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 24) | ((REG32(ADR_PMU_0)) & 0xf8ffffff))
+#define SET_RG_DLDO_BOOST_IQ(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 27) | ((REG32(ADR_PMU_0)) & 0xf7ffffff))
+#define SET_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 28) | ((REG32(ADR_PMU_0)) & 0x8fffffff))
+#define SET_RG_BUCK_VREF_SEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_0)) & 0x7fffffff))
+#define SET_RG_RTC_OSC_RES_SW_MANUAL(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_1)) & 0xfffffc00))
+#define SET_RG_RTC_OSC_RES_SW(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_1)) & 0xfc00ffff))
+#define SET_RTC_OSC_CAL_RES_RDY(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_1)) & 0x7fffffff))
+#define SET_RG_DCDC_MODE(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_2)) & 0xfffffffe))
+#define SET_RG_BUCK_EN_PSM(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_2)) & 0xffffffef))
+#define SET_RG_BUCK_PSM_VTH(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_2)) & 0xfffffeff))
+#define SET_RG_RTC_OSC_RES_SW_MANUAL_EN(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 12) | ((REG32(ADR_PMU_2)) & 0xffffefff))
+#define SET_RG_RTC_RDY_DEGLITCH_TIMER(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 13) | ((REG32(ADR_PMU_2)) & 0xffff9fff))
+#define SET_RTC_CAL_ENA(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_2)) & 0xfffeffff))
+#define SET_PMU_WAKE_TRIG_EVENT(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_3)) & 0xfffffffc))
+#define SET_DIGI_TOP_POR_MASK(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_3)) & 0xffffffef))
+#define SET_PMU_ENTER_SLEEP_MODE(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_3)) & 0xfffffeff))
+#define SET_RG_RTC_DUMMIES(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_3)) & 0x0000ffff))
+#define SET_RTC_EN(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_1)) & 0xfffffffe))
+#define SET_RTC_SRC(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_1)) & 0xfffffffd))
+#define SET_RTC_TICK_CNT(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_1)) & 0x8000ffff))
+#define SET_RTC_INT_SEC_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_2)) & 0xfffffffe))
+#define SET_RTC_INT_ALARM_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_2)) & 0xfffffffd))
+#define SET_RTC_INT_SEC(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_2)) & 0xfffeffff))
+#define SET_RTC_INT_ALARM(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 17) | ((REG32(ADR_RTC_2)) & 0xfffdffff))
+#define SET_RTC_SEC_START_CNT(_VAL_) (REG32(ADR_RTC_3W)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3W)) & 0x00000000))
+#define SET_RTC_SEC_CNT(_VAL_) (REG32(ADR_RTC_3R)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3R)) & 0x00000000))
+#define SET_RTC_SEC_ALARM_VALUE(_VAL_) (REG32(ADR_RTC_4)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_4)) & 0x00000000))
+#define SET_D2_DMA_ADR_SRC(_VAL_) (REG32(ADR_D2_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_SRC)) & 0x00000000))
+#define SET_D2_DMA_ADR_DST(_VAL_) (REG32(ADR_D2_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_DST)) & 0x00000000))
+#define SET_D2_DMA_SRC_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff8))
+#define SET_D2_DMA_SRC_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff7))
+#define SET_D2_DMA_DST_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff8f))
+#define SET_D2_DMA_DST_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff7f))
+#define SET_D2_DMA_FAST_FILL(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffeff))
+#define SET_D2_DMA_SDIO_KICK(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffefff))
+#define SET_D2_DMA_BADR_EN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffdfff))
+#define SET_D2_DMA_LEN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_D2_DMA_CTRL)) & 0x0000ffff))
+#define SET_D2_DMA_INT_MASK(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffffe))
+#define SET_D2_DMA_STS(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffeff))
+#define SET_D2_DMA_FINISH(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_D2_DMA_INT)) & 0x7fffffff))
+#define SET_D2_DMA_CONST(_VAL_) (REG32(ADR_D2_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_FILL_CONST)) & 0x00000000))
+#define SET_TRAP_UNKNOWN_TYPE(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_CONTROL)) & 0xfffffffe))
+#define SET_TX_ON_DEMAND_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_CONTROL)) & 0xfffffffd))
+#define SET_RX_2_HOST(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_CONTROL)) & 0xfffffffb))
+#define SET_AUTO_SEQNO(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 3) | ((REG32(ADR_CONTROL)) & 0xfffffff7))
+#define SET_BYPASSS_TX_PARSER_ENCAP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 4) | ((REG32(ADR_CONTROL)) & 0xffffffef))
+#define SET_HDR_STRIP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 5) | ((REG32(ADR_CONTROL)) & 0xffffffdf))
+#define SET_ERP_PROTECT(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 6) | ((REG32(ADR_CONTROL)) & 0xffffff3f))
+#define SET_PRO_VER(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_CONTROL)) & 0xfffffcff))
+#define SET_TXQ_ID0(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 12) | ((REG32(ADR_CONTROL)) & 0xffff8fff))
+#define SET_TXQ_ID1(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_CONTROL)) & 0xfff8ffff))
+#define SET_TX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 20) | ((REG32(ADR_CONTROL)) & 0xffefffff))
+#define SET_RX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 21) | ((REG32(ADR_CONTROL)) & 0xffdfffff))
+#define SET_RX_NULL_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 22) | ((REG32(ADR_CONTROL)) & 0xffbfffff))
+#define SET_RX_GET_TX_QUEUE_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 25) | ((REG32(ADR_CONTROL)) & 0xfdffffff))
+#define SET_HCI_INQ_SEL(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 26) | ((REG32(ADR_CONTROL)) & 0xfbffffff))
+#define SET_TRX_DEBUG_CNT_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 28) | ((REG32(ADR_CONTROL)) & 0xefffffff))
+#define SET_WAKE_SOON_WITH_SCK(_VAL_) (REG32(ADR_SDIO_WAKE_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_WAKE_MODE)) & 0xfffffffe))
+#define SET_TX_FLOW_CTRL(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_0)) & 0xffff0000))
+#define SET_TX_FLOW_MGMT(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FLOW_0)) & 0x0000ffff))
+#define SET_TX_FLOW_DATA(_VAL_) (REG32(ADR_TX_FLOW_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_1)) & 0x00000000))
+#define SET_DOT11RTSTHRESHOLD(_VAL_) (REG32(ADR_THREASHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_THREASHOLD)) & 0x0000ffff))
+#define SET_TXF_ID(_VAL_) (REG32(ADR_TXFID_INCREASE)) = (((_VAL_) << 0) | ((REG32(ADR_TXFID_INCREASE)) & 0xffffffc0))
+#define SET_SEQ_CTRL(_VAL_) (REG32(ADR_GLOBAL_SEQUENCE)) = (((_VAL_) << 0) | ((REG32(ADR_GLOBAL_SEQUENCE)) & 0xffff0000))
+#define SET_TX_PBOFFSET(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffffff00))
+#define SET_TX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffff00ff))
+#define SET_RX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff00ffff))
+#define SET_RX_LAST_PHY_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ffffff))
+#define SET_TX_INFO_CLEAR_SIZE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xffffffc0))
+#define SET_TX_INFO_CLEAR_ENABLE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xfffffeff))
+#define SET_TXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000))
+#define SET_TXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff))
+#define SET_RXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000))
+#define SET_RXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff))
+#define SET_TX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_0)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0x00000000))
+#define SET_RX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_1)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0x00000000))
+#define SET_HOST_CMD_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_2)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0xffffff00))
+#define SET_HOST_EVENT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_3)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0xffffff00))
+#define SET_TX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_4)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0xffffff00))
+#define SET_RX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_5)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0xffffff00))
+#define SET_TX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_6)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0xffffff00))
+#define SET_RX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_7)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0xffffff00))
+#define SET_HOST_TX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0xffffff00))
+#define SET_HOST_RX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0xffffff00))
+#define SET_HCI_STATE_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0x00000000))
+#define SET_HCI_ST_TIMEOUT_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0x00000000))
+#define SET_TX_ON_DEMAND_LENGTH(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0x00000000))
+#define SET_HCI_MONITOR_REG1(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0x00000000))
+#define SET_HCI_MONITOR_REG2(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0x00000000))
+#define SET_HCI_TX_ALLOC_TIME_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0x00000000))
+#define SET_HCI_TX_ALLOC_TIME_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xffff0000))
+#define SET_HCI_MB_MAX_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xff00ffff))
+#define SET_HCI_TX_ALLOC_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0x00000000))
+#define SET_HCI_TX_ALLOC_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xffff0000))
+#define SET_HCI_PROC_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff00ffff))
+#define SET_SDIO_TRANS_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ffffff))
+#define SET_SDIO_TX_INVALID_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0x00000000))
+#define SET_SDIO_TX_INVALID_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0xffff0000))
+#define SET_CS_START_ADDR(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_CS_START_ADDR)) & 0xffff0000))
+#define SET_CS_PKT_ID(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 16) | ((REG32(ADR_CS_START_ADDR)) & 0xff80ffff))
+#define SET_ADD_LEN(_VAL_) (REG32(ADR_CS_ADD_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_CS_ADD_LEN)) & 0xffff0000))
+#define SET_CS_ADDER_EN(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CMD)) & 0xfffffffe))
+#define SET_PSEUDO(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 1) | ((REG32(ADR_CS_CMD)) & 0xfffffffd))
+#define SET_CALCULATE(_VAL_) (REG32(ADR_CS_INI_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_INI_BUF)) & 0x00000000))
+#define SET_L4_LEN(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xffff0000))
+#define SET_L4_PROTOL(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 16) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xff00ffff))
+#define SET_CHECK_SUM(_VAL_) (REG32(ADR_CS_CHECK_SUM)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CHECK_SUM)) & 0xffff0000))
+#define SET_RAND_EN(_VAL_) (REG32(ADR_RAND_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_EN)) & 0xfffffffe))
+#define SET_RAND_NUM(_VAL_) (REG32(ADR_RAND_NUM)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_NUM)) & 0x00000000))
+#define SET_MUL_OP1(_VAL_) (REG32(ADR_MUL_OP1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP1)) & 0x00000000))
+#define SET_MUL_OP2(_VAL_) (REG32(ADR_MUL_OP2)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP2)) & 0x00000000))
+#define SET_MUL_ANS0(_VAL_) (REG32(ADR_MUL_ANS0)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS0)) & 0x00000000))
+#define SET_MUL_ANS1(_VAL_) (REG32(ADR_MUL_ANS1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS1)) & 0x00000000))
+#define SET_RD_ADDR(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_RDATA)) & 0xffff0000))
+#define SET_RD_ID(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_RDATA)) & 0xff80ffff))
+#define SET_WR_ADDR(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_WDATA)) & 0xffff0000))
+#define SET_WR_ID(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_WDATA)) & 0xff80ffff))
+#define SET_LEN(_VAL_) (REG32(ADR_DMA_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_LEN)) & 0xffff0000))
+#define SET_CLR(_VAL_) (REG32(ADR_DMA_CLR)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CLR)) & 0xfffffffe))
+#define SET_PHY_MODE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_NAV_DATA)) & 0xfffffffc))
+#define SET_SHRT_PREAM(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 2) | ((REG32(ADR_NAV_DATA)) & 0xfffffffb))
+#define SET_SHRT_GI(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 3) | ((REG32(ADR_NAV_DATA)) & 0xfffffff7))
+#define SET_DATA_RATE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 4) | ((REG32(ADR_NAV_DATA)) & 0xfffff80f))
+#define SET_MCS(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 12) | ((REG32(ADR_NAV_DATA)) & 0xffff8fff))
+#define SET_FRAME_LEN(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 16) | ((REG32(ADR_NAV_DATA)) & 0x0000ffff))
+#define SET_DURATION(_VAL_) (REG32(ADR_CO_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_CO_NAV)) & 0xffff0000))
+#define SET_SHA_DST_ADDR(_VAL_) (REG32(ADR_SHA_DST_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_DST_ADDR)) & 0x00000000))
+#define SET_SHA_SRC_ADDR(_VAL_) (REG32(ADR_SHA_SRC_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SRC_ADDR)) & 0x00000000))
+#define SET_SHA_BUSY(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffe))
+#define SET_SHA_ENDIAN(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 1) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffd))
+#define SET_EFS_CLKFREQ(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffff000))
+#define SET_LOW_ACTIVE(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffeffff))
+#define SET_EFS_CLKFREQ_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 20) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf00fffff))
+#define SET_EFS_PRE_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 28) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0fffffff))
+#define SET_EFS_LDO_ON(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000))
+#define SET_EFS_LDO_OFF(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff))
+#define SET_EFS_RDATA_0(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0x00000000))
+#define SET_EFS_WDATA_0(_VAL_) (REG32(ADR_EFUSE_WDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_0)) & 0x00000000))
+#define SET_EFS_RDATA_1(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0x00000000))
+#define SET_EFS_WDATA_1(_VAL_) (REG32(ADR_EFUSE_WDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_1)) & 0x00000000))
+#define SET_EFS_RDATA_2(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0x00000000))
+#define SET_EFS_WDATA_2(_VAL_) (REG32(ADR_EFUSE_WDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_2)) & 0x00000000))
+#define SET_EFS_RDATA_3(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0x00000000))
+#define SET_EFS_WDATA_3(_VAL_) (REG32(ADR_EFUSE_WDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_3)) & 0x00000000))
+#define SET_EFS_RDATA_4(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0x00000000))
+#define SET_EFS_WDATA_4(_VAL_) (REG32(ADR_EFUSE_WDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_4)) & 0x00000000))
+#define SET_EFS_RDATA_5(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0x00000000))
+#define SET_EFS_WDATA_5(_VAL_) (REG32(ADR_EFUSE_WDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_5)) & 0x00000000))
+#define SET_EFS_RDATA_6(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0x00000000))
+#define SET_EFS_WDATA_6(_VAL_) (REG32(ADR_EFUSE_WDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_6)) & 0x00000000))
+#define SET_EFS_RDATA_7(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0x00000000))
+#define SET_EFS_WDATA_7(_VAL_) (REG32(ADR_EFUSE_WDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_7)) & 0x00000000))
+#define SET_EFS_SPI_RD0_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD0_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD1_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD1_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD2_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD2_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD3_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD3_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD4_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD4_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD5_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD5_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD6_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD6_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD7_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD7_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RBUSY(_VAL_) (REG32(ADR_EFUSE_SPI_BUSY)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_BUSY)) & 0xfffffffe))
+#define SET_EFS_SPI_RDATA_0(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_1(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_2(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_3(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_4(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_5(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_6(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_7(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0x00000000))
+#define SET_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffe))
+#define SET_FORCE_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffd))
+#define SET_SMS4_DESCRY_EN(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG1)) & 0xffffffef))
+#define SET_DEC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffe))
+#define SET_DEC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffd))
+#define SET_ENC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffb))
+#define SET_ENC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 3) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffff7))
+#define SET_KEY_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG2)) & 0xffffffef))
+#define SET_SMS4_CBC_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffe))
+#define SET_SMS4_CFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffd))
+#define SET_SMS4_OFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffb))
+#define SET_SMS4_START_TRIG(_VAL_) (REG32(ADR_SMS4_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_TRIG)) & 0xfffffffe))
+#define SET_SMS4_BUSY(_VAL_) (REG32(ADR_SMS4_STATUS1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS1)) & 0xfffffffe))
+#define SET_SMS4_DONE(_VAL_) (REG32(ADR_SMS4_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS2)) & 0xfffffffe))
+#define SET_SMS4_DATAIN_0(_VAL_) (REG32(ADR_SMS4_DATA_IN0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN0)) & 0x00000000))
+#define SET_SMS4_DATAIN_1(_VAL_) (REG32(ADR_SMS4_DATA_IN1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN1)) & 0x00000000))
+#define SET_SMS4_DATAIN_2(_VAL_) (REG32(ADR_SMS4_DATA_IN2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN2)) & 0x00000000))
+#define SET_SMS4_DATAIN_3(_VAL_) (REG32(ADR_SMS4_DATA_IN3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN3)) & 0x00000000))
+#define SET_SMS4_DATAOUT_0(_VAL_) (REG32(ADR_SMS4_DATA_OUT0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT0)) & 0x00000000))
+#define SET_SMS4_DATAOUT_1(_VAL_) (REG32(ADR_SMS4_DATA_OUT1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT1)) & 0x00000000))
+#define SET_SMS4_DATAOUT_2(_VAL_) (REG32(ADR_SMS4_DATA_OUT2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT2)) & 0x00000000))
+#define SET_SMS4_DATAOUT_3(_VAL_) (REG32(ADR_SMS4_DATA_OUT3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT3)) & 0x00000000))
+#define SET_SMS4_KEY_0(_VAL_) (REG32(ADR_SMS4_KEY_0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_0)) & 0x00000000))
+#define SET_SMS4_KEY_1(_VAL_) (REG32(ADR_SMS4_KEY_1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_1)) & 0x00000000))
+#define SET_SMS4_KEY_2(_VAL_) (REG32(ADR_SMS4_KEY_2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_2)) & 0x00000000))
+#define SET_SMS4_KEY_3(_VAL_) (REG32(ADR_SMS4_KEY_3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_3)) & 0x00000000))
+#define SET_SMS4_MODE_IV0(_VAL_) (REG32(ADR_SMS4_MODE_IV0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV0)) & 0x00000000))
+#define SET_SMS4_MODE_IV1(_VAL_) (REG32(ADR_SMS4_MODE_IV1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV1)) & 0x00000000))
+#define SET_SMS4_MODE_IV2(_VAL_) (REG32(ADR_SMS4_MODE_IV2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV2)) & 0x00000000))
+#define SET_SMS4_MODE_IV3(_VAL_) (REG32(ADR_SMS4_MODE_IV3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV3)) & 0x00000000))
+#define SET_SMS4_OFB_ENC0(_VAL_) (REG32(ADR_SMS4_OFB_ENC0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC0)) & 0x00000000))
+#define SET_SMS4_OFB_ENC1(_VAL_) (REG32(ADR_SMS4_OFB_ENC1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC1)) & 0x00000000))
+#define SET_SMS4_OFB_ENC2(_VAL_) (REG32(ADR_SMS4_OFB_ENC2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC2)) & 0x00000000))
+#define SET_SMS4_OFB_ENC3(_VAL_) (REG32(ADR_SMS4_OFB_ENC3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC3)) & 0x00000000))
+#define SET_MRX_MCAST_TB0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_0(_VAL_) (REG32(ADR_MRX_MCAST_CTRL0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL0)) & 0xfffffffc))
+#define SET_MRX_MCAST_TB1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_1(_VAL_) (REG32(ADR_MRX_MCAST_CTRL1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL1)) & 0xfffffffc))
+#define SET_MRX_MCAST_TB2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_2(_VAL_) (REG32(ADR_MRX_MCAST_CTRL2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL2)) & 0xfffffffc))
+#define SET_MRX_MCAST_TB3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_3(_VAL_) (REG32(ADR_MRX_MCAST_CTRL3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL3)) & 0xfffffffc))
+#define SET_MRX_PHY_INFO(_VAL_) (REG32(ADR_MRX_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_PHY_INFO)) & 0x00000000))
+#define SET_DBG_BA_TYPE(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_DBG)) & 0xffffffc0))
+#define SET_DBG_BA_SEQ(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 8) | ((REG32(ADR_MRX_BA_DBG)) & 0xfff000ff))
+#define SET_MRX_FLT_TB0(_VAL_) (REG32(ADR_MRX_FLT_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB0)) & 0xffff8000))
+#define SET_MRX_FLT_TB1(_VAL_) (REG32(ADR_MRX_FLT_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB1)) & 0xffff8000))
+#define SET_MRX_FLT_TB2(_VAL_) (REG32(ADR_MRX_FLT_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB2)) & 0xffff8000))
+#define SET_MRX_FLT_TB3(_VAL_) (REG32(ADR_MRX_FLT_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB3)) & 0xffff8000))
+#define SET_MRX_FLT_TB4(_VAL_) (REG32(ADR_MRX_FLT_TB4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB4)) & 0xffff8000))
+#define SET_MRX_FLT_TB5(_VAL_) (REG32(ADR_MRX_FLT_TB5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB5)) & 0xffff8000))
+#define SET_MRX_FLT_TB6(_VAL_) (REG32(ADR_MRX_FLT_TB6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB6)) & 0xffff8000))
+#define SET_MRX_FLT_TB7(_VAL_) (REG32(ADR_MRX_FLT_TB7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB7)) & 0xffff8000))
+#define SET_MRX_FLT_TB8(_VAL_) (REG32(ADR_MRX_FLT_TB8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB8)) & 0xffff8000))
+#define SET_MRX_FLT_TB9(_VAL_) (REG32(ADR_MRX_FLT_TB9)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB9)) & 0xffff8000))
+#define SET_MRX_FLT_TB10(_VAL_) (REG32(ADR_MRX_FLT_TB10)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB10)) & 0xffff8000))
+#define SET_MRX_FLT_TB11(_VAL_) (REG32(ADR_MRX_FLT_TB11)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB11)) & 0xffff8000))
+#define SET_MRX_FLT_TB12(_VAL_) (REG32(ADR_MRX_FLT_TB12)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB12)) & 0xffff8000))
+#define SET_MRX_FLT_TB13(_VAL_) (REG32(ADR_MRX_FLT_TB13)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB13)) & 0xffff8000))
+#define SET_MRX_FLT_TB14(_VAL_) (REG32(ADR_MRX_FLT_TB14)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB14)) & 0xffff8000))
+#define SET_MRX_FLT_TB15(_VAL_) (REG32(ADR_MRX_FLT_TB15)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB15)) & 0xffff8000))
+#define SET_MRX_FLT_EN0(_VAL_) (REG32(ADR_MRX_FLT_EN0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN0)) & 0xffff0000))
+#define SET_MRX_FLT_EN1(_VAL_) (REG32(ADR_MRX_FLT_EN1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN1)) & 0xffff0000))
+#define SET_MRX_FLT_EN2(_VAL_) (REG32(ADR_MRX_FLT_EN2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN2)) & 0xffff0000))
+#define SET_MRX_FLT_EN3(_VAL_) (REG32(ADR_MRX_FLT_EN3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN3)) & 0xffff0000))
+#define SET_MRX_FLT_EN4(_VAL_) (REG32(ADR_MRX_FLT_EN4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN4)) & 0xffff0000))
+#define SET_MRX_FLT_EN5(_VAL_) (REG32(ADR_MRX_FLT_EN5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN5)) & 0xffff0000))
+#define SET_MRX_FLT_EN6(_VAL_) (REG32(ADR_MRX_FLT_EN6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN6)) & 0xffff0000))
+#define SET_MRX_FLT_EN7(_VAL_) (REG32(ADR_MRX_FLT_EN7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN7)) & 0xffff0000))
+#define SET_MRX_FLT_EN8(_VAL_) (REG32(ADR_MRX_FLT_EN8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN8)) & 0xffff0000))
+#define SET_MRX_LEN_FLT(_VAL_) (REG32(ADR_MRX_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_LEN_FLT)) & 0xffff0000))
+#define SET_RX_FLOW_DATA(_VAL_) (REG32(ADR_RX_FLOW_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_DATA)) & 0x00000000))
+#define SET_RX_FLOW_MNG(_VAL_) (REG32(ADR_RX_FLOW_MNG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_MNG)) & 0xffff0000))
+#define SET_RX_FLOW_CTRL(_VAL_) (REG32(ADR_RX_FLOW_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_CTRL)) & 0xffff0000))
+#define SET_MRX_STP_EN(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xfffffffe))
+#define SET_MRX_STP_OFST(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xffff00ff))
+#define SET_DBG_FF_FULL(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_FF_FULL)) & 0xffff0000))
+#define SET_DBG_FF_FULL_CLR(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_FF_FULL)) & 0x7fffffff))
+#define SET_DBG_WFF_FULL(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_WFF_FULL)) & 0xffff0000))
+#define SET_DBG_WFF_FULL_CLR(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_WFF_FULL)) & 0x7fffffff))
+#define SET_DBG_MB_FULL(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_MB_FULL)) & 0xffff0000))
+#define SET_DBG_MB_FULL_CLR(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_MB_FULL)) & 0x7fffffff))
+#define SET_BA_CTRL(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BA_CTRL)) & 0xfffffffc))
+#define SET_BA_DBG_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_BA_CTRL)) & 0xfffffffb))
+#define SET_BA_AGRE_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_BA_CTRL)) & 0xfffffff7))
+#define SET_BA_TA_31_0(_VAL_) (REG32(ADR_BA_TA_0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_0)) & 0x00000000))
+#define SET_BA_TA_47_32(_VAL_) (REG32(ADR_BA_TA_1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_1)) & 0xffff0000))
+#define SET_BA_TID(_VAL_) (REG32(ADR_BA_TID)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TID)) & 0xfffffff0))
+#define SET_BA_ST_SEQ(_VAL_) (REG32(ADR_BA_ST_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_BA_ST_SEQ)) & 0xfffff000))
+#define SET_BA_SB0(_VAL_) (REG32(ADR_BA_SB0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB0)) & 0x00000000))
+#define SET_BA_SB1(_VAL_) (REG32(ADR_BA_SB1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB1)) & 0x00000000))
+#define SET_MRX_WD(_VAL_) (REG32(ADR_MRX_WATCH_DOG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_WATCH_DOG)) & 0xfffe0000))
+#define SET_ACK_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffe))
+#define SET_BA_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 1) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffd))
+#define SET_ACK_GEN_DUR(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffff0000))
+#define SET_ACK_GEN_INFO(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 16) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffc0ffff))
+#define SET_ACK_GEN_RA_31_0(_VAL_) (REG32(ADR_ACK_GEN_RA_0)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_0)) & 0x00000000))
+#define SET_ACK_GEN_RA_47_32(_VAL_) (REG32(ADR_ACK_GEN_RA_1)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_1)) & 0xffff0000))
+#define SET_MIB_LEN_FAIL(_VAL_) (REG32(ADR_MIB_LEN_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_LEN_FAIL)) & 0xffff0000))
+#define SET_TRAP_HW_ID(_VAL_) (REG32(ADR_TRAP_HW_ID)) = (((_VAL_) << 0) | ((REG32(ADR_TRAP_HW_ID)) & 0xfffffff0))
+#define SET_ID_IN_USE(_VAL_) (REG32(ADR_ID_IN_USE)) = (((_VAL_) << 0) | ((REG32(ADR_ID_IN_USE)) & 0xffffff00))
+#define SET_MRX_ERR(_VAL_) (REG32(ADR_MRX_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ERR)) & 0x00000000))
+#define SET_W0_T0_SEQ(_VAL_) (REG32(ADR_WSID0_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T1_SEQ(_VAL_) (REG32(ADR_WSID0_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T2_SEQ(_VAL_) (REG32(ADR_WSID0_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T3_SEQ(_VAL_) (REG32(ADR_WSID0_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T4_SEQ(_VAL_) (REG32(ADR_WSID0_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T5_SEQ(_VAL_) (REG32(ADR_WSID0_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T6_SEQ(_VAL_) (REG32(ADR_WSID0_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T7_SEQ(_VAL_) (REG32(ADR_WSID0_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T0_SEQ(_VAL_) (REG32(ADR_WSID1_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T1_SEQ(_VAL_) (REG32(ADR_WSID1_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T2_SEQ(_VAL_) (REG32(ADR_WSID1_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T3_SEQ(_VAL_) (REG32(ADR_WSID1_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T4_SEQ(_VAL_) (REG32(ADR_WSID1_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T5_SEQ(_VAL_) (REG32(ADR_WSID1_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T6_SEQ(_VAL_) (REG32(ADR_WSID1_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T7_SEQ(_VAL_) (REG32(ADR_WSID1_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0xffff0000))
+#define SET_ADDR1A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffffc))
+#define SET_ADDR2A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 2) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffff3))
+#define SET_ADDR3A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 4) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffffcf))
+#define SET_ADDR1B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 6) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffff3f))
+#define SET_ADDR2B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffcff))
+#define SET_ADDR3B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 10) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffff3ff))
+#define SET_ADDR3C_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 12) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffcfff))
+#define SET_FRM_CTRL(_VAL_) (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (((_VAL_) << 0) | ((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0xffffffc0))
+#define SET_CSR_PHY_INFO(_VAL_) (REG32(ADR_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_INFO)) & 0xffff8000))
+#define SET_AMPDU_SIG(_VAL_) (REG32(ADR_AMPDU_SIG)) = (((_VAL_) << 0) | ((REG32(ADR_AMPDU_SIG)) & 0xffffff00))
+#define SET_MIB_AMPDU(_VAL_) (REG32(ADR_MIB_AMPDU)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_AMPDU)) & 0x00000000))
+#define SET_LEN_FLT(_VAL_) (REG32(ADR_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_LEN_FLT)) & 0xffff0000))
+#define SET_MIB_DELIMITER(_VAL_) (REG32(ADR_MIB_DELIMITER)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_DELIMITER)) & 0xffff0000))
+#define SET_MTX_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_STS)) & 0xfffeffff))
+#define SET_MTX_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_STS)) & 0xfffdffff))
+#define SET_MTX_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_STS)) & 0xfffbffff))
+#define SET_MTX_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_STS)) & 0xfff7ffff))
+#define SET_MTX_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_STS)) & 0xffefffff))
+#define SET_MTX_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_STS)) & 0xffdfffff))
+#define SET_MTX_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_STS)) & 0xffbfffff))
+#define SET_MTX_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_STS)) & 0xff7fffff))
+#define SET_MTX_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_STS)) & 0xfeffffff))
+#define SET_MTX_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_STS)) & 0xfdffffff))
+#define SET_MTX_EN_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_EN)) & 0xfffeffff))
+#define SET_MTX_EN_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_EN)) & 0xfffdffff))
+#define SET_MTX_EN_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_EN)) & 0xfffbffff))
+#define SET_MTX_EN_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_EN)) & 0xfff7ffff))
+#define SET_MTX_EN_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_EN)) & 0xffefffff))
+#define SET_MTX_EN_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_EN)) & 0xffdfffff))
+#define SET_MTX_EN_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_EN)) & 0xffbfffff))
+#define SET_MTX_EN_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_EN)) & 0xff7fffff))
+#define SET_MTX_EN_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_EN)) & 0xfeffffff))
+#define SET_MTX_EN_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_EN)) & 0xfdffffff))
+#define SET_MTX_MTX2PHY_SLOW(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffffe))
+#define SET_MTX_M2M_SLOW_PRD(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffff1))
+#define SET_MTX_AMPDU_CRC_AUTO(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffdf))
+#define SET_MTX_FAST_RSP_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffbf))
+#define SET_MTX_RAW_DATA_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffff7f))
+#define SET_MTX_ACK_DUR0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffeff))
+#define SET_MTX_TSF_AUTO_BCN(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffbff))
+#define SET_MTX_TSF_AUTO_MISC(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffff7ff))
+#define SET_MTX_FORCE_CS_IDLE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffefff))
+#define SET_MTX_FORCE_BKF_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffdfff))
+#define SET_MTX_FORCE_DMA_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffbfff))
+#define SET_MTX_FORCE_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_MISC_EN)) & 0xffff7fff))
+#define SET_MTX_HALT_Q_MB(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_MISC_EN)) & 0xffc0ffff))
+#define SET_MTX_CTS_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_MISC_EN)) & 0xffbfffff))
+#define SET_MTX_AMPDU_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_MISC_EN)) & 0xff7fffff))
+#define SET_MTX_EDCCA_TOUT(_VAL_) (REG32(ADR_MTX_EDCCA_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_EDCCA_TOUT)) & 0xfffffc00))
+#define SET_MTX_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffffd))
+#define SET_MTX_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffff7))
+#define SET_MTX_EN_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffffd))
+#define SET_MTX_EN_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffff7))
+#define SET_MTX_BCN_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffe))
+#define SET_MTX_TIME_STAMP_AUTO_FILL(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffd))
+#define SET_MTX_TSF_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffdf))
+#define SET_MTX_HALT_MNG_UNTIL_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffbf))
+#define SET_MTX_INT_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffff00ff))
+#define SET_MTX_AUTO_FLUSH_Q4(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffeffff))
+#define SET_MTX_BCN_PKTID_CH_LOCK(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffffe))
+#define SET_MTX_BCN_CFG_VLD(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff9))
+#define SET_MTX_AUTO_BCN_ONGOING(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff7))
+#define SET_MTX_BCN_TIMER(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_MISC)) & 0x0000ffff))
+#define SET_MTX_BCN_PERIOD(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_PRD)) & 0xffff0000))
+#define SET_MTX_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_BCN_PRD)) & 0x00ffffff))
+#define SET_MTX_BCN_TSF_L(_VAL_) (REG32(ADR_MTX_BCN_TSF_L)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_L)) & 0x00000000))
+#define SET_MTX_BCN_TSF_U(_VAL_) (REG32(ADR_MTX_BCN_TSF_U)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_U)) & 0x00000000))
+#define SET_MTX_BCN_PKT_ID0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xffffff80))
+#define SET_MTX_DTIM_OFST0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xfc00ffff))
+#define SET_MTX_BCN_PKT_ID1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xffffff80))
+#define SET_MTX_DTIM_OFST1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xfc00ffff))
+#define SET_MTX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffe))
+#define SET_MRX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffd))
+#define SET_MTX_DMA_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 2) | ((REG32(ADR_MTX_STATUS)) & 0xffffffe3))
+#define SET_CH_ST_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_STATUS)) & 0xffffff1f))
+#define SET_MTX_GNT_LOCK(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_STATUS)) & 0xfffffeff))
+#define SET_MTX_DMA_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MTX_STATUS)) & 0xfffffdff))
+#define SET_MTX_Q_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_STATUS)) & 0xfffffbff))
+#define SET_MTX_TX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_STATUS)) & 0xfffff7ff))
+#define SET_MRX_RX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_STATUS)) & 0xffffefff))
+#define SET_DBG_PRTC_PRD(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_STATUS)) & 0xffffdfff))
+#define SET_DBG_DMA_RDY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_STATUS)) & 0xffffbfff))
+#define SET_DBG_WAIT_RSP(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_STATUS)) & 0xffff7fff))
+#define SET_DBG_CFRM_BUSY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_STATUS)) & 0xfffeffff))
+#define SET_DBG_RST(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffe))
+#define SET_DBG_MODE(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffd))
+#define SET_MB_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000))
+#define SET_RX_EN_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff))
+#define SET_RX_CS_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000))
+#define SET_TX_CCA_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff))
+#define SET_Q_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000))
+#define SET_CH_STA0_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff))
+#define SET_MTX_DUR_RSP_TOUT_B(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffffff00))
+#define SET_MTX_DUR_RSP_TOUT_G(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffff00ff))
+#define SET_MTX_DUR_RSP_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffffff00))
+#define SET_MTX_DUR_BURST_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffff00ff))
+#define SET_MTX_DUR_SLOT(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffc0ffff))
+#define SET_MTX_DUR_RSP_EIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_IFS)) & 0x003fffff))
+#define SET_MTX_DUR_RSP_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffffff00))
+#define SET_MTX_DUR_BURST_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffff00ff))
+#define SET_MTX_DUR_SLOT_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc0ffff))
+#define SET_MTX_DUR_RSP_EIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003fffff))
+#define SET_CH_STA1_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000))
+#define SET_CH_STA2_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff))
+#define SET_MTX_NAV(_VAL_) (REG32(ADR_MTX_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_NAV)) & 0xffff0000))
+#define SET_MTX_MIB_CNT0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xc0000000))
+#define SET_MTX_MIB_EN0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xbfffffff))
+#define SET_MTX_MIB_CNT1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xc0000000))
+#define SET_MTX_MIB_EN1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xbfffffff))
+#define SET_CH_STA3_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000))
+#define SET_CH_STA4_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff))
+#define SET_TXQ0_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ0_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ0_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ0_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ0_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ0_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ0_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ0_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ0_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ0_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ0_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ0_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ0_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ0_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ0_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ1_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ1_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ1_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ1_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ1_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ1_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ1_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ1_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ1_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ1_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ1_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ1_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ1_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ1_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ1_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ2_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ2_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ2_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ2_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ2_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ2_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ2_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ2_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ2_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ2_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ2_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ2_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ2_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ2_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ2_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ3_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ3_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ3_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ3_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ3_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ3_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ3_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ3_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ3_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ3_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ3_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ3_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ3_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ3_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ3_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ4_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ4_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ4_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ4_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ4_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ4_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ4_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ4_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ4_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ4_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ4_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ4_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ4_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ4_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ4_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_VALID0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0)) & 0xfffffffe))
+#define SET_PEER_QOS_EN0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 1) | ((REG32(ADR_WSID0)) & 0xfffffffd))
+#define SET_PEER_OP_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 2) | ((REG32(ADR_WSID0)) & 0xfffffff3))
+#define SET_PEER_HT_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 4) | ((REG32(ADR_WSID0)) & 0xffffffcf))
+#define SET_PEER_MAC0_31_0(_VAL_) (REG32(ADR_PEER_MAC0_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_0)) & 0x00000000))
+#define SET_PEER_MAC0_47_32(_VAL_) (REG32(ADR_PEER_MAC0_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_1)) & 0xffff0000))
+#define SET_TX_ACK_POLICY_0_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_0)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_1)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_2)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_3)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_4)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_5)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_6)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_7)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0xfffff000))
+#define SET_VALID1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1)) & 0xfffffffe))
+#define SET_PEER_QOS_EN1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 1) | ((REG32(ADR_WSID1)) & 0xfffffffd))
+#define SET_PEER_OP_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 2) | ((REG32(ADR_WSID1)) & 0xfffffff3))
+#define SET_PEER_HT_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 4) | ((REG32(ADR_WSID1)) & 0xffffffcf))
+#define SET_PEER_MAC1_31_0(_VAL_) (REG32(ADR_PEER_MAC1_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_0)) & 0x00000000))
+#define SET_PEER_MAC1_47_32(_VAL_) (REG32(ADR_PEER_MAC1_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_1)) & 0xffff0000))
+#define SET_TX_ACK_POLICY_1_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_0)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_1)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_2)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_3)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_4)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_5)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_6)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_7)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0xfffff000))
+#define SET_INFO0(_VAL_) (REG32(ADR_INFO0)) = (((_VAL_) << 0) | ((REG32(ADR_INFO0)) & 0x00000000))
+#define SET_INFO1(_VAL_) (REG32(ADR_INFO1)) = (((_VAL_) << 0) | ((REG32(ADR_INFO1)) & 0x00000000))
+#define SET_INFO2(_VAL_) (REG32(ADR_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_INFO2)) & 0x00000000))
+#define SET_INFO3(_VAL_) (REG32(ADR_INFO3)) = (((_VAL_) << 0) | ((REG32(ADR_INFO3)) & 0x00000000))
+#define SET_INFO4(_VAL_) (REG32(ADR_INFO4)) = (((_VAL_) << 0) | ((REG32(ADR_INFO4)) & 0x00000000))
+#define SET_INFO5(_VAL_) (REG32(ADR_INFO5)) = (((_VAL_) << 0) | ((REG32(ADR_INFO5)) & 0x00000000))
+#define SET_INFO6(_VAL_) (REG32(ADR_INFO6)) = (((_VAL_) << 0) | ((REG32(ADR_INFO6)) & 0x00000000))
+#define SET_INFO7(_VAL_) (REG32(ADR_INFO7)) = (((_VAL_) << 0) | ((REG32(ADR_INFO7)) & 0x00000000))
+#define SET_INFO8(_VAL_) (REG32(ADR_INFO8)) = (((_VAL_) << 0) | ((REG32(ADR_INFO8)) & 0x00000000))
+#define SET_INFO9(_VAL_) (REG32(ADR_INFO9)) = (((_VAL_) << 0) | ((REG32(ADR_INFO9)) & 0x00000000))
+#define SET_INFO10(_VAL_) (REG32(ADR_INFO10)) = (((_VAL_) << 0) | ((REG32(ADR_INFO10)) & 0x00000000))
+#define SET_INFO11(_VAL_) (REG32(ADR_INFO11)) = (((_VAL_) << 0) | ((REG32(ADR_INFO11)) & 0x00000000))
+#define SET_INFO12(_VAL_) (REG32(ADR_INFO12)) = (((_VAL_) << 0) | ((REG32(ADR_INFO12)) & 0x00000000))
+#define SET_INFO13(_VAL_) (REG32(ADR_INFO13)) = (((_VAL_) << 0) | ((REG32(ADR_INFO13)) & 0x00000000))
+#define SET_INFO14(_VAL_) (REG32(ADR_INFO14)) = (((_VAL_) << 0) | ((REG32(ADR_INFO14)) & 0x00000000))
+#define SET_INFO15(_VAL_) (REG32(ADR_INFO15)) = (((_VAL_) << 0) | ((REG32(ADR_INFO15)) & 0x00000000))
+#define SET_INFO16(_VAL_) (REG32(ADR_INFO16)) = (((_VAL_) << 0) | ((REG32(ADR_INFO16)) & 0x00000000))
+#define SET_INFO17(_VAL_) (REG32(ADR_INFO17)) = (((_VAL_) << 0) | ((REG32(ADR_INFO17)) & 0x00000000))
+#define SET_INFO18(_VAL_) (REG32(ADR_INFO18)) = (((_VAL_) << 0) | ((REG32(ADR_INFO18)) & 0x00000000))
+#define SET_INFO19(_VAL_) (REG32(ADR_INFO19)) = (((_VAL_) << 0) | ((REG32(ADR_INFO19)) & 0x00000000))
+#define SET_INFO20(_VAL_) (REG32(ADR_INFO20)) = (((_VAL_) << 0) | ((REG32(ADR_INFO20)) & 0x00000000))
+#define SET_INFO21(_VAL_) (REG32(ADR_INFO21)) = (((_VAL_) << 0) | ((REG32(ADR_INFO21)) & 0x00000000))
+#define SET_INFO22(_VAL_) (REG32(ADR_INFO22)) = (((_VAL_) << 0) | ((REG32(ADR_INFO22)) & 0x00000000))
+#define SET_INFO23(_VAL_) (REG32(ADR_INFO23)) = (((_VAL_) << 0) | ((REG32(ADR_INFO23)) & 0x00000000))
+#define SET_INFO24(_VAL_) (REG32(ADR_INFO24)) = (((_VAL_) << 0) | ((REG32(ADR_INFO24)) & 0x00000000))
+#define SET_INFO25(_VAL_) (REG32(ADR_INFO25)) = (((_VAL_) << 0) | ((REG32(ADR_INFO25)) & 0x00000000))
+#define SET_INFO26(_VAL_) (REG32(ADR_INFO26)) = (((_VAL_) << 0) | ((REG32(ADR_INFO26)) & 0x00000000))
+#define SET_INFO27(_VAL_) (REG32(ADR_INFO27)) = (((_VAL_) << 0) | ((REG32(ADR_INFO27)) & 0x00000000))
+#define SET_INFO28(_VAL_) (REG32(ADR_INFO28)) = (((_VAL_) << 0) | ((REG32(ADR_INFO28)) & 0x00000000))
+#define SET_INFO29(_VAL_) (REG32(ADR_INFO29)) = (((_VAL_) << 0) | ((REG32(ADR_INFO29)) & 0x00000000))
+#define SET_INFO30(_VAL_) (REG32(ADR_INFO30)) = (((_VAL_) << 0) | ((REG32(ADR_INFO30)) & 0x00000000))
+#define SET_INFO31(_VAL_) (REG32(ADR_INFO31)) = (((_VAL_) << 0) | ((REG32(ADR_INFO31)) & 0x00000000))
+#define SET_INFO32(_VAL_) (REG32(ADR_INFO32)) = (((_VAL_) << 0) | ((REG32(ADR_INFO32)) & 0x00000000))
+#define SET_INFO33(_VAL_) (REG32(ADR_INFO33)) = (((_VAL_) << 0) | ((REG32(ADR_INFO33)) & 0x00000000))
+#define SET_INFO34(_VAL_) (REG32(ADR_INFO34)) = (((_VAL_) << 0) | ((REG32(ADR_INFO34)) & 0x00000000))
+#define SET_INFO35(_VAL_) (REG32(ADR_INFO35)) = (((_VAL_) << 0) | ((REG32(ADR_INFO35)) & 0x00000000))
+#define SET_INFO36(_VAL_) (REG32(ADR_INFO36)) = (((_VAL_) << 0) | ((REG32(ADR_INFO36)) & 0x00000000))
+#define SET_INFO37(_VAL_) (REG32(ADR_INFO37)) = (((_VAL_) << 0) | ((REG32(ADR_INFO37)) & 0x00000000))
+#define SET_INFO38(_VAL_) (REG32(ADR_INFO38)) = (((_VAL_) << 0) | ((REG32(ADR_INFO38)) & 0x00000000))
+#define SET_INFO_MASK(_VAL_) (REG32(ADR_INFO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_MASK)) & 0x00000000))
+#define SET_INFO_DEF_RATE(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xffffffc0))
+#define SET_INFO_MRX_OFFSET(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xfff0ffff))
+#define SET_BCAST_RATEUNKNOW(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 24) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xc0ffffff))
+#define SET_INFO_IDX_TBL_ADDR(_VAL_) (REG32(ADR_INFO_IDX_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_IDX_ADDR)) & 0x00000000))
+#define SET_INFO_LEN_TBL_ADDR(_VAL_) (REG32(ADR_INFO_LEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_LEN_ADDR)) & 0x00000000))
+#define SET_IC_TAG_31_0(_VAL_) (REG32(ADR_IC_TIME_TAG_0)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_0)) & 0x00000000))
+#define SET_IC_TAG_63_32(_VAL_) (REG32(ADR_IC_TIME_TAG_1)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_1)) & 0x00000000))
+#define SET_CH1_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffffc))
+#define SET_CH2_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 8) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffcff))
+#define SET_CH3_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 16) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffcffff))
+#define SET_RG_MAC_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_MODE)) & 0xfffffffe))
+#define SET_RG_MAC_M2M(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_MODE)) & 0xfffffffd))
+#define SET_RG_PHY_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_MAC_MODE)) & 0xfffffffb))
+#define SET_RG_LPBK_RX_EN(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_MODE)) & 0xfffffff7))
+#define SET_EXT_MAC_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_MODE)) & 0xffffffef))
+#define SET_EXT_PHY_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_MODE)) & 0xffffffdf))
+#define SET_ASIC_TAG(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 24) | ((REG32(ADR_MAC_MODE)) & 0x00ffffff))
+#define SET_HCI_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffe))
+#define SET_CO_PROC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffd))
+#define SET_MTX_MISC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffff7))
+#define SET_MTX_QUE_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffef))
+#define SET_MTX_CHST_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffdf))
+#define SET_MTX_BCN_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffbf))
+#define SET_MRX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffff7f))
+#define SET_AMPDU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffeff))
+#define SET_MMU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffdff))
+#define SET_ID_MNG_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffff7ff))
+#define SET_MBOX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffefff))
+#define SET_SCRT_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffdfff))
+#define SET_MIC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffbfff))
+#define SET_CO_PROC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffffd))
+#define SET_MTX_MISC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffff7))
+#define SET_MTX_QUE_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffef))
+#define SET_MTX_CHST_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffdf))
+#define SET_MTX_BCN_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffbf))
+#define SET_MRX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffff7f))
+#define SET_AMPDU_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffeff))
+#define SET_ID_MNG_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffbfff))
+#define SET_MBOX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffff7fff))
+#define SET_SCRT_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 16) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffeffff))
+#define SET_MIC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 17) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffdffff))
+#define SET_CO_PROC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffffd))
+#define SET_MTX_MISC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffff7))
+#define SET_MTX_QUE0_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffef))
+#define SET_MTX_QUE1_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffdf))
+#define SET_MTX_QUE2_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffbf))
+#define SET_MTX_QUE3_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffff7f))
+#define SET_MTX_QUE4_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffeff))
+#define SET_MTX_QUE5_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffdff))
+#define SET_MRX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffbff))
+#define SET_AMPDU_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffff7ff))
+#define SET_SCRT_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffdfff))
+#define SET_ID_MNG_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffbfff))
+#define SET_MBOX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffff7fff))
+#define SET_HCI_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffe))
+#define SET_CO_PROC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MTX_MISC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffff7))
+#define SET_MTX_QUE_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffef))
+#define SET_MRX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffdf))
+#define SET_AMPDU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffbf))
+#define SET_MMU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffff7f))
+#define SET_ID_MNG_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffdff))
+#define SET_MBOX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_SCRT_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffff7ff))
+#define SET_MIC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffefff))
+#define SET_MIB_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_HCI_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffe))
+#define SET_CO_PROC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MTX_MISC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffff7))
+#define SET_MTX_QUE_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffef))
+#define SET_MRX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffdf))
+#define SET_AMPDU_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffbf))
+#define SET_ID_MNG_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffefff))
+#define SET_MBOX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_SCRT_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffbfff))
+#define SET_MIC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffff7fff))
+#define SET_CO_PROC_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MRX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_AMPDU_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffff7ff))
+#define SET_SCRT_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_ID_MNG_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffbfff))
+#define SET_MBOX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffff7fff))
+#define SET_OP_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 0) | ((REG32(ADR_GLBLE_SET)) & 0xfffffffc))
+#define SET_HT_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 2) | ((REG32(ADR_GLBLE_SET)) & 0xfffffff3))
+#define SET_QOS_EN(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 4) | ((REG32(ADR_GLBLE_SET)) & 0xffffffef))
+#define SET_PB_OFFSET(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 8) | ((REG32(ADR_GLBLE_SET)) & 0xffff00ff))
+#define SET_SNIFFER_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 16) | ((REG32(ADR_GLBLE_SET)) & 0xfffeffff))
+#define SET_DUP_FLT(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 17) | ((REG32(ADR_GLBLE_SET)) & 0xfffdffff))
+#define SET_TX_PKT_RSVD(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 18) | ((REG32(ADR_GLBLE_SET)) & 0xffe3ffff))
+#define SET_AMPDU_SNIFFER(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 21) | ((REG32(ADR_GLBLE_SET)) & 0xffdfffff))
+#define SET_REASON_TRAP0(_VAL_) (REG32(ADR_REASON_TRAP0)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP0)) & 0x00000000))
+#define SET_REASON_TRAP1(_VAL_) (REG32(ADR_REASON_TRAP1)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP1)) & 0x00000000))
+#define SET_BSSID_31_0(_VAL_) (REG32(ADR_BSSID_0)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_0)) & 0x00000000))
+#define SET_BSSID_47_32(_VAL_) (REG32(ADR_BSSID_1)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_1)) & 0xffff0000))
+#define SET_SCRT_STATE(_VAL_) (REG32(ADR_SCRT_STATE)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_STATE)) & 0xfffffff0))
+#define SET_STA_MAC_31_0(_VAL_) (REG32(ADR_STA_MAC_0)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_0)) & 0x00000000))
+#define SET_STA_MAC_47_32(_VAL_) (REG32(ADR_STA_MAC_1)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_1)) & 0xffff0000))
+#define SET_PAIR_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_SET)) & 0xfffffff8))
+#define SET_GRP_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 3) | ((REG32(ADR_SCRT_SET)) & 0xffffffc7))
+#define SET_SCRT_PKT_ID(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 6) | ((REG32(ADR_SCRT_SET)) & 0xffffe03f))
+#define SET_SCRT_RPLY_IGNORE(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 16) | ((REG32(ADR_SCRT_SET)) & 0xfffeffff))
+#define SET_COEXIST_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX0)) & 0xfffffffe))
+#define SET_WIRE_MODE(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 1) | ((REG32(ADR_BTCX0)) & 0xfffffff1))
+#define SET_WL_RX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 4) | ((REG32(ADR_BTCX0)) & 0xffffffef))
+#define SET_WL_TX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 5) | ((REG32(ADR_BTCX0)) & 0xffffffdf))
+#define SET_GURAN_USE_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX0)) & 0xfffffeff))
+#define SET_GURAN_USE_CTRL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 9) | ((REG32(ADR_BTCX0)) & 0xfffffdff))
+#define SET_BEACON_TIMEOUT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 10) | ((REG32(ADR_BTCX0)) & 0xfffffbff))
+#define SET_WLAN_ACT_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 11) | ((REG32(ADR_BTCX0)) & 0xfffff7ff))
+#define SET_DUAL_ANT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 12) | ((REG32(ADR_BTCX0)) & 0xffffefff))
+#define SET_TRSW_PHY_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX0)) & 0xfffeffff))
+#define SET_WIFI_TX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 17) | ((REG32(ADR_BTCX0)) & 0xfffdffff))
+#define SET_WIFI_RX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 18) | ((REG32(ADR_BTCX0)) & 0xfffbffff))
+#define SET_BT_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 19) | ((REG32(ADR_BTCX0)) & 0xfff7ffff))
+#define SET_BT_PRI_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX1)) & 0xffffff00))
+#define SET_BT_STA_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX1)) & 0xffff00ff))
+#define SET_BEACON_TIMEOUT(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX1)) & 0xff00ffff))
+#define SET_WLAN_REMAIN_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 24) | ((REG32(ADR_BTCX1)) & 0x00ffffff))
+#define SET_SW_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffe))
+#define SET_SW_WL_TX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 1) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffd))
+#define SET_SW_WL_RX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 2) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffb))
+#define SET_SW_BT_TRX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 3) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffff7))
+#define SET_BT_TXBAR_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 4) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffef))
+#define SET_BT_TXBAR_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 5) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffdf))
+#define SET_BT_BUSY_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffeff))
+#define SET_BT_BUSY_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 9) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffdff))
+#define SET_G0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 2) | ((REG32(ADR_MIB_EN)) & 0xfffffffb))
+#define SET_G0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 3) | ((REG32(ADR_MIB_EN)) & 0xfffffff7))
+#define SET_G1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 4) | ((REG32(ADR_MIB_EN)) & 0xffffffef))
+#define SET_G1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MIB_EN)) & 0xffffffdf))
+#define SET_Q0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MIB_EN)) & 0xffffffbf))
+#define SET_Q0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MIB_EN)) & 0xffffff7f))
+#define SET_Q1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MIB_EN)) & 0xfffffeff))
+#define SET_Q1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 9) | ((REG32(ADR_MIB_EN)) & 0xfffffdff))
+#define SET_Q2_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MIB_EN)) & 0xfffffbff))
+#define SET_Q2_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MIB_EN)) & 0xfffff7ff))
+#define SET_Q3_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MIB_EN)) & 0xffffefff))
+#define SET_Q3_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MIB_EN)) & 0xffffdfff))
+#define SET_SCRT_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MIB_EN)) & 0xffffbfff))
+#define SET_SCRT_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MIB_EN)) & 0xffff7fff))
+#define SET_MISC_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MIB_EN)) & 0xfffeffff))
+#define SET_MISC_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MIB_EN)) & 0xfffdffff))
+#define SET_MTX_WSID0_SUCC(_VAL_) (REG32(ADR_MTX_WSID0_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_SUCC)) & 0xffff0000))
+#define SET_MTX_WSID0_FRM(_VAL_) (REG32(ADR_MTX_WSID0_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_FRM)) & 0xffff0000))
+#define SET_MTX_WSID0_RETRY(_VAL_) (REG32(ADR_MTX_WSID0_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_RETRY)) & 0xffff0000))
+#define SET_MTX_WSID0_TOTAL(_VAL_) (REG32(ADR_MTX_WSID0_TOTAL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_TOTAL)) & 0xffff0000))
+#define SET_MTX_GRP(_VAL_) (REG32(ADR_MTX_GROUP)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_GROUP)) & 0xfff00000))
+#define SET_MTX_FAIL(_VAL_) (REG32(ADR_MTX_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FAIL)) & 0xffff0000))
+#define SET_MTX_RETRY(_VAL_) (REG32(ADR_MTX_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RETRY)) & 0xfff00000))
+#define SET_MTX_MULTI_RETRY(_VAL_) (REG32(ADR_MTX_MULTI_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MULTI_RETRY)) & 0xfff00000))
+#define SET_MTX_RTS_SUCC(_VAL_) (REG32(ADR_MTX_RTS_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_SUCCESS)) & 0xffff0000))
+#define SET_MTX_RTS_FAIL(_VAL_) (REG32(ADR_MTX_RTS_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_FAIL)) & 0xffff0000))
+#define SET_MTX_ACK_FAIL(_VAL_) (REG32(ADR_MTX_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_FAIL)) & 0xffff0000))
+#define SET_MTX_FRM(_VAL_) (REG32(ADR_MTX_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FRM)) & 0xfff00000))
+#define SET_MTX_ACK_TX(_VAL_) (REG32(ADR_MTX_ACK_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_TX)) & 0xffff0000))
+#define SET_MTX_CTS_TX(_VAL_) (REG32(ADR_MTX_CTS_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_CTS_TX)) & 0xffff0000))
+#define SET_MRX_DUP(_VAL_) (REG32(ADR_MRX_DUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DUP_FRM)) & 0xffff0000))
+#define SET_MRX_FRG(_VAL_) (REG32(ADR_MRX_FRG_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FRG_FRM)) & 0xfff00000))
+#define SET_MRX_GRP(_VAL_) (REG32(ADR_MRX_GROUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_GROUP_FRM)) & 0xfff00000))
+#define SET_MRX_FCS_ERR(_VAL_) (REG32(ADR_MRX_FCS_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_ERR)) & 0xffff0000))
+#define SET_MRX_FCS_SUC(_VAL_) (REG32(ADR_MRX_FCS_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_SUCC)) & 0xffff0000))
+#define SET_MRX_MISS(_VAL_) (REG32(ADR_MRX_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MISS)) & 0xffff0000))
+#define SET_MRX_ALC_FAIL(_VAL_) (REG32(ADR_MRX_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ALC_FAIL)) & 0xffff0000))
+#define SET_MRX_DAT_NTF(_VAL_) (REG32(ADR_MRX_DAT_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_NTF)) & 0xffff0000))
+#define SET_MRX_RTS_NTF(_VAL_) (REG32(ADR_MRX_RTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_RTS_NTF)) & 0xffff0000))
+#define SET_MRX_CTS_NTF(_VAL_) (REG32(ADR_MRX_CTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CTS_NTF)) & 0xffff0000))
+#define SET_MRX_ACK_NTF(_VAL_) (REG32(ADR_MRX_ACK_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ACK_NTF)) & 0xffff0000))
+#define SET_MRX_BA_NTF(_VAL_) (REG32(ADR_MRX_BA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_NTF)) & 0xffff0000))
+#define SET_MRX_DATA_NTF(_VAL_) (REG32(ADR_MRX_DATA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DATA_NTF)) & 0xffff0000))
+#define SET_MRX_MNG_NTF(_VAL_) (REG32(ADR_MRX_MNG_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MNG_NTF)) & 0xffff0000))
+#define SET_MRX_DAT_CRC_NTF(_VAL_) (REG32(ADR_MRX_DAT_CRC_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_CRC_NTF)) & 0xffff0000))
+#define SET_MRX_BAR_NTF(_VAL_) (REG32(ADR_MRX_BAR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BAR_NTF)) & 0xffff0000))
+#define SET_MRX_MB_MISS(_VAL_) (REG32(ADR_MRX_MB_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MB_MISS)) & 0xffff0000))
+#define SET_MRX_NIDLE_MISS(_VAL_) (REG32(ADR_MRX_NIDLE_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_NIDLE_MISS)) & 0xffff0000))
+#define SET_MRX_CSR_NTF(_VAL_) (REG32(ADR_MRX_CSR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CSR_NTF)) & 0xffff0000))
+#define SET_DBG_Q0_SUCC(_VAL_) (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q0_FAIL(_VAL_) (REG32(ADR_DBG_Q0_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q0_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q0_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q0_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0xffff0000))
+#define SET_DBG_Q1_SUCC(_VAL_) (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q1_FAIL(_VAL_) (REG32(ADR_DBG_Q1_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q1_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q1_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q1_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0xffff0000))
+#define SET_DBG_Q2_SUCC(_VAL_) (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q2_FAIL(_VAL_) (REG32(ADR_DBG_Q2_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q2_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q2_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q2_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0xffff0000))
+#define SET_DBG_Q3_SUCC(_VAL_) (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q3_FAIL(_VAL_) (REG32(ADR_DBG_Q3_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q3_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q3_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q3_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0xffff0000))
+#define SET_SCRT_TKIP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP0)) & 0xfff00000))
+#define SET_SCRT_TKIP_MIC_ERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP1)) & 0xfff00000))
+#define SET_SCRT_TKIP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_TKIP2)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP2)) & 0xfff00000))
+#define SET_SCRT_CCMP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_CCMP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP0)) & 0xfff00000))
+#define SET_SCRT_CCMP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_CCMP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP1)) & 0xfff00000))
+#define SET_DBG_LEN_CRC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_CRC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0xffff0000))
+#define SET_DBG_LEN_ALC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0xffff0000))
+#define SET_DBG_AMPDU_PASS(_VAL_) (REG32(ADR_DBG_AMPDU_PASS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_PASS)) & 0xffff0000))
+#define SET_DBG_AMPDU_FAIL(_VAL_) (REG32(ADR_DBG_AMPDU_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_FAIL)) & 0xffff0000))
+#define SET_RXID_ALC_CNT_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL1)) & 0xffff0000))
+#define SET_RXID_ALC_LEN_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL2)) & 0xffff0000))
+#define SET_CBR_RG_EN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_TX_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_TX_PA_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_TX_DAC_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_RX_AGC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
+#define SET_CBR_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
+#define SET_CBR_RG_RFG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
+#define SET_CBR_RG_PGAG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
+#define SET_CBR_RG_MODE(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
+#define SET_CBR_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
+#define SET_CBR_RG_EN_SX(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
+#define SET_CBR_RG_EN_RX_LNA(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
+#define SET_CBR_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
+#define SET_CBR_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
+#define SET_CBR_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
+#define SET_CBR_RG_EN_RX_TZ(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
+#define SET_CBR_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
+#define SET_CBR_RG_EN_RX_HPF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
+#define SET_CBR_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
+#define SET_CBR_RG_EN_ADC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
+#define SET_CBR_RG_EN_TX_MOD(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
+#define SET_CBR_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
+#define SET_CBR_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
+#define SET_CBR_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
+#define SET_CBR_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
+#define SET_CBR_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
+#define SET_CBR_RG_EN_TX_DPD(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
+#define SET_CBR_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
+#define SET_CBR_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
+#define SET_CBR_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
+#define SET_CBR_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
+#define SET_CBR_RG_EN_IREF_RX(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
+#define SET_CBR_RG_DCDC_MODE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffefff))
+#define SET_CBR_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffff8))
+#define SET_CBR_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffffffc7))
+#define SET_CBR_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffe3f))
+#define SET_CBR_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffff1ff))
+#define SET_CBR_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffff8fff))
+#define SET_CBR_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffc7fff))
+#define SET_CBR_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffe3ffff))
+#define SET_CBR_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xff1fffff))
+#define SET_CBR_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xf8ffffff))
+#define SET_CBR_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xc7ffffff))
+#define SET_CBR_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffe))
+#define SET_CBR_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffd))
+#define SET_CBR_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffb))
+#define SET_CBR_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffe07))
+#define SET_CBR_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffdff))
+#define SET_CBR_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffbff))
+#define SET_CBR_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffff7ff))
+#define SET_CBR_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffffcfff))
+#define SET_CBR_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffff3fff))
+#define SET_CBR_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffcffff))
+#define SET_CBR_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfff3ffff))
+#define SET_CBR_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffcfffff))
+#define SET_CBR_RG_RX_HPF3M(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffbfffff))
+#define SET_CBR_RG_RX_HPF300K(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xff7fffff))
+#define SET_CBR_RG_RX_HPFI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfcffffff))
+#define SET_CBR_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xf3ffffff))
+#define SET_CBR_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xcfffffff))
+#define SET_CBR_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffffc))
+#define SET_CBR_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffff3))
+#define SET_CBR_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffffcf))
+#define SET_CBR_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffff3f))
+#define SET_CBR_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffcff))
+#define SET_CBR_RG_RX_OUTVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffff3ff))
+#define SET_CBR_RG_RX_TZI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffcfff))
+#define SET_CBR_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffbfff))
+#define SET_CBR_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffe7fff))
+#define SET_CBR_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfff1ffff))
+#define SET_CBR_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffefffff))
+#define SET_CBR_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xff9fffff))
+#define SET_CBR_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfe7fffff))
+#define SET_CBR_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfdffffff))
+#define SET_CBR_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffffffc))
+#define SET_CBR_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffff03))
+#define SET_CBR_RG_TXPGA_STEER(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffc0ff))
+#define SET_CBR_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffff3fff))
+#define SET_CBR_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffcffff))
+#define SET_CBR_RG_PACELL_EN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffe3ffff))
+#define SET_CBR_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfe1fffff))
+#define SET_CBR_RG_PABIAS_AB(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfdffffff))
+#define SET_CBR_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xf3ffffff))
+#define SET_CBR_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xcfffffff))
+#define SET_CBR_RG_RX_SQDC(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffffff8))
+#define SET_CBR_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffffe7))
+#define SET_CBR_RG_RX_LOBUF(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffff9f))
+#define SET_CBR_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffff87f))
+#define SET_CBR_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffff87ff))
+#define SET_CBR_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffc7fff))
+#define SET_CBR_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffe3ffff))
+#define SET_CBR_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffdfffff))
+#define SET_CBR_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xff3fffff))
+#define SET_CBR_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
+#define SET_CBR_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
+#define SET_CBR_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
+#define SET_CBR_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
+#define SET_CBR_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
+#define SET_CBR_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
+#define SET_CBR_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
+#define SET_CBR_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
+#define SET_CBR_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
+#define SET_CBR_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
+#define SET_CBR_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
+#define SET_CBR_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
+#define SET_CBR_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
+#define SET_CBR_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
+#define SET_CBR_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
+#define SET_CBR_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
+#define SET_CBR_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_HPF_T1A(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffffe7))
+#define SET_CBR_RG_HPF_T1B(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffff9f))
+#define SET_CBR_RG_HPF_T1C(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffe7f))
+#define SET_CBR_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffff9ff))
+#define SET_CBR_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffe7ff))
+#define SET_CBR_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff9))
+#define SET_CBR_RG_ADC_DIVR(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_ADC_DVCMI(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffffffcf))
+#define SET_CBR_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffc3f))
+#define SET_CBR_RG_ADC_STNBY(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffbff))
+#define SET_CBR_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffff7ff))
+#define SET_CBR_RG_ADC_TSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffff0fff))
+#define SET_CBR_RG_ADC_VRSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffcffff))
+#define SET_CBR_RG_DICMP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfff3ffff))
+#define SET_CBR_RG_DIOP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffcfffff))
+#define SET_CBR_RG_DACI1ST(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffffc))
+#define SET_CBR_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffff3))
+#define SET_CBR_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffffcf))
+#define SET_CBR_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffff3f))
+#define SET_CBR_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffff9ff))
+#define SET_CBR_RG_TX_DAC_OS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffc7ff))
+#define SET_CBR_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffff3fff))
+#define SET_CBR_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfff0ffff))
+#define SET_CBR_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffefffff))
+#define SET_CBR_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffdfffff))
+#define SET_CBR_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffbfffff))
+#define SET_CBR_RG_EN_SX_R3(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_EN_SX_CH(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_EN_SX_CHP(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffef))
+#define SET_CBR_RG_EN_SX_VCO(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffdf))
+#define SET_CBR_RG_EN_SX_MOD(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffbf))
+#define SET_CBR_RG_EN_SX_LCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffff7f))
+#define SET_CBR_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_EN_SX_DELCAL(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_EN_SX_PC_BYPASS(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffbff))
+#define SET_CBR_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffff7ff))
+#define SET_CBR_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffefff))
+#define SET_CBR_RG_EN_SX_DIV(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffdfff))
+#define SET_CBR_RG_EN_SX_LPF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffbfff))
+#define SET_CBR_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xff000000))
+#define SET_CBR_RG_SX_SEL_CP(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0ffffff))
+#define SET_CBR_RG_SX_SEL_CS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0fffffff))
+#define SET_CBR_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfffff800))
+#define SET_CBR_RG_SX_SEL_C3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xffff87ff))
+#define SET_CBR_RG_SX_SEL_RS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfff07fff))
+#define SET_CBR_RG_SX_SEL_R3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfe0fffff))
+#define SET_CBR_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffffe0))
+#define SET_CBR_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffffc1f))
+#define SET_CBR_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffc3ff))
+#define SET_CBR_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffc3fff))
+#define SET_CBR_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffbffff))
+#define SET_CBR_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffc7ffff))
+#define SET_CBR_RG_SX_PFDSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffbfffff))
+#define SET_CBR_RG_SX_PFD_SET(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xff7fffff))
+#define SET_CBR_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfeffffff))
+#define SET_CBR_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfdffffff))
+#define SET_CBR_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfbffffff))
+#define SET_CBR_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xf7ffffff))
+#define SET_CBR_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xefffffff))
+#define SET_CBR_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xdfffffff))
+#define SET_CBR_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xbfffffff))
+#define SET_CBR_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffffff8))
+#define SET_CBR_RG_SX_VCORSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffffff07))
+#define SET_CBR_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffff0ff))
+#define SET_CBR_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffff0fff))
+#define SET_CBR_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfff0ffff))
+#define SET_CBR_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xff0fffff))
+#define SET_CBR_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0ffffff))
+#define SET_CBR_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0fffffff))
+#define SET_CBR_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
+#define SET_CBR_RG_SX_MOD_ERRCMP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffff3))
+#define SET_CBR_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
+#define SET_CBR_RG_SX_SDM_D1(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffbf))
+#define SET_CBR_RG_SX_SDM_D2(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffff7f))
+#define SET_CBR_RG_SDM_PASS(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffeff))
+#define SET_CBR_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
+#define SET_CBR_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
+#define SET_CBR_RG_SX_XO_GM(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
+#define SET_CBR_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
+#define SET_CBR_RG_SX_XO_SWCAP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffc3fff))
+#define SET_CBR_RG_SX_SDMLUT_INV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffbffff))
+#define SET_CBR_RG_SX_LCKEN(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
+#define SET_CBR_RG_SX_PREVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
+#define SET_CBR_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
+#define SET_CBR_RG_SX_MOD_ERR_DELAY(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xcfffffff))
+#define SET_CBR_RG_SX_MODDB(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xbfffffff))
+#define SET_CBR_RG_SX_CV_CURVE_SEL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffffffc))
+#define SET_CBR_RG_SX_SEL_DELAY(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffff83))
+#define SET_CBR_RG_SX_REF_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff87f))
+#define SET_CBR_RG_SX_VCOBY16(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff7ff))
+#define SET_CBR_RG_SX_VCOBY32(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffefff))
+#define SET_CBR_RG_SX_PH(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffdfff))
+#define SET_CBR_RG_SX_PL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffbfff))
+#define SET_CBR_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffffe))
+#define SET_CBR_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffff9))
+#define SET_CBR_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffe7))
+#define SET_CBR_RG_SX_VT_SET(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffdf))
+#define SET_CBR_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffff803f))
+#define SET_CBR_RG_IDEAL_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xf0007fff))
+#define SET_CBR_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffff9))
+#define SET_CBR_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffffe7))
+#define SET_CBR_RG_DP_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffc01f))
+#define SET_CBR_RG_DP_CK320BY2(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffbfff))
+#define SET_CBR_RG_SX_DELCTRL(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffe07fff))
+#define SET_CBR_RG_DP_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffdfffff))
+#define SET_CBR_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
+#define SET_CBR_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
+#define SET_CBR_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
+#define SET_CBR_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
+#define SET_CBR_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
+#define SET_CBR_RG_DP_RP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
+#define SET_CBR_RG_DP_RHP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
+#define SET_CBR_RG_DP_DR3(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xff8fffff))
+#define SET_CBR_RG_DP_DCP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xf87fffff))
+#define SET_CBR_RG_DP_DCS(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x87ffffff))
+#define SET_CBR_RG_DP_FBDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xfffff000))
+#define SET_CBR_RG_DP_FODIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00fff))
+#define SET_CBR_RG_DP_REFDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003fffff))
+#define SET_CBR_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
+#define SET_CBR_RG_EN_RCAL(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_RCAL_SPD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_RCAL_TMR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffe03))
+#define SET_CBR_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xffff83ff))
+#define SET_CBR_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffffff01))
+#define SET_CBR_RG_DP_BBPLL_BS_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_DP_BBPLL_BS_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffff81ff))
+#define SET_CBR_RCAL_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
+#define SET_CBR_DA_LCK_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
+#define SET_CBR_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
+#define SET_CBR_DP_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffff7))
+#define SET_CBR_CH_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffffef))
+#define SET_CBR_DA_R_CODE_LUT(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
+#define SET_CBR_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
+#define SET_CBR_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
+#define SET_CBR_DA_R_CAL_CODE(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
+#define SET_CBR_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
+#define SET_CBR_DA_DP_BBPLL_BS(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffc0fff))
+#define SET_CBR_TX_EN(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffe))
+#define SET_CBR_TX_CNT_RST(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffd))
+#define SET_CBR_IFS_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xffffff03))
+#define SET_CBR_LENGTH_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfff000ff))
+#define SET_CBR_TX_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00ffffff))
+#define SET_CBR_TC_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0xff000000))
+#define SET_CBR_PLCP_PSDU_DATA_MEM(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffffff00))
+#define SET_CBR_PLCP_PSDU_PREAMBLE_SHORT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xfffffeff))
+#define SET_CBR_PLCP_BYTE_LENGTH(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffe001ff))
+#define SET_CBR_PLCP_PSDU_RATE(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xff9fffff))
+#define SET_CBR_TAIL_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xe07fffff))
+#define SET_CBR_RG_O_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffe))
+#define SET_CBR_RG_I_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffd))
+#define SET_CBR_SEL_ADCKP_INV(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffb))
+#define SET_CBR_RG_PAD_DS(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffff7))
+#define SET_CBR_SEL_ADCKP_MUX(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffef))
+#define SET_CBR_RG_PAD_DS_CLK(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffdf))
+#define SET_CBR_INTP_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffdff))
+#define SET_CBR_IQ_SWP(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffbff))
+#define SET_CBR_RG_EN_EXT_DA(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffff7ff))
+#define SET_CBR_RG_DIS_DA_OFFSET(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffefff))
+#define SET_CBR_DBG_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfff0ffff))
+#define SET_CBR_DBG_EN(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffefffff))
+#define SET_CBR_RG_PKT_GEN_TX_CNT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0x00000000))
+#define SET_CBR_TP_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffe0))
+#define SET_CBR_IDEAL_IQ_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffdf))
+#define SET_CBR_DATA_OUT_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffe3f))
+#define SET_CBR_TWO_TONE_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffdff))
+#define SET_CBR_FREQ_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xff00ffff))
+#define SET_CBR_IQ_SCALE(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ffffff))
+#define SET_CPU_QUE_POP(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 0) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffe))
+#define SET_CPU_INT(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 2) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffb))
+#define SET_CPU_ID_TB0(_VAL_) (REG32(ADR_CPU_ID_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB0)) & 0x00000000))
+#define SET_CPU_ID_TB1(_VAL_) (REG32(ADR_CPU_ID_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB1)) & 0x00000000))
+#define SET_HW_PKTID(_VAL_) (REG32(ADR_CH0_TRIG_1)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_1)) & 0xfffff800))
+#define SET_CH0_INT_ADDR(_VAL_) (REG32(ADR_CH0_TRIG_0)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_0)) & 0x00000000))
+#define SET_PRI_HW_PKTID(_VAL_) (REG32(ADR_CH0_PRI_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_PRI_TRIG)) & 0xfffff800))
+#define SET_CH0_FULL(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffe))
+#define SET_FF0_EMPTY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffd))
+#define SET_RLS_BUSY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_STATUS)) & 0xfffffdff))
+#define SET_RLS_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MCU_STATUS)) & 0xfffffbff))
+#define SET_RTN_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MCU_STATUS)) & 0xfffff7ff))
+#define SET_RLS_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MCU_STATUS)) & 0xff00ffff))
+#define SET_RTN_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MCU_STATUS)) & 0x00ffffff))
+#define SET_FF0_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffffe0))
+#define SET_FF1_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfffffe1f))
+#define SET_FF3_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffc7ff))
+#define SET_FF5_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 17) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfff1ffff))
+#define SET_FF6_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xff8fffff))
+#define SET_FF7_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 23) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfc7fffff))
+#define SET_FF8_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 26) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xe3ffffff))
+#define SET_FF9_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 29) | ((REG32(ADR_RD_IN_FFCNT1)) & 0x1fffffff))
+#define SET_FF10_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffff8))
+#define SET_FF11_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 3) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffffc7))
+#define SET_FF12_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 6) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffe3f))
+#define SET_FF13_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 9) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffff9ff))
+#define SET_FF14_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffe7ff))
+#define SET_FF15_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 13) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffff9fff))
+#define SET_FF4_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfff07fff))
+#define SET_FF2_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xff8fffff))
+#define SET_CH1_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffd))
+#define SET_CH2_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffb))
+#define SET_CH3_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffff7))
+#define SET_CH4_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffef))
+#define SET_CH5_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffdf))
+#define SET_CH6_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffbf))
+#define SET_CH7_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffff7f))
+#define SET_CH8_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffeff))
+#define SET_CH9_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffdff))
+#define SET_CH10_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffbff))
+#define SET_CH11_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffff7ff))
+#define SET_CH12_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffefff))
+#define SET_CH13_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffdfff))
+#define SET_CH14_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffbfff))
+#define SET_CH15_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffff7fff))
+#define SET_HALT_CH0(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffe))
+#define SET_HALT_CH1(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffd))
+#define SET_HALT_CH2(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffb))
+#define SET_HALT_CH3(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 3) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffff7))
+#define SET_HALT_CH4(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffef))
+#define SET_HALT_CH5(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffdf))
+#define SET_HALT_CH6(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffbf))
+#define SET_HALT_CH7(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffff7f))
+#define SET_HALT_CH8(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffeff))
+#define SET_HALT_CH9(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 9) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffdff))
+#define SET_HALT_CH10(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 10) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffbff))
+#define SET_HALT_CH11(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 11) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffff7ff))
+#define SET_HALT_CH12(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 12) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffefff))
+#define SET_HALT_CH13(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 13) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffdfff))
+#define SET_HALT_CH14(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 14) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffbfff))
+#define SET_HALT_CH15(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 15) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffff7fff))
+#define SET_STOP_MBOX(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffeffff))
+#define SET_MB_ERR_AUTO_HALT_EN(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 20) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffefffff))
+#define SET_MB_EXCEPT_CLR(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 21) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffdfffff))
+#define SET_MB_EXCEPT_CASE(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 24) | ((REG32(ADR_MBOX_HALT_CFG)) & 0x00ffffff))
+#define SET_MB_DBG_TIME_STEP(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG1)) & 0xffff0000))
+#define SET_DBG_TYPE(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffcffff))
+#define SET_MB_DBG_CLR(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffbffff))
+#define SET_DBG_ALC_LOG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfff7ffff))
+#define SET_MB_DBG_COUNTER_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfeffffff))
+#define SET_MB_DBG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG1)) & 0x7fffffff))
+#define SET_MB_DBG_RECORD_CNT(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000))
+#define SET_MB_DBG_LENGTH(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff))
+#define SET_MB_DBG_CFG_ADDR(_VAL_) (REG32(ADR_MB_DBG_CFG3)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG3)) & 0x00000000))
+#define SET_DBG_HWID0_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffe))
+#define SET_DBG_HWID1_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 1) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffd))
+#define SET_DBG_HWID2_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 2) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffb))
+#define SET_DBG_HWID3_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 3) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffff7))
+#define SET_DBG_HWID4_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 4) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffef))
+#define SET_DBG_HWID5_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 5) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffdf))
+#define SET_DBG_HWID6_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 6) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffbf))
+#define SET_DBG_HWID7_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 7) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffff7f))
+#define SET_DBG_HWID8_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 8) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffeff))
+#define SET_DBG_HWID9_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 9) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffdff))
+#define SET_DBG_HWID10_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 10) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffbff))
+#define SET_DBG_HWID11_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 11) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffff7ff))
+#define SET_DBG_HWID12_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 12) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffefff))
+#define SET_DBG_HWID13_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 13) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffdfff))
+#define SET_DBG_HWID14_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 14) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffbfff))
+#define SET_DBG_HWID15_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 15) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffff7fff))
+#define SET_DBG_HWID0_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffeffff))
+#define SET_DBG_HWID1_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 17) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffdffff))
+#define SET_DBG_HWID2_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffbffff))
+#define SET_DBG_HWID3_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfff7ffff))
+#define SET_DBG_HWID4_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 20) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffefffff))
+#define SET_DBG_HWID5_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 21) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffdfffff))
+#define SET_DBG_HWID6_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 22) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffbfffff))
+#define SET_DBG_HWID7_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 23) | ((REG32(ADR_MB_DBG_CFG4)) & 0xff7fffff))
+#define SET_DBG_HWID8_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfeffffff))
+#define SET_DBG_HWID9_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 25) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfdffffff))
+#define SET_DBG_HWID10_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 26) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfbffffff))
+#define SET_DBG_HWID11_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 27) | ((REG32(ADR_MB_DBG_CFG4)) & 0xf7ffffff))
+#define SET_DBG_HWID12_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 28) | ((REG32(ADR_MB_DBG_CFG4)) & 0xefffffff))
+#define SET_DBG_HWID13_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 29) | ((REG32(ADR_MB_DBG_CFG4)) & 0xdfffffff))
+#define SET_DBG_HWID14_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 30) | ((REG32(ADR_MB_DBG_CFG4)) & 0xbfffffff))
+#define SET_DBG_HWID15_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG4)) & 0x7fffffff))
+#define SET_MB_OUT_QUEUE_EN(_VAL_) (REG32(ADR_MB_OUT_QUEUE_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0xfffffffd))
+#define SET_CH0_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffe))
+#define SET_CH1_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffd))
+#define SET_CH2_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffb))
+#define SET_CH3_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffff7))
+#define SET_CH4_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffef))
+#define SET_CH5_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffdf))
+#define SET_CH6_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffbf))
+#define SET_CH7_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffff7f))
+#define SET_CH8_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffeff))
+#define SET_CH9_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffdff))
+#define SET_CH10_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffbff))
+#define SET_CH11_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffff7ff))
+#define SET_CH12_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffefff))
+#define SET_CH13_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffdfff))
+#define SET_CH14_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffbfff))
+#define SET_CH15_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 15) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffff7fff))
+#define SET_FFO0_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffffffe0))
+#define SET_FFO1_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffffc1f))
+#define SET_FFO2_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffff3ff))
+#define SET_FFO3_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfff07fff))
+#define SET_FFO4_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffcfffff))
+#define SET_FFO5_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xf1ffffff))
+#define SET_FFO6_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffff0))
+#define SET_FFO7_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffc1f))
+#define SET_FFO8_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xffff83ff))
+#define SET_FFO9_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfff07fff))
+#define SET_FFO10_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xff0fffff))
+#define SET_FFO11_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xc1ffffff))
+#define SET_FFO12_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffffff8))
+#define SET_FFO13_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffffff9f))
+#define SET_FFO14_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffff3ff))
+#define SET_FFO15_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffe07fff))
+#define SET_CH0_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffe))
+#define SET_CH1_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffd))
+#define SET_CH2_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffb))
+#define SET_CH3_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffff7))
+#define SET_CH4_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffef))
+#define SET_CH5_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffdf))
+#define SET_CH6_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffbf))
+#define SET_CH7_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffff7f))
+#define SET_CH8_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffeff))
+#define SET_CH9_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffdff))
+#define SET_CH10_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffbff))
+#define SET_CH11_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffff7ff))
+#define SET_CH12_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffefff))
+#define SET_CH13_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffdfff))
+#define SET_CH14_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffbfff))
+#define SET_CH15_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffff7fff))
+#define SET_CH0_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffe))
+#define SET_CH1_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 1) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffd))
+#define SET_CH2_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 2) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffb))
+#define SET_CH3_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 3) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffff7))
+#define SET_CH4_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 4) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffef))
+#define SET_CH5_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 5) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffdf))
+#define SET_CH6_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 6) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffbf))
+#define SET_CH7_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 7) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffff7f))
+#define SET_CH8_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffeff))
+#define SET_CH9_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 9) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffdff))
+#define SET_CH10_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 10) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffbff))
+#define SET_CH11_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 11) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffff7ff))
+#define SET_CH12_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 12) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffefff))
+#define SET_CH13_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 13) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffdfff))
+#define SET_CH14_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 14) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffbfff))
+#define SET_CH15_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 15) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffff7fff))
+#define SET_MB_LOW_THOLD_EN(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 31) | ((REG32(ADR_MB_THRESHOLD6)) & 0x7fffffff))
+#define SET_CH0_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffffe0))
+#define SET_CH1_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffe0ff))
+#define SET_CH2_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffe0ffff))
+#define SET_CH3_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD7)) & 0xe0ffffff))
+#define SET_CH4_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffffe0))
+#define SET_CH5_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffe0ff))
+#define SET_CH6_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffe0ffff))
+#define SET_CH7_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD8)) & 0xe0ffffff))
+#define SET_CH8_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffffe0))
+#define SET_CH9_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffe0ff))
+#define SET_CH10_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffe0ffff))
+#define SET_CH11_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD9)) & 0xe0ffffff))
+#define SET_CH12_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffffe0))
+#define SET_CH13_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffe0ff))
+#define SET_CH14_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffe0ffff))
+#define SET_CH15_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD10)) & 0xe0ffffff))
+#define SET_TRASH_TIMEOUT_EN(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffe))
+#define SET_TRASH_CAN_INT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffd))
+#define SET_TRASH_INT_ID(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffff80f))
+#define SET_TRASH_TIMEOUT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfc00ffff))
+#define SET_CH0_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffe))
+#define SET_CH1_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffd))
+#define SET_CH2_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffb))
+#define SET_CH3_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffff7))
+#define SET_CH4_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffef))
+#define SET_CH5_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffdf))
+#define SET_CH6_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffbf))
+#define SET_CH7_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffff7f))
+#define SET_CH8_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffeff))
+#define SET_CH9_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffdff))
+#define SET_CH10_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffbff))
+#define SET_CH11_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffff7ff))
+#define SET_CH12_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffefff))
+#define SET_CH13_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffdfff))
+#define SET_CH14_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffbfff))
+#define SET_CPU_ID_TB2(_VAL_) (REG32(ADR_CPU_ID_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB2)) & 0x00000000))
+#define SET_CPU_ID_TB3(_VAL_) (REG32(ADR_CPU_ID_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB3)) & 0x00000000))
+#define SET_IQ_LOG_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0xfffffffe))
+#define SET_IQ_LOG_STOP_MODE(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xfffffffe))
+#define SET_GPIO_STOP_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffef))
+#define SET_GPIO_STOP_POL(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffdf))
+#define SET_IQ_LOG_TIMER(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x0000ffff))
+#define SET_IQ_LOG_LEN(_VAL_) (REG32(ADR_PHY_IQ_LOG_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_LEN)) & 0xffff0000))
+#define SET_IQ_LOG_TAIL_ADR(_VAL_) (REG32(ADR_PHY_IQ_LOG_PTR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_PTR)) & 0xffff0000))
+#define SET_ALC_LENG(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 0) | ((REG32(ADR_WR_ALC)) & 0xfffc0000))
+#define SET_CH0_DYN_PRI(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 20) | ((REG32(ADR_WR_ALC)) & 0xffcfffff))
+#define SET_MCU_PKTID(_VAL_) (REG32(ADR_GETID)) = (((_VAL_) << 0) | ((REG32(ADR_GETID)) & 0x00000000))
+#define SET_CH0_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffffc))
+#define SET_CH1_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_STA_PRI)) & 0xffffffcf))
+#define SET_CH2_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffcff))
+#define SET_CH3_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_STA_PRI)) & 0xffffcfff))
+#define SET_ID_TB0(_VAL_) (REG32(ADR_RD_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID0)) & 0x00000000))
+#define SET_ID_TB1(_VAL_) (REG32(ADR_RD_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID1)) & 0x00000000))
+#define SET_ID_MNG_HALT(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_CFG)) & 0xffffffef))
+#define SET_ID_MNG_ERR_HALT_EN(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_CFG)) & 0xffffffdf))
+#define SET_ID_EXCEPT_FLG_CLR(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_CFG)) & 0xffffffbf))
+#define SET_ID_EXCEPT_FLG(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_CFG)) & 0xffffff7f))
+#define SET_ID_FULL(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 0) | ((REG32(ADR_IMD_STA)) & 0xfffffffe))
+#define SET_ID_MNG_BUSY(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 1) | ((REG32(ADR_IMD_STA)) & 0xfffffffd))
+#define SET_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 2) | ((REG32(ADR_IMD_STA)) & 0xfffffffb))
+#define SET_CH0_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_STA)) & 0xffffffef))
+#define SET_CH1_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_STA)) & 0xffffffdf))
+#define SET_CH2_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_STA)) & 0xffffffbf))
+#define SET_CH3_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_STA)) & 0xffffff7f))
+#define SET_REQ_LOCK_INT_EN(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 8) | ((REG32(ADR_IMD_STA)) & 0xfffffeff))
+#define SET_REQ_LOCK_INT(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 9) | ((REG32(ADR_IMD_STA)) & 0xfffffdff))
+#define SET_MCU_ALC_READY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_STA)) & 0xfffffffe))
+#define SET_ALC_FAIL(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 1) | ((REG32(ADR_ALC_STA)) & 0xfffffffd))
+#define SET_ALC_BUSY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 2) | ((REG32(ADR_ALC_STA)) & 0xfffffffb))
+#define SET_CH0_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 4) | ((REG32(ADR_ALC_STA)) & 0xffffffef))
+#define SET_CH1_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 5) | ((REG32(ADR_ALC_STA)) & 0xffffffdf))
+#define SET_CH2_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 6) | ((REG32(ADR_ALC_STA)) & 0xffffffbf))
+#define SET_CH3_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 7) | ((REG32(ADR_ALC_STA)) & 0xffffff7f))
+#define SET_ALC_INT_ID(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_STA)) & 0xffff80ff))
+#define SET_ALC_TIMEOUT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_STA)) & 0xfc00ffff))
+#define SET_ALC_TIMEOUT_INT_EN(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 30) | ((REG32(ADR_ALC_STA)) & 0xbfffffff))
+#define SET_ALC_TIMEOUT_INT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_STA)) & 0x7fffffff))
+#define SET_TX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffffff00))
+#define SET_RX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffff00ff))
+#define SET_TX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffffff00))
+#define SET_RX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffff00ff))
+#define SET_ID_THOLD_RX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfffeffff))
+#define SET_RX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 17) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfff1ffff))
+#define SET_ID_THOLD_TX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 20) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffefffff))
+#define SET_TX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 21) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xff1fffff))
+#define SET_ID_THOLD_INT_EN(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfeffffff))
+#define SET_TX_ID_TB0(_VAL_) (REG32(ADR_TX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID0)) & 0x00000000))
+#define SET_TX_ID_TB1(_VAL_) (REG32(ADR_TX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID1)) & 0x00000000))
+#define SET_RX_ID_TB0(_VAL_) (REG32(ADR_RX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID0)) & 0x00000000))
+#define SET_RX_ID_TB1(_VAL_) (REG32(ADR_RX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID1)) & 0x00000000))
+#define SET_DOUBLE_RLS_INT_EN(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 0) | ((REG32(ADR_RTN_STA)) & 0xfffffffe))
+#define SET_ID_DOUBLE_RLS_INT(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 1) | ((REG32(ADR_RTN_STA)) & 0xfffffffd))
+#define SET_DOUBLE_RLS_ID(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 8) | ((REG32(ADR_RTN_STA)) & 0xffff80ff))
+#define SET_ID_LEN_THOLD_INT_EN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffe))
+#define SET_ALL_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 1) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffd))
+#define SET_TX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 2) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffb))
+#define SET_RX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 3) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffff7))
+#define SET_ID_TX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 4) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffffe00f))
+#define SET_ID_RX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 13) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffc01fff))
+#define SET_ID_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 22) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x803fffff))
+#define SET_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffffe00))
+#define SET_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 9) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffc01ff))
+#define SET_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 18) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xf803ffff))
+#define SET_CH_ARB_EN(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffffe))
+#define SET_CH_PRI1(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffffcf))
+#define SET_CH_PRI2(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffcff))
+#define SET_CH_PRI3(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffcfff))
+#define SET_CH_PRI4(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 16) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffcffff))
+#define SET_TX_ID_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xffffff80))
+#define SET_TX_PAGE_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xfffe00ff))
+#define SET_ID_PAGE_MAX_SIZE(_VAL_) (REG32(ADR_ID_INFO_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ID_INFO_STA)) & 0xfffffe00))
+#define SET_TX_PAGE_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xfffffe00))
+#define SET_TX_COUNT_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xff00ffff))
+#define SET_TX_LIMIT_INT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 30) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xbfffffff))
+#define SET_TX_LIMIT_INT_EN(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 31) | ((REG32(ADR_TX_LIMIT_INTR)) & 0x7fffffff))
+#define SET_TX_PAGE_USE_7_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffff00))
+#define SET_TX_ID_USE_5_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffc0ff))
+#define SET_EDCA0_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 14) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xfffc3fff))
+#define SET_EDCA1_FFO_CNT_3_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 18) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffc3ffff))
+#define SET_EDCA2_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xf83fffff))
+#define SET_EDCA3_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 27) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0x07ffffff))
+#define SET_ID_TB2(_VAL_) (REG32(ADR_RD_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID2)) & 0x00000000))
+#define SET_ID_TB3(_VAL_) (REG32(ADR_RD_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID3)) & 0x00000000))
+#define SET_TX_ID_TB2(_VAL_) (REG32(ADR_TX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID2)) & 0x00000000))
+#define SET_TX_ID_TB3(_VAL_) (REG32(ADR_TX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID3)) & 0x00000000))
+#define SET_RX_ID_TB2(_VAL_) (REG32(ADR_RX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID2)) & 0x00000000))
+#define SET_RX_ID_TB3(_VAL_) (REG32(ADR_RX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID3)) & 0x00000000))
+#define SET_TX_PAGE_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffffe00))
+#define SET_TX_ID_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffe01ff))
+#define SET_EDCA4_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xffe1ffff))
+#define SET_TX_PAGE_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffffe00))
+#define SET_TX_ID_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffe01ff))
+#define SET_EDCA1_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 21) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfc1fffff))
+#define SET_EDCA4_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 26) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xc3ffffff))
+#define SET_TX_PAGE_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffffe00))
+#define SET_TX_ID_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffe01ff))
+#define SET_EDCA2_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xffc1ffff))
+#define SET_EDCA3_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xf83fffff))
+#define SET_TX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfffffe00))
+#define SET_RX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfe00ffff))
+#define SET_MAX_ALL_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INFO)) & 0xffffff00))
+#define SET_MAX_TX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_ID_INFO)) & 0xffff00ff))
+#define SET_MAX_RX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_ID_INFO)) & 0xff00ffff))
+#define SET_MAX_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffffe00))
+#define SET_MAX_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 9) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffc01ff))
+#define SET_MAX_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 18) | ((REG32(ADR_ALC_ID_INF1)) & 0xf803ffff))
+#define SET_RG_PMDLBK(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_0)) & 0xfffffffe))
+#define SET_RG_RDYACK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff9))
+#define SET_RG_ADEDGE_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff7))
+#define SET_RG_SIGN_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_0)) & 0xffffffef))
+#define SET_RG_IQ_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_0)) & 0xffffffdf))
+#define SET_RG_Q_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_0)) & 0xffffffbf))
+#define SET_RG_I_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_EN_0)) & 0xffffff7f))
+#define SET_RG_BYPASS_ACI(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_0)) & 0xfffffeff))
+#define SET_RG_LBK_ANA_PATH(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_EN_0)) & 0xfffffdff))
+#define SET_RG_SPECTRUM_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_EN_0)) & 0xfffff3ff))
+#define SET_RG_SPECTRUM_BW(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_0)) & 0xffffcfff))
+#define SET_RG_SPECTRUM_FREQ_MANUAL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_0)) & 0xffffbfff))
+#define SET_RG_SPECTRUM_EN(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_0)) & 0xffff7fff))
+#define SET_RG_TXPWRLVL_SET(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_0)) & 0xff00ffff))
+#define SET_RG_TXPWRLVL_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_EN_0)) & 0xfeffffff))
+#define SET_RG_RF_BB_CLK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_EN_0)) & 0x7fffffff))
+#define SET_RG_PHY_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffe))
+#define SET_RG_PHYRX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffd))
+#define SET_RG_PHYTX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffb))
+#define SET_RG_PHY11GN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_1)) & 0xfffffff7))
+#define SET_RG_PHY11B_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_1)) & 0xffffffef))
+#define SET_RG_PHYRXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_1)) & 0xffffffdf))
+#define SET_RG_PHYTXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_1)) & 0xffffffbf))
+#define SET_RG_PHY11BGN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_1)) & 0xfffffeff))
+#define SET_RG_FORCE_11GN_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_1)) & 0xffffefff))
+#define SET_RG_FORCE_11B_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 13) | ((REG32(ADR_PHY_EN_1)) & 0xffffdfff))
+#define SET_RG_FFT_MEM_CLK_EN_RX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_1)) & 0xffffbfff))
+#define SET_RG_FFT_MEM_CLK_EN_TX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_1)) & 0xffff7fff))
+#define SET_RG_PHY_IQ_TRIG_SEL(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_1)) & 0xfff0ffff))
+#define SET_RG_SPECTRUM_FREQ(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_EN_1)) & 0xc00fffff))
+#define SET_SVN_VERSION(_VAL_) (REG32(ADR_SVN_VERSION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SVN_VERSION_REG)) & 0x00000000))
+#define SET_RG_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffff0000))
+#define SET_RG_PKT_MODE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xfff8ffff))
+#define SET_RG_CH_BW(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 19) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffc7ffff))
+#define SET_RG_PRM(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 22) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffbfffff))
+#define SET_RG_SHORTGI(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xff7fffff))
+#define SET_RG_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0x80ffffff))
+#define SET_RG_L_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xfffff000))
+#define SET_RG_L_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff8fff))
+#define SET_RG_SERVICE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0x0000ffff))
+#define SET_RG_SMOOTHING(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffe))
+#define SET_RG_NO_SOUND(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffd))
+#define SET_RG_AGGREGATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffb))
+#define SET_RG_STBC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffe7))
+#define SET_RG_FEC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffdf))
+#define SET_RG_N_ESS(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffff3f))
+#define SET_RG_TXPWRLVL(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffff00ff))
+#define SET_RG_TX_START(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffffe))
+#define SET_RG_IFS_TIME(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xffffff03))
+#define SET_RG_CONTINUOUS_DATA(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffeff))
+#define SET_RG_DATA_SEL(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffff9ff))
+#define SET_RG_TX_D(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xff00ffff))
+#define SET_RG_TX_CNT_TARGET(_VAL_) (REG32(ADR_PHY_PKT_GEN_4)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_4)) & 0x00000000))
+#define SET_RG_FFT_IFFT_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_REG_00)) & 0xffffff3f))
+#define SET_RG_DAC_DBG_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_00)) & 0xfffffeff))
+#define SET_RG_DAC_SGN_SWAP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_REG_00)) & 0xfffffdff))
+#define SET_RG_TXD_SEL(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_REG_00)) & 0xfffff3ff))
+#define SET_RG_UP8X(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_00)) & 0xff00ffff))
+#define SET_RG_IQ_DC_BYP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_00)) & 0xfeffffff))
+#define SET_RG_IQ_DC_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_00)) & 0xcfffffff))
+#define SET_RG_DAC_DCEN(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_01)) & 0xfffffffe))
+#define SET_RG_DAC_DCQ(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_01)) & 0xffffc00f))
+#define SET_RG_DAC_DCI(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_01)) & 0xfc00ffff))
+#define SET_RG_PGA_REFDB_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffffff80))
+#define SET_RG_PGA_REFDB_TOP(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffff80ff))
+#define SET_RG_PGA_REF_UND(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xfc00ffff))
+#define SET_RG_RF_REF_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_02_AGC)) & 0x0fffffff))
+#define SET_RG_PGAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xfffffff0))
+#define SET_RG_PGAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffffef))
+#define SET_RG_RFGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff9f))
+#define SET_RG_RFGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff7f))
+#define SET_RG_WAIT_T_RXAGC(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffc0ff))
+#define SET_RG_RXAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffbfff))
+#define SET_RG_RXAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffff7fff))
+#define SET_RG_WAIT_T_FINAL(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffc0ffff))
+#define SET_RG_WAIT_T(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xc0ffffff))
+#define SET_RG_ULG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffffff0))
+#define SET_RG_LG_PGA_UND_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffffff0f))
+#define SET_RG_LG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffff0ff))
+#define SET_RG_LG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffff0fff))
+#define SET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfff0ffff))
+#define SET_RG_HG_PGA_SAT2_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xff0fffff))
+#define SET_RG_HG_PGA_SAT1_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xf0ffffff))
+#define SET_RG_HG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_04_AGC)) & 0x0fffffff))
+#define SET_RG_MG_PGA_JB_TH(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xfffffff0))
+#define SET_RG_MA_PGA_LOW_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xffe0ffff))
+#define SET_RG_WR_RFGC_INIT_SET(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 21) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff9fffff))
+#define SET_RG_WR_RFGC_INIT_EN(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff7fffff))
+#define SET_RG_MA_PGA_HIGH_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xe0ffffff))
+#define SET_RG_AGC_THRESHOLD(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xffffc000))
+#define SET_RG_ACI_POINT_CNT_LMT_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xff80ffff))
+#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xfcffffff))
+#define SET_RG_WR_ACI_GAIN_INI_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffffff00))
+#define SET_RG_WR_ACI_GAIN_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffff00ff))
+#define SET_RG_ACI_DAGC_SET_VALUE_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xff80ffff))
+#define SET_RG_WR_ACI_GAIN_OW_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x7fffffff))
+#define SET_RG_ACI_POINT_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xffffff00))
+#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xfffffcff))
+#define SET_RG_ACI_DAGC_DONE_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00ffffff))
+#define SET_RG_ACI_DAGC_SET_VALUE_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffffff80))
+#define SET_RG_ACI_GAIN_INI_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffff00ff))
+#define SET_RG_ACI_GAIN_OW_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xff00ffff))
+#define SET_RG_ACI_GAIN_OW_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x7fffffff))
+#define SET_RO_CCA_PWR_MA_11GN(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffffff80))
+#define SET_RO_ED_STATE(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffff7fff))
+#define SET_RO_CCA_PWR_MA_11B(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xff80ffff))
+#define SET_RO_PGA_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xffffc000))
+#define SET_RO_RF_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xfff0ffff))
+#define SET_RO_PGAGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xf0ffffff))
+#define SET_RO_RFGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xcfffffff))
+#define SET_RO_PGA_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xffffc000))
+#define SET_RO_RF_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xfff0ffff))
+#define SET_RO_PGAGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xf0ffffff))
+#define SET_RO_RFGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xcfffffff))
+#define SET_RO_PGA_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xffffc000))
+#define SET_RO_RF_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xfff0ffff))
+#define SET_RO_PGAGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xf0ffffff))
+#define SET_RO_RFGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xcfffffff))
+#define SET_RG_TX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffffe0))
+#define SET_RG_TX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffe0ff))
+#define SET_RG_TX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffe0ffff))
+#define SET_RG_TX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xe0ffffff))
+#define SET_RG_TX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffffe0))
+#define SET_RG_TX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffe0ff))
+#define SET_RG_TX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffe0ffff))
+#define SET_RG_TX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xe0ffffff))
+#define SET_RG_TX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffffe))
+#define SET_RG_TX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffffef))
+#define SET_RG_TX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffeff))
+#define SET_RG_TX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffefff))
+#define SET_RG_TX_DES_PWRLVL(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffe0ffff))
+#define SET_RG_TX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xe0ffffff))
+#define SET_RG_RX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffffc0))
+#define SET_RG_RX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffc0ff))
+#define SET_RG_RX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffc0ffff))
+#define SET_RG_RX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xc0ffffff))
+#define SET_RG_RX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffffc0))
+#define SET_RG_RX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffc0ff))
+#define SET_RG_RX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffc0ffff))
+#define SET_RG_RX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xc0ffffff))
+#define SET_RG_RX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffffe))
+#define SET_RG_RX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffffef))
+#define SET_RG_RX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffeff))
+#define SET_RG_RX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffefff))
+#define SET_RG_RX_DES_SNR(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfff0ffff))
+#define SET_RG_RX_DES_RCPI(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xff0fffff))
+#define SET_RG_RX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xc0ffffff))
+#define SET_RO_TX_DES_EXCP_RATE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffffff00))
+#define SET_RO_TX_DES_EXCP_CH_BW_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffff00ff))
+#define SET_RO_TX_DES_EXCP_MODE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xff00ffff))
+#define SET_RG_TX_DES_EXCP_RATE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xf8ffffff))
+#define SET_RG_TX_DES_EXCP_MODE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x8fffffff))
+#define SET_RG_TX_DES_EXCP_CLR(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x7fffffff))
+#define SET_RG_TX_DES_ACK_WIDTH(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffffe))
+#define SET_RG_TX_DES_ACK_PRD(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffff1))
+#define SET_RG_RX_DES_SNR_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xffc0ffff))
+#define SET_RG_RX_DES_RCPI_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xc0ffffff))
+#define SET_RG_TST_TBUS_SEL(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfffffff0))
+#define SET_RG_RSSI_OFFSET(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xff00ffff))
+#define SET_RG_RSSI_INV(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfeffffff))
+#define SET_RG_TST_ADC_ON(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xbfffffff))
+#define SET_RG_TST_EXT_GAIN(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x7fffffff))
+#define SET_RG_DAC_Q_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xfffffc00))
+#define SET_RG_DAC_I_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xffc00fff))
+#define SET_RG_DAC_EN_MAN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xefffffff))
+#define SET_RG_IQC_FFT_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xdfffffff))
+#define SET_RG_DAC_MAN_Q_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xbfffffff))
+#define SET_RG_DAC_MAN_I_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x7fffffff))
+#define SET_RO_MRX_EN_CNT(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0xffff0000))
+#define SET_RG_MRX_EN_CNT_RST_N(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x7fffffff))
+#define SET_RG_PA_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffffff00))
+#define SET_RG_RFTX_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffff00ff))
+#define SET_RG_DAC_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff00ffff))
+#define SET_RG_SW_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ffffff))
+#define SET_RG_PA_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffffff00))
+#define SET_RG_RFTX_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffff00ff))
+#define SET_RG_DAC_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff00ffff))
+#define SET_RG_SW_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ffffff))
+#define SET_RG_ANT_SW_0(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xfffffff8))
+#define SET_RG_ANT_SW_1(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xffffffc7))
+#define SET_RG_MTX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MTX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MTX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x7fffffff))
+#define SET_RG_MTX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MTX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MTX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x7fffffff))
+#define SET_RG_MRX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MRX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MRX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x7fffffff))
+#define SET_RG_MRX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MRX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MRX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x7fffffff))
+#define SET_RO_MTX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000))
+#define SET_RO_MTX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff))
+#define SET_RO_MRX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000))
+#define SET_RO_MRX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff))
+#define SET_RG_MODE_REG_IN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffff0000))
+#define SET_RG_PARALLEL_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffefffff))
+#define SET_RG_MBRUN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xfeffffff))
+#define SET_RG_SHIFT_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xefffffff))
+#define SET_RG_MODE_REG_SI_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xdfffffff))
+#define SET_RG_SIMULATION_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xbfffffff))
+#define SET_RG_DBIST_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_28_BIST)) & 0x7fffffff))
+#define SET_RO_MODE_REG_OUT_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xffff0000))
+#define SET_RO_MODE_REG_SO_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xfeffffff))
+#define SET_RO_MONITOR_BUS_16(_VAL_) (REG32(ADR_PHY_READ_REG_07_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_07_BIST)) & 0xfff80000))
+#define SET_RG_MRX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffffff00))
+#define SET_RG_MRX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffff00ff))
+#define SET_RG_MTX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff00ffff))
+#define SET_RG_MTX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ffffff))
+#define SET_RO_MTX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000))
+#define SET_RO_MTX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff))
+#define SET_RO_MRX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000))
+#define SET_RO_MRX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff))
+#define SET_RG_HB_COEF0(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xfffff000))
+#define SET_RG_HB_COEF1(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xf000ffff))
+#define SET_RG_HB_COEF2(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xfffff000))
+#define SET_RG_HB_COEF3(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xf000ffff))
+#define SET_RG_HB_COEF4(_VAL_) (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0xfffff000))
+#define SET_RO_TBUS_O(_VAL_) (REG32(ADR_PHY_READ_TBUS)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_TBUS)) & 0xfff00000))
+#define SET_RG_LPF4_00(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_00)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_00)) & 0xffffe000))
+#define SET_RG_LPF4_01(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_01)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_01)) & 0xffffe000))
+#define SET_RG_LPF4_02(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_02)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_02)) & 0xffffe000))
+#define SET_RG_LPF4_03(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_03)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_03)) & 0xffffe000))
+#define SET_RG_LPF4_04(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_04)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_04)) & 0xffffe000))
+#define SET_RG_LPF4_05(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_05)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_05)) & 0xffffe000))
+#define SET_RG_LPF4_06(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_06)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_06)) & 0xffffe000))
+#define SET_RG_LPF4_07(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_07)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_07)) & 0xffffe000))
+#define SET_RG_LPF4_08(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_08)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_08)) & 0xffffe000))
+#define SET_RG_LPF4_09(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_09)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_09)) & 0xffffe000))
+#define SET_RG_LPF4_10(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_10)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_10)) & 0xffffe000))
+#define SET_RG_LPF4_11(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_11)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_11)) & 0xffffe000))
+#define SET_RG_LPF4_12(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_12)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_12)) & 0xffffe000))
+#define SET_RG_LPF4_13(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_13)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_13)) & 0xffffe000))
+#define SET_RG_LPF4_14(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_14)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_14)) & 0xffffe000))
+#define SET_RG_LPF4_15(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_15)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_15)) & 0xffffe000))
+#define SET_RG_LPF4_16(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_16)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_16)) & 0xffffe000))
+#define SET_RG_LPF4_17(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_17)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_17)) & 0xffffe000))
+#define SET_RG_LPF4_18(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_18)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_18)) & 0xffffe000))
+#define SET_RG_LPF4_19(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_19)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_19)) & 0xffffe000))
+#define SET_RG_LPF4_20(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_20)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_20)) & 0xffffe000))
+#define SET_RG_LPF4_21(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_21)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_21)) & 0xffffe000))
+#define SET_RG_LPF4_22(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_22)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_22)) & 0xffffe000))
+#define SET_RG_LPF4_23(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_23)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_23)) & 0xffffe000))
+#define SET_RG_LPF4_24(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_24)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_24)) & 0xffffe000))
+#define SET_RG_LPF4_25(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_25)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_25)) & 0xffffe000))
+#define SET_RG_LPF4_26(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_26)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_26)) & 0xffffe000))
+#define SET_RG_LPF4_27(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_27)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_27)) & 0xffffe000))
+#define SET_RG_LPF4_28(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_28)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_28)) & 0xffffe000))
+#define SET_RG_LPF4_29(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_29)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_29)) & 0xffffe000))
+#define SET_RG_LPF4_30(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_30)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_30)) & 0xffffe000))
+#define SET_RG_LPF4_31(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_31)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_31)) & 0xffffe000))
+#define SET_RG_LPF4_32(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_32)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_32)) & 0xffffe000))
+#define SET_RG_LPF4_33(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_33)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_33)) & 0xffffe000))
+#define SET_RG_LPF4_34(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_34)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_34)) & 0xffffe000))
+#define SET_RG_LPF4_35(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_35)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_35)) & 0xffffe000))
+#define SET_RG_LPF4_36(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_36)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_36)) & 0xffffe000))
+#define SET_RG_LPF4_37(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_37)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_37)) & 0xffffe000))
+#define SET_RG_LPF4_38(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_38)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_38)) & 0xffffe000))
+#define SET_RG_LPF4_39(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_39)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_39)) & 0xffffe000))
+#define SET_RG_LPF4_40(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_40)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_40)) & 0xffffe000))
+#define SET_RG_BP_SMB(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 13) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffdfff))
+#define SET_RG_EN_SRVC(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 14) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffbfff))
+#define SET_RG_DES_SPD(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 16) | ((REG32(ADR_TX_11B_PLCP)) & 0xfffcffff))
+#define SET_RG_BB_11B_RISE_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_RAMP)) & 0xffffff00))
+#define SET_RG_BB_11B_FALL_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11B_RAMP)) & 0xffff00ff))
+#define SET_RG_WR_TX_EN_CNT_RST_N(_VAL_) (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0xfffffffe))
+#define SET_RO_TX_EN_CNT(_VAL_) (REG32(ADR_TX_11B_EN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT)) & 0xffff0000))
+#define SET_RO_TX_CNT(_VAL_) (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0x00000000))
+#define SET_RG_POS_DES_11B_L_EXT(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xfffffff0))
+#define SET_RG_PRE_DES_11B_DLY(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xffffff0f))
+#define SET_RG_CNT_CCA_LMT(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_0)) & 0xfff0ffff))
+#define SET_RG_BYPASS_DESCRAMBLER(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11B_CCA_0)) & 0xdfffffff))
+#define SET_RG_BYPASS_AGC(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11B_CCA_0)) & 0x7fffffff))
+#define SET_RG_CCA_BIT_CNT_LMT_RX(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CCA_1)) & 0xffffff0f))
+#define SET_RG_CCA_SCALE_BF(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_1)) & 0xff80ffff))
+#define SET_RG_PEAK_IDX_CNT_SEL(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11B_CCA_1)) & 0xcfffffff))
+#define SET_RG_TR_KI_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffffff8))
+#define SET_RG_TR_KP_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffffff8f))
+#define SET_RG_TR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffff8ff))
+#define SET_RG_TR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffff8fff))
+#define SET_RG_CR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xfff8ffff))
+#define SET_RG_CR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xff8fffff))
+#define SET_RG_CHIP_CNT_SLICER(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffffffe0))
+#define SET_RG_CE_T4_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffff00ff))
+#define SET_RG_CE_T3_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff00ffff))
+#define SET_RG_CE_T2_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ffffff))
+#define SET_RG_CE_MU_T1(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xfffffff8))
+#define SET_RG_CE_DLY_SEL(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xffc0ffff))
+#define SET_RG_CE_MU_T8(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffffff8))
+#define SET_RG_CE_MU_T7(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffffff8f))
+#define SET_RG_CE_MU_T6(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffff8ff))
+#define SET_RG_CE_MU_T5(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffff8fff))
+#define SET_RG_CE_MU_T4(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfff8ffff))
+#define SET_RG_CE_MU_T3(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xff8fffff))
+#define SET_RG_CE_MU_T2(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xf8ffffff))
+#define SET_RG_EQ_MU_FB_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfffffff0))
+#define SET_RG_EQ_MU_FF_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xffffff0f))
+#define SET_RG_EQ_MU_FB_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfff0ffff))
+#define SET_RG_EQ_MU_FF_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xff0fffff))
+#define SET_RG_EQ_MU_FB_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfffffff0))
+#define SET_RG_EQ_MU_FF_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xffffff0f))
+#define SET_RG_EQ_MU_FB_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfff0ffff))
+#define SET_RG_EQ_MU_FF_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xff0fffff))
+#define SET_RG_EQ_KI_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfffff8ff))
+#define SET_RG_EQ_KP_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xffff8fff))
+#define SET_RG_EQ_KI_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfff8ffff))
+#define SET_RG_EQ_KP_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xff8fffff))
+#define SET_RG_TR_LPF_RATE(_VAL_) (REG32(ADR_RX_11B_LPF_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_LPF_RATE)) & 0xffc00000))
+#define SET_RG_CE_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff80))
+#define SET_RG_CE_CH_MAIN_SET(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff7f))
+#define SET_RG_TC_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffff80ff))
+#define SET_RG_CR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xff80ffff))
+#define SET_RG_TR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x80ffffff))
+#define SET_RG_EQ_MAIN_TAP_MAN(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xfffffffe))
+#define SET_RG_EQ_MAIN_TAP_COEF(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xf800ffff))
+#define SET_RG_PWRON_DLY_TH_11B(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xffffff00))
+#define SET_RG_SFD_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xff00ffff))
+#define SET_RG_CCA_PWR_TH_RX(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffff8000))
+#define SET_RG_CCA_PWR_CNT_TH(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffe0ffff))
+#define SET_B_FREQ_OS(_VAL_) (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0xfffff800))
+#define SET_B_SNR(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xffffff80))
+#define SET_B_RCPI(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xff80ffff))
+#define SET_CRC_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000))
+#define SET_SFD_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff))
+#define SET_B_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xffff0000))
+#define SET_PACKET_ERR(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xfffeffff))
+#define SET_B_PACKET_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
+#define SET_B_CCA_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
+#define SET_B_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000))
+#define SET_SFD_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff))
+#define SET_SIGNAL_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffffff00))
+#define SET_B_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffff00ff))
+#define SET_CRC_CORRECT(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xfffeffff))
+#define SET_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xfffffff0))
+#define SET_RG_PACKET_STAT_EN_11B(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffefffff))
+#define SET_RG_BIT_REVERSE(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffdfffff))
+#define SET_RX_PHY_11B_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffffffe))
+#define SET_RG_CE_BYPASS_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xffffff0f))
+#define SET_RG_EQ_BYPASS_FBW_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffff0ff))
+#define SET_RG_BB_11GN_RISE_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffffff00))
+#define SET_RG_BB_11GN_FALL_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffff00ff))
+#define SET_RG_HTCARR52_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP)) & 0xfffffc00))
+#define SET_RG_HTCARR56_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 12) | ((REG32(ADR_TX_11GN_PLCP)) & 0xffc00fff))
+#define SET_RG_PACKET_STAT_EN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 23) | ((REG32(ADR_TX_11GN_PLCP)) & 0xff7fffff))
+#define SET_RG_SMB_DEF(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 24) | ((REG32(ADR_TX_11GN_PLCP)) & 0x80ffffff))
+#define SET_RG_CONTINUOUS_DATA_11GN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 31) | ((REG32(ADR_TX_11GN_PLCP)) & 0x7fffffff))
+#define SET_RO_TX_CNT_R(_VAL_) (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0x00000000))
+#define SET_RO_PACKET_ERR_CNT(_VAL_) (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0xffff0000))
+#define SET_RG_POS_DES_11GN_L_EXT(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xfffffff0))
+#define SET_RG_PRE_DES_11GN_DLY(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xffffff0f))
+#define SET_RG_TR_LPF_KI_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfffffff0))
+#define SET_RG_TR_LPF_KP_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffffff0f))
+#define SET_RG_TR_CNT_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffff00ff))
+#define SET_RG_TR_LPF_KI_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfff0ffff))
+#define SET_RG_TR_LPF_KP_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TR_0)) & 0xff0fffff))
+#define SET_RG_TR_CNT_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_TR_0)) & 0x00ffffff))
+#define SET_RG_TR_LPF_KI_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_1)) & 0xfffffff0))
+#define SET_RG_TR_LPF_KP_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffffff0f))
+#define SET_RG_TR_CNT_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffff00ff))
+#define SET_RG_TR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_2)) & 0xfffffff0))
+#define SET_RG_TR_LPF_KP_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_2)) & 0xffffff0f))
+#define SET_RG_TR_LPF_RATE_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_2)) & 0xc00000ff))
+#define SET_RG_CR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xfffffff8))
+#define SET_RG_SYM_BOUND_CNT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xffff80ff))
+#define SET_RG_XSCOR32_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xff80ffff))
+#define SET_RG_ATCOR64_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_0)) & 0x80ffffff))
+#define SET_RG_ATCOR16_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xffff80ff))
+#define SET_RG_ATCOR16_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xff80ffff))
+#define SET_RG_ATCOR16_RATIO_SB(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_1)) & 0x80ffffff))
+#define SET_RG_XSCOR64_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_2)) & 0xff80ffff))
+#define SET_RG_XSCOR64_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_2)) & 0x80ffffff))
+#define SET_RG_RX_FFT_SCALE(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffffc00))
+#define SET_RG_VITERBI_AB_SWAP(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffeffff))
+#define SET_RG_ATCOR16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xf0ffffff))
+#define SET_RG_NORMSQUARE_LOW_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffffff00))
+#define SET_RG_NORMSQUARE_LOW_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffff00ff))
+#define SET_RG_NORMSQUARE_LOW_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff00ffff))
+#define SET_RG_NORMSQUARE_LOW_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_LOW_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_SNR_3(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffffff00))
+#define SET_RG_NORMSQUARE_SNR_2(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffff00ff))
+#define SET_RG_NORMSQUARE_SNR_1(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff00ffff))
+#define SET_RG_NORMSQUARE_SNR_0(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffffff00))
+#define SET_RG_NORMSQUARE_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffff00ff))
+#define SET_RG_NORMSQUARE_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff00ffff))
+#define SET_RG_NORMSQUARE_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0x00ffffff))
+#define SET_RG_SNR_TH_64QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffffff80))
+#define SET_RG_SNR_TH_16QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffff80ff))
+#define SET_RG_ATCOR16_CNT_PLUS_LMT2(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffffff80))
+#define SET_RG_ATCOR16_CNT_PLUS_LMT1(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffff80ff))
+#define SET_RG_SYM_BOUND_METHOD(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xfffcffff))
+#define SET_RG_PWRON_DLY_TH_11GN(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffffff00))
+#define SET_RG_SB_START_CNT(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffff80ff))
+#define SET_RG_POW16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xffffff0f))
+#define SET_RG_POW16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xfffff8ff))
+#define SET_RG_POW16_TH_L(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0x80ffffff))
+#define SET_RG_XSCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfffffff8))
+#define SET_RG_XSCOR16_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xffff80ff))
+#define SET_RG_ATCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfff8ffff))
+#define SET_RG_ATCOR16_RATIO_CCD(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0x80ffffff))
+#define SET_RG_ATCOR64_ACC_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xffffff80))
+#define SET_RG_ATCOR16_SHORT_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xfff8ffff))
+#define SET_RG_VITERBI_TB_BITS(_VAL_) (REG32(ADR_RX_11GN_VTB_TB)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_VTB_TB)) & 0x00ffffff))
+#define SET_RG_CR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xffffff00))
+#define SET_RG_TR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xff00ffff))
+#define SET_RG_BYPASS_CPE_MA(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffffffef))
+#define SET_RG_PILOT_BNDRY_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfffff8ff))
+#define SET_RG_EQ_SHORT_GI_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffff8fff))
+#define SET_RG_FFT_WDW_SHORT_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfff8ffff))
+#define SET_RG_CHSMTH_COEF(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffcffff))
+#define SET_RG_CHSMTH_EN(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 18) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffbffff))
+#define SET_RG_CHEST_DD_FACTOR(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xf8ffffff))
+#define SET_RG_CH_UPDATE(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x7fffffff))
+#define SET_RG_FMT_DET_MM_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffffff00))
+#define SET_RG_FMT_DET_GF_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffff00ff))
+#define SET_RG_DO_NOT_CHECK_L_RATE(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xfdffffff))
+#define SET_RG_FMT_DET_LENGTH_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000))
+#define SET_RG_L_LENGTH_MAX(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff))
+#define SET_RG_TX_TIME_EXT(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xffffff00))
+#define SET_RG_MAC_DES_SPACE(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xff0fffff))
+#define SET_RG_TR_LPF_STBC_GF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffffff0))
+#define SET_RG_TR_LPF_STBC_GF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffffff0f))
+#define SET_RG_TR_LPF_STBC_MF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffff0ff))
+#define SET_RG_TR_LPF_STBC_MF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffff0fff))
+#define SET_RG_MODE_REG_IN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfffe0000))
+#define SET_RG_PARALLEL_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xffefffff))
+#define SET_RG_MBRUN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfeffffff))
+#define SET_RG_SHIFT_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xefffffff))
+#define SET_RG_MODE_REG_SI_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xdfffffff))
+#define SET_RG_SIMULATION_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xbfffffff))
+#define SET_RG_DBIST_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_0)) & 0x7fffffff))
+#define SET_RG_MODE_REG_IN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffff0000))
+#define SET_RG_PARALLEL_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffefffff))
+#define SET_RG_MBRUN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xfeffffff))
+#define SET_RG_SHIFT_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xefffffff))
+#define SET_RG_MODE_REG_SI_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xdfffffff))
+#define SET_RG_SIMULATION_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xbfffffff))
+#define SET_RG_DBIST_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_1)) & 0x7fffffff))
+#define SET_RO_MODE_REG_OUT_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfffe0000))
+#define SET_RO_MODE_REG_SO_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfeffffff))
+#define SET_RO_MONITOR_BUS_80(_VAL_) (REG32(ADR_RX_11GN_BIST_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_3)) & 0xffc00000))
+#define SET_RO_MODE_REG_OUT_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xffff0000))
+#define SET_RO_MODE_REG_SO_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xfeffffff))
+#define SET_RO_MONITOR_BUS_64(_VAL_) (REG32(ADR_RX_11GN_BIST_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_5)) & 0xfff80000))
+#define SET_RO_SPECTRUM_DATA(_VAL_) (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0x00000000))
+#define SET_GN_SNR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffffff80))
+#define SET_GN_NOISE_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffff80ff))
+#define SET_GN_RCPI(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_READ_0)) & 0xff80ffff))
+#define SET_GN_SIGNAL_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_READ_0)) & 0x80ffffff))
+#define SET_RO_FREQ_OS_LTS(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xffff8000))
+#define SET_CSTATE(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xfff0ffff))
+#define SET_SIGNAL_FIELD0(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0xff000000))
+#define SET_SIGNAL_FIELD1(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0xff000000))
+#define SET_GN_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0xffff0000))
+#define SET_GN_PACKET_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
+#define SET_GN_CCA_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
+#define SET_GN_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000))
+#define SET_GN_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff))
+#define SET_RO_HT_MCS_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffff80))
+#define SET_RO_L_RATE_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffc0ff))
+#define SET_RG_DAGC_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xfffffffc))
+#define SET_RG_PACKET_STAT_EN_11GN(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xffefffff))
+#define SET_RX_PHY_11GN_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffe))
+#define SET_RG_RIFS_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 1) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffd))
+#define SET_RG_STBC_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 2) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffb))
+#define SET_RG_COR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 3) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffff7))
+#define SET_RG_INI_PHASE(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffcf))
+#define SET_RG_HT_LTF_SEL_EQ(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 6) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffbf))
+#define SET_RG_HT_LTF_SEL_PILOT(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffff7f))
+#define SET_RG_CCA_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 9) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffdff))
+#define SET_RG_CCA_XSCOR_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 10) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffbff))
+#define SET_RG_CCA_XSCOR_AVGPWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 11) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffff7ff))
+#define SET_RG_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffff0fff))
+#define SET_RG_POST_CLK_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffeffff))
+#define SET_IQCAL_RF_TX_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffe))
+#define SET_IQCAL_RF_TX_PA_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 1) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffd))
+#define SET_IQCAL_RF_TX_DAC_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 2) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffb))
+#define SET_IQCAL_RF_RX_AGC(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 3) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffff7))
+#define SET_IQCAL_RF_PGAG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffff0ff))
+#define SET_IQCAL_RF_RFG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 12) | ((REG32(ADR_RF_CONTROL_0)) & 0xffffcfff))
+#define SET_RG_TONEGEN_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_CONTROL_0)) & 0xff80ffff))
+#define SET_RG_TONEGEN_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 23) | ((REG32(ADR_RF_CONTROL_0)) & 0xff7fffff))
+#define SET_RG_TONEGEN_INIT_PH(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_CONTROL_0)) & 0x80ffffff))
+#define SET_RG_TONEGEN2_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff80))
+#define SET_RG_TONEGEN2_EN(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 7) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff7f))
+#define SET_RG_TONEGEN2_SCALE(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_1)) & 0xffff00ff))
+#define SET_RG_TXIQ_CLP_THD_I(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfffffc00))
+#define SET_RG_TXIQ_CLP_THD_Q(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfc00ffff))
+#define SET_RG_TX_I_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffffff00))
+#define SET_RG_TX_Q_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffff00ff))
+#define SET_RG_TX_IQ_SWP(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffeffff))
+#define SET_RG_TX_SGN_OUT(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 17) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffdffff))
+#define SET_RG_TXIQ_EMU_IDX(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 18) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffc3ffff))
+#define SET_RG_TX_IQ_SRC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfcffffff))
+#define SET_RG_TX_I_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfffffc00))
+#define SET_RG_TX_Q_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfc00ffff))
+#define SET_RG_TX_IQ_THETA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffffe0))
+#define SET_RG_TX_IQ_ALPHA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffe0ff))
+#define SET_RG_TXIQ_NOSHRINK(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffdfff))
+#define SET_RG_TX_I_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff00ffff))
+#define SET_RG_TX_Q_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 24) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ffffff))
+#define SET_RG_RX_IQ_THETA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffffe0))
+#define SET_RG_RX_IQ_ALPHA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffe0ff))
+#define SET_RG_RXIQ_NOSHRINK(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffdfff))
+#define SET_RG_MA_DPTH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffff0))
+#define SET_RG_INTG_PH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffc0f))
+#define SET_RG_INTG_PRD(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 10) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffffe3ff))
+#define SET_RG_INTG_MU(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 13) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffff9fff))
+#define SET_RG_IQCAL_SPRM_SELQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffeffff))
+#define SET_RG_IQCAL_SPRM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 17) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffdffff))
+#define SET_RG_IQCAL_SPRM_FREQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 18) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xff03ffff))
+#define SET_RG_IQCAL_IQCOL_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfeffffff))
+#define SET_RG_IQCAL_ALPHA_ESTM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfdffffff))
+#define SET_RG_IQCAL_DC_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfbffffff))
+#define SET_RG_PHEST_STBY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xf7ffffff))
+#define SET_RG_PHEST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xefffffff))
+#define SET_RG_GP_DIV_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xdfffffff))
+#define SET_RG_DPD_GAIN_EST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xbfffffff))
+#define SET_RG_IQCAL_MULT_OP0(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfffffc00))
+#define SET_RG_IQCAL_MULT_OP1(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfc00ffff))
+#define SET_RO_IQCAL_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfff00000))
+#define SET_RO_IQCAL_SPRM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 20) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffefffff))
+#define SET_RO_IQCAL_IQCOL_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 21) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffdfffff))
+#define SET_RO_IQCAL_ALPHA_ESTM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 22) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffbfffff))
+#define SET_RO_IQCAL_DC_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 23) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xff7fffff))
+#define SET_RO_IQCAL_MULT_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfeffffff))
+#define SET_RO_FFT_ENRG_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfdffffff))
+#define SET_RO_PHEST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfbffffff))
+#define SET_RO_GP_DIV_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xf7ffffff))
+#define SET_RO_GAIN_EST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xefffffff))
+#define SET_RO_AMP_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0xfffffe00))
+#define SET_RG_RX_I_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffffff00))
+#define SET_RG_RX_Q_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffff00ff))
+#define SET_RG_RX_I_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff00ffff))
+#define SET_RG_RX_Q_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ffffff))
+#define SET_RG_RX_IQ_SWP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffe))
+#define SET_RG_RX_SGN_IN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffd))
+#define SET_RG_RX_IQ_SRC(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 2) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffff3))
+#define SET_RG_ACI_GAIN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffff00f))
+#define SET_RG_FFT_EN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 12) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffefff))
+#define SET_RG_FFT_MOD(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 13) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffdfff))
+#define SET_RG_FFT_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 14) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xff003fff))
+#define SET_RG_FFT_ENRG_FREQ(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xc0ffffff))
+#define SET_RG_FPGA_80M_PH_UP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 30) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xbfffffff))
+#define SET_RG_FPGA_80M_PH_STP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 31) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0x7fffffff))
+#define SET_RG_ADC2LA_SEL(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffe))
+#define SET_RG_ADC2LA_CLKPH(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffd))
+#define SET_RG_RXIQ_EMU_IDX(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xfffffff0))
+#define SET_RG_IQCAL_BP_ACI(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xffffffef))
+#define SET_RG_DPD_AM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffe))
+#define SET_RG_DPD_PM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffd))
+#define SET_RG_DPD_PM_AMSEL(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffb))
+#define SET_RG_DPD_020_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfffffc00))
+#define SET_RG_DPD_040_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfc00ffff))
+#define SET_RG_DPD_060_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfffffc00))
+#define SET_RG_DPD_080_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfc00ffff))
+#define SET_RG_DPD_0A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfffffc00))
+#define SET_RG_DPD_0C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfc00ffff))
+#define SET_RG_DPD_0D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfffffc00))
+#define SET_RG_DPD_0E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfc00ffff))
+#define SET_RG_DPD_0F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfffffc00))
+#define SET_RG_DPD_100_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfc00ffff))
+#define SET_RG_DPD_110_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfffffc00))
+#define SET_RG_DPD_120_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfc00ffff))
+#define SET_RG_DPD_130_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfffffc00))
+#define SET_RG_DPD_140_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfc00ffff))
+#define SET_RG_DPD_150_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfffffc00))
+#define SET_RG_DPD_160_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfc00ffff))
+#define SET_RG_DPD_170_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfffffc00))
+#define SET_RG_DPD_180_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfc00ffff))
+#define SET_RG_DPD_190_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfffffc00))
+#define SET_RG_DPD_1A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfc00ffff))
+#define SET_RG_DPD_1B0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfffffc00))
+#define SET_RG_DPD_1C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfc00ffff))
+#define SET_RG_DPD_1D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfffffc00))
+#define SET_RG_DPD_1E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfc00ffff))
+#define SET_RG_DPD_1F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfffffc00))
+#define SET_RG_DPD_200_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfc00ffff))
+#define SET_RG_DPD_020_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xffffe000))
+#define SET_RG_DPD_040_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xe000ffff))
+#define SET_RG_DPD_060_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xffffe000))
+#define SET_RG_DPD_080_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xe000ffff))
+#define SET_RG_DPD_0A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xffffe000))
+#define SET_RG_DPD_0C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xe000ffff))
+#define SET_RG_DPD_0D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xffffe000))
+#define SET_RG_DPD_0E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xe000ffff))
+#define SET_RG_DPD_0F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xffffe000))
+#define SET_RG_DPD_100_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xe000ffff))
+#define SET_RG_DPD_110_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xffffe000))
+#define SET_RG_DPD_120_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xe000ffff))
+#define SET_RG_DPD_130_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xffffe000))
+#define SET_RG_DPD_140_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xe000ffff))
+#define SET_RG_DPD_150_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xffffe000))
+#define SET_RG_DPD_160_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xe000ffff))
+#define SET_RG_DPD_170_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xffffe000))
+#define SET_RG_DPD_180_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xe000ffff))
+#define SET_RG_DPD_190_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xffffe000))
+#define SET_RG_DPD_1A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xe000ffff))
+#define SET_RG_DPD_1B0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xffffe000))
+#define SET_RG_DPD_1C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xe000ffff))
+#define SET_RG_DPD_1D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xffffe000))
+#define SET_RG_DPD_1E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xe000ffff))
+#define SET_RG_DPD_1F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xffffe000))
+#define SET_RG_DPD_200_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xe000ffff))
+#define SET_RG_DPD_GAIN_EST_Y0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfffffe00))
+#define SET_RG_DPD_GAIN_EST_Y1(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfe00ffff))
+#define SET_RG_DPD_LOOP_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0xfffffc00))
+#define SET_RG_DPD_GAIN_EST_X0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfffffe00))
+#define SET_RO_DPD_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfc00ffff))
+#define SET_TX_SCALE_11B(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffffff00))
+#define SET_TX_SCALE_11B_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 8) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffff00ff))
+#define SET_TX_SCALE_11G(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xff00ffff))
+#define SET_TX_SCALE_11G_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 24) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ffffff))
+#define SET_RG_EN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
+#define SET_RG_TX_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
+#define SET_RG_TX_PA_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
+#define SET_RG_TX_DAC_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
+#define SET_RG_RX_AGC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
+#define SET_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
+#define SET_RG_RFG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
+#define SET_RG_PGAG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
+#define SET_RG_MODE(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
+#define SET_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
+#define SET_RG_EN_SX(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
+#define SET_RG_EN_RX_LNA(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
+#define SET_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
+#define SET_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
+#define SET_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
+#define SET_RG_EN_RX_TZ(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
+#define SET_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
+#define SET_RG_EN_RX_HPF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
+#define SET_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
+#define SET_RG_EN_ADC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
+#define SET_RG_EN_TX_MOD(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
+#define SET_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
+#define SET_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
+#define SET_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
+#define SET_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
+#define SET_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
+#define SET_RG_EN_CLK_960MBY13_UART(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x7fffffff))
+#define SET_RG_EN_TX_DPD(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
+#define SET_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
+#define SET_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
+#define SET_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
+#define SET_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
+#define SET_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
+#define SET_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
+#define SET_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
+#define SET_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
+#define SET_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
+#define SET_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
+#define SET_RG_EN_IREF_RX(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
+#define SET_RG_EN_TX_DAC_VOUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffdfff))
+#define SET_RG_EN_SX_LCK_BIN(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffbfff))
+#define SET_RG_RTC_CAL_MODE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffeffff))
+#define SET_RG_EN_IQPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffdffff))
+#define SET_RG_EN_TESTPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffbffff))
+#define SET_RG_EN_TRXBF_BYPASS(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfff7ffff))
+#define SET_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffff8))
+#define SET_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_LDO_REGISTER)) & 0xffffffc7))
+#define SET_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffe3f))
+#define SET_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_LDO_REGISTER)) & 0xfffff1ff))
+#define SET_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_LDO_REGISTER)) & 0xffff8fff))
+#define SET_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_LDO_REGISTER)) & 0xfffc7fff))
+#define SET_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_LDO_REGISTER)) & 0xffe3ffff))
+#define SET_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_LDO_REGISTER)) & 0xff1fffff))
+#define SET_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_LDO_REGISTER)) & 0xf8ffffff))
+#define SET_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffe))
+#define SET_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffd))
+#define SET_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffb))
+#define SET_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffe07))
+#define SET_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffdff))
+#define SET_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffbff))
+#define SET_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffff7ff))
+#define SET_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffffcfff))
+#define SET_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffff3fff))
+#define SET_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffcffff))
+#define SET_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfff3ffff))
+#define SET_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffcfffff))
+#define SET_RG_RX_HPF3M(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffbfffff))
+#define SET_RG_RX_HPF300K(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_1)) & 0xff7fffff))
+#define SET_RG_RX_HPFI(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfcffffff))
+#define SET_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_ABB_REGISTER_1)) & 0xf3ffffff))
+#define SET_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_ABB_REGISTER_1)) & 0xcfffffff))
+#define SET_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffffc))
+#define SET_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffff3))
+#define SET_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffffcf))
+#define SET_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffff3f))
+#define SET_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffcff))
+#define SET_RG_RX_OUTVCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffff3ff))
+#define SET_RG_RX_TZI(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffcfff))
+#define SET_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffbfff))
+#define SET_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffe7fff))
+#define SET_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfff1ffff))
+#define SET_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffefffff))
+#define SET_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_ABB_REGISTER_2)) & 0xff9fffff))
+#define SET_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfe7fffff))
+#define SET_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfdffffff))
+#define SET_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffffffc))
+#define SET_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffff03))
+#define SET_RG_TXPGA_STEER(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffc0ff))
+#define SET_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffff3fff))
+#define SET_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffcffff))
+#define SET_RG_PACELL_EN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffe3ffff))
+#define SET_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfe1fffff))
+#define SET_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_TX_FE_REGISTER)) & 0xf3ffffff))
+#define SET_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_TX_FE_REGISTER)) & 0xcfffffff))
+#define SET_RG_RX_SQDC(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffffff8))
+#define SET_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffffe7))
+#define SET_RG_RX_LOBUF(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffff9f))
+#define SET_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffff87f))
+#define SET_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffff87ff))
+#define SET_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffc7fff))
+#define SET_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffe3ffff))
+#define SET_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffdfffff))
+#define SET_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xff3fffff))
+#define SET_RG_PACASCODE_CTRL(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xf8ffffff))
+#define SET_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
+#define SET_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
+#define SET_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
+#define SET_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
+#define SET_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
+#define SET_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
+#define SET_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
+#define SET_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
+#define SET_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
+#define SET_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
+#define SET_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
+#define SET_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
+#define SET_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
+#define SET_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
+#define SET_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
+#define SET_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
+#define SET_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
+#define SET_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
+#define SET_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
+#define SET_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
+#define SET_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
+#define SET_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
+#define SET_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
+#define SET_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
+#define SET_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffe))
+#define SET_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffd))
+#define SET_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffb))
+#define SET_RG_HPF_T1A(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffffe7))
+#define SET_RG_HPF_T1B(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffff9f))
+#define SET_RG_HPF_T1C(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffe7f))
+#define SET_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffff9ff))
+#define SET_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffe7ff))
+#define SET_RG_TXGAIN_PHYCTRL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffdfff))
+#define SET_RG_TX_GAIN(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffc03fff))
+#define SET_RG_TXGAIN_MANUAL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffbfffff))
+#define SET_RG_TX_GAIN_OFFSET(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xf87fffff))
+#define SET_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffffe))
+#define SET_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff9))
+#define SET_RG_ADC_DIVR(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff7))
+#define SET_RG_ADC_DVCMI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffffffcf))
+#define SET_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffc3f))
+#define SET_RG_ADC_STNBY(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffbff))
+#define SET_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffff7ff))
+#define SET_RG_ADC_TSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffff0fff))
+#define SET_RG_ADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffcffff))
+#define SET_RG_DICMP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfff3ffff))
+#define SET_RG_DIOP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffcfffff))
+#define SET_RG_SARADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xff3fffff))
+#define SET_RG_EN_SAR_TEST(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfcffffff))
+#define SET_RG_SARADC_THERMAL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfbffffff))
+#define SET_RG_SARADC_TSSI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xf7ffffff))
+#define SET_RG_CLK_SAR_SEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xcfffffff))
+#define SET_RG_EN_SARADC(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xbfffffff))
+#define SET_RG_DACI1ST(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffffc))
+#define SET_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffff3))
+#define SET_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffffcf))
+#define SET_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffff3f))
+#define SET_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffeff))
+#define SET_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffff9ff))
+#define SET_RG_TX_DAC_OS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffc7ff))
+#define SET_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffff3fff))
+#define SET_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfff0ffff))
+#define SET_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffefffff))
+#define SET_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffdfffff))
+#define SET_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffbfffff))
+#define SET_RG_TX_DAC_IOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xf87fffff))
+#define SET_RG_TX_DAC_QOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_TX_DAC_REGISTER)) & 0x87ffffff))
+#define SET_RG_EN_SX_R3(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffe))
+#define SET_RG_EN_SX_CH(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffd))
+#define SET_RG_EN_SX_CHP(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffb))
+#define SET_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffff7))
+#define SET_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffef))
+#define SET_RG_EN_SX_VCO(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffdf))
+#define SET_RG_EN_SX_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffbf))
+#define SET_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffeff))
+#define SET_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffff7ff))
+#define SET_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffefff))
+#define SET_RG_EN_SX_DIV(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffdfff))
+#define SET_RG_EN_SX_LPF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffbfff))
+#define SET_RG_EN_DPL_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffff7fff))
+#define SET_RG_DPL_MOD_ORDER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffcffff))
+#define SET_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_1)) & 0xff000000))
+#define SET_RG_SX_SEL_CP(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_REGISTER_1)) & 0xf0ffffff))
+#define SET_RG_SX_SEL_CS(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_REGISTER_1)) & 0x0fffffff))
+#define SET_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfffff800))
+#define SET_RG_SX_SEL_C3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_REGISTER_2)) & 0xffff87ff))
+#define SET_RG_SX_SEL_RS(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfff07fff))
+#define SET_RG_SX_SEL_R3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfe0fffff))
+#define SET_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffffe0))
+#define SET_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffffc1f))
+#define SET_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffc3ff))
+#define SET_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffc3fff))
+#define SET_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffbffff))
+#define SET_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffc7ffff))
+#define SET_RG_SX_PFDSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffbfffff))
+#define SET_RG_SX_PFD_SET(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_SYN_PFD_CHP)) & 0xff7fffff))
+#define SET_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfeffffff))
+#define SET_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfdffffff))
+#define SET_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfbffffff))
+#define SET_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_SYN_PFD_CHP)) & 0xf7ffffff))
+#define SET_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_PFD_CHP)) & 0xefffffff))
+#define SET_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_SYN_PFD_CHP)) & 0xdfffffff))
+#define SET_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_SYN_PFD_CHP)) & 0xbfffffff))
+#define SET_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffffff8))
+#define SET_RG_SX_VCORSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffffff07))
+#define SET_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffff0ff))
+#define SET_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffff0fff))
+#define SET_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfff0ffff))
+#define SET_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xff0fffff))
+#define SET_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xf0ffffff))
+#define SET_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_VCO_LOBF)) & 0x0fffffff))
+#define SET_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
+#define SET_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
+#define SET_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
+#define SET_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
+#define SET_RG_SX_XO_GM(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
+#define SET_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
+#define SET_RG_SX_LCKEN(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
+#define SET_RG_SX_PREVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
+#define SET_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
+#define SET_RG_SX_PH(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffdfff))
+#define SET_RG_SX_PL(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffbfff))
+#define SET_RG_XOSC_CBANK_XO(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xfff87fff))
+#define SET_RG_XOSC_CBANK_XI(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xff87ffff))
+#define SET_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffffe))
+#define SET_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 1) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffff9))
+#define SET_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffe7))
+#define SET_RG_SX_VT_SET(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffdf))
+#define SET_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 6) | ((REG32(ADR_SYN_LCK_VT)) & 0xffff803f))
+#define SET_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffffe))
+#define SET_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffff9))
+#define SET_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffffe7))
+#define SET_RG_DP_CK320BY2(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffbfff))
+#define SET_RG_DP_OD_TEST(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffdfffff))
+#define SET_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
+#define SET_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
+#define SET_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
+#define SET_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
+#define SET_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
+#define SET_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
+#define SET_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
+#define SET_RG_DP_RP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
+#define SET_RG_DP_RHP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
+#define SET_RG_DP_BBPLL_SDM_EDGE(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x7fffffff))
+#define SET_RG_DP_FODIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xfff80fff))
+#define SET_RG_DP_REFDIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xe03fffff))
+#define SET_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
+#define SET_RG_DP_BBPLL_BS(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 24) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xc0ffffff))
+#define SET_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
+#define SET_RG_EN_RCAL(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffe))
+#define SET_RG_RCAL_SPD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffd))
+#define SET_RG_RCAL_TMR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffe03))
+#define SET_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffdff))
+#define SET_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RCAL_REGISTER)) & 0xffff83ff))
+#define SET_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfffffffe))
+#define SET_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 1) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffffff01))
+#define SET_RG_SX_LCK_BIN_OFFSET(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff87fff))
+#define SET_RG_SX_LCK_BIN_PRECISION(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 19) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff7ffff))
+#define SET_RG_SX_LOCK_EN_N(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 20) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffefffff))
+#define SET_RG_SX_LOCK_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 21) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffdfffff))
+#define SET_RG_SX_SUB_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 22) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffbfffff))
+#define SET_RG_SX_SUB_SEL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xc07fffff))
+#define SET_RG_SX_MUX_SEL_VTH_BINL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 30) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xbfffffff))
+#define SET_RG_TRX_DUMMMY(_VAL_) (REG32(ADR_TRX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_DUMMY_REGISTER)) & 0x00000000))
+#define SET_RG_SX_DUMMMY(_VAL_) (REG32(ADR_SX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_DUMMY_REGISTER)) & 0x00000000))
+#define SET_RCAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
+#define SET_LCK_BIN_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
+#define SET_VT_MON_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
+#define SET_DA_R_CODE_LUT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
+#define SET_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
+#define SET_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
+#define SET_RTC_CAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 15) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff7fff))
+#define SET_RG_SARADC_BIT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 16) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffc0ffff))
+#define SET_SAR_ADC_FSM_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 22) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffbfffff))
+#define SET_AD_CIRCUIT_VERSION(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 23) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xf87fffff))
+#define SET_DA_R_CAL_CODE(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
+#define SET_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
+#define SET_RG_DPL_RFCTRL_CH(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xfffff800))
+#define SET_RG_RSSIADC_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 11) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xffff87ff))
+#define SET_RG_RX_ADC_I_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xff807fff))
+#define SET_RG_RX_ADC_Q_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x807fffff))
+#define SET_RG_DPL_RFCTRL_F(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0xff000000))
+#define SET_RG_SX_TARGET_CNT(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0xffffe000))
+#define SET_RG_RTC_OFFSET(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 0) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xffffff00))
+#define SET_RG_RTC_CAL_TARGET_COUNT(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 8) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xfff000ff))
+#define SET_RG_RF_D_REG(_VAL_) (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0xffff0000))
+#define SET_DIRECT_MODE(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffe))
+#define SET_TAG_INTERLEAVE_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffd))
+#define SET_DIS_DEMAND(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffb))
+#define SET_SAME_ID_ALLOC_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_MMU_CTRL)) & 0xfffffff7))
+#define SET_HS_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_MMU_CTRL)) & 0xffffffef))
+#define SET_SRAM_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 5) | ((REG32(ADR_MMU_CTRL)) & 0xffffffdf))
+#define SET_NOHIT_RPASS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 6) | ((REG32(ADR_MMU_CTRL)) & 0xffffffbf))
+#define SET_DMN_FLAG_CLR(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_MMU_CTRL)) & 0xffffff7f))
+#define SET_ERR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_CTRL)) & 0xfffffeff))
+#define SET_ALR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_MMU_CTRL)) & 0xfffffdff))
+#define SET_MCH_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_MMU_CTRL)) & 0xfffffbff))
+#define SET_TAG_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_MMU_CTRL)) & 0xfffff7ff))
+#define SET_ABT_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_CTRL)) & 0xffffefff))
+#define SET_MMU_VER(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_MMU_CTRL)) & 0xffff1fff))
+#define SET_MMU_SHARE_MCU(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_CTRL)) & 0xff00ffff))
+#define SET_HS_WR(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_HS_CTRL)) & 0xfffffffe))
+#define SET_HS_FLAG(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_HS_CTRL)) & 0xffffffef))
+#define SET_HS_ID(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_HS_CTRL)) & 0xffff80ff))
+#define SET_HS_CHANNEL(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_HS_CTRL)) & 0xfff0ffff))
+#define SET_HS_PAGE(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 20) | ((REG32(ADR_HS_CTRL)) & 0xff0fffff))
+#define SET_HS_DATA(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 24) | ((REG32(ADR_HS_CTRL)) & 0x00ffffff))
+#define SET_CPU_POR0(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR0_7)) & 0xfffffff0))
+#define SET_CPU_POR1(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR0_7)) & 0xffffff0f))
+#define SET_CPU_POR2(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR0_7)) & 0xfffff0ff))
+#define SET_CPU_POR3(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR0_7)) & 0xffff0fff))
+#define SET_CPU_POR4(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR0_7)) & 0xfff0ffff))
+#define SET_CPU_POR5(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR0_7)) & 0xff0fffff))
+#define SET_CPU_POR6(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR0_7)) & 0xf0ffffff))
+#define SET_CPU_POR7(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR0_7)) & 0x0fffffff))
+#define SET_CPU_POR8(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR8_F)) & 0xfffffff0))
+#define SET_CPU_POR9(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR8_F)) & 0xffffff0f))
+#define SET_CPU_PORA(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR8_F)) & 0xfffff0ff))
+#define SET_CPU_PORB(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR8_F)) & 0xffff0fff))
+#define SET_CPU_PORC(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR8_F)) & 0xfff0ffff))
+#define SET_CPU_PORD(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR8_F)) & 0xff0fffff))
+#define SET_CPU_PORE(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR8_F)) & 0xf0ffffff))
+#define SET_CPU_PORF(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR8_F)) & 0x0fffffff))
+#define SET_ACC_WR_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffffc0))
+#define SET_ACC_RD_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffc0ff))
+#define SET_REQ_NACK_CLR(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 15) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffff7fff))
+#define SET_NACK_FLAG_BUS(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_REG_LEN_CTRL)) & 0x0000ffff))
+#define SET_DMN_R_PASS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xffff0000))
+#define SET_PARA_ALC_RLS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfffeffff))
+#define SET_REQ_PORNS_CHGEN(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 24) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfeffffff))
+#define SET_ALC_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffffff80))
+#define SET_ALC_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffff7fff))
+#define SET_RLS_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xff80ffff))
+#define SET_RLS_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_RLS_ABORT)) & 0x7fffffff))
+#define SET_DEBUG_CTL(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_CTL)) & 0xffffff00))
+#define SET_DEBUG_H16(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_DEBUG_CTL)) & 0xfffffeff))
+#define SET_DEBUG_OUT(_VAL_) (REG32(ADR_DEBUG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_OUT)) & 0x00000000))
+#define SET_ALC_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffe))
+#define SET_RLS_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffd))
+#define SET_AL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_STATUS)) & 0xfffff8ff))
+#define SET_RL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_STATUS)) & 0xffff8fff))
+#define SET_ALC_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_STATUS)) & 0xff80ffff))
+#define SET_RLS_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MMU_STATUS)) & 0x80ffffff))
+#define SET_DMN_NOHIT_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffe))
+#define SET_DMN_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffd))
+#define SET_DMN_WR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_STATUS)) & 0xfffffff7))
+#define SET_DMN_PORT(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_STATUS)) & 0xffffff0f))
+#define SET_DMN_NHIT_ID(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_STATUS)) & 0xffff80ff))
+#define SET_DMN_NHIT_ADDR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_STATUS)) & 0x0000ffff))
+#define SET_TX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_STATUS)) & 0xffffff00))
+#define SET_RX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TAG_STATUS)) & 0xffff00ff))
+#define SET_AVA_TAG(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_STATUS)) & 0xfe00ffff))
+#define SET_PKTBUF_FULL(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 31) | ((REG32(ADR_TAG_STATUS)) & 0x7fffffff))
+#define SET_DMN_NOHIT_MCU(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffe))
+#define SET_DMN_MCU_FLAG(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffd))
+#define SET_DMN_MCU_WR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffff7))
+#define SET_DMN_MCU_PORT(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffffff0f))
+#define SET_DMN_MCU_ID(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffff80ff))
+#define SET_DMN_MCU_ADDR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_MCU_STATUS)) & 0x0000ffff))
+#define SET_MB_IDTBL_31_0(_VAL_) (REG32(ADR_MB_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_0_STATUS)) & 0x00000000))
+#define SET_MB_IDTBL_63_32(_VAL_) (REG32(ADR_MB_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_1_STATUS)) & 0x00000000))
+#define SET_MB_IDTBL_95_64(_VAL_) (REG32(ADR_MB_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_2_STATUS)) & 0x00000000))
+#define SET_MB_IDTBL_127_96(_VAL_) (REG32(ADR_MB_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_3_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_31_0(_VAL_) (REG32(ADR_PKT_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_63_32(_VAL_) (REG32(ADR_PKT_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_95_64(_VAL_) (REG32(ADR_PKT_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_127_96(_VAL_) (REG32(ADR_PKT_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_31_0(_VAL_) (REG32(ADR_DMN_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_63_32(_VAL_) (REG32(ADR_DMN_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_95_64(_VAL_) (REG32(ADR_DMN_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_127_96(_VAL_) (REG32(ADR_DMN_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_31_0(_VAL_) (REG32(ADR_MB_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_0_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_63_32(_VAL_) (REG32(ADR_MB_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_1_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_95_64(_VAL_) (REG32(ADR_MB_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_2_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_127_96(_VAL_) (REG32(ADR_MB_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_3_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_31_0(_VAL_) (REG32(ADR_PKT_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_0_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_63_32(_VAL_) (REG32(ADR_PKT_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_1_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_95_64(_VAL_) (REG32(ADR_PKT_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_2_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_127_96(_VAL_) (REG32(ADR_PKT_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_3_STATUS)) & 0x00000000))
+#define SET_ALC_NOCHG_ID(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffffff80))
+#define SET_ALC_NOCHG_INT(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffff7fff))
+#define SET_NEQ_PKT_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfffeffff))
+#define SET_NEQ_MB_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfeffffff))
+#define SET_SRAM_TAG_0(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000))
+#define SET_SRAM_TAG_1(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff))
+#define SET_SRAM_TAG_2(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000))
+#define SET_SRAM_TAG_3(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff))
+#define SET_SRAM_TAG_4(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000))
+#define SET_SRAM_TAG_5(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff))
+#define SET_SRAM_TAG_6(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000))
+#define SET_SRAM_TAG_7(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff))
+#define SET_SRAM_TAG_8(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000))
+#define SET_SRAM_TAG_9(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff))
+#define SET_SRAM_TAG_10(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000))
+#define SET_SRAM_TAG_11(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff))
+#define SET_SRAM_TAG_12(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000))
+#define SET_SRAM_TAG_13(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff))
+#define SET_SRAM_TAG_14(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000))
+#define SET_SRAM_TAG_15(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff))
+#define DEF_BRG_SW_RST() (REG32(ADR_BRG_SW_RST)) = (0x00000000)
+#define DEF_BOOT() (REG32(ADR_BOOT)) = (0x00040000)
+#define DEF_CHIP_ID_0() (REG32(ADR_CHIP_ID_0)) = (0x31333131)
+#define DEF_CHIP_ID_1() (REG32(ADR_CHIP_ID_1)) = (0x322d3230)
+#define DEF_CHIP_ID_2() (REG32(ADR_CHIP_ID_2)) = (0x32303041)
+#define DEF_CHIP_ID_3() (REG32(ADR_CHIP_ID_3)) = (0x53535636)
+#define DEF_CLOCK_SELECTION() (REG32(ADR_CLOCK_SELECTION)) = (0x00000000)
+#define DEF_PLATFORM_CLOCK_ENABLE() (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (0x008fffff)
+#define DEF_SYS_CSR_CLOCK_ENABLE() (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (0x00000400)
+#define DEF_MCU_DBG_SEL() (REG32(ADR_MCU_DBG_SEL)) = (0x00000000)
+#define DEF_MCU_DBG_DATA() (REG32(ADR_MCU_DBG_DATA)) = (0x00000000)
+#define DEF_AHB_BRG_STATUS() (REG32(ADR_AHB_BRG_STATUS)) = (0x00000000)
+#define DEF_BIST_BIST_CTRL() (REG32(ADR_BIST_BIST_CTRL)) = (0x00000000)
+#define DEF_BIST_MODE_REG_IN() (REG32(ADR_BIST_MODE_REG_IN)) = (0x001ffe3e)
+#define DEF_BIST_MODE_REG_OUT() (REG32(ADR_BIST_MODE_REG_OUT)) = (0x00000000)
+#define DEF_BIST_MONITOR_BUS_LSB() (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (0x00000000)
+#define DEF_BIST_MONITOR_BUS_MSB() (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (0x00000000)
+#define DEF_TB_ADR_SEL() (REG32(ADR_TB_ADR_SEL)) = (0x00000000)
+#define DEF_TB_RDATA() (REG32(ADR_TB_RDATA)) = (0x00000000)
+#define DEF_UART_W2B() (REG32(ADR_UART_W2B)) = (0x00000000)
+#define DEF_AHB_ILL_ADDR() (REG32(ADR_AHB_ILL_ADDR)) = (0x00000000)
+#define DEF_AHB_FEN_ADDR() (REG32(ADR_AHB_FEN_ADDR)) = (0x00000000)
+#define DEF_AHB_ILLFEN_STATUS() (REG32(ADR_AHB_ILLFEN_STATUS)) = (0x00000000)
+#define DEF_PWM_A() (REG32(ADR_PWM_A)) = (0x400a1010)
+#define DEF_PWM_B() (REG32(ADR_PWM_B)) = (0x400a1010)
+#define DEF_HBUSREQ_LOCK() (REG32(ADR_HBUSREQ_LOCK)) = (0x00001ffd)
+#define DEF_HBURST_LOCK() (REG32(ADR_HBURST_LOCK)) = (0x00000000)
+#define DEF_PRESCALER_USTIMER() (REG32(ADR_PRESCALER_USTIMER)) = (0x00000028)
+#define DEF_BIST_MODE_REG_IN_MMU() (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (0x0000fe3e)
+#define DEF_BIST_MODE_REG_OUT_MMU() (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (0x00000000)
+#define DEF_BIST_MONITOR_BUS_MMU() (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (0x00000000)
+#define DEF_TEST_MODE() (REG32(ADR_TEST_MODE)) = (0x00000000)
+#define DEF_BOOT_INFO() (REG32(ADR_BOOT_INFO)) = (0x00000000)
+#define DEF_SD_INIT_CFG() (REG32(ADR_SD_INIT_CFG)) = (0x00000000)
+#define DEF_SPARE_UART_INFO() (REG32(ADR_SPARE_UART_INFO)) = (0x00000000)
+#define DEF_TU0_MICROSECOND_TIMER() (REG32(ADR_TU0_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU0_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU0_DUMMY_BIT_0() (REG32(ADR_TU0_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU0_DUMMY_BIT_1() (REG32(ADR_TU0_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TU1_MICROSECOND_TIMER() (REG32(ADR_TU1_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU1_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU1_DUMMY_BIT_0() (REG32(ADR_TU1_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU1_DUMMY_BIT_1() (REG32(ADR_TU1_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TU2_MICROSECOND_TIMER() (REG32(ADR_TU2_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU2_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU2_DUMMY_BIT_0() (REG32(ADR_TU2_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU2_DUMMY_BIT_1() (REG32(ADR_TU2_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TU3_MICROSECOND_TIMER() (REG32(ADR_TU3_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU3_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU3_DUMMY_BIT_0() (REG32(ADR_TU3_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU3_DUMMY_BIT_1() (REG32(ADR_TU3_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM0_MILISECOND_TIMER() (REG32(ADR_TM0_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM0_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM0_DUMMY_BIT_0() (REG32(ADR_TM0_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM0_DUMMY_BIT_1() (REG32(ADR_TM0_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM1_MILISECOND_TIMER() (REG32(ADR_TM1_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM1_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM1_DUMMY_BIT_0() (REG32(ADR_TM1_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM1_DUMMY_BIT_1() (REG32(ADR_TM1_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM2_MILISECOND_TIMER() (REG32(ADR_TM2_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM2_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM2_DUMMY_BIT_0() (REG32(ADR_TM2_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM2_DUMMY_BIT_1() (REG32(ADR_TM2_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM3_MILISECOND_TIMER() (REG32(ADR_TM3_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM3_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM3_DUMMY_BIT_0() (REG32(ADR_TM3_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM3_DUMMY_BIT_1() (REG32(ADR_TM3_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_MCU_WDOG_REG() (REG32(ADR_MCU_WDOG_REG)) = (0x00000000)
+#define DEF_SYS_WDOG_REG() (REG32(ADR_SYS_WDOG_REG)) = (0x00000000)
+#define DEF_PAD6() (REG32(ADR_PAD6)) = (0x00000008)
+#define DEF_PAD7() (REG32(ADR_PAD7)) = (0x00000008)
+#define DEF_PAD8() (REG32(ADR_PAD8)) = (0x00000008)
+#define DEF_PAD9() (REG32(ADR_PAD9)) = (0x00000008)
+#define DEF_PAD11() (REG32(ADR_PAD11)) = (0x00000008)
+#define DEF_PAD15() (REG32(ADR_PAD15)) = (0x0000000a)
+#define DEF_PAD16() (REG32(ADR_PAD16)) = (0x0000000a)
+#define DEF_PAD17() (REG32(ADR_PAD17)) = (0x0000000a)
+#define DEF_PAD18() (REG32(ADR_PAD18)) = (0x0000000a)
+#define DEF_PAD19() (REG32(ADR_PAD19)) = (0x00007000)
+#define DEF_PAD20() (REG32(ADR_PAD20)) = (0x0000000a)
+#define DEF_PAD21() (REG32(ADR_PAD21)) = (0x0000000a)
+#define DEF_PAD22() (REG32(ADR_PAD22)) = (0x00000009)
+#define DEF_PAD24() (REG32(ADR_PAD24)) = (0x00000008)
+#define DEF_PAD25() (REG32(ADR_PAD25)) = (0x0000000b)
+#define DEF_PAD27() (REG32(ADR_PAD27)) = (0x00000008)
+#define DEF_PAD28() (REG32(ADR_PAD28)) = (0x00000008)
+#define DEF_PAD29() (REG32(ADR_PAD29)) = (0x00000009)
+#define DEF_PAD30() (REG32(ADR_PAD30)) = (0x0000000a)
+#define DEF_PAD31() (REG32(ADR_PAD31)) = (0x0000000a)
+#define DEF_PAD32() (REG32(ADR_PAD32)) = (0x0000000a)
+#define DEF_PAD33() (REG32(ADR_PAD33)) = (0x0000000a)
+#define DEF_PAD34() (REG32(ADR_PAD34)) = (0x0000000a)
+#define DEF_PAD42() (REG32(ADR_PAD42)) = (0x0000000a)
+#define DEF_PAD43() (REG32(ADR_PAD43)) = (0x0000000a)
+#define DEF_PAD44() (REG32(ADR_PAD44)) = (0x0000000a)
+#define DEF_PAD45() (REG32(ADR_PAD45)) = (0x0000000a)
+#define DEF_PAD46() (REG32(ADR_PAD46)) = (0x0000000a)
+#define DEF_PAD47() (REG32(ADR_PAD47)) = (0x00100000)
+#define DEF_PAD48() (REG32(ADR_PAD48)) = (0x00100808)
+#define DEF_PAD49() (REG32(ADR_PAD49)) = (0x00100008)
+#define DEF_PAD50() (REG32(ADR_PAD50)) = (0x00100008)
+#define DEF_PAD51() (REG32(ADR_PAD51)) = (0x00100008)
+#define DEF_PAD52() (REG32(ADR_PAD52)) = (0x00100000)
+#define DEF_PAD53() (REG32(ADR_PAD53)) = (0x0000000a)
+#define DEF_PAD54() (REG32(ADR_PAD54)) = (0x00000000)
+#define DEF_PAD56() (REG32(ADR_PAD56)) = (0x00000000)
+#define DEF_PAD57() (REG32(ADR_PAD57)) = (0x00000008)
+#define DEF_PAD58() (REG32(ADR_PAD58)) = (0x0000000a)
+#define DEF_PAD59() (REG32(ADR_PAD59)) = (0x0000000a)
+#define DEF_PAD60() (REG32(ADR_PAD60)) = (0x0000000a)
+#define DEF_PAD61() (REG32(ADR_PAD61)) = (0x0000000a)
+#define DEF_PAD62() (REG32(ADR_PAD62)) = (0x0000000a)
+#define DEF_PAD64() (REG32(ADR_PAD64)) = (0x00000009)
+#define DEF_PAD65() (REG32(ADR_PAD65)) = (0x00000009)
+#define DEF_PAD66() (REG32(ADR_PAD66)) = (0x00000008)
+#define DEF_PAD68() (REG32(ADR_PAD68)) = (0x00000008)
+#define DEF_PAD67() (REG32(ADR_PAD67)) = (0x00000159)
+#define DEF_PAD69() (REG32(ADR_PAD69)) = (0x0000000b)
+#define DEF_PAD70() (REG32(ADR_PAD70)) = (0x00000008)
+#define DEF_PAD231() (REG32(ADR_PAD231)) = (0x00000008)
+#define DEF_PIN_SEL_0() (REG32(ADR_PIN_SEL_0)) = (0x00000000)
+#define DEF_PIN_SEL_1() (REG32(ADR_PIN_SEL_1)) = (0x00000000)
+#define DEF_IO_PORT_REG() (REG32(ADR_IO_PORT_REG)) = (0x00010000)
+#define DEF_INT_MASK_REG() (REG32(ADR_INT_MASK_REG)) = (0x000000ff)
+#define DEF_INT_STATUS_REG() (REG32(ADR_INT_STATUS_REG)) = (0x00000000)
+#define DEF_FN1_STATUS_REG() (REG32(ADR_FN1_STATUS_REG)) = (0x00000000)
+#define DEF_CARD_PKT_STATUS_TEST() (REG32(ADR_CARD_PKT_STATUS_TEST)) = (0x00000000)
+#define DEF_SYSTEM_INFORMATION_REG() (REG32(ADR_SYSTEM_INFORMATION_REG)) = (0x00000000)
+#define DEF_CARD_RCA_REG() (REG32(ADR_CARD_RCA_REG)) = (0x00000000)
+#define DEF_SDIO_FIFO_WR_THLD_REG() (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (0x00000000)
+#define DEF_SDIO_FIFO_WR_LIMIT_REG() (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (0x00000000)
+#define DEF_SDIO_TX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_THLD_FOR_CMD53RD_REG() (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (0x00000000)
+#define DEF_SDIO_RX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_LOG_START_END_DATA_REG() (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (0x00000000)
+#define DEF_SDIO_BYTE_MODE_BATCH_SIZE_REG() (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_LAST_CMD_INDEX_CRC_REG() (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (0x00000000)
+#define DEF_SDIO_LAST_CMD_ARG_REG() (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (0x00000000)
+#define DEF_SDIO_BUS_STATE_DEBUG_MONITOR() (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (0x00000000)
+#define DEF_SDIO_CARD_STATUS_REG() (REG32(ADR_SDIO_CARD_STATUS_REG)) = (0x00000000)
+#define DEF_R5_RESP_FLAG_OUT_TIMING() (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (0x00000000)
+#define DEF_CMD52_DATA_FOR_LAST_TIME() (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (0x00000000)
+#define DEF_FN1_DMA_START_ADDR_REG() (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (0x00000000)
+#define DEF_FN1_INT_CTRL_RESET() (REG32(ADR_FN1_INT_CTRL_RESET)) = (0x00000000)
+#define DEF_IO_REG_PORT_REG() (REG32(ADR_IO_REG_PORT_REG)) = (0x00010020)
+#define DEF_SDIO_FIFO_ERROR_CNT() (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (0x00000000)
+#define DEF_SDIO_CRC7_CRC16_ERROR_REG() (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (0x00000000)
+#define DEF_SDIO_BLOCK_CNT_INFO() (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (0x00000000)
+#define DEF_RX_DATA_CMD52_ABORT_COUNT() (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (0x00000000)
+#define DEF_FIFO_PTR_READ_BLOCK_CNT() (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (0x00000000)
+#define DEF_TX_TIME_OUT_READ_CTRL() (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (0x00000000)
+#define DEF_SDIO_TX_ALLOC_REG() (REG32(ADR_SDIO_TX_ALLOC_REG)) = (0x00000000)
+#define DEF_SDIO_TX_INFORM() (REG32(ADR_SDIO_TX_INFORM)) = (0x00000000)
+#define DEF_F1_BLOCK_SIZE_0_REG() (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (0x00000000)
+#define DEF_SDIO_COMMAND_LOG_DATA_31_0() (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (0x000000ec)
+#define DEF_SDIO_COMMAND_LOG_DATA_63_32() (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (0xce000000)
+#define DEF_SYSTEM_INFORMATION_REGISTER() (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (0x00000000)
+#define DEF_CCCR_00H_REG() (REG32(ADR_CCCR_00H_REG)) = (0x00000000)
+#define DEF_CCCR_04H_REG() (REG32(ADR_CCCR_04H_REG)) = (0x00000000)
+#define DEF_CCCR_08H_REG() (REG32(ADR_CCCR_08H_REG)) = (0x00000000)
+#define DEF_CCCR_13H_REG() (REG32(ADR_CCCR_13H_REG)) = (0x00000000)
+#define DEF_FBR_100H_REG() (REG32(ADR_FBR_100H_REG)) = (0x00000000)
+#define DEF_FBR_109H_REG() (REG32(ADR_FBR_109H_REG)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_0() (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_1() (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_2() (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_3() (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_4() (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_5() (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_6() (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_7() (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_8() (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_9() (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_10() (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_11() (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_12() (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_13() (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_14() (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_15() (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_0() (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_1() (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_2() (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_3() (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_4() (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_5() (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_6() (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_7() (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_8() (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_9() (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_10() (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_11() (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_12() (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_13() (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_14() (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_15() (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (0x00000000)
+#define DEF_SPI_MODE() (REG32(ADR_SPI_MODE)) = (0x00000000)
+#define DEF_RX_QUOTA() (REG32(ADR_RX_QUOTA)) = (0x00000000)
+#define DEF_CONDITION_NUMBER() (REG32(ADR_CONDITION_NUMBER)) = (0x00000004)
+#define DEF_HOST_PATH() (REG32(ADR_HOST_PATH)) = (0x00000001)
+#define DEF_TX_SEG() (REG32(ADR_TX_SEG)) = (0x00000000)
+#define DEF_DEBUG_BURST_MODE() (REG32(ADR_DEBUG_BURST_MODE)) = (0x00000000)
+#define DEF_SPI_TO_PHY_PARAM1() (REG32(ADR_SPI_TO_PHY_PARAM1)) = (0x000e0006)
+#define DEF_SPI_TO_PHY_PARAM2() (REG32(ADR_SPI_TO_PHY_PARAM2)) = (0x000e000e)
+#define DEF_SPI_STS() (REG32(ADR_SPI_STS)) = (0x00000000)
+#define DEF_TX_ALLOC_SET() (REG32(ADR_TX_ALLOC_SET)) = (0x00000000)
+#define DEF_TX_ALLOC() (REG32(ADR_TX_ALLOC)) = (0x00000000)
+#define DEF_DBG_CNT() (REG32(ADR_DBG_CNT)) = (0x00000000)
+#define DEF_DBG_CNT2() (REG32(ADR_DBG_CNT2)) = (0x00000000)
+#define DEF_DBG_CNT3() (REG32(ADR_DBG_CNT3)) = (0x00000000)
+#define DEF_DBG_CNT4() (REG32(ADR_DBG_CNT4)) = (0x00000000)
+#define DEF_INT_TAG() (REG32(ADR_INT_TAG)) = (0x00000000)
+#define DEF_I2CM_EN() (REG32(ADR_I2CM_EN)) = (0x00000074)
+#define DEF_I2CM_DEV_A() (REG32(ADR_I2CM_DEV_A)) = (0x00008000)
+#define DEF_I2CM_LEN() (REG32(ADR_I2CM_LEN)) = (0x00000000)
+#define DEF_I2CM_WDAT() (REG32(ADR_I2CM_WDAT)) = (0x00000000)
+#define DEF_I2CM_RDAT() (REG32(ADR_I2CM_RDAT)) = (0x00000000)
+#define DEF_I2CM_EN_2() (REG32(ADR_I2CM_EN_2)) = (0x00010000)
+#define DEF_UART_DATA() (REG32(ADR_UART_DATA)) = (0x00000000)
+#define DEF_UART_IER() (REG32(ADR_UART_IER)) = (0x00000000)
+#define DEF_UART_FCR() (REG32(ADR_UART_FCR)) = (0x00000001)
+#define DEF_UART_LCR() (REG32(ADR_UART_LCR)) = (0x00000003)
+#define DEF_UART_MCR() (REG32(ADR_UART_MCR)) = (0x00000000)
+#define DEF_UART_LSR() (REG32(ADR_UART_LSR)) = (0x00000000)
+#define DEF_UART_MSR() (REG32(ADR_UART_MSR)) = (0x00000000)
+#define DEF_UART_SPR() (REG32(ADR_UART_SPR)) = (0x00000000)
+#define DEF_UART_RTHR() (REG32(ADR_UART_RTHR)) = (0x000000c8)
+#define DEF_UART_ISR() (REG32(ADR_UART_ISR)) = (0x000000c1)
+#define DEF_DAT_UART_DATA() (REG32(ADR_DAT_UART_DATA)) = (0x00000000)
+#define DEF_DAT_UART_IER() (REG32(ADR_DAT_UART_IER)) = (0x00000000)
+#define DEF_DAT_UART_FCR() (REG32(ADR_DAT_UART_FCR)) = (0x00000001)
+#define DEF_DAT_UART_LCR() (REG32(ADR_DAT_UART_LCR)) = (0x00000003)
+#define DEF_DAT_UART_MCR() (REG32(ADR_DAT_UART_MCR)) = (0x00000000)
+#define DEF_DAT_UART_LSR() (REG32(ADR_DAT_UART_LSR)) = (0x00000000)
+#define DEF_DAT_UART_MSR() (REG32(ADR_DAT_UART_MSR)) = (0x00000000)
+#define DEF_DAT_UART_SPR() (REG32(ADR_DAT_UART_SPR)) = (0x00000000)
+#define DEF_DAT_UART_RTHR() (REG32(ADR_DAT_UART_RTHR)) = (0x000000c8)
+#define DEF_DAT_UART_ISR() (REG32(ADR_DAT_UART_ISR)) = (0x000000c1)
+#define DEF_INT_MASK() (REG32(ADR_INT_MASK)) = (0xffffffff)
+#define DEF_INT_MODE() (REG32(ADR_INT_MODE)) = (0x00000000)
+#define DEF_INT_IRQ_STS() (REG32(ADR_INT_IRQ_STS)) = (0x00000000)
+#define DEF_INT_FIQ_STS() (REG32(ADR_INT_FIQ_STS)) = (0x00000000)
+#define DEF_INT_IRQ_RAW() (REG32(ADR_INT_IRQ_RAW)) = (0x00000000)
+#define DEF_INT_FIQ_RAW() (REG32(ADR_INT_FIQ_RAW)) = (0x00000000)
+#define DEF_INT_PERI_MASK() (REG32(ADR_INT_PERI_MASK)) = (0xffffffff)
+#define DEF_INT_PERI_STS() (REG32(ADR_INT_PERI_STS)) = (0x00000000)
+#define DEF_INT_PERI_RAW() (REG32(ADR_INT_PERI_RAW)) = (0x00000000)
+#define DEF_INT_GPI_CFG() (REG32(ADR_INT_GPI_CFG)) = (0x00000000)
+#define DEF_SYS_INT_FOR_HOST() (REG32(ADR_SYS_INT_FOR_HOST)) = (0x00000001)
+#define DEF_SPI_IPC() (REG32(ADR_SPI_IPC)) = (0x00000000)
+#define DEF_SDIO_IPC() (REG32(ADR_SDIO_IPC)) = (0x00000000)
+#define DEF_SDIO_MASK() (REG32(ADR_SDIO_MASK)) = (0xffffffff)
+#define DEF_SDIO_IRQ_STS() (REG32(ADR_SDIO_IRQ_STS)) = (0x00000000)
+#define DEF_SD_PERI_MASK() (REG32(ADR_SD_PERI_MASK)) = (0xffffffff)
+#define DEF_SD_PERI_STS() (REG32(ADR_SD_PERI_STS)) = (0x00000000)
+#define DEF_DBG_SPI_MODE() (REG32(ADR_DBG_SPI_MODE)) = (0x00000000)
+#define DEF_DBG_RX_QUOTA() (REG32(ADR_DBG_RX_QUOTA)) = (0x00000000)
+#define DEF_DBG_CONDITION_NUMBER() (REG32(ADR_DBG_CONDITION_NUMBER)) = (0x00000004)
+#define DEF_DBG_HOST_PATH() (REG32(ADR_DBG_HOST_PATH)) = (0x00000001)
+#define DEF_DBG_TX_SEG() (REG32(ADR_DBG_TX_SEG)) = (0x00000000)
+#define DEF_DBG_DEBUG_BURST_MODE() (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (0x00000000)
+#define DEF_DBG_SPI_TO_PHY_PARAM1() (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (0x000e0006)
+#define DEF_DBG_SPI_TO_PHY_PARAM2() (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (0x000e000e)
+#define DEF_DBG_SPI_STS() (REG32(ADR_DBG_SPI_STS)) = (0x00000000)
+#define DEF_DBG_TX_ALLOC_SET() (REG32(ADR_DBG_TX_ALLOC_SET)) = (0x00000000)
+#define DEF_DBG_TX_ALLOC() (REG32(ADR_DBG_TX_ALLOC)) = (0x00000000)
+#define DEF_DBG_DBG_CNT() (REG32(ADR_DBG_DBG_CNT)) = (0x00000000)
+#define DEF_DBG_DBG_CNT2() (REG32(ADR_DBG_DBG_CNT2)) = (0x00000000)
+#define DEF_DBG_DBG_CNT3() (REG32(ADR_DBG_DBG_CNT3)) = (0x00000000)
+#define DEF_DBG_DBG_CNT4() (REG32(ADR_DBG_DBG_CNT4)) = (0x00000000)
+#define DEF_DBG_INT_TAG() (REG32(ADR_DBG_INT_TAG)) = (0x00000000)
+#define DEF_BOOT_ADDR() (REG32(ADR_BOOT_ADDR)) = (0x00000000)
+#define DEF_VERIFY_DATA() (REG32(ADR_VERIFY_DATA)) = (0x5e11aa11)
+#define DEF_FLASH_ADDR() (REG32(ADR_FLASH_ADDR)) = (0x00000000)
+#define DEF_SRAM_ADDR() (REG32(ADR_SRAM_ADDR)) = (0x00000000)
+#define DEF_LEN() (REG32(ADR_LEN)) = (0x00000000)
+#define DEF_SPI_PARAM() (REG32(ADR_SPI_PARAM)) = (0x000f000f)
+#define DEF_SPI_PARAM2() (REG32(ADR_SPI_PARAM2)) = (0x00040001)
+#define DEF_CHECK_SUM_RESULT() (REG32(ADR_CHECK_SUM_RESULT)) = (0x00000000)
+#define DEF_CHECK_SUM_IN_FILE() (REG32(ADR_CHECK_SUM_IN_FILE)) = (0x00000000)
+#define DEF_COMMAND_LEN() (REG32(ADR_COMMAND_LEN)) = (0x00000000)
+#define DEF_COMMAND_ADDR() (REG32(ADR_COMMAND_ADDR)) = (0x00000000)
+#define DEF_DMA_ADR_SRC() (REG32(ADR_DMA_ADR_SRC)) = (0x00000000)
+#define DEF_DMA_ADR_DST() (REG32(ADR_DMA_ADR_DST)) = (0x00000000)
+#define DEF_DMA_CTRL() (REG32(ADR_DMA_CTRL)) = (0x000000aa)
+#define DEF_DMA_INT() (REG32(ADR_DMA_INT)) = (0x00000001)
+#define DEF_DMA_FILL_CONST() (REG32(ADR_DMA_FILL_CONST)) = (0x00000000)
+#define DEF_PMU_0() (REG32(ADR_PMU_0)) = (0x0f000040)
+#define DEF_PMU_1() (REG32(ADR_PMU_1)) = (0x015d015d)
+#define DEF_PMU_2() (REG32(ADR_PMU_2)) = (0x00000000)
+#define DEF_PMU_3() (REG32(ADR_PMU_3)) = (0x55550000)
+#define DEF_RTC_1() (REG32(ADR_RTC_1)) = (0x7fff0000)
+#define DEF_RTC_2() (REG32(ADR_RTC_2)) = (0x00000003)
+#define DEF_RTC_3W() (REG32(ADR_RTC_3W)) = (0x00000000)
+#define DEF_RTC_3R() (REG32(ADR_RTC_3R)) = (0x00000000)
+#define DEF_RTC_4() (REG32(ADR_RTC_4)) = (0x00000000)
+#define DEF_D2_DMA_ADR_SRC() (REG32(ADR_D2_DMA_ADR_SRC)) = (0x00000000)
+#define DEF_D2_DMA_ADR_DST() (REG32(ADR_D2_DMA_ADR_DST)) = (0x00000000)
+#define DEF_D2_DMA_CTRL() (REG32(ADR_D2_DMA_CTRL)) = (0x000000aa)
+#define DEF_D2_DMA_INT() (REG32(ADR_D2_DMA_INT)) = (0x00000001)
+#define DEF_D2_DMA_FILL_CONST() (REG32(ADR_D2_DMA_FILL_CONST)) = (0x00000000)
+#define DEF_CONTROL() (REG32(ADR_CONTROL)) = (0x02700008)
+#define DEF_SDIO_WAKE_MODE() (REG32(ADR_SDIO_WAKE_MODE)) = (0x00000000)
+#define DEF_TX_FLOW_0() (REG32(ADR_TX_FLOW_0)) = (0x00000000)
+#define DEF_TX_FLOW_1() (REG32(ADR_TX_FLOW_1)) = (0x00000000)
+#define DEF_THREASHOLD() (REG32(ADR_THREASHOLD)) = (0x09000000)
+#define DEF_TXFID_INCREASE() (REG32(ADR_TXFID_INCREASE)) = (0x00000000)
+#define DEF_GLOBAL_SEQUENCE() (REG32(ADR_GLOBAL_SEQUENCE)) = (0x00000000)
+#define DEF_HCI_TX_RX_INFO_SIZE() (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (0x00040450)
+#define DEF_HCI_TX_INFO_CLEAR() (REG32(ADR_HCI_TX_INFO_CLEAR)) = (0x00000008)
+#define DEF_TX_ETHER_TYPE_0() (REG32(ADR_TX_ETHER_TYPE_0)) = (0x00000000)
+#define DEF_TX_ETHER_TYPE_1() (REG32(ADR_TX_ETHER_TYPE_1)) = (0x00000000)
+#define DEF_RX_ETHER_TYPE_0() (REG32(ADR_RX_ETHER_TYPE_0)) = (0x00000000)
+#define DEF_RX_ETHER_TYPE_1() (REG32(ADR_RX_ETHER_TYPE_1)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_0() (REG32(ADR_PACKET_COUNTER_INFO_0)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_1() (REG32(ADR_PACKET_COUNTER_INFO_1)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_2() (REG32(ADR_PACKET_COUNTER_INFO_2)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_3() (REG32(ADR_PACKET_COUNTER_INFO_3)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_4() (REG32(ADR_PACKET_COUNTER_INFO_4)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_5() (REG32(ADR_PACKET_COUNTER_INFO_5)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_6() (REG32(ADR_PACKET_COUNTER_INFO_6)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_7() (REG32(ADR_PACKET_COUNTER_INFO_7)) = (0x00000000)
+#define DEF_SDIO_TX_RX_FAIL_COUNTER_0() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (0x00000000)
+#define DEF_SDIO_TX_RX_FAIL_COUNTER_1() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_0() (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_1() (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_2() (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_3() (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_4() (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_5() (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_6() (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_7() (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_8() (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_9() (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_10() (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (0x00000000)
+#define DEF_CS_START_ADDR() (REG32(ADR_CS_START_ADDR)) = (0x00000000)
+#define DEF_CS_ADD_LEN() (REG32(ADR_CS_ADD_LEN)) = (0x00000000)
+#define DEF_CS_CMD() (REG32(ADR_CS_CMD)) = (0x00000000)
+#define DEF_CS_INI_BUF() (REG32(ADR_CS_INI_BUF)) = (0x00000000)
+#define DEF_CS_PSEUDO_BUF() (REG32(ADR_CS_PSEUDO_BUF)) = (0x00000000)
+#define DEF_CS_CHECK_SUM() (REG32(ADR_CS_CHECK_SUM)) = (0x00000000)
+#define DEF_RAND_EN() (REG32(ADR_RAND_EN)) = (0x00000000)
+#define DEF_RAND_NUM() (REG32(ADR_RAND_NUM)) = (0x00000000)
+#define DEF_MUL_OP1() (REG32(ADR_MUL_OP1)) = (0x00000000)
+#define DEF_MUL_OP2() (REG32(ADR_MUL_OP2)) = (0x00000000)
+#define DEF_MUL_ANS0() (REG32(ADR_MUL_ANS0)) = (0x00000000)
+#define DEF_MUL_ANS1() (REG32(ADR_MUL_ANS1)) = (0x00000000)
+#define DEF_DMA_RDATA() (REG32(ADR_DMA_RDATA)) = (0x00000000)
+#define DEF_DMA_WDATA() (REG32(ADR_DMA_WDATA)) = (0x00000000)
+#define DEF_DMA_LEN() (REG32(ADR_DMA_LEN)) = (0x00000000)
+#define DEF_DMA_CLR() (REG32(ADR_DMA_CLR)) = (0x00000000)
+#define DEF_NAV_DATA() (REG32(ADR_NAV_DATA)) = (0x00000000)
+#define DEF_CO_NAV() (REG32(ADR_CO_NAV)) = (0x00000000)
+#define DEF_SHA_DST_ADDR() (REG32(ADR_SHA_DST_ADDR)) = (0x00000000)
+#define DEF_SHA_SRC_ADDR() (REG32(ADR_SHA_SRC_ADDR)) = (0x00000000)
+#define DEF_SHA_SETTING() (REG32(ADR_SHA_SETTING)) = (0x00000002)
+#define DEF_EFUSE_CLK_FREQ() (REG32(ADR_EFUSE_CLK_FREQ)) = (0x610100d0)
+#define DEF_EFUSE_LDO_TIME() (REG32(ADR_EFUSE_LDO_TIME)) = (0x00020002)
+#define DEF_EFUSE_AHB_RDATA_0() (REG32(ADR_EFUSE_AHB_RDATA_0)) = (0x00000000)
+#define DEF_EFUSE_WDATA_0() (REG32(ADR_EFUSE_WDATA_0)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_1() (REG32(ADR_EFUSE_AHB_RDATA_1)) = (0x00000000)
+#define DEF_EFUSE_WDATA_1() (REG32(ADR_EFUSE_WDATA_1)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_2() (REG32(ADR_EFUSE_AHB_RDATA_2)) = (0x00000000)
+#define DEF_EFUSE_WDATA_2() (REG32(ADR_EFUSE_WDATA_2)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_3() (REG32(ADR_EFUSE_AHB_RDATA_3)) = (0x00000000)
+#define DEF_EFUSE_WDATA_3() (REG32(ADR_EFUSE_WDATA_3)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_4() (REG32(ADR_EFUSE_AHB_RDATA_4)) = (0x00000000)
+#define DEF_EFUSE_WDATA_4() (REG32(ADR_EFUSE_WDATA_4)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_5() (REG32(ADR_EFUSE_AHB_RDATA_5)) = (0x00000000)
+#define DEF_EFUSE_WDATA_5() (REG32(ADR_EFUSE_WDATA_5)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_6() (REG32(ADR_EFUSE_AHB_RDATA_6)) = (0x00000000)
+#define DEF_EFUSE_WDATA_6() (REG32(ADR_EFUSE_WDATA_6)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_7() (REG32(ADR_EFUSE_AHB_RDATA_7)) = (0x00000000)
+#define DEF_EFUSE_WDATA_7() (REG32(ADR_EFUSE_WDATA_7)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD0_EN() (REG32(ADR_EFUSE_SPI_RD0_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD1_EN() (REG32(ADR_EFUSE_SPI_RD1_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD2_EN() (REG32(ADR_EFUSE_SPI_RD2_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD3_EN() (REG32(ADR_EFUSE_SPI_RD3_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD4_EN() (REG32(ADR_EFUSE_SPI_RD4_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD5_EN() (REG32(ADR_EFUSE_SPI_RD5_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD6_EN() (REG32(ADR_EFUSE_SPI_RD6_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD7_EN() (REG32(ADR_EFUSE_SPI_RD7_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_BUSY() (REG32(ADR_EFUSE_SPI_BUSY)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_0() (REG32(ADR_EFUSE_SPI_RDATA_0)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_1() (REG32(ADR_EFUSE_SPI_RDATA_1)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_2() (REG32(ADR_EFUSE_SPI_RDATA_2)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_3() (REG32(ADR_EFUSE_SPI_RDATA_3)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_4() (REG32(ADR_EFUSE_SPI_RDATA_4)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_5() (REG32(ADR_EFUSE_SPI_RDATA_5)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_6() (REG32(ADR_EFUSE_SPI_RDATA_6)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_7() (REG32(ADR_EFUSE_SPI_RDATA_7)) = (0x00000000)
+#define DEF_SMS4_CFG1() (REG32(ADR_SMS4_CFG1)) = (0x00000002)
+#define DEF_SMS4_CFG2() (REG32(ADR_SMS4_CFG2)) = (0x00000000)
+#define DEF_SMS4_MODE1() (REG32(ADR_SMS4_MODE1)) = (0x00000000)
+#define DEF_SMS4_TRIG() (REG32(ADR_SMS4_TRIG)) = (0x00000000)
+#define DEF_SMS4_STATUS1() (REG32(ADR_SMS4_STATUS1)) = (0x00000000)
+#define DEF_SMS4_STATUS2() (REG32(ADR_SMS4_STATUS2)) = (0x00000000)
+#define DEF_SMS4_DATA_IN0() (REG32(ADR_SMS4_DATA_IN0)) = (0x00000000)
+#define DEF_SMS4_DATA_IN1() (REG32(ADR_SMS4_DATA_IN1)) = (0x00000000)
+#define DEF_SMS4_DATA_IN2() (REG32(ADR_SMS4_DATA_IN2)) = (0x00000000)
+#define DEF_SMS4_DATA_IN3() (REG32(ADR_SMS4_DATA_IN3)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT0() (REG32(ADR_SMS4_DATA_OUT0)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT1() (REG32(ADR_SMS4_DATA_OUT1)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT2() (REG32(ADR_SMS4_DATA_OUT2)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT3() (REG32(ADR_SMS4_DATA_OUT3)) = (0x00000000)
+#define DEF_SMS4_KEY_0() (REG32(ADR_SMS4_KEY_0)) = (0x00000000)
+#define DEF_SMS4_KEY_1() (REG32(ADR_SMS4_KEY_1)) = (0x00000000)
+#define DEF_SMS4_KEY_2() (REG32(ADR_SMS4_KEY_2)) = (0x00000000)
+#define DEF_SMS4_KEY_3() (REG32(ADR_SMS4_KEY_3)) = (0x00000000)
+#define DEF_SMS4_MODE_IV0() (REG32(ADR_SMS4_MODE_IV0)) = (0x00000000)
+#define DEF_SMS4_MODE_IV1() (REG32(ADR_SMS4_MODE_IV1)) = (0x00000000)
+#define DEF_SMS4_MODE_IV2() (REG32(ADR_SMS4_MODE_IV2)) = (0x00000000)
+#define DEF_SMS4_MODE_IV3() (REG32(ADR_SMS4_MODE_IV3)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC0() (REG32(ADR_SMS4_OFB_ENC0)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC1() (REG32(ADR_SMS4_OFB_ENC1)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC2() (REG32(ADR_SMS4_OFB_ENC2)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC3() (REG32(ADR_SMS4_OFB_ENC3)) = (0x00000000)
+#define DEF_MRX_MCAST_TB0_0() (REG32(ADR_MRX_MCAST_TB0_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB0_1() (REG32(ADR_MRX_MCAST_TB0_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK0_0() (REG32(ADR_MRX_MCAST_MK0_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK0_1() (REG32(ADR_MRX_MCAST_MK0_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL0() (REG32(ADR_MRX_MCAST_CTRL0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB1_0() (REG32(ADR_MRX_MCAST_TB1_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB1_1() (REG32(ADR_MRX_MCAST_TB1_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK1_0() (REG32(ADR_MRX_MCAST_MK1_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK1_1() (REG32(ADR_MRX_MCAST_MK1_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL1() (REG32(ADR_MRX_MCAST_CTRL1)) = (0x00000000)
+#define DEF_MRX_MCAST_TB2_0() (REG32(ADR_MRX_MCAST_TB2_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB2_1() (REG32(ADR_MRX_MCAST_TB2_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK2_0() (REG32(ADR_MRX_MCAST_MK2_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK2_1() (REG32(ADR_MRX_MCAST_MK2_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL2() (REG32(ADR_MRX_MCAST_CTRL2)) = (0x00000000)
+#define DEF_MRX_MCAST_TB3_0() (REG32(ADR_MRX_MCAST_TB3_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB3_1() (REG32(ADR_MRX_MCAST_TB3_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK3_0() (REG32(ADR_MRX_MCAST_MK3_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK3_1() (REG32(ADR_MRX_MCAST_MK3_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL3() (REG32(ADR_MRX_MCAST_CTRL3)) = (0x00000000)
+#define DEF_MRX_PHY_INFO() (REG32(ADR_MRX_PHY_INFO)) = (0x00000000)
+#define DEF_MRX_BA_DBG() (REG32(ADR_MRX_BA_DBG)) = (0x00000000)
+#define DEF_MRX_FLT_TB0() (REG32(ADR_MRX_FLT_TB0)) = (0x00003df5)
+#define DEF_MRX_FLT_TB1() (REG32(ADR_MRX_FLT_TB1)) = (0x000031f6)
+#define DEF_MRX_FLT_TB2() (REG32(ADR_MRX_FLT_TB2)) = (0x000035f9)
+#define DEF_MRX_FLT_TB3() (REG32(ADR_MRX_FLT_TB3)) = (0x000021c1)
+#define DEF_MRX_FLT_TB4() (REG32(ADR_MRX_FLT_TB4)) = (0x00004bf9)
+#define DEF_MRX_FLT_TB5() (REG32(ADR_MRX_FLT_TB5)) = (0x00004db1)
+#define DEF_MRX_FLT_TB6() (REG32(ADR_MRX_FLT_TB6)) = (0x000011fe)
+#define DEF_MRX_FLT_TB7() (REG32(ADR_MRX_FLT_TB7)) = (0x00000bfe)
+#define DEF_MRX_FLT_TB8() (REG32(ADR_MRX_FLT_TB8)) = (0x00000000)
+#define DEF_MRX_FLT_TB9() (REG32(ADR_MRX_FLT_TB9)) = (0x00000000)
+#define DEF_MRX_FLT_TB10() (REG32(ADR_MRX_FLT_TB10)) = (0x00000000)
+#define DEF_MRX_FLT_TB11() (REG32(ADR_MRX_FLT_TB11)) = (0x00000006)
+#define DEF_MRX_FLT_TB12() (REG32(ADR_MRX_FLT_TB12)) = (0x00000001)
+#define DEF_MRX_FLT_TB13() (REG32(ADR_MRX_FLT_TB13)) = (0x00000003)
+#define DEF_MRX_FLT_TB14() (REG32(ADR_MRX_FLT_TB14)) = (0x00000005)
+#define DEF_MRX_FLT_TB15() (REG32(ADR_MRX_FLT_TB15)) = (0x00000007)
+#define DEF_MRX_FLT_EN0() (REG32(ADR_MRX_FLT_EN0)) = (0x00002008)
+#define DEF_MRX_FLT_EN1() (REG32(ADR_MRX_FLT_EN1)) = (0x00001001)
+#define DEF_MRX_FLT_EN2() (REG32(ADR_MRX_FLT_EN2)) = (0x00000808)
+#define DEF_MRX_FLT_EN3() (REG32(ADR_MRX_FLT_EN3)) = (0x00001000)
+#define DEF_MRX_FLT_EN4() (REG32(ADR_MRX_FLT_EN4)) = (0x00002008)
+#define DEF_MRX_FLT_EN5() (REG32(ADR_MRX_FLT_EN5)) = (0x0000800e)
+#define DEF_MRX_FLT_EN6() (REG32(ADR_MRX_FLT_EN6)) = (0x00000838)
+#define DEF_MRX_FLT_EN7() (REG32(ADR_MRX_FLT_EN7)) = (0x00002008)
+#define DEF_MRX_FLT_EN8() (REG32(ADR_MRX_FLT_EN8)) = (0x00002008)
+#define DEF_MRX_LEN_FLT() (REG32(ADR_MRX_LEN_FLT)) = (0x00000000)
+#define DEF_RX_FLOW_DATA() (REG32(ADR_RX_FLOW_DATA)) = (0x00105034)
+#define DEF_RX_FLOW_MNG() (REG32(ADR_RX_FLOW_MNG)) = (0x00000004)
+#define DEF_RX_FLOW_CTRL() (REG32(ADR_RX_FLOW_CTRL)) = (0x00000004)
+#define DEF_RX_TIME_STAMP_CFG() (REG32(ADR_RX_TIME_STAMP_CFG)) = (0x00001c00)
+#define DEF_DBG_FF_FULL() (REG32(ADR_DBG_FF_FULL)) = (0x00000000)
+#define DEF_DBG_WFF_FULL() (REG32(ADR_DBG_WFF_FULL)) = (0x00000000)
+#define DEF_DBG_MB_FULL() (REG32(ADR_DBG_MB_FULL)) = (0x00000000)
+#define DEF_BA_CTRL() (REG32(ADR_BA_CTRL)) = (0x00000008)
+#define DEF_BA_TA_0() (REG32(ADR_BA_TA_0)) = (0x00000000)
+#define DEF_BA_TA_1() (REG32(ADR_BA_TA_1)) = (0x00000000)
+#define DEF_BA_TID() (REG32(ADR_BA_TID)) = (0x00000000)
+#define DEF_BA_ST_SEQ() (REG32(ADR_BA_ST_SEQ)) = (0x00000000)
+#define DEF_BA_SB0() (REG32(ADR_BA_SB0)) = (0x00000000)
+#define DEF_BA_SB1() (REG32(ADR_BA_SB1)) = (0x00000000)
+#define DEF_MRX_WATCH_DOG() (REG32(ADR_MRX_WATCH_DOG)) = (0x0000ffff)
+#define DEF_ACK_GEN_EN() (REG32(ADR_ACK_GEN_EN)) = (0x00000000)
+#define DEF_ACK_GEN_PARA() (REG32(ADR_ACK_GEN_PARA)) = (0x00000000)
+#define DEF_ACK_GEN_RA_0() (REG32(ADR_ACK_GEN_RA_0)) = (0x00000000)
+#define DEF_ACK_GEN_RA_1() (REG32(ADR_ACK_GEN_RA_1)) = (0x00000000)
+#define DEF_MIB_LEN_FAIL() (REG32(ADR_MIB_LEN_FAIL)) = (0x00000000)
+#define DEF_TRAP_HW_ID() (REG32(ADR_TRAP_HW_ID)) = (0x00000000)
+#define DEF_ID_IN_USE() (REG32(ADR_ID_IN_USE)) = (0x00000000)
+#define DEF_MRX_ERR() (REG32(ADR_MRX_ERR)) = (0x00000000)
+#define DEF_WSID0_TID0_RX_SEQ() (REG32(ADR_WSID0_TID0_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID1_RX_SEQ() (REG32(ADR_WSID0_TID1_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID2_RX_SEQ() (REG32(ADR_WSID0_TID2_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID3_RX_SEQ() (REG32(ADR_WSID0_TID3_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID4_RX_SEQ() (REG32(ADR_WSID0_TID4_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID5_RX_SEQ() (REG32(ADR_WSID0_TID5_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID6_RX_SEQ() (REG32(ADR_WSID0_TID6_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID7_RX_SEQ() (REG32(ADR_WSID0_TID7_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID0_RX_SEQ() (REG32(ADR_WSID1_TID0_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID1_RX_SEQ() (REG32(ADR_WSID1_TID1_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID2_RX_SEQ() (REG32(ADR_WSID1_TID2_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID3_RX_SEQ() (REG32(ADR_WSID1_TID3_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID4_RX_SEQ() (REG32(ADR_WSID1_TID4_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID5_RX_SEQ() (REG32(ADR_WSID1_TID5_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID6_RX_SEQ() (REG32(ADR_WSID1_TID6_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID7_RX_SEQ() (REG32(ADR_WSID1_TID7_RX_SEQ)) = (0x00000000)
+#define DEF_HDR_ADDR_SEL() (REG32(ADR_HDR_ADDR_SEL)) = (0x00003e79)
+#define DEF_FRAME_TYPE_CNTR_SET() (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (0x00000000)
+#define DEF_PHY_INFO() (REG32(ADR_PHY_INFO)) = (0x00000000)
+#define DEF_AMPDU_SIG() (REG32(ADR_AMPDU_SIG)) = (0x0000004e)
+#define DEF_MIB_AMPDU() (REG32(ADR_MIB_AMPDU)) = (0x00000000)
+#define DEF_LEN_FLT() (REG32(ADR_LEN_FLT)) = (0x00000000)
+#define DEF_MIB_DELIMITER() (REG32(ADR_MIB_DELIMITER)) = (0x00000000)
+#define DEF_MTX_INT_STS() (REG32(ADR_MTX_INT_STS)) = (0x00000000)
+#define DEF_MTX_INT_EN() (REG32(ADR_MTX_INT_EN)) = (0x00000000)
+#define DEF_MTX_MISC_EN() (REG32(ADR_MTX_MISC_EN)) = (0x00c00c00)
+#define DEF_MTX_EDCCA_TOUT() (REG32(ADR_MTX_EDCCA_TOUT)) = (0x00000200)
+#define DEF_MTX_BCN_INT_STS() (REG32(ADR_MTX_BCN_INT_STS)) = (0x00000000)
+#define DEF_MTX_BCN_EN_INT() (REG32(ADR_MTX_BCN_EN_INT)) = (0x00000000)
+#define DEF_MTX_BCN_EN_MISC() (REG32(ADR_MTX_BCN_EN_MISC)) = (0x00000042)
+#define DEF_MTX_BCN_MISC() (REG32(ADR_MTX_BCN_MISC)) = (0x00000000)
+#define DEF_MTX_BCN_PRD() (REG32(ADR_MTX_BCN_PRD)) = (0x00000064)
+#define DEF_MTX_BCN_TSF_L() (REG32(ADR_MTX_BCN_TSF_L)) = (0x00000000)
+#define DEF_MTX_BCN_TSF_U() (REG32(ADR_MTX_BCN_TSF_U)) = (0x00000000)
+#define DEF_MTX_BCN_CFG0() (REG32(ADR_MTX_BCN_CFG0)) = (0x00000000)
+#define DEF_MTX_BCN_CFG1() (REG32(ADR_MTX_BCN_CFG1)) = (0x00000000)
+#define DEF_MTX_STATUS() (REG32(ADR_MTX_STATUS)) = (0x00000000)
+#define DEF_MTX_DBG_CTRL() (REG32(ADR_MTX_DBG_CTRL)) = (0x00000000)
+#define DEF_MTX_DBG_DAT0() (REG32(ADR_MTX_DBG_DAT0)) = (0x00000000)
+#define DEF_MTX_DBG_DAT1() (REG32(ADR_MTX_DBG_DAT1)) = (0x00000000)
+#define DEF_MTX_DBG_DAT2() (REG32(ADR_MTX_DBG_DAT2)) = (0x00000000)
+#define DEF_MTX_DUR_TOUT() (REG32(ADR_MTX_DUR_TOUT)) = (0x00002c2c)
+#define DEF_MTX_DUR_IFS() (REG32(ADR_MTX_DUR_IFS)) = (0x12d40a05)
+#define DEF_MTX_DUR_SIFS_G() (REG32(ADR_MTX_DUR_SIFS_G)) = (0x12c90100)
+#define DEF_MTX_DBG_DAT3() (REG32(ADR_MTX_DBG_DAT3)) = (0x00000000)
+#define DEF_MTX_NAV() (REG32(ADR_MTX_NAV)) = (0x00000000)
+#define DEF_MTX_MIB_WSID0() (REG32(ADR_MTX_MIB_WSID0)) = (0x00000000)
+#define DEF_MTX_MIB_WSID1() (REG32(ADR_MTX_MIB_WSID1)) = (0x00000000)
+#define DEF_MTX_DBG_DAT4() (REG32(ADR_MTX_DBG_DAT4)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_MISC_EN() (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_AIFSN() (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ0_MTX_Q_BKF_CNT() (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ0_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_MISC_EN() (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_AIFSN() (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ1_MTX_Q_BKF_CNT() (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ1_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_MISC_EN() (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_AIFSN() (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ2_MTX_Q_BKF_CNT() (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ2_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_MISC_EN() (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_AIFSN() (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ3_MTX_Q_BKF_CNT() (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ3_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_MISC_EN() (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_AIFSN() (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ4_MTX_Q_BKF_CNT() (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ4_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_WSID0() (REG32(ADR_WSID0)) = (0x00000000)
+#define DEF_PEER_MAC0_0() (REG32(ADR_PEER_MAC0_0)) = (0x00000000)
+#define DEF_PEER_MAC0_1() (REG32(ADR_PEER_MAC0_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_0() (REG32(ADR_TX_ACK_POLICY_0_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_0() (REG32(ADR_TX_SEQ_CTRL_0_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_1() (REG32(ADR_TX_ACK_POLICY_0_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_1() (REG32(ADR_TX_SEQ_CTRL_0_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_2() (REG32(ADR_TX_ACK_POLICY_0_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_2() (REG32(ADR_TX_SEQ_CTRL_0_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_3() (REG32(ADR_TX_ACK_POLICY_0_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_3() (REG32(ADR_TX_SEQ_CTRL_0_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_4() (REG32(ADR_TX_ACK_POLICY_0_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_4() (REG32(ADR_TX_SEQ_CTRL_0_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_5() (REG32(ADR_TX_ACK_POLICY_0_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_5() (REG32(ADR_TX_SEQ_CTRL_0_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_6() (REG32(ADR_TX_ACK_POLICY_0_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_6() (REG32(ADR_TX_SEQ_CTRL_0_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_7() (REG32(ADR_TX_ACK_POLICY_0_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_7() (REG32(ADR_TX_SEQ_CTRL_0_7)) = (0x00000000)
+#define DEF_WSID1() (REG32(ADR_WSID1)) = (0x00000000)
+#define DEF_PEER_MAC1_0() (REG32(ADR_PEER_MAC1_0)) = (0x00000000)
+#define DEF_PEER_MAC1_1() (REG32(ADR_PEER_MAC1_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_0() (REG32(ADR_TX_ACK_POLICY_1_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_0() (REG32(ADR_TX_SEQ_CTRL_1_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_1() (REG32(ADR_TX_ACK_POLICY_1_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_1() (REG32(ADR_TX_SEQ_CTRL_1_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_2() (REG32(ADR_TX_ACK_POLICY_1_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_2() (REG32(ADR_TX_SEQ_CTRL_1_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_3() (REG32(ADR_TX_ACK_POLICY_1_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_3() (REG32(ADR_TX_SEQ_CTRL_1_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_4() (REG32(ADR_TX_ACK_POLICY_1_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_4() (REG32(ADR_TX_SEQ_CTRL_1_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_5() (REG32(ADR_TX_ACK_POLICY_1_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_5() (REG32(ADR_TX_SEQ_CTRL_1_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_6() (REG32(ADR_TX_ACK_POLICY_1_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_6() (REG32(ADR_TX_SEQ_CTRL_1_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_7() (REG32(ADR_TX_ACK_POLICY_1_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_7() (REG32(ADR_TX_SEQ_CTRL_1_7)) = (0x00000000)
+#define DEF_INFO0() (REG32(ADR_INFO0)) = (0x00000000)
+#define DEF_INFO1() (REG32(ADR_INFO1)) = (0x00000100)
+#define DEF_INFO2() (REG32(ADR_INFO2)) = (0x00000200)
+#define DEF_INFO3() (REG32(ADR_INFO3)) = (0x00000300)
+#define DEF_INFO4() (REG32(ADR_INFO4)) = (0x00000140)
+#define DEF_INFO5() (REG32(ADR_INFO5)) = (0x00000240)
+#define DEF_INFO6() (REG32(ADR_INFO6)) = (0x00000340)
+#define DEF_INFO7() (REG32(ADR_INFO7)) = (0x00000001)
+#define DEF_INFO8() (REG32(ADR_INFO8)) = (0x00000101)
+#define DEF_INFO9() (REG32(ADR_INFO9)) = (0x00000201)
+#define DEF_INFO10() (REG32(ADR_INFO10)) = (0x00000301)
+#define DEF_INFO11() (REG32(ADR_INFO11)) = (0x00000401)
+#define DEF_INFO12() (REG32(ADR_INFO12)) = (0x00000501)
+#define DEF_INFO13() (REG32(ADR_INFO13)) = (0x00000601)
+#define DEF_INFO14() (REG32(ADR_INFO14)) = (0x00000701)
+#define DEF_INFO15() (REG32(ADR_INFO15)) = (0x00030002)
+#define DEF_INFO16() (REG32(ADR_INFO16)) = (0x00030102)
+#define DEF_INFO17() (REG32(ADR_INFO17)) = (0x00030202)
+#define DEF_INFO18() (REG32(ADR_INFO18)) = (0x00030302)
+#define DEF_INFO19() (REG32(ADR_INFO19)) = (0x00030402)
+#define DEF_INFO20() (REG32(ADR_INFO20)) = (0x00030502)
+#define DEF_INFO21() (REG32(ADR_INFO21)) = (0x00030602)
+#define DEF_INFO22() (REG32(ADR_INFO22)) = (0x00030702)
+#define DEF_INFO23() (REG32(ADR_INFO23)) = (0x00030082)
+#define DEF_INFO24() (REG32(ADR_INFO24)) = (0x00030182)
+#define DEF_INFO25() (REG32(ADR_INFO25)) = (0x00030282)
+#define DEF_INFO26() (REG32(ADR_INFO26)) = (0x00030382)
+#define DEF_INFO27() (REG32(ADR_INFO27)) = (0x00030482)
+#define DEF_INFO28() (REG32(ADR_INFO28)) = (0x00030582)
+#define DEF_INFO29() (REG32(ADR_INFO29)) = (0x00030682)
+#define DEF_INFO30() (REG32(ADR_INFO30)) = (0x00030782)
+#define DEF_INFO31() (REG32(ADR_INFO31)) = (0x00030042)
+#define DEF_INFO32() (REG32(ADR_INFO32)) = (0x00030142)
+#define DEF_INFO33() (REG32(ADR_INFO33)) = (0x00030242)
+#define DEF_INFO34() (REG32(ADR_INFO34)) = (0x00030342)
+#define DEF_INFO35() (REG32(ADR_INFO35)) = (0x00030442)
+#define DEF_INFO36() (REG32(ADR_INFO36)) = (0x00030542)
+#define DEF_INFO37() (REG32(ADR_INFO37)) = (0x00030642)
+#define DEF_INFO38() (REG32(ADR_INFO38)) = (0x00030742)
+#define DEF_INFO_MASK() (REG32(ADR_INFO_MASK)) = (0x00007fc7)
+#define DEF_INFO_RATE_OFFSET() (REG32(ADR_INFO_RATE_OFFSET)) = (0x00040000)
+#define DEF_INFO_IDX_ADDR() (REG32(ADR_INFO_IDX_ADDR)) = (0x00000000)
+#define DEF_INFO_LEN_ADDR() (REG32(ADR_INFO_LEN_ADDR)) = (0x00000000)
+#define DEF_IC_TIME_TAG_0() (REG32(ADR_IC_TIME_TAG_0)) = (0x00000000)
+#define DEF_IC_TIME_TAG_1() (REG32(ADR_IC_TIME_TAG_1)) = (0x00000000)
+#define DEF_PACKET_ID_ALLOCATION_PRIORITY() (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (0x00000000)
+#define DEF_MAC_MODE() (REG32(ADR_MAC_MODE)) = (0x00000000)
+#define DEF_ALL_SOFTWARE_RESET() (REG32(ADR_ALL_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_ENG_SOFTWARE_RESET() (REG32(ADR_ENG_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_CSR_SOFTWARE_RESET() (REG32(ADR_CSR_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_MAC_CLOCK_ENABLE() (REG32(ADR_MAC_CLOCK_ENABLE)) = (0x00003efb)
+#define DEF_MAC_ENGINE_CLOCK_ENABLE() (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (0x0000f07b)
+#define DEF_MAC_CSR_CLOCK_ENABLE() (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (0x0000ec02)
+#define DEF_GLBLE_SET() (REG32(ADR_GLBLE_SET)) = (0x000e5000)
+#define DEF_REASON_TRAP0() (REG32(ADR_REASON_TRAP0)) = (0x00000000)
+#define DEF_REASON_TRAP1() (REG32(ADR_REASON_TRAP1)) = (0x00000000)
+#define DEF_BSSID_0() (REG32(ADR_BSSID_0)) = (0x00000000)
+#define DEF_BSSID_1() (REG32(ADR_BSSID_1)) = (0x00000000)
+#define DEF_SCRT_STATE() (REG32(ADR_SCRT_STATE)) = (0x00000000)
+#define DEF_STA_MAC_0() (REG32(ADR_STA_MAC_0)) = (0x00000000)
+#define DEF_STA_MAC_1() (REG32(ADR_STA_MAC_1)) = (0x00000000)
+#define DEF_SCRT_SET() (REG32(ADR_SCRT_SET)) = (0x00000000)
+#define DEF_BTCX0() (REG32(ADR_BTCX0)) = (0x00000006)
+#define DEF_BTCX1() (REG32(ADR_BTCX1)) = (0x00000000)
+#define DEF_SWITCH_CTL() (REG32(ADR_SWITCH_CTL)) = (0x00000000)
+#define DEF_MIB_EN() (REG32(ADR_MIB_EN)) = (0x00000000)
+#define DEF_MTX_WSID0_SUCC() (REG32(ADR_MTX_WSID0_SUCC)) = (0x00000000)
+#define DEF_MTX_WSID0_FRM() (REG32(ADR_MTX_WSID0_FRM)) = (0x00000000)
+#define DEF_MTX_WSID0_RETRY() (REG32(ADR_MTX_WSID0_RETRY)) = (0x00000000)
+#define DEF_MTX_WSID0_TOTAL() (REG32(ADR_MTX_WSID0_TOTAL)) = (0x00000000)
+#define DEF_MTX_GROUP() (REG32(ADR_MTX_GROUP)) = (0x00000000)
+#define DEF_MTX_FAIL() (REG32(ADR_MTX_FAIL)) = (0x00000000)
+#define DEF_MTX_RETRY() (REG32(ADR_MTX_RETRY)) = (0x00000000)
+#define DEF_MTX_MULTI_RETRY() (REG32(ADR_MTX_MULTI_RETRY)) = (0x00000000)
+#define DEF_MTX_RTS_SUCCESS() (REG32(ADR_MTX_RTS_SUCCESS)) = (0x00000000)
+#define DEF_MTX_RTS_FAIL() (REG32(ADR_MTX_RTS_FAIL)) = (0x00000000)
+#define DEF_MTX_ACK_FAIL() (REG32(ADR_MTX_ACK_FAIL)) = (0x00000000)
+#define DEF_MTX_FRM() (REG32(ADR_MTX_FRM)) = (0x00000000)
+#define DEF_MTX_ACK_TX() (REG32(ADR_MTX_ACK_TX)) = (0x00000000)
+#define DEF_MTX_CTS_TX() (REG32(ADR_MTX_CTS_TX)) = (0x00000000)
+#define DEF_MRX_DUP_FRM() (REG32(ADR_MRX_DUP_FRM)) = (0x00000000)
+#define DEF_MRX_FRG_FRM() (REG32(ADR_MRX_FRG_FRM)) = (0x00000000)
+#define DEF_MRX_GROUP_FRM() (REG32(ADR_MRX_GROUP_FRM)) = (0x00000000)
+#define DEF_MRX_FCS_ERR() (REG32(ADR_MRX_FCS_ERR)) = (0x00000000)
+#define DEF_MRX_FCS_SUCC() (REG32(ADR_MRX_FCS_SUCC)) = (0x00000000)
+#define DEF_MRX_MISS() (REG32(ADR_MRX_MISS)) = (0x00000000)
+#define DEF_MRX_ALC_FAIL() (REG32(ADR_MRX_ALC_FAIL)) = (0x00000000)
+#define DEF_MRX_DAT_NTF() (REG32(ADR_MRX_DAT_NTF)) = (0x00000000)
+#define DEF_MRX_RTS_NTF() (REG32(ADR_MRX_RTS_NTF)) = (0x00000000)
+#define DEF_MRX_CTS_NTF() (REG32(ADR_MRX_CTS_NTF)) = (0x00000000)
+#define DEF_MRX_ACK_NTF() (REG32(ADR_MRX_ACK_NTF)) = (0x00000000)
+#define DEF_MRX_BA_NTF() (REG32(ADR_MRX_BA_NTF)) = (0x00000000)
+#define DEF_MRX_DATA_NTF() (REG32(ADR_MRX_DATA_NTF)) = (0x00000000)
+#define DEF_MRX_MNG_NTF() (REG32(ADR_MRX_MNG_NTF)) = (0x00000000)
+#define DEF_MRX_DAT_CRC_NTF() (REG32(ADR_MRX_DAT_CRC_NTF)) = (0x00000000)
+#define DEF_MRX_BAR_NTF() (REG32(ADR_MRX_BAR_NTF)) = (0x00000000)
+#define DEF_MRX_MB_MISS() (REG32(ADR_MRX_MB_MISS)) = (0x00000000)
+#define DEF_MRX_NIDLE_MISS() (REG32(ADR_MRX_NIDLE_MISS)) = (0x00000000)
+#define DEF_MRX_CSR_NTF() (REG32(ADR_MRX_CSR_NTF)) = (0x00000000)
+#define DEF_DBG_Q0_FRM_SUCCESS() (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q0_FRM_FAIL() (REG32(ADR_DBG_Q0_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q0_ACK_SUCCESS() (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q0_ACK_FAIL() (REG32(ADR_DBG_Q0_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q1_FRM_SUCCESS() (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q1_FRM_FAIL() (REG32(ADR_DBG_Q1_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q1_ACK_SUCCESS() (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q1_ACK_FAIL() (REG32(ADR_DBG_Q1_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q2_FRM_SUCCESS() (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q2_FRM_FAIL() (REG32(ADR_DBG_Q2_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q2_ACK_SUCCESS() (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q2_ACK_FAIL() (REG32(ADR_DBG_Q2_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q3_FRM_SUCCESS() (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q3_FRM_FAIL() (REG32(ADR_DBG_Q3_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q3_ACK_SUCCESS() (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q3_ACK_FAIL() (REG32(ADR_DBG_Q3_ACK_FAIL)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP0() (REG32(ADR_MIB_SCRT_TKIP0)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP1() (REG32(ADR_MIB_SCRT_TKIP1)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP2() (REG32(ADR_MIB_SCRT_TKIP2)) = (0x00000000)
+#define DEF_MIB_SCRT_CCMP0() (REG32(ADR_MIB_SCRT_CCMP0)) = (0x00000000)
+#define DEF_MIB_SCRT_CCMP1() (REG32(ADR_MIB_SCRT_CCMP1)) = (0x00000000)
+#define DEF_DBG_LEN_CRC_FAIL() (REG32(ADR_DBG_LEN_CRC_FAIL)) = (0x00000000)
+#define DEF_DBG_LEN_ALC_FAIL() (REG32(ADR_DBG_LEN_ALC_FAIL)) = (0x00000000)
+#define DEF_DBG_AMPDU_PASS() (REG32(ADR_DBG_AMPDU_PASS)) = (0x00000000)
+#define DEF_DBG_AMPDU_FAIL() (REG32(ADR_DBG_AMPDU_FAIL)) = (0x00000000)
+#define DEF_ID_ALC_FAIL1() (REG32(ADR_ID_ALC_FAIL1)) = (0x00000000)
+#define DEF_ID_ALC_FAIL2() (REG32(ADR_ID_ALC_FAIL2)) = (0x00000000)
+#define DEF_CBR_HARD_WIRE_PIN_REGISTER() (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
+#define DEF_CBR_MANUAL_ENABLE_REGISTER() (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (0x00001fc0)
+#define DEF_CBR_LDO_REGISTER() (REG32(ADR_CBR_LDO_REGISTER)) = (0x2496db1b)
+#define DEF_CBR_ABB_REGISTER_1() (REG32(ADR_CBR_ABB_REGISTER_1)) = (0x151558dd)
+#define DEF_CBR_ABB_REGISTER_2() (REG32(ADR_CBR_ABB_REGISTER_2)) = (0x01011a88)
+#define DEF_CBR_TX_FE_REGISTER() (REG32(ADR_CBR_TX_FE_REGISTER)) = (0x3cbe84fe)
+#define DEF_CBR_RX_FE_REGISTER_1() (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (0x00657579)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
+#define DEF_CBR_RX_FSM_REGISTER() (REG32(ADR_CBR_RX_FSM_REGISTER)) = (0x00000ca8)
+#define DEF_CBR_RX_ADC_REGISTER() (REG32(ADR_CBR_RX_ADC_REGISTER)) = (0x002a0224)
+#define DEF_CBR_TX_DAC_REGISTER() (REG32(ADR_CBR_TX_DAC_REGISTER)) = (0x00002655)
+#define DEF_CBR_SX_ENABLE_RGISTER() (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (0x0000647c)
+#define DEF_CBR_SYN_RGISTER_1() (REG32(ADR_CBR_SYN_RGISTER_1)) = (0xaa800000)
+#define DEF_CBR_SYN_RGISTER_2() (REG32(ADR_CBR_SYN_RGISTER_2)) = (0x00550800)
+#define DEF_CBR_SYN_PFD_CHP() (REG32(ADR_CBR_SYN_PFD_CHP)) = (0x07c0894a)
+#define DEF_CBR_SYN_VCO_LOBF() (REG32(ADR_CBR_SYN_VCO_LOBF)) = (0xfcccca27)
+#define DEF_CBR_SYN_DIV_SDM_XOSC() (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (0x2773c93c)
+#define DEF_CBR_SYN_LCK1() (REG32(ADR_CBR_SYN_LCK1)) = (0x00000a7c)
+#define DEF_CBR_SYN_LCK2() (REG32(ADR_CBR_SYN_LCK2)) = (0x01c67ff4)
+#define DEF_CBR_DPLL_VCO_REGISTER() (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (0x00103014)
+#define DEF_CBR_DPLL_CP_PFD_REGISTER() (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (0x0001848c)
+#define DEF_CBR_DPLL_DIVIDER_REGISTER() (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (0x034061e0)
+#define DEF_CBR_DCOC_IDAC_REGISTER1() (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER2() (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER3() (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER4() (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER5() (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER6() (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER7() (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER8() (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (0x00820820)
+#define DEF_CBR_RCAL_REGISTER() (REG32(ADR_CBR_RCAL_REGISTER)) = (0x00004080)
+#define DEF_CBR_MANUAL_REGISTER() (REG32(ADR_CBR_MANUAL_REGISTER)) = (0x00003e7e)
+#define DEF_CBR_TRX_DUMMY_REGISTER() (REG32(ADR_CBR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_CBR_SX_DUMMY_REGISTER() (REG32(ADR_CBR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_CBR_RG_PKT_GEN_0() (REG32(ADR_CBR_RG_PKT_GEN_0)) = (0x00000000)
+#define DEF_CBR_RG_PKT_GEN_1() (REG32(ADR_CBR_RG_PKT_GEN_1)) = (0x00000000)
+#define DEF_CBR_RG_PKT_GEN_2() (REG32(ADR_CBR_RG_PKT_GEN_2)) = (0x00000000)
+#define DEF_CBR_RG_INTEGRATION() (REG32(ADR_CBR_RG_INTEGRATION)) = (0x00000000)
+#define DEF_CBR_RG_PKT_GEN_TXCNT() (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (0x00000000)
+#define DEF_CBR_PATTERN_GEN() (REG32(ADR_CBR_PATTERN_GEN)) = (0xff000000)
+#define DEF_MB_CPU_INT() (REG32(ADR_MB_CPU_INT)) = (0x00000000)
+#define DEF_CPU_ID_TB0() (REG32(ADR_CPU_ID_TB0)) = (0x00000000)
+#define DEF_CPU_ID_TB1() (REG32(ADR_CPU_ID_TB1)) = (0x00000000)
+#define DEF_CH0_TRIG_1() (REG32(ADR_CH0_TRIG_1)) = (0x00000000)
+#define DEF_CH0_TRIG_0() (REG32(ADR_CH0_TRIG_0)) = (0x00000000)
+#define DEF_CH0_PRI_TRIG() (REG32(ADR_CH0_PRI_TRIG)) = (0x00000000)
+#define DEF_MCU_STATUS() (REG32(ADR_MCU_STATUS)) = (0x00000000)
+#define DEF_RD_IN_FFCNT1() (REG32(ADR_RD_IN_FFCNT1)) = (0x00000000)
+#define DEF_RD_IN_FFCNT2() (REG32(ADR_RD_IN_FFCNT2)) = (0x00000000)
+#define DEF_RD_FFIN_FULL() (REG32(ADR_RD_FFIN_FULL)) = (0x00000000)
+#define DEF_MBOX_HALT_CFG() (REG32(ADR_MBOX_HALT_CFG)) = (0x00000000)
+#define DEF_MB_DBG_CFG1() (REG32(ADR_MB_DBG_CFG1)) = (0x00080000)
+#define DEF_MB_DBG_CFG2() (REG32(ADR_MB_DBG_CFG2)) = (0x00000000)
+#define DEF_MB_DBG_CFG3() (REG32(ADR_MB_DBG_CFG3)) = (0x00000000)
+#define DEF_MB_DBG_CFG4() (REG32(ADR_MB_DBG_CFG4)) = (0xffffffff)
+#define DEF_MB_OUT_QUEUE_CFG() (REG32(ADR_MB_OUT_QUEUE_CFG)) = (0x00000002)
+#define DEF_MB_OUT_QUEUE_FLUSH() (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT1() (REG32(ADR_RD_FFOUT_CNT1)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT2() (REG32(ADR_RD_FFOUT_CNT2)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT3() (REG32(ADR_RD_FFOUT_CNT3)) = (0x00000000)
+#define DEF_RD_FFOUT_FULL() (REG32(ADR_RD_FFOUT_FULL)) = (0x00000000)
+#define DEF_MB_THRESHOLD6() (REG32(ADR_MB_THRESHOLD6)) = (0x00000000)
+#define DEF_MB_THRESHOLD7() (REG32(ADR_MB_THRESHOLD7)) = (0x00000000)
+#define DEF_MB_THRESHOLD8() (REG32(ADR_MB_THRESHOLD8)) = (0x00000000)
+#define DEF_MB_THRESHOLD9() (REG32(ADR_MB_THRESHOLD9)) = (0x00000000)
+#define DEF_MB_THRESHOLD10() (REG32(ADR_MB_THRESHOLD10)) = (0x00000000)
+#define DEF_MB_TRASH_CFG() (REG32(ADR_MB_TRASH_CFG)) = (0x01000001)
+#define DEF_MB_IN_FF_FLUSH() (REG32(ADR_MB_IN_FF_FLUSH)) = (0x00000000)
+#define DEF_CPU_ID_TB2() (REG32(ADR_CPU_ID_TB2)) = (0x00000000)
+#define DEF_CPU_ID_TB3() (REG32(ADR_CPU_ID_TB3)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_CFG0() (REG32(ADR_PHY_IQ_LOG_CFG0)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_CFG1() (REG32(ADR_PHY_IQ_LOG_CFG1)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_LEN() (REG32(ADR_PHY_IQ_LOG_LEN)) = (0x00001000)
+#define DEF_PHY_IQ_LOG_PTR() (REG32(ADR_PHY_IQ_LOG_PTR)) = (0x00000000)
+#define DEF_WR_ALC() (REG32(ADR_WR_ALC)) = (0x00000000)
+#define DEF_GETID() (REG32(ADR_GETID)) = (0x00000000)
+#define DEF_CH_STA_PRI() (REG32(ADR_CH_STA_PRI)) = (0x00000213)
+#define DEF_RD_ID0() (REG32(ADR_RD_ID0)) = (0x00000000)
+#define DEF_RD_ID1() (REG32(ADR_RD_ID1)) = (0x00000000)
+#define DEF_IMD_CFG() (REG32(ADR_IMD_CFG)) = (0x00000000)
+#define DEF_IMD_STA() (REG32(ADR_IMD_STA)) = (0x00000000)
+#define DEF_ALC_STA() (REG32(ADR_ALC_STA)) = (0x01000000)
+#define DEF_TRX_ID_COUNT() (REG32(ADR_TRX_ID_COUNT)) = (0x00000000)
+#define DEF_TRX_ID_THRESHOLD() (REG32(ADR_TRX_ID_THRESHOLD)) = (0x01ee3c3c)
+#define DEF_TX_ID0() (REG32(ADR_TX_ID0)) = (0x00000000)
+#define DEF_TX_ID1() (REG32(ADR_TX_ID1)) = (0x00000000)
+#define DEF_RX_ID0() (REG32(ADR_RX_ID0)) = (0x00000000)
+#define DEF_RX_ID1() (REG32(ADR_RX_ID1)) = (0x00000000)
+#define DEF_RTN_STA() (REG32(ADR_RTN_STA)) = (0x00000001)
+#define DEF_ID_LEN_THREADSHOLD1() (REG32(ADR_ID_LEN_THREADSHOLD1)) = (0x000f0641)
+#define DEF_ID_LEN_THREADSHOLD2() (REG32(ADR_ID_LEN_THREADSHOLD2)) = (0x00000000)
+#define DEF_CH_ARB_PRI() (REG32(ADR_CH_ARB_PRI)) = (0x00031201)
+#define DEF_TX_ID_REMAIN_STATUS() (REG32(ADR_TX_ID_REMAIN_STATUS)) = (0x00000000)
+#define DEF_ID_INFO_STA() (REG32(ADR_ID_INFO_STA)) = (0x00000100)
+#define DEF_TX_LIMIT_INTR() (REG32(ADR_TX_LIMIT_INTR)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO() (REG32(ADR_TX_ID_ALL_INFO)) = (0x00000000)
+#define DEF_RD_ID2() (REG32(ADR_RD_ID2)) = (0x00000000)
+#define DEF_RD_ID3() (REG32(ADR_RD_ID3)) = (0x00000000)
+#define DEF_TX_ID2() (REG32(ADR_TX_ID2)) = (0x00000000)
+#define DEF_TX_ID3() (REG32(ADR_TX_ID3)) = (0x00000000)
+#define DEF_RX_ID2() (REG32(ADR_RX_ID2)) = (0x00000000)
+#define DEF_RX_ID3() (REG32(ADR_RX_ID3)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO2() (REG32(ADR_TX_ID_ALL_INFO2)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO_A() (REG32(ADR_TX_ID_ALL_INFO_A)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO_B() (REG32(ADR_TX_ID_ALL_INFO_B)) = (0x00000000)
+#define DEF_TX_ID_REMAIN_STATUS2() (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (0x01000100)
+#define DEF_ALC_ID_INFO() (REG32(ADR_ALC_ID_INFO)) = (0x00000000)
+#define DEF_ALC_ID_INF1() (REG32(ADR_ALC_ID_INF1)) = (0x00000000)
+#define DEF_PHY_EN_0() (REG32(ADR_PHY_EN_0)) = (0x00000014)
+#define DEF_PHY_EN_1() (REG32(ADR_PHY_EN_1)) = (0x00000000)
+#define DEF_SVN_VERSION_REG() (REG32(ADR_SVN_VERSION_REG)) = (0x00000000)
+#define DEF_PHY_PKT_GEN_0() (REG32(ADR_PHY_PKT_GEN_0)) = (0x00000064)
+#define DEF_PHY_PKT_GEN_1() (REG32(ADR_PHY_PKT_GEN_1)) = (0x00000fff)
+#define DEF_PHY_PKT_GEN_2() (REG32(ADR_PHY_PKT_GEN_2)) = (0x00000003)
+#define DEF_PHY_PKT_GEN_3() (REG32(ADR_PHY_PKT_GEN_3)) = (0x005a0220)
+#define DEF_PHY_PKT_GEN_4() (REG32(ADR_PHY_PKT_GEN_4)) = (0x00000001)
+#define DEF_PHY_REG_00() (REG32(ADR_PHY_REG_00)) = (0x10000000)
+#define DEF_PHY_REG_01() (REG32(ADR_PHY_REG_01)) = (0x00000000)
+#define DEF_PHY_REG_02_AGC() (REG32(ADR_PHY_REG_02_AGC)) = (0x80046771)
+#define DEF_PHY_REG_03_AGC() (REG32(ADR_PHY_REG_03_AGC)) = (0x1f300f6f)
+#define DEF_PHY_REG_04_AGC() (REG32(ADR_PHY_REG_04_AGC)) = (0x663f36d0)
+#define DEF_PHY_REG_05_AGC() (REG32(ADR_PHY_REG_05_AGC)) = (0x106c0000)
+#define DEF_PHY_REG_06_11B_DAGC() (REG32(ADR_PHY_REG_06_11B_DAGC)) = (0x01603fff)
+#define DEF_PHY_REG_07_11B_DAGC() (REG32(ADR_PHY_REG_07_11B_DAGC)) = (0x00600808)
+#define DEF_PHY_REG_08_11GN_DAGC() (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (0xff000160)
+#define DEF_PHY_REG_09_11GN_DAGC() (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (0x00080840)
+#define DEF_PHY_READ_REG_00_DIG_PWR() (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (0x00000000)
+#define DEF_PHY_READ_REG_01_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (0x00000000)
+#define DEF_PHY_READ_REG_02_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (0x00000000)
+#define DEF_PHY_READ_REG_03_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (0x00000000)
+#define DEF_PHY_REG_10_TX_DES() (REG32(ADR_PHY_REG_10_TX_DES)) = (0x00010405)
+#define DEF_PHY_REG_11_TX_DES() (REG32(ADR_PHY_REG_11_TX_DES)) = (0x06090813)
+#define DEF_PHY_REG_12_TX_DES() (REG32(ADR_PHY_REG_12_TX_DES)) = (0x12070000)
+#define DEF_PHY_REG_13_RX_DES() (REG32(ADR_PHY_REG_13_RX_DES)) = (0x01000405)
+#define DEF_PHY_REG_14_RX_DES() (REG32(ADR_PHY_REG_14_RX_DES)) = (0x06090813)
+#define DEF_PHY_REG_15_RX_DES() (REG32(ADR_PHY_REG_15_RX_DES)) = (0x12010000)
+#define DEF_PHY_REG_16_TX_DES_EXCP() (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (0x00000000)
+#define DEF_PHY_REG_17_TX_DES_EXCP() (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (0x10110000)
+#define DEF_PHY_REG_18_RSSI_SNR() (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (0x00fc000f)
+#define DEF_PHY_REG_19_DAC_MANUAL() (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (0x00000000)
+#define DEF_PHY_REG_20_MRX_CNT() (REG32(ADR_PHY_REG_20_MRX_CNT)) = (0x00000000)
+#define DEF_PHY_REG_21_TRX_RAMP() (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (0x3c012801)
+#define DEF_PHY_REG_22_TRX_RAMP() (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (0x24243724)
+#define DEF_PHY_REG_23_ANT() (REG32(ADR_PHY_REG_23_ANT)) = (0x00000011)
+#define DEF_PHY_REG_24_MTX_LEN_CNT() (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_REG_25_MTX_LEN_CNT() (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_REG_26_MRX_LEN_CNT() (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_REG_27_MRX_LEN_CNT() (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_READ_REG_04() (REG32(ADR_PHY_READ_REG_04)) = (0x00000000)
+#define DEF_PHY_READ_REG_05() (REG32(ADR_PHY_READ_REG_05)) = (0x00000000)
+#define DEF_PHY_REG_28_BIST() (REG32(ADR_PHY_REG_28_BIST)) = (0x0000fe3e)
+#define DEF_PHY_READ_REG_06_BIST() (REG32(ADR_PHY_READ_REG_06_BIST)) = (0x00000000)
+#define DEF_PHY_READ_REG_07_BIST() (REG32(ADR_PHY_READ_REG_07_BIST)) = (0x00000000)
+#define DEF_PHY_REG_29_MTRX_MAC() (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (0xffffffff)
+#define DEF_PHY_READ_REG_08_MTRX_MAC() (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (0x00000000)
+#define DEF_PHY_READ_REG_09_MTRX_MAC() (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (0x00000000)
+#define DEF_PHY_REG_30_TX_UP_FIL() (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (0x0ead04f5)
+#define DEF_PHY_REG_31_TX_UP_FIL() (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (0x0fd60080)
+#define DEF_PHY_REG_32_TX_UP_FIL() (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (0x00000009)
+#define DEF_PHY_READ_TBUS() (REG32(ADR_PHY_READ_TBUS)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_00() (REG32(ADR_TX_11B_FIL_COEF_00)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_01() (REG32(ADR_TX_11B_FIL_COEF_01)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_02() (REG32(ADR_TX_11B_FIL_COEF_02)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_03() (REG32(ADR_TX_11B_FIL_COEF_03)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_04() (REG32(ADR_TX_11B_FIL_COEF_04)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_05() (REG32(ADR_TX_11B_FIL_COEF_05)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_06() (REG32(ADR_TX_11B_FIL_COEF_06)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_07() (REG32(ADR_TX_11B_FIL_COEF_07)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_08() (REG32(ADR_TX_11B_FIL_COEF_08)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_09() (REG32(ADR_TX_11B_FIL_COEF_09)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_10() (REG32(ADR_TX_11B_FIL_COEF_10)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_11() (REG32(ADR_TX_11B_FIL_COEF_11)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_12() (REG32(ADR_TX_11B_FIL_COEF_12)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_13() (REG32(ADR_TX_11B_FIL_COEF_13)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_14() (REG32(ADR_TX_11B_FIL_COEF_14)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_15() (REG32(ADR_TX_11B_FIL_COEF_15)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_16() (REG32(ADR_TX_11B_FIL_COEF_16)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_17() (REG32(ADR_TX_11B_FIL_COEF_17)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_18() (REG32(ADR_TX_11B_FIL_COEF_18)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_19() (REG32(ADR_TX_11B_FIL_COEF_19)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_20() (REG32(ADR_TX_11B_FIL_COEF_20)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_21() (REG32(ADR_TX_11B_FIL_COEF_21)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_22() (REG32(ADR_TX_11B_FIL_COEF_22)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_23() (REG32(ADR_TX_11B_FIL_COEF_23)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_24() (REG32(ADR_TX_11B_FIL_COEF_24)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_25() (REG32(ADR_TX_11B_FIL_COEF_25)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_26() (REG32(ADR_TX_11B_FIL_COEF_26)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_27() (REG32(ADR_TX_11B_FIL_COEF_27)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_28() (REG32(ADR_TX_11B_FIL_COEF_28)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_29() (REG32(ADR_TX_11B_FIL_COEF_29)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_30() (REG32(ADR_TX_11B_FIL_COEF_30)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_31() (REG32(ADR_TX_11B_FIL_COEF_31)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_32() (REG32(ADR_TX_11B_FIL_COEF_32)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_33() (REG32(ADR_TX_11B_FIL_COEF_33)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_34() (REG32(ADR_TX_11B_FIL_COEF_34)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_35() (REG32(ADR_TX_11B_FIL_COEF_35)) = (0x00000005)
+#define DEF_TX_11B_FIL_COEF_36() (REG32(ADR_TX_11B_FIL_COEF_36)) = (0x0000003d)
+#define DEF_TX_11B_FIL_COEF_37() (REG32(ADR_TX_11B_FIL_COEF_37)) = (0x00000162)
+#define DEF_TX_11B_FIL_COEF_38() (REG32(ADR_TX_11B_FIL_COEF_38)) = (0x00000400)
+#define DEF_TX_11B_FIL_COEF_39() (REG32(ADR_TX_11B_FIL_COEF_39)) = (0x00000699)
+#define DEF_TX_11B_FIL_COEF_40() (REG32(ADR_TX_11B_FIL_COEF_40)) = (0x00000787)
+#define DEF_TX_11B_PLCP() (REG32(ADR_TX_11B_PLCP)) = (0x00000000)
+#define DEF_TX_11B_RAMP() (REG32(ADR_TX_11B_RAMP)) = (0x0000403c)
+#define DEF_TX_11B_EN_CNT_RST_N() (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (0x00000001)
+#define DEF_TX_11B_EN_CNT() (REG32(ADR_TX_11B_EN_CNT)) = (0x00000000)
+#define DEF_TX_11B_PKT_GEN_CNT() (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (0x00000000)
+#define DEF_RX_11B_DES_DLY() (REG32(ADR_RX_11B_DES_DLY)) = (0x00000044)
+#define DEF_RX_11B_CCA_0() (REG32(ADR_RX_11B_CCA_0)) = (0x00040000)
+#define DEF_RX_11B_CCA_1() (REG32(ADR_RX_11B_CCA_1)) = (0x00400040)
+#define DEF_RX_11B_TR_KP_KI_0() (REG32(ADR_RX_11B_TR_KP_KI_0)) = (0x00003467)
+#define DEF_RX_11B_TR_KP_KI_1() (REG32(ADR_RX_11B_TR_KP_KI_1)) = (0x00540000)
+#define DEF_RX_11B_CE_CNT_THRESHOLD() (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (0x12243615)
+#define DEF_RX_11B_CE_MU_0() (REG32(ADR_RX_11B_CE_MU_0)) = (0x00390002)
+#define DEF_RX_11B_CE_MU_1() (REG32(ADR_RX_11B_CE_MU_1)) = (0x03456777)
+#define DEF_RX_11B_EQ_MU_0() (REG32(ADR_RX_11B_EQ_MU_0)) = (0x00350046)
+#define DEF_RX_11B_EQ_MU_1() (REG32(ADR_RX_11B_EQ_MU_1)) = (0x00570057)
+#define DEF_RX_11B_EQ_CR_KP_KI() (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (0x00236700)
+#define DEF_RX_11B_LPF_RATE() (REG32(ADR_RX_11B_LPF_RATE)) = (0x000d1746)
+#define DEF_RX_11B_CIT_CNT_THRESHOLD() (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (0x04061787)
+#define DEF_RX_11B_EQ_CH_MAIN_TAP() (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (0x07800000)
+#define DEF_RX_11B_SEARCH_CNT_TH() (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (0x00c0000a)
+#define DEF_RX_11B_CCA_CONTROL() (REG32(ADR_RX_11B_CCA_CONTROL)) = (0x00000000)
+#define DEF_RX_11B_FREQUENCY_OFFSET() (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (0x00000000)
+#define DEF_RX_11B_SNR_RSSI() (REG32(ADR_RX_11B_SNR_RSSI)) = (0x00000000)
+#define DEF_RX_11B_SFD_CRC_CNT() (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (0x00000000)
+#define DEF_RX_11B_PKT_ERR_AND_PKT_ERR_CNT() (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (0x00000000)
+#define DEF_RX_11B_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
+#define DEF_RX_11B_SFD_FILED_0() (REG32(ADR_RX_11B_SFD_FILED_0)) = (0x00000000)
+#define DEF_RX_11B_SFD_FIELD_1() (REG32(ADR_RX_11B_SFD_FIELD_1)) = (0x00000000)
+#define DEF_RX_11B_PKT_STAT_EN() (REG32(ADR_RX_11B_PKT_STAT_EN)) = (0x00100000)
+#define DEF_RX_11B_SOFT_RST() (REG32(ADR_RX_11B_SOFT_RST)) = (0x00000001)
+#define DEF_TX_11GN_RAMP() (REG32(ADR_TX_11GN_RAMP)) = (0x0000233c)
+#define DEF_TX_11GN_PLCP() (REG32(ADR_TX_11GN_PLCP)) = (0x5d08908e)
+#define DEF_TX_11GN_PKT_GEN_CNT() (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (0x00000000)
+#define DEF_TX_11GN_PLCP_CRC_ERR_CNT() (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (0x00000000)
+#define DEF_RX_11GN_DES_DLY() (REG32(ADR_RX_11GN_DES_DLY)) = (0x00000044)
+#define DEF_RX_11GN_TR_0() (REG32(ADR_RX_11GN_TR_0)) = (0x00750075)
+#define DEF_RX_11GN_TR_1() (REG32(ADR_RX_11GN_TR_1)) = (0x00000075)
+#define DEF_RX_11GN_TR_2() (REG32(ADR_RX_11GN_TR_2)) = (0x10000075)
+#define DEF_RX_11GN_CCA_0() (REG32(ADR_RX_11GN_CCA_0)) = (0x38324705)
+#define DEF_RX_11GN_CCA_1() (REG32(ADR_RX_11GN_CCA_1)) = (0x30182000)
+#define DEF_RX_11GN_CCA_2() (REG32(ADR_RX_11GN_CCA_2)) = (0x20600000)
+#define DEF_RX_11GN_CCA_FFT_SCALE() (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (0x0a010100)
+#define DEF_RX_11GN_SOFT_DEMAP_0() (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (0x50505050)
+#define DEF_RX_11GN_SOFT_DEMAP_1() (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (0x50000000)
+#define DEF_RX_11GN_SOFT_DEMAP_2() (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (0x50505050)
+#define DEF_RX_11GN_SOFT_DEMAP_3() (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (0x50505050)
+#define DEF_RX_11GN_SOFT_DEMAP_4() (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (0x50000000)
+#define DEF_RX_11GN_SOFT_DEMAP_5() (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (0x00000000)
+#define DEF_RX_11GN_SYM_BOUND_0() (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (0x00001420)
+#define DEF_RX_11GN_SYM_BOUND_1() (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (0x0000200a)
+#define DEF_RX_11GN_CCA_PWR() (REG32(ADR_RX_11GN_CCA_PWR)) = (0x30000280)
+#define DEF_RX_11GN_CCA_CNT() (REG32(ADR_RX_11GN_CCA_CNT)) = (0x30023002)
+#define DEF_RX_11GN_CCA_ATCOR_RE_CHECK() (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (0x0000003a)
+#define DEF_RX_11GN_VTB_TB() (REG32(ADR_RX_11GN_VTB_TB)) = (0x40000000)
+#define DEF_RX_11GN_ERR_UPDATE() (REG32(ADR_RX_11GN_ERR_UPDATE)) = (0x009e007e)
+#define DEF_RX_11GN_SHORT_GI() (REG32(ADR_RX_11GN_SHORT_GI)) = (0x00044400)
+#define DEF_RX_11GN_CHANNEL_UPDATE() (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (0x82000000)
+#define DEF_RX_11GN_PKT_FORMAT_0() (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (0x02003030)
+#define DEF_RX_11GN_PKT_FORMAT_1() (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (0x092a092a)
+#define DEF_RX_11GN_TX_TIME() (REG32(ADR_RX_11GN_TX_TIME)) = (0x00700010)
+#define DEF_RX_11GN_STBC_TR_KP_KI() (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (0x00007575)
+#define DEF_RX_11GN_BIST_0() (REG32(ADR_RX_11GN_BIST_0)) = (0x0001fe3e)
+#define DEF_RX_11GN_BIST_1() (REG32(ADR_RX_11GN_BIST_1)) = (0x0000fe3e)
+#define DEF_RX_11GN_BIST_2() (REG32(ADR_RX_11GN_BIST_2)) = (0x00000000)
+#define DEF_RX_11GN_BIST_3() (REG32(ADR_RX_11GN_BIST_3)) = (0x00000000)
+#define DEF_RX_11GN_BIST_4() (REG32(ADR_RX_11GN_BIST_4)) = (0x00000000)
+#define DEF_RX_11GN_BIST_5() (REG32(ADR_RX_11GN_BIST_5)) = (0x00000000)
+#define DEF_RX_11GN_SPECTRUM_ANALYZER() (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (0x00000000)
+#define DEF_RX_11GN_READ_0() (REG32(ADR_RX_11GN_READ_0)) = (0x00000000)
+#define DEF_RX_11GN_FREQ_OFFSET() (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (0x00000000)
+#define DEF_RX_11GN_SIGNAL_FIELD_0() (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (0x00000000)
+#define DEF_RX_11GN_SIGNAL_FIELD_1() (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (0x00000000)
+#define DEF_RX_11GN_PKT_ERR_CNT() (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (0x00000000)
+#define DEF_RX_11GN_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
+#define DEF_RX_11GN_SERVICE_LENGTH_FIELD() (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (0x00000000)
+#define DEF_RX_11GN_RATE() (REG32(ADR_RX_11GN_RATE)) = (0x00000000)
+#define DEF_RX_11GN_STAT_EN() (REG32(ADR_RX_11GN_STAT_EN)) = (0x00100001)
+#define DEF_RX_11GN_SOFT_RST() (REG32(ADR_RX_11GN_SOFT_RST)) = (0x00000001)
+#define DEF_RF_CONTROL_0() (REG32(ADR_RF_CONTROL_0)) = (0x00000000)
+#define DEF_RF_CONTROL_1() (REG32(ADR_RF_CONTROL_1)) = (0x00008000)
+#define DEF_TX_IQ_CONTROL_0() (REG32(ADR_TX_IQ_CONTROL_0)) = (0x00200020)
+#define DEF_TX_IQ_CONTROL_1() (REG32(ADR_TX_IQ_CONTROL_1)) = (0x00028080)
+#define DEF_TX_IQ_CONTROL_2() (REG32(ADR_TX_IQ_CONTROL_2)) = (0x00000000)
+#define DEF_TX_COMPENSATION_CONTROL() (REG32(ADR_TX_COMPENSATION_CONTROL)) = (0x00000000)
+#define DEF_RX_COMPENSATION_CONTROL() (REG32(ADR_RX_COMPENSATION_CONTROL)) = (0x00000000)
+#define DEF_RX_OBSERVATION_CIRCUIT_0() (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (0x000028ff)
+#define DEF_RX_OBSERVATION_CIRCUIT_1() (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (0x00000000)
+#define DEF_RX_OBSERVATION_CIRCUIT_2() (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (0x00000000)
+#define DEF_RX_OBSERVATION_CIRCUIT_3() (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (0x00000000)
+#define DEF_RF_IQ_CONTROL_0() (REG32(ADR_RF_IQ_CONTROL_0)) = (0x00000202)
+#define DEF_RF_IQ_CONTROL_1() (REG32(ADR_RF_IQ_CONTROL_1)) = (0x00ffc200)
+#define DEF_RF_IQ_CONTROL_2() (REG32(ADR_RF_IQ_CONTROL_2)) = (0x00000000)
+#define DEF_RF_IQ_CONTROL_3() (REG32(ADR_RF_IQ_CONTROL_3)) = (0x00000000)
+#define DEF_DPD_CONTROL() (REG32(ADR_DPD_CONTROL)) = (0x00000000)
+#define DEF_DPD_GAIN_TABLE_0() (REG32(ADR_DPD_GAIN_TABLE_0)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_1() (REG32(ADR_DPD_GAIN_TABLE_1)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_2() (REG32(ADR_DPD_GAIN_TABLE_2)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_3() (REG32(ADR_DPD_GAIN_TABLE_3)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_4() (REG32(ADR_DPD_GAIN_TABLE_4)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_5() (REG32(ADR_DPD_GAIN_TABLE_5)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_6() (REG32(ADR_DPD_GAIN_TABLE_6)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_7() (REG32(ADR_DPD_GAIN_TABLE_7)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_8() (REG32(ADR_DPD_GAIN_TABLE_8)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_9() (REG32(ADR_DPD_GAIN_TABLE_9)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_A() (REG32(ADR_DPD_GAIN_TABLE_A)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_B() (REG32(ADR_DPD_GAIN_TABLE_B)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_C() (REG32(ADR_DPD_GAIN_TABLE_C)) = (0x02000200)
+#define DEF_DPD_PH_TABLE_0() (REG32(ADR_DPD_PH_TABLE_0)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_1() (REG32(ADR_DPD_PH_TABLE_1)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_2() (REG32(ADR_DPD_PH_TABLE_2)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_3() (REG32(ADR_DPD_PH_TABLE_3)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_4() (REG32(ADR_DPD_PH_TABLE_4)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_5() (REG32(ADR_DPD_PH_TABLE_5)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_6() (REG32(ADR_DPD_PH_TABLE_6)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_7() (REG32(ADR_DPD_PH_TABLE_7)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_8() (REG32(ADR_DPD_PH_TABLE_8)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_9() (REG32(ADR_DPD_PH_TABLE_9)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_A() (REG32(ADR_DPD_PH_TABLE_A)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_B() (REG32(ADR_DPD_PH_TABLE_B)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_C() (REG32(ADR_DPD_PH_TABLE_C)) = (0x00000000)
+#define DEF_DPD_GAIN_ESTIMATION_0() (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (0x00000000)
+#define DEF_DPD_GAIN_ESTIMATION_1() (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (0x00000100)
+#define DEF_DPD_GAIN_ESTIMATION_2() (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (0x00000000)
+#define DEF_TX_GAIN_FACTOR() (REG32(ADR_TX_GAIN_FACTOR)) = (0x80808080)
+#define DEF_HARD_WIRE_PIN_REGISTER() (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
+#define DEF_MANUAL_ENABLE_REGISTER() (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (0x00000fc0)
+#define DEF_LDO_REGISTER() (REG32(ADR_LDO_REGISTER)) = (0x000db71b)
+#define DEF_ABB_REGISTER_1() (REG32(ADR_ABB_REGISTER_1)) = (0x151558dd)
+#define DEF_ABB_REGISTER_2() (REG32(ADR_ABB_REGISTER_2)) = (0x01011a88)
+#define DEF_TX_FE_REGISTER() (REG32(ADR_TX_FE_REGISTER)) = (0x3d3e84fe)
+#define DEF_RX_FE_REGISTER_1() (REG32(ADR_RX_FE_REGISTER_1)) = (0x03457579)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
+#define DEF_RX_TX_FSM_REGISTER() (REG32(ADR_RX_TX_FSM_REGISTER)) = (0x00030ca8)
+#define DEF_RX_ADC_REGISTER() (REG32(ADR_RX_ADC_REGISTER)) = (0x20ea0224)
+#define DEF_TX_DAC_REGISTER() (REG32(ADR_TX_DAC_REGISTER)) = (0x44000655)
+#define DEF_SX_ENABLE_REGISTER() (REG32(ADR_SX_ENABLE_REGISTER)) = (0x0003e07c)
+#define DEF_SYN_REGISTER_1() (REG32(ADR_SYN_REGISTER_1)) = (0xaa800000)
+#define DEF_SYN_REGISTER_2() (REG32(ADR_SYN_REGISTER_2)) = (0x00550800)
+#define DEF_SYN_PFD_CHP() (REG32(ADR_SYN_PFD_CHP)) = (0x07c0894a)
+#define DEF_SYN_VCO_LOBF() (REG32(ADR_SYN_VCO_LOBF)) = (0xfcccca27)
+#define DEF_SYN_DIV_SDM_XOSC() (REG32(ADR_SYN_DIV_SDM_XOSC)) = (0x07700830)
+#define DEF_SYN_KVCO_XO_FINE_TUNE_CBANK() (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (0x00440000)
+#define DEF_SYN_LCK_VT() (REG32(ADR_SYN_LCK_VT)) = (0x00007ff4)
+#define DEF_DPLL_VCO_REGISTER() (REG32(ADR_DPLL_VCO_REGISTER)) = (0x0000000e)
+#define DEF_DPLL_CP_PFD_REGISTER() (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (0x00088008)
+#define DEF_DPLL_DIVIDER_REGISTER() (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (0x00406000)
+#define DEF_DCOC_IDAC_REGISTER1() (REG32(ADR_DCOC_IDAC_REGISTER1)) = (0x08820820)
+#define DEF_DCOC_IDAC_REGISTER2() (REG32(ADR_DCOC_IDAC_REGISTER2)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER3() (REG32(ADR_DCOC_IDAC_REGISTER3)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER4() (REG32(ADR_DCOC_IDAC_REGISTER4)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER5() (REG32(ADR_DCOC_IDAC_REGISTER5)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER6() (REG32(ADR_DCOC_IDAC_REGISTER6)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER7() (REG32(ADR_DCOC_IDAC_REGISTER7)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER8() (REG32(ADR_DCOC_IDAC_REGISTER8)) = (0x00820820)
+#define DEF_RCAL_REGISTER() (REG32(ADR_RCAL_REGISTER)) = (0x00004080)
+#define DEF_SX_LCK_BIN_REGISTERS_I() (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (0x20080080)
+#define DEF_TRX_DUMMY_REGISTER() (REG32(ADR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_SX_DUMMY_REGISTER() (REG32(ADR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_DPLL_FB_DIVIDER_REGISTERS_II() (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (0x00ec2ec5)
+#define DEF_SX_LCK_BIN_REGISTERS_II() (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (0x00000f13)
+#define DEF_RC_OSC_32K_CAL_REGISTERS() (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (0x00098900)
+#define DEF_RF_D_DIGITAL_DEBUG_PORT_REGISTER() (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (0x00000000)
+#define DEF_MMU_CTRL() (REG32(ADR_MMU_CTRL)) = (0x00002042)
+#define DEF_HS_CTRL() (REG32(ADR_HS_CTRL)) = (0x00000000)
+#define DEF_CPU_POR0_7() (REG32(ADR_CPU_POR0_7)) = (0x00000000)
+#define DEF_CPU_POR8_F() (REG32(ADR_CPU_POR8_F)) = (0x00000000)
+#define DEF_REG_LEN_CTRL() (REG32(ADR_REG_LEN_CTRL)) = (0x00000f0f)
+#define DEF_DMN_READ_BYPASS() (REG32(ADR_DMN_READ_BYPASS)) = (0x0000ffff)
+#define DEF_ALC_RLS_ABORT() (REG32(ADR_ALC_RLS_ABORT)) = (0x00000000)
+#define DEF_DEBUG_CTL() (REG32(ADR_DEBUG_CTL)) = (0x00000000)
+#define DEF_DEBUG_OUT() (REG32(ADR_DEBUG_OUT)) = (0x00000000)
+#define DEF_MMU_STATUS() (REG32(ADR_MMU_STATUS)) = (0x00000000)
+#define DEF_DMN_STATUS() (REG32(ADR_DMN_STATUS)) = (0x00000000)
+#define DEF_TAG_STATUS() (REG32(ADR_TAG_STATUS)) = (0x00000000)
+#define DEF_DMN_MCU_STATUS() (REG32(ADR_DMN_MCU_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_0_STATUS() (REG32(ADR_MB_IDTBL_0_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_1_STATUS() (REG32(ADR_MB_IDTBL_1_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_2_STATUS() (REG32(ADR_MB_IDTBL_2_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_3_STATUS() (REG32(ADR_MB_IDTBL_3_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_0_STATUS() (REG32(ADR_PKT_IDTBL_0_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_1_STATUS() (REG32(ADR_PKT_IDTBL_1_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_2_STATUS() (REG32(ADR_PKT_IDTBL_2_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_3_STATUS() (REG32(ADR_PKT_IDTBL_3_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_0_STATUS() (REG32(ADR_DMN_IDTBL_0_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_1_STATUS() (REG32(ADR_DMN_IDTBL_1_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_2_STATUS() (REG32(ADR_DMN_IDTBL_2_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_3_STATUS() (REG32(ADR_DMN_IDTBL_3_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_0_STATUS() (REG32(ADR_MB_NEQID_0_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_1_STATUS() (REG32(ADR_MB_NEQID_1_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_2_STATUS() (REG32(ADR_MB_NEQID_2_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_3_STATUS() (REG32(ADR_MB_NEQID_3_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_0_STATUS() (REG32(ADR_PKT_NEQID_0_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_1_STATUS() (REG32(ADR_PKT_NEQID_1_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_2_STATUS() (REG32(ADR_PKT_NEQID_2_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_3_STATUS() (REG32(ADR_PKT_NEQID_3_STATUS)) = (0x00000000)
+#define DEF_ALC_NOCHG_ID_STATUS() (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_0() (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_1() (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_2() (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_3() (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_4() (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_5() (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_6() (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_7() (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (0x00000000)
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h b/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
new file mode 100644
index 00000000000..e15a481ba30
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "ssv6200_reg.h"
+#define BANK_COUNT 49
+static const u32 BASE_BANK_SSV6200[] = {
+	SYS_REG_BASE,
+	WBOOT_REG_BASE,
+	TU0_US_REG_BASE,
+	TU1_US_REG_BASE,
+	TU2_US_REG_BASE,
+	TU3_US_REG_BASE,
+	TM0_MS_REG_BASE,
+	TM1_MS_REG_BASE,
+	TM2_MS_REG_BASE,
+	TM3_MS_REG_BASE,
+	MCU_WDT_REG_BASE,
+	SYS_WDT_REG_BASE,
+	GPIO_REG_BASE,
+	SD_REG_BASE,
+	SPI_REG_BASE,
+	CSR_I2C_MST_BASE,
+	UART_REG_BASE,
+	DAT_UART_REG_BASE,
+	INT_REG_BASE,
+	DBG_SPI_REG_BASE,
+	FLASH_SPI_REG_BASE,
+	DMA_REG_BASE,
+	CSR_PMU_BASE,
+	CSR_RTC_BASE,
+	RTC_RAM_BASE,
+	D2_DMA_REG_BASE,
+	HCI_REG_BASE,
+	CO_REG_BASE,
+	EFS_REG_BASE,
+	SMS4_REG_BASE,
+	MRX_REG_BASE,
+	AMPDU_REG_BASE,
+	MT_REG_CSR_BASE,
+	TXQ0_MT_Q_REG_CSR_BASE,
+	TXQ1_MT_Q_REG_CSR_BASE,
+	TXQ2_MT_Q_REG_CSR_BASE,
+	TXQ3_MT_Q_REG_CSR_BASE,
+	TXQ4_MT_Q_REG_CSR_BASE,
+	HIF_INFO_BASE,
+	PHY_RATE_INFO_BASE,
+	MAC_GLB_SET_BASE,
+	BTCX_REG_BASE,
+	MIB_REG_BASE,
+	CBR_A_REG_BASE,
+	MB_REG_BASE,
+	ID_MNG_REG_BASE,
+	CSR_PHY_BASE,
+	CSR_RF_BASE,
+	MMU_REG_BASE,
+	0x00000000
+};
+
+static const char *STR_BANK_SSV6200[] = {
+	"SYS_REG",
+	"WBOOT_REG",
+	"TU0_US_REG",
+	"TU1_US_REG",
+	"TU2_US_REG",
+	"TU3_US_REG",
+	"TM0_MS_REG",
+	"TM1_MS_REG",
+	"TM2_MS_REG",
+	"TM3_MS_REG",
+	"MCU_WDT_REG",
+	"SYS_WDT_REG",
+	"GPIO_REG",
+	"SD_REG",
+	"SPI_REG",
+	"CSR_I2C_MST",
+	"UART_REG",
+	"DAT_UART_REG",
+	"INT_REG",
+	"DBG_SPI_REG",
+	"FLASH_SPI_REG",
+	"DMA_REG",
+	"CSR_PMU",
+	"CSR_RTC",
+	"RTC_RAM",
+	"D2_DMA_REG",
+	"HCI_REG",
+	"CO_REG",
+	"EFS_REG",
+	"SMS4_REG",
+	"MRX_REG",
+	"AMPDU_REG",
+	"MT_REG_CSR",
+	"TXQ0_MT_Q_REG_CSR",
+	"TXQ1_MT_Q_REG_CSR",
+	"TXQ2_MT_Q_REG_CSR",
+	"TXQ3_MT_Q_REG_CSR",
+	"TXQ4_MT_Q_REG_CSR",
+	"HIF_INFO",
+	"PHY_RATE_INFO",
+	"MAC_GLB_SET",
+	"BTCX_REG",
+	"MIB_REG",
+	"CBR_A_REG",
+	"MB_REG",
+	"ID_MNG_REG",
+	"CSR_PHY",
+	"CSR_RF",
+	"MMU_REG",
+	""
+};
+
+static const u32 SIZE_BANK_SSV6200[] = {
+	SYS_REG_BANK_SIZE,
+	WBOOT_REG_BANK_SIZE,
+	TU0_US_REG_BANK_SIZE,
+	TU1_US_REG_BANK_SIZE,
+	TU2_US_REG_BANK_SIZE,
+	TU3_US_REG_BANK_SIZE,
+	TM0_MS_REG_BANK_SIZE,
+	TM1_MS_REG_BANK_SIZE,
+	TM2_MS_REG_BANK_SIZE,
+	TM3_MS_REG_BANK_SIZE,
+	MCU_WDT_REG_BANK_SIZE,
+	SYS_WDT_REG_BANK_SIZE,
+	GPIO_REG_BANK_SIZE,
+	SD_REG_BANK_SIZE,
+	SPI_REG_BANK_SIZE,
+	CSR_I2C_MST_BANK_SIZE,
+	UART_REG_BANK_SIZE,
+	DAT_UART_REG_BANK_SIZE,
+	INT_REG_BANK_SIZE,
+	DBG_SPI_REG_BANK_SIZE,
+	FLASH_SPI_REG_BANK_SIZE,
+	DMA_REG_BANK_SIZE,
+	CSR_PMU_BANK_SIZE,
+	CSR_RTC_BANK_SIZE,
+	RTC_RAM_BANK_SIZE,
+	D2_DMA_REG_BANK_SIZE,
+	HCI_REG_BANK_SIZE,
+	CO_REG_BANK_SIZE,
+	EFS_REG_BANK_SIZE,
+	SMS4_REG_BANK_SIZE,
+	MRX_REG_BANK_SIZE,
+	AMPDU_REG_BANK_SIZE,
+	MT_REG_CSR_BANK_SIZE,
+	TXQ0_MT_Q_REG_CSR_BANK_SIZE,
+	TXQ1_MT_Q_REG_CSR_BANK_SIZE,
+	TXQ2_MT_Q_REG_CSR_BANK_SIZE,
+	TXQ3_MT_Q_REG_CSR_BANK_SIZE,
+	TXQ4_MT_Q_REG_CSR_BANK_SIZE,
+	HIF_INFO_BANK_SIZE,
+	PHY_RATE_INFO_BANK_SIZE,
+	MAC_GLB_SET_BANK_SIZE,
+	BTCX_REG_BANK_SIZE,
+	MIB_REG_BANK_SIZE,
+	CBR_A_REG_BANK_SIZE,
+	MB_REG_BANK_SIZE,
+	ID_MNG_REG_BANK_SIZE,
+	CSR_PHY_BANK_SIZE,
+	CSR_RF_BANK_SIZE,
+	MMU_REG_BANK_SIZE,
+	0x00000000
+};
diff --git a/drivers/net/wireless/ssv6051/include/ssv_cfg.h b/drivers/net/wireless/ssv6051/include/ssv_cfg.h
new file mode 100644
index 00000000000..79b75619936
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv_cfg.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_CFG_H_
+#define _SSV_CFG_H_
+#define SSV6200_HW_CAP_HT 0x00000001
+#define SSV6200_HW_CAP_GF 0x00000002
+#define SSV6200_HW_CAP_2GHZ 0x00000004
+#define SSV6200_HW_CAP_5GHZ 0x00000008
+#define SSV6200_HW_CAP_SECURITY 0x00000010
+#define SSV6200_HT_CAP_SGI_20 0x00000020
+#define SSV6200_HT_CAP_SGI_40 0x00000040
+#define SSV6200_HW_CAP_AP 0x00000080
+#define SSV6200_HW_CAP_P2P 0x00000100
+#define SSV6200_HW_CAP_AMPDU_RX 0x00000200
+#define SSV6200_HW_CAP_AMPDU_TX 0x00000400
+#define SSV6200_HW_CAP_TDLS 0x00000800
+#define EXTERNEL_CONFIG_SUPPORT 64
+struct ssv6xxx_cfg {
+	u32 hw_caps;
+	u32 def_chan;
+	u32 crystal_type;
+	u32 volt_regulator;
+	u32 force_chip_identity;
+	u8 maddr[2][6];
+	u32 n_maddr;
+	u32 use_wpa2_only;
+	u32 ignore_reset_in_ap;
+	u32 r_calbration_result;
+	u32 sar_result;
+	u32 crystal_frequency_offset;
+	u32 tx_power_index_1;
+	u32 tx_power_index_2;
+	u32 chip_identity;
+	u32 wifi_tx_gain_level_gn;
+	u32 wifi_tx_gain_level_b;
+	u32 rssi_ctl;
+	u32 sr_bhvr;
+	u32 configuration[EXTERNEL_CONFIG_SUPPORT + 1][2];
+	u8 firmware_path[128];
+	u8 flash_bin_path[128];
+	u8 mac_address_path[128];
+	u8 mac_output_path[128];
+	u32 ignore_efuse_mac;
+	u32 mac_address_mode;
+};
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h b/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
new file mode 100644
index 00000000000..7fabbe308f9
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_FIRMWARE_VERSION_H_
+#define _SSV_FIRMWARE_VERSION_H_
+static u32 ssv_firmware_version = 16380;
+#define SSV_FIRMWARE_URl "http://192.168.15.30/svn/software/wifi/tag/smac-release-tag/6051.Q0.1009.21.000000/ssv6xxx/smac/firmware"
+#define FIRMWARE_COMPILERHOST "ssv-ThinkPad-X230"
+#define FIRMWARE_COMPILERDATE "11-06-2017-09:17:18"
+#define FIRMWARE_COMPILEROS "linux"
+#define FIRMWARE_COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/ssv_version.h b/drivers/net/wireless/ssv6051/include/ssv_version.h
new file mode 100644
index 00000000000..99be5354f78
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv_version.h
@@ -0,0 +1,12 @@
+#ifndef _SSV_VERSION_H_
+#define _SSV_VERSION_H_
+
+static u32 ssv_root_version = 16529;
+
+#define SSV_ROOT_URl "http://192.168.15.30/svn/software/project/release/android/box/rk3x28/6051.Q0.1009.21.400401/ssv6xxx"
+#define COMPILERHOST "icomm-buildserver-T320"
+#define COMPILERDATE "12-08-2017-10:34:54"
+#define COMPILEROS "linux"
+#define COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
+
+#endif
diff --git a/drivers/net/wireless/ssv6051/platform-config.mak b/drivers/net/wireless/ssv6051/platform-config.mak
new file mode 100644
index 00000000000..566026bb17a
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/platform-config.mak
@@ -0,0 +1,93 @@
+ccflags-y += -DCONFIG_SSV6200_CORE
+
+###########################################################################
+# Compiler options                                                        #
+###########################################################################
+
+# Enable -g to help debug. Deassembly from .o to .S would help to track to 
+# the problomatic line from call stack dump.
+#ccflags-y += -g
+ccflags += -Os
+
+############################################################
+# If you change the settings, please change the file synchronization
+# smac\firmware\include\config.h & compiler firmware
+############################################################
+#ccflags-y += -DCONFIG_SSV_CABRIO_A
+ccflags-y += -DCONFIG_SSV_CABRIO_E
+
+#CONFIG_SSV_SUPPORT_BTCX=y
+
+#ccflags-y += -DDEBUG
+ccflags-y += -DCONFIG_SSV6200_CLI_ENABLE
+
+#PADPD
+#ccflags-y += -DCONFIG_SSV_DPD
+
+#ccflags-y += -DCONFIG_SSV_CABRIO_MB_DEBUG
+#ccflags-y += -DCONFIG_SSV6XXX_DEBUGFS
+
+#SDIO
+ccflags-y += -DCONFIG_SSV_TX_LOWTHRESHOLD
+
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+#ccflags-y += -DKTHREAD_BIND
+#ccflags-y += -DROCKCHIP_WIFI_AUTO_SUPPORT
+ccflags-y += -DCONFIG_SSV_RSSI
+ccflags-y += -DCONFIG_SSV_VENDOR_EXT_SUPPORT
+
+############################################################
+# Rate control update for MPDU.
+############################################################
+ccflags-y += -DRATE_CONTROL_REALTIME_UPDATA
+
+#workaround
+#ccflags-y += -DCONFIG_SSV_CABRIO_EXT_PA
+
+############################################################
+# NOTE:
+#    Only one of the following flags could be turned on.
+# It also turned off the following flags. In this case, 
+# pure software security or pure hardware security is used.
+#
+############################################################
+#ccflags-y += -DCONFIG_SSV_SW_ENCRYPT_HW_DECRYPT
+#ccflags-y += -DCONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
+
+# FOR WFA
+#ccflags-y += -DWIFI_CERTIFIED
+
+#ccflags-y += -DCONFIG_SSV_SDIO_EXT_INT
+
+#######################################################
+ccflags-y += -DCONFIG_SSV6200_HAS_RX_WORKQUEUE
+#ccflags-y += -DUSE_THREAD_RX
+ccflags-y += -DUSE_THREAD_TX
+ccflags-y += -DENABLE_AGGREGATE_IN_TIME
+ccflags-y += -DENABLE_INCREMENTAL_AGGREGATION
+
+# Generic decision table applicable to both AP and STA modes.
+ccflags-y += -DUSE_GENERIC_DECI_TBL
+
+#ccflags-y += -DCONFIG_SSV_WAPI
+
+ccflags-y += -DFW_WSID_WATCH_LIST
+#ccflags-y += -DUSE_BATCH_RX
+#ccflags-y += -DCONFIG_IRQ_DEBUG_COUNT
+
+ccflags-y += -DSSV6200_ECO
+#ccflags-y += -DENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
+ccflags-y += -DHAS_CRYPTO_LOCK
+ccflags-y += -DENABLE_TX_Q_FLOW_CONTROL
+
+#ccflags-y += -DCONFIG_DEBUG_SKB_TIMESTAMP
+
+
+#enable p2p client to parse GO broadcast noa
+#ccflags-y += -DCONFIG_P2P_NOA
+
+#enable rx management frame check
+#ccflags-y += -DCONFIG_RX_MGMT_CHECK
diff --git a/drivers/net/wireless/ssv6051/rules.mak b/drivers/net/wireless/ssv6051/rules.mak
new file mode 100644
index 00000000000..b3262852249
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/rules.mak
@@ -0,0 +1,19 @@
+
+
+$(KMODULE_NAME)-y += $(KERN_SRCS:.c=.o)
+obj-$(CONFIG_SSV6200_CORE) += $(KMODULE_NAME).o
+
+
+.PHONY: all clean install
+
+all:
+	@$(MAKE) -C /lib/modules/$(KVERSION)/build \
+		SUBDIRS=$(KBUILD_DIR) CONFIG_DEBUG_SECTION_MISMATCH=y \
+		modules
+
+clean:
+	@$(MAKE) -C /lib/modules/$(KVERSION)/build SUBDIRS=$(KBUILD_DIR) clean
+
+install:
+	@$(MAKE) INSTALL_MOD_DIR=$(DRVPATH) -C /lib/modules/$(KVERSION)/build \
+	        M=$(KBUILD_DIR) modules_install
diff --git a/drivers/net/wireless/ssv6051/smac/ampdu.c b/drivers/net/wireless/ssv6051/smac/ampdu.c
new file mode 100644
index 00000000000..16e501ee97f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ampdu.c
@@ -0,0 +1,2111 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ap.h"
+#include "sec.h"
+#include "ssv_rc_common.h"
+#include "ssv_ht_rc.h"
+extern struct ieee80211_ops ssv6200_ops;
+
+// Hack: redefine MAX_AMPDU_BUF because buf_size here is a 8-bit char
+// and mainline kernel value is 0x100, which overflows
+#ifdef IEEE80211_MAX_AMPDU_BUF
+#undef IEEE80211_MAX_AMPDU_BUF
+#define IEEE80211_MAX_AMPDU_BUF 0x40
+#endif
+
+#define BA_WAIT_TIMEOUT (800)
+#define AMPDU_BA_FRAME_LEN (68)
+#define ampdu_skb_hdr(skb) ((struct ieee80211_hdr*)((u8*)((skb)->data)+AMPDU_DELIMITER_LEN))
+#define ampdu_skb_ssn(skb) ((ampdu_skb_hdr(skb)->seq_ctrl)>>SSV_SEQ_NUM_SHIFT)
+#define ampdu_hdr_ssn(hdr) ((hdr)->seq_ctrl>>SSV_SEQ_NUM_SHIFT)
+#undef prn_aggr_dbg
+#define prn_aggr_dbg(fmt,...)
+static void void_func(const char *fmt, ...)
+{
+}
+
+#define prn_aggr_err(fmt,...) \
+    do { \
+        void_func(KERN_ERR fmt, ##__VA_ARGS__);\
+    } while (0)
+#define get_tid_aggr_len(agg_len,tid_data) \
+    ({ \
+        u32 agg_max_num = (tid_data)->agg_num_max; \
+        u32 to_agg_len = (agg_len); \
+        (agg_len >= agg_max_num) ? agg_max_num : to_agg_len; \
+    })
+#define INDEX_PKT_BY_SSN(tid,ssn) \
+    ((tid)->aggr_pkts[(ssn) % SSV_AMPDU_BA_WINDOW_SIZE])
+#define NEXT_PKT_SN(sn) \
+    ({ (sn + 1) % SSV_AMPDU_MAX_SSN; })
+#define INC_PKT_SN(sn) \
+    ({ \
+        sn = NEXT_PKT_SN(sn); \
+        sn; \
+    })
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+static ssize_t ampdu_tx_mib_dump(struct ssv_sta_priv_data *ssv_sta_priv,
+				 char *mib_str, ssize_t length);
+static int _dump_ba_skb(char *buf, int buf_size, struct sk_buff *ba_skb);
+#endif
+static struct sk_buff *_aggr_retry_mpdu(struct ssv_softc *sc,
+					struct AMPDU_TID_st *cur_AMPDU_TID,
+					struct sk_buff_head *retry_queue,
+					u32 max_aggr_len);
+static int _dump_BA_notification(char *buf,
+				 struct ampdu_ba_notify_data *ba_notification);
+static struct sk_buff *_alloc_ampdu_skb(struct ssv_softc *sc,
+					struct AMPDU_TID_st *ampdu_tid,
+					u32 len);
+static bool _sync_ampdu_pkt_arr(struct AMPDU_TID_st *ampdu_tid,
+				struct sk_buff *ampdu_skb, bool retry);
+static void _put_mpdu_to_ampdu(struct sk_buff *ampdu, struct sk_buff *mpdu);
+static void _add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb);
+static u32 _flush_early_ampdu_q(struct ssv_softc *sc,
+				struct AMPDU_TID_st *ampdu_tid);
+static bool _is_skb_q_empty(struct ssv_softc *sc, struct sk_buff *skb);
+static void _aggr_ampdu_tx_q(struct ieee80211_hw *hw,
+			     struct AMPDU_TID_st *ampdu_tid);
+static void _queue_early_ampdu(struct ssv_softc *sc,
+			       struct AMPDU_TID_st *ampdu_tid,
+			       struct sk_buff *ampdu_skb);
+static int _mark_skb_retry(struct SKB_info_st *skb_info, struct sk_buff *skb);
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage)
+{
+	unsigned int timeout;
+	SKB_info *mpdu_skb_info;
+	u16 ssn = 0;
+	struct sk_buff *mpdu = NULL;
+	struct ampdu_hdr_st *ampdu_hdr = NULL;
+	ktime_t current_ktime;
+	ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
+	ssn = ampdu_hdr->ssn[0];
+	mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn);
+	if (mpdu == NULL)
+		return 0;
+	mpdu_skb_info = (SKB_info *) (mpdu->head);
+	current_ktime = ktime_get();
+	timeout =
+	    (unsigned int)
+	    ktime_to_ms(ktime_sub(current_ktime, mpdu_skb_info->timestamp));
+	if (timeout > SKB_DURATION_TIMEOUT_MS) {
+		if (stage == SKB_DURATION_STAGE_TO_SDIO)
+			pr_debug("*a_to_sdio: %ums\n", timeout);
+		else if (stage == SKB_DURATION_STAGE_TX_ENQ)
+			pr_debug("*a_to_txenqueue: %ums\n", timeout);
+		else
+			pr_debug("*a_in_hwq: %ums\n", timeout);
+	}
+	return timeout;
+}
+#endif
+static u8 _cal_ampdu_delm_half_crc(u8 value)
+{
+	u32 c32 = value, v32 = value;
+	c32 ^= (v32 >> 1) | (v32 << 7);
+	c32 ^= (v32 >> 2);
+	if (v32 & 2)
+		c32 ^= (0xC0);
+	c32 ^= ((v32 << 4) & 0x30);
+	return (u8) c32;
+}
+
+static u8 _cal_ampdu_delm_crc(u8 * pointer)
+{
+	u8 crc = 0xCF;
+	crc ^= _cal_ampdu_delm_half_crc(*pointer++);
+	crc =
+	    _cal_ampdu_delm_half_crc(crc) ^ _cal_ampdu_delm_half_crc(*pointer);
+	return ~crc;
+}
+
+static bool ssv6200_ampdu_add_delimiter_and_crc32(struct sk_buff *mpdu)
+{
+	p_AMPDU_DELIMITER delimiter_p;
+	struct ieee80211_hdr *mpdu_hdr;
+	int ret;
+	u32 orig_mpdu_len = mpdu->len;
+	u32 pad = (4 - (orig_mpdu_len % 4)) % 4;
+	mpdu_hdr = (struct ieee80211_hdr *)(mpdu->data);
+	mpdu_hdr->duration_id = AMPDU_TX_NAV_MCS_567;
+	ret = skb_padto(mpdu, mpdu->len + (AMPDU_FCS_LEN + pad));
+	if (ret) {
+		pr_err("Failed to extand skb for aggregation\n");
+		return false;
+	}
+	skb_put(mpdu, AMPDU_FCS_LEN + pad);
+	skb_push(mpdu, AMPDU_DELIMITER_LEN);
+	delimiter_p = (p_AMPDU_DELIMITER) mpdu->data;
+	delimiter_p->reserved = 0;
+	delimiter_p->length = orig_mpdu_len + AMPDU_FCS_LEN;
+	delimiter_p->signature = AMPDU_SIGNATURE;
+	delimiter_p->crc = _cal_ampdu_delm_crc((u8 *) (delimiter_p));
+	return true;
+}
+
+static void ssv6200_ampdu_hw_init(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	u32 temp32;
+	SMAC_REG_READ(sc->sh, ADR_MTX_MISC_EN, &temp32);
+	temp32 |= (0x1 << MTX_AMPDU_CRC_AUTO_SFT);
+	SMAC_REG_WRITE(sc->sh, ADR_MTX_MISC_EN, temp32);
+	SMAC_REG_READ(sc->sh, ADR_MTX_MISC_EN, &temp32);
+}
+
+bool _sync_ampdu_pkt_arr(struct AMPDU_TID_st *ampdu_tid, struct sk_buff *ampdu,
+			 bool retry)
+{
+	struct sk_buff **pp_aggr_pkt;
+	struct sk_buff *p_aggr_pkt;
+	unsigned long flags;
+	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
+	struct sk_buff *mpdu;
+	u32 first_ssn = SSV_ILLEGAL_SN;
+	u32 old_aggr_pkt_num;
+	u32 old_baw_head;
+	u32 sync_num = skb_queue_len(&ampdu_hdr->mpdu_q);
+	bool ret = true;
+	spin_lock_irqsave(&ampdu_tid->pkt_array_lock, flags);
+	old_baw_head = ampdu_tid->ssv_baw_head;
+	old_aggr_pkt_num = ampdu_tid->aggr_pkt_num;
+	ampdu_tid->mib.ampdu_mib_ampdu_counter += 1;
+	ampdu_tid->mib.ampdu_mib_dist[sync_num] += 1;
+	do {
+		if (!retry) {
+			ampdu_tid->mib.ampdu_mib_mpdu_counter += sync_num;
+			mpdu = skb_peek_tail(&ampdu_hdr->mpdu_q);
+			if (mpdu == NULL) {
+				ret = false;
+				break;
+			} else {
+				u32 ssn = ampdu_skb_ssn(mpdu);
+				p_aggr_pkt = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+				if (p_aggr_pkt != NULL) {
+					char msg[256];
+					u32 sn = ampdu_skb_ssn(mpdu);
+					skb_queue_walk(&ampdu_hdr->mpdu_q, mpdu) {
+						sn = ampdu_skb_ssn(mpdu);
+						sprintf(msg, " %d", sn);
+					}
+					prn_aggr_err("ES %d -> %d (%s)\n",
+						     ssn,
+						     ampdu_skb_ssn(p_aggr_pkt),
+						     msg);
+					ret = false;
+					break;
+				}
+			}
+		} else
+			ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1;
+		skb_queue_walk(&ampdu_hdr->mpdu_q, mpdu) {
+			u32 ssn = ampdu_skb_ssn(mpdu);
+			SKB_info *mpdu_skb_info = (SKB_info *) (mpdu->head);
+			if (first_ssn == SSV_ILLEGAL_SN)
+				first_ssn = ssn;
+			pp_aggr_pkt = &INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+			p_aggr_pkt = *pp_aggr_pkt;
+			*pp_aggr_pkt = mpdu;
+			if (!retry)
+				ampdu_tid->aggr_pkt_num++;
+			mpdu_skb_info->ampdu_tx_status = AMPDU_ST_AGGREGATED;
+			if (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN) {
+				ampdu_tid->ssv_baw_head = ssn;
+			}
+			if ((p_aggr_pkt != NULL) && (mpdu != p_aggr_pkt))
+				prn_aggr_err("%d -> %d (H%d, N%d, Q%d)\n",
+					     ssn, ampdu_skb_ssn(p_aggr_pkt),
+					     old_baw_head, old_aggr_pkt_num,
+					     sync_num);
+		}
+	} while (0);
+	spin_unlock_irqrestore(&ampdu_tid->pkt_array_lock, flags);
+	{
+		u32 page_count = (ampdu->len + SSV6200_ALLOC_RSVD);
+		if (page_count & HW_MMU_PAGE_MASK)
+			page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
+		else
+			page_count = page_count >> HW_MMU_PAGE_SHIFT;
+		if (page_count > (SSV6200_PAGE_TX_THRESHOLD / 2))
+			pr_err("AMPDU requires pages %d(%d-%d-%d) exceeds resource limit %d.\n",
+			       page_count, ampdu->len, ampdu_hdr->max_size,
+			       ampdu_hdr->size,
+			       (SSV6200_PAGE_TX_THRESHOLD / 2));
+	}
+	return ret;
+}
+
+struct sk_buff *_aggr_retry_mpdu(struct ssv_softc *sc,
+				 struct AMPDU_TID_st *ampdu_tid,
+				 struct sk_buff_head *retry_queue,
+				 u32 max_aggr_len)
+{
+	struct sk_buff *retry_mpdu;
+	struct sk_buff *new_ampdu_skb;
+	u32 num_retry_mpdu;
+	u32 temp_i;
+	u32 total_skb_size;
+	unsigned long flags;
+	u16 head_ssn = ampdu_tid->ssv_baw_head;
+	struct ampdu_hdr_st *ampdu_hdr;
+	BUG_ON(head_ssn == SSV_ILLEGAL_SN);
+	num_retry_mpdu = skb_queue_len(retry_queue);
+	if (num_retry_mpdu == 0)
+		return NULL;
+	new_ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, max_aggr_len);
+	if (new_ampdu_skb == 0)
+		return NULL;
+	ampdu_hdr = (struct ampdu_hdr_st *)new_ampdu_skb->head;
+	total_skb_size = 0;
+	spin_lock_irqsave(&retry_queue->lock, flags);
+	for (temp_i = 0; temp_i < ampdu_tid->agg_num_max; temp_i++) {
+		struct ieee80211_hdr *mpdu_hdr;
+		u16 mpdu_sn;
+		u16 diff;
+		u32 new_total_skb_size;
+		retry_mpdu = skb_peek(retry_queue);
+		if (retry_mpdu == NULL) {
+			break;
+		}
+		mpdu_hdr = ampdu_skb_hdr(retry_mpdu);
+		mpdu_sn = ampdu_hdr_ssn(mpdu_hdr);
+		diff = SSV_AMPDU_SN_a_minus_b(head_ssn, mpdu_sn);
+		if ((head_ssn != SSV_ILLEGAL_SN)
+		    && (diff > 0)
+		    && (diff <= ampdu_tid->ssv_baw_size)) {
+			struct SKB_info_st *skb_info;
+			prn_aggr_err("Z. release skb (s %d, h %d, d %d)\n",
+				     mpdu_sn, head_ssn, diff);
+			skb_info = (struct SKB_info_st *)(retry_mpdu->head);
+			skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
+			ampdu_tid->mib.ampdu_mib_discard_counter++;
+			continue;
+		}
+		new_total_skb_size = total_skb_size + retry_mpdu->len;
+		if (new_total_skb_size > ampdu_hdr->max_size)
+			break;
+		total_skb_size = new_total_skb_size;
+		retry_mpdu = __skb_dequeue(retry_queue);
+		_put_mpdu_to_ampdu(new_ampdu_skb, retry_mpdu);
+		ampdu_tid->mib.ampdu_mib_retry_counter++;
+	}
+	ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1;
+	ampdu_tid->mib.ampdu_mib_dist[temp_i] += 1;
+	spin_unlock_irqrestore(&retry_queue->lock, flags);
+	if (ampdu_hdr->mpdu_num == 0) {
+		dev_kfree_skb_any(new_ampdu_skb);
+		return NULL;
+	}
+	return new_ampdu_skb;
+}
+
+static void _add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb)
+{
+	struct ssv6200_tx_desc *tx_desc;
+	ssv6xxx_add_txinfo(sc, ampdu_skb);
+	tx_desc = (struct ssv6200_tx_desc *)ampdu_skb->data;
+	tx_desc->tx_report = 1;
+}
+
+void _send_hci_skb(struct ssv_softc *sc, struct sk_buff *skb, u32 tx_flag)
+{
+	struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *)skb->data;
+	int ret = AMPDU_HCI_SEND(sc->sh, skb, tx_desc->txq_idx, tx_flag);
+	if ((tx_desc->txq_idx > 3) && (ret <= 0)) {
+		prn_aggr_err("BUG!! %d %d\n", tx_desc->txq_idx, ret);
+	}
+}
+
+static void ssv6200_ampdu_add_txinfo_and_send_HCI(struct ssv_softc *sc,
+						  struct sk_buff *ampdu_skb,
+						  u32 tx_flag)
+{
+	_add_ampdu_txinfo(sc, ampdu_skb);
+	_send_hci_skb(sc, ampdu_skb, tx_flag);
+}
+
+static void ssv6200_ampdu_send_retry(struct ieee80211_hw *hw,
+				     AMPDU_TID * cur_ampdu_tid,
+				     struct sk_buff_head
+				     *ampdu_skb_retry_queue_p,
+				     bool send_aggr_tx)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct sk_buff *ampdu_retry_skb;
+	u32 ampdu_skb_retry_queue_len;
+	u32 max_agg_len;
+	u16 lowest_rate;
+	struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
+	ampdu_skb_retry_queue_len = skb_queue_len(ampdu_skb_retry_queue_p);
+	if (ampdu_skb_retry_queue_len == 0)
+		return;
+	ampdu_retry_skb = skb_peek(ampdu_skb_retry_queue_p);
+	lowest_rate = ssv62xx_ht_rate_update(ampdu_retry_skb, sc, rates);
+	max_agg_len = ampdu_max_transmit_length[lowest_rate];
+	if (max_agg_len > 0) {
+		u32 cur_ampdu_max_size = SSV_GET_MAX_AMPDU_SIZE(sc->sh);
+		if (max_agg_len >= cur_ampdu_max_size)
+			max_agg_len = cur_ampdu_max_size;
+		while (ampdu_skb_retry_queue_len > 0) {
+			struct sk_buff *retry_mpdu =
+			    skb_peek(ampdu_skb_retry_queue_p);
+			SKB_info *mpdu_skb_info =
+			    (SKB_info *) (retry_mpdu->head);
+			mpdu_skb_info->lowest_rate = lowest_rate;
+			memcpy(mpdu_skb_info->rates, rates, sizeof(rates));
+			ampdu_retry_skb =
+			    _aggr_retry_mpdu(sc, cur_ampdu_tid,
+					     ampdu_skb_retry_queue_p,
+					     max_agg_len);
+			if (ampdu_retry_skb != NULL) {
+				_sync_ampdu_pkt_arr(cur_ampdu_tid,
+						    ampdu_retry_skb, true);
+				ssv6200_ampdu_add_txinfo_and_send_HCI(sc,
+								      ampdu_retry_skb,
+								      AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL);
+			} else {
+				prn_aggr_err("AMPDU retry failed.\n");
+				return;
+			}
+			ampdu_skb_retry_queue_len =
+			    skb_queue_len(ampdu_skb_retry_queue_p);
+		}
+	} else {
+		struct ieee80211_tx_rate rates[IEEE80211_TX_MAX_RATES];
+		struct ieee80211_tx_info *info =
+		    IEEE80211_SKB_CB(ampdu_retry_skb);
+		memcpy(rates, info->control.rates, sizeof(info->control.rates));
+		while ((ampdu_retry_skb =
+			__skb_dequeue_tail(ampdu_skb_retry_queue_p)) != NULL) {
+			struct ieee80211_tx_info *info =
+			    IEEE80211_SKB_CB(ampdu_retry_skb);
+			info->flags &= ~IEEE80211_TX_CTL_AMPDU;
+			memcpy(info->control.rates, rates,
+			       sizeof(info->control.rates));
+			ssv6xxx_update_txinfo(sc, ampdu_retry_skb);
+			_send_hci_skb(sc, ampdu_retry_skb,
+				      AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL);
+		}
+	}
+}
+
+void ssv6200_ampdu_init(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	ssv6200_ampdu_hw_init(hw);
+	sc->tx.ampdu_tx_group_id = 0;
+#ifdef USE_ENCRYPT_WORK
+	INIT_WORK(&sc->ampdu_tx_encry_work, encry_work);
+	INIT_WORK(&sc->sync_hwkey_work, sync_hw_key_work);
+#endif
+}
+
+void ssv6200_ampdu_deinit(struct ieee80211_hw *hw)
+{
+}
+
+void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw)
+{
+	ieee80211_free_txskb(hw, skb);
+}
+
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+struct mib_dump_data {
+	char *prt_buff;
+	size_t buff_size;
+	size_t prt_len;
+};
+#define AMPDU_TX_MIB_SUMMARY_BUF_SIZE (4096)
+static ssize_t ampdu_tx_mib_summary_read(struct file *file,
+					 char __user * user_buf, size_t count,
+					 loff_t * ppos)
+{
+	struct ssv_sta_priv_data *ssv_sta_priv =
+	    (struct ssv_sta_priv_data *)file->private_data;
+	char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL);
+	ssize_t summary_size;
+	ssize_t ret;
+	if (!summary_buf)
+		return -ENOMEM;
+	summary_size = ampdu_tx_mib_dump(ssv_sta_priv, summary_buf,
+					 AMPDU_TX_MIB_SUMMARY_BUF_SIZE);
+	ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf,
+				      summary_size);
+	kfree(summary_buf);
+	return ret;
+}
+
+static int ampdu_tx_mib_summary_open(struct inode *inode, struct file *file)
+{
+	file->private_data = inode->i_private;
+	return 0;
+}
+
+static const struct file_operations mib_summary_fops = {.read =
+	    ampdu_tx_mib_summary_read,.open = ampdu_tx_mib_summary_open,
+};
+
+static ssize_t ampdu_tx_tid_window_read(struct file *file,
+					char __user * user_buf, size_t count,
+					loff_t * ppos)
+{
+	struct AMPDU_TID_st *ampdu_tid =
+	    (struct AMPDU_TID_st *)file->private_data;
+	char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL);
+	ssize_t ret;
+	char *prn_ptr = summary_buf;
+	int prt_size;
+	int buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE;
+	int i;
+	struct sk_buff *ba_skb, *tmp_ba_skb;
+	if (!summary_buf)
+		return -ENOMEM;
+	prt_size = snprintf(prn_ptr, buf_size, "\nWMM_TID %d:\n"
+			    "\tWindow:", ampdu_tid->tidno);
+	prn_ptr += prt_size;
+	buf_size -= prt_size;
+	for (i = 0; i < SSV_AMPDU_BA_WINDOW_SIZE; i++) {
+		struct sk_buff *skb = ampdu_tid->aggr_pkts[i];
+		if ((i % 8) == 0) {
+			prt_size = snprintf(prn_ptr, buf_size, "\n\t\t");
+			prn_ptr += prt_size;
+			buf_size -= prt_size;
+		}
+		if (skb == NULL)
+			prt_size = snprintf(prn_ptr, buf_size, " %s", "NULL ");
+		else {
+			struct SKB_info_st *skb_info =
+			    (struct SKB_info_st *)(skb->head);
+			const char status_symbol[] = { 'N',
+				'A',
+				'S',
+				'R',
+				'P',
+				'D'
+			};
+			prt_size =
+			    snprintf(prn_ptr, buf_size, " %4d%c",
+				     ampdu_skb_ssn(skb),
+				     ((skb_info->ampdu_tx_status <=
+				       AMPDU_ST_DONE)
+				      ? status_symbol[skb_info->ampdu_tx_status]
+				      : 'X'));
+		}
+		prn_ptr += prt_size;
+		buf_size -= prt_size;
+	}
+	prt_size =
+	    snprintf(prn_ptr, buf_size, "\n\tEarly aggregated #: %d\n",
+		     ampdu_tid->early_aggr_skb_num);
+	prn_ptr += prt_size;
+	buf_size -= prt_size;
+	prt_size =
+	    snprintf(prn_ptr, buf_size, "\tBAW skb #: %d\n",
+		     ampdu_tid->aggr_pkt_num);
+	prn_ptr += prt_size;
+	buf_size -= prt_size;
+	prt_size =
+	    snprintf(prn_ptr, buf_size, "\tBAW head: %d\n",
+		     ampdu_tid->ssv_baw_head);
+	prn_ptr += prt_size;
+	buf_size -= prt_size;
+	prt_size =
+	    snprintf(prn_ptr, buf_size, "\tState: %d\n", ampdu_tid->state);
+	prn_ptr += prt_size;
+	buf_size -= prt_size;
+	prt_size = snprintf(prn_ptr, buf_size, "\tBA:\n");
+	prn_ptr += prt_size;
+	buf_size -= prt_size;
+	skb_queue_walk_safe(&ampdu_tid->ba_q, ba_skb, tmp_ba_skb) {
+		prt_size = _dump_ba_skb(prn_ptr, buf_size, ba_skb);
+		prn_ptr += prt_size;
+		buf_size -= prt_size;
+	}
+	buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE - buf_size;
+	ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf,
+				      buf_size);
+	kfree(summary_buf);
+	return ret;
+}
+
+static int ampdu_tx_tid_window_open(struct inode *inode, struct file *file)
+{
+	file->private_data = inode->i_private;
+	return 0;
+}
+
+static const struct file_operations tid_window_fops = {.read =
+	    ampdu_tx_tid_window_read,.open = ampdu_tx_tid_window_open,
+};
+
+static int ampdu_tx_mib_reset_open(struct inode *inode, struct file *file)
+{
+	file->private_data = inode->i_private;
+	return 0;
+}
+
+static ssize_t ampdu_tx_mib_reset_read(struct file *file,
+				       char __user * user_buf, size_t count,
+				       loff_t * ppos)
+{
+	char *reset_buf = kzalloc(64, GFP_KERNEL);
+	ssize_t ret;
+	u32 reset_size;
+	if (!reset_buf)
+		return -ENOMEM;
+	reset_size = snprintf(reset_buf, 63, "%d", 0);
+	ret = simple_read_from_buffer(user_buf, count, ppos, reset_buf,
+				      reset_size);
+	kfree(reset_buf);
+	return ret;
+}
+
+static ssize_t ampdu_tx_mib_reset_write(struct file *file,
+					const char __user * buffer,
+					size_t count, loff_t * pos)
+{
+	struct AMPDU_TID_st *ampdu_tid =
+	    (struct AMPDU_TID_st *)file->private_data;
+	memset(&ampdu_tid->mib, 0, sizeof(struct AMPDU_MIB_st));
+	return count;
+}
+
+static const struct file_operations mib_reset_fops
+    = {.read = ampdu_tx_mib_reset_read,
+	.open = ampdu_tx_mib_reset_open,
+	.write = ampdu_tx_mib_reset_write
+};
+
+static void ssv6200_ampdu_tx_init_debugfs(struct ssv_softc *sc,
+					  struct ssv_sta_priv_data
+					  *ssv_sta_priv)
+{
+	struct ssv_sta_info *sta_info = ssv_sta_priv->sta_info;
+	int i;
+	struct dentry *sta_debugfs_dir = sta_info->debugfs_dir;
+	dev_info(sc->dev, "Creating AMPDU TX debugfs.\n");
+	if (sta_debugfs_dir == NULL) {
+		dev_err(sc->dev, "No STA debugfs.\n");
+		return;
+	}
+	debugfs_create_file("ampdu_tx_summary", 00444, sta_debugfs_dir,
+			    ssv_sta_priv, &mib_summary_fops);
+	debugfs_create_u32("total_BA", 00644, sta_debugfs_dir,
+			   &ssv_sta_priv->ampdu_mib_total_BA_counter);
+	for (i = 0; i < WMM_TID_NUM; i++) {
+		char debugfs_name[20];
+		struct dentry *ampdu_tx_debugfs_dir;
+		int j;
+		struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i];
+		struct AMPDU_MIB_st *ampdu_mib = &ampdu_tid->mib;
+		snprintf(debugfs_name, sizeof(debugfs_name), "ampdu_tx_%d", i);
+		ampdu_tx_debugfs_dir = debugfs_create_dir(debugfs_name,
+							  sta_debugfs_dir);
+		if (ampdu_tx_debugfs_dir == NULL) {
+			dev_err(sc->dev,
+				"Failed to create debugfs for AMPDU TX TID %d: %s\n",
+				i, debugfs_name);
+			continue;
+		}
+		ssv_sta_priv->ampdu_tid[i].debugfs_dir = ampdu_tx_debugfs_dir;
+		debugfs_create_file("baw_status", 00444, ampdu_tx_debugfs_dir,
+				    ampdu_tid, &tid_window_fops);
+		debugfs_create_file("reset", 00644, ampdu_tx_debugfs_dir,
+				    ampdu_tid, &mib_reset_fops);
+		debugfs_create_u32("total", 00444, ampdu_tx_debugfs_dir,
+				   &ampdu_mib->ampdu_mib_ampdu_counter);
+		debugfs_create_u32("retry", 00444, ampdu_tx_debugfs_dir,
+				   &ampdu_mib->ampdu_mib_retry_counter);
+		debugfs_create_u32("aggr_retry", 00444, ampdu_tx_debugfs_dir,
+				   &ampdu_mib->ampdu_mib_aggr_retry_counter);
+		debugfs_create_u32("BAR", 00444, ampdu_tx_debugfs_dir,
+				   &ampdu_mib->ampdu_mib_bar_counter);
+		debugfs_create_u32("Discarded", 00444, ampdu_tx_debugfs_dir,
+				   &ampdu_mib->ampdu_mib_discard_counter);
+		debugfs_create_u32("BA", 00444, ampdu_tx_debugfs_dir,
+				   &ampdu_mib->ampdu_mib_BA_counter);
+		debugfs_create_u32("Pass", 00444, ampdu_tx_debugfs_dir,
+				   &ampdu_mib->ampdu_mib_pass_counter);
+		for (j = 0; j <= SSV_AMPDU_aggr_num_max; j++) {
+			char dist_dbg_name[10];
+			snprintf(dist_dbg_name, sizeof(dist_dbg_name),
+				 "aggr_%d", j);
+			debugfs_create_u32(dist_dbg_name, 00444,
+					   ampdu_tx_debugfs_dir,
+					   &ampdu_mib->ampdu_mib_dist[j]);
+		}
+		skb_queue_head_init(&ssv_sta_priv->ampdu_tid[i].ba_q);
+	}
+}
+#endif
+void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw,
+			      struct ieee80211_sta *sta)
+{
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	struct ssv_softc *sc;
+	u32 temp_i;
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	sc = (struct ssv_softc *)hw->priv;
+	for (temp_i = 0; temp_i < WMM_TID_NUM; temp_i++) {
+		ssv_sta_priv->ampdu_tid[temp_i].sta = sta;
+		ssv_sta_priv->ampdu_tid[temp_i].state = AMPDU_STATE_STOP;
+		spin_lock_init(&ssv_sta_priv->ampdu_tid[temp_i].
+			       ampdu_skb_tx_queue_lock);
+		spin_lock_init(&ssv_sta_priv->ampdu_tid[temp_i].pkt_array_lock);
+	}
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	ssv6200_ampdu_tx_init_debugfs(sc, ssv_sta_priv);
+#endif
+}
+
+void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta,
+			    struct ieee80211_hw *hw, u16 * ssn)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	struct AMPDU_TID_st *ampdu_tid;
+	int i;
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	ampdu_tid = &ssv_sta_priv->ampdu_tid[tid];
+	ampdu_tid->ssv_baw_head = SSV_ILLEGAL_SN;
+#ifdef DEBUG_AMPDU_FLUSH
+	pr_debug("Adding %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n",
+	       sta->addr[0], sta->addr[1], sta->addr[2],
+	       sta->addr[3], sta->addr[4], sta->addr[5],
+	       ampdu_tid->tidno, ampdu_tid);
+	{
+		int j;
+		for (j = 0; j <= MAX_TID; j++) {
+			if (sc->tid[j] == 0)
+				break;
+		}
+		if (j == MAX_TID) {
+			dev_err(sc->dev, "No room for new TID.\n");
+		} else
+			sc->tid[j] = ampdu_tid;
+	}
+#endif
+	list_add_tail_rcu(&ampdu_tid->list, &sc->tx.ampdu_tx_que);
+	skb_queue_head_init(&ampdu_tid->ampdu_skb_tx_queue);
+	skb_queue_head_init(&ampdu_tid->early_aggr_ampdu_q);
+	ampdu_tid->early_aggr_skb_num = 0;
+	skb_queue_head_init(&ampdu_tid->ampdu_skb_wait_encry_queue);
+	skb_queue_head_init(&ampdu_tid->retry_queue);
+	skb_queue_head_init(&ampdu_tid->release_queue);
+	for (i = 0;
+	     i <
+	     (sizeof(ampdu_tid->aggr_pkts) / sizeof(ampdu_tid->aggr_pkts[0]));
+	     i++)
+		ampdu_tid->aggr_pkts[i] = 0;
+	ampdu_tid->aggr_pkt_num = 0;
+	ampdu_tid->cur_ampdu_pkt = _alloc_ampdu_skb(sc, ampdu_tid, 0);
+#ifdef AMPDU_CHECK_SKB_SEQNO
+	ssv_sta_priv->ampdu_tid[tid].last_seqno = (-1);
+#endif
+	ssv_sta_priv->ampdu_mib_total_BA_counter = 0;
+	memset(&ssv_sta_priv->ampdu_tid[tid].mib, 0,
+	       sizeof(struct AMPDU_MIB_st));
+	ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_START;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	skb_queue_head_init(&ssv_sta_priv->ampdu_tid[tid].ba_q);
+#endif
+}
+
+void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta,
+				struct ieee80211_hw *hw, u8 buffer_size)
+{
+    struct ssv_softc *sc = hw->priv;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	ssv_sta_priv->ampdu_tid[tid].tidno = tid;
+	ssv_sta_priv->ampdu_tid[tid].sta = sta;
+	ssv_sta_priv->ampdu_tid[tid].agg_num_max = MAX_AGGR_NUM;
+	if (buffer_size > IEEE80211_MAX_AMPDU_BUF) {
+		buffer_size = IEEE80211_MAX_AMPDU_BUF;
+	}
+	dev_info(sc->dev, "AMPDU buffer_size=%d\n", buffer_size);
+	ssv_sta_priv->ampdu_tid[tid].ssv_baw_size = SSV_AMPDU_WINDOW_SIZE;
+	ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_OPERATION;
+}
+
+static void _clear_mpdu_q(struct ieee80211_hw *hw, struct sk_buff_head *q,
+			  bool aggregated_mpdu)
+{
+	struct sk_buff *skb;
+	while (1) {
+		skb = skb_dequeue(q);
+		if (!skb)
+			break;
+		if (aggregated_mpdu)
+			skb_pull(skb, AMPDU_DELIMITER_LEN);
+		ieee80211_tx_status(hw, skb);
+	}
+}
+
+void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta,
+			   struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	if (ssv_sta_priv->ampdu_tid[tid].state == AMPDU_STATE_STOP)
+		return;
+	ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_STOP;
+	dev_dbg(sc->dev, "ssv6200_ampdu_tx_stop\n");
+	if (!list_empty(&sc->tx.ampdu_tx_que)) {
+#ifdef DEBUG_AMPDU_FLUSH
+		{
+			int j;
+			struct AMPDU_TID_st *ampdu_tid =
+			    &ssv_sta_priv->ampdu_tid[tid];
+			for (j = 0; j <= MAX_TID; j++) {
+				if (sc->tid[j] == ampdu_tid)
+					break;
+			}
+			if (j == MAX_TID) {
+				dev_dbg(sc->dev, "No TID found when deleting it.\n");
+			} else
+				sc->tid[j] = NULL;
+			dev_dbg(sc->dev, "Deleting %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n",
+			       sta->addr[0], sta->addr[1], sta->addr[2],
+			       sta->addr[3], sta->addr[4], sta->addr[5],
+			       ampdu_tid->tidno, ampdu_tid);
+		}
+#endif
+		list_del_rcu(&ssv_sta_priv->ampdu_tid[tid].list);
+	}
+	dev_dbg(sc->dev, "clear tx q len=%d\n",
+	       skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue));
+	_clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue,
+		      true);
+	dev_dbg(sc->dev, "clear retry q len=%d\n",
+	       skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].retry_queue));
+	_clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].retry_queue, true);
+#ifdef USE_ENCRYPT_WORK
+	dev_dbg(sc->dev, "clear encrypt q len=%d\n",
+	       skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].
+			     ampdu_skb_wait_encry_queue));
+	_clear_mpdu_q(sc->hw,
+		      &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_wait_encry_queue,
+		      false);
+#endif
+	if (ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt != NULL) {
+		dev_kfree_skb_any(ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt);
+		ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt = NULL;
+	}
+	ssv6200_tx_flow_control((void *)sc,
+				sc->tx.hw_txqid[ssv_sta_priv->ampdu_tid[tid].
+						ac], false, 1000);
+}
+
+static void ssv6200_ampdu_tx_state_stop_func(struct ssv_softc *sc,
+					     struct ieee80211_sta *sta,
+					     struct sk_buff *skb,
+					     struct AMPDU_TID_st *cur_AMPDU_TID)
+{
+	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+	u8 *skb_qos_ctl = ieee80211_get_qos_ctl(hdr);
+	u8 tid_no = skb_qos_ctl[0] & 0xf;
+	if ((sta->ht_cap.ht_supported == true)
+	    && (!!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) {
+		ieee80211_start_tx_ba_session(sta, tid_no, 0);
+		ampdu_db_log("start ampdu_tx(rc) : tid_no = %d\n", tid_no);
+	}
+}
+
+static void ssv6200_ampdu_tx_state_operation_func(struct ssv_softc *sc,
+						  struct ieee80211_sta *sta,
+						  struct sk_buff *skb,
+						  struct AMPDU_TID_st
+						  *cur_AMPDU_TID)
+{
+}
+
+void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta,
+				   struct sk_buff *skb)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)priv;
+	struct ssv_sta_priv_data *ssv_sta_priv =
+	    (struct ssv_sta_priv_data *)sta->drv_priv;
+	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+	u8 *skb_qos_ctl;
+	u8 tid_no;
+	{
+		skb_qos_ctl = ieee80211_get_qos_ctl(hdr);
+		tid_no = skb_qos_ctl[0] & 0xf;
+		switch (ssv_sta_priv->ampdu_tid[tid_no].state) {
+		case AMPDU_STATE_STOP:
+			ssv6200_ampdu_tx_state_stop_func(sc, sta, skb,
+							 &(ssv_sta_priv->
+							   ampdu_tid[tid_no]));
+			break;
+		case AMPDU_STATE_START:
+			break;
+		case AMPDU_STATE_OPERATION:
+			ssv6200_ampdu_tx_state_operation_func(sc, sta, skb,
+							      &(ssv_sta_priv->
+								ampdu_tid
+								[tid_no]));
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+void _put_mpdu_to_ampdu(struct sk_buff *ampdu, struct sk_buff *mpdu)
+{
+	bool is_empty_ampdu = (ampdu->len == 0);
+	unsigned char *data_dest;
+	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
+	BUG_ON(skb_tailroom(ampdu) < mpdu->len);
+	data_dest = skb_tail_pointer(ampdu);
+	skb_put(ampdu, mpdu->len);
+	if (is_empty_ampdu) {
+		struct ieee80211_tx_info *ampdu_info = IEEE80211_SKB_CB(ampdu);
+		struct ieee80211_tx_info *mpdu_info = IEEE80211_SKB_CB(mpdu);
+		SKB_info *mpdu_skb_info = (SKB_info *) (mpdu->head);
+		u32 max_size_for_rate =
+		    ampdu_max_transmit_length[mpdu_skb_info->lowest_rate];
+		BUG_ON(max_size_for_rate == 0);
+		memcpy(ampdu_info, mpdu_info, sizeof(struct ieee80211_tx_info));
+		skb_set_queue_mapping(ampdu, skb_get_queue_mapping(mpdu));
+		ampdu_hdr->first_sn = ampdu_skb_ssn(mpdu);
+		ampdu_hdr->sta = ((struct SKB_info_st *)mpdu->head)->sta;
+		if (ampdu_hdr->max_size > max_size_for_rate)
+			ampdu_hdr->max_size = max_size_for_rate;
+		memcpy(ampdu_hdr->rates, mpdu_skb_info->rates,
+		       sizeof(ampdu_hdr->rates));
+	}
+	memcpy(data_dest, mpdu->data, mpdu->len);
+	__skb_queue_tail(&ampdu_hdr->mpdu_q, mpdu);
+	ampdu_hdr->ssn[ampdu_hdr->mpdu_num++] = ampdu_skb_ssn(mpdu);
+	ampdu_hdr->size += mpdu->len;
+	BUG_ON(ampdu_hdr->size > ampdu_hdr->max_size);
+}
+
+u32 _flush_early_ampdu_q(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid)
+{
+	u32 flushed_ampdu = 0;
+	unsigned long flags;
+	struct sk_buff_head *early_aggr_ampdu_q =
+	    &ampdu_tid->early_aggr_ampdu_q;
+	spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+	while (skb_queue_len(early_aggr_ampdu_q)) {
+		struct sk_buff *head_ampdu;
+		struct ampdu_hdr_st *head_ampdu_hdr;
+		u32 ampdu_aggr_num;
+		head_ampdu = skb_peek(early_aggr_ampdu_q);
+		head_ampdu_hdr = (struct ampdu_hdr_st *)head_ampdu->head;
+		ampdu_aggr_num = skb_queue_len(&head_ampdu_hdr->mpdu_q);
+		if ((SSV_AMPDU_BA_WINDOW_SIZE - ampdu_tid->aggr_pkt_num)
+		    < ampdu_aggr_num)
+			break;
+		if (_sync_ampdu_pkt_arr(ampdu_tid, head_ampdu, false)) {
+			head_ampdu = __skb_dequeue(early_aggr_ampdu_q);
+			ampdu_tid->early_aggr_skb_num -= ampdu_aggr_num;
+#ifdef SSV_AMPDU_FLOW_CONTROL
+			if (ampdu_tid->early_aggr_skb_num
+			    <= SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND) {
+				ssv6200_tx_flow_control((void *)sc,
+							sc->tx.
+							hw_txqid[ampdu_tid->ac],
+							false, 1000);
+			}
+#endif
+			if ((skb_queue_len(early_aggr_ampdu_q) == 0)
+			    && (ampdu_tid->early_aggr_skb_num > 0)) {
+				dev_warn(sc->dev, "Empty early Q w. %d.\n",
+				       ampdu_tid->early_aggr_skb_num);
+			}
+			spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
+					       flags);
+			_send_hci_skb(sc, head_ampdu,
+				      AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
+			spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+			flushed_ampdu++;
+		} else
+			break;
+	}
+	spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
+	return flushed_ampdu;
+}
+
+volatile int max_aggr_num = 24;
+void _aggr_ampdu_tx_q(struct ieee80211_hw *hw, struct AMPDU_TID_st *ampdu_tid)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct sk_buff *ampdu_skb = ampdu_tid->cur_ampdu_pkt;
+	while (skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue)) {
+		u32 aggr_len;
+		struct sk_buff *mpdu_skb;
+		struct ampdu_hdr_st *ampdu_hdr;
+		bool is_aggr_full = false;
+		if (ampdu_skb == NULL) {
+			ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, 0);
+			if (ampdu_skb == NULL)
+				break;
+			ampdu_tid->cur_ampdu_pkt = ampdu_skb;
+		}
+		ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
+		aggr_len = skb_queue_len(&ampdu_hdr->mpdu_q);
+		do {
+			struct sk_buff_head *tx_q =
+			    &ampdu_tid->ampdu_skb_tx_queue;
+			unsigned long flags;
+			spin_lock_irqsave(&tx_q->lock, flags);
+			mpdu_skb = skb_peek(&ampdu_tid->ampdu_skb_tx_queue);
+			if (mpdu_skb == NULL) {
+				spin_unlock_irqrestore(&tx_q->lock, flags);
+				break;
+			}
+			if ((mpdu_skb->len + ampdu_hdr->size) >
+			    ampdu_hdr->max_size) {
+				is_aggr_full = true;
+				spin_unlock_irqrestore(&tx_q->lock, flags);
+				break;
+			}
+			mpdu_skb =
+			    __skb_dequeue(&ampdu_tid->ampdu_skb_tx_queue);
+			spin_unlock_irqrestore(&tx_q->lock, flags);
+			_put_mpdu_to_ampdu(ampdu_skb, mpdu_skb);
+		} while (++aggr_len < max_aggr_num);
+		if ((is_aggr_full || (aggr_len >= max_aggr_num))
+		    || ((aggr_len > 0)
+			&& (skb_queue_len(&ampdu_tid->early_aggr_ampdu_q) == 0)
+			&& (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN)
+			&& _is_skb_q_empty(sc, ampdu_skb))) {
+			_add_ampdu_txinfo(sc, ampdu_skb);
+			_queue_early_ampdu(sc, ampdu_tid, ampdu_skb);
+			ampdu_tid->cur_ampdu_pkt = ampdu_skb = NULL;
+		}
+		_flush_early_ampdu_q(sc, ampdu_tid);
+	}
+}
+
+void _queue_early_ampdu(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid,
+			struct sk_buff *ampdu_skb)
+{
+	unsigned long flags;
+	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
+	spin_lock_irqsave(&ampdu_tid->early_aggr_ampdu_q.lock, flags);
+	__skb_queue_tail(&ampdu_tid->early_aggr_ampdu_q, ampdu_skb);
+	ampdu_tid->early_aggr_skb_num += skb_queue_len(&ampdu_hdr->mpdu_q);
+#ifdef SSV_AMPDU_FLOW_CONTROL
+	if (ampdu_tid->early_aggr_skb_num >= SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND) {
+		ssv6200_tx_flow_control((void *)sc,
+					sc->tx.hw_txqid[ampdu_tid->ac], true,
+					1000);
+	}
+#endif
+	spin_unlock_irqrestore(&ampdu_tid->early_aggr_ampdu_q.lock, flags);
+}
+
+void _flush_mpdu(struct ssv_softc *sc, struct ieee80211_sta *sta)
+{
+	unsigned long flags;
+	struct ssv_sta_priv_data *ssv_sta_priv =
+	    (struct ssv_sta_priv_data *)sta->drv_priv;
+	int i;
+	for (i = 0;
+	     i <
+	     (sizeof(ssv_sta_priv->ampdu_tid) /
+	      sizeof(ssv_sta_priv->ampdu_tid[0])); i++) {
+		struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i];
+		struct sk_buff_head *early_aggr_ampdu_q;
+		struct sk_buff *ampdu;
+		struct ampdu_hdr_st *ampdu_hdr;
+		struct sk_buff_head *mpdu_q;
+		struct sk_buff *mpdu;
+		if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+			continue;
+		early_aggr_ampdu_q = &ampdu_tid->early_aggr_ampdu_q;
+		spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+		while ((ampdu = __skb_dequeue(early_aggr_ampdu_q)) != NULL) {
+			ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
+			mpdu_q = &ampdu_hdr->mpdu_q;
+			spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
+					       flags);
+			while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) {
+				_send_hci_skb(sc, mpdu,
+					      AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
+			}
+			ssv6200_ampdu_release_skb(ampdu, sc->hw);
+			spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+		}
+		if (ampdu_tid->cur_ampdu_pkt != NULL) {
+			ampdu_hdr =
+			    (struct ampdu_hdr_st *)ampdu_tid->cur_ampdu_pkt->
+			    head;
+			mpdu_q = &ampdu_hdr->mpdu_q;
+			spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
+					       flags);
+			while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) {
+				_send_hci_skb(sc, mpdu,
+					      AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
+			}
+			ssv6200_ampdu_release_skb(ampdu_tid->cur_ampdu_pkt,
+						  sc->hw);
+			spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+			ampdu_tid->cur_ampdu_pkt = NULL;
+		}
+		spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
+	}
+}
+
+bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+#ifdef REPORT_TX_STATUS_DIRECTLY
+	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+	struct sk_buff *tx_skb = skb;
+	struct sk_buff *copy_skb = NULL;
+#endif
+	struct SKB_info_st *mpdu_skb_info_p = (SKB_info *) (skb->head);
+	struct ieee80211_sta *sta = mpdu_skb_info_p->sta;
+	struct ssv_sta_priv_data *ssv_sta_priv =
+	    (struct ssv_sta_priv_data *)sta->drv_priv;
+	u8 tidno;
+	struct AMPDU_TID_st *ampdu_tid;
+	if (sta == NULL) {
+		WARN_ON(1);
+		return false;
+	}
+	tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+	ampdu_db_log("tidno = %d\n", tidno);
+	ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno];
+	if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+		return false;
+#ifdef AMPDU_CHECK_SKB_SEQNO
+	{
+		u32 skb_seqno = ((struct ieee80211_hdr *)(skb->data))->seq_ctrl
+		    >> SSV_SEQ_NUM_SHIFT;
+		u32 tid_seqno = ampdu_tid->last_seqno;
+		if ((tid_seqno != (-1))
+		    && (skb_seqno != NEXT_PKT_SN(tid_seqno))) {
+			prn_aggr_err("Non continueous seq no: %d - %d\n",
+				     tid_seqno, skb_seqno);
+			return false;
+		}
+		ampdu_tid->last_seqno = skb_seqno;
+	}
+#endif
+	mpdu_skb_info_p->lowest_rate =
+	    ssv62xx_ht_rate_update(skb, sc, mpdu_skb_info_p->rates);
+	if (ampdu_max_transmit_length[mpdu_skb_info_p->lowest_rate] == 0) {
+		_flush_mpdu(sc, sta);
+		return false;
+	}
+	mpdu_skb_info_p = (SKB_info *) (skb->head);
+	mpdu_skb_info_p->mpdu_retry_counter = 0;
+	mpdu_skb_info_p->ampdu_tx_status = AMPDU_ST_NON_AMPDU;
+	mpdu_skb_info_p->ampdu_tx_final_retry_count = 0;
+	ssv_sta_priv->ampdu_tid[tidno].ac = skb_get_queue_mapping(skb);
+#ifdef REPORT_TX_STATUS_DIRECTLY
+	info->flags |= IEEE80211_TX_STAT_ACK;
+	copy_skb = skb_copy(tx_skb, GFP_ATOMIC);
+	if (!copy_skb) {
+		dev_err(sc->dev, "create TX skb copy failed!\n");
+		return false;
+	}
+	ieee80211_tx_status(sc->hw, tx_skb);
+	skb = copy_skb;
+#endif
+	{
+		bool ret;
+		ret = ssv6200_ampdu_add_delimiter_and_crc32(skb);
+		if (ret == false) {
+			ssv6200_ampdu_release_skb(skb, hw);
+			return false;
+		}
+		skb_queue_tail(&ssv_sta_priv->ampdu_tid[tidno].
+			       ampdu_skb_tx_queue, skb);
+		ssv_sta_priv->ampdu_tid[tidno].timestamp = jiffies;
+	}
+	_aggr_ampdu_tx_q(hw, &ssv_sta_priv->ampdu_tid[tidno]);
+	return true;
+}
+
+u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct AMPDU_TID_st *cur_AMPDU_TID;
+	u32 flushed_ampdu = 0;
+	u32 tid_idx = 0;
+	if (!list_empty(&sc->tx.ampdu_tx_que)) {
+		list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que,
+					list) {
+			tid_idx++;
+#ifdef DEBUG_AMPDU_FLUSH
+			{
+				int i = 0;
+				for (i = 0; i < MAX_TID; i++)
+					if (sc->tid[i] == cur_AMPDU_TID)
+						break;
+				if (i == MAX_TID) {
+					dev_err(sc->dev, "No matching TID (%d) found! %p\n",
+					       tid_idx, cur_AMPDU_TID);
+					continue;
+				}
+			}
+#endif
+			if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION) {
+				struct ieee80211_sta *sta = cur_AMPDU_TID->sta;
+				struct ssv_sta_priv_data *sta_priv =
+				    (struct ssv_sta_priv_data *)sta->drv_priv;
+				dev_dbg(sc->dev, "STA %d TID %d is @%d\n",
+					sta_priv->sta_idx, cur_AMPDU_TID->tidno,
+					cur_AMPDU_TID->state);
+				continue;
+			}
+			if ((cur_AMPDU_TID->state == AMPDU_STATE_OPERATION)
+			    &&
+			    (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q)
+			     == 0)
+			    && (cur_AMPDU_TID->cur_ampdu_pkt != NULL)) {
+				struct ampdu_hdr_st *ampdu_hdr =
+				    (struct ampdu_hdr_st *)(cur_AMPDU_TID->
+							    cur_ampdu_pkt->
+							    head);
+				u32 aggr_len =
+				    skb_queue_len(&ampdu_hdr->mpdu_q);
+				if (aggr_len) {
+					struct sk_buff *ampdu_skb =
+					    cur_AMPDU_TID->cur_ampdu_pkt;
+					cur_AMPDU_TID->cur_ampdu_pkt = NULL;
+					_add_ampdu_txinfo(sc, ampdu_skb);
+					_queue_early_ampdu(sc, cur_AMPDU_TID,
+							   ampdu_skb);
+				}
+			}
+			if (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q) >
+			    0)
+				flushed_ampdu +=
+				    _flush_early_ampdu_q(sc, cur_AMPDU_TID);
+		}
+	}
+	return flushed_ampdu;
+}
+
+int _dump_BA_notification(char *buf,
+			  struct ampdu_ba_notify_data *ba_notification)
+{
+	int i;
+	char *orig_buf = buf;
+	for (i = 0; i < MAX_AGGR_NUM; i++) {
+		if (ba_notification->seq_no[i] == (u16) (-1))
+			break;
+		buf += sprintf(buf, " %d", ba_notification->seq_no[i]);
+	}
+	return ((size_t)buf - (size_t)orig_buf);
+}
+
+int _dump_ba_skb(char *buf, int buf_size, struct sk_buff *ba_skb)
+{
+	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(ba_skb->data
+							     +
+							     SSV6XXX_RX_DESC_LEN);
+	AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr;
+	u32 ssn = BA_frame->BA_ssn;
+	struct ampdu_ba_notify_data *ba_notification =
+	    (struct ampdu_ba_notify_data *)(ba_skb->data + ba_skb->len
+					    -
+					    sizeof(struct
+						   ampdu_ba_notify_data));
+	int prt_size;
+	prt_size = snprintf(buf, buf_size, "\n\t\t%04d %08X %08X -",
+			    ssn, BA_frame->BA_sn_bit_map[0],
+			    BA_frame->BA_sn_bit_map[1]);
+	buf_size -= prt_size;
+	buf += prt_size;
+	prt_size = prt_size + _dump_BA_notification(buf, ba_notification);
+	return prt_size;
+}
+
+static bool _ssn_to_bit_idx(u32 start_ssn, u32 mpdu_ssn, u32 * word_idx,
+			    u32 * bit_idx)
+{
+	u32 ret_bit_idx, ret_word_idx = 0;
+	s32 diff = mpdu_ssn - start_ssn;
+	if (diff >= 0) {
+		if (diff >= SSV_AMPDU_BA_WINDOW_SIZE) {
+			return false;
+		}
+		ret_bit_idx = diff;
+	} else {
+		diff = -diff;
+		if (diff <= (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) {
+			*word_idx = 0;
+			*bit_idx = 0;
+			return false;
+		}
+		ret_bit_idx = SSV_AMPDU_MAX_SSN - diff;
+	}
+	if (ret_bit_idx >= 32) {
+		ret_bit_idx -= 32;
+		ret_word_idx = 1;
+	}
+	*bit_idx = ret_bit_idx;
+	*word_idx = ret_word_idx;
+	return true;
+}
+
+static bool _inc_bit_idx(u32 ssn_1st, u32 ssn_next, u32 * word_idx,
+			 u32 * bit_idx)
+{
+	u32 ret_word_idx = *word_idx, ret_bit_idx = *bit_idx;
+	s32 diff = (s32) ssn_1st - (s32) ssn_next;
+	if (diff > 0) {
+		if (diff < (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) {
+			prn_aggr_err
+			    ("Irrational SN distance in AMPDU: %d %d.\n",
+			     ssn_1st, ssn_next);
+			return false;
+		}
+		diff = SSV_AMPDU_MAX_SSN - diff;
+	} else {
+		diff = -diff;
+	}
+	if (diff > SSV_AMPDU_MAX_SSN)
+		prn_aggr_err("DF %d - %d = %d\n", ssn_1st, ssn_next, diff);
+	ret_bit_idx += diff;
+	if (ret_bit_idx >= 32) {
+		ret_bit_idx -= 32;
+		ret_word_idx++;
+	}
+	*word_idx = ret_word_idx;
+	*bit_idx = ret_bit_idx;
+	return true;
+}
+
+static void _release_frames(struct AMPDU_TID_st *ampdu_tid)
+{
+	u32 head_ssn, head_ssn_before, last_ssn;
+	struct sk_buff **skb;
+	struct SKB_info_st *skb_info;
+	spin_lock_bh(&ampdu_tid->pkt_array_lock);
+	head_ssn_before = ampdu_tid->ssv_baw_head;
+	if (head_ssn_before >= SSV_AMPDU_MAX_SSN) {
+		spin_unlock_bh(&ampdu_tid->pkt_array_lock);
+		prn_aggr_err("l x.x %d\n", head_ssn_before);
+		return;
+	}
+	head_ssn = ampdu_tid->ssv_baw_head;
+	last_ssn = head_ssn;
+	do {
+		skb = &INDEX_PKT_BY_SSN(ampdu_tid, head_ssn);
+		if (*skb == NULL) {
+			head_ssn = SSV_ILLEGAL_SN;
+			{
+				int i;
+				char sn_str[66 * 5] = "";
+				char *str = sn_str;
+				for (i = 0; i < 64; i++)
+					if (ampdu_tid->aggr_pkts[i] != NULL) {
+						str += sprintf(str, "%d ",
+							       ampdu_skb_ssn
+							       (ampdu_tid->
+								aggr_pkts[i]));
+					}
+				*str = 0;
+				if (str == sn_str) {
+				} else
+					prn_aggr_err("ILL %d %d - %d (%s)\n",
+						     head_ssn_before, last_ssn,
+						     ampdu_tid->aggr_pkt_num,
+						     sn_str);
+			}
+			break;
+		}
+		skb_info = (struct SKB_info_st *)((*skb)->head);
+		if ((skb_info->ampdu_tx_status == AMPDU_ST_DONE)
+		    || (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)) {
+			__skb_queue_tail(&ampdu_tid->release_queue, *skb);
+			*skb = NULL;
+			last_ssn = head_ssn;
+			INC_PKT_SN(head_ssn);
+			ampdu_tid->aggr_pkt_num--;
+			if (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)
+				ampdu_tid->mib.ampdu_mib_discard_counter++;
+		} else {
+			break;
+		}
+	} while (1);
+	ampdu_tid->ssv_baw_head = head_ssn;
+	spin_unlock_bh(&ampdu_tid->pkt_array_lock);
+}
+
+static int _collect_retry_frames(struct AMPDU_TID_st *ampdu_tid)
+{
+	u16 ssn, head_ssn, end_ssn;
+	int num_retry = 0;
+	int timeout_check = 1;
+	unsigned long check_jiffies = jiffies;
+	head_ssn = ampdu_tid->ssv_baw_head;
+	ssn = head_ssn;
+	if (ssn == SSV_ILLEGAL_SN)
+		return 0;
+	end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE) % SSV_AMPDU_MAX_SSN;
+	do {
+		struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+		struct SKB_info_st *skb_info;
+		int timeout_retry = 0;
+		if (skb == NULL)
+			break;
+		skb_info = (SKB_info *) (skb->head);
+		if (timeout_check
+		    && (skb_info->ampdu_tx_status == AMPDU_ST_SENT)) {
+			unsigned long cur_jiffies = jiffies;
+			unsigned long timeout_jiffies = skb_info->aggr_timestamp
+			    + msecs_to_jiffies(BA_WAIT_TIMEOUT);
+			u32 delta_ms;
+			if (time_before(cur_jiffies, timeout_jiffies)) {
+				timeout_check = 0;
+				continue;
+			}
+			_mark_skb_retry(skb_info, skb);
+			delta_ms =
+			    jiffies_to_msecs(cur_jiffies -
+					     skb_info->aggr_timestamp);
+			prn_aggr_err("t S%d-T%d-%d (%u)\n",
+				     ((struct ssv_sta_priv_data *)skb_info->
+				      sta->drv_priv)->sta_idx, ampdu_tid->tidno,
+				     ssn, delta_ms);
+			if (delta_ms > 1000) {
+				prn_aggr_err("Last checktime %lu - %lu = %u\n",
+					     check_jiffies,
+					     ampdu_tid->timestamp,
+					     jiffies_to_msecs(check_jiffies -
+							      ampdu_tid->
+							      timestamp));
+			}
+			timeout_retry = 1;
+		}
+		if (skb_info->ampdu_tx_status == AMPDU_ST_RETRY) {
+			skb_queue_tail(&ampdu_tid->retry_queue, skb);
+			ampdu_tid->mib.ampdu_mib_retry_counter++;
+			num_retry++;
+		}
+		INC_PKT_SN(ssn);
+	} while (ssn != end_ssn);
+	ampdu_tid->timestamp = check_jiffies;
+	return num_retry;
+}
+
+int _mark_skb_retry(struct SKB_info_st *skb_info, struct sk_buff *skb)
+{
+	if (skb_info->mpdu_retry_counter < SSV_AMPDU_retry_counter_max) {
+		if (skb_info->mpdu_retry_counter == 0) {
+			struct ieee80211_hdr *skb_hdr = ampdu_skb_hdr(skb);
+			skb_hdr->frame_control |=
+			    cpu_to_le16(IEEE80211_FCTL_RETRY);
+		}
+		skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
+		skb_info->mpdu_retry_counter++;
+		return 1;
+	} else {
+		skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
+		prn_aggr_err("p %d\n", ampdu_skb_ssn(skb));
+		return 0;
+	}
+}
+
+static u32 _ba_map_walker(struct AMPDU_TID_st *ampdu_tid, u32 start_ssn,
+			  u32 sn_bit_map[2],
+			  struct ampdu_ba_notify_data *ba_notify_data,
+			  u32 * p_acked_num)
+{
+	int i = 0;
+	u32 ssn = ba_notify_data->seq_no[0];
+	u32 word_idx = (-1), bit_idx = (-1);
+	bool found = _ssn_to_bit_idx(start_ssn, ssn, &word_idx, &bit_idx);
+	bool first_found = found;
+	u32 aggr_num = 0;
+	u32 acked_num = 0;
+	if (found && (word_idx >= 2 || bit_idx >= 32))
+		prn_aggr_err("idx error 1: %d %d %d %d\n",
+			     start_ssn, ssn, word_idx, bit_idx);
+	while ((i < MAX_AGGR_NUM) && (ssn < SSV_AMPDU_MAX_SSN)) {
+		u32 cur_ssn;
+		struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+		u32 skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
+		struct SKB_info_st *skb_info;
+		aggr_num++;
+		if (skb_ssn != ssn) {
+			prn_aggr_err("Unmatched SSN packet: %d - %d - %d\n",
+				     ssn, skb_ssn, start_ssn);
+		} else {
+			skb_info = (struct SKB_info_st *)(skb->head);
+			if (found && (sn_bit_map[word_idx] & (1 << bit_idx))) {
+				if (skb_info->ampdu_tx_status != AMPDU_ST_SENT) {
+					pr_err("BA marks a MPDU of status %d!\n",
+					       skb_info->ampdu_tx_status);
+				}
+				skb_info->ampdu_tx_status = AMPDU_ST_DONE;
+				acked_num++;
+			} else {
+				_mark_skb_retry(skb_info, skb);
+			}
+		}
+		cur_ssn = ssn;
+		if (++i >= MAX_AGGR_NUM)
+			break;
+		ssn = ba_notify_data->seq_no[i];
+		if (ssn >= SSV_AMPDU_MAX_SSN)
+			break;
+		if (first_found) {
+			u32 old_word_idx = word_idx, old_bit_idx = bit_idx;
+			found = _inc_bit_idx(cur_ssn, ssn, &word_idx, &bit_idx);
+			if (found && (word_idx >= 2 || bit_idx >= 32)) {
+				prn_aggr_err
+				    ("idx error 2: %d 0x%08X 0X%08X %d %d (%d %d) (%d %d)\n",
+				     start_ssn, sn_bit_map[1], sn_bit_map[0],
+				     cur_ssn, ssn, word_idx, bit_idx,
+				     old_word_idx, old_bit_idx);
+				found = false;
+			} else if (!found) {
+				char strbuf[256];
+				_dump_BA_notification(strbuf, ba_notify_data);
+				prn_aggr_err("SN out-of-order: %d\n%s\n",
+					     start_ssn, strbuf);
+			}
+		} else {
+			found =
+			    _ssn_to_bit_idx(start_ssn, ssn, &word_idx,
+					    &bit_idx);
+			first_found = found;
+			if (found && (word_idx >= 2 || bit_idx >= 32))
+				prn_aggr_err("idx error 3: %d %d %d %d\n",
+					     cur_ssn, ssn, word_idx, bit_idx);
+		}
+	}
+	_release_frames(ampdu_tid);
+	if (p_acked_num != NULL)
+		*p_acked_num = acked_num;
+	return aggr_num;
+}
+
+static void _flush_release_queue(struct ieee80211_hw *hw,
+				 struct sk_buff_head *release_queue)
+{
+	do {
+		struct sk_buff *ampdu_skb = __skb_dequeue(release_queue);
+		struct ieee80211_tx_info *tx_info;
+		struct SKB_info_st *skb_info;
+		if (ampdu_skb == NULL)
+			break;
+		skb_info = (struct SKB_info_st *)(ampdu_skb->head);
+		skb_pull(ampdu_skb, AMPDU_DELIMITER_LEN);
+		tx_info = IEEE80211_SKB_CB(ampdu_skb);
+		ieee80211_tx_info_clear_status(tx_info);
+		tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
+		if (skb_info->ampdu_tx_status == AMPDU_ST_DONE)
+			tx_info->flags |= IEEE80211_TX_STAT_ACK;
+		tx_info->status.ampdu_len = 1;
+		tx_info->status.ampdu_ack_len = 1;
+#ifdef REPORT_TX_STATUS_DIRECTLY
+		dev_kfree_skb_any(ampdu_skb);
+#else
+#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_TX_DATA)
+		ieee80211_tx_status(hw, ampdu_skb);
+#else
+		ieee80211_tx_status_irqsafe(hw, ampdu_skb);
+#endif
+#endif
+	} while (1);
+}
+
+void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+	struct cfg_host_event *host_event = (struct cfg_host_event *)skb->data;
+	struct ampdu_ba_notify_data *ba_notification =
+	    (struct ampdu_ba_notify_data *)&host_event->dat[0];
+	struct ieee80211_hdr *hdr =
+	    (struct ieee80211_hdr *)(ba_notification + 1);
+	struct ssv_softc *sc = hw->priv;
+	struct ieee80211_sta *sta = ssv6xxx_find_sta_by_addr(sc, hdr->addr1);
+	u8 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	char seq_str[256];
+	struct AMPDU_TID_st *ampdu_tid;
+	int i;
+	u16 aggr_num = 0;
+	struct firmware_rate_control_report_data *report_data;
+	if (sta == NULL) {
+		prn_aggr_err
+		    ("NO BA for %d to unmatched STA %02X-%02X-%02X-%02X-%02X-%02X: %s\n",
+		     tidno, hdr->addr1[0], hdr->addr1[1], hdr->addr1[2],
+		     hdr->addr1[3], hdr->addr1[4], hdr->addr1[5], seq_str);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	_dump_BA_notification(seq_str, ba_notification);
+	prn_aggr_err("NO BA for %d to %02X-%02X-%02X-%02X-%02X-%02X: %s\n",
+		     tidno, sta->addr[0], sta->addr[1], sta->addr[2],
+		     sta->addr[3], sta->addr[4], sta->addr[5], seq_str);
+	ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno];
+	if (ampdu_tid->state != AMPDU_STATE_OPERATION) {
+		dev_kfree_skb_any(skb);
+		return;
+	}
+	for (i = 0; i < MAX_AGGR_NUM; i++) {
+		u32 ssn = ba_notification->seq_no[i];
+		struct sk_buff *skb;
+		u32 skb_ssn;
+		struct SKB_info_st *skb_info;
+		if (ssn >= (4096))
+			break;
+		aggr_num++;
+		skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+		skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
+		if (skb_ssn != ssn) {
+			prn_aggr_err("Unmatched SSN packet: %d - %d\n", ssn,
+				     skb_ssn);
+			continue;
+		}
+		skb_info = (struct SKB_info_st *)(skb->head);
+		if (skb_info->ampdu_tx_status == AMPDU_ST_SENT) {
+			if (skb_info->mpdu_retry_counter <
+			    SSV_AMPDU_retry_counter_max) {
+				if (skb_info->mpdu_retry_counter == 0) {
+					struct ieee80211_hdr *skb_hdr =
+					    ampdu_skb_hdr(skb);
+					skb_hdr->frame_control |=
+					    cpu_to_le16(IEEE80211_FCTL_RETRY);
+				}
+				skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
+				skb_info->mpdu_retry_counter++;
+			} else {
+				skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
+				prn_aggr_err("p %d\n", skb_ssn);
+			}
+		} else {
+			prn_aggr_err("S %d %d\n", skb_ssn,
+				     skb_info->ampdu_tx_status);
+		}
+	}
+	_release_frames(ampdu_tid);
+	host_event->h_event = SOC_EVT_RC_AMPDU_REPORT;
+	report_data =
+	    (struct firmware_rate_control_report_data *)&host_event->dat[0];
+	report_data->ampdu_len = aggr_num;
+	report_data->ampdu_ack_len = 0;
+	report_data->wsid = ssv_sta_priv->sta_info->hw_wsid;
+	skb_queue_tail(&sc->rc_report_queue, skb);
+	if (sc->rc_sample_sechedule == 0)
+		queue_work(sc->rc_sample_workqueue, &sc->rc_sample_work);
+}
+
+void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data
+							     +
+							     SSV6XXX_RX_DESC_LEN);
+	AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr;
+	struct ieee80211_sta *sta;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	struct ampdu_ba_notify_data *ba_notification;
+	u32 ssn, aggr_num = 0, acked_num = 0;
+	u8 tid_no;
+	u32 sn_bit_map[2];
+	struct firmware_rate_control_report_data *report_data;
+	HDR_HostEvent *host_evt;
+	sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
+	if (sta == NULL) {
+		if (skb->len > AMPDU_BA_FRAME_LEN) {
+			char strbuf[256];
+			struct ampdu_ba_notify_data *ba_notification =
+			    (struct ampdu_ba_notify_data *)(skb->data + skb->len
+							    -
+							    sizeof(struct
+								   ampdu_ba_notify_data));
+			_dump_BA_notification(strbuf, ba_notification);
+			prn_aggr_err
+			    ("BA from not connected STA (%02X-%02X-%02X-%02X-%02X-%02X) (%s)\n",
+			     BA_frame->ta_addr[0], BA_frame->ta_addr[1],
+			     BA_frame->ta_addr[2], BA_frame->ta_addr[3],
+			     BA_frame->ta_addr[4], BA_frame->ta_addr[5],
+			     strbuf);
+		}
+		dev_kfree_skb_any(skb);
+		return;
+	}
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	ssn = BA_frame->BA_ssn;
+	sn_bit_map[0] = BA_frame->BA_sn_bit_map[0];
+	sn_bit_map[1] = BA_frame->BA_sn_bit_map[1];
+	tid_no = BA_frame->tid_info;
+	ssv_sta_priv->ampdu_mib_total_BA_counter++;
+	if (ssv_sta_priv->ampdu_tid[tid_no].state == AMPDU_STATE_STOP) {
+		prn_aggr_err
+		    ("ssv6200_ampdu_BA_handler state == AMPDU_STATE_STOP.\n");
+		dev_kfree_skb_any(skb);
+		return;
+	}
+	ssv_sta_priv->ampdu_tid[tid_no].mib.ampdu_mib_BA_counter++;
+	if (skb->len <= AMPDU_BA_FRAME_LEN) {
+		prn_aggr_err("b %d\n", ssn);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+	ba_notification =
+	    (struct ampdu_ba_notify_data *)(skb->data + skb->len
+					    -
+					    sizeof(struct
+						   ampdu_ba_notify_data));
+	aggr_num =
+	    _ba_map_walker(&(ssv_sta_priv->ampdu_tid[tid_no]), ssn, sn_bit_map,
+			   ba_notification, &acked_num);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	if (ssv_sta_priv->ampdu_tid[tid_no].debugfs_dir) {
+		struct sk_buff *dup_skb;
+		if (skb_queue_len(&ssv_sta_priv->ampdu_tid[tid_no].ba_q) > 24) {
+			struct sk_buff *ba_skb =
+			    skb_dequeue(&ssv_sta_priv->ampdu_tid[tid_no].ba_q);
+			if (ba_skb)
+				dev_kfree_skb_any(ba_skb);
+		}
+		dup_skb = skb_clone(skb, GFP_ATOMIC);
+		if (dup_skb)
+			skb_queue_tail(&ssv_sta_priv->ampdu_tid[tid_no].ba_q,
+				       dup_skb);
+	}
+#endif
+	skb_trim(skb, skb->len - sizeof(struct ampdu_ba_notify_data));
+	host_evt = (HDR_HostEvent *) skb->data;
+	host_evt->h_event = SOC_EVT_RC_AMPDU_REPORT;
+	report_data =
+	    (struct firmware_rate_control_report_data *)&host_evt->dat[0];
+	memcpy(report_data, ba_notification,
+	       sizeof(struct firmware_rate_control_report_data));
+	report_data->ampdu_len = aggr_num;
+	report_data->ampdu_ack_len = acked_num;
+#ifdef RATE_CONTROL_HT_PERCENTAGE_TRACE
+	if ((acked_num) && (acked_num != aggr_num)) {
+		int i;
+		for (i = 0; i < SSV62XX_TX_MAX_RATES; i++) {
+			if (report_data->rates[i].data_rate == -1)
+				break;
+			if (report_data->rates[i].count == 0)
+                dev_err(sc->dev, "illegal HT report\n");
+
+			dev_dbg(sc->dev, "i=[%d] rate[%d] count[%d]\n", i,
+			       report_data->rates[i].data_rate,
+			       report_data->rates[i].count);
+		}
+		dev_dbg(sc->dev, "AMPDU percentage = %d%% \n",
+		       acked_num * 100 / aggr_num);
+	} else if (acked_num == 0) {
+		dev_dbg(sc->dev, "AMPDU percentage = 0%% aggr_num=%d acked_num=%d\n",
+		       aggr_num, acked_num);
+	}
+#endif
+	skb_queue_tail(&sc->rc_report_queue, skb);
+	if (sc->rc_sample_sechedule == 0)
+		queue_work(sc->rc_sample_workqueue, &sc->rc_sample_work);
+}
+
+static void _postprocess_BA(struct ssv_softc *sc, struct ssv_sta_info *sta_info,
+			    void *param)
+{
+	int j;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	if ((sta_info->sta == NULL)
+	    || ((sta_info->s_flags & STA_FLAG_VALID) == 0))
+		return;
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+	for (j = 0; j < WMM_TID_NUM; j++) {
+		AMPDU_TID *ampdu_tid = &ssv_sta_priv->ampdu_tid[j];
+		if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+			continue;
+		_collect_retry_frames(ampdu_tid);
+		ssv6200_ampdu_send_retry(sc->hw, ampdu_tid,
+					 &ampdu_tid->retry_queue, true);
+		_flush_early_ampdu_q(sc, ampdu_tid);
+		_flush_release_queue(sc->hw, &ampdu_tid->release_queue);
+	}
+}
+
+void ssv6xxx_ampdu_postprocess_BA(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	ssv6xxx_foreach_sta(sc, _postprocess_BA, NULL);
+}
+
+static void ssv6200_hw_set_rx_ba_session(struct ssv_hw *sh, bool on, u8 * ta,
+					 u16 tid, u16 ssn, u8 buf_size)
+{
+	if (on) {
+		u32 u32ta;
+		u32ta = 0;
+		u32ta |= (ta[0] & 0xff) << (8 * 0);
+		u32ta |= (ta[1] & 0xff) << (8 * 1);
+		u32ta |= (ta[2] & 0xff) << (8 * 2);
+		u32ta |= (ta[3] & 0xff) << (8 * 3);
+		SMAC_REG_WRITE(sh, ADR_BA_TA_0, u32ta);
+		u32ta = 0;
+		u32ta |= (ta[4] & 0xff) << (8 * 0);
+		u32ta |= (ta[5] & 0xff) << (8 * 1);
+		SMAC_REG_WRITE(sh, ADR_BA_TA_1, u32ta);
+		SMAC_REG_WRITE(sh, ADR_BA_TID, tid);
+		SMAC_REG_WRITE(sh, ADR_BA_ST_SEQ, ssn);
+		SMAC_REG_WRITE(sh, ADR_BA_SB0, 0);
+		SMAC_REG_WRITE(sh, ADR_BA_SB1, 0);
+		SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0xb);
+	} else {
+		SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0x0);
+	}
+}
+
+void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work)
+{
+	struct ssv_softc
+	*sc = container_of(work, struct ssv_softc, set_ampdu_rx_add_work);
+	ssv6200_hw_set_rx_ba_session(sc->sh, true, sc->ba_ra_addr, sc->ba_tid,
+				     sc->ba_ssn, 64);
+}
+
+void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work)
+{
+	struct ssv_softc *sc = container_of(work, struct ssv_softc,
+					    set_ampdu_rx_del_work);
+	u8 addr[6] = { 0 };
+	ssv6200_hw_set_rx_ba_session(sc->sh, false, addr, 0, 0, 0);
+}
+
+static void _reset_ampdu_mib(struct ssv_softc *sc,
+			     struct ssv_sta_info *sta_info, void *param)
+{
+	struct ieee80211_sta *sta = sta_info->sta;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	int i;
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	for (i = 0; i < WMM_TID_NUM; i++) {
+		ssv_sta_priv->ampdu_tid[i].ampdu_mib_reset = 1;
+	}
+}
+
+void ssv6xxx_ampdu_mib_reset(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	if (sc == NULL)
+		return;
+	ssv6xxx_foreach_sta(sc, _reset_ampdu_mib, NULL);
+}
+
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ssize_t ampdu_tx_mib_dump(struct ssv_sta_priv_data *ssv_sta_priv,
+			  char *mib_str, ssize_t length)
+{
+	ssize_t buf_size = length;
+	ssize_t prt_size;
+	int j;
+	struct ssv_sta_info *ssv_sta = ssv_sta_priv->sta_info;
+	if (ssv_sta->sta == NULL) {
+		prt_size = snprintf(mib_str, buf_size, "\n    NULL STA.\n");
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		goto mib_dump_exit;
+	}
+	for (j = 0; j < WMM_TID_NUM; j++) {
+		int k;
+		struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[j];
+		struct AMPDU_MIB_st *ampdu_mib = &ampdu_tid->mib;
+		prt_size =
+		    snprintf(mib_str, buf_size, "\n    WMM_TID %d@%d\n", j,
+			     ampdu_tid->state);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+			continue;
+		prt_size =
+		    snprintf(mib_str, buf_size, "        BA window size: %d\n",
+			     ampdu_tid->ssv_baw_size);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size =
+		    snprintf(mib_str, buf_size, "        BA window head: %d\n",
+			     ampdu_tid->ssv_baw_head);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        Sending aggregated #: %d\n",
+				    ampdu_tid->aggr_pkt_num);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size =
+		    snprintf(mib_str, buf_size, "        Waiting #: %d\n",
+			     skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue));
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size =
+		    snprintf(mib_str, buf_size, "        Early aggregated %d\n",
+			     ampdu_tid->early_aggr_skb_num);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        MPDU: %d\n",
+				    ampdu_mib->ampdu_mib_mpdu_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        Passed: %d\n",
+				    ampdu_mib->ampdu_mib_pass_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        Retry: %d\n",
+				    ampdu_mib->ampdu_mib_retry_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        AMPDU: %d\n",
+				    ampdu_mib->ampdu_mib_ampdu_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        Retry AMPDU: %d\n",
+				    ampdu_mib->ampdu_mib_aggr_retry_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        BAR count: %d\n",
+				    ampdu_mib->ampdu_mib_bar_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        Discard count: %d\n",
+				    ampdu_mib->ampdu_mib_discard_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        BA count: %d\n",
+				    ampdu_mib->ampdu_mib_BA_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size =
+		    snprintf(mib_str, buf_size, "        Total BA count: %d\n",
+			     ssv_sta_priv->ampdu_mib_total_BA_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size =
+		    snprintf(mib_str, buf_size, "        Aggr # count:\n");
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		for (k = 0; k <= SSV_AMPDU_aggr_num_max; k++) {
+			prt_size =
+			    snprintf(mib_str, buf_size, "            %d: %d\n",
+				     k, ampdu_mib->ampdu_mib_dist[k]);
+			mib_str += prt_size;
+			buf_size -= prt_size;
+		}
+	}
+ mib_dump_exit:
+	return (length - buf_size);
+}
+
+static void _dump_ampdu_mib(struct ssv_softc *sc, struct ssv_sta_info *sta_info,
+			    void *param)
+{
+	struct mib_dump_data *dump_data = (struct mib_dump_data *)param;
+	struct ieee80211_sta *sta;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	ssize_t buf_size;
+	ssize_t prt_size;
+	char *mib_str = dump_data->prt_buff;
+	if (param == NULL)
+		return;
+	buf_size = dump_data->buff_size - 1;
+	sta = sta_info->sta;
+	if ((sta == NULL) || ((sta_info->s_flags & STA_FLAG_VALID) == 0))
+		return;
+	prt_size = snprintf(mib_str, buf_size,
+			    "STA: %02X-%02X-%02X-%02X-%02X-%02X:\n",
+			    sta->addr[0], sta->addr[1], sta->addr[2],
+			    sta->addr[3], sta->addr[4], sta->addr[5]);
+	mib_str += prt_size;
+	buf_size -= prt_size;
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	prt_size = ampdu_tx_mib_dump(ssv_sta_priv, mib_str, buf_size);
+	mib_str += prt_size;
+	buf_size -= prt_size;
+	dump_data->prt_len = (dump_data->buff_size - 1 - buf_size);
+	dump_data->prt_buff = mib_str;
+	dump_data->buff_size = buf_size;
+}
+
+ssize_t ssv6xxx_ampdu_mib_dump(struct ieee80211_hw *hw, char *mib_str,
+			       ssize_t length)
+{
+	struct ssv_softc *sc = hw->priv;
+	ssize_t buf_size = length - 1;
+	struct mib_dump_data dump_data = { mib_str, buf_size, 0 };
+	if (sc == NULL)
+		return 0;
+	ssv6xxx_foreach_sta(sc, _dump_ampdu_mib, &dump_data);
+	return dump_data.prt_len;
+}
+#endif
+struct sk_buff *_alloc_ampdu_skb(struct ssv_softc *sc,
+				 struct AMPDU_TID_st *ampdu_tid, u32 len)
+{
+	unsigned char *payload_addr;
+	u32 headroom = sc->hw->extra_tx_headroom;
+	u32 offset;
+	u32 cur_max_ampdu_size = SSV_GET_MAX_AMPDU_SIZE(sc->sh);
+	u32 extra_room = sc->sh->tx_desc_len * 2 + 48;
+	u32 max_physical_len = (len
+				&& ((len + extra_room) < cur_max_ampdu_size))
+	    ? (len + extra_room)
+	    : cur_max_ampdu_size;
+	u32 skb_len = max_physical_len + headroom + 3;
+	struct sk_buff *ampdu_skb = __dev_alloc_skb(skb_len, GFP_KERNEL);
+	struct ampdu_hdr_st *ampdu_hdr;
+	if (ampdu_skb == NULL) {
+		dev_err(sc->dev, "AMPDU allocation of size %d(%d) failed\n",
+			len, skb_len);
+		return NULL;
+	}
+	payload_addr = ampdu_skb->data + headroom - sc->sh->tx_desc_len;
+	offset = ((size_t)payload_addr) % 4U;
+	if (offset) {
+		dev_dbg(sc->dev, "Align AMPDU data %d\n", offset);
+		skb_reserve(ampdu_skb, headroom + 4 - offset);
+	} else
+		skb_reserve(ampdu_skb, headroom);
+	ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
+	skb_queue_head_init(&ampdu_hdr->mpdu_q);
+	ampdu_hdr->max_size = max_physical_len - extra_room;
+	ampdu_hdr->size = 0;
+	ampdu_hdr->ampdu_tid = ampdu_tid;
+	memset(ampdu_hdr->ssn, 0xFF, sizeof(ampdu_hdr->ssn));
+	ampdu_hdr->mpdu_num = 0;
+	return ampdu_skb;
+}
+
+bool _is_skb_q_empty(struct ssv_softc *sc, struct sk_buff *skb)
+{
+	u32 ac = skb_get_queue_mapping(skb);
+	u32 hw_txqid = sc->tx.hw_txqid[ac];
+	return AMPDU_HCI_Q_EMPTY(sc->sh, hw_txqid);
+}
+
+static u32 _check_timeout(struct AMPDU_TID_st *ampdu_tid)
+{
+	u16 ssn, head_ssn, end_ssn;
+	unsigned long check_jiffies = jiffies;
+	u32 has_retry = 0;
+	head_ssn = ampdu_tid->ssv_baw_head;
+	ssn = head_ssn;
+	if (ssn == SSV_ILLEGAL_SN)
+		return 0;
+	end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE) % SSV_AMPDU_MAX_SSN;
+	do {
+		struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+		struct SKB_info_st *skb_info;
+		unsigned long cur_jiffies;
+		unsigned long timeout_jiffies;
+		u32 delta_ms;
+		if (skb == NULL)
+			break;
+		skb_info = (SKB_info *) (skb->head);
+		cur_jiffies = jiffies;
+		timeout_jiffies =
+		    skb_info->aggr_timestamp +
+		    msecs_to_jiffies(BA_WAIT_TIMEOUT);
+		if ((skb_info->ampdu_tx_status != AMPDU_ST_SENT)
+		    || time_before(cur_jiffies, timeout_jiffies))
+			break;
+		delta_ms =
+		    jiffies_to_msecs(cur_jiffies - skb_info->aggr_timestamp);
+		prn_aggr_err("rt S%d-T%d-%d (%u)\n",
+			     ((struct ssv_sta_priv_data *)skb_info->sta->
+			      drv_priv)->sta_idx, ampdu_tid->tidno, ssn,
+			     delta_ms);
+		if (delta_ms > 1000) {
+			prn_aggr_err("Last checktime %lu - %lu = %u\n",
+				     check_jiffies, ampdu_tid->timestamp,
+				     jiffies_to_msecs(check_jiffies -
+						      ampdu_tid->timestamp));
+		}
+		has_retry += _mark_skb_retry(skb_info, skb);
+		INC_PKT_SN(ssn);
+	} while (ssn != end_ssn);
+	ampdu_tid->timestamp = check_jiffies;
+	return has_retry;
+}
+
+void ssv6xxx_ampdu_check_timeout(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct AMPDU_TID_st *cur_AMPDU_TID;
+	if (!list_empty(&sc->tx.ampdu_tx_que)) {
+		list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que,
+					list) {
+			u32 has_retry;
+			if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION)
+				continue;
+			has_retry = _check_timeout(cur_AMPDU_TID);
+			if (has_retry) {
+				_collect_retry_frames(cur_AMPDU_TID);
+				ssv6200_ampdu_send_retry(sc->hw, cur_AMPDU_TID,
+							 &cur_AMPDU_TID->
+							 retry_queue, true);
+			}
+		}
+	}
+}
+
+void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
+	struct sk_buff *mpdu;
+	unsigned long cur_jiffies = jiffies;
+	int i;
+	SKB_info *mpdu_skb_info;
+	u16 ssn;
+	if (ampdu_hdr->ampdu_tid->state != AMPDU_STATE_OPERATION)
+		return;
+	spin_lock_bh(&ampdu_hdr->ampdu_tid->pkt_array_lock);
+	for (i = 0; i < ampdu_hdr->mpdu_num; i++) {
+		ssn = ampdu_hdr->ssn[i];
+		mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn);
+		if (mpdu == NULL) {
+			dev_err(sc->dev, "T%d-%d is a NULL MPDU.\n",
+				ampdu_hdr->ampdu_tid->tidno, ssn);
+			continue;
+		}
+		if (ampdu_skb_ssn(mpdu) != ssn) {
+			dev_err(sc->dev, "T%d-%d does not match %d MPDU.\n",
+				ampdu_hdr->ampdu_tid->tidno, ssn,
+				ampdu_skb_ssn(mpdu));
+			continue;
+		}
+		mpdu_skb_info = (SKB_info *) (mpdu->head);
+		mpdu_skb_info->aggr_timestamp = cur_jiffies;
+		mpdu_skb_info->ampdu_tx_status = AMPDU_ST_SENT;
+	}
+	spin_unlock_bh(&ampdu_hdr->ampdu_tid->pkt_array_lock);
+}
diff --git a/drivers/net/wireless/ssv6051/smac/ampdu.h b/drivers/net/wireless/ssv6051/smac/ampdu.h
new file mode 100644
index 00000000000..faa61c4f929
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ampdu.h
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _AMPDU_H_
+#define _AMPDU_H_
+#include <linux/version.h>
+#include <ssv6200_common.h>
+#define Enable_ampdu_debug_log (0)
+#define Enable_AMPDU_Live_Time (0)
+#define Enable_HW_AUTO_CRC_32 (1)
+#define Enable_AMPDU_Rx (1)
+#define Enable_AMPDU_Tx (1)
+#define Enable_AMPDU_FW_Retry (1)
+#define Enable_AMPDU_delay_work (1)
+#define USE_FLUSH_RETRY
+#define USE_AMPDU_TX_STATUS_ARRAY
+#define SSV_AMPDU_FLOW_CONTROL
+#define AMPDU_CHECK_SKB_SEQNO
+#define REPORT_TX_STATUS_DIRECTLY
+#define SSV_AMPDU_aggr_num_max MAX_AGGR_NUM
+#define SSV_AMPDU_seq_num_max (4096)
+#define SSV_AMPDU_retry_counter_max (3)
+#define SSV_AMPDU_tx_group_id_max (64)
+#define SSV_AMPDU_MAX_SSN (4096)
+#define SSV_AMPDU_BA_WINDOW_SIZE (64)
+#define SSV_AMPDU_WINDOW_SIZE (64)
+#define SSV_GET_MAX_AMPDU_SIZE(sh) (((sh)->tx_page_available/(sh)->ampdu_divider) << HW_MMU_PAGE_SHIFT)
+#define SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND (64)
+#define SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND (48)
+#define SSV_AMPDU_timer_period (50)
+#define SSV_AMPDU_TX_TIME_THRESHOLD (50)
+#define SSV_AMPDU_MPDU_LIVE_TIME (SSV_AMPDU_retry_counter_max*8)
+#define SSV_AMPDU_BA_TIME (50)
+#define SSV_ILLEGAL_SN (0xffff)
+#define AMPDU_BUFFER_SIZE (32*1024)
+#define AMPDU_SIGNATURE (0x4E)
+#define AMPDU_DELIMITER_LEN (4)
+#define AMPDU_FCS_LEN (4)
+#define AMPDU_RESERVED_LEN (3)
+#define AMPDU_TX_NAV_MCS_567 (48)
+#define SSV_SEQ_NUM_SHIFT (4)
+#define SSV_RETRY_BIT_SHIFT (11)
+#define IEEE80211_SEQ_SEQ_SHIFT (4)
+#define IEEE80211_AMPDU_BA_LEN (34)
+#define SSV6200_AMPDU_TRIGGER_INDEX 0
+#define SSV_SN_STATUS_Release (0xaa)
+#define SSV_SN_STATUS_Retry (0xbb)
+#define SSV_SN_STATUS_Wait_BA (0xcc)
+#define SSV_SN_STATUS_Discard (0xdd)
+#define AMPDU_HCI_SEND_TAIL_WITH_FLOWCTRL (0)
+#define AMPDU_HCI_SEND_HEAD_WITH_FLOWCTRL (1)
+#define AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL (2)
+#define AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL (3)
+#define SSV_BAR_CTRL_ACK_POLICY_NORMAL (0x0000)
+#define SSV_BAR_CTRL_CBMTID_COMPRESSED_BA (0x0004)
+#define SSV_BAR_CTRL_TID_INFO_SHIFT (12)
+#define AMPDU_STATE_START BIT(0)
+#define AMPDU_STATE_OPERATION BIT(1)
+#define AMPDU_STATE_STOP BIT(2)
+typedef enum {
+	AMPDU_REKEY_PAUSE_STOP = 0,
+	AMPDU_REKEY_PAUSE_START,
+	AMPDU_REKEY_PAUSE_ONGOING,
+	AMPDU_REKEY_PAUSE_DEFER,
+	AMPDU_REKEY_PAUSE_HWKEY_SYNC,
+} AMPDU_REKEY_PAUSE_STATE;
+#define SSV_a_minus_b_in_c(a,b,c) (((a)>=(b))?((a)-(b)):((c)-(b)+(a)))
+#define SSV_AMPDU_SN_a_minus_b(a,b) (SSV_a_minus_b_in_c((a), (b), SSV_AMPDU_seq_num_max))
+#define AMPDU_HCI_SEND(_sh,_sk,_q,_flag) (_sh)->hci.hci_ops->hci_tx((_sk), (_q), (_flag))
+#define AMPDU_HCI_Q_EMPTY(_sh,_q) (_sh)->hci.hci_ops->hci_txq_empty((_q))
+struct ampdu_hdr_st {
+	u32 first_sn;
+	struct sk_buff_head mpdu_q;
+	u32 max_size;
+	u32 size;
+	struct AMPDU_TID_st *ampdu_tid;
+	u16 ssn[MAX_AGGR_NUM];
+	u16 mpdu_num;
+	struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
+	struct ieee80211_sta *sta;
+};
+enum AMPDU_TX_STATUS_E {
+	AMPDU_ST_NON_AMPDU,
+	AMPDU_ST_AGGREGATED,
+	AMPDU_ST_SENT,
+	AMPDU_ST_RETRY,
+	AMPDU_ST_DROPPED,
+	AMPDU_ST_DONE,
+};
+typedef struct AMPDU_MIB_st {
+	u32 ampdu_mib_mpdu_counter;
+	u32 ampdu_mib_retry_counter;
+	u32 ampdu_mib_ampdu_counter;
+	u32 ampdu_mib_aggr_retry_counter;
+	u32 ampdu_mib_bar_counter;
+	u32 ampdu_mib_discard_counter;
+	u32 ampdu_mib_total_BA_counter;
+	u32 ampdu_mib_BA_counter;
+	u32 ampdu_mib_pass_counter;
+	u32 ampdu_mib_dist[SSV_AMPDU_aggr_num_max + 1];
+} AMPDU_MIB;
+typedef struct AMPDU_TID_st {
+	struct list_head list;
+	volatile unsigned long timestamp;
+	u32 tidno;
+	u16 ac;
+	struct ieee80211_sta *sta;
+	u16 ssv_baw_size;
+	u8 agg_num_max;
+	u8 state;
+#ifdef AMPDU_CHECK_SKB_SEQNO
+	u32 last_seqno;
+#endif
+	struct sk_buff_head ampdu_skb_tx_queue;
+	spinlock_t ampdu_skb_tx_queue_lock;
+	struct sk_buff_head retry_queue;
+	struct sk_buff_head release_queue;
+	struct sk_buff *aggr_pkts[SSV_AMPDU_BA_WINDOW_SIZE];
+	volatile u32 aggr_pkt_num;
+	volatile u16 ssv_baw_head;
+	spinlock_t pkt_array_lock;
+	struct sk_buff *cur_ampdu_pkt;
+	struct sk_buff_head early_aggr_ampdu_q;
+	u32 early_aggr_skb_num;
+	struct sk_buff_head ampdu_skb_wait_encry_queue;
+	u32 ampdu_mib_reset;
+	struct AMPDU_MIB_st mib;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct dentry *debugfs_dir;
+	struct sk_buff_head ba_q;
+#endif
+} AMPDU_TID, *p_AMPDU_TID;
+typedef struct AMPDU_DELIMITER_st {
+	u16 reserved:4;
+	u16 length:12;
+	u8 crc;
+	u8 signature;
+} AMPDU_DELIMITER, *p_AMPDU_DELIMITER;
+typedef struct AMPDU_BLOCKACK_st {
+	u16 frame_control;
+	u16 duration;
+	u8 ra_addr[ETH_ALEN];
+	u8 ta_addr[ETH_ALEN];
+	u16 BA_ack_ploicy:1;
+	u16 multi_tid:1;
+	u16 compress_bitmap:1;
+	u16 reserved:9;
+	u16 tid_info:4;
+	u16 BA_fragment_sn:4;
+	u16 BA_ssn:12;
+	u32 BA_sn_bit_map[2];
+} AMPDU_BLOCKACK, *p_AMPDU_BLOCKACK;
+struct ssv_bar {
+	unsigned short frame_control;
+	unsigned short duration;
+	unsigned char ra[6];
+	unsigned char ta[6];
+	unsigned short control;
+	unsigned short start_seq_num;
+} __packed;
+#if Enable_ampdu_debug_log
+#define ampdu_db_log(format, args...) printk("~~~ampdu [%s:%d] "format, __FUNCTION__, __LINE__, ##args)
+#define ampdu_db_log_simple(format, args...) printk(format, ##args)
+#else
+#define ampdu_db_log(...) do {} while (0)
+#define ampdu_db_log_simple(...) do {} while (0)
+#endif
+#if Enable_AMPDU_delay_work
+void ssv6200_ampdu_delayed_work_callback_func(struct work_struct *work);
+#else
+void ssv6200_ampdu_timer_callback_func(unsigned long data);
+#endif
+void ssv6200_ampdu_init(struct ieee80211_hw *hw);
+void ssv6200_ampdu_deinit(struct ieee80211_hw *hw);
+void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw);
+void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta,
+			    struct ieee80211_hw *hw, u16 * ssn);
+void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta,
+				struct ieee80211_hw *hw, u8 buffer_size);
+void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta,
+			   struct ieee80211_hw *hw);
+bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
+u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw);
+void ssv6200_ampdu_timeout_tx(struct ieee80211_hw *hw);
+struct cfg_host_event;
+void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
+void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
+void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta,
+				   struct sk_buff *skb);
+void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw,
+			      struct ieee80211_sta *sta);
+void ssv6xxx_ampdu_postprocess_BA(struct ieee80211_hw *hw);
+void ssv6xxx_ampdu_check_timeout(struct ieee80211_hw *hw);
+void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu);
+extern void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work);
+extern void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work);
+void ssv6xxx_mib_reset(struct ieee80211_hw *hw);
+ssize_t ssv6xxx_mib_dump(struct ieee80211_hw *hw, char *mib_str,
+			 ssize_t length);
+void encry_work(struct work_struct *work);
+void sync_hw_key_work(struct work_struct *work);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/ap.c b/drivers/net/wireless/ssv6051/smac/ap.c
new file mode 100644
index 00000000000..0f2ba6a31a0
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ap.c
@@ -0,0 +1,598 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200.h>
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <linux/sched.h>
+#include <net/mac80211.h>
+#include <ssv6200.h>
+#include "lib.h"
+#include "dev.h"
+#include "ap.h"
+#include "ssv_rc_common.h"
+#include "ssv_rc.h"
+int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);
+#define IS_EQUAL(a,b) ( (a) == (b) )
+#define SET_BIT(v,b) ( (v) |= (0x01<<b) )
+#define CLEAR_BIT(v,b) ( (v) &= ~(0x01<<b) )
+#define IS_BIT_SET(v,b) ( (v) & (0x01<<(b) ) )
+#define PBUF_BASE_ADDR 0x80000000
+#define PBUF_ADDR_SHIFT 16
+#define PBUF_MapPkttoID(_PKT) (((u32)_PKT&0x0FFF0000)>>PBUF_ADDR_SHIFT)
+#define PBUF_MapIDtoPkt(_ID) (PBUF_BASE_ADDR|((_ID)<<PBUF_ADDR_SHIFT))
+#define SSV6xxx_BEACON_MAX_ALLOCATE_CNT 10
+#define MTX_BCN_PKTID_CH_LOCK_SHIFT MTX_BCN_PKTID_CH_LOCK_SFT
+#define MTX_BCN_CFG_VLD_SHIFT MTX_BCN_CFG_VLD_SFT
+#define MTX_BCN_CFG_VLD_MASK MTX_BCN_CFG_VLD_MSK
+#define AUTO_BCN_ONGOING_MASK MTX_AUTO_BCN_ONGOING_MSK
+#define AUTO_BCN_ONGOING_SHIFT MTX_AUTO_BCN_ONGOING_SFT
+#define MTX_BCN_TIMER_EN_SHIFT MTX_BCN_TIMER_EN_SFT
+#define MTX_TSF_TIMER_EN_SHIFT MTX_TSF_TIMER_EN_SFT
+#define MTX_HALT_MNG_UNTIL_DTIM_SHIFT MTX_HALT_MNG_UNTIL_DTIM_SFT
+#define MTX_BCN_ENABLE_MASK (MTX_BCN_TIMER_EN_I_MSK)
+#define MTX_BCN_PERIOD_SHIFT MTX_BCN_PERIOD_SFT
+#define MTX_DTIM_NUM_SHIFT MTX_DTIM_NUM_SFT
+#define MTX_DTIM_OFST0 MTX_DTIM_OFST0_SFT
+enum ssv6xxx_beacon_type {
+	SSV6xxx_BEACON_0,
+	SSV6xxx_BEACON_1,
+};
+static const u32 ssv6xxx_beacon_adr[] = {
+	ADR_MTX_BCN_CFG0,
+	ADR_MTX_BCN_CFG1,
+};
+
+void ssv6xxx_beacon_reg_lock(struct ssv_softc *sc, bool block)
+{
+	u32 val;
+	val = block << MTX_BCN_PKTID_CH_LOCK_SHIFT;
+#ifdef BEACON_DEBUG
+	printk("ssv6xxx_beacon_reg_lock   val[0x:%08x]\n ", val);
+#endif
+	SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_MISC, val);
+}
+
+void ssv6xxx_beacon_set_info(struct ssv_softc *sc, u8 beacon_interval,
+			     u8 dtim_cnt)
+{
+	u32 val;
+	if (beacon_interval == 0)
+		beacon_interval = 100;
+#ifdef BEACON_DEBUG
+	printk("[A] BSS_CHANGED_BEACON_INT beacon_int[%d] dtim_cnt[%d]\n",
+	       beacon_interval, (dtim_cnt));
+#endif
+	val =
+	    (beacon_interval << MTX_BCN_PERIOD_SHIFT) | (dtim_cnt <<
+							 MTX_DTIM_NUM_SHIFT);
+	SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_PRD, val);
+}
+
+bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable)
+{
+	u32 regval = 0;
+	int ret = 0;
+	if (bEnable && !sc->beacon_usage) {
+		printk
+		    ("[A] Reject to set beacon!!!.        ssv6xxx_beacon_enable bEnable[%d] sc->beacon_usage[%d]\n",
+		     bEnable, sc->beacon_usage);
+		sc->enable_beacon = BEACON_WAITING_ENABLED;
+		return 0;
+	}
+	if ((bEnable && (BEACON_ENABLED & sc->enable_beacon)) ||
+	    (!bEnable && !sc->enable_beacon)) {
+		printk
+		    ("[A] ssv6xxx_beacon_enable bEnable[%d] and sc->enable_beacon[%d] are the same. no need to execute.\n",
+		     bEnable, sc->enable_beacon);
+		if (bEnable) {
+			printk("        Ignore enable beacon cmd!!!!\n");
+			return 0;
+		}
+	}
+	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, &regval);
+#ifdef BEACON_DEBUG
+	printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
+#endif
+	regval &= MTX_BCN_ENABLE_MASK;
+#ifdef BEACON_DEBUG
+	printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
+#endif
+	regval |= (bEnable << MTX_BCN_TIMER_EN_SHIFT);
+	ret = SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval);
+#ifdef BEACON_DEBUG
+	printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
+#endif
+	sc->enable_beacon = (bEnable == true) ? BEACON_ENABLED : 0;
+	return ret;
+}
+
+int ssv6xxx_beacon_fill_content(struct ssv_softc *sc, u32 regaddr, u8 * beacon,
+				int size)
+{
+	u32 i, val;
+	u32 *ptr = (u32 *) beacon;
+	size = size / 4;
+	for (i = 0; i < size; i++) {
+		val = (u32) (*(ptr + i));
+#ifdef BEACON_DEBUG
+		printk("[%08x] ", val);
+#endif
+		SMAC_REG_WRITE(sc->sh, regaddr + i * 4, val);
+	}
+#ifdef BEACON_DEBUG
+	printk("\n");
+#endif
+	return 0;
+}
+
+void ssv6xxx_beacon_fill_tx_desc(struct ssv_softc *sc,
+				 struct sk_buff *beacon_skb)
+{
+	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(beacon_skb);
+	struct ssv6200_tx_desc *tx_desc;
+	u16 pb_offset = TXPB_OFFSET;
+	struct ssv_rate_info ssv_rate;
+	skb_push(beacon_skb, pb_offset);
+	tx_desc = (struct ssv6200_tx_desc *)beacon_skb->data;
+	memset(tx_desc, 0, pb_offset);
+	ssv6xxx_rc_hw_rate_idx(sc, tx_info, &ssv_rate);
+	tx_desc->len = beacon_skb->len - pb_offset;
+	tx_desc->c_type = M2_TXREQ;
+	tx_desc->f80211 = 1;
+	tx_desc->ack_policy = 1;
+	tx_desc->hdr_offset = pb_offset;
+	tx_desc->hdr_len = 24;
+	tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len;
+	tx_desc->crate_idx = ssv_rate.crate_hw_idx;
+	tx_desc->drate_idx = ssv_rate.drate_hw_idx;
+	skb_put(beacon_skb, 4);
+}
+
+inline enum ssv6xxx_beacon_type ssv6xxx_beacon_get_valid_reg(struct ssv_softc
+							     *sc)
+{
+	u32 regval = 0;
+	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_MISC, &regval);
+	regval &= MTX_BCN_CFG_VLD_MASK;
+	regval = regval >> MTX_BCN_CFG_VLD_SHIFT;
+	if (regval == 0x2 || regval == 0x0)
+		return SSV6xxx_BEACON_0;
+	else if (regval == 0x1)
+		return SSV6xxx_BEACON_1;
+	else
+		printk("=============>ERROR!!drv_bcn_reg_available\n");
+	return SSV6xxx_BEACON_0;
+}
+
+bool ssv6xxx_beacon_set(struct ssv_softc *sc, struct sk_buff *beacon_skb,
+			int dtim_offset)
+{
+	u32 reg_tx_beacon_adr = ADR_MTX_BCN_CFG0;
+	enum ssv6xxx_beacon_type avl_bcn_type = SSV6xxx_BEACON_0;
+	bool ret = true;
+	int val;
+	ssv6xxx_beacon_reg_lock(sc, 1);
+	avl_bcn_type = ssv6xxx_beacon_get_valid_reg(sc);
+	if (avl_bcn_type == SSV6xxx_BEACON_1)
+		reg_tx_beacon_adr = ADR_MTX_BCN_CFG1;
+#ifdef BEACON_DEBUG
+	printk("[A] ssv6xxx_beacon_set avl_bcn_type[%d]\n", avl_bcn_type);
+#endif
+	do {
+		if (IS_BIT_SET(sc->beacon_usage, avl_bcn_type)) {
+#ifdef BEACON_DEBUG
+			printk
+			    ("[A] beacon has already been set old len[%d] new len[%d]\n",
+			     sc->beacon_info[avl_bcn_type].len,
+			     beacon_skb->len);
+#endif
+			if (sc->beacon_info[avl_bcn_type].len >=
+			    beacon_skb->len) {
+				break;
+			} else {
+				if (false ==
+				    ssv6xxx_pbuf_free(sc,
+						      sc->
+						      beacon_info[avl_bcn_type].
+						      pubf_addr)) {
+#ifdef BEACON_DEBUG
+					printk
+					    ("=============>ERROR!!Intend to allcoate beacon from ASIC fail.\n");
+#endif
+					ret = false;
+					goto out;
+				}
+				CLEAR_BIT(sc->beacon_usage, avl_bcn_type);
+			}
+		}
+		sc->beacon_info[avl_bcn_type].pubf_addr =
+		    ssv6xxx_pbuf_alloc(sc, beacon_skb->len, TX_BUF);
+		sc->beacon_info[avl_bcn_type].len = beacon_skb->len;
+		if (sc->beacon_info[avl_bcn_type].pubf_addr == 0) {
+			ret = false;
+			goto out;
+		}
+		SET_BIT(sc->beacon_usage, avl_bcn_type);
+#ifdef BEACON_DEBUG
+		printk
+		    ("[A] beacon type[%d] usage[%d] allocate new beacon addr[%08x] \n",
+		     avl_bcn_type, sc->beacon_usage,
+		     sc->beacon_info[avl_bcn_type].pubf_addr);
+#endif
+	} while (0);
+	ssv6xxx_beacon_fill_content(sc, sc->beacon_info[avl_bcn_type].pubf_addr,
+				    beacon_skb->data, beacon_skb->len);
+	val =
+	    (PBUF_MapPkttoID(sc->beacon_info[avl_bcn_type].pubf_addr)) |
+	    (dtim_offset << MTX_DTIM_OFST0);
+	SMAC_REG_WRITE(sc->sh, reg_tx_beacon_adr, val);
+#ifdef BEACON_DEBUG
+	printk("[A] update to register reg_tx_beacon_adr[%08x] val[%08x]\n",
+	       reg_tx_beacon_adr, val);
+#endif
+ out:
+	ssv6xxx_beacon_reg_lock(sc, 0);
+	if (sc->beacon_usage && (sc->enable_beacon & BEACON_WAITING_ENABLED)) {
+		printk("[A] enable beacon for BEACON_WAITING_ENABLED flags\n");
+		ssv6xxx_beacon_enable(sc, true);
+	}
+	return ret;
+}
+
+inline bool ssv6xxx_auto_bcn_ongoing(struct ssv_softc *sc)
+{
+	u32 regval;
+	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_MISC, &regval);
+	return ((AUTO_BCN_ONGOING_MASK & regval) >> AUTO_BCN_ONGOING_SHIFT);
+}
+
+void ssv6xxx_beacon_release(struct ssv_softc *sc)
+{
+	int cnt = 10;
+	printk("[A] ssv6xxx_beacon_release Enter\n");
+	cancel_work_sync(&sc->set_tim_work);
+	do {
+		if (ssv6xxx_auto_bcn_ongoing(sc))
+			ssv6xxx_beacon_enable(sc, false);
+		else
+			break;
+		cnt--;
+		if (cnt <= 0)
+			break;
+	} while (1);
+	if (IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_0)) {
+		ssv6xxx_pbuf_free(sc,
+				  sc->beacon_info[SSV6xxx_BEACON_0].pubf_addr);
+		CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_0);
+	}
+	if (IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_1)) {
+		ssv6xxx_pbuf_free(sc,
+				  sc->beacon_info[SSV6xxx_BEACON_1].pubf_addr);
+		CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_1);
+	}
+	sc->enable_beacon = 0;
+	if (sc->beacon_buf) {
+		dev_kfree_skb_any(sc->beacon_buf);
+		sc->beacon_buf = NULL;
+	}
+#ifdef BEACON_DEBUG
+	printk("[A] ssv6xxx_beacon_release leave\n");
+#endif
+}
+
+void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw,
+			   struct ieee80211_vif *vif, bool aid0_bit_set)
+{
+	struct sk_buff *skb;
+	struct sk_buff *old_skb = NULL;
+	u16 tim_offset, tim_length;
+	if (sc == NULL || hw == NULL || vif == NULL) {
+		printk("[Error]........ssv6xxx_beacon_change input error\n");
+		return;
+	}
+	do {
+		skb = ieee80211_beacon_get_tim(hw, vif,
+					       &tim_offset, &tim_length);
+		if (skb == NULL) {
+			printk("[Error]........skb is NULL\n");
+			break;
+		}
+		if (tim_offset && tim_length >= 6) {
+			skb->data[tim_offset + 2] = 0;
+			if (aid0_bit_set)
+				skb->data[tim_offset + 4] |= 1;
+			else
+				skb->data[tim_offset + 4] &= ~1;
+		}
+#ifdef BEACON_DEBUG
+		printk("[A] beacon len [%d] tim_offset[%d]\n", skb->len,
+		       tim_offset);
+#endif
+		ssv6xxx_beacon_fill_tx_desc(sc, skb);
+#ifdef BEACON_DEBUG
+		printk("[A] beacon len [%d] tim_offset[%d]\n", skb->len,
+		       tim_offset);
+#endif
+		if (sc->beacon_buf) {
+			if (memcmp
+			    (sc->beacon_buf->data, skb->data,
+			     (skb->len - FCS_LEN)) == 0) {
+				old_skb = skb;
+				break;
+			} else {
+				old_skb = sc->beacon_buf;
+				sc->beacon_buf = skb;
+			}
+		} else {
+			sc->beacon_buf = skb;
+		}
+		tim_offset += 2;
+		if (ssv6xxx_beacon_set(sc, skb, tim_offset)) {
+			u8 dtim_cnt = vif->bss_conf.dtim_period - 1;
+			if (sc->beacon_dtim_cnt != dtim_cnt) {
+				sc->beacon_dtim_cnt = dtim_cnt;
+#ifdef BEACON_DEBUG
+				printk("[A] beacon_dtim_cnt [%d]\n",
+				       sc->beacon_dtim_cnt);
+#endif
+				ssv6xxx_beacon_set_info(sc, sc->beacon_interval,
+							sc->beacon_dtim_cnt);
+			}
+		}
+	} while (0);
+	if (old_skb)
+		dev_kfree_skb_any(old_skb);
+}
+
+void ssv6200_set_tim_work(struct work_struct *work)
+{
+	struct ssv_softc *sc =
+	    container_of(work, struct ssv_softc, set_tim_work);
+#ifdef BROADCAST_DEBUG
+	printk("%s() enter\n", __FUNCTION__);
+#endif
+	ssv6xxx_beacon_change(sc, sc->hw, sc->ap_vif, sc->aid0_bit_set);
+#ifdef BROADCAST_DEBUG
+	printk("%s() leave\n", __FUNCTION__);
+#endif
+}
+
+int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq)
+{
+	u32 len;
+	unsigned long flags;
+	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+	len = bcast_txq->cur_qsize;
+	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+	return len;
+}
+
+struct sk_buff *ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq,
+				      u8 * remain_len)
+{
+	struct sk_buff *skb = NULL;
+	unsigned long flags;
+	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+	if (bcast_txq->cur_qsize) {
+		bcast_txq->cur_qsize--;
+		if (remain_len)
+			*remain_len = bcast_txq->cur_qsize;
+		skb = __skb_dequeue(&bcast_txq->qhead);
+	}
+	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+	return skb;
+}
+
+int ssv6200_bcast_enqueue(struct ssv_softc *sc,
+			  struct ssv6xxx_bcast_txq *bcast_txq,
+			  struct sk_buff *skb)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+	if (bcast_txq->cur_qsize >= SSV6200_MAX_BCAST_QUEUE_LEN) {
+		struct sk_buff *old_skb;
+		old_skb = __skb_dequeue(&bcast_txq->qhead);
+		bcast_txq->cur_qsize--;
+		ssv6xxx_txbuf_free_skb(old_skb, (void *)sc);
+		printk("[B] ssv6200_bcast_enqueue - remove oldest queue\n");
+	}
+	__skb_queue_tail(&bcast_txq->qhead, skb);
+	bcast_txq->cur_qsize++;
+	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+	return bcast_txq->cur_qsize;
+}
+
+void ssv6200_bcast_flush(struct ssv_softc *sc,
+			 struct ssv6xxx_bcast_txq *bcast_txq)
+{
+	struct sk_buff *skb;
+	unsigned long flags;
+#ifdef BCAST_DEBUG
+	printk("ssv6200_bcast_flush\n");
+#endif
+	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+	while (bcast_txq->cur_qsize > 0) {
+		skb = __skb_dequeue(&bcast_txq->qhead);
+		bcast_txq->cur_qsize--;
+		ssv6xxx_txbuf_free_skb(skb, (void *)sc);
+	}
+	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+}
+
+static int queue_block_cnt = 0;
+void ssv6200_bcast_tx_work(struct work_struct *work)
+{
+	struct ssv_softc *sc =
+	    container_of(work, struct ssv_softc, bcast_tx_work.work);
+	struct sk_buff *skb;
+	int i;
+	u8 remain_size;
+	unsigned long flags;
+	bool needtimer = true;
+	long tmo = sc->bcast_interval;
+	spin_lock_irqsave(&sc->ps_state_lock, flags);
+	do {
+#ifdef BCAST_DEBUG
+		printk
+		    ("[B] bcast_timer: hw_mng_used[%d] HCI_TXQ_EMPTY[%d] bcast_queue_len[%d].....................\n",
+		     sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4),
+		     ssv6200_bcast_queue_len(&sc->bcast_txq));
+#endif
+		if (sc->hw_mng_used != 0 || false == HCI_TXQ_EMPTY(sc->sh, 4)) {
+#ifdef BCAST_DEBUG
+			printk
+			    ("HW queue still have frames insdide. skip this one hw_mng_used[%d] bEmptyTXQ4[%d]\n",
+			     sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4));
+#endif
+			queue_block_cnt++;
+			if (queue_block_cnt > 5) {
+				queue_block_cnt = 0;
+				ssv6200_bcast_flush(sc, &sc->bcast_txq);
+				needtimer = false;
+			}
+			break;
+		}
+		queue_block_cnt = 0;
+		for (i = 0; i < SSV6200_ID_MANAGER_QUEUE; i++) {
+			skb =
+			    ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size);
+			if (!skb) {
+				needtimer = false;
+				break;
+			}
+			if ((0 != remain_size) &&
+			    (SSV6200_ID_MANAGER_QUEUE - 1) != i) {
+				struct ieee80211_hdr *hdr;
+				struct ssv6200_tx_desc *tx_desc =
+				    (struct ssv6200_tx_desc *)skb->data;
+				hdr =
+				    (struct ieee80211_hdr *)((u8 *) tx_desc +
+							     tx_desc->
+							     hdr_offset);
+				hdr->frame_control |=
+				    cpu_to_le16(IEEE80211_FCTL_MOREDATA);
+			}
+#ifdef BCAST_DEBUG
+			printk("[B] bcast_timer:tx remain_size[%d] i[%d]\n",
+			       remain_size, i);
+#endif
+			spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+			if (HCI_SEND(sc->sh, skb, 4) < 0) {
+				printk("bcast_timer send fail!!!!!!! \n");
+				ssv6xxx_txbuf_free_skb(skb, (void *)sc);
+				BUG_ON(1);
+			}
+			spin_lock_irqsave(&sc->ps_state_lock, flags);
+		}
+	} while (0);
+	if (needtimer) {
+#ifdef BCAST_DEBUG
+		printk
+		    ("[B] bcast_timer:need more timer to tx bcast frame time[%d]\n",
+		     sc->bcast_interval);
+#endif
+		queue_delayed_work(sc->config_wq, &sc->bcast_tx_work, tmo);
+	} else {
+#ifdef BCAST_DEBUG
+		printk("[B] bcast_timer: ssv6200_bcast_stop\n");
+#endif
+		ssv6200_bcast_stop(sc);
+	}
+	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+#ifdef BCAST_DEBUG
+	printk("[B] bcast_timer: leave.....................\n");
+#endif
+}
+
+void ssv6200_bcast_start_work(struct work_struct *work)
+{
+	struct ssv_softc *sc =
+	    container_of(work, struct ssv_softc, bcast_start_work);
+#ifdef BCAST_DEBUG
+	printk("[B] ssv6200_bcast_start_work==\n");
+#endif
+	sc->bcast_interval = (sc->beacon_dtim_cnt + 1) *
+	    (sc->beacon_interval + 20) * HZ / 1000;
+	if (!sc->aid0_bit_set) {
+		sc->aid0_bit_set = true;
+		ssv6xxx_beacon_change(sc, sc->hw, sc->ap_vif, sc->aid0_bit_set);
+		queue_delayed_work(sc->config_wq,
+				   &sc->bcast_tx_work, sc->bcast_interval);
+#ifdef BCAST_DEBUG
+		printk("[B] bcast_start_work: Modify timer to DTIM[%d]ms==\n",
+		       (sc->beacon_dtim_cnt + 1) * (sc->beacon_interval + 20));
+#endif
+	}
+}
+
+void ssv6200_bcast_stop_work(struct work_struct *work)
+{
+	struct ssv_softc *sc =
+	    container_of(work, struct ssv_softc, bcast_stop_work.work);
+	long tmo = HZ / 100;
+#ifdef BCAST_DEBUG
+	printk("[B] ssv6200_bcast_stop_work\n");
+#endif
+	if (sc->aid0_bit_set) {
+		if (0 == ssv6200_bcast_queue_len(&sc->bcast_txq)) {
+			cancel_delayed_work_sync(&sc->bcast_tx_work);
+			sc->aid0_bit_set = false;
+			ssv6xxx_beacon_change(sc, sc->hw,
+					      sc->ap_vif, sc->aid0_bit_set);
+#ifdef BCAST_DEBUG
+			printk("remove group bit in DTIM\n");
+#endif
+		} else {
+#ifdef BCAST_DEBUG
+			printk
+			    ("bcast_stop_work: bcast queue still have data. just modify timer to 10ms\n");
+#endif
+			queue_delayed_work(sc->config_wq,
+					   &sc->bcast_tx_work, tmo);
+		}
+	}
+}
+
+void ssv6200_bcast_stop(struct ssv_softc *sc)
+{
+	queue_delayed_work(sc->config_wq,
+			   &sc->bcast_stop_work,
+			   sc->beacon_interval * HZ / 1024);
+}
+
+void ssv6200_bcast_start(struct ssv_softc *sc)
+{
+	queue_work(sc->config_wq, &sc->bcast_start_work);
+}
+
+void ssv6200_release_bcast_frame_res(struct ssv_softc *sc,
+				     struct ieee80211_vif *vif)
+{
+	unsigned long flags;
+	struct ssv_vif_priv_data *priv_vif =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	spin_lock_irqsave(&sc->ps_state_lock, flags);
+	priv_vif->sta_asleep_mask = 0;
+	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+	cancel_work_sync(&sc->bcast_start_work);
+	cancel_delayed_work_sync(&sc->bcast_stop_work);
+	ssv6200_bcast_flush(sc, &sc->bcast_txq);
+	cancel_delayed_work_sync(&sc->bcast_tx_work);
+}
diff --git a/drivers/net/wireless/ssv6051/smac/ap.h b/drivers/net/wireless/ssv6051/smac/ap.h
new file mode 100644
index 00000000000..93b5275715b
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ap.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _AP_H_
+#define _AP_H_
+#define BEACON_WAITING_ENABLED 1<<0
+#define BEACON_ENABLED 1<<1
+void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw,
+			   struct ieee80211_vif *vif, bool aid0_bit_set);
+void ssv6xxx_beacon_set_info(struct ssv_softc *sc, u8 beacon_interval,
+			     u8 dtim_cnt);
+bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable);
+void ssv6xxx_beacon_release(struct ssv_softc *sc);
+void ssv6200_set_tim_work(struct work_struct *work);
+void ssv6200_bcast_start_work(struct work_struct *work);
+void ssv6200_bcast_stop_work(struct work_struct *work);
+void ssv6200_bcast_tx_work(struct work_struct *work);
+int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);
+struct sk_buff *ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq,
+				      u8 * remain_len);
+int ssv6200_bcast_enqueue(struct ssv_softc *sc,
+			  struct ssv6xxx_bcast_txq *bcast_txq,
+			  struct sk_buff *skb);
+void ssv6200_bcast_start(struct ssv_softc *sc);
+void ssv6200_bcast_stop(struct ssv_softc *sc);
+void ssv6200_release_bcast_frame_res(struct ssv_softc *sc,
+				     struct ieee80211_vif *vif);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/dev.c b/drivers/net/wireless/ssv6051/smac/dev.c
new file mode 100644
index 00000000000..4b9c66a71d9
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/dev.c
@@ -0,0 +1,3880 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <linux/kthread.h>
+#include <linux/ktime.h>
+
+#include <net/mac80211.h>
+#include <ssv6200.h>
+#include <hci/hctrl.h>
+#include "linux_80211.h"
+#include "lib.h"
+#include "ssv_rc.h"
+#include "ssv_ht_rc.h"
+#include "dev.h"
+#include "ap.h"
+#include "init.h"
+#include "p2p.h"
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+#include "ssv6xxx_debugfs.h"
+#endif
+struct rssi_res_st rssi_res, *p_rssi_res;
+#define NO_USE_RXQ_LOCK
+#ifndef WLAN_CIPHER_SUITE_SMS4
+#define WLAN_CIPHER_SUITE_SMS4 0x00147201
+#endif
+#define MAX_TX_Q_LEN (64)
+#define LOW_TX_Q_LEN (MAX_TX_Q_LEN/2)
+static u16 bits_per_symbol[][2] = {
+	{26, 54},
+	{52, 108},
+	{78, 162},
+	{104, 216},
+	{156, 324},
+	{208, 432},
+	{234, 486},
+	{260, 540},
+};
+
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
+extern unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage);
+#endif
+struct ssv6xxx_calib_table {
+	u16 channel_id;
+	u32 rf_ctrl_N;
+	u32 rf_ctrl_F;
+	u16 rf_precision_default;
+};
+static void _process_rx_q(struct ssv_softc *sc, struct sk_buff_head *rx_q,
+			  spinlock_t * rx_q_lock);
+static u32 _process_tx_done(struct ssv_softc *sc);
+
+void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)args;
+	if (!skb)
+		return;
+	ieee80211_free_txskb(sc->hw, skb);
+}
+
+#define ADDRESS_OFFSET 16
+#define HW_ID_OFFSET 7
+#define CH0_FULL_MASK CH0_FULL_MSK
+#define MAX_FAIL_COUNT 100
+#define MAX_RETRY_COUNT 20
+inline bool ssv6xxx_mcu_input_full(struct ssv_softc *sc)
+{
+	u32 regval = 0;
+	SMAC_REG_READ(sc->sh, ADR_MCU_STATUS, &regval);
+	return CH0_FULL_MASK & regval;
+}
+
+u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type)
+{
+	u32 regval, pad;
+	int cnt = MAX_RETRY_COUNT;
+	int page_cnt =
+	    (size + ((1 << HW_MMU_PAGE_SHIFT) - 1)) >> HW_MMU_PAGE_SHIFT;
+	regval = 0;
+	mutex_lock(&sc->mem_mutex);
+	pad = size % 4;
+	size += pad;
+	do {
+		SMAC_REG_WRITE(sc->sh, ADR_WR_ALC, (size | (type << 16)));
+		SMAC_REG_READ(sc->sh, ADR_WR_ALC, &regval);
+		if (regval == 0) {
+			cnt--;
+			msleep(1);
+		} else
+			break;
+	} while (cnt);
+	if (type == TX_BUF) {
+		sc->sh->tx_page_available -= page_cnt;
+		sc->sh->page_count[PACKET_ADDR_2_ID(regval)] = page_cnt;
+	}
+	mutex_unlock(&sc->mem_mutex);
+	if (regval == 0)
+		dev_err(sc->dev,
+			"Failed to allocate packet buffer of %d bytes in %d type.",
+			size, type);
+	else {
+		dev_dbg(sc->dev,
+			"Allocated %d type packet buffer of size %d (%d) at address %x.\n",
+			type, size, page_cnt, regval);
+	}
+	return regval;
+}
+
+bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr)
+{
+	u32 regval = 0;
+	u16 failCount = 0;
+	u8 *p_tx_page_cnt = &sc->sh->page_count[PACKET_ADDR_2_ID(pbuf_addr)];
+	while (ssv6xxx_mcu_input_full(sc)) {
+		if (failCount++ < 1000)
+			continue;
+		dev_err(sc->dev, "Error in mailbox block after %d iterations\n", failCount);
+		return false;
+	}
+	mutex_lock(&sc->mem_mutex);
+	regval =
+	    ((M_ENG_TRASH_CAN << HW_ID_OFFSET) | (pbuf_addr >> ADDRESS_OFFSET));
+	SMAC_REG_WRITE(sc->sh, ADR_CH0_TRIG_1, regval);
+	if (*p_tx_page_cnt) {
+		sc->sh->tx_page_available += *p_tx_page_cnt;
+		*p_tx_page_cnt = 0;
+	}
+	mutex_unlock(&sc->mem_mutex);
+	return true;
+}
+
+static const struct ssv6xxx_calib_table vt_tbl[SSV6XXX_IQK_CFG_XTAL_MAX][14] = {
+	{
+	 {1, 0xB9, 0x89D89E, 3859},
+	 {2, 0xB9, 0xEC4EC5, 3867},
+	 {3, 0xBA, 0x4EC4EC, 3875},
+	 {4, 0xBA, 0xB13B14, 3883},
+	 {5, 0xBB, 0x13B13B, 3891},
+	 {6, 0xBB, 0x762762, 3899},
+	 {7, 0xBB, 0xD89D8A, 3907},
+	 {8, 0xBC, 0x3B13B1, 3915},
+	 {9, 0xBC, 0x9D89D9, 3923},
+	 {10, 0xBD, 0x000000, 3931},
+	 {11, 0xBD, 0x627627, 3939},
+	 {12, 0xBD, 0xC4EC4F, 3947},
+	 {13, 0xBE, 0x276276, 3955},
+	 {14, 0xBF, 0x13B13B, 3974},
+	 },
+	{
+	 {1, 0xf1, 0x333333, 3859},
+	 {2, 0xf1, 0xB33333, 3867},
+	 {3, 0xf2, 0x333333, 3875},
+	 {4, 0xf2, 0xB33333, 3883},
+	 {5, 0xf3, 0x333333, 3891},
+	 {6, 0xf3, 0xB33333, 3899},
+	 {7, 0xf4, 0x333333, 3907},
+	 {8, 0xf4, 0xB33333, 3915},
+	 {9, 0xf5, 0x333333, 3923},
+	 {10, 0xf5, 0xB33333, 3931},
+	 {11, 0xf6, 0x333333, 3939},
+	 {12, 0xf6, 0xB33333, 3947},
+	 {13, 0xf7, 0x333333, 3955},
+	 {14, 0xf8, 0x666666, 3974},
+	 },
+	{
+	 {1, 0xC9, 0x000000, 3859},
+	 {2, 0xC9, 0x6AAAAB, 3867},
+	 {3, 0xC9, 0xD55555, 3875},
+	 {4, 0xCA, 0x400000, 3883},
+	 {5, 0xCA, 0xAAAAAB, 3891},
+	 {6, 0xCB, 0x155555, 3899},
+	 {7, 0xCB, 0x800000, 3907},
+	 {8, 0xCB, 0xEAAAAB, 3915},
+	 {9, 0xCC, 0x555555, 3923},
+	 {10, 0xCC, 0xC00000, 3931},
+	 {11, 0xCD, 0x2AAAAB, 3939},
+	 {12, 0xCD, 0x955555, 3947},
+	 {13, 0xCE, 0x000000, 3955},
+	 {14, 0xCF, 0x000000, 3974},
+	 }
+};
+
+#define FAIL_MAX 100
+#define RETRY_MAX 20
+int ssv6xxx_set_channel(struct ssv_softc *sc, int ch)
+{
+	struct ssv_hw *sh = sc->sh;
+	int retry_cnt, fail_cnt = 0;
+	u32 regval;
+	int ret = -1;
+	int chidx;
+	bool chidx_vld = 0;
+	dev_dbg(sc->dev, "Setting channel to %d\n", ch);
+	if ((sh->cfg.chip_identity == SSV6051Z)
+	    || (sc->sh->cfg.chip_identity == SSV6051P)) {
+		if ((ch == 13) || (ch == 14)) {
+			if (sh->ipd_channel_touch == 0) {
+				for (chidx = 0; chidx < sh->ch_cfg_size;
+				     chidx++) {
+					SMAC_REG_WRITE(sh,
+						       sh->p_ch_cfg[chidx].
+						       reg_addr,
+						       sh->p_ch_cfg[chidx].
+						       ch13_14_value);
+				}
+				sh->ipd_channel_touch = 1;
+			}
+		} else {
+			if (sh->ipd_channel_touch) {
+				for (chidx = 0; chidx < sh->ch_cfg_size;
+				     chidx++) {
+					SMAC_REG_WRITE(sh,
+						       sh->p_ch_cfg[chidx].
+						       reg_addr,
+						       sh->p_ch_cfg[chidx].
+						       ch1_12_value);
+				}
+				sh->ipd_channel_touch = 0;
+			}
+		}
+	}
+	for (chidx = 0; chidx < 14; chidx++) {
+		if (vt_tbl[sh->cfg.crystal_type][chidx].channel_id == ch) {
+			chidx_vld = 1;
+			break;
+		}
+	}
+	if (chidx_vld == 0) {
+		dev_dbg(sc->dev, "%s(): fail! channel_id not found in vt_tbl\n",
+			__FUNCTION__);
+		goto exit;
+	}
+	if ((ret = ssv6xxx_rf_disable(sc->sh)) != 0)
+		goto exit;
+	do {
+		if ((sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M)
+		    || (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M)) {
+			if ((ret =
+			     SMAC_REG_SET_BITS(sc->sh, ADR_SYN_DIV_SDM_XOSC,
+					       (0x00 << 13),
+					       (0x01 << 13))) != 0)
+				break;
+		} else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_40M) {
+			if ((ret =
+			     SMAC_REG_SET_BITS(sc->sh, ADR_SYN_DIV_SDM_XOSC,
+					       (0x01 << 13),
+					       (0x01 << 13))) != 0)
+				break;
+		} else {
+			dev_warn(sc->dev, "Illegal crystal setting in ssv6xxx_set_channel\n");
+			BUG_ON(1);
+		}
+		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SX_LCK_BIN_REGISTERS_I,
+					     (0x01 << 19), (0x01 << 19))) != 0)
+			break;
+		regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_F;
+		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_1,
+					     (regval << 0),
+					     (0x00ffffff << 0))) != 0)
+			break;
+		regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_N;
+		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_2,
+					     (regval << 0),
+					     (0x07ff << 0))) != 0)
+			break;
+		if ((ret =
+		     SMAC_REG_READ(sc->sh, ADR_SX_LCK_BIN_REGISTERS_I,
+				   &regval)) != 0)
+			break;
+		regval =
+		    vt_tbl[sh->cfg.crystal_type][chidx].rf_precision_default;
+		if ((ret =
+		     SMAC_REG_SET_BITS(sc->sh, ADR_SX_LCK_BIN_REGISTERS_II,
+				       (regval << 0), (0x1fff << 0))) != 0)
+			break;
+		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER,
+					     (0x00 << 14), (0x01 << 14))) != 0)
+			break;
+		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER,
+					     (0x01 << 14), (0x01 << 14))) != 0)
+			break;
+		retry_cnt = 0;
+		do {
+			mdelay(1);
+			if ((ret =
+			     SMAC_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_1,
+					   &regval)) != 0)
+				break;
+			if (regval & 0x00000002) {
+				if ((ret =
+				     SMAC_REG_READ(sc->sh,
+						   ADR_READ_ONLY_FLAGS_2,
+						   &regval)) != 0)
+					break;
+				ret = ssv6xxx_rf_enable(sc->sh);
+				//dev_info(sc->dev, "Lock to channel %d ([0xce010098]=%x)!!\n", vt_tbl[sh->cfg.crystal_type][chidx].channel_id, regval);
+				sc->hw_chan = ch;
+				goto exit;
+			}
+			retry_cnt++;
+		}
+		while (retry_cnt < RETRY_MAX);
+		fail_cnt++;
+		dev_warn(sc->dev, "calibation fail after %d iterations\n", fail_cnt);
+	}
+	while ((fail_cnt < FAIL_MAX) && (ret == 0));
+ exit:
+	if (ch == 14 && regval == 0xff0) {
+		SMAC_IFC_RESET(sc->sh);
+		ssv6xxx_restart_hw(sc);
+	}
+	if (ch <= 7) {
+		if (sh->cfg.tx_power_index_1) {
+			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+			regval &= RG_TX_GAIN_OFFSET_I_MSK;
+			regval |=
+			    (sh->cfg.tx_power_index_1 << RG_TX_GAIN_OFFSET_SFT);
+			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+		} else if (sh->cfg.tx_power_index_2) {
+			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+			regval &= RG_TX_GAIN_OFFSET_I_MSK;
+			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+		}
+	} else {
+		if (sh->cfg.tx_power_index_2) {
+			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+			regval &= RG_TX_GAIN_OFFSET_I_MSK;
+			regval |=
+			    (sh->cfg.tx_power_index_2 << RG_TX_GAIN_OFFSET_SFT);
+			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+		} else if (sh->cfg.tx_power_index_1) {
+			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+			regval &= RG_TX_GAIN_OFFSET_I_MSK;
+			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+		}
+	}
+	return ret;
+}
+
+#ifdef CONFIG_SSV_SMARTLINK
+int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch)
+{
+	*pch = sc->hw_chan;
+	return 0;
+}
+
+int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept)
+{
+	u32 val = 0;
+	if (accept) {
+		val = 0x2;
+	} else {
+		val = 0x3;
+	}
+	SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB13, val);
+	return 0;
+}
+
+int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept)
+{
+	u32 val = 0;
+	SMAC_REG_READ(sc->sh, ADR_MRX_FLT_TB13, &val);
+	if (val == 0x2) {
+		*paccept = 1;
+	} else {
+		*paccept = 0;
+	}
+	return 0;
+}
+#endif
+int ssv6xxx_rf_enable(struct ssv_hw *sh)
+{
+	return SMAC_REG_SET_BITS(sh, 0xce010000, (0x02 << 12), (0x03 << 12)
+	    );
+}
+
+int ssv6xxx_rf_disable(struct ssv_hw *sh)
+{
+	return SMAC_REG_SET_BITS(sh, 0xce010000, (0x01 << 12), (0x03 << 12)
+	    );
+}
+
+int ssv6xxx_update_decision_table(struct ssv_softc *sc)
+{
+	int i;
+	for (i = 0; i < MAC_DECITBL1_SIZE; i++) {
+		SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + i * 4,
+			       sc->mac_deci_tbl[i]);
+		SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_TB0 + i * 4,
+				 sc->mac_deci_tbl[i]);
+	}
+	for (i = 0; i < MAC_DECITBL2_SIZE; i++) {
+		SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN0 + i * 4,
+			       sc->mac_deci_tbl[i + MAC_DECITBL1_SIZE]);
+		SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_EN0 + i * 4,
+				 sc->mac_deci_tbl[i + MAC_DECITBL1_SIZE]);
+	}
+	return 0;
+}
+
+static int ssv6xxx_frame_hdrlen(struct ieee80211_hdr *hdr, bool is_ht)
+{
+#define CTRL_FRAME_INDEX(fc) ((hdr->frame_control-IEEE80211_STYPE_BACK_REQ)>>4)
+	u16 fc, CTRL_FLEN[] = { 16, 16, 16, 16, 10, 10, 16, 16 };
+	int hdr_len = 24;
+	fc = hdr->frame_control;
+	if (ieee80211_is_ctl(fc))
+		hdr_len = CTRL_FLEN[CTRL_FRAME_INDEX(fc)];
+	else if (ieee80211_is_mgmt(fc)) {
+		if (ieee80211_has_order(fc))
+			hdr_len += ((is_ht == 1) ? 4 : 0);
+	} else {
+		if (ieee80211_has_a4(fc))
+			hdr_len += 6;
+		if (ieee80211_is_data_qos(fc)) {
+			hdr_len += 2;
+			if (ieee80211_has_order(hdr->frame_control) &&
+			    is_ht == true)
+				hdr_len += 4;
+		}
+	}
+	return hdr_len;
+}
+
+static u32 ssv6xxx_ht_txtime(u8 rix, int pktlen, int width,
+			     int half_gi, bool is_gf)
+{
+	u32 nbits, nsymbits, duration, nsymbols;
+	int streams;
+	streams = 1;
+	nbits = (pktlen << 3) + OFDM_PLCP_BITS;
+	nsymbits = bits_per_symbol[rix % 8][width] * streams;
+	nsymbols = (nbits + nsymbits - 1) / nsymbits;
+	if (!half_gi)
+		duration = SYMBOL_TIME(nsymbols);
+	else {
+		if (!is_gf)
+			duration =
+			    DIV_ROUND_UP(SYMBOL_TIME_HALFGI(nsymbols), 4) << 2;
+		else
+			duration = SYMBOL_TIME_HALFGI(nsymbols);
+	}
+	duration +=
+	    L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams) +
+	    HT_SIGNAL_EXT;
+	if (is_gf)
+		duration -= 12;
+	duration += HT_SIFS_TIME;
+	return duration;
+}
+
+static u32 ssv6xxx_non_ht_txtime(u8 phy, int kbps,
+				 u32 frameLen, bool shortPreamble)
+{
+	u32 bits_per_symbol, num_bits, num_symbols;
+	u32 phy_time, tx_time;
+	if (kbps == 0)
+		return 0;
+	switch (phy) {
+	case WLAN_RC_PHY_CCK:
+		phy_time = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
+		if (shortPreamble)
+			phy_time >>= 1;
+		num_bits = frameLen << 3;
+		tx_time = CCK_SIFS_TIME + phy_time + ((num_bits * 1000) / kbps);
+		break;
+	case WLAN_RC_PHY_OFDM:
+		bits_per_symbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
+		num_bits = OFDM_PLCP_BITS + (frameLen << 3);
+		num_symbols = DIV_ROUND_UP(num_bits, bits_per_symbol);
+		tx_time = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
+		    + (num_symbols * OFDM_SYMBOL_TIME);
+		break;
+	default:
+		pr_err("ssv6051: unknown phy %u\n", phy);
+		BUG_ON(1);
+		tx_time = 0;
+		break;
+	}
+	return tx_time;
+}
+
+static u32 ssv6xxx_set_frame_duration(struct ieee80211_tx_info *info,
+				      struct ssv_rate_info *ssv_rate, u16 len,
+				      struct ssv6200_tx_desc *tx_desc,
+				      struct fw_rc_retry_params *rc_params,
+				      struct ssv_softc *sc)
+{
+	struct ieee80211_tx_rate *tx_drate;
+	u32 frame_time = 0, ack_time = 0, rts_cts_nav = 0, frame_consume_time =
+	    0;
+	u32 l_length = 0, drate_kbps = 0, crate_kbps = 0;
+	bool ctrl_short_preamble = false, is_sgi, is_ht40;
+	bool is_ht, is_gf;
+	int d_phy, c_phy, nRCParams, mcsidx;
+	struct ssv_rate_ctrl *ssv_rc = NULL;
+	tx_drate = &info->control.rates[0];
+	is_sgi = !!(tx_drate->flags & IEEE80211_TX_RC_SHORT_GI);
+	is_ht40 = !!(tx_drate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
+	is_ht = !!(tx_drate->flags & IEEE80211_TX_RC_MCS);
+	is_gf = !!(tx_drate->flags & IEEE80211_TX_RC_GREEN_FIELD);
+	if ((info->control.short_preamble) ||
+	    (tx_drate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
+		ctrl_short_preamble = true;
+	pr_debug("mcs = %d, data rate idx=%d\n", tx_drate->idx, tx_drate[3].count);
+	for (nRCParams = 0; (nRCParams < SSV62XX_TX_MAX_RATES); nRCParams++) {
+		if ((rc_params == NULL) || (sc == NULL)) {
+			mcsidx = tx_drate->idx;
+			drate_kbps = ssv_rate->drate_kbps;
+			crate_kbps = ssv_rate->crate_kbps;
+		} else {
+			if (rc_params[nRCParams].count == 0) {
+				break;
+			}
+			ssv_rc = sc->rc;
+			mcsidx =
+			    (rc_params[nRCParams].drate -
+			     SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES;
+			drate_kbps =
+			    ssv_rc->rc_table[rc_params[nRCParams].drate].
+			    rate_kbps;
+			crate_kbps =
+			    ssv_rc->rc_table[rc_params[nRCParams].crate].
+			    rate_kbps;
+		}
+		if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
+			frame_time = ssv6xxx_ht_txtime(mcsidx,
+						       len, is_ht40, is_sgi,
+						       is_gf);
+			d_phy = 0;
+		} else {
+			if ((info->band == INDEX_80211_BAND_2GHZ) &&
+			    !(ssv_rate->d_flags & IEEE80211_RATE_ERP_G))
+				d_phy = WLAN_RC_PHY_CCK;
+			else
+				d_phy = WLAN_RC_PHY_OFDM;
+			frame_time = ssv6xxx_non_ht_txtime(d_phy, drate_kbps,
+							   len,
+							   ctrl_short_preamble);
+		}
+		if ((info->band == INDEX_80211_BAND_2GHZ) &&
+		    !(ssv_rate->c_flags & IEEE80211_RATE_ERP_G))
+			c_phy = WLAN_RC_PHY_CCK;
+		else
+			c_phy = WLAN_RC_PHY_OFDM;
+		if (tx_desc->unicast) {
+			if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+				ack_time = ssv6xxx_non_ht_txtime(c_phy,
+								 crate_kbps,
+								 BA_LEN,
+								 ctrl_short_preamble);
+			} else {
+				ack_time = ssv6xxx_non_ht_txtime(c_phy,
+								 crate_kbps,
+								 ACK_LEN,
+								 ctrl_short_preamble);
+			}
+		}
+		if (tx_desc->do_rts_cts & IEEE80211_TX_RC_USE_RTS_CTS) {
+			rts_cts_nav = frame_time;
+			rts_cts_nav += ack_time;
+			rts_cts_nav += ssv6xxx_non_ht_txtime(c_phy,
+							     crate_kbps,
+							     CTS_LEN,
+							     ctrl_short_preamble);
+			frame_consume_time = rts_cts_nav;
+			frame_consume_time += ssv6xxx_non_ht_txtime(c_phy,
+								    crate_kbps,
+								    RTS_LEN,
+								    ctrl_short_preamble);
+		} else if (tx_desc->
+			   do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) {
+			rts_cts_nav = frame_time;
+			rts_cts_nav += ack_time;
+			frame_consume_time = rts_cts_nav;
+			frame_consume_time += ssv6xxx_non_ht_txtime(c_phy,
+								    crate_kbps,
+								    CTS_LEN,
+								    ctrl_short_preamble);
+		} else {;
+		}
+		if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
+			l_length = frame_time - HT_SIFS_TIME;
+			l_length = ((l_length - (HT_SIGNAL_EXT + 20)) + 3) >> 2;
+			l_length += ((l_length << 1) - 3);
+		}
+		if ((rc_params == NULL) || (sc == NULL)) {
+			tx_desc->rts_cts_nav = rts_cts_nav;
+			tx_desc->frame_consume_time =
+			    (frame_consume_time >> 5) + 1;;
+			tx_desc->dl_length = l_length;
+			break;
+		} else {
+			rc_params[nRCParams].rts_cts_nav = rts_cts_nav;
+			rc_params[nRCParams].frame_consume_time =
+			    (frame_consume_time >> 5) + 1;
+			rc_params[nRCParams].dl_length = l_length;
+			if (nRCParams == 0) {
+				tx_desc->drate_idx = rc_params[nRCParams].drate;
+				tx_desc->crate_idx = rc_params[nRCParams].crate;
+				tx_desc->rts_cts_nav =
+				    rc_params[nRCParams].rts_cts_nav;
+				tx_desc->frame_consume_time =
+				    rc_params[nRCParams].frame_consume_time;
+				tx_desc->dl_length =
+				    rc_params[nRCParams].dl_length;
+			}
+		}
+	}
+	return ack_time;
+}
+
+static void ssv6200_hw_set_pair_type(struct ssv_hw *sh, u8 type)
+{
+	u32 temp;
+	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
+	temp = (temp & PAIR_SCRT_I_MSK);
+	temp |= (type << PAIR_SCRT_SFT);
+	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
+	dev_dbg(sh->sc->dev, "==>%s: write cipher type %d into hw\n", __func__, type);
+}
+
+static u32 ssv6200_hw_get_pair_type(struct ssv_hw *sh)
+{
+	u32 temp;
+	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
+	temp &= PAIR_SCRT_MSK;
+	temp = (temp >> PAIR_SCRT_SFT);
+	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
+	dev_dbg(sh->sc->dev, "==>%s: read cipher type %d from hw\n", __func__, temp);
+	return temp;
+}
+
+static void ssv6200_hw_set_group_type(struct ssv_hw *sh, u8 type)
+{
+	u32 temp;
+	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
+	temp = temp & GRP_SCRT_I_MSK;
+	temp |= (type << GRP_SCRT_SFT);
+	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
+	dev_dbg(sh->sc->dev, "Set group key type %d\n", type);
+}
+
+void ssv6xxx_reset_sec_module(struct ssv_softc *sc)
+{
+	ssv6200_hw_set_group_type(sc->sh, ME_NONE);
+	ssv6200_hw_set_pair_type(sc->sh, ME_NONE);
+}
+
+static int hw_update_watch_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,
+				struct ssv_sta_info *sta_info, int sta_idx,
+				int rx_hw_sec, int ops)
+{
+	int ret = 0;
+	int retry_cnt = 20;
+	struct sk_buff *skb = NULL;
+	struct cfg_host_cmd *host_cmd;
+	struct ssv6xxx_wsid_params *ptr;
+	dev_dbg(sc->dev, "cmd=%d for fw wsid list, wsid %d \n", ops, sta_idx);
+	skb =
+	    ssv_skb_alloc(HOST_CMD_HDR_LEN +
+			  sizeof(struct ssv6xxx_wsid_params));
+	if (skb == NULL || sta_info == NULL || sc == NULL)
+		return -1;
+	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_wsid_params);
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_WSID_OP;
+	host_cmd->len = skb->data_len;
+	ptr = (struct ssv6xxx_wsid_params *)host_cmd->dat8;
+	ptr->cmd = ops;
+	ptr->hw_security = rx_hw_sec;
+	if ((ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE)
+	    && (ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE)) {
+		ptr->wsid_idx = (u8) (sta_idx - SSV_NUM_HW_STA);
+	} else {
+		ptr->wsid_idx = (u8) (sta_idx);
+	};
+	memcpy(&ptr->target_wsid, &sta->addr[0], 6);
+	while (((sc->sh->hci.hci_ops->hci_send_cmd(skb)) != 0) && (retry_cnt)) {
+		dev_dbg(sc->dev, "WSID cmd=%d retry=%d!!\n", ops, retry_cnt);
+		retry_cnt--;
+	}
+	dev_dbg(sc->dev, "%s: wsid_idx = %u\n", __FUNCTION__, ptr->wsid_idx);
+	ssv_skb_free(skb);
+	if (ops == SSV6XXX_WSID_OPS_ADD)
+		sta_info->hw_wsid = sta_idx;
+	return ret;
+}
+
+static void hw_crypto_key_clear(struct ieee80211_hw *hw, int index,
+				struct ieee80211_key_conf *key,
+				struct ssv_vif_priv_data *vif_priv,
+				struct ssv_sta_priv_data *sta_priv)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_sta_info *sta_info = NULL;
+	if ((index == 0) && (sta_priv == NULL))
+		return;
+	if ((index < 0) || (index >= 4))
+		return;
+	if (index > 0) {
+		if (vif_priv)
+			vif_priv->group_key_idx = 0;
+		if (sta_priv)
+			sta_priv->group_key_idx = 0;
+	}
+	if (sta_priv) {
+		sta_info = &sc->sta_info[sta_priv->sta_idx];
+		if ((index == 0) && (sta_priv->has_hw_decrypt == true)
+		    && (sta_info->hw_wsid >= SSV_NUM_HW_STA)) {
+			hw_update_watch_wsid(sc, sta_info->sta, sta_info,
+					     sta_priv->sta_idx,
+					     SSV6XXX_WSID_SEC_PAIRWISE,
+					     SSV6XXX_WSID_OPS_DISABLE_CAPS);
+		}
+	}
+	if (vif_priv) {
+		if ((index != 0) && !list_empty(&vif_priv->sta_list)) {
+			struct ssv_sta_priv_data *sta_priv_iter;
+			list_for_each_entry(sta_priv_iter, &vif_priv->sta_list,
+					    list) {
+				if (((sta_priv_iter->sta_info->
+				      s_flags & STA_FLAG_VALID) == 0)
+				    || (sta_priv_iter->sta_info->hw_wsid <
+					SSV_NUM_HW_STA))
+					continue;
+				hw_update_watch_wsid(sc,
+						     sta_priv_iter->sta_info->
+						     sta,
+						     sta_priv_iter->sta_info,
+						     sta_priv_iter->sta_idx,
+						     SSV6XXX_WSID_SEC_GROUP,
+						     SSV6XXX_WSID_OPS_DISABLE_CAPS);
+			}
+		}
+	}
+}
+
+static void _set_wep_sw_crypto_key(struct ssv_softc *sc,
+				   struct ssv_vif_info *vif_info,
+				   struct ssv_sta_info *sta_info, void *param)
+{
+	struct ssv_sta_priv_data *sta_priv =
+	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+	sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
+	sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
+	sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
+	sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
+}
+
+static void _set_wep_hw_crypto_pair_key(struct ssv_softc *sc,
+					struct ssv_vif_info *vif_info,
+					struct ssv_sta_info *sta_info,
+					void *param)
+{
+	int wsid = sta_info->hw_wsid;
+	struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param;
+	int address = 0;
+	int *pointer = NULL;
+	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
+	u32 sec_key_tbl = sec_key_tbl_base;
+	int i;
+	u8 *key = sram_key->sta_key[0].pair.key;
+	u32 key_len = *(u16 *) & sram_key->sta_key[0].reserve[0];
+	struct ssv_sta_priv_data *sta_priv =
+	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+	if (wsid == (-1))
+		return;
+	sram_key->sta_key[wsid].pair_key_idx = 0;
+	sram_key->sta_key[wsid].group_key_idx = 0;
+	sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
+	sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
+	sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
+	sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
+	if (wsid != 0)
+		memcpy(sram_key->sta_key[wsid].pair.key, key, key_len);
+	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
+	    + wsid * sizeof(struct ssv6xxx_hw_sta_key);
+	address += (0x10000 * wsid);
+	pointer = (int *)&sram_key->sta_key[wsid];
+	for (i = 0; i < (sizeof(struct ssv6xxx_hw_sta_key) / 4); i++)
+		SMAC_REG_WRITE(sc->sh, address + (i * 4), *(pointer++));
+}
+
+static void _set_wep_hw_crypto_group_key(struct ssv_softc *sc,
+					 struct ssv_vif_info *vif_info,
+					 struct ssv_sta_info *sta_info,
+					 void *param)
+{
+	int wsid = sta_info->hw_wsid;
+	struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param;
+	int address = 0;
+	int *pointer = NULL;
+	u32 key_idx = sram_key->sta_key[0].pair_key_idx;
+	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
+	u32 key_len = *(u16 *) & sram_key->sta_key[0].reserve[0];
+	u8 *key = sram_key->group_key[key_idx - 1].key;
+	u32 sec_key_tbl = sec_key_tbl_base;
+	struct ssv_sta_priv_data *sta_priv =
+	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+	if (wsid == (-1))
+		return;
+	if (wsid != 0) {
+		sram_key->sta_key[wsid].pair_key_idx = key_idx;
+		sram_key->sta_key[wsid].group_key_idx = key_idx;
+		sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
+		sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
+		sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
+		sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
+	}
+	if (wsid != 0)
+		memcpy(sram_key->group_key[key_idx - 1].key, key, key_len);
+	sec_key_tbl += (0x10000 * wsid);
+	address = sec_key_tbl + ((key_idx - 1) * sizeof(struct ssv6xxx_hw_key));
+	pointer = (int *)&sram_key->group_key[key_idx - 1];
+	{
+		int i;
+		for (i = 0; i < (sizeof(struct ssv6xxx_hw_key) / 4); i++)
+			SMAC_REG_WRITE(sc->sh, address + (i * 4), *(pointer++));
+	}
+	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
+	    + (wsid * sizeof(struct ssv6xxx_hw_sta_key));
+	pointer = (int *)&sram_key->sta_key[wsid];
+	SMAC_REG_WRITE(sc->sh, address, *(pointer));
+}
+
+static int hw_crypto_key_write_wep(struct ieee80211_hw *hw,
+				   struct ieee80211_key_conf *key,
+				   u8 algorithm, struct ssv_vif_info *vif_info)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey;
+	if (key->keyidx == 0) {
+		ssv6xxx_foreach_vif_sta(sc, vif_info,
+					_set_wep_hw_crypto_pair_key, sramKey);
+	} else {
+		ssv6xxx_foreach_vif_sta(sc, vif_info,
+					_set_wep_hw_crypto_group_key, sramKey);
+	}
+	return 0;
+}
+
+static void _set_aes_tkip_hw_crypto_group_key(struct ssv_softc *sc,
+					      struct ssv_vif_info *vif_info,
+					      struct ssv_sta_info *sta_info,
+					      void *param)
+{
+	int wsid = sta_info->hw_wsid;
+	int j;
+	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
+	u32 sec_key_tbl = sec_key_tbl_base;
+	int address = 0;
+	int *pointer = 0;
+	struct ssv6xxx_hw_sec *sramKey = &(vif_info->sramKey);
+	int index = *(u8 *) param;
+	if (wsid == (-1))
+		return;
+	BUG_ON(index == 0);
+	sramKey->sta_key[wsid].group_key_idx = index;
+	sec_key_tbl += (0x10000 * wsid);
+	address = sec_key_tbl + ((index - 1) * sizeof(struct ssv6xxx_hw_key));
+	if (vif_info->vif_priv != NULL)
+		dev_dbg(sc->dev, "Write group key %d to VIF %d to %08X\n",
+			index, vif_info->vif_priv->vif_idx, address);
+	else
+		dev_err(sc->dev, "NULL VIF.\n");
+	pointer = (int *)&sramKey->group_key[index - 1];
+	for (j = 0; j < (sizeof(struct ssv6xxx_hw_key) / 4); j++)
+		SMAC_REG_WRITE(sc->sh, address + (j * 4), *(pointer++));
+	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
+	    + (wsid * sizeof(struct ssv6xxx_hw_sta_key));
+	pointer = (int *)&sramKey->sta_key[wsid];
+	SMAC_REG_WRITE(sc->sh, address, *(pointer));
+	if (wsid >= SSV_NUM_HW_STA) {
+		hw_update_watch_wsid(sc, sta_info->sta, sta_info,
+				     wsid, SSV6XXX_WSID_SEC_GROUP,
+				     SSV6XXX_WSID_OPS_ENABLE_CAPS);
+	}
+}
+
+static int _write_pairwise_key_to_hw(struct ssv_softc *sc,
+				     int index, u8 algorithm,
+				     const u8 * key, int key_len,
+				     struct ieee80211_key_conf *keyconf,
+				     struct ssv_vif_priv_data *vif_priv,
+				     struct ssv_sta_priv_data *sta_priv)
+{
+	int i;
+	struct ssv6xxx_hw_sec *sramKey;
+	int address = 0;
+	int *pointer = NULL;
+	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
+	u32 sec_key_tbl;
+	int wsid = (-1);
+	if (sta_priv == NULL) {
+		dev_err(sc->dev, "Set pair-wise key with NULL STA.\n");
+		return -EOPNOTSUPP;
+	}
+	wsid = sta_priv->sta_info->hw_wsid;
+	if ((wsid < 0) || (wsid >= SSV_NUM_STA)) {
+		dev_err(sc->dev, "Set pair-wise key to invalid WSID %d.\n",
+			wsid);
+		return -EOPNOTSUPP;
+	}
+	dev_dbg(sc->dev, "Set STA %d's pair-wise key of %d bytes.\n", wsid,
+		key_len);
+	sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
+	sramKey->sta_key[wsid].pair_key_idx = 0;
+	sramKey->sta_key[wsid].group_key_idx = vif_priv->group_key_idx;
+	memcpy(sramKey->sta_key[wsid].pair.key, key, key_len);
+	sec_key_tbl = sec_key_tbl_base;
+	sec_key_tbl += (0x10000 * wsid);
+	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
+	    + wsid * sizeof(struct ssv6xxx_hw_sta_key);
+	pointer = (int *)&sramKey->sta_key[wsid];
+	for (i = 0; i < (sizeof(struct ssv6xxx_hw_sta_key) / 4); i++)
+		SMAC_REG_WRITE(sc->sh, (address + (i * 4)), *(pointer++));
+	if (wsid >= SSV_NUM_HW_STA) {
+		hw_update_watch_wsid(sc, sta_priv->sta_info->sta,
+				     sta_priv->sta_info, sta_priv->sta_idx,
+				     SSV6XXX_WSID_SEC_PAIRWISE,
+				     SSV6XXX_WSID_OPS_ENABLE_CAPS);
+	}
+	return 0;
+}
+
+static int _write_group_key_to_hw(struct ssv_softc *sc,
+				  int index, u8 algorithm,
+				  const u8 * key, int key_len,
+				  struct ieee80211_key_conf *keyconf,
+				  struct ssv_vif_priv_data *vif_priv,
+				  struct ssv_sta_priv_data *sta_priv)
+{
+	struct ssv6xxx_hw_sec *sramKey;
+	int wsid = sta_priv ? sta_priv->sta_info->hw_wsid : (-1);
+	int ret = 0;
+	if (vif_priv == NULL) {
+		dev_err(sc->dev, "Setting group key to NULL VIF\n");
+		return -EOPNOTSUPP;
+	}
+	dev_dbg(sc->dev,
+		"Setting VIF %d group key %d of length %d to WSID %d.\n",
+		vif_priv->vif_idx, index, key_len, wsid);
+	sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
+	vif_priv->group_key_idx = index;
+	if (sta_priv)
+		sta_priv->group_key_idx = index;
+	memcpy(sramKey->group_key[index - 1].key, key, key_len);
+	WARN_ON(sc->vif_info[vif_priv->vif_idx].vif_priv == NULL);
+	ssv6xxx_foreach_vif_sta(sc, &sc->vif_info[vif_priv->vif_idx],
+				_set_aes_tkip_hw_crypto_group_key, &index);
+	ret = 0;
+	return ret;
+}
+
+static enum SSV_CIPHER_E _prepare_key(struct ieee80211_key_conf *key)
+{
+	enum SSV_CIPHER_E cipher;
+	switch (key->cipher) {
+	case WLAN_CIPHER_SUITE_WEP40:
+		cipher = SSV_CIPHER_WEP40;
+		break;
+	case WLAN_CIPHER_SUITE_WEP104:
+		cipher = SSV_CIPHER_WEP104;
+		break;
+	case WLAN_CIPHER_SUITE_TKIP:
+		key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
+		cipher = SSV_CIPHER_TKIP;
+		break;
+	case WLAN_CIPHER_SUITE_CCMP:
+		key->flags |=
+		    (IEEE80211_KEY_FLAG_SW_MGMT_TX |
+		     IEEE80211_KEY_FLAG_RX_MGMT);
+		cipher = SSV_CIPHER_CCMP;
+		break;
+	default:
+		cipher = SSV_CIPHER_INVALID;
+		break;
+	}
+	return cipher;
+}
+int _set_key_wep(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+		 struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher,
+		 struct ieee80211_key_conf *key)
+{
+	int ret = 0;
+	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+	struct ssv6xxx_hw_sec *sram_key = &vif_info->sramKey;
+	sram_key->sta_key[0].pair_key_idx = key->keyidx;
+	sram_key->sta_key[0].group_key_idx = key->keyidx;
+	*(u16 *) & sram_key->sta_key[0].reserve[0] = key->keylen;
+	dev_dbg(sc->dev, "Set WEP %02X %02X %02X %02X %02X %02X %02X %02X... (%d %d)\n",
+	       key->key[0], key->key[1], key->key[2], key->key[3], key->key[4],
+	       key->key[5], key->key[6], key->key[7], key->keyidx, key->keylen);
+	if (key->keyidx == 0) {
+		memcpy(sram_key->sta_key[0].pair.key, key->key, key->keylen);
+	} else {
+		memcpy(sram_key->group_key[key->keyidx - 1].key, key->key,
+		       key->keylen);
+	}
+	if (sc->sh->cfg.use_wpa2_only) {
+		dev_warn(sc->dev, "WEP: use WPA2 HW security mode only.\n");
+	}
+	if ((sc->sh->cfg.use_wpa2_only == 0)
+	    && vif_priv->vif_idx == 0) {
+		vif_priv->has_hw_decrypt = true;
+		vif_priv->has_hw_encrypt = true;
+		vif_priv->need_sw_decrypt = false;
+		vif_priv->need_sw_encrypt = false;
+		vif_priv->use_mac80211_decrypt = false;
+		ssv6200_hw_set_pair_type(sc->sh, cipher);
+		ssv6200_hw_set_group_type(sc->sh, cipher);
+		hw_crypto_key_write_wep(sc->hw, key, cipher,
+					&sc->vif_info[vif_priv->vif_idx]);
+	} else {
+		vif_priv->has_hw_decrypt = false;
+		vif_priv->has_hw_encrypt = false;
+		vif_priv->need_sw_decrypt = false;
+		vif_priv->need_sw_encrypt = false;
+		vif_priv->use_mac80211_decrypt = true;
+		ssv6xxx_foreach_vif_sta(sc, vif_info, _set_wep_sw_crypto_key,
+					NULL);
+		ret = -EOPNOTSUPP;
+	}
+	vif_priv->pair_cipher = vif_priv->group_cipher = cipher;
+	vif_priv->is_security_valid = true;
+	return ret;
+}
+
+static int _set_pairwise_key_tkip_ccmp(struct ssv_softc *sc,
+				       struct ssv_vif_priv_data *vif_priv,
+				       struct ssv_sta_priv_data *sta_priv,
+				       enum SSV_CIPHER_E cipher,
+				       struct ieee80211_key_conf *key)
+{
+	int ret = 0;
+	const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP";
+	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+	bool tdls_link = false, tdls_use_sw_cipher = false, tkip_use_sw_cipher =
+	    false;
+	bool use_non_ccmp = false;
+	int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
+	struct ssv_vif_priv_data *another_vif_priv =
+	    (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].vif_priv;
+	if (sta_priv == NULL) {
+		dev_err(sc->dev,
+			"Setting pairwise TKIP/CCMP key to NULL STA.\n");
+		return -EOPNOTSUPP;
+	}
+	if (sc->sh->cfg.use_wpa2_only) {
+		dev_warn(sc->dev, "Pairwise TKIP/CCMP: use WPA2 HW security mode only.\n");
+	}
+	if (vif_info->if_type == NL80211_IFTYPE_STATION) {
+		struct ssv_sta_priv_data *first_sta_priv =
+		    list_first_entry(&vif_priv->sta_list,
+				     struct ssv_sta_priv_data, list);
+		if (first_sta_priv->sta_idx != sta_priv->sta_idx) {
+			tdls_link = true;
+		}
+		dev_dbg(sc->dev, "first sta idx %d, current sta idx %d\n",
+		       first_sta_priv->sta_idx, sta_priv->sta_idx);
+	}
+	if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)
+	    && (sc->sh->cfg.use_wpa2_only == false)) {
+		tdls_use_sw_cipher = true;
+	}
+	if (another_vif_priv != NULL) {
+		if ((another_vif_priv->pair_cipher != SSV_CIPHER_CCMP)
+		    && (another_vif_priv->pair_cipher != SSV_CIPHER_NONE)) {
+			use_non_ccmp = true;
+			dev_dbg(sc->dev, "another vif use none ccmp\n");
+		}
+	}
+	if ((((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP))
+	     || (use_non_ccmp))
+	    && (sc->sh->cfg.use_wpa2_only == 1) && (cipher == SSV_CIPHER_CCMP)) {
+		u32 val;
+		SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val);
+		if (((val >> 4) & 0xF) != M_ENG_CPU) {
+			SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+				       ((val & 0xf) | (M_ENG_CPU << 4)
+					| (val & 0xfffffff0) << 4));
+			dev_dbg(sc->dev,
+				"orginal Rx_Flow %x , modified flow %x \n", val,
+				((val & 0xf) | (M_ENG_CPU << 4) |
+				 (val & 0xfffffff0) << 4));
+		}
+	}
+	if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) {
+		tkip_use_sw_cipher = true;
+	}
+	if (tkip_use_sw_cipher == true)
+		dev_info(sc->dev, "Using software TKIP cipher\n");
+	if ((((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false)
+	      && (tkip_use_sw_cipher == false)))
+	    || ((cipher == SSV_CIPHER_CCMP)
+		&& (sc->sh->cfg.use_wpa2_only == 1))) {
+		sta_priv->has_hw_decrypt = true;
+		sta_priv->need_sw_decrypt = false;
+		if ((cipher == SSV_CIPHER_TKIP)
+		    || ((!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX) ||
+			 (sta_priv->sta_info->sta->ht_cap.ht_supported ==
+			  false))
+			&& (vif_priv->force_sw_encrypt == false))) {
+			dev_dbg(sc->dev,
+				"STA %d uses HW encrypter for pairwise.\n",
+				sta_priv->sta_idx);
+			sta_priv->has_hw_encrypt = true;
+			sta_priv->need_sw_encrypt = false;
+			sta_priv->use_mac80211_decrypt = false;
+			ret = 0;
+		} else {
+			sta_priv->has_hw_encrypt = false;
+			sta_priv->need_sw_encrypt = false;
+			sta_priv->use_mac80211_decrypt = true;
+			ret = -EOPNOTSUPP;
+		}
+	} else {
+		sta_priv->has_hw_encrypt = false;
+		sta_priv->has_hw_decrypt = false;
+		dev_err(sc->dev, "STA %d MAC80211's %s cipher.\n",
+			sta_priv->sta_idx, cipher_name);
+		sta_priv->need_sw_encrypt = false;
+		sta_priv->need_sw_decrypt = false;
+		sta_priv->use_mac80211_decrypt = true;
+		ret = -EOPNOTSUPP;
+	}
+	if (sta_priv->has_hw_encrypt || sta_priv->has_hw_decrypt) {
+		ssv6200_hw_set_pair_type(sc->sh, cipher);
+		_write_pairwise_key_to_hw(sc, key->keyidx, cipher,
+					  key->key, key->keylen, key,
+					  vif_priv, sta_priv);
+	}
+	if ((vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt)
+	    && (vif_priv->group_key_idx > 0)) {
+		_set_aes_tkip_hw_crypto_group_key(sc,
+						  &sc->vif_info[vif_priv->
+								vif_idx],
+						  sta_priv->sta_info,
+						  &vif_priv->group_key_idx);
+	}
+	return ret;
+}
+
+static int _set_group_key_tkip_ccmp(struct ssv_softc *sc,
+				    struct ssv_vif_priv_data *vif_priv,
+				    struct ssv_sta_priv_data *sta_priv,
+				    enum SSV_CIPHER_E cipher,
+				    struct ieee80211_key_conf *key)
+{
+	int ret = 0;
+	const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP";
+	bool tkip_use_sw_cipher = false;
+	vif_priv->group_cipher = cipher;
+	if (sc->sh->cfg.use_wpa2_only) {
+		dev_warn(sc->dev, "Group TKIP/CCMP: use WPA2 HW security mode only.\n");
+	}
+	if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) {
+		tkip_use_sw_cipher = true;
+	}
+	if (((vif_priv->vif_idx == 0) && (tkip_use_sw_cipher == false))
+	    || ((cipher == SSV_CIPHER_CCMP)
+		&& (sc->sh->cfg.use_wpa2_only == 1))) {
+		dev_dbg(sc->dev, "VIF %d uses HW %s cipher for group.\n",
+			vif_priv->vif_idx, cipher_name);
+#ifdef USE_MAC80211_DECRYPT_BROADCAST
+		vif_priv->has_hw_decrypt = false;
+		ret = -EOPNOTSUPP;
+#else
+		vif_priv->has_hw_decrypt = true;
+#endif
+		vif_priv->has_hw_encrypt = true;
+		vif_priv->need_sw_decrypt = false;
+		vif_priv->need_sw_encrypt = false;
+		vif_priv->use_mac80211_decrypt = false;
+	} else {
+		vif_priv->has_hw_decrypt = false;
+		vif_priv->has_hw_encrypt = false;
+		dev_err(sc->dev, "VIF %d uses MAC80211's %s cipher.\n",
+			vif_priv->vif_idx, cipher_name);
+		vif_priv->need_sw_encrypt = false;
+		vif_priv->need_sw_encrypt = false;
+		vif_priv->use_mac80211_decrypt = true;
+		ret = -EOPNOTSUPP;
+	}
+	if (vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt) {
+#ifdef USE_MAC80211_DECRYPT_BROADCAST
+		ssv6200_hw_set_group_type(sc->sh, ME_NONE);
+#else
+		ssv6200_hw_set_group_type(sc->sh, cipher);
+#endif
+		key->hw_key_idx = key->keyidx;
+		_write_group_key_to_hw(sc, key->keyidx, cipher,
+				       key->key, key->keylen, key,
+				       vif_priv, sta_priv);
+	}
+	vif_priv->is_security_valid = true;
+	{
+		int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
+		struct ssv_vif_priv_data *another_vif_priv =
+		    (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].
+		    vif_priv;
+		if (another_vif_priv != NULL) {
+			if (((SSV6XXX_USE_SW_DECRYPT(vif_priv)
+			      && SSV6XXX_USE_HW_DECRYPT(another_vif_priv)))
+			    || ((SSV6XXX_USE_HW_DECRYPT(vif_priv)
+				 &&
+				 (SSV6XXX_USE_SW_DECRYPT(another_vif_priv))))) {
+				u32 val;
+				SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val);
+				if (((val >> 4) & 0xF) != M_ENG_CPU) {
+					SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+						       ((val & 0xf) |
+							(M_ENG_CPU << 4)
+							| (val & 0xfffffff0) <<
+							4));
+					dev_dbg(sc->dev,
+						"orginal Rx_Flow %x , modified flow %x \n",
+						val,
+						((val & 0xf) | (M_ENG_CPU << 4)
+						 | (val & 0xfffffff0) << 4));
+				} else {
+					dev_dbg(sc->dev, " doesn't need to change rx flow\n");
+				}
+			}
+		}
+	}
+	return ret;
+}
+
+static int _set_key_tkip_ccmp(struct ssv_softc *sc,
+			      struct ssv_vif_priv_data *vif_priv,
+			      struct ssv_sta_priv_data *sta_priv,
+			      enum SSV_CIPHER_E cipher,
+			      struct ieee80211_key_conf *key)
+{
+	if (key->keyidx == 0)
+		return _set_pairwise_key_tkip_ccmp(sc, vif_priv, sta_priv,
+						   cipher, key);
+	else
+		return _set_group_key_tkip_ccmp(sc, vif_priv, sta_priv, cipher,
+						key);
+}
+
+static int ssv6200_set_key(struct ieee80211_hw *hw,
+			   enum set_key_cmd cmd,
+			   struct ieee80211_vif *vif,
+			   struct ieee80211_sta *sta,
+			   struct ieee80211_key_conf *key)
+{
+	struct ssv_softc *sc = hw->priv;
+	int ret = 0;
+	enum SSV_CIPHER_E cipher = SSV_CIPHER_NONE;
+	int sta_idx = (-1);
+	struct ssv_sta_info *sta_info = NULL;
+	struct ssv_sta_priv_data *sta_priv = NULL;
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+	if (sta) {
+		sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+		sta_idx = sta_priv->sta_idx;
+		sta_info = sta_priv->sta_info;
+	}
+	BUG_ON((cmd != SET_KEY) && (cmd != DISABLE_KEY));
+	if (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_SECURITY)) {
+		dev_warn(sc->dev, "HW does not support security.\n");
+		return -EOPNOTSUPP;
+	}
+	if (sta_info && (sta_info->hw_wsid == (-1))) {
+		dev_warn(sc->dev,
+			 "Add STA without HW resource. Use MAC80211's solution.\n");
+		return -EOPNOTSUPP;
+	}
+	cipher = _prepare_key(key);
+	dev_dbg(sc->dev,
+		"Set key VIF %d VIF type %d STA %d algorithm = %d, key->keyidx = %d, cmd = %d\n",
+		vif_priv->vif_idx, vif->type, sta_idx, cipher, key->keyidx,
+		cmd);
+	if (cipher == SSV_CIPHER_INVALID) {
+		dev_warn(sc->dev, "Unsupported cipher type.\n");
+		return -EOPNOTSUPP;
+	}
+	mutex_lock(&sc->mutex);
+	switch (cmd) {
+	case SET_KEY:
+		{
+			switch (cipher) {
+			case SSV_CIPHER_WEP40:
+			case SSV_CIPHER_WEP104:
+				ret =
+				    _set_key_wep(sc, vif_priv, sta_priv, cipher,
+						 key);
+				break;
+			case SSV_CIPHER_TKIP:
+			case SSV_CIPHER_CCMP:
+				ret =
+				    _set_key_tkip_ccmp(sc, vif_priv, sta_priv,
+						       cipher, key);
+				break;
+			default:
+				break;
+			}
+			if (sta) {
+				struct ssv_sta_priv_data *first_sta_priv =
+				    list_first_entry(&vif_priv->sta_list,
+						     struct ssv_sta_priv_data,
+						     list);
+				if (first_sta_priv->sta_idx ==
+				    sta_priv->sta_idx) {
+					vif_priv->pair_cipher = cipher;
+				}
+				if (SSV6200_USE_HW_WSID(sta_idx)) {
+					if (SSV6XXX_USE_SW_DECRYPT(sta_priv)) {
+						u32 cipher_setting;
+						cipher_setting =
+						    ssv6200_hw_get_pair_type
+						    (sc->sh);
+						if (cipher_setting != ME_NONE) {
+							u32 val;
+							SMAC_REG_READ(sc->sh,
+								      ADR_RX_FLOW_DATA,
+								      &val);
+							if (((val >> 4) & 0xF)
+							    != M_ENG_CPU) {
+								SMAC_REG_WRITE
+								    (sc->sh,
+								     ADR_RX_FLOW_DATA,
+								     ((val &
+								       0xf) |
+								      (M_ENG_CPU
+								       << 4)
+								      | (val &
+									 0xfffffff0)
+								      << 4));
+								dev_dbg(sc->dev,
+									"orginal Rx_Flow %x , modified flow %x \n",
+									val,
+									((val &
+									  0xf) |
+									 (M_ENG_CPU
+									  << 4)
+									 | (val
+									    &
+									    0xfffffff0)
+									 << 4));
+							} else {
+								dev_dbg(sc->dev, " doesn't need to change rx flow\n");
+							}
+						}
+					}
+					if (sta_priv->has_hw_decrypt) {
+						hw_update_watch_wsid(sc, sta,
+								     sta_info,
+								     sta_idx,
+								     SSV6XXX_WSID_SEC_HW,
+								     SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE);
+						dev_info(sc->dev, "set hw wsid %d cipher mode to HW cipher for pairwise key\n", sta_idx);
+					}
+				}
+			} else {
+				if (vif_info->if_type == NL80211_IFTYPE_STATION) {
+					struct ssv_sta_priv_data *first_sta_priv
+					    =
+					    list_first_entry(&vif_priv->
+							     sta_list,
+							     struct
+							     ssv_sta_priv_data,
+							     list);
+					if (SSV6200_USE_HW_WSID
+					    (first_sta_priv->sta_idx)) {
+						if (vif_priv->has_hw_decrypt) {
+							hw_update_watch_wsid(sc,
+									     sta,
+									     sta_info,
+									     first_sta_priv->
+									     sta_idx,
+									     SSV6XXX_WSID_SEC_HW,
+									     SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE);
+							dev_info(sc->dev, "set hw wsid %d cipher mode to HW cipher for group key\n", first_sta_priv->sta_idx);
+						}
+					}
+				}
+			}
+		}
+		break;
+	case DISABLE_KEY:
+		{
+			int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
+			struct ssv_vif_priv_data *another_vif_priv =
+			    (struct ssv_vif_priv_data *)sc->
+			    vif_info[another_vif_idx].vif_priv;
+			if (another_vif_priv != NULL) {
+				struct ssv_vif_info *vif_info =
+				    &sc->vif_info[vif_priv->vif_idx];
+				if (vif_info->if_type != NL80211_IFTYPE_AP) {
+					if ((SSV6XXX_USE_SW_DECRYPT(vif_priv)
+					     &&
+					     SSV6XXX_USE_HW_DECRYPT
+					     (another_vif_priv))
+					    ||
+					    (SSV6XXX_USE_SW_DECRYPT
+					     (another_vif_priv)
+					     &&
+					     SSV6XXX_USE_HW_DECRYPT(vif_priv)))
+					{
+						SMAC_REG_WRITE(sc->sh,
+							       ADR_RX_FLOW_DATA,
+							       M_ENG_MACRX |
+							       (M_ENG_ENCRYPT_SEC
+								<< 4) |
+							       (M_ENG_HWHCI <<
+								8));
+						dev_dbg(sc->dev, "redirect Rx flow for disconnect\n");
+					}
+				} else {
+					if (sta == NULL) {
+						if (SSV6XXX_USE_SW_DECRYPT
+						    (another_vif_priv)
+						    &&
+						    SSV6XXX_USE_HW_DECRYPT
+						    (vif_priv)) {
+							SMAC_REG_WRITE(sc->sh,
+								       ADR_RX_FLOW_DATA,
+								       M_ENG_MACRX
+								       |
+								       (M_ENG_ENCRYPT_SEC
+									<< 4) |
+								       (M_ENG_HWHCI
+									<< 8));
+							dev_dbg(sc->dev, "redirect Rx flow for disconnect\n");
+						}
+					}
+				}
+			}
+			if (sta == NULL) {
+				vif_priv->group_cipher = ME_NONE;
+				if ((another_vif_priv == NULL)
+				    || ((another_vif_priv != NULL)
+					&&
+					(!SSV6XXX_USE_HW_DECRYPT
+					 (another_vif_priv)))) {
+					ssv6200_hw_set_group_type(sc->sh,
+								  ME_NONE);
+				}
+			} else {
+				struct ssv_vif_info *vif_info =
+				    &sc->vif_info[vif_priv->vif_idx];
+				if ((vif_info->if_type != NL80211_IFTYPE_AP)
+				    && (another_vif_priv == NULL)) {
+					struct ssv_sta_priv_data *first_sta_priv
+					    =
+					    list_first_entry(&vif_priv->
+							     sta_list,
+							     struct
+							     ssv_sta_priv_data,
+							     list);
+					if (sta_priv == first_sta_priv) {
+						ssv6200_hw_set_pair_type(sc->sh,
+									 ME_NONE);
+					}
+				}
+				vif_priv->pair_cipher = ME_NONE;
+			}
+			if ((cipher == ME_TKIP) || (cipher == ME_CCMP)) {
+				dev_dbg(sc->dev, "Clear key %d VIF %d, STA %d\n",
+				       key->keyidx, (vif != NULL),
+				       (sta != NULL));
+				hw_crypto_key_clear(hw, key->keyidx, key,
+						    vif_priv, sta_priv);
+			}
+			{
+				if ((key->keyidx == 0) && (sta_priv != NULL)) {
+					sta_priv->has_hw_decrypt = false;
+					sta_priv->has_hw_encrypt = false;
+					sta_priv->need_sw_encrypt = false;
+					sta_priv->use_mac80211_decrypt = false;
+				}
+				if ((vif_priv->is_security_valid)
+				    && (key->keyidx != 0)) {
+					vif_priv->is_security_valid = false;
+				}
+			}
+			ret = 0;
+		}
+		break;
+	default:
+		ret = -EINVAL;
+	}
+	mutex_unlock(&sc->mutex);
+	if (sta_priv != NULL) {
+		dev_info(sc->dev, "station mode: hardware encrypt:%d/decrypt:%d, software encrypt:%d/decrypt:%d\n",
+		       (sta_priv->has_hw_encrypt == true),
+		       (sta_priv->has_hw_decrypt == true),
+		       (sta_priv->need_sw_encrypt == true),
+		       (sta_priv->need_sw_decrypt == true));
+	}
+	if (vif_priv) {
+		dev_info
+		    (sc->dev, "vif mode: hardware encrypt:%d/decrypt:%d, software encrypt:%d/decrypt:%d, mac80211 decrypt: %d, valid:%d\n",
+		     (vif_priv->has_hw_encrypt == true),
+		     (vif_priv->has_hw_decrypt == true),
+		     (vif_priv->need_sw_encrypt == true),
+		     (vif_priv->need_sw_decrypt == true),
+		     (vif_priv->use_mac80211_decrypt == true),
+		     (vif_priv->is_security_valid == true));
+	}
+	if (vif_priv->force_sw_encrypt
+	    || (sta_info && (sta_info->hw_wsid != 1)
+		&& (sta_info->hw_wsid != 0))) {
+		if (vif_priv->force_sw_encrypt == false)
+			vif_priv->force_sw_encrypt = true;
+		ret = -EOPNOTSUPP;
+	}
+	dev_dbg(sc->dev, "SET KEY %d\n", ret);
+	return ret;
+}
+
+u32 _process_tx_done(struct ssv_softc *sc)
+{
+	struct ieee80211_tx_info *tx_info;
+	struct sk_buff *skb;
+	while ((skb = skb_dequeue(&sc->tx_done_q))) {
+		struct ssv6200_tx_desc *tx_desc;
+		tx_info = IEEE80211_SKB_CB(skb);
+		tx_desc = (struct ssv6200_tx_desc *)skb->data;
+		if (tx_desc->c_type > M2_TXREQ) {
+			ssv_skb_free(skb);
+			dev_dbg(sc->dev, "free cmd skb!\n");
+			continue;
+		}
+		if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
+			ssv6200_ampdu_release_skb(skb, sc->hw);
+			continue;
+		}
+		skb_pull(skb, SSV6XXX_TX_DESC_LEN);
+		ieee80211_tx_info_clear_status(tx_info);
+		tx_info->flags |= IEEE80211_TX_STAT_ACK;
+		tx_info->status.ack_signal = 100;
+#ifdef REPORT_TX_DONE_IN_IRQ
+		ieee80211_tx_status_irqsafe(sc->hw, skb);
+#else
+		ieee80211_tx_status(sc->hw, skb);
+		if (skb_queue_len(&sc->rx_skb_q))
+			break;
+#endif
+	}
+	return skb_queue_len(&sc->tx_done_q);
+}
+
+#ifdef REPORT_TX_DONE_IN_IRQ
+void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)args;
+	_process_tx_done *(sc);
+}
+#else
+void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)args;
+	struct sk_buff *skb;
+	while ((skb = skb_dequeue(skb_head))) {
+		struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+		struct ssv6200_tx_desc *tx_desc;
+		tx_desc = (struct ssv6200_tx_desc *)skb->data;
+		if (tx_desc->c_type > M2_TXREQ) {
+			ssv_skb_free(skb);
+			dev_dbg(sc->dev, "free cmd skb!\n");
+			continue;
+		}
+		if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
+			ssv6xxx_ampdu_sent(sc->hw, skb);
+		skb_queue_tail(&sc->tx_done_q, skb);
+	}
+	wake_up_interruptible(&sc->rx_wait_q);
+}
+#endif
+void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args)
+{
+	struct ieee80211_hdr *hdr;
+	struct ssv_softc *sc = args;
+	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+	struct ssv6200_tx_desc *tx_desc;
+	struct ssv_rate_info ssv_rate;
+	u32 nav = 0;
+	int ret = 0;
+	tx_desc = (struct ssv6200_tx_desc *)skb->data;
+	if (tx_desc->c_type > M2_TXREQ)
+		return;
+	if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) {
+		hdr = (struct ieee80211_hdr *)(skb->data + SSV6XXX_TX_DESC_LEN);
+		if ((ieee80211_is_data_qos(hdr->frame_control)
+		     || ieee80211_is_data(hdr->frame_control))
+		    && (tx_desc->wsid < SSV_RC_MAX_HARDWARE_SUPPORT)) {
+			ret =
+			    ssv6xxx_rc_hw_rate_update_check(skb, sc,
+							    tx_desc->
+							    do_rts_cts);
+			if (ret & RC_FIRMWARE_REPORT_FLAG) {
+				{
+					tx_desc->RSVD_0 = SSV6XXX_RC_REPORT;
+					tx_desc->tx_report = 1;
+				}
+				ret &= 0xf;
+			}
+			if (ret) {
+				ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
+				tx_desc->crate_idx = ssv_rate.crate_hw_idx;
+				tx_desc->drate_idx = ssv_rate.drate_hw_idx;
+				nav =
+				    ssv6xxx_set_frame_duration(info, &ssv_rate,
+							       skb->len +
+							       FCS_LEN, tx_desc,
+							       NULL, NULL);
+				if (tx_desc->tx_burst == 0) {
+					if (tx_desc->ack_policy != 0x01)
+						hdr->duration_id = nav;
+				}
+			}
+		}
+	} else {
+	}
+	return;
+}
+
+void ssv6xxx_update_txinfo(struct ssv_softc *sc, struct sk_buff *skb)
+{
+	struct ieee80211_hdr *hdr;
+	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+	struct ieee80211_sta *sta;
+	struct ssv_sta_info *sta_info = NULL;
+	struct ssv_sta_priv_data *ssv_sta_priv = NULL;
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
+	struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *)skb->data;
+	struct ieee80211_tx_rate *tx_drate;
+	struct ssv_rate_info ssv_rate;
+	int ac, hw_txqid;
+	u32 nav = 0;
+	if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+		struct ampdu_hdr_st *ampdu_hdr =
+		    (struct ampdu_hdr_st *)skb->head;
+		sta = ampdu_hdr->ampdu_tid->sta;
+		hdr =
+		    (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET +
+					     AMPDU_DELIMITER_LEN);
+	} else {
+		struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+		sta = skb_info->sta;
+		hdr = (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET);
+	}
+	if (sta) {
+		ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+		sta_info = ssv_sta_priv->sta_info;
+	}
+	if ((!sc->bq4_dtim) &&
+	    (ieee80211_is_mgmt(hdr->frame_control) ||
+	     ieee80211_is_nullfunc(hdr->frame_control) ||
+	     ieee80211_is_qos_nullfunc(hdr->frame_control))) {
+		ac = 4;
+		hw_txqid = 4;
+	} else if ((sc->bq4_dtim) &&
+		   info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
+		hw_txqid = 4;
+		ac = 4;
+	} else {
+		ac = skb_get_queue_mapping(skb);
+		hw_txqid = sc->tx.hw_txqid[ac];
+	}
+	tx_drate = &info->control.rates[0];
+	ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
+	tx_desc->len = skb->len;
+	tx_desc->c_type = M2_TXREQ;
+	tx_desc->f80211 = 1;
+	tx_desc->qos = (ieee80211_is_data_qos(hdr->frame_control)) ? 1 : 0;
+	if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
+		if (ieee80211_is_mgmt(hdr->frame_control) &&
+		    ieee80211_has_order(hdr->frame_control))
+			tx_desc->ht = 1;
+	}
+	tx_desc->use_4addr = (ieee80211_has_a4(hdr->frame_control)) ? 1 : 0;
+	tx_desc->more_data =
+	    (ieee80211_has_morefrags(hdr->frame_control)) ? 1 : 0;
+	tx_desc->stype_b5b4 = (cpu_to_le16(hdr->frame_control) >> 4) & 0x3;
+	tx_desc->frag = (tx_desc->more_data || (hdr->seq_ctrl & 0xf)) ? 1 : 0;
+	tx_desc->unicast = (is_multicast_ether_addr(hdr->addr1)) ? 0 : 1;
+	tx_desc->tx_burst = (tx_desc->frag) ? 1 : 0;
+	tx_desc->wsid = (!sta_info
+			 || (sta_info->hw_wsid < 0)) ? 0x0F : sta_info->hw_wsid;
+	tx_desc->txq_idx = hw_txqid;
+	tx_desc->hdr_offset = TXPB_OFFSET;
+	tx_desc->hdr_len = ssv6xxx_frame_hdrlen(hdr, tx_desc->ht);
+	tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len;
+	if (info->control.use_rts)
+		tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS;
+	else if (info->control.use_cts_prot)
+		tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_CTS_PROTECT;
+	if (tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT)
+		tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS;
+	if (tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT) {
+		tx_desc->crate_idx = 0;
+	} else
+		tx_desc->crate_idx = ssv_rate.crate_hw_idx;
+	tx_desc->drate_idx = ssv_rate.drate_hw_idx;
+	if (tx_desc->unicast == 0)
+		tx_desc->ack_policy = 1;
+	else if (tx_desc->qos == 1)
+		tx_desc->ack_policy = (*ieee80211_get_qos_ctl(hdr) & 0x60) >> 5;
+	else if (ieee80211_is_ctl(hdr->frame_control))
+		tx_desc->ack_policy = 1;
+	tx_desc->security = 0;
+	tx_desc->fCmdIdx = 0;
+	tx_desc->fCmd = (hw_txqid + M_ENG_TX_EDCA0);
+	if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+#ifdef AMPDU_HAS_LEADING_FRAME
+		tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_CPU;
+#else
+		tx_desc->RSVD_1 = 1;
+#endif
+		tx_desc->aggregation = 1;
+		tx_desc->ack_policy = 0x01;
+		if ((tx_desc->do_rts_cts == 0)
+		    && ((sc->hw->wiphy->rts_threshold == (-1))
+			|| ((skb->len - sc->sh->tx_desc_len) >
+			    sc->hw->wiphy->rts_threshold))) {
+			tx_drate->flags |= IEEE80211_TX_RC_USE_RTS_CTS;
+			tx_desc->do_rts_cts = 1;
+		}
+	}
+	if (ieee80211_has_protected(hdr->frame_control)
+	    && (ieee80211_is_data_qos(hdr->frame_control)
+		|| ieee80211_is_data(hdr->frame_control))) {
+		if ((tx_desc->unicast && ssv_sta_priv
+		     && ssv_sta_priv->has_hw_encrypt)
+		    || (!tx_desc->unicast && vif_priv
+			&& vif_priv->has_hw_encrypt)) {
+			if (!tx_desc->unicast
+			    && !list_empty(&vif_priv->sta_list)) {
+				struct ssv_sta_priv_data *one_sta_priv;
+				int hw_wsid;
+				one_sta_priv =
+				    list_first_entry(&vif_priv->sta_list,
+						     struct ssv_sta_priv_data,
+						     list);
+				hw_wsid = one_sta_priv->sta_info->hw_wsid;
+				if (hw_wsid != (-1)) {
+					tx_desc->wsid = hw_wsid;
+				}
+			}
+			tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_ENCRYPT;
+		} else if (ssv_sta_priv->need_sw_encrypt) {
+		} else {
+		}
+	} else {
+	}
+	tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_HWHCI;
+	if (tx_desc->aggregation == 1) {
+		struct ampdu_hdr_st *ampdu_hdr =
+		    (struct ampdu_hdr_st *)skb->head;
+		memcpy(&tx_desc->rc_params[0], ampdu_hdr->rates,
+		       sizeof(tx_desc->rc_params));
+		nav =
+		    ssv6xxx_set_frame_duration(info, &ssv_rate,
+					       (skb->len + FCS_LEN), tx_desc,
+					       &tx_desc->rc_params[0], sc);
+#ifdef FW_RC_RETRY_DEBUG
+		{
+			dev_dbg
+			    (sc->dev, "[FW_RC]:param[0]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
+			     tx_desc->rc_params[0].drate,
+			     tx_desc->rc_params[0].count,
+			     tx_desc->rc_params[0].crate,
+			     tx_desc->rc_params[0].dl_length,
+			     tx_desc->rc_params[0].frame_consume_time,
+			     tx_desc->rc_params[0].rts_cts_nav);
+			dev_dbg
+			    (sc->dev, "[FW_RC]:param[1]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
+			     tx_desc->rc_params[1].drate,
+			     tx_desc->rc_params[1].count,
+			     tx_desc->rc_params[1].crate,
+			     tx_desc->rc_params[1].dl_length,
+			     tx_desc->rc_params[1].frame_consume_time,
+			     tx_desc->rc_params[1].rts_cts_nav);
+			dev_dbg
+			    (sc->dev, "[FW_RC]:param[2]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
+			     tx_desc->rc_params[2].drate,
+			     tx_desc->rc_params[2].count,
+			     tx_desc->rc_params[2].crate,
+			     tx_desc->rc_params[2].dl_length,
+			     tx_desc->rc_params[2].frame_consume_time,
+			     tx_desc->rc_params[2].rts_cts_nav);
+		}
+#endif
+	} else {
+		nav =
+		    ssv6xxx_set_frame_duration(info, &ssv_rate,
+					       (skb->len + FCS_LEN), tx_desc,
+					       NULL, NULL);
+	}
+	if ((tx_desc->aggregation == 0)) {
+		if (tx_desc->tx_burst == 0) {
+			if (tx_desc->ack_policy != 0x01)
+				hdr->duration_id = nav;
+		} else {
+		}
+	}
+}
+
+void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb)
+{
+	struct ssv6200_tx_desc *tx_desc;
+	skb_push(skb, sc->sh->tx_desc_len);
+	tx_desc = (struct ssv6200_tx_desc *)skb->data;
+	memset((void *)tx_desc, 0, sc->sh->tx_desc_len);
+	ssv6xxx_update_txinfo(sc, skb);
+}
+
+int ssv6xxx_get_real_index(struct ssv_softc *sc, struct sk_buff *skb)
+{
+	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+	struct ieee80211_tx_rate *tx_drate;
+	struct ssv_rate_info ssv_rate;
+	tx_drate = &info->control.rates[0];
+	ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
+	return ssv_rate.drate_hw_idx;
+}
+
+static void _ssv6xxx_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+	struct ieee80211_vif *vif = info->control.vif;
+	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+	struct ssv6200_tx_desc *tx_desc;
+	int ret;
+	unsigned long flags;
+	bool send_hci = false;
+	do {
+		if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
+			if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
+				sc->tx.seq_no += 0x10;
+			hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
+			hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
+		}
+		if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+			if (ssv6xxx_get_real_index(sc, skb) <
+			    SSV62XX_RATE_MCS_INDEX) {
+				info->flags &= (~IEEE80211_TX_CTL_AMPDU);
+				goto tx_mpdu;
+			}
+			if (ssv6200_ampdu_tx_handler(hw, skb)) {
+				break;
+			} else {
+				info->flags &= (~IEEE80211_TX_CTL_AMPDU);
+			}
+		}
+ tx_mpdu:
+		ssv6xxx_add_txinfo(sc, skb);
+		if (vif &&
+		    vif->type == NL80211_IFTYPE_AP &&
+		    (sc->bq4_dtim) &&
+		    info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
+			struct ssv_vif_priv_data *priv_vif =
+			    (struct ssv_vif_priv_data *)vif->drv_priv;
+			u8 buffered = 0;
+			spin_lock_irqsave(&sc->ps_state_lock, flags);
+			if (priv_vif->sta_asleep_mask) {
+				buffered =
+				    ssv6200_bcast_enqueue(sc, &sc->bcast_txq,
+							  skb);
+				if (1 == buffered) {
+					dev_dbg(sc->dev, "ssv6200_tx:ssv6200_bcast_start\n");
+					ssv6200_bcast_start(sc);
+				}
+			}
+			spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+			if (buffered)
+				break;
+		}
+		if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
+			struct ssv_vif_priv_data *vif_priv =
+			    (struct ssv_vif_priv_data *)vif->drv_priv;
+			dev_dbg(sc->dev, "vif[%d] sc->bq4_dtim[%d]\n",
+				vif_priv->vif_idx, sc->bq4_dtim);
+		}
+		tx_desc = (struct ssv6200_tx_desc *)skb->data;
+		ret = HCI_SEND(sc->sh, skb, tx_desc->txq_idx);
+		send_hci = true;
+	} while (0);
+	if ((skb_queue_len(&sc->tx_skb_q) < LOW_TX_Q_LEN)
+	    ) {
+		if (sc->tx.flow_ctrl_status != 0) {
+			int ac;
+			for (ac = 0; ac < sc->hw->queues; ac++) {
+				if ((sc->tx.flow_ctrl_status & BIT(ac)) == 0)
+					ieee80211_wake_queue(sc->hw, ac);
+			}
+		} else {
+			ieee80211_wake_queues(sc->hw);
+		}
+	}
+}
+
+static void ssv6200_tx(struct ieee80211_hw *hw,
+		       struct ieee80211_tx_control *control,
+		       struct sk_buff *skb)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)hw->priv;
+	struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+	skb_info->sta = control ? control->sta : NULL;
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+	skb_info->timestamp = ktime_get();
+#endif
+	skb_queue_tail(&sc->tx_skb_q, skb);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	if (sc->max_tx_skb_q_len < skb_queue_len(&sc->tx_skb_q))
+		sc->max_tx_skb_q_len = skb_queue_len(&sc->tx_skb_q);
+#endif
+	wake_up_interruptible(&sc->tx_wait_q);
+	do {
+		if (skb_queue_len(&sc->tx_skb_q) >= MAX_TX_Q_LEN)
+			ieee80211_stop_queues(sc->hw);
+	} while (0);
+}
+
+int ssv6xxx_tx_task(void *data)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)data;
+	u32 wait_period = SSV_AMPDU_timer_period / 2;
+	dev_info(sc->dev, "TX Task started\n");
+	while (!kthread_should_stop()) {
+		u32 before_timeout = (-1);
+		set_current_state(TASK_INTERRUPTIBLE);
+		before_timeout = wait_event_interruptible_timeout(sc->tx_wait_q,
+								  (skb_queue_len
+								   (&sc->
+								    tx_skb_q)
+								   ||
+								   kthread_should_stop
+								   ()
+								   || sc->
+								   tx_q_empty),
+								  msecs_to_jiffies
+								  (wait_period));
+		if (kthread_should_stop()) {
+			dev_dbg(sc->dev, "Quit TX task loop...\n");
+			break;
+		}
+		set_current_state(TASK_RUNNING);
+		do {
+			struct sk_buff *tx_skb = skb_dequeue(&sc->tx_skb_q);
+			if (tx_skb == NULL)
+				break;
+			_ssv6xxx_tx(sc->hw, tx_skb);
+		} while (1);
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+		{
+			struct ssv_hw_txq *hw_txq = NULL;
+			struct ieee80211_tx_info *tx_info = NULL;
+			struct sk_buff *skb = NULL;
+			int txqid;
+			unsigned int timeout;
+			u32 status;
+			for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
+				hw_txq = &ssv_dbg_ctrl_hci->hw_txq[txqid];
+				skb = skb_peek(&hw_txq->qhead);
+				if (skb != NULL) {
+					tx_info = IEEE80211_SKB_CB(skb);
+					if (tx_info->
+					    flags & IEEE80211_TX_CTL_AMPDU)
+						timeout =
+						    cal_duration_of_ampdu(skb,
+									  SKB_DURATION_STAGE_IN_HWQ);
+					else
+						timeout =
+						    cal_duration_of_mpdu(skb);
+					if (timeout > SKB_DURATION_TIMEOUT_MS) {
+						HCI_IRQ_STATUS(ssv_dbg_ctrl_hci,
+							       &status);
+						dev_dbg(sc->dev, "hci int_mask: %08x\n",
+						       ssv_dbg_ctrl_hci->
+						       int_mask);
+						dev_dbg(sc->dev, "sdio status: %08x\n",
+						       status);
+						dev_dbg(sc->dev, "hwq%d len: %d\n", txqid,
+						       skb_queue_len(&hw_txq->
+								     qhead));
+					}
+				}
+			}
+		}
+#endif
+		if (sc->tx_q_empty || (before_timeout == 0)) {
+			u32 flused_ampdu = ssv6xxx_ampdu_flush(sc->hw);
+			sc->tx_q_empty = false;
+			if (flused_ampdu == 0 && before_timeout == 0) {
+				wait_period *= 2;
+				if (wait_period > 1000)
+					wait_period = 1000;
+			}
+		} else
+			wait_period = SSV_AMPDU_timer_period / 2;
+	}
+	return 0;
+}
+
+int ssv6xxx_rx_task(void *data)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)data;
+	unsigned long wait_period = msecs_to_jiffies(200);
+	unsigned long last_timeout_check_jiffies = jiffies;
+	unsigned long cur_jiffies;
+	dev_info(sc->dev, "RX Task started\n");
+	while (!kthread_should_stop()) {
+		u32 before_timeout = (-1);
+		set_current_state(TASK_INTERRUPTIBLE);
+		before_timeout = wait_event_interruptible_timeout(sc->rx_wait_q,
+								  (skb_queue_len
+								   (&sc->
+								    rx_skb_q)
+								   ||
+								   skb_queue_len
+								   (&sc->
+								    tx_done_q)
+								   ||
+								   kthread_should_stop
+								   ()),
+								  wait_period);
+		if (kthread_should_stop()) {
+			dev_dbg(sc->dev, "Quit RX task loop...\n");
+			break;
+		}
+		set_current_state(TASK_RUNNING);
+		cur_jiffies = jiffies;
+		if ((before_timeout == 0)
+		    || time_before((last_timeout_check_jiffies + wait_period),
+				   cur_jiffies)) {
+			ssv6xxx_ampdu_check_timeout(sc->hw);
+			last_timeout_check_jiffies = cur_jiffies;
+		}
+		if (skb_queue_len(&sc->rx_skb_q))
+			_process_rx_q(sc, &sc->rx_skb_q, NULL);
+		if (skb_queue_len(&sc->tx_done_q))
+			_process_tx_done(sc);
+	}
+	return 0;
+}
+
+struct ssv6xxx_iqk_cfg init_iqk_cfg = {
+	SSV6XXX_IQK_CFG_XTAL_26M,
+#ifdef CONFIG_SSV_DPD
+	SSV6XXX_IQK_CFG_PA_LI_MPB,
+#else
+	SSV6XXX_IQK_CFG_PA_DEF,
+#endif
+	0,
+	0,
+	26,
+	3,
+	0x75,
+	0x75,
+	0x80,
+	0x80,
+	SSV6XXX_IQK_CMD_INIT_CALI,
+	{SSV6XXX_IQK_TEMPERATURE
+	 + SSV6XXX_IQK_RXDC
+	 + SSV6XXX_IQK_RXRC
+	 + SSV6XXX_IQK_TXDC + SSV6XXX_IQK_TXIQ + SSV6XXX_IQK_RXIQ
+#ifdef CONFIG_SSV_DPD
+	 + SSV6XXX_IQK_PAPD
+#endif
+	 },
+};
+
+static int ssv6200_start(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_hw *sh = sc->sh;
+	struct ieee80211_channel *chan;
+    int ret;
+    
+	mutex_lock(&sc->mutex);
+    ret = ssv6xxx_init_mac(sc->sh);
+	if (ret != 0) {
+		dev_err(sc->dev, "Failed to initialize mac, ret=%d\n", ret);
+		ssv6xxx_deinit_mac(sc);
+		mutex_unlock(&sc->mutex);
+		return -1;
+	}
+#ifdef CONFIG_P2P_NOA
+	ssv6xxx_noa_reset(sc);
+#endif
+	HCI_START(sh);
+	ieee80211_wake_queues(hw);
+	ssv6200_ampdu_init(hw);
+	sc->watchdog_flag = WD_KICKED;
+	mutex_unlock(&sc->mutex);
+	mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
+#ifdef CONFIG_SSV_SMARTLINK
+	{
+		extern int ksmartlink_init(void);
+		(void)ksmartlink_init();
+	}
+#endif
+    ret = ssv6xxx_do_iq_calib(sc->sh, &init_iqk_cfg);
+    if (ret != 0) {
+        dev_err(sc->dev, "IQ Calibration failed, ret=%d\n", ret);
+        return ret;
+    }
+
+	dev_info(sc->dev, "Calibration successful\n");
+
+	SMAC_REG_WRITE(sc->sh, ADR_PHY_EN_1, 0x217f);
+	if ((sh->cfg.chip_identity == SSV6051Z)
+	    || (sc->sh->cfg.chip_identity == SSV6051P)) {
+		int i;
+		for (i = 0; i < sh->ch_cfg_size; i++) {
+			SMAC_REG_READ(sh, sh->p_ch_cfg[i].reg_addr,
+				      &sh->p_ch_cfg[i].ch1_12_value);
+		}
+	}
+	chan = hw->conf.chandef.chan;
+	sc->cur_channel = chan;
+	dev_dbg(sc->dev, "%s(): current channel: %d,sc->ps_status=%d\n", __FUNCTION__,
+	       sc->cur_channel->hw_value, sc->ps_status);
+	ssv6xxx_set_channel(sc, chan->hw_value);
+	ssv6xxx_rf_enable(sh);
+	return 0;
+}
+
+static void ssv6200_stop(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	u32 count = 0;
+	struct rssi_res_st *rssi_tmp0, *rssi_tmp1;
+	dev_dbg(sc->dev, "%s(): sc->ps_status=%d\n", __FUNCTION__,
+	       sc->ps_status);
+	mutex_lock(&sc->mutex);
+	list_for_each_entry_safe(rssi_tmp0, rssi_tmp1, &rssi_res.rssi_list,
+				 rssi_list) {
+		list_del(&rssi_tmp0->rssi_list);
+		kfree(rssi_tmp0);
+	}
+	ssv6200_ampdu_deinit(hw);
+	ssv6xxx_rf_disable(sc->sh);
+	HCI_STOP(sc->sh);
+#ifndef NO_USE_RXQ_LOCK
+	while (0) {
+#else
+	while (skb_queue_len(&sc->rx.rxq_head)) {
+#endif
+		dev_dbg(sc->dev, "sc->rx.rxq_count=%d\n", sc->rx.rxq_count);
+		count++;
+		if (count > 90000000) {
+			dev_err(sc->dev, "Could not empty RX queue during shutdown\n");
+			break;
+		}
+	}
+	HCI_TXQ_FLUSH(sc->sh, (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2 |
+			       TXQ_EDCA_3 | TXQ_MGMT));
+	if ((sc->ps_status == PWRSV_PREPARE) || (sc->ps_status == PWRSV_ENABLE)) {
+		ssv6xxx_enable_ps(sc);
+		ssv6xxx_rf_enable(sc->sh);
+	}
+	sc->watchdog_flag = WD_SLEEP;
+	mutex_unlock(&sc->mutex);
+	del_timer_sync(&sc->watchdog_timeout);
+#ifdef CONFIG_SSV_SMARTLINK
+	{
+		extern void ksmartlink_exit(void);
+		ksmartlink_exit();
+	}
+#endif
+	dev_dbg(sc->dev, "%s(): leave\n", __FUNCTION__);
+}
+
+void inline ssv62xxx_set_bssid(struct ssv_softc *sc, u8 * bssid)
+{
+	memcpy(sc->bssid, bssid, 6);
+	SMAC_REG_WRITE(sc->sh, ADR_BSSID_0, *((u32 *) & sc->bssid[0]));
+	SMAC_REG_WRITE(sc->sh, ADR_BSSID_1, *((u32 *) & sc->bssid[4]));
+}
+
+struct ssv_vif_priv_data *ssv6xxx_config_vif_res(struct ssv_softc *sc,
+						 struct ieee80211_vif *vif)
+{
+	int i;
+	struct ssv_vif_priv_data *priv_vif;
+	struct ssv_vif_info *vif_info;
+	lockdep_assert_held(&sc->mutex);
+	for (i = 0; i < SSV6200_MAX_VIF; i++) {
+		if (sc->vif_info[i].vif == NULL)
+			break;
+	}
+	BUG_ON(i >= SSV6200_MAX_VIF);
+	dev_dbg(sc->dev, "ssv6xxx_config_vif_res id[%d].\n", i);
+	priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
+	memset(priv_vif, 0, sizeof(struct ssv_vif_priv_data));
+	priv_vif->vif_idx = i;
+	memset(&sc->vif_info[i], 0, sizeof(sc->vif_info[0]));
+	sc->vif_info[i].vif = vif;
+	sc->vif_info[i].vif_priv = priv_vif;
+	INIT_LIST_HEAD(&priv_vif->sta_list);
+	priv_vif->pair_cipher = SSV_CIPHER_NONE;
+	priv_vif->group_cipher = SSV_CIPHER_NONE;
+	priv_vif->has_hw_decrypt = false;
+	priv_vif->has_hw_encrypt = false;
+	priv_vif->need_sw_encrypt = false;
+	priv_vif->need_sw_decrypt = false;
+	priv_vif->use_mac80211_decrypt = false;
+	priv_vif->is_security_valid = false;
+	priv_vif->force_sw_encrypt = (vif->type == NL80211_IFTYPE_AP);
+	vif_info = &sc->vif_info[priv_vif->vif_idx];
+	vif_info->if_type = vif->type;
+	vif_info->vif = vif;
+	return priv_vif;
+}
+
+static int ssv6200_add_interface(struct ieee80211_hw *hw,
+				 struct ieee80211_vif *vif)
+{
+	struct ssv_softc *sc = hw->priv;
+	int ret = 0;
+	struct ssv_vif_priv_data *vif_priv = NULL;
+	dev_dbg(sc->dev, "[I] %s(): vif->type = %d, NL80211_IFTYPE_AP=%d\n", __FUNCTION__,
+	       vif->type, NL80211_IFTYPE_AP);
+	if ((sc->nvif >= SSV6200_MAX_VIF)
+	    || (((vif->type == NL80211_IFTYPE_AP)
+		 || (vif->p2p))
+		&& (sc->ap_vif != NULL))) {
+		dev_err(sc->dev, "Add interface of type %d (p2p: %d) failed.\n",
+			vif->type, vif->p2p);
+		return -EOPNOTSUPP;
+	}
+	mutex_lock(&sc->mutex);
+	vif_priv = ssv6xxx_config_vif_res(sc, vif);
+	if ((vif_priv->vif_idx == 0) && (vif->p2p == 0)
+	    && (vif->type == NL80211_IFTYPE_AP)) {
+		dev_dbg(sc->dev, "VIF[0] set bssid and config opmode to ap\n");
+		ssv62xxx_set_bssid(sc, sc->sh->cfg.maddr[0]);
+		SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, SSV6200_OPMODE_AP,
+				  OP_MODE_MSK);
+	}
+	if (vif->type == NL80211_IFTYPE_AP) {
+		BUG_ON(sc->ap_vif != NULL);
+		sc->ap_vif = vif;
+		if (!vif->p2p && (vif_priv->vif_idx == 0)) {
+			dev_dbg(sc->dev, "Normal AP mode. Config Q4 to DTIM Q.\n");
+			SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC,
+					  MTX_HALT_MNG_UNTIL_DTIM_MSK,
+					  MTX_HALT_MNG_UNTIL_DTIM_MSK);
+			sc->bq4_dtim = true;
+		}
+	}
+	sc->nvif++;
+	dev_dbg(sc->dev,
+		"VIF %02x:%02x:%02x:%02x:%02x:%02x of type %d is added.\n",
+		vif->addr[0], vif->addr[1], vif->addr[2], vif->addr[3],
+		vif->addr[4], vif->addr[5], vif->type);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	ssv6xxx_debugfs_add_interface(sc, vif);
+#endif
+	mutex_unlock(&sc->mutex);
+	return ret;
+}
+
+static void ssv6200_remove_interface(struct ieee80211_hw *hw,
+				     struct ieee80211_vif *vif)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	dev_err(sc->dev,
+		"Removing interface %02x:%02x:%02x:%02x:%02x:%02x. PS=%d\n",
+		vif->addr[0], vif->addr[1], vif->addr[2], vif->addr[3],
+		vif->addr[4], vif->addr[5], sc->ps_status);
+	mutex_lock(&sc->mutex);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	ssv6xxx_debugfs_remove_interface(sc, vif);
+#endif
+	if (vif->type == NL80211_IFTYPE_AP) {
+		if (sc->bq4_dtim) {
+			sc->bq4_dtim = false;
+			ssv6200_release_bcast_frame_res(sc, vif);
+			SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC,
+					  0, MTX_HALT_MNG_UNTIL_DTIM_MSK);
+			dev_dbg(sc->dev, "Config Q4 to normal Q \n");
+		}
+		ssv6xxx_beacon_release(sc);
+		sc->ap_vif = NULL;
+	}
+	memset(&sc->vif_info[vif_priv->vif_idx], 0,
+	       sizeof(struct ssv_vif_info));
+	sc->nvif--;
+	mutex_unlock(&sc->mutex);
+}
+
+static int ssv6200_change_interface(struct ieee80211_hw *dev,
+				    struct ieee80211_vif *vif,
+				    enum nl80211_iftype new_type, bool p2p)
+{
+    struct ssv_softc *sc = dev->priv;
+	int ret = 0;
+    
+	dev_dbg(sc->dev, "change_interface new: %d (%d), old: %d (%d)\n", new_type,
+	       p2p, vif->type, vif->p2p);
+
+	if (new_type != vif->type || vif->p2p != p2p) {
+		ssv6200_remove_interface(dev, vif);
+		vif->type = new_type;
+		vif->p2p = p2p;
+		ret = ssv6200_add_interface(dev, vif);
+	}
+
+	return ret;
+}
+
+void ssv6xxx_ps_callback_func(unsigned long data)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)data;
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	int retry_cnt = 20;
+#ifdef SSV_WAKEUP_HOST
+	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
+		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
+	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
+	SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + 6 * 4,
+		       (sc->mac_deci_tbl[6] | 1));
+#else
+	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
+		       M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
+	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+		       M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
+	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
+		       M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
+#endif
+	skb = ssv_skb_alloc(sizeof(struct cfg_host_cmd));
+	skb->data_len = sizeof(struct cfg_host_cmd);
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->RSVD0 = 0;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_PS;
+	host_cmd->len = skb->data_len;
+#ifdef SSV_WAKEUP_HOST
+	host_cmd->dummy = sc->ps_aid;
+#else
+	host_cmd->dummy = 0;
+#endif
+	sc->ps_aid = 0;
+	while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
+		dev_warn(sc->dev, "PS cmd retry=%d!!\n", retry_cnt);
+		retry_cnt--;
+	}
+	ssv_skb_free(skb);
+	dev_dbg(sc->dev, "SSV6XXX_HOST_CMD_PS,ps_aid = %d,len=%d,tabl=0x%x\n",
+	       host_cmd->dummy, skb->len, (sc->mac_deci_tbl[6] | 1));
+}
+
+void ssv6xxx_enable_ps(struct ssv_softc *sc)
+{
+	sc->ps_status = PWRSV_ENABLE;
+}
+
+void ssv6xxx_disable_ps(struct ssv_softc *sc)
+{
+	sc->ps_status = PWRSV_DISABLE;
+	dev_info(sc->dev, "Power saving disabled\n");
+}
+
+int ssv6xxx_watchdog_controller(struct ssv_hw *sh, u8 flag)
+{
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	int ret = 0;
+	dev_dbg(sh->sc->dev, "ssv6xxx_watchdog_controller %d\n", flag);
+	skb = ssv_skb_alloc(HOST_CMD_HDR_LEN);
+	if (skb == NULL) {
+		dev_warn(sh->sc->dev, "init ssv6xxx_watchdog_controller fail!!!\n");
+		return (-1);
+	}
+	skb->data_len = HOST_CMD_HDR_LEN;
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) flag;
+	host_cmd->len = skb->data_len;
+	sh->hci.hci_ops->hci_send_cmd(skb);
+	ssv_skb_free(skb);
+	return ret;
+}
+
+static int ssv6200_config(struct ieee80211_hw *hw, u32 changed)
+{
+	struct ssv_softc *sc = hw->priv;
+	int ret = 0;
+	mutex_lock(&sc->mutex);
+	if (changed & IEEE80211_CONF_CHANGE_PS) {
+		struct ieee80211_conf *conf = &hw->conf;
+		if (conf->flags & IEEE80211_CONF_PS) {
+			dev_dbg(sc->dev, "Enable IEEE80211_CONF_PS ps_aid=%d\n",
+			       sc->ps_aid);
+		} else {
+			dev_dbg(sc->dev, "Disable IEEE80211_CONF_PS ps_aid=%d\n",
+			       sc->ps_aid);
+		}
+	}
+	if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
+		struct ieee80211_channel *chan;
+		chan = hw->conf.chandef.chan;
+#ifdef CONFIG_P2P_NOA
+		if (sc->p2p_noa.active_noa_vif) {
+			dev_dbg(sc->dev, "NOA operating-active vif[%02x] skip scan\n",
+			       sc->p2p_noa.active_noa_vif);
+			goto out;
+		}
+#endif
+		if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) {
+			if ((sc->ap_vif == NULL)
+			    ||
+			    list_empty(&
+				       ((struct ssv_vif_priv_data *)sc->ap_vif->
+					drv_priv)->sta_list)) {
+				HCI_PAUSE(sc->sh,
+					  (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
+					   | TXQ_EDCA_3 | TXQ_MGMT));
+				sc->sc_flags |= SC_OP_OFFCHAN;
+				ssv6xxx_set_channel(sc, chan->hw_value);
+				sc->hw_chan = chan->hw_value;
+				HCI_RESUME(sc->sh, TXQ_MGMT);
+			} else {
+				dev_dbg(sc->dev,
+					"Off-channel to %d is ignored when AP mode enabled.\n",
+					chan->hw_value);
+			}
+		} else {
+			if ((sc->cur_channel == NULL)
+			    || (sc->sc_flags & SC_OP_OFFCHAN)
+			    || (sc->hw_chan != chan->hw_value)) {
+				HCI_PAUSE(sc->sh,
+					  (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
+					   | TXQ_EDCA_3 | TXQ_MGMT));
+				ssv6xxx_set_channel(sc, chan->hw_value);
+				sc->cur_channel = chan;
+				HCI_RESUME(sc->sh,
+					   (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
+					    | TXQ_EDCA_3 | TXQ_MGMT));
+				sc->sc_flags &= ~SC_OP_OFFCHAN;
+			} else {
+				dev_dbg(sc->dev,
+					"Change to the same channel %d\n",
+					chan->hw_value);
+			}
+		}
+	}
+#ifdef CONFIG_P2P_NOA
+ out:
+#endif
+	mutex_unlock(&sc->mutex);
+	return ret;
+}
+
+#define SUPPORTED_FILTERS \
+    (FIF_ALLMULTI | \
+    FIF_CONTROL | \
+    FIF_PSPOLL | \
+    FIF_OTHER_BSS | \
+    FIF_BCN_PRBRESP_PROMISC | \
+    FIF_PROBE_REQ | \
+    FIF_FCSFAIL)
+static void ssv6200_config_filter(struct ieee80211_hw *hw,
+				  unsigned int changed_flags,
+				  unsigned int *total_flags, u64 multicast)
+{
+	changed_flags &= SUPPORTED_FILTERS;
+	*total_flags &= SUPPORTED_FILTERS;
+}
+
+static void ssv6200_bss_info_changed(struct ieee80211_hw *hw,
+				     struct ieee80211_vif *vif,
+				     struct ieee80211_bss_conf *info,
+				     u32 changed)
+{
+	struct ssv_vif_priv_data *priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
+	struct ssv_softc *sc = hw->priv;
+#ifdef CONFIG_P2P_NOA
+	u8 null_address[6] = { 0 };
+#endif
+	mutex_lock(&sc->mutex);
+	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
+		dev_dbg(sc->dev, "BSS Changed use_short_preamble[%d]\n",
+		       info->use_short_preamble);
+		if (info->use_short_preamble)
+			sc->sc_flags |= SC_OP_SHORT_PREAMBLE;
+		else
+			sc->sc_flags &= ~SC_OP_SHORT_PREAMBLE;
+	}
+	if (!priv_vif->vif_idx) {
+		if (changed & BSS_CHANGED_BSSID) {
+#ifdef CONFIG_P2P_NOA
+			struct ssv_vif_priv_data *vif_priv;
+			vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+#endif
+			ssv62xxx_set_bssid(sc, (u8 *) info->bssid);
+			dev_dbg(sc->dev, "BSS_CHANGED_BSSID: %02x:%02x:%02x:%02x:%02x:%02x\n",
+			     info->bssid[0], info->bssid[1], info->bssid[2],
+			     info->bssid[3], info->bssid[4], info->bssid[5]);
+#ifdef CONFIG_P2P_NOA
+			if (memcmp(info->bssid, null_address, 6))
+				ssv6xxx_noa_hdl_bss_change(sc,
+							   MONITOR_NOA_CONF_ADD,
+							   vif_priv->vif_idx);
+			else
+				ssv6xxx_noa_hdl_bss_change(sc,
+							   MONITOR_NOA_CONF_REMOVE,
+							   vif_priv->vif_idx);
+#endif
+		}
+		if (changed & BSS_CHANGED_ERP_SLOT) {
+			u32 regval = 0;
+			dev_dbg(sc->dev, "BSS_CHANGED_ERP_SLOT: use_short_slot[%d]\n",
+			       info->use_short_slot);
+			if (info->use_short_slot) {
+				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_IFS, &regval);
+				regval = regval & MTX_DUR_SLOT_I_MSK;
+				regval |= 9 << MTX_DUR_SLOT_SFT;
+				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_IFS, regval);
+				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_SIFS_G,
+					      &regval);
+				regval = regval & MTX_DUR_BURST_SIFS_G_I_MSK;
+				regval |= 0xa << MTX_DUR_BURST_SIFS_G_SFT;
+				regval = regval & MTX_DUR_SLOT_G_I_MSK;
+				regval |= 9 << MTX_DUR_SLOT_G_SFT;
+				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_SIFS_G,
+					       regval);
+			} else {
+				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_IFS, &regval);
+				regval = regval & MTX_DUR_SLOT_I_MSK;
+				regval |= 20 << MTX_DUR_SLOT_SFT;
+				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_IFS, regval);
+				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_SIFS_G,
+					      &regval);
+				regval = regval & MTX_DUR_BURST_SIFS_G_I_MSK;
+				regval |= 0xa << MTX_DUR_BURST_SIFS_G_SFT;
+				regval = regval & MTX_DUR_SLOT_G_I_MSK;
+				regval |= 20 << MTX_DUR_SLOT_G_SFT;
+				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_SIFS_G,
+					       regval);
+			}
+		}
+	}
+	if (changed & BSS_CHANGED_HT) {
+		dev_dbg(sc->dev, "BSS_CHANGED_HT: Untreated!!\n");
+	}
+	if (changed & BSS_CHANGED_BASIC_RATES) {
+		dev_dbg(sc->dev, "ssv6xxx_rc_update_basic_rate!!\n");
+		ssv6xxx_rc_update_basic_rate(sc, info->basic_rates);
+	}
+	if (vif->type == NL80211_IFTYPE_STATION) {
+		dev_dbg(sc->dev, "NL80211_IFTYPE_STATION!!\n");
+		if ((changed & BSS_CHANGED_ASSOC) && (vif->p2p == 0)) {
+			sc->isAssoc = info->assoc;
+			if (!sc->isAssoc) {
+				sc->channel_center_freq = 0;
+				sc->ps_aid = 0;
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x0400);
+#endif
+				SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_CONTROL,
+					       0x0);
+			} else {
+				struct ieee80211_channel *curchan;
+				curchan = hw->conf.chandef.chan;
+				sc->channel_center_freq = curchan->center_freq;
+				dev_dbg(sc->dev, "info->aid = %d\n", info->aid);
+				sc->ps_aid = info->aid;
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x1000);
+#endif
+			}
+		}
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+		else if ((changed & BSS_CHANGED_ASSOC) && vif->p2p == 1) {
+			if (info->assoc)
+				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x0400);
+			else if (sc->ps_aid != 0)
+				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x1000);
+		}
+#endif
+	}
+	if (vif->type == NL80211_IFTYPE_AP) {
+		if (changed & (BSS_CHANGED_BEACON
+			       | BSS_CHANGED_SSID
+			       | BSS_CHANGED_BSSID | BSS_CHANGED_BASIC_RATES)) {
+#ifdef BROADCAST_DEBUG
+			dev_dbg(sc->dev, "[A] ssv6200_bss_info_changed:beacon changed\n");
+#endif
+			queue_work(sc->config_wq, &sc->set_tim_work);
+		}
+		if (changed & BSS_CHANGED_BEACON_INT) {
+			dev_dbg(sc->dev, "[A] BSS_CHANGED_BEACON_INT beacon_interval(%d)\n",
+			     info->beacon_int);
+			if (sc->beacon_interval != info->beacon_int) {
+				sc->beacon_interval = info->beacon_int;
+				ssv6xxx_beacon_set_info(sc, sc->beacon_interval,
+							sc->beacon_dtim_cnt);
+			}
+		}
+		if (changed & BSS_CHANGED_BEACON_ENABLED) {
+#ifdef BEACON_DEBUG
+			dev_dbg(sc->dev, "[A] BSS_CHANGED_BEACON_ENABLED (0x%x)\n",
+			       info->enable_beacon);
+#endif
+			if (0 != ssv6xxx_beacon_enable(sc, info->enable_beacon)) {
+				dev_err(sc->dev, "Beacon enable %d error.\n",
+					info->enable_beacon);
+			}
+		}
+	}
+	mutex_unlock(&sc->mutex);
+	dev_dbg(sc->dev, "[I] %s(): leave\n", __FUNCTION__);
+}
+
+static int ssv6200_sta_add(struct ieee80211_hw *hw,
+			   struct ieee80211_vif *vif, struct ieee80211_sta *sta)
+{
+	struct ssv_sta_priv_data *sta_priv_dat = NULL;
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_sta_info *sta_info;
+	u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
+	int s, i;
+	u32 reg_wsid_tid0[] = { ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ };
+	u32 reg_wsid_tid7[] = { ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ };
+	unsigned long flags;
+	int ret = 0;
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	int fw_sec_caps = SSV6XXX_WSID_SEC_NONE;
+	bool tdls_use_sw_cipher = false, tdls_link = false;
+	dev_dbg(sc->dev, "[I] %s(): vif[%d] ", __FUNCTION__, vif_priv->vif_idx);
+	if (sc->force_triger_reset == true) {
+		vif_priv->sta_asleep_mask = 0;
+		do {
+			spin_lock_irqsave(&sc->ps_state_lock, flags);
+			for (s = 0; s < SSV_NUM_STA; s++, sta_info++) {
+				sta_info = &sc->sta_info[s];
+				if ((sta_info->s_flags & STA_FLAG_VALID)) {
+					if (sta_info->sta == sta) {
+						dev_dbg
+						    (sc->dev, "search stat %02x:%02x:%02x:%02x:%02x:%02x to  wsid=%d\n",
+						     sta->addr[0], sta->addr[1],
+						     sta->addr[2], sta->addr[3],
+						     sta->addr[4], sta->addr[5],
+						     sta_info->hw_wsid);
+						spin_unlock_irqrestore(&sc->
+								       ps_state_lock,
+								       flags);
+						return ret;
+					}
+				}
+			}
+			spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+			if (s >= SSV_NUM_STA) {
+				break;
+			}
+		} while (0);
+	}
+	do {
+		spin_lock_irqsave(&sc->ps_state_lock, flags);
+		if (!list_empty(&vif_priv->sta_list)
+		    && vif->type == NL80211_IFTYPE_STATION) {
+			tdls_link = true;
+		}
+		if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_NONE)
+		    && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)
+		    && (sc->sh->cfg.use_wpa2_only == false)) {
+			tdls_use_sw_cipher = true;
+		}
+		if (((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false))
+		    || sc->sh->cfg.use_wpa2_only)
+			s = 0;
+		else
+			s = 2;
+		for (; s < SSV_NUM_STA; s++) {
+			sta_info = &sc->sta_info[s];
+			if ((sta_info->s_flags & STA_FLAG_VALID) == 0) {
+				sta_info->aid = sta->aid;
+				sta_info->sta = sta;
+				sta_info->vif = vif;
+				sta_info->s_flags = STA_FLAG_VALID;
+				sta_priv_dat =
+				    (struct ssv_sta_priv_data *)sta->drv_priv;
+				sta_priv_dat->sta_idx = s;
+				sta_priv_dat->sta_info = sta_info;
+				sta_priv_dat->has_hw_encrypt = false;
+				sta_priv_dat->has_hw_decrypt = false;
+				sta_priv_dat->need_sw_decrypt = false;
+				sta_priv_dat->need_sw_encrypt = false;
+				sta_priv_dat->use_mac80211_decrypt = false;
+				if ((vif_priv->pair_cipher == SSV_CIPHER_WEP40)
+				    || (vif_priv->pair_cipher ==
+					SSV_CIPHER_WEP104)) {
+					sta_priv_dat->has_hw_encrypt =
+					    vif_priv->has_hw_encrypt;
+					sta_priv_dat->has_hw_decrypt =
+					    vif_priv->has_hw_decrypt;
+					sta_priv_dat->need_sw_encrypt =
+					    vif_priv->need_sw_encrypt;
+					sta_priv_dat->need_sw_decrypt =
+					    vif_priv->need_sw_decrypt;
+				}
+				list_add_tail(&sta_priv_dat->list,
+					      &vif_priv->sta_list);
+				break;
+			}
+		}
+		spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+		if (s >= SSV_NUM_STA) {
+			dev_err(sc->dev,
+				"Number of STA exceeds driver limitation %d\n.",
+				SSV_NUM_STA);
+			ret = -1;
+			break;
+		}
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		ssv6xxx_debugfs_add_sta(sc, sta_info);
+#endif
+		sta_info->hw_wsid = -1;
+		if (sta_priv_dat->sta_idx < SSV_NUM_HW_STA) {
+			SMAC_REG_WRITE(sc->sh, reg_wsid[s] + 4,
+				       *((u32 *) & sta->addr[0]));
+			SMAC_REG_WRITE(sc->sh, reg_wsid[s] + 8,
+				       *((u32 *) & sta->addr[4]));
+			SMAC_REG_WRITE(sc->sh, reg_wsid[s], 1);
+			for (i = reg_wsid_tid0[s]; i <= reg_wsid_tid7[s];
+			     i += 4)
+				SMAC_REG_WRITE(sc->sh, i, 0);
+			ssv6xxx_rc_hw_reset(sc, sta_priv_dat->rc_idx, s);
+			sta_info->hw_wsid = sta_priv_dat->sta_idx;
+		} else if ((vif_priv->vif_idx == 0)
+			   || sc->sh->cfg.use_wpa2_only) {
+			sta_info->hw_wsid = sta_priv_dat->sta_idx;
+		}
+		if ((sta_priv_dat->has_hw_encrypt
+		     || sta_priv_dat->has_hw_decrypt)
+		    && ((vif_priv->pair_cipher == SSV_CIPHER_WEP40)
+			|| (vif_priv->pair_cipher == SSV_CIPHER_WEP104))) {
+			struct ssv_vif_info *vif_info =
+			    &sc->vif_info[vif_priv->vif_idx];
+			struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey;
+			_set_wep_hw_crypto_pair_key(sc, vif_info, sta_info,
+						    (void *)sramKey);
+			if (sramKey->sta_key[0].pair_key_idx != 0) {
+				_set_wep_hw_crypto_group_key(sc, vif_info,
+							     sta_info,
+							     (void *)sramKey);
+			}
+		}
+		ssv6200_ampdu_tx_add_sta(hw, sta);
+		if (sta_info->hw_wsid >= SSV_NUM_HW_STA) {
+			if (sta_priv_dat->has_hw_decrypt)
+				fw_sec_caps = SSV6XXX_WSID_SEC_PAIRWISE;
+			if (vif_priv->has_hw_decrypt)
+				fw_sec_caps |= SSV6XXX_WSID_SEC_GROUP;
+			hw_update_watch_wsid(sc, sta, sta_info,
+					     sta_priv_dat->sta_idx, fw_sec_caps,
+					     SSV6XXX_WSID_OPS_ADD);
+		} else if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx)) {
+			hw_update_watch_wsid(sc, sta, sta_info,
+					     sta_priv_dat->sta_idx,
+					     SSV6XXX_WSID_SEC_SW,
+					     SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE);
+			hw_update_watch_wsid(sc, sta, sta_info,
+					     sta_priv_dat->sta_idx,
+					     SSV6XXX_WSID_SEC_SW,
+					     SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE);
+		}
+		dev_dbg
+		    (sc->dev, "Add %02x:%02x:%02x:%02x:%02x:%02x to VIF %d sw_idx=%d, wsid=%d\n",
+		     sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+		     sta->addr[4], sta->addr[5], vif_priv->vif_idx,
+		     sta_priv_dat->sta_idx, sta_info->hw_wsid);
+	} while (0);
+	return ret;
+}
+
+void ssv6200_rx_flow_check(struct ssv_sta_priv_data *sta_priv_dat,
+			   struct ssv_softc *sc)
+{
+	if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx)
+	    && (sta_priv_dat->need_sw_decrypt)) {
+		int other_hw_wsid = (sta_priv_dat->sta_idx + 1) & 1;
+		struct ssv_sta_info *sta_info = &sc->sta_info[other_hw_wsid];
+		struct ieee80211_sta *sta = sta_info->sta;
+		struct ssv_sta_priv_data *sta_priv =
+		    (struct ssv_sta_priv_data *)sta->drv_priv;
+		mutex_lock(&sc->mutex);
+		if ((sta_info->s_flags == 0)
+		    || ((sta_info->s_flags && STA_FLAG_VALID)
+			&& (sta_priv->has_hw_decrypt))) {
+			SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+				       M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) |
+				       (M_ENG_HWHCI << 8));
+			dev_dbg(sc->dev, "redirect Rx flow for sta %d disconnect\n",
+			       sta_priv_dat->sta_idx);
+		}
+		mutex_unlock(&sc->mutex);
+	}
+}
+
+static int ssv6200_sta_remove(struct ieee80211_hw *hw,
+			      struct ieee80211_vif *vif,
+			      struct ieee80211_sta *sta)
+{
+	u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
+	struct ssv_sta_priv_data *sta_priv_dat =
+	    (struct ssv_sta_priv_data *)sta->drv_priv;
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_sta_info *sta_info = sta_priv_dat->sta_info;
+	unsigned long flags;
+	u32 bit;
+	struct ssv_vif_priv_data *priv_vif =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	u8 hw_wsid = -1;
+	BUG_ON(sta_priv_dat->sta_idx >= SSV_NUM_STA);
+	dev_notice(sc->dev,
+		   "Removing STA %d (%02X:%02X:%02X:%02X:%02X:%02X) from VIF %d\n.",
+		   sta_priv_dat->sta_idx, sta->addr[0], sta->addr[1],
+		   sta->addr[2], sta->addr[3], sta->addr[4], sta->addr[5],
+		   priv_vif->vif_idx);
+	ssv6200_rx_flow_check(sta_priv_dat, sc);
+	spin_lock_irqsave(&sc->ps_state_lock, flags);
+	bit = BIT(sta_priv_dat->sta_idx);
+	priv_vif->sta_asleep_mask &= ~bit;
+	if (sta_info->hw_wsid != -1) {
+		hw_wsid = sta_info->hw_wsid;
+	}
+	if (sta_info->hw_wsid >= SSV_NUM_HW_STA) {
+		spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+		hw_update_watch_wsid(sc, sta, sta_info, sta_info->hw_wsid, 0,
+				     SSV6XXX_WSID_OPS_DEL);
+		spin_lock_irqsave(&sc->ps_state_lock, flags);
+	}
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	{
+		ssv6xxx_debugfs_remove_sta(sc, sta_info);
+	}
+#endif
+	memset(sta_info, 0, sizeof(*sta_info));
+	sta_priv_dat->sta_idx = -1;
+	list_del(&sta_priv_dat->list);
+	if (list_empty(&priv_vif->sta_list)
+	    && vif->type == NL80211_IFTYPE_STATION) {
+		priv_vif->pair_cipher = 0;
+		priv_vif->group_cipher = 0;
+	}
+	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+	if ((hw_wsid != -1) && (hw_wsid < SSV_NUM_HW_STA))
+		SMAC_REG_WRITE(sc->sh, reg_wsid[hw_wsid], 0x00);
+	return 0;
+}
+
+static void ssv6200_sta_notify(struct ieee80211_hw *hw,
+			       struct ieee80211_vif *vif,
+			       enum sta_notify_cmd cmd,
+			       struct ieee80211_sta *sta)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_vif_priv_data *priv_vif =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	struct ssv_sta_priv_data *sta_priv_dat =
+	    sta != NULL ? (struct ssv_sta_priv_data *)sta->drv_priv : NULL;
+	struct ssv_sta_info *sta_info;
+	u32 bit, prev;
+	unsigned long flags;
+	spin_lock_irqsave(&sc->ps_state_lock, flags);
+	if (sta_priv_dat != NULL) {
+		bit = BIT(sta_priv_dat->sta_idx);
+		prev = priv_vif->sta_asleep_mask & bit;
+		sta_info = sta_priv_dat->sta_info;
+		switch (cmd) {
+		case STA_NOTIFY_SLEEP:
+			if (!prev) {
+				sta_info->sleeping = true;
+				if ((vif->type == NL80211_IFTYPE_AP)
+				    && sc->bq4_dtim
+				    && !priv_vif->sta_asleep_mask
+				    && ssv6200_bcast_queue_len(&sc->
+							       bcast_txq)) {
+					dev_dbg(sc->dev, "%s(): ssv6200_bcast_start\n", __FUNCTION__);
+					ssv6200_bcast_start(sc);
+				}
+				priv_vif->sta_asleep_mask |= bit;
+			}
+			break;
+		case STA_NOTIFY_AWAKE:
+			if (prev) {
+				sta_info->sleeping = false;
+				priv_vif->sta_asleep_mask &= ~bit;
+			}
+			break;
+		default:
+			break;
+		}
+	}
+	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+}
+
+static u64 ssv6200_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
+{
+	return jiffies * 1000 * 1000 / HZ;
+}
+
+static u64 ssv6200_get_systime_us(void)
+{
+#if LINUX_VERSION_CODE > KERNEL_VERSION(4,19,0)
+	struct timespec64 ts;
+	ktime_get_boottime_ts64(&ts);
+#else
+	struct timespec ts;
+	get_monotonic_boottime(&ts);
+#endif
+	return ((u64) ts.tv_sec * 1000000) + ts.tv_nsec / 1000;
+}
+
+static u32 pre_11b_cca_control;
+static u32 pre_11b_cca_1;
+static void ssv6200_sw_scan_start(struct ieee80211_hw *hw,
+				  struct ieee80211_vif *vif,
+				  const u8 * mac_addr)
+{
+	((struct ssv_softc *)(hw->priv))->bScanning = true;
+	SMAC_REG_READ(((struct ssv_softc *)(hw->priv))->sh,
+		      ADR_RX_11B_CCA_CONTROL, &pre_11b_cca_control);
+	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
+		       ADR_RX_11B_CCA_CONTROL, 0x0);
+	SMAC_REG_READ(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
+		      &pre_11b_cca_1);
+	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
+		       RX_11B_CCA_IN_SCAN);
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_MRX_FLT_EN3,
+		       0x0400);
+#endif
+}
+
+static void ssv6200_sw_scan_complete(struct ieee80211_hw *hw,
+				     struct ieee80211_vif *vif)
+{
+
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+	bool is_p2p_assoc;
+#endif
+	((struct ssv_softc *)(hw->priv))->bScanning = false;
+	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
+		       ADR_RX_11B_CCA_CONTROL, pre_11b_cca_control);
+	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
+		       pre_11b_cca_1);
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+	is_p2p_assoc =
+	    ((struct ssv_softc *)(hw->priv))->vif_info[1].vif->bss_conf.assoc;
+	if (((struct ssv_softc *)(hw->priv))->ps_aid != 0 && (!is_p2p_assoc))
+		SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
+			       ADR_MRX_FLT_EN3, 0x1000);
+#endif
+}
+
+static int ssv6200_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
+			   bool set)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_sta_info *sta_info = sta
+	    ? ((struct ssv_sta_priv_data *)sta->drv_priv)->sta_info : NULL;
+	if (sta_info && (sta_info->tim_set ^ set)) {
+        dev_dbg(sc->dev, "[I] [A] ssvcabrio_set_tim");
+		sta_info->tim_set = set;
+		queue_work(sc->config_wq, &sc->set_tim_work);
+	}
+	return 0;
+}
+
+static int ssv6200_conf_tx(struct ieee80211_hw *hw,
+			   struct ieee80211_vif *vif, u16 queue,
+			   const struct ieee80211_tx_queue_params *params)
+{
+	struct ssv_softc *sc = hw->priv;
+	u32 cw;
+	u8 hw_txqid = sc->tx.hw_txqid[queue];
+	struct ssv_vif_priv_data *priv_vif =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	dev_dbg
+	    (sc->dev, "[I] sv6200_conf_tx vif[%d] qos[%d] queue[%d] aifsn[%d] cwmin[%d] cwmax[%d] txop[%d] \n",
+	     priv_vif->vif_idx, vif->bss_conf.qos, queue, params->aifs,
+	     params->cw_min, params->cw_max, params->txop);
+	if (queue > NL80211_TXQ_Q_BK)
+		return 1;
+	if (priv_vif->vif_idx != 0) {
+		dev_warn(sc->dev,
+			 "WMM setting applicable to primary interface only.\n");
+		return 1;
+	}
+	mutex_lock(&sc->mutex);
+	SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET,
+			  (vif->bss_conf.qos << QOS_EN_SFT), QOS_EN_MSK);
+	cw = (params->aifs - 1) & 0xf;
+	cw |= ((ilog2(params->cw_min + 1)) & 0xf) << TXQ1_MTX_Q_ECWMIN_SFT;
+	cw |= ((ilog2(params->cw_max + 1)) & 0xf) << TXQ1_MTX_Q_ECWMAX_SFT;
+	cw |= ((params->txop) & 0xff) << TXQ1_MTX_Q_TXOP_LIMIT_SFT;
+	SMAC_REG_WRITE(sc->sh, ADR_TXQ0_MTX_Q_AIFSN + 0x100 * hw_txqid, cw);
+	mutex_unlock(&sc->mutex);
+	return 0;
+}
+
+static int ssv6200_ampdu_action(struct ieee80211_hw *hw,
+				struct ieee80211_vif *vif,
+				struct ieee80211_ampdu_params *params)
+{
+	struct ssv_softc *sc = hw->priv;
+	int ret = 0;
+	struct ieee80211_sta *sta = params->sta;
+	enum ieee80211_ampdu_mlme_action action = params->action;
+	u16 tid = params->tid;
+	u16 *ssn = &(params->ssn);
+	u8 buf_size = params->buf_size;
+	if (sta == NULL)
+		return ret;
+#if (!Enable_AMPDU_Rx)
+	if (action == IEEE80211_AMPDU_RX_START
+	    || action == IEEE80211_AMPDU_RX_STOP) {
+		ampdu_db_log("Disable AMPDU_RX for test(1).\n");
+		return -EOPNOTSUPP;
+	}
+#endif
+#if (!Enable_AMPDU_Tx)
+	if (action == IEEE80211_AMPDU_TX_START
+	    || action == IEEE80211_AMPDU_TX_STOP
+	    || action == IEEE80211_AMPDU_TX_OPERATIONAL) {
+		ampdu_db_log("Disable AMPDU_TX for test(1).\n");
+		return -EOPNOTSUPP;
+	}
+#endif
+	if ((action == IEEE80211_AMPDU_RX_START
+	     || action == IEEE80211_AMPDU_RX_STOP)
+	    && (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX))) {
+		ampdu_db_log("Disable AMPDU_RX(2).\n");
+		return -EOPNOTSUPP;
+	}
+	if ((action == IEEE80211_AMPDU_TX_START
+	     || action == IEEE80211_AMPDU_TX_STOP_CONT
+	     || action == IEEE80211_AMPDU_TX_STOP_FLUSH
+	     || action == IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
+	     || action == IEEE80211_AMPDU_TX_OPERATIONAL)
+	    && (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) {
+		ampdu_db_log("Disable AMPDU_TX(2).\n");
+		return -EOPNOTSUPP;
+	}
+	switch (action) {
+	case IEEE80211_AMPDU_RX_START:
+#ifdef WIFI_CERTIFIED
+		if (sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS) {
+			ieee80211_stop_rx_ba_session(vif,
+						     (1 << (sc->ba_tid)),
+						     sc->ba_ra_addr);
+			sc->rx_ba_session_count--;
+		}
+#else
+		if ((sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS)
+		    && (sc->rx_ba_sta != sta)) {
+			ret = -EBUSY;
+			break;
+		} else
+		    if ((sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS)
+			&& (sc->rx_ba_sta == sta)) {
+			ieee80211_stop_rx_ba_session(vif, (1 << (sc->ba_tid)),
+						     sc->ba_ra_addr);
+			sc->rx_ba_session_count--;
+		}
+#endif
+		dev_dbg(sc->dev, "IEEE80211_AMPDU_RX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+		       sta->addr[4], sta->addr[5], tid);
+		sc->rx_ba_session_count++;
+		sc->rx_ba_sta = sta;
+		sc->ba_tid = tid;
+		sc->ba_ssn = *ssn;
+		memcpy(sc->ba_ra_addr, sta->addr, ETH_ALEN);
+		queue_work(sc->config_wq, &sc->set_ampdu_rx_add_work);
+		break;
+	case IEEE80211_AMPDU_RX_STOP:
+		sc->rx_ba_session_count--;
+		if (sc->rx_ba_session_count == 0)
+			sc->rx_ba_sta = NULL;
+		queue_work(sc->config_wq, &sc->set_ampdu_rx_del_work);
+		break;
+	case IEEE80211_AMPDU_TX_START:
+		dev_dbg(sc->dev, "AMPDU_TX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+		       sta->addr[4], sta->addr[5], tid);
+		ssv6200_ampdu_tx_start(tid, sta, hw, ssn);
+		ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+		break;
+	case IEEE80211_AMPDU_TX_STOP_CONT:
+	case IEEE80211_AMPDU_TX_STOP_FLUSH:
+	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
+		dev_dbg(sc->dev, "AMPDU_TX_STOP %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+		       sta->addr[4], sta->addr[5], tid);
+		ssv6200_ampdu_tx_stop(tid, sta, hw);
+		ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+		break;
+	case IEEE80211_AMPDU_TX_OPERATIONAL:
+		dev_dbg(sc->dev, "AMPDU_TX_OPERATIONAL %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+		       sta->addr[4], sta->addr[5], tid);
+		ssv6200_ampdu_tx_operation(tid, sta, hw, buf_size);
+		break;
+	default:
+		ret = -EOPNOTSUPP;
+		break;
+	}
+	return ret;
+}
+
+#ifdef CONFIG_PM
+int ssv6xxx_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan)
+{
+	return 0;
+}
+
+int ssv6xxx_resume(struct ieee80211_hw *hw)
+{
+	return 0;
+}
+#endif
+struct ieee80211_ops ssv6200_ops = {
+	.tx = ssv6200_tx,
+	.start = ssv6200_start,
+	.stop = ssv6200_stop,
+	.add_interface = ssv6200_add_interface,
+	.remove_interface = ssv6200_remove_interface,
+	.change_interface = ssv6200_change_interface,
+	.config = ssv6200_config,
+	.configure_filter = ssv6200_config_filter,
+	.bss_info_changed = ssv6200_bss_info_changed,
+	.sta_add = ssv6200_sta_add,
+	.sta_remove = ssv6200_sta_remove,
+	.sta_notify = ssv6200_sta_notify,
+	.set_key = ssv6200_set_key,
+	.sw_scan_start = ssv6200_sw_scan_start,
+	.sw_scan_complete = ssv6200_sw_scan_complete,
+	.get_tsf = ssv6200_get_tsf,
+	.set_tim = ssv6200_set_tim,
+	.conf_tx = ssv6200_conf_tx,
+	.ampdu_action = ssv6200_ampdu_action,
+#ifdef CONFIG_PM
+	.suspend = ssv6xxx_suspend,
+	.resume = ssv6xxx_resume,
+#endif
+};
+
+int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug)
+{
+	struct ssv_softc *sc = dev;
+	int ac;
+	BUG_ON(hw_txqid > 4);
+	if (hw_txqid == 4)
+		return 0;
+	ac = sc->tx.ac_txqid[hw_txqid];
+	if (fc_en == false) {
+		if (sc->tx.flow_ctrl_status & (1 << ac)) {
+			ieee80211_wake_queue(sc->hw, ac);
+			sc->tx.flow_ctrl_status &= ~(1 << ac);
+		} else {
+		}
+	} else {
+		if ((sc->tx.flow_ctrl_status & (1 << ac)) == 0) {
+			ieee80211_stop_queue(sc->hw, ac);
+			sc->tx.flow_ctrl_status |= (1 << ac);
+		} else {
+		}
+	}
+	return 0;
+}
+
+void ssv6xxx_tx_q_empty_cb(u32 txq_no, void *cb_data)
+{
+	struct ssv_softc *sc = cb_data;
+	BUG_ON(sc == NULL);
+	sc->tx_q_empty = true;
+	smp_mb();
+	wake_up_interruptible(&sc->tx_wait_q);
+}
+
+struct ssv6xxx_b_cca_control {
+	u32 down_level;
+	u32 upper_level;
+	u32 adjust_cca_control;
+	u32 adjust_cca_1;
+};
+struct ssv6xxx_b_cca_control adjust_cci[] = {
+	{0, 43, 0x00162000, 0x20380050},
+	{40, 48, 0x00161000, 0x20380050},
+	{45, 53, 0x00160800, 0x20380050},
+	{50, 63, 0x00160400, 0x20380050},
+	{60, 68, 0x00160200, 0x20380050},
+	{65, 73, 0x00160100, 0x20380050},
+	{70, 128, 0x00000000, 0x20300050},
+};
+
+#define MAX_CCI_LEVEL 128
+static unsigned long last_jiffies = INITIAL_JIFFIES;
+static s32 size = sizeof(adjust_cci) / sizeof(adjust_cci[0]);
+static u32 current_level = MAX_CCI_LEVEL;
+static u32 current_gate = (sizeof(adjust_cci) / sizeof(adjust_cci[0])) - 1;
+void mitigate_cci(struct ssv_softc *sc, u32 input_level)
+{
+	s32 i;
+	if (input_level > MAX_CCI_LEVEL) {
+		dev_dbg(sc->dev, "mitigate_cci input error[%d]!!\n", input_level);
+		return;
+	}
+	if (time_after(jiffies, last_jiffies + msecs_to_jiffies(3000))) {
+		dev_dbg(sc->dev, "jiffies=%lu, input_level=%d\n", jiffies, input_level);
+		last_jiffies = jiffies;
+		if ((input_level >= adjust_cci[current_gate].down_level)
+		    && (input_level <= adjust_cci[current_gate].upper_level)) {
+			current_level = input_level;
+#ifdef DEBUG_MITIGATE_CCI
+			dev_dbg(sc->dev, "Keep the 0xce0020a0[%x] 0xce002008[%x]!!\n",
+			       adjust_cci[current_gate].adjust_cca_control,
+			       adjust_cci[current_gate].adjust_cca_1);
+#endif
+		} else {
+			if (current_level < input_level) {
+				for (i = 0; i < size; i++) {
+					if (input_level <=
+					    adjust_cci[i].upper_level) {
+#ifdef DEBUG_MITIGATE_CCI
+						dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].upper_level=%d, value=%08x\n",
+						     current_gate, input_level,
+						     i,
+						     adjust_cci[i].upper_level,
+						     adjust_cci[i].
+						     adjust_cca_control);
+#endif
+						current_level = input_level;
+						current_gate = i;
+						SMAC_REG_WRITE(sc->sh,
+							       ADR_RX_11B_CCA_CONTROL,
+							       adjust_cci[i].
+							       adjust_cca_control);
+						SMAC_REG_WRITE(sc->sh,
+							       ADR_RX_11B_CCA_1,
+							       adjust_cci[i].
+							       adjust_cca_1);
+#ifdef DEBUG_MITIGATE_CCI
+						dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n",
+						     adjust_cci[current_gate].
+						     adjust_cca_control,
+						     adjust_cci[current_gate].
+						     adjust_cca_1);
+#endif
+						return;
+					}
+				}
+			} else {
+				for (i = (size - 1); i >= 0; i--) {
+					if (input_level >=
+					    adjust_cci[i].down_level) {
+#ifdef DEBUG_MITIGATE_CCI
+						dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].down_level=%d, value=%08x\n",
+						     current_gate, input_level,
+						     i,
+						     adjust_cci[i].down_level,
+						     adjust_cci[i].
+						     adjust_cca_control);
+#endif
+						current_level = input_level;
+						current_gate = i;
+						SMAC_REG_WRITE(sc->sh,
+							       ADR_RX_11B_CCA_CONTROL,
+							       adjust_cci[i].
+							       adjust_cca_control);
+						SMAC_REG_WRITE(sc->sh,
+							       ADR_RX_11B_CCA_1,
+							       adjust_cci[i].
+							       adjust_cca_1);
+#ifdef DEBUG_MITIGATE_CCI
+						dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n",
+						     adjust_cci[current_gate].
+						     adjust_cca_control,
+						     adjust_cci[current_gate].
+						     adjust_cca_1);
+#endif
+						return;
+					}
+				}
+			}
+		}
+	}
+}
+
+#define RSSI_SMOOTHING_SHIFT 5
+#define RSSI_DECIMAL_POINT_SHIFT 6
+static void _proc_data_rx_skb(struct ssv_softc *sc, struct sk_buff *rx_skb)
+{
+	struct ieee80211_rx_status *rxs;
+	struct ieee80211_hdr *hdr;
+	__le16 fc;
+	struct ssv6200_rx_desc *rxdesc;
+	struct ssv6200_rxphy_info_padding *rxphypad;
+	struct ssv6200_rxphy_info *rxphy;
+	struct ieee80211_channel *chan;
+	struct ieee80211_vif *vif = NULL;
+	struct ieee80211_sta *sta = NULL;
+	bool rx_hw_dec = false;
+	bool do_sw_dec = false;
+	struct ssv_sta_priv_data *sta_priv = NULL;
+	struct ssv_vif_priv_data *vif_priv = NULL;
+	SKB_info *skb_info = NULL;
+	u8 is_beacon;
+	u8 is_probe_resp;
+	s32 found = 0;
+#ifdef CONFIG_SSV_SMARTLINK
+	{
+		extern int ksmartlink_smartlink_started(void);
+		void smartlink_nl_send_msg(struct sk_buff *skb);
+		if (unlikely(ksmartlink_smartlink_started())) {
+			skb_pull(rx_skb, SSV6XXX_RX_DESC_LEN);
+			skb_trim(rx_skb, rx_skb->len - sc->sh->rx_pinfo_pad);
+			smartlink_nl_send_msg(rx_skb);
+			return;
+		}
+	}
+#endif
+	rxdesc = (struct ssv6200_rx_desc *)rx_skb->data;
+	rxphy = (struct ssv6200_rxphy_info *)(rx_skb->data + sizeof(*rxdesc));
+	rxphypad =
+	    (struct ssv6200_rxphy_info_padding *)(rx_skb->data + rx_skb->len -
+						  sizeof(struct
+							 ssv6200_rxphy_info_padding));
+	hdr = (struct ieee80211_hdr *)(rx_skb->data + SSV6XXX_RX_DESC_LEN);
+	fc = hdr->frame_control;
+	skb_info = (SKB_info *) rx_skb->head;
+	if (rxdesc->wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) {
+		if ((ieee80211_is_data(hdr->frame_control))
+		    && (!(ieee80211_is_nullfunc(hdr->frame_control)))) {
+			ssv6xxx_rc_rx_data_handler(sc->hw, rx_skb,
+						   rxdesc->rate_idx);
+		}
+	}
+	rxs = IEEE80211_SKB_RXCB(rx_skb);
+	memset(rxs, 0, sizeof(struct ieee80211_rx_status));
+	ssv6xxx_rc_mac8011_rate_idx(sc, rxdesc->rate_idx, rxs);
+
+	rxs->mactime = *((u32 *) & rx_skb->data[28]);
+	chan = sc->hw->conf.chandef.chan;
+	rxs->band = chan->band;
+	rxs->freq = chan->center_freq;
+	rxs->antenna = 1;
+	is_beacon = ieee80211_is_beacon(hdr->frame_control);
+	is_probe_resp = ieee80211_is_probe_resp(hdr->frame_control);
+	if (is_beacon)		//+++
+	{
+		struct ieee80211_mgmt *mgmt_tmp = NULL;
+		mgmt_tmp =
+		    (struct ieee80211_mgmt *)(rx_skb->data +
+					      SSV6XXX_RX_DESC_LEN);
+		mgmt_tmp->u.beacon.timestamp =
+		    cpu_to_le64(ssv6200_get_systime_us());
+	}
+	if (is_probe_resp) {
+		struct ieee80211_mgmt *mgmt_tmp = NULL;
+		mgmt_tmp =
+		    (struct ieee80211_mgmt *)(rx_skb->data +
+					      SSV6XXX_RX_DESC_LEN);
+		mgmt_tmp->u.probe_resp.timestamp =
+		    cpu_to_le64(ssv6200_get_systime_us());
+	}
+
+	if (rxdesc->rate_idx < SSV62XX_G_RATE_INDEX && rxphypad->RSVD == 0) {
+		if (is_beacon || is_probe_resp) {
+			sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+			if (sta) {
+				sta_priv =
+				    (struct ssv_sta_priv_data *)sta->drv_priv;
+#ifdef SSV_RSSI_DEBUG
+				dev_dbg(sc->dev, "b_beacon %02X:%02X:%02X:%02X:%02X:%02X rssi=%d, snr=%d\n",
+				       hdr->addr2[0], hdr->addr2[1],
+				       hdr->addr2[2], hdr->addr2[3],
+				       hdr->addr2[4], hdr->addr2[5],
+				       rxphypad->rpci, rxphypad->snr);
+#endif
+				if (sta_priv->beacon_rssi) {
+					sta_priv->beacon_rssi =
+					    ((rxphypad->
+					      rpci << RSSI_DECIMAL_POINT_SHIFT)
+					     +
+					     ((sta_priv->
+					       beacon_rssi <<
+					       RSSI_SMOOTHING_SHIFT) -
+					      sta_priv->
+					      beacon_rssi)) >>
+					    RSSI_SMOOTHING_SHIFT;
+					rxphypad->rpci =
+					    (sta_priv->
+					     beacon_rssi >>
+					     RSSI_DECIMAL_POINT_SHIFT);
+				} else
+					sta_priv->beacon_rssi =
+					    (rxphypad->
+					     rpci << RSSI_DECIMAL_POINT_SHIFT);
+#ifdef SSV_RSSI_DEBUG
+				dev_dbg(sc->dev, "Beacon smoothing RSSI %d\n", rxphypad->rpci);
+#endif
+				mitigate_cci(sc, rxphypad->rpci);
+			} else {
+				mutex_lock(&sc->mutex);
+				list_for_each_entry(p_rssi_res,
+						    &rssi_res.rssi_list,
+						    rssi_list) {
+					if (!memcmp
+					    (p_rssi_res->bssid, hdr->addr2,
+					     ETH_ALEN)) {
+						{
+							p_rssi_res->rssi =
+							    ((rxphypad->
+							      rpci <<
+							      RSSI_DECIMAL_POINT_SHIFT)
+							     +
+							     ((p_rssi_res->
+							       rssi <<
+							       RSSI_SMOOTHING_SHIFT)
+							      -
+							      p_rssi_res->
+							      rssi)) >>
+							    RSSI_SMOOTHING_SHIFT;
+							rxphypad->rpci =
+							    (p_rssi_res->
+							     rssi >>
+							     RSSI_DECIMAL_POINT_SHIFT);
+						}
+						p_rssi_res->cache_jiffies =
+						    jiffies;
+						found = 1;
+						break;
+					} else {
+						if (p_rssi_res->rssi) {
+							if (time_after
+							    (jiffies,
+							     p_rssi_res->
+							     cache_jiffies +
+							     msecs_to_jiffies
+							     (40000))) {
+								p_rssi_res->
+								    timeout = 1;
+							}
+						}
+					}
+				}
+				if (!found) {
+					p_rssi_res =
+					    kmalloc(sizeof(struct rssi_res_st),
+						    GFP_KERNEL);
+					memcpy(p_rssi_res->bssid, hdr->addr2,
+					       ETH_ALEN);
+					p_rssi_res->cache_jiffies = jiffies;
+					p_rssi_res->rssi =
+					    (rxphypad->
+					     rpci << RSSI_DECIMAL_POINT_SHIFT);
+					p_rssi_res->timeout = 0;
+					INIT_LIST_HEAD(&p_rssi_res->rssi_list);
+					list_add_tail_rcu(&
+							  (p_rssi_res->
+							   rssi_list),
+							  &(rssi_res.
+							    rssi_list));
+				}
+				mutex_unlock(&sc->mutex);
+			}
+			if (rxphypad->rpci > 88)
+				rxphypad->rpci = 88;
+		}
+		if (sc->sh->cfg.rssi_ctl) {
+			rxs->signal = (-rxphypad->rpci) + sc->sh->cfg.rssi_ctl;
+		} else {
+			rxs->signal = (-rxphypad->rpci);
+		}
+	} else if (rxdesc->rate_idx >= SSV62XX_G_RATE_INDEX
+		   && rxphy->service == 0) {
+		if (is_beacon || is_probe_resp) {
+			sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+			if (sta) {
+				sta_priv =
+				    (struct ssv_sta_priv_data *)sta->drv_priv;
+#ifdef SSV_RSSI_DEBUG
+				dev_dbg(sc->dev, "gn_beacon %02X:%02X:%02X:%02X:%02X:%02X rssi=%d, snr=%d\n",
+				     hdr->addr2[0], hdr->addr2[1],
+				     hdr->addr2[2], hdr->addr2[3],
+				     hdr->addr2[4], hdr->addr2[5], rxphy->rpci,
+				     rxphy->snr);
+#endif
+				if (sta_priv->beacon_rssi) {
+					sta_priv->beacon_rssi =
+					    ((rxphy->
+					      rpci << RSSI_DECIMAL_POINT_SHIFT)
+					     +
+					     ((sta_priv->
+					       beacon_rssi <<
+					       RSSI_SMOOTHING_SHIFT) -
+					      sta_priv->
+					      beacon_rssi)) >>
+					    RSSI_SMOOTHING_SHIFT;
+					rxphy->rpci =
+					    (sta_priv->
+					     beacon_rssi >>
+					     RSSI_DECIMAL_POINT_SHIFT);
+				} else
+					sta_priv->beacon_rssi =
+					    (rxphy->
+					     rpci << RSSI_DECIMAL_POINT_SHIFT);
+#ifdef SSV_RSSI_DEBUG
+				dev_dbg(sc->dev, "Beacon smoothing RSSI %d\n", rxphy->rpci);
+#endif
+			}
+			if (rxphy->rpci > 88)
+				rxphy->rpci = 88;
+		}
+		if (sc->sh->cfg.rssi_ctl) {
+			rxs->signal = (-rxphy->rpci) + sc->sh->cfg.rssi_ctl;
+		} else {
+			rxs->signal = (-rxphy->rpci);
+		}
+	} else {
+#ifdef SSV_RSSI_DEBUG
+		dev_dbg(sc->dev, "########unicast: %d, b_rssi/snr: %d/%d, gn_rssi/snr: %d/%d, rate:%d###############\n",
+		     rxdesc->unicast, (-rxphy->rpci), rxphy->snr,
+		     (-rxphypad->rpci), rxphypad->snr, rxdesc->rate_idx);
+		dev_dbg(sc->dev, "RSSI, %d, rate_idx, %d\n", rxs->signal,
+		       rxdesc->rate_idx);
+		dev_dbg(sc->dev, "rxdesc->RxResult = %x,rxdesc->wsid = %d\n",
+		       rxdesc->RxResult, rxdesc->wsid);
+#endif
+		sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+		if (sta) {
+			sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+			rxs->signal =
+			    -(sta_priv->
+			      beacon_rssi >> RSSI_DECIMAL_POINT_SHIFT);
+		}
+#ifdef SSV_RSSI_DEBUG
+		dev_dbg(sc->dev, "Others signal %d\n", rxs->signal);
+#endif
+	}
+//    rxs->flag = RX_FLAG_MACTIME_START;          //+++
+	rxs->rx_flags = 0;
+	if (rxphy->aggregate)
+		rxs->flag |= RX_FLAG_NO_SIGNAL_VAL;
+	sc->hw_mng_used = rxdesc->mng_used;
+	if ((ieee80211_is_data(fc) || ieee80211_is_data_qos(fc))
+	    && ieee80211_has_protected(fc)) {
+		sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+		if (sta == NULL)
+			goto drop_rx;
+		sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+		vif = sta_priv->sta_info->vif;
+		if (vif == NULL)
+			goto drop_rx;
+		if (is_broadcast_ether_addr(hdr->addr1)) {
+			vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+			rx_hw_dec = vif_priv->has_hw_decrypt;
+			do_sw_dec = vif_priv->need_sw_decrypt;
+		} else {
+			rx_hw_dec = sta_priv->has_hw_decrypt;
+			do_sw_dec = sta_priv->need_sw_decrypt;
+		}
+	}
+	skb_pull(rx_skb, SSV6XXX_RX_DESC_LEN);
+	skb_trim(rx_skb, rx_skb->len - sc->sh->rx_pinfo_pad);
+#ifdef CONFIG_P2P_NOA
+	if (is_beacon)
+		ssv6xxx_noa_detect(sc, hdr, rx_skb->len);
+#endif
+	if (rx_hw_dec || do_sw_dec) {
+		hdr = (struct ieee80211_hdr *)rx_skb->data;
+		rxs = IEEE80211_SKB_RXCB(rx_skb);
+		hdr->frame_control =
+		    hdr->
+		    frame_control & ~(cpu_to_le16(IEEE80211_FCTL_PROTECTED));
+		rxs->flag |= (RX_FLAG_DECRYPTED | RX_FLAG_IV_STRIPPED);
+	}
+#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_RX_DATA)
+	local_bh_disable();
+	ieee80211_rx(sc->hw, rx_skb);
+	local_bh_enable();
+#else
+	ieee80211_rx_irqsafe(sc->hw, rx_skb);
+#endif
+	return;
+ drop_rx:
+	dev_kfree_skb_any(rx_skb);
+}
+
+#ifdef IRQ_PROC_RX_DATA
+static struct sk_buff *_proc_rx_skb(struct ssv_softc *sc,
+				    struct sk_buff *rx_skb)
+{
+	struct ieee80211_hdr *hdr =
+	    (struct ieee80211_hdr *)(rx_skb->data + SSV6XXX_RX_DESC_LEN);
+	struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)rx_skb->data;
+	if (ieee80211_is_back(hdr->frame_control)
+	    || (rxdesc->c_type == HOST_EVENT))
+		return rx_skb;
+	_proc_data_rx_skb(sc, rx_skb);
+	return NULL;
+}
+#endif
+void _process_rx_q(struct ssv_softc *sc, struct sk_buff_head *rx_q,
+		   spinlock_t * rx_q_lock)
+{
+	struct sk_buff *skb;
+	struct ieee80211_hdr *hdr;
+	struct ssv6200_rx_desc *rxdesc;
+	unsigned long flags = 0;
+#ifdef USE_FLUSH_RETRY
+	bool has_ba_processed = false;
+#endif
+	while (1) {
+		if (rx_q_lock != NULL) {
+			spin_lock_irqsave(rx_q_lock, flags);
+			skb = __skb_dequeue(rx_q);
+		} else
+			skb = skb_dequeue(rx_q);
+		if (!skb) {
+			if (rx_q_lock != NULL)
+				spin_unlock_irqrestore(rx_q_lock, flags);
+			break;
+		}
+		sc->rx.rxq_count--;
+		if (rx_q_lock != NULL)
+			spin_unlock_irqrestore(rx_q_lock, flags);
+		rxdesc = (struct ssv6200_rx_desc *)skb->data;
+		if (rxdesc->c_type == HOST_EVENT) {
+			struct cfg_host_event *h_evt =
+			    (struct cfg_host_event *)rxdesc;
+			if (h_evt->h_event == SOC_EVT_NO_BA) {
+				ssv6200_ampdu_no_BA_handler(sc->hw, skb);
+#ifdef USE_FLUSH_RETRY
+				has_ba_processed = true;
+#endif
+			} else if (h_evt->h_event == SOC_EVT_RC_MPDU_REPORT) {
+				skb_queue_tail(&sc->rc_report_queue, skb);
+				if (sc->rc_sample_sechedule == 0)
+					queue_work(sc->rc_sample_workqueue,
+						   &sc->rc_sample_work);
+			} else if (h_evt->h_event == SOC_EVT_SDIO_TEST_COMMAND) {
+				if (h_evt->evt_seq_no == 0) {
+					dev_dbg(sc->dev, "SOC_EVT_SDIO_TEST_COMMAND\n");
+					sc->sdio_rx_evt_size = h_evt->len;
+					sc->sdio_throughput_timestamp = jiffies;
+				} else {
+					sc->sdio_rx_evt_size += h_evt->len;
+					if (time_after
+					    (jiffies,
+					     sc->sdio_throughput_timestamp +
+					     msecs_to_jiffies(1000))) {
+						dev_dbg(sc->dev, "data[%ld] SDIO RX throughput %ld Kbps\n",
+						     sc->sdio_rx_evt_size,
+						     (sc->
+						      sdio_rx_evt_size << 3) /
+						     jiffies_to_msecs(jiffies -
+								      sc->
+								      sdio_throughput_timestamp));
+						sc->sdio_throughput_timestamp =
+						    jiffies;
+						sc->sdio_rx_evt_size = 0;
+					}
+				}
+				dev_kfree_skb_any(skb);
+			} else if (h_evt->h_event == SOC_EVT_WATCHDOG_TRIGGER) {
+				dev_kfree_skb_any(skb);
+//              if(sc->watchdog_flag != WD_SLEEP)     //+++
+				sc->watchdog_flag = WD_KICKED;
+			} else if (h_evt->h_event == SOC_EVT_RESET_HOST) {
+				dev_kfree_skb_any(skb);
+				if ((sc->ap_vif == NULL)
+				    || !(sc->sh->cfg.ignore_reset_in_ap)) {
+					ssv6xxx_restart_hw(sc);
+				} else {
+					dev_warn(sc->dev,
+						 "Reset event ignored.\n");
+				}
+			}
+#ifdef CONFIG_P2P_NOA
+			else if (h_evt->h_event == SOC_EVT_NOA) {
+				ssv6xxx_process_noa_event(sc, skb);
+				dev_kfree_skb_any(skb);
+			}
+#endif
+			else if (h_evt->h_event == SOC_EVT_SDIO_TXTPUT_RESULT) {
+				dev_dbg(sc->dev, "data SDIO TX throughput %d Kbps\n",
+				       h_evt->evt_seq_no);
+				dev_kfree_skb_any(skb);
+			} else if (h_evt->h_event == SOC_EVT_TXLOOPBK_RESULT) {
+				if (h_evt->evt_seq_no == SSV6XXX_STATE_OK) {
+					dev_dbg(sc->dev, "FW TX LOOPBACK OK\n");
+					sc->iq_cali_done = IQ_CALI_OK;
+				} else {
+					dev_dbg(sc->dev, "FW TX LOOPBACK FAILED\n");
+					sc->iq_cali_done = IQ_CALI_FAILED;
+				}
+				dev_kfree_skb_any(skb);
+				wake_up_interruptible(&sc->fw_wait_q);
+			} else {
+				dev_warn(sc->dev, "Unkown event %d received\n",
+					 h_evt->h_event);
+				dev_kfree_skb_any(skb);
+			}
+			continue;
+		}
+		hdr = (struct ieee80211_hdr *)(skb->data + SSV6XXX_RX_DESC_LEN);
+		if (ieee80211_is_back(hdr->frame_control)) {
+			ssv6200_ampdu_BA_handler(sc->hw, skb);
+#ifdef USE_FLUSH_RETRY
+			has_ba_processed = true;
+#endif
+			continue;
+		}
+		_proc_data_rx_skb(sc, skb);
+	}
+#ifdef USE_FLUSH_RETRY
+	if (has_ba_processed) {
+		ssv6xxx_ampdu_postprocess_BA(sc->hw);
+	}
+#endif
+}
+
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args)
+#else
+int ssv6200_rx(struct sk_buff *rx_skb, void *args)
+#endif
+{
+	struct ssv_softc *sc = args;
+#ifdef IRQ_PROC_RX_DATA
+	struct sk_buff *skb;
+	skb = _proc_rx_skb(sc, rx_skb);
+	if (skb == NULL)
+		return 0;
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+	{
+		unsigned long flags;
+		spin_lock_irqsave(&sc->rx_skb_q.lock, flags);
+		while (skb_queue_len(rx_skb_q))
+			__skb_queue_tail(&sc->rx_skb_q,
+					 __skb_dequeue(rx_skb_q));
+		spin_unlock_irqrestore(&sc->rx_skb_q.lock, flags);
+	}
+#else
+	skb_queue_tail(&sc->rx_skb_q, rx_skb);
+#endif
+	wake_up_interruptible(&sc->rx_wait_q);
+	return 0;
+}
+
+struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb(struct ssv_softc *sc,
+						 struct sk_buff *skb)
+{
+	struct ieee80211_hdr *hdr =
+	    (struct ieee80211_hdr *)(skb->data + SSV6XXX_RX_DESC_LEN);
+	struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)skb->data;;
+	if ((rxdesc->wsid >= 0) && (rxdesc->wsid < SSV_NUM_STA))
+		return sc->sta_info[rxdesc->wsid].sta;
+	else
+		return ssv6xxx_find_sta_by_addr(sc, hdr->addr2);
+}
+
+struct ieee80211_sta *ssv6xxx_find_sta_by_addr(struct ssv_softc *sc, u8 addr[6])
+{
+	struct ieee80211_sta *sta;
+	int i;
+	for (i = 0; i < SSV6200_MAX_VIF; i++) {
+		if (sc->vif_info[i].vif == NULL)
+			continue;
+		sta = ieee80211_find_sta(sc->vif_info[i].vif, addr);
+		if (sta != NULL)
+			return sta;
+	}
+	return NULL;
+}
+
+void ssv6xxx_foreach_sta(struct ssv_softc *sc,
+			 void (*sta_func)(struct ssv_softc *,
+					  struct ssv_sta_info *, void *),
+			 void *param)
+{
+	int i;
+	BUG_ON(sta_func == NULL);
+	for (i = 0; i < SSV_NUM_STA; i++) {
+		if ((sc->sta_info[i].s_flags & STA_FLAG_VALID) == 0)
+			continue;
+		(*sta_func) (sc, &sc->sta_info[i], param);
+	}
+}
+
+void ssv6xxx_foreach_vif_sta(struct ssv_softc *sc,
+			     struct ssv_vif_info *vif_info,
+			     void (*sta_func)(struct ssv_softc *,
+					      struct ssv_vif_info *,
+					      struct ssv_sta_info *,
+					      void *), void *param)
+{
+	struct ssv_vif_priv_data *vif_priv;
+	struct ssv_sta_priv_data *sta_priv_iter;
+	BUG_ON(vif_info == NULL);
+	BUG_ON((size_t)vif_info < 0x30000);
+	vif_priv = (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+	BUG_ON((size_t)vif_info->vif < 0x30000);
+	BUG_ON((size_t)vif_priv < 0x30000);
+	list_for_each_entry(sta_priv_iter, &vif_priv->sta_list, list) {
+		BUG_ON(sta_priv_iter == NULL);
+		BUG_ON((size_t)sta_priv_iter < 0x30000);
+		BUG_ON(sta_priv_iter->sta_info == NULL);
+		BUG_ON((size_t)sta_priv_iter->sta_info < 0x30000);
+		if ((sta_priv_iter->sta_info->s_flags & STA_FLAG_VALID) == 0)
+			continue;
+		(*sta_func) (sc, vif_info, sta_priv_iter->sta_info, param);
+	}
+}
+
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ssize_t ssv6xxx_tx_queue_status_dump(struct ssv_softc *sc, char *status_buf,
+				     ssize_t length)
+{
+	ssize_t buf_size = length;
+	ssize_t prt_size;
+	prt_size =
+	    snprintf(status_buf, buf_size, "\nSMAC driver queue status:.\n");
+	status_buf += prt_size;
+	buf_size -= prt_size;
+	prt_size = snprintf(status_buf, buf_size, "\tTX queue: %d\n",
+			    skb_queue_len(&sc->tx_skb_q));
+	status_buf += prt_size;
+	buf_size -= prt_size;
+	prt_size = snprintf(status_buf, buf_size, "\tMax TX queue: %d\n",
+			    sc->max_tx_skb_q_len);
+	status_buf += prt_size;
+	buf_size -= prt_size;
+	return (length - buf_size);
+}
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/dev.h b/drivers/net/wireless/ssv6051/smac/dev.h
new file mode 100644
index 00000000000..0a6357624b1
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/dev.h
@@ -0,0 +1,445 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DEV_H_
+#define _DEV_H_
+#include <linux/version.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <net/mac80211.h>
+#include "ampdu.h"
+#include "ssv_rc_common.h"
+#include "drv_comm.h"
+#include "sec.h"
+#include "p2p.h"
+#include <linux/kthread.h>
+#define SSV6200_MAX_HW_MAC_ADDR 2
+#define SSV6200_MAX_VIF 2
+#define SSV6200_RX_BA_MAX_SESSIONS 1
+#define SSV6200_OPMODE_STA 0
+#define SSV6200_OPMODE_AP 1
+#define SSV6200_OPMODE_IBSS 2
+#define SSV6200_OPMODE_WDS 3
+#define SSV6200_USE_HW_WSID(_sta_idx) ((_sta_idx == 0) || (_sta_idx == 1))
+#define HW_MAX_RATE_TRIES 7
+#define MAC_DECITBL1_SIZE 16
+#define MAC_DECITBL2_SIZE 9
+#define RX_11B_CCA_IN_SCAN 0x20230050
+//#define WATCHDOG_TIMEOUT (10*HZ)
+#define WATCHDOG_TIMEOUT (99999*HZ)
+extern u16 generic_deci_tbl[];
+#define ap_deci_tbl generic_deci_tbl
+#define sta_deci_tbl generic_deci_tbl
+#define HT_SIGNAL_EXT 6
+#define HT_SIFS_TIME 10
+#define BITS_PER_BYTE 8
+#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
+#define ACK_LEN (14)
+#define BA_LEN (32)
+#define RTS_LEN (20)
+#define CTS_LEN (14)
+#define L_STF 8
+#define L_LTF 8
+#define L_SIG 4
+#define HT_SIG 8
+#define HT_STF 4
+#define HT_LTF(_ns) (4 * (_ns))
+#define SYMBOL_TIME(_ns) ((_ns) << 2)
+#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5)
+#define CCK_SIFS_TIME 10
+#define CCK_PREAMBLE_BITS 144
+#define CCK_PLCP_BITS 48
+#define OFDM_SIFS_TIME 16
+#define OFDM_PREAMBLE_TIME 20
+#define OFDM_PLCP_BITS 22
+#define OFDM_SYMBOL_TIME 4
+#define WMM_AC_VO 0
+#define WMM_AC_VI 1
+#define WMM_AC_BE 2
+#define WMM_AC_BK 3
+#define WMM_NUM_AC 4
+#define WMM_TID_NUM 8
+#define TXQ_EDCA_0 0x01
+#define TXQ_EDCA_1 0x02
+#define TXQ_EDCA_2 0x04
+#define TXQ_EDCA_3 0x08
+#define TXQ_MGMT 0x10
+#define IS_SSV_HT(dsc) ((dsc)->rate_idx >= 15)
+#define IS_SSV_SHORT_GI(dsc) ((dsc)->rate_idx>=23 && (dsc)->rate_idx<=30)
+#define IS_SSV_HT_GF(dsc) ((dsc)->rate_idx >= 31)
+#define IS_SSV_SHORT_PRE(dsc) ((dsc)->rate_idx>=4 && (dsc)->rate_idx<=14)
+#define SMAC_REG_WRITE(_s,_r,_v) \
+        (_s)->hci.hci_ops->hci_write_word(_r,_v)
+#define SMAC_REG_READ(_s,_r,_v) \
+        (_s)->hci.hci_ops->hci_read_word(_r, _v)
+#define SMAC_LOAD_FW(_s,_r,_v) \
+        (_s)->hci.hci_ops->hci_load_fw(_r, _v)
+#define SMAC_IFC_RESET(_s) (_s)->hci.hci_ops->hci_interface_reset()
+#define SMAC_REG_CONFIRM(_s,_r,_v) \
+{ \
+    u32 _regval; \
+    SMAC_REG_READ(_s, _r, &_regval); \
+    if (_regval != (_v)) { \
+        printk("ERROR!!Please check interface!\n"); \
+        printk("[0x%08x]: 0x%08x!=0x%08x\n", \
+        (_r), (_v), _regval); \
+        printk("SOS!SOS!\n"); \
+        return -1; \
+    } \
+}
+#define SMAC_REG_SET_BITS(_sh,_reg,_set,_clr) \
+({ \
+    int ret; \
+    u32 _regval; \
+    ret = SMAC_REG_READ(_sh, _reg, &_regval); \
+    _regval &= ~(_clr); \
+    _regval |= (_set); \
+    if (ret == 0) \
+        ret = SMAC_REG_WRITE(_sh, _reg, _regval); \
+    ret; \
+})
+#define HCI_START(_sh) \
+    (_sh)->hci.hci_ops->hci_start()
+#define HCI_STOP(_sh) \
+    (_sh)->hci.hci_ops->hci_stop()
+#define HCI_SEND(_sh,_sk,_q) \
+    (_sh)->hci.hci_ops->hci_tx(_sk, _q, 0)
+#define HCI_PAUSE(_sh,_mk) \
+    (_sh)->hci.hci_ops->hci_tx_pause(_mk)
+#define HCI_RESUME(_sh,_mk) \
+    (_sh)->hci.hci_ops->hci_tx_resume(_mk)
+#define HCI_TXQ_FLUSH(_sh,_mk) \
+    (_sh)->hci.hci_ops->hci_txq_flush(_mk)
+#define HCI_TXQ_FLUSH_BY_STA(_sh,_aid) \
+  (_sh)->hci.hci_ops->hci_txq_flush_by_sta(_aid)
+#define HCI_TXQ_EMPTY(_sh,_txqid) \
+  (_sh)->hci.hci_ops->hci_txq_empty(_txqid)
+#define HCI_WAKEUP_PMU(_sh) \
+    (_sh)->hci.hci_ops->hci_pmu_wakeup()
+#define HCI_SEND_CMD(_sh,_sk) \
+        (_sh)->hci.hci_ops->hci_send_cmd(_sk)
+#define SSV6XXX_SET_HW_TABLE(sh_,tbl_) \
+({ \
+    int ret = 0; \
+    u32 i=0; \
+    for(; i<sizeof(tbl_)/sizeof(struct ssv6xxx_dev_table); i++) { \
+        ret = SMAC_REG_WRITE(sh_, tbl_[i].address, tbl_[i].data); \
+        if (ret) break; \
+    } \
+    ret; \
+})
+#define SSV6XXX_USE_HW_DECRYPT(_priv) (_priv->has_hw_decrypt)
+#define SSV6XXX_USE_SW_DECRYPT(_priv) (SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) || SSV6XXX_USE_MAC80211_DECRYPT(_priv))
+#define SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) (_priv->need_sw_decrypt)
+#define SSV6XXX_USE_MAC80211_DECRYPT(_priv) (_priv->use_mac80211_decrypt)
+struct ssv_softc;
+#ifdef CONFIG_P2P_NOA
+struct ssv_p2p_noa;
+#endif
+#define SSV6200_HT_TX_STREAMS 1
+#define SSV6200_HT_RX_STREAMS 1
+#define SSV6200_RX_HIGHEST_RATE 72
+enum PWRSV_STATUS {
+	PWRSV_DISABLE,
+	PWRSV_ENABLE,
+	PWRSV_PREPARE,
+};
+struct rssi_res_st {
+	struct list_head rssi_list;
+	unsigned long cache_jiffies;
+	s32 rssi;
+	s32 timeout;
+	u8 bssid[ETH_ALEN];
+};
+struct ssv_hw {
+	struct ssv_softc *sc;
+	struct ssv6xxx_platform_data *priv;
+	struct ssv6xxx_hci_info hci;
+	char chip_id[24];
+	u64 chip_tag;
+	u32 tx_desc_len;
+	u32 rx_desc_len;
+	u32 rx_pinfo_pad;
+	u32 tx_page_available;
+	u32 ampdu_divider;
+	u8 page_count[SSV6200_ID_NUMBER];
+	u32 hw_buf_ptr[SSV_RC_MAX_STA];
+	u32 hw_sec_key[SSV_RC_MAX_STA];
+	u32 hw_pinfo;
+	struct ssv6xxx_cfg cfg;
+	u32 n_addresses;
+	struct mac_address maddr[SSV6200_MAX_HW_MAC_ADDR];
+	u8 ipd_channel_touch;
+	struct ssv6xxx_ch_cfg *p_ch_cfg;
+	u32 ch_cfg_size;
+};
+struct ssv_tx {
+	u16 seq_no;
+	int hw_txqid[WMM_NUM_AC];
+	int ac_txqid[WMM_NUM_AC];
+	u32 flow_ctrl_status;
+	u32 tx_pkt[SSV_HW_TXQ_NUM];
+	u32 tx_frag[SSV_HW_TXQ_NUM];
+	struct list_head ampdu_tx_que;
+	spinlock_t ampdu_tx_que_lock;
+	u16 ampdu_tx_group_id;
+};
+struct ssv_rx {
+	struct sk_buff *rx_buf;
+	spinlock_t rxq_lock;
+	struct sk_buff_head rxq_head;
+	u32 rxq_count;
+};
+#define SSV6XXX_GET_STA_INFO(_sc,_s) \
+    &(_sc)->sta_info[((struct ssv_sta_priv_data *)((_s)->drv_priv))->sta_idx]
+#define STA_FLAG_VALID 0x00001
+#define STA_FLAG_QOS 0x00002
+#define STA_FLAG_AMPDU 0x00004
+#define STA_FLAG_ENCRYPT 0x00008
+struct ssv_sta_info {
+	u16 aid;
+	u16 s_flags;
+	int hw_wsid;
+	struct ieee80211_sta *sta;
+	struct ieee80211_vif *vif;
+	bool sleeping;
+	bool tim_set;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct dentry *debugfs_dir;
+#endif
+};
+struct ssv_vif_info {
+	struct ieee80211_vif *vif;
+	struct ssv_vif_priv_data *vif_priv;
+	enum nl80211_iftype if_type;
+	struct ssv6xxx_hw_sec sramKey;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct dentry *debugfs_dir;
+#endif
+};
+struct ssv_sta_priv_data {
+	int sta_idx;
+	int rc_idx;
+	int rx_data_rate;
+	struct ssv_sta_info *sta_info;
+	struct list_head list;
+	u32 ampdu_mib_total_BA_counter;
+	AMPDU_TID ampdu_tid[WMM_TID_NUM];
+	bool has_hw_encrypt;
+	bool need_sw_encrypt;
+	bool has_hw_decrypt;
+	bool need_sw_decrypt;
+	bool use_mac80211_decrypt;
+	u8 group_key_idx;
+	u32 beacon_rssi;
+};
+struct ssv_vif_priv_data {
+	int vif_idx;
+	struct list_head sta_list;
+	u32 sta_asleep_mask;
+	u32 pair_cipher;
+	u32 group_cipher;
+	bool is_security_valid;
+	bool has_hw_encrypt;
+	bool need_sw_encrypt;
+	bool has_hw_decrypt;
+	bool need_sw_decrypt;
+	bool use_mac80211_decrypt;
+	bool force_sw_encrypt;
+	u8 group_key_idx;
+};
+#define SC_OP_INVALID 0x00000001
+#define SC_OP_HW_RESET 0x00000002
+#define SC_OP_OFFCHAN 0x00000004
+#define SC_OP_FIXED_RATE 0x00000008
+#define SC_OP_SHORT_PREAMBLE 0x00000010
+struct ssv6xxx_beacon_info {
+	u32 pubf_addr;
+	u16 len;
+	u8 tim_offset;
+	u8 tim_cnt;
+};
+#define SSV6200_MAX_BCAST_QUEUE_LEN 16
+struct ssv6xxx_bcast_txq {
+	spinlock_t txq_lock;
+	struct sk_buff_head qhead;
+	int cur_qsize;
+};
+#ifdef DEBUG_AMPDU_FLUSH
+typedef struct AMPDU_TID_st AMPDU_TID;
+#define MAX_TID (24)
+#endif
+struct ssv_softc {
+	struct ieee80211_hw *hw;
+	struct device *dev;
+	u32 restart_counter;
+	bool force_triger_reset;
+	unsigned long sdio_throughput_timestamp;
+	unsigned long sdio_rx_evt_size;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
+	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
+#else
+	struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
+#endif
+	struct ieee80211_channel *cur_channel;
+	u16 hw_chan;
+	struct mutex mutex;
+	struct ssv_hw *sh;
+	struct ssv_tx tx;
+	struct ssv_rx rx;
+	struct ssv_vif_info vif_info[SSV_NUM_VIF];
+	struct ssv_sta_info sta_info[SSV_NUM_STA];
+	struct ieee80211_vif *ap_vif;
+	u8 nvif;
+	u32 sc_flags;
+	void *rc;
+	int max_rate_idx;
+	struct workqueue_struct *rc_sample_workqueue;
+	struct sk_buff_head rc_report_queue;
+	struct work_struct rc_sample_work;
+#ifdef DEBUG_AMPDU_FLUSH
+	struct AMPDU_TID_st *tid[MAX_TID];
+#endif
+	u16 rc_sample_sechedule;
+	u16 *mac_deci_tbl;
+	struct workqueue_struct *config_wq;
+	bool bq4_dtim;
+	struct work_struct set_tim_work;
+	u8 enable_beacon;
+	u8 beacon_interval;
+	u8 beacon_dtim_cnt;
+	u8 beacon_usage;
+	struct ssv6xxx_beacon_info beacon_info[2];
+	struct sk_buff *beacon_buf;
+	struct work_struct bcast_start_work;
+	struct delayed_work bcast_stop_work;
+	struct delayed_work bcast_tx_work;
+	struct delayed_work thermal_monitor_work;
+	struct workqueue_struct *thermal_wq;
+	int is_sar_enabled;
+	bool aid0_bit_set;
+	u8 hw_mng_used;
+	struct ssv6xxx_bcast_txq bcast_txq;
+	int bcast_interval;
+	u8 bssid[6];
+	struct mutex mem_mutex;
+	spinlock_t ps_state_lock;
+	u8 hw_wsid_bit;
+	int rx_ba_session_count;
+	struct ieee80211_sta *rx_ba_sta;
+	u8 rx_ba_bitmap;
+	u8 ba_ra_addr[ETH_ALEN];
+	u16 ba_tid;
+	u16 ba_ssn;
+	struct work_struct set_ampdu_rx_add_work;
+	struct work_struct set_ampdu_rx_del_work;
+	bool isAssoc;
+	u16 channel_center_freq;
+	bool bScanning;
+	int ps_status;
+	u16 ps_aid;
+	u16 tx_wait_q_woken;
+	wait_queue_head_t tx_wait_q;
+	struct sk_buff_head tx_skb_q;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	u32 max_tx_skb_q_len;
+#endif
+	struct task_struct *tx_task;
+	bool tx_q_empty;
+	struct sk_buff_head tx_done_q;
+	u16 rx_wait_q_woken;
+	wait_queue_head_t rx_wait_q;
+	struct sk_buff_head rx_skb_q;
+	struct task_struct *rx_task;
+	bool dbg_rx_frame;
+	bool dbg_tx_frame;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct dentry *debugfs_dir;
+#endif
+#ifdef CONFIG_P2P_NOA
+	struct ssv_p2p_noa p2p_noa;
+#endif
+	struct timer_list watchdog_timeout;
+	u32 watchdog_flag;
+	wait_queue_head_t fw_wait_q;
+	u32 iq_cali_done;
+	u32 sr_bhvr;
+};
+enum {
+	IQ_CALI_RUNNING,
+	IQ_CALI_OK,
+	IQ_CALI_FAILED
+};
+enum {
+	WD_SLEEP,
+	WD_BARKING,
+	WD_KICKED,
+	WD_MAX
+};
+void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args);
+void ssv6200_rx_process(struct work_struct *work);
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args);
+#else
+int ssv6200_rx(struct sk_buff *rx_skb, void *args);
+#endif
+void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args);
+void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args);
+int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug);
+void ssv6xxx_tx_q_empty_cb(u32 txq_no, void *);
+int ssv6xxx_rf_disable(struct ssv_hw *sh);
+int ssv6xxx_rf_enable(struct ssv_hw *sh);
+int ssv6xxx_set_channel(struct ssv_softc *sc, int ch);
+#ifdef CONFIG_SSV_SMARTLINK
+int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch);
+int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept);
+int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept);
+#endif
+int ssv6xxx_tx_task(void *data);
+int ssv6xxx_rx_task(void *data);
+u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type);
+bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr);
+void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb);
+void ssv6xxx_update_txinfo(struct ssv_softc *sc, struct sk_buff *skb);
+int ssv6xxx_update_decision_table(struct ssv_softc *sc);
+void ssv6xxx_ps_callback_func(unsigned long data);
+void ssv6xxx_enable_ps(struct ssv_softc *sc);
+void ssv6xxx_disable_ps(struct ssv_softc *sc);
+int ssv6xxx_watchdog_controller(struct ssv_hw *sh, u8 flag);
+int ssv6xxx_skb_encrypt(struct sk_buff *mpdu, struct ssv_softc *sc);
+int ssv6xxx_skb_decrypt(struct sk_buff *mpdu, struct ieee80211_sta *sta,
+			struct ssv_softc *sc);
+void ssv6200_sync_hw_key_sequence(struct ssv_softc *sc,
+				  struct ssv_sta_info *sta_info, bool bWrite);
+struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb(struct ssv_softc *sc,
+						 struct sk_buff *skb);
+struct ieee80211_sta *ssv6xxx_find_sta_by_addr(struct ssv_softc *sc,
+					       u8 addr[6]);
+void ssv6xxx_foreach_sta(struct ssv_softc *sc,
+			 void (*sta_func)(struct ssv_softc *,
+					  struct ssv_sta_info *, void *),
+			 void *param);
+void ssv6xxx_foreach_vif_sta(struct ssv_softc *sc,
+			     struct ssv_vif_info *vif_info,
+			     void (*sta_func)(struct ssv_softc *,
+					      struct ssv_vif_info *,
+					      struct ssv_sta_info *, void *),
+			     void *param);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ssize_t ssv6xxx_tx_queue_status_dump(struct ssv_softc *sc, char *status_buf,
+				     ssize_t buf_size);
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/dev_tbl.h b/drivers/net/wireless/ssv6051/smac/dev_tbl.h
new file mode 100644
index 00000000000..5c49d0bde6a
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/dev_tbl.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DEV_TBL_H_
+#define _DEV_TBL_H_
+#include "ssv6200_configuration.h"
+#include "drv_comm.h"
+struct ssv6xxx_dev_table {
+	u32 address;
+	u32 data;
+};
+#define ssv6200_phy_tbl phy_setting
+#define ssv6200_rf_tbl asic_rf_setting
+#define ACTION_DO_NOTHING 0
+#define ACTION_UPDATE_NAV 1
+#define ACTION_RESET_NAV 2
+#define ACTION_SIGNAL_ACK 3
+#define FRAME_ACCEPT 0
+#define FRAME_DROP 1
+#define SET_DEC_TBL(_type,_mask,_action,_drop) \
+    (_type<<9| \
+    _mask <<3| \
+    _action<<1| \
+    _drop)
+u16 generic_deci_tbl[] = {
+	SET_DEC_TBL(0x1e, 0x3e, ACTION_RESET_NAV, FRAME_DROP),
+	SET_DEC_TBL(0x18, 0x3e, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+	SET_DEC_TBL(0x1a, 0x3f, ACTION_DO_NOTHING, FRAME_ACCEPT),
+	SET_DEC_TBL(0x10, 0x38, ACTION_DO_NOTHING, FRAME_DROP),
+	0,
+	0,
+	0,
+	SET_DEC_TBL(0x05, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+	SET_DEC_TBL(0x0b, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+	SET_DEC_TBL(0x01, 0x3d, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+	SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_ACCEPT),
+	SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+	SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_DROP),
+	SET_DEC_TBL(0x00, 0x00, ACTION_UPDATE_NAV, FRAME_DROP),
+	SET_DEC_TBL(0x00, 0x00, ACTION_RESET_NAV, FRAME_DROP),
+	SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_DROP),
+	0x2008,
+	0x1001,
+	0x0400,
+	0x0400,
+	0x2000,
+	0x800E,
+	0x0800,
+	0x0B88,
+	0x0800,
+};
+
+#define SET_PHY_INFO(_ctsdur,_ba_rate_idx,_ack_rate_idx,_llength_idx,_llength_enable) \
+         (_ctsdur<<16| \
+         _ba_rate_idx <<10| \
+         _ack_rate_idx<<4| \
+         _llength_idx<<1| \
+         _llength_enable)
+#define SET_PHY_L_LENGTH(_l_ba,_l_rts,_l_cts_ack) (_l_ba<<12|_l_rts<<6 |_l_cts_ack)
+static u32 phy_info_6051z[] = {
+	0x18000000, 0x18000100, 0x18000200, 0x18000300, 0x18000140,
+	0x18000240, 0x18000340, 0x0C000001, 0x0C000101, 0x0C000201,
+	0x0C000301, 0x18000401, 0x18000501, 0x18000601, 0x18000701,
+	0x0C030002, 0x0C030102, 0x0C030202, 0x18030302, 0x18030402,
+	0x18030502, 0x18030602, 0x1C030702, 0x0C030082, 0x0C030182,
+	0x0C030282, 0x18030382, 0x18030482, 0x18030582, 0x18030682,
+	0x1C030782, 0x0C030042, 0x0C030142, 0x0C030242, 0x18030342,
+	0x18030442, 0x18030542, 0x18030642, 0x1C030742
+};
+
+static u32 phy_info_tbl[] = {
+	0x0C000000, 0x0C000100, 0x0C000200, 0x0C000300, 0x0C000140,
+	0x0C000240, 0x0C000340, 0x00000001, 0x00000101, 0x00000201,
+	0x00000301, 0x0C000401, 0x0C000501, 0x0C000601, 0x0C000701,
+	0x00030002, 0x00030102, 0x00030202, 0x0C030302, 0x0C030402,
+	0x0C030502, 0x0C030602, 0x10030702, 0x00030082, 0x00030182,
+	0x00030282, 0x0C030382, 0x0C030482, 0x0C030582, 0x0C030682,
+	0x10030782, 0x00030042, 0x00030142, 0x00030242, 0x0C030342,
+	0x0C030442, 0x0C030542, 0x0C030642, 0x10030742,
+	SET_PHY_INFO(314, 0, 0, 0, 0),
+	SET_PHY_INFO(258, 0, 1, 0, 0),
+	SET_PHY_INFO(223, 0, 1, 0, 0),
+	SET_PHY_INFO(213, 0, 1, 0, 0),
+	SET_PHY_INFO(162, 0, 4, 0, 0),
+	SET_PHY_INFO(127, 0, 4, 0, 0),
+	SET_PHY_INFO(117, 0, 4, 0, 0),
+	SET_PHY_INFO(60, 7, 7, 0, 0),
+	SET_PHY_INFO(52, 7, 7, 0, 0),
+	SET_PHY_INFO(48, 9, 9, 0, 0),
+	SET_PHY_INFO(44, 9, 9, 0, 0),
+	SET_PHY_INFO(44, 11, 11, 0, 0),
+	SET_PHY_INFO(40, 11, 11, 0, 0),
+	SET_PHY_INFO(40, 11, 11, 0, 0),
+	SET_PHY_INFO(40, 11, 11, 0, 0),
+	SET_PHY_INFO(76, 7, 7, 0, 1),
+	SET_PHY_INFO(64, 9, 9, 1, 1),
+	SET_PHY_INFO(60, 9, 9, 2, 1),
+	SET_PHY_INFO(60, 11, 11, 3, 1),
+	SET_PHY_INFO(56, 11, 11, 4, 1),
+	SET_PHY_INFO(56, 11, 11, 5, 1),
+	SET_PHY_INFO(56, 11, 11, 5, 1),
+	SET_PHY_INFO(56, 11, 11, 5, 1),
+	SET_PHY_INFO(76, 7, 7, 6, 1),
+	SET_PHY_INFO(64, 9, 9, 1, 1),
+	SET_PHY_INFO(60, 9, 9, 2, 1),
+	SET_PHY_INFO(60, 11, 11, 3, 1),
+	SET_PHY_INFO(56, 11, 11, 4, 1),
+	SET_PHY_INFO(56, 11, 11, 5, 1),
+	SET_PHY_INFO(56, 11, 11, 5, 1),
+	SET_PHY_INFO(56, 11, 11, 5, 1),
+	SET_PHY_INFO(64, 7, 7, 0, 0),
+	SET_PHY_INFO(52, 9, 9, 0, 0),
+	SET_PHY_INFO(48, 9, 9, 0, 0),
+	SET_PHY_INFO(48, 11, 11, 0, 0),
+	SET_PHY_INFO(44, 11, 11, 0, 0),
+	SET_PHY_INFO(44, 11, 11, 0, 0),
+	SET_PHY_INFO(44, 11, 11, 0, 0),
+	SET_PHY_INFO(44, 11, 11, 0, 0),
+	SET_PHY_L_LENGTH(50, 38, 35),
+	SET_PHY_L_LENGTH(35, 29, 26),
+	SET_PHY_L_LENGTH(29, 26, 23),
+	SET_PHY_L_LENGTH(26, 23, 23),
+	SET_PHY_L_LENGTH(23, 23, 20),
+	SET_PHY_L_LENGTH(23, 20, 20),
+	SET_PHY_L_LENGTH(47, 38, 35),
+	SET_PHY_L_LENGTH(0, 0, 0),
+};
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/drv_comm.h b/drivers/net/wireless/ssv6051/smac/drv_comm.h
new file mode 100644
index 00000000000..f04fbae004c
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/drv_comm.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DRV_COMM_H_
+#define _DRV_COMM_H_
+#define PHY_INFO_TBL1_SIZE 39
+#define PHY_INFO_TBL2_SIZE 39
+#define PHY_INFO_TBL3_SIZE 8
+#define ampdu_fw_rate_info_status_no_use BIT(0)
+#define ampdu_fw_rate_info_status_in_use BIT(1)
+#define ampdu_fw_rate_info_status_reset BIT(2)
+#define SSV_NUM_STA 8
+#define SSV_NUM_VIF 2
+#define SECURITY_KEY_LEN (32)
+enum SSV_CIPHER_E {
+	SSV_CIPHER_NONE,
+	SSV_CIPHER_WEP40,
+	SSV_CIPHER_WEP104,
+	SSV_CIPHER_TKIP,
+	SSV_CIPHER_CCMP,
+	SSV_CIPHER_SMS4,
+	SSV_CIPHER_INVALID = (-1)
+};
+#define ME_NONE 0
+#define ME_WEP40 1
+#define ME_WEP104 2
+#define ME_TKIP 3
+#define ME_CCMP 4
+#define ME_SMS4 5
+struct ssv6xxx_hw_key {
+	u8 key[SECURITY_KEY_LEN];
+	u32 tx_pn_l;
+	u32 tx_pn_h;
+	u32 rx_pn_l;
+	u32 rx_pn_h;
+} __attribute__((packed));
+struct ssv6xxx_hw_sta_key {
+	u8 pair_key_idx:4;
+	u8 group_key_idx:4;
+	u8 valid;
+	u8 reserve[2];
+	struct ssv6xxx_hw_key pair;
+} __attribute__((packed));
+struct ssv6xxx_hw_sec {
+	struct ssv6xxx_hw_key group_key[3];
+	struct ssv6xxx_hw_sta_key sta_key[8];
+} __attribute__((packed));
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/efuse.c b/drivers/net/wireless/ssv6051/smac/efuse.c
new file mode 100644
index 00000000000..9a1f3f5488f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/efuse.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/etherdevice.h>
+#include <ssv6200.h>
+#include "efuse.h"
+
+struct file *openFile(char *path, int flag, int mode)
+{
+	struct file *fp = NULL;
+	fp = filp_open(path, flag, 0);
+	if (IS_ERR(fp))
+		return NULL;
+	else
+		return fp;
+}
+
+int readFile(struct file *fp, char *buf, int readlen)
+{
+	if (fp->f_op && fp->f_op->read)
+		return fp->f_op->read(fp, buf, readlen, &fp->f_pos);
+	else
+		return -1;
+}
+
+int closeFile(struct file *fp)
+{
+	filp_close(fp, NULL);
+	return 0;
+}
+
+void initKernelEnv(void)
+{
+}
+
+void parseMac(char *mac, u_int8_t addr[])
+{
+	long b;
+	int i;
+	for (i = 0; i < 6; i++) {
+		b = simple_strtol(mac + (3 * i), (char **)NULL, 16);
+		addr[i] = (char)b;
+	}
+}
+
+static int readfile_mac(u8 * path, u8 * mac_addr)
+{
+	char buf[128];
+	struct file *fp = NULL;
+	int ret = 0;
+	fp = openFile(path, O_RDONLY, 0);
+	if (fp != NULL) {
+		initKernelEnv();
+		memset(buf, 0, 128);
+		if ((ret = readFile(fp, buf, 128)) > 0) {
+			parseMac(buf, (uint8_t *) mac_addr);
+		} else
+			pr_err("read file error %d=[%s]\n", ret, path);
+		closeFile(fp);
+	} else
+		pr_err("Read open File fail[%s]!!!! \n", path);
+	return ret;
+}
+
+static int write_mac_to_file(u8 * mac_path, u8 * mac_addr)
+{
+	char buf[128];
+	struct file *fp = NULL;
+	int ret = 0, len;
+	fp = openFile(mac_path, O_WRONLY | O_CREAT, 0640);
+	if (fp != NULL) {
+		initKernelEnv();
+		memset(buf, 0, 128);
+		sprintf(buf, "%x:%x:%x:%x:%x:%x", mac_addr[0], mac_addr[1],
+			mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
+		len = strlen(buf) + 1;
+		fp->f_op->write(fp, (char *)buf, len, &fp->f_pos);
+		closeFile(fp);
+	} else
+		pr_err("Write open File fail!!!![%s] \n", mac_path);
+	return ret;
+}
+
+static struct efuse_map SSV_EFUSE_ITEM_TABLE[] = {
+	{4, 0, 0},
+	{4, 8, 0},
+	{4, 8, 0},
+	{4, 48, 0},
+	{4, 8, 0},
+	{4, 8, 0},
+	{4, 8, 0},
+};
+
+static u8 read_efuse(struct ssv_hw *sh, u8 * pbuf)
+{
+	extern struct ssv6xxx_cfg ssv_cfg;
+	u32 val, i;
+	u32 *temp = (u32 *) pbuf;
+	SMAC_REG_WRITE(sh, 0xC0000328, 0x11);
+	SMAC_REG_WRITE(sh, SSV_EFUSE_ID_READ_SWITCH, 0x1);
+	SMAC_REG_READ(sh, SSV_EFUSE_ID_RAW_DATA_BASE, &val);
+	ssv_cfg.chip_identity = val;
+	SMAC_REG_WRITE(sh, SSV_EFUSE_READ_SWITCH, 0x1);
+	SMAC_REG_READ(sh, SSV_EFUSE_RAW_DATA_BASE, &val);
+	if (val == 0x00) {
+		return 0;
+	}
+	for (i = 0; i < (EFUSE_MAX_SECTION_MAP); i++) {
+		SMAC_REG_WRITE(sh, SSV_EFUSE_READ_SWITCH + i * 4, 0x1);
+		SMAC_REG_READ(sh, SSV_EFUSE_RAW_DATA_BASE + i * 4, &val);
+		*temp++ = val;
+	}
+	SMAC_REG_WRITE(sh, 0xC0000328, 0x1800000a);
+	return 1;
+}
+
+static u16 parser_efuse(u8 * pbuf, u8 * mac_addr)
+{
+	u8 *rtemp8, idx = 0;
+	u16 shift = 0, i;
+	u16 efuse_real_content_len = 0;
+	rtemp8 = pbuf;
+	if (*rtemp8 == 0x00) {
+		return efuse_real_content_len;
+	}
+	do {
+		idx = (*(rtemp8) >> shift) & 0xf;
+		switch (idx) {
+		case EFUSE_R_CALIBRATION_RESULT:
+		case EFUSE_CRYSTAL_FREQUENCY_OFFSET:
+		case EFUSE_TX_POWER_INDEX_1:
+		case EFUSE_TX_POWER_INDEX_2:
+		case EFUSE_SAR_RESULT:
+			if (shift) {
+				rtemp8++;
+				SSV_EFUSE_ITEM_TABLE[idx].value =
+				    (u16) ((u8) (*((u16 *) rtemp8)) &
+					   ((1 <<
+					     SSV_EFUSE_ITEM_TABLE
+					     [idx].byte_cnts) - 1));
+			} else {
+				SSV_EFUSE_ITEM_TABLE[idx].value =
+				    (u16) ((u8) (*((u16 *) rtemp8) >> 4) &
+					   ((1 <<
+					     SSV_EFUSE_ITEM_TABLE
+					     [idx].byte_cnts) - 1));
+			}
+			efuse_real_content_len +=
+			    (SSV_EFUSE_ITEM_TABLE[idx].offset +
+			     SSV_EFUSE_ITEM_TABLE[idx].byte_cnts);
+			break;
+		case EFUSE_MAC:
+			if (shift) {
+				rtemp8++;
+				memcpy(mac_addr, rtemp8, 6);
+			} else {
+				for (i = 0; i < 6; i++) {
+					mac_addr[i] =
+					    (u16) (*((u16 *) rtemp8) >> 4) &
+					    0xff;
+					rtemp8++;
+				}
+			}
+			efuse_real_content_len +=
+			    (SSV_EFUSE_ITEM_TABLE[idx].offset +
+			     SSV_EFUSE_ITEM_TABLE[idx].byte_cnts);
+			break;
+		default:
+			idx = 0;
+			break;
+		}
+		shift = efuse_real_content_len % 8;
+		rtemp8 = &pbuf[efuse_real_content_len / 8];
+	} while (idx != 0);
+	return efuse_real_content_len;
+}
+
+void addr_increase_copy(u8 * dst, u8 * src)
+{
+	u8 *a = (u8 *) dst;
+	const u8 *b = (const u8 *)src;
+	a[0] = b[0];
+	a[1] = b[1];
+	a[2] = b[2];
+	a[3] = b[3];
+	a[4] = b[4];
+	if (b[5] & 0x1)
+		a[5] = b[5] - 1;
+	else
+		a[5] = b[5] + 1;
+}
+
+static u8 key_char2num(u8 ch)
+{
+	if ((ch >= '0') && (ch <= '9'))
+		return ch - '0';
+	else if ((ch >= 'a') && (ch <= 'f'))
+		return ch - 'a' + 10;
+	else if ((ch >= 'A') && (ch <= 'F'))
+		return ch - 'A' + 10;
+	else
+		return 0xff;
+}
+
+u8 key_2char2num(u8 hch, u8 lch)
+{
+	return ((key_char2num(hch) << 4) | key_char2num(lch));
+}
+
+extern struct ssv6xxx_cfg ssv_cfg;
+extern char *ssv_initmac;
+void efuse_read_all_map(struct ssv_hw *sh)
+{
+	u8 mac[ETH_ALEN] = { 0 };
+	int jj, kk;
+	u8 efuse_mapping_table[EFUSE_HWSET_MAX_SIZE / 8];
+#ifndef CONFIG_SSV_RANDOM_MAC
+	u8 pseudo_mac0[ETH_ALEN] = { 0x00, 0x33, 0x33, 0x33, 0x33, 0x33 };
+#endif
+	u8 rom_mac0[ETH_ALEN];
+	memset(rom_mac0, 0x00, ETH_ALEN);
+	memset(efuse_mapping_table, 0x00, EFUSE_HWSET_MAX_SIZE / 8);
+	read_efuse(sh, efuse_mapping_table);
+	parser_efuse(efuse_mapping_table, rom_mac0);
+	ssv_cfg.r_calbration_result =
+	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_R_CALIBRATION_RESULT].value;
+	ssv_cfg.sar_result = (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_SAR_RESULT].value;
+	ssv_cfg.crystal_frequency_offset =
+	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_CRYSTAL_FREQUENCY_OFFSET].value;
+	ssv_cfg.tx_power_index_1 =
+	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_TX_POWER_INDEX_1].value;
+	ssv_cfg.tx_power_index_2 =
+	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_TX_POWER_INDEX_2].value;
+	if (!is_valid_ether_addr(&sh->cfg.maddr[0][0])) {
+		if (!sh->cfg.ignore_efuse_mac) {
+			if (is_valid_ether_addr(rom_mac0)) {
+				dev_info(sh->sc->dev, "Using MAC address from e-fuse\n");
+				memcpy(&sh->cfg.maddr[0][0], rom_mac0,
+				       ETH_ALEN);
+				addr_increase_copy(&sh->cfg.maddr[1][0],
+						   rom_mac0);
+				goto Done;
+			}
+		}
+		if (ssv_initmac != NULL) {
+			for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) {
+				mac[jj] =
+				    key_2char2num(ssv_initmac[kk],
+						  ssv_initmac[kk + 1]);
+			}
+			if (is_valid_ether_addr(mac)) {
+				dev_info(sh->sc->dev, "Using MAC address from module option\n");
+				memcpy(&sh->cfg.maddr[0][0], mac, ETH_ALEN);
+				addr_increase_copy(&sh->cfg.maddr[1][0], mac);
+				goto Done;
+			}
+		}
+		if (sh->cfg.mac_address_path[0] != 0x00) {
+			if ((readfile_mac
+			     (sh->cfg.mac_address_path, &sh->cfg.maddr[0][0]))
+			    && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) {
+				dev_info
+				    (sh->sc->dev, "Using MAC address from configuration file\n");
+				addr_increase_copy(&sh->cfg.maddr[1][0],
+						   &sh->cfg.maddr[0][0]);
+				goto Done;
+			}
+		}
+		switch (sh->cfg.mac_address_mode) {
+		case 1:
+			get_random_bytes(&sh->cfg.maddr[0][0], ETH_ALEN);
+			sh->cfg.maddr[0][0] = sh->cfg.maddr[0][0] & 0xF0;
+			addr_increase_copy(&sh->cfg.maddr[1][0],
+					   &sh->cfg.maddr[0][0]);
+			break;
+		case 2:
+			if ((readfile_mac
+			     (sh->cfg.mac_output_path, &sh->cfg.maddr[0][0]))
+			    && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) {
+				addr_increase_copy(&sh->cfg.maddr[1][0],
+						   &sh->cfg.maddr[0][0]);
+			} else {
+				{
+					get_random_bytes(&sh->cfg.maddr[0][0],
+							 ETH_ALEN);
+					sh->cfg.maddr[0][0] =
+					    sh->cfg.maddr[0][0] & 0xF0;
+					addr_increase_copy(&sh->cfg.maddr[1][0],
+							   &sh->
+							   cfg.maddr[0][0]);
+					if (sh->cfg.mac_output_path[0] != 0x00)
+						write_mac_to_file(sh->
+								  cfg.mac_output_path,
+								  &sh->
+								  cfg.maddr[0]
+								  [0]);
+				}
+			}
+			break;
+		default:
+			memcpy(&sh->cfg.maddr[0][0], pseudo_mac0, ETH_ALEN);
+			addr_increase_copy(&sh->cfg.maddr[1][0], pseudo_mac0);
+			break;
+		}
+		dev_info(sh->sc->dev, "MAC address from Software MAC mode[%d]\n",
+			sh->cfg.mac_address_mode);
+	}
+ Done:
+	dev_info(sh->sc->dev, "Chip identity from efuse: %08x\n", ssv_cfg.chip_identity);
+	dev_dbg(sh->sc->dev, "r_calbration_result- %x\n", ssv_cfg.r_calbration_result);
+	dev_dbg(sh->sc->dev, "sar_result- %x\n", ssv_cfg.sar_result);
+	dev_dbg(sh->sc->dev, "crystal_frequency_offset- %x\n",
+		 ssv_cfg.crystal_frequency_offset);
+	dev_dbg(sh->sc->dev, "tx_power_index_1- %x\n", ssv_cfg.tx_power_index_1);
+	dev_dbg(sh->sc->dev, "tx_power_index_2- %x\n", ssv_cfg.tx_power_index_2);
+	dev_dbg(sh->sc->dev, "MAC address - %pM\n", rom_mac0);
+	sh->cfg.crystal_frequency_offset = ssv_cfg.crystal_frequency_offset;
+	sh->cfg.tx_power_index_1 = ssv_cfg.tx_power_index_1;
+	sh->cfg.tx_power_index_2 = ssv_cfg.tx_power_index_2;
+	sh->cfg.chip_identity = ssv_cfg.chip_identity;
+}
diff --git a/drivers/net/wireless/ssv6051/smac/efuse.h b/drivers/net/wireless/ssv6051/smac/efuse.h
new file mode 100644
index 00000000000..c25280c5aba
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/efuse.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_EFUSE_H_
+#define _SSV_EFUSE_H_
+#include "dev.h"
+struct efuse_map {
+	u8 offset;
+	u8 byte_cnts;
+	u16 value;
+};
+enum efuse_data_item {
+	EFUSE_R_CALIBRATION_RESULT = 1,
+	EFUSE_SAR_RESULT,
+	EFUSE_MAC,
+	EFUSE_CRYSTAL_FREQUENCY_OFFSET,
+	EFUSE_TX_POWER_INDEX_1,
+	EFUSE_TX_POWER_INDEX_2
+};
+#define EFUSE_HWSET_MAX_SIZE (256-32)
+#define EFUSE_MAX_SECTION_MAP (EFUSE_HWSET_MAX_SIZE>>5)
+#define SSV_EFUSE_ID_READ_SWITCH 0xC2000128
+#define SSV_EFUSE_ID_RAW_DATA_BASE 0xC200014C
+#define SSV_EFUSE_READ_SWITCH 0xC200012C
+#define SSV_EFUSE_RAW_DATA_BASE 0xC2000150
+void efuse_read_all_map(struct ssv_hw *sh);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/init.c b/drivers/net/wireless/ssv6051/smac/init.c
new file mode 100644
index 00000000000..592c52a2838
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/init.c
@@ -0,0 +1,1347 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/nl80211.h>
+#include <linux/kthread.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+#include <crypto/hash.h>
+#else
+#include <linux/crypto.h>
+#endif
+#include <ssv6200.h>
+#include <hci/hctrl.h>
+#include <ssv_firmware_version.h>
+#include "dev_tbl.h"
+#include "dev.h"
+#include "lib.h"
+#include "ssv_rc.h"
+#include "ap.h"
+#include "efuse.h"
+#include "sar.h"
+#include "ssv_cfgvendor.h"
+
+#include "linux_80211.h"
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+#include "ssv6xxx_debugfs.h"
+#endif
+
+#define WIFI_FIRMWARE_NAME "ssv6051-sw.bin"
+static const struct ieee80211_iface_limit ssv6xxx_p2p_limits[] = {
+	{
+	 .max = 2,
+	 .types = BIT(NL80211_IFTYPE_STATION),
+	 },
+	{
+	 .max = 1,
+	 .types = BIT(NL80211_IFTYPE_P2P_GO) |
+	 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_AP),
+	 },
+};
+
+static const struct ieee80211_iface_combination
+ ssv6xxx_iface_combinations_p2p[] = {
+	{.num_different_channels = 1,
+	 .max_interfaces = SSV6200_MAX_VIF,
+	 .beacon_int_infra_match = true,
+	 .limits = ssv6xxx_p2p_limits,
+	 .n_limits = ARRAY_SIZE(ssv6xxx_p2p_limits),
+	 },
+};
+
+#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
+    (((a) & 0xff00ff00) >> 8))
+#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
+#define CHAN2G(_freq,_idx) { \
+    .band = INDEX_80211_BAND_2GHZ, \
+    .center_freq = (_freq), \
+    .hw_value = (_idx), \
+    .max_power = 20, \
+}
+#ifndef WLAN_CIPHER_SUITE_SMS4
+#define WLAN_CIPHER_SUITE_SMS4 0x00147201
+#endif
+#define SHPCHECK(__hw_rate,__flags) \
+    ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate +3 ) : 0)
+#define RATE(_bitrate,_hw_rate,_flags) { \
+    .bitrate = (_bitrate), \
+    .flags = (_flags), \
+    .hw_value = (_hw_rate), \
+    .hw_value_short = SHPCHECK(_hw_rate,_flags) \
+}
+extern struct ssv6xxx_cfg ssv_cfg;
+static const struct ieee80211_channel ssv6200_2ghz_chantable[] = {
+	CHAN2G(2412, 1),
+	CHAN2G(2417, 2),
+	CHAN2G(2422, 3),
+	CHAN2G(2427, 4),
+	CHAN2G(2432, 5),
+	CHAN2G(2437, 6),
+	CHAN2G(2442, 7),
+	CHAN2G(2447, 8),
+	CHAN2G(2452, 9),
+	CHAN2G(2457, 10),
+	CHAN2G(2462, 11),
+	CHAN2G(2467, 12),
+	CHAN2G(2472, 13),
+	CHAN2G(2484, 14),
+};
+
+static struct ieee80211_rate ssv6200_legacy_rates[] = {
+	RATE(10, 0x00, 0),
+	RATE(20, 0x01, IEEE80211_RATE_SHORT_PREAMBLE),
+	RATE(55, 0x02, IEEE80211_RATE_SHORT_PREAMBLE),
+	RATE(110, 0x03, IEEE80211_RATE_SHORT_PREAMBLE),
+	RATE(60, 0x07, 0),
+	RATE(90, 0x08, 0),
+	RATE(120, 0x09, 0),
+	RATE(180, 0x0a, 0),
+	RATE(240, 0x0b, 0),
+	RATE(360, 0x0c, 0),
+	RATE(480, 0x0d, 0),
+	RATE(540, 0x0e, 0),
+};
+
+struct ssv6xxx_ch_cfg ch_cfg_z[] = {
+	{ADR_ABB_REGISTER_1, 0, 0x151559fc},
+	{ADR_LDO_REGISTER, 0, 0x00eb7c1c},
+	{ADR_RX_ADC_REGISTER, 0, 0x20d000d2}
+};
+
+struct ssv6xxx_ch_cfg ch_cfg_p[] = {
+	{ADR_ABB_REGISTER_1, 0, 0x151559fc},
+	{ADR_RX_ADC_REGISTER, 0, 0x20d000d2}
+};
+
+int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg)
+{
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	int ret = 0;
+	dev_dbg(sh->sc->dev, "# Do init_cali (iq)\n");
+	skb =
+	    ssv_skb_alloc(HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE +
+			  RF_SETTING_SIZE);
+	if (skb == NULL) {
+		dev_err(sh->sc->dev, "init ssv6xxx_do_iq_calib failure\n");
+		return (-1);
+	}
+	if ((PHY_SETTING_SIZE > MAX_PHY_SETTING_TABLE_SIZE) ||
+	    (RF_SETTING_SIZE > MAX_RF_SETTING_TABLE_SIZE)) {
+		dev_warn(sh->sc->dev, "wrong RF or PHY table size\n");
+		WARN_ON(1);
+		return (-1);
+	}
+	skb->data_len =
+	    HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE;
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_INIT_CALI;
+	host_cmd->len = skb->data_len;
+	p_cfg->phy_tbl_size = PHY_SETTING_SIZE;
+	p_cfg->rf_tbl_size = RF_SETTING_SIZE;
+	memcpy(host_cmd->dat32, p_cfg, IQK_CFG_LEN);
+	memcpy(host_cmd->dat8 + IQK_CFG_LEN, phy_setting, PHY_SETTING_SIZE);
+	memcpy(host_cmd->dat8 + IQK_CFG_LEN + PHY_SETTING_SIZE, ssv6200_rf_tbl,
+	       RF_SETTING_SIZE);
+	sh->hci.hci_ops->hci_send_cmd(skb);
+	ssv_skb_free(skb);
+	{
+		u32 timeout;
+		sh->sc->iq_cali_done = IQ_CALI_RUNNING;
+		set_current_state(TASK_INTERRUPTIBLE);
+		timeout = wait_event_interruptible_timeout(sh->sc->fw_wait_q,
+							   sh->sc->iq_cali_done,
+							   msecs_to_jiffies
+							   (500));
+		set_current_state(TASK_RUNNING);
+		if (timeout == 0)
+			return -ETIME;
+		if (sh->sc->iq_cali_done != IQ_CALI_OK)
+			return (-1);
+	}
+	return ret;
+}
+
+#define HT_CAP_RX_STBC_ONE_STREAM 0x1
+#if defined(CONFIG_PM)
+static const struct wiphy_wowlan_support wowlan_support = {
+#ifdef SSV_WAKEUP_HOST
+	.flags = WIPHY_WOWLAN_ANY,
+#else
+	.flags = WIPHY_WOWLAN_DISCONNECT,
+#endif
+	.n_patterns = 0,
+	.pattern_max_len = 0,
+	.pattern_min_len = 0,
+	.max_pkt_offset = 0,
+};
+#endif
+static void ssv6xxx_set_80211_hw_capab(struct ssv_softc *sc)
+{
+	struct ieee80211_hw *hw = sc->hw;
+	struct ssv_hw *sh = sc->sh;
+	struct ieee80211_sta_ht_cap *ht_info;
+	ieee80211_hw_set(hw, SIGNAL_DBM);
+	hw->rate_control_algorithm = "ssv6xxx_rate_control";
+	//hw->rate_control_algorithm = NULL; // NULL selects default
+	ht_info = &sc->sbands[INDEX_80211_BAND_2GHZ].ht_cap;
+	ampdu_db_log("sh->cfg.hw_caps = 0x%x\n", sh->cfg.hw_caps);
+	if (sh->cfg.hw_caps & SSV6200_HW_CAP_HT) {
+		if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX) {
+			ieee80211_hw_set(hw, AMPDU_AGGREGATION);
+			ampdu_db_log("set IEEE80211_HW_AMPDU_AGGREGATION(%d)\n",
+				     ieee80211_hw_check(hw, AMPDU_AGGREGATION));
+		}
+		ht_info->cap = IEEE80211_HT_CAP_SM_PS;
+		if (sh->cfg.hw_caps & SSV6200_HW_CAP_GF) {
+			ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
+			ht_info->cap |=
+			    HT_CAP_RX_STBC_ONE_STREAM <<
+			    IEEE80211_HT_CAP_RX_STBC_SHIFT;
+		}
+		if (sh->cfg.hw_caps & SSV6200_HT_CAP_SGI_20)
+			ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
+		ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_32K;
+		ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
+		memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
+		ht_info->mcs.rx_mask[0] = 0xff;
+		ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
+		ht_info->mcs.rx_highest = cpu_to_le16(SSV6200_RX_HIGHEST_RATE);
+		ht_info->ht_supported = true;
+	}
+	hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
+	if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) {
+		hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_CLIENT);
+		hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_GO);
+		hw->wiphy->iface_combinations = ssv6xxx_iface_combinations_p2p;
+		hw->wiphy->n_iface_combinations =
+		    ARRAY_SIZE(ssv6xxx_iface_combinations_p2p);
+	}
+	hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
+	if (sh->cfg.hw_caps & SSV6200_HW_CAP_AP) {
+		hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
+		hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
+	}
+	if (sh->cfg.hw_caps & SSV6200_HW_CAP_TDLS) {
+		hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
+		hw->wiphy->flags |= WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
+		dev_info(sc->dev, "TDLS function enabled in sta.cfg\n");
+	}
+	hw->queues = 4;
+	hw->max_rates = 4;
+	hw->max_listen_interval = 1;
+	hw->max_rate_tries = HW_MAX_RATE_TRIES;
+	hw->extra_tx_headroom = TXPB_OFFSET + AMPDU_DELIMITER_LEN;
+	if (sizeof(struct ampdu_hdr_st) > SSV_SKB_info_size)
+		hw->extra_tx_headroom += sizeof(struct ampdu_hdr_st);
+	else
+		hw->extra_tx_headroom += SSV_SKB_info_size;
+	if (sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
+		hw->wiphy->bands[INDEX_80211_BAND_2GHZ] =
+		    &sc->sbands[INDEX_80211_BAND_2GHZ];
+	}
+	if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX)
+#ifdef PREFER_RX
+		hw->max_rx_aggregation_subframes = 64;
+#else
+		hw->max_rx_aggregation_subframes = 16;
+#endif
+	else
+		hw->max_rx_aggregation_subframes = 12;
+	hw->max_tx_aggregation_subframes = 64;
+	hw->sta_data_size = sizeof(struct ssv_sta_priv_data);
+	hw->vif_data_size = sizeof(struct ssv_vif_priv_data);
+	memcpy(sh->maddr[0].addr, &sh->cfg.maddr[0][0], ETH_ALEN);
+	hw->wiphy->addresses = sh->maddr;
+	hw->wiphy->n_addresses = 1;
+	if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) {
+		int i;
+		for (i = 1; i < SSV6200_MAX_HW_MAC_ADDR; i++) {
+			memcpy(sh->maddr[i].addr, sh->maddr[i - 1].addr,
+			       ETH_ALEN);
+			sh->maddr[i].addr[5]++;
+			hw->wiphy->n_addresses++;
+		}
+	}
+	if (!is_zero_ether_addr(sh->cfg.maddr[1])) {
+		memcpy(sh->maddr[1].addr, sh->cfg.maddr[1], ETH_ALEN);
+		if (hw->wiphy->n_addresses < 2)
+			hw->wiphy->n_addresses = 2;
+	}
+#if defined(CONFIG_PM)
+	hw->wiphy->wowlan = &wowlan_support;
+#endif
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) && defined(CONFIG_SSV_VENDOR_EXT_SUPPORT)
+    {
+        int err = 0;
+        struct ssv_softc *softc = (struct ssv_softc *)hw->priv;
+        if (softc)
+        {
+            set_wiphy_dev(hw->wiphy, softc->dev);
+            *((struct ssv_softc **)wiphy_priv(hw->wiphy)) = softc;
+        }
+       	dev_dbg(sc->dev, "Registering Vendor80211\n");
+       	err = ssv_cfgvendor_attach(hw->wiphy);
+       	if (unlikely(err < 0)) {
+       		dev_err(sc->dev, "Couldn not attach vendor commands (%d)\n", err);
+       	}
+    }
+#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) || defined(WL_VENDOR_EXT_SUPPORT) */
+}
+
+void ssv6xxx_watchdog_restart_hw(struct ssv_softc *sc)
+{
+	dev_dbg(sc->dev, "%s()\n", __FUNCTION__);
+	sc->restart_counter++;
+	sc->force_triger_reset = true;
+	sc->beacon_info[0].pubf_addr = 0x00;
+	sc->beacon_info[1].pubf_addr = 0x00;
+	ieee80211_restart_hw(sc->hw);
+}
+
+extern struct rssi_res_st rssi_res;
+void ssv6200_watchdog_timeout(struct timer_list *t)
+{
+	static u32 count = 0;
+	struct rssi_res_st *rssi_tmp0 = NULL, *rssi_tmp1 = NULL;
+	struct ssv_softc *sc = from_timer(sc, t, watchdog_timeout);
+	if (sc->watchdog_flag == WD_BARKING) {
+		ssv6xxx_watchdog_restart_hw(sc);
+		mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
+		return;
+	}
+	if (sc->watchdog_flag != WD_SLEEP)
+		sc->watchdog_flag = WD_BARKING;
+	count++;
+	if (count == 6) {
+		count = 0;
+		if (list_empty(&rssi_res.rssi_list)) {
+			return;
+		}
+		list_for_each_entry_safe(rssi_tmp0, rssi_tmp1,
+					 &rssi_res.rssi_list, rssi_list) {
+			if (rssi_tmp0->timeout) {
+				list_del_rcu(&rssi_tmp0->rssi_list);
+				kfree(rssi_tmp0);
+			}
+		}
+	}
+	mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
+	return;
+}
+
+static void ssv6xxx_preload_sw_cipher(void)
+{
+}
+
+static int ssv6xxx_init_softc(struct ssv_softc *sc)
+{
+	void *channels;
+	int ret = 0;
+	sc->sc_flags = SC_OP_INVALID;
+	mutex_init(&sc->mutex);
+	mutex_init(&sc->mem_mutex);
+	sc->config_wq = create_singlethread_workqueue("ssv6xxx_cong_wq");
+	sc->thermal_wq = create_singlethread_workqueue("ssv6xxx_thermal_wq");
+	INIT_DELAYED_WORK(&sc->thermal_monitor_work, thermal_monitor);
+	INIT_WORK(&sc->set_tim_work, ssv6200_set_tim_work);
+	INIT_WORK(&sc->bcast_start_work, ssv6200_bcast_start_work);
+	INIT_DELAYED_WORK(&sc->bcast_stop_work, ssv6200_bcast_stop_work);
+	INIT_DELAYED_WORK(&sc->bcast_tx_work, ssv6200_bcast_tx_work);
+	INIT_WORK(&sc->set_ampdu_rx_add_work, ssv6xxx_set_ampdu_rx_add_work);
+	INIT_WORK(&sc->set_ampdu_rx_del_work, ssv6xxx_set_ampdu_rx_del_work);
+	sc->mac_deci_tbl = sta_deci_tbl;
+	memset((void *)&sc->tx, 0, sizeof(struct ssv_tx));
+	sc->tx.hw_txqid[WMM_AC_VO] = 3;
+	sc->tx.ac_txqid[3] = WMM_AC_VO;
+	sc->tx.hw_txqid[WMM_AC_VI] = 2;
+	sc->tx.ac_txqid[2] = WMM_AC_VI;
+	sc->tx.hw_txqid[WMM_AC_BE] = 1;
+	sc->tx.ac_txqid[1] = WMM_AC_BE;
+	sc->tx.hw_txqid[WMM_AC_BK] = 0;
+	sc->tx.ac_txqid[0] = WMM_AC_BK;
+	INIT_LIST_HEAD(&sc->tx.ampdu_tx_que);
+	spin_lock_init(&sc->tx.ampdu_tx_que_lock);
+	memset((void *)&sc->rx, 0, sizeof(struct ssv_rx));
+	spin_lock_init(&sc->rx.rxq_lock);
+	skb_queue_head_init(&sc->rx.rxq_head);
+	sc->rx.rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
+	if (sc->rx.rx_buf == NULL)
+		return -ENOMEM;
+	memset(&sc->bcast_txq, 0, sizeof(struct ssv6xxx_bcast_txq));
+	spin_lock_init(&sc->bcast_txq.txq_lock);
+	skb_queue_head_init(&sc->bcast_txq.qhead);
+	spin_lock_init(&sc->ps_state_lock);
+#ifdef CONFIG_P2P_NOA
+	spin_lock_init(&sc->p2p_noa.p2p_config_lock);
+#endif
+	if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
+		channels = kmemdup(ssv6200_2ghz_chantable,
+				   sizeof(ssv6200_2ghz_chantable), GFP_KERNEL);
+		if (!channels) {
+			kfree(sc->rx.rx_buf);
+			return -ENOMEM;
+		}
+		sc->sbands[INDEX_80211_BAND_2GHZ].channels = channels;
+		sc->sbands[INDEX_80211_BAND_2GHZ].band = INDEX_80211_BAND_2GHZ;
+		sc->sbands[INDEX_80211_BAND_2GHZ].n_channels =
+		    ARRAY_SIZE(ssv6200_2ghz_chantable);
+		sc->sbands[INDEX_80211_BAND_2GHZ].bitrates =
+		    ssv6200_legacy_rates;
+		sc->sbands[INDEX_80211_BAND_2GHZ].n_bitrates =
+		    ARRAY_SIZE(ssv6200_legacy_rates);
+	}
+	sc->cur_channel = NULL;
+	sc->hw_chan = (-1);
+	ssv6xxx_set_80211_hw_capab(sc);
+	ret = ssv6xxx_rate_control_register();
+	if (ret != 0) {
+		dev_warn(sc->dev, "%s(): Failed to register rc algorithm.\n",__FUNCTION__);
+	}
+	init_waitqueue_head(&sc->tx_wait_q);
+	sc->tx_wait_q_woken = 0;
+	skb_queue_head_init(&sc->tx_skb_q);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	sc->max_tx_skb_q_len = 0;
+#endif
+	sc->tx_task = kthread_run(ssv6xxx_tx_task, sc, "ssv6xxx_tx_task");
+	sc->tx_q_empty = false;
+	skb_queue_head_init(&sc->tx_done_q);
+	init_waitqueue_head(&sc->rx_wait_q);
+	sc->rx_wait_q_woken = 0;
+	skb_queue_head_init(&sc->rx_skb_q);
+	sc->rx_task = kthread_run(ssv6xxx_rx_task, sc, "ssv6xxx_rx_task");
+	ssv6xxx_preload_sw_cipher();
+	timer_setup(&sc->watchdog_timeout, ssv6200_watchdog_timeout, 0);
+	init_waitqueue_head(&sc->fw_wait_q);
+	INIT_LIST_HEAD(&rssi_res.rssi_list);
+	rssi_res.rssi = 0;
+	mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
+	//add_timer(&sc->watchdog_timeout);
+	//if(get_flash_info(sc) == 1)
+	sc->is_sar_enabled = get_flash_info(sc);
+	if (sc->is_sar_enabled)
+		queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
+				   THERMAL_MONITOR_TIME);
+	//schedule_delayed_work(&sc->thermal_monitor_work, THERMAL_MONITOR_TIME);
+	return ret;
+}
+
+static int ssv6xxx_deinit_softc(struct ssv_softc *sc)
+{
+	void *channels;
+	struct sk_buff *skb;
+	u8 remain_size;
+	dev_dbg(sc->dev, "%s():\n", __FUNCTION__);
+	if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
+		channels = sc->sbands[INDEX_80211_BAND_2GHZ].channels;
+		kfree(channels);
+	}
+	ssv_skb_free(sc->rx.rx_buf);
+	sc->rx.rx_buf = NULL;
+	ssv6xxx_rate_control_unregister();
+	cancel_delayed_work_sync(&sc->bcast_tx_work);
+	//ssv6xxx_watchdog_controller(sc->sh ,(u8)SSV6XXX_HOST_CMD_WATCHDOG_STOP);
+	del_timer_sync(&sc->watchdog_timeout);
+	cancel_delayed_work(&sc->thermal_monitor_work);
+	sc->ps_status = PWRSV_PREPARE;
+	flush_workqueue(sc->thermal_wq);
+	destroy_workqueue(sc->thermal_wq);
+	do {
+		skb = ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size);
+		if (skb)
+			ssv6xxx_txbuf_free_skb(skb, (void *)sc);
+		else
+			break;
+	} while (remain_size);
+	if (sc->tx_task != NULL) {
+		dev_dbg(sc->dev, "Stopping TX task...\n");
+		kthread_stop(sc->tx_task);
+		sc->tx_task = NULL;
+		dev_dbg(sc->dev, "Stopped TX task.\n");
+	}
+	if (sc->rx_task != NULL) {
+		dev_dbg(sc->dev, "Stopping RX task...\n");
+		kthread_stop(sc->rx_task);
+		sc->rx_task = NULL;
+		dev_dbg(sc->dev, "Stopped RX task.\n");
+	}
+	destroy_workqueue(sc->config_wq);
+	return 0;
+}
+
+static void ssv6xxx_hw_set_replay_ignore(struct ssv_hw *sh, u8 ignore)
+{
+	u32 temp;
+	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
+	temp = temp & SCRT_RPLY_IGNORE_I_MSK;
+	temp |= (ignore << SCRT_RPLY_IGNORE_SFT);
+	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
+}
+
+int ssv6xxx_init_mac(struct ssv_hw *sh)
+{
+	struct ssv_softc *sc = sh->sc;
+	int i = 0, ret = 0;
+
+	u32 *ptr, id_len, regval, temp[0x8];
+	char *chip_id = sh->chip_id;
+	SMAC_REG_READ(sh, ADR_IC_TIME_TAG_1, &regval);
+	sh->chip_tag = ((u64) regval << 32);
+	SMAC_REG_READ(sh, ADR_IC_TIME_TAG_0, &regval);
+	sh->chip_tag |= (regval);
+	SMAC_REG_READ(sh, ADR_CHIP_ID_3, &regval);
+	*((u32 *) & chip_id[0]) = (u32) LONGSWAP(regval);
+	SMAC_REG_READ(sh, ADR_CHIP_ID_2, &regval);
+	*((u32 *) & chip_id[4]) = (u32) LONGSWAP(regval);
+	SMAC_REG_READ(sh, ADR_CHIP_ID_1, &regval);
+	*((u32 *) & chip_id[8]) = (u32) LONGSWAP(regval);
+	SMAC_REG_READ(sh, ADR_CHIP_ID_0, &regval);
+	*((u32 *) & chip_id[12]) = (u32) LONGSWAP(regval);
+	chip_id[12 + sizeof(u32)] = 0;
+	dev_info(sh->sc->dev, "chip id: %s, tag: %llx\n", chip_id, sh->chip_tag);
+	if (sc->ps_status == PWRSV_ENABLE) {
+		SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA,
+			       M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) |
+			       (M_ENG_HWHCI << 8));
+		SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
+			       M_ENG_MACRX | (M_ENG_HWHCI << 4));
+#if Enable_AMPDU_FW_Retry
+		SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
+			       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI <<
+								 8));
+#else
+		SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
+			       M_ENG_MACRX | (M_ENG_HWHCI << 4));
+#endif
+		SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + 6 * 4,
+			       (sc->mac_deci_tbl[6]));
+		return ret;
+	}
+	SMAC_REG_SET_BITS(sh, ADR_PHY_EN_1, (0 << RG_PHY_MD_EN_SFT),
+			  RG_PHY_MD_EN_MSK);
+	SMAC_REG_WRITE(sh, ADR_BRG_SW_RST, 1 << MAC_SW_RST_SFT);
+	do {
+		SMAC_REG_READ(sh, ADR_BRG_SW_RST, &regval);
+		i++;
+		if (i > 10000) {
+			dev_err(sh->sc->dev, "MAC reset fail !!!!\n");
+			WARN_ON(1);
+			ret = 1;
+			goto exit;
+		}
+	} while (regval != 0);
+	SMAC_REG_WRITE(sc->sh, ADR_TXQ4_MTX_Q_AIFSN, 0xffff2101);
+	SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC, 0,
+			  MTX_HALT_MNG_UNTIL_DTIM_MSK);
+	SMAC_REG_WRITE(sh, ADR_CONTROL, 0x12000006);
+	SMAC_REG_WRITE(sh, ADR_RX_TIME_STAMP_CFG,
+		       ((28 << MRX_STP_OFST_SFT) | 0x01));
+	SMAC_REG_WRITE(sh, ADR_HCI_TX_RX_INFO_SIZE,
+		       ((u32) (TXPB_OFFSET) << TX_PBOFFSET_SFT) |
+		       ((u32) (sh->tx_desc_len) << TX_INFO_SIZE_SFT) |
+		       ((u32) (sh->rx_desc_len) << RX_INFO_SIZE_SFT) |
+		       ((u32) (sh->rx_pinfo_pad) << RX_LAST_PHY_SIZE_SFT)
+	    );
+	SMAC_REG_READ(sh, ADR_MMU_CTRL, &regval);
+	regval |= (0xff << MMU_SHARE_MCU_SFT);
+	SMAC_REG_WRITE(sh, ADR_MMU_CTRL, regval);
+	SMAC_REG_READ(sh, ADR_MRX_WATCH_DOG, &regval);
+	regval &= 0xfffffff0;
+	SMAC_REG_WRITE(sh, ADR_MRX_WATCH_DOG, regval);
+	SMAC_REG_READ(sh, ADR_TRX_ID_THRESHOLD, &id_len);
+	id_len = (id_len & 0xffff0000) |
+	    (SSV6200_ID_TX_THRESHOLD << TX_ID_THOLD_SFT) |
+	    (SSV6200_ID_RX_THRESHOLD << RX_ID_THOLD_SFT);
+	SMAC_REG_WRITE(sh, ADR_TRX_ID_THRESHOLD, id_len);
+	SMAC_REG_READ(sh, ADR_ID_LEN_THREADSHOLD1, &id_len);
+	id_len = (id_len & 0x0f) |
+	    (SSV6200_PAGE_TX_THRESHOLD << ID_TX_LEN_THOLD_SFT) |
+	    (SSV6200_PAGE_RX_THRESHOLD << ID_RX_LEN_THOLD_SFT);
+	SMAC_REG_WRITE(sh, ADR_ID_LEN_THREADSHOLD1, id_len);
+#ifdef CONFIG_SSV_CABRIO_MB_DEBUG
+	SMAC_REG_READ(sh, ADR_MB_DBG_CFG3, &regval);
+	regval |= (debug_buffer << 0);
+	SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG3, regval);
+	SMAC_REG_READ(sh, ADR_MB_DBG_CFG2, &regval);
+	regval |= (DEBUG_SIZE << 16);
+	SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG2, regval);
+	SMAC_REG_READ(sh, ADR_MB_DBG_CFG1, &regval);
+	regval |= (1 << MB_DBG_EN_SFT);
+	SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG1, regval);
+	SMAC_REG_READ(sh, ADR_MBOX_HALT_CFG, &regval);
+	regval |= (1 << MB_ERR_AUTO_HALT_EN_SFT);
+	SMAC_REG_WRITE(sh, ADR_MBOX_HALT_CFG, regval);
+#endif
+	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, &regval);
+	regval |= (1 << MTX_TSF_TIMER_EN_SFT);
+	SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval);
+	SMAC_REG_WRITE(sh, 0xcd010004, 0x1213);
+	for (i = 0; i < SSV_RC_MAX_STA; i++) {
+		if (i == 0) {
+			sh->hw_buf_ptr[i] =
+			    ssv6xxx_pbuf_alloc(sc,
+					       sizeof(phy_info_tbl) +
+					       sizeof(struct ssv6xxx_hw_sec),
+					       NOTYPE_BUF);
+			if ((sh->hw_buf_ptr[i] >> 28) != 8) {
+				dev_err(sh->sc->dev, "opps allocate pbuf error\n");
+				WARN_ON(1);
+				ret = 1;
+				goto exit;
+			}
+		} else {
+			sh->hw_buf_ptr[i] =
+			    ssv6xxx_pbuf_alloc(sc,
+					       sizeof(struct ssv6xxx_hw_sec),
+					       NOTYPE_BUF);
+			if ((sh->hw_buf_ptr[i] >> 28) != 8) {
+				dev_err(sh->sc->dev, "opps allocate pbuf error\n");
+				WARN_ON(1);
+				ret = 1;
+				goto exit;
+			}
+		}
+	}
+	for (i = 0; i < 0x8; i++) {
+		temp[i] = 0;
+		temp[i] = ssv6xxx_pbuf_alloc(sc, 256, NOTYPE_BUF);
+	}
+	for (i = 0; i < 0x8; i++) {
+		if (temp[i] == 0x800e0000)
+			dev_dbg(sh->sc->dev, "Found 0x800e0000 at position %d\n", i);
+		else
+			ssv6xxx_pbuf_free(sc, temp[i]);
+	}
+	for (i = 0; i < SSV_RC_MAX_STA; i++)
+		sh->hw_sec_key[i] = sh->hw_buf_ptr[i];
+	for (i = 0; i < SSV_RC_MAX_STA; i++) {
+		int x;
+		for (x = 0; x < sizeof(struct ssv6xxx_hw_sec); x += 4) {
+			SMAC_REG_WRITE(sh, sh->hw_sec_key[i] + x, 0);
+		}
+	}
+	SMAC_REG_READ(sh, ADR_SCRT_SET, &regval);
+	regval &= SCRT_PKT_ID_I_MSK;
+	regval |= ((sh->hw_sec_key[0] >> 16) << SCRT_PKT_ID_SFT);
+	SMAC_REG_WRITE(sh, ADR_SCRT_SET, regval);
+	sh->hw_pinfo = sh->hw_sec_key[0] + sizeof(struct ssv6xxx_hw_sec);
+	for (i = 0, ptr = phy_info_tbl; i < PHY_INFO_TBL1_SIZE; i++, ptr++) {
+		SMAC_REG_WRITE(sh, ADR_INFO0 + i * 4, *ptr);
+		SMAC_REG_CONFIRM(sh, ADR_INFO0 + i * 4, *ptr);
+	}
+	for (i = 0; i < PHY_INFO_TBL2_SIZE; i++, ptr++) {
+		SMAC_REG_WRITE(sh, sh->hw_pinfo + i * 4, *ptr);
+		SMAC_REG_CONFIRM(sh, sh->hw_pinfo + i * 4, *ptr);
+	}
+	for (i = 0; i < PHY_INFO_TBL3_SIZE; i++, ptr++) {
+		SMAC_REG_WRITE(sh, sh->hw_pinfo +
+			       (PHY_INFO_TBL2_SIZE << 2) + i * 4, *ptr);
+		SMAC_REG_CONFIRM(sh, sh->hw_pinfo +
+				 (PHY_INFO_TBL2_SIZE << 2) + i * 4, *ptr);
+	}
+	SMAC_REG_WRITE(sh, ADR_INFO_RATE_OFFSET, 0x00040000);
+	SMAC_REG_WRITE(sh, ADR_INFO_IDX_ADDR, sh->hw_pinfo);
+	SMAC_REG_WRITE(sh, ADR_INFO_LEN_ADDR,
+		       sh->hw_pinfo + (PHY_INFO_TBL2_SIZE) * 4);
+	dev_dbg(sh->sc->dev, "ADR_INFO_IDX_ADDR[%08x] ADR_INFO_LEN_ADDR[%08x]\n",
+	       sh->hw_pinfo, sh->hw_pinfo + (PHY_INFO_TBL2_SIZE) * 4);
+	SMAC_REG_WRITE(sh, ADR_GLBLE_SET,
+		       (0 << OP_MODE_SFT) | (0 << SNIFFER_MODE_SFT) | (1 <<
+								       DUP_FLT_SFT)
+		       | (SSV6200_TX_PKT_RSVD_SETTING << TX_PKT_RSVD_SFT) |
+		       ((u32) (RXPB_OFFSET) << PB_OFFSET_SFT)
+	    );
+	SMAC_REG_WRITE(sh, ADR_STA_MAC_0, *((u32 *) & sh->cfg.maddr[0][0]));
+	SMAC_REG_WRITE(sh, ADR_STA_MAC_1, *((u32 *) & sh->cfg.maddr[0][4]));
+	SMAC_REG_WRITE(sh, ADR_BSSID_0, *((u32 *) & sc->bssid[0]));
+	SMAC_REG_WRITE(sh, ADR_BSSID_1, *((u32 *) & sc->bssid[4]));
+	SMAC_REG_WRITE(sh, ADR_TX_ETHER_TYPE_0, 0x00000000);
+	SMAC_REG_WRITE(sh, ADR_TX_ETHER_TYPE_1, 0x00000000);
+	SMAC_REG_WRITE(sh, ADR_RX_ETHER_TYPE_0, 0x00000000);
+	SMAC_REG_WRITE(sh, ADR_RX_ETHER_TYPE_1, 0x00000000);
+	SMAC_REG_WRITE(sh, ADR_REASON_TRAP0, 0x7FBC7F87);
+	SMAC_REG_WRITE(sh, ADR_REASON_TRAP1, 0x0000003F);
+	SMAC_REG_WRITE(sh, ADR_TRAP_HW_ID, M_ENG_CPU);
+	SMAC_REG_WRITE(sh, ADR_WSID0, 0x00000000);
+	SMAC_REG_WRITE(sh, ADR_WSID1, 0x00000000);
+	SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA,
+		       M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) | (M_ENG_HWHCI <<
+								 8));
+#if defined(CONFIG_P2P_NOA) || defined(CONFIG_RX_MGMT_CHECK)
+	SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG,
+		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
+#else
+	SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG, M_ENG_MACRX | (M_ENG_HWHCI << 4));
+#endif
+#if Enable_AMPDU_FW_Retry
+	SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
+		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
+#else
+	SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL, M_ENG_MACRX | (M_ENG_HWHCI << 4));
+#endif
+	ssv6xxx_hw_set_replay_ignore(sh, 1);
+	ssv6xxx_update_decision_table(sc);
+	SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, SSV6200_OPMODE_STA,
+			  OP_MODE_MSK);
+	SMAC_REG_WRITE(sh, ADR_SDIO_MASK, 0xfffe1fff);
+	SMAC_REG_WRITE(sh, ADR_TX_LIMIT_INTR, 0x80000000 |
+		       SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER << 16 |
+		       SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER);
+#ifdef CONFIG_SSV_SUPPORT_BTCX
+	SMAC_REG_WRITE(sh, ADR_BTCX0,
+		       COEXIST_EN_MSK | (WIRE_MODE_SZ << WIRE_MODE_SFT)
+		       | WIFI_TX_SW_POL_MSK | BT_SW_POL_MSK);
+	SMAC_REG_WRITE(sh, ADR_BTCX1,
+		       SSV6200_BT_PRI_SMP_TIME | (SSV6200_BT_STA_SMP_TIME <<
+						  BT_STA_SMP_TIME_SFT)
+		       | (SSV6200_WLAN_REMAIN_TIME << WLAN_REMAIN_TIME_SFT));
+	SMAC_REG_WRITE(sh, ADR_SWITCH_CTL, BT_2WIRE_EN_MSK);
+	SMAC_REG_WRITE(sh, ADR_PAD7, 1);
+	SMAC_REG_WRITE(sh, ADR_PAD8, 0);
+	SMAC_REG_WRITE(sh, ADR_PAD9, 1);
+	SMAC_REG_WRITE(sh, ADR_PAD25, 1);
+	SMAC_REG_WRITE(sh, ADR_PAD27, 8);
+	SMAC_REG_WRITE(sh, ADR_PAD28, 8);
+#endif
+	dev_info(sh->sc->dev, "attempt to load firmware %s\n", WIFI_FIRMWARE_NAME);
+	ret = SMAC_LOAD_FW(sh, WIFI_FIRMWARE_NAME, 0);
+
+	SMAC_REG_READ(sh, FW_VERSION_REG, &regval);
+	if (regval == ssv_firmware_version) {
+		SMAC_REG_SET_BITS(sh, ADR_PHY_EN_1, (1 << RG_PHY_MD_EN_SFT),
+				  RG_PHY_MD_EN_MSK);
+		dev_info(sh->sc->dev, "Firmware version %d\n", regval);
+	} else {
+		dev_err(sh->sc->dev, "Firmware version not mapping %d\n", regval);
+		ret = -1;
+	}
+	ssv6xxx_watchdog_controller(sh, (u8) SSV6XXX_HOST_CMD_WATCHDOG_START);
+ exit:
+	return ret;
+}
+
+void ssv6xxx_deinit_mac(struct ssv_softc *sc)
+{
+	int i;
+	for (i = 0; i < SSV_RC_MAX_STA; i++) {
+		if (sc->sh->hw_buf_ptr[i])
+			ssv6xxx_pbuf_free(sc, sc->sh->hw_buf_ptr[i]);
+	}
+}
+
+void inline ssv6xxx_deinit_hw(struct ssv_softc *sc)
+{
+	dev_dbg(sc->dev, "%s(): \n", __FUNCTION__);
+	ssv6xxx_deinit_mac(sc);
+}
+
+void ssv6xxx_restart_hw(struct ssv_softc *sc)
+{
+	dev_info(sc->dev, "Software MAC reset\n");
+	sc->restart_counter++;
+	sc->force_triger_reset = true;
+	HCI_STOP(sc->sh);
+	SMAC_REG_WRITE(sc->sh, 0xce000004, 0x0);
+	sc->beacon_info[0].pubf_addr = 0x00;
+	sc->beacon_info[1].pubf_addr = 0x00;
+	ieee80211_restart_hw(sc->hw);
+}
+
+extern struct ssv6xxx_iqk_cfg init_iqk_cfg;
+static int ssv6xxx_init_hw(struct ssv_hw *sh)
+{
+	int ret = 0, i = 0, x = 0;
+	u32 regval;
+	sh->tx_desc_len = SSV6XXX_TX_DESC_LEN;
+	sh->rx_desc_len = SSV6XXX_RX_DESC_LEN;
+	sh->rx_pinfo_pad = 0x04;
+	sh->tx_page_available = SSV6200_PAGE_TX_THRESHOLD;
+	sh->ampdu_divider = SSV6XXX_AMPDU_DIVIDER;
+	memset(sh->page_count, 0, sizeof(sh->page_count));
+	if (sh->cfg.force_chip_identity) {
+		dev_info(sh->sc->dev, "Force use external RF setting [%08x]\n",
+		       sh->cfg.force_chip_identity);
+		sh->cfg.chip_identity = sh->cfg.force_chip_identity;
+	}
+	if (sh->cfg.chip_identity == SSV6051Z) {
+		sh->p_ch_cfg = &ch_cfg_z[0];
+		sh->ch_cfg_size =
+		    sizeof(ch_cfg_z) / sizeof(struct ssv6xxx_ch_cfg);
+		memcpy(phy_info_tbl, phy_info_6051z, sizeof(phy_info_6051z));
+	} else if (sh->cfg.chip_identity == SSV6051P) {
+		sh->p_ch_cfg = &ch_cfg_p[0];
+		sh->ch_cfg_size =
+		    sizeof(ch_cfg_p) / sizeof(struct ssv6xxx_ch_cfg);
+	}
+	switch (sh->cfg.chip_identity) {
+	case SSV6051Q_P1:
+	case SSV6051Q_P2:
+	case SSV6051Q:
+		dev_info(sh->sc->dev, "Using SSV6051Q setting\n");
+		for (i = 0;
+		     i <
+		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (ssv6200_rf_tbl[i].address == 0xCE010008)
+				ssv6200_rf_tbl[i].data = 0x008DF61B;
+			if (ssv6200_rf_tbl[i].address == 0xCE010014)
+				ssv6200_rf_tbl[i].data = 0x3D3E84FE;
+			if (ssv6200_rf_tbl[i].address == 0xCE010018)
+				ssv6200_rf_tbl[i].data = 0x01457D79;
+			if (ssv6200_rf_tbl[i].address == 0xCE01001C)
+				ssv6200_rf_tbl[i].data = 0x000103A7;
+			if (ssv6200_rf_tbl[i].address == 0xCE010020)
+				ssv6200_rf_tbl[i].data = 0x000103A6;
+			if (ssv6200_rf_tbl[i].address == 0xCE01002C)
+				ssv6200_rf_tbl[i].data = 0x00032CA8;
+			if (ssv6200_rf_tbl[i].address == 0xCE010048)
+				ssv6200_rf_tbl[i].data = 0xFCCCCF27;
+			if (ssv6200_rf_tbl[i].address == 0xCE010050)
+				ssv6200_rf_tbl[i].data = 0x0047C000;
+		}
+		break;
+	case SSV6051Z:
+		dev_info(sh->sc->dev, "Using SSV6051Z setting\n");
+		for (i = 0;
+		     i <
+		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (ssv6200_rf_tbl[i].address == 0xCE010008)
+				ssv6200_rf_tbl[i].data = 0x004D561C;
+			if (ssv6200_rf_tbl[i].address == 0xCE010014)
+				ssv6200_rf_tbl[i].data = 0x3D9E84FE;
+			if (ssv6200_rf_tbl[i].address == 0xCE010018)
+				ssv6200_rf_tbl[i].data = 0x00457D79;
+			if (ssv6200_rf_tbl[i].address == 0xCE01001C)
+				ssv6200_rf_tbl[i].data = 0x000103EB;
+			if (ssv6200_rf_tbl[i].address == 0xCE010020)
+				ssv6200_rf_tbl[i].data = 0x000103EA;
+			if (ssv6200_rf_tbl[i].address == 0xCE01002C)
+				ssv6200_rf_tbl[i].data = 0x00062CA8;
+			if (ssv6200_rf_tbl[i].address == 0xCE010048)
+				ssv6200_rf_tbl[i].data = 0xFCCCCF27;
+			if (ssv6200_rf_tbl[i].address == 0xCE010050)
+				ssv6200_rf_tbl[i].data = 0x0047C000;
+		}
+		break;
+	case SSV6051P:
+		dev_info(sh->sc->dev, "Using SSV6051P setting\n");
+		for (i = 0;
+		     i <
+		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (ssv6200_rf_tbl[i].address == 0xCE010008)
+				ssv6200_rf_tbl[i].data = 0x008B7C1C;
+			if (ssv6200_rf_tbl[i].address == 0xCE010014)
+				ssv6200_rf_tbl[i].data = 0x3D7E84FE;
+			if (ssv6200_rf_tbl[i].address == 0xCE010018)
+				ssv6200_rf_tbl[i].data = 0x01457D79;
+			if (ssv6200_rf_tbl[i].address == 0xCE01001C)
+				ssv6200_rf_tbl[i].data = 0x000103EB;
+			if (ssv6200_rf_tbl[i].address == 0xCE010020)
+				ssv6200_rf_tbl[i].data = 0x000103EA;
+			if (ssv6200_rf_tbl[i].address == 0xCE01002C)
+				ssv6200_rf_tbl[i].data = 0x00032CA8;
+			if (ssv6200_rf_tbl[i].address == 0xCE010048)
+				ssv6200_rf_tbl[i].data = 0xFCCCCC27;
+			if (ssv6200_rf_tbl[i].address == 0xCE010050)
+				ssv6200_rf_tbl[i].data = 0x0047C000;
+			if (ssv6200_rf_tbl[i].address == 0xC0001D00)
+				ssv6200_rf_tbl[i].data = 0x5E000040;
+		}
+		break;
+	default:
+		dev_err(sh->sc->dev, "No RF setting\n");
+		break;
+	}
+	if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M) {
+		init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_26M;
+		dev_info(sh->sc->dev, "Crystal frequency: 26 Mhz\n");
+	} else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_40M) {
+		init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_40M;
+		dev_info(sh->sc->dev, "Crystal frequency: 40 Mhz\n");
+	} else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M) {
+		init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_24M;
+		dev_info(sh->sc->dev, "Crystal frequency: 24 Mhz\n");
+		for (i = 0;
+		     i <
+		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (ssv6200_rf_tbl[i].address == ADR_SX_ENABLE_REGISTER)
+				ssv6200_rf_tbl[i].data = 0x0003E07C;
+			if (ssv6200_rf_tbl[i].address ==
+			    ADR_DPLL_DIVIDER_REGISTER)
+				ssv6200_rf_tbl[i].data = 0x00406000;
+			if (ssv6200_rf_tbl[i].address ==
+			    ADR_DPLL_FB_DIVIDER_REGISTERS_I)
+				ssv6200_rf_tbl[i].data = 0x00000028;
+			if (ssv6200_rf_tbl[i].address ==
+			    ADR_DPLL_FB_DIVIDER_REGISTERS_II)
+				ssv6200_rf_tbl[i].data = 0x00000000;
+		}
+	} else {
+		dev_warn(sh->sc->dev, "Illegal crystal setting, using default value of 26 Mhz\n");
+	}
+	for (i = 0;
+	     i < sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+	     i++) {
+		if (ssv6200_rf_tbl[i].address ==
+		    ADR_SYN_KVCO_XO_FINE_TUNE_CBANK) {
+			if (sh->cfg.crystal_frequency_offset) {
+				ssv6200_rf_tbl[i].data &=
+				    RG_XOSC_CBANK_XO_I_MSK;
+				ssv6200_rf_tbl[i].data |=
+				    (sh->cfg.
+				     crystal_frequency_offset <<
+				     RG_XOSC_CBANK_XO_SFT);
+			}
+		}
+	}
+	for (i = 0; i < sizeof(phy_setting) / sizeof(struct ssv6xxx_dev_table);
+	     i++) {
+		if (phy_setting[i].address == ADR_TX_GAIN_FACTOR) {
+			switch (sh->cfg.chip_identity) {
+			case SSV6051Q_P1:
+			case SSV6051Q_P2:
+			case SSV6051Q:
+				dev_dbg(sh->sc->dev, "SSV6051Q setting [0x5B606C72]\n");
+				phy_setting[i].data = 0x5B606C72;
+				break;
+			case SSV6051Z:
+				dev_dbg(sh->sc->dev, "SSV6051Z setting [0x60606060]\n");
+				phy_setting[i].data = 0x60606060;
+				break;
+			case SSV6051P:
+				dev_dbg(sh->sc->dev, "SSV6051P setting [0x6C726C72]\n");
+				phy_setting[i].data = 0x6C726C72;
+				break;
+			default:
+				dev_dbg(sh->sc->dev, "Use default power setting\n");
+				break;
+			}
+			if (sh->cfg.wifi_tx_gain_level_b) {
+				phy_setting[i].data &= 0xffff0000;
+				phy_setting[i].data |=
+				    wifi_tx_gain[sh->cfg.
+						 wifi_tx_gain_level_b] &
+				    0x0000ffff;
+			}
+			if (sh->cfg.wifi_tx_gain_level_gn) {
+				phy_setting[i].data &= 0x0000ffff;
+				phy_setting[i].data |=
+				    wifi_tx_gain[sh->cfg.
+						 wifi_tx_gain_level_gn] &
+				    0xffff0000;
+			}
+			dev_dbg(sh->sc->dev, "TX power setting 0x%x\n", phy_setting[i].data);
+			init_iqk_cfg.cfg_def_tx_scale_11b =
+			    (phy_setting[i].data >> 0) & 0xff;
+			init_iqk_cfg.cfg_def_tx_scale_11b_p0d5 =
+			    (phy_setting[i].data >> 8) & 0xff;
+			init_iqk_cfg.cfg_def_tx_scale_11g =
+			    (phy_setting[i].data >> 16) & 0xff;
+			init_iqk_cfg.cfg_def_tx_scale_11g_p0d5 =
+			    (phy_setting[i].data >> 24) & 0xff;
+			break;
+		}
+	}
+	if (sh->cfg.volt_regulator == SSV6XXX_VOLT_LDO_CONVERT) {
+		dev_info(sh->sc->dev, "Using LDO voltage regulator\n");
+		for (i = 0;
+		     i <
+		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (ssv6200_rf_tbl[i].address == ADR_PMU_2) {
+				ssv6200_rf_tbl[i].data &= 0xFFFFFFFE;
+				ssv6200_rf_tbl[i].data |= 0x00000000;
+			}
+		}
+	} else if (sh->cfg.volt_regulator == SSV6XXX_VOLT_DCDC_CONVERT) {
+		dev_info(sh->sc->dev, "Using DCDC buck regulator\n");
+		for (i = 0;
+		     i <
+		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (ssv6200_rf_tbl[i].address == ADR_PMU_2) {
+				ssv6200_rf_tbl[i].data &= 0xFFFFFFFE;
+				ssv6200_rf_tbl[i].data |= 0x00000001;
+			}
+		}
+	} else {
+		dev_warn(sh->sc->dev, "Illegal regulator setting, using DCDC buck as default\n");
+	}
+	while (ssv_cfg.configuration[x][0]) {
+		for (i = 0;
+		     i <
+		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (ssv6200_rf_tbl[i].address ==
+			    ssv_cfg.configuration[x][0]) {
+				ssv6200_rf_tbl[i].data =
+				    ssv_cfg.configuration[x][1];
+				break;
+			}
+		}
+		for (i = 0;
+		     i < sizeof(phy_setting) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (phy_setting[i].address ==
+			    ssv_cfg.configuration[x][0]) {
+				phy_setting[i].data =
+				    ssv_cfg.configuration[x][1];
+				break;
+			}
+		}
+		x++;
+	};
+	if (ret == 0)
+		ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_rf_tbl);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1, 0x00000000);
+	SMAC_REG_READ(sh, ADR_PHY_EN_0, &regval);
+	if (regval & (1 << RG_RF_BB_CLK_SEL_SFT)) {
+		dev_dbg(sh->sc->dev, "already do clock switch\n");
+	} else {
+		dev_dbg(sh->sc->dev, "reset PLL\n");
+		SMAC_REG_READ(sh, ADR_DPLL_CP_PFD_REGISTER, &regval);
+		regval |=
+		    ((1 << RG_DP_BBPLL_PD_SFT) |
+		     (1 << RG_DP_BBPLL_SDM_EDGE_SFT));
+		SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval);
+		regval &=
+		    ~((1 << RG_DP_BBPLL_PD_SFT) |
+		      (1 << RG_DP_BBPLL_SDM_EDGE_SFT));
+		SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval);
+		mdelay(10);
+	}
+	if (ret == 0)
+		ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_phy_tbl);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xEAAAAAAA);
+	SMAC_REG_READ(sh, ADR_TRX_DUMMY_REGISTER, &regval);
+	if (regval != 0xEAAAAAAA) {
+		dev_warn(sh->sc->dev, "Unexpected register value\n");
+		WARN_ON(1);
+	}
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_PAD53, 0x21);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_PAD54, 0x3000);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_PIN_SEL_0, 0x4000);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, 0xc0000304, 0x01);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, 0xc0000308, 0x01);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_CLOCK_SELECTION, 0x3);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xAAAAAAAA);
+	if ((ret = ssv6xxx_set_channel(sh->sc, sh->cfg.def_chan)))
+		return ret;
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1,
+				     (RG_PHYRX_MD_EN_MSK | RG_PHYTX_MD_EN_MSK |
+				      RG_PHY11GN_MD_EN_MSK | RG_PHY11B_MD_EN_MSK
+				      | RG_PHYRXFIFO_MD_EN_MSK |
+				      RG_PHYTXFIFO_MD_EN_MSK |
+				      RG_PHY11BGN_MD_EN_MSK));
+	return ret;
+}
+
+static void ssv6xxx_check_mac2(struct ssv_hw *sh)
+{
+	const u8 addr_mask[6] = { 0xfd, 0xff, 0xff, 0xff, 0xff, 0xfc };
+	u8 i;
+	bool invalid = false;
+	for (i = 0; i < 6; i++) {
+		if ((ssv_cfg.maddr[0][i] & addr_mask[i]) !=
+		    (ssv_cfg.maddr[1][i] & addr_mask[i])) {
+			invalid = true;
+			dev_dbg(sh->sc->dev, " i %d , mac1[i] %x, mac2[i] %x, mask %x \n", i,
+			       ssv_cfg.maddr[0][i], ssv_cfg.maddr[1][i],
+			       addr_mask[i]);
+			break;
+		}
+	}
+	if (invalid) {
+		memcpy(&ssv_cfg.maddr[1][0], &ssv_cfg.maddr[0][0], 6);
+		ssv_cfg.maddr[1][5] ^= 0x01;
+		if (ssv_cfg.maddr[1][5] < ssv_cfg.maddr[0][5]) {
+			u8 temp;
+			temp = ssv_cfg.maddr[0][5];
+			ssv_cfg.maddr[0][5] = ssv_cfg.maddr[1][5];
+			ssv_cfg.maddr[1][5] = temp;
+			sh->cfg.maddr[0][5] = ssv_cfg.maddr[0][5];
+		}
+		dev_warn(sh->sc->dev, "MAC 2 address invalid!!\n");
+		dev_warn(sh->sc->dev, "After modification, MAC1 %pM, MAC2 %pM\n",
+		       ssv_cfg.maddr[0], ssv_cfg.maddr[1]);
+	}
+}
+
+static int ssv6xxx_read_configuration(struct ssv_hw *sh)
+{
+	extern u32 sdio_sr_bhvr;
+	if (is_valid_ether_addr(&ssv_cfg.maddr[0][0]))
+		memcpy(&sh->cfg.maddr[0][0], &ssv_cfg.maddr[0][0], ETH_ALEN);
+	if (is_valid_ether_addr(&ssv_cfg.maddr[1][0])) {
+		ssv6xxx_check_mac2(sh);
+		memcpy(&sh->cfg.maddr[1][0], &ssv_cfg.maddr[1][0], ETH_ALEN);
+	}
+	if (ssv_cfg.hw_caps)
+		sh->cfg.hw_caps = ssv_cfg.hw_caps;
+	else
+		sh->cfg.hw_caps = SSV6200_HW_CAP_HT |
+		    SSV6200_HW_CAP_2GHZ |
+		    SSV6200_HW_CAP_SECURITY |
+		    SSV6200_HW_CAP_P2P |
+		    SSV6200_HT_CAP_SGI_20 |
+		    SSV6200_HW_CAP_AMPDU_RX |
+		    SSV6200_HW_CAP_AMPDU_TX | SSV6200_HW_CAP_AP;
+	if (ssv_cfg.def_chan)
+		sh->cfg.def_chan = ssv_cfg.def_chan;
+	else
+		sh->cfg.def_chan = 6;
+	sh->cfg.use_wpa2_only = ssv_cfg.use_wpa2_only;
+	if (ssv_cfg.crystal_type == 26)
+		sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_26M;
+	else if (ssv_cfg.crystal_type == 40)
+		sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_40M;
+	else if (ssv_cfg.crystal_type == 24)
+		sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_24M;
+	else {
+		dev_warn(sh->sc->dev, "Please redefine xtal_clock(wifi.cfg)!!\n");
+		WARN_ON(1);
+		return 1;
+	}
+	if (ssv_cfg.volt_regulator < 2)
+		sh->cfg.volt_regulator = ssv_cfg.volt_regulator;
+	else {
+		dev_warn(sh->sc->dev, "Please redefine volt_regulator(wifi.cfg)!!\n");
+		WARN_ON(1);
+		return 1;
+	}
+	sh->cfg.wifi_tx_gain_level_gn = ssv_cfg.wifi_tx_gain_level_gn;
+	sh->cfg.wifi_tx_gain_level_b = ssv_cfg.wifi_tx_gain_level_b;
+	sh->cfg.rssi_ctl = ssv_cfg.rssi_ctl;
+	sh->cfg.sr_bhvr = ssv_cfg.sr_bhvr;
+	sdio_sr_bhvr = ssv_cfg.sr_bhvr;
+	sh->cfg.force_chip_identity = ssv_cfg.force_chip_identity;
+	strncpy(sh->cfg.firmware_path, ssv_cfg.firmware_path,
+		sizeof(sh->cfg.firmware_path) - 1);
+	strncpy(sh->cfg.flash_bin_path, ssv_cfg.flash_bin_path,
+		sizeof(sh->cfg.flash_bin_path) - 1);
+	strncpy(sh->cfg.mac_address_path, ssv_cfg.mac_address_path,
+		sizeof(sh->cfg.mac_address_path) - 1);
+	strncpy(sh->cfg.mac_output_path, ssv_cfg.mac_output_path,
+		sizeof(sh->cfg.mac_output_path) - 1);
+	sh->cfg.ignore_efuse_mac = ssv_cfg.ignore_efuse_mac;
+	sh->cfg.mac_address_mode = ssv_cfg.mac_address_mode;
+	return 0;
+}
+
+static int ssv6xxx_read_hw_info(struct ssv_softc *sc)
+{
+	struct ssv_hw *sh;
+	sh = kzalloc(sizeof(struct ssv_hw), GFP_KERNEL);
+	if (sh == NULL)
+		return -ENOMEM;
+	memset((void *)sh, 0, sizeof(struct ssv_hw));
+	sc->sh = sh;
+	sh->sc = sc;
+	sh->priv = sc->dev->platform_data;
+	if (ssv6xxx_read_configuration(sh))
+		return -ENOMEM;
+	sh->hci.dev = sc->dev;
+	sh->hci.hci_ops = NULL;
+	sh->hci.hci_rx_cb = ssv6200_rx;
+	sh->hci.rx_cb_args = (void *)sc;
+	sh->hci.hci_tx_cb = ssv6xxx_tx_cb;
+	sh->hci.tx_cb_args = (void *)sc;
+	sh->hci.hci_skb_update_cb = ssv6xxx_tx_rate_update;
+	sh->hci.skb_update_args = (void *)sc;
+	sh->hci.hci_tx_flow_ctrl_cb = ssv6200_tx_flow_control;
+	sh->hci.tx_fctrl_cb_args = (void *)sc;
+	sh->hci.hci_tx_q_empty_cb = ssv6xxx_tx_q_empty_cb;
+	sh->hci.tx_q_empty_args = (void *)sc;
+	sh->hci.if_ops = sh->priv->ops;
+	sh->hci.hci_tx_buf_free_cb = ssv6xxx_txbuf_free_skb;
+	sh->hci.tx_buf_free_args = (void *)sc;
+	return 0;
+}
+
+static int ssv6xxx_init_device(struct ssv_softc *sc, const char *name)
+{
+	struct ieee80211_hw *hw = sc->hw;
+	struct ssv_hw *sh;
+	int error = 0;
+	BUG_ON(!sc->dev->platform_data);
+	if ((error = ssv6xxx_read_hw_info(sc)) != 0) {
+		return error;
+	}
+	sh = sc->sh;
+	if (sh->cfg.hw_caps == 0)
+		return -1;
+	ssv6xxx_hci_register(&sh->hci);
+	efuse_read_all_map(sh);
+	if ((error = ssv6xxx_init_softc(sc)) != 0) {
+		ssv6xxx_deinit_softc(sc);
+		ssv6xxx_hci_deregister();
+		kfree(sh);
+		return error;
+	}
+	if ((error = ssv6xxx_init_hw(sc->sh)) != 0) {
+		ssv6xxx_deinit_hw(sc);
+		ssv6xxx_deinit_softc(sc);
+		ssv6xxx_hci_deregister();
+		kfree(sh);
+		return error;
+	}
+	if ((error = ieee80211_register_hw(hw)) != 0) {
+		dev_err(sc->dev, "Failed to register ieee80211 wireless device. ret=%d.\n", error);
+		ssv6xxx_deinit_hw(sc);
+		ssv6xxx_deinit_softc(sc);
+		ssv6xxx_hci_deregister();
+		kfree(sh);
+		return error;
+	}
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	ssv6xxx_init_debugfs(sc, name);
+#endif
+	return 0;
+}
+
+static void ssv6xxx_deinit_device(struct ssv_softc *sc)
+{
+	dev_dbg(sc->dev, "%s(): \n", __FUNCTION__);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	ssv6xxx_deinit_debugfs(sc);
+#endif
+	ssv6xxx_rf_disable(sc->sh);
+	ieee80211_unregister_hw(sc->hw);
+	ssv6xxx_deinit_hw(sc);
+	ssv6xxx_deinit_softc(sc);
+	ssv6xxx_hci_deregister();
+	kfree(sc->sh);
+}
+
+extern struct ieee80211_ops ssv6200_ops;
+int ssv6xxx_dev_probe(struct platform_device *pdev)
+{
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+	extern struct ssv_softc *ssv_dbg_sc;
+#endif
+#ifdef CONFIG_SSV_SMARTLINK
+	extern struct ssv_softc *ssv_smartlink_sc;
+#endif
+	struct ssv_softc *softc;
+	struct ieee80211_hw *hw;
+	int ret;
+	if (!pdev->dev.platform_data) {
+		dev_err(&pdev->dev, "no platform data specified!\n");
+		return -EINVAL;
+	}
+	hw = ieee80211_alloc_hw(sizeof(struct ssv_softc), &ssv6200_ops);
+	if (hw == NULL) {
+		dev_err(&pdev->dev, "Could not allocate memory for ieee80211 wireless device\n");
+		return -ENOMEM;
+	}
+	SET_IEEE80211_DEV(hw, &pdev->dev);
+	dev_set_drvdata(&pdev->dev, hw);
+	memset((void *)hw->priv, 0, sizeof(struct ssv_softc));
+	softc = hw->priv;
+	softc->hw = hw;
+	softc->dev = &pdev->dev;
+	//SET_IEEE80211_PERM_ADDR(hw, (const u8 *)&softc->sh->maddr[0]);
+	ret = ssv6xxx_init_device(softc, pdev->name);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to initialize device\n");
+		ieee80211_free_hw(hw);
+		return ret;
+	}
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+	ssv_dbg_sc = softc;
+#endif
+#ifdef CONFIG_SSV_SMARTLINK
+	ssv_smartlink_sc = softc;
+#endif
+	wiphy_info(hw->wiphy, "%s\n", "SSV6200 of South Silicon Valley");
+	return 0;
+}
+
+EXPORT_SYMBOL(ssv6xxx_dev_probe);
+int ssv6xxx_dev_remove(struct platform_device *pdev)
+{
+	struct ieee80211_hw *hw = dev_get_drvdata(&pdev->dev);
+	struct ssv_softc *softc = hw->priv;
+	dev_dbg(&pdev->dev, "ssv6xxx_dev_remove(): pdev=%p, hw=%p\n", pdev, hw);
+	ssv6xxx_deinit_device(softc);
+	dev_dbg(&pdev->dev, "ieee80211_free_hw(): \n");
+	ieee80211_free_hw(hw);
+	dev_info(&pdev->dev, "driver unloaded\n");
+	return 0;
+}
+
+EXPORT_SYMBOL(ssv6xxx_dev_remove);
+static const struct platform_device_id ssv6xxx_id_table[] = {
+	{
+	 .name = "ssv6200",
+	 .driver_data = 0x00,
+	 },
+	{},
+};
+
+MODULE_DEVICE_TABLE(platform, ssv6xxx_id_table);
+static struct platform_driver ssv6xxx_driver = {
+	.probe = ssv6xxx_dev_probe,
+	.remove = ssv6xxx_dev_remove,
+	.id_table = ssv6xxx_id_table,
+	.driver = {
+		   .name = "SSV WLAN driver",
+		   .owner = THIS_MODULE,
+		   }
+};
+
+int ssv6xxx_init(void)
+{
+	extern void *ssv_dbg_phy_table;
+	extern u32 ssv_dbg_phy_len;
+	extern void *ssv_dbg_rf_table;
+	extern u32 ssv_dbg_rf_len;
+	ssv_dbg_phy_table = (void *)ssv6200_phy_tbl;
+	ssv_dbg_phy_len =
+	    sizeof(ssv6200_phy_tbl) / sizeof(struct ssv6xxx_dev_table);
+	ssv_dbg_rf_table = (void *)ssv6200_rf_tbl;
+	ssv_dbg_rf_len =
+	    sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+	return platform_driver_register(&ssv6xxx_driver);
+}
+
+void ssv6xxx_exit(void)
+{
+	platform_driver_unregister(&ssv6xxx_driver);
+}
+
+EXPORT_SYMBOL(ssv6xxx_init);
+EXPORT_SYMBOL(ssv6xxx_exit);
diff --git a/drivers/net/wireless/ssv6051/smac/init.h b/drivers/net/wireless/ssv6051/smac/init.h
new file mode 100644
index 00000000000..97994d00d4d
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/init.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _INIT_H_
+#define _INIT_H_
+int ssv6xxx_init_mac(struct ssv_hw *sh);
+int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg);
+void ssv6xxx_deinit_mac(struct ssv_softc *sc);
+void ssv6xxx_restart_hw(struct ssv_softc *sc);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/lib.c b/drivers/net/wireless/ssv6051/smac/lib.c
new file mode 100644
index 00000000000..ccf0974b0f2
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/lib.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200.h>
+#include "lib.h"
+struct sk_buff *ssv_skb_alloc(s32 len)
+{
+	struct sk_buff *skb;
+	skb = __dev_alloc_skb(len + 128, GFP_KERNEL);
+	if (skb != NULL) {
+		skb_put(skb, 0x20);
+		skb_pull(skb, 0x20);
+	}
+	return skb;
+}
+
+void ssv_skb_free(struct sk_buff *skb)
+{
+	dev_kfree_skb_any(skb);
+}
diff --git a/drivers/net/wireless/ssv6051/smac/lib.h b/drivers/net/wireless/ssv6051/smac/lib.h
new file mode 100644
index 00000000000..266cf7afac9
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/lib.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _LIB_H_
+#define _LIB_H_
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+struct sk_buff *ssv_skb_alloc(s32 len);
+void ssv_skb_free(struct sk_buff *skb);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/linux_80211.h b/drivers/net/wireless/ssv6051/smac/linux_80211.h
new file mode 100644
index 00000000000..e268808e3c9
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/linux_80211.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _LINUX_80211_H_
+#define _LINUX_80211_H_
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
+#define INDEX_80211_BAND_2GHZ IEEE80211_BAND_2GHZ
+#else
+#define INDEX_80211_BAND_2GHZ NL80211_BAND_2GHZ
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/p2p.c b/drivers/net/wireless/ssv6051/smac/p2p.c
new file mode 100644
index 00000000000..60fd8effd6e
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/p2p.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200.h>
+#include <linux/types.h>
+#include <linux/nl80211.h>
+#include <net/mac80211.h>
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <linux/kthread.h>
+#include <net/mac80211.h>
+#include <ssv6200.h>
+#include "p2p.h"
+#include "dev.h"
+#include "lib.h"
+#ifdef CONFIG_P2P_NOA
+#define P2P_IE_VENDOR_TYPE 0x506f9a09
+#define P2P_NOA_DETECT_INTERVAL (5 * HZ)
+#ifndef MAC2STR
+#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
+#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
+#define COMPACT_MACSTR "%02x%02x%02x%02x%02x%02x"
+#endif
+void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
+			  struct ssv6xxx_p2p_noa_param *p2p_noa_param);
+static inline u32 WPA_GET_BE32(const u8 * a)
+{
+	return (a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3];
+}
+
+static inline u16 WPA_GET_LE16(const u8 * a)
+{
+	return (a[1] << 8) | a[0];
+}
+
+static inline u32 WPA_GET_LE32(const u8 * a)
+{
+	return (a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0];
+}
+
+#define IEEE80211_HDRLEN 24
+enum p2p_attr_id {
+	P2P_ATTR_STATUS = 0,
+	P2P_ATTR_MINOR_REASON_CODE = 1,
+	P2P_ATTR_CAPABILITY = 2,
+	P2P_ATTR_DEVICE_ID = 3,
+	P2P_ATTR_GROUP_OWNER_INTENT = 4,
+	P2P_ATTR_CONFIGURATION_TIMEOUT = 5,
+	P2P_ATTR_LISTEN_CHANNEL = 6,
+	P2P_ATTR_GROUP_BSSID = 7,
+	P2P_ATTR_EXT_LISTEN_TIMING = 8,
+	P2P_ATTR_INTENDED_INTERFACE_ADDR = 9,
+	P2P_ATTR_MANAGEABILITY = 10,
+	P2P_ATTR_CHANNEL_LIST = 11,
+	P2P_ATTR_NOTICE_OF_ABSENCE = 12,
+	P2P_ATTR_DEVICE_INFO = 13,
+	P2P_ATTR_GROUP_INFO = 14,
+	P2P_ATTR_GROUP_ID = 15,
+	P2P_ATTR_INTERFACE = 16,
+	P2P_ATTR_OPERATING_CHANNEL = 17,
+	P2P_ATTR_INVITATION_FLAGS = 18,
+	P2P_ATTR_OOB_GO_NEG_CHANNEL = 19,
+	P2P_ATTR_VENDOR_SPECIFIC = 221
+};
+struct ssv6xxx_p2p_noa_attribute {
+	u8 index;
+	u16 ctwindows_oppps;
+	struct ssv6xxx_p2p_noa_param noa_param;
+};
+extern void _ssv6xxx_hexdump(const char *title, const u8 * buf, size_t len);
+bool p2p_find_noa(const u8 * ies, struct ssv6xxx_p2p_noa_attribute *noa_attr)
+{
+	const u8 *end, *pos, *ie;
+	u32 len;
+	len = ie[1] - 4;
+	pos = ie + 6;
+	end = pos + len;
+	while (pos < end) {
+		u16 attr_len;
+		if (pos + 2 >= end) {
+			return false;
+		}
+		attr_len = WPA_GET_LE16(pos + 1);
+		if (pos + 3 + attr_len > end) {
+			return false;
+		}
+		if (pos[0] != P2P_ATTR_NOTICE_OF_ABSENCE) {
+			pos += 3 + attr_len;
+			continue;
+		}
+		if (attr_len < 15) {
+			printk
+			    ("*********************NOA descriptor does not exist len[%d]\n",
+			     attr_len);
+			break;
+		}
+		if (attr_len > 15)
+			printk("More than one NOA descriptor\n");
+		noa_attr->index = pos[3];
+		noa_attr->ctwindows_oppps = pos[4];
+		noa_attr->noa_param.count = pos[5];
+		noa_attr->noa_param.duration = WPA_GET_LE32(&pos[6]);
+		noa_attr->noa_param.interval = WPA_GET_LE32(&pos[10]);
+		noa_attr->noa_param.start_time = WPA_GET_LE32(&pos[14]);
+		return true;
+	}
+	return false;
+}
+
+bool p2p_get_attribute_noa(const u8 * ies, u32 oui_type,
+			   struct ssv6xxx_p2p_noa_attribute *noa_attr)
+{
+	const u8 *end, *pos, *ie;
+	u32 len;
+	pos = ies;
+	end = ies + ies_len;
+	ie = NULL;
+	while (pos + 1 < end) {
+		if (pos + 2 + pos[1] > end)
+			return false;
+		if (pos[0] == WLAN_EID_VENDOR_SPECIFIC && pos[1] >= 4 &&
+		    WPA_GET_BE32(&pos[2]) == oui_type) {
+			ie = pos;
+			if (p2p_find_noa(ie, 0, noa_attr) == true)
+				return true;
+		}
+		pos += 2 + pos[1];
+	}
+	return false;
+}
+
+void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb)
+{
+	struct cfg_host_event *host_event;
+	struct ssv62xx_noa_evt *noa_evt;
+	host_event = (struct cfg_host_event *)skb->data;
+	noa_evt = (struct ssv62xx_noa_evt *)&host_event->dat[0];
+	switch (noa_evt->evt_id) {
+	case SSV6XXX_NOA_START:
+		sc->p2p_noa.active_noa_vif |= (1 << noa_evt->vif);
+		printk("SSV6XXX_NOA_START===>[%08x]\n",
+		       sc->p2p_noa.active_noa_vif);
+		break;
+	case SSV6XXX_NOA_STOP:
+		sc->p2p_noa.active_noa_vif &= ~(1 << noa_evt->vif);
+		printk("SSV6XXX_NOA_STOP===>[%08x]\n",
+		       sc->p2p_noa.active_noa_vif);
+		break;
+	default:
+		printk("--------->NOA wrong command<---------\n");
+		break;
+	}
+}
+
+void ssv6xxx_noa_reset(struct ssv_softc *sc)
+{
+	unsigned long flags;
+	printk("Reset NOA param...\n");
+	spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
+	memset(&sc->p2p_noa.noa_detect, 0,
+	       sizeof(struct ssv_p2p_noa_detect) * SSV_NUM_VIF);
+	sc->p2p_noa.active_noa_vif = 0;
+	sc->p2p_noa.monitor_noa_vif = 0;
+	spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
+}
+
+void ssv6xxx_noa_host_stop_noa(struct ssv_softc *sc, u8 vif_id)
+{
+	struct ssv6xxx_p2p_noa_attribute noa_attr;
+	if (sc->p2p_noa.noa_detect[vif_id].p2p_noa_index >= 0) {
+		sc->p2p_noa.noa_detect[vif_id].p2p_noa_index = -1;
+		sc->p2p_noa.active_noa_vif &= ~(1 << vif_id);
+		memset(&sc->p2p_noa.noa_detect[vif_id].noa_param_cmd, 0,
+		       sizeof(struct ssv6xxx_p2p_noa_param));
+		printk("->remove NOA operating vif[%d]\n", vif_id);
+		noa_attr.noa_param.enable = 0;
+		noa_attr.noa_param.vif_id = vif_id;
+		ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param);
+	}
+}
+
+void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr *hdr,
+			u32 len)
+{
+	int i;
+	unsigned long flags;
+	struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
+	struct ssv6xxx_p2p_noa_attribute noa_attr;
+	spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
+	if (sc->p2p_noa.monitor_noa_vif == 0)
+		goto out;
+	for (i = 0; i < SSV_NUM_VIF; i++) {
+		if (sc->p2p_noa.noa_detect[i].noa_addr == NULL)
+			continue;
+		if (memcmp(mgmt->bssid, sc->p2p_noa.noa_detect[i].noa_addr, 6)
+		    != 0)
+			continue;
+		if (sc->p2p_noa.active_noa_vif &&
+		    ((sc->p2p_noa.active_noa_vif & 1 << i) == 0))
+			continue;
+		sc->p2p_noa.noa_detect[i].last_rx = jiffies;
+		if (p2p_get_attribute_noa((const u8 *)mgmt->u.beacon.variable,
+					  len - (IEEE80211_HDRLEN +
+						 sizeof(mgmt->u.beacon)),
+					  P2P_IE_VENDOR_TYPE,
+					  &noa_attr) == false) {
+			continue;
+		}
+		if (sc->p2p_noa.noa_detect[i].p2p_noa_index == noa_attr.index) {
+			goto out;
+		}
+		printk(MACSTR "->set NOA element\n", MAC2STR(mgmt->bssid));
+		sc->p2p_noa.active_noa_vif |= (1 << i);
+		sc->p2p_noa.noa_detect[i].p2p_noa_index = noa_attr.index;
+		memcpy(&sc->p2p_noa.noa_detect[i].noa_param_cmd,
+		       &noa_attr.noa_param,
+		       sizeof(struct ssv6xxx_p2p_noa_param));
+		noa_attr.noa_param.enable = 1;
+		noa_attr.noa_param.vif_id = i;
+		memcpy(noa_attr.noa_param.addr, hdr->addr2, 6);
+		ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param);
+	}
+ out:
+	spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
+}
+
+void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc,
+				enum ssv6xxx_noa_conf conf, u8 vif_idx)
+{
+	unsigned long flags;
+	if (sc->vif_info[vif_idx].vif->type != NL80211_IFTYPE_STATION ||
+	    sc->vif_info[vif_idx].vif->p2p != true)
+		return;
+	spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
+	printk("====>[NOA]ssv6xxx_noa_hdl_bss_change conf[%d] vif_idx[%d]\n",
+	       conf, vif_idx);
+	switch (conf) {
+	case MONITOR_NOA_CONF_ADD:
+		memset(&sc->p2p_noa.noa_detect[vif_idx], 0,
+		       sizeof(struct ssv_p2p_noa_detect));
+		sc->p2p_noa.noa_detect[vif_idx].noa_addr =
+		    sc->vif_info[vif_idx].vif->bss_conf.bssid;
+		sc->p2p_noa.noa_detect[vif_idx].p2p_noa_index = -1;
+		sc->p2p_noa.noa_detect[vif_idx].last_rx = jiffies;
+		sc->p2p_noa.monitor_noa_vif |= 1 << vif_idx;
+		break;
+	case MONITOR_NOA_CONF_REMOVE:
+		sc->p2p_noa.monitor_noa_vif &= ~(1 << vif_idx);
+		sc->p2p_noa.noa_detect[vif_idx].noa_addr = NULL;
+		ssv6xxx_noa_host_stop_noa(sc, vif_idx);
+		break;
+	default:
+		break;
+	}
+	spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
+}
+
+void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
+			  struct ssv6xxx_p2p_noa_param *p2p_noa_param)
+{
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	int retry_cnt = 5;
+	skb =
+	    ssv_skb_alloc(HOST_CMD_HDR_LEN +
+			  sizeof(struct ssv6xxx_p2p_noa_param));
+	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param);
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_SET_NOA;
+	host_cmd->len = skb->data_len;
+	memcpy(host_cmd->dat32, p2p_noa_param,
+	       sizeof(struct ssv6xxx_p2p_noa_param));
+	printk
+	    ("Noa cmd NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]vif[%d]\n\n",
+	     p2p_noa_param->enable, p2p_noa_param->interval,
+	     p2p_noa_param->duration, p2p_noa_param->start_time,
+	     p2p_noa_param->count, p2p_noa_param->addr[0],
+	     p2p_noa_param->addr[1], p2p_noa_param->addr[2],
+	     p2p_noa_param->addr[3], p2p_noa_param->addr[4],
+	     p2p_noa_param->addr[5], p2p_noa_param->vif_id);
+	while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
+		printk(KERN_INFO "NOA cmd retry=%d!!\n", retry_cnt);
+		retry_cnt--;
+	}
+	ssv_skb_free(skb);
+}
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/p2p.h b/drivers/net/wireless/ssv6051/smac/p2p.h
new file mode 100644
index 00000000000..a5bb99c61bb
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/p2p.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _P2P_H_
+#define _P2P_H_
+#include <net/mac80211.h>
+#include <ssv6200.h>
+#include "drv_comm.h"
+#ifdef CONFIG_P2P_NOA
+#define P2P_MAX_NOA_INTERFACE 1
+struct ssv_p2p_noa_detect {
+	const u8 *noa_addr;
+	s16 p2p_noa_index;
+	unsigned long last_rx;
+	struct ssv6xxx_p2p_noa_param noa_param_cmd;
+};
+struct ssv_p2p_noa {
+	spinlock_t p2p_config_lock;
+	struct ssv_p2p_noa_detect noa_detect[SSV_NUM_VIF];
+	u8 active_noa_vif;
+	u8 monitor_noa_vif;
+};
+enum ssv_cmd_state {
+	SSC_CMD_STATE_IDLE,
+	SSC_CMD_STATE_WAIT_RSP,
+};
+struct ssv_cmd_Info {
+	struct sk_buff_head cmd_que;
+	struct sk_buff_head evt_que;
+	enum ssv_cmd_state state;
+};
+enum ssv6xxx_noa_conf {
+	MONITOR_NOA_CONF_ADD,
+	MONITOR_NOA_CONF_REMOVE,
+};
+struct ssv_softc;
+void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb);
+void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc,
+				enum ssv6xxx_noa_conf conf, u8 vif_idx);
+void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb);
+void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr *hdr,
+			u32 len);
+void ssv6xxx_noa_reset(struct ssv_softc *sc);
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/sar.c b/drivers/net/wireless/ssv6051/smac/sar.c
new file mode 100644
index 00000000000..44a47a5c7a0
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/sar.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200_reg.h>
+#include <ssv6200_aux.h>
+#include <linux/fs.h>
+#include "dev.h"
+#include "sar.h"
+
+WIFI_FLASH_CCFG flash_cfg = {
+	//16bytes
+	0x6051, 0x3009, 0x20170519, 0x1, 0x0, 0x0,
+	{			//16bytes
+	 {0x47c000, 0x47c000, 0x47c000, 0x9, 0x1d, 0x0},
+	 //16bytes
+	 {0x79807980, 0x79807980, 0x79807980, 0x9, 0x1d, 0x0}
+	 }
+};
+
+WIFI_FLASH_CCFG *pflash_cfg;
+
+struct t_sar_info sar_info[] = {
+	{SAR_LVL_INVALID, 0x0047c000, NULL},
+	{SAR_LVL_INVALID, 0x79807980, NULL}
+};
+
+int sar_info_size = sizeof(sar_info) / sizeof(sar_info[0]);
+
+static u8 get_sar_lvl(u32 sar)
+{
+	static u32 prev_sar = 0;
+	int i;
+	u8 changed = 0x0;
+
+	if (sar == prev_sar)
+		return changed;
+
+	pr_debug("[thermal_sar] %d\n", (int)sar);
+
+	for (i = 0; i < sar_info_size; i++) {
+		if (sar_info[i].lvl == SAR_LVL_INVALID) {	//if driver loaded under LT/HT env, it would cause wrong settings at this time.
+			sar_info[i].lvl = SAR_LVL_RT;
+			sar_info[i].value = sar_info[i].p->rt;
+			changed |= BIT(i);
+		} else if (sar_info[i].lvl == SAR_LVL_RT) {
+			if (sar < prev_sar) {
+				if (sar <= (u32) (sar_info[i].p->lt_ts - 2)) {	//we need check if (g_tt_lt - 1) < SAR_MIN
+					sar_info[i].lvl = SAR_LVL_LT;
+					sar_info[i].value = sar_info[i].p->lt;
+					changed |= BIT(i);
+				}
+			} else if (sar > prev_sar) {
+				if (sar >= (u32) (sar_info[i].p->ht_ts + 2)) {	//we need check if (g_tt_lt + 1) > SAR_MAX
+					sar_info[i].lvl = SAR_LVL_HT;
+					sar_info[i].value = sar_info[i].p->ht;
+					changed |= BIT(i);
+				}
+			}
+		} else if (sar_info[i].lvl == SAR_LVL_LT) {
+			if (sar >= (u32) (sar_info[i].p->lt_ts + 2)) {
+				sar_info[i].lvl = SAR_LVL_RT;
+				sar_info[i].value = sar_info[i].p->rt;
+				changed |= BIT(i);
+			}
+		} else if (sar_info[i].lvl == SAR_LVL_HT) {
+			if (sar <= (u32) (sar_info[i].p->ht_ts - 2)) {
+				sar_info[i].lvl = SAR_LVL_RT;
+				sar_info[i].value = sar_info[i].p->rt;
+				changed |= BIT(i);
+			}
+		}
+	}
+	if (changed) {
+		pr_debug("changed: 0x%x\n", changed);
+	}
+	prev_sar = sar;
+	return changed;
+}
+
+void sar_monitor(u32 curr_sar, struct ssv_softc *sc)
+{
+	//static u32 prev_sar_lvl = SAR_LVL_INVALID; //sar = 0, temparature < -25C
+	u8 changed;
+	changed = get_sar_lvl(curr_sar);
+
+	if (changed & BIT(SAR_TXGAIN_INDEX)) {
+		dev_dbg(sc->dev, "TXGAIN: 0x%08x\n", sar_info[SAR_TXGAIN_INDEX].value);
+		SMAC_REG_WRITE(sc->sh, ADR_TX_GAIN_FACTOR,
+			       sar_info[SAR_TXGAIN_INDEX].value);
+	}
+	if (changed & BIT(SAR_XTAL_INDEX)) {
+		dev_dbg(sc->dev, "XTAL: 0x%08x\n", sar_info[SAR_XTAL_INDEX].value);
+		SMAC_REG_WRITE(sc->sh, ADR_SYN_KVCO_XO_FINE_TUNE_CBANK,
+			       sar_info[SAR_XTAL_INDEX].value);
+	}
+}
+
+/*
+    SET_RG_SARADC_THERMAL(1);     //ce010030[26]
+    SET_RG_EN_SARADC(1);          //ce010030[30]
+    while(!GET_SAR_ADC_FSM_RDY);  //ce010094[23]
+    sar_code = GET_RG_SARADC_BIT; //ce010094[21:16]
+    SET_RG_SARADC_THERMAL(0);
+    SET_RG_EN_SARADC(0);
+*/
+void thermal_monitor(struct work_struct *work)
+{
+	struct ssv_softc *sc =
+	    container_of(work, struct ssv_softc, thermal_monitor_work.work);
+	u32 curr_sar;
+
+	u32 temp;
+	if (sc->ps_status == PWRSV_PREPARE) {
+		dev_dbg(sc->dev, "sar PWRSV_PREPARE\n");
+		return;
+	}
+
+	mutex_lock(&sc->mutex);
+	SMAC_REG_READ(sc->sh, ADR_RX_11B_CCA_1, &temp);
+	if (temp == RX_11B_CCA_IN_SCAN) {
+		dev_dbg(sc->dev, "in scan\n");
+		mutex_unlock(&sc->mutex);
+		queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
+				   THERMAL_MONITOR_TIME);
+		return;
+	}
+	SMAC_REG_READ(sc->sh, ADR_RX_ADC_REGISTER, &temp);
+	//printk("ori %08x:%08x\n", ADR_RX_ADC_REGISTER, temp);
+	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER,
+			  (1 << RG_SARADC_THERMAL_SFT), RG_SARADC_THERMAL_MSK);
+	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, (1 << RG_EN_SARADC_SFT),
+			  RG_EN_SARADC_MSK);
+
+	do {
+		msleep(1);
+		SMAC_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_1, &temp);
+	} while (((temp & SAR_ADC_FSM_RDY_MSK) >> SAR_ADC_FSM_RDY_SFT) != 1);
+	//printk("SAR_ADC_FSM_RDY_STAT %d\n", (temp & SAR_ADC_FSM_RDY_MSK) >> SAR_ADC_FSM_RDY_SFT);
+	curr_sar = (temp & RG_SARADC_BIT_MSK) >> RG_SARADC_BIT_SFT;
+	SMAC_REG_READ(sc->sh, ADR_RX_ADC_REGISTER, &temp);
+
+	//printk("new %08x:%08x\n", ADR_RX_ADC_REGISTER, temp);
+
+	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER,
+			  (0 << RG_SARADC_THERMAL_SFT), RG_SARADC_THERMAL_MSK);
+	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, (0 << RG_EN_SARADC_SFT),
+			  RG_EN_SARADC_MSK);
+	sar_monitor(curr_sar, sc);
+
+	mutex_unlock(&sc->mutex);
+
+	queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
+			   THERMAL_MONITOR_TIME);
+}
+
+int get_flash_info(struct ssv_softc *sc)
+{
+	struct file *fp = (struct file *)NULL;
+	int i, ret;
+
+	pflash_cfg = &flash_cfg;
+
+	if (sc->sh->cfg.flash_bin_path[0] != 0x00) {
+		fp = filp_open(sc->sh->cfg.flash_bin_path, O_RDONLY, 0);
+		if (IS_ERR(fp) || fp == NULL) {
+			fp = filp_open(SEC_CFG_BIN_NAME, O_RDONLY, 0);
+		}
+	} else {
+		fp = filp_open(DEFAULT_CFG_BIN_NAME, O_RDONLY, 0);
+		if (IS_ERR(fp) || fp == NULL) {
+			fp = filp_open(SEC_CFG_BIN_NAME, O_RDONLY, 0);
+		}
+	}
+	if (IS_ERR(fp) || fp == NULL) {
+		dev_info(sc->dev, "flash_file %s not found, disable sar\n",
+		       DEFAULT_CFG_BIN_NAME);
+		//WARN_ON(1);
+		ret = 0;
+		return ret;
+	}
+
+	fp->f_op->read(fp, (char *)pflash_cfg, sizeof(flash_cfg), &fp->f_pos);
+
+	filp_close(fp, NULL);
+	ret = 1;
+
+	for (i = 0; i < sar_info_size; i++) {
+		sar_info[i].p = &flash_cfg.sar_rlh[i];
+		dev_dbg(sc->dev, "rt = %x, lt = %x, ht = %x\n", sar_info[i].p->rt,
+		       sar_info[i].p->lt, sar_info[i].p->ht);
+		dev_dbg(sc->dev, "lt_ts = %x, ht_ts = %x\n", sar_info[i].p->lt_ts,
+		       sar_info[i].p->ht_ts);
+	}
+	return ret;
+}
diff --git a/drivers/net/wireless/ssv6051/smac/sar.h b/drivers/net/wireless/ssv6051/smac/sar.h
new file mode 100644
index 00000000000..291d58f236e
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/sar.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _CFG_H_
+#define _CFG_H_
+#include <linux/kthread.h>
+
+#define SAR_XTAL_INDEX     (0)
+#define SAR_TXGAIN_INDEX    (1)
+#define THERMAL_MONITOR_TIME (10 * HZ)
+#define DEFAULT_CFG_BIN_NAME "/lib/firmware/ssv6051_sar.bin"
+#define SEC_CFG_BIN_NAME "/lib/firmware/ssv6xxx_sar.bin"
+enum {
+	SAR_LVL_LT,
+	SAR_LVL_RT,
+	SAR_LVL_HT,
+	SAR_LVL_INVALID
+};
+
+struct flash_thermal_info {
+	u32 rt;
+	u32 lt;
+	u32 ht;
+	u8 lt_ts;
+	u8 ht_ts;
+	u16 reserve;
+};
+typedef struct t_WIFI_FLASH_CCFG {
+	//16bytes
+	u16 chip_id;
+	u16 sid;
+	u32 date;
+	u16 version;
+	u16 reserve_1;
+	u32 reserve_2;
+	//16bytes
+	struct flash_thermal_info sar_rlh[2];
+} WIFI_FLASH_CCFG;
+
+struct t_sar_info {
+	u32 lvl;
+	u32 value;
+	struct flash_thermal_info *p;
+};
+
+void thermal_monitor(struct work_struct *work);
+int get_flash_info(struct ssv_softc *sc);
+void flash_hexdump(void);
+
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/sec.h b/drivers/net/wireless/ssv6051/smac/sec.h
new file mode 100644
index 00000000000..04a0f47c8ce
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/sec.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SEC_H
+#define SEC_H
+#include <linux/types.h>
+#include <linux/ieee80211.h>
+#include <net/mac80211.h>
+#define CCMP_TK_LEN 16
+#define TKIP_KEY_LEN 32
+#define WEP_KEY_LEN 13
+struct ssv_crypto_ops {
+	const char *name;
+	struct list_head list;
+	void *(*init)(int keyidx);
+	void (*deinit)(void *priv);
+	int (*encrypt_mpdu)(struct sk_buff * skb, int hdr_len, void *priv);
+	int (*decrypt_mpdu)(struct sk_buff * skb, int hdr_len, void *priv);
+	int (*encrypt_msdu)(struct sk_buff * skb, int hdr_len, void *priv);
+	int (*decrypt_msdu)(struct sk_buff * skb, int keyidx, int hdr_len,
+			    void *priv);
+	int (*set_tx_pn)(u8 * seq, void *priv);
+	int (*set_key)(void *key, int len, u8 * seq, void *priv);
+	int (*get_key)(void *key, int len, u8 * seq, void *priv);
+	char *(*print_stats)(char *p, void *priv);
+	unsigned long (*get_flags)(void *priv);
+	unsigned long (*set_flags)(unsigned long flags, void *priv);
+	int extra_mpdu_prefix_len, extra_mpdu_postfix_len;
+	int extra_msdu_prefix_len, extra_msdu_postfix_len;
+};
+struct ssv_crypto_data {
+	struct ssv_crypto_ops *ops;
+	void *priv;
+	rwlock_t lock;
+};
+struct ssv_crypto_ops *get_crypto_ccmp_ops(void);
+struct ssv_crypto_ops *get_crypto_tkip_ops(void);
+struct ssv_crypto_ops *get_crypto_wep_ops(void);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/smartlink.c b/drivers/net/wireless/ssv6051/smac/smartlink.c
new file mode 100644
index 00000000000..69e8d5118e0
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/smartlink.c
@@ -0,0 +1,340 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <net/sock.h>
+#include <linux/socket.h>
+#include <linux/net.h>
+#include <asm/types.h>
+#include <linux/netlink.h>
+#include <linux/skbuff.h>
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "lib.h"
+#include "dev.h"
+#define NETLINK_SMARTLINK (31)
+#define MAX_PAYLOAD (2048)
+static struct sock *nl_sk = NULL;
+struct ssv_softc *ssv_smartlink_sc = NULL;
+EXPORT_SYMBOL(ssv_smartlink_sc);
+u32 ssv_smartlink_status = 0;
+static int _ksmartlink_start_smartlink(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+				       u32 * pOutBufLen)
+{
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s\n", __FUNCTION__);
+#endif
+	ssv_smartlink_status = 1;
+	*pOutBufLen = 0;
+	return 0;
+}
+
+int ksmartlink_smartlink_started(void)
+{
+	return ssv_smartlink_status;
+}
+
+EXPORT_SYMBOL(ksmartlink_smartlink_started);
+static int _ksmartlink_stop_smartlink(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+				      u32 * pOutBufLen)
+{
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s\n", __FUNCTION__);
+#endif
+	ssv_smartlink_status = 0;
+	*pOutBufLen = 0;
+	return 0;
+}
+
+static int _ksmartlink_set_channel(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+				   u32 * pOutBufLen)
+{
+	int ret = -10;
+	int ch = (int)(*pInBuf);
+	struct ssv_softc *sc = ssv_smartlink_sc;
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s %d\n", __FUNCTION__, ch);
+#endif
+	if (!sc) {
+		goto out;
+	}
+	mutex_lock(&sc->mutex);
+	ret = ssv6xxx_set_channel(sc, ch);
+	mutex_unlock(&sc->mutex);
+	*pOutBufLen = 0;
+ out:
+	return ret;
+}
+
+static int _ksmartlink_get_channel(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+				   u32 * pOutBufLen)
+{
+	int ret = -10;
+	int ch = 0;
+	struct ssv_softc *sc = ssv_smartlink_sc;
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s\n", __FUNCTION__);
+#endif
+	if (!sc) {
+		goto out;
+	}
+	mutex_lock(&sc->mutex);
+	ret = ssv6xxx_get_channel(sc, &ch);
+	mutex_unlock(&sc->mutex);
+	*pOutBuf = ch;
+	*pOutBufLen = 1;
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s %d\n", __FUNCTION__, ch);
+#endif
+ out:
+	return ret;
+}
+
+static int _ksmartlink_set_promisc(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+				   u32 * pOutBufLen)
+{
+	int ret = -10;
+	int accept = (int)(*pInBuf);
+	struct ssv_softc *sc = ssv_smartlink_sc;
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s %d\n", __FUNCTION__, accept);
+#endif
+	if (!sc) {
+		goto out;
+	}
+	mutex_lock(&sc->mutex);
+	ret = ssv6xxx_set_promisc(sc, accept);
+	mutex_unlock(&sc->mutex);
+	*pOutBufLen = 0;
+ out:
+	return ret;
+}
+
+static int _ksmartlink_get_promisc(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+				   u32 * pOutBufLen)
+{
+	int ret = -10;
+	int accept = (int)(*pInBuf);
+	struct ssv_softc *sc = ssv_smartlink_sc;
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s\n", __FUNCTION__);
+#endif
+	if (!sc) {
+		goto out;
+	}
+	mutex_lock(&sc->mutex);
+	ret = ssv6xxx_get_promisc(sc, &accept);
+	mutex_unlock(&sc->mutex);
+	*pOutBuf = accept;
+	*pOutBufLen = 1;
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s %d\n", __FUNCTION__, accept);
+#endif
+ out:
+	return ret;
+}
+
+#define SMARTLINK_CMD_FIXED_LEN (10)
+#define SMARTLINK_CMD_FIXED_TOT_LEN (SMARTLINK_CMD_FIXED_LEN+1)
+#define SMARTLINK_RES_FIXED_LEN (SMARTLINK_CMD_FIXED_LEN)
+#define SMARTLINK_RES_FIXED_TOT_LEN (SMARTLINK_RES_FIXED_LEN+2)
+struct ksmartlink_cmd {
+	char *cmd;
+	int (*process_func)(u8 *, u32, u8 *, u32 *);
+};
+static struct ksmartlink_cmd _ksmartlink_cmd_table[] = {
+	{"startairki", _ksmartlink_start_smartlink},
+	{"stopairkis", _ksmartlink_stop_smartlink},
+	{"setchannel", _ksmartlink_set_channel},
+	{"getchannel", _ksmartlink_get_channel},
+	{"setpromisc", _ksmartlink_set_promisc},
+	{"getpromisc", _ksmartlink_get_promisc},
+};
+
+static u32 _ksmartlink_cmd_table_size =
+    sizeof(_ksmartlink_cmd_table) / sizeof(struct ksmartlink_cmd);
+#ifdef KSMARTLINK_DEBUG
+static void _ksmartlink_hex_dump(u8 * pInBuf, u32 inBufLen)
+{
+	u32 i = 0;
+	printk(KERN_INFO "\nKernel Hex Dump(len=%d):\n", inBufLen);
+	printk(KERN_INFO ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
+	for (i = 0; i < inBufLen; i++) {
+		if ((i) && ((i & 0xf) == 0)) {
+			printk("\n");
+		}
+		printk("%02x ", pInBuf[i]);
+	}
+	printk(KERN_INFO "<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
+}
+#endif
+static int _ksmartlink_process_msg(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+				   u32 * pOutBufLen)
+{
+	int ret = 0;
+	u32 i = 0;
+	struct ksmartlink_cmd *pCmd;
+	if (!pInBuf || !pOutBuf || !pOutBufLen) {
+		printk(KERN_ERR "NULL pointer\n");
+		return -1;
+	}
+	for (i = 0; i < _ksmartlink_cmd_table_size; i++) {
+		if (!strncmp
+		    (_ksmartlink_cmd_table[i].cmd, pInBuf,
+		     SMARTLINK_CMD_FIXED_LEN)) {
+			break;
+		}
+	}
+	if (i < _ksmartlink_cmd_table_size) {
+		pCmd = &_ksmartlink_cmd_table[i];
+		if (!pCmd->process_func) {
+			printk(KERN_ERR "CMD %s has NULL process_func\n",
+			       pCmd->cmd);
+			return -3;
+		}
+		ret =
+		    pCmd->process_func(pInBuf + SMARTLINK_CMD_FIXED_LEN,
+				       inBufLen, pOutBuf, pOutBufLen);
+#ifdef CONFIG_SSV_NETLINK_RESPONSE
+		if (ret < 0) {
+			*pOutBufLen = SMARTLINK_RES_FIXED_TOT_LEN;
+		} else {
+			if (*pOutBufLen > 0) {
+				pOutBuf[SMARTLINK_RES_FIXED_LEN] = (u8) ret;
+				pOutBuf[SMARTLINK_RES_FIXED_LEN + 1] = *pOutBuf;
+			} else {
+				pOutBuf[SMARTLINK_RES_FIXED_LEN] = (u8) ret;
+				pOutBuf[SMARTLINK_RES_FIXED_LEN + 1] = 0;
+			}
+			*pOutBufLen = SMARTLINK_RES_FIXED_TOT_LEN;
+		}
+		memcpy(pOutBuf, pCmd->cmd, SMARTLINK_RES_FIXED_LEN);
+#else
+		(void)pOutBuf;
+		(void)pOutBufLen;
+#endif
+		return 0;
+	} else {
+		printk(KERN_INFO "Unknow CMD or Packet?\n");
+	}
+	return 0;
+}
+static u8 gkBuf[MAX_PAYLOAD] = { 0 };
+
+static int ssv_usr_pid = 0;
+void smartlink_nl_recv_msg(struct sk_buff *skb)
+{
+	struct nlmsghdr *nlh;
+#ifdef CONFIG_SSV_NETLINK_RESPONSE
+	struct sk_buff *skb_out;
+#endif
+	int ret = 0;
+	u8 *pInBuf = NULL;
+	u32 inBufLen = 0;
+	u32 outBufLen = 0;
+	nlh = (struct nlmsghdr *)skb->data;
+	ssv_usr_pid = nlh->nlmsg_pid;
+	pInBuf = (u8 *) nlmsg_data(nlh);
+	inBufLen = nlmsg_len(nlh);
+#ifdef KSMARTLINK_DEBUG
+	_ksmartlink_hex_dump(pInBuf, inBufLen);
+#endif
+	outBufLen = 0;
+	memset(gkBuf, 0, MAX_PAYLOAD);
+	ret = _ksmartlink_process_msg(pInBuf, inBufLen, gkBuf, &outBufLen);
+#ifdef CONFIG_SSV_NETLINK_RESPONSE
+	if (outBufLen == 0) {
+		memcpy(gkBuf, "Nothing", 8);
+		outBufLen = strlen(gkBuf);
+	}
+	skb_out = nlmsg_new(outBufLen, 0);
+	if (!skb_out) {
+		printk(KERN_ERR "Failed to allocate new skb\n");
+		return;
+	}
+	nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, outBufLen, 0);
+	NETLINK_CB(skb_out).dst_group = 0;
+	memcpy(nlmsg_data(nlh), gkBuf, outBufLen);
+	ret = nlmsg_unicast(nl_sk, skb_out, ssv_usr_pid);
+	if (ret < 0) {
+		printk(KERN_ERR "Error while sending bak to user\n");
+	}
+#endif
+	return;
+}
+
+void smartlink_nl_send_msg(struct sk_buff *skb)
+{
+	struct nlmsghdr *nlh;
+	struct sk_buff *skb_out;
+	int ret = 0;
+	u8 *pOutBuf = skb->data;
+	u32 outBufLen = skb->len;
+#ifdef KSMARTLINK_DEBUG
+#endif
+	skb_out = nlmsg_new(outBufLen, 0);
+	if (!skb_out) {
+		printk(KERN_ERR "Allocate new skb failed!\n");
+		return;
+	}
+	nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, outBufLen, 0);
+	NETLINK_CB(skb_out).dst_group = 0;
+	memcpy(nlmsg_data(nlh), pOutBuf, outBufLen);
+	ret = nlmsg_unicast(nl_sk, skb_out, ssv_usr_pid);
+	if (ret < 0) {
+		printk(KERN_ERR "nlmsg_unicast failed!\n");
+	}
+	kfree_skb(skb);
+	return;
+}
+
+EXPORT_SYMBOL(smartlink_nl_send_msg);
+int ksmartlink_init(void)
+{
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0)
+	nl_sk = netlink_kernel_create(&init_net,
+				      NETLINK_SMARTLINK,
+				      0,
+				      smartlink_nl_recv_msg, NULL, THIS_MODULE);
+#else
+	struct netlink_kernel_cfg cfg = {
+		.groups = 0,
+		.input = smartlink_nl_recv_msg,
+	};
+	nl_sk = netlink_kernel_create(&init_net, NETLINK_SMARTLINK, &cfg);
+#endif
+	printk(KERN_INFO "***************SmartLink Init-S**************\n");
+	if (!nl_sk) {
+		printk(KERN_ERR "Error creating socket.\n");
+		return -10;
+	}
+	printk(KERN_INFO "***************SmartLink Init-E**************\n");
+	return 0;
+}
+
+void ksmartlink_exit(void)
+{
+	printk(KERN_INFO "%s\n", __FUNCTION__);
+	if (nl_sk) {
+		netlink_kernel_release(nl_sk);
+		nl_sk = NULL;
+	}
+}
+
+EXPORT_SYMBOL(ksmartlink_init);
+EXPORT_SYMBOL(ksmartlink_exit);
diff --git a/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
new file mode 100644
index 00000000000..9be5ea96e7f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <net/mac80211.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ssv6xxx_debugfs.h"
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+#define QUEUE_STATUS_BUF_SIZE (4096)
+static ssize_t queue_status_read(struct file *file,
+				 char __user * user_buf, size_t count,
+				 loff_t * ppos)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)file->private_data;
+	char *status_buf = kzalloc(QUEUE_STATUS_BUF_SIZE, GFP_KERNEL);
+	ssize_t status_size;
+	ssize_t ret;
+	if (!status_buf)
+		return -ENOMEM;
+	status_size = ssv6xxx_tx_queue_status_dump(sc, status_buf,
+						   QUEUE_STATUS_BUF_SIZE);
+	ret = simple_read_from_buffer(user_buf, count, ppos, status_buf,
+				      status_size);
+	kfree(status_buf);
+	return ret;
+}
+
+static int queue_status_open(struct inode *inode, struct file *file)
+{
+	file->private_data = inode->i_private;
+	return 0;
+}
+
+static const struct file_operations queue_status_fops
+    = {.read = queue_status_read,
+	.open = queue_status_open
+};
+#endif
+int ssv6xxx_init_debugfs(struct ssv_softc *sc, const char *name)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct ieee80211_hw *hw = sc->hw;
+	struct dentry *phy_debugfs_dir = hw->wiphy->debugfsdir;
+	struct dentry *drv_debugfs_dir;
+	drv_debugfs_dir = debugfs_create_dir(name, phy_debugfs_dir);
+	if (!drv_debugfs_dir) {
+		dev_err(sc->dev, "Failed to create debugfs.\n");
+		return -ENOMEM;
+	}
+	sc->debugfs_dir = drv_debugfs_dir;
+	sc->sh->hci.hci_ops->hci_init_debugfs(sc->debugfs_dir);
+	debugfs_create_file("queue_status", 00444, drv_debugfs_dir,
+			    sc, &queue_status_fops);
+#endif
+	return 0;
+}
+
+void ssv6xxx_deinit_debugfs(struct ssv_softc *sc)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	if (!sc->debugfs_dir)
+		return;
+	sc->sh->hci.hci_ops->hci_deinit_debugfs();
+	debugfs_remove_recursive(sc->debugfs_dir);
+	sc->debugfs_dir = NULL;
+#endif
+}
+
+int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc,
+				  struct ieee80211_vif *vif)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct dentry *drv_debugfs_dir = sc->debugfs_dir;
+	struct dentry *vif_debugfs_dir;
+	char vif_addr[18];
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+	snprintf(vif_addr, sizeof(vif_addr), "%02X-%02X-%02X-%02X-%02X-%02X",
+		 vif->addr[0], vif->addr[1], vif->addr[2],
+		 vif->addr[3], vif->addr[4], vif->addr[5]);
+	vif_debugfs_dir = debugfs_create_dir(vif_addr, drv_debugfs_dir);
+	if (!vif_debugfs_dir) {
+		dev_err(sc->dev, "Failed to create interface debugfs for %s.\n",
+			vif_addr);
+		return -ENOMEM;
+	}
+	sc->debugfs_dir = drv_debugfs_dir;
+	vif_info->debugfs_dir = vif_debugfs_dir;
+#endif
+	return 0;
+}
+
+int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc,
+				     struct ieee80211_vif *vif)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+	if ((vif_info->debugfs_dir == NULL) || (sc->debugfs_dir == NULL))
+		return 0;
+	debugfs_remove_recursive(vif_info->debugfs_dir);
+	vif_info->debugfs_dir = NULL;
+#endif
+	return 0;
+}
+
+int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)sta->vif->drv_priv;
+	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+	if ((sc->debugfs_dir == NULL) || (vif_info->debugfs_dir == NULL)
+	    || (sta->debugfs_dir == NULL))
+		return 0;
+	debugfs_remove_recursive(sta->debugfs_dir);
+	sta->debugfs_dir = NULL;
+#endif
+	return 0;
+}
+
+int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)sta->vif->drv_priv;
+	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+	struct dentry *vif_debugfs_dir = vif_info->debugfs_dir;
+	struct dentry *sta_debugfs_dir;
+	char sta_addr[18];
+	if (vif_debugfs_dir == NULL)
+		return 0;
+	snprintf(sta_addr, sizeof(sta_addr), "%02X-%02X-%02X-%02X-%02X-%02X",
+		 sta->sta->addr[0], sta->sta->addr[1], sta->sta->addr[2],
+		 sta->sta->addr[3], sta->sta->addr[4], sta->sta->addr[5]);
+	sta_debugfs_dir = debugfs_create_dir(sta_addr, vif_debugfs_dir);
+	if (!sta_debugfs_dir) {
+		dev_err(sc->dev, "Failed to create interface debugfs for %s.\n",
+			sta_addr);
+		return -ENOMEM;
+	}
+	sta->debugfs_dir = sta_debugfs_dir;
+#endif
+	return 0;
+}
+
+#define DEBUGFS_ADD_FILE(name,parent,mode) do { \
+    if (!debugfs_create_file(#name, mode, parent, priv, \
+                 &ssv_dbgfs_##name##_ops)) \
+        goto err; \
+} while (0)
+#define DEBUGFS_ADD_BOOL(name,parent,ptr) do { \
+    struct dentry *__tmp; \
+    __tmp = debugfs_create_bool(#name, S_IWUSR | S_IRUSR, \
+                    parent, ptr); \
+    if (IS_ERR(__tmp) || !__tmp) \
+        goto err; \
+} while (0)
+#define DEBUGFS_ADD_X32(name,parent,ptr) do { \
+    struct dentry *__tmp; \
+    __tmp = debugfs_create_x32(#name, S_IWUSR | S_IRUSR, \
+                   parent, ptr); \
+    if (IS_ERR(__tmp) || !__tmp) \
+        goto err; \
+} while (0)
+#define DEBUGFS_ADD_U32(name,parent,ptr,mode) do { \
+    struct dentry *__tmp; \
+    __tmp = debugfs_create_u32(#name, mode, \
+                   parent, ptr); \
+    if (IS_ERR(__tmp) || !__tmp) \
+        goto err; \
+} while (0)
+#define DEBUGFS_READ_FUNC(name) \
+static ssize_t ssv_dbgfs_##name##_read(struct file *file, \
+                    char __user *user_buf, \
+                    size_t count, loff_t *ppos);
+#define DEBUGFS_WRITE_FUNC(name) \
+static ssize_t ssv_dbgfs_##name##_write(struct file *file, \
+                    const char __user *user_buf, \
+                    size_t count, loff_t *ppos);
+#define DEBUGFS_READ_FILE_OPS(name) \
+    DEBUGFS_READ_FUNC(name); \
+static const struct file_operations ssv_dbgfs_##name##_ops = { \
+    .read = ssv_dbgfs_##name##_read, \
+    .open = ssv_dbgfs_open_file_generic, \
+    .llseek = generic_file_llseek, \
+};
+#define DEBUGFS_WRITE_FILE_OPS(name) \
+    DEBUGFS_WRITE_FUNC(name); \
+static const struct file_operations ssv_dbgfs_##name##_ops = { \
+    .write = ssv_dbgfs_##name##_write, \
+    .open = ssv_dbgfs_open_file_generic, \
+    .llseek = generic_file_llseek, \
+};
+#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
+    DEBUGFS_READ_FUNC(name); \
+    DEBUGFS_WRITE_FUNC(name); \
+static const struct file_operations ssv_dbgfs_##name##_ops = { \
+    .write = ssv_dbgfs_##name##_write, \
+    .read = ssv_dbgfs_##name##_read, \
+    .open = ssv_dbgfs_open_file_generic, \
+    .llseek = generic_file_llseek, \
+};
diff --git a/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
new file mode 100644
index 00000000000..39caceadda4
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SSV6XXX_DBGFS_H__
+#define __SSV6XXX_DBGFS_H__
+int ssv6xxx_init_debugfs(struct ssv_softc *sc, const char *name);
+void ssv6xxx_deinit_debugfs(struct ssv_softc *sc);
+int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc,
+				     struct ieee80211_vif *vif);
+int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc,
+				  struct ieee80211_vif *vif);
+int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);
+int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
new file mode 100644
index 00000000000..f0135447b1f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
@@ -0,0 +1,1384 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2018 icomm Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#include "dev.h"
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(CONFIG_SSV_VENDOR_EXT_SUPPORT)
+
+#include <linux/kernel.h>
+#include <linux/if_arp.h>
+#include <asm/uaccess.h>
+
+#include <linux/kernel.h>
+#include <linux/kthread.h>
+#include <linux/netdevice.h>
+#include <linux/sched.h>
+#include <linux/etherdevice.h>
+#include <linux/wireless.h>
+#include <linux/ieee80211.h>
+#include <linux/wait.h>
+#include <net/cfg80211.h>
+
+#include <net/rtnetlink.h>
+#include "ssv_cfgvendor.h"
+
+#define wiphy_to_softc(x) (*((struct ssv_softc**)wiphy_priv(x)))
+#define FUNC_NDEV_FMT "%s"
+#define FUNC_NDEV_ARG(ndev) __func__
+
+#define _drv_always_		1
+#define _drv_emerg_			2
+#define _drv_alert_			3
+#define _drv_crit_			4
+#define _drv_err_			5
+#define _drv_warning_		6
+#define _drv_notice_		7
+#define _drv_info_			8
+#define _drv_dump_			9
+#define _drv_debug_			10
+
+struct sk_buff *ssv_cfg80211_vendor_event_alloc(struct wiphy *wiphy, int len,
+						int event_id, gfp_t gfp)
+{
+	struct sk_buff *skb;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))
+	skb = cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp);
+#else
+	skb = cfg80211_vendor_event_alloc(wiphy, NULL, len, event_id, gfp);
+#endif
+	return skb;
+}
+
+#define ssv_cfg80211_vendor_event(skb, gfp) \
+	cfg80211_vendor_event(skb, gfp)
+
+#define ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) \
+	cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len)
+
+#define ssv_cfg80211_vendor_cmd_reply(skb) \
+	cfg80211_vendor_cmd_reply(skb)
+
+/*
+ * This API is to be used for asynchronous vendor events. This
+ * shouldn't be used in response to a vendor command from its
+ * do_it handler context (instead ssv_cfgvendor_send_cmd_reply should
+ * be used).
+ */
+int ssv_cfgvendor_send_async_event(struct wiphy *wiphy,
+				   struct net_device *dev, int event_id,
+				   const void *data, int len)
+{
+	u16 kflags;
+	struct sk_buff *skb;
+
+	kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
+
+	/* Alloc the SKB for vendor_event */
+	skb = ssv_cfg80211_vendor_event_alloc(wiphy, len, event_id, kflags);
+	if (!skb) {
+		dev_err(&wiphy->dev, "skb alloc failed\n");
+		return -ENOMEM;
+	}
+
+	/* Push the data to the skb */
+	nla_put_nohdr(skb, len, data);
+
+	ssv_cfg80211_vendor_event(skb, kflags);
+
+	return 0;
+}
+
+static int ssv_cfgvendor_send_cmd_reply(struct wiphy *wiphy,
+					struct net_device *dev,
+					const void *data, int len)
+{
+	struct sk_buff *skb;
+
+	/* Alloc the SKB for vendor_event */
+	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);
+	if (unlikely(!skb)) {
+		dev_err(&wiphy->dev, "skb alloc failed");
+		return -ENOMEM;
+	}
+
+	/* Push the data to the skb */
+	nla_put_nohdr(skb, len, data);
+
+	return ssv_cfg80211_vendor_cmd_reply(skb);
+}
+
+#define WIFI_FEATURE_INFRA              0x0001	/* Basic infrastructure mode        */
+#define WIFI_FEATURE_INFRA_5G           0x0002	/* Support for 5 GHz Band           */
+#define WIFI_FEATURE_HOTSPOT            0x0004	/* Support for GAS/ANQP             */
+#define WIFI_FEATURE_P2P                0x0008	/* Wifi-Direct                      */
+#define WIFI_FEATURE_SOFT_AP            0x0010	/* Soft AP                          */
+#define WIFI_FEATURE_GSCAN              0x0020	/* Google-Scan APIs                 */
+#define WIFI_FEATURE_NAN                0x0040	/* Neighbor Awareness Networking    */
+#define WIFI_FEATURE_D2D_RTT            0x0080	/* Device-to-device RTT             */
+#define WIFI_FEATURE_D2AP_RTT           0x0100	/* Device-to-AP RTT                 */
+#define WIFI_FEATURE_BATCH_SCAN         0x0200	/* Batched Scan (legacy)            */
+#define WIFI_FEATURE_PNO                0x0400	/* Preferred network offload        */
+#define WIFI_FEATURE_ADDITIONAL_STA     0x0800	/* Support for two STAs             */
+#define WIFI_FEATURE_TDLS               0x1000	/* Tunnel directed link setup       */
+#define WIFI_FEATURE_TDLS_OFFCHANNEL    0x2000	/* Support for TDLS off channel     */
+#define WIFI_FEATURE_EPR                0x4000	/* Enhanced power reporting         */
+#define WIFI_FEATURE_AP_STA             0x8000	/* Support for AP STA Concurrency   */
+
+#define MAX_FEATURE_SET_CONCURRRENT_GROUPS  3
+
+int ssv_dev_get_feature_set(struct net_device *dev)
+{
+	int feature_set = 0;
+
+	feature_set |= WIFI_FEATURE_INFRA;
+
+	feature_set |= WIFI_FEATURE_P2P;
+	feature_set |= WIFI_FEATURE_SOFT_AP;
+
+#if defined(GSCAN_SUPPORT)
+	feature_set |= WIFI_FEATURE_GSCAN;
+#endif
+
+#if defined(RTT_SUPPORT)
+	feature_set |= WIFI_FEATURE_NAN;
+	feature_set |= WIFI_FEATURE_D2D_RTT;
+	feature_set |= WIFI_FEATURE_D2AP_RTT;
+#endif
+
+	return feature_set;
+}
+
+int *ssv_dev_get_feature_set_matrix(struct net_device *dev, int *num)
+{
+	int feature_set_full, mem_needed;
+	int *ret;
+
+	*num = 0;
+	mem_needed = sizeof(int) * MAX_FEATURE_SET_CONCURRRENT_GROUPS;
+	ret =
+	    (int *)kmalloc(mem_needed, in_interrupt()? GFP_ATOMIC : GFP_KERNEL);
+
+	if (!ret) {
+		dev_err(&dev->dev, "failed to allocate %d bytes\n", mem_needed);
+		return ret;
+	}
+
+	feature_set_full = ssv_dev_get_feature_set(dev);
+
+	ret[0] = (feature_set_full & WIFI_FEATURE_INFRA) |
+	    (feature_set_full & WIFI_FEATURE_INFRA_5G) |
+	    (feature_set_full & WIFI_FEATURE_NAN) |
+	    (feature_set_full & WIFI_FEATURE_D2D_RTT) |
+	    (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
+	    (feature_set_full & WIFI_FEATURE_PNO) |
+	    (feature_set_full & WIFI_FEATURE_BATCH_SCAN) |
+	    (feature_set_full & WIFI_FEATURE_GSCAN) |
+	    (feature_set_full & WIFI_FEATURE_HOTSPOT) |
+	    (feature_set_full & WIFI_FEATURE_ADDITIONAL_STA) |
+	    (feature_set_full & WIFI_FEATURE_EPR);
+
+	ret[1] = (feature_set_full & WIFI_FEATURE_INFRA) |
+	    (feature_set_full & WIFI_FEATURE_INFRA_5G) |
+	    /* Not yet verified NAN with P2P */
+	    /* (feature_set_full & WIFI_FEATURE_NAN) | */
+	    (feature_set_full & WIFI_FEATURE_P2P) |
+	    (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
+	    (feature_set_full & WIFI_FEATURE_D2D_RTT) |
+	    (feature_set_full & WIFI_FEATURE_EPR);
+
+	ret[2] = (feature_set_full & WIFI_FEATURE_INFRA) |
+	    (feature_set_full & WIFI_FEATURE_INFRA_5G) |
+	    (feature_set_full & WIFI_FEATURE_NAN) |
+	    (feature_set_full & WIFI_FEATURE_D2D_RTT) |
+	    (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
+	    (feature_set_full & WIFI_FEATURE_TDLS) |
+	    (feature_set_full & WIFI_FEATURE_TDLS_OFFCHANNEL) |
+	    (feature_set_full & WIFI_FEATURE_EPR);
+	*num = MAX_FEATURE_SET_CONCURRRENT_GROUPS;
+
+	return ret;
+}
+
+#define wdev_to_ndev(wdev) NULL
+
+static int ssv_cfgvendor_get_feature_set(struct wiphy *wiphy,
+					 struct wireless_dev *wdev,
+					 const void *data, int len)
+{
+	int err = 0;
+	int reply;
+
+	reply = ssv_dev_get_feature_set(wdev_to_ndev(wdev));
+
+	err =
+	    ssv_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &reply,
+					 sizeof(int));
+
+	if (unlikely(err))
+		dev_err(&wiphy->dev, "vendor Command reply failed, ret:%d\n", err);
+
+	return err;
+}
+
+static int ssv_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy,
+						struct wireless_dev *wdev,
+						const void *data, int len)
+{
+	int err = 0;
+	struct sk_buff *skb;
+	int *reply;
+	int num, mem_needed, i;
+
+	reply = ssv_dev_get_feature_set_matrix(wdev_to_ndev(wdev), &num);
+
+	if (!reply) {
+		dev_err(&wiphy->dev, "could not get feature list matrix\n");
+		err = -EINVAL;
+		return err;
+	}
+
+	mem_needed = VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * num) +
+	    ATTRIBUTE_U32_LEN;
+
+	/* Alloc the SKB for vendor_event */
+	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
+	if (unlikely(!skb)) {
+		dev_err(&wiphy->dev, "skb alloc failed\n");
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, num);
+	for (i = 0; i < num; i++) {
+		nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_FEATURE_SET, reply[i]);
+	}
+
+	err = ssv_cfg80211_vendor_cmd_reply(skb);
+
+	if (unlikely(err))
+		dev_err(&wiphy->dev, "vendor Command reply failed, ret=%d\n", err);
+ exit:
+	kfree((void *)reply);
+	return err;
+}
+
+#if defined(GSCAN_SUPPORT) && 0
+int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
+				    struct net_device *dev, void *data, int len,
+				    wl_vendor_event_t event)
+{
+	u16 kflags;
+	const void *ptr;
+	struct sk_buff *skb;
+	int malloc_len, total, iter_cnt_to_send, cnt;
+	gscan_results_cache_t *cache = (gscan_results_cache_t *) data;
+
+	total = len / sizeof(wifi_gscan_result_t);
+	while (total > 0) {
+		malloc_len =
+		    (total * sizeof(wifi_gscan_result_t)) +
+		    VENDOR_DATA_OVERHEAD;
+		if (malloc_len > NLMSG_DEFAULT_SIZE) {
+			malloc_len = NLMSG_DEFAULT_SIZE;
+		}
+		iter_cnt_to_send =
+		    (malloc_len -
+		     VENDOR_DATA_OVERHEAD) / sizeof(wifi_gscan_result_t);
+		total = total - iter_cnt_to_send;
+
+		kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
+
+		/* Alloc the SKB for vendor_event */
+		skb =
+		    ssv_cfg80211_vendor_event_alloc(wiphy, malloc_len, event,
+						    kflags);
+		if (!skb) {
+			WL_ERR(("skb alloc failed"));
+			return -ENOMEM;
+		}
+
+		while (cache && iter_cnt_to_send) {
+			ptr =
+			    (const void *)&cache->results[cache->tot_consumed];
+
+			if (iter_cnt_to_send <
+			    (cache->tot_count - cache->tot_consumed))
+				cnt = iter_cnt_to_send;
+			else
+				cnt = (cache->tot_count - cache->tot_consumed);
+
+			iter_cnt_to_send -= cnt;
+			cache->tot_consumed += cnt;
+			/* Push the data to the skb */
+			nla_append(skb, cnt * sizeof(wifi_gscan_result_t), ptr);
+			if (cache->tot_consumed == cache->tot_count)
+				cache = cache->next;
+
+		}
+
+		ssv_cfg80211_vendor_event(skb, kflags);
+	}
+
+	return 0;
+}
+
+static int wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy,
+					       struct wireless_dev *wdev,
+					       const void *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	dhd_pno_gscan_capabilities_t *reply = NULL;
+	uint32 reply_len = 0;
+
+	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
+				      DHD_PNO_GET_CAPABILITIES, NULL,
+				      &reply_len);
+	if (!reply) {
+		WL_ERR(("Could not get capabilities\n"));
+		err = -EINVAL;
+		return err;
+	}
+
+	err = ssv_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
+					   reply, reply_len);
+
+	if (unlikely(err))
+		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
+
+	kfree(reply);
+	return err;
+}
+
+static int wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy,
+					       struct wireless_dev *wdev,
+					       const void *data, int len)
+{
+	int err = 0, type, band;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	uint16 *reply = NULL;
+	uint32 reply_len = 0, num_channels, mem_needed;
+	struct sk_buff *skb;
+
+	type = nla_type(data);
+
+	if (type == GSCAN_ATTRIBUTE_BAND) {
+		band = nla_get_u32(data);
+	} else {
+		return -1;
+	}
+
+	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
+				      DHD_PNO_GET_CHANNEL_LIST, &band,
+				      &reply_len);
+
+	if (!reply) {
+		WL_ERR(("Could not get channel list\n"));
+		err = -EINVAL;
+		return err;
+	}
+	num_channels = reply_len / sizeof(uint32);
+	mem_needed =
+	    reply_len + VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * 2);
+
+	/* Alloc the SKB for vendor_event */
+	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
+	if (unlikely(!skb)) {
+		WL_ERR(("skb alloc failed"));
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_CHANNELS, num_channels);
+	nla_put(skb, GSCAN_ATTRIBUTE_CHANNEL_LIST, reply_len, reply);
+
+	err = ssv_cfg80211_vendor_cmd_reply(skb);
+
+	if (unlikely(err))
+		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
+ exit:
+	kfree(reply);
+	return err;
+}
+
+static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy,
+						struct wireless_dev *wdev,
+						const void *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	gscan_results_cache_t *results, *iter;
+	uint32 reply_len, complete = 0, num_results_iter;
+	int32 mem_needed;
+	wifi_gscan_result_t *ptr;
+	uint16 num_scan_ids, num_results;
+	struct sk_buff *skb;
+	struct nlattr *scan_hdr;
+
+	dhd_dev_wait_batch_results_complete(bcmcfg_to_prmry_ndev(cfg));
+	dhd_dev_pno_lock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
+	results = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
+					DHD_PNO_GET_BATCH_RESULTS, NULL,
+					&reply_len);
+
+	if (!results) {
+		WL_ERR(("No results to send %d\n", err));
+		err =
+		    ssv_cfgvendor_send_cmd_reply(wiphy,
+						 bcmcfg_to_prmry_ndev(cfg),
+						 results, 0);
+
+		if (unlikely(err))
+			WL_ERR(("Vendor Command reply failed ret:%d \n", err));
+		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev
+							(cfg));
+		return err;
+	}
+	num_scan_ids = reply_len & 0xFFFF;
+	num_results = (reply_len & 0xFFFF0000) >> 16;
+	mem_needed = (num_results * sizeof(wifi_gscan_result_t)) +
+	    (num_scan_ids * GSCAN_BATCH_RESULT_HDR_LEN) +
+	    VENDOR_REPLY_OVERHEAD + SCAN_RESULTS_COMPLETE_FLAG_LEN;
+
+	if (mem_needed > (int32) NLMSG_DEFAULT_SIZE) {
+		mem_needed = (int32) NLMSG_DEFAULT_SIZE;
+		complete = 0;
+	} else {
+		complete = 1;
+	}
+
+	WL_TRACE(("complete %d mem_needed %d max_mem %d\n", complete,
+		  mem_needed, (int)NLMSG_DEFAULT_SIZE));
+	/* Alloc the SKB for vendor_event */
+	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
+	if (unlikely(!skb)) {
+		WL_ERR(("skb alloc failed"));
+		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev
+							(cfg));
+		return -ENOMEM;
+	}
+	iter = results;
+
+	nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE, complete);
+
+	mem_needed =
+	    mem_needed - (SCAN_RESULTS_COMPLETE_FLAG_LEN +
+			  VENDOR_REPLY_OVERHEAD);
+
+	while (iter && ((mem_needed - GSCAN_BATCH_RESULT_HDR_LEN) > 0)) {
+		scan_hdr = nla_nest_start(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS);
+		nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_ID, iter->scan_id);
+		nla_put_u8(skb, GSCAN_ATTRIBUTE_SCAN_FLAGS, iter->flag);
+		num_results_iter =
+		    (mem_needed -
+		     GSCAN_BATCH_RESULT_HDR_LEN) / sizeof(wifi_gscan_result_t);
+
+		if ((iter->tot_count - iter->tot_consumed) < num_results_iter)
+			num_results_iter = iter->tot_count - iter->tot_consumed;
+
+		nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_OF_RESULTS,
+			    num_results_iter);
+		if (num_results_iter) {
+			ptr = &iter->results[iter->tot_consumed];
+			iter->tot_consumed += num_results_iter;
+			nla_put(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS,
+				num_results_iter * sizeof(wifi_gscan_result_t),
+				ptr);
+		}
+		nla_nest_end(skb, scan_hdr);
+		mem_needed -= GSCAN_BATCH_RESULT_HDR_LEN +
+		    (num_results_iter * sizeof(wifi_gscan_result_t));
+		iter = iter->next;
+	}
+
+	dhd_dev_gscan_batch_cache_cleanup(bcmcfg_to_prmry_ndev(cfg));
+	dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
+
+	return ssv_cfg80211_vendor_cmd_reply(skb);
+}
+
+static int wl_cfgvendor_initiate_gscan(struct wiphy *wiphy,
+				       struct wireless_dev *wdev,
+				       const void *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	int type, tmp = len;
+	int run = 0xFF;
+	int flush = 0;
+	const struct nlattr *iter;
+
+	nla_for_each_attr(iter, data, len, tmp) {
+		type = nla_type(iter);
+		if (type == GSCAN_ATTRIBUTE_ENABLE_FEATURE)
+			run = nla_get_u32(iter);
+		else if (type == GSCAN_ATTRIBUTE_FLUSH_FEATURE)
+			flush = nla_get_u32(iter);
+	}
+
+	if (run != 0xFF) {
+		err =
+		    dhd_dev_pno_run_gscan(bcmcfg_to_prmry_ndev(cfg), run,
+					  flush);
+
+		if (unlikely(err))
+			WL_ERR(("Could not run gscan:%d \n", err));
+		return err;
+	} else {
+		return -1;
+	}
+
+}
+
+static int wl_cfgvendor_enable_full_scan_result(struct wiphy *wiphy,
+						struct wireless_dev *wdev,
+						const void *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	int type;
+	bool real_time = FALSE;
+
+	type = nla_type(data);
+
+	if (type == GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS) {
+		real_time = nla_get_u32(data);
+
+		err =
+		    dhd_dev_pno_enable_full_scan_result(bcmcfg_to_prmry_ndev
+							(cfg), real_time);
+
+		if (unlikely(err))
+			WL_ERR(("Could not run gscan:%d \n", err));
+
+	} else {
+		err = -1;
+	}
+
+	return err;
+}
+
+static int wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy,
+				     struct wireless_dev *wdev,
+				     const void *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	gscan_scan_params_t *scan_param;
+	int j = 0;
+	int type, tmp, tmp1, tmp2, k = 0;
+	const struct nlattr *iter, *iter1, *iter2;
+	struct dhd_pno_gscan_channel_bucket *ch_bucket;
+
+	scan_param = kzalloc(sizeof(gscan_scan_params_t), GFP_KERNEL);
+	if (!scan_param) {
+		WL_ERR(("Could not set GSCAN scan cfg, mem alloc failure\n"));
+		err = -EINVAL;
+		return err;
+
+	}
+
+	scan_param->scan_fr = PNO_SCAN_MIN_FW_SEC;
+	nla_for_each_attr(iter, data, len, tmp) {
+		type = nla_type(iter);
+
+		if (j >= GSCAN_MAX_CH_BUCKETS)
+			break;
+
+		switch (type) {
+		case GSCAN_ATTRIBUTE_BASE_PERIOD:
+			scan_param->scan_fr = nla_get_u32(iter) / 1000;
+			break;
+		case GSCAN_ATTRIBUTE_NUM_BUCKETS:
+			scan_param->nchannel_buckets = nla_get_u32(iter);
+			break;
+		case GSCAN_ATTRIBUTE_CH_BUCKET_1:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_2:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_3:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_4:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_5:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_6:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_7:
+			nla_for_each_nested(iter1, iter, tmp1) {
+				type = nla_type(iter1);
+				ch_bucket = scan_param->channel_bucket;
+
+				switch (type) {
+				case GSCAN_ATTRIBUTE_BUCKET_ID:
+					break;
+				case GSCAN_ATTRIBUTE_BUCKET_PERIOD:
+					ch_bucket[j].bucket_freq_multiple =
+					    nla_get_u32(iter1) / 1000;
+					break;
+				case GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS:
+					ch_bucket[j].num_channels =
+					    nla_get_u32(iter1);
+					break;
+				case GSCAN_ATTRIBUTE_BUCKET_CHANNELS:
+					nla_for_each_nested(iter2, iter1, tmp2) {
+						if (k >=
+						    PFN_SWC_RSSI_WINDOW_MAX)
+							break;
+						ch_bucket[j].chan_list[k] =
+						    nla_get_u32(iter2);
+						k++;
+					}
+					k = 0;
+					break;
+				case GSCAN_ATTRIBUTE_BUCKETS_BAND:
+					ch_bucket[j].band = (uint16)
+					    nla_get_u32(iter1);
+					break;
+				case GSCAN_ATTRIBUTE_REPORT_EVENTS:
+					ch_bucket[j].report_flag = (uint8)
+					    nla_get_u32(iter1);
+					break;
+				}
+			}
+			j++;
+			break;
+		}
+	}
+
+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+				      DHD_PNO_SCAN_CFG_ID, scan_param, 0) < 0) {
+		WL_ERR(("Could not set GSCAN scan cfg\n"));
+		err = -EINVAL;
+	}
+
+	kfree(scan_param);
+	return err;
+
+}
+
+static int wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy,
+				    struct wireless_dev *wdev, const void *data,
+				    int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	gscan_hotlist_scan_params_t *hotlist_params;
+	int tmp, tmp1, tmp2, type, j = 0, dummy;
+	const struct nlattr *outer, *inner, *iter;
+	uint8 flush = 0;
+	struct bssid_t *pbssid;
+
+	hotlist_params =
+	    (gscan_hotlist_scan_params_t *) kzalloc(len, GFP_KERNEL);
+	if (!hotlist_params) {
+		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes \n", len));
+		return -1;
+	}
+
+	hotlist_params->lost_ap_window = GSCAN_LOST_AP_WINDOW_DEFAULT;
+
+	nla_for_each_attr(iter, data, len, tmp2) {
+		type = nla_type(iter);
+		switch (type) {
+		case GSCAN_ATTRIBUTE_HOTLIST_BSSIDS:
+			pbssid = hotlist_params->bssid;
+			nla_for_each_nested(outer, iter, tmp) {
+				nla_for_each_nested(inner, outer, tmp1) {
+					type = nla_type(inner);
+
+					switch (type) {
+					case GSCAN_ATTRIBUTE_BSSID:
+						memcpy(&(pbssid[j].macaddr),
+						       nla_data(inner),
+						       ETHER_ADDR_LEN);
+						break;
+					case GSCAN_ATTRIBUTE_RSSI_LOW:
+						pbssid[j].
+						    rssi_reporting_threshold =
+						    (int8) nla_get_u8(inner);
+						break;
+					case GSCAN_ATTRIBUTE_RSSI_HIGH:
+						dummy =
+						    (int8) nla_get_u8(inner);
+						break;
+					}
+				}
+				j++;
+			}
+			hotlist_params->nbssid = j;
+			break;
+		case GSCAN_ATTRIBUTE_HOTLIST_FLUSH:
+			flush = nla_get_u8(iter);
+			break;
+		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
+			hotlist_params->lost_ap_window = nla_get_u32(iter);
+			break;
+		}
+
+	}
+
+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+				      DHD_PNO_GEOFENCE_SCAN_CFG_ID,
+				      hotlist_params, flush) < 0) {
+		WL_ERR(("Could not set GSCAN HOTLIST cfg\n"));
+		err = -EINVAL;
+		goto exit;
+	}
+ exit:
+	kfree(hotlist_params);
+	return err;
+}
+
+static int wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy,
+					   struct wireless_dev *wdev,
+					   const void *data, int len)
+{
+	int err = 0, tmp, type;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	gscan_batch_params_t batch_param;
+	const struct nlattr *iter;
+
+	batch_param.mscan = batch_param.bestn = 0;
+	batch_param.buffer_threshold = GSCAN_BATCH_NO_THR_SET;
+
+	nla_for_each_attr(iter, data, len, tmp) {
+		type = nla_type(iter);
+
+		switch (type) {
+		case GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN:
+			batch_param.bestn = nla_get_u32(iter);
+			break;
+		case GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE:
+			batch_param.mscan = nla_get_u32(iter);
+			break;
+		case GSCAN_ATTRIBUTE_REPORT_THRESHOLD:
+			batch_param.buffer_threshold = nla_get_u32(iter);
+			break;
+		}
+	}
+
+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+				      DHD_PNO_BATCH_SCAN_CFG_ID, &batch_param,
+				      0) < 0) {
+		WL_ERR(("Could not set batch cfg\n"));
+		err = -EINVAL;
+		return err;
+	}
+
+	return err;
+}
+
+static int wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy,
+					       struct wireless_dev *wdev,
+					       const void *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	gscan_swc_params_t *significant_params;
+	int tmp, tmp1, tmp2, type, j = 0;
+	const struct nlattr *outer, *inner, *iter;
+	uint8 flush = 0;
+	wl_pfn_significant_bssid_t *pbssid;
+
+	significant_params = (gscan_swc_params_t *) kzalloc(len, GFP_KERNEL);
+	if (!significant_params) {
+		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes \n", len));
+		return -1;
+	}
+
+	nla_for_each_attr(iter, data, len, tmp2) {
+		type = nla_type(iter);
+
+		switch (type) {
+		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH:
+			flush = nla_get_u8(iter);
+			break;
+		case GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE:
+			significant_params->rssi_window = nla_get_u16(iter);
+			break;
+		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
+			significant_params->lost_ap_window = nla_get_u16(iter);
+			break;
+		case GSCAN_ATTRIBUTE_MIN_BREACHING:
+			significant_params->swc_threshold = nla_get_u16(iter);
+			break;
+		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS:
+			pbssid = significant_params->bssid_elem_list;
+			nla_for_each_nested(outer, iter, tmp) {
+				nla_for_each_nested(inner, outer, tmp1) {
+					switch (nla_type(inner)) {
+					case GSCAN_ATTRIBUTE_BSSID:
+						memcpy(&(pbssid[j].macaddr),
+						       nla_data(inner),
+						       ETHER_ADDR_LEN);
+						break;
+					case GSCAN_ATTRIBUTE_RSSI_HIGH:
+						pbssid[j].rssi_high_threshold =
+						    (int8) nla_get_u8(inner);
+						break;
+					case GSCAN_ATTRIBUTE_RSSI_LOW:
+						pbssid[j].rssi_low_threshold =
+						    (int8) nla_get_u8(inner);
+						break;
+					}
+				}
+				j++;
+			}
+			break;
+		}
+	}
+	significant_params->nbssid = j;
+
+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+				      DHD_PNO_SIGNIFICANT_SCAN_CFG_ID,
+				      significant_params, flush) < 0) {
+		WL_ERR(("Could not set GSCAN significant cfg\n"));
+		err = -EINVAL;
+		goto exit;
+	}
+ exit:
+	kfree(significant_params);
+	return err;
+}
+#endif				/* GSCAN_SUPPORT */
+
+#if defined(RTT_SUPPORT) && 0
+void wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data)
+{
+	struct wireless_dev *wdev = (struct wireless_dev *)ctx;
+	struct wiphy *wiphy;
+	struct sk_buff *skb;
+	uint32 tot_len = NLMSG_DEFAULT_SIZE, entry_len = 0;
+	gfp_t kflags;
+	rtt_report_t *rtt_report = NULL;
+	rtt_result_t *rtt_result = NULL;
+	struct list_head *rtt_list;
+	wiphy = wdev->wiphy;
+
+	WL_DBG(("In\n"));
+	/* Push the data to the skb */
+	if (!rtt_data) {
+		WL_ERR(("rtt_data is NULL\n"));
+		goto exit;
+	}
+	rtt_list = (struct list_head *)rtt_data;
+	kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
+	/* Alloc the SKB for vendor_event */
+	skb =
+	    ssv_cfg80211_vendor_event_alloc(wiphy, tot_len,
+					    GOOGLE_RTT_COMPLETE_EVENT, kflags);
+	if (!skb) {
+		WL_ERR(("skb alloc failed"));
+		goto exit;
+	}
+	/* fill in the rtt results on each entry */
+	list_for_each_entry(rtt_result, rtt_list, list) {
+		entry_len = 0;
+		if (rtt_result->TOF_type == TOF_TYPE_ONE_WAY) {
+			entry_len = sizeof(rtt_report_t);
+			rtt_report = kzalloc(entry_len, kflags);
+			if (!rtt_report) {
+				WL_ERR(("rtt_report alloc failed"));
+				goto exit;
+			}
+			rtt_report->addr = rtt_result->peer_mac;
+			rtt_report->num_measurement = 1;	/* ONE SHOT */
+			rtt_report->status = rtt_result->err_code;
+			rtt_report->type =
+			    (rtt_result->TOF_type ==
+			     TOF_TYPE_ONE_WAY) ? RTT_ONE_WAY : RTT_TWO_WAY;
+			rtt_report->peer = rtt_result->target_info->peer;
+			rtt_report->channel = rtt_result->target_info->channel;
+			rtt_report->rssi = rtt_result->avg_rssi;
+			/* tx_rate */
+			rtt_report->tx_rate = rtt_result->tx_rate;
+			/* RTT */
+			rtt_report->rtt = rtt_result->meanrtt;
+			rtt_report->rtt_sd = rtt_result->sdrtt;
+			/* convert to centi meter */
+			if (rtt_result->distance != 0xffffffff)
+				rtt_report->distance =
+				    (rtt_result->distance >> 2) * 25;
+			else	/* invalid distance */
+				rtt_report->distance = -1;
+
+			rtt_report->ts = rtt_result->ts;
+			nla_append(skb, entry_len, rtt_report);
+			kfree(rtt_report);
+		}
+	}
+	ssv_cfg80211_vendor_event(skb, kflags);
+ exit:
+	return;
+}
+
+static int wl_cfgvendor_rtt_set_config(struct wiphy *wiphy,
+				       struct wireless_dev *wdev,
+				       const void *data, int len)
+{
+	int err = 0, rem, rem1, rem2, type;
+	rtt_config_params_t rtt_param;
+	rtt_target_info_t *rtt_target = NULL;
+	const struct nlattr *iter, *iter1, *iter2;
+	int8 eabuf[ETHER_ADDR_STR_LEN];
+	int8 chanbuf[CHANSPEC_STR_LEN];
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+
+	WL_DBG(("In\n"));
+	err =
+	    dhd_dev_rtt_register_noti_callback(wdev->netdev, wdev,
+					       wl_cfgvendor_rtt_evt);
+	if (err < 0) {
+		WL_ERR(("failed to register rtt_noti_callback\n"));
+		goto exit;
+	}
+	memset(&rtt_param, 0, sizeof(rtt_param));
+	nla_for_each_attr(iter, data, len, rem) {
+		type = nla_type(iter);
+		switch (type) {
+		case RTT_ATTRIBUTE_TARGET_CNT:
+			rtt_param.rtt_target_cnt = nla_get_u8(iter);
+			if (rtt_param.rtt_target_cnt > RTT_MAX_TARGET_CNT) {
+				WL_ERR(("exceed max target count : %d\n",
+					rtt_param.rtt_target_cnt));
+				err = BCME_RANGE;
+			}
+			break;
+		case RTT_ATTRIBUTE_TARGET_INFO:
+			rtt_target = rtt_param.target_info;
+			nla_for_each_nested(iter1, iter, rem1) {
+				nla_for_each_nested(iter2, iter1, rem2) {
+					type = nla_type(iter2);
+					switch (type) {
+					case RTT_ATTRIBUTE_TARGET_MAC:
+						memcpy(&rtt_target->addr,
+						       nla_data(iter2),
+						       ETHER_ADDR_LEN);
+						break;
+					case RTT_ATTRIBUTE_TARGET_TYPE:
+						rtt_target->type =
+						    nla_get_u8(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_PEER:
+						rtt_target->peer =
+						    nla_get_u8(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_CHAN:
+						memcpy(&rtt_target->channel,
+						       nla_data(iter2),
+						       sizeof(rtt_target->
+							      channel));
+						break;
+					case RTT_ATTRIBUTE_TARGET_MODE:
+						rtt_target->continuous =
+						    nla_get_u8(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_INTERVAL:
+						rtt_target->interval =
+						    nla_get_u32(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT:
+						rtt_target->measure_cnt =
+						    nla_get_u32(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_NUM_PKT:
+						rtt_target->ftm_cnt =
+						    nla_get_u32(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_NUM_RETRY:
+						rtt_target->retry_cnt =
+						    nla_get_u32(iter2);
+					}
+				}
+				/* convert to chanspec value */
+				rtt_target->chanspec =
+				    dhd_rtt_convert_to_chspec(rtt_target->
+							      channel);
+				if (rtt_target->chanspec == 0) {
+					WL_ERR(("Channel is not valid \n"));
+					goto exit;
+				}
+				WL_INFORM(("Target addr %s, Channel : %s for RTT \n", bcm_ether_ntoa((const struct ether_addr *)&rtt_target->addr, eabuf), wf_chspec_ntoa(rtt_target->chanspec, chanbuf)));
+				rtt_target++;
+			}
+			break;
+		}
+	}
+	WL_DBG(("leave :target_cnt : %d\n", rtt_param.rtt_target_cnt));
+	if (dhd_dev_rtt_set_cfg(bcmcfg_to_prmry_ndev(cfg), &rtt_param) < 0) {
+		WL_ERR(("Could not set RTT configuration\n"));
+		err = -EINVAL;
+	}
+ exit:
+	return err;
+}
+
+static int wl_cfgvendor_rtt_cancel_config(struct wiphy *wiphy,
+					  struct wireless_dev *wdev,
+					  const void *data, int len)
+{
+	int err = 0, rem, type, target_cnt = 0;
+	const struct nlattr *iter;
+	struct ether_addr *mac_list = NULL, *mac_addr = NULL;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+
+	nla_for_each_attr(iter, data, len, rem) {
+		type = nla_type(iter);
+		switch (type) {
+		case RTT_ATTRIBUTE_TARGET_CNT:
+			target_cnt = nla_get_u8(iter);
+			mac_list =
+			    (struct ether_addr *)kzalloc(target_cnt *
+							 ETHER_ADDR_LEN,
+							 GFP_KERNEL);
+			if (mac_list == NULL) {
+				WL_ERR(("failed to allocate mem for mac list\n"));
+				goto exit;
+			}
+			mac_addr = &mac_list[0];
+			break;
+		case RTT_ATTRIBUTE_TARGET_MAC:
+			if (mac_addr)
+				memcpy(mac_addr++, nla_data(iter),
+				       ETHER_ADDR_LEN);
+			else {
+				WL_ERR(("mac_list is NULL\n"));
+				goto exit;
+			}
+			break;
+		}
+		if (dhd_dev_rtt_cancel_cfg
+		    (bcmcfg_to_prmry_ndev(cfg), mac_list, target_cnt) < 0) {
+			WL_ERR(("Could not cancel RTT configuration\n"));
+			err = -EINVAL;
+			goto exit;
+		}
+	}
+ exit:
+	if (mac_list)
+		kfree(mac_list);
+	return err;
+}
+
+static int wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy,
+					   struct wireless_dev *wdev,
+					   const void *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	rtt_capabilities_t capability;
+
+	err = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability);
+	if (unlikely(err)) {
+		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
+		goto exit;
+	}
+	err = ssv_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
+					   &capability, sizeof(capability));
+
+	if (unlikely(err)) {
+		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
+	}
+ exit:
+	return err;
+}
+
+#endif				/* RTT_SUPPORT */
+static int wl_cfgvendor_priv_string_handler(struct wiphy *wiphy,
+					    struct wireless_dev *wdev,
+					    const void *data, int len)
+{
+	int err = 0;
+	u8 resp[1] = { '\0' };
+
+	dev_dbg(&wiphy->dev, "%s\n", (char *)data);
+	err = ssv_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), resp, 1);
+	if (unlikely(err))
+		dev_err(&wiphy->dev, "vendor Command reply failed, ret=:%d\n", err);
+
+	return err;
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+static const struct wiphy_vendor_command ssv_vendor_cmds[] = {
+	{
+	 {
+	  .vendor_id = OUI_SSV,
+	  .subcmd = RTK_VENDOR_SCMD_PRIV_STR},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_priv_string_handler,
+	 .policy = VENDOR_CMD_RAW_DATA},
+#if defined(GSCAN_SUPPORT) && 0
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_gscan_get_capabilities,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_set_scan_cfg,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_set_batch_scan_cfg,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_initiate_gscan,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_enable_full_scan_result,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_HOTLIST},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_hotlist_cfg,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_significant_change_cfg,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_gscan_get_batch_results,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_gscan_get_channel_list,
+	 .policy = VENDOR_CMD_RAW_DATA},
+#endif				/* GSCAN_SUPPORT */
+#if defined(RTT_SUPPORT) && 0
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = RTT_SUBCMD_SET_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_rtt_set_config,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = RTT_SUBCMD_CANCEL_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_rtt_cancel_config,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = RTT_SUBCMD_GETCAPABILITY},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_rtt_get_capability,
+	 .policy = VENDOR_CMD_RAW_DATA},
+#endif				/* RTT_SUPPORT */
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = ssv_cfgvendor_get_feature_set,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = ssv_cfgvendor_get_feature_set_matrix,
+	 .policy = VENDOR_CMD_RAW_DATA}
+};
+#else
+static const struct wiphy_vendor_command ssv_vendor_cmds[] = {
+	{
+	 {
+	  .vendor_id = OUI_SSV,
+	  .subcmd = RTK_VENDOR_SCMD_PRIV_STR},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_priv_string_handler
+	},
+#if defined(GSCAN_SUPPORT) && 0
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_gscan_get_capabilities
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_set_scan_cfg
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_set_batch_scan_cfg
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_initiate_gscan
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_enable_full_scan_result
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_HOTLIST},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_hotlist_cfg
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_significant_change_cfg
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_gscan_get_batch_results
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_gscan_get_channel_list
+	},
+#endif				/* GSCAN_SUPPORT */
+#if defined(RTT_SUPPORT) && 0
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = RTT_SUBCMD_SET_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_rtt_set_config
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = RTT_SUBCMD_CANCEL_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_rtt_cancel_config
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = RTT_SUBCMD_GETCAPABILITY},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_rtt_get_capability
+	},
+#endif				/* RTT_SUPPORT */
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = ssv_cfgvendor_get_feature_set
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = ssv_cfgvendor_get_feature_set_matrix
+	}
+};
+#endif
+
+static const struct nl80211_vendor_cmd_info ssv_vendor_events[] = {
+	{OUI_SSV, RTK_VENDOR_EVENT_UNSPEC},
+	{OUI_SSV, RTK_VENDOR_EVENT_PRIV_STR},
+#if defined(GSCAN_SUPPORT) && 0
+	{OUI_GOOGLE, GOOGLE_GSCAN_SIGNIFICANT_EVENT},
+	{OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT},
+	{OUI_GOOGLE, GOOGLE_GSCAN_BATCH_SCAN_EVENT},
+	{OUI_GOOGLE, GOOGLE_SCAN_FULL_RESULTS_EVENT},
+#endif				/* GSCAN_SUPPORT */
+#if defined(RTT_SUPPORT) && 0
+	{OUI_GOOGLE, GOOGLE_RTT_COMPLETE_EVENT},
+#endif				/* RTT_SUPPORT */
+#if defined(GSCAN_SUPPORT) && 0
+	{OUI_GOOGLE, GOOGLE_SCAN_COMPLETE_EVENT},
+	{OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_LOST_EVENT}
+#endif				/* GSCAN_SUPPORT */
+};
+
+int ssv_cfgvendor_attach(struct wiphy *wiphy)
+{
+
+	dev_info(&wiphy->dev, "register SSV cfg80211 vendor cmd(0x%x) interface\n",
+		NL80211_CMD_VENDOR);
+
+	wiphy->vendor_commands = ssv_vendor_cmds;
+	wiphy->n_vendor_commands = ARRAY_SIZE(ssv_vendor_cmds);
+	wiphy->vendor_events = ssv_vendor_events;
+	wiphy->n_vendor_events = ARRAY_SIZE(ssv_vendor_events);
+
+	return 0;
+}
+
+int ssv_cfgvendor_detach(struct wiphy *wiphy)
+{
+	dev_info(&wiphy->dev, "unregister SSV cfg80211 vendor interface\n");
+
+	wiphy->vendor_commands = NULL;
+	wiphy->vendor_events = NULL;
+	wiphy->n_vendor_commands = 0;
+	wiphy->n_vendor_events = 0;
+
+	return 0;
+}
+#endif				/* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(SSV_VENDOR_EXT_SUPPORT) */
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
new file mode 100644
index 00000000000..6d8696fcd22
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
@@ -0,0 +1,247 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef _RTW_CFGVENDOR_H_
+#define _RTW_CFGVENDOR_H_
+
+#define OUI_SSV		0x00E04C
+#define OUI_GOOGLE	0x001A11
+#define ATTRIBUTE_U32_LEN                  (NLA_HDRLEN  + 4)
+#define VENDOR_ID_OVERHEAD                 ATTRIBUTE_U32_LEN
+#define VENDOR_SUBCMD_OVERHEAD             ATTRIBUTE_U32_LEN
+#define VENDOR_DATA_OVERHEAD               (NLA_HDRLEN)
+
+#define SCAN_RESULTS_COMPLETE_FLAG_LEN       ATTRIBUTE_U32_LEN
+#define SCAN_INDEX_HDR_LEN                   (NLA_HDRLEN)
+#define SCAN_ID_HDR_LEN                      ATTRIBUTE_U32_LEN
+#define SCAN_FLAGS_HDR_LEN                   ATTRIBUTE_U32_LEN
+#define GSCAN_NUM_RESULTS_HDR_LEN            ATTRIBUTE_U32_LEN
+#define GSCAN_RESULTS_HDR_LEN                (NLA_HDRLEN)
+#define GSCAN_BATCH_RESULT_HDR_LEN  (SCAN_INDEX_HDR_LEN + SCAN_ID_HDR_LEN + \
+									SCAN_FLAGS_HDR_LEN + \
+							        GSCAN_NUM_RESULTS_HDR_LEN + \
+									GSCAN_RESULTS_HDR_LEN)
+
+#define VENDOR_REPLY_OVERHEAD       (VENDOR_ID_OVERHEAD + \
+									VENDOR_SUBCMD_OVERHEAD + \
+									VENDOR_DATA_OVERHEAD)
+typedef enum {
+	/* don't use 0 as a valid subcommand */
+	VENDOR_NL80211_SUBCMD_UNSPECIFIED,
+
+	/* define all vendor startup commands between 0x0 and 0x0FFF */
+	VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001,
+	VENDOR_NL80211_SUBCMD_RANGE_END = 0x0FFF,
+
+	/* define all GScan related commands between 0x1000 and 0x10FF */
+	ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000,
+	ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END = 0x10FF,
+
+	/* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */
+	ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100,
+	ANDROID_NL80211_SUBCMD_NBD_RANGE_END = 0x11FF,
+
+	/* define all RTT related commands between 0x1100 and 0x11FF */
+	ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100,
+	ANDROID_NL80211_SUBCMD_RTT_RANGE_END = 0x11FF,
+
+	ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200,
+	ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END = 0x12FF,
+
+	ANDROID_NL80211_SUBCMD_TDLS_RANGE_START = 0x1300,
+	ANDROID_NL80211_SUBCMD_TDLS_RANGE_END = 0x13FF,
+	/* This is reserved for future usage */
+
+} ANDROID_VENDOR_SUB_COMMAND;
+
+enum wl_vendor_subcmd {
+	RTK_VENDOR_SCMD_UNSPEC,
+	RTK_VENDOR_SCMD_PRIV_STR,
+	GSCAN_SUBCMD_GET_CAPABILITIES =
+	    ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START,
+	GSCAN_SUBCMD_SET_CONFIG,
+	GSCAN_SUBCMD_SET_SCAN_CONFIG,
+	GSCAN_SUBCMD_ENABLE_GSCAN,
+	GSCAN_SUBCMD_GET_SCAN_RESULTS,
+	GSCAN_SUBCMD_SCAN_RESULTS,
+	GSCAN_SUBCMD_SET_HOTLIST,
+	GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG,
+	GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS,
+	GSCAN_SUBCMD_GET_CHANNEL_LIST,
+	ANDR_WIFI_SUBCMD_GET_FEATURE_SET,
+	ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX,
+	RTT_SUBCMD_SET_CONFIG = ANDROID_NL80211_SUBCMD_RTT_RANGE_START,
+	RTT_SUBCMD_CANCEL_CONFIG,
+	RTT_SUBCMD_GETCAPABILITY,
+	/* Add more sub commands here */
+	VENDOR_SUBCMD_MAX
+};
+
+enum gscan_attributes {
+	GSCAN_ATTRIBUTE_NUM_BUCKETS = 10,
+	GSCAN_ATTRIBUTE_BASE_PERIOD,
+	GSCAN_ATTRIBUTE_BUCKETS_BAND,
+	GSCAN_ATTRIBUTE_BUCKET_ID,
+	GSCAN_ATTRIBUTE_BUCKET_PERIOD,
+	GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS,
+	GSCAN_ATTRIBUTE_BUCKET_CHANNELS,
+	GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN,
+	GSCAN_ATTRIBUTE_REPORT_THRESHOLD,
+	GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE,
+	GSCAN_ATTRIBUTE_BAND = GSCAN_ATTRIBUTE_BUCKETS_BAND,
+
+	GSCAN_ATTRIBUTE_ENABLE_FEATURE = 20,
+	GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE,
+	GSCAN_ATTRIBUTE_FLUSH_FEATURE,
+	GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS,
+	GSCAN_ATTRIBUTE_REPORT_EVENTS,
+	/* remaining reserved for additional attributes */
+	GSCAN_ATTRIBUTE_NUM_OF_RESULTS = 30,
+	GSCAN_ATTRIBUTE_FLUSH_RESULTS,
+	GSCAN_ATTRIBUTE_SCAN_RESULTS,	/* flat array of wifi_scan_result */
+	GSCAN_ATTRIBUTE_SCAN_ID,	/* indicates scan number */
+	GSCAN_ATTRIBUTE_SCAN_FLAGS,	/* indicates if scan was aborted */
+	GSCAN_ATTRIBUTE_AP_FLAGS,	/* flags on significant change event */
+	GSCAN_ATTRIBUTE_NUM_CHANNELS,
+	GSCAN_ATTRIBUTE_CHANNEL_LIST,
+
+	/* remaining reserved for additional attributes */
+
+	GSCAN_ATTRIBUTE_SSID = 40,
+	GSCAN_ATTRIBUTE_BSSID,
+	GSCAN_ATTRIBUTE_CHANNEL,
+	GSCAN_ATTRIBUTE_RSSI,
+	GSCAN_ATTRIBUTE_TIMESTAMP,
+	GSCAN_ATTRIBUTE_RTT,
+	GSCAN_ATTRIBUTE_RTTSD,
+
+	/* remaining reserved for additional attributes */
+
+	GSCAN_ATTRIBUTE_HOTLIST_BSSIDS = 50,
+	GSCAN_ATTRIBUTE_RSSI_LOW,
+	GSCAN_ATTRIBUTE_RSSI_HIGH,
+	GSCAN_ATTRIBUTE_HOSTLIST_BSSID_ELEM,
+	GSCAN_ATTRIBUTE_HOTLIST_FLUSH,
+
+	/* remaining reserved for additional attributes */
+	GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE = 60,
+	GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE,
+	GSCAN_ATTRIBUTE_MIN_BREACHING,
+	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS,
+	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH,
+	GSCAN_ATTRIBUTE_MAX
+};
+
+enum gscan_bucket_attributes {
+	GSCAN_ATTRIBUTE_CH_BUCKET_1,
+	GSCAN_ATTRIBUTE_CH_BUCKET_2,
+	GSCAN_ATTRIBUTE_CH_BUCKET_3,
+	GSCAN_ATTRIBUTE_CH_BUCKET_4,
+	GSCAN_ATTRIBUTE_CH_BUCKET_5,
+	GSCAN_ATTRIBUTE_CH_BUCKET_6,
+	GSCAN_ATTRIBUTE_CH_BUCKET_7
+};
+
+enum gscan_ch_attributes {
+	GSCAN_ATTRIBUTE_CH_ID_1,
+	GSCAN_ATTRIBUTE_CH_ID_2,
+	GSCAN_ATTRIBUTE_CH_ID_3,
+	GSCAN_ATTRIBUTE_CH_ID_4,
+	GSCAN_ATTRIBUTE_CH_ID_5,
+	GSCAN_ATTRIBUTE_CH_ID_6,
+	GSCAN_ATTRIBUTE_CH_ID_7
+};
+
+enum rtt_attributes {
+	RTT_ATTRIBUTE_TARGET_CNT,
+	RTT_ATTRIBUTE_TARGET_INFO,
+	RTT_ATTRIBUTE_TARGET_MAC,
+	RTT_ATTRIBUTE_TARGET_TYPE,
+	RTT_ATTRIBUTE_TARGET_PEER,
+	RTT_ATTRIBUTE_TARGET_CHAN,
+	RTT_ATTRIBUTE_TARGET_MODE,
+	RTT_ATTRIBUTE_TARGET_INTERVAL,
+	RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT,
+	RTT_ATTRIBUTE_TARGET_NUM_PKT,
+	RTT_ATTRIBUTE_TARGET_NUM_RETRY
+};
+
+typedef enum wl_vendor_event {
+	RTK_VENDOR_EVENT_UNSPEC,
+	RTK_VENDOR_EVENT_PRIV_STR,
+	GOOGLE_GSCAN_SIGNIFICANT_EVENT,
+	GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT,
+	GOOGLE_GSCAN_BATCH_SCAN_EVENT,
+	GOOGLE_SCAN_FULL_RESULTS_EVENT,
+	GOOGLE_RTT_COMPLETE_EVENT,
+	GOOGLE_SCAN_COMPLETE_EVENT,
+	GOOGLE_GSCAN_GEOFENCE_LOST_EVENT
+} wl_vendor_event_t;
+
+enum andr_wifi_feature_set_attr {
+	ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET,
+	ANDR_WIFI_ATTRIBUTE_FEATURE_SET
+};
+
+typedef enum wl_vendor_gscan_attribute {
+	ATTR_START_GSCAN,
+	ATTR_STOP_GSCAN,
+	ATTR_SET_SCAN_BATCH_CFG_ID,	/* set batch scan params */
+	ATTR_SET_SCAN_GEOFENCE_CFG_ID,	/* set list of bssids to track */
+	ATTR_SET_SCAN_SIGNIFICANT_CFG_ID,	/* set list of bssids, rssi threshold etc.. */
+	ATTR_SET_SCAN_CFG_ID,	/* set common scan config params here */
+	ATTR_GET_GSCAN_CAPABILITIES_ID,
+	/* Add more sub commands here */
+	ATTR_GSCAN_MAX
+} wl_vendor_gscan_attribute_t;
+
+typedef enum gscan_batch_attribute {
+	ATTR_GSCAN_BATCH_BESTN,
+	ATTR_GSCAN_BATCH_MSCAN,
+	ATTR_GSCAN_BATCH_BUFFER_THRESHOLD
+} gscan_batch_attribute_t;
+
+typedef enum gscan_geofence_attribute {
+	ATTR_GSCAN_NUM_HOTLIST_BSSID,
+	ATTR_GSCAN_HOTLIST_BSSID
+} gscan_geofence_attribute_t;
+
+typedef enum gscan_complete_event {
+	WIFI_SCAN_BUFFER_FULL,
+	WIFI_SCAN_COMPLETE
+} gscan_complete_event_t;
+
+/* Capture the RTK_VENDOR_SUBCMD_PRIV_STRINGS* here */
+#define RTK_VENDOR_SCMD_CAPA	"cap"
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(SSV_VENDOR_EXT_SUPPORT)
+extern int ssv_cfgvendor_attach(struct wiphy *wiphy);
+extern int ssv_cfgvendor_detach(struct wiphy *wiphy);
+extern int ssv_cfgvendor_send_async_event(struct wiphy *wiphy,
+					  struct net_device *dev, int event_id,
+					  const void *data, int len);
+#if defined(GSCAN_SUPPORT) && 0
+extern int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
+					   struct net_device *dev, void *data,
+					   int len, wl_vendor_event_t event);
+#endif
+#endif				/* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */
+
+#endif				/* _RTW_CFGVENDOR_H_ */
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
new file mode 100644
index 00000000000..fae819c4340
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
@@ -0,0 +1,546 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ssv_ht_rc.h"
+#include "ssv_rc.h"
+#define SAMPLE_COUNT 4
+#define HT_CW_MIN 15
+#define HT_SEGMENT_SIZE 6000
+#define AVG_PKT_SIZE 12000
+#define SAMPLE_COLUMNS 10
+#define EWMA_LEVEL 75
+#define MCS_NBITS (AVG_PKT_SIZE << 3)
+#define MCS_NSYMS(bps) ((MCS_NBITS + (bps) - 1) / (bps))
+#define MCS_SYMBOL_TIME(sgi,syms) \
+    (sgi ? \
+      ((syms) * 18 + 4) / 5 : \
+      (syms) << 2 \
+    )
+#define MCS_DURATION(streams,sgi,bps) MCS_SYMBOL_TIME(sgi, MCS_NSYMS((streams) * (bps)))
+#define MCS_GROUP(_streams,_sgi,_ht40) { \
+    .duration = { \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 54 : 26), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 108 : 52), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 162 : 78), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 216 : 104), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 324 : 156), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 432 : 208), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 486 : 234), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 540 : 260) \
+    } \
+}
+const struct mcs_group minstrel_mcs_groups_ssv[] = {
+	MCS_GROUP(1, 0, 0),
+	MCS_GROUP(1, 1, 0),
+};
+
+const u16 ampdu_max_transmit_length[RATE_TABLE_SIZE] = {
+	0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0,
+	4600, 9200, 13800, 18500, 27700, 37000, 41600, 46200,
+	5100, 10200, 15400, 20500, 30800, 41100, 46200, 51300,
+	4600, 9200, 13800, 18500, 27700, 37000, 41600, 46200
+};
+
+static u8 sample_table[SAMPLE_COLUMNS][MCS_GROUP_RATES];
+static int minstrel_ewma(int old, int new, int weight)
+{
+	return (new * (100 - weight) + old * weight) / 100;
+}
+
+static inline struct minstrel_rate_stats *minstrel_get_ratestats(struct
+								 ssv62xx_ht *mi,
+								 int index)
+{
+	return &mi->groups.rates[index % MCS_GROUP_RATES];
+}
+
+static void minstrel_calc_rate_ewma(struct minstrel_rate_stats *mr)
+{
+	if (unlikely(mr->attempts > 0)) {
+		mr->sample_skipped = 0;
+		mr->cur_prob = MINSTREL_FRAC(mr->success, mr->attempts);
+		if (!mr->att_hist)
+			mr->probability = mr->cur_prob;
+		else
+			mr->probability = minstrel_ewma(mr->probability,
+							mr->cur_prob,
+							EWMA_LEVEL);
+		mr->att_hist += mr->attempts;
+		mr->succ_hist += mr->success;
+	} else {
+		mr->sample_skipped++;
+	}
+	mr->last_success = mr->success;
+	mr->last_attempts = mr->attempts;
+	mr->success = 0;
+	mr->attempts = 0;
+}
+
+static void minstrel_ht_calc_tp(struct ssv62xx_ht *mi,
+				struct ssv_sta_rc_info *rc_sta, int rate)
+{
+	struct minstrel_rate_stats *mr;
+	unsigned int usecs, group_id;
+	if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
+		group_id = 0;
+	else
+		group_id = 1;
+	mr = &mi->groups.rates[rate];
+	if (mr->probability < MINSTREL_FRAC(1, 10)) {
+		mr->cur_tp = 0;
+		return;
+	}
+	usecs = mi->overhead / MINSTREL_TRUNC(mi->avg_ampdu_len);
+	usecs += minstrel_mcs_groups_ssv[group_id].duration[rate];
+	mr->cur_tp = MINSTREL_TRUNC((1000000 / usecs) * mr->probability);
+}
+
+static void rate_control_ht_sample(struct ssv62xx_ht *mi,
+				   struct ssv_sta_rc_info *rc_sta)
+{
+	struct minstrel_mcs_group_data *mg;
+	struct minstrel_rate_stats *mr;
+	int cur_prob, cur_prob_tp, cur_tp, cur_tp2;
+	int i, index;
+	if (mi->ampdu_packets > 0) {
+		mi->avg_ampdu_len = minstrel_ewma(mi->avg_ampdu_len,
+						  MINSTREL_FRAC(mi->ampdu_len,
+								mi->
+								ampdu_packets),
+						  EWMA_LEVEL);
+		mi->ampdu_len = 0;
+		mi->ampdu_packets = 0;
+	} else
+		return;
+	mi->sample_slow = 0;
+	mi->sample_count = 0;
+	{
+		cur_prob = 0;
+		cur_prob_tp = 0;
+		cur_tp = 0;
+		cur_tp2 = 0;
+		mg = &mi->groups;
+		mg->max_tp_rate = 0;
+		mg->max_tp_rate2 = 0;
+		mg->max_prob_rate = 0;
+		for (i = 0; i < MCS_GROUP_RATES; i++) {
+			if (!(rc_sta->ht_supp_rates & BIT(i)))
+				continue;
+			mr = &mg->rates[i];
+			index = i;
+			minstrel_calc_rate_ewma(mr);
+			minstrel_ht_calc_tp(mi, rc_sta, i);
+#ifdef RATE_CONTROL_HT_PARAMETER_DEBUG
+			if (mr->cur_prob)
+				pr_debug
+				    ("rate[%d]probability[%08d]cur_prob[%08d]TP[%04d]\n",
+				     i, mr->probability, mr->cur_prob,
+				     mr->cur_tp);
+#endif
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+			pr_debug
+			    ("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n",
+			     mg->max_tp_rate, mg->max_tp_rate2,
+			     mg->max_prob_rate);
+			pr_debug("rate[%d]probability[%08d]TP[%d]\n", i,
+			       mr->probability, mr->cur_tp);
+#endif
+			if (!mr->cur_tp)
+				continue;
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+			pr_debug("HT--1 mr->cur_tp[%d]cur_prob_tp[%d]\n",
+			       mr->cur_tp, cur_prob_tp);
+#endif
+			if ((mr->cur_tp > cur_prob_tp && mr->probability >
+			     MINSTREL_FRAC(3, 4))
+			    || mr->probability > cur_prob) {
+				mg->max_prob_rate = index;
+				cur_prob = mr->probability;
+				cur_prob_tp = mr->cur_tp;
+			}
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+			pr_debug("HT--2 mr->cur_tp[%d]cur_tp[%d]\n", mr->cur_tp,
+			       cur_tp);
+#endif
+			if (mr->cur_tp > cur_tp) {
+				swap(index, mg->max_tp_rate);
+				cur_tp = mr->cur_tp;
+				mr = minstrel_get_ratestats(mi, index);
+			}
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+			if (index != i)
+				pr_debug
+				    ("HT--3 index[%d]i[%d]mg->max_tp_rate[%d]\n",
+				     index, i, mg->max_tp_rate);
+#endif
+			if (index >= mg->max_tp_rate)
+				continue;
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+			if (index != i)
+				pr_debug("HT--4 mr->cur_tp[%d]cur_tp2[%d]\n",
+				       mr->cur_tp, cur_tp2);
+#endif
+			if (mr->cur_tp > cur_tp2) {
+				mg->max_tp_rate2 = index;
+				cur_tp2 = mr->cur_tp;
+			}
+		}
+	}
+	mi->sample_count = SAMPLE_COUNT;
+	mi->max_tp_rate = mg->max_tp_rate;
+	mi->max_tp_rate2 = mg->max_tp_rate2;
+	mi->max_prob_rate = mg->max_prob_rate;
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+	pr_debug
+	    ("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n",
+	     mi->max_tp_rate, mi->max_tp_rate2, mi->max_prob_rate);
+#endif
+	mi->stats_update = jiffies;
+}
+
+static void minstrel_ht_set_rate(struct ssv62xx_ht *mi,
+				 struct fw_rc_retry_params *rate, int index,
+				 bool sample, bool rtscts,
+				 struct ssv_sta_rc_info *rc_sta,
+				 struct ssv_rate_ctrl *ssv_rc)
+{
+	struct minstrel_rate_stats *mr;
+	mr = minstrel_get_ratestats(mi, index);
+	rate->drate = ssv_rc->rc_table[mr->rc_index].hw_rate_idx;
+	rate->crate = ssv_rc->rc_table[mr->rc_index].ctrl_rate_idx;
+}
+
+static inline int minstrel_get_duration(int index,
+					struct ssv_sta_rc_info *rc_sta)
+{
+	unsigned int group_id;
+	const struct mcs_group *group;
+	if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
+		group_id = 0;
+	else
+		group_id = 1;
+	group = &minstrel_mcs_groups_ssv[group_id];
+	return group->duration[index % MCS_GROUP_RATES];
+}
+
+static void minstrel_next_sample_idx(struct ssv62xx_ht *mi)
+{
+	struct minstrel_mcs_group_data *mg;
+	for (;;) {
+		mg = &mi->groups;
+		if (++mg->index >= MCS_GROUP_RATES) {
+			mg->index = 0;
+			if (++mg->column >= ARRAY_SIZE(sample_table))
+				mg->column = 0;
+		}
+		break;
+	}
+}
+
+static int minstrel_get_sample_rate(struct ssv62xx_ht *mi,
+				    struct ssv_sta_rc_info *rc_sta)
+{
+	struct minstrel_rate_stats *mr;
+	struct minstrel_mcs_group_data *mg;
+	int sample_idx = 0;
+	if (mi->sample_wait > 0) {
+		mi->sample_wait--;
+		return -1;
+	}
+	if (!mi->sample_tries)
+		return -1;
+	mi->sample_tries--;
+	mg = &mi->groups;
+	sample_idx = sample_table[mg->column][mg->index];
+	mr = &mg->rates[sample_idx];
+	minstrel_next_sample_idx(mi);
+	if (minstrel_get_duration(sample_idx, rc_sta) >
+	    minstrel_get_duration(mi->max_tp_rate, rc_sta)) {
+		if (mr->sample_skipped < 20) {
+			return -1;
+		}
+		if (mi->sample_slow++ > 2) {
+			return -1;
+		}
+	}
+	return sample_idx;
+}
+
+static void _fill_txinfo_rates(struct ssv_rate_ctrl *ssv_rc,
+			       struct sk_buff *skb,
+			       struct fw_rc_retry_params *ar)
+{
+	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+	info->control.rates[0].idx =
+	    ssv_rc->rc_table[ar[0].drate].dot11_rate_idx;
+	info->control.rates[0].count = 1;
+	info->control.rates[SSV_DRATE_IDX].count = ar[0].drate;
+	info->control.rates[SSV_CRATE_IDX].count = ar[0].crate;
+}
+
+extern const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13];
+s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc,
+			   struct fw_rc_retry_params *ar)
+{
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+	struct ieee80211_sta *sta = skb_info->sta;
+	struct ssv62xx_ht *mi = NULL;
+	int sample_idx;
+	bool sample = false;
+	struct ssv_sta_rc_info *rc_sta;
+	struct ssv_sta_priv_data *sta_priv;
+	struct rc_pid_sta_info *spinfo;
+	int ret = 0;
+	if (sc->sc_flags & SC_OP_FIXED_RATE) {
+		ar[0].count = 3;
+		ar[0].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+		ar[0].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
+		ar[1].count = 2;
+		ar[1].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+		ar[1].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
+		ar[2].count = 2;
+		ar[2].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+		ar[2].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
+		_fill_txinfo_rates(ssv_rc, skb, ar);
+		return ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+	}
+	if (sta == NULL) {
+		dev_err(sc->dev, "Station NULL\n");
+		BUG_ON(1);
+	}
+	sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx];
+	spinfo = &rc_sta->spinfo;
+	if ((rc_sta->rc_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT)
+	    || (rc_sta->rc_wsid < 0)) {
+		struct ssv_sta_priv_data *ssv_sta_priv;
+		int rateidx = 99;
+		ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+		{
+			if ((rc_sta->ht_rc_type >= RC_TYPE_HT_SGI_20) &&
+			    (ssv_sta_priv->rx_data_rate <
+			     SSV62XX_RATE_MCS_INDEX)) {
+				if (ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0]
+				    == 12)
+					rateidx =
+					    (int)rc_sta->pinfo.rinfo[4].
+					    rc_index;
+				else
+					rateidx =
+					    (int)rc_sta->pinfo.rinfo[0].
+					    rc_index;
+			} else {
+				rateidx = (int)ssv_sta_priv->rx_data_rate;
+				rateidx -= SSV62XX_RATE_MCS_INDEX;
+				rateidx %= 8;
+				if (rc_sta->ht_rc_type == RC_TYPE_HT_SGI_20)
+					rateidx += SSV62XX_RATE_MCS_SGI_INDEX;
+				else if (rc_sta->ht_rc_type ==
+					 RC_TYPE_HT_LGI_20)
+					rateidx += SSV62XX_RATE_MCS_LGI_INDEX;
+				else
+					rateidx +=
+					    SSV62XX_RATE_MCS_GREENFIELD_INDEX;
+			}
+		}
+		ar[0].count = 3;
+		ar[2].drate = ar[1].drate = ar[0].drate =
+		    ssv_rc->rc_table[rateidx].hw_rate_idx;
+		ar[2].crate = ar[1].crate = ar[0].crate =
+		    ssv_rc->rc_table[rateidx].ctrl_rate_idx;
+		ar[1].count = 2;
+		ar[2].count = 2;
+		_fill_txinfo_rates(ssv_rc, skb, ar);
+		return rateidx;
+	}
+	mi = &rc_sta->ht;
+	sample_idx = minstrel_get_sample_rate(mi, rc_sta);
+	if (sample_idx >= 0) {
+		sample = true;
+		minstrel_ht_set_rate(mi, &ar[0], sample_idx,
+				     true, false, rc_sta, ssv_rc);
+	} else {
+		minstrel_ht_set_rate(mi, &ar[0], mi->max_tp_rate,
+				     false, false, rc_sta, ssv_rc);
+	}
+	ar[0].count = mi->first_try_count;
+	ret = ar[0].drate;
+	{
+		if (sample_idx >= 0)
+			minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate,
+					     false, false, rc_sta, ssv_rc);
+		else
+			minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate2,
+					     false, true, rc_sta, ssv_rc);
+		ar[1].count = mi->second_try_count;
+		if (ret > ar[1].drate)
+			ret = ar[1].drate;
+		minstrel_ht_set_rate(mi, &ar[2], mi->max_prob_rate,
+				     false, !sample, rc_sta, ssv_rc);
+		ar[2].count = mi->other_try_count;
+		if (ret > ar[2].drate)
+			ret = ar[2].drate;
+	}
+	mi->total_packets++;
+	if (mi->total_packets == ~0) {
+		mi->total_packets = 0;
+		mi->sample_packets = 0;
+	}
+	if (spinfo->real_hw_index < SSV62XX_RATE_MCS_INDEX)
+		return spinfo->real_hw_index;
+	_fill_txinfo_rates(ssv_rc, skb, ar);
+	return ret;
+}
+
+static void init_sample_table(void)
+{
+	int col, i, new_idx;
+	u8 rnd[MCS_GROUP_RATES];
+	memset(sample_table, 0xff, sizeof(sample_table));
+	for (col = 0; col < SAMPLE_COLUMNS; col++) {
+		for (i = 0; i < MCS_GROUP_RATES; i++) {
+			get_random_bytes(rnd, sizeof(rnd));
+			new_idx = (i + rnd[i]) % MCS_GROUP_RATES;
+			while (sample_table[col][new_idx] != 0xff)
+				new_idx = (new_idx + 1) % MCS_GROUP_RATES;
+			sample_table[col][new_idx] = i;
+		}
+	}
+}
+
+void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],
+			struct ssv_sta_rc_info *rc_sta)
+{
+	struct ssv62xx_ht *mi = &rc_sta->ht;
+	int ack_dur;
+	int i;
+	unsigned int group_id;
+	if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
+		group_id = 0;
+	else
+		group_id = 1;
+	for (i = 0; i < MCS_GROUP_RATES; i++) {
+		pr_debug("[RC]HT duration[%d][%d]\n", i,
+		       minstrel_mcs_groups_ssv[group_id].duration[i]);
+	}
+	init_sample_table();
+	memset(mi, 0, sizeof(*mi));
+	mi->stats_update = jiffies;
+	ack_dur = pide_frame_duration(10, 60, 0, 0);
+	mi->overhead = pide_frame_duration(0, 60, 0, 0) + ack_dur;
+	mi->overhead_rtscts = mi->overhead + 2 * ack_dur;
+	mi->avg_ampdu_len = MINSTREL_FRAC(1, 1);
+	mi->sample_count = 16;
+	mi->sample_wait = 0;
+	mi->sample_tries = 4;
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+	mi->max_tp_rate = MCS_GROUP_RATES - 1;
+	mi->max_tp_rate2 = MCS_GROUP_RATES - 1;
+	mi->max_prob_rate = MCS_GROUP_RATES - 1;
+#endif
+#if (HW_MAX_RATE_TRIES == 7)
+	{
+		mi->first_try_count = 3;
+		mi->second_try_count = 2;
+		mi->other_try_count = 2;
+	}
+#else
+	{
+		mi->first_try_count = 2;
+		mi->second_try_count = 1;
+		mi->other_try_count = 1;
+	}
+#endif
+	for (i = 0; i < MCS_GROUP_RATES; i++) {
+		mi->groups.rates[i].rc_index =
+		    ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][i + 1];
+	}
+}
+
+static bool minstrel_ht_txstat_valid(struct ssv62xx_tx_rate *rate)
+{
+	if (!rate->count)
+		return false;
+	if (rate->data_rate < 0)
+		return false;
+	return true;
+}
+
+void ssv6xxx_ht_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
+			       struct ssv_sta_rc_info *rc_sta)
+{
+	struct cfg_host_event *host_event;
+	struct firmware_rate_control_report_data *report_data;
+	struct ssv62xx_ht *mi;
+	struct minstrel_rate_stats *rate;
+	bool last = false;
+	int i = 0;
+	u16 report_ampdu_packets = 0;
+	unsigned long period;
+	host_event = (struct cfg_host_event *)skb->data;
+	report_data =
+	    (struct firmware_rate_control_report_data *)&host_event->dat[0];
+	if (host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) {
+		report_ampdu_packets = 1;
+	} else if (host_event->h_event == SOC_EVT_RC_MPDU_REPORT) {
+		report_data->ampdu_len = 1;
+		report_ampdu_packets = report_data->ampdu_len;
+	} else {
+		dev_warn(sc->dev, "rate control report handler got garbage\n");
+		return;
+	}
+	mi = &rc_sta->ht;
+	mi->ampdu_packets += report_ampdu_packets;
+	mi->ampdu_len += report_data->ampdu_len;
+	if (!mi->sample_wait && !mi->sample_tries && mi->sample_count > 0) {
+		mi->sample_wait = 16 + 2 * MINSTREL_TRUNC(mi->avg_ampdu_len);
+		mi->sample_tries = 2;
+		mi->sample_count--;
+	}
+	for (i = 0; !last; i++) {
+		last = (i == SSV62XX_TX_MAX_RATES - 1) ||
+		    !minstrel_ht_txstat_valid(&report_data->rates[i + 1]);
+		if (!minstrel_ht_txstat_valid(&report_data->rates[i]))
+			break;
+#ifdef RATE_CONTROL_DEBUG
+		if ((report_data->rates[i].data_rate < SSV62XX_RATE_MCS_INDEX)
+		    || (report_data->rates[i].data_rate >=
+			SSV62XX_RATE_MCS_GREENFIELD_INDEX)) {
+			dev_dbg
+			    (sc->dev, "[RC]ssv6xxx_ht_report_handler get error report rate[%d]\n",
+			     report_data->rates[i].data_rate);
+			break;
+		}
+#endif
+		rate =
+		    &mi->groups.
+		    rates[(report_data->rates[i].data_rate -
+			   SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES];
+		if (last)
+			rate->success += report_data->ampdu_ack_len;
+		rate->attempts +=
+		    report_data->rates[i].count * report_data->ampdu_len;
+	}
+	period = msecs_to_jiffies(SSV_RC_HT_INTERVAL / 2);
+	if (time_after(jiffies, mi->stats_update + period)) {
+		rate_control_ht_sample(mi, rc_sta);
+	}
+}
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
new file mode 100644
index 00000000000..275c3356e03
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_RC_HT_H_
+#define _SSV_RC_HT_H_
+#include "ssv_rc_common.h"
+#define MINSTREL_SCALE 16
+#define MINSTREL_FRAC(val,div) (((val) << MINSTREL_SCALE) / div)
+#define MINSTREL_TRUNC(val) ((val) >> MINSTREL_SCALE)
+#define SSV_RC_HT_INTERVAL 100
+extern const u16 ampdu_max_transmit_length[];
+s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc,
+			   struct fw_rc_retry_params *ar);
+void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],
+			struct ssv_sta_rc_info *rc_sta);
+void ssv6xxx_ht_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
+			       struct ssv_sta_rc_info *rc_sta);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_pm.c b/drivers/net/wireless/ssv6051/smac/ssv_pm.c
new file mode 100644
index 00000000000..fc3be2013f6
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_pm.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200.h>
+#include "dev.h"
+#include "sar.h"
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_pm.h b/drivers/net/wireless/ssv6051/smac/ssv_pm.h
new file mode 100644
index 00000000000..9be260dd904
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_pm.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_PM_H_
+#define _SSV_PM_H_
+#include <linux/version.h>
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc.c b/drivers/net/wireless/ssv6051/smac/ssv_rc.c
new file mode 100644
index 00000000000..796ff01494b
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_rc.c
@@ -0,0 +1,1716 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ssv_ht_rc.h"
+#include "ssv_rc.h"
+#include "ssv_rc_common.h"
+static struct ssv_rc_rate ssv_11bgn_rate_table[] = {
+	[0] = {.rc_flags = RC_FLAG_LEGACY,
+	       .phy_type = WLAN_RC_PHY_CCK,
+	       .rate_kbps = 1000,
+	       .dot11_rate_idx = 0,
+	       .ctrl_rate_idx = 0,
+	       .hw_rate_idx = 0,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[1] = {.rc_flags = RC_FLAG_LEGACY,
+	       .phy_type = WLAN_RC_PHY_CCK,
+	       .rate_kbps = 2000,
+	       .dot11_rate_idx = 1,
+	       .ctrl_rate_idx = 1,
+	       .hw_rate_idx = 1,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[2] = {.rc_flags = RC_FLAG_LEGACY,
+	       .phy_type = WLAN_RC_PHY_CCK,
+	       .rate_kbps = 5500,
+	       .dot11_rate_idx = 2,
+	       .ctrl_rate_idx = 1,
+	       .hw_rate_idx = 2,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[3] = {.rc_flags = RC_FLAG_LEGACY,
+	       .phy_type = WLAN_RC_PHY_CCK,
+	       .rate_kbps = 11000,
+	       .dot11_rate_idx = 3,
+	       .ctrl_rate_idx = 1,
+	       .hw_rate_idx = 3,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[4] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
+	       .phy_type = WLAN_RC_PHY_CCK,
+	       .rate_kbps = 2000,
+	       .dot11_rate_idx = 1,
+	       .ctrl_rate_idx = 4,
+	       .hw_rate_idx = 4,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[5] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
+	       .phy_type = WLAN_RC_PHY_CCK,
+	       .rate_kbps = 5500,
+	       .dot11_rate_idx = 2,
+	       .ctrl_rate_idx = 4,
+	       .hw_rate_idx = 5,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[6] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
+	       .phy_type = WLAN_RC_PHY_CCK,
+	       .rate_kbps = 11000,
+	       .dot11_rate_idx = 3,
+	       .ctrl_rate_idx = 4,
+	       .hw_rate_idx = 6,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[7] = {.rc_flags = RC_FLAG_LEGACY,
+	       .phy_type = WLAN_RC_PHY_OFDM,
+	       .rate_kbps = 6000,
+	       .dot11_rate_idx = 4,
+	       .ctrl_rate_idx = 7,
+	       .hw_rate_idx = 7,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[8] = {.rc_flags = RC_FLAG_LEGACY,
+	       .phy_type = WLAN_RC_PHY_OFDM,
+	       .rate_kbps = 9000,
+	       .dot11_rate_idx = 5,
+	       .ctrl_rate_idx = 7,
+	       .hw_rate_idx = 8,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[9] = {.rc_flags = RC_FLAG_LEGACY,
+	       .phy_type = WLAN_RC_PHY_OFDM,
+	       .rate_kbps = 12000,
+	       .dot11_rate_idx = 6,
+	       .ctrl_rate_idx = 9,
+	       .hw_rate_idx = 9,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[10] = {.rc_flags = RC_FLAG_LEGACY,
+		.phy_type = WLAN_RC_PHY_OFDM,
+		.rate_kbps = 18000,
+		.dot11_rate_idx = 7,
+		.ctrl_rate_idx = 9,
+		.hw_rate_idx = 10,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[11] = {.rc_flags = RC_FLAG_LEGACY,
+		.phy_type = WLAN_RC_PHY_OFDM,
+		.rate_kbps = 24000,
+		.dot11_rate_idx = 8,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 11,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[12] = {.rc_flags = RC_FLAG_LEGACY,
+		.phy_type = WLAN_RC_PHY_OFDM,
+		.rate_kbps = 36000,
+		.dot11_rate_idx = 9,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 12,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[13] = {.rc_flags = RC_FLAG_LEGACY,
+		.phy_type = WLAN_RC_PHY_OFDM,
+		.rate_kbps = 48000,
+		.dot11_rate_idx = 10,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 13,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[14] = {.rc_flags = RC_FLAG_LEGACY,
+		.phy_type = WLAN_RC_PHY_OFDM,
+		.rate_kbps = 54000,
+		.dot11_rate_idx = 11,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 14,
+		.arith_shift = 8,
+		.target_pf = 8},
+	[15] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 6500,
+		.dot11_rate_idx = 0,
+		.ctrl_rate_idx = 7,
+		.hw_rate_idx = 15,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[16] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 13000,
+		.dot11_rate_idx = 1,
+		.ctrl_rate_idx = 9,
+		.hw_rate_idx = 16,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[17] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 19500,
+		.dot11_rate_idx = 2,
+		.ctrl_rate_idx = 9,
+		.hw_rate_idx = 17,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[18] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 26000,
+		.dot11_rate_idx = 3,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 18,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[19] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 39000,
+		.dot11_rate_idx = 4,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 19,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[20] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 52000,
+		.dot11_rate_idx = 5,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 20,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[21] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 58500,
+		.dot11_rate_idx = 6,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 21,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[22] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 65000,
+		.dot11_rate_idx = 7,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 22,
+		.arith_shift = 8,
+		.target_pf = 8},
+	[23] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 7200,
+		.dot11_rate_idx = 0,
+		.ctrl_rate_idx = 7,
+		.hw_rate_idx = 23,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[24] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 14400,
+		.dot11_rate_idx = 1,
+		.ctrl_rate_idx = 9,
+		.hw_rate_idx = 24,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[25] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 21700,
+		.dot11_rate_idx = 2,
+		.ctrl_rate_idx = 9,
+		.hw_rate_idx = 25,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[26] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 28900,
+		.dot11_rate_idx = 3,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 26,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[27] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 43300,
+		.dot11_rate_idx = 4,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 27,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[28] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 57800,
+		.dot11_rate_idx = 5,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 28,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[29] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 65000,
+		.dot11_rate_idx = 6,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 29,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[30] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 72200,
+		.dot11_rate_idx = 7,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 30,
+		.arith_shift = 8,
+		.target_pf = 8},
+	[31] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 6500,
+		.dot11_rate_idx = 0,
+		.ctrl_rate_idx = 7,
+		.hw_rate_idx = 31,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[32] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 13000,
+		.dot11_rate_idx = 1,
+		.ctrl_rate_idx = 9,
+		.hw_rate_idx = 32,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[33] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 19500,
+		.dot11_rate_idx = 2,
+		.ctrl_rate_idx = 9,
+		.hw_rate_idx = 33,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[34] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 26000,
+		.dot11_rate_idx = 3,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 34,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[35] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 39000,
+		.dot11_rate_idx = 4,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 35,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[36] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 52000,
+		.dot11_rate_idx = 5,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 36,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[37] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 58500,
+		.dot11_rate_idx = 6,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 37,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[38] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 65000,
+		.dot11_rate_idx = 7,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 38,
+		.arith_shift = 8,
+		.target_pf = 8},
+};
+
+const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13] = {
+	[RC_TYPE_B_ONLY] = {4, 0, 1, 2, 3},
+	[RC_TYPE_LEGACY_GB] = {12, 0, 1, 2, 7, 8, 3, 9, 10, 11, 12, 13, 14},
+	[RC_TYPE_SGI_20] = {8, 23, 24, 25, 26, 27, 28, 29, 30},
+	[RC_TYPE_LGI_20] = {8, 15, 16, 17, 18, 19, 20, 21, 22},
+	[RC_TYPE_HT_SGI_20] = {8, 23, 24, 25, 26, 27, 28, 29, 30},
+	[RC_TYPE_HT_LGI_20] = {8, 15, 16, 17, 18, 19, 20, 21, 22},
+	[RC_TYPE_HT_GF] = {8, 31, 32, 33, 34, 35, 36, 37, 38},
+};
+
+static u32 ssv6xxx_rate_supported(struct ssv_sta_rc_info *rc_sta, u32 index)
+{
+	return (rc_sta->rc_supp_rates & BIT(index));
+}
+
+static u8 ssv6xxx_rate_lowest_index(struct ssv_sta_rc_info *rc_sta)
+{
+	int i;
+	for (i = 0; i < rc_sta->rc_num_rate; i++)
+		if (ssv6xxx_rate_supported(rc_sta, i))
+			return i;
+	return 0;
+}
+
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+static u8 ssv6xxx_rate_highest_index(struct ssv_sta_rc_info *rc_sta)
+{
+	int i;
+	for (i = rc_sta->rc_num_rate - 1; i >= 0; i--)
+		if (ssv6xxx_rate_supported(rc_sta, i))
+			return i;
+	return 0;
+}
+#endif
+static void rate_control_pid_adjust_rate(struct ssv_sta_rc_info *rc_sta,
+					 struct rc_pid_sta_info *spinfo,
+					 int adj, struct rc_pid_rateinfo *rinfo)
+{
+	int cur_sorted, new_sorted, probe, tmp, n_bitrates;
+	int cur = spinfo->txrate_idx;
+	n_bitrates = rc_sta->rc_num_rate;
+	cur_sorted = rinfo[cur].index;
+	new_sorted = cur_sorted + adj;
+	if (new_sorted < 0)
+		new_sorted = rinfo[0].index;
+	else if (new_sorted >= n_bitrates)
+		new_sorted = rinfo[n_bitrates - 1].index;
+	tmp = new_sorted;
+	if (adj < 0) {
+		for (probe = cur_sorted; probe >= new_sorted; probe--)
+			if (rinfo[probe].diff <= rinfo[cur_sorted].diff &&
+			    ssv6xxx_rate_supported(rc_sta, rinfo[probe].index))
+				tmp = probe;
+	} else {
+		for (probe = new_sorted + 1; probe < n_bitrates; probe++)
+			if (rinfo[probe].diff <= rinfo[new_sorted].diff &&
+			    ssv6xxx_rate_supported(rc_sta, rinfo[probe].index))
+				tmp = probe;
+	}
+	BUG_ON(tmp < 0 || tmp >= n_bitrates);
+	do {
+		if (ssv6xxx_rate_supported(rc_sta, rinfo[tmp].index)) {
+			spinfo->tmp_rate_idx = rinfo[tmp].index;
+			break;
+		}
+		if (adj < 0)
+			tmp--;
+		else
+			tmp++;
+	} while (tmp < n_bitrates && tmp >= 0);
+	spinfo->oldrate = spinfo->txrate_idx;
+	if (spinfo->tmp_rate_idx != spinfo->txrate_idx) {
+		spinfo->monitoring = 1;
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+		pr_debug("Trigger monitor tmp_rate_idx=[%d]\n",
+		       spinfo->tmp_rate_idx);
+#endif
+		spinfo->probe_cnt = MAXPROBES;
+	}
+}
+
+static void rate_control_pid_normalize(struct rc_pid_info *pinfo, int l)
+{
+	int i, norm_offset = RC_PID_NORM_OFFSET;
+	struct rc_pid_rateinfo *r = pinfo->rinfo;
+	if (r[0].diff > norm_offset)
+		r[0].diff -= norm_offset;
+	else if (r[0].diff < -norm_offset)
+		r[0].diff += norm_offset;
+	for (i = 0; i < l - 1; i++)
+		if (r[i + 1].diff > r[i].diff + norm_offset)
+			r[i + 1].diff -= norm_offset;
+		else if (r[i + 1].diff <= r[i].diff)
+			r[i + 1].diff += norm_offset;
+}
+
+#ifdef RATE_CONTROL_DEBUG
+unsigned int txrate_dlr = 0;
+#endif
+static void rate_control_pid_sample(struct ssv_rate_ctrl *ssv_rc,
+				    struct rc_pid_info *pinfo,
+				    struct ssv_sta_rc_info *rc_sta,
+				    struct rc_pid_sta_info *spinfo)
+{
+	struct rc_pid_rateinfo *rinfo = pinfo->rinfo;
+	u8 pf;
+	s32 err_avg;
+	s32 err_prop;
+	s32 err_int;
+	s32 err_der;
+	int adj, i, j, tmp;
+	struct ssv_rc_rate *rc_table;
+	unsigned int dlr;
+	unsigned int perfect_time = 0;
+	unsigned int this_thp, ewma_thp;
+	struct rc_pid_rateinfo *rate;
+	if (!spinfo->monitoring) {
+		if (spinfo->tx_num_xmit == 0)
+			return;
+		spinfo->last_sample = jiffies;
+		pf = spinfo->tx_num_failed * 100 / spinfo->tx_num_xmit;
+		if (pinfo->rinfo[spinfo->txrate_idx].this_attempt > 0) {
+			rate = &pinfo->rinfo[spinfo->txrate_idx];
+			rc_table = &ssv_rc->rc_table[spinfo->txrate_idx];
+			dlr = 100 - rate->this_fail * 100 / rate->this_attempt;
+			perfect_time = rate->perfect_tx_time;
+			if (!perfect_time)
+				perfect_time = 1000000;
+			this_thp = dlr * (1000000 / perfect_time);
+			ewma_thp = rate->throughput;
+			if (ewma_thp == 0)
+				rate->throughput = this_thp;
+			else
+				rate->throughput = (ewma_thp + this_thp) >> 1;
+			rate->attempt += rate->this_attempt;
+			rate->success += rate->this_success;
+			rate->fail += rate->this_fail;
+			spinfo->tx_num_xmit = 0;
+			spinfo->tx_num_failed = 0;
+			rate->this_fail = 0;
+			rate->this_success = 0;
+			rate->this_attempt = 0;
+			if (pinfo->oldrate < 0
+			    || pinfo->oldrate >= rc_sta->rc_num_rate) {
+				WARN_ON(1);
+			}
+			if (spinfo->txrate_idx < 0
+			    || spinfo->txrate_idx >= rc_sta->rc_num_rate) {
+				WARN_ON(1);
+			}
+			if (pinfo->oldrate != spinfo->txrate_idx) {
+				i = rinfo[pinfo->oldrate].index;
+				j = rinfo[spinfo->txrate_idx].index;
+				tmp = (pf - spinfo->last_pf);
+				tmp =
+				    RC_PID_DO_ARITH_RIGHT_SHIFT(tmp,
+								rc_table->arith_shift);
+				rinfo[j].diff = rinfo[i].diff + tmp;
+				pinfo->oldrate = spinfo->txrate_idx;
+			}
+			rate_control_pid_normalize(pinfo, rc_sta->rc_num_rate);
+			err_prop =
+			    (rc_table->target_pf - pf) << rc_table->arith_shift;
+			err_avg = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT;
+			spinfo->err_avg_sc =
+			    spinfo->err_avg_sc - err_avg + err_prop;
+			err_int = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT;
+			err_der = pf - spinfo->last_pf;
+			spinfo->last_pf = pf;
+			spinfo->last_dlr = dlr;
+			spinfo->oldrate = spinfo->txrate_idx;
+			adj =
+			    (err_prop * RC_PID_COEFF_P +
+			     err_int * RC_PID_COEFF_I +
+			     err_der * RC_PID_COEFF_D);
+			adj =
+			    RC_PID_DO_ARITH_RIGHT_SHIFT(adj,
+							rc_table->arith_shift <<
+							1);
+			if (adj) {
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+				if ((spinfo->txrate_idx != 11)
+				    || ((spinfo->txrate_idx == 11)
+					&& (adj < 0)))
+					pr_debug
+					    ("[RC]Probe adjust[%d] dlr[%d%%] this_thp[%d] ewma_thp[%d] index[%d]\n",
+					     adj, dlr, this_thp, ewma_thp,
+					     spinfo->txrate_idx);
+#endif
+				rate_control_pid_adjust_rate(rc_sta, spinfo,
+							     adj, rinfo);
+			}
+		}
+	} else {
+		if ((spinfo->feedback_probes >= MAXPROBES)
+		    || (spinfo->feedback_probes && spinfo->probe_cnt)) {
+			rate = &pinfo->rinfo[spinfo->txrate_idx];
+			spinfo->last_sample = jiffies;
+			if (rate->this_attempt > 0) {
+				dlr =
+				    100 -
+				    rate->this_fail * 100 / rate->this_attempt;
+#ifdef RATE_CONTROL_DEBUG
+#ifdef PROBE
+				txrate_dlr = dlr;
+#endif
+#endif
+				spinfo->last_dlr = dlr;
+				perfect_time = rate->perfect_tx_time;
+				if (!perfect_time)
+					perfect_time = 1000000;
+				this_thp = dlr * (1000000 / perfect_time);
+				ewma_thp = rate->throughput;
+				if (ewma_thp == 0)
+					rate->throughput = this_thp;
+				else
+					rate->throughput =
+					    (ewma_thp + this_thp) >> 1;
+				rate->attempt += rate->this_attempt;
+				rate->success += rate->this_success;
+				rinfo[spinfo->txrate_idx].fail +=
+				    rate->this_fail;
+				rate->this_fail = 0;
+				rate->this_success = 0;
+				rate->this_attempt = 0;
+			} else {
+#ifdef RATE_CONTROL_DEBUG
+#ifdef PROBE
+				txrate_dlr = 0;
+#endif
+#endif
+			}
+			rate = &pinfo->rinfo[spinfo->tmp_rate_idx];
+			if (rate->this_attempt > 0) {
+				dlr =
+				    100 -
+				    ((rate->this_fail * 100) /
+				     rate->this_attempt);
+				{
+					perfect_time = rate->perfect_tx_time;
+					if (!perfect_time)
+						perfect_time = 1000000;
+					if (dlr)
+						this_thp =
+						    dlr * (1000000 /
+							   perfect_time);
+					else
+						this_thp = 0;
+					ewma_thp = rate->throughput;
+					if (ewma_thp == 0)
+						rate->throughput = this_thp;
+					else
+						rate->throughput =
+						    (ewma_thp + this_thp) >> 1;
+					if (rate->throughput >
+					    pinfo->rinfo[spinfo->
+							 txrate_idx].throughput)
+					{
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+						pr_debug
+						    ("[RC]UPDATE probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n",
+						     spinfo->tmp_rate_idx,
+						     rate->throughput, dlr,
+						     spinfo->txrate_idx,
+						     pinfo->
+						     rinfo
+						     [spinfo->txrate_idx].throughput,
+						     txrate_dlr,
+						     spinfo->feedback_probes);
+#endif
+						spinfo->txrate_idx =
+						    spinfo->tmp_rate_idx;
+					} else {
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+						pr_debug
+						    ("[RC]Fail probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n",
+						     spinfo->tmp_rate_idx,
+						     rate->throughput, dlr,
+						     spinfo->txrate_idx,
+						     pinfo->
+						     rinfo
+						     [spinfo->txrate_idx].throughput,
+						     txrate_dlr,
+						     spinfo->feedback_probes);
+#endif
+						;
+					}
+					rate->attempt += rate->this_attempt;
+					rate->success += rate->this_success;
+					rate->fail += rate->this_fail;
+					rate->this_fail = 0;
+					rate->this_success = 0;
+					rate->this_attempt = 0;
+					spinfo->oldrate = spinfo->txrate_idx;
+				}
+			}
+#ifdef RATE_CONTROL_DEBUG
+			else
+				pr_err("Unexpected error\n");
+#endif
+			spinfo->feedback_probes = 0;
+			spinfo->tx_num_xmit = 0;
+			spinfo->tx_num_failed = 0;
+			spinfo->monitoring = 0;
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+			pr_debug("Disable monitor\n");
+#endif
+			spinfo->probe_report_flag = 0;
+			spinfo->probe_wating_times = 0;
+		} else {
+			spinfo->probe_wating_times++;
+#ifdef RATE_CONTROL_DEBUG
+			if (spinfo->probe_wating_times > 3) {
+				pr_debug
+				    ("[RC]@@@@@ PROBE LOSE @@@@@ feedback=[%d] need=[%d] probe_cnt=[%d] wating times[%d]\n",
+				     spinfo->feedback_probes, MAXPROBES,
+				     spinfo->probe_cnt,
+				     spinfo->probe_wating_times);
+				spinfo->feedback_probes = 0;
+				spinfo->tx_num_xmit = 0;
+				spinfo->tx_num_failed = 0;
+				spinfo->monitoring = 0;
+				spinfo->probe_report_flag = 0;
+				spinfo->probe_wating_times = 0;
+			}
+#else
+			if (spinfo->probe_wating_times > 3) {
+				spinfo->feedback_probes = 0;
+				spinfo->tx_num_xmit = 0;
+				spinfo->tx_num_failed = 0;
+				spinfo->monitoring = 0;
+				spinfo->probe_report_flag = 0;
+				spinfo->probe_wating_times = 0;
+			}
+#endif
+		}
+	}
+}
+
+#ifdef RATE_CONTROL_PERCENTAGE_TRACE
+int percentage = 0;
+int percentageCounter = 0;
+#endif
+void ssv6xxx_legacy_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
+				   struct ssv_sta_rc_info *rc_sta)
+{
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	struct cfg_host_event *host_event;
+	struct firmware_rate_control_report_data *report_data;
+	struct rc_pid_info *pinfo;
+	struct rc_pid_sta_info *spinfo;
+	struct rc_pid_rateinfo *pidrate;
+	struct rc_pid_rateinfo *rate;
+	s32 report_data_index = 0;
+	unsigned long period;
+	host_event = (struct cfg_host_event *)skb->data;
+	report_data =
+	    (struct firmware_rate_control_report_data *)&host_event->dat[0];
+	if ((report_data->wsid != (-1))
+	    && sc->sta_info[report_data->wsid].sta == NULL) {
+		dev_warn(sc->dev, "RC report has no valid STA.(%d)\n",
+			 report_data->wsid);
+		return;
+	}
+	pinfo = &rc_sta->pinfo;
+	spinfo = &rc_sta->spinfo;
+	pidrate = rc_sta->pinfo.rinfo;
+	if (host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) {
+		period = msecs_to_jiffies(HT_RC_UPDATE_INTERVAL);
+		if (time_after(jiffies, spinfo->last_sample + period)) {
+			if (rc_sta->rc_num_rate == 12)
+				spinfo->txrate_idx = rc_sta->ht.max_tp_rate + 4;
+			else
+				spinfo->txrate_idx = rc_sta->ht.max_tp_rate;
+#ifdef RATE_CONTROL_DEBUG
+			pr_debug("MPDU rate update time txrate_idx[%d]!!\n",
+			       spinfo->txrate_idx);
+#endif
+			spinfo->last_sample = jiffies;
+		}
+		return;
+	} else if (host_event->h_event == SOC_EVT_RC_MPDU_REPORT) {
+		;
+	} else {
+		dev_warn(sc->dev, "RC report handler got garbage\n");
+		return;
+	}
+	if (report_data->rates[0].data_rate < 7) {
+		if (report_data->rates[0].data_rate > 3) {
+			report_data->rates[0].data_rate -= 3;
+		}
+	}
+	if (ssv_rc->
+	    rc_table[rc_sta->pinfo.rinfo[spinfo->txrate_idx].
+		     rc_index].hw_rate_idx == report_data->rates[0].data_rate) {
+		report_data_index =
+		    rc_sta->pinfo.rinfo[spinfo->txrate_idx].index;
+	} else
+	    if (ssv_rc->rc_table
+		[rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].
+		 rc_index].hw_rate_idx == report_data->rates[0].data_rate) {
+		report_data_index =
+		    rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].index;
+	}
+	if ((report_data_index != spinfo->tmp_rate_idx)
+	    && (report_data_index != spinfo->txrate_idx)) {
+#ifdef RATE_CONTROL_DEBUG
+		dev_dbg
+		    (sc->dev, "Rate control report mismatch report_rate_idx[%d] tmp_rate_idx[%d]rate[%d] txrate_idx[%d]rate[%d]!!\n",
+		     report_data->rates[0].data_rate, spinfo->tmp_rate_idx,
+		     ssv_rc->rc_table[rc_sta->pinfo.
+				      rinfo[spinfo->tmp_rate_idx].rc_index].
+		     hw_rate_idx, spinfo->txrate_idx,
+		     ssv_rc->rc_table[rc_sta->pinfo.
+				      rinfo[spinfo->txrate_idx].rc_index].
+		     hw_rate_idx);
+#endif
+		return;
+	}
+	if (report_data_index == spinfo->txrate_idx) {
+		spinfo->tx_num_xmit += report_data->rates[0].count;
+		spinfo->tx_num_failed +=
+		    (report_data->rates[0].count - report_data->ampdu_ack_len);
+		rate = &pidrate[spinfo->txrate_idx];
+		rate->this_fail +=
+		    (report_data->rates[0].count - report_data->ampdu_ack_len);
+		rate->this_attempt += report_data->rates[0].count;
+		rate->this_success += report_data->ampdu_ack_len;
+	}
+	if (report_data_index != spinfo->txrate_idx
+	    && report_data_index == spinfo->tmp_rate_idx) {
+		spinfo->feedback_probes += report_data->ampdu_len;
+		rate = &pidrate[spinfo->tmp_rate_idx];
+		rate->this_fail +=
+		    (report_data->rates[0].count - report_data->ampdu_ack_len);
+		rate->this_attempt += report_data->rates[0].count;
+		rate->this_success += report_data->ampdu_ack_len;
+	}
+	period = msecs_to_jiffies(RC_PID_INTERVAL);
+	if (time_after(jiffies, spinfo->last_sample + period)) {
+#ifdef RATE_CONTROL_PERCENTAGE_TRACE
+		rate = &pidrate[spinfo->txrate_idx];
+		if (rate->this_success > rate->this_attempt) {
+			dev_dbg(sc->dev, "this_success[%ld] this_attempt[%ld]\n",
+			       rate->this_success, rate->this_attempt);
+		} else {
+			if (percentage == 0)
+				percentage =
+				    (int)((rate->this_success * 100) /
+					  rate->this_attempt);
+			else
+				percentage =
+				    (percentage +
+				     (int)((rate->this_success * 100) /
+					   rate->this_attempt)) / 2;
+			deb_dbg(sc->dev, "Percentage[%d]\n", percentage);
+			if ((percentageCounter % 16) == 1)
+				percentage = 0;
+		}
+#endif
+#ifdef RATE_CONTROL_STUPID_DEBUG
+		if (spinfo->txrate_idx != spinfo->tmp_rate_idx) {
+			rate = &pidrate[spinfo->tmp_rate_idx];
+			if (spinfo->monitoring && ((rate->this_attempt == 0)
+						   || (rate->this_attempt !=
+						       MAXPROBES))) {
+				dev_dbg(sc->dev, "Probe result a[%ld]s[%ld]f[%ld]",
+				       rate->this_attempt, rate->this_success,
+				       rate->this_fail);
+			}
+			rate = &pidrate[spinfo->txrate_idx];
+			dev_dbg(sc->dev, "New a[%ld]s[%ld]f[%ld] \n", rate->this_attempt,
+			       rate->this_success, rate->this_fail);
+		} else {
+			rate = &pidrate[spinfo->txrate_idx];
+			dev_dbg(sc->dev, "New a[%ld]s[%ld]f[%ld] \n", rate->this_attempt,
+			       rate->this_success, rate->this_fail);
+		}
+		dev_dbg(sc->dev, "w[%d]x%03d-f%03d\n", rc_sta->rc_wsid,
+		       spinfo->tx_num_xmit, spinfo->tx_num_failed);
+#endif
+		rate_control_pid_sample(sc->rc, pinfo, rc_sta, spinfo);
+	}
+}
+
+void ssv6xxx_sample_work(struct work_struct *work)
+{
+	struct ssv_softc *sc =
+	    container_of(work, struct ssv_softc, rc_sample_work);
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	struct sk_buff *skb;
+	struct cfg_host_event *host_event;
+	struct ssv_sta_rc_info *rc_sta = NULL;
+	struct firmware_rate_control_report_data *report_data;
+	struct ssv_sta_info *ssv_sta;
+	u8 hw_wsid = 0;
+	sc->rc_sample_sechedule = 1;
+	while (1) {
+		skb = skb_dequeue(&sc->rc_report_queue);
+		if (skb == NULL)
+			break;
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+		{
+			dev_kfree_skb_any(skb);
+			continue;
+		}
+#endif
+		host_event = (struct cfg_host_event *)skb->data;
+		if ((host_event->h_event == SOC_EVT_RC_AMPDU_REPORT)
+		    || (host_event->h_event == SOC_EVT_RC_MPDU_REPORT)) {
+			report_data =
+			    (struct firmware_rate_control_report_data *)
+			    &host_event->dat[0];
+			hw_wsid = report_data->wsid;
+		} else {
+			dev_warn(sc->dev, "rate control sampling got garbage\n");
+			dev_kfree_skb_any(skb);
+			continue;
+		}
+		if (hw_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) {
+#ifdef RATE_CONTROL_DEBUG
+			dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-0!!\n");
+#endif
+			dev_kfree_skb_any(skb);
+			continue;
+		}
+		ssv_sta = &sc->sta_info[hw_wsid];
+		if (ssv_sta->sta == NULL) {
+			dev_err(sc->dev, "Null STA %d for RC report.\n",
+				hw_wsid);
+			rc_sta = NULL;
+		} else {
+			struct ssv_sta_priv_data *ssv_sta_priv =
+			    (struct ssv_sta_priv_data *)ssv_sta->sta->drv_priv;
+			rc_sta = &ssv_rc->sta_rc_info[ssv_sta_priv->rc_idx];
+			if (rc_sta->rc_wsid != hw_wsid) {
+				rc_sta = NULL;
+			}
+		}
+		if (rc_sta == NULL) {
+			dev_err(sc->dev,
+				"[RC]rc_sta is NULL pointer Check-1!!\n");
+			dev_kfree_skb_any(skb);
+			continue;
+		}
+		if (rc_sta == NULL) {
+#ifdef RATE_CONTROL_DEBUG
+			dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-2!!\n");
+#endif
+			dev_kfree_skb_any(skb);
+			continue;
+		}
+		if (rc_sta->is_ht) {
+			ssv6xxx_legacy_report_handler(sc, skb, rc_sta);
+			ssv6xxx_ht_report_handler(sc, skb, rc_sta);
+		} else
+			ssv6xxx_legacy_report_handler(sc, skb, rc_sta);
+		dev_kfree_skb_any(skb);
+	}
+	sc->rc_sample_sechedule = 0;
+}
+
+static void ssv6xxx_tx_status(void *priv,
+			      struct ieee80211_supported_band *sband,
+			      struct ieee80211_sta *sta, void *priv_sta,
+			      struct sk_buff *skb)
+{
+	struct ssv_softc *sc;
+	struct ieee80211_hdr *hdr;
+	__le16 fc;
+	hdr = (struct ieee80211_hdr *)skb->data;
+	fc = hdr->frame_control;
+	if (!priv_sta || !ieee80211_is_data_qos(fc))
+		return;
+	sc = (struct ssv_softc *)priv;
+	if (conf_is_ht(&sc->hw->conf)
+	    && (!(skb->protocol == cpu_to_be16(ETH_P_PAE)))) {
+		if (skb_get_queue_mapping(skb) != IEEE80211_AC_VO)
+			ssv6200_ampdu_tx_update_state(priv, sta, skb);
+	}
+	return;
+}
+
+static void rateControlGetRate(u8 rateIndex, char *pointer)
+{
+	switch (rateIndex) {
+	case 0:
+		sprintf(pointer, "1Mbps");
+		return;
+	case 1:
+	case 4:
+		sprintf(pointer, "2Mbps");
+		return;
+	case 2:
+	case 5:
+		sprintf(pointer, "5.5Mbps");
+		return;
+	case 3:
+	case 6:
+		sprintf(pointer, "11Mbps");
+		return;
+	case 7:
+		sprintf(pointer, "6Mbps");
+		return;
+	case 8:
+		sprintf(pointer, "9Mbps");
+		return;
+	case 9:
+		sprintf(pointer, "12Mbps");
+		return;
+	case 10:
+		sprintf(pointer, "18Mbps");
+		return;
+	case 11:
+		sprintf(pointer, "24Mbps");
+		return;
+	case 12:
+		sprintf(pointer, "36Mbps");
+		return;
+	case 13:
+		sprintf(pointer, "48Mbps");
+		return;
+	case 14:
+		sprintf(pointer, "54Mbps");
+		return;
+	case 15:
+	case 31:
+		sprintf(pointer, "MCS0-l");
+		return;
+	case 16:
+	case 32:
+		sprintf(pointer, "MCS1-l");
+		return;
+	case 17:
+	case 33:
+		sprintf(pointer, "MCS2-l");
+		return;
+	case 18:
+	case 34:
+		sprintf(pointer, "MCS3-l");
+		return;
+	case 19:
+	case 35:
+		sprintf(pointer, "MCS4-l");
+		return;
+	case 20:
+	case 36:
+		sprintf(pointer, "MCS5-l");
+		return;
+	case 21:
+	case 37:
+		sprintf(pointer, "MCS6-l");
+		return;
+	case 22:
+	case 38:
+		sprintf(pointer, "MCS7-l");
+		return;
+	case 23:
+		sprintf(pointer, "MCS0-s");
+		return;
+	case 24:
+		sprintf(pointer, "MCS1-s");
+		return;
+	case 25:
+		sprintf(pointer, "MCS2-s");
+		return;
+	case 26:
+		sprintf(pointer, "MCS3-s");
+		return;
+	case 27:
+		sprintf(pointer, "MCS4-s");
+		return;
+	case 28:
+		sprintf(pointer, "MCS5-s");
+		return;
+	case 29:
+		sprintf(pointer, "MCS6-s");
+		return;
+	case 30:
+		sprintf(pointer, "MCS7-s");
+		return;
+	default:
+		sprintf(pointer, "Unknow");
+		return;
+	};
+}
+
+static void ssv6xxx_get_rate(void *priv, struct ieee80211_sta *sta,
+			     void *priv_sta,
+			     struct ieee80211_tx_rate_control *txrc)
+{
+	struct ssv_softc *sc = priv;
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	struct ssv_sta_rc_info *rc_sta = priv_sta;
+	struct sk_buff *skb = txrc->skb;
+	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+	struct ieee80211_tx_rate *rates = tx_info->control.rates;
+	struct rc_pid_sta_info *spinfo = &rc_sta->spinfo;
+	struct ssv_rc_rate *rc_rate = NULL;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	int rateidx = 99;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(5,2,0)
+	if (rate_control_send_low(sta, priv_sta, txrc)) {
+		int i = 0;
+		int total_rates =
+		    (sizeof(ssv_11bgn_rate_table) /
+		     sizeof(ssv_11bgn_rate_table[0]));
+#if 1
+		if ((txrc->rate_idx_mask & (1 << rates[0].idx)) == 0) {
+			u32 rate_idx = rates[0].idx + 1;
+			u32 rate_idx_mask = txrc->rate_idx_mask >> rate_idx;
+			while (rate_idx_mask && (rate_idx_mask & 1) == 0) {
+				rate_idx_mask >>= 1;
+				rate_idx++;
+			}
+			if (rate_idx_mask)
+				rates[0].idx = rate_idx;
+			else {
+				WARN_ON(rate_idx_mask == 0);
+			}
+		}
+#endif
+		for (i = 0; i < total_rates; i++) {
+			if (rates[0].idx ==
+			    ssv_11bgn_rate_table[i].dot11_rate_idx) {
+				break;
+			}
+		}
+		if (i < total_rates)
+			rc_rate = &ssv_rc->rc_table[i];
+		else {
+			WARN_ON("Failed to find matching low rate.");
+		}
+	}
+#endif
+	if (rc_rate == NULL) {
+		if (conf_is_ht(&sc->hw->conf) &&
+		    (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING))
+			tx_info->flags |= IEEE80211_TX_CTL_LDPC;
+		if (conf_is_ht(&sc->hw->conf) &&
+		    (sta->ht_cap.cap & IEEE80211_HT_CAP_TX_STBC))
+			tx_info->flags |= (1 << IEEE80211_TX_CTL_STBC_SHIFT);
+		if (sc->sc_flags & SC_OP_FIXED_RATE) {
+			rateidx = sc->max_rate_idx;
+		} else {
+			if (rc_sta->rc_valid == false) {
+				rateidx = 0;
+			} else {
+				if ((rc_sta->rc_wsid >=
+				     SSV_RC_MAX_HARDWARE_SUPPORT)
+				    || (rc_sta->rc_wsid < 0)) {
+					ssv_sta_priv =
+					    (struct ssv_sta_priv_data *)
+					    sta->drv_priv;
+					{
+						if ((rc_sta->ht_rc_type >=
+						     RC_TYPE_HT_SGI_20)
+						    &&
+						    (ssv_sta_priv->rx_data_rate
+						     <
+						     SSV62XX_RATE_MCS_INDEX)) {
+							rateidx =
+							    rc_sta->
+							    pinfo.rinfo
+							    [spinfo->txrate_idx].rc_index;
+						} else {
+							rateidx =
+							    ssv_sta_priv->rx_data_rate;
+						}
+					}
+				} else {
+					if (rc_sta->is_ht) {
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+						rateidx =
+						    rc_sta->ht.
+						    groups.rates[MCS_GROUP_RATES
+								 - 1].rc_index;
+#else
+						rateidx =
+						    rc_sta->pinfo.
+						    rinfo
+						    [spinfo->txrate_idx].rc_index;
+#endif
+					} else {
+						{
+							BUG_ON
+							    (spinfo->txrate_idx
+							     >=
+							     rc_sta->rc_num_rate);
+							rateidx =
+							    rc_sta->
+							    pinfo.rinfo
+							    [spinfo->txrate_idx].rc_index;
+						}
+						if (rateidx < 4) {
+							if (rateidx) {
+								if ((sc->sc_flags & SC_OP_SHORT_PREAMBLE)
+								    ||
+								    (txrc->short_preamble))
+								{
+									rateidx
+									    +=
+									    3;
+								}
+							}
+						}
+					}
+				}
+			}
+		}
+		rc_rate = &ssv_rc->rc_table[rateidx];
+		if (spinfo->real_hw_index != rc_rate->hw_rate_idx) {
+			char string[24];
+			rateControlGetRate(rc_rate->hw_rate_idx, string);
+		}
+		spinfo->real_hw_index = rc_rate->hw_rate_idx;
+		rates[0].count = 4;
+		rates[0].idx = rc_rate->dot11_rate_idx;
+		tx_info->control.rts_cts_rate_idx =
+		    ssv_rc->rc_table[rc_rate->ctrl_rate_idx].dot11_rate_idx;
+		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
+			rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
+		if (rc_rate->rc_flags & RC_FLAG_HT) {
+			rates[0].flags |= IEEE80211_TX_RC_MCS;
+			if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
+				rates[0].flags |= IEEE80211_TX_RC_SHORT_GI;
+			if (rc_rate->rc_flags & RC_FLAG_HT_GF)
+				rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD;
+		}
+	}
+	rates[1].count = 0;
+	rates[1].idx = -1;
+	rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx;
+	rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx];
+	rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx;
+}
+
+int pide_frame_duration(size_t len, int rate, int short_preamble, int flags)
+{
+	int dur = 0;
+	if (flags == WLAN_RC_PHY_CCK) {
+		dur = 10;
+		dur += short_preamble ? (72 + 24) : (144 + 48);
+		dur += DIV_ROUND_UP(8 * (len + 4) * 10, rate);
+	} else {
+		dur = 16;
+		dur += 16;
+		dur += 4;
+		dur += 4 * DIV_ROUND_UP((16 + 8 * (len + 4) + 6) * 10,
+					4 * rate);
+	}
+	return dur;
+}
+
+static void ssv62xx_rc_caps(struct ssv_sta_rc_info *rc_sta)
+{
+	struct rc_pid_sta_info *spinfo;
+	struct rc_pid_info *pinfo;
+	struct rc_pid_rateinfo *rinfo;
+	int i;
+	spinfo = &rc_sta->spinfo;
+	pinfo = &rc_sta->pinfo;
+	memset(spinfo, 0, sizeof(struct rc_pid_sta_info));
+	memset(pinfo, 0, sizeof(struct rc_pid_info));
+	rinfo = rc_sta->pinfo.rinfo;
+	for (i = 0; i < rc_sta->rc_num_rate; i++) {
+		rinfo[i].rc_index = ssv6xxx_rc_rate_set[rc_sta->rc_type][i + 1];
+		rinfo[i].diff = i * RC_PID_NORM_OFFSET;
+		rinfo[i].index = (u16) i;
+		rinfo[i].perfect_tx_time =
+		    TDIFS + (TSLOT * 15 >> 1) + pide_frame_duration(1530,
+								    ssv_11bgn_rate_table
+								    [rinfo
+								     [i].rc_index].rate_kbps
+								    / 100, 1,
+								    ssv_11bgn_rate_table
+								    [rinfo
+								     [i].rc_index].phy_type)
+		    + pide_frame_duration(10,
+					  ssv_11bgn_rate_table[rinfo[i].
+							       rc_index].rate_kbps
+					  / 100, 1,
+					  ssv_11bgn_rate_table[rinfo[i].
+							       rc_index].phy_type);
+		pr_debug("[RC]Init perfect_tx_time[%d][%d]\n", i,
+		       rinfo[i].perfect_tx_time);
+		rinfo[i].throughput = 0;
+	}
+	if (rc_sta->is_ht) {
+		if (ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0] == 12)
+			spinfo->txrate_idx = 4;
+		else
+			spinfo->txrate_idx = 0;
+	} else {
+		spinfo->txrate_idx = ssv6xxx_rate_lowest_index(rc_sta);
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+		spinfo->txrate_idx = ssv6xxx_rate_highest_index(rc_sta);
+#endif
+	}
+	spinfo->real_hw_index = 0;
+	spinfo->probe_cnt = MAXPROBES;
+	spinfo->tmp_rate_idx = spinfo->txrate_idx;
+	spinfo->oldrate = spinfo->txrate_idx;
+	spinfo->last_sample = jiffies;
+	spinfo->last_report = jiffies;
+}
+
+static void ssv6xxx_rate_update_rc_type(void *priv,
+					struct ieee80211_supported_band *sband,
+					struct ieee80211_sta *sta,
+					void *priv_sta)
+{
+	struct ssv_softc *sc = priv;
+	struct ssv_hw *sh = sc->sh;
+	struct ssv_sta_rc_info *rc_sta = priv_sta;
+	int i;
+	u32 ht_supp_rates = 0;
+	BUG_ON(rc_sta->rc_valid == false);
+	dev_dbg(sc->dev, "[I] %s(): \n", __FUNCTION__);
+	rc_sta->ht_supp_rates = 0;
+	rc_sta->rc_supp_rates = 0;
+	rc_sta->is_ht = 0;
+#ifndef CONFIG_CH14_SUPPORT_GN_MODE
+	if (sc->cur_channel->hw_value == 14) {
+		dev_dbg(sc->dev, "[RC init ]Channel 14 support\n");
+		if ((sta->supp_rates[sband->band] & (~0xfL)) == 0x0) {
+			dev_dbg(sc->dev, "[RC init ]B only mode\n");
+			rc_sta->rc_type = RC_TYPE_B_ONLY;
+		} else {
+			dev_dbg(sc->dev, "[RC init ]GB mode\n");
+			rc_sta->rc_type = RC_TYPE_LEGACY_GB;
+		}
+	} else
+#endif
+	if (sta->ht_cap.ht_supported == true) {
+		dev_dbg(sc->dev, "[RC init ]HT support wsid\n");
+		for (i = 0; i < SSV_HT_RATE_MAX; i++) {
+			if (sta->ht_cap.mcs.rx_mask[i /
+						    MCS_GROUP_RATES] & (1 << (i
+									      %
+									      MCS_GROUP_RATES)))
+				ht_supp_rates |= BIT(i);
+		}
+		rc_sta->ht_supp_rates = ht_supp_rates;
+		if (sta->ht_cap.cap & IEEE80211_HT_CAP_GRN_FLD) {
+			rc_sta->rc_type = RC_TYPE_HT_GF;
+			rc_sta->ht_rc_type = RC_TYPE_HT_GF;
+		} else if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) {
+			rc_sta->rc_type = RC_TYPE_SGI_20;
+			rc_sta->ht_rc_type = RC_TYPE_HT_SGI_20;
+		} else {
+			rc_sta->rc_type = RC_TYPE_LGI_20;
+			rc_sta->ht_rc_type = RC_TYPE_HT_LGI_20;
+		}
+	} else {
+		if ((sta->supp_rates[sband->band] & (~0xfL)) == 0x0) {
+			rc_sta->rc_type = RC_TYPE_B_ONLY;
+			dev_dbg(sc->dev, "[RC init ]B only mode\n");
+		} else {
+			rc_sta->rc_type = RC_TYPE_LEGACY_GB;
+			dev_dbg(sc->dev, "[RC init ]legacy G mode\n");
+		}
+	}
+#ifdef CONFIG_SSV_DPD
+	if (rc_sta->rc_type == RC_TYPE_B_ONLY) {
+		SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3D3E84FE);
+		SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x1457D79);
+		SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x0);
+	} else {
+		SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3CBE84FE);
+		SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x4507F9);
+		SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x3);
+	}
+#endif
+	if ((rc_sta->rc_type != RC_TYPE_B_ONLY)
+	    && (rc_sta->rc_type != RC_TYPE_LEGACY_GB)) {
+		if ((sta->ht_cap.ht_supported)
+		    && (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX)) {
+			rc_sta->is_ht = 1;
+			ssv62xx_ht_rc_caps(ssv6xxx_rc_rate_set, rc_sta);
+		}
+	}
+	{
+		rc_sta->rc_num_rate =
+		    (u8) ssv6xxx_rc_rate_set[rc_sta->rc_type][0];
+		if ((rc_sta->rc_type == RC_TYPE_HT_GF)
+		    || (rc_sta->rc_type == RC_TYPE_LGI_20)
+		    || (rc_sta->rc_type == RC_TYPE_SGI_20)) {
+			if (rc_sta->rc_num_rate == 12) {
+				rc_sta->rc_supp_rates =
+				    sta->supp_rates[sband->band] & 0xfL;
+				rc_sta->rc_supp_rates |= (ht_supp_rates << 4);
+			} else
+				rc_sta->rc_supp_rates = ht_supp_rates;
+		} else if (rc_sta->rc_type == RC_TYPE_LEGACY_GB)
+			rc_sta->rc_supp_rates = sta->supp_rates[sband->band];
+		else if (rc_sta->rc_type == RC_TYPE_B_ONLY)
+			rc_sta->rc_supp_rates =
+			    sta->supp_rates[sband->band] & 0xfL;
+		ssv62xx_rc_caps(rc_sta);
+	}
+}
+
+static void ssv6xxx_rate_update(void *priv,
+				struct ieee80211_supported_band *sband,
+				struct cfg80211_chan_def *chandef,
+				struct ieee80211_sta *sta, void *priv_sta,
+				u32 changed)
+{
+	pr_debug("%s: changed=%d\n", __FUNCTION__, changed);
+	return;
+}
+
+static void ssv6xxx_rate_init(void *priv,
+			      struct ieee80211_supported_band *sband,
+			      struct cfg80211_chan_def *chandef,
+			      struct ieee80211_sta *sta, void *priv_sta)
+{
+	ssv6xxx_rate_update_rc_type(priv, sband, sta, priv_sta);
+}
+
+static void *ssv6xxx_rate_alloc_sta(void *priv, struct ieee80211_sta *sta,
+				    gfp_t gfp)
+{
+	struct ssv_sta_priv_data *sta_priv =
+	    (struct ssv_sta_priv_data *)sta->drv_priv;
+#ifndef RC_STA_DIRECT_MAP
+	struct ssv_softc *sc = priv;
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	int s;
+	sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	for (s = 0; s < SSV_RC_MAX_STA; s++) {
+		if (ssv_rc->sta_rc_info[s].rc_valid == false) {
+			dev_dbg(sc->dev, "%s(): use index %d\n", __FUNCTION__, s);
+			memset(&ssv_rc->sta_rc_info[s], 0,
+			       sizeof(struct ssv_sta_rc_info));
+			ssv_rc->sta_rc_info[s].rc_valid = true;
+			ssv_rc->sta_rc_info[s].rc_wsid = -1;
+			sta_priv->rc_idx = s;
+			return &ssv_rc->sta_rc_info[s];
+		}
+	}
+	return NULL;
+#else
+	sta_priv->rc_idx = (-1);
+	return sta_priv;
+#endif
+}
+
+static void ssv6xxx_rate_free_sta(void *priv, struct ieee80211_sta *sta,
+				  void *priv_sta)
+{
+	struct ssv_sta_rc_info *rc_sta = priv_sta;
+	rc_sta->rc_valid = false;
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
+static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw)
+#else
+static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw,
+				struct dentry *debugfsdir)
+#endif
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_rate_ctrl *ssv_rc;
+	sc->rc = kzalloc(sizeof(struct ssv_rate_ctrl), GFP_KERNEL);
+	if (!sc->rc) {
+		pr_err("%s(): Unable to allocate RC structure !\n",
+		       __FUNCTION__);
+		return NULL;
+	}
+	memset(sc->rc, 0, sizeof(struct ssv_rate_ctrl));
+	ssv_rc = (struct ssv_rate_ctrl *)sc->rc;
+	ssv_rc->rc_table = ssv_11bgn_rate_table;
+	skb_queue_head_init(&sc->rc_report_queue);
+	INIT_WORK(&sc->rc_sample_work, ssv6xxx_sample_work);
+	sc->rc_sample_workqueue = create_workqueue("ssv6xxx_rc_sample");
+	sc->rc_sample_sechedule = 0;
+	return hw->priv;
+}
+
+static void ssv6xxx_rate_free(void *priv)
+{
+	struct ssv_softc *sc = priv;
+	if (sc->rc) {
+		kfree(sc->rc);
+		sc->rc = NULL;
+	}
+	sc->rc_sample_sechedule = 0;
+	cancel_work_sync(&sc->rc_sample_work);
+	flush_workqueue(sc->rc_sample_workqueue);
+	destroy_workqueue(sc->rc_sample_workqueue);
+}
+
+static struct rate_control_ops ssv_rate_ops = {
+	.name = "ssv6xxx_rate_control",
+	.tx_status = ssv6xxx_tx_status,
+	.get_rate = ssv6xxx_get_rate,
+	.rate_init = ssv6xxx_rate_init,
+	.rate_update = ssv6xxx_rate_update,
+	.alloc = ssv6xxx_rate_alloc,
+	.free = ssv6xxx_rate_free,
+	.alloc_sta = ssv6xxx_rate_alloc_sta,
+	.free_sta = ssv6xxx_rate_free_sta,
+};
+
+void ssv6xxx_rc_mac8011_rate_idx(struct ssv_softc *sc,
+				 int hw_rate_idx,
+				 struct ieee80211_rx_status *rxs)
+{
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	struct ssv_rc_rate *rc_rate;
+	BUG_ON(hw_rate_idx >= RATE_TABLE_SIZE && hw_rate_idx < 0);
+	rc_rate = &ssv_rc->rc_table[hw_rate_idx];
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)
+	if (rc_rate->rc_flags & RC_FLAG_HT) {
+		rxs->flag |= RC_FLAG_HT;
+		if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
+			rxs->flag |= RX_ENC_FLAG_SHORT_GI;
+	} else {
+		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
+			rxs->flag |= RX_ENC_FLAG_SHORTPRE;
+	}
+#else
+	if (rc_rate->rc_flags & RC_FLAG_HT) {
+		rxs->flag |= RC_FLAG_HT;
+		if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
+			rxs->flag |= RX_FLAG_SHORT_GI;
+	} else {
+		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
+			rxs->flag |= RX_FLAG_SHORTPRE;
+	}
+#endif
+	rxs->rate_idx = rc_rate->dot11_rate_idx;
+}
+
+void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,
+			    struct ieee80211_tx_info *info,
+			    struct ssv_rate_info *sr)
+{
+	struct ieee80211_tx_rate *tx_rate;
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	tx_rate = &info->control.rates[0];
+	sr->d_flags =
+	    (ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].phy_type ==
+	     WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G : 0;
+	sr->d_flags |=
+	    (ssv_rc->
+	     rc_table[tx_rate[SSV_DRATE_IDX].
+		      count].rc_flags & RC_FLAG_SHORT_PREAMBLE) ?
+	    IEEE80211_RATE_SHORT_PREAMBLE : 0;
+	sr->c_flags =
+	    (ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].phy_type ==
+	     WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G : 0;
+	sr->c_flags |=
+	    (ssv_rc->
+	     rc_table[tx_rate[SSV_CRATE_IDX].
+		      count].rc_flags & RC_FLAG_SHORT_PREAMBLE) ?
+	    IEEE80211_RATE_SHORT_PREAMBLE : 0;
+	sr->drate_kbps =
+	    ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].rate_kbps;
+	sr->drate_hw_idx = tx_rate[SSV_DRATE_IDX].count;
+	sr->crate_kbps =
+	    ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].rate_kbps;
+	sr->crate_hw_idx = tx_rate[SSV_CRATE_IDX].count;
+}
+
+u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc,
+				   u32 do_rts_cts)
+{
+	int ret = 0;
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+	struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+	struct ieee80211_sta *sta = skb_info->sta;
+	struct ieee80211_tx_rate *rates = &tx_info->control.rates[0];
+	struct ssv_rc_rate *rc_rate = NULL;
+	u8 rateidx = 0;
+	struct ssv_sta_rc_info *rc_sta = NULL;
+	struct rc_pid_sta_info *spinfo;
+	struct ssv_sta_priv_data *sta_priv = NULL;
+	unsigned long period = 0;
+	if (sc->sc_flags & SC_OP_FIXED_RATE)
+		return ret;
+	if (sta == NULL)
+		return ret;
+	sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	if (sta_priv == NULL) {
+#ifdef RATE_CONTROL_DEBUG
+		dev_dbg(rc->dev, "%s sta_priv == NULL \n\r", __FUNCTION__);
+#endif
+		return ret;
+	}
+	if ((sta_priv->rc_idx < 0) || (sta_priv->rc_idx >= SSV_RC_MAX_STA)) {
+#ifdef RATE_CONTROL_DEBUG
+		dev_dbg(sc->dev, "%s rc_idx %x illegal \n\r", __FUNCTION__,
+		       sta_priv->rc_idx);
+#endif
+		return ret;
+	}
+	rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx];
+	if (rc_sta->rc_valid == false) {
+#ifdef RATE_CONTROL_DEBUG
+		dev_dbg(sc->dev, "%s rc_valid false \n\r", __FUNCTION__);
+#endif
+		return ret;
+	}
+	spinfo = &rc_sta->spinfo;
+	period = msecs_to_jiffies(RC_PID_REPORT_INTERVAL);
+	if (time_after(jiffies, spinfo->last_report + period)) {
+		ret |= RC_FIRMWARE_REPORT_FLAG;
+		spinfo->last_report = jiffies;
+	}
+	{
+		if (spinfo->monitoring) {
+			if (spinfo->probe_report_flag == 0) {
+				ret |= RC_FIRMWARE_REPORT_FLAG;
+				spinfo->last_report = jiffies;
+				spinfo->probe_report_flag = 1;
+				rateidx = spinfo->real_hw_index;
+			} else if (spinfo->probe_cnt > 0
+				   && spinfo->probe_report_flag) {
+				rateidx =
+				    rc_sta->pinfo.rinfo[spinfo->
+							tmp_rate_idx].rc_index;
+				spinfo->probe_cnt--;
+				if (spinfo->probe_cnt == 0) {
+					ret |= RC_FIRMWARE_REPORT_FLAG;
+					spinfo->last_report = jiffies;
+				}
+			} else
+				rateidx = spinfo->real_hw_index;
+		} else
+			rateidx = spinfo->real_hw_index;
+	}
+	if (rateidx >= RATE_TABLE_SIZE) {
+		dev_err(sc->dev, "rateidx over range\n");
+		return 0;
+	}
+	rc_rate = &ssv_rc->rc_table[rateidx];
+#ifdef RATE_CONTROL_STUPID_DEBUG
+	if (spinfo->monitoring && (spinfo->probe_cnt)) {
+		char string[24];
+		rateControlGetRate(rc_rate->hw_rate_idx, string);
+		dev_dbg(sc->dev, "[RC]Probe rate[%s]\n", string);
+	}
+#endif
+	if (rc_rate == NULL)
+		return ret;
+	if (rc_rate->hw_rate_idx != rates[SSV_DRATE_IDX].count) {
+		rates[0].flags = 0;
+		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
+			rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
+		if (rc_rate->rc_flags & RC_FLAG_HT) {
+			rates[0].flags |= IEEE80211_TX_RC_MCS;
+			if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
+				rates[0].flags |= IEEE80211_TX_RC_SHORT_GI;
+			if (rc_rate->rc_flags & RC_FLAG_HT_GF)
+				rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD;
+		}
+		rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx;
+		if (do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) {
+			rates[SSV_CRATE_IDX].count = 0;
+		} else {
+			rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx];
+			rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx;
+		}
+		ret |= 0x1;
+	}
+	return ret;
+}
+
+void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx)
+{
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	struct ssv_sta_rc_info *rc_sta;
+	u32 rc_hw_reg[] = { ADR_MTX_MIB_WSID0, ADR_MTX_MIB_WSID1 };
+	BUG_ON(rc_idx >= SSV_RC_MAX_STA);
+	rc_sta = &ssv_rc->sta_rc_info[rc_idx];
+	if (hwidx >= 0 && hwidx < SSV_NUM_HW_STA) {
+		rc_sta->rc_wsid = hwidx;
+		dev_dbg(sc->dev, "rc_wsid[%d] rc_idx[%d]\n", rc_sta[rc_idx].rc_wsid,
+		       rc_idx);
+		SMAC_REG_WRITE(sc->sh, rc_hw_reg[hwidx], 0x40000000);
+	} else {
+		rc_sta->rc_wsid = -1;
+	}
+}
+
+#define UPDATE_PHY_INFO_ACK_RATE(_phy_info,_ack_rate_idx) ( _phy_info = (_phy_info&0xfffffc0f)|(_ack_rate_idx<<4))
+int ssv6xxx_rc_update_bmode_ctrl_rate(struct ssv_softc *sc, int rate_tbl_idx,
+				      int ctrl_rate_idx)
+{
+	u32 temp32;
+	struct ssv_hw *sh = sc->sh;
+	u32 addr;
+	addr = sh->hw_pinfo + rate_tbl_idx * 4;
+	ssv_11bgn_rate_table[rate_tbl_idx].ctrl_rate_idx = ctrl_rate_idx;
+	SMAC_REG_READ(sh, addr, &temp32);
+	UPDATE_PHY_INFO_ACK_RATE(temp32, ctrl_rate_idx);
+	SMAC_REG_WRITE(sh, addr, temp32);
+	SMAC_REG_CONFIRM(sh, addr, temp32);
+	return 0;
+}
+
+void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates)
+{
+	int i;
+	int rate_idx, pre_rate_idx = 0;
+	for (i = 0; i < 4; i++) {
+		if (((basic_rates >> i) & 0x01)) {
+			rate_idx = i;
+			pre_rate_idx = i;
+		} else
+			rate_idx = pre_rate_idx;
+		ssv6xxx_rc_update_bmode_ctrl_rate(sc, i, rate_idx);
+		if (i)
+			ssv6xxx_rc_update_bmode_ctrl_rate(sc, i + 3, rate_idx);
+	}
+}
+
+int ssv6xxx_rate_control_register(void)
+{
+	return ieee80211_rate_control_register(&ssv_rate_ops);
+}
+
+void ssv6xxx_rate_control_unregister(void)
+{
+	ieee80211_rate_control_unregister(&ssv_rate_ops);
+}
+
+void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb,
+				u32 rate_index)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ieee80211_sta *sta;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
+	if (sta == NULL) {
+		return;
+	}
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	ssv_sta_priv->rx_data_rate = rate_index;
+}
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc.h b/drivers/net/wireless/ssv6051/smac/ssv_rc.h
new file mode 100644
index 00000000000..911c182897f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_rc.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_RC_H_
+#define _SSV_RC_H_
+#include "ssv_rc_common.h"
+#define RC_PID_REPORT_INTERVAL 40
+#define RC_PID_INTERVAL 125
+#define RC_PID_DO_ARITH_RIGHT_SHIFT(x,y) \
+ ((x) < 0 ? -((-(x)) >> (y)) : (x) >> (y))
+#define RC_PID_NORM_OFFSET 3
+#define RC_PID_SMOOTHING_SHIFT 1
+#define RC_PID_SMOOTHING (1 << RC_PID_SMOOTHING_SHIFT)
+#define RC_PID_COEFF_P 15
+#define RC_PID_COEFF_I 15
+#define RC_PID_COEFF_D 5
+#define MAXPROBES 3
+#define SSV_DRATE_IDX (2)
+#define SSV_CRATE_IDX (3)
+
+struct ssv_softc;
+struct ssv_rc_rate *ssv6xxx_rc_get_rate(int rc_index);
+void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,
+			    struct ieee80211_tx_info *info,
+			    struct ssv_rate_info *sr);
+u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc,
+				   u32 do_rts_cts);
+void ssv6xxx_rc_mac8011_rate_idx(struct ssv_softc *sc, int hw_rate_idx,
+				 struct ieee80211_rx_status *rxs);
+void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx);
+void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates);
+int ssv6xxx_rate_control_register(void);
+void ssv6xxx_rate_control_unregister(void);
+void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb,
+				u32 rate_index);
+int pide_frame_duration(size_t len, int rate, int short_preamble, int flags);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h b/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
new file mode 100644
index 00000000000..13f3fdd8072
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_RC_COM_H_
+#define _SSV_RC_COM_H_
+#define SSV_RC_MAX_STA 8
+#define MCS_GROUP_RATES 8
+#define SSV_HT_RATE_MAX 8
+#define TDIFS 34
+#define TSLOT 9
+#define SSV_RC_MAX_HARDWARE_SUPPORT 2
+#define RC_FIRMWARE_REPORT_FLAG 0x80
+#define RC_FLAG_INVALID 0x00000001
+#define RC_FLAG_LEGACY 0x00000002
+#define RC_FLAG_HT 0x00000004
+#define RC_FLAG_HT_SGI 0x00000008
+#define RC_FLAG_HT_GF 0x00000010
+#define RC_FLAG_SHORT_PREAMBLE 0x00000020
+enum ssv6xxx_rc_phy_type {
+	WLAN_RC_PHY_CCK,
+	WLAN_RC_PHY_OFDM,
+	WLAN_RC_PHY_HT_20_SS_LGI,
+	WLAN_RC_PHY_HT_20_SS_SGI,
+	WLAN_RC_PHY_HT_20_SS_GF,
+};
+#define RATE_TABLE_SIZE 39
+#define RC_STA_VALID 0x00000001
+#define RC_STA_CAP_HT 0x00000002
+#define RC_STA_CAP_GF 0x00000004
+#define RC_STA_CAP_SGI_20 0x00000008
+#define RC_STA_CAP_SHORT_PREAMBLE 0x00000010
+#define SSV62XX_G_RATE_INDEX 7
+#define SSV62XX_RATE_MCS_INDEX 15
+#define SSV62XX_RATE_MCS_LGI_INDEX 15
+#define SSV62XX_RATE_MCS_SGI_INDEX 23
+#define SSV62XX_RATE_MCS_GREENFIELD_INDEX 31
+enum ssv_rc_rate_type {
+	RC_TYPE_B_ONLY = 0,
+	RC_TYPE_LEGACY_GB,
+	RC_TYPE_SGI_20,
+	RC_TYPE_LGI_20,
+	RC_TYPE_HT_SGI_20,
+	RC_TYPE_HT_LGI_20,
+	RC_TYPE_HT_GF,
+	RC_TYPE_MAX,
+};
+struct ssv_rate_info {
+	int crate_kbps;
+	int crate_hw_idx;
+	int drate_kbps;
+	int drate_hw_idx;
+	u32 d_flags;
+	u32 c_flags;
+};
+struct ssv_rc_rate {
+	u32 rc_flags;
+	u16 phy_type;
+	u32 rate_kbps;
+	u8 dot11_rate_idx;
+	u8 ctrl_rate_idx;
+	u8 hw_rate_idx;
+	u8 arith_shift;
+	u8 target_pf;
+};
+struct rc_pid_sta_info {
+	unsigned long last_sample;
+	unsigned long last_report;
+	u16 tx_num_failed;
+	u16 tx_num_xmit;
+	u8 probe_report_flag;
+	u8 probe_wating_times;
+	u8 real_hw_index;
+	int txrate_idx;
+	u8 last_pf;
+	s32 err_avg_sc;
+	int last_dlr;
+	u8 feedback_probes;
+	u8 monitoring;
+	u8 oldrate;
+	u8 tmp_rate_idx;
+	u8 probe_cnt;
+};
+struct rc_pid_rateinfo {
+	u16 rc_index;
+	u16 index;
+	s32 diff;
+	u16 perfect_tx_time;
+	u32 throughput;
+	unsigned long this_attempt;
+	unsigned long this_success;
+	unsigned long this_fail;
+	u64 attempt;
+	u64 success;
+	u64 fail;
+};
+struct rc_pid_info {
+	unsigned int target;
+	int oldrate;
+	struct rc_pid_rateinfo rinfo[12];
+};
+struct mcs_group {
+	unsigned int duration[MCS_GROUP_RATES];
+};
+struct minstrel_rate_stats {
+	u16 rc_index;
+	unsigned int attempts, last_attempts;
+	unsigned int success, last_success;
+	u64 att_hist, succ_hist;
+	unsigned int cur_tp;
+	unsigned int cur_prob, probability;
+	unsigned int retry_count;
+	unsigned int retry_count_rtscts;
+	u8 sample_skipped;
+};
+struct minstrel_mcs_group_data {
+	u8 index;
+	u8 column;
+	unsigned int max_tp_rate;
+	unsigned int max_tp_rate2;
+	unsigned int max_prob_rate;
+	struct minstrel_rate_stats rates[MCS_GROUP_RATES];
+};
+struct ssv62xx_ht {
+	unsigned int ampdu_len;
+	unsigned int ampdu_packets;
+	unsigned int avg_ampdu_len;
+	unsigned int max_tp_rate;
+	unsigned int max_tp_rate2;
+	unsigned int max_prob_rate;
+	int first_try_count;
+	int second_try_count;
+	int other_try_count;
+	unsigned long stats_update;
+	unsigned int overhead;
+	unsigned int overhead_rtscts;
+	unsigned int total_packets;
+	unsigned int sample_packets;
+	u8 sample_wait;
+	u8 sample_tries;
+	u8 sample_count;
+	u8 sample_slow;
+	struct minstrel_mcs_group_data groups;
+};
+struct ssv_sta_rc_info {
+	u8 rc_valid;
+	u8 rc_type;
+	u8 rc_num_rate;
+	s8 rc_wsid;
+	u8 ht_rc_type;
+	u8 is_ht;
+	u32 rc_supp_rates;
+	u32 ht_supp_rates;
+	struct rc_pid_info pinfo;
+	struct rc_pid_sta_info spinfo;
+	struct ssv62xx_ht ht;
+};
+struct ssv_rate_ctrl {
+	struct ssv_rc_rate *rc_table;
+	struct ssv_sta_rc_info sta_rc_info[SSV_RC_MAX_STA];
+};
+#define HT_RC_UPDATE_INTERVAL 1000
+#endif
diff --git a/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c b/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
new file mode 100644
index 00000000000..10a9a77081d
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+#include <asm/io.h>
+#include <linux/printk.h>
+#include <linux/err.h>
+
+static int g_wifidev_registered = 0;
+extern int ssvdevice_init(void);
+extern void ssvdevice_exit(void);
+extern int ssv6xxx_get_dev_status(void);
+
+static __init int ssv_init_module(void)
+{
+	int ret = 0;
+	int time = 5;
+
+	msleep(120);
+
+	g_wifidev_registered = 1;
+	ret = ssvdevice_init();
+
+	while(time-- > 0){
+		msleep(500);
+		if(ssv6xxx_get_dev_status() == 1)
+			break;
+		pr_info("%s : Retry to carddetect\n",__func__);
+	}
+
+	return ret;
+
+}
+static __exit void ssv_exit_module(void)
+{
+
+	if (g_wifidev_registered)
+    {
+        ssvdevice_exit();
+        msleep(50);
+        g_wifidev_registered = 0;
+    }
+
+    return;
+
+}
+
+module_init(ssv_init_module);
+module_exit(ssv_exit_module);
+
+MODULE_AUTHOR("iComm Semiconductor Co., Ltd");
+MODULE_FIRMWARE("ssv*-sw.bin");
+MODULE_FIRMWARE("ssv*-wifi.cfg");
+MODULE_DESCRIPTION("Shared library for SSV wireless LAN cards.");
+MODULE_LICENSE("Dual BSD/GPL");
+
diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
new file mode 100644
index 00000000000..503df1ea6dc
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
@@ -0,0 +1,1765 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/export.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+#include <ssv6200_reg.h>
+#include <ssv6200.h>
+#include <hci/hctrl.h>
+#include <smac/dev.h>
+#include "ssv_cmd.h"
+#include <ssv_version.h>
+#include <ssv6200_configuration.h>
+#define SSV_CMD_PRINTF()
+struct ssv6xxx_dev_table {
+	u32 address;
+	u32 val;
+};
+struct ssv6xxx_debug {
+	struct device *dev;
+	struct platform_device *pdev;
+	struct ssv6xxx_hwif_ops *ifops;
+};
+static struct ssv6xxx_debug *ssv6xxx_debug_ifops;
+static char sg_cmd_buffer[CLI_BUFFER_SIZE + 1];
+static char *sg_argv[CLI_ARG_SIZE];
+static u32 sg_argc;
+extern char *ssv6xxx_result_buf;
+#if defined (CONFIG_ARM64) || defined (__x86_64__)
+u64 ssv6xxx_ifdebug_info[3] = { 0, 0, 0 };
+#else
+u32 ssv6xxx_ifdebug_info[3] = { 0, 0, 0 };
+#endif
+EXPORT_SYMBOL(ssv6xxx_ifdebug_info);
+struct sk_buff *ssvdevice_skb_alloc(s32 len)
+{
+	struct sk_buff *skb;
+	skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL);
+	if (skb != NULL) {
+		skb_put(skb, 0x20);
+		skb_pull(skb, 0x20);
+	}
+	return skb;
+}
+
+void ssvdevice_skb_free(struct sk_buff *skb)
+{
+	dev_kfree_skb_any(skb);
+}
+
+static int ssv_cmd_help(int argc, char *argv[])
+{
+	extern struct ssv_cmd_table cmd_table[];
+	struct ssv_cmd_table *sc_tbl;
+	char tmpbf[161];
+	int total_cmd = 0;
+	{
+		sprintf(ssv6xxx_result_buf, "Usage:\n");
+		for (sc_tbl = &cmd_table[3]; sc_tbl->cmd; sc_tbl++) {
+			sprintf(tmpbf, "%-20s\t\t%s\n", sc_tbl->cmd,
+				sc_tbl->usage);
+			strcat(ssv6xxx_result_buf, tmpbf);
+			total_cmd++;
+		}
+		sprintf(tmpbf,
+			"Total CMDs: %d\n\nType cli help [CMD] for more detail command.\n\n",
+			total_cmd);
+		strcat(ssv6xxx_result_buf, tmpbf);
+	}
+	return 0;
+}
+
+static int ssv_cmd_reg(int argc, char *argv[])
+{
+	u32 addr, value, count;
+	char tmpbf[64], *endp;
+	int s;
+	if (argc == 4 && strcmp(argv[1], "w") == 0) {
+		addr = simple_strtoul(argv[2], &endp, 16);
+		value = simple_strtoul(argv[3], &endp, 16);
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, addr, value)) ;
+		sprintf(ssv6xxx_result_buf, " => write [0x%08x]: 0x%08x\n",
+			addr, value);
+		return 0;
+	} else if ((argc == 4 || argc == 3) && strcmp(argv[1], "r") == 0) {
+		count = (argc == 3) ? 1 : simple_strtoul(argv[3], &endp, 10);
+		addr = simple_strtoul(argv[2], &endp, 16);
+		sprintf(ssv6xxx_result_buf, "ADDRESS: 0x%08x\n", addr);
+		for (s = 0; s < count; s++, addr += 4) {
+			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+			sprintf(tmpbf, "%08x ", value);
+			strcat(ssv6xxx_result_buf, tmpbf);
+			if (((s + 1) & 0x07) == 0)
+				strcat(ssv6xxx_result_buf, "\n");
+		}
+		strcat(ssv6xxx_result_buf, "\n");
+		return 0;
+	} else {
+		sprintf(tmpbf, "reg [r|w] [address] [value|word-count]\n\n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		return 0;
+	}
+	return -1;
+}
+
+struct ssv6xxx_cfg ssv_cfg;
+EXPORT_SYMBOL(ssv_cfg);
+static int __string2u32(u8 * u8str, void *val, u32 arg)
+{
+	char *endp;
+	int base = 10;
+	if (u8str[0] == '0' && ((u8str[1] == 'x') || (u8str[1] == 'X')))
+		base = 16;
+	*(u32 *) val = simple_strtoul(u8str, &endp, base);
+	return 0;
+}
+
+static int __string2flag32(u8 * flag_str, void *flag, u32 arg)
+{
+	u32 *val = (u32 *) flag;
+	if (arg >= (sizeof(u32) << 3))
+		return -1;
+	if (strcmp(flag_str, "on") == 0) {
+		*val |= (1 << arg);
+		return 0;
+	}
+	if (strcmp(flag_str, "off") == 0) {
+		*val &= ~(1 << arg);
+		return 0;
+	}
+	return -1;
+}
+
+static int __string2mac(u8 * mac_str, void *val, u32 arg)
+{
+	int s, macaddr[6];
+	u8 *mac = (u8 *) val;
+	s = sscanf(mac_str, "%02x:%02x:%02x:%02x:%02x:%02x",
+		   &macaddr[0], &macaddr[1], &macaddr[2],
+		   &macaddr[3], &macaddr[4], &macaddr[5]);
+	if (s != 6)
+		return -1;
+	mac[0] = (u8) macaddr[0], mac[1] = (u8) macaddr[1];
+	mac[2] = (u8) macaddr[2], mac[3] = (u8) macaddr[3];
+	mac[4] = (u8) macaddr[4], mac[5] = (u8) macaddr[5];
+	return 0;
+}
+
+static int __string2str(u8 * path, void *val, u32 arg)
+{
+	u8 *temp = (u8 *) val;
+	sprintf(temp, "%s", path);
+	return 0;
+}
+
+static int __string2configuration(u8 * mac_str, void *val, u32 arg)
+{
+	unsigned int address, value;
+	int i;
+	i = sscanf(mac_str, "%08x:%08x", &address, &value);
+	if (i != 2)
+		return -1;
+	for (i = 0; i < EXTERNEL_CONFIG_SUPPORT; i++) {
+		if (ssv_cfg.configuration[i][0] == 0x0) {
+			ssv_cfg.configuration[i][0] = address;
+			ssv_cfg.configuration[i][1] = value;
+			return 0;
+		}
+	}
+	return 0;
+}
+
+struct ssv6xxx_cfg_cmd_table cfg_cmds[] = {
+	{"hw_mac", (void *)&ssv_cfg.maddr[0][0], 0, __string2mac},
+	{"hw_mac_2", (void *)&ssv_cfg.maddr[1][0], 0, __string2mac},
+	{"def_chan", (void *)&ssv_cfg.def_chan, 0, __string2u32},
+	{"hw_cap_ht", (void *)&ssv_cfg.hw_caps, 0, __string2flag32},
+	{"hw_cap_gf", (void *)&ssv_cfg.hw_caps, 1, __string2flag32},
+	{"hw_cap_2ghz", (void *)&ssv_cfg.hw_caps, 2, __string2flag32},
+	{"hw_cap_5ghz", (void *)&ssv_cfg.hw_caps, 3, __string2flag32},
+	{"hw_cap_security", (void *)&ssv_cfg.hw_caps, 4, __string2flag32},
+	{"hw_cap_sgi_20", (void *)&ssv_cfg.hw_caps, 5, __string2flag32},
+	{"hw_cap_sgi_40", (void *)&ssv_cfg.hw_caps, 6, __string2flag32},
+	{"hw_cap_ap", (void *)&ssv_cfg.hw_caps, 7, __string2flag32},
+	{"hw_cap_p2p", (void *)&ssv_cfg.hw_caps, 8, __string2flag32},
+	{"hw_cap_ampdu_rx", (void *)&ssv_cfg.hw_caps, 9, __string2flag32},
+	{"hw_cap_ampdu_tx", (void *)&ssv_cfg.hw_caps, 10, __string2flag32},
+	{"hw_cap_tdls", (void *)&ssv_cfg.hw_caps, 11, __string2flag32},
+	{"use_wpa2_only", (void *)&ssv_cfg.use_wpa2_only, 0, __string2u32},
+	{"wifi_tx_gain_level_gn", (void *)&ssv_cfg.wifi_tx_gain_level_gn, 0,
+	 __string2u32},
+	{"wifi_tx_gain_level_b", (void *)&ssv_cfg.wifi_tx_gain_level_b, 0,
+	 __string2u32},
+	{"rssi_ctl", (void *)&ssv_cfg.rssi_ctl, 0, __string2u32},
+	{"xtal_clock", (void *)&ssv_cfg.crystal_type, 0, __string2u32},
+	{"volt_regulator", (void *)&ssv_cfg.volt_regulator, 0, __string2u32},
+	{"force_chip_identity", (void *)&ssv_cfg.force_chip_identity, 0,
+	 __string2u32},
+	{"firmware_path", (void *)&ssv_cfg.firmware_path[0], 0, __string2str},
+	{"flash_bin_path", (void *)&ssv_cfg.flash_bin_path[0], 0, __string2str},
+	{"mac_address_path", (void *)&ssv_cfg.mac_address_path[0], 0,
+	 __string2str},
+	{"mac_output_path", (void *)&ssv_cfg.mac_output_path[0], 0,
+	 __string2str},
+	{"ignore_efuse_mac", (void *)&ssv_cfg.ignore_efuse_mac, 0,
+	 __string2u32},
+	{"mac_address_mode", (void *)&ssv_cfg.mac_address_mode, 0,
+	 __string2u32},
+	{"sr_bhvr", (void *)&ssv_cfg.sr_bhvr, 0, __string2u32},
+	{"register", NULL, 0, __string2configuration},
+	{NULL, NULL, 0, NULL},
+};
+
+EXPORT_SYMBOL(cfg_cmds);
+static int ssv_cmd_cfg(int argc, char *argv[])
+{
+	char temp_buf[64];
+	int s;
+	if (argc == 2 && strcmp(argv[1], "reset") == 0) {
+		memset(&ssv_cfg, 0, sizeof(ssv_cfg));
+		return 0;
+	} else if (argc == 2 && strcmp(argv[1], "show") == 0) {
+		strcpy(ssv6xxx_result_buf, ">> ssv6xxx config:\n");
+		sprintf(temp_buf, "    hw_caps = 0x%08x\n", ssv_cfg.hw_caps);
+		strcat(ssv6xxx_result_buf, temp_buf);
+		sprintf(temp_buf, "    def_chan = %d\n", ssv_cfg.def_chan);
+		strcat(ssv6xxx_result_buf, temp_buf);
+		sprintf(temp_buf, "    wifi_tx_gain_level_gn = %d\n",
+			ssv_cfg.wifi_tx_gain_level_gn);
+		strcat(ssv6xxx_result_buf, temp_buf);
+		sprintf(temp_buf, "    wifi_tx_gain_level_b = %d\n",
+			ssv_cfg.wifi_tx_gain_level_b);
+		strcat(ssv6xxx_result_buf, temp_buf);
+		sprintf(temp_buf, "    rssi_ctl = %d\n", ssv_cfg.rssi_ctl);
+		strcat(ssv6xxx_result_buf, temp_buf);
+		sprintf(temp_buf, "    sr_bhvr = %d\n", ssv_cfg.sr_bhvr);
+		strcat(ssv6xxx_result_buf, temp_buf);
+		sprintf(temp_buf, "    sta-mac = %02x:%02x:%02x:%02x:%02x:%02x",
+			ssv_cfg.maddr[0][0], ssv_cfg.maddr[0][1],
+			ssv_cfg.maddr[0][2], ssv_cfg.maddr[0][3],
+			ssv_cfg.maddr[0][4], ssv_cfg.maddr[0][5]);
+		strcat(ssv6xxx_result_buf, temp_buf);
+		strcat(ssv6xxx_result_buf, "\n");
+		return 0;
+	}
+	if (argc != 4)
+		return -1;
+	for (s = 0; cfg_cmds[s].cfg_cmd != NULL; s++) {
+		if (strcmp(cfg_cmds[s].cfg_cmd, argv[1]) == 0) {
+			cfg_cmds[s].translate_func(argv[3],
+						   cfg_cmds[s].var,
+						   cfg_cmds[s].arg);
+			strcpy(ssv6xxx_result_buf, "");
+			return 0;
+		}
+	}
+	return -1;
+}
+
+void *ssv_dbg_phy_table = NULL;
+EXPORT_SYMBOL(ssv_dbg_phy_table);
+u32 ssv_dbg_phy_len = 0;
+EXPORT_SYMBOL(ssv_dbg_phy_len);
+void *ssv_dbg_rf_table = NULL;
+EXPORT_SYMBOL(ssv_dbg_rf_table);
+u32 ssv_dbg_rf_len = 0;
+EXPORT_SYMBOL(ssv_dbg_rf_len);
+struct ssv_softc *ssv_dbg_sc = NULL;
+EXPORT_SYMBOL(ssv_dbg_sc);
+struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci = NULL;
+EXPORT_SYMBOL(ssv_dbg_ctrl_hci);
+struct Dump_Sta_Info {
+	char *dump_buf;
+	int sta_idx;
+};
+static void _dump_sta_info(struct ssv_softc *sc,
+			   struct ssv_vif_info *vif_info,
+			   struct ssv_sta_info *sta_info, void *param)
+{
+	char tmpbf[128];
+	struct Dump_Sta_Info *dump_sta_info = (struct Dump_Sta_Info *)param;
+	struct ssv_sta_priv_data *priv_sta =
+	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+	if ((sta_info->s_flags & STA_FLAG_VALID) == 0)
+		sprintf(tmpbf,
+			"        Station %d: %d is not valid\n",
+			dump_sta_info->sta_idx, priv_sta->sta_idx);
+	else
+		sprintf(tmpbf,
+			"        Station %d: %d\n"
+			"             Address: %02X:%02X:%02X:%02X:%02X:%02X\n"
+			"             WISD: %d\n"
+			"             AID: %d\n"
+			"             Sleep: %d\n",
+			dump_sta_info->sta_idx, priv_sta->sta_idx,
+			sta_info->sta->addr[0], sta_info->sta->addr[1],
+			sta_info->sta->addr[2], sta_info->sta->addr[3],
+			sta_info->sta->addr[4], sta_info->sta->addr[5],
+			sta_info->hw_wsid, sta_info->aid, sta_info->sleeping);
+	dump_sta_info->sta_idx++;
+	strcat(dump_sta_info->dump_buf, tmpbf);
+}
+
+void ssv6xxx_dump_sta_info(struct ssv_softc *sc, char *target_buf)
+{
+	int j;
+	char tmpbf[128];
+	struct Dump_Sta_Info dump_sta_info = { target_buf, 0 };
+	sprintf(tmpbf, "  >>>> bcast queue len[%d]\n", sc->bcast_txq.cur_qsize);
+	strcat(target_buf, tmpbf);
+	for (j = 0; j < SSV6200_MAX_VIF; j++) {
+		struct ieee80211_vif *vif = sc->vif_info[j].vif;
+		struct ssv_vif_priv_data *priv_vif;
+		struct ssv_sta_priv_data *sta_priv_iter;
+		if (vif == NULL) {
+			sprintf(tmpbf, "    VIF: %d is not used.\n", j);
+			strcat(target_buf, tmpbf);
+			continue;
+		}
+		sprintf(tmpbf,
+			"    VIF: %d - [%02X:%02X:%02X:%02X:%02X:%02X] type[%d] p2p[%d]\n",
+			j, vif->addr[0], vif->addr[1], vif->addr[2],
+			vif->addr[3], vif->addr[4], vif->addr[5], vif->type,
+			vif->p2p);
+		strcat(target_buf, tmpbf);
+		priv_vif = (struct ssv_vif_priv_data *)(vif->drv_priv);
+		list_for_each_entry(sta_priv_iter, &priv_vif->sta_list, list) {
+			if ((sta_priv_iter->sta_info->
+			     s_flags & STA_FLAG_VALID) == 0) {
+				sprintf(tmpbf, "    VIF: %d  is not valid.\n",
+					j);
+				strcat(target_buf, tmpbf);
+				continue;
+			}
+			_dump_sta_info(sc, &sc->vif_info[priv_vif->vif_idx],
+				       sta_priv_iter->sta_info, &dump_sta_info);
+		}
+	}
+}
+
+static int ssv_cmd_sta(int argc, char *argv[])
+{
+	if (argc >= 2 && strcmp(argv[1], "show") == 0)
+		ssv6xxx_dump_sta_info(ssv_dbg_sc, ssv6xxx_result_buf);
+	else
+		strcat(ssv6xxx_result_buf, "sta show\n\n");
+	return 0;
+}
+
+static int ssv_cmd_dump(int argc, char *argv[])
+{
+	u32 addr, regval;
+	char tmpbf[64];
+	int s;
+	if (!ssv6xxx_result_buf) {
+		pr_warn("ssv6xxx_result_buf = NULL!!\n");
+		return -1;
+	}
+	if (argc != 2) {
+		sprintf(tmpbf,
+			"dump [wsid|decision|phy-info|phy-reg|rf-reg]\n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		return 0;
+	}
+	if (strcmp(argv[1], "wsid") == 0) {
+		const u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
+		const u32 reg_wsid_tid0[] =
+		    { ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ };
+		const u32 reg_wsid_tid7[] =
+		    { ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ };
+		const u8 *op_mode_str[] = { "STA", "AP", "AD-HOC", "WDS" };
+		const u8 *ht_mode_str[] =
+		    { "Non-HT", "HT-MF", "HT-GF", "RSVD" };
+		for (s = 0; s < SSV_NUM_HW_STA; s++) {
+			if (SSV_REG_READ1
+			    (ssv6xxx_debug_ifops, reg_wsid[s], &regval)) ;
+			sprintf(tmpbf,
+				"==>WSID[%d]\n\tvalid[%d] qos[%d] op_mode[%s] ht_mode[%s]\n",
+				s, regval & 0x1, (regval >> 1) & 0x1,
+				op_mode_str[((regval >> 2) & 3)],
+				ht_mode_str[((regval >> 4) & 3)]);
+			strcat(ssv6xxx_result_buf, tmpbf);
+			if (SSV_REG_READ1
+			    (ssv6xxx_debug_ifops, reg_wsid[s] + 4, &regval)) ;
+			sprintf(tmpbf, "\tMAC[%02x:%02x:%02x:%02x:",
+				(regval & 0xff), ((regval >> 8) & 0xff),
+				((regval >> 16) & 0xff),
+				((regval >> 24) & 0xff));
+			strcat(ssv6xxx_result_buf, tmpbf);
+			if (SSV_REG_READ1
+			    (ssv6xxx_debug_ifops, reg_wsid[s] + 8, &regval)) ;
+			sprintf(tmpbf, "%02x:%02x]\n", (regval & 0xff),
+				((regval >> 8) & 0xff));
+			strcat(ssv6xxx_result_buf, tmpbf);
+			for (addr = reg_wsid_tid0[s]; addr <= reg_wsid_tid7[s];
+			     addr += 4) {
+				if (SSV_REG_READ1
+				    (ssv6xxx_debug_ifops, addr, &regval)) ;
+				sprintf(tmpbf, "\trx_seq%d[%d]\n",
+					((addr - reg_wsid_tid0[s]) >> 2),
+					((regval) & 0xffff));
+				strcat(ssv6xxx_result_buf, tmpbf);
+			}
+		}
+		return 0;
+	}
+	if (strcmp(argv[1], "decision") == 0) {
+		strcpy(ssv6xxx_result_buf, ">> Decision Table:\n");
+		for (s = 0, addr = ADR_MRX_FLT_TB0; s < 16; s++, addr += 4) {
+			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &regval)) ;
+			sprintf(tmpbf, "   [%d]: ADDR[0x%08x] = 0x%08x\n",
+				s, addr, regval);
+			strcat(ssv6xxx_result_buf, tmpbf);
+		}
+		strcat(ssv6xxx_result_buf, "\n\n>> Decision Mask:\n");
+		for (s = 0, addr = ADR_MRX_FLT_EN0; s < 9; s++, addr += 4) {
+			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &regval)) ;
+			sprintf(tmpbf, "   [%d]: ADDR[0x%08x] = 0x%08x\n",
+				s, addr, regval);
+			strcat(ssv6xxx_result_buf, tmpbf);
+		}
+		strcat(ssv6xxx_result_buf, "\n\n");
+		return 0;
+	}
+	if (strcmp(argv[1], "phy-info") == 0) {
+		return 0;
+	}
+	if (strcmp(argv[1], "phy-reg") == 0) {
+		struct ssv6xxx_dev_table *raw;
+		raw = (struct ssv6xxx_dev_table *)ssv_dbg_phy_table;
+		strcpy(ssv6xxx_result_buf, ">> PHY Register Table:\n");
+		for (s = 0; s < ssv_dbg_phy_len; s++, raw++) {
+			if (SSV_REG_READ1
+			    (ssv6xxx_debug_ifops, raw->address, &regval)) ;
+			sprintf(tmpbf, "   ADDR[0x%08x] = 0x%08x\n",
+				raw->address, regval);
+			strcat(ssv6xxx_result_buf, tmpbf);
+		}
+		strcat(ssv6xxx_result_buf, "\n\n");
+		return 0;
+	}
+	if (strcmp(argv[1], "rf-reg") == 0) {
+		struct ssv6xxx_dev_table *raw;
+		raw = (struct ssv6xxx_dev_table *)ssv_dbg_rf_table;
+		strcpy(ssv6xxx_result_buf, ">> RF Register Table:\n");
+		for (s = 0; s < ssv_dbg_rf_len; s++, raw++) {
+			if (SSV_REG_READ1
+			    (ssv6xxx_debug_ifops, raw->address, &regval)) ;
+			sprintf(tmpbf, "   ADDR[0x%08x] = 0x%08x\n",
+				raw->address, regval);
+			strcat(ssv6xxx_result_buf, tmpbf);
+		}
+		strcat(ssv6xxx_result_buf, "\n\n");
+		return 0;
+	}
+	return -1;
+}
+
+static int ssv_cmd_irq(int argc, char *argv[])
+{
+	char *endp;
+	u32 irq_sts;
+	if (argc >= 3 && strcmp(argv[1], "set") == 0) {
+		if (strcmp(argv[2], "mask") == 0 && argc == 4) {
+			irq_sts = simple_strtoul(argv[3], &endp, 16);
+			if (!ssv6xxx_debug_ifops->ifops->irq_setmask) {
+				sprintf(ssv6xxx_result_buf,
+					"The interface doesn't provide irq_setmask operation.\n");
+				return 0;
+			}
+			ssv6xxx_debug_ifops->ifops->
+			    irq_setmask(ssv6xxx_debug_ifops->dev, irq_sts);
+			sprintf(ssv6xxx_result_buf,
+				"set sdio irq mask to 0x%08x\n", irq_sts);
+			return 0;
+		}
+		if (strcmp(argv[2], "enable") == 0) {
+			if (!ssv6xxx_debug_ifops->ifops->irq_enable) {
+				sprintf(ssv6xxx_result_buf,
+					"The interface doesn't provide irq_enable operation.\n");
+				return 0;
+			}
+			ssv6xxx_debug_ifops->ifops->
+			    irq_enable(ssv6xxx_debug_ifops->dev);
+			strcpy(ssv6xxx_result_buf, "enable sdio irq.\n");
+			return 0;
+		}
+		if (strcmp(argv[2], "disable") == 0) {
+			if (!ssv6xxx_debug_ifops->ifops->irq_disable) {
+				sprintf(ssv6xxx_result_buf,
+					"The interface doesn't provide irq_disable operation.\n");
+				return 0;
+			}
+			ssv6xxx_debug_ifops->ifops->
+			    irq_disable(ssv6xxx_debug_ifops->dev, false);
+			strcpy(ssv6xxx_result_buf, "disable sdio irq.\n");
+			return 0;
+		}
+		return -1;
+	} else if (argc == 3 && strcmp(argv[1], "get") == 0) {
+		if (strcmp(argv[2], "mask") == 0) {
+			if (!ssv6xxx_debug_ifops->ifops->irq_getmask) {
+				sprintf(ssv6xxx_result_buf,
+					"The interface doesn't provide irq_getmask operation.\n");
+				return 0;
+			}
+			ssv6xxx_debug_ifops->ifops->
+			    irq_getmask(ssv6xxx_debug_ifops->dev, &irq_sts);
+			sprintf(ssv6xxx_result_buf,
+				"sdio irq mask: 0x%08x, int_mask=0x%08x\n",
+				irq_sts, ssv_dbg_ctrl_hci->int_mask);
+			return 0;
+		}
+		if (strcmp(argv[2], "status") == 0) {
+			if (!ssv6xxx_debug_ifops->ifops->irq_getstatus) {
+				sprintf(ssv6xxx_result_buf,
+					"The interface doesn't provide irq_getstatus operation.\n");
+				return 0;
+			}
+			ssv6xxx_debug_ifops->ifops->
+			    irq_getstatus(ssv6xxx_debug_ifops->dev, &irq_sts);
+			sprintf(ssv6xxx_result_buf, "sdio irq status: 0x%08x\n",
+				irq_sts);
+			return 0;
+		}
+		return -1;
+	} else {
+		sprintf(ssv6xxx_result_buf,
+			"irq [set|get] [mask|enable|disable|status]\n");
+	}
+	return 0;
+}
+
+static int ssv_cmd_mac(int argc, char *argv[])
+{
+	char temp_str[128], *endp;
+	u32 s;
+	int i;
+	if (argc == 3 && !strcmp(argv[1], "wsid") && !strcmp(argv[2], "show")) {
+		for (s = 0; s < SSV_NUM_HW_STA; s++) {
+		}
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "rx")) {
+		if (!strcmp(argv[2], "enable")) {
+			ssv_dbg_sc->dbg_rx_frame = 1;
+		} else {
+			ssv_dbg_sc->dbg_rx_frame = 0;
+		}
+		sprintf(temp_str, "  dbg_rx_frame %d\n",
+			ssv_dbg_sc->dbg_rx_frame);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "tx")) {
+		if (!strcmp(argv[2], "enable")) {
+			ssv_dbg_sc->dbg_tx_frame = 1;
+		} else {
+			ssv_dbg_sc->dbg_tx_frame = 0;
+		}
+		sprintf(temp_str, "  dbg_tx_frame %d\n",
+			ssv_dbg_sc->dbg_tx_frame);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "rxq")
+		   && !strcmp(argv[2], "show")) {
+		sprintf(temp_str, ">> MAC RXQ: (%s)\n    cur_qsize=%d\n",
+			((ssv_dbg_sc->
+			  sc_flags & SC_OP_OFFCHAN) ? "off channel" :
+			 "on channel"), ssv_dbg_sc->rx.rxq_count);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if (argc == 4 && !strcmp(argv[1], "set")
+		   && !strcmp(argv[2], "rate")) {
+		if (strcmp(argv[3], "auto") == 0) {
+			ssv_dbg_sc->sc_flags &= ~SC_OP_FIXED_RATE;
+			return 0;
+		}
+		i = simple_strtoul(argv[3], &endp, 10);
+		if (i < 0 || i > 38) {
+			strcpy(ssv6xxx_result_buf, " Invalid rat index !!\n");
+			return -1;
+		}
+		ssv_dbg_sc->max_rate_idx = i;
+		ssv_dbg_sc->sc_flags |= SC_OP_FIXED_RATE;
+		sprintf(temp_str, " Set rate to index %d\n", i);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "get")
+		   && !strcmp(argv[2], "rate")) {
+		if (ssv_dbg_sc->sc_flags & SC_OP_FIXED_RATE)
+			sprintf(temp_str, " Current Rate Index: %d\n",
+				ssv_dbg_sc->max_rate_idx);
+		else
+			sprintf(temp_str, "  Current Rate Index: auto\n");
+		strcpy(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else {
+		sprintf(temp_str, "mac [security|wsid|rxq]  [show]\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "mac [set|get] [rate] [auto|idx]\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "mac [rx|tx] [eable|disable]\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	}
+	return 0;
+}
+
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+void print_irq_count(void)
+{
+	char temp_str[512];
+	sprintf(temp_str, "irq debug (%s)\n",
+		ssv_dbg_ctrl_hci->irq_enable ? "enable" : "disable");
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "total irq (%d)\n", ssv_dbg_ctrl_hci->irq_count);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "invalid irq (%d)\n",
+		ssv_dbg_ctrl_hci->invalid_irq_count);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "rx irq (%d)\n", ssv_dbg_ctrl_hci->rx_irq_count);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "tx irq (%d)\n", ssv_dbg_ctrl_hci->tx_irq_count);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "real tx count irq (%d)\n",
+		ssv_dbg_ctrl_hci->real_tx_irq_count);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "tx  packet count (%d)\n",
+		ssv_dbg_ctrl_hci->irq_tx_pkt_count);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "rx packet (%d)\n",
+		ssv_dbg_ctrl_hci->irq_rx_pkt_count);
+	strcat(ssv6xxx_result_buf, temp_str);
+}
+#endif
+void print_isr_info(void)
+{
+	char temp_str[512];
+	sprintf(temp_str, ">>>> HCI Calculate ISR TIME(%s) unit:us\n",
+		((ssv_dbg_ctrl_hci->isr_summary_eable) ? "enable" : "disable"));
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "isr_routine_time(%d)\n",
+		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_routine_time));
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "isr_tx_time(%d)\n",
+		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_tx_time));
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "isr_rx_time(%d)\n",
+		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_rx_time));
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "isr_idle_time(%d)\n",
+		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_idle_time));
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "isr_rx_idle_time(%d)\n",
+		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_rx_idle_time));
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "isr_miss_cnt(%d)\n", ssv_dbg_ctrl_hci->isr_miss_cnt);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "prev_isr_jiffes(%lu)\n",
+		ssv_dbg_ctrl_hci->prev_isr_jiffes);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "prev_rx_isr_jiffes(%lu)\n",
+		ssv_dbg_ctrl_hci->prev_rx_isr_jiffes);
+	strcat(ssv6xxx_result_buf, temp_str);
+}
+
+static int ssv_cmd_hci(int argc, char *argv[])
+{
+	struct ssv_hw_txq *txq;
+	char temp_str[512];
+	int s, ac = 0;
+	if (argc == 3 && !strcmp(argv[1], "txq") && !strcmp(argv[2], "show")) {
+		for (s = 0; s < WMM_NUM_AC; s++) {
+			if (ssv_dbg_sc != NULL)
+				ac = ssv_dbg_sc->tx.ac_txqid[s];
+			txq = &ssv_dbg_ctrl_hci->hw_txq[s];
+			sprintf(temp_str, ">> txq[%d]", txq->txq_no);
+			if (ssv_dbg_sc != NULL)
+				sprintf(temp_str, "(%s): ",
+					((ssv_dbg_sc->
+					  sc_flags & SC_OP_OFFCHAN) ?
+					 "off channel" : "on channel"));
+			sprintf(temp_str, "cur_qsize=%d\n",
+				skb_queue_len(&txq->qhead));
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str,
+				"            max_qsize=%d, pause=%d, resume_thres=%d",
+				txq->max_qsize, txq->paused, txq->resum_thres);
+			if (ssv_dbg_sc != NULL)
+				sprintf(temp_str, " flow_control[%d]\n",
+					!!(ssv_dbg_sc->tx.
+					   flow_ctrl_status & (1 << ac)));
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "            Total %d frame sent\n",
+				txq->tx_pkt);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		sprintf(temp_str,
+			">> HCI Debug Counters:\n    read_rs0_info_fail=%d, read_rs1_info_fail=%d\n",
+			ssv_dbg_ctrl_hci->read_rs0_info_fail,
+			ssv_dbg_ctrl_hci->read_rs1_info_fail);
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str,
+			"    rx_work_running=%d, isr_running=%d, xmit_running=%d\n",
+			ssv_dbg_ctrl_hci->rx_work_running,
+			ssv_dbg_ctrl_hci->isr_running,
+			ssv_dbg_ctrl_hci->xmit_running);
+		strcat(ssv6xxx_result_buf, temp_str);
+		if (ssv_dbg_sc != NULL)
+			sprintf(temp_str, "    flow_ctrl_status=%08x\n",
+				ssv_dbg_sc->tx.flow_ctrl_status);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "rxq")
+		   && !strcmp(argv[2], "show")) {
+		sprintf(temp_str, ">> HCI RX Queue (%s): cur_qsize=%d\n",
+			((ssv_dbg_sc->
+			  sc_flags & SC_OP_OFFCHAN) ? "off channel" :
+			 "on channel"), ssv_dbg_ctrl_hci->rx_pkt);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "isr_time")
+		   && !strcmp(argv[2], "start")) {
+		ssv_dbg_ctrl_hci->isr_summary_eable = 1;
+		ssv_dbg_ctrl_hci->isr_routine_time = 0;
+		ssv_dbg_ctrl_hci->isr_tx_time = 0;
+		ssv_dbg_ctrl_hci->isr_rx_time = 0;
+		ssv_dbg_ctrl_hci->isr_idle_time = 0;
+		ssv_dbg_ctrl_hci->isr_rx_idle_time = 0;
+		ssv_dbg_ctrl_hci->isr_miss_cnt = 0;
+		ssv_dbg_ctrl_hci->prev_isr_jiffes = 0;
+		ssv_dbg_ctrl_hci->prev_rx_isr_jiffes = 0;
+		print_isr_info();
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "isr_time")
+		   && !strcmp(argv[2], "stop")) {
+		ssv_dbg_ctrl_hci->isr_summary_eable = 0;
+		print_isr_info();
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "isr_time")
+		   && !strcmp(argv[2], "show")) {
+		print_isr_info();
+		return 0;
+	}
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+	else if (argc == 3 && !strcmp(argv[1], "isr_debug")
+		 && !strcmp(argv[2], "reset")) {
+		ssv_dbg_ctrl_hci->irq_enable = 0;
+		ssv_dbg_ctrl_hci->irq_count = 0;
+		ssv_dbg_ctrl_hci->invalid_irq_count = 0;
+		ssv_dbg_ctrl_hci->tx_irq_count = 0;
+		ssv_dbg_ctrl_hci->real_tx_irq_count = 0;
+		ssv_dbg_ctrl_hci->rx_irq_count = 0;
+		ssv_dbg_ctrl_hci->isr_rx_idle_time = 0;
+		ssv_dbg_ctrl_hci->irq_rx_pkt_count = 0;
+		ssv_dbg_ctrl_hci->irq_tx_pkt_count = 0;
+		strcat(ssv6xxx_result_buf, "irq debug reset count\n");
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "isr_debug")
+		   && !strcmp(argv[2], "show")) {
+		print_irq_count();
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "isr_debug")
+		   && !strcmp(argv[2], "stop")) {
+		ssv_dbg_ctrl_hci->irq_enable = 0;
+		strcat(ssv6xxx_result_buf, "irq debug stop\n");
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "isr_debug")
+		   && !strcmp(argv[2], "start")) {
+		ssv_dbg_ctrl_hci->irq_enable = 1;
+		strcat(ssv6xxx_result_buf, "irq debug start\n");
+		return 0;
+	}
+#endif
+	else {
+		strcat(ssv6xxx_result_buf,
+		       "hci [txq|rxq] [show]\nhci [isr_time] [start|stop|show]\n\n");
+		return 0;
+	}
+	return -1;
+}
+
+static int ssv_cmd_hwq(int argc, char *argv[])
+{
+#undef GET_FFO0_CNT
+#undef GET_FFO1_CNT
+#undef GET_FFO2_CNT
+#undef GET_FFO3_CNT
+#undef GET_FFO4_CNT
+#undef GET_FFO5_CNT
+#undef GET_FFO6_CNT
+#undef GET_FFO7_CNT
+#undef GET_FFO8_CNT
+#undef GET_FFO9_CNT
+#undef GET_FFO10_CNT
+#undef GET_FFO11_CNT
+#undef GET_FFO12_CNT
+#undef GET_FFO13_CNT
+#undef GET_FFO14_CNT
+#undef GET_FFO15_CNT
+#undef GET_FF0_CNT
+#undef GET_FF1_CNT
+#undef GET_FF3_CNT
+#undef GET_FF5_CNT
+#undef GET_FF6_CNT
+#undef GET_FF7_CNT
+#undef GET_FF8_CNT
+#undef GET_FF9_CNT
+#undef GET_FF10_CNT
+#undef GET_FF11_CNT
+#undef GET_FF12_CNT
+#undef GET_FF13_CNT
+#undef GET_FF14_CNT
+#undef GET_FF15_CNT
+#undef GET_FF4_CNT
+#undef GET_FF2_CNT
+#undef GET_TX_ID_ALC_LEN
+#undef GET_RX_ID_ALC_LEN
+#undef GET_AVA_TAG
+#define GET_FFO0_CNT ((value & 0x0000001f ) >> 0)
+#define GET_FFO1_CNT ((value & 0x000003e0 ) >> 5)
+#define GET_FFO2_CNT ((value & 0x00000c00 ) >> 10)
+#define GET_FFO3_CNT ((value & 0x000f8000 ) >> 15)
+#define GET_FFO4_CNT ((value & 0x00300000 ) >> 20)
+#define GET_FFO5_CNT ((value & 0x0e000000 ) >> 25)
+#define GET_FFO6_CNT ((value1 & 0x0000000f ) >> 0)
+#define GET_FFO7_CNT ((value1 & 0x000003e0 ) >> 5)
+#define GET_FFO8_CNT ((value1 & 0x00007c00 ) >> 10)
+#define GET_FFO9_CNT ((value1 & 0x000f8000 ) >> 15)
+#define GET_FFO10_CNT ((value1 & 0x00f00000 ) >> 20)
+#define GET_FFO11_CNT ((value1 & 0x3e000000 ) >> 25)
+#define GET_FFO12_CNT ((value2 & 0x00000007 ) >> 0)
+#define GET_FFO13_CNT ((value2 & 0x00000060 ) >> 5)
+#define GET_FFO14_CNT ((value2 & 0x00000c00 ) >> 10)
+#define GET_FFO15_CNT ((value2 & 0x001f8000 ) >> 15)
+#define GET_FF0_CNT ((value & 0x0000001f ) >> 0)
+#define GET_FF1_CNT ((value & 0x000001e0 ) >> 5)
+#define GET_FF3_CNT ((value & 0x00003800 ) >> 11)
+#define GET_FF5_CNT ((value & 0x000e0000 ) >> 17)
+#define GET_FF6_CNT ((value & 0x00700000 ) >> 20)
+#define GET_FF7_CNT ((value & 0x03800000 ) >> 23)
+#define GET_FF8_CNT ((value & 0x1c000000 ) >> 26)
+#define GET_FF9_CNT ((value & 0xe0000000 ) >> 29)
+#define GET_FF10_CNT ((value1 & 0x00000007 ) >> 0)
+#define GET_FF11_CNT ((value1 & 0x00000038 ) >> 3)
+#define GET_FF12_CNT ((value1 & 0x000001c0 ) >> 6)
+#define GET_FF13_CNT ((value1 & 0x00000600 ) >> 9)
+#define GET_FF14_CNT ((value1 & 0x00001800 ) >> 11)
+#define GET_FF15_CNT ((value1 & 0x00006000 ) >> 13)
+#define GET_FF4_CNT ((value1 & 0x000f8000 ) >> 15)
+#define GET_FF2_CNT ((value1 & 0x00700000 ) >> 20)
+#define GET_TX_ID_ALC_LEN ((value & 0x0003fe00 ) >> 9)
+#define GET_RX_ID_ALC_LEN ((value & 0x07fc0000 ) >> 18)
+#define GET_AVA_TAG ((value1 & 0x01ff0000 ) >> 16)
+	u32 addr, value, value1, value2;
+	char temp_str[512];
+	addr = ADR_RD_FFOUT_CNT1;
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+	addr = ADR_RD_FFOUT_CNT2;
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
+	addr = ADR_RD_FFOUT_CNT3;
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value2)) ;
+	sprintf(temp_str,
+		"\n[TAG]  MCU - HCI - SEC -  RX - MIC - TX0 - TX1 - TX2 - TX3 - TX4 - SEC - MIC - TSH\n");
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str,
+		"OUTPUT %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
+		GET_FFO0_CNT, GET_FFO1_CNT, GET_FFO3_CNT, GET_FFO4_CNT,
+		GET_FFO5_CNT, GET_FFO6_CNT, GET_FFO7_CNT, GET_FFO8_CNT,
+		GET_FFO9_CNT, GET_FFO10_CNT, GET_FFO11_CNT, GET_FFO12_CNT,
+		GET_FFO15_CNT);
+	strcat(ssv6xxx_result_buf, temp_str);
+	addr = ADR_RD_IN_FFCNT1;
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+	addr = ADR_RD_IN_FFCNT2;
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
+	sprintf(temp_str,
+		"INPUT  %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
+		GET_FF0_CNT, GET_FF1_CNT, GET_FF3_CNT, GET_FF4_CNT, GET_FF5_CNT,
+		GET_FF6_CNT, GET_FF7_CNT, GET_FF8_CNT, GET_FF9_CNT,
+		GET_FF10_CNT, GET_FF11_CNT, GET_FF12_CNT, GET_FF15_CNT);
+	strcat(ssv6xxx_result_buf, temp_str);
+	addr = ADR_ID_LEN_THREADSHOLD2;
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+	addr = ADR_TAG_STATUS;
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
+	sprintf(temp_str, "TX[%d]RX[%d]AVA[%d]\n", GET_TX_ID_ALC_LEN,
+		GET_RX_ID_ALC_LEN, GET_AVA_TAG);
+	strcat(ssv6xxx_result_buf, temp_str);
+	return 0;
+}
+
+#ifdef CONFIG_P2P_NOA
+static struct ssv6xxx_p2p_noa_param cmd_noa_param = {
+	50,
+	100,
+	0x12345678,
+	1,
+	255,
+	{0x4c, 0xe6, 0x76, 0xa2, 0x4e, 0x7c}
+};
+
+void noa_dump(char *temp_str)
+{
+	sprintf(temp_str,
+		"NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]\n",
+		cmd_noa_param.enable, cmd_noa_param.interval,
+		cmd_noa_param.duration, cmd_noa_param.start_time,
+		cmd_noa_param.count, cmd_noa_param.addr[0],
+		cmd_noa_param.addr[1], cmd_noa_param.addr[2],
+		cmd_noa_param.addr[3], cmd_noa_param.addr[4],
+		cmd_noa_param.addr[5]);
+	strcat(ssv6xxx_result_buf, temp_str);
+}
+
+void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
+			  struct ssv6xxx_p2p_noa_param *p2p_noa_param)
+{
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	int retry_cnt = 5;
+	skb =
+	    ssvdevice_skb_alloc(HOST_CMD_HDR_LEN +
+				sizeof(struct ssv6xxx_p2p_noa_param));
+	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param);
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_SET_NOA;
+	host_cmd->len = skb->data_len;
+	memcpy(host_cmd->dat32, p2p_noa_param,
+	       sizeof(struct ssv6xxx_p2p_noa_param));
+	while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
+		pr_debug("NOA cmd retry=%d\n", retry_cnt);
+		retry_cnt--;
+	}
+	ssvdevice_skb_free(skb);
+}
+
+static int ssv_cmd_noa(int argc, char *argv[])
+{
+	char temp_str[512];
+	char *endp;
+	if (argc == 2 && !strcmp(argv[1], "show")) {
+		;
+	} else if (argc == 3 && !strcmp(argv[1], "duration")) {
+		cmd_noa_param.duration = simple_strtoul(argv[2], &endp, 0);
+	} else if (argc == 3 && !strcmp(argv[1], "interval")) {
+		cmd_noa_param.interval = simple_strtoul(argv[2], &endp, 0);
+	} else if (argc == 3 && !strcmp(argv[1], "start")) {
+		cmd_noa_param.start_time = simple_strtoul(argv[2], &endp, 0);
+	} else if (argc == 3 && !strcmp(argv[1], "enable")) {
+		cmd_noa_param.enable = simple_strtoul(argv[2], &endp, 0);
+	} else if (argc == 3 && !strcmp(argv[1], "count")) {
+		cmd_noa_param.count = simple_strtoul(argv[2], &endp, 0);
+	} else if (argc == 8 && !strcmp(argv[1], "addr")) {
+		cmd_noa_param.addr[0] = simple_strtoul(argv[2], &endp, 16);
+		cmd_noa_param.addr[1] = simple_strtoul(argv[3], &endp, 16);
+		cmd_noa_param.addr[2] = simple_strtoul(argv[4], &endp, 16);
+		cmd_noa_param.addr[3] = simple_strtoul(argv[5], &endp, 16);
+		cmd_noa_param.addr[4] = simple_strtoul(argv[6], &endp, 16);
+		cmd_noa_param.addr[5] = simple_strtoul(argv[7], &endp, 16);
+	} else if (argc == 2 && !strcmp(argv[1], "send")) {
+		ssv6xxx_send_noa_cmd(ssv_dbg_sc, &cmd_noa_param);
+	} else {
+		sprintf(temp_str, "## wrong command\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	}
+	noa_dump(temp_str);
+	return 0;
+}
+#endif
+static int ssv_cmd_mib(int argc, char *argv[])
+{
+	u32 addr, value;
+	char temp_str[512];
+	int i;
+	if (argc == 2 && !strcmp(argv[1], "reset")) {
+		addr = MIB_REG_BASE;
+		value = 0x0;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, MIB_REG_BASE, value)) ;
+		value = 0xffffffff;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, MIB_REG_BASE, value)) ;
+		value = 0x0;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0023F8, value)) ;
+		value = 0x100000;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0023F8, value)) ;
+		value = 0x0;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0043F8, value)) ;
+		value = 0x100000;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0043F8, value)) ;
+		value = 0x0;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE000088, value)) ;
+		value = 0x80000000;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE000088, value)) ;
+		sprintf(temp_str, " => MIB reseted\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if (argc == 2 && !strcmp(argv[1], "list")) {
+		addr = MIB_REG_BASE;
+		for (i = 0; i < 120; i++, addr += 4) {
+			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+			sprintf(temp_str, "%08x ", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+			if (((i + 1) & 0x07) == 0)
+				strcat(ssv6xxx_result_buf, "\n");
+		}
+		strcat(ssv6xxx_result_buf, "\n");
+	} else if (argc == 2 && strcmp(argv[1], "rx") == 0) {
+		sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\t\t%-10s\n",
+			"MRX_FCS_SUCC", "MRX_FCS_ERR", "MRX_ALC_FAIL",
+			"MRX_MISS");
+		strcat(ssv6xxx_result_buf, temp_str);
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_MRX_FCS_SUCC, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_FCS_ERR, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_MRX_ALC_FAIL, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_MISS, &value)) {
+			sprintf(temp_str, "[%08x]\n", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\t%-10s\n",
+				"MRX_MB_MISS", "MRX_NIDLE_MISS",
+				"DBG_LEN_ALC_FAIL", "DBG_LEN_CRC_FAIL");
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_MB_MISS, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_MRX_NIDLE_MISS, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_DBG_LEN_ALC_FAIL, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_DBG_LEN_CRC_FAIL, &value)) {
+			sprintf(temp_str, "[%08x]\n\n", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_DBG_AMPDU_PASS, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_DBG_AMPDU_FAIL, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_ID_ALC_FAIL1, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_ID_ALC_FAIL2, &value)) {
+			sprintf(temp_str, "[%08x]\n\n", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "PHY B mode:\n");
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\n",
+				"CRC error", "CCA", "counter");
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0023E8, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value & 0xffff);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0023EC, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", (value >> 16) & 0xffff);
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "[%08x]\t\t\n\n", value & 0xffff);
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "PHY G/N mode:\n");
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\n",
+				"CRC error", "CCA", "counter");
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0043E8, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value & 0xffff);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0043EC, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", (value >> 16) & 0xffff);
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "[%08x]\t\t\n\n", value & 0xffff);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+	} else {
+		sprintf(temp_str, "mib [reset|list|rx]\n\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	}
+	return 0;
+}
+
+static int ssv_cmd_sdio(int argc, char *argv[])
+{
+	u32 addr, value;
+	char temp_str[512], *endp;
+	int ret = 0;
+	if (argc == 4 && !strcmp(argv[1], "reg") && !strcmp(argv[2], "r")) {
+		addr = simple_strtoul(argv[3], &endp, 16);
+		if (!ssv6xxx_debug_ifops->ifops->cmd52_read) {
+			sprintf(temp_str,
+				"The interface doesn't provide cmd52 read\n");
+			strcat(ssv6xxx_result_buf, temp_str);
+			return 0;
+		}
+		ret =
+		    ssv6xxx_debug_ifops->ifops->cmd52_read(ssv6xxx_debug_ifops->
+							   dev, addr, &value);
+		if (ret >= 0) {
+			sprintf(temp_str, "  ==> %x\n", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+			return 0;
+		}
+	} else if (argc == 5 && !strcmp(argv[1], "reg")
+		   && !strcmp(argv[2], "w")) {
+		addr = simple_strtoul(argv[3], &endp, 16);
+		value = simple_strtoul(argv[4], &endp, 16);
+		if (!ssv6xxx_debug_ifops->ifops->cmd52_write) {
+			sprintf(temp_str,
+				"The interface doesn't provide cmd52 write\n");
+			strcat(ssv6xxx_result_buf, temp_str);
+			return 0;
+		}
+		ret =
+		    ssv6xxx_debug_ifops->ifops->
+		    cmd52_write(ssv6xxx_debug_ifops->dev, addr, value);
+		if (ret >= 0) {
+			sprintf(temp_str, "  ==> write odne.\n");
+			strcat(ssv6xxx_result_buf, temp_str);
+			return 0;
+		}
+	}
+	sprintf(temp_str, "sdio cmd52 fail: %d\n", ret);
+	strcat(ssv6xxx_result_buf, temp_str);
+	return 0;
+}
+
+static struct ssv6xxx_iqk_cfg cmd_iqk_cfg = {
+	SSV6XXX_IQK_CFG_XTAL_26M,
+	SSV6XXX_IQK_CFG_PA_DEF,
+	0,
+	0,
+	26,
+	3,
+	0x75,
+	0x75,
+	0x80,
+	0x80,
+	SSV6XXX_IQK_CMD_INIT_CALI,
+	{SSV6XXX_IQK_TEMPERATURE
+	 + SSV6XXX_IQK_RXDC
+	 + SSV6XXX_IQK_RXRC
+	 + SSV6XXX_IQK_TXDC + SSV6XXX_IQK_TXIQ + SSV6XXX_IQK_RXIQ},
+};
+
+static int ssv_cmd_iqk(int argc, char *argv[])
+{
+	char temp_str[512], *endp;
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	u32 rxcnt_total, rxcnt_error;
+	sprintf(temp_str, "# got iqk command\n");
+	strcat(ssv6xxx_result_buf, temp_str);
+	if ((argc == 3) && (strcmp(argv[1], "cfg-pa") == 0)) {
+		cmd_iqk_cfg.cfg_pa = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## set cfg_pa as %d\n", cmd_iqk_cfg.cfg_pa);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if ((argc == 3) && (strcmp(argv[1], "cfg-tssi-trgt") == 0)) {
+		cmd_iqk_cfg.cfg_tssi_trgt = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## set cfg_tssi_trgt as %d\n",
+			cmd_iqk_cfg.cfg_tssi_trgt);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if ((argc == 3) && (strcmp(argv[1], "init-cali") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_INIT_CALI;
+		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do init-cali\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-load") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD;
+		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do rtbl-load\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-load-def") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD_DEF;
+		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do rtbl-load\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-reset") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_RESET;
+		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do rtbl-reset\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-set") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_SET;
+		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do rtbl-set\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-export") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_EXPORT;
+		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do rtbl-export\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "tk-evm") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_EVM;
+		cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do tk-evm\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "tk-tone") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_TONE;
+		cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do tk-tone\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "channel") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_CHCH;
+		cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do change channel\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 2) && (strcmp(argv[1], "tk-rxcnt-report") == 0)) {
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, 0xCE0043E8, &rxcnt_error)) ;
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, 0xCE0043EC, &rxcnt_total)) ;
+		sprintf(temp_str, "## GN Rx error rate = (%06d/%06d)\n",
+			rxcnt_error, rxcnt_total);
+		strcat(ssv6xxx_result_buf, temp_str);
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, 0xCE0023E8, &rxcnt_error)) ;
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, 0xCE0023EC, &rxcnt_total)) ;
+		sprintf(temp_str, "## B Rx error rate = (%06d/%06d)\n",
+			rxcnt_error, rxcnt_total);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else {
+		sprintf(temp_str, "## invalid iqk command\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "## cmd: cfg-pa/cfg-tssi-trgt\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str,
+			"## cmd: init-cali/rtbl-load/rtbl-load-def/rtbl-reset/rtbl-set/rtbl-export/tk-evm/tk-tone/tk-channel\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "## fx_sel: 0x0008: RXDC\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "           0x0010: RXRC\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "           0x0020: TXDC\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "           0x0040: TXIQ\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "           0x0080: RXIQ\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "           0x0100: TSSI\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "           0x0200: PAPD\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	}
+	skb =
+	    ssvdevice_skb_alloc(HOST_CMD_HDR_LEN + IQK_CFG_LEN +
+				PHY_SETTING_SIZE + RF_SETTING_SIZE);
+	if (skb == NULL) {
+		pr_err("ssv command ssvdevice_skb_alloc failure\n");
+		return 0;
+	}
+	if ((PHY_SETTING_SIZE > MAX_PHY_SETTING_TABLE_SIZE) ||
+	    (RF_SETTING_SIZE > MAX_RF_SETTING_TABLE_SIZE)) {
+		pr_err("Please check RF or PHY table size\n");
+		BUG_ON(1);
+		return 0;
+	}
+	skb->data_len =
+	    HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE;
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_INIT_CALI;
+	host_cmd->len = skb->data_len;
+	cmd_iqk_cfg.phy_tbl_size = PHY_SETTING_SIZE;
+	cmd_iqk_cfg.rf_tbl_size = RF_SETTING_SIZE;
+	memcpy(host_cmd->dat32, &cmd_iqk_cfg, IQK_CFG_LEN);
+	memcpy(host_cmd->dat8 + IQK_CFG_LEN, phy_setting, PHY_SETTING_SIZE);
+	memcpy(host_cmd->dat8 + IQK_CFG_LEN + PHY_SETTING_SIZE, asic_rf_setting,
+	       RF_SETTING_SIZE);
+	if (ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb) == 0) {
+		sprintf(temp_str, "## hci send cmd success\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else {
+		sprintf(temp_str, "## hci send cmd fail\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	}
+	ssvdevice_skb_free(skb);
+	return 0;
+}
+
+#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
+    (((a) & 0xff00ff00) >> 8))
+#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
+static int ssv_cmd_version(int argc, char *argv[])
+{
+	char temp_str[256];
+	u32 regval;
+	u64 chip_tag = 0;
+	char chip_id[24] = "";
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_IC_TIME_TAG_1, &regval)) ;
+	chip_tag = ((u64) regval << 32);
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_IC_TIME_TAG_0, &regval)) ;
+	chip_tag |= (regval);
+	sprintf(temp_str, "CHIP TAG: %llx \n", chip_tag);
+	strcat(ssv6xxx_result_buf, temp_str);
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_3, &regval)) ;
+	*((u32 *) & chip_id[0]) = (u32) LONGSWAP(regval);
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_2, &regval)) ;
+	*((u32 *) & chip_id[4]) = (u32) LONGSWAP(regval);
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_1, &regval)) ;
+	*((u32 *) & chip_id[8]) = (u32) LONGSWAP(regval);
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_0, &regval)) ;
+	*((u32 *) & chip_id[12]) = (u32) LONGSWAP(regval);
+	sprintf(temp_str, "CHIP ID: %s \n", chip_id);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "# current Software mac version: %d\n",
+		ssv_root_version);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "SVN ROOT URL %s \n", SSV_ROOT_URl);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "COMPILER HOST %s \n", COMPILERHOST);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "COMPILER DATE %s \n", COMPILERDATE);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "COMPILER OS %s \n", COMPILEROS);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "COMPILER OS ARCH %s \n", COMPILEROSARCH);
+	strcat(ssv6xxx_result_buf, temp_str);
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, FW_VERSION_REG, &regval)) ;
+	sprintf(temp_str, "Firmware image version: %d\n", regval);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "\n[Compiler Option!!]\n");
+	strcat(ssv6xxx_result_buf, temp_str);
+	return 0;
+}
+
+static int ssv_cmd_tool(int argc, char *argv[])
+{
+	u32 addr, value, count;
+	char tmpbf[12], *endp;
+	int s;
+	if (argc == 4 && strcmp(argv[1], "w") == 0) {
+		addr = simple_strtoul(argv[2], &endp, 16);
+		value = simple_strtoul(argv[3], &endp, 16);
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, addr, value)) ;
+		sprintf(ssv6xxx_result_buf, "ok");
+		return 0;
+	}
+	if ((argc == 4 || argc == 3) && strcmp(argv[1], "r") == 0) {
+		count = (argc == 3) ? 1 : simple_strtoul(argv[3], &endp, 10);
+		addr = simple_strtoul(argv[2], &endp, 16);
+		for (s = 0; s < count; s++, addr += 4) {
+			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+			sprintf(tmpbf, "%08x\n", value);
+			strcat(ssv6xxx_result_buf, tmpbf);
+		}
+		return 0;
+	}
+	return -1;
+}
+
+struct _ssv6xxx_txtput {
+	struct task_struct *txtput_tsk;
+	struct sk_buff *skb;
+	u32 size_per_frame;
+	u32 loop_times;
+	u32 occupied_tx_pages;
+};
+struct _ssv6xxx_txtput *ssv6xxx_txtput;
+struct _ssv6xxx_txtput ssv_txtput = { NULL, NULL, 0, 0, 0 };
+
+static int txtput_thread_m2(void *data)
+{
+#define Q_DELAY_MS 20
+	struct sk_buff *skb = NULL;
+	struct ssv6200_tx_desc *tx_desc;
+	int qlen = 0, max_qlen, q_delay_urange[2];
+	max_qlen =
+	    (200 * 1000 / 8 * Q_DELAY_MS) / ssv6xxx_txtput->size_per_frame;
+	q_delay_urange[0] = Q_DELAY_MS * 1000;
+	q_delay_urange[1] = q_delay_urange[0] + 1000;
+	pr_debug("max_qlen: %d\n", max_qlen);
+	while (!kthread_should_stop() && ssv6xxx_txtput->loop_times > 0) {
+		ssv6xxx_txtput->loop_times--;
+		skb = ssvdevice_skb_alloc(ssv6xxx_txtput->size_per_frame);
+		if (skb == NULL) {
+			pr_debug("ssv command txtput_generate_m2 "
+			       "ssvdevice_skb_alloc fail!!!\n");
+			goto end;
+		}
+		skb->data_len = ssv6xxx_txtput->size_per_frame;
+		skb->len = ssv6xxx_txtput->size_per_frame;
+		tx_desc = (struct ssv6200_tx_desc *)skb->data;
+		memset((void *)tx_desc, 0xff, SSV6XXX_TX_DESC_LEN);
+		tx_desc->len = skb->len;
+		tx_desc->c_type = M2_TXREQ;
+		tx_desc->fCmd = (M_ENG_CPU << 4) | M_ENG_HWHCI;
+		tx_desc->reason = ID_TRAP_SW_TXTPUT;
+		qlen = ssv_dbg_ctrl_hci->shi->hci_ops->hci_tx(skb, 0, 0);
+		if (qlen >= max_qlen) {
+			usleep_range(q_delay_urange[0], q_delay_urange[1]);
+		}
+	}
+ end:
+	ssv6xxx_txtput->txtput_tsk = NULL;
+	return 0;
+}
+
+static int txtput_thread(void *data)
+{
+	struct sk_buff *skb = ssv6xxx_txtput->skb;
+	struct ssv6xxx_hci_txq_info2 txq_info2;
+	u32 ret = 0, free_tx_page;
+	int send_cnt;
+	unsigned long start_time, end_time, throughput, time_elapse;
+	throughput =
+	    ssv6xxx_txtput->loop_times * ssv6xxx_txtput->size_per_frame * 8;
+	start_time = jiffies;
+	while (!kthread_should_stop() && ssv6xxx_txtput->loop_times > 0) {
+		ret =
+		    SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_TX_ID_ALL_INFO2,
+				  (u32 *) & txq_info2);
+		if (ret < 0) {
+			pr_debug("%s, read ADR_TX_ID_ALL_INFO2 failed\n",
+			       __func__);
+			goto end;
+		}
+		free_tx_page =
+		    SSV6200_PAGE_TX_THRESHOLD - txq_info2.tx_use_page;
+		send_cnt = free_tx_page / ssv6xxx_txtput->occupied_tx_pages;
+		while (send_cnt > 0 && ssv6xxx_txtput->loop_times > 0) {
+			send_cnt--;
+			ssv6xxx_txtput->loop_times--;
+			ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb);
+		}
+	}
+	end_time = jiffies;
+	ssvdevice_skb_free(skb);
+	time_elapse = ((end_time - start_time) * 1000) / HZ;
+	if (time_elapse > 0) {
+		throughput = throughput / time_elapse;
+		pr_debug("duration %ldms, avg. throughput %d Kbps\n", time_elapse,
+		       (int)throughput);
+	}
+ end:
+	ssv6xxx_txtput->txtput_tsk = NULL;
+	return 0;
+}
+
+int txtput_generate_m2(u32 size_per_frame, u32 loop_times)
+{
+	ssv6xxx_txtput->size_per_frame = size_per_frame;
+	ssv6xxx_txtput->loop_times = loop_times;
+	ssv6xxx_txtput->txtput_tsk =
+	    kthread_run(txtput_thread_m2, NULL, "txtput_thread_m2");
+	return 0;
+}
+
+int txtput_generate_host_cmd(u32 size_per_frame, u32 loop_times)
+{
+#define PAGESIZE 256
+	struct cfg_host_cmd *host_cmd;
+	struct sk_buff *skb;
+	skb = ssvdevice_skb_alloc(size_per_frame);
+	if (skb == NULL) {
+		pr_debug
+		    ("ssv command txtput_generate_host_cmd ssvdevice_skb_alloc fail!!!\n");
+		return 0;
+	}
+	skb->data_len = size_per_frame;
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = TEST_CMD;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_TX_TPUT;
+	host_cmd->len = skb->data_len;
+	memcpy(host_cmd->dat32, skb->data, size_per_frame);
+	ssv6xxx_txtput->occupied_tx_pages =
+	    (size_per_frame / PAGESIZE) + ((size_per_frame % PAGESIZE) != 0);
+	ssv6xxx_txtput->size_per_frame = size_per_frame;
+	ssv6xxx_txtput->loop_times = loop_times;
+	ssv6xxx_txtput->skb = skb;
+	ssv6xxx_txtput->txtput_tsk =
+	    kthread_run(txtput_thread, NULL, "txtput_thread");
+	return 0;
+}
+
+int txtput_tsk_cleanup(void)
+{
+	int ret = 0;
+	if (ssv6xxx_txtput->txtput_tsk) {
+		ret = kthread_stop(ssv6xxx_txtput->txtput_tsk);
+		ssv6xxx_txtput->txtput_tsk = NULL;
+	}
+	return ret;
+}
+
+int watchdog_controller(struct ssv_hw *sh, u8 flag)
+{
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	int ret = 0;
+	pr_debug("watchdog_controller %d\n", flag);
+	skb = ssvdevice_skb_alloc(HOST_CMD_HDR_LEN);
+	if (skb == NULL) {
+		pr_err("init watchdog_controller failure\n");
+		return (-1);
+	}
+	skb->data_len = HOST_CMD_HDR_LEN;
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) flag;
+	host_cmd->len = skb->data_len;
+	sh->hci.hci_ops->hci_send_cmd(skb);
+	ssvdevice_skb_free(skb);
+	return ret;
+}
+
+static int ssv_cmd_txtput(int argc, char *argv[])
+{
+	char tmpbf[64], *endp;
+	u32 size_per_frame, loop_times, pkt_type;
+	ssv6xxx_txtput = &ssv_txtput;
+	if (argc == 2 && !strcmp(argv[1], "stop")) {
+		txtput_tsk_cleanup();
+		return 0;
+	}
+	if (argc != 4) {
+		sprintf(tmpbf, "* txtput stop\n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		sprintf(tmpbf, "* txtput [type] [size] [frames]\n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		sprintf(tmpbf, "    type(packet type):\n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		sprintf(tmpbf, "         0 = host_cmd\n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		sprintf(tmpbf, "         1 = m2_type \n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		sprintf(tmpbf, " EX: txtput 1 14000 9999 \n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		return 0;
+	}
+	pkt_type = simple_strtoul(argv[1], &endp, 10);
+	size_per_frame = simple_strtoul(argv[2], &endp, 10);
+	loop_times = simple_strtoul(argv[3], &endp, 10);
+	sprintf(tmpbf, "type&size&frames:%d&%d&%d\n", pkt_type, size_per_frame,
+		loop_times);
+	strcat(ssv6xxx_result_buf, tmpbf);
+	if (ssv6xxx_txtput->txtput_tsk) {
+		sprintf(tmpbf, "txtput already in progress\n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		return 0;
+	}
+	watchdog_controller(((struct ssv_softc *)ssv_dbg_sc)->sh,
+			    (u8) SSV6XXX_HOST_CMD_WATCHDOG_STOP);
+	((struct ssv_softc *)ssv_dbg_sc)->watchdog_flag = WD_SLEEP;
+	if (pkt_type)
+		txtput_generate_m2(size_per_frame + SSV6XXX_TX_DESC_LEN,
+				   loop_times);
+	else
+		txtput_generate_host_cmd(size_per_frame + HOST_CMD_HDR_LEN,
+					 loop_times);
+	return 0;
+}
+
+static int ssv_cmd_rxtput(int argc, char *argv[])
+{
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	struct sdio_rxtput_cfg cmd_rxtput_cfg;
+	char tmpbf[32], *endp;
+	if (argc != 3) {
+		sprintf(ssv6xxx_result_buf, "rxtput [size] [frames]\n");
+		return 0;
+	}
+	skb =
+	    ssvdevice_skb_alloc(HOST_CMD_HDR_LEN +
+				sizeof(struct sdio_rxtput_cfg));
+	if (skb == NULL) {
+		pr_err("ssv command ssvdevice_skb_alloc fail\n");
+		return 0;
+	}
+	watchdog_controller(((struct ssv_softc *)ssv_dbg_sc)->sh,
+			    (u8) SSV6XXX_HOST_CMD_WATCHDOG_STOP);
+	((struct ssv_softc *)ssv_dbg_sc)->watchdog_flag = WD_SLEEP;
+	cmd_rxtput_cfg.size_per_frame = simple_strtoul(argv[1], &endp, 10);
+	cmd_rxtput_cfg.total_frames = simple_strtoul(argv[2], &endp, 10);
+	sprintf(tmpbf, "size&frames:%d&%d\n", cmd_rxtput_cfg.size_per_frame,
+		cmd_rxtput_cfg.total_frames);
+	strcat(ssv6xxx_result_buf, tmpbf);
+	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct sdio_rxtput_cfg);
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_RX_TPUT;
+	host_cmd->len = skb->data_len;
+	memcpy(host_cmd->dat32, &cmd_rxtput_cfg,
+	       sizeof(struct sdio_rxtput_cfg));
+	if (ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb) == 0) {
+		strcat(ssv6xxx_result_buf,
+		       "## hci cmd was sent successfully\n");
+	} else {
+		strcat(ssv6xxx_result_buf, "## hci cmd was sent failed\n");
+	}
+	ssvdevice_skb_free(skb);
+	return 0;
+}
+
+static int ssv_cmd_check(int argc, char *argv[])
+{
+	u32 size, i, j, x, y, id, value, address, id_value;
+	char *endp;
+	u32 id_base_address[4];
+	id_base_address[0] = 0xcd010008;
+	id_base_address[1] = 0xcd01000c;
+	id_base_address[2] = 0xcd010054;
+	id_base_address[3] = 0xcd010058;
+	if (argc != 2) {
+		sprintf(ssv6xxx_result_buf, "check [packet size]\n");
+		return 0;
+	}
+	size = simple_strtoul(argv[1], &endp, 10);
+	size = size >> 2;
+	for (x = 0; x < 4; x++) {
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, id_base_address[x], &id_value)) ;
+		for (y = 0; y < 32 && id_value; y++, id_value >>= 1) {
+			if (id_value & 0x1) {
+				id = 32 * x + y;
+				address = 0x80000000 + (id << 16);
+				{
+					for (i = 0; i < size; i += 8) {
+						if (SSV_REG_READ1
+						    (ssv6xxx_debug_ifops,
+						     address, &value)) ;
+						address += 4;
+						for (j = 1; j < 8; j++) {
+							if (SSV_REG_READ1
+							    (ssv6xxx_debug_ifops,
+							     address, &value)) ;
+							address += 4;
+						}
+					}
+				}
+			}
+		}
+	}
+	return 0;
+}
+
+struct ssv_cmd_table cmd_table[] = {
+	{"help", ssv_cmd_help, "ssv6200 command usage."},
+	{"-h", ssv_cmd_help, "ssv6200 command usage."},
+	{"--help", ssv_cmd_help, "ssv6200 command usage."},
+	{"reg", ssv_cmd_reg, "ssv6200 register read/write."},
+	{"cfg", ssv_cmd_cfg, "ssv6200 configuration."},
+	{"sta", ssv_cmd_sta, "svv6200 station info."},
+	{"dump", ssv_cmd_dump, "dump ssv6200 tables."},
+	{"hwq", ssv_cmd_hwq, "hardware queue staus"},
+#ifdef CONFIG_P2P_NOA
+	{"noa", ssv_cmd_noa, "config noa param"},
+#endif
+	{"irq", ssv_cmd_irq, "get sdio irq status."},
+	{"mac", ssv_cmd_mac, "ieee80211 swmac."},
+	{"hci", ssv_cmd_hci, "HCI command."},
+	{"sdio", ssv_cmd_sdio, "SDIO command."},
+	{"iqk", ssv_cmd_iqk, "iqk command"},
+	{"version", ssv_cmd_version, "version information"},
+	{"mib", ssv_cmd_mib, "mib counter related"},
+	{"tool", ssv_cmd_tool, "ssv6200 tool register read/write."},
+	{"rxtput", ssv_cmd_rxtput, "test rx sdio throughput"},
+	{"txtput", ssv_cmd_txtput, "test tx sdio throughput"},
+	{"check", ssv_cmd_check, "dump all allocate packet buffer"},
+	{NULL, NULL, NULL},
+};
+
+int ssv_cmd_submit(char *cmd)
+{
+	struct ssv_cmd_table *sc_tbl;
+	char *pch, ch;
+	int ret;
+	ssv6xxx_debug_ifops = (void *)ssv6xxx_ifdebug_info;
+	strcpy(sg_cmd_buffer, cmd);
+	for (sg_argc = 0, ch = 0, pch = sg_cmd_buffer;
+	     (*pch != 0x00) && (sg_argc < CLI_ARG_SIZE); pch++) {
+		if ((ch == 0) && (*pch != ' ')) {
+			ch = 1;
+			sg_argv[sg_argc] = pch;
+		}
+		if ((ch == 1) && (*pch == ' ')) {
+			*pch = 0x00;
+			ch = 0;
+			sg_argc++;
+		}
+	}
+	if (ch == 1) {
+		sg_argc++;
+	} else if (sg_argc > 0) {
+		*(pch - 1) = ' ';
+	}
+	if (sg_argc > 0) {
+		for (sc_tbl = cmd_table; sc_tbl->cmd; sc_tbl++) {
+			if (!strcmp(sg_argv[0], sc_tbl->cmd)) {
+				if ((sc_tbl->cmd_func_ptr != ssv_cmd_cfg) &&
+				    (!ssv6xxx_debug_ifops->dev ||
+				     !ssv6xxx_debug_ifops->ifops ||
+				     !ssv6xxx_debug_ifops->pdev)) {
+					strcpy(ssv6xxx_result_buf,
+					       "Member of ssv6xxx_ifdebug_info is NULL !\n");
+					return -1;
+				}
+				ssv6xxx_result_buf[0] = 0x00;
+				ret = sc_tbl->cmd_func_ptr(sg_argc, sg_argv);
+				if (ret < 0) {
+					strcpy(ssv6xxx_result_buf,
+					       "Invalid command !\n");
+				}
+				return 0;
+			}
+		}
+		strcpy(ssv6xxx_result_buf, "Command not found !\n");
+	} else {
+		strcpy(ssv6xxx_result_buf, "./cli -h\n");
+	}
+	return 0;
+}
diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
new file mode 100644
index 00000000000..d96bfcc5495
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_CMD_H_
+#define _SSV_CMD_H_
+#define CLI_BUFFER_SIZE 256
+#define CLI_ARG_SIZE 10
+#define CLI_RESULT_BUF_SIZE (4096)
+#define DEBUG_DIR_ENTRY "ssv"
+#define DEBUG_DEVICETYPE_ENTRY "ssv_devicetype"
+#define DEBUG_CMD_ENTRY "ssv_cmd"
+#define MAX_CHARS_PER_LINE 256
+struct ssv_cmd_table {
+	const char *cmd;
+	int (*cmd_func_ptr)(int, char **);
+	const char *usage;
+};
+struct ssv6xxx_cfg_cmd_table {
+	u8 *cfg_cmd;
+	void *var;
+	u32 arg;
+	int (*translate_func)(u8 *, void *, u32);
+};
+#define SSV_REG_READ1(ops,reg,val) \
+        (ops)->ifops->readreg((ops)->dev, reg, val)
+#define SSV_REG_WRITE1(ops,reg,val) \
+        (ops)->ifops->writereg((ops)->dev, reg, val)
+#define SSV_REG_SET_BITS1(ops,reg,set,clr) \
+    { \
+        u32 reg_val; \
+        SSV_REG_READ(ops, reg, &reg_val); \
+        reg_val &= ~(clr); \
+        reg_val |= (set); \
+        SSV_REG_WRITE(ops, reg, reg_val); \
+    }
+int ssv_cmd_submit(char *cmd);
+#endif
diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c b/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
new file mode 100644
index 00000000000..eb848553798
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/slab.h>
+#include <asm/uaccess.h>
+#include <linux/errno.h>
+#include "ssv_cmd.h"
+#include "ssv_cfg.h"
+#include <linux/fs.h>
+#include <asm/uaccess.h>
+#include <linux/buffer_head.h>
+#include <linux/ctype.h>
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+#endif
+
+char *ssv_initmac = NULL;
+EXPORT_SYMBOL(ssv_initmac);
+module_param(ssv_initmac, charp, 0644);
+MODULE_PARM_DESC(ssv_initmac, "Wi-Fi MAC address");
+
+u32 ssv_devicetype = 0;
+EXPORT_SYMBOL(ssv_devicetype);
+
+#ifdef CONFIG_DEBUG_FS
+static struct dentry *debugfs;
+#endif
+
+struct proc_dir_entry *procfs;
+static char *ssv6xxx_cmd_buf;
+char *ssv6xxx_result_buf;
+extern struct ssv6xxx_cfg_cmd_table cfg_cmds[];
+extern struct ssv6xxx_cfg ssv_cfg;
+char DEFAULT_CFG_PATH[] = "/lib/firmware/ssv6051-wifi.cfg";
+static int ssv6xxx_dbg_open(struct inode *inode, struct file *filp)
+{
+	filp->private_data = inode->i_private;
+	return 0;
+}
+
+static ssize_t ssv6xxx_dbg_read(struct file *filp, char __user * buffer,
+				size_t count, loff_t * ppos)
+{
+	int len;
+	if (*ppos != 0)
+		return 0;
+	len = strlen(ssv6xxx_result_buf) + 1;
+	if (len == 1)
+		return 0;
+	if (copy_to_user(buffer, ssv6xxx_result_buf, len))
+		return -EFAULT;
+	ssv6xxx_result_buf[0] = 0x00;
+	return len;
+}
+
+static ssize_t ssv6xxx_dbg_write(struct file *filp, const char __user * buffer,
+				 size_t count, loff_t * ppos)
+{
+	if (*ppos != 0 || count > 255)
+		return 0;
+	if (copy_from_user(ssv6xxx_cmd_buf, buffer, count))
+		return -EFAULT;
+	ssv6xxx_cmd_buf[count - 1] = 0x00;
+	ssv_cmd_submit(ssv6xxx_cmd_buf);
+	return count;
+}
+
+size_t read_line(struct file * fp, char *buf, size_t size)
+{
+	size_t num_read = 0;
+	size_t total_read = 0;
+	char *buffer;
+	char ch;
+	size_t start_ignore = 0;
+	if (size <= 0 || buf == NULL) {
+		total_read = -EINVAL;
+		return -EINVAL;
+	}
+	buffer = buf;
+	for (;;) {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
+		num_read = kernel_read(fp, &ch, 1, &fp->f_pos);
+#else
+		mm_segment_t fs;
+		fs = get_fs();
+		set_fs(KERNEL_DS);
+		num_read = vfs_read(fp, &ch, 1, &fp->f_pos);
+		set_fs(fs);
+#endif
+		if (num_read < 0) {
+			if (num_read == EINTR)
+				continue;
+			else
+				return -1;
+		} else if (num_read == 0) {
+			if (total_read == 0)
+				return 0;
+			else
+				break;
+		} else {
+			if (ch == '#')
+				start_ignore = 1;
+			if (total_read < size - 1) {
+				total_read++;
+				if (start_ignore)
+					*buffer++ = '\0';
+				else
+					*buffer++ = ch;
+			}
+			if (ch == '\n')
+				break;
+		}
+	}
+	*buffer = '\0';
+	return total_read;
+}
+
+int ischar(char *c)
+{
+	int is_char = 1;
+	while (*c) {
+		if (isalpha(*c) || isdigit(*c) || *c == '_' || *c == ':'
+		    || *c == '/' || *c == '.' || *c == '-')
+			c++;
+		else {
+			is_char = 0;
+			break;
+		}
+	}
+	return is_char;
+}
+
+void sta_cfg_set(void)
+{
+	struct file *fp = (struct file *)NULL;
+	char buf[MAX_CHARS_PER_LINE], cfg_cmd[32], cfg_value[32];
+	size_t s, read_len = 0, is_cmd_support = 0;
+
+	memset(&ssv_cfg, 0, sizeof(ssv_cfg));
+	memset(buf, 0, sizeof(buf));
+	fp = filp_open(DEFAULT_CFG_PATH, O_RDONLY, 0);
+	if (IS_ERR(fp) || fp == NULL) {
+		WARN_ON(1);
+		return;
+	}
+	if (fp->f_path.dentry == NULL) {
+		WARN_ON(1);
+		return;
+	}
+	do {
+		memset(cfg_cmd, '\0', sizeof(cfg_cmd));
+		memset(cfg_value, '\0', sizeof(cfg_value));
+		read_len = read_line(fp, buf, MAX_CHARS_PER_LINE);
+		sscanf(buf, "%s = %s", cfg_cmd, cfg_value);
+		if (!ischar(cfg_cmd) || !ischar(cfg_value)) {
+			pr_warn("Invalid configuration parameter: %s\n", buf);
+			continue;
+		}
+		is_cmd_support = 0;
+		for (s = 0; cfg_cmds[s].cfg_cmd != NULL; s++) {
+			if (strcmp(cfg_cmds[s].cfg_cmd, cfg_cmd) == 0) {
+				cfg_cmds[s].translate_func(cfg_value,
+							   cfg_cmds[s].var,
+							   cfg_cmds[s].arg);
+				is_cmd_support = 1;
+				break;
+			}
+		}
+		if (!is_cmd_support && strlen(cfg_cmd) > 0) {
+			pr_warn("Unsupported configuration command: %s", cfg_cmd);
+		}
+	} while (read_len > 0);
+	filp_close(fp, NULL);
+}
+
+static const struct file_operations ssv6xxx_dbg_fops = {
+	.owner = THIS_MODULE,
+	.open = ssv6xxx_dbg_open,
+	.read = ssv6xxx_dbg_read,
+	.write = ssv6xxx_dbg_write,
+};
+
+extern int ssv6xxx_hci_init(void);
+extern void ssv6xxx_hci_exit(void);
+extern int ssv6xxx_init(void);
+extern void ssv6xxx_exit(void);
+extern int ssv6xxx_sdio_init(void);
+extern void ssv6xxx_sdio_exit(void);
+
+int ssvdevice_init(void)
+{
+	ssv6xxx_cmd_buf =
+	    (char *)kzalloc(CLI_BUFFER_SIZE + CLI_RESULT_BUF_SIZE, GFP_KERNEL);
+	if (!ssv6xxx_cmd_buf)
+		return -ENOMEM;
+	ssv6xxx_result_buf = ssv6xxx_cmd_buf + CLI_BUFFER_SIZE;
+	ssv6xxx_cmd_buf[0] = 0x00;
+	ssv6xxx_result_buf[0] = 0x00;
+#ifdef CONFIG_DEBUG_FS
+	debugfs = debugfs_create_dir(DEBUG_DIR_ENTRY, NULL);
+	if (!debugfs)
+		return -ENOMEM;
+	debugfs_create_u32(DEBUG_DEVICETYPE_ENTRY, S_IRUGO | S_IWUSR, debugfs,
+			   &ssv_devicetype);
+	debugfs_create_file(DEBUG_CMD_ENTRY, S_IRUGO | S_IWUSR, debugfs, NULL,
+			    &ssv6xxx_dbg_fops);
+#endif
+	sta_cfg_set();
+	{
+		int ret;
+		ret = ssv6xxx_hci_init();
+		if (!ret) {
+			ret = ssv6xxx_init();
+		}
+		if (!ret) {
+			ret = ssv6xxx_sdio_init();
+		}
+		return ret;
+	}
+
+	return 0;
+}
+
+void ssvdevice_exit(void)
+{
+
+	ssv6xxx_exit();
+	ssv6xxx_hci_exit();
+	ssv6xxx_sdio_exit();
+
+#ifdef CONFIG_DEBUG_FS
+	debugfs_remove_recursive(debugfs);
+#endif
+	kfree(ssv6xxx_cmd_buf);
+}
+
+EXPORT_SYMBOL(ssvdevice_init);
+EXPORT_SYMBOL(ssvdevice_exit);
-- 
2.30.2



================================================
FILE: kernel-patch/beta/deprecated-patches/5.15.y-201-wifi-add-ssv6051-driver.patch
================================================
From 75106f4dbbc4f694a9659bf7fae0354422f009e2 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Wed, 2 Nov 2022 16:16:21 +0000
Subject: [PATCH] add ssv6xxx wifi driver

---
 drivers/net/wireless/Kconfig                  |     1 +
 drivers/net/wireless/Makefile                 |     1 +
 drivers/net/wireless/ssv6051/Kconfig          |    11 +
 drivers/net/wireless/ssv6051/Makefile         |    26 +
 drivers/net/wireless/ssv6051/Makefile.bak     |   107 +
 .../ssv6051/firmware/ssv6051-wifi.cfg         |    91 +
 drivers/net/wireless/ssv6051/hci/hctrl.h      |   178 +
 drivers/net/wireless/ssv6051/hci/ssv_hci.c    |   967 +
 drivers/net/wireless/ssv6051/hci/ssv_hci.h    |    77 +
 drivers/net/wireless/ssv6051/hwif/hwif.h      |    84 +
 drivers/net/wireless/ssv6051/hwif/sdio/sdio.c |  1254 ++
 .../net/wireless/ssv6051/hwif/sdio/sdio_def.h |    80 +
 drivers/net/wireless/ssv6051/include/cabrio.h |    28 +
 .../net/wireless/ssv6051/include/ssv6200.h    |    76 +
 .../wireless/ssv6051/include/ssv6200_aux.h    | 18221 ++++++++++++++++
 .../wireless/ssv6051/include/ssv6200_common.h |   452 +
 .../ssv6051/include/ssv6200_configuration.h   |   317 +
 .../wireless/ssv6051/include/ssv6200_reg.h    |  9694 ++++++++
 .../ssv6051/include/ssv6200_reg_sim.h         |   176 +
 .../net/wireless/ssv6051/include/ssv_cfg.h    |    60 +
 .../ssv6051/include/ssv_firmware_version.h    |    25 +
 .../wireless/ssv6051/include/ssv_version.h    |    12 +
 .../net/wireless/ssv6051/platform-config.mak  |    97 +
 drivers/net/wireless/ssv6051/rules.mak        |    19 +
 drivers/net/wireless/ssv6051/smac/ampdu.c     |  2109 ++
 drivers/net/wireless/ssv6051/smac/ampdu.h     |   215 +
 drivers/net/wireless/ssv6051/smac/ap.c        |   598 +
 drivers/net/wireless/ssv6051/smac/ap.h        |    41 +
 drivers/net/wireless/ssv6051/smac/dev.c       |  3880 ++++
 drivers/net/wireless/ssv6051/smac/dev.h       |   445 +
 drivers/net/wireless/ssv6051/smac/dev_tbl.h   |   141 +
 drivers/net/wireless/ssv6051/smac/drv_comm.h  |    61 +
 drivers/net/wireless/ssv6051/smac/efuse.c     |   334 +
 drivers/net/wireless/ssv6051/smac/efuse.h     |    40 +
 drivers/net/wireless/ssv6051/smac/init.c      |  1347 ++
 drivers/net/wireless/ssv6051/smac/init.h      |    23 +
 drivers/net/wireless/ssv6051/smac/lib.c       |    33 +
 drivers/net/wireless/ssv6051/smac/lib.h       |    23 +
 .../net/wireless/ssv6051/smac/linux_80211.h   |    24 +
 drivers/net/wireless/ssv6051/smac/p2p.c       |   305 +
 drivers/net/wireless/ssv6051/smac/p2p.h       |    58 +
 drivers/net/wireless/ssv6051/smac/sar.c       |   208 +
 drivers/net/wireless/ssv6051/smac/sar.h       |    63 +
 drivers/net/wireless/ssv6051/smac/sec.h       |    52 +
 drivers/net/wireless/ssv6051/smac/smartlink.c |   340 +
 .../wireless/ssv6051/smac/ssv6xxx_debugfs.c   |   223 +
 .../wireless/ssv6051/smac/ssv6xxx_debugfs.h   |    27 +
 .../net/wireless/ssv6051/smac/ssv_cfgvendor.c |  1384 ++
 .../net/wireless/ssv6051/smac/ssv_cfgvendor.h |   247 +
 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c |   546 +
 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h |    31 +
 drivers/net/wireless/ssv6051/smac/ssv_pm.c    |    19 +
 drivers/net/wireless/ssv6051/smac/ssv_pm.h    |    20 +
 drivers/net/wireless/ssv6051/smac/ssv_rc.c    |  1716 ++
 drivers/net/wireless/ssv6051/smac/ssv_rc.h    |    50 +
 .../net/wireless/ssv6051/smac/ssv_rc_common.h |   175 +
 .../wireless/ssv6051/ssv6051-generic-wlan.c   |    76 +
 .../net/wireless/ssv6051/ssvdevice/ssv_cmd.c  |  1765 ++
 .../net/wireless/ssv6051/ssvdevice/ssv_cmd.h  |    50 +
 .../wireless/ssv6051/ssvdevice/ssvdevice.c    |   256 +
 60 files changed, 48979 insertions(+)
 create mode 100644 drivers/net/wireless/ssv6051/Kconfig
 create mode 100644 drivers/net/wireless/ssv6051/Makefile
 create mode 100644 drivers/net/wireless/ssv6051/Makefile.bak
 create mode 100644 drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
 create mode 100644 drivers/net/wireless/ssv6051/hci/hctrl.h
 create mode 100644 drivers/net/wireless/ssv6051/hci/ssv_hci.c
 create mode 100644 drivers/net/wireless/ssv6051/hci/ssv_hci.h
 create mode 100644 drivers/net/wireless/ssv6051/hwif/hwif.h
 create mode 100644 drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
 create mode 100644 drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
 create mode 100644 drivers/net/wireless/ssv6051/include/cabrio.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_aux.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_common.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_reg.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv_cfg.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
 create mode 100644 drivers/net/wireless/ssv6051/include/ssv_version.h
 create mode 100644 drivers/net/wireless/ssv6051/platform-config.mak
 create mode 100644 drivers/net/wireless/ssv6051/rules.mak
 create mode 100644 drivers/net/wireless/ssv6051/smac/ampdu.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ampdu.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/ap.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ap.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/dev.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/dev.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/dev_tbl.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/drv_comm.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/efuse.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/efuse.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/init.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/init.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/lib.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/lib.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/linux_80211.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/p2p.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/p2p.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/sar.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/sar.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/sec.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/smartlink.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_pm.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_pm.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc.c
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc.h
 create mode 100644 drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
 create mode 100644 drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
 create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
 create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
 create mode 100644 drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c

diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
index b9a010192a8..60a9ed3ece9 100644
--- a/drivers/net/wireless/Kconfig
+++ b/drivers/net/wireless/Kconfig
@@ -18,6 +18,7 @@ menuconfig WLAN
 
 if WLAN
 
+source "drivers/net/wireless/ssv6051/Kconfig"
 source "drivers/net/wireless/admtek/Kconfig"
 source "drivers/net/wireless/ath/Kconfig"
 source "drivers/net/wireless/atmel/Kconfig"
diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
index ee8b47e953c..37b8a948cca 100644
--- a/drivers/net/wireless/Makefile
+++ b/drivers/net/wireless/Makefile
@@ -3,6 +3,7 @@
 # Makefile for the Linux Wireless network device drivers.
 #
 
+obj-$(CONFIG_SSV6051) += ssv6051/
 obj-$(CONFIG_WLAN_VENDOR_ADMTEK) += admtek/
 obj-$(CONFIG_WLAN_VENDOR_ATH) += ath/
 obj-$(CONFIG_WLAN_VENDOR_ATMEL) += atmel/
diff --git a/drivers/net/wireless/ssv6051/Kconfig b/drivers/net/wireless/ssv6051/Kconfig
new file mode 100644
index 00000000000..7706ad52ed7
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config SSV6051
+        tristate "South Silicon Valley (ssv) 6051 family WLAN support"
+	depends on MAC80211
+	depends on (MMC = y)
+        default n
+	select FW_LOADER
+        help
+		Enable South Silicon Valley (SSV) 6051 family support.
+
+
diff --git a/drivers/net/wireless/ssv6051/Makefile b/drivers/net/wireless/ssv6051/Makefile
new file mode 100644
index 00000000000..985d730f3d5
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/Makefile
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: ISC
+
+include $(src)/platform-config.mak
+
+ccflags-y += \
+	-I $(srctree)/$(src) \
+        -I $(srctree)/$(src)/include
+
+obj-$(CONFIG_SSV6051) += ssv6051.o
+ssv6051-objs += \
+	ssv6051-generic-wlan.o \
+	ssvdevice/ssvdevice.o \
+	ssvdevice/ssv_cmd.o \
+	hci/ssv_hci.o \
+	smac/init.o \
+	smac/dev.o \
+	smac/ssv_rc.o \
+	smac/ssv_ht_rc.o \
+	smac/ap.o \
+	smac/ampdu.o \
+	smac/efuse.o \
+	smac/ssv_pm.o \
+	smac/sar.o \
+	smac/ssv_cfgvendor.o \
+	hwif/sdio/sdio.o
+
diff --git a/drivers/net/wireless/ssv6051/Makefile.bak b/drivers/net/wireless/ssv6051/Makefile.bak
new file mode 100644
index 00000000000..2733fa4dd3b
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/Makefile.bak
@@ -0,0 +1,107 @@
+KMODULE_NAME=ssv6051
+
+KBUILD_TOP := $(PWD)
+
+ifeq ($(KERNELRELEASE),)
+
+KVERS_UNAME ?= $(shell uname -r)
+KVERS_ARCH ?= $(shell arch)
+
+KBUILD ?= $(shell readlink -f /lib/modules/$(KVERS_UNAME)/build)
+
+ifeq (,$(KBUILD))
+$(error kernel build tree not found - set KBUILD to configured kernel)
+endif
+
+#KCONFIG := $(KBUILD)/config
+#ifeq (,$(wildcard $(KCONFIG)))
+#$(error No .config found in $(KBUILD), set KBUILD to configured kernel)
+#endif
+
+ifneq (,$(wildcard $(KBUILD)/include/linux/version.h))
+ifneq (,$(wildcard $(KBUILD)/include/generated/uapi/linux/version.h))
+$(error Multiple copied of version.h found, clean build tree)
+endif
+endif
+
+# Kernel Makefile doesn't always know the exact kernel version, so we
+# get it from the kernel headers instead and pass it to make.
+VERSION_H := $(KBUILD)/include/generated/utsrelease.h
+ifeq (,$(wildcard $(VERSION_H)))
+VERSION_H := $(KBUILD)/include/linux/utsrelease.h
+endif
+ifeq (,$(wildcard $(VERSION_H)))
+VERSION_H := $(KBUILD)/include/linux/version.h
+endif
+ifeq (,$(wildcard $(VERSION_H)))
+$(error Please run 'make modules_prepare' in $(KBUILD))
+endif
+
+KVERS := $(shell sed -ne 's/"//g;s/^\#define UTS_RELEASE //p' $(VERSION_H))
+
+ifeq (,$(KVERS))
+$(error Cannot find UTS_RELEASE in $(VERSION_H), please report)
+endif
+
+INST_DIR = /lib/modules/$(KVERS)/misc
+
+#include $(KCONFIG)
+
+endif
+
+include $(KBUILD_TOP)/platform-config.mak
+
+EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include #-Wno-error=missing-attributes
+DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h
+
+OBJS := ssvdevice/ssvdevice.c \
+	ssvdevice/ssv_cmd.c \
+	hci/ssv_hci.c \
+	smac/init.c \
+	smac/dev.c \
+	smac/ssv_rc.c \
+	smac/ssv_ht_rc.c \
+	smac/ap.c \
+	smac/ampdu.c \
+	smac/efuse.c \
+	smac/ssv_pm.c \
+	smac/sar.c \
+	hwif/sdio/sdio.c \
+	ssv6051-generic-wlan.c
+
+ifeq ($(findstring -DCONFIG_SSV6XXX_DEBUGFS, $(ccflags-y)), -DCONFIG_SSV6XXX_DEBUGFS)
+OBJS +=	smac/ssv6xxx_debugfs.c
+endif
+
+ifeq ($(findstring -DCONFIG_SSV_VENDOR_EXT_SUPPORT, $(ccflags-y)), -DCONFIG_SSV_VENDOR_EXT_SUPPORT)
+OBJS +=	smac/ssv_cfgvendor.c
+endif
+
+ifeq ($(findstring -DCONFIG_SSV_SMARTLINK, $(ccflags-y)), -DCONFIG_SSV_SMARTLINK)
+OBJS += smac/smartlink.c
+endif
+
+$(KMODULE_NAME)-y += $(ASMS:.S=.o)
+$(KMODULE_NAME)-y += $(OBJS:.c=.o)
+
+obj-$(CONFIG_SSV6200_CORE) += $(KMODULE_NAME).o
+
+all: modules
+
+modules:
+	ARCH=arm $(MAKE) -C $(KBUILD) M=$(KBUILD_TOP)
+
+clean:
+	find -type f -iname '*.o' -exec rm {} \;
+	find -type f -iname '*.o.cmd' -exec rm {} \;
+	rm -f *.o *.ko .*.cmd *.mod.c *.symvers modules.order
+	rm -rf .tmp_versions
+
+install: modules
+	mkdir -p -m 755 $(DESTDIR)$(INST_DIR)
+	install -m 0644 $(KMODULE_NAME).ko $(DESTDIR)$(INST_DIR)
+ifndef DESTDIR
+	-/sbin/depmod -a $(KVERS)
+endif
+
+.PHONY: all modules clean install
diff --git a/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg b/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
new file mode 100644
index 00000000000..c072960f6de
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/firmware/ssv6051-wifi.cfg
@@ -0,0 +1,91 @@
+############################################################
+# ROCKCHIP RK3X28 & RK322X
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /vendor/etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+xtal_clock = 24
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ht = on
+hw_cap_gf = off
+hw_cap_2ghz = on
+hw_cap_5ghz = off
+hw_cap_security = on
+hw_cap_sgi_20 = on
+hw_cap_sgi_40 = off
+hw_cap_ap = on
+hw_cap_p2p = on
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+################################################
+# Signal strength control
+# rssi control
+#rssi_ctl = 10
+
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################
diff --git a/drivers/net/wireless/ssv6051/hci/hctrl.h b/drivers/net/wireless/ssv6051/hci/hctrl.h
new file mode 100644
index 00000000000..95218c8040e
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hci/hctrl.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _HCTRL_H_
+#define _HCTRL_H_
+#define MAX_FRAME_SIZE 4096
+#define SSV6XXX_INT_RX 0x00000001
+#define SSV6XXX_INT_TX 0x00000002
+#define SSV6XXX_INT_SOC 0x00000004
+#define SSV6XXX_INT_LOW_EDCA_0 0x00000008
+#define SSV6XXX_INT_LOW_EDCA_1 0x00000010
+#define SSV6XXX_INT_LOW_EDCA_2 0x00000020
+#define SSV6XXX_INT_LOW_EDCA_3 0x00000040
+#define SSV6XXX_INT_RESOURCE_LOW 0x00000080
+#define IFDEV(_ct) ((_ct)->shi->dev)
+#define IFOPS(_ct) ((_ct)->shi->if_ops)
+#define HCI_REG_READ(_ct,_adr,_val) IFOPS(_ct)->readreg(IFDEV(_ct), _adr, _val)
+#define HCI_REG_WRITE(_ct,_adr,_val) IFOPS(_ct)->writereg(IFDEV(_ct), _adr, _val)
+#define HCI_REG_SET_BITS(_ct,_reg,_set,_clr) \
+{ \
+    u32 _regval; \
+    if(HCI_REG_READ(_ct, _reg, &_regval)); \
+    _regval &= ~(_clr); \
+    _regval |= (_set); \
+    if(HCI_REG_WRITE(_ct, _reg, _regval)); \
+}
+#define IF_SEND(_ct,_bf,_len,_qid) IFOPS(_ct)->write(IFDEV(_ct), _bf, _len, _qid)
+#define IF_RECV(ct,bf,len) IFOPS(ct)->read(IFDEV(ct), bf, len)
+#define HCI_LOAD_FW(ct,_bf,open) IFOPS(ct)->load_fw(IFDEV(ct), _bf, open)
+#define HCI_IFC_RESET(ct) IFOPS(ct)->interface_reset(IFDEV(ct))
+struct ssv6xxx_hci_ctrl {
+	struct ssv6xxx_hci_info *shi;
+	spinlock_t int_lock;
+	u32 int_status;
+	u32 int_mask;
+	struct mutex txq_mask_lock;
+	u32 txq_mask;
+	struct ssv_hw_txq hw_txq[SSV_HW_TXQ_NUM];
+	struct mutex hci_mutex;
+	bool hci_start;
+	struct sk_buff *rx_buf;
+	u32 rx_pkt;
+	struct workqueue_struct *hci_work_queue;
+	struct work_struct hci_rx_work;
+	struct work_struct hci_tx_work;
+	u32 read_rs0_info_fail;
+	u32 read_rs1_info_fail;
+	u32 rx_work_running;
+	u32 isr_running;
+	u32 xmit_running;
+	u32 isr_summary_eable;
+	u32 isr_routine_time;
+	u32 isr_tx_time;
+	u32 isr_rx_time;
+	u32 isr_idle_time;
+	u32 isr_rx_idle_time;
+	u32 isr_miss_cnt;
+	unsigned long prev_isr_jiffes;
+	unsigned long prev_rx_isr_jiffes;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct dentry *debugfs_dir;
+	u32 isr_mib_enable;
+	u32 isr_mib_reset;
+	long long isr_total_time;
+	long long isr_tx_io_time;
+	long long isr_rx_io_time;
+	u32 isr_rx_io_count;
+	u32 isr_tx_io_count;
+	long long isr_rx_proc_time;
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+	bool irq_enable;
+	u32 irq_count;
+	u32 invalid_irq_count;
+	u32 tx_irq_count;
+	u32 real_tx_irq_count;
+	u32 rx_irq_count;
+	u32 irq_rx_pkt_count;
+	u32 irq_tx_pkt_count;
+#endif
+#endif
+};
+struct ssv6xxx_hci_txq_info {
+	u32 tx_use_page:8;
+	u32 tx_use_id:6;
+	u32 txq0_size:4;
+	u32 txq1_size:4;
+	u32 txq2_size:5;
+	u32 txq3_size:5;
+};
+struct ssv6xxx_hci_txq_info2 {
+	u32 tx_use_page:9;
+	u32 tx_use_id:8;
+	u32 txq4_size:4;
+	u32 rsvd:11;
+};
+struct ssv6xxx_hw_resource {
+	u32 free_tx_page;
+	u32 free_tx_id;
+	int max_tx_frame[SSV_HW_TXQ_NUM];
+};
+static inline void ssv6xxx_hwif_irq_request(struct ssv6xxx_hci_ctrl *hctrl,
+					    irq_handler_t irq_handler)
+{
+	if (hctrl->shi->if_ops->irq_request)
+		hctrl->shi->if_ops->irq_request(IFDEV(hctrl), irq_handler,
+						hctrl);
+}
+
+static inline void ssv6xxx_hwif_irq_enable(struct ssv6xxx_hci_ctrl *hctrl)
+{
+	if (hctrl->shi->if_ops->irq_enable)
+		hctrl->shi->if_ops->irq_enable(IFDEV(hctrl));
+}
+
+static inline void ssv6xxx_hwif_irq_disable(struct ssv6xxx_hci_ctrl *hctrl)
+{
+	if (hctrl->shi->if_ops->irq_disable)
+		hctrl->shi->if_ops->irq_disable(IFDEV(hctrl), false);
+}
+
+static inline int ssv6xxx_hwif_irq_getstatus(struct ssv6xxx_hci_ctrl *hctrl,
+					     int *status)
+{
+	if (hctrl->shi->if_ops->irq_getstatus)
+		return hctrl->shi->if_ops->irq_getstatus(IFDEV(hctrl), status);
+	return 0;
+}
+
+static inline void ssv6xxx_hwif_irq_setmask(struct ssv6xxx_hci_ctrl *hctrl,
+					    int mask)
+{
+	if (hctrl->shi->if_ops->irq_setmask)
+		hctrl->shi->if_ops->irq_setmask(IFDEV(hctrl), mask);
+}
+
+static inline void ssv6xxx_hwif_irq_trigger(struct ssv6xxx_hci_ctrl *hctrl)
+{
+	if (hctrl->shi->if_ops->irq_trigger)
+		hctrl->shi->if_ops->irq_trigger(IFDEV(hctrl));
+}
+
+static inline void ssv6xxx_hwif_pmu_wakeup(struct ssv6xxx_hci_ctrl *hctrl)
+{
+	if (hctrl->shi->if_ops->pmu_wakeup)
+		hctrl->shi->if_ops->pmu_wakeup(IFDEV(hctrl));
+}
+
+static inline int ssv6xxx_hwif_write_sram(struct ssv6xxx_hci_ctrl *hctrl,
+					  u32 addr, u8 * data, u32 size)
+{
+	if (hctrl->shi->if_ops->write_sram)
+		return hctrl->shi->if_ops->write_sram(IFDEV(hctrl), addr, data,
+						      size);
+	return 0;
+}
+
+#define HCI_IRQ_REQUEST(ct,hdle) ssv6xxx_hwif_irq_request(ct, hdle)
+#define HCI_IRQ_ENABLE(ct) ssv6xxx_hwif_irq_enable(ct)
+#define HCI_IRQ_DISABLE(ct) ssv6xxx_hwif_irq_disable(ct)
+#define HCI_IRQ_STATUS(ct,sts) ssv6xxx_hwif_irq_getstatus(ct, sts)
+#define HCI_IRQ_SET_MASK(ct,mk) ssv6xxx_hwif_irq_setmask(ct, mk)
+#define HCI_IRQ_TRIGGER(ct) ssv6xxx_hwif_irq_trigger(ct)
+#define HCI_PMU_WAKEUP(ct) ssv6xxx_hwif_pmu_wakeup(ct)
+#define HCI_SRAM_WRITE(_ct,_adr,_dat,_size) ssv6xxx_hwif_write_sram(_ct, _adr, _dat, _size);
+#endif
diff --git a/drivers/net/wireless/ssv6051/hci/ssv_hci.c b/drivers/net/wireless/ssv6051/hci/ssv_hci.c
new file mode 100644
index 00000000000..9fedbeb5575
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hci/ssv_hci.c
@@ -0,0 +1,967 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/jiffies.h>
+#include <ssv6200.h>
+#include "hctrl.h"
+
+static struct ssv6xxx_hci_ctrl *ctrl_hci = NULL;
+
+struct sk_buff *ssv_skb_alloc(s32 len)
+{
+	struct sk_buff *skb;
+	skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL);
+	if (skb != NULL) {
+		skb_reserve(skb, SSV_SKB_info_size);
+	}
+	return skb;
+}
+
+void ssv_skb_free(struct sk_buff *skb)
+{
+	dev_kfree_skb_any(skb);
+}
+
+static int ssv6xxx_hci_irq_enable(void)
+{
+	HCI_IRQ_SET_MASK(ctrl_hci, ~(ctrl_hci->int_mask));
+	HCI_IRQ_ENABLE(ctrl_hci);
+	return 0;
+}
+
+static int ssv6xxx_hci_irq_disable(void)
+{
+	HCI_IRQ_SET_MASK(ctrl_hci, 0xffffffff);
+	HCI_IRQ_DISABLE(ctrl_hci);
+	return 0;
+}
+
+static void ssv6xxx_hci_irq_register(u32 irq_mask)
+{
+	unsigned long flags;
+	u32 regval;
+	mutex_lock(&ctrl_hci->hci_mutex);
+	spin_lock_irqsave(&ctrl_hci->int_lock, flags);
+	ctrl_hci->int_mask |= irq_mask;
+	regval = ~ctrl_hci->int_mask;
+	spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+	smp_mb();
+	HCI_IRQ_SET_MASK(ctrl_hci, regval);
+	mutex_unlock(&ctrl_hci->hci_mutex);
+}
+
+static inline u32 ssv6xxx_hci_get_int_bitno(int txqid)
+{
+	if (txqid == SSV_HW_TXQ_NUM - 1)
+		return 1;
+	else
+		return txqid + 3;
+}
+
+static int ssv6xxx_hci_start(void)
+{
+	ssv6xxx_hci_irq_enable();
+	ctrl_hci->hci_start = true;
+	HCI_IRQ_TRIGGER(ctrl_hci);
+	return 0;
+}
+
+static int ssv6xxx_hci_stop(void)
+{
+	ssv6xxx_hci_irq_disable();
+	ctrl_hci->hci_start = false;
+	return 0;
+}
+
+static int ssv6xxx_hci_read_word(u32 addr, u32 * regval)
+{
+	int ret = HCI_REG_READ(ctrl_hci, addr, regval);
+	return ret;
+}
+
+static int ssv6xxx_hci_write_word(u32 addr, u32 regval)
+{
+	return HCI_REG_WRITE(ctrl_hci, addr, regval);
+}
+
+static int ssv6xxx_hci_load_fw(u8 * firmware_name, u8 openfile)
+{
+	return HCI_LOAD_FW(ctrl_hci, firmware_name, openfile);
+}
+
+static int ssv6xxx_hci_write_sram(u32 addr, u8 * data, u32 size)
+{
+	return HCI_SRAM_WRITE(ctrl_hci, addr, data, size);
+}
+
+static int ssv6xxx_hci_pmu_wakeup(void)
+{
+	HCI_PMU_WAKEUP(ctrl_hci);
+	return 0;
+}
+
+static int ssv6xxx_hci_interface_reset(void)
+{
+	HCI_IFC_RESET(ctrl_hci);
+	return 0;
+}
+
+static int ssv6xxx_hci_send_cmd(struct sk_buff *skb)
+{
+	int ret;
+	ret = IF_SEND(ctrl_hci, (void *)skb->data, skb->len, 0);
+
+	if (ret < 0)
+		pr_warn("ssv6xxx_hci_send_cmd failed, ret=%d\n", ret);
+
+	return ret;
+}
+
+static int ssv6xxx_hci_enqueue(struct sk_buff *skb, int txqid, u32 tx_flags)
+{
+	struct ssv_hw_txq *hw_txq;
+	unsigned long flags;
+	u32 status;
+	int qlen = 0;
+	BUG_ON(txqid >= SSV_HW_TXQ_NUM || txqid < 0);
+	if (txqid >= SSV_HW_TXQ_NUM || txqid < 0)
+		return -1;
+	hw_txq = &ctrl_hci->hw_txq[txqid];
+	hw_txq->tx_flags = tx_flags;
+	if (tx_flags & HCI_FLAGS_ENQUEUE_HEAD)
+		skb_queue_head(&hw_txq->qhead, skb);
+	else
+		skb_queue_tail(&hw_txq->qhead, skb);
+	qlen = (int)skb_queue_len(&hw_txq->qhead);
+	if (!(tx_flags & HCI_FLAGS_NO_FLOWCTRL)) {
+		if (skb_queue_len(&hw_txq->qhead) >= hw_txq->max_qsize) {
+			ctrl_hci->shi->hci_tx_flow_ctrl_cb(ctrl_hci->
+							   shi->tx_fctrl_cb_args,
+							   hw_txq->txq_no, true,
+							   2000);
+		}
+	}
+
+	mutex_lock(&ctrl_hci->hci_mutex);
+	spin_lock_irqsave(&ctrl_hci->int_lock, flags);
+	status = ctrl_hci->int_mask;
+
+	if ((ctrl_hci->int_mask & SSV6XXX_INT_RESOURCE_LOW) == 0) {
+		if (ctrl_hci->shi->if_ops->trigger_tx_rx == NULL) {
+			u32 regval;
+			ctrl_hci->int_mask |= SSV6XXX_INT_RESOURCE_LOW;
+			regval = ~ctrl_hci->int_mask;
+			spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+			HCI_IRQ_SET_MASK(ctrl_hci, regval);
+			mutex_unlock(&ctrl_hci->hci_mutex);
+		} else {
+			ctrl_hci->int_status |= SSV6XXX_INT_RESOURCE_LOW;
+			smp_mb();
+			spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+			mutex_unlock(&ctrl_hci->hci_mutex);
+			ctrl_hci->shi->if_ops->trigger_tx_rx(ctrl_hci->
+							     shi->dev);
+		}
+	} else {
+		spin_unlock_irqrestore(&ctrl_hci->int_lock, flags);
+		mutex_unlock(&ctrl_hci->hci_mutex);
+	}
+
+	return qlen;
+}
+
+static bool ssv6xxx_hci_is_txq_empty(int txqid)
+{
+	struct ssv_hw_txq *hw_txq;
+	BUG_ON(txqid >= SSV_HW_TXQ_NUM);
+	if (txqid >= SSV_HW_TXQ_NUM)
+		return false;
+	hw_txq = &ctrl_hci->hw_txq[txqid];
+	if (skb_queue_len(&hw_txq->qhead) <= 0)
+		return true;
+	return false;
+}
+
+static int ssv6xxx_hci_txq_flush(u32 txq_mask)
+{
+	struct ssv_hw_txq *hw_txq;
+	struct sk_buff *skb = NULL;
+	int txqid;
+	for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
+		if ((txq_mask & (1 << txqid)) != 0)
+			continue;
+		hw_txq = &ctrl_hci->hw_txq[txqid];
+		while ((skb = skb_dequeue(&hw_txq->qhead))) {
+			ctrl_hci->shi->hci_tx_buf_free_cb(skb,
+							  ctrl_hci->
+							  shi->tx_buf_free_args);
+		}
+	}
+	return 0;
+}
+
+static int ssv6xxx_hci_txq_flush_by_sta(int aid)
+{
+	return 0;
+}
+
+static int ssv6xxx_hci_txq_pause(u32 txq_mask)
+{
+	struct ssv_hw_txq *hw_txq;
+	int txqid;
+	mutex_lock(&ctrl_hci->txq_mask_lock);
+	ctrl_hci->txq_mask |= (txq_mask & 0x1F);
+	for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
+		if ((ctrl_hci->txq_mask & (1 << txqid)) == 0)
+			continue;
+		hw_txq = &ctrl_hci->hw_txq[txqid];
+		hw_txq->paused = true;
+	}
+	HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN,
+			 (ctrl_hci->txq_mask << 16), (0x1F << 16));
+	mutex_unlock(&ctrl_hci->txq_mask_lock);
+	return 0;
+}
+
+static int ssv6xxx_hci_txq_resume(u32 txq_mask)
+{
+	struct ssv_hw_txq *hw_txq;
+	int txqid;
+	mutex_lock(&ctrl_hci->txq_mask_lock);
+	ctrl_hci->txq_mask &= ~(txq_mask & 0x1F);
+	for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
+		if ((ctrl_hci->txq_mask & (1 << txqid)) != 0)
+			continue;
+		hw_txq = &ctrl_hci->hw_txq[txqid];
+		hw_txq->paused = false;
+	}
+	HCI_REG_SET_BITS(ctrl_hci, ADR_MTX_MISC_EN,
+			 (ctrl_hci->txq_mask << 16), (0x1F << 16));
+	mutex_unlock(&ctrl_hci->txq_mask_lock);
+	return 0;
+}
+
+static int ssv6xxx_hci_xmit(struct ssv_hw_txq *hw_txq, int max_count,
+			    struct ssv6xxx_hw_resource *phw_resource)
+{
+	struct sk_buff_head tx_cb_list;
+	struct sk_buff *skb = NULL;
+	int tx_count, ret, page_count;
+	struct ssv6200_tx_desc *tx_desc = NULL;
+	ctrl_hci->xmit_running = 1;
+	skb_queue_head_init(&tx_cb_list);
+	for (tx_count = 0; tx_count < max_count; tx_count++) {
+		if (ctrl_hci->hci_start == false) {
+			pr_debug("ssv6xxx_hci_xmit - hci_start = false\n");
+			goto xmit_out;
+		}
+		skb = skb_dequeue(&hw_txq->qhead);
+		if (!skb) {
+			pr_debug("ssv6xxx_hci_xmit - queue empty\n");
+			goto xmit_out;
+		}
+		page_count = (skb->len + SSV6200_ALLOC_RSVD);
+		if (page_count & HW_MMU_PAGE_MASK)
+			page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
+		else
+			page_count = page_count >> HW_MMU_PAGE_SHIFT;
+		if (page_count > (SSV6200_PAGE_TX_THRESHOLD / 2))
+			pr_err("Asking page %d(%d) exceeds resource limit %d.\n",
+			       page_count, skb->len,
+			       (SSV6200_PAGE_TX_THRESHOLD / 2));
+		if ((phw_resource->free_tx_page < page_count)
+		    || (phw_resource->free_tx_id <= 0)
+		    || (phw_resource->max_tx_frame[hw_txq->txq_no] <= 0)) {
+			skb_queue_head(&hw_txq->qhead, skb);
+			break;
+		}
+		phw_resource->free_tx_page -= page_count;
+		phw_resource->free_tx_id--;
+		phw_resource->max_tx_frame[hw_txq->txq_no]--;
+		tx_desc = (struct ssv6200_tx_desc *)skb->data;
+
+		if (ctrl_hci->shi->hci_skb_update_cb != NULL
+		    && tx_desc->reason != ID_TRAP_SW_TXTPUT) {
+			ctrl_hci->shi->hci_skb_update_cb(skb,
+							 ctrl_hci->
+							 shi->skb_update_args);
+		}
+
+		ret =
+		    IF_SEND(ctrl_hci, (void *)skb->data, skb->len,
+			    hw_txq->txq_no);
+		if (ret < 0) {
+			pr_err("ssv6xxx_hci_xmit failure\n");
+			skb_queue_head(&hw_txq->qhead, skb);
+			break;
+		}
+		if (tx_desc->reason != ID_TRAP_SW_TXTPUT)
+			skb_queue_tail(&tx_cb_list, skb);
+		else
+			ssv_skb_free(skb);
+		hw_txq->tx_pkt++;
+
+		if (!(hw_txq->tx_flags & HCI_FLAGS_NO_FLOWCTRL)) {
+			if (skb_queue_len(&hw_txq->qhead) < hw_txq->resum_thres) {
+				ctrl_hci->shi->
+				    hci_tx_flow_ctrl_cb
+				    (ctrl_hci->shi->tx_fctrl_cb_args,
+				     hw_txq->txq_no, false, 2000);
+			}
+		}
+	}
+ xmit_out:
+	if (ctrl_hci->shi->hci_tx_cb && tx_desc
+	    && tx_desc->reason != ID_TRAP_SW_TXTPUT) {
+		ctrl_hci->shi->hci_tx_cb(&tx_cb_list,
+					 ctrl_hci->shi->tx_cb_args);
+	}
+	ctrl_hci->xmit_running = 0;
+	return tx_count;
+}
+
+static int ssv6xxx_hci_tx_handler(void *dev, int max_count)
+{
+	struct ssv6xxx_hci_txq_info txq_info;
+	struct ssv6xxx_hci_txq_info2 txq_info2;
+	struct ssv6xxx_hw_resource hw_resource;
+	struct ssv_hw_txq *hw_txq = dev;
+	int ret, tx_count = 0;
+	max_count = skb_queue_len(&hw_txq->qhead);
+	if (max_count == 0)
+		return 0;
+	if (hw_txq->txq_no == 4) {
+		ret =
+		    HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO2,
+				 (u32 *) & txq_info2);
+		if (ret < 0) {
+			ctrl_hci->read_rs1_info_fail++;
+			return 0;
+		}
+		//BUG_ON(SSV6200_PAGE_TX_THRESHOLD < txq_info2.tx_use_page);
+		//BUG_ON(SSV6200_ID_TX_THRESHOLD < txq_info2.tx_use_id);
+		if (SSV6200_PAGE_TX_THRESHOLD < txq_info2.tx_use_page)
+			return 0;
+		if (SSV6200_ID_TX_THRESHOLD < txq_info2.tx_use_page)
+			return 0;
+		hw_resource.free_tx_page =
+		    SSV6200_PAGE_TX_THRESHOLD - txq_info2.tx_use_page;
+		hw_resource.free_tx_id =
+		    SSV6200_ID_TX_THRESHOLD - txq_info2.tx_use_id;
+		hw_resource.max_tx_frame[4] =
+		    SSV6200_ID_MANAGER_QUEUE - txq_info2.txq4_size;
+	} else {
+		ret =
+		    HCI_REG_READ(ctrl_hci, ADR_TX_ID_ALL_INFO,
+				 (u32 *) & txq_info);
+		if (ret < 0) {
+			ctrl_hci->read_rs0_info_fail++;
+			return 0;
+		}
+		//BUG_ON(SSV6200_PAGE_TX_THRESHOLD < txq_info.tx_use_page);
+		//BUG_ON(SSV6200_ID_TX_THRESHOLD < txq_info.tx_use_id);
+		if (SSV6200_PAGE_TX_THRESHOLD < txq_info.tx_use_page)
+			return 0;
+		if (SSV6200_ID_TX_THRESHOLD < txq_info.tx_use_page)
+			return 0;
+		hw_resource.free_tx_page =
+		    SSV6200_PAGE_TX_THRESHOLD - txq_info.tx_use_page;
+		hw_resource.free_tx_id =
+		    SSV6200_ID_TX_THRESHOLD - txq_info.tx_use_id;
+		hw_resource.max_tx_frame[0] =
+		    SSV6200_ID_AC_BK_OUT_QUEUE - txq_info.txq0_size;
+		hw_resource.max_tx_frame[1] =
+		    SSV6200_ID_AC_BE_OUT_QUEUE - txq_info.txq1_size;
+		hw_resource.max_tx_frame[2] =
+		    SSV6200_ID_AC_VI_OUT_QUEUE - txq_info.txq2_size;
+		hw_resource.max_tx_frame[3] =
+		    SSV6200_ID_AC_VO_OUT_QUEUE - txq_info.txq3_size;
+		BUG_ON(hw_resource.max_tx_frame[3] < 0);
+		BUG_ON(hw_resource.max_tx_frame[2] < 0);
+		BUG_ON(hw_resource.max_tx_frame[1] < 0);
+		BUG_ON(hw_resource.max_tx_frame[0] < 0);
+	}
+	{
+		tx_count = ssv6xxx_hci_xmit(hw_txq, max_count, &hw_resource);
+	}
+	if ((ctrl_hci->shi->hci_tx_q_empty_cb != NULL)
+	    && (skb_queue_len(&hw_txq->qhead) == 0)) {
+		ctrl_hci->shi->hci_tx_q_empty_cb(hw_txq->txq_no,
+						 ctrl_hci->
+						 shi->tx_q_empty_args);
+	}
+	return tx_count;
+}
+
+void ssv6xxx_hci_tx_work(struct work_struct *work)
+{
+	ssv6xxx_hci_irq_register(SSV6XXX_INT_RESOURCE_LOW);
+}
+
+static int _do_rx(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
+{
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+	struct sk_buff_head rx_list;
+#endif
+	struct sk_buff *rx_mpdu;
+	int rx_cnt, ret = 0;
+	size_t dlen;
+	u32 status = isr_status;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
+	struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+	skb_queue_head_init(&rx_list);
+#endif
+	for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32); rx_cnt++) {
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (hctl->isr_mib_enable)
+			getnstimeofday(&rx_io_start_time);
+#endif
+		ret = IF_RECV(hctl, hctl->rx_buf->data, &dlen);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (hctl->isr_mib_enable)
+			getnstimeofday(&rx_io_end_time);
+#endif
+		if (ret < 0 || dlen <= 0) {
+			pr_warn("%s(): IF_RECV() retruns %d (dlen=%d)\n",
+			       __FUNCTION__, ret, (int)dlen);
+			if (ret != -84 || dlen > MAX_FRAME_SIZE)
+				break;
+		}
+		rx_mpdu = hctl->rx_buf;
+		hctl->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
+		if (hctl->rx_buf == NULL) {
+			pr_err("RX buffer allocation failure!\n");
+			hctl->rx_buf = rx_mpdu;
+			break;
+		}
+		hctl->rx_pkt++;
+		skb_put(rx_mpdu, dlen);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (hctl->isr_mib_enable)
+			getnstimeofday(&rx_proc_start_time);
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+		__skb_queue_tail(&rx_list, rx_mpdu);
+#else
+		hctl->shi->hci_rx_cb(rx_mpdu, hctl->shi->rx_cb_args);
+#endif
+		HCI_IRQ_STATUS(hctl, &status);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (hctl->isr_mib_enable) {
+			getnstimeofday(&rx_proc_end_time);
+			hctl->isr_rx_io_count++;
+			rx_io_diff_time =
+			    timespec_sub(rx_io_end_time, rx_io_start_time);
+			hctl->isr_rx_io_time +=
+			    timespec_to_ns(&rx_io_diff_time);
+			rx_proc_diff_time =
+			    timespec_sub(rx_proc_end_time, rx_proc_start_time);
+			hctl->isr_rx_proc_time +=
+			    timespec_to_ns(&rx_proc_diff_time);
+		}
+#endif
+	}
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	if (hctl->isr_mib_enable)
+		getnstimeofday(&rx_proc_start_time);
+#endif
+	hctl->shi->hci_rx_cb(&rx_list, hctl->shi->rx_cb_args);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	if (hctl->isr_mib_enable) {
+		getnstimeofday(&rx_proc_end_time);
+		rx_proc_diff_time =
+		    timespec_sub(rx_proc_end_time, rx_proc_start_time);
+		hctl->isr_rx_proc_time += timespec_to_ns(&rx_proc_diff_time);
+	}
+#endif
+#endif
+	return ret;
+}
+
+static void ssv6xxx_hci_rx_work(struct work_struct *work)
+{
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+	struct sk_buff_head rx_list;
+#endif
+	struct sk_buff *rx_mpdu;
+	int rx_cnt, ret;
+	size_t dlen;
+	u32 status;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct timespec rx_io_start_time, rx_io_end_time, rx_io_diff_time;
+	struct timespec rx_proc_start_time, rx_proc_end_time, rx_proc_diff_time;
+#endif
+	ctrl_hci->rx_work_running = 1;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+	skb_queue_head_init(&rx_list);
+#endif
+	status = SSV6XXX_INT_RX;
+	for (rx_cnt = 0; (status & SSV6XXX_INT_RX) && (rx_cnt < 32); rx_cnt++) {
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (ctrl_hci->isr_mib_enable)
+			getnstimeofday(&rx_io_start_time);
+#endif
+		ret = IF_RECV(ctrl_hci, ctrl_hci->rx_buf->data, &dlen);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (ctrl_hci->isr_mib_enable)
+			getnstimeofday(&rx_io_end_time);
+#endif
+		if (ret < 0 || dlen <= 0) {
+			pr_warn("%s(): IF_RECV() retruns %d (dlen=%d)\n",
+			       __FUNCTION__, ret, (int)dlen);
+			if (ret != -84 || dlen > MAX_FRAME_SIZE)
+				break;
+		}
+		rx_mpdu = ctrl_hci->rx_buf;
+		ctrl_hci->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
+		if (ctrl_hci->rx_buf == NULL) {
+			pr_err("RX buffer allocation failure!\n");
+			ctrl_hci->rx_buf = rx_mpdu;
+			break;
+		}
+		ctrl_hci->rx_pkt++;
+		skb_put(rx_mpdu, dlen);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (ctrl_hci->isr_mib_enable)
+			getnstimeofday(&rx_proc_start_time);
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+		__skb_queue_tail(&rx_list, rx_mpdu);
+#else
+		ctrl_hci->shi->hci_rx_cb(rx_mpdu, ctrl_hci->shi->rx_cb_args);
+#endif
+		HCI_IRQ_STATUS(ctrl_hci, &status);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (ctrl_hci->isr_mib_enable) {
+			getnstimeofday(&rx_proc_end_time);
+			ctrl_hci->isr_rx_io_count++;
+			rx_io_diff_time =
+			    timespec_sub(rx_io_end_time, rx_io_start_time);
+			ctrl_hci->isr_rx_io_time +=
+			    timespec_to_ns(&rx_io_diff_time);
+			rx_proc_diff_time =
+			    timespec_sub(rx_proc_end_time, rx_proc_start_time);
+			ctrl_hci->isr_rx_proc_time +=
+			    timespec_to_ns(&rx_proc_diff_time);
+		}
+#endif
+	}
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	if (ctrl_hci->isr_mib_enable)
+		getnstimeofday(&rx_proc_start_time);
+#endif
+	ctrl_hci->shi->hci_rx_cb(&rx_list, ctrl_hci->shi->rx_cb_args);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	if (ctrl_hci->isr_mib_enable) {
+		getnstimeofday(&rx_proc_end_time);
+		rx_proc_diff_time =
+		    timespec_sub(rx_proc_end_time, rx_proc_start_time);
+		ctrl_hci->isr_rx_proc_time +=
+		    timespec_to_ns(&rx_proc_diff_time);
+	}
+#endif
+#endif
+	ctrl_hci->rx_work_running = 0;
+}
+
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+static void ssv6xxx_isr_mib_reset(void)
+{
+	ctrl_hci->isr_mib_reset = 0;
+	ctrl_hci->isr_total_time = 0;
+	ctrl_hci->isr_rx_io_time = 0;
+	ctrl_hci->isr_tx_io_time = 0;
+	ctrl_hci->isr_rx_io_count = 0;
+	ctrl_hci->isr_tx_io_count = 0;
+	ctrl_hci->isr_rx_proc_time = 0;
+}
+
+static int hw_txq_len_open(struct inode *inode, struct file *filp)
+{
+	filp->private_data = inode->i_private;
+	return 0;
+}
+
+static ssize_t hw_txq_len_read(struct file *filp, char __user * buffer,
+			       size_t count, loff_t * ppos)
+{
+	ssize_t ret;
+	struct ssv6xxx_hci_ctrl *hctl =
+	    (struct ssv6xxx_hci_ctrl *)filp->private_data;
+	char *summary_buf = kzalloc(1024, GFP_KERNEL);
+	char *prn_ptr = summary_buf;
+	int prt_size;
+	int buf_size = 1024;
+	int i = 0;
+	if (!summary_buf)
+		return -ENOMEM;
+	for (i = 0; i < SSV_HW_TXQ_NUM; i++) {
+		prt_size =
+		    snprintf(prn_ptr, buf_size, "\n\rhw_txq%d_len: %d", i,
+			     skb_queue_len(&hctl->hw_txq[i].qhead));
+		prn_ptr += prt_size;
+		buf_size -= prt_size;
+	}
+	buf_size = 1024 - buf_size;
+	ret =
+	    simple_read_from_buffer(buffer, count, ppos, summary_buf, buf_size);
+	kfree(summary_buf);
+	return ret;
+}
+
+struct file_operations hw_txq_len_fops = {
+	.owner = THIS_MODULE,
+	.open = hw_txq_len_open,
+	.read = hw_txq_len_read,
+};
+
+bool ssv6xxx_hci_init_debugfs(struct dentry *dev_deugfs_dir)
+{
+	ctrl_hci->debugfs_dir = debugfs_create_dir("hci", dev_deugfs_dir);
+	if (ctrl_hci->debugfs_dir == NULL) {
+		dev_err(ctrl_hci->shi->dev,
+			"Failed to create HCI debugfs directory.\n");
+		return false;
+	}
+	debugfs_create_u32("TXQ_mask", 00444, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->txq_mask);
+	debugfs_create_u32("hci_isr_mib_enable", 00644, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_mib_enable);
+	debugfs_create_u32("hci_isr_mib_reset", 00644, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_mib_reset);
+	debugfs_create_u64("isr_total_time", 00444, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_total_time);
+	debugfs_create_u64("tx_io_time", 00444, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_tx_io_time);
+	debugfs_create_u64("rx_io_time", 00444, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_rx_io_time);
+	debugfs_create_u32("tx_io_count", 00444, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_tx_io_count);
+	debugfs_create_u32("rx_io_count", 00444, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_rx_io_count);
+	debugfs_create_u64("rx_proc_time", 00444, ctrl_hci->debugfs_dir,
+			   &ctrl_hci->isr_rx_proc_time);
+	debugfs_create_file("hw_txq_len", 00444, ctrl_hci->debugfs_dir,
+			    ctrl_hci, &hw_txq_len_fops);
+	return true;
+}
+
+void ssv6xxx_hci_deinit_debugfs(void)
+{
+	if (ctrl_hci->debugfs_dir == NULL)
+		return;
+	ctrl_hci->debugfs_dir = NULL;
+}
+#endif
+static int _isr_do_rx(struct ssv6xxx_hci_ctrl *hctl, u32 isr_status)
+{
+	int status;
+	u32 before = jiffies;
+
+	if (hctl->isr_summary_eable && hctl->prev_rx_isr_jiffes) {
+		if (hctl->isr_rx_idle_time) {
+			hctl->isr_rx_idle_time +=
+			    (jiffies - hctl->prev_rx_isr_jiffes);
+			hctl->isr_rx_idle_time = hctl->isr_rx_idle_time >> 1;
+		} else {
+			hctl->isr_rx_idle_time +=
+			    (jiffies - hctl->prev_rx_isr_jiffes);
+		}
+	}
+	status = _do_rx(hctl, isr_status);
+	if (hctl->isr_summary_eable) {
+		if (hctl->isr_rx_time) {
+			hctl->isr_rx_time += (jiffies - before);
+			hctl->isr_rx_time = hctl->isr_rx_time >> 1;
+		} else {
+			hctl->isr_rx_time += (jiffies - before);
+		}
+		hctl->prev_rx_isr_jiffes = jiffies;
+	}
+	return status;
+}
+
+static int _do_tx(struct ssv6xxx_hci_ctrl *hctl, u32 status)
+{
+	int q_num;
+	int tx_count = 0;
+	u32 to_disable_int = 1;
+	unsigned long flags;
+	struct ssv_hw_txq *hw_txq;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct timespec tx_io_start_time, tx_io_end_time, tx_io_diff_time;
+#endif
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+	if ((!(status & SSV6XXX_INT_RX)) && htcl->irq_enable)
+		hctl->tx_irq_count++;
+#endif
+	if ((status & SSV6XXX_INT_RESOURCE_LOW) == 0)
+		return 0;
+	for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
+		u32 before = jiffies;
+		hw_txq = &hctl->hw_txq[q_num];
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (hctl->isr_mib_enable)
+			getnstimeofday(&tx_io_start_time);
+#endif
+		tx_count += ssv6xxx_hci_tx_handler(hw_txq, 999);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (hctl->isr_mib_enable) {
+			getnstimeofday(&tx_io_end_time);
+			tx_io_diff_time =
+			    timespec_sub(tx_io_end_time, tx_io_start_time);
+			hctl->isr_tx_io_time +=
+			    timespec_to_ns(&tx_io_diff_time);
+		}
+#endif
+		if (hctl->isr_summary_eable) {
+			if (hctl->isr_tx_time) {
+				hctl->isr_tx_time += (jiffies - before);
+				hctl->isr_tx_time = hctl->isr_tx_time >> 1;
+			} else {
+				hctl->isr_tx_time += (jiffies - before);
+			}
+		}
+	}
+	mutex_lock(&hctl->hci_mutex);
+	spin_lock_irqsave(&hctl->int_lock, flags);
+	for (q_num = (SSV_HW_TXQ_NUM - 1); q_num >= 0; q_num--) {
+		hw_txq = &hctl->hw_txq[q_num];
+		if (skb_queue_len(&hw_txq->qhead) > 0) {
+			to_disable_int = 0;
+			break;
+		}
+	}
+	if (to_disable_int) {
+		u32 reg_val;
+		hctl->int_mask &= ~(SSV6XXX_INT_RESOURCE_LOW | SSV6XXX_INT_TX);
+		reg_val = ~hctl->int_mask;
+		spin_unlock_irqrestore(&hctl->int_lock, flags);
+		HCI_IRQ_SET_MASK(hctl, reg_val);
+	} else {
+		spin_unlock_irqrestore(&hctl->int_lock, flags);
+	}
+	mutex_unlock(&hctl->hci_mutex);
+	return tx_count;
+}
+
+irqreturn_t ssv6xxx_hci_isr(int irq, void *args)
+{
+	struct ssv6xxx_hci_ctrl *hctl = args;
+	u32 status;
+	unsigned long flags;
+	int ret = IRQ_HANDLED;
+	bool dbg_isr_miss = true;
+	if (ctrl_hci->isr_summary_eable && ctrl_hci->prev_isr_jiffes) {
+		if (ctrl_hci->isr_idle_time) {
+			ctrl_hci->isr_idle_time +=
+			    (jiffies - ctrl_hci->prev_isr_jiffes);
+			ctrl_hci->isr_idle_time = ctrl_hci->isr_idle_time >> 1;
+		} else {
+			ctrl_hci->isr_idle_time +=
+			    (jiffies - ctrl_hci->prev_isr_jiffes);
+		}
+	}
+	BUG_ON(!args);
+	do {
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		struct timespec start_time, end_time, diff_time;
+		if (hctl->isr_mib_reset)
+			ssv6xxx_isr_mib_reset();
+		if (hctl->isr_mib_enable)
+			getnstimeofday(&start_time);
+#endif
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+		if (ctrl_hci->irq_enable)
+			ctrl_hci->irq_count++;
+#endif
+		mutex_lock(&hctl->hci_mutex);
+		if (hctl->int_status) {
+			u32 regval;
+			spin_lock_irqsave(&hctl->int_lock, flags);
+			hctl->int_mask |= hctl->int_status;
+			hctl->int_status = 0;
+			regval = ~ctrl_hci->int_mask;
+			smp_mb();
+			spin_unlock_irqrestore(&hctl->int_lock, flags);
+			HCI_IRQ_SET_MASK(hctl, regval);
+		}
+		ret = HCI_IRQ_STATUS(hctl, &status);
+		if ((ret < 0) || ((status & hctl->int_mask) == 0)) {
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+			if (ctrl_hci->irq_enable)
+				ctrl_hci->invalid_irq_count++;
+#endif
+			mutex_unlock(&hctl->hci_mutex);
+			ret = IRQ_NONE;
+			break;
+		}
+		spin_lock_irqsave(&hctl->int_lock, flags);
+		status &= hctl->int_mask;
+		spin_unlock_irqrestore(&hctl->int_lock, flags);
+		mutex_unlock(&hctl->hci_mutex);
+		ctrl_hci->isr_running = 1;
+		if (status & SSV6XXX_INT_RX) {
+			ret = _isr_do_rx(hctl, status);
+			if (ret < 0) {
+				ret = IRQ_NONE;
+				break;
+			}
+			dbg_isr_miss = false;
+		}
+		if (_do_tx(hctl, status)) {
+			dbg_isr_miss = false;
+		}
+		ctrl_hci->isr_running = 0;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		if (ctrl_hci->isr_mib_enable) {
+			getnstimeofday(&end_time);
+			diff_time = timespec_sub(end_time, start_time);
+			ctrl_hci->isr_total_time += timespec_to_ns(&diff_time);
+		}
+#endif
+	} while (1);
+	if (ctrl_hci->isr_summary_eable) {
+		if (dbg_isr_miss)
+			ctrl_hci->isr_miss_cnt++;
+		ctrl_hci->prev_isr_jiffes = jiffies;
+	}
+	return ret;
+}
+
+static struct ssv6xxx_hci_ops hci_ops = {
+	.hci_start = ssv6xxx_hci_start,
+	.hci_stop = ssv6xxx_hci_stop,
+	.hci_read_word = ssv6xxx_hci_read_word,
+	.hci_write_word = ssv6xxx_hci_write_word,
+	.hci_tx = ssv6xxx_hci_enqueue,
+	.hci_tx_pause = ssv6xxx_hci_txq_pause,
+	.hci_tx_resume = ssv6xxx_hci_txq_resume,
+	.hci_txq_flush = ssv6xxx_hci_txq_flush,
+	.hci_txq_flush_by_sta = ssv6xxx_hci_txq_flush_by_sta,
+	.hci_txq_empty = ssv6xxx_hci_is_txq_empty,
+	.hci_load_fw = ssv6xxx_hci_load_fw,
+	.hci_pmu_wakeup = ssv6xxx_hci_pmu_wakeup,
+	.hci_send_cmd = ssv6xxx_hci_send_cmd,
+	.hci_write_sram = ssv6xxx_hci_write_sram,
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	.hci_init_debugfs = ssv6xxx_hci_init_debugfs,
+	.hci_deinit_debugfs = ssv6xxx_hci_deinit_debugfs,
+#endif
+	.hci_interface_reset = ssv6xxx_hci_interface_reset,
+};
+
+int ssv6xxx_hci_deregister(void)
+{
+	u32 regval;
+	pr_debug("%s(): \n", __FUNCTION__);
+	if (ctrl_hci->shi == NULL)
+		return -1;
+	regval = 1;
+	ssv6xxx_hci_irq_disable();
+	flush_workqueue(ctrl_hci->hci_work_queue);
+	destroy_workqueue(ctrl_hci->hci_work_queue);
+	ctrl_hci->shi = NULL;
+	return 0;
+}
+
+EXPORT_SYMBOL(ssv6xxx_hci_deregister);
+int ssv6xxx_hci_register(struct ssv6xxx_hci_info *shi)
+{
+	int i;
+	if (shi == NULL || ctrl_hci->shi)
+		return -1;
+	shi->hci_ops = &hci_ops;
+	ctrl_hci->shi = shi;
+	ctrl_hci->txq_mask = 0;
+	mutex_init(&ctrl_hci->txq_mask_lock);
+	mutex_init(&ctrl_hci->hci_mutex);
+	spin_lock_init(&ctrl_hci->int_lock);
+
+	for (i = 0; i < SSV_HW_TXQ_NUM; i++) {
+		memset(&ctrl_hci->hw_txq[i], 0, sizeof(struct ssv_hw_txq));
+		skb_queue_head_init(&ctrl_hci->hw_txq[i].qhead);
+		ctrl_hci->hw_txq[i].txq_no = (u32) i;
+		ctrl_hci->hw_txq[i].max_qsize = SSV_HW_TXQ_MAX_SIZE;
+		ctrl_hci->hw_txq[i].resum_thres = SSV_HW_TXQ_RESUME_THRES;
+	}
+	ctrl_hci->hci_work_queue =
+	    create_singlethread_workqueue("ssv6xxx_hci_wq");
+	INIT_WORK(&ctrl_hci->hci_rx_work, ssv6xxx_hci_rx_work);
+	INIT_WORK(&ctrl_hci->hci_tx_work, ssv6xxx_hci_tx_work);
+	ctrl_hci->int_mask = SSV6XXX_INT_RX | SSV6XXX_INT_RESOURCE_LOW;
+	ctrl_hci->int_status = 0;
+	HCI_IRQ_SET_MASK(ctrl_hci, 0xFFFFFFFF);
+	ssv6xxx_hci_irq_disable();
+	HCI_IRQ_REQUEST(ctrl_hci, ssv6xxx_hci_isr);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	ctrl_hci->debugfs_dir = NULL;
+	ctrl_hci->isr_mib_enable = false;
+	ctrl_hci->isr_mib_reset = 0;
+	ctrl_hci->isr_total_time = 0;
+	ctrl_hci->isr_rx_io_time = 0;
+	ctrl_hci->isr_tx_io_time = 0;
+	ctrl_hci->isr_rx_io_count = 0;
+	ctrl_hci->isr_tx_io_count = 0;
+	ctrl_hci->isr_rx_proc_time = 0;
+#endif
+	return 0;
+}
+
+EXPORT_SYMBOL(ssv6xxx_hci_register);
+int ssv6xxx_hci_init(void)
+{
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+	extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
+#endif
+	ctrl_hci = kzalloc(sizeof(*ctrl_hci), GFP_KERNEL);
+	if (ctrl_hci == NULL)
+		return -ENOMEM;
+	memset((void *)ctrl_hci, 0, sizeof(*ctrl_hci));
+	ctrl_hci->rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
+	if (ctrl_hci->rx_buf == NULL) {
+		kfree(ctrl_hci);
+		return -ENOMEM;
+	}
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+	ssv_dbg_ctrl_hci = ctrl_hci;
+#endif
+	return 0;
+}
+
+void ssv6xxx_hci_exit(void)
+{
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+	extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
+#endif
+	kfree(ctrl_hci);
+	ctrl_hci = NULL;
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+	ssv_dbg_ctrl_hci = NULL;
+#endif
+}
+
+EXPORT_SYMBOL(ssv6xxx_hci_init);
+EXPORT_SYMBOL(ssv6xxx_hci_exit);
diff --git a/drivers/net/wireless/ssv6051/hci/ssv_hci.h b/drivers/net/wireless/ssv6051/hci/ssv_hci.h
new file mode 100644
index 00000000000..dd166c607d5
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hci/ssv_hci.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_HCI_H_
+#define _SSV_HCI_H_
+#define SSV_HW_TXQ_NUM 5
+#define SSV_HW_TXQ_MAX_SIZE 64
+#define SSV_HW_TXQ_RESUME_THRES ((SSV_HW_TXQ_MAX_SIZE >> 2) *3)
+#define HCI_FLAGS_ENQUEUE_HEAD 0x00000001
+#define HCI_FLAGS_NO_FLOWCTRL 0x00000002
+struct ssv_hw_txq {
+	u32 txq_no;
+	struct sk_buff_head qhead;
+	int max_qsize;
+	int resum_thres;
+	bool paused;
+	u32 tx_pkt;
+	u32 tx_flags;
+};
+struct ssv6xxx_hci_ops {
+	int (*hci_start)(void);
+	int (*hci_stop)(void);
+	int (*hci_read_word)(u32 addr, u32 * regval);
+	int (*hci_write_word)(u32 addr, u32 regval);
+	int (*hci_load_fw)(u8 * firmware_name, u8 openfile);
+	int (*hci_tx)(struct sk_buff *, int, u32);
+	int (*hci_tx_pause)(u32 txq_mask);
+	int (*hci_tx_resume)(u32 txq_mask);
+	int (*hci_txq_flush)(u32 txq_mask);
+	int (*hci_txq_flush_by_sta)(int aid);
+	bool (*hci_txq_empty)(int txqid);
+	int (*hci_pmu_wakeup)(void);
+	int (*hci_send_cmd)(struct sk_buff *);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	bool (*hci_init_debugfs)(struct dentry * dev_deugfs_dir);
+	void (*hci_deinit_debugfs)(void);
+#endif
+	int (*hci_write_sram)(u32 addr, u8 * data, u32 size);
+	int (*hci_interface_reset)(void);
+};
+struct ssv6xxx_hci_info {
+	struct device *dev;
+	struct ssv6xxx_hwif_ops *if_ops;
+	struct ssv6xxx_hci_ops *hci_ops;
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+	int (*hci_rx_cb)(struct sk_buff_head *, void *);
+#else
+	int (*hci_rx_cb)(struct sk_buff *, void *);
+#endif
+	void *rx_cb_args;
+	void (*hci_tx_cb)(struct sk_buff_head *, void *);
+	void *tx_cb_args;
+	int (*hci_tx_flow_ctrl_cb)(void *, int, bool, int debug);
+	void *tx_fctrl_cb_args;
+	void (*hci_tx_buf_free_cb)(struct sk_buff *, void *);
+	void *tx_buf_free_args;
+	void (*hci_skb_update_cb)(struct sk_buff *, void *);
+	void *skb_update_args;
+	void (*hci_tx_q_empty_cb)(u32 txq_no, void *);
+	void *tx_q_empty_args;
+};
+int ssv6xxx_hci_deregister(void);
+int ssv6xxx_hci_register(struct ssv6xxx_hci_info *);
+#endif
diff --git a/drivers/net/wireless/ssv6051/hwif/hwif.h b/drivers/net/wireless/ssv6051/hwif/hwif.h
new file mode 100644
index 00000000000..6b5263d157d
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hwif/hwif.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _LINUX_SSVCABRIO_PLATFORM_H
+#define _LINUX_SSVCABRIO_PLATFORM_H 
+#include <linux/mmc/host.h>
+#include <hwif/sdio/sdio_def.h>
+#define SSVCABRIO_PLAT_EEP_MAX_WORDS 2048
+#define SSV_REG_WRITE(dev,reg,val) \
+        (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
+#define SSV_REG_READ(dev,reg,buf) \
+        (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
+#if 0
+#define SSV_REG_WRITE(sh,reg,val) \
+        (sh)->priv->ops->writereg((sh)->sc->dev, (reg), (val))
+#define SSV_REG_READ(sh,reg,buf) \
+        (sh)->priv->ops->readreg((sh)->sc->dev, (reg), (buf))
+#define SSV_REG_CONFIRM(sh,reg,val) \
+{ \
+    u32 regval; \
+    SSV_REG_READ(sh, reg, &regval); \
+    if (regval != (val)) { \
+        printk("[0x%08x]: 0x%08x!=0x%08x\n",\
+        (reg), (val), regval); \
+        return -1; \
+    } \
+}
+#define SSV_REG_SET_BITS(sh,reg,set,clr) \
+{ \
+    u32 reg_val; \
+    SSV_REG_READ(sh, reg, &reg_val); \
+    reg_val &= ~(clr); \
+    reg_val |= (set); \
+    SSV_REG_WRITE(sh, reg, reg_val); \
+}
+#endif
+struct ssv6xxx_hwif_ops {
+    int __must_check (*read)(struct device *child, void *buf,size_t *size);
+    int __must_check (*write)(struct device *child, void *buf, size_t len,u8 queue_num);
+    int __must_check (*readreg)(struct device *child, u32 addr, u32 *buf);
+    int __must_check (*writereg)(struct device *child, u32 addr, u32 buf);
+    int (*trigger_tx_rx)(struct device *child);
+    int (*irq_getmask)(struct device *child, u32 *mask);
+    void (*irq_setmask)(struct device *child,int mask);
+    void (*irq_enable)(struct device *child);
+    void (*irq_disable)(struct device *child,bool iswaitirq);
+    int (*irq_getstatus)(struct device *child,int *status);
+    void (*irq_request)(struct device *child,irq_handler_t irq_handler,void *irq_dev);
+    void (*irq_trigger)(struct device *child);
+    void (*pmu_wakeup)(struct device *child);
+    int __must_check (*load_fw)(struct device *child, u8 *firmware_name, u8 openfile);
+    int (*cmd52_read)(struct device *child, u32 addr, u32 *value);
+    int (*cmd52_write)(struct device *child, u32 addr, u32 value);
+    bool (*support_scatter)(struct device *child);
+    int (*rw_scatter)(struct device *child, struct sdio_scatter_req *scat_req);
+    bool (*is_ready)(struct device *child);
+    int (*write_sram)(struct device *child, u32 addr, u8 *data, u32 size);
+    void (*interface_reset)(struct device *child);
+};
+struct ssv6xxx_if_debug {
+    struct device *dev;
+    struct platform_device *pdev;
+};
+struct ssv6xxx_platform_data {
+    atomic_t irq_handling;
+    bool is_enabled;
+    unsigned short vendor;
+    unsigned short device;
+    struct ssv6xxx_hwif_ops *ops;
+};
+#endif
diff --git a/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c b/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
new file mode 100644
index 00000000000..273777cd048
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hwif/sdio/sdio.c
@@ -0,0 +1,1254 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/sdio.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include "sdio_def.h"
+#include <linux/pm_runtime.h>
+#include <linux/version.h>
+#include <linux/firmware.h>
+#include <linux/reboot.h>
+#include <ssv6200.h>
+#include <linux/skbuff.h>
+
+#define LOW_SPEED_SDIO_CLOCK (25000000)
+#define HIGH_SPEED_SDIO_CLOCK (37500000)
+#define MAX_RX_FRAME_SIZE 0x900
+#define SSV_VENDOR_ID 0x3030
+#define SSV_CABRIO_DEVID 0x3030
+#define ENABLE_FW_SELF_CHECK 1
+#define FW_BLOCK_SIZE 0x8000
+#define CHECKSUM_BLOCK_SIZE 1024
+#define FW_CHECKSUM_INIT (0x12345678)
+#define FW_STATUS_REG ADR_TX_SEG
+#define FW_STATUS_MASK (0x00FF0000)
+
+#define ret_if_not_ready(value) \
+    do { \
+    if ((wlan_data.is_enabled == false) || \
+        (glue == NULL) || (glue->dev_ready == false)) { \
+        pr_warn("ret_if_not_ready() called when not ready"); \
+        return value; }\
+    } while(0)
+
+static int ssv6xxx_sdio_trigger_pmu(struct device *dev);
+static void ssv6xxx_sdio_reset(struct device *child);
+
+static void ssv6xxx_high_sdio_clk(struct sdio_func *func);
+static void ssv6xxx_low_sdio_clk(struct sdio_func *func);
+extern void *ssv6xxx_ifdebug_info[];
+extern int ssv_devicetype;
+extern void ssv6xxx_deinit_prepare(void);
+
+static struct ssv6xxx_platform_data wlan_data;
+
+static int ssv6xxx_sdio_status = 0;
+u32 sdio_sr_bhvr = SUSPEND_RESUME_0;
+EXPORT_SYMBOL(sdio_sr_bhvr);
+
+u32 shutdown_flags = SSV_SYS_REBOOT;
+
+struct ssv6xxx_sdio_glue {
+	struct device *dev;
+	struct platform_device *core;
+	struct sk_buff *dma_skb;
+#ifdef CONFIG_PM
+	struct sk_buff *cmd_skb;
+#endif
+	unsigned int ioport_data;
+	unsigned int ioport_reg;
+	irq_handler_t irq_handler;
+	void *irq_dev;
+	bool dev_ready;
+};
+
+static const struct sdio_device_id ssv6xxx_sdio_devices[] = {
+	{SDIO_DEVICE(SSV_VENDOR_ID, SSV_CABRIO_DEVID)},
+	{}
+};
+
+MODULE_DEVICE_TABLE(sdio, ssv6xxx_sdio_devices);
+
+static bool ssv6xxx_is_ready(struct device *child)
+{
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+
+	ret_if_not_ready(false);
+
+	return true;
+}
+
+static int ssv6xxx_sdio_cmd52_read(struct device *child, u32 addr, u32 * value)
+{
+	int ret;
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+	ret_if_not_ready(-1);
+
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    *value = sdio_readb(func, addr, &ret);
+    sdio_release_host(func);
+
+	return ret;
+}
+
+static int ssv6xxx_sdio_cmd52_write(struct device *child, u32 addr, u32 value)
+{
+	int ret;
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+    ret_if_not_ready(-1);
+
+	func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    sdio_writeb(func, value, addr, &ret);
+    sdio_release_host(func);
+
+	return ret;
+}
+
+static int __must_check
+ssv6xxx_sdio_read_reg(struct device *child, u32 addr, u32 * buf)
+{
+	int ret;
+
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+	u32 data;
+
+    ret_if_not_ready(-1);
+
+    func = dev_to_sdio_func(glue->dev);
+
+    sdio_claim_host(func);
+
+    data = addr;
+
+    ret = sdio_memcpy_toio(func, glue->ioport_reg, &data, sizeof(data));
+
+    if (unlikely(ret)) {
+        dev_err(child->parent, "sdio read reg write address failed (%d)\n", ret);
+        goto io_err;
+    }
+
+    ret = sdio_memcpy_fromio(func, &data, glue->ioport_reg, sizeof(data));
+
+    if (unlikely(ret)) {
+        *buf = 0xffffffff;
+        dev_err(child->parent, "sdio read reg from I/O failed (%d)\n", ret);
+        goto io_err;
+    }
+
+    *buf = data;
+
+io_err:
+    sdio_release_host(func);
+
+	return ret;
+}
+
+#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
+static int ssv6xxx_sdio_trigger_tx_rx(struct device *child)
+{
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+	struct mmc_host *host;
+
+	if (glue == NULL)
+		return -1;
+
+	func = dev_to_sdio_func(glue->dev);
+	host = func->card->host;
+	mmc_signal_sdio_irq(host);
+
+	return 0;
+
+}
+#endif
+
+static int __must_check
+ssv6xxx_sdio_write_reg(struct device *child, u32 addr, u32 buf)
+{
+	int ret;
+
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+    u32 data[2];
+
+    ret_if_not_ready(-1);
+
+    func = dev_to_sdio_func(glue->dev);
+
+    sdio_claim_host(func);
+    data[0] = addr;
+    data[1] = buf;
+
+    ret = sdio_memcpy_toio(func, glue->ioport_reg, data, sizeof(data));
+    sdio_release_host(func);
+
+	return ret;
+}
+
+static int
+ssv6xxx_sdio_write_sram(struct device *child, u32 addr, u8 * data, u32 size)
+{
+	int ret = 0;
+	struct ssv6xxx_sdio_glue *glue;
+	struct sdio_func *func = NULL;
+	glue = dev_get_drvdata(child->parent);
+
+    ret_if_not_ready(-1);
+
+	func = dev_to_sdio_func(glue->dev);
+	sdio_claim_host(func);
+
+    ret |= ssv6xxx_sdio_write_reg(child, 0xc0000860, addr);
+    if (unlikely(ret))
+        goto out;
+
+    sdio_writeb(func, 0x2, REG_Fn1_STATUS, &ret);
+    if (unlikely(ret))
+        goto out;
+
+    ret = sdio_memcpy_toio(func, glue->ioport_data, data, size);
+    if (unlikely(ret))
+        goto out;
+
+    sdio_writeb(func, 0, REG_Fn1_STATUS, &ret);
+    if (unlikely(ret))
+        goto out;
+
+out:
+	sdio_release_host(func);
+	return ret;
+
+}
+
+struct file *ssv6xxx_open_firmware(char *user_mainfw)
+{
+	struct file *fp;
+	fp = filp_open(user_mainfw, O_RDONLY, 0);
+
+	if (IS_ERR(fp))
+		fp = NULL;
+
+	return fp;
+}
+
+int ssv6xxx_read_fw_block(char *buf, int len, struct file *fp)
+{
+
+	int read;
+	loff_t pos;
+
+	pos = fp->f_pos;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
+	read = kernel_read(fp, (void *)buf, len, &pos);
+#else
+	read = kernel_read(fp, pos, buf, len);
+#endif
+
+	if (read > 0)
+		fp->f_pos += read;
+
+	return read;
+
+}
+
+void ssv6xxx_close_firmware(struct file *fp)
+{
+	if (fp)
+		filp_close(fp, NULL);
+}
+
+static int
+ssv6xxx_sdio_upload_firmware(struct device *child, const u8 *firmware, u32 firmware_length)
+{
+	int ret;
+    u32 clk_en;
+	u32 word_count, i;
+    u32 block_size;
+	u8 *buffer;
+	u32 sram_ptr = 0;
+	u32 block_count = 0;
+    u32 firmware_ptr = 0;
+
+	u32 checksum = FW_CHECKSUM_INIT;
+	u32 fw_checksum, fw_blkcnt;
+
+	struct ssv6xxx_sdio_glue *glue;
+
+	glue = dev_get_drvdata(child->parent);
+
+    if ((wlan_data.is_enabled == false) &&
+        (glue == NULL) &&
+        (glue->dev_ready == false))
+        goto out;
+
+    buffer = (u8 *)kzalloc(FW_BLOCK_SIZE, GFP_KERNEL);
+    if (buffer == NULL) {
+        dev_err(child, "Failed to allocate buffer for firmware.\n");
+        ret = -ENOMEM;
+        goto out;
+    }
+
+    dev_dbg(child, "preparing registers and clock for firmware upload\n");
+
+    ret = ssv6xxx_sdio_write_reg(child, ADR_BRG_SW_RST, 0x0);
+    if (unlikely(ret))
+        goto out;
+
+    ret = ssv6xxx_sdio_write_reg(child, ADR_BOOT, 0x01);
+    if (unlikely(ret))
+        goto out;
+
+    ret = ssv6xxx_sdio_read_reg(child, ADR_PLATFORM_CLOCK_ENABLE, &clk_en);
+    if (unlikely(ret))
+        goto out;
+
+    ret = ssv6xxx_sdio_write_reg(child, ADR_PLATFORM_CLOCK_ENABLE, clk_en | (1 << 2));
+    if (unlikely(ret))
+        goto out;
+
+    dev_dbg(child, "begin writing firmware\n");
+
+    while (firmware_length > 0) {
+
+        memset(buffer, 0xA5, FW_BLOCK_SIZE);
+
+        block_size = firmware_length;
+        if (block_size > FW_BLOCK_SIZE)
+            block_size = FW_BLOCK_SIZE;
+
+        memcpy(buffer, &firmware[firmware_ptr], block_size);
+
+        firmware_ptr += block_size;
+        firmware_length -= block_size;
+
+        /*
+         * Uploading to chip sram and checksumming happens in chunks of CHECKSUM_BLOCK_SIZE,
+         * so we round the block size accordingly and use that valueù
+         */
+        block_size = DIV_ROUND_UP(block_size, CHECKSUM_BLOCK_SIZE) * CHECKSUM_BLOCK_SIZE;
+        ret = ssv6xxx_sdio_write_sram(child, sram_ptr, (u8 *)buffer, block_size);
+
+        if (ret) {
+            dev_err(child, "firmware upload failed\n");
+            goto out;
+        }
+
+        sram_ptr += block_size;
+
+        word_count = block_size / sizeof(u32);
+        for (i = 0; i < word_count; i++)
+            checksum += ((u32 *)buffer)[i];
+
+    }
+
+    checksum = ((checksum >> 24) +
+                (checksum >> 16) +
+                (checksum >> 8) +
+                checksum) & 0x0FF;
+    checksum <<= 16;
+
+    block_count = DIV_ROUND_UP(sram_ptr, CHECKSUM_BLOCK_SIZE);
+    ret = ssv6xxx_sdio_write_reg(child, FW_STATUS_REG, (block_count << 16));
+    if (unlikely(ret))
+        goto out;
+
+    ret = ssv6xxx_sdio_read_reg(child, FW_STATUS_REG, &fw_blkcnt);
+    if (unlikely(ret))
+        goto out;
+
+    ret = ssv6xxx_sdio_write_reg(child, ADR_BRG_SW_RST, 0x1);
+    if (unlikely(ret))
+        goto out;
+
+    dev_info(child, "firmware upload complete (wrote %d blocks, verified %d blocks)\n", block_count, fw_blkcnt >> 16);
+
+    msleep(50);
+
+    ret = ssv6xxx_sdio_read_reg(child, FW_STATUS_REG, &fw_checksum);
+    fw_checksum = fw_checksum & FW_STATUS_MASK;
+
+    if (fw_checksum == checksum) {
+        dev_dbg(child, "firmware check ok, checksum=0x%x\n", checksum);
+        ret = ssv6xxx_sdio_write_reg(child, FW_STATUS_REG, (~checksum & FW_STATUS_MASK));
+        if (unlikely(ret))
+            dev_warn(child, "could not clear checksum condition");
+    } else {
+        dev_err(child, "firmware checksum mismatch, local=0x%x, sram=0x%x\n", checksum, fw_checksum);
+    }
+
+    msleep(50);
+
+    ret = 0;
+
+ out:
+
+	if (buffer)
+		kfree(buffer);
+
+	return ret;
+
+}
+
+static int
+ssv6xxx_sdio_load_firmware(struct device *child, u8 *firmware_name, u8 openfile)
+{
+
+    int ret;
+    const struct firmware *firmware = NULL;
+    struct sdio_func *func;
+   	struct ssv6xxx_sdio_glue *glue;
+
+    glue = dev_get_drvdata(child->parent);
+
+    ret = request_firmware(&firmware, firmware_name, glue->dev);
+
+    if (ret) {
+        dev_err(child, "could not find firmware file %s, err=%d\n", firmware_name, ret);
+        goto out;
+    }
+
+    ret = ssv6xxx_sdio_upload_firmware(child, firmware->data, firmware->size);
+
+    if (ret) {
+        dev_err(child, "could not upload firmware to device, err=%d\n", ret);
+        goto out;
+    }
+
+    if (glue != NULL) {
+		func = dev_to_sdio_func(glue->dev);
+		ssv6xxx_high_sdio_clk(func);
+	}
+
+out:
+    if (firmware != NULL)
+        release_firmware(firmware);
+
+    return ret;
+
+}
+
+static int ssv6xxx_sdio_irq_getstatus(struct device *child, int *status)
+{
+	int ret = (-1);
+	struct ssv6xxx_sdio_glue *glue;
+	struct sdio_func *func;
+	glue = dev_get_drvdata(child->parent);
+
+    ret_if_not_ready(-1);
+
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    *status = sdio_readb(func, REG_INT_STATUS, &ret);
+    sdio_release_host(func);
+
+    return ret;
+
+}
+
+static int __must_check
+ssv6xxx_sdio_read(struct device *child, void *buf, size_t *size)
+{
+
+	int ret;
+    u32 data_size;
+
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+    ret_if_not_ready(-1);
+
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+
+    data_size = sdio_readb(func, REG_CARD_PKT_LEN_0, &ret);
+
+    if (unlikely(ret)) {
+        dev_err(child->parent, "sdio read high byte len failed, ret=%d\n", ret);
+        goto out;
+    }
+
+    data_size = data_size | (sdio_readb(func, REG_CARD_PKT_LEN_1, &ret) << 0x8);
+
+    if (unlikely(ret)) {
+        dev_err(child->parent, "sdio read low len failed ret[%d]\n", ret);
+        goto out;
+    }
+
+    ret = sdio_memcpy_fromio(func, buf, glue->ioport_data, sdio_align_size(func, data_size));
+
+    if (unlikely(ret)) {
+        dev_err(child->parent, "sdio read failed size ret[%d]\n", ret);
+        goto out;
+    }
+    
+    *size = data_size;
+
+out:
+
+    sdio_release_host(func);
+
+	return ret;
+}
+
+static int __must_check
+ssv6xxx_sdio_write(struct device *child, void *buf, size_t len, u8 queue_num)
+{
+	int ret;
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+	void *ptr;
+
+    ret_if_not_ready(-1);
+
+#ifdef CONFIG_ARM64
+    if (((u64) buf) & 3) {
+#else
+    if (((u32) buf) & 3) {
+#endif
+        memcpy(glue->dma_skb->data, buf, len);
+        ptr = glue->dma_skb->data;
+    } else
+        ptr = buf;
+
+    func = dev_to_sdio_func(glue->dev);
+
+    sdio_claim_host(func);
+
+    len = sdio_align_size(func, len);
+    ret = sdio_memcpy_toio(func, glue->ioport_data, ptr, len);
+
+    if (unlikely(ret))
+        dev_err(glue->dev, "sdio write failed, ret=%d\n", ret);
+
+    sdio_release_host(func);
+
+    return ret;
+
+}
+
+static void ssv6xxx_sdio_irq_handler(struct sdio_func *func)
+{
+	int status;
+	struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
+
+    ret_if_not_ready();
+
+    if (glue->irq_handler == NULL)
+        return;
+
+    atomic_set(&pwlan_data->irq_handling, 1);
+    sdio_release_host(func);
+    if (glue->irq_handler != NULL)
+        status = glue->irq_handler(0, glue->irq_dev);
+    sdio_claim_host(func);
+    atomic_set(&pwlan_data->irq_handling, 0);
+
+}
+
+static void ssv6xxx_sdio_irq_setmask(struct device *child, int mask)
+{
+	int err_ret;
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+    ret_if_not_ready();
+
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    sdio_writeb(func, mask, REG_INT_MASK, &err_ret);
+    sdio_release_host(func);
+
+}
+
+static void ssv6xxx_sdio_irq_trigger(struct device *child)
+{
+	int err_ret;
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+    ret_if_not_ready();
+
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    sdio_writeb(func, 0x2, REG_INT_TRIGGER, &err_ret);
+    sdio_release_host(func);
+
+}
+
+static int ssv6xxx_sdio_irq_getmask(struct device *child, u32 * mask)
+{
+	u8 imask = 0;
+	int ret = (-1);
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+    ret_if_not_ready(-1);
+
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    imask = sdio_readb(func, REG_INT_MASK, &ret);
+    *mask = imask;
+    sdio_release_host(func);
+
+	return ret;
+
+}
+
+static void ssv6xxx_sdio_irq_enable(struct device *child)
+{
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+	int ret;
+	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
+	if ((pwlan_data->is_enabled == false)
+	    || (glue == NULL) || (glue->dev_ready == false))
+		return;
+
+    func = dev_to_sdio_func(glue->dev);
+    sdio_claim_host(func);
+    ret = sdio_claim_irq(func, ssv6xxx_sdio_irq_handler);
+    if (ret)
+        dev_err(child->parent, "Failed to claim sdio irq: %d\n",
+            ret);
+    sdio_release_host(func);
+
+	dev_dbg(child, "ssv6xxx_sdio_irq_enable\n");
+
+}
+
+static void ssv6xxx_sdio_irq_disable(struct device *child, bool iswaitirq)
+{
+	struct ssv6xxx_sdio_glue *glue = NULL;
+	struct sdio_func *func;
+	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
+	int ret;
+
+	dev_dbg(child, "ssv6xxx_sdio_irq_disable\n");
+
+	if ((wlan_data.is_enabled == false) || (child->parent == NULL))
+		return;
+
+	glue = dev_get_drvdata(child->parent);
+
+
+	if ((glue == NULL) || (glue->dev_ready == false)
+	    || (glue->dev == NULL))
+		return;
+
+    func = dev_to_sdio_func(glue->dev);
+
+    if (func == NULL) {
+        dev_dbg(child, "sdio func == NULL\n");
+        return;
+    }
+
+    sdio_claim_host(func);
+    while (atomic_read(&pwlan_data->irq_handling)) {
+        sdio_release_host(func);
+        schedule_timeout(HZ / 10);
+        sdio_claim_host(func);
+    }
+    ret = sdio_release_irq(func);
+
+    if (ret)
+        dev_err(child->parent,
+            "Failed to release sdio irq: %d\n", ret);
+
+    sdio_release_host(func);
+
+}
+
+static void
+ssv6xxx_sdio_irq_request(struct device *child, irq_handler_t irq_handler,
+			 void *irq_dev)
+{
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+	bool isIrqEn = false;
+
+    ret_if_not_ready();
+
+    func = dev_to_sdio_func(glue->dev);
+    glue->irq_handler = irq_handler;
+    glue->irq_dev = irq_dev;
+    if (isIrqEn) {
+        ssv6xxx_sdio_irq_enable(child);
+    }
+
+}
+
+static void
+ssv6xxx_sdio_read_parameter(struct sdio_func *func,
+			    struct ssv6xxx_sdio_glue *glue)
+{
+	int err_ret;
+	sdio_claim_host(func);
+	glue->ioport_data = 0;
+	glue->ioport_data =
+	    glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_0, &err_ret)
+				<< (8 * 0));
+	glue->ioport_data =
+	    glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_1, &err_ret)
+				<< (8 * 1));
+	glue->ioport_data =
+	    glue->ioport_data | (sdio_readb(func, REG_DATA_IO_PORT_2, &err_ret)
+				<< (8 * 2));
+	glue->ioport_reg = 0;
+	glue->ioport_reg =
+	    glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_0, &err_ret) <<
+			       (8 * 0));
+	glue->ioport_reg =
+	    glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_1, &err_ret) <<
+			       (8 * 1));
+	glue->ioport_reg =
+	    glue->ioport_reg | (sdio_readb(func, REG_REG_IO_PORT_2, &err_ret) <<
+			       (8 * 2));
+	dev_dbg(&func->dev, "ioport_data=0x%x ioport_reg=0x%x\n",
+		glue->ioport_data, glue->ioport_reg);
+	err_ret = sdio_set_block_size(func, CONFIG_PLATFORM_SDIO_BLOCK_SIZE);
+	if (err_ret != 0) {
+		dev_warn(&func->dev, "SDIO setting SDIO_DEF_BLOCK_SIZE fail!!\n");
+	}
+	sdio_writeb(func, CONFIG_PLATFORM_SDIO_OUTPUT_TIMING,
+		    REG_OUTPUT_TIMING_REG, &err_ret);
+	sdio_writeb(func, 0x00, REG_Fn1_STATUS, &err_ret);
+	sdio_release_host(func);
+}
+
+static void ssv6xxx_do_sdio_wakeup(struct sdio_func *func)
+{
+	int err_ret;
+	if (func != NULL) {
+		sdio_claim_host(func);
+		sdio_writeb(func, 0x01, REG_PMU_WAKEUP, &err_ret);
+		mdelay(10);
+		sdio_writeb(func, 0x00, REG_PMU_WAKEUP, &err_ret);
+		sdio_release_host(func);
+	}
+}
+
+static void ssv6xxx_sdio_pmu_wakeup(struct device *child)
+{
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+	if (glue != NULL) {
+		func = dev_to_sdio_func(glue->dev);
+		ssv6xxx_do_sdio_wakeup(func);
+	}
+}
+
+static bool ssv6xxx_sdio_support_scatter(struct device *child)
+{
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+
+    if (!glue) {
+        dev_err(child->parent, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
+        return false;
+    }
+
+    func = dev_to_sdio_func(glue->dev);
+
+    if (func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
+        dev_err(child->parent,
+            "host controller only supports scatter of :%d entries, driver need: %d\n",
+            func->card->host->max_segs,
+            MAX_SCATTER_ENTRIES_PER_REQ);
+        return false;
+    }
+
+    return true;
+
+}
+
+static void
+ssv6xxx_sdio_setup_scat_data(struct sdio_scatter_req *scat_req,
+			     struct mmc_data *data)
+{
+	struct scatterlist *sg;
+	int i;
+	data->blksz = SDIO_DEF_BLOCK_SIZE;
+	data->blocks = scat_req->len / SDIO_DEF_BLOCK_SIZE;
+	pr_debug
+	    ("scatter: (%s)  (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
+	     (scat_req->req & SDIO_WRITE) ? "WR" : "RD", data->blksz,
+	     data->blocks, scat_req->len, scat_req->scat_entries);
+	data->flags =
+	    (scat_req->req & SDIO_WRITE) ? MMC_DATA_WRITE : MMC_DATA_READ;
+	sg = scat_req->sgentries;
+	sg_init_table(sg, scat_req->scat_entries);
+	for (i = 0; i < scat_req->scat_entries; i++, sg++) {
+		pr_debug("%d: addr:0x%p, len:%d\n",
+		       i, scat_req->scat_list[i].buf,
+		       scat_req->scat_list[i].len);
+		sg_set_buf(sg, scat_req->scat_list[i].buf,
+			   scat_req->scat_list[i].len);
+	}
+	data->sg = scat_req->sgentries;
+	data->sg_len = scat_req->scat_entries;
+}
+
+static inline void
+ssv6xxx_sdio_set_cmd53_arg(u32 * arg, u8 rw, u8 func,
+			   u8 mode, u8 opcode, u32 addr, u16 blksz)
+{
+	*arg = (((rw & 1) << 31) |
+		((func & 0x7) << 28) |
+		((mode & 1) << 27) |
+		((opcode & 1) << 26) | ((addr & 0x1FFFF) << 9) | (blksz &
+								  0x1FF));
+}
+
+static int
+ssv6xxx_sdio_rw_scatter(struct device *child, struct sdio_scatter_req *scat_req)
+{
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func;
+	struct mmc_request mmc_req;
+	struct mmc_command cmd;
+	struct mmc_data data;
+	u8 opcode, rw;
+	int status = 1;
+
+    if (!glue) {
+        dev_err(child->parent, "ssv6xxx_sdio_enable_scatter glue == NULL!!!\n");
+        return 1;
+    }
+
+    func = dev_to_sdio_func(glue->dev);
+    memset(&mmc_req, 0, sizeof(struct mmc_request));
+    memset(&cmd, 0, sizeof(struct mmc_command));
+    memset(&data, 0, sizeof(struct mmc_data));
+    ssv6xxx_sdio_setup_scat_data(scat_req, &data);
+    opcode = 0;
+    rw = (scat_req->req & SDIO_WRITE) ? CMD53_ARG_WRITE :
+        CMD53_ARG_READ;
+    ssv6xxx_sdio_set_cmd53_arg(&cmd.arg, rw, func->num,
+                    CMD53_ARG_BLOCK_BASIS, opcode,
+                    glue->ioport_data, data.blocks);
+    cmd.opcode = SD_IO_RW_EXTENDED;
+    cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
+    mmc_req.cmd = &cmd;
+    mmc_req.data = &data;
+    mmc_set_data_timeout(&data, func->card);
+    mmc_wait_for_req(func->card->host, &mmc_req);
+
+    status = cmd.error ? cmd.error : data.error;
+
+    if (cmd.error)
+        return cmd.error;
+
+    if (data.error)
+        return data.error;
+
+    return status;
+
+}
+
+static void ssv6xxx_set_sdio_clk(struct sdio_func *func, u32 sdio_hz)
+{
+	struct mmc_host *host;
+	host = func->card->host;
+	if (sdio_hz < host->f_min)
+		sdio_hz = host->f_min;
+	else if (sdio_hz > host->f_max)
+		sdio_hz = host->f_max;
+	dev_dbg(&func->dev, "%s:set sdio clk %dHz\n", __FUNCTION__, sdio_hz);
+	sdio_claim_host(func);
+	host->ios.clock = sdio_hz;
+	host->ops->set_ios(host, &host->ios);
+	mdelay(20);
+	sdio_release_host(func);
+}
+
+static void ssv6xxx_low_sdio_clk(struct sdio_func *func)
+{
+	ssv6xxx_set_sdio_clk(func, LOW_SPEED_SDIO_CLOCK);
+}
+
+static void ssv6xxx_high_sdio_clk(struct sdio_func *func)
+{
+#ifndef SDIO_USE_SLOW_CLOCK
+	ssv6xxx_set_sdio_clk(func, HIGH_SPEED_SDIO_CLOCK);
+#endif
+}
+
+static struct ssv6xxx_hwif_ops sdio_ops = {
+	.read = ssv6xxx_sdio_read,
+	.write = ssv6xxx_sdio_write,
+	.readreg = ssv6xxx_sdio_read_reg,
+	.writereg = ssv6xxx_sdio_write_reg,
+#ifdef ENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
+	.trigger_tx_rx = ssv6xxx_sdio_trigger_tx_rx,
+#endif
+	.irq_getmask = ssv6xxx_sdio_irq_getmask,
+	.irq_setmask = ssv6xxx_sdio_irq_setmask,
+	.irq_enable = ssv6xxx_sdio_irq_enable,
+	.irq_disable = ssv6xxx_sdio_irq_disable,
+	.irq_getstatus = ssv6xxx_sdio_irq_getstatus,
+	.irq_request = ssv6xxx_sdio_irq_request,
+	.irq_trigger = ssv6xxx_sdio_irq_trigger,
+	.pmu_wakeup = ssv6xxx_sdio_pmu_wakeup,
+	.load_fw = ssv6xxx_sdio_load_firmware,
+	.cmd52_read = ssv6xxx_sdio_cmd52_read,
+	.cmd52_write = ssv6xxx_sdio_cmd52_write,
+	.support_scatter = ssv6xxx_sdio_support_scatter,
+	.rw_scatter = ssv6xxx_sdio_rw_scatter,
+	.is_ready = ssv6xxx_is_ready,
+	.write_sram = ssv6xxx_sdio_write_sram,
+	.interface_reset = ssv6xxx_sdio_reset,
+};
+
+static int
+ssv6xxx_sdio_power_on(struct ssv6xxx_platform_data *pdata,
+		      struct sdio_func *func)
+{
+	int ret = 0;
+	if (pdata->is_enabled == true)
+		return 0;
+
+	dev_dbg(&func->dev, "ssv6xxx_sdio_power_on\n");
+
+	sdio_claim_host(func);
+	ret = sdio_enable_func(func);
+	sdio_release_host(func);
+
+	if (ret) {
+		dev_err(&func->dev, "Unable to enable sdio func: %d)\n", ret);
+		return ret;
+	}
+
+	msleep(10);
+	pdata->is_enabled = true;
+
+	return ret;
+}
+
+static int
+ssv6xxx_sdio_power_off(struct ssv6xxx_platform_data *pdata,
+		       struct sdio_func *func)
+{
+	int ret;
+	if (pdata->is_enabled == false)
+		return 0;
+	dev_dbg(&func->dev, "ssv6xxx_sdio_power_off\n");
+	sdio_claim_host(func);
+	ret = sdio_disable_func(func);
+	sdio_release_host(func);
+	if (ret)
+		return ret;
+	pdata->is_enabled = false;
+	return ret;
+}
+
+int ssv6xxx_get_dev_status(void)
+{
+	return ssv6xxx_sdio_status;
+}
+
+EXPORT_SYMBOL(ssv6xxx_get_dev_status);
+
+static int
+ssv6xxx_sdio_probe(struct sdio_func *func, const struct sdio_device_id *id)
+{
+	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
+	struct ssv6xxx_sdio_glue *glue;
+	int ret;
+	const char *chip_family = "ssv6200";
+
+	if (ssv_devicetype != 0) {
+		dev_info(&func->dev, "Not using SSV6200 normal SDIO driver.\n");
+		return -ENODEV;
+	}
+
+	if (func->num != 0x01)
+		return -ENODEV;
+
+	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
+
+	if (!glue) {
+		dev_err(&func->dev, "can't allocate glue\n");
+		return -ENOMEM;
+	}
+
+	ssv6xxx_sdio_status = 1;
+	ssv6xxx_low_sdio_clk(func);
+
+	glue->dma_skb = __dev_alloc_skb(SDIO_DMA_BUFFER_LEN, GFP_KERNEL);
+
+#ifdef CONFIG_PM
+	glue->cmd_skb = __dev_alloc_skb(SDIO_COMMAND_BUFFER_LEN, GFP_KERNEL);
+#endif
+	memset(pwlan_data, 0, sizeof(struct ssv6xxx_platform_data));
+	atomic_set(&pwlan_data->irq_handling, 0);
+	glue->dev = &func->dev;
+	func->card->quirks |= MMC_QUIRK_LENIENT_FN0;
+	func->card->quirks |= MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
+	glue->dev_ready = true;
+	pwlan_data->vendor = func->vendor;
+	pwlan_data->device = func->device;
+	dev_info(glue->dev, "device id: %x:%x\n", pwlan_data->vendor,
+		pwlan_data->device);
+	pwlan_data->ops = &sdio_ops;
+	sdio_set_drvdata(func, glue);
+#ifdef CONFIG_PM
+	ssv6xxx_do_sdio_wakeup(func);
+#endif
+	ssv6xxx_sdio_power_on(pwlan_data, func);
+	ssv6xxx_sdio_read_parameter(func, glue);
+	glue->core = platform_device_alloc(chip_family, -1);
+
+	if (!glue->core) {
+		dev_err(glue->dev, "can't allocate platform_device");
+		ret = -ENOMEM;
+		goto out_free_glue;
+	}
+
+	glue->core->dev.parent = &func->dev;
+
+	ret = platform_device_add_data(glue->core, pwlan_data,
+				       sizeof(*pwlan_data));
+
+	if (ret) {
+		dev_err(glue->dev, "can't add platform data\n");
+		goto out_dev_put;
+	}
+
+	ret = platform_device_add(glue->core);
+
+	if (ret) {
+		dev_err(glue->dev, "can't add platform device\n");
+		goto out_dev_put;
+	}
+
+	ssv6xxx_sdio_irq_setmask(&glue->core->dev, 0xff);
+
+	ssv6xxx_ifdebug_info[0] = (void *)&glue->core->dev;
+	ssv6xxx_ifdebug_info[1] = (void *)glue->core;
+	ssv6xxx_ifdebug_info[2] = (void *)&sdio_ops;
+	return 0;
+
+ out_dev_put:
+	platform_device_put(glue->core);
+ out_free_glue:
+	kfree(glue);
+
+	return ret;
+
+}
+
+static void ssv6xxx_sdio_remove(struct sdio_func *func)
+{
+	struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+	struct ssv6xxx_platform_data *pwlan_data = &wlan_data;
+
+	dev_dbg(&func->dev, "ssv6xxx_sdio_remove enter\n");
+
+	ssv6xxx_sdio_status = 0;
+
+	if (glue) {
+		dev_dbg(&func->dev, "ssv6xxx_sdio_remove - ssv6xxx_sdio_irq_disable\n");
+		ssv6xxx_sdio_irq_disable(&glue->core->dev, false);
+		glue->dev_ready = false;
+		ssv6xxx_low_sdio_clk(func);
+
+		if (glue->dma_skb != NULL)
+			dev_kfree_skb(glue->dma_skb);
+
+		dev_dbg(&func->dev, "ssv6xxx_sdio_remove - disable mask\n");
+		ssv6xxx_sdio_irq_setmask(&glue->core->dev, 0xff);
+#ifdef CONFIG_PM
+		ssv6xxx_sdio_trigger_pmu(glue->dev);
+		if (glue->cmd_skb != NULL)
+			dev_kfree_skb(glue->cmd_skb);
+#endif
+		ssv6xxx_sdio_power_off(pwlan_data, func);
+		dev_dbg(&func->dev, "platform_device_del \n");
+		platform_device_del(glue->core);
+		dev_dbg(&func->dev, "platform_device_put \n");
+		platform_device_put(glue->core);
+		kfree(glue);
+	}
+
+	sdio_set_drvdata(func, NULL);
+	dev_dbg(&func->dev, "ssv6xxx_sdio_remove leave\n");
+
+}
+
+static int ssv6xxx_sdio_trigger_pmu(struct device *dev)
+{
+
+	int ret = 0;
+
+#ifdef CONFIG_PM
+	struct sdio_func *func = dev_to_sdio_func(dev);
+	struct ssv6xxx_sdio_glue *glue = sdio_get_drvdata(func);
+	struct cfg_host_cmd *host_cmd;
+	int writesize;
+	void *tempPointer;
+
+	if (ssv6xxx_sdio_write_reg
+	    (dev, ADR_RX_FLOW_MNG, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
+	if (ssv6xxx_sdio_write_reg
+	    (dev, ADR_RX_FLOW_DATA, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
+	if (ssv6xxx_sdio_write_reg
+	    (dev, ADR_RX_FLOW_CTRL, M_ENG_MACRX | (M_ENG_TRASH_CAN << 4))) ;
+
+	host_cmd = (struct cfg_host_cmd *)glue->cmd_skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->RSVD0 = 0;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_PS;
+	host_cmd->len = sizeof(struct cfg_host_cmd);
+
+	host_cmd->dummy = 0;
+
+	{
+		tempPointer = glue->cmd_skb->data;
+		sdio_claim_host(func);
+		writesize = sdio_align_size(func, sizeof(struct cfg_host_cmd));
+		do {
+			ret =
+			    sdio_memcpy_toio(func, glue->ioport_data,
+					     tempPointer, writesize);
+			if (ret == -EILSEQ || ret == -ETIMEDOUT) {
+				ret = -1;
+				break;
+			} else {
+				if (ret)
+					dev_err(glue->dev,
+						"Unexpected return value ret=[%d]\n",
+						ret);
+			}
+		}
+		while (ret == -EILSEQ || ret == -ETIMEDOUT);
+		sdio_release_host(func);
+		if (ret)
+			dev_err(glue->dev, "sdio write failed (%d)\n", ret);
+	}
+
+#endif
+
+	return ret;
+
+}
+
+static void ssv6xxx_sdio_reset(struct device *child)
+{
+
+#ifdef CONFIG_PM
+	struct ssv6xxx_sdio_glue *glue = dev_get_drvdata(child->parent);
+	struct sdio_func *func = dev_to_sdio_func(glue->dev);
+	dev_dbg(child, "%s\n", __FUNCTION__);
+	if (glue == NULL || glue->dev == NULL || func == NULL)
+		return;
+	ssv6xxx_sdio_trigger_pmu(glue->dev);
+	ssv6xxx_do_sdio_wakeup(func);
+#endif
+
+	return;
+
+}
+
+#ifdef CONFIG_PM
+static int ssv6xxx_sdio_suspend(struct device *dev)
+{
+	struct sdio_func *func = dev_to_sdio_func(dev);
+	mmc_pm_flag_t flags = sdio_get_host_pm_caps(func);
+	{
+		int ret = 0;
+		dev_info(dev, "%s: suspend: PM flags = 0x%x\n",
+			 sdio_func_id(func), flags);
+		ssv6xxx_low_sdio_clk(func);
+		ret = ssv6xxx_sdio_trigger_pmu(dev);
+		if (ret)
+			dev_warn(dev, "ssv6xxx_sdio_trigger_pmu fail!!\n");
+		if (!(flags & MMC_PM_KEEP_POWER)) {
+			dev_err(dev,
+				"%s: cannot remain alive while host is suspended\n",
+				sdio_func_id(func));
+		}
+		ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
+		if (ret)
+			return ret;
+		mdelay(10);
+		return ret;
+	}
+}
+
+static int ssv6xxx_sdio_resume(struct device *dev)
+{
+	struct sdio_func *func = dev_to_sdio_func(dev);
+	{
+		dev_dbg(dev, "ssv6xxx_sdio_resume\n");
+		{
+			ssv6xxx_do_sdio_wakeup(func);
+			mdelay(10);
+			ssv6xxx_high_sdio_clk(func);
+			mdelay(10);
+		}
+	}
+	return 0;
+}
+
+static const struct dev_pm_ops ssv6xxx_sdio_pm_ops = {
+	.suspend = ssv6xxx_sdio_suspend,
+	.resume = ssv6xxx_sdio_resume,
+};
+#endif
+
+struct sdio_driver ssv6xxx_sdio_driver = {
+	.name = "ssv6051",
+	.id_table = ssv6xxx_sdio_devices,
+	.probe = ssv6xxx_sdio_probe,
+	.remove = ssv6xxx_sdio_remove,
+#ifdef CONFIG_PM
+	.drv = {
+		.pm = &ssv6xxx_sdio_pm_ops,
+		},
+#endif
+};
+
+EXPORT_SYMBOL(ssv6xxx_sdio_driver);
+
+int ssv6xxx_sdio_init(void)
+{
+	return sdio_register_driver(&ssv6xxx_sdio_driver);
+}
+
+void ssv6xxx_sdio_exit(void)
+{
+	pr_info("ssv6xxx_sdio_exit\n");
+	sdio_unregister_driver(&ssv6xxx_sdio_driver);
+}
+
+EXPORT_SYMBOL(ssv6xxx_sdio_init);
+EXPORT_SYMBOL(ssv6xxx_sdio_exit);
diff --git a/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h b/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
new file mode 100644
index 00000000000..57aefd3bf9f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/hwif/sdio/sdio_def.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SDIO_DEF_H_
+#define _SDIO_DEF_H_
+#include <linux/scatterlist.h>
+#define BASE_SDIO 0
+#define REG_DATA_IO_PORT_0 (BASE_SDIO + 0x00)
+#define REG_DATA_IO_PORT_1 (BASE_SDIO + 0x01)
+#define REG_DATA_IO_PORT_2 (BASE_SDIO + 0x02)
+#define REG_INT_MASK (BASE_SDIO + 0x04)
+#define REG_INT_STATUS (BASE_SDIO + 0x08)
+#define REG_INT_TRIGGER (BASE_SDIO + 0x09)
+#define REG_Fn1_STATUS (BASE_SDIO + 0x0c)
+#define REG_CARD_PKT_LEN_0 (BASE_SDIO + 0x10)
+#define REG_CARD_PKT_LEN_1 (BASE_SDIO + 0x11)
+#define REG_CARD_FW_DL_STATUS (BASE_SDIO + 0x12)
+#define REG_CARD_SELF_TEST (BASE_SDIO + 0x13)
+#define REG_CARD_RCA_0 (BASE_SDIO + 0x20)
+#define REG_CARD_RCA_1 (BASE_SDIO + 0x21)
+#define REG_SDIO_FIFO_WR_THLD_0 (BASE_SDIO + 0x24)
+#define REG_SDIO_FIFO_WR_THLD_1 (BASE_SDIO + 0x25)
+#define REG_OUTPUT_TIMING_REG (BASE_SDIO + 0x55)
+#define REG_PMU_WAKEUP (BASE_SDIO + 0x67)
+#define REG_REG_IO_PORT_0 (BASE_SDIO + 0x70)
+#define REG_REG_IO_PORT_1 (BASE_SDIO + 0x71)
+#define REG_REG_IO_PORT_2 (BASE_SDIO + 0x72)
+#define REG_SDIO_TX_ALLOC_SIZE (BASE_SDIO + 0x98)
+#define REG_SDIO_TX_ALLOC_SHIFT (BASE_SDIO + 0x99)
+#define REG_SDIO_TX_ALLOC_STATE (BASE_SDIO + 0x9a)
+#define REG_SDIO_TX_INFORM_0 (BASE_SDIO + 0x9c)
+#define REG_SDIO_TX_INFORM_1 (BASE_SDIO + 0x9d)
+#define REG_SDIO_TX_INFORM_2 (BASE_SDIO + 0x9e)
+#define SDIO_DEF_BLOCK_SIZE 0x80
+#if (SDIO_DEF_BLOCK_SIZE % 8)
+#error Wrong SDIO_DEF_BLOCK_SIZE value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
+#endif
+#define SDIO_DEF_OUTPUT_TIMING 0
+#define SDIO_DEF_BLOCK_MODE_THRD 128
+#if (SDIO_DEF_BLOCK_MODE_THRD % 8)
+#error Wrong SDIO_DEF_BLOCK_MODE_THRD value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
+#endif
+#define SDIO_DEF_FORCE_BLOCK_MODE 0
+#define MAX_SCATTER_ENTRIES_PER_REQ 8
+struct sdio_scatter_item {
+	u8 *buf;
+	int len;
+};
+struct sdio_scatter_req {
+	u32 req;
+	u32 len;
+	int scat_entries;
+	struct sdio_scatter_item scat_list[MAX_SCATTER_ENTRIES_PER_REQ];
+	struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];
+};
+#define SDIO_READ 0x00000001
+#define SDIO_WRITE 0x00000002
+#define CMD53_ARG_READ 0
+#define CMD53_ARG_WRITE 1
+#define CMD53_ARG_BLOCK_BASIS 1
+#define CMD53_ARG_FIXED_ADDRESS 0
+#define CMD53_ARG_INCR_ADDRESS 1
+#define SDIO_DMA_BUFFER_LEN 2048
+#ifdef CONFIG_PM
+#define SDIO_COMMAND_BUFFER_LEN 256
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/cabrio.h b/drivers/net/wireless/ssv6051/include/cabrio.h
new file mode 100644
index 00000000000..0b1327865c6
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/cabrio.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CABRIO_H
+#define CABRIO_H
+#define SSV_VENDOR_ID 0x3030
+#define SSV_CABRIO_DEVID 0x3030
+#define SSV_SUBVENDOR_ID_NOG 0x0e11
+#define SSV_SUBVENDOR_ID_NEW_A 0x7065
+#define SSV_CABRIO_MAGIC 0x19641014
+#define SSV_AMPDU_LIMIT_MAX (64 * 1024 - 1)
+#define SSV_DEFAULT_NOISE_FLOOR -95
+#define SSVCABRIO_RSSI_BAD -128
+#define SSVCABRIO_NUM_CHANNELS 38
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200.h b/drivers/net/wireless/ssv6051/include/ssv6200.h
new file mode 100644
index 00000000000..22eaceaf285
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV6200_H_
+#define _SSV6200_H_
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <net/mac80211.h>
+#ifdef ECLIPSE
+#include <ssv_mod_conf.h>
+#endif
+#include <ssv6200_reg.h>
+#include <ssv6200_aux.h>
+#include <hwif/hwif.h>
+#include <hci/ssv_hci.h>
+#include "ssv6200_common.h"
+#define SSV6200_TOTAL_ID 128
+#ifndef HUW_DRV
+#define SSV6200_ID_TX_THRESHOLD 19
+#define SSV6200_ID_RX_THRESHOLD 60
+#define SSV6200_PAGE_TX_THRESHOLD 115
+#define SSV6200_PAGE_RX_THRESHOLD 115
+#define SSV6XXX_AMPDU_DIVIDER (2)
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER (SSV6200_PAGE_TX_THRESHOLD - (SSV6200_PAGE_TX_THRESHOLD/SSV6XXX_AMPDU_DIVIDER))
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#else
+#undef SSV6200_ID_TX_THRESHOLD
+#undef SSV6200_ID_RX_THRESHOLD
+#undef SSV6200_PAGE_TX_THRESHOLD
+#undef SSV6200_PAGE_RX_THRESHOLD
+#undef SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER
+#undef SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER
+#define SSV6200_ID_TX_THRESHOLD 31
+#define SSV6200_ID_RX_THRESHOLD 31
+#define SSV6200_PAGE_TX_THRESHOLD 61
+#define SSV6200_PAGE_RX_THRESHOLD 61
+#define SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER 45
+#define SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER 2
+#endif
+#define SSV6200_ID_NUMBER (128)
+#define PACKET_ADDR_2_ID(addr) ((addr >> 16) & 0x7F)
+#define SSV6200_ID_AC_RESERVED 1
+#define SSV6200_ID_AC_BK_OUT_QUEUE 8
+#define SSV6200_ID_AC_BE_OUT_QUEUE 15
+#define SSV6200_ID_AC_VI_OUT_QUEUE 16
+#define SSV6200_ID_AC_VO_OUT_QUEUE 16
+#define SSV6200_ID_MANAGER_QUEUE 8
+#define HW_MMU_PAGE_SHIFT 0x8
+#define HW_MMU_PAGE_MASK 0xff
+#define SSV6200_BT_PRI_SMP_TIME 0
+#define SSV6200_BT_STA_SMP_TIME (SSV6200_BT_PRI_SMP_TIME+0)
+#define SSV6200_WLAN_REMAIN_TIME 0
+#define BT_2WIRE_EN_MSK 0x00000400
+struct txResourceControl {
+	u32 txUsePage:8;
+	u32 txUseID:6;
+	u32 edca0:4;
+	u32 edca1:4;
+	u32 edca2:5;
+	u32 edca3:5;
+};
+#include <ssv_cfg.h>
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_aux.h b/drivers/net/wireless/ssv6051/include/ssv6200_aux.h
new file mode 100644
index 00000000000..03ec3f07d33
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200_aux.h
@@ -0,0 +1,18221 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define MCU_ENABLE_MSK 0x00000001
+#define MCU_ENABLE_I_MSK 0xfffffffe
+#define MCU_ENABLE_SFT 0
+#define MCU_ENABLE_HI 0
+#define MCU_ENABLE_SZ 1
+#define MAC_SW_RST_MSK 0x00000002
+#define MAC_SW_RST_I_MSK 0xfffffffd
+#define MAC_SW_RST_SFT 1
+#define MAC_SW_RST_HI 1
+#define MAC_SW_RST_SZ 1
+#define MCU_SW_RST_MSK 0x00000004
+#define MCU_SW_RST_I_MSK 0xfffffffb
+#define MCU_SW_RST_SFT 2
+#define MCU_SW_RST_HI 2
+#define MCU_SW_RST_SZ 1
+#define SDIO_SW_RST_MSK 0x00000008
+#define SDIO_SW_RST_I_MSK 0xfffffff7
+#define SDIO_SW_RST_SFT 3
+#define SDIO_SW_RST_HI 3
+#define SDIO_SW_RST_SZ 1
+#define SPI_SLV_SW_RST_MSK 0x00000010
+#define SPI_SLV_SW_RST_I_MSK 0xffffffef
+#define SPI_SLV_SW_RST_SFT 4
+#define SPI_SLV_SW_RST_HI 4
+#define SPI_SLV_SW_RST_SZ 1
+#define UART_SW_RST_MSK 0x00000020
+#define UART_SW_RST_I_MSK 0xffffffdf
+#define UART_SW_RST_SFT 5
+#define UART_SW_RST_HI 5
+#define UART_SW_RST_SZ 1
+#define DMA_SW_RST_MSK 0x00000040
+#define DMA_SW_RST_I_MSK 0xffffffbf
+#define DMA_SW_RST_SFT 6
+#define DMA_SW_RST_HI 6
+#define DMA_SW_RST_SZ 1
+#define WDT_SW_RST_MSK 0x00000080
+#define WDT_SW_RST_I_MSK 0xffffff7f
+#define WDT_SW_RST_SFT 7
+#define WDT_SW_RST_HI 7
+#define WDT_SW_RST_SZ 1
+#define I2C_SLV_SW_RST_MSK 0x00000100
+#define I2C_SLV_SW_RST_I_MSK 0xfffffeff
+#define I2C_SLV_SW_RST_SFT 8
+#define I2C_SLV_SW_RST_HI 8
+#define I2C_SLV_SW_RST_SZ 1
+#define INT_CTL_SW_RST_MSK 0x00000200
+#define INT_CTL_SW_RST_I_MSK 0xfffffdff
+#define INT_CTL_SW_RST_SFT 9
+#define INT_CTL_SW_RST_HI 9
+#define INT_CTL_SW_RST_SZ 1
+#define BTCX_SW_RST_MSK 0x00000400
+#define BTCX_SW_RST_I_MSK 0xfffffbff
+#define BTCX_SW_RST_SFT 10
+#define BTCX_SW_RST_HI 10
+#define BTCX_SW_RST_SZ 1
+#define GPIO_SW_RST_MSK 0x00000800
+#define GPIO_SW_RST_I_MSK 0xfffff7ff
+#define GPIO_SW_RST_SFT 11
+#define GPIO_SW_RST_HI 11
+#define GPIO_SW_RST_SZ 1
+#define US0TMR_SW_RST_MSK 0x00001000
+#define US0TMR_SW_RST_I_MSK 0xffffefff
+#define US0TMR_SW_RST_SFT 12
+#define US0TMR_SW_RST_HI 12
+#define US0TMR_SW_RST_SZ 1
+#define US1TMR_SW_RST_MSK 0x00002000
+#define US1TMR_SW_RST_I_MSK 0xffffdfff
+#define US1TMR_SW_RST_SFT 13
+#define US1TMR_SW_RST_HI 13
+#define US1TMR_SW_RST_SZ 1
+#define US2TMR_SW_RST_MSK 0x00004000
+#define US2TMR_SW_RST_I_MSK 0xffffbfff
+#define US2TMR_SW_RST_SFT 14
+#define US2TMR_SW_RST_HI 14
+#define US2TMR_SW_RST_SZ 1
+#define US3TMR_SW_RST_MSK 0x00008000
+#define US3TMR_SW_RST_I_MSK 0xffff7fff
+#define US3TMR_SW_RST_SFT 15
+#define US3TMR_SW_RST_HI 15
+#define US3TMR_SW_RST_SZ 1
+#define MS0TMR_SW_RST_MSK 0x00010000
+#define MS0TMR_SW_RST_I_MSK 0xfffeffff
+#define MS0TMR_SW_RST_SFT 16
+#define MS0TMR_SW_RST_HI 16
+#define MS0TMR_SW_RST_SZ 1
+#define MS1TMR_SW_RST_MSK 0x00020000
+#define MS1TMR_SW_RST_I_MSK 0xfffdffff
+#define MS1TMR_SW_RST_SFT 17
+#define MS1TMR_SW_RST_HI 17
+#define MS1TMR_SW_RST_SZ 1
+#define MS2TMR_SW_RST_MSK 0x00040000
+#define MS2TMR_SW_RST_I_MSK 0xfffbffff
+#define MS2TMR_SW_RST_SFT 18
+#define MS2TMR_SW_RST_HI 18
+#define MS2TMR_SW_RST_SZ 1
+#define MS3TMR_SW_RST_MSK 0x00080000
+#define MS3TMR_SW_RST_I_MSK 0xfff7ffff
+#define MS3TMR_SW_RST_SFT 19
+#define MS3TMR_SW_RST_HI 19
+#define MS3TMR_SW_RST_SZ 1
+#define RF_BB_SW_RST_MSK 0x00100000
+#define RF_BB_SW_RST_I_MSK 0xffefffff
+#define RF_BB_SW_RST_SFT 20
+#define RF_BB_SW_RST_HI 20
+#define RF_BB_SW_RST_SZ 1
+#define SYS_ALL_RST_MSK 0x00200000
+#define SYS_ALL_RST_I_MSK 0xffdfffff
+#define SYS_ALL_RST_SFT 21
+#define SYS_ALL_RST_HI 21
+#define SYS_ALL_RST_SZ 1
+#define DAT_UART_SW_RST_MSK 0x00400000
+#define DAT_UART_SW_RST_I_MSK 0xffbfffff
+#define DAT_UART_SW_RST_SFT 22
+#define DAT_UART_SW_RST_HI 22
+#define DAT_UART_SW_RST_SZ 1
+#define I2C_MST_SW_RST_MSK 0x00800000
+#define I2C_MST_SW_RST_I_MSK 0xff7fffff
+#define I2C_MST_SW_RST_SFT 23
+#define I2C_MST_SW_RST_HI 23
+#define I2C_MST_SW_RST_SZ 1
+#define RG_REBOOT_MSK 0x00000001
+#define RG_REBOOT_I_MSK 0xfffffffe
+#define RG_REBOOT_SFT 0
+#define RG_REBOOT_HI 0
+#define RG_REBOOT_SZ 1
+#define TRAP_IMG_FLS_MSK 0x00010000
+#define TRAP_IMG_FLS_I_MSK 0xfffeffff
+#define TRAP_IMG_FLS_SFT 16
+#define TRAP_IMG_FLS_HI 16
+#define TRAP_IMG_FLS_SZ 1
+#define TRAP_REBOOT_MSK 0x00020000
+#define TRAP_REBOOT_I_MSK 0xfffdffff
+#define TRAP_REBOOT_SFT 17
+#define TRAP_REBOOT_HI 17
+#define TRAP_REBOOT_SZ 1
+#define TRAP_BOOT_FLS_MSK 0x00040000
+#define TRAP_BOOT_FLS_I_MSK 0xfffbffff
+#define TRAP_BOOT_FLS_SFT 18
+#define TRAP_BOOT_FLS_HI 18
+#define TRAP_BOOT_FLS_SZ 1
+#define CHIP_ID_31_0_MSK 0xffffffff
+#define CHIP_ID_31_0_I_MSK 0x00000000
+#define CHIP_ID_31_0_SFT 0
+#define CHIP_ID_31_0_HI 31
+#define CHIP_ID_31_0_SZ 32
+#define CHIP_ID_63_32_MSK 0xffffffff
+#define CHIP_ID_63_32_I_MSK 0x00000000
+#define CHIP_ID_63_32_SFT 0
+#define CHIP_ID_63_32_HI 31
+#define CHIP_ID_63_32_SZ 32
+#define CHIP_ID_95_64_MSK 0xffffffff
+#define CHIP_ID_95_64_I_MSK 0x00000000
+#define CHIP_ID_95_64_SFT 0
+#define CHIP_ID_95_64_HI 31
+#define CHIP_ID_95_64_SZ 32
+#define CHIP_ID_127_96_MSK 0xffffffff
+#define CHIP_ID_127_96_I_MSK 0x00000000
+#define CHIP_ID_127_96_SFT 0
+#define CHIP_ID_127_96_HI 31
+#define CHIP_ID_127_96_SZ 32
+#define CK_SEL_1_0_MSK 0x00000003
+#define CK_SEL_1_0_I_MSK 0xfffffffc
+#define CK_SEL_1_0_SFT 0
+#define CK_SEL_1_0_HI 1
+#define CK_SEL_1_0_SZ 2
+#define CK_SEL_2_MSK 0x00000004
+#define CK_SEL_2_I_MSK 0xfffffffb
+#define CK_SEL_2_SFT 2
+#define CK_SEL_2_HI 2
+#define CK_SEL_2_SZ 1
+#define SYS_CLK_EN_MSK 0x00000001
+#define SYS_CLK_EN_I_MSK 0xfffffffe
+#define SYS_CLK_EN_SFT 0
+#define SYS_CLK_EN_HI 0
+#define SYS_CLK_EN_SZ 1
+#define MAC_CLK_EN_MSK 0x00000002
+#define MAC_CLK_EN_I_MSK 0xfffffffd
+#define MAC_CLK_EN_SFT 1
+#define MAC_CLK_EN_HI 1
+#define MAC_CLK_EN_SZ 1
+#define MCU_CLK_EN_MSK 0x00000004
+#define MCU_CLK_EN_I_MSK 0xfffffffb
+#define MCU_CLK_EN_SFT 2
+#define MCU_CLK_EN_HI 2
+#define MCU_CLK_EN_SZ 1
+#define SDIO_CLK_EN_MSK 0x00000008
+#define SDIO_CLK_EN_I_MSK 0xfffffff7
+#define SDIO_CLK_EN_SFT 3
+#define SDIO_CLK_EN_HI 3
+#define SDIO_CLK_EN_SZ 1
+#define SPI_SLV_CLK_EN_MSK 0x00000010
+#define SPI_SLV_CLK_EN_I_MSK 0xffffffef
+#define SPI_SLV_CLK_EN_SFT 4
+#define SPI_SLV_CLK_EN_HI 4
+#define SPI_SLV_CLK_EN_SZ 1
+#define UART_CLK_EN_MSK 0x00000020
+#define UART_CLK_EN_I_MSK 0xffffffdf
+#define UART_CLK_EN_SFT 5
+#define UART_CLK_EN_HI 5
+#define UART_CLK_EN_SZ 1
+#define DMA_CLK_EN_MSK 0x00000040
+#define DMA_CLK_EN_I_MSK 0xffffffbf
+#define DMA_CLK_EN_SFT 6
+#define DMA_CLK_EN_HI 6
+#define DMA_CLK_EN_SZ 1
+#define WDT_CLK_EN_MSK 0x00000080
+#define WDT_CLK_EN_I_MSK 0xffffff7f
+#define WDT_CLK_EN_SFT 7
+#define WDT_CLK_EN_HI 7
+#define WDT_CLK_EN_SZ 1
+#define I2C_SLV_CLK_EN_MSK 0x00000100
+#define I2C_SLV_CLK_EN_I_MSK 0xfffffeff
+#define I2C_SLV_CLK_EN_SFT 8
+#define I2C_SLV_CLK_EN_HI 8
+#define I2C_SLV_CLK_EN_SZ 1
+#define INT_CTL_CLK_EN_MSK 0x00000200
+#define INT_CTL_CLK_EN_I_MSK 0xfffffdff
+#define INT_CTL_CLK_EN_SFT 9
+#define INT_CTL_CLK_EN_HI 9
+#define INT_CTL_CLK_EN_SZ 1
+#define BTCX_CLK_EN_MSK 0x00000400
+#define BTCX_CLK_EN_I_MSK 0xfffffbff
+#define BTCX_CLK_EN_SFT 10
+#define BTCX_CLK_EN_HI 10
+#define BTCX_CLK_EN_SZ 1
+#define GPIO_CLK_EN_MSK 0x00000800
+#define GPIO_CLK_EN_I_MSK 0xfffff7ff
+#define GPIO_CLK_EN_SFT 11
+#define GPIO_CLK_EN_HI 11
+#define GPIO_CLK_EN_SZ 1
+#define US0TMR_CLK_EN_MSK 0x00001000
+#define US0TMR_CLK_EN_I_MSK 0xffffefff
+#define US0TMR_CLK_EN_SFT 12
+#define US0TMR_CLK_EN_HI 12
+#define US0TMR_CLK_EN_SZ 1
+#define US1TMR_CLK_EN_MSK 0x00002000
+#define US1TMR_CLK_EN_I_MSK 0xffffdfff
+#define US1TMR_CLK_EN_SFT 13
+#define US1TMR_CLK_EN_HI 13
+#define US1TMR_CLK_EN_SZ 1
+#define US2TMR_CLK_EN_MSK 0x00004000
+#define US2TMR_CLK_EN_I_MSK 0xffffbfff
+#define US2TMR_CLK_EN_SFT 14
+#define US2TMR_CLK_EN_HI 14
+#define US2TMR_CLK_EN_SZ 1
+#define US3TMR_CLK_EN_MSK 0x00008000
+#define US3TMR_CLK_EN_I_MSK 0xffff7fff
+#define US3TMR_CLK_EN_SFT 15
+#define US3TMR_CLK_EN_HI 15
+#define US3TMR_CLK_EN_SZ 1
+#define MS0TMR_CLK_EN_MSK 0x00010000
+#define MS0TMR_CLK_EN_I_MSK 0xfffeffff
+#define MS0TMR_CLK_EN_SFT 16
+#define MS0TMR_CLK_EN_HI 16
+#define MS0TMR_CLK_EN_SZ 1
+#define MS1TMR_CLK_EN_MSK 0x00020000
+#define MS1TMR_CLK_EN_I_MSK 0xfffdffff
+#define MS1TMR_CLK_EN_SFT 17
+#define MS1TMR_CLK_EN_HI 17
+#define MS1TMR_CLK_EN_SZ 1
+#define MS2TMR_CLK_EN_MSK 0x00040000
+#define MS2TMR_CLK_EN_I_MSK 0xfffbffff
+#define MS2TMR_CLK_EN_SFT 18
+#define MS2TMR_CLK_EN_HI 18
+#define MS2TMR_CLK_EN_SZ 1
+#define MS3TMR_CLK_EN_MSK 0x00080000
+#define MS3TMR_CLK_EN_I_MSK 0xfff7ffff
+#define MS3TMR_CLK_EN_SFT 19
+#define MS3TMR_CLK_EN_HI 19
+#define MS3TMR_CLK_EN_SZ 1
+#define BIST_CLK_EN_MSK 0x00100000
+#define BIST_CLK_EN_I_MSK 0xffefffff
+#define BIST_CLK_EN_SFT 20
+#define BIST_CLK_EN_HI 20
+#define BIST_CLK_EN_SZ 1
+#define I2C_MST_CLK_EN_MSK 0x00800000
+#define I2C_MST_CLK_EN_I_MSK 0xff7fffff
+#define I2C_MST_CLK_EN_SFT 23
+#define I2C_MST_CLK_EN_HI 23
+#define I2C_MST_CLK_EN_SZ 1
+#define BTCX_CSR_CLK_EN_MSK 0x00000400
+#define BTCX_CSR_CLK_EN_I_MSK 0xfffffbff
+#define BTCX_CSR_CLK_EN_SFT 10
+#define BTCX_CSR_CLK_EN_HI 10
+#define BTCX_CSR_CLK_EN_SZ 1
+#define MCU_DBG_SEL_MSK 0x0000003f
+#define MCU_DBG_SEL_I_MSK 0xffffffc0
+#define MCU_DBG_SEL_SFT 0
+#define MCU_DBG_SEL_HI 5
+#define MCU_DBG_SEL_SZ 6
+#define MCU_STOP_NOGRANT_MSK 0x00000100
+#define MCU_STOP_NOGRANT_I_MSK 0xfffffeff
+#define MCU_STOP_NOGRANT_SFT 8
+#define MCU_STOP_NOGRANT_HI 8
+#define MCU_STOP_NOGRANT_SZ 1
+#define MCU_STOP_ANYTIME_MSK 0x00000200
+#define MCU_STOP_ANYTIME_I_MSK 0xfffffdff
+#define MCU_STOP_ANYTIME_SFT 9
+#define MCU_STOP_ANYTIME_HI 9
+#define MCU_STOP_ANYTIME_SZ 1
+#define MCU_DBG_DATA_MSK 0xffffffff
+#define MCU_DBG_DATA_I_MSK 0x00000000
+#define MCU_DBG_DATA_SFT 0
+#define MCU_DBG_DATA_HI 31
+#define MCU_DBG_DATA_SZ 32
+#define AHB_SW_RST_MSK 0x00000001
+#define AHB_SW_RST_I_MSK 0xfffffffe
+#define AHB_SW_RST_SFT 0
+#define AHB_SW_RST_HI 0
+#define AHB_SW_RST_SZ 1
+#define AHB_ERR_RST_MSK 0x00000002
+#define AHB_ERR_RST_I_MSK 0xfffffffd
+#define AHB_ERR_RST_SFT 1
+#define AHB_ERR_RST_HI 1
+#define AHB_ERR_RST_SZ 1
+#define REG_AHB_DEBUG_MX_MSK 0x00000030
+#define REG_AHB_DEBUG_MX_I_MSK 0xffffffcf
+#define REG_AHB_DEBUG_MX_SFT 4
+#define REG_AHB_DEBUG_MX_HI 5
+#define REG_AHB_DEBUG_MX_SZ 2
+#define REG_PKT_W_NBRT_MSK 0x00000100
+#define REG_PKT_W_NBRT_I_MSK 0xfffffeff
+#define REG_PKT_W_NBRT_SFT 8
+#define REG_PKT_W_NBRT_HI 8
+#define REG_PKT_W_NBRT_SZ 1
+#define REG_PKT_R_NBRT_MSK 0x00000200
+#define REG_PKT_R_NBRT_I_MSK 0xfffffdff
+#define REG_PKT_R_NBRT_SFT 9
+#define REG_PKT_R_NBRT_HI 9
+#define REG_PKT_R_NBRT_SZ 1
+#define IQ_SRAM_SEL_0_MSK 0x00001000
+#define IQ_SRAM_SEL_0_I_MSK 0xffffefff
+#define IQ_SRAM_SEL_0_SFT 12
+#define IQ_SRAM_SEL_0_HI 12
+#define IQ_SRAM_SEL_0_SZ 1
+#define IQ_SRAM_SEL_1_MSK 0x00002000
+#define IQ_SRAM_SEL_1_I_MSK 0xffffdfff
+#define IQ_SRAM_SEL_1_SFT 13
+#define IQ_SRAM_SEL_1_HI 13
+#define IQ_SRAM_SEL_1_SZ 1
+#define IQ_SRAM_SEL_2_MSK 0x00004000
+#define IQ_SRAM_SEL_2_I_MSK 0xffffbfff
+#define IQ_SRAM_SEL_2_SFT 14
+#define IQ_SRAM_SEL_2_HI 14
+#define IQ_SRAM_SEL_2_SZ 1
+#define AHB_STATUS_MSK 0xffff0000
+#define AHB_STATUS_I_MSK 0x0000ffff
+#define AHB_STATUS_SFT 16
+#define AHB_STATUS_HI 31
+#define AHB_STATUS_SZ 16
+#define PARALLEL_DR_MSK 0x00000001
+#define PARALLEL_DR_I_MSK 0xfffffffe
+#define PARALLEL_DR_SFT 0
+#define PARALLEL_DR_HI 0
+#define PARALLEL_DR_SZ 1
+#define MBRUN_MSK 0x00000010
+#define MBRUN_I_MSK 0xffffffef
+#define MBRUN_SFT 4
+#define MBRUN_HI 4
+#define MBRUN_SZ 1
+#define SHIFT_DR_MSK 0x00000100
+#define SHIFT_DR_I_MSK 0xfffffeff
+#define SHIFT_DR_SFT 8
+#define SHIFT_DR_HI 8
+#define SHIFT_DR_SZ 1
+#define MODE_REG_SI_MSK 0x00000200
+#define MODE_REG_SI_I_MSK 0xfffffdff
+#define MODE_REG_SI_SFT 9
+#define MODE_REG_SI_HI 9
+#define MODE_REG_SI_SZ 1
+#define SIMULATION_MODE_MSK 0x00000400
+#define SIMULATION_MODE_I_MSK 0xfffffbff
+#define SIMULATION_MODE_SFT 10
+#define SIMULATION_MODE_HI 10
+#define SIMULATION_MODE_SZ 1
+#define DBIST_MODE_MSK 0x00000800
+#define DBIST_MODE_I_MSK 0xfffff7ff
+#define DBIST_MODE_SFT 11
+#define DBIST_MODE_HI 11
+#define DBIST_MODE_SZ 1
+#define MODE_REG_IN_MSK 0x001fffff
+#define MODE_REG_IN_I_MSK 0xffe00000
+#define MODE_REG_IN_SFT 0
+#define MODE_REG_IN_HI 20
+#define MODE_REG_IN_SZ 21
+#define MODE_REG_OUT_MCU_MSK 0x001fffff
+#define MODE_REG_OUT_MCU_I_MSK 0xffe00000
+#define MODE_REG_OUT_MCU_SFT 0
+#define MODE_REG_OUT_MCU_HI 20
+#define MODE_REG_OUT_MCU_SZ 21
+#define MODE_REG_SO_MCU_MSK 0x80000000
+#define MODE_REG_SO_MCU_I_MSK 0x7fffffff
+#define MODE_REG_SO_MCU_SFT 31
+#define MODE_REG_SO_MCU_HI 31
+#define MODE_REG_SO_MCU_SZ 1
+#define MONITOR_BUS_MCU_31_0_MSK 0xffffffff
+#define MONITOR_BUS_MCU_31_0_I_MSK 0x00000000
+#define MONITOR_BUS_MCU_31_0_SFT 0
+#define MONITOR_BUS_MCU_31_0_HI 31
+#define MONITOR_BUS_MCU_31_0_SZ 32
+#define MONITOR_BUS_MCU_33_32_MSK 0x00000003
+#define MONITOR_BUS_MCU_33_32_I_MSK 0xfffffffc
+#define MONITOR_BUS_MCU_33_32_SFT 0
+#define MONITOR_BUS_MCU_33_32_HI 1
+#define MONITOR_BUS_MCU_33_32_SZ 2
+#define TB_ADR_SEL_MSK 0x0000ffff
+#define TB_ADR_SEL_I_MSK 0xffff0000
+#define TB_ADR_SEL_SFT 0
+#define TB_ADR_SEL_HI 15
+#define TB_ADR_SEL_SZ 16
+#define TB_CS_MSK 0x80000000
+#define TB_CS_I_MSK 0x7fffffff
+#define TB_CS_SFT 31
+#define TB_CS_HI 31
+#define TB_CS_SZ 1
+#define TB_RDATA_MSK 0xffffffff
+#define TB_RDATA_I_MSK 0x00000000
+#define TB_RDATA_SFT 0
+#define TB_RDATA_HI 31
+#define TB_RDATA_SZ 32
+#define UART_W2B_EN_MSK 0x00000001
+#define UART_W2B_EN_I_MSK 0xfffffffe
+#define UART_W2B_EN_SFT 0
+#define UART_W2B_EN_HI 0
+#define UART_W2B_EN_SZ 1
+#define DATA_UART_W2B_EN_MSK 0x00000010
+#define DATA_UART_W2B_EN_I_MSK 0xffffffef
+#define DATA_UART_W2B_EN_SFT 4
+#define DATA_UART_W2B_EN_HI 4
+#define DATA_UART_W2B_EN_SZ 1
+#define AHB_ILL_ADDR_MSK 0xffffffff
+#define AHB_ILL_ADDR_I_MSK 0x00000000
+#define AHB_ILL_ADDR_SFT 0
+#define AHB_ILL_ADDR_HI 31
+#define AHB_ILL_ADDR_SZ 32
+#define AHB_FEN_ADDR_MSK 0xffffffff
+#define AHB_FEN_ADDR_I_MSK 0x00000000
+#define AHB_FEN_ADDR_SFT 0
+#define AHB_FEN_ADDR_HI 31
+#define AHB_FEN_ADDR_SZ 32
+#define ILL_ADDR_CLR_MSK 0x00000001
+#define ILL_ADDR_CLR_I_MSK 0xfffffffe
+#define ILL_ADDR_CLR_SFT 0
+#define ILL_ADDR_CLR_HI 0
+#define ILL_ADDR_CLR_SZ 1
+#define FENCE_HIT_CLR_MSK 0x00000002
+#define FENCE_HIT_CLR_I_MSK 0xfffffffd
+#define FENCE_HIT_CLR_SFT 1
+#define FENCE_HIT_CLR_HI 1
+#define FENCE_HIT_CLR_SZ 1
+#define ILL_ADDR_INT_MSK 0x00000010
+#define ILL_ADDR_INT_I_MSK 0xffffffef
+#define ILL_ADDR_INT_SFT 4
+#define ILL_ADDR_INT_HI 4
+#define ILL_ADDR_INT_SZ 1
+#define FENCE_HIT_INT_MSK 0x00000020
+#define FENCE_HIT_INT_I_MSK 0xffffffdf
+#define FENCE_HIT_INT_SFT 5
+#define FENCE_HIT_INT_HI 5
+#define FENCE_HIT_INT_SZ 1
+#define PWM_INI_VALUE_P_A_MSK 0x000000ff
+#define PWM_INI_VALUE_P_A_I_MSK 0xffffff00
+#define PWM_INI_VALUE_P_A_SFT 0
+#define PWM_INI_VALUE_P_A_HI 7
+#define PWM_INI_VALUE_P_A_SZ 8
+#define PWM_INI_VALUE_N_A_MSK 0x0000ff00
+#define PWM_INI_VALUE_N_A_I_MSK 0xffff00ff
+#define PWM_INI_VALUE_N_A_SFT 8
+#define PWM_INI_VALUE_N_A_HI 15
+#define PWM_INI_VALUE_N_A_SZ 8
+#define PWM_POST_SCALER_A_MSK 0x000f0000
+#define PWM_POST_SCALER_A_I_MSK 0xfff0ffff
+#define PWM_POST_SCALER_A_SFT 16
+#define PWM_POST_SCALER_A_HI 19
+#define PWM_POST_SCALER_A_SZ 4
+#define PWM_ALWAYSON_A_MSK 0x20000000
+#define PWM_ALWAYSON_A_I_MSK 0xdfffffff
+#define PWM_ALWAYSON_A_SFT 29
+#define PWM_ALWAYSON_A_HI 29
+#define PWM_ALWAYSON_A_SZ 1
+#define PWM_INVERT_A_MSK 0x40000000
+#define PWM_INVERT_A_I_MSK 0xbfffffff
+#define PWM_INVERT_A_SFT 30
+#define PWM_INVERT_A_HI 30
+#define PWM_INVERT_A_SZ 1
+#define PWM_ENABLE_A_MSK 0x80000000
+#define PWM_ENABLE_A_I_MSK 0x7fffffff
+#define PWM_ENABLE_A_SFT 31
+#define PWM_ENABLE_A_HI 31
+#define PWM_ENABLE_A_SZ 1
+#define PWM_INI_VALUE_P_B_MSK 0x000000ff
+#define PWM_INI_VALUE_P_B_I_MSK 0xffffff00
+#define PWM_INI_VALUE_P_B_SFT 0
+#define PWM_INI_VALUE_P_B_HI 7
+#define PWM_INI_VALUE_P_B_SZ 8
+#define PWM_INI_VALUE_N_B_MSK 0x0000ff00
+#define PWM_INI_VALUE_N_B_I_MSK 0xffff00ff
+#define PWM_INI_VALUE_N_B_SFT 8
+#define PWM_INI_VALUE_N_B_HI 15
+#define PWM_INI_VALUE_N_B_SZ 8
+#define PWM_POST_SCALER_B_MSK 0x000f0000
+#define PWM_POST_SCALER_B_I_MSK 0xfff0ffff
+#define PWM_POST_SCALER_B_SFT 16
+#define PWM_POST_SCALER_B_HI 19
+#define PWM_POST_SCALER_B_SZ 4
+#define PWM_ALWAYSON_B_MSK 0x20000000
+#define PWM_ALWAYSON_B_I_MSK 0xdfffffff
+#define PWM_ALWAYSON_B_SFT 29
+#define PWM_ALWAYSON_B_HI 29
+#define PWM_ALWAYSON_B_SZ 1
+#define PWM_INVERT_B_MSK 0x40000000
+#define PWM_INVERT_B_I_MSK 0xbfffffff
+#define PWM_INVERT_B_SFT 30
+#define PWM_INVERT_B_HI 30
+#define PWM_INVERT_B_SZ 1
+#define PWM_ENABLE_B_MSK 0x80000000
+#define PWM_ENABLE_B_I_MSK 0x7fffffff
+#define PWM_ENABLE_B_SFT 31
+#define PWM_ENABLE_B_HI 31
+#define PWM_ENABLE_B_SZ 1
+#define HBUSREQ_LOCK_MSK 0x00001fff
+#define HBUSREQ_LOCK_I_MSK 0xffffe000
+#define HBUSREQ_LOCK_SFT 0
+#define HBUSREQ_LOCK_HI 12
+#define HBUSREQ_LOCK_SZ 13
+#define HBURST_LOCK_MSK 0x00001fff
+#define HBURST_LOCK_I_MSK 0xffffe000
+#define HBURST_LOCK_SFT 0
+#define HBURST_LOCK_HI 12
+#define HBURST_LOCK_SZ 13
+#define PRESCALER_USTIMER_MSK 0x000001ff
+#define PRESCALER_USTIMER_I_MSK 0xfffffe00
+#define PRESCALER_USTIMER_SFT 0
+#define PRESCALER_USTIMER_HI 8
+#define PRESCALER_USTIMER_SZ 9
+#define MODE_REG_IN_MMU_MSK 0x0000ffff
+#define MODE_REG_IN_MMU_I_MSK 0xffff0000
+#define MODE_REG_IN_MMU_SFT 0
+#define MODE_REG_IN_MMU_HI 15
+#define MODE_REG_IN_MMU_SZ 16
+#define MODE_REG_OUT_MMU_MSK 0x0000ffff
+#define MODE_REG_OUT_MMU_I_MSK 0xffff0000
+#define MODE_REG_OUT_MMU_SFT 0
+#define MODE_REG_OUT_MMU_HI 15
+#define MODE_REG_OUT_MMU_SZ 16
+#define MODE_REG_SO_MMU_MSK 0x80000000
+#define MODE_REG_SO_MMU_I_MSK 0x7fffffff
+#define MODE_REG_SO_MMU_SFT 31
+#define MODE_REG_SO_MMU_HI 31
+#define MODE_REG_SO_MMU_SZ 1
+#define MONITOR_BUS_MMU_MSK 0x0007ffff
+#define MONITOR_BUS_MMU_I_MSK 0xfff80000
+#define MONITOR_BUS_MMU_SFT 0
+#define MONITOR_BUS_MMU_HI 18
+#define MONITOR_BUS_MMU_SZ 19
+#define TEST_MODE0_MSK 0x00000001
+#define TEST_MODE0_I_MSK 0xfffffffe
+#define TEST_MODE0_SFT 0
+#define TEST_MODE0_HI 0
+#define TEST_MODE0_SZ 1
+#define TEST_MODE1_MSK 0x00000002
+#define TEST_MODE1_I_MSK 0xfffffffd
+#define TEST_MODE1_SFT 1
+#define TEST_MODE1_HI 1
+#define TEST_MODE1_SZ 1
+#define TEST_MODE2_MSK 0x00000004
+#define TEST_MODE2_I_MSK 0xfffffffb
+#define TEST_MODE2_SFT 2
+#define TEST_MODE2_HI 2
+#define TEST_MODE2_SZ 1
+#define TEST_MODE3_MSK 0x00000008
+#define TEST_MODE3_I_MSK 0xfffffff7
+#define TEST_MODE3_SFT 3
+#define TEST_MODE3_HI 3
+#define TEST_MODE3_SZ 1
+#define TEST_MODE4_MSK 0x00000010
+#define TEST_MODE4_I_MSK 0xffffffef
+#define TEST_MODE4_SFT 4
+#define TEST_MODE4_HI 4
+#define TEST_MODE4_SZ 1
+#define TEST_MODE_ALL_MSK 0x00000020
+#define TEST_MODE_ALL_I_MSK 0xffffffdf
+#define TEST_MODE_ALL_SFT 5
+#define TEST_MODE_ALL_HI 5
+#define TEST_MODE_ALL_SZ 1
+#define WDT_INIT_MSK 0x00000001
+#define WDT_INIT_I_MSK 0xfffffffe
+#define WDT_INIT_SFT 0
+#define WDT_INIT_HI 0
+#define WDT_INIT_SZ 1
+#define SD_HOST_INIT_MSK 0x00000002
+#define SD_HOST_INIT_I_MSK 0xfffffffd
+#define SD_HOST_INIT_SFT 1
+#define SD_HOST_INIT_HI 1
+#define SD_HOST_INIT_SZ 1
+#define ALLOW_SD_RESET_MSK 0x00000001
+#define ALLOW_SD_RESET_I_MSK 0xfffffffe
+#define ALLOW_SD_RESET_SFT 0
+#define ALLOW_SD_RESET_HI 0
+#define ALLOW_SD_RESET_SZ 1
+#define UART_NRTS_MSK 0x00000001
+#define UART_NRTS_I_MSK 0xfffffffe
+#define UART_NRTS_SFT 0
+#define UART_NRTS_HI 0
+#define UART_NRTS_SZ 1
+#define UART_NCTS_MSK 0x00000002
+#define UART_NCTS_I_MSK 0xfffffffd
+#define UART_NCTS_SFT 1
+#define UART_NCTS_HI 1
+#define UART_NCTS_SZ 1
+#define TU0_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU0_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU0_TM_INIT_VALUE_SFT 0
+#define TU0_TM_INIT_VALUE_HI 15
+#define TU0_TM_INIT_VALUE_SZ 16
+#define TU0_TM_MODE_MSK 0x00010000
+#define TU0_TM_MODE_I_MSK 0xfffeffff
+#define TU0_TM_MODE_SFT 16
+#define TU0_TM_MODE_HI 16
+#define TU0_TM_MODE_SZ 1
+#define TU0_TM_INT_STS_DONE_MSK 0x00020000
+#define TU0_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU0_TM_INT_STS_DONE_SFT 17
+#define TU0_TM_INT_STS_DONE_HI 17
+#define TU0_TM_INT_STS_DONE_SZ 1
+#define TU0_TM_INT_MASK_MSK 0x00040000
+#define TU0_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU0_TM_INT_MASK_SFT 18
+#define TU0_TM_INT_MASK_HI 18
+#define TU0_TM_INT_MASK_SZ 1
+#define TU0_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU0_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU0_TM_CUR_VALUE_SFT 0
+#define TU0_TM_CUR_VALUE_HI 15
+#define TU0_TM_CUR_VALUE_SZ 16
+#define TU1_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU1_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU1_TM_INIT_VALUE_SFT 0
+#define TU1_TM_INIT_VALUE_HI 15
+#define TU1_TM_INIT_VALUE_SZ 16
+#define TU1_TM_MODE_MSK 0x00010000
+#define TU1_TM_MODE_I_MSK 0xfffeffff
+#define TU1_TM_MODE_SFT 16
+#define TU1_TM_MODE_HI 16
+#define TU1_TM_MODE_SZ 1
+#define TU1_TM_INT_STS_DONE_MSK 0x00020000
+#define TU1_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU1_TM_INT_STS_DONE_SFT 17
+#define TU1_TM_INT_STS_DONE_HI 17
+#define TU1_TM_INT_STS_DONE_SZ 1
+#define TU1_TM_INT_MASK_MSK 0x00040000
+#define TU1_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU1_TM_INT_MASK_SFT 18
+#define TU1_TM_INT_MASK_HI 18
+#define TU1_TM_INT_MASK_SZ 1
+#define TU1_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU1_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU1_TM_CUR_VALUE_SFT 0
+#define TU1_TM_CUR_VALUE_HI 15
+#define TU1_TM_CUR_VALUE_SZ 16
+#define TU2_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU2_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU2_TM_INIT_VALUE_SFT 0
+#define TU2_TM_INIT_VALUE_HI 15
+#define TU2_TM_INIT_VALUE_SZ 16
+#define TU2_TM_MODE_MSK 0x00010000
+#define TU2_TM_MODE_I_MSK 0xfffeffff
+#define TU2_TM_MODE_SFT 16
+#define TU2_TM_MODE_HI 16
+#define TU2_TM_MODE_SZ 1
+#define TU2_TM_INT_STS_DONE_MSK 0x00020000
+#define TU2_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU2_TM_INT_STS_DONE_SFT 17
+#define TU2_TM_INT_STS_DONE_HI 17
+#define TU2_TM_INT_STS_DONE_SZ 1
+#define TU2_TM_INT_MASK_MSK 0x00040000
+#define TU2_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU2_TM_INT_MASK_SFT 18
+#define TU2_TM_INT_MASK_HI 18
+#define TU2_TM_INT_MASK_SZ 1
+#define TU2_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU2_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU2_TM_CUR_VALUE_SFT 0
+#define TU2_TM_CUR_VALUE_HI 15
+#define TU2_TM_CUR_VALUE_SZ 16
+#define TU3_TM_INIT_VALUE_MSK 0x0000ffff
+#define TU3_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TU3_TM_INIT_VALUE_SFT 0
+#define TU3_TM_INIT_VALUE_HI 15
+#define TU3_TM_INIT_VALUE_SZ 16
+#define TU3_TM_MODE_MSK 0x00010000
+#define TU3_TM_MODE_I_MSK 0xfffeffff
+#define TU3_TM_MODE_SFT 16
+#define TU3_TM_MODE_HI 16
+#define TU3_TM_MODE_SZ 1
+#define TU3_TM_INT_STS_DONE_MSK 0x00020000
+#define TU3_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TU3_TM_INT_STS_DONE_SFT 17
+#define TU3_TM_INT_STS_DONE_HI 17
+#define TU3_TM_INT_STS_DONE_SZ 1
+#define TU3_TM_INT_MASK_MSK 0x00040000
+#define TU3_TM_INT_MASK_I_MSK 0xfffbffff
+#define TU3_TM_INT_MASK_SFT 18
+#define TU3_TM_INT_MASK_HI 18
+#define TU3_TM_INT_MASK_SZ 1
+#define TU3_TM_CUR_VALUE_MSK 0x0000ffff
+#define TU3_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TU3_TM_CUR_VALUE_SFT 0
+#define TU3_TM_CUR_VALUE_HI 15
+#define TU3_TM_CUR_VALUE_SZ 16
+#define TM0_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM0_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM0_TM_INIT_VALUE_SFT 0
+#define TM0_TM_INIT_VALUE_HI 15
+#define TM0_TM_INIT_VALUE_SZ 16
+#define TM0_TM_MODE_MSK 0x00010000
+#define TM0_TM_MODE_I_MSK 0xfffeffff
+#define TM0_TM_MODE_SFT 16
+#define TM0_TM_MODE_HI 16
+#define TM0_TM_MODE_SZ 1
+#define TM0_TM_INT_STS_DONE_MSK 0x00020000
+#define TM0_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM0_TM_INT_STS_DONE_SFT 17
+#define TM0_TM_INT_STS_DONE_HI 17
+#define TM0_TM_INT_STS_DONE_SZ 1
+#define TM0_TM_INT_MASK_MSK 0x00040000
+#define TM0_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM0_TM_INT_MASK_SFT 18
+#define TM0_TM_INT_MASK_HI 18
+#define TM0_TM_INT_MASK_SZ 1
+#define TM0_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM0_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM0_TM_CUR_VALUE_SFT 0
+#define TM0_TM_CUR_VALUE_HI 15
+#define TM0_TM_CUR_VALUE_SZ 16
+#define TM1_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM1_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM1_TM_INIT_VALUE_SFT 0
+#define TM1_TM_INIT_VALUE_HI 15
+#define TM1_TM_INIT_VALUE_SZ 16
+#define TM1_TM_MODE_MSK 0x00010000
+#define TM1_TM_MODE_I_MSK 0xfffeffff
+#define TM1_TM_MODE_SFT 16
+#define TM1_TM_MODE_HI 16
+#define TM1_TM_MODE_SZ 1
+#define TM1_TM_INT_STS_DONE_MSK 0x00020000
+#define TM1_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM1_TM_INT_STS_DONE_SFT 17
+#define TM1_TM_INT_STS_DONE_HI 17
+#define TM1_TM_INT_STS_DONE_SZ 1
+#define TM1_TM_INT_MASK_MSK 0x00040000
+#define TM1_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM1_TM_INT_MASK_SFT 18
+#define TM1_TM_INT_MASK_HI 18
+#define TM1_TM_INT_MASK_SZ 1
+#define TM1_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM1_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM1_TM_CUR_VALUE_SFT 0
+#define TM1_TM_CUR_VALUE_HI 15
+#define TM1_TM_CUR_VALUE_SZ 16
+#define TM2_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM2_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM2_TM_INIT_VALUE_SFT 0
+#define TM2_TM_INIT_VALUE_HI 15
+#define TM2_TM_INIT_VALUE_SZ 16
+#define TM2_TM_MODE_MSK 0x00010000
+#define TM2_TM_MODE_I_MSK 0xfffeffff
+#define TM2_TM_MODE_SFT 16
+#define TM2_TM_MODE_HI 16
+#define TM2_TM_MODE_SZ 1
+#define TM2_TM_INT_STS_DONE_MSK 0x00020000
+#define TM2_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM2_TM_INT_STS_DONE_SFT 17
+#define TM2_TM_INT_STS_DONE_HI 17
+#define TM2_TM_INT_STS_DONE_SZ 1
+#define TM2_TM_INT_MASK_MSK 0x00040000
+#define TM2_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM2_TM_INT_MASK_SFT 18
+#define TM2_TM_INT_MASK_HI 18
+#define TM2_TM_INT_MASK_SZ 1
+#define TM2_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM2_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM2_TM_CUR_VALUE_SFT 0
+#define TM2_TM_CUR_VALUE_HI 15
+#define TM2_TM_CUR_VALUE_SZ 16
+#define TM3_TM_INIT_VALUE_MSK 0x0000ffff
+#define TM3_TM_INIT_VALUE_I_MSK 0xffff0000
+#define TM3_TM_INIT_VALUE_SFT 0
+#define TM3_TM_INIT_VALUE_HI 15
+#define TM3_TM_INIT_VALUE_SZ 16
+#define TM3_TM_MODE_MSK 0x00010000
+#define TM3_TM_MODE_I_MSK 0xfffeffff
+#define TM3_TM_MODE_SFT 16
+#define TM3_TM_MODE_HI 16
+#define TM3_TM_MODE_SZ 1
+#define TM3_TM_INT_STS_DONE_MSK 0x00020000
+#define TM3_TM_INT_STS_DONE_I_MSK 0xfffdffff
+#define TM3_TM_INT_STS_DONE_SFT 17
+#define TM3_TM_INT_STS_DONE_HI 17
+#define TM3_TM_INT_STS_DONE_SZ 1
+#define TM3_TM_INT_MASK_MSK 0x00040000
+#define TM3_TM_INT_MASK_I_MSK 0xfffbffff
+#define TM3_TM_INT_MASK_SFT 18
+#define TM3_TM_INT_MASK_HI 18
+#define TM3_TM_INT_MASK_SZ 1
+#define TM3_TM_CUR_VALUE_MSK 0x0000ffff
+#define TM3_TM_CUR_VALUE_I_MSK 0xffff0000
+#define TM3_TM_CUR_VALUE_SFT 0
+#define TM3_TM_CUR_VALUE_HI 15
+#define TM3_TM_CUR_VALUE_SZ 16
+#define MCU_WDT_TIME_CNT_MSK 0x0000ffff
+#define MCU_WDT_TIME_CNT_I_MSK 0xffff0000
+#define MCU_WDT_TIME_CNT_SFT 0
+#define MCU_WDT_TIME_CNT_HI 15
+#define MCU_WDT_TIME_CNT_SZ 16
+#define MCU_WDT_STATUS_MSK 0x00020000
+#define MCU_WDT_STATUS_I_MSK 0xfffdffff
+#define MCU_WDT_STATUS_SFT 17
+#define MCU_WDT_STATUS_HI 17
+#define MCU_WDT_STATUS_SZ 1
+#define MCU_WDOG_ENA_MSK 0x80000000
+#define MCU_WDOG_ENA_I_MSK 0x7fffffff
+#define MCU_WDOG_ENA_SFT 31
+#define MCU_WDOG_ENA_HI 31
+#define MCU_WDOG_ENA_SZ 1
+#define SYS_WDT_TIME_CNT_MSK 0x0000ffff
+#define SYS_WDT_TIME_CNT_I_MSK 0xffff0000
+#define SYS_WDT_TIME_CNT_SFT 0
+#define SYS_WDT_TIME_CNT_HI 15
+#define SYS_WDT_TIME_CNT_SZ 16
+#define SYS_WDT_STATUS_MSK 0x00020000
+#define SYS_WDT_STATUS_I_MSK 0xfffdffff
+#define SYS_WDT_STATUS_SFT 17
+#define SYS_WDT_STATUS_HI 17
+#define SYS_WDT_STATUS_SZ 1
+#define SYS_WDOG_ENA_MSK 0x80000000
+#define SYS_WDOG_ENA_I_MSK 0x7fffffff
+#define SYS_WDOG_ENA_SFT 31
+#define SYS_WDOG_ENA_HI 31
+#define SYS_WDOG_ENA_SZ 1
+#define XLNA_EN_O_OE_MSK 0x00000001
+#define XLNA_EN_O_OE_I_MSK 0xfffffffe
+#define XLNA_EN_O_OE_SFT 0
+#define XLNA_EN_O_OE_HI 0
+#define XLNA_EN_O_OE_SZ 1
+#define XLNA_EN_O_PE_MSK 0x00000002
+#define XLNA_EN_O_PE_I_MSK 0xfffffffd
+#define XLNA_EN_O_PE_SFT 1
+#define XLNA_EN_O_PE_HI 1
+#define XLNA_EN_O_PE_SZ 1
+#define PAD6_IE_MSK 0x00000008
+#define PAD6_IE_I_MSK 0xfffffff7
+#define PAD6_IE_SFT 3
+#define PAD6_IE_HI 3
+#define PAD6_IE_SZ 1
+#define PAD6_SEL_I_MSK 0x00000030
+#define PAD6_SEL_I_I_MSK 0xffffffcf
+#define PAD6_SEL_I_SFT 4
+#define PAD6_SEL_I_HI 5
+#define PAD6_SEL_I_SZ 2
+#define PAD6_OD_MSK 0x00000100
+#define PAD6_OD_I_MSK 0xfffffeff
+#define PAD6_OD_SFT 8
+#define PAD6_OD_HI 8
+#define PAD6_OD_SZ 1
+#define PAD6_SEL_O_MSK 0x00001000
+#define PAD6_SEL_O_I_MSK 0xffffefff
+#define PAD6_SEL_O_SFT 12
+#define PAD6_SEL_O_HI 12
+#define PAD6_SEL_O_SZ 1
+#define XLNA_EN_O_C_MSK 0x10000000
+#define XLNA_EN_O_C_I_MSK 0xefffffff
+#define XLNA_EN_O_C_SFT 28
+#define XLNA_EN_O_C_HI 28
+#define XLNA_EN_O_C_SZ 1
+#define WIFI_TX_SW_O_OE_MSK 0x00000001
+#define WIFI_TX_SW_O_OE_I_MSK 0xfffffffe
+#define WIFI_TX_SW_O_OE_SFT 0
+#define WIFI_TX_SW_O_OE_HI 0
+#define WIFI_TX_SW_O_OE_SZ 1
+#define WIFI_TX_SW_O_PE_MSK 0x00000002
+#define WIFI_TX_SW_O_PE_I_MSK 0xfffffffd
+#define WIFI_TX_SW_O_PE_SFT 1
+#define WIFI_TX_SW_O_PE_HI 1
+#define WIFI_TX_SW_O_PE_SZ 1
+#define PAD7_IE_MSK 0x00000008
+#define PAD7_IE_I_MSK 0xfffffff7
+#define PAD7_IE_SFT 3
+#define PAD7_IE_HI 3
+#define PAD7_IE_SZ 1
+#define PAD7_SEL_I_MSK 0x00000030
+#define PAD7_SEL_I_I_MSK 0xffffffcf
+#define PAD7_SEL_I_SFT 4
+#define PAD7_SEL_I_HI 5
+#define PAD7_SEL_I_SZ 2
+#define PAD7_OD_MSK 0x00000100
+#define PAD7_OD_I_MSK 0xfffffeff
+#define PAD7_OD_SFT 8
+#define PAD7_OD_HI 8
+#define PAD7_OD_SZ 1
+#define PAD7_SEL_O_MSK 0x00001000
+#define PAD7_SEL_O_I_MSK 0xffffefff
+#define PAD7_SEL_O_SFT 12
+#define PAD7_SEL_O_HI 12
+#define PAD7_SEL_O_SZ 1
+#define WIFI_TX_SW_O_C_MSK 0x10000000
+#define WIFI_TX_SW_O_C_I_MSK 0xefffffff
+#define WIFI_TX_SW_O_C_SFT 28
+#define WIFI_TX_SW_O_C_HI 28
+#define WIFI_TX_SW_O_C_SZ 1
+#define WIFI_RX_SW_O_OE_MSK 0x00000001
+#define WIFI_RX_SW_O_OE_I_MSK 0xfffffffe
+#define WIFI_RX_SW_O_OE_SFT 0
+#define WIFI_RX_SW_O_OE_HI 0
+#define WIFI_RX_SW_O_OE_SZ 1
+#define WIFI_RX_SW_O_PE_MSK 0x00000002
+#define WIFI_RX_SW_O_PE_I_MSK 0xfffffffd
+#define WIFI_RX_SW_O_PE_SFT 1
+#define WIFI_RX_SW_O_PE_HI 1
+#define WIFI_RX_SW_O_PE_SZ 1
+#define PAD8_IE_MSK 0x00000008
+#define PAD8_IE_I_MSK 0xfffffff7
+#define PAD8_IE_SFT 3
+#define PAD8_IE_HI 3
+#define PAD8_IE_SZ 1
+#define PAD8_SEL_I_MSK 0x00000030
+#define PAD8_SEL_I_I_MSK 0xffffffcf
+#define PAD8_SEL_I_SFT 4
+#define PAD8_SEL_I_HI 5
+#define PAD8_SEL_I_SZ 2
+#define PAD8_OD_MSK 0x00000100
+#define PAD8_OD_I_MSK 0xfffffeff
+#define PAD8_OD_SFT 8
+#define PAD8_OD_HI 8
+#define PAD8_OD_SZ 1
+#define WIFI_RX_SW_O_C_MSK 0x10000000
+#define WIFI_RX_SW_O_C_I_MSK 0xefffffff
+#define WIFI_RX_SW_O_C_SFT 28
+#define WIFI_RX_SW_O_C_HI 28
+#define WIFI_RX_SW_O_C_SZ 1
+#define BT_SW_O_OE_MSK 0x00000001
+#define BT_SW_O_OE_I_MSK 0xfffffffe
+#define BT_SW_O_OE_SFT 0
+#define BT_SW_O_OE_HI 0
+#define BT_SW_O_OE_SZ 1
+#define BT_SW_O_PE_MSK 0x00000002
+#define BT_SW_O_PE_I_MSK 0xfffffffd
+#define BT_SW_O_PE_SFT 1
+#define BT_SW_O_PE_HI 1
+#define BT_SW_O_PE_SZ 1
+#define PAD9_IE_MSK 0x00000008
+#define PAD9_IE_I_MSK 0xfffffff7
+#define PAD9_IE_SFT 3
+#define PAD9_IE_HI 3
+#define PAD9_IE_SZ 1
+#define PAD9_SEL_I_MSK 0x00000030
+#define PAD9_SEL_I_I_MSK 0xffffffcf
+#define PAD9_SEL_I_SFT 4
+#define PAD9_SEL_I_HI 5
+#define PAD9_SEL_I_SZ 2
+#define PAD9_OD_MSK 0x00000100
+#define PAD9_OD_I_MSK 0xfffffeff
+#define PAD9_OD_SFT 8
+#define PAD9_OD_HI 8
+#define PAD9_OD_SZ 1
+#define PAD9_SEL_O_MSK 0x00001000
+#define PAD9_SEL_O_I_MSK 0xffffefff
+#define PAD9_SEL_O_SFT 12
+#define PAD9_SEL_O_HI 12
+#define PAD9_SEL_O_SZ 1
+#define BT_SW_O_C_MSK 0x10000000
+#define BT_SW_O_C_I_MSK 0xefffffff
+#define BT_SW_O_C_SFT 28
+#define BT_SW_O_C_HI 28
+#define BT_SW_O_C_SZ 1
+#define XPA_EN_O_OE_MSK 0x00000001
+#define XPA_EN_O_OE_I_MSK 0xfffffffe
+#define XPA_EN_O_OE_SFT 0
+#define XPA_EN_O_OE_HI 0
+#define XPA_EN_O_OE_SZ 1
+#define XPA_EN_O_PE_MSK 0x00000002
+#define XPA_EN_O_PE_I_MSK 0xfffffffd
+#define XPA_EN_O_PE_SFT 1
+#define XPA_EN_O_PE_HI 1
+#define XPA_EN_O_PE_SZ 1
+#define PAD11_IE_MSK 0x00000008
+#define PAD11_IE_I_MSK 0xfffffff7
+#define PAD11_IE_SFT 3
+#define PAD11_IE_HI 3
+#define PAD11_IE_SZ 1
+#define PAD11_SEL_I_MSK 0x00000030
+#define PAD11_SEL_I_I_MSK 0xffffffcf
+#define PAD11_SEL_I_SFT 4
+#define PAD11_SEL_I_HI 5
+#define PAD11_SEL_I_SZ 2
+#define PAD11_OD_MSK 0x00000100
+#define PAD11_OD_I_MSK 0xfffffeff
+#define PAD11_OD_SFT 8
+#define PAD11_OD_HI 8
+#define PAD11_OD_SZ 1
+#define PAD11_SEL_O_MSK 0x00001000
+#define PAD11_SEL_O_I_MSK 0xffffefff
+#define PAD11_SEL_O_SFT 12
+#define PAD11_SEL_O_HI 12
+#define PAD11_SEL_O_SZ 1
+#define XPA_EN_O_C_MSK 0x10000000
+#define XPA_EN_O_C_I_MSK 0xefffffff
+#define XPA_EN_O_C_SFT 28
+#define XPA_EN_O_C_HI 28
+#define XPA_EN_O_C_SZ 1
+#define PAD15_OE_MSK 0x00000001
+#define PAD15_OE_I_MSK 0xfffffffe
+#define PAD15_OE_SFT 0
+#define PAD15_OE_HI 0
+#define PAD15_OE_SZ 1
+#define PAD15_PE_MSK 0x00000002
+#define PAD15_PE_I_MSK 0xfffffffd
+#define PAD15_PE_SFT 1
+#define PAD15_PE_HI 1
+#define PAD15_PE_SZ 1
+#define PAD15_DS_MSK 0x00000004
+#define PAD15_DS_I_MSK 0xfffffffb
+#define PAD15_DS_SFT 2
+#define PAD15_DS_HI 2
+#define PAD15_DS_SZ 1
+#define PAD15_IE_MSK 0x00000008
+#define PAD15_IE_I_MSK 0xfffffff7
+#define PAD15_IE_SFT 3
+#define PAD15_IE_HI 3
+#define PAD15_IE_SZ 1
+#define PAD15_SEL_I_MSK 0x00000030
+#define PAD15_SEL_I_I_MSK 0xffffffcf
+#define PAD15_SEL_I_SFT 4
+#define PAD15_SEL_I_HI 5
+#define PAD15_SEL_I_SZ 2
+#define PAD15_OD_MSK 0x00000100
+#define PAD15_OD_I_MSK 0xfffffeff
+#define PAD15_OD_SFT 8
+#define PAD15_OD_HI 8
+#define PAD15_OD_SZ 1
+#define PAD15_SEL_O_MSK 0x00001000
+#define PAD15_SEL_O_I_MSK 0xffffefff
+#define PAD15_SEL_O_SFT 12
+#define PAD15_SEL_O_HI 12
+#define PAD15_SEL_O_SZ 1
+#define TEST_1_ID_MSK 0x10000000
+#define TEST_1_ID_I_MSK 0xefffffff
+#define TEST_1_ID_SFT 28
+#define TEST_1_ID_HI 28
+#define TEST_1_ID_SZ 1
+#define PAD16_OE_MSK 0x00000001
+#define PAD16_OE_I_MSK 0xfffffffe
+#define PAD16_OE_SFT 0
+#define PAD16_OE_HI 0
+#define PAD16_OE_SZ 1
+#define PAD16_PE_MSK 0x00000002
+#define PAD16_PE_I_MSK 0xfffffffd
+#define PAD16_PE_SFT 1
+#define PAD16_PE_HI 1
+#define PAD16_PE_SZ 1
+#define PAD16_DS_MSK 0x00000004
+#define PAD16_DS_I_MSK 0xfffffffb
+#define PAD16_DS_SFT 2
+#define PAD16_DS_HI 2
+#define PAD16_DS_SZ 1
+#define PAD16_IE_MSK 0x00000008
+#define PAD16_IE_I_MSK 0xfffffff7
+#define PAD16_IE_SFT 3
+#define PAD16_IE_HI 3
+#define PAD16_IE_SZ 1
+#define PAD16_SEL_I_MSK 0x00000030
+#define PAD16_SEL_I_I_MSK 0xffffffcf
+#define PAD16_SEL_I_SFT 4
+#define PAD16_SEL_I_HI 5
+#define PAD16_SEL_I_SZ 2
+#define PAD16_OD_MSK 0x00000100
+#define PAD16_OD_I_MSK 0xfffffeff
+#define PAD16_OD_SFT 8
+#define PAD16_OD_HI 8
+#define PAD16_OD_SZ 1
+#define PAD16_SEL_O_MSK 0x00001000
+#define PAD16_SEL_O_I_MSK 0xffffefff
+#define PAD16_SEL_O_SFT 12
+#define PAD16_SEL_O_HI 12
+#define PAD16_SEL_O_SZ 1
+#define TEST_2_ID_MSK 0x10000000
+#define TEST_2_ID_I_MSK 0xefffffff
+#define TEST_2_ID_SFT 28
+#define TEST_2_ID_HI 28
+#define TEST_2_ID_SZ 1
+#define PAD17_OE_MSK 0x00000001
+#define PAD17_OE_I_MSK 0xfffffffe
+#define PAD17_OE_SFT 0
+#define PAD17_OE_HI 0
+#define PAD17_OE_SZ 1
+#define PAD17_PE_MSK 0x00000002
+#define PAD17_PE_I_MSK 0xfffffffd
+#define PAD17_PE_SFT 1
+#define PAD17_PE_HI 1
+#define PAD17_PE_SZ 1
+#define PAD17_DS_MSK 0x00000004
+#define PAD17_DS_I_MSK 0xfffffffb
+#define PAD17_DS_SFT 2
+#define PAD17_DS_HI 2
+#define PAD17_DS_SZ 1
+#define PAD17_IE_MSK 0x00000008
+#define PAD17_IE_I_MSK 0xfffffff7
+#define PAD17_IE_SFT 3
+#define PAD17_IE_HI 3
+#define PAD17_IE_SZ 1
+#define PAD17_SEL_I_MSK 0x00000030
+#define PAD17_SEL_I_I_MSK 0xffffffcf
+#define PAD17_SEL_I_SFT 4
+#define PAD17_SEL_I_HI 5
+#define PAD17_SEL_I_SZ 2
+#define PAD17_OD_MSK 0x00000100
+#define PAD17_OD_I_MSK 0xfffffeff
+#define PAD17_OD_SFT 8
+#define PAD17_OD_HI 8
+#define PAD17_OD_SZ 1
+#define PAD17_SEL_O_MSK 0x00001000
+#define PAD17_SEL_O_I_MSK 0xffffefff
+#define PAD17_SEL_O_SFT 12
+#define PAD17_SEL_O_HI 12
+#define PAD17_SEL_O_SZ 1
+#define TEST_3_ID_MSK 0x10000000
+#define TEST_3_ID_I_MSK 0xefffffff
+#define TEST_3_ID_SFT 28
+#define TEST_3_ID_HI 28
+#define TEST_3_ID_SZ 1
+#define PAD18_OE_MSK 0x00000001
+#define PAD18_OE_I_MSK 0xfffffffe
+#define PAD18_OE_SFT 0
+#define PAD18_OE_HI 0
+#define PAD18_OE_SZ 1
+#define PAD18_PE_MSK 0x00000002
+#define PAD18_PE_I_MSK 0xfffffffd
+#define PAD18_PE_SFT 1
+#define PAD18_PE_HI 1
+#define PAD18_PE_SZ 1
+#define PAD18_DS_MSK 0x00000004
+#define PAD18_DS_I_MSK 0xfffffffb
+#define PAD18_DS_SFT 2
+#define PAD18_DS_HI 2
+#define PAD18_DS_SZ 1
+#define PAD18_IE_MSK 0x00000008
+#define PAD18_IE_I_MSK 0xfffffff7
+#define PAD18_IE_SFT 3
+#define PAD18_IE_HI 3
+#define PAD18_IE_SZ 1
+#define PAD18_SEL_I_MSK 0x00000030
+#define PAD18_SEL_I_I_MSK 0xffffffcf
+#define PAD18_SEL_I_SFT 4
+#define PAD18_SEL_I_HI 5
+#define PAD18_SEL_I_SZ 2
+#define PAD18_OD_MSK 0x00000100
+#define PAD18_OD_I_MSK 0xfffffeff
+#define PAD18_OD_SFT 8
+#define PAD18_OD_HI 8
+#define PAD18_OD_SZ 1
+#define PAD18_SEL_O_MSK 0x00003000
+#define PAD18_SEL_O_I_MSK 0xffffcfff
+#define PAD18_SEL_O_SFT 12
+#define PAD18_SEL_O_HI 13
+#define PAD18_SEL_O_SZ 2
+#define TEST_4_ID_MSK 0x10000000
+#define TEST_4_ID_I_MSK 0xefffffff
+#define TEST_4_ID_SFT 28
+#define TEST_4_ID_HI 28
+#define TEST_4_ID_SZ 1
+#define PAD19_OE_MSK 0x00000001
+#define PAD19_OE_I_MSK 0xfffffffe
+#define PAD19_OE_SFT 0
+#define PAD19_OE_HI 0
+#define PAD19_OE_SZ 1
+#define PAD19_PE_MSK 0x00000002
+#define PAD19_PE_I_MSK 0xfffffffd
+#define PAD19_PE_SFT 1
+#define PAD19_PE_HI 1
+#define PAD19_PE_SZ 1
+#define PAD19_DS_MSK 0x00000004
+#define PAD19_DS_I_MSK 0xfffffffb
+#define PAD19_DS_SFT 2
+#define PAD19_DS_HI 2
+#define PAD19_DS_SZ 1
+#define PAD19_IE_MSK 0x00000008
+#define PAD19_IE_I_MSK 0xfffffff7
+#define PAD19_IE_SFT 3
+#define PAD19_IE_HI 3
+#define PAD19_IE_SZ 1
+#define PAD19_SEL_I_MSK 0x00000030
+#define PAD19_SEL_I_I_MSK 0xffffffcf
+#define PAD19_SEL_I_SFT 4
+#define PAD19_SEL_I_HI 5
+#define PAD19_SEL_I_SZ 2
+#define PAD19_OD_MSK 0x00000100
+#define PAD19_OD_I_MSK 0xfffffeff
+#define PAD19_OD_SFT 8
+#define PAD19_OD_HI 8
+#define PAD19_OD_SZ 1
+#define PAD19_SEL_O_MSK 0x00007000
+#define PAD19_SEL_O_I_MSK 0xffff8fff
+#define PAD19_SEL_O_SFT 12
+#define PAD19_SEL_O_HI 14
+#define PAD19_SEL_O_SZ 3
+#define SHORT_TO_20_ID_MSK 0x10000000
+#define SHORT_TO_20_ID_I_MSK 0xefffffff
+#define SHORT_TO_20_ID_SFT 28
+#define SHORT_TO_20_ID_HI 28
+#define SHORT_TO_20_ID_SZ 1
+#define PAD20_OE_MSK 0x00000001
+#define PAD20_OE_I_MSK 0xfffffffe
+#define PAD20_OE_SFT 0
+#define PAD20_OE_HI 0
+#define PAD20_OE_SZ 1
+#define PAD20_PE_MSK 0x00000002
+#define PAD20_PE_I_MSK 0xfffffffd
+#define PAD20_PE_SFT 1
+#define PAD20_PE_HI 1
+#define PAD20_PE_SZ 1
+#define PAD20_DS_MSK 0x00000004
+#define PAD20_DS_I_MSK 0xfffffffb
+#define PAD20_DS_SFT 2
+#define PAD20_DS_HI 2
+#define PAD20_DS_SZ 1
+#define PAD20_IE_MSK 0x00000008
+#define PAD20_IE_I_MSK 0xfffffff7
+#define PAD20_IE_SFT 3
+#define PAD20_IE_HI 3
+#define PAD20_IE_SZ 1
+#define PAD20_SEL_I_MSK 0x000000f0
+#define PAD20_SEL_I_I_MSK 0xffffff0f
+#define PAD20_SEL_I_SFT 4
+#define PAD20_SEL_I_HI 7
+#define PAD20_SEL_I_SZ 4
+#define PAD20_OD_MSK 0x00000100
+#define PAD20_OD_I_MSK 0xfffffeff
+#define PAD20_OD_SFT 8
+#define PAD20_OD_HI 8
+#define PAD20_OD_SZ 1
+#define PAD20_SEL_O_MSK 0x00003000
+#define PAD20_SEL_O_I_MSK 0xffffcfff
+#define PAD20_SEL_O_SFT 12
+#define PAD20_SEL_O_HI 13
+#define PAD20_SEL_O_SZ 2
+#define STRAP0_MSK 0x08000000
+#define STRAP0_I_MSK 0xf7ffffff
+#define STRAP0_SFT 27
+#define STRAP0_HI 27
+#define STRAP0_SZ 1
+#define GPIO_TEST_1_ID_MSK 0x10000000
+#define GPIO_TEST_1_ID_I_MSK 0xefffffff
+#define GPIO_TEST_1_ID_SFT 28
+#define GPIO_TEST_1_ID_HI 28
+#define GPIO_TEST_1_ID_SZ 1
+#define PAD21_OE_MSK 0x00000001
+#define PAD21_OE_I_MSK 0xfffffffe
+#define PAD21_OE_SFT 0
+#define PAD21_OE_HI 0
+#define PAD21_OE_SZ 1
+#define PAD21_PE_MSK 0x00000002
+#define PAD21_PE_I_MSK 0xfffffffd
+#define PAD21_PE_SFT 1
+#define PAD21_PE_HI 1
+#define PAD21_PE_SZ 1
+#define PAD21_DS_MSK 0x00000004
+#define PAD21_DS_I_MSK 0xfffffffb
+#define PAD21_DS_SFT 2
+#define PAD21_DS_HI 2
+#define PAD21_DS_SZ 1
+#define PAD21_IE_MSK 0x00000008
+#define PAD21_IE_I_MSK 0xfffffff7
+#define PAD21_IE_SFT 3
+#define PAD21_IE_HI 3
+#define PAD21_IE_SZ 1
+#define PAD21_SEL_I_MSK 0x00000070
+#define PAD21_SEL_I_I_MSK 0xffffff8f
+#define PAD21_SEL_I_SFT 4
+#define PAD21_SEL_I_HI 6
+#define PAD21_SEL_I_SZ 3
+#define PAD21_OD_MSK 0x00000100
+#define PAD21_OD_I_MSK 0xfffffeff
+#define PAD21_OD_SFT 8
+#define PAD21_OD_HI 8
+#define PAD21_OD_SZ 1
+#define PAD21_SEL_O_MSK 0x00003000
+#define PAD21_SEL_O_I_MSK 0xffffcfff
+#define PAD21_SEL_O_SFT 12
+#define PAD21_SEL_O_HI 13
+#define PAD21_SEL_O_SZ 2
+#define STRAP3_MSK 0x08000000
+#define STRAP3_I_MSK 0xf7ffffff
+#define STRAP3_SFT 27
+#define STRAP3_HI 27
+#define STRAP3_SZ 1
+#define GPIO_TEST_2_ID_MSK 0x10000000
+#define GPIO_TEST_2_ID_I_MSK 0xefffffff
+#define GPIO_TEST_2_ID_SFT 28
+#define GPIO_TEST_2_ID_HI 28
+#define GPIO_TEST_2_ID_SZ 1
+#define PAD22_OE_MSK 0x00000001
+#define PAD22_OE_I_MSK 0xfffffffe
+#define PAD22_OE_SFT 0
+#define PAD22_OE_HI 0
+#define PAD22_OE_SZ 1
+#define PAD22_PE_MSK 0x00000002
+#define PAD22_PE_I_MSK 0xfffffffd
+#define PAD22_PE_SFT 1
+#define PAD22_PE_HI 1
+#define PAD22_PE_SZ 1
+#define PAD22_DS_MSK 0x00000004
+#define PAD22_DS_I_MSK 0xfffffffb
+#define PAD22_DS_SFT 2
+#define PAD22_DS_HI 2
+#define PAD22_DS_SZ 1
+#define PAD22_IE_MSK 0x00000008
+#define PAD22_IE_I_MSK 0xfffffff7
+#define PAD22_IE_SFT 3
+#define PAD22_IE_HI 3
+#define PAD22_IE_SZ 1
+#define PAD22_SEL_I_MSK 0x00000070
+#define PAD22_SEL_I_I_MSK 0xffffff8f
+#define PAD22_SEL_I_SFT 4
+#define PAD22_SEL_I_HI 6
+#define PAD22_SEL_I_SZ 3
+#define PAD22_OD_MSK 0x00000100
+#define PAD22_OD_I_MSK 0xfffffeff
+#define PAD22_OD_SFT 8
+#define PAD22_OD_HI 8
+#define PAD22_OD_SZ 1
+#define PAD22_SEL_O_MSK 0x00007000
+#define PAD22_SEL_O_I_MSK 0xffff8fff
+#define PAD22_SEL_O_SFT 12
+#define PAD22_SEL_O_HI 14
+#define PAD22_SEL_O_SZ 3
+#define PAD22_SEL_OE_MSK 0x00100000
+#define PAD22_SEL_OE_I_MSK 0xffefffff
+#define PAD22_SEL_OE_SFT 20
+#define PAD22_SEL_OE_HI 20
+#define PAD22_SEL_OE_SZ 1
+#define GPIO_TEST_3_ID_MSK 0x10000000
+#define GPIO_TEST_3_ID_I_MSK 0xefffffff
+#define GPIO_TEST_3_ID_SFT 28
+#define GPIO_TEST_3_ID_HI 28
+#define GPIO_TEST_3_ID_SZ 1
+#define PAD24_OE_MSK 0x00000001
+#define PAD24_OE_I_MSK 0xfffffffe
+#define PAD24_OE_SFT 0
+#define PAD24_OE_HI 0
+#define PAD24_OE_SZ 1
+#define PAD24_PE_MSK 0x00000002
+#define PAD24_PE_I_MSK 0xfffffffd
+#define PAD24_PE_SFT 1
+#define PAD24_PE_HI 1
+#define PAD24_PE_SZ 1
+#define PAD24_DS_MSK 0x00000004
+#define PAD24_DS_I_MSK 0xfffffffb
+#define PAD24_DS_SFT 2
+#define PAD24_DS_HI 2
+#define PAD24_DS_SZ 1
+#define PAD24_IE_MSK 0x00000008
+#define PAD24_IE_I_MSK 0xfffffff7
+#define PAD24_IE_SFT 3
+#define PAD24_IE_HI 3
+#define PAD24_IE_SZ 1
+#define PAD24_SEL_I_MSK 0x00000030
+#define PAD24_SEL_I_I_MSK 0xffffffcf
+#define PAD24_SEL_I_SFT 4
+#define PAD24_SEL_I_HI 5
+#define PAD24_SEL_I_SZ 2
+#define PAD24_OD_MSK 0x00000100
+#define PAD24_OD_I_MSK 0xfffffeff
+#define PAD24_OD_SFT 8
+#define PAD24_OD_HI 8
+#define PAD24_OD_SZ 1
+#define PAD24_SEL_O_MSK 0x00007000
+#define PAD24_SEL_O_I_MSK 0xffff8fff
+#define PAD24_SEL_O_SFT 12
+#define PAD24_SEL_O_HI 14
+#define PAD24_SEL_O_SZ 3
+#define GPIO_TEST_4_ID_MSK 0x10000000
+#define GPIO_TEST_4_ID_I_MSK 0xefffffff
+#define GPIO_TEST_4_ID_SFT 28
+#define GPIO_TEST_4_ID_HI 28
+#define GPIO_TEST_4_ID_SZ 1
+#define PAD25_OE_MSK 0x00000001
+#define PAD25_OE_I_MSK 0xfffffffe
+#define PAD25_OE_SFT 0
+#define PAD25_OE_HI 0
+#define PAD25_OE_SZ 1
+#define PAD25_PE_MSK 0x00000002
+#define PAD25_PE_I_MSK 0xfffffffd
+#define PAD25_PE_SFT 1
+#define PAD25_PE_HI 1
+#define PAD25_PE_SZ 1
+#define PAD25_DS_MSK 0x00000004
+#define PAD25_DS_I_MSK 0xfffffffb
+#define PAD25_DS_SFT 2
+#define PAD25_DS_HI 2
+#define PAD25_DS_SZ 1
+#define PAD25_IE_MSK 0x00000008
+#define PAD25_IE_I_MSK 0xfffffff7
+#define PAD25_IE_SFT 3
+#define PAD25_IE_HI 3
+#define PAD25_IE_SZ 1
+#define PAD25_SEL_I_MSK 0x00000070
+#define PAD25_SEL_I_I_MSK 0xffffff8f
+#define PAD25_SEL_I_SFT 4
+#define PAD25_SEL_I_HI 6
+#define PAD25_SEL_I_SZ 3
+#define PAD25_OD_MSK 0x00000100
+#define PAD25_OD_I_MSK 0xfffffeff
+#define PAD25_OD_SFT 8
+#define PAD25_OD_HI 8
+#define PAD25_OD_SZ 1
+#define PAD25_SEL_O_MSK 0x00007000
+#define PAD25_SEL_O_I_MSK 0xffff8fff
+#define PAD25_SEL_O_SFT 12
+#define PAD25_SEL_O_HI 14
+#define PAD25_SEL_O_SZ 3
+#define PAD25_SEL_OE_MSK 0x00100000
+#define PAD25_SEL_OE_I_MSK 0xffefffff
+#define PAD25_SEL_OE_SFT 20
+#define PAD25_SEL_OE_HI 20
+#define PAD25_SEL_OE_SZ 1
+#define STRAP1_MSK 0x08000000
+#define STRAP1_I_MSK 0xf7ffffff
+#define STRAP1_SFT 27
+#define STRAP1_HI 27
+#define STRAP1_SZ 1
+#define GPIO_1_ID_MSK 0x10000000
+#define GPIO_1_ID_I_MSK 0xefffffff
+#define GPIO_1_ID_SFT 28
+#define GPIO_1_ID_HI 28
+#define GPIO_1_ID_SZ 1
+#define PAD27_OE_MSK 0x00000001
+#define PAD27_OE_I_MSK 0xfffffffe
+#define PAD27_OE_SFT 0
+#define PAD27_OE_HI 0
+#define PAD27_OE_SZ 1
+#define PAD27_PE_MSK 0x00000002
+#define PAD27_PE_I_MSK 0xfffffffd
+#define PAD27_PE_SFT 1
+#define PAD27_PE_HI 1
+#define PAD27_PE_SZ 1
+#define PAD27_DS_MSK 0x00000004
+#define PAD27_DS_I_MSK 0xfffffffb
+#define PAD27_DS_SFT 2
+#define PAD27_DS_HI 2
+#define PAD27_DS_SZ 1
+#define PAD27_IE_MSK 0x00000008
+#define PAD27_IE_I_MSK 0xfffffff7
+#define PAD27_IE_SFT 3
+#define PAD27_IE_HI 3
+#define PAD27_IE_SZ 1
+#define PAD27_SEL_I_MSK 0x00000070
+#define PAD27_SEL_I_I_MSK 0xffffff8f
+#define PAD27_SEL_I_SFT 4
+#define PAD27_SEL_I_HI 6
+#define PAD27_SEL_I_SZ 3
+#define PAD27_OD_MSK 0x00000100
+#define PAD27_OD_I_MSK 0xfffffeff
+#define PAD27_OD_SFT 8
+#define PAD27_OD_HI 8
+#define PAD27_OD_SZ 1
+#define PAD27_SEL_O_MSK 0x00007000
+#define PAD27_SEL_O_I_MSK 0xffff8fff
+#define PAD27_SEL_O_SFT 12
+#define PAD27_SEL_O_HI 14
+#define PAD27_SEL_O_SZ 3
+#define GPIO_2_ID_MSK 0x10000000
+#define GPIO_2_ID_I_MSK 0xefffffff
+#define GPIO_2_ID_SFT 28
+#define GPIO_2_ID_HI 28
+#define GPIO_2_ID_SZ 1
+#define PAD28_OE_MSK 0x00000001
+#define PAD28_OE_I_MSK 0xfffffffe
+#define PAD28_OE_SFT 0
+#define PAD28_OE_HI 0
+#define PAD28_OE_SZ 1
+#define PAD28_PE_MSK 0x00000002
+#define PAD28_PE_I_MSK 0xfffffffd
+#define PAD28_PE_SFT 1
+#define PAD28_PE_HI 1
+#define PAD28_PE_SZ 1
+#define PAD28_DS_MSK 0x00000004
+#define PAD28_DS_I_MSK 0xfffffffb
+#define PAD28_DS_SFT 2
+#define PAD28_DS_HI 2
+#define PAD28_DS_SZ 1
+#define PAD28_IE_MSK 0x00000008
+#define PAD28_IE_I_MSK 0xfffffff7
+#define PAD28_IE_SFT 3
+#define PAD28_IE_HI 3
+#define PAD28_IE_SZ 1
+#define PAD28_SEL_I_MSK 0x00000070
+#define PAD28_SEL_I_I_MSK 0xffffff8f
+#define PAD28_SEL_I_SFT 4
+#define PAD28_SEL_I_HI 6
+#define PAD28_SEL_I_SZ 3
+#define PAD28_OD_MSK 0x00000100
+#define PAD28_OD_I_MSK 0xfffffeff
+#define PAD28_OD_SFT 8
+#define PAD28_OD_HI 8
+#define PAD28_OD_SZ 1
+#define PAD28_SEL_O_MSK 0x0000f000
+#define PAD28_SEL_O_I_MSK 0xffff0fff
+#define PAD28_SEL_O_SFT 12
+#define PAD28_SEL_O_HI 15
+#define PAD28_SEL_O_SZ 4
+#define PAD28_SEL_OE_MSK 0x00100000
+#define PAD28_SEL_OE_I_MSK 0xffefffff
+#define PAD28_SEL_OE_SFT 20
+#define PAD28_SEL_OE_HI 20
+#define PAD28_SEL_OE_SZ 1
+#define GPIO_3_ID_MSK 0x10000000
+#define GPIO_3_ID_I_MSK 0xefffffff
+#define GPIO_3_ID_SFT 28
+#define GPIO_3_ID_HI 28
+#define GPIO_3_ID_SZ 1
+#define PAD29_OE_MSK 0x00000001
+#define PAD29_OE_I_MSK 0xfffffffe
+#define PAD29_OE_SFT 0
+#define PAD29_OE_HI 0
+#define PAD29_OE_SZ 1
+#define PAD29_PE_MSK 0x00000002
+#define PAD29_PE_I_MSK 0xfffffffd
+#define PAD29_PE_SFT 1
+#define PAD29_PE_HI 1
+#define PAD29_PE_SZ 1
+#define PAD29_DS_MSK 0x00000004
+#define PAD29_DS_I_MSK 0xfffffffb
+#define PAD29_DS_SFT 2
+#define PAD29_DS_HI 2
+#define PAD29_DS_SZ 1
+#define PAD29_IE_MSK 0x00000008
+#define PAD29_IE_I_MSK 0xfffffff7
+#define PAD29_IE_SFT 3
+#define PAD29_IE_HI 3
+#define PAD29_IE_SZ 1
+#define PAD29_SEL_I_MSK 0x00000070
+#define PAD29_SEL_I_I_MSK 0xffffff8f
+#define PAD29_SEL_I_SFT 4
+#define PAD29_SEL_I_HI 6
+#define PAD29_SEL_I_SZ 3
+#define PAD29_OD_MSK 0x00000100
+#define PAD29_OD_I_MSK 0xfffffeff
+#define PAD29_OD_SFT 8
+#define PAD29_OD_HI 8
+#define PAD29_OD_SZ 1
+#define PAD29_SEL_O_MSK 0x00007000
+#define PAD29_SEL_O_I_MSK 0xffff8fff
+#define PAD29_SEL_O_SFT 12
+#define PAD29_SEL_O_HI 14
+#define PAD29_SEL_O_SZ 3
+#define GPIO_TEST_5_ID_MSK 0x10000000
+#define GPIO_TEST_5_ID_I_MSK 0xefffffff
+#define GPIO_TEST_5_ID_SFT 28
+#define GPIO_TEST_5_ID_HI 28
+#define GPIO_TEST_5_ID_SZ 1
+#define PAD30_OE_MSK 0x00000001
+#define PAD30_OE_I_MSK 0xfffffffe
+#define PAD30_OE_SFT 0
+#define PAD30_OE_HI 0
+#define PAD30_OE_SZ 1
+#define PAD30_PE_MSK 0x00000002
+#define PAD30_PE_I_MSK 0xfffffffd
+#define PAD30_PE_SFT 1
+#define PAD30_PE_HI 1
+#define PAD30_PE_SZ 1
+#define PAD30_DS_MSK 0x00000004
+#define PAD30_DS_I_MSK 0xfffffffb
+#define PAD30_DS_SFT 2
+#define PAD30_DS_HI 2
+#define PAD30_DS_SZ 1
+#define PAD30_IE_MSK 0x00000008
+#define PAD30_IE_I_MSK 0xfffffff7
+#define PAD30_IE_SFT 3
+#define PAD30_IE_HI 3
+#define PAD30_IE_SZ 1
+#define PAD30_SEL_I_MSK 0x00000030
+#define PAD30_SEL_I_I_MSK 0xffffffcf
+#define PAD30_SEL_I_SFT 4
+#define PAD30_SEL_I_HI 5
+#define PAD30_SEL_I_SZ 2
+#define PAD30_OD_MSK 0x00000100
+#define PAD30_OD_I_MSK 0xfffffeff
+#define PAD30_OD_SFT 8
+#define PAD30_OD_HI 8
+#define PAD30_OD_SZ 1
+#define PAD30_SEL_O_MSK 0x00003000
+#define PAD30_SEL_O_I_MSK 0xffffcfff
+#define PAD30_SEL_O_SFT 12
+#define PAD30_SEL_O_HI 13
+#define PAD30_SEL_O_SZ 2
+#define TEST_6_ID_MSK 0x10000000
+#define TEST_6_ID_I_MSK 0xefffffff
+#define TEST_6_ID_SFT 28
+#define TEST_6_ID_HI 28
+#define TEST_6_ID_SZ 1
+#define PAD31_OE_MSK 0x00000001
+#define PAD31_OE_I_MSK 0xfffffffe
+#define PAD31_OE_SFT 0
+#define PAD31_OE_HI 0
+#define PAD31_OE_SZ 1
+#define PAD31_PE_MSK 0x00000002
+#define PAD31_PE_I_MSK 0xfffffffd
+#define PAD31_PE_SFT 1
+#define PAD31_PE_HI 1
+#define PAD31_PE_SZ 1
+#define PAD31_DS_MSK 0x00000004
+#define PAD31_DS_I_MSK 0xfffffffb
+#define PAD31_DS_SFT 2
+#define PAD31_DS_HI 2
+#define PAD31_DS_SZ 1
+#define PAD31_IE_MSK 0x00000008
+#define PAD31_IE_I_MSK 0xfffffff7
+#define PAD31_IE_SFT 3
+#define PAD31_IE_HI 3
+#define PAD31_IE_SZ 1
+#define PAD31_SEL_I_MSK 0x00000030
+#define PAD31_SEL_I_I_MSK 0xffffffcf
+#define PAD31_SEL_I_SFT 4
+#define PAD31_SEL_I_HI 5
+#define PAD31_SEL_I_SZ 2
+#define PAD31_OD_MSK 0x00000100
+#define PAD31_OD_I_MSK 0xfffffeff
+#define PAD31_OD_SFT 8
+#define PAD31_OD_HI 8
+#define PAD31_OD_SZ 1
+#define PAD31_SEL_O_MSK 0x00003000
+#define PAD31_SEL_O_I_MSK 0xffffcfff
+#define PAD31_SEL_O_SFT 12
+#define PAD31_SEL_O_HI 13
+#define PAD31_SEL_O_SZ 2
+#define TEST_7_ID_MSK 0x10000000
+#define TEST_7_ID_I_MSK 0xefffffff
+#define TEST_7_ID_SFT 28
+#define TEST_7_ID_HI 28
+#define TEST_7_ID_SZ 1
+#define PAD32_OE_MSK 0x00000001
+#define PAD32_OE_I_MSK 0xfffffffe
+#define PAD32_OE_SFT 0
+#define PAD32_OE_HI 0
+#define PAD32_OE_SZ 1
+#define PAD32_PE_MSK 0x00000002
+#define PAD32_PE_I_MSK 0xfffffffd
+#define PAD32_PE_SFT 1
+#define PAD32_PE_HI 1
+#define PAD32_PE_SZ 1
+#define PAD32_DS_MSK 0x00000004
+#define PAD32_DS_I_MSK 0xfffffffb
+#define PAD32_DS_SFT 2
+#define PAD32_DS_HI 2
+#define PAD32_DS_SZ 1
+#define PAD32_IE_MSK 0x00000008
+#define PAD32_IE_I_MSK 0xfffffff7
+#define PAD32_IE_SFT 3
+#define PAD32_IE_HI 3
+#define PAD32_IE_SZ 1
+#define PAD32_SEL_I_MSK 0x00000030
+#define PAD32_SEL_I_I_MSK 0xffffffcf
+#define PAD32_SEL_I_SFT 4
+#define PAD32_SEL_I_HI 5
+#define PAD32_SEL_I_SZ 2
+#define PAD32_OD_MSK 0x00000100
+#define PAD32_OD_I_MSK 0xfffffeff
+#define PAD32_OD_SFT 8
+#define PAD32_OD_HI 8
+#define PAD32_OD_SZ 1
+#define PAD32_SEL_O_MSK 0x00003000
+#define PAD32_SEL_O_I_MSK 0xffffcfff
+#define PAD32_SEL_O_SFT 12
+#define PAD32_SEL_O_HI 13
+#define PAD32_SEL_O_SZ 2
+#define TEST_8_ID_MSK 0x10000000
+#define TEST_8_ID_I_MSK 0xefffffff
+#define TEST_8_ID_SFT 28
+#define TEST_8_ID_HI 28
+#define TEST_8_ID_SZ 1
+#define PAD33_OE_MSK 0x00000001
+#define PAD33_OE_I_MSK 0xfffffffe
+#define PAD33_OE_SFT 0
+#define PAD33_OE_HI 0
+#define PAD33_OE_SZ 1
+#define PAD33_PE_MSK 0x00000002
+#define PAD33_PE_I_MSK 0xfffffffd
+#define PAD33_PE_SFT 1
+#define PAD33_PE_HI 1
+#define PAD33_PE_SZ 1
+#define PAD33_DS_MSK 0x00000004
+#define PAD33_DS_I_MSK 0xfffffffb
+#define PAD33_DS_SFT 2
+#define PAD33_DS_HI 2
+#define PAD33_DS_SZ 1
+#define PAD33_IE_MSK 0x00000008
+#define PAD33_IE_I_MSK 0xfffffff7
+#define PAD33_IE_SFT 3
+#define PAD33_IE_HI 3
+#define PAD33_IE_SZ 1
+#define PAD33_SEL_I_MSK 0x00000030
+#define PAD33_SEL_I_I_MSK 0xffffffcf
+#define PAD33_SEL_I_SFT 4
+#define PAD33_SEL_I_HI 5
+#define PAD33_SEL_I_SZ 2
+#define PAD33_OD_MSK 0x00000100
+#define PAD33_OD_I_MSK 0xfffffeff
+#define PAD33_OD_SFT 8
+#define PAD33_OD_HI 8
+#define PAD33_OD_SZ 1
+#define PAD33_SEL_O_MSK 0x00003000
+#define PAD33_SEL_O_I_MSK 0xffffcfff
+#define PAD33_SEL_O_SFT 12
+#define PAD33_SEL_O_HI 13
+#define PAD33_SEL_O_SZ 2
+#define TEST_9_ID_MSK 0x10000000
+#define TEST_9_ID_I_MSK 0xefffffff
+#define TEST_9_ID_SFT 28
+#define TEST_9_ID_HI 28
+#define TEST_9_ID_SZ 1
+#define PAD34_OE_MSK 0x00000001
+#define PAD34_OE_I_MSK 0xfffffffe
+#define PAD34_OE_SFT 0
+#define PAD34_OE_HI 0
+#define PAD34_OE_SZ 1
+#define PAD34_PE_MSK 0x00000002
+#define PAD34_PE_I_MSK 0xfffffffd
+#define PAD34_PE_SFT 1
+#define PAD34_PE_HI 1
+#define PAD34_PE_SZ 1
+#define PAD34_DS_MSK 0x00000004
+#define PAD34_DS_I_MSK 0xfffffffb
+#define PAD34_DS_SFT 2
+#define PAD34_DS_HI 2
+#define PAD34_DS_SZ 1
+#define PAD34_IE_MSK 0x00000008
+#define PAD34_IE_I_MSK 0xfffffff7
+#define PAD34_IE_SFT 3
+#define PAD34_IE_HI 3
+#define PAD34_IE_SZ 1
+#define PAD34_SEL_I_MSK 0x00000030
+#define PAD34_SEL_I_I_MSK 0xffffffcf
+#define PAD34_SEL_I_SFT 4
+#define PAD34_SEL_I_HI 5
+#define PAD34_SEL_I_SZ 2
+#define PAD34_OD_MSK 0x00000100
+#define PAD34_OD_I_MSK 0xfffffeff
+#define PAD34_OD_SFT 8
+#define PAD34_OD_HI 8
+#define PAD34_OD_SZ 1
+#define PAD34_SEL_O_MSK 0x00003000
+#define PAD34_SEL_O_I_MSK 0xffffcfff
+#define PAD34_SEL_O_SFT 12
+#define PAD34_SEL_O_HI 13
+#define PAD34_SEL_O_SZ 2
+#define TEST_10_ID_MSK 0x10000000
+#define TEST_10_ID_I_MSK 0xefffffff
+#define TEST_10_ID_SFT 28
+#define TEST_10_ID_HI 28
+#define TEST_10_ID_SZ 1
+#define PAD42_OE_MSK 0x00000001
+#define PAD42_OE_I_MSK 0xfffffffe
+#define PAD42_OE_SFT 0
+#define PAD42_OE_HI 0
+#define PAD42_OE_SZ 1
+#define PAD42_PE_MSK 0x00000002
+#define PAD42_PE_I_MSK 0xfffffffd
+#define PAD42_PE_SFT 1
+#define PAD42_PE_HI 1
+#define PAD42_PE_SZ 1
+#define PAD42_DS_MSK 0x00000004
+#define PAD42_DS_I_MSK 0xfffffffb
+#define PAD42_DS_SFT 2
+#define PAD42_DS_HI 2
+#define PAD42_DS_SZ 1
+#define PAD42_IE_MSK 0x00000008
+#define PAD42_IE_I_MSK 0xfffffff7
+#define PAD42_IE_SFT 3
+#define PAD42_IE_HI 3
+#define PAD42_IE_SZ 1
+#define PAD42_SEL_I_MSK 0x00000030
+#define PAD42_SEL_I_I_MSK 0xffffffcf
+#define PAD42_SEL_I_SFT 4
+#define PAD42_SEL_I_HI 5
+#define PAD42_SEL_I_SZ 2
+#define PAD42_OD_MSK 0x00000100
+#define PAD42_OD_I_MSK 0xfffffeff
+#define PAD42_OD_SFT 8
+#define PAD42_OD_HI 8
+#define PAD42_OD_SZ 1
+#define PAD42_SEL_O_MSK 0x00001000
+#define PAD42_SEL_O_I_MSK 0xffffefff
+#define PAD42_SEL_O_SFT 12
+#define PAD42_SEL_O_HI 12
+#define PAD42_SEL_O_SZ 1
+#define TEST_11_ID_MSK 0x10000000
+#define TEST_11_ID_I_MSK 0xefffffff
+#define TEST_11_ID_SFT 28
+#define TEST_11_ID_HI 28
+#define TEST_11_ID_SZ 1
+#define PAD43_OE_MSK 0x00000001
+#define PAD43_OE_I_MSK 0xfffffffe
+#define PAD43_OE_SFT 0
+#define PAD43_OE_HI 0
+#define PAD43_OE_SZ 1
+#define PAD43_PE_MSK 0x00000002
+#define PAD43_PE_I_MSK 0xfffffffd
+#define PAD43_PE_SFT 1
+#define PAD43_PE_HI 1
+#define PAD43_PE_SZ 1
+#define PAD43_DS_MSK 0x00000004
+#define PAD43_DS_I_MSK 0xfffffffb
+#define PAD43_DS_SFT 2
+#define PAD43_DS_HI 2
+#define PAD43_DS_SZ 1
+#define PAD43_IE_MSK 0x00000008
+#define PAD43_IE_I_MSK 0xfffffff7
+#define PAD43_IE_SFT 3
+#define PAD43_IE_HI 3
+#define PAD43_IE_SZ 1
+#define PAD43_SEL_I_MSK 0x00000030
+#define PAD43_SEL_I_I_MSK 0xffffffcf
+#define PAD43_SEL_I_SFT 4
+#define PAD43_SEL_I_HI 5
+#define PAD43_SEL_I_SZ 2
+#define PAD43_OD_MSK 0x00000100
+#define PAD43_OD_I_MSK 0xfffffeff
+#define PAD43_OD_SFT 8
+#define PAD43_OD_HI 8
+#define PAD43_OD_SZ 1
+#define PAD43_SEL_O_MSK 0x00001000
+#define PAD43_SEL_O_I_MSK 0xffffefff
+#define PAD43_SEL_O_SFT 12
+#define PAD43_SEL_O_HI 12
+#define PAD43_SEL_O_SZ 1
+#define TEST_12_ID_MSK 0x10000000
+#define TEST_12_ID_I_MSK 0xefffffff
+#define TEST_12_ID_SFT 28
+#define TEST_12_ID_HI 28
+#define TEST_12_ID_SZ 1
+#define PAD44_OE_MSK 0x00000001
+#define PAD44_OE_I_MSK 0xfffffffe
+#define PAD44_OE_SFT 0
+#define PAD44_OE_HI 0
+#define PAD44_OE_SZ 1
+#define PAD44_PE_MSK 0x00000002
+#define PAD44_PE_I_MSK 0xfffffffd
+#define PAD44_PE_SFT 1
+#define PAD44_PE_HI 1
+#define PAD44_PE_SZ 1
+#define PAD44_DS_MSK 0x00000004
+#define PAD44_DS_I_MSK 0xfffffffb
+#define PAD44_DS_SFT 2
+#define PAD44_DS_HI 2
+#define PAD44_DS_SZ 1
+#define PAD44_IE_MSK 0x00000008
+#define PAD44_IE_I_MSK 0xfffffff7
+#define PAD44_IE_SFT 3
+#define PAD44_IE_HI 3
+#define PAD44_IE_SZ 1
+#define PAD44_SEL_I_MSK 0x00000030
+#define PAD44_SEL_I_I_MSK 0xffffffcf
+#define PAD44_SEL_I_SFT 4
+#define PAD44_SEL_I_HI 5
+#define PAD44_SEL_I_SZ 2
+#define PAD44_OD_MSK 0x00000100
+#define PAD44_OD_I_MSK 0xfffffeff
+#define PAD44_OD_SFT 8
+#define PAD44_OD_HI 8
+#define PAD44_OD_SZ 1
+#define PAD44_SEL_O_MSK 0x00003000
+#define PAD44_SEL_O_I_MSK 0xffffcfff
+#define PAD44_SEL_O_SFT 12
+#define PAD44_SEL_O_HI 13
+#define PAD44_SEL_O_SZ 2
+#define TEST_13_ID_MSK 0x10000000
+#define TEST_13_ID_I_MSK 0xefffffff
+#define TEST_13_ID_SFT 28
+#define TEST_13_ID_HI 28
+#define TEST_13_ID_SZ 1
+#define PAD45_OE_MSK 0x00000001
+#define PAD45_OE_I_MSK 0xfffffffe
+#define PAD45_OE_SFT 0
+#define PAD45_OE_HI 0
+#define PAD45_OE_SZ 1
+#define PAD45_PE_MSK 0x00000002
+#define PAD45_PE_I_MSK 0xfffffffd
+#define PAD45_PE_SFT 1
+#define PAD45_PE_HI 1
+#define PAD45_PE_SZ 1
+#define PAD45_DS_MSK 0x00000004
+#define PAD45_DS_I_MSK 0xfffffffb
+#define PAD45_DS_SFT 2
+#define PAD45_DS_HI 2
+#define PAD45_DS_SZ 1
+#define PAD45_IE_MSK 0x00000008
+#define PAD45_IE_I_MSK 0xfffffff7
+#define PAD45_IE_SFT 3
+#define PAD45_IE_HI 3
+#define PAD45_IE_SZ 1
+#define PAD45_SEL_I_MSK 0x00000030
+#define PAD45_SEL_I_I_MSK 0xffffffcf
+#define PAD45_SEL_I_SFT 4
+#define PAD45_SEL_I_HI 5
+#define PAD45_SEL_I_SZ 2
+#define PAD45_OD_MSK 0x00000100
+#define PAD45_OD_I_MSK 0xfffffeff
+#define PAD45_OD_SFT 8
+#define PAD45_OD_HI 8
+#define PAD45_OD_SZ 1
+#define PAD45_SEL_O_MSK 0x00003000
+#define PAD45_SEL_O_I_MSK 0xffffcfff
+#define PAD45_SEL_O_SFT 12
+#define PAD45_SEL_O_HI 13
+#define PAD45_SEL_O_SZ 2
+#define TEST_14_ID_MSK 0x10000000
+#define TEST_14_ID_I_MSK 0xefffffff
+#define TEST_14_ID_SFT 28
+#define TEST_14_ID_HI 28
+#define TEST_14_ID_SZ 1
+#define PAD46_OE_MSK 0x00000001
+#define PAD46_OE_I_MSK 0xfffffffe
+#define PAD46_OE_SFT 0
+#define PAD46_OE_HI 0
+#define PAD46_OE_SZ 1
+#define PAD46_PE_MSK 0x00000002
+#define PAD46_PE_I_MSK 0xfffffffd
+#define PAD46_PE_SFT 1
+#define PAD46_PE_HI 1
+#define PAD46_PE_SZ 1
+#define PAD46_DS_MSK 0x00000004
+#define PAD46_DS_I_MSK 0xfffffffb
+#define PAD46_DS_SFT 2
+#define PAD46_DS_HI 2
+#define PAD46_DS_SZ 1
+#define PAD46_IE_MSK 0x00000008
+#define PAD46_IE_I_MSK 0xfffffff7
+#define PAD46_IE_SFT 3
+#define PAD46_IE_HI 3
+#define PAD46_IE_SZ 1
+#define PAD46_SEL_I_MSK 0x00000030
+#define PAD46_SEL_I_I_MSK 0xffffffcf
+#define PAD46_SEL_I_SFT 4
+#define PAD46_SEL_I_HI 5
+#define PAD46_SEL_I_SZ 2
+#define PAD46_OD_MSK 0x00000100
+#define PAD46_OD_I_MSK 0xfffffeff
+#define PAD46_OD_SFT 8
+#define PAD46_OD_HI 8
+#define PAD46_OD_SZ 1
+#define PAD46_SEL_O_MSK 0x00003000
+#define PAD46_SEL_O_I_MSK 0xffffcfff
+#define PAD46_SEL_O_SFT 12
+#define PAD46_SEL_O_HI 13
+#define PAD46_SEL_O_SZ 2
+#define TEST_15_ID_MSK 0x10000000
+#define TEST_15_ID_I_MSK 0xefffffff
+#define TEST_15_ID_SFT 28
+#define TEST_15_ID_HI 28
+#define TEST_15_ID_SZ 1
+#define PAD47_OE_MSK 0x00000001
+#define PAD47_OE_I_MSK 0xfffffffe
+#define PAD47_OE_SFT 0
+#define PAD47_OE_HI 0
+#define PAD47_OE_SZ 1
+#define PAD47_PE_MSK 0x00000002
+#define PAD47_PE_I_MSK 0xfffffffd
+#define PAD47_PE_SFT 1
+#define PAD47_PE_HI 1
+#define PAD47_PE_SZ 1
+#define PAD47_DS_MSK 0x00000004
+#define PAD47_DS_I_MSK 0xfffffffb
+#define PAD47_DS_SFT 2
+#define PAD47_DS_HI 2
+#define PAD47_DS_SZ 1
+#define PAD47_SEL_I_MSK 0x00000030
+#define PAD47_SEL_I_I_MSK 0xffffffcf
+#define PAD47_SEL_I_SFT 4
+#define PAD47_SEL_I_HI 5
+#define PAD47_SEL_I_SZ 2
+#define PAD47_OD_MSK 0x00000100
+#define PAD47_OD_I_MSK 0xfffffeff
+#define PAD47_OD_SFT 8
+#define PAD47_OD_HI 8
+#define PAD47_OD_SZ 1
+#define PAD47_SEL_O_MSK 0x00003000
+#define PAD47_SEL_O_I_MSK 0xffffcfff
+#define PAD47_SEL_O_SFT 12
+#define PAD47_SEL_O_HI 13
+#define PAD47_SEL_O_SZ 2
+#define PAD47_SEL_OE_MSK 0x00100000
+#define PAD47_SEL_OE_I_MSK 0xffefffff
+#define PAD47_SEL_OE_SFT 20
+#define PAD47_SEL_OE_HI 20
+#define PAD47_SEL_OE_SZ 1
+#define GPIO_9_ID_MSK 0x10000000
+#define GPIO_9_ID_I_MSK 0xefffffff
+#define GPIO_9_ID_SFT 28
+#define GPIO_9_ID_HI 28
+#define GPIO_9_ID_SZ 1
+#define PAD48_OE_MSK 0x00000001
+#define PAD48_OE_I_MSK 0xfffffffe
+#define PAD48_OE_SFT 0
+#define PAD48_OE_HI 0
+#define PAD48_OE_SZ 1
+#define PAD48_PE_MSK 0x00000002
+#define PAD48_PE_I_MSK 0xfffffffd
+#define PAD48_PE_SFT 1
+#define PAD48_PE_HI 1
+#define PAD48_PE_SZ 1
+#define PAD48_DS_MSK 0x00000004
+#define PAD48_DS_I_MSK 0xfffffffb
+#define PAD48_DS_SFT 2
+#define PAD48_DS_HI 2
+#define PAD48_DS_SZ 1
+#define PAD48_IE_MSK 0x00000008
+#define PAD48_IE_I_MSK 0xfffffff7
+#define PAD48_IE_SFT 3
+#define PAD48_IE_HI 3
+#define PAD48_IE_SZ 1
+#define PAD48_SEL_I_MSK 0x00000070
+#define PAD48_SEL_I_I_MSK 0xffffff8f
+#define PAD48_SEL_I_SFT 4
+#define PAD48_SEL_I_HI 6
+#define PAD48_SEL_I_SZ 3
+#define PAD48_OD_MSK 0x00000100
+#define PAD48_OD_I_MSK 0xfffffeff
+#define PAD48_OD_SFT 8
+#define PAD48_OD_HI 8
+#define PAD48_OD_SZ 1
+#define PAD48_PE_SEL_MSK 0x00000800
+#define PAD48_PE_SEL_I_MSK 0xfffff7ff
+#define PAD48_PE_SEL_SFT 11
+#define PAD48_PE_SEL_HI 11
+#define PAD48_PE_SEL_SZ 1
+#define PAD48_SEL_O_MSK 0x00003000
+#define PAD48_SEL_O_I_MSK 0xffffcfff
+#define PAD48_SEL_O_SFT 12
+#define PAD48_SEL_O_HI 13
+#define PAD48_SEL_O_SZ 2
+#define PAD48_SEL_OE_MSK 0x00100000
+#define PAD48_SEL_OE_I_MSK 0xffefffff
+#define PAD48_SEL_OE_SFT 20
+#define PAD48_SEL_OE_HI 20
+#define PAD48_SEL_OE_SZ 1
+#define GPIO_10_ID_MSK 0x10000000
+#define GPIO_10_ID_I_MSK 0xefffffff
+#define GPIO_10_ID_SFT 28
+#define GPIO_10_ID_HI 28
+#define GPIO_10_ID_SZ 1
+#define PAD49_OE_MSK 0x00000001
+#define PAD49_OE_I_MSK 0xfffffffe
+#define PAD49_OE_SFT 0
+#define PAD49_OE_HI 0
+#define PAD49_OE_SZ 1
+#define PAD49_PE_MSK 0x00000002
+#define PAD49_PE_I_MSK 0xfffffffd
+#define PAD49_PE_SFT 1
+#define PAD49_PE_HI 1
+#define PAD49_PE_SZ 1
+#define PAD49_DS_MSK 0x00000004
+#define PAD49_DS_I_MSK 0xfffffffb
+#define PAD49_DS_SFT 2
+#define PAD49_DS_HI 2
+#define PAD49_DS_SZ 1
+#define PAD49_IE_MSK 0x00000008
+#define PAD49_IE_I_MSK 0xfffffff7
+#define PAD49_IE_SFT 3
+#define PAD49_IE_HI 3
+#define PAD49_IE_SZ 1
+#define PAD49_SEL_I_MSK 0x00000070
+#define PAD49_SEL_I_I_MSK 0xffffff8f
+#define PAD49_SEL_I_SFT 4
+#define PAD49_SEL_I_HI 6
+#define PAD49_SEL_I_SZ 3
+#define PAD49_OD_MSK 0x00000100
+#define PAD49_OD_I_MSK 0xfffffeff
+#define PAD49_OD_SFT 8
+#define PAD49_OD_HI 8
+#define PAD49_OD_SZ 1
+#define PAD49_SEL_O_MSK 0x00003000
+#define PAD49_SEL_O_I_MSK 0xffffcfff
+#define PAD49_SEL_O_SFT 12
+#define PAD49_SEL_O_HI 13
+#define PAD49_SEL_O_SZ 2
+#define PAD49_SEL_OE_MSK 0x00100000
+#define PAD49_SEL_OE_I_MSK 0xffefffff
+#define PAD49_SEL_OE_SFT 20
+#define PAD49_SEL_OE_HI 20
+#define PAD49_SEL_OE_SZ 1
+#define GPIO_11_ID_MSK 0x10000000
+#define GPIO_11_ID_I_MSK 0xefffffff
+#define GPIO_11_ID_SFT 28
+#define GPIO_11_ID_HI 28
+#define GPIO_11_ID_SZ 1
+#define PAD50_OE_MSK 0x00000001
+#define PAD50_OE_I_MSK 0xfffffffe
+#define PAD50_OE_SFT 0
+#define PAD50_OE_HI 0
+#define PAD50_OE_SZ 1
+#define PAD50_PE_MSK 0x00000002
+#define PAD50_PE_I_MSK 0xfffffffd
+#define PAD50_PE_SFT 1
+#define PAD50_PE_HI 1
+#define PAD50_PE_SZ 1
+#define PAD50_DS_MSK 0x00000004
+#define PAD50_DS_I_MSK 0xfffffffb
+#define PAD50_DS_SFT 2
+#define PAD50_DS_HI 2
+#define PAD50_DS_SZ 1
+#define PAD50_IE_MSK 0x00000008
+#define PAD50_IE_I_MSK 0xfffffff7
+#define PAD50_IE_SFT 3
+#define PAD50_IE_HI 3
+#define PAD50_IE_SZ 1
+#define PAD50_SEL_I_MSK 0x00000070
+#define PAD50_SEL_I_I_MSK 0xffffff8f
+#define PAD50_SEL_I_SFT 4
+#define PAD50_SEL_I_HI 6
+#define PAD50_SEL_I_SZ 3
+#define PAD50_OD_MSK 0x00000100
+#define PAD50_OD_I_MSK 0xfffffeff
+#define PAD50_OD_SFT 8
+#define PAD50_OD_HI 8
+#define PAD50_OD_SZ 1
+#define PAD50_SEL_O_MSK 0x00003000
+#define PAD50_SEL_O_I_MSK 0xffffcfff
+#define PAD50_SEL_O_SFT 12
+#define PAD50_SEL_O_HI 13
+#define PAD50_SEL_O_SZ 2
+#define PAD50_SEL_OE_MSK 0x00100000
+#define PAD50_SEL_OE_I_MSK 0xffefffff
+#define PAD50_SEL_OE_SFT 20
+#define PAD50_SEL_OE_HI 20
+#define PAD50_SEL_OE_SZ 1
+#define GPIO_12_ID_MSK 0x10000000
+#define GPIO_12_ID_I_MSK 0xefffffff
+#define GPIO_12_ID_SFT 28
+#define GPIO_12_ID_HI 28
+#define GPIO_12_ID_SZ 1
+#define PAD51_OE_MSK 0x00000001
+#define PAD51_OE_I_MSK 0xfffffffe
+#define PAD51_OE_SFT 0
+#define PAD51_OE_HI 0
+#define PAD51_OE_SZ 1
+#define PAD51_PE_MSK 0x00000002
+#define PAD51_PE_I_MSK 0xfffffffd
+#define PAD51_PE_SFT 1
+#define PAD51_PE_HI 1
+#define PAD51_PE_SZ 1
+#define PAD51_DS_MSK 0x00000004
+#define PAD51_DS_I_MSK 0xfffffffb
+#define PAD51_DS_SFT 2
+#define PAD51_DS_HI 2
+#define PAD51_DS_SZ 1
+#define PAD51_IE_MSK 0x00000008
+#define PAD51_IE_I_MSK 0xfffffff7
+#define PAD51_IE_SFT 3
+#define PAD51_IE_HI 3
+#define PAD51_IE_SZ 1
+#define PAD51_SEL_I_MSK 0x00000030
+#define PAD51_SEL_I_I_MSK 0xffffffcf
+#define PAD51_SEL_I_SFT 4
+#define PAD51_SEL_I_HI 5
+#define PAD51_SEL_I_SZ 2
+#define PAD51_OD_MSK 0x00000100
+#define PAD51_OD_I_MSK 0xfffffeff
+#define PAD51_OD_SFT 8
+#define PAD51_OD_HI 8
+#define PAD51_OD_SZ 1
+#define PAD51_SEL_O_MSK 0x00001000
+#define PAD51_SEL_O_I_MSK 0xffffefff
+#define PAD51_SEL_O_SFT 12
+#define PAD51_SEL_O_HI 12
+#define PAD51_SEL_O_SZ 1
+#define PAD51_SEL_OE_MSK 0x00100000
+#define PAD51_SEL_OE_I_MSK 0xffefffff
+#define PAD51_SEL_OE_SFT 20
+#define PAD51_SEL_OE_HI 20
+#define PAD51_SEL_OE_SZ 1
+#define GPIO_13_ID_MSK 0x10000000
+#define GPIO_13_ID_I_MSK 0xefffffff
+#define GPIO_13_ID_SFT 28
+#define GPIO_13_ID_HI 28
+#define GPIO_13_ID_SZ 1
+#define PAD52_OE_MSK 0x00000001
+#define PAD52_OE_I_MSK 0xfffffffe
+#define PAD52_OE_SFT 0
+#define PAD52_OE_HI 0
+#define PAD52_OE_SZ 1
+#define PAD52_PE_MSK 0x00000002
+#define PAD52_PE_I_MSK 0xfffffffd
+#define PAD52_PE_SFT 1
+#define PAD52_PE_HI 1
+#define PAD52_PE_SZ 1
+#define PAD52_DS_MSK 0x00000004
+#define PAD52_DS_I_MSK 0xfffffffb
+#define PAD52_DS_SFT 2
+#define PAD52_DS_HI 2
+#define PAD52_DS_SZ 1
+#define PAD52_SEL_I_MSK 0x00000030
+#define PAD52_SEL_I_I_MSK 0xffffffcf
+#define PAD52_SEL_I_SFT 4
+#define PAD52_SEL_I_HI 5
+#define PAD52_SEL_I_SZ 2
+#define PAD52_OD_MSK 0x00000100
+#define PAD52_OD_I_MSK 0xfffffeff
+#define PAD52_OD_SFT 8
+#define PAD52_OD_HI 8
+#define PAD52_OD_SZ 1
+#define PAD52_SEL_O_MSK 0x00001000
+#define PAD52_SEL_O_I_MSK 0xffffefff
+#define PAD52_SEL_O_SFT 12
+#define PAD52_SEL_O_HI 12
+#define PAD52_SEL_O_SZ 1
+#define PAD52_SEL_OE_MSK 0x00100000
+#define PAD52_SEL_OE_I_MSK 0xffefffff
+#define PAD52_SEL_OE_SFT 20
+#define PAD52_SEL_OE_HI 20
+#define PAD52_SEL_OE_SZ 1
+#define GPIO_14_ID_MSK 0x10000000
+#define GPIO_14_ID_I_MSK 0xefffffff
+#define GPIO_14_ID_SFT 28
+#define GPIO_14_ID_HI 28
+#define GPIO_14_ID_SZ 1
+#define PAD53_OE_MSK 0x00000001
+#define PAD53_OE_I_MSK 0xfffffffe
+#define PAD53_OE_SFT 0
+#define PAD53_OE_HI 0
+#define PAD53_OE_SZ 1
+#define PAD53_PE_MSK 0x00000002
+#define PAD53_PE_I_MSK 0xfffffffd
+#define PAD53_PE_SFT 1
+#define PAD53_PE_HI 1
+#define PAD53_PE_SZ 1
+#define PAD53_DS_MSK 0x00000004
+#define PAD53_DS_I_MSK 0xfffffffb
+#define PAD53_DS_SFT 2
+#define PAD53_DS_HI 2
+#define PAD53_DS_SZ 1
+#define PAD53_IE_MSK 0x00000008
+#define PAD53_IE_I_MSK 0xfffffff7
+#define PAD53_IE_SFT 3
+#define PAD53_IE_HI 3
+#define PAD53_IE_SZ 1
+#define PAD53_SEL_I_MSK 0x00000030
+#define PAD53_SEL_I_I_MSK 0xffffffcf
+#define PAD53_SEL_I_SFT 4
+#define PAD53_SEL_I_HI 5
+#define PAD53_SEL_I_SZ 2
+#define PAD53_OD_MSK 0x00000100
+#define PAD53_OD_I_MSK 0xfffffeff
+#define PAD53_OD_SFT 8
+#define PAD53_OD_HI 8
+#define PAD53_OD_SZ 1
+#define PAD53_SEL_O_MSK 0x00001000
+#define PAD53_SEL_O_I_MSK 0xffffefff
+#define PAD53_SEL_O_SFT 12
+#define PAD53_SEL_O_HI 12
+#define PAD53_SEL_O_SZ 1
+#define JTAG_TMS_ID_MSK 0x10000000
+#define JTAG_TMS_ID_I_MSK 0xefffffff
+#define JTAG_TMS_ID_SFT 28
+#define JTAG_TMS_ID_HI 28
+#define JTAG_TMS_ID_SZ 1
+#define PAD54_OE_MSK 0x00000001
+#define PAD54_OE_I_MSK 0xfffffffe
+#define PAD54_OE_SFT 0
+#define PAD54_OE_HI 0
+#define PAD54_OE_SZ 1
+#define PAD54_PE_MSK 0x00000002
+#define PAD54_PE_I_MSK 0xfffffffd
+#define PAD54_PE_SFT 1
+#define PAD54_PE_HI 1
+#define PAD54_PE_SZ 1
+#define PAD54_DS_MSK 0x00000004
+#define PAD54_DS_I_MSK 0xfffffffb
+#define PAD54_DS_SFT 2
+#define PAD54_DS_HI 2
+#define PAD54_DS_SZ 1
+#define PAD54_OD_MSK 0x00000100
+#define PAD54_OD_I_MSK 0xfffffeff
+#define PAD54_OD_SFT 8
+#define PAD54_OD_HI 8
+#define PAD54_OD_SZ 1
+#define PAD54_SEL_O_MSK 0x00003000
+#define PAD54_SEL_O_I_MSK 0xffffcfff
+#define PAD54_SEL_O_SFT 12
+#define PAD54_SEL_O_HI 13
+#define PAD54_SEL_O_SZ 2
+#define JTAG_TCK_ID_MSK 0x10000000
+#define JTAG_TCK_ID_I_MSK 0xefffffff
+#define JTAG_TCK_ID_SFT 28
+#define JTAG_TCK_ID_HI 28
+#define JTAG_TCK_ID_SZ 1
+#define PAD56_PE_MSK 0x00000002
+#define PAD56_PE_I_MSK 0xfffffffd
+#define PAD56_PE_SFT 1
+#define PAD56_PE_HI 1
+#define PAD56_PE_SZ 1
+#define PAD56_DS_MSK 0x00000004
+#define PAD56_DS_I_MSK 0xfffffffb
+#define PAD56_DS_SFT 2
+#define PAD56_DS_HI 2
+#define PAD56_DS_SZ 1
+#define PAD56_SEL_I_MSK 0x00000010
+#define PAD56_SEL_I_I_MSK 0xffffffef
+#define PAD56_SEL_I_SFT 4
+#define PAD56_SEL_I_HI 4
+#define PAD56_SEL_I_SZ 1
+#define PAD56_OD_MSK 0x00000100
+#define PAD56_OD_I_MSK 0xfffffeff
+#define PAD56_OD_SFT 8
+#define PAD56_OD_HI 8
+#define PAD56_OD_SZ 1
+#define JTAG_TDI_ID_MSK 0x10000000
+#define JTAG_TDI_ID_I_MSK 0xefffffff
+#define JTAG_TDI_ID_SFT 28
+#define JTAG_TDI_ID_HI 28
+#define JTAG_TDI_ID_SZ 1
+#define PAD57_OE_MSK 0x00000001
+#define PAD57_OE_I_MSK 0xfffffffe
+#define PAD57_OE_SFT 0
+#define PAD57_OE_HI 0
+#define PAD57_OE_SZ 1
+#define PAD57_PE_MSK 0x00000002
+#define PAD57_PE_I_MSK 0xfffffffd
+#define PAD57_PE_SFT 1
+#define PAD57_PE_HI 1
+#define PAD57_PE_SZ 1
+#define PAD57_DS_MSK 0x00000004
+#define PAD57_DS_I_MSK 0xfffffffb
+#define PAD57_DS_SFT 2
+#define PAD57_DS_HI 2
+#define PAD57_DS_SZ 1
+#define PAD57_IE_MSK 0x00000008
+#define PAD57_IE_I_MSK 0xfffffff7
+#define PAD57_IE_SFT 3
+#define PAD57_IE_HI 3
+#define PAD57_IE_SZ 1
+#define PAD57_SEL_I_MSK 0x00000030
+#define PAD57_SEL_I_I_MSK 0xffffffcf
+#define PAD57_SEL_I_SFT 4
+#define PAD57_SEL_I_HI 5
+#define PAD57_SEL_I_SZ 2
+#define PAD57_OD_MSK 0x00000100
+#define PAD57_OD_I_MSK 0xfffffeff
+#define PAD57_OD_SFT 8
+#define PAD57_OD_HI 8
+#define PAD57_OD_SZ 1
+#define PAD57_SEL_O_MSK 0x00003000
+#define PAD57_SEL_O_I_MSK 0xffffcfff
+#define PAD57_SEL_O_SFT 12
+#define PAD57_SEL_O_HI 13
+#define PAD57_SEL_O_SZ 2
+#define PAD57_SEL_OE_MSK 0x00100000
+#define PAD57_SEL_OE_I_MSK 0xffefffff
+#define PAD57_SEL_OE_SFT 20
+#define PAD57_SEL_OE_HI 20
+#define PAD57_SEL_OE_SZ 1
+#define JTAG_TDO_ID_MSK 0x10000000
+#define JTAG_TDO_ID_I_MSK 0xefffffff
+#define JTAG_TDO_ID_SFT 28
+#define JTAG_TDO_ID_HI 28
+#define JTAG_TDO_ID_SZ 1
+#define PAD58_OE_MSK 0x00000001
+#define PAD58_OE_I_MSK 0xfffffffe
+#define PAD58_OE_SFT 0
+#define PAD58_OE_HI 0
+#define PAD58_OE_SZ 1
+#define PAD58_PE_MSK 0x00000002
+#define PAD58_PE_I_MSK 0xfffffffd
+#define PAD58_PE_SFT 1
+#define PAD58_PE_HI 1
+#define PAD58_PE_SZ 1
+#define PAD58_DS_MSK 0x00000004
+#define PAD58_DS_I_MSK 0xfffffffb
+#define PAD58_DS_SFT 2
+#define PAD58_DS_HI 2
+#define PAD58_DS_SZ 1
+#define PAD58_IE_MSK 0x00000008
+#define PAD58_IE_I_MSK 0xfffffff7
+#define PAD58_IE_SFT 3
+#define PAD58_IE_HI 3
+#define PAD58_IE_SZ 1
+#define PAD58_SEL_I_MSK 0x00000030
+#define PAD58_SEL_I_I_MSK 0xffffffcf
+#define PAD58_SEL_I_SFT 4
+#define PAD58_SEL_I_HI 5
+#define PAD58_SEL_I_SZ 2
+#define PAD58_OD_MSK 0x00000100
+#define PAD58_OD_I_MSK 0xfffffeff
+#define PAD58_OD_SFT 8
+#define PAD58_OD_HI 8
+#define PAD58_OD_SZ 1
+#define PAD58_SEL_O_MSK 0x00001000
+#define PAD58_SEL_O_I_MSK 0xffffefff
+#define PAD58_SEL_O_SFT 12
+#define PAD58_SEL_O_HI 12
+#define PAD58_SEL_O_SZ 1
+#define TEST_16_ID_MSK 0x10000000
+#define TEST_16_ID_I_MSK 0xefffffff
+#define TEST_16_ID_SFT 28
+#define TEST_16_ID_HI 28
+#define TEST_16_ID_SZ 1
+#define PAD59_OE_MSK 0x00000001
+#define PAD59_OE_I_MSK 0xfffffffe
+#define PAD59_OE_SFT 0
+#define PAD59_OE_HI 0
+#define PAD59_OE_SZ 1
+#define PAD59_PE_MSK 0x00000002
+#define PAD59_PE_I_MSK 0xfffffffd
+#define PAD59_PE_SFT 1
+#define PAD59_PE_HI 1
+#define PAD59_PE_SZ 1
+#define PAD59_DS_MSK 0x00000004
+#define PAD59_DS_I_MSK 0xfffffffb
+#define PAD59_DS_SFT 2
+#define PAD59_DS_HI 2
+#define PAD59_DS_SZ 1
+#define PAD59_IE_MSK 0x00000008
+#define PAD59_IE_I_MSK 0xfffffff7
+#define PAD59_IE_SFT 3
+#define PAD59_IE_HI 3
+#define PAD59_IE_SZ 1
+#define PAD59_SEL_I_MSK 0x00000030
+#define PAD59_SEL_I_I_MSK 0xffffffcf
+#define PAD59_SEL_I_SFT 4
+#define PAD59_SEL_I_HI 5
+#define PAD59_SEL_I_SZ 2
+#define PAD59_OD_MSK 0x00000100
+#define PAD59_OD_I_MSK 0xfffffeff
+#define PAD59_OD_SFT 8
+#define PAD59_OD_HI 8
+#define PAD59_OD_SZ 1
+#define PAD59_SEL_O_MSK 0x00001000
+#define PAD59_SEL_O_I_MSK 0xffffefff
+#define PAD59_SEL_O_SFT 12
+#define PAD59_SEL_O_HI 12
+#define PAD59_SEL_O_SZ 1
+#define TEST_17_ID_MSK 0x10000000
+#define TEST_17_ID_I_MSK 0xefffffff
+#define TEST_17_ID_SFT 28
+#define TEST_17_ID_HI 28
+#define TEST_17_ID_SZ 1
+#define PAD60_OE_MSK 0x00000001
+#define PAD60_OE_I_MSK 0xfffffffe
+#define PAD60_OE_SFT 0
+#define PAD60_OE_HI 0
+#define PAD60_OE_SZ 1
+#define PAD60_PE_MSK 0x00000002
+#define PAD60_PE_I_MSK 0xfffffffd
+#define PAD60_PE_SFT 1
+#define PAD60_PE_HI 1
+#define PAD60_PE_SZ 1
+#define PAD60_DS_MSK 0x00000004
+#define PAD60_DS_I_MSK 0xfffffffb
+#define PAD60_DS_SFT 2
+#define PAD60_DS_HI 2
+#define PAD60_DS_SZ 1
+#define PAD60_IE_MSK 0x00000008
+#define PAD60_IE_I_MSK 0xfffffff7
+#define PAD60_IE_SFT 3
+#define PAD60_IE_HI 3
+#define PAD60_IE_SZ 1
+#define PAD60_SEL_I_MSK 0x00000030
+#define PAD60_SEL_I_I_MSK 0xffffffcf
+#define PAD60_SEL_I_SFT 4
+#define PAD60_SEL_I_HI 5
+#define PAD60_SEL_I_SZ 2
+#define PAD60_OD_MSK 0x00000100
+#define PAD60_OD_I_MSK 0xfffffeff
+#define PAD60_OD_SFT 8
+#define PAD60_OD_HI 8
+#define PAD60_OD_SZ 1
+#define PAD60_SEL_O_MSK 0x00001000
+#define PAD60_SEL_O_I_MSK 0xffffefff
+#define PAD60_SEL_O_SFT 12
+#define PAD60_SEL_O_HI 12
+#define PAD60_SEL_O_SZ 1
+#define TEST_18_ID_MSK 0x10000000
+#define TEST_18_ID_I_MSK 0xefffffff
+#define TEST_18_ID_SFT 28
+#define TEST_18_ID_HI 28
+#define TEST_18_ID_SZ 1
+#define PAD61_OE_MSK 0x00000001
+#define PAD61_OE_I_MSK 0xfffffffe
+#define PAD61_OE_SFT 0
+#define PAD61_OE_HI 0
+#define PAD61_OE_SZ 1
+#define PAD61_PE_MSK 0x00000002
+#define PAD61_PE_I_MSK 0xfffffffd
+#define PAD61_PE_SFT 1
+#define PAD61_PE_HI 1
+#define PAD61_PE_SZ 1
+#define PAD61_DS_MSK 0x00000004
+#define PAD61_DS_I_MSK 0xfffffffb
+#define PAD61_DS_SFT 2
+#define PAD61_DS_HI 2
+#define PAD61_DS_SZ 1
+#define PAD61_IE_MSK 0x00000008
+#define PAD61_IE_I_MSK 0xfffffff7
+#define PAD61_IE_SFT 3
+#define PAD61_IE_HI 3
+#define PAD61_IE_SZ 1
+#define PAD61_SEL_I_MSK 0x00000010
+#define PAD61_SEL_I_I_MSK 0xffffffef
+#define PAD61_SEL_I_SFT 4
+#define PAD61_SEL_I_HI 4
+#define PAD61_SEL_I_SZ 1
+#define PAD61_OD_MSK 0x00000100
+#define PAD61_OD_I_MSK 0xfffffeff
+#define PAD61_OD_SFT 8
+#define PAD61_OD_HI 8
+#define PAD61_OD_SZ 1
+#define PAD61_SEL_O_MSK 0x00003000
+#define PAD61_SEL_O_I_MSK 0xffffcfff
+#define PAD61_SEL_O_SFT 12
+#define PAD61_SEL_O_HI 13
+#define PAD61_SEL_O_SZ 2
+#define TEST_19_ID_MSK 0x10000000
+#define TEST_19_ID_I_MSK 0xefffffff
+#define TEST_19_ID_SFT 28
+#define TEST_19_ID_HI 28
+#define TEST_19_ID_SZ 1
+#define PAD62_OE_MSK 0x00000001
+#define PAD62_OE_I_MSK 0xfffffffe
+#define PAD62_OE_SFT 0
+#define PAD62_OE_HI 0
+#define PAD62_OE_SZ 1
+#define PAD62_PE_MSK 0x00000002
+#define PAD62_PE_I_MSK 0xfffffffd
+#define PAD62_PE_SFT 1
+#define PAD62_PE_HI 1
+#define PAD62_PE_SZ 1
+#define PAD62_DS_MSK 0x00000004
+#define PAD62_DS_I_MSK 0xfffffffb
+#define PAD62_DS_SFT 2
+#define PAD62_DS_HI 2
+#define PAD62_DS_SZ 1
+#define PAD62_IE_MSK 0x00000008
+#define PAD62_IE_I_MSK 0xfffffff7
+#define PAD62_IE_SFT 3
+#define PAD62_IE_HI 3
+#define PAD62_IE_SZ 1
+#define PAD62_SEL_I_MSK 0x00000010
+#define PAD62_SEL_I_I_MSK 0xffffffef
+#define PAD62_SEL_I_SFT 4
+#define PAD62_SEL_I_HI 4
+#define PAD62_SEL_I_SZ 1
+#define PAD62_OD_MSK 0x00000100
+#define PAD62_OD_I_MSK 0xfffffeff
+#define PAD62_OD_SFT 8
+#define PAD62_OD_HI 8
+#define PAD62_OD_SZ 1
+#define PAD62_SEL_O_MSK 0x00001000
+#define PAD62_SEL_O_I_MSK 0xffffefff
+#define PAD62_SEL_O_SFT 12
+#define PAD62_SEL_O_HI 12
+#define PAD62_SEL_O_SZ 1
+#define TEST_20_ID_MSK 0x10000000
+#define TEST_20_ID_I_MSK 0xefffffff
+#define TEST_20_ID_SFT 28
+#define TEST_20_ID_HI 28
+#define TEST_20_ID_SZ 1
+#define PAD64_OE_MSK 0x00000001
+#define PAD64_OE_I_MSK 0xfffffffe
+#define PAD64_OE_SFT 0
+#define PAD64_OE_HI 0
+#define PAD64_OE_SZ 1
+#define PAD64_PE_MSK 0x00000002
+#define PAD64_PE_I_MSK 0xfffffffd
+#define PAD64_PE_SFT 1
+#define PAD64_PE_HI 1
+#define PAD64_PE_SZ 1
+#define PAD64_DS_MSK 0x00000004
+#define PAD64_DS_I_MSK 0xfffffffb
+#define PAD64_DS_SFT 2
+#define PAD64_DS_HI 2
+#define PAD64_DS_SZ 1
+#define PAD64_IE_MSK 0x00000008
+#define PAD64_IE_I_MSK 0xfffffff7
+#define PAD64_IE_SFT 3
+#define PAD64_IE_HI 3
+#define PAD64_IE_SZ 1
+#define PAD64_SEL_I_MSK 0x00000070
+#define PAD64_SEL_I_I_MSK 0xffffff8f
+#define PAD64_SEL_I_SFT 4
+#define PAD64_SEL_I_HI 6
+#define PAD64_SEL_I_SZ 3
+#define PAD64_OD_MSK 0x00000100
+#define PAD64_OD_I_MSK 0xfffffeff
+#define PAD64_OD_SFT 8
+#define PAD64_OD_HI 8
+#define PAD64_OD_SZ 1
+#define PAD64_SEL_O_MSK 0x00003000
+#define PAD64_SEL_O_I_MSK 0xffffcfff
+#define PAD64_SEL_O_SFT 12
+#define PAD64_SEL_O_HI 13
+#define PAD64_SEL_O_SZ 2
+#define PAD64_SEL_OE_MSK 0x00100000
+#define PAD64_SEL_OE_I_MSK 0xffefffff
+#define PAD64_SEL_OE_SFT 20
+#define PAD64_SEL_OE_HI 20
+#define PAD64_SEL_OE_SZ 1
+#define GPIO_15_IP_ID_MSK 0x10000000
+#define GPIO_15_IP_ID_I_MSK 0xefffffff
+#define GPIO_15_IP_ID_SFT 28
+#define GPIO_15_IP_ID_HI 28
+#define GPIO_15_IP_ID_SZ 1
+#define PAD65_OE_MSK 0x00000001
+#define PAD65_OE_I_MSK 0xfffffffe
+#define PAD65_OE_SFT 0
+#define PAD65_OE_HI 0
+#define PAD65_OE_SZ 1
+#define PAD65_PE_MSK 0x00000002
+#define PAD65_PE_I_MSK 0xfffffffd
+#define PAD65_PE_SFT 1
+#define PAD65_PE_HI 1
+#define PAD65_PE_SZ 1
+#define PAD65_DS_MSK 0x00000004
+#define PAD65_DS_I_MSK 0xfffffffb
+#define PAD65_DS_SFT 2
+#define PAD65_DS_HI 2
+#define PAD65_DS_SZ 1
+#define PAD65_IE_MSK 0x00000008
+#define PAD65_IE_I_MSK 0xfffffff7
+#define PAD65_IE_SFT 3
+#define PAD65_IE_HI 3
+#define PAD65_IE_SZ 1
+#define PAD65_SEL_I_MSK 0x00000070
+#define PAD65_SEL_I_I_MSK 0xffffff8f
+#define PAD65_SEL_I_SFT 4
+#define PAD65_SEL_I_HI 6
+#define PAD65_SEL_I_SZ 3
+#define PAD65_OD_MSK 0x00000100
+#define PAD65_OD_I_MSK 0xfffffeff
+#define PAD65_OD_SFT 8
+#define PAD65_OD_HI 8
+#define PAD65_OD_SZ 1
+#define PAD65_SEL_O_MSK 0x00001000
+#define PAD65_SEL_O_I_MSK 0xffffefff
+#define PAD65_SEL_O_SFT 12
+#define PAD65_SEL_O_HI 12
+#define PAD65_SEL_O_SZ 1
+#define GPIO_TEST_7_IN_ID_MSK 0x10000000
+#define GPIO_TEST_7_IN_ID_I_MSK 0xefffffff
+#define GPIO_TEST_7_IN_ID_SFT 28
+#define GPIO_TEST_7_IN_ID_HI 28
+#define GPIO_TEST_7_IN_ID_SZ 1
+#define PAD66_OE_MSK 0x00000001
+#define PAD66_OE_I_MSK 0xfffffffe
+#define PAD66_OE_SFT 0
+#define PAD66_OE_HI 0
+#define PAD66_OE_SZ 1
+#define PAD66_PE_MSK 0x00000002
+#define PAD66_PE_I_MSK 0xfffffffd
+#define PAD66_PE_SFT 1
+#define PAD66_PE_HI 1
+#define PAD66_PE_SZ 1
+#define PAD66_DS_MSK 0x00000004
+#define PAD66_DS_I_MSK 0xfffffffb
+#define PAD66_DS_SFT 2
+#define PAD66_DS_HI 2
+#define PAD66_DS_SZ 1
+#define PAD66_IE_MSK 0x00000008
+#define PAD66_IE_I_MSK 0xfffffff7
+#define PAD66_IE_SFT 3
+#define PAD66_IE_HI 3
+#define PAD66_IE_SZ 1
+#define PAD66_SEL_I_MSK 0x00000030
+#define PAD66_SEL_I_I_MSK 0xffffffcf
+#define PAD66_SEL_I_SFT 4
+#define PAD66_SEL_I_HI 5
+#define PAD66_SEL_I_SZ 2
+#define PAD66_OD_MSK 0x00000100
+#define PAD66_OD_I_MSK 0xfffffeff
+#define PAD66_OD_SFT 8
+#define PAD66_OD_HI 8
+#define PAD66_OD_SZ 1
+#define PAD66_SEL_O_MSK 0x00003000
+#define PAD66_SEL_O_I_MSK 0xffffcfff
+#define PAD66_SEL_O_SFT 12
+#define PAD66_SEL_O_HI 13
+#define PAD66_SEL_O_SZ 2
+#define GPIO_17_QP_ID_MSK 0x10000000
+#define GPIO_17_QP_ID_I_MSK 0xefffffff
+#define GPIO_17_QP_ID_SFT 28
+#define GPIO_17_QP_ID_HI 28
+#define GPIO_17_QP_ID_SZ 1
+#define PAD68_OE_MSK 0x00000001
+#define PAD68_OE_I_MSK 0xfffffffe
+#define PAD68_OE_SFT 0
+#define PAD68_OE_HI 0
+#define PAD68_OE_SZ 1
+#define PAD68_PE_MSK 0x00000002
+#define PAD68_PE_I_MSK 0xfffffffd
+#define PAD68_PE_SFT 1
+#define PAD68_PE_HI 1
+#define PAD68_PE_SZ 1
+#define PAD68_DS_MSK 0x00000004
+#define PAD68_DS_I_MSK 0xfffffffb
+#define PAD68_DS_SFT 2
+#define PAD68_DS_HI 2
+#define PAD68_DS_SZ 1
+#define PAD68_IE_MSK 0x00000008
+#define PAD68_IE_I_MSK 0xfffffff7
+#define PAD68_IE_SFT 3
+#define PAD68_IE_HI 3
+#define PAD68_IE_SZ 1
+#define PAD68_OD_MSK 0x00000100
+#define PAD68_OD_I_MSK 0xfffffeff
+#define PAD68_OD_SFT 8
+#define PAD68_OD_HI 8
+#define PAD68_OD_SZ 1
+#define PAD68_SEL_O_MSK 0x00001000
+#define PAD68_SEL_O_I_MSK 0xffffefff
+#define PAD68_SEL_O_SFT 12
+#define PAD68_SEL_O_HI 12
+#define PAD68_SEL_O_SZ 1
+#define GPIO_19_ID_MSK 0x10000000
+#define GPIO_19_ID_I_MSK 0xefffffff
+#define GPIO_19_ID_SFT 28
+#define GPIO_19_ID_HI 28
+#define GPIO_19_ID_SZ 1
+#define PAD67_OE_MSK 0x00000001
+#define PAD67_OE_I_MSK 0xfffffffe
+#define PAD67_OE_SFT 0
+#define PAD67_OE_HI 0
+#define PAD67_OE_SZ 1
+#define PAD67_PE_MSK 0x00000002
+#define PAD67_PE_I_MSK 0xfffffffd
+#define PAD67_PE_SFT 1
+#define PAD67_PE_HI 1
+#define PAD67_PE_SZ 1
+#define PAD67_DS_MSK 0x00000004
+#define PAD67_DS_I_MSK 0xfffffffb
+#define PAD67_DS_SFT 2
+#define PAD67_DS_HI 2
+#define PAD67_DS_SZ 1
+#define PAD67_IE_MSK 0x00000008
+#define PAD67_IE_I_MSK 0xfffffff7
+#define PAD67_IE_SFT 3
+#define PAD67_IE_HI 3
+#define PAD67_IE_SZ 1
+#define PAD67_SEL_I_MSK 0x00000070
+#define PAD67_SEL_I_I_MSK 0xffffff8f
+#define PAD67_SEL_I_SFT 4
+#define PAD67_SEL_I_HI 6
+#define PAD67_SEL_I_SZ 3
+#define PAD67_OD_MSK 0x00000100
+#define PAD67_OD_I_MSK 0xfffffeff
+#define PAD67_OD_SFT 8
+#define PAD67_OD_HI 8
+#define PAD67_OD_SZ 1
+#define PAD67_SEL_O_MSK 0x00003000
+#define PAD67_SEL_O_I_MSK 0xffffcfff
+#define PAD67_SEL_O_SFT 12
+#define PAD67_SEL_O_HI 13
+#define PAD67_SEL_O_SZ 2
+#define GPIO_TEST_8_QN_ID_MSK 0x10000000
+#define GPIO_TEST_8_QN_ID_I_MSK 0xefffffff
+#define GPIO_TEST_8_QN_ID_SFT 28
+#define GPIO_TEST_8_QN_ID_HI 28
+#define GPIO_TEST_8_QN_ID_SZ 1
+#define PAD69_OE_MSK 0x00000001
+#define PAD69_OE_I_MSK 0xfffffffe
+#define PAD69_OE_SFT 0
+#define PAD69_OE_HI 0
+#define PAD69_OE_SZ 1
+#define PAD69_PE_MSK 0x00000002
+#define PAD69_PE_I_MSK 0xfffffffd
+#define PAD69_PE_SFT 1
+#define PAD69_PE_HI 1
+#define PAD69_PE_SZ 1
+#define PAD69_DS_MSK 0x00000004
+#define PAD69_DS_I_MSK 0xfffffffb
+#define PAD69_DS_SFT 2
+#define PAD69_DS_HI 2
+#define PAD69_DS_SZ 1
+#define PAD69_IE_MSK 0x00000008
+#define PAD69_IE_I_MSK 0xfffffff7
+#define PAD69_IE_SFT 3
+#define PAD69_IE_HI 3
+#define PAD69_IE_SZ 1
+#define PAD69_SEL_I_MSK 0x00000030
+#define PAD69_SEL_I_I_MSK 0xffffffcf
+#define PAD69_SEL_I_SFT 4
+#define PAD69_SEL_I_HI 5
+#define PAD69_SEL_I_SZ 2
+#define PAD69_OD_MSK 0x00000100
+#define PAD69_OD_I_MSK 0xfffffeff
+#define PAD69_OD_SFT 8
+#define PAD69_OD_HI 8
+#define PAD69_OD_SZ 1
+#define PAD69_SEL_O_MSK 0x00001000
+#define PAD69_SEL_O_I_MSK 0xffffefff
+#define PAD69_SEL_O_SFT 12
+#define PAD69_SEL_O_HI 12
+#define PAD69_SEL_O_SZ 1
+#define STRAP2_MSK 0x08000000
+#define STRAP2_I_MSK 0xf7ffffff
+#define STRAP2_SFT 27
+#define STRAP2_HI 27
+#define STRAP2_SZ 1
+#define GPIO_20_ID_MSK 0x10000000
+#define GPIO_20_ID_I_MSK 0xefffffff
+#define GPIO_20_ID_SFT 28
+#define GPIO_20_ID_HI 28
+#define GPIO_20_ID_SZ 1
+#define PAD70_OE_MSK 0x00000001
+#define PAD70_OE_I_MSK 0xfffffffe
+#define PAD70_OE_SFT 0
+#define PAD70_OE_HI 0
+#define PAD70_OE_SZ 1
+#define PAD70_PE_MSK 0x00000002
+#define PAD70_PE_I_MSK 0xfffffffd
+#define PAD70_PE_SFT 1
+#define PAD70_PE_HI 1
+#define PAD70_PE_SZ 1
+#define PAD70_DS_MSK 0x00000004
+#define PAD70_DS_I_MSK 0xfffffffb
+#define PAD70_DS_SFT 2
+#define PAD70_DS_HI 2
+#define PAD70_DS_SZ 1
+#define PAD70_IE_MSK 0x00000008
+#define PAD70_IE_I_MSK 0xfffffff7
+#define PAD70_IE_SFT 3
+#define PAD70_IE_HI 3
+#define PAD70_IE_SZ 1
+#define PAD70_SEL_I_MSK 0x00000030
+#define PAD70_SEL_I_I_MSK 0xffffffcf
+#define PAD70_SEL_I_SFT 4
+#define PAD70_SEL_I_HI 5
+#define PAD70_SEL_I_SZ 2
+#define PAD70_OD_MSK 0x00000100
+#define PAD70_OD_I_MSK 0xfffffeff
+#define PAD70_OD_SFT 8
+#define PAD70_OD_HI 8
+#define PAD70_OD_SZ 1
+#define PAD70_SEL_O_MSK 0x00007000
+#define PAD70_SEL_O_I_MSK 0xffff8fff
+#define PAD70_SEL_O_SFT 12
+#define PAD70_SEL_O_HI 14
+#define PAD70_SEL_O_SZ 3
+#define GPIO_21_ID_MSK 0x10000000
+#define GPIO_21_ID_I_MSK 0xefffffff
+#define GPIO_21_ID_SFT 28
+#define GPIO_21_ID_HI 28
+#define GPIO_21_ID_SZ 1
+#define PAD231_OE_MSK 0x00000001
+#define PAD231_OE_I_MSK 0xfffffffe
+#define PAD231_OE_SFT 0
+#define PAD231_OE_HI 0
+#define PAD231_OE_SZ 1
+#define PAD231_PE_MSK 0x00000002
+#define PAD231_PE_I_MSK 0xfffffffd
+#define PAD231_PE_SFT 1
+#define PAD231_PE_HI 1
+#define PAD231_PE_SZ 1
+#define PAD231_DS_MSK 0x00000004
+#define PAD231_DS_I_MSK 0xfffffffb
+#define PAD231_DS_SFT 2
+#define PAD231_DS_HI 2
+#define PAD231_DS_SZ 1
+#define PAD231_IE_MSK 0x00000008
+#define PAD231_IE_I_MSK 0xfffffff7
+#define PAD231_IE_SFT 3
+#define PAD231_IE_HI 3
+#define PAD231_IE_SZ 1
+#define PAD231_OD_MSK 0x00000100
+#define PAD231_OD_I_MSK 0xfffffeff
+#define PAD231_OD_SFT 8
+#define PAD231_OD_HI 8
+#define PAD231_OD_SZ 1
+#define PIN_40_OR_56_ID_MSK 0x10000000
+#define PIN_40_OR_56_ID_I_MSK 0xefffffff
+#define PIN_40_OR_56_ID_SFT 28
+#define PIN_40_OR_56_ID_HI 28
+#define PIN_40_OR_56_ID_SZ 1
+#define MP_PHY2RX_DATA__0_SEL_MSK 0x00000001
+#define MP_PHY2RX_DATA__0_SEL_I_MSK 0xfffffffe
+#define MP_PHY2RX_DATA__0_SEL_SFT 0
+#define MP_PHY2RX_DATA__0_SEL_HI 0
+#define MP_PHY2RX_DATA__0_SEL_SZ 1
+#define MP_PHY2RX_DATA__1_SEL_MSK 0x00000002
+#define MP_PHY2RX_DATA__1_SEL_I_MSK 0xfffffffd
+#define MP_PHY2RX_DATA__1_SEL_SFT 1
+#define MP_PHY2RX_DATA__1_SEL_HI 1
+#define MP_PHY2RX_DATA__1_SEL_SZ 1
+#define MP_TX_FF_RPTR__1_SEL_MSK 0x00000004
+#define MP_TX_FF_RPTR__1_SEL_I_MSK 0xfffffffb
+#define MP_TX_FF_RPTR__1_SEL_SFT 2
+#define MP_TX_FF_RPTR__1_SEL_HI 2
+#define MP_TX_FF_RPTR__1_SEL_SZ 1
+#define MP_RX_FF_WPTR__2_SEL_MSK 0x00000008
+#define MP_RX_FF_WPTR__2_SEL_I_MSK 0xfffffff7
+#define MP_RX_FF_WPTR__2_SEL_SFT 3
+#define MP_RX_FF_WPTR__2_SEL_HI 3
+#define MP_RX_FF_WPTR__2_SEL_SZ 1
+#define MP_RX_FF_WPTR__1_SEL_MSK 0x00000010
+#define MP_RX_FF_WPTR__1_SEL_I_MSK 0xffffffef
+#define MP_RX_FF_WPTR__1_SEL_SFT 4
+#define MP_RX_FF_WPTR__1_SEL_HI 4
+#define MP_RX_FF_WPTR__1_SEL_SZ 1
+#define MP_RX_FF_WPTR__0_SEL_MSK 0x00000020
+#define MP_RX_FF_WPTR__0_SEL_I_MSK 0xffffffdf
+#define MP_RX_FF_WPTR__0_SEL_SFT 5
+#define MP_RX_FF_WPTR__0_SEL_HI 5
+#define MP_RX_FF_WPTR__0_SEL_SZ 1
+#define MP_PHY2RX_DATA__2_SEL_MSK 0x00000040
+#define MP_PHY2RX_DATA__2_SEL_I_MSK 0xffffffbf
+#define MP_PHY2RX_DATA__2_SEL_SFT 6
+#define MP_PHY2RX_DATA__2_SEL_HI 6
+#define MP_PHY2RX_DATA__2_SEL_SZ 1
+#define MP_PHY2RX_DATA__4_SEL_MSK 0x00000080
+#define MP_PHY2RX_DATA__4_SEL_I_MSK 0xffffff7f
+#define MP_PHY2RX_DATA__4_SEL_SFT 7
+#define MP_PHY2RX_DATA__4_SEL_HI 7
+#define MP_PHY2RX_DATA__4_SEL_SZ 1
+#define I2CM_SDA_ID_SEL_MSK 0x00000300
+#define I2CM_SDA_ID_SEL_I_MSK 0xfffffcff
+#define I2CM_SDA_ID_SEL_SFT 8
+#define I2CM_SDA_ID_SEL_HI 9
+#define I2CM_SDA_ID_SEL_SZ 2
+#define CRYSTAL_OUT_REQ_SEL_MSK 0x00000400
+#define CRYSTAL_OUT_REQ_SEL_I_MSK 0xfffffbff
+#define CRYSTAL_OUT_REQ_SEL_SFT 10
+#define CRYSTAL_OUT_REQ_SEL_HI 10
+#define CRYSTAL_OUT_REQ_SEL_SZ 1
+#define MP_PHY2RX_DATA__5_SEL_MSK 0x00000800
+#define MP_PHY2RX_DATA__5_SEL_I_MSK 0xfffff7ff
+#define MP_PHY2RX_DATA__5_SEL_SFT 11
+#define MP_PHY2RX_DATA__5_SEL_HI 11
+#define MP_PHY2RX_DATA__5_SEL_SZ 1
+#define MP_PHY2RX_DATA__3_SEL_MSK 0x00001000
+#define MP_PHY2RX_DATA__3_SEL_I_MSK 0xffffefff
+#define MP_PHY2RX_DATA__3_SEL_SFT 12
+#define MP_PHY2RX_DATA__3_SEL_HI 12
+#define MP_PHY2RX_DATA__3_SEL_SZ 1
+#define UART_RXD_SEL_MSK 0x00006000
+#define UART_RXD_SEL_I_MSK 0xffff9fff
+#define UART_RXD_SEL_SFT 13
+#define UART_RXD_SEL_HI 14
+#define UART_RXD_SEL_SZ 2
+#define MP_PHY2RX_DATA__6_SEL_MSK 0x00008000
+#define MP_PHY2RX_DATA__6_SEL_I_MSK 0xffff7fff
+#define MP_PHY2RX_DATA__6_SEL_SFT 15
+#define MP_PHY2RX_DATA__6_SEL_HI 15
+#define MP_PHY2RX_DATA__6_SEL_SZ 1
+#define DAT_UART_NCTS_SEL_MSK 0x00010000
+#define DAT_UART_NCTS_SEL_I_MSK 0xfffeffff
+#define DAT_UART_NCTS_SEL_SFT 16
+#define DAT_UART_NCTS_SEL_HI 16
+#define DAT_UART_NCTS_SEL_SZ 1
+#define GPIO_LOG_STOP_SEL_MSK 0x000e0000
+#define GPIO_LOG_STOP_SEL_I_MSK 0xfff1ffff
+#define GPIO_LOG_STOP_SEL_SFT 17
+#define GPIO_LOG_STOP_SEL_HI 19
+#define GPIO_LOG_STOP_SEL_SZ 3
+#define MP_TX_FF_RPTR__0_SEL_MSK 0x00100000
+#define MP_TX_FF_RPTR__0_SEL_I_MSK 0xffefffff
+#define MP_TX_FF_RPTR__0_SEL_SFT 20
+#define MP_TX_FF_RPTR__0_SEL_HI 20
+#define MP_TX_FF_RPTR__0_SEL_SZ 1
+#define MP_PHY_RX_WRST_N_SEL_MSK 0x00200000
+#define MP_PHY_RX_WRST_N_SEL_I_MSK 0xffdfffff
+#define MP_PHY_RX_WRST_N_SEL_SFT 21
+#define MP_PHY_RX_WRST_N_SEL_HI 21
+#define MP_PHY_RX_WRST_N_SEL_SZ 1
+#define EXT_32K_SEL_MSK 0x00c00000
+#define EXT_32K_SEL_I_MSK 0xff3fffff
+#define EXT_32K_SEL_SFT 22
+#define EXT_32K_SEL_HI 23
+#define EXT_32K_SEL_SZ 2
+#define MP_PHY2RX_DATA__7_SEL_MSK 0x01000000
+#define MP_PHY2RX_DATA__7_SEL_I_MSK 0xfeffffff
+#define MP_PHY2RX_DATA__7_SEL_SFT 24
+#define MP_PHY2RX_DATA__7_SEL_HI 24
+#define MP_PHY2RX_DATA__7_SEL_SZ 1
+#define MP_TX_FF_RPTR__2_SEL_MSK 0x02000000
+#define MP_TX_FF_RPTR__2_SEL_I_MSK 0xfdffffff
+#define MP_TX_FF_RPTR__2_SEL_SFT 25
+#define MP_TX_FF_RPTR__2_SEL_HI 25
+#define MP_TX_FF_RPTR__2_SEL_SZ 1
+#define PMUINT_WAKE_SEL_MSK 0x1c000000
+#define PMUINT_WAKE_SEL_I_MSK 0xe3ffffff
+#define PMUINT_WAKE_SEL_SFT 26
+#define PMUINT_WAKE_SEL_HI 28
+#define PMUINT_WAKE_SEL_SZ 3
+#define I2CM_SCL_ID_SEL_MSK 0x20000000
+#define I2CM_SCL_ID_SEL_I_MSK 0xdfffffff
+#define I2CM_SCL_ID_SEL_SFT 29
+#define I2CM_SCL_ID_SEL_HI 29
+#define I2CM_SCL_ID_SEL_SZ 1
+#define MP_MRX_RX_EN_SEL_MSK 0x40000000
+#define MP_MRX_RX_EN_SEL_I_MSK 0xbfffffff
+#define MP_MRX_RX_EN_SEL_SFT 30
+#define MP_MRX_RX_EN_SEL_HI 30
+#define MP_MRX_RX_EN_SEL_SZ 1
+#define DAT_UART_RXD_SEL_0_MSK 0x80000000
+#define DAT_UART_RXD_SEL_0_I_MSK 0x7fffffff
+#define DAT_UART_RXD_SEL_0_SFT 31
+#define DAT_UART_RXD_SEL_0_HI 31
+#define DAT_UART_RXD_SEL_0_SZ 1
+#define DAT_UART_RXD_SEL_1_MSK 0x00000001
+#define DAT_UART_RXD_SEL_1_I_MSK 0xfffffffe
+#define DAT_UART_RXD_SEL_1_SFT 0
+#define DAT_UART_RXD_SEL_1_HI 0
+#define DAT_UART_RXD_SEL_1_SZ 1
+#define SPI_DI_SEL_MSK 0x00000002
+#define SPI_DI_SEL_I_MSK 0xfffffffd
+#define SPI_DI_SEL_SFT 1
+#define SPI_DI_SEL_HI 1
+#define SPI_DI_SEL_SZ 1
+#define IO_PORT_REG_MSK 0x0001ffff
+#define IO_PORT_REG_I_MSK 0xfffe0000
+#define IO_PORT_REG_SFT 0
+#define IO_PORT_REG_HI 16
+#define IO_PORT_REG_SZ 17
+#define MASK_RX_INT_MSK 0x00000001
+#define MASK_RX_INT_I_MSK 0xfffffffe
+#define MASK_RX_INT_SFT 0
+#define MASK_RX_INT_HI 0
+#define MASK_RX_INT_SZ 1
+#define MASK_TX_INT_MSK 0x00000002
+#define MASK_TX_INT_I_MSK 0xfffffffd
+#define MASK_TX_INT_SFT 1
+#define MASK_TX_INT_HI 1
+#define MASK_TX_INT_SZ 1
+#define MASK_SOC_SYSTEM_INT_MSK 0x00000004
+#define MASK_SOC_SYSTEM_INT_I_MSK 0xfffffffb
+#define MASK_SOC_SYSTEM_INT_SFT 2
+#define MASK_SOC_SYSTEM_INT_HI 2
+#define MASK_SOC_SYSTEM_INT_SZ 1
+#define EDCA0_LOW_THR_INT_MASK_MSK 0x00000008
+#define EDCA0_LOW_THR_INT_MASK_I_MSK 0xfffffff7
+#define EDCA0_LOW_THR_INT_MASK_SFT 3
+#define EDCA0_LOW_THR_INT_MASK_HI 3
+#define EDCA0_LOW_THR_INT_MASK_SZ 1
+#define EDCA1_LOW_THR_INT_MASK_MSK 0x00000010
+#define EDCA1_LOW_THR_INT_MASK_I_MSK 0xffffffef
+#define EDCA1_LOW_THR_INT_MASK_SFT 4
+#define EDCA1_LOW_THR_INT_MASK_HI 4
+#define EDCA1_LOW_THR_INT_MASK_SZ 1
+#define EDCA2_LOW_THR_INT_MASK_MSK 0x00000020
+#define EDCA2_LOW_THR_INT_MASK_I_MSK 0xffffffdf
+#define EDCA2_LOW_THR_INT_MASK_SFT 5
+#define EDCA2_LOW_THR_INT_MASK_HI 5
+#define EDCA2_LOW_THR_INT_MASK_SZ 1
+#define EDCA3_LOW_THR_INT_MASK_MSK 0x00000040
+#define EDCA3_LOW_THR_INT_MASK_I_MSK 0xffffffbf
+#define EDCA3_LOW_THR_INT_MASK_SFT 6
+#define EDCA3_LOW_THR_INT_MASK_HI 6
+#define EDCA3_LOW_THR_INT_MASK_SZ 1
+#define TX_LIMIT_INT_MASK_MSK 0x00000080
+#define TX_LIMIT_INT_MASK_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_MASK_SFT 7
+#define TX_LIMIT_INT_MASK_HI 7
+#define TX_LIMIT_INT_MASK_SZ 1
+#define RX_INT_MSK 0x00000001
+#define RX_INT_I_MSK 0xfffffffe
+#define RX_INT_SFT 0
+#define RX_INT_HI 0
+#define RX_INT_SZ 1
+#define TX_COMPLETE_INT_MSK 0x00000002
+#define TX_COMPLETE_INT_I_MSK 0xfffffffd
+#define TX_COMPLETE_INT_SFT 1
+#define TX_COMPLETE_INT_HI 1
+#define TX_COMPLETE_INT_SZ 1
+#define SOC_SYSTEM_INT_STATUS_MSK 0x00000004
+#define SOC_SYSTEM_INT_STATUS_I_MSK 0xfffffffb
+#define SOC_SYSTEM_INT_STATUS_SFT 2
+#define SOC_SYSTEM_INT_STATUS_HI 2
+#define SOC_SYSTEM_INT_STATUS_SZ 1
+#define EDCA0_LOW_THR_INT_STS_MSK 0x00000008
+#define EDCA0_LOW_THR_INT_STS_I_MSK 0xfffffff7
+#define EDCA0_LOW_THR_INT_STS_SFT 3
+#define EDCA0_LOW_THR_INT_STS_HI 3
+#define EDCA0_LOW_THR_INT_STS_SZ 1
+#define EDCA1_LOW_THR_INT_STS_MSK 0x00000010
+#define EDCA1_LOW_THR_INT_STS_I_MSK 0xffffffef
+#define EDCA1_LOW_THR_INT_STS_SFT 4
+#define EDCA1_LOW_THR_INT_STS_HI 4
+#define EDCA1_LOW_THR_INT_STS_SZ 1
+#define EDCA2_LOW_THR_INT_STS_MSK 0x00000020
+#define EDCA2_LOW_THR_INT_STS_I_MSK 0xffffffdf
+#define EDCA2_LOW_THR_INT_STS_SFT 5
+#define EDCA2_LOW_THR_INT_STS_HI 5
+#define EDCA2_LOW_THR_INT_STS_SZ 1
+#define EDCA3_LOW_THR_INT_STS_MSK 0x00000040
+#define EDCA3_LOW_THR_INT_STS_I_MSK 0xffffffbf
+#define EDCA3_LOW_THR_INT_STS_SFT 6
+#define EDCA3_LOW_THR_INT_STS_HI 6
+#define EDCA3_LOW_THR_INT_STS_SZ 1
+#define TX_LIMIT_INT_STS_MSK 0x00000080
+#define TX_LIMIT_INT_STS_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_STS_SFT 7
+#define TX_LIMIT_INT_STS_HI 7
+#define TX_LIMIT_INT_STS_SZ 1
+#define HOST_TRIGGERED_RX_INT_MSK 0x00000100
+#define HOST_TRIGGERED_RX_INT_I_MSK 0xfffffeff
+#define HOST_TRIGGERED_RX_INT_SFT 8
+#define HOST_TRIGGERED_RX_INT_HI 8
+#define HOST_TRIGGERED_RX_INT_SZ 1
+#define HOST_TRIGGERED_TX_INT_MSK 0x00000200
+#define HOST_TRIGGERED_TX_INT_I_MSK 0xfffffdff
+#define HOST_TRIGGERED_TX_INT_SFT 9
+#define HOST_TRIGGERED_TX_INT_HI 9
+#define HOST_TRIGGERED_TX_INT_SZ 1
+#define SOC_TRIGGER_RX_INT_MSK 0x00000400
+#define SOC_TRIGGER_RX_INT_I_MSK 0xfffffbff
+#define SOC_TRIGGER_RX_INT_SFT 10
+#define SOC_TRIGGER_RX_INT_HI 10
+#define SOC_TRIGGER_RX_INT_SZ 1
+#define SOC_TRIGGER_TX_INT_MSK 0x00000800
+#define SOC_TRIGGER_TX_INT_I_MSK 0xfffff7ff
+#define SOC_TRIGGER_TX_INT_SFT 11
+#define SOC_TRIGGER_TX_INT_HI 11
+#define SOC_TRIGGER_TX_INT_SZ 1
+#define RDY_FOR_TX_RX_MSK 0x00000001
+#define RDY_FOR_TX_RX_I_MSK 0xfffffffe
+#define RDY_FOR_TX_RX_SFT 0
+#define RDY_FOR_TX_RX_HI 0
+#define RDY_FOR_TX_RX_SZ 1
+#define RDY_FOR_FW_DOWNLOAD_MSK 0x00000002
+#define RDY_FOR_FW_DOWNLOAD_I_MSK 0xfffffffd
+#define RDY_FOR_FW_DOWNLOAD_SFT 1
+#define RDY_FOR_FW_DOWNLOAD_HI 1
+#define RDY_FOR_FW_DOWNLOAD_SZ 1
+#define ILLEGAL_CMD_RESP_OPTION_MSK 0x00000004
+#define ILLEGAL_CMD_RESP_OPTION_I_MSK 0xfffffffb
+#define ILLEGAL_CMD_RESP_OPTION_SFT 2
+#define ILLEGAL_CMD_RESP_OPTION_HI 2
+#define ILLEGAL_CMD_RESP_OPTION_SZ 1
+#define SDIO_TRX_DATA_SEQUENCE_MSK 0x00000008
+#define SDIO_TRX_DATA_SEQUENCE_I_MSK 0xfffffff7
+#define SDIO_TRX_DATA_SEQUENCE_SFT 3
+#define SDIO_TRX_DATA_SEQUENCE_HI 3
+#define SDIO_TRX_DATA_SEQUENCE_SZ 1
+#define GPIO_INT_TRIGGER_OPTION_MSK 0x00000010
+#define GPIO_INT_TRIGGER_OPTION_I_MSK 0xffffffef
+#define GPIO_INT_TRIGGER_OPTION_SFT 4
+#define GPIO_INT_TRIGGER_OPTION_HI 4
+#define GPIO_INT_TRIGGER_OPTION_SZ 1
+#define TRIGGER_FUNCTION_SETTING_MSK 0x00000060
+#define TRIGGER_FUNCTION_SETTING_I_MSK 0xffffff9f
+#define TRIGGER_FUNCTION_SETTING_SFT 5
+#define TRIGGER_FUNCTION_SETTING_HI 6
+#define TRIGGER_FUNCTION_SETTING_SZ 2
+#define CMD52_ABORT_RESPONSE_MSK 0x00000080
+#define CMD52_ABORT_RESPONSE_I_MSK 0xffffff7f
+#define CMD52_ABORT_RESPONSE_SFT 7
+#define CMD52_ABORT_RESPONSE_HI 7
+#define CMD52_ABORT_RESPONSE_SZ 1
+#define RX_PACKET_LENGTH_MSK 0x0000ffff
+#define RX_PACKET_LENGTH_I_MSK 0xffff0000
+#define RX_PACKET_LENGTH_SFT 0
+#define RX_PACKET_LENGTH_HI 15
+#define RX_PACKET_LENGTH_SZ 16
+#define CARD_FW_DL_STATUS_MSK 0x00ff0000
+#define CARD_FW_DL_STATUS_I_MSK 0xff00ffff
+#define CARD_FW_DL_STATUS_SFT 16
+#define CARD_FW_DL_STATUS_HI 23
+#define CARD_FW_DL_STATUS_SZ 8
+#define TX_RX_LOOP_BACK_TEST_MSK 0x01000000
+#define TX_RX_LOOP_BACK_TEST_I_MSK 0xfeffffff
+#define TX_RX_LOOP_BACK_TEST_SFT 24
+#define TX_RX_LOOP_BACK_TEST_HI 24
+#define TX_RX_LOOP_BACK_TEST_SZ 1
+#define SDIO_LOOP_BACK_TEST_MSK 0x02000000
+#define SDIO_LOOP_BACK_TEST_I_MSK 0xfdffffff
+#define SDIO_LOOP_BACK_TEST_SFT 25
+#define SDIO_LOOP_BACK_TEST_HI 25
+#define SDIO_LOOP_BACK_TEST_SZ 1
+#define CMD52_ABORT_ACTIVE_MSK 0x10000000
+#define CMD52_ABORT_ACTIVE_I_MSK 0xefffffff
+#define CMD52_ABORT_ACTIVE_SFT 28
+#define CMD52_ABORT_ACTIVE_HI 28
+#define CMD52_ABORT_ACTIVE_SZ 1
+#define CMD52_RESET_ACTIVE_MSK 0x20000000
+#define CMD52_RESET_ACTIVE_I_MSK 0xdfffffff
+#define CMD52_RESET_ACTIVE_SFT 29
+#define CMD52_RESET_ACTIVE_HI 29
+#define CMD52_RESET_ACTIVE_SZ 1
+#define SDIO_PARTIAL_RESET_ACTIVE_MSK 0x40000000
+#define SDIO_PARTIAL_RESET_ACTIVE_I_MSK 0xbfffffff
+#define SDIO_PARTIAL_RESET_ACTIVE_SFT 30
+#define SDIO_PARTIAL_RESET_ACTIVE_HI 30
+#define SDIO_PARTIAL_RESET_ACTIVE_SZ 1
+#define SDIO_ALL_RESE_ACTIVE_MSK 0x80000000
+#define SDIO_ALL_RESE_ACTIVE_I_MSK 0x7fffffff
+#define SDIO_ALL_RESE_ACTIVE_SFT 31
+#define SDIO_ALL_RESE_ACTIVE_HI 31
+#define SDIO_ALL_RESE_ACTIVE_SZ 1
+#define RX_PACKET_LENGTH2_MSK 0x0000ffff
+#define RX_PACKET_LENGTH2_I_MSK 0xffff0000
+#define RX_PACKET_LENGTH2_SFT 0
+#define RX_PACKET_LENGTH2_HI 15
+#define RX_PACKET_LENGTH2_SZ 16
+#define RX_INT1_MSK 0x00010000
+#define RX_INT1_I_MSK 0xfffeffff
+#define RX_INT1_SFT 16
+#define RX_INT1_HI 16
+#define RX_INT1_SZ 1
+#define TX_DONE_MSK 0x00020000
+#define TX_DONE_I_MSK 0xfffdffff
+#define TX_DONE_SFT 17
+#define TX_DONE_HI 17
+#define TX_DONE_SZ 1
+#define HCI_TRX_FINISH_MSK 0x00040000
+#define HCI_TRX_FINISH_I_MSK 0xfffbffff
+#define HCI_TRX_FINISH_SFT 18
+#define HCI_TRX_FINISH_HI 18
+#define HCI_TRX_FINISH_SZ 1
+#define ALLOCATE_STATUS_MSK 0x00080000
+#define ALLOCATE_STATUS_I_MSK 0xfff7ffff
+#define ALLOCATE_STATUS_SFT 19
+#define ALLOCATE_STATUS_HI 19
+#define ALLOCATE_STATUS_SZ 1
+#define HCI_INPUT_FF_CNT_MSK 0x00f00000
+#define HCI_INPUT_FF_CNT_I_MSK 0xff0fffff
+#define HCI_INPUT_FF_CNT_SFT 20
+#define HCI_INPUT_FF_CNT_HI 23
+#define HCI_INPUT_FF_CNT_SZ 4
+#define HCI_OUTPUT_FF_CNT_MSK 0x1f000000
+#define HCI_OUTPUT_FF_CNT_I_MSK 0xe0ffffff
+#define HCI_OUTPUT_FF_CNT_SFT 24
+#define HCI_OUTPUT_FF_CNT_HI 28
+#define HCI_OUTPUT_FF_CNT_SZ 5
+#define AHB_HANG4_MSK 0x20000000
+#define AHB_HANG4_I_MSK 0xdfffffff
+#define AHB_HANG4_SFT 29
+#define AHB_HANG4_HI 29
+#define AHB_HANG4_SZ 1
+#define HCI_IN_QUE_EMPTY_MSK 0x40000000
+#define HCI_IN_QUE_EMPTY_I_MSK 0xbfffffff
+#define HCI_IN_QUE_EMPTY_SFT 30
+#define HCI_IN_QUE_EMPTY_HI 30
+#define HCI_IN_QUE_EMPTY_SZ 1
+#define SYSTEM_INT_MSK 0x80000000
+#define SYSTEM_INT_I_MSK 0x7fffffff
+#define SYSTEM_INT_SFT 31
+#define SYSTEM_INT_HI 31
+#define SYSTEM_INT_SZ 1
+#define CARD_RCA_REG_MSK 0x0000ffff
+#define CARD_RCA_REG_I_MSK 0xffff0000
+#define CARD_RCA_REG_SFT 0
+#define CARD_RCA_REG_HI 15
+#define CARD_RCA_REG_SZ 16
+#define SDIO_FIFO_WR_THLD_REG_MSK 0x000001ff
+#define SDIO_FIFO_WR_THLD_REG_I_MSK 0xfffffe00
+#define SDIO_FIFO_WR_THLD_REG_SFT 0
+#define SDIO_FIFO_WR_THLD_REG_HI 8
+#define SDIO_FIFO_WR_THLD_REG_SZ 9
+#define SDIO_FIFO_WR_LIMIT_REG_MSK 0x000001ff
+#define SDIO_FIFO_WR_LIMIT_REG_I_MSK 0xfffffe00
+#define SDIO_FIFO_WR_LIMIT_REG_SFT 0
+#define SDIO_FIFO_WR_LIMIT_REG_HI 8
+#define SDIO_FIFO_WR_LIMIT_REG_SZ 9
+#define SDIO_TX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
+#define SDIO_TX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
+#define SDIO_TX_DATA_BATCH_SIZE_REG_SFT 0
+#define SDIO_TX_DATA_BATCH_SIZE_REG_HI 8
+#define SDIO_TX_DATA_BATCH_SIZE_REG_SZ 9
+#define SDIO_THLD_FOR_CMD53RD_REG_MSK 0x000001ff
+#define SDIO_THLD_FOR_CMD53RD_REG_I_MSK 0xfffffe00
+#define SDIO_THLD_FOR_CMD53RD_REG_SFT 0
+#define SDIO_THLD_FOR_CMD53RD_REG_HI 8
+#define SDIO_THLD_FOR_CMD53RD_REG_SZ 9
+#define SDIO_RX_DATA_BATCH_SIZE_REG_MSK 0x000001ff
+#define SDIO_RX_DATA_BATCH_SIZE_REG_I_MSK 0xfffffe00
+#define SDIO_RX_DATA_BATCH_SIZE_REG_SFT 0
+#define SDIO_RX_DATA_BATCH_SIZE_REG_HI 8
+#define SDIO_RX_DATA_BATCH_SIZE_REG_SZ 9
+#define START_BYTE_VALUE_MSK 0x000000ff
+#define START_BYTE_VALUE_I_MSK 0xffffff00
+#define START_BYTE_VALUE_SFT 0
+#define START_BYTE_VALUE_HI 7
+#define START_BYTE_VALUE_SZ 8
+#define END_BYTE_VALUE_MSK 0x0000ff00
+#define END_BYTE_VALUE_I_MSK 0xffff00ff
+#define END_BYTE_VALUE_SFT 8
+#define END_BYTE_VALUE_HI 15
+#define END_BYTE_VALUE_SZ 8
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_MSK 0x000000ff
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_I_MSK 0xffffff00
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SFT 0
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_HI 7
+#define SDIO_BYTE_MODE_BATCH_SIZE_REG_SZ 8
+#define SDIO_LAST_CMD_INDEX_REG_MSK 0x0000003f
+#define SDIO_LAST_CMD_INDEX_REG_I_MSK 0xffffffc0
+#define SDIO_LAST_CMD_INDEX_REG_SFT 0
+#define SDIO_LAST_CMD_INDEX_REG_HI 5
+#define SDIO_LAST_CMD_INDEX_REG_SZ 6
+#define SDIO_LAST_CMD_CRC_REG_MSK 0x00007f00
+#define SDIO_LAST_CMD_CRC_REG_I_MSK 0xffff80ff
+#define SDIO_LAST_CMD_CRC_REG_SFT 8
+#define SDIO_LAST_CMD_CRC_REG_HI 14
+#define SDIO_LAST_CMD_CRC_REG_SZ 7
+#define SDIO_LAST_CMD_ARG_REG_MSK 0xffffffff
+#define SDIO_LAST_CMD_ARG_REG_I_MSK 0x00000000
+#define SDIO_LAST_CMD_ARG_REG_SFT 0
+#define SDIO_LAST_CMD_ARG_REG_HI 31
+#define SDIO_LAST_CMD_ARG_REG_SZ 32
+#define SDIO_BUS_STATE_REG_MSK 0x0000001f
+#define SDIO_BUS_STATE_REG_I_MSK 0xffffffe0
+#define SDIO_BUS_STATE_REG_SFT 0
+#define SDIO_BUS_STATE_REG_HI 4
+#define SDIO_BUS_STATE_REG_SZ 5
+#define SDIO_BUSY_LONG_CNT_MSK 0xffff0000
+#define SDIO_BUSY_LONG_CNT_I_MSK 0x0000ffff
+#define SDIO_BUSY_LONG_CNT_SFT 16
+#define SDIO_BUSY_LONG_CNT_HI 31
+#define SDIO_BUSY_LONG_CNT_SZ 16
+#define SDIO_CARD_STATUS_REG_MSK 0xffffffff
+#define SDIO_CARD_STATUS_REG_I_MSK 0x00000000
+#define SDIO_CARD_STATUS_REG_SFT 0
+#define SDIO_CARD_STATUS_REG_HI 31
+#define SDIO_CARD_STATUS_REG_SZ 32
+#define R5_RESPONSE_FLAG_MSK 0x000000ff
+#define R5_RESPONSE_FLAG_I_MSK 0xffffff00
+#define R5_RESPONSE_FLAG_SFT 0
+#define R5_RESPONSE_FLAG_HI 7
+#define R5_RESPONSE_FLAG_SZ 8
+#define RESP_OUT_EDGE_MSK 0x00000100
+#define RESP_OUT_EDGE_I_MSK 0xfffffeff
+#define RESP_OUT_EDGE_SFT 8
+#define RESP_OUT_EDGE_HI 8
+#define RESP_OUT_EDGE_SZ 1
+#define DAT_OUT_EDGE_MSK 0x00000200
+#define DAT_OUT_EDGE_I_MSK 0xfffffdff
+#define DAT_OUT_EDGE_SFT 9
+#define DAT_OUT_EDGE_HI 9
+#define DAT_OUT_EDGE_SZ 1
+#define MCU_TO_SDIO_INFO_MASK_MSK 0x00010000
+#define MCU_TO_SDIO_INFO_MASK_I_MSK 0xfffeffff
+#define MCU_TO_SDIO_INFO_MASK_SFT 16
+#define MCU_TO_SDIO_INFO_MASK_HI 16
+#define MCU_TO_SDIO_INFO_MASK_SZ 1
+#define INT_THROUGH_PIN_MSK 0x00020000
+#define INT_THROUGH_PIN_I_MSK 0xfffdffff
+#define INT_THROUGH_PIN_SFT 17
+#define INT_THROUGH_PIN_HI 17
+#define INT_THROUGH_PIN_SZ 1
+#define WRITE_DATA_MSK 0x000000ff
+#define WRITE_DATA_I_MSK 0xffffff00
+#define WRITE_DATA_SFT 0
+#define WRITE_DATA_HI 7
+#define WRITE_DATA_SZ 8
+#define WRITE_ADDRESS_MSK 0x0000ff00
+#define WRITE_ADDRESS_I_MSK 0xffff00ff
+#define WRITE_ADDRESS_SFT 8
+#define WRITE_ADDRESS_HI 15
+#define WRITE_ADDRESS_SZ 8
+#define READ_DATA_MSK 0x00ff0000
+#define READ_DATA_I_MSK 0xff00ffff
+#define READ_DATA_SFT 16
+#define READ_DATA_HI 23
+#define READ_DATA_SZ 8
+#define READ_ADDRESS_MSK 0xff000000
+#define READ_ADDRESS_I_MSK 0x00ffffff
+#define READ_ADDRESS_SFT 24
+#define READ_ADDRESS_HI 31
+#define READ_ADDRESS_SZ 8
+#define FN1_DMA_START_ADDR_REG_MSK 0xffffffff
+#define FN1_DMA_START_ADDR_REG_I_MSK 0x00000000
+#define FN1_DMA_START_ADDR_REG_SFT 0
+#define FN1_DMA_START_ADDR_REG_HI 31
+#define FN1_DMA_START_ADDR_REG_SZ 32
+#define SDIO_TO_MCU_INFO_MSK 0x000000ff
+#define SDIO_TO_MCU_INFO_I_MSK 0xffffff00
+#define SDIO_TO_MCU_INFO_SFT 0
+#define SDIO_TO_MCU_INFO_HI 7
+#define SDIO_TO_MCU_INFO_SZ 8
+#define SDIO_PARTIAL_RESET_MSK 0x00000100
+#define SDIO_PARTIAL_RESET_I_MSK 0xfffffeff
+#define SDIO_PARTIAL_RESET_SFT 8
+#define SDIO_PARTIAL_RESET_HI 8
+#define SDIO_PARTIAL_RESET_SZ 1
+#define SDIO_ALL_RESET_MSK 0x00000200
+#define SDIO_ALL_RESET_I_MSK 0xfffffdff
+#define SDIO_ALL_RESET_SFT 9
+#define SDIO_ALL_RESET_HI 9
+#define SDIO_ALL_RESET_SZ 1
+#define PERI_MAC_ALL_RESET_MSK 0x00000400
+#define PERI_MAC_ALL_RESET_I_MSK 0xfffffbff
+#define PERI_MAC_ALL_RESET_SFT 10
+#define PERI_MAC_ALL_RESET_HI 10
+#define PERI_MAC_ALL_RESET_SZ 1
+#define MAC_ALL_RESET_MSK 0x00000800
+#define MAC_ALL_RESET_I_MSK 0xfffff7ff
+#define MAC_ALL_RESET_SFT 11
+#define MAC_ALL_RESET_HI 11
+#define MAC_ALL_RESET_SZ 1
+#define AHB_BRIDGE_RESET_MSK 0x00001000
+#define AHB_BRIDGE_RESET_I_MSK 0xffffefff
+#define AHB_BRIDGE_RESET_SFT 12
+#define AHB_BRIDGE_RESET_HI 12
+#define AHB_BRIDGE_RESET_SZ 1
+#define IO_REG_PORT_REG_MSK 0x0001ffff
+#define IO_REG_PORT_REG_I_MSK 0xfffe0000
+#define IO_REG_PORT_REG_SFT 0
+#define IO_REG_PORT_REG_HI 16
+#define IO_REG_PORT_REG_SZ 17
+#define SDIO_FIFO_EMPTY_CNT_MSK 0x0000ffff
+#define SDIO_FIFO_EMPTY_CNT_I_MSK 0xffff0000
+#define SDIO_FIFO_EMPTY_CNT_SFT 0
+#define SDIO_FIFO_EMPTY_CNT_HI 15
+#define SDIO_FIFO_EMPTY_CNT_SZ 16
+#define SDIO_FIFO_FULL_CNT_MSK 0xffff0000
+#define SDIO_FIFO_FULL_CNT_I_MSK 0x0000ffff
+#define SDIO_FIFO_FULL_CNT_SFT 16
+#define SDIO_FIFO_FULL_CNT_HI 31
+#define SDIO_FIFO_FULL_CNT_SZ 16
+#define SDIO_CRC7_ERROR_CNT_MSK 0x0000ffff
+#define SDIO_CRC7_ERROR_CNT_I_MSK 0xffff0000
+#define SDIO_CRC7_ERROR_CNT_SFT 0
+#define SDIO_CRC7_ERROR_CNT_HI 15
+#define SDIO_CRC7_ERROR_CNT_SZ 16
+#define SDIO_CRC16_ERROR_CNT_MSK 0xffff0000
+#define SDIO_CRC16_ERROR_CNT_I_MSK 0x0000ffff
+#define SDIO_CRC16_ERROR_CNT_SFT 16
+#define SDIO_CRC16_ERROR_CNT_HI 31
+#define SDIO_CRC16_ERROR_CNT_SZ 16
+#define SDIO_RD_BLOCK_CNT_MSK 0x000001ff
+#define SDIO_RD_BLOCK_CNT_I_MSK 0xfffffe00
+#define SDIO_RD_BLOCK_CNT_SFT 0
+#define SDIO_RD_BLOCK_CNT_HI 8
+#define SDIO_RD_BLOCK_CNT_SZ 9
+#define SDIO_WR_BLOCK_CNT_MSK 0x01ff0000
+#define SDIO_WR_BLOCK_CNT_I_MSK 0xfe00ffff
+#define SDIO_WR_BLOCK_CNT_SFT 16
+#define SDIO_WR_BLOCK_CNT_HI 24
+#define SDIO_WR_BLOCK_CNT_SZ 9
+#define CMD52_RD_ABORT_CNT_MSK 0x000f0000
+#define CMD52_RD_ABORT_CNT_I_MSK 0xfff0ffff
+#define CMD52_RD_ABORT_CNT_SFT 16
+#define CMD52_RD_ABORT_CNT_HI 19
+#define CMD52_RD_ABORT_CNT_SZ 4
+#define CMD52_WR_ABORT_CNT_MSK 0x00f00000
+#define CMD52_WR_ABORT_CNT_I_MSK 0xff0fffff
+#define CMD52_WR_ABORT_CNT_SFT 20
+#define CMD52_WR_ABORT_CNT_HI 23
+#define CMD52_WR_ABORT_CNT_SZ 4
+#define SDIO_FIFO_WR_PTR_REG_MSK 0x000000ff
+#define SDIO_FIFO_WR_PTR_REG_I_MSK 0xffffff00
+#define SDIO_FIFO_WR_PTR_REG_SFT 0
+#define SDIO_FIFO_WR_PTR_REG_HI 7
+#define SDIO_FIFO_WR_PTR_REG_SZ 8
+#define SDIO_FIFO_RD_PTR_REG_MSK 0x0000ff00
+#define SDIO_FIFO_RD_PTR_REG_I_MSK 0xffff00ff
+#define SDIO_FIFO_RD_PTR_REG_SFT 8
+#define SDIO_FIFO_RD_PTR_REG_HI 15
+#define SDIO_FIFO_RD_PTR_REG_SZ 8
+#define SDIO_READ_DATA_CTRL_MSK 0x00010000
+#define SDIO_READ_DATA_CTRL_I_MSK 0xfffeffff
+#define SDIO_READ_DATA_CTRL_SFT 16
+#define SDIO_READ_DATA_CTRL_HI 16
+#define SDIO_READ_DATA_CTRL_SZ 1
+#define TX_SIZE_BEFORE_SHIFT_MSK 0x000000ff
+#define TX_SIZE_BEFORE_SHIFT_I_MSK 0xffffff00
+#define TX_SIZE_BEFORE_SHIFT_SFT 0
+#define TX_SIZE_BEFORE_SHIFT_HI 7
+#define TX_SIZE_BEFORE_SHIFT_SZ 8
+#define TX_SIZE_SHIFT_BITS_MSK 0x00000700
+#define TX_SIZE_SHIFT_BITS_I_MSK 0xfffff8ff
+#define TX_SIZE_SHIFT_BITS_SFT 8
+#define TX_SIZE_SHIFT_BITS_HI 10
+#define TX_SIZE_SHIFT_BITS_SZ 3
+#define SDIO_TX_ALLOC_STATE_MSK 0x00001000
+#define SDIO_TX_ALLOC_STATE_I_MSK 0xffffefff
+#define SDIO_TX_ALLOC_STATE_SFT 12
+#define SDIO_TX_ALLOC_STATE_HI 12
+#define SDIO_TX_ALLOC_STATE_SZ 1
+#define ALLOCATE_STATUS2_MSK 0x00010000
+#define ALLOCATE_STATUS2_I_MSK 0xfffeffff
+#define ALLOCATE_STATUS2_SFT 16
+#define ALLOCATE_STATUS2_HI 16
+#define ALLOCATE_STATUS2_SZ 1
+#define NO_ALLOCATE_SEND_ERROR_MSK 0x00020000
+#define NO_ALLOCATE_SEND_ERROR_I_MSK 0xfffdffff
+#define NO_ALLOCATE_SEND_ERROR_SFT 17
+#define NO_ALLOCATE_SEND_ERROR_HI 17
+#define NO_ALLOCATE_SEND_ERROR_SZ 1
+#define DOUBLE_ALLOCATE_ERROR_MSK 0x00040000
+#define DOUBLE_ALLOCATE_ERROR_I_MSK 0xfffbffff
+#define DOUBLE_ALLOCATE_ERROR_SFT 18
+#define DOUBLE_ALLOCATE_ERROR_HI 18
+#define DOUBLE_ALLOCATE_ERROR_SZ 1
+#define TX_DONE_STATUS_MSK 0x00080000
+#define TX_DONE_STATUS_I_MSK 0xfff7ffff
+#define TX_DONE_STATUS_SFT 19
+#define TX_DONE_STATUS_HI 19
+#define TX_DONE_STATUS_SZ 1
+#define AHB_HANG2_MSK 0x00100000
+#define AHB_HANG2_I_MSK 0xffefffff
+#define AHB_HANG2_SFT 20
+#define AHB_HANG2_HI 20
+#define AHB_HANG2_SZ 1
+#define HCI_TRX_FINISH2_MSK 0x00200000
+#define HCI_TRX_FINISH2_I_MSK 0xffdfffff
+#define HCI_TRX_FINISH2_SFT 21
+#define HCI_TRX_FINISH2_HI 21
+#define HCI_TRX_FINISH2_SZ 1
+#define INTR_RX_MSK 0x00400000
+#define INTR_RX_I_MSK 0xffbfffff
+#define INTR_RX_SFT 22
+#define INTR_RX_HI 22
+#define INTR_RX_SZ 1
+#define HCI_INPUT_QUEUE_FULL_MSK 0x00800000
+#define HCI_INPUT_QUEUE_FULL_I_MSK 0xff7fffff
+#define HCI_INPUT_QUEUE_FULL_SFT 23
+#define HCI_INPUT_QUEUE_FULL_HI 23
+#define HCI_INPUT_QUEUE_FULL_SZ 1
+#define ALLOCATESTATUS_MSK 0x00000001
+#define ALLOCATESTATUS_I_MSK 0xfffffffe
+#define ALLOCATESTATUS_SFT 0
+#define ALLOCATESTATUS_HI 0
+#define ALLOCATESTATUS_SZ 1
+#define HCI_TRX_FINISH3_MSK 0x00000002
+#define HCI_TRX_FINISH3_I_MSK 0xfffffffd
+#define HCI_TRX_FINISH3_SFT 1
+#define HCI_TRX_FINISH3_HI 1
+#define HCI_TRX_FINISH3_SZ 1
+#define HCI_IN_QUE_EMPTY2_MSK 0x00000004
+#define HCI_IN_QUE_EMPTY2_I_MSK 0xfffffffb
+#define HCI_IN_QUE_EMPTY2_SFT 2
+#define HCI_IN_QUE_EMPTY2_HI 2
+#define HCI_IN_QUE_EMPTY2_SZ 1
+#define MTX_MNG_UPTHOLD_INT_MSK 0x00000008
+#define MTX_MNG_UPTHOLD_INT_I_MSK 0xfffffff7
+#define MTX_MNG_UPTHOLD_INT_SFT 3
+#define MTX_MNG_UPTHOLD_INT_HI 3
+#define MTX_MNG_UPTHOLD_INT_SZ 1
+#define EDCA0_UPTHOLD_INT_MSK 0x00000010
+#define EDCA0_UPTHOLD_INT_I_MSK 0xffffffef
+#define EDCA0_UPTHOLD_INT_SFT 4
+#define EDCA0_UPTHOLD_INT_HI 4
+#define EDCA0_UPTHOLD_INT_SZ 1
+#define EDCA1_UPTHOLD_INT_MSK 0x00000020
+#define EDCA1_UPTHOLD_INT_I_MSK 0xffffffdf
+#define EDCA1_UPTHOLD_INT_SFT 5
+#define EDCA1_UPTHOLD_INT_HI 5
+#define EDCA1_UPTHOLD_INT_SZ 1
+#define EDCA2_UPTHOLD_INT_MSK 0x00000040
+#define EDCA2_UPTHOLD_INT_I_MSK 0xffffffbf
+#define EDCA2_UPTHOLD_INT_SFT 6
+#define EDCA2_UPTHOLD_INT_HI 6
+#define EDCA2_UPTHOLD_INT_SZ 1
+#define EDCA3_UPTHOLD_INT_MSK 0x00000080
+#define EDCA3_UPTHOLD_INT_I_MSK 0xffffff7f
+#define EDCA3_UPTHOLD_INT_SFT 7
+#define EDCA3_UPTHOLD_INT_HI 7
+#define EDCA3_UPTHOLD_INT_SZ 1
+#define TX_PAGE_REMAIN2_MSK 0x0000ff00
+#define TX_PAGE_REMAIN2_I_MSK 0xffff00ff
+#define TX_PAGE_REMAIN2_SFT 8
+#define TX_PAGE_REMAIN2_HI 15
+#define TX_PAGE_REMAIN2_SZ 8
+#define TX_ID_REMAIN3_MSK 0x007f0000
+#define TX_ID_REMAIN3_I_MSK 0xff80ffff
+#define TX_ID_REMAIN3_SFT 16
+#define TX_ID_REMAIN3_HI 22
+#define TX_ID_REMAIN3_SZ 7
+#define HCI_OUTPUT_FF_CNT_0_MSK 0x00800000
+#define HCI_OUTPUT_FF_CNT_0_I_MSK 0xff7fffff
+#define HCI_OUTPUT_FF_CNT_0_SFT 23
+#define HCI_OUTPUT_FF_CNT_0_HI 23
+#define HCI_OUTPUT_FF_CNT_0_SZ 1
+#define HCI_OUTPUT_FF_CNT2_MSK 0x0f000000
+#define HCI_OUTPUT_FF_CNT2_I_MSK 0xf0ffffff
+#define HCI_OUTPUT_FF_CNT2_SFT 24
+#define HCI_OUTPUT_FF_CNT2_HI 27
+#define HCI_OUTPUT_FF_CNT2_SZ 4
+#define HCI_INPUT_FF_CNT2_MSK 0xf0000000
+#define HCI_INPUT_FF_CNT2_I_MSK 0x0fffffff
+#define HCI_INPUT_FF_CNT2_SFT 28
+#define HCI_INPUT_FF_CNT2_HI 31
+#define HCI_INPUT_FF_CNT2_SZ 4
+#define F1_BLOCK_SIZE_0_REG_MSK 0x00000fff
+#define F1_BLOCK_SIZE_0_REG_I_MSK 0xfffff000
+#define F1_BLOCK_SIZE_0_REG_SFT 0
+#define F1_BLOCK_SIZE_0_REG_HI 11
+#define F1_BLOCK_SIZE_0_REG_SZ 12
+#define START_BYTE_VALUE2_MSK 0x000000ff
+#define START_BYTE_VALUE2_I_MSK 0xffffff00
+#define START_BYTE_VALUE2_SFT 0
+#define START_BYTE_VALUE2_HI 7
+#define START_BYTE_VALUE2_SZ 8
+#define COMMAND_COUNTER_MSK 0x0000ff00
+#define COMMAND_COUNTER_I_MSK 0xffff00ff
+#define COMMAND_COUNTER_SFT 8
+#define COMMAND_COUNTER_HI 15
+#define COMMAND_COUNTER_SZ 8
+#define CMD_LOG_PART1_MSK 0xffff0000
+#define CMD_LOG_PART1_I_MSK 0x0000ffff
+#define CMD_LOG_PART1_SFT 16
+#define CMD_LOG_PART1_HI 31
+#define CMD_LOG_PART1_SZ 16
+#define CMD_LOG_PART2_MSK 0x00ffffff
+#define CMD_LOG_PART2_I_MSK 0xff000000
+#define CMD_LOG_PART2_SFT 0
+#define CMD_LOG_PART2_HI 23
+#define CMD_LOG_PART2_SZ 24
+#define END_BYTE_VALUE2_MSK 0xff000000
+#define END_BYTE_VALUE2_I_MSK 0x00ffffff
+#define END_BYTE_VALUE2_SFT 24
+#define END_BYTE_VALUE2_HI 31
+#define END_BYTE_VALUE2_SZ 8
+#define RX_PACKET_LENGTH3_MSK 0x0000ffff
+#define RX_PACKET_LENGTH3_I_MSK 0xffff0000
+#define RX_PACKET_LENGTH3_SFT 0
+#define RX_PACKET_LENGTH3_HI 15
+#define RX_PACKET_LENGTH3_SZ 16
+#define RX_INT3_MSK 0x00010000
+#define RX_INT3_I_MSK 0xfffeffff
+#define RX_INT3_SFT 16
+#define RX_INT3_HI 16
+#define RX_INT3_SZ 1
+#define TX_ID_REMAIN2_MSK 0x00fe0000
+#define TX_ID_REMAIN2_I_MSK 0xff01ffff
+#define TX_ID_REMAIN2_SFT 17
+#define TX_ID_REMAIN2_HI 23
+#define TX_ID_REMAIN2_SZ 7
+#define TX_PAGE_REMAIN3_MSK 0xff000000
+#define TX_PAGE_REMAIN3_I_MSK 0x00ffffff
+#define TX_PAGE_REMAIN3_SFT 24
+#define TX_PAGE_REMAIN3_HI 31
+#define TX_PAGE_REMAIN3_SZ 8
+#define CCCR_00H_REG_MSK 0x000000ff
+#define CCCR_00H_REG_I_MSK 0xffffff00
+#define CCCR_00H_REG_SFT 0
+#define CCCR_00H_REG_HI 7
+#define CCCR_00H_REG_SZ 8
+#define CCCR_02H_REG_MSK 0x00ff0000
+#define CCCR_02H_REG_I_MSK 0xff00ffff
+#define CCCR_02H_REG_SFT 16
+#define CCCR_02H_REG_HI 23
+#define CCCR_02H_REG_SZ 8
+#define CCCR_03H_REG_MSK 0xff000000
+#define CCCR_03H_REG_I_MSK 0x00ffffff
+#define CCCR_03H_REG_SFT 24
+#define CCCR_03H_REG_HI 31
+#define CCCR_03H_REG_SZ 8
+#define CCCR_04H_REG_MSK 0x000000ff
+#define CCCR_04H_REG_I_MSK 0xffffff00
+#define CCCR_04H_REG_SFT 0
+#define CCCR_04H_REG_HI 7
+#define CCCR_04H_REG_SZ 8
+#define CCCR_05H_REG_MSK 0x0000ff00
+#define CCCR_05H_REG_I_MSK 0xffff00ff
+#define CCCR_05H_REG_SFT 8
+#define CCCR_05H_REG_HI 15
+#define CCCR_05H_REG_SZ 8
+#define CCCR_06H_REG_MSK 0x000f0000
+#define CCCR_06H_REG_I_MSK 0xfff0ffff
+#define CCCR_06H_REG_SFT 16
+#define CCCR_06H_REG_HI 19
+#define CCCR_06H_REG_SZ 4
+#define CCCR_07H_REG_MSK 0xff000000
+#define CCCR_07H_REG_I_MSK 0x00ffffff
+#define CCCR_07H_REG_SFT 24
+#define CCCR_07H_REG_HI 31
+#define CCCR_07H_REG_SZ 8
+#define SUPPORT_DIRECT_COMMAND_SDIO_MSK 0x00000001
+#define SUPPORT_DIRECT_COMMAND_SDIO_I_MSK 0xfffffffe
+#define SUPPORT_DIRECT_COMMAND_SDIO_SFT 0
+#define SUPPORT_DIRECT_COMMAND_SDIO_HI 0
+#define SUPPORT_DIRECT_COMMAND_SDIO_SZ 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_MSK 0x00000002
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_I_MSK 0xfffffffd
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SFT 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_HI 1
+#define SUPPORT_MULTIPLE_BLOCK_TRANSFER_SZ 1
+#define SUPPORT_READ_WAIT_MSK 0x00000004
+#define SUPPORT_READ_WAIT_I_MSK 0xfffffffb
+#define SUPPORT_READ_WAIT_SFT 2
+#define SUPPORT_READ_WAIT_HI 2
+#define SUPPORT_READ_WAIT_SZ 1
+#define SUPPORT_BUS_CONTROL_MSK 0x00000008
+#define SUPPORT_BUS_CONTROL_I_MSK 0xfffffff7
+#define SUPPORT_BUS_CONTROL_SFT 3
+#define SUPPORT_BUS_CONTROL_HI 3
+#define SUPPORT_BUS_CONTROL_SZ 1
+#define SUPPORT_BLOCK_GAP_INTERRUPT_MSK 0x00000010
+#define SUPPORT_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffef
+#define SUPPORT_BLOCK_GAP_INTERRUPT_SFT 4
+#define SUPPORT_BLOCK_GAP_INTERRUPT_HI 4
+#define SUPPORT_BLOCK_GAP_INTERRUPT_SZ 1
+#define ENABLE_BLOCK_GAP_INTERRUPT_MSK 0x00000020
+#define ENABLE_BLOCK_GAP_INTERRUPT_I_MSK 0xffffffdf
+#define ENABLE_BLOCK_GAP_INTERRUPT_SFT 5
+#define ENABLE_BLOCK_GAP_INTERRUPT_HI 5
+#define ENABLE_BLOCK_GAP_INTERRUPT_SZ 1
+#define LOW_SPEED_CARD_MSK 0x00000040
+#define LOW_SPEED_CARD_I_MSK 0xffffffbf
+#define LOW_SPEED_CARD_SFT 6
+#define LOW_SPEED_CARD_HI 6
+#define LOW_SPEED_CARD_SZ 1
+#define LOW_SPEED_CARD_4BIT_MSK 0x00000080
+#define LOW_SPEED_CARD_4BIT_I_MSK 0xffffff7f
+#define LOW_SPEED_CARD_4BIT_SFT 7
+#define LOW_SPEED_CARD_4BIT_HI 7
+#define LOW_SPEED_CARD_4BIT_SZ 1
+#define COMMON_CIS_PONTER_MSK 0x01ffff00
+#define COMMON_CIS_PONTER_I_MSK 0xfe0000ff
+#define COMMON_CIS_PONTER_SFT 8
+#define COMMON_CIS_PONTER_HI 24
+#define COMMON_CIS_PONTER_SZ 17
+#define SUPPORT_HIGH_SPEED_MSK 0x01000000
+#define SUPPORT_HIGH_SPEED_I_MSK 0xfeffffff
+#define SUPPORT_HIGH_SPEED_SFT 24
+#define SUPPORT_HIGH_SPEED_HI 24
+#define SUPPORT_HIGH_SPEED_SZ 1
+#define BSS_MSK 0x0e000000
+#define BSS_I_MSK 0xf1ffffff
+#define BSS_SFT 25
+#define BSS_HI 27
+#define BSS_SZ 3
+#define FBR_100H_REG_MSK 0x0000000f
+#define FBR_100H_REG_I_MSK 0xfffffff0
+#define FBR_100H_REG_SFT 0
+#define FBR_100H_REG_HI 3
+#define FBR_100H_REG_SZ 4
+#define CSASUPPORT_MSK 0x00000040
+#define CSASUPPORT_I_MSK 0xffffffbf
+#define CSASUPPORT_SFT 6
+#define CSASUPPORT_HI 6
+#define CSASUPPORT_SZ 1
+#define ENABLECSA_MSK 0x00000080
+#define ENABLECSA_I_MSK 0xffffff7f
+#define ENABLECSA_SFT 7
+#define ENABLECSA_HI 7
+#define ENABLECSA_SZ 1
+#define FBR_101H_REG_MSK 0x0000ff00
+#define FBR_101H_REG_I_MSK 0xffff00ff
+#define FBR_101H_REG_SFT 8
+#define FBR_101H_REG_HI 15
+#define FBR_101H_REG_SZ 8
+#define FBR_109H_REG_MSK 0x01ffff00
+#define FBR_109H_REG_I_MSK 0xfe0000ff
+#define FBR_109H_REG_SFT 8
+#define FBR_109H_REG_HI 24
+#define FBR_109H_REG_SZ 17
+#define F0_CIS_CONTENT_REG_31_0_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_31_0_SFT 0
+#define F0_CIS_CONTENT_REG_31_0_HI 31
+#define F0_CIS_CONTENT_REG_31_0_SZ 32
+#define F0_CIS_CONTENT_REG_63_32_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_63_32_SFT 0
+#define F0_CIS_CONTENT_REG_63_32_HI 31
+#define F0_CIS_CONTENT_REG_63_32_SZ 32
+#define F0_CIS_CONTENT_REG_95_64_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_95_64_SFT 0
+#define F0_CIS_CONTENT_REG_95_64_HI 31
+#define F0_CIS_CONTENT_REG_95_64_SZ 32
+#define F0_CIS_CONTENT_REG_127_96_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_127_96_SFT 0
+#define F0_CIS_CONTENT_REG_127_96_HI 31
+#define F0_CIS_CONTENT_REG_127_96_SZ 32
+#define F0_CIS_CONTENT_REG_159_128_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_159_128_SFT 0
+#define F0_CIS_CONTENT_REG_159_128_HI 31
+#define F0_CIS_CONTENT_REG_159_128_SZ 32
+#define F0_CIS_CONTENT_REG_191_160_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_191_160_SFT 0
+#define F0_CIS_CONTENT_REG_191_160_HI 31
+#define F0_CIS_CONTENT_REG_191_160_SZ 32
+#define F0_CIS_CONTENT_REG_223_192_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_223_192_SFT 0
+#define F0_CIS_CONTENT_REG_223_192_HI 31
+#define F0_CIS_CONTENT_REG_223_192_SZ 32
+#define F0_CIS_CONTENT_REG_255_224_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_255_224_SFT 0
+#define F0_CIS_CONTENT_REG_255_224_HI 31
+#define F0_CIS_CONTENT_REG_255_224_SZ 32
+#define F0_CIS_CONTENT_REG_287_256_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_287_256_SFT 0
+#define F0_CIS_CONTENT_REG_287_256_HI 31
+#define F0_CIS_CONTENT_REG_287_256_SZ 32
+#define F0_CIS_CONTENT_REG_319_288_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_319_288_SFT 0
+#define F0_CIS_CONTENT_REG_319_288_HI 31
+#define F0_CIS_CONTENT_REG_319_288_SZ 32
+#define F0_CIS_CONTENT_REG_351_320_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_351_320_SFT 0
+#define F0_CIS_CONTENT_REG_351_320_HI 31
+#define F0_CIS_CONTENT_REG_351_320_SZ 32
+#define F0_CIS_CONTENT_REG_383_352_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_383_352_SFT 0
+#define F0_CIS_CONTENT_REG_383_352_HI 31
+#define F0_CIS_CONTENT_REG_383_352_SZ 32
+#define F0_CIS_CONTENT_REG_415_384_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_415_384_SFT 0
+#define F0_CIS_CONTENT_REG_415_384_HI 31
+#define F0_CIS_CONTENT_REG_415_384_SZ 32
+#define F0_CIS_CONTENT_REG_447_416_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_447_416_SFT 0
+#define F0_CIS_CONTENT_REG_447_416_HI 31
+#define F0_CIS_CONTENT_REG_447_416_SZ 32
+#define F0_CIS_CONTENT_REG_479_448_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_479_448_SFT 0
+#define F0_CIS_CONTENT_REG_479_448_HI 31
+#define F0_CIS_CONTENT_REG_479_448_SZ 32
+#define F0_CIS_CONTENT_REG_511_480_MSK 0xffffffff
+#define F0_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
+#define F0_CIS_CONTENT_REG_511_480_SFT 0
+#define F0_CIS_CONTENT_REG_511_480_HI 31
+#define F0_CIS_CONTENT_REG_511_480_SZ 32
+#define F1_CIS_CONTENT_REG_31_0_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_31_0_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_31_0_SFT 0
+#define F1_CIS_CONTENT_REG_31_0_HI 31
+#define F1_CIS_CONTENT_REG_31_0_SZ 32
+#define F1_CIS_CONTENT_REG_63_32_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_63_32_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_63_32_SFT 0
+#define F1_CIS_CONTENT_REG_63_32_HI 31
+#define F1_CIS_CONTENT_REG_63_32_SZ 32
+#define F1_CIS_CONTENT_REG_95_64_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_95_64_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_95_64_SFT 0
+#define F1_CIS_CONTENT_REG_95_64_HI 31
+#define F1_CIS_CONTENT_REG_95_64_SZ 32
+#define F1_CIS_CONTENT_REG_127_96_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_127_96_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_127_96_SFT 0
+#define F1_CIS_CONTENT_REG_127_96_HI 31
+#define F1_CIS_CONTENT_REG_127_96_SZ 32
+#define F1_CIS_CONTENT_REG_159_128_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_159_128_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_159_128_SFT 0
+#define F1_CIS_CONTENT_REG_159_128_HI 31
+#define F1_CIS_CONTENT_REG_159_128_SZ 32
+#define F1_CIS_CONTENT_REG_191_160_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_191_160_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_191_160_SFT 0
+#define F1_CIS_CONTENT_REG_191_160_HI 31
+#define F1_CIS_CONTENT_REG_191_160_SZ 32
+#define F1_CIS_CONTENT_REG_223_192_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_223_192_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_223_192_SFT 0
+#define F1_CIS_CONTENT_REG_223_192_HI 31
+#define F1_CIS_CONTENT_REG_223_192_SZ 32
+#define F1_CIS_CONTENT_REG_255_224_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_255_224_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_255_224_SFT 0
+#define F1_CIS_CONTENT_REG_255_224_HI 31
+#define F1_CIS_CONTENT_REG_255_224_SZ 32
+#define F1_CIS_CONTENT_REG_287_256_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_287_256_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_287_256_SFT 0
+#define F1_CIS_CONTENT_REG_287_256_HI 31
+#define F1_CIS_CONTENT_REG_287_256_SZ 32
+#define F1_CIS_CONTENT_REG_319_288_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_319_288_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_319_288_SFT 0
+#define F1_CIS_CONTENT_REG_319_288_HI 31
+#define F1_CIS_CONTENT_REG_319_288_SZ 32
+#define F1_CIS_CONTENT_REG_351_320_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_351_320_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_351_320_SFT 0
+#define F1_CIS_CONTENT_REG_351_320_HI 31
+#define F1_CIS_CONTENT_REG_351_320_SZ 32
+#define F1_CIS_CONTENT_REG_383_352_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_383_352_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_383_352_SFT 0
+#define F1_CIS_CONTENT_REG_383_352_HI 31
+#define F1_CIS_CONTENT_REG_383_352_SZ 32
+#define F1_CIS_CONTENT_REG_415_384_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_415_384_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_415_384_SFT 0
+#define F1_CIS_CONTENT_REG_415_384_HI 31
+#define F1_CIS_CONTENT_REG_415_384_SZ 32
+#define F1_CIS_CONTENT_REG_447_416_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_447_416_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_447_416_SFT 0
+#define F1_CIS_CONTENT_REG_447_416_HI 31
+#define F1_CIS_CONTENT_REG_447_416_SZ 32
+#define F1_CIS_CONTENT_REG_479_448_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_479_448_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_479_448_SFT 0
+#define F1_CIS_CONTENT_REG_479_448_HI 31
+#define F1_CIS_CONTENT_REG_479_448_SZ 32
+#define F1_CIS_CONTENT_REG_511_480_MSK 0xffffffff
+#define F1_CIS_CONTENT_REG_511_480_I_MSK 0x00000000
+#define F1_CIS_CONTENT_REG_511_480_SFT 0
+#define F1_CIS_CONTENT_REG_511_480_HI 31
+#define F1_CIS_CONTENT_REG_511_480_SZ 32
+#define SPI_MODE_MSK 0xffffffff
+#define SPI_MODE_I_MSK 0x00000000
+#define SPI_MODE_SFT 0
+#define SPI_MODE_HI 31
+#define SPI_MODE_SZ 32
+#define RX_QUOTA_MSK 0x0000ffff
+#define RX_QUOTA_I_MSK 0xffff0000
+#define RX_QUOTA_SFT 0
+#define RX_QUOTA_HI 15
+#define RX_QUOTA_SZ 16
+#define CONDI_NUM_MSK 0x000000ff
+#define CONDI_NUM_I_MSK 0xffffff00
+#define CONDI_NUM_SFT 0
+#define CONDI_NUM_HI 7
+#define CONDI_NUM_SZ 8
+#define HOST_PATH_MSK 0x00000001
+#define HOST_PATH_I_MSK 0xfffffffe
+#define HOST_PATH_SFT 0
+#define HOST_PATH_HI 0
+#define HOST_PATH_SZ 1
+#define TX_SEG_MSK 0xffffffff
+#define TX_SEG_I_MSK 0x00000000
+#define TX_SEG_SFT 0
+#define TX_SEG_HI 31
+#define TX_SEG_SZ 32
+#define BRST_MODE_MSK 0x00000001
+#define BRST_MODE_I_MSK 0xfffffffe
+#define BRST_MODE_SFT 0
+#define BRST_MODE_HI 0
+#define BRST_MODE_SZ 1
+#define CLK_WIDTH_MSK 0x0000ffff
+#define CLK_WIDTH_I_MSK 0xffff0000
+#define CLK_WIDTH_SFT 0
+#define CLK_WIDTH_HI 15
+#define CLK_WIDTH_SZ 16
+#define CSN_INTER_MSK 0xffff0000
+#define CSN_INTER_I_MSK 0x0000ffff
+#define CSN_INTER_SFT 16
+#define CSN_INTER_HI 31
+#define CSN_INTER_SZ 16
+#define BACK_DLY_MSK 0x0000ffff
+#define BACK_DLY_I_MSK 0xffff0000
+#define BACK_DLY_SFT 0
+#define BACK_DLY_HI 15
+#define BACK_DLY_SZ 16
+#define FRONT_DLY_MSK 0xffff0000
+#define FRONT_DLY_I_MSK 0x0000ffff
+#define FRONT_DLY_SFT 16
+#define FRONT_DLY_HI 31
+#define FRONT_DLY_SZ 16
+#define RX_FIFO_FAIL_MSK 0x00000002
+#define RX_FIFO_FAIL_I_MSK 0xfffffffd
+#define RX_FIFO_FAIL_SFT 1
+#define RX_FIFO_FAIL_HI 1
+#define RX_FIFO_FAIL_SZ 1
+#define RX_HOST_FAIL_MSK 0x00000004
+#define RX_HOST_FAIL_I_MSK 0xfffffffb
+#define RX_HOST_FAIL_SFT 2
+#define RX_HOST_FAIL_HI 2
+#define RX_HOST_FAIL_SZ 1
+#define TX_FIFO_FAIL_MSK 0x00000008
+#define TX_FIFO_FAIL_I_MSK 0xfffffff7
+#define TX_FIFO_FAIL_SFT 3
+#define TX_FIFO_FAIL_HI 3
+#define TX_FIFO_FAIL_SZ 1
+#define TX_HOST_FAIL_MSK 0x00000010
+#define TX_HOST_FAIL_I_MSK 0xffffffef
+#define TX_HOST_FAIL_SFT 4
+#define TX_HOST_FAIL_HI 4
+#define TX_HOST_FAIL_SZ 1
+#define SPI_DOUBLE_ALLOC_MSK 0x00000020
+#define SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
+#define SPI_DOUBLE_ALLOC_SFT 5
+#define SPI_DOUBLE_ALLOC_HI 5
+#define SPI_DOUBLE_ALLOC_SZ 1
+#define SPI_TX_NO_ALLOC_MSK 0x00000040
+#define SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
+#define SPI_TX_NO_ALLOC_SFT 6
+#define SPI_TX_NO_ALLOC_HI 6
+#define SPI_TX_NO_ALLOC_SZ 1
+#define RDATA_RDY_MSK 0x00000080
+#define RDATA_RDY_I_MSK 0xffffff7f
+#define RDATA_RDY_SFT 7
+#define RDATA_RDY_HI 7
+#define RDATA_RDY_SZ 1
+#define SPI_ALLOC_STATUS_MSK 0x00000100
+#define SPI_ALLOC_STATUS_I_MSK 0xfffffeff
+#define SPI_ALLOC_STATUS_SFT 8
+#define SPI_ALLOC_STATUS_HI 8
+#define SPI_ALLOC_STATUS_SZ 1
+#define SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
+#define SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
+#define SPI_DBG_WR_FIFO_FULL_SFT 9
+#define SPI_DBG_WR_FIFO_FULL_HI 9
+#define SPI_DBG_WR_FIFO_FULL_SZ 1
+#define RX_LEN_MSK 0xffff0000
+#define RX_LEN_I_MSK 0x0000ffff
+#define RX_LEN_SFT 16
+#define RX_LEN_HI 31
+#define RX_LEN_SZ 16
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
+#define SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
+#define SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
+#define SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
+#define SPI_HOST_TX_ALLOC_PKBUF_SFT 8
+#define SPI_HOST_TX_ALLOC_PKBUF_HI 8
+#define SPI_HOST_TX_ALLOC_PKBUF_SZ 1
+#define SPI_TX_ALLOC_SIZE_MSK 0x000000ff
+#define SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
+#define SPI_TX_ALLOC_SIZE_SFT 0
+#define SPI_TX_ALLOC_SIZE_HI 7
+#define SPI_TX_ALLOC_SIZE_SZ 8
+#define RD_DAT_CNT_MSK 0x0000ffff
+#define RD_DAT_CNT_I_MSK 0xffff0000
+#define RD_DAT_CNT_SFT 0
+#define RD_DAT_CNT_HI 15
+#define RD_DAT_CNT_SZ 16
+#define RD_STS_CNT_MSK 0xffff0000
+#define RD_STS_CNT_I_MSK 0x0000ffff
+#define RD_STS_CNT_SFT 16
+#define RD_STS_CNT_HI 31
+#define RD_STS_CNT_SZ 16
+#define JUDGE_CNT_MSK 0x0000ffff
+#define JUDGE_CNT_I_MSK 0xffff0000
+#define JUDGE_CNT_SFT 0
+#define JUDGE_CNT_HI 15
+#define JUDGE_CNT_SZ 16
+#define RD_STS_CNT_CLR_MSK 0x00010000
+#define RD_STS_CNT_CLR_I_MSK 0xfffeffff
+#define RD_STS_CNT_CLR_SFT 16
+#define RD_STS_CNT_CLR_HI 16
+#define RD_STS_CNT_CLR_SZ 1
+#define RD_DAT_CNT_CLR_MSK 0x00020000
+#define RD_DAT_CNT_CLR_I_MSK 0xfffdffff
+#define RD_DAT_CNT_CLR_SFT 17
+#define RD_DAT_CNT_CLR_HI 17
+#define RD_DAT_CNT_CLR_SZ 1
+#define JUDGE_CNT_CLR_MSK 0x00040000
+#define JUDGE_CNT_CLR_I_MSK 0xfffbffff
+#define JUDGE_CNT_CLR_SFT 18
+#define JUDGE_CNT_CLR_HI 18
+#define JUDGE_CNT_CLR_SZ 1
+#define TX_DONE_CNT_MSK 0x0000ffff
+#define TX_DONE_CNT_I_MSK 0xffff0000
+#define TX_DONE_CNT_SFT 0
+#define TX_DONE_CNT_HI 15
+#define TX_DONE_CNT_SZ 16
+#define TX_DISCARD_CNT_MSK 0xffff0000
+#define TX_DISCARD_CNT_I_MSK 0x0000ffff
+#define TX_DISCARD_CNT_SFT 16
+#define TX_DISCARD_CNT_HI 31
+#define TX_DISCARD_CNT_SZ 16
+#define TX_SET_CNT_MSK 0x0000ffff
+#define TX_SET_CNT_I_MSK 0xffff0000
+#define TX_SET_CNT_SFT 0
+#define TX_SET_CNT_HI 15
+#define TX_SET_CNT_SZ 16
+#define TX_DISCARD_CNT_CLR_MSK 0x00010000
+#define TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
+#define TX_DISCARD_CNT_CLR_SFT 16
+#define TX_DISCARD_CNT_CLR_HI 16
+#define TX_DISCARD_CNT_CLR_SZ 1
+#define TX_DONE_CNT_CLR_MSK 0x00020000
+#define TX_DONE_CNT_CLR_I_MSK 0xfffdffff
+#define TX_DONE_CNT_CLR_SFT 17
+#define TX_DONE_CNT_CLR_HI 17
+#define TX_DONE_CNT_CLR_SZ 1
+#define TX_SET_CNT_CLR_MSK 0x00040000
+#define TX_SET_CNT_CLR_I_MSK 0xfffbffff
+#define TX_SET_CNT_CLR_SFT 18
+#define TX_SET_CNT_CLR_HI 18
+#define TX_SET_CNT_CLR_SZ 1
+#define DAT_MODE_OFF_MSK 0x00080000
+#define DAT_MODE_OFF_I_MSK 0xfff7ffff
+#define DAT_MODE_OFF_SFT 19
+#define DAT_MODE_OFF_HI 19
+#define DAT_MODE_OFF_SZ 1
+#define TX_FIFO_RESIDUE_MSK 0x00700000
+#define TX_FIFO_RESIDUE_I_MSK 0xff8fffff
+#define TX_FIFO_RESIDUE_SFT 20
+#define TX_FIFO_RESIDUE_HI 22
+#define TX_FIFO_RESIDUE_SZ 3
+#define RX_FIFO_RESIDUE_MSK 0x07000000
+#define RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
+#define RX_FIFO_RESIDUE_SFT 24
+#define RX_FIFO_RESIDUE_HI 26
+#define RX_FIFO_RESIDUE_SZ 3
+#define RX_RDY_MSK 0x00000001
+#define RX_RDY_I_MSK 0xfffffffe
+#define RX_RDY_SFT 0
+#define RX_RDY_HI 0
+#define RX_RDY_SZ 1
+#define SDIO_SYS_INT_MSK 0x00000004
+#define SDIO_SYS_INT_I_MSK 0xfffffffb
+#define SDIO_SYS_INT_SFT 2
+#define SDIO_SYS_INT_HI 2
+#define SDIO_SYS_INT_SZ 1
+#define EDCA0_LOWTHOLD_INT_MSK 0x00000008
+#define EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define EDCA0_LOWTHOLD_INT_SFT 3
+#define EDCA0_LOWTHOLD_INT_HI 3
+#define EDCA0_LOWTHOLD_INT_SZ 1
+#define EDCA1_LOWTHOLD_INT_MSK 0x00000010
+#define EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
+#define EDCA1_LOWTHOLD_INT_SFT 4
+#define EDCA1_LOWTHOLD_INT_HI 4
+#define EDCA1_LOWTHOLD_INT_SZ 1
+#define EDCA2_LOWTHOLD_INT_MSK 0x00000020
+#define EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define EDCA2_LOWTHOLD_INT_SFT 5
+#define EDCA2_LOWTHOLD_INT_HI 5
+#define EDCA2_LOWTHOLD_INT_SZ 1
+#define EDCA3_LOWTHOLD_INT_MSK 0x00000040
+#define EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define EDCA3_LOWTHOLD_INT_SFT 6
+#define EDCA3_LOWTHOLD_INT_HI 6
+#define EDCA3_LOWTHOLD_INT_SZ 1
+#define TX_LIMIT_INT_IN_MSK 0x00000080
+#define TX_LIMIT_INT_IN_I_MSK 0xffffff7f
+#define TX_LIMIT_INT_IN_SFT 7
+#define TX_LIMIT_INT_IN_HI 7
+#define TX_LIMIT_INT_IN_SZ 1
+#define SPI_FN1_MSK 0x00007f00
+#define SPI_FN1_I_MSK 0xffff80ff
+#define SPI_FN1_SFT 8
+#define SPI_FN1_HI 14
+#define SPI_FN1_SZ 7
+#define SPI_CLK_EN_INT_MSK 0x00008000
+#define SPI_CLK_EN_INT_I_MSK 0xffff7fff
+#define SPI_CLK_EN_INT_SFT 15
+#define SPI_CLK_EN_INT_HI 15
+#define SPI_CLK_EN_INT_SZ 1
+#define SPI_HOST_MASK_MSK 0x00ff0000
+#define SPI_HOST_MASK_I_MSK 0xff00ffff
+#define SPI_HOST_MASK_SFT 16
+#define SPI_HOST_MASK_HI 23
+#define SPI_HOST_MASK_SZ 8
+#define I2CM_INT_WDONE_MSK 0x00000001
+#define I2CM_INT_WDONE_I_MSK 0xfffffffe
+#define I2CM_INT_WDONE_SFT 0
+#define I2CM_INT_WDONE_HI 0
+#define I2CM_INT_WDONE_SZ 1
+#define I2CM_INT_RDONE_MSK 0x00000002
+#define I2CM_INT_RDONE_I_MSK 0xfffffffd
+#define I2CM_INT_RDONE_SFT 1
+#define I2CM_INT_RDONE_HI 1
+#define I2CM_INT_RDONE_SZ 1
+#define I2CM_IDLE_MSK 0x00000004
+#define I2CM_IDLE_I_MSK 0xfffffffb
+#define I2CM_IDLE_SFT 2
+#define I2CM_IDLE_HI 2
+#define I2CM_IDLE_SZ 1
+#define I2CM_INT_MISMATCH_MSK 0x00000008
+#define I2CM_INT_MISMATCH_I_MSK 0xfffffff7
+#define I2CM_INT_MISMATCH_SFT 3
+#define I2CM_INT_MISMATCH_HI 3
+#define I2CM_INT_MISMATCH_SZ 1
+#define I2CM_PSCL_MSK 0x00003ff0
+#define I2CM_PSCL_I_MSK 0xffffc00f
+#define I2CM_PSCL_SFT 4
+#define I2CM_PSCL_HI 13
+#define I2CM_PSCL_SZ 10
+#define I2CM_MANUAL_MODE_MSK 0x00010000
+#define I2CM_MANUAL_MODE_I_MSK 0xfffeffff
+#define I2CM_MANUAL_MODE_SFT 16
+#define I2CM_MANUAL_MODE_HI 16
+#define I2CM_MANUAL_MODE_SZ 1
+#define I2CM_INT_WDATA_NEED_MSK 0x00020000
+#define I2CM_INT_WDATA_NEED_I_MSK 0xfffdffff
+#define I2CM_INT_WDATA_NEED_SFT 17
+#define I2CM_INT_WDATA_NEED_HI 17
+#define I2CM_INT_WDATA_NEED_SZ 1
+#define I2CM_INT_RDATA_NEED_MSK 0x00040000
+#define I2CM_INT_RDATA_NEED_I_MSK 0xfffbffff
+#define I2CM_INT_RDATA_NEED_SFT 18
+#define I2CM_INT_RDATA_NEED_HI 18
+#define I2CM_INT_RDATA_NEED_SZ 1
+#define I2CM_DEV_A_MSK 0x000003ff
+#define I2CM_DEV_A_I_MSK 0xfffffc00
+#define I2CM_DEV_A_SFT 0
+#define I2CM_DEV_A_HI 9
+#define I2CM_DEV_A_SZ 10
+#define I2CM_DEV_A10B_MSK 0x00004000
+#define I2CM_DEV_A10B_I_MSK 0xffffbfff
+#define I2CM_DEV_A10B_SFT 14
+#define I2CM_DEV_A10B_HI 14
+#define I2CM_DEV_A10B_SZ 1
+#define I2CM_RX_MSK 0x00008000
+#define I2CM_RX_I_MSK 0xffff7fff
+#define I2CM_RX_SFT 15
+#define I2CM_RX_HI 15
+#define I2CM_RX_SZ 1
+#define I2CM_LEN_MSK 0x0000ffff
+#define I2CM_LEN_I_MSK 0xffff0000
+#define I2CM_LEN_SFT 0
+#define I2CM_LEN_HI 15
+#define I2CM_LEN_SZ 16
+#define I2CM_T_LEFT_MSK 0x00070000
+#define I2CM_T_LEFT_I_MSK 0xfff8ffff
+#define I2CM_T_LEFT_SFT 16
+#define I2CM_T_LEFT_HI 18
+#define I2CM_T_LEFT_SZ 3
+#define I2CM_R_GET_MSK 0x07000000
+#define I2CM_R_GET_I_MSK 0xf8ffffff
+#define I2CM_R_GET_SFT 24
+#define I2CM_R_GET_HI 26
+#define I2CM_R_GET_SZ 3
+#define I2CM_WDAT_MSK 0xffffffff
+#define I2CM_WDAT_I_MSK 0x00000000
+#define I2CM_WDAT_SFT 0
+#define I2CM_WDAT_HI 31
+#define I2CM_WDAT_SZ 32
+#define I2CM_RDAT_MSK 0xffffffff
+#define I2CM_RDAT_I_MSK 0x00000000
+#define I2CM_RDAT_SFT 0
+#define I2CM_RDAT_HI 31
+#define I2CM_RDAT_SZ 32
+#define I2CM_SR_LEN_MSK 0x0000ffff
+#define I2CM_SR_LEN_I_MSK 0xffff0000
+#define I2CM_SR_LEN_SFT 0
+#define I2CM_SR_LEN_HI 15
+#define I2CM_SR_LEN_SZ 16
+#define I2CM_SR_RX_MSK 0x00010000
+#define I2CM_SR_RX_I_MSK 0xfffeffff
+#define I2CM_SR_RX_SFT 16
+#define I2CM_SR_RX_HI 16
+#define I2CM_SR_RX_SZ 1
+#define I2CM_REPEAT_START_MSK 0x00020000
+#define I2CM_REPEAT_START_I_MSK 0xfffdffff
+#define I2CM_REPEAT_START_SFT 17
+#define I2CM_REPEAT_START_HI 17
+#define I2CM_REPEAT_START_SZ 1
+#define UART_DATA_MSK 0x000000ff
+#define UART_DATA_I_MSK 0xffffff00
+#define UART_DATA_SFT 0
+#define UART_DATA_HI 7
+#define UART_DATA_SZ 8
+#define DATA_RDY_IE_MSK 0x00000001
+#define DATA_RDY_IE_I_MSK 0xfffffffe
+#define DATA_RDY_IE_SFT 0
+#define DATA_RDY_IE_HI 0
+#define DATA_RDY_IE_SZ 1
+#define THR_EMPTY_IE_MSK 0x00000002
+#define THR_EMPTY_IE_I_MSK 0xfffffffd
+#define THR_EMPTY_IE_SFT 1
+#define THR_EMPTY_IE_HI 1
+#define THR_EMPTY_IE_SZ 1
+#define RX_LINESTS_IE_MSK 0x00000004
+#define RX_LINESTS_IE_I_MSK 0xfffffffb
+#define RX_LINESTS_IE_SFT 2
+#define RX_LINESTS_IE_HI 2
+#define RX_LINESTS_IE_SZ 1
+#define MDM_STS_IE_MSK 0x00000008
+#define MDM_STS_IE_I_MSK 0xfffffff7
+#define MDM_STS_IE_SFT 3
+#define MDM_STS_IE_HI 3
+#define MDM_STS_IE_SZ 1
+#define DMA_RXEND_IE_MSK 0x00000040
+#define DMA_RXEND_IE_I_MSK 0xffffffbf
+#define DMA_RXEND_IE_SFT 6
+#define DMA_RXEND_IE_HI 6
+#define DMA_RXEND_IE_SZ 1
+#define DMA_TXEND_IE_MSK 0x00000080
+#define DMA_TXEND_IE_I_MSK 0xffffff7f
+#define DMA_TXEND_IE_SFT 7
+#define DMA_TXEND_IE_HI 7
+#define DMA_TXEND_IE_SZ 1
+#define FIFO_EN_MSK 0x00000001
+#define FIFO_EN_I_MSK 0xfffffffe
+#define FIFO_EN_SFT 0
+#define FIFO_EN_HI 0
+#define FIFO_EN_SZ 1
+#define RXFIFO_RST_MSK 0x00000002
+#define RXFIFO_RST_I_MSK 0xfffffffd
+#define RXFIFO_RST_SFT 1
+#define RXFIFO_RST_HI 1
+#define RXFIFO_RST_SZ 1
+#define TXFIFO_RST_MSK 0x00000004
+#define TXFIFO_RST_I_MSK 0xfffffffb
+#define TXFIFO_RST_SFT 2
+#define TXFIFO_RST_HI 2
+#define TXFIFO_RST_SZ 1
+#define DMA_MODE_MSK 0x00000008
+#define DMA_MODE_I_MSK 0xfffffff7
+#define DMA_MODE_SFT 3
+#define DMA_MODE_HI 3
+#define DMA_MODE_SZ 1
+#define EN_AUTO_RTS_MSK 0x00000010
+#define EN_AUTO_RTS_I_MSK 0xffffffef
+#define EN_AUTO_RTS_SFT 4
+#define EN_AUTO_RTS_HI 4
+#define EN_AUTO_RTS_SZ 1
+#define EN_AUTO_CTS_MSK 0x00000020
+#define EN_AUTO_CTS_I_MSK 0xffffffdf
+#define EN_AUTO_CTS_SFT 5
+#define EN_AUTO_CTS_HI 5
+#define EN_AUTO_CTS_SZ 1
+#define RXFIFO_TRGLVL_MSK 0x000000c0
+#define RXFIFO_TRGLVL_I_MSK 0xffffff3f
+#define RXFIFO_TRGLVL_SFT 6
+#define RXFIFO_TRGLVL_HI 7
+#define RXFIFO_TRGLVL_SZ 2
+#define WORD_LEN_MSK 0x00000003
+#define WORD_LEN_I_MSK 0xfffffffc
+#define WORD_LEN_SFT 0
+#define WORD_LEN_HI 1
+#define WORD_LEN_SZ 2
+#define STOP_BIT_MSK 0x00000004
+#define STOP_BIT_I_MSK 0xfffffffb
+#define STOP_BIT_SFT 2
+#define STOP_BIT_HI 2
+#define STOP_BIT_SZ 1
+#define PARITY_EN_MSK 0x00000008
+#define PARITY_EN_I_MSK 0xfffffff7
+#define PARITY_EN_SFT 3
+#define PARITY_EN_HI 3
+#define PARITY_EN_SZ 1
+#define EVEN_PARITY_MSK 0x00000010
+#define EVEN_PARITY_I_MSK 0xffffffef
+#define EVEN_PARITY_SFT 4
+#define EVEN_PARITY_HI 4
+#define EVEN_PARITY_SZ 1
+#define FORCE_PARITY_MSK 0x00000020
+#define FORCE_PARITY_I_MSK 0xffffffdf
+#define FORCE_PARITY_SFT 5
+#define FORCE_PARITY_HI 5
+#define FORCE_PARITY_SZ 1
+#define SET_BREAK_MSK 0x00000040
+#define SET_BREAK_I_MSK 0xffffffbf
+#define SET_BREAK_SFT 6
+#define SET_BREAK_HI 6
+#define SET_BREAK_SZ 1
+#define DLAB_MSK 0x00000080
+#define DLAB_I_MSK 0xffffff7f
+#define DLAB_SFT 7
+#define DLAB_HI 7
+#define DLAB_SZ 1
+#define DTR_MSK 0x00000001
+#define DTR_I_MSK 0xfffffffe
+#define DTR_SFT 0
+#define DTR_HI 0
+#define DTR_SZ 1
+#define RTS_MSK 0x00000002
+#define RTS_I_MSK 0xfffffffd
+#define RTS_SFT 1
+#define RTS_HI 1
+#define RTS_SZ 1
+#define OUT_1_MSK 0x00000004
+#define OUT_1_I_MSK 0xfffffffb
+#define OUT_1_SFT 2
+#define OUT_1_HI 2
+#define OUT_1_SZ 1
+#define OUT_2_MSK 0x00000008
+#define OUT_2_I_MSK 0xfffffff7
+#define OUT_2_SFT 3
+#define OUT_2_HI 3
+#define OUT_2_SZ 1
+#define LOOP_BACK_MSK 0x00000010
+#define LOOP_BACK_I_MSK 0xffffffef
+#define LOOP_BACK_SFT 4
+#define LOOP_BACK_HI 4
+#define LOOP_BACK_SZ 1
+#define DATA_RDY_MSK 0x00000001
+#define DATA_RDY_I_MSK 0xfffffffe
+#define DATA_RDY_SFT 0
+#define DATA_RDY_HI 0
+#define DATA_RDY_SZ 1
+#define OVERRUN_ERR_MSK 0x00000002
+#define OVERRUN_ERR_I_MSK 0xfffffffd
+#define OVERRUN_ERR_SFT 1
+#define OVERRUN_ERR_HI 1
+#define OVERRUN_ERR_SZ 1
+#define PARITY_ERR_MSK 0x00000004
+#define PARITY_ERR_I_MSK 0xfffffffb
+#define PARITY_ERR_SFT 2
+#define PARITY_ERR_HI 2
+#define PARITY_ERR_SZ 1
+#define FRAMING_ERR_MSK 0x00000008
+#define FRAMING_ERR_I_MSK 0xfffffff7
+#define FRAMING_ERR_SFT 3
+#define FRAMING_ERR_HI 3
+#define FRAMING_ERR_SZ 1
+#define BREAK_INT_MSK 0x00000010
+#define BREAK_INT_I_MSK 0xffffffef
+#define BREAK_INT_SFT 4
+#define BREAK_INT_HI 4
+#define BREAK_INT_SZ 1
+#define THR_EMPTY_MSK 0x00000020
+#define THR_EMPTY_I_MSK 0xffffffdf
+#define THR_EMPTY_SFT 5
+#define THR_EMPTY_HI 5
+#define THR_EMPTY_SZ 1
+#define TX_EMPTY_MSK 0x00000040
+#define TX_EMPTY_I_MSK 0xffffffbf
+#define TX_EMPTY_SFT 6
+#define TX_EMPTY_HI 6
+#define TX_EMPTY_SZ 1
+#define FIFODATA_ERR_MSK 0x00000080
+#define FIFODATA_ERR_I_MSK 0xffffff7f
+#define FIFODATA_ERR_SFT 7
+#define FIFODATA_ERR_HI 7
+#define FIFODATA_ERR_SZ 1
+#define DELTA_CTS_MSK 0x00000001
+#define DELTA_CTS_I_MSK 0xfffffffe
+#define DELTA_CTS_SFT 0
+#define DELTA_CTS_HI 0
+#define DELTA_CTS_SZ 1
+#define DELTA_DSR_MSK 0x00000002
+#define DELTA_DSR_I_MSK 0xfffffffd
+#define DELTA_DSR_SFT 1
+#define DELTA_DSR_HI 1
+#define DELTA_DSR_SZ 1
+#define TRAILEDGE_RI_MSK 0x00000004
+#define TRAILEDGE_RI_I_MSK 0xfffffffb
+#define TRAILEDGE_RI_SFT 2
+#define TRAILEDGE_RI_HI 2
+#define TRAILEDGE_RI_SZ 1
+#define DELTA_CD_MSK 0x00000008
+#define DELTA_CD_I_MSK 0xfffffff7
+#define DELTA_CD_SFT 3
+#define DELTA_CD_HI 3
+#define DELTA_CD_SZ 1
+#define CTS_MSK 0x00000010
+#define CTS_I_MSK 0xffffffef
+#define CTS_SFT 4
+#define CTS_HI 4
+#define CTS_SZ 1
+#define DSR_MSK 0x00000020
+#define DSR_I_MSK 0xffffffdf
+#define DSR_SFT 5
+#define DSR_HI 5
+#define DSR_SZ 1
+#define RI_MSK 0x00000040
+#define RI_I_MSK 0xffffffbf
+#define RI_SFT 6
+#define RI_HI 6
+#define RI_SZ 1
+#define CD_MSK 0x00000080
+#define CD_I_MSK 0xffffff7f
+#define CD_SFT 7
+#define CD_HI 7
+#define CD_SZ 1
+#define BRDC_DIV_MSK 0x0000ffff
+#define BRDC_DIV_I_MSK 0xffff0000
+#define BRDC_DIV_SFT 0
+#define BRDC_DIV_HI 15
+#define BRDC_DIV_SZ 16
+#define RTHR_L_MSK 0x0000000f
+#define RTHR_L_I_MSK 0xfffffff0
+#define RTHR_L_SFT 0
+#define RTHR_L_HI 3
+#define RTHR_L_SZ 4
+#define RTHR_H_MSK 0x000000f0
+#define RTHR_H_I_MSK 0xffffff0f
+#define RTHR_H_SFT 4
+#define RTHR_H_HI 7
+#define RTHR_H_SZ 4
+#define INT_IDCODE_MSK 0x0000000f
+#define INT_IDCODE_I_MSK 0xfffffff0
+#define INT_IDCODE_SFT 0
+#define INT_IDCODE_HI 3
+#define INT_IDCODE_SZ 4
+#define FIFOS_ENABLED_MSK 0x000000c0
+#define FIFOS_ENABLED_I_MSK 0xffffff3f
+#define FIFOS_ENABLED_SFT 6
+#define FIFOS_ENABLED_HI 7
+#define FIFOS_ENABLED_SZ 2
+#define DAT_UART_DATA_MSK 0x000000ff
+#define DAT_UART_DATA_I_MSK 0xffffff00
+#define DAT_UART_DATA_SFT 0
+#define DAT_UART_DATA_HI 7
+#define DAT_UART_DATA_SZ 8
+#define DAT_DATA_RDY_IE_MSK 0x00000001
+#define DAT_DATA_RDY_IE_I_MSK 0xfffffffe
+#define DAT_DATA_RDY_IE_SFT 0
+#define DAT_DATA_RDY_IE_HI 0
+#define DAT_DATA_RDY_IE_SZ 1
+#define DAT_THR_EMPTY_IE_MSK 0x00000002
+#define DAT_THR_EMPTY_IE_I_MSK 0xfffffffd
+#define DAT_THR_EMPTY_IE_SFT 1
+#define DAT_THR_EMPTY_IE_HI 1
+#define DAT_THR_EMPTY_IE_SZ 1
+#define DAT_RX_LINESTS_IE_MSK 0x00000004
+#define DAT_RX_LINESTS_IE_I_MSK 0xfffffffb
+#define DAT_RX_LINESTS_IE_SFT 2
+#define DAT_RX_LINESTS_IE_HI 2
+#define DAT_RX_LINESTS_IE_SZ 1
+#define DAT_MDM_STS_IE_MSK 0x00000008
+#define DAT_MDM_STS_IE_I_MSK 0xfffffff7
+#define DAT_MDM_STS_IE_SFT 3
+#define DAT_MDM_STS_IE_HI 3
+#define DAT_MDM_STS_IE_SZ 1
+#define DAT_DMA_RXEND_IE_MSK 0x00000040
+#define DAT_DMA_RXEND_IE_I_MSK 0xffffffbf
+#define DAT_DMA_RXEND_IE_SFT 6
+#define DAT_DMA_RXEND_IE_HI 6
+#define DAT_DMA_RXEND_IE_SZ 1
+#define DAT_DMA_TXEND_IE_MSK 0x00000080
+#define DAT_DMA_TXEND_IE_I_MSK 0xffffff7f
+#define DAT_DMA_TXEND_IE_SFT 7
+#define DAT_DMA_TXEND_IE_HI 7
+#define DAT_DMA_TXEND_IE_SZ 1
+#define DAT_FIFO_EN_MSK 0x00000001
+#define DAT_FIFO_EN_I_MSK 0xfffffffe
+#define DAT_FIFO_EN_SFT 0
+#define DAT_FIFO_EN_HI 0
+#define DAT_FIFO_EN_SZ 1
+#define DAT_RXFIFO_RST_MSK 0x00000002
+#define DAT_RXFIFO_RST_I_MSK 0xfffffffd
+#define DAT_RXFIFO_RST_SFT 1
+#define DAT_RXFIFO_RST_HI 1
+#define DAT_RXFIFO_RST_SZ 1
+#define DAT_TXFIFO_RST_MSK 0x00000004
+#define DAT_TXFIFO_RST_I_MSK 0xfffffffb
+#define DAT_TXFIFO_RST_SFT 2
+#define DAT_TXFIFO_RST_HI 2
+#define DAT_TXFIFO_RST_SZ 1
+#define DAT_DMA_MODE_MSK 0x00000008
+#define DAT_DMA_MODE_I_MSK 0xfffffff7
+#define DAT_DMA_MODE_SFT 3
+#define DAT_DMA_MODE_HI 3
+#define DAT_DMA_MODE_SZ 1
+#define DAT_EN_AUTO_RTS_MSK 0x00000010
+#define DAT_EN_AUTO_RTS_I_MSK 0xffffffef
+#define DAT_EN_AUTO_RTS_SFT 4
+#define DAT_EN_AUTO_RTS_HI 4
+#define DAT_EN_AUTO_RTS_SZ 1
+#define DAT_EN_AUTO_CTS_MSK 0x00000020
+#define DAT_EN_AUTO_CTS_I_MSK 0xffffffdf
+#define DAT_EN_AUTO_CTS_SFT 5
+#define DAT_EN_AUTO_CTS_HI 5
+#define DAT_EN_AUTO_CTS_SZ 1
+#define DAT_RXFIFO_TRGLVL_MSK 0x000000c0
+#define DAT_RXFIFO_TRGLVL_I_MSK 0xffffff3f
+#define DAT_RXFIFO_TRGLVL_SFT 6
+#define DAT_RXFIFO_TRGLVL_HI 7
+#define DAT_RXFIFO_TRGLVL_SZ 2
+#define DAT_WORD_LEN_MSK 0x00000003
+#define DAT_WORD_LEN_I_MSK 0xfffffffc
+#define DAT_WORD_LEN_SFT 0
+#define DAT_WORD_LEN_HI 1
+#define DAT_WORD_LEN_SZ 2
+#define DAT_STOP_BIT_MSK 0x00000004
+#define DAT_STOP_BIT_I_MSK 0xfffffffb
+#define DAT_STOP_BIT_SFT 2
+#define DAT_STOP_BIT_HI 2
+#define DAT_STOP_BIT_SZ 1
+#define DAT_PARITY_EN_MSK 0x00000008
+#define DAT_PARITY_EN_I_MSK 0xfffffff7
+#define DAT_PARITY_EN_SFT 3
+#define DAT_PARITY_EN_HI 3
+#define DAT_PARITY_EN_SZ 1
+#define DAT_EVEN_PARITY_MSK 0x00000010
+#define DAT_EVEN_PARITY_I_MSK 0xffffffef
+#define DAT_EVEN_PARITY_SFT 4
+#define DAT_EVEN_PARITY_HI 4
+#define DAT_EVEN_PARITY_SZ 1
+#define DAT_FORCE_PARITY_MSK 0x00000020
+#define DAT_FORCE_PARITY_I_MSK 0xffffffdf
+#define DAT_FORCE_PARITY_SFT 5
+#define DAT_FORCE_PARITY_HI 5
+#define DAT_FORCE_PARITY_SZ 1
+#define DAT_SET_BREAK_MSK 0x00000040
+#define DAT_SET_BREAK_I_MSK 0xffffffbf
+#define DAT_SET_BREAK_SFT 6
+#define DAT_SET_BREAK_HI 6
+#define DAT_SET_BREAK_SZ 1
+#define DAT_DLAB_MSK 0x00000080
+#define DAT_DLAB_I_MSK 0xffffff7f
+#define DAT_DLAB_SFT 7
+#define DAT_DLAB_HI 7
+#define DAT_DLAB_SZ 1
+#define DAT_DTR_MSK 0x00000001
+#define DAT_DTR_I_MSK 0xfffffffe
+#define DAT_DTR_SFT 0
+#define DAT_DTR_HI 0
+#define DAT_DTR_SZ 1
+#define DAT_RTS_MSK 0x00000002
+#define DAT_RTS_I_MSK 0xfffffffd
+#define DAT_RTS_SFT 1
+#define DAT_RTS_HI 1
+#define DAT_RTS_SZ 1
+#define DAT_OUT_1_MSK 0x00000004
+#define DAT_OUT_1_I_MSK 0xfffffffb
+#define DAT_OUT_1_SFT 2
+#define DAT_OUT_1_HI 2
+#define DAT_OUT_1_SZ 1
+#define DAT_OUT_2_MSK 0x00000008
+#define DAT_OUT_2_I_MSK 0xfffffff7
+#define DAT_OUT_2_SFT 3
+#define DAT_OUT_2_HI 3
+#define DAT_OUT_2_SZ 1
+#define DAT_LOOP_BACK_MSK 0x00000010
+#define DAT_LOOP_BACK_I_MSK 0xffffffef
+#define DAT_LOOP_BACK_SFT 4
+#define DAT_LOOP_BACK_HI 4
+#define DAT_LOOP_BACK_SZ 1
+#define DAT_DATA_RDY_MSK 0x00000001
+#define DAT_DATA_RDY_I_MSK 0xfffffffe
+#define DAT_DATA_RDY_SFT 0
+#define DAT_DATA_RDY_HI 0
+#define DAT_DATA_RDY_SZ 1
+#define DAT_OVERRUN_ERR_MSK 0x00000002
+#define DAT_OVERRUN_ERR_I_MSK 0xfffffffd
+#define DAT_OVERRUN_ERR_SFT 1
+#define DAT_OVERRUN_ERR_HI 1
+#define DAT_OVERRUN_ERR_SZ 1
+#define DAT_PARITY_ERR_MSK 0x00000004
+#define DAT_PARITY_ERR_I_MSK 0xfffffffb
+#define DAT_PARITY_ERR_SFT 2
+#define DAT_PARITY_ERR_HI 2
+#define DAT_PARITY_ERR_SZ 1
+#define DAT_FRAMING_ERR_MSK 0x00000008
+#define DAT_FRAMING_ERR_I_MSK 0xfffffff7
+#define DAT_FRAMING_ERR_SFT 3
+#define DAT_FRAMING_ERR_HI 3
+#define DAT_FRAMING_ERR_SZ 1
+#define DAT_BREAK_INT_MSK 0x00000010
+#define DAT_BREAK_INT_I_MSK 0xffffffef
+#define DAT_BREAK_INT_SFT 4
+#define DAT_BREAK_INT_HI 4
+#define DAT_BREAK_INT_SZ 1
+#define DAT_THR_EMPTY_MSK 0x00000020
+#define DAT_THR_EMPTY_I_MSK 0xffffffdf
+#define DAT_THR_EMPTY_SFT 5
+#define DAT_THR_EMPTY_HI 5
+#define DAT_THR_EMPTY_SZ 1
+#define DAT_TX_EMPTY_MSK 0x00000040
+#define DAT_TX_EMPTY_I_MSK 0xffffffbf
+#define DAT_TX_EMPTY_SFT 6
+#define DAT_TX_EMPTY_HI 6
+#define DAT_TX_EMPTY_SZ 1
+#define DAT_FIFODATA_ERR_MSK 0x00000080
+#define DAT_FIFODATA_ERR_I_MSK 0xffffff7f
+#define DAT_FIFODATA_ERR_SFT 7
+#define DAT_FIFODATA_ERR_HI 7
+#define DAT_FIFODATA_ERR_SZ 1
+#define DAT_DELTA_CTS_MSK 0x00000001
+#define DAT_DELTA_CTS_I_MSK 0xfffffffe
+#define DAT_DELTA_CTS_SFT 0
+#define DAT_DELTA_CTS_HI 0
+#define DAT_DELTA_CTS_SZ 1
+#define DAT_DELTA_DSR_MSK 0x00000002
+#define DAT_DELTA_DSR_I_MSK 0xfffffffd
+#define DAT_DELTA_DSR_SFT 1
+#define DAT_DELTA_DSR_HI 1
+#define DAT_DELTA_DSR_SZ 1
+#define DAT_TRAILEDGE_RI_MSK 0x00000004
+#define DAT_TRAILEDGE_RI_I_MSK 0xfffffffb
+#define DAT_TRAILEDGE_RI_SFT 2
+#define DAT_TRAILEDGE_RI_HI 2
+#define DAT_TRAILEDGE_RI_SZ 1
+#define DAT_DELTA_CD_MSK 0x00000008
+#define DAT_DELTA_CD_I_MSK 0xfffffff7
+#define DAT_DELTA_CD_SFT 3
+#define DAT_DELTA_CD_HI 3
+#define DAT_DELTA_CD_SZ 1
+#define DAT_CTS_MSK 0x00000010
+#define DAT_CTS_I_MSK 0xffffffef
+#define DAT_CTS_SFT 4
+#define DAT_CTS_HI 4
+#define DAT_CTS_SZ 1
+#define DAT_DSR_MSK 0x00000020
+#define DAT_DSR_I_MSK 0xffffffdf
+#define DAT_DSR_SFT 5
+#define DAT_DSR_HI 5
+#define DAT_DSR_SZ 1
+#define DAT_RI_MSK 0x00000040
+#define DAT_RI_I_MSK 0xffffffbf
+#define DAT_RI_SFT 6
+#define DAT_RI_HI 6
+#define DAT_RI_SZ 1
+#define DAT_CD_MSK 0x00000080
+#define DAT_CD_I_MSK 0xffffff7f
+#define DAT_CD_SFT 7
+#define DAT_CD_HI 7
+#define DAT_CD_SZ 1
+#define DAT_BRDC_DIV_MSK 0x0000ffff
+#define DAT_BRDC_DIV_I_MSK 0xffff0000
+#define DAT_BRDC_DIV_SFT 0
+#define DAT_BRDC_DIV_HI 15
+#define DAT_BRDC_DIV_SZ 16
+#define DAT_RTHR_L_MSK 0x0000000f
+#define DAT_RTHR_L_I_MSK 0xfffffff0
+#define DAT_RTHR_L_SFT 0
+#define DAT_RTHR_L_HI 3
+#define DAT_RTHR_L_SZ 4
+#define DAT_RTHR_H_MSK 0x000000f0
+#define DAT_RTHR_H_I_MSK 0xffffff0f
+#define DAT_RTHR_H_SFT 4
+#define DAT_RTHR_H_HI 7
+#define DAT_RTHR_H_SZ 4
+#define DAT_INT_IDCODE_MSK 0x0000000f
+#define DAT_INT_IDCODE_I_MSK 0xfffffff0
+#define DAT_INT_IDCODE_SFT 0
+#define DAT_INT_IDCODE_HI 3
+#define DAT_INT_IDCODE_SZ 4
+#define DAT_FIFOS_ENABLED_MSK 0x000000c0
+#define DAT_FIFOS_ENABLED_I_MSK 0xffffff3f
+#define DAT_FIFOS_ENABLED_SFT 6
+#define DAT_FIFOS_ENABLED_HI 7
+#define DAT_FIFOS_ENABLED_SZ 2
+#define MASK_TOP_MSK 0xffffffff
+#define MASK_TOP_I_MSK 0x00000000
+#define MASK_TOP_SFT 0
+#define MASK_TOP_HI 31
+#define MASK_TOP_SZ 32
+#define INT_MODE_MSK 0xffffffff
+#define INT_MODE_I_MSK 0x00000000
+#define INT_MODE_SFT 0
+#define INT_MODE_HI 31
+#define INT_MODE_SZ 32
+#define IRQ_PHY_0_MSK 0x00000001
+#define IRQ_PHY_0_I_MSK 0xfffffffe
+#define IRQ_PHY_0_SFT 0
+#define IRQ_PHY_0_HI 0
+#define IRQ_PHY_0_SZ 1
+#define IRQ_PHY_1_MSK 0x00000002
+#define IRQ_PHY_1_I_MSK 0xfffffffd
+#define IRQ_PHY_1_SFT 1
+#define IRQ_PHY_1_HI 1
+#define IRQ_PHY_1_SZ 1
+#define IRQ_SDIO_MSK 0x00000004
+#define IRQ_SDIO_I_MSK 0xfffffffb
+#define IRQ_SDIO_SFT 2
+#define IRQ_SDIO_HI 2
+#define IRQ_SDIO_SZ 1
+#define IRQ_BEACON_DONE_MSK 0x00000008
+#define IRQ_BEACON_DONE_I_MSK 0xfffffff7
+#define IRQ_BEACON_DONE_SFT 3
+#define IRQ_BEACON_DONE_HI 3
+#define IRQ_BEACON_DONE_SZ 1
+#define IRQ_BEACON_MSK 0x00000010
+#define IRQ_BEACON_I_MSK 0xffffffef
+#define IRQ_BEACON_SFT 4
+#define IRQ_BEACON_HI 4
+#define IRQ_BEACON_SZ 1
+#define IRQ_PRE_BEACON_MSK 0x00000020
+#define IRQ_PRE_BEACON_I_MSK 0xffffffdf
+#define IRQ_PRE_BEACON_SFT 5
+#define IRQ_PRE_BEACON_HI 5
+#define IRQ_PRE_BEACON_SZ 1
+#define IRQ_EDCA0_TX_DONE_MSK 0x00000040
+#define IRQ_EDCA0_TX_DONE_I_MSK 0xffffffbf
+#define IRQ_EDCA0_TX_DONE_SFT 6
+#define IRQ_EDCA0_TX_DONE_HI 6
+#define IRQ_EDCA0_TX_DONE_SZ 1
+#define IRQ_EDCA1_TX_DONE_MSK 0x00000080
+#define IRQ_EDCA1_TX_DONE_I_MSK 0xffffff7f
+#define IRQ_EDCA1_TX_DONE_SFT 7
+#define IRQ_EDCA1_TX_DONE_HI 7
+#define IRQ_EDCA1_TX_DONE_SZ 1
+#define IRQ_EDCA2_TX_DONE_MSK 0x00000100
+#define IRQ_EDCA2_TX_DONE_I_MSK 0xfffffeff
+#define IRQ_EDCA2_TX_DONE_SFT 8
+#define IRQ_EDCA2_TX_DONE_HI 8
+#define IRQ_EDCA2_TX_DONE_SZ 1
+#define IRQ_EDCA3_TX_DONE_MSK 0x00000200
+#define IRQ_EDCA3_TX_DONE_I_MSK 0xfffffdff
+#define IRQ_EDCA3_TX_DONE_SFT 9
+#define IRQ_EDCA3_TX_DONE_HI 9
+#define IRQ_EDCA3_TX_DONE_SZ 1
+#define IRQ_EDCA4_TX_DONE_MSK 0x00000400
+#define IRQ_EDCA4_TX_DONE_I_MSK 0xfffffbff
+#define IRQ_EDCA4_TX_DONE_SFT 10
+#define IRQ_EDCA4_TX_DONE_HI 10
+#define IRQ_EDCA4_TX_DONE_SZ 1
+#define IRQ_BEACON_DTIM_MSK 0x00001000
+#define IRQ_BEACON_DTIM_I_MSK 0xffffefff
+#define IRQ_BEACON_DTIM_SFT 12
+#define IRQ_BEACON_DTIM_HI 12
+#define IRQ_BEACON_DTIM_SZ 1
+#define IRQ_EDCA0_LOWTHOLD_INT_MSK 0x00002000
+#define IRQ_EDCA0_LOWTHOLD_INT_I_MSK 0xffffdfff
+#define IRQ_EDCA0_LOWTHOLD_INT_SFT 13
+#define IRQ_EDCA0_LOWTHOLD_INT_HI 13
+#define IRQ_EDCA0_LOWTHOLD_INT_SZ 1
+#define IRQ_EDCA1_LOWTHOLD_INT_MSK 0x00004000
+#define IRQ_EDCA1_LOWTHOLD_INT_I_MSK 0xffffbfff
+#define IRQ_EDCA1_LOWTHOLD_INT_SFT 14
+#define IRQ_EDCA1_LOWTHOLD_INT_HI 14
+#define IRQ_EDCA1_LOWTHOLD_INT_SZ 1
+#define IRQ_EDCA2_LOWTHOLD_INT_MSK 0x00008000
+#define IRQ_EDCA2_LOWTHOLD_INT_I_MSK 0xffff7fff
+#define IRQ_EDCA2_LOWTHOLD_INT_SFT 15
+#define IRQ_EDCA2_LOWTHOLD_INT_HI 15
+#define IRQ_EDCA2_LOWTHOLD_INT_SZ 1
+#define IRQ_EDCA3_LOWTHOLD_INT_MSK 0x00010000
+#define IRQ_EDCA3_LOWTHOLD_INT_I_MSK 0xfffeffff
+#define IRQ_EDCA3_LOWTHOLD_INT_SFT 16
+#define IRQ_EDCA3_LOWTHOLD_INT_HI 16
+#define IRQ_EDCA3_LOWTHOLD_INT_SZ 1
+#define IRQ_FENCE_HIT_INT_MSK 0x00020000
+#define IRQ_FENCE_HIT_INT_I_MSK 0xfffdffff
+#define IRQ_FENCE_HIT_INT_SFT 17
+#define IRQ_FENCE_HIT_INT_HI 17
+#define IRQ_FENCE_HIT_INT_SZ 1
+#define IRQ_ILL_ADDR_INT_MSK 0x00040000
+#define IRQ_ILL_ADDR_INT_I_MSK 0xfffbffff
+#define IRQ_ILL_ADDR_INT_SFT 18
+#define IRQ_ILL_ADDR_INT_HI 18
+#define IRQ_ILL_ADDR_INT_SZ 1
+#define IRQ_MBOX_MSK 0x00080000
+#define IRQ_MBOX_I_MSK 0xfff7ffff
+#define IRQ_MBOX_SFT 19
+#define IRQ_MBOX_HI 19
+#define IRQ_MBOX_SZ 1
+#define IRQ_US_TIMER0_MSK 0x00100000
+#define IRQ_US_TIMER0_I_MSK 0xffefffff
+#define IRQ_US_TIMER0_SFT 20
+#define IRQ_US_TIMER0_HI 20
+#define IRQ_US_TIMER0_SZ 1
+#define IRQ_US_TIMER1_MSK 0x00200000
+#define IRQ_US_TIMER1_I_MSK 0xffdfffff
+#define IRQ_US_TIMER1_SFT 21
+#define IRQ_US_TIMER1_HI 21
+#define IRQ_US_TIMER1_SZ 1
+#define IRQ_US_TIMER2_MSK 0x00400000
+#define IRQ_US_TIMER2_I_MSK 0xffbfffff
+#define IRQ_US_TIMER2_SFT 22
+#define IRQ_US_TIMER2_HI 22
+#define IRQ_US_TIMER2_SZ 1
+#define IRQ_US_TIMER3_MSK 0x00800000
+#define IRQ_US_TIMER3_I_MSK 0xff7fffff
+#define IRQ_US_TIMER3_SFT 23
+#define IRQ_US_TIMER3_HI 23
+#define IRQ_US_TIMER3_SZ 1
+#define IRQ_MS_TIMER0_MSK 0x01000000
+#define IRQ_MS_TIMER0_I_MSK 0xfeffffff
+#define IRQ_MS_TIMER0_SFT 24
+#define IRQ_MS_TIMER0_HI 24
+#define IRQ_MS_TIMER0_SZ 1
+#define IRQ_MS_TIMER1_MSK 0x02000000
+#define IRQ_MS_TIMER1_I_MSK 0xfdffffff
+#define IRQ_MS_TIMER1_SFT 25
+#define IRQ_MS_TIMER1_HI 25
+#define IRQ_MS_TIMER1_SZ 1
+#define IRQ_MS_TIMER2_MSK 0x04000000
+#define IRQ_MS_TIMER2_I_MSK 0xfbffffff
+#define IRQ_MS_TIMER2_SFT 26
+#define IRQ_MS_TIMER2_HI 26
+#define IRQ_MS_TIMER2_SZ 1
+#define IRQ_MS_TIMER3_MSK 0x08000000
+#define IRQ_MS_TIMER3_I_MSK 0xf7ffffff
+#define IRQ_MS_TIMER3_SFT 27
+#define IRQ_MS_TIMER3_HI 27
+#define IRQ_MS_TIMER3_SZ 1
+#define IRQ_TX_LIMIT_INT_MSK 0x10000000
+#define IRQ_TX_LIMIT_INT_I_MSK 0xefffffff
+#define IRQ_TX_LIMIT_INT_SFT 28
+#define IRQ_TX_LIMIT_INT_HI 28
+#define IRQ_TX_LIMIT_INT_SZ 1
+#define IRQ_DMA0_MSK 0x20000000
+#define IRQ_DMA0_I_MSK 0xdfffffff
+#define IRQ_DMA0_SFT 29
+#define IRQ_DMA0_HI 29
+#define IRQ_DMA0_SZ 1
+#define IRQ_CO_DMA_MSK 0x40000000
+#define IRQ_CO_DMA_I_MSK 0xbfffffff
+#define IRQ_CO_DMA_SFT 30
+#define IRQ_CO_DMA_HI 30
+#define IRQ_CO_DMA_SZ 1
+#define IRQ_PERI_GROUP_MSK 0x80000000
+#define IRQ_PERI_GROUP_I_MSK 0x7fffffff
+#define IRQ_PERI_GROUP_SFT 31
+#define IRQ_PERI_GROUP_HI 31
+#define IRQ_PERI_GROUP_SZ 1
+#define FIQ_STATUS_MSK 0xffffffff
+#define FIQ_STATUS_I_MSK 0x00000000
+#define FIQ_STATUS_SFT 0
+#define FIQ_STATUS_HI 31
+#define FIQ_STATUS_SZ 32
+#define IRQ_RAW_MSK 0xffffffff
+#define IRQ_RAW_I_MSK 0x00000000
+#define IRQ_RAW_SFT 0
+#define IRQ_RAW_HI 31
+#define IRQ_RAW_SZ 32
+#define FIQ_RAW_MSK 0xffffffff
+#define FIQ_RAW_I_MSK 0x00000000
+#define FIQ_RAW_SFT 0
+#define FIQ_RAW_HI 31
+#define FIQ_RAW_SZ 32
+#define INT_PERI_MASK_MSK 0xffffffff
+#define INT_PERI_MASK_I_MSK 0x00000000
+#define INT_PERI_MASK_SFT 0
+#define INT_PERI_MASK_HI 31
+#define INT_PERI_MASK_SZ 32
+#define PERI_RTC_MSK 0x00000001
+#define PERI_RTC_I_MSK 0xfffffffe
+#define PERI_RTC_SFT 0
+#define PERI_RTC_HI 0
+#define PERI_RTC_SZ 1
+#define IRQ_UART0_TX_MSK 0x00000002
+#define IRQ_UART0_TX_I_MSK 0xfffffffd
+#define IRQ_UART0_TX_SFT 1
+#define IRQ_UART0_TX_HI 1
+#define IRQ_UART0_TX_SZ 1
+#define IRQ_UART0_RX_MSK 0x00000004
+#define IRQ_UART0_RX_I_MSK 0xfffffffb
+#define IRQ_UART0_RX_SFT 2
+#define IRQ_UART0_RX_HI 2
+#define IRQ_UART0_RX_SZ 1
+#define PERI_GPI_2_MSK 0x00000008
+#define PERI_GPI_2_I_MSK 0xfffffff7
+#define PERI_GPI_2_SFT 3
+#define PERI_GPI_2_HI 3
+#define PERI_GPI_2_SZ 1
+#define IRQ_SPI_IPC_MSK 0x00000010
+#define IRQ_SPI_IPC_I_MSK 0xffffffef
+#define IRQ_SPI_IPC_SFT 4
+#define IRQ_SPI_IPC_HI 4
+#define IRQ_SPI_IPC_SZ 1
+#define PERI_GPI_1_0_MSK 0x00000060
+#define PERI_GPI_1_0_I_MSK 0xffffff9f
+#define PERI_GPI_1_0_SFT 5
+#define PERI_GPI_1_0_HI 6
+#define PERI_GPI_1_0_SZ 2
+#define SCRT_INT_1_MSK 0x00000080
+#define SCRT_INT_1_I_MSK 0xffffff7f
+#define SCRT_INT_1_SFT 7
+#define SCRT_INT_1_HI 7
+#define SCRT_INT_1_SZ 1
+#define MMU_ALC_ERR_MSK 0x00000100
+#define MMU_ALC_ERR_I_MSK 0xfffffeff
+#define MMU_ALC_ERR_SFT 8
+#define MMU_ALC_ERR_HI 8
+#define MMU_ALC_ERR_SZ 1
+#define MMU_RLS_ERR_MSK 0x00000200
+#define MMU_RLS_ERR_I_MSK 0xfffffdff
+#define MMU_RLS_ERR_SFT 9
+#define MMU_RLS_ERR_HI 9
+#define MMU_RLS_ERR_SZ 1
+#define ID_MNG_INT_1_MSK 0x00000400
+#define ID_MNG_INT_1_I_MSK 0xfffffbff
+#define ID_MNG_INT_1_SFT 10
+#define ID_MNG_INT_1_HI 10
+#define ID_MNG_INT_1_SZ 1
+#define MBOX_INT_1_MSK 0x00000800
+#define MBOX_INT_1_I_MSK 0xfffff7ff
+#define MBOX_INT_1_SFT 11
+#define MBOX_INT_1_HI 11
+#define MBOX_INT_1_SZ 1
+#define MBOX_INT_2_MSK 0x00001000
+#define MBOX_INT_2_I_MSK 0xffffefff
+#define MBOX_INT_2_SFT 12
+#define MBOX_INT_2_HI 12
+#define MBOX_INT_2_SZ 1
+#define MBOX_INT_3_MSK 0x00002000
+#define MBOX_INT_3_I_MSK 0xffffdfff
+#define MBOX_INT_3_SFT 13
+#define MBOX_INT_3_HI 13
+#define MBOX_INT_3_SZ 1
+#define HCI_INT_1_MSK 0x00004000
+#define HCI_INT_1_I_MSK 0xffffbfff
+#define HCI_INT_1_SFT 14
+#define HCI_INT_1_HI 14
+#define HCI_INT_1_SZ 1
+#define UART_RX_TIMEOUT_MSK 0x00008000
+#define UART_RX_TIMEOUT_I_MSK 0xffff7fff
+#define UART_RX_TIMEOUT_SFT 15
+#define UART_RX_TIMEOUT_HI 15
+#define UART_RX_TIMEOUT_SZ 1
+#define UART_MULTI_IRQ_MSK 0x00010000
+#define UART_MULTI_IRQ_I_MSK 0xfffeffff
+#define UART_MULTI_IRQ_SFT 16
+#define UART_MULTI_IRQ_HI 16
+#define UART_MULTI_IRQ_SZ 1
+#define ID_MNG_INT_2_MSK 0x00020000
+#define ID_MNG_INT_2_I_MSK 0xfffdffff
+#define ID_MNG_INT_2_SFT 17
+#define ID_MNG_INT_2_HI 17
+#define ID_MNG_INT_2_SZ 1
+#define DMN_NOHIT_INT_MSK 0x00040000
+#define DMN_NOHIT_INT_I_MSK 0xfffbffff
+#define DMN_NOHIT_INT_SFT 18
+#define DMN_NOHIT_INT_HI 18
+#define DMN_NOHIT_INT_SZ 1
+#define ID_THOLD_RX_MSK 0x00080000
+#define ID_THOLD_RX_I_MSK 0xfff7ffff
+#define ID_THOLD_RX_SFT 19
+#define ID_THOLD_RX_HI 19
+#define ID_THOLD_RX_SZ 1
+#define ID_THOLD_TX_MSK 0x00100000
+#define ID_THOLD_TX_I_MSK 0xffefffff
+#define ID_THOLD_TX_SFT 20
+#define ID_THOLD_TX_HI 20
+#define ID_THOLD_TX_SZ 1
+#define ID_DOUBLE_RLS_MSK 0x00200000
+#define ID_DOUBLE_RLS_I_MSK 0xffdfffff
+#define ID_DOUBLE_RLS_SFT 21
+#define ID_DOUBLE_RLS_HI 21
+#define ID_DOUBLE_RLS_SZ 1
+#define RX_ID_LEN_THOLD_MSK 0x00400000
+#define RX_ID_LEN_THOLD_I_MSK 0xffbfffff
+#define RX_ID_LEN_THOLD_SFT 22
+#define RX_ID_LEN_THOLD_HI 22
+#define RX_ID_LEN_THOLD_SZ 1
+#define TX_ID_LEN_THOLD_MSK 0x00800000
+#define TX_ID_LEN_THOLD_I_MSK 0xff7fffff
+#define TX_ID_LEN_THOLD_SFT 23
+#define TX_ID_LEN_THOLD_HI 23
+#define TX_ID_LEN_THOLD_SZ 1
+#define ALL_ID_LEN_THOLD_MSK 0x01000000
+#define ALL_ID_LEN_THOLD_I_MSK 0xfeffffff
+#define ALL_ID_LEN_THOLD_SFT 24
+#define ALL_ID_LEN_THOLD_HI 24
+#define ALL_ID_LEN_THOLD_SZ 1
+#define DMN_MCU_INT_MSK 0x02000000
+#define DMN_MCU_INT_I_MSK 0xfdffffff
+#define DMN_MCU_INT_SFT 25
+#define DMN_MCU_INT_HI 25
+#define DMN_MCU_INT_SZ 1
+#define IRQ_DAT_UART_TX_MSK 0x04000000
+#define IRQ_DAT_UART_TX_I_MSK 0xfbffffff
+#define IRQ_DAT_UART_TX_SFT 26
+#define IRQ_DAT_UART_TX_HI 26
+#define IRQ_DAT_UART_TX_SZ 1
+#define IRQ_DAT_UART_RX_MSK 0x08000000
+#define IRQ_DAT_UART_RX_I_MSK 0xf7ffffff
+#define IRQ_DAT_UART_RX_SFT 27
+#define IRQ_DAT_UART_RX_HI 27
+#define IRQ_DAT_UART_RX_SZ 1
+#define DAT_UART_RX_TIMEOUT_MSK 0x10000000
+#define DAT_UART_RX_TIMEOUT_I_MSK 0xefffffff
+#define DAT_UART_RX_TIMEOUT_SFT 28
+#define DAT_UART_RX_TIMEOUT_HI 28
+#define DAT_UART_RX_TIMEOUT_SZ 1
+#define DAT_UART_MULTI_IRQ_MSK 0x20000000
+#define DAT_UART_MULTI_IRQ_I_MSK 0xdfffffff
+#define DAT_UART_MULTI_IRQ_SFT 29
+#define DAT_UART_MULTI_IRQ_HI 29
+#define DAT_UART_MULTI_IRQ_SZ 1
+#define ALR_ABT_NOCHG_INT_IRQ_MSK 0x40000000
+#define ALR_ABT_NOCHG_INT_IRQ_I_MSK 0xbfffffff
+#define ALR_ABT_NOCHG_INT_IRQ_SFT 30
+#define ALR_ABT_NOCHG_INT_IRQ_HI 30
+#define ALR_ABT_NOCHG_INT_IRQ_SZ 1
+#define TBLNEQ_MNGPKT_INT_IRQ_MSK 0x80000000
+#define TBLNEQ_MNGPKT_INT_IRQ_I_MSK 0x7fffffff
+#define TBLNEQ_MNGPKT_INT_IRQ_SFT 31
+#define TBLNEQ_MNGPKT_INT_IRQ_HI 31
+#define TBLNEQ_MNGPKT_INT_IRQ_SZ 1
+#define INTR_PERI_RAW_MSK 0xffffffff
+#define INTR_PERI_RAW_I_MSK 0x00000000
+#define INTR_PERI_RAW_SFT 0
+#define INTR_PERI_RAW_HI 31
+#define INTR_PERI_RAW_SZ 32
+#define INTR_GPI00_CFG_MSK 0x00000003
+#define INTR_GPI00_CFG_I_MSK 0xfffffffc
+#define INTR_GPI00_CFG_SFT 0
+#define INTR_GPI00_CFG_HI 1
+#define INTR_GPI00_CFG_SZ 2
+#define INTR_GPI01_CFG_MSK 0x0000000c
+#define INTR_GPI01_CFG_I_MSK 0xfffffff3
+#define INTR_GPI01_CFG_SFT 2
+#define INTR_GPI01_CFG_HI 3
+#define INTR_GPI01_CFG_SZ 2
+#define SYS_RST_INT_MSK 0x00000001
+#define SYS_RST_INT_I_MSK 0xfffffffe
+#define SYS_RST_INT_SFT 0
+#define SYS_RST_INT_HI 0
+#define SYS_RST_INT_SZ 1
+#define SPI_IPC_ADDR_MSK 0xffffffff
+#define SPI_IPC_ADDR_I_MSK 0x00000000
+#define SPI_IPC_ADDR_SFT 0
+#define SPI_IPC_ADDR_HI 31
+#define SPI_IPC_ADDR_SZ 32
+#define SD_MASK_TOP_MSK 0xffffffff
+#define SD_MASK_TOP_I_MSK 0x00000000
+#define SD_MASK_TOP_SFT 0
+#define SD_MASK_TOP_HI 31
+#define SD_MASK_TOP_SZ 32
+#define IRQ_PHY_0_SD_MSK 0x00000001
+#define IRQ_PHY_0_SD_I_MSK 0xfffffffe
+#define IRQ_PHY_0_SD_SFT 0
+#define IRQ_PHY_0_SD_HI 0
+#define IRQ_PHY_0_SD_SZ 1
+#define IRQ_PHY_1_SD_MSK 0x00000002
+#define IRQ_PHY_1_SD_I_MSK 0xfffffffd
+#define IRQ_PHY_1_SD_SFT 1
+#define IRQ_PHY_1_SD_HI 1
+#define IRQ_PHY_1_SD_SZ 1
+#define IRQ_SDIO_SD_MSK 0x00000004
+#define IRQ_SDIO_SD_I_MSK 0xfffffffb
+#define IRQ_SDIO_SD_SFT 2
+#define IRQ_SDIO_SD_HI 2
+#define IRQ_SDIO_SD_SZ 1
+#define IRQ_BEACON_DONE_SD_MSK 0x00000008
+#define IRQ_BEACON_DONE_SD_I_MSK 0xfffffff7
+#define IRQ_BEACON_DONE_SD_SFT 3
+#define IRQ_BEACON_DONE_SD_HI 3
+#define IRQ_BEACON_DONE_SD_SZ 1
+#define IRQ_BEACON_SD_MSK 0x00000010
+#define IRQ_BEACON_SD_I_MSK 0xffffffef
+#define IRQ_BEACON_SD_SFT 4
+#define IRQ_BEACON_SD_HI 4
+#define IRQ_BEACON_SD_SZ 1
+#define IRQ_PRE_BEACON_SD_MSK 0x00000020
+#define IRQ_PRE_BEACON_SD_I_MSK 0xffffffdf
+#define IRQ_PRE_BEACON_SD_SFT 5
+#define IRQ_PRE_BEACON_SD_HI 5
+#define IRQ_PRE_BEACON_SD_SZ 1
+#define IRQ_EDCA0_TX_DONE_SD_MSK 0x00000040
+#define IRQ_EDCA0_TX_DONE_SD_I_MSK 0xffffffbf
+#define IRQ_EDCA0_TX_DONE_SD_SFT 6
+#define IRQ_EDCA0_TX_DONE_SD_HI 6
+#define IRQ_EDCA0_TX_DONE_SD_SZ 1
+#define IRQ_EDCA1_TX_DONE_SD_MSK 0x00000080
+#define IRQ_EDCA1_TX_DONE_SD_I_MSK 0xffffff7f
+#define IRQ_EDCA1_TX_DONE_SD_SFT 7
+#define IRQ_EDCA1_TX_DONE_SD_HI 7
+#define IRQ_EDCA1_TX_DONE_SD_SZ 1
+#define IRQ_EDCA2_TX_DONE_SD_MSK 0x00000100
+#define IRQ_EDCA2_TX_DONE_SD_I_MSK 0xfffffeff
+#define IRQ_EDCA2_TX_DONE_SD_SFT 8
+#define IRQ_EDCA2_TX_DONE_SD_HI 8
+#define IRQ_EDCA2_TX_DONE_SD_SZ 1
+#define IRQ_EDCA3_TX_DONE_SD_MSK 0x00000200
+#define IRQ_EDCA3_TX_DONE_SD_I_MSK 0xfffffdff
+#define IRQ_EDCA3_TX_DONE_SD_SFT 9
+#define IRQ_EDCA3_TX_DONE_SD_HI 9
+#define IRQ_EDCA3_TX_DONE_SD_SZ 1
+#define IRQ_EDCA4_TX_DONE_SD_MSK 0x00000400
+#define IRQ_EDCA4_TX_DONE_SD_I_MSK 0xfffffbff
+#define IRQ_EDCA4_TX_DONE_SD_SFT 10
+#define IRQ_EDCA4_TX_DONE_SD_HI 10
+#define IRQ_EDCA4_TX_DONE_SD_SZ 1
+#define IRQ_BEACON_DTIM_SD_MSK 0x00001000
+#define IRQ_BEACON_DTIM_SD_I_MSK 0xffffefff
+#define IRQ_BEACON_DTIM_SD_SFT 12
+#define IRQ_BEACON_DTIM_SD_HI 12
+#define IRQ_BEACON_DTIM_SD_SZ 1
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_MSK 0x00002000
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_I_MSK 0xffffdfff
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_SFT 13
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_HI 13
+#define IRQ_EDCA0_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_MSK 0x00004000
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_I_MSK 0xffffbfff
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_SFT 14
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_HI 14
+#define IRQ_EDCA1_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_MSK 0x00008000
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_I_MSK 0xffff7fff
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_SFT 15
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_HI 15
+#define IRQ_EDCA2_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_MSK 0x00010000
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_I_MSK 0xfffeffff
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_SFT 16
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_HI 16
+#define IRQ_EDCA3_LOWTHOLD_INT_SD_SZ 1
+#define IRQ_FENCE_HIT_INT_SD_MSK 0x00020000
+#define IRQ_FENCE_HIT_INT_SD_I_MSK 0xfffdffff
+#define IRQ_FENCE_HIT_INT_SD_SFT 17
+#define IRQ_FENCE_HIT_INT_SD_HI 17
+#define IRQ_FENCE_HIT_INT_SD_SZ 1
+#define IRQ_ILL_ADDR_INT_SD_MSK 0x00040000
+#define IRQ_ILL_ADDR_INT_SD_I_MSK 0xfffbffff
+#define IRQ_ILL_ADDR_INT_SD_SFT 18
+#define IRQ_ILL_ADDR_INT_SD_HI 18
+#define IRQ_ILL_ADDR_INT_SD_SZ 1
+#define IRQ_MBOX_SD_MSK 0x00080000
+#define IRQ_MBOX_SD_I_MSK 0xfff7ffff
+#define IRQ_MBOX_SD_SFT 19
+#define IRQ_MBOX_SD_HI 19
+#define IRQ_MBOX_SD_SZ 1
+#define IRQ_US_TIMER0_SD_MSK 0x00100000
+#define IRQ_US_TIMER0_SD_I_MSK 0xffefffff
+#define IRQ_US_TIMER0_SD_SFT 20
+#define IRQ_US_TIMER0_SD_HI 20
+#define IRQ_US_TIMER0_SD_SZ 1
+#define IRQ_US_TIMER1_SD_MSK 0x00200000
+#define IRQ_US_TIMER1_SD_I_MSK 0xffdfffff
+#define IRQ_US_TIMER1_SD_SFT 21
+#define IRQ_US_TIMER1_SD_HI 21
+#define IRQ_US_TIMER1_SD_SZ 1
+#define IRQ_US_TIMER2_SD_MSK 0x00400000
+#define IRQ_US_TIMER2_SD_I_MSK 0xffbfffff
+#define IRQ_US_TIMER2_SD_SFT 22
+#define IRQ_US_TIMER2_SD_HI 22
+#define IRQ_US_TIMER2_SD_SZ 1
+#define IRQ_US_TIMER3_SD_MSK 0x00800000
+#define IRQ_US_TIMER3_SD_I_MSK 0xff7fffff
+#define IRQ_US_TIMER3_SD_SFT 23
+#define IRQ_US_TIMER3_SD_HI 23
+#define IRQ_US_TIMER3_SD_SZ 1
+#define IRQ_MS_TIMER0_SD_MSK 0x01000000
+#define IRQ_MS_TIMER0_SD_I_MSK 0xfeffffff
+#define IRQ_MS_TIMER0_SD_SFT 24
+#define IRQ_MS_TIMER0_SD_HI 24
+#define IRQ_MS_TIMER0_SD_SZ 1
+#define IRQ_MS_TIMER1_SD_MSK 0x02000000
+#define IRQ_MS_TIMER1_SD_I_MSK 0xfdffffff
+#define IRQ_MS_TIMER1_SD_SFT 25
+#define IRQ_MS_TIMER1_SD_HI 25
+#define IRQ_MS_TIMER1_SD_SZ 1
+#define IRQ_MS_TIMER2_SD_MSK 0x04000000
+#define IRQ_MS_TIMER2_SD_I_MSK 0xfbffffff
+#define IRQ_MS_TIMER2_SD_SFT 26
+#define IRQ_MS_TIMER2_SD_HI 26
+#define IRQ_MS_TIMER2_SD_SZ 1
+#define IRQ_MS_TIMER3_SD_MSK 0x08000000
+#define IRQ_MS_TIMER3_SD_I_MSK 0xf7ffffff
+#define IRQ_MS_TIMER3_SD_SFT 27
+#define IRQ_MS_TIMER3_SD_HI 27
+#define IRQ_MS_TIMER3_SD_SZ 1
+#define IRQ_TX_LIMIT_INT_SD_MSK 0x10000000
+#define IRQ_TX_LIMIT_INT_SD_I_MSK 0xefffffff
+#define IRQ_TX_LIMIT_INT_SD_SFT 28
+#define IRQ_TX_LIMIT_INT_SD_HI 28
+#define IRQ_TX_LIMIT_INT_SD_SZ 1
+#define IRQ_DMA0_SD_MSK 0x20000000
+#define IRQ_DMA0_SD_I_MSK 0xdfffffff
+#define IRQ_DMA0_SD_SFT 29
+#define IRQ_DMA0_SD_HI 29
+#define IRQ_DMA0_SD_SZ 1
+#define IRQ_CO_DMA_SD_MSK 0x40000000
+#define IRQ_CO_DMA_SD_I_MSK 0xbfffffff
+#define IRQ_CO_DMA_SD_SFT 30
+#define IRQ_CO_DMA_SD_HI 30
+#define IRQ_CO_DMA_SD_SZ 1
+#define IRQ_PERI_GROUP_SD_MSK 0x80000000
+#define IRQ_PERI_GROUP_SD_I_MSK 0x7fffffff
+#define IRQ_PERI_GROUP_SD_SFT 31
+#define IRQ_PERI_GROUP_SD_HI 31
+#define IRQ_PERI_GROUP_SD_SZ 1
+#define INT_PERI_MASK_SD_MSK 0xffffffff
+#define INT_PERI_MASK_SD_I_MSK 0x00000000
+#define INT_PERI_MASK_SD_SFT 0
+#define INT_PERI_MASK_SD_HI 31
+#define INT_PERI_MASK_SD_SZ 32
+#define PERI_RTC_SD_MSK 0x00000001
+#define PERI_RTC_SD_I_MSK 0xfffffffe
+#define PERI_RTC_SD_SFT 0
+#define PERI_RTC_SD_HI 0
+#define PERI_RTC_SD_SZ 1
+#define IRQ_UART0_TX_SD_MSK 0x00000002
+#define IRQ_UART0_TX_SD_I_MSK 0xfffffffd
+#define IRQ_UART0_TX_SD_SFT 1
+#define IRQ_UART0_TX_SD_HI 1
+#define IRQ_UART0_TX_SD_SZ 1
+#define IRQ_UART0_RX_SD_MSK 0x00000004
+#define IRQ_UART0_RX_SD_I_MSK 0xfffffffb
+#define IRQ_UART0_RX_SD_SFT 2
+#define IRQ_UART0_RX_SD_HI 2
+#define IRQ_UART0_RX_SD_SZ 1
+#define PERI_GPI_SD_2_MSK 0x00000008
+#define PERI_GPI_SD_2_I_MSK 0xfffffff7
+#define PERI_GPI_SD_2_SFT 3
+#define PERI_GPI_SD_2_HI 3
+#define PERI_GPI_SD_2_SZ 1
+#define IRQ_SPI_IPC_SD_MSK 0x00000010
+#define IRQ_SPI_IPC_SD_I_MSK 0xffffffef
+#define IRQ_SPI_IPC_SD_SFT 4
+#define IRQ_SPI_IPC_SD_HI 4
+#define IRQ_SPI_IPC_SD_SZ 1
+#define PERI_GPI_SD_1_0_MSK 0x00000060
+#define PERI_GPI_SD_1_0_I_MSK 0xffffff9f
+#define PERI_GPI_SD_1_0_SFT 5
+#define PERI_GPI_SD_1_0_HI 6
+#define PERI_GPI_SD_1_0_SZ 2
+#define SCRT_INT_1_SD_MSK 0x00000080
+#define SCRT_INT_1_SD_I_MSK 0xffffff7f
+#define SCRT_INT_1_SD_SFT 7
+#define SCRT_INT_1_SD_HI 7
+#define SCRT_INT_1_SD_SZ 1
+#define MMU_ALC_ERR_SD_MSK 0x00000100
+#define MMU_ALC_ERR_SD_I_MSK 0xfffffeff
+#define MMU_ALC_ERR_SD_SFT 8
+#define MMU_ALC_ERR_SD_HI 8
+#define MMU_ALC_ERR_SD_SZ 1
+#define MMU_RLS_ERR_SD_MSK 0x00000200
+#define MMU_RLS_ERR_SD_I_MSK 0xfffffdff
+#define MMU_RLS_ERR_SD_SFT 9
+#define MMU_RLS_ERR_SD_HI 9
+#define MMU_RLS_ERR_SD_SZ 1
+#define ID_MNG_INT_1_SD_MSK 0x00000400
+#define ID_MNG_INT_1_SD_I_MSK 0xfffffbff
+#define ID_MNG_INT_1_SD_SFT 10
+#define ID_MNG_INT_1_SD_HI 10
+#define ID_MNG_INT_1_SD_SZ 1
+#define MBOX_INT_1_SD_MSK 0x00000800
+#define MBOX_INT_1_SD_I_MSK 0xfffff7ff
+#define MBOX_INT_1_SD_SFT 11
+#define MBOX_INT_1_SD_HI 11
+#define MBOX_INT_1_SD_SZ 1
+#define MBOX_INT_2_SD_MSK 0x00001000
+#define MBOX_INT_2_SD_I_MSK 0xffffefff
+#define MBOX_INT_2_SD_SFT 12
+#define MBOX_INT_2_SD_HI 12
+#define MBOX_INT_2_SD_SZ 1
+#define MBOX_INT_3_SD_MSK 0x00002000
+#define MBOX_INT_3_SD_I_MSK 0xffffdfff
+#define MBOX_INT_3_SD_SFT 13
+#define MBOX_INT_3_SD_HI 13
+#define MBOX_INT_3_SD_SZ 1
+#define HCI_INT_1_SD_MSK 0x00004000
+#define HCI_INT_1_SD_I_MSK 0xffffbfff
+#define HCI_INT_1_SD_SFT 14
+#define HCI_INT_1_SD_HI 14
+#define HCI_INT_1_SD_SZ 1
+#define UART_RX_TIMEOUT_SD_MSK 0x00008000
+#define UART_RX_TIMEOUT_SD_I_MSK 0xffff7fff
+#define UART_RX_TIMEOUT_SD_SFT 15
+#define UART_RX_TIMEOUT_SD_HI 15
+#define UART_RX_TIMEOUT_SD_SZ 1
+#define UART_MULTI_IRQ_SD_MSK 0x00010000
+#define UART_MULTI_IRQ_SD_I_MSK 0xfffeffff
+#define UART_MULTI_IRQ_SD_SFT 16
+#define UART_MULTI_IRQ_SD_HI 16
+#define UART_MULTI_IRQ_SD_SZ 1
+#define ID_MNG_INT_2_SD_MSK 0x00020000
+#define ID_MNG_INT_2_SD_I_MSK 0xfffdffff
+#define ID_MNG_INT_2_SD_SFT 17
+#define ID_MNG_INT_2_SD_HI 17
+#define ID_MNG_INT_2_SD_SZ 1
+#define DMN_NOHIT_INT_SD_MSK 0x00040000
+#define DMN_NOHIT_INT_SD_I_MSK 0xfffbffff
+#define DMN_NOHIT_INT_SD_SFT 18
+#define DMN_NOHIT_INT_SD_HI 18
+#define DMN_NOHIT_INT_SD_SZ 1
+#define ID_THOLD_RX_SD_MSK 0x00080000
+#define ID_THOLD_RX_SD_I_MSK 0xfff7ffff
+#define ID_THOLD_RX_SD_SFT 19
+#define ID_THOLD_RX_SD_HI 19
+#define ID_THOLD_RX_SD_SZ 1
+#define ID_THOLD_TX_SD_MSK 0x00100000
+#define ID_THOLD_TX_SD_I_MSK 0xffefffff
+#define ID_THOLD_TX_SD_SFT 20
+#define ID_THOLD_TX_SD_HI 20
+#define ID_THOLD_TX_SD_SZ 1
+#define ID_DOUBLE_RLS_SD_MSK 0x00200000
+#define ID_DOUBLE_RLS_SD_I_MSK 0xffdfffff
+#define ID_DOUBLE_RLS_SD_SFT 21
+#define ID_DOUBLE_RLS_SD_HI 21
+#define ID_DOUBLE_RLS_SD_SZ 1
+#define RX_ID_LEN_THOLD_SD_MSK 0x00400000
+#define RX_ID_LEN_THOLD_SD_I_MSK 0xffbfffff
+#define RX_ID_LEN_THOLD_SD_SFT 22
+#define RX_ID_LEN_THOLD_SD_HI 22
+#define RX_ID_LEN_THOLD_SD_SZ 1
+#define TX_ID_LEN_THOLD_SD_MSK 0x00800000
+#define TX_ID_LEN_THOLD_SD_I_MSK 0xff7fffff
+#define TX_ID_LEN_THOLD_SD_SFT 23
+#define TX_ID_LEN_THOLD_SD_HI 23
+#define TX_ID_LEN_THOLD_SD_SZ 1
+#define ALL_ID_LEN_THOLD_SD_MSK 0x01000000
+#define ALL_ID_LEN_THOLD_SD_I_MSK 0xfeffffff
+#define ALL_ID_LEN_THOLD_SD_SFT 24
+#define ALL_ID_LEN_THOLD_SD_HI 24
+#define ALL_ID_LEN_THOLD_SD_SZ 1
+#define DMN_MCU_INT_SD_MSK 0x02000000
+#define DMN_MCU_INT_SD_I_MSK 0xfdffffff
+#define DMN_MCU_INT_SD_SFT 25
+#define DMN_MCU_INT_SD_HI 25
+#define DMN_MCU_INT_SD_SZ 1
+#define IRQ_DAT_UART_TX_SD_MSK 0x04000000
+#define IRQ_DAT_UART_TX_SD_I_MSK 0xfbffffff
+#define IRQ_DAT_UART_TX_SD_SFT 26
+#define IRQ_DAT_UART_TX_SD_HI 26
+#define IRQ_DAT_UART_TX_SD_SZ 1
+#define IRQ_DAT_UART_RX_SD_MSK 0x08000000
+#define IRQ_DAT_UART_RX_SD_I_MSK 0xf7ffffff
+#define IRQ_DAT_UART_RX_SD_SFT 27
+#define IRQ_DAT_UART_RX_SD_HI 27
+#define IRQ_DAT_UART_RX_SD_SZ 1
+#define DAT_UART_RX_TIMEOUT_SD_MSK 0x10000000
+#define DAT_UART_RX_TIMEOUT_SD_I_MSK 0xefffffff
+#define DAT_UART_RX_TIMEOUT_SD_SFT 28
+#define DAT_UART_RX_TIMEOUT_SD_HI 28
+#define DAT_UART_RX_TIMEOUT_SD_SZ 1
+#define DAT_UART_MULTI_IRQ_SD_MSK 0x20000000
+#define DAT_UART_MULTI_IRQ_SD_I_MSK 0xdfffffff
+#define DAT_UART_MULTI_IRQ_SD_SFT 29
+#define DAT_UART_MULTI_IRQ_SD_HI 29
+#define DAT_UART_MULTI_IRQ_SD_SZ 1
+#define ALR_ABT_NOCHG_INT_IRQ_SD_MSK 0x40000000
+#define ALR_ABT_NOCHG_INT_IRQ_SD_I_MSK 0xbfffffff
+#define ALR_ABT_NOCHG_INT_IRQ_SD_SFT 30
+#define ALR_ABT_NOCHG_INT_IRQ_SD_HI 30
+#define ALR_ABT_NOCHG_INT_IRQ_SD_SZ 1
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_MSK 0x80000000
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_I_MSK 0x7fffffff
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_SFT 31
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_HI 31
+#define TBLNEQ_MNGPKT_INT_IRQ_SD_SZ 1
+#define DBG_SPI_MODE_MSK 0xffffffff
+#define DBG_SPI_MODE_I_MSK 0x00000000
+#define DBG_SPI_MODE_SFT 0
+#define DBG_SPI_MODE_HI 31
+#define DBG_SPI_MODE_SZ 32
+#define DBG_RX_QUOTA_MSK 0x0000ffff
+#define DBG_RX_QUOTA_I_MSK 0xffff0000
+#define DBG_RX_QUOTA_SFT 0
+#define DBG_RX_QUOTA_HI 15
+#define DBG_RX_QUOTA_SZ 16
+#define DBG_CONDI_NUM_MSK 0x000000ff
+#define DBG_CONDI_NUM_I_MSK 0xffffff00
+#define DBG_CONDI_NUM_SFT 0
+#define DBG_CONDI_NUM_HI 7
+#define DBG_CONDI_NUM_SZ 8
+#define DBG_HOST_PATH_MSK 0x00000001
+#define DBG_HOST_PATH_I_MSK 0xfffffffe
+#define DBG_HOST_PATH_SFT 0
+#define DBG_HOST_PATH_HI 0
+#define DBG_HOST_PATH_SZ 1
+#define DBG_TX_SEG_MSK 0xffffffff
+#define DBG_TX_SEG_I_MSK 0x00000000
+#define DBG_TX_SEG_SFT 0
+#define DBG_TX_SEG_HI 31
+#define DBG_TX_SEG_SZ 32
+#define DBG_BRST_MODE_MSK 0x00000001
+#define DBG_BRST_MODE_I_MSK 0xfffffffe
+#define DBG_BRST_MODE_SFT 0
+#define DBG_BRST_MODE_HI 0
+#define DBG_BRST_MODE_SZ 1
+#define DBG_CLK_WIDTH_MSK 0x0000ffff
+#define DBG_CLK_WIDTH_I_MSK 0xffff0000
+#define DBG_CLK_WIDTH_SFT 0
+#define DBG_CLK_WIDTH_HI 15
+#define DBG_CLK_WIDTH_SZ 16
+#define DBG_CSN_INTER_MSK 0xffff0000
+#define DBG_CSN_INTER_I_MSK 0x0000ffff
+#define DBG_CSN_INTER_SFT 16
+#define DBG_CSN_INTER_HI 31
+#define DBG_CSN_INTER_SZ 16
+#define DBG_BACK_DLY_MSK 0x0000ffff
+#define DBG_BACK_DLY_I_MSK 0xffff0000
+#define DBG_BACK_DLY_SFT 0
+#define DBG_BACK_DLY_HI 15
+#define DBG_BACK_DLY_SZ 16
+#define DBG_FRONT_DLY_MSK 0xffff0000
+#define DBG_FRONT_DLY_I_MSK 0x0000ffff
+#define DBG_FRONT_DLY_SFT 16
+#define DBG_FRONT_DLY_HI 31
+#define DBG_FRONT_DLY_SZ 16
+#define DBG_RX_FIFO_FAIL_MSK 0x00000002
+#define DBG_RX_FIFO_FAIL_I_MSK 0xfffffffd
+#define DBG_RX_FIFO_FAIL_SFT 1
+#define DBG_RX_FIFO_FAIL_HI 1
+#define DBG_RX_FIFO_FAIL_SZ 1
+#define DBG_RX_HOST_FAIL_MSK 0x00000004
+#define DBG_RX_HOST_FAIL_I_MSK 0xfffffffb
+#define DBG_RX_HOST_FAIL_SFT 2
+#define DBG_RX_HOST_FAIL_HI 2
+#define DBG_RX_HOST_FAIL_SZ 1
+#define DBG_TX_FIFO_FAIL_MSK 0x00000008
+#define DBG_TX_FIFO_FAIL_I_MSK 0xfffffff7
+#define DBG_TX_FIFO_FAIL_SFT 3
+#define DBG_TX_FIFO_FAIL_HI 3
+#define DBG_TX_FIFO_FAIL_SZ 1
+#define DBG_TX_HOST_FAIL_MSK 0x00000010
+#define DBG_TX_HOST_FAIL_I_MSK 0xffffffef
+#define DBG_TX_HOST_FAIL_SFT 4
+#define DBG_TX_HOST_FAIL_HI 4
+#define DBG_TX_HOST_FAIL_SZ 1
+#define DBG_SPI_DOUBLE_ALLOC_MSK 0x00000020
+#define DBG_SPI_DOUBLE_ALLOC_I_MSK 0xffffffdf
+#define DBG_SPI_DOUBLE_ALLOC_SFT 5
+#define DBG_SPI_DOUBLE_ALLOC_HI 5
+#define DBG_SPI_DOUBLE_ALLOC_SZ 1
+#define DBG_SPI_TX_NO_ALLOC_MSK 0x00000040
+#define DBG_SPI_TX_NO_ALLOC_I_MSK 0xffffffbf
+#define DBG_SPI_TX_NO_ALLOC_SFT 6
+#define DBG_SPI_TX_NO_ALLOC_HI 6
+#define DBG_SPI_TX_NO_ALLOC_SZ 1
+#define DBG_RDATA_RDY_MSK 0x00000080
+#define DBG_RDATA_RDY_I_MSK 0xffffff7f
+#define DBG_RDATA_RDY_SFT 7
+#define DBG_RDATA_RDY_HI 7
+#define DBG_RDATA_RDY_SZ 1
+#define DBG_SPI_ALLOC_STATUS_MSK 0x00000100
+#define DBG_SPI_ALLOC_STATUS_I_MSK 0xfffffeff
+#define DBG_SPI_ALLOC_STATUS_SFT 8
+#define DBG_SPI_ALLOC_STATUS_HI 8
+#define DBG_SPI_ALLOC_STATUS_SZ 1
+#define DBG_SPI_DBG_WR_FIFO_FULL_MSK 0x00000200
+#define DBG_SPI_DBG_WR_FIFO_FULL_I_MSK 0xfffffdff
+#define DBG_SPI_DBG_WR_FIFO_FULL_SFT 9
+#define DBG_SPI_DBG_WR_FIFO_FULL_HI 9
+#define DBG_SPI_DBG_WR_FIFO_FULL_SZ 1
+#define DBG_RX_LEN_MSK 0xffff0000
+#define DBG_RX_LEN_I_MSK 0x0000ffff
+#define DBG_RX_LEN_SFT 16
+#define DBG_RX_LEN_HI 31
+#define DBG_RX_LEN_SZ 16
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_MSK 0x00000007
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_I_MSK 0xfffffff8
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SFT 0
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_HI 2
+#define DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS_SZ 3
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_MSK 0x00000100
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_I_MSK 0xfffffeff
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SFT 8
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_HI 8
+#define DBG_SPI_HOST_TX_ALLOC_PKBUF_SZ 1
+#define DBG_SPI_TX_ALLOC_SIZE_MSK 0x000000ff
+#define DBG_SPI_TX_ALLOC_SIZE_I_MSK 0xffffff00
+#define DBG_SPI_TX_ALLOC_SIZE_SFT 0
+#define DBG_SPI_TX_ALLOC_SIZE_HI 7
+#define DBG_SPI_TX_ALLOC_SIZE_SZ 8
+#define DBG_RD_DAT_CNT_MSK 0x0000ffff
+#define DBG_RD_DAT_CNT_I_MSK 0xffff0000
+#define DBG_RD_DAT_CNT_SFT 0
+#define DBG_RD_DAT_CNT_HI 15
+#define DBG_RD_DAT_CNT_SZ 16
+#define DBG_RD_STS_CNT_MSK 0xffff0000
+#define DBG_RD_STS_CNT_I_MSK 0x0000ffff
+#define DBG_RD_STS_CNT_SFT 16
+#define DBG_RD_STS_CNT_HI 31
+#define DBG_RD_STS_CNT_SZ 16
+#define DBG_JUDGE_CNT_MSK 0x0000ffff
+#define DBG_JUDGE_CNT_I_MSK 0xffff0000
+#define DBG_JUDGE_CNT_SFT 0
+#define DBG_JUDGE_CNT_HI 15
+#define DBG_JUDGE_CNT_SZ 16
+#define DBG_RD_STS_CNT_CLR_MSK 0x00010000
+#define DBG_RD_STS_CNT_CLR_I_MSK 0xfffeffff
+#define DBG_RD_STS_CNT_CLR_SFT 16
+#define DBG_RD_STS_CNT_CLR_HI 16
+#define DBG_RD_STS_CNT_CLR_SZ 1
+#define DBG_RD_DAT_CNT_CLR_MSK 0x00020000
+#define DBG_RD_DAT_CNT_CLR_I_MSK 0xfffdffff
+#define DBG_RD_DAT_CNT_CLR_SFT 17
+#define DBG_RD_DAT_CNT_CLR_HI 17
+#define DBG_RD_DAT_CNT_CLR_SZ 1
+#define DBG_JUDGE_CNT_CLR_MSK 0x00040000
+#define DBG_JUDGE_CNT_CLR_I_MSK 0xfffbffff
+#define DBG_JUDGE_CNT_CLR_SFT 18
+#define DBG_JUDGE_CNT_CLR_HI 18
+#define DBG_JUDGE_CNT_CLR_SZ 1
+#define DBG_TX_DONE_CNT_MSK 0x0000ffff
+#define DBG_TX_DONE_CNT_I_MSK 0xffff0000
+#define DBG_TX_DONE_CNT_SFT 0
+#define DBG_TX_DONE_CNT_HI 15
+#define DBG_TX_DONE_CNT_SZ 16
+#define DBG_TX_DISCARD_CNT_MSK 0xffff0000
+#define DBG_TX_DISCARD_CNT_I_MSK 0x0000ffff
+#define DBG_TX_DISCARD_CNT_SFT 16
+#define DBG_TX_DISCARD_CNT_HI 31
+#define DBG_TX_DISCARD_CNT_SZ 16
+#define DBG_TX_SET_CNT_MSK 0x0000ffff
+#define DBG_TX_SET_CNT_I_MSK 0xffff0000
+#define DBG_TX_SET_CNT_SFT 0
+#define DBG_TX_SET_CNT_HI 15
+#define DBG_TX_SET_CNT_SZ 16
+#define DBG_TX_DISCARD_CNT_CLR_MSK 0x00010000
+#define DBG_TX_DISCARD_CNT_CLR_I_MSK 0xfffeffff
+#define DBG_TX_DISCARD_CNT_CLR_SFT 16
+#define DBG_TX_DISCARD_CNT_CLR_HI 16
+#define DBG_TX_DISCARD_CNT_CLR_SZ 1
+#define DBG_TX_DONE_CNT_CLR_MSK 0x00020000
+#define DBG_TX_DONE_CNT_CLR_I_MSK 0xfffdffff
+#define DBG_TX_DONE_CNT_CLR_SFT 17
+#define DBG_TX_DONE_CNT_CLR_HI 17
+#define DBG_TX_DONE_CNT_CLR_SZ 1
+#define DBG_TX_SET_CNT_CLR_MSK 0x00040000
+#define DBG_TX_SET_CNT_CLR_I_MSK 0xfffbffff
+#define DBG_TX_SET_CNT_CLR_SFT 18
+#define DBG_TX_SET_CNT_CLR_HI 18
+#define DBG_TX_SET_CNT_CLR_SZ 1
+#define DBG_DAT_MODE_OFF_MSK 0x00080000
+#define DBG_DAT_MODE_OFF_I_MSK 0xfff7ffff
+#define DBG_DAT_MODE_OFF_SFT 19
+#define DBG_DAT_MODE_OFF_HI 19
+#define DBG_DAT_MODE_OFF_SZ 1
+#define DBG_TX_FIFO_RESIDUE_MSK 0x00700000
+#define DBG_TX_FIFO_RESIDUE_I_MSK 0xff8fffff
+#define DBG_TX_FIFO_RESIDUE_SFT 20
+#define DBG_TX_FIFO_RESIDUE_HI 22
+#define DBG_TX_FIFO_RESIDUE_SZ 3
+#define DBG_RX_FIFO_RESIDUE_MSK 0x07000000
+#define DBG_RX_FIFO_RESIDUE_I_MSK 0xf8ffffff
+#define DBG_RX_FIFO_RESIDUE_SFT 24
+#define DBG_RX_FIFO_RESIDUE_HI 26
+#define DBG_RX_FIFO_RESIDUE_SZ 3
+#define DBG_RX_RDY_MSK 0x00000001
+#define DBG_RX_RDY_I_MSK 0xfffffffe
+#define DBG_RX_RDY_SFT 0
+#define DBG_RX_RDY_HI 0
+#define DBG_RX_RDY_SZ 1
+#define DBG_SDIO_SYS_INT_MSK 0x00000004
+#define DBG_SDIO_SYS_INT_I_MSK 0xfffffffb
+#define DBG_SDIO_SYS_INT_SFT 2
+#define DBG_SDIO_SYS_INT_HI 2
+#define DBG_SDIO_SYS_INT_SZ 1
+#define DBG_EDCA0_LOWTHOLD_INT_MSK 0x00000008
+#define DBG_EDCA0_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define DBG_EDCA0_LOWTHOLD_INT_SFT 3
+#define DBG_EDCA0_LOWTHOLD_INT_HI 3
+#define DBG_EDCA0_LOWTHOLD_INT_SZ 1
+#define DBG_EDCA1_LOWTHOLD_INT_MSK 0x00000010
+#define DBG_EDCA1_LOWTHOLD_INT_I_MSK 0xffffffef
+#define DBG_EDCA1_LOWTHOLD_INT_SFT 4
+#define DBG_EDCA1_LOWTHOLD_INT_HI 4
+#define DBG_EDCA1_LOWTHOLD_INT_SZ 1
+#define DBG_EDCA2_LOWTHOLD_INT_MSK 0x00000020
+#define DBG_EDCA2_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define DBG_EDCA2_LOWTHOLD_INT_SFT 5
+#define DBG_EDCA2_LOWTHOLD_INT_HI 5
+#define DBG_EDCA2_LOWTHOLD_INT_SZ 1
+#define DBG_EDCA3_LOWTHOLD_INT_MSK 0x00000040
+#define DBG_EDCA3_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define DBG_EDCA3_LOWTHOLD_INT_SFT 6
+#define DBG_EDCA3_LOWTHOLD_INT_HI 6
+#define DBG_EDCA3_LOWTHOLD_INT_SZ 1
+#define DBG_TX_LIMIT_INT_IN_MSK 0x00000080
+#define DBG_TX_LIMIT_INT_IN_I_MSK 0xffffff7f
+#define DBG_TX_LIMIT_INT_IN_SFT 7
+#define DBG_TX_LIMIT_INT_IN_HI 7
+#define DBG_TX_LIMIT_INT_IN_SZ 1
+#define DBG_SPI_FN1_MSK 0x00007f00
+#define DBG_SPI_FN1_I_MSK 0xffff80ff
+#define DBG_SPI_FN1_SFT 8
+#define DBG_SPI_FN1_HI 14
+#define DBG_SPI_FN1_SZ 7
+#define DBG_SPI_CLK_EN_INT_MSK 0x00008000
+#define DBG_SPI_CLK_EN_INT_I_MSK 0xffff7fff
+#define DBG_SPI_CLK_EN_INT_SFT 15
+#define DBG_SPI_CLK_EN_INT_HI 15
+#define DBG_SPI_CLK_EN_INT_SZ 1
+#define DBG_SPI_HOST_MASK_MSK 0x00ff0000
+#define DBG_SPI_HOST_MASK_I_MSK 0xff00ffff
+#define DBG_SPI_HOST_MASK_SFT 16
+#define DBG_SPI_HOST_MASK_HI 23
+#define DBG_SPI_HOST_MASK_SZ 8
+#define BOOT_ADDR_MSK 0x00ffffff
+#define BOOT_ADDR_I_MSK 0xff000000
+#define BOOT_ADDR_SFT 0
+#define BOOT_ADDR_HI 23
+#define BOOT_ADDR_SZ 24
+#define CHECK_SUM_FAIL_MSK 0x80000000
+#define CHECK_SUM_FAIL_I_MSK 0x7fffffff
+#define CHECK_SUM_FAIL_SFT 31
+#define CHECK_SUM_FAIL_HI 31
+#define CHECK_SUM_FAIL_SZ 1
+#define VERIFY_DATA_MSK 0xffffffff
+#define VERIFY_DATA_I_MSK 0x00000000
+#define VERIFY_DATA_SFT 0
+#define VERIFY_DATA_HI 31
+#define VERIFY_DATA_SZ 32
+#define FLASH_ADDR_MSK 0x00ffffff
+#define FLASH_ADDR_I_MSK 0xff000000
+#define FLASH_ADDR_SFT 0
+#define FLASH_ADDR_HI 23
+#define FLASH_ADDR_SZ 24
+#define FLASH_CMD_CLR_MSK 0x10000000
+#define FLASH_CMD_CLR_I_MSK 0xefffffff
+#define FLASH_CMD_CLR_SFT 28
+#define FLASH_CMD_CLR_HI 28
+#define FLASH_CMD_CLR_SZ 1
+#define FLASH_DMA_CLR_MSK 0x20000000
+#define FLASH_DMA_CLR_I_MSK 0xdfffffff
+#define FLASH_DMA_CLR_SFT 29
+#define FLASH_DMA_CLR_HI 29
+#define FLASH_DMA_CLR_SZ 1
+#define DMA_EN_MSK 0x40000000
+#define DMA_EN_I_MSK 0xbfffffff
+#define DMA_EN_SFT 30
+#define DMA_EN_HI 30
+#define DMA_EN_SZ 1
+#define DMA_BUSY_MSK 0x80000000
+#define DMA_BUSY_I_MSK 0x7fffffff
+#define DMA_BUSY_SFT 31
+#define DMA_BUSY_HI 31
+#define DMA_BUSY_SZ 1
+#define SRAM_ADDR_MSK 0xffffffff
+#define SRAM_ADDR_I_MSK 0x00000000
+#define SRAM_ADDR_SFT 0
+#define SRAM_ADDR_HI 31
+#define SRAM_ADDR_SZ 32
+#define FLASH_DMA_LEN_MSK 0xffffffff
+#define FLASH_DMA_LEN_I_MSK 0x00000000
+#define FLASH_DMA_LEN_SFT 0
+#define FLASH_DMA_LEN_HI 31
+#define FLASH_DMA_LEN_SZ 32
+#define FLASH_FRONT_DLY_MSK 0x0000ffff
+#define FLASH_FRONT_DLY_I_MSK 0xffff0000
+#define FLASH_FRONT_DLY_SFT 0
+#define FLASH_FRONT_DLY_HI 15
+#define FLASH_FRONT_DLY_SZ 16
+#define FLASH_BACK_DLY_MSK 0xffff0000
+#define FLASH_BACK_DLY_I_MSK 0x0000ffff
+#define FLASH_BACK_DLY_SFT 16
+#define FLASH_BACK_DLY_HI 31
+#define FLASH_BACK_DLY_SZ 16
+#define FLASH_CLK_WIDTH_MSK 0x0000ffff
+#define FLASH_CLK_WIDTH_I_MSK 0xffff0000
+#define FLASH_CLK_WIDTH_SFT 0
+#define FLASH_CLK_WIDTH_HI 15
+#define FLASH_CLK_WIDTH_SZ 16
+#define SPI_BUSY_MSK 0x00010000
+#define SPI_BUSY_I_MSK 0xfffeffff
+#define SPI_BUSY_SFT 16
+#define SPI_BUSY_HI 16
+#define SPI_BUSY_SZ 1
+#define FLS_REMAP_MSK 0x00020000
+#define FLS_REMAP_I_MSK 0xfffdffff
+#define FLS_REMAP_SFT 17
+#define FLS_REMAP_HI 17
+#define FLS_REMAP_SZ 1
+#define PBUS_SWP_MSK 0x00040000
+#define PBUS_SWP_I_MSK 0xfffbffff
+#define PBUS_SWP_SFT 18
+#define PBUS_SWP_HI 18
+#define PBUS_SWP_SZ 1
+#define BIT_MODE1_MSK 0x00080000
+#define BIT_MODE1_I_MSK 0xfff7ffff
+#define BIT_MODE1_SFT 19
+#define BIT_MODE1_HI 19
+#define BIT_MODE1_SZ 1
+#define BIT_MODE2_MSK 0x00100000
+#define BIT_MODE2_I_MSK 0xffefffff
+#define BIT_MODE2_SFT 20
+#define BIT_MODE2_HI 20
+#define BIT_MODE2_SZ 1
+#define BIT_MODE4_MSK 0x00200000
+#define BIT_MODE4_I_MSK 0xffdfffff
+#define BIT_MODE4_SFT 21
+#define BIT_MODE4_HI 21
+#define BIT_MODE4_SZ 1
+#define BOOT_CHECK_SUM_MSK 0xffffffff
+#define BOOT_CHECK_SUM_I_MSK 0x00000000
+#define BOOT_CHECK_SUM_SFT 0
+#define BOOT_CHECK_SUM_HI 31
+#define BOOT_CHECK_SUM_SZ 32
+#define CHECK_SUM_TAG_MSK 0xffffffff
+#define CHECK_SUM_TAG_I_MSK 0x00000000
+#define CHECK_SUM_TAG_SFT 0
+#define CHECK_SUM_TAG_HI 31
+#define CHECK_SUM_TAG_SZ 32
+#define CMD_LEN_MSK 0x0000ffff
+#define CMD_LEN_I_MSK 0xffff0000
+#define CMD_LEN_SFT 0
+#define CMD_LEN_HI 15
+#define CMD_LEN_SZ 16
+#define CMD_ADDR_MSK 0xffffffff
+#define CMD_ADDR_I_MSK 0x00000000
+#define CMD_ADDR_SFT 0
+#define CMD_ADDR_HI 31
+#define CMD_ADDR_SZ 32
+#define DMA_ADR_SRC_MSK 0xffffffff
+#define DMA_ADR_SRC_I_MSK 0x00000000
+#define DMA_ADR_SRC_SFT 0
+#define DMA_ADR_SRC_HI 31
+#define DMA_ADR_SRC_SZ 32
+#define DMA_ADR_DST_MSK 0xffffffff
+#define DMA_ADR_DST_I_MSK 0x00000000
+#define DMA_ADR_DST_SFT 0
+#define DMA_ADR_DST_HI 31
+#define DMA_ADR_DST_SZ 32
+#define DMA_SRC_SIZE_MSK 0x00000007
+#define DMA_SRC_SIZE_I_MSK 0xfffffff8
+#define DMA_SRC_SIZE_SFT 0
+#define DMA_SRC_SIZE_HI 2
+#define DMA_SRC_SIZE_SZ 3
+#define DMA_SRC_INC_MSK 0x00000008
+#define DMA_SRC_INC_I_MSK 0xfffffff7
+#define DMA_SRC_INC_SFT 3
+#define DMA_SRC_INC_HI 3
+#define DMA_SRC_INC_SZ 1
+#define DMA_DST_SIZE_MSK 0x00000070
+#define DMA_DST_SIZE_I_MSK 0xffffff8f
+#define DMA_DST_SIZE_SFT 4
+#define DMA_DST_SIZE_HI 6
+#define DMA_DST_SIZE_SZ 3
+#define DMA_DST_INC_MSK 0x00000080
+#define DMA_DST_INC_I_MSK 0xffffff7f
+#define DMA_DST_INC_SFT 7
+#define DMA_DST_INC_HI 7
+#define DMA_DST_INC_SZ 1
+#define DMA_FAST_FILL_MSK 0x00000100
+#define DMA_FAST_FILL_I_MSK 0xfffffeff
+#define DMA_FAST_FILL_SFT 8
+#define DMA_FAST_FILL_HI 8
+#define DMA_FAST_FILL_SZ 1
+#define DMA_SDIO_KICK_MSK 0x00001000
+#define DMA_SDIO_KICK_I_MSK 0xffffefff
+#define DMA_SDIO_KICK_SFT 12
+#define DMA_SDIO_KICK_HI 12
+#define DMA_SDIO_KICK_SZ 1
+#define DMA_BADR_EN_MSK 0x00002000
+#define DMA_BADR_EN_I_MSK 0xffffdfff
+#define DMA_BADR_EN_SFT 13
+#define DMA_BADR_EN_HI 13
+#define DMA_BADR_EN_SZ 1
+#define DMA_LEN_MSK 0xffff0000
+#define DMA_LEN_I_MSK 0x0000ffff
+#define DMA_LEN_SFT 16
+#define DMA_LEN_HI 31
+#define DMA_LEN_SZ 16
+#define DMA_INT_MASK_MSK 0x00000001
+#define DMA_INT_MASK_I_MSK 0xfffffffe
+#define DMA_INT_MASK_SFT 0
+#define DMA_INT_MASK_HI 0
+#define DMA_INT_MASK_SZ 1
+#define DMA_STS_MSK 0x00000100
+#define DMA_STS_I_MSK 0xfffffeff
+#define DMA_STS_SFT 8
+#define DMA_STS_HI 8
+#define DMA_STS_SZ 1
+#define DMA_FINISH_MSK 0x80000000
+#define DMA_FINISH_I_MSK 0x7fffffff
+#define DMA_FINISH_SFT 31
+#define DMA_FINISH_HI 31
+#define DMA_FINISH_SZ 1
+#define DMA_CONST_MSK 0xffffffff
+#define DMA_CONST_I_MSK 0x00000000
+#define DMA_CONST_SFT 0
+#define DMA_CONST_HI 31
+#define DMA_CONST_SZ 32
+#define SLEEP_WAKE_CNT_MSK 0x00ffffff
+#define SLEEP_WAKE_CNT_I_MSK 0xff000000
+#define SLEEP_WAKE_CNT_SFT 0
+#define SLEEP_WAKE_CNT_HI 23
+#define SLEEP_WAKE_CNT_SZ 24
+#define RG_DLDO_LEVEL_MSK 0x07000000
+#define RG_DLDO_LEVEL_I_MSK 0xf8ffffff
+#define RG_DLDO_LEVEL_SFT 24
+#define RG_DLDO_LEVEL_HI 26
+#define RG_DLDO_LEVEL_SZ 3
+#define RG_DLDO_BOOST_IQ_MSK 0x08000000
+#define RG_DLDO_BOOST_IQ_I_MSK 0xf7ffffff
+#define RG_DLDO_BOOST_IQ_SFT 27
+#define RG_DLDO_BOOST_IQ_HI 27
+#define RG_DLDO_BOOST_IQ_SZ 1
+#define RG_BUCK_LEVEL_MSK 0x70000000
+#define RG_BUCK_LEVEL_I_MSK 0x8fffffff
+#define RG_BUCK_LEVEL_SFT 28
+#define RG_BUCK_LEVEL_HI 30
+#define RG_BUCK_LEVEL_SZ 3
+#define RG_BUCK_VREF_SEL_MSK 0x80000000
+#define RG_BUCK_VREF_SEL_I_MSK 0x7fffffff
+#define RG_BUCK_VREF_SEL_SFT 31
+#define RG_BUCK_VREF_SEL_HI 31
+#define RG_BUCK_VREF_SEL_SZ 1
+#define RG_RTC_OSC_RES_SW_MANUAL_MSK 0x000003ff
+#define RG_RTC_OSC_RES_SW_MANUAL_I_MSK 0xfffffc00
+#define RG_RTC_OSC_RES_SW_MANUAL_SFT 0
+#define RG_RTC_OSC_RES_SW_MANUAL_HI 9
+#define RG_RTC_OSC_RES_SW_MANUAL_SZ 10
+#define RG_RTC_OSC_RES_SW_MSK 0x03ff0000
+#define RG_RTC_OSC_RES_SW_I_MSK 0xfc00ffff
+#define RG_RTC_OSC_RES_SW_SFT 16
+#define RG_RTC_OSC_RES_SW_HI 25
+#define RG_RTC_OSC_RES_SW_SZ 10
+#define RTC_OSC_CAL_RES_RDY_MSK 0x80000000
+#define RTC_OSC_CAL_RES_RDY_I_MSK 0x7fffffff
+#define RTC_OSC_CAL_RES_RDY_SFT 31
+#define RTC_OSC_CAL_RES_RDY_HI 31
+#define RTC_OSC_CAL_RES_RDY_SZ 1
+#define RG_DCDC_MODE_MSK 0x00000001
+#define RG_DCDC_MODE_I_MSK 0xfffffffe
+#define RG_DCDC_MODE_SFT 0
+#define RG_DCDC_MODE_HI 0
+#define RG_DCDC_MODE_SZ 1
+#define RG_BUCK_EN_PSM_MSK 0x00000010
+#define RG_BUCK_EN_PSM_I_MSK 0xffffffef
+#define RG_BUCK_EN_PSM_SFT 4
+#define RG_BUCK_EN_PSM_HI 4
+#define RG_BUCK_EN_PSM_SZ 1
+#define RG_BUCK_PSM_VTH_MSK 0x00000100
+#define RG_BUCK_PSM_VTH_I_MSK 0xfffffeff
+#define RG_BUCK_PSM_VTH_SFT 8
+#define RG_BUCK_PSM_VTH_HI 8
+#define RG_BUCK_PSM_VTH_SZ 1
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_MSK 0x00001000
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_I_MSK 0xffffefff
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_SFT 12
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_HI 12
+#define RG_RTC_OSC_RES_SW_MANUAL_EN_SZ 1
+#define RG_RTC_RDY_DEGLITCH_TIMER_MSK 0x00006000
+#define RG_RTC_RDY_DEGLITCH_TIMER_I_MSK 0xffff9fff
+#define RG_RTC_RDY_DEGLITCH_TIMER_SFT 13
+#define RG_RTC_RDY_DEGLITCH_TIMER_HI 14
+#define RG_RTC_RDY_DEGLITCH_TIMER_SZ 2
+#define RTC_CAL_ENA_MSK 0x00010000
+#define RTC_CAL_ENA_I_MSK 0xfffeffff
+#define RTC_CAL_ENA_SFT 16
+#define RTC_CAL_ENA_HI 16
+#define RTC_CAL_ENA_SZ 1
+#define PMU_WAKE_TRIG_EVENT_MSK 0x00000003
+#define PMU_WAKE_TRIG_EVENT_I_MSK 0xfffffffc
+#define PMU_WAKE_TRIG_EVENT_SFT 0
+#define PMU_WAKE_TRIG_EVENT_HI 1
+#define PMU_WAKE_TRIG_EVENT_SZ 2
+#define DIGI_TOP_POR_MASK_MSK 0x00000010
+#define DIGI_TOP_POR_MASK_I_MSK 0xffffffef
+#define DIGI_TOP_POR_MASK_SFT 4
+#define DIGI_TOP_POR_MASK_HI 4
+#define DIGI_TOP_POR_MASK_SZ 1
+#define PMU_ENTER_SLEEP_MODE_MSK 0x00000100
+#define PMU_ENTER_SLEEP_MODE_I_MSK 0xfffffeff
+#define PMU_ENTER_SLEEP_MODE_SFT 8
+#define PMU_ENTER_SLEEP_MODE_HI 8
+#define PMU_ENTER_SLEEP_MODE_SZ 1
+#define RG_RTC_DUMMIES_MSK 0xffff0000
+#define RG_RTC_DUMMIES_I_MSK 0x0000ffff
+#define RG_RTC_DUMMIES_SFT 16
+#define RG_RTC_DUMMIES_HI 31
+#define RG_RTC_DUMMIES_SZ 16
+#define RTC_EN_MSK 0x00000001
+#define RTC_EN_I_MSK 0xfffffffe
+#define RTC_EN_SFT 0
+#define RTC_EN_HI 0
+#define RTC_EN_SZ 1
+#define RTC_SRC_MSK 0x00000002
+#define RTC_SRC_I_MSK 0xfffffffd
+#define RTC_SRC_SFT 1
+#define RTC_SRC_HI 1
+#define RTC_SRC_SZ 1
+#define RTC_TICK_CNT_MSK 0x7fff0000
+#define RTC_TICK_CNT_I_MSK 0x8000ffff
+#define RTC_TICK_CNT_SFT 16
+#define RTC_TICK_CNT_HI 30
+#define RTC_TICK_CNT_SZ 15
+#define RTC_INT_SEC_MASK_MSK 0x00000001
+#define RTC_INT_SEC_MASK_I_MSK 0xfffffffe
+#define RTC_INT_SEC_MASK_SFT 0
+#define RTC_INT_SEC_MASK_HI 0
+#define RTC_INT_SEC_MASK_SZ 1
+#define RTC_INT_ALARM_MASK_MSK 0x00000002
+#define RTC_INT_ALARM_MASK_I_MSK 0xfffffffd
+#define RTC_INT_ALARM_MASK_SFT 1
+#define RTC_INT_ALARM_MASK_HI 1
+#define RTC_INT_ALARM_MASK_SZ 1
+#define RTC_INT_SEC_MSK 0x00010000
+#define RTC_INT_SEC_I_MSK 0xfffeffff
+#define RTC_INT_SEC_SFT 16
+#define RTC_INT_SEC_HI 16
+#define RTC_INT_SEC_SZ 1
+#define RTC_INT_ALARM_MSK 0x00020000
+#define RTC_INT_ALARM_I_MSK 0xfffdffff
+#define RTC_INT_ALARM_SFT 17
+#define RTC_INT_ALARM_HI 17
+#define RTC_INT_ALARM_SZ 1
+#define RTC_SEC_START_CNT_MSK 0xffffffff
+#define RTC_SEC_START_CNT_I_MSK 0x00000000
+#define RTC_SEC_START_CNT_SFT 0
+#define RTC_SEC_START_CNT_HI 31
+#define RTC_SEC_START_CNT_SZ 32
+#define RTC_SEC_CNT_MSK 0xffffffff
+#define RTC_SEC_CNT_I_MSK 0x00000000
+#define RTC_SEC_CNT_SFT 0
+#define RTC_SEC_CNT_HI 31
+#define RTC_SEC_CNT_SZ 32
+#define RTC_SEC_ALARM_VALUE_MSK 0xffffffff
+#define RTC_SEC_ALARM_VALUE_I_MSK 0x00000000
+#define RTC_SEC_ALARM_VALUE_SFT 0
+#define RTC_SEC_ALARM_VALUE_HI 31
+#define RTC_SEC_ALARM_VALUE_SZ 32
+#define D2_DMA_ADR_SRC_MSK 0xffffffff
+#define D2_DMA_ADR_SRC_I_MSK 0x00000000
+#define D2_DMA_ADR_SRC_SFT 0
+#define D2_DMA_ADR_SRC_HI 31
+#define D2_DMA_ADR_SRC_SZ 32
+#define D2_DMA_ADR_DST_MSK 0xffffffff
+#define D2_DMA_ADR_DST_I_MSK 0x00000000
+#define D2_DMA_ADR_DST_SFT 0
+#define D2_DMA_ADR_DST_HI 31
+#define D2_DMA_ADR_DST_SZ 32
+#define D2_DMA_SRC_SIZE_MSK 0x00000007
+#define D2_DMA_SRC_SIZE_I_MSK 0xfffffff8
+#define D2_DMA_SRC_SIZE_SFT 0
+#define D2_DMA_SRC_SIZE_HI 2
+#define D2_DMA_SRC_SIZE_SZ 3
+#define D2_DMA_SRC_INC_MSK 0x00000008
+#define D2_DMA_SRC_INC_I_MSK 0xfffffff7
+#define D2_DMA_SRC_INC_SFT 3
+#define D2_DMA_SRC_INC_HI 3
+#define D2_DMA_SRC_INC_SZ 1
+#define D2_DMA_DST_SIZE_MSK 0x00000070
+#define D2_DMA_DST_SIZE_I_MSK 0xffffff8f
+#define D2_DMA_DST_SIZE_SFT 4
+#define D2_DMA_DST_SIZE_HI 6
+#define D2_DMA_DST_SIZE_SZ 3
+#define D2_DMA_DST_INC_MSK 0x00000080
+#define D2_DMA_DST_INC_I_MSK 0xffffff7f
+#define D2_DMA_DST_INC_SFT 7
+#define D2_DMA_DST_INC_HI 7
+#define D2_DMA_DST_INC_SZ 1
+#define D2_DMA_FAST_FILL_MSK 0x00000100
+#define D2_DMA_FAST_FILL_I_MSK 0xfffffeff
+#define D2_DMA_FAST_FILL_SFT 8
+#define D2_DMA_FAST_FILL_HI 8
+#define D2_DMA_FAST_FILL_SZ 1
+#define D2_DMA_SDIO_KICK_MSK 0x00001000
+#define D2_DMA_SDIO_KICK_I_MSK 0xffffefff
+#define D2_DMA_SDIO_KICK_SFT 12
+#define D2_DMA_SDIO_KICK_HI 12
+#define D2_DMA_SDIO_KICK_SZ 1
+#define D2_DMA_BADR_EN_MSK 0x00002000
+#define D2_DMA_BADR_EN_I_MSK 0xffffdfff
+#define D2_DMA_BADR_EN_SFT 13
+#define D2_DMA_BADR_EN_HI 13
+#define D2_DMA_BADR_EN_SZ 1
+#define D2_DMA_LEN_MSK 0xffff0000
+#define D2_DMA_LEN_I_MSK 0x0000ffff
+#define D2_DMA_LEN_SFT 16
+#define D2_DMA_LEN_HI 31
+#define D2_DMA_LEN_SZ 16
+#define D2_DMA_INT_MASK_MSK 0x00000001
+#define D2_DMA_INT_MASK_I_MSK 0xfffffffe
+#define D2_DMA_INT_MASK_SFT 0
+#define D2_DMA_INT_MASK_HI 0
+#define D2_DMA_INT_MASK_SZ 1
+#define D2_DMA_STS_MSK 0x00000100
+#define D2_DMA_STS_I_MSK 0xfffffeff
+#define D2_DMA_STS_SFT 8
+#define D2_DMA_STS_HI 8
+#define D2_DMA_STS_SZ 1
+#define D2_DMA_FINISH_MSK 0x80000000
+#define D2_DMA_FINISH_I_MSK 0x7fffffff
+#define D2_DMA_FINISH_SFT 31
+#define D2_DMA_FINISH_HI 31
+#define D2_DMA_FINISH_SZ 1
+#define D2_DMA_CONST_MSK 0xffffffff
+#define D2_DMA_CONST_I_MSK 0x00000000
+#define D2_DMA_CONST_SFT 0
+#define D2_DMA_CONST_HI 31
+#define D2_DMA_CONST_SZ 32
+#define TRAP_UNKNOWN_TYPE_MSK 0x00000001
+#define TRAP_UNKNOWN_TYPE_I_MSK 0xfffffffe
+#define TRAP_UNKNOWN_TYPE_SFT 0
+#define TRAP_UNKNOWN_TYPE_HI 0
+#define TRAP_UNKNOWN_TYPE_SZ 1
+#define TX_ON_DEMAND_ENA_MSK 0x00000002
+#define TX_ON_DEMAND_ENA_I_MSK 0xfffffffd
+#define TX_ON_DEMAND_ENA_SFT 1
+#define TX_ON_DEMAND_ENA_HI 1
+#define TX_ON_DEMAND_ENA_SZ 1
+#define RX_2_HOST_MSK 0x00000004
+#define RX_2_HOST_I_MSK 0xfffffffb
+#define RX_2_HOST_SFT 2
+#define RX_2_HOST_HI 2
+#define RX_2_HOST_SZ 1
+#define AUTO_SEQNO_MSK 0x00000008
+#define AUTO_SEQNO_I_MSK 0xfffffff7
+#define AUTO_SEQNO_SFT 3
+#define AUTO_SEQNO_HI 3
+#define AUTO_SEQNO_SZ 1
+#define BYPASSS_TX_PARSER_ENCAP_MSK 0x00000010
+#define BYPASSS_TX_PARSER_ENCAP_I_MSK 0xffffffef
+#define BYPASSS_TX_PARSER_ENCAP_SFT 4
+#define BYPASSS_TX_PARSER_ENCAP_HI 4
+#define BYPASSS_TX_PARSER_ENCAP_SZ 1
+#define HDR_STRIP_MSK 0x00000020
+#define HDR_STRIP_I_MSK 0xffffffdf
+#define HDR_STRIP_SFT 5
+#define HDR_STRIP_HI 5
+#define HDR_STRIP_SZ 1
+#define ERP_PROTECT_MSK 0x000000c0
+#define ERP_PROTECT_I_MSK 0xffffff3f
+#define ERP_PROTECT_SFT 6
+#define ERP_PROTECT_HI 7
+#define ERP_PROTECT_SZ 2
+#define PRO_VER_MSK 0x00000300
+#define PRO_VER_I_MSK 0xfffffcff
+#define PRO_VER_SFT 8
+#define PRO_VER_HI 9
+#define PRO_VER_SZ 2
+#define TXQ_ID0_MSK 0x00007000
+#define TXQ_ID0_I_MSK 0xffff8fff
+#define TXQ_ID0_SFT 12
+#define TXQ_ID0_HI 14
+#define TXQ_ID0_SZ 3
+#define TXQ_ID1_MSK 0x00070000
+#define TXQ_ID1_I_MSK 0xfff8ffff
+#define TXQ_ID1_SFT 16
+#define TXQ_ID1_HI 18
+#define TXQ_ID1_SZ 3
+#define TX_ETHER_TRAP_EN_MSK 0x00100000
+#define TX_ETHER_TRAP_EN_I_MSK 0xffefffff
+#define TX_ETHER_TRAP_EN_SFT 20
+#define TX_ETHER_TRAP_EN_HI 20
+#define TX_ETHER_TRAP_EN_SZ 1
+#define RX_ETHER_TRAP_EN_MSK 0x00200000
+#define RX_ETHER_TRAP_EN_I_MSK 0xffdfffff
+#define RX_ETHER_TRAP_EN_SFT 21
+#define RX_ETHER_TRAP_EN_HI 21
+#define RX_ETHER_TRAP_EN_SZ 1
+#define RX_NULL_TRAP_EN_MSK 0x00400000
+#define RX_NULL_TRAP_EN_I_MSK 0xffbfffff
+#define RX_NULL_TRAP_EN_SFT 22
+#define RX_NULL_TRAP_EN_HI 22
+#define RX_NULL_TRAP_EN_SZ 1
+#define RX_GET_TX_QUEUE_EN_MSK 0x02000000
+#define RX_GET_TX_QUEUE_EN_I_MSK 0xfdffffff
+#define RX_GET_TX_QUEUE_EN_SFT 25
+#define RX_GET_TX_QUEUE_EN_HI 25
+#define RX_GET_TX_QUEUE_EN_SZ 1
+#define HCI_INQ_SEL_MSK 0x04000000
+#define HCI_INQ_SEL_I_MSK 0xfbffffff
+#define HCI_INQ_SEL_SFT 26
+#define HCI_INQ_SEL_HI 26
+#define HCI_INQ_SEL_SZ 1
+#define TRX_DEBUG_CNT_ENA_MSK 0x10000000
+#define TRX_DEBUG_CNT_ENA_I_MSK 0xefffffff
+#define TRX_DEBUG_CNT_ENA_SFT 28
+#define TRX_DEBUG_CNT_ENA_HI 28
+#define TRX_DEBUG_CNT_ENA_SZ 1
+#define WAKE_SOON_WITH_SCK_MSK 0x00000001
+#define WAKE_SOON_WITH_SCK_I_MSK 0xfffffffe
+#define WAKE_SOON_WITH_SCK_SFT 0
+#define WAKE_SOON_WITH_SCK_HI 0
+#define WAKE_SOON_WITH_SCK_SZ 1
+#define TX_FLOW_CTRL_MSK 0x0000ffff
+#define TX_FLOW_CTRL_I_MSK 0xffff0000
+#define TX_FLOW_CTRL_SFT 0
+#define TX_FLOW_CTRL_HI 15
+#define TX_FLOW_CTRL_SZ 16
+#define TX_FLOW_MGMT_MSK 0xffff0000
+#define TX_FLOW_MGMT_I_MSK 0x0000ffff
+#define TX_FLOW_MGMT_SFT 16
+#define TX_FLOW_MGMT_HI 31
+#define TX_FLOW_MGMT_SZ 16
+#define TX_FLOW_DATA_MSK 0xffffffff
+#define TX_FLOW_DATA_I_MSK 0x00000000
+#define TX_FLOW_DATA_SFT 0
+#define TX_FLOW_DATA_HI 31
+#define TX_FLOW_DATA_SZ 32
+#define DOT11RTSTHRESHOLD_MSK 0xffff0000
+#define DOT11RTSTHRESHOLD_I_MSK 0x0000ffff
+#define DOT11RTSTHRESHOLD_SFT 16
+#define DOT11RTSTHRESHOLD_HI 31
+#define DOT11RTSTHRESHOLD_SZ 16
+#define TXF_ID_MSK 0x0000003f
+#define TXF_ID_I_MSK 0xffffffc0
+#define TXF_ID_SFT 0
+#define TXF_ID_HI 5
+#define TXF_ID_SZ 6
+#define SEQ_CTRL_MSK 0x0000ffff
+#define SEQ_CTRL_I_MSK 0xffff0000
+#define SEQ_CTRL_SFT 0
+#define SEQ_CTRL_HI 15
+#define SEQ_CTRL_SZ 16
+#define TX_PBOFFSET_MSK 0x000000ff
+#define TX_PBOFFSET_I_MSK 0xffffff00
+#define TX_PBOFFSET_SFT 0
+#define TX_PBOFFSET_HI 7
+#define TX_PBOFFSET_SZ 8
+#define TX_INFO_SIZE_MSK 0x0000ff00
+#define TX_INFO_SIZE_I_MSK 0xffff00ff
+#define TX_INFO_SIZE_SFT 8
+#define TX_INFO_SIZE_HI 15
+#define TX_INFO_SIZE_SZ 8
+#define RX_INFO_SIZE_MSK 0x00ff0000
+#define RX_INFO_SIZE_I_MSK 0xff00ffff
+#define RX_INFO_SIZE_SFT 16
+#define RX_INFO_SIZE_HI 23
+#define RX_INFO_SIZE_SZ 8
+#define RX_LAST_PHY_SIZE_MSK 0xff000000
+#define RX_LAST_PHY_SIZE_I_MSK 0x00ffffff
+#define RX_LAST_PHY_SIZE_SFT 24
+#define RX_LAST_PHY_SIZE_HI 31
+#define RX_LAST_PHY_SIZE_SZ 8
+#define TX_INFO_CLEAR_SIZE_MSK 0x0000003f
+#define TX_INFO_CLEAR_SIZE_I_MSK 0xffffffc0
+#define TX_INFO_CLEAR_SIZE_SFT 0
+#define TX_INFO_CLEAR_SIZE_HI 5
+#define TX_INFO_CLEAR_SIZE_SZ 6
+#define TX_INFO_CLEAR_ENABLE_MSK 0x00000100
+#define TX_INFO_CLEAR_ENABLE_I_MSK 0xfffffeff
+#define TX_INFO_CLEAR_ENABLE_SFT 8
+#define TX_INFO_CLEAR_ENABLE_HI 8
+#define TX_INFO_CLEAR_ENABLE_SZ 1
+#define TXTRAP_ETHTYPE1_MSK 0x0000ffff
+#define TXTRAP_ETHTYPE1_I_MSK 0xffff0000
+#define TXTRAP_ETHTYPE1_SFT 0
+#define TXTRAP_ETHTYPE1_HI 15
+#define TXTRAP_ETHTYPE1_SZ 16
+#define TXTRAP_ETHTYPE0_MSK 0xffff0000
+#define TXTRAP_ETHTYPE0_I_MSK 0x0000ffff
+#define TXTRAP_ETHTYPE0_SFT 16
+#define TXTRAP_ETHTYPE0_HI 31
+#define TXTRAP_ETHTYPE0_SZ 16
+#define RXTRAP_ETHTYPE1_MSK 0x0000ffff
+#define RXTRAP_ETHTYPE1_I_MSK 0xffff0000
+#define RXTRAP_ETHTYPE1_SFT 0
+#define RXTRAP_ETHTYPE1_HI 15
+#define RXTRAP_ETHTYPE1_SZ 16
+#define RXTRAP_ETHTYPE0_MSK 0xffff0000
+#define RXTRAP_ETHTYPE0_I_MSK 0x0000ffff
+#define RXTRAP_ETHTYPE0_SFT 16
+#define RXTRAP_ETHTYPE0_HI 31
+#define RXTRAP_ETHTYPE0_SZ 16
+#define TX_PKT_COUNTER_MSK 0xffffffff
+#define TX_PKT_COUNTER_I_MSK 0x00000000
+#define TX_PKT_COUNTER_SFT 0
+#define TX_PKT_COUNTER_HI 31
+#define TX_PKT_COUNTER_SZ 32
+#define RX_PKT_COUNTER_MSK 0xffffffff
+#define RX_PKT_COUNTER_I_MSK 0x00000000
+#define RX_PKT_COUNTER_SFT 0
+#define RX_PKT_COUNTER_HI 31
+#define RX_PKT_COUNTER_SZ 32
+#define HOST_CMD_COUNTER_MSK 0x000000ff
+#define HOST_CMD_COUNTER_I_MSK 0xffffff00
+#define HOST_CMD_COUNTER_SFT 0
+#define HOST_CMD_COUNTER_HI 7
+#define HOST_CMD_COUNTER_SZ 8
+#define HOST_EVENT_COUNTER_MSK 0x000000ff
+#define HOST_EVENT_COUNTER_I_MSK 0xffffff00
+#define HOST_EVENT_COUNTER_SFT 0
+#define HOST_EVENT_COUNTER_HI 7
+#define HOST_EVENT_COUNTER_SZ 8
+#define TX_PKT_DROP_COUNTER_MSK 0x000000ff
+#define TX_PKT_DROP_COUNTER_I_MSK 0xffffff00
+#define TX_PKT_DROP_COUNTER_SFT 0
+#define TX_PKT_DROP_COUNTER_HI 7
+#define TX_PKT_DROP_COUNTER_SZ 8
+#define RX_PKT_DROP_COUNTER_MSK 0x000000ff
+#define RX_PKT_DROP_COUNTER_I_MSK 0xffffff00
+#define RX_PKT_DROP_COUNTER_SFT 0
+#define RX_PKT_DROP_COUNTER_HI 7
+#define RX_PKT_DROP_COUNTER_SZ 8
+#define TX_PKT_TRAP_COUNTER_MSK 0x000000ff
+#define TX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
+#define TX_PKT_TRAP_COUNTER_SFT 0
+#define TX_PKT_TRAP_COUNTER_HI 7
+#define TX_PKT_TRAP_COUNTER_SZ 8
+#define RX_PKT_TRAP_COUNTER_MSK 0x000000ff
+#define RX_PKT_TRAP_COUNTER_I_MSK 0xffffff00
+#define RX_PKT_TRAP_COUNTER_SFT 0
+#define RX_PKT_TRAP_COUNTER_HI 7
+#define RX_PKT_TRAP_COUNTER_SZ 8
+#define HOST_TX_FAIL_COUNTER_MSK 0x000000ff
+#define HOST_TX_FAIL_COUNTER_I_MSK 0xffffff00
+#define HOST_TX_FAIL_COUNTER_SFT 0
+#define HOST_TX_FAIL_COUNTER_HI 7
+#define HOST_TX_FAIL_COUNTER_SZ 8
+#define HOST_RX_FAIL_COUNTER_MSK 0x000000ff
+#define HOST_RX_FAIL_COUNTER_I_MSK 0xffffff00
+#define HOST_RX_FAIL_COUNTER_SFT 0
+#define HOST_RX_FAIL_COUNTER_HI 7
+#define HOST_RX_FAIL_COUNTER_SZ 8
+#define HCI_STATE_MONITOR_MSK 0xffffffff
+#define HCI_STATE_MONITOR_I_MSK 0x00000000
+#define HCI_STATE_MONITOR_SFT 0
+#define HCI_STATE_MONITOR_HI 31
+#define HCI_STATE_MONITOR_SZ 32
+#define HCI_ST_TIMEOUT_MONITOR_MSK 0xffffffff
+#define HCI_ST_TIMEOUT_MONITOR_I_MSK 0x00000000
+#define HCI_ST_TIMEOUT_MONITOR_SFT 0
+#define HCI_ST_TIMEOUT_MONITOR_HI 31
+#define HCI_ST_TIMEOUT_MONITOR_SZ 32
+#define TX_ON_DEMAND_LENGTH_MSK 0xffffffff
+#define TX_ON_DEMAND_LENGTH_I_MSK 0x00000000
+#define TX_ON_DEMAND_LENGTH_SFT 0
+#define TX_ON_DEMAND_LENGTH_HI 31
+#define TX_ON_DEMAND_LENGTH_SZ 32
+#define HCI_MONITOR_REG1_MSK 0xffffffff
+#define HCI_MONITOR_REG1_I_MSK 0x00000000
+#define HCI_MONITOR_REG1_SFT 0
+#define HCI_MONITOR_REG1_HI 31
+#define HCI_MONITOR_REG1_SZ 32
+#define HCI_MONITOR_REG2_MSK 0xffffffff
+#define HCI_MONITOR_REG2_I_MSK 0x00000000
+#define HCI_MONITOR_REG2_SFT 0
+#define HCI_MONITOR_REG2_HI 31
+#define HCI_MONITOR_REG2_SZ 32
+#define HCI_TX_ALLOC_TIME_31_0_MSK 0xffffffff
+#define HCI_TX_ALLOC_TIME_31_0_I_MSK 0x00000000
+#define HCI_TX_ALLOC_TIME_31_0_SFT 0
+#define HCI_TX_ALLOC_TIME_31_0_HI 31
+#define HCI_TX_ALLOC_TIME_31_0_SZ 32
+#define HCI_TX_ALLOC_TIME_47_32_MSK 0x0000ffff
+#define HCI_TX_ALLOC_TIME_47_32_I_MSK 0xffff0000
+#define HCI_TX_ALLOC_TIME_47_32_SFT 0
+#define HCI_TX_ALLOC_TIME_47_32_HI 15
+#define HCI_TX_ALLOC_TIME_47_32_SZ 16
+#define HCI_MB_MAX_CNT_MSK 0x00ff0000
+#define HCI_MB_MAX_CNT_I_MSK 0xff00ffff
+#define HCI_MB_MAX_CNT_SFT 16
+#define HCI_MB_MAX_CNT_HI 23
+#define HCI_MB_MAX_CNT_SZ 8
+#define HCI_TX_ALLOC_CNT_31_0_MSK 0xffffffff
+#define HCI_TX_ALLOC_CNT_31_0_I_MSK 0x00000000
+#define HCI_TX_ALLOC_CNT_31_0_SFT 0
+#define HCI_TX_ALLOC_CNT_31_0_HI 31
+#define HCI_TX_ALLOC_CNT_31_0_SZ 32
+#define HCI_TX_ALLOC_CNT_47_32_MSK 0x0000ffff
+#define HCI_TX_ALLOC_CNT_47_32_I_MSK 0xffff0000
+#define HCI_TX_ALLOC_CNT_47_32_SFT 0
+#define HCI_TX_ALLOC_CNT_47_32_HI 15
+#define HCI_TX_ALLOC_CNT_47_32_SZ 16
+#define HCI_PROC_CNT_MSK 0x00ff0000
+#define HCI_PROC_CNT_I_MSK 0xff00ffff
+#define HCI_PROC_CNT_SFT 16
+#define HCI_PROC_CNT_HI 23
+#define HCI_PROC_CNT_SZ 8
+#define SDIO_TRANS_CNT_MSK 0xff000000
+#define SDIO_TRANS_CNT_I_MSK 0x00ffffff
+#define SDIO_TRANS_CNT_SFT 24
+#define SDIO_TRANS_CNT_HI 31
+#define SDIO_TRANS_CNT_SZ 8
+#define SDIO_TX_INVALID_CNT_31_0_MSK 0xffffffff
+#define SDIO_TX_INVALID_CNT_31_0_I_MSK 0x00000000
+#define SDIO_TX_INVALID_CNT_31_0_SFT 0
+#define SDIO_TX_INVALID_CNT_31_0_HI 31
+#define SDIO_TX_INVALID_CNT_31_0_SZ 32
+#define SDIO_TX_INVALID_CNT_47_32_MSK 0x0000ffff
+#define SDIO_TX_INVALID_CNT_47_32_I_MSK 0xffff0000
+#define SDIO_TX_INVALID_CNT_47_32_SFT 0
+#define SDIO_TX_INVALID_CNT_47_32_HI 15
+#define SDIO_TX_INVALID_CNT_47_32_SZ 16
+#define CS_START_ADDR_MSK 0x0000ffff
+#define CS_START_ADDR_I_MSK 0xffff0000
+#define CS_START_ADDR_SFT 0
+#define CS_START_ADDR_HI 15
+#define CS_START_ADDR_SZ 16
+#define CS_PKT_ID_MSK 0x007f0000
+#define CS_PKT_ID_I_MSK 0xff80ffff
+#define CS_PKT_ID_SFT 16
+#define CS_PKT_ID_HI 22
+#define CS_PKT_ID_SZ 7
+#define ADD_LEN_MSK 0x0000ffff
+#define ADD_LEN_I_MSK 0xffff0000
+#define ADD_LEN_SFT 0
+#define ADD_LEN_HI 15
+#define ADD_LEN_SZ 16
+#define CS_ADDER_EN_MSK 0x00000001
+#define CS_ADDER_EN_I_MSK 0xfffffffe
+#define CS_ADDER_EN_SFT 0
+#define CS_ADDER_EN_HI 0
+#define CS_ADDER_EN_SZ 1
+#define PSEUDO_MSK 0x00000002
+#define PSEUDO_I_MSK 0xfffffffd
+#define PSEUDO_SFT 1
+#define PSEUDO_HI 1
+#define PSEUDO_SZ 1
+#define CALCULATE_MSK 0xffffffff
+#define CALCULATE_I_MSK 0x00000000
+#define CALCULATE_SFT 0
+#define CALCULATE_HI 31
+#define CALCULATE_SZ 32
+#define L4_LEN_MSK 0x0000ffff
+#define L4_LEN_I_MSK 0xffff0000
+#define L4_LEN_SFT 0
+#define L4_LEN_HI 15
+#define L4_LEN_SZ 16
+#define L4_PROTOL_MSK 0x00ff0000
+#define L4_PROTOL_I_MSK 0xff00ffff
+#define L4_PROTOL_SFT 16
+#define L4_PROTOL_HI 23
+#define L4_PROTOL_SZ 8
+#define CHECK_SUM_MSK 0x0000ffff
+#define CHECK_SUM_I_MSK 0xffff0000
+#define CHECK_SUM_SFT 0
+#define CHECK_SUM_HI 15
+#define CHECK_SUM_SZ 16
+#define RAND_EN_MSK 0x00000001
+#define RAND_EN_I_MSK 0xfffffffe
+#define RAND_EN_SFT 0
+#define RAND_EN_HI 0
+#define RAND_EN_SZ 1
+#define RAND_NUM_MSK 0xffffffff
+#define RAND_NUM_I_MSK 0x00000000
+#define RAND_NUM_SFT 0
+#define RAND_NUM_HI 31
+#define RAND_NUM_SZ 32
+#define MUL_OP1_MSK 0xffffffff
+#define MUL_OP1_I_MSK 0x00000000
+#define MUL_OP1_SFT 0
+#define MUL_OP1_HI 31
+#define MUL_OP1_SZ 32
+#define MUL_OP2_MSK 0xffffffff
+#define MUL_OP2_I_MSK 0x00000000
+#define MUL_OP2_SFT 0
+#define MUL_OP2_HI 31
+#define MUL_OP2_SZ 32
+#define MUL_ANS0_MSK 0xffffffff
+#define MUL_ANS0_I_MSK 0x00000000
+#define MUL_ANS0_SFT 0
+#define MUL_ANS0_HI 31
+#define MUL_ANS0_SZ 32
+#define MUL_ANS1_MSK 0xffffffff
+#define MUL_ANS1_I_MSK 0x00000000
+#define MUL_ANS1_SFT 0
+#define MUL_ANS1_HI 31
+#define MUL_ANS1_SZ 32
+#define RD_ADDR_MSK 0x0000ffff
+#define RD_ADDR_I_MSK 0xffff0000
+#define RD_ADDR_SFT 0
+#define RD_ADDR_HI 15
+#define RD_ADDR_SZ 16
+#define RD_ID_MSK 0x007f0000
+#define RD_ID_I_MSK 0xff80ffff
+#define RD_ID_SFT 16
+#define RD_ID_HI 22
+#define RD_ID_SZ 7
+#define WR_ADDR_MSK 0x0000ffff
+#define WR_ADDR_I_MSK 0xffff0000
+#define WR_ADDR_SFT 0
+#define WR_ADDR_HI 15
+#define WR_ADDR_SZ 16
+#define WR_ID_MSK 0x007f0000
+#define WR_ID_I_MSK 0xff80ffff
+#define WR_ID_SFT 16
+#define WR_ID_HI 22
+#define WR_ID_SZ 7
+#define LEN_MSK 0x0000ffff
+#define LEN_I_MSK 0xffff0000
+#define LEN_SFT 0
+#define LEN_HI 15
+#define LEN_SZ 16
+#define CLR_MSK 0x00000001
+#define CLR_I_MSK 0xfffffffe
+#define CLR_SFT 0
+#define CLR_HI 0
+#define CLR_SZ 1
+#define PHY_MODE_MSK 0x00000003
+#define PHY_MODE_I_MSK 0xfffffffc
+#define PHY_MODE_SFT 0
+#define PHY_MODE_HI 1
+#define PHY_MODE_SZ 2
+#define SHRT_PREAM_MSK 0x00000004
+#define SHRT_PREAM_I_MSK 0xfffffffb
+#define SHRT_PREAM_SFT 2
+#define SHRT_PREAM_HI 2
+#define SHRT_PREAM_SZ 1
+#define SHRT_GI_MSK 0x00000008
+#define SHRT_GI_I_MSK 0xfffffff7
+#define SHRT_GI_SFT 3
+#define SHRT_GI_HI 3
+#define SHRT_GI_SZ 1
+#define DATA_RATE_MSK 0x000007f0
+#define DATA_RATE_I_MSK 0xfffff80f
+#define DATA_RATE_SFT 4
+#define DATA_RATE_HI 10
+#define DATA_RATE_SZ 7
+#define MCS_MSK 0x00007000
+#define MCS_I_MSK 0xffff8fff
+#define MCS_SFT 12
+#define MCS_HI 14
+#define MCS_SZ 3
+#define FRAME_LEN_MSK 0xffff0000
+#define FRAME_LEN_I_MSK 0x0000ffff
+#define FRAME_LEN_SFT 16
+#define FRAME_LEN_HI 31
+#define FRAME_LEN_SZ 16
+#define DURATION_MSK 0x0000ffff
+#define DURATION_I_MSK 0xffff0000
+#define DURATION_SFT 0
+#define DURATION_HI 15
+#define DURATION_SZ 16
+#define SHA_DST_ADDR_MSK 0xffffffff
+#define SHA_DST_ADDR_I_MSK 0x00000000
+#define SHA_DST_ADDR_SFT 0
+#define SHA_DST_ADDR_HI 31
+#define SHA_DST_ADDR_SZ 32
+#define SHA_SRC_ADDR_MSK 0xffffffff
+#define SHA_SRC_ADDR_I_MSK 0x00000000
+#define SHA_SRC_ADDR_SFT 0
+#define SHA_SRC_ADDR_HI 31
+#define SHA_SRC_ADDR_SZ 32
+#define SHA_BUSY_MSK 0x00000001
+#define SHA_BUSY_I_MSK 0xfffffffe
+#define SHA_BUSY_SFT 0
+#define SHA_BUSY_HI 0
+#define SHA_BUSY_SZ 1
+#define SHA_ENDIAN_MSK 0x00000002
+#define SHA_ENDIAN_I_MSK 0xfffffffd
+#define SHA_ENDIAN_SFT 1
+#define SHA_ENDIAN_HI 1
+#define SHA_ENDIAN_SZ 1
+#define EFS_CLKFREQ_MSK 0x00000fff
+#define EFS_CLKFREQ_I_MSK 0xfffff000
+#define EFS_CLKFREQ_SFT 0
+#define EFS_CLKFREQ_HI 11
+#define EFS_CLKFREQ_SZ 12
+#define LOW_ACTIVE_MSK 0x00010000
+#define LOW_ACTIVE_I_MSK 0xfffeffff
+#define LOW_ACTIVE_SFT 16
+#define LOW_ACTIVE_HI 16
+#define LOW_ACTIVE_SZ 1
+#define EFS_CLKFREQ_RD_MSK 0x0ff00000
+#define EFS_CLKFREQ_RD_I_MSK 0xf00fffff
+#define EFS_CLKFREQ_RD_SFT 20
+#define EFS_CLKFREQ_RD_HI 27
+#define EFS_CLKFREQ_RD_SZ 8
+#define EFS_PRE_RD_MSK 0xf0000000
+#define EFS_PRE_RD_I_MSK 0x0fffffff
+#define EFS_PRE_RD_SFT 28
+#define EFS_PRE_RD_HI 31
+#define EFS_PRE_RD_SZ 4
+#define EFS_LDO_ON_MSK 0x0000ffff
+#define EFS_LDO_ON_I_MSK 0xffff0000
+#define EFS_LDO_ON_SFT 0
+#define EFS_LDO_ON_HI 15
+#define EFS_LDO_ON_SZ 16
+#define EFS_LDO_OFF_MSK 0xffff0000
+#define EFS_LDO_OFF_I_MSK 0x0000ffff
+#define EFS_LDO_OFF_SFT 16
+#define EFS_LDO_OFF_HI 31
+#define EFS_LDO_OFF_SZ 16
+#define EFS_RDATA_0_MSK 0xffffffff
+#define EFS_RDATA_0_I_MSK 0x00000000
+#define EFS_RDATA_0_SFT 0
+#define EFS_RDATA_0_HI 31
+#define EFS_RDATA_0_SZ 32
+#define EFS_WDATA_0_MSK 0xffffffff
+#define EFS_WDATA_0_I_MSK 0x00000000
+#define EFS_WDATA_0_SFT 0
+#define EFS_WDATA_0_HI 31
+#define EFS_WDATA_0_SZ 32
+#define EFS_RDATA_1_MSK 0xffffffff
+#define EFS_RDATA_1_I_MSK 0x00000000
+#define EFS_RDATA_1_SFT 0
+#define EFS_RDATA_1_HI 31
+#define EFS_RDATA_1_SZ 32
+#define EFS_WDATA_1_MSK 0xffffffff
+#define EFS_WDATA_1_I_MSK 0x00000000
+#define EFS_WDATA_1_SFT 0
+#define EFS_WDATA_1_HI 31
+#define EFS_WDATA_1_SZ 32
+#define EFS_RDATA_2_MSK 0xffffffff
+#define EFS_RDATA_2_I_MSK 0x00000000
+#define EFS_RDATA_2_SFT 0
+#define EFS_RDATA_2_HI 31
+#define EFS_RDATA_2_SZ 32
+#define EFS_WDATA_2_MSK 0xffffffff
+#define EFS_WDATA_2_I_MSK 0x00000000
+#define EFS_WDATA_2_SFT 0
+#define EFS_WDATA_2_HI 31
+#define EFS_WDATA_2_SZ 32
+#define EFS_RDATA_3_MSK 0xffffffff
+#define EFS_RDATA_3_I_MSK 0x00000000
+#define EFS_RDATA_3_SFT 0
+#define EFS_RDATA_3_HI 31
+#define EFS_RDATA_3_SZ 32
+#define EFS_WDATA_3_MSK 0xffffffff
+#define EFS_WDATA_3_I_MSK 0x00000000
+#define EFS_WDATA_3_SFT 0
+#define EFS_WDATA_3_HI 31
+#define EFS_WDATA_3_SZ 32
+#define EFS_RDATA_4_MSK 0xffffffff
+#define EFS_RDATA_4_I_MSK 0x00000000
+#define EFS_RDATA_4_SFT 0
+#define EFS_RDATA_4_HI 31
+#define EFS_RDATA_4_SZ 32
+#define EFS_WDATA_4_MSK 0xffffffff
+#define EFS_WDATA_4_I_MSK 0x00000000
+#define EFS_WDATA_4_SFT 0
+#define EFS_WDATA_4_HI 31
+#define EFS_WDATA_4_SZ 32
+#define EFS_RDATA_5_MSK 0xffffffff
+#define EFS_RDATA_5_I_MSK 0x00000000
+#define EFS_RDATA_5_SFT 0
+#define EFS_RDATA_5_HI 31
+#define EFS_RDATA_5_SZ 32
+#define EFS_WDATA_5_MSK 0xffffffff
+#define EFS_WDATA_5_I_MSK 0x00000000
+#define EFS_WDATA_5_SFT 0
+#define EFS_WDATA_5_HI 31
+#define EFS_WDATA_5_SZ 32
+#define EFS_RDATA_6_MSK 0xffffffff
+#define EFS_RDATA_6_I_MSK 0x00000000
+#define EFS_RDATA_6_SFT 0
+#define EFS_RDATA_6_HI 31
+#define EFS_RDATA_6_SZ 32
+#define EFS_WDATA_6_MSK 0xffffffff
+#define EFS_WDATA_6_I_MSK 0x00000000
+#define EFS_WDATA_6_SFT 0
+#define EFS_WDATA_6_HI 31
+#define EFS_WDATA_6_SZ 32
+#define EFS_RDATA_7_MSK 0xffffffff
+#define EFS_RDATA_7_I_MSK 0x00000000
+#define EFS_RDATA_7_SFT 0
+#define EFS_RDATA_7_HI 31
+#define EFS_RDATA_7_SZ 32
+#define EFS_WDATA_7_MSK 0xffffffff
+#define EFS_WDATA_7_I_MSK 0x00000000
+#define EFS_WDATA_7_SFT 0
+#define EFS_WDATA_7_HI 31
+#define EFS_WDATA_7_SZ 32
+#define EFS_SPI_RD0_EN_MSK 0x00000001
+#define EFS_SPI_RD0_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD0_EN_SFT 0
+#define EFS_SPI_RD0_EN_HI 0
+#define EFS_SPI_RD0_EN_SZ 1
+#define EFS_SPI_RD1_EN_MSK 0x00000001
+#define EFS_SPI_RD1_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD1_EN_SFT 0
+#define EFS_SPI_RD1_EN_HI 0
+#define EFS_SPI_RD1_EN_SZ 1
+#define EFS_SPI_RD2_EN_MSK 0x00000001
+#define EFS_SPI_RD2_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD2_EN_SFT 0
+#define EFS_SPI_RD2_EN_HI 0
+#define EFS_SPI_RD2_EN_SZ 1
+#define EFS_SPI_RD3_EN_MSK 0x00000001
+#define EFS_SPI_RD3_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD3_EN_SFT 0
+#define EFS_SPI_RD3_EN_HI 0
+#define EFS_SPI_RD3_EN_SZ 1
+#define EFS_SPI_RD4_EN_MSK 0x00000001
+#define EFS_SPI_RD4_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD4_EN_SFT 0
+#define EFS_SPI_RD4_EN_HI 0
+#define EFS_SPI_RD4_EN_SZ 1
+#define EFS_SPI_RD5_EN_MSK 0x00000001
+#define EFS_SPI_RD5_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD5_EN_SFT 0
+#define EFS_SPI_RD5_EN_HI 0
+#define EFS_SPI_RD5_EN_SZ 1
+#define EFS_SPI_RD6_EN_MSK 0x00000001
+#define EFS_SPI_RD6_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD6_EN_SFT 0
+#define EFS_SPI_RD6_EN_HI 0
+#define EFS_SPI_RD6_EN_SZ 1
+#define EFS_SPI_RD7_EN_MSK 0x00000001
+#define EFS_SPI_RD7_EN_I_MSK 0xfffffffe
+#define EFS_SPI_RD7_EN_SFT 0
+#define EFS_SPI_RD7_EN_HI 0
+#define EFS_SPI_RD7_EN_SZ 1
+#define EFS_SPI_RBUSY_MSK 0x00000001
+#define EFS_SPI_RBUSY_I_MSK 0xfffffffe
+#define EFS_SPI_RBUSY_SFT 0
+#define EFS_SPI_RBUSY_HI 0
+#define EFS_SPI_RBUSY_SZ 1
+#define EFS_SPI_RDATA_0_MSK 0xffffffff
+#define EFS_SPI_RDATA_0_I_MSK 0x00000000
+#define EFS_SPI_RDATA_0_SFT 0
+#define EFS_SPI_RDATA_0_HI 31
+#define EFS_SPI_RDATA_0_SZ 32
+#define EFS_SPI_RDATA_1_MSK 0xffffffff
+#define EFS_SPI_RDATA_1_I_MSK 0x00000000
+#define EFS_SPI_RDATA_1_SFT 0
+#define EFS_SPI_RDATA_1_HI 31
+#define EFS_SPI_RDATA_1_SZ 32
+#define EFS_SPI_RDATA_2_MSK 0xffffffff
+#define EFS_SPI_RDATA_2_I_MSK 0x00000000
+#define EFS_SPI_RDATA_2_SFT 0
+#define EFS_SPI_RDATA_2_HI 31
+#define EFS_SPI_RDATA_2_SZ 32
+#define EFS_SPI_RDATA_3_MSK 0xffffffff
+#define EFS_SPI_RDATA_3_I_MSK 0x00000000
+#define EFS_SPI_RDATA_3_SFT 0
+#define EFS_SPI_RDATA_3_HI 31
+#define EFS_SPI_RDATA_3_SZ 32
+#define EFS_SPI_RDATA_4_MSK 0xffffffff
+#define EFS_SPI_RDATA_4_I_MSK 0x00000000
+#define EFS_SPI_RDATA_4_SFT 0
+#define EFS_SPI_RDATA_4_HI 31
+#define EFS_SPI_RDATA_4_SZ 32
+#define EFS_SPI_RDATA_5_MSK 0xffffffff
+#define EFS_SPI_RDATA_5_I_MSK 0x00000000
+#define EFS_SPI_RDATA_5_SFT 0
+#define EFS_SPI_RDATA_5_HI 31
+#define EFS_SPI_RDATA_5_SZ 32
+#define EFS_SPI_RDATA_6_MSK 0xffffffff
+#define EFS_SPI_RDATA_6_I_MSK 0x00000000
+#define EFS_SPI_RDATA_6_SFT 0
+#define EFS_SPI_RDATA_6_HI 31
+#define EFS_SPI_RDATA_6_SZ 32
+#define EFS_SPI_RDATA_7_MSK 0xffffffff
+#define EFS_SPI_RDATA_7_I_MSK 0x00000000
+#define EFS_SPI_RDATA_7_SFT 0
+#define EFS_SPI_RDATA_7_HI 31
+#define EFS_SPI_RDATA_7_SZ 32
+#define GET_RK_MSK 0x00000001
+#define GET_RK_I_MSK 0xfffffffe
+#define GET_RK_SFT 0
+#define GET_RK_HI 0
+#define GET_RK_SZ 1
+#define FORCE_GET_RK_MSK 0x00000002
+#define FORCE_GET_RK_I_MSK 0xfffffffd
+#define FORCE_GET_RK_SFT 1
+#define FORCE_GET_RK_HI 1
+#define FORCE_GET_RK_SZ 1
+#define SMS4_DESCRY_EN_MSK 0x00000010
+#define SMS4_DESCRY_EN_I_MSK 0xffffffef
+#define SMS4_DESCRY_EN_SFT 4
+#define SMS4_DESCRY_EN_HI 4
+#define SMS4_DESCRY_EN_SZ 1
+#define DEC_DOUT_MSB_MSK 0x00000001
+#define DEC_DOUT_MSB_I_MSK 0xfffffffe
+#define DEC_DOUT_MSB_SFT 0
+#define DEC_DOUT_MSB_HI 0
+#define DEC_DOUT_MSB_SZ 1
+#define DEC_DIN_MSB_MSK 0x00000002
+#define DEC_DIN_MSB_I_MSK 0xfffffffd
+#define DEC_DIN_MSB_SFT 1
+#define DEC_DIN_MSB_HI 1
+#define DEC_DIN_MSB_SZ 1
+#define ENC_DOUT_MSB_MSK 0x00000004
+#define ENC_DOUT_MSB_I_MSK 0xfffffffb
+#define ENC_DOUT_MSB_SFT 2
+#define ENC_DOUT_MSB_HI 2
+#define ENC_DOUT_MSB_SZ 1
+#define ENC_DIN_MSB_MSK 0x00000008
+#define ENC_DIN_MSB_I_MSK 0xfffffff7
+#define ENC_DIN_MSB_SFT 3
+#define ENC_DIN_MSB_HI 3
+#define ENC_DIN_MSB_SZ 1
+#define KEY_DIN_MSB_MSK 0x00000010
+#define KEY_DIN_MSB_I_MSK 0xffffffef
+#define KEY_DIN_MSB_SFT 4
+#define KEY_DIN_MSB_HI 4
+#define KEY_DIN_MSB_SZ 1
+#define SMS4_CBC_EN_MSK 0x00000001
+#define SMS4_CBC_EN_I_MSK 0xfffffffe
+#define SMS4_CBC_EN_SFT 0
+#define SMS4_CBC_EN_HI 0
+#define SMS4_CBC_EN_SZ 1
+#define SMS4_CFB_EN_MSK 0x00000002
+#define SMS4_CFB_EN_I_MSK 0xfffffffd
+#define SMS4_CFB_EN_SFT 1
+#define SMS4_CFB_EN_HI 1
+#define SMS4_CFB_EN_SZ 1
+#define SMS4_OFB_EN_MSK 0x00000004
+#define SMS4_OFB_EN_I_MSK 0xfffffffb
+#define SMS4_OFB_EN_SFT 2
+#define SMS4_OFB_EN_HI 2
+#define SMS4_OFB_EN_SZ 1
+#define SMS4_START_TRIG_MSK 0x00000001
+#define SMS4_START_TRIG_I_MSK 0xfffffffe
+#define SMS4_START_TRIG_SFT 0
+#define SMS4_START_TRIG_HI 0
+#define SMS4_START_TRIG_SZ 1
+#define SMS4_BUSY_MSK 0x00000001
+#define SMS4_BUSY_I_MSK 0xfffffffe
+#define SMS4_BUSY_SFT 0
+#define SMS4_BUSY_HI 0
+#define SMS4_BUSY_SZ 1
+#define SMS4_DONE_MSK 0x00000001
+#define SMS4_DONE_I_MSK 0xfffffffe
+#define SMS4_DONE_SFT 0
+#define SMS4_DONE_HI 0
+#define SMS4_DONE_SZ 1
+#define SMS4_DATAIN_0_MSK 0xffffffff
+#define SMS4_DATAIN_0_I_MSK 0x00000000
+#define SMS4_DATAIN_0_SFT 0
+#define SMS4_DATAIN_0_HI 31
+#define SMS4_DATAIN_0_SZ 32
+#define SMS4_DATAIN_1_MSK 0xffffffff
+#define SMS4_DATAIN_1_I_MSK 0x00000000
+#define SMS4_DATAIN_1_SFT 0
+#define SMS4_DATAIN_1_HI 31
+#define SMS4_DATAIN_1_SZ 32
+#define SMS4_DATAIN_2_MSK 0xffffffff
+#define SMS4_DATAIN_2_I_MSK 0x00000000
+#define SMS4_DATAIN_2_SFT 0
+#define SMS4_DATAIN_2_HI 31
+#define SMS4_DATAIN_2_SZ 32
+#define SMS4_DATAIN_3_MSK 0xffffffff
+#define SMS4_DATAIN_3_I_MSK 0x00000000
+#define SMS4_DATAIN_3_SFT 0
+#define SMS4_DATAIN_3_HI 31
+#define SMS4_DATAIN_3_SZ 32
+#define SMS4_DATAOUT_0_MSK 0xffffffff
+#define SMS4_DATAOUT_0_I_MSK 0x00000000
+#define SMS4_DATAOUT_0_SFT 0
+#define SMS4_DATAOUT_0_HI 31
+#define SMS4_DATAOUT_0_SZ 32
+#define SMS4_DATAOUT_1_MSK 0xffffffff
+#define SMS4_DATAOUT_1_I_MSK 0x00000000
+#define SMS4_DATAOUT_1_SFT 0
+#define SMS4_DATAOUT_1_HI 31
+#define SMS4_DATAOUT_1_SZ 32
+#define SMS4_DATAOUT_2_MSK 0xffffffff
+#define SMS4_DATAOUT_2_I_MSK 0x00000000
+#define SMS4_DATAOUT_2_SFT 0
+#define SMS4_DATAOUT_2_HI 31
+#define SMS4_DATAOUT_2_SZ 32
+#define SMS4_DATAOUT_3_MSK 0xffffffff
+#define SMS4_DATAOUT_3_I_MSK 0x00000000
+#define SMS4_DATAOUT_3_SFT 0
+#define SMS4_DATAOUT_3_HI 31
+#define SMS4_DATAOUT_3_SZ 32
+#define SMS4_KEY_0_MSK 0xffffffff
+#define SMS4_KEY_0_I_MSK 0x00000000
+#define SMS4_KEY_0_SFT 0
+#define SMS4_KEY_0_HI 31
+#define SMS4_KEY_0_SZ 32
+#define SMS4_KEY_1_MSK 0xffffffff
+#define SMS4_KEY_1_I_MSK 0x00000000
+#define SMS4_KEY_1_SFT 0
+#define SMS4_KEY_1_HI 31
+#define SMS4_KEY_1_SZ 32
+#define SMS4_KEY_2_MSK 0xffffffff
+#define SMS4_KEY_2_I_MSK 0x00000000
+#define SMS4_KEY_2_SFT 0
+#define SMS4_KEY_2_HI 31
+#define SMS4_KEY_2_SZ 32
+#define SMS4_KEY_3_MSK 0xffffffff
+#define SMS4_KEY_3_I_MSK 0x00000000
+#define SMS4_KEY_3_SFT 0
+#define SMS4_KEY_3_HI 31
+#define SMS4_KEY_3_SZ 32
+#define SMS4_MODE_IV0_MSK 0xffffffff
+#define SMS4_MODE_IV0_I_MSK 0x00000000
+#define SMS4_MODE_IV0_SFT 0
+#define SMS4_MODE_IV0_HI 31
+#define SMS4_MODE_IV0_SZ 32
+#define SMS4_MODE_IV1_MSK 0xffffffff
+#define SMS4_MODE_IV1_I_MSK 0x00000000
+#define SMS4_MODE_IV1_SFT 0
+#define SMS4_MODE_IV1_HI 31
+#define SMS4_MODE_IV1_SZ 32
+#define SMS4_MODE_IV2_MSK 0xffffffff
+#define SMS4_MODE_IV2_I_MSK 0x00000000
+#define SMS4_MODE_IV2_SFT 0
+#define SMS4_MODE_IV2_HI 31
+#define SMS4_MODE_IV2_SZ 32
+#define SMS4_MODE_IV3_MSK 0xffffffff
+#define SMS4_MODE_IV3_I_MSK 0x00000000
+#define SMS4_MODE_IV3_SFT 0
+#define SMS4_MODE_IV3_HI 31
+#define SMS4_MODE_IV3_SZ 32
+#define SMS4_OFB_ENC0_MSK 0xffffffff
+#define SMS4_OFB_ENC0_I_MSK 0x00000000
+#define SMS4_OFB_ENC0_SFT 0
+#define SMS4_OFB_ENC0_HI 31
+#define SMS4_OFB_ENC0_SZ 32
+#define SMS4_OFB_ENC1_MSK 0xffffffff
+#define SMS4_OFB_ENC1_I_MSK 0x00000000
+#define SMS4_OFB_ENC1_SFT 0
+#define SMS4_OFB_ENC1_HI 31
+#define SMS4_OFB_ENC1_SZ 32
+#define SMS4_OFB_ENC2_MSK 0xffffffff
+#define SMS4_OFB_ENC2_I_MSK 0x00000000
+#define SMS4_OFB_ENC2_SFT 0
+#define SMS4_OFB_ENC2_HI 31
+#define SMS4_OFB_ENC2_SZ 32
+#define SMS4_OFB_ENC3_MSK 0xffffffff
+#define SMS4_OFB_ENC3_I_MSK 0x00000000
+#define SMS4_OFB_ENC3_SFT 0
+#define SMS4_OFB_ENC3_HI 31
+#define SMS4_OFB_ENC3_SZ 32
+#define MRX_MCAST_TB0_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB0_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB0_31_0_SFT 0
+#define MRX_MCAST_TB0_31_0_HI 31
+#define MRX_MCAST_TB0_31_0_SZ 32
+#define MRX_MCAST_TB0_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB0_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB0_47_32_SFT 0
+#define MRX_MCAST_TB0_47_32_HI 15
+#define MRX_MCAST_TB0_47_32_SZ 16
+#define MRX_MCAST_MASK0_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK0_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK0_31_0_SFT 0
+#define MRX_MCAST_MASK0_31_0_HI 31
+#define MRX_MCAST_MASK0_31_0_SZ 32
+#define MRX_MCAST_MASK0_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK0_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK0_47_32_SFT 0
+#define MRX_MCAST_MASK0_47_32_HI 15
+#define MRX_MCAST_MASK0_47_32_SZ 16
+#define MRX_MCAST_CTRL_0_MSK 0x00000003
+#define MRX_MCAST_CTRL_0_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_0_SFT 0
+#define MRX_MCAST_CTRL_0_HI 1
+#define MRX_MCAST_CTRL_0_SZ 2
+#define MRX_MCAST_TB1_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB1_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB1_31_0_SFT 0
+#define MRX_MCAST_TB1_31_0_HI 31
+#define MRX_MCAST_TB1_31_0_SZ 32
+#define MRX_MCAST_TB1_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB1_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB1_47_32_SFT 0
+#define MRX_MCAST_TB1_47_32_HI 15
+#define MRX_MCAST_TB1_47_32_SZ 16
+#define MRX_MCAST_MASK1_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK1_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK1_31_0_SFT 0
+#define MRX_MCAST_MASK1_31_0_HI 31
+#define MRX_MCAST_MASK1_31_0_SZ 32
+#define MRX_MCAST_MASK1_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK1_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK1_47_32_SFT 0
+#define MRX_MCAST_MASK1_47_32_HI 15
+#define MRX_MCAST_MASK1_47_32_SZ 16
+#define MRX_MCAST_CTRL_1_MSK 0x00000003
+#define MRX_MCAST_CTRL_1_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_1_SFT 0
+#define MRX_MCAST_CTRL_1_HI 1
+#define MRX_MCAST_CTRL_1_SZ 2
+#define MRX_MCAST_TB2_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB2_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB2_31_0_SFT 0
+#define MRX_MCAST_TB2_31_0_HI 31
+#define MRX_MCAST_TB2_31_0_SZ 32
+#define MRX_MCAST_TB2_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB2_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB2_47_32_SFT 0
+#define MRX_MCAST_TB2_47_32_HI 15
+#define MRX_MCAST_TB2_47_32_SZ 16
+#define MRX_MCAST_MASK2_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK2_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK2_31_0_SFT 0
+#define MRX_MCAST_MASK2_31_0_HI 31
+#define MRX_MCAST_MASK2_31_0_SZ 32
+#define MRX_MCAST_MASK2_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK2_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK2_47_32_SFT 0
+#define MRX_MCAST_MASK2_47_32_HI 15
+#define MRX_MCAST_MASK2_47_32_SZ 16
+#define MRX_MCAST_CTRL_2_MSK 0x00000003
+#define MRX_MCAST_CTRL_2_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_2_SFT 0
+#define MRX_MCAST_CTRL_2_HI 1
+#define MRX_MCAST_CTRL_2_SZ 2
+#define MRX_MCAST_TB3_31_0_MSK 0xffffffff
+#define MRX_MCAST_TB3_31_0_I_MSK 0x00000000
+#define MRX_MCAST_TB3_31_0_SFT 0
+#define MRX_MCAST_TB3_31_0_HI 31
+#define MRX_MCAST_TB3_31_0_SZ 32
+#define MRX_MCAST_TB3_47_32_MSK 0x0000ffff
+#define MRX_MCAST_TB3_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_TB3_47_32_SFT 0
+#define MRX_MCAST_TB3_47_32_HI 15
+#define MRX_MCAST_TB3_47_32_SZ 16
+#define MRX_MCAST_MASK3_31_0_MSK 0xffffffff
+#define MRX_MCAST_MASK3_31_0_I_MSK 0x00000000
+#define MRX_MCAST_MASK3_31_0_SFT 0
+#define MRX_MCAST_MASK3_31_0_HI 31
+#define MRX_MCAST_MASK3_31_0_SZ 32
+#define MRX_MCAST_MASK3_47_32_MSK 0x0000ffff
+#define MRX_MCAST_MASK3_47_32_I_MSK 0xffff0000
+#define MRX_MCAST_MASK3_47_32_SFT 0
+#define MRX_MCAST_MASK3_47_32_HI 15
+#define MRX_MCAST_MASK3_47_32_SZ 16
+#define MRX_MCAST_CTRL_3_MSK 0x00000003
+#define MRX_MCAST_CTRL_3_I_MSK 0xfffffffc
+#define MRX_MCAST_CTRL_3_SFT 0
+#define MRX_MCAST_CTRL_3_HI 1
+#define MRX_MCAST_CTRL_3_SZ 2
+#define MRX_PHY_INFO_MSK 0xffffffff
+#define MRX_PHY_INFO_I_MSK 0x00000000
+#define MRX_PHY_INFO_SFT 0
+#define MRX_PHY_INFO_HI 31
+#define MRX_PHY_INFO_SZ 32
+#define DBG_BA_TYPE_MSK 0x0000003f
+#define DBG_BA_TYPE_I_MSK 0xffffffc0
+#define DBG_BA_TYPE_SFT 0
+#define DBG_BA_TYPE_HI 5
+#define DBG_BA_TYPE_SZ 6
+#define DBG_BA_SEQ_MSK 0x000fff00
+#define DBG_BA_SEQ_I_MSK 0xfff000ff
+#define DBG_BA_SEQ_SFT 8
+#define DBG_BA_SEQ_HI 19
+#define DBG_BA_SEQ_SZ 12
+#define MRX_FLT_TB0_MSK 0x00007fff
+#define MRX_FLT_TB0_I_MSK 0xffff8000
+#define MRX_FLT_TB0_SFT 0
+#define MRX_FLT_TB0_HI 14
+#define MRX_FLT_TB0_SZ 15
+#define MRX_FLT_TB1_MSK 0x00007fff
+#define MRX_FLT_TB1_I_MSK 0xffff8000
+#define MRX_FLT_TB1_SFT 0
+#define MRX_FLT_TB1_HI 14
+#define MRX_FLT_TB1_SZ 15
+#define MRX_FLT_TB2_MSK 0x00007fff
+#define MRX_FLT_TB2_I_MSK 0xffff8000
+#define MRX_FLT_TB2_SFT 0
+#define MRX_FLT_TB2_HI 14
+#define MRX_FLT_TB2_SZ 15
+#define MRX_FLT_TB3_MSK 0x00007fff
+#define MRX_FLT_TB3_I_MSK 0xffff8000
+#define MRX_FLT_TB3_SFT 0
+#define MRX_FLT_TB3_HI 14
+#define MRX_FLT_TB3_SZ 15
+#define MRX_FLT_TB4_MSK 0x00007fff
+#define MRX_FLT_TB4_I_MSK 0xffff8000
+#define MRX_FLT_TB4_SFT 0
+#define MRX_FLT_TB4_HI 14
+#define MRX_FLT_TB4_SZ 15
+#define MRX_FLT_TB5_MSK 0x00007fff
+#define MRX_FLT_TB5_I_MSK 0xffff8000
+#define MRX_FLT_TB5_SFT 0
+#define MRX_FLT_TB5_HI 14
+#define MRX_FLT_TB5_SZ 15
+#define MRX_FLT_TB6_MSK 0x00007fff
+#define MRX_FLT_TB6_I_MSK 0xffff8000
+#define MRX_FLT_TB6_SFT 0
+#define MRX_FLT_TB6_HI 14
+#define MRX_FLT_TB6_SZ 15
+#define MRX_FLT_TB7_MSK 0x00007fff
+#define MRX_FLT_TB7_I_MSK 0xffff8000
+#define MRX_FLT_TB7_SFT 0
+#define MRX_FLT_TB7_HI 14
+#define MRX_FLT_TB7_SZ 15
+#define MRX_FLT_TB8_MSK 0x00007fff
+#define MRX_FLT_TB8_I_MSK 0xffff8000
+#define MRX_FLT_TB8_SFT 0
+#define MRX_FLT_TB8_HI 14
+#define MRX_FLT_TB8_SZ 15
+#define MRX_FLT_TB9_MSK 0x00007fff
+#define MRX_FLT_TB9_I_MSK 0xffff8000
+#define MRX_FLT_TB9_SFT 0
+#define MRX_FLT_TB9_HI 14
+#define MRX_FLT_TB9_SZ 15
+#define MRX_FLT_TB10_MSK 0x00007fff
+#define MRX_FLT_TB10_I_MSK 0xffff8000
+#define MRX_FLT_TB10_SFT 0
+#define MRX_FLT_TB10_HI 14
+#define MRX_FLT_TB10_SZ 15
+#define MRX_FLT_TB11_MSK 0x00007fff
+#define MRX_FLT_TB11_I_MSK 0xffff8000
+#define MRX_FLT_TB11_SFT 0
+#define MRX_FLT_TB11_HI 14
+#define MRX_FLT_TB11_SZ 15
+#define MRX_FLT_TB12_MSK 0x00007fff
+#define MRX_FLT_TB12_I_MSK 0xffff8000
+#define MRX_FLT_TB12_SFT 0
+#define MRX_FLT_TB12_HI 14
+#define MRX_FLT_TB12_SZ 15
+#define MRX_FLT_TB13_MSK 0x00007fff
+#define MRX_FLT_TB13_I_MSK 0xffff8000
+#define MRX_FLT_TB13_SFT 0
+#define MRX_FLT_TB13_HI 14
+#define MRX_FLT_TB13_SZ 15
+#define MRX_FLT_TB14_MSK 0x00007fff
+#define MRX_FLT_TB14_I_MSK 0xffff8000
+#define MRX_FLT_TB14_SFT 0
+#define MRX_FLT_TB14_HI 14
+#define MRX_FLT_TB14_SZ 15
+#define MRX_FLT_TB15_MSK 0x00007fff
+#define MRX_FLT_TB15_I_MSK 0xffff8000
+#define MRX_FLT_TB15_SFT 0
+#define MRX_FLT_TB15_HI 14
+#define MRX_FLT_TB15_SZ 15
+#define MRX_FLT_EN0_MSK 0x0000ffff
+#define MRX_FLT_EN0_I_MSK 0xffff0000
+#define MRX_FLT_EN0_SFT 0
+#define MRX_FLT_EN0_HI 15
+#define MRX_FLT_EN0_SZ 16
+#define MRX_FLT_EN1_MSK 0x0000ffff
+#define MRX_FLT_EN1_I_MSK 0xffff0000
+#define MRX_FLT_EN1_SFT 0
+#define MRX_FLT_EN1_HI 15
+#define MRX_FLT_EN1_SZ 16
+#define MRX_FLT_EN2_MSK 0x0000ffff
+#define MRX_FLT_EN2_I_MSK 0xffff0000
+#define MRX_FLT_EN2_SFT 0
+#define MRX_FLT_EN2_HI 15
+#define MRX_FLT_EN2_SZ 16
+#define MRX_FLT_EN3_MSK 0x0000ffff
+#define MRX_FLT_EN3_I_MSK 0xffff0000
+#define MRX_FLT_EN3_SFT 0
+#define MRX_FLT_EN3_HI 15
+#define MRX_FLT_EN3_SZ 16
+#define MRX_FLT_EN4_MSK 0x0000ffff
+#define MRX_FLT_EN4_I_MSK 0xffff0000
+#define MRX_FLT_EN4_SFT 0
+#define MRX_FLT_EN4_HI 15
+#define MRX_FLT_EN4_SZ 16
+#define MRX_FLT_EN5_MSK 0x0000ffff
+#define MRX_FLT_EN5_I_MSK 0xffff0000
+#define MRX_FLT_EN5_SFT 0
+#define MRX_FLT_EN5_HI 15
+#define MRX_FLT_EN5_SZ 16
+#define MRX_FLT_EN6_MSK 0x0000ffff
+#define MRX_FLT_EN6_I_MSK 0xffff0000
+#define MRX_FLT_EN6_SFT 0
+#define MRX_FLT_EN6_HI 15
+#define MRX_FLT_EN6_SZ 16
+#define MRX_FLT_EN7_MSK 0x0000ffff
+#define MRX_FLT_EN7_I_MSK 0xffff0000
+#define MRX_FLT_EN7_SFT 0
+#define MRX_FLT_EN7_HI 15
+#define MRX_FLT_EN7_SZ 16
+#define MRX_FLT_EN8_MSK 0x0000ffff
+#define MRX_FLT_EN8_I_MSK 0xffff0000
+#define MRX_FLT_EN8_SFT 0
+#define MRX_FLT_EN8_HI 15
+#define MRX_FLT_EN8_SZ 16
+#define MRX_LEN_FLT_MSK 0x0000ffff
+#define MRX_LEN_FLT_I_MSK 0xffff0000
+#define MRX_LEN_FLT_SFT 0
+#define MRX_LEN_FLT_HI 15
+#define MRX_LEN_FLT_SZ 16
+#define RX_FLOW_DATA_MSK 0xffffffff
+#define RX_FLOW_DATA_I_MSK 0x00000000
+#define RX_FLOW_DATA_SFT 0
+#define RX_FLOW_DATA_HI 31
+#define RX_FLOW_DATA_SZ 32
+#define RX_FLOW_MNG_MSK 0x0000ffff
+#define RX_FLOW_MNG_I_MSK 0xffff0000
+#define RX_FLOW_MNG_SFT 0
+#define RX_FLOW_MNG_HI 15
+#define RX_FLOW_MNG_SZ 16
+#define RX_FLOW_CTRL_MSK 0x0000ffff
+#define RX_FLOW_CTRL_I_MSK 0xffff0000
+#define RX_FLOW_CTRL_SFT 0
+#define RX_FLOW_CTRL_HI 15
+#define RX_FLOW_CTRL_SZ 16
+#define MRX_STP_EN_MSK 0x00000001
+#define MRX_STP_EN_I_MSK 0xfffffffe
+#define MRX_STP_EN_SFT 0
+#define MRX_STP_EN_HI 0
+#define MRX_STP_EN_SZ 1
+#define MRX_STP_OFST_MSK 0x0000ff00
+#define MRX_STP_OFST_I_MSK 0xffff00ff
+#define MRX_STP_OFST_SFT 8
+#define MRX_STP_OFST_HI 15
+#define MRX_STP_OFST_SZ 8
+#define DBG_FF_FULL_MSK 0x0000ffff
+#define DBG_FF_FULL_I_MSK 0xffff0000
+#define DBG_FF_FULL_SFT 0
+#define DBG_FF_FULL_HI 15
+#define DBG_FF_FULL_SZ 16
+#define DBG_FF_FULL_CLR_MSK 0x80000000
+#define DBG_FF_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_FF_FULL_CLR_SFT 31
+#define DBG_FF_FULL_CLR_HI 31
+#define DBG_FF_FULL_CLR_SZ 1
+#define DBG_WFF_FULL_MSK 0x0000ffff
+#define DBG_WFF_FULL_I_MSK 0xffff0000
+#define DBG_WFF_FULL_SFT 0
+#define DBG_WFF_FULL_HI 15
+#define DBG_WFF_FULL_SZ 16
+#define DBG_WFF_FULL_CLR_MSK 0x80000000
+#define DBG_WFF_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_WFF_FULL_CLR_SFT 31
+#define DBG_WFF_FULL_CLR_HI 31
+#define DBG_WFF_FULL_CLR_SZ 1
+#define DBG_MB_FULL_MSK 0x0000ffff
+#define DBG_MB_FULL_I_MSK 0xffff0000
+#define DBG_MB_FULL_SFT 0
+#define DBG_MB_FULL_HI 15
+#define DBG_MB_FULL_SZ 16
+#define DBG_MB_FULL_CLR_MSK 0x80000000
+#define DBG_MB_FULL_CLR_I_MSK 0x7fffffff
+#define DBG_MB_FULL_CLR_SFT 31
+#define DBG_MB_FULL_CLR_HI 31
+#define DBG_MB_FULL_CLR_SZ 1
+#define BA_CTRL_MSK 0x00000003
+#define BA_CTRL_I_MSK 0xfffffffc
+#define BA_CTRL_SFT 0
+#define BA_CTRL_HI 1
+#define BA_CTRL_SZ 2
+#define BA_DBG_EN_MSK 0x00000004
+#define BA_DBG_EN_I_MSK 0xfffffffb
+#define BA_DBG_EN_SFT 2
+#define BA_DBG_EN_HI 2
+#define BA_DBG_EN_SZ 1
+#define BA_AGRE_EN_MSK 0x00000008
+#define BA_AGRE_EN_I_MSK 0xfffffff7
+#define BA_AGRE_EN_SFT 3
+#define BA_AGRE_EN_HI 3
+#define BA_AGRE_EN_SZ 1
+#define BA_TA_31_0_MSK 0xffffffff
+#define BA_TA_31_0_I_MSK 0x00000000
+#define BA_TA_31_0_SFT 0
+#define BA_TA_31_0_HI 31
+#define BA_TA_31_0_SZ 32
+#define BA_TA_47_32_MSK 0x0000ffff
+#define BA_TA_47_32_I_MSK 0xffff0000
+#define BA_TA_47_32_SFT 0
+#define BA_TA_47_32_HI 15
+#define BA_TA_47_32_SZ 16
+#define BA_TID_MSK 0x0000000f
+#define BA_TID_I_MSK 0xfffffff0
+#define BA_TID_SFT 0
+#define BA_TID_HI 3
+#define BA_TID_SZ 4
+#define BA_ST_SEQ_MSK 0x00000fff
+#define BA_ST_SEQ_I_MSK 0xfffff000
+#define BA_ST_SEQ_SFT 0
+#define BA_ST_SEQ_HI 11
+#define BA_ST_SEQ_SZ 12
+#define BA_SB0_MSK 0xffffffff
+#define BA_SB0_I_MSK 0x00000000
+#define BA_SB0_SFT 0
+#define BA_SB0_HI 31
+#define BA_SB0_SZ 32
+#define BA_SB1_MSK 0xffffffff
+#define BA_SB1_I_MSK 0x00000000
+#define BA_SB1_SFT 0
+#define BA_SB1_HI 31
+#define BA_SB1_SZ 32
+#define MRX_WD_MSK 0x0001ffff
+#define MRX_WD_I_MSK 0xfffe0000
+#define MRX_WD_SFT 0
+#define MRX_WD_HI 16
+#define MRX_WD_SZ 17
+#define ACK_GEN_EN_MSK 0x00000001
+#define ACK_GEN_EN_I_MSK 0xfffffffe
+#define ACK_GEN_EN_SFT 0
+#define ACK_GEN_EN_HI 0
+#define ACK_GEN_EN_SZ 1
+#define BA_GEN_EN_MSK 0x00000002
+#define BA_GEN_EN_I_MSK 0xfffffffd
+#define BA_GEN_EN_SFT 1
+#define BA_GEN_EN_HI 1
+#define BA_GEN_EN_SZ 1
+#define ACK_GEN_DUR_MSK 0x0000ffff
+#define ACK_GEN_DUR_I_MSK 0xffff0000
+#define ACK_GEN_DUR_SFT 0
+#define ACK_GEN_DUR_HI 15
+#define ACK_GEN_DUR_SZ 16
+#define ACK_GEN_INFO_MSK 0x003f0000
+#define ACK_GEN_INFO_I_MSK 0xffc0ffff
+#define ACK_GEN_INFO_SFT 16
+#define ACK_GEN_INFO_HI 21
+#define ACK_GEN_INFO_SZ 6
+#define ACK_GEN_RA_31_0_MSK 0xffffffff
+#define ACK_GEN_RA_31_0_I_MSK 0x00000000
+#define ACK_GEN_RA_31_0_SFT 0
+#define ACK_GEN_RA_31_0_HI 31
+#define ACK_GEN_RA_31_0_SZ 32
+#define ACK_GEN_RA_47_32_MSK 0x0000ffff
+#define ACK_GEN_RA_47_32_I_MSK 0xffff0000
+#define ACK_GEN_RA_47_32_SFT 0
+#define ACK_GEN_RA_47_32_HI 15
+#define ACK_GEN_RA_47_32_SZ 16
+#define MIB_LEN_FAIL_MSK 0x0000ffff
+#define MIB_LEN_FAIL_I_MSK 0xffff0000
+#define MIB_LEN_FAIL_SFT 0
+#define MIB_LEN_FAIL_HI 15
+#define MIB_LEN_FAIL_SZ 16
+#define TRAP_HW_ID_MSK 0x0000000f
+#define TRAP_HW_ID_I_MSK 0xfffffff0
+#define TRAP_HW_ID_SFT 0
+#define TRAP_HW_ID_HI 3
+#define TRAP_HW_ID_SZ 4
+#define ID_IN_USE_MSK 0x000000ff
+#define ID_IN_USE_I_MSK 0xffffff00
+#define ID_IN_USE_SFT 0
+#define ID_IN_USE_HI 7
+#define ID_IN_USE_SZ 8
+#define MRX_ERR_MSK 0xffffffff
+#define MRX_ERR_I_MSK 0x00000000
+#define MRX_ERR_SFT 0
+#define MRX_ERR_HI 31
+#define MRX_ERR_SZ 32
+#define W0_T0_SEQ_MSK 0x0000ffff
+#define W0_T0_SEQ_I_MSK 0xffff0000
+#define W0_T0_SEQ_SFT 0
+#define W0_T0_SEQ_HI 15
+#define W0_T0_SEQ_SZ 16
+#define W0_T1_SEQ_MSK 0x0000ffff
+#define W0_T1_SEQ_I_MSK 0xffff0000
+#define W0_T1_SEQ_SFT 0
+#define W0_T1_SEQ_HI 15
+#define W0_T1_SEQ_SZ 16
+#define W0_T2_SEQ_MSK 0x0000ffff
+#define W0_T2_SEQ_I_MSK 0xffff0000
+#define W0_T2_SEQ_SFT 0
+#define W0_T2_SEQ_HI 15
+#define W0_T2_SEQ_SZ 16
+#define W0_T3_SEQ_MSK 0x0000ffff
+#define W0_T3_SEQ_I_MSK 0xffff0000
+#define W0_T3_SEQ_SFT 0
+#define W0_T3_SEQ_HI 15
+#define W0_T3_SEQ_SZ 16
+#define W0_T4_SEQ_MSK 0x0000ffff
+#define W0_T4_SEQ_I_MSK 0xffff0000
+#define W0_T4_SEQ_SFT 0
+#define W0_T4_SEQ_HI 15
+#define W0_T4_SEQ_SZ 16
+#define W0_T5_SEQ_MSK 0x0000ffff
+#define W0_T5_SEQ_I_MSK 0xffff0000
+#define W0_T5_SEQ_SFT 0
+#define W0_T5_SEQ_HI 15
+#define W0_T5_SEQ_SZ 16
+#define W0_T6_SEQ_MSK 0x0000ffff
+#define W0_T6_SEQ_I_MSK 0xffff0000
+#define W0_T6_SEQ_SFT 0
+#define W0_T6_SEQ_HI 15
+#define W0_T6_SEQ_SZ 16
+#define W0_T7_SEQ_MSK 0x0000ffff
+#define W0_T7_SEQ_I_MSK 0xffff0000
+#define W0_T7_SEQ_SFT 0
+#define W0_T7_SEQ_HI 15
+#define W0_T7_SEQ_SZ 16
+#define W1_T0_SEQ_MSK 0x0000ffff
+#define W1_T0_SEQ_I_MSK 0xffff0000
+#define W1_T0_SEQ_SFT 0
+#define W1_T0_SEQ_HI 15
+#define W1_T0_SEQ_SZ 16
+#define W1_T1_SEQ_MSK 0x0000ffff
+#define W1_T1_SEQ_I_MSK 0xffff0000
+#define W1_T1_SEQ_SFT 0
+#define W1_T1_SEQ_HI 15
+#define W1_T1_SEQ_SZ 16
+#define W1_T2_SEQ_MSK 0x0000ffff
+#define W1_T2_SEQ_I_MSK 0xffff0000
+#define W1_T2_SEQ_SFT 0
+#define W1_T2_SEQ_HI 15
+#define W1_T2_SEQ_SZ 16
+#define W1_T3_SEQ_MSK 0x0000ffff
+#define W1_T3_SEQ_I_MSK 0xffff0000
+#define W1_T3_SEQ_SFT 0
+#define W1_T3_SEQ_HI 15
+#define W1_T3_SEQ_SZ 16
+#define W1_T4_SEQ_MSK 0x0000ffff
+#define W1_T4_SEQ_I_MSK 0xffff0000
+#define W1_T4_SEQ_SFT 0
+#define W1_T4_SEQ_HI 15
+#define W1_T4_SEQ_SZ 16
+#define W1_T5_SEQ_MSK 0x0000ffff
+#define W1_T5_SEQ_I_MSK 0xffff0000
+#define W1_T5_SEQ_SFT 0
+#define W1_T5_SEQ_HI 15
+#define W1_T5_SEQ_SZ 16
+#define W1_T6_SEQ_MSK 0x0000ffff
+#define W1_T6_SEQ_I_MSK 0xffff0000
+#define W1_T6_SEQ_SFT 0
+#define W1_T6_SEQ_HI 15
+#define W1_T6_SEQ_SZ 16
+#define W1_T7_SEQ_MSK 0x0000ffff
+#define W1_T7_SEQ_I_MSK 0xffff0000
+#define W1_T7_SEQ_SFT 0
+#define W1_T7_SEQ_HI 15
+#define W1_T7_SEQ_SZ 16
+#define ADDR1A_SEL_MSK 0x00000003
+#define ADDR1A_SEL_I_MSK 0xfffffffc
+#define ADDR1A_SEL_SFT 0
+#define ADDR1A_SEL_HI 1
+#define ADDR1A_SEL_SZ 2
+#define ADDR2A_SEL_MSK 0x0000000c
+#define ADDR2A_SEL_I_MSK 0xfffffff3
+#define ADDR2A_SEL_SFT 2
+#define ADDR2A_SEL_HI 3
+#define ADDR2A_SEL_SZ 2
+#define ADDR3A_SEL_MSK 0x00000030
+#define ADDR3A_SEL_I_MSK 0xffffffcf
+#define ADDR3A_SEL_SFT 4
+#define ADDR3A_SEL_HI 5
+#define ADDR3A_SEL_SZ 2
+#define ADDR1B_SEL_MSK 0x000000c0
+#define ADDR1B_SEL_I_MSK 0xffffff3f
+#define ADDR1B_SEL_SFT 6
+#define ADDR1B_SEL_HI 7
+#define ADDR1B_SEL_SZ 2
+#define ADDR2B_SEL_MSK 0x00000300
+#define ADDR2B_SEL_I_MSK 0xfffffcff
+#define ADDR2B_SEL_SFT 8
+#define ADDR2B_SEL_HI 9
+#define ADDR2B_SEL_SZ 2
+#define ADDR3B_SEL_MSK 0x00000c00
+#define ADDR3B_SEL_I_MSK 0xfffff3ff
+#define ADDR3B_SEL_SFT 10
+#define ADDR3B_SEL_HI 11
+#define ADDR3B_SEL_SZ 2
+#define ADDR3C_SEL_MSK 0x00003000
+#define ADDR3C_SEL_I_MSK 0xffffcfff
+#define ADDR3C_SEL_SFT 12
+#define ADDR3C_SEL_HI 13
+#define ADDR3C_SEL_SZ 2
+#define FRM_CTRL_MSK 0x0000003f
+#define FRM_CTRL_I_MSK 0xffffffc0
+#define FRM_CTRL_SFT 0
+#define FRM_CTRL_HI 5
+#define FRM_CTRL_SZ 6
+#define CSR_PHY_INFO_MSK 0x00007fff
+#define CSR_PHY_INFO_I_MSK 0xffff8000
+#define CSR_PHY_INFO_SFT 0
+#define CSR_PHY_INFO_HI 14
+#define CSR_PHY_INFO_SZ 15
+#define AMPDU_SIG_MSK 0x000000ff
+#define AMPDU_SIG_I_MSK 0xffffff00
+#define AMPDU_SIG_SFT 0
+#define AMPDU_SIG_HI 7
+#define AMPDU_SIG_SZ 8
+#define MIB_AMPDU_MSK 0xffffffff
+#define MIB_AMPDU_I_MSK 0x00000000
+#define MIB_AMPDU_SFT 0
+#define MIB_AMPDU_HI 31
+#define MIB_AMPDU_SZ 32
+#define LEN_FLT_MSK 0x0000ffff
+#define LEN_FLT_I_MSK 0xffff0000
+#define LEN_FLT_SFT 0
+#define LEN_FLT_HI 15
+#define LEN_FLT_SZ 16
+#define MIB_DELIMITER_MSK 0x0000ffff
+#define MIB_DELIMITER_I_MSK 0xffff0000
+#define MIB_DELIMITER_SFT 0
+#define MIB_DELIMITER_HI 15
+#define MIB_DELIMITER_SZ 16
+#define MTX_INT_Q0_Q_EMPTY_MSK 0x00010000
+#define MTX_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
+#define MTX_INT_Q0_Q_EMPTY_SFT 16
+#define MTX_INT_Q0_Q_EMPTY_HI 16
+#define MTX_INT_Q0_Q_EMPTY_SZ 1
+#define MTX_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
+#define MTX_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
+#define MTX_INT_Q0_TXOP_RUNOUT_SFT 17
+#define MTX_INT_Q0_TXOP_RUNOUT_HI 17
+#define MTX_INT_Q0_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q1_Q_EMPTY_MSK 0x00040000
+#define MTX_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
+#define MTX_INT_Q1_Q_EMPTY_SFT 18
+#define MTX_INT_Q1_Q_EMPTY_HI 18
+#define MTX_INT_Q1_Q_EMPTY_SZ 1
+#define MTX_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
+#define MTX_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
+#define MTX_INT_Q1_TXOP_RUNOUT_SFT 19
+#define MTX_INT_Q1_TXOP_RUNOUT_HI 19
+#define MTX_INT_Q1_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q2_Q_EMPTY_MSK 0x00100000
+#define MTX_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
+#define MTX_INT_Q2_Q_EMPTY_SFT 20
+#define MTX_INT_Q2_Q_EMPTY_HI 20
+#define MTX_INT_Q2_Q_EMPTY_SZ 1
+#define MTX_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
+#define MTX_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
+#define MTX_INT_Q2_TXOP_RUNOUT_SFT 21
+#define MTX_INT_Q2_TXOP_RUNOUT_HI 21
+#define MTX_INT_Q2_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q3_Q_EMPTY_MSK 0x00400000
+#define MTX_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
+#define MTX_INT_Q3_Q_EMPTY_SFT 22
+#define MTX_INT_Q3_Q_EMPTY_HI 22
+#define MTX_INT_Q3_Q_EMPTY_SZ 1
+#define MTX_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
+#define MTX_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
+#define MTX_INT_Q3_TXOP_RUNOUT_SFT 23
+#define MTX_INT_Q3_TXOP_RUNOUT_HI 23
+#define MTX_INT_Q3_TXOP_RUNOUT_SZ 1
+#define MTX_INT_Q4_Q_EMPTY_MSK 0x01000000
+#define MTX_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
+#define MTX_INT_Q4_Q_EMPTY_SFT 24
+#define MTX_INT_Q4_Q_EMPTY_HI 24
+#define MTX_INT_Q4_Q_EMPTY_SZ 1
+#define MTX_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
+#define MTX_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
+#define MTX_INT_Q4_TXOP_RUNOUT_SFT 25
+#define MTX_INT_Q4_TXOP_RUNOUT_HI 25
+#define MTX_INT_Q4_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q0_Q_EMPTY_MSK 0x00010000
+#define MTX_EN_INT_Q0_Q_EMPTY_I_MSK 0xfffeffff
+#define MTX_EN_INT_Q0_Q_EMPTY_SFT 16
+#define MTX_EN_INT_Q0_Q_EMPTY_HI 16
+#define MTX_EN_INT_Q0_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_MSK 0x00020000
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_I_MSK 0xfffdffff
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_SFT 17
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_HI 17
+#define MTX_EN_INT_Q0_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q1_Q_EMPTY_MSK 0x00040000
+#define MTX_EN_INT_Q1_Q_EMPTY_I_MSK 0xfffbffff
+#define MTX_EN_INT_Q1_Q_EMPTY_SFT 18
+#define MTX_EN_INT_Q1_Q_EMPTY_HI 18
+#define MTX_EN_INT_Q1_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_MSK 0x00080000
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_I_MSK 0xfff7ffff
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_SFT 19
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_HI 19
+#define MTX_EN_INT_Q1_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q2_Q_EMPTY_MSK 0x00100000
+#define MTX_EN_INT_Q2_Q_EMPTY_I_MSK 0xffefffff
+#define MTX_EN_INT_Q2_Q_EMPTY_SFT 20
+#define MTX_EN_INT_Q2_Q_EMPTY_HI 20
+#define MTX_EN_INT_Q2_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_MSK 0x00200000
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_I_MSK 0xffdfffff
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_SFT 21
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_HI 21
+#define MTX_EN_INT_Q2_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q3_Q_EMPTY_MSK 0x00400000
+#define MTX_EN_INT_Q3_Q_EMPTY_I_MSK 0xffbfffff
+#define MTX_EN_INT_Q3_Q_EMPTY_SFT 22
+#define MTX_EN_INT_Q3_Q_EMPTY_HI 22
+#define MTX_EN_INT_Q3_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_MSK 0x00800000
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_I_MSK 0xff7fffff
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_SFT 23
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_HI 23
+#define MTX_EN_INT_Q3_TXOP_RUNOUT_SZ 1
+#define MTX_EN_INT_Q4_Q_EMPTY_MSK 0x01000000
+#define MTX_EN_INT_Q4_Q_EMPTY_I_MSK 0xfeffffff
+#define MTX_EN_INT_Q4_Q_EMPTY_SFT 24
+#define MTX_EN_INT_Q4_Q_EMPTY_HI 24
+#define MTX_EN_INT_Q4_Q_EMPTY_SZ 1
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_MSK 0x02000000
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_I_MSK 0xfdffffff
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_SFT 25
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_HI 25
+#define MTX_EN_INT_Q4_TXOP_RUNOUT_SZ 1
+#define MTX_MTX2PHY_SLOW_MSK 0x00000001
+#define MTX_MTX2PHY_SLOW_I_MSK 0xfffffffe
+#define MTX_MTX2PHY_SLOW_SFT 0
+#define MTX_MTX2PHY_SLOW_HI 0
+#define MTX_MTX2PHY_SLOW_SZ 1
+#define MTX_M2M_SLOW_PRD_MSK 0x0000000e
+#define MTX_M2M_SLOW_PRD_I_MSK 0xfffffff1
+#define MTX_M2M_SLOW_PRD_SFT 1
+#define MTX_M2M_SLOW_PRD_HI 3
+#define MTX_M2M_SLOW_PRD_SZ 3
+#define MTX_AMPDU_CRC_AUTO_MSK 0x00000020
+#define MTX_AMPDU_CRC_AUTO_I_MSK 0xffffffdf
+#define MTX_AMPDU_CRC_AUTO_SFT 5
+#define MTX_AMPDU_CRC_AUTO_HI 5
+#define MTX_AMPDU_CRC_AUTO_SZ 1
+#define MTX_FAST_RSP_MODE_MSK 0x00000040
+#define MTX_FAST_RSP_MODE_I_MSK 0xffffffbf
+#define MTX_FAST_RSP_MODE_SFT 6
+#define MTX_FAST_RSP_MODE_HI 6
+#define MTX_FAST_RSP_MODE_SZ 1
+#define MTX_RAW_DATA_MODE_MSK 0x00000080
+#define MTX_RAW_DATA_MODE_I_MSK 0xffffff7f
+#define MTX_RAW_DATA_MODE_SFT 7
+#define MTX_RAW_DATA_MODE_HI 7
+#define MTX_RAW_DATA_MODE_SZ 1
+#define MTX_ACK_DUR0_MSK 0x00000100
+#define MTX_ACK_DUR0_I_MSK 0xfffffeff
+#define MTX_ACK_DUR0_SFT 8
+#define MTX_ACK_DUR0_HI 8
+#define MTX_ACK_DUR0_SZ 1
+#define MTX_TSF_AUTO_BCN_MSK 0x00000400
+#define MTX_TSF_AUTO_BCN_I_MSK 0xfffffbff
+#define MTX_TSF_AUTO_BCN_SFT 10
+#define MTX_TSF_AUTO_BCN_HI 10
+#define MTX_TSF_AUTO_BCN_SZ 1
+#define MTX_TSF_AUTO_MISC_MSK 0x00000800
+#define MTX_TSF_AUTO_MISC_I_MSK 0xfffff7ff
+#define MTX_TSF_AUTO_MISC_SFT 11
+#define MTX_TSF_AUTO_MISC_HI 11
+#define MTX_TSF_AUTO_MISC_SZ 1
+#define MTX_FORCE_CS_IDLE_MSK 0x00001000
+#define MTX_FORCE_CS_IDLE_I_MSK 0xffffefff
+#define MTX_FORCE_CS_IDLE_SFT 12
+#define MTX_FORCE_CS_IDLE_HI 12
+#define MTX_FORCE_CS_IDLE_SZ 1
+#define MTX_FORCE_BKF_RXEN0_MSK 0x00002000
+#define MTX_FORCE_BKF_RXEN0_I_MSK 0xffffdfff
+#define MTX_FORCE_BKF_RXEN0_SFT 13
+#define MTX_FORCE_BKF_RXEN0_HI 13
+#define MTX_FORCE_BKF_RXEN0_SZ 1
+#define MTX_FORCE_DMA_RXEN0_MSK 0x00004000
+#define MTX_FORCE_DMA_RXEN0_I_MSK 0xffffbfff
+#define MTX_FORCE_DMA_RXEN0_SFT 14
+#define MTX_FORCE_DMA_RXEN0_HI 14
+#define MTX_FORCE_DMA_RXEN0_SZ 1
+#define MTX_FORCE_RXEN0_MSK 0x00008000
+#define MTX_FORCE_RXEN0_I_MSK 0xffff7fff
+#define MTX_FORCE_RXEN0_SFT 15
+#define MTX_FORCE_RXEN0_HI 15
+#define MTX_FORCE_RXEN0_SZ 1
+#define MTX_HALT_Q_MB_MSK 0x003f0000
+#define MTX_HALT_Q_MB_I_MSK 0xffc0ffff
+#define MTX_HALT_Q_MB_SFT 16
+#define MTX_HALT_Q_MB_HI 21
+#define MTX_HALT_Q_MB_SZ 6
+#define MTX_CTS_SET_DIF_MSK 0x00400000
+#define MTX_CTS_SET_DIF_I_MSK 0xffbfffff
+#define MTX_CTS_SET_DIF_SFT 22
+#define MTX_CTS_SET_DIF_HI 22
+#define MTX_CTS_SET_DIF_SZ 1
+#define MTX_AMPDU_SET_DIF_MSK 0x00800000
+#define MTX_AMPDU_SET_DIF_I_MSK 0xff7fffff
+#define MTX_AMPDU_SET_DIF_SFT 23
+#define MTX_AMPDU_SET_DIF_HI 23
+#define MTX_AMPDU_SET_DIF_SZ 1
+#define MTX_EDCCA_TOUT_MSK 0x000003ff
+#define MTX_EDCCA_TOUT_I_MSK 0xfffffc00
+#define MTX_EDCCA_TOUT_SFT 0
+#define MTX_EDCCA_TOUT_HI 9
+#define MTX_EDCCA_TOUT_SZ 10
+#define MTX_INT_BCN_MSK 0x00000002
+#define MTX_INT_BCN_I_MSK 0xfffffffd
+#define MTX_INT_BCN_SFT 1
+#define MTX_INT_BCN_HI 1
+#define MTX_INT_BCN_SZ 1
+#define MTX_INT_DTIM_MSK 0x00000008
+#define MTX_INT_DTIM_I_MSK 0xfffffff7
+#define MTX_INT_DTIM_SFT 3
+#define MTX_INT_DTIM_HI 3
+#define MTX_INT_DTIM_SZ 1
+#define MTX_EN_INT_BCN_MSK 0x00000002
+#define MTX_EN_INT_BCN_I_MSK 0xfffffffd
+#define MTX_EN_INT_BCN_SFT 1
+#define MTX_EN_INT_BCN_HI 1
+#define MTX_EN_INT_BCN_SZ 1
+#define MTX_EN_INT_DTIM_MSK 0x00000008
+#define MTX_EN_INT_DTIM_I_MSK 0xfffffff7
+#define MTX_EN_INT_DTIM_SFT 3
+#define MTX_EN_INT_DTIM_HI 3
+#define MTX_EN_INT_DTIM_SZ 1
+#define MTX_BCN_TIMER_EN_MSK 0x00000001
+#define MTX_BCN_TIMER_EN_I_MSK 0xfffffffe
+#define MTX_BCN_TIMER_EN_SFT 0
+#define MTX_BCN_TIMER_EN_HI 0
+#define MTX_BCN_TIMER_EN_SZ 1
+#define MTX_TIME_STAMP_AUTO_FILL_MSK 0x00000002
+#define MTX_TIME_STAMP_AUTO_FILL_I_MSK 0xfffffffd
+#define MTX_TIME_STAMP_AUTO_FILL_SFT 1
+#define MTX_TIME_STAMP_AUTO_FILL_HI 1
+#define MTX_TIME_STAMP_AUTO_FILL_SZ 1
+#define MTX_TSF_TIMER_EN_MSK 0x00000020
+#define MTX_TSF_TIMER_EN_I_MSK 0xffffffdf
+#define MTX_TSF_TIMER_EN_SFT 5
+#define MTX_TSF_TIMER_EN_HI 5
+#define MTX_TSF_TIMER_EN_SZ 1
+#define MTX_HALT_MNG_UNTIL_DTIM_MSK 0x00000040
+#define MTX_HALT_MNG_UNTIL_DTIM_I_MSK 0xffffffbf
+#define MTX_HALT_MNG_UNTIL_DTIM_SFT 6
+#define MTX_HALT_MNG_UNTIL_DTIM_HI 6
+#define MTX_HALT_MNG_UNTIL_DTIM_SZ 1
+#define MTX_INT_DTIM_NUM_MSK 0x0000ff00
+#define MTX_INT_DTIM_NUM_I_MSK 0xffff00ff
+#define MTX_INT_DTIM_NUM_SFT 8
+#define MTX_INT_DTIM_NUM_HI 15
+#define MTX_INT_DTIM_NUM_SZ 8
+#define MTX_AUTO_FLUSH_Q4_MSK 0x00010000
+#define MTX_AUTO_FLUSH_Q4_I_MSK 0xfffeffff
+#define MTX_AUTO_FLUSH_Q4_SFT 16
+#define MTX_AUTO_FLUSH_Q4_HI 16
+#define MTX_AUTO_FLUSH_Q4_SZ 1
+#define MTX_BCN_PKTID_CH_LOCK_MSK 0x00000001
+#define MTX_BCN_PKTID_CH_LOCK_I_MSK 0xfffffffe
+#define MTX_BCN_PKTID_CH_LOCK_SFT 0
+#define MTX_BCN_PKTID_CH_LOCK_HI 0
+#define MTX_BCN_PKTID_CH_LOCK_SZ 1
+#define MTX_BCN_CFG_VLD_MSK 0x00000006
+#define MTX_BCN_CFG_VLD_I_MSK 0xfffffff9
+#define MTX_BCN_CFG_VLD_SFT 1
+#define MTX_BCN_CFG_VLD_HI 2
+#define MTX_BCN_CFG_VLD_SZ 2
+#define MTX_AUTO_BCN_ONGOING_MSK 0x00000008
+#define MTX_AUTO_BCN_ONGOING_I_MSK 0xfffffff7
+#define MTX_AUTO_BCN_ONGOING_SFT 3
+#define MTX_AUTO_BCN_ONGOING_HI 3
+#define MTX_AUTO_BCN_ONGOING_SZ 1
+#define MTX_BCN_TIMER_MSK 0xffff0000
+#define MTX_BCN_TIMER_I_MSK 0x0000ffff
+#define MTX_BCN_TIMER_SFT 16
+#define MTX_BCN_TIMER_HI 31
+#define MTX_BCN_TIMER_SZ 16
+#define MTX_BCN_PERIOD_MSK 0x0000ffff
+#define MTX_BCN_PERIOD_I_MSK 0xffff0000
+#define MTX_BCN_PERIOD_SFT 0
+#define MTX_BCN_PERIOD_HI 15
+#define MTX_BCN_PERIOD_SZ 16
+#define MTX_DTIM_NUM_MSK 0xff000000
+#define MTX_DTIM_NUM_I_MSK 0x00ffffff
+#define MTX_DTIM_NUM_SFT 24
+#define MTX_DTIM_NUM_HI 31
+#define MTX_DTIM_NUM_SZ 8
+#define MTX_BCN_TSF_L_MSK 0xffffffff
+#define MTX_BCN_TSF_L_I_MSK 0x00000000
+#define MTX_BCN_TSF_L_SFT 0
+#define MTX_BCN_TSF_L_HI 31
+#define MTX_BCN_TSF_L_SZ 32
+#define MTX_BCN_TSF_U_MSK 0xffffffff
+#define MTX_BCN_TSF_U_I_MSK 0x00000000
+#define MTX_BCN_TSF_U_SFT 0
+#define MTX_BCN_TSF_U_HI 31
+#define MTX_BCN_TSF_U_SZ 32
+#define MTX_BCN_PKT_ID0_MSK 0x0000007f
+#define MTX_BCN_PKT_ID0_I_MSK 0xffffff80
+#define MTX_BCN_PKT_ID0_SFT 0
+#define MTX_BCN_PKT_ID0_HI 6
+#define MTX_BCN_PKT_ID0_SZ 7
+#define MTX_DTIM_OFST0_MSK 0x03ff0000
+#define MTX_DTIM_OFST0_I_MSK 0xfc00ffff
+#define MTX_DTIM_OFST0_SFT 16
+#define MTX_DTIM_OFST0_HI 25
+#define MTX_DTIM_OFST0_SZ 10
+#define MTX_BCN_PKT_ID1_MSK 0x0000007f
+#define MTX_BCN_PKT_ID1_I_MSK 0xffffff80
+#define MTX_BCN_PKT_ID1_SFT 0
+#define MTX_BCN_PKT_ID1_HI 6
+#define MTX_BCN_PKT_ID1_SZ 7
+#define MTX_DTIM_OFST1_MSK 0x03ff0000
+#define MTX_DTIM_OFST1_I_MSK 0xfc00ffff
+#define MTX_DTIM_OFST1_SFT 16
+#define MTX_DTIM_OFST1_HI 25
+#define MTX_DTIM_OFST1_SZ 10
+#define MTX_CCA_MSK 0x00000001
+#define MTX_CCA_I_MSK 0xfffffffe
+#define MTX_CCA_SFT 0
+#define MTX_CCA_HI 0
+#define MTX_CCA_SZ 1
+#define MRX_CCA_MSK 0x00000002
+#define MRX_CCA_I_MSK 0xfffffffd
+#define MRX_CCA_SFT 1
+#define MRX_CCA_HI 1
+#define MRX_CCA_SZ 1
+#define MTX_DMA_FSM_MSK 0x0000001c
+#define MTX_DMA_FSM_I_MSK 0xffffffe3
+#define MTX_DMA_FSM_SFT 2
+#define MTX_DMA_FSM_HI 4
+#define MTX_DMA_FSM_SZ 3
+#define CH_ST_FSM_MSK 0x000000e0
+#define CH_ST_FSM_I_MSK 0xffffff1f
+#define CH_ST_FSM_SFT 5
+#define CH_ST_FSM_HI 7
+#define CH_ST_FSM_SZ 3
+#define MTX_GNT_LOCK_MSK 0x00000100
+#define MTX_GNT_LOCK_I_MSK 0xfffffeff
+#define MTX_GNT_LOCK_SFT 8
+#define MTX_GNT_LOCK_HI 8
+#define MTX_GNT_LOCK_SZ 1
+#define MTX_DMA_REQ_MSK 0x00000200
+#define MTX_DMA_REQ_I_MSK 0xfffffdff
+#define MTX_DMA_REQ_SFT 9
+#define MTX_DMA_REQ_HI 9
+#define MTX_DMA_REQ_SZ 1
+#define MTX_Q_REQ_MSK 0x00000400
+#define MTX_Q_REQ_I_MSK 0xfffffbff
+#define MTX_Q_REQ_SFT 10
+#define MTX_Q_REQ_HI 10
+#define MTX_Q_REQ_SZ 1
+#define MTX_TX_EN_MSK 0x00000800
+#define MTX_TX_EN_I_MSK 0xfffff7ff
+#define MTX_TX_EN_SFT 11
+#define MTX_TX_EN_HI 11
+#define MTX_TX_EN_SZ 1
+#define MRX_RX_EN_MSK 0x00001000
+#define MRX_RX_EN_I_MSK 0xffffefff
+#define MRX_RX_EN_SFT 12
+#define MRX_RX_EN_HI 12
+#define MRX_RX_EN_SZ 1
+#define DBG_PRTC_PRD_MSK 0x00002000
+#define DBG_PRTC_PRD_I_MSK 0xffffdfff
+#define DBG_PRTC_PRD_SFT 13
+#define DBG_PRTC_PRD_HI 13
+#define DBG_PRTC_PRD_SZ 1
+#define DBG_DMA_RDY_MSK 0x00004000
+#define DBG_DMA_RDY_I_MSK 0xffffbfff
+#define DBG_DMA_RDY_SFT 14
+#define DBG_DMA_RDY_HI 14
+#define DBG_DMA_RDY_SZ 1
+#define DBG_WAIT_RSP_MSK 0x00008000
+#define DBG_WAIT_RSP_I_MSK 0xffff7fff
+#define DBG_WAIT_RSP_SFT 15
+#define DBG_WAIT_RSP_HI 15
+#define DBG_WAIT_RSP_SZ 1
+#define DBG_CFRM_BUSY_MSK 0x00010000
+#define DBG_CFRM_BUSY_I_MSK 0xfffeffff
+#define DBG_CFRM_BUSY_SFT 16
+#define DBG_CFRM_BUSY_HI 16
+#define DBG_CFRM_BUSY_SZ 1
+#define DBG_RST_MSK 0x00000001
+#define DBG_RST_I_MSK 0xfffffffe
+#define DBG_RST_SFT 0
+#define DBG_RST_HI 0
+#define DBG_RST_SZ 1
+#define DBG_MODE_MSK 0x00000002
+#define DBG_MODE_I_MSK 0xfffffffd
+#define DBG_MODE_SFT 1
+#define DBG_MODE_HI 1
+#define DBG_MODE_SZ 1
+#define MB_REQ_DUR_MSK 0x0000ffff
+#define MB_REQ_DUR_I_MSK 0xffff0000
+#define MB_REQ_DUR_SFT 0
+#define MB_REQ_DUR_HI 15
+#define MB_REQ_DUR_SZ 16
+#define RX_EN_DUR_MSK 0xffff0000
+#define RX_EN_DUR_I_MSK 0x0000ffff
+#define RX_EN_DUR_SFT 16
+#define RX_EN_DUR_HI 31
+#define RX_EN_DUR_SZ 16
+#define RX_CS_DUR_MSK 0x0000ffff
+#define RX_CS_DUR_I_MSK 0xffff0000
+#define RX_CS_DUR_SFT 0
+#define RX_CS_DUR_HI 15
+#define RX_CS_DUR_SZ 16
+#define TX_CCA_DUR_MSK 0xffff0000
+#define TX_CCA_DUR_I_MSK 0x0000ffff
+#define TX_CCA_DUR_SFT 16
+#define TX_CCA_DUR_HI 31
+#define TX_CCA_DUR_SZ 16
+#define Q_REQ_DUR_MSK 0x0000ffff
+#define Q_REQ_DUR_I_MSK 0xffff0000
+#define Q_REQ_DUR_SFT 0
+#define Q_REQ_DUR_HI 15
+#define Q_REQ_DUR_SZ 16
+#define CH_STA0_DUR_MSK 0xffff0000
+#define CH_STA0_DUR_I_MSK 0x0000ffff
+#define CH_STA0_DUR_SFT 16
+#define CH_STA0_DUR_HI 31
+#define CH_STA0_DUR_SZ 16
+#define MTX_DUR_RSP_TOUT_B_MSK 0x000000ff
+#define MTX_DUR_RSP_TOUT_B_I_MSK 0xffffff00
+#define MTX_DUR_RSP_TOUT_B_SFT 0
+#define MTX_DUR_RSP_TOUT_B_HI 7
+#define MTX_DUR_RSP_TOUT_B_SZ 8
+#define MTX_DUR_RSP_TOUT_G_MSK 0x0000ff00
+#define MTX_DUR_RSP_TOUT_G_I_MSK 0xffff00ff
+#define MTX_DUR_RSP_TOUT_G_SFT 8
+#define MTX_DUR_RSP_TOUT_G_HI 15
+#define MTX_DUR_RSP_TOUT_G_SZ 8
+#define MTX_DUR_RSP_SIFS_MSK 0x000000ff
+#define MTX_DUR_RSP_SIFS_I_MSK 0xffffff00
+#define MTX_DUR_RSP_SIFS_SFT 0
+#define MTX_DUR_RSP_SIFS_HI 7
+#define MTX_DUR_RSP_SIFS_SZ 8
+#define MTX_DUR_BURST_SIFS_MSK 0x0000ff00
+#define MTX_DUR_BURST_SIFS_I_MSK 0xffff00ff
+#define MTX_DUR_BURST_SIFS_SFT 8
+#define MTX_DUR_BURST_SIFS_HI 15
+#define MTX_DUR_BURST_SIFS_SZ 8
+#define MTX_DUR_SLOT_MSK 0x003f0000
+#define MTX_DUR_SLOT_I_MSK 0xffc0ffff
+#define MTX_DUR_SLOT_SFT 16
+#define MTX_DUR_SLOT_HI 21
+#define MTX_DUR_SLOT_SZ 6
+#define MTX_DUR_RSP_EIFS_MSK 0xffc00000
+#define MTX_DUR_RSP_EIFS_I_MSK 0x003fffff
+#define MTX_DUR_RSP_EIFS_SFT 22
+#define MTX_DUR_RSP_EIFS_HI 31
+#define MTX_DUR_RSP_EIFS_SZ 10
+#define MTX_DUR_RSP_SIFS_G_MSK 0x000000ff
+#define MTX_DUR_RSP_SIFS_G_I_MSK 0xffffff00
+#define MTX_DUR_RSP_SIFS_G_SFT 0
+#define MTX_DUR_RSP_SIFS_G_HI 7
+#define MTX_DUR_RSP_SIFS_G_SZ 8
+#define MTX_DUR_BURST_SIFS_G_MSK 0x0000ff00
+#define MTX_DUR_BURST_SIFS_G_I_MSK 0xffff00ff
+#define MTX_DUR_BURST_SIFS_G_SFT 8
+#define MTX_DUR_BURST_SIFS_G_HI 15
+#define MTX_DUR_BURST_SIFS_G_SZ 8
+#define MTX_DUR_SLOT_G_MSK 0x003f0000
+#define MTX_DUR_SLOT_G_I_MSK 0xffc0ffff
+#define MTX_DUR_SLOT_G_SFT 16
+#define MTX_DUR_SLOT_G_HI 21
+#define MTX_DUR_SLOT_G_SZ 6
+#define MTX_DUR_RSP_EIFS_G_MSK 0xffc00000
+#define MTX_DUR_RSP_EIFS_G_I_MSK 0x003fffff
+#define MTX_DUR_RSP_EIFS_G_SFT 22
+#define MTX_DUR_RSP_EIFS_G_HI 31
+#define MTX_DUR_RSP_EIFS_G_SZ 10
+#define CH_STA1_DUR_MSK 0x0000ffff
+#define CH_STA1_DUR_I_MSK 0xffff0000
+#define CH_STA1_DUR_SFT 0
+#define CH_STA1_DUR_HI 15
+#define CH_STA1_DUR_SZ 16
+#define CH_STA2_DUR_MSK 0xffff0000
+#define CH_STA2_DUR_I_MSK 0x0000ffff
+#define CH_STA2_DUR_SFT 16
+#define CH_STA2_DUR_HI 31
+#define CH_STA2_DUR_SZ 16
+#define MTX_NAV_MSK 0x0000ffff
+#define MTX_NAV_I_MSK 0xffff0000
+#define MTX_NAV_SFT 0
+#define MTX_NAV_HI 15
+#define MTX_NAV_SZ 16
+#define MTX_MIB_CNT0_MSK 0x3fffffff
+#define MTX_MIB_CNT0_I_MSK 0xc0000000
+#define MTX_MIB_CNT0_SFT 0
+#define MTX_MIB_CNT0_HI 29
+#define MTX_MIB_CNT0_SZ 30
+#define MTX_MIB_EN0_MSK 0x40000000
+#define MTX_MIB_EN0_I_MSK 0xbfffffff
+#define MTX_MIB_EN0_SFT 30
+#define MTX_MIB_EN0_HI 30
+#define MTX_MIB_EN0_SZ 1
+#define MTX_MIB_CNT1_MSK 0x3fffffff
+#define MTX_MIB_CNT1_I_MSK 0xc0000000
+#define MTX_MIB_CNT1_SFT 0
+#define MTX_MIB_CNT1_HI 29
+#define MTX_MIB_CNT1_SZ 30
+#define MTX_MIB_EN1_MSK 0x40000000
+#define MTX_MIB_EN1_I_MSK 0xbfffffff
+#define MTX_MIB_EN1_SFT 30
+#define MTX_MIB_EN1_HI 30
+#define MTX_MIB_EN1_SZ 1
+#define CH_STA3_DUR_MSK 0x0000ffff
+#define CH_STA3_DUR_I_MSK 0xffff0000
+#define CH_STA3_DUR_SFT 0
+#define CH_STA3_DUR_HI 15
+#define CH_STA3_DUR_SZ 16
+#define CH_STA4_DUR_MSK 0xffff0000
+#define CH_STA4_DUR_I_MSK 0x0000ffff
+#define CH_STA4_DUR_SFT 16
+#define CH_STA4_DUR_HI 31
+#define CH_STA4_DUR_SZ 16
+#define TXQ0_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ0_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ0_MTX_Q_PRE_LD_SFT 1
+#define TXQ0_MTX_Q_PRE_LD_HI 1
+#define TXQ0_MTX_Q_PRE_LD_SZ 1
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ0_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ0_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ0_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ0_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ0_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ0_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ0_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ0_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ0_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ0_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ0_MTX_Q_RND_MODE_SFT 6
+#define TXQ0_MTX_Q_RND_MODE_HI 7
+#define TXQ0_MTX_Q_RND_MODE_SZ 2
+#define TXQ0_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ0_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ0_MTX_Q_AIFSN_SFT 0
+#define TXQ0_MTX_Q_AIFSN_HI 3
+#define TXQ0_MTX_Q_AIFSN_SZ 4
+#define TXQ0_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ0_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ0_MTX_Q_ECWMIN_SFT 8
+#define TXQ0_MTX_Q_ECWMIN_HI 11
+#define TXQ0_MTX_Q_ECWMIN_SZ 4
+#define TXQ0_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ0_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ0_MTX_Q_ECWMAX_SFT 12
+#define TXQ0_MTX_Q_ECWMAX_HI 15
+#define TXQ0_MTX_Q_ECWMAX_SZ 4
+#define TXQ0_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ0_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ0_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ0_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ0_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_BKF_CNT_SFT 0
+#define TXQ0_MTX_Q_BKF_CNT_HI 15
+#define TXQ0_MTX_Q_BKF_CNT_SZ 16
+#define TXQ0_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ0_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ0_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ0_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ0_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ0_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ0_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ0_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ0_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ0_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ0_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ0_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ0_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ0_MTX_Q_ID_MAP_L_HI 31
+#define TXQ0_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ0_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ0_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ0_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ0_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ0_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ0_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ0_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ0_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ1_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ1_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ1_MTX_Q_PRE_LD_SFT 1
+#define TXQ1_MTX_Q_PRE_LD_HI 1
+#define TXQ1_MTX_Q_PRE_LD_SZ 1
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ1_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ1_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ1_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ1_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ1_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ1_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ1_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ1_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ1_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ1_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ1_MTX_Q_RND_MODE_SFT 6
+#define TXQ1_MTX_Q_RND_MODE_HI 7
+#define TXQ1_MTX_Q_RND_MODE_SZ 2
+#define TXQ1_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ1_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ1_MTX_Q_AIFSN_SFT 0
+#define TXQ1_MTX_Q_AIFSN_HI 3
+#define TXQ1_MTX_Q_AIFSN_SZ 4
+#define TXQ1_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ1_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ1_MTX_Q_ECWMIN_SFT 8
+#define TXQ1_MTX_Q_ECWMIN_HI 11
+#define TXQ1_MTX_Q_ECWMIN_SZ 4
+#define TXQ1_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ1_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ1_MTX_Q_ECWMAX_SFT 12
+#define TXQ1_MTX_Q_ECWMAX_HI 15
+#define TXQ1_MTX_Q_ECWMAX_SZ 4
+#define TXQ1_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ1_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ1_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ1_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ1_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_BKF_CNT_SFT 0
+#define TXQ1_MTX_Q_BKF_CNT_HI 15
+#define TXQ1_MTX_Q_BKF_CNT_SZ 16
+#define TXQ1_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ1_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ1_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ1_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ1_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ1_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ1_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ1_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ1_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ1_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ1_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ1_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ1_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ1_MTX_Q_ID_MAP_L_HI 31
+#define TXQ1_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ1_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ1_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ1_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ1_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ1_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ1_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ1_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ1_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ2_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ2_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ2_MTX_Q_PRE_LD_SFT 1
+#define TXQ2_MTX_Q_PRE_LD_HI 1
+#define TXQ2_MTX_Q_PRE_LD_SZ 1
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ2_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ2_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ2_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ2_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ2_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ2_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ2_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ2_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ2_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ2_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ2_MTX_Q_RND_MODE_SFT 6
+#define TXQ2_MTX_Q_RND_MODE_HI 7
+#define TXQ2_MTX_Q_RND_MODE_SZ 2
+#define TXQ2_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ2_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ2_MTX_Q_AIFSN_SFT 0
+#define TXQ2_MTX_Q_AIFSN_HI 3
+#define TXQ2_MTX_Q_AIFSN_SZ 4
+#define TXQ2_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ2_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ2_MTX_Q_ECWMIN_SFT 8
+#define TXQ2_MTX_Q_ECWMIN_HI 11
+#define TXQ2_MTX_Q_ECWMIN_SZ 4
+#define TXQ2_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ2_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ2_MTX_Q_ECWMAX_SFT 12
+#define TXQ2_MTX_Q_ECWMAX_HI 15
+#define TXQ2_MTX_Q_ECWMAX_SZ 4
+#define TXQ2_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ2_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ2_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ2_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ2_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_BKF_CNT_SFT 0
+#define TXQ2_MTX_Q_BKF_CNT_HI 15
+#define TXQ2_MTX_Q_BKF_CNT_SZ 16
+#define TXQ2_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ2_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ2_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ2_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ2_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ2_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ2_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ2_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ2_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ2_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ2_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ2_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ2_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ2_MTX_Q_ID_MAP_L_HI 31
+#define TXQ2_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ2_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ2_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ2_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ2_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ2_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ2_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ2_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ2_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ3_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ3_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ3_MTX_Q_PRE_LD_SFT 1
+#define TXQ3_MTX_Q_PRE_LD_HI 1
+#define TXQ3_MTX_Q_PRE_LD_SZ 1
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ3_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ3_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ3_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ3_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ3_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ3_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ3_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ3_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ3_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ3_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ3_MTX_Q_RND_MODE_SFT 6
+#define TXQ3_MTX_Q_RND_MODE_HI 7
+#define TXQ3_MTX_Q_RND_MODE_SZ 2
+#define TXQ3_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ3_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ3_MTX_Q_AIFSN_SFT 0
+#define TXQ3_MTX_Q_AIFSN_HI 3
+#define TXQ3_MTX_Q_AIFSN_SZ 4
+#define TXQ3_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ3_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ3_MTX_Q_ECWMIN_SFT 8
+#define TXQ3_MTX_Q_ECWMIN_HI 11
+#define TXQ3_MTX_Q_ECWMIN_SZ 4
+#define TXQ3_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ3_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ3_MTX_Q_ECWMAX_SFT 12
+#define TXQ3_MTX_Q_ECWMAX_HI 15
+#define TXQ3_MTX_Q_ECWMAX_SZ 4
+#define TXQ3_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ3_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ3_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ3_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ3_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_BKF_CNT_SFT 0
+#define TXQ3_MTX_Q_BKF_CNT_HI 15
+#define TXQ3_MTX_Q_BKF_CNT_SZ 16
+#define TXQ3_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ3_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ3_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ3_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ3_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ3_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ3_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ3_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ3_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ3_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ3_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ3_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ3_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ3_MTX_Q_ID_MAP_L_HI 31
+#define TXQ3_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ3_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ3_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ3_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ3_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ3_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ3_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ3_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ3_MTX_Q_TXOP_OV_THD_SZ 16
+#define TXQ4_MTX_Q_PRE_LD_MSK 0x00000002
+#define TXQ4_MTX_Q_PRE_LD_I_MSK 0xfffffffd
+#define TXQ4_MTX_Q_PRE_LD_SFT 1
+#define TXQ4_MTX_Q_PRE_LD_HI 1
+#define TXQ4_MTX_Q_PRE_LD_SZ 1
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_MSK 0x00000004
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_I_MSK 0xfffffffb
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_SFT 2
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_HI 2
+#define TXQ4_MTX_Q_BKF_CNT_FIXED_SZ 1
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_MSK 0x00000008
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_I_MSK 0xfffffff7
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SFT 3
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_HI 3
+#define TXQ4_MTX_Q_TXOP_SUB_FRM_TIME_SZ 1
+#define TXQ4_MTX_Q_MB_NO_RLS_MSK 0x00000010
+#define TXQ4_MTX_Q_MB_NO_RLS_I_MSK 0xffffffef
+#define TXQ4_MTX_Q_MB_NO_RLS_SFT 4
+#define TXQ4_MTX_Q_MB_NO_RLS_HI 4
+#define TXQ4_MTX_Q_MB_NO_RLS_SZ 1
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_MSK 0x00000020
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_I_MSK 0xffffffdf
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_SFT 5
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_HI 5
+#define TXQ4_MTX_Q_TXOP_FRC_BUR_SZ 1
+#define TXQ4_MTX_Q_RND_MODE_MSK 0x000000c0
+#define TXQ4_MTX_Q_RND_MODE_I_MSK 0xffffff3f
+#define TXQ4_MTX_Q_RND_MODE_SFT 6
+#define TXQ4_MTX_Q_RND_MODE_HI 7
+#define TXQ4_MTX_Q_RND_MODE_SZ 2
+#define TXQ4_MTX_Q_AIFSN_MSK 0x0000000f
+#define TXQ4_MTX_Q_AIFSN_I_MSK 0xfffffff0
+#define TXQ4_MTX_Q_AIFSN_SFT 0
+#define TXQ4_MTX_Q_AIFSN_HI 3
+#define TXQ4_MTX_Q_AIFSN_SZ 4
+#define TXQ4_MTX_Q_ECWMIN_MSK 0x00000f00
+#define TXQ4_MTX_Q_ECWMIN_I_MSK 0xfffff0ff
+#define TXQ4_MTX_Q_ECWMIN_SFT 8
+#define TXQ4_MTX_Q_ECWMIN_HI 11
+#define TXQ4_MTX_Q_ECWMIN_SZ 4
+#define TXQ4_MTX_Q_ECWMAX_MSK 0x0000f000
+#define TXQ4_MTX_Q_ECWMAX_I_MSK 0xffff0fff
+#define TXQ4_MTX_Q_ECWMAX_SFT 12
+#define TXQ4_MTX_Q_ECWMAX_HI 15
+#define TXQ4_MTX_Q_ECWMAX_SZ 4
+#define TXQ4_MTX_Q_TXOP_LIMIT_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_LIMIT_I_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_LIMIT_SFT 16
+#define TXQ4_MTX_Q_TXOP_LIMIT_HI 31
+#define TXQ4_MTX_Q_TXOP_LIMIT_SZ 16
+#define TXQ4_MTX_Q_BKF_CNT_MSK 0x0000ffff
+#define TXQ4_MTX_Q_BKF_CNT_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_BKF_CNT_SFT 0
+#define TXQ4_MTX_Q_BKF_CNT_HI 15
+#define TXQ4_MTX_Q_BKF_CNT_SZ 16
+#define TXQ4_MTX_Q_SRC_LIMIT_MSK 0x000000ff
+#define TXQ4_MTX_Q_SRC_LIMIT_I_MSK 0xffffff00
+#define TXQ4_MTX_Q_SRC_LIMIT_SFT 0
+#define TXQ4_MTX_Q_SRC_LIMIT_HI 7
+#define TXQ4_MTX_Q_SRC_LIMIT_SZ 8
+#define TXQ4_MTX_Q_LRC_LIMIT_MSK 0x0000ff00
+#define TXQ4_MTX_Q_LRC_LIMIT_I_MSK 0xffff00ff
+#define TXQ4_MTX_Q_LRC_LIMIT_SFT 8
+#define TXQ4_MTX_Q_LRC_LIMIT_HI 15
+#define TXQ4_MTX_Q_LRC_LIMIT_SZ 8
+#define TXQ4_MTX_Q_ID_MAP_L_MSK 0xffffffff
+#define TXQ4_MTX_Q_ID_MAP_L_I_MSK 0x00000000
+#define TXQ4_MTX_Q_ID_MAP_L_SFT 0
+#define TXQ4_MTX_Q_ID_MAP_L_HI 31
+#define TXQ4_MTX_Q_ID_MAP_L_SZ 32
+#define TXQ4_MTX_Q_TXOP_CH_THD_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_CH_THD_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_CH_THD_SFT 0
+#define TXQ4_MTX_Q_TXOP_CH_THD_HI 15
+#define TXQ4_MTX_Q_TXOP_CH_THD_SZ 16
+#define TXQ4_MTX_Q_TXOP_OV_THD_MSK 0x0000ffff
+#define TXQ4_MTX_Q_TXOP_OV_THD_I_MSK 0xffff0000
+#define TXQ4_MTX_Q_TXOP_OV_THD_SFT 0
+#define TXQ4_MTX_Q_TXOP_OV_THD_HI 15
+#define TXQ4_MTX_Q_TXOP_OV_THD_SZ 16
+#define VALID0_MSK 0x00000001
+#define VALID0_I_MSK 0xfffffffe
+#define VALID0_SFT 0
+#define VALID0_HI 0
+#define VALID0_SZ 1
+#define PEER_QOS_EN0_MSK 0x00000002
+#define PEER_QOS_EN0_I_MSK 0xfffffffd
+#define PEER_QOS_EN0_SFT 1
+#define PEER_QOS_EN0_HI 1
+#define PEER_QOS_EN0_SZ 1
+#define PEER_OP_MODE0_MSK 0x0000000c
+#define PEER_OP_MODE0_I_MSK 0xfffffff3
+#define PEER_OP_MODE0_SFT 2
+#define PEER_OP_MODE0_HI 3
+#define PEER_OP_MODE0_SZ 2
+#define PEER_HT_MODE0_MSK 0x00000030
+#define PEER_HT_MODE0_I_MSK 0xffffffcf
+#define PEER_HT_MODE0_SFT 4
+#define PEER_HT_MODE0_HI 5
+#define PEER_HT_MODE0_SZ 2
+#define PEER_MAC0_31_0_MSK 0xffffffff
+#define PEER_MAC0_31_0_I_MSK 0x00000000
+#define PEER_MAC0_31_0_SFT 0
+#define PEER_MAC0_31_0_HI 31
+#define PEER_MAC0_31_0_SZ 32
+#define PEER_MAC0_47_32_MSK 0x0000ffff
+#define PEER_MAC0_47_32_I_MSK 0xffff0000
+#define PEER_MAC0_47_32_SFT 0
+#define PEER_MAC0_47_32_HI 15
+#define PEER_MAC0_47_32_SZ 16
+#define TX_ACK_POLICY_0_0_MSK 0x00000003
+#define TX_ACK_POLICY_0_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_0_SFT 0
+#define TX_ACK_POLICY_0_0_HI 1
+#define TX_ACK_POLICY_0_0_SZ 2
+#define TX_SEQ_CTRL_0_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_0_SFT 0
+#define TX_SEQ_CTRL_0_0_HI 11
+#define TX_SEQ_CTRL_0_0_SZ 12
+#define TX_ACK_POLICY_0_1_MSK 0x00000003
+#define TX_ACK_POLICY_0_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_1_SFT 0
+#define TX_ACK_POLICY_0_1_HI 1
+#define TX_ACK_POLICY_0_1_SZ 2
+#define TX_SEQ_CTRL_0_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_1_SFT 0
+#define TX_SEQ_CTRL_0_1_HI 11
+#define TX_SEQ_CTRL_0_1_SZ 12
+#define TX_ACK_POLICY_0_2_MSK 0x00000003
+#define TX_ACK_POLICY_0_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_2_SFT 0
+#define TX_ACK_POLICY_0_2_HI 1
+#define TX_ACK_POLICY_0_2_SZ 2
+#define TX_SEQ_CTRL_0_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_2_SFT 0
+#define TX_SEQ_CTRL_0_2_HI 11
+#define TX_SEQ_CTRL_0_2_SZ 12
+#define TX_ACK_POLICY_0_3_MSK 0x00000003
+#define TX_ACK_POLICY_0_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_3_SFT 0
+#define TX_ACK_POLICY_0_3_HI 1
+#define TX_ACK_POLICY_0_3_SZ 2
+#define TX_SEQ_CTRL_0_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_3_SFT 0
+#define TX_SEQ_CTRL_0_3_HI 11
+#define TX_SEQ_CTRL_0_3_SZ 12
+#define TX_ACK_POLICY_0_4_MSK 0x00000003
+#define TX_ACK_POLICY_0_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_4_SFT 0
+#define TX_ACK_POLICY_0_4_HI 1
+#define TX_ACK_POLICY_0_4_SZ 2
+#define TX_SEQ_CTRL_0_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_4_SFT 0
+#define TX_SEQ_CTRL_0_4_HI 11
+#define TX_SEQ_CTRL_0_4_SZ 12
+#define TX_ACK_POLICY_0_5_MSK 0x00000003
+#define TX_ACK_POLICY_0_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_5_SFT 0
+#define TX_ACK_POLICY_0_5_HI 1
+#define TX_ACK_POLICY_0_5_SZ 2
+#define TX_SEQ_CTRL_0_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_5_SFT 0
+#define TX_SEQ_CTRL_0_5_HI 11
+#define TX_SEQ_CTRL_0_5_SZ 12
+#define TX_ACK_POLICY_0_6_MSK 0x00000003
+#define TX_ACK_POLICY_0_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_6_SFT 0
+#define TX_ACK_POLICY_0_6_HI 1
+#define TX_ACK_POLICY_0_6_SZ 2
+#define TX_SEQ_CTRL_0_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_6_SFT 0
+#define TX_SEQ_CTRL_0_6_HI 11
+#define TX_SEQ_CTRL_0_6_SZ 12
+#define TX_ACK_POLICY_0_7_MSK 0x00000003
+#define TX_ACK_POLICY_0_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_0_7_SFT 0
+#define TX_ACK_POLICY_0_7_HI 1
+#define TX_ACK_POLICY_0_7_SZ 2
+#define TX_SEQ_CTRL_0_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_0_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_0_7_SFT 0
+#define TX_SEQ_CTRL_0_7_HI 11
+#define TX_SEQ_CTRL_0_7_SZ 12
+#define VALID1_MSK 0x00000001
+#define VALID1_I_MSK 0xfffffffe
+#define VALID1_SFT 0
+#define VALID1_HI 0
+#define VALID1_SZ 1
+#define PEER_QOS_EN1_MSK 0x00000002
+#define PEER_QOS_EN1_I_MSK 0xfffffffd
+#define PEER_QOS_EN1_SFT 1
+#define PEER_QOS_EN1_HI 1
+#define PEER_QOS_EN1_SZ 1
+#define PEER_OP_MODE1_MSK 0x0000000c
+#define PEER_OP_MODE1_I_MSK 0xfffffff3
+#define PEER_OP_MODE1_SFT 2
+#define PEER_OP_MODE1_HI 3
+#define PEER_OP_MODE1_SZ 2
+#define PEER_HT_MODE1_MSK 0x00000030
+#define PEER_HT_MODE1_I_MSK 0xffffffcf
+#define PEER_HT_MODE1_SFT 4
+#define PEER_HT_MODE1_HI 5
+#define PEER_HT_MODE1_SZ 2
+#define PEER_MAC1_31_0_MSK 0xffffffff
+#define PEER_MAC1_31_0_I_MSK 0x00000000
+#define PEER_MAC1_31_0_SFT 0
+#define PEER_MAC1_31_0_HI 31
+#define PEER_MAC1_31_0_SZ 32
+#define PEER_MAC1_47_32_MSK 0x0000ffff
+#define PEER_MAC1_47_32_I_MSK 0xffff0000
+#define PEER_MAC1_47_32_SFT 0
+#define PEER_MAC1_47_32_HI 15
+#define PEER_MAC1_47_32_SZ 16
+#define TX_ACK_POLICY_1_0_MSK 0x00000003
+#define TX_ACK_POLICY_1_0_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_0_SFT 0
+#define TX_ACK_POLICY_1_0_HI 1
+#define TX_ACK_POLICY_1_0_SZ 2
+#define TX_SEQ_CTRL_1_0_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_0_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_0_SFT 0
+#define TX_SEQ_CTRL_1_0_HI 11
+#define TX_SEQ_CTRL_1_0_SZ 12
+#define TX_ACK_POLICY_1_1_MSK 0x00000003
+#define TX_ACK_POLICY_1_1_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_1_SFT 0
+#define TX_ACK_POLICY_1_1_HI 1
+#define TX_ACK_POLICY_1_1_SZ 2
+#define TX_SEQ_CTRL_1_1_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_1_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_1_SFT 0
+#define TX_SEQ_CTRL_1_1_HI 11
+#define TX_SEQ_CTRL_1_1_SZ 12
+#define TX_ACK_POLICY_1_2_MSK 0x00000003
+#define TX_ACK_POLICY_1_2_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_2_SFT 0
+#define TX_ACK_POLICY_1_2_HI 1
+#define TX_ACK_POLICY_1_2_SZ 2
+#define TX_SEQ_CTRL_1_2_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_2_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_2_SFT 0
+#define TX_SEQ_CTRL_1_2_HI 11
+#define TX_SEQ_CTRL_1_2_SZ 12
+#define TX_ACK_POLICY_1_3_MSK 0x00000003
+#define TX_ACK_POLICY_1_3_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_3_SFT 0
+#define TX_ACK_POLICY_1_3_HI 1
+#define TX_ACK_POLICY_1_3_SZ 2
+#define TX_SEQ_CTRL_1_3_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_3_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_3_SFT 0
+#define TX_SEQ_CTRL_1_3_HI 11
+#define TX_SEQ_CTRL_1_3_SZ 12
+#define TX_ACK_POLICY_1_4_MSK 0x00000003
+#define TX_ACK_POLICY_1_4_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_4_SFT 0
+#define TX_ACK_POLICY_1_4_HI 1
+#define TX_ACK_POLICY_1_4_SZ 2
+#define TX_SEQ_CTRL_1_4_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_4_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_4_SFT 0
+#define TX_SEQ_CTRL_1_4_HI 11
+#define TX_SEQ_CTRL_1_4_SZ 12
+#define TX_ACK_POLICY_1_5_MSK 0x00000003
+#define TX_ACK_POLICY_1_5_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_5_SFT 0
+#define TX_ACK_POLICY_1_5_HI 1
+#define TX_ACK_POLICY_1_5_SZ 2
+#define TX_SEQ_CTRL_1_5_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_5_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_5_SFT 0
+#define TX_SEQ_CTRL_1_5_HI 11
+#define TX_SEQ_CTRL_1_5_SZ 12
+#define TX_ACK_POLICY_1_6_MSK 0x00000003
+#define TX_ACK_POLICY_1_6_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_6_SFT 0
+#define TX_ACK_POLICY_1_6_HI 1
+#define TX_ACK_POLICY_1_6_SZ 2
+#define TX_SEQ_CTRL_1_6_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_6_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_6_SFT 0
+#define TX_SEQ_CTRL_1_6_HI 11
+#define TX_SEQ_CTRL_1_6_SZ 12
+#define TX_ACK_POLICY_1_7_MSK 0x00000003
+#define TX_ACK_POLICY_1_7_I_MSK 0xfffffffc
+#define TX_ACK_POLICY_1_7_SFT 0
+#define TX_ACK_POLICY_1_7_HI 1
+#define TX_ACK_POLICY_1_7_SZ 2
+#define TX_SEQ_CTRL_1_7_MSK 0x00000fff
+#define TX_SEQ_CTRL_1_7_I_MSK 0xfffff000
+#define TX_SEQ_CTRL_1_7_SFT 0
+#define TX_SEQ_CTRL_1_7_HI 11
+#define TX_SEQ_CTRL_1_7_SZ 12
+#define INFO0_MSK 0xffffffff
+#define INFO0_I_MSK 0x00000000
+#define INFO0_SFT 0
+#define INFO0_HI 31
+#define INFO0_SZ 32
+#define INFO1_MSK 0xffffffff
+#define INFO1_I_MSK 0x00000000
+#define INFO1_SFT 0
+#define INFO1_HI 31
+#define INFO1_SZ 32
+#define INFO2_MSK 0xffffffff
+#define INFO2_I_MSK 0x00000000
+#define INFO2_SFT 0
+#define INFO2_HI 31
+#define INFO2_SZ 32
+#define INFO3_MSK 0xffffffff
+#define INFO3_I_MSK 0x00000000
+#define INFO3_SFT 0
+#define INFO3_HI 31
+#define INFO3_SZ 32
+#define INFO4_MSK 0xffffffff
+#define INFO4_I_MSK 0x00000000
+#define INFO4_SFT 0
+#define INFO4_HI 31
+#define INFO4_SZ 32
+#define INFO5_MSK 0xffffffff
+#define INFO5_I_MSK 0x00000000
+#define INFO5_SFT 0
+#define INFO5_HI 31
+#define INFO5_SZ 32
+#define INFO6_MSK 0xffffffff
+#define INFO6_I_MSK 0x00000000
+#define INFO6_SFT 0
+#define INFO6_HI 31
+#define INFO6_SZ 32
+#define INFO7_MSK 0xffffffff
+#define INFO7_I_MSK 0x00000000
+#define INFO7_SFT 0
+#define INFO7_HI 31
+#define INFO7_SZ 32
+#define INFO8_MSK 0xffffffff
+#define INFO8_I_MSK 0x00000000
+#define INFO8_SFT 0
+#define INFO8_HI 31
+#define INFO8_SZ 32
+#define INFO9_MSK 0xffffffff
+#define INFO9_I_MSK 0x00000000
+#define INFO9_SFT 0
+#define INFO9_HI 31
+#define INFO9_SZ 32
+#define INFO10_MSK 0xffffffff
+#define INFO10_I_MSK 0x00000000
+#define INFO10_SFT 0
+#define INFO10_HI 31
+#define INFO10_SZ 32
+#define INFO11_MSK 0xffffffff
+#define INFO11_I_MSK 0x00000000
+#define INFO11_SFT 0
+#define INFO11_HI 31
+#define INFO11_SZ 32
+#define INFO12_MSK 0xffffffff
+#define INFO12_I_MSK 0x00000000
+#define INFO12_SFT 0
+#define INFO12_HI 31
+#define INFO12_SZ 32
+#define INFO13_MSK 0xffffffff
+#define INFO13_I_MSK 0x00000000
+#define INFO13_SFT 0
+#define INFO13_HI 31
+#define INFO13_SZ 32
+#define INFO14_MSK 0xffffffff
+#define INFO14_I_MSK 0x00000000
+#define INFO14_SFT 0
+#define INFO14_HI 31
+#define INFO14_SZ 32
+#define INFO15_MSK 0xffffffff
+#define INFO15_I_MSK 0x00000000
+#define INFO15_SFT 0
+#define INFO15_HI 31
+#define INFO15_SZ 32
+#define INFO16_MSK 0xffffffff
+#define INFO16_I_MSK 0x00000000
+#define INFO16_SFT 0
+#define INFO16_HI 31
+#define INFO16_SZ 32
+#define INFO17_MSK 0xffffffff
+#define INFO17_I_MSK 0x00000000
+#define INFO17_SFT 0
+#define INFO17_HI 31
+#define INFO17_SZ 32
+#define INFO18_MSK 0xffffffff
+#define INFO18_I_MSK 0x00000000
+#define INFO18_SFT 0
+#define INFO18_HI 31
+#define INFO18_SZ 32
+#define INFO19_MSK 0xffffffff
+#define INFO19_I_MSK 0x00000000
+#define INFO19_SFT 0
+#define INFO19_HI 31
+#define INFO19_SZ 32
+#define INFO20_MSK 0xffffffff
+#define INFO20_I_MSK 0x00000000
+#define INFO20_SFT 0
+#define INFO20_HI 31
+#define INFO20_SZ 32
+#define INFO21_MSK 0xffffffff
+#define INFO21_I_MSK 0x00000000
+#define INFO21_SFT 0
+#define INFO21_HI 31
+#define INFO21_SZ 32
+#define INFO22_MSK 0xffffffff
+#define INFO22_I_MSK 0x00000000
+#define INFO22_SFT 0
+#define INFO22_HI 31
+#define INFO22_SZ 32
+#define INFO23_MSK 0xffffffff
+#define INFO23_I_MSK 0x00000000
+#define INFO23_SFT 0
+#define INFO23_HI 31
+#define INFO23_SZ 32
+#define INFO24_MSK 0xffffffff
+#define INFO24_I_MSK 0x00000000
+#define INFO24_SFT 0
+#define INFO24_HI 31
+#define INFO24_SZ 32
+#define INFO25_MSK 0xffffffff
+#define INFO25_I_MSK 0x00000000
+#define INFO25_SFT 0
+#define INFO25_HI 31
+#define INFO25_SZ 32
+#define INFO26_MSK 0xffffffff
+#define INFO26_I_MSK 0x00000000
+#define INFO26_SFT 0
+#define INFO26_HI 31
+#define INFO26_SZ 32
+#define INFO27_MSK 0xffffffff
+#define INFO27_I_MSK 0x00000000
+#define INFO27_SFT 0
+#define INFO27_HI 31
+#define INFO27_SZ 32
+#define INFO28_MSK 0xffffffff
+#define INFO28_I_MSK 0x00000000
+#define INFO28_SFT 0
+#define INFO28_HI 31
+#define INFO28_SZ 32
+#define INFO29_MSK 0xffffffff
+#define INFO29_I_MSK 0x00000000
+#define INFO29_SFT 0
+#define INFO29_HI 31
+#define INFO29_SZ 32
+#define INFO30_MSK 0xffffffff
+#define INFO30_I_MSK 0x00000000
+#define INFO30_SFT 0
+#define INFO30_HI 31
+#define INFO30_SZ 32
+#define INFO31_MSK 0xffffffff
+#define INFO31_I_MSK 0x00000000
+#define INFO31_SFT 0
+#define INFO31_HI 31
+#define INFO31_SZ 32
+#define INFO32_MSK 0xffffffff
+#define INFO32_I_MSK 0x00000000
+#define INFO32_SFT 0
+#define INFO32_HI 31
+#define INFO32_SZ 32
+#define INFO33_MSK 0xffffffff
+#define INFO33_I_MSK 0x00000000
+#define INFO33_SFT 0
+#define INFO33_HI 31
+#define INFO33_SZ 32
+#define INFO34_MSK 0xffffffff
+#define INFO34_I_MSK 0x00000000
+#define INFO34_SFT 0
+#define INFO34_HI 31
+#define INFO34_SZ 32
+#define INFO35_MSK 0xffffffff
+#define INFO35_I_MSK 0x00000000
+#define INFO35_SFT 0
+#define INFO35_HI 31
+#define INFO35_SZ 32
+#define INFO36_MSK 0xffffffff
+#define INFO36_I_MSK 0x00000000
+#define INFO36_SFT 0
+#define INFO36_HI 31
+#define INFO36_SZ 32
+#define INFO37_MSK 0xffffffff
+#define INFO37_I_MSK 0x00000000
+#define INFO37_SFT 0
+#define INFO37_HI 31
+#define INFO37_SZ 32
+#define INFO38_MSK 0xffffffff
+#define INFO38_I_MSK 0x00000000
+#define INFO38_SFT 0
+#define INFO38_HI 31
+#define INFO38_SZ 32
+#define INFO_MASK_MSK 0xffffffff
+#define INFO_MASK_I_MSK 0x00000000
+#define INFO_MASK_SFT 0
+#define INFO_MASK_HI 31
+#define INFO_MASK_SZ 32
+#define INFO_DEF_RATE_MSK 0x0000003f
+#define INFO_DEF_RATE_I_MSK 0xffffffc0
+#define INFO_DEF_RATE_SFT 0
+#define INFO_DEF_RATE_HI 5
+#define INFO_DEF_RATE_SZ 6
+#define INFO_MRX_OFFSET_MSK 0x000f0000
+#define INFO_MRX_OFFSET_I_MSK 0xfff0ffff
+#define INFO_MRX_OFFSET_SFT 16
+#define INFO_MRX_OFFSET_HI 19
+#define INFO_MRX_OFFSET_SZ 4
+#define BCAST_RATEUNKNOW_MSK 0x3f000000
+#define BCAST_RATEUNKNOW_I_MSK 0xc0ffffff
+#define BCAST_RATEUNKNOW_SFT 24
+#define BCAST_RATEUNKNOW_HI 29
+#define BCAST_RATEUNKNOW_SZ 6
+#define INFO_IDX_TBL_ADDR_MSK 0xffffffff
+#define INFO_IDX_TBL_ADDR_I_MSK 0x00000000
+#define INFO_IDX_TBL_ADDR_SFT 0
+#define INFO_IDX_TBL_ADDR_HI 31
+#define INFO_IDX_TBL_ADDR_SZ 32
+#define INFO_LEN_TBL_ADDR_MSK 0xffffffff
+#define INFO_LEN_TBL_ADDR_I_MSK 0x00000000
+#define INFO_LEN_TBL_ADDR_SFT 0
+#define INFO_LEN_TBL_ADDR_HI 31
+#define INFO_LEN_TBL_ADDR_SZ 32
+#define IC_TAG_31_0_MSK 0xffffffff
+#define IC_TAG_31_0_I_MSK 0x00000000
+#define IC_TAG_31_0_SFT 0
+#define IC_TAG_31_0_HI 31
+#define IC_TAG_31_0_SZ 32
+#define IC_TAG_63_32_MSK 0xffffffff
+#define IC_TAG_63_32_I_MSK 0x00000000
+#define IC_TAG_63_32_SFT 0
+#define IC_TAG_63_32_HI 31
+#define IC_TAG_63_32_SZ 32
+#define CH1_PRI_MSK 0x00000003
+#define CH1_PRI_I_MSK 0xfffffffc
+#define CH1_PRI_SFT 0
+#define CH1_PRI_HI 1
+#define CH1_PRI_SZ 2
+#define CH2_PRI_MSK 0x00000300
+#define CH2_PRI_I_MSK 0xfffffcff
+#define CH2_PRI_SFT 8
+#define CH2_PRI_HI 9
+#define CH2_PRI_SZ 2
+#define CH3_PRI_MSK 0x00030000
+#define CH3_PRI_I_MSK 0xfffcffff
+#define CH3_PRI_SFT 16
+#define CH3_PRI_HI 17
+#define CH3_PRI_SZ 2
+#define RG_MAC_LPBK_MSK 0x00000001
+#define RG_MAC_LPBK_I_MSK 0xfffffffe
+#define RG_MAC_LPBK_SFT 0
+#define RG_MAC_LPBK_HI 0
+#define RG_MAC_LPBK_SZ 1
+#define RG_MAC_M2M_MSK 0x00000002
+#define RG_MAC_M2M_I_MSK 0xfffffffd
+#define RG_MAC_M2M_SFT 1
+#define RG_MAC_M2M_HI 1
+#define RG_MAC_M2M_SZ 1
+#define RG_PHY_LPBK_MSK 0x00000004
+#define RG_PHY_LPBK_I_MSK 0xfffffffb
+#define RG_PHY_LPBK_SFT 2
+#define RG_PHY_LPBK_HI 2
+#define RG_PHY_LPBK_SZ 1
+#define RG_LPBK_RX_EN_MSK 0x00000008
+#define RG_LPBK_RX_EN_I_MSK 0xfffffff7
+#define RG_LPBK_RX_EN_SFT 3
+#define RG_LPBK_RX_EN_HI 3
+#define RG_LPBK_RX_EN_SZ 1
+#define EXT_MAC_MODE_MSK 0x00000010
+#define EXT_MAC_MODE_I_MSK 0xffffffef
+#define EXT_MAC_MODE_SFT 4
+#define EXT_MAC_MODE_HI 4
+#define EXT_MAC_MODE_SZ 1
+#define EXT_PHY_MODE_MSK 0x00000020
+#define EXT_PHY_MODE_I_MSK 0xffffffdf
+#define EXT_PHY_MODE_SFT 5
+#define EXT_PHY_MODE_HI 5
+#define EXT_PHY_MODE_SZ 1
+#define ASIC_TAG_MSK 0xff000000
+#define ASIC_TAG_I_MSK 0x00ffffff
+#define ASIC_TAG_SFT 24
+#define ASIC_TAG_HI 31
+#define ASIC_TAG_SZ 8
+#define HCI_SW_RST_MSK 0x00000001
+#define HCI_SW_RST_I_MSK 0xfffffffe
+#define HCI_SW_RST_SFT 0
+#define HCI_SW_RST_HI 0
+#define HCI_SW_RST_SZ 1
+#define CO_PROC_SW_RST_MSK 0x00000002
+#define CO_PROC_SW_RST_I_MSK 0xfffffffd
+#define CO_PROC_SW_RST_SFT 1
+#define CO_PROC_SW_RST_HI 1
+#define CO_PROC_SW_RST_SZ 1
+#define MTX_MISC_SW_RST_MSK 0x00000008
+#define MTX_MISC_SW_RST_I_MSK 0xfffffff7
+#define MTX_MISC_SW_RST_SFT 3
+#define MTX_MISC_SW_RST_HI 3
+#define MTX_MISC_SW_RST_SZ 1
+#define MTX_QUE_SW_RST_MSK 0x00000010
+#define MTX_QUE_SW_RST_I_MSK 0xffffffef
+#define MTX_QUE_SW_RST_SFT 4
+#define MTX_QUE_SW_RST_HI 4
+#define MTX_QUE_SW_RST_SZ 1
+#define MTX_CHST_SW_RST_MSK 0x00000020
+#define MTX_CHST_SW_RST_I_MSK 0xffffffdf
+#define MTX_CHST_SW_RST_SFT 5
+#define MTX_CHST_SW_RST_HI 5
+#define MTX_CHST_SW_RST_SZ 1
+#define MTX_BCN_SW_RST_MSK 0x00000040
+#define MTX_BCN_SW_RST_I_MSK 0xffffffbf
+#define MTX_BCN_SW_RST_SFT 6
+#define MTX_BCN_SW_RST_HI 6
+#define MTX_BCN_SW_RST_SZ 1
+#define MRX_SW_RST_MSK 0x00000080
+#define MRX_SW_RST_I_MSK 0xffffff7f
+#define MRX_SW_RST_SFT 7
+#define MRX_SW_RST_HI 7
+#define MRX_SW_RST_SZ 1
+#define AMPDU_SW_RST_MSK 0x00000100
+#define AMPDU_SW_RST_I_MSK 0xfffffeff
+#define AMPDU_SW_RST_SFT 8
+#define AMPDU_SW_RST_HI 8
+#define AMPDU_SW_RST_SZ 1
+#define MMU_SW_RST_MSK 0x00000200
+#define MMU_SW_RST_I_MSK 0xfffffdff
+#define MMU_SW_RST_SFT 9
+#define MMU_SW_RST_HI 9
+#define MMU_SW_RST_SZ 1
+#define ID_MNG_SW_RST_MSK 0x00000800
+#define ID_MNG_SW_RST_I_MSK 0xfffff7ff
+#define ID_MNG_SW_RST_SFT 11
+#define ID_MNG_SW_RST_HI 11
+#define ID_MNG_SW_RST_SZ 1
+#define MBOX_SW_RST_MSK 0x00001000
+#define MBOX_SW_RST_I_MSK 0xffffefff
+#define MBOX_SW_RST_SFT 12
+#define MBOX_SW_RST_HI 12
+#define MBOX_SW_RST_SZ 1
+#define SCRT_SW_RST_MSK 0x00002000
+#define SCRT_SW_RST_I_MSK 0xffffdfff
+#define SCRT_SW_RST_SFT 13
+#define SCRT_SW_RST_HI 13
+#define SCRT_SW_RST_SZ 1
+#define MIC_SW_RST_MSK 0x00004000
+#define MIC_SW_RST_I_MSK 0xffffbfff
+#define MIC_SW_RST_SFT 14
+#define MIC_SW_RST_HI 14
+#define MIC_SW_RST_SZ 1
+#define CO_PROC_ENG_RST_MSK 0x00000002
+#define CO_PROC_ENG_RST_I_MSK 0xfffffffd
+#define CO_PROC_ENG_RST_SFT 1
+#define CO_PROC_ENG_RST_HI 1
+#define CO_PROC_ENG_RST_SZ 1
+#define MTX_MISC_ENG_RST_MSK 0x00000008
+#define MTX_MISC_ENG_RST_I_MSK 0xfffffff7
+#define MTX_MISC_ENG_RST_SFT 3
+#define MTX_MISC_ENG_RST_HI 3
+#define MTX_MISC_ENG_RST_SZ 1
+#define MTX_QUE_ENG_RST_MSK 0x00000010
+#define MTX_QUE_ENG_RST_I_MSK 0xffffffef
+#define MTX_QUE_ENG_RST_SFT 4
+#define MTX_QUE_ENG_RST_HI 4
+#define MTX_QUE_ENG_RST_SZ 1
+#define MTX_CHST_ENG_RST_MSK 0x00000020
+#define MTX_CHST_ENG_RST_I_MSK 0xffffffdf
+#define MTX_CHST_ENG_RST_SFT 5
+#define MTX_CHST_ENG_RST_HI 5
+#define MTX_CHST_ENG_RST_SZ 1
+#define MTX_BCN_ENG_RST_MSK 0x00000040
+#define MTX_BCN_ENG_RST_I_MSK 0xffffffbf
+#define MTX_BCN_ENG_RST_SFT 6
+#define MTX_BCN_ENG_RST_HI 6
+#define MTX_BCN_ENG_RST_SZ 1
+#define MRX_ENG_RST_MSK 0x00000080
+#define MRX_ENG_RST_I_MSK 0xffffff7f
+#define MRX_ENG_RST_SFT 7
+#define MRX_ENG_RST_HI 7
+#define MRX_ENG_RST_SZ 1
+#define AMPDU_ENG_RST_MSK 0x00000100
+#define AMPDU_ENG_RST_I_MSK 0xfffffeff
+#define AMPDU_ENG_RST_SFT 8
+#define AMPDU_ENG_RST_HI 8
+#define AMPDU_ENG_RST_SZ 1
+#define ID_MNG_ENG_RST_MSK 0x00004000
+#define ID_MNG_ENG_RST_I_MSK 0xffffbfff
+#define ID_MNG_ENG_RST_SFT 14
+#define ID_MNG_ENG_RST_HI 14
+#define ID_MNG_ENG_RST_SZ 1
+#define MBOX_ENG_RST_MSK 0x00008000
+#define MBOX_ENG_RST_I_MSK 0xffff7fff
+#define MBOX_ENG_RST_SFT 15
+#define MBOX_ENG_RST_HI 15
+#define MBOX_ENG_RST_SZ 1
+#define SCRT_ENG_RST_MSK 0x00010000
+#define SCRT_ENG_RST_I_MSK 0xfffeffff
+#define SCRT_ENG_RST_SFT 16
+#define SCRT_ENG_RST_HI 16
+#define SCRT_ENG_RST_SZ 1
+#define MIC_ENG_RST_MSK 0x00020000
+#define MIC_ENG_RST_I_MSK 0xfffdffff
+#define MIC_ENG_RST_SFT 17
+#define MIC_ENG_RST_HI 17
+#define MIC_ENG_RST_SZ 1
+#define CO_PROC_CSR_RST_MSK 0x00000002
+#define CO_PROC_CSR_RST_I_MSK 0xfffffffd
+#define CO_PROC_CSR_RST_SFT 1
+#define CO_PROC_CSR_RST_HI 1
+#define CO_PROC_CSR_RST_SZ 1
+#define MTX_MISC_CSR_RST_MSK 0x00000008
+#define MTX_MISC_CSR_RST_I_MSK 0xfffffff7
+#define MTX_MISC_CSR_RST_SFT 3
+#define MTX_MISC_CSR_RST_HI 3
+#define MTX_MISC_CSR_RST_SZ 1
+#define MTX_QUE0_CSR_RST_MSK 0x00000010
+#define MTX_QUE0_CSR_RST_I_MSK 0xffffffef
+#define MTX_QUE0_CSR_RST_SFT 4
+#define MTX_QUE0_CSR_RST_HI 4
+#define MTX_QUE0_CSR_RST_SZ 1
+#define MTX_QUE1_CSR_RST_MSK 0x00000020
+#define MTX_QUE1_CSR_RST_I_MSK 0xffffffdf
+#define MTX_QUE1_CSR_RST_SFT 5
+#define MTX_QUE1_CSR_RST_HI 5
+#define MTX_QUE1_CSR_RST_SZ 1
+#define MTX_QUE2_CSR_RST_MSK 0x00000040
+#define MTX_QUE2_CSR_RST_I_MSK 0xffffffbf
+#define MTX_QUE2_CSR_RST_SFT 6
+#define MTX_QUE2_CSR_RST_HI 6
+#define MTX_QUE2_CSR_RST_SZ 1
+#define MTX_QUE3_CSR_RST_MSK 0x00000080
+#define MTX_QUE3_CSR_RST_I_MSK 0xffffff7f
+#define MTX_QUE3_CSR_RST_SFT 7
+#define MTX_QUE3_CSR_RST_HI 7
+#define MTX_QUE3_CSR_RST_SZ 1
+#define MTX_QUE4_CSR_RST_MSK 0x00000100
+#define MTX_QUE4_CSR_RST_I_MSK 0xfffffeff
+#define MTX_QUE4_CSR_RST_SFT 8
+#define MTX_QUE4_CSR_RST_HI 8
+#define MTX_QUE4_CSR_RST_SZ 1
+#define MTX_QUE5_CSR_RST_MSK 0x00000200
+#define MTX_QUE5_CSR_RST_I_MSK 0xfffffdff
+#define MTX_QUE5_CSR_RST_SFT 9
+#define MTX_QUE5_CSR_RST_HI 9
+#define MTX_QUE5_CSR_RST_SZ 1
+#define MRX_CSR_RST_MSK 0x00000400
+#define MRX_CSR_RST_I_MSK 0xfffffbff
+#define MRX_CSR_RST_SFT 10
+#define MRX_CSR_RST_HI 10
+#define MRX_CSR_RST_SZ 1
+#define AMPDU_CSR_RST_MSK 0x00000800
+#define AMPDU_CSR_RST_I_MSK 0xfffff7ff
+#define AMPDU_CSR_RST_SFT 11
+#define AMPDU_CSR_RST_HI 11
+#define AMPDU_CSR_RST_SZ 1
+#define SCRT_CSR_RST_MSK 0x00002000
+#define SCRT_CSR_RST_I_MSK 0xffffdfff
+#define SCRT_CSR_RST_SFT 13
+#define SCRT_CSR_RST_HI 13
+#define SCRT_CSR_RST_SZ 1
+#define ID_MNG_CSR_RST_MSK 0x00004000
+#define ID_MNG_CSR_RST_I_MSK 0xffffbfff
+#define ID_MNG_CSR_RST_SFT 14
+#define ID_MNG_CSR_RST_HI 14
+#define ID_MNG_CSR_RST_SZ 1
+#define MBOX_CSR_RST_MSK 0x00008000
+#define MBOX_CSR_RST_I_MSK 0xffff7fff
+#define MBOX_CSR_RST_SFT 15
+#define MBOX_CSR_RST_HI 15
+#define MBOX_CSR_RST_SZ 1
+#define HCI_CLK_EN_MSK 0x00000001
+#define HCI_CLK_EN_I_MSK 0xfffffffe
+#define HCI_CLK_EN_SFT 0
+#define HCI_CLK_EN_HI 0
+#define HCI_CLK_EN_SZ 1
+#define CO_PROC_CLK_EN_MSK 0x00000002
+#define CO_PROC_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_CLK_EN_SFT 1
+#define CO_PROC_CLK_EN_HI 1
+#define CO_PROC_CLK_EN_SZ 1
+#define MTX_MISC_CLK_EN_MSK 0x00000008
+#define MTX_MISC_CLK_EN_I_MSK 0xfffffff7
+#define MTX_MISC_CLK_EN_SFT 3
+#define MTX_MISC_CLK_EN_HI 3
+#define MTX_MISC_CLK_EN_SZ 1
+#define MTX_QUE_CLK_EN_MSK 0x00000010
+#define MTX_QUE_CLK_EN_I_MSK 0xffffffef
+#define MTX_QUE_CLK_EN_SFT 4
+#define MTX_QUE_CLK_EN_HI 4
+#define MTX_QUE_CLK_EN_SZ 1
+#define MRX_CLK_EN_MSK 0x00000020
+#define MRX_CLK_EN_I_MSK 0xffffffdf
+#define MRX_CLK_EN_SFT 5
+#define MRX_CLK_EN_HI 5
+#define MRX_CLK_EN_SZ 1
+#define AMPDU_CLK_EN_MSK 0x00000040
+#define AMPDU_CLK_EN_I_MSK 0xffffffbf
+#define AMPDU_CLK_EN_SFT 6
+#define AMPDU_CLK_EN_HI 6
+#define AMPDU_CLK_EN_SZ 1
+#define MMU_CLK_EN_MSK 0x00000080
+#define MMU_CLK_EN_I_MSK 0xffffff7f
+#define MMU_CLK_EN_SFT 7
+#define MMU_CLK_EN_HI 7
+#define MMU_CLK_EN_SZ 1
+#define ID_MNG_CLK_EN_MSK 0x00000200
+#define ID_MNG_CLK_EN_I_MSK 0xfffffdff
+#define ID_MNG_CLK_EN_SFT 9
+#define ID_MNG_CLK_EN_HI 9
+#define ID_MNG_CLK_EN_SZ 1
+#define MBOX_CLK_EN_MSK 0x00000400
+#define MBOX_CLK_EN_I_MSK 0xfffffbff
+#define MBOX_CLK_EN_SFT 10
+#define MBOX_CLK_EN_HI 10
+#define MBOX_CLK_EN_SZ 1
+#define SCRT_CLK_EN_MSK 0x00000800
+#define SCRT_CLK_EN_I_MSK 0xfffff7ff
+#define SCRT_CLK_EN_SFT 11
+#define SCRT_CLK_EN_HI 11
+#define SCRT_CLK_EN_SZ 1
+#define MIC_CLK_EN_MSK 0x00001000
+#define MIC_CLK_EN_I_MSK 0xffffefff
+#define MIC_CLK_EN_SFT 12
+#define MIC_CLK_EN_HI 12
+#define MIC_CLK_EN_SZ 1
+#define MIB_CLK_EN_MSK 0x00002000
+#define MIB_CLK_EN_I_MSK 0xffffdfff
+#define MIB_CLK_EN_SFT 13
+#define MIB_CLK_EN_HI 13
+#define MIB_CLK_EN_SZ 1
+#define HCI_ENG_CLK_EN_MSK 0x00000001
+#define HCI_ENG_CLK_EN_I_MSK 0xfffffffe
+#define HCI_ENG_CLK_EN_SFT 0
+#define HCI_ENG_CLK_EN_HI 0
+#define HCI_ENG_CLK_EN_SZ 1
+#define CO_PROC_ENG_CLK_EN_MSK 0x00000002
+#define CO_PROC_ENG_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_ENG_CLK_EN_SFT 1
+#define CO_PROC_ENG_CLK_EN_HI 1
+#define CO_PROC_ENG_CLK_EN_SZ 1
+#define MTX_MISC_ENG_CLK_EN_MSK 0x00000008
+#define MTX_MISC_ENG_CLK_EN_I_MSK 0xfffffff7
+#define MTX_MISC_ENG_CLK_EN_SFT 3
+#define MTX_MISC_ENG_CLK_EN_HI 3
+#define MTX_MISC_ENG_CLK_EN_SZ 1
+#define MTX_QUE_ENG_CLK_EN_MSK 0x00000010
+#define MTX_QUE_ENG_CLK_EN_I_MSK 0xffffffef
+#define MTX_QUE_ENG_CLK_EN_SFT 4
+#define MTX_QUE_ENG_CLK_EN_HI 4
+#define MTX_QUE_ENG_CLK_EN_SZ 1
+#define MRX_ENG_CLK_EN_MSK 0x00000020
+#define MRX_ENG_CLK_EN_I_MSK 0xffffffdf
+#define MRX_ENG_CLK_EN_SFT 5
+#define MRX_ENG_CLK_EN_HI 5
+#define MRX_ENG_CLK_EN_SZ 1
+#define AMPDU_ENG_CLK_EN_MSK 0x00000040
+#define AMPDU_ENG_CLK_EN_I_MSK 0xffffffbf
+#define AMPDU_ENG_CLK_EN_SFT 6
+#define AMPDU_ENG_CLK_EN_HI 6
+#define AMPDU_ENG_CLK_EN_SZ 1
+#define ID_MNG_ENG_CLK_EN_MSK 0x00001000
+#define ID_MNG_ENG_CLK_EN_I_MSK 0xffffefff
+#define ID_MNG_ENG_CLK_EN_SFT 12
+#define ID_MNG_ENG_CLK_EN_HI 12
+#define ID_MNG_ENG_CLK_EN_SZ 1
+#define MBOX_ENG_CLK_EN_MSK 0x00002000
+#define MBOX_ENG_CLK_EN_I_MSK 0xffffdfff
+#define MBOX_ENG_CLK_EN_SFT 13
+#define MBOX_ENG_CLK_EN_HI 13
+#define MBOX_ENG_CLK_EN_SZ 1
+#define SCRT_ENG_CLK_EN_MSK 0x00004000
+#define SCRT_ENG_CLK_EN_I_MSK 0xffffbfff
+#define SCRT_ENG_CLK_EN_SFT 14
+#define SCRT_ENG_CLK_EN_HI 14
+#define SCRT_ENG_CLK_EN_SZ 1
+#define MIC_ENG_CLK_EN_MSK 0x00008000
+#define MIC_ENG_CLK_EN_I_MSK 0xffff7fff
+#define MIC_ENG_CLK_EN_SFT 15
+#define MIC_ENG_CLK_EN_HI 15
+#define MIC_ENG_CLK_EN_SZ 1
+#define CO_PROC_CSR_CLK_EN_MSK 0x00000002
+#define CO_PROC_CSR_CLK_EN_I_MSK 0xfffffffd
+#define CO_PROC_CSR_CLK_EN_SFT 1
+#define CO_PROC_CSR_CLK_EN_HI 1
+#define CO_PROC_CSR_CLK_EN_SZ 1
+#define MRX_CSR_CLK_EN_MSK 0x00000400
+#define MRX_CSR_CLK_EN_I_MSK 0xfffffbff
+#define MRX_CSR_CLK_EN_SFT 10
+#define MRX_CSR_CLK_EN_HI 10
+#define MRX_CSR_CLK_EN_SZ 1
+#define AMPDU_CSR_CLK_EN_MSK 0x00000800
+#define AMPDU_CSR_CLK_EN_I_MSK 0xfffff7ff
+#define AMPDU_CSR_CLK_EN_SFT 11
+#define AMPDU_CSR_CLK_EN_HI 11
+#define AMPDU_CSR_CLK_EN_SZ 1
+#define SCRT_CSR_CLK_EN_MSK 0x00002000
+#define SCRT_CSR_CLK_EN_I_MSK 0xffffdfff
+#define SCRT_CSR_CLK_EN_SFT 13
+#define SCRT_CSR_CLK_EN_HI 13
+#define SCRT_CSR_CLK_EN_SZ 1
+#define ID_MNG_CSR_CLK_EN_MSK 0x00004000
+#define ID_MNG_CSR_CLK_EN_I_MSK 0xffffbfff
+#define ID_MNG_CSR_CLK_EN_SFT 14
+#define ID_MNG_CSR_CLK_EN_HI 14
+#define ID_MNG_CSR_CLK_EN_SZ 1
+#define MBOX_CSR_CLK_EN_MSK 0x00008000
+#define MBOX_CSR_CLK_EN_I_MSK 0xffff7fff
+#define MBOX_CSR_CLK_EN_SFT 15
+#define MBOX_CSR_CLK_EN_HI 15
+#define MBOX_CSR_CLK_EN_SZ 1
+#define OP_MODE_MSK 0x00000003
+#define OP_MODE_I_MSK 0xfffffffc
+#define OP_MODE_SFT 0
+#define OP_MODE_HI 1
+#define OP_MODE_SZ 2
+#define HT_MODE_MSK 0x0000000c
+#define HT_MODE_I_MSK 0xfffffff3
+#define HT_MODE_SFT 2
+#define HT_MODE_HI 3
+#define HT_MODE_SZ 2
+#define QOS_EN_MSK 0x00000010
+#define QOS_EN_I_MSK 0xffffffef
+#define QOS_EN_SFT 4
+#define QOS_EN_HI 4
+#define QOS_EN_SZ 1
+#define PB_OFFSET_MSK 0x0000ff00
+#define PB_OFFSET_I_MSK 0xffff00ff
+#define PB_OFFSET_SFT 8
+#define PB_OFFSET_HI 15
+#define PB_OFFSET_SZ 8
+#define SNIFFER_MODE_MSK 0x00010000
+#define SNIFFER_MODE_I_MSK 0xfffeffff
+#define SNIFFER_MODE_SFT 16
+#define SNIFFER_MODE_HI 16
+#define SNIFFER_MODE_SZ 1
+#define DUP_FLT_MSK 0x00020000
+#define DUP_FLT_I_MSK 0xfffdffff
+#define DUP_FLT_SFT 17
+#define DUP_FLT_HI 17
+#define DUP_FLT_SZ 1
+#define TX_PKT_RSVD_MSK 0x001c0000
+#define TX_PKT_RSVD_I_MSK 0xffe3ffff
+#define TX_PKT_RSVD_SFT 18
+#define TX_PKT_RSVD_HI 20
+#define TX_PKT_RSVD_SZ 3
+#define AMPDU_SNIFFER_MSK 0x00200000
+#define AMPDU_SNIFFER_I_MSK 0xffdfffff
+#define AMPDU_SNIFFER_SFT 21
+#define AMPDU_SNIFFER_HI 21
+#define AMPDU_SNIFFER_SZ 1
+#define REASON_TRAP0_MSK 0xffffffff
+#define REASON_TRAP0_I_MSK 0x00000000
+#define REASON_TRAP0_SFT 0
+#define REASON_TRAP0_HI 31
+#define REASON_TRAP0_SZ 32
+#define REASON_TRAP1_MSK 0xffffffff
+#define REASON_TRAP1_I_MSK 0x00000000
+#define REASON_TRAP1_SFT 0
+#define REASON_TRAP1_HI 31
+#define REASON_TRAP1_SZ 32
+#define BSSID_31_0_MSK 0xffffffff
+#define BSSID_31_0_I_MSK 0x00000000
+#define BSSID_31_0_SFT 0
+#define BSSID_31_0_HI 31
+#define BSSID_31_0_SZ 32
+#define BSSID_47_32_MSK 0x0000ffff
+#define BSSID_47_32_I_MSK 0xffff0000
+#define BSSID_47_32_SFT 0
+#define BSSID_47_32_HI 15
+#define BSSID_47_32_SZ 16
+#define SCRT_STATE_MSK 0x0000000f
+#define SCRT_STATE_I_MSK 0xfffffff0
+#define SCRT_STATE_SFT 0
+#define SCRT_STATE_HI 3
+#define SCRT_STATE_SZ 4
+#define STA_MAC_31_0_MSK 0xffffffff
+#define STA_MAC_31_0_I_MSK 0x00000000
+#define STA_MAC_31_0_SFT 0
+#define STA_MAC_31_0_HI 31
+#define STA_MAC_31_0_SZ 32
+#define STA_MAC_47_32_MSK 0x0000ffff
+#define STA_MAC_47_32_I_MSK 0xffff0000
+#define STA_MAC_47_32_SFT 0
+#define STA_MAC_47_32_HI 15
+#define STA_MAC_47_32_SZ 16
+#define PAIR_SCRT_MSK 0x00000007
+#define PAIR_SCRT_I_MSK 0xfffffff8
+#define PAIR_SCRT_SFT 0
+#define PAIR_SCRT_HI 2
+#define PAIR_SCRT_SZ 3
+#define GRP_SCRT_MSK 0x00000038
+#define GRP_SCRT_I_MSK 0xffffffc7
+#define GRP_SCRT_SFT 3
+#define GRP_SCRT_HI 5
+#define GRP_SCRT_SZ 3
+#define SCRT_PKT_ID_MSK 0x00001fc0
+#define SCRT_PKT_ID_I_MSK 0xffffe03f
+#define SCRT_PKT_ID_SFT 6
+#define SCRT_PKT_ID_HI 12
+#define SCRT_PKT_ID_SZ 7
+#define SCRT_RPLY_IGNORE_MSK 0x00010000
+#define SCRT_RPLY_IGNORE_I_MSK 0xfffeffff
+#define SCRT_RPLY_IGNORE_SFT 16
+#define SCRT_RPLY_IGNORE_HI 16
+#define SCRT_RPLY_IGNORE_SZ 1
+#define COEXIST_EN_MSK 0x00000001
+#define COEXIST_EN_I_MSK 0xfffffffe
+#define COEXIST_EN_SFT 0
+#define COEXIST_EN_HI 0
+#define COEXIST_EN_SZ 1
+#define WIRE_MODE_MSK 0x0000000e
+#define WIRE_MODE_I_MSK 0xfffffff1
+#define WIRE_MODE_SFT 1
+#define WIRE_MODE_HI 3
+#define WIRE_MODE_SZ 3
+#define WL_RX_PRI_MSK 0x00000010
+#define WL_RX_PRI_I_MSK 0xffffffef
+#define WL_RX_PRI_SFT 4
+#define WL_RX_PRI_HI 4
+#define WL_RX_PRI_SZ 1
+#define WL_TX_PRI_MSK 0x00000020
+#define WL_TX_PRI_I_MSK 0xffffffdf
+#define WL_TX_PRI_SFT 5
+#define WL_TX_PRI_HI 5
+#define WL_TX_PRI_SZ 1
+#define GURAN_USE_EN_MSK 0x00000100
+#define GURAN_USE_EN_I_MSK 0xfffffeff
+#define GURAN_USE_EN_SFT 8
+#define GURAN_USE_EN_HI 8
+#define GURAN_USE_EN_SZ 1
+#define GURAN_USE_CTRL_MSK 0x00000200
+#define GURAN_USE_CTRL_I_MSK 0xfffffdff
+#define GURAN_USE_CTRL_SFT 9
+#define GURAN_USE_CTRL_HI 9
+#define GURAN_USE_CTRL_SZ 1
+#define BEACON_TIMEOUT_EN_MSK 0x00000400
+#define BEACON_TIMEOUT_EN_I_MSK 0xfffffbff
+#define BEACON_TIMEOUT_EN_SFT 10
+#define BEACON_TIMEOUT_EN_HI 10
+#define BEACON_TIMEOUT_EN_SZ 1
+#define WLAN_ACT_POL_MSK 0x00000800
+#define WLAN_ACT_POL_I_MSK 0xfffff7ff
+#define WLAN_ACT_POL_SFT 11
+#define WLAN_ACT_POL_HI 11
+#define WLAN_ACT_POL_SZ 1
+#define DUAL_ANT_EN_MSK 0x00001000
+#define DUAL_ANT_EN_I_MSK 0xffffefff
+#define DUAL_ANT_EN_SFT 12
+#define DUAL_ANT_EN_HI 12
+#define DUAL_ANT_EN_SZ 1
+#define TRSW_PHY_POL_MSK 0x00010000
+#define TRSW_PHY_POL_I_MSK 0xfffeffff
+#define TRSW_PHY_POL_SFT 16
+#define TRSW_PHY_POL_HI 16
+#define TRSW_PHY_POL_SZ 1
+#define WIFI_TX_SW_POL_MSK 0x00020000
+#define WIFI_TX_SW_POL_I_MSK 0xfffdffff
+#define WIFI_TX_SW_POL_SFT 17
+#define WIFI_TX_SW_POL_HI 17
+#define WIFI_TX_SW_POL_SZ 1
+#define WIFI_RX_SW_POL_MSK 0x00040000
+#define WIFI_RX_SW_POL_I_MSK 0xfffbffff
+#define WIFI_RX_SW_POL_SFT 18
+#define WIFI_RX_SW_POL_HI 18
+#define WIFI_RX_SW_POL_SZ 1
+#define BT_SW_POL_MSK 0x00080000
+#define BT_SW_POL_I_MSK 0xfff7ffff
+#define BT_SW_POL_SFT 19
+#define BT_SW_POL_HI 19
+#define BT_SW_POL_SZ 1
+#define BT_PRI_SMP_TIME_MSK 0x000000ff
+#define BT_PRI_SMP_TIME_I_MSK 0xffffff00
+#define BT_PRI_SMP_TIME_SFT 0
+#define BT_PRI_SMP_TIME_HI 7
+#define BT_PRI_SMP_TIME_SZ 8
+#define BT_STA_SMP_TIME_MSK 0x0000ff00
+#define BT_STA_SMP_TIME_I_MSK 0xffff00ff
+#define BT_STA_SMP_TIME_SFT 8
+#define BT_STA_SMP_TIME_HI 15
+#define BT_STA_SMP_TIME_SZ 8
+#define BEACON_TIMEOUT_MSK 0x00ff0000
+#define BEACON_TIMEOUT_I_MSK 0xff00ffff
+#define BEACON_TIMEOUT_SFT 16
+#define BEACON_TIMEOUT_HI 23
+#define BEACON_TIMEOUT_SZ 8
+#define WLAN_REMAIN_TIME_MSK 0xff000000
+#define WLAN_REMAIN_TIME_I_MSK 0x00ffffff
+#define WLAN_REMAIN_TIME_SFT 24
+#define WLAN_REMAIN_TIME_HI 31
+#define WLAN_REMAIN_TIME_SZ 8
+#define SW_MANUAL_EN_MSK 0x00000001
+#define SW_MANUAL_EN_I_MSK 0xfffffffe
+#define SW_MANUAL_EN_SFT 0
+#define SW_MANUAL_EN_HI 0
+#define SW_MANUAL_EN_SZ 1
+#define SW_WL_TX_MSK 0x00000002
+#define SW_WL_TX_I_MSK 0xfffffffd
+#define SW_WL_TX_SFT 1
+#define SW_WL_TX_HI 1
+#define SW_WL_TX_SZ 1
+#define SW_WL_RX_MSK 0x00000004
+#define SW_WL_RX_I_MSK 0xfffffffb
+#define SW_WL_RX_SFT 2
+#define SW_WL_RX_HI 2
+#define SW_WL_RX_SZ 1
+#define SW_BT_TRX_MSK 0x00000008
+#define SW_BT_TRX_I_MSK 0xfffffff7
+#define SW_BT_TRX_SFT 3
+#define SW_BT_TRX_HI 3
+#define SW_BT_TRX_SZ 1
+#define BT_TXBAR_MANUAL_EN_MSK 0x00000010
+#define BT_TXBAR_MANUAL_EN_I_MSK 0xffffffef
+#define BT_TXBAR_MANUAL_EN_SFT 4
+#define BT_TXBAR_MANUAL_EN_HI 4
+#define BT_TXBAR_MANUAL_EN_SZ 1
+#define BT_TXBAR_SET_MSK 0x00000020
+#define BT_TXBAR_SET_I_MSK 0xffffffdf
+#define BT_TXBAR_SET_SFT 5
+#define BT_TXBAR_SET_HI 5
+#define BT_TXBAR_SET_SZ 1
+#define BT_BUSY_MANUAL_EN_MSK 0x00000100
+#define BT_BUSY_MANUAL_EN_I_MSK 0xfffffeff
+#define BT_BUSY_MANUAL_EN_SFT 8
+#define BT_BUSY_MANUAL_EN_HI 8
+#define BT_BUSY_MANUAL_EN_SZ 1
+#define BT_BUSY_SET_MSK 0x00000200
+#define BT_BUSY_SET_I_MSK 0xfffffdff
+#define BT_BUSY_SET_SFT 9
+#define BT_BUSY_SET_HI 9
+#define BT_BUSY_SET_SZ 1
+#define G0_PKT_CLS_MIB_EN_MSK 0x00000004
+#define G0_PKT_CLS_MIB_EN_I_MSK 0xfffffffb
+#define G0_PKT_CLS_MIB_EN_SFT 2
+#define G0_PKT_CLS_MIB_EN_HI 2
+#define G0_PKT_CLS_MIB_EN_SZ 1
+#define G0_PKT_CLS_ONGOING_MSK 0x00000008
+#define G0_PKT_CLS_ONGOING_I_MSK 0xfffffff7
+#define G0_PKT_CLS_ONGOING_SFT 3
+#define G0_PKT_CLS_ONGOING_HI 3
+#define G0_PKT_CLS_ONGOING_SZ 1
+#define G1_PKT_CLS_MIB_EN_MSK 0x00000010
+#define G1_PKT_CLS_MIB_EN_I_MSK 0xffffffef
+#define G1_PKT_CLS_MIB_EN_SFT 4
+#define G1_PKT_CLS_MIB_EN_HI 4
+#define G1_PKT_CLS_MIB_EN_SZ 1
+#define G1_PKT_CLS_ONGOING_MSK 0x00000020
+#define G1_PKT_CLS_ONGOING_I_MSK 0xffffffdf
+#define G1_PKT_CLS_ONGOING_SFT 5
+#define G1_PKT_CLS_ONGOING_HI 5
+#define G1_PKT_CLS_ONGOING_SZ 1
+#define Q0_PKT_CLS_MIB_EN_MSK 0x00000040
+#define Q0_PKT_CLS_MIB_EN_I_MSK 0xffffffbf
+#define Q0_PKT_CLS_MIB_EN_SFT 6
+#define Q0_PKT_CLS_MIB_EN_HI 6
+#define Q0_PKT_CLS_MIB_EN_SZ 1
+#define Q0_PKT_CLS_ONGOING_MSK 0x00000080
+#define Q0_PKT_CLS_ONGOING_I_MSK 0xffffff7f
+#define Q0_PKT_CLS_ONGOING_SFT 7
+#define Q0_PKT_CLS_ONGOING_HI 7
+#define Q0_PKT_CLS_ONGOING_SZ 1
+#define Q1_PKT_CLS_MIB_EN_MSK 0x00000100
+#define Q1_PKT_CLS_MIB_EN_I_MSK 0xfffffeff
+#define Q1_PKT_CLS_MIB_EN_SFT 8
+#define Q1_PKT_CLS_MIB_EN_HI 8
+#define Q1_PKT_CLS_MIB_EN_SZ 1
+#define Q1_PKT_CLS_ONGOING_MSK 0x00000200
+#define Q1_PKT_CLS_ONGOING_I_MSK 0xfffffdff
+#define Q1_PKT_CLS_ONGOING_SFT 9
+#define Q1_PKT_CLS_ONGOING_HI 9
+#define Q1_PKT_CLS_ONGOING_SZ 1
+#define Q2_PKT_CLS_MIB_EN_MSK 0x00000400
+#define Q2_PKT_CLS_MIB_EN_I_MSK 0xfffffbff
+#define Q2_PKT_CLS_MIB_EN_SFT 10
+#define Q2_PKT_CLS_MIB_EN_HI 10
+#define Q2_PKT_CLS_MIB_EN_SZ 1
+#define Q2_PKT_CLS_ONGOING_MSK 0x00000800
+#define Q2_PKT_CLS_ONGOING_I_MSK 0xfffff7ff
+#define Q2_PKT_CLS_ONGOING_SFT 11
+#define Q2_PKT_CLS_ONGOING_HI 11
+#define Q2_PKT_CLS_ONGOING_SZ 1
+#define Q3_PKT_CLS_MIB_EN_MSK 0x00001000
+#define Q3_PKT_CLS_MIB_EN_I_MSK 0xffffefff
+#define Q3_PKT_CLS_MIB_EN_SFT 12
+#define Q3_PKT_CLS_MIB_EN_HI 12
+#define Q3_PKT_CLS_MIB_EN_SZ 1
+#define Q3_PKT_CLS_ONGOING_MSK 0x00002000
+#define Q3_PKT_CLS_ONGOING_I_MSK 0xffffdfff
+#define Q3_PKT_CLS_ONGOING_SFT 13
+#define Q3_PKT_CLS_ONGOING_HI 13
+#define Q3_PKT_CLS_ONGOING_SZ 1
+#define SCRT_PKT_CLS_MIB_EN_MSK 0x00004000
+#define SCRT_PKT_CLS_MIB_EN_I_MSK 0xffffbfff
+#define SCRT_PKT_CLS_MIB_EN_SFT 14
+#define SCRT_PKT_CLS_MIB_EN_HI 14
+#define SCRT_PKT_CLS_MIB_EN_SZ 1
+#define SCRT_PKT_CLS_ONGOING_MSK 0x00008000
+#define SCRT_PKT_CLS_ONGOING_I_MSK 0xffff7fff
+#define SCRT_PKT_CLS_ONGOING_SFT 15
+#define SCRT_PKT_CLS_ONGOING_HI 15
+#define SCRT_PKT_CLS_ONGOING_SZ 1
+#define MISC_PKT_CLS_MIB_EN_MSK 0x00010000
+#define MISC_PKT_CLS_MIB_EN_I_MSK 0xfffeffff
+#define MISC_PKT_CLS_MIB_EN_SFT 16
+#define MISC_PKT_CLS_MIB_EN_HI 16
+#define MISC_PKT_CLS_MIB_EN_SZ 1
+#define MISC_PKT_CLS_ONGOING_MSK 0x00020000
+#define MISC_PKT_CLS_ONGOING_I_MSK 0xfffdffff
+#define MISC_PKT_CLS_ONGOING_SFT 17
+#define MISC_PKT_CLS_ONGOING_HI 17
+#define MISC_PKT_CLS_ONGOING_SZ 1
+#define MTX_WSID0_SUCC_MSK 0x0000ffff
+#define MTX_WSID0_SUCC_I_MSK 0xffff0000
+#define MTX_WSID0_SUCC_SFT 0
+#define MTX_WSID0_SUCC_HI 15
+#define MTX_WSID0_SUCC_SZ 16
+#define MTX_WSID0_FRM_MSK 0x0000ffff
+#define MTX_WSID0_FRM_I_MSK 0xffff0000
+#define MTX_WSID0_FRM_SFT 0
+#define MTX_WSID0_FRM_HI 15
+#define MTX_WSID0_FRM_SZ 16
+#define MTX_WSID0_RETRY_MSK 0x0000ffff
+#define MTX_WSID0_RETRY_I_MSK 0xffff0000
+#define MTX_WSID0_RETRY_SFT 0
+#define MTX_WSID0_RETRY_HI 15
+#define MTX_WSID0_RETRY_SZ 16
+#define MTX_WSID0_TOTAL_MSK 0x0000ffff
+#define MTX_WSID0_TOTAL_I_MSK 0xffff0000
+#define MTX_WSID0_TOTAL_SFT 0
+#define MTX_WSID0_TOTAL_HI 15
+#define MTX_WSID0_TOTAL_SZ 16
+#define MTX_GRP_MSK 0x000fffff
+#define MTX_GRP_I_MSK 0xfff00000
+#define MTX_GRP_SFT 0
+#define MTX_GRP_HI 19
+#define MTX_GRP_SZ 20
+#define MTX_FAIL_MSK 0x0000ffff
+#define MTX_FAIL_I_MSK 0xffff0000
+#define MTX_FAIL_SFT 0
+#define MTX_FAIL_HI 15
+#define MTX_FAIL_SZ 16
+#define MTX_RETRY_MSK 0x000fffff
+#define MTX_RETRY_I_MSK 0xfff00000
+#define MTX_RETRY_SFT 0
+#define MTX_RETRY_HI 19
+#define MTX_RETRY_SZ 20
+#define MTX_MULTI_RETRY_MSK 0x000fffff
+#define MTX_MULTI_RETRY_I_MSK 0xfff00000
+#define MTX_MULTI_RETRY_SFT 0
+#define MTX_MULTI_RETRY_HI 19
+#define MTX_MULTI_RETRY_SZ 20
+#define MTX_RTS_SUCC_MSK 0x0000ffff
+#define MTX_RTS_SUCC_I_MSK 0xffff0000
+#define MTX_RTS_SUCC_SFT 0
+#define MTX_RTS_SUCC_HI 15
+#define MTX_RTS_SUCC_SZ 16
+#define MTX_RTS_FAIL_MSK 0x0000ffff
+#define MTX_RTS_FAIL_I_MSK 0xffff0000
+#define MTX_RTS_FAIL_SFT 0
+#define MTX_RTS_FAIL_HI 15
+#define MTX_RTS_FAIL_SZ 16
+#define MTX_ACK_FAIL_MSK 0x0000ffff
+#define MTX_ACK_FAIL_I_MSK 0xffff0000
+#define MTX_ACK_FAIL_SFT 0
+#define MTX_ACK_FAIL_HI 15
+#define MTX_ACK_FAIL_SZ 16
+#define MTX_FRM_MSK 0x000fffff
+#define MTX_FRM_I_MSK 0xfff00000
+#define MTX_FRM_SFT 0
+#define MTX_FRM_HI 19
+#define MTX_FRM_SZ 20
+#define MTX_ACK_TX_MSK 0x0000ffff
+#define MTX_ACK_TX_I_MSK 0xffff0000
+#define MTX_ACK_TX_SFT 0
+#define MTX_ACK_TX_HI 15
+#define MTX_ACK_TX_SZ 16
+#define MTX_CTS_TX_MSK 0x0000ffff
+#define MTX_CTS_TX_I_MSK 0xffff0000
+#define MTX_CTS_TX_SFT 0
+#define MTX_CTS_TX_HI 15
+#define MTX_CTS_TX_SZ 16
+#define MRX_DUP_MSK 0x0000ffff
+#define MRX_DUP_I_MSK 0xffff0000
+#define MRX_DUP_SFT 0
+#define MRX_DUP_HI 15
+#define MRX_DUP_SZ 16
+#define MRX_FRG_MSK 0x000fffff
+#define MRX_FRG_I_MSK 0xfff00000
+#define MRX_FRG_SFT 0
+#define MRX_FRG_HI 19
+#define MRX_FRG_SZ 20
+#define MRX_GRP_MSK 0x000fffff
+#define MRX_GRP_I_MSK 0xfff00000
+#define MRX_GRP_SFT 0
+#define MRX_GRP_HI 19
+#define MRX_GRP_SZ 20
+#define MRX_FCS_ERR_MSK 0x0000ffff
+#define MRX_FCS_ERR_I_MSK 0xffff0000
+#define MRX_FCS_ERR_SFT 0
+#define MRX_FCS_ERR_HI 15
+#define MRX_FCS_ERR_SZ 16
+#define MRX_FCS_SUC_MSK 0x0000ffff
+#define MRX_FCS_SUC_I_MSK 0xffff0000
+#define MRX_FCS_SUC_SFT 0
+#define MRX_FCS_SUC_HI 15
+#define MRX_FCS_SUC_SZ 16
+#define MRX_MISS_MSK 0x0000ffff
+#define MRX_MISS_I_MSK 0xffff0000
+#define MRX_MISS_SFT 0
+#define MRX_MISS_HI 15
+#define MRX_MISS_SZ 16
+#define MRX_ALC_FAIL_MSK 0x0000ffff
+#define MRX_ALC_FAIL_I_MSK 0xffff0000
+#define MRX_ALC_FAIL_SFT 0
+#define MRX_ALC_FAIL_HI 15
+#define MRX_ALC_FAIL_SZ 16
+#define MRX_DAT_NTF_MSK 0x0000ffff
+#define MRX_DAT_NTF_I_MSK 0xffff0000
+#define MRX_DAT_NTF_SFT 0
+#define MRX_DAT_NTF_HI 15
+#define MRX_DAT_NTF_SZ 16
+#define MRX_RTS_NTF_MSK 0x0000ffff
+#define MRX_RTS_NTF_I_MSK 0xffff0000
+#define MRX_RTS_NTF_SFT 0
+#define MRX_RTS_NTF_HI 15
+#define MRX_RTS_NTF_SZ 16
+#define MRX_CTS_NTF_MSK 0x0000ffff
+#define MRX_CTS_NTF_I_MSK 0xffff0000
+#define MRX_CTS_NTF_SFT 0
+#define MRX_CTS_NTF_HI 15
+#define MRX_CTS_NTF_SZ 16
+#define MRX_ACK_NTF_MSK 0x0000ffff
+#define MRX_ACK_NTF_I_MSK 0xffff0000
+#define MRX_ACK_NTF_SFT 0
+#define MRX_ACK_NTF_HI 15
+#define MRX_ACK_NTF_SZ 16
+#define MRX_BA_NTF_MSK 0x0000ffff
+#define MRX_BA_NTF_I_MSK 0xffff0000
+#define MRX_BA_NTF_SFT 0
+#define MRX_BA_NTF_HI 15
+#define MRX_BA_NTF_SZ 16
+#define MRX_DATA_NTF_MSK 0x0000ffff
+#define MRX_DATA_NTF_I_MSK 0xffff0000
+#define MRX_DATA_NTF_SFT 0
+#define MRX_DATA_NTF_HI 15
+#define MRX_DATA_NTF_SZ 16
+#define MRX_MNG_NTF_MSK 0x0000ffff
+#define MRX_MNG_NTF_I_MSK 0xffff0000
+#define MRX_MNG_NTF_SFT 0
+#define MRX_MNG_NTF_HI 15
+#define MRX_MNG_NTF_SZ 16
+#define MRX_DAT_CRC_NTF_MSK 0x0000ffff
+#define MRX_DAT_CRC_NTF_I_MSK 0xffff0000
+#define MRX_DAT_CRC_NTF_SFT 0
+#define MRX_DAT_CRC_NTF_HI 15
+#define MRX_DAT_CRC_NTF_SZ 16
+#define MRX_BAR_NTF_MSK 0x0000ffff
+#define MRX_BAR_NTF_I_MSK 0xffff0000
+#define MRX_BAR_NTF_SFT 0
+#define MRX_BAR_NTF_HI 15
+#define MRX_BAR_NTF_SZ 16
+#define MRX_MB_MISS_MSK 0x0000ffff
+#define MRX_MB_MISS_I_MSK 0xffff0000
+#define MRX_MB_MISS_SFT 0
+#define MRX_MB_MISS_HI 15
+#define MRX_MB_MISS_SZ 16
+#define MRX_NIDLE_MISS_MSK 0x0000ffff
+#define MRX_NIDLE_MISS_I_MSK 0xffff0000
+#define MRX_NIDLE_MISS_SFT 0
+#define MRX_NIDLE_MISS_HI 15
+#define MRX_NIDLE_MISS_SZ 16
+#define MRX_CSR_NTF_MSK 0x0000ffff
+#define MRX_CSR_NTF_I_MSK 0xffff0000
+#define MRX_CSR_NTF_SFT 0
+#define MRX_CSR_NTF_HI 15
+#define MRX_CSR_NTF_SZ 16
+#define DBG_Q0_SUCC_MSK 0x0000ffff
+#define DBG_Q0_SUCC_I_MSK 0xffff0000
+#define DBG_Q0_SUCC_SFT 0
+#define DBG_Q0_SUCC_HI 15
+#define DBG_Q0_SUCC_SZ 16
+#define DBG_Q0_FAIL_MSK 0x0000ffff
+#define DBG_Q0_FAIL_I_MSK 0xffff0000
+#define DBG_Q0_FAIL_SFT 0
+#define DBG_Q0_FAIL_HI 15
+#define DBG_Q0_FAIL_SZ 16
+#define DBG_Q0_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q0_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q0_ACK_SUCC_SFT 0
+#define DBG_Q0_ACK_SUCC_HI 15
+#define DBG_Q0_ACK_SUCC_SZ 16
+#define DBG_Q0_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q0_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q0_ACK_FAIL_SFT 0
+#define DBG_Q0_ACK_FAIL_HI 15
+#define DBG_Q0_ACK_FAIL_SZ 16
+#define DBG_Q1_SUCC_MSK 0x0000ffff
+#define DBG_Q1_SUCC_I_MSK 0xffff0000
+#define DBG_Q1_SUCC_SFT 0
+#define DBG_Q1_SUCC_HI 15
+#define DBG_Q1_SUCC_SZ 16
+#define DBG_Q1_FAIL_MSK 0x0000ffff
+#define DBG_Q1_FAIL_I_MSK 0xffff0000
+#define DBG_Q1_FAIL_SFT 0
+#define DBG_Q1_FAIL_HI 15
+#define DBG_Q1_FAIL_SZ 16
+#define DBG_Q1_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q1_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q1_ACK_SUCC_SFT 0
+#define DBG_Q1_ACK_SUCC_HI 15
+#define DBG_Q1_ACK_SUCC_SZ 16
+#define DBG_Q1_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q1_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q1_ACK_FAIL_SFT 0
+#define DBG_Q1_ACK_FAIL_HI 15
+#define DBG_Q1_ACK_FAIL_SZ 16
+#define DBG_Q2_SUCC_MSK 0x0000ffff
+#define DBG_Q2_SUCC_I_MSK 0xffff0000
+#define DBG_Q2_SUCC_SFT 0
+#define DBG_Q2_SUCC_HI 15
+#define DBG_Q2_SUCC_SZ 16
+#define DBG_Q2_FAIL_MSK 0x0000ffff
+#define DBG_Q2_FAIL_I_MSK 0xffff0000
+#define DBG_Q2_FAIL_SFT 0
+#define DBG_Q2_FAIL_HI 15
+#define DBG_Q2_FAIL_SZ 16
+#define DBG_Q2_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q2_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q2_ACK_SUCC_SFT 0
+#define DBG_Q2_ACK_SUCC_HI 15
+#define DBG_Q2_ACK_SUCC_SZ 16
+#define DBG_Q2_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q2_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q2_ACK_FAIL_SFT 0
+#define DBG_Q2_ACK_FAIL_HI 15
+#define DBG_Q2_ACK_FAIL_SZ 16
+#define DBG_Q3_SUCC_MSK 0x0000ffff
+#define DBG_Q3_SUCC_I_MSK 0xffff0000
+#define DBG_Q3_SUCC_SFT 0
+#define DBG_Q3_SUCC_HI 15
+#define DBG_Q3_SUCC_SZ 16
+#define DBG_Q3_FAIL_MSK 0x0000ffff
+#define DBG_Q3_FAIL_I_MSK 0xffff0000
+#define DBG_Q3_FAIL_SFT 0
+#define DBG_Q3_FAIL_HI 15
+#define DBG_Q3_FAIL_SZ 16
+#define DBG_Q3_ACK_SUCC_MSK 0x0000ffff
+#define DBG_Q3_ACK_SUCC_I_MSK 0xffff0000
+#define DBG_Q3_ACK_SUCC_SFT 0
+#define DBG_Q3_ACK_SUCC_HI 15
+#define DBG_Q3_ACK_SUCC_SZ 16
+#define DBG_Q3_ACK_FAIL_MSK 0x0000ffff
+#define DBG_Q3_ACK_FAIL_I_MSK 0xffff0000
+#define DBG_Q3_ACK_FAIL_SFT 0
+#define DBG_Q3_ACK_FAIL_HI 15
+#define DBG_Q3_ACK_FAIL_SZ 16
+#define SCRT_TKIP_CERR_MSK 0x000fffff
+#define SCRT_TKIP_CERR_I_MSK 0xfff00000
+#define SCRT_TKIP_CERR_SFT 0
+#define SCRT_TKIP_CERR_HI 19
+#define SCRT_TKIP_CERR_SZ 20
+#define SCRT_TKIP_MIC_ERR_MSK 0x000fffff
+#define SCRT_TKIP_MIC_ERR_I_MSK 0xfff00000
+#define SCRT_TKIP_MIC_ERR_SFT 0
+#define SCRT_TKIP_MIC_ERR_HI 19
+#define SCRT_TKIP_MIC_ERR_SZ 20
+#define SCRT_TKIP_RPLY_MSK 0x000fffff
+#define SCRT_TKIP_RPLY_I_MSK 0xfff00000
+#define SCRT_TKIP_RPLY_SFT 0
+#define SCRT_TKIP_RPLY_HI 19
+#define SCRT_TKIP_RPLY_SZ 20
+#define SCRT_CCMP_RPLY_MSK 0x000fffff
+#define SCRT_CCMP_RPLY_I_MSK 0xfff00000
+#define SCRT_CCMP_RPLY_SFT 0
+#define SCRT_CCMP_RPLY_HI 19
+#define SCRT_CCMP_RPLY_SZ 20
+#define SCRT_CCMP_CERR_MSK 0x000fffff
+#define SCRT_CCMP_CERR_I_MSK 0xfff00000
+#define SCRT_CCMP_CERR_SFT 0
+#define SCRT_CCMP_CERR_HI 19
+#define SCRT_CCMP_CERR_SZ 20
+#define DBG_LEN_CRC_FAIL_MSK 0x0000ffff
+#define DBG_LEN_CRC_FAIL_I_MSK 0xffff0000
+#define DBG_LEN_CRC_FAIL_SFT 0
+#define DBG_LEN_CRC_FAIL_HI 15
+#define DBG_LEN_CRC_FAIL_SZ 16
+#define DBG_LEN_ALC_FAIL_MSK 0x0000ffff
+#define DBG_LEN_ALC_FAIL_I_MSK 0xffff0000
+#define DBG_LEN_ALC_FAIL_SFT 0
+#define DBG_LEN_ALC_FAIL_HI 15
+#define DBG_LEN_ALC_FAIL_SZ 16
+#define DBG_AMPDU_PASS_MSK 0x0000ffff
+#define DBG_AMPDU_PASS_I_MSK 0xffff0000
+#define DBG_AMPDU_PASS_SFT 0
+#define DBG_AMPDU_PASS_HI 15
+#define DBG_AMPDU_PASS_SZ 16
+#define DBG_AMPDU_FAIL_MSK 0x0000ffff
+#define DBG_AMPDU_FAIL_I_MSK 0xffff0000
+#define DBG_AMPDU_FAIL_SFT 0
+#define DBG_AMPDU_FAIL_HI 15
+#define DBG_AMPDU_FAIL_SZ 16
+#define RXID_ALC_CNT_FAIL_MSK 0x0000ffff
+#define RXID_ALC_CNT_FAIL_I_MSK 0xffff0000
+#define RXID_ALC_CNT_FAIL_SFT 0
+#define RXID_ALC_CNT_FAIL_HI 15
+#define RXID_ALC_CNT_FAIL_SZ 16
+#define RXID_ALC_LEN_FAIL_MSK 0x0000ffff
+#define RXID_ALC_LEN_FAIL_I_MSK 0xffff0000
+#define RXID_ALC_LEN_FAIL_SFT 0
+#define RXID_ALC_LEN_FAIL_HI 15
+#define RXID_ALC_LEN_FAIL_SZ 16
+#define CBR_RG_EN_MANUAL_MSK 0x00000001
+#define CBR_RG_EN_MANUAL_I_MSK 0xfffffffe
+#define CBR_RG_EN_MANUAL_SFT 0
+#define CBR_RG_EN_MANUAL_HI 0
+#define CBR_RG_EN_MANUAL_SZ 1
+#define CBR_RG_TX_EN_MSK 0x00000002
+#define CBR_RG_TX_EN_I_MSK 0xfffffffd
+#define CBR_RG_TX_EN_SFT 1
+#define CBR_RG_TX_EN_HI 1
+#define CBR_RG_TX_EN_SZ 1
+#define CBR_RG_TX_PA_EN_MSK 0x00000004
+#define CBR_RG_TX_PA_EN_I_MSK 0xfffffffb
+#define CBR_RG_TX_PA_EN_SFT 2
+#define CBR_RG_TX_PA_EN_HI 2
+#define CBR_RG_TX_PA_EN_SZ 1
+#define CBR_RG_TX_DAC_EN_MSK 0x00000008
+#define CBR_RG_TX_DAC_EN_I_MSK 0xfffffff7
+#define CBR_RG_TX_DAC_EN_SFT 3
+#define CBR_RG_TX_DAC_EN_HI 3
+#define CBR_RG_TX_DAC_EN_SZ 1
+#define CBR_RG_RX_AGC_MSK 0x00000010
+#define CBR_RG_RX_AGC_I_MSK 0xffffffef
+#define CBR_RG_RX_AGC_SFT 4
+#define CBR_RG_RX_AGC_HI 4
+#define CBR_RG_RX_AGC_SZ 1
+#define CBR_RG_RX_GAIN_MANUAL_MSK 0x00000020
+#define CBR_RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
+#define CBR_RG_RX_GAIN_MANUAL_SFT 5
+#define CBR_RG_RX_GAIN_MANUAL_HI 5
+#define CBR_RG_RX_GAIN_MANUAL_SZ 1
+#define CBR_RG_RFG_MSK 0x000000c0
+#define CBR_RG_RFG_I_MSK 0xffffff3f
+#define CBR_RG_RFG_SFT 6
+#define CBR_RG_RFG_HI 7
+#define CBR_RG_RFG_SZ 2
+#define CBR_RG_PGAG_MSK 0x00000f00
+#define CBR_RG_PGAG_I_MSK 0xfffff0ff
+#define CBR_RG_PGAG_SFT 8
+#define CBR_RG_PGAG_HI 11
+#define CBR_RG_PGAG_SZ 4
+#define CBR_RG_MODE_MSK 0x00003000
+#define CBR_RG_MODE_I_MSK 0xffffcfff
+#define CBR_RG_MODE_SFT 12
+#define CBR_RG_MODE_HI 13
+#define CBR_RG_MODE_SZ 2
+#define CBR_RG_EN_TX_TRSW_MSK 0x00004000
+#define CBR_RG_EN_TX_TRSW_I_MSK 0xffffbfff
+#define CBR_RG_EN_TX_TRSW_SFT 14
+#define CBR_RG_EN_TX_TRSW_HI 14
+#define CBR_RG_EN_TX_TRSW_SZ 1
+#define CBR_RG_EN_SX_MSK 0x00008000
+#define CBR_RG_EN_SX_I_MSK 0xffff7fff
+#define CBR_RG_EN_SX_SFT 15
+#define CBR_RG_EN_SX_HI 15
+#define CBR_RG_EN_SX_SZ 1
+#define CBR_RG_EN_RX_LNA_MSK 0x00010000
+#define CBR_RG_EN_RX_LNA_I_MSK 0xfffeffff
+#define CBR_RG_EN_RX_LNA_SFT 16
+#define CBR_RG_EN_RX_LNA_HI 16
+#define CBR_RG_EN_RX_LNA_SZ 1
+#define CBR_RG_EN_RX_MIXER_MSK 0x00020000
+#define CBR_RG_EN_RX_MIXER_I_MSK 0xfffdffff
+#define CBR_RG_EN_RX_MIXER_SFT 17
+#define CBR_RG_EN_RX_MIXER_HI 17
+#define CBR_RG_EN_RX_MIXER_SZ 1
+#define CBR_RG_EN_RX_DIV2_MSK 0x00040000
+#define CBR_RG_EN_RX_DIV2_I_MSK 0xfffbffff
+#define CBR_RG_EN_RX_DIV2_SFT 18
+#define CBR_RG_EN_RX_DIV2_HI 18
+#define CBR_RG_EN_RX_DIV2_SZ 1
+#define CBR_RG_EN_RX_LOBUF_MSK 0x00080000
+#define CBR_RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
+#define CBR_RG_EN_RX_LOBUF_SFT 19
+#define CBR_RG_EN_RX_LOBUF_HI 19
+#define CBR_RG_EN_RX_LOBUF_SZ 1
+#define CBR_RG_EN_RX_TZ_MSK 0x00100000
+#define CBR_RG_EN_RX_TZ_I_MSK 0xffefffff
+#define CBR_RG_EN_RX_TZ_SFT 20
+#define CBR_RG_EN_RX_TZ_HI 20
+#define CBR_RG_EN_RX_TZ_SZ 1
+#define CBR_RG_EN_RX_FILTER_MSK 0x00200000
+#define CBR_RG_EN_RX_FILTER_I_MSK 0xffdfffff
+#define CBR_RG_EN_RX_FILTER_SFT 21
+#define CBR_RG_EN_RX_FILTER_HI 21
+#define CBR_RG_EN_RX_FILTER_SZ 1
+#define CBR_RG_EN_RX_HPF_MSK 0x00400000
+#define CBR_RG_EN_RX_HPF_I_MSK 0xffbfffff
+#define CBR_RG_EN_RX_HPF_SFT 22
+#define CBR_RG_EN_RX_HPF_HI 22
+#define CBR_RG_EN_RX_HPF_SZ 1
+#define CBR_RG_EN_RX_RSSI_MSK 0x00800000
+#define CBR_RG_EN_RX_RSSI_I_MSK 0xff7fffff
+#define CBR_RG_EN_RX_RSSI_SFT 23
+#define CBR_RG_EN_RX_RSSI_HI 23
+#define CBR_RG_EN_RX_RSSI_SZ 1
+#define CBR_RG_EN_ADC_MSK 0x01000000
+#define CBR_RG_EN_ADC_I_MSK 0xfeffffff
+#define CBR_RG_EN_ADC_SFT 24
+#define CBR_RG_EN_ADC_HI 24
+#define CBR_RG_EN_ADC_SZ 1
+#define CBR_RG_EN_TX_MOD_MSK 0x02000000
+#define CBR_RG_EN_TX_MOD_I_MSK 0xfdffffff
+#define CBR_RG_EN_TX_MOD_SFT 25
+#define CBR_RG_EN_TX_MOD_HI 25
+#define CBR_RG_EN_TX_MOD_SZ 1
+#define CBR_RG_EN_TX_DIV2_MSK 0x04000000
+#define CBR_RG_EN_TX_DIV2_I_MSK 0xfbffffff
+#define CBR_RG_EN_TX_DIV2_SFT 26
+#define CBR_RG_EN_TX_DIV2_HI 26
+#define CBR_RG_EN_TX_DIV2_SZ 1
+#define CBR_RG_EN_TX_DIV2_BUF_MSK 0x08000000
+#define CBR_RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
+#define CBR_RG_EN_TX_DIV2_BUF_SFT 27
+#define CBR_RG_EN_TX_DIV2_BUF_HI 27
+#define CBR_RG_EN_TX_DIV2_BUF_SZ 1
+#define CBR_RG_EN_TX_LOBF_MSK 0x10000000
+#define CBR_RG_EN_TX_LOBF_I_MSK 0xefffffff
+#define CBR_RG_EN_TX_LOBF_SFT 28
+#define CBR_RG_EN_TX_LOBF_HI 28
+#define CBR_RG_EN_TX_LOBF_SZ 1
+#define CBR_RG_EN_RX_LOBF_MSK 0x20000000
+#define CBR_RG_EN_RX_LOBF_I_MSK 0xdfffffff
+#define CBR_RG_EN_RX_LOBF_SFT 29
+#define CBR_RG_EN_RX_LOBF_HI 29
+#define CBR_RG_EN_RX_LOBF_SZ 1
+#define CBR_RG_SEL_DPLL_CLK_MSK 0x40000000
+#define CBR_RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
+#define CBR_RG_SEL_DPLL_CLK_SFT 30
+#define CBR_RG_SEL_DPLL_CLK_HI 30
+#define CBR_RG_SEL_DPLL_CLK_SZ 1
+#define CBR_RG_EN_TX_DPD_MSK 0x00000001
+#define CBR_RG_EN_TX_DPD_I_MSK 0xfffffffe
+#define CBR_RG_EN_TX_DPD_SFT 0
+#define CBR_RG_EN_TX_DPD_HI 0
+#define CBR_RG_EN_TX_DPD_SZ 1
+#define CBR_RG_EN_TX_TSSI_MSK 0x00000002
+#define CBR_RG_EN_TX_TSSI_I_MSK 0xfffffffd
+#define CBR_RG_EN_TX_TSSI_SFT 1
+#define CBR_RG_EN_TX_TSSI_HI 1
+#define CBR_RG_EN_TX_TSSI_SZ 1
+#define CBR_RG_EN_RX_IQCAL_MSK 0x00000004
+#define CBR_RG_EN_RX_IQCAL_I_MSK 0xfffffffb
+#define CBR_RG_EN_RX_IQCAL_SFT 2
+#define CBR_RG_EN_RX_IQCAL_HI 2
+#define CBR_RG_EN_RX_IQCAL_SZ 1
+#define CBR_RG_EN_TX_DAC_CAL_MSK 0x00000008
+#define CBR_RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
+#define CBR_RG_EN_TX_DAC_CAL_SFT 3
+#define CBR_RG_EN_TX_DAC_CAL_HI 3
+#define CBR_RG_EN_TX_DAC_CAL_SZ 1
+#define CBR_RG_EN_TX_SELF_MIXER_MSK 0x00000010
+#define CBR_RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
+#define CBR_RG_EN_TX_SELF_MIXER_SFT 4
+#define CBR_RG_EN_TX_SELF_MIXER_HI 4
+#define CBR_RG_EN_TX_SELF_MIXER_SZ 1
+#define CBR_RG_EN_TX_DAC_OUT_MSK 0x00000020
+#define CBR_RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
+#define CBR_RG_EN_TX_DAC_OUT_SFT 5
+#define CBR_RG_EN_TX_DAC_OUT_HI 5
+#define CBR_RG_EN_TX_DAC_OUT_SZ 1
+#define CBR_RG_EN_LDO_RX_FE_MSK 0x00000040
+#define CBR_RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
+#define CBR_RG_EN_LDO_RX_FE_SFT 6
+#define CBR_RG_EN_LDO_RX_FE_HI 6
+#define CBR_RG_EN_LDO_RX_FE_SZ 1
+#define CBR_RG_EN_LDO_ABB_MSK 0x00000080
+#define CBR_RG_EN_LDO_ABB_I_MSK 0xffffff7f
+#define CBR_RG_EN_LDO_ABB_SFT 7
+#define CBR_RG_EN_LDO_ABB_HI 7
+#define CBR_RG_EN_LDO_ABB_SZ 1
+#define CBR_RG_EN_LDO_AFE_MSK 0x00000100
+#define CBR_RG_EN_LDO_AFE_I_MSK 0xfffffeff
+#define CBR_RG_EN_LDO_AFE_SFT 8
+#define CBR_RG_EN_LDO_AFE_HI 8
+#define CBR_RG_EN_LDO_AFE_SZ 1
+#define CBR_RG_EN_SX_CHPLDO_MSK 0x00000200
+#define CBR_RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
+#define CBR_RG_EN_SX_CHPLDO_SFT 9
+#define CBR_RG_EN_SX_CHPLDO_HI 9
+#define CBR_RG_EN_SX_CHPLDO_SZ 1
+#define CBR_RG_EN_SX_LOBFLDO_MSK 0x00000400
+#define CBR_RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
+#define CBR_RG_EN_SX_LOBFLDO_SFT 10
+#define CBR_RG_EN_SX_LOBFLDO_HI 10
+#define CBR_RG_EN_SX_LOBFLDO_SZ 1
+#define CBR_RG_EN_IREF_RX_MSK 0x00000800
+#define CBR_RG_EN_IREF_RX_I_MSK 0xfffff7ff
+#define CBR_RG_EN_IREF_RX_SFT 11
+#define CBR_RG_EN_IREF_RX_HI 11
+#define CBR_RG_EN_IREF_RX_SZ 1
+#define CBR_RG_DCDC_MODE_MSK 0x00001000
+#define CBR_RG_DCDC_MODE_I_MSK 0xffffefff
+#define CBR_RG_DCDC_MODE_SFT 12
+#define CBR_RG_DCDC_MODE_HI 12
+#define CBR_RG_DCDC_MODE_SZ 1
+#define CBR_RG_LDO_LEVEL_RX_FE_MSK 0x00000007
+#define CBR_RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
+#define CBR_RG_LDO_LEVEL_RX_FE_SFT 0
+#define CBR_RG_LDO_LEVEL_RX_FE_HI 2
+#define CBR_RG_LDO_LEVEL_RX_FE_SZ 3
+#define CBR_RG_LDO_LEVEL_ABB_MSK 0x00000038
+#define CBR_RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
+#define CBR_RG_LDO_LEVEL_ABB_SFT 3
+#define CBR_RG_LDO_LEVEL_ABB_HI 5
+#define CBR_RG_LDO_LEVEL_ABB_SZ 3
+#define CBR_RG_LDO_LEVEL_AFE_MSK 0x000001c0
+#define CBR_RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
+#define CBR_RG_LDO_LEVEL_AFE_SFT 6
+#define CBR_RG_LDO_LEVEL_AFE_HI 8
+#define CBR_RG_LDO_LEVEL_AFE_SZ 3
+#define CBR_RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
+#define CBR_RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
+#define CBR_RG_SX_LDO_CHP_LEVEL_SFT 9
+#define CBR_RG_SX_LDO_CHP_LEVEL_HI 11
+#define CBR_RG_SX_LDO_CHP_LEVEL_SZ 3
+#define CBR_RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
+#define CBR_RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
+#define CBR_RG_SX_LDO_LOBF_LEVEL_SFT 12
+#define CBR_RG_SX_LDO_LOBF_LEVEL_HI 14
+#define CBR_RG_SX_LDO_LOBF_LEVEL_SZ 3
+#define CBR_RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
+#define CBR_RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
+#define CBR_RG_SX_LDO_XOSC_LEVEL_SFT 15
+#define CBR_RG_SX_LDO_XOSC_LEVEL_HI 17
+#define CBR_RG_SX_LDO_XOSC_LEVEL_SZ 3
+#define CBR_RG_DP_LDO_LEVEL_MSK 0x001c0000
+#define CBR_RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
+#define CBR_RG_DP_LDO_LEVEL_SFT 18
+#define CBR_RG_DP_LDO_LEVEL_HI 20
+#define CBR_RG_DP_LDO_LEVEL_SZ 3
+#define CBR_RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
+#define CBR_RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
+#define CBR_RG_SX_LDO_VCO_LEVEL_SFT 21
+#define CBR_RG_SX_LDO_VCO_LEVEL_HI 23
+#define CBR_RG_SX_LDO_VCO_LEVEL_SZ 3
+#define CBR_RG_TX_LDO_TX_LEVEL_MSK 0x07000000
+#define CBR_RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
+#define CBR_RG_TX_LDO_TX_LEVEL_SFT 24
+#define CBR_RG_TX_LDO_TX_LEVEL_HI 26
+#define CBR_RG_TX_LDO_TX_LEVEL_SZ 3
+#define CBR_RG_BUCK_LEVEL_MSK 0x38000000
+#define CBR_RG_BUCK_LEVEL_I_MSK 0xc7ffffff
+#define CBR_RG_BUCK_LEVEL_SFT 27
+#define CBR_RG_BUCK_LEVEL_HI 29
+#define CBR_RG_BUCK_LEVEL_SZ 3
+#define CBR_RG_EN_RX_PADSW_MSK 0x00000001
+#define CBR_RG_EN_RX_PADSW_I_MSK 0xfffffffe
+#define CBR_RG_EN_RX_PADSW_SFT 0
+#define CBR_RG_EN_RX_PADSW_HI 0
+#define CBR_RG_EN_RX_PADSW_SZ 1
+#define CBR_RG_EN_RX_TESTNODE_MSK 0x00000002
+#define CBR_RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
+#define CBR_RG_EN_RX_TESTNODE_SFT 1
+#define CBR_RG_EN_RX_TESTNODE_HI 1
+#define CBR_RG_EN_RX_TESTNODE_SZ 1
+#define CBR_RG_RX_ABBCFIX_MSK 0x00000004
+#define CBR_RG_RX_ABBCFIX_I_MSK 0xfffffffb
+#define CBR_RG_RX_ABBCFIX_SFT 2
+#define CBR_RG_RX_ABBCFIX_HI 2
+#define CBR_RG_RX_ABBCFIX_SZ 1
+#define CBR_RG_RX_ABBCTUNE_MSK 0x000001f8
+#define CBR_RG_RX_ABBCTUNE_I_MSK 0xfffffe07
+#define CBR_RG_RX_ABBCTUNE_SFT 3
+#define CBR_RG_RX_ABBCTUNE_HI 8
+#define CBR_RG_RX_ABBCTUNE_SZ 6
+#define CBR_RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
+#define CBR_RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
+#define CBR_RG_RX_ABBOUT_TRI_STATE_SFT 9
+#define CBR_RG_RX_ABBOUT_TRI_STATE_HI 9
+#define CBR_RG_RX_ABBOUT_TRI_STATE_SZ 1
+#define CBR_RG_RX_ABB_N_MODE_MSK 0x00000400
+#define CBR_RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
+#define CBR_RG_RX_ABB_N_MODE_SFT 10
+#define CBR_RG_RX_ABB_N_MODE_HI 10
+#define CBR_RG_RX_ABB_N_MODE_SZ 1
+#define CBR_RG_RX_EN_LOOPA_MSK 0x00000800
+#define CBR_RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
+#define CBR_RG_RX_EN_LOOPA_SFT 11
+#define CBR_RG_RX_EN_LOOPA_HI 11
+#define CBR_RG_RX_EN_LOOPA_SZ 1
+#define CBR_RG_RX_FILTERI1ST_MSK 0x00003000
+#define CBR_RG_RX_FILTERI1ST_I_MSK 0xffffcfff
+#define CBR_RG_RX_FILTERI1ST_SFT 12
+#define CBR_RG_RX_FILTERI1ST_HI 13
+#define CBR_RG_RX_FILTERI1ST_SZ 2
+#define CBR_RG_RX_FILTERI2ND_MSK 0x0000c000
+#define CBR_RG_RX_FILTERI2ND_I_MSK 0xffff3fff
+#define CBR_RG_RX_FILTERI2ND_SFT 14
+#define CBR_RG_RX_FILTERI2ND_HI 15
+#define CBR_RG_RX_FILTERI2ND_SZ 2
+#define CBR_RG_RX_FILTERI3RD_MSK 0x00030000
+#define CBR_RG_RX_FILTERI3RD_I_MSK 0xfffcffff
+#define CBR_RG_RX_FILTERI3RD_SFT 16
+#define CBR_RG_RX_FILTERI3RD_HI 17
+#define CBR_RG_RX_FILTERI3RD_SZ 2
+#define CBR_RG_RX_FILTERI_COURSE_MSK 0x000c0000
+#define CBR_RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
+#define CBR_RG_RX_FILTERI_COURSE_SFT 18
+#define CBR_RG_RX_FILTERI_COURSE_HI 19
+#define CBR_RG_RX_FILTERI_COURSE_SZ 2
+#define CBR_RG_RX_FILTERVCM_MSK 0x00300000
+#define CBR_RG_RX_FILTERVCM_I_MSK 0xffcfffff
+#define CBR_RG_RX_FILTERVCM_SFT 20
+#define CBR_RG_RX_FILTERVCM_HI 21
+#define CBR_RG_RX_FILTERVCM_SZ 2
+#define CBR_RG_RX_HPF3M_MSK 0x00400000
+#define CBR_RG_RX_HPF3M_I_MSK 0xffbfffff
+#define CBR_RG_RX_HPF3M_SFT 22
+#define CBR_RG_RX_HPF3M_HI 22
+#define CBR_RG_RX_HPF3M_SZ 1
+#define CBR_RG_RX_HPF300K_MSK 0x00800000
+#define CBR_RG_RX_HPF300K_I_MSK 0xff7fffff
+#define CBR_RG_RX_HPF300K_SFT 23
+#define CBR_RG_RX_HPF300K_HI 23
+#define CBR_RG_RX_HPF300K_SZ 1
+#define CBR_RG_RX_HPFI_MSK 0x03000000
+#define CBR_RG_RX_HPFI_I_MSK 0xfcffffff
+#define CBR_RG_RX_HPFI_SFT 24
+#define CBR_RG_RX_HPFI_HI 25
+#define CBR_RG_RX_HPFI_SZ 2
+#define CBR_RG_RX_HPF_FINALCORNER_MSK 0x0c000000
+#define CBR_RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
+#define CBR_RG_RX_HPF_FINALCORNER_SFT 26
+#define CBR_RG_RX_HPF_FINALCORNER_HI 27
+#define CBR_RG_RX_HPF_FINALCORNER_SZ 2
+#define CBR_RG_RX_HPF_SETTLE1_C_MSK 0x30000000
+#define CBR_RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
+#define CBR_RG_RX_HPF_SETTLE1_C_SFT 28
+#define CBR_RG_RX_HPF_SETTLE1_C_HI 29
+#define CBR_RG_RX_HPF_SETTLE1_C_SZ 2
+#define CBR_RG_RX_HPF_SETTLE1_R_MSK 0x00000003
+#define CBR_RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
+#define CBR_RG_RX_HPF_SETTLE1_R_SFT 0
+#define CBR_RG_RX_HPF_SETTLE1_R_HI 1
+#define CBR_RG_RX_HPF_SETTLE1_R_SZ 2
+#define CBR_RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
+#define CBR_RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
+#define CBR_RG_RX_HPF_SETTLE2_C_SFT 2
+#define CBR_RG_RX_HPF_SETTLE2_C_HI 3
+#define CBR_RG_RX_HPF_SETTLE2_C_SZ 2
+#define CBR_RG_RX_HPF_SETTLE2_R_MSK 0x00000030
+#define CBR_RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
+#define CBR_RG_RX_HPF_SETTLE2_R_SFT 4
+#define CBR_RG_RX_HPF_SETTLE2_R_HI 5
+#define CBR_RG_RX_HPF_SETTLE2_R_SZ 2
+#define CBR_RG_RX_HPF_VCMCON2_MSK 0x000000c0
+#define CBR_RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
+#define CBR_RG_RX_HPF_VCMCON2_SFT 6
+#define CBR_RG_RX_HPF_VCMCON2_HI 7
+#define CBR_RG_RX_HPF_VCMCON2_SZ 2
+#define CBR_RG_RX_HPF_VCMCON_MSK 0x00000300
+#define CBR_RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
+#define CBR_RG_RX_HPF_VCMCON_SFT 8
+#define CBR_RG_RX_HPF_VCMCON_HI 9
+#define CBR_RG_RX_HPF_VCMCON_SZ 2
+#define CBR_RG_RX_OUTVCM_MSK 0x00000c00
+#define CBR_RG_RX_OUTVCM_I_MSK 0xfffff3ff
+#define CBR_RG_RX_OUTVCM_SFT 10
+#define CBR_RG_RX_OUTVCM_HI 11
+#define CBR_RG_RX_OUTVCM_SZ 2
+#define CBR_RG_RX_TZI_MSK 0x00003000
+#define CBR_RG_RX_TZI_I_MSK 0xffffcfff
+#define CBR_RG_RX_TZI_SFT 12
+#define CBR_RG_RX_TZI_HI 13
+#define CBR_RG_RX_TZI_SZ 2
+#define CBR_RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
+#define CBR_RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
+#define CBR_RG_RX_TZ_OUT_TRISTATE_SFT 14
+#define CBR_RG_RX_TZ_OUT_TRISTATE_HI 14
+#define CBR_RG_RX_TZ_OUT_TRISTATE_SZ 1
+#define CBR_RG_RX_TZ_VCM_MSK 0x00018000
+#define CBR_RG_RX_TZ_VCM_I_MSK 0xfffe7fff
+#define CBR_RG_RX_TZ_VCM_SFT 15
+#define CBR_RG_RX_TZ_VCM_HI 16
+#define CBR_RG_RX_TZ_VCM_SZ 2
+#define CBR_RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
+#define CBR_RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
+#define CBR_RG_EN_RX_RSSI_TESTNODE_SFT 17
+#define CBR_RG_EN_RX_RSSI_TESTNODE_HI 19
+#define CBR_RG_EN_RX_RSSI_TESTNODE_SZ 3
+#define CBR_RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
+#define CBR_RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
+#define CBR_RG_RX_ADCRSSI_CLKSEL_SFT 20
+#define CBR_RG_RX_ADCRSSI_CLKSEL_HI 20
+#define CBR_RG_RX_ADCRSSI_CLKSEL_SZ 1
+#define CBR_RG_RX_ADCRSSI_VCM_MSK 0x00600000
+#define CBR_RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
+#define CBR_RG_RX_ADCRSSI_VCM_SFT 21
+#define CBR_RG_RX_ADCRSSI_VCM_HI 22
+#define CBR_RG_RX_ADCRSSI_VCM_SZ 2
+#define CBR_RG_RX_REC_LPFCORNER_MSK 0x01800000
+#define CBR_RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
+#define CBR_RG_RX_REC_LPFCORNER_SFT 23
+#define CBR_RG_RX_REC_LPFCORNER_HI 24
+#define CBR_RG_RX_REC_LPFCORNER_SZ 2
+#define CBR_RG_RSSI_CLOCK_GATING_MSK 0x02000000
+#define CBR_RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
+#define CBR_RG_RSSI_CLOCK_GATING_SFT 25
+#define CBR_RG_RSSI_CLOCK_GATING_HI 25
+#define CBR_RG_RSSI_CLOCK_GATING_SZ 1
+#define CBR_RG_TXPGA_CAPSW_MSK 0x00000003
+#define CBR_RG_TXPGA_CAPSW_I_MSK 0xfffffffc
+#define CBR_RG_TXPGA_CAPSW_SFT 0
+#define CBR_RG_TXPGA_CAPSW_HI 1
+#define CBR_RG_TXPGA_CAPSW_SZ 2
+#define CBR_RG_TXPGA_MAIN_MSK 0x000000fc
+#define CBR_RG_TXPGA_MAIN_I_MSK 0xffffff03
+#define CBR_RG_TXPGA_MAIN_SFT 2
+#define CBR_RG_TXPGA_MAIN_HI 7
+#define CBR_RG_TXPGA_MAIN_SZ 6
+#define CBR_RG_TXPGA_STEER_MSK 0x00003f00
+#define CBR_RG_TXPGA_STEER_I_MSK 0xffffc0ff
+#define CBR_RG_TXPGA_STEER_SFT 8
+#define CBR_RG_TXPGA_STEER_HI 13
+#define CBR_RG_TXPGA_STEER_SZ 6
+#define CBR_RG_TXMOD_GMCELL_MSK 0x0000c000
+#define CBR_RG_TXMOD_GMCELL_I_MSK 0xffff3fff
+#define CBR_RG_TXMOD_GMCELL_SFT 14
+#define CBR_RG_TXMOD_GMCELL_HI 15
+#define CBR_RG_TXMOD_GMCELL_SZ 2
+#define CBR_RG_TXLPF_GMCELL_MSK 0x00030000
+#define CBR_RG_TXLPF_GMCELL_I_MSK 0xfffcffff
+#define CBR_RG_TXLPF_GMCELL_SFT 16
+#define CBR_RG_TXLPF_GMCELL_HI 17
+#define CBR_RG_TXLPF_GMCELL_SZ 2
+#define CBR_RG_PACELL_EN_MSK 0x001c0000
+#define CBR_RG_PACELL_EN_I_MSK 0xffe3ffff
+#define CBR_RG_PACELL_EN_SFT 18
+#define CBR_RG_PACELL_EN_HI 20
+#define CBR_RG_PACELL_EN_SZ 3
+#define CBR_RG_PABIAS_CTRL_MSK 0x01e00000
+#define CBR_RG_PABIAS_CTRL_I_MSK 0xfe1fffff
+#define CBR_RG_PABIAS_CTRL_SFT 21
+#define CBR_RG_PABIAS_CTRL_HI 24
+#define CBR_RG_PABIAS_CTRL_SZ 4
+#define CBR_RG_PABIAS_AB_MSK 0x02000000
+#define CBR_RG_PABIAS_AB_I_MSK 0xfdffffff
+#define CBR_RG_PABIAS_AB_SFT 25
+#define CBR_RG_PABIAS_AB_HI 25
+#define CBR_RG_PABIAS_AB_SZ 1
+#define CBR_RG_TX_DIV_VSET_MSK 0x0c000000
+#define CBR_RG_TX_DIV_VSET_I_MSK 0xf3ffffff
+#define CBR_RG_TX_DIV_VSET_SFT 26
+#define CBR_RG_TX_DIV_VSET_HI 27
+#define CBR_RG_TX_DIV_VSET_SZ 2
+#define CBR_RG_TX_LOBUF_VSET_MSK 0x30000000
+#define CBR_RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
+#define CBR_RG_TX_LOBUF_VSET_SFT 28
+#define CBR_RG_TX_LOBUF_VSET_HI 29
+#define CBR_RG_TX_LOBUF_VSET_SZ 2
+#define CBR_RG_RX_SQDC_MSK 0x00000007
+#define CBR_RG_RX_SQDC_I_MSK 0xfffffff8
+#define CBR_RG_RX_SQDC_SFT 0
+#define CBR_RG_RX_SQDC_HI 2
+#define CBR_RG_RX_SQDC_SZ 3
+#define CBR_RG_RX_DIV2_CORE_MSK 0x00000018
+#define CBR_RG_RX_DIV2_CORE_I_MSK 0xffffffe7
+#define CBR_RG_RX_DIV2_CORE_SFT 3
+#define CBR_RG_RX_DIV2_CORE_HI 4
+#define CBR_RG_RX_DIV2_CORE_SZ 2
+#define CBR_RG_RX_LOBUF_MSK 0x00000060
+#define CBR_RG_RX_LOBUF_I_MSK 0xffffff9f
+#define CBR_RG_RX_LOBUF_SFT 5
+#define CBR_RG_RX_LOBUF_HI 6
+#define CBR_RG_RX_LOBUF_SZ 2
+#define CBR_RG_TX_DPDGM_BIAS_MSK 0x00000780
+#define CBR_RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
+#define CBR_RG_TX_DPDGM_BIAS_SFT 7
+#define CBR_RG_TX_DPDGM_BIAS_HI 10
+#define CBR_RG_TX_DPDGM_BIAS_SZ 4
+#define CBR_RG_TX_DPD_DIV_MSK 0x00007800
+#define CBR_RG_TX_DPD_DIV_I_MSK 0xffff87ff
+#define CBR_RG_TX_DPD_DIV_SFT 11
+#define CBR_RG_TX_DPD_DIV_HI 14
+#define CBR_RG_TX_DPD_DIV_SZ 4
+#define CBR_RG_TX_TSSI_BIAS_MSK 0x00038000
+#define CBR_RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
+#define CBR_RG_TX_TSSI_BIAS_SFT 15
+#define CBR_RG_TX_TSSI_BIAS_HI 17
+#define CBR_RG_TX_TSSI_BIAS_SZ 3
+#define CBR_RG_TX_TSSI_DIV_MSK 0x001c0000
+#define CBR_RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
+#define CBR_RG_TX_TSSI_DIV_SFT 18
+#define CBR_RG_TX_TSSI_DIV_HI 20
+#define CBR_RG_TX_TSSI_DIV_SZ 3
+#define CBR_RG_TX_TSSI_TESTMODE_MSK 0x00200000
+#define CBR_RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
+#define CBR_RG_TX_TSSI_TESTMODE_SFT 21
+#define CBR_RG_TX_TSSI_TESTMODE_HI 21
+#define CBR_RG_TX_TSSI_TESTMODE_SZ 1
+#define CBR_RG_TX_TSSI_TEST_MSK 0x00c00000
+#define CBR_RG_TX_TSSI_TEST_I_MSK 0xff3fffff
+#define CBR_RG_TX_TSSI_TEST_SFT 22
+#define CBR_RG_TX_TSSI_TEST_HI 23
+#define CBR_RG_TX_TSSI_TEST_SZ 2
+#define CBR_RG_RX_HG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_HG_LNA_GC_SFT 0
+#define CBR_RG_RX_HG_LNA_GC_HI 1
+#define CBR_RG_RX_HG_LNA_GC_SZ 2
+#define CBR_RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_HG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_HG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_HG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_HG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_HG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_HG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_HG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_HG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_HG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_HG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_HG_TZ_GC_SFT 14
+#define CBR_RG_RX_HG_TZ_GC_HI 15
+#define CBR_RG_RX_HG_TZ_GC_SZ 2
+#define CBR_RG_RX_HG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_HG_TZ_CAP_SFT 16
+#define CBR_RG_RX_HG_TZ_CAP_HI 18
+#define CBR_RG_RX_HG_TZ_CAP_SZ 3
+#define CBR_RG_RX_MG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_MG_LNA_GC_SFT 0
+#define CBR_RG_RX_MG_LNA_GC_HI 1
+#define CBR_RG_RX_MG_LNA_GC_SZ 2
+#define CBR_RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_MG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_MG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_MG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_MG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_MG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_MG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_MG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_MG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_MG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_MG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_MG_TZ_GC_SFT 14
+#define CBR_RG_RX_MG_TZ_GC_HI 15
+#define CBR_RG_RX_MG_TZ_GC_SZ 2
+#define CBR_RG_RX_MG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_MG_TZ_CAP_SFT 16
+#define CBR_RG_RX_MG_TZ_CAP_HI 18
+#define CBR_RG_RX_MG_TZ_CAP_SZ 3
+#define CBR_RG_RX_LG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_LG_LNA_GC_SFT 0
+#define CBR_RG_RX_LG_LNA_GC_HI 1
+#define CBR_RG_RX_LG_LNA_GC_SZ 2
+#define CBR_RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_LG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_LG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_LG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_LG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_LG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_LG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_LG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_LG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_LG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_LG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_LG_TZ_GC_SFT 14
+#define CBR_RG_RX_LG_TZ_GC_HI 15
+#define CBR_RG_RX_LG_TZ_GC_SZ 2
+#define CBR_RG_RX_LG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_LG_TZ_CAP_SFT 16
+#define CBR_RG_RX_LG_TZ_CAP_HI 18
+#define CBR_RG_RX_LG_TZ_CAP_SZ 3
+#define CBR_RG_RX_ULG_LNA_GC_MSK 0x00000003
+#define CBR_RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define CBR_RG_RX_ULG_LNA_GC_SFT 0
+#define CBR_RG_RX_ULG_LNA_GC_HI 1
+#define CBR_RG_RX_ULG_LNA_GC_SZ 2
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_SFT 2
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_HI 5
+#define CBR_RG_RX_ULG_LNAHGN_BIAS_SZ 4
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_SFT 6
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_HI 9
+#define CBR_RG_RX_ULG_LNAHGP_BIAS_SZ 4
+#define CBR_RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
+#define CBR_RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define CBR_RG_RX_ULG_LNALG_BIAS_SFT 10
+#define CBR_RG_RX_ULG_LNALG_BIAS_HI 13
+#define CBR_RG_RX_ULG_LNALG_BIAS_SZ 4
+#define CBR_RG_RX_ULG_TZ_GC_MSK 0x0000c000
+#define CBR_RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
+#define CBR_RG_RX_ULG_TZ_GC_SFT 14
+#define CBR_RG_RX_ULG_TZ_GC_HI 15
+#define CBR_RG_RX_ULG_TZ_GC_SZ 2
+#define CBR_RG_RX_ULG_TZ_CAP_MSK 0x00070000
+#define CBR_RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define CBR_RG_RX_ULG_TZ_CAP_SFT 16
+#define CBR_RG_RX_ULG_TZ_CAP_HI 18
+#define CBR_RG_RX_ULG_TZ_CAP_SZ 3
+#define CBR_RG_HPF1_FAST_SET_X_MSK 0x00000001
+#define CBR_RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
+#define CBR_RG_HPF1_FAST_SET_X_SFT 0
+#define CBR_RG_HPF1_FAST_SET_X_HI 0
+#define CBR_RG_HPF1_FAST_SET_X_SZ 1
+#define CBR_RG_HPF1_FAST_SET_Y_MSK 0x00000002
+#define CBR_RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
+#define CBR_RG_HPF1_FAST_SET_Y_SFT 1
+#define CBR_RG_HPF1_FAST_SET_Y_HI 1
+#define CBR_RG_HPF1_FAST_SET_Y_SZ 1
+#define CBR_RG_HPF1_FAST_SET_Z_MSK 0x00000004
+#define CBR_RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
+#define CBR_RG_HPF1_FAST_SET_Z_SFT 2
+#define CBR_RG_HPF1_FAST_SET_Z_HI 2
+#define CBR_RG_HPF1_FAST_SET_Z_SZ 1
+#define CBR_RG_HPF_T1A_MSK 0x00000018
+#define CBR_RG_HPF_T1A_I_MSK 0xffffffe7
+#define CBR_RG_HPF_T1A_SFT 3
+#define CBR_RG_HPF_T1A_HI 4
+#define CBR_RG_HPF_T1A_SZ 2
+#define CBR_RG_HPF_T1B_MSK 0x00000060
+#define CBR_RG_HPF_T1B_I_MSK 0xffffff9f
+#define CBR_RG_HPF_T1B_SFT 5
+#define CBR_RG_HPF_T1B_HI 6
+#define CBR_RG_HPF_T1B_SZ 2
+#define CBR_RG_HPF_T1C_MSK 0x00000180
+#define CBR_RG_HPF_T1C_I_MSK 0xfffffe7f
+#define CBR_RG_HPF_T1C_SFT 7
+#define CBR_RG_HPF_T1C_HI 8
+#define CBR_RG_HPF_T1C_SZ 2
+#define CBR_RG_RX_LNA_TRI_SEL_MSK 0x00000600
+#define CBR_RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
+#define CBR_RG_RX_LNA_TRI_SEL_SFT 9
+#define CBR_RG_RX_LNA_TRI_SEL_HI 10
+#define CBR_RG_RX_LNA_TRI_SEL_SZ 2
+#define CBR_RG_RX_LNA_SETTLE_MSK 0x00001800
+#define CBR_RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
+#define CBR_RG_RX_LNA_SETTLE_SFT 11
+#define CBR_RG_RX_LNA_SETTLE_HI 12
+#define CBR_RG_RX_LNA_SETTLE_SZ 2
+#define CBR_RG_ADC_CLKSEL_MSK 0x00000001
+#define CBR_RG_ADC_CLKSEL_I_MSK 0xfffffffe
+#define CBR_RG_ADC_CLKSEL_SFT 0
+#define CBR_RG_ADC_CLKSEL_HI 0
+#define CBR_RG_ADC_CLKSEL_SZ 1
+#define CBR_RG_ADC_DIBIAS_MSK 0x00000006
+#define CBR_RG_ADC_DIBIAS_I_MSK 0xfffffff9
+#define CBR_RG_ADC_DIBIAS_SFT 1
+#define CBR_RG_ADC_DIBIAS_HI 2
+#define CBR_RG_ADC_DIBIAS_SZ 2
+#define CBR_RG_ADC_DIVR_MSK 0x00000008
+#define CBR_RG_ADC_DIVR_I_MSK 0xfffffff7
+#define CBR_RG_ADC_DIVR_SFT 3
+#define CBR_RG_ADC_DIVR_HI 3
+#define CBR_RG_ADC_DIVR_SZ 1
+#define CBR_RG_ADC_DVCMI_MSK 0x00000030
+#define CBR_RG_ADC_DVCMI_I_MSK 0xffffffcf
+#define CBR_RG_ADC_DVCMI_SFT 4
+#define CBR_RG_ADC_DVCMI_HI 5
+#define CBR_RG_ADC_DVCMI_SZ 2
+#define CBR_RG_ADC_SAMSEL_MSK 0x000003c0
+#define CBR_RG_ADC_SAMSEL_I_MSK 0xfffffc3f
+#define CBR_RG_ADC_SAMSEL_SFT 6
+#define CBR_RG_ADC_SAMSEL_HI 9
+#define CBR_RG_ADC_SAMSEL_SZ 4
+#define CBR_RG_ADC_STNBY_MSK 0x00000400
+#define CBR_RG_ADC_STNBY_I_MSK 0xfffffbff
+#define CBR_RG_ADC_STNBY_SFT 10
+#define CBR_RG_ADC_STNBY_HI 10
+#define CBR_RG_ADC_STNBY_SZ 1
+#define CBR_RG_ADC_TESTMODE_MSK 0x00000800
+#define CBR_RG_ADC_TESTMODE_I_MSK 0xfffff7ff
+#define CBR_RG_ADC_TESTMODE_SFT 11
+#define CBR_RG_ADC_TESTMODE_HI 11
+#define CBR_RG_ADC_TESTMODE_SZ 1
+#define CBR_RG_ADC_TSEL_MSK 0x0000f000
+#define CBR_RG_ADC_TSEL_I_MSK 0xffff0fff
+#define CBR_RG_ADC_TSEL_SFT 12
+#define CBR_RG_ADC_TSEL_HI 15
+#define CBR_RG_ADC_TSEL_SZ 4
+#define CBR_RG_ADC_VRSEL_MSK 0x00030000
+#define CBR_RG_ADC_VRSEL_I_MSK 0xfffcffff
+#define CBR_RG_ADC_VRSEL_SFT 16
+#define CBR_RG_ADC_VRSEL_HI 17
+#define CBR_RG_ADC_VRSEL_SZ 2
+#define CBR_RG_DICMP_MSK 0x000c0000
+#define CBR_RG_DICMP_I_MSK 0xfff3ffff
+#define CBR_RG_DICMP_SFT 18
+#define CBR_RG_DICMP_HI 19
+#define CBR_RG_DICMP_SZ 2
+#define CBR_RG_DIOP_MSK 0x00300000
+#define CBR_RG_DIOP_I_MSK 0xffcfffff
+#define CBR_RG_DIOP_SFT 20
+#define CBR_RG_DIOP_HI 21
+#define CBR_RG_DIOP_SZ 2
+#define CBR_RG_DACI1ST_MSK 0x00000003
+#define CBR_RG_DACI1ST_I_MSK 0xfffffffc
+#define CBR_RG_DACI1ST_SFT 0
+#define CBR_RG_DACI1ST_HI 1
+#define CBR_RG_DACI1ST_SZ 2
+#define CBR_RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
+#define CBR_RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
+#define CBR_RG_TX_DACLPF_ICOURSE_SFT 2
+#define CBR_RG_TX_DACLPF_ICOURSE_HI 3
+#define CBR_RG_TX_DACLPF_ICOURSE_SZ 2
+#define CBR_RG_TX_DACLPF_IFINE_MSK 0x00000030
+#define CBR_RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define CBR_RG_TX_DACLPF_IFINE_SFT 4
+#define CBR_RG_TX_DACLPF_IFINE_HI 5
+#define CBR_RG_TX_DACLPF_IFINE_SZ 2
+#define CBR_RG_TX_DACLPF_VCM_MSK 0x000000c0
+#define CBR_RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define CBR_RG_TX_DACLPF_VCM_SFT 6
+#define CBR_RG_TX_DACLPF_VCM_HI 7
+#define CBR_RG_TX_DACLPF_VCM_SZ 2
+#define CBR_RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
+#define CBR_RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
+#define CBR_RG_TX_DAC_CKEDGE_SEL_SFT 8
+#define CBR_RG_TX_DAC_CKEDGE_SEL_HI 8
+#define CBR_RG_TX_DAC_CKEDGE_SEL_SZ 1
+#define CBR_RG_TX_DAC_IBIAS_MSK 0x00000600
+#define CBR_RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
+#define CBR_RG_TX_DAC_IBIAS_SFT 9
+#define CBR_RG_TX_DAC_IBIAS_HI 10
+#define CBR_RG_TX_DAC_IBIAS_SZ 2
+#define CBR_RG_TX_DAC_OS_MSK 0x00003800
+#define CBR_RG_TX_DAC_OS_I_MSK 0xffffc7ff
+#define CBR_RG_TX_DAC_OS_SFT 11
+#define CBR_RG_TX_DAC_OS_HI 13
+#define CBR_RG_TX_DAC_OS_SZ 3
+#define CBR_RG_TX_DAC_RCAL_MSK 0x0000c000
+#define CBR_RG_TX_DAC_RCAL_I_MSK 0xffff3fff
+#define CBR_RG_TX_DAC_RCAL_SFT 14
+#define CBR_RG_TX_DAC_RCAL_HI 15
+#define CBR_RG_TX_DAC_RCAL_SZ 2
+#define CBR_RG_TX_DAC_TSEL_MSK 0x000f0000
+#define CBR_RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
+#define CBR_RG_TX_DAC_TSEL_SFT 16
+#define CBR_RG_TX_DAC_TSEL_HI 19
+#define CBR_RG_TX_DAC_TSEL_SZ 4
+#define CBR_RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
+#define CBR_RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
+#define CBR_RG_TX_EN_VOLTAGE_IN_SFT 20
+#define CBR_RG_TX_EN_VOLTAGE_IN_HI 20
+#define CBR_RG_TX_EN_VOLTAGE_IN_SZ 1
+#define CBR_RG_TXLPF_BYPASS_MSK 0x00200000
+#define CBR_RG_TXLPF_BYPASS_I_MSK 0xffdfffff
+#define CBR_RG_TXLPF_BYPASS_SFT 21
+#define CBR_RG_TXLPF_BYPASS_HI 21
+#define CBR_RG_TXLPF_BYPASS_SZ 1
+#define CBR_RG_TXLPF_BOOSTI_MSK 0x00400000
+#define CBR_RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
+#define CBR_RG_TXLPF_BOOSTI_SFT 22
+#define CBR_RG_TXLPF_BOOSTI_HI 22
+#define CBR_RG_TXLPF_BOOSTI_SZ 1
+#define CBR_RG_EN_SX_R3_MSK 0x00000001
+#define CBR_RG_EN_SX_R3_I_MSK 0xfffffffe
+#define CBR_RG_EN_SX_R3_SFT 0
+#define CBR_RG_EN_SX_R3_HI 0
+#define CBR_RG_EN_SX_R3_SZ 1
+#define CBR_RG_EN_SX_CH_MSK 0x00000002
+#define CBR_RG_EN_SX_CH_I_MSK 0xfffffffd
+#define CBR_RG_EN_SX_CH_SFT 1
+#define CBR_RG_EN_SX_CH_HI 1
+#define CBR_RG_EN_SX_CH_SZ 1
+#define CBR_RG_EN_SX_CHP_MSK 0x00000004
+#define CBR_RG_EN_SX_CHP_I_MSK 0xfffffffb
+#define CBR_RG_EN_SX_CHP_SFT 2
+#define CBR_RG_EN_SX_CHP_HI 2
+#define CBR_RG_EN_SX_CHP_SZ 1
+#define CBR_RG_EN_SX_DIVCK_MSK 0x00000008
+#define CBR_RG_EN_SX_DIVCK_I_MSK 0xfffffff7
+#define CBR_RG_EN_SX_DIVCK_SFT 3
+#define CBR_RG_EN_SX_DIVCK_HI 3
+#define CBR_RG_EN_SX_DIVCK_SZ 1
+#define CBR_RG_EN_SX_VCOBF_MSK 0x00000010
+#define CBR_RG_EN_SX_VCOBF_I_MSK 0xffffffef
+#define CBR_RG_EN_SX_VCOBF_SFT 4
+#define CBR_RG_EN_SX_VCOBF_HI 4
+#define CBR_RG_EN_SX_VCOBF_SZ 1
+#define CBR_RG_EN_SX_VCO_MSK 0x00000020
+#define CBR_RG_EN_SX_VCO_I_MSK 0xffffffdf
+#define CBR_RG_EN_SX_VCO_SFT 5
+#define CBR_RG_EN_SX_VCO_HI 5
+#define CBR_RG_EN_SX_VCO_SZ 1
+#define CBR_RG_EN_SX_MOD_MSK 0x00000040
+#define CBR_RG_EN_SX_MOD_I_MSK 0xffffffbf
+#define CBR_RG_EN_SX_MOD_SFT 6
+#define CBR_RG_EN_SX_MOD_HI 6
+#define CBR_RG_EN_SX_MOD_SZ 1
+#define CBR_RG_EN_SX_LCK_MSK 0x00000080
+#define CBR_RG_EN_SX_LCK_I_MSK 0xffffff7f
+#define CBR_RG_EN_SX_LCK_SFT 7
+#define CBR_RG_EN_SX_LCK_HI 7
+#define CBR_RG_EN_SX_LCK_SZ 1
+#define CBR_RG_EN_SX_DITHER_MSK 0x00000100
+#define CBR_RG_EN_SX_DITHER_I_MSK 0xfffffeff
+#define CBR_RG_EN_SX_DITHER_SFT 8
+#define CBR_RG_EN_SX_DITHER_HI 8
+#define CBR_RG_EN_SX_DITHER_SZ 1
+#define CBR_RG_EN_SX_DELCAL_MSK 0x00000200
+#define CBR_RG_EN_SX_DELCAL_I_MSK 0xfffffdff
+#define CBR_RG_EN_SX_DELCAL_SFT 9
+#define CBR_RG_EN_SX_DELCAL_HI 9
+#define CBR_RG_EN_SX_DELCAL_SZ 1
+#define CBR_RG_EN_SX_PC_BYPASS_MSK 0x00000400
+#define CBR_RG_EN_SX_PC_BYPASS_I_MSK 0xfffffbff
+#define CBR_RG_EN_SX_PC_BYPASS_SFT 10
+#define CBR_RG_EN_SX_PC_BYPASS_HI 10
+#define CBR_RG_EN_SX_PC_BYPASS_SZ 1
+#define CBR_RG_EN_SX_VT_MON_MSK 0x00000800
+#define CBR_RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
+#define CBR_RG_EN_SX_VT_MON_SFT 11
+#define CBR_RG_EN_SX_VT_MON_HI 11
+#define CBR_RG_EN_SX_VT_MON_SZ 1
+#define CBR_RG_EN_SX_VT_MON_DG_MSK 0x00001000
+#define CBR_RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
+#define CBR_RG_EN_SX_VT_MON_DG_SFT 12
+#define CBR_RG_EN_SX_VT_MON_DG_HI 12
+#define CBR_RG_EN_SX_VT_MON_DG_SZ 1
+#define CBR_RG_EN_SX_DIV_MSK 0x00002000
+#define CBR_RG_EN_SX_DIV_I_MSK 0xffffdfff
+#define CBR_RG_EN_SX_DIV_SFT 13
+#define CBR_RG_EN_SX_DIV_HI 13
+#define CBR_RG_EN_SX_DIV_SZ 1
+#define CBR_RG_EN_SX_LPF_MSK 0x00004000
+#define CBR_RG_EN_SX_LPF_I_MSK 0xffffbfff
+#define CBR_RG_EN_SX_LPF_SFT 14
+#define CBR_RG_EN_SX_LPF_HI 14
+#define CBR_RG_EN_SX_LPF_SZ 1
+#define CBR_RG_SX_RFCTRL_F_MSK 0x00ffffff
+#define CBR_RG_SX_RFCTRL_F_I_MSK 0xff000000
+#define CBR_RG_SX_RFCTRL_F_SFT 0
+#define CBR_RG_SX_RFCTRL_F_HI 23
+#define CBR_RG_SX_RFCTRL_F_SZ 24
+#define CBR_RG_SX_SEL_CP_MSK 0x0f000000
+#define CBR_RG_SX_SEL_CP_I_MSK 0xf0ffffff
+#define CBR_RG_SX_SEL_CP_SFT 24
+#define CBR_RG_SX_SEL_CP_HI 27
+#define CBR_RG_SX_SEL_CP_SZ 4
+#define CBR_RG_SX_SEL_CS_MSK 0xf0000000
+#define CBR_RG_SX_SEL_CS_I_MSK 0x0fffffff
+#define CBR_RG_SX_SEL_CS_SFT 28
+#define CBR_RG_SX_SEL_CS_HI 31
+#define CBR_RG_SX_SEL_CS_SZ 4
+#define CBR_RG_SX_RFCTRL_CH_MSK 0x000007ff
+#define CBR_RG_SX_RFCTRL_CH_I_MSK 0xfffff800
+#define CBR_RG_SX_RFCTRL_CH_SFT 0
+#define CBR_RG_SX_RFCTRL_CH_HI 10
+#define CBR_RG_SX_RFCTRL_CH_SZ 11
+#define CBR_RG_SX_SEL_C3_MSK 0x00007800
+#define CBR_RG_SX_SEL_C3_I_MSK 0xffff87ff
+#define CBR_RG_SX_SEL_C3_SFT 11
+#define CBR_RG_SX_SEL_C3_HI 14
+#define CBR_RG_SX_SEL_C3_SZ 4
+#define CBR_RG_SX_SEL_RS_MSK 0x000f8000
+#define CBR_RG_SX_SEL_RS_I_MSK 0xfff07fff
+#define CBR_RG_SX_SEL_RS_SFT 15
+#define CBR_RG_SX_SEL_RS_HI 19
+#define CBR_RG_SX_SEL_RS_SZ 5
+#define CBR_RG_SX_SEL_R3_MSK 0x01f00000
+#define CBR_RG_SX_SEL_R3_I_MSK 0xfe0fffff
+#define CBR_RG_SX_SEL_R3_SFT 20
+#define CBR_RG_SX_SEL_R3_HI 24
+#define CBR_RG_SX_SEL_R3_SZ 5
+#define CBR_RG_SX_SEL_ICHP_MSK 0x0000001f
+#define CBR_RG_SX_SEL_ICHP_I_MSK 0xffffffe0
+#define CBR_RG_SX_SEL_ICHP_SFT 0
+#define CBR_RG_SX_SEL_ICHP_HI 4
+#define CBR_RG_SX_SEL_ICHP_SZ 5
+#define CBR_RG_SX_SEL_PCHP_MSK 0x000003e0
+#define CBR_RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
+#define CBR_RG_SX_SEL_PCHP_SFT 5
+#define CBR_RG_SX_SEL_PCHP_HI 9
+#define CBR_RG_SX_SEL_PCHP_SZ 5
+#define CBR_RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
+#define CBR_RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
+#define CBR_RG_SX_SEL_CHP_REGOP_SFT 10
+#define CBR_RG_SX_SEL_CHP_REGOP_HI 13
+#define CBR_RG_SX_SEL_CHP_REGOP_SZ 4
+#define CBR_RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
+#define CBR_RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
+#define CBR_RG_SX_SEL_CHP_UNIOP_SFT 14
+#define CBR_RG_SX_SEL_CHP_UNIOP_HI 17
+#define CBR_RG_SX_SEL_CHP_UNIOP_SZ 4
+#define CBR_RG_SX_CHP_IOST_POL_MSK 0x00040000
+#define CBR_RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
+#define CBR_RG_SX_CHP_IOST_POL_SFT 18
+#define CBR_RG_SX_CHP_IOST_POL_HI 18
+#define CBR_RG_SX_CHP_IOST_POL_SZ 1
+#define CBR_RG_SX_CHP_IOST_MSK 0x00380000
+#define CBR_RG_SX_CHP_IOST_I_MSK 0xffc7ffff
+#define CBR_RG_SX_CHP_IOST_SFT 19
+#define CBR_RG_SX_CHP_IOST_HI 21
+#define CBR_RG_SX_CHP_IOST_SZ 3
+#define CBR_RG_SX_PFDSEL_MSK 0x00400000
+#define CBR_RG_SX_PFDSEL_I_MSK 0xffbfffff
+#define CBR_RG_SX_PFDSEL_SFT 22
+#define CBR_RG_SX_PFDSEL_HI 22
+#define CBR_RG_SX_PFDSEL_SZ 1
+#define CBR_RG_SX_PFD_SET_MSK 0x00800000
+#define CBR_RG_SX_PFD_SET_I_MSK 0xff7fffff
+#define CBR_RG_SX_PFD_SET_SFT 23
+#define CBR_RG_SX_PFD_SET_HI 23
+#define CBR_RG_SX_PFD_SET_SZ 1
+#define CBR_RG_SX_PFD_SET1_MSK 0x01000000
+#define CBR_RG_SX_PFD_SET1_I_MSK 0xfeffffff
+#define CBR_RG_SX_PFD_SET1_SFT 24
+#define CBR_RG_SX_PFD_SET1_HI 24
+#define CBR_RG_SX_PFD_SET1_SZ 1
+#define CBR_RG_SX_PFD_SET2_MSK 0x02000000
+#define CBR_RG_SX_PFD_SET2_I_MSK 0xfdffffff
+#define CBR_RG_SX_PFD_SET2_SFT 25
+#define CBR_RG_SX_PFD_SET2_HI 25
+#define CBR_RG_SX_PFD_SET2_SZ 1
+#define CBR_RG_SX_VBNCAS_SEL_MSK 0x04000000
+#define CBR_RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
+#define CBR_RG_SX_VBNCAS_SEL_SFT 26
+#define CBR_RG_SX_VBNCAS_SEL_HI 26
+#define CBR_RG_SX_VBNCAS_SEL_SZ 1
+#define CBR_RG_SX_PFD_RST_H_MSK 0x08000000
+#define CBR_RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
+#define CBR_RG_SX_PFD_RST_H_SFT 27
+#define CBR_RG_SX_PFD_RST_H_HI 27
+#define CBR_RG_SX_PFD_RST_H_SZ 1
+#define CBR_RG_SX_PFD_TRUP_MSK 0x10000000
+#define CBR_RG_SX_PFD_TRUP_I_MSK 0xefffffff
+#define CBR_RG_SX_PFD_TRUP_SFT 28
+#define CBR_RG_SX_PFD_TRUP_HI 28
+#define CBR_RG_SX_PFD_TRUP_SZ 1
+#define CBR_RG_SX_PFD_TRDN_MSK 0x20000000
+#define CBR_RG_SX_PFD_TRDN_I_MSK 0xdfffffff
+#define CBR_RG_SX_PFD_TRDN_SFT 29
+#define CBR_RG_SX_PFD_TRDN_HI 29
+#define CBR_RG_SX_PFD_TRDN_SZ 1
+#define CBR_RG_SX_PFD_TRSEL_MSK 0x40000000
+#define CBR_RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
+#define CBR_RG_SX_PFD_TRSEL_SFT 30
+#define CBR_RG_SX_PFD_TRSEL_HI 30
+#define CBR_RG_SX_PFD_TRSEL_SZ 1
+#define CBR_RG_SX_VCOBA_R_MSK 0x00000007
+#define CBR_RG_SX_VCOBA_R_I_MSK 0xfffffff8
+#define CBR_RG_SX_VCOBA_R_SFT 0
+#define CBR_RG_SX_VCOBA_R_HI 2
+#define CBR_RG_SX_VCOBA_R_SZ 3
+#define CBR_RG_SX_VCORSEL_MSK 0x000000f8
+#define CBR_RG_SX_VCORSEL_I_MSK 0xffffff07
+#define CBR_RG_SX_VCORSEL_SFT 3
+#define CBR_RG_SX_VCORSEL_HI 7
+#define CBR_RG_SX_VCORSEL_SZ 5
+#define CBR_RG_SX_VCOCUSEL_MSK 0x00000f00
+#define CBR_RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
+#define CBR_RG_SX_VCOCUSEL_SFT 8
+#define CBR_RG_SX_VCOCUSEL_HI 11
+#define CBR_RG_SX_VCOCUSEL_SZ 4
+#define CBR_RG_SX_RXBFSEL_MSK 0x0000f000
+#define CBR_RG_SX_RXBFSEL_I_MSK 0xffff0fff
+#define CBR_RG_SX_RXBFSEL_SFT 12
+#define CBR_RG_SX_RXBFSEL_HI 15
+#define CBR_RG_SX_RXBFSEL_SZ 4
+#define CBR_RG_SX_TXBFSEL_MSK 0x000f0000
+#define CBR_RG_SX_TXBFSEL_I_MSK 0xfff0ffff
+#define CBR_RG_SX_TXBFSEL_SFT 16
+#define CBR_RG_SX_TXBFSEL_HI 19
+#define CBR_RG_SX_TXBFSEL_SZ 4
+#define CBR_RG_SX_VCOBFSEL_MSK 0x00f00000
+#define CBR_RG_SX_VCOBFSEL_I_MSK 0xff0fffff
+#define CBR_RG_SX_VCOBFSEL_SFT 20
+#define CBR_RG_SX_VCOBFSEL_HI 23
+#define CBR_RG_SX_VCOBFSEL_SZ 4
+#define CBR_RG_SX_DIVBFSEL_MSK 0x0f000000
+#define CBR_RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
+#define CBR_RG_SX_DIVBFSEL_SFT 24
+#define CBR_RG_SX_DIVBFSEL_HI 27
+#define CBR_RG_SX_DIVBFSEL_SZ 4
+#define CBR_RG_SX_GNDR_SEL_MSK 0xf0000000
+#define CBR_RG_SX_GNDR_SEL_I_MSK 0x0fffffff
+#define CBR_RG_SX_GNDR_SEL_SFT 28
+#define CBR_RG_SX_GNDR_SEL_HI 31
+#define CBR_RG_SX_GNDR_SEL_SZ 4
+#define CBR_RG_SX_DITHER_WEIGHT_MSK 0x00000003
+#define CBR_RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
+#define CBR_RG_SX_DITHER_WEIGHT_SFT 0
+#define CBR_RG_SX_DITHER_WEIGHT_HI 1
+#define CBR_RG_SX_DITHER_WEIGHT_SZ 2
+#define CBR_RG_SX_MOD_ERRCMP_MSK 0x0000000c
+#define CBR_RG_SX_MOD_ERRCMP_I_MSK 0xfffffff3
+#define CBR_RG_SX_MOD_ERRCMP_SFT 2
+#define CBR_RG_SX_MOD_ERRCMP_HI 3
+#define CBR_RG_SX_MOD_ERRCMP_SZ 2
+#define CBR_RG_SX_MOD_ORDER_MSK 0x00000030
+#define CBR_RG_SX_MOD_ORDER_I_MSK 0xffffffcf
+#define CBR_RG_SX_MOD_ORDER_SFT 4
+#define CBR_RG_SX_MOD_ORDER_HI 5
+#define CBR_RG_SX_MOD_ORDER_SZ 2
+#define CBR_RG_SX_SDM_D1_MSK 0x00000040
+#define CBR_RG_SX_SDM_D1_I_MSK 0xffffffbf
+#define CBR_RG_SX_SDM_D1_SFT 6
+#define CBR_RG_SX_SDM_D1_HI 6
+#define CBR_RG_SX_SDM_D1_SZ 1
+#define CBR_RG_SX_SDM_D2_MSK 0x00000080
+#define CBR_RG_SX_SDM_D2_I_MSK 0xffffff7f
+#define CBR_RG_SX_SDM_D2_SFT 7
+#define CBR_RG_SX_SDM_D2_HI 7
+#define CBR_RG_SX_SDM_D2_SZ 1
+#define CBR_RG_SDM_PASS_MSK 0x00000100
+#define CBR_RG_SDM_PASS_I_MSK 0xfffffeff
+#define CBR_RG_SDM_PASS_SFT 8
+#define CBR_RG_SDM_PASS_HI 8
+#define CBR_RG_SDM_PASS_SZ 1
+#define CBR_RG_SX_RST_H_DIV_MSK 0x00000200
+#define CBR_RG_SX_RST_H_DIV_I_MSK 0xfffffdff
+#define CBR_RG_SX_RST_H_DIV_SFT 9
+#define CBR_RG_SX_RST_H_DIV_HI 9
+#define CBR_RG_SX_RST_H_DIV_SZ 1
+#define CBR_RG_SX_SDM_EDGE_MSK 0x00000400
+#define CBR_RG_SX_SDM_EDGE_I_MSK 0xfffffbff
+#define CBR_RG_SX_SDM_EDGE_SFT 10
+#define CBR_RG_SX_SDM_EDGE_HI 10
+#define CBR_RG_SX_SDM_EDGE_SZ 1
+#define CBR_RG_SX_XO_GM_MSK 0x00001800
+#define CBR_RG_SX_XO_GM_I_MSK 0xffffe7ff
+#define CBR_RG_SX_XO_GM_SFT 11
+#define CBR_RG_SX_XO_GM_HI 12
+#define CBR_RG_SX_XO_GM_SZ 2
+#define CBR_RG_SX_REFBYTWO_MSK 0x00002000
+#define CBR_RG_SX_REFBYTWO_I_MSK 0xffffdfff
+#define CBR_RG_SX_REFBYTWO_SFT 13
+#define CBR_RG_SX_REFBYTWO_HI 13
+#define CBR_RG_SX_REFBYTWO_SZ 1
+#define CBR_RG_SX_XO_SWCAP_MSK 0x0003c000
+#define CBR_RG_SX_XO_SWCAP_I_MSK 0xfffc3fff
+#define CBR_RG_SX_XO_SWCAP_SFT 14
+#define CBR_RG_SX_XO_SWCAP_HI 17
+#define CBR_RG_SX_XO_SWCAP_SZ 4
+#define CBR_RG_SX_SDMLUT_INV_MSK 0x00040000
+#define CBR_RG_SX_SDMLUT_INV_I_MSK 0xfffbffff
+#define CBR_RG_SX_SDMLUT_INV_SFT 18
+#define CBR_RG_SX_SDMLUT_INV_HI 18
+#define CBR_RG_SX_SDMLUT_INV_SZ 1
+#define CBR_RG_SX_LCKEN_MSK 0x00080000
+#define CBR_RG_SX_LCKEN_I_MSK 0xfff7ffff
+#define CBR_RG_SX_LCKEN_SFT 19
+#define CBR_RG_SX_LCKEN_HI 19
+#define CBR_RG_SX_LCKEN_SZ 1
+#define CBR_RG_SX_PREVDD_MSK 0x00f00000
+#define CBR_RG_SX_PREVDD_I_MSK 0xff0fffff
+#define CBR_RG_SX_PREVDD_SFT 20
+#define CBR_RG_SX_PREVDD_HI 23
+#define CBR_RG_SX_PREVDD_SZ 4
+#define CBR_RG_SX_PSCONTERVDD_MSK 0x0f000000
+#define CBR_RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
+#define CBR_RG_SX_PSCONTERVDD_SFT 24
+#define CBR_RG_SX_PSCONTERVDD_HI 27
+#define CBR_RG_SX_PSCONTERVDD_SZ 4
+#define CBR_RG_SX_MOD_ERR_DELAY_MSK 0x30000000
+#define CBR_RG_SX_MOD_ERR_DELAY_I_MSK 0xcfffffff
+#define CBR_RG_SX_MOD_ERR_DELAY_SFT 28
+#define CBR_RG_SX_MOD_ERR_DELAY_HI 29
+#define CBR_RG_SX_MOD_ERR_DELAY_SZ 2
+#define CBR_RG_SX_MODDB_MSK 0x40000000
+#define CBR_RG_SX_MODDB_I_MSK 0xbfffffff
+#define CBR_RG_SX_MODDB_SFT 30
+#define CBR_RG_SX_MODDB_HI 30
+#define CBR_RG_SX_MODDB_SZ 1
+#define CBR_RG_SX_CV_CURVE_SEL_MSK 0x00000003
+#define CBR_RG_SX_CV_CURVE_SEL_I_MSK 0xfffffffc
+#define CBR_RG_SX_CV_CURVE_SEL_SFT 0
+#define CBR_RG_SX_CV_CURVE_SEL_HI 1
+#define CBR_RG_SX_CV_CURVE_SEL_SZ 2
+#define CBR_RG_SX_SEL_DELAY_MSK 0x0000007c
+#define CBR_RG_SX_SEL_DELAY_I_MSK 0xffffff83
+#define CBR_RG_SX_SEL_DELAY_SFT 2
+#define CBR_RG_SX_SEL_DELAY_HI 6
+#define CBR_RG_SX_SEL_DELAY_SZ 5
+#define CBR_RG_SX_REF_CYCLE_MSK 0x00000780
+#define CBR_RG_SX_REF_CYCLE_I_MSK 0xfffff87f
+#define CBR_RG_SX_REF_CYCLE_SFT 7
+#define CBR_RG_SX_REF_CYCLE_HI 10
+#define CBR_RG_SX_REF_CYCLE_SZ 4
+#define CBR_RG_SX_VCOBY16_MSK 0x00000800
+#define CBR_RG_SX_VCOBY16_I_MSK 0xfffff7ff
+#define CBR_RG_SX_VCOBY16_SFT 11
+#define CBR_RG_SX_VCOBY16_HI 11
+#define CBR_RG_SX_VCOBY16_SZ 1
+#define CBR_RG_SX_VCOBY32_MSK 0x00001000
+#define CBR_RG_SX_VCOBY32_I_MSK 0xffffefff
+#define CBR_RG_SX_VCOBY32_SFT 12
+#define CBR_RG_SX_VCOBY32_HI 12
+#define CBR_RG_SX_VCOBY32_SZ 1
+#define CBR_RG_SX_PH_MSK 0x00002000
+#define CBR_RG_SX_PH_I_MSK 0xffffdfff
+#define CBR_RG_SX_PH_SFT 13
+#define CBR_RG_SX_PH_HI 13
+#define CBR_RG_SX_PH_SZ 1
+#define CBR_RG_SX_PL_MSK 0x00004000
+#define CBR_RG_SX_PL_I_MSK 0xffffbfff
+#define CBR_RG_SX_PL_SFT 14
+#define CBR_RG_SX_PL_HI 14
+#define CBR_RG_SX_PL_SZ 1
+#define CBR_RG_SX_VT_MON_MODE_MSK 0x00000001
+#define CBR_RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
+#define CBR_RG_SX_VT_MON_MODE_SFT 0
+#define CBR_RG_SX_VT_MON_MODE_HI 0
+#define CBR_RG_SX_VT_MON_MODE_SZ 1
+#define CBR_RG_SX_VT_TH_HI_MSK 0x00000006
+#define CBR_RG_SX_VT_TH_HI_I_MSK 0xfffffff9
+#define CBR_RG_SX_VT_TH_HI_SFT 1
+#define CBR_RG_SX_VT_TH_HI_HI 2
+#define CBR_RG_SX_VT_TH_HI_SZ 2
+#define CBR_RG_SX_VT_TH_LO_MSK 0x00000018
+#define CBR_RG_SX_VT_TH_LO_I_MSK 0xffffffe7
+#define CBR_RG_SX_VT_TH_LO_SFT 3
+#define CBR_RG_SX_VT_TH_LO_HI 4
+#define CBR_RG_SX_VT_TH_LO_SZ 2
+#define CBR_RG_SX_VT_SET_MSK 0x00000020
+#define CBR_RG_SX_VT_SET_I_MSK 0xffffffdf
+#define CBR_RG_SX_VT_SET_SFT 5
+#define CBR_RG_SX_VT_SET_HI 5
+#define CBR_RG_SX_VT_SET_SZ 1
+#define CBR_RG_SX_VT_MON_TMR_MSK 0x00007fc0
+#define CBR_RG_SX_VT_MON_TMR_I_MSK 0xffff803f
+#define CBR_RG_SX_VT_MON_TMR_SFT 6
+#define CBR_RG_SX_VT_MON_TMR_HI 14
+#define CBR_RG_SX_VT_MON_TMR_SZ 9
+#define CBR_RG_IDEAL_CYCLE_MSK 0x0fff8000
+#define CBR_RG_IDEAL_CYCLE_I_MSK 0xf0007fff
+#define CBR_RG_IDEAL_CYCLE_SFT 15
+#define CBR_RG_IDEAL_CYCLE_HI 27
+#define CBR_RG_IDEAL_CYCLE_SZ 13
+#define CBR_RG_EN_DP_VT_MON_MSK 0x00000001
+#define CBR_RG_EN_DP_VT_MON_I_MSK 0xfffffffe
+#define CBR_RG_EN_DP_VT_MON_SFT 0
+#define CBR_RG_EN_DP_VT_MON_HI 0
+#define CBR_RG_EN_DP_VT_MON_SZ 1
+#define CBR_RG_DP_VT_TH_HI_MSK 0x00000006
+#define CBR_RG_DP_VT_TH_HI_I_MSK 0xfffffff9
+#define CBR_RG_DP_VT_TH_HI_SFT 1
+#define CBR_RG_DP_VT_TH_HI_HI 2
+#define CBR_RG_DP_VT_TH_HI_SZ 2
+#define CBR_RG_DP_VT_TH_LO_MSK 0x00000018
+#define CBR_RG_DP_VT_TH_LO_I_MSK 0xffffffe7
+#define CBR_RG_DP_VT_TH_LO_SFT 3
+#define CBR_RG_DP_VT_TH_LO_HI 4
+#define CBR_RG_DP_VT_TH_LO_SZ 2
+#define CBR_RG_DP_VT_MON_TMR_MSK 0x00003fe0
+#define CBR_RG_DP_VT_MON_TMR_I_MSK 0xffffc01f
+#define CBR_RG_DP_VT_MON_TMR_SFT 5
+#define CBR_RG_DP_VT_MON_TMR_HI 13
+#define CBR_RG_DP_VT_MON_TMR_SZ 9
+#define CBR_RG_DP_CK320BY2_MSK 0x00004000
+#define CBR_RG_DP_CK320BY2_I_MSK 0xffffbfff
+#define CBR_RG_DP_CK320BY2_SFT 14
+#define CBR_RG_DP_CK320BY2_HI 14
+#define CBR_RG_DP_CK320BY2_SZ 1
+#define CBR_RG_SX_DELCTRL_MSK 0x001f8000
+#define CBR_RG_SX_DELCTRL_I_MSK 0xffe07fff
+#define CBR_RG_SX_DELCTRL_SFT 15
+#define CBR_RG_SX_DELCTRL_HI 20
+#define CBR_RG_SX_DELCTRL_SZ 6
+#define CBR_RG_DP_OD_TEST_MSK 0x00200000
+#define CBR_RG_DP_OD_TEST_I_MSK 0xffdfffff
+#define CBR_RG_DP_OD_TEST_SFT 21
+#define CBR_RG_DP_OD_TEST_HI 21
+#define CBR_RG_DP_OD_TEST_SZ 1
+#define CBR_RG_DP_BBPLL_BP_MSK 0x00000001
+#define CBR_RG_DP_BBPLL_BP_I_MSK 0xfffffffe
+#define CBR_RG_DP_BBPLL_BP_SFT 0
+#define CBR_RG_DP_BBPLL_BP_HI 0
+#define CBR_RG_DP_BBPLL_BP_SZ 1
+#define CBR_RG_DP_BBPLL_ICP_MSK 0x00000006
+#define CBR_RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
+#define CBR_RG_DP_BBPLL_ICP_SFT 1
+#define CBR_RG_DP_BBPLL_ICP_HI 2
+#define CBR_RG_DP_BBPLL_ICP_SZ 2
+#define CBR_RG_DP_BBPLL_IDUAL_MSK 0x00000018
+#define CBR_RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
+#define CBR_RG_DP_BBPLL_IDUAL_SFT 3
+#define CBR_RG_DP_BBPLL_IDUAL_HI 4
+#define CBR_RG_DP_BBPLL_IDUAL_SZ 2
+#define CBR_RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
+#define CBR_RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
+#define CBR_RG_DP_BBPLL_OD_TEST_SFT 5
+#define CBR_RG_DP_BBPLL_OD_TEST_HI 8
+#define CBR_RG_DP_BBPLL_OD_TEST_SZ 4
+#define CBR_RG_DP_BBPLL_PD_MSK 0x00000200
+#define CBR_RG_DP_BBPLL_PD_I_MSK 0xfffffdff
+#define CBR_RG_DP_BBPLL_PD_SFT 9
+#define CBR_RG_DP_BBPLL_PD_HI 9
+#define CBR_RG_DP_BBPLL_PD_SZ 1
+#define CBR_RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
+#define CBR_RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
+#define CBR_RG_DP_BBPLL_TESTSEL_SFT 10
+#define CBR_RG_DP_BBPLL_TESTSEL_HI 12
+#define CBR_RG_DP_BBPLL_TESTSEL_SZ 3
+#define CBR_RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
+#define CBR_RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
+#define CBR_RG_DP_BBPLL_PFD_DLY_SFT 13
+#define CBR_RG_DP_BBPLL_PFD_DLY_HI 14
+#define CBR_RG_DP_BBPLL_PFD_DLY_SZ 2
+#define CBR_RG_DP_RP_MSK 0x00038000
+#define CBR_RG_DP_RP_I_MSK 0xfffc7fff
+#define CBR_RG_DP_RP_SFT 15
+#define CBR_RG_DP_RP_HI 17
+#define CBR_RG_DP_RP_SZ 3
+#define CBR_RG_DP_RHP_MSK 0x000c0000
+#define CBR_RG_DP_RHP_I_MSK 0xfff3ffff
+#define CBR_RG_DP_RHP_SFT 18
+#define CBR_RG_DP_RHP_HI 19
+#define CBR_RG_DP_RHP_SZ 2
+#define CBR_RG_DP_DR3_MSK 0x00700000
+#define CBR_RG_DP_DR3_I_MSK 0xff8fffff
+#define CBR_RG_DP_DR3_SFT 20
+#define CBR_RG_DP_DR3_HI 22
+#define CBR_RG_DP_DR3_SZ 3
+#define CBR_RG_DP_DCP_MSK 0x07800000
+#define CBR_RG_DP_DCP_I_MSK 0xf87fffff
+#define CBR_RG_DP_DCP_SFT 23
+#define CBR_RG_DP_DCP_HI 26
+#define CBR_RG_DP_DCP_SZ 4
+#define CBR_RG_DP_DCS_MSK 0x78000000
+#define CBR_RG_DP_DCS_I_MSK 0x87ffffff
+#define CBR_RG_DP_DCS_SFT 27
+#define CBR_RG_DP_DCS_HI 30
+#define CBR_RG_DP_DCS_SZ 4
+#define CBR_RG_DP_FBDIV_MSK 0x00000fff
+#define CBR_RG_DP_FBDIV_I_MSK 0xfffff000
+#define CBR_RG_DP_FBDIV_SFT 0
+#define CBR_RG_DP_FBDIV_HI 11
+#define CBR_RG_DP_FBDIV_SZ 12
+#define CBR_RG_DP_FODIV_MSK 0x003ff000
+#define CBR_RG_DP_FODIV_I_MSK 0xffc00fff
+#define CBR_RG_DP_FODIV_SFT 12
+#define CBR_RG_DP_FODIV_HI 21
+#define CBR_RG_DP_FODIV_SZ 10
+#define CBR_RG_DP_REFDIV_MSK 0xffc00000
+#define CBR_RG_DP_REFDIV_I_MSK 0x003fffff
+#define CBR_RG_DP_REFDIV_SFT 22
+#define CBR_RG_DP_REFDIV_HI 31
+#define CBR_RG_DP_REFDIV_SZ 10
+#define CBR_RG_IDACAI_PGAG15_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG15_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG15_SFT 0
+#define CBR_RG_IDACAI_PGAG15_HI 5
+#define CBR_RG_IDACAI_PGAG15_SZ 6
+#define CBR_RG_IDACAQ_PGAG15_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG15_SFT 6
+#define CBR_RG_IDACAQ_PGAG15_HI 11
+#define CBR_RG_IDACAQ_PGAG15_SZ 6
+#define CBR_RG_IDACAI_PGAG14_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG14_SFT 12
+#define CBR_RG_IDACAI_PGAG14_HI 17
+#define CBR_RG_IDACAI_PGAG14_SZ 6
+#define CBR_RG_IDACAQ_PGAG14_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG14_SFT 18
+#define CBR_RG_IDACAQ_PGAG14_HI 23
+#define CBR_RG_IDACAQ_PGAG14_SZ 6
+#define CBR_RG_IDACAI_PGAG13_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG13_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG13_SFT 0
+#define CBR_RG_IDACAI_PGAG13_HI 5
+#define CBR_RG_IDACAI_PGAG13_SZ 6
+#define CBR_RG_IDACAQ_PGAG13_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG13_SFT 6
+#define CBR_RG_IDACAQ_PGAG13_HI 11
+#define CBR_RG_IDACAQ_PGAG13_SZ 6
+#define CBR_RG_IDACAI_PGAG12_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG12_SFT 12
+#define CBR_RG_IDACAI_PGAG12_HI 17
+#define CBR_RG_IDACAI_PGAG12_SZ 6
+#define CBR_RG_IDACAQ_PGAG12_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG12_SFT 18
+#define CBR_RG_IDACAQ_PGAG12_HI 23
+#define CBR_RG_IDACAQ_PGAG12_SZ 6
+#define CBR_RG_IDACAI_PGAG11_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG11_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG11_SFT 0
+#define CBR_RG_IDACAI_PGAG11_HI 5
+#define CBR_RG_IDACAI_PGAG11_SZ 6
+#define CBR_RG_IDACAQ_PGAG11_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG11_SFT 6
+#define CBR_RG_IDACAQ_PGAG11_HI 11
+#define CBR_RG_IDACAQ_PGAG11_SZ 6
+#define CBR_RG_IDACAI_PGAG10_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG10_SFT 12
+#define CBR_RG_IDACAI_PGAG10_HI 17
+#define CBR_RG_IDACAI_PGAG10_SZ 6
+#define CBR_RG_IDACAQ_PGAG10_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG10_SFT 18
+#define CBR_RG_IDACAQ_PGAG10_HI 23
+#define CBR_RG_IDACAQ_PGAG10_SZ 6
+#define CBR_RG_IDACAI_PGAG9_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG9_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG9_SFT 0
+#define CBR_RG_IDACAI_PGAG9_HI 5
+#define CBR_RG_IDACAI_PGAG9_SZ 6
+#define CBR_RG_IDACAQ_PGAG9_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG9_SFT 6
+#define CBR_RG_IDACAQ_PGAG9_HI 11
+#define CBR_RG_IDACAQ_PGAG9_SZ 6
+#define CBR_RG_IDACAI_PGAG8_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG8_SFT 12
+#define CBR_RG_IDACAI_PGAG8_HI 17
+#define CBR_RG_IDACAI_PGAG8_SZ 6
+#define CBR_RG_IDACAQ_PGAG8_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG8_SFT 18
+#define CBR_RG_IDACAQ_PGAG8_HI 23
+#define CBR_RG_IDACAQ_PGAG8_SZ 6
+#define CBR_RG_IDACAI_PGAG7_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG7_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG7_SFT 0
+#define CBR_RG_IDACAI_PGAG7_HI 5
+#define CBR_RG_IDACAI_PGAG7_SZ 6
+#define CBR_RG_IDACAQ_PGAG7_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG7_SFT 6
+#define CBR_RG_IDACAQ_PGAG7_HI 11
+#define CBR_RG_IDACAQ_PGAG7_SZ 6
+#define CBR_RG_IDACAI_PGAG6_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG6_SFT 12
+#define CBR_RG_IDACAI_PGAG6_HI 17
+#define CBR_RG_IDACAI_PGAG6_SZ 6
+#define CBR_RG_IDACAQ_PGAG6_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG6_SFT 18
+#define CBR_RG_IDACAQ_PGAG6_HI 23
+#define CBR_RG_IDACAQ_PGAG6_SZ 6
+#define CBR_RG_IDACAI_PGAG5_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG5_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG5_SFT 0
+#define CBR_RG_IDACAI_PGAG5_HI 5
+#define CBR_RG_IDACAI_PGAG5_SZ 6
+#define CBR_RG_IDACAQ_PGAG5_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG5_SFT 6
+#define CBR_RG_IDACAQ_PGAG5_HI 11
+#define CBR_RG_IDACAQ_PGAG5_SZ 6
+#define CBR_RG_IDACAI_PGAG4_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG4_SFT 12
+#define CBR_RG_IDACAI_PGAG4_HI 17
+#define CBR_RG_IDACAI_PGAG4_SZ 6
+#define CBR_RG_IDACAQ_PGAG4_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG4_SFT 18
+#define CBR_RG_IDACAQ_PGAG4_HI 23
+#define CBR_RG_IDACAQ_PGAG4_SZ 6
+#define CBR_RG_IDACAI_PGAG3_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG3_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG3_SFT 0
+#define CBR_RG_IDACAI_PGAG3_HI 5
+#define CBR_RG_IDACAI_PGAG3_SZ 6
+#define CBR_RG_IDACAQ_PGAG3_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG3_SFT 6
+#define CBR_RG_IDACAQ_PGAG3_HI 11
+#define CBR_RG_IDACAQ_PGAG3_SZ 6
+#define CBR_RG_IDACAI_PGAG2_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG2_SFT 12
+#define CBR_RG_IDACAI_PGAG2_HI 17
+#define CBR_RG_IDACAI_PGAG2_SZ 6
+#define CBR_RG_IDACAQ_PGAG2_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG2_SFT 18
+#define CBR_RG_IDACAQ_PGAG2_HI 23
+#define CBR_RG_IDACAQ_PGAG2_SZ 6
+#define CBR_RG_IDACAI_PGAG1_MSK 0x0000003f
+#define CBR_RG_IDACAI_PGAG1_I_MSK 0xffffffc0
+#define CBR_RG_IDACAI_PGAG1_SFT 0
+#define CBR_RG_IDACAI_PGAG1_HI 5
+#define CBR_RG_IDACAI_PGAG1_SZ 6
+#define CBR_RG_IDACAQ_PGAG1_MSK 0x00000fc0
+#define CBR_RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
+#define CBR_RG_IDACAQ_PGAG1_SFT 6
+#define CBR_RG_IDACAQ_PGAG1_HI 11
+#define CBR_RG_IDACAQ_PGAG1_SZ 6
+#define CBR_RG_IDACAI_PGAG0_MSK 0x0003f000
+#define CBR_RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
+#define CBR_RG_IDACAI_PGAG0_SFT 12
+#define CBR_RG_IDACAI_PGAG0_HI 17
+#define CBR_RG_IDACAI_PGAG0_SZ 6
+#define CBR_RG_IDACAQ_PGAG0_MSK 0x00fc0000
+#define CBR_RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
+#define CBR_RG_IDACAQ_PGAG0_SFT 18
+#define CBR_RG_IDACAQ_PGAG0_HI 23
+#define CBR_RG_IDACAQ_PGAG0_SZ 6
+#define CBR_RG_EN_RCAL_MSK 0x00000001
+#define CBR_RG_EN_RCAL_I_MSK 0xfffffffe
+#define CBR_RG_EN_RCAL_SFT 0
+#define CBR_RG_EN_RCAL_HI 0
+#define CBR_RG_EN_RCAL_SZ 1
+#define CBR_RG_RCAL_SPD_MSK 0x00000002
+#define CBR_RG_RCAL_SPD_I_MSK 0xfffffffd
+#define CBR_RG_RCAL_SPD_SFT 1
+#define CBR_RG_RCAL_SPD_HI 1
+#define CBR_RG_RCAL_SPD_SZ 1
+#define CBR_RG_RCAL_TMR_MSK 0x000001fc
+#define CBR_RG_RCAL_TMR_I_MSK 0xfffffe03
+#define CBR_RG_RCAL_TMR_SFT 2
+#define CBR_RG_RCAL_TMR_HI 8
+#define CBR_RG_RCAL_TMR_SZ 7
+#define CBR_RG_RCAL_CODE_CWR_MSK 0x00000200
+#define CBR_RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
+#define CBR_RG_RCAL_CODE_CWR_SFT 9
+#define CBR_RG_RCAL_CODE_CWR_HI 9
+#define CBR_RG_RCAL_CODE_CWR_SZ 1
+#define CBR_RG_RCAL_CODE_CWD_MSK 0x00007c00
+#define CBR_RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
+#define CBR_RG_RCAL_CODE_CWD_SFT 10
+#define CBR_RG_RCAL_CODE_CWD_HI 14
+#define CBR_RG_RCAL_CODE_CWD_SZ 5
+#define CBR_RG_SX_SUB_SEL_CWR_MSK 0x00000001
+#define CBR_RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
+#define CBR_RG_SX_SUB_SEL_CWR_SFT 0
+#define CBR_RG_SX_SUB_SEL_CWR_HI 0
+#define CBR_RG_SX_SUB_SEL_CWR_SZ 1
+#define CBR_RG_SX_SUB_SEL_CWD_MSK 0x000000fe
+#define CBR_RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
+#define CBR_RG_SX_SUB_SEL_CWD_SFT 1
+#define CBR_RG_SX_SUB_SEL_CWD_HI 7
+#define CBR_RG_SX_SUB_SEL_CWD_SZ 7
+#define CBR_RG_DP_BBPLL_BS_CWR_MSK 0x00000100
+#define CBR_RG_DP_BBPLL_BS_CWR_I_MSK 0xfffffeff
+#define CBR_RG_DP_BBPLL_BS_CWR_SFT 8
+#define CBR_RG_DP_BBPLL_BS_CWR_HI 8
+#define CBR_RG_DP_BBPLL_BS_CWR_SZ 1
+#define CBR_RG_DP_BBPLL_BS_CWD_MSK 0x00007e00
+#define CBR_RG_DP_BBPLL_BS_CWD_I_MSK 0xffff81ff
+#define CBR_RG_DP_BBPLL_BS_CWD_SFT 9
+#define CBR_RG_DP_BBPLL_BS_CWD_HI 14
+#define CBR_RG_DP_BBPLL_BS_CWD_SZ 6
+#define CBR_RCAL_RDY_MSK 0x00000001
+#define CBR_RCAL_RDY_I_MSK 0xfffffffe
+#define CBR_RCAL_RDY_SFT 0
+#define CBR_RCAL_RDY_HI 0
+#define CBR_RCAL_RDY_SZ 1
+#define CBR_DA_LCK_RDY_MSK 0x00000002
+#define CBR_DA_LCK_RDY_I_MSK 0xfffffffd
+#define CBR_DA_LCK_RDY_SFT 1
+#define CBR_DA_LCK_RDY_HI 1
+#define CBR_DA_LCK_RDY_SZ 1
+#define CBR_VT_MON_RDY_MSK 0x00000004
+#define CBR_VT_MON_RDY_I_MSK 0xfffffffb
+#define CBR_VT_MON_RDY_SFT 2
+#define CBR_VT_MON_RDY_HI 2
+#define CBR_VT_MON_RDY_SZ 1
+#define CBR_DP_VT_MON_RDY_MSK 0x00000008
+#define CBR_DP_VT_MON_RDY_I_MSK 0xfffffff7
+#define CBR_DP_VT_MON_RDY_SFT 3
+#define CBR_DP_VT_MON_RDY_HI 3
+#define CBR_DP_VT_MON_RDY_SZ 1
+#define CBR_CH_RDY_MSK 0x00000010
+#define CBR_CH_RDY_I_MSK 0xffffffef
+#define CBR_CH_RDY_SFT 4
+#define CBR_CH_RDY_HI 4
+#define CBR_CH_RDY_SZ 1
+#define CBR_DA_R_CODE_LUT_MSK 0x000007c0
+#define CBR_DA_R_CODE_LUT_I_MSK 0xfffff83f
+#define CBR_DA_R_CODE_LUT_SFT 6
+#define CBR_DA_R_CODE_LUT_HI 10
+#define CBR_DA_R_CODE_LUT_SZ 5
+#define CBR_AD_SX_VT_MON_Q_MSK 0x00001800
+#define CBR_AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
+#define CBR_AD_SX_VT_MON_Q_SFT 11
+#define CBR_AD_SX_VT_MON_Q_HI 12
+#define CBR_AD_SX_VT_MON_Q_SZ 2
+#define CBR_AD_DP_VT_MON_Q_MSK 0x00006000
+#define CBR_AD_DP_VT_MON_Q_I_MSK 0xffff9fff
+#define CBR_AD_DP_VT_MON_Q_SFT 13
+#define CBR_AD_DP_VT_MON_Q_HI 14
+#define CBR_AD_DP_VT_MON_Q_SZ 2
+#define CBR_DA_R_CAL_CODE_MSK 0x0000001f
+#define CBR_DA_R_CAL_CODE_I_MSK 0xffffffe0
+#define CBR_DA_R_CAL_CODE_SFT 0
+#define CBR_DA_R_CAL_CODE_HI 4
+#define CBR_DA_R_CAL_CODE_SZ 5
+#define CBR_DA_SX_SUB_SEL_MSK 0x00000fe0
+#define CBR_DA_SX_SUB_SEL_I_MSK 0xfffff01f
+#define CBR_DA_SX_SUB_SEL_SFT 5
+#define CBR_DA_SX_SUB_SEL_HI 11
+#define CBR_DA_SX_SUB_SEL_SZ 7
+#define CBR_DA_DP_BBPLL_BS_MSK 0x0003f000
+#define CBR_DA_DP_BBPLL_BS_I_MSK 0xfffc0fff
+#define CBR_DA_DP_BBPLL_BS_SFT 12
+#define CBR_DA_DP_BBPLL_BS_HI 17
+#define CBR_DA_DP_BBPLL_BS_SZ 6
+#define CBR_TX_EN_MSK 0x00000001
+#define CBR_TX_EN_I_MSK 0xfffffffe
+#define CBR_TX_EN_SFT 0
+#define CBR_TX_EN_HI 0
+#define CBR_TX_EN_SZ 1
+#define CBR_TX_CNT_RST_MSK 0x00000002
+#define CBR_TX_CNT_RST_I_MSK 0xfffffffd
+#define CBR_TX_CNT_RST_SFT 1
+#define CBR_TX_CNT_RST_HI 1
+#define CBR_TX_CNT_RST_SZ 1
+#define CBR_IFS_TIME_MSK 0x000000fc
+#define CBR_IFS_TIME_I_MSK 0xffffff03
+#define CBR_IFS_TIME_SFT 2
+#define CBR_IFS_TIME_HI 7
+#define CBR_IFS_TIME_SZ 6
+#define CBR_LENGTH_TARGET_MSK 0x000fff00
+#define CBR_LENGTH_TARGET_I_MSK 0xfff000ff
+#define CBR_LENGTH_TARGET_SFT 8
+#define CBR_LENGTH_TARGET_HI 19
+#define CBR_LENGTH_TARGET_SZ 12
+#define CBR_TX_CNT_TARGET_MSK 0xff000000
+#define CBR_TX_CNT_TARGET_I_MSK 0x00ffffff
+#define CBR_TX_CNT_TARGET_SFT 24
+#define CBR_TX_CNT_TARGET_HI 31
+#define CBR_TX_CNT_TARGET_SZ 8
+#define CBR_TC_CNT_TARGET_MSK 0x00ffffff
+#define CBR_TC_CNT_TARGET_I_MSK 0xff000000
+#define CBR_TC_CNT_TARGET_SFT 0
+#define CBR_TC_CNT_TARGET_HI 23
+#define CBR_TC_CNT_TARGET_SZ 24
+#define CBR_PLCP_PSDU_DATA_MEM_MSK 0x000000ff
+#define CBR_PLCP_PSDU_DATA_MEM_I_MSK 0xffffff00
+#define CBR_PLCP_PSDU_DATA_MEM_SFT 0
+#define CBR_PLCP_PSDU_DATA_MEM_HI 7
+#define CBR_PLCP_PSDU_DATA_MEM_SZ 8
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_MSK 0x00000100
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_I_MSK 0xfffffeff
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SFT 8
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_HI 8
+#define CBR_PLCP_PSDU_PREAMBLE_SHORT_SZ 1
+#define CBR_PLCP_BYTE_LENGTH_MSK 0x001ffe00
+#define CBR_PLCP_BYTE_LENGTH_I_MSK 0xffe001ff
+#define CBR_PLCP_BYTE_LENGTH_SFT 9
+#define CBR_PLCP_BYTE_LENGTH_HI 20
+#define CBR_PLCP_BYTE_LENGTH_SZ 12
+#define CBR_PLCP_PSDU_RATE_MSK 0x00600000
+#define CBR_PLCP_PSDU_RATE_I_MSK 0xff9fffff
+#define CBR_PLCP_PSDU_RATE_SFT 21
+#define CBR_PLCP_PSDU_RATE_HI 22
+#define CBR_PLCP_PSDU_RATE_SZ 2
+#define CBR_TAIL_TIME_MSK 0x1f800000
+#define CBR_TAIL_TIME_I_MSK 0xe07fffff
+#define CBR_TAIL_TIME_SFT 23
+#define CBR_TAIL_TIME_HI 28
+#define CBR_TAIL_TIME_SZ 6
+#define CBR_RG_O_PAD_PD_MSK 0x00000001
+#define CBR_RG_O_PAD_PD_I_MSK 0xfffffffe
+#define CBR_RG_O_PAD_PD_SFT 0
+#define CBR_RG_O_PAD_PD_HI 0
+#define CBR_RG_O_PAD_PD_SZ 1
+#define CBR_RG_I_PAD_PD_MSK 0x00000002
+#define CBR_RG_I_PAD_PD_I_MSK 0xfffffffd
+#define CBR_RG_I_PAD_PD_SFT 1
+#define CBR_RG_I_PAD_PD_HI 1
+#define CBR_RG_I_PAD_PD_SZ 1
+#define CBR_SEL_ADCKP_INV_MSK 0x00000004
+#define CBR_SEL_ADCKP_INV_I_MSK 0xfffffffb
+#define CBR_SEL_ADCKP_INV_SFT 2
+#define CBR_SEL_ADCKP_INV_HI 2
+#define CBR_SEL_ADCKP_INV_SZ 1
+#define CBR_RG_PAD_DS_MSK 0x00000008
+#define CBR_RG_PAD_DS_I_MSK 0xfffffff7
+#define CBR_RG_PAD_DS_SFT 3
+#define CBR_RG_PAD_DS_HI 3
+#define CBR_RG_PAD_DS_SZ 1
+#define CBR_SEL_ADCKP_MUX_MSK 0x00000010
+#define CBR_SEL_ADCKP_MUX_I_MSK 0xffffffef
+#define CBR_SEL_ADCKP_MUX_SFT 4
+#define CBR_SEL_ADCKP_MUX_HI 4
+#define CBR_SEL_ADCKP_MUX_SZ 1
+#define CBR_RG_PAD_DS_CLK_MSK 0x00000020
+#define CBR_RG_PAD_DS_CLK_I_MSK 0xffffffdf
+#define CBR_RG_PAD_DS_CLK_SFT 5
+#define CBR_RG_PAD_DS_CLK_HI 5
+#define CBR_RG_PAD_DS_CLK_SZ 1
+#define CBR_INTP_SEL_MSK 0x00000200
+#define CBR_INTP_SEL_I_MSK 0xfffffdff
+#define CBR_INTP_SEL_SFT 9
+#define CBR_INTP_SEL_HI 9
+#define CBR_INTP_SEL_SZ 1
+#define CBR_IQ_SWP_MSK 0x00000400
+#define CBR_IQ_SWP_I_MSK 0xfffffbff
+#define CBR_IQ_SWP_SFT 10
+#define CBR_IQ_SWP_HI 10
+#define CBR_IQ_SWP_SZ 1
+#define CBR_RG_EN_EXT_DA_MSK 0x00000800
+#define CBR_RG_EN_EXT_DA_I_MSK 0xfffff7ff
+#define CBR_RG_EN_EXT_DA_SFT 11
+#define CBR_RG_EN_EXT_DA_HI 11
+#define CBR_RG_EN_EXT_DA_SZ 1
+#define CBR_RG_DIS_DA_OFFSET_MSK 0x00001000
+#define CBR_RG_DIS_DA_OFFSET_I_MSK 0xffffefff
+#define CBR_RG_DIS_DA_OFFSET_SFT 12
+#define CBR_RG_DIS_DA_OFFSET_HI 12
+#define CBR_RG_DIS_DA_OFFSET_SZ 1
+#define CBR_DBG_SEL_MSK 0x000f0000
+#define CBR_DBG_SEL_I_MSK 0xfff0ffff
+#define CBR_DBG_SEL_SFT 16
+#define CBR_DBG_SEL_HI 19
+#define CBR_DBG_SEL_SZ 4
+#define CBR_DBG_EN_MSK 0x00100000
+#define CBR_DBG_EN_I_MSK 0xffefffff
+#define CBR_DBG_EN_SFT 20
+#define CBR_DBG_EN_HI 20
+#define CBR_DBG_EN_SZ 1
+#define CBR_RG_PKT_GEN_TX_CNT_MSK 0xffffffff
+#define CBR_RG_PKT_GEN_TX_CNT_I_MSK 0x00000000
+#define CBR_RG_PKT_GEN_TX_CNT_SFT 0
+#define CBR_RG_PKT_GEN_TX_CNT_HI 31
+#define CBR_RG_PKT_GEN_TX_CNT_SZ 32
+#define CBR_TP_SEL_MSK 0x0000001f
+#define CBR_TP_SEL_I_MSK 0xffffffe0
+#define CBR_TP_SEL_SFT 0
+#define CBR_TP_SEL_HI 4
+#define CBR_TP_SEL_SZ 5
+#define CBR_IDEAL_IQ_EN_MSK 0x00000020
+#define CBR_IDEAL_IQ_EN_I_MSK 0xffffffdf
+#define CBR_IDEAL_IQ_EN_SFT 5
+#define CBR_IDEAL_IQ_EN_HI 5
+#define CBR_IDEAL_IQ_EN_SZ 1
+#define CBR_DATA_OUT_SEL_MSK 0x000001c0
+#define CBR_DATA_OUT_SEL_I_MSK 0xfffffe3f
+#define CBR_DATA_OUT_SEL_SFT 6
+#define CBR_DATA_OUT_SEL_HI 8
+#define CBR_DATA_OUT_SEL_SZ 3
+#define CBR_TWO_TONE_EN_MSK 0x00000200
+#define CBR_TWO_TONE_EN_I_MSK 0xfffffdff
+#define CBR_TWO_TONE_EN_SFT 9
+#define CBR_TWO_TONE_EN_HI 9
+#define CBR_TWO_TONE_EN_SZ 1
+#define CBR_FREQ_SEL_MSK 0x00ff0000
+#define CBR_FREQ_SEL_I_MSK 0xff00ffff
+#define CBR_FREQ_SEL_SFT 16
+#define CBR_FREQ_SEL_HI 23
+#define CBR_FREQ_SEL_SZ 8
+#define CBR_IQ_SCALE_MSK 0xff000000
+#define CBR_IQ_SCALE_I_MSK 0x00ffffff
+#define CBR_IQ_SCALE_SFT 24
+#define CBR_IQ_SCALE_HI 31
+#define CBR_IQ_SCALE_SZ 8
+#define CPU_QUE_POP_MSK 0x00000001
+#define CPU_QUE_POP_I_MSK 0xfffffffe
+#define CPU_QUE_POP_SFT 0
+#define CPU_QUE_POP_HI 0
+#define CPU_QUE_POP_SZ 1
+#define CPU_INT_MSK 0x00000004
+#define CPU_INT_I_MSK 0xfffffffb
+#define CPU_INT_SFT 2
+#define CPU_INT_HI 2
+#define CPU_INT_SZ 1
+#define CPU_ID_TB0_MSK 0xffffffff
+#define CPU_ID_TB0_I_MSK 0x00000000
+#define CPU_ID_TB0_SFT 0
+#define CPU_ID_TB0_HI 31
+#define CPU_ID_TB0_SZ 32
+#define CPU_ID_TB1_MSK 0xffffffff
+#define CPU_ID_TB1_I_MSK 0x00000000
+#define CPU_ID_TB1_SFT 0
+#define CPU_ID_TB1_HI 31
+#define CPU_ID_TB1_SZ 32
+#define HW_PKTID_MSK 0x000007ff
+#define HW_PKTID_I_MSK 0xfffff800
+#define HW_PKTID_SFT 0
+#define HW_PKTID_HI 10
+#define HW_PKTID_SZ 11
+#define CH0_INT_ADDR_MSK 0xffffffff
+#define CH0_INT_ADDR_I_MSK 0x00000000
+#define CH0_INT_ADDR_SFT 0
+#define CH0_INT_ADDR_HI 31
+#define CH0_INT_ADDR_SZ 32
+#define PRI_HW_PKTID_MSK 0x000007ff
+#define PRI_HW_PKTID_I_MSK 0xfffff800
+#define PRI_HW_PKTID_SFT 0
+#define PRI_HW_PKTID_HI 10
+#define PRI_HW_PKTID_SZ 11
+#define CH0_FULL_MSK 0x00000001
+#define CH0_FULL_I_MSK 0xfffffffe
+#define CH0_FULL_SFT 0
+#define CH0_FULL_HI 0
+#define CH0_FULL_SZ 1
+#define FF0_EMPTY_MSK 0x00000002
+#define FF0_EMPTY_I_MSK 0xfffffffd
+#define FF0_EMPTY_SFT 1
+#define FF0_EMPTY_HI 1
+#define FF0_EMPTY_SZ 1
+#define RLS_BUSY_MSK 0x00000200
+#define RLS_BUSY_I_MSK 0xfffffdff
+#define RLS_BUSY_SFT 9
+#define RLS_BUSY_HI 9
+#define RLS_BUSY_SZ 1
+#define RLS_COUNT_CLR_MSK 0x00000400
+#define RLS_COUNT_CLR_I_MSK 0xfffffbff
+#define RLS_COUNT_CLR_SFT 10
+#define RLS_COUNT_CLR_HI 10
+#define RLS_COUNT_CLR_SZ 1
+#define RTN_COUNT_CLR_MSK 0x00000800
+#define RTN_COUNT_CLR_I_MSK 0xfffff7ff
+#define RTN_COUNT_CLR_SFT 11
+#define RTN_COUNT_CLR_HI 11
+#define RTN_COUNT_CLR_SZ 1
+#define RLS_COUNT_MSK 0x00ff0000
+#define RLS_COUNT_I_MSK 0xff00ffff
+#define RLS_COUNT_SFT 16
+#define RLS_COUNT_HI 23
+#define RLS_COUNT_SZ 8
+#define RTN_COUNT_MSK 0xff000000
+#define RTN_COUNT_I_MSK 0x00ffffff
+#define RTN_COUNT_SFT 24
+#define RTN_COUNT_HI 31
+#define RTN_COUNT_SZ 8
+#define FF0_CNT_MSK 0x0000001f
+#define FF0_CNT_I_MSK 0xffffffe0
+#define FF0_CNT_SFT 0
+#define FF0_CNT_HI 4
+#define FF0_CNT_SZ 5
+#define FF1_CNT_MSK 0x000001e0
+#define FF1_CNT_I_MSK 0xfffffe1f
+#define FF1_CNT_SFT 5
+#define FF1_CNT_HI 8
+#define FF1_CNT_SZ 4
+#define FF3_CNT_MSK 0x00003800
+#define FF3_CNT_I_MSK 0xffffc7ff
+#define FF3_CNT_SFT 11
+#define FF3_CNT_HI 13
+#define FF3_CNT_SZ 3
+#define FF5_CNT_MSK 0x000e0000
+#define FF5_CNT_I_MSK 0xfff1ffff
+#define FF5_CNT_SFT 17
+#define FF5_CNT_HI 19
+#define FF5_CNT_SZ 3
+#define FF6_CNT_MSK 0x00700000
+#define FF6_CNT_I_MSK 0xff8fffff
+#define FF6_CNT_SFT 20
+#define FF6_CNT_HI 22
+#define FF6_CNT_SZ 3
+#define FF7_CNT_MSK 0x03800000
+#define FF7_CNT_I_MSK 0xfc7fffff
+#define FF7_CNT_SFT 23
+#define FF7_CNT_HI 25
+#define FF7_CNT_SZ 3
+#define FF8_CNT_MSK 0x1c000000
+#define FF8_CNT_I_MSK 0xe3ffffff
+#define FF8_CNT_SFT 26
+#define FF8_CNT_HI 28
+#define FF8_CNT_SZ 3
+#define FF9_CNT_MSK 0xe0000000
+#define FF9_CNT_I_MSK 0x1fffffff
+#define FF9_CNT_SFT 29
+#define FF9_CNT_HI 31
+#define FF9_CNT_SZ 3
+#define FF10_CNT_MSK 0x00000007
+#define FF10_CNT_I_MSK 0xfffffff8
+#define FF10_CNT_SFT 0
+#define FF10_CNT_HI 2
+#define FF10_CNT_SZ 3
+#define FF11_CNT_MSK 0x00000038
+#define FF11_CNT_I_MSK 0xffffffc7
+#define FF11_CNT_SFT 3
+#define FF11_CNT_HI 5
+#define FF11_CNT_SZ 3
+#define FF12_CNT_MSK 0x000001c0
+#define FF12_CNT_I_MSK 0xfffffe3f
+#define FF12_CNT_SFT 6
+#define FF12_CNT_HI 8
+#define FF12_CNT_SZ 3
+#define FF13_CNT_MSK 0x00000600
+#define FF13_CNT_I_MSK 0xfffff9ff
+#define FF13_CNT_SFT 9
+#define FF13_CNT_HI 10
+#define FF13_CNT_SZ 2
+#define FF14_CNT_MSK 0x00001800
+#define FF14_CNT_I_MSK 0xffffe7ff
+#define FF14_CNT_SFT 11
+#define FF14_CNT_HI 12
+#define FF14_CNT_SZ 2
+#define FF15_CNT_MSK 0x00006000
+#define FF15_CNT_I_MSK 0xffff9fff
+#define FF15_CNT_SFT 13
+#define FF15_CNT_HI 14
+#define FF15_CNT_SZ 2
+#define FF4_CNT_MSK 0x000f8000
+#define FF4_CNT_I_MSK 0xfff07fff
+#define FF4_CNT_SFT 15
+#define FF4_CNT_HI 19
+#define FF4_CNT_SZ 5
+#define FF2_CNT_MSK 0x00700000
+#define FF2_CNT_I_MSK 0xff8fffff
+#define FF2_CNT_SFT 20
+#define FF2_CNT_HI 22
+#define FF2_CNT_SZ 3
+#define CH1_FULL_MSK 0x00000002
+#define CH1_FULL_I_MSK 0xfffffffd
+#define CH1_FULL_SFT 1
+#define CH1_FULL_HI 1
+#define CH1_FULL_SZ 1
+#define CH2_FULL_MSK 0x00000004
+#define CH2_FULL_I_MSK 0xfffffffb
+#define CH2_FULL_SFT 2
+#define CH2_FULL_HI 2
+#define CH2_FULL_SZ 1
+#define CH3_FULL_MSK 0x00000008
+#define CH3_FULL_I_MSK 0xfffffff7
+#define CH3_FULL_SFT 3
+#define CH3_FULL_HI 3
+#define CH3_FULL_SZ 1
+#define CH4_FULL_MSK 0x00000010
+#define CH4_FULL_I_MSK 0xffffffef
+#define CH4_FULL_SFT 4
+#define CH4_FULL_HI 4
+#define CH4_FULL_SZ 1
+#define CH5_FULL_MSK 0x00000020
+#define CH5_FULL_I_MSK 0xffffffdf
+#define CH5_FULL_SFT 5
+#define CH5_FULL_HI 5
+#define CH5_FULL_SZ 1
+#define CH6_FULL_MSK 0x00000040
+#define CH6_FULL_I_MSK 0xffffffbf
+#define CH6_FULL_SFT 6
+#define CH6_FULL_HI 6
+#define CH6_FULL_SZ 1
+#define CH7_FULL_MSK 0x00000080
+#define CH7_FULL_I_MSK 0xffffff7f
+#define CH7_FULL_SFT 7
+#define CH7_FULL_HI 7
+#define CH7_FULL_SZ 1
+#define CH8_FULL_MSK 0x00000100
+#define CH8_FULL_I_MSK 0xfffffeff
+#define CH8_FULL_SFT 8
+#define CH8_FULL_HI 8
+#define CH8_FULL_SZ 1
+#define CH9_FULL_MSK 0x00000200
+#define CH9_FULL_I_MSK 0xfffffdff
+#define CH9_FULL_SFT 9
+#define CH9_FULL_HI 9
+#define CH9_FULL_SZ 1
+#define CH10_FULL_MSK 0x00000400
+#define CH10_FULL_I_MSK 0xfffffbff
+#define CH10_FULL_SFT 10
+#define CH10_FULL_HI 10
+#define CH10_FULL_SZ 1
+#define CH11_FULL_MSK 0x00000800
+#define CH11_FULL_I_MSK 0xfffff7ff
+#define CH11_FULL_SFT 11
+#define CH11_FULL_HI 11
+#define CH11_FULL_SZ 1
+#define CH12_FULL_MSK 0x00001000
+#define CH12_FULL_I_MSK 0xffffefff
+#define CH12_FULL_SFT 12
+#define CH12_FULL_HI 12
+#define CH12_FULL_SZ 1
+#define CH13_FULL_MSK 0x00002000
+#define CH13_FULL_I_MSK 0xffffdfff
+#define CH13_FULL_SFT 13
+#define CH13_FULL_HI 13
+#define CH13_FULL_SZ 1
+#define CH14_FULL_MSK 0x00004000
+#define CH14_FULL_I_MSK 0xffffbfff
+#define CH14_FULL_SFT 14
+#define CH14_FULL_HI 14
+#define CH14_FULL_SZ 1
+#define CH15_FULL_MSK 0x00008000
+#define CH15_FULL_I_MSK 0xffff7fff
+#define CH15_FULL_SFT 15
+#define CH15_FULL_HI 15
+#define CH15_FULL_SZ 1
+#define HALT_CH0_MSK 0x00000001
+#define HALT_CH0_I_MSK 0xfffffffe
+#define HALT_CH0_SFT 0
+#define HALT_CH0_HI 0
+#define HALT_CH0_SZ 1
+#define HALT_CH1_MSK 0x00000002
+#define HALT_CH1_I_MSK 0xfffffffd
+#define HALT_CH1_SFT 1
+#define HALT_CH1_HI 1
+#define HALT_CH1_SZ 1
+#define HALT_CH2_MSK 0x00000004
+#define HALT_CH2_I_MSK 0xfffffffb
+#define HALT_CH2_SFT 2
+#define HALT_CH2_HI 2
+#define HALT_CH2_SZ 1
+#define HALT_CH3_MSK 0x00000008
+#define HALT_CH3_I_MSK 0xfffffff7
+#define HALT_CH3_SFT 3
+#define HALT_CH3_HI 3
+#define HALT_CH3_SZ 1
+#define HALT_CH4_MSK 0x00000010
+#define HALT_CH4_I_MSK 0xffffffef
+#define HALT_CH4_SFT 4
+#define HALT_CH4_HI 4
+#define HALT_CH4_SZ 1
+#define HALT_CH5_MSK 0x00000020
+#define HALT_CH5_I_MSK 0xffffffdf
+#define HALT_CH5_SFT 5
+#define HALT_CH5_HI 5
+#define HALT_CH5_SZ 1
+#define HALT_CH6_MSK 0x00000040
+#define HALT_CH6_I_MSK 0xffffffbf
+#define HALT_CH6_SFT 6
+#define HALT_CH6_HI 6
+#define HALT_CH6_SZ 1
+#define HALT_CH7_MSK 0x00000080
+#define HALT_CH7_I_MSK 0xffffff7f
+#define HALT_CH7_SFT 7
+#define HALT_CH7_HI 7
+#define HALT_CH7_SZ 1
+#define HALT_CH8_MSK 0x00000100
+#define HALT_CH8_I_MSK 0xfffffeff
+#define HALT_CH8_SFT 8
+#define HALT_CH8_HI 8
+#define HALT_CH8_SZ 1
+#define HALT_CH9_MSK 0x00000200
+#define HALT_CH9_I_MSK 0xfffffdff
+#define HALT_CH9_SFT 9
+#define HALT_CH9_HI 9
+#define HALT_CH9_SZ 1
+#define HALT_CH10_MSK 0x00000400
+#define HALT_CH10_I_MSK 0xfffffbff
+#define HALT_CH10_SFT 10
+#define HALT_CH10_HI 10
+#define HALT_CH10_SZ 1
+#define HALT_CH11_MSK 0x00000800
+#define HALT_CH11_I_MSK 0xfffff7ff
+#define HALT_CH11_SFT 11
+#define HALT_CH11_HI 11
+#define HALT_CH11_SZ 1
+#define HALT_CH12_MSK 0x00001000
+#define HALT_CH12_I_MSK 0xffffefff
+#define HALT_CH12_SFT 12
+#define HALT_CH12_HI 12
+#define HALT_CH12_SZ 1
+#define HALT_CH13_MSK 0x00002000
+#define HALT_CH13_I_MSK 0xffffdfff
+#define HALT_CH13_SFT 13
+#define HALT_CH13_HI 13
+#define HALT_CH13_SZ 1
+#define HALT_CH14_MSK 0x00004000
+#define HALT_CH14_I_MSK 0xffffbfff
+#define HALT_CH14_SFT 14
+#define HALT_CH14_HI 14
+#define HALT_CH14_SZ 1
+#define HALT_CH15_MSK 0x00008000
+#define HALT_CH15_I_MSK 0xffff7fff
+#define HALT_CH15_SFT 15
+#define HALT_CH15_HI 15
+#define HALT_CH15_SZ 1
+#define STOP_MBOX_MSK 0x00010000
+#define STOP_MBOX_I_MSK 0xfffeffff
+#define STOP_MBOX_SFT 16
+#define STOP_MBOX_HI 16
+#define STOP_MBOX_SZ 1
+#define MB_ERR_AUTO_HALT_EN_MSK 0x00100000
+#define MB_ERR_AUTO_HALT_EN_I_MSK 0xffefffff
+#define MB_ERR_AUTO_HALT_EN_SFT 20
+#define MB_ERR_AUTO_HALT_EN_HI 20
+#define MB_ERR_AUTO_HALT_EN_SZ 1
+#define MB_EXCEPT_CLR_MSK 0x00200000
+#define MB_EXCEPT_CLR_I_MSK 0xffdfffff
+#define MB_EXCEPT_CLR_SFT 21
+#define MB_EXCEPT_CLR_HI 21
+#define MB_EXCEPT_CLR_SZ 1
+#define MB_EXCEPT_CASE_MSK 0xff000000
+#define MB_EXCEPT_CASE_I_MSK 0x00ffffff
+#define MB_EXCEPT_CASE_SFT 24
+#define MB_EXCEPT_CASE_HI 31
+#define MB_EXCEPT_CASE_SZ 8
+#define MB_DBG_TIME_STEP_MSK 0x0000ffff
+#define MB_DBG_TIME_STEP_I_MSK 0xffff0000
+#define MB_DBG_TIME_STEP_SFT 0
+#define MB_DBG_TIME_STEP_HI 15
+#define MB_DBG_TIME_STEP_SZ 16
+#define DBG_TYPE_MSK 0x00030000
+#define DBG_TYPE_I_MSK 0xfffcffff
+#define DBG_TYPE_SFT 16
+#define DBG_TYPE_HI 17
+#define DBG_TYPE_SZ 2
+#define MB_DBG_CLR_MSK 0x00040000
+#define MB_DBG_CLR_I_MSK 0xfffbffff
+#define MB_DBG_CLR_SFT 18
+#define MB_DBG_CLR_HI 18
+#define MB_DBG_CLR_SZ 1
+#define DBG_ALC_LOG_EN_MSK 0x00080000
+#define DBG_ALC_LOG_EN_I_MSK 0xfff7ffff
+#define DBG_ALC_LOG_EN_SFT 19
+#define DBG_ALC_LOG_EN_HI 19
+#define DBG_ALC_LOG_EN_SZ 1
+#define MB_DBG_COUNTER_EN_MSK 0x01000000
+#define MB_DBG_COUNTER_EN_I_MSK 0xfeffffff
+#define MB_DBG_COUNTER_EN_SFT 24
+#define MB_DBG_COUNTER_EN_HI 24
+#define MB_DBG_COUNTER_EN_SZ 1
+#define MB_DBG_EN_MSK 0x80000000
+#define MB_DBG_EN_I_MSK 0x7fffffff
+#define MB_DBG_EN_SFT 31
+#define MB_DBG_EN_HI 31
+#define MB_DBG_EN_SZ 1
+#define MB_DBG_RECORD_CNT_MSK 0x0000ffff
+#define MB_DBG_RECORD_CNT_I_MSK 0xffff0000
+#define MB_DBG_RECORD_CNT_SFT 0
+#define MB_DBG_RECORD_CNT_HI 15
+#define MB_DBG_RECORD_CNT_SZ 16
+#define MB_DBG_LENGTH_MSK 0xffff0000
+#define MB_DBG_LENGTH_I_MSK 0x0000ffff
+#define MB_DBG_LENGTH_SFT 16
+#define MB_DBG_LENGTH_HI 31
+#define MB_DBG_LENGTH_SZ 16
+#define MB_DBG_CFG_ADDR_MSK 0xffffffff
+#define MB_DBG_CFG_ADDR_I_MSK 0x00000000
+#define MB_DBG_CFG_ADDR_SFT 0
+#define MB_DBG_CFG_ADDR_HI 31
+#define MB_DBG_CFG_ADDR_SZ 32
+#define DBG_HWID0_WR_EN_MSK 0x00000001
+#define DBG_HWID0_WR_EN_I_MSK 0xfffffffe
+#define DBG_HWID0_WR_EN_SFT 0
+#define DBG_HWID0_WR_EN_HI 0
+#define DBG_HWID0_WR_EN_SZ 1
+#define DBG_HWID1_WR_EN_MSK 0x00000002
+#define DBG_HWID1_WR_EN_I_MSK 0xfffffffd
+#define DBG_HWID1_WR_EN_SFT 1
+#define DBG_HWID1_WR_EN_HI 1
+#define DBG_HWID1_WR_EN_SZ 1
+#define DBG_HWID2_WR_EN_MSK 0x00000004
+#define DBG_HWID2_WR_EN_I_MSK 0xfffffffb
+#define DBG_HWID2_WR_EN_SFT 2
+#define DBG_HWID2_WR_EN_HI 2
+#define DBG_HWID2_WR_EN_SZ 1
+#define DBG_HWID3_WR_EN_MSK 0x00000008
+#define DBG_HWID3_WR_EN_I_MSK 0xfffffff7
+#define DBG_HWID3_WR_EN_SFT 3
+#define DBG_HWID3_WR_EN_HI 3
+#define DBG_HWID3_WR_EN_SZ 1
+#define DBG_HWID4_WR_EN_MSK 0x00000010
+#define DBG_HWID4_WR_EN_I_MSK 0xffffffef
+#define DBG_HWID4_WR_EN_SFT 4
+#define DBG_HWID4_WR_EN_HI 4
+#define DBG_HWID4_WR_EN_SZ 1
+#define DBG_HWID5_WR_EN_MSK 0x00000020
+#define DBG_HWID5_WR_EN_I_MSK 0xffffffdf
+#define DBG_HWID5_WR_EN_SFT 5
+#define DBG_HWID5_WR_EN_HI 5
+#define DBG_HWID5_WR_EN_SZ 1
+#define DBG_HWID6_WR_EN_MSK 0x00000040
+#define DBG_HWID6_WR_EN_I_MSK 0xffffffbf
+#define DBG_HWID6_WR_EN_SFT 6
+#define DBG_HWID6_WR_EN_HI 6
+#define DBG_HWID6_WR_EN_SZ 1
+#define DBG_HWID7_WR_EN_MSK 0x00000080
+#define DBG_HWID7_WR_EN_I_MSK 0xffffff7f
+#define DBG_HWID7_WR_EN_SFT 7
+#define DBG_HWID7_WR_EN_HI 7
+#define DBG_HWID7_WR_EN_SZ 1
+#define DBG_HWID8_WR_EN_MSK 0x00000100
+#define DBG_HWID8_WR_EN_I_MSK 0xfffffeff
+#define DBG_HWID8_WR_EN_SFT 8
+#define DBG_HWID8_WR_EN_HI 8
+#define DBG_HWID8_WR_EN_SZ 1
+#define DBG_HWID9_WR_EN_MSK 0x00000200
+#define DBG_HWID9_WR_EN_I_MSK 0xfffffdff
+#define DBG_HWID9_WR_EN_SFT 9
+#define DBG_HWID9_WR_EN_HI 9
+#define DBG_HWID9_WR_EN_SZ 1
+#define DBG_HWID10_WR_EN_MSK 0x00000400
+#define DBG_HWID10_WR_EN_I_MSK 0xfffffbff
+#define DBG_HWID10_WR_EN_SFT 10
+#define DBG_HWID10_WR_EN_HI 10
+#define DBG_HWID10_WR_EN_SZ 1
+#define DBG_HWID11_WR_EN_MSK 0x00000800
+#define DBG_HWID11_WR_EN_I_MSK 0xfffff7ff
+#define DBG_HWID11_WR_EN_SFT 11
+#define DBG_HWID11_WR_EN_HI 11
+#define DBG_HWID11_WR_EN_SZ 1
+#define DBG_HWID12_WR_EN_MSK 0x00001000
+#define DBG_HWID12_WR_EN_I_MSK 0xffffefff
+#define DBG_HWID12_WR_EN_SFT 12
+#define DBG_HWID12_WR_EN_HI 12
+#define DBG_HWID12_WR_EN_SZ 1
+#define DBG_HWID13_WR_EN_MSK 0x00002000
+#define DBG_HWID13_WR_EN_I_MSK 0xffffdfff
+#define DBG_HWID13_WR_EN_SFT 13
+#define DBG_HWID13_WR_EN_HI 13
+#define DBG_HWID13_WR_EN_SZ 1
+#define DBG_HWID14_WR_EN_MSK 0x00004000
+#define DBG_HWID14_WR_EN_I_MSK 0xffffbfff
+#define DBG_HWID14_WR_EN_SFT 14
+#define DBG_HWID14_WR_EN_HI 14
+#define DBG_HWID14_WR_EN_SZ 1
+#define DBG_HWID15_WR_EN_MSK 0x00008000
+#define DBG_HWID15_WR_EN_I_MSK 0xffff7fff
+#define DBG_HWID15_WR_EN_SFT 15
+#define DBG_HWID15_WR_EN_HI 15
+#define DBG_HWID15_WR_EN_SZ 1
+#define DBG_HWID0_RD_EN_MSK 0x00010000
+#define DBG_HWID0_RD_EN_I_MSK 0xfffeffff
+#define DBG_HWID0_RD_EN_SFT 16
+#define DBG_HWID0_RD_EN_HI 16
+#define DBG_HWID0_RD_EN_SZ 1
+#define DBG_HWID1_RD_EN_MSK 0x00020000
+#define DBG_HWID1_RD_EN_I_MSK 0xfffdffff
+#define DBG_HWID1_RD_EN_SFT 17
+#define DBG_HWID1_RD_EN_HI 17
+#define DBG_HWID1_RD_EN_SZ 1
+#define DBG_HWID2_RD_EN_MSK 0x00040000
+#define DBG_HWID2_RD_EN_I_MSK 0xfffbffff
+#define DBG_HWID2_RD_EN_SFT 18
+#define DBG_HWID2_RD_EN_HI 18
+#define DBG_HWID2_RD_EN_SZ 1
+#define DBG_HWID3_RD_EN_MSK 0x00080000
+#define DBG_HWID3_RD_EN_I_MSK 0xfff7ffff
+#define DBG_HWID3_RD_EN_SFT 19
+#define DBG_HWID3_RD_EN_HI 19
+#define DBG_HWID3_RD_EN_SZ 1
+#define DBG_HWID4_RD_EN_MSK 0x00100000
+#define DBG_HWID4_RD_EN_I_MSK 0xffefffff
+#define DBG_HWID4_RD_EN_SFT 20
+#define DBG_HWID4_RD_EN_HI 20
+#define DBG_HWID4_RD_EN_SZ 1
+#define DBG_HWID5_RD_EN_MSK 0x00200000
+#define DBG_HWID5_RD_EN_I_MSK 0xffdfffff
+#define DBG_HWID5_RD_EN_SFT 21
+#define DBG_HWID5_RD_EN_HI 21
+#define DBG_HWID5_RD_EN_SZ 1
+#define DBG_HWID6_RD_EN_MSK 0x00400000
+#define DBG_HWID6_RD_EN_I_MSK 0xffbfffff
+#define DBG_HWID6_RD_EN_SFT 22
+#define DBG_HWID6_RD_EN_HI 22
+#define DBG_HWID6_RD_EN_SZ 1
+#define DBG_HWID7_RD_EN_MSK 0x00800000
+#define DBG_HWID7_RD_EN_I_MSK 0xff7fffff
+#define DBG_HWID7_RD_EN_SFT 23
+#define DBG_HWID7_RD_EN_HI 23
+#define DBG_HWID7_RD_EN_SZ 1
+#define DBG_HWID8_RD_EN_MSK 0x01000000
+#define DBG_HWID8_RD_EN_I_MSK 0xfeffffff
+#define DBG_HWID8_RD_EN_SFT 24
+#define DBG_HWID8_RD_EN_HI 24
+#define DBG_HWID8_RD_EN_SZ 1
+#define DBG_HWID9_RD_EN_MSK 0x02000000
+#define DBG_HWID9_RD_EN_I_MSK 0xfdffffff
+#define DBG_HWID9_RD_EN_SFT 25
+#define DBG_HWID9_RD_EN_HI 25
+#define DBG_HWID9_RD_EN_SZ 1
+#define DBG_HWID10_RD_EN_MSK 0x04000000
+#define DBG_HWID10_RD_EN_I_MSK 0xfbffffff
+#define DBG_HWID10_RD_EN_SFT 26
+#define DBG_HWID10_RD_EN_HI 26
+#define DBG_HWID10_RD_EN_SZ 1
+#define DBG_HWID11_RD_EN_MSK 0x08000000
+#define DBG_HWID11_RD_EN_I_MSK 0xf7ffffff
+#define DBG_HWID11_RD_EN_SFT 27
+#define DBG_HWID11_RD_EN_HI 27
+#define DBG_HWID11_RD_EN_SZ 1
+#define DBG_HWID12_RD_EN_MSK 0x10000000
+#define DBG_HWID12_RD_EN_I_MSK 0xefffffff
+#define DBG_HWID12_RD_EN_SFT 28
+#define DBG_HWID12_RD_EN_HI 28
+#define DBG_HWID12_RD_EN_SZ 1
+#define DBG_HWID13_RD_EN_MSK 0x20000000
+#define DBG_HWID13_RD_EN_I_MSK 0xdfffffff
+#define DBG_HWID13_RD_EN_SFT 29
+#define DBG_HWID13_RD_EN_HI 29
+#define DBG_HWID13_RD_EN_SZ 1
+#define DBG_HWID14_RD_EN_MSK 0x40000000
+#define DBG_HWID14_RD_EN_I_MSK 0xbfffffff
+#define DBG_HWID14_RD_EN_SFT 30
+#define DBG_HWID14_RD_EN_HI 30
+#define DBG_HWID14_RD_EN_SZ 1
+#define DBG_HWID15_RD_EN_MSK 0x80000000
+#define DBG_HWID15_RD_EN_I_MSK 0x7fffffff
+#define DBG_HWID15_RD_EN_SFT 31
+#define DBG_HWID15_RD_EN_HI 31
+#define DBG_HWID15_RD_EN_SZ 1
+#define MB_OUT_QUEUE_EN_MSK 0x00000002
+#define MB_OUT_QUEUE_EN_I_MSK 0xfffffffd
+#define MB_OUT_QUEUE_EN_SFT 1
+#define MB_OUT_QUEUE_EN_HI 1
+#define MB_OUT_QUEUE_EN_SZ 1
+#define CH0_QUEUE_FLUSH_MSK 0x00000001
+#define CH0_QUEUE_FLUSH_I_MSK 0xfffffffe
+#define CH0_QUEUE_FLUSH_SFT 0
+#define CH0_QUEUE_FLUSH_HI 0
+#define CH0_QUEUE_FLUSH_SZ 1
+#define CH1_QUEUE_FLUSH_MSK 0x00000002
+#define CH1_QUEUE_FLUSH_I_MSK 0xfffffffd
+#define CH1_QUEUE_FLUSH_SFT 1
+#define CH1_QUEUE_FLUSH_HI 1
+#define CH1_QUEUE_FLUSH_SZ 1
+#define CH2_QUEUE_FLUSH_MSK 0x00000004
+#define CH2_QUEUE_FLUSH_I_MSK 0xfffffffb
+#define CH2_QUEUE_FLUSH_SFT 2
+#define CH2_QUEUE_FLUSH_HI 2
+#define CH2_QUEUE_FLUSH_SZ 1
+#define CH3_QUEUE_FLUSH_MSK 0x00000008
+#define CH3_QUEUE_FLUSH_I_MSK 0xfffffff7
+#define CH3_QUEUE_FLUSH_SFT 3
+#define CH3_QUEUE_FLUSH_HI 3
+#define CH3_QUEUE_FLUSH_SZ 1
+#define CH4_QUEUE_FLUSH_MSK 0x00000010
+#define CH4_QUEUE_FLUSH_I_MSK 0xffffffef
+#define CH4_QUEUE_FLUSH_SFT 4
+#define CH4_QUEUE_FLUSH_HI 4
+#define CH4_QUEUE_FLUSH_SZ 1
+#define CH5_QUEUE_FLUSH_MSK 0x00000020
+#define CH5_QUEUE_FLUSH_I_MSK 0xffffffdf
+#define CH5_QUEUE_FLUSH_SFT 5
+#define CH5_QUEUE_FLUSH_HI 5
+#define CH5_QUEUE_FLUSH_SZ 1
+#define CH6_QUEUE_FLUSH_MSK 0x00000040
+#define CH6_QUEUE_FLUSH_I_MSK 0xffffffbf
+#define CH6_QUEUE_FLUSH_SFT 6
+#define CH6_QUEUE_FLUSH_HI 6
+#define CH6_QUEUE_FLUSH_SZ 1
+#define CH7_QUEUE_FLUSH_MSK 0x00000080
+#define CH7_QUEUE_FLUSH_I_MSK 0xffffff7f
+#define CH7_QUEUE_FLUSH_SFT 7
+#define CH7_QUEUE_FLUSH_HI 7
+#define CH7_QUEUE_FLUSH_SZ 1
+#define CH8_QUEUE_FLUSH_MSK 0x00000100
+#define CH8_QUEUE_FLUSH_I_MSK 0xfffffeff
+#define CH8_QUEUE_FLUSH_SFT 8
+#define CH8_QUEUE_FLUSH_HI 8
+#define CH8_QUEUE_FLUSH_SZ 1
+#define CH9_QUEUE_FLUSH_MSK 0x00000200
+#define CH9_QUEUE_FLUSH_I_MSK 0xfffffdff
+#define CH9_QUEUE_FLUSH_SFT 9
+#define CH9_QUEUE_FLUSH_HI 9
+#define CH9_QUEUE_FLUSH_SZ 1
+#define CH10_QUEUE_FLUSH_MSK 0x00000400
+#define CH10_QUEUE_FLUSH_I_MSK 0xfffffbff
+#define CH10_QUEUE_FLUSH_SFT 10
+#define CH10_QUEUE_FLUSH_HI 10
+#define CH10_QUEUE_FLUSH_SZ 1
+#define CH11_QUEUE_FLUSH_MSK 0x00000800
+#define CH11_QUEUE_FLUSH_I_MSK 0xfffff7ff
+#define CH11_QUEUE_FLUSH_SFT 11
+#define CH11_QUEUE_FLUSH_HI 11
+#define CH11_QUEUE_FLUSH_SZ 1
+#define CH12_QUEUE_FLUSH_MSK 0x00001000
+#define CH12_QUEUE_FLUSH_I_MSK 0xffffefff
+#define CH12_QUEUE_FLUSH_SFT 12
+#define CH12_QUEUE_FLUSH_HI 12
+#define CH12_QUEUE_FLUSH_SZ 1
+#define CH13_QUEUE_FLUSH_MSK 0x00002000
+#define CH13_QUEUE_FLUSH_I_MSK 0xffffdfff
+#define CH13_QUEUE_FLUSH_SFT 13
+#define CH13_QUEUE_FLUSH_HI 13
+#define CH13_QUEUE_FLUSH_SZ 1
+#define CH14_QUEUE_FLUSH_MSK 0x00004000
+#define CH14_QUEUE_FLUSH_I_MSK 0xffffbfff
+#define CH14_QUEUE_FLUSH_SFT 14
+#define CH14_QUEUE_FLUSH_HI 14
+#define CH14_QUEUE_FLUSH_SZ 1
+#define CH15_QUEUE_FLUSH_MSK 0x00008000
+#define CH15_QUEUE_FLUSH_I_MSK 0xffff7fff
+#define CH15_QUEUE_FLUSH_SFT 15
+#define CH15_QUEUE_FLUSH_HI 15
+#define CH15_QUEUE_FLUSH_SZ 1
+#define FFO0_CNT_MSK 0x0000001f
+#define FFO0_CNT_I_MSK 0xffffffe0
+#define FFO0_CNT_SFT 0
+#define FFO0_CNT_HI 4
+#define FFO0_CNT_SZ 5
+#define FFO1_CNT_MSK 0x000003e0
+#define FFO1_CNT_I_MSK 0xfffffc1f
+#define FFO1_CNT_SFT 5
+#define FFO1_CNT_HI 9
+#define FFO1_CNT_SZ 5
+#define FFO2_CNT_MSK 0x00000c00
+#define FFO2_CNT_I_MSK 0xfffff3ff
+#define FFO2_CNT_SFT 10
+#define FFO2_CNT_HI 11
+#define FFO2_CNT_SZ 2
+#define FFO3_CNT_MSK 0x000f8000
+#define FFO3_CNT_I_MSK 0xfff07fff
+#define FFO3_CNT_SFT 15
+#define FFO3_CNT_HI 19
+#define FFO3_CNT_SZ 5
+#define FFO4_CNT_MSK 0x00300000
+#define FFO4_CNT_I_MSK 0xffcfffff
+#define FFO4_CNT_SFT 20
+#define FFO4_CNT_HI 21
+#define FFO4_CNT_SZ 2
+#define FFO5_CNT_MSK 0x0e000000
+#define FFO5_CNT_I_MSK 0xf1ffffff
+#define FFO5_CNT_SFT 25
+#define FFO5_CNT_HI 27
+#define FFO5_CNT_SZ 3
+#define FFO6_CNT_MSK 0x0000000f
+#define FFO6_CNT_I_MSK 0xfffffff0
+#define FFO6_CNT_SFT 0
+#define FFO6_CNT_HI 3
+#define FFO6_CNT_SZ 4
+#define FFO7_CNT_MSK 0x000003e0
+#define FFO7_CNT_I_MSK 0xfffffc1f
+#define FFO7_CNT_SFT 5
+#define FFO7_CNT_HI 9
+#define FFO7_CNT_SZ 5
+#define FFO8_CNT_MSK 0x00007c00
+#define FFO8_CNT_I_MSK 0xffff83ff
+#define FFO8_CNT_SFT 10
+#define FFO8_CNT_HI 14
+#define FFO8_CNT_SZ 5
+#define FFO9_CNT_MSK 0x000f8000
+#define FFO9_CNT_I_MSK 0xfff07fff
+#define FFO9_CNT_SFT 15
+#define FFO9_CNT_HI 19
+#define FFO9_CNT_SZ 5
+#define FFO10_CNT_MSK 0x00f00000
+#define FFO10_CNT_I_MSK 0xff0fffff
+#define FFO10_CNT_SFT 20
+#define FFO10_CNT_HI 23
+#define FFO10_CNT_SZ 4
+#define FFO11_CNT_MSK 0x3e000000
+#define FFO11_CNT_I_MSK 0xc1ffffff
+#define FFO11_CNT_SFT 25
+#define FFO11_CNT_HI 29
+#define FFO11_CNT_SZ 5
+#define FFO12_CNT_MSK 0x00000007
+#define FFO12_CNT_I_MSK 0xfffffff8
+#define FFO12_CNT_SFT 0
+#define FFO12_CNT_HI 2
+#define FFO12_CNT_SZ 3
+#define FFO13_CNT_MSK 0x00000060
+#define FFO13_CNT_I_MSK 0xffffff9f
+#define FFO13_CNT_SFT 5
+#define FFO13_CNT_HI 6
+#define FFO13_CNT_SZ 2
+#define FFO14_CNT_MSK 0x00000c00
+#define FFO14_CNT_I_MSK 0xfffff3ff
+#define FFO14_CNT_SFT 10
+#define FFO14_CNT_HI 11
+#define FFO14_CNT_SZ 2
+#define FFO15_CNT_MSK 0x001f8000
+#define FFO15_CNT_I_MSK 0xffe07fff
+#define FFO15_CNT_SFT 15
+#define FFO15_CNT_HI 20
+#define FFO15_CNT_SZ 6
+#define CH0_FFO_FULL_MSK 0x00000001
+#define CH0_FFO_FULL_I_MSK 0xfffffffe
+#define CH0_FFO_FULL_SFT 0
+#define CH0_FFO_FULL_HI 0
+#define CH0_FFO_FULL_SZ 1
+#define CH1_FFO_FULL_MSK 0x00000002
+#define CH1_FFO_FULL_I_MSK 0xfffffffd
+#define CH1_FFO_FULL_SFT 1
+#define CH1_FFO_FULL_HI 1
+#define CH1_FFO_FULL_SZ 1
+#define CH2_FFO_FULL_MSK 0x00000004
+#define CH2_FFO_FULL_I_MSK 0xfffffffb
+#define CH2_FFO_FULL_SFT 2
+#define CH2_FFO_FULL_HI 2
+#define CH2_FFO_FULL_SZ 1
+#define CH3_FFO_FULL_MSK 0x00000008
+#define CH3_FFO_FULL_I_MSK 0xfffffff7
+#define CH3_FFO_FULL_SFT 3
+#define CH3_FFO_FULL_HI 3
+#define CH3_FFO_FULL_SZ 1
+#define CH4_FFO_FULL_MSK 0x00000010
+#define CH4_FFO_FULL_I_MSK 0xffffffef
+#define CH4_FFO_FULL_SFT 4
+#define CH4_FFO_FULL_HI 4
+#define CH4_FFO_FULL_SZ 1
+#define CH5_FFO_FULL_MSK 0x00000020
+#define CH5_FFO_FULL_I_MSK 0xffffffdf
+#define CH5_FFO_FULL_SFT 5
+#define CH5_FFO_FULL_HI 5
+#define CH5_FFO_FULL_SZ 1
+#define CH6_FFO_FULL_MSK 0x00000040
+#define CH6_FFO_FULL_I_MSK 0xffffffbf
+#define CH6_FFO_FULL_SFT 6
+#define CH6_FFO_FULL_HI 6
+#define CH6_FFO_FULL_SZ 1
+#define CH7_FFO_FULL_MSK 0x00000080
+#define CH7_FFO_FULL_I_MSK 0xffffff7f
+#define CH7_FFO_FULL_SFT 7
+#define CH7_FFO_FULL_HI 7
+#define CH7_FFO_FULL_SZ 1
+#define CH8_FFO_FULL_MSK 0x00000100
+#define CH8_FFO_FULL_I_MSK 0xfffffeff
+#define CH8_FFO_FULL_SFT 8
+#define CH8_FFO_FULL_HI 8
+#define CH8_FFO_FULL_SZ 1
+#define CH9_FFO_FULL_MSK 0x00000200
+#define CH9_FFO_FULL_I_MSK 0xfffffdff
+#define CH9_FFO_FULL_SFT 9
+#define CH9_FFO_FULL_HI 9
+#define CH9_FFO_FULL_SZ 1
+#define CH10_FFO_FULL_MSK 0x00000400
+#define CH10_FFO_FULL_I_MSK 0xfffffbff
+#define CH10_FFO_FULL_SFT 10
+#define CH10_FFO_FULL_HI 10
+#define CH10_FFO_FULL_SZ 1
+#define CH11_FFO_FULL_MSK 0x00000800
+#define CH11_FFO_FULL_I_MSK 0xfffff7ff
+#define CH11_FFO_FULL_SFT 11
+#define CH11_FFO_FULL_HI 11
+#define CH11_FFO_FULL_SZ 1
+#define CH12_FFO_FULL_MSK 0x00001000
+#define CH12_FFO_FULL_I_MSK 0xffffefff
+#define CH12_FFO_FULL_SFT 12
+#define CH12_FFO_FULL_HI 12
+#define CH12_FFO_FULL_SZ 1
+#define CH13_FFO_FULL_MSK 0x00002000
+#define CH13_FFO_FULL_I_MSK 0xffffdfff
+#define CH13_FFO_FULL_SFT 13
+#define CH13_FFO_FULL_HI 13
+#define CH13_FFO_FULL_SZ 1
+#define CH14_FFO_FULL_MSK 0x00004000
+#define CH14_FFO_FULL_I_MSK 0xffffbfff
+#define CH14_FFO_FULL_SFT 14
+#define CH14_FFO_FULL_HI 14
+#define CH14_FFO_FULL_SZ 1
+#define CH15_FFO_FULL_MSK 0x00008000
+#define CH15_FFO_FULL_I_MSK 0xffff7fff
+#define CH15_FFO_FULL_SFT 15
+#define CH15_FFO_FULL_HI 15
+#define CH15_FFO_FULL_SZ 1
+#define CH0_LOWTHOLD_INT_MSK 0x00000001
+#define CH0_LOWTHOLD_INT_I_MSK 0xfffffffe
+#define CH0_LOWTHOLD_INT_SFT 0
+#define CH0_LOWTHOLD_INT_HI 0
+#define CH0_LOWTHOLD_INT_SZ 1
+#define CH1_LOWTHOLD_INT_MSK 0x00000002
+#define CH1_LOWTHOLD_INT_I_MSK 0xfffffffd
+#define CH1_LOWTHOLD_INT_SFT 1
+#define CH1_LOWTHOLD_INT_HI 1
+#define CH1_LOWTHOLD_INT_SZ 1
+#define CH2_LOWTHOLD_INT_MSK 0x00000004
+#define CH2_LOWTHOLD_INT_I_MSK 0xfffffffb
+#define CH2_LOWTHOLD_INT_SFT 2
+#define CH2_LOWTHOLD_INT_HI 2
+#define CH2_LOWTHOLD_INT_SZ 1
+#define CH3_LOWTHOLD_INT_MSK 0x00000008
+#define CH3_LOWTHOLD_INT_I_MSK 0xfffffff7
+#define CH3_LOWTHOLD_INT_SFT 3
+#define CH3_LOWTHOLD_INT_HI 3
+#define CH3_LOWTHOLD_INT_SZ 1
+#define CH4_LOWTHOLD_INT_MSK 0x00000010
+#define CH4_LOWTHOLD_INT_I_MSK 0xffffffef
+#define CH4_LOWTHOLD_INT_SFT 4
+#define CH4_LOWTHOLD_INT_HI 4
+#define CH4_LOWTHOLD_INT_SZ 1
+#define CH5_LOWTHOLD_INT_MSK 0x00000020
+#define CH5_LOWTHOLD_INT_I_MSK 0xffffffdf
+#define CH5_LOWTHOLD_INT_SFT 5
+#define CH5_LOWTHOLD_INT_HI 5
+#define CH5_LOWTHOLD_INT_SZ 1
+#define CH6_LOWTHOLD_INT_MSK 0x00000040
+#define CH6_LOWTHOLD_INT_I_MSK 0xffffffbf
+#define CH6_LOWTHOLD_INT_SFT 6
+#define CH6_LOWTHOLD_INT_HI 6
+#define CH6_LOWTHOLD_INT_SZ 1
+#define CH7_LOWTHOLD_INT_MSK 0x00000080
+#define CH7_LOWTHOLD_INT_I_MSK 0xffffff7f
+#define CH7_LOWTHOLD_INT_SFT 7
+#define CH7_LOWTHOLD_INT_HI 7
+#define CH7_LOWTHOLD_INT_SZ 1
+#define CH8_LOWTHOLD_INT_MSK 0x00000100
+#define CH8_LOWTHOLD_INT_I_MSK 0xfffffeff
+#define CH8_LOWTHOLD_INT_SFT 8
+#define CH8_LOWTHOLD_INT_HI 8
+#define CH8_LOWTHOLD_INT_SZ 1
+#define CH9_LOWTHOLD_INT_MSK 0x00000200
+#define CH9_LOWTHOLD_INT_I_MSK 0xfffffdff
+#define CH9_LOWTHOLD_INT_SFT 9
+#define CH9_LOWTHOLD_INT_HI 9
+#define CH9_LOWTHOLD_INT_SZ 1
+#define CH10_LOWTHOLD_INT_MSK 0x00000400
+#define CH10_LOWTHOLD_INT_I_MSK 0xfffffbff
+#define CH10_LOWTHOLD_INT_SFT 10
+#define CH10_LOWTHOLD_INT_HI 10
+#define CH10_LOWTHOLD_INT_SZ 1
+#define CH11_LOWTHOLD_INT_MSK 0x00000800
+#define CH11_LOWTHOLD_INT_I_MSK 0xfffff7ff
+#define CH11_LOWTHOLD_INT_SFT 11
+#define CH11_LOWTHOLD_INT_HI 11
+#define CH11_LOWTHOLD_INT_SZ 1
+#define CH12_LOWTHOLD_INT_MSK 0x00001000
+#define CH12_LOWTHOLD_INT_I_MSK 0xffffefff
+#define CH12_LOWTHOLD_INT_SFT 12
+#define CH12_LOWTHOLD_INT_HI 12
+#define CH12_LOWTHOLD_INT_SZ 1
+#define CH13_LOWTHOLD_INT_MSK 0x00002000
+#define CH13_LOWTHOLD_INT_I_MSK 0xffffdfff
+#define CH13_LOWTHOLD_INT_SFT 13
+#define CH13_LOWTHOLD_INT_HI 13
+#define CH13_LOWTHOLD_INT_SZ 1
+#define CH14_LOWTHOLD_INT_MSK 0x00004000
+#define CH14_LOWTHOLD_INT_I_MSK 0xffffbfff
+#define CH14_LOWTHOLD_INT_SFT 14
+#define CH14_LOWTHOLD_INT_HI 14
+#define CH14_LOWTHOLD_INT_SZ 1
+#define CH15_LOWTHOLD_INT_MSK 0x00008000
+#define CH15_LOWTHOLD_INT_I_MSK 0xffff7fff
+#define CH15_LOWTHOLD_INT_SFT 15
+#define CH15_LOWTHOLD_INT_HI 15
+#define CH15_LOWTHOLD_INT_SZ 1
+#define MB_LOW_THOLD_EN_MSK 0x80000000
+#define MB_LOW_THOLD_EN_I_MSK 0x7fffffff
+#define MB_LOW_THOLD_EN_SFT 31
+#define MB_LOW_THOLD_EN_HI 31
+#define MB_LOW_THOLD_EN_SZ 1
+#define CH0_LOWTHOLD_MSK 0x0000001f
+#define CH0_LOWTHOLD_I_MSK 0xffffffe0
+#define CH0_LOWTHOLD_SFT 0
+#define CH0_LOWTHOLD_HI 4
+#define CH0_LOWTHOLD_SZ 5
+#define CH1_LOWTHOLD_MSK 0x00001f00
+#define CH1_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH1_LOWTHOLD_SFT 8
+#define CH1_LOWTHOLD_HI 12
+#define CH1_LOWTHOLD_SZ 5
+#define CH2_LOWTHOLD_MSK 0x001f0000
+#define CH2_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH2_LOWTHOLD_SFT 16
+#define CH2_LOWTHOLD_HI 20
+#define CH2_LOWTHOLD_SZ 5
+#define CH3_LOWTHOLD_MSK 0x1f000000
+#define CH3_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH3_LOWTHOLD_SFT 24
+#define CH3_LOWTHOLD_HI 28
+#define CH3_LOWTHOLD_SZ 5
+#define CH4_LOWTHOLD_MSK 0x0000001f
+#define CH4_LOWTHOLD_I_MSK 0xffffffe0
+#define CH4_LOWTHOLD_SFT 0
+#define CH4_LOWTHOLD_HI 4
+#define CH4_LOWTHOLD_SZ 5
+#define CH5_LOWTHOLD_MSK 0x00001f00
+#define CH5_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH5_LOWTHOLD_SFT 8
+#define CH5_LOWTHOLD_HI 12
+#define CH5_LOWTHOLD_SZ 5
+#define CH6_LOWTHOLD_MSK 0x001f0000
+#define CH6_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH6_LOWTHOLD_SFT 16
+#define CH6_LOWTHOLD_HI 20
+#define CH6_LOWTHOLD_SZ 5
+#define CH7_LOWTHOLD_MSK 0x1f000000
+#define CH7_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH7_LOWTHOLD_SFT 24
+#define CH7_LOWTHOLD_HI 28
+#define CH7_LOWTHOLD_SZ 5
+#define CH8_LOWTHOLD_MSK 0x0000001f
+#define CH8_LOWTHOLD_I_MSK 0xffffffe0
+#define CH8_LOWTHOLD_SFT 0
+#define CH8_LOWTHOLD_HI 4
+#define CH8_LOWTHOLD_SZ 5
+#define CH9_LOWTHOLD_MSK 0x00001f00
+#define CH9_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH9_LOWTHOLD_SFT 8
+#define CH9_LOWTHOLD_HI 12
+#define CH9_LOWTHOLD_SZ 5
+#define CH10_LOWTHOLD_MSK 0x001f0000
+#define CH10_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH10_LOWTHOLD_SFT 16
+#define CH10_LOWTHOLD_HI 20
+#define CH10_LOWTHOLD_SZ 5
+#define CH11_LOWTHOLD_MSK 0x1f000000
+#define CH11_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH11_LOWTHOLD_SFT 24
+#define CH11_LOWTHOLD_HI 28
+#define CH11_LOWTHOLD_SZ 5
+#define CH12_LOWTHOLD_MSK 0x0000001f
+#define CH12_LOWTHOLD_I_MSK 0xffffffe0
+#define CH12_LOWTHOLD_SFT 0
+#define CH12_LOWTHOLD_HI 4
+#define CH12_LOWTHOLD_SZ 5
+#define CH13_LOWTHOLD_MSK 0x00001f00
+#define CH13_LOWTHOLD_I_MSK 0xffffe0ff
+#define CH13_LOWTHOLD_SFT 8
+#define CH13_LOWTHOLD_HI 12
+#define CH13_LOWTHOLD_SZ 5
+#define CH14_LOWTHOLD_MSK 0x001f0000
+#define CH14_LOWTHOLD_I_MSK 0xffe0ffff
+#define CH14_LOWTHOLD_SFT 16
+#define CH14_LOWTHOLD_HI 20
+#define CH14_LOWTHOLD_SZ 5
+#define CH15_LOWTHOLD_MSK 0x1f000000
+#define CH15_LOWTHOLD_I_MSK 0xe0ffffff
+#define CH15_LOWTHOLD_SFT 24
+#define CH15_LOWTHOLD_HI 28
+#define CH15_LOWTHOLD_SZ 5
+#define TRASH_TIMEOUT_EN_MSK 0x00000001
+#define TRASH_TIMEOUT_EN_I_MSK 0xfffffffe
+#define TRASH_TIMEOUT_EN_SFT 0
+#define TRASH_TIMEOUT_EN_HI 0
+#define TRASH_TIMEOUT_EN_SZ 1
+#define TRASH_CAN_INT_MSK 0x00000002
+#define TRASH_CAN_INT_I_MSK 0xfffffffd
+#define TRASH_CAN_INT_SFT 1
+#define TRASH_CAN_INT_HI 1
+#define TRASH_CAN_INT_SZ 1
+#define TRASH_INT_ID_MSK 0x000007f0
+#define TRASH_INT_ID_I_MSK 0xfffff80f
+#define TRASH_INT_ID_SFT 4
+#define TRASH_INT_ID_HI 10
+#define TRASH_INT_ID_SZ 7
+#define TRASH_TIMEOUT_MSK 0x03ff0000
+#define TRASH_TIMEOUT_I_MSK 0xfc00ffff
+#define TRASH_TIMEOUT_SFT 16
+#define TRASH_TIMEOUT_HI 25
+#define TRASH_TIMEOUT_SZ 10
+#define CH0_WRFF_FLUSH_MSK 0x00000001
+#define CH0_WRFF_FLUSH_I_MSK 0xfffffffe
+#define CH0_WRFF_FLUSH_SFT 0
+#define CH0_WRFF_FLUSH_HI 0
+#define CH0_WRFF_FLUSH_SZ 1
+#define CH1_WRFF_FLUSH_MSK 0x00000002
+#define CH1_WRFF_FLUSH_I_MSK 0xfffffffd
+#define CH1_WRFF_FLUSH_SFT 1
+#define CH1_WRFF_FLUSH_HI 1
+#define CH1_WRFF_FLUSH_SZ 1
+#define CH2_WRFF_FLUSH_MSK 0x00000004
+#define CH2_WRFF_FLUSH_I_MSK 0xfffffffb
+#define CH2_WRFF_FLUSH_SFT 2
+#define CH2_WRFF_FLUSH_HI 2
+#define CH2_WRFF_FLUSH_SZ 1
+#define CH3_WRFF_FLUSH_MSK 0x00000008
+#define CH3_WRFF_FLUSH_I_MSK 0xfffffff7
+#define CH3_WRFF_FLUSH_SFT 3
+#define CH3_WRFF_FLUSH_HI 3
+#define CH3_WRFF_FLUSH_SZ 1
+#define CH4_WRFF_FLUSH_MSK 0x00000010
+#define CH4_WRFF_FLUSH_I_MSK 0xffffffef
+#define CH4_WRFF_FLUSH_SFT 4
+#define CH4_WRFF_FLUSH_HI 4
+#define CH4_WRFF_FLUSH_SZ 1
+#define CH5_WRFF_FLUSH_MSK 0x00000020
+#define CH5_WRFF_FLUSH_I_MSK 0xffffffdf
+#define CH5_WRFF_FLUSH_SFT 5
+#define CH5_WRFF_FLUSH_HI 5
+#define CH5_WRFF_FLUSH_SZ 1
+#define CH6_WRFF_FLUSH_MSK 0x00000040
+#define CH6_WRFF_FLUSH_I_MSK 0xffffffbf
+#define CH6_WRFF_FLUSH_SFT 6
+#define CH6_WRFF_FLUSH_HI 6
+#define CH6_WRFF_FLUSH_SZ 1
+#define CH7_WRFF_FLUSH_MSK 0x00000080
+#define CH7_WRFF_FLUSH_I_MSK 0xffffff7f
+#define CH7_WRFF_FLUSH_SFT 7
+#define CH7_WRFF_FLUSH_HI 7
+#define CH7_WRFF_FLUSH_SZ 1
+#define CH8_WRFF_FLUSH_MSK 0x00000100
+#define CH8_WRFF_FLUSH_I_MSK 0xfffffeff
+#define CH8_WRFF_FLUSH_SFT 8
+#define CH8_WRFF_FLUSH_HI 8
+#define CH8_WRFF_FLUSH_SZ 1
+#define CH9_WRFF_FLUSH_MSK 0x00000200
+#define CH9_WRFF_FLUSH_I_MSK 0xfffffdff
+#define CH9_WRFF_FLUSH_SFT 9
+#define CH9_WRFF_FLUSH_HI 9
+#define CH9_WRFF_FLUSH_SZ 1
+#define CH10_WRFF_FLUSH_MSK 0x00000400
+#define CH10_WRFF_FLUSH_I_MSK 0xfffffbff
+#define CH10_WRFF_FLUSH_SFT 10
+#define CH10_WRFF_FLUSH_HI 10
+#define CH10_WRFF_FLUSH_SZ 1
+#define CH11_WRFF_FLUSH_MSK 0x00000800
+#define CH11_WRFF_FLUSH_I_MSK 0xfffff7ff
+#define CH11_WRFF_FLUSH_SFT 11
+#define CH11_WRFF_FLUSH_HI 11
+#define CH11_WRFF_FLUSH_SZ 1
+#define CH12_WRFF_FLUSH_MSK 0x00001000
+#define CH12_WRFF_FLUSH_I_MSK 0xffffefff
+#define CH12_WRFF_FLUSH_SFT 12
+#define CH12_WRFF_FLUSH_HI 12
+#define CH12_WRFF_FLUSH_SZ 1
+#define CH13_WRFF_FLUSH_MSK 0x00002000
+#define CH13_WRFF_FLUSH_I_MSK 0xffffdfff
+#define CH13_WRFF_FLUSH_SFT 13
+#define CH13_WRFF_FLUSH_HI 13
+#define CH13_WRFF_FLUSH_SZ 1
+#define CH14_WRFF_FLUSH_MSK 0x00004000
+#define CH14_WRFF_FLUSH_I_MSK 0xffffbfff
+#define CH14_WRFF_FLUSH_SFT 14
+#define CH14_WRFF_FLUSH_HI 14
+#define CH14_WRFF_FLUSH_SZ 1
+#define CPU_ID_TB2_MSK 0xffffffff
+#define CPU_ID_TB2_I_MSK 0x00000000
+#define CPU_ID_TB2_SFT 0
+#define CPU_ID_TB2_HI 31
+#define CPU_ID_TB2_SZ 32
+#define CPU_ID_TB3_MSK 0xffffffff
+#define CPU_ID_TB3_I_MSK 0x00000000
+#define CPU_ID_TB3_SFT 0
+#define CPU_ID_TB3_HI 31
+#define CPU_ID_TB3_SZ 32
+#define IQ_LOG_EN_MSK 0x00000001
+#define IQ_LOG_EN_I_MSK 0xfffffffe
+#define IQ_LOG_EN_SFT 0
+#define IQ_LOG_EN_HI 0
+#define IQ_LOG_EN_SZ 1
+#define IQ_LOG_STOP_MODE_MSK 0x00000001
+#define IQ_LOG_STOP_MODE_I_MSK 0xfffffffe
+#define IQ_LOG_STOP_MODE_SFT 0
+#define IQ_LOG_STOP_MODE_HI 0
+#define IQ_LOG_STOP_MODE_SZ 1
+#define GPIO_STOP_EN_MSK 0x00000010
+#define GPIO_STOP_EN_I_MSK 0xffffffef
+#define GPIO_STOP_EN_SFT 4
+#define GPIO_STOP_EN_HI 4
+#define GPIO_STOP_EN_SZ 1
+#define GPIO_STOP_POL_MSK 0x00000020
+#define GPIO_STOP_POL_I_MSK 0xffffffdf
+#define GPIO_STOP_POL_SFT 5
+#define GPIO_STOP_POL_HI 5
+#define GPIO_STOP_POL_SZ 1
+#define IQ_LOG_TIMER_MSK 0xffff0000
+#define IQ_LOG_TIMER_I_MSK 0x0000ffff
+#define IQ_LOG_TIMER_SFT 16
+#define IQ_LOG_TIMER_HI 31
+#define IQ_LOG_TIMER_SZ 16
+#define IQ_LOG_LEN_MSK 0x0000ffff
+#define IQ_LOG_LEN_I_MSK 0xffff0000
+#define IQ_LOG_LEN_SFT 0
+#define IQ_LOG_LEN_HI 15
+#define IQ_LOG_LEN_SZ 16
+#define IQ_LOG_TAIL_ADR_MSK 0x0000ffff
+#define IQ_LOG_TAIL_ADR_I_MSK 0xffff0000
+#define IQ_LOG_TAIL_ADR_SFT 0
+#define IQ_LOG_TAIL_ADR_HI 15
+#define IQ_LOG_TAIL_ADR_SZ 16
+#define ALC_LENG_MSK 0x0003ffff
+#define ALC_LENG_I_MSK 0xfffc0000
+#define ALC_LENG_SFT 0
+#define ALC_LENG_HI 17
+#define ALC_LENG_SZ 18
+#define CH0_DYN_PRI_MSK 0x00300000
+#define CH0_DYN_PRI_I_MSK 0xffcfffff
+#define CH0_DYN_PRI_SFT 20
+#define CH0_DYN_PRI_HI 21
+#define CH0_DYN_PRI_SZ 2
+#define MCU_PKTID_MSK 0xffffffff
+#define MCU_PKTID_I_MSK 0x00000000
+#define MCU_PKTID_SFT 0
+#define MCU_PKTID_HI 31
+#define MCU_PKTID_SZ 32
+#define CH0_STA_PRI_MSK 0x00000003
+#define CH0_STA_PRI_I_MSK 0xfffffffc
+#define CH0_STA_PRI_SFT 0
+#define CH0_STA_PRI_HI 1
+#define CH0_STA_PRI_SZ 2
+#define CH1_STA_PRI_MSK 0x00000030
+#define CH1_STA_PRI_I_MSK 0xffffffcf
+#define CH1_STA_PRI_SFT 4
+#define CH1_STA_PRI_HI 5
+#define CH1_STA_PRI_SZ 2
+#define CH2_STA_PRI_MSK 0x00000300
+#define CH2_STA_PRI_I_MSK 0xfffffcff
+#define CH2_STA_PRI_SFT 8
+#define CH2_STA_PRI_HI 9
+#define CH2_STA_PRI_SZ 2
+#define CH3_STA_PRI_MSK 0x00003000
+#define CH3_STA_PRI_I_MSK 0xffffcfff
+#define CH3_STA_PRI_SFT 12
+#define CH3_STA_PRI_HI 13
+#define CH3_STA_PRI_SZ 2
+#define ID_TB0_MSK 0xffffffff
+#define ID_TB0_I_MSK 0x00000000
+#define ID_TB0_SFT 0
+#define ID_TB0_HI 31
+#define ID_TB0_SZ 32
+#define ID_TB1_MSK 0xffffffff
+#define ID_TB1_I_MSK 0x00000000
+#define ID_TB1_SFT 0
+#define ID_TB1_HI 31
+#define ID_TB1_SZ 32
+#define ID_MNG_HALT_MSK 0x00000010
+#define ID_MNG_HALT_I_MSK 0xffffffef
+#define ID_MNG_HALT_SFT 4
+#define ID_MNG_HALT_HI 4
+#define ID_MNG_HALT_SZ 1
+#define ID_MNG_ERR_HALT_EN_MSK 0x00000020
+#define ID_MNG_ERR_HALT_EN_I_MSK 0xffffffdf
+#define ID_MNG_ERR_HALT_EN_SFT 5
+#define ID_MNG_ERR_HALT_EN_HI 5
+#define ID_MNG_ERR_HALT_EN_SZ 1
+#define ID_EXCEPT_FLG_CLR_MSK 0x00000040
+#define ID_EXCEPT_FLG_CLR_I_MSK 0xffffffbf
+#define ID_EXCEPT_FLG_CLR_SFT 6
+#define ID_EXCEPT_FLG_CLR_HI 6
+#define ID_EXCEPT_FLG_CLR_SZ 1
+#define ID_EXCEPT_FLG_MSK 0x00000080
+#define ID_EXCEPT_FLG_I_MSK 0xffffff7f
+#define ID_EXCEPT_FLG_SFT 7
+#define ID_EXCEPT_FLG_HI 7
+#define ID_EXCEPT_FLG_SZ 1
+#define ID_FULL_MSK 0x00000001
+#define ID_FULL_I_MSK 0xfffffffe
+#define ID_FULL_SFT 0
+#define ID_FULL_HI 0
+#define ID_FULL_SZ 1
+#define ID_MNG_BUSY_MSK 0x00000002
+#define ID_MNG_BUSY_I_MSK 0xfffffffd
+#define ID_MNG_BUSY_SFT 1
+#define ID_MNG_BUSY_HI 1
+#define ID_MNG_BUSY_SZ 1
+#define REQ_LOCK_MSK 0x00000004
+#define REQ_LOCK_I_MSK 0xfffffffb
+#define REQ_LOCK_SFT 2
+#define REQ_LOCK_HI 2
+#define REQ_LOCK_SZ 1
+#define CH0_REQ_LOCK_MSK 0x00000010
+#define CH0_REQ_LOCK_I_MSK 0xffffffef
+#define CH0_REQ_LOCK_SFT 4
+#define CH0_REQ_LOCK_HI 4
+#define CH0_REQ_LOCK_SZ 1
+#define CH1_REQ_LOCK_MSK 0x00000020
+#define CH1_REQ_LOCK_I_MSK 0xffffffdf
+#define CH1_REQ_LOCK_SFT 5
+#define CH1_REQ_LOCK_HI 5
+#define CH1_REQ_LOCK_SZ 1
+#define CH2_REQ_LOCK_MSK 0x00000040
+#define CH2_REQ_LOCK_I_MSK 0xffffffbf
+#define CH2_REQ_LOCK_SFT 6
+#define CH2_REQ_LOCK_HI 6
+#define CH2_REQ_LOCK_SZ 1
+#define CH3_REQ_LOCK_MSK 0x00000080
+#define CH3_REQ_LOCK_I_MSK 0xffffff7f
+#define CH3_REQ_LOCK_SFT 7
+#define CH3_REQ_LOCK_HI 7
+#define CH3_REQ_LOCK_SZ 1
+#define REQ_LOCK_INT_EN_MSK 0x00000100
+#define REQ_LOCK_INT_EN_I_MSK 0xfffffeff
+#define REQ_LOCK_INT_EN_SFT 8
+#define REQ_LOCK_INT_EN_HI 8
+#define REQ_LOCK_INT_EN_SZ 1
+#define REQ_LOCK_INT_MSK 0x00000200
+#define REQ_LOCK_INT_I_MSK 0xfffffdff
+#define REQ_LOCK_INT_SFT 9
+#define REQ_LOCK_INT_HI 9
+#define REQ_LOCK_INT_SZ 1
+#define MCU_ALC_READY_MSK 0x00000001
+#define MCU_ALC_READY_I_MSK 0xfffffffe
+#define MCU_ALC_READY_SFT 0
+#define MCU_ALC_READY_HI 0
+#define MCU_ALC_READY_SZ 1
+#define ALC_FAIL_MSK 0x00000002
+#define ALC_FAIL_I_MSK 0xfffffffd
+#define ALC_FAIL_SFT 1
+#define ALC_FAIL_HI 1
+#define ALC_FAIL_SZ 1
+#define ALC_BUSY_MSK 0x00000004
+#define ALC_BUSY_I_MSK 0xfffffffb
+#define ALC_BUSY_SFT 2
+#define ALC_BUSY_HI 2
+#define ALC_BUSY_SZ 1
+#define CH0_NVLD_MSK 0x00000010
+#define CH0_NVLD_I_MSK 0xffffffef
+#define CH0_NVLD_SFT 4
+#define CH0_NVLD_HI 4
+#define CH0_NVLD_SZ 1
+#define CH1_NVLD_MSK 0x00000020
+#define CH1_NVLD_I_MSK 0xffffffdf
+#define CH1_NVLD_SFT 5
+#define CH1_NVLD_HI 5
+#define CH1_NVLD_SZ 1
+#define CH2_NVLD_MSK 0x00000040
+#define CH2_NVLD_I_MSK 0xffffffbf
+#define CH2_NVLD_SFT 6
+#define CH2_NVLD_HI 6
+#define CH2_NVLD_SZ 1
+#define CH3_NVLD_MSK 0x00000080
+#define CH3_NVLD_I_MSK 0xffffff7f
+#define CH3_NVLD_SFT 7
+#define CH3_NVLD_HI 7
+#define CH3_NVLD_SZ 1
+#define ALC_INT_ID_MSK 0x00007f00
+#define ALC_INT_ID_I_MSK 0xffff80ff
+#define ALC_INT_ID_SFT 8
+#define ALC_INT_ID_HI 14
+#define ALC_INT_ID_SZ 7
+#define ALC_TIMEOUT_MSK 0x03ff0000
+#define ALC_TIMEOUT_I_MSK 0xfc00ffff
+#define ALC_TIMEOUT_SFT 16
+#define ALC_TIMEOUT_HI 25
+#define ALC_TIMEOUT_SZ 10
+#define ALC_TIMEOUT_INT_EN_MSK 0x40000000
+#define ALC_TIMEOUT_INT_EN_I_MSK 0xbfffffff
+#define ALC_TIMEOUT_INT_EN_SFT 30
+#define ALC_TIMEOUT_INT_EN_HI 30
+#define ALC_TIMEOUT_INT_EN_SZ 1
+#define ALC_TIMEOUT_INT_MSK 0x80000000
+#define ALC_TIMEOUT_INT_I_MSK 0x7fffffff
+#define ALC_TIMEOUT_INT_SFT 31
+#define ALC_TIMEOUT_INT_HI 31
+#define ALC_TIMEOUT_INT_SZ 1
+#define TX_ID_COUNT_MSK 0x000000ff
+#define TX_ID_COUNT_I_MSK 0xffffff00
+#define TX_ID_COUNT_SFT 0
+#define TX_ID_COUNT_HI 7
+#define TX_ID_COUNT_SZ 8
+#define RX_ID_COUNT_MSK 0x0000ff00
+#define RX_ID_COUNT_I_MSK 0xffff00ff
+#define RX_ID_COUNT_SFT 8
+#define RX_ID_COUNT_HI 15
+#define RX_ID_COUNT_SZ 8
+#define TX_ID_THOLD_MSK 0x000000ff
+#define TX_ID_THOLD_I_MSK 0xffffff00
+#define TX_ID_THOLD_SFT 0
+#define TX_ID_THOLD_HI 7
+#define TX_ID_THOLD_SZ 8
+#define RX_ID_THOLD_MSK 0x0000ff00
+#define RX_ID_THOLD_I_MSK 0xffff00ff
+#define RX_ID_THOLD_SFT 8
+#define RX_ID_THOLD_HI 15
+#define RX_ID_THOLD_SZ 8
+#define ID_THOLD_RX_INT_MSK 0x00010000
+#define ID_THOLD_RX_INT_I_MSK 0xfffeffff
+#define ID_THOLD_RX_INT_SFT 16
+#define ID_THOLD_RX_INT_HI 16
+#define ID_THOLD_RX_INT_SZ 1
+#define RX_INT_CH_MSK 0x000e0000
+#define RX_INT_CH_I_MSK 0xfff1ffff
+#define RX_INT_CH_SFT 17
+#define RX_INT_CH_HI 19
+#define RX_INT_CH_SZ 3
+#define ID_THOLD_TX_INT_MSK 0x00100000
+#define ID_THOLD_TX_INT_I_MSK 0xffefffff
+#define ID_THOLD_TX_INT_SFT 20
+#define ID_THOLD_TX_INT_HI 20
+#define ID_THOLD_TX_INT_SZ 1
+#define TX_INT_CH_MSK 0x00e00000
+#define TX_INT_CH_I_MSK 0xff1fffff
+#define TX_INT_CH_SFT 21
+#define TX_INT_CH_HI 23
+#define TX_INT_CH_SZ 3
+#define ID_THOLD_INT_EN_MSK 0x01000000
+#define ID_THOLD_INT_EN_I_MSK 0xfeffffff
+#define ID_THOLD_INT_EN_SFT 24
+#define ID_THOLD_INT_EN_HI 24
+#define ID_THOLD_INT_EN_SZ 1
+#define TX_ID_TB0_MSK 0xffffffff
+#define TX_ID_TB0_I_MSK 0x00000000
+#define TX_ID_TB0_SFT 0
+#define TX_ID_TB0_HI 31
+#define TX_ID_TB0_SZ 32
+#define TX_ID_TB1_MSK 0xffffffff
+#define TX_ID_TB1_I_MSK 0x00000000
+#define TX_ID_TB1_SFT 0
+#define TX_ID_TB1_HI 31
+#define TX_ID_TB1_SZ 32
+#define RX_ID_TB0_MSK 0xffffffff
+#define RX_ID_TB0_I_MSK 0x00000000
+#define RX_ID_TB0_SFT 0
+#define RX_ID_TB0_HI 31
+#define RX_ID_TB0_SZ 32
+#define RX_ID_TB1_MSK 0xffffffff
+#define RX_ID_TB1_I_MSK 0x00000000
+#define RX_ID_TB1_SFT 0
+#define RX_ID_TB1_HI 31
+#define RX_ID_TB1_SZ 32
+#define DOUBLE_RLS_INT_EN_MSK 0x00000001
+#define DOUBLE_RLS_INT_EN_I_MSK 0xfffffffe
+#define DOUBLE_RLS_INT_EN_SFT 0
+#define DOUBLE_RLS_INT_EN_HI 0
+#define DOUBLE_RLS_INT_EN_SZ 1
+#define ID_DOUBLE_RLS_INT_MSK 0x00000002
+#define ID_DOUBLE_RLS_INT_I_MSK 0xfffffffd
+#define ID_DOUBLE_RLS_INT_SFT 1
+#define ID_DOUBLE_RLS_INT_HI 1
+#define ID_DOUBLE_RLS_INT_SZ 1
+#define DOUBLE_RLS_ID_MSK 0x00007f00
+#define DOUBLE_RLS_ID_I_MSK 0xffff80ff
+#define DOUBLE_RLS_ID_SFT 8
+#define DOUBLE_RLS_ID_HI 14
+#define DOUBLE_RLS_ID_SZ 7
+#define ID_LEN_THOLD_INT_EN_MSK 0x00000001
+#define ID_LEN_THOLD_INT_EN_I_MSK 0xfffffffe
+#define ID_LEN_THOLD_INT_EN_SFT 0
+#define ID_LEN_THOLD_INT_EN_HI 0
+#define ID_LEN_THOLD_INT_EN_SZ 1
+#define ALL_ID_LEN_THOLD_INT_MSK 0x00000002
+#define ALL_ID_LEN_THOLD_INT_I_MSK 0xfffffffd
+#define ALL_ID_LEN_THOLD_INT_SFT 1
+#define ALL_ID_LEN_THOLD_INT_HI 1
+#define ALL_ID_LEN_THOLD_INT_SZ 1
+#define TX_ID_LEN_THOLD_INT_MSK 0x00000004
+#define TX_ID_LEN_THOLD_INT_I_MSK 0xfffffffb
+#define TX_ID_LEN_THOLD_INT_SFT 2
+#define TX_ID_LEN_THOLD_INT_HI 2
+#define TX_ID_LEN_THOLD_INT_SZ 1
+#define RX_ID_LEN_THOLD_INT_MSK 0x00000008
+#define RX_ID_LEN_THOLD_INT_I_MSK 0xfffffff7
+#define RX_ID_LEN_THOLD_INT_SFT 3
+#define RX_ID_LEN_THOLD_INT_HI 3
+#define RX_ID_LEN_THOLD_INT_SZ 1
+#define ID_TX_LEN_THOLD_MSK 0x00001ff0
+#define ID_TX_LEN_THOLD_I_MSK 0xffffe00f
+#define ID_TX_LEN_THOLD_SFT 4
+#define ID_TX_LEN_THOLD_HI 12
+#define ID_TX_LEN_THOLD_SZ 9
+#define ID_RX_LEN_THOLD_MSK 0x003fe000
+#define ID_RX_LEN_THOLD_I_MSK 0xffc01fff
+#define ID_RX_LEN_THOLD_SFT 13
+#define ID_RX_LEN_THOLD_HI 21
+#define ID_RX_LEN_THOLD_SZ 9
+#define ID_LEN_THOLD_MSK 0x7fc00000
+#define ID_LEN_THOLD_I_MSK 0x803fffff
+#define ID_LEN_THOLD_SFT 22
+#define ID_LEN_THOLD_HI 30
+#define ID_LEN_THOLD_SZ 9
+#define ALL_ID_ALC_LEN_MSK 0x000001ff
+#define ALL_ID_ALC_LEN_I_MSK 0xfffffe00
+#define ALL_ID_ALC_LEN_SFT 0
+#define ALL_ID_ALC_LEN_HI 8
+#define ALL_ID_ALC_LEN_SZ 9
+#define TX_ID_ALC_LEN_MSK 0x0003fe00
+#define TX_ID_ALC_LEN_I_MSK 0xfffc01ff
+#define TX_ID_ALC_LEN_SFT 9
+#define TX_ID_ALC_LEN_HI 17
+#define TX_ID_ALC_LEN_SZ 9
+#define RX_ID_ALC_LEN_MSK 0x07fc0000
+#define RX_ID_ALC_LEN_I_MSK 0xf803ffff
+#define RX_ID_ALC_LEN_SFT 18
+#define RX_ID_ALC_LEN_HI 26
+#define RX_ID_ALC_LEN_SZ 9
+#define CH_ARB_EN_MSK 0x00000001
+#define CH_ARB_EN_I_MSK 0xfffffffe
+#define CH_ARB_EN_SFT 0
+#define CH_ARB_EN_HI 0
+#define CH_ARB_EN_SZ 1
+#define CH_PRI1_MSK 0x00000030
+#define CH_PRI1_I_MSK 0xffffffcf
+#define CH_PRI1_SFT 4
+#define CH_PRI1_HI 5
+#define CH_PRI1_SZ 2
+#define CH_PRI2_MSK 0x00000300
+#define CH_PRI2_I_MSK 0xfffffcff
+#define CH_PRI2_SFT 8
+#define CH_PRI2_HI 9
+#define CH_PRI2_SZ 2
+#define CH_PRI3_MSK 0x00003000
+#define CH_PRI3_I_MSK 0xffffcfff
+#define CH_PRI3_SFT 12
+#define CH_PRI3_HI 13
+#define CH_PRI3_SZ 2
+#define CH_PRI4_MSK 0x00030000
+#define CH_PRI4_I_MSK 0xfffcffff
+#define CH_PRI4_SFT 16
+#define CH_PRI4_HI 17
+#define CH_PRI4_SZ 2
+#define TX_ID_REMAIN_MSK 0x0000007f
+#define TX_ID_REMAIN_I_MSK 0xffffff80
+#define TX_ID_REMAIN_SFT 0
+#define TX_ID_REMAIN_HI 6
+#define TX_ID_REMAIN_SZ 7
+#define TX_PAGE_REMAIN_MSK 0x0001ff00
+#define TX_PAGE_REMAIN_I_MSK 0xfffe00ff
+#define TX_PAGE_REMAIN_SFT 8
+#define TX_PAGE_REMAIN_HI 16
+#define TX_PAGE_REMAIN_SZ 9
+#define ID_PAGE_MAX_SIZE_MSK 0x000001ff
+#define ID_PAGE_MAX_SIZE_I_MSK 0xfffffe00
+#define ID_PAGE_MAX_SIZE_SFT 0
+#define ID_PAGE_MAX_SIZE_HI 8
+#define ID_PAGE_MAX_SIZE_SZ 9
+#define TX_PAGE_LIMIT_MSK 0x000001ff
+#define TX_PAGE_LIMIT_I_MSK 0xfffffe00
+#define TX_PAGE_LIMIT_SFT 0
+#define TX_PAGE_LIMIT_HI 8
+#define TX_PAGE_LIMIT_SZ 9
+#define TX_COUNT_LIMIT_MSK 0x00ff0000
+#define TX_COUNT_LIMIT_I_MSK 0xff00ffff
+#define TX_COUNT_LIMIT_SFT 16
+#define TX_COUNT_LIMIT_HI 23
+#define TX_COUNT_LIMIT_SZ 8
+#define TX_LIMIT_INT_MSK 0x40000000
+#define TX_LIMIT_INT_I_MSK 0xbfffffff
+#define TX_LIMIT_INT_SFT 30
+#define TX_LIMIT_INT_HI 30
+#define TX_LIMIT_INT_SZ 1
+#define TX_LIMIT_INT_EN_MSK 0x80000000
+#define TX_LIMIT_INT_EN_I_MSK 0x7fffffff
+#define TX_LIMIT_INT_EN_SFT 31
+#define TX_LIMIT_INT_EN_HI 31
+#define TX_LIMIT_INT_EN_SZ 1
+#define TX_PAGE_USE_7_0_MSK 0x000000ff
+#define TX_PAGE_USE_7_0_I_MSK 0xffffff00
+#define TX_PAGE_USE_7_0_SFT 0
+#define TX_PAGE_USE_7_0_HI 7
+#define TX_PAGE_USE_7_0_SZ 8
+#define TX_ID_USE_5_0_MSK 0x00003f00
+#define TX_ID_USE_5_0_I_MSK 0xffffc0ff
+#define TX_ID_USE_5_0_SFT 8
+#define TX_ID_USE_5_0_HI 13
+#define TX_ID_USE_5_0_SZ 6
+#define EDCA0_FFO_CNT_MSK 0x0003c000
+#define EDCA0_FFO_CNT_I_MSK 0xfffc3fff
+#define EDCA0_FFO_CNT_SFT 14
+#define EDCA0_FFO_CNT_HI 17
+#define EDCA0_FFO_CNT_SZ 4
+#define EDCA1_FFO_CNT_3_0_MSK 0x003c0000
+#define EDCA1_FFO_CNT_3_0_I_MSK 0xffc3ffff
+#define EDCA1_FFO_CNT_3_0_SFT 18
+#define EDCA1_FFO_CNT_3_0_HI 21
+#define EDCA1_FFO_CNT_3_0_SZ 4
+#define EDCA2_FFO_CNT_MSK 0x07c00000
+#define EDCA2_FFO_CNT_I_MSK 0xf83fffff
+#define EDCA2_FFO_CNT_SFT 22
+#define EDCA2_FFO_CNT_HI 26
+#define EDCA2_FFO_CNT_SZ 5
+#define EDCA3_FFO_CNT_MSK 0xf8000000
+#define EDCA3_FFO_CNT_I_MSK 0x07ffffff
+#define EDCA3_FFO_CNT_SFT 27
+#define EDCA3_FFO_CNT_HI 31
+#define EDCA3_FFO_CNT_SZ 5
+#define ID_TB2_MSK 0xffffffff
+#define ID_TB2_I_MSK 0x00000000
+#define ID_TB2_SFT 0
+#define ID_TB2_HI 31
+#define ID_TB2_SZ 32
+#define ID_TB3_MSK 0xffffffff
+#define ID_TB3_I_MSK 0x00000000
+#define ID_TB3_SFT 0
+#define ID_TB3_HI 31
+#define ID_TB3_SZ 32
+#define TX_ID_TB2_MSK 0xffffffff
+#define TX_ID_TB2_I_MSK 0x00000000
+#define TX_ID_TB2_SFT 0
+#define TX_ID_TB2_HI 31
+#define TX_ID_TB2_SZ 32
+#define TX_ID_TB3_MSK 0xffffffff
+#define TX_ID_TB3_I_MSK 0x00000000
+#define TX_ID_TB3_SFT 0
+#define TX_ID_TB3_HI 31
+#define TX_ID_TB3_SZ 32
+#define RX_ID_TB2_MSK 0xffffffff
+#define RX_ID_TB2_I_MSK 0x00000000
+#define RX_ID_TB2_SFT 0
+#define RX_ID_TB2_HI 31
+#define RX_ID_TB2_SZ 32
+#define RX_ID_TB3_MSK 0xffffffff
+#define RX_ID_TB3_I_MSK 0x00000000
+#define RX_ID_TB3_SFT 0
+#define RX_ID_TB3_HI 31
+#define RX_ID_TB3_SZ 32
+#define TX_PAGE_USE2_MSK 0x000001ff
+#define TX_PAGE_USE2_I_MSK 0xfffffe00
+#define TX_PAGE_USE2_SFT 0
+#define TX_PAGE_USE2_HI 8
+#define TX_PAGE_USE2_SZ 9
+#define TX_ID_USE2_MSK 0x0001fe00
+#define TX_ID_USE2_I_MSK 0xfffe01ff
+#define TX_ID_USE2_SFT 9
+#define TX_ID_USE2_HI 16
+#define TX_ID_USE2_SZ 8
+#define EDCA4_FFO_CNT_MSK 0x001e0000
+#define EDCA4_FFO_CNT_I_MSK 0xffe1ffff
+#define EDCA4_FFO_CNT_SFT 17
+#define EDCA4_FFO_CNT_HI 20
+#define EDCA4_FFO_CNT_SZ 4
+#define TX_PAGE_USE3_MSK 0x000001ff
+#define TX_PAGE_USE3_I_MSK 0xfffffe00
+#define TX_PAGE_USE3_SFT 0
+#define TX_PAGE_USE3_HI 8
+#define TX_PAGE_USE3_SZ 9
+#define TX_ID_USE3_MSK 0x0001fe00
+#define TX_ID_USE3_I_MSK 0xfffe01ff
+#define TX_ID_USE3_SFT 9
+#define TX_ID_USE3_HI 16
+#define TX_ID_USE3_SZ 8
+#define EDCA1_FFO_CNT2_MSK 0x03e00000
+#define EDCA1_FFO_CNT2_I_MSK 0xfc1fffff
+#define EDCA1_FFO_CNT2_SFT 21
+#define EDCA1_FFO_CNT2_HI 25
+#define EDCA1_FFO_CNT2_SZ 5
+#define EDCA4_FFO_CNT2_MSK 0x3c000000
+#define EDCA4_FFO_CNT2_I_MSK 0xc3ffffff
+#define EDCA4_FFO_CNT2_SFT 26
+#define EDCA4_FFO_CNT2_HI 29
+#define EDCA4_FFO_CNT2_SZ 4
+#define TX_PAGE_USE4_MSK 0x000001ff
+#define TX_PAGE_USE4_I_MSK 0xfffffe00
+#define TX_PAGE_USE4_SFT 0
+#define TX_PAGE_USE4_HI 8
+#define TX_PAGE_USE4_SZ 9
+#define TX_ID_USE4_MSK 0x0001fe00
+#define TX_ID_USE4_I_MSK 0xfffe01ff
+#define TX_ID_USE4_SFT 9
+#define TX_ID_USE4_HI 16
+#define TX_ID_USE4_SZ 8
+#define EDCA2_FFO_CNT2_MSK 0x003e0000
+#define EDCA2_FFO_CNT2_I_MSK 0xffc1ffff
+#define EDCA2_FFO_CNT2_SFT 17
+#define EDCA2_FFO_CNT2_HI 21
+#define EDCA2_FFO_CNT2_SZ 5
+#define EDCA3_FFO_CNT2_MSK 0x07c00000
+#define EDCA3_FFO_CNT2_I_MSK 0xf83fffff
+#define EDCA3_FFO_CNT2_SFT 22
+#define EDCA3_FFO_CNT2_HI 26
+#define EDCA3_FFO_CNT2_SZ 5
+#define TX_ID_IFO_LEN_MSK 0x000001ff
+#define TX_ID_IFO_LEN_I_MSK 0xfffffe00
+#define TX_ID_IFO_LEN_SFT 0
+#define TX_ID_IFO_LEN_HI 8
+#define TX_ID_IFO_LEN_SZ 9
+#define RX_ID_IFO_LEN_MSK 0x01ff0000
+#define RX_ID_IFO_LEN_I_MSK 0xfe00ffff
+#define RX_ID_IFO_LEN_SFT 16
+#define RX_ID_IFO_LEN_HI 24
+#define RX_ID_IFO_LEN_SZ 9
+#define MAX_ALL_ALC_ID_CNT_MSK 0x000000ff
+#define MAX_ALL_ALC_ID_CNT_I_MSK 0xffffff00
+#define MAX_ALL_ALC_ID_CNT_SFT 0
+#define MAX_ALL_ALC_ID_CNT_HI 7
+#define MAX_ALL_ALC_ID_CNT_SZ 8
+#define MAX_TX_ALC_ID_CNT_MSK 0x0000ff00
+#define MAX_TX_ALC_ID_CNT_I_MSK 0xffff00ff
+#define MAX_TX_ALC_ID_CNT_SFT 8
+#define MAX_TX_ALC_ID_CNT_HI 15
+#define MAX_TX_ALC_ID_CNT_SZ 8
+#define MAX_RX_ALC_ID_CNT_MSK 0x00ff0000
+#define MAX_RX_ALC_ID_CNT_I_MSK 0xff00ffff
+#define MAX_RX_ALC_ID_CNT_SFT 16
+#define MAX_RX_ALC_ID_CNT_HI 23
+#define MAX_RX_ALC_ID_CNT_SZ 8
+#define MAX_ALL_ID_ALC_LEN_MSK 0x000001ff
+#define MAX_ALL_ID_ALC_LEN_I_MSK 0xfffffe00
+#define MAX_ALL_ID_ALC_LEN_SFT 0
+#define MAX_ALL_ID_ALC_LEN_HI 8
+#define MAX_ALL_ID_ALC_LEN_SZ 9
+#define MAX_TX_ID_ALC_LEN_MSK 0x0003fe00
+#define MAX_TX_ID_ALC_LEN_I_MSK 0xfffc01ff
+#define MAX_TX_ID_ALC_LEN_SFT 9
+#define MAX_TX_ID_ALC_LEN_HI 17
+#define MAX_TX_ID_ALC_LEN_SZ 9
+#define MAX_RX_ID_ALC_LEN_MSK 0x07fc0000
+#define MAX_RX_ID_ALC_LEN_I_MSK 0xf803ffff
+#define MAX_RX_ID_ALC_LEN_SFT 18
+#define MAX_RX_ID_ALC_LEN_HI 26
+#define MAX_RX_ID_ALC_LEN_SZ 9
+#define RG_PMDLBK_MSK 0x00000001
+#define RG_PMDLBK_I_MSK 0xfffffffe
+#define RG_PMDLBK_SFT 0
+#define RG_PMDLBK_HI 0
+#define RG_PMDLBK_SZ 1
+#define RG_RDYACK_SEL_MSK 0x00000006
+#define RG_RDYACK_SEL_I_MSK 0xfffffff9
+#define RG_RDYACK_SEL_SFT 1
+#define RG_RDYACK_SEL_HI 2
+#define RG_RDYACK_SEL_SZ 2
+#define RG_ADEDGE_SEL_MSK 0x00000008
+#define RG_ADEDGE_SEL_I_MSK 0xfffffff7
+#define RG_ADEDGE_SEL_SFT 3
+#define RG_ADEDGE_SEL_HI 3
+#define RG_ADEDGE_SEL_SZ 1
+#define RG_SIGN_SWAP_MSK 0x00000010
+#define RG_SIGN_SWAP_I_MSK 0xffffffef
+#define RG_SIGN_SWAP_SFT 4
+#define RG_SIGN_SWAP_HI 4
+#define RG_SIGN_SWAP_SZ 1
+#define RG_IQ_SWAP_MSK 0x00000020
+#define RG_IQ_SWAP_I_MSK 0xffffffdf
+#define RG_IQ_SWAP_SFT 5
+#define RG_IQ_SWAP_HI 5
+#define RG_IQ_SWAP_SZ 1
+#define RG_Q_INV_MSK 0x00000040
+#define RG_Q_INV_I_MSK 0xffffffbf
+#define RG_Q_INV_SFT 6
+#define RG_Q_INV_HI 6
+#define RG_Q_INV_SZ 1
+#define RG_I_INV_MSK 0x00000080
+#define RG_I_INV_I_MSK 0xffffff7f
+#define RG_I_INV_SFT 7
+#define RG_I_INV_HI 7
+#define RG_I_INV_SZ 1
+#define RG_BYPASS_ACI_MSK 0x00000100
+#define RG_BYPASS_ACI_I_MSK 0xfffffeff
+#define RG_BYPASS_ACI_SFT 8
+#define RG_BYPASS_ACI_HI 8
+#define RG_BYPASS_ACI_SZ 1
+#define RG_LBK_ANA_PATH_MSK 0x00000200
+#define RG_LBK_ANA_PATH_I_MSK 0xfffffdff
+#define RG_LBK_ANA_PATH_SFT 9
+#define RG_LBK_ANA_PATH_HI 9
+#define RG_LBK_ANA_PATH_SZ 1
+#define RG_SPECTRUM_LEAKY_FACTOR_MSK 0x00000c00
+#define RG_SPECTRUM_LEAKY_FACTOR_I_MSK 0xfffff3ff
+#define RG_SPECTRUM_LEAKY_FACTOR_SFT 10
+#define RG_SPECTRUM_LEAKY_FACTOR_HI 11
+#define RG_SPECTRUM_LEAKY_FACTOR_SZ 2
+#define RG_SPECTRUM_BW_MSK 0x00003000
+#define RG_SPECTRUM_BW_I_MSK 0xffffcfff
+#define RG_SPECTRUM_BW_SFT 12
+#define RG_SPECTRUM_BW_HI 13
+#define RG_SPECTRUM_BW_SZ 2
+#define RG_SPECTRUM_FREQ_MANUAL_MSK 0x00004000
+#define RG_SPECTRUM_FREQ_MANUAL_I_MSK 0xffffbfff
+#define RG_SPECTRUM_FREQ_MANUAL_SFT 14
+#define RG_SPECTRUM_FREQ_MANUAL_HI 14
+#define RG_SPECTRUM_FREQ_MANUAL_SZ 1
+#define RG_SPECTRUM_EN_MSK 0x00008000
+#define RG_SPECTRUM_EN_I_MSK 0xffff7fff
+#define RG_SPECTRUM_EN_SFT 15
+#define RG_SPECTRUM_EN_HI 15
+#define RG_SPECTRUM_EN_SZ 1
+#define RG_TXPWRLVL_SET_MSK 0x00ff0000
+#define RG_TXPWRLVL_SET_I_MSK 0xff00ffff
+#define RG_TXPWRLVL_SET_SFT 16
+#define RG_TXPWRLVL_SET_HI 23
+#define RG_TXPWRLVL_SET_SZ 8
+#define RG_TXPWRLVL_SEL_MSK 0x01000000
+#define RG_TXPWRLVL_SEL_I_MSK 0xfeffffff
+#define RG_TXPWRLVL_SEL_SFT 24
+#define RG_TXPWRLVL_SEL_HI 24
+#define RG_TXPWRLVL_SEL_SZ 1
+#define RG_RF_BB_CLK_SEL_MSK 0x80000000
+#define RG_RF_BB_CLK_SEL_I_MSK 0x7fffffff
+#define RG_RF_BB_CLK_SEL_SFT 31
+#define RG_RF_BB_CLK_SEL_HI 31
+#define RG_RF_BB_CLK_SEL_SZ 1
+#define RG_PHY_MD_EN_MSK 0x00000001
+#define RG_PHY_MD_EN_I_MSK 0xfffffffe
+#define RG_PHY_MD_EN_SFT 0
+#define RG_PHY_MD_EN_HI 0
+#define RG_PHY_MD_EN_SZ 1
+#define RG_PHYRX_MD_EN_MSK 0x00000002
+#define RG_PHYRX_MD_EN_I_MSK 0xfffffffd
+#define RG_PHYRX_MD_EN_SFT 1
+#define RG_PHYRX_MD_EN_HI 1
+#define RG_PHYRX_MD_EN_SZ 1
+#define RG_PHYTX_MD_EN_MSK 0x00000004
+#define RG_PHYTX_MD_EN_I_MSK 0xfffffffb
+#define RG_PHYTX_MD_EN_SFT 2
+#define RG_PHYTX_MD_EN_HI 2
+#define RG_PHYTX_MD_EN_SZ 1
+#define RG_PHY11GN_MD_EN_MSK 0x00000008
+#define RG_PHY11GN_MD_EN_I_MSK 0xfffffff7
+#define RG_PHY11GN_MD_EN_SFT 3
+#define RG_PHY11GN_MD_EN_HI 3
+#define RG_PHY11GN_MD_EN_SZ 1
+#define RG_PHY11B_MD_EN_MSK 0x00000010
+#define RG_PHY11B_MD_EN_I_MSK 0xffffffef
+#define RG_PHY11B_MD_EN_SFT 4
+#define RG_PHY11B_MD_EN_HI 4
+#define RG_PHY11B_MD_EN_SZ 1
+#define RG_PHYRXFIFO_MD_EN_MSK 0x00000020
+#define RG_PHYRXFIFO_MD_EN_I_MSK 0xffffffdf
+#define RG_PHYRXFIFO_MD_EN_SFT 5
+#define RG_PHYRXFIFO_MD_EN_HI 5
+#define RG_PHYRXFIFO_MD_EN_SZ 1
+#define RG_PHYTXFIFO_MD_EN_MSK 0x00000040
+#define RG_PHYTXFIFO_MD_EN_I_MSK 0xffffffbf
+#define RG_PHYTXFIFO_MD_EN_SFT 6
+#define RG_PHYTXFIFO_MD_EN_HI 6
+#define RG_PHYTXFIFO_MD_EN_SZ 1
+#define RG_PHY11BGN_MD_EN_MSK 0x00000100
+#define RG_PHY11BGN_MD_EN_I_MSK 0xfffffeff
+#define RG_PHY11BGN_MD_EN_SFT 8
+#define RG_PHY11BGN_MD_EN_HI 8
+#define RG_PHY11BGN_MD_EN_SZ 1
+#define RG_FORCE_11GN_EN_MSK 0x00001000
+#define RG_FORCE_11GN_EN_I_MSK 0xffffefff
+#define RG_FORCE_11GN_EN_SFT 12
+#define RG_FORCE_11GN_EN_HI 12
+#define RG_FORCE_11GN_EN_SZ 1
+#define RG_FORCE_11B_EN_MSK 0x00002000
+#define RG_FORCE_11B_EN_I_MSK 0xffffdfff
+#define RG_FORCE_11B_EN_SFT 13
+#define RG_FORCE_11B_EN_HI 13
+#define RG_FORCE_11B_EN_SZ 1
+#define RG_FFT_MEM_CLK_EN_RX_MSK 0x00004000
+#define RG_FFT_MEM_CLK_EN_RX_I_MSK 0xffffbfff
+#define RG_FFT_MEM_CLK_EN_RX_SFT 14
+#define RG_FFT_MEM_CLK_EN_RX_HI 14
+#define RG_FFT_MEM_CLK_EN_RX_SZ 1
+#define RG_FFT_MEM_CLK_EN_TX_MSK 0x00008000
+#define RG_FFT_MEM_CLK_EN_TX_I_MSK 0xffff7fff
+#define RG_FFT_MEM_CLK_EN_TX_SFT 15
+#define RG_FFT_MEM_CLK_EN_TX_HI 15
+#define RG_FFT_MEM_CLK_EN_TX_SZ 1
+#define RG_PHY_IQ_TRIG_SEL_MSK 0x000f0000
+#define RG_PHY_IQ_TRIG_SEL_I_MSK 0xfff0ffff
+#define RG_PHY_IQ_TRIG_SEL_SFT 16
+#define RG_PHY_IQ_TRIG_SEL_HI 19
+#define RG_PHY_IQ_TRIG_SEL_SZ 4
+#define RG_SPECTRUM_FREQ_MSK 0x3ff00000
+#define RG_SPECTRUM_FREQ_I_MSK 0xc00fffff
+#define RG_SPECTRUM_FREQ_SFT 20
+#define RG_SPECTRUM_FREQ_HI 29
+#define RG_SPECTRUM_FREQ_SZ 10
+#define SVN_VERSION_MSK 0xffffffff
+#define SVN_VERSION_I_MSK 0x00000000
+#define SVN_VERSION_SFT 0
+#define SVN_VERSION_HI 31
+#define SVN_VERSION_SZ 32
+#define RG_LENGTH_MSK 0x0000ffff
+#define RG_LENGTH_I_MSK 0xffff0000
+#define RG_LENGTH_SFT 0
+#define RG_LENGTH_HI 15
+#define RG_LENGTH_SZ 16
+#define RG_PKT_MODE_MSK 0x00070000
+#define RG_PKT_MODE_I_MSK 0xfff8ffff
+#define RG_PKT_MODE_SFT 16
+#define RG_PKT_MODE_HI 18
+#define RG_PKT_MODE_SZ 3
+#define RG_CH_BW_MSK 0x00380000
+#define RG_CH_BW_I_MSK 0xffc7ffff
+#define RG_CH_BW_SFT 19
+#define RG_CH_BW_HI 21
+#define RG_CH_BW_SZ 3
+#define RG_PRM_MSK 0x00400000
+#define RG_PRM_I_MSK 0xffbfffff
+#define RG_PRM_SFT 22
+#define RG_PRM_HI 22
+#define RG_PRM_SZ 1
+#define RG_SHORTGI_MSK 0x00800000
+#define RG_SHORTGI_I_MSK 0xff7fffff
+#define RG_SHORTGI_SFT 23
+#define RG_SHORTGI_HI 23
+#define RG_SHORTGI_SZ 1
+#define RG_RATE_MSK 0x7f000000
+#define RG_RATE_I_MSK 0x80ffffff
+#define RG_RATE_SFT 24
+#define RG_RATE_HI 30
+#define RG_RATE_SZ 7
+#define RG_L_LENGTH_MSK 0x00000fff
+#define RG_L_LENGTH_I_MSK 0xfffff000
+#define RG_L_LENGTH_SFT 0
+#define RG_L_LENGTH_HI 11
+#define RG_L_LENGTH_SZ 12
+#define RG_L_RATE_MSK 0x00007000
+#define RG_L_RATE_I_MSK 0xffff8fff
+#define RG_L_RATE_SFT 12
+#define RG_L_RATE_HI 14
+#define RG_L_RATE_SZ 3
+#define RG_SERVICE_MSK 0xffff0000
+#define RG_SERVICE_I_MSK 0x0000ffff
+#define RG_SERVICE_SFT 16
+#define RG_SERVICE_HI 31
+#define RG_SERVICE_SZ 16
+#define RG_SMOOTHING_MSK 0x00000001
+#define RG_SMOOTHING_I_MSK 0xfffffffe
+#define RG_SMOOTHING_SFT 0
+#define RG_SMOOTHING_HI 0
+#define RG_SMOOTHING_SZ 1
+#define RG_NO_SOUND_MSK 0x00000002
+#define RG_NO_SOUND_I_MSK 0xfffffffd
+#define RG_NO_SOUND_SFT 1
+#define RG_NO_SOUND_HI 1
+#define RG_NO_SOUND_SZ 1
+#define RG_AGGREGATE_MSK 0x00000004
+#define RG_AGGREGATE_I_MSK 0xfffffffb
+#define RG_AGGREGATE_SFT 2
+#define RG_AGGREGATE_HI 2
+#define RG_AGGREGATE_SZ 1
+#define RG_STBC_MSK 0x00000018
+#define RG_STBC_I_MSK 0xffffffe7
+#define RG_STBC_SFT 3
+#define RG_STBC_HI 4
+#define RG_STBC_SZ 2
+#define RG_FEC_MSK 0x00000020
+#define RG_FEC_I_MSK 0xffffffdf
+#define RG_FEC_SFT 5
+#define RG_FEC_HI 5
+#define RG_FEC_SZ 1
+#define RG_N_ESS_MSK 0x000000c0
+#define RG_N_ESS_I_MSK 0xffffff3f
+#define RG_N_ESS_SFT 6
+#define RG_N_ESS_HI 7
+#define RG_N_ESS_SZ 2
+#define RG_TXPWRLVL_MSK 0x0000ff00
+#define RG_TXPWRLVL_I_MSK 0xffff00ff
+#define RG_TXPWRLVL_SFT 8
+#define RG_TXPWRLVL_HI 15
+#define RG_TXPWRLVL_SZ 8
+#define RG_TX_START_MSK 0x00000001
+#define RG_TX_START_I_MSK 0xfffffffe
+#define RG_TX_START_SFT 0
+#define RG_TX_START_HI 0
+#define RG_TX_START_SZ 1
+#define RG_IFS_TIME_MSK 0x000000fc
+#define RG_IFS_TIME_I_MSK 0xffffff03
+#define RG_IFS_TIME_SFT 2
+#define RG_IFS_TIME_HI 7
+#define RG_IFS_TIME_SZ 6
+#define RG_CONTINUOUS_DATA_MSK 0x00000100
+#define RG_CONTINUOUS_DATA_I_MSK 0xfffffeff
+#define RG_CONTINUOUS_DATA_SFT 8
+#define RG_CONTINUOUS_DATA_HI 8
+#define RG_CONTINUOUS_DATA_SZ 1
+#define RG_DATA_SEL_MSK 0x00000600
+#define RG_DATA_SEL_I_MSK 0xfffff9ff
+#define RG_DATA_SEL_SFT 9
+#define RG_DATA_SEL_HI 10
+#define RG_DATA_SEL_SZ 2
+#define RG_TX_D_MSK 0x00ff0000
+#define RG_TX_D_I_MSK 0xff00ffff
+#define RG_TX_D_SFT 16
+#define RG_TX_D_HI 23
+#define RG_TX_D_SZ 8
+#define RG_TX_CNT_TARGET_MSK 0xffffffff
+#define RG_TX_CNT_TARGET_I_MSK 0x00000000
+#define RG_TX_CNT_TARGET_SFT 0
+#define RG_TX_CNT_TARGET_HI 31
+#define RG_TX_CNT_TARGET_SZ 32
+#define RG_FFT_IFFT_MODE_MSK 0x000000c0
+#define RG_FFT_IFFT_MODE_I_MSK 0xffffff3f
+#define RG_FFT_IFFT_MODE_SFT 6
+#define RG_FFT_IFFT_MODE_HI 7
+#define RG_FFT_IFFT_MODE_SZ 2
+#define RG_DAC_DBG_MODE_MSK 0x00000100
+#define RG_DAC_DBG_MODE_I_MSK 0xfffffeff
+#define RG_DAC_DBG_MODE_SFT 8
+#define RG_DAC_DBG_MODE_HI 8
+#define RG_DAC_DBG_MODE_SZ 1
+#define RG_DAC_SGN_SWAP_MSK 0x00000200
+#define RG_DAC_SGN_SWAP_I_MSK 0xfffffdff
+#define RG_DAC_SGN_SWAP_SFT 9
+#define RG_DAC_SGN_SWAP_HI 9
+#define RG_DAC_SGN_SWAP_SZ 1
+#define RG_TXD_SEL_MSK 0x00000c00
+#define RG_TXD_SEL_I_MSK 0xfffff3ff
+#define RG_TXD_SEL_SFT 10
+#define RG_TXD_SEL_HI 11
+#define RG_TXD_SEL_SZ 2
+#define RG_UP8X_MSK 0x00ff0000
+#define RG_UP8X_I_MSK 0xff00ffff
+#define RG_UP8X_SFT 16
+#define RG_UP8X_HI 23
+#define RG_UP8X_SZ 8
+#define RG_IQ_DC_BYP_MSK 0x01000000
+#define RG_IQ_DC_BYP_I_MSK 0xfeffffff
+#define RG_IQ_DC_BYP_SFT 24
+#define RG_IQ_DC_BYP_HI 24
+#define RG_IQ_DC_BYP_SZ 1
+#define RG_IQ_DC_LEAKY_FACTOR_MSK 0x30000000
+#define RG_IQ_DC_LEAKY_FACTOR_I_MSK 0xcfffffff
+#define RG_IQ_DC_LEAKY_FACTOR_SFT 28
+#define RG_IQ_DC_LEAKY_FACTOR_HI 29
+#define RG_IQ_DC_LEAKY_FACTOR_SZ 2
+#define RG_DAC_DCEN_MSK 0x00000001
+#define RG_DAC_DCEN_I_MSK 0xfffffffe
+#define RG_DAC_DCEN_SFT 0
+#define RG_DAC_DCEN_HI 0
+#define RG_DAC_DCEN_SZ 1
+#define RG_DAC_DCQ_MSK 0x00003ff0
+#define RG_DAC_DCQ_I_MSK 0xffffc00f
+#define RG_DAC_DCQ_SFT 4
+#define RG_DAC_DCQ_HI 13
+#define RG_DAC_DCQ_SZ 10
+#define RG_DAC_DCI_MSK 0x03ff0000
+#define RG_DAC_DCI_I_MSK 0xfc00ffff
+#define RG_DAC_DCI_SFT 16
+#define RG_DAC_DCI_HI 25
+#define RG_DAC_DCI_SZ 10
+#define RG_PGA_REFDB_SAT_MSK 0x0000007f
+#define RG_PGA_REFDB_SAT_I_MSK 0xffffff80
+#define RG_PGA_REFDB_SAT_SFT 0
+#define RG_PGA_REFDB_SAT_HI 6
+#define RG_PGA_REFDB_SAT_SZ 7
+#define RG_PGA_REFDB_TOP_MSK 0x00007f00
+#define RG_PGA_REFDB_TOP_I_MSK 0xffff80ff
+#define RG_PGA_REFDB_TOP_SFT 8
+#define RG_PGA_REFDB_TOP_HI 14
+#define RG_PGA_REFDB_TOP_SZ 7
+#define RG_PGA_REF_UND_MSK 0x03ff0000
+#define RG_PGA_REF_UND_I_MSK 0xfc00ffff
+#define RG_PGA_REF_UND_SFT 16
+#define RG_PGA_REF_UND_HI 25
+#define RG_PGA_REF_UND_SZ 10
+#define RG_RF_REF_SAT_MSK 0xf0000000
+#define RG_RF_REF_SAT_I_MSK 0x0fffffff
+#define RG_RF_REF_SAT_SFT 28
+#define RG_RF_REF_SAT_HI 31
+#define RG_RF_REF_SAT_SZ 4
+#define RG_PGAGC_SET_MSK 0x0000000f
+#define RG_PGAGC_SET_I_MSK 0xfffffff0
+#define RG_PGAGC_SET_SFT 0
+#define RG_PGAGC_SET_HI 3
+#define RG_PGAGC_SET_SZ 4
+#define RG_PGAGC_OW_MSK 0x00000010
+#define RG_PGAGC_OW_I_MSK 0xffffffef
+#define RG_PGAGC_OW_SFT 4
+#define RG_PGAGC_OW_HI 4
+#define RG_PGAGC_OW_SZ 1
+#define RG_RFGC_SET_MSK 0x00000060
+#define RG_RFGC_SET_I_MSK 0xffffff9f
+#define RG_RFGC_SET_SFT 5
+#define RG_RFGC_SET_HI 6
+#define RG_RFGC_SET_SZ 2
+#define RG_RFGC_OW_MSK 0x00000080
+#define RG_RFGC_OW_I_MSK 0xffffff7f
+#define RG_RFGC_OW_SFT 7
+#define RG_RFGC_OW_HI 7
+#define RG_RFGC_OW_SZ 1
+#define RG_WAIT_T_RXAGC_MSK 0x00003f00
+#define RG_WAIT_T_RXAGC_I_MSK 0xffffc0ff
+#define RG_WAIT_T_RXAGC_SFT 8
+#define RG_WAIT_T_RXAGC_HI 13
+#define RG_WAIT_T_RXAGC_SZ 6
+#define RG_RXAGC_SET_MSK 0x00004000
+#define RG_RXAGC_SET_I_MSK 0xffffbfff
+#define RG_RXAGC_SET_SFT 14
+#define RG_RXAGC_SET_HI 14
+#define RG_RXAGC_SET_SZ 1
+#define RG_RXAGC_OW_MSK 0x00008000
+#define RG_RXAGC_OW_I_MSK 0xffff7fff
+#define RG_RXAGC_OW_SFT 15
+#define RG_RXAGC_OW_HI 15
+#define RG_RXAGC_OW_SZ 1
+#define RG_WAIT_T_FINAL_MSK 0x003f0000
+#define RG_WAIT_T_FINAL_I_MSK 0xffc0ffff
+#define RG_WAIT_T_FINAL_SFT 16
+#define RG_WAIT_T_FINAL_HI 21
+#define RG_WAIT_T_FINAL_SZ 6
+#define RG_WAIT_T_MSK 0x3f000000
+#define RG_WAIT_T_I_MSK 0xc0ffffff
+#define RG_WAIT_T_SFT 24
+#define RG_WAIT_T_HI 29
+#define RG_WAIT_T_SZ 6
+#define RG_ULG_PGA_SAT_PGA_GAIN_MSK 0x0000000f
+#define RG_ULG_PGA_SAT_PGA_GAIN_I_MSK 0xfffffff0
+#define RG_ULG_PGA_SAT_PGA_GAIN_SFT 0
+#define RG_ULG_PGA_SAT_PGA_GAIN_HI 3
+#define RG_ULG_PGA_SAT_PGA_GAIN_SZ 4
+#define RG_LG_PGA_UND_PGA_GAIN_MSK 0x000000f0
+#define RG_LG_PGA_UND_PGA_GAIN_I_MSK 0xffffff0f
+#define RG_LG_PGA_UND_PGA_GAIN_SFT 4
+#define RG_LG_PGA_UND_PGA_GAIN_HI 7
+#define RG_LG_PGA_UND_PGA_GAIN_SZ 4
+#define RG_LG_PGA_SAT_PGA_GAIN_MSK 0x00000f00
+#define RG_LG_PGA_SAT_PGA_GAIN_I_MSK 0xfffff0ff
+#define RG_LG_PGA_SAT_PGA_GAIN_SFT 8
+#define RG_LG_PGA_SAT_PGA_GAIN_HI 11
+#define RG_LG_PGA_SAT_PGA_GAIN_SZ 4
+#define RG_LG_RF_SAT_PGA_GAIN_MSK 0x0000f000
+#define RG_LG_RF_SAT_PGA_GAIN_I_MSK 0xffff0fff
+#define RG_LG_RF_SAT_PGA_GAIN_SFT 12
+#define RG_LG_RF_SAT_PGA_GAIN_HI 15
+#define RG_LG_RF_SAT_PGA_GAIN_SZ 4
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_MSK 0x000f0000
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_I_MSK 0xfff0ffff
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SFT 16
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_HI 19
+#define RG_MG_RF_SAT_PGANOREF_PGA_GAIN_SZ 4
+#define RG_HG_PGA_SAT2_PGA_GAIN_MSK 0x00f00000
+#define RG_HG_PGA_SAT2_PGA_GAIN_I_MSK 0xff0fffff
+#define RG_HG_PGA_SAT2_PGA_GAIN_SFT 20
+#define RG_HG_PGA_SAT2_PGA_GAIN_HI 23
+#define RG_HG_PGA_SAT2_PGA_GAIN_SZ 4
+#define RG_HG_PGA_SAT1_PGA_GAIN_MSK 0x0f000000
+#define RG_HG_PGA_SAT1_PGA_GAIN_I_MSK 0xf0ffffff
+#define RG_HG_PGA_SAT1_PGA_GAIN_SFT 24
+#define RG_HG_PGA_SAT1_PGA_GAIN_HI 27
+#define RG_HG_PGA_SAT1_PGA_GAIN_SZ 4
+#define RG_HG_RF_SAT_PGA_GAIN_MSK 0xf0000000
+#define RG_HG_RF_SAT_PGA_GAIN_I_MSK 0x0fffffff
+#define RG_HG_RF_SAT_PGA_GAIN_SFT 28
+#define RG_HG_RF_SAT_PGA_GAIN_HI 31
+#define RG_HG_RF_SAT_PGA_GAIN_SZ 4
+#define RG_MG_PGA_JB_TH_MSK 0x0000000f
+#define RG_MG_PGA_JB_TH_I_MSK 0xfffffff0
+#define RG_MG_PGA_JB_TH_SFT 0
+#define RG_MG_PGA_JB_TH_HI 3
+#define RG_MG_PGA_JB_TH_SZ 4
+#define RG_MA_PGA_LOW_TH_CNT_LMT_MSK 0x001f0000
+#define RG_MA_PGA_LOW_TH_CNT_LMT_I_MSK 0xffe0ffff
+#define RG_MA_PGA_LOW_TH_CNT_LMT_SFT 16
+#define RG_MA_PGA_LOW_TH_CNT_LMT_HI 20
+#define RG_MA_PGA_LOW_TH_CNT_LMT_SZ 5
+#define RG_WR_RFGC_INIT_SET_MSK 0x00600000
+#define RG_WR_RFGC_INIT_SET_I_MSK 0xff9fffff
+#define RG_WR_RFGC_INIT_SET_SFT 21
+#define RG_WR_RFGC_INIT_SET_HI 22
+#define RG_WR_RFGC_INIT_SET_SZ 2
+#define RG_WR_RFGC_INIT_EN_MSK 0x00800000
+#define RG_WR_RFGC_INIT_EN_I_MSK 0xff7fffff
+#define RG_WR_RFGC_INIT_EN_SFT 23
+#define RG_WR_RFGC_INIT_EN_HI 23
+#define RG_WR_RFGC_INIT_EN_SZ 1
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_MSK 0x1f000000
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_I_MSK 0xe0ffffff
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_SFT 24
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_HI 28
+#define RG_MA_PGA_HIGH_TH_CNT_LMT_SZ 5
+#define RG_AGC_THRESHOLD_MSK 0x00003fff
+#define RG_AGC_THRESHOLD_I_MSK 0xffffc000
+#define RG_AGC_THRESHOLD_SFT 0
+#define RG_AGC_THRESHOLD_HI 13
+#define RG_AGC_THRESHOLD_SZ 14
+#define RG_ACI_POINT_CNT_LMT_11B_MSK 0x007f0000
+#define RG_ACI_POINT_CNT_LMT_11B_I_MSK 0xff80ffff
+#define RG_ACI_POINT_CNT_LMT_11B_SFT 16
+#define RG_ACI_POINT_CNT_LMT_11B_HI 22
+#define RG_ACI_POINT_CNT_LMT_11B_SZ 7
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_MSK 0x03000000
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_I_MSK 0xfcffffff
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SFT 24
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_HI 25
+#define RG_ACI_DAGC_LEAKY_FACTOR_11B_SZ 2
+#define RG_WR_ACI_GAIN_INI_SEL_11B_MSK 0x000000ff
+#define RG_WR_ACI_GAIN_INI_SEL_11B_I_MSK 0xffffff00
+#define RG_WR_ACI_GAIN_INI_SEL_11B_SFT 0
+#define RG_WR_ACI_GAIN_INI_SEL_11B_HI 7
+#define RG_WR_ACI_GAIN_INI_SEL_11B_SZ 8
+#define RG_WR_ACI_GAIN_SEL_11B_MSK 0x0000ff00
+#define RG_WR_ACI_GAIN_SEL_11B_I_MSK 0xffff00ff
+#define RG_WR_ACI_GAIN_SEL_11B_SFT 8
+#define RG_WR_ACI_GAIN_SEL_11B_HI 15
+#define RG_WR_ACI_GAIN_SEL_11B_SZ 8
+#define RG_ACI_DAGC_SET_VALUE_11B_MSK 0x007f0000
+#define RG_ACI_DAGC_SET_VALUE_11B_I_MSK 0xff80ffff
+#define RG_ACI_DAGC_SET_VALUE_11B_SFT 16
+#define RG_ACI_DAGC_SET_VALUE_11B_HI 22
+#define RG_ACI_DAGC_SET_VALUE_11B_SZ 7
+#define RG_WR_ACI_GAIN_OW_11B_MSK 0x80000000
+#define RG_WR_ACI_GAIN_OW_11B_I_MSK 0x7fffffff
+#define RG_WR_ACI_GAIN_OW_11B_SFT 31
+#define RG_WR_ACI_GAIN_OW_11B_HI 31
+#define RG_WR_ACI_GAIN_OW_11B_SZ 1
+#define RG_ACI_POINT_CNT_LMT_11GN_MSK 0x000000ff
+#define RG_ACI_POINT_CNT_LMT_11GN_I_MSK 0xffffff00
+#define RG_ACI_POINT_CNT_LMT_11GN_SFT 0
+#define RG_ACI_POINT_CNT_LMT_11GN_HI 7
+#define RG_ACI_POINT_CNT_LMT_11GN_SZ 8
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_MSK 0x00000300
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_I_MSK 0xfffffcff
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SFT 8
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_HI 9
+#define RG_ACI_DAGC_LEAKY_FACTOR_11GN_SZ 2
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_MSK 0xff000000
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_I_MSK 0x00ffffff
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SFT 24
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_HI 31
+#define RG_ACI_DAGC_DONE_CNT_LMT_11GN_SZ 8
+#define RG_ACI_DAGC_SET_VALUE_11GN_MSK 0x0000007f
+#define RG_ACI_DAGC_SET_VALUE_11GN_I_MSK 0xffffff80
+#define RG_ACI_DAGC_SET_VALUE_11GN_SFT 0
+#define RG_ACI_DAGC_SET_VALUE_11GN_HI 6
+#define RG_ACI_DAGC_SET_VALUE_11GN_SZ 7
+#define RG_ACI_GAIN_INI_VAL_11GN_MSK 0x0000ff00
+#define RG_ACI_GAIN_INI_VAL_11GN_I_MSK 0xffff00ff
+#define RG_ACI_GAIN_INI_VAL_11GN_SFT 8
+#define RG_ACI_GAIN_INI_VAL_11GN_HI 15
+#define RG_ACI_GAIN_INI_VAL_11GN_SZ 8
+#define RG_ACI_GAIN_OW_VAL_11GN_MSK 0x00ff0000
+#define RG_ACI_GAIN_OW_VAL_11GN_I_MSK 0xff00ffff
+#define RG_ACI_GAIN_OW_VAL_11GN_SFT 16
+#define RG_ACI_GAIN_OW_VAL_11GN_HI 23
+#define RG_ACI_GAIN_OW_VAL_11GN_SZ 8
+#define RG_ACI_GAIN_OW_11GN_MSK 0x80000000
+#define RG_ACI_GAIN_OW_11GN_I_MSK 0x7fffffff
+#define RG_ACI_GAIN_OW_11GN_SFT 31
+#define RG_ACI_GAIN_OW_11GN_HI 31
+#define RG_ACI_GAIN_OW_11GN_SZ 1
+#define RO_CCA_PWR_MA_11GN_MSK 0x0000007f
+#define RO_CCA_PWR_MA_11GN_I_MSK 0xffffff80
+#define RO_CCA_PWR_MA_11GN_SFT 0
+#define RO_CCA_PWR_MA_11GN_HI 6
+#define RO_CCA_PWR_MA_11GN_SZ 7
+#define RO_ED_STATE_MSK 0x00008000
+#define RO_ED_STATE_I_MSK 0xffff7fff
+#define RO_ED_STATE_SFT 15
+#define RO_ED_STATE_HI 15
+#define RO_ED_STATE_SZ 1
+#define RO_CCA_PWR_MA_11B_MSK 0x007f0000
+#define RO_CCA_PWR_MA_11B_I_MSK 0xff80ffff
+#define RO_CCA_PWR_MA_11B_SFT 16
+#define RO_CCA_PWR_MA_11B_HI 22
+#define RO_CCA_PWR_MA_11B_SZ 7
+#define RO_PGA_PWR_FF1_MSK 0x00003fff
+#define RO_PGA_PWR_FF1_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF1_SFT 0
+#define RO_PGA_PWR_FF1_HI 13
+#define RO_PGA_PWR_FF1_SZ 14
+#define RO_RF_PWR_FF1_MSK 0x000f0000
+#define RO_RF_PWR_FF1_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF1_SFT 16
+#define RO_RF_PWR_FF1_HI 19
+#define RO_RF_PWR_FF1_SZ 4
+#define RO_PGAGC_FF1_MSK 0x0f000000
+#define RO_PGAGC_FF1_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF1_SFT 24
+#define RO_PGAGC_FF1_HI 27
+#define RO_PGAGC_FF1_SZ 4
+#define RO_RFGC_FF1_MSK 0x30000000
+#define RO_RFGC_FF1_I_MSK 0xcfffffff
+#define RO_RFGC_FF1_SFT 28
+#define RO_RFGC_FF1_HI 29
+#define RO_RFGC_FF1_SZ 2
+#define RO_PGA_PWR_FF2_MSK 0x00003fff
+#define RO_PGA_PWR_FF2_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF2_SFT 0
+#define RO_PGA_PWR_FF2_HI 13
+#define RO_PGA_PWR_FF2_SZ 14
+#define RO_RF_PWR_FF2_MSK 0x000f0000
+#define RO_RF_PWR_FF2_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF2_SFT 16
+#define RO_RF_PWR_FF2_HI 19
+#define RO_RF_PWR_FF2_SZ 4
+#define RO_PGAGC_FF2_MSK 0x0f000000
+#define RO_PGAGC_FF2_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF2_SFT 24
+#define RO_PGAGC_FF2_HI 27
+#define RO_PGAGC_FF2_SZ 4
+#define RO_RFGC_FF2_MSK 0x30000000
+#define RO_RFGC_FF2_I_MSK 0xcfffffff
+#define RO_RFGC_FF2_SFT 28
+#define RO_RFGC_FF2_HI 29
+#define RO_RFGC_FF2_SZ 2
+#define RO_PGA_PWR_FF3_MSK 0x00003fff
+#define RO_PGA_PWR_FF3_I_MSK 0xffffc000
+#define RO_PGA_PWR_FF3_SFT 0
+#define RO_PGA_PWR_FF3_HI 13
+#define RO_PGA_PWR_FF3_SZ 14
+#define RO_RF_PWR_FF3_MSK 0x000f0000
+#define RO_RF_PWR_FF3_I_MSK 0xfff0ffff
+#define RO_RF_PWR_FF3_SFT 16
+#define RO_RF_PWR_FF3_HI 19
+#define RO_RF_PWR_FF3_SZ 4
+#define RO_PGAGC_FF3_MSK 0x0f000000
+#define RO_PGAGC_FF3_I_MSK 0xf0ffffff
+#define RO_PGAGC_FF3_SFT 24
+#define RO_PGAGC_FF3_HI 27
+#define RO_PGAGC_FF3_SZ 4
+#define RO_RFGC_FF3_MSK 0x30000000
+#define RO_RFGC_FF3_I_MSK 0xcfffffff
+#define RO_RFGC_FF3_SFT 28
+#define RO_RFGC_FF3_HI 29
+#define RO_RFGC_FF3_SZ 2
+#define RG_TX_DES_RATE_MSK 0x0000001f
+#define RG_TX_DES_RATE_I_MSK 0xffffffe0
+#define RG_TX_DES_RATE_SFT 0
+#define RG_TX_DES_RATE_HI 4
+#define RG_TX_DES_RATE_SZ 5
+#define RG_TX_DES_MODE_MSK 0x00001f00
+#define RG_TX_DES_MODE_I_MSK 0xffffe0ff
+#define RG_TX_DES_MODE_SFT 8
+#define RG_TX_DES_MODE_HI 12
+#define RG_TX_DES_MODE_SZ 5
+#define RG_TX_DES_LEN_LO_MSK 0x001f0000
+#define RG_TX_DES_LEN_LO_I_MSK 0xffe0ffff
+#define RG_TX_DES_LEN_LO_SFT 16
+#define RG_TX_DES_LEN_LO_HI 20
+#define RG_TX_DES_LEN_LO_SZ 5
+#define RG_TX_DES_LEN_UP_MSK 0x1f000000
+#define RG_TX_DES_LEN_UP_I_MSK 0xe0ffffff
+#define RG_TX_DES_LEN_UP_SFT 24
+#define RG_TX_DES_LEN_UP_HI 28
+#define RG_TX_DES_LEN_UP_SZ 5
+#define RG_TX_DES_SRVC_UP_MSK 0x0000001f
+#define RG_TX_DES_SRVC_UP_I_MSK 0xffffffe0
+#define RG_TX_DES_SRVC_UP_SFT 0
+#define RG_TX_DES_SRVC_UP_HI 4
+#define RG_TX_DES_SRVC_UP_SZ 5
+#define RG_TX_DES_L_LEN_LO_MSK 0x00001f00
+#define RG_TX_DES_L_LEN_LO_I_MSK 0xffffe0ff
+#define RG_TX_DES_L_LEN_LO_SFT 8
+#define RG_TX_DES_L_LEN_LO_HI 12
+#define RG_TX_DES_L_LEN_LO_SZ 5
+#define RG_TX_DES_L_LEN_UP_MSK 0x001f0000
+#define RG_TX_DES_L_LEN_UP_I_MSK 0xffe0ffff
+#define RG_TX_DES_L_LEN_UP_SFT 16
+#define RG_TX_DES_L_LEN_UP_HI 20
+#define RG_TX_DES_L_LEN_UP_SZ 5
+#define RG_TX_DES_TYPE_MSK 0x1f000000
+#define RG_TX_DES_TYPE_I_MSK 0xe0ffffff
+#define RG_TX_DES_TYPE_SFT 24
+#define RG_TX_DES_TYPE_HI 28
+#define RG_TX_DES_TYPE_SZ 5
+#define RG_TX_DES_L_LEN_UP_COMB_MSK 0x00000001
+#define RG_TX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
+#define RG_TX_DES_L_LEN_UP_COMB_SFT 0
+#define RG_TX_DES_L_LEN_UP_COMB_HI 0
+#define RG_TX_DES_L_LEN_UP_COMB_SZ 1
+#define RG_TX_DES_TYPE_COMB_MSK 0x00000010
+#define RG_TX_DES_TYPE_COMB_I_MSK 0xffffffef
+#define RG_TX_DES_TYPE_COMB_SFT 4
+#define RG_TX_DES_TYPE_COMB_HI 4
+#define RG_TX_DES_TYPE_COMB_SZ 1
+#define RG_TX_DES_RATE_COMB_MSK 0x00000100
+#define RG_TX_DES_RATE_COMB_I_MSK 0xfffffeff
+#define RG_TX_DES_RATE_COMB_SFT 8
+#define RG_TX_DES_RATE_COMB_HI 8
+#define RG_TX_DES_RATE_COMB_SZ 1
+#define RG_TX_DES_MODE_COMB_MSK 0x00001000
+#define RG_TX_DES_MODE_COMB_I_MSK 0xffffefff
+#define RG_TX_DES_MODE_COMB_SFT 12
+#define RG_TX_DES_MODE_COMB_HI 12
+#define RG_TX_DES_MODE_COMB_SZ 1
+#define RG_TX_DES_PWRLVL_MSK 0x001f0000
+#define RG_TX_DES_PWRLVL_I_MSK 0xffe0ffff
+#define RG_TX_DES_PWRLVL_SFT 16
+#define RG_TX_DES_PWRLVL_HI 20
+#define RG_TX_DES_PWRLVL_SZ 5
+#define RG_TX_DES_SRVC_LO_MSK 0x1f000000
+#define RG_TX_DES_SRVC_LO_I_MSK 0xe0ffffff
+#define RG_TX_DES_SRVC_LO_SFT 24
+#define RG_TX_DES_SRVC_LO_HI 28
+#define RG_TX_DES_SRVC_LO_SZ 5
+#define RG_RX_DES_RATE_MSK 0x0000003f
+#define RG_RX_DES_RATE_I_MSK 0xffffffc0
+#define RG_RX_DES_RATE_SFT 0
+#define RG_RX_DES_RATE_HI 5
+#define RG_RX_DES_RATE_SZ 6
+#define RG_RX_DES_MODE_MSK 0x00003f00
+#define RG_RX_DES_MODE_I_MSK 0xffffc0ff
+#define RG_RX_DES_MODE_SFT 8
+#define RG_RX_DES_MODE_HI 13
+#define RG_RX_DES_MODE_SZ 6
+#define RG_RX_DES_LEN_LO_MSK 0x003f0000
+#define RG_RX_DES_LEN_LO_I_MSK 0xffc0ffff
+#define RG_RX_DES_LEN_LO_SFT 16
+#define RG_RX_DES_LEN_LO_HI 21
+#define RG_RX_DES_LEN_LO_SZ 6
+#define RG_RX_DES_LEN_UP_MSK 0x3f000000
+#define RG_RX_DES_LEN_UP_I_MSK 0xc0ffffff
+#define RG_RX_DES_LEN_UP_SFT 24
+#define RG_RX_DES_LEN_UP_HI 29
+#define RG_RX_DES_LEN_UP_SZ 6
+#define RG_RX_DES_SRVC_UP_MSK 0x0000003f
+#define RG_RX_DES_SRVC_UP_I_MSK 0xffffffc0
+#define RG_RX_DES_SRVC_UP_SFT 0
+#define RG_RX_DES_SRVC_UP_HI 5
+#define RG_RX_DES_SRVC_UP_SZ 6
+#define RG_RX_DES_L_LEN_LO_MSK 0x00003f00
+#define RG_RX_DES_L_LEN_LO_I_MSK 0xffffc0ff
+#define RG_RX_DES_L_LEN_LO_SFT 8
+#define RG_RX_DES_L_LEN_LO_HI 13
+#define RG_RX_DES_L_LEN_LO_SZ 6
+#define RG_RX_DES_L_LEN_UP_MSK 0x003f0000
+#define RG_RX_DES_L_LEN_UP_I_MSK 0xffc0ffff
+#define RG_RX_DES_L_LEN_UP_SFT 16
+#define RG_RX_DES_L_LEN_UP_HI 21
+#define RG_RX_DES_L_LEN_UP_SZ 6
+#define RG_RX_DES_TYPE_MSK 0x3f000000
+#define RG_RX_DES_TYPE_I_MSK 0xc0ffffff
+#define RG_RX_DES_TYPE_SFT 24
+#define RG_RX_DES_TYPE_HI 29
+#define RG_RX_DES_TYPE_SZ 6
+#define RG_RX_DES_L_LEN_UP_COMB_MSK 0x00000001
+#define RG_RX_DES_L_LEN_UP_COMB_I_MSK 0xfffffffe
+#define RG_RX_DES_L_LEN_UP_COMB_SFT 0
+#define RG_RX_DES_L_LEN_UP_COMB_HI 0
+#define RG_RX_DES_L_LEN_UP_COMB_SZ 1
+#define RG_RX_DES_TYPE_COMB_MSK 0x00000010
+#define RG_RX_DES_TYPE_COMB_I_MSK 0xffffffef
+#define RG_RX_DES_TYPE_COMB_SFT 4
+#define RG_RX_DES_TYPE_COMB_HI 4
+#define RG_RX_DES_TYPE_COMB_SZ 1
+#define RG_RX_DES_RATE_COMB_MSK 0x00000100
+#define RG_RX_DES_RATE_COMB_I_MSK 0xfffffeff
+#define RG_RX_DES_RATE_COMB_SFT 8
+#define RG_RX_DES_RATE_COMB_HI 8
+#define RG_RX_DES_RATE_COMB_SZ 1
+#define RG_RX_DES_MODE_COMB_MSK 0x00001000
+#define RG_RX_DES_MODE_COMB_I_MSK 0xffffefff
+#define RG_RX_DES_MODE_COMB_SFT 12
+#define RG_RX_DES_MODE_COMB_HI 12
+#define RG_RX_DES_MODE_COMB_SZ 1
+#define RG_RX_DES_SNR_MSK 0x000f0000
+#define RG_RX_DES_SNR_I_MSK 0xfff0ffff
+#define RG_RX_DES_SNR_SFT 16
+#define RG_RX_DES_SNR_HI 19
+#define RG_RX_DES_SNR_SZ 4
+#define RG_RX_DES_RCPI_MSK 0x00f00000
+#define RG_RX_DES_RCPI_I_MSK 0xff0fffff
+#define RG_RX_DES_RCPI_SFT 20
+#define RG_RX_DES_RCPI_HI 23
+#define RG_RX_DES_RCPI_SZ 4
+#define RG_RX_DES_SRVC_LO_MSK 0x3f000000
+#define RG_RX_DES_SRVC_LO_I_MSK 0xc0ffffff
+#define RG_RX_DES_SRVC_LO_SFT 24
+#define RG_RX_DES_SRVC_LO_HI 29
+#define RG_RX_DES_SRVC_LO_SZ 6
+#define RO_TX_DES_EXCP_RATE_CNT_MSK 0x000000ff
+#define RO_TX_DES_EXCP_RATE_CNT_I_MSK 0xffffff00
+#define RO_TX_DES_EXCP_RATE_CNT_SFT 0
+#define RO_TX_DES_EXCP_RATE_CNT_HI 7
+#define RO_TX_DES_EXCP_RATE_CNT_SZ 8
+#define RO_TX_DES_EXCP_CH_BW_CNT_MSK 0x0000ff00
+#define RO_TX_DES_EXCP_CH_BW_CNT_I_MSK 0xffff00ff
+#define RO_TX_DES_EXCP_CH_BW_CNT_SFT 8
+#define RO_TX_DES_EXCP_CH_BW_CNT_HI 15
+#define RO_TX_DES_EXCP_CH_BW_CNT_SZ 8
+#define RO_TX_DES_EXCP_MODE_CNT_MSK 0x00ff0000
+#define RO_TX_DES_EXCP_MODE_CNT_I_MSK 0xff00ffff
+#define RO_TX_DES_EXCP_MODE_CNT_SFT 16
+#define RO_TX_DES_EXCP_MODE_CNT_HI 23
+#define RO_TX_DES_EXCP_MODE_CNT_SZ 8
+#define RG_TX_DES_EXCP_RATE_DEFAULT_MSK 0x07000000
+#define RG_TX_DES_EXCP_RATE_DEFAULT_I_MSK 0xf8ffffff
+#define RG_TX_DES_EXCP_RATE_DEFAULT_SFT 24
+#define RG_TX_DES_EXCP_RATE_DEFAULT_HI 26
+#define RG_TX_DES_EXCP_RATE_DEFAULT_SZ 3
+#define RG_TX_DES_EXCP_MODE_DEFAULT_MSK 0x70000000
+#define RG_TX_DES_EXCP_MODE_DEFAULT_I_MSK 0x8fffffff
+#define RG_TX_DES_EXCP_MODE_DEFAULT_SFT 28
+#define RG_TX_DES_EXCP_MODE_DEFAULT_HI 30
+#define RG_TX_DES_EXCP_MODE_DEFAULT_SZ 3
+#define RG_TX_DES_EXCP_CLR_MSK 0x80000000
+#define RG_TX_DES_EXCP_CLR_I_MSK 0x7fffffff
+#define RG_TX_DES_EXCP_CLR_SFT 31
+#define RG_TX_DES_EXCP_CLR_HI 31
+#define RG_TX_DES_EXCP_CLR_SZ 1
+#define RG_TX_DES_ACK_WIDTH_MSK 0x00000001
+#define RG_TX_DES_ACK_WIDTH_I_MSK 0xfffffffe
+#define RG_TX_DES_ACK_WIDTH_SFT 0
+#define RG_TX_DES_ACK_WIDTH_HI 0
+#define RG_TX_DES_ACK_WIDTH_SZ 1
+#define RG_TX_DES_ACK_PRD_MSK 0x0000000e
+#define RG_TX_DES_ACK_PRD_I_MSK 0xfffffff1
+#define RG_TX_DES_ACK_PRD_SFT 1
+#define RG_TX_DES_ACK_PRD_HI 3
+#define RG_TX_DES_ACK_PRD_SZ 3
+#define RG_RX_DES_SNR_GN_MSK 0x003f0000
+#define RG_RX_DES_SNR_GN_I_MSK 0xffc0ffff
+#define RG_RX_DES_SNR_GN_SFT 16
+#define RG_RX_DES_SNR_GN_HI 21
+#define RG_RX_DES_SNR_GN_SZ 6
+#define RG_RX_DES_RCPI_GN_MSK 0x3f000000
+#define RG_RX_DES_RCPI_GN_I_MSK 0xc0ffffff
+#define RG_RX_DES_RCPI_GN_SFT 24
+#define RG_RX_DES_RCPI_GN_HI 29
+#define RG_RX_DES_RCPI_GN_SZ 6
+#define RG_TST_TBUS_SEL_MSK 0x0000000f
+#define RG_TST_TBUS_SEL_I_MSK 0xfffffff0
+#define RG_TST_TBUS_SEL_SFT 0
+#define RG_TST_TBUS_SEL_HI 3
+#define RG_TST_TBUS_SEL_SZ 4
+#define RG_RSSI_OFFSET_MSK 0x00ff0000
+#define RG_RSSI_OFFSET_I_MSK 0xff00ffff
+#define RG_RSSI_OFFSET_SFT 16
+#define RG_RSSI_OFFSET_HI 23
+#define RG_RSSI_OFFSET_SZ 8
+#define RG_RSSI_INV_MSK 0x01000000
+#define RG_RSSI_INV_I_MSK 0xfeffffff
+#define RG_RSSI_INV_SFT 24
+#define RG_RSSI_INV_HI 24
+#define RG_RSSI_INV_SZ 1
+#define RG_TST_ADC_ON_MSK 0x40000000
+#define RG_TST_ADC_ON_I_MSK 0xbfffffff
+#define RG_TST_ADC_ON_SFT 30
+#define RG_TST_ADC_ON_HI 30
+#define RG_TST_ADC_ON_SZ 1
+#define RG_TST_EXT_GAIN_MSK 0x80000000
+#define RG_TST_EXT_GAIN_I_MSK 0x7fffffff
+#define RG_TST_EXT_GAIN_SFT 31
+#define RG_TST_EXT_GAIN_HI 31
+#define RG_TST_EXT_GAIN_SZ 1
+#define RG_DAC_Q_SET_MSK 0x000003ff
+#define RG_DAC_Q_SET_I_MSK 0xfffffc00
+#define RG_DAC_Q_SET_SFT 0
+#define RG_DAC_Q_SET_HI 9
+#define RG_DAC_Q_SET_SZ 10
+#define RG_DAC_I_SET_MSK 0x003ff000
+#define RG_DAC_I_SET_I_MSK 0xffc00fff
+#define RG_DAC_I_SET_SFT 12
+#define RG_DAC_I_SET_HI 21
+#define RG_DAC_I_SET_SZ 10
+#define RG_DAC_EN_MAN_MSK 0x10000000
+#define RG_DAC_EN_MAN_I_MSK 0xefffffff
+#define RG_DAC_EN_MAN_SFT 28
+#define RG_DAC_EN_MAN_HI 28
+#define RG_DAC_EN_MAN_SZ 1
+#define RG_IQC_FFT_EN_MSK 0x20000000
+#define RG_IQC_FFT_EN_I_MSK 0xdfffffff
+#define RG_IQC_FFT_EN_SFT 29
+#define RG_IQC_FFT_EN_HI 29
+#define RG_IQC_FFT_EN_SZ 1
+#define RG_DAC_MAN_Q_EN_MSK 0x40000000
+#define RG_DAC_MAN_Q_EN_I_MSK 0xbfffffff
+#define RG_DAC_MAN_Q_EN_SFT 30
+#define RG_DAC_MAN_Q_EN_HI 30
+#define RG_DAC_MAN_Q_EN_SZ 1
+#define RG_DAC_MAN_I_EN_MSK 0x80000000
+#define RG_DAC_MAN_I_EN_I_MSK 0x7fffffff
+#define RG_DAC_MAN_I_EN_SFT 31
+#define RG_DAC_MAN_I_EN_HI 31
+#define RG_DAC_MAN_I_EN_SZ 1
+#define RO_MRX_EN_CNT_MSK 0x0000ffff
+#define RO_MRX_EN_CNT_I_MSK 0xffff0000
+#define RO_MRX_EN_CNT_SFT 0
+#define RO_MRX_EN_CNT_HI 15
+#define RO_MRX_EN_CNT_SZ 16
+#define RG_MRX_EN_CNT_RST_N_MSK 0x80000000
+#define RG_MRX_EN_CNT_RST_N_I_MSK 0x7fffffff
+#define RG_MRX_EN_CNT_RST_N_SFT 31
+#define RG_MRX_EN_CNT_RST_N_HI 31
+#define RG_MRX_EN_CNT_RST_N_SZ 1
+#define RG_PA_RISE_TIME_MSK 0x000000ff
+#define RG_PA_RISE_TIME_I_MSK 0xffffff00
+#define RG_PA_RISE_TIME_SFT 0
+#define RG_PA_RISE_TIME_HI 7
+#define RG_PA_RISE_TIME_SZ 8
+#define RG_RFTX_RISE_TIME_MSK 0x0000ff00
+#define RG_RFTX_RISE_TIME_I_MSK 0xffff00ff
+#define RG_RFTX_RISE_TIME_SFT 8
+#define RG_RFTX_RISE_TIME_HI 15
+#define RG_RFTX_RISE_TIME_SZ 8
+#define RG_DAC_RISE_TIME_MSK 0x00ff0000
+#define RG_DAC_RISE_TIME_I_MSK 0xff00ffff
+#define RG_DAC_RISE_TIME_SFT 16
+#define RG_DAC_RISE_TIME_HI 23
+#define RG_DAC_RISE_TIME_SZ 8
+#define RG_SW_RISE_TIME_MSK 0xff000000
+#define RG_SW_RISE_TIME_I_MSK 0x00ffffff
+#define RG_SW_RISE_TIME_SFT 24
+#define RG_SW_RISE_TIME_HI 31
+#define RG_SW_RISE_TIME_SZ 8
+#define RG_PA_FALL_TIME_MSK 0x000000ff
+#define RG_PA_FALL_TIME_I_MSK 0xffffff00
+#define RG_PA_FALL_TIME_SFT 0
+#define RG_PA_FALL_TIME_HI 7
+#define RG_PA_FALL_TIME_SZ 8
+#define RG_RFTX_FALL_TIME_MSK 0x0000ff00
+#define RG_RFTX_FALL_TIME_I_MSK 0xffff00ff
+#define RG_RFTX_FALL_TIME_SFT 8
+#define RG_RFTX_FALL_TIME_HI 15
+#define RG_RFTX_FALL_TIME_SZ 8
+#define RG_DAC_FALL_TIME_MSK 0x00ff0000
+#define RG_DAC_FALL_TIME_I_MSK 0xff00ffff
+#define RG_DAC_FALL_TIME_SFT 16
+#define RG_DAC_FALL_TIME_HI 23
+#define RG_DAC_FALL_TIME_SZ 8
+#define RG_SW_FALL_TIME_MSK 0xff000000
+#define RG_SW_FALL_TIME_I_MSK 0x00ffffff
+#define RG_SW_FALL_TIME_SFT 24
+#define RG_SW_FALL_TIME_HI 31
+#define RG_SW_FALL_TIME_SZ 8
+#define RG_ANT_SW_0_MSK 0x00000007
+#define RG_ANT_SW_0_I_MSK 0xfffffff8
+#define RG_ANT_SW_0_SFT 0
+#define RG_ANT_SW_0_HI 2
+#define RG_ANT_SW_0_SZ 3
+#define RG_ANT_SW_1_MSK 0x00000038
+#define RG_ANT_SW_1_I_MSK 0xffffffc7
+#define RG_ANT_SW_1_SFT 3
+#define RG_ANT_SW_1_HI 5
+#define RG_ANT_SW_1_SZ 3
+#define RG_MTX_LEN_LOWER_TH_0_MSK 0x00001fff
+#define RG_MTX_LEN_LOWER_TH_0_I_MSK 0xffffe000
+#define RG_MTX_LEN_LOWER_TH_0_SFT 0
+#define RG_MTX_LEN_LOWER_TH_0_HI 12
+#define RG_MTX_LEN_LOWER_TH_0_SZ 13
+#define RG_MTX_LEN_UPPER_TH_0_MSK 0x1fff0000
+#define RG_MTX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
+#define RG_MTX_LEN_UPPER_TH_0_SFT 16
+#define RG_MTX_LEN_UPPER_TH_0_HI 28
+#define RG_MTX_LEN_UPPER_TH_0_SZ 13
+#define RG_MTX_LEN_CNT_EN_0_MSK 0x80000000
+#define RG_MTX_LEN_CNT_EN_0_I_MSK 0x7fffffff
+#define RG_MTX_LEN_CNT_EN_0_SFT 31
+#define RG_MTX_LEN_CNT_EN_0_HI 31
+#define RG_MTX_LEN_CNT_EN_0_SZ 1
+#define RG_MTX_LEN_LOWER_TH_1_MSK 0x00001fff
+#define RG_MTX_LEN_LOWER_TH_1_I_MSK 0xffffe000
+#define RG_MTX_LEN_LOWER_TH_1_SFT 0
+#define RG_MTX_LEN_LOWER_TH_1_HI 12
+#define RG_MTX_LEN_LOWER_TH_1_SZ 13
+#define RG_MTX_LEN_UPPER_TH_1_MSK 0x1fff0000
+#define RG_MTX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
+#define RG_MTX_LEN_UPPER_TH_1_SFT 16
+#define RG_MTX_LEN_UPPER_TH_1_HI 28
+#define RG_MTX_LEN_UPPER_TH_1_SZ 13
+#define RG_MTX_LEN_CNT_EN_1_MSK 0x80000000
+#define RG_MTX_LEN_CNT_EN_1_I_MSK 0x7fffffff
+#define RG_MTX_LEN_CNT_EN_1_SFT 31
+#define RG_MTX_LEN_CNT_EN_1_HI 31
+#define RG_MTX_LEN_CNT_EN_1_SZ 1
+#define RG_MRX_LEN_LOWER_TH_0_MSK 0x00001fff
+#define RG_MRX_LEN_LOWER_TH_0_I_MSK 0xffffe000
+#define RG_MRX_LEN_LOWER_TH_0_SFT 0
+#define RG_MRX_LEN_LOWER_TH_0_HI 12
+#define RG_MRX_LEN_LOWER_TH_0_SZ 13
+#define RG_MRX_LEN_UPPER_TH_0_MSK 0x1fff0000
+#define RG_MRX_LEN_UPPER_TH_0_I_MSK 0xe000ffff
+#define RG_MRX_LEN_UPPER_TH_0_SFT 16
+#define RG_MRX_LEN_UPPER_TH_0_HI 28
+#define RG_MRX_LEN_UPPER_TH_0_SZ 13
+#define RG_MRX_LEN_CNT_EN_0_MSK 0x80000000
+#define RG_MRX_LEN_CNT_EN_0_I_MSK 0x7fffffff
+#define RG_MRX_LEN_CNT_EN_0_SFT 31
+#define RG_MRX_LEN_CNT_EN_0_HI 31
+#define RG_MRX_LEN_CNT_EN_0_SZ 1
+#define RG_MRX_LEN_LOWER_TH_1_MSK 0x00001fff
+#define RG_MRX_LEN_LOWER_TH_1_I_MSK 0xffffe000
+#define RG_MRX_LEN_LOWER_TH_1_SFT 0
+#define RG_MRX_LEN_LOWER_TH_1_HI 12
+#define RG_MRX_LEN_LOWER_TH_1_SZ 13
+#define RG_MRX_LEN_UPPER_TH_1_MSK 0x1fff0000
+#define RG_MRX_LEN_UPPER_TH_1_I_MSK 0xe000ffff
+#define RG_MRX_LEN_UPPER_TH_1_SFT 16
+#define RG_MRX_LEN_UPPER_TH_1_HI 28
+#define RG_MRX_LEN_UPPER_TH_1_SZ 13
+#define RG_MRX_LEN_CNT_EN_1_MSK 0x80000000
+#define RG_MRX_LEN_CNT_EN_1_I_MSK 0x7fffffff
+#define RG_MRX_LEN_CNT_EN_1_SFT 31
+#define RG_MRX_LEN_CNT_EN_1_HI 31
+#define RG_MRX_LEN_CNT_EN_1_SZ 1
+#define RO_MTX_LEN_CNT_1_MSK 0x0000ffff
+#define RO_MTX_LEN_CNT_1_I_MSK 0xffff0000
+#define RO_MTX_LEN_CNT_1_SFT 0
+#define RO_MTX_LEN_CNT_1_HI 15
+#define RO_MTX_LEN_CNT_1_SZ 16
+#define RO_MTX_LEN_CNT_0_MSK 0xffff0000
+#define RO_MTX_LEN_CNT_0_I_MSK 0x0000ffff
+#define RO_MTX_LEN_CNT_0_SFT 16
+#define RO_MTX_LEN_CNT_0_HI 31
+#define RO_MTX_LEN_CNT_0_SZ 16
+#define RO_MRX_LEN_CNT_1_MSK 0x0000ffff
+#define RO_MRX_LEN_CNT_1_I_MSK 0xffff0000
+#define RO_MRX_LEN_CNT_1_SFT 0
+#define RO_MRX_LEN_CNT_1_HI 15
+#define RO_MRX_LEN_CNT_1_SZ 16
+#define RO_MRX_LEN_CNT_0_MSK 0xffff0000
+#define RO_MRX_LEN_CNT_0_I_MSK 0x0000ffff
+#define RO_MRX_LEN_CNT_0_SFT 16
+#define RO_MRX_LEN_CNT_0_HI 31
+#define RO_MRX_LEN_CNT_0_SZ 16
+#define RG_MODE_REG_IN_16_MSK 0x0000ffff
+#define RG_MODE_REG_IN_16_I_MSK 0xffff0000
+#define RG_MODE_REG_IN_16_SFT 0
+#define RG_MODE_REG_IN_16_HI 15
+#define RG_MODE_REG_IN_16_SZ 16
+#define RG_PARALLEL_DR_16_MSK 0x00100000
+#define RG_PARALLEL_DR_16_I_MSK 0xffefffff
+#define RG_PARALLEL_DR_16_SFT 20
+#define RG_PARALLEL_DR_16_HI 20
+#define RG_PARALLEL_DR_16_SZ 1
+#define RG_MBRUN_16_MSK 0x01000000
+#define RG_MBRUN_16_I_MSK 0xfeffffff
+#define RG_MBRUN_16_SFT 24
+#define RG_MBRUN_16_HI 24
+#define RG_MBRUN_16_SZ 1
+#define RG_SHIFT_DR_16_MSK 0x10000000
+#define RG_SHIFT_DR_16_I_MSK 0xefffffff
+#define RG_SHIFT_DR_16_SFT 28
+#define RG_SHIFT_DR_16_HI 28
+#define RG_SHIFT_DR_16_SZ 1
+#define RG_MODE_REG_SI_16_MSK 0x20000000
+#define RG_MODE_REG_SI_16_I_MSK 0xdfffffff
+#define RG_MODE_REG_SI_16_SFT 29
+#define RG_MODE_REG_SI_16_HI 29
+#define RG_MODE_REG_SI_16_SZ 1
+#define RG_SIMULATION_MODE_16_MSK 0x40000000
+#define RG_SIMULATION_MODE_16_I_MSK 0xbfffffff
+#define RG_SIMULATION_MODE_16_SFT 30
+#define RG_SIMULATION_MODE_16_HI 30
+#define RG_SIMULATION_MODE_16_SZ 1
+#define RG_DBIST_MODE_16_MSK 0x80000000
+#define RG_DBIST_MODE_16_I_MSK 0x7fffffff
+#define RG_DBIST_MODE_16_SFT 31
+#define RG_DBIST_MODE_16_HI 31
+#define RG_DBIST_MODE_16_SZ 1
+#define RO_MODE_REG_OUT_16_MSK 0x0000ffff
+#define RO_MODE_REG_OUT_16_I_MSK 0xffff0000
+#define RO_MODE_REG_OUT_16_SFT 0
+#define RO_MODE_REG_OUT_16_HI 15
+#define RO_MODE_REG_OUT_16_SZ 16
+#define RO_MODE_REG_SO_16_MSK 0x01000000
+#define RO_MODE_REG_SO_16_I_MSK 0xfeffffff
+#define RO_MODE_REG_SO_16_SFT 24
+#define RO_MODE_REG_SO_16_HI 24
+#define RO_MODE_REG_SO_16_SZ 1
+#define RO_MONITOR_BUS_16_MSK 0x0007ffff
+#define RO_MONITOR_BUS_16_I_MSK 0xfff80000
+#define RO_MONITOR_BUS_16_SFT 0
+#define RO_MONITOR_BUS_16_HI 18
+#define RO_MONITOR_BUS_16_SZ 19
+#define RG_MRX_TYPE_1_MSK 0x000000ff
+#define RG_MRX_TYPE_1_I_MSK 0xffffff00
+#define RG_MRX_TYPE_1_SFT 0
+#define RG_MRX_TYPE_1_HI 7
+#define RG_MRX_TYPE_1_SZ 8
+#define RG_MRX_TYPE_0_MSK 0x0000ff00
+#define RG_MRX_TYPE_0_I_MSK 0xffff00ff
+#define RG_MRX_TYPE_0_SFT 8
+#define RG_MRX_TYPE_0_HI 15
+#define RG_MRX_TYPE_0_SZ 8
+#define RG_MTX_TYPE_1_MSK 0x00ff0000
+#define RG_MTX_TYPE_1_I_MSK 0xff00ffff
+#define RG_MTX_TYPE_1_SFT 16
+#define RG_MTX_TYPE_1_HI 23
+#define RG_MTX_TYPE_1_SZ 8
+#define RG_MTX_TYPE_0_MSK 0xff000000
+#define RG_MTX_TYPE_0_I_MSK 0x00ffffff
+#define RG_MTX_TYPE_0_SFT 24
+#define RG_MTX_TYPE_0_HI 31
+#define RG_MTX_TYPE_0_SZ 8
+#define RO_MTX_TYPE_CNT_1_MSK 0x0000ffff
+#define RO_MTX_TYPE_CNT_1_I_MSK 0xffff0000
+#define RO_MTX_TYPE_CNT_1_SFT 0
+#define RO_MTX_TYPE_CNT_1_HI 15
+#define RO_MTX_TYPE_CNT_1_SZ 16
+#define RO_MTX_TYPE_CNT_0_MSK 0xffff0000
+#define RO_MTX_TYPE_CNT_0_I_MSK 0x0000ffff
+#define RO_MTX_TYPE_CNT_0_SFT 16
+#define RO_MTX_TYPE_CNT_0_HI 31
+#define RO_MTX_TYPE_CNT_0_SZ 16
+#define RO_MRX_TYPE_CNT_1_MSK 0x0000ffff
+#define RO_MRX_TYPE_CNT_1_I_MSK 0xffff0000
+#define RO_MRX_TYPE_CNT_1_SFT 0
+#define RO_MRX_TYPE_CNT_1_HI 15
+#define RO_MRX_TYPE_CNT_1_SZ 16
+#define RO_MRX_TYPE_CNT_0_MSK 0xffff0000
+#define RO_MRX_TYPE_CNT_0_I_MSK 0x0000ffff
+#define RO_MRX_TYPE_CNT_0_SFT 16
+#define RO_MRX_TYPE_CNT_0_HI 31
+#define RO_MRX_TYPE_CNT_0_SZ 16
+#define RG_HB_COEF0_MSK 0x00000fff
+#define RG_HB_COEF0_I_MSK 0xfffff000
+#define RG_HB_COEF0_SFT 0
+#define RG_HB_COEF0_HI 11
+#define RG_HB_COEF0_SZ 12
+#define RG_HB_COEF1_MSK 0x0fff0000
+#define RG_HB_COEF1_I_MSK 0xf000ffff
+#define RG_HB_COEF1_SFT 16
+#define RG_HB_COEF1_HI 27
+#define RG_HB_COEF1_SZ 12
+#define RG_HB_COEF2_MSK 0x00000fff
+#define RG_HB_COEF2_I_MSK 0xfffff000
+#define RG_HB_COEF2_SFT 0
+#define RG_HB_COEF2_HI 11
+#define RG_HB_COEF2_SZ 12
+#define RG_HB_COEF3_MSK 0x0fff0000
+#define RG_HB_COEF3_I_MSK 0xf000ffff
+#define RG_HB_COEF3_SFT 16
+#define RG_HB_COEF3_HI 27
+#define RG_HB_COEF3_SZ 12
+#define RG_HB_COEF4_MSK 0x00000fff
+#define RG_HB_COEF4_I_MSK 0xfffff000
+#define RG_HB_COEF4_SFT 0
+#define RG_HB_COEF4_HI 11
+#define RG_HB_COEF4_SZ 12
+#define RO_TBUS_O_MSK 0x000fffff
+#define RO_TBUS_O_I_MSK 0xfff00000
+#define RO_TBUS_O_SFT 0
+#define RO_TBUS_O_HI 19
+#define RO_TBUS_O_SZ 20
+#define RG_LPF4_00_MSK 0x00001fff
+#define RG_LPF4_00_I_MSK 0xffffe000
+#define RG_LPF4_00_SFT 0
+#define RG_LPF4_00_HI 12
+#define RG_LPF4_00_SZ 13
+#define RG_LPF4_01_MSK 0x00001fff
+#define RG_LPF4_01_I_MSK 0xffffe000
+#define RG_LPF4_01_SFT 0
+#define RG_LPF4_01_HI 12
+#define RG_LPF4_01_SZ 13
+#define RG_LPF4_02_MSK 0x00001fff
+#define RG_LPF4_02_I_MSK 0xffffe000
+#define RG_LPF4_02_SFT 0
+#define RG_LPF4_02_HI 12
+#define RG_LPF4_02_SZ 13
+#define RG_LPF4_03_MSK 0x00001fff
+#define RG_LPF4_03_I_MSK 0xffffe000
+#define RG_LPF4_03_SFT 0
+#define RG_LPF4_03_HI 12
+#define RG_LPF4_03_SZ 13
+#define RG_LPF4_04_MSK 0x00001fff
+#define RG_LPF4_04_I_MSK 0xffffe000
+#define RG_LPF4_04_SFT 0
+#define RG_LPF4_04_HI 12
+#define RG_LPF4_04_SZ 13
+#define RG_LPF4_05_MSK 0x00001fff
+#define RG_LPF4_05_I_MSK 0xffffe000
+#define RG_LPF4_05_SFT 0
+#define RG_LPF4_05_HI 12
+#define RG_LPF4_05_SZ 13
+#define RG_LPF4_06_MSK 0x00001fff
+#define RG_LPF4_06_I_MSK 0xffffe000
+#define RG_LPF4_06_SFT 0
+#define RG_LPF4_06_HI 12
+#define RG_LPF4_06_SZ 13
+#define RG_LPF4_07_MSK 0x00001fff
+#define RG_LPF4_07_I_MSK 0xffffe000
+#define RG_LPF4_07_SFT 0
+#define RG_LPF4_07_HI 12
+#define RG_LPF4_07_SZ 13
+#define RG_LPF4_08_MSK 0x00001fff
+#define RG_LPF4_08_I_MSK 0xffffe000
+#define RG_LPF4_08_SFT 0
+#define RG_LPF4_08_HI 12
+#define RG_LPF4_08_SZ 13
+#define RG_LPF4_09_MSK 0x00001fff
+#define RG_LPF4_09_I_MSK 0xffffe000
+#define RG_LPF4_09_SFT 0
+#define RG_LPF4_09_HI 12
+#define RG_LPF4_09_SZ 13
+#define RG_LPF4_10_MSK 0x00001fff
+#define RG_LPF4_10_I_MSK 0xffffe000
+#define RG_LPF4_10_SFT 0
+#define RG_LPF4_10_HI 12
+#define RG_LPF4_10_SZ 13
+#define RG_LPF4_11_MSK 0x00001fff
+#define RG_LPF4_11_I_MSK 0xffffe000
+#define RG_LPF4_11_SFT 0
+#define RG_LPF4_11_HI 12
+#define RG_LPF4_11_SZ 13
+#define RG_LPF4_12_MSK 0x00001fff
+#define RG_LPF4_12_I_MSK 0xffffe000
+#define RG_LPF4_12_SFT 0
+#define RG_LPF4_12_HI 12
+#define RG_LPF4_12_SZ 13
+#define RG_LPF4_13_MSK 0x00001fff
+#define RG_LPF4_13_I_MSK 0xffffe000
+#define RG_LPF4_13_SFT 0
+#define RG_LPF4_13_HI 12
+#define RG_LPF4_13_SZ 13
+#define RG_LPF4_14_MSK 0x00001fff
+#define RG_LPF4_14_I_MSK 0xffffe000
+#define RG_LPF4_14_SFT 0
+#define RG_LPF4_14_HI 12
+#define RG_LPF4_14_SZ 13
+#define RG_LPF4_15_MSK 0x00001fff
+#define RG_LPF4_15_I_MSK 0xffffe000
+#define RG_LPF4_15_SFT 0
+#define RG_LPF4_15_HI 12
+#define RG_LPF4_15_SZ 13
+#define RG_LPF4_16_MSK 0x00001fff
+#define RG_LPF4_16_I_MSK 0xffffe000
+#define RG_LPF4_16_SFT 0
+#define RG_LPF4_16_HI 12
+#define RG_LPF4_16_SZ 13
+#define RG_LPF4_17_MSK 0x00001fff
+#define RG_LPF4_17_I_MSK 0xffffe000
+#define RG_LPF4_17_SFT 0
+#define RG_LPF4_17_HI 12
+#define RG_LPF4_17_SZ 13
+#define RG_LPF4_18_MSK 0x00001fff
+#define RG_LPF4_18_I_MSK 0xffffe000
+#define RG_LPF4_18_SFT 0
+#define RG_LPF4_18_HI 12
+#define RG_LPF4_18_SZ 13
+#define RG_LPF4_19_MSK 0x00001fff
+#define RG_LPF4_19_I_MSK 0xffffe000
+#define RG_LPF4_19_SFT 0
+#define RG_LPF4_19_HI 12
+#define RG_LPF4_19_SZ 13
+#define RG_LPF4_20_MSK 0x00001fff
+#define RG_LPF4_20_I_MSK 0xffffe000
+#define RG_LPF4_20_SFT 0
+#define RG_LPF4_20_HI 12
+#define RG_LPF4_20_SZ 13
+#define RG_LPF4_21_MSK 0x00001fff
+#define RG_LPF4_21_I_MSK 0xffffe000
+#define RG_LPF4_21_SFT 0
+#define RG_LPF4_21_HI 12
+#define RG_LPF4_21_SZ 13
+#define RG_LPF4_22_MSK 0x00001fff
+#define RG_LPF4_22_I_MSK 0xffffe000
+#define RG_LPF4_22_SFT 0
+#define RG_LPF4_22_HI 12
+#define RG_LPF4_22_SZ 13
+#define RG_LPF4_23_MSK 0x00001fff
+#define RG_LPF4_23_I_MSK 0xffffe000
+#define RG_LPF4_23_SFT 0
+#define RG_LPF4_23_HI 12
+#define RG_LPF4_23_SZ 13
+#define RG_LPF4_24_MSK 0x00001fff
+#define RG_LPF4_24_I_MSK 0xffffe000
+#define RG_LPF4_24_SFT 0
+#define RG_LPF4_24_HI 12
+#define RG_LPF4_24_SZ 13
+#define RG_LPF4_25_MSK 0x00001fff
+#define RG_LPF4_25_I_MSK 0xffffe000
+#define RG_LPF4_25_SFT 0
+#define RG_LPF4_25_HI 12
+#define RG_LPF4_25_SZ 13
+#define RG_LPF4_26_MSK 0x00001fff
+#define RG_LPF4_26_I_MSK 0xffffe000
+#define RG_LPF4_26_SFT 0
+#define RG_LPF4_26_HI 12
+#define RG_LPF4_26_SZ 13
+#define RG_LPF4_27_MSK 0x00001fff
+#define RG_LPF4_27_I_MSK 0xffffe000
+#define RG_LPF4_27_SFT 0
+#define RG_LPF4_27_HI 12
+#define RG_LPF4_27_SZ 13
+#define RG_LPF4_28_MSK 0x00001fff
+#define RG_LPF4_28_I_MSK 0xffffe000
+#define RG_LPF4_28_SFT 0
+#define RG_LPF4_28_HI 12
+#define RG_LPF4_28_SZ 13
+#define RG_LPF4_29_MSK 0x00001fff
+#define RG_LPF4_29_I_MSK 0xffffe000
+#define RG_LPF4_29_SFT 0
+#define RG_LPF4_29_HI 12
+#define RG_LPF4_29_SZ 13
+#define RG_LPF4_30_MSK 0x00001fff
+#define RG_LPF4_30_I_MSK 0xffffe000
+#define RG_LPF4_30_SFT 0
+#define RG_LPF4_30_HI 12
+#define RG_LPF4_30_SZ 13
+#define RG_LPF4_31_MSK 0x00001fff
+#define RG_LPF4_31_I_MSK 0xffffe000
+#define RG_LPF4_31_SFT 0
+#define RG_LPF4_31_HI 12
+#define RG_LPF4_31_SZ 13
+#define RG_LPF4_32_MSK 0x00001fff
+#define RG_LPF4_32_I_MSK 0xffffe000
+#define RG_LPF4_32_SFT 0
+#define RG_LPF4_32_HI 12
+#define RG_LPF4_32_SZ 13
+#define RG_LPF4_33_MSK 0x00001fff
+#define RG_LPF4_33_I_MSK 0xffffe000
+#define RG_LPF4_33_SFT 0
+#define RG_LPF4_33_HI 12
+#define RG_LPF4_33_SZ 13
+#define RG_LPF4_34_MSK 0x00001fff
+#define RG_LPF4_34_I_MSK 0xffffe000
+#define RG_LPF4_34_SFT 0
+#define RG_LPF4_34_HI 12
+#define RG_LPF4_34_SZ 13
+#define RG_LPF4_35_MSK 0x00001fff
+#define RG_LPF4_35_I_MSK 0xffffe000
+#define RG_LPF4_35_SFT 0
+#define RG_LPF4_35_HI 12
+#define RG_LPF4_35_SZ 13
+#define RG_LPF4_36_MSK 0x00001fff
+#define RG_LPF4_36_I_MSK 0xffffe000
+#define RG_LPF4_36_SFT 0
+#define RG_LPF4_36_HI 12
+#define RG_LPF4_36_SZ 13
+#define RG_LPF4_37_MSK 0x00001fff
+#define RG_LPF4_37_I_MSK 0xffffe000
+#define RG_LPF4_37_SFT 0
+#define RG_LPF4_37_HI 12
+#define RG_LPF4_37_SZ 13
+#define RG_LPF4_38_MSK 0x00001fff
+#define RG_LPF4_38_I_MSK 0xffffe000
+#define RG_LPF4_38_SFT 0
+#define RG_LPF4_38_HI 12
+#define RG_LPF4_38_SZ 13
+#define RG_LPF4_39_MSK 0x00001fff
+#define RG_LPF4_39_I_MSK 0xffffe000
+#define RG_LPF4_39_SFT 0
+#define RG_LPF4_39_HI 12
+#define RG_LPF4_39_SZ 13
+#define RG_LPF4_40_MSK 0x00001fff
+#define RG_LPF4_40_I_MSK 0xffffe000
+#define RG_LPF4_40_SFT 0
+#define RG_LPF4_40_HI 12
+#define RG_LPF4_40_SZ 13
+#define RG_BP_SMB_MSK 0x00002000
+#define RG_BP_SMB_I_MSK 0xffffdfff
+#define RG_BP_SMB_SFT 13
+#define RG_BP_SMB_HI 13
+#define RG_BP_SMB_SZ 1
+#define RG_EN_SRVC_MSK 0x00004000
+#define RG_EN_SRVC_I_MSK 0xffffbfff
+#define RG_EN_SRVC_SFT 14
+#define RG_EN_SRVC_HI 14
+#define RG_EN_SRVC_SZ 1
+#define RG_DES_SPD_MSK 0x00030000
+#define RG_DES_SPD_I_MSK 0xfffcffff
+#define RG_DES_SPD_SFT 16
+#define RG_DES_SPD_HI 17
+#define RG_DES_SPD_SZ 2
+#define RG_BB_11B_RISE_TIME_MSK 0x000000ff
+#define RG_BB_11B_RISE_TIME_I_MSK 0xffffff00
+#define RG_BB_11B_RISE_TIME_SFT 0
+#define RG_BB_11B_RISE_TIME_HI 7
+#define RG_BB_11B_RISE_TIME_SZ 8
+#define RG_BB_11B_FALL_TIME_MSK 0x0000ff00
+#define RG_BB_11B_FALL_TIME_I_MSK 0xffff00ff
+#define RG_BB_11B_FALL_TIME_SFT 8
+#define RG_BB_11B_FALL_TIME_HI 15
+#define RG_BB_11B_FALL_TIME_SZ 8
+#define RG_WR_TX_EN_CNT_RST_N_MSK 0x00000001
+#define RG_WR_TX_EN_CNT_RST_N_I_MSK 0xfffffffe
+#define RG_WR_TX_EN_CNT_RST_N_SFT 0
+#define RG_WR_TX_EN_CNT_RST_N_HI 0
+#define RG_WR_TX_EN_CNT_RST_N_SZ 1
+#define RO_TX_EN_CNT_MSK 0x0000ffff
+#define RO_TX_EN_CNT_I_MSK 0xffff0000
+#define RO_TX_EN_CNT_SFT 0
+#define RO_TX_EN_CNT_HI 15
+#define RO_TX_EN_CNT_SZ 16
+#define RO_TX_CNT_MSK 0xffffffff
+#define RO_TX_CNT_I_MSK 0x00000000
+#define RO_TX_CNT_SFT 0
+#define RO_TX_CNT_HI 31
+#define RO_TX_CNT_SZ 32
+#define RG_POS_DES_11B_L_EXT_MSK 0x0000000f
+#define RG_POS_DES_11B_L_EXT_I_MSK 0xfffffff0
+#define RG_POS_DES_11B_L_EXT_SFT 0
+#define RG_POS_DES_11B_L_EXT_HI 3
+#define RG_POS_DES_11B_L_EXT_SZ 4
+#define RG_PRE_DES_11B_DLY_MSK 0x000000f0
+#define RG_PRE_DES_11B_DLY_I_MSK 0xffffff0f
+#define RG_PRE_DES_11B_DLY_SFT 4
+#define RG_PRE_DES_11B_DLY_HI 7
+#define RG_PRE_DES_11B_DLY_SZ 4
+#define RG_CNT_CCA_LMT_MSK 0x000f0000
+#define RG_CNT_CCA_LMT_I_MSK 0xfff0ffff
+#define RG_CNT_CCA_LMT_SFT 16
+#define RG_CNT_CCA_LMT_HI 19
+#define RG_CNT_CCA_LMT_SZ 4
+#define RG_BYPASS_DESCRAMBLER_MSK 0x20000000
+#define RG_BYPASS_DESCRAMBLER_I_MSK 0xdfffffff
+#define RG_BYPASS_DESCRAMBLER_SFT 29
+#define RG_BYPASS_DESCRAMBLER_HI 29
+#define RG_BYPASS_DESCRAMBLER_SZ 1
+#define RG_BYPASS_AGC_MSK 0x80000000
+#define RG_BYPASS_AGC_I_MSK 0x7fffffff
+#define RG_BYPASS_AGC_SFT 31
+#define RG_BYPASS_AGC_HI 31
+#define RG_BYPASS_AGC_SZ 1
+#define RG_CCA_BIT_CNT_LMT_RX_MSK 0x000000f0
+#define RG_CCA_BIT_CNT_LMT_RX_I_MSK 0xffffff0f
+#define RG_CCA_BIT_CNT_LMT_RX_SFT 4
+#define RG_CCA_BIT_CNT_LMT_RX_HI 7
+#define RG_CCA_BIT_CNT_LMT_RX_SZ 4
+#define RG_CCA_SCALE_BF_MSK 0x007f0000
+#define RG_CCA_SCALE_BF_I_MSK 0xff80ffff
+#define RG_CCA_SCALE_BF_SFT 16
+#define RG_CCA_SCALE_BF_HI 22
+#define RG_CCA_SCALE_BF_SZ 7
+#define RG_PEAK_IDX_CNT_SEL_MSK 0x30000000
+#define RG_PEAK_IDX_CNT_SEL_I_MSK 0xcfffffff
+#define RG_PEAK_IDX_CNT_SEL_SFT 28
+#define RG_PEAK_IDX_CNT_SEL_HI 29
+#define RG_PEAK_IDX_CNT_SEL_SZ 2
+#define RG_TR_KI_T2_MSK 0x00000007
+#define RG_TR_KI_T2_I_MSK 0xfffffff8
+#define RG_TR_KI_T2_SFT 0
+#define RG_TR_KI_T2_HI 2
+#define RG_TR_KI_T2_SZ 3
+#define RG_TR_KP_T2_MSK 0x00000070
+#define RG_TR_KP_T2_I_MSK 0xffffff8f
+#define RG_TR_KP_T2_SFT 4
+#define RG_TR_KP_T2_HI 6
+#define RG_TR_KP_T2_SZ 3
+#define RG_TR_KI_T1_MSK 0x00000700
+#define RG_TR_KI_T1_I_MSK 0xfffff8ff
+#define RG_TR_KI_T1_SFT 8
+#define RG_TR_KI_T1_HI 10
+#define RG_TR_KI_T1_SZ 3
+#define RG_TR_KP_T1_MSK 0x00007000
+#define RG_TR_KP_T1_I_MSK 0xffff8fff
+#define RG_TR_KP_T1_SFT 12
+#define RG_TR_KP_T1_HI 14
+#define RG_TR_KP_T1_SZ 3
+#define RG_CR_KI_T1_MSK 0x00070000
+#define RG_CR_KI_T1_I_MSK 0xfff8ffff
+#define RG_CR_KI_T1_SFT 16
+#define RG_CR_KI_T1_HI 18
+#define RG_CR_KI_T1_SZ 3
+#define RG_CR_KP_T1_MSK 0x00700000
+#define RG_CR_KP_T1_I_MSK 0xff8fffff
+#define RG_CR_KP_T1_SFT 20
+#define RG_CR_KP_T1_HI 22
+#define RG_CR_KP_T1_SZ 3
+#define RG_CHIP_CNT_SLICER_MSK 0x0000001f
+#define RG_CHIP_CNT_SLICER_I_MSK 0xffffffe0
+#define RG_CHIP_CNT_SLICER_SFT 0
+#define RG_CHIP_CNT_SLICER_HI 4
+#define RG_CHIP_CNT_SLICER_SZ 5
+#define RG_CE_T4_CNT_LMT_MSK 0x0000ff00
+#define RG_CE_T4_CNT_LMT_I_MSK 0xffff00ff
+#define RG_CE_T4_CNT_LMT_SFT 8
+#define RG_CE_T4_CNT_LMT_HI 15
+#define RG_CE_T4_CNT_LMT_SZ 8
+#define RG_CE_T3_CNT_LMT_MSK 0x00ff0000
+#define RG_CE_T3_CNT_LMT_I_MSK 0xff00ffff
+#define RG_CE_T3_CNT_LMT_SFT 16
+#define RG_CE_T3_CNT_LMT_HI 23
+#define RG_CE_T3_CNT_LMT_SZ 8
+#define RG_CE_T2_CNT_LMT_MSK 0xff000000
+#define RG_CE_T2_CNT_LMT_I_MSK 0x00ffffff
+#define RG_CE_T2_CNT_LMT_SFT 24
+#define RG_CE_T2_CNT_LMT_HI 31
+#define RG_CE_T2_CNT_LMT_SZ 8
+#define RG_CE_MU_T1_MSK 0x00000007
+#define RG_CE_MU_T1_I_MSK 0xfffffff8
+#define RG_CE_MU_T1_SFT 0
+#define RG_CE_MU_T1_HI 2
+#define RG_CE_MU_T1_SZ 3
+#define RG_CE_DLY_SEL_MSK 0x003f0000
+#define RG_CE_DLY_SEL_I_MSK 0xffc0ffff
+#define RG_CE_DLY_SEL_SFT 16
+#define RG_CE_DLY_SEL_HI 21
+#define RG_CE_DLY_SEL_SZ 6
+#define RG_CE_MU_T8_MSK 0x00000007
+#define RG_CE_MU_T8_I_MSK 0xfffffff8
+#define RG_CE_MU_T8_SFT 0
+#define RG_CE_MU_T8_HI 2
+#define RG_CE_MU_T8_SZ 3
+#define RG_CE_MU_T7_MSK 0x00000070
+#define RG_CE_MU_T7_I_MSK 0xffffff8f
+#define RG_CE_MU_T7_SFT 4
+#define RG_CE_MU_T7_HI 6
+#define RG_CE_MU_T7_SZ 3
+#define RG_CE_MU_T6_MSK 0x00000700
+#define RG_CE_MU_T6_I_MSK 0xfffff8ff
+#define RG_CE_MU_T6_SFT 8
+#define RG_CE_MU_T6_HI 10
+#define RG_CE_MU_T6_SZ 3
+#define RG_CE_MU_T5_MSK 0x00007000
+#define RG_CE_MU_T5_I_MSK 0xffff8fff
+#define RG_CE_MU_T5_SFT 12
+#define RG_CE_MU_T5_HI 14
+#define RG_CE_MU_T5_SZ 3
+#define RG_CE_MU_T4_MSK 0x00070000
+#define RG_CE_MU_T4_I_MSK 0xfff8ffff
+#define RG_CE_MU_T4_SFT 16
+#define RG_CE_MU_T4_HI 18
+#define RG_CE_MU_T4_SZ 3
+#define RG_CE_MU_T3_MSK 0x00700000
+#define RG_CE_MU_T3_I_MSK 0xff8fffff
+#define RG_CE_MU_T3_SFT 20
+#define RG_CE_MU_T3_HI 22
+#define RG_CE_MU_T3_SZ 3
+#define RG_CE_MU_T2_MSK 0x07000000
+#define RG_CE_MU_T2_I_MSK 0xf8ffffff
+#define RG_CE_MU_T2_SFT 24
+#define RG_CE_MU_T2_HI 26
+#define RG_CE_MU_T2_SZ 3
+#define RG_EQ_MU_FB_T2_MSK 0x0000000f
+#define RG_EQ_MU_FB_T2_I_MSK 0xfffffff0
+#define RG_EQ_MU_FB_T2_SFT 0
+#define RG_EQ_MU_FB_T2_HI 3
+#define RG_EQ_MU_FB_T2_SZ 4
+#define RG_EQ_MU_FF_T2_MSK 0x000000f0
+#define RG_EQ_MU_FF_T2_I_MSK 0xffffff0f
+#define RG_EQ_MU_FF_T2_SFT 4
+#define RG_EQ_MU_FF_T2_HI 7
+#define RG_EQ_MU_FF_T2_SZ 4
+#define RG_EQ_MU_FB_T1_MSK 0x000f0000
+#define RG_EQ_MU_FB_T1_I_MSK 0xfff0ffff
+#define RG_EQ_MU_FB_T1_SFT 16
+#define RG_EQ_MU_FB_T1_HI 19
+#define RG_EQ_MU_FB_T1_SZ 4
+#define RG_EQ_MU_FF_T1_MSK 0x00f00000
+#define RG_EQ_MU_FF_T1_I_MSK 0xff0fffff
+#define RG_EQ_MU_FF_T1_SFT 20
+#define RG_EQ_MU_FF_T1_HI 23
+#define RG_EQ_MU_FF_T1_SZ 4
+#define RG_EQ_MU_FB_T4_MSK 0x0000000f
+#define RG_EQ_MU_FB_T4_I_MSK 0xfffffff0
+#define RG_EQ_MU_FB_T4_SFT 0
+#define RG_EQ_MU_FB_T4_HI 3
+#define RG_EQ_MU_FB_T4_SZ 4
+#define RG_EQ_MU_FF_T4_MSK 0x000000f0
+#define RG_EQ_MU_FF_T4_I_MSK 0xffffff0f
+#define RG_EQ_MU_FF_T4_SFT 4
+#define RG_EQ_MU_FF_T4_HI 7
+#define RG_EQ_MU_FF_T4_SZ 4
+#define RG_EQ_MU_FB_T3_MSK 0x000f0000
+#define RG_EQ_MU_FB_T3_I_MSK 0xfff0ffff
+#define RG_EQ_MU_FB_T3_SFT 16
+#define RG_EQ_MU_FB_T3_HI 19
+#define RG_EQ_MU_FB_T3_SZ 4
+#define RG_EQ_MU_FF_T3_MSK 0x00f00000
+#define RG_EQ_MU_FF_T3_I_MSK 0xff0fffff
+#define RG_EQ_MU_FF_T3_SFT 20
+#define RG_EQ_MU_FF_T3_HI 23
+#define RG_EQ_MU_FF_T3_SZ 4
+#define RG_EQ_KI_T2_MSK 0x00000700
+#define RG_EQ_KI_T2_I_MSK 0xfffff8ff
+#define RG_EQ_KI_T2_SFT 8
+#define RG_EQ_KI_T2_HI 10
+#define RG_EQ_KI_T2_SZ 3
+#define RG_EQ_KP_T2_MSK 0x00007000
+#define RG_EQ_KP_T2_I_MSK 0xffff8fff
+#define RG_EQ_KP_T2_SFT 12
+#define RG_EQ_KP_T2_HI 14
+#define RG_EQ_KP_T2_SZ 3
+#define RG_EQ_KI_T1_MSK 0x00070000
+#define RG_EQ_KI_T1_I_MSK 0xfff8ffff
+#define RG_EQ_KI_T1_SFT 16
+#define RG_EQ_KI_T1_HI 18
+#define RG_EQ_KI_T1_SZ 3
+#define RG_EQ_KP_T1_MSK 0x00700000
+#define RG_EQ_KP_T1_I_MSK 0xff8fffff
+#define RG_EQ_KP_T1_SFT 20
+#define RG_EQ_KP_T1_HI 22
+#define RG_EQ_KP_T1_SZ 3
+#define RG_TR_LPF_RATE_MSK 0x003fffff
+#define RG_TR_LPF_RATE_I_MSK 0xffc00000
+#define RG_TR_LPF_RATE_SFT 0
+#define RG_TR_LPF_RATE_HI 21
+#define RG_TR_LPF_RATE_SZ 22
+#define RG_CE_BIT_CNT_LMT_MSK 0x0000007f
+#define RG_CE_BIT_CNT_LMT_I_MSK 0xffffff80
+#define RG_CE_BIT_CNT_LMT_SFT 0
+#define RG_CE_BIT_CNT_LMT_HI 6
+#define RG_CE_BIT_CNT_LMT_SZ 7
+#define RG_CE_CH_MAIN_SET_MSK 0x00000080
+#define RG_CE_CH_MAIN_SET_I_MSK 0xffffff7f
+#define RG_CE_CH_MAIN_SET_SFT 7
+#define RG_CE_CH_MAIN_SET_HI 7
+#define RG_CE_CH_MAIN_SET_SZ 1
+#define RG_TC_BIT_CNT_LMT_MSK 0x00007f00
+#define RG_TC_BIT_CNT_LMT_I_MSK 0xffff80ff
+#define RG_TC_BIT_CNT_LMT_SFT 8
+#define RG_TC_BIT_CNT_LMT_HI 14
+#define RG_TC_BIT_CNT_LMT_SZ 7
+#define RG_CR_BIT_CNT_LMT_MSK 0x007f0000
+#define RG_CR_BIT_CNT_LMT_I_MSK 0xff80ffff
+#define RG_CR_BIT_CNT_LMT_SFT 16
+#define RG_CR_BIT_CNT_LMT_HI 22
+#define RG_CR_BIT_CNT_LMT_SZ 7
+#define RG_TR_BIT_CNT_LMT_MSK 0x7f000000
+#define RG_TR_BIT_CNT_LMT_I_MSK 0x80ffffff
+#define RG_TR_BIT_CNT_LMT_SFT 24
+#define RG_TR_BIT_CNT_LMT_HI 30
+#define RG_TR_BIT_CNT_LMT_SZ 7
+#define RG_EQ_MAIN_TAP_MAN_MSK 0x00000001
+#define RG_EQ_MAIN_TAP_MAN_I_MSK 0xfffffffe
+#define RG_EQ_MAIN_TAP_MAN_SFT 0
+#define RG_EQ_MAIN_TAP_MAN_HI 0
+#define RG_EQ_MAIN_TAP_MAN_SZ 1
+#define RG_EQ_MAIN_TAP_COEF_MSK 0x07ff0000
+#define RG_EQ_MAIN_TAP_COEF_I_MSK 0xf800ffff
+#define RG_EQ_MAIN_TAP_COEF_SFT 16
+#define RG_EQ_MAIN_TAP_COEF_HI 26
+#define RG_EQ_MAIN_TAP_COEF_SZ 11
+#define RG_PWRON_DLY_TH_11B_MSK 0x000000ff
+#define RG_PWRON_DLY_TH_11B_I_MSK 0xffffff00
+#define RG_PWRON_DLY_TH_11B_SFT 0
+#define RG_PWRON_DLY_TH_11B_HI 7
+#define RG_PWRON_DLY_TH_11B_SZ 8
+#define RG_SFD_BIT_CNT_LMT_MSK 0x00ff0000
+#define RG_SFD_BIT_CNT_LMT_I_MSK 0xff00ffff
+#define RG_SFD_BIT_CNT_LMT_SFT 16
+#define RG_SFD_BIT_CNT_LMT_HI 23
+#define RG_SFD_BIT_CNT_LMT_SZ 8
+#define RG_CCA_PWR_TH_RX_MSK 0x00007fff
+#define RG_CCA_PWR_TH_RX_I_MSK 0xffff8000
+#define RG_CCA_PWR_TH_RX_SFT 0
+#define RG_CCA_PWR_TH_RX_HI 14
+#define RG_CCA_PWR_TH_RX_SZ 15
+#define RG_CCA_PWR_CNT_TH_MSK 0x001f0000
+#define RG_CCA_PWR_CNT_TH_I_MSK 0xffe0ffff
+#define RG_CCA_PWR_CNT_TH_SFT 16
+#define RG_CCA_PWR_CNT_TH_HI 20
+#define RG_CCA_PWR_CNT_TH_SZ 5
+#define B_FREQ_OS_MSK 0x000007ff
+#define B_FREQ_OS_I_MSK 0xfffff800
+#define B_FREQ_OS_SFT 0
+#define B_FREQ_OS_HI 10
+#define B_FREQ_OS_SZ 11
+#define B_SNR_MSK 0x0000007f
+#define B_SNR_I_MSK 0xffffff80
+#define B_SNR_SFT 0
+#define B_SNR_HI 6
+#define B_SNR_SZ 7
+#define B_RCPI_MSK 0x007f0000
+#define B_RCPI_I_MSK 0xff80ffff
+#define B_RCPI_SFT 16
+#define B_RCPI_HI 22
+#define B_RCPI_SZ 7
+#define CRC_CNT_MSK 0x0000ffff
+#define CRC_CNT_I_MSK 0xffff0000
+#define CRC_CNT_SFT 0
+#define CRC_CNT_HI 15
+#define CRC_CNT_SZ 16
+#define SFD_CNT_MSK 0xffff0000
+#define SFD_CNT_I_MSK 0x0000ffff
+#define SFD_CNT_SFT 16
+#define SFD_CNT_HI 31
+#define SFD_CNT_SZ 16
+#define B_PACKET_ERR_CNT_MSK 0x0000ffff
+#define B_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define B_PACKET_ERR_CNT_SFT 0
+#define B_PACKET_ERR_CNT_HI 15
+#define B_PACKET_ERR_CNT_SZ 16
+#define PACKET_ERR_MSK 0x00010000
+#define PACKET_ERR_I_MSK 0xfffeffff
+#define PACKET_ERR_SFT 16
+#define PACKET_ERR_HI 16
+#define PACKET_ERR_SZ 1
+#define B_PACKET_CNT_MSK 0x0000ffff
+#define B_PACKET_CNT_I_MSK 0xffff0000
+#define B_PACKET_CNT_SFT 0
+#define B_PACKET_CNT_HI 15
+#define B_PACKET_CNT_SZ 16
+#define B_CCA_CNT_MSK 0xffff0000
+#define B_CCA_CNT_I_MSK 0x0000ffff
+#define B_CCA_CNT_SFT 16
+#define B_CCA_CNT_HI 31
+#define B_CCA_CNT_SZ 16
+#define B_LENGTH_FIELD_MSK 0x0000ffff
+#define B_LENGTH_FIELD_I_MSK 0xffff0000
+#define B_LENGTH_FIELD_SFT 0
+#define B_LENGTH_FIELD_HI 15
+#define B_LENGTH_FIELD_SZ 16
+#define SFD_FIELD_MSK 0xffff0000
+#define SFD_FIELD_I_MSK 0x0000ffff
+#define SFD_FIELD_SFT 16
+#define SFD_FIELD_HI 31
+#define SFD_FIELD_SZ 16
+#define SIGNAL_FIELD_MSK 0x000000ff
+#define SIGNAL_FIELD_I_MSK 0xffffff00
+#define SIGNAL_FIELD_SFT 0
+#define SIGNAL_FIELD_HI 7
+#define SIGNAL_FIELD_SZ 8
+#define B_SERVICE_FIELD_MSK 0x0000ff00
+#define B_SERVICE_FIELD_I_MSK 0xffff00ff
+#define B_SERVICE_FIELD_SFT 8
+#define B_SERVICE_FIELD_HI 15
+#define B_SERVICE_FIELD_SZ 8
+#define CRC_CORRECT_MSK 0x00010000
+#define CRC_CORRECT_I_MSK 0xfffeffff
+#define CRC_CORRECT_SFT 16
+#define CRC_CORRECT_HI 16
+#define CRC_CORRECT_SZ 1
+#define DEBUG_SEL_MSK 0x0000000f
+#define DEBUG_SEL_I_MSK 0xfffffff0
+#define DEBUG_SEL_SFT 0
+#define DEBUG_SEL_HI 3
+#define DEBUG_SEL_SZ 4
+#define RG_PACKET_STAT_EN_11B_MSK 0x00100000
+#define RG_PACKET_STAT_EN_11B_I_MSK 0xffefffff
+#define RG_PACKET_STAT_EN_11B_SFT 20
+#define RG_PACKET_STAT_EN_11B_HI 20
+#define RG_PACKET_STAT_EN_11B_SZ 1
+#define RG_BIT_REVERSE_MSK 0x00200000
+#define RG_BIT_REVERSE_I_MSK 0xffdfffff
+#define RG_BIT_REVERSE_SFT 21
+#define RG_BIT_REVERSE_HI 21
+#define RG_BIT_REVERSE_SZ 1
+#define RX_PHY_11B_SOFT_RST_N_MSK 0x00000001
+#define RX_PHY_11B_SOFT_RST_N_I_MSK 0xfffffffe
+#define RX_PHY_11B_SOFT_RST_N_SFT 0
+#define RX_PHY_11B_SOFT_RST_N_HI 0
+#define RX_PHY_11B_SOFT_RST_N_SZ 1
+#define RG_CE_BYPASS_TAP_MSK 0x000000f0
+#define RG_CE_BYPASS_TAP_I_MSK 0xffffff0f
+#define RG_CE_BYPASS_TAP_SFT 4
+#define RG_CE_BYPASS_TAP_HI 7
+#define RG_CE_BYPASS_TAP_SZ 4
+#define RG_EQ_BYPASS_FBW_TAP_MSK 0x00000f00
+#define RG_EQ_BYPASS_FBW_TAP_I_MSK 0xfffff0ff
+#define RG_EQ_BYPASS_FBW_TAP_SFT 8
+#define RG_EQ_BYPASS_FBW_TAP_HI 11
+#define RG_EQ_BYPASS_FBW_TAP_SZ 4
+#define RG_BB_11GN_RISE_TIME_MSK 0x000000ff
+#define RG_BB_11GN_RISE_TIME_I_MSK 0xffffff00
+#define RG_BB_11GN_RISE_TIME_SFT 0
+#define RG_BB_11GN_RISE_TIME_HI 7
+#define RG_BB_11GN_RISE_TIME_SZ 8
+#define RG_BB_11GN_FALL_TIME_MSK 0x0000ff00
+#define RG_BB_11GN_FALL_TIME_I_MSK 0xffff00ff
+#define RG_BB_11GN_FALL_TIME_SFT 8
+#define RG_BB_11GN_FALL_TIME_HI 15
+#define RG_BB_11GN_FALL_TIME_SZ 8
+#define RG_HTCARR52_FFT_SCALE_MSK 0x000003ff
+#define RG_HTCARR52_FFT_SCALE_I_MSK 0xfffffc00
+#define RG_HTCARR52_FFT_SCALE_SFT 0
+#define RG_HTCARR52_FFT_SCALE_HI 9
+#define RG_HTCARR52_FFT_SCALE_SZ 10
+#define RG_HTCARR56_FFT_SCALE_MSK 0x003ff000
+#define RG_HTCARR56_FFT_SCALE_I_MSK 0xffc00fff
+#define RG_HTCARR56_FFT_SCALE_SFT 12
+#define RG_HTCARR56_FFT_SCALE_HI 21
+#define RG_HTCARR56_FFT_SCALE_SZ 10
+#define RG_PACKET_STAT_EN_MSK 0x00800000
+#define RG_PACKET_STAT_EN_I_MSK 0xff7fffff
+#define RG_PACKET_STAT_EN_SFT 23
+#define RG_PACKET_STAT_EN_HI 23
+#define RG_PACKET_STAT_EN_SZ 1
+#define RG_SMB_DEF_MSK 0x7f000000
+#define RG_SMB_DEF_I_MSK 0x80ffffff
+#define RG_SMB_DEF_SFT 24
+#define RG_SMB_DEF_HI 30
+#define RG_SMB_DEF_SZ 7
+#define RG_CONTINUOUS_DATA_11GN_MSK 0x80000000
+#define RG_CONTINUOUS_DATA_11GN_I_MSK 0x7fffffff
+#define RG_CONTINUOUS_DATA_11GN_SFT 31
+#define RG_CONTINUOUS_DATA_11GN_HI 31
+#define RG_CONTINUOUS_DATA_11GN_SZ 1
+#define RO_TX_CNT_R_MSK 0xffffffff
+#define RO_TX_CNT_R_I_MSK 0x00000000
+#define RO_TX_CNT_R_SFT 0
+#define RO_TX_CNT_R_HI 31
+#define RO_TX_CNT_R_SZ 32
+#define RO_PACKET_ERR_CNT_MSK 0x0000ffff
+#define RO_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define RO_PACKET_ERR_CNT_SFT 0
+#define RO_PACKET_ERR_CNT_HI 15
+#define RO_PACKET_ERR_CNT_SZ 16
+#define RG_POS_DES_11GN_L_EXT_MSK 0x0000000f
+#define RG_POS_DES_11GN_L_EXT_I_MSK 0xfffffff0
+#define RG_POS_DES_11GN_L_EXT_SFT 0
+#define RG_POS_DES_11GN_L_EXT_HI 3
+#define RG_POS_DES_11GN_L_EXT_SZ 4
+#define RG_PRE_DES_11GN_DLY_MSK 0x000000f0
+#define RG_PRE_DES_11GN_DLY_I_MSK 0xffffff0f
+#define RG_PRE_DES_11GN_DLY_SFT 4
+#define RG_PRE_DES_11GN_DLY_HI 7
+#define RG_PRE_DES_11GN_DLY_SZ 4
+#define RG_TR_LPF_KI_G_T1_MSK 0x0000000f
+#define RG_TR_LPF_KI_G_T1_I_MSK 0xfffffff0
+#define RG_TR_LPF_KI_G_T1_SFT 0
+#define RG_TR_LPF_KI_G_T1_HI 3
+#define RG_TR_LPF_KI_G_T1_SZ 4
+#define RG_TR_LPF_KP_G_T1_MSK 0x000000f0
+#define RG_TR_LPF_KP_G_T1_I_MSK 0xffffff0f
+#define RG_TR_LPF_KP_G_T1_SFT 4
+#define RG_TR_LPF_KP_G_T1_HI 7
+#define RG_TR_LPF_KP_G_T1_SZ 4
+#define RG_TR_CNT_T1_MSK 0x0000ff00
+#define RG_TR_CNT_T1_I_MSK 0xffff00ff
+#define RG_TR_CNT_T1_SFT 8
+#define RG_TR_CNT_T1_HI 15
+#define RG_TR_CNT_T1_SZ 8
+#define RG_TR_LPF_KI_G_T0_MSK 0x000f0000
+#define RG_TR_LPF_KI_G_T0_I_MSK 0xfff0ffff
+#define RG_TR_LPF_KI_G_T0_SFT 16
+#define RG_TR_LPF_KI_G_T0_HI 19
+#define RG_TR_LPF_KI_G_T0_SZ 4
+#define RG_TR_LPF_KP_G_T0_MSK 0x00f00000
+#define RG_TR_LPF_KP_G_T0_I_MSK 0xff0fffff
+#define RG_TR_LPF_KP_G_T0_SFT 20
+#define RG_TR_LPF_KP_G_T0_HI 23
+#define RG_TR_LPF_KP_G_T0_SZ 4
+#define RG_TR_CNT_T0_MSK 0xff000000
+#define RG_TR_CNT_T0_I_MSK 0x00ffffff
+#define RG_TR_CNT_T0_SFT 24
+#define RG_TR_CNT_T0_HI 31
+#define RG_TR_CNT_T0_SZ 8
+#define RG_TR_LPF_KI_G_T2_MSK 0x0000000f
+#define RG_TR_LPF_KI_G_T2_I_MSK 0xfffffff0
+#define RG_TR_LPF_KI_G_T2_SFT 0
+#define RG_TR_LPF_KI_G_T2_HI 3
+#define RG_TR_LPF_KI_G_T2_SZ 4
+#define RG_TR_LPF_KP_G_T2_MSK 0x000000f0
+#define RG_TR_LPF_KP_G_T2_I_MSK 0xffffff0f
+#define RG_TR_LPF_KP_G_T2_SFT 4
+#define RG_TR_LPF_KP_G_T2_HI 7
+#define RG_TR_LPF_KP_G_T2_SZ 4
+#define RG_TR_CNT_T2_MSK 0x0000ff00
+#define RG_TR_CNT_T2_I_MSK 0xffff00ff
+#define RG_TR_CNT_T2_SFT 8
+#define RG_TR_CNT_T2_HI 15
+#define RG_TR_CNT_T2_SZ 8
+#define RG_TR_LPF_KI_G_MSK 0x0000000f
+#define RG_TR_LPF_KI_G_I_MSK 0xfffffff0
+#define RG_TR_LPF_KI_G_SFT 0
+#define RG_TR_LPF_KI_G_HI 3
+#define RG_TR_LPF_KI_G_SZ 4
+#define RG_TR_LPF_KP_G_MSK 0x000000f0
+#define RG_TR_LPF_KP_G_I_MSK 0xffffff0f
+#define RG_TR_LPF_KP_G_SFT 4
+#define RG_TR_LPF_KP_G_HI 7
+#define RG_TR_LPF_KP_G_SZ 4
+#define RG_TR_LPF_RATE_G_MSK 0x3fffff00
+#define RG_TR_LPF_RATE_G_I_MSK 0xc00000ff
+#define RG_TR_LPF_RATE_G_SFT 8
+#define RG_TR_LPF_RATE_G_HI 29
+#define RG_TR_LPF_RATE_G_SZ 22
+#define RG_CR_LPF_KI_G_MSK 0x00000007
+#define RG_CR_LPF_KI_G_I_MSK 0xfffffff8
+#define RG_CR_LPF_KI_G_SFT 0
+#define RG_CR_LPF_KI_G_HI 2
+#define RG_CR_LPF_KI_G_SZ 3
+#define RG_SYM_BOUND_CNT_MSK 0x00007f00
+#define RG_SYM_BOUND_CNT_I_MSK 0xffff80ff
+#define RG_SYM_BOUND_CNT_SFT 8
+#define RG_SYM_BOUND_CNT_HI 14
+#define RG_SYM_BOUND_CNT_SZ 7
+#define RG_XSCOR32_RATIO_MSK 0x007f0000
+#define RG_XSCOR32_RATIO_I_MSK 0xff80ffff
+#define RG_XSCOR32_RATIO_SFT 16
+#define RG_XSCOR32_RATIO_HI 22
+#define RG_XSCOR32_RATIO_SZ 7
+#define RG_ATCOR64_CNT_LMT_MSK 0x7f000000
+#define RG_ATCOR64_CNT_LMT_I_MSK 0x80ffffff
+#define RG_ATCOR64_CNT_LMT_SFT 24
+#define RG_ATCOR64_CNT_LMT_HI 30
+#define RG_ATCOR64_CNT_LMT_SZ 7
+#define RG_ATCOR16_CNT_LMT2_MSK 0x00007f00
+#define RG_ATCOR16_CNT_LMT2_I_MSK 0xffff80ff
+#define RG_ATCOR16_CNT_LMT2_SFT 8
+#define RG_ATCOR16_CNT_LMT2_HI 14
+#define RG_ATCOR16_CNT_LMT2_SZ 7
+#define RG_ATCOR16_CNT_LMT1_MSK 0x007f0000
+#define RG_ATCOR16_CNT_LMT1_I_MSK 0xff80ffff
+#define RG_ATCOR16_CNT_LMT1_SFT 16
+#define RG_ATCOR16_CNT_LMT1_HI 22
+#define RG_ATCOR16_CNT_LMT1_SZ 7
+#define RG_ATCOR16_RATIO_SB_MSK 0x7f000000
+#define RG_ATCOR16_RATIO_SB_I_MSK 0x80ffffff
+#define RG_ATCOR16_RATIO_SB_SFT 24
+#define RG_ATCOR16_RATIO_SB_HI 30
+#define RG_ATCOR16_RATIO_SB_SZ 7
+#define RG_XSCOR64_CNT_LMT2_MSK 0x007f0000
+#define RG_XSCOR64_CNT_LMT2_I_MSK 0xff80ffff
+#define RG_XSCOR64_CNT_LMT2_SFT 16
+#define RG_XSCOR64_CNT_LMT2_HI 22
+#define RG_XSCOR64_CNT_LMT2_SZ 7
+#define RG_XSCOR64_CNT_LMT1_MSK 0x7f000000
+#define RG_XSCOR64_CNT_LMT1_I_MSK 0x80ffffff
+#define RG_XSCOR64_CNT_LMT1_SFT 24
+#define RG_XSCOR64_CNT_LMT1_HI 30
+#define RG_XSCOR64_CNT_LMT1_SZ 7
+#define RG_RX_FFT_SCALE_MSK 0x000003ff
+#define RG_RX_FFT_SCALE_I_MSK 0xfffffc00
+#define RG_RX_FFT_SCALE_SFT 0
+#define RG_RX_FFT_SCALE_HI 9
+#define RG_RX_FFT_SCALE_SZ 10
+#define RG_VITERBI_AB_SWAP_MSK 0x00010000
+#define RG_VITERBI_AB_SWAP_I_MSK 0xfffeffff
+#define RG_VITERBI_AB_SWAP_SFT 16
+#define RG_VITERBI_AB_SWAP_HI 16
+#define RG_VITERBI_AB_SWAP_SZ 1
+#define RG_ATCOR16_CNT_TH_MSK 0x0f000000
+#define RG_ATCOR16_CNT_TH_I_MSK 0xf0ffffff
+#define RG_ATCOR16_CNT_TH_SFT 24
+#define RG_ATCOR16_CNT_TH_HI 27
+#define RG_ATCOR16_CNT_TH_SZ 4
+#define RG_NORMSQUARE_LOW_SNR_7_MSK 0x000000ff
+#define RG_NORMSQUARE_LOW_SNR_7_I_MSK 0xffffff00
+#define RG_NORMSQUARE_LOW_SNR_7_SFT 0
+#define RG_NORMSQUARE_LOW_SNR_7_HI 7
+#define RG_NORMSQUARE_LOW_SNR_7_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_6_MSK 0x0000ff00
+#define RG_NORMSQUARE_LOW_SNR_6_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_LOW_SNR_6_SFT 8
+#define RG_NORMSQUARE_LOW_SNR_6_HI 15
+#define RG_NORMSQUARE_LOW_SNR_6_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_5_MSK 0x00ff0000
+#define RG_NORMSQUARE_LOW_SNR_5_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_LOW_SNR_5_SFT 16
+#define RG_NORMSQUARE_LOW_SNR_5_HI 23
+#define RG_NORMSQUARE_LOW_SNR_5_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_4_MSK 0xff000000
+#define RG_NORMSQUARE_LOW_SNR_4_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_LOW_SNR_4_SFT 24
+#define RG_NORMSQUARE_LOW_SNR_4_HI 31
+#define RG_NORMSQUARE_LOW_SNR_4_SZ 8
+#define RG_NORMSQUARE_LOW_SNR_8_MSK 0xff000000
+#define RG_NORMSQUARE_LOW_SNR_8_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_LOW_SNR_8_SFT 24
+#define RG_NORMSQUARE_LOW_SNR_8_HI 31
+#define RG_NORMSQUARE_LOW_SNR_8_SZ 8
+#define RG_NORMSQUARE_SNR_3_MSK 0x000000ff
+#define RG_NORMSQUARE_SNR_3_I_MSK 0xffffff00
+#define RG_NORMSQUARE_SNR_3_SFT 0
+#define RG_NORMSQUARE_SNR_3_HI 7
+#define RG_NORMSQUARE_SNR_3_SZ 8
+#define RG_NORMSQUARE_SNR_2_MSK 0x0000ff00
+#define RG_NORMSQUARE_SNR_2_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_SNR_2_SFT 8
+#define RG_NORMSQUARE_SNR_2_HI 15
+#define RG_NORMSQUARE_SNR_2_SZ 8
+#define RG_NORMSQUARE_SNR_1_MSK 0x00ff0000
+#define RG_NORMSQUARE_SNR_1_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_SNR_1_SFT 16
+#define RG_NORMSQUARE_SNR_1_HI 23
+#define RG_NORMSQUARE_SNR_1_SZ 8
+#define RG_NORMSQUARE_SNR_0_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_0_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_0_SFT 24
+#define RG_NORMSQUARE_SNR_0_HI 31
+#define RG_NORMSQUARE_SNR_0_SZ 8
+#define RG_NORMSQUARE_SNR_7_MSK 0x000000ff
+#define RG_NORMSQUARE_SNR_7_I_MSK 0xffffff00
+#define RG_NORMSQUARE_SNR_7_SFT 0
+#define RG_NORMSQUARE_SNR_7_HI 7
+#define RG_NORMSQUARE_SNR_7_SZ 8
+#define RG_NORMSQUARE_SNR_6_MSK 0x0000ff00
+#define RG_NORMSQUARE_SNR_6_I_MSK 0xffff00ff
+#define RG_NORMSQUARE_SNR_6_SFT 8
+#define RG_NORMSQUARE_SNR_6_HI 15
+#define RG_NORMSQUARE_SNR_6_SZ 8
+#define RG_NORMSQUARE_SNR_5_MSK 0x00ff0000
+#define RG_NORMSQUARE_SNR_5_I_MSK 0xff00ffff
+#define RG_NORMSQUARE_SNR_5_SFT 16
+#define RG_NORMSQUARE_SNR_5_HI 23
+#define RG_NORMSQUARE_SNR_5_SZ 8
+#define RG_NORMSQUARE_SNR_4_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_4_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_4_SFT 24
+#define RG_NORMSQUARE_SNR_4_HI 31
+#define RG_NORMSQUARE_SNR_4_SZ 8
+#define RG_NORMSQUARE_SNR_8_MSK 0xff000000
+#define RG_NORMSQUARE_SNR_8_I_MSK 0x00ffffff
+#define RG_NORMSQUARE_SNR_8_SFT 24
+#define RG_NORMSQUARE_SNR_8_HI 31
+#define RG_NORMSQUARE_SNR_8_SZ 8
+#define RG_SNR_TH_64QAM_MSK 0x0000007f
+#define RG_SNR_TH_64QAM_I_MSK 0xffffff80
+#define RG_SNR_TH_64QAM_SFT 0
+#define RG_SNR_TH_64QAM_HI 6
+#define RG_SNR_TH_64QAM_SZ 7
+#define RG_SNR_TH_16QAM_MSK 0x00007f00
+#define RG_SNR_TH_16QAM_I_MSK 0xffff80ff
+#define RG_SNR_TH_16QAM_SFT 8
+#define RG_SNR_TH_16QAM_HI 14
+#define RG_SNR_TH_16QAM_SZ 7
+#define RG_ATCOR16_CNT_PLUS_LMT2_MSK 0x0000007f
+#define RG_ATCOR16_CNT_PLUS_LMT2_I_MSK 0xffffff80
+#define RG_ATCOR16_CNT_PLUS_LMT2_SFT 0
+#define RG_ATCOR16_CNT_PLUS_LMT2_HI 6
+#define RG_ATCOR16_CNT_PLUS_LMT2_SZ 7
+#define RG_ATCOR16_CNT_PLUS_LMT1_MSK 0x00007f00
+#define RG_ATCOR16_CNT_PLUS_LMT1_I_MSK 0xffff80ff
+#define RG_ATCOR16_CNT_PLUS_LMT1_SFT 8
+#define RG_ATCOR16_CNT_PLUS_LMT1_HI 14
+#define RG_ATCOR16_CNT_PLUS_LMT1_SZ 7
+#define RG_SYM_BOUND_METHOD_MSK 0x00030000
+#define RG_SYM_BOUND_METHOD_I_MSK 0xfffcffff
+#define RG_SYM_BOUND_METHOD_SFT 16
+#define RG_SYM_BOUND_METHOD_HI 17
+#define RG_SYM_BOUND_METHOD_SZ 2
+#define RG_PWRON_DLY_TH_11GN_MSK 0x000000ff
+#define RG_PWRON_DLY_TH_11GN_I_MSK 0xffffff00
+#define RG_PWRON_DLY_TH_11GN_SFT 0
+#define RG_PWRON_DLY_TH_11GN_HI 7
+#define RG_PWRON_DLY_TH_11GN_SZ 8
+#define RG_SB_START_CNT_MSK 0x00007f00
+#define RG_SB_START_CNT_I_MSK 0xffff80ff
+#define RG_SB_START_CNT_SFT 8
+#define RG_SB_START_CNT_HI 14
+#define RG_SB_START_CNT_SZ 7
+#define RG_POW16_CNT_TH_MSK 0x000000f0
+#define RG_POW16_CNT_TH_I_MSK 0xffffff0f
+#define RG_POW16_CNT_TH_SFT 4
+#define RG_POW16_CNT_TH_HI 7
+#define RG_POW16_CNT_TH_SZ 4
+#define RG_POW16_SHORT_CNT_LMT_MSK 0x00000700
+#define RG_POW16_SHORT_CNT_LMT_I_MSK 0xfffff8ff
+#define RG_POW16_SHORT_CNT_LMT_SFT 8
+#define RG_POW16_SHORT_CNT_LMT_HI 10
+#define RG_POW16_SHORT_CNT_LMT_SZ 3
+#define RG_POW16_TH_L_MSK 0x7f000000
+#define RG_POW16_TH_L_I_MSK 0x80ffffff
+#define RG_POW16_TH_L_SFT 24
+#define RG_POW16_TH_L_HI 30
+#define RG_POW16_TH_L_SZ 7
+#define RG_XSCOR16_SHORT_CNT_LMT_MSK 0x00000007
+#define RG_XSCOR16_SHORT_CNT_LMT_I_MSK 0xfffffff8
+#define RG_XSCOR16_SHORT_CNT_LMT_SFT 0
+#define RG_XSCOR16_SHORT_CNT_LMT_HI 2
+#define RG_XSCOR16_SHORT_CNT_LMT_SZ 3
+#define RG_XSCOR16_RATIO_MSK 0x00007f00
+#define RG_XSCOR16_RATIO_I_MSK 0xffff80ff
+#define RG_XSCOR16_RATIO_SFT 8
+#define RG_XSCOR16_RATIO_HI 14
+#define RG_XSCOR16_RATIO_SZ 7
+#define RG_ATCOR16_SHORT_CNT_LMT_MSK 0x00070000
+#define RG_ATCOR16_SHORT_CNT_LMT_I_MSK 0xfff8ffff
+#define RG_ATCOR16_SHORT_CNT_LMT_SFT 16
+#define RG_ATCOR16_SHORT_CNT_LMT_HI 18
+#define RG_ATCOR16_SHORT_CNT_LMT_SZ 3
+#define RG_ATCOR16_RATIO_CCD_MSK 0x7f000000
+#define RG_ATCOR16_RATIO_CCD_I_MSK 0x80ffffff
+#define RG_ATCOR16_RATIO_CCD_SFT 24
+#define RG_ATCOR16_RATIO_CCD_HI 30
+#define RG_ATCOR16_RATIO_CCD_SZ 7
+#define RG_ATCOR64_ACC_LMT_MSK 0x0000007f
+#define RG_ATCOR64_ACC_LMT_I_MSK 0xffffff80
+#define RG_ATCOR64_ACC_LMT_SFT 0
+#define RG_ATCOR64_ACC_LMT_HI 6
+#define RG_ATCOR64_ACC_LMT_SZ 7
+#define RG_ATCOR16_SHORT_CNT_LMT2_MSK 0x00070000
+#define RG_ATCOR16_SHORT_CNT_LMT2_I_MSK 0xfff8ffff
+#define RG_ATCOR16_SHORT_CNT_LMT2_SFT 16
+#define RG_ATCOR16_SHORT_CNT_LMT2_HI 18
+#define RG_ATCOR16_SHORT_CNT_LMT2_SZ 3
+#define RG_VITERBI_TB_BITS_MSK 0xff000000
+#define RG_VITERBI_TB_BITS_I_MSK 0x00ffffff
+#define RG_VITERBI_TB_BITS_SFT 24
+#define RG_VITERBI_TB_BITS_HI 31
+#define RG_VITERBI_TB_BITS_SZ 8
+#define RG_CR_CNT_UPDATE_MSK 0x000000ff
+#define RG_CR_CNT_UPDATE_I_MSK 0xffffff00
+#define RG_CR_CNT_UPDATE_SFT 0
+#define RG_CR_CNT_UPDATE_HI 7
+#define RG_CR_CNT_UPDATE_SZ 8
+#define RG_TR_CNT_UPDATE_MSK 0x00ff0000
+#define RG_TR_CNT_UPDATE_I_MSK 0xff00ffff
+#define RG_TR_CNT_UPDATE_SFT 16
+#define RG_TR_CNT_UPDATE_HI 23
+#define RG_TR_CNT_UPDATE_SZ 8
+#define RG_BYPASS_CPE_MA_MSK 0x00000010
+#define RG_BYPASS_CPE_MA_I_MSK 0xffffffef
+#define RG_BYPASS_CPE_MA_SFT 4
+#define RG_BYPASS_CPE_MA_HI 4
+#define RG_BYPASS_CPE_MA_SZ 1
+#define RG_PILOT_BNDRY_SHIFT_MSK 0x00000700
+#define RG_PILOT_BNDRY_SHIFT_I_MSK 0xfffff8ff
+#define RG_PILOT_BNDRY_SHIFT_SFT 8
+#define RG_PILOT_BNDRY_SHIFT_HI 10
+#define RG_PILOT_BNDRY_SHIFT_SZ 3
+#define RG_EQ_SHORT_GI_SHIFT_MSK 0x00007000
+#define RG_EQ_SHORT_GI_SHIFT_I_MSK 0xffff8fff
+#define RG_EQ_SHORT_GI_SHIFT_SFT 12
+#define RG_EQ_SHORT_GI_SHIFT_HI 14
+#define RG_EQ_SHORT_GI_SHIFT_SZ 3
+#define RG_FFT_WDW_SHORT_SHIFT_MSK 0x00070000
+#define RG_FFT_WDW_SHORT_SHIFT_I_MSK 0xfff8ffff
+#define RG_FFT_WDW_SHORT_SHIFT_SFT 16
+#define RG_FFT_WDW_SHORT_SHIFT_HI 18
+#define RG_FFT_WDW_SHORT_SHIFT_SZ 3
+#define RG_CHSMTH_COEF_MSK 0x00030000
+#define RG_CHSMTH_COEF_I_MSK 0xfffcffff
+#define RG_CHSMTH_COEF_SFT 16
+#define RG_CHSMTH_COEF_HI 17
+#define RG_CHSMTH_COEF_SZ 2
+#define RG_CHSMTH_EN_MSK 0x00040000
+#define RG_CHSMTH_EN_I_MSK 0xfffbffff
+#define RG_CHSMTH_EN_SFT 18
+#define RG_CHSMTH_EN_HI 18
+#define RG_CHSMTH_EN_SZ 1
+#define RG_CHEST_DD_FACTOR_MSK 0x07000000
+#define RG_CHEST_DD_FACTOR_I_MSK 0xf8ffffff
+#define RG_CHEST_DD_FACTOR_SFT 24
+#define RG_CHEST_DD_FACTOR_HI 26
+#define RG_CHEST_DD_FACTOR_SZ 3
+#define RG_CH_UPDATE_MSK 0x80000000
+#define RG_CH_UPDATE_I_MSK 0x7fffffff
+#define RG_CH_UPDATE_SFT 31
+#define RG_CH_UPDATE_HI 31
+#define RG_CH_UPDATE_SZ 1
+#define RG_FMT_DET_MM_TH_MSK 0x000000ff
+#define RG_FMT_DET_MM_TH_I_MSK 0xffffff00
+#define RG_FMT_DET_MM_TH_SFT 0
+#define RG_FMT_DET_MM_TH_HI 7
+#define RG_FMT_DET_MM_TH_SZ 8
+#define RG_FMT_DET_GF_TH_MSK 0x0000ff00
+#define RG_FMT_DET_GF_TH_I_MSK 0xffff00ff
+#define RG_FMT_DET_GF_TH_SFT 8
+#define RG_FMT_DET_GF_TH_HI 15
+#define RG_FMT_DET_GF_TH_SZ 8
+#define RG_DO_NOT_CHECK_L_RATE_MSK 0x02000000
+#define RG_DO_NOT_CHECK_L_RATE_I_MSK 0xfdffffff
+#define RG_DO_NOT_CHECK_L_RATE_SFT 25
+#define RG_DO_NOT_CHECK_L_RATE_HI 25
+#define RG_DO_NOT_CHECK_L_RATE_SZ 1
+#define RG_FMT_DET_LENGTH_TH_MSK 0x0000ffff
+#define RG_FMT_DET_LENGTH_TH_I_MSK 0xffff0000
+#define RG_FMT_DET_LENGTH_TH_SFT 0
+#define RG_FMT_DET_LENGTH_TH_HI 15
+#define RG_FMT_DET_LENGTH_TH_SZ 16
+#define RG_L_LENGTH_MAX_MSK 0xffff0000
+#define RG_L_LENGTH_MAX_I_MSK 0x0000ffff
+#define RG_L_LENGTH_MAX_SFT 16
+#define RG_L_LENGTH_MAX_HI 31
+#define RG_L_LENGTH_MAX_SZ 16
+#define RG_TX_TIME_EXT_MSK 0x000000ff
+#define RG_TX_TIME_EXT_I_MSK 0xffffff00
+#define RG_TX_TIME_EXT_SFT 0
+#define RG_TX_TIME_EXT_HI 7
+#define RG_TX_TIME_EXT_SZ 8
+#define RG_MAC_DES_SPACE_MSK 0x00f00000
+#define RG_MAC_DES_SPACE_I_MSK 0xff0fffff
+#define RG_MAC_DES_SPACE_SFT 20
+#define RG_MAC_DES_SPACE_HI 23
+#define RG_MAC_DES_SPACE_SZ 4
+#define RG_TR_LPF_STBC_GF_KI_G_MSK 0x0000000f
+#define RG_TR_LPF_STBC_GF_KI_G_I_MSK 0xfffffff0
+#define RG_TR_LPF_STBC_GF_KI_G_SFT 0
+#define RG_TR_LPF_STBC_GF_KI_G_HI 3
+#define RG_TR_LPF_STBC_GF_KI_G_SZ 4
+#define RG_TR_LPF_STBC_GF_KP_G_MSK 0x000000f0
+#define RG_TR_LPF_STBC_GF_KP_G_I_MSK 0xffffff0f
+#define RG_TR_LPF_STBC_GF_KP_G_SFT 4
+#define RG_TR_LPF_STBC_GF_KP_G_HI 7
+#define RG_TR_LPF_STBC_GF_KP_G_SZ 4
+#define RG_TR_LPF_STBC_MF_KI_G_MSK 0x00000f00
+#define RG_TR_LPF_STBC_MF_KI_G_I_MSK 0xfffff0ff
+#define RG_TR_LPF_STBC_MF_KI_G_SFT 8
+#define RG_TR_LPF_STBC_MF_KI_G_HI 11
+#define RG_TR_LPF_STBC_MF_KI_G_SZ 4
+#define RG_TR_LPF_STBC_MF_KP_G_MSK 0x0000f000
+#define RG_TR_LPF_STBC_MF_KP_G_I_MSK 0xffff0fff
+#define RG_TR_LPF_STBC_MF_KP_G_SFT 12
+#define RG_TR_LPF_STBC_MF_KP_G_HI 15
+#define RG_TR_LPF_STBC_MF_KP_G_SZ 4
+#define RG_MODE_REG_IN_80_MSK 0x0001ffff
+#define RG_MODE_REG_IN_80_I_MSK 0xfffe0000
+#define RG_MODE_REG_IN_80_SFT 0
+#define RG_MODE_REG_IN_80_HI 16
+#define RG_MODE_REG_IN_80_SZ 17
+#define RG_PARALLEL_DR_80_MSK 0x00100000
+#define RG_PARALLEL_DR_80_I_MSK 0xffefffff
+#define RG_PARALLEL_DR_80_SFT 20
+#define RG_PARALLEL_DR_80_HI 20
+#define RG_PARALLEL_DR_80_SZ 1
+#define RG_MBRUN_80_MSK 0x01000000
+#define RG_MBRUN_80_I_MSK 0xfeffffff
+#define RG_MBRUN_80_SFT 24
+#define RG_MBRUN_80_HI 24
+#define RG_MBRUN_80_SZ 1
+#define RG_SHIFT_DR_80_MSK 0x10000000
+#define RG_SHIFT_DR_80_I_MSK 0xefffffff
+#define RG_SHIFT_DR_80_SFT 28
+#define RG_SHIFT_DR_80_HI 28
+#define RG_SHIFT_DR_80_SZ 1
+#define RG_MODE_REG_SI_80_MSK 0x20000000
+#define RG_MODE_REG_SI_80_I_MSK 0xdfffffff
+#define RG_MODE_REG_SI_80_SFT 29
+#define RG_MODE_REG_SI_80_HI 29
+#define RG_MODE_REG_SI_80_SZ 1
+#define RG_SIMULATION_MODE_80_MSK 0x40000000
+#define RG_SIMULATION_MODE_80_I_MSK 0xbfffffff
+#define RG_SIMULATION_MODE_80_SFT 30
+#define RG_SIMULATION_MODE_80_HI 30
+#define RG_SIMULATION_MODE_80_SZ 1
+#define RG_DBIST_MODE_80_MSK 0x80000000
+#define RG_DBIST_MODE_80_I_MSK 0x7fffffff
+#define RG_DBIST_MODE_80_SFT 31
+#define RG_DBIST_MODE_80_HI 31
+#define RG_DBIST_MODE_80_SZ 1
+#define RG_MODE_REG_IN_64_MSK 0x0000ffff
+#define RG_MODE_REG_IN_64_I_MSK 0xffff0000
+#define RG_MODE_REG_IN_64_SFT 0
+#define RG_MODE_REG_IN_64_HI 15
+#define RG_MODE_REG_IN_64_SZ 16
+#define RG_PARALLEL_DR_64_MSK 0x00100000
+#define RG_PARALLEL_DR_64_I_MSK 0xffefffff
+#define RG_PARALLEL_DR_64_SFT 20
+#define RG_PARALLEL_DR_64_HI 20
+#define RG_PARALLEL_DR_64_SZ 1
+#define RG_MBRUN_64_MSK 0x01000000
+#define RG_MBRUN_64_I_MSK 0xfeffffff
+#define RG_MBRUN_64_SFT 24
+#define RG_MBRUN_64_HI 24
+#define RG_MBRUN_64_SZ 1
+#define RG_SHIFT_DR_64_MSK 0x10000000
+#define RG_SHIFT_DR_64_I_MSK 0xefffffff
+#define RG_SHIFT_DR_64_SFT 28
+#define RG_SHIFT_DR_64_HI 28
+#define RG_SHIFT_DR_64_SZ 1
+#define RG_MODE_REG_SI_64_MSK 0x20000000
+#define RG_MODE_REG_SI_64_I_MSK 0xdfffffff
+#define RG_MODE_REG_SI_64_SFT 29
+#define RG_MODE_REG_SI_64_HI 29
+#define RG_MODE_REG_SI_64_SZ 1
+#define RG_SIMULATION_MODE_64_MSK 0x40000000
+#define RG_SIMULATION_MODE_64_I_MSK 0xbfffffff
+#define RG_SIMULATION_MODE_64_SFT 30
+#define RG_SIMULATION_MODE_64_HI 30
+#define RG_SIMULATION_MODE_64_SZ 1
+#define RG_DBIST_MODE_64_MSK 0x80000000
+#define RG_DBIST_MODE_64_I_MSK 0x7fffffff
+#define RG_DBIST_MODE_64_SFT 31
+#define RG_DBIST_MODE_64_HI 31
+#define RG_DBIST_MODE_64_SZ 1
+#define RO_MODE_REG_OUT_80_MSK 0x0001ffff
+#define RO_MODE_REG_OUT_80_I_MSK 0xfffe0000
+#define RO_MODE_REG_OUT_80_SFT 0
+#define RO_MODE_REG_OUT_80_HI 16
+#define RO_MODE_REG_OUT_80_SZ 17
+#define RO_MODE_REG_SO_80_MSK 0x01000000
+#define RO_MODE_REG_SO_80_I_MSK 0xfeffffff
+#define RO_MODE_REG_SO_80_SFT 24
+#define RO_MODE_REG_SO_80_HI 24
+#define RO_MODE_REG_SO_80_SZ 1
+#define RO_MONITOR_BUS_80_MSK 0x003fffff
+#define RO_MONITOR_BUS_80_I_MSK 0xffc00000
+#define RO_MONITOR_BUS_80_SFT 0
+#define RO_MONITOR_BUS_80_HI 21
+#define RO_MONITOR_BUS_80_SZ 22
+#define RO_MODE_REG_OUT_64_MSK 0x0000ffff
+#define RO_MODE_REG_OUT_64_I_MSK 0xffff0000
+#define RO_MODE_REG_OUT_64_SFT 0
+#define RO_MODE_REG_OUT_64_HI 15
+#define RO_MODE_REG_OUT_64_SZ 16
+#define RO_MODE_REG_SO_64_MSK 0x01000000
+#define RO_MODE_REG_SO_64_I_MSK 0xfeffffff
+#define RO_MODE_REG_SO_64_SFT 24
+#define RO_MODE_REG_SO_64_HI 24
+#define RO_MODE_REG_SO_64_SZ 1
+#define RO_MONITOR_BUS_64_MSK 0x0007ffff
+#define RO_MONITOR_BUS_64_I_MSK 0xfff80000
+#define RO_MONITOR_BUS_64_SFT 0
+#define RO_MONITOR_BUS_64_HI 18
+#define RO_MONITOR_BUS_64_SZ 19
+#define RO_SPECTRUM_DATA_MSK 0xffffffff
+#define RO_SPECTRUM_DATA_I_MSK 0x00000000
+#define RO_SPECTRUM_DATA_SFT 0
+#define RO_SPECTRUM_DATA_HI 31
+#define RO_SPECTRUM_DATA_SZ 32
+#define GN_SNR_MSK 0x0000007f
+#define GN_SNR_I_MSK 0xffffff80
+#define GN_SNR_SFT 0
+#define GN_SNR_HI 6
+#define GN_SNR_SZ 7
+#define GN_NOISE_PWR_MSK 0x00007f00
+#define GN_NOISE_PWR_I_MSK 0xffff80ff
+#define GN_NOISE_PWR_SFT 8
+#define GN_NOISE_PWR_HI 14
+#define GN_NOISE_PWR_SZ 7
+#define GN_RCPI_MSK 0x007f0000
+#define GN_RCPI_I_MSK 0xff80ffff
+#define GN_RCPI_SFT 16
+#define GN_RCPI_HI 22
+#define GN_RCPI_SZ 7
+#define GN_SIGNAL_PWR_MSK 0x7f000000
+#define GN_SIGNAL_PWR_I_MSK 0x80ffffff
+#define GN_SIGNAL_PWR_SFT 24
+#define GN_SIGNAL_PWR_HI 30
+#define GN_SIGNAL_PWR_SZ 7
+#define RO_FREQ_OS_LTS_MSK 0x00007fff
+#define RO_FREQ_OS_LTS_I_MSK 0xffff8000
+#define RO_FREQ_OS_LTS_SFT 0
+#define RO_FREQ_OS_LTS_HI 14
+#define RO_FREQ_OS_LTS_SZ 15
+#define CSTATE_MSK 0x000f0000
+#define CSTATE_I_MSK 0xfff0ffff
+#define CSTATE_SFT 16
+#define CSTATE_HI 19
+#define CSTATE_SZ 4
+#define SIGNAL_FIELD0_MSK 0x00ffffff
+#define SIGNAL_FIELD0_I_MSK 0xff000000
+#define SIGNAL_FIELD0_SFT 0
+#define SIGNAL_FIELD0_HI 23
+#define SIGNAL_FIELD0_SZ 24
+#define SIGNAL_FIELD1_MSK 0x00ffffff
+#define SIGNAL_FIELD1_I_MSK 0xff000000
+#define SIGNAL_FIELD1_SFT 0
+#define SIGNAL_FIELD1_HI 23
+#define SIGNAL_FIELD1_SZ 24
+#define GN_PACKET_ERR_CNT_MSK 0x0000ffff
+#define GN_PACKET_ERR_CNT_I_MSK 0xffff0000
+#define GN_PACKET_ERR_CNT_SFT 0
+#define GN_PACKET_ERR_CNT_HI 15
+#define GN_PACKET_ERR_CNT_SZ 16
+#define GN_PACKET_CNT_MSK 0x0000ffff
+#define GN_PACKET_CNT_I_MSK 0xffff0000
+#define GN_PACKET_CNT_SFT 0
+#define GN_PACKET_CNT_HI 15
+#define GN_PACKET_CNT_SZ 16
+#define GN_CCA_CNT_MSK 0xffff0000
+#define GN_CCA_CNT_I_MSK 0x0000ffff
+#define GN_CCA_CNT_SFT 16
+#define GN_CCA_CNT_HI 31
+#define GN_CCA_CNT_SZ 16
+#define GN_LENGTH_FIELD_MSK 0x0000ffff
+#define GN_LENGTH_FIELD_I_MSK 0xffff0000
+#define GN_LENGTH_FIELD_SFT 0
+#define GN_LENGTH_FIELD_HI 15
+#define GN_LENGTH_FIELD_SZ 16
+#define GN_SERVICE_FIELD_MSK 0xffff0000
+#define GN_SERVICE_FIELD_I_MSK 0x0000ffff
+#define GN_SERVICE_FIELD_SFT 16
+#define GN_SERVICE_FIELD_HI 31
+#define GN_SERVICE_FIELD_SZ 16
+#define RO_HT_MCS_40M_MSK 0x0000007f
+#define RO_HT_MCS_40M_I_MSK 0xffffff80
+#define RO_HT_MCS_40M_SFT 0
+#define RO_HT_MCS_40M_HI 6
+#define RO_HT_MCS_40M_SZ 7
+#define RO_L_RATE_40M_MSK 0x00003f00
+#define RO_L_RATE_40M_I_MSK 0xffffc0ff
+#define RO_L_RATE_40M_SFT 8
+#define RO_L_RATE_40M_HI 13
+#define RO_L_RATE_40M_SZ 6
+#define RG_DAGC_CNT_TH_MSK 0x00000003
+#define RG_DAGC_CNT_TH_I_MSK 0xfffffffc
+#define RG_DAGC_CNT_TH_SFT 0
+#define RG_DAGC_CNT_TH_HI 1
+#define RG_DAGC_CNT_TH_SZ 2
+#define RG_PACKET_STAT_EN_11GN_MSK 0x00100000
+#define RG_PACKET_STAT_EN_11GN_I_MSK 0xffefffff
+#define RG_PACKET_STAT_EN_11GN_SFT 20
+#define RG_PACKET_STAT_EN_11GN_HI 20
+#define RG_PACKET_STAT_EN_11GN_SZ 1
+#define RX_PHY_11GN_SOFT_RST_N_MSK 0x00000001
+#define RX_PHY_11GN_SOFT_RST_N_I_MSK 0xfffffffe
+#define RX_PHY_11GN_SOFT_RST_N_SFT 0
+#define RX_PHY_11GN_SOFT_RST_N_HI 0
+#define RX_PHY_11GN_SOFT_RST_N_SZ 1
+#define RG_RIFS_EN_MSK 0x00000002
+#define RG_RIFS_EN_I_MSK 0xfffffffd
+#define RG_RIFS_EN_SFT 1
+#define RG_RIFS_EN_HI 1
+#define RG_RIFS_EN_SZ 1
+#define RG_STBC_EN_MSK 0x00000004
+#define RG_STBC_EN_I_MSK 0xfffffffb
+#define RG_STBC_EN_SFT 2
+#define RG_STBC_EN_HI 2
+#define RG_STBC_EN_SZ 1
+#define RG_COR_SEL_MSK 0x00000008
+#define RG_COR_SEL_I_MSK 0xfffffff7
+#define RG_COR_SEL_SFT 3
+#define RG_COR_SEL_HI 3
+#define RG_COR_SEL_SZ 1
+#define RG_INI_PHASE_MSK 0x00000030
+#define RG_INI_PHASE_I_MSK 0xffffffcf
+#define RG_INI_PHASE_SFT 4
+#define RG_INI_PHASE_HI 5
+#define RG_INI_PHASE_SZ 2
+#define RG_HT_LTF_SEL_EQ_MSK 0x00000040
+#define RG_HT_LTF_SEL_EQ_I_MSK 0xffffffbf
+#define RG_HT_LTF_SEL_EQ_SFT 6
+#define RG_HT_LTF_SEL_EQ_HI 6
+#define RG_HT_LTF_SEL_EQ_SZ 1
+#define RG_HT_LTF_SEL_PILOT_MSK 0x00000080
+#define RG_HT_LTF_SEL_PILOT_I_MSK 0xffffff7f
+#define RG_HT_LTF_SEL_PILOT_SFT 7
+#define RG_HT_LTF_SEL_PILOT_HI 7
+#define RG_HT_LTF_SEL_PILOT_SZ 1
+#define RG_CCA_PWR_SEL_MSK 0x00000200
+#define RG_CCA_PWR_SEL_I_MSK 0xfffffdff
+#define RG_CCA_PWR_SEL_SFT 9
+#define RG_CCA_PWR_SEL_HI 9
+#define RG_CCA_PWR_SEL_SZ 1
+#define RG_CCA_XSCOR_PWR_SEL_MSK 0x00000400
+#define RG_CCA_XSCOR_PWR_SEL_I_MSK 0xfffffbff
+#define RG_CCA_XSCOR_PWR_SEL_SFT 10
+#define RG_CCA_XSCOR_PWR_SEL_HI 10
+#define RG_CCA_XSCOR_PWR_SEL_SZ 1
+#define RG_CCA_XSCOR_AVGPWR_SEL_MSK 0x00000800
+#define RG_CCA_XSCOR_AVGPWR_SEL_I_MSK 0xfffff7ff
+#define RG_CCA_XSCOR_AVGPWR_SEL_SFT 11
+#define RG_CCA_XSCOR_AVGPWR_SEL_HI 11
+#define RG_CCA_XSCOR_AVGPWR_SEL_SZ 1
+#define RG_DEBUG_SEL_MSK 0x0000f000
+#define RG_DEBUG_SEL_I_MSK 0xffff0fff
+#define RG_DEBUG_SEL_SFT 12
+#define RG_DEBUG_SEL_HI 15
+#define RG_DEBUG_SEL_SZ 4
+#define RG_POST_CLK_EN_MSK 0x00010000
+#define RG_POST_CLK_EN_I_MSK 0xfffeffff
+#define RG_POST_CLK_EN_SFT 16
+#define RG_POST_CLK_EN_HI 16
+#define RG_POST_CLK_EN_SZ 1
+#define IQCAL_RF_TX_EN_MSK 0x00000001
+#define IQCAL_RF_TX_EN_I_MSK 0xfffffffe
+#define IQCAL_RF_TX_EN_SFT 0
+#define IQCAL_RF_TX_EN_HI 0
+#define IQCAL_RF_TX_EN_SZ 1
+#define IQCAL_RF_TX_PA_EN_MSK 0x00000002
+#define IQCAL_RF_TX_PA_EN_I_MSK 0xfffffffd
+#define IQCAL_RF_TX_PA_EN_SFT 1
+#define IQCAL_RF_TX_PA_EN_HI 1
+#define IQCAL_RF_TX_PA_EN_SZ 1
+#define IQCAL_RF_TX_DAC_EN_MSK 0x00000004
+#define IQCAL_RF_TX_DAC_EN_I_MSK 0xfffffffb
+#define IQCAL_RF_TX_DAC_EN_SFT 2
+#define IQCAL_RF_TX_DAC_EN_HI 2
+#define IQCAL_RF_TX_DAC_EN_SZ 1
+#define IQCAL_RF_RX_AGC_MSK 0x00000008
+#define IQCAL_RF_RX_AGC_I_MSK 0xfffffff7
+#define IQCAL_RF_RX_AGC_SFT 3
+#define IQCAL_RF_RX_AGC_HI 3
+#define IQCAL_RF_RX_AGC_SZ 1
+#define IQCAL_RF_PGAG_MSK 0x00000f00
+#define IQCAL_RF_PGAG_I_MSK 0xfffff0ff
+#define IQCAL_RF_PGAG_SFT 8
+#define IQCAL_RF_PGAG_HI 11
+#define IQCAL_RF_PGAG_SZ 4
+#define IQCAL_RF_RFG_MSK 0x00003000
+#define IQCAL_RF_RFG_I_MSK 0xffffcfff
+#define IQCAL_RF_RFG_SFT 12
+#define IQCAL_RF_RFG_HI 13
+#define IQCAL_RF_RFG_SZ 2
+#define RG_TONEGEN_FREQ_MSK 0x007f0000
+#define RG_TONEGEN_FREQ_I_MSK 0xff80ffff
+#define RG_TONEGEN_FREQ_SFT 16
+#define RG_TONEGEN_FREQ_HI 22
+#define RG_TONEGEN_FREQ_SZ 7
+#define RG_TONEGEN_EN_MSK 0x00800000
+#define RG_TONEGEN_EN_I_MSK 0xff7fffff
+#define RG_TONEGEN_EN_SFT 23
+#define RG_TONEGEN_EN_HI 23
+#define RG_TONEGEN_EN_SZ 1
+#define RG_TONEGEN_INIT_PH_MSK 0x7f000000
+#define RG_TONEGEN_INIT_PH_I_MSK 0x80ffffff
+#define RG_TONEGEN_INIT_PH_SFT 24
+#define RG_TONEGEN_INIT_PH_HI 30
+#define RG_TONEGEN_INIT_PH_SZ 7
+#define RG_TONEGEN2_FREQ_MSK 0x0000007f
+#define RG_TONEGEN2_FREQ_I_MSK 0xffffff80
+#define RG_TONEGEN2_FREQ_SFT 0
+#define RG_TONEGEN2_FREQ_HI 6
+#define RG_TONEGEN2_FREQ_SZ 7
+#define RG_TONEGEN2_EN_MSK 0x00000080
+#define RG_TONEGEN2_EN_I_MSK 0xffffff7f
+#define RG_TONEGEN2_EN_SFT 7
+#define RG_TONEGEN2_EN_HI 7
+#define RG_TONEGEN2_EN_SZ 1
+#define RG_TONEGEN2_SCALE_MSK 0x0000ff00
+#define RG_TONEGEN2_SCALE_I_MSK 0xffff00ff
+#define RG_TONEGEN2_SCALE_SFT 8
+#define RG_TONEGEN2_SCALE_HI 15
+#define RG_TONEGEN2_SCALE_SZ 8
+#define RG_TXIQ_CLP_THD_I_MSK 0x000003ff
+#define RG_TXIQ_CLP_THD_I_I_MSK 0xfffffc00
+#define RG_TXIQ_CLP_THD_I_SFT 0
+#define RG_TXIQ_CLP_THD_I_HI 9
+#define RG_TXIQ_CLP_THD_I_SZ 10
+#define RG_TXIQ_CLP_THD_Q_MSK 0x03ff0000
+#define RG_TXIQ_CLP_THD_Q_I_MSK 0xfc00ffff
+#define RG_TXIQ_CLP_THD_Q_SFT 16
+#define RG_TXIQ_CLP_THD_Q_HI 25
+#define RG_TXIQ_CLP_THD_Q_SZ 10
+#define RG_TX_I_SCALE_MSK 0x000000ff
+#define RG_TX_I_SCALE_I_MSK 0xffffff00
+#define RG_TX_I_SCALE_SFT 0
+#define RG_TX_I_SCALE_HI 7
+#define RG_TX_I_SCALE_SZ 8
+#define RG_TX_Q_SCALE_MSK 0x0000ff00
+#define RG_TX_Q_SCALE_I_MSK 0xffff00ff
+#define RG_TX_Q_SCALE_SFT 8
+#define RG_TX_Q_SCALE_HI 15
+#define RG_TX_Q_SCALE_SZ 8
+#define RG_TX_IQ_SWP_MSK 0x00010000
+#define RG_TX_IQ_SWP_I_MSK 0xfffeffff
+#define RG_TX_IQ_SWP_SFT 16
+#define RG_TX_IQ_SWP_HI 16
+#define RG_TX_IQ_SWP_SZ 1
+#define RG_TX_SGN_OUT_MSK 0x00020000
+#define RG_TX_SGN_OUT_I_MSK 0xfffdffff
+#define RG_TX_SGN_OUT_SFT 17
+#define RG_TX_SGN_OUT_HI 17
+#define RG_TX_SGN_OUT_SZ 1
+#define RG_TXIQ_EMU_IDX_MSK 0x003c0000
+#define RG_TXIQ_EMU_IDX_I_MSK 0xffc3ffff
+#define RG_TXIQ_EMU_IDX_SFT 18
+#define RG_TXIQ_EMU_IDX_HI 21
+#define RG_TXIQ_EMU_IDX_SZ 4
+#define RG_TX_IQ_SRC_MSK 0x03000000
+#define RG_TX_IQ_SRC_I_MSK 0xfcffffff
+#define RG_TX_IQ_SRC_SFT 24
+#define RG_TX_IQ_SRC_HI 25
+#define RG_TX_IQ_SRC_SZ 2
+#define RG_TX_I_DC_MSK 0x000003ff
+#define RG_TX_I_DC_I_MSK 0xfffffc00
+#define RG_TX_I_DC_SFT 0
+#define RG_TX_I_DC_HI 9
+#define RG_TX_I_DC_SZ 10
+#define RG_TX_Q_DC_MSK 0x03ff0000
+#define RG_TX_Q_DC_I_MSK 0xfc00ffff
+#define RG_TX_Q_DC_SFT 16
+#define RG_TX_Q_DC_HI 25
+#define RG_TX_Q_DC_SZ 10
+#define RG_TX_IQ_THETA_MSK 0x0000001f
+#define RG_TX_IQ_THETA_I_MSK 0xffffffe0
+#define RG_TX_IQ_THETA_SFT 0
+#define RG_TX_IQ_THETA_HI 4
+#define RG_TX_IQ_THETA_SZ 5
+#define RG_TX_IQ_ALPHA_MSK 0x00001f00
+#define RG_TX_IQ_ALPHA_I_MSK 0xffffe0ff
+#define RG_TX_IQ_ALPHA_SFT 8
+#define RG_TX_IQ_ALPHA_HI 12
+#define RG_TX_IQ_ALPHA_SZ 5
+#define RG_TXIQ_NOSHRINK_MSK 0x00002000
+#define RG_TXIQ_NOSHRINK_I_MSK 0xffffdfff
+#define RG_TXIQ_NOSHRINK_SFT 13
+#define RG_TXIQ_NOSHRINK_HI 13
+#define RG_TXIQ_NOSHRINK_SZ 1
+#define RG_TX_I_OFFSET_MSK 0x00ff0000
+#define RG_TX_I_OFFSET_I_MSK 0xff00ffff
+#define RG_TX_I_OFFSET_SFT 16
+#define RG_TX_I_OFFSET_HI 23
+#define RG_TX_I_OFFSET_SZ 8
+#define RG_TX_Q_OFFSET_MSK 0xff000000
+#define RG_TX_Q_OFFSET_I_MSK 0x00ffffff
+#define RG_TX_Q_OFFSET_SFT 24
+#define RG_TX_Q_OFFSET_HI 31
+#define RG_TX_Q_OFFSET_SZ 8
+#define RG_RX_IQ_THETA_MSK 0x0000001f
+#define RG_RX_IQ_THETA_I_MSK 0xffffffe0
+#define RG_RX_IQ_THETA_SFT 0
+#define RG_RX_IQ_THETA_HI 4
+#define RG_RX_IQ_THETA_SZ 5
+#define RG_RX_IQ_ALPHA_MSK 0x00001f00
+#define RG_RX_IQ_ALPHA_I_MSK 0xffffe0ff
+#define RG_RX_IQ_ALPHA_SFT 8
+#define RG_RX_IQ_ALPHA_HI 12
+#define RG_RX_IQ_ALPHA_SZ 5
+#define RG_RXIQ_NOSHRINK_MSK 0x00002000
+#define RG_RXIQ_NOSHRINK_I_MSK 0xffffdfff
+#define RG_RXIQ_NOSHRINK_SFT 13
+#define RG_RXIQ_NOSHRINK_HI 13
+#define RG_RXIQ_NOSHRINK_SZ 1
+#define RG_MA_DPTH_MSK 0x0000000f
+#define RG_MA_DPTH_I_MSK 0xfffffff0
+#define RG_MA_DPTH_SFT 0
+#define RG_MA_DPTH_HI 3
+#define RG_MA_DPTH_SZ 4
+#define RG_INTG_PH_MSK 0x000003f0
+#define RG_INTG_PH_I_MSK 0xfffffc0f
+#define RG_INTG_PH_SFT 4
+#define RG_INTG_PH_HI 9
+#define RG_INTG_PH_SZ 6
+#define RG_INTG_PRD_MSK 0x00001c00
+#define RG_INTG_PRD_I_MSK 0xffffe3ff
+#define RG_INTG_PRD_SFT 10
+#define RG_INTG_PRD_HI 12
+#define RG_INTG_PRD_SZ 3
+#define RG_INTG_MU_MSK 0x00006000
+#define RG_INTG_MU_I_MSK 0xffff9fff
+#define RG_INTG_MU_SFT 13
+#define RG_INTG_MU_HI 14
+#define RG_INTG_MU_SZ 2
+#define RG_IQCAL_SPRM_SELQ_MSK 0x00010000
+#define RG_IQCAL_SPRM_SELQ_I_MSK 0xfffeffff
+#define RG_IQCAL_SPRM_SELQ_SFT 16
+#define RG_IQCAL_SPRM_SELQ_HI 16
+#define RG_IQCAL_SPRM_SELQ_SZ 1
+#define RG_IQCAL_SPRM_EN_MSK 0x00020000
+#define RG_IQCAL_SPRM_EN_I_MSK 0xfffdffff
+#define RG_IQCAL_SPRM_EN_SFT 17
+#define RG_IQCAL_SPRM_EN_HI 17
+#define RG_IQCAL_SPRM_EN_SZ 1
+#define RG_IQCAL_SPRM_FREQ_MSK 0x00fc0000
+#define RG_IQCAL_SPRM_FREQ_I_MSK 0xff03ffff
+#define RG_IQCAL_SPRM_FREQ_SFT 18
+#define RG_IQCAL_SPRM_FREQ_HI 23
+#define RG_IQCAL_SPRM_FREQ_SZ 6
+#define RG_IQCAL_IQCOL_EN_MSK 0x01000000
+#define RG_IQCAL_IQCOL_EN_I_MSK 0xfeffffff
+#define RG_IQCAL_IQCOL_EN_SFT 24
+#define RG_IQCAL_IQCOL_EN_HI 24
+#define RG_IQCAL_IQCOL_EN_SZ 1
+#define RG_IQCAL_ALPHA_ESTM_EN_MSK 0x02000000
+#define RG_IQCAL_ALPHA_ESTM_EN_I_MSK 0xfdffffff
+#define RG_IQCAL_ALPHA_ESTM_EN_SFT 25
+#define RG_IQCAL_ALPHA_ESTM_EN_HI 25
+#define RG_IQCAL_ALPHA_ESTM_EN_SZ 1
+#define RG_IQCAL_DC_EN_MSK 0x04000000
+#define RG_IQCAL_DC_EN_I_MSK 0xfbffffff
+#define RG_IQCAL_DC_EN_SFT 26
+#define RG_IQCAL_DC_EN_HI 26
+#define RG_IQCAL_DC_EN_SZ 1
+#define RG_PHEST_STBY_MSK 0x08000000
+#define RG_PHEST_STBY_I_MSK 0xf7ffffff
+#define RG_PHEST_STBY_SFT 27
+#define RG_PHEST_STBY_HI 27
+#define RG_PHEST_STBY_SZ 1
+#define RG_PHEST_EN_MSK 0x10000000
+#define RG_PHEST_EN_I_MSK 0xefffffff
+#define RG_PHEST_EN_SFT 28
+#define RG_PHEST_EN_HI 28
+#define RG_PHEST_EN_SZ 1
+#define RG_GP_DIV_EN_MSK 0x20000000
+#define RG_GP_DIV_EN_I_MSK 0xdfffffff
+#define RG_GP_DIV_EN_SFT 29
+#define RG_GP_DIV_EN_HI 29
+#define RG_GP_DIV_EN_SZ 1
+#define RG_DPD_GAIN_EST_EN_MSK 0x40000000
+#define RG_DPD_GAIN_EST_EN_I_MSK 0xbfffffff
+#define RG_DPD_GAIN_EST_EN_SFT 30
+#define RG_DPD_GAIN_EST_EN_HI 30
+#define RG_DPD_GAIN_EST_EN_SZ 1
+#define RG_IQCAL_MULT_OP0_MSK 0x000003ff
+#define RG_IQCAL_MULT_OP0_I_MSK 0xfffffc00
+#define RG_IQCAL_MULT_OP0_SFT 0
+#define RG_IQCAL_MULT_OP0_HI 9
+#define RG_IQCAL_MULT_OP0_SZ 10
+#define RG_IQCAL_MULT_OP1_MSK 0x03ff0000
+#define RG_IQCAL_MULT_OP1_I_MSK 0xfc00ffff
+#define RG_IQCAL_MULT_OP1_SFT 16
+#define RG_IQCAL_MULT_OP1_HI 25
+#define RG_IQCAL_MULT_OP1_SZ 10
+#define RO_IQCAL_O_MSK 0x000fffff
+#define RO_IQCAL_O_I_MSK 0xfff00000
+#define RO_IQCAL_O_SFT 0
+#define RO_IQCAL_O_HI 19
+#define RO_IQCAL_O_SZ 20
+#define RO_IQCAL_SPRM_RDY_MSK 0x00100000
+#define RO_IQCAL_SPRM_RDY_I_MSK 0xffefffff
+#define RO_IQCAL_SPRM_RDY_SFT 20
+#define RO_IQCAL_SPRM_RDY_HI 20
+#define RO_IQCAL_SPRM_RDY_SZ 1
+#define RO_IQCAL_IQCOL_RDY_MSK 0x00200000
+#define RO_IQCAL_IQCOL_RDY_I_MSK 0xffdfffff
+#define RO_IQCAL_IQCOL_RDY_SFT 21
+#define RO_IQCAL_IQCOL_RDY_HI 21
+#define RO_IQCAL_IQCOL_RDY_SZ 1
+#define RO_IQCAL_ALPHA_ESTM_RDY_MSK 0x00400000
+#define RO_IQCAL_ALPHA_ESTM_RDY_I_MSK 0xffbfffff
+#define RO_IQCAL_ALPHA_ESTM_RDY_SFT 22
+#define RO_IQCAL_ALPHA_ESTM_RDY_HI 22
+#define RO_IQCAL_ALPHA_ESTM_RDY_SZ 1
+#define RO_IQCAL_DC_RDY_MSK 0x00800000
+#define RO_IQCAL_DC_RDY_I_MSK 0xff7fffff
+#define RO_IQCAL_DC_RDY_SFT 23
+#define RO_IQCAL_DC_RDY_HI 23
+#define RO_IQCAL_DC_RDY_SZ 1
+#define RO_IQCAL_MULT_RDY_MSK 0x01000000
+#define RO_IQCAL_MULT_RDY_I_MSK 0xfeffffff
+#define RO_IQCAL_MULT_RDY_SFT 24
+#define RO_IQCAL_MULT_RDY_HI 24
+#define RO_IQCAL_MULT_RDY_SZ 1
+#define RO_FFT_ENRG_RDY_MSK 0x02000000
+#define RO_FFT_ENRG_RDY_I_MSK 0xfdffffff
+#define RO_FFT_ENRG_RDY_SFT 25
+#define RO_FFT_ENRG_RDY_HI 25
+#define RO_FFT_ENRG_RDY_SZ 1
+#define RO_PHEST_RDY_MSK 0x04000000
+#define RO_PHEST_RDY_I_MSK 0xfbffffff
+#define RO_PHEST_RDY_SFT 26
+#define RO_PHEST_RDY_HI 26
+#define RO_PHEST_RDY_SZ 1
+#define RO_GP_DIV_RDY_MSK 0x08000000
+#define RO_GP_DIV_RDY_I_MSK 0xf7ffffff
+#define RO_GP_DIV_RDY_SFT 27
+#define RO_GP_DIV_RDY_HI 27
+#define RO_GP_DIV_RDY_SZ 1
+#define RO_GAIN_EST_RDY_MSK 0x10000000
+#define RO_GAIN_EST_RDY_I_MSK 0xefffffff
+#define RO_GAIN_EST_RDY_SFT 28
+#define RO_GAIN_EST_RDY_HI 28
+#define RO_GAIN_EST_RDY_SZ 1
+#define RO_AMP_O_MSK 0x000001ff
+#define RO_AMP_O_I_MSK 0xfffffe00
+#define RO_AMP_O_SFT 0
+#define RO_AMP_O_HI 8
+#define RO_AMP_O_SZ 9
+#define RG_RX_I_SCALE_MSK 0x000000ff
+#define RG_RX_I_SCALE_I_MSK 0xffffff00
+#define RG_RX_I_SCALE_SFT 0
+#define RG_RX_I_SCALE_HI 7
+#define RG_RX_I_SCALE_SZ 8
+#define RG_RX_Q_SCALE_MSK 0x0000ff00
+#define RG_RX_Q_SCALE_I_MSK 0xffff00ff
+#define RG_RX_Q_SCALE_SFT 8
+#define RG_RX_Q_SCALE_HI 15
+#define RG_RX_Q_SCALE_SZ 8
+#define RG_RX_I_OFFSET_MSK 0x00ff0000
+#define RG_RX_I_OFFSET_I_MSK 0xff00ffff
+#define RG_RX_I_OFFSET_SFT 16
+#define RG_RX_I_OFFSET_HI 23
+#define RG_RX_I_OFFSET_SZ 8
+#define RG_RX_Q_OFFSET_MSK 0xff000000
+#define RG_RX_Q_OFFSET_I_MSK 0x00ffffff
+#define RG_RX_Q_OFFSET_SFT 24
+#define RG_RX_Q_OFFSET_HI 31
+#define RG_RX_Q_OFFSET_SZ 8
+#define RG_RX_IQ_SWP_MSK 0x00000001
+#define RG_RX_IQ_SWP_I_MSK 0xfffffffe
+#define RG_RX_IQ_SWP_SFT 0
+#define RG_RX_IQ_SWP_HI 0
+#define RG_RX_IQ_SWP_SZ 1
+#define RG_RX_SGN_IN_MSK 0x00000002
+#define RG_RX_SGN_IN_I_MSK 0xfffffffd
+#define RG_RX_SGN_IN_SFT 1
+#define RG_RX_SGN_IN_HI 1
+#define RG_RX_SGN_IN_SZ 1
+#define RG_RX_IQ_SRC_MSK 0x0000000c
+#define RG_RX_IQ_SRC_I_MSK 0xfffffff3
+#define RG_RX_IQ_SRC_SFT 2
+#define RG_RX_IQ_SRC_HI 3
+#define RG_RX_IQ_SRC_SZ 2
+#define RG_ACI_GAIN_MSK 0x00000ff0
+#define RG_ACI_GAIN_I_MSK 0xfffff00f
+#define RG_ACI_GAIN_SFT 4
+#define RG_ACI_GAIN_HI 11
+#define RG_ACI_GAIN_SZ 8
+#define RG_FFT_EN_MSK 0x00001000
+#define RG_FFT_EN_I_MSK 0xffffefff
+#define RG_FFT_EN_SFT 12
+#define RG_FFT_EN_HI 12
+#define RG_FFT_EN_SZ 1
+#define RG_FFT_MOD_MSK 0x00002000
+#define RG_FFT_MOD_I_MSK 0xffffdfff
+#define RG_FFT_MOD_SFT 13
+#define RG_FFT_MOD_HI 13
+#define RG_FFT_MOD_SZ 1
+#define RG_FFT_SCALE_MSK 0x00ffc000
+#define RG_FFT_SCALE_I_MSK 0xff003fff
+#define RG_FFT_SCALE_SFT 14
+#define RG_FFT_SCALE_HI 23
+#define RG_FFT_SCALE_SZ 10
+#define RG_FFT_ENRG_FREQ_MSK 0x3f000000
+#define RG_FFT_ENRG_FREQ_I_MSK 0xc0ffffff
+#define RG_FFT_ENRG_FREQ_SFT 24
+#define RG_FFT_ENRG_FREQ_HI 29
+#define RG_FFT_ENRG_FREQ_SZ 6
+#define RG_FPGA_80M_PH_UP_MSK 0x40000000
+#define RG_FPGA_80M_PH_UP_I_MSK 0xbfffffff
+#define RG_FPGA_80M_PH_UP_SFT 30
+#define RG_FPGA_80M_PH_UP_HI 30
+#define RG_FPGA_80M_PH_UP_SZ 1
+#define RG_FPGA_80M_PH_STP_MSK 0x80000000
+#define RG_FPGA_80M_PH_STP_I_MSK 0x7fffffff
+#define RG_FPGA_80M_PH_STP_SFT 31
+#define RG_FPGA_80M_PH_STP_HI 31
+#define RG_FPGA_80M_PH_STP_SZ 1
+#define RG_ADC2LA_SEL_MSK 0x00000001
+#define RG_ADC2LA_SEL_I_MSK 0xfffffffe
+#define RG_ADC2LA_SEL_SFT 0
+#define RG_ADC2LA_SEL_HI 0
+#define RG_ADC2LA_SEL_SZ 1
+#define RG_ADC2LA_CLKPH_MSK 0x00000002
+#define RG_ADC2LA_CLKPH_I_MSK 0xfffffffd
+#define RG_ADC2LA_CLKPH_SFT 1
+#define RG_ADC2LA_CLKPH_HI 1
+#define RG_ADC2LA_CLKPH_SZ 1
+#define RG_RXIQ_EMU_IDX_MSK 0x0000000f
+#define RG_RXIQ_EMU_IDX_I_MSK 0xfffffff0
+#define RG_RXIQ_EMU_IDX_SFT 0
+#define RG_RXIQ_EMU_IDX_HI 3
+#define RG_RXIQ_EMU_IDX_SZ 4
+#define RG_IQCAL_BP_ACI_MSK 0x00000010
+#define RG_IQCAL_BP_ACI_I_MSK 0xffffffef
+#define RG_IQCAL_BP_ACI_SFT 4
+#define RG_IQCAL_BP_ACI_HI 4
+#define RG_IQCAL_BP_ACI_SZ 1
+#define RG_DPD_AM_EN_MSK 0x00000001
+#define RG_DPD_AM_EN_I_MSK 0xfffffffe
+#define RG_DPD_AM_EN_SFT 0
+#define RG_DPD_AM_EN_HI 0
+#define RG_DPD_AM_EN_SZ 1
+#define RG_DPD_PM_EN_MSK 0x00000002
+#define RG_DPD_PM_EN_I_MSK 0xfffffffd
+#define RG_DPD_PM_EN_SFT 1
+#define RG_DPD_PM_EN_HI 1
+#define RG_DPD_PM_EN_SZ 1
+#define RG_DPD_PM_AMSEL_MSK 0x00000004
+#define RG_DPD_PM_AMSEL_I_MSK 0xfffffffb
+#define RG_DPD_PM_AMSEL_SFT 2
+#define RG_DPD_PM_AMSEL_HI 2
+#define RG_DPD_PM_AMSEL_SZ 1
+#define RG_DPD_020_GAIN_MSK 0x000003ff
+#define RG_DPD_020_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_020_GAIN_SFT 0
+#define RG_DPD_020_GAIN_HI 9
+#define RG_DPD_020_GAIN_SZ 10
+#define RG_DPD_040_GAIN_MSK 0x03ff0000
+#define RG_DPD_040_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_040_GAIN_SFT 16
+#define RG_DPD_040_GAIN_HI 25
+#define RG_DPD_040_GAIN_SZ 10
+#define RG_DPD_060_GAIN_MSK 0x000003ff
+#define RG_DPD_060_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_060_GAIN_SFT 0
+#define RG_DPD_060_GAIN_HI 9
+#define RG_DPD_060_GAIN_SZ 10
+#define RG_DPD_080_GAIN_MSK 0x03ff0000
+#define RG_DPD_080_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_080_GAIN_SFT 16
+#define RG_DPD_080_GAIN_HI 25
+#define RG_DPD_080_GAIN_SZ 10
+#define RG_DPD_0A0_GAIN_MSK 0x000003ff
+#define RG_DPD_0A0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0A0_GAIN_SFT 0
+#define RG_DPD_0A0_GAIN_HI 9
+#define RG_DPD_0A0_GAIN_SZ 10
+#define RG_DPD_0C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_0C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_0C0_GAIN_SFT 16
+#define RG_DPD_0C0_GAIN_HI 25
+#define RG_DPD_0C0_GAIN_SZ 10
+#define RG_DPD_0D0_GAIN_MSK 0x000003ff
+#define RG_DPD_0D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0D0_GAIN_SFT 0
+#define RG_DPD_0D0_GAIN_HI 9
+#define RG_DPD_0D0_GAIN_SZ 10
+#define RG_DPD_0E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_0E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_0E0_GAIN_SFT 16
+#define RG_DPD_0E0_GAIN_HI 25
+#define RG_DPD_0E0_GAIN_SZ 10
+#define RG_DPD_0F0_GAIN_MSK 0x000003ff
+#define RG_DPD_0F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_0F0_GAIN_SFT 0
+#define RG_DPD_0F0_GAIN_HI 9
+#define RG_DPD_0F0_GAIN_SZ 10
+#define RG_DPD_100_GAIN_MSK 0x03ff0000
+#define RG_DPD_100_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_100_GAIN_SFT 16
+#define RG_DPD_100_GAIN_HI 25
+#define RG_DPD_100_GAIN_SZ 10
+#define RG_DPD_110_GAIN_MSK 0x000003ff
+#define RG_DPD_110_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_110_GAIN_SFT 0
+#define RG_DPD_110_GAIN_HI 9
+#define RG_DPD_110_GAIN_SZ 10
+#define RG_DPD_120_GAIN_MSK 0x03ff0000
+#define RG_DPD_120_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_120_GAIN_SFT 16
+#define RG_DPD_120_GAIN_HI 25
+#define RG_DPD_120_GAIN_SZ 10
+#define RG_DPD_130_GAIN_MSK 0x000003ff
+#define RG_DPD_130_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_130_GAIN_SFT 0
+#define RG_DPD_130_GAIN_HI 9
+#define RG_DPD_130_GAIN_SZ 10
+#define RG_DPD_140_GAIN_MSK 0x03ff0000
+#define RG_DPD_140_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_140_GAIN_SFT 16
+#define RG_DPD_140_GAIN_HI 25
+#define RG_DPD_140_GAIN_SZ 10
+#define RG_DPD_150_GAIN_MSK 0x000003ff
+#define RG_DPD_150_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_150_GAIN_SFT 0
+#define RG_DPD_150_GAIN_HI 9
+#define RG_DPD_150_GAIN_SZ 10
+#define RG_DPD_160_GAIN_MSK 0x03ff0000
+#define RG_DPD_160_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_160_GAIN_SFT 16
+#define RG_DPD_160_GAIN_HI 25
+#define RG_DPD_160_GAIN_SZ 10
+#define RG_DPD_170_GAIN_MSK 0x000003ff
+#define RG_DPD_170_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_170_GAIN_SFT 0
+#define RG_DPD_170_GAIN_HI 9
+#define RG_DPD_170_GAIN_SZ 10
+#define RG_DPD_180_GAIN_MSK 0x03ff0000
+#define RG_DPD_180_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_180_GAIN_SFT 16
+#define RG_DPD_180_GAIN_HI 25
+#define RG_DPD_180_GAIN_SZ 10
+#define RG_DPD_190_GAIN_MSK 0x000003ff
+#define RG_DPD_190_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_190_GAIN_SFT 0
+#define RG_DPD_190_GAIN_HI 9
+#define RG_DPD_190_GAIN_SZ 10
+#define RG_DPD_1A0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1A0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1A0_GAIN_SFT 16
+#define RG_DPD_1A0_GAIN_HI 25
+#define RG_DPD_1A0_GAIN_SZ 10
+#define RG_DPD_1B0_GAIN_MSK 0x000003ff
+#define RG_DPD_1B0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1B0_GAIN_SFT 0
+#define RG_DPD_1B0_GAIN_HI 9
+#define RG_DPD_1B0_GAIN_SZ 10
+#define RG_DPD_1C0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1C0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1C0_GAIN_SFT 16
+#define RG_DPD_1C0_GAIN_HI 25
+#define RG_DPD_1C0_GAIN_SZ 10
+#define RG_DPD_1D0_GAIN_MSK 0x000003ff
+#define RG_DPD_1D0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1D0_GAIN_SFT 0
+#define RG_DPD_1D0_GAIN_HI 9
+#define RG_DPD_1D0_GAIN_SZ 10
+#define RG_DPD_1E0_GAIN_MSK 0x03ff0000
+#define RG_DPD_1E0_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_1E0_GAIN_SFT 16
+#define RG_DPD_1E0_GAIN_HI 25
+#define RG_DPD_1E0_GAIN_SZ 10
+#define RG_DPD_1F0_GAIN_MSK 0x000003ff
+#define RG_DPD_1F0_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_1F0_GAIN_SFT 0
+#define RG_DPD_1F0_GAIN_HI 9
+#define RG_DPD_1F0_GAIN_SZ 10
+#define RG_DPD_200_GAIN_MSK 0x03ff0000
+#define RG_DPD_200_GAIN_I_MSK 0xfc00ffff
+#define RG_DPD_200_GAIN_SFT 16
+#define RG_DPD_200_GAIN_HI 25
+#define RG_DPD_200_GAIN_SZ 10
+#define RG_DPD_020_PH_MSK 0x00001fff
+#define RG_DPD_020_PH_I_MSK 0xffffe000
+#define RG_DPD_020_PH_SFT 0
+#define RG_DPD_020_PH_HI 12
+#define RG_DPD_020_PH_SZ 13
+#define RG_DPD_040_PH_MSK 0x1fff0000
+#define RG_DPD_040_PH_I_MSK 0xe000ffff
+#define RG_DPD_040_PH_SFT 16
+#define RG_DPD_040_PH_HI 28
+#define RG_DPD_040_PH_SZ 13
+#define RG_DPD_060_PH_MSK 0x00001fff
+#define RG_DPD_060_PH_I_MSK 0xffffe000
+#define RG_DPD_060_PH_SFT 0
+#define RG_DPD_060_PH_HI 12
+#define RG_DPD_060_PH_SZ 13
+#define RG_DPD_080_PH_MSK 0x1fff0000
+#define RG_DPD_080_PH_I_MSK 0xe000ffff
+#define RG_DPD_080_PH_SFT 16
+#define RG_DPD_080_PH_HI 28
+#define RG_DPD_080_PH_SZ 13
+#define RG_DPD_0A0_PH_MSK 0x00001fff
+#define RG_DPD_0A0_PH_I_MSK 0xffffe000
+#define RG_DPD_0A0_PH_SFT 0
+#define RG_DPD_0A0_PH_HI 12
+#define RG_DPD_0A0_PH_SZ 13
+#define RG_DPD_0C0_PH_MSK 0x1fff0000
+#define RG_DPD_0C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_0C0_PH_SFT 16
+#define RG_DPD_0C0_PH_HI 28
+#define RG_DPD_0C0_PH_SZ 13
+#define RG_DPD_0D0_PH_MSK 0x00001fff
+#define RG_DPD_0D0_PH_I_MSK 0xffffe000
+#define RG_DPD_0D0_PH_SFT 0
+#define RG_DPD_0D0_PH_HI 12
+#define RG_DPD_0D0_PH_SZ 13
+#define RG_DPD_0E0_PH_MSK 0x1fff0000
+#define RG_DPD_0E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_0E0_PH_SFT 16
+#define RG_DPD_0E0_PH_HI 28
+#define RG_DPD_0E0_PH_SZ 13
+#define RG_DPD_0F0_PH_MSK 0x00001fff
+#define RG_DPD_0F0_PH_I_MSK 0xffffe000
+#define RG_DPD_0F0_PH_SFT 0
+#define RG_DPD_0F0_PH_HI 12
+#define RG_DPD_0F0_PH_SZ 13
+#define RG_DPD_100_PH_MSK 0x1fff0000
+#define RG_DPD_100_PH_I_MSK 0xe000ffff
+#define RG_DPD_100_PH_SFT 16
+#define RG_DPD_100_PH_HI 28
+#define RG_DPD_100_PH_SZ 13
+#define RG_DPD_110_PH_MSK 0x00001fff
+#define RG_DPD_110_PH_I_MSK 0xffffe000
+#define RG_DPD_110_PH_SFT 0
+#define RG_DPD_110_PH_HI 12
+#define RG_DPD_110_PH_SZ 13
+#define RG_DPD_120_PH_MSK 0x1fff0000
+#define RG_DPD_120_PH_I_MSK 0xe000ffff
+#define RG_DPD_120_PH_SFT 16
+#define RG_DPD_120_PH_HI 28
+#define RG_DPD_120_PH_SZ 13
+#define RG_DPD_130_PH_MSK 0x00001fff
+#define RG_DPD_130_PH_I_MSK 0xffffe000
+#define RG_DPD_130_PH_SFT 0
+#define RG_DPD_130_PH_HI 12
+#define RG_DPD_130_PH_SZ 13
+#define RG_DPD_140_PH_MSK 0x1fff0000
+#define RG_DPD_140_PH_I_MSK 0xe000ffff
+#define RG_DPD_140_PH_SFT 16
+#define RG_DPD_140_PH_HI 28
+#define RG_DPD_140_PH_SZ 13
+#define RG_DPD_150_PH_MSK 0x00001fff
+#define RG_DPD_150_PH_I_MSK 0xffffe000
+#define RG_DPD_150_PH_SFT 0
+#define RG_DPD_150_PH_HI 12
+#define RG_DPD_150_PH_SZ 13
+#define RG_DPD_160_PH_MSK 0x1fff0000
+#define RG_DPD_160_PH_I_MSK 0xe000ffff
+#define RG_DPD_160_PH_SFT 16
+#define RG_DPD_160_PH_HI 28
+#define RG_DPD_160_PH_SZ 13
+#define RG_DPD_170_PH_MSK 0x00001fff
+#define RG_DPD_170_PH_I_MSK 0xffffe000
+#define RG_DPD_170_PH_SFT 0
+#define RG_DPD_170_PH_HI 12
+#define RG_DPD_170_PH_SZ 13
+#define RG_DPD_180_PH_MSK 0x1fff0000
+#define RG_DPD_180_PH_I_MSK 0xe000ffff
+#define RG_DPD_180_PH_SFT 16
+#define RG_DPD_180_PH_HI 28
+#define RG_DPD_180_PH_SZ 13
+#define RG_DPD_190_PH_MSK 0x00001fff
+#define RG_DPD_190_PH_I_MSK 0xffffe000
+#define RG_DPD_190_PH_SFT 0
+#define RG_DPD_190_PH_HI 12
+#define RG_DPD_190_PH_SZ 13
+#define RG_DPD_1A0_PH_MSK 0x1fff0000
+#define RG_DPD_1A0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1A0_PH_SFT 16
+#define RG_DPD_1A0_PH_HI 28
+#define RG_DPD_1A0_PH_SZ 13
+#define RG_DPD_1B0_PH_MSK 0x00001fff
+#define RG_DPD_1B0_PH_I_MSK 0xffffe000
+#define RG_DPD_1B0_PH_SFT 0
+#define RG_DPD_1B0_PH_HI 12
+#define RG_DPD_1B0_PH_SZ 13
+#define RG_DPD_1C0_PH_MSK 0x1fff0000
+#define RG_DPD_1C0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1C0_PH_SFT 16
+#define RG_DPD_1C0_PH_HI 28
+#define RG_DPD_1C0_PH_SZ 13
+#define RG_DPD_1D0_PH_MSK 0x00001fff
+#define RG_DPD_1D0_PH_I_MSK 0xffffe000
+#define RG_DPD_1D0_PH_SFT 0
+#define RG_DPD_1D0_PH_HI 12
+#define RG_DPD_1D0_PH_SZ 13
+#define RG_DPD_1E0_PH_MSK 0x1fff0000
+#define RG_DPD_1E0_PH_I_MSK 0xe000ffff
+#define RG_DPD_1E0_PH_SFT 16
+#define RG_DPD_1E0_PH_HI 28
+#define RG_DPD_1E0_PH_SZ 13
+#define RG_DPD_1F0_PH_MSK 0x00001fff
+#define RG_DPD_1F0_PH_I_MSK 0xffffe000
+#define RG_DPD_1F0_PH_SFT 0
+#define RG_DPD_1F0_PH_HI 12
+#define RG_DPD_1F0_PH_SZ 13
+#define RG_DPD_200_PH_MSK 0x1fff0000
+#define RG_DPD_200_PH_I_MSK 0xe000ffff
+#define RG_DPD_200_PH_SFT 16
+#define RG_DPD_200_PH_HI 28
+#define RG_DPD_200_PH_SZ 13
+#define RG_DPD_GAIN_EST_Y0_MSK 0x000001ff
+#define RG_DPD_GAIN_EST_Y0_I_MSK 0xfffffe00
+#define RG_DPD_GAIN_EST_Y0_SFT 0
+#define RG_DPD_GAIN_EST_Y0_HI 8
+#define RG_DPD_GAIN_EST_Y0_SZ 9
+#define RG_DPD_GAIN_EST_Y1_MSK 0x01ff0000
+#define RG_DPD_GAIN_EST_Y1_I_MSK 0xfe00ffff
+#define RG_DPD_GAIN_EST_Y1_SFT 16
+#define RG_DPD_GAIN_EST_Y1_HI 24
+#define RG_DPD_GAIN_EST_Y1_SZ 9
+#define RG_DPD_LOOP_GAIN_MSK 0x000003ff
+#define RG_DPD_LOOP_GAIN_I_MSK 0xfffffc00
+#define RG_DPD_LOOP_GAIN_SFT 0
+#define RG_DPD_LOOP_GAIN_HI 9
+#define RG_DPD_LOOP_GAIN_SZ 10
+#define RG_DPD_GAIN_EST_X0_MSK 0x000001ff
+#define RG_DPD_GAIN_EST_X0_I_MSK 0xfffffe00
+#define RG_DPD_GAIN_EST_X0_SFT 0
+#define RG_DPD_GAIN_EST_X0_HI 8
+#define RG_DPD_GAIN_EST_X0_SZ 9
+#define RO_DPD_GAIN_MSK 0x03ff0000
+#define RO_DPD_GAIN_I_MSK 0xfc00ffff
+#define RO_DPD_GAIN_SFT 16
+#define RO_DPD_GAIN_HI 25
+#define RO_DPD_GAIN_SZ 10
+#define TX_SCALE_11B_MSK 0x000000ff
+#define TX_SCALE_11B_I_MSK 0xffffff00
+#define TX_SCALE_11B_SFT 0
+#define TX_SCALE_11B_HI 7
+#define TX_SCALE_11B_SZ 8
+#define TX_SCALE_11B_P0D5_MSK 0x0000ff00
+#define TX_SCALE_11B_P0D5_I_MSK 0xffff00ff
+#define TX_SCALE_11B_P0D5_SFT 8
+#define TX_SCALE_11B_P0D5_HI 15
+#define TX_SCALE_11B_P0D5_SZ 8
+#define TX_SCALE_11G_MSK 0x00ff0000
+#define TX_SCALE_11G_I_MSK 0xff00ffff
+#define TX_SCALE_11G_SFT 16
+#define TX_SCALE_11G_HI 23
+#define TX_SCALE_11G_SZ 8
+#define TX_SCALE_11G_P0D5_MSK 0xff000000
+#define TX_SCALE_11G_P0D5_I_MSK 0x00ffffff
+#define TX_SCALE_11G_P0D5_SFT 24
+#define TX_SCALE_11G_P0D5_HI 31
+#define TX_SCALE_11G_P0D5_SZ 8
+#define RG_EN_MANUAL_MSK 0x00000001
+#define RG_EN_MANUAL_I_MSK 0xfffffffe
+#define RG_EN_MANUAL_SFT 0
+#define RG_EN_MANUAL_HI 0
+#define RG_EN_MANUAL_SZ 1
+#define RG_TX_EN_MSK 0x00000002
+#define RG_TX_EN_I_MSK 0xfffffffd
+#define RG_TX_EN_SFT 1
+#define RG_TX_EN_HI 1
+#define RG_TX_EN_SZ 1
+#define RG_TX_PA_EN_MSK 0x00000004
+#define RG_TX_PA_EN_I_MSK 0xfffffffb
+#define RG_TX_PA_EN_SFT 2
+#define RG_TX_PA_EN_HI 2
+#define RG_TX_PA_EN_SZ 1
+#define RG_TX_DAC_EN_MSK 0x00000008
+#define RG_TX_DAC_EN_I_MSK 0xfffffff7
+#define RG_TX_DAC_EN_SFT 3
+#define RG_TX_DAC_EN_HI 3
+#define RG_TX_DAC_EN_SZ 1
+#define RG_RX_AGC_MSK 0x00000010
+#define RG_RX_AGC_I_MSK 0xffffffef
+#define RG_RX_AGC_SFT 4
+#define RG_RX_AGC_HI 4
+#define RG_RX_AGC_SZ 1
+#define RG_RX_GAIN_MANUAL_MSK 0x00000020
+#define RG_RX_GAIN_MANUAL_I_MSK 0xffffffdf
+#define RG_RX_GAIN_MANUAL_SFT 5
+#define RG_RX_GAIN_MANUAL_HI 5
+#define RG_RX_GAIN_MANUAL_SZ 1
+#define RG_RFG_MSK 0x000000c0
+#define RG_RFG_I_MSK 0xffffff3f
+#define RG_RFG_SFT 6
+#define RG_RFG_HI 7
+#define RG_RFG_SZ 2
+#define RG_PGAG_MSK 0x00000f00
+#define RG_PGAG_I_MSK 0xfffff0ff
+#define RG_PGAG_SFT 8
+#define RG_PGAG_HI 11
+#define RG_PGAG_SZ 4
+#define RG_MODE_MSK 0x00003000
+#define RG_MODE_I_MSK 0xffffcfff
+#define RG_MODE_SFT 12
+#define RG_MODE_HI 13
+#define RG_MODE_SZ 2
+#define RG_EN_TX_TRSW_MSK 0x00004000
+#define RG_EN_TX_TRSW_I_MSK 0xffffbfff
+#define RG_EN_TX_TRSW_SFT 14
+#define RG_EN_TX_TRSW_HI 14
+#define RG_EN_TX_TRSW_SZ 1
+#define RG_EN_SX_MSK 0x00008000
+#define RG_EN_SX_I_MSK 0xffff7fff
+#define RG_EN_SX_SFT 15
+#define RG_EN_SX_HI 15
+#define RG_EN_SX_SZ 1
+#define RG_EN_RX_LNA_MSK 0x00010000
+#define RG_EN_RX_LNA_I_MSK 0xfffeffff
+#define RG_EN_RX_LNA_SFT 16
+#define RG_EN_RX_LNA_HI 16
+#define RG_EN_RX_LNA_SZ 1
+#define RG_EN_RX_MIXER_MSK 0x00020000
+#define RG_EN_RX_MIXER_I_MSK 0xfffdffff
+#define RG_EN_RX_MIXER_SFT 17
+#define RG_EN_RX_MIXER_HI 17
+#define RG_EN_RX_MIXER_SZ 1
+#define RG_EN_RX_DIV2_MSK 0x00040000
+#define RG_EN_RX_DIV2_I_MSK 0xfffbffff
+#define RG_EN_RX_DIV2_SFT 18
+#define RG_EN_RX_DIV2_HI 18
+#define RG_EN_RX_DIV2_SZ 1
+#define RG_EN_RX_LOBUF_MSK 0x00080000
+#define RG_EN_RX_LOBUF_I_MSK 0xfff7ffff
+#define RG_EN_RX_LOBUF_SFT 19
+#define RG_EN_RX_LOBUF_HI 19
+#define RG_EN_RX_LOBUF_SZ 1
+#define RG_EN_RX_TZ_MSK 0x00100000
+#define RG_EN_RX_TZ_I_MSK 0xffefffff
+#define RG_EN_RX_TZ_SFT 20
+#define RG_EN_RX_TZ_HI 20
+#define RG_EN_RX_TZ_SZ 1
+#define RG_EN_RX_FILTER_MSK 0x00200000
+#define RG_EN_RX_FILTER_I_MSK 0xffdfffff
+#define RG_EN_RX_FILTER_SFT 21
+#define RG_EN_RX_FILTER_HI 21
+#define RG_EN_RX_FILTER_SZ 1
+#define RG_EN_RX_HPF_MSK 0x00400000
+#define RG_EN_RX_HPF_I_MSK 0xffbfffff
+#define RG_EN_RX_HPF_SFT 22
+#define RG_EN_RX_HPF_HI 22
+#define RG_EN_RX_HPF_SZ 1
+#define RG_EN_RX_RSSI_MSK 0x00800000
+#define RG_EN_RX_RSSI_I_MSK 0xff7fffff
+#define RG_EN_RX_RSSI_SFT 23
+#define RG_EN_RX_RSSI_HI 23
+#define RG_EN_RX_RSSI_SZ 1
+#define RG_EN_ADC_MSK 0x01000000
+#define RG_EN_ADC_I_MSK 0xfeffffff
+#define RG_EN_ADC_SFT 24
+#define RG_EN_ADC_HI 24
+#define RG_EN_ADC_SZ 1
+#define RG_EN_TX_MOD_MSK 0x02000000
+#define RG_EN_TX_MOD_I_MSK 0xfdffffff
+#define RG_EN_TX_MOD_SFT 25
+#define RG_EN_TX_MOD_HI 25
+#define RG_EN_TX_MOD_SZ 1
+#define RG_EN_TX_DIV2_MSK 0x04000000
+#define RG_EN_TX_DIV2_I_MSK 0xfbffffff
+#define RG_EN_TX_DIV2_SFT 26
+#define RG_EN_TX_DIV2_HI 26
+#define RG_EN_TX_DIV2_SZ 1
+#define RG_EN_TX_DIV2_BUF_MSK 0x08000000
+#define RG_EN_TX_DIV2_BUF_I_MSK 0xf7ffffff
+#define RG_EN_TX_DIV2_BUF_SFT 27
+#define RG_EN_TX_DIV2_BUF_HI 27
+#define RG_EN_TX_DIV2_BUF_SZ 1
+#define RG_EN_TX_LOBF_MSK 0x10000000
+#define RG_EN_TX_LOBF_I_MSK 0xefffffff
+#define RG_EN_TX_LOBF_SFT 28
+#define RG_EN_TX_LOBF_HI 28
+#define RG_EN_TX_LOBF_SZ 1
+#define RG_EN_RX_LOBF_MSK 0x20000000
+#define RG_EN_RX_LOBF_I_MSK 0xdfffffff
+#define RG_EN_RX_LOBF_SFT 29
+#define RG_EN_RX_LOBF_HI 29
+#define RG_EN_RX_LOBF_SZ 1
+#define RG_SEL_DPLL_CLK_MSK 0x40000000
+#define RG_SEL_DPLL_CLK_I_MSK 0xbfffffff
+#define RG_SEL_DPLL_CLK_SFT 30
+#define RG_SEL_DPLL_CLK_HI 30
+#define RG_SEL_DPLL_CLK_SZ 1
+#define RG_EN_CLK_960MBY13_UART_MSK 0x80000000
+#define RG_EN_CLK_960MBY13_UART_I_MSK 0x7fffffff
+#define RG_EN_CLK_960MBY13_UART_SFT 31
+#define RG_EN_CLK_960MBY13_UART_HI 31
+#define RG_EN_CLK_960MBY13_UART_SZ 1
+#define RG_EN_TX_DPD_MSK 0x00000001
+#define RG_EN_TX_DPD_I_MSK 0xfffffffe
+#define RG_EN_TX_DPD_SFT 0
+#define RG_EN_TX_DPD_HI 0
+#define RG_EN_TX_DPD_SZ 1
+#define RG_EN_TX_TSSI_MSK 0x00000002
+#define RG_EN_TX_TSSI_I_MSK 0xfffffffd
+#define RG_EN_TX_TSSI_SFT 1
+#define RG_EN_TX_TSSI_HI 1
+#define RG_EN_TX_TSSI_SZ 1
+#define RG_EN_RX_IQCAL_MSK 0x00000004
+#define RG_EN_RX_IQCAL_I_MSK 0xfffffffb
+#define RG_EN_RX_IQCAL_SFT 2
+#define RG_EN_RX_IQCAL_HI 2
+#define RG_EN_RX_IQCAL_SZ 1
+#define RG_EN_TX_DAC_CAL_MSK 0x00000008
+#define RG_EN_TX_DAC_CAL_I_MSK 0xfffffff7
+#define RG_EN_TX_DAC_CAL_SFT 3
+#define RG_EN_TX_DAC_CAL_HI 3
+#define RG_EN_TX_DAC_CAL_SZ 1
+#define RG_EN_TX_SELF_MIXER_MSK 0x00000010
+#define RG_EN_TX_SELF_MIXER_I_MSK 0xffffffef
+#define RG_EN_TX_SELF_MIXER_SFT 4
+#define RG_EN_TX_SELF_MIXER_HI 4
+#define RG_EN_TX_SELF_MIXER_SZ 1
+#define RG_EN_TX_DAC_OUT_MSK 0x00000020
+#define RG_EN_TX_DAC_OUT_I_MSK 0xffffffdf
+#define RG_EN_TX_DAC_OUT_SFT 5
+#define RG_EN_TX_DAC_OUT_HI 5
+#define RG_EN_TX_DAC_OUT_SZ 1
+#define RG_EN_LDO_RX_FE_MSK 0x00000040
+#define RG_EN_LDO_RX_FE_I_MSK 0xffffffbf
+#define RG_EN_LDO_RX_FE_SFT 6
+#define RG_EN_LDO_RX_FE_HI 6
+#define RG_EN_LDO_RX_FE_SZ 1
+#define RG_EN_LDO_ABB_MSK 0x00000080
+#define RG_EN_LDO_ABB_I_MSK 0xffffff7f
+#define RG_EN_LDO_ABB_SFT 7
+#define RG_EN_LDO_ABB_HI 7
+#define RG_EN_LDO_ABB_SZ 1
+#define RG_EN_LDO_AFE_MSK 0x00000100
+#define RG_EN_LDO_AFE_I_MSK 0xfffffeff
+#define RG_EN_LDO_AFE_SFT 8
+#define RG_EN_LDO_AFE_HI 8
+#define RG_EN_LDO_AFE_SZ 1
+#define RG_EN_SX_CHPLDO_MSK 0x00000200
+#define RG_EN_SX_CHPLDO_I_MSK 0xfffffdff
+#define RG_EN_SX_CHPLDO_SFT 9
+#define RG_EN_SX_CHPLDO_HI 9
+#define RG_EN_SX_CHPLDO_SZ 1
+#define RG_EN_SX_LOBFLDO_MSK 0x00000400
+#define RG_EN_SX_LOBFLDO_I_MSK 0xfffffbff
+#define RG_EN_SX_LOBFLDO_SFT 10
+#define RG_EN_SX_LOBFLDO_HI 10
+#define RG_EN_SX_LOBFLDO_SZ 1
+#define RG_EN_IREF_RX_MSK 0x00000800
+#define RG_EN_IREF_RX_I_MSK 0xfffff7ff
+#define RG_EN_IREF_RX_SFT 11
+#define RG_EN_IREF_RX_HI 11
+#define RG_EN_IREF_RX_SZ 1
+#define RG_EN_TX_DAC_VOUT_MSK 0x00002000
+#define RG_EN_TX_DAC_VOUT_I_MSK 0xffffdfff
+#define RG_EN_TX_DAC_VOUT_SFT 13
+#define RG_EN_TX_DAC_VOUT_HI 13
+#define RG_EN_TX_DAC_VOUT_SZ 1
+#define RG_EN_SX_LCK_BIN_MSK 0x00004000
+#define RG_EN_SX_LCK_BIN_I_MSK 0xffffbfff
+#define RG_EN_SX_LCK_BIN_SFT 14
+#define RG_EN_SX_LCK_BIN_HI 14
+#define RG_EN_SX_LCK_BIN_SZ 1
+#define RG_RTC_CAL_MODE_MSK 0x00010000
+#define RG_RTC_CAL_MODE_I_MSK 0xfffeffff
+#define RG_RTC_CAL_MODE_SFT 16
+#define RG_RTC_CAL_MODE_HI 16
+#define RG_RTC_CAL_MODE_SZ 1
+#define RG_EN_IQPAD_IOSW_MSK 0x00020000
+#define RG_EN_IQPAD_IOSW_I_MSK 0xfffdffff
+#define RG_EN_IQPAD_IOSW_SFT 17
+#define RG_EN_IQPAD_IOSW_HI 17
+#define RG_EN_IQPAD_IOSW_SZ 1
+#define RG_EN_TESTPAD_IOSW_MSK 0x00040000
+#define RG_EN_TESTPAD_IOSW_I_MSK 0xfffbffff
+#define RG_EN_TESTPAD_IOSW_SFT 18
+#define RG_EN_TESTPAD_IOSW_HI 18
+#define RG_EN_TESTPAD_IOSW_SZ 1
+#define RG_EN_TRXBF_BYPASS_MSK 0x00080000
+#define RG_EN_TRXBF_BYPASS_I_MSK 0xfff7ffff
+#define RG_EN_TRXBF_BYPASS_SFT 19
+#define RG_EN_TRXBF_BYPASS_HI 19
+#define RG_EN_TRXBF_BYPASS_SZ 1
+#define RG_LDO_LEVEL_RX_FE_MSK 0x00000007
+#define RG_LDO_LEVEL_RX_FE_I_MSK 0xfffffff8
+#define RG_LDO_LEVEL_RX_FE_SFT 0
+#define RG_LDO_LEVEL_RX_FE_HI 2
+#define RG_LDO_LEVEL_RX_FE_SZ 3
+#define RG_LDO_LEVEL_ABB_MSK 0x00000038
+#define RG_LDO_LEVEL_ABB_I_MSK 0xffffffc7
+#define RG_LDO_LEVEL_ABB_SFT 3
+#define RG_LDO_LEVEL_ABB_HI 5
+#define RG_LDO_LEVEL_ABB_SZ 3
+#define RG_LDO_LEVEL_AFE_MSK 0x000001c0
+#define RG_LDO_LEVEL_AFE_I_MSK 0xfffffe3f
+#define RG_LDO_LEVEL_AFE_SFT 6
+#define RG_LDO_LEVEL_AFE_HI 8
+#define RG_LDO_LEVEL_AFE_SZ 3
+#define RG_SX_LDO_CHP_LEVEL_MSK 0x00000e00
+#define RG_SX_LDO_CHP_LEVEL_I_MSK 0xfffff1ff
+#define RG_SX_LDO_CHP_LEVEL_SFT 9
+#define RG_SX_LDO_CHP_LEVEL_HI 11
+#define RG_SX_LDO_CHP_LEVEL_SZ 3
+#define RG_SX_LDO_LOBF_LEVEL_MSK 0x00007000
+#define RG_SX_LDO_LOBF_LEVEL_I_MSK 0xffff8fff
+#define RG_SX_LDO_LOBF_LEVEL_SFT 12
+#define RG_SX_LDO_LOBF_LEVEL_HI 14
+#define RG_SX_LDO_LOBF_LEVEL_SZ 3
+#define RG_SX_LDO_XOSC_LEVEL_MSK 0x00038000
+#define RG_SX_LDO_XOSC_LEVEL_I_MSK 0xfffc7fff
+#define RG_SX_LDO_XOSC_LEVEL_SFT 15
+#define RG_SX_LDO_XOSC_LEVEL_HI 17
+#define RG_SX_LDO_XOSC_LEVEL_SZ 3
+#define RG_DP_LDO_LEVEL_MSK 0x001c0000
+#define RG_DP_LDO_LEVEL_I_MSK 0xffe3ffff
+#define RG_DP_LDO_LEVEL_SFT 18
+#define RG_DP_LDO_LEVEL_HI 20
+#define RG_DP_LDO_LEVEL_SZ 3
+#define RG_SX_LDO_VCO_LEVEL_MSK 0x00e00000
+#define RG_SX_LDO_VCO_LEVEL_I_MSK 0xff1fffff
+#define RG_SX_LDO_VCO_LEVEL_SFT 21
+#define RG_SX_LDO_VCO_LEVEL_HI 23
+#define RG_SX_LDO_VCO_LEVEL_SZ 3
+#define RG_TX_LDO_TX_LEVEL_MSK 0x07000000
+#define RG_TX_LDO_TX_LEVEL_I_MSK 0xf8ffffff
+#define RG_TX_LDO_TX_LEVEL_SFT 24
+#define RG_TX_LDO_TX_LEVEL_HI 26
+#define RG_TX_LDO_TX_LEVEL_SZ 3
+#define RG_EN_RX_PADSW_MSK 0x00000001
+#define RG_EN_RX_PADSW_I_MSK 0xfffffffe
+#define RG_EN_RX_PADSW_SFT 0
+#define RG_EN_RX_PADSW_HI 0
+#define RG_EN_RX_PADSW_SZ 1
+#define RG_EN_RX_TESTNODE_MSK 0x00000002
+#define RG_EN_RX_TESTNODE_I_MSK 0xfffffffd
+#define RG_EN_RX_TESTNODE_SFT 1
+#define RG_EN_RX_TESTNODE_HI 1
+#define RG_EN_RX_TESTNODE_SZ 1
+#define RG_RX_ABBCFIX_MSK 0x00000004
+#define RG_RX_ABBCFIX_I_MSK 0xfffffffb
+#define RG_RX_ABBCFIX_SFT 2
+#define RG_RX_ABBCFIX_HI 2
+#define RG_RX_ABBCFIX_SZ 1
+#define RG_RX_ABBCTUNE_MSK 0x000001f8
+#define RG_RX_ABBCTUNE_I_MSK 0xfffffe07
+#define RG_RX_ABBCTUNE_SFT 3
+#define RG_RX_ABBCTUNE_HI 8
+#define RG_RX_ABBCTUNE_SZ 6
+#define RG_RX_ABBOUT_TRI_STATE_MSK 0x00000200
+#define RG_RX_ABBOUT_TRI_STATE_I_MSK 0xfffffdff
+#define RG_RX_ABBOUT_TRI_STATE_SFT 9
+#define RG_RX_ABBOUT_TRI_STATE_HI 9
+#define RG_RX_ABBOUT_TRI_STATE_SZ 1
+#define RG_RX_ABB_N_MODE_MSK 0x00000400
+#define RG_RX_ABB_N_MODE_I_MSK 0xfffffbff
+#define RG_RX_ABB_N_MODE_SFT 10
+#define RG_RX_ABB_N_MODE_HI 10
+#define RG_RX_ABB_N_MODE_SZ 1
+#define RG_RX_EN_LOOPA_MSK 0x00000800
+#define RG_RX_EN_LOOPA_I_MSK 0xfffff7ff
+#define RG_RX_EN_LOOPA_SFT 11
+#define RG_RX_EN_LOOPA_HI 11
+#define RG_RX_EN_LOOPA_SZ 1
+#define RG_RX_FILTERI1ST_MSK 0x00003000
+#define RG_RX_FILTERI1ST_I_MSK 0xffffcfff
+#define RG_RX_FILTERI1ST_SFT 12
+#define RG_RX_FILTERI1ST_HI 13
+#define RG_RX_FILTERI1ST_SZ 2
+#define RG_RX_FILTERI2ND_MSK 0x0000c000
+#define RG_RX_FILTERI2ND_I_MSK 0xffff3fff
+#define RG_RX_FILTERI2ND_SFT 14
+#define RG_RX_FILTERI2ND_HI 15
+#define RG_RX_FILTERI2ND_SZ 2
+#define RG_RX_FILTERI3RD_MSK 0x00030000
+#define RG_RX_FILTERI3RD_I_MSK 0xfffcffff
+#define RG_RX_FILTERI3RD_SFT 16
+#define RG_RX_FILTERI3RD_HI 17
+#define RG_RX_FILTERI3RD_SZ 2
+#define RG_RX_FILTERI_COURSE_MSK 0x000c0000
+#define RG_RX_FILTERI_COURSE_I_MSK 0xfff3ffff
+#define RG_RX_FILTERI_COURSE_SFT 18
+#define RG_RX_FILTERI_COURSE_HI 19
+#define RG_RX_FILTERI_COURSE_SZ 2
+#define RG_RX_FILTERVCM_MSK 0x00300000
+#define RG_RX_FILTERVCM_I_MSK 0xffcfffff
+#define RG_RX_FILTERVCM_SFT 20
+#define RG_RX_FILTERVCM_HI 21
+#define RG_RX_FILTERVCM_SZ 2
+#define RG_RX_HPF3M_MSK 0x00400000
+#define RG_RX_HPF3M_I_MSK 0xffbfffff
+#define RG_RX_HPF3M_SFT 22
+#define RG_RX_HPF3M_HI 22
+#define RG_RX_HPF3M_SZ 1
+#define RG_RX_HPF300K_MSK 0x00800000
+#define RG_RX_HPF300K_I_MSK 0xff7fffff
+#define RG_RX_HPF300K_SFT 23
+#define RG_RX_HPF300K_HI 23
+#define RG_RX_HPF300K_SZ 1
+#define RG_RX_HPFI_MSK 0x03000000
+#define RG_RX_HPFI_I_MSK 0xfcffffff
+#define RG_RX_HPFI_SFT 24
+#define RG_RX_HPFI_HI 25
+#define RG_RX_HPFI_SZ 2
+#define RG_RX_HPF_FINALCORNER_MSK 0x0c000000
+#define RG_RX_HPF_FINALCORNER_I_MSK 0xf3ffffff
+#define RG_RX_HPF_FINALCORNER_SFT 26
+#define RG_RX_HPF_FINALCORNER_HI 27
+#define RG_RX_HPF_FINALCORNER_SZ 2
+#define RG_RX_HPF_SETTLE1_C_MSK 0x30000000
+#define RG_RX_HPF_SETTLE1_C_I_MSK 0xcfffffff
+#define RG_RX_HPF_SETTLE1_C_SFT 28
+#define RG_RX_HPF_SETTLE1_C_HI 29
+#define RG_RX_HPF_SETTLE1_C_SZ 2
+#define RG_RX_HPF_SETTLE1_R_MSK 0x00000003
+#define RG_RX_HPF_SETTLE1_R_I_MSK 0xfffffffc
+#define RG_RX_HPF_SETTLE1_R_SFT 0
+#define RG_RX_HPF_SETTLE1_R_HI 1
+#define RG_RX_HPF_SETTLE1_R_SZ 2
+#define RG_RX_HPF_SETTLE2_C_MSK 0x0000000c
+#define RG_RX_HPF_SETTLE2_C_I_MSK 0xfffffff3
+#define RG_RX_HPF_SETTLE2_C_SFT 2
+#define RG_RX_HPF_SETTLE2_C_HI 3
+#define RG_RX_HPF_SETTLE2_C_SZ 2
+#define RG_RX_HPF_SETTLE2_R_MSK 0x00000030
+#define RG_RX_HPF_SETTLE2_R_I_MSK 0xffffffcf
+#define RG_RX_HPF_SETTLE2_R_SFT 4
+#define RG_RX_HPF_SETTLE2_R_HI 5
+#define RG_RX_HPF_SETTLE2_R_SZ 2
+#define RG_RX_HPF_VCMCON2_MSK 0x000000c0
+#define RG_RX_HPF_VCMCON2_I_MSK 0xffffff3f
+#define RG_RX_HPF_VCMCON2_SFT 6
+#define RG_RX_HPF_VCMCON2_HI 7
+#define RG_RX_HPF_VCMCON2_SZ 2
+#define RG_RX_HPF_VCMCON_MSK 0x00000300
+#define RG_RX_HPF_VCMCON_I_MSK 0xfffffcff
+#define RG_RX_HPF_VCMCON_SFT 8
+#define RG_RX_HPF_VCMCON_HI 9
+#define RG_RX_HPF_VCMCON_SZ 2
+#define RG_RX_OUTVCM_MSK 0x00000c00
+#define RG_RX_OUTVCM_I_MSK 0xfffff3ff
+#define RG_RX_OUTVCM_SFT 10
+#define RG_RX_OUTVCM_HI 11
+#define RG_RX_OUTVCM_SZ 2
+#define RG_RX_TZI_MSK 0x00003000
+#define RG_RX_TZI_I_MSK 0xffffcfff
+#define RG_RX_TZI_SFT 12
+#define RG_RX_TZI_HI 13
+#define RG_RX_TZI_SZ 2
+#define RG_RX_TZ_OUT_TRISTATE_MSK 0x00004000
+#define RG_RX_TZ_OUT_TRISTATE_I_MSK 0xffffbfff
+#define RG_RX_TZ_OUT_TRISTATE_SFT 14
+#define RG_RX_TZ_OUT_TRISTATE_HI 14
+#define RG_RX_TZ_OUT_TRISTATE_SZ 1
+#define RG_RX_TZ_VCM_MSK 0x00018000
+#define RG_RX_TZ_VCM_I_MSK 0xfffe7fff
+#define RG_RX_TZ_VCM_SFT 15
+#define RG_RX_TZ_VCM_HI 16
+#define RG_RX_TZ_VCM_SZ 2
+#define RG_EN_RX_RSSI_TESTNODE_MSK 0x000e0000
+#define RG_EN_RX_RSSI_TESTNODE_I_MSK 0xfff1ffff
+#define RG_EN_RX_RSSI_TESTNODE_SFT 17
+#define RG_EN_RX_RSSI_TESTNODE_HI 19
+#define RG_EN_RX_RSSI_TESTNODE_SZ 3
+#define RG_RX_ADCRSSI_CLKSEL_MSK 0x00100000
+#define RG_RX_ADCRSSI_CLKSEL_I_MSK 0xffefffff
+#define RG_RX_ADCRSSI_CLKSEL_SFT 20
+#define RG_RX_ADCRSSI_CLKSEL_HI 20
+#define RG_RX_ADCRSSI_CLKSEL_SZ 1
+#define RG_RX_ADCRSSI_VCM_MSK 0x00600000
+#define RG_RX_ADCRSSI_VCM_I_MSK 0xff9fffff
+#define RG_RX_ADCRSSI_VCM_SFT 21
+#define RG_RX_ADCRSSI_VCM_HI 22
+#define RG_RX_ADCRSSI_VCM_SZ 2
+#define RG_RX_REC_LPFCORNER_MSK 0x01800000
+#define RG_RX_REC_LPFCORNER_I_MSK 0xfe7fffff
+#define RG_RX_REC_LPFCORNER_SFT 23
+#define RG_RX_REC_LPFCORNER_HI 24
+#define RG_RX_REC_LPFCORNER_SZ 2
+#define RG_RSSI_CLOCK_GATING_MSK 0x02000000
+#define RG_RSSI_CLOCK_GATING_I_MSK 0xfdffffff
+#define RG_RSSI_CLOCK_GATING_SFT 25
+#define RG_RSSI_CLOCK_GATING_HI 25
+#define RG_RSSI_CLOCK_GATING_SZ 1
+#define RG_TXPGA_CAPSW_MSK 0x00000003
+#define RG_TXPGA_CAPSW_I_MSK 0xfffffffc
+#define RG_TXPGA_CAPSW_SFT 0
+#define RG_TXPGA_CAPSW_HI 1
+#define RG_TXPGA_CAPSW_SZ 2
+#define RG_TXPGA_MAIN_MSK 0x000000fc
+#define RG_TXPGA_MAIN_I_MSK 0xffffff03
+#define RG_TXPGA_MAIN_SFT 2
+#define RG_TXPGA_MAIN_HI 7
+#define RG_TXPGA_MAIN_SZ 6
+#define RG_TXPGA_STEER_MSK 0x00003f00
+#define RG_TXPGA_STEER_I_MSK 0xffffc0ff
+#define RG_TXPGA_STEER_SFT 8
+#define RG_TXPGA_STEER_HI 13
+#define RG_TXPGA_STEER_SZ 6
+#define RG_TXMOD_GMCELL_MSK 0x0000c000
+#define RG_TXMOD_GMCELL_I_MSK 0xffff3fff
+#define RG_TXMOD_GMCELL_SFT 14
+#define RG_TXMOD_GMCELL_HI 15
+#define RG_TXMOD_GMCELL_SZ 2
+#define RG_TXLPF_GMCELL_MSK 0x00030000
+#define RG_TXLPF_GMCELL_I_MSK 0xfffcffff
+#define RG_TXLPF_GMCELL_SFT 16
+#define RG_TXLPF_GMCELL_HI 17
+#define RG_TXLPF_GMCELL_SZ 2
+#define RG_PACELL_EN_MSK 0x001c0000
+#define RG_PACELL_EN_I_MSK 0xffe3ffff
+#define RG_PACELL_EN_SFT 18
+#define RG_PACELL_EN_HI 20
+#define RG_PACELL_EN_SZ 3
+#define RG_PABIAS_CTRL_MSK 0x01e00000
+#define RG_PABIAS_CTRL_I_MSK 0xfe1fffff
+#define RG_PABIAS_CTRL_SFT 21
+#define RG_PABIAS_CTRL_HI 24
+#define RG_PABIAS_CTRL_SZ 4
+#define RG_TX_DIV_VSET_MSK 0x0c000000
+#define RG_TX_DIV_VSET_I_MSK 0xf3ffffff
+#define RG_TX_DIV_VSET_SFT 26
+#define RG_TX_DIV_VSET_HI 27
+#define RG_TX_DIV_VSET_SZ 2
+#define RG_TX_LOBUF_VSET_MSK 0x30000000
+#define RG_TX_LOBUF_VSET_I_MSK 0xcfffffff
+#define RG_TX_LOBUF_VSET_SFT 28
+#define RG_TX_LOBUF_VSET_HI 29
+#define RG_TX_LOBUF_VSET_SZ 2
+#define RG_RX_SQDC_MSK 0x00000007
+#define RG_RX_SQDC_I_MSK 0xfffffff8
+#define RG_RX_SQDC_SFT 0
+#define RG_RX_SQDC_HI 2
+#define RG_RX_SQDC_SZ 3
+#define RG_RX_DIV2_CORE_MSK 0x00000018
+#define RG_RX_DIV2_CORE_I_MSK 0xffffffe7
+#define RG_RX_DIV2_CORE_SFT 3
+#define RG_RX_DIV2_CORE_HI 4
+#define RG_RX_DIV2_CORE_SZ 2
+#define RG_RX_LOBUF_MSK 0x00000060
+#define RG_RX_LOBUF_I_MSK 0xffffff9f
+#define RG_RX_LOBUF_SFT 5
+#define RG_RX_LOBUF_HI 6
+#define RG_RX_LOBUF_SZ 2
+#define RG_TX_DPDGM_BIAS_MSK 0x00000780
+#define RG_TX_DPDGM_BIAS_I_MSK 0xfffff87f
+#define RG_TX_DPDGM_BIAS_SFT 7
+#define RG_TX_DPDGM_BIAS_HI 10
+#define RG_TX_DPDGM_BIAS_SZ 4
+#define RG_TX_DPD_DIV_MSK 0x00007800
+#define RG_TX_DPD_DIV_I_MSK 0xffff87ff
+#define RG_TX_DPD_DIV_SFT 11
+#define RG_TX_DPD_DIV_HI 14
+#define RG_TX_DPD_DIV_SZ 4
+#define RG_TX_TSSI_BIAS_MSK 0x00038000
+#define RG_TX_TSSI_BIAS_I_MSK 0xfffc7fff
+#define RG_TX_TSSI_BIAS_SFT 15
+#define RG_TX_TSSI_BIAS_HI 17
+#define RG_TX_TSSI_BIAS_SZ 3
+#define RG_TX_TSSI_DIV_MSK 0x001c0000
+#define RG_TX_TSSI_DIV_I_MSK 0xffe3ffff
+#define RG_TX_TSSI_DIV_SFT 18
+#define RG_TX_TSSI_DIV_HI 20
+#define RG_TX_TSSI_DIV_SZ 3
+#define RG_TX_TSSI_TESTMODE_MSK 0x00200000
+#define RG_TX_TSSI_TESTMODE_I_MSK 0xffdfffff
+#define RG_TX_TSSI_TESTMODE_SFT 21
+#define RG_TX_TSSI_TESTMODE_HI 21
+#define RG_TX_TSSI_TESTMODE_SZ 1
+#define RG_TX_TSSI_TEST_MSK 0x00c00000
+#define RG_TX_TSSI_TEST_I_MSK 0xff3fffff
+#define RG_TX_TSSI_TEST_SFT 22
+#define RG_TX_TSSI_TEST_HI 23
+#define RG_TX_TSSI_TEST_SZ 2
+#define RG_PACASCODE_CTRL_MSK 0x07000000
+#define RG_PACASCODE_CTRL_I_MSK 0xf8ffffff
+#define RG_PACASCODE_CTRL_SFT 24
+#define RG_PACASCODE_CTRL_HI 26
+#define RG_PACASCODE_CTRL_SZ 3
+#define RG_RX_HG_LNA_GC_MSK 0x00000003
+#define RG_RX_HG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_HG_LNA_GC_SFT 0
+#define RG_RX_HG_LNA_GC_HI 1
+#define RG_RX_HG_LNA_GC_SZ 2
+#define RG_RX_HG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_HG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_HG_LNAHGN_BIAS_SFT 2
+#define RG_RX_HG_LNAHGN_BIAS_HI 5
+#define RG_RX_HG_LNAHGN_BIAS_SZ 4
+#define RG_RX_HG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_HG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_HG_LNAHGP_BIAS_SFT 6
+#define RG_RX_HG_LNAHGP_BIAS_HI 9
+#define RG_RX_HG_LNAHGP_BIAS_SZ 4
+#define RG_RX_HG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_HG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_HG_LNALG_BIAS_SFT 10
+#define RG_RX_HG_LNALG_BIAS_HI 13
+#define RG_RX_HG_LNALG_BIAS_SZ 4
+#define RG_RX_HG_TZ_GC_MSK 0x0000c000
+#define RG_RX_HG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_HG_TZ_GC_SFT 14
+#define RG_RX_HG_TZ_GC_HI 15
+#define RG_RX_HG_TZ_GC_SZ 2
+#define RG_RX_HG_TZ_CAP_MSK 0x00070000
+#define RG_RX_HG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_HG_TZ_CAP_SFT 16
+#define RG_RX_HG_TZ_CAP_HI 18
+#define RG_RX_HG_TZ_CAP_SZ 3
+#define RG_RX_MG_LNA_GC_MSK 0x00000003
+#define RG_RX_MG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_MG_LNA_GC_SFT 0
+#define RG_RX_MG_LNA_GC_HI 1
+#define RG_RX_MG_LNA_GC_SZ 2
+#define RG_RX_MG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_MG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_MG_LNAHGN_BIAS_SFT 2
+#define RG_RX_MG_LNAHGN_BIAS_HI 5
+#define RG_RX_MG_LNAHGN_BIAS_SZ 4
+#define RG_RX_MG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_MG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_MG_LNAHGP_BIAS_SFT 6
+#define RG_RX_MG_LNAHGP_BIAS_HI 9
+#define RG_RX_MG_LNAHGP_BIAS_SZ 4
+#define RG_RX_MG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_MG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_MG_LNALG_BIAS_SFT 10
+#define RG_RX_MG_LNALG_BIAS_HI 13
+#define RG_RX_MG_LNALG_BIAS_SZ 4
+#define RG_RX_MG_TZ_GC_MSK 0x0000c000
+#define RG_RX_MG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_MG_TZ_GC_SFT 14
+#define RG_RX_MG_TZ_GC_HI 15
+#define RG_RX_MG_TZ_GC_SZ 2
+#define RG_RX_MG_TZ_CAP_MSK 0x00070000
+#define RG_RX_MG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_MG_TZ_CAP_SFT 16
+#define RG_RX_MG_TZ_CAP_HI 18
+#define RG_RX_MG_TZ_CAP_SZ 3
+#define RG_RX_LG_LNA_GC_MSK 0x00000003
+#define RG_RX_LG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_LG_LNA_GC_SFT 0
+#define RG_RX_LG_LNA_GC_HI 1
+#define RG_RX_LG_LNA_GC_SZ 2
+#define RG_RX_LG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_LG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_LG_LNAHGN_BIAS_SFT 2
+#define RG_RX_LG_LNAHGN_BIAS_HI 5
+#define RG_RX_LG_LNAHGN_BIAS_SZ 4
+#define RG_RX_LG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_LG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_LG_LNAHGP_BIAS_SFT 6
+#define RG_RX_LG_LNAHGP_BIAS_HI 9
+#define RG_RX_LG_LNAHGP_BIAS_SZ 4
+#define RG_RX_LG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_LG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_LG_LNALG_BIAS_SFT 10
+#define RG_RX_LG_LNALG_BIAS_HI 13
+#define RG_RX_LG_LNALG_BIAS_SZ 4
+#define RG_RX_LG_TZ_GC_MSK 0x0000c000
+#define RG_RX_LG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_LG_TZ_GC_SFT 14
+#define RG_RX_LG_TZ_GC_HI 15
+#define RG_RX_LG_TZ_GC_SZ 2
+#define RG_RX_LG_TZ_CAP_MSK 0x00070000
+#define RG_RX_LG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_LG_TZ_CAP_SFT 16
+#define RG_RX_LG_TZ_CAP_HI 18
+#define RG_RX_LG_TZ_CAP_SZ 3
+#define RG_RX_ULG_LNA_GC_MSK 0x00000003
+#define RG_RX_ULG_LNA_GC_I_MSK 0xfffffffc
+#define RG_RX_ULG_LNA_GC_SFT 0
+#define RG_RX_ULG_LNA_GC_HI 1
+#define RG_RX_ULG_LNA_GC_SZ 2
+#define RG_RX_ULG_LNAHGN_BIAS_MSK 0x0000003c
+#define RG_RX_ULG_LNAHGN_BIAS_I_MSK 0xffffffc3
+#define RG_RX_ULG_LNAHGN_BIAS_SFT 2
+#define RG_RX_ULG_LNAHGN_BIAS_HI 5
+#define RG_RX_ULG_LNAHGN_BIAS_SZ 4
+#define RG_RX_ULG_LNAHGP_BIAS_MSK 0x000003c0
+#define RG_RX_ULG_LNAHGP_BIAS_I_MSK 0xfffffc3f
+#define RG_RX_ULG_LNAHGP_BIAS_SFT 6
+#define RG_RX_ULG_LNAHGP_BIAS_HI 9
+#define RG_RX_ULG_LNAHGP_BIAS_SZ 4
+#define RG_RX_ULG_LNALG_BIAS_MSK 0x00003c00
+#define RG_RX_ULG_LNALG_BIAS_I_MSK 0xffffc3ff
+#define RG_RX_ULG_LNALG_BIAS_SFT 10
+#define RG_RX_ULG_LNALG_BIAS_HI 13
+#define RG_RX_ULG_LNALG_BIAS_SZ 4
+#define RG_RX_ULG_TZ_GC_MSK 0x0000c000
+#define RG_RX_ULG_TZ_GC_I_MSK 0xffff3fff
+#define RG_RX_ULG_TZ_GC_SFT 14
+#define RG_RX_ULG_TZ_GC_HI 15
+#define RG_RX_ULG_TZ_GC_SZ 2
+#define RG_RX_ULG_TZ_CAP_MSK 0x00070000
+#define RG_RX_ULG_TZ_CAP_I_MSK 0xfff8ffff
+#define RG_RX_ULG_TZ_CAP_SFT 16
+#define RG_RX_ULG_TZ_CAP_HI 18
+#define RG_RX_ULG_TZ_CAP_SZ 3
+#define RG_HPF1_FAST_SET_X_MSK 0x00000001
+#define RG_HPF1_FAST_SET_X_I_MSK 0xfffffffe
+#define RG_HPF1_FAST_SET_X_SFT 0
+#define RG_HPF1_FAST_SET_X_HI 0
+#define RG_HPF1_FAST_SET_X_SZ 1
+#define RG_HPF1_FAST_SET_Y_MSK 0x00000002
+#define RG_HPF1_FAST_SET_Y_I_MSK 0xfffffffd
+#define RG_HPF1_FAST_SET_Y_SFT 1
+#define RG_HPF1_FAST_SET_Y_HI 1
+#define RG_HPF1_FAST_SET_Y_SZ 1
+#define RG_HPF1_FAST_SET_Z_MSK 0x00000004
+#define RG_HPF1_FAST_SET_Z_I_MSK 0xfffffffb
+#define RG_HPF1_FAST_SET_Z_SFT 2
+#define RG_HPF1_FAST_SET_Z_HI 2
+#define RG_HPF1_FAST_SET_Z_SZ 1
+#define RG_HPF_T1A_MSK 0x00000018
+#define RG_HPF_T1A_I_MSK 0xffffffe7
+#define RG_HPF_T1A_SFT 3
+#define RG_HPF_T1A_HI 4
+#define RG_HPF_T1A_SZ 2
+#define RG_HPF_T1B_MSK 0x00000060
+#define RG_HPF_T1B_I_MSK 0xffffff9f
+#define RG_HPF_T1B_SFT 5
+#define RG_HPF_T1B_HI 6
+#define RG_HPF_T1B_SZ 2
+#define RG_HPF_T1C_MSK 0x00000180
+#define RG_HPF_T1C_I_MSK 0xfffffe7f
+#define RG_HPF_T1C_SFT 7
+#define RG_HPF_T1C_HI 8
+#define RG_HPF_T1C_SZ 2
+#define RG_RX_LNA_TRI_SEL_MSK 0x00000600
+#define RG_RX_LNA_TRI_SEL_I_MSK 0xfffff9ff
+#define RG_RX_LNA_TRI_SEL_SFT 9
+#define RG_RX_LNA_TRI_SEL_HI 10
+#define RG_RX_LNA_TRI_SEL_SZ 2
+#define RG_RX_LNA_SETTLE_MSK 0x00001800
+#define RG_RX_LNA_SETTLE_I_MSK 0xffffe7ff
+#define RG_RX_LNA_SETTLE_SFT 11
+#define RG_RX_LNA_SETTLE_HI 12
+#define RG_RX_LNA_SETTLE_SZ 2
+#define RG_TXGAIN_PHYCTRL_MSK 0x00002000
+#define RG_TXGAIN_PHYCTRL_I_MSK 0xffffdfff
+#define RG_TXGAIN_PHYCTRL_SFT 13
+#define RG_TXGAIN_PHYCTRL_HI 13
+#define RG_TXGAIN_PHYCTRL_SZ 1
+#define RG_TX_GAIN_MSK 0x003fc000
+#define RG_TX_GAIN_I_MSK 0xffc03fff
+#define RG_TX_GAIN_SFT 14
+#define RG_TX_GAIN_HI 21
+#define RG_TX_GAIN_SZ 8
+#define RG_TXGAIN_MANUAL_MSK 0x00400000
+#define RG_TXGAIN_MANUAL_I_MSK 0xffbfffff
+#define RG_TXGAIN_MANUAL_SFT 22
+#define RG_TXGAIN_MANUAL_HI 22
+#define RG_TXGAIN_MANUAL_SZ 1
+#define RG_TX_GAIN_OFFSET_MSK 0x07800000
+#define RG_TX_GAIN_OFFSET_I_MSK 0xf87fffff
+#define RG_TX_GAIN_OFFSET_SFT 23
+#define RG_TX_GAIN_OFFSET_HI 26
+#define RG_TX_GAIN_OFFSET_SZ 4
+#define RG_ADC_CLKSEL_MSK 0x00000001
+#define RG_ADC_CLKSEL_I_MSK 0xfffffffe
+#define RG_ADC_CLKSEL_SFT 0
+#define RG_ADC_CLKSEL_HI 0
+#define RG_ADC_CLKSEL_SZ 1
+#define RG_ADC_DIBIAS_MSK 0x00000006
+#define RG_ADC_DIBIAS_I_MSK 0xfffffff9
+#define RG_ADC_DIBIAS_SFT 1
+#define RG_ADC_DIBIAS_HI 2
+#define RG_ADC_DIBIAS_SZ 2
+#define RG_ADC_DIVR_MSK 0x00000008
+#define RG_ADC_DIVR_I_MSK 0xfffffff7
+#define RG_ADC_DIVR_SFT 3
+#define RG_ADC_DIVR_HI 3
+#define RG_ADC_DIVR_SZ 1
+#define RG_ADC_DVCMI_MSK 0x00000030
+#define RG_ADC_DVCMI_I_MSK 0xffffffcf
+#define RG_ADC_DVCMI_SFT 4
+#define RG_ADC_DVCMI_HI 5
+#define RG_ADC_DVCMI_SZ 2
+#define RG_ADC_SAMSEL_MSK 0x000003c0
+#define RG_ADC_SAMSEL_I_MSK 0xfffffc3f
+#define RG_ADC_SAMSEL_SFT 6
+#define RG_ADC_SAMSEL_HI 9
+#define RG_ADC_SAMSEL_SZ 4
+#define RG_ADC_STNBY_MSK 0x00000400
+#define RG_ADC_STNBY_I_MSK 0xfffffbff
+#define RG_ADC_STNBY_SFT 10
+#define RG_ADC_STNBY_HI 10
+#define RG_ADC_STNBY_SZ 1
+#define RG_ADC_TESTMODE_MSK 0x00000800
+#define RG_ADC_TESTMODE_I_MSK 0xfffff7ff
+#define RG_ADC_TESTMODE_SFT 11
+#define RG_ADC_TESTMODE_HI 11
+#define RG_ADC_TESTMODE_SZ 1
+#define RG_ADC_TSEL_MSK 0x0000f000
+#define RG_ADC_TSEL_I_MSK 0xffff0fff
+#define RG_ADC_TSEL_SFT 12
+#define RG_ADC_TSEL_HI 15
+#define RG_ADC_TSEL_SZ 4
+#define RG_ADC_VRSEL_MSK 0x00030000
+#define RG_ADC_VRSEL_I_MSK 0xfffcffff
+#define RG_ADC_VRSEL_SFT 16
+#define RG_ADC_VRSEL_HI 17
+#define RG_ADC_VRSEL_SZ 2
+#define RG_DICMP_MSK 0x000c0000
+#define RG_DICMP_I_MSK 0xfff3ffff
+#define RG_DICMP_SFT 18
+#define RG_DICMP_HI 19
+#define RG_DICMP_SZ 2
+#define RG_DIOP_MSK 0x00300000
+#define RG_DIOP_I_MSK 0xffcfffff
+#define RG_DIOP_SFT 20
+#define RG_DIOP_HI 21
+#define RG_DIOP_SZ 2
+#define RG_SARADC_VRSEL_MSK 0x00c00000
+#define RG_SARADC_VRSEL_I_MSK 0xff3fffff
+#define RG_SARADC_VRSEL_SFT 22
+#define RG_SARADC_VRSEL_HI 23
+#define RG_SARADC_VRSEL_SZ 2
+#define RG_EN_SAR_TEST_MSK 0x03000000
+#define RG_EN_SAR_TEST_I_MSK 0xfcffffff
+#define RG_EN_SAR_TEST_SFT 24
+#define RG_EN_SAR_TEST_HI 25
+#define RG_EN_SAR_TEST_SZ 2
+#define RG_SARADC_THERMAL_MSK 0x04000000
+#define RG_SARADC_THERMAL_I_MSK 0xfbffffff
+#define RG_SARADC_THERMAL_SFT 26
+#define RG_SARADC_THERMAL_HI 26
+#define RG_SARADC_THERMAL_SZ 1
+#define RG_SARADC_TSSI_MSK 0x08000000
+#define RG_SARADC_TSSI_I_MSK 0xf7ffffff
+#define RG_SARADC_TSSI_SFT 27
+#define RG_SARADC_TSSI_HI 27
+#define RG_SARADC_TSSI_SZ 1
+#define RG_CLK_SAR_SEL_MSK 0x30000000
+#define RG_CLK_SAR_SEL_I_MSK 0xcfffffff
+#define RG_CLK_SAR_SEL_SFT 28
+#define RG_CLK_SAR_SEL_HI 29
+#define RG_CLK_SAR_SEL_SZ 2
+#define RG_EN_SARADC_MSK 0x40000000
+#define RG_EN_SARADC_I_MSK 0xbfffffff
+#define RG_EN_SARADC_SFT 30
+#define RG_EN_SARADC_HI 30
+#define RG_EN_SARADC_SZ 1
+#define RG_DACI1ST_MSK 0x00000003
+#define RG_DACI1ST_I_MSK 0xfffffffc
+#define RG_DACI1ST_SFT 0
+#define RG_DACI1ST_HI 1
+#define RG_DACI1ST_SZ 2
+#define RG_TX_DACLPF_ICOURSE_MSK 0x0000000c
+#define RG_TX_DACLPF_ICOURSE_I_MSK 0xfffffff3
+#define RG_TX_DACLPF_ICOURSE_SFT 2
+#define RG_TX_DACLPF_ICOURSE_HI 3
+#define RG_TX_DACLPF_ICOURSE_SZ 2
+#define RG_TX_DACLPF_IFINE_MSK 0x00000030
+#define RG_TX_DACLPF_IFINE_I_MSK 0xffffffcf
+#define RG_TX_DACLPF_IFINE_SFT 4
+#define RG_TX_DACLPF_IFINE_HI 5
+#define RG_TX_DACLPF_IFINE_SZ 2
+#define RG_TX_DACLPF_VCM_MSK 0x000000c0
+#define RG_TX_DACLPF_VCM_I_MSK 0xffffff3f
+#define RG_TX_DACLPF_VCM_SFT 6
+#define RG_TX_DACLPF_VCM_HI 7
+#define RG_TX_DACLPF_VCM_SZ 2
+#define RG_TX_DAC_CKEDGE_SEL_MSK 0x00000100
+#define RG_TX_DAC_CKEDGE_SEL_I_MSK 0xfffffeff
+#define RG_TX_DAC_CKEDGE_SEL_SFT 8
+#define RG_TX_DAC_CKEDGE_SEL_HI 8
+#define RG_TX_DAC_CKEDGE_SEL_SZ 1
+#define RG_TX_DAC_IBIAS_MSK 0x00000600
+#define RG_TX_DAC_IBIAS_I_MSK 0xfffff9ff
+#define RG_TX_DAC_IBIAS_SFT 9
+#define RG_TX_DAC_IBIAS_HI 10
+#define RG_TX_DAC_IBIAS_SZ 2
+#define RG_TX_DAC_OS_MSK 0x00003800
+#define RG_TX_DAC_OS_I_MSK 0xffffc7ff
+#define RG_TX_DAC_OS_SFT 11
+#define RG_TX_DAC_OS_HI 13
+#define RG_TX_DAC_OS_SZ 3
+#define RG_TX_DAC_RCAL_MSK 0x0000c000
+#define RG_TX_DAC_RCAL_I_MSK 0xffff3fff
+#define RG_TX_DAC_RCAL_SFT 14
+#define RG_TX_DAC_RCAL_HI 15
+#define RG_TX_DAC_RCAL_SZ 2
+#define RG_TX_DAC_TSEL_MSK 0x000f0000
+#define RG_TX_DAC_TSEL_I_MSK 0xfff0ffff
+#define RG_TX_DAC_TSEL_SFT 16
+#define RG_TX_DAC_TSEL_HI 19
+#define RG_TX_DAC_TSEL_SZ 4
+#define RG_TX_EN_VOLTAGE_IN_MSK 0x00100000
+#define RG_TX_EN_VOLTAGE_IN_I_MSK 0xffefffff
+#define RG_TX_EN_VOLTAGE_IN_SFT 20
+#define RG_TX_EN_VOLTAGE_IN_HI 20
+#define RG_TX_EN_VOLTAGE_IN_SZ 1
+#define RG_TXLPF_BYPASS_MSK 0x00200000
+#define RG_TXLPF_BYPASS_I_MSK 0xffdfffff
+#define RG_TXLPF_BYPASS_SFT 21
+#define RG_TXLPF_BYPASS_HI 21
+#define RG_TXLPF_BYPASS_SZ 1
+#define RG_TXLPF_BOOSTI_MSK 0x00400000
+#define RG_TXLPF_BOOSTI_I_MSK 0xffbfffff
+#define RG_TXLPF_BOOSTI_SFT 22
+#define RG_TXLPF_BOOSTI_HI 22
+#define RG_TXLPF_BOOSTI_SZ 1
+#define RG_TX_DAC_IOFFSET_MSK 0x07800000
+#define RG_TX_DAC_IOFFSET_I_MSK 0xf87fffff
+#define RG_TX_DAC_IOFFSET_SFT 23
+#define RG_TX_DAC_IOFFSET_HI 26
+#define RG_TX_DAC_IOFFSET_SZ 4
+#define RG_TX_DAC_QOFFSET_MSK 0x78000000
+#define RG_TX_DAC_QOFFSET_I_MSK 0x87ffffff
+#define RG_TX_DAC_QOFFSET_SFT 27
+#define RG_TX_DAC_QOFFSET_HI 30
+#define RG_TX_DAC_QOFFSET_SZ 4
+#define RG_EN_SX_R3_MSK 0x00000001
+#define RG_EN_SX_R3_I_MSK 0xfffffffe
+#define RG_EN_SX_R3_SFT 0
+#define RG_EN_SX_R3_HI 0
+#define RG_EN_SX_R3_SZ 1
+#define RG_EN_SX_CH_MSK 0x00000002
+#define RG_EN_SX_CH_I_MSK 0xfffffffd
+#define RG_EN_SX_CH_SFT 1
+#define RG_EN_SX_CH_HI 1
+#define RG_EN_SX_CH_SZ 1
+#define RG_EN_SX_CHP_MSK 0x00000004
+#define RG_EN_SX_CHP_I_MSK 0xfffffffb
+#define RG_EN_SX_CHP_SFT 2
+#define RG_EN_SX_CHP_HI 2
+#define RG_EN_SX_CHP_SZ 1
+#define RG_EN_SX_DIVCK_MSK 0x00000008
+#define RG_EN_SX_DIVCK_I_MSK 0xfffffff7
+#define RG_EN_SX_DIVCK_SFT 3
+#define RG_EN_SX_DIVCK_HI 3
+#define RG_EN_SX_DIVCK_SZ 1
+#define RG_EN_SX_VCOBF_MSK 0x00000010
+#define RG_EN_SX_VCOBF_I_MSK 0xffffffef
+#define RG_EN_SX_VCOBF_SFT 4
+#define RG_EN_SX_VCOBF_HI 4
+#define RG_EN_SX_VCOBF_SZ 1
+#define RG_EN_SX_VCO_MSK 0x00000020
+#define RG_EN_SX_VCO_I_MSK 0xffffffdf
+#define RG_EN_SX_VCO_SFT 5
+#define RG_EN_SX_VCO_HI 5
+#define RG_EN_SX_VCO_SZ 1
+#define RG_EN_SX_MOD_MSK 0x00000040
+#define RG_EN_SX_MOD_I_MSK 0xffffffbf
+#define RG_EN_SX_MOD_SFT 6
+#define RG_EN_SX_MOD_HI 6
+#define RG_EN_SX_MOD_SZ 1
+#define RG_EN_SX_DITHER_MSK 0x00000100
+#define RG_EN_SX_DITHER_I_MSK 0xfffffeff
+#define RG_EN_SX_DITHER_SFT 8
+#define RG_EN_SX_DITHER_HI 8
+#define RG_EN_SX_DITHER_SZ 1
+#define RG_EN_SX_VT_MON_MSK 0x00000800
+#define RG_EN_SX_VT_MON_I_MSK 0xfffff7ff
+#define RG_EN_SX_VT_MON_SFT 11
+#define RG_EN_SX_VT_MON_HI 11
+#define RG_EN_SX_VT_MON_SZ 1
+#define RG_EN_SX_VT_MON_DG_MSK 0x00001000
+#define RG_EN_SX_VT_MON_DG_I_MSK 0xffffefff
+#define RG_EN_SX_VT_MON_DG_SFT 12
+#define RG_EN_SX_VT_MON_DG_HI 12
+#define RG_EN_SX_VT_MON_DG_SZ 1
+#define RG_EN_SX_DIV_MSK 0x00002000
+#define RG_EN_SX_DIV_I_MSK 0xffffdfff
+#define RG_EN_SX_DIV_SFT 13
+#define RG_EN_SX_DIV_HI 13
+#define RG_EN_SX_DIV_SZ 1
+#define RG_EN_SX_LPF_MSK 0x00004000
+#define RG_EN_SX_LPF_I_MSK 0xffffbfff
+#define RG_EN_SX_LPF_SFT 14
+#define RG_EN_SX_LPF_HI 14
+#define RG_EN_SX_LPF_SZ 1
+#define RG_EN_DPL_MOD_MSK 0x00008000
+#define RG_EN_DPL_MOD_I_MSK 0xffff7fff
+#define RG_EN_DPL_MOD_SFT 15
+#define RG_EN_DPL_MOD_HI 15
+#define RG_EN_DPL_MOD_SZ 1
+#define RG_DPL_MOD_ORDER_MSK 0x00030000
+#define RG_DPL_MOD_ORDER_I_MSK 0xfffcffff
+#define RG_DPL_MOD_ORDER_SFT 16
+#define RG_DPL_MOD_ORDER_HI 17
+#define RG_DPL_MOD_ORDER_SZ 2
+#define RG_SX_RFCTRL_F_MSK 0x00ffffff
+#define RG_SX_RFCTRL_F_I_MSK 0xff000000
+#define RG_SX_RFCTRL_F_SFT 0
+#define RG_SX_RFCTRL_F_HI 23
+#define RG_SX_RFCTRL_F_SZ 24
+#define RG_SX_SEL_CP_MSK 0x0f000000
+#define RG_SX_SEL_CP_I_MSK 0xf0ffffff
+#define RG_SX_SEL_CP_SFT 24
+#define RG_SX_SEL_CP_HI 27
+#define RG_SX_SEL_CP_SZ 4
+#define RG_SX_SEL_CS_MSK 0xf0000000
+#define RG_SX_SEL_CS_I_MSK 0x0fffffff
+#define RG_SX_SEL_CS_SFT 28
+#define RG_SX_SEL_CS_HI 31
+#define RG_SX_SEL_CS_SZ 4
+#define RG_SX_RFCTRL_CH_MSK 0x000007ff
+#define RG_SX_RFCTRL_CH_I_MSK 0xfffff800
+#define RG_SX_RFCTRL_CH_SFT 0
+#define RG_SX_RFCTRL_CH_HI 10
+#define RG_SX_RFCTRL_CH_SZ 11
+#define RG_SX_SEL_C3_MSK 0x00007800
+#define RG_SX_SEL_C3_I_MSK 0xffff87ff
+#define RG_SX_SEL_C3_SFT 11
+#define RG_SX_SEL_C3_HI 14
+#define RG_SX_SEL_C3_SZ 4
+#define RG_SX_SEL_RS_MSK 0x000f8000
+#define RG_SX_SEL_RS_I_MSK 0xfff07fff
+#define RG_SX_SEL_RS_SFT 15
+#define RG_SX_SEL_RS_HI 19
+#define RG_SX_SEL_RS_SZ 5
+#define RG_SX_SEL_R3_MSK 0x01f00000
+#define RG_SX_SEL_R3_I_MSK 0xfe0fffff
+#define RG_SX_SEL_R3_SFT 20
+#define RG_SX_SEL_R3_HI 24
+#define RG_SX_SEL_R3_SZ 5
+#define RG_SX_SEL_ICHP_MSK 0x0000001f
+#define RG_SX_SEL_ICHP_I_MSK 0xffffffe0
+#define RG_SX_SEL_ICHP_SFT 0
+#define RG_SX_SEL_ICHP_HI 4
+#define RG_SX_SEL_ICHP_SZ 5
+#define RG_SX_SEL_PCHP_MSK 0x000003e0
+#define RG_SX_SEL_PCHP_I_MSK 0xfffffc1f
+#define RG_SX_SEL_PCHP_SFT 5
+#define RG_SX_SEL_PCHP_HI 9
+#define RG_SX_SEL_PCHP_SZ 5
+#define RG_SX_SEL_CHP_REGOP_MSK 0x00003c00
+#define RG_SX_SEL_CHP_REGOP_I_MSK 0xffffc3ff
+#define RG_SX_SEL_CHP_REGOP_SFT 10
+#define RG_SX_SEL_CHP_REGOP_HI 13
+#define RG_SX_SEL_CHP_REGOP_SZ 4
+#define RG_SX_SEL_CHP_UNIOP_MSK 0x0003c000
+#define RG_SX_SEL_CHP_UNIOP_I_MSK 0xfffc3fff
+#define RG_SX_SEL_CHP_UNIOP_SFT 14
+#define RG_SX_SEL_CHP_UNIOP_HI 17
+#define RG_SX_SEL_CHP_UNIOP_SZ 4
+#define RG_SX_CHP_IOST_POL_MSK 0x00040000
+#define RG_SX_CHP_IOST_POL_I_MSK 0xfffbffff
+#define RG_SX_CHP_IOST_POL_SFT 18
+#define RG_SX_CHP_IOST_POL_HI 18
+#define RG_SX_CHP_IOST_POL_SZ 1
+#define RG_SX_CHP_IOST_MSK 0x00380000
+#define RG_SX_CHP_IOST_I_MSK 0xffc7ffff
+#define RG_SX_CHP_IOST_SFT 19
+#define RG_SX_CHP_IOST_HI 21
+#define RG_SX_CHP_IOST_SZ 3
+#define RG_SX_PFDSEL_MSK 0x00400000
+#define RG_SX_PFDSEL_I_MSK 0xffbfffff
+#define RG_SX_PFDSEL_SFT 22
+#define RG_SX_PFDSEL_HI 22
+#define RG_SX_PFDSEL_SZ 1
+#define RG_SX_PFD_SET_MSK 0x00800000
+#define RG_SX_PFD_SET_I_MSK 0xff7fffff
+#define RG_SX_PFD_SET_SFT 23
+#define RG_SX_PFD_SET_HI 23
+#define RG_SX_PFD_SET_SZ 1
+#define RG_SX_PFD_SET1_MSK 0x01000000
+#define RG_SX_PFD_SET1_I_MSK 0xfeffffff
+#define RG_SX_PFD_SET1_SFT 24
+#define RG_SX_PFD_SET1_HI 24
+#define RG_SX_PFD_SET1_SZ 1
+#define RG_SX_PFD_SET2_MSK 0x02000000
+#define RG_SX_PFD_SET2_I_MSK 0xfdffffff
+#define RG_SX_PFD_SET2_SFT 25
+#define RG_SX_PFD_SET2_HI 25
+#define RG_SX_PFD_SET2_SZ 1
+#define RG_SX_VBNCAS_SEL_MSK 0x04000000
+#define RG_SX_VBNCAS_SEL_I_MSK 0xfbffffff
+#define RG_SX_VBNCAS_SEL_SFT 26
+#define RG_SX_VBNCAS_SEL_HI 26
+#define RG_SX_VBNCAS_SEL_SZ 1
+#define RG_SX_PFD_RST_H_MSK 0x08000000
+#define RG_SX_PFD_RST_H_I_MSK 0xf7ffffff
+#define RG_SX_PFD_RST_H_SFT 27
+#define RG_SX_PFD_RST_H_HI 27
+#define RG_SX_PFD_RST_H_SZ 1
+#define RG_SX_PFD_TRUP_MSK 0x10000000
+#define RG_SX_PFD_TRUP_I_MSK 0xefffffff
+#define RG_SX_PFD_TRUP_SFT 28
+#define RG_SX_PFD_TRUP_HI 28
+#define RG_SX_PFD_TRUP_SZ 1
+#define RG_SX_PFD_TRDN_MSK 0x20000000
+#define RG_SX_PFD_TRDN_I_MSK 0xdfffffff
+#define RG_SX_PFD_TRDN_SFT 29
+#define RG_SX_PFD_TRDN_HI 29
+#define RG_SX_PFD_TRDN_SZ 1
+#define RG_SX_PFD_TRSEL_MSK 0x40000000
+#define RG_SX_PFD_TRSEL_I_MSK 0xbfffffff
+#define RG_SX_PFD_TRSEL_SFT 30
+#define RG_SX_PFD_TRSEL_HI 30
+#define RG_SX_PFD_TRSEL_SZ 1
+#define RG_SX_VCOBA_R_MSK 0x00000007
+#define RG_SX_VCOBA_R_I_MSK 0xfffffff8
+#define RG_SX_VCOBA_R_SFT 0
+#define RG_SX_VCOBA_R_HI 2
+#define RG_SX_VCOBA_R_SZ 3
+#define RG_SX_VCORSEL_MSK 0x000000f8
+#define RG_SX_VCORSEL_I_MSK 0xffffff07
+#define RG_SX_VCORSEL_SFT 3
+#define RG_SX_VCORSEL_HI 7
+#define RG_SX_VCORSEL_SZ 5
+#define RG_SX_VCOCUSEL_MSK 0x00000f00
+#define RG_SX_VCOCUSEL_I_MSK 0xfffff0ff
+#define RG_SX_VCOCUSEL_SFT 8
+#define RG_SX_VCOCUSEL_HI 11
+#define RG_SX_VCOCUSEL_SZ 4
+#define RG_SX_RXBFSEL_MSK 0x0000f000
+#define RG_SX_RXBFSEL_I_MSK 0xffff0fff
+#define RG_SX_RXBFSEL_SFT 12
+#define RG_SX_RXBFSEL_HI 15
+#define RG_SX_RXBFSEL_SZ 4
+#define RG_SX_TXBFSEL_MSK 0x000f0000
+#define RG_SX_TXBFSEL_I_MSK 0xfff0ffff
+#define RG_SX_TXBFSEL_SFT 16
+#define RG_SX_TXBFSEL_HI 19
+#define RG_SX_TXBFSEL_SZ 4
+#define RG_SX_VCOBFSEL_MSK 0x00f00000
+#define RG_SX_VCOBFSEL_I_MSK 0xff0fffff
+#define RG_SX_VCOBFSEL_SFT 20
+#define RG_SX_VCOBFSEL_HI 23
+#define RG_SX_VCOBFSEL_SZ 4
+#define RG_SX_DIVBFSEL_MSK 0x0f000000
+#define RG_SX_DIVBFSEL_I_MSK 0xf0ffffff
+#define RG_SX_DIVBFSEL_SFT 24
+#define RG_SX_DIVBFSEL_HI 27
+#define RG_SX_DIVBFSEL_SZ 4
+#define RG_SX_GNDR_SEL_MSK 0xf0000000
+#define RG_SX_GNDR_SEL_I_MSK 0x0fffffff
+#define RG_SX_GNDR_SEL_SFT 28
+#define RG_SX_GNDR_SEL_HI 31
+#define RG_SX_GNDR_SEL_SZ 4
+#define RG_SX_DITHER_WEIGHT_MSK 0x00000003
+#define RG_SX_DITHER_WEIGHT_I_MSK 0xfffffffc
+#define RG_SX_DITHER_WEIGHT_SFT 0
+#define RG_SX_DITHER_WEIGHT_HI 1
+#define RG_SX_DITHER_WEIGHT_SZ 2
+#define RG_SX_MOD_ORDER_MSK 0x00000030
+#define RG_SX_MOD_ORDER_I_MSK 0xffffffcf
+#define RG_SX_MOD_ORDER_SFT 4
+#define RG_SX_MOD_ORDER_HI 5
+#define RG_SX_MOD_ORDER_SZ 2
+#define RG_SX_RST_H_DIV_MSK 0x00000200
+#define RG_SX_RST_H_DIV_I_MSK 0xfffffdff
+#define RG_SX_RST_H_DIV_SFT 9
+#define RG_SX_RST_H_DIV_HI 9
+#define RG_SX_RST_H_DIV_SZ 1
+#define RG_SX_SDM_EDGE_MSK 0x00000400
+#define RG_SX_SDM_EDGE_I_MSK 0xfffffbff
+#define RG_SX_SDM_EDGE_SFT 10
+#define RG_SX_SDM_EDGE_HI 10
+#define RG_SX_SDM_EDGE_SZ 1
+#define RG_SX_XO_GM_MSK 0x00001800
+#define RG_SX_XO_GM_I_MSK 0xffffe7ff
+#define RG_SX_XO_GM_SFT 11
+#define RG_SX_XO_GM_HI 12
+#define RG_SX_XO_GM_SZ 2
+#define RG_SX_REFBYTWO_MSK 0x00002000
+#define RG_SX_REFBYTWO_I_MSK 0xffffdfff
+#define RG_SX_REFBYTWO_SFT 13
+#define RG_SX_REFBYTWO_HI 13
+#define RG_SX_REFBYTWO_SZ 1
+#define RG_SX_LCKEN_MSK 0x00080000
+#define RG_SX_LCKEN_I_MSK 0xfff7ffff
+#define RG_SX_LCKEN_SFT 19
+#define RG_SX_LCKEN_HI 19
+#define RG_SX_LCKEN_SZ 1
+#define RG_SX_PREVDD_MSK 0x00f00000
+#define RG_SX_PREVDD_I_MSK 0xff0fffff
+#define RG_SX_PREVDD_SFT 20
+#define RG_SX_PREVDD_HI 23
+#define RG_SX_PREVDD_SZ 4
+#define RG_SX_PSCONTERVDD_MSK 0x0f000000
+#define RG_SX_PSCONTERVDD_I_MSK 0xf0ffffff
+#define RG_SX_PSCONTERVDD_SFT 24
+#define RG_SX_PSCONTERVDD_HI 27
+#define RG_SX_PSCONTERVDD_SZ 4
+#define RG_SX_PH_MSK 0x00002000
+#define RG_SX_PH_I_MSK 0xffffdfff
+#define RG_SX_PH_SFT 13
+#define RG_SX_PH_HI 13
+#define RG_SX_PH_SZ 1
+#define RG_SX_PL_MSK 0x00004000
+#define RG_SX_PL_I_MSK 0xffffbfff
+#define RG_SX_PL_SFT 14
+#define RG_SX_PL_HI 14
+#define RG_SX_PL_SZ 1
+#define RG_XOSC_CBANK_XO_MSK 0x00078000
+#define RG_XOSC_CBANK_XO_I_MSK 0xfff87fff
+#define RG_XOSC_CBANK_XO_SFT 15
+#define RG_XOSC_CBANK_XO_HI 18
+#define RG_XOSC_CBANK_XO_SZ 4
+#define RG_XOSC_CBANK_XI_MSK 0x00780000
+#define RG_XOSC_CBANK_XI_I_MSK 0xff87ffff
+#define RG_XOSC_CBANK_XI_SFT 19
+#define RG_XOSC_CBANK_XI_HI 22
+#define RG_XOSC_CBANK_XI_SZ 4
+#define RG_SX_VT_MON_MODE_MSK 0x00000001
+#define RG_SX_VT_MON_MODE_I_MSK 0xfffffffe
+#define RG_SX_VT_MON_MODE_SFT 0
+#define RG_SX_VT_MON_MODE_HI 0
+#define RG_SX_VT_MON_MODE_SZ 1
+#define RG_SX_VT_TH_HI_MSK 0x00000006
+#define RG_SX_VT_TH_HI_I_MSK 0xfffffff9
+#define RG_SX_VT_TH_HI_SFT 1
+#define RG_SX_VT_TH_HI_HI 2
+#define RG_SX_VT_TH_HI_SZ 2
+#define RG_SX_VT_TH_LO_MSK 0x00000018
+#define RG_SX_VT_TH_LO_I_MSK 0xffffffe7
+#define RG_SX_VT_TH_LO_SFT 3
+#define RG_SX_VT_TH_LO_HI 4
+#define RG_SX_VT_TH_LO_SZ 2
+#define RG_SX_VT_SET_MSK 0x00000020
+#define RG_SX_VT_SET_I_MSK 0xffffffdf
+#define RG_SX_VT_SET_SFT 5
+#define RG_SX_VT_SET_HI 5
+#define RG_SX_VT_SET_SZ 1
+#define RG_SX_VT_MON_TMR_MSK 0x00007fc0
+#define RG_SX_VT_MON_TMR_I_MSK 0xffff803f
+#define RG_SX_VT_MON_TMR_SFT 6
+#define RG_SX_VT_MON_TMR_HI 14
+#define RG_SX_VT_MON_TMR_SZ 9
+#define RG_EN_DP_VT_MON_MSK 0x00000001
+#define RG_EN_DP_VT_MON_I_MSK 0xfffffffe
+#define RG_EN_DP_VT_MON_SFT 0
+#define RG_EN_DP_VT_MON_HI 0
+#define RG_EN_DP_VT_MON_SZ 1
+#define RG_DP_VT_TH_HI_MSK 0x00000006
+#define RG_DP_VT_TH_HI_I_MSK 0xfffffff9
+#define RG_DP_VT_TH_HI_SFT 1
+#define RG_DP_VT_TH_HI_HI 2
+#define RG_DP_VT_TH_HI_SZ 2
+#define RG_DP_VT_TH_LO_MSK 0x00000018
+#define RG_DP_VT_TH_LO_I_MSK 0xffffffe7
+#define RG_DP_VT_TH_LO_SFT 3
+#define RG_DP_VT_TH_LO_HI 4
+#define RG_DP_VT_TH_LO_SZ 2
+#define RG_DP_CK320BY2_MSK 0x00004000
+#define RG_DP_CK320BY2_I_MSK 0xffffbfff
+#define RG_DP_CK320BY2_SFT 14
+#define RG_DP_CK320BY2_HI 14
+#define RG_DP_CK320BY2_SZ 1
+#define RG_DP_OD_TEST_MSK 0x00200000
+#define RG_DP_OD_TEST_I_MSK 0xffdfffff
+#define RG_DP_OD_TEST_SFT 21
+#define RG_DP_OD_TEST_HI 21
+#define RG_DP_OD_TEST_SZ 1
+#define RG_DP_BBPLL_BP_MSK 0x00000001
+#define RG_DP_BBPLL_BP_I_MSK 0xfffffffe
+#define RG_DP_BBPLL_BP_SFT 0
+#define RG_DP_BBPLL_BP_HI 0
+#define RG_DP_BBPLL_BP_SZ 1
+#define RG_DP_BBPLL_ICP_MSK 0x00000006
+#define RG_DP_BBPLL_ICP_I_MSK 0xfffffff9
+#define RG_DP_BBPLL_ICP_SFT 1
+#define RG_DP_BBPLL_ICP_HI 2
+#define RG_DP_BBPLL_ICP_SZ 2
+#define RG_DP_BBPLL_IDUAL_MSK 0x00000018
+#define RG_DP_BBPLL_IDUAL_I_MSK 0xffffffe7
+#define RG_DP_BBPLL_IDUAL_SFT 3
+#define RG_DP_BBPLL_IDUAL_HI 4
+#define RG_DP_BBPLL_IDUAL_SZ 2
+#define RG_DP_BBPLL_OD_TEST_MSK 0x000001e0
+#define RG_DP_BBPLL_OD_TEST_I_MSK 0xfffffe1f
+#define RG_DP_BBPLL_OD_TEST_SFT 5
+#define RG_DP_BBPLL_OD_TEST_HI 8
+#define RG_DP_BBPLL_OD_TEST_SZ 4
+#define RG_DP_BBPLL_PD_MSK 0x00000200
+#define RG_DP_BBPLL_PD_I_MSK 0xfffffdff
+#define RG_DP_BBPLL_PD_SFT 9
+#define RG_DP_BBPLL_PD_HI 9
+#define RG_DP_BBPLL_PD_SZ 1
+#define RG_DP_BBPLL_TESTSEL_MSK 0x00001c00
+#define RG_DP_BBPLL_TESTSEL_I_MSK 0xffffe3ff
+#define RG_DP_BBPLL_TESTSEL_SFT 10
+#define RG_DP_BBPLL_TESTSEL_HI 12
+#define RG_DP_BBPLL_TESTSEL_SZ 3
+#define RG_DP_BBPLL_PFD_DLY_MSK 0x00006000
+#define RG_DP_BBPLL_PFD_DLY_I_MSK 0xffff9fff
+#define RG_DP_BBPLL_PFD_DLY_SFT 13
+#define RG_DP_BBPLL_PFD_DLY_HI 14
+#define RG_DP_BBPLL_PFD_DLY_SZ 2
+#define RG_DP_RP_MSK 0x00038000
+#define RG_DP_RP_I_MSK 0xfffc7fff
+#define RG_DP_RP_SFT 15
+#define RG_DP_RP_HI 17
+#define RG_DP_RP_SZ 3
+#define RG_DP_RHP_MSK 0x000c0000
+#define RG_DP_RHP_I_MSK 0xfff3ffff
+#define RG_DP_RHP_SFT 18
+#define RG_DP_RHP_HI 19
+#define RG_DP_RHP_SZ 2
+#define RG_DP_BBPLL_SDM_EDGE_MSK 0x80000000
+#define RG_DP_BBPLL_SDM_EDGE_I_MSK 0x7fffffff
+#define RG_DP_BBPLL_SDM_EDGE_SFT 31
+#define RG_DP_BBPLL_SDM_EDGE_HI 31
+#define RG_DP_BBPLL_SDM_EDGE_SZ 1
+#define RG_DP_FODIV_MSK 0x0007f000
+#define RG_DP_FODIV_I_MSK 0xfff80fff
+#define RG_DP_FODIV_SFT 12
+#define RG_DP_FODIV_HI 18
+#define RG_DP_FODIV_SZ 7
+#define RG_DP_REFDIV_MSK 0x1fc00000
+#define RG_DP_REFDIV_I_MSK 0xe03fffff
+#define RG_DP_REFDIV_SFT 22
+#define RG_DP_REFDIV_HI 28
+#define RG_DP_REFDIV_SZ 7
+#define RG_IDACAI_PGAG15_MSK 0x0000003f
+#define RG_IDACAI_PGAG15_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG15_SFT 0
+#define RG_IDACAI_PGAG15_HI 5
+#define RG_IDACAI_PGAG15_SZ 6
+#define RG_IDACAQ_PGAG15_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG15_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG15_SFT 6
+#define RG_IDACAQ_PGAG15_HI 11
+#define RG_IDACAQ_PGAG15_SZ 6
+#define RG_IDACAI_PGAG14_MSK 0x0003f000
+#define RG_IDACAI_PGAG14_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG14_SFT 12
+#define RG_IDACAI_PGAG14_HI 17
+#define RG_IDACAI_PGAG14_SZ 6
+#define RG_IDACAQ_PGAG14_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG14_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG14_SFT 18
+#define RG_IDACAQ_PGAG14_HI 23
+#define RG_IDACAQ_PGAG14_SZ 6
+#define RG_DP_BBPLL_BS_MSK 0x3f000000
+#define RG_DP_BBPLL_BS_I_MSK 0xc0ffffff
+#define RG_DP_BBPLL_BS_SFT 24
+#define RG_DP_BBPLL_BS_HI 29
+#define RG_DP_BBPLL_BS_SZ 6
+#define RG_IDACAI_PGAG13_MSK 0x0000003f
+#define RG_IDACAI_PGAG13_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG13_SFT 0
+#define RG_IDACAI_PGAG13_HI 5
+#define RG_IDACAI_PGAG13_SZ 6
+#define RG_IDACAQ_PGAG13_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG13_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG13_SFT 6
+#define RG_IDACAQ_PGAG13_HI 11
+#define RG_IDACAQ_PGAG13_SZ 6
+#define RG_IDACAI_PGAG12_MSK 0x0003f000
+#define RG_IDACAI_PGAG12_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG12_SFT 12
+#define RG_IDACAI_PGAG12_HI 17
+#define RG_IDACAI_PGAG12_SZ 6
+#define RG_IDACAQ_PGAG12_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG12_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG12_SFT 18
+#define RG_IDACAQ_PGAG12_HI 23
+#define RG_IDACAQ_PGAG12_SZ 6
+#define RG_IDACAI_PGAG11_MSK 0x0000003f
+#define RG_IDACAI_PGAG11_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG11_SFT 0
+#define RG_IDACAI_PGAG11_HI 5
+#define RG_IDACAI_PGAG11_SZ 6
+#define RG_IDACAQ_PGAG11_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG11_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG11_SFT 6
+#define RG_IDACAQ_PGAG11_HI 11
+#define RG_IDACAQ_PGAG11_SZ 6
+#define RG_IDACAI_PGAG10_MSK 0x0003f000
+#define RG_IDACAI_PGAG10_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG10_SFT 12
+#define RG_IDACAI_PGAG10_HI 17
+#define RG_IDACAI_PGAG10_SZ 6
+#define RG_IDACAQ_PGAG10_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG10_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG10_SFT 18
+#define RG_IDACAQ_PGAG10_HI 23
+#define RG_IDACAQ_PGAG10_SZ 6
+#define RG_IDACAI_PGAG9_MSK 0x0000003f
+#define RG_IDACAI_PGAG9_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG9_SFT 0
+#define RG_IDACAI_PGAG9_HI 5
+#define RG_IDACAI_PGAG9_SZ 6
+#define RG_IDACAQ_PGAG9_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG9_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG9_SFT 6
+#define RG_IDACAQ_PGAG9_HI 11
+#define RG_IDACAQ_PGAG9_SZ 6
+#define RG_IDACAI_PGAG8_MSK 0x0003f000
+#define RG_IDACAI_PGAG8_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG8_SFT 12
+#define RG_IDACAI_PGAG8_HI 17
+#define RG_IDACAI_PGAG8_SZ 6
+#define RG_IDACAQ_PGAG8_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG8_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG8_SFT 18
+#define RG_IDACAQ_PGAG8_HI 23
+#define RG_IDACAQ_PGAG8_SZ 6
+#define RG_IDACAI_PGAG7_MSK 0x0000003f
+#define RG_IDACAI_PGAG7_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG7_SFT 0
+#define RG_IDACAI_PGAG7_HI 5
+#define RG_IDACAI_PGAG7_SZ 6
+#define RG_IDACAQ_PGAG7_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG7_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG7_SFT 6
+#define RG_IDACAQ_PGAG7_HI 11
+#define RG_IDACAQ_PGAG7_SZ 6
+#define RG_IDACAI_PGAG6_MSK 0x0003f000
+#define RG_IDACAI_PGAG6_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG6_SFT 12
+#define RG_IDACAI_PGAG6_HI 17
+#define RG_IDACAI_PGAG6_SZ 6
+#define RG_IDACAQ_PGAG6_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG6_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG6_SFT 18
+#define RG_IDACAQ_PGAG6_HI 23
+#define RG_IDACAQ_PGAG6_SZ 6
+#define RG_IDACAI_PGAG5_MSK 0x0000003f
+#define RG_IDACAI_PGAG5_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG5_SFT 0
+#define RG_IDACAI_PGAG5_HI 5
+#define RG_IDACAI_PGAG5_SZ 6
+#define RG_IDACAQ_PGAG5_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG5_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG5_SFT 6
+#define RG_IDACAQ_PGAG5_HI 11
+#define RG_IDACAQ_PGAG5_SZ 6
+#define RG_IDACAI_PGAG4_MSK 0x0003f000
+#define RG_IDACAI_PGAG4_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG4_SFT 12
+#define RG_IDACAI_PGAG4_HI 17
+#define RG_IDACAI_PGAG4_SZ 6
+#define RG_IDACAQ_PGAG4_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG4_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG4_SFT 18
+#define RG_IDACAQ_PGAG4_HI 23
+#define RG_IDACAQ_PGAG4_SZ 6
+#define RG_IDACAI_PGAG3_MSK 0x0000003f
+#define RG_IDACAI_PGAG3_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG3_SFT 0
+#define RG_IDACAI_PGAG3_HI 5
+#define RG_IDACAI_PGAG3_SZ 6
+#define RG_IDACAQ_PGAG3_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG3_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG3_SFT 6
+#define RG_IDACAQ_PGAG3_HI 11
+#define RG_IDACAQ_PGAG3_SZ 6
+#define RG_IDACAI_PGAG2_MSK 0x0003f000
+#define RG_IDACAI_PGAG2_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG2_SFT 12
+#define RG_IDACAI_PGAG2_HI 17
+#define RG_IDACAI_PGAG2_SZ 6
+#define RG_IDACAQ_PGAG2_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG2_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG2_SFT 18
+#define RG_IDACAQ_PGAG2_HI 23
+#define RG_IDACAQ_PGAG2_SZ 6
+#define RG_IDACAI_PGAG1_MSK 0x0000003f
+#define RG_IDACAI_PGAG1_I_MSK 0xffffffc0
+#define RG_IDACAI_PGAG1_SFT 0
+#define RG_IDACAI_PGAG1_HI 5
+#define RG_IDACAI_PGAG1_SZ 6
+#define RG_IDACAQ_PGAG1_MSK 0x00000fc0
+#define RG_IDACAQ_PGAG1_I_MSK 0xfffff03f
+#define RG_IDACAQ_PGAG1_SFT 6
+#define RG_IDACAQ_PGAG1_HI 11
+#define RG_IDACAQ_PGAG1_SZ 6
+#define RG_IDACAI_PGAG0_MSK 0x0003f000
+#define RG_IDACAI_PGAG0_I_MSK 0xfffc0fff
+#define RG_IDACAI_PGAG0_SFT 12
+#define RG_IDACAI_PGAG0_HI 17
+#define RG_IDACAI_PGAG0_SZ 6
+#define RG_IDACAQ_PGAG0_MSK 0x00fc0000
+#define RG_IDACAQ_PGAG0_I_MSK 0xff03ffff
+#define RG_IDACAQ_PGAG0_SFT 18
+#define RG_IDACAQ_PGAG0_HI 23
+#define RG_IDACAQ_PGAG0_SZ 6
+#define RG_EN_RCAL_MSK 0x00000001
+#define RG_EN_RCAL_I_MSK 0xfffffffe
+#define RG_EN_RCAL_SFT 0
+#define RG_EN_RCAL_HI 0
+#define RG_EN_RCAL_SZ 1
+#define RG_RCAL_SPD_MSK 0x00000002
+#define RG_RCAL_SPD_I_MSK 0xfffffffd
+#define RG_RCAL_SPD_SFT 1
+#define RG_RCAL_SPD_HI 1
+#define RG_RCAL_SPD_SZ 1
+#define RG_RCAL_TMR_MSK 0x000001fc
+#define RG_RCAL_TMR_I_MSK 0xfffffe03
+#define RG_RCAL_TMR_SFT 2
+#define RG_RCAL_TMR_HI 8
+#define RG_RCAL_TMR_SZ 7
+#define RG_RCAL_CODE_CWR_MSK 0x00000200
+#define RG_RCAL_CODE_CWR_I_MSK 0xfffffdff
+#define RG_RCAL_CODE_CWR_SFT 9
+#define RG_RCAL_CODE_CWR_HI 9
+#define RG_RCAL_CODE_CWR_SZ 1
+#define RG_RCAL_CODE_CWD_MSK 0x00007c00
+#define RG_RCAL_CODE_CWD_I_MSK 0xffff83ff
+#define RG_RCAL_CODE_CWD_SFT 10
+#define RG_RCAL_CODE_CWD_HI 14
+#define RG_RCAL_CODE_CWD_SZ 5
+#define RG_SX_SUB_SEL_CWR_MSK 0x00000001
+#define RG_SX_SUB_SEL_CWR_I_MSK 0xfffffffe
+#define RG_SX_SUB_SEL_CWR_SFT 0
+#define RG_SX_SUB_SEL_CWR_HI 0
+#define RG_SX_SUB_SEL_CWR_SZ 1
+#define RG_SX_SUB_SEL_CWD_MSK 0x000000fe
+#define RG_SX_SUB_SEL_CWD_I_MSK 0xffffff01
+#define RG_SX_SUB_SEL_CWD_SFT 1
+#define RG_SX_SUB_SEL_CWD_HI 7
+#define RG_SX_SUB_SEL_CWD_SZ 7
+#define RG_SX_LCK_BIN_OFFSET_MSK 0x00078000
+#define RG_SX_LCK_BIN_OFFSET_I_MSK 0xfff87fff
+#define RG_SX_LCK_BIN_OFFSET_SFT 15
+#define RG_SX_LCK_BIN_OFFSET_HI 18
+#define RG_SX_LCK_BIN_OFFSET_SZ 4
+#define RG_SX_LCK_BIN_PRECISION_MSK 0x00080000
+#define RG_SX_LCK_BIN_PRECISION_I_MSK 0xfff7ffff
+#define RG_SX_LCK_BIN_PRECISION_SFT 19
+#define RG_SX_LCK_BIN_PRECISION_HI 19
+#define RG_SX_LCK_BIN_PRECISION_SZ 1
+#define RG_SX_LOCK_EN_N_MSK 0x00100000
+#define RG_SX_LOCK_EN_N_I_MSK 0xffefffff
+#define RG_SX_LOCK_EN_N_SFT 20
+#define RG_SX_LOCK_EN_N_HI 20
+#define RG_SX_LOCK_EN_N_SZ 1
+#define RG_SX_LOCK_MANUAL_MSK 0x00200000
+#define RG_SX_LOCK_MANUAL_I_MSK 0xffdfffff
+#define RG_SX_LOCK_MANUAL_SFT 21
+#define RG_SX_LOCK_MANUAL_HI 21
+#define RG_SX_LOCK_MANUAL_SZ 1
+#define RG_SX_SUB_MANUAL_MSK 0x00400000
+#define RG_SX_SUB_MANUAL_I_MSK 0xffbfffff
+#define RG_SX_SUB_MANUAL_SFT 22
+#define RG_SX_SUB_MANUAL_HI 22
+#define RG_SX_SUB_MANUAL_SZ 1
+#define RG_SX_SUB_SEL_MSK 0x3f800000
+#define RG_SX_SUB_SEL_I_MSK 0xc07fffff
+#define RG_SX_SUB_SEL_SFT 23
+#define RG_SX_SUB_SEL_HI 29
+#define RG_SX_SUB_SEL_SZ 7
+#define RG_SX_MUX_SEL_VTH_BINL_MSK 0x40000000
+#define RG_SX_MUX_SEL_VTH_BINL_I_MSK 0xbfffffff
+#define RG_SX_MUX_SEL_VTH_BINL_SFT 30
+#define RG_SX_MUX_SEL_VTH_BINL_HI 30
+#define RG_SX_MUX_SEL_VTH_BINL_SZ 1
+#define RG_TRX_DUMMMY_MSK 0xffffffff
+#define RG_TRX_DUMMMY_I_MSK 0x00000000
+#define RG_TRX_DUMMMY_SFT 0
+#define RG_TRX_DUMMMY_HI 31
+#define RG_TRX_DUMMMY_SZ 32
+#define RG_SX_DUMMMY_MSK 0xffffffff
+#define RG_SX_DUMMMY_I_MSK 0x00000000
+#define RG_SX_DUMMMY_SFT 0
+#define RG_SX_DUMMMY_HI 31
+#define RG_SX_DUMMMY_SZ 32
+#define RCAL_RDY_MSK 0x00000001
+#define RCAL_RDY_I_MSK 0xfffffffe
+#define RCAL_RDY_SFT 0
+#define RCAL_RDY_HI 0
+#define RCAL_RDY_SZ 1
+#define LCK_BIN_RDY_MSK 0x00000002
+#define LCK_BIN_RDY_I_MSK 0xfffffffd
+#define LCK_BIN_RDY_SFT 1
+#define LCK_BIN_RDY_HI 1
+#define LCK_BIN_RDY_SZ 1
+#define VT_MON_RDY_MSK 0x00000004
+#define VT_MON_RDY_I_MSK 0xfffffffb
+#define VT_MON_RDY_SFT 2
+#define VT_MON_RDY_HI 2
+#define VT_MON_RDY_SZ 1
+#define DA_R_CODE_LUT_MSK 0x000007c0
+#define DA_R_CODE_LUT_I_MSK 0xfffff83f
+#define DA_R_CODE_LUT_SFT 6
+#define DA_R_CODE_LUT_HI 10
+#define DA_R_CODE_LUT_SZ 5
+#define AD_SX_VT_MON_Q_MSK 0x00001800
+#define AD_SX_VT_MON_Q_I_MSK 0xffffe7ff
+#define AD_SX_VT_MON_Q_SFT 11
+#define AD_SX_VT_MON_Q_HI 12
+#define AD_SX_VT_MON_Q_SZ 2
+#define AD_DP_VT_MON_Q_MSK 0x00006000
+#define AD_DP_VT_MON_Q_I_MSK 0xffff9fff
+#define AD_DP_VT_MON_Q_SFT 13
+#define AD_DP_VT_MON_Q_HI 14
+#define AD_DP_VT_MON_Q_SZ 2
+#define RTC_CAL_RDY_MSK 0x00008000
+#define RTC_CAL_RDY_I_MSK 0xffff7fff
+#define RTC_CAL_RDY_SFT 15
+#define RTC_CAL_RDY_HI 15
+#define RTC_CAL_RDY_SZ 1
+#define RG_SARADC_BIT_MSK 0x003f0000
+#define RG_SARADC_BIT_I_MSK 0xffc0ffff
+#define RG_SARADC_BIT_SFT 16
+#define RG_SARADC_BIT_HI 21
+#define RG_SARADC_BIT_SZ 6
+#define SAR_ADC_FSM_RDY_MSK 0x00400000
+#define SAR_ADC_FSM_RDY_I_MSK 0xffbfffff
+#define SAR_ADC_FSM_RDY_SFT 22
+#define SAR_ADC_FSM_RDY_HI 22
+#define SAR_ADC_FSM_RDY_SZ 1
+#define AD_CIRCUIT_VERSION_MSK 0x07800000
+#define AD_CIRCUIT_VERSION_I_MSK 0xf87fffff
+#define AD_CIRCUIT_VERSION_SFT 23
+#define AD_CIRCUIT_VERSION_HI 26
+#define AD_CIRCUIT_VERSION_SZ 4
+#define DA_R_CAL_CODE_MSK 0x0000001f
+#define DA_R_CAL_CODE_I_MSK 0xffffffe0
+#define DA_R_CAL_CODE_SFT 0
+#define DA_R_CAL_CODE_HI 4
+#define DA_R_CAL_CODE_SZ 5
+#define DA_SX_SUB_SEL_MSK 0x00000fe0
+#define DA_SX_SUB_SEL_I_MSK 0xfffff01f
+#define DA_SX_SUB_SEL_SFT 5
+#define DA_SX_SUB_SEL_HI 11
+#define DA_SX_SUB_SEL_SZ 7
+#define RG_DPL_RFCTRL_CH_MSK 0x000007ff
+#define RG_DPL_RFCTRL_CH_I_MSK 0xfffff800
+#define RG_DPL_RFCTRL_CH_SFT 0
+#define RG_DPL_RFCTRL_CH_HI 10
+#define RG_DPL_RFCTRL_CH_SZ 11
+#define RG_RSSIADC_RO_BIT_MSK 0x00007800
+#define RG_RSSIADC_RO_BIT_I_MSK 0xffff87ff
+#define RG_RSSIADC_RO_BIT_SFT 11
+#define RG_RSSIADC_RO_BIT_HI 14
+#define RG_RSSIADC_RO_BIT_SZ 4
+#define RG_RX_ADC_I_RO_BIT_MSK 0x007f8000
+#define RG_RX_ADC_I_RO_BIT_I_MSK 0xff807fff
+#define RG_RX_ADC_I_RO_BIT_SFT 15
+#define RG_RX_ADC_I_RO_BIT_HI 22
+#define RG_RX_ADC_I_RO_BIT_SZ 8
+#define RG_RX_ADC_Q_RO_BIT_MSK 0x7f800000
+#define RG_RX_ADC_Q_RO_BIT_I_MSK 0x807fffff
+#define RG_RX_ADC_Q_RO_BIT_SFT 23
+#define RG_RX_ADC_Q_RO_BIT_HI 30
+#define RG_RX_ADC_Q_RO_BIT_SZ 8
+#define RG_DPL_RFCTRL_F_MSK 0x00ffffff
+#define RG_DPL_RFCTRL_F_I_MSK 0xff000000
+#define RG_DPL_RFCTRL_F_SFT 0
+#define RG_DPL_RFCTRL_F_HI 23
+#define RG_DPL_RFCTRL_F_SZ 24
+#define RG_SX_TARGET_CNT_MSK 0x00001fff
+#define RG_SX_TARGET_CNT_I_MSK 0xffffe000
+#define RG_SX_TARGET_CNT_SFT 0
+#define RG_SX_TARGET_CNT_HI 12
+#define RG_SX_TARGET_CNT_SZ 13
+#define RG_RTC_OFFSET_MSK 0x000000ff
+#define RG_RTC_OFFSET_I_MSK 0xffffff00
+#define RG_RTC_OFFSET_SFT 0
+#define RG_RTC_OFFSET_HI 7
+#define RG_RTC_OFFSET_SZ 8
+#define RG_RTC_CAL_TARGET_COUNT_MSK 0x000fff00
+#define RG_RTC_CAL_TARGET_COUNT_I_MSK 0xfff000ff
+#define RG_RTC_CAL_TARGET_COUNT_SFT 8
+#define RG_RTC_CAL_TARGET_COUNT_HI 19
+#define RG_RTC_CAL_TARGET_COUNT_SZ 12
+#define RG_RF_D_REG_MSK 0x0000ffff
+#define RG_RF_D_REG_I_MSK 0xffff0000
+#define RG_RF_D_REG_SFT 0
+#define RG_RF_D_REG_HI 15
+#define RG_RF_D_REG_SZ 16
+#define DIRECT_MODE_MSK 0x00000001
+#define DIRECT_MODE_I_MSK 0xfffffffe
+#define DIRECT_MODE_SFT 0
+#define DIRECT_MODE_HI 0
+#define DIRECT_MODE_SZ 1
+#define TAG_INTERLEAVE_MD_MSK 0x00000002
+#define TAG_INTERLEAVE_MD_I_MSK 0xfffffffd
+#define TAG_INTERLEAVE_MD_SFT 1
+#define TAG_INTERLEAVE_MD_HI 1
+#define TAG_INTERLEAVE_MD_SZ 1
+#define DIS_DEMAND_MSK 0x00000004
+#define DIS_DEMAND_I_MSK 0xfffffffb
+#define DIS_DEMAND_SFT 2
+#define DIS_DEMAND_HI 2
+#define DIS_DEMAND_SZ 1
+#define SAME_ID_ALLOC_MD_MSK 0x00000008
+#define SAME_ID_ALLOC_MD_I_MSK 0xfffffff7
+#define SAME_ID_ALLOC_MD_SFT 3
+#define SAME_ID_ALLOC_MD_HI 3
+#define SAME_ID_ALLOC_MD_SZ 1
+#define HS_ACCESS_MD_MSK 0x00000010
+#define HS_ACCESS_MD_I_MSK 0xffffffef
+#define HS_ACCESS_MD_SFT 4
+#define HS_ACCESS_MD_HI 4
+#define HS_ACCESS_MD_SZ 1
+#define SRAM_ACCESS_MD_MSK 0x00000020
+#define SRAM_ACCESS_MD_I_MSK 0xffffffdf
+#define SRAM_ACCESS_MD_SFT 5
+#define SRAM_ACCESS_MD_HI 5
+#define SRAM_ACCESS_MD_SZ 1
+#define NOHIT_RPASS_MD_MSK 0x00000040
+#define NOHIT_RPASS_MD_I_MSK 0xffffffbf
+#define NOHIT_RPASS_MD_SFT 6
+#define NOHIT_RPASS_MD_HI 6
+#define NOHIT_RPASS_MD_SZ 1
+#define DMN_FLAG_CLR_MSK 0x00000080
+#define DMN_FLAG_CLR_I_MSK 0xffffff7f
+#define DMN_FLAG_CLR_SFT 7
+#define DMN_FLAG_CLR_HI 7
+#define DMN_FLAG_CLR_SZ 1
+#define ERR_SW_RST_N_MSK 0x00000100
+#define ERR_SW_RST_N_I_MSK 0xfffffeff
+#define ERR_SW_RST_N_SFT 8
+#define ERR_SW_RST_N_HI 8
+#define ERR_SW_RST_N_SZ 1
+#define ALR_SW_RST_N_MSK 0x00000200
+#define ALR_SW_RST_N_I_MSK 0xfffffdff
+#define ALR_SW_RST_N_SFT 9
+#define ALR_SW_RST_N_HI 9
+#define ALR_SW_RST_N_SZ 1
+#define MCH_SW_RST_N_MSK 0x00000400
+#define MCH_SW_RST_N_I_MSK 0xfffffbff
+#define MCH_SW_RST_N_SFT 10
+#define MCH_SW_RST_N_HI 10
+#define MCH_SW_RST_N_SZ 1
+#define TAG_SW_RST_N_MSK 0x00000800
+#define TAG_SW_RST_N_I_MSK 0xfffff7ff
+#define TAG_SW_RST_N_SFT 11
+#define TAG_SW_RST_N_HI 11
+#define TAG_SW_RST_N_SZ 1
+#define ABT_SW_RST_N_MSK 0x00001000
+#define ABT_SW_RST_N_I_MSK 0xffffefff
+#define ABT_SW_RST_N_SFT 12
+#define ABT_SW_RST_N_HI 12
+#define ABT_SW_RST_N_SZ 1
+#define MMU_VER_MSK 0x0000e000
+#define MMU_VER_I_MSK 0xffff1fff
+#define MMU_VER_SFT 13
+#define MMU_VER_HI 15
+#define MMU_VER_SZ 3
+#define MMU_SHARE_MCU_MSK 0x00ff0000
+#define MMU_SHARE_MCU_I_MSK 0xff00ffff
+#define MMU_SHARE_MCU_SFT 16
+#define MMU_SHARE_MCU_HI 23
+#define MMU_SHARE_MCU_SZ 8
+#define HS_WR_MSK 0x00000001
+#define HS_WR_I_MSK 0xfffffffe
+#define HS_WR_SFT 0
+#define HS_WR_HI 0
+#define HS_WR_SZ 1
+#define HS_FLAG_MSK 0x00000010
+#define HS_FLAG_I_MSK 0xffffffef
+#define HS_FLAG_SFT 4
+#define HS_FLAG_HI 4
+#define HS_FLAG_SZ 1
+#define HS_ID_MSK 0x00007f00
+#define HS_ID_I_MSK 0xffff80ff
+#define HS_ID_SFT 8
+#define HS_ID_HI 14
+#define HS_ID_SZ 7
+#define HS_CHANNEL_MSK 0x000f0000
+#define HS_CHANNEL_I_MSK 0xfff0ffff
+#define HS_CHANNEL_SFT 16
+#define HS_CHANNEL_HI 19
+#define HS_CHANNEL_SZ 4
+#define HS_PAGE_MSK 0x00f00000
+#define HS_PAGE_I_MSK 0xff0fffff
+#define HS_PAGE_SFT 20
+#define HS_PAGE_HI 23
+#define HS_PAGE_SZ 4
+#define HS_DATA_MSK 0xff000000
+#define HS_DATA_I_MSK 0x00ffffff
+#define HS_DATA_SFT 24
+#define HS_DATA_HI 31
+#define HS_DATA_SZ 8
+#define CPU_POR0_MSK 0x0000000f
+#define CPU_POR0_I_MSK 0xfffffff0
+#define CPU_POR0_SFT 0
+#define CPU_POR0_HI 3
+#define CPU_POR0_SZ 4
+#define CPU_POR1_MSK 0x000000f0
+#define CPU_POR1_I_MSK 0xffffff0f
+#define CPU_POR1_SFT 4
+#define CPU_POR1_HI 7
+#define CPU_POR1_SZ 4
+#define CPU_POR2_MSK 0x00000f00
+#define CPU_POR2_I_MSK 0xfffff0ff
+#define CPU_POR2_SFT 8
+#define CPU_POR2_HI 11
+#define CPU_POR2_SZ 4
+#define CPU_POR3_MSK 0x0000f000
+#define CPU_POR3_I_MSK 0xffff0fff
+#define CPU_POR3_SFT 12
+#define CPU_POR3_HI 15
+#define CPU_POR3_SZ 4
+#define CPU_POR4_MSK 0x000f0000
+#define CPU_POR4_I_MSK 0xfff0ffff
+#define CPU_POR4_SFT 16
+#define CPU_POR4_HI 19
+#define CPU_POR4_SZ 4
+#define CPU_POR5_MSK 0x00f00000
+#define CPU_POR5_I_MSK 0xff0fffff
+#define CPU_POR5_SFT 20
+#define CPU_POR5_HI 23
+#define CPU_POR5_SZ 4
+#define CPU_POR6_MSK 0x0f000000
+#define CPU_POR6_I_MSK 0xf0ffffff
+#define CPU_POR6_SFT 24
+#define CPU_POR6_HI 27
+#define CPU_POR6_SZ 4
+#define CPU_POR7_MSK 0xf0000000
+#define CPU_POR7_I_MSK 0x0fffffff
+#define CPU_POR7_SFT 28
+#define CPU_POR7_HI 31
+#define CPU_POR7_SZ 4
+#define CPU_POR8_MSK 0x0000000f
+#define CPU_POR8_I_MSK 0xfffffff0
+#define CPU_POR8_SFT 0
+#define CPU_POR8_HI 3
+#define CPU_POR8_SZ 4
+#define CPU_POR9_MSK 0x000000f0
+#define CPU_POR9_I_MSK 0xffffff0f
+#define CPU_POR9_SFT 4
+#define CPU_POR9_HI 7
+#define CPU_POR9_SZ 4
+#define CPU_PORA_MSK 0x00000f00
+#define CPU_PORA_I_MSK 0xfffff0ff
+#define CPU_PORA_SFT 8
+#define CPU_PORA_HI 11
+#define CPU_PORA_SZ 4
+#define CPU_PORB_MSK 0x0000f000
+#define CPU_PORB_I_MSK 0xffff0fff
+#define CPU_PORB_SFT 12
+#define CPU_PORB_HI 15
+#define CPU_PORB_SZ 4
+#define CPU_PORC_MSK 0x000f0000
+#define CPU_PORC_I_MSK 0xfff0ffff
+#define CPU_PORC_SFT 16
+#define CPU_PORC_HI 19
+#define CPU_PORC_SZ 4
+#define CPU_PORD_MSK 0x00f00000
+#define CPU_PORD_I_MSK 0xff0fffff
+#define CPU_PORD_SFT 20
+#define CPU_PORD_HI 23
+#define CPU_PORD_SZ 4
+#define CPU_PORE_MSK 0x0f000000
+#define CPU_PORE_I_MSK 0xf0ffffff
+#define CPU_PORE_SFT 24
+#define CPU_PORE_HI 27
+#define CPU_PORE_SZ 4
+#define CPU_PORF_MSK 0xf0000000
+#define CPU_PORF_I_MSK 0x0fffffff
+#define CPU_PORF_SFT 28
+#define CPU_PORF_HI 31
+#define CPU_PORF_SZ 4
+#define ACC_WR_LEN_MSK 0x0000003f
+#define ACC_WR_LEN_I_MSK 0xffffffc0
+#define ACC_WR_LEN_SFT 0
+#define ACC_WR_LEN_HI 5
+#define ACC_WR_LEN_SZ 6
+#define ACC_RD_LEN_MSK 0x00003f00
+#define ACC_RD_LEN_I_MSK 0xffffc0ff
+#define ACC_RD_LEN_SFT 8
+#define ACC_RD_LEN_HI 13
+#define ACC_RD_LEN_SZ 6
+#define REQ_NACK_CLR_MSK 0x00008000
+#define REQ_NACK_CLR_I_MSK 0xffff7fff
+#define REQ_NACK_CLR_SFT 15
+#define REQ_NACK_CLR_HI 15
+#define REQ_NACK_CLR_SZ 1
+#define NACK_FLAG_BUS_MSK 0xffff0000
+#define NACK_FLAG_BUS_I_MSK 0x0000ffff
+#define NACK_FLAG_BUS_SFT 16
+#define NACK_FLAG_BUS_HI 31
+#define NACK_FLAG_BUS_SZ 16
+#define DMN_R_PASS_MSK 0x0000ffff
+#define DMN_R_PASS_I_MSK 0xffff0000
+#define DMN_R_PASS_SFT 0
+#define DMN_R_PASS_HI 15
+#define DMN_R_PASS_SZ 16
+#define PARA_ALC_RLS_MSK 0x00010000
+#define PARA_ALC_RLS_I_MSK 0xfffeffff
+#define PARA_ALC_RLS_SFT 16
+#define PARA_ALC_RLS_HI 16
+#define PARA_ALC_RLS_SZ 1
+#define REQ_PORNS_CHGEN_MSK 0x01000000
+#define REQ_PORNS_CHGEN_I_MSK 0xfeffffff
+#define REQ_PORNS_CHGEN_SFT 24
+#define REQ_PORNS_CHGEN_HI 24
+#define REQ_PORNS_CHGEN_SZ 1
+#define ALC_ABT_ID_MSK 0x0000007f
+#define ALC_ABT_ID_I_MSK 0xffffff80
+#define ALC_ABT_ID_SFT 0
+#define ALC_ABT_ID_HI 6
+#define ALC_ABT_ID_SZ 7
+#define ALC_ABT_INT_MSK 0x00008000
+#define ALC_ABT_INT_I_MSK 0xffff7fff
+#define ALC_ABT_INT_SFT 15
+#define ALC_ABT_INT_HI 15
+#define ALC_ABT_INT_SZ 1
+#define RLS_ABT_ID_MSK 0x007f0000
+#define RLS_ABT_ID_I_MSK 0xff80ffff
+#define RLS_ABT_ID_SFT 16
+#define RLS_ABT_ID_HI 22
+#define RLS_ABT_ID_SZ 7
+#define RLS_ABT_INT_MSK 0x80000000
+#define RLS_ABT_INT_I_MSK 0x7fffffff
+#define RLS_ABT_INT_SFT 31
+#define RLS_ABT_INT_HI 31
+#define RLS_ABT_INT_SZ 1
+#define DEBUG_CTL_MSK 0x000000ff
+#define DEBUG_CTL_I_MSK 0xffffff00
+#define DEBUG_CTL_SFT 0
+#define DEBUG_CTL_HI 7
+#define DEBUG_CTL_SZ 8
+#define DEBUG_H16_MSK 0x00000100
+#define DEBUG_H16_I_MSK 0xfffffeff
+#define DEBUG_H16_SFT 8
+#define DEBUG_H16_HI 8
+#define DEBUG_H16_SZ 1
+#define DEBUG_OUT_MSK 0xffffffff
+#define DEBUG_OUT_I_MSK 0x00000000
+#define DEBUG_OUT_SFT 0
+#define DEBUG_OUT_HI 31
+#define DEBUG_OUT_SZ 32
+#define ALC_ERR_MSK 0x00000001
+#define ALC_ERR_I_MSK 0xfffffffe
+#define ALC_ERR_SFT 0
+#define ALC_ERR_HI 0
+#define ALC_ERR_SZ 1
+#define RLS_ERR_MSK 0x00000002
+#define RLS_ERR_I_MSK 0xfffffffd
+#define RLS_ERR_SFT 1
+#define RLS_ERR_HI 1
+#define RLS_ERR_SZ 1
+#define AL_STATE_MSK 0x00000700
+#define AL_STATE_I_MSK 0xfffff8ff
+#define AL_STATE_SFT 8
+#define AL_STATE_HI 10
+#define AL_STATE_SZ 3
+#define RL_STATE_MSK 0x00007000
+#define RL_STATE_I_MSK 0xffff8fff
+#define RL_STATE_SFT 12
+#define RL_STATE_HI 14
+#define RL_STATE_SZ 3
+#define ALC_ERR_ID_MSK 0x007f0000
+#define ALC_ERR_ID_I_MSK 0xff80ffff
+#define ALC_ERR_ID_SFT 16
+#define ALC_ERR_ID_HI 22
+#define ALC_ERR_ID_SZ 7
+#define RLS_ERR_ID_MSK 0x7f000000
+#define RLS_ERR_ID_I_MSK 0x80ffffff
+#define RLS_ERR_ID_SFT 24
+#define RLS_ERR_ID_HI 30
+#define RLS_ERR_ID_SZ 7
+#define DMN_NOHIT_FLAG_MSK 0x00000001
+#define DMN_NOHIT_FLAG_I_MSK 0xfffffffe
+#define DMN_NOHIT_FLAG_SFT 0
+#define DMN_NOHIT_FLAG_HI 0
+#define DMN_NOHIT_FLAG_SZ 1
+#define DMN_FLAG_MSK 0x00000002
+#define DMN_FLAG_I_MSK 0xfffffffd
+#define DMN_FLAG_SFT 1
+#define DMN_FLAG_HI 1
+#define DMN_FLAG_SZ 1
+#define DMN_WR_MSK 0x00000008
+#define DMN_WR_I_MSK 0xfffffff7
+#define DMN_WR_SFT 3
+#define DMN_WR_HI 3
+#define DMN_WR_SZ 1
+#define DMN_PORT_MSK 0x000000f0
+#define DMN_PORT_I_MSK 0xffffff0f
+#define DMN_PORT_SFT 4
+#define DMN_PORT_HI 7
+#define DMN_PORT_SZ 4
+#define DMN_NHIT_ID_MSK 0x00007f00
+#define DMN_NHIT_ID_I_MSK 0xffff80ff
+#define DMN_NHIT_ID_SFT 8
+#define DMN_NHIT_ID_HI 14
+#define DMN_NHIT_ID_SZ 7
+#define DMN_NHIT_ADDR_MSK 0xffff0000
+#define DMN_NHIT_ADDR_I_MSK 0x0000ffff
+#define DMN_NHIT_ADDR_SFT 16
+#define DMN_NHIT_ADDR_HI 31
+#define DMN_NHIT_ADDR_SZ 16
+#define TX_MOUNT_MSK 0x000000ff
+#define TX_MOUNT_I_MSK 0xffffff00
+#define TX_MOUNT_SFT 0
+#define TX_MOUNT_HI 7
+#define TX_MOUNT_SZ 8
+#define RX_MOUNT_MSK 0x0000ff00
+#define RX_MOUNT_I_MSK 0xffff00ff
+#define RX_MOUNT_SFT 8
+#define RX_MOUNT_HI 15
+#define RX_MOUNT_SZ 8
+#define AVA_TAG_MSK 0x01ff0000
+#define AVA_TAG_I_MSK 0xfe00ffff
+#define AVA_TAG_SFT 16
+#define AVA_TAG_HI 24
+#define AVA_TAG_SZ 9
+#define PKTBUF_FULL_MSK 0x80000000
+#define PKTBUF_FULL_I_MSK 0x7fffffff
+#define PKTBUF_FULL_SFT 31
+#define PKTBUF_FULL_HI 31
+#define PKTBUF_FULL_SZ 1
+#define DMN_NOHIT_MCU_MSK 0x00000001
+#define DMN_NOHIT_MCU_I_MSK 0xfffffffe
+#define DMN_NOHIT_MCU_SFT 0
+#define DMN_NOHIT_MCU_HI 0
+#define DMN_NOHIT_MCU_SZ 1
+#define DMN_MCU_FLAG_MSK 0x00000002
+#define DMN_MCU_FLAG_I_MSK 0xfffffffd
+#define DMN_MCU_FLAG_SFT 1
+#define DMN_MCU_FLAG_HI 1
+#define DMN_MCU_FLAG_SZ 1
+#define DMN_MCU_WR_MSK 0x00000008
+#define DMN_MCU_WR_I_MSK 0xfffffff7
+#define DMN_MCU_WR_SFT 3
+#define DMN_MCU_WR_HI 3
+#define DMN_MCU_WR_SZ 1
+#define DMN_MCU_PORT_MSK 0x000000f0
+#define DMN_MCU_PORT_I_MSK 0xffffff0f
+#define DMN_MCU_PORT_SFT 4
+#define DMN_MCU_PORT_HI 7
+#define DMN_MCU_PORT_SZ 4
+#define DMN_MCU_ID_MSK 0x00007f00
+#define DMN_MCU_ID_I_MSK 0xffff80ff
+#define DMN_MCU_ID_SFT 8
+#define DMN_MCU_ID_HI 14
+#define DMN_MCU_ID_SZ 7
+#define DMN_MCU_ADDR_MSK 0xffff0000
+#define DMN_MCU_ADDR_I_MSK 0x0000ffff
+#define DMN_MCU_ADDR_SFT 16
+#define DMN_MCU_ADDR_HI 31
+#define DMN_MCU_ADDR_SZ 16
+#define MB_IDTBL_31_0_MSK 0xffffffff
+#define MB_IDTBL_31_0_I_MSK 0x00000000
+#define MB_IDTBL_31_0_SFT 0
+#define MB_IDTBL_31_0_HI 31
+#define MB_IDTBL_31_0_SZ 32
+#define MB_IDTBL_63_32_MSK 0xffffffff
+#define MB_IDTBL_63_32_I_MSK 0x00000000
+#define MB_IDTBL_63_32_SFT 0
+#define MB_IDTBL_63_32_HI 31
+#define MB_IDTBL_63_32_SZ 32
+#define MB_IDTBL_95_64_MSK 0xffffffff
+#define MB_IDTBL_95_64_I_MSK 0x00000000
+#define MB_IDTBL_95_64_SFT 0
+#define MB_IDTBL_95_64_HI 31
+#define MB_IDTBL_95_64_SZ 32
+#define MB_IDTBL_127_96_MSK 0xffffffff
+#define MB_IDTBL_127_96_I_MSK 0x00000000
+#define MB_IDTBL_127_96_SFT 0
+#define MB_IDTBL_127_96_HI 31
+#define MB_IDTBL_127_96_SZ 32
+#define PKT_IDTBL_31_0_MSK 0xffffffff
+#define PKT_IDTBL_31_0_I_MSK 0x00000000
+#define PKT_IDTBL_31_0_SFT 0
+#define PKT_IDTBL_31_0_HI 31
+#define PKT_IDTBL_31_0_SZ 32
+#define PKT_IDTBL_63_32_MSK 0xffffffff
+#define PKT_IDTBL_63_32_I_MSK 0x00000000
+#define PKT_IDTBL_63_32_SFT 0
+#define PKT_IDTBL_63_32_HI 31
+#define PKT_IDTBL_63_32_SZ 32
+#define PKT_IDTBL_95_64_MSK 0xffffffff
+#define PKT_IDTBL_95_64_I_MSK 0x00000000
+#define PKT_IDTBL_95_64_SFT 0
+#define PKT_IDTBL_95_64_HI 31
+#define PKT_IDTBL_95_64_SZ 32
+#define PKT_IDTBL_127_96_MSK 0xffffffff
+#define PKT_IDTBL_127_96_I_MSK 0x00000000
+#define PKT_IDTBL_127_96_SFT 0
+#define PKT_IDTBL_127_96_HI 31
+#define PKT_IDTBL_127_96_SZ 32
+#define DMN_IDTBL_31_0_MSK 0xffffffff
+#define DMN_IDTBL_31_0_I_MSK 0x00000000
+#define DMN_IDTBL_31_0_SFT 0
+#define DMN_IDTBL_31_0_HI 31
+#define DMN_IDTBL_31_0_SZ 32
+#define DMN_IDTBL_63_32_MSK 0xffffffff
+#define DMN_IDTBL_63_32_I_MSK 0x00000000
+#define DMN_IDTBL_63_32_SFT 0
+#define DMN_IDTBL_63_32_HI 31
+#define DMN_IDTBL_63_32_SZ 32
+#define DMN_IDTBL_95_64_MSK 0xffffffff
+#define DMN_IDTBL_95_64_I_MSK 0x00000000
+#define DMN_IDTBL_95_64_SFT 0
+#define DMN_IDTBL_95_64_HI 31
+#define DMN_IDTBL_95_64_SZ 32
+#define DMN_IDTBL_127_96_MSK 0xffffffff
+#define DMN_IDTBL_127_96_I_MSK 0x00000000
+#define DMN_IDTBL_127_96_SFT 0
+#define DMN_IDTBL_127_96_HI 31
+#define DMN_IDTBL_127_96_SZ 32
+#define NEQ_MB_ID_31_0_MSK 0xffffffff
+#define NEQ_MB_ID_31_0_I_MSK 0x00000000
+#define NEQ_MB_ID_31_0_SFT 0
+#define NEQ_MB_ID_31_0_HI 31
+#define NEQ_MB_ID_31_0_SZ 32
+#define NEQ_MB_ID_63_32_MSK 0xffffffff
+#define NEQ_MB_ID_63_32_I_MSK 0x00000000
+#define NEQ_MB_ID_63_32_SFT 0
+#define NEQ_MB_ID_63_32_HI 31
+#define NEQ_MB_ID_63_32_SZ 32
+#define NEQ_MB_ID_95_64_MSK 0xffffffff
+#define NEQ_MB_ID_95_64_I_MSK 0x00000000
+#define NEQ_MB_ID_95_64_SFT 0
+#define NEQ_MB_ID_95_64_HI 31
+#define NEQ_MB_ID_95_64_SZ 32
+#define NEQ_MB_ID_127_96_MSK 0xffffffff
+#define NEQ_MB_ID_127_96_I_MSK 0x00000000
+#define NEQ_MB_ID_127_96_SFT 0
+#define NEQ_MB_ID_127_96_HI 31
+#define NEQ_MB_ID_127_96_SZ 32
+#define NEQ_PKT_ID_31_0_MSK 0xffffffff
+#define NEQ_PKT_ID_31_0_I_MSK 0x00000000
+#define NEQ_PKT_ID_31_0_SFT 0
+#define NEQ_PKT_ID_31_0_HI 31
+#define NEQ_PKT_ID_31_0_SZ 32
+#define NEQ_PKT_ID_63_32_MSK 0xffffffff
+#define NEQ_PKT_ID_63_32_I_MSK 0x00000000
+#define NEQ_PKT_ID_63_32_SFT 0
+#define NEQ_PKT_ID_63_32_HI 31
+#define NEQ_PKT_ID_63_32_SZ 32
+#define NEQ_PKT_ID_95_64_MSK 0xffffffff
+#define NEQ_PKT_ID_95_64_I_MSK 0x00000000
+#define NEQ_PKT_ID_95_64_SFT 0
+#define NEQ_PKT_ID_95_64_HI 31
+#define NEQ_PKT_ID_95_64_SZ 32
+#define NEQ_PKT_ID_127_96_MSK 0xffffffff
+#define NEQ_PKT_ID_127_96_I_MSK 0x00000000
+#define NEQ_PKT_ID_127_96_SFT 0
+#define NEQ_PKT_ID_127_96_HI 31
+#define NEQ_PKT_ID_127_96_SZ 32
+#define ALC_NOCHG_ID_MSK 0x0000007f
+#define ALC_NOCHG_ID_I_MSK 0xffffff80
+#define ALC_NOCHG_ID_SFT 0
+#define ALC_NOCHG_ID_HI 6
+#define ALC_NOCHG_ID_SZ 7
+#define ALC_NOCHG_INT_MSK 0x00008000
+#define ALC_NOCHG_INT_I_MSK 0xffff7fff
+#define ALC_NOCHG_INT_SFT 15
+#define ALC_NOCHG_INT_HI 15
+#define ALC_NOCHG_INT_SZ 1
+#define NEQ_PKT_FLAG_MSK 0x00010000
+#define NEQ_PKT_FLAG_I_MSK 0xfffeffff
+#define NEQ_PKT_FLAG_SFT 16
+#define NEQ_PKT_FLAG_HI 16
+#define NEQ_PKT_FLAG_SZ 1
+#define NEQ_MB_FLAG_MSK 0x01000000
+#define NEQ_MB_FLAG_I_MSK 0xfeffffff
+#define NEQ_MB_FLAG_SFT 24
+#define NEQ_MB_FLAG_HI 24
+#define NEQ_MB_FLAG_SZ 1
+#define SRAM_TAG_0_MSK 0x0000ffff
+#define SRAM_TAG_0_I_MSK 0xffff0000
+#define SRAM_TAG_0_SFT 0
+#define SRAM_TAG_0_HI 15
+#define SRAM_TAG_0_SZ 16
+#define SRAM_TAG_1_MSK 0xffff0000
+#define SRAM_TAG_1_I_MSK 0x0000ffff
+#define SRAM_TAG_1_SFT 16
+#define SRAM_TAG_1_HI 31
+#define SRAM_TAG_1_SZ 16
+#define SRAM_TAG_2_MSK 0x0000ffff
+#define SRAM_TAG_2_I_MSK 0xffff0000
+#define SRAM_TAG_2_SFT 0
+#define SRAM_TAG_2_HI 15
+#define SRAM_TAG_2_SZ 16
+#define SRAM_TAG_3_MSK 0xffff0000
+#define SRAM_TAG_3_I_MSK 0x0000ffff
+#define SRAM_TAG_3_SFT 16
+#define SRAM_TAG_3_HI 31
+#define SRAM_TAG_3_SZ 16
+#define SRAM_TAG_4_MSK 0x0000ffff
+#define SRAM_TAG_4_I_MSK 0xffff0000
+#define SRAM_TAG_4_SFT 0
+#define SRAM_TAG_4_HI 15
+#define SRAM_TAG_4_SZ 16
+#define SRAM_TAG_5_MSK 0xffff0000
+#define SRAM_TAG_5_I_MSK 0x0000ffff
+#define SRAM_TAG_5_SFT 16
+#define SRAM_TAG_5_HI 31
+#define SRAM_TAG_5_SZ 16
+#define SRAM_TAG_6_MSK 0x0000ffff
+#define SRAM_TAG_6_I_MSK 0xffff0000
+#define SRAM_TAG_6_SFT 0
+#define SRAM_TAG_6_HI 15
+#define SRAM_TAG_6_SZ 16
+#define SRAM_TAG_7_MSK 0xffff0000
+#define SRAM_TAG_7_I_MSK 0x0000ffff
+#define SRAM_TAG_7_SFT 16
+#define SRAM_TAG_7_HI 31
+#define SRAM_TAG_7_SZ 16
+#define SRAM_TAG_8_MSK 0x0000ffff
+#define SRAM_TAG_8_I_MSK 0xffff0000
+#define SRAM_TAG_8_SFT 0
+#define SRAM_TAG_8_HI 15
+#define SRAM_TAG_8_SZ 16
+#define SRAM_TAG_9_MSK 0xffff0000
+#define SRAM_TAG_9_I_MSK 0x0000ffff
+#define SRAM_TAG_9_SFT 16
+#define SRAM_TAG_9_HI 31
+#define SRAM_TAG_9_SZ 16
+#define SRAM_TAG_10_MSK 0x0000ffff
+#define SRAM_TAG_10_I_MSK 0xffff0000
+#define SRAM_TAG_10_SFT 0
+#define SRAM_TAG_10_HI 15
+#define SRAM_TAG_10_SZ 16
+#define SRAM_TAG_11_MSK 0xffff0000
+#define SRAM_TAG_11_I_MSK 0x0000ffff
+#define SRAM_TAG_11_SFT 16
+#define SRAM_TAG_11_HI 31
+#define SRAM_TAG_11_SZ 16
+#define SRAM_TAG_12_MSK 0x0000ffff
+#define SRAM_TAG_12_I_MSK 0xffff0000
+#define SRAM_TAG_12_SFT 0
+#define SRAM_TAG_12_HI 15
+#define SRAM_TAG_12_SZ 16
+#define SRAM_TAG_13_MSK 0xffff0000
+#define SRAM_TAG_13_I_MSK 0x0000ffff
+#define SRAM_TAG_13_SFT 16
+#define SRAM_TAG_13_HI 31
+#define SRAM_TAG_13_SZ 16
+#define SRAM_TAG_14_MSK 0x0000ffff
+#define SRAM_TAG_14_I_MSK 0xffff0000
+#define SRAM_TAG_14_SFT 0
+#define SRAM_TAG_14_HI 15
+#define SRAM_TAG_14_SZ 16
+#define SRAM_TAG_15_MSK 0xffff0000
+#define SRAM_TAG_15_I_MSK 0x0000ffff
+#define SRAM_TAG_15_SFT 16
+#define SRAM_TAG_15_HI 31
+#define SRAM_TAG_15_SZ 16
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_common.h b/drivers/net/wireless/ssv6051/include/ssv6200_common.h
new file mode 100644
index 00000000000..e6d30f3714f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200_common.h
@@ -0,0 +1,452 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV6200_COMMON_H_
+#define _SSV6200_COMMON_H_
+#define FW_VERSION_REG ADR_TX_SEG
+#define M_ENG_CPU 0x00
+#define M_ENG_HWHCI 0x01
+#define M_ENG_EMPTY 0x02
+#define M_ENG_ENCRYPT 0x03
+#define M_ENG_MACRX 0x04
+#define M_ENG_MIC 0x05
+#define M_ENG_TX_EDCA0 0x06
+#define M_ENG_TX_EDCA1 0x07
+#define M_ENG_TX_EDCA2 0x08
+#define M_ENG_TX_EDCA3 0x09
+#define M_ENG_TX_MNG 0x0A
+#define M_ENG_ENCRYPT_SEC 0x0B
+#define M_ENG_MIC_SEC 0x0C
+#define M_ENG_RESERVED_1 0x0D
+#define M_ENG_RESERVED_2 0x0E
+#define M_ENG_TRASH_CAN 0x0F
+#define M_ENG_MAX (M_ENG_TRASH_CAN+1)
+#define M_CPU_HWENG 0x00
+#define M_CPU_TXL34CS 0x01
+#define M_CPU_RXL34CS 0x02
+#define M_CPU_DEFRAG 0x03
+#define M_CPU_EDCATX 0x04
+#define M_CPU_RXDATA 0x05
+#define M_CPU_RXMGMT 0x06
+#define M_CPU_RXCTRL 0x07
+#define M_CPU_FRAG 0x08
+#define M_CPU_TXTPUT 0x09
+#ifndef ID_TRAP_SW_TXTPUT
+#define ID_TRAP_SW_TXTPUT 50
+#endif
+#define M0_TXREQ 0
+#define M1_TXREQ 1
+#define M2_TXREQ 2
+#define M0_RXEVENT 3
+#define M2_RXEVENT 4
+#define HOST_CMD 5
+#define HOST_EVENT 6
+#define TEST_CMD 7
+#define SSV6XXX_RX_DESC_LEN \
+        (sizeof(struct ssv6200_rx_desc) + \
+         sizeof(struct ssv6200_rxphy_info))
+#define SSV6XXX_TX_DESC_LEN \
+        (sizeof(struct ssv6200_tx_desc) + 0)
+#define TXPB_OFFSET 80
+#define RXPB_OFFSET 80
+#define SSV6200_TX_PKT_RSVD_SETTING 0x3
+#define SSV6200_TX_PKT_RSVD SSV6200_TX_PKT_RSVD_SETTING*16
+#define SSV6200_ALLOC_RSVD TXPB_OFFSET+SSV6200_TX_PKT_RSVD
+#define SSV62XX_TX_MAX_RATES 3
+
+enum ssv6xxx_sr_bhvr {
+	SUSPEND_RESUME_0,
+	SUSPEND_RESUME_1,
+	SUSPEND_RESUME_MAX
+};
+
+enum ssv6xxx_reboot_bhvr {
+	SSV_SYS_REBOOT = 1,
+	SSV_SYS_HALF,
+	SSV_SYS_POWER_OFF
+};
+
+struct fw_rc_retry_params {
+	u32 count:4;
+	u32 drate:6;
+	u32 crate:6;
+	u32 rts_cts_nav:16;
+	u32 frame_consume_time:10;
+	u32 dl_length:12;
+	u32 RSVD:10;
+} __attribute__((packed));
+struct ssv6200_tx_desc {
+	u32 len:16;
+	u32 c_type:3;
+	u32 f80211:1;
+	u32 qos:1;
+	u32 ht:1;
+	u32 use_4addr:1;
+	u32 RSVD_0:3;
+	u32 bc_que:1;
+	u32 security:1;
+	u32 more_data:1;
+	u32 stype_b5b4:2;
+	u32 extra_info:1;
+	u32 fCmd;
+	u32 hdr_offset:8;
+	u32 frag:1;
+	u32 unicast:1;
+	u32 hdr_len:6;
+	u32 tx_report:1;
+	u32 tx_burst:1;
+	u32 ack_policy:2;
+	u32 aggregation:1;
+	u32 RSVD_1:3;
+	u32 do_rts_cts:2;
+	u32 reason:6;
+	u32 payload_offset:8;
+	u32 RSVD_4:7;
+	u32 RSVD_2:1;
+	u32 fCmdIdx:3;
+	u32 wsid:4;
+	u32 txq_idx:3;
+	u32 TxF_ID:6;
+	u32 rts_cts_nav:16;
+	u32 frame_consume_time:10;
+	u32 crate_idx:6;
+	u32 drate_idx:6;
+	u32 dl_length:12;
+	u32 RSVD_3:14;
+	u32 RESERVED[8];
+	struct fw_rc_retry_params rc_params[SSV62XX_TX_MAX_RATES];
+};
+struct ssv6200_rx_desc {
+	u32 len:16;
+	u32 c_type:3;
+	u32 f80211:1;
+	u32 qos:1;
+	u32 ht:1;
+	u32 use_4addr:1;
+	u32 l3cs_err:1;
+	u32 l4cs_err:1;
+	u32 align2:1;
+	u32 RSVD_0:2;
+	u32 psm:1;
+	u32 stype_b5b4:2;
+	u32 extra_info:1;
+	u32 edca0_used:4;
+	u32 edca1_used:5;
+	u32 edca2_used:5;
+	u32 edca3_used:5;
+	u32 mng_used:4;
+	u32 tx_page_used:9;
+	u32 hdr_offset:8;
+	u32 frag:1;
+	u32 unicast:1;
+	u32 hdr_len:6;
+	u32 RxResult:8;
+	u32 wildcard_bssid:1;
+	u32 RSVD_1:1;
+	u32 reason:6;
+	u32 payload_offset:8;
+	u32 tx_id_used:8;
+	u32 fCmdIdx:3;
+	u32 wsid:4;
+	u32 RSVD_3:3;
+	u32 rate_idx:6;
+};
+struct ssv6200_rxphy_info {
+	u32 len:16;
+	u32 rsvd0:16;
+	u32 mode:3;
+	u32 ch_bw:3;
+	u32 preamble:1;
+	u32 ht_short_gi:1;
+	u32 rate:7;
+	u32 rsvd1:1;
+	u32 smoothing:1;
+	u32 no_sounding:1;
+	u32 aggregate:1;
+	u32 stbc:2;
+	u32 fec:1;
+	u32 n_ess:2;
+	u32 rsvd2:8;
+	u32 l_length:12;
+	u32 l_rate:3;
+	u32 rsvd3:17;
+	u32 rsvd4;
+	u32 rpci:8;
+	u32 snr:8;
+	u32 service:16;
+};
+struct ssv6200_rxphy_info_padding {
+	u32 rpci:8;
+	u32 snr:8;
+	u32 RSVD:16;
+};
+struct ssv6200_txphy_info {
+	u32 rsvd[7];
+};
+#ifdef CONFIG_P2P_NOA
+struct ssv6xxx_p2p_noa_param {
+	u32 duration;
+	u32 interval;
+	u32 start_time;
+	u32 enable:8;
+	u32 count:8;
+	u8 addr[6];
+	u8 vif_id;
+} __attribute__((packed));
+#endif
+typedef struct cfg_host_cmd {
+	u32 len:16;
+	u32 c_type:3;
+	u32 RSVD0:5;
+	u32 h_cmd:8;
+	u32 cmd_seq_no;
+	union {
+		u32 dummy;
+		u8 dat8[0];
+		u16 dat16[0];
+		u32 dat32[0];
+	};
+} HDR_HostCmd;
+#define HOST_CMD_HDR_LEN ((size_t)(((HDR_HostCmd *)100)->dat8)-100U)
+struct sdio_rxtput_cfg {
+	u32 size_per_frame;
+	u32 total_frames;
+};
+typedef enum {
+	SSV6XXX_HOST_CMD_START = 0,
+	SSV6XXX_HOST_CMD_LOG,
+	SSV6XXX_HOST_CMD_PS,
+	SSV6XXX_HOST_CMD_INIT_CALI,
+	SSV6XXX_HOST_CMD_RX_TPUT,
+	SSV6XXX_HOST_CMD_TX_TPUT,
+	SSV6XXX_HOST_CMD_WATCHDOG_START,
+	SSV6XXX_HOST_CMD_WATCHDOG_STOP,
+	SSV6XXX_HOST_CMD_WSID_OP,
+#ifdef CONFIG_P2P_NOA
+	SSV6XXX_HOST_CMD_SET_NOA,
+#endif
+	SSV6XXX_HOST_SOC_CMD_MAXID,
+} ssv6xxx_host_cmd_id;
+#define SSV_NUM_HW_STA 2
+typedef struct cfg_host_event {
+	u32 len:16;
+	u32 c_type:3;
+	u32 RSVD0:5;
+	u32 h_event:8;
+	u32 evt_seq_no;
+	u8 dat[0];
+} HDR_HostEvent;
+typedef enum {
+#ifdef USE_CMD_RESP
+	SOC_EVT_CMD_RESP,
+	SOC_EVT_SCAN_RESULT,
+	SOC_EVT_DEAUTH,
+#else
+	SOC_EVT_GET_REG_RESP,
+#endif
+	SOC_EVT_NO_BA,
+	SOC_EVT_RC_MPDU_REPORT,
+	SOC_EVT_RC_AMPDU_REPORT,
+	SOC_EVT_LOG,
+#ifdef CONFIG_P2P_NOA
+	SOC_EVT_NOA,
+#endif
+	SOC_EVT_USER_END,
+	SOC_EVT_SDIO_TEST_COMMAND,
+	SOC_EVT_RESET_HOST,
+	SOC_EVT_SDIO_TXTPUT_RESULT,
+	SOC_EVT_WATCHDOG_TRIGGER,
+	SOC_EVT_TXLOOPBK_RESULT,
+	SOC_EVT_MAXID,
+} ssv6xxx_soc_event;
+#ifdef CONFIG_P2P_NOA
+typedef enum {
+	SSV6XXX_NOA_START = 0,
+	SSV6XXX_NOA_STOP,
+} ssv6xxx_host_noa_event;
+struct ssv62xx_noa_evt {
+	u8 evt_id;
+	u8 vif;
+} __attribute__((packed));
+#endif
+typedef enum {
+	SSV6XXX_RC_COUNTER_CLEAR = 1,
+	SSV6XXX_RC_REPORT,
+} ssv6xxx_host_rate_control_event;
+#define MAX_AGGR_NUM (24)
+struct ssv62xx_tx_rate {
+	s8 data_rate;
+	u8 count;
+} __attribute__((packed));
+struct ampdu_ba_notify_data {
+	u8 wsid;
+	struct ssv62xx_tx_rate tried_rates[SSV62XX_TX_MAX_RATES];
+	u16 seq_no[MAX_AGGR_NUM];
+} __attribute__((packed));
+struct firmware_rate_control_report_data {
+	u8 wsid;
+	struct ssv62xx_tx_rate rates[SSV62XX_TX_MAX_RATES];
+	u16 ampdu_len;
+	u16 ampdu_ack_len;
+	int ack_signal;
+} __attribute__((packed));
+#define RC_RETRY_PARAM_OFFSET ((sizeof(struct fw_rc_retry_params))*SSV62XX_TX_MAX_RATES)
+#define SSV_RC_RATE_MAX 39
+enum SSV6XXX_WSID_OPS {
+	SSV6XXX_WSID_OPS_ADD,
+	SSV6XXX_WSID_OPS_DEL,
+	SSV6XXX_WSID_OPS_RESETALL,
+	SSV6XXX_WSID_OPS_ENABLE_CAPS,
+	SSV6XXX_WSID_OPS_DISABLE_CAPS,
+	SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE,
+	SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE,
+	SSV6XXX_WSID_OPS_MAX
+};
+enum SSV6XXX_WSID_SEC {
+	SSV6XXX_WSID_SEC_NONE = 0,
+	SSV6XXX_WSID_SEC_PAIRWISE = 1 << 0,
+	SSV6XXX_WSID_SEC_GROUP = 1 << 1,
+};
+enum SSV6XXX_WSID_SEC_TYPE {
+	SSV6XXX_WSID_SEC_SW,
+	SSV6XXX_WSID_SEC_HW,
+	SSV6XXX_WSID_SEC_TYPE_MAX
+};
+enum SSV6XXX_RETURN_STATE {
+	SSV6XXX_STATE_OK,
+	SSV6XXX_STATE_NG,
+	SSV6XXX_STATE_MAX
+};
+struct ssv6xxx_wsid_params {
+	u8 cmd;
+	u8 wsid_idx;
+	u8 target_wsid[6];
+	u8 hw_security;
+};
+struct ssv6xxx_iqk_cfg {
+	u32 cfg_xtal:8;
+	u32 cfg_pa:8;
+	u32 cfg_pabias_ctrl:8;
+	u32 cfg_pacascode_ctrl:8;
+	u32 cfg_tssi_trgt:8;
+	u32 cfg_tssi_div:8;
+	u32 cfg_def_tx_scale_11b:8;
+	u32 cfg_def_tx_scale_11b_p0d5:8;
+	u32 cfg_def_tx_scale_11g:8;
+	u32 cfg_def_tx_scale_11g_p0d5:8;
+	u32 cmd_sel;
+	union {
+		u32 fx_sel;
+		u32 argv;
+	};
+	u32 phy_tbl_size;
+	u32 rf_tbl_size;
+};
+#define PHY_SETTING_SIZE sizeof(phy_setting)
+struct ssv6xxx_ch_cfg {
+	u32 reg_addr;
+	u32 ch1_12_value;
+	u32 ch13_14_value;
+};
+#define IQK_CFG_LEN (sizeof(struct ssv6xxx_iqk_cfg))
+#define RF_SETTING_SIZE (sizeof(asic_rf_setting))
+#define MAX_PHY_SETTING_TABLE_SIZE 1920
+#define MAX_RF_SETTING_TABLE_SIZE 512
+typedef enum {
+	SSV6XXX_VOLT_DCDC_CONVERT = 0,
+	SSV6XXX_VOLT_LDO_CONVERT,
+} ssv6xxx_cfg_volt;
+typedef enum {
+	SSV6XXX_VOLT_33V = 0,
+	SSV6XXX_VOLT_42V,
+} ssv6xxx_cfg_volt_value;
+typedef enum {
+	SSV6XXX_IQK_CFG_XTAL_26M = 0,
+	SSV6XXX_IQK_CFG_XTAL_40M,
+	SSV6XXX_IQK_CFG_XTAL_24M,
+	SSV6XXX_IQK_CFG_XTAL_MAX,
+} ssv6xxx_iqk_cfg_xtal;
+typedef enum {
+	SSV6XXX_IQK_CFG_PA_DEF = 0,
+	SSV6XXX_IQK_CFG_PA_LI_MPB,
+	SSV6XXX_IQK_CFG_PA_LI_EVB,
+	SSV6XXX_IQK_CFG_PA_HP,
+} ssv6xxx_iqk_cfg_pa;
+typedef enum {
+	SSV6XXX_IQK_CMD_INIT_CALI = 0,
+	SSV6XXX_IQK_CMD_RTBL_LOAD,
+	SSV6XXX_IQK_CMD_RTBL_LOAD_DEF,
+	SSV6XXX_IQK_CMD_RTBL_RESET,
+	SSV6XXX_IQK_CMD_RTBL_SET,
+	SSV6XXX_IQK_CMD_RTBL_EXPORT,
+	SSV6XXX_IQK_CMD_TK_EVM,
+	SSV6XXX_IQK_CMD_TK_TONE,
+	SSV6XXX_IQK_CMD_TK_CHCH,
+} ssv6xxx_iqk_cmd_sel;
+#define SSV6XXX_IQK_TEMPERATURE 0x00000004
+#define SSV6XXX_IQK_RXDC 0x00000008
+#define SSV6XXX_IQK_RXRC 0x00000010
+#define SSV6XXX_IQK_TXDC 0x00000020
+#define SSV6XXX_IQK_TXIQ 0x00000040
+#define SSV6XXX_IQK_RXIQ 0x00000080
+#define SSV6XXX_IQK_TSSI 0x00000100
+#define SSV6XXX_IQK_PAPD 0x00000200
+typedef struct ssv_cabrio_reg_st {
+	u32 address;
+	u32 data;
+} ssv_cabrio_reg;
+typedef enum __PBuf_Type_E {
+	NOTYPE_BUF = 0,
+	TX_BUF = 1,
+	RX_BUF = 2
+} PBuf_Type_E;
+struct SKB_info_st {
+	struct ieee80211_sta *sta;
+	u16 mpdu_retry_counter;
+	unsigned long aggr_timestamp;
+	u16 ampdu_tx_status;
+	u16 ampdu_tx_final_retry_count;
+	u16 lowest_rate;
+	struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+	ktime_t timestamp;
+#endif
+};
+typedef struct SKB_info_st SKB_info;
+typedef struct SKB_info_st *p_SKB_info;
+#define SSV_SKB_info_size (sizeof(struct SKB_info_st))
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+#define SKB_DURATION_TIMEOUT_MS 100
+enum ssv_debug_skb_timestamp {
+	SKB_DURATION_STAGE_TX_ENQ,
+	SKB_DURATION_STAGE_TO_SDIO,
+	SKB_DURATION_STAGE_IN_HWQ,
+	SKB_DURATION_STAGE_END
+};
+#endif
+#define SSV6051Q_P1 0x00000000
+#define SSV6051Q_P2 0x70000000
+#define SSV6051Z 0x71000000
+#define SSV6051Q 0x73000000
+#define SSV6051P 0x75000000
+struct ssv6xxx_tx_loopback {
+	u32 reg;
+	u32 val;
+	u32 restore_val;
+	u8 restore;
+	u8 delay_ms;
+};
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h b/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
new file mode 100644
index 00000000000..0327393de3f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200_configuration.h
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static ssv_cabrio_reg phy_setting[] = {
+	{0xce0071bc, 0x565B565B},
+	{0xce000008, 0x0000006a},
+	{0xce00000c, 0x00000064},
+	{0xce000010, 0x00007FFF},
+	{0xce000014, 0x00000003},
+	{0xce000018, 0x0055003C},
+	{0xce00001c, 0x00000064},
+	{0xce000020, 0x20000000},
+	{0xce00002c, 0x00000000},
+	{0xce000030, 0x80046072},
+	{0xce000034, 0x1f300f6f},
+	{0xce000038, 0x660F36D0},
+	{0xce00003c, 0x106C0004},
+	{0xce000040, 0x01601400},
+	{0xce000044, 0x00600008},
+	{0xce000048, 0xff000160},
+	{0xce00004c, 0x00000840},
+	{0xce000060, 0x01000405},
+	{0xce000064, 0x06090813},
+	{0xce000068, 0x12070000},
+	{0xce00006c, 0x01000405},
+	{0xce000070, 0x06090813},
+	{0xce000074, 0x12010000},
+	{0xce000078, 0x00000000},
+	{0xce00007c, 0x10110003},
+	{0xce000080, 0x0110000F},
+	{0xce000084, 0x00000000},
+	{0xce000088, 0x00000000},
+	{0xce000094, 0x01012425},
+	{0xce000098, 0x01010101},
+	{0xce00009c, 0x00000011},
+	{0xce0000a0, 0x1fff0000},
+	{0xce0000a4, 0x1fff0000},
+	{0xce0000a8, 0x1fff0000},
+	{0xce0000ac, 0x1fff0000},
+	{0xce0000b8, 0x0000fe3e},
+	{0xce0000fc, 0xffffffff},
+	{0xce000108, 0x0ead04f5},
+	{0xce00010c, 0x0fd60080},
+	{0xce000110, 0x00000009},
+	{0xce0010a4, 0x0000002c},
+	{0xce0010b4, 0x00003001},
+	{0xce0010d4, 0x00000001},
+	{0xce002000, 0x00000044},
+	{0xce002004, 0x00040000},
+	{0xce002008, 0x20300050},
+	{0xce00200c, 0x00003467},
+	{0xce002010, 0x00430000},
+	{0xce002014, 0x20304015},
+	{0xce002018, 0x00390005},
+	{0xce00201c, 0x05555555},
+	{0xce002020, 0x00570057},
+	{0xce002024, 0x00570057},
+	{0xce002028, 0x00236700},
+	{0xce00202c, 0x000d1746},
+	{0xce002030, 0x05061787},
+	{0xce002034, 0x07800000},
+	{0xce00209c, 0x00900008},
+	{0xce0020a0, 0x00000000},
+	{0xce0023f8, 0x00000000},
+	{0xce0023fc, 0x00000001},
+	{0xce0030a4, 0x00001901},
+	{0xce0030b8, 0x5d08908e},
+	{0xce004000, 0x00000044},
+	{0xce004004, 0x00750075},
+	{0xce004008, 0x00000075},
+	{0xce00400c, 0x10000075},
+	{0xce004010, 0x3F384905},
+	{0xce004014, 0x40182000},
+	{0xce004018, 0x20600000},
+	{0xce00401c, 0x0C010120},
+	{0xce004020, 0x50505050},
+	{0xce004024, 0x50000000},
+	{0xce004028, 0x50505050},
+	{0xce00402c, 0x506070A0},
+	{0xce004030, 0xF0000000},
+	{0xce004034, 0x00002424},
+	{0xce004038, 0x00001420},
+	{0xce00409c, 0x0000300A},
+	{0xce0040c0, 0x20000280},
+	{0xce0040c4, 0x30023002},
+	{0xce0040c8, 0x0000003a},
+	{0xce004130, 0x40000000},
+	{0xce004164, 0x009C007E},
+	{0xce004180, 0x00044400},
+	{0xce004188, 0x82000000},
+	{0xce004190, 0x00000000},
+	{0xce004194, 0xffffffff},
+	{0xce004380, 0x00700010},
+	{0xce004384, 0x00007575},
+	{0xce004388, 0x0001fe3e},
+	{0xce00438c, 0x0000fe3e},
+	{0xce0043f8, 0x00000001},
+	{0xce007000, 0x00000000},
+	{0xce007004, 0x00008000},
+	{0xce007008, 0x00000000},
+	{0xce00700c, 0x00000000},
+	{0xce007010, 0x00000000},
+	{0xce007014, 0x00000000},
+	{0xce007018, 0x00000000},
+	{0xce00701c, 0x00000000},
+	{0xce007020, 0x00000000},
+	{0xce007024, 0x00000000},
+	{0xce007028, 0x00000000},
+	{0xce00702c, 0x00000000},
+	{0xce007030, 0x00000000},
+	{0xce007034, 0x00000000},
+	{0xce007038, 0x00000000},
+	{0xce00703c, 0x00000000},
+	{0xce007040, 0x02000200},
+	{0xce007048, 0x00000000},
+	{0xce00704c, 0x00000000},
+	{0xce007050, 0x00000000},
+	{0xce007054, 0x00000000},
+	{0xce007058, 0x000028ff},
+	{0xce00705c, 0x00000000},
+	{0xce007060, 0x00000000},
+	{0xce007064, 0x00000000},
+	{0xce007068, 0x00000000},
+	{0xce00706c, 0x00000202},
+	{0xce007070, 0x80ffc200},
+	{0xce007074, 0x00000000},
+	{0xce007078, 0x00000000},
+	{0xce00707c, 0x00000000},
+	{0xce007080, 0x00000000},
+	{0xce007084, 0x00000000},
+	{0xce007088, 0x00000000},
+	{0xce00708c, 0x00000000},
+	{0xce007090, 0x00000000},
+	{0xce007094, 0x00000000},
+	{0xce007098, 0x00000000},
+	{0xce00709c, 0x00000000},
+	{0xce0070a0, 0x00000000},
+	{0xce0070a4, 0x00000000},
+	{0xce0070a8, 0x00000000},
+	{0xce0070ac, 0x00000000},
+	{0xce0070b0, 0x00000000},
+	{0xce0070b4, 0x00000000},
+	{0xce0070b8, 0x00000000},
+	{0xce0070bc, 0x00000000},
+	{0xce0070c0, 0x00000000},
+	{0xce0070c4, 0x00000000},
+	{0xce0070c8, 0x00000000},
+	{0xce0070cc, 0x00000000},
+	{0xce0070d0, 0x00000000},
+	{0xce0070d4, 0x00000000},
+	{0xce0070d8, 0x00000000},
+	{0xce0070dc, 0x00000000},
+	{0xce0070e0, 0x00000000},
+	{0xce0070e4, 0x00000000},
+	{0xce0070e8, 0x00000000},
+	{0xce0070ec, 0x00000000},
+	{0xce0070f0, 0x00000000},
+	{0xce0070f4, 0x00000000},
+	{0xce0070f8, 0x00000000},
+	{0xce0070fc, 0x00000000},
+	{0xce007100, 0x00000000},
+	{0xce007104, 0x00000000},
+	{0xce007108, 0x00000000},
+	{0xce00710c, 0x00000000},
+	{0xce007110, 0x00000000},
+	{0xce007114, 0x00000000},
+	{0xce007118, 0x00000000},
+	{0xce00711c, 0x00000000},
+	{0xce007120, 0x02000200},
+	{0xce007124, 0x02000200},
+	{0xce007128, 0x02000200},
+	{0xce00712c, 0x02000200},
+	{0xce007130, 0x02000200},
+	{0xce007134, 0x02000200},
+	{0xce007138, 0x02000200},
+	{0xce00713c, 0x02000200},
+	{0xce007140, 0x02000200},
+	{0xce007144, 0x02000200},
+	{0xce007148, 0x02000200},
+	{0xce00714c, 0x02000200},
+	{0xce007150, 0x02000200},
+	{0xce007154, 0x02000200},
+	{0xce007158, 0x00000000},
+	{0xce00715c, 0x00000000},
+	{0xce007160, 0x00000000},
+	{0xce007164, 0x00000000},
+	{0xce007168, 0x00000000},
+	{0xce00716c, 0x00000000},
+	{0xce007170, 0x00000000},
+	{0xce007174, 0x00000000},
+	{0xce007178, 0x00000000},
+	{0xce00717c, 0x00000000},
+	{0xce007180, 0x00000000},
+	{0xce007184, 0x00000000},
+	{0xce007188, 0x00000000},
+	{0xce00718c, 0x00000000},
+	{0xce007190, 0x00000000},
+	{0xce007194, 0x00000000},
+	{0xce007198, 0x00000000},
+	{0xce00719c, 0x00000000},
+	{0xce0071a0, 0x00000000},
+	{0xce0071a4, 0x00000000},
+	{0xce0071a8, 0x00000000},
+	{0xce0071ac, 0x00000000},
+	{0xce0071b0, 0x00000000},
+	{0xce0071b4, 0x00000100},
+	{0xce0071b8, 0x00000000},
+	{0xce0071c0, 0x00000000},
+	{0xce0071c4, 0x00000000},
+	{0xce0071c8, 0x00000000},
+	{0xce0071cc, 0x00000000},
+	{0xce0071d0, 0x00000000},
+	{0xce0071d4, 0x00000000},
+	{0xce0071d8, 0x00000000},
+	{0xce0071dc, 0x00000000},
+	{0xce0071e0, 0x00000000},
+	{0xce0071e4, 0x00000000},
+	{0xce0071e8, 0x00000000},
+	{0xce0071ec, 0x00000000},
+	{0xce0071f0, 0x00000000},
+	{0xce0071f4, 0x00000000},
+	{0xce0071f8, 0x00000000},
+	{0xce0071fc, 0x00000000},
+	{0xce0043fc, 0x000104E5},
+	{0xce007044, 0x00028080},
+	{0xce000000, 0x80000016},
+};
+
+static const u32 wifi_tx_gain[] = {
+	0x79807980,
+	0x72797279,
+	0x6C726C72,
+	0x666C666C,
+	0x60666066,
+	0x5B605B60,
+	0x565B565B,
+	0x51565156,
+	0x4C514C51,
+	0x484C484C,
+	0x44484448,
+	0x40444044,
+	0x3C403C40,
+	0x3A3D3A3D,
+	0x36393639,
+};
+
+static ssv_cabrio_reg asic_rf_setting[] = {
+	{0xCE010038, 0x0003E07C},
+	{0xCE010060, 0x00406000},
+	{0xCE01009C, 0x00000024},
+	{0xCE0100A0, 0x00EC4CC5},
+	{0xCE010000, 0x40002000},
+	{0xCE010004, 0x00020FC0},
+	{0xCE010008, 0x000DF69B},
+	{0xCE010014, 0x3D3E84FE},
+	{0xCE010018, 0x01457D79},
+	{0xCE01001C, 0x000103A7},
+	{0xCE010020, 0x000103A6},
+	{0xCE01002C, 0x00032CA8},
+	{0xCE010048, 0xFCCCCF27},
+	{0xCE010050, 0x00444000},
+	{0xCE01000C, 0x151558C5},
+	{0xCE010010, 0x01011A88},
+	{0xCE010024, 0x00012001},
+	{0xCE010028, 0x00036000},
+	{0xCE010030, 0x20EA0224},
+	{0xCE010034, 0x44000755},
+	{0xCE01003C, 0x55D89D8A},
+	{0xCE010040, 0x005508BB},
+	{0xCE010044, 0x07C08BFF},
+	{0xCE01004C, 0x07700830},
+	{0xCE010054, 0x00007FF4},
+	{0xCE010058, 0x0000000E},
+	{0xCE01005C, 0x00088018},
+	{0xCE010064, 0x08820820},
+	{0xCE010068, 0x00820820},
+	{0xCE01006C, 0x00820820},
+	{0xCE010070, 0x00820820},
+	{0xCE010074, 0x00820820},
+	{0xCE010078, 0x00820820},
+	{0xCE01007C, 0x00820820},
+	{0xCE010080, 0x00820820},
+	{0xCE010084, 0x00004080},
+	{0xCE010088, 0x200800FE},
+	{0xCE01008C, 0xAAAAAAAA},
+	{0xCE010090, 0xAAAAAAAA},
+	{0xCE010094, 0x0000A487},
+	{0xCE010098, 0x0000070E},
+	{0xCE0100A4, 0x00000F43},
+	{0xCE0100A8, 0x00098900},
+	{0xCE0100AC, 0x00000000},
+	{0xC00003AC, 0x00000000},
+	{0xC00003B0, 0x00000000},
+	{0xC00003B4, 0x00000000},
+	{0xC00003BC, 0x00000000},
+	{0xC0001D00, 0x5E000040},
+	{0xC0001D04, 0x015D015D},
+	{0xC0001D08, 0x00000001},
+	{0xC0001D0C, 0x55550000},
+	{0xC0001D20, 0x7FFF0000},
+	{0xC0001D24, 0x00000003},
+	{0xC0001D28, 0x00000000},
+	{0xC0001D2C, 0x00000000},
+};
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_reg.h b/drivers/net/wireless/ssv6051/include/ssv6200_reg.h
new file mode 100644
index 00000000000..d4a99b25d61
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200_reg.h
@@ -0,0 +1,9694 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define SYS_REG_BASE 0xc0000000
+#define WBOOT_REG_BASE 0xc0000100
+#define TU0_US_REG_BASE 0xc0000200
+#define TU1_US_REG_BASE 0xc0000210
+#define TU2_US_REG_BASE 0xc0000220
+#define TU3_US_REG_BASE 0xc0000230
+#define TM0_MS_REG_BASE 0xc0000240
+#define TM1_MS_REG_BASE 0xc0000250
+#define TM2_MS_REG_BASE 0xc0000260
+#define TM3_MS_REG_BASE 0xc0000270
+#define MCU_WDT_REG_BASE 0xc0000280
+#define SYS_WDT_REG_BASE 0xc0000284
+#define GPIO_REG_BASE 0xc0000300
+#define SD_REG_BASE 0xc0000800
+#define SPI_REG_BASE 0xc0000a00
+#define CSR_I2C_MST_BASE 0xc0000b00
+#define UART_REG_BASE 0xc0000c00
+#define DAT_UART_REG_BASE 0xc0000d00
+#define INT_REG_BASE 0xc0000e00
+#define DBG_SPI_REG_BASE 0xc0000f00
+#define FLASH_SPI_REG_BASE 0xc0001000
+#define DMA_REG_BASE 0xc0001c00
+#define CSR_PMU_BASE 0xc0001d00
+#define CSR_RTC_BASE 0xc0001d20
+#define RTC_RAM_BASE 0xc0001d80
+#define D2_DMA_REG_BASE 0xc0001e00
+#define HCI_REG_BASE 0xc1000000
+#define CO_REG_BASE 0xc2000000
+#define EFS_REG_BASE 0xc2000100
+#define SMS4_REG_BASE 0xc3000000
+#define MRX_REG_BASE 0xc6000000
+#define AMPDU_REG_BASE 0xc6001000
+#define MT_REG_CSR_BASE 0xc6002000
+#define TXQ0_MT_Q_REG_CSR_BASE 0xc6002100
+#define TXQ1_MT_Q_REG_CSR_BASE 0xc6002200
+#define TXQ2_MT_Q_REG_CSR_BASE 0xc6002300
+#define TXQ3_MT_Q_REG_CSR_BASE 0xc6002400
+#define TXQ4_MT_Q_REG_CSR_BASE 0xc6002500
+#define HIF_INFO_BASE 0xca000000
+#define PHY_RATE_INFO_BASE 0xca000200
+#define MAC_GLB_SET_BASE 0xca000300
+#define BTCX_REG_BASE 0xca000400
+#define MIB_REG_BASE 0xca000800
+#define CBR_A_REG_BASE 0xcb000000
+#define MB_REG_BASE 0xcd000000
+#define ID_MNG_REG_BASE 0xcd010000
+#define CSR_PHY_BASE 0xce000000
+#define CSR_RF_BASE 0xce010000
+#define MMU_REG_BASE 0xcf000000
+#define SYS_REG_BANK_SIZE 0x000000b4
+#define WBOOT_REG_BANK_SIZE 0x0000000c
+#define TU0_US_REG_BANK_SIZE 0x00000010
+#define TU1_US_REG_BANK_SIZE 0x00000010
+#define TU2_US_REG_BANK_SIZE 0x00000010
+#define TU3_US_REG_BANK_SIZE 0x00000010
+#define TM0_MS_REG_BANK_SIZE 0x00000010
+#define TM1_MS_REG_BANK_SIZE 0x00000010
+#define TM2_MS_REG_BANK_SIZE 0x00000010
+#define TM3_MS_REG_BANK_SIZE 0x00000010
+#define MCU_WDT_REG_BANK_SIZE 0x00000004
+#define SYS_WDT_REG_BANK_SIZE 0x00000004
+#define GPIO_REG_BANK_SIZE 0x000000d4
+#define SD_REG_BANK_SIZE 0x00000180
+#define SPI_REG_BANK_SIZE 0x00000040
+#define CSR_I2C_MST_BANK_SIZE 0x00000018
+#define UART_REG_BANK_SIZE 0x00000028
+#define DAT_UART_REG_BANK_SIZE 0x00000028
+#define INT_REG_BANK_SIZE 0x0000004c
+#define DBG_SPI_REG_BANK_SIZE 0x00000040
+#define FLASH_SPI_REG_BANK_SIZE 0x0000002c
+#define DMA_REG_BANK_SIZE 0x00000014
+#define CSR_PMU_BANK_SIZE 0x00000100
+#define CSR_RTC_BANK_SIZE 0x000000e0
+#define RTC_RAM_BANK_SIZE 0x00000080
+#define D2_DMA_REG_BANK_SIZE 0x00000014
+#define HCI_REG_BANK_SIZE 0x000000cc
+#define CO_REG_BANK_SIZE 0x000000ac
+#define EFS_REG_BANK_SIZE 0x0000006c
+#define SMS4_REG_BANK_SIZE 0x00000070
+#define MRX_REG_BANK_SIZE 0x00000198
+#define AMPDU_REG_BANK_SIZE 0x00000014
+#define MT_REG_CSR_BANK_SIZE 0x00000100
+#define TXQ0_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ1_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ2_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ3_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define TXQ4_MT_Q_REG_CSR_BANK_SIZE 0x0000001c
+#define HIF_INFO_BANK_SIZE 0x0000009c
+#define PHY_RATE_INFO_BANK_SIZE 0x000000b8
+#define MAC_GLB_SET_BANK_SIZE 0x0000003c
+#define BTCX_REG_BANK_SIZE 0x0000000c
+#define MIB_REG_BANK_SIZE 0x00000480
+#define CBR_A_REG_BANK_SIZE 0x001203fc
+#define MB_REG_BANK_SIZE 0x000000a0
+#define ID_MNG_REG_BANK_SIZE 0x00000084
+#define CSR_PHY_BANK_SIZE 0x000071c0
+#define CSR_RF_BANK_SIZE 0x000000b0
+#define MMU_REG_BANK_SIZE 0x000000c0
+#define ADR_BRG_SW_RST (SYS_REG_BASE+0x00000000)
+#define ADR_BOOT (SYS_REG_BASE+0x00000004)
+#define ADR_CHIP_ID_0 (SYS_REG_BASE+0x00000008)
+#define ADR_CHIP_ID_1 (SYS_REG_BASE+0x0000000c)
+#define ADR_CHIP_ID_2 (SYS_REG_BASE+0x00000010)
+#define ADR_CHIP_ID_3 (SYS_REG_BASE+0x00000014)
+#define ADR_CLOCK_SELECTION (SYS_REG_BASE+0x00000018)
+#define ADR_PLATFORM_CLOCK_ENABLE (SYS_REG_BASE+0x0000001c)
+#define ADR_SYS_CSR_CLOCK_ENABLE (SYS_REG_BASE+0x00000020)
+#define ADR_MCU_DBG_SEL (SYS_REG_BASE+0x00000024)
+#define ADR_MCU_DBG_DATA (SYS_REG_BASE+0x00000028)
+#define ADR_AHB_BRG_STATUS (SYS_REG_BASE+0x0000002c)
+#define ADR_BIST_BIST_CTRL (SYS_REG_BASE+0x00000030)
+#define ADR_BIST_MODE_REG_IN (SYS_REG_BASE+0x00000034)
+#define ADR_BIST_MODE_REG_OUT (SYS_REG_BASE+0x00000038)
+#define ADR_BIST_MONITOR_BUS_LSB (SYS_REG_BASE+0x0000003c)
+#define ADR_BIST_MONITOR_BUS_MSB (SYS_REG_BASE+0x00000040)
+#define ADR_TB_ADR_SEL (SYS_REG_BASE+0x00000044)
+#define ADR_TB_RDATA (SYS_REG_BASE+0x00000048)
+#define ADR_UART_W2B (SYS_REG_BASE+0x0000004c)
+#define ADR_AHB_ILL_ADDR (SYS_REG_BASE+0x00000050)
+#define ADR_AHB_FEN_ADDR (SYS_REG_BASE+0x00000054)
+#define ADR_AHB_ILLFEN_STATUS (SYS_REG_BASE+0x00000058)
+#define ADR_PWM_A (SYS_REG_BASE+0x00000080)
+#define ADR_PWM_B (SYS_REG_BASE+0x00000084)
+#define ADR_HBUSREQ_LOCK (SYS_REG_BASE+0x00000090)
+#define ADR_HBURST_LOCK (SYS_REG_BASE+0x00000094)
+#define ADR_PRESCALER_USTIMER (SYS_REG_BASE+0x000000a0)
+#define ADR_BIST_MODE_REG_IN_MMU (SYS_REG_BASE+0x000000a4)
+#define ADR_BIST_MODE_REG_OUT_MMU (SYS_REG_BASE+0x000000a8)
+#define ADR_BIST_MONITOR_BUS_MMU (SYS_REG_BASE+0x000000ac)
+#define ADR_TEST_MODE (SYS_REG_BASE+0x000000b0)
+#define ADR_BOOT_INFO (WBOOT_REG_BASE+0x00000000)
+#define ADR_SD_INIT_CFG (WBOOT_REG_BASE+0x00000004)
+#define ADR_SPARE_UART_INFO (WBOOT_REG_BASE+0x00000008)
+#define ADR_TU0_MICROSECOND_TIMER (TU0_US_REG_BASE+0x00000000)
+#define ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE (TU0_US_REG_BASE+0x00000004)
+#define ADR_TU0_DUMMY_BIT_0 (TU0_US_REG_BASE+0x00000008)
+#define ADR_TU0_DUMMY_BIT_1 (TU0_US_REG_BASE+0x0000000c)
+#define ADR_TU1_MICROSECOND_TIMER (TU1_US_REG_BASE+0x00000000)
+#define ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE (TU1_US_REG_BASE+0x00000004)
+#define ADR_TU1_DUMMY_BIT_0 (TU1_US_REG_BASE+0x00000008)
+#define ADR_TU1_DUMMY_BIT_1 (TU1_US_REG_BASE+0x0000000c)
+#define ADR_TU2_MICROSECOND_TIMER (TU2_US_REG_BASE+0x00000000)
+#define ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE (TU2_US_REG_BASE+0x00000004)
+#define ADR_TU2_DUMMY_BIT_0 (TU2_US_REG_BASE+0x00000008)
+#define ADR_TU2_DUMMY_BIT_1 (TU2_US_REG_BASE+0x0000000c)
+#define ADR_TU3_MICROSECOND_TIMER (TU3_US_REG_BASE+0x00000000)
+#define ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE (TU3_US_REG_BASE+0x00000004)
+#define ADR_TU3_DUMMY_BIT_0 (TU3_US_REG_BASE+0x00000008)
+#define ADR_TU3_DUMMY_BIT_1 (TU3_US_REG_BASE+0x0000000c)
+#define ADR_TM0_MILISECOND_TIMER (TM0_MS_REG_BASE+0x00000000)
+#define ADR_TM0_CURRENT_MILISECOND_TIME_VALUE (TM0_MS_REG_BASE+0x00000004)
+#define ADR_TM0_DUMMY_BIT_0 (TM0_MS_REG_BASE+0x00000008)
+#define ADR_TM0_DUMMY_BIT_1 (TM0_MS_REG_BASE+0x0000000c)
+#define ADR_TM1_MILISECOND_TIMER (TM1_MS_REG_BASE+0x00000000)
+#define ADR_TM1_CURRENT_MILISECOND_TIME_VALUE (TM1_MS_REG_BASE+0x00000004)
+#define ADR_TM1_DUMMY_BIT_0 (TM1_MS_REG_BASE+0x00000008)
+#define ADR_TM1_DUMMY_BIT_1 (TM1_MS_REG_BASE+0x0000000c)
+#define ADR_TM2_MILISECOND_TIMER (TM2_MS_REG_BASE+0x00000000)
+#define ADR_TM2_CURRENT_MILISECOND_TIME_VALUE (TM2_MS_REG_BASE+0x00000004)
+#define ADR_TM2_DUMMY_BIT_0 (TM2_MS_REG_BASE+0x00000008)
+#define ADR_TM2_DUMMY_BIT_1 (TM2_MS_REG_BASE+0x0000000c)
+#define ADR_TM3_MILISECOND_TIMER (TM3_MS_REG_BASE+0x00000000)
+#define ADR_TM3_CURRENT_MILISECOND_TIME_VALUE (TM3_MS_REG_BASE+0x00000004)
+#define ADR_TM3_DUMMY_BIT_0 (TM3_MS_REG_BASE+0x00000008)
+#define ADR_TM3_DUMMY_BIT_1 (TM3_MS_REG_BASE+0x0000000c)
+#define ADR_MCU_WDOG_REG (MCU_WDT_REG_BASE+0x00000000)
+#define ADR_SYS_WDOG_REG (SYS_WDT_REG_BASE+0x00000000)
+#define ADR_PAD6 (GPIO_REG_BASE+0x00000000)
+#define ADR_PAD7 (GPIO_REG_BASE+0x00000004)
+#define ADR_PAD8 (GPIO_REG_BASE+0x00000008)
+#define ADR_PAD9 (GPIO_REG_BASE+0x0000000c)
+#define ADR_PAD11 (GPIO_REG_BASE+0x00000010)
+#define ADR_PAD15 (GPIO_REG_BASE+0x00000014)
+#define ADR_PAD16 (GPIO_REG_BASE+0x00000018)
+#define ADR_PAD17 (GPIO_REG_BASE+0x0000001c)
+#define ADR_PAD18 (GPIO_REG_BASE+0x00000020)
+#define ADR_PAD19 (GPIO_REG_BASE+0x00000024)
+#define ADR_PAD20 (GPIO_REG_BASE+0x00000028)
+#define ADR_PAD21 (GPIO_REG_BASE+0x0000002c)
+#define ADR_PAD22 (GPIO_REG_BASE+0x00000030)
+#define ADR_PAD24 (GPIO_REG_BASE+0x00000034)
+#define ADR_PAD25 (GPIO_REG_BASE+0x00000038)
+#define ADR_PAD27 (GPIO_REG_BASE+0x0000003c)
+#define ADR_PAD28 (GPIO_REG_BASE+0x00000040)
+#define ADR_PAD29 (GPIO_REG_BASE+0x00000044)
+#define ADR_PAD30 (GPIO_REG_BASE+0x00000048)
+#define ADR_PAD31 (GPIO_REG_BASE+0x0000004c)
+#define ADR_PAD32 (GPIO_REG_BASE+0x00000050)
+#define ADR_PAD33 (GPIO_REG_BASE+0x00000054)
+#define ADR_PAD34 (GPIO_REG_BASE+0x00000058)
+#define ADR_PAD42 (GPIO_REG_BASE+0x0000005c)
+#define ADR_PAD43 (GPIO_REG_BASE+0x00000060)
+#define ADR_PAD44 (GPIO_REG_BASE+0x00000064)
+#define ADR_PAD45 (GPIO_REG_BASE+0x00000068)
+#define ADR_PAD46 (GPIO_REG_BASE+0x0000006c)
+#define ADR_PAD47 (GPIO_REG_BASE+0x00000070)
+#define ADR_PAD48 (GPIO_REG_BASE+0x00000074)
+#define ADR_PAD49 (GPIO_REG_BASE+0x00000078)
+#define ADR_PAD50 (GPIO_REG_BASE+0x0000007c)
+#define ADR_PAD51 (GPIO_REG_BASE+0x00000080)
+#define ADR_PAD52 (GPIO_REG_BASE+0x00000084)
+#define ADR_PAD53 (GPIO_REG_BASE+0x00000088)
+#define ADR_PAD54 (GPIO_REG_BASE+0x0000008c)
+#define ADR_PAD56 (GPIO_REG_BASE+0x00000090)
+#define ADR_PAD57 (GPIO_REG_BASE+0x00000094)
+#define ADR_PAD58 (GPIO_REG_BASE+0x00000098)
+#define ADR_PAD59 (GPIO_REG_BASE+0x0000009c)
+#define ADR_PAD60 (GPIO_REG_BASE+0x000000a0)
+#define ADR_PAD61 (GPIO_REG_BASE+0x000000a4)
+#define ADR_PAD62 (GPIO_REG_BASE+0x000000a8)
+#define ADR_PAD64 (GPIO_REG_BASE+0x000000ac)
+#define ADR_PAD65 (GPIO_REG_BASE+0x000000b0)
+#define ADR_PAD66 (GPIO_REG_BASE+0x000000b4)
+#define ADR_PAD68 (GPIO_REG_BASE+0x000000b8)
+#define ADR_PAD67 (GPIO_REG_BASE+0x000000bc)
+#define ADR_PAD69 (GPIO_REG_BASE+0x000000c0)
+#define ADR_PAD70 (GPIO_REG_BASE+0x000000c4)
+#define ADR_PAD231 (GPIO_REG_BASE+0x000000c8)
+#define ADR_PIN_SEL_0 (GPIO_REG_BASE+0x000000cc)
+#define ADR_PIN_SEL_1 (GPIO_REG_BASE+0x000000d0)
+#define ADR_IO_PORT_REG (SD_REG_BASE+0x00000000)
+#define ADR_INT_MASK_REG (SD_REG_BASE+0x00000004)
+#define ADR_INT_STATUS_REG (SD_REG_BASE+0x00000008)
+#define ADR_FN1_STATUS_REG (SD_REG_BASE+0x0000000c)
+#define ADR_CARD_PKT_STATUS_TEST (SD_REG_BASE+0x00000010)
+#define ADR_SYSTEM_INFORMATION_REG (SD_REG_BASE+0x0000001c)
+#define ADR_CARD_RCA_REG (SD_REG_BASE+0x00000020)
+#define ADR_SDIO_FIFO_WR_THLD_REG (SD_REG_BASE+0x00000024)
+#define ADR_SDIO_FIFO_WR_LIMIT_REG (SD_REG_BASE+0x00000028)
+#define ADR_SDIO_TX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x0000002c)
+#define ADR_SDIO_THLD_FOR_CMD53RD_REG (SD_REG_BASE+0x00000030)
+#define ADR_SDIO_RX_DATA_BATCH_SIZE_REG (SD_REG_BASE+0x00000034)
+#define ADR_SDIO_LOG_START_END_DATA_REG (SD_REG_BASE+0x00000038)
+#define ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG (SD_REG_BASE+0x00000040)
+#define ADR_SDIO_LAST_CMD_INDEX_CRC_REG (SD_REG_BASE+0x00000044)
+#define ADR_SDIO_LAST_CMD_ARG_REG (SD_REG_BASE+0x00000048)
+#define ADR_SDIO_BUS_STATE_DEBUG_MONITOR (SD_REG_BASE+0x0000004c)
+#define ADR_SDIO_CARD_STATUS_REG (SD_REG_BASE+0x00000050)
+#define ADR_R5_RESP_FLAG_OUT_TIMING (SD_REG_BASE+0x00000054)
+#define ADR_CMD52_DATA_FOR_LAST_TIME (SD_REG_BASE+0x0000005c)
+#define ADR_FN1_DMA_START_ADDR_REG (SD_REG_BASE+0x00000060)
+#define ADR_FN1_INT_CTRL_RESET (SD_REG_BASE+0x00000064)
+#define ADR_IO_REG_PORT_REG (SD_REG_BASE+0x00000070)
+#define ADR_SDIO_FIFO_ERROR_CNT (SD_REG_BASE+0x0000007c)
+#define ADR_SDIO_CRC7_CRC16_ERROR_REG (SD_REG_BASE+0x00000080)
+#define ADR_SDIO_BLOCK_CNT_INFO (SD_REG_BASE+0x00000084)
+#define ADR_RX_DATA_CMD52_ABORT_COUNT (SD_REG_BASE+0x0000008c)
+#define ADR_FIFO_PTR_READ_BLOCK_CNT (SD_REG_BASE+0x00000090)
+#define ADR_TX_TIME_OUT_READ_CTRL (SD_REG_BASE+0x00000094)
+#define ADR_SDIO_TX_ALLOC_REG (SD_REG_BASE+0x00000098)
+#define ADR_SDIO_TX_INFORM (SD_REG_BASE+0x0000009c)
+#define ADR_F1_BLOCK_SIZE_0_REG (SD_REG_BASE+0x000000a0)
+#define ADR_SDIO_COMMAND_LOG_DATA_31_0 (SD_REG_BASE+0x000000b0)
+#define ADR_SDIO_COMMAND_LOG_DATA_63_32 (SD_REG_BASE+0x000000b4)
+#define ADR_SYSTEM_INFORMATION_REGISTER (SD_REG_BASE+0x000000bc)
+#define ADR_CCCR_00H_REG (SD_REG_BASE+0x000000c0)
+#define ADR_CCCR_04H_REG (SD_REG_BASE+0x000000c4)
+#define ADR_CCCR_08H_REG (SD_REG_BASE+0x000000c8)
+#define ADR_CCCR_13H_REG (SD_REG_BASE+0x000000d0)
+#define ADR_FBR_100H_REG (SD_REG_BASE+0x000000e0)
+#define ADR_FBR_109H_REG (SD_REG_BASE+0x000000e8)
+#define ADR_F0_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000100)
+#define ADR_F0_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000104)
+#define ADR_F0_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000108)
+#define ADR_F0_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000010c)
+#define ADR_F0_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000110)
+#define ADR_F0_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000114)
+#define ADR_F0_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000118)
+#define ADR_F0_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000011c)
+#define ADR_F0_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000120)
+#define ADR_F0_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000124)
+#define ADR_F0_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000128)
+#define ADR_F0_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000012c)
+#define ADR_F0_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000130)
+#define ADR_F0_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000134)
+#define ADR_F0_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000138)
+#define ADR_F0_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000013c)
+#define ADR_F1_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000140)
+#define ADR_F1_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000144)
+#define ADR_F1_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000148)
+#define ADR_F1_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000014c)
+#define ADR_F1_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000150)
+#define ADR_F1_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000154)
+#define ADR_F1_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000158)
+#define ADR_F1_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000015c)
+#define ADR_F1_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000160)
+#define ADR_F1_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000164)
+#define ADR_F1_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000168)
+#define ADR_F1_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000016c)
+#define ADR_F1_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000170)
+#define ADR_F1_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000174)
+#define ADR_F1_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000178)
+#define ADR_F1_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000017c)
+#define ADR_SPI_MODE (SPI_REG_BASE+0x00000000)
+#define ADR_RX_QUOTA (SPI_REG_BASE+0x00000004)
+#define ADR_CONDITION_NUMBER (SPI_REG_BASE+0x00000008)
+#define ADR_HOST_PATH (SPI_REG_BASE+0x0000000c)
+#define ADR_TX_SEG (SPI_REG_BASE+0x00000010)
+#define ADR_DEBUG_BURST_MODE (SPI_REG_BASE+0x00000014)
+#define ADR_SPI_TO_PHY_PARAM1 (SPI_REG_BASE+0x00000018)
+#define ADR_SPI_TO_PHY_PARAM2 (SPI_REG_BASE+0x0000001c)
+#define ADR_SPI_STS (SPI_REG_BASE+0x00000020)
+#define ADR_TX_ALLOC_SET (SPI_REG_BASE+0x00000024)
+#define ADR_TX_ALLOC (SPI_REG_BASE+0x00000028)
+#define ADR_DBG_CNT (SPI_REG_BASE+0x0000002c)
+#define ADR_DBG_CNT2 (SPI_REG_BASE+0x00000030)
+#define ADR_DBG_CNT3 (SPI_REG_BASE+0x00000034)
+#define ADR_DBG_CNT4 (SPI_REG_BASE+0x00000038)
+#define ADR_INT_TAG (SPI_REG_BASE+0x0000003c)
+#define ADR_I2CM_EN (CSR_I2C_MST_BASE+0x00000000)
+#define ADR_I2CM_DEV_A (CSR_I2C_MST_BASE+0x00000004)
+#define ADR_I2CM_LEN (CSR_I2C_MST_BASE+0x00000008)
+#define ADR_I2CM_WDAT (CSR_I2C_MST_BASE+0x0000000c)
+#define ADR_I2CM_RDAT (CSR_I2C_MST_BASE+0x00000010)
+#define ADR_I2CM_EN_2 (CSR_I2C_MST_BASE+0x00000014)
+#define ADR_UART_DATA (UART_REG_BASE+0x00000000)
+#define ADR_UART_IER (UART_REG_BASE+0x00000004)
+#define ADR_UART_FCR (UART_REG_BASE+0x00000008)
+#define ADR_UART_LCR (UART_REG_BASE+0x0000000c)
+#define ADR_UART_MCR (UART_REG_BASE+0x00000010)
+#define ADR_UART_LSR (UART_REG_BASE+0x00000014)
+#define ADR_UART_MSR (UART_REG_BASE+0x00000018)
+#define ADR_UART_SPR (UART_REG_BASE+0x0000001c)
+#define ADR_UART_RTHR (UART_REG_BASE+0x00000020)
+#define ADR_UART_ISR (UART_REG_BASE+0x00000024)
+#define ADR_DAT_UART_DATA (DAT_UART_REG_BASE+0x00000000)
+#define ADR_DAT_UART_IER (DAT_UART_REG_BASE+0x00000004)
+#define ADR_DAT_UART_FCR (DAT_UART_REG_BASE+0x00000008)
+#define ADR_DAT_UART_LCR (DAT_UART_REG_BASE+0x0000000c)
+#define ADR_DAT_UART_MCR (DAT_UART_REG_BASE+0x00000010)
+#define ADR_DAT_UART_LSR (DAT_UART_REG_BASE+0x00000014)
+#define ADR_DAT_UART_MSR (DAT_UART_REG_BASE+0x00000018)
+#define ADR_DAT_UART_SPR (DAT_UART_REG_BASE+0x0000001c)
+#define ADR_DAT_UART_RTHR (DAT_UART_REG_BASE+0x00000020)
+#define ADR_DAT_UART_ISR (DAT_UART_REG_BASE+0x00000024)
+#define ADR_INT_MASK (INT_REG_BASE+0x00000000)
+#define ADR_INT_MODE (INT_REG_BASE+0x00000004)
+#define ADR_INT_IRQ_STS (INT_REG_BASE+0x00000008)
+#define ADR_INT_FIQ_STS (INT_REG_BASE+0x0000000c)
+#define ADR_INT_IRQ_RAW (INT_REG_BASE+0x00000010)
+#define ADR_INT_FIQ_RAW (INT_REG_BASE+0x00000014)
+#define ADR_INT_PERI_MASK (INT_REG_BASE+0x00000018)
+#define ADR_INT_PERI_STS (INT_REG_BASE+0x0000001c)
+#define ADR_INT_PERI_RAW (INT_REG_BASE+0x00000020)
+#define ADR_INT_GPI_CFG (INT_REG_BASE+0x00000024)
+#define ADR_SYS_INT_FOR_HOST (INT_REG_BASE+0x00000028)
+#define ADR_SPI_IPC (INT_REG_BASE+0x00000034)
+#define ADR_SDIO_IPC (INT_REG_BASE+0x00000038)
+#define ADR_SDIO_MASK (INT_REG_BASE+0x0000003c)
+#define ADR_SDIO_IRQ_STS (INT_REG_BASE+0x00000040)
+#define ADR_SD_PERI_MASK (INT_REG_BASE+0x00000044)
+#define ADR_SD_PERI_STS (INT_REG_BASE+0x00000048)
+#define ADR_DBG_SPI_MODE (DBG_SPI_REG_BASE+0x00000000)
+#define ADR_DBG_RX_QUOTA (DBG_SPI_REG_BASE+0x00000004)
+#define ADR_DBG_CONDITION_NUMBER (DBG_SPI_REG_BASE+0x00000008)
+#define ADR_DBG_HOST_PATH (DBG_SPI_REG_BASE+0x0000000c)
+#define ADR_DBG_TX_SEG (DBG_SPI_REG_BASE+0x00000010)
+#define ADR_DBG_DEBUG_BURST_MODE (DBG_SPI_REG_BASE+0x00000014)
+#define ADR_DBG_SPI_TO_PHY_PARAM1 (DBG_SPI_REG_BASE+0x00000018)
+#define ADR_DBG_SPI_TO_PHY_PARAM2 (DBG_SPI_REG_BASE+0x0000001c)
+#define ADR_DBG_SPI_STS (DBG_SPI_REG_BASE+0x00000020)
+#define ADR_DBG_TX_ALLOC_SET (DBG_SPI_REG_BASE+0x00000024)
+#define ADR_DBG_TX_ALLOC (DBG_SPI_REG_BASE+0x00000028)
+#define ADR_DBG_DBG_CNT (DBG_SPI_REG_BASE+0x0000002c)
+#define ADR_DBG_DBG_CNT2 (DBG_SPI_REG_BASE+0x00000030)
+#define ADR_DBG_DBG_CNT3 (DBG_SPI_REG_BASE+0x00000034)
+#define ADR_DBG_DBG_CNT4 (DBG_SPI_REG_BASE+0x00000038)
+#define ADR_DBG_INT_TAG (DBG_SPI_REG_BASE+0x0000003c)
+#define ADR_BOOT_ADDR (FLASH_SPI_REG_BASE+0x00000000)
+#define ADR_VERIFY_DATA (FLASH_SPI_REG_BASE+0x00000004)
+#define ADR_FLASH_ADDR (FLASH_SPI_REG_BASE+0x00000008)
+#define ADR_SRAM_ADDR (FLASH_SPI_REG_BASE+0x0000000c)
+#define ADR_LEN (FLASH_SPI_REG_BASE+0x00000010)
+#define ADR_SPI_PARAM (FLASH_SPI_REG_BASE+0x00000014)
+#define ADR_SPI_PARAM2 (FLASH_SPI_REG_BASE+0x00000018)
+#define ADR_CHECK_SUM_RESULT (FLASH_SPI_REG_BASE+0x0000001c)
+#define ADR_CHECK_SUM_IN_FILE (FLASH_SPI_REG_BASE+0x00000020)
+#define ADR_COMMAND_LEN (FLASH_SPI_REG_BASE+0x00000024)
+#define ADR_COMMAND_ADDR (FLASH_SPI_REG_BASE+0x00000028)
+#define ADR_DMA_ADR_SRC (DMA_REG_BASE+0x00000000)
+#define ADR_DMA_ADR_DST (DMA_REG_BASE+0x00000004)
+#define ADR_DMA_CTRL (DMA_REG_BASE+0x00000008)
+#define ADR_DMA_INT (DMA_REG_BASE+0x0000000c)
+#define ADR_DMA_FILL_CONST (DMA_REG_BASE+0x00000010)
+#define ADR_PMU_0 (CSR_PMU_BASE+0x00000000)
+#define ADR_PMU_1 (CSR_PMU_BASE+0x00000004)
+#define ADR_PMU_2 (CSR_PMU_BASE+0x00000008)
+#define ADR_PMU_3 (CSR_PMU_BASE+0x0000000c)
+#define ADR_RTC_1 (CSR_RTC_BASE+0x00000000)
+#define ADR_RTC_2 (CSR_RTC_BASE+0x00000004)
+#define ADR_RTC_3W (CSR_RTC_BASE+0x00000008)
+#define ADR_RTC_3R (CSR_RTC_BASE+0x00000008)
+#define ADR_RTC_4 (CSR_RTC_BASE+0x0000000c)
+#define ADR_RTC_RAM (RTC_RAM_BASE+0x00000000)
+#define ADR_D2_DMA_ADR_SRC (D2_DMA_REG_BASE+0x00000000)
+#define ADR_D2_DMA_ADR_DST (D2_DMA_REG_BASE+0x00000004)
+#define ADR_D2_DMA_CTRL (D2_DMA_REG_BASE+0x00000008)
+#define ADR_D2_DMA_INT (D2_DMA_REG_BASE+0x0000000c)
+#define ADR_D2_DMA_FILL_CONST (D2_DMA_REG_BASE+0x00000010)
+#define ADR_CONTROL (HCI_REG_BASE+0x00000000)
+#define ADR_SDIO_WAKE_MODE (HCI_REG_BASE+0x00000004)
+#define ADR_TX_FLOW_0 (HCI_REG_BASE+0x00000008)
+#define ADR_TX_FLOW_1 (HCI_REG_BASE+0x0000000c)
+#define ADR_THREASHOLD (HCI_REG_BASE+0x00000018)
+#define ADR_TXFID_INCREASE (HCI_REG_BASE+0x00000020)
+#define ADR_GLOBAL_SEQUENCE (HCI_REG_BASE+0x00000028)
+#define ADR_HCI_TX_RX_INFO_SIZE (HCI_REG_BASE+0x00000030)
+#define ADR_HCI_TX_INFO_CLEAR (HCI_REG_BASE+0x00000034)
+#define ADR_TX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000050)
+#define ADR_TX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000054)
+#define ADR_RX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000060)
+#define ADR_RX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000064)
+#define ADR_PACKET_COUNTER_INFO_0 (HCI_REG_BASE+0x00000070)
+#define ADR_PACKET_COUNTER_INFO_1 (HCI_REG_BASE+0x00000074)
+#define ADR_PACKET_COUNTER_INFO_2 (HCI_REG_BASE+0x00000078)
+#define ADR_PACKET_COUNTER_INFO_3 (HCI_REG_BASE+0x0000007c)
+#define ADR_PACKET_COUNTER_INFO_4 (HCI_REG_BASE+0x00000080)
+#define ADR_PACKET_COUNTER_INFO_5 (HCI_REG_BASE+0x00000084)
+#define ADR_PACKET_COUNTER_INFO_6 (HCI_REG_BASE+0x00000088)
+#define ADR_PACKET_COUNTER_INFO_7 (HCI_REG_BASE+0x0000008c)
+#define ADR_SDIO_TX_RX_FAIL_COUNTER_0 (HCI_REG_BASE+0x00000090)
+#define ADR_SDIO_TX_RX_FAIL_COUNTER_1 (HCI_REG_BASE+0x00000094)
+#define ADR_HCI_STATE_DEBUG_MODE_0 (HCI_REG_BASE+0x000000a0)
+#define ADR_HCI_STATE_DEBUG_MODE_1 (HCI_REG_BASE+0x000000a4)
+#define ADR_HCI_STATE_DEBUG_MODE_2 (HCI_REG_BASE+0x000000a8)
+#define ADR_HCI_STATE_DEBUG_MODE_3 (HCI_REG_BASE+0x000000ac)
+#define ADR_HCI_STATE_DEBUG_MODE_4 (HCI_REG_BASE+0x000000b0)
+#define ADR_HCI_STATE_DEBUG_MODE_5 (HCI_REG_BASE+0x000000b4)
+#define ADR_HCI_STATE_DEBUG_MODE_6 (HCI_REG_BASE+0x000000b8)
+#define ADR_HCI_STATE_DEBUG_MODE_7 (HCI_REG_BASE+0x000000bc)
+#define ADR_HCI_STATE_DEBUG_MODE_8 (HCI_REG_BASE+0x000000c0)
+#define ADR_HCI_STATE_DEBUG_MODE_9 (HCI_REG_BASE+0x000000c4)
+#define ADR_HCI_STATE_DEBUG_MODE_10 (HCI_REG_BASE+0x000000c8)
+#define ADR_CS_START_ADDR (CO_REG_BASE+0x00000000)
+#define ADR_CS_ADD_LEN (CO_REG_BASE+0x00000004)
+#define ADR_CS_CMD (CO_REG_BASE+0x00000008)
+#define ADR_CS_INI_BUF (CO_REG_BASE+0x0000000c)
+#define ADR_CS_PSEUDO_BUF (CO_REG_BASE+0x00000010)
+#define ADR_CS_CHECK_SUM (CO_REG_BASE+0x00000014)
+#define ADR_RAND_EN (CO_REG_BASE+0x00000018)
+#define ADR_RAND_NUM (CO_REG_BASE+0x0000001c)
+#define ADR_MUL_OP1 (CO_REG_BASE+0x00000060)
+#define ADR_MUL_OP2 (CO_REG_BASE+0x00000064)
+#define ADR_MUL_ANS0 (CO_REG_BASE+0x00000068)
+#define ADR_MUL_ANS1 (CO_REG_BASE+0x0000006c)
+#define ADR_DMA_RDATA (CO_REG_BASE+0x00000070)
+#define ADR_DMA_WDATA (CO_REG_BASE+0x00000074)
+#define ADR_DMA_LEN (CO_REG_BASE+0x00000078)
+#define ADR_DMA_CLR (CO_REG_BASE+0x0000007c)
+#define ADR_NAV_DATA (CO_REG_BASE+0x00000080)
+#define ADR_CO_NAV (CO_REG_BASE+0x00000084)
+#define ADR_SHA_DST_ADDR (CO_REG_BASE+0x000000a0)
+#define ADR_SHA_SRC_ADDR (CO_REG_BASE+0x000000a4)
+#define ADR_SHA_SETTING (CO_REG_BASE+0x000000a8)
+#define ADR_EFUSE_CLK_FREQ (EFS_REG_BASE+0x00000000)
+#define ADR_EFUSE_LDO_TIME (EFS_REG_BASE+0x00000004)
+#define ADR_EFUSE_AHB_RDATA_0 (EFS_REG_BASE+0x00000008)
+#define ADR_EFUSE_WDATA_0 (EFS_REG_BASE+0x00000008)
+#define ADR_EFUSE_AHB_RDATA_1 (EFS_REG_BASE+0x0000000c)
+#define ADR_EFUSE_WDATA_1 (EFS_REG_BASE+0x0000000c)
+#define ADR_EFUSE_AHB_RDATA_2 (EFS_REG_BASE+0x00000010)
+#define ADR_EFUSE_WDATA_2 (EFS_REG_BASE+0x00000010)
+#define ADR_EFUSE_AHB_RDATA_3 (EFS_REG_BASE+0x00000014)
+#define ADR_EFUSE_WDATA_3 (EFS_REG_BASE+0x00000014)
+#define ADR_EFUSE_AHB_RDATA_4 (EFS_REG_BASE+0x00000018)
+#define ADR_EFUSE_WDATA_4 (EFS_REG_BASE+0x00000018)
+#define ADR_EFUSE_AHB_RDATA_5 (EFS_REG_BASE+0x0000001c)
+#define ADR_EFUSE_WDATA_5 (EFS_REG_BASE+0x0000001c)
+#define ADR_EFUSE_AHB_RDATA_6 (EFS_REG_BASE+0x00000020)
+#define ADR_EFUSE_WDATA_6 (EFS_REG_BASE+0x00000020)
+#define ADR_EFUSE_AHB_RDATA_7 (EFS_REG_BASE+0x00000024)
+#define ADR_EFUSE_WDATA_7 (EFS_REG_BASE+0x00000024)
+#define ADR_EFUSE_SPI_RD0_EN (EFS_REG_BASE+0x00000028)
+#define ADR_EFUSE_SPI_RD1_EN (EFS_REG_BASE+0x0000002c)
+#define ADR_EFUSE_SPI_RD2_EN (EFS_REG_BASE+0x00000030)
+#define ADR_EFUSE_SPI_RD3_EN (EFS_REG_BASE+0x00000034)
+#define ADR_EFUSE_SPI_RD4_EN (EFS_REG_BASE+0x00000038)
+#define ADR_EFUSE_SPI_RD5_EN (EFS_REG_BASE+0x0000003c)
+#define ADR_EFUSE_SPI_RD6_EN (EFS_REG_BASE+0x00000040)
+#define ADR_EFUSE_SPI_RD7_EN (EFS_REG_BASE+0x00000044)
+#define ADR_EFUSE_SPI_BUSY (EFS_REG_BASE+0x00000048)
+#define ADR_EFUSE_SPI_RDATA_0 (EFS_REG_BASE+0x0000004c)
+#define ADR_EFUSE_SPI_RDATA_1 (EFS_REG_BASE+0x00000050)
+#define ADR_EFUSE_SPI_RDATA_2 (EFS_REG_BASE+0x00000054)
+#define ADR_EFUSE_SPI_RDATA_3 (EFS_REG_BASE+0x00000058)
+#define ADR_EFUSE_SPI_RDATA_4 (EFS_REG_BASE+0x0000005c)
+#define ADR_EFUSE_SPI_RDATA_5 (EFS_REG_BASE+0x00000060)
+#define ADR_EFUSE_SPI_RDATA_6 (EFS_REG_BASE+0x00000064)
+#define ADR_EFUSE_SPI_RDATA_7 (EFS_REG_BASE+0x00000068)
+#define ADR_SMS4_CFG1 (SMS4_REG_BASE+0x00000000)
+#define ADR_SMS4_CFG2 (SMS4_REG_BASE+0x00000004)
+#define ADR_SMS4_MODE1 (SMS4_REG_BASE+0x00000008)
+#define ADR_SMS4_TRIG (SMS4_REG_BASE+0x00000010)
+#define ADR_SMS4_STATUS1 (SMS4_REG_BASE+0x00000014)
+#define ADR_SMS4_STATUS2 (SMS4_REG_BASE+0x00000018)
+#define ADR_SMS4_DATA_IN0 (SMS4_REG_BASE+0x00000020)
+#define ADR_SMS4_DATA_IN1 (SMS4_REG_BASE+0x00000024)
+#define ADR_SMS4_DATA_IN2 (SMS4_REG_BASE+0x00000028)
+#define ADR_SMS4_DATA_IN3 (SMS4_REG_BASE+0x0000002c)
+#define ADR_SMS4_DATA_OUT0 (SMS4_REG_BASE+0x00000030)
+#define ADR_SMS4_DATA_OUT1 (SMS4_REG_BASE+0x00000034)
+#define ADR_SMS4_DATA_OUT2 (SMS4_REG_BASE+0x00000038)
+#define ADR_SMS4_DATA_OUT3 (SMS4_REG_BASE+0x0000003c)
+#define ADR_SMS4_KEY_0 (SMS4_REG_BASE+0x00000040)
+#define ADR_SMS4_KEY_1 (SMS4_REG_BASE+0x00000044)
+#define ADR_SMS4_KEY_2 (SMS4_REG_BASE+0x00000048)
+#define ADR_SMS4_KEY_3 (SMS4_REG_BASE+0x0000004c)
+#define ADR_SMS4_MODE_IV0 (SMS4_REG_BASE+0x00000050)
+#define ADR_SMS4_MODE_IV1 (SMS4_REG_BASE+0x00000054)
+#define ADR_SMS4_MODE_IV2 (SMS4_REG_BASE+0x00000058)
+#define ADR_SMS4_MODE_IV3 (SMS4_REG_BASE+0x0000005c)
+#define ADR_SMS4_OFB_ENC0 (SMS4_REG_BASE+0x00000060)
+#define ADR_SMS4_OFB_ENC1 (SMS4_REG_BASE+0x00000064)
+#define ADR_SMS4_OFB_ENC2 (SMS4_REG_BASE+0x00000068)
+#define ADR_SMS4_OFB_ENC3 (SMS4_REG_BASE+0x0000006c)
+#define ADR_MRX_MCAST_TB0_0 (MRX_REG_BASE+0x00000000)
+#define ADR_MRX_MCAST_TB0_1 (MRX_REG_BASE+0x00000004)
+#define ADR_MRX_MCAST_MK0_0 (MRX_REG_BASE+0x00000008)
+#define ADR_MRX_MCAST_MK0_1 (MRX_REG_BASE+0x0000000c)
+#define ADR_MRX_MCAST_CTRL0 (MRX_REG_BASE+0x00000010)
+#define ADR_MRX_MCAST_TB1_0 (MRX_REG_BASE+0x00000014)
+#define ADR_MRX_MCAST_TB1_1 (MRX_REG_BASE+0x00000018)
+#define ADR_MRX_MCAST_MK1_0 (MRX_REG_BASE+0x0000001c)
+#define ADR_MRX_MCAST_MK1_1 (MRX_REG_BASE+0x00000020)
+#define ADR_MRX_MCAST_CTRL1 (MRX_REG_BASE+0x00000024)
+#define ADR_MRX_MCAST_TB2_0 (MRX_REG_BASE+0x00000028)
+#define ADR_MRX_MCAST_TB2_1 (MRX_REG_BASE+0x0000002c)
+#define ADR_MRX_MCAST_MK2_0 (MRX_REG_BASE+0x00000030)
+#define ADR_MRX_MCAST_MK2_1 (MRX_REG_BASE+0x00000034)
+#define ADR_MRX_MCAST_CTRL2 (MRX_REG_BASE+0x00000038)
+#define ADR_MRX_MCAST_TB3_0 (MRX_REG_BASE+0x0000003c)
+#define ADR_MRX_MCAST_TB3_1 (MRX_REG_BASE+0x00000040)
+#define ADR_MRX_MCAST_MK3_0 (MRX_REG_BASE+0x00000044)
+#define ADR_MRX_MCAST_MK3_1 (MRX_REG_BASE+0x00000048)
+#define ADR_MRX_MCAST_CTRL3 (MRX_REG_BASE+0x0000004c)
+#define ADR_MRX_PHY_INFO (MRX_REG_BASE+0x00000050)
+#define ADR_MRX_BA_DBG (MRX_REG_BASE+0x00000054)
+#define ADR_MRX_FLT_TB0 (MRX_REG_BASE+0x00000070)
+#define ADR_MRX_FLT_TB1 (MRX_REG_BASE+0x00000074)
+#define ADR_MRX_FLT_TB2 (MRX_REG_BASE+0x00000078)
+#define ADR_MRX_FLT_TB3 (MRX_REG_BASE+0x0000007c)
+#define ADR_MRX_FLT_TB4 (MRX_REG_BASE+0x00000080)
+#define ADR_MRX_FLT_TB5 (MRX_REG_BASE+0x00000084)
+#define ADR_MRX_FLT_TB6 (MRX_REG_BASE+0x00000088)
+#define ADR_MRX_FLT_TB7 (MRX_REG_BASE+0x0000008c)
+#define ADR_MRX_FLT_TB8 (MRX_REG_BASE+0x00000090)
+#define ADR_MRX_FLT_TB9 (MRX_REG_BASE+0x00000094)
+#define ADR_MRX_FLT_TB10 (MRX_REG_BASE+0x00000098)
+#define ADR_MRX_FLT_TB11 (MRX_REG_BASE+0x0000009c)
+#define ADR_MRX_FLT_TB12 (MRX_REG_BASE+0x000000a0)
+#define ADR_MRX_FLT_TB13 (MRX_REG_BASE+0x000000a4)
+#define ADR_MRX_FLT_TB14 (MRX_REG_BASE+0x000000a8)
+#define ADR_MRX_FLT_TB15 (MRX_REG_BASE+0x000000ac)
+#define ADR_MRX_FLT_EN0 (MRX_REG_BASE+0x000000b0)
+#define ADR_MRX_FLT_EN1 (MRX_REG_BASE+0x000000b4)
+#define ADR_MRX_FLT_EN2 (MRX_REG_BASE+0x000000b8)
+#define ADR_MRX_FLT_EN3 (MRX_REG_BASE+0x000000bc)
+#define ADR_MRX_FLT_EN4 (MRX_REG_BASE+0x000000c0)
+#define ADR_MRX_FLT_EN5 (MRX_REG_BASE+0x000000c4)
+#define ADR_MRX_FLT_EN6 (MRX_REG_BASE+0x000000c8)
+#define ADR_MRX_FLT_EN7 (MRX_REG_BASE+0x000000cc)
+#define ADR_MRX_FLT_EN8 (MRX_REG_BASE+0x000000d0)
+#define ADR_MRX_LEN_FLT (MRX_REG_BASE+0x000000d4)
+#define ADR_RX_FLOW_DATA (MRX_REG_BASE+0x000000e0)
+#define ADR_RX_FLOW_MNG (MRX_REG_BASE+0x000000e4)
+#define ADR_RX_FLOW_CTRL (MRX_REG_BASE+0x000000e8)
+#define ADR_RX_TIME_STAMP_CFG (MRX_REG_BASE+0x000000ec)
+#define ADR_DBG_FF_FULL (MRX_REG_BASE+0x000000f0)
+#define ADR_DBG_WFF_FULL (MRX_REG_BASE+0x000000f4)
+#define ADR_DBG_MB_FULL (MRX_REG_BASE+0x000000f8)
+#define ADR_BA_CTRL (MRX_REG_BASE+0x00000100)
+#define ADR_BA_TA_0 (MRX_REG_BASE+0x00000104)
+#define ADR_BA_TA_1 (MRX_REG_BASE+0x00000108)
+#define ADR_BA_TID (MRX_REG_BASE+0x0000010c)
+#define ADR_BA_ST_SEQ (MRX_REG_BASE+0x00000110)
+#define ADR_BA_SB0 (MRX_REG_BASE+0x00000114)
+#define ADR_BA_SB1 (MRX_REG_BASE+0x00000118)
+#define ADR_MRX_WATCH_DOG (MRX_REG_BASE+0x0000011c)
+#define ADR_ACK_GEN_EN (MRX_REG_BASE+0x00000120)
+#define ADR_ACK_GEN_PARA (MRX_REG_BASE+0x00000124)
+#define ADR_ACK_GEN_RA_0 (MRX_REG_BASE+0x00000128)
+#define ADR_ACK_GEN_RA_1 (MRX_REG_BASE+0x0000012c)
+#define ADR_MIB_LEN_FAIL (MRX_REG_BASE+0x00000130)
+#define ADR_TRAP_HW_ID (MRX_REG_BASE+0x00000134)
+#define ADR_ID_IN_USE (MRX_REG_BASE+0x00000138)
+#define ADR_MRX_ERR (MRX_REG_BASE+0x0000013c)
+#define ADR_WSID0_TID0_RX_SEQ (MRX_REG_BASE+0x00000140)
+#define ADR_WSID0_TID1_RX_SEQ (MRX_REG_BASE+0x00000144)
+#define ADR_WSID0_TID2_RX_SEQ (MRX_REG_BASE+0x00000148)
+#define ADR_WSID0_TID3_RX_SEQ (MRX_REG_BASE+0x0000014c)
+#define ADR_WSID0_TID4_RX_SEQ (MRX_REG_BASE+0x00000150)
+#define ADR_WSID0_TID5_RX_SEQ (MRX_REG_BASE+0x00000154)
+#define ADR_WSID0_TID6_RX_SEQ (MRX_REG_BASE+0x00000158)
+#define ADR_WSID0_TID7_RX_SEQ (MRX_REG_BASE+0x0000015c)
+#define ADR_WSID1_TID0_RX_SEQ (MRX_REG_BASE+0x00000170)
+#define ADR_WSID1_TID1_RX_SEQ (MRX_REG_BASE+0x00000174)
+#define ADR_WSID1_TID2_RX_SEQ (MRX_REG_BASE+0x00000178)
+#define ADR_WSID1_TID3_RX_SEQ (MRX_REG_BASE+0x0000017c)
+#define ADR_WSID1_TID4_RX_SEQ (MRX_REG_BASE+0x00000180)
+#define ADR_WSID1_TID5_RX_SEQ (MRX_REG_BASE+0x00000184)
+#define ADR_WSID1_TID6_RX_SEQ (MRX_REG_BASE+0x00000188)
+#define ADR_WSID1_TID7_RX_SEQ (MRX_REG_BASE+0x0000018c)
+#define ADR_HDR_ADDR_SEL (MRX_REG_BASE+0x00000190)
+#define ADR_FRAME_TYPE_CNTR_SET (MRX_REG_BASE+0x00000194)
+#define ADR_PHY_INFO (AMPDU_REG_BASE+0x00000000)
+#define ADR_AMPDU_SIG (AMPDU_REG_BASE+0x00000004)
+#define ADR_MIB_AMPDU (AMPDU_REG_BASE+0x00000008)
+#define ADR_LEN_FLT (AMPDU_REG_BASE+0x0000000c)
+#define ADR_MIB_DELIMITER (AMPDU_REG_BASE+0x00000010)
+#define ADR_MTX_INT_STS (MT_REG_CSR_BASE+0x00000000)
+#define ADR_MTX_INT_EN (MT_REG_CSR_BASE+0x00000004)
+#define ADR_MTX_MISC_EN (MT_REG_CSR_BASE+0x00000008)
+#define ADR_MTX_EDCCA_TOUT (MT_REG_CSR_BASE+0x00000010)
+#define ADR_MTX_BCN_INT_STS (MT_REG_CSR_BASE+0x000000a0)
+#define ADR_MTX_BCN_EN_INT (MT_REG_CSR_BASE+0x000000a4)
+#define ADR_MTX_BCN_EN_MISC (MT_REG_CSR_BASE+0x000000a8)
+#define ADR_MTX_BCN_MISC (MT_REG_CSR_BASE+0x000000ac)
+#define ADR_MTX_BCN_PRD (MT_REG_CSR_BASE+0x000000b0)
+#define ADR_MTX_BCN_TSF_L (MT_REG_CSR_BASE+0x000000b4)
+#define ADR_MTX_BCN_TSF_U (MT_REG_CSR_BASE+0x000000b8)
+#define ADR_MTX_BCN_CFG0 (MT_REG_CSR_BASE+0x000000bc)
+#define ADR_MTX_BCN_CFG1 (MT_REG_CSR_BASE+0x000000c0)
+#define ADR_MTX_STATUS (MT_REG_CSR_BASE+0x000000cc)
+#define ADR_MTX_DBG_CTRL (MT_REG_CSR_BASE+0x000000d0)
+#define ADR_MTX_DBG_DAT0 (MT_REG_CSR_BASE+0x000000d4)
+#define ADR_MTX_DBG_DAT1 (MT_REG_CSR_BASE+0x000000d8)
+#define ADR_MTX_DBG_DAT2 (MT_REG_CSR_BASE+0x000000dc)
+#define ADR_MTX_DUR_TOUT (MT_REG_CSR_BASE+0x000000e0)
+#define ADR_MTX_DUR_IFS (MT_REG_CSR_BASE+0x000000e4)
+#define ADR_MTX_DUR_SIFS_G (MT_REG_CSR_BASE+0x000000e8)
+#define ADR_MTX_DBG_DAT3 (MT_REG_CSR_BASE+0x000000ec)
+#define ADR_MTX_NAV (MT_REG_CSR_BASE+0x000000f0)
+#define ADR_MTX_MIB_WSID0 (MT_REG_CSR_BASE+0x000000f4)
+#define ADR_MTX_MIB_WSID1 (MT_REG_CSR_BASE+0x000000f8)
+#define ADR_MTX_DBG_DAT4 (MT_REG_CSR_BASE+0x000000fc)
+#define ADR_TXQ0_MTX_Q_MISC_EN (TXQ0_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ0_MTX_Q_AIFSN (TXQ0_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ0_MTX_Q_BKF_CNT (TXQ0_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ0_MTX_Q_RC_LIMIT (TXQ0_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ0_MTX_Q_ID_MAP_L (TXQ0_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ0_MTX_Q_TXOP_CH_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ0_MTX_Q_TXOP_OV_THD (TXQ0_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ1_MTX_Q_MISC_EN (TXQ1_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ1_MTX_Q_AIFSN (TXQ1_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ1_MTX_Q_BKF_CNT (TXQ1_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ1_MTX_Q_RC_LIMIT (TXQ1_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ1_MTX_Q_ID_MAP_L (TXQ1_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ1_MTX_Q_TXOP_CH_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ1_MTX_Q_TXOP_OV_THD (TXQ1_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ2_MTX_Q_MISC_EN (TXQ2_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ2_MTX_Q_AIFSN (TXQ2_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ2_MTX_Q_BKF_CNT (TXQ2_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ2_MTX_Q_RC_LIMIT (TXQ2_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ2_MTX_Q_ID_MAP_L (TXQ2_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ2_MTX_Q_TXOP_CH_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ2_MTX_Q_TXOP_OV_THD (TXQ2_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ3_MTX_Q_MISC_EN (TXQ3_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ3_MTX_Q_AIFSN (TXQ3_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ3_MTX_Q_BKF_CNT (TXQ3_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ3_MTX_Q_RC_LIMIT (TXQ3_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ3_MTX_Q_ID_MAP_L (TXQ3_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ3_MTX_Q_TXOP_CH_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ3_MTX_Q_TXOP_OV_THD (TXQ3_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_TXQ4_MTX_Q_MISC_EN (TXQ4_MT_Q_REG_CSR_BASE+0x00000000)
+#define ADR_TXQ4_MTX_Q_AIFSN (TXQ4_MT_Q_REG_CSR_BASE+0x00000004)
+#define ADR_TXQ4_MTX_Q_BKF_CNT (TXQ4_MT_Q_REG_CSR_BASE+0x00000008)
+#define ADR_TXQ4_MTX_Q_RC_LIMIT (TXQ4_MT_Q_REG_CSR_BASE+0x0000000c)
+#define ADR_TXQ4_MTX_Q_ID_MAP_L (TXQ4_MT_Q_REG_CSR_BASE+0x00000010)
+#define ADR_TXQ4_MTX_Q_TXOP_CH_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000014)
+#define ADR_TXQ4_MTX_Q_TXOP_OV_THD (TXQ4_MT_Q_REG_CSR_BASE+0x00000018)
+#define ADR_WSID0 (HIF_INFO_BASE+0x00000000)
+#define ADR_PEER_MAC0_0 (HIF_INFO_BASE+0x00000004)
+#define ADR_PEER_MAC0_1 (HIF_INFO_BASE+0x00000008)
+#define ADR_TX_ACK_POLICY_0_0 (HIF_INFO_BASE+0x0000000c)
+#define ADR_TX_SEQ_CTRL_0_0 (HIF_INFO_BASE+0x00000010)
+#define ADR_TX_ACK_POLICY_0_1 (HIF_INFO_BASE+0x00000014)
+#define ADR_TX_SEQ_CTRL_0_1 (HIF_INFO_BASE+0x00000018)
+#define ADR_TX_ACK_POLICY_0_2 (HIF_INFO_BASE+0x0000001c)
+#define ADR_TX_SEQ_CTRL_0_2 (HIF_INFO_BASE+0x00000020)
+#define ADR_TX_ACK_POLICY_0_3 (HIF_INFO_BASE+0x00000024)
+#define ADR_TX_SEQ_CTRL_0_3 (HIF_INFO_BASE+0x00000028)
+#define ADR_TX_ACK_POLICY_0_4 (HIF_INFO_BASE+0x0000002c)
+#define ADR_TX_SEQ_CTRL_0_4 (HIF_INFO_BASE+0x00000030)
+#define ADR_TX_ACK_POLICY_0_5 (HIF_INFO_BASE+0x00000034)
+#define ADR_TX_SEQ_CTRL_0_5 (HIF_INFO_BASE+0x00000038)
+#define ADR_TX_ACK_POLICY_0_6 (HIF_INFO_BASE+0x0000003c)
+#define ADR_TX_SEQ_CTRL_0_6 (HIF_INFO_BASE+0x00000040)
+#define ADR_TX_ACK_POLICY_0_7 (HIF_INFO_BASE+0x00000044)
+#define ADR_TX_SEQ_CTRL_0_7 (HIF_INFO_BASE+0x00000048)
+#define ADR_WSID1 (HIF_INFO_BASE+0x00000050)
+#define ADR_PEER_MAC1_0 (HIF_INFO_BASE+0x00000054)
+#define ADR_PEER_MAC1_1 (HIF_INFO_BASE+0x00000058)
+#define ADR_TX_ACK_POLICY_1_0 (HIF_INFO_BASE+0x0000005c)
+#define ADR_TX_SEQ_CTRL_1_0 (HIF_INFO_BASE+0x00000060)
+#define ADR_TX_ACK_POLICY_1_1 (HIF_INFO_BASE+0x00000064)
+#define ADR_TX_SEQ_CTRL_1_1 (HIF_INFO_BASE+0x00000068)
+#define ADR_TX_ACK_POLICY_1_2 (HIF_INFO_BASE+0x0000006c)
+#define ADR_TX_SEQ_CTRL_1_2 (HIF_INFO_BASE+0x00000070)
+#define ADR_TX_ACK_POLICY_1_3 (HIF_INFO_BASE+0x00000074)
+#define ADR_TX_SEQ_CTRL_1_3 (HIF_INFO_BASE+0x00000078)
+#define ADR_TX_ACK_POLICY_1_4 (HIF_INFO_BASE+0x0000007c)
+#define ADR_TX_SEQ_CTRL_1_4 (HIF_INFO_BASE+0x00000080)
+#define ADR_TX_ACK_POLICY_1_5 (HIF_INFO_BASE+0x00000084)
+#define ADR_TX_SEQ_CTRL_1_5 (HIF_INFO_BASE+0x00000088)
+#define ADR_TX_ACK_POLICY_1_6 (HIF_INFO_BASE+0x0000008c)
+#define ADR_TX_SEQ_CTRL_1_6 (HIF_INFO_BASE+0x00000090)
+#define ADR_TX_ACK_POLICY_1_7 (HIF_INFO_BASE+0x00000094)
+#define ADR_TX_SEQ_CTRL_1_7 (HIF_INFO_BASE+0x00000098)
+#define ADR_INFO0 (PHY_RATE_INFO_BASE+0x00000000)
+#define ADR_INFO1 (PHY_RATE_INFO_BASE+0x00000004)
+#define ADR_INFO2 (PHY_RATE_INFO_BASE+0x00000008)
+#define ADR_INFO3 (PHY_RATE_INFO_BASE+0x0000000c)
+#define ADR_INFO4 (PHY_RATE_INFO_BASE+0x00000010)
+#define ADR_INFO5 (PHY_RATE_INFO_BASE+0x00000014)
+#define ADR_INFO6 (PHY_RATE_INFO_BASE+0x00000018)
+#define ADR_INFO7 (PHY_RATE_INFO_BASE+0x0000001c)
+#define ADR_INFO8 (PHY_RATE_INFO_BASE+0x00000020)
+#define ADR_INFO9 (PHY_RATE_INFO_BASE+0x00000024)
+#define ADR_INFO10 (PHY_RATE_INFO_BASE+0x00000028)
+#define ADR_INFO11 (PHY_RATE_INFO_BASE+0x0000002c)
+#define ADR_INFO12 (PHY_RATE_INFO_BASE+0x00000030)
+#define ADR_INFO13 (PHY_RATE_INFO_BASE+0x00000034)
+#define ADR_INFO14 (PHY_RATE_INFO_BASE+0x00000038)
+#define ADR_INFO15 (PHY_RATE_INFO_BASE+0x0000003c)
+#define ADR_INFO16 (PHY_RATE_INFO_BASE+0x00000040)
+#define ADR_INFO17 (PHY_RATE_INFO_BASE+0x00000044)
+#define ADR_INFO18 (PHY_RATE_INFO_BASE+0x00000048)
+#define ADR_INFO19 (PHY_RATE_INFO_BASE+0x0000004c)
+#define ADR_INFO20 (PHY_RATE_INFO_BASE+0x00000050)
+#define ADR_INFO21 (PHY_RATE_INFO_BASE+0x00000054)
+#define ADR_INFO22 (PHY_RATE_INFO_BASE+0x00000058)
+#define ADR_INFO23 (PHY_RATE_INFO_BASE+0x0000005c)
+#define ADR_INFO24 (PHY_RATE_INFO_BASE+0x00000060)
+#define ADR_INFO25 (PHY_RATE_INFO_BASE+0x00000064)
+#define ADR_INFO26 (PHY_RATE_INFO_BASE+0x00000068)
+#define ADR_INFO27 (PHY_RATE_INFO_BASE+0x0000006c)
+#define ADR_INFO28 (PHY_RATE_INFO_BASE+0x00000070)
+#define ADR_INFO29 (PHY_RATE_INFO_BASE+0x00000074)
+#define ADR_INFO30 (PHY_RATE_INFO_BASE+0x00000078)
+#define ADR_INFO31 (PHY_RATE_INFO_BASE+0x0000007c)
+#define ADR_INFO32 (PHY_RATE_INFO_BASE+0x00000080)
+#define ADR_INFO33 (PHY_RATE_INFO_BASE+0x00000084)
+#define ADR_INFO34 (PHY_RATE_INFO_BASE+0x00000088)
+#define ADR_INFO35 (PHY_RATE_INFO_BASE+0x0000008c)
+#define ADR_INFO36 (PHY_RATE_INFO_BASE+0x00000090)
+#define ADR_INFO37 (PHY_RATE_INFO_BASE+0x00000094)
+#define ADR_INFO38 (PHY_RATE_INFO_BASE+0x00000098)
+#define ADR_INFO_MASK (PHY_RATE_INFO_BASE+0x0000009c)
+#define ADR_INFO_RATE_OFFSET (PHY_RATE_INFO_BASE+0x000000a0)
+#define ADR_INFO_IDX_ADDR (PHY_RATE_INFO_BASE+0x000000a4)
+#define ADR_INFO_LEN_ADDR (PHY_RATE_INFO_BASE+0x000000a8)
+#define ADR_IC_TIME_TAG_0 (PHY_RATE_INFO_BASE+0x000000ac)
+#define ADR_IC_TIME_TAG_1 (PHY_RATE_INFO_BASE+0x000000b0)
+#define ADR_PACKET_ID_ALLOCATION_PRIORITY (PHY_RATE_INFO_BASE+0x000000b4)
+#define ADR_MAC_MODE (MAC_GLB_SET_BASE+0x00000000)
+#define ADR_ALL_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000004)
+#define ADR_ENG_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000008)
+#define ADR_CSR_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x0000000c)
+#define ADR_MAC_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000010)
+#define ADR_MAC_ENGINE_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000014)
+#define ADR_MAC_CSR_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000018)
+#define ADR_GLBLE_SET (MAC_GLB_SET_BASE+0x0000001c)
+#define ADR_REASON_TRAP0 (MAC_GLB_SET_BASE+0x00000020)
+#define ADR_REASON_TRAP1 (MAC_GLB_SET_BASE+0x00000024)
+#define ADR_BSSID_0 (MAC_GLB_SET_BASE+0x00000028)
+#define ADR_BSSID_1 (MAC_GLB_SET_BASE+0x0000002c)
+#define ADR_SCRT_STATE (MAC_GLB_SET_BASE+0x0000002c)
+#define ADR_STA_MAC_0 (MAC_GLB_SET_BASE+0x00000030)
+#define ADR_STA_MAC_1 (MAC_GLB_SET_BASE+0x00000034)
+#define ADR_SCRT_SET (MAC_GLB_SET_BASE+0x00000038)
+#define ADR_BTCX0 (BTCX_REG_BASE+0x00000000)
+#define ADR_BTCX1 (BTCX_REG_BASE+0x00000004)
+#define ADR_SWITCH_CTL (BTCX_REG_BASE+0x00000008)
+#define ADR_MIB_EN (MIB_REG_BASE+0x00000000)
+#define ADR_MTX_WSID0_SUCC (MIB_REG_BASE+0x00000118)
+#define ADR_MTX_WSID0_FRM (MIB_REG_BASE+0x00000128)
+#define ADR_MTX_WSID0_RETRY (MIB_REG_BASE+0x00000138)
+#define ADR_MTX_WSID0_TOTAL (MIB_REG_BASE+0x00000148)
+#define ADR_MTX_GROUP (MIB_REG_BASE+0x0000016c)
+#define ADR_MTX_FAIL (MIB_REG_BASE+0x00000170)
+#define ADR_MTX_RETRY (MIB_REG_BASE+0x00000174)
+#define ADR_MTX_MULTI_RETRY (MIB_REG_BASE+0x00000178)
+#define ADR_MTX_RTS_SUCCESS (MIB_REG_BASE+0x0000017c)
+#define ADR_MTX_RTS_FAIL (MIB_REG_BASE+0x00000180)
+#define ADR_MTX_ACK_FAIL (MIB_REG_BASE+0x00000184)
+#define ADR_MTX_FRM (MIB_REG_BASE+0x00000188)
+#define ADR_MTX_ACK_TX (MIB_REG_BASE+0x0000018c)
+#define ADR_MTX_CTS_TX (MIB_REG_BASE+0x00000190)
+#define ADR_MRX_DUP_FRM (MIB_REG_BASE+0x00000194)
+#define ADR_MRX_FRG_FRM (MIB_REG_BASE+0x00000198)
+#define ADR_MRX_GROUP_FRM (MIB_REG_BASE+0x0000019c)
+#define ADR_MRX_FCS_ERR (MIB_REG_BASE+0x000001a0)
+#define ADR_MRX_FCS_SUCC (MIB_REG_BASE+0x000001a4)
+#define ADR_MRX_MISS (MIB_REG_BASE+0x000001a8)
+#define ADR_MRX_ALC_FAIL (MIB_REG_BASE+0x000001ac)
+#define ADR_MRX_DAT_NTF (MIB_REG_BASE+0x000001b0)
+#define ADR_MRX_RTS_NTF (MIB_REG_BASE+0x000001b4)
+#define ADR_MRX_CTS_NTF (MIB_REG_BASE+0x000001b8)
+#define ADR_MRX_ACK_NTF (MIB_REG_BASE+0x000001bc)
+#define ADR_MRX_BA_NTF (MIB_REG_BASE+0x000001c0)
+#define ADR_MRX_DATA_NTF (MIB_REG_BASE+0x000001c4)
+#define ADR_MRX_MNG_NTF (MIB_REG_BASE+0x000001c8)
+#define ADR_MRX_DAT_CRC_NTF (MIB_REG_BASE+0x000001cc)
+#define ADR_MRX_BAR_NTF (MIB_REG_BASE+0x000001d0)
+#define ADR_MRX_MB_MISS (MIB_REG_BASE+0x000001d4)
+#define ADR_MRX_NIDLE_MISS (MIB_REG_BASE+0x000001d8)
+#define ADR_MRX_CSR_NTF (MIB_REG_BASE+0x000001dc)
+#define ADR_DBG_Q0_FRM_SUCCESS (MIB_REG_BASE+0x00000218)
+#define ADR_DBG_Q0_FRM_FAIL (MIB_REG_BASE+0x0000021c)
+#define ADR_DBG_Q0_ACK_SUCCESS (MIB_REG_BASE+0x00000220)
+#define ADR_DBG_Q0_ACK_FAIL (MIB_REG_BASE+0x00000224)
+#define ADR_DBG_Q1_FRM_SUCCESS (MIB_REG_BASE+0x00000268)
+#define ADR_DBG_Q1_FRM_FAIL (MIB_REG_BASE+0x0000026c)
+#define ADR_DBG_Q1_ACK_SUCCESS (MIB_REG_BASE+0x00000270)
+#define ADR_DBG_Q1_ACK_FAIL (MIB_REG_BASE+0x00000274)
+#define ADR_DBG_Q2_FRM_SUCCESS (MIB_REG_BASE+0x00000318)
+#define ADR_DBG_Q2_FRM_FAIL (MIB_REG_BASE+0x0000031c)
+#define ADR_DBG_Q2_ACK_SUCCESS (MIB_REG_BASE+0x00000320)
+#define ADR_DBG_Q2_ACK_FAIL (MIB_REG_BASE+0x00000324)
+#define ADR_DBG_Q3_FRM_SUCCESS (MIB_REG_BASE+0x00000368)
+#define ADR_DBG_Q3_FRM_FAIL (MIB_REG_BASE+0x0000036c)
+#define ADR_DBG_Q3_ACK_SUCCESS (MIB_REG_BASE+0x00000370)
+#define ADR_DBG_Q3_ACK_FAIL (MIB_REG_BASE+0x00000374)
+#define ADR_MIB_SCRT_TKIP0 (MIB_REG_BASE+0x00000418)
+#define ADR_MIB_SCRT_TKIP1 (MIB_REG_BASE+0x0000041c)
+#define ADR_MIB_SCRT_TKIP2 (MIB_REG_BASE+0x00000420)
+#define ADR_MIB_SCRT_CCMP0 (MIB_REG_BASE+0x00000424)
+#define ADR_MIB_SCRT_CCMP1 (MIB_REG_BASE+0x00000428)
+#define ADR_DBG_LEN_CRC_FAIL (MIB_REG_BASE+0x00000468)
+#define ADR_DBG_LEN_ALC_FAIL (MIB_REG_BASE+0x0000046c)
+#define ADR_DBG_AMPDU_PASS (MIB_REG_BASE+0x00000470)
+#define ADR_DBG_AMPDU_FAIL (MIB_REG_BASE+0x00000474)
+#define ADR_ID_ALC_FAIL1 (MIB_REG_BASE+0x00000478)
+#define ADR_ID_ALC_FAIL2 (MIB_REG_BASE+0x0000047c)
+#define ADR_CBR_HARD_WIRE_PIN_REGISTER (CBR_A_REG_BASE+0x00110000)
+#define ADR_CBR_MANUAL_ENABLE_REGISTER (CBR_A_REG_BASE+0x00110004)
+#define ADR_CBR_LDO_REGISTER (CBR_A_REG_BASE+0x00110008)
+#define ADR_CBR_ABB_REGISTER_1 (CBR_A_REG_BASE+0x0011000c)
+#define ADR_CBR_ABB_REGISTER_2 (CBR_A_REG_BASE+0x00110010)
+#define ADR_CBR_TX_FE_REGISTER (CBR_A_REG_BASE+0x00110014)
+#define ADR_CBR_RX_FE_REGISTER_1 (CBR_A_REG_BASE+0x00110018)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1 (CBR_A_REG_BASE+0x0011001c)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2 (CBR_A_REG_BASE+0x00110020)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3 (CBR_A_REG_BASE+0x00110024)
+#define ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4 (CBR_A_REG_BASE+0x00110028)
+#define ADR_CBR_RX_FSM_REGISTER (CBR_A_REG_BASE+0x0011002c)
+#define ADR_CBR_RX_ADC_REGISTER (CBR_A_REG_BASE+0x00110030)
+#define ADR_CBR_TX_DAC_REGISTER (CBR_A_REG_BASE+0x00110034)
+#define ADR_CBR_SX_ENABLE_RGISTER (CBR_A_REG_BASE+0x00110038)
+#define ADR_CBR_SYN_RGISTER_1 (CBR_A_REG_BASE+0x0011003c)
+#define ADR_CBR_SYN_RGISTER_2 (CBR_A_REG_BASE+0x00110040)
+#define ADR_CBR_SYN_PFD_CHP (CBR_A_REG_BASE+0x00110044)
+#define ADR_CBR_SYN_VCO_LOBF (CBR_A_REG_BASE+0x00110048)
+#define ADR_CBR_SYN_DIV_SDM_XOSC (CBR_A_REG_BASE+0x0011004c)
+#define ADR_CBR_SYN_LCK1 (CBR_A_REG_BASE+0x00110050)
+#define ADR_CBR_SYN_LCK2 (CBR_A_REG_BASE+0x00110054)
+#define ADR_CBR_DPLL_VCO_REGISTER (CBR_A_REG_BASE+0x00110058)
+#define ADR_CBR_DPLL_CP_PFD_REGISTER (CBR_A_REG_BASE+0x0011005c)
+#define ADR_CBR_DPLL_DIVIDER_REGISTER (CBR_A_REG_BASE+0x00110060)
+#define ADR_CBR_DCOC_IDAC_REGISTER1 (CBR_A_REG_BASE+0x00110064)
+#define ADR_CBR_DCOC_IDAC_REGISTER2 (CBR_A_REG_BASE+0x00110068)
+#define ADR_CBR_DCOC_IDAC_REGISTER3 (CBR_A_REG_BASE+0x0011006c)
+#define ADR_CBR_DCOC_IDAC_REGISTER4 (CBR_A_REG_BASE+0x00110070)
+#define ADR_CBR_DCOC_IDAC_REGISTER5 (CBR_A_REG_BASE+0x00110074)
+#define ADR_CBR_DCOC_IDAC_REGISTER6 (CBR_A_REG_BASE+0x00110078)
+#define ADR_CBR_DCOC_IDAC_REGISTER7 (CBR_A_REG_BASE+0x0011007c)
+#define ADR_CBR_DCOC_IDAC_REGISTER8 (CBR_A_REG_BASE+0x00110080)
+#define ADR_CBR_RCAL_REGISTER (CBR_A_REG_BASE+0x00110084)
+#define ADR_CBR_MANUAL_REGISTER (CBR_A_REG_BASE+0x00110088)
+#define ADR_CBR_TRX_DUMMY_REGISTER (CBR_A_REG_BASE+0x0011008c)
+#define ADR_CBR_SX_DUMMY_REGISTER (CBR_A_REG_BASE+0x00110090)
+#define ADR_CBR_READ_ONLY_FLAGS_1 (CBR_A_REG_BASE+0x00110094)
+#define ADR_CBR_READ_ONLY_FLAGS_2 (CBR_A_REG_BASE+0x00110098)
+#define ADR_CBR_RG_PKT_GEN_0 (CBR_A_REG_BASE+0x00120080)
+#define ADR_CBR_RG_PKT_GEN_1 (CBR_A_REG_BASE+0x00120084)
+#define ADR_CBR_RG_PKT_GEN_2 (CBR_A_REG_BASE+0x00120088)
+#define ADR_CBR_RG_INTEGRATION (CBR_A_REG_BASE+0x00120090)
+#define ADR_CBR_RG_PKT_GEN_TXCNT (CBR_A_REG_BASE+0x00120094)
+#define ADR_CBR_PATTERN_GEN (CBR_A_REG_BASE+0x001203f8)
+#define ADR_MB_CPU_INT (MB_REG_BASE+0x00000004)
+#define ADR_CPU_ID_TB0 (MB_REG_BASE+0x00000008)
+#define ADR_CPU_ID_TB1 (MB_REG_BASE+0x0000000c)
+#define ADR_CH0_TRIG_1 (MB_REG_BASE+0x00000010)
+#define ADR_CH0_TRIG_0 (MB_REG_BASE+0x00000010)
+#define ADR_CH0_PRI_TRIG (MB_REG_BASE+0x00000014)
+#define ADR_MCU_STATUS (MB_REG_BASE+0x00000018)
+#define ADR_RD_IN_FFCNT1 (MB_REG_BASE+0x0000001c)
+#define ADR_RD_IN_FFCNT2 (MB_REG_BASE+0x00000020)
+#define ADR_RD_FFIN_FULL (MB_REG_BASE+0x00000024)
+#define ADR_MBOX_HALT_CFG (MB_REG_BASE+0x0000002c)
+#define ADR_MB_DBG_CFG1 (MB_REG_BASE+0x00000030)
+#define ADR_MB_DBG_CFG2 (MB_REG_BASE+0x00000034)
+#define ADR_MB_DBG_CFG3 (MB_REG_BASE+0x00000038)
+#define ADR_MB_DBG_CFG4 (MB_REG_BASE+0x0000003c)
+#define ADR_MB_OUT_QUEUE_CFG (MB_REG_BASE+0x00000040)
+#define ADR_MB_OUT_QUEUE_FLUSH (MB_REG_BASE+0x00000044)
+#define ADR_RD_FFOUT_CNT1 (MB_REG_BASE+0x00000048)
+#define ADR_RD_FFOUT_CNT2 (MB_REG_BASE+0x0000004c)
+#define ADR_RD_FFOUT_CNT3 (MB_REG_BASE+0x00000050)
+#define ADR_RD_FFOUT_FULL (MB_REG_BASE+0x00000054)
+#define ADR_MB_THRESHOLD6 (MB_REG_BASE+0x0000006c)
+#define ADR_MB_THRESHOLD7 (MB_REG_BASE+0x00000070)
+#define ADR_MB_THRESHOLD8 (MB_REG_BASE+0x00000074)
+#define ADR_MB_THRESHOLD9 (MB_REG_BASE+0x00000078)
+#define ADR_MB_THRESHOLD10 (MB_REG_BASE+0x0000007c)
+#define ADR_MB_TRASH_CFG (MB_REG_BASE+0x00000080)
+#define ADR_MB_IN_FF_FLUSH (MB_REG_BASE+0x00000084)
+#define ADR_CPU_ID_TB2 (MB_REG_BASE+0x00000088)
+#define ADR_CPU_ID_TB3 (MB_REG_BASE+0x0000008c)
+#define ADR_PHY_IQ_LOG_CFG0 (MB_REG_BASE+0x00000090)
+#define ADR_PHY_IQ_LOG_CFG1 (MB_REG_BASE+0x00000094)
+#define ADR_PHY_IQ_LOG_LEN (MB_REG_BASE+0x00000098)
+#define ADR_PHY_IQ_LOG_PTR (MB_REG_BASE+0x0000009c)
+#define ADR_WR_ALC (ID_MNG_REG_BASE+0x00000000)
+#define ADR_GETID (ID_MNG_REG_BASE+0x00000000)
+#define ADR_CH_STA_PRI (ID_MNG_REG_BASE+0x00000004)
+#define ADR_RD_ID0 (ID_MNG_REG_BASE+0x00000008)
+#define ADR_RD_ID1 (ID_MNG_REG_BASE+0x0000000c)
+#define ADR_IMD_CFG (ID_MNG_REG_BASE+0x00000010)
+#define ADR_IMD_STA (ID_MNG_REG_BASE+0x00000014)
+#define ADR_ALC_STA (ID_MNG_REG_BASE+0x00000018)
+#define ADR_TRX_ID_COUNT (ID_MNG_REG_BASE+0x0000001c)
+#define ADR_TRX_ID_THRESHOLD (ID_MNG_REG_BASE+0x00000020)
+#define ADR_TX_ID0 (ID_MNG_REG_BASE+0x00000024)
+#define ADR_TX_ID1 (ID_MNG_REG_BASE+0x00000028)
+#define ADR_RX_ID0 (ID_MNG_REG_BASE+0x0000002c)
+#define ADR_RX_ID1 (ID_MNG_REG_BASE+0x00000030)
+#define ADR_RTN_STA (ID_MNG_REG_BASE+0x00000034)
+#define ADR_ID_LEN_THREADSHOLD1 (ID_MNG_REG_BASE+0x00000038)
+#define ADR_ID_LEN_THREADSHOLD2 (ID_MNG_REG_BASE+0x0000003c)
+#define ADR_CH_ARB_PRI (ID_MNG_REG_BASE+0x00000040)
+#define ADR_TX_ID_REMAIN_STATUS (ID_MNG_REG_BASE+0x00000044)
+#define ADR_ID_INFO_STA (ID_MNG_REG_BASE+0x00000048)
+#define ADR_TX_LIMIT_INTR (ID_MNG_REG_BASE+0x0000004c)
+#define ADR_TX_ID_ALL_INFO (ID_MNG_REG_BASE+0x00000050)
+#define ADR_RD_ID2 (ID_MNG_REG_BASE+0x00000054)
+#define ADR_RD_ID3 (ID_MNG_REG_BASE+0x00000058)
+#define ADR_TX_ID2 (ID_MNG_REG_BASE+0x0000005c)
+#define ADR_TX_ID3 (ID_MNG_REG_BASE+0x00000060)
+#define ADR_RX_ID2 (ID_MNG_REG_BASE+0x00000064)
+#define ADR_RX_ID3 (ID_MNG_REG_BASE+0x00000068)
+#define ADR_TX_ID_ALL_INFO2 (ID_MNG_REG_BASE+0x0000006c)
+#define ADR_TX_ID_ALL_INFO_A (ID_MNG_REG_BASE+0x00000070)
+#define ADR_TX_ID_ALL_INFO_B (ID_MNG_REG_BASE+0x00000074)
+#define ADR_TX_ID_REMAIN_STATUS2 (ID_MNG_REG_BASE+0x00000078)
+#define ADR_ALC_ID_INFO (ID_MNG_REG_BASE+0x0000007c)
+#define ADR_ALC_ID_INF1 (ID_MNG_REG_BASE+0x00000080)
+#define ADR_PHY_EN_0 (CSR_PHY_BASE+0x00000000)
+#define ADR_PHY_EN_1 (CSR_PHY_BASE+0x00000004)
+#define ADR_SVN_VERSION_REG (CSR_PHY_BASE+0x00000008)
+#define ADR_PHY_PKT_GEN_0 (CSR_PHY_BASE+0x0000000c)
+#define ADR_PHY_PKT_GEN_1 (CSR_PHY_BASE+0x00000010)
+#define ADR_PHY_PKT_GEN_2 (CSR_PHY_BASE+0x00000014)
+#define ADR_PHY_PKT_GEN_3 (CSR_PHY_BASE+0x00000018)
+#define ADR_PHY_PKT_GEN_4 (CSR_PHY_BASE+0x0000001c)
+#define ADR_PHY_REG_00 (CSR_PHY_BASE+0x00000020)
+#define ADR_PHY_REG_01 (CSR_PHY_BASE+0x0000002c)
+#define ADR_PHY_REG_02_AGC (CSR_PHY_BASE+0x00000030)
+#define ADR_PHY_REG_03_AGC (CSR_PHY_BASE+0x00000034)
+#define ADR_PHY_REG_04_AGC (CSR_PHY_BASE+0x00000038)
+#define ADR_PHY_REG_05_AGC (CSR_PHY_BASE+0x0000003c)
+#define ADR_PHY_REG_06_11B_DAGC (CSR_PHY_BASE+0x00000040)
+#define ADR_PHY_REG_07_11B_DAGC (CSR_PHY_BASE+0x00000044)
+#define ADR_PHY_REG_08_11GN_DAGC (CSR_PHY_BASE+0x00000048)
+#define ADR_PHY_REG_09_11GN_DAGC (CSR_PHY_BASE+0x0000004c)
+#define ADR_PHY_READ_REG_00_DIG_PWR (CSR_PHY_BASE+0x00000050)
+#define ADR_PHY_READ_REG_01_RF_GAIN_PWR (CSR_PHY_BASE+0x00000054)
+#define ADR_PHY_READ_REG_02_RF_GAIN_PWR (CSR_PHY_BASE+0x00000058)
+#define ADR_PHY_READ_REG_03_RF_GAIN_PWR (CSR_PHY_BASE+0x0000005c)
+#define ADR_PHY_REG_10_TX_DES (CSR_PHY_BASE+0x00000060)
+#define ADR_PHY_REG_11_TX_DES (CSR_PHY_BASE+0x00000064)
+#define ADR_PHY_REG_12_TX_DES (CSR_PHY_BASE+0x00000068)
+#define ADR_PHY_REG_13_RX_DES (CSR_PHY_BASE+0x0000006c)
+#define ADR_PHY_REG_14_RX_DES (CSR_PHY_BASE+0x00000070)
+#define ADR_PHY_REG_15_RX_DES (CSR_PHY_BASE+0x00000074)
+#define ADR_PHY_REG_16_TX_DES_EXCP (CSR_PHY_BASE+0x00000078)
+#define ADR_PHY_REG_17_TX_DES_EXCP (CSR_PHY_BASE+0x0000007c)
+#define ADR_PHY_REG_18_RSSI_SNR (CSR_PHY_BASE+0x00000080)
+#define ADR_PHY_REG_19_DAC_MANUAL (CSR_PHY_BASE+0x00000084)
+#define ADR_PHY_REG_20_MRX_CNT (CSR_PHY_BASE+0x00000088)
+#define ADR_PHY_REG_21_TRX_RAMP (CSR_PHY_BASE+0x00000094)
+#define ADR_PHY_REG_22_TRX_RAMP (CSR_PHY_BASE+0x00000098)
+#define ADR_PHY_REG_23_ANT (CSR_PHY_BASE+0x0000009c)
+#define ADR_PHY_REG_24_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a0)
+#define ADR_PHY_REG_25_MTX_LEN_CNT (CSR_PHY_BASE+0x000000a4)
+#define ADR_PHY_REG_26_MRX_LEN_CNT (CSR_PHY_BASE+0x000000a8)
+#define ADR_PHY_REG_27_MRX_LEN_CNT (CSR_PHY_BASE+0x000000ac)
+#define ADR_PHY_READ_REG_04 (CSR_PHY_BASE+0x000000b0)
+#define ADR_PHY_READ_REG_05 (CSR_PHY_BASE+0x000000b4)
+#define ADR_PHY_REG_28_BIST (CSR_PHY_BASE+0x000000b8)
+#define ADR_PHY_READ_REG_06_BIST (CSR_PHY_BASE+0x000000d8)
+#define ADR_PHY_READ_REG_07_BIST (CSR_PHY_BASE+0x000000f0)
+#define ADR_PHY_REG_29_MTRX_MAC (CSR_PHY_BASE+0x000000fc)
+#define ADR_PHY_READ_REG_08_MTRX_MAC (CSR_PHY_BASE+0x00000100)
+#define ADR_PHY_READ_REG_09_MTRX_MAC (CSR_PHY_BASE+0x00000104)
+#define ADR_PHY_REG_30_TX_UP_FIL (CSR_PHY_BASE+0x00000108)
+#define ADR_PHY_REG_31_TX_UP_FIL (CSR_PHY_BASE+0x0000010c)
+#define ADR_PHY_REG_32_TX_UP_FIL (CSR_PHY_BASE+0x00000110)
+#define ADR_PHY_READ_TBUS (CSR_PHY_BASE+0x000003fc)
+#define ADR_TX_11B_FIL_COEF_00 (CSR_PHY_BASE+0x00001000)
+#define ADR_TX_11B_FIL_COEF_01 (CSR_PHY_BASE+0x00001004)
+#define ADR_TX_11B_FIL_COEF_02 (CSR_PHY_BASE+0x00001008)
+#define ADR_TX_11B_FIL_COEF_03 (CSR_PHY_BASE+0x0000100c)
+#define ADR_TX_11B_FIL_COEF_04 (CSR_PHY_BASE+0x00001010)
+#define ADR_TX_11B_FIL_COEF_05 (CSR_PHY_BASE+0x00001014)
+#define ADR_TX_11B_FIL_COEF_06 (CSR_PHY_BASE+0x00001018)
+#define ADR_TX_11B_FIL_COEF_07 (CSR_PHY_BASE+0x0000101c)
+#define ADR_TX_11B_FIL_COEF_08 (CSR_PHY_BASE+0x00001020)
+#define ADR_TX_11B_FIL_COEF_09 (CSR_PHY_BASE+0x00001024)
+#define ADR_TX_11B_FIL_COEF_10 (CSR_PHY_BASE+0x00001028)
+#define ADR_TX_11B_FIL_COEF_11 (CSR_PHY_BASE+0x0000102c)
+#define ADR_TX_11B_FIL_COEF_12 (CSR_PHY_BASE+0x00001030)
+#define ADR_TX_11B_FIL_COEF_13 (CSR_PHY_BASE+0x00001034)
+#define ADR_TX_11B_FIL_COEF_14 (CSR_PHY_BASE+0x00001038)
+#define ADR_TX_11B_FIL_COEF_15 (CSR_PHY_BASE+0x0000103c)
+#define ADR_TX_11B_FIL_COEF_16 (CSR_PHY_BASE+0x00001040)
+#define ADR_TX_11B_FIL_COEF_17 (CSR_PHY_BASE+0x00001044)
+#define ADR_TX_11B_FIL_COEF_18 (CSR_PHY_BASE+0x00001048)
+#define ADR_TX_11B_FIL_COEF_19 (CSR_PHY_BASE+0x0000104c)
+#define ADR_TX_11B_FIL_COEF_20 (CSR_PHY_BASE+0x00001050)
+#define ADR_TX_11B_FIL_COEF_21 (CSR_PHY_BASE+0x00001054)
+#define ADR_TX_11B_FIL_COEF_22 (CSR_PHY_BASE+0x00001058)
+#define ADR_TX_11B_FIL_COEF_23 (CSR_PHY_BASE+0x0000105c)
+#define ADR_TX_11B_FIL_COEF_24 (CSR_PHY_BASE+0x00001060)
+#define ADR_TX_11B_FIL_COEF_25 (CSR_PHY_BASE+0x00001064)
+#define ADR_TX_11B_FIL_COEF_26 (CSR_PHY_BASE+0x00001068)
+#define ADR_TX_11B_FIL_COEF_27 (CSR_PHY_BASE+0x0000106c)
+#define ADR_TX_11B_FIL_COEF_28 (CSR_PHY_BASE+0x00001070)
+#define ADR_TX_11B_FIL_COEF_29 (CSR_PHY_BASE+0x00001074)
+#define ADR_TX_11B_FIL_COEF_30 (CSR_PHY_BASE+0x00001078)
+#define ADR_TX_11B_FIL_COEF_31 (CSR_PHY_BASE+0x0000107c)
+#define ADR_TX_11B_FIL_COEF_32 (CSR_PHY_BASE+0x00001080)
+#define ADR_TX_11B_FIL_COEF_33 (CSR_PHY_BASE+0x00001084)
+#define ADR_TX_11B_FIL_COEF_34 (CSR_PHY_BASE+0x00001088)
+#define ADR_TX_11B_FIL_COEF_35 (CSR_PHY_BASE+0x0000108c)
+#define ADR_TX_11B_FIL_COEF_36 (CSR_PHY_BASE+0x00001090)
+#define ADR_TX_11B_FIL_COEF_37 (CSR_PHY_BASE+0x00001094)
+#define ADR_TX_11B_FIL_COEF_38 (CSR_PHY_BASE+0x00001098)
+#define ADR_TX_11B_FIL_COEF_39 (CSR_PHY_BASE+0x0000109c)
+#define ADR_TX_11B_FIL_COEF_40 (CSR_PHY_BASE+0x000010a0)
+#define ADR_TX_11B_PLCP (CSR_PHY_BASE+0x000010a4)
+#define ADR_TX_11B_RAMP (CSR_PHY_BASE+0x000010b4)
+#define ADR_TX_11B_EN_CNT_RST_N (CSR_PHY_BASE+0x000010d4)
+#define ADR_TX_11B_EN_CNT (CSR_PHY_BASE+0x000010d8)
+#define ADR_TX_11B_PKT_GEN_CNT (CSR_PHY_BASE+0x00001c00)
+#define ADR_RX_11B_DES_DLY (CSR_PHY_BASE+0x00002000)
+#define ADR_RX_11B_CCA_0 (CSR_PHY_BASE+0x00002004)
+#define ADR_RX_11B_CCA_1 (CSR_PHY_BASE+0x00002008)
+#define ADR_RX_11B_TR_KP_KI_0 (CSR_PHY_BASE+0x0000200c)
+#define ADR_RX_11B_TR_KP_KI_1 (CSR_PHY_BASE+0x00002010)
+#define ADR_RX_11B_CE_CNT_THRESHOLD (CSR_PHY_BASE+0x00002014)
+#define ADR_RX_11B_CE_MU_0 (CSR_PHY_BASE+0x00002018)
+#define ADR_RX_11B_CE_MU_1 (CSR_PHY_BASE+0x0000201c)
+#define ADR_RX_11B_EQ_MU_0 (CSR_PHY_BASE+0x00002020)
+#define ADR_RX_11B_EQ_MU_1 (CSR_PHY_BASE+0x00002024)
+#define ADR_RX_11B_EQ_CR_KP_KI (CSR_PHY_BASE+0x00002028)
+#define ADR_RX_11B_LPF_RATE (CSR_PHY_BASE+0x0000202c)
+#define ADR_RX_11B_CIT_CNT_THRESHOLD (CSR_PHY_BASE+0x00002030)
+#define ADR_RX_11B_EQ_CH_MAIN_TAP (CSR_PHY_BASE+0x00002034)
+#define ADR_RX_11B_SEARCH_CNT_TH (CSR_PHY_BASE+0x0000209c)
+#define ADR_RX_11B_CCA_CONTROL (CSR_PHY_BASE+0x000020a0)
+#define ADR_RX_11B_FREQUENCY_OFFSET (CSR_PHY_BASE+0x000023d4)
+#define ADR_RX_11B_SNR_RSSI (CSR_PHY_BASE+0x000023d8)
+#define ADR_RX_11B_SFD_CRC_CNT (CSR_PHY_BASE+0x000023e4)
+#define ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT (CSR_PHY_BASE+0x000023e8)
+#define ADR_RX_11B_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000023ec)
+#define ADR_RX_11B_SFD_FILED_0 (CSR_PHY_BASE+0x000023f0)
+#define ADR_RX_11B_SFD_FIELD_1 (CSR_PHY_BASE+0x000023f4)
+#define ADR_RX_11B_PKT_STAT_EN (CSR_PHY_BASE+0x000023f8)
+#define ADR_RX_11B_SOFT_RST (CSR_PHY_BASE+0x000023fc)
+#define ADR_TX_11GN_RAMP (CSR_PHY_BASE+0x000030a4)
+#define ADR_TX_11GN_PLCP (CSR_PHY_BASE+0x000030b8)
+#define ADR_TX_11GN_PKT_GEN_CNT (CSR_PHY_BASE+0x00003c00)
+#define ADR_TX_11GN_PLCP_CRC_ERR_CNT (CSR_PHY_BASE+0x00003c08)
+#define ADR_RX_11GN_DES_DLY (CSR_PHY_BASE+0x00004000)
+#define ADR_RX_11GN_TR_0 (CSR_PHY_BASE+0x00004004)
+#define ADR_RX_11GN_TR_1 (CSR_PHY_BASE+0x00004008)
+#define ADR_RX_11GN_TR_2 (CSR_PHY_BASE+0x0000400c)
+#define ADR_RX_11GN_CCA_0 (CSR_PHY_BASE+0x00004010)
+#define ADR_RX_11GN_CCA_1 (CSR_PHY_BASE+0x00004014)
+#define ADR_RX_11GN_CCA_2 (CSR_PHY_BASE+0x00004018)
+#define ADR_RX_11GN_CCA_FFT_SCALE (CSR_PHY_BASE+0x0000401c)
+#define ADR_RX_11GN_SOFT_DEMAP_0 (CSR_PHY_BASE+0x00004020)
+#define ADR_RX_11GN_SOFT_DEMAP_1 (CSR_PHY_BASE+0x00004024)
+#define ADR_RX_11GN_SOFT_DEMAP_2 (CSR_PHY_BASE+0x00004028)
+#define ADR_RX_11GN_SOFT_DEMAP_3 (CSR_PHY_BASE+0x0000402c)
+#define ADR_RX_11GN_SOFT_DEMAP_4 (CSR_PHY_BASE+0x00004030)
+#define ADR_RX_11GN_SOFT_DEMAP_5 (CSR_PHY_BASE+0x00004034)
+#define ADR_RX_11GN_SYM_BOUND_0 (CSR_PHY_BASE+0x00004038)
+#define ADR_RX_11GN_SYM_BOUND_1 (CSR_PHY_BASE+0x0000409c)
+#define ADR_RX_11GN_CCA_PWR (CSR_PHY_BASE+0x000040c0)
+#define ADR_RX_11GN_CCA_CNT (CSR_PHY_BASE+0x000040c4)
+#define ADR_RX_11GN_CCA_ATCOR_RE_CHECK (CSR_PHY_BASE+0x000040c8)
+#define ADR_RX_11GN_VTB_TB (CSR_PHY_BASE+0x00004130)
+#define ADR_RX_11GN_ERR_UPDATE (CSR_PHY_BASE+0x00004164)
+#define ADR_RX_11GN_SHORT_GI (CSR_PHY_BASE+0x00004180)
+#define ADR_RX_11GN_CHANNEL_UPDATE (CSR_PHY_BASE+0x00004188)
+#define ADR_RX_11GN_PKT_FORMAT_0 (CSR_PHY_BASE+0x00004190)
+#define ADR_RX_11GN_PKT_FORMAT_1 (CSR_PHY_BASE+0x00004194)
+#define ADR_RX_11GN_TX_TIME (CSR_PHY_BASE+0x00004380)
+#define ADR_RX_11GN_STBC_TR_KP_KI (CSR_PHY_BASE+0x00004384)
+#define ADR_RX_11GN_BIST_0 (CSR_PHY_BASE+0x00004388)
+#define ADR_RX_11GN_BIST_1 (CSR_PHY_BASE+0x0000438c)
+#define ADR_RX_11GN_BIST_2 (CSR_PHY_BASE+0x000043c0)
+#define ADR_RX_11GN_BIST_3 (CSR_PHY_BASE+0x000043c4)
+#define ADR_RX_11GN_BIST_4 (CSR_PHY_BASE+0x000043c8)
+#define ADR_RX_11GN_BIST_5 (CSR_PHY_BASE+0x000043cc)
+#define ADR_RX_11GN_SPECTRUM_ANALYZER (CSR_PHY_BASE+0x000043d4)
+#define ADR_RX_11GN_READ_0 (CSR_PHY_BASE+0x000043d8)
+#define ADR_RX_11GN_FREQ_OFFSET (CSR_PHY_BASE+0x000043dc)
+#define ADR_RX_11GN_SIGNAL_FIELD_0 (CSR_PHY_BASE+0x000043e0)
+#define ADR_RX_11GN_SIGNAL_FIELD_1 (CSR_PHY_BASE+0x000043e4)
+#define ADR_RX_11GN_PKT_ERR_CNT (CSR_PHY_BASE+0x000043e8)
+#define ADR_RX_11GN_PKT_CCA_AND_PKT_CNT (CSR_PHY_BASE+0x000043ec)
+#define ADR_RX_11GN_SERVICE_LENGTH_FIELD (CSR_PHY_BASE+0x000043f0)
+#define ADR_RX_11GN_RATE (CSR_PHY_BASE+0x000043f4)
+#define ADR_RX_11GN_STAT_EN (CSR_PHY_BASE+0x000043f8)
+#define ADR_RX_11GN_SOFT_RST (CSR_PHY_BASE+0x000043fc)
+#define ADR_RF_CONTROL_0 (CSR_PHY_BASE+0x00007000)
+#define ADR_RF_CONTROL_1 (CSR_PHY_BASE+0x00007004)
+#define ADR_TX_IQ_CONTROL_0 (CSR_PHY_BASE+0x00007040)
+#define ADR_TX_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007044)
+#define ADR_TX_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007048)
+#define ADR_TX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x0000704c)
+#define ADR_RX_COMPENSATION_CONTROL (CSR_PHY_BASE+0x00007050)
+#define ADR_RX_OBSERVATION_CIRCUIT_0 (CSR_PHY_BASE+0x00007058)
+#define ADR_RX_OBSERVATION_CIRCUIT_1 (CSR_PHY_BASE+0x0000705c)
+#define ADR_RX_OBSERVATION_CIRCUIT_2 (CSR_PHY_BASE+0x00007060)
+#define ADR_RX_OBSERVATION_CIRCUIT_3 (CSR_PHY_BASE+0x00007064)
+#define ADR_RF_IQ_CONTROL_0 (CSR_PHY_BASE+0x0000706c)
+#define ADR_RF_IQ_CONTROL_1 (CSR_PHY_BASE+0x00007070)
+#define ADR_RF_IQ_CONTROL_2 (CSR_PHY_BASE+0x00007074)
+#define ADR_RF_IQ_CONTROL_3 (CSR_PHY_BASE+0x00007078)
+#define ADR_DPD_CONTROL (CSR_PHY_BASE+0x0000711c)
+#define ADR_DPD_GAIN_TABLE_0 (CSR_PHY_BASE+0x00007120)
+#define ADR_DPD_GAIN_TABLE_1 (CSR_PHY_BASE+0x00007124)
+#define ADR_DPD_GAIN_TABLE_2 (CSR_PHY_BASE+0x00007128)
+#define ADR_DPD_GAIN_TABLE_3 (CSR_PHY_BASE+0x00007130)
+#define ADR_DPD_GAIN_TABLE_4 (CSR_PHY_BASE+0x00007134)
+#define ADR_DPD_GAIN_TABLE_5 (CSR_PHY_BASE+0x00007138)
+#define ADR_DPD_GAIN_TABLE_6 (CSR_PHY_BASE+0x0000713c)
+#define ADR_DPD_GAIN_TABLE_7 (CSR_PHY_BASE+0x00007140)
+#define ADR_DPD_GAIN_TABLE_8 (CSR_PHY_BASE+0x00007144)
+#define ADR_DPD_GAIN_TABLE_9 (CSR_PHY_BASE+0x00007148)
+#define ADR_DPD_GAIN_TABLE_A (CSR_PHY_BASE+0x0000714c)
+#define ADR_DPD_GAIN_TABLE_B (CSR_PHY_BASE+0x00007150)
+#define ADR_DPD_GAIN_TABLE_C (CSR_PHY_BASE+0x00007154)
+#define ADR_DPD_PH_TABLE_0 (CSR_PHY_BASE+0x00007170)
+#define ADR_DPD_PH_TABLE_1 (CSR_PHY_BASE+0x00007174)
+#define ADR_DPD_PH_TABLE_2 (CSR_PHY_BASE+0x00007178)
+#define ADR_DPD_PH_TABLE_3 (CSR_PHY_BASE+0x00007180)
+#define ADR_DPD_PH_TABLE_4 (CSR_PHY_BASE+0x00007184)
+#define ADR_DPD_PH_TABLE_5 (CSR_PHY_BASE+0x00007188)
+#define ADR_DPD_PH_TABLE_6 (CSR_PHY_BASE+0x0000718c)
+#define ADR_DPD_PH_TABLE_7 (CSR_PHY_BASE+0x00007190)
+#define ADR_DPD_PH_TABLE_8 (CSR_PHY_BASE+0x00007194)
+#define ADR_DPD_PH_TABLE_9 (CSR_PHY_BASE+0x00007198)
+#define ADR_DPD_PH_TABLE_A (CSR_PHY_BASE+0x0000719c)
+#define ADR_DPD_PH_TABLE_B (CSR_PHY_BASE+0x000071a0)
+#define ADR_DPD_PH_TABLE_C (CSR_PHY_BASE+0x000071a4)
+#define ADR_DPD_GAIN_ESTIMATION_0 (CSR_PHY_BASE+0x000071b0)
+#define ADR_DPD_GAIN_ESTIMATION_1 (CSR_PHY_BASE+0x000071b4)
+#define ADR_DPD_GAIN_ESTIMATION_2 (CSR_PHY_BASE+0x000071b8)
+#define ADR_TX_GAIN_FACTOR (CSR_PHY_BASE+0x000071bc)
+#define ADR_HARD_WIRE_PIN_REGISTER (CSR_RF_BASE+0x00000000)
+#define ADR_MANUAL_ENABLE_REGISTER (CSR_RF_BASE+0x00000004)
+#define ADR_LDO_REGISTER (CSR_RF_BASE+0x00000008)
+#define ADR_ABB_REGISTER_1 (CSR_RF_BASE+0x0000000c)
+#define ADR_ABB_REGISTER_2 (CSR_RF_BASE+0x00000010)
+#define ADR_TX_FE_REGISTER (CSR_RF_BASE+0x00000014)
+#define ADR_RX_FE_REGISTER_1 (CSR_RF_BASE+0x00000018)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_1 (CSR_RF_BASE+0x0000001c)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_2 (CSR_RF_BASE+0x00000020)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_3 (CSR_RF_BASE+0x00000024)
+#define ADR_RX_FE_GAIN_DECODER_REGISTER_4 (CSR_RF_BASE+0x00000028)
+#define ADR_RX_TX_FSM_REGISTER (CSR_RF_BASE+0x0000002c)
+#define ADR_RX_ADC_REGISTER (CSR_RF_BASE+0x00000030)
+#define ADR_TX_DAC_REGISTER (CSR_RF_BASE+0x00000034)
+#define ADR_SX_ENABLE_REGISTER (CSR_RF_BASE+0x00000038)
+#define ADR_SYN_REGISTER_1 (CSR_RF_BASE+0x0000003c)
+#define ADR_SYN_REGISTER_2 (CSR_RF_BASE+0x00000040)
+#define ADR_SYN_PFD_CHP (CSR_RF_BASE+0x00000044)
+#define ADR_SYN_VCO_LOBF (CSR_RF_BASE+0x00000048)
+#define ADR_SYN_DIV_SDM_XOSC (CSR_RF_BASE+0x0000004c)
+#define ADR_SYN_KVCO_XO_FINE_TUNE_CBANK (CSR_RF_BASE+0x00000050)
+#define ADR_SYN_LCK_VT (CSR_RF_BASE+0x00000054)
+#define ADR_DPLL_VCO_REGISTER (CSR_RF_BASE+0x00000058)
+#define ADR_DPLL_CP_PFD_REGISTER (CSR_RF_BASE+0x0000005c)
+#define ADR_DPLL_DIVIDER_REGISTER (CSR_RF_BASE+0x00000060)
+#define ADR_DCOC_IDAC_REGISTER1 (CSR_RF_BASE+0x00000064)
+#define ADR_DCOC_IDAC_REGISTER2 (CSR_RF_BASE+0x00000068)
+#define ADR_DCOC_IDAC_REGISTER3 (CSR_RF_BASE+0x0000006c)
+#define ADR_DCOC_IDAC_REGISTER4 (CSR_RF_BASE+0x00000070)
+#define ADR_DCOC_IDAC_REGISTER5 (CSR_RF_BASE+0x00000074)
+#define ADR_DCOC_IDAC_REGISTER6 (CSR_RF_BASE+0x00000078)
+#define ADR_DCOC_IDAC_REGISTER7 (CSR_RF_BASE+0x0000007c)
+#define ADR_DCOC_IDAC_REGISTER8 (CSR_RF_BASE+0x00000080)
+#define ADR_RCAL_REGISTER (CSR_RF_BASE+0x00000084)
+#define ADR_SX_LCK_BIN_REGISTERS_I (CSR_RF_BASE+0x00000088)
+#define ADR_TRX_DUMMY_REGISTER (CSR_RF_BASE+0x0000008c)
+#define ADR_SX_DUMMY_REGISTER (CSR_RF_BASE+0x00000090)
+#define ADR_READ_ONLY_FLAGS_1 (CSR_RF_BASE+0x00000094)
+#define ADR_READ_ONLY_FLAGS_2 (CSR_RF_BASE+0x00000098)
+#define ADR_DPLL_FB_DIVIDER_REGISTERS_I (CSR_RF_BASE+0x0000009c)
+#define ADR_DPLL_FB_DIVIDER_REGISTERS_II (CSR_RF_BASE+0x000000a0)
+#define ADR_SX_LCK_BIN_REGISTERS_II (CSR_RF_BASE+0x000000a4)
+#define ADR_RC_OSC_32K_CAL_REGISTERS (CSR_RF_BASE+0x000000a8)
+#define ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER (CSR_RF_BASE+0x000000ac)
+#define ADR_MMU_CTRL (MMU_REG_BASE+0x00000000)
+#define ADR_HS_CTRL (MMU_REG_BASE+0x00000004)
+#define ADR_CPU_POR0_7 (MMU_REG_BASE+0x00000008)
+#define ADR_CPU_POR8_F (MMU_REG_BASE+0x0000000c)
+#define ADR_REG_LEN_CTRL (MMU_REG_BASE+0x00000010)
+#define ADR_DMN_READ_BYPASS (MMU_REG_BASE+0x00000014)
+#define ADR_ALC_RLS_ABORT (MMU_REG_BASE+0x00000018)
+#define ADR_DEBUG_CTL (MMU_REG_BASE+0x00000020)
+#define ADR_DEBUG_OUT (MMU_REG_BASE+0x00000024)
+#define ADR_MMU_STATUS (MMU_REG_BASE+0x00000028)
+#define ADR_DMN_STATUS (MMU_REG_BASE+0x0000002c)
+#define ADR_TAG_STATUS (MMU_REG_BASE+0x00000030)
+#define ADR_DMN_MCU_STATUS (MMU_REG_BASE+0x00000034)
+#define ADR_MB_IDTBL_0_STATUS (MMU_REG_BASE+0x00000040)
+#define ADR_MB_IDTBL_1_STATUS (MMU_REG_BASE+0x00000044)
+#define ADR_MB_IDTBL_2_STATUS (MMU_REG_BASE+0x00000048)
+#define ADR_MB_IDTBL_3_STATUS (MMU_REG_BASE+0x0000004c)
+#define ADR_PKT_IDTBL_0_STATUS (MMU_REG_BASE+0x00000050)
+#define ADR_PKT_IDTBL_1_STATUS (MMU_REG_BASE+0x00000054)
+#define ADR_PKT_IDTBL_2_STATUS (MMU_REG_BASE+0x00000058)
+#define ADR_PKT_IDTBL_3_STATUS (MMU_REG_BASE+0x0000005c)
+#define ADR_DMN_IDTBL_0_STATUS (MMU_REG_BASE+0x00000060)
+#define ADR_DMN_IDTBL_1_STATUS (MMU_REG_BASE+0x00000064)
+#define ADR_DMN_IDTBL_2_STATUS (MMU_REG_BASE+0x00000068)
+#define ADR_DMN_IDTBL_3_STATUS (MMU_REG_BASE+0x0000006c)
+#define ADR_MB_NEQID_0_STATUS (MMU_REG_BASE+0x00000070)
+#define ADR_MB_NEQID_1_STATUS (MMU_REG_BASE+0x00000074)
+#define ADR_MB_NEQID_2_STATUS (MMU_REG_BASE+0x00000078)
+#define ADR_MB_NEQID_3_STATUS (MMU_REG_BASE+0x0000007c)
+#define ADR_PKT_NEQID_0_STATUS (MMU_REG_BASE+0x00000080)
+#define ADR_PKT_NEQID_1_STATUS (MMU_REG_BASE+0x00000084)
+#define ADR_PKT_NEQID_2_STATUS (MMU_REG_BASE+0x00000088)
+#define ADR_PKT_NEQID_3_STATUS (MMU_REG_BASE+0x0000008c)
+#define ADR_ALC_NOCHG_ID_STATUS (MMU_REG_BASE+0x00000090)
+#define ADR_TAG_SRAM0_F_STATUS_0 (MMU_REG_BASE+0x000000a0)
+#define ADR_TAG_SRAM0_F_STATUS_1 (MMU_REG_BASE+0x000000a4)
+#define ADR_TAG_SRAM0_F_STATUS_2 (MMU_REG_BASE+0x000000a8)
+#define ADR_TAG_SRAM0_F_STATUS_3 (MMU_REG_BASE+0x000000ac)
+#define ADR_TAG_SRAM0_F_STATUS_4 (MMU_REG_BASE+0x000000b0)
+#define ADR_TAG_SRAM0_F_STATUS_5 (MMU_REG_BASE+0x000000b4)
+#define ADR_TAG_SRAM0_F_STATUS_6 (MMU_REG_BASE+0x000000b8)
+#define ADR_TAG_SRAM0_F_STATUS_7 (MMU_REG_BASE+0x000000bc)
+#define GET_MCU_ENABLE (((REG32(ADR_BRG_SW_RST)) & 0x00000001 ) >> 0)
+#define GET_MAC_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000002 ) >> 1)
+#define GET_MCU_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000004 ) >> 2)
+#define GET_SDIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000008 ) >> 3)
+#define GET_SPI_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000010 ) >> 4)
+#define GET_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000020 ) >> 5)
+#define GET_DMA_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000040 ) >> 6)
+#define GET_WDT_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000080 ) >> 7)
+#define GET_I2C_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000100 ) >> 8)
+#define GET_INT_CTL_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000200 ) >> 9)
+#define GET_BTCX_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000400 ) >> 10)
+#define GET_GPIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000800 ) >> 11)
+#define GET_US0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00001000 ) >> 12)
+#define GET_US1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00002000 ) >> 13)
+#define GET_US2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00004000 ) >> 14)
+#define GET_US3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00008000 ) >> 15)
+#define GET_MS0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00010000 ) >> 16)
+#define GET_MS1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00020000 ) >> 17)
+#define GET_MS2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00040000 ) >> 18)
+#define GET_MS3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00080000 ) >> 19)
+#define GET_RF_BB_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00100000 ) >> 20)
+#define GET_SYS_ALL_RST (((REG32(ADR_BRG_SW_RST)) & 0x00200000 ) >> 21)
+#define GET_DAT_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00400000 ) >> 22)
+#define GET_I2C_MST_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00800000 ) >> 23)
+#define GET_RG_REBOOT (((REG32(ADR_BOOT)) & 0x00000001 ) >> 0)
+#define GET_TRAP_IMG_FLS (((REG32(ADR_BOOT)) & 0x00010000 ) >> 16)
+#define GET_TRAP_REBOOT (((REG32(ADR_BOOT)) & 0x00020000 ) >> 17)
+#define GET_TRAP_BOOT_FLS (((REG32(ADR_BOOT)) & 0x00040000 ) >> 18)
+#define GET_CHIP_ID_31_0 (((REG32(ADR_CHIP_ID_0)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_63_32 (((REG32(ADR_CHIP_ID_1)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_95_64 (((REG32(ADR_CHIP_ID_2)) & 0xffffffff ) >> 0)
+#define GET_CHIP_ID_127_96 (((REG32(ADR_CHIP_ID_3)) & 0xffffffff ) >> 0)
+#define GET_CK_SEL_1_0 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000003 ) >> 0)
+#define GET_CK_SEL_2 (((REG32(ADR_CLOCK_SELECTION)) & 0x00000004 ) >> 2)
+#define GET_SYS_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_MAC_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MCU_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000004 ) >> 2)
+#define GET_SDIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_SPI_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_UART_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_DMA_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_WDT_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
+#define GET_I2C_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000100 ) >> 8)
+#define GET_INT_CTL_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
+#define GET_BTCX_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_GPIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_US0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_US1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_US2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_US3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_MS0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00010000 ) >> 16)
+#define GET_MS1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00020000 ) >> 17)
+#define GET_MS2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00040000 ) >> 18)
+#define GET_MS3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00080000 ) >> 19)
+#define GET_BIST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00100000 ) >> 20)
+#define GET_I2C_MST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00800000 ) >> 23)
+#define GET_BTCX_CSR_CLK_EN (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_MCU_DBG_SEL (((REG32(ADR_MCU_DBG_SEL)) & 0x0000003f ) >> 0)
+#define GET_MCU_STOP_NOGRANT (((REG32(ADR_MCU_DBG_SEL)) & 0x00000100 ) >> 8)
+#define GET_MCU_STOP_ANYTIME (((REG32(ADR_MCU_DBG_SEL)) & 0x00000200 ) >> 9)
+#define GET_MCU_DBG_DATA (((REG32(ADR_MCU_DBG_DATA)) & 0xffffffff ) >> 0)
+#define GET_AHB_SW_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000001 ) >> 0)
+#define GET_AHB_ERR_RST (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000002 ) >> 1)
+#define GET_REG_AHB_DEBUG_MX (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000030 ) >> 4)
+#define GET_REG_PKT_W_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000100 ) >> 8)
+#define GET_REG_PKT_R_NBRT (((REG32(ADR_AHB_BRG_STATUS)) & 0x00000200 ) >> 9)
+#define GET_IQ_SRAM_SEL_0 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00001000 ) >> 12)
+#define GET_IQ_SRAM_SEL_1 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00002000 ) >> 13)
+#define GET_IQ_SRAM_SEL_2 (((REG32(ADR_AHB_BRG_STATUS)) & 0x00004000 ) >> 14)
+#define GET_AHB_STATUS (((REG32(ADR_AHB_BRG_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_PARALLEL_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000001 ) >> 0)
+#define GET_MBRUN (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000010 ) >> 4)
+#define GET_SHIFT_DR (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000100 ) >> 8)
+#define GET_MODE_REG_SI (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000200 ) >> 9)
+#define GET_SIMULATION_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000400 ) >> 10)
+#define GET_DBIST_MODE (((REG32(ADR_BIST_BIST_CTRL)) & 0x00000800 ) >> 11)
+#define GET_MODE_REG_IN (((REG32(ADR_BIST_MODE_REG_IN)) & 0x001fffff ) >> 0)
+#define GET_MODE_REG_OUT_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x001fffff ) >> 0)
+#define GET_MODE_REG_SO_MCU (((REG32(ADR_BIST_MODE_REG_OUT)) & 0x80000000 ) >> 31)
+#define GET_MONITOR_BUS_MCU_31_0 (((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0xffffffff ) >> 0)
+#define GET_MONITOR_BUS_MCU_33_32 (((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0x00000003 ) >> 0)
+#define GET_TB_ADR_SEL (((REG32(ADR_TB_ADR_SEL)) & 0x0000ffff ) >> 0)
+#define GET_TB_CS (((REG32(ADR_TB_ADR_SEL)) & 0x80000000 ) >> 31)
+#define GET_TB_RDATA (((REG32(ADR_TB_RDATA)) & 0xffffffff ) >> 0)
+#define GET_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000001 ) >> 0)
+#define GET_DATA_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000010 ) >> 4)
+#define GET_AHB_ILL_ADDR (((REG32(ADR_AHB_ILL_ADDR)) & 0xffffffff ) >> 0)
+#define GET_AHB_FEN_ADDR (((REG32(ADR_AHB_FEN_ADDR)) & 0xffffffff ) >> 0)
+#define GET_ILL_ADDR_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000001 ) >> 0)
+#define GET_FENCE_HIT_CLR (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000002 ) >> 1)
+#define GET_ILL_ADDR_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000010 ) >> 4)
+#define GET_FENCE_HIT_INT (((REG32(ADR_AHB_ILLFEN_STATUS)) & 0x00000020 ) >> 5)
+#define GET_PWM_INI_VALUE_P_A (((REG32(ADR_PWM_A)) & 0x000000ff ) >> 0)
+#define GET_PWM_INI_VALUE_N_A (((REG32(ADR_PWM_A)) & 0x0000ff00 ) >> 8)
+#define GET_PWM_POST_SCALER_A (((REG32(ADR_PWM_A)) & 0x000f0000 ) >> 16)
+#define GET_PWM_ALWAYSON_A (((REG32(ADR_PWM_A)) & 0x20000000 ) >> 29)
+#define GET_PWM_INVERT_A (((REG32(ADR_PWM_A)) & 0x40000000 ) >> 30)
+#define GET_PWM_ENABLE_A (((REG32(ADR_PWM_A)) & 0x80000000 ) >> 31)
+#define GET_PWM_INI_VALUE_P_B (((REG32(ADR_PWM_B)) & 0x000000ff ) >> 0)
+#define GET_PWM_INI_VALUE_N_B (((REG32(ADR_PWM_B)) & 0x0000ff00 ) >> 8)
+#define GET_PWM_POST_SCALER_B (((REG32(ADR_PWM_B)) & 0x000f0000 ) >> 16)
+#define GET_PWM_ALWAYSON_B (((REG32(ADR_PWM_B)) & 0x20000000 ) >> 29)
+#define GET_PWM_INVERT_B (((REG32(ADR_PWM_B)) & 0x40000000 ) >> 30)
+#define GET_PWM_ENABLE_B (((REG32(ADR_PWM_B)) & 0x80000000 ) >> 31)
+#define GET_HBUSREQ_LOCK (((REG32(ADR_HBUSREQ_LOCK)) & 0x00001fff ) >> 0)
+#define GET_HBURST_LOCK (((REG32(ADR_HBURST_LOCK)) & 0x00001fff ) >> 0)
+#define GET_PRESCALER_USTIMER (((REG32(ADR_PRESCALER_USTIMER)) & 0x000001ff ) >> 0)
+#define GET_MODE_REG_IN_MMU (((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0x0000ffff ) >> 0)
+#define GET_MODE_REG_OUT_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x0000ffff ) >> 0)
+#define GET_MODE_REG_SO_MMU (((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x80000000 ) >> 31)
+#define GET_MONITOR_BUS_MMU (((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0x0007ffff ) >> 0)
+#define GET_TEST_MODE0 (((REG32(ADR_TEST_MODE)) & 0x00000001 ) >> 0)
+#define GET_TEST_MODE1 (((REG32(ADR_TEST_MODE)) & 0x00000002 ) >> 1)
+#define GET_TEST_MODE2 (((REG32(ADR_TEST_MODE)) & 0x00000004 ) >> 2)
+#define GET_TEST_MODE3 (((REG32(ADR_TEST_MODE)) & 0x00000008 ) >> 3)
+#define GET_TEST_MODE4 (((REG32(ADR_TEST_MODE)) & 0x00000010 ) >> 4)
+#define GET_TEST_MODE_ALL (((REG32(ADR_TEST_MODE)) & 0x00000020 ) >> 5)
+#define GET_WDT_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000001 ) >> 0)
+#define GET_SD_HOST_INIT (((REG32(ADR_BOOT_INFO)) & 0x00000002 ) >> 1)
+#define GET_ALLOW_SD_RESET (((REG32(ADR_SD_INIT_CFG)) & 0x00000001 ) >> 0)
+#define GET_UART_NRTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000001 ) >> 0)
+#define GET_UART_NCTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000002 ) >> 1)
+#define GET_TU0_TM_INIT_VALUE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU0_TM_MODE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU0_TM_INT_STS_DONE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU0_TM_INT_MASK (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU0_TM_CUR_VALUE (((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU1_TM_INIT_VALUE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU1_TM_MODE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU1_TM_INT_STS_DONE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU1_TM_INT_MASK (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU1_TM_CUR_VALUE (((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU2_TM_INIT_VALUE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU2_TM_MODE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU2_TM_INT_STS_DONE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU2_TM_INT_MASK (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU2_TM_CUR_VALUE (((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TU3_TM_INIT_VALUE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TU3_TM_MODE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TU3_TM_INT_STS_DONE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TU3_TM_INT_MASK (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TU3_TM_CUR_VALUE (((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM0_TM_INIT_VALUE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM0_TM_MODE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM0_TM_INT_STS_DONE (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM0_TM_INT_MASK (((REG32(ADR_TM0_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM0_TM_CUR_VALUE (((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM1_TM_INIT_VALUE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM1_TM_MODE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM1_TM_INT_STS_DONE (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM1_TM_INT_MASK (((REG32(ADR_TM1_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM1_TM_CUR_VALUE (((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM2_TM_INIT_VALUE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM2_TM_MODE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM2_TM_INT_STS_DONE (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM2_TM_INT_MASK (((REG32(ADR_TM2_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM2_TM_CUR_VALUE (((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_TM3_TM_INIT_VALUE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x0000ffff ) >> 0)
+#define GET_TM3_TM_MODE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00010000 ) >> 16)
+#define GET_TM3_TM_INT_STS_DONE (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00020000 ) >> 17)
+#define GET_TM3_TM_INT_MASK (((REG32(ADR_TM3_MILISECOND_TIMER)) & 0x00040000 ) >> 18)
+#define GET_TM3_TM_CUR_VALUE (((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0)
+#define GET_MCU_WDT_TIME_CNT (((REG32(ADR_MCU_WDOG_REG)) & 0x0000ffff ) >> 0)
+#define GET_MCU_WDT_STATUS (((REG32(ADR_MCU_WDOG_REG)) & 0x00020000 ) >> 17)
+#define GET_MCU_WDOG_ENA (((REG32(ADR_MCU_WDOG_REG)) & 0x80000000 ) >> 31)
+#define GET_SYS_WDT_TIME_CNT (((REG32(ADR_SYS_WDOG_REG)) & 0x0000ffff ) >> 0)
+#define GET_SYS_WDT_STATUS (((REG32(ADR_SYS_WDOG_REG)) & 0x00020000 ) >> 17)
+#define GET_SYS_WDOG_ENA (((REG32(ADR_SYS_WDOG_REG)) & 0x80000000 ) >> 31)
+#define GET_XLNA_EN_O_OE (((REG32(ADR_PAD6)) & 0x00000001 ) >> 0)
+#define GET_XLNA_EN_O_PE (((REG32(ADR_PAD6)) & 0x00000002 ) >> 1)
+#define GET_PAD6_IE (((REG32(ADR_PAD6)) & 0x00000008 ) >> 3)
+#define GET_PAD6_SEL_I (((REG32(ADR_PAD6)) & 0x00000030 ) >> 4)
+#define GET_PAD6_OD (((REG32(ADR_PAD6)) & 0x00000100 ) >> 8)
+#define GET_PAD6_SEL_O (((REG32(ADR_PAD6)) & 0x00001000 ) >> 12)
+#define GET_XLNA_EN_O_C (((REG32(ADR_PAD6)) & 0x10000000 ) >> 28)
+#define GET_WIFI_TX_SW_O_OE (((REG32(ADR_PAD7)) & 0x00000001 ) >> 0)
+#define GET_WIFI_TX_SW_O_PE (((REG32(ADR_PAD7)) & 0x00000002 ) >> 1)
+#define GET_PAD7_IE (((REG32(ADR_PAD7)) & 0x00000008 ) >> 3)
+#define GET_PAD7_SEL_I (((REG32(ADR_PAD7)) & 0x00000030 ) >> 4)
+#define GET_PAD7_OD (((REG32(ADR_PAD7)) & 0x00000100 ) >> 8)
+#define GET_PAD7_SEL_O (((REG32(ADR_PAD7)) & 0x00001000 ) >> 12)
+#define GET_WIFI_TX_SW_O_C (((REG32(ADR_PAD7)) & 0x10000000 ) >> 28)
+#define GET_WIFI_RX_SW_O_OE (((REG32(ADR_PAD8)) & 0x00000001 ) >> 0)
+#define GET_WIFI_RX_SW_O_PE (((REG32(ADR_PAD8)) & 0x00000002 ) >> 1)
+#define GET_PAD8_IE (((REG32(ADR_PAD8)) & 0x00000008 ) >> 3)
+#define GET_PAD8_SEL_I (((REG32(ADR_PAD8)) & 0x00000030 ) >> 4)
+#define GET_PAD8_OD (((REG32(ADR_PAD8)) & 0x00000100 ) >> 8)
+#define GET_WIFI_RX_SW_O_C (((REG32(ADR_PAD8)) & 0x10000000 ) >> 28)
+#define GET_BT_SW_O_OE (((REG32(ADR_PAD9)) & 0x00000001 ) >> 0)
+#define GET_BT_SW_O_PE (((REG32(ADR_PAD9)) & 0x00000002 ) >> 1)
+#define GET_PAD9_IE (((REG32(ADR_PAD9)) & 0x00000008 ) >> 3)
+#define GET_PAD9_SEL_I (((REG32(ADR_PAD9)) & 0x00000030 ) >> 4)
+#define GET_PAD9_OD (((REG32(ADR_PAD9)) & 0x00000100 ) >> 8)
+#define GET_PAD9_SEL_O (((REG32(ADR_PAD9)) & 0x00001000 ) >> 12)
+#define GET_BT_SW_O_C (((REG32(ADR_PAD9)) & 0x10000000 ) >> 28)
+#define GET_XPA_EN_O_OE (((REG32(ADR_PAD11)) & 0x00000001 ) >> 0)
+#define GET_XPA_EN_O_PE (((REG32(ADR_PAD11)) & 0x00000002 ) >> 1)
+#define GET_PAD11_IE (((REG32(ADR_PAD11)) & 0x00000008 ) >> 3)
+#define GET_PAD11_SEL_I (((REG32(ADR_PAD11)) & 0x00000030 ) >> 4)
+#define GET_PAD11_OD (((REG32(ADR_PAD11)) & 0x00000100 ) >> 8)
+#define GET_PAD11_SEL_O (((REG32(ADR_PAD11)) & 0x00001000 ) >> 12)
+#define GET_XPA_EN_O_C (((REG32(ADR_PAD11)) & 0x10000000 ) >> 28)
+#define GET_PAD15_OE (((REG32(ADR_PAD15)) & 0x00000001 ) >> 0)
+#define GET_PAD15_PE (((REG32(ADR_PAD15)) & 0x00000002 ) >> 1)
+#define GET_PAD15_DS (((REG32(ADR_PAD15)) & 0x00000004 ) >> 2)
+#define GET_PAD15_IE (((REG32(ADR_PAD15)) & 0x00000008 ) >> 3)
+#define GET_PAD15_SEL_I (((REG32(ADR_PAD15)) & 0x00000030 ) >> 4)
+#define GET_PAD15_OD (((REG32(ADR_PAD15)) & 0x00000100 ) >> 8)
+#define GET_PAD15_SEL_O (((REG32(ADR_PAD15)) & 0x00001000 ) >> 12)
+#define GET_TEST_1_ID (((REG32(ADR_PAD15)) & 0x10000000 ) >> 28)
+#define GET_PAD16_OE (((REG32(ADR_PAD16)) & 0x00000001 ) >> 0)
+#define GET_PAD16_PE (((REG32(ADR_PAD16)) & 0x00000002 ) >> 1)
+#define GET_PAD16_DS (((REG32(ADR_PAD16)) & 0x00000004 ) >> 2)
+#define GET_PAD16_IE (((REG32(ADR_PAD16)) & 0x00000008 ) >> 3)
+#define GET_PAD16_SEL_I (((REG32(ADR_PAD16)) & 0x00000030 ) >> 4)
+#define GET_PAD16_OD (((REG32(ADR_PAD16)) & 0x00000100 ) >> 8)
+#define GET_PAD16_SEL_O (((REG32(ADR_PAD16)) & 0x00001000 ) >> 12)
+#define GET_TEST_2_ID (((REG32(ADR_PAD16)) & 0x10000000 ) >> 28)
+#define GET_PAD17_OE (((REG32(ADR_PAD17)) & 0x00000001 ) >> 0)
+#define GET_PAD17_PE (((REG32(ADR_PAD17)) & 0x00000002 ) >> 1)
+#define GET_PAD17_DS (((REG32(ADR_PAD17)) & 0x00000004 ) >> 2)
+#define GET_PAD17_IE (((REG32(ADR_PAD17)) & 0x00000008 ) >> 3)
+#define GET_PAD17_SEL_I (((REG32(ADR_PAD17)) & 0x00000030 ) >> 4)
+#define GET_PAD17_OD (((REG32(ADR_PAD17)) & 0x00000100 ) >> 8)
+#define GET_PAD17_SEL_O (((REG32(ADR_PAD17)) & 0x00001000 ) >> 12)
+#define GET_TEST_3_ID (((REG32(ADR_PAD17)) & 0x10000000 ) >> 28)
+#define GET_PAD18_OE (((REG32(ADR_PAD18)) & 0x00000001 ) >> 0)
+#define GET_PAD18_PE (((REG32(ADR_PAD18)) & 0x00000002 ) >> 1)
+#define GET_PAD18_DS (((REG32(ADR_PAD18)) & 0x00000004 ) >> 2)
+#define GET_PAD18_IE (((REG32(ADR_PAD18)) & 0x00000008 ) >> 3)
+#define GET_PAD18_SEL_I (((REG32(ADR_PAD18)) & 0x00000030 ) >> 4)
+#define GET_PAD18_OD (((REG32(ADR_PAD18)) & 0x00000100 ) >> 8)
+#define GET_PAD18_SEL_O (((REG32(ADR_PAD18)) & 0x00003000 ) >> 12)
+#define GET_TEST_4_ID (((REG32(ADR_PAD18)) & 0x10000000 ) >> 28)
+#define GET_PAD19_OE (((REG32(ADR_PAD19)) & 0x00000001 ) >> 0)
+#define GET_PAD19_PE (((REG32(ADR_PAD19)) & 0x00000002 ) >> 1)
+#define GET_PAD19_DS (((REG32(ADR_PAD19)) & 0x00000004 ) >> 2)
+#define GET_PAD19_IE (((REG32(ADR_PAD19)) & 0x00000008 ) >> 3)
+#define GET_PAD19_SEL_I (((REG32(ADR_PAD19)) & 0x00000030 ) >> 4)
+#define GET_PAD19_OD (((REG32(ADR_PAD19)) & 0x00000100 ) >> 8)
+#define GET_PAD19_SEL_O (((REG32(ADR_PAD19)) & 0x00007000 ) >> 12)
+#define GET_SHORT_TO_20_ID (((REG32(ADR_PAD19)) & 0x10000000 ) >> 28)
+#define GET_PAD20_OE (((REG32(ADR_PAD20)) & 0x00000001 ) >> 0)
+#define GET_PAD20_PE (((REG32(ADR_PAD20)) & 0x00000002 ) >> 1)
+#define GET_PAD20_DS (((REG32(ADR_PAD20)) & 0x00000004 ) >> 2)
+#define GET_PAD20_IE (((REG32(ADR_PAD20)) & 0x00000008 ) >> 3)
+#define GET_PAD20_SEL_I (((REG32(ADR_PAD20)) & 0x000000f0 ) >> 4)
+#define GET_PAD20_OD (((REG32(ADR_PAD20)) & 0x00000100 ) >> 8)
+#define GET_PAD20_SEL_O (((REG32(ADR_PAD20)) & 0x00003000 ) >> 12)
+#define GET_STRAP0 (((REG32(ADR_PAD20)) & 0x08000000 ) >> 27)
+#define GET_GPIO_TEST_1_ID (((REG32(ADR_PAD20)) & 0x10000000 ) >> 28)
+#define GET_PAD21_OE (((REG32(ADR_PAD21)) & 0x00000001 ) >> 0)
+#define GET_PAD21_PE (((REG32(ADR_PAD21)) & 0x00000002 ) >> 1)
+#define GET_PAD21_DS (((REG32(ADR_PAD21)) & 0x00000004 ) >> 2)
+#define GET_PAD21_IE (((REG32(ADR_PAD21)) & 0x00000008 ) >> 3)
+#define GET_PAD21_SEL_I (((REG32(ADR_PAD21)) & 0x00000070 ) >> 4)
+#define GET_PAD21_OD (((REG32(ADR_PAD21)) & 0x00000100 ) >> 8)
+#define GET_PAD21_SEL_O (((REG32(ADR_PAD21)) & 0x00003000 ) >> 12)
+#define GET_STRAP3 (((REG32(ADR_PAD21)) & 0x08000000 ) >> 27)
+#define GET_GPIO_TEST_2_ID (((REG32(ADR_PAD21)) & 0x10000000 ) >> 28)
+#define GET_PAD22_OE (((REG32(ADR_PAD22)) & 0x00000001 ) >> 0)
+#define GET_PAD22_PE (((REG32(ADR_PAD22)) & 0x00000002 ) >> 1)
+#define GET_PAD22_DS (((REG32(ADR_PAD22)) & 0x00000004 ) >> 2)
+#define GET_PAD22_IE (((REG32(ADR_PAD22)) & 0x00000008 ) >> 3)
+#define GET_PAD22_SEL_I (((REG32(ADR_PAD22)) & 0x00000070 ) >> 4)
+#define GET_PAD22_OD (((REG32(ADR_PAD22)) & 0x00000100 ) >> 8)
+#define GET_PAD22_SEL_O (((REG32(ADR_PAD22)) & 0x00007000 ) >> 12)
+#define GET_PAD22_SEL_OE (((REG32(ADR_PAD22)) & 0x00100000 ) >> 20)
+#define GET_GPIO_TEST_3_ID (((REG32(ADR_PAD22)) & 0x10000000 ) >> 28)
+#define GET_PAD24_OE (((REG32(ADR_PAD24)) & 0x00000001 ) >> 0)
+#define GET_PAD24_PE (((REG32(ADR_PAD24)) & 0x00000002 ) >> 1)
+#define GET_PAD24_DS (((REG32(ADR_PAD24)) & 0x00000004 ) >> 2)
+#define GET_PAD24_IE (((REG32(ADR_PAD24)) & 0x00000008 ) >> 3)
+#define GET_PAD24_SEL_I (((REG32(ADR_PAD24)) & 0x00000030 ) >> 4)
+#define GET_PAD24_OD (((REG32(ADR_PAD24)) & 0x00000100 ) >> 8)
+#define GET_PAD24_SEL_O (((REG32(ADR_PAD24)) & 0x00007000 ) >> 12)
+#define GET_GPIO_TEST_4_ID (((REG32(ADR_PAD24)) & 0x10000000 ) >> 28)
+#define GET_PAD25_OE (((REG32(ADR_PAD25)) & 0x00000001 ) >> 0)
+#define GET_PAD25_PE (((REG32(ADR_PAD25)) & 0x00000002 ) >> 1)
+#define GET_PAD25_DS (((REG32(ADR_PAD25)) & 0x00000004 ) >> 2)
+#define GET_PAD25_IE (((REG32(ADR_PAD25)) & 0x00000008 ) >> 3)
+#define GET_PAD25_SEL_I (((REG32(ADR_PAD25)) & 0x00000070 ) >> 4)
+#define GET_PAD25_OD (((REG32(ADR_PAD25)) & 0x00000100 ) >> 8)
+#define GET_PAD25_SEL_O (((REG32(ADR_PAD25)) & 0x00007000 ) >> 12)
+#define GET_PAD25_SEL_OE (((REG32(ADR_PAD25)) & 0x00100000 ) >> 20)
+#define GET_STRAP1 (((REG32(ADR_PAD25)) & 0x08000000 ) >> 27)
+#define GET_GPIO_1_ID (((REG32(ADR_PAD25)) & 0x10000000 ) >> 28)
+#define GET_PAD27_OE (((REG32(ADR_PAD27)) & 0x00000001 ) >> 0)
+#define GET_PAD27_PE (((REG32(ADR_PAD27)) & 0x00000002 ) >> 1)
+#define GET_PAD27_DS (((REG32(ADR_PAD27)) & 0x00000004 ) >> 2)
+#define GET_PAD27_IE (((REG32(ADR_PAD27)) & 0x00000008 ) >> 3)
+#define GET_PAD27_SEL_I (((REG32(ADR_PAD27)) & 0x00000070 ) >> 4)
+#define GET_PAD27_OD (((REG32(ADR_PAD27)) & 0x00000100 ) >> 8)
+#define GET_PAD27_SEL_O (((REG32(ADR_PAD27)) & 0x00007000 ) >> 12)
+#define GET_GPIO_2_ID (((REG32(ADR_PAD27)) & 0x10000000 ) >> 28)
+#define GET_PAD28_OE (((REG32(ADR_PAD28)) & 0x00000001 ) >> 0)
+#define GET_PAD28_PE (((REG32(ADR_PAD28)) & 0x00000002 ) >> 1)
+#define GET_PAD28_DS (((REG32(ADR_PAD28)) & 0x00000004 ) >> 2)
+#define GET_PAD28_IE (((REG32(ADR_PAD28)) & 0x00000008 ) >> 3)
+#define GET_PAD28_SEL_I (((REG32(ADR_PAD28)) & 0x00000070 ) >> 4)
+#define GET_PAD28_OD (((REG32(ADR_PAD28)) & 0x00000100 ) >> 8)
+#define GET_PAD28_SEL_O (((REG32(ADR_PAD28)) & 0x0000f000 ) >> 12)
+#define GET_PAD28_SEL_OE (((REG32(ADR_PAD28)) & 0x00100000 ) >> 20)
+#define GET_GPIO_3_ID (((REG32(ADR_PAD28)) & 0x10000000 ) >> 28)
+#define GET_PAD29_OE (((REG32(ADR_PAD29)) & 0x00000001 ) >> 0)
+#define GET_PAD29_PE (((REG32(ADR_PAD29)) & 0x00000002 ) >> 1)
+#define GET_PAD29_DS (((REG32(ADR_PAD29)) & 0x00000004 ) >> 2)
+#define GET_PAD29_IE (((REG32(ADR_PAD29)) & 0x00000008 ) >> 3)
+#define GET_PAD29_SEL_I (((REG32(ADR_PAD29)) & 0x00000070 ) >> 4)
+#define GET_PAD29_OD (((REG32(ADR_PAD29)) & 0x00000100 ) >> 8)
+#define GET_PAD29_SEL_O (((REG32(ADR_PAD29)) & 0x00007000 ) >> 12)
+#define GET_GPIO_TEST_5_ID (((REG32(ADR_PAD29)) & 0x10000000 ) >> 28)
+#define GET_PAD30_OE (((REG32(ADR_PAD30)) & 0x00000001 ) >> 0)
+#define GET_PAD30_PE (((REG32(ADR_PAD30)) & 0x00000002 ) >> 1)
+#define GET_PAD30_DS (((REG32(ADR_PAD30)) & 0x00000004 ) >> 2)
+#define GET_PAD30_IE (((REG32(ADR_PAD30)) & 0x00000008 ) >> 3)
+#define GET_PAD30_SEL_I (((REG32(ADR_PAD30)) & 0x00000030 ) >> 4)
+#define GET_PAD30_OD (((REG32(ADR_PAD30)) & 0x00000100 ) >> 8)
+#define GET_PAD30_SEL_O (((REG32(ADR_PAD30)) & 0x00003000 ) >> 12)
+#define GET_TEST_6_ID (((REG32(ADR_PAD30)) & 0x10000000 ) >> 28)
+#define GET_PAD31_OE (((REG32(ADR_PAD31)) & 0x00000001 ) >> 0)
+#define GET_PAD31_PE (((REG32(ADR_PAD31)) & 0x00000002 ) >> 1)
+#define GET_PAD31_DS (((REG32(ADR_PAD31)) & 0x00000004 ) >> 2)
+#define GET_PAD31_IE (((REG32(ADR_PAD31)) & 0x00000008 ) >> 3)
+#define GET_PAD31_SEL_I (((REG32(ADR_PAD31)) & 0x00000030 ) >> 4)
+#define GET_PAD31_OD (((REG32(ADR_PAD31)) & 0x00000100 ) >> 8)
+#define GET_PAD31_SEL_O (((REG32(ADR_PAD31)) & 0x00003000 ) >> 12)
+#define GET_TEST_7_ID (((REG32(ADR_PAD31)) & 0x10000000 ) >> 28)
+#define GET_PAD32_OE (((REG32(ADR_PAD32)) & 0x00000001 ) >> 0)
+#define GET_PAD32_PE (((REG32(ADR_PAD32)) & 0x00000002 ) >> 1)
+#define GET_PAD32_DS (((REG32(ADR_PAD32)) & 0x00000004 ) >> 2)
+#define GET_PAD32_IE (((REG32(ADR_PAD32)) & 0x00000008 ) >> 3)
+#define GET_PAD32_SEL_I (((REG32(ADR_PAD32)) & 0x00000030 ) >> 4)
+#define GET_PAD32_OD (((REG32(ADR_PAD32)) & 0x00000100 ) >> 8)
+#define GET_PAD32_SEL_O (((REG32(ADR_PAD32)) & 0x00003000 ) >> 12)
+#define GET_TEST_8_ID (((REG32(ADR_PAD32)) & 0x10000000 ) >> 28)
+#define GET_PAD33_OE (((REG32(ADR_PAD33)) & 0x00000001 ) >> 0)
+#define GET_PAD33_PE (((REG32(ADR_PAD33)) & 0x00000002 ) >> 1)
+#define GET_PAD33_DS (((REG32(ADR_PAD33)) & 0x00000004 ) >> 2)
+#define GET_PAD33_IE (((REG32(ADR_PAD33)) & 0x00000008 ) >> 3)
+#define GET_PAD33_SEL_I (((REG32(ADR_PAD33)) & 0x00000030 ) >> 4)
+#define GET_PAD33_OD (((REG32(ADR_PAD33)) & 0x00000100 ) >> 8)
+#define GET_PAD33_SEL_O (((REG32(ADR_PAD33)) & 0x00003000 ) >> 12)
+#define GET_TEST_9_ID (((REG32(ADR_PAD33)) & 0x10000000 ) >> 28)
+#define GET_PAD34_OE (((REG32(ADR_PAD34)) & 0x00000001 ) >> 0)
+#define GET_PAD34_PE (((REG32(ADR_PAD34)) & 0x00000002 ) >> 1)
+#define GET_PAD34_DS (((REG32(ADR_PAD34)) & 0x00000004 ) >> 2)
+#define GET_PAD34_IE (((REG32(ADR_PAD34)) & 0x00000008 ) >> 3)
+#define GET_PAD34_SEL_I (((REG32(ADR_PAD34)) & 0x00000030 ) >> 4)
+#define GET_PAD34_OD (((REG32(ADR_PAD34)) & 0x00000100 ) >> 8)
+#define GET_PAD34_SEL_O (((REG32(ADR_PAD34)) & 0x00003000 ) >> 12)
+#define GET_TEST_10_ID (((REG32(ADR_PAD34)) & 0x10000000 ) >> 28)
+#define GET_PAD42_OE (((REG32(ADR_PAD42)) & 0x00000001 ) >> 0)
+#define GET_PAD42_PE (((REG32(ADR_PAD42)) & 0x00000002 ) >> 1)
+#define GET_PAD42_DS (((REG32(ADR_PAD42)) & 0x00000004 ) >> 2)
+#define GET_PAD42_IE (((REG32(ADR_PAD42)) & 0x00000008 ) >> 3)
+#define GET_PAD42_SEL_I (((REG32(ADR_PAD42)) & 0x00000030 ) >> 4)
+#define GET_PAD42_OD (((REG32(ADR_PAD42)) & 0x00000100 ) >> 8)
+#define GET_PAD42_SEL_O (((REG32(ADR_PAD42)) & 0x00001000 ) >> 12)
+#define GET_TEST_11_ID (((REG32(ADR_PAD42)) & 0x10000000 ) >> 28)
+#define GET_PAD43_OE (((REG32(ADR_PAD43)) & 0x00000001 ) >> 0)
+#define GET_PAD43_PE (((REG32(ADR_PAD43)) & 0x00000002 ) >> 1)
+#define GET_PAD43_DS (((REG32(ADR_PAD43)) & 0x00000004 ) >> 2)
+#define GET_PAD43_IE (((REG32(ADR_PAD43)) & 0x00000008 ) >> 3)
+#define GET_PAD43_SEL_I (((REG32(ADR_PAD43)) & 0x00000030 ) >> 4)
+#define GET_PAD43_OD (((REG32(ADR_PAD43)) & 0x00000100 ) >> 8)
+#define GET_PAD43_SEL_O (((REG32(ADR_PAD43)) & 0x00001000 ) >> 12)
+#define GET_TEST_12_ID (((REG32(ADR_PAD43)) & 0x10000000 ) >> 28)
+#define GET_PAD44_OE (((REG32(ADR_PAD44)) & 0x00000001 ) >> 0)
+#define GET_PAD44_PE (((REG32(ADR_PAD44)) & 0x00000002 ) >> 1)
+#define GET_PAD44_DS (((REG32(ADR_PAD44)) & 0x00000004 ) >> 2)
+#define GET_PAD44_IE (((REG32(ADR_PAD44)) & 0x00000008 ) >> 3)
+#define GET_PAD44_SEL_I (((REG32(ADR_PAD44)) & 0x00000030 ) >> 4)
+#define GET_PAD44_OD (((REG32(ADR_PAD44)) & 0x00000100 ) >> 8)
+#define GET_PAD44_SEL_O (((REG32(ADR_PAD44)) & 0x00003000 ) >> 12)
+#define GET_TEST_13_ID (((REG32(ADR_PAD44)) & 0x10000000 ) >> 28)
+#define GET_PAD45_OE (((REG32(ADR_PAD45)) & 0x00000001 ) >> 0)
+#define GET_PAD45_PE (((REG32(ADR_PAD45)) & 0x00000002 ) >> 1)
+#define GET_PAD45_DS (((REG32(ADR_PAD45)) & 0x00000004 ) >> 2)
+#define GET_PAD45_IE (((REG32(ADR_PAD45)) & 0x00000008 ) >> 3)
+#define GET_PAD45_SEL_I (((REG32(ADR_PAD45)) & 0x00000030 ) >> 4)
+#define GET_PAD45_OD (((REG32(ADR_PAD45)) & 0x00000100 ) >> 8)
+#define GET_PAD45_SEL_O (((REG32(ADR_PAD45)) & 0x00003000 ) >> 12)
+#define GET_TEST_14_ID (((REG32(ADR_PAD45)) & 0x10000000 ) >> 28)
+#define GET_PAD46_OE (((REG32(ADR_PAD46)) & 0x00000001 ) >> 0)
+#define GET_PAD46_PE (((REG32(ADR_PAD46)) & 0x00000002 ) >> 1)
+#define GET_PAD46_DS (((REG32(ADR_PAD46)) & 0x00000004 ) >> 2)
+#define GET_PAD46_IE (((REG32(ADR_PAD46)) & 0x00000008 ) >> 3)
+#define GET_PAD46_SEL_I (((REG32(ADR_PAD46)) & 0x00000030 ) >> 4)
+#define GET_PAD46_OD (((REG32(ADR_PAD46)) & 0x00000100 ) >> 8)
+#define GET_PAD46_SEL_O (((REG32(ADR_PAD46)) & 0x00003000 ) >> 12)
+#define GET_TEST_15_ID (((REG32(ADR_PAD46)) & 0x10000000 ) >> 28)
+#define GET_PAD47_OE (((REG32(ADR_PAD47)) & 0x00000001 ) >> 0)
+#define GET_PAD47_PE (((REG32(ADR_PAD47)) & 0x00000002 ) >> 1)
+#define GET_PAD47_DS (((REG32(ADR_PAD47)) & 0x00000004 ) >> 2)
+#define GET_PAD47_SEL_I (((REG32(ADR_PAD47)) & 0x00000030 ) >> 4)
+#define GET_PAD47_OD (((REG32(ADR_PAD47)) & 0x00000100 ) >> 8)
+#define GET_PAD47_SEL_O (((REG32(ADR_PAD47)) & 0x00003000 ) >> 12)
+#define GET_PAD47_SEL_OE (((REG32(ADR_PAD47)) & 0x00100000 ) >> 20)
+#define GET_GPIO_9_ID (((REG32(ADR_PAD47)) & 0x10000000 ) >> 28)
+#define GET_PAD48_OE (((REG32(ADR_PAD48)) & 0x00000001 ) >> 0)
+#define GET_PAD48_PE (((REG32(ADR_PAD48)) & 0x00000002 ) >> 1)
+#define GET_PAD48_DS (((REG32(ADR_PAD48)) & 0x00000004 ) >> 2)
+#define GET_PAD48_IE (((REG32(ADR_PAD48)) & 0x00000008 ) >> 3)
+#define GET_PAD48_SEL_I (((REG32(ADR_PAD48)) & 0x00000070 ) >> 4)
+#define GET_PAD48_OD (((REG32(ADR_PAD48)) & 0x00000100 ) >> 8)
+#define GET_PAD48_PE_SEL (((REG32(ADR_PAD48)) & 0x00000800 ) >> 11)
+#define GET_PAD48_SEL_O (((REG32(ADR_PAD48)) & 0x00003000 ) >> 12)
+#define GET_PAD48_SEL_OE (((REG32(ADR_PAD48)) & 0x00100000 ) >> 20)
+#define GET_GPIO_10_ID (((REG32(ADR_PAD48)) & 0x10000000 ) >> 28)
+#define GET_PAD49_OE (((REG32(ADR_PAD49)) & 0x00000001 ) >> 0)
+#define GET_PAD49_PE (((REG32(ADR_PAD49)) & 0x00000002 ) >> 1)
+#define GET_PAD49_DS (((REG32(ADR_PAD49)) & 0x00000004 ) >> 2)
+#define GET_PAD49_IE (((REG32(ADR_PAD49)) & 0x00000008 ) >> 3)
+#define GET_PAD49_SEL_I (((REG32(ADR_PAD49)) & 0x00000070 ) >> 4)
+#define GET_PAD49_OD (((REG32(ADR_PAD49)) & 0x00000100 ) >> 8)
+#define GET_PAD49_SEL_O (((REG32(ADR_PAD49)) & 0x00003000 ) >> 12)
+#define GET_PAD49_SEL_OE (((REG32(ADR_PAD49)) & 0x00100000 ) >> 20)
+#define GET_GPIO_11_ID (((REG32(ADR_PAD49)) & 0x10000000 ) >> 28)
+#define GET_PAD50_OE (((REG32(ADR_PAD50)) & 0x00000001 ) >> 0)
+#define GET_PAD50_PE (((REG32(ADR_PAD50)) & 0x00000002 ) >> 1)
+#define GET_PAD50_DS (((REG32(ADR_PAD50)) & 0x00000004 ) >> 2)
+#define GET_PAD50_IE (((REG32(ADR_PAD50)) & 0x00000008 ) >> 3)
+#define GET_PAD50_SEL_I (((REG32(ADR_PAD50)) & 0x00000070 ) >> 4)
+#define GET_PAD50_OD (((REG32(ADR_PAD50)) & 0x00000100 ) >> 8)
+#define GET_PAD50_SEL_O (((REG32(ADR_PAD50)) & 0x00003000 ) >> 12)
+#define GET_PAD50_SEL_OE (((REG32(ADR_PAD50)) & 0x00100000 ) >> 20)
+#define GET_GPIO_12_ID (((REG32(ADR_PAD50)) & 0x10000000 ) >> 28)
+#define GET_PAD51_OE (((REG32(ADR_PAD51)) & 0x00000001 ) >> 0)
+#define GET_PAD51_PE (((REG32(ADR_PAD51)) & 0x00000002 ) >> 1)
+#define GET_PAD51_DS (((REG32(ADR_PAD51)) & 0x00000004 ) >> 2)
+#define GET_PAD51_IE (((REG32(ADR_PAD51)) & 0x00000008 ) >> 3)
+#define GET_PAD51_SEL_I (((REG32(ADR_PAD51)) & 0x00000030 ) >> 4)
+#define GET_PAD51_OD (((REG32(ADR_PAD51)) & 0x00000100 ) >> 8)
+#define GET_PAD51_SEL_O (((REG32(ADR_PAD51)) & 0x00001000 ) >> 12)
+#define GET_PAD51_SEL_OE (((REG32(ADR_PAD51)) & 0x00100000 ) >> 20)
+#define GET_GPIO_13_ID (((REG32(ADR_PAD51)) & 0x10000000 ) >> 28)
+#define GET_PAD52_OE (((REG32(ADR_PAD52)) & 0x00000001 ) >> 0)
+#define GET_PAD52_PE (((REG32(ADR_PAD52)) & 0x00000002 ) >> 1)
+#define GET_PAD52_DS (((REG32(ADR_PAD52)) & 0x00000004 ) >> 2)
+#define GET_PAD52_SEL_I (((REG32(ADR_PAD52)) & 0x00000030 ) >> 4)
+#define GET_PAD52_OD (((REG32(ADR_PAD52)) & 0x00000100 ) >> 8)
+#define GET_PAD52_SEL_O (((REG32(ADR_PAD52)) & 0x00001000 ) >> 12)
+#define GET_PAD52_SEL_OE (((REG32(ADR_PAD52)) & 0x00100000 ) >> 20)
+#define GET_GPIO_14_ID (((REG32(ADR_PAD52)) & 0x10000000 ) >> 28)
+#define GET_PAD53_OE (((REG32(ADR_PAD53)) & 0x00000001 ) >> 0)
+#define GET_PAD53_PE (((REG32(ADR_PAD53)) & 0x00000002 ) >> 1)
+#define GET_PAD53_DS (((REG32(ADR_PAD53)) & 0x00000004 ) >> 2)
+#define GET_PAD53_IE (((REG32(ADR_PAD53)) & 0x00000008 ) >> 3)
+#define GET_PAD53_SEL_I (((REG32(ADR_PAD53)) & 0x00000030 ) >> 4)
+#define GET_PAD53_OD (((REG32(ADR_PAD53)) & 0x00000100 ) >> 8)
+#define GET_PAD53_SEL_O (((REG32(ADR_PAD53)) & 0x00001000 ) >> 12)
+#define GET_JTAG_TMS_ID (((REG32(ADR_PAD53)) & 0x10000000 ) >> 28)
+#define GET_PAD54_OE (((REG32(ADR_PAD54)) & 0x00000001 ) >> 0)
+#define GET_PAD54_PE (((REG32(ADR_PAD54)) & 0x00000002 ) >> 1)
+#define GET_PAD54_DS (((REG32(ADR_PAD54)) & 0x00000004 ) >> 2)
+#define GET_PAD54_OD (((REG32(ADR_PAD54)) & 0x00000100 ) >> 8)
+#define GET_PAD54_SEL_O (((REG32(ADR_PAD54)) & 0x00003000 ) >> 12)
+#define GET_JTAG_TCK_ID (((REG32(ADR_PAD54)) & 0x10000000 ) >> 28)
+#define GET_PAD56_PE (((REG32(ADR_PAD56)) & 0x00000002 ) >> 1)
+#define GET_PAD56_DS (((REG32(ADR_PAD56)) & 0x00000004 ) >> 2)
+#define GET_PAD56_SEL_I (((REG32(ADR_PAD56)) & 0x00000010 ) >> 4)
+#define GET_PAD56_OD (((REG32(ADR_PAD56)) & 0x00000100 ) >> 8)
+#define GET_JTAG_TDI_ID (((REG32(ADR_PAD56)) & 0x10000000 ) >> 28)
+#define GET_PAD57_OE (((REG32(ADR_PAD57)) & 0x00000001 ) >> 0)
+#define GET_PAD57_PE (((REG32(ADR_PAD57)) & 0x00000002 ) >> 1)
+#define GET_PAD57_DS (((REG32(ADR_PAD57)) & 0x00000004 ) >> 2)
+#define GET_PAD57_IE (((REG32(ADR_PAD57)) & 0x00000008 ) >> 3)
+#define GET_PAD57_SEL_I (((REG32(ADR_PAD57)) & 0x00000030 ) >> 4)
+#define GET_PAD57_OD (((REG32(ADR_PAD57)) & 0x00000100 ) >> 8)
+#define GET_PAD57_SEL_O (((REG32(ADR_PAD57)) & 0x00003000 ) >> 12)
+#define GET_PAD57_SEL_OE (((REG32(ADR_PAD57)) & 0x00100000 ) >> 20)
+#define GET_JTAG_TDO_ID (((REG32(ADR_PAD57)) & 0x10000000 ) >> 28)
+#define GET_PAD58_OE (((REG32(ADR_PAD58)) & 0x00000001 ) >> 0)
+#define GET_PAD58_PE (((REG32(ADR_PAD58)) & 0x00000002 ) >> 1)
+#define GET_PAD58_DS (((REG32(ADR_PAD58)) & 0x00000004 ) >> 2)
+#define GET_PAD58_IE (((REG32(ADR_PAD58)) & 0x00000008 ) >> 3)
+#define GET_PAD58_SEL_I (((REG32(ADR_PAD58)) & 0x00000030 ) >> 4)
+#define GET_PAD58_OD (((REG32(ADR_PAD58)) & 0x00000100 ) >> 8)
+#define GET_PAD58_SEL_O (((REG32(ADR_PAD58)) & 0x00001000 ) >> 12)
+#define GET_TEST_16_ID (((REG32(ADR_PAD58)) & 0x10000000 ) >> 28)
+#define GET_PAD59_OE (((REG32(ADR_PAD59)) & 0x00000001 ) >> 0)
+#define GET_PAD59_PE (((REG32(ADR_PAD59)) & 0x00000002 ) >> 1)
+#define GET_PAD59_DS (((REG32(ADR_PAD59)) & 0x00000004 ) >> 2)
+#define GET_PAD59_IE (((REG32(ADR_PAD59)) & 0x00000008 ) >> 3)
+#define GET_PAD59_SEL_I (((REG32(ADR_PAD59)) & 0x00000030 ) >> 4)
+#define GET_PAD59_OD (((REG32(ADR_PAD59)) & 0x00000100 ) >> 8)
+#define GET_PAD59_SEL_O (((REG32(ADR_PAD59)) & 0x00001000 ) >> 12)
+#define GET_TEST_17_ID (((REG32(ADR_PAD59)) & 0x10000000 ) >> 28)
+#define GET_PAD60_OE (((REG32(ADR_PAD60)) & 0x00000001 ) >> 0)
+#define GET_PAD60_PE (((REG32(ADR_PAD60)) & 0x00000002 ) >> 1)
+#define GET_PAD60_DS (((REG32(ADR_PAD60)) & 0x00000004 ) >> 2)
+#define GET_PAD60_IE (((REG32(ADR_PAD60)) & 0x00000008 ) >> 3)
+#define GET_PAD60_SEL_I (((REG32(ADR_PAD60)) & 0x00000030 ) >> 4)
+#define GET_PAD60_OD (((REG32(ADR_PAD60)) & 0x00000100 ) >> 8)
+#define GET_PAD60_SEL_O (((REG32(ADR_PAD60)) & 0x00001000 ) >> 12)
+#define GET_TEST_18_ID (((REG32(ADR_PAD60)) & 0x10000000 ) >> 28)
+#define GET_PAD61_OE (((REG32(ADR_PAD61)) & 0x00000001 ) >> 0)
+#define GET_PAD61_PE (((REG32(ADR_PAD61)) & 0x00000002 ) >> 1)
+#define GET_PAD61_DS (((REG32(ADR_PAD61)) & 0x00000004 ) >> 2)
+#define GET_PAD61_IE (((REG32(ADR_PAD61)) & 0x00000008 ) >> 3)
+#define GET_PAD61_SEL_I (((REG32(ADR_PAD61)) & 0x00000010 ) >> 4)
+#define GET_PAD61_OD (((REG32(ADR_PAD61)) & 0x00000100 ) >> 8)
+#define GET_PAD61_SEL_O (((REG32(ADR_PAD61)) & 0x00003000 ) >> 12)
+#define GET_TEST_19_ID (((REG32(ADR_PAD61)) & 0x10000000 ) >> 28)
+#define GET_PAD62_OE (((REG32(ADR_PAD62)) & 0x00000001 ) >> 0)
+#define GET_PAD62_PE (((REG32(ADR_PAD62)) & 0x00000002 ) >> 1)
+#define GET_PAD62_DS (((REG32(ADR_PAD62)) & 0x00000004 ) >> 2)
+#define GET_PAD62_IE (((REG32(ADR_PAD62)) & 0x00000008 ) >> 3)
+#define GET_PAD62_SEL_I (((REG32(ADR_PAD62)) & 0x00000010 ) >> 4)
+#define GET_PAD62_OD (((REG32(ADR_PAD62)) & 0x00000100 ) >> 8)
+#define GET_PAD62_SEL_O (((REG32(ADR_PAD62)) & 0x00001000 ) >> 12)
+#define GET_TEST_20_ID (((REG32(ADR_PAD62)) & 0x10000000 ) >> 28)
+#define GET_PAD64_OE (((REG32(ADR_PAD64)) & 0x00000001 ) >> 0)
+#define GET_PAD64_PE (((REG32(ADR_PAD64)) & 0x00000002 ) >> 1)
+#define GET_PAD64_DS (((REG32(ADR_PAD64)) & 0x00000004 ) >> 2)
+#define GET_PAD64_IE (((REG32(ADR_PAD64)) & 0x00000008 ) >> 3)
+#define GET_PAD64_SEL_I (((REG32(ADR_PAD64)) & 0x00000070 ) >> 4)
+#define GET_PAD64_OD (((REG32(ADR_PAD64)) & 0x00000100 ) >> 8)
+#define GET_PAD64_SEL_O (((REG32(ADR_PAD64)) & 0x00003000 ) >> 12)
+#define GET_PAD64_SEL_OE (((REG32(ADR_PAD64)) & 0x00100000 ) >> 20)
+#define GET_GPIO_15_IP_ID (((REG32(ADR_PAD64)) & 0x10000000 ) >> 28)
+#define GET_PAD65_OE (((REG32(ADR_PAD65)) & 0x00000001 ) >> 0)
+#define GET_PAD65_PE (((REG32(ADR_PAD65)) & 0x00000002 ) >> 1)
+#define GET_PAD65_DS (((REG32(ADR_PAD65)) & 0x00000004 ) >> 2)
+#define GET_PAD65_IE (((REG32(ADR_PAD65)) & 0x00000008 ) >> 3)
+#define GET_PAD65_SEL_I (((REG32(ADR_PAD65)) & 0x00000070 ) >> 4)
+#define GET_PAD65_OD (((REG32(ADR_PAD65)) & 0x00000100 ) >> 8)
+#define GET_PAD65_SEL_O (((REG32(ADR_PAD65)) & 0x00001000 ) >> 12)
+#define GET_GPIO_TEST_7_IN_ID (((REG32(ADR_PAD65)) & 0x10000000 ) >> 28)
+#define GET_PAD66_OE (((REG32(ADR_PAD66)) & 0x00000001 ) >> 0)
+#define GET_PAD66_PE (((REG32(ADR_PAD66)) & 0x00000002 ) >> 1)
+#define GET_PAD66_DS (((REG32(ADR_PAD66)) & 0x00000004 ) >> 2)
+#define GET_PAD66_IE (((REG32(ADR_PAD66)) & 0x00000008 ) >> 3)
+#define GET_PAD66_SEL_I (((REG32(ADR_PAD66)) & 0x00000030 ) >> 4)
+#define GET_PAD66_OD (((REG32(ADR_PAD66)) & 0x00000100 ) >> 8)
+#define GET_PAD66_SEL_O (((REG32(ADR_PAD66)) & 0x00003000 ) >> 12)
+#define GET_GPIO_17_QP_ID (((REG32(ADR_PAD66)) & 0x10000000 ) >> 28)
+#define GET_PAD68_OE (((REG32(ADR_PAD68)) & 0x00000001 ) >> 0)
+#define GET_PAD68_PE (((REG32(ADR_PAD68)) & 0x00000002 ) >> 1)
+#define GET_PAD68_DS (((REG32(ADR_PAD68)) & 0x00000004 ) >> 2)
+#define GET_PAD68_IE (((REG32(ADR_PAD68)) & 0x00000008 ) >> 3)
+#define GET_PAD68_OD (((REG32(ADR_PAD68)) & 0x00000100 ) >> 8)
+#define GET_PAD68_SEL_O (((REG32(ADR_PAD68)) & 0x00001000 ) >> 12)
+#define GET_GPIO_19_ID (((REG32(ADR_PAD68)) & 0x10000000 ) >> 28)
+#define GET_PAD67_OE (((REG32(ADR_PAD67)) & 0x00000001 ) >> 0)
+#define GET_PAD67_PE (((REG32(ADR_PAD67)) & 0x00000002 ) >> 1)
+#define GET_PAD67_DS (((REG32(ADR_PAD67)) & 0x00000004 ) >> 2)
+#define GET_PAD67_IE (((REG32(ADR_PAD67)) & 0x00000008 ) >> 3)
+#define GET_PAD67_SEL_I (((REG32(ADR_PAD67)) & 0x00000070 ) >> 4)
+#define GET_PAD67_OD (((REG32(ADR_PAD67)) & 0x00000100 ) >> 8)
+#define GET_PAD67_SEL_O (((REG32(ADR_PAD67)) & 0x00003000 ) >> 12)
+#define GET_GPIO_TEST_8_QN_ID (((REG32(ADR_PAD67)) & 0x10000000 ) >> 28)
+#define GET_PAD69_OE (((REG32(ADR_PAD69)) & 0x00000001 ) >> 0)
+#define GET_PAD69_PE (((REG32(ADR_PAD69)) & 0x00000002 ) >> 1)
+#define GET_PAD69_DS (((REG32(ADR_PAD69)) & 0x00000004 ) >> 2)
+#define GET_PAD69_IE (((REG32(ADR_PAD69)) & 0x00000008 ) >> 3)
+#define GET_PAD69_SEL_I (((REG32(ADR_PAD69)) & 0x00000030 ) >> 4)
+#define GET_PAD69_OD (((REG32(ADR_PAD69)) & 0x00000100 ) >> 8)
+#define GET_PAD69_SEL_O (((REG32(ADR_PAD69)) & 0x00001000 ) >> 12)
+#define GET_STRAP2 (((REG32(ADR_PAD69)) & 0x08000000 ) >> 27)
+#define GET_GPIO_20_ID (((REG32(ADR_PAD69)) & 0x10000000 ) >> 28)
+#define GET_PAD70_OE (((REG32(ADR_PAD70)) & 0x00000001 ) >> 0)
+#define GET_PAD70_PE (((REG32(ADR_PAD70)) & 0x00000002 ) >> 1)
+#define GET_PAD70_DS (((REG32(ADR_PAD70)) & 0x00000004 ) >> 2)
+#define GET_PAD70_IE (((REG32(ADR_PAD70)) & 0x00000008 ) >> 3)
+#define GET_PAD70_SEL_I (((REG32(ADR_PAD70)) & 0x00000030 ) >> 4)
+#define GET_PAD70_OD (((REG32(ADR_PAD70)) & 0x00000100 ) >> 8)
+#define GET_PAD70_SEL_O (((REG32(ADR_PAD70)) & 0x00007000 ) >> 12)
+#define GET_GPIO_21_ID (((REG32(ADR_PAD70)) & 0x10000000 ) >> 28)
+#define GET_PAD231_OE (((REG32(ADR_PAD231)) & 0x00000001 ) >> 0)
+#define GET_PAD231_PE (((REG32(ADR_PAD231)) & 0x00000002 ) >> 1)
+#define GET_PAD231_DS (((REG32(ADR_PAD231)) & 0x00000004 ) >> 2)
+#define GET_PAD231_IE (((REG32(ADR_PAD231)) & 0x00000008 ) >> 3)
+#define GET_PAD231_OD (((REG32(ADR_PAD231)) & 0x00000100 ) >> 8)
+#define GET_PIN_40_OR_56_ID (((REG32(ADR_PAD231)) & 0x10000000 ) >> 28)
+#define GET_MP_PHY2RX_DATA__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000001 ) >> 0)
+#define GET_MP_PHY2RX_DATA__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000002 ) >> 1)
+#define GET_MP_TX_FF_RPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000004 ) >> 2)
+#define GET_MP_RX_FF_WPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000008 ) >> 3)
+#define GET_MP_RX_FF_WPTR__1_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000010 ) >> 4)
+#define GET_MP_RX_FF_WPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000020 ) >> 5)
+#define GET_MP_PHY2RX_DATA__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000040 ) >> 6)
+#define GET_MP_PHY2RX_DATA__4_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000080 ) >> 7)
+#define GET_I2CM_SDA_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000300 ) >> 8)
+#define GET_CRYSTAL_OUT_REQ_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000400 ) >> 10)
+#define GET_MP_PHY2RX_DATA__5_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00000800 ) >> 11)
+#define GET_MP_PHY2RX_DATA__3_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00001000 ) >> 12)
+#define GET_UART_RXD_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00006000 ) >> 13)
+#define GET_MP_PHY2RX_DATA__6_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00008000 ) >> 15)
+#define GET_DAT_UART_NCTS_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00010000 ) >> 16)
+#define GET_GPIO_LOG_STOP_SEL (((REG32(ADR_PIN_SEL_0)) & 0x000e0000 ) >> 17)
+#define GET_MP_TX_FF_RPTR__0_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00100000 ) >> 20)
+#define GET_MP_PHY_RX_WRST_N_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00200000 ) >> 21)
+#define GET_EXT_32K_SEL (((REG32(ADR_PIN_SEL_0)) & 0x00c00000 ) >> 22)
+#define GET_MP_PHY2RX_DATA__7_SEL (((REG32(ADR_PIN_SEL_0)) & 0x01000000 ) >> 24)
+#define GET_MP_TX_FF_RPTR__2_SEL (((REG32(ADR_PIN_SEL_0)) & 0x02000000 ) >> 25)
+#define GET_PMUINT_WAKE_SEL (((REG32(ADR_PIN_SEL_0)) & 0x1c000000 ) >> 26)
+#define GET_I2CM_SCL_ID_SEL (((REG32(ADR_PIN_SEL_0)) & 0x20000000 ) >> 29)
+#define GET_MP_MRX_RX_EN_SEL (((REG32(ADR_PIN_SEL_0)) & 0x40000000 ) >> 30)
+#define GET_DAT_UART_RXD_SEL_0 (((REG32(ADR_PIN_SEL_0)) & 0x80000000 ) >> 31)
+#define GET_DAT_UART_RXD_SEL_1 (((REG32(ADR_PIN_SEL_1)) & 0x00000001 ) >> 0)
+#define GET_SPI_DI_SEL (((REG32(ADR_PIN_SEL_1)) & 0x00000002 ) >> 1)
+#define GET_IO_PORT_REG (((REG32(ADR_IO_PORT_REG)) & 0x0001ffff ) >> 0)
+#define GET_MASK_RX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000001 ) >> 0)
+#define GET_MASK_TX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000002 ) >> 1)
+#define GET_MASK_SOC_SYSTEM_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000080 ) >> 7)
+#define GET_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000001 ) >> 0)
+#define GET_TX_COMPLETE_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000002 ) >> 1)
+#define GET_SOC_SYSTEM_INT_STATUS (((REG32(ADR_INT_STATUS_REG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000080 ) >> 7)
+#define GET_HOST_TRIGGERED_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000100 ) >> 8)
+#define GET_HOST_TRIGGERED_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000200 ) >> 9)
+#define GET_SOC_TRIGGER_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000400 ) >> 10)
+#define GET_SOC_TRIGGER_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000800 ) >> 11)
+#define GET_RDY_FOR_TX_RX (((REG32(ADR_FN1_STATUS_REG)) & 0x00000001 ) >> 0)
+#define GET_RDY_FOR_FW_DOWNLOAD (((REG32(ADR_FN1_STATUS_REG)) & 0x00000002 ) >> 1)
+#define GET_ILLEGAL_CMD_RESP_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000004 ) >> 2)
+#define GET_SDIO_TRX_DATA_SEQUENCE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000008 ) >> 3)
+#define GET_GPIO_INT_TRIGGER_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000010 ) >> 4)
+#define GET_TRIGGER_FUNCTION_SETTING (((REG32(ADR_FN1_STATUS_REG)) & 0x00000060 ) >> 5)
+#define GET_CMD52_ABORT_RESPONSE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000080 ) >> 7)
+#define GET_RX_PACKET_LENGTH (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x0000ffff ) >> 0)
+#define GET_CARD_FW_DL_STATUS (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x00ff0000 ) >> 16)
+#define GET_TX_RX_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x01000000 ) >> 24)
+#define GET_SDIO_LOOP_BACK_TEST (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x02000000 ) >> 25)
+#define GET_CMD52_ABORT_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x10000000 ) >> 28)
+#define GET_CMD52_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x20000000 ) >> 29)
+#define GET_SDIO_PARTIAL_RESET_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x40000000 ) >> 30)
+#define GET_SDIO_ALL_RESE_ACTIVE (((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x80000000 ) >> 31)
+#define GET_RX_PACKET_LENGTH2 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x0000ffff ) >> 0)
+#define GET_RX_INT1 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00010000 ) >> 16)
+#define GET_TX_DONE (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00020000 ) >> 17)
+#define GET_HCI_TRX_FINISH (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00040000 ) >> 18)
+#define GET_ALLOCATE_STATUS (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00080000 ) >> 19)
+#define GET_HCI_INPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x00f00000 ) >> 20)
+#define GET_HCI_OUTPUT_FF_CNT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x1f000000 ) >> 24)
+#define GET_AHB_HANG4 (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x20000000 ) >> 29)
+#define GET_HCI_IN_QUE_EMPTY (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x40000000 ) >> 30)
+#define GET_SYSTEM_INT (((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x80000000 ) >> 31)
+#define GET_CARD_RCA_REG (((REG32(ADR_CARD_RCA_REG)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_FIFO_WR_THLD_REG (((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_FIFO_WR_LIMIT_REG (((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_TX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_THLD_FOR_CMD53RD_REG (((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0x000001ff ) >> 0)
+#define GET_SDIO_RX_DATA_BATCH_SIZE_REG (((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0x000001ff ) >> 0)
+#define GET_START_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x000000ff ) >> 0)
+#define GET_END_BYTE_VALUE (((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0x0000ff00 ) >> 8)
+#define GET_SDIO_BYTE_MODE_BATCH_SIZE_REG (((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0x000000ff ) >> 0)
+#define GET_SDIO_LAST_CMD_INDEX_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x0000003f ) >> 0)
+#define GET_SDIO_LAST_CMD_CRC_REG (((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0x00007f00 ) >> 8)
+#define GET_SDIO_LAST_CMD_ARG_REG (((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0xffffffff ) >> 0)
+#define GET_SDIO_BUS_STATE_REG (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000001f ) >> 0)
+#define GET_SDIO_BUSY_LONG_CNT (((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffff0000 ) >> 16)
+#define GET_SDIO_CARD_STATUS_REG (((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0xffffffff ) >> 0)
+#define GET_R5_RESPONSE_FLAG (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x000000ff ) >> 0)
+#define GET_RESP_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000100 ) >> 8)
+#define GET_DAT_OUT_EDGE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00000200 ) >> 9)
+#define GET_MCU_TO_SDIO_INFO_MASK (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00010000 ) >> 16)
+#define GET_INT_THROUGH_PIN (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00020000 ) >> 17)
+#define GET_WRITE_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x000000ff ) >> 0)
+#define GET_WRITE_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x0000ff00 ) >> 8)
+#define GET_READ_DATA (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ff0000 ) >> 16)
+#define GET_READ_ADDRESS (((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff000000 ) >> 24)
+#define GET_FN1_DMA_START_ADDR_REG (((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0xffffffff ) >> 0)
+#define GET_SDIO_TO_MCU_INFO (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x000000ff ) >> 0)
+#define GET_SDIO_PARTIAL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000100 ) >> 8)
+#define GET_SDIO_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000200 ) >> 9)
+#define GET_PERI_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000400 ) >> 10)
+#define GET_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000800 ) >> 11)
+#define GET_AHB_BRIDGE_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00001000 ) >> 12)
+#define GET_IO_REG_PORT_REG (((REG32(ADR_IO_REG_PORT_REG)) & 0x0001ffff ) >> 0)
+#define GET_SDIO_FIFO_EMPTY_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_FIFO_FULL_CNT (((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000 ) >> 16)
+#define GET_SDIO_CRC7_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff ) >> 0)
+#define GET_SDIO_CRC16_ERROR_CNT (((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000 ) >> 16)
+#define GET_SDIO_RD_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x000001ff ) >> 0)
+#define GET_SDIO_WR_BLOCK_CNT (((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0x01ff0000 ) >> 16)
+#define GET_CMD52_RD_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x000f0000 ) >> 16)
+#define GET_CMD52_WR_ABORT_CNT (((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0x00f00000 ) >> 20)
+#define GET_SDIO_FIFO_WR_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x000000ff ) >> 0)
+#define GET_SDIO_FIFO_RD_PTR_REG (((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0x0000ff00 ) >> 8)
+#define GET_SDIO_READ_DATA_CTRL (((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0x00010000 ) >> 16)
+#define GET_TX_SIZE_BEFORE_SHIFT (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x000000ff ) >> 0)
+#define GET_TX_SIZE_SHIFT_BITS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00000700 ) >> 8)
+#define GET_SDIO_TX_ALLOC_STATE (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00001000 ) >> 12)
+#define GET_ALLOCATE_STATUS2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00010000 ) >> 16)
+#define GET_NO_ALLOCATE_SEND_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00020000 ) >> 17)
+#define GET_DOUBLE_ALLOCATE_ERROR (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00040000 ) >> 18)
+#define GET_TX_DONE_STATUS (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00080000 ) >> 19)
+#define GET_AHB_HANG2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00100000 ) >> 20)
+#define GET_HCI_TRX_FINISH2 (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00200000 ) >> 21)
+#define GET_INTR_RX (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00400000 ) >> 22)
+#define GET_HCI_INPUT_QUEUE_FULL (((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0x00800000 ) >> 23)
+#define GET_ALLOCATESTATUS (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000001 ) >> 0)
+#define GET_HCI_TRX_FINISH3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000002 ) >> 1)
+#define GET_HCI_IN_QUE_EMPTY2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000004 ) >> 2)
+#define GET_MTX_MNG_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000008 ) >> 3)
+#define GET_EDCA0_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000010 ) >> 4)
+#define GET_EDCA1_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000020 ) >> 5)
+#define GET_EDCA2_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000040 ) >> 6)
+#define GET_EDCA3_UPTHOLD_INT (((REG32(ADR_SDIO_TX_INFORM)) & 0x00000080 ) >> 7)
+#define GET_TX_PAGE_REMAIN2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0000ff00 ) >> 8)
+#define GET_TX_ID_REMAIN3 (((REG32(ADR_SDIO_TX_INFORM)) & 0x007f0000 ) >> 16)
+#define GET_HCI_OUTPUT_FF_CNT_0 (((REG32(ADR_SDIO_TX_INFORM)) & 0x00800000 ) >> 23)
+#define GET_HCI_OUTPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0x0f000000 ) >> 24)
+#define GET_HCI_INPUT_FF_CNT2 (((REG32(ADR_SDIO_TX_INFORM)) & 0xf0000000 ) >> 28)
+#define GET_F1_BLOCK_SIZE_0_REG (((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0x00000fff ) >> 0)
+#define GET_START_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x000000ff ) >> 0)
+#define GET_COMMAND_COUNTER (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ff00 ) >> 8)
+#define GET_CMD_LOG_PART1 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff0000 ) >> 16)
+#define GET_CMD_LOG_PART2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff ) >> 0)
+#define GET_END_BYTE_VALUE2 (((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000 ) >> 24)
+#define GET_RX_PACKET_LENGTH3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x0000ffff ) >> 0)
+#define GET_RX_INT3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_TX_ID_REMAIN2 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00fe0000 ) >> 17)
+#define GET_TX_PAGE_REMAIN3 (((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff000000 ) >> 24)
+#define GET_CCCR_00H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x000000ff ) >> 0)
+#define GET_CCCR_02H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x00ff0000 ) >> 16)
+#define GET_CCCR_03H_REG (((REG32(ADR_CCCR_00H_REG)) & 0xff000000 ) >> 24)
+#define GET_CCCR_04H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000000ff ) >> 0)
+#define GET_CCCR_05H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x0000ff00 ) >> 8)
+#define GET_CCCR_06H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000f0000 ) >> 16)
+#define GET_CCCR_07H_REG (((REG32(ADR_CCCR_04H_REG)) & 0xff000000 ) >> 24)
+#define GET_SUPPORT_DIRECT_COMMAND_SDIO (((REG32(ADR_CCCR_08H_REG)) & 0x00000001 ) >> 0)
+#define GET_SUPPORT_MULTIPLE_BLOCK_TRANSFER (((REG32(ADR_CCCR_08H_REG)) & 0x00000002 ) >> 1)
+#define GET_SUPPORT_READ_WAIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000004 ) >> 2)
+#define GET_SUPPORT_BUS_CONTROL (((REG32(ADR_CCCR_08H_REG)) & 0x00000008 ) >> 3)
+#define GET_SUPPORT_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000010 ) >> 4)
+#define GET_ENABLE_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000020 ) >> 5)
+#define GET_LOW_SPEED_CARD (((REG32(ADR_CCCR_08H_REG)) & 0x00000040 ) >> 6)
+#define GET_LOW_SPEED_CARD_4BIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000080 ) >> 7)
+#define GET_COMMON_CIS_PONTER (((REG32(ADR_CCCR_08H_REG)) & 0x01ffff00 ) >> 8)
+#define GET_SUPPORT_HIGH_SPEED (((REG32(ADR_CCCR_13H_REG)) & 0x01000000 ) >> 24)
+#define GET_BSS (((REG32(ADR_CCCR_13H_REG)) & 0x0e000000 ) >> 25)
+#define GET_FBR_100H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000000f ) >> 0)
+#define GET_CSASUPPORT (((REG32(ADR_FBR_100H_REG)) & 0x00000040 ) >> 6)
+#define GET_ENABLECSA (((REG32(ADR_FBR_100H_REG)) & 0x00000080 ) >> 7)
+#define GET_FBR_101H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000ff00 ) >> 8)
+#define GET_FBR_109H_REG (((REG32(ADR_FBR_109H_REG)) & 0x01ffff00 ) >> 8)
+#define GET_F0_CIS_CONTENT_REG_31_0 (((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_63_32 (((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_95_64 (((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_127_96 (((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_159_128 (((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_191_160 (((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_223_192 (((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_255_224 (((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_287_256 (((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_319_288 (((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_351_320 (((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_383_352 (((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_415_384 (((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_447_416 (((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_479_448 (((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
+#define GET_F0_CIS_CONTENT_REG_511_480 (((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_31_0 (((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_63_32 (((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_95_64 (((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_127_96 (((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_159_128 (((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_191_160 (((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_223_192 (((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_255_224 (((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_287_256 (((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_319_288 (((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_351_320 (((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_383_352 (((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_415_384 (((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_447_416 (((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_479_448 (((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0)
+#define GET_F1_CIS_CONTENT_REG_511_480 (((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0)
+#define GET_SPI_MODE (((REG32(ADR_SPI_MODE)) & 0xffffffff ) >> 0)
+#define GET_RX_QUOTA (((REG32(ADR_RX_QUOTA)) & 0x0000ffff ) >> 0)
+#define GET_CONDI_NUM (((REG32(ADR_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
+#define GET_HOST_PATH (((REG32(ADR_HOST_PATH)) & 0x00000001 ) >> 0)
+#define GET_TX_SEG (((REG32(ADR_TX_SEG)) & 0xffffffff ) >> 0)
+#define GET_BRST_MODE (((REG32(ADR_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
+#define GET_CLK_WIDTH (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
+#define GET_CSN_INTER (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
+#define GET_BACK_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_FRONT_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
+#define GET_RX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000002 ) >> 1)
+#define GET_RX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000004 ) >> 2)
+#define GET_TX_FIFO_FAIL (((REG32(ADR_SPI_STS)) & 0x00000008 ) >> 3)
+#define GET_TX_HOST_FAIL (((REG32(ADR_SPI_STS)) & 0x00000010 ) >> 4)
+#define GET_SPI_DOUBLE_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000020 ) >> 5)
+#define GET_SPI_TX_NO_ALLOC (((REG32(ADR_SPI_STS)) & 0x00000040 ) >> 6)
+#define GET_RDATA_RDY (((REG32(ADR_SPI_STS)) & 0x00000080 ) >> 7)
+#define GET_SPI_ALLOC_STATUS (((REG32(ADR_SPI_STS)) & 0x00000100 ) >> 8)
+#define GET_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_SPI_STS)) & 0x00000200 ) >> 9)
+#define GET_RX_LEN (((REG32(ADR_SPI_STS)) & 0xffff0000 ) >> 16)
+#define GET_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
+#define GET_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
+#define GET_SPI_TX_ALLOC_SIZE (((REG32(ADR_TX_ALLOC)) & 0x000000ff ) >> 0)
+#define GET_RD_DAT_CNT (((REG32(ADR_DBG_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RD_STS_CNT (((REG32(ADR_DBG_CNT)) & 0xffff0000 ) >> 16)
+#define GET_JUDGE_CNT (((REG32(ADR_DBG_CNT2)) & 0x0000ffff ) >> 0)
+#define GET_RD_STS_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00010000 ) >> 16)
+#define GET_RD_DAT_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00020000 ) >> 17)
+#define GET_JUDGE_CNT_CLR (((REG32(ADR_DBG_CNT2)) & 0x00040000 ) >> 18)
+#define GET_TX_DONE_CNT (((REG32(ADR_DBG_CNT3)) & 0x0000ffff ) >> 0)
+#define GET_TX_DISCARD_CNT (((REG32(ADR_DBG_CNT3)) & 0xffff0000 ) >> 16)
+#define GET_TX_SET_CNT (((REG32(ADR_DBG_CNT4)) & 0x0000ffff ) >> 0)
+#define GET_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00010000 ) >> 16)
+#define GET_TX_DONE_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00020000 ) >> 17)
+#define GET_TX_SET_CNT_CLR (((REG32(ADR_DBG_CNT4)) & 0x00040000 ) >> 18)
+#define GET_DAT_MODE_OFF (((REG32(ADR_DBG_CNT4)) & 0x00080000 ) >> 19)
+#define GET_TX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x00700000 ) >> 20)
+#define GET_RX_FIFO_RESIDUE (((REG32(ADR_DBG_CNT4)) & 0x07000000 ) >> 24)
+#define GET_RX_RDY (((REG32(ADR_INT_TAG)) & 0x00000001 ) >> 0)
+#define GET_SDIO_SYS_INT (((REG32(ADR_INT_TAG)) & 0x00000004 ) >> 2)
+#define GET_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000008 ) >> 3)
+#define GET_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000010 ) >> 4)
+#define GET_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000020 ) >> 5)
+#define GET_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_TAG)) & 0x00000040 ) >> 6)
+#define GET_TX_LIMIT_INT_IN (((REG32(ADR_INT_TAG)) & 0x00000080 ) >> 7)
+#define GET_SPI_FN1 (((REG32(ADR_INT_TAG)) & 0x00007f00 ) >> 8)
+#define GET_SPI_CLK_EN_INT (((REG32(ADR_INT_TAG)) & 0x00008000 ) >> 15)
+#define GET_SPI_HOST_MASK (((REG32(ADR_INT_TAG)) & 0x00ff0000 ) >> 16)
+#define GET_I2CM_INT_WDONE (((REG32(ADR_I2CM_EN)) & 0x00000001 ) >> 0)
+#define GET_I2CM_INT_RDONE (((REG32(ADR_I2CM_EN)) & 0x00000002 ) >> 1)
+#define GET_I2CM_IDLE (((REG32(ADR_I2CM_EN)) & 0x00000004 ) >> 2)
+#define GET_I2CM_INT_MISMATCH (((REG32(ADR_I2CM_EN)) & 0x00000008 ) >> 3)
+#define GET_I2CM_PSCL (((REG32(ADR_I2CM_EN)) & 0x00003ff0 ) >> 4)
+#define GET_I2CM_MANUAL_MODE (((REG32(ADR_I2CM_EN)) & 0x00010000 ) >> 16)
+#define GET_I2CM_INT_WDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00020000 ) >> 17)
+#define GET_I2CM_INT_RDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00040000 ) >> 18)
+#define GET_I2CM_DEV_A (((REG32(ADR_I2CM_DEV_A)) & 0x000003ff ) >> 0)
+#define GET_I2CM_DEV_A10B (((REG32(ADR_I2CM_DEV_A)) & 0x00004000 ) >> 14)
+#define GET_I2CM_RX (((REG32(ADR_I2CM_DEV_A)) & 0x00008000 ) >> 15)
+#define GET_I2CM_LEN (((REG32(ADR_I2CM_LEN)) & 0x0000ffff ) >> 0)
+#define GET_I2CM_T_LEFT (((REG32(ADR_I2CM_LEN)) & 0x00070000 ) >> 16)
+#define GET_I2CM_R_GET (((REG32(ADR_I2CM_LEN)) & 0x07000000 ) >> 24)
+#define GET_I2CM_WDAT (((REG32(ADR_I2CM_WDAT)) & 0xffffffff ) >> 0)
+#define GET_I2CM_RDAT (((REG32(ADR_I2CM_RDAT)) & 0xffffffff ) >> 0)
+#define GET_I2CM_SR_LEN (((REG32(ADR_I2CM_EN_2)) & 0x0000ffff ) >> 0)
+#define GET_I2CM_SR_RX (((REG32(ADR_I2CM_EN_2)) & 0x00010000 ) >> 16)
+#define GET_I2CM_REPEAT_START (((REG32(ADR_I2CM_EN_2)) & 0x00020000 ) >> 17)
+#define GET_UART_DATA (((REG32(ADR_UART_DATA)) & 0x000000ff ) >> 0)
+#define GET_DATA_RDY_IE (((REG32(ADR_UART_IER)) & 0x00000001 ) >> 0)
+#define GET_THR_EMPTY_IE (((REG32(ADR_UART_IER)) & 0x00000002 ) >> 1)
+#define GET_RX_LINESTS_IE (((REG32(ADR_UART_IER)) & 0x00000004 ) >> 2)
+#define GET_MDM_STS_IE (((REG32(ADR_UART_IER)) & 0x00000008 ) >> 3)
+#define GET_DMA_RXEND_IE (((REG32(ADR_UART_IER)) & 0x00000040 ) >> 6)
+#define GET_DMA_TXEND_IE (((REG32(ADR_UART_IER)) & 0x00000080 ) >> 7)
+#define GET_FIFO_EN (((REG32(ADR_UART_FCR)) & 0x00000001 ) >> 0)
+#define GET_RXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000002 ) >> 1)
+#define GET_TXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000004 ) >> 2)
+#define GET_DMA_MODE (((REG32(ADR_UART_FCR)) & 0x00000008 ) >> 3)
+#define GET_EN_AUTO_RTS (((REG32(ADR_UART_FCR)) & 0x00000010 ) >> 4)
+#define GET_EN_AUTO_CTS (((REG32(ADR_UART_FCR)) & 0x00000020 ) >> 5)
+#define GET_RXFIFO_TRGLVL (((REG32(ADR_UART_FCR)) & 0x000000c0 ) >> 6)
+#define GET_WORD_LEN (((REG32(ADR_UART_LCR)) & 0x00000003 ) >> 0)
+#define GET_STOP_BIT (((REG32(ADR_UART_LCR)) & 0x00000004 ) >> 2)
+#define GET_PARITY_EN (((REG32(ADR_UART_LCR)) & 0x00000008 ) >> 3)
+#define GET_EVEN_PARITY (((REG32(ADR_UART_LCR)) & 0x00000010 ) >> 4)
+#define GET_FORCE_PARITY (((REG32(ADR_UART_LCR)) & 0x00000020 ) >> 5)
+#define GET_SET_BREAK (((REG32(ADR_UART_LCR)) & 0x00000040 ) >> 6)
+#define GET_DLAB (((REG32(ADR_UART_LCR)) & 0x00000080 ) >> 7)
+#define GET_DTR (((REG32(ADR_UART_MCR)) & 0x00000001 ) >> 0)
+#define GET_RTS (((REG32(ADR_UART_MCR)) & 0x00000002 ) >> 1)
+#define GET_OUT_1 (((REG32(ADR_UART_MCR)) & 0x00000004 ) >> 2)
+#define GET_OUT_2 (((REG32(ADR_UART_MCR)) & 0x00000008 ) >> 3)
+#define GET_LOOP_BACK (((REG32(ADR_UART_MCR)) & 0x00000010 ) >> 4)
+#define GET_DATA_RDY (((REG32(ADR_UART_LSR)) & 0x00000001 ) >> 0)
+#define GET_OVERRUN_ERR (((REG32(ADR_UART_LSR)) & 0x00000002 ) >> 1)
+#define GET_PARITY_ERR (((REG32(ADR_UART_LSR)) & 0x00000004 ) >> 2)
+#define GET_FRAMING_ERR (((REG32(ADR_UART_LSR)) & 0x00000008 ) >> 3)
+#define GET_BREAK_INT (((REG32(ADR_UART_LSR)) & 0x00000010 ) >> 4)
+#define GET_THR_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000020 ) >> 5)
+#define GET_TX_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000040 ) >> 6)
+#define GET_FIFODATA_ERR (((REG32(ADR_UART_LSR)) & 0x00000080 ) >> 7)
+#define GET_DELTA_CTS (((REG32(ADR_UART_MSR)) & 0x00000001 ) >> 0)
+#define GET_DELTA_DSR (((REG32(ADR_UART_MSR)) & 0x00000002 ) >> 1)
+#define GET_TRAILEDGE_RI (((REG32(ADR_UART_MSR)) & 0x00000004 ) >> 2)
+#define GET_DELTA_CD (((REG32(ADR_UART_MSR)) & 0x00000008 ) >> 3)
+#define GET_CTS (((REG32(ADR_UART_MSR)) & 0x00000010 ) >> 4)
+#define GET_DSR (((REG32(ADR_UART_MSR)) & 0x00000020 ) >> 5)
+#define GET_RI (((REG32(ADR_UART_MSR)) & 0x00000040 ) >> 6)
+#define GET_CD (((REG32(ADR_UART_MSR)) & 0x00000080 ) >> 7)
+#define GET_BRDC_DIV (((REG32(ADR_UART_SPR)) & 0x0000ffff ) >> 0)
+#define GET_RTHR_L (((REG32(ADR_UART_RTHR)) & 0x0000000f ) >> 0)
+#define GET_RTHR_H (((REG32(ADR_UART_RTHR)) & 0x000000f0 ) >> 4)
+#define GET_INT_IDCODE (((REG32(ADR_UART_ISR)) & 0x0000000f ) >> 0)
+#define GET_FIFOS_ENABLED (((REG32(ADR_UART_ISR)) & 0x000000c0 ) >> 6)
+#define GET_DAT_UART_DATA (((REG32(ADR_DAT_UART_DATA)) & 0x000000ff ) >> 0)
+#define GET_DAT_DATA_RDY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000001 ) >> 0)
+#define GET_DAT_THR_EMPTY_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000002 ) >> 1)
+#define GET_DAT_RX_LINESTS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000004 ) >> 2)
+#define GET_DAT_MDM_STS_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000008 ) >> 3)
+#define GET_DAT_DMA_RXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000040 ) >> 6)
+#define GET_DAT_DMA_TXEND_IE (((REG32(ADR_DAT_UART_IER)) & 0x00000080 ) >> 7)
+#define GET_DAT_FIFO_EN (((REG32(ADR_DAT_UART_FCR)) & 0x00000001 ) >> 0)
+#define GET_DAT_RXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000002 ) >> 1)
+#define GET_DAT_TXFIFO_RST (((REG32(ADR_DAT_UART_FCR)) & 0x00000004 ) >> 2)
+#define GET_DAT_DMA_MODE (((REG32(ADR_DAT_UART_FCR)) & 0x00000008 ) >> 3)
+#define GET_DAT_EN_AUTO_RTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000010 ) >> 4)
+#define GET_DAT_EN_AUTO_CTS (((REG32(ADR_DAT_UART_FCR)) & 0x00000020 ) >> 5)
+#define GET_DAT_RXFIFO_TRGLVL (((REG32(ADR_DAT_UART_FCR)) & 0x000000c0 ) >> 6)
+#define GET_DAT_WORD_LEN (((REG32(ADR_DAT_UART_LCR)) & 0x00000003 ) >> 0)
+#define GET_DAT_STOP_BIT (((REG32(ADR_DAT_UART_LCR)) & 0x00000004 ) >> 2)
+#define GET_DAT_PARITY_EN (((REG32(ADR_DAT_UART_LCR)) & 0x00000008 ) >> 3)
+#define GET_DAT_EVEN_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000010 ) >> 4)
+#define GET_DAT_FORCE_PARITY (((REG32(ADR_DAT_UART_LCR)) & 0x00000020 ) >> 5)
+#define GET_DAT_SET_BREAK (((REG32(ADR_DAT_UART_LCR)) & 0x00000040 ) >> 6)
+#define GET_DAT_DLAB (((REG32(ADR_DAT_UART_LCR)) & 0x00000080 ) >> 7)
+#define GET_DAT_DTR (((REG32(ADR_DAT_UART_MCR)) & 0x00000001 ) >> 0)
+#define GET_DAT_RTS (((REG32(ADR_DAT_UART_MCR)) & 0x00000002 ) >> 1)
+#define GET_DAT_OUT_1 (((REG32(ADR_DAT_UART_MCR)) & 0x00000004 ) >> 2)
+#define GET_DAT_OUT_2 (((REG32(ADR_DAT_UART_MCR)) & 0x00000008 ) >> 3)
+#define GET_DAT_LOOP_BACK (((REG32(ADR_DAT_UART_MCR)) & 0x00000010 ) >> 4)
+#define GET_DAT_DATA_RDY (((REG32(ADR_DAT_UART_LSR)) & 0x00000001 ) >> 0)
+#define GET_DAT_OVERRUN_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000002 ) >> 1)
+#define GET_DAT_PARITY_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000004 ) >> 2)
+#define GET_DAT_FRAMING_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000008 ) >> 3)
+#define GET_DAT_BREAK_INT (((REG32(ADR_DAT_UART_LSR)) & 0x00000010 ) >> 4)
+#define GET_DAT_THR_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000020 ) >> 5)
+#define GET_DAT_TX_EMPTY (((REG32(ADR_DAT_UART_LSR)) & 0x00000040 ) >> 6)
+#define GET_DAT_FIFODATA_ERR (((REG32(ADR_DAT_UART_LSR)) & 0x00000080 ) >> 7)
+#define GET_DAT_DELTA_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000001 ) >> 0)
+#define GET_DAT_DELTA_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000002 ) >> 1)
+#define GET_DAT_TRAILEDGE_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000004 ) >> 2)
+#define GET_DAT_DELTA_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000008 ) >> 3)
+#define GET_DAT_CTS (((REG32(ADR_DAT_UART_MSR)) & 0x00000010 ) >> 4)
+#define GET_DAT_DSR (((REG32(ADR_DAT_UART_MSR)) & 0x00000020 ) >> 5)
+#define GET_DAT_RI (((REG32(ADR_DAT_UART_MSR)) & 0x00000040 ) >> 6)
+#define GET_DAT_CD (((REG32(ADR_DAT_UART_MSR)) & 0x00000080 ) >> 7)
+#define GET_DAT_BRDC_DIV (((REG32(ADR_DAT_UART_SPR)) & 0x0000ffff ) >> 0)
+#define GET_DAT_RTHR_L (((REG32(ADR_DAT_UART_RTHR)) & 0x0000000f ) >> 0)
+#define GET_DAT_RTHR_H (((REG32(ADR_DAT_UART_RTHR)) & 0x000000f0 ) >> 4)
+#define GET_DAT_INT_IDCODE (((REG32(ADR_DAT_UART_ISR)) & 0x0000000f ) >> 0)
+#define GET_DAT_FIFOS_ENABLED (((REG32(ADR_DAT_UART_ISR)) & 0x000000c0 ) >> 6)
+#define GET_MASK_TOP (((REG32(ADR_INT_MASK)) & 0xffffffff ) >> 0)
+#define GET_INT_MODE (((REG32(ADR_INT_MODE)) & 0xffffffff ) >> 0)
+#define GET_IRQ_PHY_0 (((REG32(ADR_INT_IRQ_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_PHY_1 (((REG32(ADR_INT_IRQ_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_SDIO (((REG32(ADR_INT_IRQ_STS)) & 0x00000004 ) >> 2)
+#define GET_IRQ_BEACON_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000010 ) >> 4)
+#define GET_IRQ_PRE_BEACON (((REG32(ADR_INT_IRQ_STS)) & 0x00000020 ) >> 5)
+#define GET_IRQ_EDCA0_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000040 ) >> 6)
+#define GET_IRQ_EDCA1_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000080 ) >> 7)
+#define GET_IRQ_EDCA2_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000100 ) >> 8)
+#define GET_IRQ_EDCA3_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000200 ) >> 9)
+#define GET_IRQ_EDCA4_TX_DONE (((REG32(ADR_INT_IRQ_STS)) & 0x00000400 ) >> 10)
+#define GET_IRQ_BEACON_DTIM (((REG32(ADR_INT_IRQ_STS)) & 0x00001000 ) >> 12)
+#define GET_IRQ_EDCA0_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00002000 ) >> 13)
+#define GET_IRQ_EDCA1_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00004000 ) >> 14)
+#define GET_IRQ_EDCA2_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00008000 ) >> 15)
+#define GET_IRQ_EDCA3_LOWTHOLD_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00010000 ) >> 16)
+#define GET_IRQ_FENCE_HIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00020000 ) >> 17)
+#define GET_IRQ_ILL_ADDR_INT (((REG32(ADR_INT_IRQ_STS)) & 0x00040000 ) >> 18)
+#define GET_IRQ_MBOX (((REG32(ADR_INT_IRQ_STS)) & 0x00080000 ) >> 19)
+#define GET_IRQ_US_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x00100000 ) >> 20)
+#define GET_IRQ_US_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x00200000 ) >> 21)
+#define GET_IRQ_US_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x00400000 ) >> 22)
+#define GET_IRQ_US_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x00800000 ) >> 23)
+#define GET_IRQ_MS_TIMER0 (((REG32(ADR_INT_IRQ_STS)) & 0x01000000 ) >> 24)
+#define GET_IRQ_MS_TIMER1 (((REG32(ADR_INT_IRQ_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_MS_TIMER2 (((REG32(ADR_INT_IRQ_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_MS_TIMER3 (((REG32(ADR_INT_IRQ_STS)) & 0x08000000 ) >> 27)
+#define GET_IRQ_TX_LIMIT_INT (((REG32(ADR_INT_IRQ_STS)) & 0x10000000 ) >> 28)
+#define GET_IRQ_DMA0 (((REG32(ADR_INT_IRQ_STS)) & 0x20000000 ) >> 29)
+#define GET_IRQ_CO_DMA (((REG32(ADR_INT_IRQ_STS)) & 0x40000000 ) >> 30)
+#define GET_IRQ_PERI_GROUP (((REG32(ADR_INT_IRQ_STS)) & 0x80000000 ) >> 31)
+#define GET_FIQ_STATUS (((REG32(ADR_INT_FIQ_STS)) & 0xffffffff ) >> 0)
+#define GET_IRQ_RAW (((REG32(ADR_INT_IRQ_RAW)) & 0xffffffff ) >> 0)
+#define GET_FIQ_RAW (((REG32(ADR_INT_FIQ_RAW)) & 0xffffffff ) >> 0)
+#define GET_INT_PERI_MASK (((REG32(ADR_INT_PERI_MASK)) & 0xffffffff ) >> 0)
+#define GET_PERI_RTC (((REG32(ADR_INT_PERI_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_UART0_TX (((REG32(ADR_INT_PERI_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_UART0_RX (((REG32(ADR_INT_PERI_STS)) & 0x00000004 ) >> 2)
+#define GET_PERI_GPI_2 (((REG32(ADR_INT_PERI_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_SPI_IPC (((REG32(ADR_INT_PERI_STS)) & 0x00000010 ) >> 4)
+#define GET_PERI_GPI_1_0 (((REG32(ADR_INT_PERI_STS)) & 0x00000060 ) >> 5)
+#define GET_SCRT_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000080 ) >> 7)
+#define GET_MMU_ALC_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000100 ) >> 8)
+#define GET_MMU_RLS_ERR (((REG32(ADR_INT_PERI_STS)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000400 ) >> 10)
+#define GET_MBOX_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00000800 ) >> 11)
+#define GET_MBOX_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00001000 ) >> 12)
+#define GET_MBOX_INT_3 (((REG32(ADR_INT_PERI_STS)) & 0x00002000 ) >> 13)
+#define GET_HCI_INT_1 (((REG32(ADR_INT_PERI_STS)) & 0x00004000 ) >> 14)
+#define GET_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x00008000 ) >> 15)
+#define GET_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x00010000 ) >> 16)
+#define GET_ID_MNG_INT_2 (((REG32(ADR_INT_PERI_STS)) & 0x00020000 ) >> 17)
+#define GET_DMN_NOHIT_INT (((REG32(ADR_INT_PERI_STS)) & 0x00040000 ) >> 18)
+#define GET_ID_THOLD_RX (((REG32(ADR_INT_PERI_STS)) & 0x00080000 ) >> 19)
+#define GET_ID_THOLD_TX (((REG32(ADR_INT_PERI_STS)) & 0x00100000 ) >> 20)
+#define GET_ID_DOUBLE_RLS (((REG32(ADR_INT_PERI_STS)) & 0x00200000 ) >> 21)
+#define GET_RX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00400000 ) >> 22)
+#define GET_TX_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x00800000 ) >> 23)
+#define GET_ALL_ID_LEN_THOLD (((REG32(ADR_INT_PERI_STS)) & 0x01000000 ) >> 24)
+#define GET_DMN_MCU_INT (((REG32(ADR_INT_PERI_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_DAT_UART_TX (((REG32(ADR_INT_PERI_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_DAT_UART_RX (((REG32(ADR_INT_PERI_STS)) & 0x08000000 ) >> 27)
+#define GET_DAT_UART_RX_TIMEOUT (((REG32(ADR_INT_PERI_STS)) & 0x10000000 ) >> 28)
+#define GET_DAT_UART_MULTI_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x20000000 ) >> 29)
+#define GET_ALR_ABT_NOCHG_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x40000000 ) >> 30)
+#define GET_TBLNEQ_MNGPKT_INT_IRQ (((REG32(ADR_INT_PERI_STS)) & 0x80000000 ) >> 31)
+#define GET_INTR_PERI_RAW (((REG32(ADR_INT_PERI_RAW)) & 0xffffffff ) >> 0)
+#define GET_INTR_GPI00_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x00000003 ) >> 0)
+#define GET_INTR_GPI01_CFG (((REG32(ADR_INT_GPI_CFG)) & 0x0000000c ) >> 2)
+#define GET_SYS_RST_INT (((REG32(ADR_SYS_INT_FOR_HOST)) & 0x00000001 ) >> 0)
+#define GET_SPI_IPC_ADDR (((REG32(ADR_SPI_IPC)) & 0xffffffff ) >> 0)
+#define GET_SD_MASK_TOP (((REG32(ADR_SDIO_MASK)) & 0xffffffff ) >> 0)
+#define GET_IRQ_PHY_0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_PHY_1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_SDIO_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000004 ) >> 2)
+#define GET_IRQ_BEACON_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000010 ) >> 4)
+#define GET_IRQ_PRE_BEACON_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000020 ) >> 5)
+#define GET_IRQ_EDCA0_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000040 ) >> 6)
+#define GET_IRQ_EDCA1_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000080 ) >> 7)
+#define GET_IRQ_EDCA2_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000100 ) >> 8)
+#define GET_IRQ_EDCA3_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000200 ) >> 9)
+#define GET_IRQ_EDCA4_TX_DONE_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00000400 ) >> 10)
+#define GET_IRQ_BEACON_DTIM_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00001000 ) >> 12)
+#define GET_IRQ_EDCA0_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00002000 ) >> 13)
+#define GET_IRQ_EDCA1_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00004000 ) >> 14)
+#define GET_IRQ_EDCA2_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00008000 ) >> 15)
+#define GET_IRQ_EDCA3_LOWTHOLD_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00010000 ) >> 16)
+#define GET_IRQ_FENCE_HIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00020000 ) >> 17)
+#define GET_IRQ_ILL_ADDR_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00040000 ) >> 18)
+#define GET_IRQ_MBOX_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00080000 ) >> 19)
+#define GET_IRQ_US_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00100000 ) >> 20)
+#define GET_IRQ_US_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00200000 ) >> 21)
+#define GET_IRQ_US_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00400000 ) >> 22)
+#define GET_IRQ_US_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x00800000 ) >> 23)
+#define GET_IRQ_MS_TIMER0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x01000000 ) >> 24)
+#define GET_IRQ_MS_TIMER1_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_MS_TIMER2_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_MS_TIMER3_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x08000000 ) >> 27)
+#define GET_IRQ_TX_LIMIT_INT_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x10000000 ) >> 28)
+#define GET_IRQ_DMA0_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x20000000 ) >> 29)
+#define GET_IRQ_CO_DMA_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x40000000 ) >> 30)
+#define GET_IRQ_PERI_GROUP_SD (((REG32(ADR_SDIO_IRQ_STS)) & 0x80000000 ) >> 31)
+#define GET_INT_PERI_MASK_SD (((REG32(ADR_SD_PERI_MASK)) & 0xffffffff ) >> 0)
+#define GET_PERI_RTC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000001 ) >> 0)
+#define GET_IRQ_UART0_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000002 ) >> 1)
+#define GET_IRQ_UART0_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000004 ) >> 2)
+#define GET_PERI_GPI_SD_2 (((REG32(ADR_SD_PERI_STS)) & 0x00000008 ) >> 3)
+#define GET_IRQ_SPI_IPC_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000010 ) >> 4)
+#define GET_PERI_GPI_SD_1_0 (((REG32(ADR_SD_PERI_STS)) & 0x00000060 ) >> 5)
+#define GET_SCRT_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000080 ) >> 7)
+#define GET_MMU_ALC_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000100 ) >> 8)
+#define GET_MMU_RLS_ERR_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000400 ) >> 10)
+#define GET_MBOX_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00000800 ) >> 11)
+#define GET_MBOX_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00001000 ) >> 12)
+#define GET_MBOX_INT_3_SD (((REG32(ADR_SD_PERI_STS)) & 0x00002000 ) >> 13)
+#define GET_HCI_INT_1_SD (((REG32(ADR_SD_PERI_STS)) & 0x00004000 ) >> 14)
+#define GET_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00008000 ) >> 15)
+#define GET_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x00010000 ) >> 16)
+#define GET_ID_MNG_INT_2_SD (((REG32(ADR_SD_PERI_STS)) & 0x00020000 ) >> 17)
+#define GET_DMN_NOHIT_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x00040000 ) >> 18)
+#define GET_ID_THOLD_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00080000 ) >> 19)
+#define GET_ID_THOLD_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x00100000 ) >> 20)
+#define GET_ID_DOUBLE_RLS_SD (((REG32(ADR_SD_PERI_STS)) & 0x00200000 ) >> 21)
+#define GET_RX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00400000 ) >> 22)
+#define GET_TX_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x00800000 ) >> 23)
+#define GET_ALL_ID_LEN_THOLD_SD (((REG32(ADR_SD_PERI_STS)) & 0x01000000 ) >> 24)
+#define GET_DMN_MCU_INT_SD (((REG32(ADR_SD_PERI_STS)) & 0x02000000 ) >> 25)
+#define GET_IRQ_DAT_UART_TX_SD (((REG32(ADR_SD_PERI_STS)) & 0x04000000 ) >> 26)
+#define GET_IRQ_DAT_UART_RX_SD (((REG32(ADR_SD_PERI_STS)) & 0x08000000 ) >> 27)
+#define GET_DAT_UART_RX_TIMEOUT_SD (((REG32(ADR_SD_PERI_STS)) & 0x10000000 ) >> 28)
+#define GET_DAT_UART_MULTI_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x20000000 ) >> 29)
+#define GET_ALR_ABT_NOCHG_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x40000000 ) >> 30)
+#define GET_TBLNEQ_MNGPKT_INT_IRQ_SD (((REG32(ADR_SD_PERI_STS)) & 0x80000000 ) >> 31)
+#define GET_DBG_SPI_MODE (((REG32(ADR_DBG_SPI_MODE)) & 0xffffffff ) >> 0)
+#define GET_DBG_RX_QUOTA (((REG32(ADR_DBG_RX_QUOTA)) & 0x0000ffff ) >> 0)
+#define GET_DBG_CONDI_NUM (((REG32(ADR_DBG_CONDITION_NUMBER)) & 0x000000ff ) >> 0)
+#define GET_DBG_HOST_PATH (((REG32(ADR_DBG_HOST_PATH)) & 0x00000001 ) >> 0)
+#define GET_DBG_TX_SEG (((REG32(ADR_DBG_TX_SEG)) & 0xffffffff ) >> 0)
+#define GET_DBG_BRST_MODE (((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0x00000001 ) >> 0)
+#define GET_DBG_CLK_WIDTH (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0)
+#define GET_DBG_CSN_INTER (((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16)
+#define GET_DBG_BACK_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_DBG_FRONT_DLY (((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16)
+#define GET_DBG_RX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000002 ) >> 1)
+#define GET_DBG_RX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000004 ) >> 2)
+#define GET_DBG_TX_FIFO_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000008 ) >> 3)
+#define GET_DBG_TX_HOST_FAIL (((REG32(ADR_DBG_SPI_STS)) & 0x00000010 ) >> 4)
+#define GET_DBG_SPI_DOUBLE_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000020 ) >> 5)
+#define GET_DBG_SPI_TX_NO_ALLOC (((REG32(ADR_DBG_SPI_STS)) & 0x00000040 ) >> 6)
+#define GET_DBG_RDATA_RDY (((REG32(ADR_DBG_SPI_STS)) & 0x00000080 ) >> 7)
+#define GET_DBG_SPI_ALLOC_STATUS (((REG32(ADR_DBG_SPI_STS)) & 0x00000100 ) >> 8)
+#define GET_DBG_SPI_DBG_WR_FIFO_FULL (((REG32(ADR_DBG_SPI_STS)) & 0x00000200 ) >> 9)
+#define GET_DBG_RX_LEN (((REG32(ADR_DBG_SPI_STS)) & 0xffff0000 ) >> 16)
+#define GET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000007 ) >> 0)
+#define GET_DBG_SPI_HOST_TX_ALLOC_PKBUF (((REG32(ADR_DBG_TX_ALLOC_SET)) & 0x00000100 ) >> 8)
+#define GET_DBG_SPI_TX_ALLOC_SIZE (((REG32(ADR_DBG_TX_ALLOC)) & 0x000000ff ) >> 0)
+#define GET_DBG_RD_DAT_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff ) >> 0)
+#define GET_DBG_RD_STS_CNT (((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000 ) >> 16)
+#define GET_DBG_JUDGE_CNT (((REG32(ADR_DBG_DBG_CNT2)) & 0x0000ffff ) >> 0)
+#define GET_DBG_RD_STS_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00010000 ) >> 16)
+#define GET_DBG_RD_DAT_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00020000 ) >> 17)
+#define GET_DBG_JUDGE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT2)) & 0x00040000 ) >> 18)
+#define GET_DBG_TX_DONE_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TX_DISCARD_CNT (((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000 ) >> 16)
+#define GET_DBG_TX_SET_CNT (((REG32(ADR_DBG_DBG_CNT4)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TX_DISCARD_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00010000 ) >> 16)
+#define GET_DBG_TX_DONE_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00020000 ) >> 17)
+#define GET_DBG_TX_SET_CNT_CLR (((REG32(ADR_DBG_DBG_CNT4)) & 0x00040000 ) >> 18)
+#define GET_DBG_DAT_MODE_OFF (((REG32(ADR_DBG_DBG_CNT4)) & 0x00080000 ) >> 19)
+#define GET_DBG_TX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x00700000 ) >> 20)
+#define GET_DBG_RX_FIFO_RESIDUE (((REG32(ADR_DBG_DBG_CNT4)) & 0x07000000 ) >> 24)
+#define GET_DBG_RX_RDY (((REG32(ADR_DBG_INT_TAG)) & 0x00000001 ) >> 0)
+#define GET_DBG_SDIO_SYS_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000004 ) >> 2)
+#define GET_DBG_EDCA0_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000008 ) >> 3)
+#define GET_DBG_EDCA1_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000010 ) >> 4)
+#define GET_DBG_EDCA2_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000020 ) >> 5)
+#define GET_DBG_EDCA3_LOWTHOLD_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00000040 ) >> 6)
+#define GET_DBG_TX_LIMIT_INT_IN (((REG32(ADR_DBG_INT_TAG)) & 0x00000080 ) >> 7)
+#define GET_DBG_SPI_FN1 (((REG32(ADR_DBG_INT_TAG)) & 0x00007f00 ) >> 8)
+#define GET_DBG_SPI_CLK_EN_INT (((REG32(ADR_DBG_INT_TAG)) & 0x00008000 ) >> 15)
+#define GET_DBG_SPI_HOST_MASK (((REG32(ADR_DBG_INT_TAG)) & 0x00ff0000 ) >> 16)
+#define GET_BOOT_ADDR (((REG32(ADR_BOOT_ADDR)) & 0x00ffffff ) >> 0)
+#define GET_CHECK_SUM_FAIL (((REG32(ADR_BOOT_ADDR)) & 0x80000000 ) >> 31)
+#define GET_VERIFY_DATA (((REG32(ADR_VERIFY_DATA)) & 0xffffffff ) >> 0)
+#define GET_FLASH_ADDR (((REG32(ADR_FLASH_ADDR)) & 0x00ffffff ) >> 0)
+#define GET_FLASH_CMD_CLR (((REG32(ADR_FLASH_ADDR)) & 0x10000000 ) >> 28)
+#define GET_FLASH_DMA_CLR (((REG32(ADR_FLASH_ADDR)) & 0x20000000 ) >> 29)
+#define GET_DMA_EN (((REG32(ADR_FLASH_ADDR)) & 0x40000000 ) >> 30)
+#define GET_DMA_BUSY (((REG32(ADR_FLASH_ADDR)) & 0x80000000 ) >> 31)
+#define GET_SRAM_ADDR (((REG32(ADR_SRAM_ADDR)) & 0xffffffff ) >> 0)
+#define GET_FLASH_DMA_LEN (((REG32(ADR_LEN)) & 0xffffffff ) >> 0)
+#define GET_FLASH_FRONT_DLY (((REG32(ADR_SPI_PARAM)) & 0x0000ffff ) >> 0)
+#define GET_FLASH_BACK_DLY (((REG32(ADR_SPI_PARAM)) & 0xffff0000 ) >> 16)
+#define GET_FLASH_CLK_WIDTH (((REG32(ADR_SPI_PARAM2)) & 0x0000ffff ) >> 0)
+#define GET_SPI_BUSY (((REG32(ADR_SPI_PARAM2)) & 0x00010000 ) >> 16)
+#define GET_FLS_REMAP (((REG32(ADR_SPI_PARAM2)) & 0x00020000 ) >> 17)
+#define GET_PBUS_SWP (((REG32(ADR_SPI_PARAM2)) & 0x00040000 ) >> 18)
+#define GET_BIT_MODE1 (((REG32(ADR_SPI_PARAM2)) & 0x00080000 ) >> 19)
+#define GET_BIT_MODE2 (((REG32(ADR_SPI_PARAM2)) & 0x00100000 ) >> 20)
+#define GET_BIT_MODE4 (((REG32(ADR_SPI_PARAM2)) & 0x00200000 ) >> 21)
+#define GET_BOOT_CHECK_SUM (((REG32(ADR_CHECK_SUM_RESULT)) & 0xffffffff ) >> 0)
+#define GET_CHECK_SUM_TAG (((REG32(ADR_CHECK_SUM_IN_FILE)) & 0xffffffff ) >> 0)
+#define GET_CMD_LEN (((REG32(ADR_COMMAND_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CMD_ADDR (((REG32(ADR_COMMAND_ADDR)) & 0xffffffff ) >> 0)
+#define GET_DMA_ADR_SRC (((REG32(ADR_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
+#define GET_DMA_ADR_DST (((REG32(ADR_DMA_ADR_DST)) & 0xffffffff ) >> 0)
+#define GET_DMA_SRC_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000007 ) >> 0)
+#define GET_DMA_SRC_INC (((REG32(ADR_DMA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_DMA_DST_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000070 ) >> 4)
+#define GET_DMA_DST_INC (((REG32(ADR_DMA_CTRL)) & 0x00000080 ) >> 7)
+#define GET_DMA_FAST_FILL (((REG32(ADR_DMA_CTRL)) & 0x00000100 ) >> 8)
+#define GET_DMA_SDIO_KICK (((REG32(ADR_DMA_CTRL)) & 0x00001000 ) >> 12)
+#define GET_DMA_BADR_EN (((REG32(ADR_DMA_CTRL)) & 0x00002000 ) >> 13)
+#define GET_DMA_LEN (((REG32(ADR_DMA_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_DMA_INT_MASK (((REG32(ADR_DMA_INT)) & 0x00000001 ) >> 0)
+#define GET_DMA_STS (((REG32(ADR_DMA_INT)) & 0x00000100 ) >> 8)
+#define GET_DMA_FINISH (((REG32(ADR_DMA_INT)) & 0x80000000 ) >> 31)
+#define GET_DMA_CONST (((REG32(ADR_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
+#define GET_SLEEP_WAKE_CNT (((REG32(ADR_PMU_0)) & 0x00ffffff ) >> 0)
+#define GET_RG_DLDO_LEVEL (((REG32(ADR_PMU_0)) & 0x07000000 ) >> 24)
+#define GET_RG_DLDO_BOOST_IQ (((REG32(ADR_PMU_0)) & 0x08000000 ) >> 27)
+#define GET_RG_BUCK_LEVEL (((REG32(ADR_PMU_0)) & 0x70000000 ) >> 28)
+#define GET_RG_BUCK_VREF_SEL (((REG32(ADR_PMU_0)) & 0x80000000 ) >> 31)
+#define GET_RG_RTC_OSC_RES_SW_MANUAL (((REG32(ADR_PMU_1)) & 0x000003ff ) >> 0)
+#define GET_RG_RTC_OSC_RES_SW (((REG32(ADR_PMU_1)) & 0x03ff0000 ) >> 16)
+#define GET_RTC_OSC_CAL_RES_RDY (((REG32(ADR_PMU_1)) & 0x80000000 ) >> 31)
+#define GET_RG_DCDC_MODE (((REG32(ADR_PMU_2)) & 0x00000001 ) >> 0)
+#define GET_RG_BUCK_EN_PSM (((REG32(ADR_PMU_2)) & 0x00000010 ) >> 4)
+#define GET_RG_BUCK_PSM_VTH (((REG32(ADR_PMU_2)) & 0x00000100 ) >> 8)
+#define GET_RG_RTC_OSC_RES_SW_MANUAL_EN (((REG32(ADR_PMU_2)) & 0x00001000 ) >> 12)
+#define GET_RG_RTC_RDY_DEGLITCH_TIMER (((REG32(ADR_PMU_2)) & 0x00006000 ) >> 13)
+#define GET_RTC_CAL_ENA (((REG32(ADR_PMU_2)) & 0x00010000 ) >> 16)
+#define GET_PMU_WAKE_TRIG_EVENT (((REG32(ADR_PMU_3)) & 0x00000003 ) >> 0)
+#define GET_DIGI_TOP_POR_MASK (((REG32(ADR_PMU_3)) & 0x00000010 ) >> 4)
+#define GET_PMU_ENTER_SLEEP_MODE (((REG32(ADR_PMU_3)) & 0x00000100 ) >> 8)
+#define GET_RG_RTC_DUMMIES (((REG32(ADR_PMU_3)) & 0xffff0000 ) >> 16)
+#define GET_RTC_EN (((REG32(ADR_RTC_1)) & 0x00000001 ) >> 0)
+#define GET_RTC_SRC (((REG32(ADR_RTC_1)) & 0x00000002 ) >> 1)
+#define GET_RTC_TICK_CNT (((REG32(ADR_RTC_1)) & 0x7fff0000 ) >> 16)
+#define GET_RTC_INT_SEC_MASK (((REG32(ADR_RTC_2)) & 0x00000001 ) >> 0)
+#define GET_RTC_INT_ALARM_MASK (((REG32(ADR_RTC_2)) & 0x00000002 ) >> 1)
+#define GET_RTC_INT_SEC (((REG32(ADR_RTC_2)) & 0x00010000 ) >> 16)
+#define GET_RTC_INT_ALARM (((REG32(ADR_RTC_2)) & 0x00020000 ) >> 17)
+#define GET_RTC_SEC_START_CNT (((REG32(ADR_RTC_3W)) & 0xffffffff ) >> 0)
+#define GET_RTC_SEC_CNT (((REG32(ADR_RTC_3R)) & 0xffffffff ) >> 0)
+#define GET_RTC_SEC_ALARM_VALUE (((REG32(ADR_RTC_4)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_ADR_SRC (((REG32(ADR_D2_DMA_ADR_SRC)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_ADR_DST (((REG32(ADR_D2_DMA_ADR_DST)) & 0xffffffff ) >> 0)
+#define GET_D2_DMA_SRC_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000007 ) >> 0)
+#define GET_D2_DMA_SRC_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_D2_DMA_DST_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000070 ) >> 4)
+#define GET_D2_DMA_DST_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000080 ) >> 7)
+#define GET_D2_DMA_FAST_FILL (((REG32(ADR_D2_DMA_CTRL)) & 0x00000100 ) >> 8)
+#define GET_D2_DMA_SDIO_KICK (((REG32(ADR_D2_DMA_CTRL)) & 0x00001000 ) >> 12)
+#define GET_D2_DMA_BADR_EN (((REG32(ADR_D2_DMA_CTRL)) & 0x00002000 ) >> 13)
+#define GET_D2_DMA_LEN (((REG32(ADR_D2_DMA_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_D2_DMA_INT_MASK (((REG32(ADR_D2_DMA_INT)) & 0x00000001 ) >> 0)
+#define GET_D2_DMA_STS (((REG32(ADR_D2_DMA_INT)) & 0x00000100 ) >> 8)
+#define GET_D2_DMA_FINISH (((REG32(ADR_D2_DMA_INT)) & 0x80000000 ) >> 31)
+#define GET_D2_DMA_CONST (((REG32(ADR_D2_DMA_FILL_CONST)) & 0xffffffff ) >> 0)
+#define GET_TRAP_UNKNOWN_TYPE (((REG32(ADR_CONTROL)) & 0x00000001 ) >> 0)
+#define GET_TX_ON_DEMAND_ENA (((REG32(ADR_CONTROL)) & 0x00000002 ) >> 1)
+#define GET_RX_2_HOST (((REG32(ADR_CONTROL)) & 0x00000004 ) >> 2)
+#define GET_AUTO_SEQNO (((REG32(ADR_CONTROL)) & 0x00000008 ) >> 3)
+#define GET_BYPASSS_TX_PARSER_ENCAP (((REG32(ADR_CONTROL)) & 0x00000010 ) >> 4)
+#define GET_HDR_STRIP (((REG32(ADR_CONTROL)) & 0x00000020 ) >> 5)
+#define GET_ERP_PROTECT (((REG32(ADR_CONTROL)) & 0x000000c0 ) >> 6)
+#define GET_PRO_VER (((REG32(ADR_CONTROL)) & 0x00000300 ) >> 8)
+#define GET_TXQ_ID0 (((REG32(ADR_CONTROL)) & 0x00007000 ) >> 12)
+#define GET_TXQ_ID1 (((REG32(ADR_CONTROL)) & 0x00070000 ) >> 16)
+#define GET_TX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00100000 ) >> 20)
+#define GET_RX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00200000 ) >> 21)
+#define GET_RX_NULL_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00400000 ) >> 22)
+#define GET_RX_GET_TX_QUEUE_EN (((REG32(ADR_CONTROL)) & 0x02000000 ) >> 25)
+#define GET_HCI_INQ_SEL (((REG32(ADR_CONTROL)) & 0x04000000 ) >> 26)
+#define GET_TRX_DEBUG_CNT_ENA (((REG32(ADR_CONTROL)) & 0x10000000 ) >> 28)
+#define GET_WAKE_SOON_WITH_SCK (((REG32(ADR_SDIO_WAKE_MODE)) & 0x00000001 ) >> 0)
+#define GET_TX_FLOW_CTRL (((REG32(ADR_TX_FLOW_0)) & 0x0000ffff ) >> 0)
+#define GET_TX_FLOW_MGMT (((REG32(ADR_TX_FLOW_0)) & 0xffff0000 ) >> 16)
+#define GET_TX_FLOW_DATA (((REG32(ADR_TX_FLOW_1)) & 0xffffffff ) >> 0)
+#define GET_DOT11RTSTHRESHOLD (((REG32(ADR_THREASHOLD)) & 0xffff0000 ) >> 16)
+#define GET_TXF_ID (((REG32(ADR_TXFID_INCREASE)) & 0x0000003f ) >> 0)
+#define GET_SEQ_CTRL (((REG32(ADR_GLOBAL_SEQUENCE)) & 0x0000ffff ) >> 0)
+#define GET_TX_PBOFFSET (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x000000ff ) >> 0)
+#define GET_TX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x0000ff00 ) >> 8)
+#define GET_RX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ff0000 ) >> 16)
+#define GET_RX_LAST_PHY_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff000000 ) >> 24)
+#define GET_TX_INFO_CLEAR_SIZE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x0000003f ) >> 0)
+#define GET_TX_INFO_CLEAR_ENABLE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x00000100 ) >> 8)
+#define GET_TXTRAP_ETHTYPE1 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
+#define GET_TXTRAP_ETHTYPE0 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
+#define GET_RXTRAP_ETHTYPE1 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0)
+#define GET_RXTRAP_ETHTYPE0 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16)
+#define GET_TX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0xffffffff ) >> 0)
+#define GET_RX_PKT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0xffffffff ) >> 0)
+#define GET_HOST_CMD_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0x000000ff ) >> 0)
+#define GET_HOST_EVENT_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0x000000ff ) >> 0)
+#define GET_TX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0x000000ff ) >> 0)
+#define GET_RX_PKT_DROP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0x000000ff ) >> 0)
+#define GET_TX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0x000000ff ) >> 0)
+#define GET_RX_PKT_TRAP_COUNTER (((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0x000000ff ) >> 0)
+#define GET_HOST_TX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0x000000ff ) >> 0)
+#define GET_HOST_RX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0x000000ff ) >> 0)
+#define GET_HCI_STATE_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0xffffffff ) >> 0)
+#define GET_HCI_ST_TIMEOUT_MONITOR (((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0xffffffff ) >> 0)
+#define GET_TX_ON_DEMAND_LENGTH (((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0xffffffff ) >> 0)
+#define GET_HCI_MONITOR_REG1 (((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0xffffffff ) >> 0)
+#define GET_HCI_MONITOR_REG2 (((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_TIME_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_TIME_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x0000ffff ) >> 0)
+#define GET_HCI_MB_MAX_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0x00ff0000 ) >> 16)
+#define GET_HCI_TX_ALLOC_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0xffffffff ) >> 0)
+#define GET_HCI_TX_ALLOC_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x0000ffff ) >> 0)
+#define GET_HCI_PROC_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ff0000 ) >> 16)
+#define GET_SDIO_TRANS_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff000000 ) >> 24)
+#define GET_SDIO_TX_INVALID_CNT_31_0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0xffffffff ) >> 0)
+#define GET_SDIO_TX_INVALID_CNT_47_32 (((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0x0000ffff ) >> 0)
+#define GET_CS_START_ADDR (((REG32(ADR_CS_START_ADDR)) & 0x0000ffff ) >> 0)
+#define GET_CS_PKT_ID (((REG32(ADR_CS_START_ADDR)) & 0x007f0000 ) >> 16)
+#define GET_ADD_LEN (((REG32(ADR_CS_ADD_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CS_ADDER_EN (((REG32(ADR_CS_CMD)) & 0x00000001 ) >> 0)
+#define GET_PSEUDO (((REG32(ADR_CS_CMD)) & 0x00000002 ) >> 1)
+#define GET_CALCULATE (((REG32(ADR_CS_INI_BUF)) & 0xffffffff ) >> 0)
+#define GET_L4_LEN (((REG32(ADR_CS_PSEUDO_BUF)) & 0x0000ffff ) >> 0)
+#define GET_L4_PROTOL (((REG32(ADR_CS_PSEUDO_BUF)) & 0x00ff0000 ) >> 16)
+#define GET_CHECK_SUM (((REG32(ADR_CS_CHECK_SUM)) & 0x0000ffff ) >> 0)
+#define GET_RAND_EN (((REG32(ADR_RAND_EN)) & 0x00000001 ) >> 0)
+#define GET_RAND_NUM (((REG32(ADR_RAND_NUM)) & 0xffffffff ) >> 0)
+#define GET_MUL_OP1 (((REG32(ADR_MUL_OP1)) & 0xffffffff ) >> 0)
+#define GET_MUL_OP2 (((REG32(ADR_MUL_OP2)) & 0xffffffff ) >> 0)
+#define GET_MUL_ANS0 (((REG32(ADR_MUL_ANS0)) & 0xffffffff ) >> 0)
+#define GET_MUL_ANS1 (((REG32(ADR_MUL_ANS1)) & 0xffffffff ) >> 0)
+#define GET_RD_ADDR (((REG32(ADR_DMA_RDATA)) & 0x0000ffff ) >> 0)
+#define GET_RD_ID (((REG32(ADR_DMA_RDATA)) & 0x007f0000 ) >> 16)
+#define GET_WR_ADDR (((REG32(ADR_DMA_WDATA)) & 0x0000ffff ) >> 0)
+#define GET_WR_ID (((REG32(ADR_DMA_WDATA)) & 0x007f0000 ) >> 16)
+#define GET_LEN (((REG32(ADR_DMA_LEN)) & 0x0000ffff ) >> 0)
+#define GET_CLR (((REG32(ADR_DMA_CLR)) & 0x00000001 ) >> 0)
+#define GET_PHY_MODE (((REG32(ADR_NAV_DATA)) & 0x00000003 ) >> 0)
+#define GET_SHRT_PREAM (((REG32(ADR_NAV_DATA)) & 0x00000004 ) >> 2)
+#define GET_SHRT_GI (((REG32(ADR_NAV_DATA)) & 0x00000008 ) >> 3)
+#define GET_DATA_RATE (((REG32(ADR_NAV_DATA)) & 0x000007f0 ) >> 4)
+#define GET_MCS (((REG32(ADR_NAV_DATA)) & 0x00007000 ) >> 12)
+#define GET_FRAME_LEN (((REG32(ADR_NAV_DATA)) & 0xffff0000 ) >> 16)
+#define GET_DURATION (((REG32(ADR_CO_NAV)) & 0x0000ffff ) >> 0)
+#define GET_SHA_DST_ADDR (((REG32(ADR_SHA_DST_ADDR)) & 0xffffffff ) >> 0)
+#define GET_SHA_SRC_ADDR (((REG32(ADR_SHA_SRC_ADDR)) & 0xffffffff ) >> 0)
+#define GET_SHA_BUSY (((REG32(ADR_SHA_SETTING)) & 0x00000001 ) >> 0)
+#define GET_SHA_ENDIAN (((REG32(ADR_SHA_SETTING)) & 0x00000002 ) >> 1)
+#define GET_EFS_CLKFREQ (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00000fff ) >> 0)
+#define GET_LOW_ACTIVE (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00010000 ) >> 16)
+#define GET_EFS_CLKFREQ_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0ff00000 ) >> 20)
+#define GET_EFS_PRE_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf0000000 ) >> 28)
+#define GET_EFS_LDO_ON (((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff ) >> 0)
+#define GET_EFS_LDO_OFF (((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000 ) >> 16)
+#define GET_EFS_RDATA_0 (((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_0 (((REG32(ADR_EFUSE_WDATA_0)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_1 (((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_1 (((REG32(ADR_EFUSE_WDATA_1)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_2 (((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_2 (((REG32(ADR_EFUSE_WDATA_2)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_3 (((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_3 (((REG32(ADR_EFUSE_WDATA_3)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_4 (((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_4 (((REG32(ADR_EFUSE_WDATA_4)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_5 (((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_5 (((REG32(ADR_EFUSE_WDATA_5)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_6 (((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_6 (((REG32(ADR_EFUSE_WDATA_6)) & 0xffffffff ) >> 0)
+#define GET_EFS_RDATA_7 (((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0xffffffff ) >> 0)
+#define GET_EFS_WDATA_7 (((REG32(ADR_EFUSE_WDATA_7)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RD0_EN (((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD1_EN (((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD2_EN (((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD3_EN (((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD4_EN (((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD5_EN (((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD6_EN (((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RD7_EN (((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RBUSY (((REG32(ADR_EFUSE_SPI_BUSY)) & 0x00000001 ) >> 0)
+#define GET_EFS_SPI_RDATA_0 (((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_1 (((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_2 (((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_3 (((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_4 (((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_5 (((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_6 (((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0xffffffff ) >> 0)
+#define GET_EFS_SPI_RDATA_7 (((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0xffffffff ) >> 0)
+#define GET_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000001 ) >> 0)
+#define GET_FORCE_GET_RK (((REG32(ADR_SMS4_CFG1)) & 0x00000002 ) >> 1)
+#define GET_SMS4_DESCRY_EN (((REG32(ADR_SMS4_CFG1)) & 0x00000010 ) >> 4)
+#define GET_DEC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000001 ) >> 0)
+#define GET_DEC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000002 ) >> 1)
+#define GET_ENC_DOUT_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000004 ) >> 2)
+#define GET_ENC_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000008 ) >> 3)
+#define GET_KEY_DIN_MSB (((REG32(ADR_SMS4_CFG2)) & 0x00000010 ) >> 4)
+#define GET_SMS4_CBC_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000001 ) >> 0)
+#define GET_SMS4_CFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000002 ) >> 1)
+#define GET_SMS4_OFB_EN (((REG32(ADR_SMS4_MODE1)) & 0x00000004 ) >> 2)
+#define GET_SMS4_START_TRIG (((REG32(ADR_SMS4_TRIG)) & 0x00000001 ) >> 0)
+#define GET_SMS4_BUSY (((REG32(ADR_SMS4_STATUS1)) & 0x00000001 ) >> 0)
+#define GET_SMS4_DONE (((REG32(ADR_SMS4_STATUS2)) & 0x00000001 ) >> 0)
+#define GET_SMS4_DATAIN_0 (((REG32(ADR_SMS4_DATA_IN0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAIN_1 (((REG32(ADR_SMS4_DATA_IN1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAIN_2 (((REG32(ADR_SMS4_DATA_IN2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAIN_3 (((REG32(ADR_SMS4_DATA_IN3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_0 (((REG32(ADR_SMS4_DATA_OUT0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_1 (((REG32(ADR_SMS4_DATA_OUT1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_2 (((REG32(ADR_SMS4_DATA_OUT2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_DATAOUT_3 (((REG32(ADR_SMS4_DATA_OUT3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_0 (((REG32(ADR_SMS4_KEY_0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_1 (((REG32(ADR_SMS4_KEY_1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_2 (((REG32(ADR_SMS4_KEY_2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_KEY_3 (((REG32(ADR_SMS4_KEY_3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV0 (((REG32(ADR_SMS4_MODE_IV0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV1 (((REG32(ADR_SMS4_MODE_IV1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV2 (((REG32(ADR_SMS4_MODE_IV2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_MODE_IV3 (((REG32(ADR_SMS4_MODE_IV3)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC0 (((REG32(ADR_SMS4_OFB_ENC0)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC1 (((REG32(ADR_SMS4_OFB_ENC1)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC2 (((REG32(ADR_SMS4_OFB_ENC2)) & 0xffffffff ) >> 0)
+#define GET_SMS4_OFB_ENC3 (((REG32(ADR_SMS4_OFB_ENC3)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB0_31_0 (((REG32(ADR_MRX_MCAST_TB0_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB0_47_32 (((REG32(ADR_MRX_MCAST_TB0_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK0_31_0 (((REG32(ADR_MRX_MCAST_MK0_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK0_47_32 (((REG32(ADR_MRX_MCAST_MK0_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_0 (((REG32(ADR_MRX_MCAST_CTRL0)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB1_31_0 (((REG32(ADR_MRX_MCAST_TB1_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB1_47_32 (((REG32(ADR_MRX_MCAST_TB1_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK1_31_0 (((REG32(ADR_MRX_MCAST_MK1_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK1_47_32 (((REG32(ADR_MRX_MCAST_MK1_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_1 (((REG32(ADR_MRX_MCAST_CTRL1)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB2_31_0 (((REG32(ADR_MRX_MCAST_TB2_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB2_47_32 (((REG32(ADR_MRX_MCAST_TB2_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK2_31_0 (((REG32(ADR_MRX_MCAST_MK2_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK2_47_32 (((REG32(ADR_MRX_MCAST_MK2_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_2 (((REG32(ADR_MRX_MCAST_CTRL2)) & 0x00000003 ) >> 0)
+#define GET_MRX_MCAST_TB3_31_0 (((REG32(ADR_MRX_MCAST_TB3_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_TB3_47_32 (((REG32(ADR_MRX_MCAST_TB3_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_MASK3_31_0 (((REG32(ADR_MRX_MCAST_MK3_0)) & 0xffffffff ) >> 0)
+#define GET_MRX_MCAST_MASK3_47_32 (((REG32(ADR_MRX_MCAST_MK3_1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MCAST_CTRL_3 (((REG32(ADR_MRX_MCAST_CTRL3)) & 0x00000003 ) >> 0)
+#define GET_MRX_PHY_INFO (((REG32(ADR_MRX_PHY_INFO)) & 0xffffffff ) >> 0)
+#define GET_DBG_BA_TYPE (((REG32(ADR_MRX_BA_DBG)) & 0x0000003f ) >> 0)
+#define GET_DBG_BA_SEQ (((REG32(ADR_MRX_BA_DBG)) & 0x000fff00 ) >> 8)
+#define GET_MRX_FLT_TB0 (((REG32(ADR_MRX_FLT_TB0)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB1 (((REG32(ADR_MRX_FLT_TB1)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB2 (((REG32(ADR_MRX_FLT_TB2)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB3 (((REG32(ADR_MRX_FLT_TB3)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB4 (((REG32(ADR_MRX_FLT_TB4)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB5 (((REG32(ADR_MRX_FLT_TB5)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB6 (((REG32(ADR_MRX_FLT_TB6)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB7 (((REG32(ADR_MRX_FLT_TB7)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB8 (((REG32(ADR_MRX_FLT_TB8)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB9 (((REG32(ADR_MRX_FLT_TB9)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB10 (((REG32(ADR_MRX_FLT_TB10)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB11 (((REG32(ADR_MRX_FLT_TB11)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB12 (((REG32(ADR_MRX_FLT_TB12)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB13 (((REG32(ADR_MRX_FLT_TB13)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB14 (((REG32(ADR_MRX_FLT_TB14)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_TB15 (((REG32(ADR_MRX_FLT_TB15)) & 0x00007fff ) >> 0)
+#define GET_MRX_FLT_EN0 (((REG32(ADR_MRX_FLT_EN0)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN1 (((REG32(ADR_MRX_FLT_EN1)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN2 (((REG32(ADR_MRX_FLT_EN2)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN3 (((REG32(ADR_MRX_FLT_EN3)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN4 (((REG32(ADR_MRX_FLT_EN4)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN5 (((REG32(ADR_MRX_FLT_EN5)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN6 (((REG32(ADR_MRX_FLT_EN6)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN7 (((REG32(ADR_MRX_FLT_EN7)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FLT_EN8 (((REG32(ADR_MRX_FLT_EN8)) & 0x0000ffff ) >> 0)
+#define GET_MRX_LEN_FLT (((REG32(ADR_MRX_LEN_FLT)) & 0x0000ffff ) >> 0)
+#define GET_RX_FLOW_DATA (((REG32(ADR_RX_FLOW_DATA)) & 0xffffffff ) >> 0)
+#define GET_RX_FLOW_MNG (((REG32(ADR_RX_FLOW_MNG)) & 0x0000ffff ) >> 0)
+#define GET_RX_FLOW_CTRL (((REG32(ADR_RX_FLOW_CTRL)) & 0x0000ffff ) >> 0)
+#define GET_MRX_STP_EN (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x00000001 ) >> 0)
+#define GET_MRX_STP_OFST (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x0000ff00 ) >> 8)
+#define GET_DBG_FF_FULL (((REG32(ADR_DBG_FF_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_FF_FULL_CLR (((REG32(ADR_DBG_FF_FULL)) & 0x80000000 ) >> 31)
+#define GET_DBG_WFF_FULL (((REG32(ADR_DBG_WFF_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_WFF_FULL_CLR (((REG32(ADR_DBG_WFF_FULL)) & 0x80000000 ) >> 31)
+#define GET_DBG_MB_FULL (((REG32(ADR_DBG_MB_FULL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_MB_FULL_CLR (((REG32(ADR_DBG_MB_FULL)) & 0x80000000 ) >> 31)
+#define GET_BA_CTRL (((REG32(ADR_BA_CTRL)) & 0x00000003 ) >> 0)
+#define GET_BA_DBG_EN (((REG32(ADR_BA_CTRL)) & 0x00000004 ) >> 2)
+#define GET_BA_AGRE_EN (((REG32(ADR_BA_CTRL)) & 0x00000008 ) >> 3)
+#define GET_BA_TA_31_0 (((REG32(ADR_BA_TA_0)) & 0xffffffff ) >> 0)
+#define GET_BA_TA_47_32 (((REG32(ADR_BA_TA_1)) & 0x0000ffff ) >> 0)
+#define GET_BA_TID (((REG32(ADR_BA_TID)) & 0x0000000f ) >> 0)
+#define GET_BA_ST_SEQ (((REG32(ADR_BA_ST_SEQ)) & 0x00000fff ) >> 0)
+#define GET_BA_SB0 (((REG32(ADR_BA_SB0)) & 0xffffffff ) >> 0)
+#define GET_BA_SB1 (((REG32(ADR_BA_SB1)) & 0xffffffff ) >> 0)
+#define GET_MRX_WD (((REG32(ADR_MRX_WATCH_DOG)) & 0x0001ffff ) >> 0)
+#define GET_ACK_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000001 ) >> 0)
+#define GET_BA_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000002 ) >> 1)
+#define GET_ACK_GEN_DUR (((REG32(ADR_ACK_GEN_PARA)) & 0x0000ffff ) >> 0)
+#define GET_ACK_GEN_INFO (((REG32(ADR_ACK_GEN_PARA)) & 0x003f0000 ) >> 16)
+#define GET_ACK_GEN_RA_31_0 (((REG32(ADR_ACK_GEN_RA_0)) & 0xffffffff ) >> 0)
+#define GET_ACK_GEN_RA_47_32 (((REG32(ADR_ACK_GEN_RA_1)) & 0x0000ffff ) >> 0)
+#define GET_MIB_LEN_FAIL (((REG32(ADR_MIB_LEN_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_TRAP_HW_ID (((REG32(ADR_TRAP_HW_ID)) & 0x0000000f ) >> 0)
+#define GET_ID_IN_USE (((REG32(ADR_ID_IN_USE)) & 0x000000ff ) >> 0)
+#define GET_MRX_ERR (((REG32(ADR_MRX_ERR)) & 0xffffffff ) >> 0)
+#define GET_W0_T0_SEQ (((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T1_SEQ (((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T2_SEQ (((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T3_SEQ (((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T4_SEQ (((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T5_SEQ (((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T6_SEQ (((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W0_T7_SEQ (((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T0_SEQ (((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T1_SEQ (((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T2_SEQ (((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T3_SEQ (((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T4_SEQ (((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T5_SEQ (((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T6_SEQ (((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_W1_T7_SEQ (((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0x0000ffff ) >> 0)
+#define GET_ADDR1A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000003 ) >> 0)
+#define GET_ADDR2A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x0000000c ) >> 2)
+#define GET_ADDR3A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000030 ) >> 4)
+#define GET_ADDR1B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x000000c0 ) >> 6)
+#define GET_ADDR2B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000300 ) >> 8)
+#define GET_ADDR3B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000c00 ) >> 10)
+#define GET_ADDR3C_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00003000 ) >> 12)
+#define GET_FRM_CTRL (((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0x0000003f ) >> 0)
+#define GET_CSR_PHY_INFO (((REG32(ADR_PHY_INFO)) & 0x00007fff ) >> 0)
+#define GET_AMPDU_SIG (((REG32(ADR_AMPDU_SIG)) & 0x000000ff ) >> 0)
+#define GET_MIB_AMPDU (((REG32(ADR_MIB_AMPDU)) & 0xffffffff ) >> 0)
+#define GET_LEN_FLT (((REG32(ADR_LEN_FLT)) & 0x0000ffff ) >> 0)
+#define GET_MIB_DELIMITER (((REG32(ADR_MIB_DELIMITER)) & 0x0000ffff ) >> 0)
+#define GET_MTX_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00010000 ) >> 16)
+#define GET_MTX_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00020000 ) >> 17)
+#define GET_MTX_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00040000 ) >> 18)
+#define GET_MTX_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00080000 ) >> 19)
+#define GET_MTX_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00100000 ) >> 20)
+#define GET_MTX_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00200000 ) >> 21)
+#define GET_MTX_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00400000 ) >> 22)
+#define GET_MTX_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00800000 ) >> 23)
+#define GET_MTX_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x01000000 ) >> 24)
+#define GET_MTX_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x02000000 ) >> 25)
+#define GET_MTX_EN_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00010000 ) >> 16)
+#define GET_MTX_EN_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00020000 ) >> 17)
+#define GET_MTX_EN_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00040000 ) >> 18)
+#define GET_MTX_EN_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00080000 ) >> 19)
+#define GET_MTX_EN_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00100000 ) >> 20)
+#define GET_MTX_EN_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00200000 ) >> 21)
+#define GET_MTX_EN_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00400000 ) >> 22)
+#define GET_MTX_EN_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00800000 ) >> 23)
+#define GET_MTX_EN_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x01000000 ) >> 24)
+#define GET_MTX_EN_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x02000000 ) >> 25)
+#define GET_MTX_MTX2PHY_SLOW (((REG32(ADR_MTX_MISC_EN)) & 0x00000001 ) >> 0)
+#define GET_MTX_M2M_SLOW_PRD (((REG32(ADR_MTX_MISC_EN)) & 0x0000000e ) >> 1)
+#define GET_MTX_AMPDU_CRC_AUTO (((REG32(ADR_MTX_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_MTX_FAST_RSP_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000040 ) >> 6)
+#define GET_MTX_RAW_DATA_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000080 ) >> 7)
+#define GET_MTX_ACK_DUR0 (((REG32(ADR_MTX_MISC_EN)) & 0x00000100 ) >> 8)
+#define GET_MTX_TSF_AUTO_BCN (((REG32(ADR_MTX_MISC_EN)) & 0x00000400 ) >> 10)
+#define GET_MTX_TSF_AUTO_MISC (((REG32(ADR_MTX_MISC_EN)) & 0x00000800 ) >> 11)
+#define GET_MTX_FORCE_CS_IDLE (((REG32(ADR_MTX_MISC_EN)) & 0x00001000 ) >> 12)
+#define GET_MTX_FORCE_BKF_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00002000 ) >> 13)
+#define GET_MTX_FORCE_DMA_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00004000 ) >> 14)
+#define GET_MTX_FORCE_RXEN0 (((REG32(ADR_MTX_MISC_EN)) & 0x00008000 ) >> 15)
+#define GET_MTX_HALT_Q_MB (((REG32(ADR_MTX_MISC_EN)) & 0x003f0000 ) >> 16)
+#define GET_MTX_CTS_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00400000 ) >> 22)
+#define GET_MTX_AMPDU_SET_DIF (((REG32(ADR_MTX_MISC_EN)) & 0x00800000 ) >> 23)
+#define GET_MTX_EDCCA_TOUT (((REG32(ADR_MTX_EDCCA_TOUT)) & 0x000003ff ) >> 0)
+#define GET_MTX_INT_BCN (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000002 ) >> 1)
+#define GET_MTX_INT_DTIM (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000008 ) >> 3)
+#define GET_MTX_EN_INT_BCN (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000002 ) >> 1)
+#define GET_MTX_EN_INT_DTIM (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000008 ) >> 3)
+#define GET_MTX_BCN_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000001 ) >> 0)
+#define GET_MTX_TIME_STAMP_AUTO_FILL (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000002 ) >> 1)
+#define GET_MTX_TSF_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000020 ) >> 5)
+#define GET_MTX_HALT_MNG_UNTIL_DTIM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000040 ) >> 6)
+#define GET_MTX_INT_DTIM_NUM (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_AUTO_FLUSH_Q4 (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00010000 ) >> 16)
+#define GET_MTX_BCN_PKTID_CH_LOCK (((REG32(ADR_MTX_BCN_MISC)) & 0x00000001 ) >> 0)
+#define GET_MTX_BCN_CFG_VLD (((REG32(ADR_MTX_BCN_MISC)) & 0x00000006 ) >> 1)
+#define GET_MTX_AUTO_BCN_ONGOING (((REG32(ADR_MTX_BCN_MISC)) & 0x00000008 ) >> 3)
+#define GET_MTX_BCN_TIMER (((REG32(ADR_MTX_BCN_MISC)) & 0xffff0000 ) >> 16)
+#define GET_MTX_BCN_PERIOD (((REG32(ADR_MTX_BCN_PRD)) & 0x0000ffff ) >> 0)
+#define GET_MTX_DTIM_NUM (((REG32(ADR_MTX_BCN_PRD)) & 0xff000000 ) >> 24)
+#define GET_MTX_BCN_TSF_L (((REG32(ADR_MTX_BCN_TSF_L)) & 0xffffffff ) >> 0)
+#define GET_MTX_BCN_TSF_U (((REG32(ADR_MTX_BCN_TSF_U)) & 0xffffffff ) >> 0)
+#define GET_MTX_BCN_PKT_ID0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x0000007f ) >> 0)
+#define GET_MTX_DTIM_OFST0 (((REG32(ADR_MTX_BCN_CFG0)) & 0x03ff0000 ) >> 16)
+#define GET_MTX_BCN_PKT_ID1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x0000007f ) >> 0)
+#define GET_MTX_DTIM_OFST1 (((REG32(ADR_MTX_BCN_CFG1)) & 0x03ff0000 ) >> 16)
+#define GET_MTX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000001 ) >> 0)
+#define GET_MRX_CCA (((REG32(ADR_MTX_STATUS)) & 0x00000002 ) >> 1)
+#define GET_MTX_DMA_FSM (((REG32(ADR_MTX_STATUS)) & 0x0000001c ) >> 2)
+#define GET_CH_ST_FSM (((REG32(ADR_MTX_STATUS)) & 0x000000e0 ) >> 5)
+#define GET_MTX_GNT_LOCK (((REG32(ADR_MTX_STATUS)) & 0x00000100 ) >> 8)
+#define GET_MTX_DMA_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000200 ) >> 9)
+#define GET_MTX_Q_REQ (((REG32(ADR_MTX_STATUS)) & 0x00000400 ) >> 10)
+#define GET_MTX_TX_EN (((REG32(ADR_MTX_STATUS)) & 0x00000800 ) >> 11)
+#define GET_MRX_RX_EN (((REG32(ADR_MTX_STATUS)) & 0x00001000 ) >> 12)
+#define GET_DBG_PRTC_PRD (((REG32(ADR_MTX_STATUS)) & 0x00002000 ) >> 13)
+#define GET_DBG_DMA_RDY (((REG32(ADR_MTX_STATUS)) & 0x00004000 ) >> 14)
+#define GET_DBG_WAIT_RSP (((REG32(ADR_MTX_STATUS)) & 0x00008000 ) >> 15)
+#define GET_DBG_CFRM_BUSY (((REG32(ADR_MTX_STATUS)) & 0x00010000 ) >> 16)
+#define GET_DBG_RST (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000001 ) >> 0)
+#define GET_DBG_MODE (((REG32(ADR_MTX_DBG_CTRL)) & 0x00000002 ) >> 1)
+#define GET_MB_REQ_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff ) >> 0)
+#define GET_RX_EN_DUR (((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000 ) >> 16)
+#define GET_RX_CS_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff ) >> 0)
+#define GET_TX_CCA_DUR (((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000 ) >> 16)
+#define GET_Q_REQ_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff ) >> 0)
+#define GET_CH_STA0_DUR (((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000 ) >> 16)
+#define GET_MTX_DUR_RSP_TOUT_B (((REG32(ADR_MTX_DUR_TOUT)) & 0x000000ff ) >> 0)
+#define GET_MTX_DUR_RSP_TOUT_G (((REG32(ADR_MTX_DUR_TOUT)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DUR_RSP_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x000000ff ) >> 0)
+#define GET_MTX_DUR_BURST_SIFS (((REG32(ADR_MTX_DUR_IFS)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DUR_SLOT (((REG32(ADR_MTX_DUR_IFS)) & 0x003f0000 ) >> 16)
+#define GET_MTX_DUR_RSP_EIFS (((REG32(ADR_MTX_DUR_IFS)) & 0xffc00000 ) >> 22)
+#define GET_MTX_DUR_RSP_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x000000ff ) >> 0)
+#define GET_MTX_DUR_BURST_SIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x0000ff00 ) >> 8)
+#define GET_MTX_DUR_SLOT_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003f0000 ) >> 16)
+#define GET_MTX_DUR_RSP_EIFS_G (((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc00000 ) >> 22)
+#define GET_CH_STA1_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff ) >> 0)
+#define GET_CH_STA2_DUR (((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000 ) >> 16)
+#define GET_MTX_NAV (((REG32(ADR_MTX_NAV)) & 0x0000ffff ) >> 0)
+#define GET_MTX_MIB_CNT0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x3fffffff ) >> 0)
+#define GET_MTX_MIB_EN0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x40000000 ) >> 30)
+#define GET_MTX_MIB_CNT1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x3fffffff ) >> 0)
+#define GET_MTX_MIB_EN1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x40000000 ) >> 30)
+#define GET_CH_STA3_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff ) >> 0)
+#define GET_CH_STA4_DUR (((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000 ) >> 16)
+#define GET_TXQ0_MTX_Q_PRE_LD (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ0_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ0_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ0_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ0_MTX_Q_RND_MODE (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ0_MTX_Q_AIFSN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ0_MTX_Q_ECWMIN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ0_MTX_Q_ECWMAX (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ0_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ0_MTX_Q_BKF_CNT (((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ0_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ0_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ0_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ0_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ0_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_MTX_Q_PRE_LD (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ1_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ1_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ1_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ1_MTX_Q_RND_MODE (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ1_MTX_Q_AIFSN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ1_MTX_Q_ECWMIN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ1_MTX_Q_ECWMAX (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ1_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ1_MTX_Q_BKF_CNT (((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ1_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ1_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ1_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ1_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_MTX_Q_PRE_LD (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ2_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ2_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ2_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ2_MTX_Q_RND_MODE (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ2_MTX_Q_AIFSN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ2_MTX_Q_ECWMIN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ2_MTX_Q_ECWMAX (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ2_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ2_MTX_Q_BKF_CNT (((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ2_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ2_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ2_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ2_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_MTX_Q_PRE_LD (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ3_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ3_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ3_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ3_MTX_Q_RND_MODE (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ3_MTX_Q_AIFSN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ3_MTX_Q_ECWMIN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ3_MTX_Q_ECWMAX (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ3_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ3_MTX_Q_BKF_CNT (((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ3_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ3_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ3_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ3_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_MTX_Q_PRE_LD (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000002 ) >> 1)
+#define GET_TXQ4_MTX_Q_BKF_CNT_FIXED (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000004 ) >> 2)
+#define GET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000008 ) >> 3)
+#define GET_TXQ4_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4)
+#define GET_TXQ4_MTX_Q_TXOP_FRC_BUR (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000020 ) >> 5)
+#define GET_TXQ4_MTX_Q_RND_MODE (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x000000c0 ) >> 6)
+#define GET_TXQ4_MTX_Q_AIFSN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000000f ) >> 0)
+#define GET_TXQ4_MTX_Q_ECWMIN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8)
+#define GET_TXQ4_MTX_Q_ECWMAX (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12)
+#define GET_TXQ4_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16)
+#define GET_TXQ4_MTX_Q_BKF_CNT (((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_MTX_Q_SRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x000000ff ) >> 0)
+#define GET_TXQ4_MTX_Q_LRC_LIMIT (((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0x0000ff00 ) >> 8)
+#define GET_TXQ4_MTX_Q_ID_MAP_L (((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0xffffffff ) >> 0)
+#define GET_TXQ4_MTX_Q_TXOP_CH_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0x0000ffff ) >> 0)
+#define GET_TXQ4_MTX_Q_TXOP_OV_THD (((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0x0000ffff ) >> 0)
+#define GET_VALID0 (((REG32(ADR_WSID0)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN0 (((REG32(ADR_WSID0)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE0 (((REG32(ADR_WSID0)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE0 (((REG32(ADR_WSID0)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC0_31_0 (((REG32(ADR_PEER_MAC0_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC0_47_32 (((REG32(ADR_PEER_MAC0_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_0_0 (((REG32(ADR_TX_ACK_POLICY_0_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_0 (((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_1 (((REG32(ADR_TX_ACK_POLICY_0_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_1 (((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_2 (((REG32(ADR_TX_ACK_POLICY_0_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_2 (((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_3 (((REG32(ADR_TX_ACK_POLICY_0_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_3 (((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_4 (((REG32(ADR_TX_ACK_POLICY_0_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_4 (((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_5 (((REG32(ADR_TX_ACK_POLICY_0_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_5 (((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_6 (((REG32(ADR_TX_ACK_POLICY_0_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_6 (((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_0_7 (((REG32(ADR_TX_ACK_POLICY_0_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_0_7 (((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0x00000fff ) >> 0)
+#define GET_VALID1 (((REG32(ADR_WSID1)) & 0x00000001 ) >> 0)
+#define GET_PEER_QOS_EN1 (((REG32(ADR_WSID1)) & 0x00000002 ) >> 1)
+#define GET_PEER_OP_MODE1 (((REG32(ADR_WSID1)) & 0x0000000c ) >> 2)
+#define GET_PEER_HT_MODE1 (((REG32(ADR_WSID1)) & 0x00000030 ) >> 4)
+#define GET_PEER_MAC1_31_0 (((REG32(ADR_PEER_MAC1_0)) & 0xffffffff ) >> 0)
+#define GET_PEER_MAC1_47_32 (((REG32(ADR_PEER_MAC1_1)) & 0x0000ffff ) >> 0)
+#define GET_TX_ACK_POLICY_1_0 (((REG32(ADR_TX_ACK_POLICY_1_0)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_0 (((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_1 (((REG32(ADR_TX_ACK_POLICY_1_1)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_1 (((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_2 (((REG32(ADR_TX_ACK_POLICY_1_2)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_2 (((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_3 (((REG32(ADR_TX_ACK_POLICY_1_3)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_3 (((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_4 (((REG32(ADR_TX_ACK_POLICY_1_4)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_4 (((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_5 (((REG32(ADR_TX_ACK_POLICY_1_5)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_5 (((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_6 (((REG32(ADR_TX_ACK_POLICY_1_6)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_6 (((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0x00000fff ) >> 0)
+#define GET_TX_ACK_POLICY_1_7 (((REG32(ADR_TX_ACK_POLICY_1_7)) & 0x00000003 ) >> 0)
+#define GET_TX_SEQ_CTRL_1_7 (((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0x00000fff ) >> 0)
+#define GET_INFO0 (((REG32(ADR_INFO0)) & 0xffffffff ) >> 0)
+#define GET_INFO1 (((REG32(ADR_INFO1)) & 0xffffffff ) >> 0)
+#define GET_INFO2 (((REG32(ADR_INFO2)) & 0xffffffff ) >> 0)
+#define GET_INFO3 (((REG32(ADR_INFO3)) & 0xffffffff ) >> 0)
+#define GET_INFO4 (((REG32(ADR_INFO4)) & 0xffffffff ) >> 0)
+#define GET_INFO5 (((REG32(ADR_INFO5)) & 0xffffffff ) >> 0)
+#define GET_INFO6 (((REG32(ADR_INFO6)) & 0xffffffff ) >> 0)
+#define GET_INFO7 (((REG32(ADR_INFO7)) & 0xffffffff ) >> 0)
+#define GET_INFO8 (((REG32(ADR_INFO8)) & 0xffffffff ) >> 0)
+#define GET_INFO9 (((REG32(ADR_INFO9)) & 0xffffffff ) >> 0)
+#define GET_INFO10 (((REG32(ADR_INFO10)) & 0xffffffff ) >> 0)
+#define GET_INFO11 (((REG32(ADR_INFO11)) & 0xffffffff ) >> 0)
+#define GET_INFO12 (((REG32(ADR_INFO12)) & 0xffffffff ) >> 0)
+#define GET_INFO13 (((REG32(ADR_INFO13)) & 0xffffffff ) >> 0)
+#define GET_INFO14 (((REG32(ADR_INFO14)) & 0xffffffff ) >> 0)
+#define GET_INFO15 (((REG32(ADR_INFO15)) & 0xffffffff ) >> 0)
+#define GET_INFO16 (((REG32(ADR_INFO16)) & 0xffffffff ) >> 0)
+#define GET_INFO17 (((REG32(ADR_INFO17)) & 0xffffffff ) >> 0)
+#define GET_INFO18 (((REG32(ADR_INFO18)) & 0xffffffff ) >> 0)
+#define GET_INFO19 (((REG32(ADR_INFO19)) & 0xffffffff ) >> 0)
+#define GET_INFO20 (((REG32(ADR_INFO20)) & 0xffffffff ) >> 0)
+#define GET_INFO21 (((REG32(ADR_INFO21)) & 0xffffffff ) >> 0)
+#define GET_INFO22 (((REG32(ADR_INFO22)) & 0xffffffff ) >> 0)
+#define GET_INFO23 (((REG32(ADR_INFO23)) & 0xffffffff ) >> 0)
+#define GET_INFO24 (((REG32(ADR_INFO24)) & 0xffffffff ) >> 0)
+#define GET_INFO25 (((REG32(ADR_INFO25)) & 0xffffffff ) >> 0)
+#define GET_INFO26 (((REG32(ADR_INFO26)) & 0xffffffff ) >> 0)
+#define GET_INFO27 (((REG32(ADR_INFO27)) & 0xffffffff ) >> 0)
+#define GET_INFO28 (((REG32(ADR_INFO28)) & 0xffffffff ) >> 0)
+#define GET_INFO29 (((REG32(ADR_INFO29)) & 0xffffffff ) >> 0)
+#define GET_INFO30 (((REG32(ADR_INFO30)) & 0xffffffff ) >> 0)
+#define GET_INFO31 (((REG32(ADR_INFO31)) & 0xffffffff ) >> 0)
+#define GET_INFO32 (((REG32(ADR_INFO32)) & 0xffffffff ) >> 0)
+#define GET_INFO33 (((REG32(ADR_INFO33)) & 0xffffffff ) >> 0)
+#define GET_INFO34 (((REG32(ADR_INFO34)) & 0xffffffff ) >> 0)
+#define GET_INFO35 (((REG32(ADR_INFO35)) & 0xffffffff ) >> 0)
+#define GET_INFO36 (((REG32(ADR_INFO36)) & 0xffffffff ) >> 0)
+#define GET_INFO37 (((REG32(ADR_INFO37)) & 0xffffffff ) >> 0)
+#define GET_INFO38 (((REG32(ADR_INFO38)) & 0xffffffff ) >> 0)
+#define GET_INFO_MASK (((REG32(ADR_INFO_MASK)) & 0xffffffff ) >> 0)
+#define GET_INFO_DEF_RATE (((REG32(ADR_INFO_RATE_OFFSET)) & 0x0000003f ) >> 0)
+#define GET_INFO_MRX_OFFSET (((REG32(ADR_INFO_RATE_OFFSET)) & 0x000f0000 ) >> 16)
+#define GET_BCAST_RATEUNKNOW (((REG32(ADR_INFO_RATE_OFFSET)) & 0x3f000000 ) >> 24)
+#define GET_INFO_IDX_TBL_ADDR (((REG32(ADR_INFO_IDX_ADDR)) & 0xffffffff ) >> 0)
+#define GET_INFO_LEN_TBL_ADDR (((REG32(ADR_INFO_LEN_ADDR)) & 0xffffffff ) >> 0)
+#define GET_IC_TAG_31_0 (((REG32(ADR_IC_TIME_TAG_0)) & 0xffffffff ) >> 0)
+#define GET_IC_TAG_63_32 (((REG32(ADR_IC_TIME_TAG_1)) & 0xffffffff ) >> 0)
+#define GET_CH1_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000003 ) >> 0)
+#define GET_CH2_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000300 ) >> 8)
+#define GET_CH3_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00030000 ) >> 16)
+#define GET_RG_MAC_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000001 ) >> 0)
+#define GET_RG_MAC_M2M (((REG32(ADR_MAC_MODE)) & 0x00000002 ) >> 1)
+#define GET_RG_PHY_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000004 ) >> 2)
+#define GET_RG_LPBK_RX_EN (((REG32(ADR_MAC_MODE)) & 0x00000008 ) >> 3)
+#define GET_EXT_MAC_MODE (((REG32(ADR_MAC_MODE)) & 0x00000010 ) >> 4)
+#define GET_EXT_PHY_MODE (((REG32(ADR_MAC_MODE)) & 0x00000020 ) >> 5)
+#define GET_ASIC_TAG (((REG32(ADR_MAC_MODE)) & 0xff000000 ) >> 24)
+#define GET_HCI_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_CHST_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_BCN_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MRX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_AMPDU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_MMU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
+#define GET_ID_MNG_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
+#define GET_MBOX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00001000 ) >> 12)
+#define GET_SCRT_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
+#define GET_MIC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_CO_PROC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_CHST_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_BCN_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MRX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_AMPDU_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_ID_MNG_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_MBOX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
+#define GET_SCRT_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00010000 ) >> 16)
+#define GET_MIC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00020000 ) >> 17)
+#define GET_CO_PROC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE0_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000010 ) >> 4)
+#define GET_MTX_QUE1_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000020 ) >> 5)
+#define GET_MTX_QUE2_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000040 ) >> 6)
+#define GET_MTX_QUE3_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000080 ) >> 7)
+#define GET_MTX_QUE4_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000100 ) >> 8)
+#define GET_MTX_QUE5_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000200 ) >> 9)
+#define GET_MRX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000400 ) >> 10)
+#define GET_AMPDU_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000800 ) >> 11)
+#define GET_SCRT_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00002000 ) >> 13)
+#define GET_ID_MNG_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00004000 ) >> 14)
+#define GET_MBOX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00008000 ) >> 15)
+#define GET_HCI_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_MRX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_AMPDU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_MMU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000080 ) >> 7)
+#define GET_ID_MNG_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000200 ) >> 9)
+#define GET_MBOX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_SCRT_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_MIC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_MIB_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_HCI_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000001 ) >> 0)
+#define GET_CO_PROC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MTX_MISC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000008 ) >> 3)
+#define GET_MTX_QUE_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000010 ) >> 4)
+#define GET_MRX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000020 ) >> 5)
+#define GET_AMPDU_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000040 ) >> 6)
+#define GET_ID_MNG_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00001000 ) >> 12)
+#define GET_MBOX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_SCRT_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_MIC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_CO_PROC_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000002 ) >> 1)
+#define GET_MRX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10)
+#define GET_AMPDU_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000800 ) >> 11)
+#define GET_SCRT_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00002000 ) >> 13)
+#define GET_ID_MNG_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00004000 ) >> 14)
+#define GET_MBOX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00008000 ) >> 15)
+#define GET_OP_MODE (((REG32(ADR_GLBLE_SET)) & 0x00000003 ) >> 0)
+#define GET_HT_MODE (((REG32(ADR_GLBLE_SET)) & 0x0000000c ) >> 2)
+#define GET_QOS_EN (((REG32(ADR_GLBLE_SET)) & 0x00000010 ) >> 4)
+#define GET_PB_OFFSET (((REG32(ADR_GLBLE_SET)) & 0x0000ff00 ) >> 8)
+#define GET_SNIFFER_MODE (((REG32(ADR_GLBLE_SET)) & 0x00010000 ) >> 16)
+#define GET_DUP_FLT (((REG32(ADR_GLBLE_SET)) & 0x00020000 ) >> 17)
+#define GET_TX_PKT_RSVD (((REG32(ADR_GLBLE_SET)) & 0x001c0000 ) >> 18)
+#define GET_AMPDU_SNIFFER (((REG32(ADR_GLBLE_SET)) & 0x00200000 ) >> 21)
+#define GET_REASON_TRAP0 (((REG32(ADR_REASON_TRAP0)) & 0xffffffff ) >> 0)
+#define GET_REASON_TRAP1 (((REG32(ADR_REASON_TRAP1)) & 0xffffffff ) >> 0)
+#define GET_BSSID_31_0 (((REG32(ADR_BSSID_0)) & 0xffffffff ) >> 0)
+#define GET_BSSID_47_32 (((REG32(ADR_BSSID_1)) & 0x0000ffff ) >> 0)
+#define GET_SCRT_STATE (((REG32(ADR_SCRT_STATE)) & 0x0000000f ) >> 0)
+#define GET_STA_MAC_31_0 (((REG32(ADR_STA_MAC_0)) & 0xffffffff ) >> 0)
+#define GET_STA_MAC_47_32 (((REG32(ADR_STA_MAC_1)) & 0x0000ffff ) >> 0)
+#define GET_PAIR_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000007 ) >> 0)
+#define GET_GRP_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000038 ) >> 3)
+#define GET_SCRT_PKT_ID (((REG32(ADR_SCRT_SET)) & 0x00001fc0 ) >> 6)
+#define GET_SCRT_RPLY_IGNORE (((REG32(ADR_SCRT_SET)) & 0x00010000 ) >> 16)
+#define GET_COEXIST_EN (((REG32(ADR_BTCX0)) & 0x00000001 ) >> 0)
+#define GET_WIRE_MODE (((REG32(ADR_BTCX0)) & 0x0000000e ) >> 1)
+#define GET_WL_RX_PRI (((REG32(ADR_BTCX0)) & 0x00000010 ) >> 4)
+#define GET_WL_TX_PRI (((REG32(ADR_BTCX0)) & 0x00000020 ) >> 5)
+#define GET_GURAN_USE_EN (((REG32(ADR_BTCX0)) & 0x00000100 ) >> 8)
+#define GET_GURAN_USE_CTRL (((REG32(ADR_BTCX0)) & 0x00000200 ) >> 9)
+#define GET_BEACON_TIMEOUT_EN (((REG32(ADR_BTCX0)) & 0x00000400 ) >> 10)
+#define GET_WLAN_ACT_POL (((REG32(ADR_BTCX0)) & 0x00000800 ) >> 11)
+#define GET_DUAL_ANT_EN (((REG32(ADR_BTCX0)) & 0x00001000 ) >> 12)
+#define GET_TRSW_PHY_POL (((REG32(ADR_BTCX0)) & 0x00010000 ) >> 16)
+#define GET_WIFI_TX_SW_POL (((REG32(ADR_BTCX0)) & 0x00020000 ) >> 17)
+#define GET_WIFI_RX_SW_POL (((REG32(ADR_BTCX0)) & 0x00040000 ) >> 18)
+#define GET_BT_SW_POL (((REG32(ADR_BTCX0)) & 0x00080000 ) >> 19)
+#define GET_BT_PRI_SMP_TIME (((REG32(ADR_BTCX1)) & 0x000000ff ) >> 0)
+#define GET_BT_STA_SMP_TIME (((REG32(ADR_BTCX1)) & 0x0000ff00 ) >> 8)
+#define GET_BEACON_TIMEOUT (((REG32(ADR_BTCX1)) & 0x00ff0000 ) >> 16)
+#define GET_WLAN_REMAIN_TIME (((REG32(ADR_BTCX1)) & 0xff000000 ) >> 24)
+#define GET_SW_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000001 ) >> 0)
+#define GET_SW_WL_TX (((REG32(ADR_SWITCH_CTL)) & 0x00000002 ) >> 1)
+#define GET_SW_WL_RX (((REG32(ADR_SWITCH_CTL)) & 0x00000004 ) >> 2)
+#define GET_SW_BT_TRX (((REG32(ADR_SWITCH_CTL)) & 0x00000008 ) >> 3)
+#define GET_BT_TXBAR_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000010 ) >> 4)
+#define GET_BT_TXBAR_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000020 ) >> 5)
+#define GET_BT_BUSY_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000100 ) >> 8)
+#define GET_BT_BUSY_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000200 ) >> 9)
+#define GET_G0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000004 ) >> 2)
+#define GET_G0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000008 ) >> 3)
+#define GET_G1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000010 ) >> 4)
+#define GET_G1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000020 ) >> 5)
+#define GET_Q0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000040 ) >> 6)
+#define GET_Q0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000080 ) >> 7)
+#define GET_Q1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000100 ) >> 8)
+#define GET_Q1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000200 ) >> 9)
+#define GET_Q2_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000400 ) >> 10)
+#define GET_Q2_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000800 ) >> 11)
+#define GET_Q3_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00001000 ) >> 12)
+#define GET_Q3_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00002000 ) >> 13)
+#define GET_SCRT_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00004000 ) >> 14)
+#define GET_SCRT_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00008000 ) >> 15)
+#define GET_MISC_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00010000 ) >> 16)
+#define GET_MISC_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00020000 ) >> 17)
+#define GET_MTX_WSID0_SUCC (((REG32(ADR_MTX_WSID0_SUCC)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_FRM (((REG32(ADR_MTX_WSID0_FRM)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_RETRY (((REG32(ADR_MTX_WSID0_RETRY)) & 0x0000ffff ) >> 0)
+#define GET_MTX_WSID0_TOTAL (((REG32(ADR_MTX_WSID0_TOTAL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_GRP (((REG32(ADR_MTX_GROUP)) & 0x000fffff ) >> 0)
+#define GET_MTX_FAIL (((REG32(ADR_MTX_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RETRY (((REG32(ADR_MTX_RETRY)) & 0x000fffff ) >> 0)
+#define GET_MTX_MULTI_RETRY (((REG32(ADR_MTX_MULTI_RETRY)) & 0x000fffff ) >> 0)
+#define GET_MTX_RTS_SUCC (((REG32(ADR_MTX_RTS_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_MTX_RTS_FAIL (((REG32(ADR_MTX_RTS_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_ACK_FAIL (((REG32(ADR_MTX_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MTX_FRM (((REG32(ADR_MTX_FRM)) & 0x000fffff ) >> 0)
+#define GET_MTX_ACK_TX (((REG32(ADR_MTX_ACK_TX)) & 0x0000ffff ) >> 0)
+#define GET_MTX_CTS_TX (((REG32(ADR_MTX_CTS_TX)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DUP (((REG32(ADR_MRX_DUP_FRM)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FRG (((REG32(ADR_MRX_FRG_FRM)) & 0x000fffff ) >> 0)
+#define GET_MRX_GRP (((REG32(ADR_MRX_GROUP_FRM)) & 0x000fffff ) >> 0)
+#define GET_MRX_FCS_ERR (((REG32(ADR_MRX_FCS_ERR)) & 0x0000ffff ) >> 0)
+#define GET_MRX_FCS_SUC (((REG32(ADR_MRX_FCS_SUCC)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MISS (((REG32(ADR_MRX_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_ALC_FAIL (((REG32(ADR_MRX_ALC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DAT_NTF (((REG32(ADR_MRX_DAT_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_RTS_NTF (((REG32(ADR_MRX_RTS_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_CTS_NTF (((REG32(ADR_MRX_CTS_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_ACK_NTF (((REG32(ADR_MRX_ACK_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_BA_NTF (((REG32(ADR_MRX_BA_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DATA_NTF (((REG32(ADR_MRX_DATA_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MNG_NTF (((REG32(ADR_MRX_MNG_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_DAT_CRC_NTF (((REG32(ADR_MRX_DAT_CRC_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_BAR_NTF (((REG32(ADR_MRX_BAR_NTF)) & 0x0000ffff ) >> 0)
+#define GET_MRX_MB_MISS (((REG32(ADR_MRX_MB_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_NIDLE_MISS (((REG32(ADR_MRX_NIDLE_MISS)) & 0x0000ffff ) >> 0)
+#define GET_MRX_CSR_NTF (((REG32(ADR_MRX_CSR_NTF)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_SUCC (((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_FAIL (((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_ACK_SUCC (((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q0_ACK_FAIL (((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_SUCC (((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_FAIL (((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_ACK_SUCC (((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q1_ACK_FAIL (((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_SUCC (((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_FAIL (((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_ACK_SUCC (((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q2_ACK_FAIL (((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_SUCC (((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_FAIL (((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_ACK_SUCC (((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_Q3_ACK_FAIL (((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_SCRT_TKIP_CERR (((REG32(ADR_MIB_SCRT_TKIP0)) & 0x000fffff ) >> 0)
+#define GET_SCRT_TKIP_MIC_ERR (((REG32(ADR_MIB_SCRT_TKIP1)) & 0x000fffff ) >> 0)
+#define GET_SCRT_TKIP_RPLY (((REG32(ADR_MIB_SCRT_TKIP2)) & 0x000fffff ) >> 0)
+#define GET_SCRT_CCMP_RPLY (((REG32(ADR_MIB_SCRT_CCMP0)) & 0x000fffff ) >> 0)
+#define GET_SCRT_CCMP_CERR (((REG32(ADR_MIB_SCRT_CCMP1)) & 0x000fffff ) >> 0)
+#define GET_DBG_LEN_CRC_FAIL (((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_LEN_ALC_FAIL (((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_DBG_AMPDU_PASS (((REG32(ADR_DBG_AMPDU_PASS)) & 0x0000ffff ) >> 0)
+#define GET_DBG_AMPDU_FAIL (((REG32(ADR_DBG_AMPDU_FAIL)) & 0x0000ffff ) >> 0)
+#define GET_RXID_ALC_CNT_FAIL (((REG32(ADR_ID_ALC_FAIL1)) & 0x0000ffff ) >> 0)
+#define GET_RXID_ALC_LEN_FAIL (((REG32(ADR_ID_ALC_FAIL2)) & 0x0000ffff ) >> 0)
+#define GET_CBR_RG_EN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_TX_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_TX_PA_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_TX_DAC_EN (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_RX_AGC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_RX_GAIN_MANUAL (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_RFG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_CBR_RG_PGAG (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_CBR_RG_MODE (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_CBR_RG_EN_TX_TRSW (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_EN_SX (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_CBR_RG_EN_RX_LNA (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_CBR_RG_EN_RX_MIXER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_CBR_RG_EN_RX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_CBR_RG_EN_RX_LOBUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_CBR_RG_EN_RX_TZ (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_EN_RX_FILTER (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_EN_RX_HPF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_EN_RX_RSSI (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_CBR_RG_EN_ADC (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_CBR_RG_EN_TX_MOD (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_EN_TX_DIV2 (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_CBR_RG_EN_TX_DIV2_BUF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_CBR_RG_EN_TX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_CBR_RG_EN_RX_LOBF (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_CBR_RG_SEL_DPLL_CLK (((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_CBR_RG_EN_TX_DPD (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_EN_TX_TSSI (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_EN_RX_IQCAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_EN_TX_DAC_CAL (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_EN_TX_SELF_MIXER (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_EN_TX_DAC_OUT (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_EN_LDO_RX_FE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_CBR_RG_EN_LDO_ABB (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_CBR_RG_EN_LDO_AFE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_EN_SX_CHPLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_EN_SX_LOBFLDO (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_EN_IREF_RX (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_DCDC_MODE (((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_CBR_RG_LDO_LEVEL_RX_FE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_CBR_RG_LDO_LEVEL_ABB (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000038 ) >> 3)
+#define GET_CBR_RG_LDO_LEVEL_AFE (((REG32(ADR_CBR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
+#define GET_CBR_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
+#define GET_CBR_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_CBR_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_CBR_RG_DP_LDO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_CBR_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
+#define GET_CBR_RG_TX_LDO_TX_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_CBR_RG_BUCK_LEVEL (((REG32(ADR_CBR_LDO_REGISTER)) & 0x38000000 ) >> 27)
+#define GET_CBR_RG_EN_RX_PADSW (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_EN_RX_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_RX_ABBCFIX (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_RX_ABBCTUNE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
+#define GET_CBR_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_RX_ABB_N_MODE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_RX_EN_LOOPA (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_RX_FILTERI1ST (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
+#define GET_CBR_RG_RX_FILTERI2ND (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_FILTERI3RD (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
+#define GET_CBR_RG_RX_FILTERI_COURSE (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
+#define GET_CBR_RG_RX_FILTERVCM (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
+#define GET_CBR_RG_RX_HPF3M (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_RX_HPF300K (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
+#define GET_CBR_RG_RX_HPFI (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
+#define GET_CBR_RG_RX_HPF_FINALCORNER (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
+#define GET_CBR_RG_RX_HPF_SETTLE1_C (((REG32(ADR_CBR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
+#define GET_CBR_RG_RX_HPF_SETTLE1_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_HPF_SETTLE2_C (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
+#define GET_CBR_RG_RX_HPF_SETTLE2_R (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_RX_HPF_VCMCON2 (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
+#define GET_CBR_RG_RX_HPF_VCMCON (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
+#define GET_CBR_RG_RX_OUTVCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
+#define GET_CBR_RG_RX_TZI (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
+#define GET_CBR_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_RX_TZ_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
+#define GET_CBR_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
+#define GET_CBR_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_RX_ADCRSSI_VCM (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
+#define GET_CBR_RG_RX_REC_LPFCORNER (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
+#define GET_CBR_RG_RSSI_CLOCK_GATING (((REG32(ADR_CBR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_TXPGA_CAPSW (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_TXPGA_MAIN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
+#define GET_CBR_RG_TXPGA_STEER (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
+#define GET_CBR_RG_TXMOD_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_TXLPF_GMCELL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_CBR_RG_PACELL_EN (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_CBR_RG_PABIAS_CTRL (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
+#define GET_CBR_RG_PABIAS_AB (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_TX_DIV_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_CBR_RG_TX_LOBUF_VSET (((REG32(ADR_CBR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_CBR_RG_RX_SQDC (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
+#define GET_CBR_RG_RX_DIV2_CORE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_RX_LOBUF (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
+#define GET_CBR_RG_TX_DPDGM_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
+#define GET_CBR_RG_TX_DPD_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
+#define GET_CBR_RG_TX_TSSI_BIAS (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
+#define GET_CBR_RG_TX_TSSI_DIV (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
+#define GET_CBR_RG_TX_TSSI_TESTMODE (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_TX_TSSI_TEST (((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
+#define GET_CBR_RG_RX_HG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_HG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_HG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_HG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_RX_MG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_MG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_MG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_MG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_RX_LG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_LG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_LG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_LG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_RX_ULG_LNA_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
+#define GET_CBR_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_RX_ULG_TZ_GC (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_RX_ULG_TZ_CAP (((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
+#define GET_CBR_RG_HPF1_FAST_SET_X (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_HPF1_FAST_SET_Y (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_HPF1_FAST_SET_Z (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_HPF_T1A (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_HPF_T1B (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000060 ) >> 5)
+#define GET_CBR_RG_HPF_T1C (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000180 ) >> 7)
+#define GET_CBR_RG_RX_LNA_TRI_SEL (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_CBR_RG_RX_LNA_SETTLE (((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0x00001800 ) >> 11)
+#define GET_CBR_RG_ADC_CLKSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_ADC_DIBIAS (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_ADC_DIVR (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_ADC_DVCMI (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_ADC_SAMSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
+#define GET_CBR_RG_ADC_STNBY (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_ADC_TESTMODE (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_ADC_TSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_CBR_RG_ADC_VRSEL (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_CBR_RG_DICMP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_CBR_RG_DIOP (((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_CBR_RG_DACI1ST (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_TX_DACLPF_ICOURSE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_CBR_RG_TX_DACLPF_IFINE (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_TX_DACLPF_VCM (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_CBR_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_TX_DAC_IBIAS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_CBR_RG_TX_DAC_OS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
+#define GET_CBR_RG_TX_DAC_RCAL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_CBR_RG_TX_DAC_TSEL (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
+#define GET_CBR_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_TXLPF_BYPASS (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_TXLPF_BOOSTI (((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_EN_SX_R3 (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_EN_SX_CH (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_EN_SX_CHP (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_EN_SX_DIVCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000008 ) >> 3)
+#define GET_CBR_RG_EN_SX_VCOBF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_EN_SX_VCO (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_EN_SX_MOD (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000040 ) >> 6)
+#define GET_CBR_RG_EN_SX_LCK (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000080 ) >> 7)
+#define GET_CBR_RG_EN_SX_DITHER (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_EN_SX_DELCAL (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_EN_SX_PC_BYPASS (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_EN_SX_VT_MON (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_EN_SX_VT_MON_DG (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00001000 ) >> 12)
+#define GET_CBR_RG_EN_SX_DIV (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00002000 ) >> 13)
+#define GET_CBR_RG_EN_SX_LPF (((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_SX_RFCTRL_F (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x00ffffff ) >> 0)
+#define GET_CBR_RG_SX_SEL_CP (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0f000000 ) >> 24)
+#define GET_CBR_RG_SX_SEL_CS (((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0000000 ) >> 28)
+#define GET_CBR_RG_SX_RFCTRL_CH (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000007ff ) >> 0)
+#define GET_CBR_RG_SX_SEL_C3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x00007800 ) >> 11)
+#define GET_CBR_RG_SX_SEL_RS (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x000f8000 ) >> 15)
+#define GET_CBR_RG_SX_SEL_R3 (((REG32(ADR_CBR_SYN_RGISTER_2)) & 0x01f00000 ) >> 20)
+#define GET_CBR_RG_SX_SEL_ICHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
+#define GET_CBR_RG_SX_SEL_PCHP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
+#define GET_CBR_RG_SX_SEL_CHP_REGOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
+#define GET_CBR_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
+#define GET_CBR_RG_SX_CHP_IOST_POL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
+#define GET_CBR_RG_SX_CHP_IOST (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
+#define GET_CBR_RG_SX_PFDSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
+#define GET_CBR_RG_SX_PFD_SET (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
+#define GET_CBR_RG_SX_PFD_SET1 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
+#define GET_CBR_RG_SX_PFD_SET2 (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
+#define GET_CBR_RG_SX_VBNCAS_SEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
+#define GET_CBR_RG_SX_PFD_RST_H (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
+#define GET_CBR_RG_SX_PFD_TRUP (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
+#define GET_CBR_RG_SX_PFD_TRDN (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
+#define GET_CBR_RG_SX_PFD_TRSEL (((REG32(ADR_CBR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
+#define GET_CBR_RG_SX_VCOBA_R (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
+#define GET_CBR_RG_SX_VCORSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
+#define GET_CBR_RG_SX_VCOCUSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
+#define GET_CBR_RG_SX_RXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
+#define GET_CBR_RG_SX_TXBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
+#define GET_CBR_RG_SX_VCOBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
+#define GET_CBR_RG_SX_DIVBFSEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
+#define GET_CBR_RG_SX_GNDR_SEL (((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
+#define GET_CBR_RG_SX_DITHER_WEIGHT (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_SX_MOD_ERRCMP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0000000c ) >> 2)
+#define GET_CBR_RG_SX_MOD_ORDER (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
+#define GET_CBR_RG_SX_SDM_D1 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000040 ) >> 6)
+#define GET_CBR_RG_SX_SDM_D2 (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000080 ) >> 7)
+#define GET_CBR_RG_SDM_PASS (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_SX_RST_H_DIV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_SX_SDM_EDGE (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_SX_XO_GM (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
+#define GET_CBR_RG_SX_REFBYTWO (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
+#define GET_CBR_RG_SX_XO_SWCAP (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0003c000 ) >> 14)
+#define GET_CBR_RG_SX_SDMLUT_INV (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00040000 ) >> 18)
+#define GET_CBR_RG_SX_LCKEN (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
+#define GET_CBR_RG_SX_PREVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
+#define GET_CBR_RG_SX_PSCONTERVDD (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
+#define GET_CBR_RG_SX_MOD_ERR_DELAY (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x30000000 ) >> 28)
+#define GET_CBR_RG_SX_MODDB (((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0x40000000 ) >> 30)
+#define GET_CBR_RG_SX_CV_CURVE_SEL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000003 ) >> 0)
+#define GET_CBR_RG_SX_SEL_DELAY (((REG32(ADR_CBR_SYN_LCK1)) & 0x0000007c ) >> 2)
+#define GET_CBR_RG_SX_REF_CYCLE (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000780 ) >> 7)
+#define GET_CBR_RG_SX_VCOBY16 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_SX_VCOBY32 (((REG32(ADR_CBR_SYN_LCK1)) & 0x00001000 ) >> 12)
+#define GET_CBR_RG_SX_PH (((REG32(ADR_CBR_SYN_LCK1)) & 0x00002000 ) >> 13)
+#define GET_CBR_RG_SX_PL (((REG32(ADR_CBR_SYN_LCK1)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_SX_VT_MON_MODE (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_SX_VT_TH_HI (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_SX_VT_TH_LO (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_SX_VT_SET (((REG32(ADR_CBR_SYN_LCK2)) & 0x00000020 ) >> 5)
+#define GET_CBR_RG_SX_VT_MON_TMR (((REG32(ADR_CBR_SYN_LCK2)) & 0x00007fc0 ) >> 6)
+#define GET_CBR_RG_IDEAL_CYCLE (((REG32(ADR_CBR_SYN_LCK2)) & 0x0fff8000 ) >> 15)
+#define GET_CBR_RG_EN_DP_VT_MON (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_DP_VT_TH_HI (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_DP_VT_TH_LO (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_DP_VT_MON_TMR (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00003fe0 ) >> 5)
+#define GET_CBR_RG_DP_CK320BY2 (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_CBR_RG_SX_DELCTRL (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x001f8000 ) >> 15)
+#define GET_CBR_RG_DP_OD_TEST (((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_CBR_RG_DP_BBPLL_BP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_DP_BBPLL_ICP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_CBR_RG_DP_BBPLL_IDUAL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_CBR_RG_DP_BBPLL_OD_TEST (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
+#define GET_CBR_RG_DP_BBPLL_PD (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_DP_BBPLL_TESTSEL (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
+#define GET_CBR_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
+#define GET_CBR_RG_DP_RP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_CBR_RG_DP_RHP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_CBR_RG_DP_DR3 (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x00700000 ) >> 20)
+#define GET_CBR_RG_DP_DCP (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x07800000 ) >> 23)
+#define GET_CBR_RG_DP_DCS (((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x78000000 ) >> 27)
+#define GET_CBR_RG_DP_FBDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x00000fff ) >> 0)
+#define GET_CBR_RG_DP_FODIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003ff000 ) >> 12)
+#define GET_CBR_RG_DP_REFDIV (((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00000 ) >> 22)
+#define GET_CBR_RG_IDACAI_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG15 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG14 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG13 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG12 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG11 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG10 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG9 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG8 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG7 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG6 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG5 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG4 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG3 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG2 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_IDACAI_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_CBR_RG_IDACAQ_PGAG1 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
+#define GET_CBR_RG_IDACAI_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
+#define GET_CBR_RG_IDACAQ_PGAG0 (((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
+#define GET_CBR_RG_EN_RCAL (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_RCAL_SPD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_CBR_RG_RCAL_TMR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
+#define GET_CBR_RG_RCAL_CODE_CWR (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_CBR_RG_RCAL_CODE_CWD (((REG32(ADR_CBR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
+#define GET_CBR_RG_SX_SUB_SEL_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_SX_SUB_SEL_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x000000fe ) >> 1)
+#define GET_CBR_RG_DP_BBPLL_BS_CWR (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_CBR_RG_DP_BBPLL_BS_CWD (((REG32(ADR_CBR_MANUAL_REGISTER)) & 0x00007e00 ) >> 9)
+#define GET_CBR_RCAL_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
+#define GET_CBR_DA_LCK_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
+#define GET_CBR_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
+#define GET_CBR_DP_VT_MON_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000008 ) >> 3)
+#define GET_CBR_CH_RDY (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00000010 ) >> 4)
+#define GET_CBR_DA_R_CODE_LUT (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
+#define GET_CBR_AD_SX_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
+#define GET_CBR_AD_DP_VT_MON_Q (((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
+#define GET_CBR_DA_R_CAL_CODE (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
+#define GET_CBR_DA_SX_SUB_SEL (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
+#define GET_CBR_DA_DP_BBPLL_BS (((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0x0003f000 ) >> 12)
+#define GET_CBR_TX_EN (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000001 ) >> 0)
+#define GET_CBR_TX_CNT_RST (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00000002 ) >> 1)
+#define GET_CBR_IFS_TIME (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000000fc ) >> 2)
+#define GET_CBR_LENGTH_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x000fff00 ) >> 8)
+#define GET_CBR_TX_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xff000000 ) >> 24)
+#define GET_CBR_TC_CNT_TARGET (((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0x00ffffff ) >> 0)
+#define GET_CBR_PLCP_PSDU_DATA_MEM (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x000000ff ) >> 0)
+#define GET_CBR_PLCP_PSDU_PREAMBLE_SHORT (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00000100 ) >> 8)
+#define GET_CBR_PLCP_BYTE_LENGTH (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x001ffe00 ) >> 9)
+#define GET_CBR_PLCP_PSDU_RATE (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x00600000 ) >> 21)
+#define GET_CBR_TAIL_TIME (((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0x1f800000 ) >> 23)
+#define GET_CBR_RG_O_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000001 ) >> 0)
+#define GET_CBR_RG_I_PAD_PD (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000002 ) >> 1)
+#define GET_CBR_SEL_ADCKP_INV (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000004 ) >> 2)
+#define GET_CBR_RG_PAD_DS (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000008 ) >> 3)
+#define GET_CBR_SEL_ADCKP_MUX (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000010 ) >> 4)
+#define GET_CBR_RG_PAD_DS_CLK (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000020 ) >> 5)
+#define GET_CBR_INTP_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000200 ) >> 9)
+#define GET_CBR_IQ_SWP (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000400 ) >> 10)
+#define GET_CBR_RG_EN_EXT_DA (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00000800 ) >> 11)
+#define GET_CBR_RG_DIS_DA_OFFSET (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00001000 ) >> 12)
+#define GET_CBR_DBG_SEL (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x000f0000 ) >> 16)
+#define GET_CBR_DBG_EN (((REG32(ADR_CBR_RG_INTEGRATION)) & 0x00100000 ) >> 20)
+#define GET_CBR_RG_PKT_GEN_TX_CNT (((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0xffffffff ) >> 0)
+#define GET_CBR_TP_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x0000001f ) >> 0)
+#define GET_CBR_IDEAL_IQ_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000020 ) >> 5)
+#define GET_CBR_DATA_OUT_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x000001c0 ) >> 6)
+#define GET_CBR_TWO_TONE_EN (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00000200 ) >> 9)
+#define GET_CBR_FREQ_SEL (((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ff0000 ) >> 16)
+#define GET_CBR_IQ_SCALE (((REG32(ADR_CBR_PATTERN_GEN)) & 0xff000000 ) >> 24)
+#define GET_CPU_QUE_POP (((REG32(ADR_MB_CPU_INT)) & 0x00000001 ) >> 0)
+#define GET_CPU_INT (((REG32(ADR_MB_CPU_INT)) & 0x00000004 ) >> 2)
+#define GET_CPU_ID_TB0 (((REG32(ADR_CPU_ID_TB0)) & 0xffffffff ) >> 0)
+#define GET_CPU_ID_TB1 (((REG32(ADR_CPU_ID_TB1)) & 0xffffffff ) >> 0)
+#define GET_HW_PKTID (((REG32(ADR_CH0_TRIG_1)) & 0x000007ff ) >> 0)
+#define GET_CH0_INT_ADDR (((REG32(ADR_CH0_TRIG_0)) & 0xffffffff ) >> 0)
+#define GET_PRI_HW_PKTID (((REG32(ADR_CH0_PRI_TRIG)) & 0x000007ff ) >> 0)
+#define GET_CH0_FULL (((REG32(ADR_MCU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_FF0_EMPTY (((REG32(ADR_MCU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_RLS_BUSY (((REG32(ADR_MCU_STATUS)) & 0x00000200 ) >> 9)
+#define GET_RLS_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000400 ) >> 10)
+#define GET_RTN_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000800 ) >> 11)
+#define GET_RLS_COUNT (((REG32(ADR_MCU_STATUS)) & 0x00ff0000 ) >> 16)
+#define GET_RTN_COUNT (((REG32(ADR_MCU_STATUS)) & 0xff000000 ) >> 24)
+#define GET_FF0_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x0000001f ) >> 0)
+#define GET_FF1_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000001e0 ) >> 5)
+#define GET_FF3_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00003800 ) >> 11)
+#define GET_FF5_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000e0000 ) >> 17)
+#define GET_FF6_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00700000 ) >> 20)
+#define GET_FF7_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x03800000 ) >> 23)
+#define GET_FF8_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x1c000000 ) >> 26)
+#define GET_FF9_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0xe0000000 ) >> 29)
+#define GET_FF10_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000007 ) >> 0)
+#define GET_FF11_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000038 ) >> 3)
+#define GET_FF12_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000001c0 ) >> 6)
+#define GET_FF13_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000600 ) >> 9)
+#define GET_FF14_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00001800 ) >> 11)
+#define GET_FF15_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00006000 ) >> 13)
+#define GET_FF4_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000f8000 ) >> 15)
+#define GET_FF2_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00700000 ) >> 20)
+#define GET_CH1_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000002 ) >> 1)
+#define GET_CH2_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000004 ) >> 2)
+#define GET_CH3_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000008 ) >> 3)
+#define GET_CH4_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000010 ) >> 4)
+#define GET_CH5_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000020 ) >> 5)
+#define GET_CH6_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000040 ) >> 6)
+#define GET_CH7_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000080 ) >> 7)
+#define GET_CH8_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000100 ) >> 8)
+#define GET_CH9_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000200 ) >> 9)
+#define GET_CH10_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000400 ) >> 10)
+#define GET_CH11_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000800 ) >> 11)
+#define GET_CH12_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00001000 ) >> 12)
+#define GET_CH13_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00002000 ) >> 13)
+#define GET_CH14_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00004000 ) >> 14)
+#define GET_CH15_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00008000 ) >> 15)
+#define GET_HALT_CH0 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000001 ) >> 0)
+#define GET_HALT_CH1 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000002 ) >> 1)
+#define GET_HALT_CH2 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000004 ) >> 2)
+#define GET_HALT_CH3 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000008 ) >> 3)
+#define GET_HALT_CH4 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000010 ) >> 4)
+#define GET_HALT_CH5 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000020 ) >> 5)
+#define GET_HALT_CH6 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000040 ) >> 6)
+#define GET_HALT_CH7 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000080 ) >> 7)
+#define GET_HALT_CH8 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000100 ) >> 8)
+#define GET_HALT_CH9 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000200 ) >> 9)
+#define GET_HALT_CH10 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000400 ) >> 10)
+#define GET_HALT_CH11 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000800 ) >> 11)
+#define GET_HALT_CH12 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00001000 ) >> 12)
+#define GET_HALT_CH13 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00002000 ) >> 13)
+#define GET_HALT_CH14 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00004000 ) >> 14)
+#define GET_HALT_CH15 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00008000 ) >> 15)
+#define GET_STOP_MBOX (((REG32(ADR_MBOX_HALT_CFG)) & 0x00010000 ) >> 16)
+#define GET_MB_ERR_AUTO_HALT_EN (((REG32(ADR_MBOX_HALT_CFG)) & 0x00100000 ) >> 20)
+#define GET_MB_EXCEPT_CLR (((REG32(ADR_MBOX_HALT_CFG)) & 0x00200000 ) >> 21)
+#define GET_MB_EXCEPT_CASE (((REG32(ADR_MBOX_HALT_CFG)) & 0xff000000 ) >> 24)
+#define GET_MB_DBG_TIME_STEP (((REG32(ADR_MB_DBG_CFG1)) & 0x0000ffff ) >> 0)
+#define GET_DBG_TYPE (((REG32(ADR_MB_DBG_CFG1)) & 0x00030000 ) >> 16)
+#define GET_MB_DBG_CLR (((REG32(ADR_MB_DBG_CFG1)) & 0x00040000 ) >> 18)
+#define GET_DBG_ALC_LOG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x00080000 ) >> 19)
+#define GET_MB_DBG_COUNTER_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x01000000 ) >> 24)
+#define GET_MB_DBG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x80000000 ) >> 31)
+#define GET_MB_DBG_RECORD_CNT (((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff ) >> 0)
+#define GET_MB_DBG_LENGTH (((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000 ) >> 16)
+#define GET_MB_DBG_CFG_ADDR (((REG32(ADR_MB_DBG_CFG3)) & 0xffffffff ) >> 0)
+#define GET_DBG_HWID0_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000001 ) >> 0)
+#define GET_DBG_HWID1_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000002 ) >> 1)
+#define GET_DBG_HWID2_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000004 ) >> 2)
+#define GET_DBG_HWID3_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000008 ) >> 3)
+#define GET_DBG_HWID4_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000010 ) >> 4)
+#define GET_DBG_HWID5_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000020 ) >> 5)
+#define GET_DBG_HWID6_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000040 ) >> 6)
+#define GET_DBG_HWID7_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000080 ) >> 7)
+#define GET_DBG_HWID8_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000100 ) >> 8)
+#define GET_DBG_HWID9_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000200 ) >> 9)
+#define GET_DBG_HWID10_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000400 ) >> 10)
+#define GET_DBG_HWID11_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000800 ) >> 11)
+#define GET_DBG_HWID12_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00001000 ) >> 12)
+#define GET_DBG_HWID13_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00002000 ) >> 13)
+#define GET_DBG_HWID14_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00004000 ) >> 14)
+#define GET_DBG_HWID15_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00008000 ) >> 15)
+#define GET_DBG_HWID0_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00010000 ) >> 16)
+#define GET_DBG_HWID1_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00020000 ) >> 17)
+#define GET_DBG_HWID2_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00040000 ) >> 18)
+#define GET_DBG_HWID3_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00080000 ) >> 19)
+#define GET_DBG_HWID4_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00100000 ) >> 20)
+#define GET_DBG_HWID5_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00200000 ) >> 21)
+#define GET_DBG_HWID6_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00400000 ) >> 22)
+#define GET_DBG_HWID7_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00800000 ) >> 23)
+#define GET_DBG_HWID8_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x01000000 ) >> 24)
+#define GET_DBG_HWID9_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x02000000 ) >> 25)
+#define GET_DBG_HWID10_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x04000000 ) >> 26)
+#define GET_DBG_HWID11_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x08000000 ) >> 27)
+#define GET_DBG_HWID12_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x10000000 ) >> 28)
+#define GET_DBG_HWID13_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x20000000 ) >> 29)
+#define GET_DBG_HWID14_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x40000000 ) >> 30)
+#define GET_DBG_HWID15_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x80000000 ) >> 31)
+#define GET_MB_OUT_QUEUE_EN (((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0x00000002 ) >> 1)
+#define GET_CH0_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000001 ) >> 0)
+#define GET_CH1_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000002 ) >> 1)
+#define GET_CH2_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000004 ) >> 2)
+#define GET_CH3_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000008 ) >> 3)
+#define GET_CH4_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000010 ) >> 4)
+#define GET_CH5_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000020 ) >> 5)
+#define GET_CH6_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000040 ) >> 6)
+#define GET_CH7_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000080 ) >> 7)
+#define GET_CH8_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000100 ) >> 8)
+#define GET_CH9_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000200 ) >> 9)
+#define GET_CH10_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000400 ) >> 10)
+#define GET_CH11_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000800 ) >> 11)
+#define GET_CH12_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00001000 ) >> 12)
+#define GET_CH13_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00002000 ) >> 13)
+#define GET_CH14_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00004000 ) >> 14)
+#define GET_CH15_QUEUE_FLUSH (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00008000 ) >> 15)
+#define GET_FFO0_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0000001f ) >> 0)
+#define GET_FFO1_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000003e0 ) >> 5)
+#define GET_FFO2_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00000c00 ) >> 10)
+#define GET_FFO3_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000f8000 ) >> 15)
+#define GET_FFO4_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00300000 ) >> 20)
+#define GET_FFO5_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0e000000 ) >> 25)
+#define GET_FFO6_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x0000000f ) >> 0)
+#define GET_FFO7_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000003e0 ) >> 5)
+#define GET_FFO8_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00007c00 ) >> 10)
+#define GET_FFO9_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000f8000 ) >> 15)
+#define GET_FFO10_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00f00000 ) >> 20)
+#define GET_FFO11_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x3e000000 ) >> 25)
+#define GET_FFO12_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000007 ) >> 0)
+#define GET_FFO13_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000060 ) >> 5)
+#define GET_FFO14_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000c00 ) >> 10)
+#define GET_FFO15_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x001f8000 ) >> 15)
+#define GET_CH0_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000001 ) >> 0)
+#define GET_CH1_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000002 ) >> 1)
+#define GET_CH2_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000004 ) >> 2)
+#define GET_CH3_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000008 ) >> 3)
+#define GET_CH4_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000010 ) >> 4)
+#define GET_CH5_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000020 ) >> 5)
+#define GET_CH6_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000040 ) >> 6)
+#define GET_CH7_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000080 ) >> 7)
+#define GET_CH8_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000100 ) >> 8)
+#define GET_CH9_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000200 ) >> 9)
+#define GET_CH10_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000400 ) >> 10)
+#define GET_CH11_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000800 ) >> 11)
+#define GET_CH12_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00001000 ) >> 12)
+#define GET_CH13_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00002000 ) >> 13)
+#define GET_CH14_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00004000 ) >> 14)
+#define GET_CH15_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00008000 ) >> 15)
+#define GET_CH0_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000001 ) >> 0)
+#define GET_CH1_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000002 ) >> 1)
+#define GET_CH2_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000004 ) >> 2)
+#define GET_CH3_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000008 ) >> 3)
+#define GET_CH4_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000010 ) >> 4)
+#define GET_CH5_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000020 ) >> 5)
+#define GET_CH6_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000040 ) >> 6)
+#define GET_CH7_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000080 ) >> 7)
+#define GET_CH8_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000100 ) >> 8)
+#define GET_CH9_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000200 ) >> 9)
+#define GET_CH10_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000400 ) >> 10)
+#define GET_CH11_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000800 ) >> 11)
+#define GET_CH12_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00001000 ) >> 12)
+#define GET_CH13_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00002000 ) >> 13)
+#define GET_CH14_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00004000 ) >> 14)
+#define GET_CH15_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00008000 ) >> 15)
+#define GET_MB_LOW_THOLD_EN (((REG32(ADR_MB_THRESHOLD6)) & 0x80000000 ) >> 31)
+#define GET_CH0_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x0000001f ) >> 0)
+#define GET_CH1_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x00001f00 ) >> 8)
+#define GET_CH2_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x001f0000 ) >> 16)
+#define GET_CH3_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x1f000000 ) >> 24)
+#define GET_CH4_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x0000001f ) >> 0)
+#define GET_CH5_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x00001f00 ) >> 8)
+#define GET_CH6_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x001f0000 ) >> 16)
+#define GET_CH7_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x1f000000 ) >> 24)
+#define GET_CH8_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x0000001f ) >> 0)
+#define GET_CH9_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x00001f00 ) >> 8)
+#define GET_CH10_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x001f0000 ) >> 16)
+#define GET_CH11_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x1f000000 ) >> 24)
+#define GET_CH12_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x0000001f ) >> 0)
+#define GET_CH13_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x00001f00 ) >> 8)
+#define GET_CH14_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x001f0000 ) >> 16)
+#define GET_CH15_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x1f000000 ) >> 24)
+#define GET_TRASH_TIMEOUT_EN (((REG32(ADR_MB_TRASH_CFG)) & 0x00000001 ) >> 0)
+#define GET_TRASH_CAN_INT (((REG32(ADR_MB_TRASH_CFG)) & 0x00000002 ) >> 1)
+#define GET_TRASH_INT_ID (((REG32(ADR_MB_TRASH_CFG)) & 0x000007f0 ) >> 4)
+#define GET_TRASH_TIMEOUT (((REG32(ADR_MB_TRASH_CFG)) & 0x03ff0000 ) >> 16)
+#define GET_CH0_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000001 ) >> 0)
+#define GET_CH1_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000002 ) >> 1)
+#define GET_CH2_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000004 ) >> 2)
+#define GET_CH3_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000008 ) >> 3)
+#define GET_CH4_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000010 ) >> 4)
+#define GET_CH5_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000020 ) >> 5)
+#define GET_CH6_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000040 ) >> 6)
+#define GET_CH7_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000080 ) >> 7)
+#define GET_CH8_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000100 ) >> 8)
+#define GET_CH9_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000200 ) >> 9)
+#define GET_CH10_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000400 ) >> 10)
+#define GET_CH11_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000800 ) >> 11)
+#define GET_CH12_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00001000 ) >> 12)
+#define GET_CH13_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00002000 ) >> 13)
+#define GET_CH14_WRFF_FLUSH (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00004000 ) >> 14)
+#define GET_CPU_ID_TB2 (((REG32(ADR_CPU_ID_TB2)) & 0xffffffff ) >> 0)
+#define GET_CPU_ID_TB3 (((REG32(ADR_CPU_ID_TB3)) & 0xffffffff ) >> 0)
+#define GET_IQ_LOG_EN (((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0x00000001 ) >> 0)
+#define GET_IQ_LOG_STOP_MODE (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000001 ) >> 0)
+#define GET_GPIO_STOP_EN (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000010 ) >> 4)
+#define GET_GPIO_STOP_POL (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000020 ) >> 5)
+#define GET_IQ_LOG_TIMER (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffff0000 ) >> 16)
+#define GET_IQ_LOG_LEN (((REG32(ADR_PHY_IQ_LOG_LEN)) & 0x0000ffff ) >> 0)
+#define GET_IQ_LOG_TAIL_ADR (((REG32(ADR_PHY_IQ_LOG_PTR)) & 0x0000ffff ) >> 0)
+#define GET_ALC_LENG (((REG32(ADR_WR_ALC)) & 0x0003ffff ) >> 0)
+#define GET_CH0_DYN_PRI (((REG32(ADR_WR_ALC)) & 0x00300000 ) >> 20)
+#define GET_MCU_PKTID (((REG32(ADR_GETID)) & 0xffffffff ) >> 0)
+#define GET_CH0_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000003 ) >> 0)
+#define GET_CH1_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000030 ) >> 4)
+#define GET_CH2_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000300 ) >> 8)
+#define GET_CH3_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00003000 ) >> 12)
+#define GET_ID_TB0 (((REG32(ADR_RD_ID0)) & 0xffffffff ) >> 0)
+#define GET_ID_TB1 (((REG32(ADR_RD_ID1)) & 0xffffffff ) >> 0)
+#define GET_ID_MNG_HALT (((REG32(ADR_IMD_CFG)) & 0x00000010 ) >> 4)
+#define GET_ID_MNG_ERR_HALT_EN (((REG32(ADR_IMD_CFG)) & 0x00000020 ) >> 5)
+#define GET_ID_EXCEPT_FLG_CLR (((REG32(ADR_IMD_CFG)) & 0x00000040 ) >> 6)
+#define GET_ID_EXCEPT_FLG (((REG32(ADR_IMD_CFG)) & 0x00000080 ) >> 7)
+#define GET_ID_FULL (((REG32(ADR_IMD_STA)) & 0x00000001 ) >> 0)
+#define GET_ID_MNG_BUSY (((REG32(ADR_IMD_STA)) & 0x00000002 ) >> 1)
+#define GET_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000004 ) >> 2)
+#define GET_CH0_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000010 ) >> 4)
+#define GET_CH1_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000020 ) >> 5)
+#define GET_CH2_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000040 ) >> 6)
+#define GET_CH3_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000080 ) >> 7)
+#define GET_REQ_LOCK_INT_EN (((REG32(ADR_IMD_STA)) & 0x00000100 ) >> 8)
+#define GET_REQ_LOCK_INT (((REG32(ADR_IMD_STA)) & 0x00000200 ) >> 9)
+#define GET_MCU_ALC_READY (((REG32(ADR_ALC_STA)) & 0x00000001 ) >> 0)
+#define GET_ALC_FAIL (((REG32(ADR_ALC_STA)) & 0x00000002 ) >> 1)
+#define GET_ALC_BUSY (((REG32(ADR_ALC_STA)) & 0x00000004 ) >> 2)
+#define GET_CH0_NVLD (((REG32(ADR_ALC_STA)) & 0x00000010 ) >> 4)
+#define GET_CH1_NVLD (((REG32(ADR_ALC_STA)) & 0x00000020 ) >> 5)
+#define GET_CH2_NVLD (((REG32(ADR_ALC_STA)) & 0x00000040 ) >> 6)
+#define GET_CH3_NVLD (((REG32(ADR_ALC_STA)) & 0x00000080 ) >> 7)
+#define GET_ALC_INT_ID (((REG32(ADR_ALC_STA)) & 0x00007f00 ) >> 8)
+#define GET_ALC_TIMEOUT (((REG32(ADR_ALC_STA)) & 0x03ff0000 ) >> 16)
+#define GET_ALC_TIMEOUT_INT_EN (((REG32(ADR_ALC_STA)) & 0x40000000 ) >> 30)
+#define GET_ALC_TIMEOUT_INT (((REG32(ADR_ALC_STA)) & 0x80000000 ) >> 31)
+#define GET_TX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x000000ff ) >> 0)
+#define GET_RX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x0000ff00 ) >> 8)
+#define GET_TX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000000ff ) >> 0)
+#define GET_RX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x0000ff00 ) >> 8)
+#define GET_ID_THOLD_RX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00010000 ) >> 16)
+#define GET_RX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000e0000 ) >> 17)
+#define GET_ID_THOLD_TX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00100000 ) >> 20)
+#define GET_TX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00e00000 ) >> 21)
+#define GET_ID_THOLD_INT_EN (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x01000000 ) >> 24)
+#define GET_TX_ID_TB0 (((REG32(ADR_TX_ID0)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB1 (((REG32(ADR_TX_ID1)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB0 (((REG32(ADR_RX_ID0)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB1 (((REG32(ADR_RX_ID1)) & 0xffffffff ) >> 0)
+#define GET_DOUBLE_RLS_INT_EN (((REG32(ADR_RTN_STA)) & 0x00000001 ) >> 0)
+#define GET_ID_DOUBLE_RLS_INT (((REG32(ADR_RTN_STA)) & 0x00000002 ) >> 1)
+#define GET_DOUBLE_RLS_ID (((REG32(ADR_RTN_STA)) & 0x00007f00 ) >> 8)
+#define GET_ID_LEN_THOLD_INT_EN (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000001 ) >> 0)
+#define GET_ALL_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000002 ) >> 1)
+#define GET_TX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000004 ) >> 2)
+#define GET_RX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000008 ) >> 3)
+#define GET_ID_TX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00001ff0 ) >> 4)
+#define GET_ID_RX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x003fe000 ) >> 13)
+#define GET_ID_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x7fc00000 ) >> 22)
+#define GET_ALL_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x0003fe00 ) >> 9)
+#define GET_RX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x07fc0000 ) >> 18)
+#define GET_CH_ARB_EN (((REG32(ADR_CH_ARB_PRI)) & 0x00000001 ) >> 0)
+#define GET_CH_PRI1 (((REG32(ADR_CH_ARB_PRI)) & 0x00000030 ) >> 4)
+#define GET_CH_PRI2 (((REG32(ADR_CH_ARB_PRI)) & 0x00000300 ) >> 8)
+#define GET_CH_PRI3 (((REG32(ADR_CH_ARB_PRI)) & 0x00003000 ) >> 12)
+#define GET_CH_PRI4 (((REG32(ADR_CH_ARB_PRI)) & 0x00030000 ) >> 16)
+#define GET_TX_ID_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0000007f ) >> 0)
+#define GET_TX_PAGE_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0001ff00 ) >> 8)
+#define GET_ID_PAGE_MAX_SIZE (((REG32(ADR_ID_INFO_STA)) & 0x000001ff ) >> 0)
+#define GET_TX_PAGE_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x000001ff ) >> 0)
+#define GET_TX_COUNT_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x00ff0000 ) >> 16)
+#define GET_TX_LIMIT_INT (((REG32(ADR_TX_LIMIT_INTR)) & 0x40000000 ) >> 30)
+#define GET_TX_LIMIT_INT_EN (((REG32(ADR_TX_LIMIT_INTR)) & 0x80000000 ) >> 31)
+#define GET_TX_PAGE_USE_7_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x000000ff ) >> 0)
+#define GET_TX_ID_USE_5_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x00003f00 ) >> 8)
+#define GET_EDCA0_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x0003c000 ) >> 14)
+#define GET_EDCA1_FFO_CNT_3_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x003c0000 ) >> 18)
+#define GET_EDCA2_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x07c00000 ) >> 22)
+#define GET_EDCA3_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0xf8000000 ) >> 27)
+#define GET_ID_TB2 (((REG32(ADR_RD_ID2)) & 0xffffffff ) >> 0)
+#define GET_ID_TB3 (((REG32(ADR_RD_ID3)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB2 (((REG32(ADR_TX_ID2)) & 0xffffffff ) >> 0)
+#define GET_TX_ID_TB3 (((REG32(ADR_TX_ID3)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB2 (((REG32(ADR_RX_ID2)) & 0xffffffff ) >> 0)
+#define GET_RX_ID_TB3 (((REG32(ADR_RX_ID3)) & 0xffffffff ) >> 0)
+#define GET_TX_PAGE_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA4_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x001e0000 ) >> 17)
+#define GET_TX_PAGE_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA1_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x03e00000 ) >> 21)
+#define GET_EDCA4_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x3c000000 ) >> 26)
+#define GET_TX_PAGE_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x000001ff ) >> 0)
+#define GET_TX_ID_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x0001fe00 ) >> 9)
+#define GET_EDCA2_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x003e0000 ) >> 17)
+#define GET_EDCA3_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x07c00000 ) >> 22)
+#define GET_TX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x000001ff ) >> 0)
+#define GET_RX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x01ff0000 ) >> 16)
+#define GET_MAX_ALL_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x000000ff ) >> 0)
+#define GET_MAX_TX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x0000ff00 ) >> 8)
+#define GET_MAX_RX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x00ff0000 ) >> 16)
+#define GET_MAX_ALL_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x000001ff ) >> 0)
+#define GET_MAX_TX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x0003fe00 ) >> 9)
+#define GET_MAX_RX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x07fc0000 ) >> 18)
+#define GET_RG_PMDLBK (((REG32(ADR_PHY_EN_0)) & 0x00000001 ) >> 0)
+#define GET_RG_RDYACK_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000006 ) >> 1)
+#define GET_RG_ADEDGE_SEL (((REG32(ADR_PHY_EN_0)) & 0x00000008 ) >> 3)
+#define GET_RG_SIGN_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000010 ) >> 4)
+#define GET_RG_IQ_SWAP (((REG32(ADR_PHY_EN_0)) & 0x00000020 ) >> 5)
+#define GET_RG_Q_INV (((REG32(ADR_PHY_EN_0)) & 0x00000040 ) >> 6)
+#define GET_RG_I_INV (((REG32(ADR_PHY_EN_0)) & 0x00000080 ) >> 7)
+#define GET_RG_BYPASS_ACI (((REG32(ADR_PHY_EN_0)) & 0x00000100 ) >> 8)
+#define GET_RG_LBK_ANA_PATH (((REG32(ADR_PHY_EN_0)) & 0x00000200 ) >> 9)
+#define GET_RG_SPECTRUM_LEAKY_FACTOR (((REG32(ADR_PHY_EN_0)) & 0x00000c00 ) >> 10)
+#define GET_RG_SPECTRUM_BW (((REG32(ADR_PHY_EN_0)) & 0x00003000 ) >> 12)
+#define GET_RG_SPECTRUM_FREQ_MANUAL (((REG32(ADR_PHY_EN_0)) & 0x00004000 ) >> 14)
+#define GET_RG_SPECTRUM_EN (((REG32(ADR_PHY_EN_0)) & 0x00008000 ) >> 15)
+#define GET_RG_TXPWRLVL_SET (((REG32(ADR_PHY_EN_0)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TXPWRLVL_SEL (((REG32(ADR_PHY_EN_0)) & 0x01000000 ) >> 24)
+#define GET_RG_RF_BB_CLK_SEL (((REG32(ADR_PHY_EN_0)) & 0x80000000 ) >> 31)
+#define GET_RG_PHY_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000001 ) >> 0)
+#define GET_RG_PHYRX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000002 ) >> 1)
+#define GET_RG_PHYTX_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000004 ) >> 2)
+#define GET_RG_PHY11GN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000008 ) >> 3)
+#define GET_RG_PHY11B_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000010 ) >> 4)
+#define GET_RG_PHYRXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000020 ) >> 5)
+#define GET_RG_PHYTXFIFO_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000040 ) >> 6)
+#define GET_RG_PHY11BGN_MD_EN (((REG32(ADR_PHY_EN_1)) & 0x00000100 ) >> 8)
+#define GET_RG_FORCE_11GN_EN (((REG32(ADR_PHY_EN_1)) & 0x00001000 ) >> 12)
+#define GET_RG_FORCE_11B_EN (((REG32(ADR_PHY_EN_1)) & 0x00002000 ) >> 13)
+#define GET_RG_FFT_MEM_CLK_EN_RX (((REG32(ADR_PHY_EN_1)) & 0x00004000 ) >> 14)
+#define GET_RG_FFT_MEM_CLK_EN_TX (((REG32(ADR_PHY_EN_1)) & 0x00008000 ) >> 15)
+#define GET_RG_PHY_IQ_TRIG_SEL (((REG32(ADR_PHY_EN_1)) & 0x000f0000 ) >> 16)
+#define GET_RG_SPECTRUM_FREQ (((REG32(ADR_PHY_EN_1)) & 0x3ff00000 ) >> 20)
+#define GET_SVN_VERSION (((REG32(ADR_SVN_VERSION_REG)) & 0xffffffff ) >> 0)
+#define GET_RG_LENGTH (((REG32(ADR_PHY_PKT_GEN_0)) & 0x0000ffff ) >> 0)
+#define GET_RG_PKT_MODE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00070000 ) >> 16)
+#define GET_RG_CH_BW (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00380000 ) >> 19)
+#define GET_RG_PRM (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00400000 ) >> 22)
+#define GET_RG_SHORTGI (((REG32(ADR_PHY_PKT_GEN_0)) & 0x00800000 ) >> 23)
+#define GET_RG_RATE (((REG32(ADR_PHY_PKT_GEN_0)) & 0x7f000000 ) >> 24)
+#define GET_RG_L_LENGTH (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00000fff ) >> 0)
+#define GET_RG_L_RATE (((REG32(ADR_PHY_PKT_GEN_1)) & 0x00007000 ) >> 12)
+#define GET_RG_SERVICE (((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff0000 ) >> 16)
+#define GET_RG_SMOOTHING (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000001 ) >> 0)
+#define GET_RG_NO_SOUND (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000002 ) >> 1)
+#define GET_RG_AGGREGATE (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000004 ) >> 2)
+#define GET_RG_STBC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000018 ) >> 3)
+#define GET_RG_FEC (((REG32(ADR_PHY_PKT_GEN_2)) & 0x00000020 ) >> 5)
+#define GET_RG_N_ESS (((REG32(ADR_PHY_PKT_GEN_2)) & 0x000000c0 ) >> 6)
+#define GET_RG_TXPWRLVL (((REG32(ADR_PHY_PKT_GEN_2)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TX_START (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000001 ) >> 0)
+#define GET_RG_IFS_TIME (((REG32(ADR_PHY_PKT_GEN_3)) & 0x000000fc ) >> 2)
+#define GET_RG_CONTINUOUS_DATA (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000100 ) >> 8)
+#define GET_RG_DATA_SEL (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00000600 ) >> 9)
+#define GET_RG_TX_D (((REG32(ADR_PHY_PKT_GEN_3)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_CNT_TARGET (((REG32(ADR_PHY_PKT_GEN_4)) & 0xffffffff ) >> 0)
+#define GET_RG_FFT_IFFT_MODE (((REG32(ADR_PHY_REG_00)) & 0x000000c0 ) >> 6)
+#define GET_RG_DAC_DBG_MODE (((REG32(ADR_PHY_REG_00)) & 0x00000100 ) >> 8)
+#define GET_RG_DAC_SGN_SWAP (((REG32(ADR_PHY_REG_00)) & 0x00000200 ) >> 9)
+#define GET_RG_TXD_SEL (((REG32(ADR_PHY_REG_00)) & 0x00000c00 ) >> 10)
+#define GET_RG_UP8X (((REG32(ADR_PHY_REG_00)) & 0x00ff0000 ) >> 16)
+#define GET_RG_IQ_DC_BYP (((REG32(ADR_PHY_REG_00)) & 0x01000000 ) >> 24)
+#define GET_RG_IQ_DC_LEAKY_FACTOR (((REG32(ADR_PHY_REG_00)) & 0x30000000 ) >> 28)
+#define GET_RG_DAC_DCEN (((REG32(ADR_PHY_REG_01)) & 0x00000001 ) >> 0)
+#define GET_RG_DAC_DCQ (((REG32(ADR_PHY_REG_01)) & 0x00003ff0 ) >> 4)
+#define GET_RG_DAC_DCI (((REG32(ADR_PHY_REG_01)) & 0x03ff0000 ) >> 16)
+#define GET_RG_PGA_REFDB_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0x0000007f ) >> 0)
+#define GET_RG_PGA_REFDB_TOP (((REG32(ADR_PHY_REG_02_AGC)) & 0x00007f00 ) >> 8)
+#define GET_RG_PGA_REF_UND (((REG32(ADR_PHY_REG_02_AGC)) & 0x03ff0000 ) >> 16)
+#define GET_RG_RF_REF_SAT (((REG32(ADR_PHY_REG_02_AGC)) & 0xf0000000 ) >> 28)
+#define GET_RG_PGAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x0000000f ) >> 0)
+#define GET_RG_PGAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000010 ) >> 4)
+#define GET_RG_RFGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000060 ) >> 5)
+#define GET_RG_RFGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00000080 ) >> 7)
+#define GET_RG_WAIT_T_RXAGC (((REG32(ADR_PHY_REG_03_AGC)) & 0x00003f00 ) >> 8)
+#define GET_RG_RXAGC_SET (((REG32(ADR_PHY_REG_03_AGC)) & 0x00004000 ) >> 14)
+#define GET_RG_RXAGC_OW (((REG32(ADR_PHY_REG_03_AGC)) & 0x00008000 ) >> 15)
+#define GET_RG_WAIT_T_FINAL (((REG32(ADR_PHY_REG_03_AGC)) & 0x003f0000 ) >> 16)
+#define GET_RG_WAIT_T (((REG32(ADR_PHY_REG_03_AGC)) & 0x3f000000 ) >> 24)
+#define GET_RG_ULG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000000f ) >> 0)
+#define GET_RG_LG_PGA_UND_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000000f0 ) >> 4)
+#define GET_RG_LG_PGA_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00000f00 ) >> 8)
+#define GET_RG_LG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0000f000 ) >> 12)
+#define GET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x000f0000 ) >> 16)
+#define GET_RG_HG_PGA_SAT2_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x00f00000 ) >> 20)
+#define GET_RG_HG_PGA_SAT1_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0x0f000000 ) >> 24)
+#define GET_RG_HG_RF_SAT_PGA_GAIN (((REG32(ADR_PHY_REG_04_AGC)) & 0xf0000000 ) >> 28)
+#define GET_RG_MG_PGA_JB_TH (((REG32(ADR_PHY_REG_05_AGC)) & 0x0000000f ) >> 0)
+#define GET_RG_MA_PGA_LOW_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x001f0000 ) >> 16)
+#define GET_RG_WR_RFGC_INIT_SET (((REG32(ADR_PHY_REG_05_AGC)) & 0x00600000 ) >> 21)
+#define GET_RG_WR_RFGC_INIT_EN (((REG32(ADR_PHY_REG_05_AGC)) & 0x00800000 ) >> 23)
+#define GET_RG_MA_PGA_HIGH_TH_CNT_LMT (((REG32(ADR_PHY_REG_05_AGC)) & 0x1f000000 ) >> 24)
+#define GET_RG_AGC_THRESHOLD (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x00003fff ) >> 0)
+#define GET_RG_ACI_POINT_CNT_LMT_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x007f0000 ) >> 16)
+#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11B (((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0x03000000 ) >> 24)
+#define GET_RG_WR_ACI_GAIN_INI_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x000000ff ) >> 0)
+#define GET_RG_WR_ACI_GAIN_SEL_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x0000ff00 ) >> 8)
+#define GET_RG_ACI_DAGC_SET_VALUE_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x007f0000 ) >> 16)
+#define GET_RG_WR_ACI_GAIN_OW_11B (((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x80000000 ) >> 31)
+#define GET_RG_ACI_POINT_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x000000ff ) >> 0)
+#define GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00000300 ) >> 8)
+#define GET_RG_ACI_DAGC_DONE_CNT_LMT_11GN (((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xff000000 ) >> 24)
+#define GET_RG_ACI_DAGC_SET_VALUE_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000007f ) >> 0)
+#define GET_RG_ACI_GAIN_INI_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x0000ff00 ) >> 8)
+#define GET_RG_ACI_GAIN_OW_VAL_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x00ff0000 ) >> 16)
+#define GET_RG_ACI_GAIN_OW_11GN (((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x80000000 ) >> 31)
+#define GET_RO_CCA_PWR_MA_11GN (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x0000007f ) >> 0)
+#define GET_RO_ED_STATE (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x00008000 ) >> 15)
+#define GET_RO_CCA_PWR_MA_11B (((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0x007f0000 ) >> 16)
+#define GET_RO_PGA_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF1 (((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
+#define GET_RO_PGA_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF2 (((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
+#define GET_RO_PGA_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x00003fff ) >> 0)
+#define GET_RO_RF_PWR_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x000f0000 ) >> 16)
+#define GET_RO_PGAGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x0f000000 ) >> 24)
+#define GET_RO_RFGC_FF3 (((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0x30000000 ) >> 28)
+#define GET_RG_TX_DES_RATE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_DES_MODE (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_DES_LEN_LO (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_DES_LEN_UP (((REG32(ADR_PHY_REG_10_TX_DES)) & 0x1f000000 ) >> 24)
+#define GET_RG_TX_DES_SRVC_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x00001f00 ) >> 8)
+#define GET_RG_TX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_DES_TYPE (((REG32(ADR_PHY_REG_11_TX_DES)) & 0x1f000000 ) >> 24)
+#define GET_RG_TX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000010 ) >> 4)
+#define GET_RG_TX_DES_RATE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00000100 ) >> 8)
+#define GET_RG_TX_DES_MODE_COMB (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x00001000 ) >> 12)
+#define GET_RG_TX_DES_PWRLVL (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x001f0000 ) >> 16)
+#define GET_RG_TX_DES_SRVC_LO (((REG32(ADR_PHY_REG_12_TX_DES)) & 0x1f000000 ) >> 24)
+#define GET_RG_RX_DES_RATE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x0000003f ) >> 0)
+#define GET_RG_RX_DES_MODE (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x00003f00 ) >> 8)
+#define GET_RG_RX_DES_LEN_LO (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x003f0000 ) >> 16)
+#define GET_RG_RX_DES_LEN_UP (((REG32(ADR_PHY_REG_13_RX_DES)) & 0x3f000000 ) >> 24)
+#define GET_RG_RX_DES_SRVC_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x0000003f ) >> 0)
+#define GET_RG_RX_DES_L_LEN_LO (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x00003f00 ) >> 8)
+#define GET_RG_RX_DES_L_LEN_UP (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x003f0000 ) >> 16)
+#define GET_RG_RX_DES_TYPE (((REG32(ADR_PHY_REG_14_RX_DES)) & 0x3f000000 ) >> 24)
+#define GET_RG_RX_DES_L_LEN_UP_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000001 ) >> 0)
+#define GET_RG_RX_DES_TYPE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000010 ) >> 4)
+#define GET_RG_RX_DES_RATE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00000100 ) >> 8)
+#define GET_RG_RX_DES_MODE_COMB (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00001000 ) >> 12)
+#define GET_RG_RX_DES_SNR (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x000f0000 ) >> 16)
+#define GET_RG_RX_DES_RCPI (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x00f00000 ) >> 20)
+#define GET_RG_RX_DES_SRVC_LO (((REG32(ADR_PHY_REG_15_RX_DES)) & 0x3f000000 ) >> 24)
+#define GET_RO_TX_DES_EXCP_RATE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x000000ff ) >> 0)
+#define GET_RO_TX_DES_EXCP_CH_BW_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x0000ff00 ) >> 8)
+#define GET_RO_TX_DES_EXCP_MODE_CNT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_DES_EXCP_RATE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x07000000 ) >> 24)
+#define GET_RG_TX_DES_EXCP_MODE_DEFAULT (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x70000000 ) >> 28)
+#define GET_RG_TX_DES_EXCP_CLR (((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x80000000 ) >> 31)
+#define GET_RG_TX_DES_ACK_WIDTH (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_DES_ACK_PRD (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x0000000e ) >> 1)
+#define GET_RG_RX_DES_SNR_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x003f0000 ) >> 16)
+#define GET_RG_RX_DES_RCPI_GN (((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0x3f000000 ) >> 24)
+#define GET_RG_TST_TBUS_SEL (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x0000000f ) >> 0)
+#define GET_RG_RSSI_OFFSET (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x00ff0000 ) >> 16)
+#define GET_RG_RSSI_INV (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x01000000 ) >> 24)
+#define GET_RG_TST_ADC_ON (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x40000000 ) >> 30)
+#define GET_RG_TST_EXT_GAIN (((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x80000000 ) >> 31)
+#define GET_RG_DAC_Q_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x000003ff ) >> 0)
+#define GET_RG_DAC_I_SET (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x003ff000 ) >> 12)
+#define GET_RG_DAC_EN_MAN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x10000000 ) >> 28)
+#define GET_RG_IQC_FFT_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x20000000 ) >> 29)
+#define GET_RG_DAC_MAN_Q_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x40000000 ) >> 30)
+#define GET_RG_DAC_MAN_I_EN (((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x80000000 ) >> 31)
+#define GET_RO_MRX_EN_CNT (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RG_MRX_EN_CNT_RST_N (((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_PA_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_RFTX_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DAC_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ff0000 ) >> 16)
+#define GET_RG_SW_RISE_TIME (((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff000000 ) >> 24)
+#define GET_RG_PA_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_RFTX_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DAC_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ff0000 ) >> 16)
+#define GET_RG_SW_FALL_TIME (((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff000000 ) >> 24)
+#define GET_RG_ANT_SW_0 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000007 ) >> 0)
+#define GET_RG_ANT_SW_1 (((REG32(ADR_PHY_REG_23_ANT)) & 0x00000038 ) >> 3)
+#define GET_RG_MTX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MTX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MTX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_MTX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MTX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MTX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_MRX_LEN_LOWER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MRX_LEN_UPPER_TH_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MRX_LEN_CNT_EN_0 (((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RG_MRX_LEN_LOWER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x00001fff ) >> 0)
+#define GET_RG_MRX_LEN_UPPER_TH_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x1fff0000 ) >> 16)
+#define GET_RG_MRX_LEN_CNT_EN_1 (((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x80000000 ) >> 31)
+#define GET_RO_MTX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff ) >> 0)
+#define GET_RO_MTX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000 ) >> 16)
+#define GET_RO_MRX_LEN_CNT_1 (((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff ) >> 0)
+#define GET_RO_MRX_LEN_CNT_0 (((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000 ) >> 16)
+#define GET_RG_MODE_REG_IN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x0000ffff ) >> 0)
+#define GET_RG_PARALLEL_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x00100000 ) >> 20)
+#define GET_RG_MBRUN_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x01000000 ) >> 24)
+#define GET_RG_SHIFT_DR_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x10000000 ) >> 28)
+#define GET_RG_MODE_REG_SI_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x20000000 ) >> 29)
+#define GET_RG_SIMULATION_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x40000000 ) >> 30)
+#define GET_RG_DBIST_MODE_16 (((REG32(ADR_PHY_REG_28_BIST)) & 0x80000000 ) >> 31)
+#define GET_RO_MODE_REG_OUT_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x0000ffff ) >> 0)
+#define GET_RO_MODE_REG_SO_16 (((REG32(ADR_PHY_READ_REG_06_BIST)) & 0x01000000 ) >> 24)
+#define GET_RO_MONITOR_BUS_16 (((REG32(ADR_PHY_READ_REG_07_BIST)) & 0x0007ffff ) >> 0)
+#define GET_RG_MRX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x000000ff ) >> 0)
+#define GET_RG_MRX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x0000ff00 ) >> 8)
+#define GET_RG_MTX_TYPE_1 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ff0000 ) >> 16)
+#define GET_RG_MTX_TYPE_0 (((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff000000 ) >> 24)
+#define GET_RO_MTX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff ) >> 0)
+#define GET_RO_MTX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000 ) >> 16)
+#define GET_RO_MRX_TYPE_CNT_1 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff ) >> 0)
+#define GET_RO_MRX_TYPE_CNT_0 (((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000 ) >> 16)
+#define GET_RG_HB_COEF0 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x00000fff ) >> 0)
+#define GET_RG_HB_COEF1 (((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
+#define GET_RG_HB_COEF2 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x00000fff ) >> 0)
+#define GET_RG_HB_COEF3 (((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0x0fff0000 ) >> 16)
+#define GET_RG_HB_COEF4 (((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0x00000fff ) >> 0)
+#define GET_RO_TBUS_O (((REG32(ADR_PHY_READ_TBUS)) & 0x000fffff ) >> 0)
+#define GET_RG_LPF4_00 (((REG32(ADR_TX_11B_FIL_COEF_00)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_01 (((REG32(ADR_TX_11B_FIL_COEF_01)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_02 (((REG32(ADR_TX_11B_FIL_COEF_02)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_03 (((REG32(ADR_TX_11B_FIL_COEF_03)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_04 (((REG32(ADR_TX_11B_FIL_COEF_04)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_05 (((REG32(ADR_TX_11B_FIL_COEF_05)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_06 (((REG32(ADR_TX_11B_FIL_COEF_06)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_07 (((REG32(ADR_TX_11B_FIL_COEF_07)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_08 (((REG32(ADR_TX_11B_FIL_COEF_08)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_09 (((REG32(ADR_TX_11B_FIL_COEF_09)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_10 (((REG32(ADR_TX_11B_FIL_COEF_10)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_11 (((REG32(ADR_TX_11B_FIL_COEF_11)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_12 (((REG32(ADR_TX_11B_FIL_COEF_12)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_13 (((REG32(ADR_TX_11B_FIL_COEF_13)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_14 (((REG32(ADR_TX_11B_FIL_COEF_14)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_15 (((REG32(ADR_TX_11B_FIL_COEF_15)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_16 (((REG32(ADR_TX_11B_FIL_COEF_16)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_17 (((REG32(ADR_TX_11B_FIL_COEF_17)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_18 (((REG32(ADR_TX_11B_FIL_COEF_18)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_19 (((REG32(ADR_TX_11B_FIL_COEF_19)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_20 (((REG32(ADR_TX_11B_FIL_COEF_20)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_21 (((REG32(ADR_TX_11B_FIL_COEF_21)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_22 (((REG32(ADR_TX_11B_FIL_COEF_22)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_23 (((REG32(ADR_TX_11B_FIL_COEF_23)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_24 (((REG32(ADR_TX_11B_FIL_COEF_24)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_25 (((REG32(ADR_TX_11B_FIL_COEF_25)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_26 (((REG32(ADR_TX_11B_FIL_COEF_26)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_27 (((REG32(ADR_TX_11B_FIL_COEF_27)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_28 (((REG32(ADR_TX_11B_FIL_COEF_28)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_29 (((REG32(ADR_TX_11B_FIL_COEF_29)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_30 (((REG32(ADR_TX_11B_FIL_COEF_30)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_31 (((REG32(ADR_TX_11B_FIL_COEF_31)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_32 (((REG32(ADR_TX_11B_FIL_COEF_32)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_33 (((REG32(ADR_TX_11B_FIL_COEF_33)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_34 (((REG32(ADR_TX_11B_FIL_COEF_34)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_35 (((REG32(ADR_TX_11B_FIL_COEF_35)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_36 (((REG32(ADR_TX_11B_FIL_COEF_36)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_37 (((REG32(ADR_TX_11B_FIL_COEF_37)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_38 (((REG32(ADR_TX_11B_FIL_COEF_38)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_39 (((REG32(ADR_TX_11B_FIL_COEF_39)) & 0x00001fff ) >> 0)
+#define GET_RG_LPF4_40 (((REG32(ADR_TX_11B_FIL_COEF_40)) & 0x00001fff ) >> 0)
+#define GET_RG_BP_SMB (((REG32(ADR_TX_11B_PLCP)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_SRVC (((REG32(ADR_TX_11B_PLCP)) & 0x00004000 ) >> 14)
+#define GET_RG_DES_SPD (((REG32(ADR_TX_11B_PLCP)) & 0x00030000 ) >> 16)
+#define GET_RG_BB_11B_RISE_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_11B_FALL_TIME (((REG32(ADR_TX_11B_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_WR_TX_EN_CNT_RST_N (((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0x00000001 ) >> 0)
+#define GET_RO_TX_EN_CNT (((REG32(ADR_TX_11B_EN_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RO_TX_CNT (((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
+#define GET_RG_POS_DES_11B_L_EXT (((REG32(ADR_RX_11B_DES_DLY)) & 0x0000000f ) >> 0)
+#define GET_RG_PRE_DES_11B_DLY (((REG32(ADR_RX_11B_DES_DLY)) & 0x000000f0 ) >> 4)
+#define GET_RG_CNT_CCA_LMT (((REG32(ADR_RX_11B_CCA_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_BYPASS_DESCRAMBLER (((REG32(ADR_RX_11B_CCA_0)) & 0x20000000 ) >> 29)
+#define GET_RG_BYPASS_AGC (((REG32(ADR_RX_11B_CCA_0)) & 0x80000000 ) >> 31)
+#define GET_RG_CCA_BIT_CNT_LMT_RX (((REG32(ADR_RX_11B_CCA_1)) & 0x000000f0 ) >> 4)
+#define GET_RG_CCA_SCALE_BF (((REG32(ADR_RX_11B_CCA_1)) & 0x007f0000 ) >> 16)
+#define GET_RG_PEAK_IDX_CNT_SEL (((REG32(ADR_RX_11B_CCA_1)) & 0x30000000 ) >> 28)
+#define GET_RG_TR_KI_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000007 ) >> 0)
+#define GET_RG_TR_KP_T2 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000070 ) >> 4)
+#define GET_RG_TR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00000700 ) >> 8)
+#define GET_RG_TR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0x00007000 ) >> 12)
+#define GET_RG_CR_KI_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00070000 ) >> 16)
+#define GET_RG_CR_KP_T1 (((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0x00700000 ) >> 20)
+#define GET_RG_CHIP_CNT_SLICER (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000001f ) >> 0)
+#define GET_RG_CE_T4_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x0000ff00 ) >> 8)
+#define GET_RG_CE_T3_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ff0000 ) >> 16)
+#define GET_RG_CE_T2_CNT_LMT (((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff000000 ) >> 24)
+#define GET_RG_CE_MU_T1 (((REG32(ADR_RX_11B_CE_MU_0)) & 0x00000007 ) >> 0)
+#define GET_RG_CE_DLY_SEL (((REG32(ADR_RX_11B_CE_MU_0)) & 0x003f0000 ) >> 16)
+#define GET_RG_CE_MU_T8 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000007 ) >> 0)
+#define GET_RG_CE_MU_T7 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000070 ) >> 4)
+#define GET_RG_CE_MU_T6 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00000700 ) >> 8)
+#define GET_RG_CE_MU_T5 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00007000 ) >> 12)
+#define GET_RG_CE_MU_T4 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00070000 ) >> 16)
+#define GET_RG_CE_MU_T3 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x00700000 ) >> 20)
+#define GET_RG_CE_MU_T2 (((REG32(ADR_RX_11B_CE_MU_1)) & 0x07000000 ) >> 24)
+#define GET_RG_EQ_MU_FB_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x0000000f ) >> 0)
+#define GET_RG_EQ_MU_FF_T2 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_MU_FB_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_EQ_MU_FF_T1 (((REG32(ADR_RX_11B_EQ_MU_0)) & 0x00f00000 ) >> 20)
+#define GET_RG_EQ_MU_FB_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x0000000f ) >> 0)
+#define GET_RG_EQ_MU_FF_T4 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_MU_FB_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x000f0000 ) >> 16)
+#define GET_RG_EQ_MU_FF_T3 (((REG32(ADR_RX_11B_EQ_MU_1)) & 0x00f00000 ) >> 20)
+#define GET_RG_EQ_KI_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00000700 ) >> 8)
+#define GET_RG_EQ_KP_T2 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00007000 ) >> 12)
+#define GET_RG_EQ_KI_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00070000 ) >> 16)
+#define GET_RG_EQ_KP_T1 (((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0x00700000 ) >> 20)
+#define GET_RG_TR_LPF_RATE (((REG32(ADR_RX_11B_LPF_RATE)) & 0x003fffff ) >> 0)
+#define GET_RG_CE_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x0000007f ) >> 0)
+#define GET_RG_CE_CH_MAIN_SET (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00000080 ) >> 7)
+#define GET_RG_TC_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x00007f00 ) >> 8)
+#define GET_RG_CR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x007f0000 ) >> 16)
+#define GET_RG_TR_BIT_CNT_LMT (((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x7f000000 ) >> 24)
+#define GET_RG_EQ_MAIN_TAP_MAN (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x00000001 ) >> 0)
+#define GET_RG_EQ_MAIN_TAP_COEF (((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0x07ff0000 ) >> 16)
+#define GET_RG_PWRON_DLY_TH_11B (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x000000ff ) >> 0)
+#define GET_RG_SFD_BIT_CNT_LMT (((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0x00ff0000 ) >> 16)
+#define GET_RG_CCA_PWR_TH_RX (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x00007fff ) >> 0)
+#define GET_RG_CCA_PWR_CNT_TH (((REG32(ADR_RX_11B_CCA_CONTROL)) & 0x001f0000 ) >> 16)
+#define GET_B_FREQ_OS (((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0x000007ff ) >> 0)
+#define GET_B_SNR (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x0000007f ) >> 0)
+#define GET_B_RCPI (((REG32(ADR_RX_11B_SNR_RSSI)) & 0x007f0000 ) >> 16)
+#define GET_CRC_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff ) >> 0)
+#define GET_SFD_CNT (((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000 ) >> 16)
+#define GET_B_PACKET_ERR_CNT (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_PACKET_ERR (((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0x00010000 ) >> 16)
+#define GET_B_PACKET_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
+#define GET_B_CCA_CNT (((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
+#define GET_B_LENGTH_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff ) >> 0)
+#define GET_SFD_FIELD (((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000 ) >> 16)
+#define GET_SIGNAL_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x000000ff ) >> 0)
+#define GET_B_SERVICE_FIELD (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x0000ff00 ) >> 8)
+#define GET_CRC_CORRECT (((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0x00010000 ) >> 16)
+#define GET_DEBUG_SEL (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x0000000f ) >> 0)
+#define GET_RG_PACKET_STAT_EN_11B (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00100000 ) >> 20)
+#define GET_RG_BIT_REVERSE (((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0x00200000 ) >> 21)
+#define GET_RX_PHY_11B_SOFT_RST_N (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000001 ) >> 0)
+#define GET_RG_CE_BYPASS_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x000000f0 ) >> 4)
+#define GET_RG_EQ_BYPASS_FBW_TAP (((REG32(ADR_RX_11B_SOFT_RST)) & 0x00000f00 ) >> 8)
+#define GET_RG_BB_11GN_RISE_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x000000ff ) >> 0)
+#define GET_RG_BB_11GN_FALL_TIME (((REG32(ADR_TX_11GN_RAMP)) & 0x0000ff00 ) >> 8)
+#define GET_RG_HTCARR52_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x000003ff ) >> 0)
+#define GET_RG_HTCARR56_FFT_SCALE (((REG32(ADR_TX_11GN_PLCP)) & 0x003ff000 ) >> 12)
+#define GET_RG_PACKET_STAT_EN (((REG32(ADR_TX_11GN_PLCP)) & 0x00800000 ) >> 23)
+#define GET_RG_SMB_DEF (((REG32(ADR_TX_11GN_PLCP)) & 0x7f000000 ) >> 24)
+#define GET_RG_CONTINUOUS_DATA_11GN (((REG32(ADR_TX_11GN_PLCP)) & 0x80000000 ) >> 31)
+#define GET_RO_TX_CNT_R (((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0xffffffff ) >> 0)
+#define GET_RO_PACKET_ERR_CNT (((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_RG_POS_DES_11GN_L_EXT (((REG32(ADR_RX_11GN_DES_DLY)) & 0x0000000f ) >> 0)
+#define GET_RG_PRE_DES_11GN_DLY (((REG32(ADR_RX_11GN_DES_DLY)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_KI_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_KP_G_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_CNT_T1 (((REG32(ADR_RX_11GN_TR_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TR_LPF_KI_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x000f0000 ) >> 16)
+#define GET_RG_TR_LPF_KP_G_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0x00f00000 ) >> 20)
+#define GET_RG_TR_CNT_T0 (((REG32(ADR_RX_11GN_TR_0)) & 0xff000000 ) >> 24)
+#define GET_RG_TR_LPF_KI_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_KP_G_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_CNT_T2 (((REG32(ADR_RX_11GN_TR_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TR_LPF_KI_G (((REG32(ADR_RX_11GN_TR_2)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_KP_G (((REG32(ADR_RX_11GN_TR_2)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_RATE_G (((REG32(ADR_RX_11GN_TR_2)) & 0x3fffff00 ) >> 8)
+#define GET_RG_CR_LPF_KI_G (((REG32(ADR_RX_11GN_CCA_0)) & 0x00000007 ) >> 0)
+#define GET_RG_SYM_BOUND_CNT (((REG32(ADR_RX_11GN_CCA_0)) & 0x00007f00 ) >> 8)
+#define GET_RG_XSCOR32_RATIO (((REG32(ADR_RX_11GN_CCA_0)) & 0x007f0000 ) >> 16)
+#define GET_RG_ATCOR64_CNT_LMT (((REG32(ADR_RX_11GN_CCA_0)) & 0x7f000000 ) >> 24)
+#define GET_RG_ATCOR16_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_1)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_1)) & 0x007f0000 ) >> 16)
+#define GET_RG_ATCOR16_RATIO_SB (((REG32(ADR_RX_11GN_CCA_1)) & 0x7f000000 ) >> 24)
+#define GET_RG_XSCOR64_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_2)) & 0x007f0000 ) >> 16)
+#define GET_RG_XSCOR64_CNT_LMT1 (((REG32(ADR_RX_11GN_CCA_2)) & 0x7f000000 ) >> 24)
+#define GET_RG_RX_FFT_SCALE (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x000003ff ) >> 0)
+#define GET_RG_VITERBI_AB_SWAP (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x00010000 ) >> 16)
+#define GET_RG_ATCOR16_CNT_TH (((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0x0f000000 ) >> 24)
+#define GET_RG_NORMSQUARE_LOW_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_LOW_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_LOW_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_LOW_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_LOW_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_3 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_SNR_2 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_SNR_1 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_SNR_0 (((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_7 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x000000ff ) >> 0)
+#define GET_RG_NORMSQUARE_SNR_6 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x0000ff00 ) >> 8)
+#define GET_RG_NORMSQUARE_SNR_5 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ff0000 ) >> 16)
+#define GET_RG_NORMSQUARE_SNR_4 (((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff000000 ) >> 24)
+#define GET_RG_NORMSQUARE_SNR_8 (((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0xff000000 ) >> 24)
+#define GET_RG_SNR_TH_64QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x0000007f ) >> 0)
+#define GET_RG_SNR_TH_16QAM (((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_CNT_PLUS_LMT2 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x0000007f ) >> 0)
+#define GET_RG_ATCOR16_CNT_PLUS_LMT1 (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00007f00 ) >> 8)
+#define GET_RG_SYM_BOUND_METHOD (((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0x00030000 ) >> 16)
+#define GET_RG_PWRON_DLY_TH_11GN (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x000000ff ) >> 0)
+#define GET_RG_SB_START_CNT (((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0x00007f00 ) >> 8)
+#define GET_RG_POW16_CNT_TH (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x000000f0 ) >> 4)
+#define GET_RG_POW16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x00000700 ) >> 8)
+#define GET_RG_POW16_TH_L (((REG32(ADR_RX_11GN_CCA_PWR)) & 0x7f000000 ) >> 24)
+#define GET_RG_XSCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00000007 ) >> 0)
+#define GET_RG_XSCOR16_RATIO (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00007f00 ) >> 8)
+#define GET_RG_ATCOR16_SHORT_CNT_LMT (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x00070000 ) >> 16)
+#define GET_RG_ATCOR16_RATIO_CCD (((REG32(ADR_RX_11GN_CCA_CNT)) & 0x7f000000 ) >> 24)
+#define GET_RG_ATCOR64_ACC_LMT (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x0000007f ) >> 0)
+#define GET_RG_ATCOR16_SHORT_CNT_LMT2 (((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0x00070000 ) >> 16)
+#define GET_RG_VITERBI_TB_BITS (((REG32(ADR_RX_11GN_VTB_TB)) & 0xff000000 ) >> 24)
+#define GET_RG_CR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x000000ff ) >> 0)
+#define GET_RG_TR_CNT_UPDATE (((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0x00ff0000 ) >> 16)
+#define GET_RG_BYPASS_CPE_MA (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000010 ) >> 4)
+#define GET_RG_PILOT_BNDRY_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00000700 ) >> 8)
+#define GET_RG_EQ_SHORT_GI_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00007000 ) >> 12)
+#define GET_RG_FFT_WDW_SHORT_SHIFT (((REG32(ADR_RX_11GN_SHORT_GI)) & 0x00070000 ) >> 16)
+#define GET_RG_CHSMTH_COEF (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00030000 ) >> 16)
+#define GET_RG_CHSMTH_EN (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x00040000 ) >> 18)
+#define GET_RG_CHEST_DD_FACTOR (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x07000000 ) >> 24)
+#define GET_RG_CH_UPDATE (((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x80000000 ) >> 31)
+#define GET_RG_FMT_DET_MM_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x000000ff ) >> 0)
+#define GET_RG_FMT_DET_GF_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_DO_NOT_CHECK_L_RATE (((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0x02000000 ) >> 25)
+#define GET_RG_FMT_DET_LENGTH_TH (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff ) >> 0)
+#define GET_RG_L_LENGTH_MAX (((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000 ) >> 16)
+#define GET_RG_TX_TIME_EXT (((REG32(ADR_RX_11GN_TX_TIME)) & 0x000000ff ) >> 0)
+#define GET_RG_MAC_DES_SPACE (((REG32(ADR_RX_11GN_TX_TIME)) & 0x00f00000 ) >> 20)
+#define GET_RG_TR_LPF_STBC_GF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000000f ) >> 0)
+#define GET_RG_TR_LPF_STBC_GF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x000000f0 ) >> 4)
+#define GET_RG_TR_LPF_STBC_MF_KI_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x00000f00 ) >> 8)
+#define GET_RG_TR_LPF_STBC_MF_KP_G (((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0x0000f000 ) >> 12)
+#define GET_RG_MODE_REG_IN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x0001ffff ) >> 0)
+#define GET_RG_PARALLEL_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x00100000 ) >> 20)
+#define GET_RG_MBRUN_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x01000000 ) >> 24)
+#define GET_RG_SHIFT_DR_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x10000000 ) >> 28)
+#define GET_RG_MODE_REG_SI_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x20000000 ) >> 29)
+#define GET_RG_SIMULATION_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x40000000 ) >> 30)
+#define GET_RG_DBIST_MODE_80 (((REG32(ADR_RX_11GN_BIST_0)) & 0x80000000 ) >> 31)
+#define GET_RG_MODE_REG_IN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x0000ffff ) >> 0)
+#define GET_RG_PARALLEL_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x00100000 ) >> 20)
+#define GET_RG_MBRUN_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x01000000 ) >> 24)
+#define GET_RG_SHIFT_DR_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x10000000 ) >> 28)
+#define GET_RG_MODE_REG_SI_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x20000000 ) >> 29)
+#define GET_RG_SIMULATION_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x40000000 ) >> 30)
+#define GET_RG_DBIST_MODE_64 (((REG32(ADR_RX_11GN_BIST_1)) & 0x80000000 ) >> 31)
+#define GET_RO_MODE_REG_OUT_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x0001ffff ) >> 0)
+#define GET_RO_MODE_REG_SO_80 (((REG32(ADR_RX_11GN_BIST_2)) & 0x01000000 ) >> 24)
+#define GET_RO_MONITOR_BUS_80 (((REG32(ADR_RX_11GN_BIST_3)) & 0x003fffff ) >> 0)
+#define GET_RO_MODE_REG_OUT_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x0000ffff ) >> 0)
+#define GET_RO_MODE_REG_SO_64 (((REG32(ADR_RX_11GN_BIST_4)) & 0x01000000 ) >> 24)
+#define GET_RO_MONITOR_BUS_64 (((REG32(ADR_RX_11GN_BIST_5)) & 0x0007ffff ) >> 0)
+#define GET_RO_SPECTRUM_DATA (((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0xffffffff ) >> 0)
+#define GET_GN_SNR (((REG32(ADR_RX_11GN_READ_0)) & 0x0000007f ) >> 0)
+#define GET_GN_NOISE_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x00007f00 ) >> 8)
+#define GET_GN_RCPI (((REG32(ADR_RX_11GN_READ_0)) & 0x007f0000 ) >> 16)
+#define GET_GN_SIGNAL_PWR (((REG32(ADR_RX_11GN_READ_0)) & 0x7f000000 ) >> 24)
+#define GET_RO_FREQ_OS_LTS (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x00007fff ) >> 0)
+#define GET_CSTATE (((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0x000f0000 ) >> 16)
+#define GET_SIGNAL_FIELD0 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0x00ffffff ) >> 0)
+#define GET_SIGNAL_FIELD1 (((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0x00ffffff ) >> 0)
+#define GET_GN_PACKET_ERR_CNT (((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0x0000ffff ) >> 0)
+#define GET_GN_PACKET_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff ) >> 0)
+#define GET_GN_CCA_CNT (((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000 ) >> 16)
+#define GET_GN_LENGTH_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff ) >> 0)
+#define GET_GN_SERVICE_FIELD (((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000 ) >> 16)
+#define GET_RO_HT_MCS_40M (((REG32(ADR_RX_11GN_RATE)) & 0x0000007f ) >> 0)
+#define GET_RO_L_RATE_40M (((REG32(ADR_RX_11GN_RATE)) & 0x00003f00 ) >> 8)
+#define GET_RG_DAGC_CNT_TH (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00000003 ) >> 0)
+#define GET_RG_PACKET_STAT_EN_11GN (((REG32(ADR_RX_11GN_STAT_EN)) & 0x00100000 ) >> 20)
+#define GET_RX_PHY_11GN_SOFT_RST_N (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000001 ) >> 0)
+#define GET_RG_RIFS_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000002 ) >> 1)
+#define GET_RG_STBC_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000004 ) >> 2)
+#define GET_RG_COR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000008 ) >> 3)
+#define GET_RG_INI_PHASE (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000030 ) >> 4)
+#define GET_RG_HT_LTF_SEL_EQ (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000040 ) >> 6)
+#define GET_RG_HT_LTF_SEL_PILOT (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000080 ) >> 7)
+#define GET_RG_CCA_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000200 ) >> 9)
+#define GET_RG_CCA_XSCOR_PWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000400 ) >> 10)
+#define GET_RG_CCA_XSCOR_AVGPWR_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00000800 ) >> 11)
+#define GET_RG_DEBUG_SEL (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x0000f000 ) >> 12)
+#define GET_RG_POST_CLK_EN (((REG32(ADR_RX_11GN_SOFT_RST)) & 0x00010000 ) >> 16)
+#define GET_IQCAL_RF_TX_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000001 ) >> 0)
+#define GET_IQCAL_RF_TX_PA_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000002 ) >> 1)
+#define GET_IQCAL_RF_TX_DAC_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00000004 ) >> 2)
+#define GET_IQCAL_RF_RX_AGC (((REG32(ADR_RF_CONTROL_0)) & 0x00000008 ) >> 3)
+#define GET_IQCAL_RF_PGAG (((REG32(ADR_RF_CONTROL_0)) & 0x00000f00 ) >> 8)
+#define GET_IQCAL_RF_RFG (((REG32(ADR_RF_CONTROL_0)) & 0x00003000 ) >> 12)
+#define GET_RG_TONEGEN_FREQ (((REG32(ADR_RF_CONTROL_0)) & 0x007f0000 ) >> 16)
+#define GET_RG_TONEGEN_EN (((REG32(ADR_RF_CONTROL_0)) & 0x00800000 ) >> 23)
+#define GET_RG_TONEGEN_INIT_PH (((REG32(ADR_RF_CONTROL_0)) & 0x7f000000 ) >> 24)
+#define GET_RG_TONEGEN2_FREQ (((REG32(ADR_RF_CONTROL_1)) & 0x0000007f ) >> 0)
+#define GET_RG_TONEGEN2_EN (((REG32(ADR_RF_CONTROL_1)) & 0x00000080 ) >> 7)
+#define GET_RG_TONEGEN2_SCALE (((REG32(ADR_RF_CONTROL_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TXIQ_CLP_THD_I (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x000003ff ) >> 0)
+#define GET_RG_TXIQ_CLP_THD_Q (((REG32(ADR_TX_IQ_CONTROL_0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_TX_I_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x000000ff ) >> 0)
+#define GET_RG_TX_Q_SCALE (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x0000ff00 ) >> 8)
+#define GET_RG_TX_IQ_SWP (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00010000 ) >> 16)
+#define GET_RG_TX_SGN_OUT (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x00020000 ) >> 17)
+#define GET_RG_TXIQ_EMU_IDX (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x003c0000 ) >> 18)
+#define GET_RG_TX_IQ_SRC (((REG32(ADR_TX_IQ_CONTROL_1)) & 0x03000000 ) >> 24)
+#define GET_RG_TX_I_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x000003ff ) >> 0)
+#define GET_RG_TX_Q_DC (((REG32(ADR_TX_IQ_CONTROL_2)) & 0x03ff0000 ) >> 16)
+#define GET_RG_TX_IQ_THETA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
+#define GET_RG_TX_IQ_ALPHA (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
+#define GET_RG_TXIQ_NOSHRINK (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
+#define GET_RG_TX_I_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ff0000 ) >> 16)
+#define GET_RG_TX_Q_OFFSET (((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff000000 ) >> 24)
+#define GET_RG_RX_IQ_THETA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x0000001f ) >> 0)
+#define GET_RG_RX_IQ_ALPHA (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00001f00 ) >> 8)
+#define GET_RG_RXIQ_NOSHRINK (((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0x00002000 ) >> 13)
+#define GET_RG_MA_DPTH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x0000000f ) >> 0)
+#define GET_RG_INTG_PH (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x000003f0 ) >> 4)
+#define GET_RG_INTG_PRD (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00001c00 ) >> 10)
+#define GET_RG_INTG_MU (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00006000 ) >> 13)
+#define GET_RG_IQCAL_SPRM_SELQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00010000 ) >> 16)
+#define GET_RG_IQCAL_SPRM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00020000 ) >> 17)
+#define GET_RG_IQCAL_SPRM_FREQ (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IQCAL_IQCOL_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x01000000 ) >> 24)
+#define GET_RG_IQCAL_ALPHA_ESTM_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x02000000 ) >> 25)
+#define GET_RG_IQCAL_DC_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x04000000 ) >> 26)
+#define GET_RG_PHEST_STBY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x08000000 ) >> 27)
+#define GET_RG_PHEST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x10000000 ) >> 28)
+#define GET_RG_GP_DIV_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x20000000 ) >> 29)
+#define GET_RG_DPD_GAIN_EST_EN (((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0x40000000 ) >> 30)
+#define GET_RG_IQCAL_MULT_OP0 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x000003ff ) >> 0)
+#define GET_RG_IQCAL_MULT_OP1 (((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0x03ff0000 ) >> 16)
+#define GET_RO_IQCAL_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x000fffff ) >> 0)
+#define GET_RO_IQCAL_SPRM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00100000 ) >> 20)
+#define GET_RO_IQCAL_IQCOL_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00200000 ) >> 21)
+#define GET_RO_IQCAL_ALPHA_ESTM_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00400000 ) >> 22)
+#define GET_RO_IQCAL_DC_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x00800000 ) >> 23)
+#define GET_RO_IQCAL_MULT_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x01000000 ) >> 24)
+#define GET_RO_FFT_ENRG_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x02000000 ) >> 25)
+#define GET_RO_PHEST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x04000000 ) >> 26)
+#define GET_RO_GP_DIV_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x08000000 ) >> 27)
+#define GET_RO_GAIN_EST_RDY (((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0x10000000 ) >> 28)
+#define GET_RO_AMP_O (((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0x000001ff ) >> 0)
+#define GET_RG_RX_I_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x000000ff ) >> 0)
+#define GET_RG_RX_Q_SCALE (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x0000ff00 ) >> 8)
+#define GET_RG_RX_I_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ff0000 ) >> 16)
+#define GET_RG_RX_Q_OFFSET (((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff000000 ) >> 24)
+#define GET_RG_RX_IQ_SWP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000001 ) >> 0)
+#define GET_RG_RX_SGN_IN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000002 ) >> 1)
+#define GET_RG_RX_IQ_SRC (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x0000000c ) >> 2)
+#define GET_RG_ACI_GAIN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00000ff0 ) >> 4)
+#define GET_RG_FFT_EN (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00001000 ) >> 12)
+#define GET_RG_FFT_MOD (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00002000 ) >> 13)
+#define GET_RG_FFT_SCALE (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x00ffc000 ) >> 14)
+#define GET_RG_FFT_ENRG_FREQ (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x3f000000 ) >> 24)
+#define GET_RG_FPGA_80M_PH_UP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x40000000 ) >> 30)
+#define GET_RG_FPGA_80M_PH_STP (((REG32(ADR_RF_IQ_CONTROL_1)) & 0x80000000 ) >> 31)
+#define GET_RG_ADC2LA_SEL (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000001 ) >> 0)
+#define GET_RG_ADC2LA_CLKPH (((REG32(ADR_RF_IQ_CONTROL_2)) & 0x00000002 ) >> 1)
+#define GET_RG_RXIQ_EMU_IDX (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x0000000f ) >> 0)
+#define GET_RG_IQCAL_BP_ACI (((REG32(ADR_RF_IQ_CONTROL_3)) & 0x00000010 ) >> 4)
+#define GET_RG_DPD_AM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000001 ) >> 0)
+#define GET_RG_DPD_PM_EN (((REG32(ADR_DPD_CONTROL)) & 0x00000002 ) >> 1)
+#define GET_RG_DPD_PM_AMSEL (((REG32(ADR_DPD_CONTROL)) & 0x00000004 ) >> 2)
+#define GET_RG_DPD_020_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_040_GAIN (((REG32(ADR_DPD_GAIN_TABLE_0)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_060_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_080_GAIN (((REG32(ADR_DPD_GAIN_TABLE_1)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_0C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_2)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_0E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_3)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_0F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_100_GAIN (((REG32(ADR_DPD_GAIN_TABLE_4)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_110_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_120_GAIN (((REG32(ADR_DPD_GAIN_TABLE_5)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_130_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_140_GAIN (((REG32(ADR_DPD_GAIN_TABLE_6)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_150_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_160_GAIN (((REG32(ADR_DPD_GAIN_TABLE_7)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_170_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_180_GAIN (((REG32(ADR_DPD_GAIN_TABLE_8)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_190_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1A0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_9)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1B0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1C0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_A)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1D0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_1E0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_B)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_1F0_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_200_GAIN (((REG32(ADR_DPD_GAIN_TABLE_C)) & 0x03ff0000 ) >> 16)
+#define GET_RG_DPD_020_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_040_PH (((REG32(ADR_DPD_PH_TABLE_0)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_060_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_080_PH (((REG32(ADR_DPD_PH_TABLE_1)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0A0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_0C0_PH (((REG32(ADR_DPD_PH_TABLE_2)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0D0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_0E0_PH (((REG32(ADR_DPD_PH_TABLE_3)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_0F0_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_100_PH (((REG32(ADR_DPD_PH_TABLE_4)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_110_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_120_PH (((REG32(ADR_DPD_PH_TABLE_5)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_130_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_140_PH (((REG32(ADR_DPD_PH_TABLE_6)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_150_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_160_PH (((REG32(ADR_DPD_PH_TABLE_7)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_170_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_180_PH (((REG32(ADR_DPD_PH_TABLE_8)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_190_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1A0_PH (((REG32(ADR_DPD_PH_TABLE_9)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1B0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1C0_PH (((REG32(ADR_DPD_PH_TABLE_A)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1D0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_1E0_PH (((REG32(ADR_DPD_PH_TABLE_B)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_1F0_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x00001fff ) >> 0)
+#define GET_RG_DPD_200_PH (((REG32(ADR_DPD_PH_TABLE_C)) & 0x1fff0000 ) >> 16)
+#define GET_RG_DPD_GAIN_EST_Y0 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x000001ff ) >> 0)
+#define GET_RG_DPD_GAIN_EST_Y1 (((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0x01ff0000 ) >> 16)
+#define GET_RG_DPD_LOOP_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0x000003ff ) >> 0)
+#define GET_RG_DPD_GAIN_EST_X0 (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x000001ff ) >> 0)
+#define GET_RO_DPD_GAIN (((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0x03ff0000 ) >> 16)
+#define GET_TX_SCALE_11B (((REG32(ADR_TX_GAIN_FACTOR)) & 0x000000ff ) >> 0)
+#define GET_TX_SCALE_11B_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0x0000ff00 ) >> 8)
+#define GET_TX_SCALE_11G (((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ff0000 ) >> 16)
+#define GET_TX_SCALE_11G_P0D5 (((REG32(ADR_TX_GAIN_FACTOR)) & 0xff000000 ) >> 24)
+#define GET_RG_EN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_TX_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_TX_PA_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_TX_DAC_EN (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_RX_AGC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_RX_GAIN_MANUAL (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_RFG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_PGAG (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00000f00 ) >> 8)
+#define GET_RG_MODE (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00003000 ) >> 12)
+#define GET_RG_EN_TX_TRSW (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_EN_SX (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_EN_RX_LNA (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_EN_RX_MIXER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_EN_RX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_EN_RX_LOBUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_EN_RX_TZ (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_EN_RX_FILTER (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_EN_RX_HPF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_EN_RX_RSSI (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x00800000 ) >> 23)
+#define GET_RG_EN_ADC (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x01000000 ) >> 24)
+#define GET_RG_EN_TX_MOD (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x02000000 ) >> 25)
+#define GET_RG_EN_TX_DIV2 (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_EN_TX_DIV2_BUF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_EN_TX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x10000000 ) >> 28)
+#define GET_RG_EN_RX_LOBF (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x20000000 ) >> 29)
+#define GET_RG_SEL_DPLL_CLK (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_EN_CLK_960MBY13_UART (((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_EN_TX_DPD (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_TX_TSSI (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_RX_IQCAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_TX_DAC_CAL (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_EN_TX_SELF_MIXER (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_TX_DAC_OUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_EN_LDO_RX_FE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_LDO_ABB (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7)
+#define GET_RG_EN_LDO_AFE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_EN_SX_CHPLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_EN_SX_LOBFLDO (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_EN_IREF_RX (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_TX_DAC_VOUT (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_SX_LCK_BIN (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_RTC_CAL_MODE (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00010000 ) >> 16)
+#define GET_RG_EN_IQPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00020000 ) >> 17)
+#define GET_RG_EN_TESTPAD_IOSW (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18)
+#define GET_RG_EN_TRXBF_BYPASS (((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19)
+#define GET_RG_LDO_LEVEL_RX_FE (((REG32(ADR_LDO_REGISTER)) & 0x00000007 ) >> 0)
+#define GET_RG_LDO_LEVEL_ABB (((REG32(ADR_LDO_REGISTER)) & 0x00000038 ) >> 3)
+#define GET_RG_LDO_LEVEL_AFE (((REG32(ADR_LDO_REGISTER)) & 0x000001c0 ) >> 6)
+#define GET_RG_SX_LDO_CHP_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00000e00 ) >> 9)
+#define GET_RG_SX_LDO_LOBF_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00007000 ) >> 12)
+#define GET_RG_SX_LDO_XOSC_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_RG_DP_LDO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x00e00000 ) >> 21)
+#define GET_RG_TX_LDO_TX_LEVEL (((REG32(ADR_LDO_REGISTER)) & 0x07000000 ) >> 24)
+#define GET_RG_EN_RX_PADSW (((REG32(ADR_ABB_REGISTER_1)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_RX_TESTNODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000002 ) >> 1)
+#define GET_RG_RX_ABBCFIX (((REG32(ADR_ABB_REGISTER_1)) & 0x00000004 ) >> 2)
+#define GET_RG_RX_ABBCTUNE (((REG32(ADR_ABB_REGISTER_1)) & 0x000001f8 ) >> 3)
+#define GET_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000200 ) >> 9)
+#define GET_RG_RX_ABB_N_MODE (((REG32(ADR_ABB_REGISTER_1)) & 0x00000400 ) >> 10)
+#define GET_RG_RX_EN_LOOPA (((REG32(ADR_ABB_REGISTER_1)) & 0x00000800 ) >> 11)
+#define GET_RG_RX_FILTERI1ST (((REG32(ADR_ABB_REGISTER_1)) & 0x00003000 ) >> 12)
+#define GET_RG_RX_FILTERI2ND (((REG32(ADR_ABB_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_FILTERI3RD (((REG32(ADR_ABB_REGISTER_1)) & 0x00030000 ) >> 16)
+#define GET_RG_RX_FILTERI_COURSE (((REG32(ADR_ABB_REGISTER_1)) & 0x000c0000 ) >> 18)
+#define GET_RG_RX_FILTERVCM (((REG32(ADR_ABB_REGISTER_1)) & 0x00300000 ) >> 20)
+#define GET_RG_RX_HPF3M (((REG32(ADR_ABB_REGISTER_1)) & 0x00400000 ) >> 22)
+#define GET_RG_RX_HPF300K (((REG32(ADR_ABB_REGISTER_1)) & 0x00800000 ) >> 23)
+#define GET_RG_RX_HPFI (((REG32(ADR_ABB_REGISTER_1)) & 0x03000000 ) >> 24)
+#define GET_RG_RX_HPF_FINALCORNER (((REG32(ADR_ABB_REGISTER_1)) & 0x0c000000 ) >> 26)
+#define GET_RG_RX_HPF_SETTLE1_C (((REG32(ADR_ABB_REGISTER_1)) & 0x30000000 ) >> 28)
+#define GET_RG_RX_HPF_SETTLE1_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_HPF_SETTLE2_C (((REG32(ADR_ABB_REGISTER_2)) & 0x0000000c ) >> 2)
+#define GET_RG_RX_HPF_SETTLE2_R (((REG32(ADR_ABB_REGISTER_2)) & 0x00000030 ) >> 4)
+#define GET_RG_RX_HPF_VCMCON2 (((REG32(ADR_ABB_REGISTER_2)) & 0x000000c0 ) >> 6)
+#define GET_RG_RX_HPF_VCMCON (((REG32(ADR_ABB_REGISTER_2)) & 0x00000300 ) >> 8)
+#define GET_RG_RX_OUTVCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00000c00 ) >> 10)
+#define GET_RG_RX_TZI (((REG32(ADR_ABB_REGISTER_2)) & 0x00003000 ) >> 12)
+#define GET_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_ABB_REGISTER_2)) & 0x00004000 ) >> 14)
+#define GET_RG_RX_TZ_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00018000 ) >> 15)
+#define GET_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_ABB_REGISTER_2)) & 0x000e0000 ) >> 17)
+#define GET_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_ABB_REGISTER_2)) & 0x00100000 ) >> 20)
+#define GET_RG_RX_ADCRSSI_VCM (((REG32(ADR_ABB_REGISTER_2)) & 0x00600000 ) >> 21)
+#define GET_RG_RX_REC_LPFCORNER (((REG32(ADR_ABB_REGISTER_2)) & 0x01800000 ) >> 23)
+#define GET_RG_RSSI_CLOCK_GATING (((REG32(ADR_ABB_REGISTER_2)) & 0x02000000 ) >> 25)
+#define GET_RG_TXPGA_CAPSW (((REG32(ADR_TX_FE_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TXPGA_MAIN (((REG32(ADR_TX_FE_REGISTER)) & 0x000000fc ) >> 2)
+#define GET_RG_TXPGA_STEER (((REG32(ADR_TX_FE_REGISTER)) & 0x00003f00 ) >> 8)
+#define GET_RG_TXMOD_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TXLPF_GMCELL (((REG32(ADR_TX_FE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_PACELL_EN (((REG32(ADR_TX_FE_REGISTER)) & 0x001c0000 ) >> 18)
+#define GET_RG_PABIAS_CTRL (((REG32(ADR_TX_FE_REGISTER)) & 0x01e00000 ) >> 21)
+#define GET_RG_TX_DIV_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x0c000000 ) >> 26)
+#define GET_RG_TX_LOBUF_VSET (((REG32(ADR_TX_FE_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_RX_SQDC (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000007 ) >> 0)
+#define GET_RG_RX_DIV2_CORE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000018 ) >> 3)
+#define GET_RG_RX_LOBUF (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000060 ) >> 5)
+#define GET_RG_TX_DPDGM_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00000780 ) >> 7)
+#define GET_RG_TX_DPD_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00007800 ) >> 11)
+#define GET_RG_TX_TSSI_BIAS (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00038000 ) >> 15)
+#define GET_RG_TX_TSSI_DIV (((REG32(ADR_RX_FE_REGISTER_1)) & 0x001c0000 ) >> 18)
+#define GET_RG_TX_TSSI_TESTMODE (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00200000 ) >> 21)
+#define GET_RG_TX_TSSI_TEST (((REG32(ADR_RX_FE_REGISTER_1)) & 0x00c00000 ) >> 22)
+#define GET_RG_PACASCODE_CTRL (((REG32(ADR_RX_FE_REGISTER_1)) & 0x07000000 ) >> 24)
+#define GET_RG_RX_HG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_HG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_HG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_HG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_HG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_HG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_MG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_MG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_MG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_MG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_MG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_MG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_LG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_LG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_LG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_LG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_LG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_LG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0x00070000 ) >> 16)
+#define GET_RG_RX_ULG_LNA_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00000003 ) >> 0)
+#define GET_RG_RX_ULG_LNAHGN_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000003c ) >> 2)
+#define GET_RG_RX_ULG_LNAHGP_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x000003c0 ) >> 6)
+#define GET_RG_RX_ULG_LNALG_BIAS (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00003c00 ) >> 10)
+#define GET_RG_RX_ULG_TZ_GC (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x0000c000 ) >> 14)
+#define GET_RG_RX_ULG_TZ_CAP (((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0x00070000 ) >> 16)
+#define GET_RG_HPF1_FAST_SET_X (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_HPF1_FAST_SET_Y (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_HPF1_FAST_SET_Z (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_HPF_T1A (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_RG_HPF_T1B (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000060 ) >> 5)
+#define GET_RG_HPF_T1C (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000180 ) >> 7)
+#define GET_RG_RX_LNA_TRI_SEL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_RG_RX_LNA_SETTLE (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00001800 ) >> 11)
+#define GET_RG_TXGAIN_PHYCTRL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_TX_GAIN (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x003fc000 ) >> 14)
+#define GET_RG_TXGAIN_MANUAL (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TX_GAIN_OFFSET (((REG32(ADR_RX_TX_FSM_REGISTER)) & 0x07800000 ) >> 23)
+#define GET_RG_ADC_CLKSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_ADC_DIBIAS (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_RG_ADC_DIVR (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_ADC_DVCMI (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_ADC_SAMSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x000003c0 ) >> 6)
+#define GET_RG_ADC_STNBY (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000400 ) >> 10)
+#define GET_RG_ADC_TESTMODE (((REG32(ADR_RX_ADC_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_ADC_TSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x0000f000 ) >> 12)
+#define GET_RG_ADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_DICMP (((REG32(ADR_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_DIOP (((REG32(ADR_RX_ADC_REGISTER)) & 0x00300000 ) >> 20)
+#define GET_RG_SARADC_VRSEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x00c00000 ) >> 22)
+#define GET_RG_EN_SAR_TEST (((REG32(ADR_RX_ADC_REGISTER)) & 0x03000000 ) >> 24)
+#define GET_RG_SARADC_THERMAL (((REG32(ADR_RX_ADC_REGISTER)) & 0x04000000 ) >> 26)
+#define GET_RG_SARADC_TSSI (((REG32(ADR_RX_ADC_REGISTER)) & 0x08000000 ) >> 27)
+#define GET_RG_CLK_SAR_SEL (((REG32(ADR_RX_ADC_REGISTER)) & 0x30000000 ) >> 28)
+#define GET_RG_EN_SARADC (((REG32(ADR_RX_ADC_REGISTER)) & 0x40000000 ) >> 30)
+#define GET_RG_DACI1ST (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000003 ) >> 0)
+#define GET_RG_TX_DACLPF_ICOURSE (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000000c ) >> 2)
+#define GET_RG_TX_DACLPF_IFINE (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000030 ) >> 4)
+#define GET_RG_TX_DACLPF_VCM (((REG32(ADR_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6)
+#define GET_RG_TX_DAC_CKEDGE_SEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_TX_DAC_IBIAS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00000600 ) >> 9)
+#define GET_RG_TX_DAC_OS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00003800 ) >> 11)
+#define GET_RG_TX_DAC_RCAL (((REG32(ADR_TX_DAC_REGISTER)) & 0x0000c000 ) >> 14)
+#define GET_RG_TX_DAC_TSEL (((REG32(ADR_TX_DAC_REGISTER)) & 0x000f0000 ) >> 16)
+#define GET_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_TX_DAC_REGISTER)) & 0x00100000 ) >> 20)
+#define GET_RG_TXLPF_BYPASS (((REG32(ADR_TX_DAC_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_TXLPF_BOOSTI (((REG32(ADR_TX_DAC_REGISTER)) & 0x00400000 ) >> 22)
+#define GET_RG_TX_DAC_IOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x07800000 ) >> 23)
+#define GET_RG_TX_DAC_QOFFSET (((REG32(ADR_TX_DAC_REGISTER)) & 0x78000000 ) >> 27)
+#define GET_RG_EN_SX_R3 (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_EN_SX_CH (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_EN_SX_CHP (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000004 ) >> 2)
+#define GET_RG_EN_SX_DIVCK (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000008 ) >> 3)
+#define GET_RG_EN_SX_VCOBF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000010 ) >> 4)
+#define GET_RG_EN_SX_VCO (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000020 ) >> 5)
+#define GET_RG_EN_SX_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000040 ) >> 6)
+#define GET_RG_EN_SX_DITHER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000100 ) >> 8)
+#define GET_RG_EN_SX_VT_MON (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00000800 ) >> 11)
+#define GET_RG_EN_SX_VT_MON_DG (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00001000 ) >> 12)
+#define GET_RG_EN_SX_DIV (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00002000 ) >> 13)
+#define GET_RG_EN_SX_LPF (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_EN_DPL_MOD (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00008000 ) >> 15)
+#define GET_RG_DPL_MOD_ORDER (((REG32(ADR_SX_ENABLE_REGISTER)) & 0x00030000 ) >> 16)
+#define GET_RG_SX_RFCTRL_F (((REG32(ADR_SYN_REGISTER_1)) & 0x00ffffff ) >> 0)
+#define GET_RG_SX_SEL_CP (((REG32(ADR_SYN_REGISTER_1)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_SEL_CS (((REG32(ADR_SYN_REGISTER_1)) & 0xf0000000 ) >> 28)
+#define GET_RG_SX_RFCTRL_CH (((REG32(ADR_SYN_REGISTER_2)) & 0x000007ff ) >> 0)
+#define GET_RG_SX_SEL_C3 (((REG32(ADR_SYN_REGISTER_2)) & 0x00007800 ) >> 11)
+#define GET_RG_SX_SEL_RS (((REG32(ADR_SYN_REGISTER_2)) & 0x000f8000 ) >> 15)
+#define GET_RG_SX_SEL_R3 (((REG32(ADR_SYN_REGISTER_2)) & 0x01f00000 ) >> 20)
+#define GET_RG_SX_SEL_ICHP (((REG32(ADR_SYN_PFD_CHP)) & 0x0000001f ) >> 0)
+#define GET_RG_SX_SEL_PCHP (((REG32(ADR_SYN_PFD_CHP)) & 0x000003e0 ) >> 5)
+#define GET_RG_SX_SEL_CHP_REGOP (((REG32(ADR_SYN_PFD_CHP)) & 0x00003c00 ) >> 10)
+#define GET_RG_SX_SEL_CHP_UNIOP (((REG32(ADR_SYN_PFD_CHP)) & 0x0003c000 ) >> 14)
+#define GET_RG_SX_CHP_IOST_POL (((REG32(ADR_SYN_PFD_CHP)) & 0x00040000 ) >> 18)
+#define GET_RG_SX_CHP_IOST (((REG32(ADR_SYN_PFD_CHP)) & 0x00380000 ) >> 19)
+#define GET_RG_SX_PFDSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x00400000 ) >> 22)
+#define GET_RG_SX_PFD_SET (((REG32(ADR_SYN_PFD_CHP)) & 0x00800000 ) >> 23)
+#define GET_RG_SX_PFD_SET1 (((REG32(ADR_SYN_PFD_CHP)) & 0x01000000 ) >> 24)
+#define GET_RG_SX_PFD_SET2 (((REG32(ADR_SYN_PFD_CHP)) & 0x02000000 ) >> 25)
+#define GET_RG_SX_VBNCAS_SEL (((REG32(ADR_SYN_PFD_CHP)) & 0x04000000 ) >> 26)
+#define GET_RG_SX_PFD_RST_H (((REG32(ADR_SYN_PFD_CHP)) & 0x08000000 ) >> 27)
+#define GET_RG_SX_PFD_TRUP (((REG32(ADR_SYN_PFD_CHP)) & 0x10000000 ) >> 28)
+#define GET_RG_SX_PFD_TRDN (((REG32(ADR_SYN_PFD_CHP)) & 0x20000000 ) >> 29)
+#define GET_RG_SX_PFD_TRSEL (((REG32(ADR_SYN_PFD_CHP)) & 0x40000000 ) >> 30)
+#define GET_RG_SX_VCOBA_R (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000007 ) >> 0)
+#define GET_RG_SX_VCORSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000000f8 ) >> 3)
+#define GET_RG_SX_VCOCUSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00000f00 ) >> 8)
+#define GET_RG_SX_RXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0000f000 ) >> 12)
+#define GET_RG_SX_TXBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x000f0000 ) >> 16)
+#define GET_RG_SX_VCOBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x00f00000 ) >> 20)
+#define GET_RG_SX_DIVBFSEL (((REG32(ADR_SYN_VCO_LOBF)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_GNDR_SEL (((REG32(ADR_SYN_VCO_LOBF)) & 0xf0000000 ) >> 28)
+#define GET_RG_SX_DITHER_WEIGHT (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000003 ) >> 0)
+#define GET_RG_SX_MOD_ORDER (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000030 ) >> 4)
+#define GET_RG_SX_RST_H_DIV (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000200 ) >> 9)
+#define GET_RG_SX_SDM_EDGE (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00000400 ) >> 10)
+#define GET_RG_SX_XO_GM (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00001800 ) >> 11)
+#define GET_RG_SX_REFBYTWO (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00002000 ) >> 13)
+#define GET_RG_SX_LCKEN (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00080000 ) >> 19)
+#define GET_RG_SX_PREVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x00f00000 ) >> 20)
+#define GET_RG_SX_PSCONTERVDD (((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0x0f000000 ) >> 24)
+#define GET_RG_SX_PH (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00002000 ) >> 13)
+#define GET_RG_SX_PL (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00004000 ) >> 14)
+#define GET_RG_XOSC_CBANK_XO (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00078000 ) >> 15)
+#define GET_RG_XOSC_CBANK_XI (((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0x00780000 ) >> 19)
+#define GET_RG_SX_VT_MON_MODE (((REG32(ADR_SYN_LCK_VT)) & 0x00000001 ) >> 0)
+#define GET_RG_SX_VT_TH_HI (((REG32(ADR_SYN_LCK_VT)) & 0x00000006 ) >> 1)
+#define GET_RG_SX_VT_TH_LO (((REG32(ADR_SYN_LCK_VT)) & 0x00000018 ) >> 3)
+#define GET_RG_SX_VT_SET (((REG32(ADR_SYN_LCK_VT)) & 0x00000020 ) >> 5)
+#define GET_RG_SX_VT_MON_TMR (((REG32(ADR_SYN_LCK_VT)) & 0x00007fc0 ) >> 6)
+#define GET_RG_EN_DP_VT_MON (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_DP_VT_TH_HI (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_RG_DP_VT_TH_LO (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_RG_DP_CK320BY2 (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00004000 ) >> 14)
+#define GET_RG_DP_OD_TEST (((REG32(ADR_DPLL_VCO_REGISTER)) & 0x00200000 ) >> 21)
+#define GET_RG_DP_BBPLL_BP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_DP_BBPLL_ICP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000006 ) >> 1)
+#define GET_RG_DP_BBPLL_IDUAL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000018 ) >> 3)
+#define GET_RG_DP_BBPLL_OD_TEST (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000001e0 ) >> 5)
+#define GET_RG_DP_BBPLL_PD (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_DP_BBPLL_TESTSEL (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00001c00 ) >> 10)
+#define GET_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00006000 ) >> 13)
+#define GET_RG_DP_RP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x00038000 ) >> 15)
+#define GET_RG_DP_RHP (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x000c0000 ) >> 18)
+#define GET_RG_DP_BBPLL_SDM_EDGE (((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x80000000 ) >> 31)
+#define GET_RG_DP_FODIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x0007f000 ) >> 12)
+#define GET_RG_DP_REFDIV (((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0x1fc00000 ) >> 22)
+#define GET_RG_IDACAI_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG15 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG14 (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x00fc0000 ) >> 18)
+#define GET_RG_DP_BBPLL_BS (((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24)
+#define GET_RG_IDACAI_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG13 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG12 (((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG11 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG10 (((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG9 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG8 (((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG7 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG6 (((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG5 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG4 (((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG3 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG2 (((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0x00fc0000 ) >> 18)
+#define GET_RG_IDACAI_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0)
+#define GET_RG_IDACAQ_PGAG1 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00000fc0 ) >> 6)
+#define GET_RG_IDACAI_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x0003f000 ) >> 12)
+#define GET_RG_IDACAQ_PGAG0 (((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0x00fc0000 ) >> 18)
+#define GET_RG_EN_RCAL (((REG32(ADR_RCAL_REGISTER)) & 0x00000001 ) >> 0)
+#define GET_RG_RCAL_SPD (((REG32(ADR_RCAL_REGISTER)) & 0x00000002 ) >> 1)
+#define GET_RG_RCAL_TMR (((REG32(ADR_RCAL_REGISTER)) & 0x000001fc ) >> 2)
+#define GET_RG_RCAL_CODE_CWR (((REG32(ADR_RCAL_REGISTER)) & 0x00000200 ) >> 9)
+#define GET_RG_RCAL_CODE_CWD (((REG32(ADR_RCAL_REGISTER)) & 0x00007c00 ) >> 10)
+#define GET_RG_SX_SUB_SEL_CWR (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00000001 ) >> 0)
+#define GET_RG_SX_SUB_SEL_CWD (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x000000fe ) >> 1)
+#define GET_RG_SX_LCK_BIN_OFFSET (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00078000 ) >> 15)
+#define GET_RG_SX_LCK_BIN_PRECISION (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00080000 ) >> 19)
+#define GET_RG_SX_LOCK_EN_N (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00100000 ) >> 20)
+#define GET_RG_SX_LOCK_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00200000 ) >> 21)
+#define GET_RG_SX_SUB_MANUAL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x00400000 ) >> 22)
+#define GET_RG_SX_SUB_SEL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x3f800000 ) >> 23)
+#define GET_RG_SX_MUX_SEL_VTH_BINL (((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0x40000000 ) >> 30)
+#define GET_RG_TRX_DUMMMY (((REG32(ADR_TRX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
+#define GET_RG_SX_DUMMMY (((REG32(ADR_SX_DUMMY_REGISTER)) & 0xffffffff ) >> 0)
+#define GET_RCAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000001 ) >> 0)
+#define GET_LCK_BIN_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000002 ) >> 1)
+#define GET_VT_MON_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00000004 ) >> 2)
+#define GET_DA_R_CODE_LUT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x000007c0 ) >> 6)
+#define GET_AD_SX_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00001800 ) >> 11)
+#define GET_AD_DP_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00006000 ) >> 13)
+#define GET_RTC_CAL_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00008000 ) >> 15)
+#define GET_RG_SARADC_BIT (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x003f0000 ) >> 16)
+#define GET_SAR_ADC_FSM_RDY (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x00400000 ) >> 22)
+#define GET_AD_CIRCUIT_VERSION (((REG32(ADR_READ_ONLY_FLAGS_1)) & 0x07800000 ) >> 23)
+#define GET_DA_R_CAL_CODE (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x0000001f ) >> 0)
+#define GET_DA_SX_SUB_SEL (((REG32(ADR_READ_ONLY_FLAGS_2)) & 0x00000fe0 ) >> 5)
+#define GET_RG_DPL_RFCTRL_CH (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x000007ff ) >> 0)
+#define GET_RG_RSSIADC_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x00007800 ) >> 11)
+#define GET_RG_RX_ADC_I_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x007f8000 ) >> 15)
+#define GET_RG_RX_ADC_Q_RO_BIT (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x7f800000 ) >> 23)
+#define GET_RG_DPL_RFCTRL_F (((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0x00ffffff ) >> 0)
+#define GET_RG_SX_TARGET_CNT (((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0x00001fff ) >> 0)
+#define GET_RG_RTC_OFFSET (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000000ff ) >> 0)
+#define GET_RG_RTC_CAL_TARGET_COUNT (((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0x000fff00 ) >> 8)
+#define GET_RG_RF_D_REG (((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0x0000ffff ) >> 0)
+#define GET_DIRECT_MODE (((REG32(ADR_MMU_CTRL)) & 0x00000001 ) >> 0)
+#define GET_TAG_INTERLEAVE_MD (((REG32(ADR_MMU_CTRL)) & 0x00000002 ) >> 1)
+#define GET_DIS_DEMAND (((REG32(ADR_MMU_CTRL)) & 0x00000004 ) >> 2)
+#define GET_SAME_ID_ALLOC_MD (((REG32(ADR_MMU_CTRL)) & 0x00000008 ) >> 3)
+#define GET_HS_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000010 ) >> 4)
+#define GET_SRAM_ACCESS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000020 ) >> 5)
+#define GET_NOHIT_RPASS_MD (((REG32(ADR_MMU_CTRL)) & 0x00000040 ) >> 6)
+#define GET_DMN_FLAG_CLR (((REG32(ADR_MMU_CTRL)) & 0x00000080 ) >> 7)
+#define GET_ERR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000100 ) >> 8)
+#define GET_ALR_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000200 ) >> 9)
+#define GET_MCH_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000400 ) >> 10)
+#define GET_TAG_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00000800 ) >> 11)
+#define GET_ABT_SW_RST_N (((REG32(ADR_MMU_CTRL)) & 0x00001000 ) >> 12)
+#define GET_MMU_VER (((REG32(ADR_MMU_CTRL)) & 0x0000e000 ) >> 13)
+#define GET_MMU_SHARE_MCU (((REG32(ADR_MMU_CTRL)) & 0x00ff0000 ) >> 16)
+#define GET_HS_WR (((REG32(ADR_HS_CTRL)) & 0x00000001 ) >> 0)
+#define GET_HS_FLAG (((REG32(ADR_HS_CTRL)) & 0x00000010 ) >> 4)
+#define GET_HS_ID (((REG32(ADR_HS_CTRL)) & 0x00007f00 ) >> 8)
+#define GET_HS_CHANNEL (((REG32(ADR_HS_CTRL)) & 0x000f0000 ) >> 16)
+#define GET_HS_PAGE (((REG32(ADR_HS_CTRL)) & 0x00f00000 ) >> 20)
+#define GET_HS_DATA (((REG32(ADR_HS_CTRL)) & 0xff000000 ) >> 24)
+#define GET_CPU_POR0 (((REG32(ADR_CPU_POR0_7)) & 0x0000000f ) >> 0)
+#define GET_CPU_POR1 (((REG32(ADR_CPU_POR0_7)) & 0x000000f0 ) >> 4)
+#define GET_CPU_POR2 (((REG32(ADR_CPU_POR0_7)) & 0x00000f00 ) >> 8)
+#define GET_CPU_POR3 (((REG32(ADR_CPU_POR0_7)) & 0x0000f000 ) >> 12)
+#define GET_CPU_POR4 (((REG32(ADR_CPU_POR0_7)) & 0x000f0000 ) >> 16)
+#define GET_CPU_POR5 (((REG32(ADR_CPU_POR0_7)) & 0x00f00000 ) >> 20)
+#define GET_CPU_POR6 (((REG32(ADR_CPU_POR0_7)) & 0x0f000000 ) >> 24)
+#define GET_CPU_POR7 (((REG32(ADR_CPU_POR0_7)) & 0xf0000000 ) >> 28)
+#define GET_CPU_POR8 (((REG32(ADR_CPU_POR8_F)) & 0x0000000f ) >> 0)
+#define GET_CPU_POR9 (((REG32(ADR_CPU_POR8_F)) & 0x000000f0 ) >> 4)
+#define GET_CPU_PORA (((REG32(ADR_CPU_POR8_F)) & 0x00000f00 ) >> 8)
+#define GET_CPU_PORB (((REG32(ADR_CPU_POR8_F)) & 0x0000f000 ) >> 12)
+#define GET_CPU_PORC (((REG32(ADR_CPU_POR8_F)) & 0x000f0000 ) >> 16)
+#define GET_CPU_PORD (((REG32(ADR_CPU_POR8_F)) & 0x00f00000 ) >> 20)
+#define GET_CPU_PORE (((REG32(ADR_CPU_POR8_F)) & 0x0f000000 ) >> 24)
+#define GET_CPU_PORF (((REG32(ADR_CPU_POR8_F)) & 0xf0000000 ) >> 28)
+#define GET_ACC_WR_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x0000003f ) >> 0)
+#define GET_ACC_RD_LEN (((REG32(ADR_REG_LEN_CTRL)) & 0x00003f00 ) >> 8)
+#define GET_REQ_NACK_CLR (((REG32(ADR_REG_LEN_CTRL)) & 0x00008000 ) >> 15)
+#define GET_NACK_FLAG_BUS (((REG32(ADR_REG_LEN_CTRL)) & 0xffff0000 ) >> 16)
+#define GET_DMN_R_PASS (((REG32(ADR_DMN_READ_BYPASS)) & 0x0000ffff ) >> 0)
+#define GET_PARA_ALC_RLS (((REG32(ADR_DMN_READ_BYPASS)) & 0x00010000 ) >> 16)
+#define GET_REQ_PORNS_CHGEN (((REG32(ADR_DMN_READ_BYPASS)) & 0x01000000 ) >> 24)
+#define GET_ALC_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x0000007f ) >> 0)
+#define GET_ALC_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x00008000 ) >> 15)
+#define GET_RLS_ABT_ID (((REG32(ADR_ALC_RLS_ABORT)) & 0x007f0000 ) >> 16)
+#define GET_RLS_ABT_INT (((REG32(ADR_ALC_RLS_ABORT)) & 0x80000000 ) >> 31)
+#define GET_DEBUG_CTL (((REG32(ADR_DEBUG_CTL)) & 0x000000ff ) >> 0)
+#define GET_DEBUG_H16 (((REG32(ADR_DEBUG_CTL)) & 0x00000100 ) >> 8)
+#define GET_DEBUG_OUT (((REG32(ADR_DEBUG_OUT)) & 0xffffffff ) >> 0)
+#define GET_ALC_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_RLS_ERR (((REG32(ADR_MMU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_AL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00000700 ) >> 8)
+#define GET_RL_STATE (((REG32(ADR_MMU_STATUS)) & 0x00007000 ) >> 12)
+#define GET_ALC_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x007f0000 ) >> 16)
+#define GET_RLS_ERR_ID (((REG32(ADR_MMU_STATUS)) & 0x7f000000 ) >> 24)
+#define GET_DMN_NOHIT_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000001 ) >> 0)
+#define GET_DMN_FLAG (((REG32(ADR_DMN_STATUS)) & 0x00000002 ) >> 1)
+#define GET_DMN_WR (((REG32(ADR_DMN_STATUS)) & 0x00000008 ) >> 3)
+#define GET_DMN_PORT (((REG32(ADR_DMN_STATUS)) & 0x000000f0 ) >> 4)
+#define GET_DMN_NHIT_ID (((REG32(ADR_DMN_STATUS)) & 0x00007f00 ) >> 8)
+#define GET_DMN_NHIT_ADDR (((REG32(ADR_DMN_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_TX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x000000ff ) >> 0)
+#define GET_RX_MOUNT (((REG32(ADR_TAG_STATUS)) & 0x0000ff00 ) >> 8)
+#define GET_AVA_TAG (((REG32(ADR_TAG_STATUS)) & 0x01ff0000 ) >> 16)
+#define GET_PKTBUF_FULL (((REG32(ADR_TAG_STATUS)) & 0x80000000 ) >> 31)
+#define GET_DMN_NOHIT_MCU (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000001 ) >> 0)
+#define GET_DMN_MCU_FLAG (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000002 ) >> 1)
+#define GET_DMN_MCU_WR (((REG32(ADR_DMN_MCU_STATUS)) & 0x00000008 ) >> 3)
+#define GET_DMN_MCU_PORT (((REG32(ADR_DMN_MCU_STATUS)) & 0x000000f0 ) >> 4)
+#define GET_DMN_MCU_ID (((REG32(ADR_DMN_MCU_STATUS)) & 0x00007f00 ) >> 8)
+#define GET_DMN_MCU_ADDR (((REG32(ADR_DMN_MCU_STATUS)) & 0xffff0000 ) >> 16)
+#define GET_MB_IDTBL_31_0 (((REG32(ADR_MB_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_MB_IDTBL_63_32 (((REG32(ADR_MB_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_MB_IDTBL_95_64 (((REG32(ADR_MB_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_MB_IDTBL_127_96 (((REG32(ADR_MB_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_31_0 (((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_63_32 (((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_95_64 (((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_PKT_IDTBL_127_96 (((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_31_0 (((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_63_32 (((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_95_64 (((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_DMN_IDTBL_127_96 (((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_31_0 (((REG32(ADR_MB_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_63_32 (((REG32(ADR_MB_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_95_64 (((REG32(ADR_MB_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_MB_ID_127_96 (((REG32(ADR_MB_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_31_0 (((REG32(ADR_PKT_NEQID_0_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_63_32 (((REG32(ADR_PKT_NEQID_1_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_95_64 (((REG32(ADR_PKT_NEQID_2_STATUS)) & 0xffffffff ) >> 0)
+#define GET_NEQ_PKT_ID_127_96 (((REG32(ADR_PKT_NEQID_3_STATUS)) & 0xffffffff ) >> 0)
+#define GET_ALC_NOCHG_ID (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x0000007f ) >> 0)
+#define GET_ALC_NOCHG_INT (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00008000 ) >> 15)
+#define GET_NEQ_PKT_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x00010000 ) >> 16)
+#define GET_NEQ_MB_FLAG (((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0x01000000 ) >> 24)
+#define GET_SRAM_TAG_0 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_1 (((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_2 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_3 (((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_4 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_5 (((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_6 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_7 (((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_8 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_9 (((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_10 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_11 (((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_12 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_13 (((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000 ) >> 16)
+#define GET_SRAM_TAG_14 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff ) >> 0)
+#define GET_SRAM_TAG_15 (((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000 ) >> 16)
+#define SET_MCU_ENABLE(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 0) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffe))
+#define SET_MAC_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 1) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffd))
+#define SET_MCU_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 2) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffffb))
+#define SET_SDIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 3) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffff7))
+#define SET_SPI_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 4) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffef))
+#define SET_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 5) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffdf))
+#define SET_DMA_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 6) | ((REG32(ADR_BRG_SW_RST)) & 0xffffffbf))
+#define SET_WDT_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 7) | ((REG32(ADR_BRG_SW_RST)) & 0xffffff7f))
+#define SET_I2C_SLV_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 8) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffeff))
+#define SET_INT_CTL_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 9) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffdff))
+#define SET_BTCX_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 10) | ((REG32(ADR_BRG_SW_RST)) & 0xfffffbff))
+#define SET_GPIO_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 11) | ((REG32(ADR_BRG_SW_RST)) & 0xfffff7ff))
+#define SET_US0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 12) | ((REG32(ADR_BRG_SW_RST)) & 0xffffefff))
+#define SET_US1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 13) | ((REG32(ADR_BRG_SW_RST)) & 0xffffdfff))
+#define SET_US2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 14) | ((REG32(ADR_BRG_SW_RST)) & 0xffffbfff))
+#define SET_US3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 15) | ((REG32(ADR_BRG_SW_RST)) & 0xffff7fff))
+#define SET_MS0TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 16) | ((REG32(ADR_BRG_SW_RST)) & 0xfffeffff))
+#define SET_MS1TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 17) | ((REG32(ADR_BRG_SW_RST)) & 0xfffdffff))
+#define SET_MS2TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 18) | ((REG32(ADR_BRG_SW_RST)) & 0xfffbffff))
+#define SET_MS3TMR_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 19) | ((REG32(ADR_BRG_SW_RST)) & 0xfff7ffff))
+#define SET_RF_BB_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 20) | ((REG32(ADR_BRG_SW_RST)) & 0xffefffff))
+#define SET_SYS_ALL_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 21) | ((REG32(ADR_BRG_SW_RST)) & 0xffdfffff))
+#define SET_DAT_UART_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 22) | ((REG32(ADR_BRG_SW_RST)) & 0xffbfffff))
+#define SET_I2C_MST_SW_RST(_VAL_) (REG32(ADR_BRG_SW_RST)) = (((_VAL_) << 23) | ((REG32(ADR_BRG_SW_RST)) & 0xff7fffff))
+#define SET_RG_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT)) & 0xfffffffe))
+#define SET_TRAP_IMG_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 16) | ((REG32(ADR_BOOT)) & 0xfffeffff))
+#define SET_TRAP_REBOOT(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 17) | ((REG32(ADR_BOOT)) & 0xfffdffff))
+#define SET_TRAP_BOOT_FLS(_VAL_) (REG32(ADR_BOOT)) = (((_VAL_) << 18) | ((REG32(ADR_BOOT)) & 0xfffbffff))
+#define SET_CHIP_ID_31_0(_VAL_) (REG32(ADR_CHIP_ID_0)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_0)) & 0x00000000))
+#define SET_CHIP_ID_63_32(_VAL_) (REG32(ADR_CHIP_ID_1)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_1)) & 0x00000000))
+#define SET_CHIP_ID_95_64(_VAL_) (REG32(ADR_CHIP_ID_2)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_2)) & 0x00000000))
+#define SET_CHIP_ID_127_96(_VAL_) (REG32(ADR_CHIP_ID_3)) = (((_VAL_) << 0) | ((REG32(ADR_CHIP_ID_3)) & 0x00000000))
+#define SET_CK_SEL_1_0(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 0) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffc))
+#define SET_CK_SEL_2(_VAL_) (REG32(ADR_CLOCK_SELECTION)) = (((_VAL_) << 2) | ((REG32(ADR_CLOCK_SELECTION)) & 0xfffffffb))
+#define SET_SYS_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffe))
+#define SET_MAC_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MCU_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 2) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffffb))
+#define SET_SDIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffff7))
+#define SET_SPI_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffef))
+#define SET_UART_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffdf))
+#define SET_DMA_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffffbf))
+#define SET_WDT_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffff7f))
+#define SET_I2C_SLV_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 8) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffeff))
+#define SET_INT_CTL_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffdff))
+#define SET_BTCX_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_GPIO_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffff7ff))
+#define SET_US0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffefff))
+#define SET_US1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_US2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffffbfff))
+#define SET_US3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffff7fff))
+#define SET_MS0TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 16) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffeffff))
+#define SET_MS1TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 17) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffdffff))
+#define SET_MS2TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 18) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfffbffff))
+#define SET_MS3TMR_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 19) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xfff7ffff))
+#define SET_BIST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 20) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xffefffff))
+#define SET_I2C_MST_CLK_EN(_VAL_) (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (((_VAL_) << 23) | ((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0xff7fffff))
+#define SET_BTCX_CSR_CLK_EN(_VAL_) (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_MCU_DBG_SEL(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_SEL)) & 0xffffffc0))
+#define SET_MCU_STOP_NOGRANT(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffeff))
+#define SET_MCU_STOP_ANYTIME(_VAL_) (REG32(ADR_MCU_DBG_SEL)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_DBG_SEL)) & 0xfffffdff))
+#define SET_MCU_DBG_DATA(_VAL_) (REG32(ADR_MCU_DBG_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_DBG_DATA)) & 0x00000000))
+#define SET_AHB_SW_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffe))
+#define SET_AHB_ERR_RST(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffffd))
+#define SET_REG_AHB_DEBUG_MX(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffffcf))
+#define SET_REG_PKT_W_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffeff))
+#define SET_REG_PKT_R_NBRT(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xfffffdff))
+#define SET_IQ_SRAM_SEL_0(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffefff))
+#define SET_IQ_SRAM_SEL_1(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffdfff))
+#define SET_IQ_SRAM_SEL_2(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_AHB_BRG_STATUS)) & 0xffffbfff))
+#define SET_AHB_STATUS(_VAL_) (REG32(ADR_AHB_BRG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_AHB_BRG_STATUS)) & 0x0000ffff))
+#define SET_PARALLEL_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffffe))
+#define SET_MBRUN(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xffffffef))
+#define SET_SHIFT_DR(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffeff))
+#define SET_MODE_REG_SI(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffdff))
+#define SET_SIMULATION_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffffbff))
+#define SET_DBIST_MODE(_VAL_) (REG32(ADR_BIST_BIST_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_BIST_BIST_CTRL)) & 0xfffff7ff))
+#define SET_MODE_REG_IN(_VAL_) (REG32(ADR_BIST_MODE_REG_IN)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN)) & 0xffe00000))
+#define SET_MODE_REG_OUT_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0xffe00000))
+#define SET_MODE_REG_SO_MCU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT)) & 0x7fffffff))
+#define SET_MONITOR_BUS_MCU_31_0(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_LSB)) & 0x00000000))
+#define SET_MONITOR_BUS_MCU_33_32(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MSB)) & 0xfffffffc))
+#define SET_TB_ADR_SEL(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_TB_ADR_SEL)) & 0xffff0000))
+#define SET_TB_CS(_VAL_) (REG32(ADR_TB_ADR_SEL)) = (((_VAL_) << 31) | ((REG32(ADR_TB_ADR_SEL)) & 0x7fffffff))
+#define SET_TB_RDATA(_VAL_) (REG32(ADR_TB_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_TB_RDATA)) & 0x00000000))
+#define SET_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 0) | ((REG32(ADR_UART_W2B)) & 0xfffffffe))
+#define SET_DATA_UART_W2B_EN(_VAL_) (REG32(ADR_UART_W2B)) = (((_VAL_) << 4) | ((REG32(ADR_UART_W2B)) & 0xffffffef))
+#define SET_AHB_ILL_ADDR(_VAL_) (REG32(ADR_AHB_ILL_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILL_ADDR)) & 0x00000000))
+#define SET_AHB_FEN_ADDR(_VAL_) (REG32(ADR_AHB_FEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_FEN_ADDR)) & 0x00000000))
+#define SET_ILL_ADDR_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffe))
+#define SET_FENCE_HIT_CLR(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xfffffffd))
+#define SET_ILL_ADDR_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffef))
+#define SET_FENCE_HIT_INT(_VAL_) (REG32(ADR_AHB_ILLFEN_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_AHB_ILLFEN_STATUS)) & 0xffffffdf))
+#define SET_PWM_INI_VALUE_P_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_A)) & 0xffffff00))
+#define SET_PWM_INI_VALUE_N_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_A)) & 0xffff00ff))
+#define SET_PWM_POST_SCALER_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_A)) & 0xfff0ffff))
+#define SET_PWM_ALWAYSON_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_A)) & 0xdfffffff))
+#define SET_PWM_INVERT_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_A)) & 0xbfffffff))
+#define SET_PWM_ENABLE_A(_VAL_) (REG32(ADR_PWM_A)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_A)) & 0x7fffffff))
+#define SET_PWM_INI_VALUE_P_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 0) | ((REG32(ADR_PWM_B)) & 0xffffff00))
+#define SET_PWM_INI_VALUE_N_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 8) | ((REG32(ADR_PWM_B)) & 0xffff00ff))
+#define SET_PWM_POST_SCALER_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 16) | ((REG32(ADR_PWM_B)) & 0xfff0ffff))
+#define SET_PWM_ALWAYSON_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 29) | ((REG32(ADR_PWM_B)) & 0xdfffffff))
+#define SET_PWM_INVERT_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 30) | ((REG32(ADR_PWM_B)) & 0xbfffffff))
+#define SET_PWM_ENABLE_B(_VAL_) (REG32(ADR_PWM_B)) = (((_VAL_) << 31) | ((REG32(ADR_PWM_B)) & 0x7fffffff))
+#define SET_HBUSREQ_LOCK(_VAL_) (REG32(ADR_HBUSREQ_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBUSREQ_LOCK)) & 0xffffe000))
+#define SET_HBURST_LOCK(_VAL_) (REG32(ADR_HBURST_LOCK)) = (((_VAL_) << 0) | ((REG32(ADR_HBURST_LOCK)) & 0xffffe000))
+#define SET_PRESCALER_USTIMER(_VAL_) (REG32(ADR_PRESCALER_USTIMER)) = (((_VAL_) << 0) | ((REG32(ADR_PRESCALER_USTIMER)) & 0xfffffe00))
+#define SET_MODE_REG_IN_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_IN_MMU)) & 0xffff0000))
+#define SET_MODE_REG_OUT_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0xffff0000))
+#define SET_MODE_REG_SO_MMU(_VAL_) (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (((_VAL_) << 31) | ((REG32(ADR_BIST_MODE_REG_OUT_MMU)) & 0x7fffffff))
+#define SET_MONITOR_BUS_MMU(_VAL_) (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (((_VAL_) << 0) | ((REG32(ADR_BIST_MONITOR_BUS_MMU)) & 0xfff80000))
+#define SET_TEST_MODE0(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_TEST_MODE)) & 0xfffffffe))
+#define SET_TEST_MODE1(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_TEST_MODE)) & 0xfffffffd))
+#define SET_TEST_MODE2(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_TEST_MODE)) & 0xfffffffb))
+#define SET_TEST_MODE3(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_TEST_MODE)) & 0xfffffff7))
+#define SET_TEST_MODE4(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_TEST_MODE)) & 0xffffffef))
+#define SET_TEST_MODE_ALL(_VAL_) (REG32(ADR_TEST_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_TEST_MODE)) & 0xffffffdf))
+#define SET_WDT_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffe))
+#define SET_SD_HOST_INIT(_VAL_) (REG32(ADR_BOOT_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_BOOT_INFO)) & 0xfffffffd))
+#define SET_ALLOW_SD_RESET(_VAL_) (REG32(ADR_SD_INIT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_SD_INIT_CFG)) & 0xfffffffe))
+#define SET_UART_NRTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffe))
+#define SET_UART_NCTS(_VAL_) (REG32(ADR_SPARE_UART_INFO)) = (((_VAL_) << 1) | ((REG32(ADR_SPARE_UART_INFO)) & 0xfffffffd))
+#define SET_TU0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU0_TM_MODE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU0_TM_INT_MASK(_VAL_) (REG32(ADR_TU0_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TU1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU1_TM_MODE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU1_TM_INT_MASK(_VAL_) (REG32(ADR_TU1_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TU2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU2_TM_MODE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU2_TM_INT_MASK(_VAL_) (REG32(ADR_TU2_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TU3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xffff0000))
+#define SET_TU3_TM_MODE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffeffff))
+#define SET_TU3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffdffff))
+#define SET_TU3_TM_INT_MASK(_VAL_) (REG32(ADR_TU3_MICROSECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0xfffbffff))
+#define SET_TU3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM0_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM0_TM_MODE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM0_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM0_TM_INT_MASK(_VAL_) (REG32(ADR_TM0_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM0_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM0_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM1_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM1_TM_MODE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM1_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM1_TM_INT_MASK(_VAL_) (REG32(ADR_TM1_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM1_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM1_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM2_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM2_TM_MODE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM2_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM2_TM_INT_MASK(_VAL_) (REG32(ADR_TM2_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM2_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM2_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_TM3_TM_INIT_VALUE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xffff0000))
+#define SET_TM3_TM_MODE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 16) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffeffff))
+#define SET_TM3_TM_INT_STS_DONE(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 17) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffdffff))
+#define SET_TM3_TM_INT_MASK(_VAL_) (REG32(ADR_TM3_MILISECOND_TIMER)) = (((_VAL_) << 18) | ((REG32(ADR_TM3_MILISECOND_TIMER)) & 0xfffbffff))
+#define SET_TM3_TM_CUR_VALUE(_VAL_) (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (((_VAL_) << 0) | ((REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) & 0xffff0000))
+#define SET_MCU_WDT_TIME_CNT(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_WDOG_REG)) & 0xffff0000))
+#define SET_MCU_WDT_STATUS(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_MCU_WDOG_REG)) & 0xfffdffff))
+#define SET_MCU_WDOG_ENA(_VAL_) (REG32(ADR_MCU_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_MCU_WDOG_REG)) & 0x7fffffff))
+#define SET_SYS_WDT_TIME_CNT(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_WDOG_REG)) & 0xffff0000))
+#define SET_SYS_WDT_STATUS(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYS_WDOG_REG)) & 0xfffdffff))
+#define SET_SYS_WDOG_ENA(_VAL_) (REG32(ADR_SYS_WDOG_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYS_WDOG_REG)) & 0x7fffffff))
+#define SET_XLNA_EN_O_OE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 0) | ((REG32(ADR_PAD6)) & 0xfffffffe))
+#define SET_XLNA_EN_O_PE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 1) | ((REG32(ADR_PAD6)) & 0xfffffffd))
+#define SET_PAD6_IE(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 3) | ((REG32(ADR_PAD6)) & 0xfffffff7))
+#define SET_PAD6_SEL_I(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 4) | ((REG32(ADR_PAD6)) & 0xffffffcf))
+#define SET_PAD6_OD(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 8) | ((REG32(ADR_PAD6)) & 0xfffffeff))
+#define SET_PAD6_SEL_O(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 12) | ((REG32(ADR_PAD6)) & 0xffffefff))
+#define SET_XLNA_EN_O_C(_VAL_) (REG32(ADR_PAD6)) = (((_VAL_) << 28) | ((REG32(ADR_PAD6)) & 0xefffffff))
+#define SET_WIFI_TX_SW_O_OE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 0) | ((REG32(ADR_PAD7)) & 0xfffffffe))
+#define SET_WIFI_TX_SW_O_PE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 1) | ((REG32(ADR_PAD7)) & 0xfffffffd))
+#define SET_PAD7_IE(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 3) | ((REG32(ADR_PAD7)) & 0xfffffff7))
+#define SET_PAD7_SEL_I(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 4) | ((REG32(ADR_PAD7)) & 0xffffffcf))
+#define SET_PAD7_OD(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 8) | ((REG32(ADR_PAD7)) & 0xfffffeff))
+#define SET_PAD7_SEL_O(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 12) | ((REG32(ADR_PAD7)) & 0xffffefff))
+#define SET_WIFI_TX_SW_O_C(_VAL_) (REG32(ADR_PAD7)) = (((_VAL_) << 28) | ((REG32(ADR_PAD7)) & 0xefffffff))
+#define SET_WIFI_RX_SW_O_OE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 0) | ((REG32(ADR_PAD8)) & 0xfffffffe))
+#define SET_WIFI_RX_SW_O_PE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 1) | ((REG32(ADR_PAD8)) & 0xfffffffd))
+#define SET_PAD8_IE(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 3) | ((REG32(ADR_PAD8)) & 0xfffffff7))
+#define SET_PAD8_SEL_I(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 4) | ((REG32(ADR_PAD8)) & 0xffffffcf))
+#define SET_PAD8_OD(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 8) | ((REG32(ADR_PAD8)) & 0xfffffeff))
+#define SET_WIFI_RX_SW_O_C(_VAL_) (REG32(ADR_PAD8)) = (((_VAL_) << 28) | ((REG32(ADR_PAD8)) & 0xefffffff))
+#define SET_BT_SW_O_OE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 0) | ((REG32(ADR_PAD9)) & 0xfffffffe))
+#define SET_BT_SW_O_PE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 1) | ((REG32(ADR_PAD9)) & 0xfffffffd))
+#define SET_PAD9_IE(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 3) | ((REG32(ADR_PAD9)) & 0xfffffff7))
+#define SET_PAD9_SEL_I(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 4) | ((REG32(ADR_PAD9)) & 0xffffffcf))
+#define SET_PAD9_OD(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 8) | ((REG32(ADR_PAD9)) & 0xfffffeff))
+#define SET_PAD9_SEL_O(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 12) | ((REG32(ADR_PAD9)) & 0xffffefff))
+#define SET_BT_SW_O_C(_VAL_) (REG32(ADR_PAD9)) = (((_VAL_) << 28) | ((REG32(ADR_PAD9)) & 0xefffffff))
+#define SET_XPA_EN_O_OE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 0) | ((REG32(ADR_PAD11)) & 0xfffffffe))
+#define SET_XPA_EN_O_PE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 1) | ((REG32(ADR_PAD11)) & 0xfffffffd))
+#define SET_PAD11_IE(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 3) | ((REG32(ADR_PAD11)) & 0xfffffff7))
+#define SET_PAD11_SEL_I(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 4) | ((REG32(ADR_PAD11)) & 0xffffffcf))
+#define SET_PAD11_OD(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 8) | ((REG32(ADR_PAD11)) & 0xfffffeff))
+#define SET_PAD11_SEL_O(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 12) | ((REG32(ADR_PAD11)) & 0xffffefff))
+#define SET_XPA_EN_O_C(_VAL_) (REG32(ADR_PAD11)) = (((_VAL_) << 28) | ((REG32(ADR_PAD11)) & 0xefffffff))
+#define SET_PAD15_OE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 0) | ((REG32(ADR_PAD15)) & 0xfffffffe))
+#define SET_PAD15_PE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 1) | ((REG32(ADR_PAD15)) & 0xfffffffd))
+#define SET_PAD15_DS(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 2) | ((REG32(ADR_PAD15)) & 0xfffffffb))
+#define SET_PAD15_IE(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 3) | ((REG32(ADR_PAD15)) & 0xfffffff7))
+#define SET_PAD15_SEL_I(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 4) | ((REG32(ADR_PAD15)) & 0xffffffcf))
+#define SET_PAD15_OD(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 8) | ((REG32(ADR_PAD15)) & 0xfffffeff))
+#define SET_PAD15_SEL_O(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 12) | ((REG32(ADR_PAD15)) & 0xffffefff))
+#define SET_TEST_1_ID(_VAL_) (REG32(ADR_PAD15)) = (((_VAL_) << 28) | ((REG32(ADR_PAD15)) & 0xefffffff))
+#define SET_PAD16_OE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 0) | ((REG32(ADR_PAD16)) & 0xfffffffe))
+#define SET_PAD16_PE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 1) | ((REG32(ADR_PAD16)) & 0xfffffffd))
+#define SET_PAD16_DS(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 2) | ((REG32(ADR_PAD16)) & 0xfffffffb))
+#define SET_PAD16_IE(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 3) | ((REG32(ADR_PAD16)) & 0xfffffff7))
+#define SET_PAD16_SEL_I(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 4) | ((REG32(ADR_PAD16)) & 0xffffffcf))
+#define SET_PAD16_OD(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 8) | ((REG32(ADR_PAD16)) & 0xfffffeff))
+#define SET_PAD16_SEL_O(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 12) | ((REG32(ADR_PAD16)) & 0xffffefff))
+#define SET_TEST_2_ID(_VAL_) (REG32(ADR_PAD16)) = (((_VAL_) << 28) | ((REG32(ADR_PAD16)) & 0xefffffff))
+#define SET_PAD17_OE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 0) | ((REG32(ADR_PAD17)) & 0xfffffffe))
+#define SET_PAD17_PE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 1) | ((REG32(ADR_PAD17)) & 0xfffffffd))
+#define SET_PAD17_DS(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 2) | ((REG32(ADR_PAD17)) & 0xfffffffb))
+#define SET_PAD17_IE(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 3) | ((REG32(ADR_PAD17)) & 0xfffffff7))
+#define SET_PAD17_SEL_I(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 4) | ((REG32(ADR_PAD17)) & 0xffffffcf))
+#define SET_PAD17_OD(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 8) | ((REG32(ADR_PAD17)) & 0xfffffeff))
+#define SET_PAD17_SEL_O(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 12) | ((REG32(ADR_PAD17)) & 0xffffefff))
+#define SET_TEST_3_ID(_VAL_) (REG32(ADR_PAD17)) = (((_VAL_) << 28) | ((REG32(ADR_PAD17)) & 0xefffffff))
+#define SET_PAD18_OE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 0) | ((REG32(ADR_PAD18)) & 0xfffffffe))
+#define SET_PAD18_PE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 1) | ((REG32(ADR_PAD18)) & 0xfffffffd))
+#define SET_PAD18_DS(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 2) | ((REG32(ADR_PAD18)) & 0xfffffffb))
+#define SET_PAD18_IE(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 3) | ((REG32(ADR_PAD18)) & 0xfffffff7))
+#define SET_PAD18_SEL_I(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 4) | ((REG32(ADR_PAD18)) & 0xffffffcf))
+#define SET_PAD18_OD(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 8) | ((REG32(ADR_PAD18)) & 0xfffffeff))
+#define SET_PAD18_SEL_O(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 12) | ((REG32(ADR_PAD18)) & 0xffffcfff))
+#define SET_TEST_4_ID(_VAL_) (REG32(ADR_PAD18)) = (((_VAL_) << 28) | ((REG32(ADR_PAD18)) & 0xefffffff))
+#define SET_PAD19_OE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 0) | ((REG32(ADR_PAD19)) & 0xfffffffe))
+#define SET_PAD19_PE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 1) | ((REG32(ADR_PAD19)) & 0xfffffffd))
+#define SET_PAD19_DS(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 2) | ((REG32(ADR_PAD19)) & 0xfffffffb))
+#define SET_PAD19_IE(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 3) | ((REG32(ADR_PAD19)) & 0xfffffff7))
+#define SET_PAD19_SEL_I(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 4) | ((REG32(ADR_PAD19)) & 0xffffffcf))
+#define SET_PAD19_OD(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 8) | ((REG32(ADR_PAD19)) & 0xfffffeff))
+#define SET_PAD19_SEL_O(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 12) | ((REG32(ADR_PAD19)) & 0xffff8fff))
+#define SET_SHORT_TO_20_ID(_VAL_) (REG32(ADR_PAD19)) = (((_VAL_) << 28) | ((REG32(ADR_PAD19)) & 0xefffffff))
+#define SET_PAD20_OE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 0) | ((REG32(ADR_PAD20)) & 0xfffffffe))
+#define SET_PAD20_PE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 1) | ((REG32(ADR_PAD20)) & 0xfffffffd))
+#define SET_PAD20_DS(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 2) | ((REG32(ADR_PAD20)) & 0xfffffffb))
+#define SET_PAD20_IE(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 3) | ((REG32(ADR_PAD20)) & 0xfffffff7))
+#define SET_PAD20_SEL_I(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 4) | ((REG32(ADR_PAD20)) & 0xffffff0f))
+#define SET_PAD20_OD(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 8) | ((REG32(ADR_PAD20)) & 0xfffffeff))
+#define SET_PAD20_SEL_O(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 12) | ((REG32(ADR_PAD20)) & 0xffffcfff))
+#define SET_STRAP0(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 27) | ((REG32(ADR_PAD20)) & 0xf7ffffff))
+#define SET_GPIO_TEST_1_ID(_VAL_) (REG32(ADR_PAD20)) = (((_VAL_) << 28) | ((REG32(ADR_PAD20)) & 0xefffffff))
+#define SET_PAD21_OE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 0) | ((REG32(ADR_PAD21)) & 0xfffffffe))
+#define SET_PAD21_PE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 1) | ((REG32(ADR_PAD21)) & 0xfffffffd))
+#define SET_PAD21_DS(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 2) | ((REG32(ADR_PAD21)) & 0xfffffffb))
+#define SET_PAD21_IE(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 3) | ((REG32(ADR_PAD21)) & 0xfffffff7))
+#define SET_PAD21_SEL_I(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 4) | ((REG32(ADR_PAD21)) & 0xffffff8f))
+#define SET_PAD21_OD(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 8) | ((REG32(ADR_PAD21)) & 0xfffffeff))
+#define SET_PAD21_SEL_O(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 12) | ((REG32(ADR_PAD21)) & 0xffffcfff))
+#define SET_STRAP3(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 27) | ((REG32(ADR_PAD21)) & 0xf7ffffff))
+#define SET_GPIO_TEST_2_ID(_VAL_) (REG32(ADR_PAD21)) = (((_VAL_) << 28) | ((REG32(ADR_PAD21)) & 0xefffffff))
+#define SET_PAD22_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 0) | ((REG32(ADR_PAD22)) & 0xfffffffe))
+#define SET_PAD22_PE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 1) | ((REG32(ADR_PAD22)) & 0xfffffffd))
+#define SET_PAD22_DS(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 2) | ((REG32(ADR_PAD22)) & 0xfffffffb))
+#define SET_PAD22_IE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 3) | ((REG32(ADR_PAD22)) & 0xfffffff7))
+#define SET_PAD22_SEL_I(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 4) | ((REG32(ADR_PAD22)) & 0xffffff8f))
+#define SET_PAD22_OD(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 8) | ((REG32(ADR_PAD22)) & 0xfffffeff))
+#define SET_PAD22_SEL_O(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 12) | ((REG32(ADR_PAD22)) & 0xffff8fff))
+#define SET_PAD22_SEL_OE(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 20) | ((REG32(ADR_PAD22)) & 0xffefffff))
+#define SET_GPIO_TEST_3_ID(_VAL_) (REG32(ADR_PAD22)) = (((_VAL_) << 28) | ((REG32(ADR_PAD22)) & 0xefffffff))
+#define SET_PAD24_OE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 0) | ((REG32(ADR_PAD24)) & 0xfffffffe))
+#define SET_PAD24_PE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 1) | ((REG32(ADR_PAD24)) & 0xfffffffd))
+#define SET_PAD24_DS(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 2) | ((REG32(ADR_PAD24)) & 0xfffffffb))
+#define SET_PAD24_IE(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 3) | ((REG32(ADR_PAD24)) & 0xfffffff7))
+#define SET_PAD24_SEL_I(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 4) | ((REG32(ADR_PAD24)) & 0xffffffcf))
+#define SET_PAD24_OD(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 8) | ((REG32(ADR_PAD24)) & 0xfffffeff))
+#define SET_PAD24_SEL_O(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 12) | ((REG32(ADR_PAD24)) & 0xffff8fff))
+#define SET_GPIO_TEST_4_ID(_VAL_) (REG32(ADR_PAD24)) = (((_VAL_) << 28) | ((REG32(ADR_PAD24)) & 0xefffffff))
+#define SET_PAD25_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 0) | ((REG32(ADR_PAD25)) & 0xfffffffe))
+#define SET_PAD25_PE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 1) | ((REG32(ADR_PAD25)) & 0xfffffffd))
+#define SET_PAD25_DS(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 2) | ((REG32(ADR_PAD25)) & 0xfffffffb))
+#define SET_PAD25_IE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 3) | ((REG32(ADR_PAD25)) & 0xfffffff7))
+#define SET_PAD25_SEL_I(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 4) | ((REG32(ADR_PAD25)) & 0xffffff8f))
+#define SET_PAD25_OD(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 8) | ((REG32(ADR_PAD25)) & 0xfffffeff))
+#define SET_PAD25_SEL_O(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 12) | ((REG32(ADR_PAD25)) & 0xffff8fff))
+#define SET_PAD25_SEL_OE(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 20) | ((REG32(ADR_PAD25)) & 0xffefffff))
+#define SET_STRAP1(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 27) | ((REG32(ADR_PAD25)) & 0xf7ffffff))
+#define SET_GPIO_1_ID(_VAL_) (REG32(ADR_PAD25)) = (((_VAL_) << 28) | ((REG32(ADR_PAD25)) & 0xefffffff))
+#define SET_PAD27_OE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 0) | ((REG32(ADR_PAD27)) & 0xfffffffe))
+#define SET_PAD27_PE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 1) | ((REG32(ADR_PAD27)) & 0xfffffffd))
+#define SET_PAD27_DS(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 2) | ((REG32(ADR_PAD27)) & 0xfffffffb))
+#define SET_PAD27_IE(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 3) | ((REG32(ADR_PAD27)) & 0xfffffff7))
+#define SET_PAD27_SEL_I(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 4) | ((REG32(ADR_PAD27)) & 0xffffff8f))
+#define SET_PAD27_OD(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 8) | ((REG32(ADR_PAD27)) & 0xfffffeff))
+#define SET_PAD27_SEL_O(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 12) | ((REG32(ADR_PAD27)) & 0xffff8fff))
+#define SET_GPIO_2_ID(_VAL_) (REG32(ADR_PAD27)) = (((_VAL_) << 28) | ((REG32(ADR_PAD27)) & 0xefffffff))
+#define SET_PAD28_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 0) | ((REG32(ADR_PAD28)) & 0xfffffffe))
+#define SET_PAD28_PE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 1) | ((REG32(ADR_PAD28)) & 0xfffffffd))
+#define SET_PAD28_DS(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 2) | ((REG32(ADR_PAD28)) & 0xfffffffb))
+#define SET_PAD28_IE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 3) | ((REG32(ADR_PAD28)) & 0xfffffff7))
+#define SET_PAD28_SEL_I(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 4) | ((REG32(ADR_PAD28)) & 0xffffff8f))
+#define SET_PAD28_OD(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 8) | ((REG32(ADR_PAD28)) & 0xfffffeff))
+#define SET_PAD28_SEL_O(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 12) | ((REG32(ADR_PAD28)) & 0xffff0fff))
+#define SET_PAD28_SEL_OE(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 20) | ((REG32(ADR_PAD28)) & 0xffefffff))
+#define SET_GPIO_3_ID(_VAL_) (REG32(ADR_PAD28)) = (((_VAL_) << 28) | ((REG32(ADR_PAD28)) & 0xefffffff))
+#define SET_PAD29_OE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 0) | ((REG32(ADR_PAD29)) & 0xfffffffe))
+#define SET_PAD29_PE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 1) | ((REG32(ADR_PAD29)) & 0xfffffffd))
+#define SET_PAD29_DS(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 2) | ((REG32(ADR_PAD29)) & 0xfffffffb))
+#define SET_PAD29_IE(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 3) | ((REG32(ADR_PAD29)) & 0xfffffff7))
+#define SET_PAD29_SEL_I(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 4) | ((REG32(ADR_PAD29)) & 0xffffff8f))
+#define SET_PAD29_OD(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 8) | ((REG32(ADR_PAD29)) & 0xfffffeff))
+#define SET_PAD29_SEL_O(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 12) | ((REG32(ADR_PAD29)) & 0xffff8fff))
+#define SET_GPIO_TEST_5_ID(_VAL_) (REG32(ADR_PAD29)) = (((_VAL_) << 28) | ((REG32(ADR_PAD29)) & 0xefffffff))
+#define SET_PAD30_OE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 0) | ((REG32(ADR_PAD30)) & 0xfffffffe))
+#define SET_PAD30_PE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 1) | ((REG32(ADR_PAD30)) & 0xfffffffd))
+#define SET_PAD30_DS(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 2) | ((REG32(ADR_PAD30)) & 0xfffffffb))
+#define SET_PAD30_IE(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 3) | ((REG32(ADR_PAD30)) & 0xfffffff7))
+#define SET_PAD30_SEL_I(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 4) | ((REG32(ADR_PAD30)) & 0xffffffcf))
+#define SET_PAD30_OD(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 8) | ((REG32(ADR_PAD30)) & 0xfffffeff))
+#define SET_PAD30_SEL_O(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 12) | ((REG32(ADR_PAD30)) & 0xffffcfff))
+#define SET_TEST_6_ID(_VAL_) (REG32(ADR_PAD30)) = (((_VAL_) << 28) | ((REG32(ADR_PAD30)) & 0xefffffff))
+#define SET_PAD31_OE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 0) | ((REG32(ADR_PAD31)) & 0xfffffffe))
+#define SET_PAD31_PE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 1) | ((REG32(ADR_PAD31)) & 0xfffffffd))
+#define SET_PAD31_DS(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 2) | ((REG32(ADR_PAD31)) & 0xfffffffb))
+#define SET_PAD31_IE(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 3) | ((REG32(ADR_PAD31)) & 0xfffffff7))
+#define SET_PAD31_SEL_I(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 4) | ((REG32(ADR_PAD31)) & 0xffffffcf))
+#define SET_PAD31_OD(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 8) | ((REG32(ADR_PAD31)) & 0xfffffeff))
+#define SET_PAD31_SEL_O(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 12) | ((REG32(ADR_PAD31)) & 0xffffcfff))
+#define SET_TEST_7_ID(_VAL_) (REG32(ADR_PAD31)) = (((_VAL_) << 28) | ((REG32(ADR_PAD31)) & 0xefffffff))
+#define SET_PAD32_OE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 0) | ((REG32(ADR_PAD32)) & 0xfffffffe))
+#define SET_PAD32_PE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 1) | ((REG32(ADR_PAD32)) & 0xfffffffd))
+#define SET_PAD32_DS(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 2) | ((REG32(ADR_PAD32)) & 0xfffffffb))
+#define SET_PAD32_IE(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 3) | ((REG32(ADR_PAD32)) & 0xfffffff7))
+#define SET_PAD32_SEL_I(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 4) | ((REG32(ADR_PAD32)) & 0xffffffcf))
+#define SET_PAD32_OD(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 8) | ((REG32(ADR_PAD32)) & 0xfffffeff))
+#define SET_PAD32_SEL_O(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 12) | ((REG32(ADR_PAD32)) & 0xffffcfff))
+#define SET_TEST_8_ID(_VAL_) (REG32(ADR_PAD32)) = (((_VAL_) << 28) | ((REG32(ADR_PAD32)) & 0xefffffff))
+#define SET_PAD33_OE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 0) | ((REG32(ADR_PAD33)) & 0xfffffffe))
+#define SET_PAD33_PE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 1) | ((REG32(ADR_PAD33)) & 0xfffffffd))
+#define SET_PAD33_DS(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 2) | ((REG32(ADR_PAD33)) & 0xfffffffb))
+#define SET_PAD33_IE(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 3) | ((REG32(ADR_PAD33)) & 0xfffffff7))
+#define SET_PAD33_SEL_I(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 4) | ((REG32(ADR_PAD33)) & 0xffffffcf))
+#define SET_PAD33_OD(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 8) | ((REG32(ADR_PAD33)) & 0xfffffeff))
+#define SET_PAD33_SEL_O(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 12) | ((REG32(ADR_PAD33)) & 0xffffcfff))
+#define SET_TEST_9_ID(_VAL_) (REG32(ADR_PAD33)) = (((_VAL_) << 28) | ((REG32(ADR_PAD33)) & 0xefffffff))
+#define SET_PAD34_OE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 0) | ((REG32(ADR_PAD34)) & 0xfffffffe))
+#define SET_PAD34_PE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 1) | ((REG32(ADR_PAD34)) & 0xfffffffd))
+#define SET_PAD34_DS(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 2) | ((REG32(ADR_PAD34)) & 0xfffffffb))
+#define SET_PAD34_IE(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 3) | ((REG32(ADR_PAD34)) & 0xfffffff7))
+#define SET_PAD34_SEL_I(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 4) | ((REG32(ADR_PAD34)) & 0xffffffcf))
+#define SET_PAD34_OD(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 8) | ((REG32(ADR_PAD34)) & 0xfffffeff))
+#define SET_PAD34_SEL_O(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 12) | ((REG32(ADR_PAD34)) & 0xffffcfff))
+#define SET_TEST_10_ID(_VAL_) (REG32(ADR_PAD34)) = (((_VAL_) << 28) | ((REG32(ADR_PAD34)) & 0xefffffff))
+#define SET_PAD42_OE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 0) | ((REG32(ADR_PAD42)) & 0xfffffffe))
+#define SET_PAD42_PE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 1) | ((REG32(ADR_PAD42)) & 0xfffffffd))
+#define SET_PAD42_DS(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 2) | ((REG32(ADR_PAD42)) & 0xfffffffb))
+#define SET_PAD42_IE(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 3) | ((REG32(ADR_PAD42)) & 0xfffffff7))
+#define SET_PAD42_SEL_I(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 4) | ((REG32(ADR_PAD42)) & 0xffffffcf))
+#define SET_PAD42_OD(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 8) | ((REG32(ADR_PAD42)) & 0xfffffeff))
+#define SET_PAD42_SEL_O(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 12) | ((REG32(ADR_PAD42)) & 0xffffefff))
+#define SET_TEST_11_ID(_VAL_) (REG32(ADR_PAD42)) = (((_VAL_) << 28) | ((REG32(ADR_PAD42)) & 0xefffffff))
+#define SET_PAD43_OE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 0) | ((REG32(ADR_PAD43)) & 0xfffffffe))
+#define SET_PAD43_PE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 1) | ((REG32(ADR_PAD43)) & 0xfffffffd))
+#define SET_PAD43_DS(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 2) | ((REG32(ADR_PAD43)) & 0xfffffffb))
+#define SET_PAD43_IE(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 3) | ((REG32(ADR_PAD43)) & 0xfffffff7))
+#define SET_PAD43_SEL_I(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 4) | ((REG32(ADR_PAD43)) & 0xffffffcf))
+#define SET_PAD43_OD(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 8) | ((REG32(ADR_PAD43)) & 0xfffffeff))
+#define SET_PAD43_SEL_O(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 12) | ((REG32(ADR_PAD43)) & 0xffffefff))
+#define SET_TEST_12_ID(_VAL_) (REG32(ADR_PAD43)) = (((_VAL_) << 28) | ((REG32(ADR_PAD43)) & 0xefffffff))
+#define SET_PAD44_OE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 0) | ((REG32(ADR_PAD44)) & 0xfffffffe))
+#define SET_PAD44_PE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 1) | ((REG32(ADR_PAD44)) & 0xfffffffd))
+#define SET_PAD44_DS(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 2) | ((REG32(ADR_PAD44)) & 0xfffffffb))
+#define SET_PAD44_IE(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 3) | ((REG32(ADR_PAD44)) & 0xfffffff7))
+#define SET_PAD44_SEL_I(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 4) | ((REG32(ADR_PAD44)) & 0xffffffcf))
+#define SET_PAD44_OD(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 8) | ((REG32(ADR_PAD44)) & 0xfffffeff))
+#define SET_PAD44_SEL_O(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 12) | ((REG32(ADR_PAD44)) & 0xffffcfff))
+#define SET_TEST_13_ID(_VAL_) (REG32(ADR_PAD44)) = (((_VAL_) << 28) | ((REG32(ADR_PAD44)) & 0xefffffff))
+#define SET_PAD45_OE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 0) | ((REG32(ADR_PAD45)) & 0xfffffffe))
+#define SET_PAD45_PE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 1) | ((REG32(ADR_PAD45)) & 0xfffffffd))
+#define SET_PAD45_DS(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 2) | ((REG32(ADR_PAD45)) & 0xfffffffb))
+#define SET_PAD45_IE(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 3) | ((REG32(ADR_PAD45)) & 0xfffffff7))
+#define SET_PAD45_SEL_I(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 4) | ((REG32(ADR_PAD45)) & 0xffffffcf))
+#define SET_PAD45_OD(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 8) | ((REG32(ADR_PAD45)) & 0xfffffeff))
+#define SET_PAD45_SEL_O(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 12) | ((REG32(ADR_PAD45)) & 0xffffcfff))
+#define SET_TEST_14_ID(_VAL_) (REG32(ADR_PAD45)) = (((_VAL_) << 28) | ((REG32(ADR_PAD45)) & 0xefffffff))
+#define SET_PAD46_OE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 0) | ((REG32(ADR_PAD46)) & 0xfffffffe))
+#define SET_PAD46_PE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 1) | ((REG32(ADR_PAD46)) & 0xfffffffd))
+#define SET_PAD46_DS(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 2) | ((REG32(ADR_PAD46)) & 0xfffffffb))
+#define SET_PAD46_IE(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 3) | ((REG32(ADR_PAD46)) & 0xfffffff7))
+#define SET_PAD46_SEL_I(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 4) | ((REG32(ADR_PAD46)) & 0xffffffcf))
+#define SET_PAD46_OD(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 8) | ((REG32(ADR_PAD46)) & 0xfffffeff))
+#define SET_PAD46_SEL_O(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 12) | ((REG32(ADR_PAD46)) & 0xffffcfff))
+#define SET_TEST_15_ID(_VAL_) (REG32(ADR_PAD46)) = (((_VAL_) << 28) | ((REG32(ADR_PAD46)) & 0xefffffff))
+#define SET_PAD47_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 0) | ((REG32(ADR_PAD47)) & 0xfffffffe))
+#define SET_PAD47_PE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 1) | ((REG32(ADR_PAD47)) & 0xfffffffd))
+#define SET_PAD47_DS(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 2) | ((REG32(ADR_PAD47)) & 0xfffffffb))
+#define SET_PAD47_SEL_I(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 4) | ((REG32(ADR_PAD47)) & 0xffffffcf))
+#define SET_PAD47_OD(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 8) | ((REG32(ADR_PAD47)) & 0xfffffeff))
+#define SET_PAD47_SEL_O(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 12) | ((REG32(ADR_PAD47)) & 0xffffcfff))
+#define SET_PAD47_SEL_OE(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 20) | ((REG32(ADR_PAD47)) & 0xffefffff))
+#define SET_GPIO_9_ID(_VAL_) (REG32(ADR_PAD47)) = (((_VAL_) << 28) | ((REG32(ADR_PAD47)) & 0xefffffff))
+#define SET_PAD48_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 0) | ((REG32(ADR_PAD48)) & 0xfffffffe))
+#define SET_PAD48_PE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 1) | ((REG32(ADR_PAD48)) & 0xfffffffd))
+#define SET_PAD48_DS(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 2) | ((REG32(ADR_PAD48)) & 0xfffffffb))
+#define SET_PAD48_IE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 3) | ((REG32(ADR_PAD48)) & 0xfffffff7))
+#define SET_PAD48_SEL_I(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 4) | ((REG32(ADR_PAD48)) & 0xffffff8f))
+#define SET_PAD48_OD(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 8) | ((REG32(ADR_PAD48)) & 0xfffffeff))
+#define SET_PAD48_PE_SEL(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 11) | ((REG32(ADR_PAD48)) & 0xfffff7ff))
+#define SET_PAD48_SEL_O(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 12) | ((REG32(ADR_PAD48)) & 0xffffcfff))
+#define SET_PAD48_SEL_OE(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 20) | ((REG32(ADR_PAD48)) & 0xffefffff))
+#define SET_GPIO_10_ID(_VAL_) (REG32(ADR_PAD48)) = (((_VAL_) << 28) | ((REG32(ADR_PAD48)) & 0xefffffff))
+#define SET_PAD49_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 0) | ((REG32(ADR_PAD49)) & 0xfffffffe))
+#define SET_PAD49_PE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 1) | ((REG32(ADR_PAD49)) & 0xfffffffd))
+#define SET_PAD49_DS(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 2) | ((REG32(ADR_PAD49)) & 0xfffffffb))
+#define SET_PAD49_IE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 3) | ((REG32(ADR_PAD49)) & 0xfffffff7))
+#define SET_PAD49_SEL_I(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 4) | ((REG32(ADR_PAD49)) & 0xffffff8f))
+#define SET_PAD49_OD(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 8) | ((REG32(ADR_PAD49)) & 0xfffffeff))
+#define SET_PAD49_SEL_O(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 12) | ((REG32(ADR_PAD49)) & 0xffffcfff))
+#define SET_PAD49_SEL_OE(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 20) | ((REG32(ADR_PAD49)) & 0xffefffff))
+#define SET_GPIO_11_ID(_VAL_) (REG32(ADR_PAD49)) = (((_VAL_) << 28) | ((REG32(ADR_PAD49)) & 0xefffffff))
+#define SET_PAD50_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 0) | ((REG32(ADR_PAD50)) & 0xfffffffe))
+#define SET_PAD50_PE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 1) | ((REG32(ADR_PAD50)) & 0xfffffffd))
+#define SET_PAD50_DS(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 2) | ((REG32(ADR_PAD50)) & 0xfffffffb))
+#define SET_PAD50_IE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 3) | ((REG32(ADR_PAD50)) & 0xfffffff7))
+#define SET_PAD50_SEL_I(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 4) | ((REG32(ADR_PAD50)) & 0xffffff8f))
+#define SET_PAD50_OD(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 8) | ((REG32(ADR_PAD50)) & 0xfffffeff))
+#define SET_PAD50_SEL_O(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 12) | ((REG32(ADR_PAD50)) & 0xffffcfff))
+#define SET_PAD50_SEL_OE(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 20) | ((REG32(ADR_PAD50)) & 0xffefffff))
+#define SET_GPIO_12_ID(_VAL_) (REG32(ADR_PAD50)) = (((_VAL_) << 28) | ((REG32(ADR_PAD50)) & 0xefffffff))
+#define SET_PAD51_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 0) | ((REG32(ADR_PAD51)) & 0xfffffffe))
+#define SET_PAD51_PE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 1) | ((REG32(ADR_PAD51)) & 0xfffffffd))
+#define SET_PAD51_DS(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 2) | ((REG32(ADR_PAD51)) & 0xfffffffb))
+#define SET_PAD51_IE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 3) | ((REG32(ADR_PAD51)) & 0xfffffff7))
+#define SET_PAD51_SEL_I(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 4) | ((REG32(ADR_PAD51)) & 0xffffffcf))
+#define SET_PAD51_OD(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 8) | ((REG32(ADR_PAD51)) & 0xfffffeff))
+#define SET_PAD51_SEL_O(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 12) | ((REG32(ADR_PAD51)) & 0xffffefff))
+#define SET_PAD51_SEL_OE(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 20) | ((REG32(ADR_PAD51)) & 0xffefffff))
+#define SET_GPIO_13_ID(_VAL_) (REG32(ADR_PAD51)) = (((_VAL_) << 28) | ((REG32(ADR_PAD51)) & 0xefffffff))
+#define SET_PAD52_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 0) | ((REG32(ADR_PAD52)) & 0xfffffffe))
+#define SET_PAD52_PE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 1) | ((REG32(ADR_PAD52)) & 0xfffffffd))
+#define SET_PAD52_DS(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 2) | ((REG32(ADR_PAD52)) & 0xfffffffb))
+#define SET_PAD52_SEL_I(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 4) | ((REG32(ADR_PAD52)) & 0xffffffcf))
+#define SET_PAD52_OD(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 8) | ((REG32(ADR_PAD52)) & 0xfffffeff))
+#define SET_PAD52_SEL_O(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 12) | ((REG32(ADR_PAD52)) & 0xffffefff))
+#define SET_PAD52_SEL_OE(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 20) | ((REG32(ADR_PAD52)) & 0xffefffff))
+#define SET_GPIO_14_ID(_VAL_) (REG32(ADR_PAD52)) = (((_VAL_) << 28) | ((REG32(ADR_PAD52)) & 0xefffffff))
+#define SET_PAD53_OE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 0) | ((REG32(ADR_PAD53)) & 0xfffffffe))
+#define SET_PAD53_PE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 1) | ((REG32(ADR_PAD53)) & 0xfffffffd))
+#define SET_PAD53_DS(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 2) | ((REG32(ADR_PAD53)) & 0xfffffffb))
+#define SET_PAD53_IE(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 3) | ((REG32(ADR_PAD53)) & 0xfffffff7))
+#define SET_PAD53_SEL_I(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 4) | ((REG32(ADR_PAD53)) & 0xffffffcf))
+#define SET_PAD53_OD(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 8) | ((REG32(ADR_PAD53)) & 0xfffffeff))
+#define SET_PAD53_SEL_O(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 12) | ((REG32(ADR_PAD53)) & 0xffffefff))
+#define SET_JTAG_TMS_ID(_VAL_) (REG32(ADR_PAD53)) = (((_VAL_) << 28) | ((REG32(ADR_PAD53)) & 0xefffffff))
+#define SET_PAD54_OE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 0) | ((REG32(ADR_PAD54)) & 0xfffffffe))
+#define SET_PAD54_PE(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 1) | ((REG32(ADR_PAD54)) & 0xfffffffd))
+#define SET_PAD54_DS(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 2) | ((REG32(ADR_PAD54)) & 0xfffffffb))
+#define SET_PAD54_OD(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 8) | ((REG32(ADR_PAD54)) & 0xfffffeff))
+#define SET_PAD54_SEL_O(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 12) | ((REG32(ADR_PAD54)) & 0xffffcfff))
+#define SET_JTAG_TCK_ID(_VAL_) (REG32(ADR_PAD54)) = (((_VAL_) << 28) | ((REG32(ADR_PAD54)) & 0xefffffff))
+#define SET_PAD56_PE(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 1) | ((REG32(ADR_PAD56)) & 0xfffffffd))
+#define SET_PAD56_DS(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 2) | ((REG32(ADR_PAD56)) & 0xfffffffb))
+#define SET_PAD56_SEL_I(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 4) | ((REG32(ADR_PAD56)) & 0xffffffef))
+#define SET_PAD56_OD(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 8) | ((REG32(ADR_PAD56)) & 0xfffffeff))
+#define SET_JTAG_TDI_ID(_VAL_) (REG32(ADR_PAD56)) = (((_VAL_) << 28) | ((REG32(ADR_PAD56)) & 0xefffffff))
+#define SET_PAD57_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 0) | ((REG32(ADR_PAD57)) & 0xfffffffe))
+#define SET_PAD57_PE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 1) | ((REG32(ADR_PAD57)) & 0xfffffffd))
+#define SET_PAD57_DS(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 2) | ((REG32(ADR_PAD57)) & 0xfffffffb))
+#define SET_PAD57_IE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 3) | ((REG32(ADR_PAD57)) & 0xfffffff7))
+#define SET_PAD57_SEL_I(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 4) | ((REG32(ADR_PAD57)) & 0xffffffcf))
+#define SET_PAD57_OD(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 8) | ((REG32(ADR_PAD57)) & 0xfffffeff))
+#define SET_PAD57_SEL_O(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 12) | ((REG32(ADR_PAD57)) & 0xffffcfff))
+#define SET_PAD57_SEL_OE(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 20) | ((REG32(ADR_PAD57)) & 0xffefffff))
+#define SET_JTAG_TDO_ID(_VAL_) (REG32(ADR_PAD57)) = (((_VAL_) << 28) | ((REG32(ADR_PAD57)) & 0xefffffff))
+#define SET_PAD58_OE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 0) | ((REG32(ADR_PAD58)) & 0xfffffffe))
+#define SET_PAD58_PE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 1) | ((REG32(ADR_PAD58)) & 0xfffffffd))
+#define SET_PAD58_DS(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 2) | ((REG32(ADR_PAD58)) & 0xfffffffb))
+#define SET_PAD58_IE(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 3) | ((REG32(ADR_PAD58)) & 0xfffffff7))
+#define SET_PAD58_SEL_I(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 4) | ((REG32(ADR_PAD58)) & 0xffffffcf))
+#define SET_PAD58_OD(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 8) | ((REG32(ADR_PAD58)) & 0xfffffeff))
+#define SET_PAD58_SEL_O(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 12) | ((REG32(ADR_PAD58)) & 0xffffefff))
+#define SET_TEST_16_ID(_VAL_) (REG32(ADR_PAD58)) = (((_VAL_) << 28) | ((REG32(ADR_PAD58)) & 0xefffffff))
+#define SET_PAD59_OE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 0) | ((REG32(ADR_PAD59)) & 0xfffffffe))
+#define SET_PAD59_PE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 1) | ((REG32(ADR_PAD59)) & 0xfffffffd))
+#define SET_PAD59_DS(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 2) | ((REG32(ADR_PAD59)) & 0xfffffffb))
+#define SET_PAD59_IE(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 3) | ((REG32(ADR_PAD59)) & 0xfffffff7))
+#define SET_PAD59_SEL_I(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 4) | ((REG32(ADR_PAD59)) & 0xffffffcf))
+#define SET_PAD59_OD(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 8) | ((REG32(ADR_PAD59)) & 0xfffffeff))
+#define SET_PAD59_SEL_O(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 12) | ((REG32(ADR_PAD59)) & 0xffffefff))
+#define SET_TEST_17_ID(_VAL_) (REG32(ADR_PAD59)) = (((_VAL_) << 28) | ((REG32(ADR_PAD59)) & 0xefffffff))
+#define SET_PAD60_OE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 0) | ((REG32(ADR_PAD60)) & 0xfffffffe))
+#define SET_PAD60_PE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 1) | ((REG32(ADR_PAD60)) & 0xfffffffd))
+#define SET_PAD60_DS(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 2) | ((REG32(ADR_PAD60)) & 0xfffffffb))
+#define SET_PAD60_IE(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 3) | ((REG32(ADR_PAD60)) & 0xfffffff7))
+#define SET_PAD60_SEL_I(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 4) | ((REG32(ADR_PAD60)) & 0xffffffcf))
+#define SET_PAD60_OD(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 8) | ((REG32(ADR_PAD60)) & 0xfffffeff))
+#define SET_PAD60_SEL_O(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 12) | ((REG32(ADR_PAD60)) & 0xffffefff))
+#define SET_TEST_18_ID(_VAL_) (REG32(ADR_PAD60)) = (((_VAL_) << 28) | ((REG32(ADR_PAD60)) & 0xefffffff))
+#define SET_PAD61_OE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 0) | ((REG32(ADR_PAD61)) & 0xfffffffe))
+#define SET_PAD61_PE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 1) | ((REG32(ADR_PAD61)) & 0xfffffffd))
+#define SET_PAD61_DS(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 2) | ((REG32(ADR_PAD61)) & 0xfffffffb))
+#define SET_PAD61_IE(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 3) | ((REG32(ADR_PAD61)) & 0xfffffff7))
+#define SET_PAD61_SEL_I(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 4) | ((REG32(ADR_PAD61)) & 0xffffffef))
+#define SET_PAD61_OD(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 8) | ((REG32(ADR_PAD61)) & 0xfffffeff))
+#define SET_PAD61_SEL_O(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 12) | ((REG32(ADR_PAD61)) & 0xffffcfff))
+#define SET_TEST_19_ID(_VAL_) (REG32(ADR_PAD61)) = (((_VAL_) << 28) | ((REG32(ADR_PAD61)) & 0xefffffff))
+#define SET_PAD62_OE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 0) | ((REG32(ADR_PAD62)) & 0xfffffffe))
+#define SET_PAD62_PE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 1) | ((REG32(ADR_PAD62)) & 0xfffffffd))
+#define SET_PAD62_DS(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 2) | ((REG32(ADR_PAD62)) & 0xfffffffb))
+#define SET_PAD62_IE(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 3) | ((REG32(ADR_PAD62)) & 0xfffffff7))
+#define SET_PAD62_SEL_I(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 4) | ((REG32(ADR_PAD62)) & 0xffffffef))
+#define SET_PAD62_OD(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 8) | ((REG32(ADR_PAD62)) & 0xfffffeff))
+#define SET_PAD62_SEL_O(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 12) | ((REG32(ADR_PAD62)) & 0xffffefff))
+#define SET_TEST_20_ID(_VAL_) (REG32(ADR_PAD62)) = (((_VAL_) << 28) | ((REG32(ADR_PAD62)) & 0xefffffff))
+#define SET_PAD64_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 0) | ((REG32(ADR_PAD64)) & 0xfffffffe))
+#define SET_PAD64_PE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 1) | ((REG32(ADR_PAD64)) & 0xfffffffd))
+#define SET_PAD64_DS(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 2) | ((REG32(ADR_PAD64)) & 0xfffffffb))
+#define SET_PAD64_IE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 3) | ((REG32(ADR_PAD64)) & 0xfffffff7))
+#define SET_PAD64_SEL_I(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 4) | ((REG32(ADR_PAD64)) & 0xffffff8f))
+#define SET_PAD64_OD(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 8) | ((REG32(ADR_PAD64)) & 0xfffffeff))
+#define SET_PAD64_SEL_O(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 12) | ((REG32(ADR_PAD64)) & 0xffffcfff))
+#define SET_PAD64_SEL_OE(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 20) | ((REG32(ADR_PAD64)) & 0xffefffff))
+#define SET_GPIO_15_IP_ID(_VAL_) (REG32(ADR_PAD64)) = (((_VAL_) << 28) | ((REG32(ADR_PAD64)) & 0xefffffff))
+#define SET_PAD65_OE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 0) | ((REG32(ADR_PAD65)) & 0xfffffffe))
+#define SET_PAD65_PE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 1) | ((REG32(ADR_PAD65)) & 0xfffffffd))
+#define SET_PAD65_DS(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 2) | ((REG32(ADR_PAD65)) & 0xfffffffb))
+#define SET_PAD65_IE(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 3) | ((REG32(ADR_PAD65)) & 0xfffffff7))
+#define SET_PAD65_SEL_I(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 4) | ((REG32(ADR_PAD65)) & 0xffffff8f))
+#define SET_PAD65_OD(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 8) | ((REG32(ADR_PAD65)) & 0xfffffeff))
+#define SET_PAD65_SEL_O(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 12) | ((REG32(ADR_PAD65)) & 0xffffefff))
+#define SET_GPIO_TEST_7_IN_ID(_VAL_) (REG32(ADR_PAD65)) = (((_VAL_) << 28) | ((REG32(ADR_PAD65)) & 0xefffffff))
+#define SET_PAD66_OE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 0) | ((REG32(ADR_PAD66)) & 0xfffffffe))
+#define SET_PAD66_PE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 1) | ((REG32(ADR_PAD66)) & 0xfffffffd))
+#define SET_PAD66_DS(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 2) | ((REG32(ADR_PAD66)) & 0xfffffffb))
+#define SET_PAD66_IE(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 3) | ((REG32(ADR_PAD66)) & 0xfffffff7))
+#define SET_PAD66_SEL_I(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 4) | ((REG32(ADR_PAD66)) & 0xffffffcf))
+#define SET_PAD66_OD(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 8) | ((REG32(ADR_PAD66)) & 0xfffffeff))
+#define SET_PAD66_SEL_O(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 12) | ((REG32(ADR_PAD66)) & 0xffffcfff))
+#define SET_GPIO_17_QP_ID(_VAL_) (REG32(ADR_PAD66)) = (((_VAL_) << 28) | ((REG32(ADR_PAD66)) & 0xefffffff))
+#define SET_PAD68_OE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 0) | ((REG32(ADR_PAD68)) & 0xfffffffe))
+#define SET_PAD68_PE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 1) | ((REG32(ADR_PAD68)) & 0xfffffffd))
+#define SET_PAD68_DS(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 2) | ((REG32(ADR_PAD68)) & 0xfffffffb))
+#define SET_PAD68_IE(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 3) | ((REG32(ADR_PAD68)) & 0xfffffff7))
+#define SET_PAD68_OD(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 8) | ((REG32(ADR_PAD68)) & 0xfffffeff))
+#define SET_PAD68_SEL_O(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 12) | ((REG32(ADR_PAD68)) & 0xffffefff))
+#define SET_GPIO_19_ID(_VAL_) (REG32(ADR_PAD68)) = (((_VAL_) << 28) | ((REG32(ADR_PAD68)) & 0xefffffff))
+#define SET_PAD67_OE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 0) | ((REG32(ADR_PAD67)) & 0xfffffffe))
+#define SET_PAD67_PE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 1) | ((REG32(ADR_PAD67)) & 0xfffffffd))
+#define SET_PAD67_DS(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 2) | ((REG32(ADR_PAD67)) & 0xfffffffb))
+#define SET_PAD67_IE(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 3) | ((REG32(ADR_PAD67)) & 0xfffffff7))
+#define SET_PAD67_SEL_I(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 4) | ((REG32(ADR_PAD67)) & 0xffffff8f))
+#define SET_PAD67_OD(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 8) | ((REG32(ADR_PAD67)) & 0xfffffeff))
+#define SET_PAD67_SEL_O(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 12) | ((REG32(ADR_PAD67)) & 0xffffcfff))
+#define SET_GPIO_TEST_8_QN_ID(_VAL_) (REG32(ADR_PAD67)) = (((_VAL_) << 28) | ((REG32(ADR_PAD67)) & 0xefffffff))
+#define SET_PAD69_OE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 0) | ((REG32(ADR_PAD69)) & 0xfffffffe))
+#define SET_PAD69_PE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 1) | ((REG32(ADR_PAD69)) & 0xfffffffd))
+#define SET_PAD69_DS(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 2) | ((REG32(ADR_PAD69)) & 0xfffffffb))
+#define SET_PAD69_IE(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 3) | ((REG32(ADR_PAD69)) & 0xfffffff7))
+#define SET_PAD69_SEL_I(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 4) | ((REG32(ADR_PAD69)) & 0xffffffcf))
+#define SET_PAD69_OD(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 8) | ((REG32(ADR_PAD69)) & 0xfffffeff))
+#define SET_PAD69_SEL_O(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 12) | ((REG32(ADR_PAD69)) & 0xffffefff))
+#define SET_STRAP2(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 27) | ((REG32(ADR_PAD69)) & 0xf7ffffff))
+#define SET_GPIO_20_ID(_VAL_) (REG32(ADR_PAD69)) = (((_VAL_) << 28) | ((REG32(ADR_PAD69)) & 0xefffffff))
+#define SET_PAD70_OE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 0) | ((REG32(ADR_PAD70)) & 0xfffffffe))
+#define SET_PAD70_PE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 1) | ((REG32(ADR_PAD70)) & 0xfffffffd))
+#define SET_PAD70_DS(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 2) | ((REG32(ADR_PAD70)) & 0xfffffffb))
+#define SET_PAD70_IE(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 3) | ((REG32(ADR_PAD70)) & 0xfffffff7))
+#define SET_PAD70_SEL_I(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 4) | ((REG32(ADR_PAD70)) & 0xffffffcf))
+#define SET_PAD70_OD(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 8) | ((REG32(ADR_PAD70)) & 0xfffffeff))
+#define SET_PAD70_SEL_O(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 12) | ((REG32(ADR_PAD70)) & 0xffff8fff))
+#define SET_GPIO_21_ID(_VAL_) (REG32(ADR_PAD70)) = (((_VAL_) << 28) | ((REG32(ADR_PAD70)) & 0xefffffff))
+#define SET_PAD231_OE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 0) | ((REG32(ADR_PAD231)) & 0xfffffffe))
+#define SET_PAD231_PE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 1) | ((REG32(ADR_PAD231)) & 0xfffffffd))
+#define SET_PAD231_DS(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 2) | ((REG32(ADR_PAD231)) & 0xfffffffb))
+#define SET_PAD231_IE(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 3) | ((REG32(ADR_PAD231)) & 0xfffffff7))
+#define SET_PAD231_OD(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 8) | ((REG32(ADR_PAD231)) & 0xfffffeff))
+#define SET_PIN_40_OR_56_ID(_VAL_) (REG32(ADR_PAD231)) = (((_VAL_) << 28) | ((REG32(ADR_PAD231)) & 0xefffffff))
+#define SET_MP_PHY2RX_DATA__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffe))
+#define SET_MP_PHY2RX_DATA__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffd))
+#define SET_MP_TX_FF_RPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 2) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffffb))
+#define SET_MP_RX_FF_WPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 3) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffff7))
+#define SET_MP_RX_FF_WPTR__1_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 4) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffef))
+#define SET_MP_RX_FF_WPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 5) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffdf))
+#define SET_MP_PHY2RX_DATA__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 6) | ((REG32(ADR_PIN_SEL_0)) & 0xffffffbf))
+#define SET_MP_PHY2RX_DATA__4_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 7) | ((REG32(ADR_PIN_SEL_0)) & 0xffffff7f))
+#define SET_I2CM_SDA_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 8) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffcff))
+#define SET_CRYSTAL_OUT_REQ_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 10) | ((REG32(ADR_PIN_SEL_0)) & 0xfffffbff))
+#define SET_MP_PHY2RX_DATA__5_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 11) | ((REG32(ADR_PIN_SEL_0)) & 0xfffff7ff))
+#define SET_MP_PHY2RX_DATA__3_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 12) | ((REG32(ADR_PIN_SEL_0)) & 0xffffefff))
+#define SET_UART_RXD_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 13) | ((REG32(ADR_PIN_SEL_0)) & 0xffff9fff))
+#define SET_MP_PHY2RX_DATA__6_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 15) | ((REG32(ADR_PIN_SEL_0)) & 0xffff7fff))
+#define SET_DAT_UART_NCTS_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 16) | ((REG32(ADR_PIN_SEL_0)) & 0xfffeffff))
+#define SET_GPIO_LOG_STOP_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 17) | ((REG32(ADR_PIN_SEL_0)) & 0xfff1ffff))
+#define SET_MP_TX_FF_RPTR__0_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 20) | ((REG32(ADR_PIN_SEL_0)) & 0xffefffff))
+#define SET_MP_PHY_RX_WRST_N_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 21) | ((REG32(ADR_PIN_SEL_0)) & 0xffdfffff))
+#define SET_EXT_32K_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 22) | ((REG32(ADR_PIN_SEL_0)) & 0xff3fffff))
+#define SET_MP_PHY2RX_DATA__7_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 24) | ((REG32(ADR_PIN_SEL_0)) & 0xfeffffff))
+#define SET_MP_TX_FF_RPTR__2_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 25) | ((REG32(ADR_PIN_SEL_0)) & 0xfdffffff))
+#define SET_PMUINT_WAKE_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 26) | ((REG32(ADR_PIN_SEL_0)) & 0xe3ffffff))
+#define SET_I2CM_SCL_ID_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 29) | ((REG32(ADR_PIN_SEL_0)) & 0xdfffffff))
+#define SET_MP_MRX_RX_EN_SEL(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 30) | ((REG32(ADR_PIN_SEL_0)) & 0xbfffffff))
+#define SET_DAT_UART_RXD_SEL_0(_VAL_) (REG32(ADR_PIN_SEL_0)) = (((_VAL_) << 31) | ((REG32(ADR_PIN_SEL_0)) & 0x7fffffff))
+#define SET_DAT_UART_RXD_SEL_1(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 0) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffe))
+#define SET_SPI_DI_SEL(_VAL_) (REG32(ADR_PIN_SEL_1)) = (((_VAL_) << 1) | ((REG32(ADR_PIN_SEL_1)) & 0xfffffffd))
+#define SET_IO_PORT_REG(_VAL_) (REG32(ADR_IO_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_PORT_REG)) & 0xfffe0000))
+#define SET_MASK_RX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffe))
+#define SET_MASK_TX_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffd))
+#define SET_MASK_SOC_SYSTEM_INT(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffffb))
+#define SET_EDCA0_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_MASK_REG)) & 0xfffffff7))
+#define SET_EDCA1_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffef))
+#define SET_EDCA2_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffdf))
+#define SET_EDCA3_LOW_THR_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_MASK_REG)) & 0xffffffbf))
+#define SET_TX_LIMIT_INT_MASK(_VAL_) (REG32(ADR_INT_MASK_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_MASK_REG)) & 0xffffff7f))
+#define SET_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffe))
+#define SET_TX_COMPLETE_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffd))
+#define SET_SOC_SYSTEM_INT_STATUS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffffb))
+#define SET_EDCA0_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffff7))
+#define SET_EDCA1_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffef))
+#define SET_EDCA2_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffdf))
+#define SET_EDCA3_LOW_THR_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffffbf))
+#define SET_TX_LIMIT_INT_STS(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_STATUS_REG)) & 0xffffff7f))
+#define SET_HOST_TRIGGERED_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffeff))
+#define SET_HOST_TRIGGERED_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 9) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffdff))
+#define SET_SOC_TRIGGER_RX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 10) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffffbff))
+#define SET_SOC_TRIGGER_TX_INT(_VAL_) (REG32(ADR_INT_STATUS_REG)) = (((_VAL_) << 11) | ((REG32(ADR_INT_STATUS_REG)) & 0xfffff7ff))
+#define SET_RDY_FOR_TX_RX(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffe))
+#define SET_RDY_FOR_FW_DOWNLOAD(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 1) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffd))
+#define SET_ILLEGAL_CMD_RESP_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 2) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffffb))
+#define SET_SDIO_TRX_DATA_SEQUENCE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 3) | ((REG32(ADR_FN1_STATUS_REG)) & 0xfffffff7))
+#define SET_GPIO_INT_TRIGGER_OPTION(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 4) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffffef))
+#define SET_TRIGGER_FUNCTION_SETTING(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 5) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff9f))
+#define SET_CMD52_ABORT_RESPONSE(_VAL_) (REG32(ADR_FN1_STATUS_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FN1_STATUS_REG)) & 0xffffff7f))
+#define SET_RX_PACKET_LENGTH(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xffff0000))
+#define SET_CARD_FW_DL_STATUS(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 16) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xff00ffff))
+#define SET_TX_RX_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 24) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfeffffff))
+#define SET_SDIO_LOOP_BACK_TEST(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 25) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xfdffffff))
+#define SET_CMD52_ABORT_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 28) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xefffffff))
+#define SET_CMD52_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 29) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xdfffffff))
+#define SET_SDIO_PARTIAL_RESET_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 30) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0xbfffffff))
+#define SET_SDIO_ALL_RESE_ACTIVE(_VAL_) (REG32(ADR_CARD_PKT_STATUS_TEST)) = (((_VAL_) << 31) | ((REG32(ADR_CARD_PKT_STATUS_TEST)) & 0x7fffffff))
+#define SET_RX_PACKET_LENGTH2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xffff0000))
+#define SET_RX_INT1(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffeffff))
+#define SET_TX_DONE(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffdffff))
+#define SET_HCI_TRX_FINISH(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfffbffff))
+#define SET_ALLOCATE_STATUS(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xfff7ffff))
+#define SET_HCI_INPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xff0fffff))
+#define SET_HCI_OUTPUT_FF_CNT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xe0ffffff))
+#define SET_AHB_HANG4(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 29) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xdfffffff))
+#define SET_HCI_IN_QUE_EMPTY(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 30) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0xbfffffff))
+#define SET_SYSTEM_INT(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REG)) = (((_VAL_) << 31) | ((REG32(ADR_SYSTEM_INFORMATION_REG)) & 0x7fffffff))
+#define SET_CARD_RCA_REG(_VAL_) (REG32(ADR_CARD_RCA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CARD_RCA_REG)) & 0xffff0000))
+#define SET_SDIO_FIFO_WR_THLD_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_THLD_REG)) & 0xfffffe00))
+#define SET_SDIO_FIFO_WR_LIMIT_REG(_VAL_) (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) & 0xfffffe00))
+#define SET_SDIO_TX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
+#define SET_SDIO_THLD_FOR_CMD53RD_REG(_VAL_) (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) & 0xfffffe00))
+#define SET_SDIO_RX_DATA_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) & 0xfffffe00))
+#define SET_START_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffffff00))
+#define SET_END_BYTE_VALUE(_VAL_) (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LOG_START_END_DATA_REG)) & 0xffff00ff))
+#define SET_SDIO_BYTE_MODE_BATCH_SIZE_REG(_VAL_) (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0xffffff00))
+#define SET_SDIO_LAST_CMD_INDEX_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffffffc0))
+#define SET_SDIO_LAST_CMD_CRC_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) & 0xffff80ff))
+#define SET_SDIO_LAST_CMD_ARG_REG(_VAL_) (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_LAST_CMD_ARG_REG)) & 0x00000000))
+#define SET_SDIO_BUS_STATE_REG(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0xffffffe0))
+#define SET_SDIO_BUSY_LONG_CNT(_VAL_) (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) & 0x0000ffff))
+#define SET_SDIO_CARD_STATUS_REG(_VAL_) (REG32(ADR_SDIO_CARD_STATUS_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0x00000000))
+#define SET_R5_RESPONSE_FLAG(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 0) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xffffff00))
+#define SET_RESP_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 8) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffeff))
+#define SET_DAT_OUT_EDGE(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 9) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffffdff))
+#define SET_MCU_TO_SDIO_INFO_MASK(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 16) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffeffff))
+#define SET_INT_THROUGH_PIN(_VAL_) (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (((_VAL_) << 17) | ((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0xfffdffff))
+#define SET_WRITE_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffffff00))
+#define SET_WRITE_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 8) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xffff00ff))
+#define SET_READ_DATA(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0xff00ffff))
+#define SET_READ_ADDRESS(_VAL_) (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (((_VAL_) << 24) | ((REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) & 0x00ffffff))
+#define SET_FN1_DMA_START_ADDR_REG(_VAL_) (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0x00000000))
+#define SET_SDIO_TO_MCU_INFO(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffff00))
+#define SET_SDIO_PARTIAL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffeff))
+#define SET_SDIO_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffdff))
+#define SET_PERI_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffffbff))
+#define SET_MAC_ALL_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xfffff7ff))
+#define SET_AHB_BRIDGE_RESET(_VAL_) (REG32(ADR_FN1_INT_CTRL_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_FN1_INT_CTRL_RESET)) & 0xffffefff))
+#define SET_IO_REG_PORT_REG(_VAL_) (REG32(ADR_IO_REG_PORT_REG)) = (((_VAL_) << 0) | ((REG32(ADR_IO_REG_PORT_REG)) & 0xfffe0000))
+#define SET_SDIO_FIFO_EMPTY_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0xffff0000))
+#define SET_SDIO_FIFO_FULL_CNT(_VAL_) (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_FIFO_ERROR_CNT)) & 0x0000ffff))
+#define SET_SDIO_CRC7_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0xffff0000))
+#define SET_SDIO_CRC16_ERROR_CNT(_VAL_) (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) & 0x0000ffff))
+#define SET_SDIO_RD_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfffffe00))
+#define SET_SDIO_WR_BLOCK_CNT(_VAL_) (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_BLOCK_CNT_INFO)) & 0xfe00ffff))
+#define SET_CMD52_RD_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xfff0ffff))
+#define SET_CMD52_WR_ABORT_CNT(_VAL_) (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (((_VAL_) << 20) | ((REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) & 0xff0fffff))
+#define SET_SDIO_FIFO_WR_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffffff00))
+#define SET_SDIO_FIFO_RD_PTR_REG(_VAL_) (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) & 0xffff00ff))
+#define SET_SDIO_READ_DATA_CTRL(_VAL_) (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_TIME_OUT_READ_CTRL)) & 0xfffeffff))
+#define SET_TX_SIZE_BEFORE_SHIFT(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffff00))
+#define SET_TX_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffff8ff))
+#define SET_SDIO_TX_ALLOC_STATE(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffffefff))
+#define SET_ALLOCATE_STATUS2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffeffff))
+#define SET_NO_ALLOCATE_SEND_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffdffff))
+#define SET_DOUBLE_ALLOCATE_ERROR(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfffbffff))
+#define SET_TX_DONE_STATUS(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xfff7ffff))
+#define SET_AHB_HANG2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffefffff))
+#define SET_HCI_TRX_FINISH2(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffdfffff))
+#define SET_INTR_RX(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xffbfffff))
+#define SET_HCI_INPUT_QUEUE_FULL(_VAL_) (REG32(ADR_SDIO_TX_ALLOC_REG)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_ALLOC_REG)) & 0xff7fffff))
+#define SET_ALLOCATESTATUS(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffe))
+#define SET_HCI_TRX_FINISH3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffd))
+#define SET_HCI_IN_QUE_EMPTY2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffffb))
+#define SET_MTX_MNG_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xfffffff7))
+#define SET_EDCA0_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffef))
+#define SET_EDCA1_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffdf))
+#define SET_EDCA2_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffffbf))
+#define SET_EDCA3_UPTHOLD_INT(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffffff7f))
+#define SET_TX_PAGE_REMAIN2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xffff00ff))
+#define SET_TX_ID_REMAIN3(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff80ffff))
+#define SET_HCI_OUTPUT_FF_CNT_0(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xff7fffff))
+#define SET_HCI_OUTPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_TX_INFORM)) & 0xf0ffffff))
+#define SET_HCI_INPUT_FF_CNT2(_VAL_) (REG32(ADR_SDIO_TX_INFORM)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_TX_INFORM)) & 0x0fffffff))
+#define SET_F1_BLOCK_SIZE_0_REG(_VAL_) (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (((_VAL_) << 0) | ((REG32(ADR_F1_BLOCK_SIZE_0_REG)) & 0xfffff000))
+#define SET_START_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffffff00))
+#define SET_COMMAND_COUNTER(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0xffff00ff))
+#define SET_CMD_LOG_PART1(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) & 0x0000ffff))
+#define SET_CMD_LOG_PART2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0xff000000))
+#define SET_END_BYTE_VALUE2(_VAL_) (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) & 0x00ffffff))
+#define SET_RX_PACKET_LENGTH3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xffff0000))
+#define SET_RX_INT3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xfffeffff))
+#define SET_TX_ID_REMAIN2(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0xff01ffff))
+#define SET_TX_PAGE_REMAIN3(_VAL_) (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_SYSTEM_INFORMATION_REGISTER)) & 0x00ffffff))
+#define SET_CCCR_00H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_00H_REG)) & 0xffffff00))
+#define SET_CCCR_02H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_00H_REG)) & 0xff00ffff))
+#define SET_CCCR_03H_REG(_VAL_) (REG32(ADR_CCCR_00H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_00H_REG)) & 0x00ffffff))
+#define SET_CCCR_04H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_04H_REG)) & 0xffffff00))
+#define SET_CCCR_05H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_04H_REG)) & 0xffff00ff))
+#define SET_CCCR_06H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 16) | ((REG32(ADR_CCCR_04H_REG)) & 0xfff0ffff))
+#define SET_CCCR_07H_REG(_VAL_) (REG32(ADR_CCCR_04H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_04H_REG)) & 0x00ffffff))
+#define SET_SUPPORT_DIRECT_COMMAND_SDIO(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffe))
+#define SET_SUPPORT_MULTIPLE_BLOCK_TRANSFER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 1) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffd))
+#define SET_SUPPORT_READ_WAIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 2) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffffb))
+#define SET_SUPPORT_BUS_CONTROL(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 3) | ((REG32(ADR_CCCR_08H_REG)) & 0xfffffff7))
+#define SET_SUPPORT_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 4) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffef))
+#define SET_ENABLE_BLOCK_GAP_INTERRUPT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 5) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffdf))
+#define SET_LOW_SPEED_CARD(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffffbf))
+#define SET_LOW_SPEED_CARD_4BIT(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_CCCR_08H_REG)) & 0xffffff7f))
+#define SET_COMMON_CIS_PONTER(_VAL_) (REG32(ADR_CCCR_08H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_CCCR_08H_REG)) & 0xfe0000ff))
+#define SET_SUPPORT_HIGH_SPEED(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 24) | ((REG32(ADR_CCCR_13H_REG)) & 0xfeffffff))
+#define SET_BSS(_VAL_) (REG32(ADR_CCCR_13H_REG)) = (((_VAL_) << 25) | ((REG32(ADR_CCCR_13H_REG)) & 0xf1ffffff))
+#define SET_FBR_100H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 0) | ((REG32(ADR_FBR_100H_REG)) & 0xfffffff0))
+#define SET_CSASUPPORT(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 6) | ((REG32(ADR_FBR_100H_REG)) & 0xffffffbf))
+#define SET_ENABLECSA(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 7) | ((REG32(ADR_FBR_100H_REG)) & 0xffffff7f))
+#define SET_FBR_101H_REG(_VAL_) (REG32(ADR_FBR_100H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_100H_REG)) & 0xffff00ff))
+#define SET_FBR_109H_REG(_VAL_) (REG32(ADR_FBR_109H_REG)) = (((_VAL_) << 8) | ((REG32(ADR_FBR_109H_REG)) & 0xfe0000ff))
+#define SET_F0_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0x00000000))
+#define SET_F0_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_31_0(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_63_32(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_95_64(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_127_96(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_159_128(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_191_160(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_223_192(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_255_224(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_287_256(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_319_288(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_351_320(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_383_352(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_415_384(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_447_416(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_479_448(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0x00000000))
+#define SET_F1_CIS_CONTENT_REG_511_480(_VAL_) (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (((_VAL_) << 0) | ((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0x00000000))
+#define SET_SPI_MODE(_VAL_) (REG32(ADR_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_MODE)) & 0x00000000))
+#define SET_RX_QUOTA(_VAL_) (REG32(ADR_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_QUOTA)) & 0xffff0000))
+#define SET_CONDI_NUM(_VAL_) (REG32(ADR_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_CONDITION_NUMBER)) & 0xffffff00))
+#define SET_HOST_PATH(_VAL_) (REG32(ADR_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_HOST_PATH)) & 0xfffffffe))
+#define SET_TX_SEG(_VAL_) (REG32(ADR_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEG)) & 0x00000000))
+#define SET_BRST_MODE(_VAL_) (REG32(ADR_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_BURST_MODE)) & 0xfffffffe))
+#define SET_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000))
+#define SET_CSN_INTER(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
+#define SET_BACK_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000))
+#define SET_FRONT_DLY(_VAL_) (REG32(ADR_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
+#define SET_RX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SPI_STS)) & 0xfffffffd))
+#define SET_RX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SPI_STS)) & 0xfffffffb))
+#define SET_TX_FIFO_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SPI_STS)) & 0xfffffff7))
+#define SET_TX_HOST_FAIL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SPI_STS)) & 0xffffffef))
+#define SET_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SPI_STS)) & 0xffffffdf))
+#define SET_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SPI_STS)) & 0xffffffbf))
+#define SET_RDATA_RDY(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SPI_STS)) & 0xffffff7f))
+#define SET_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SPI_STS)) & 0xfffffeff))
+#define SET_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SPI_STS)) & 0xfffffdff))
+#define SET_RX_LEN(_VAL_) (REG32(ADR_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_STS)) & 0x0000ffff))
+#define SET_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffff8))
+#define SET_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ALLOC_SET)) & 0xfffffeff))
+#define SET_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ALLOC)) & 0xffffff00))
+#define SET_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT)) & 0xffff0000))
+#define SET_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT)) & 0x0000ffff))
+#define SET_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT2)) & 0xffff0000))
+#define SET_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT2)) & 0xfffeffff))
+#define SET_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT2)) & 0xfffdffff))
+#define SET_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT2)) & 0xfffbffff))
+#define SET_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT3)) & 0xffff0000))
+#define SET_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT3)) & 0x0000ffff))
+#define SET_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CNT4)) & 0xffff0000))
+#define SET_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_CNT4)) & 0xfffeffff))
+#define SET_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_CNT4)) & 0xfffdffff))
+#define SET_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_CNT4)) & 0xfffbffff))
+#define SET_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_CNT4)) & 0xfff7ffff))
+#define SET_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_CNT4)) & 0xff8fffff))
+#define SET_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_CNT4)) & 0xf8ffffff))
+#define SET_RX_RDY(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_TAG)) & 0xfffffffe))
+#define SET_SDIO_SYS_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_TAG)) & 0xfffffffb))
+#define SET_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_INT_TAG)) & 0xfffffff7))
+#define SET_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_INT_TAG)) & 0xffffffef))
+#define SET_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_INT_TAG)) & 0xffffffdf))
+#define SET_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_INT_TAG)) & 0xffffffbf))
+#define SET_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_INT_TAG)) & 0xffffff7f))
+#define SET_SPI_FN1(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_INT_TAG)) & 0xffff80ff))
+#define SET_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_INT_TAG)) & 0xffff7fff))
+#define SET_SPI_HOST_MASK(_VAL_) (REG32(ADR_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_INT_TAG)) & 0xff00ffff))
+#define SET_I2CM_INT_WDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN)) & 0xfffffffe))
+#define SET_I2CM_INT_RDONE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 1) | ((REG32(ADR_I2CM_EN)) & 0xfffffffd))
+#define SET_I2CM_IDLE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 2) | ((REG32(ADR_I2CM_EN)) & 0xfffffffb))
+#define SET_I2CM_INT_MISMATCH(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 3) | ((REG32(ADR_I2CM_EN)) & 0xfffffff7))
+#define SET_I2CM_PSCL(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 4) | ((REG32(ADR_I2CM_EN)) & 0xffffc00f))
+#define SET_I2CM_MANUAL_MODE(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN)) & 0xfffeffff))
+#define SET_I2CM_INT_WDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN)) & 0xfffdffff))
+#define SET_I2CM_INT_RDATA_NEED(_VAL_) (REG32(ADR_I2CM_EN)) = (((_VAL_) << 18) | ((REG32(ADR_I2CM_EN)) & 0xfffbffff))
+#define SET_I2CM_DEV_A(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_DEV_A)) & 0xfffffc00))
+#define SET_I2CM_DEV_A10B(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 14) | ((REG32(ADR_I2CM_DEV_A)) & 0xffffbfff))
+#define SET_I2CM_RX(_VAL_) (REG32(ADR_I2CM_DEV_A)) = (((_VAL_) << 15) | ((REG32(ADR_I2CM_DEV_A)) & 0xffff7fff))
+#define SET_I2CM_LEN(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_LEN)) & 0xffff0000))
+#define SET_I2CM_T_LEFT(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_LEN)) & 0xfff8ffff))
+#define SET_I2CM_R_GET(_VAL_) (REG32(ADR_I2CM_LEN)) = (((_VAL_) << 24) | ((REG32(ADR_I2CM_LEN)) & 0xf8ffffff))
+#define SET_I2CM_WDAT(_VAL_) (REG32(ADR_I2CM_WDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_WDAT)) & 0x00000000))
+#define SET_I2CM_RDAT(_VAL_) (REG32(ADR_I2CM_RDAT)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_RDAT)) & 0x00000000))
+#define SET_I2CM_SR_LEN(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 0) | ((REG32(ADR_I2CM_EN_2)) & 0xffff0000))
+#define SET_I2CM_SR_RX(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 16) | ((REG32(ADR_I2CM_EN_2)) & 0xfffeffff))
+#define SET_I2CM_REPEAT_START(_VAL_) (REG32(ADR_I2CM_EN_2)) = (((_VAL_) << 17) | ((REG32(ADR_I2CM_EN_2)) & 0xfffdffff))
+#define SET_UART_DATA(_VAL_) (REG32(ADR_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_UART_DATA)) & 0xffffff00))
+#define SET_DATA_RDY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_UART_IER)) & 0xfffffffe))
+#define SET_THR_EMPTY_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_UART_IER)) & 0xfffffffd))
+#define SET_RX_LINESTS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_UART_IER)) & 0xfffffffb))
+#define SET_MDM_STS_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_UART_IER)) & 0xfffffff7))
+#define SET_DMA_RXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_UART_IER)) & 0xffffffbf))
+#define SET_DMA_TXEND_IE(_VAL_) (REG32(ADR_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_UART_IER)) & 0xffffff7f))
+#define SET_FIFO_EN(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_FCR)) & 0xfffffffe))
+#define SET_RXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_FCR)) & 0xfffffffd))
+#define SET_TXFIFO_RST(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_FCR)) & 0xfffffffb))
+#define SET_DMA_MODE(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_FCR)) & 0xfffffff7))
+#define SET_EN_AUTO_RTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_FCR)) & 0xffffffef))
+#define SET_EN_AUTO_CTS(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_FCR)) & 0xffffffdf))
+#define SET_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_FCR)) & 0xffffff3f))
+#define SET_WORD_LEN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LCR)) & 0xfffffffc))
+#define SET_STOP_BIT(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LCR)) & 0xfffffffb))
+#define SET_PARITY_EN(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LCR)) & 0xfffffff7))
+#define SET_EVEN_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LCR)) & 0xffffffef))
+#define SET_FORCE_PARITY(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LCR)) & 0xffffffdf))
+#define SET_SET_BREAK(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LCR)) & 0xffffffbf))
+#define SET_DLAB(_VAL_) (REG32(ADR_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LCR)) & 0xffffff7f))
+#define SET_DTR(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MCR)) & 0xfffffffe))
+#define SET_RTS(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MCR)) & 0xfffffffd))
+#define SET_OUT_1(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MCR)) & 0xfffffffb))
+#define SET_OUT_2(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MCR)) & 0xfffffff7))
+#define SET_LOOP_BACK(_VAL_) (REG32(ADR_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MCR)) & 0xffffffef))
+#define SET_DATA_RDY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_LSR)) & 0xfffffffe))
+#define SET_OVERRUN_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_LSR)) & 0xfffffffd))
+#define SET_PARITY_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_LSR)) & 0xfffffffb))
+#define SET_FRAMING_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_LSR)) & 0xfffffff7))
+#define SET_BREAK_INT(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_LSR)) & 0xffffffef))
+#define SET_THR_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_LSR)) & 0xffffffdf))
+#define SET_TX_EMPTY(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_LSR)) & 0xffffffbf))
+#define SET_FIFODATA_ERR(_VAL_) (REG32(ADR_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_LSR)) & 0xffffff7f))
+#define SET_DELTA_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_MSR)) & 0xfffffffe))
+#define SET_DELTA_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_UART_MSR)) & 0xfffffffd))
+#define SET_TRAILEDGE_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_UART_MSR)) & 0xfffffffb))
+#define SET_DELTA_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_UART_MSR)) & 0xfffffff7))
+#define SET_CTS(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_MSR)) & 0xffffffef))
+#define SET_DSR(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_UART_MSR)) & 0xffffffdf))
+#define SET_RI(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_MSR)) & 0xffffffbf))
+#define SET_CD(_VAL_) (REG32(ADR_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_UART_MSR)) & 0xffffff7f))
+#define SET_BRDC_DIV(_VAL_) (REG32(ADR_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_SPR)) & 0xffff0000))
+#define SET_RTHR_L(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_RTHR)) & 0xfffffff0))
+#define SET_RTHR_H(_VAL_) (REG32(ADR_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_UART_RTHR)) & 0xffffff0f))
+#define SET_INT_IDCODE(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_UART_ISR)) & 0xfffffff0))
+#define SET_FIFOS_ENABLED(_VAL_) (REG32(ADR_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_UART_ISR)) & 0xffffff3f))
+#define SET_DAT_UART_DATA(_VAL_) (REG32(ADR_DAT_UART_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_DATA)) & 0xffffff00))
+#define SET_DAT_DATA_RDY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffe))
+#define SET_DAT_THR_EMPTY_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffd))
+#define SET_DAT_RX_LINESTS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffffb))
+#define SET_DAT_MDM_STS_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_IER)) & 0xfffffff7))
+#define SET_DAT_DMA_RXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_IER)) & 0xffffffbf))
+#define SET_DAT_DMA_TXEND_IE(_VAL_) (REG32(ADR_DAT_UART_IER)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_IER)) & 0xffffff7f))
+#define SET_DAT_FIFO_EN(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffe))
+#define SET_DAT_RXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffd))
+#define SET_DAT_TXFIFO_RST(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffffb))
+#define SET_DAT_DMA_MODE(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_FCR)) & 0xfffffff7))
+#define SET_DAT_EN_AUTO_RTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffef))
+#define SET_DAT_EN_AUTO_CTS(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffffdf))
+#define SET_DAT_RXFIFO_TRGLVL(_VAL_) (REG32(ADR_DAT_UART_FCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_FCR)) & 0xffffff3f))
+#define SET_DAT_WORD_LEN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffc))
+#define SET_DAT_STOP_BIT(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffffb))
+#define SET_DAT_PARITY_EN(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LCR)) & 0xfffffff7))
+#define SET_DAT_EVEN_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffef))
+#define SET_DAT_FORCE_PARITY(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffdf))
+#define SET_DAT_SET_BREAK(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffffbf))
+#define SET_DAT_DLAB(_VAL_) (REG32(ADR_DAT_UART_LCR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LCR)) & 0xffffff7f))
+#define SET_DAT_DTR(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffe))
+#define SET_DAT_RTS(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffd))
+#define SET_DAT_OUT_1(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffffb))
+#define SET_DAT_OUT_2(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MCR)) & 0xfffffff7))
+#define SET_DAT_LOOP_BACK(_VAL_) (REG32(ADR_DAT_UART_MCR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MCR)) & 0xffffffef))
+#define SET_DAT_DATA_RDY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffe))
+#define SET_DAT_OVERRUN_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffd))
+#define SET_DAT_PARITY_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffffb))
+#define SET_DAT_FRAMING_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_LSR)) & 0xfffffff7))
+#define SET_DAT_BREAK_INT(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffef))
+#define SET_DAT_THR_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffdf))
+#define SET_DAT_TX_EMPTY(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffffbf))
+#define SET_DAT_FIFODATA_ERR(_VAL_) (REG32(ADR_DAT_UART_LSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_LSR)) & 0xffffff7f))
+#define SET_DAT_DELTA_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffe))
+#define SET_DAT_DELTA_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 1) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffd))
+#define SET_DAT_TRAILEDGE_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 2) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffffb))
+#define SET_DAT_DELTA_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 3) | ((REG32(ADR_DAT_UART_MSR)) & 0xfffffff7))
+#define SET_DAT_CTS(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffef))
+#define SET_DAT_DSR(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 5) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffdf))
+#define SET_DAT_RI(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffffbf))
+#define SET_DAT_CD(_VAL_) (REG32(ADR_DAT_UART_MSR)) = (((_VAL_) << 7) | ((REG32(ADR_DAT_UART_MSR)) & 0xffffff7f))
+#define SET_DAT_BRDC_DIV(_VAL_) (REG32(ADR_DAT_UART_SPR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_SPR)) & 0xffff0000))
+#define SET_DAT_RTHR_L(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_RTHR)) & 0xfffffff0))
+#define SET_DAT_RTHR_H(_VAL_) (REG32(ADR_DAT_UART_RTHR)) = (((_VAL_) << 4) | ((REG32(ADR_DAT_UART_RTHR)) & 0xffffff0f))
+#define SET_DAT_INT_IDCODE(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 0) | ((REG32(ADR_DAT_UART_ISR)) & 0xfffffff0))
+#define SET_DAT_FIFOS_ENABLED(_VAL_) (REG32(ADR_DAT_UART_ISR)) = (((_VAL_) << 6) | ((REG32(ADR_DAT_UART_ISR)) & 0xffffff3f))
+#define SET_MASK_TOP(_VAL_) (REG32(ADR_INT_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MASK)) & 0x00000000))
+#define SET_INT_MODE(_VAL_) (REG32(ADR_INT_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_INT_MODE)) & 0x00000000))
+#define SET_IRQ_PHY_0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffe))
+#define SET_IRQ_PHY_1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffd))
+#define SET_IRQ_SDIO(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffffb))
+#define SET_IRQ_BEACON_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffff7))
+#define SET_IRQ_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffef))
+#define SET_IRQ_PRE_BEACON(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffdf))
+#define SET_IRQ_EDCA0_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffffbf))
+#define SET_IRQ_EDCA1_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffff7f))
+#define SET_IRQ_EDCA2_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffeff))
+#define SET_IRQ_EDCA3_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffdff))
+#define SET_IRQ_EDCA4_TX_DONE(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffffbff))
+#define SET_IRQ_BEACON_DTIM(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffefff))
+#define SET_IRQ_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffdfff))
+#define SET_IRQ_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_IRQ_STS)) & 0xffffbfff))
+#define SET_IRQ_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_IRQ_STS)) & 0xffff7fff))
+#define SET_IRQ_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffeffff))
+#define SET_IRQ_FENCE_HIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffdffff))
+#define SET_IRQ_ILL_ADDR_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_IRQ_STS)) & 0xfffbffff))
+#define SET_IRQ_MBOX(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_IRQ_STS)) & 0xfff7ffff))
+#define SET_IRQ_US_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_IRQ_STS)) & 0xffefffff))
+#define SET_IRQ_US_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_IRQ_STS)) & 0xffdfffff))
+#define SET_IRQ_US_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_IRQ_STS)) & 0xffbfffff))
+#define SET_IRQ_US_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_IRQ_STS)) & 0xff7fffff))
+#define SET_IRQ_MS_TIMER0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_IRQ_STS)) & 0xfeffffff))
+#define SET_IRQ_MS_TIMER1(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_IRQ_STS)) & 0xfdffffff))
+#define SET_IRQ_MS_TIMER2(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_IRQ_STS)) & 0xfbffffff))
+#define SET_IRQ_MS_TIMER3(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_IRQ_STS)) & 0xf7ffffff))
+#define SET_IRQ_TX_LIMIT_INT(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_IRQ_STS)) & 0xefffffff))
+#define SET_IRQ_DMA0(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_IRQ_STS)) & 0xdfffffff))
+#define SET_IRQ_CO_DMA(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_IRQ_STS)) & 0xbfffffff))
+#define SET_IRQ_PERI_GROUP(_VAL_) (REG32(ADR_INT_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_IRQ_STS)) & 0x7fffffff))
+#define SET_FIQ_STATUS(_VAL_) (REG32(ADR_INT_FIQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_STS)) & 0x00000000))
+#define SET_IRQ_RAW(_VAL_) (REG32(ADR_INT_IRQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_IRQ_RAW)) & 0x00000000))
+#define SET_FIQ_RAW(_VAL_) (REG32(ADR_INT_FIQ_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_FIQ_RAW)) & 0x00000000))
+#define SET_INT_PERI_MASK(_VAL_) (REG32(ADR_INT_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_MASK)) & 0x00000000))
+#define SET_PERI_RTC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffe))
+#define SET_IRQ_UART0_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffd))
+#define SET_IRQ_UART0_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffffb))
+#define SET_PERI_GPI_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffff7))
+#define SET_IRQ_SPI_IPC(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_INT_PERI_STS)) & 0xffffffef))
+#define SET_PERI_GPI_1_0(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff9f))
+#define SET_SCRT_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_INT_PERI_STS)) & 0xffffff7f))
+#define SET_MMU_ALC_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffeff))
+#define SET_MMU_RLS_ERR(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffdff))
+#define SET_ID_MNG_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_INT_PERI_STS)) & 0xfffffbff))
+#define SET_MBOX_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_INT_PERI_STS)) & 0xfffff7ff))
+#define SET_MBOX_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_INT_PERI_STS)) & 0xffffefff))
+#define SET_MBOX_INT_3(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_INT_PERI_STS)) & 0xffffdfff))
+#define SET_HCI_INT_1(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_INT_PERI_STS)) & 0xffffbfff))
+#define SET_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_INT_PERI_STS)) & 0xffff7fff))
+#define SET_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_INT_PERI_STS)) & 0xfffeffff))
+#define SET_ID_MNG_INT_2(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_INT_PERI_STS)) & 0xfffdffff))
+#define SET_DMN_NOHIT_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_INT_PERI_STS)) & 0xfffbffff))
+#define SET_ID_THOLD_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_INT_PERI_STS)) & 0xfff7ffff))
+#define SET_ID_THOLD_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_INT_PERI_STS)) & 0xffefffff))
+#define SET_ID_DOUBLE_RLS(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_INT_PERI_STS)) & 0xffdfffff))
+#define SET_RX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_INT_PERI_STS)) & 0xffbfffff))
+#define SET_TX_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_INT_PERI_STS)) & 0xff7fffff))
+#define SET_ALL_ID_LEN_THOLD(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_INT_PERI_STS)) & 0xfeffffff))
+#define SET_DMN_MCU_INT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_INT_PERI_STS)) & 0xfdffffff))
+#define SET_IRQ_DAT_UART_TX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_INT_PERI_STS)) & 0xfbffffff))
+#define SET_IRQ_DAT_UART_RX(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_INT_PERI_STS)) & 0xf7ffffff))
+#define SET_DAT_UART_RX_TIMEOUT(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_INT_PERI_STS)) & 0xefffffff))
+#define SET_DAT_UART_MULTI_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_INT_PERI_STS)) & 0xdfffffff))
+#define SET_ALR_ABT_NOCHG_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_INT_PERI_STS)) & 0xbfffffff))
+#define SET_TBLNEQ_MNGPKT_INT_IRQ(_VAL_) (REG32(ADR_INT_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_INT_PERI_STS)) & 0x7fffffff))
+#define SET_INTR_PERI_RAW(_VAL_) (REG32(ADR_INT_PERI_RAW)) = (((_VAL_) << 0) | ((REG32(ADR_INT_PERI_RAW)) & 0x00000000))
+#define SET_INTR_GPI00_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffffc))
+#define SET_INTR_GPI01_CFG(_VAL_) (REG32(ADR_INT_GPI_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_INT_GPI_CFG)) & 0xfffffff3))
+#define SET_SYS_RST_INT(_VAL_) (REG32(ADR_SYS_INT_FOR_HOST)) = (((_VAL_) << 0) | ((REG32(ADR_SYS_INT_FOR_HOST)) & 0xfffffffe))
+#define SET_SPI_IPC_ADDR(_VAL_) (REG32(ADR_SPI_IPC)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_IPC)) & 0x00000000))
+#define SET_SD_MASK_TOP(_VAL_) (REG32(ADR_SDIO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_MASK)) & 0x00000000))
+#define SET_IRQ_PHY_0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffe))
+#define SET_IRQ_PHY_1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffd))
+#define SET_IRQ_SDIO_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffffb))
+#define SET_IRQ_BEACON_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffff7))
+#define SET_IRQ_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffef))
+#define SET_IRQ_PRE_BEACON_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffdf))
+#define SET_IRQ_EDCA0_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 6) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffffbf))
+#define SET_IRQ_EDCA1_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffff7f))
+#define SET_IRQ_EDCA2_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffeff))
+#define SET_IRQ_EDCA3_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffdff))
+#define SET_IRQ_EDCA4_TX_DONE_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffffbff))
+#define SET_IRQ_BEACON_DTIM_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffefff))
+#define SET_IRQ_EDCA0_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffdfff))
+#define SET_IRQ_EDCA1_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffffbfff))
+#define SET_IRQ_EDCA2_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffff7fff))
+#define SET_IRQ_EDCA3_LOWTHOLD_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffeffff))
+#define SET_IRQ_FENCE_HIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffdffff))
+#define SET_IRQ_ILL_ADDR_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfffbffff))
+#define SET_IRQ_MBOX_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfff7ffff))
+#define SET_IRQ_US_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffefffff))
+#define SET_IRQ_US_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffdfffff))
+#define SET_IRQ_US_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xffbfffff))
+#define SET_IRQ_US_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xff7fffff))
+#define SET_IRQ_MS_TIMER0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfeffffff))
+#define SET_IRQ_MS_TIMER1_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfdffffff))
+#define SET_IRQ_MS_TIMER2_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xfbffffff))
+#define SET_IRQ_MS_TIMER3_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xf7ffffff))
+#define SET_IRQ_TX_LIMIT_INT_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xefffffff))
+#define SET_IRQ_DMA0_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xdfffffff))
+#define SET_IRQ_CO_DMA_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SDIO_IRQ_STS)) & 0xbfffffff))
+#define SET_IRQ_PERI_GROUP_SD(_VAL_) (REG32(ADR_SDIO_IRQ_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SDIO_IRQ_STS)) & 0x7fffffff))
+#define SET_INT_PERI_MASK_SD(_VAL_) (REG32(ADR_SD_PERI_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_MASK)) & 0x00000000))
+#define SET_PERI_RTC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 0) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffe))
+#define SET_IRQ_UART0_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffd))
+#define SET_IRQ_UART0_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffffb))
+#define SET_PERI_GPI_SD_2(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffff7))
+#define SET_IRQ_SPI_IPC_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_SD_PERI_STS)) & 0xffffffef))
+#define SET_PERI_GPI_SD_1_0(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff9f))
+#define SET_SCRT_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_SD_PERI_STS)) & 0xffffff7f))
+#define SET_MMU_ALC_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffeff))
+#define SET_MMU_RLS_ERR_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffdff))
+#define SET_ID_MNG_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 10) | ((REG32(ADR_SD_PERI_STS)) & 0xfffffbff))
+#define SET_MBOX_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 11) | ((REG32(ADR_SD_PERI_STS)) & 0xfffff7ff))
+#define SET_MBOX_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 12) | ((REG32(ADR_SD_PERI_STS)) & 0xffffefff))
+#define SET_MBOX_INT_3_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 13) | ((REG32(ADR_SD_PERI_STS)) & 0xffffdfff))
+#define SET_HCI_INT_1_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 14) | ((REG32(ADR_SD_PERI_STS)) & 0xffffbfff))
+#define SET_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 15) | ((REG32(ADR_SD_PERI_STS)) & 0xffff7fff))
+#define SET_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_SD_PERI_STS)) & 0xfffeffff))
+#define SET_ID_MNG_INT_2_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 17) | ((REG32(ADR_SD_PERI_STS)) & 0xfffdffff))
+#define SET_DMN_NOHIT_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 18) | ((REG32(ADR_SD_PERI_STS)) & 0xfffbffff))
+#define SET_ID_THOLD_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 19) | ((REG32(ADR_SD_PERI_STS)) & 0xfff7ffff))
+#define SET_ID_THOLD_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 20) | ((REG32(ADR_SD_PERI_STS)) & 0xffefffff))
+#define SET_ID_DOUBLE_RLS_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 21) | ((REG32(ADR_SD_PERI_STS)) & 0xffdfffff))
+#define SET_RX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 22) | ((REG32(ADR_SD_PERI_STS)) & 0xffbfffff))
+#define SET_TX_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 23) | ((REG32(ADR_SD_PERI_STS)) & 0xff7fffff))
+#define SET_ALL_ID_LEN_THOLD_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 24) | ((REG32(ADR_SD_PERI_STS)) & 0xfeffffff))
+#define SET_DMN_MCU_INT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 25) | ((REG32(ADR_SD_PERI_STS)) & 0xfdffffff))
+#define SET_IRQ_DAT_UART_TX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 26) | ((REG32(ADR_SD_PERI_STS)) & 0xfbffffff))
+#define SET_IRQ_DAT_UART_RX_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 27) | ((REG32(ADR_SD_PERI_STS)) & 0xf7ffffff))
+#define SET_DAT_UART_RX_TIMEOUT_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 28) | ((REG32(ADR_SD_PERI_STS)) & 0xefffffff))
+#define SET_DAT_UART_MULTI_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 29) | ((REG32(ADR_SD_PERI_STS)) & 0xdfffffff))
+#define SET_ALR_ABT_NOCHG_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 30) | ((REG32(ADR_SD_PERI_STS)) & 0xbfffffff))
+#define SET_TBLNEQ_MNGPKT_INT_IRQ_SD(_VAL_) (REG32(ADR_SD_PERI_STS)) = (((_VAL_) << 31) | ((REG32(ADR_SD_PERI_STS)) & 0x7fffffff))
+#define SET_DBG_SPI_MODE(_VAL_) (REG32(ADR_DBG_SPI_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_MODE)) & 0x00000000))
+#define SET_DBG_RX_QUOTA(_VAL_) (REG32(ADR_DBG_RX_QUOTA)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_RX_QUOTA)) & 0xffff0000))
+#define SET_DBG_CONDI_NUM(_VAL_) (REG32(ADR_DBG_CONDITION_NUMBER)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_CONDITION_NUMBER)) & 0xffffff00))
+#define SET_DBG_HOST_PATH(_VAL_) (REG32(ADR_DBG_HOST_PATH)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_HOST_PATH)) & 0xfffffffe))
+#define SET_DBG_TX_SEG(_VAL_) (REG32(ADR_DBG_TX_SEG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_SEG)) & 0x00000000))
+#define SET_DBG_BRST_MODE(_VAL_) (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DEBUG_BURST_MODE)) & 0xfffffffe))
+#define SET_DBG_CLK_WIDTH(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0xffff0000))
+#define SET_DBG_CSN_INTER(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) & 0x0000ffff))
+#define SET_DBG_BACK_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0xffff0000))
+#define SET_DBG_FRONT_DLY(_VAL_) (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) & 0x0000ffff))
+#define SET_DBG_RX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 1) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffd))
+#define SET_DBG_RX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffffb))
+#define SET_DBG_TX_FIFO_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffff7))
+#define SET_DBG_TX_HOST_FAIL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffef))
+#define SET_DBG_SPI_DOUBLE_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffdf))
+#define SET_DBG_SPI_TX_NO_ALLOC(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffffbf))
+#define SET_DBG_RDATA_RDY(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_SPI_STS)) & 0xffffff7f))
+#define SET_DBG_SPI_ALLOC_STATUS(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffeff))
+#define SET_DBG_SPI_DBG_WR_FIFO_FULL(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 9) | ((REG32(ADR_DBG_SPI_STS)) & 0xfffffdff))
+#define SET_DBG_RX_LEN(_VAL_) (REG32(ADR_DBG_SPI_STS)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_SPI_STS)) & 0x0000ffff))
+#define SET_DBG_SPI_TX_ALLOC_SIZE_SHIFT_BITS(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffff8))
+#define SET_DBG_SPI_HOST_TX_ALLOC_PKBUF(_VAL_) (REG32(ADR_DBG_TX_ALLOC_SET)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_TX_ALLOC_SET)) & 0xfffffeff))
+#define SET_DBG_SPI_TX_ALLOC_SIZE(_VAL_) (REG32(ADR_DBG_TX_ALLOC)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_TX_ALLOC)) & 0xffffff00))
+#define SET_DBG_RD_DAT_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT)) & 0xffff0000))
+#define SET_DBG_RD_STS_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT)) & 0x0000ffff))
+#define SET_DBG_JUDGE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xffff0000))
+#define SET_DBG_RD_STS_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffeffff))
+#define SET_DBG_RD_DAT_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffdffff))
+#define SET_DBG_JUDGE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT2)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT2)) & 0xfffbffff))
+#define SET_DBG_TX_DONE_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT3)) & 0xffff0000))
+#define SET_DBG_TX_DISCARD_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT3)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT3)) & 0x0000ffff))
+#define SET_DBG_TX_SET_CNT(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xffff0000))
+#define SET_DBG_TX_DISCARD_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffeffff))
+#define SET_DBG_TX_DONE_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 17) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffdffff))
+#define SET_DBG_TX_SET_CNT_CLR(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 18) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfffbffff))
+#define SET_DBG_DAT_MODE_OFF(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 19) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xfff7ffff))
+#define SET_DBG_TX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 20) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xff8fffff))
+#define SET_DBG_RX_FIFO_RESIDUE(_VAL_) (REG32(ADR_DBG_DBG_CNT4)) = (((_VAL_) << 24) | ((REG32(ADR_DBG_DBG_CNT4)) & 0xf8ffffff))
+#define SET_DBG_RX_RDY(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffe))
+#define SET_DBG_SDIO_SYS_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 2) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffffb))
+#define SET_DBG_EDCA0_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 3) | ((REG32(ADR_DBG_INT_TAG)) & 0xfffffff7))
+#define SET_DBG_EDCA1_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 4) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffef))
+#define SET_DBG_EDCA2_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 5) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffdf))
+#define SET_DBG_EDCA3_LOWTHOLD_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 6) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffffbf))
+#define SET_DBG_TX_LIMIT_INT_IN(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 7) | ((REG32(ADR_DBG_INT_TAG)) & 0xffffff7f))
+#define SET_DBG_SPI_FN1(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 8) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff80ff))
+#define SET_DBG_SPI_CLK_EN_INT(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 15) | ((REG32(ADR_DBG_INT_TAG)) & 0xffff7fff))
+#define SET_DBG_SPI_HOST_MASK(_VAL_) (REG32(ADR_DBG_INT_TAG)) = (((_VAL_) << 16) | ((REG32(ADR_DBG_INT_TAG)) & 0xff00ffff))
+#define SET_BOOT_ADDR(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_BOOT_ADDR)) & 0xff000000))
+#define SET_CHECK_SUM_FAIL(_VAL_) (REG32(ADR_BOOT_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_BOOT_ADDR)) & 0x7fffffff))
+#define SET_VERIFY_DATA(_VAL_) (REG32(ADR_VERIFY_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_VERIFY_DATA)) & 0x00000000))
+#define SET_FLASH_ADDR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_FLASH_ADDR)) & 0xff000000))
+#define SET_FLASH_CMD_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 28) | ((REG32(ADR_FLASH_ADDR)) & 0xefffffff))
+#define SET_FLASH_DMA_CLR(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 29) | ((REG32(ADR_FLASH_ADDR)) & 0xdfffffff))
+#define SET_DMA_EN(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 30) | ((REG32(ADR_FLASH_ADDR)) & 0xbfffffff))
+#define SET_DMA_BUSY(_VAL_) (REG32(ADR_FLASH_ADDR)) = (((_VAL_) << 31) | ((REG32(ADR_FLASH_ADDR)) & 0x7fffffff))
+#define SET_SRAM_ADDR(_VAL_) (REG32(ADR_SRAM_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SRAM_ADDR)) & 0x00000000))
+#define SET_FLASH_DMA_LEN(_VAL_) (REG32(ADR_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_LEN)) & 0x00000000))
+#define SET_FLASH_FRONT_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM)) & 0xffff0000))
+#define SET_FLASH_BACK_DLY(_VAL_) (REG32(ADR_SPI_PARAM)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM)) & 0x0000ffff))
+#define SET_FLASH_CLK_WIDTH(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 0) | ((REG32(ADR_SPI_PARAM2)) & 0xffff0000))
+#define SET_SPI_BUSY(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 16) | ((REG32(ADR_SPI_PARAM2)) & 0xfffeffff))
+#define SET_FLS_REMAP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 17) | ((REG32(ADR_SPI_PARAM2)) & 0xfffdffff))
+#define SET_PBUS_SWP(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 18) | ((REG32(ADR_SPI_PARAM2)) & 0xfffbffff))
+#define SET_BIT_MODE1(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 19) | ((REG32(ADR_SPI_PARAM2)) & 0xfff7ffff))
+#define SET_BIT_MODE2(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 20) | ((REG32(ADR_SPI_PARAM2)) & 0xffefffff))
+#define SET_BIT_MODE4(_VAL_) (REG32(ADR_SPI_PARAM2)) = (((_VAL_) << 21) | ((REG32(ADR_SPI_PARAM2)) & 0xffdfffff))
+#define SET_BOOT_CHECK_SUM(_VAL_) (REG32(ADR_CHECK_SUM_RESULT)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_RESULT)) & 0x00000000))
+#define SET_CHECK_SUM_TAG(_VAL_) (REG32(ADR_CHECK_SUM_IN_FILE)) = (((_VAL_) << 0) | ((REG32(ADR_CHECK_SUM_IN_FILE)) & 0x00000000))
+#define SET_CMD_LEN(_VAL_) (REG32(ADR_COMMAND_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_LEN)) & 0xffff0000))
+#define SET_CMD_ADDR(_VAL_) (REG32(ADR_COMMAND_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_COMMAND_ADDR)) & 0x00000000))
+#define SET_DMA_ADR_SRC(_VAL_) (REG32(ADR_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_SRC)) & 0x00000000))
+#define SET_DMA_ADR_DST(_VAL_) (REG32(ADR_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_ADR_DST)) & 0x00000000))
+#define SET_DMA_SRC_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff8))
+#define SET_DMA_SRC_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_DMA_CTRL)) & 0xfffffff7))
+#define SET_DMA_DST_SIZE(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_DMA_CTRL)) & 0xffffff8f))
+#define SET_DMA_DST_INC(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_DMA_CTRL)) & 0xffffff7f))
+#define SET_DMA_FAST_FILL(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_CTRL)) & 0xfffffeff))
+#define SET_DMA_SDIO_KICK(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_DMA_CTRL)) & 0xffffefff))
+#define SET_DMA_BADR_EN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_DMA_CTRL)) & 0xffffdfff))
+#define SET_DMA_LEN(_VAL_) (REG32(ADR_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_CTRL)) & 0x0000ffff))
+#define SET_DMA_INT_MASK(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_INT)) & 0xfffffffe))
+#define SET_DMA_STS(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_DMA_INT)) & 0xfffffeff))
+#define SET_DMA_FINISH(_VAL_) (REG32(ADR_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_DMA_INT)) & 0x7fffffff))
+#define SET_DMA_CONST(_VAL_) (REG32(ADR_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_FILL_CONST)) & 0x00000000))
+#define SET_SLEEP_WAKE_CNT(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_0)) & 0xff000000))
+#define SET_RG_DLDO_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 24) | ((REG32(ADR_PMU_0)) & 0xf8ffffff))
+#define SET_RG_DLDO_BOOST_IQ(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 27) | ((REG32(ADR_PMU_0)) & 0xf7ffffff))
+#define SET_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 28) | ((REG32(ADR_PMU_0)) & 0x8fffffff))
+#define SET_RG_BUCK_VREF_SEL(_VAL_) (REG32(ADR_PMU_0)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_0)) & 0x7fffffff))
+#define SET_RG_RTC_OSC_RES_SW_MANUAL(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_1)) & 0xfffffc00))
+#define SET_RG_RTC_OSC_RES_SW(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_1)) & 0xfc00ffff))
+#define SET_RTC_OSC_CAL_RES_RDY(_VAL_) (REG32(ADR_PMU_1)) = (((_VAL_) << 31) | ((REG32(ADR_PMU_1)) & 0x7fffffff))
+#define SET_RG_DCDC_MODE(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_2)) & 0xfffffffe))
+#define SET_RG_BUCK_EN_PSM(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_2)) & 0xffffffef))
+#define SET_RG_BUCK_PSM_VTH(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_2)) & 0xfffffeff))
+#define SET_RG_RTC_OSC_RES_SW_MANUAL_EN(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 12) | ((REG32(ADR_PMU_2)) & 0xffffefff))
+#define SET_RG_RTC_RDY_DEGLITCH_TIMER(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 13) | ((REG32(ADR_PMU_2)) & 0xffff9fff))
+#define SET_RTC_CAL_ENA(_VAL_) (REG32(ADR_PMU_2)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_2)) & 0xfffeffff))
+#define SET_PMU_WAKE_TRIG_EVENT(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 0) | ((REG32(ADR_PMU_3)) & 0xfffffffc))
+#define SET_DIGI_TOP_POR_MASK(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 4) | ((REG32(ADR_PMU_3)) & 0xffffffef))
+#define SET_PMU_ENTER_SLEEP_MODE(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 8) | ((REG32(ADR_PMU_3)) & 0xfffffeff))
+#define SET_RG_RTC_DUMMIES(_VAL_) (REG32(ADR_PMU_3)) = (((_VAL_) << 16) | ((REG32(ADR_PMU_3)) & 0x0000ffff))
+#define SET_RTC_EN(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_1)) & 0xfffffffe))
+#define SET_RTC_SRC(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_1)) & 0xfffffffd))
+#define SET_RTC_TICK_CNT(_VAL_) (REG32(ADR_RTC_1)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_1)) & 0x8000ffff))
+#define SET_RTC_INT_SEC_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_2)) & 0xfffffffe))
+#define SET_RTC_INT_ALARM_MASK(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 1) | ((REG32(ADR_RTC_2)) & 0xfffffffd))
+#define SET_RTC_INT_SEC(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 16) | ((REG32(ADR_RTC_2)) & 0xfffeffff))
+#define SET_RTC_INT_ALARM(_VAL_) (REG32(ADR_RTC_2)) = (((_VAL_) << 17) | ((REG32(ADR_RTC_2)) & 0xfffdffff))
+#define SET_RTC_SEC_START_CNT(_VAL_) (REG32(ADR_RTC_3W)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3W)) & 0x00000000))
+#define SET_RTC_SEC_CNT(_VAL_) (REG32(ADR_RTC_3R)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_3R)) & 0x00000000))
+#define SET_RTC_SEC_ALARM_VALUE(_VAL_) (REG32(ADR_RTC_4)) = (((_VAL_) << 0) | ((REG32(ADR_RTC_4)) & 0x00000000))
+#define SET_D2_DMA_ADR_SRC(_VAL_) (REG32(ADR_D2_DMA_ADR_SRC)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_SRC)) & 0x00000000))
+#define SET_D2_DMA_ADR_DST(_VAL_) (REG32(ADR_D2_DMA_ADR_DST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_ADR_DST)) & 0x00000000))
+#define SET_D2_DMA_SRC_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff8))
+#define SET_D2_DMA_SRC_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffff7))
+#define SET_D2_DMA_DST_SIZE(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff8f))
+#define SET_D2_DMA_DST_INC(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffff7f))
+#define SET_D2_DMA_FAST_FILL(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_CTRL)) & 0xfffffeff))
+#define SET_D2_DMA_SDIO_KICK(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffefff))
+#define SET_D2_DMA_BADR_EN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_D2_DMA_CTRL)) & 0xffffdfff))
+#define SET_D2_DMA_LEN(_VAL_) (REG32(ADR_D2_DMA_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_D2_DMA_CTRL)) & 0x0000ffff))
+#define SET_D2_DMA_INT_MASK(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffffe))
+#define SET_D2_DMA_STS(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 8) | ((REG32(ADR_D2_DMA_INT)) & 0xfffffeff))
+#define SET_D2_DMA_FINISH(_VAL_) (REG32(ADR_D2_DMA_INT)) = (((_VAL_) << 31) | ((REG32(ADR_D2_DMA_INT)) & 0x7fffffff))
+#define SET_D2_DMA_CONST(_VAL_) (REG32(ADR_D2_DMA_FILL_CONST)) = (((_VAL_) << 0) | ((REG32(ADR_D2_DMA_FILL_CONST)) & 0x00000000))
+#define SET_TRAP_UNKNOWN_TYPE(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_CONTROL)) & 0xfffffffe))
+#define SET_TX_ON_DEMAND_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_CONTROL)) & 0xfffffffd))
+#define SET_RX_2_HOST(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_CONTROL)) & 0xfffffffb))
+#define SET_AUTO_SEQNO(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 3) | ((REG32(ADR_CONTROL)) & 0xfffffff7))
+#define SET_BYPASSS_TX_PARSER_ENCAP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 4) | ((REG32(ADR_CONTROL)) & 0xffffffef))
+#define SET_HDR_STRIP(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 5) | ((REG32(ADR_CONTROL)) & 0xffffffdf))
+#define SET_ERP_PROTECT(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 6) | ((REG32(ADR_CONTROL)) & 0xffffff3f))
+#define SET_PRO_VER(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_CONTROL)) & 0xfffffcff))
+#define SET_TXQ_ID0(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 12) | ((REG32(ADR_CONTROL)) & 0xffff8fff))
+#define SET_TXQ_ID1(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_CONTROL)) & 0xfff8ffff))
+#define SET_TX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 20) | ((REG32(ADR_CONTROL)) & 0xffefffff))
+#define SET_RX_ETHER_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 21) | ((REG32(ADR_CONTROL)) & 0xffdfffff))
+#define SET_RX_NULL_TRAP_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 22) | ((REG32(ADR_CONTROL)) & 0xffbfffff))
+#define SET_RX_GET_TX_QUEUE_EN(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 25) | ((REG32(ADR_CONTROL)) & 0xfdffffff))
+#define SET_HCI_INQ_SEL(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 26) | ((REG32(ADR_CONTROL)) & 0xfbffffff))
+#define SET_TRX_DEBUG_CNT_ENA(_VAL_) (REG32(ADR_CONTROL)) = (((_VAL_) << 28) | ((REG32(ADR_CONTROL)) & 0xefffffff))
+#define SET_WAKE_SOON_WITH_SCK(_VAL_) (REG32(ADR_SDIO_WAKE_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_WAKE_MODE)) & 0xfffffffe))
+#define SET_TX_FLOW_CTRL(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_0)) & 0xffff0000))
+#define SET_TX_FLOW_MGMT(_VAL_) (REG32(ADR_TX_FLOW_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FLOW_0)) & 0x0000ffff))
+#define SET_TX_FLOW_DATA(_VAL_) (REG32(ADR_TX_FLOW_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FLOW_1)) & 0x00000000))
+#define SET_DOT11RTSTHRESHOLD(_VAL_) (REG32(ADR_THREASHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_THREASHOLD)) & 0x0000ffff))
+#define SET_TXF_ID(_VAL_) (REG32(ADR_TXFID_INCREASE)) = (((_VAL_) << 0) | ((REG32(ADR_TXFID_INCREASE)) & 0xffffffc0))
+#define SET_SEQ_CTRL(_VAL_) (REG32(ADR_GLOBAL_SEQUENCE)) = (((_VAL_) << 0) | ((REG32(ADR_GLOBAL_SEQUENCE)) & 0xffff0000))
+#define SET_TX_PBOFFSET(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffffff00))
+#define SET_TX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xffff00ff))
+#define SET_RX_INFO_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff00ffff))
+#define SET_RX_LAST_PHY_SIZE(_VAL_) (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ffffff))
+#define SET_TX_INFO_CLEAR_SIZE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xffffffc0))
+#define SET_TX_INFO_CLEAR_ENABLE(_VAL_) (REG32(ADR_HCI_TX_INFO_CLEAR)) = (((_VAL_) << 8) | ((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0xfffffeff))
+#define SET_TXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000))
+#define SET_TXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_TX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff))
+#define SET_RXTRAP_ETHTYPE1(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000))
+#define SET_RXTRAP_ETHTYPE0(_VAL_) (REG32(ADR_RX_ETHER_TYPE_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff))
+#define SET_TX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_0)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_0)) & 0x00000000))
+#define SET_RX_PKT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_1)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_1)) & 0x00000000))
+#define SET_HOST_CMD_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_2)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_2)) & 0xffffff00))
+#define SET_HOST_EVENT_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_3)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_3)) & 0xffffff00))
+#define SET_TX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_4)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_4)) & 0xffffff00))
+#define SET_RX_PKT_DROP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_5)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_5)) & 0xffffff00))
+#define SET_TX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_6)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_6)) & 0xffffff00))
+#define SET_RX_PKT_TRAP_COUNTER(_VAL_) (REG32(ADR_PACKET_COUNTER_INFO_7)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_COUNTER_INFO_7)) & 0xffffff00))
+#define SET_HOST_TX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) & 0xffffff00))
+#define SET_HOST_RX_FAIL_COUNTER(_VAL_) (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) & 0xffffff00))
+#define SET_HCI_STATE_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0x00000000))
+#define SET_HCI_ST_TIMEOUT_MONITOR(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_1)) & 0x00000000))
+#define SET_TX_ON_DEMAND_LENGTH(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0x00000000))
+#define SET_HCI_MONITOR_REG1(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0x00000000))
+#define SET_HCI_MONITOR_REG2(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0x00000000))
+#define SET_HCI_TX_ALLOC_TIME_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0x00000000))
+#define SET_HCI_TX_ALLOC_TIME_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xffff0000))
+#define SET_HCI_MB_MAX_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xff00ffff))
+#define SET_HCI_TX_ALLOC_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0x00000000))
+#define SET_HCI_TX_ALLOC_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xffff0000))
+#define SET_HCI_PROC_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 16) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0xff00ffff))
+#define SET_SDIO_TRANS_CNT(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (((_VAL_) << 24) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_8)) & 0x00ffffff))
+#define SET_SDIO_TX_INVALID_CNT_31_0(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_9)) & 0x00000000))
+#define SET_SDIO_TX_INVALID_CNT_47_32(_VAL_) (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (((_VAL_) << 0) | ((REG32(ADR_HCI_STATE_DEBUG_MODE_10)) & 0xffff0000))
+#define SET_CS_START_ADDR(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_CS_START_ADDR)) & 0xffff0000))
+#define SET_CS_PKT_ID(_VAL_) (REG32(ADR_CS_START_ADDR)) = (((_VAL_) << 16) | ((REG32(ADR_CS_START_ADDR)) & 0xff80ffff))
+#define SET_ADD_LEN(_VAL_) (REG32(ADR_CS_ADD_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_CS_ADD_LEN)) & 0xffff0000))
+#define SET_CS_ADDER_EN(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CMD)) & 0xfffffffe))
+#define SET_PSEUDO(_VAL_) (REG32(ADR_CS_CMD)) = (((_VAL_) << 1) | ((REG32(ADR_CS_CMD)) & 0xfffffffd))
+#define SET_CALCULATE(_VAL_) (REG32(ADR_CS_INI_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_INI_BUF)) & 0x00000000))
+#define SET_L4_LEN(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 0) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xffff0000))
+#define SET_L4_PROTOL(_VAL_) (REG32(ADR_CS_PSEUDO_BUF)) = (((_VAL_) << 16) | ((REG32(ADR_CS_PSEUDO_BUF)) & 0xff00ffff))
+#define SET_CHECK_SUM(_VAL_) (REG32(ADR_CS_CHECK_SUM)) = (((_VAL_) << 0) | ((REG32(ADR_CS_CHECK_SUM)) & 0xffff0000))
+#define SET_RAND_EN(_VAL_) (REG32(ADR_RAND_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_EN)) & 0xfffffffe))
+#define SET_RAND_NUM(_VAL_) (REG32(ADR_RAND_NUM)) = (((_VAL_) << 0) | ((REG32(ADR_RAND_NUM)) & 0x00000000))
+#define SET_MUL_OP1(_VAL_) (REG32(ADR_MUL_OP1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP1)) & 0x00000000))
+#define SET_MUL_OP2(_VAL_) (REG32(ADR_MUL_OP2)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_OP2)) & 0x00000000))
+#define SET_MUL_ANS0(_VAL_) (REG32(ADR_MUL_ANS0)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS0)) & 0x00000000))
+#define SET_MUL_ANS1(_VAL_) (REG32(ADR_MUL_ANS1)) = (((_VAL_) << 0) | ((REG32(ADR_MUL_ANS1)) & 0x00000000))
+#define SET_RD_ADDR(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_RDATA)) & 0xffff0000))
+#define SET_RD_ID(_VAL_) (REG32(ADR_DMA_RDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_RDATA)) & 0xff80ffff))
+#define SET_WR_ADDR(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_WDATA)) & 0xffff0000))
+#define SET_WR_ID(_VAL_) (REG32(ADR_DMA_WDATA)) = (((_VAL_) << 16) | ((REG32(ADR_DMA_WDATA)) & 0xff80ffff))
+#define SET_LEN(_VAL_) (REG32(ADR_DMA_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_LEN)) & 0xffff0000))
+#define SET_CLR(_VAL_) (REG32(ADR_DMA_CLR)) = (((_VAL_) << 0) | ((REG32(ADR_DMA_CLR)) & 0xfffffffe))
+#define SET_PHY_MODE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_NAV_DATA)) & 0xfffffffc))
+#define SET_SHRT_PREAM(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 2) | ((REG32(ADR_NAV_DATA)) & 0xfffffffb))
+#define SET_SHRT_GI(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 3) | ((REG32(ADR_NAV_DATA)) & 0xfffffff7))
+#define SET_DATA_RATE(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 4) | ((REG32(ADR_NAV_DATA)) & 0xfffff80f))
+#define SET_MCS(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 12) | ((REG32(ADR_NAV_DATA)) & 0xffff8fff))
+#define SET_FRAME_LEN(_VAL_) (REG32(ADR_NAV_DATA)) = (((_VAL_) << 16) | ((REG32(ADR_NAV_DATA)) & 0x0000ffff))
+#define SET_DURATION(_VAL_) (REG32(ADR_CO_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_CO_NAV)) & 0xffff0000))
+#define SET_SHA_DST_ADDR(_VAL_) (REG32(ADR_SHA_DST_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_DST_ADDR)) & 0x00000000))
+#define SET_SHA_SRC_ADDR(_VAL_) (REG32(ADR_SHA_SRC_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SRC_ADDR)) & 0x00000000))
+#define SET_SHA_BUSY(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 0) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffe))
+#define SET_SHA_ENDIAN(_VAL_) (REG32(ADR_SHA_SETTING)) = (((_VAL_) << 1) | ((REG32(ADR_SHA_SETTING)) & 0xfffffffd))
+#define SET_EFS_CLKFREQ(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffff000))
+#define SET_LOW_ACTIVE(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xfffeffff))
+#define SET_EFS_CLKFREQ_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 20) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf00fffff))
+#define SET_EFS_PRE_RD(_VAL_) (REG32(ADR_EFUSE_CLK_FREQ)) = (((_VAL_) << 28) | ((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0fffffff))
+#define SET_EFS_LDO_ON(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000))
+#define SET_EFS_LDO_OFF(_VAL_) (REG32(ADR_EFUSE_LDO_TIME)) = (((_VAL_) << 16) | ((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff))
+#define SET_EFS_RDATA_0(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_0)) & 0x00000000))
+#define SET_EFS_WDATA_0(_VAL_) (REG32(ADR_EFUSE_WDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_0)) & 0x00000000))
+#define SET_EFS_RDATA_1(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_1)) & 0x00000000))
+#define SET_EFS_WDATA_1(_VAL_) (REG32(ADR_EFUSE_WDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_1)) & 0x00000000))
+#define SET_EFS_RDATA_2(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_2)) & 0x00000000))
+#define SET_EFS_WDATA_2(_VAL_) (REG32(ADR_EFUSE_WDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_2)) & 0x00000000))
+#define SET_EFS_RDATA_3(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_3)) & 0x00000000))
+#define SET_EFS_WDATA_3(_VAL_) (REG32(ADR_EFUSE_WDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_3)) & 0x00000000))
+#define SET_EFS_RDATA_4(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_4)) & 0x00000000))
+#define SET_EFS_WDATA_4(_VAL_) (REG32(ADR_EFUSE_WDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_4)) & 0x00000000))
+#define SET_EFS_RDATA_5(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_5)) & 0x00000000))
+#define SET_EFS_WDATA_5(_VAL_) (REG32(ADR_EFUSE_WDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_5)) & 0x00000000))
+#define SET_EFS_RDATA_6(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_6)) & 0x00000000))
+#define SET_EFS_WDATA_6(_VAL_) (REG32(ADR_EFUSE_WDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_6)) & 0x00000000))
+#define SET_EFS_RDATA_7(_VAL_) (REG32(ADR_EFUSE_AHB_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_AHB_RDATA_7)) & 0x00000000))
+#define SET_EFS_WDATA_7(_VAL_) (REG32(ADR_EFUSE_WDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_WDATA_7)) & 0x00000000))
+#define SET_EFS_SPI_RD0_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD0_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD0_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD1_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD1_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD1_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD2_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD2_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD2_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD3_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD3_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD3_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD4_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD4_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD4_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD5_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD5_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD5_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD6_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD6_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD6_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RD7_EN(_VAL_) (REG32(ADR_EFUSE_SPI_RD7_EN)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RD7_EN)) & 0xfffffffe))
+#define SET_EFS_SPI_RBUSY(_VAL_) (REG32(ADR_EFUSE_SPI_BUSY)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_BUSY)) & 0xfffffffe))
+#define SET_EFS_SPI_RDATA_0(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_0)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_0)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_1(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_1)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_1)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_2(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_2)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_2)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_3(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_3)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_3)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_4(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_4)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_4)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_5(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_5)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_5)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_6(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_6)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_6)) & 0x00000000))
+#define SET_EFS_SPI_RDATA_7(_VAL_) (REG32(ADR_EFUSE_SPI_RDATA_7)) = (((_VAL_) << 0) | ((REG32(ADR_EFUSE_SPI_RDATA_7)) & 0x00000000))
+#define SET_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffe))
+#define SET_FORCE_GET_RK(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG1)) & 0xfffffffd))
+#define SET_SMS4_DESCRY_EN(_VAL_) (REG32(ADR_SMS4_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG1)) & 0xffffffef))
+#define SET_DEC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffe))
+#define SET_DEC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffd))
+#define SET_ENC_DOUT_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffffb))
+#define SET_ENC_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 3) | ((REG32(ADR_SMS4_CFG2)) & 0xfffffff7))
+#define SET_KEY_DIN_MSB(_VAL_) (REG32(ADR_SMS4_CFG2)) = (((_VAL_) << 4) | ((REG32(ADR_SMS4_CFG2)) & 0xffffffef))
+#define SET_SMS4_CBC_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffe))
+#define SET_SMS4_CFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 1) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffd))
+#define SET_SMS4_OFB_EN(_VAL_) (REG32(ADR_SMS4_MODE1)) = (((_VAL_) << 2) | ((REG32(ADR_SMS4_MODE1)) & 0xfffffffb))
+#define SET_SMS4_START_TRIG(_VAL_) (REG32(ADR_SMS4_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_TRIG)) & 0xfffffffe))
+#define SET_SMS4_BUSY(_VAL_) (REG32(ADR_SMS4_STATUS1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS1)) & 0xfffffffe))
+#define SET_SMS4_DONE(_VAL_) (REG32(ADR_SMS4_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_STATUS2)) & 0xfffffffe))
+#define SET_SMS4_DATAIN_0(_VAL_) (REG32(ADR_SMS4_DATA_IN0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN0)) & 0x00000000))
+#define SET_SMS4_DATAIN_1(_VAL_) (REG32(ADR_SMS4_DATA_IN1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN1)) & 0x00000000))
+#define SET_SMS4_DATAIN_2(_VAL_) (REG32(ADR_SMS4_DATA_IN2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN2)) & 0x00000000))
+#define SET_SMS4_DATAIN_3(_VAL_) (REG32(ADR_SMS4_DATA_IN3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_IN3)) & 0x00000000))
+#define SET_SMS4_DATAOUT_0(_VAL_) (REG32(ADR_SMS4_DATA_OUT0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT0)) & 0x00000000))
+#define SET_SMS4_DATAOUT_1(_VAL_) (REG32(ADR_SMS4_DATA_OUT1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT1)) & 0x00000000))
+#define SET_SMS4_DATAOUT_2(_VAL_) (REG32(ADR_SMS4_DATA_OUT2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT2)) & 0x00000000))
+#define SET_SMS4_DATAOUT_3(_VAL_) (REG32(ADR_SMS4_DATA_OUT3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_DATA_OUT3)) & 0x00000000))
+#define SET_SMS4_KEY_0(_VAL_) (REG32(ADR_SMS4_KEY_0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_0)) & 0x00000000))
+#define SET_SMS4_KEY_1(_VAL_) (REG32(ADR_SMS4_KEY_1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_1)) & 0x00000000))
+#define SET_SMS4_KEY_2(_VAL_) (REG32(ADR_SMS4_KEY_2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_2)) & 0x00000000))
+#define SET_SMS4_KEY_3(_VAL_) (REG32(ADR_SMS4_KEY_3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_KEY_3)) & 0x00000000))
+#define SET_SMS4_MODE_IV0(_VAL_) (REG32(ADR_SMS4_MODE_IV0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV0)) & 0x00000000))
+#define SET_SMS4_MODE_IV1(_VAL_) (REG32(ADR_SMS4_MODE_IV1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV1)) & 0x00000000))
+#define SET_SMS4_MODE_IV2(_VAL_) (REG32(ADR_SMS4_MODE_IV2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV2)) & 0x00000000))
+#define SET_SMS4_MODE_IV3(_VAL_) (REG32(ADR_SMS4_MODE_IV3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_MODE_IV3)) & 0x00000000))
+#define SET_SMS4_OFB_ENC0(_VAL_) (REG32(ADR_SMS4_OFB_ENC0)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC0)) & 0x00000000))
+#define SET_SMS4_OFB_ENC1(_VAL_) (REG32(ADR_SMS4_OFB_ENC1)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC1)) & 0x00000000))
+#define SET_SMS4_OFB_ENC2(_VAL_) (REG32(ADR_SMS4_OFB_ENC2)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC2)) & 0x00000000))
+#define SET_SMS4_OFB_ENC3(_VAL_) (REG32(ADR_SMS4_OFB_ENC3)) = (((_VAL_) << 0) | ((REG32(ADR_SMS4_OFB_ENC3)) & 0x00000000))
+#define SET_MRX_MCAST_TB0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB0_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK0_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK0_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK0_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK0_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK0_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_0(_VAL_) (REG32(ADR_MRX_MCAST_CTRL0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL0)) & 0xfffffffc))
+#define SET_MRX_MCAST_TB1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB1_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK1_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK1_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK1_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK1_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK1_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_1(_VAL_) (REG32(ADR_MRX_MCAST_CTRL1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL1)) & 0xfffffffc))
+#define SET_MRX_MCAST_TB2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB2_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK2_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK2_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK2_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK2_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK2_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_2(_VAL_) (REG32(ADR_MRX_MCAST_CTRL2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL2)) & 0xfffffffc))
+#define SET_MRX_MCAST_TB3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_TB3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_0)) & 0x00000000))
+#define SET_MRX_MCAST_TB3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_TB3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_TB3_1)) & 0xffff0000))
+#define SET_MRX_MCAST_MASK3_31_0(_VAL_) (REG32(ADR_MRX_MCAST_MK3_0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_0)) & 0x00000000))
+#define SET_MRX_MCAST_MASK3_47_32(_VAL_) (REG32(ADR_MRX_MCAST_MK3_1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_MK3_1)) & 0xffff0000))
+#define SET_MRX_MCAST_CTRL_3(_VAL_) (REG32(ADR_MRX_MCAST_CTRL3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MCAST_CTRL3)) & 0xfffffffc))
+#define SET_MRX_PHY_INFO(_VAL_) (REG32(ADR_MRX_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_PHY_INFO)) & 0x00000000))
+#define SET_DBG_BA_TYPE(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_DBG)) & 0xffffffc0))
+#define SET_DBG_BA_SEQ(_VAL_) (REG32(ADR_MRX_BA_DBG)) = (((_VAL_) << 8) | ((REG32(ADR_MRX_BA_DBG)) & 0xfff000ff))
+#define SET_MRX_FLT_TB0(_VAL_) (REG32(ADR_MRX_FLT_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB0)) & 0xffff8000))
+#define SET_MRX_FLT_TB1(_VAL_) (REG32(ADR_MRX_FLT_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB1)) & 0xffff8000))
+#define SET_MRX_FLT_TB2(_VAL_) (REG32(ADR_MRX_FLT_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB2)) & 0xffff8000))
+#define SET_MRX_FLT_TB3(_VAL_) (REG32(ADR_MRX_FLT_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB3)) & 0xffff8000))
+#define SET_MRX_FLT_TB4(_VAL_) (REG32(ADR_MRX_FLT_TB4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB4)) & 0xffff8000))
+#define SET_MRX_FLT_TB5(_VAL_) (REG32(ADR_MRX_FLT_TB5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB5)) & 0xffff8000))
+#define SET_MRX_FLT_TB6(_VAL_) (REG32(ADR_MRX_FLT_TB6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB6)) & 0xffff8000))
+#define SET_MRX_FLT_TB7(_VAL_) (REG32(ADR_MRX_FLT_TB7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB7)) & 0xffff8000))
+#define SET_MRX_FLT_TB8(_VAL_) (REG32(ADR_MRX_FLT_TB8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB8)) & 0xffff8000))
+#define SET_MRX_FLT_TB9(_VAL_) (REG32(ADR_MRX_FLT_TB9)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB9)) & 0xffff8000))
+#define SET_MRX_FLT_TB10(_VAL_) (REG32(ADR_MRX_FLT_TB10)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB10)) & 0xffff8000))
+#define SET_MRX_FLT_TB11(_VAL_) (REG32(ADR_MRX_FLT_TB11)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB11)) & 0xffff8000))
+#define SET_MRX_FLT_TB12(_VAL_) (REG32(ADR_MRX_FLT_TB12)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB12)) & 0xffff8000))
+#define SET_MRX_FLT_TB13(_VAL_) (REG32(ADR_MRX_FLT_TB13)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB13)) & 0xffff8000))
+#define SET_MRX_FLT_TB14(_VAL_) (REG32(ADR_MRX_FLT_TB14)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB14)) & 0xffff8000))
+#define SET_MRX_FLT_TB15(_VAL_) (REG32(ADR_MRX_FLT_TB15)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_TB15)) & 0xffff8000))
+#define SET_MRX_FLT_EN0(_VAL_) (REG32(ADR_MRX_FLT_EN0)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN0)) & 0xffff0000))
+#define SET_MRX_FLT_EN1(_VAL_) (REG32(ADR_MRX_FLT_EN1)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN1)) & 0xffff0000))
+#define SET_MRX_FLT_EN2(_VAL_) (REG32(ADR_MRX_FLT_EN2)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN2)) & 0xffff0000))
+#define SET_MRX_FLT_EN3(_VAL_) (REG32(ADR_MRX_FLT_EN3)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN3)) & 0xffff0000))
+#define SET_MRX_FLT_EN4(_VAL_) (REG32(ADR_MRX_FLT_EN4)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN4)) & 0xffff0000))
+#define SET_MRX_FLT_EN5(_VAL_) (REG32(ADR_MRX_FLT_EN5)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN5)) & 0xffff0000))
+#define SET_MRX_FLT_EN6(_VAL_) (REG32(ADR_MRX_FLT_EN6)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN6)) & 0xffff0000))
+#define SET_MRX_FLT_EN7(_VAL_) (REG32(ADR_MRX_FLT_EN7)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN7)) & 0xffff0000))
+#define SET_MRX_FLT_EN8(_VAL_) (REG32(ADR_MRX_FLT_EN8)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FLT_EN8)) & 0xffff0000))
+#define SET_MRX_LEN_FLT(_VAL_) (REG32(ADR_MRX_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_LEN_FLT)) & 0xffff0000))
+#define SET_RX_FLOW_DATA(_VAL_) (REG32(ADR_RX_FLOW_DATA)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_DATA)) & 0x00000000))
+#define SET_RX_FLOW_MNG(_VAL_) (REG32(ADR_RX_FLOW_MNG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_MNG)) & 0xffff0000))
+#define SET_RX_FLOW_CTRL(_VAL_) (REG32(ADR_RX_FLOW_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FLOW_CTRL)) & 0xffff0000))
+#define SET_MRX_STP_EN(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xfffffffe))
+#define SET_MRX_STP_OFST(_VAL_) (REG32(ADR_RX_TIME_STAMP_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_RX_TIME_STAMP_CFG)) & 0xffff00ff))
+#define SET_DBG_FF_FULL(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_FF_FULL)) & 0xffff0000))
+#define SET_DBG_FF_FULL_CLR(_VAL_) (REG32(ADR_DBG_FF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_FF_FULL)) & 0x7fffffff))
+#define SET_DBG_WFF_FULL(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_WFF_FULL)) & 0xffff0000))
+#define SET_DBG_WFF_FULL_CLR(_VAL_) (REG32(ADR_DBG_WFF_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_WFF_FULL)) & 0x7fffffff))
+#define SET_DBG_MB_FULL(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_MB_FULL)) & 0xffff0000))
+#define SET_DBG_MB_FULL_CLR(_VAL_) (REG32(ADR_DBG_MB_FULL)) = (((_VAL_) << 31) | ((REG32(ADR_DBG_MB_FULL)) & 0x7fffffff))
+#define SET_BA_CTRL(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_BA_CTRL)) & 0xfffffffc))
+#define SET_BA_DBG_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_BA_CTRL)) & 0xfffffffb))
+#define SET_BA_AGRE_EN(_VAL_) (REG32(ADR_BA_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_BA_CTRL)) & 0xfffffff7))
+#define SET_BA_TA_31_0(_VAL_) (REG32(ADR_BA_TA_0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_0)) & 0x00000000))
+#define SET_BA_TA_47_32(_VAL_) (REG32(ADR_BA_TA_1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TA_1)) & 0xffff0000))
+#define SET_BA_TID(_VAL_) (REG32(ADR_BA_TID)) = (((_VAL_) << 0) | ((REG32(ADR_BA_TID)) & 0xfffffff0))
+#define SET_BA_ST_SEQ(_VAL_) (REG32(ADR_BA_ST_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_BA_ST_SEQ)) & 0xfffff000))
+#define SET_BA_SB0(_VAL_) (REG32(ADR_BA_SB0)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB0)) & 0x00000000))
+#define SET_BA_SB1(_VAL_) (REG32(ADR_BA_SB1)) = (((_VAL_) << 0) | ((REG32(ADR_BA_SB1)) & 0x00000000))
+#define SET_MRX_WD(_VAL_) (REG32(ADR_MRX_WATCH_DOG)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_WATCH_DOG)) & 0xfffe0000))
+#define SET_ACK_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffe))
+#define SET_BA_GEN_EN(_VAL_) (REG32(ADR_ACK_GEN_EN)) = (((_VAL_) << 1) | ((REG32(ADR_ACK_GEN_EN)) & 0xfffffffd))
+#define SET_ACK_GEN_DUR(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffff0000))
+#define SET_ACK_GEN_INFO(_VAL_) (REG32(ADR_ACK_GEN_PARA)) = (((_VAL_) << 16) | ((REG32(ADR_ACK_GEN_PARA)) & 0xffc0ffff))
+#define SET_ACK_GEN_RA_31_0(_VAL_) (REG32(ADR_ACK_GEN_RA_0)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_0)) & 0x00000000))
+#define SET_ACK_GEN_RA_47_32(_VAL_) (REG32(ADR_ACK_GEN_RA_1)) = (((_VAL_) << 0) | ((REG32(ADR_ACK_GEN_RA_1)) & 0xffff0000))
+#define SET_MIB_LEN_FAIL(_VAL_) (REG32(ADR_MIB_LEN_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_LEN_FAIL)) & 0xffff0000))
+#define SET_TRAP_HW_ID(_VAL_) (REG32(ADR_TRAP_HW_ID)) = (((_VAL_) << 0) | ((REG32(ADR_TRAP_HW_ID)) & 0xfffffff0))
+#define SET_ID_IN_USE(_VAL_) (REG32(ADR_ID_IN_USE)) = (((_VAL_) << 0) | ((REG32(ADR_ID_IN_USE)) & 0xffffff00))
+#define SET_MRX_ERR(_VAL_) (REG32(ADR_MRX_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ERR)) & 0x00000000))
+#define SET_W0_T0_SEQ(_VAL_) (REG32(ADR_WSID0_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID0_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T1_SEQ(_VAL_) (REG32(ADR_WSID0_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID1_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T2_SEQ(_VAL_) (REG32(ADR_WSID0_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID2_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T3_SEQ(_VAL_) (REG32(ADR_WSID0_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID3_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T4_SEQ(_VAL_) (REG32(ADR_WSID0_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID4_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T5_SEQ(_VAL_) (REG32(ADR_WSID0_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID5_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T6_SEQ(_VAL_) (REG32(ADR_WSID0_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID6_RX_SEQ)) & 0xffff0000))
+#define SET_W0_T7_SEQ(_VAL_) (REG32(ADR_WSID0_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0_TID7_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T0_SEQ(_VAL_) (REG32(ADR_WSID1_TID0_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID0_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T1_SEQ(_VAL_) (REG32(ADR_WSID1_TID1_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID1_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T2_SEQ(_VAL_) (REG32(ADR_WSID1_TID2_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID2_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T3_SEQ(_VAL_) (REG32(ADR_WSID1_TID3_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID3_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T4_SEQ(_VAL_) (REG32(ADR_WSID1_TID4_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID4_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T5_SEQ(_VAL_) (REG32(ADR_WSID1_TID5_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID5_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T6_SEQ(_VAL_) (REG32(ADR_WSID1_TID6_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID6_RX_SEQ)) & 0xffff0000))
+#define SET_W1_T7_SEQ(_VAL_) (REG32(ADR_WSID1_TID7_RX_SEQ)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1_TID7_RX_SEQ)) & 0xffff0000))
+#define SET_ADDR1A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 0) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffffc))
+#define SET_ADDR2A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 2) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffff3))
+#define SET_ADDR3A_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 4) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffffcf))
+#define SET_ADDR1B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 6) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffff3f))
+#define SET_ADDR2B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 8) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffffcff))
+#define SET_ADDR3B_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 10) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xfffff3ff))
+#define SET_ADDR3C_SEL(_VAL_) (REG32(ADR_HDR_ADDR_SEL)) = (((_VAL_) << 12) | ((REG32(ADR_HDR_ADDR_SEL)) & 0xffffcfff))
+#define SET_FRM_CTRL(_VAL_) (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (((_VAL_) << 0) | ((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0xffffffc0))
+#define SET_CSR_PHY_INFO(_VAL_) (REG32(ADR_PHY_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_INFO)) & 0xffff8000))
+#define SET_AMPDU_SIG(_VAL_) (REG32(ADR_AMPDU_SIG)) = (((_VAL_) << 0) | ((REG32(ADR_AMPDU_SIG)) & 0xffffff00))
+#define SET_MIB_AMPDU(_VAL_) (REG32(ADR_MIB_AMPDU)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_AMPDU)) & 0x00000000))
+#define SET_LEN_FLT(_VAL_) (REG32(ADR_LEN_FLT)) = (((_VAL_) << 0) | ((REG32(ADR_LEN_FLT)) & 0xffff0000))
+#define SET_MIB_DELIMITER(_VAL_) (REG32(ADR_MIB_DELIMITER)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_DELIMITER)) & 0xffff0000))
+#define SET_MTX_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_STS)) & 0xfffeffff))
+#define SET_MTX_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_STS)) & 0xfffdffff))
+#define SET_MTX_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_STS)) & 0xfffbffff))
+#define SET_MTX_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_STS)) & 0xfff7ffff))
+#define SET_MTX_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_STS)) & 0xffefffff))
+#define SET_MTX_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_STS)) & 0xffdfffff))
+#define SET_MTX_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_STS)) & 0xffbfffff))
+#define SET_MTX_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_STS)) & 0xff7fffff))
+#define SET_MTX_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_STS)) & 0xfeffffff))
+#define SET_MTX_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_STS)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_STS)) & 0xfdffffff))
+#define SET_MTX_EN_INT_Q0_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_INT_EN)) & 0xfffeffff))
+#define SET_MTX_EN_INT_Q0_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MTX_INT_EN)) & 0xfffdffff))
+#define SET_MTX_EN_INT_Q1_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 18) | ((REG32(ADR_MTX_INT_EN)) & 0xfffbffff))
+#define SET_MTX_EN_INT_Q1_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 19) | ((REG32(ADR_MTX_INT_EN)) & 0xfff7ffff))
+#define SET_MTX_EN_INT_Q2_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_MTX_INT_EN)) & 0xffefffff))
+#define SET_MTX_EN_INT_Q2_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_MTX_INT_EN)) & 0xffdfffff))
+#define SET_MTX_EN_INT_Q3_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_INT_EN)) & 0xffbfffff))
+#define SET_MTX_EN_INT_Q3_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_INT_EN)) & 0xff7fffff))
+#define SET_MTX_EN_INT_Q4_Q_EMPTY(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_INT_EN)) & 0xfeffffff))
+#define SET_MTX_EN_INT_Q4_TXOP_RUNOUT(_VAL_) (REG32(ADR_MTX_INT_EN)) = (((_VAL_) << 25) | ((REG32(ADR_MTX_INT_EN)) & 0xfdffffff))
+#define SET_MTX_MTX2PHY_SLOW(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffffe))
+#define SET_MTX_M2M_SLOW_PRD(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffff1))
+#define SET_MTX_AMPDU_CRC_AUTO(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffdf))
+#define SET_MTX_FAST_RSP_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffffbf))
+#define SET_MTX_RAW_DATA_MODE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffff7f))
+#define SET_MTX_ACK_DUR0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffeff))
+#define SET_MTX_TSF_AUTO_BCN(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffffbff))
+#define SET_MTX_TSF_AUTO_MISC(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_MISC_EN)) & 0xfffff7ff))
+#define SET_MTX_FORCE_CS_IDLE(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffefff))
+#define SET_MTX_FORCE_BKF_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffdfff))
+#define SET_MTX_FORCE_DMA_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_MISC_EN)) & 0xffffbfff))
+#define SET_MTX_FORCE_RXEN0(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_MISC_EN)) & 0xffff7fff))
+#define SET_MTX_HALT_Q_MB(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_MISC_EN)) & 0xffc0ffff))
+#define SET_MTX_CTS_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_MISC_EN)) & 0xffbfffff))
+#define SET_MTX_AMPDU_SET_DIF(_VAL_) (REG32(ADR_MTX_MISC_EN)) = (((_VAL_) << 23) | ((REG32(ADR_MTX_MISC_EN)) & 0xff7fffff))
+#define SET_MTX_EDCCA_TOUT(_VAL_) (REG32(ADR_MTX_EDCCA_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_EDCCA_TOUT)) & 0xfffffc00))
+#define SET_MTX_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffffd))
+#define SET_MTX_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_INT_STS)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_INT_STS)) & 0xfffffff7))
+#define SET_MTX_EN_INT_BCN(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffffd))
+#define SET_MTX_EN_INT_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_INT)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_EN_INT)) & 0xfffffff7))
+#define SET_MTX_BCN_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffe))
+#define SET_MTX_TIME_STAMP_AUTO_FILL(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffffffd))
+#define SET_MTX_TSF_TIMER_EN(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffdf))
+#define SET_MTX_HALT_MNG_UNTIL_DTIM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 6) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffffffbf))
+#define SET_MTX_INT_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xffff00ff))
+#define SET_MTX_AUTO_FLUSH_Q4(_VAL_) (REG32(ADR_MTX_BCN_EN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_EN_MISC)) & 0xfffeffff))
+#define SET_MTX_BCN_PKTID_CH_LOCK(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffffe))
+#define SET_MTX_BCN_CFG_VLD(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff9))
+#define SET_MTX_AUTO_BCN_ONGOING(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 3) | ((REG32(ADR_MTX_BCN_MISC)) & 0xfffffff7))
+#define SET_MTX_BCN_TIMER(_VAL_) (REG32(ADR_MTX_BCN_MISC)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_MISC)) & 0x0000ffff))
+#define SET_MTX_BCN_PERIOD(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_PRD)) & 0xffff0000))
+#define SET_MTX_DTIM_NUM(_VAL_) (REG32(ADR_MTX_BCN_PRD)) = (((_VAL_) << 24) | ((REG32(ADR_MTX_BCN_PRD)) & 0x00ffffff))
+#define SET_MTX_BCN_TSF_L(_VAL_) (REG32(ADR_MTX_BCN_TSF_L)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_L)) & 0x00000000))
+#define SET_MTX_BCN_TSF_U(_VAL_) (REG32(ADR_MTX_BCN_TSF_U)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_TSF_U)) & 0x00000000))
+#define SET_MTX_BCN_PKT_ID0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xffffff80))
+#define SET_MTX_DTIM_OFST0(_VAL_) (REG32(ADR_MTX_BCN_CFG0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG0)) & 0xfc00ffff))
+#define SET_MTX_BCN_PKT_ID1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xffffff80))
+#define SET_MTX_DTIM_OFST1(_VAL_) (REG32(ADR_MTX_BCN_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_BCN_CFG1)) & 0xfc00ffff))
+#define SET_MTX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffe))
+#define SET_MRX_CCA(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_STATUS)) & 0xfffffffd))
+#define SET_MTX_DMA_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 2) | ((REG32(ADR_MTX_STATUS)) & 0xffffffe3))
+#define SET_CH_ST_FSM(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 5) | ((REG32(ADR_MTX_STATUS)) & 0xffffff1f))
+#define SET_MTX_GNT_LOCK(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_STATUS)) & 0xfffffeff))
+#define SET_MTX_DMA_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MTX_STATUS)) & 0xfffffdff))
+#define SET_MTX_Q_REQ(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MTX_STATUS)) & 0xfffffbff))
+#define SET_MTX_TX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MTX_STATUS)) & 0xfffff7ff))
+#define SET_MRX_RX_EN(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MTX_STATUS)) & 0xffffefff))
+#define SET_DBG_PRTC_PRD(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 13) | ((REG32(ADR_MTX_STATUS)) & 0xffffdfff))
+#define SET_DBG_DMA_RDY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 14) | ((REG32(ADR_MTX_STATUS)) & 0xffffbfff))
+#define SET_DBG_WAIT_RSP(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_MTX_STATUS)) & 0xffff7fff))
+#define SET_DBG_CFRM_BUSY(_VAL_) (REG32(ADR_MTX_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_STATUS)) & 0xfffeffff))
+#define SET_DBG_RST(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffe))
+#define SET_DBG_MODE(_VAL_) (REG32(ADR_MTX_DBG_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MTX_DBG_CTRL)) & 0xfffffffd))
+#define SET_MB_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT0)) & 0xffff0000))
+#define SET_RX_EN_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT0)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT0)) & 0x0000ffff))
+#define SET_RX_CS_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT1)) & 0xffff0000))
+#define SET_TX_CCA_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT1)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT1)) & 0x0000ffff))
+#define SET_Q_REQ_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT2)) & 0xffff0000))
+#define SET_CH_STA0_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT2)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT2)) & 0x0000ffff))
+#define SET_MTX_DUR_RSP_TOUT_B(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffffff00))
+#define SET_MTX_DUR_RSP_TOUT_G(_VAL_) (REG32(ADR_MTX_DUR_TOUT)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_TOUT)) & 0xffff00ff))
+#define SET_MTX_DUR_RSP_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffffff00))
+#define SET_MTX_DUR_BURST_SIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffff00ff))
+#define SET_MTX_DUR_SLOT(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_IFS)) & 0xffc0ffff))
+#define SET_MTX_DUR_RSP_EIFS(_VAL_) (REG32(ADR_MTX_DUR_IFS)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_IFS)) & 0x003fffff))
+#define SET_MTX_DUR_RSP_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffffff00))
+#define SET_MTX_DUR_BURST_SIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 8) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffff00ff))
+#define SET_MTX_DUR_SLOT_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0xffc0ffff))
+#define SET_MTX_DUR_RSP_EIFS_G(_VAL_) (REG32(ADR_MTX_DUR_SIFS_G)) = (((_VAL_) << 22) | ((REG32(ADR_MTX_DUR_SIFS_G)) & 0x003fffff))
+#define SET_CH_STA1_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT3)) & 0xffff0000))
+#define SET_CH_STA2_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT3)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT3)) & 0x0000ffff))
+#define SET_MTX_NAV(_VAL_) (REG32(ADR_MTX_NAV)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_NAV)) & 0xffff0000))
+#define SET_MTX_MIB_CNT0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xc0000000))
+#define SET_MTX_MIB_EN0(_VAL_) (REG32(ADR_MTX_MIB_WSID0)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID0)) & 0xbfffffff))
+#define SET_MTX_MIB_CNT1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xc0000000))
+#define SET_MTX_MIB_EN1(_VAL_) (REG32(ADR_MTX_MIB_WSID1)) = (((_VAL_) << 30) | ((REG32(ADR_MTX_MIB_WSID1)) & 0xbfffffff))
+#define SET_CH_STA3_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_DBG_DAT4)) & 0xffff0000))
+#define SET_CH_STA4_DUR(_VAL_) (REG32(ADR_MTX_DBG_DAT4)) = (((_VAL_) << 16) | ((REG32(ADR_MTX_DBG_DAT4)) & 0x0000ffff))
+#define SET_TXQ0_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ0_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ0_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ0_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ0_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ0_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ0_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ0_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ0_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ0_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ0_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ0_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ0_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ0_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ0_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ0_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ1_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ1_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ1_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ1_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ1_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ1_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ1_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ1_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ1_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ1_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ1_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ1_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ1_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ1_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ1_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ1_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ2_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ2_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ2_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ2_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ2_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ2_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ2_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ2_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ2_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ2_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ2_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ2_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ2_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ2_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ2_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ2_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ3_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ3_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ3_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ3_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ3_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ3_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ3_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ3_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ3_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ3_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ3_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ3_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ3_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ3_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ3_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ3_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_TXQ4_MTX_Q_PRE_LD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 1) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffd))
+#define SET_TXQ4_MTX_Q_BKF_CNT_FIXED(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 2) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffffb))
+#define SET_TXQ4_MTX_Q_TXOP_SUB_FRM_TIME(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 3) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xfffffff7))
+#define SET_TXQ4_MTX_Q_MB_NO_RLS(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 4) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffef))
+#define SET_TXQ4_MTX_Q_TXOP_FRC_BUR(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 5) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffffdf))
+#define SET_TXQ4_MTX_Q_RND_MODE(_VAL_) (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (((_VAL_) << 6) | ((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0xffffff3f))
+#define SET_TXQ4_MTX_Q_AIFSN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffffff0))
+#define SET_TXQ4_MTX_Q_ECWMIN(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xfffff0ff))
+#define SET_TXQ4_MTX_Q_ECWMAX(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 12) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0fff))
+#define SET_TXQ4_MTX_Q_TXOP_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (((_VAL_) << 16) | ((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000ffff))
+#define SET_TXQ4_MTX_Q_BKF_CNT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) & 0xffff0000))
+#define SET_TXQ4_MTX_Q_SRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffffff00))
+#define SET_TXQ4_MTX_Q_LRC_LIMIT(_VAL_) (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (((_VAL_) << 8) | ((REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) & 0xffff00ff))
+#define SET_TXQ4_MTX_Q_ID_MAP_L(_VAL_) (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) & 0x00000000))
+#define SET_TXQ4_MTX_Q_TXOP_CH_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) & 0xffff0000))
+#define SET_TXQ4_MTX_Q_TXOP_OV_THD(_VAL_) (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (((_VAL_) << 0) | ((REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) & 0xffff0000))
+#define SET_VALID0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 0) | ((REG32(ADR_WSID0)) & 0xfffffffe))
+#define SET_PEER_QOS_EN0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 1) | ((REG32(ADR_WSID0)) & 0xfffffffd))
+#define SET_PEER_OP_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 2) | ((REG32(ADR_WSID0)) & 0xfffffff3))
+#define SET_PEER_HT_MODE0(_VAL_) (REG32(ADR_WSID0)) = (((_VAL_) << 4) | ((REG32(ADR_WSID0)) & 0xffffffcf))
+#define SET_PEER_MAC0_31_0(_VAL_) (REG32(ADR_PEER_MAC0_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_0)) & 0x00000000))
+#define SET_PEER_MAC0_47_32(_VAL_) (REG32(ADR_PEER_MAC0_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC0_1)) & 0xffff0000))
+#define SET_TX_ACK_POLICY_0_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_0)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_1)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_2)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_3)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_4)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_5)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_6)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_0_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_0_7)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_0_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_0_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0xfffff000))
+#define SET_VALID1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 0) | ((REG32(ADR_WSID1)) & 0xfffffffe))
+#define SET_PEER_QOS_EN1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 1) | ((REG32(ADR_WSID1)) & 0xfffffffd))
+#define SET_PEER_OP_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 2) | ((REG32(ADR_WSID1)) & 0xfffffff3))
+#define SET_PEER_HT_MODE1(_VAL_) (REG32(ADR_WSID1)) = (((_VAL_) << 4) | ((REG32(ADR_WSID1)) & 0xffffffcf))
+#define SET_PEER_MAC1_31_0(_VAL_) (REG32(ADR_PEER_MAC1_0)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_0)) & 0x00000000))
+#define SET_PEER_MAC1_47_32(_VAL_) (REG32(ADR_PEER_MAC1_1)) = (((_VAL_) << 0) | ((REG32(ADR_PEER_MAC1_1)) & 0xffff0000))
+#define SET_TX_ACK_POLICY_1_0(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_0)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_0(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_1(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_1)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_1(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_2(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_2)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_2(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_3(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_3)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_3(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_4(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_4)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_4(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_4)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_5(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_5)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_5(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_5)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_6(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_6)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_6(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_6)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0xfffff000))
+#define SET_TX_ACK_POLICY_1_7(_VAL_) (REG32(ADR_TX_ACK_POLICY_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ACK_POLICY_1_7)) & 0xfffffffc))
+#define SET_TX_SEQ_CTRL_1_7(_VAL_) (REG32(ADR_TX_SEQ_CTRL_1_7)) = (((_VAL_) << 0) | ((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0xfffff000))
+#define SET_INFO0(_VAL_) (REG32(ADR_INFO0)) = (((_VAL_) << 0) | ((REG32(ADR_INFO0)) & 0x00000000))
+#define SET_INFO1(_VAL_) (REG32(ADR_INFO1)) = (((_VAL_) << 0) | ((REG32(ADR_INFO1)) & 0x00000000))
+#define SET_INFO2(_VAL_) (REG32(ADR_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_INFO2)) & 0x00000000))
+#define SET_INFO3(_VAL_) (REG32(ADR_INFO3)) = (((_VAL_) << 0) | ((REG32(ADR_INFO3)) & 0x00000000))
+#define SET_INFO4(_VAL_) (REG32(ADR_INFO4)) = (((_VAL_) << 0) | ((REG32(ADR_INFO4)) & 0x00000000))
+#define SET_INFO5(_VAL_) (REG32(ADR_INFO5)) = (((_VAL_) << 0) | ((REG32(ADR_INFO5)) & 0x00000000))
+#define SET_INFO6(_VAL_) (REG32(ADR_INFO6)) = (((_VAL_) << 0) | ((REG32(ADR_INFO6)) & 0x00000000))
+#define SET_INFO7(_VAL_) (REG32(ADR_INFO7)) = (((_VAL_) << 0) | ((REG32(ADR_INFO7)) & 0x00000000))
+#define SET_INFO8(_VAL_) (REG32(ADR_INFO8)) = (((_VAL_) << 0) | ((REG32(ADR_INFO8)) & 0x00000000))
+#define SET_INFO9(_VAL_) (REG32(ADR_INFO9)) = (((_VAL_) << 0) | ((REG32(ADR_INFO9)) & 0x00000000))
+#define SET_INFO10(_VAL_) (REG32(ADR_INFO10)) = (((_VAL_) << 0) | ((REG32(ADR_INFO10)) & 0x00000000))
+#define SET_INFO11(_VAL_) (REG32(ADR_INFO11)) = (((_VAL_) << 0) | ((REG32(ADR_INFO11)) & 0x00000000))
+#define SET_INFO12(_VAL_) (REG32(ADR_INFO12)) = (((_VAL_) << 0) | ((REG32(ADR_INFO12)) & 0x00000000))
+#define SET_INFO13(_VAL_) (REG32(ADR_INFO13)) = (((_VAL_) << 0) | ((REG32(ADR_INFO13)) & 0x00000000))
+#define SET_INFO14(_VAL_) (REG32(ADR_INFO14)) = (((_VAL_) << 0) | ((REG32(ADR_INFO14)) & 0x00000000))
+#define SET_INFO15(_VAL_) (REG32(ADR_INFO15)) = (((_VAL_) << 0) | ((REG32(ADR_INFO15)) & 0x00000000))
+#define SET_INFO16(_VAL_) (REG32(ADR_INFO16)) = (((_VAL_) << 0) | ((REG32(ADR_INFO16)) & 0x00000000))
+#define SET_INFO17(_VAL_) (REG32(ADR_INFO17)) = (((_VAL_) << 0) | ((REG32(ADR_INFO17)) & 0x00000000))
+#define SET_INFO18(_VAL_) (REG32(ADR_INFO18)) = (((_VAL_) << 0) | ((REG32(ADR_INFO18)) & 0x00000000))
+#define SET_INFO19(_VAL_) (REG32(ADR_INFO19)) = (((_VAL_) << 0) | ((REG32(ADR_INFO19)) & 0x00000000))
+#define SET_INFO20(_VAL_) (REG32(ADR_INFO20)) = (((_VAL_) << 0) | ((REG32(ADR_INFO20)) & 0x00000000))
+#define SET_INFO21(_VAL_) (REG32(ADR_INFO21)) = (((_VAL_) << 0) | ((REG32(ADR_INFO21)) & 0x00000000))
+#define SET_INFO22(_VAL_) (REG32(ADR_INFO22)) = (((_VAL_) << 0) | ((REG32(ADR_INFO22)) & 0x00000000))
+#define SET_INFO23(_VAL_) (REG32(ADR_INFO23)) = (((_VAL_) << 0) | ((REG32(ADR_INFO23)) & 0x00000000))
+#define SET_INFO24(_VAL_) (REG32(ADR_INFO24)) = (((_VAL_) << 0) | ((REG32(ADR_INFO24)) & 0x00000000))
+#define SET_INFO25(_VAL_) (REG32(ADR_INFO25)) = (((_VAL_) << 0) | ((REG32(ADR_INFO25)) & 0x00000000))
+#define SET_INFO26(_VAL_) (REG32(ADR_INFO26)) = (((_VAL_) << 0) | ((REG32(ADR_INFO26)) & 0x00000000))
+#define SET_INFO27(_VAL_) (REG32(ADR_INFO27)) = (((_VAL_) << 0) | ((REG32(ADR_INFO27)) & 0x00000000))
+#define SET_INFO28(_VAL_) (REG32(ADR_INFO28)) = (((_VAL_) << 0) | ((REG32(ADR_INFO28)) & 0x00000000))
+#define SET_INFO29(_VAL_) (REG32(ADR_INFO29)) = (((_VAL_) << 0) | ((REG32(ADR_INFO29)) & 0x00000000))
+#define SET_INFO30(_VAL_) (REG32(ADR_INFO30)) = (((_VAL_) << 0) | ((REG32(ADR_INFO30)) & 0x00000000))
+#define SET_INFO31(_VAL_) (REG32(ADR_INFO31)) = (((_VAL_) << 0) | ((REG32(ADR_INFO31)) & 0x00000000))
+#define SET_INFO32(_VAL_) (REG32(ADR_INFO32)) = (((_VAL_) << 0) | ((REG32(ADR_INFO32)) & 0x00000000))
+#define SET_INFO33(_VAL_) (REG32(ADR_INFO33)) = (((_VAL_) << 0) | ((REG32(ADR_INFO33)) & 0x00000000))
+#define SET_INFO34(_VAL_) (REG32(ADR_INFO34)) = (((_VAL_) << 0) | ((REG32(ADR_INFO34)) & 0x00000000))
+#define SET_INFO35(_VAL_) (REG32(ADR_INFO35)) = (((_VAL_) << 0) | ((REG32(ADR_INFO35)) & 0x00000000))
+#define SET_INFO36(_VAL_) (REG32(ADR_INFO36)) = (((_VAL_) << 0) | ((REG32(ADR_INFO36)) & 0x00000000))
+#define SET_INFO37(_VAL_) (REG32(ADR_INFO37)) = (((_VAL_) << 0) | ((REG32(ADR_INFO37)) & 0x00000000))
+#define SET_INFO38(_VAL_) (REG32(ADR_INFO38)) = (((_VAL_) << 0) | ((REG32(ADR_INFO38)) & 0x00000000))
+#define SET_INFO_MASK(_VAL_) (REG32(ADR_INFO_MASK)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_MASK)) & 0x00000000))
+#define SET_INFO_DEF_RATE(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xffffffc0))
+#define SET_INFO_MRX_OFFSET(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xfff0ffff))
+#define SET_BCAST_RATEUNKNOW(_VAL_) (REG32(ADR_INFO_RATE_OFFSET)) = (((_VAL_) << 24) | ((REG32(ADR_INFO_RATE_OFFSET)) & 0xc0ffffff))
+#define SET_INFO_IDX_TBL_ADDR(_VAL_) (REG32(ADR_INFO_IDX_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_IDX_ADDR)) & 0x00000000))
+#define SET_INFO_LEN_TBL_ADDR(_VAL_) (REG32(ADR_INFO_LEN_ADDR)) = (((_VAL_) << 0) | ((REG32(ADR_INFO_LEN_ADDR)) & 0x00000000))
+#define SET_IC_TAG_31_0(_VAL_) (REG32(ADR_IC_TIME_TAG_0)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_0)) & 0x00000000))
+#define SET_IC_TAG_63_32(_VAL_) (REG32(ADR_IC_TIME_TAG_1)) = (((_VAL_) << 0) | ((REG32(ADR_IC_TIME_TAG_1)) & 0x00000000))
+#define SET_CH1_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 0) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffffc))
+#define SET_CH2_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 8) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffffcff))
+#define SET_CH3_PRI(_VAL_) (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (((_VAL_) << 16) | ((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0xfffcffff))
+#define SET_RG_MAC_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_MODE)) & 0xfffffffe))
+#define SET_RG_MAC_M2M(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_MODE)) & 0xfffffffd))
+#define SET_RG_PHY_LPBK(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 2) | ((REG32(ADR_MAC_MODE)) & 0xfffffffb))
+#define SET_RG_LPBK_RX_EN(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_MODE)) & 0xfffffff7))
+#define SET_EXT_MAC_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_MODE)) & 0xffffffef))
+#define SET_EXT_PHY_MODE(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_MODE)) & 0xffffffdf))
+#define SET_ASIC_TAG(_VAL_) (REG32(ADR_MAC_MODE)) = (((_VAL_) << 24) | ((REG32(ADR_MAC_MODE)) & 0x00ffffff))
+#define SET_HCI_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 0) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffe))
+#define SET_CO_PROC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffffd))
+#define SET_MTX_MISC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffff7))
+#define SET_MTX_QUE_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffef))
+#define SET_MTX_CHST_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffdf))
+#define SET_MTX_BCN_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffffbf))
+#define SET_MRX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffff7f))
+#define SET_AMPDU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffeff))
+#define SET_MMU_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffffdff))
+#define SET_ID_MNG_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xfffff7ff))
+#define SET_MBOX_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 12) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffefff))
+#define SET_SCRT_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffdfff))
+#define SET_MIC_SW_RST(_VAL_) (REG32(ADR_ALL_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ALL_SOFTWARE_RESET)) & 0xffffbfff))
+#define SET_CO_PROC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffffd))
+#define SET_MTX_MISC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffff7))
+#define SET_MTX_QUE_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffef))
+#define SET_MTX_CHST_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffdf))
+#define SET_MTX_BCN_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffffbf))
+#define SET_MRX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffff7f))
+#define SET_AMPDU_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffffeff))
+#define SET_ID_MNG_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffffbfff))
+#define SET_MBOX_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xffff7fff))
+#define SET_SCRT_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 16) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffeffff))
+#define SET_MIC_ENG_RST(_VAL_) (REG32(ADR_ENG_SOFTWARE_RESET)) = (((_VAL_) << 17) | ((REG32(ADR_ENG_SOFTWARE_RESET)) & 0xfffdffff))
+#define SET_CO_PROC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 1) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffffd))
+#define SET_MTX_MISC_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 3) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffff7))
+#define SET_MTX_QUE0_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 4) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffef))
+#define SET_MTX_QUE1_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 5) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffdf))
+#define SET_MTX_QUE2_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 6) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffffbf))
+#define SET_MTX_QUE3_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 7) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffff7f))
+#define SET_MTX_QUE4_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 8) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffeff))
+#define SET_MTX_QUE5_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 9) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffdff))
+#define SET_MRX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 10) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffffbff))
+#define SET_AMPDU_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 11) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xfffff7ff))
+#define SET_SCRT_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 13) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffdfff))
+#define SET_ID_MNG_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 14) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffffbfff))
+#define SET_MBOX_CSR_RST(_VAL_) (REG32(ADR_CSR_SOFTWARE_RESET)) = (((_VAL_) << 15) | ((REG32(ADR_CSR_SOFTWARE_RESET)) & 0xffff7fff))
+#define SET_HCI_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffe))
+#define SET_CO_PROC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MTX_MISC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffff7))
+#define SET_MTX_QUE_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffef))
+#define SET_MRX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffdf))
+#define SET_AMPDU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffffbf))
+#define SET_MMU_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 7) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffff7f))
+#define SET_ID_MNG_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 9) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffdff))
+#define SET_MBOX_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_SCRT_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xfffff7ff))
+#define SET_MIC_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffefff))
+#define SET_MIB_CLK_EN(_VAL_) (REG32(ADR_MAC_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_HCI_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 0) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffe))
+#define SET_CO_PROC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MTX_MISC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 3) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xfffffff7))
+#define SET_MTX_QUE_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 4) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffef))
+#define SET_MRX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 5) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffdf))
+#define SET_AMPDU_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 6) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffffbf))
+#define SET_ID_MNG_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 12) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffefff))
+#define SET_MBOX_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_SCRT_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffffbfff))
+#define SET_MIC_ENG_CLK_EN(_VAL_) (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0xffff7fff))
+#define SET_CO_PROC_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 1) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffffd))
+#define SET_MRX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 10) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffffbff))
+#define SET_AMPDU_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 11) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xfffff7ff))
+#define SET_SCRT_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 13) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffdfff))
+#define SET_ID_MNG_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 14) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffffbfff))
+#define SET_MBOX_CSR_CLK_EN(_VAL_) (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (((_VAL_) << 15) | ((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0xffff7fff))
+#define SET_OP_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 0) | ((REG32(ADR_GLBLE_SET)) & 0xfffffffc))
+#define SET_HT_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 2) | ((REG32(ADR_GLBLE_SET)) & 0xfffffff3))
+#define SET_QOS_EN(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 4) | ((REG32(ADR_GLBLE_SET)) & 0xffffffef))
+#define SET_PB_OFFSET(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 8) | ((REG32(ADR_GLBLE_SET)) & 0xffff00ff))
+#define SET_SNIFFER_MODE(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 16) | ((REG32(ADR_GLBLE_SET)) & 0xfffeffff))
+#define SET_DUP_FLT(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 17) | ((REG32(ADR_GLBLE_SET)) & 0xfffdffff))
+#define SET_TX_PKT_RSVD(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 18) | ((REG32(ADR_GLBLE_SET)) & 0xffe3ffff))
+#define SET_AMPDU_SNIFFER(_VAL_) (REG32(ADR_GLBLE_SET)) = (((_VAL_) << 21) | ((REG32(ADR_GLBLE_SET)) & 0xffdfffff))
+#define SET_REASON_TRAP0(_VAL_) (REG32(ADR_REASON_TRAP0)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP0)) & 0x00000000))
+#define SET_REASON_TRAP1(_VAL_) (REG32(ADR_REASON_TRAP1)) = (((_VAL_) << 0) | ((REG32(ADR_REASON_TRAP1)) & 0x00000000))
+#define SET_BSSID_31_0(_VAL_) (REG32(ADR_BSSID_0)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_0)) & 0x00000000))
+#define SET_BSSID_47_32(_VAL_) (REG32(ADR_BSSID_1)) = (((_VAL_) << 0) | ((REG32(ADR_BSSID_1)) & 0xffff0000))
+#define SET_SCRT_STATE(_VAL_) (REG32(ADR_SCRT_STATE)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_STATE)) & 0xfffffff0))
+#define SET_STA_MAC_31_0(_VAL_) (REG32(ADR_STA_MAC_0)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_0)) & 0x00000000))
+#define SET_STA_MAC_47_32(_VAL_) (REG32(ADR_STA_MAC_1)) = (((_VAL_) << 0) | ((REG32(ADR_STA_MAC_1)) & 0xffff0000))
+#define SET_PAIR_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 0) | ((REG32(ADR_SCRT_SET)) & 0xfffffff8))
+#define SET_GRP_SCRT(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 3) | ((REG32(ADR_SCRT_SET)) & 0xffffffc7))
+#define SET_SCRT_PKT_ID(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 6) | ((REG32(ADR_SCRT_SET)) & 0xffffe03f))
+#define SET_SCRT_RPLY_IGNORE(_VAL_) (REG32(ADR_SCRT_SET)) = (((_VAL_) << 16) | ((REG32(ADR_SCRT_SET)) & 0xfffeffff))
+#define SET_COEXIST_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX0)) & 0xfffffffe))
+#define SET_WIRE_MODE(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 1) | ((REG32(ADR_BTCX0)) & 0xfffffff1))
+#define SET_WL_RX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 4) | ((REG32(ADR_BTCX0)) & 0xffffffef))
+#define SET_WL_TX_PRI(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 5) | ((REG32(ADR_BTCX0)) & 0xffffffdf))
+#define SET_GURAN_USE_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX0)) & 0xfffffeff))
+#define SET_GURAN_USE_CTRL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 9) | ((REG32(ADR_BTCX0)) & 0xfffffdff))
+#define SET_BEACON_TIMEOUT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 10) | ((REG32(ADR_BTCX0)) & 0xfffffbff))
+#define SET_WLAN_ACT_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 11) | ((REG32(ADR_BTCX0)) & 0xfffff7ff))
+#define SET_DUAL_ANT_EN(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 12) | ((REG32(ADR_BTCX0)) & 0xffffefff))
+#define SET_TRSW_PHY_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX0)) & 0xfffeffff))
+#define SET_WIFI_TX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 17) | ((REG32(ADR_BTCX0)) & 0xfffdffff))
+#define SET_WIFI_RX_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 18) | ((REG32(ADR_BTCX0)) & 0xfffbffff))
+#define SET_BT_SW_POL(_VAL_) (REG32(ADR_BTCX0)) = (((_VAL_) << 19) | ((REG32(ADR_BTCX0)) & 0xfff7ffff))
+#define SET_BT_PRI_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 0) | ((REG32(ADR_BTCX1)) & 0xffffff00))
+#define SET_BT_STA_SMP_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 8) | ((REG32(ADR_BTCX1)) & 0xffff00ff))
+#define SET_BEACON_TIMEOUT(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 16) | ((REG32(ADR_BTCX1)) & 0xff00ffff))
+#define SET_WLAN_REMAIN_TIME(_VAL_) (REG32(ADR_BTCX1)) = (((_VAL_) << 24) | ((REG32(ADR_BTCX1)) & 0x00ffffff))
+#define SET_SW_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffe))
+#define SET_SW_WL_TX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 1) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffd))
+#define SET_SW_WL_RX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 2) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffffb))
+#define SET_SW_BT_TRX(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 3) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffff7))
+#define SET_BT_TXBAR_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 4) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffef))
+#define SET_BT_TXBAR_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 5) | ((REG32(ADR_SWITCH_CTL)) & 0xffffffdf))
+#define SET_BT_BUSY_MANUAL_EN(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffeff))
+#define SET_BT_BUSY_SET(_VAL_) (REG32(ADR_SWITCH_CTL)) = (((_VAL_) << 9) | ((REG32(ADR_SWITCH_CTL)) & 0xfffffdff))
+#define SET_G0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 2) | ((REG32(ADR_MIB_EN)) & 0xfffffffb))
+#define SET_G0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 3) | ((REG32(ADR_MIB_EN)) & 0xfffffff7))
+#define SET_G1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 4) | ((REG32(ADR_MIB_EN)) & 0xffffffef))
+#define SET_G1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 5) | ((REG32(ADR_MIB_EN)) & 0xffffffdf))
+#define SET_Q0_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 6) | ((REG32(ADR_MIB_EN)) & 0xffffffbf))
+#define SET_Q0_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 7) | ((REG32(ADR_MIB_EN)) & 0xffffff7f))
+#define SET_Q1_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 8) | ((REG32(ADR_MIB_EN)) & 0xfffffeff))
+#define SET_Q1_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 9) | ((REG32(ADR_MIB_EN)) & 0xfffffdff))
+#define SET_Q2_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 10) | ((REG32(ADR_MIB_EN)) & 0xfffffbff))
+#define SET_Q2_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 11) | ((REG32(ADR_MIB_EN)) & 0xfffff7ff))
+#define SET_Q3_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 12) | ((REG32(ADR_MIB_EN)) & 0xffffefff))
+#define SET_Q3_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 13) | ((REG32(ADR_MIB_EN)) & 0xffffdfff))
+#define SET_SCRT_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 14) | ((REG32(ADR_MIB_EN)) & 0xffffbfff))
+#define SET_SCRT_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 15) | ((REG32(ADR_MIB_EN)) & 0xffff7fff))
+#define SET_MISC_PKT_CLS_MIB_EN(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 16) | ((REG32(ADR_MIB_EN)) & 0xfffeffff))
+#define SET_MISC_PKT_CLS_ONGOING(_VAL_) (REG32(ADR_MIB_EN)) = (((_VAL_) << 17) | ((REG32(ADR_MIB_EN)) & 0xfffdffff))
+#define SET_MTX_WSID0_SUCC(_VAL_) (REG32(ADR_MTX_WSID0_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_SUCC)) & 0xffff0000))
+#define SET_MTX_WSID0_FRM(_VAL_) (REG32(ADR_MTX_WSID0_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_FRM)) & 0xffff0000))
+#define SET_MTX_WSID0_RETRY(_VAL_) (REG32(ADR_MTX_WSID0_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_RETRY)) & 0xffff0000))
+#define SET_MTX_WSID0_TOTAL(_VAL_) (REG32(ADR_MTX_WSID0_TOTAL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_WSID0_TOTAL)) & 0xffff0000))
+#define SET_MTX_GRP(_VAL_) (REG32(ADR_MTX_GROUP)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_GROUP)) & 0xfff00000))
+#define SET_MTX_FAIL(_VAL_) (REG32(ADR_MTX_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FAIL)) & 0xffff0000))
+#define SET_MTX_RETRY(_VAL_) (REG32(ADR_MTX_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RETRY)) & 0xfff00000))
+#define SET_MTX_MULTI_RETRY(_VAL_) (REG32(ADR_MTX_MULTI_RETRY)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_MULTI_RETRY)) & 0xfff00000))
+#define SET_MTX_RTS_SUCC(_VAL_) (REG32(ADR_MTX_RTS_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_SUCCESS)) & 0xffff0000))
+#define SET_MTX_RTS_FAIL(_VAL_) (REG32(ADR_MTX_RTS_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_RTS_FAIL)) & 0xffff0000))
+#define SET_MTX_ACK_FAIL(_VAL_) (REG32(ADR_MTX_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_FAIL)) & 0xffff0000))
+#define SET_MTX_FRM(_VAL_) (REG32(ADR_MTX_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_FRM)) & 0xfff00000))
+#define SET_MTX_ACK_TX(_VAL_) (REG32(ADR_MTX_ACK_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_ACK_TX)) & 0xffff0000))
+#define SET_MTX_CTS_TX(_VAL_) (REG32(ADR_MTX_CTS_TX)) = (((_VAL_) << 0) | ((REG32(ADR_MTX_CTS_TX)) & 0xffff0000))
+#define SET_MRX_DUP(_VAL_) (REG32(ADR_MRX_DUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DUP_FRM)) & 0xffff0000))
+#define SET_MRX_FRG(_VAL_) (REG32(ADR_MRX_FRG_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FRG_FRM)) & 0xfff00000))
+#define SET_MRX_GRP(_VAL_) (REG32(ADR_MRX_GROUP_FRM)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_GROUP_FRM)) & 0xfff00000))
+#define SET_MRX_FCS_ERR(_VAL_) (REG32(ADR_MRX_FCS_ERR)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_ERR)) & 0xffff0000))
+#define SET_MRX_FCS_SUC(_VAL_) (REG32(ADR_MRX_FCS_SUCC)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_FCS_SUCC)) & 0xffff0000))
+#define SET_MRX_MISS(_VAL_) (REG32(ADR_MRX_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MISS)) & 0xffff0000))
+#define SET_MRX_ALC_FAIL(_VAL_) (REG32(ADR_MRX_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ALC_FAIL)) & 0xffff0000))
+#define SET_MRX_DAT_NTF(_VAL_) (REG32(ADR_MRX_DAT_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_NTF)) & 0xffff0000))
+#define SET_MRX_RTS_NTF(_VAL_) (REG32(ADR_MRX_RTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_RTS_NTF)) & 0xffff0000))
+#define SET_MRX_CTS_NTF(_VAL_) (REG32(ADR_MRX_CTS_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CTS_NTF)) & 0xffff0000))
+#define SET_MRX_ACK_NTF(_VAL_) (REG32(ADR_MRX_ACK_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_ACK_NTF)) & 0xffff0000))
+#define SET_MRX_BA_NTF(_VAL_) (REG32(ADR_MRX_BA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BA_NTF)) & 0xffff0000))
+#define SET_MRX_DATA_NTF(_VAL_) (REG32(ADR_MRX_DATA_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DATA_NTF)) & 0xffff0000))
+#define SET_MRX_MNG_NTF(_VAL_) (REG32(ADR_MRX_MNG_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MNG_NTF)) & 0xffff0000))
+#define SET_MRX_DAT_CRC_NTF(_VAL_) (REG32(ADR_MRX_DAT_CRC_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_DAT_CRC_NTF)) & 0xffff0000))
+#define SET_MRX_BAR_NTF(_VAL_) (REG32(ADR_MRX_BAR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_BAR_NTF)) & 0xffff0000))
+#define SET_MRX_MB_MISS(_VAL_) (REG32(ADR_MRX_MB_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_MB_MISS)) & 0xffff0000))
+#define SET_MRX_NIDLE_MISS(_VAL_) (REG32(ADR_MRX_NIDLE_MISS)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_NIDLE_MISS)) & 0xffff0000))
+#define SET_MRX_CSR_NTF(_VAL_) (REG32(ADR_MRX_CSR_NTF)) = (((_VAL_) << 0) | ((REG32(ADR_MRX_CSR_NTF)) & 0xffff0000))
+#define SET_DBG_Q0_SUCC(_VAL_) (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q0_FAIL(_VAL_) (REG32(ADR_DBG_Q0_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q0_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q0_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q0_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0xffff0000))
+#define SET_DBG_Q1_SUCC(_VAL_) (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q1_FAIL(_VAL_) (REG32(ADR_DBG_Q1_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q1_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q1_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q1_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0xffff0000))
+#define SET_DBG_Q2_SUCC(_VAL_) (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q2_FAIL(_VAL_) (REG32(ADR_DBG_Q2_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q2_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q2_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q2_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0xffff0000))
+#define SET_DBG_Q3_SUCC(_VAL_) (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q3_FAIL(_VAL_) (REG32(ADR_DBG_Q3_FRM_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0xffff0000))
+#define SET_DBG_Q3_ACK_SUCC(_VAL_) (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0xffff0000))
+#define SET_DBG_Q3_ACK_FAIL(_VAL_) (REG32(ADR_DBG_Q3_ACK_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0xffff0000))
+#define SET_SCRT_TKIP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP0)) & 0xfff00000))
+#define SET_SCRT_TKIP_MIC_ERR(_VAL_) (REG32(ADR_MIB_SCRT_TKIP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP1)) & 0xfff00000))
+#define SET_SCRT_TKIP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_TKIP2)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_TKIP2)) & 0xfff00000))
+#define SET_SCRT_CCMP_RPLY(_VAL_) (REG32(ADR_MIB_SCRT_CCMP0)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP0)) & 0xfff00000))
+#define SET_SCRT_CCMP_CERR(_VAL_) (REG32(ADR_MIB_SCRT_CCMP1)) = (((_VAL_) << 0) | ((REG32(ADR_MIB_SCRT_CCMP1)) & 0xfff00000))
+#define SET_DBG_LEN_CRC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_CRC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0xffff0000))
+#define SET_DBG_LEN_ALC_FAIL(_VAL_) (REG32(ADR_DBG_LEN_ALC_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0xffff0000))
+#define SET_DBG_AMPDU_PASS(_VAL_) (REG32(ADR_DBG_AMPDU_PASS)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_PASS)) & 0xffff0000))
+#define SET_DBG_AMPDU_FAIL(_VAL_) (REG32(ADR_DBG_AMPDU_FAIL)) = (((_VAL_) << 0) | ((REG32(ADR_DBG_AMPDU_FAIL)) & 0xffff0000))
+#define SET_RXID_ALC_CNT_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL1)) & 0xffff0000))
+#define SET_RXID_ALC_LEN_FAIL(_VAL_) (REG32(ADR_ID_ALC_FAIL2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_ALC_FAIL2)) & 0xffff0000))
+#define SET_CBR_RG_EN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_TX_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_TX_PA_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_TX_DAC_EN(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_RX_AGC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
+#define SET_CBR_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
+#define SET_CBR_RG_RFG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
+#define SET_CBR_RG_PGAG(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
+#define SET_CBR_RG_MODE(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
+#define SET_CBR_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
+#define SET_CBR_RG_EN_SX(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
+#define SET_CBR_RG_EN_RX_LNA(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
+#define SET_CBR_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
+#define SET_CBR_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
+#define SET_CBR_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
+#define SET_CBR_RG_EN_RX_TZ(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
+#define SET_CBR_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
+#define SET_CBR_RG_EN_RX_HPF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
+#define SET_CBR_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
+#define SET_CBR_RG_EN_ADC(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
+#define SET_CBR_RG_EN_TX_MOD(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
+#define SET_CBR_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
+#define SET_CBR_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
+#define SET_CBR_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
+#define SET_CBR_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
+#define SET_CBR_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
+#define SET_CBR_RG_EN_TX_DPD(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
+#define SET_CBR_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
+#define SET_CBR_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
+#define SET_CBR_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
+#define SET_CBR_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
+#define SET_CBR_RG_EN_IREF_RX(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
+#define SET_CBR_RG_DCDC_MODE(_VAL_) (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) & 0xffffefff))
+#define SET_CBR_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffff8))
+#define SET_CBR_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffffffc7))
+#define SET_CBR_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffffe3f))
+#define SET_CBR_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffff1ff))
+#define SET_CBR_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffff8fff))
+#define SET_CBR_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xfffc7fff))
+#define SET_CBR_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xffe3ffff))
+#define SET_CBR_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xff1fffff))
+#define SET_CBR_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xf8ffffff))
+#define SET_CBR_RG_BUCK_LEVEL(_VAL_) (REG32(ADR_CBR_LDO_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_LDO_REGISTER)) & 0xc7ffffff))
+#define SET_CBR_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffe))
+#define SET_CBR_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffd))
+#define SET_CBR_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffffb))
+#define SET_CBR_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffe07))
+#define SET_CBR_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffdff))
+#define SET_CBR_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffffbff))
+#define SET_CBR_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffff7ff))
+#define SET_CBR_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffffcfff))
+#define SET_CBR_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffff3fff))
+#define SET_CBR_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfffcffff))
+#define SET_CBR_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfff3ffff))
+#define SET_CBR_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffcfffff))
+#define SET_CBR_RG_RX_HPF3M(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xffbfffff))
+#define SET_CBR_RG_RX_HPF300K(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xff7fffff))
+#define SET_CBR_RG_RX_HPFI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xfcffffff))
+#define SET_CBR_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xf3ffffff))
+#define SET_CBR_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_ABB_REGISTER_1)) & 0xcfffffff))
+#define SET_CBR_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffffc))
+#define SET_CBR_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffff3))
+#define SET_CBR_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffffcf))
+#define SET_CBR_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffff3f))
+#define SET_CBR_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffffcff))
+#define SET_CBR_RG_RX_OUTVCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffff3ff))
+#define SET_CBR_RG_RX_TZI(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffcfff))
+#define SET_CBR_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffffbfff))
+#define SET_CBR_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfffe7fff))
+#define SET_CBR_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfff1ffff))
+#define SET_CBR_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xffefffff))
+#define SET_CBR_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xff9fffff))
+#define SET_CBR_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfe7fffff))
+#define SET_CBR_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_CBR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_ABB_REGISTER_2)) & 0xfdffffff))
+#define SET_CBR_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffffffc))
+#define SET_CBR_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffff03))
+#define SET_CBR_RG_TXPGA_STEER(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffffc0ff))
+#define SET_CBR_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffff3fff))
+#define SET_CBR_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfffcffff))
+#define SET_CBR_RG_PACELL_EN(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xffe3ffff))
+#define SET_CBR_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfe1fffff))
+#define SET_CBR_RG_PABIAS_AB(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xfdffffff))
+#define SET_CBR_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xf3ffffff))
+#define SET_CBR_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_CBR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_TX_FE_REGISTER)) & 0xcfffffff))
+#define SET_CBR_RG_RX_SQDC(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffffff8))
+#define SET_CBR_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffffe7))
+#define SET_CBR_RG_RX_LOBUF(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffffff9f))
+#define SET_CBR_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffff87f))
+#define SET_CBR_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffff87ff))
+#define SET_CBR_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xfffc7fff))
+#define SET_CBR_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffe3ffff))
+#define SET_CBR_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xffdfffff))
+#define SET_CBR_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_RX_FE_REGISTER_1)) & 0xff3fffff))
+#define SET_CBR_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
+#define SET_CBR_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
+#define SET_CBR_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
+#define SET_CBR_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
+#define SET_CBR_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
+#define SET_CBR_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
+#define SET_CBR_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
+#define SET_CBR_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
+#define SET_CBR_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
+#define SET_CBR_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
+#define SET_CBR_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
+#define SET_CBR_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
+#define SET_CBR_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
+#define SET_CBR_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
+#define SET_CBR_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
+#define SET_CBR_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
+#define SET_CBR_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
+#define SET_CBR_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
+#define SET_CBR_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_HPF_T1A(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffffe7))
+#define SET_CBR_RG_HPF_T1B(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffff9f))
+#define SET_CBR_RG_HPF_T1C(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffffe7f))
+#define SET_CBR_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xfffff9ff))
+#define SET_CBR_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_CBR_RX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_FSM_REGISTER)) & 0xffffe7ff))
+#define SET_CBR_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff9))
+#define SET_CBR_RG_ADC_DIVR(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_ADC_DVCMI(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffffffcf))
+#define SET_CBR_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffc3f))
+#define SET_CBR_RG_ADC_STNBY(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffffbff))
+#define SET_CBR_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffff7ff))
+#define SET_CBR_RG_ADC_TSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffff0fff))
+#define SET_CBR_RG_ADC_VRSEL(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfffcffff))
+#define SET_CBR_RG_DICMP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xfff3ffff))
+#define SET_CBR_RG_DIOP(_VAL_) (REG32(ADR_CBR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RX_ADC_REGISTER)) & 0xffcfffff))
+#define SET_CBR_RG_DACI1ST(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffffc))
+#define SET_CBR_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffff3))
+#define SET_CBR_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffffcf))
+#define SET_CBR_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffff3f))
+#define SET_CBR_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfffff9ff))
+#define SET_CBR_RG_TX_DAC_OS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffffc7ff))
+#define SET_CBR_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffff3fff))
+#define SET_CBR_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xfff0ffff))
+#define SET_CBR_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffefffff))
+#define SET_CBR_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffdfffff))
+#define SET_CBR_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_CBR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_TX_DAC_REGISTER)) & 0xffbfffff))
+#define SET_CBR_RG_EN_SX_R3(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_EN_SX_CH(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_EN_SX_CHP(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffffb))
+#define SET_CBR_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffff7))
+#define SET_CBR_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffef))
+#define SET_CBR_RG_EN_SX_VCO(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffdf))
+#define SET_CBR_RG_EN_SX_MOD(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffffbf))
+#define SET_CBR_RG_EN_SX_LCK(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffff7f))
+#define SET_CBR_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_EN_SX_DELCAL(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_EN_SX_PC_BYPASS(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffffbff))
+#define SET_CBR_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xfffff7ff))
+#define SET_CBR_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffefff))
+#define SET_CBR_RG_EN_SX_DIV(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffdfff))
+#define SET_CBR_RG_EN_SX_LPF(_VAL_) (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SX_ENABLE_RGISTER)) & 0xffffbfff))
+#define SET_CBR_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xff000000))
+#define SET_CBR_RG_SX_SEL_CP(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0xf0ffffff))
+#define SET_CBR_RG_SX_SEL_CS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_RGISTER_1)) & 0x0fffffff))
+#define SET_CBR_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfffff800))
+#define SET_CBR_RG_SX_SEL_C3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xffff87ff))
+#define SET_CBR_RG_SX_SEL_RS(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfff07fff))
+#define SET_CBR_RG_SX_SEL_R3(_VAL_) (REG32(ADR_CBR_SYN_RGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_RGISTER_2)) & 0xfe0fffff))
+#define SET_CBR_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffffe0))
+#define SET_CBR_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffffc1f))
+#define SET_CBR_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffffc3ff))
+#define SET_CBR_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffc3fff))
+#define SET_CBR_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfffbffff))
+#define SET_CBR_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffc7ffff))
+#define SET_CBR_RG_SX_PFDSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xffbfffff))
+#define SET_CBR_RG_SX_PFD_SET(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xff7fffff))
+#define SET_CBR_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfeffffff))
+#define SET_CBR_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfdffffff))
+#define SET_CBR_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xfbffffff))
+#define SET_CBR_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xf7ffffff))
+#define SET_CBR_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xefffffff))
+#define SET_CBR_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xdfffffff))
+#define SET_CBR_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_CBR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_PFD_CHP)) & 0xbfffffff))
+#define SET_CBR_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffffff8))
+#define SET_CBR_RG_SX_VCORSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffffff07))
+#define SET_CBR_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfffff0ff))
+#define SET_CBR_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xffff0fff))
+#define SET_CBR_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xfff0ffff))
+#define SET_CBR_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xff0fffff))
+#define SET_CBR_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0xf0ffffff))
+#define SET_CBR_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_CBR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_VCO_LOBF)) & 0x0fffffff))
+#define SET_CBR_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
+#define SET_CBR_RG_SX_MOD_ERRCMP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffff3))
+#define SET_CBR_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
+#define SET_CBR_RG_SX_SDM_D1(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffffbf))
+#define SET_CBR_RG_SX_SDM_D2(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffff7f))
+#define SET_CBR_RG_SDM_PASS(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffeff))
+#define SET_CBR_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
+#define SET_CBR_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
+#define SET_CBR_RG_SX_XO_GM(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
+#define SET_CBR_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
+#define SET_CBR_RG_SX_XO_SWCAP(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffc3fff))
+#define SET_CBR_RG_SX_SDMLUT_INV(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfffbffff))
+#define SET_CBR_RG_SX_LCKEN(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
+#define SET_CBR_RG_SX_PREVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
+#define SET_CBR_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
+#define SET_CBR_RG_SX_MOD_ERR_DELAY(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 28) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xcfffffff))
+#define SET_CBR_RG_SX_MODDB(_VAL_) (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 30) | ((REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) & 0xbfffffff))
+#define SET_CBR_RG_SX_CV_CURVE_SEL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffffffc))
+#define SET_CBR_RG_SX_SEL_DELAY(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffff83))
+#define SET_CBR_RG_SX_REF_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 7) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff87f))
+#define SET_CBR_RG_SX_VCOBY16(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xfffff7ff))
+#define SET_CBR_RG_SX_VCOBY32(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffefff))
+#define SET_CBR_RG_SX_PH(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffdfff))
+#define SET_CBR_RG_SX_PL(_VAL_) (REG32(ADR_CBR_SYN_LCK1)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_SYN_LCK1)) & 0xffffbfff))
+#define SET_CBR_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffffe))
+#define SET_CBR_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xfffffff9))
+#define SET_CBR_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffe7))
+#define SET_CBR_RG_SX_VT_SET(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffffffdf))
+#define SET_CBR_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xffff803f))
+#define SET_CBR_RG_IDEAL_CYCLE(_VAL_) (REG32(ADR_CBR_SYN_LCK2)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_SYN_LCK2)) & 0xf0007fff))
+#define SET_CBR_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xfffffff9))
+#define SET_CBR_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffffe7))
+#define SET_CBR_RG_DP_VT_MON_TMR(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffc01f))
+#define SET_CBR_RG_DP_CK320BY2(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffffbfff))
+#define SET_CBR_RG_SX_DELCTRL(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffe07fff))
+#define SET_CBR_RG_DP_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_DPLL_VCO_REGISTER)) & 0xffdfffff))
+#define SET_CBR_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
+#define SET_CBR_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
+#define SET_CBR_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
+#define SET_CBR_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
+#define SET_CBR_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
+#define SET_CBR_RG_DP_RP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
+#define SET_CBR_RG_DP_RHP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
+#define SET_CBR_RG_DP_DR3(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xff8fffff))
+#define SET_CBR_RG_DP_DCP(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0xf87fffff))
+#define SET_CBR_RG_DP_DCS(_VAL_) (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) & 0x87ffffff))
+#define SET_CBR_RG_DP_FBDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xfffff000))
+#define SET_CBR_RG_DP_FODIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0xffc00fff))
+#define SET_CBR_RG_DP_REFDIV(_VAL_) (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) & 0x003fffff))
+#define SET_CBR_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
+#define SET_CBR_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
+#define SET_CBR_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
+#define SET_CBR_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
+#define SET_CBR_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
+#define SET_CBR_RG_EN_RCAL(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_RCAL_SPD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffffd))
+#define SET_CBR_RG_RCAL_TMR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffe03))
+#define SET_CBR_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xfffffdff))
+#define SET_CBR_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_CBR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RCAL_REGISTER)) & 0xffff83ff))
+#define SET_CBR_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffffe))
+#define SET_CBR_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffffff01))
+#define SET_CBR_RG_DP_BBPLL_BS_CWR(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xfffffeff))
+#define SET_CBR_RG_DP_BBPLL_BS_CWD(_VAL_) (REG32(ADR_CBR_MANUAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_MANUAL_REGISTER)) & 0xffff81ff))
+#define SET_CBR_RCAL_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
+#define SET_CBR_DA_LCK_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
+#define SET_CBR_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
+#define SET_CBR_DP_VT_MON_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffffff7))
+#define SET_CBR_CH_RDY(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffffef))
+#define SET_CBR_DA_R_CODE_LUT(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
+#define SET_CBR_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
+#define SET_CBR_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
+#define SET_CBR_DA_R_CAL_CODE(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
+#define SET_CBR_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
+#define SET_CBR_DA_DP_BBPLL_BS(_VAL_) (REG32(ADR_CBR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_READ_ONLY_FLAGS_2)) & 0xfffc0fff))
+#define SET_CBR_TX_EN(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffe))
+#define SET_CBR_TX_CNT_RST(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfffffffd))
+#define SET_CBR_IFS_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xffffff03))
+#define SET_CBR_LENGTH_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0xfff000ff))
+#define SET_CBR_TX_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_RG_PKT_GEN_0)) & 0x00ffffff))
+#define SET_CBR_TC_CNT_TARGET(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_1)) & 0xff000000))
+#define SET_CBR_PLCP_PSDU_DATA_MEM(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffffff00))
+#define SET_CBR_PLCP_PSDU_PREAMBLE_SHORT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xfffffeff))
+#define SET_CBR_PLCP_BYTE_LENGTH(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xffe001ff))
+#define SET_CBR_PLCP_PSDU_RATE(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 21) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xff9fffff))
+#define SET_CBR_TAIL_TIME(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_2)) = (((_VAL_) << 23) | ((REG32(ADR_CBR_RG_PKT_GEN_2)) & 0xe07fffff))
+#define SET_CBR_RG_O_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffe))
+#define SET_CBR_RG_I_PAD_PD(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 1) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffd))
+#define SET_CBR_SEL_ADCKP_INV(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 2) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffffb))
+#define SET_CBR_RG_PAD_DS(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 3) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffff7))
+#define SET_CBR_SEL_ADCKP_MUX(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 4) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffef))
+#define SET_CBR_RG_PAD_DS_CLK(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffffdf))
+#define SET_CBR_INTP_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffdff))
+#define SET_CBR_IQ_SWP(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 10) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffffbff))
+#define SET_CBR_RG_EN_EXT_DA(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 11) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfffff7ff))
+#define SET_CBR_RG_DIS_DA_OFFSET(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 12) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffffefff))
+#define SET_CBR_DBG_SEL(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xfff0ffff))
+#define SET_CBR_DBG_EN(_VAL_) (REG32(ADR_CBR_RG_INTEGRATION)) = (((_VAL_) << 20) | ((REG32(ADR_CBR_RG_INTEGRATION)) & 0xffefffff))
+#define SET_CBR_RG_PKT_GEN_TX_CNT(_VAL_) (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) & 0x00000000))
+#define SET_CBR_TP_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 0) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffe0))
+#define SET_CBR_IDEAL_IQ_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 5) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xffffffdf))
+#define SET_CBR_DATA_OUT_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 6) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffe3f))
+#define SET_CBR_TWO_TONE_EN(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 9) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xfffffdff))
+#define SET_CBR_FREQ_SEL(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 16) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0xff00ffff))
+#define SET_CBR_IQ_SCALE(_VAL_) (REG32(ADR_CBR_PATTERN_GEN)) = (((_VAL_) << 24) | ((REG32(ADR_CBR_PATTERN_GEN)) & 0x00ffffff))
+#define SET_CPU_QUE_POP(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 0) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffe))
+#define SET_CPU_INT(_VAL_) (REG32(ADR_MB_CPU_INT)) = (((_VAL_) << 2) | ((REG32(ADR_MB_CPU_INT)) & 0xfffffffb))
+#define SET_CPU_ID_TB0(_VAL_) (REG32(ADR_CPU_ID_TB0)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB0)) & 0x00000000))
+#define SET_CPU_ID_TB1(_VAL_) (REG32(ADR_CPU_ID_TB1)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB1)) & 0x00000000))
+#define SET_HW_PKTID(_VAL_) (REG32(ADR_CH0_TRIG_1)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_1)) & 0xfffff800))
+#define SET_CH0_INT_ADDR(_VAL_) (REG32(ADR_CH0_TRIG_0)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_TRIG_0)) & 0x00000000))
+#define SET_PRI_HW_PKTID(_VAL_) (REG32(ADR_CH0_PRI_TRIG)) = (((_VAL_) << 0) | ((REG32(ADR_CH0_PRI_TRIG)) & 0xfffff800))
+#define SET_CH0_FULL(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffe))
+#define SET_FF0_EMPTY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MCU_STATUS)) & 0xfffffffd))
+#define SET_RLS_BUSY(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 9) | ((REG32(ADR_MCU_STATUS)) & 0xfffffdff))
+#define SET_RLS_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 10) | ((REG32(ADR_MCU_STATUS)) & 0xfffffbff))
+#define SET_RTN_COUNT_CLR(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 11) | ((REG32(ADR_MCU_STATUS)) & 0xfffff7ff))
+#define SET_RLS_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MCU_STATUS)) & 0xff00ffff))
+#define SET_RTN_COUNT(_VAL_) (REG32(ADR_MCU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MCU_STATUS)) & 0x00ffffff))
+#define SET_FF0_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffffe0))
+#define SET_FF1_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfffffe1f))
+#define SET_FF3_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xffffc7ff))
+#define SET_FF5_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 17) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfff1ffff))
+#define SET_FF6_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xff8fffff))
+#define SET_FF7_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 23) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xfc7fffff))
+#define SET_FF8_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 26) | ((REG32(ADR_RD_IN_FFCNT1)) & 0xe3ffffff))
+#define SET_FF9_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT1)) = (((_VAL_) << 29) | ((REG32(ADR_RD_IN_FFCNT1)) & 0x1fffffff))
+#define SET_FF10_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffff8))
+#define SET_FF11_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 3) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffffc7))
+#define SET_FF12_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 6) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffffe3f))
+#define SET_FF13_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 9) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfffff9ff))
+#define SET_FF14_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 11) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffffe7ff))
+#define SET_FF15_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 13) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xffff9fff))
+#define SET_FF4_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xfff07fff))
+#define SET_FF2_CNT(_VAL_) (REG32(ADR_RD_IN_FFCNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_IN_FFCNT2)) & 0xff8fffff))
+#define SET_CH1_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffd))
+#define SET_CH2_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffffb))
+#define SET_CH3_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffff7))
+#define SET_CH4_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffef))
+#define SET_CH5_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffdf))
+#define SET_CH6_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffffbf))
+#define SET_CH7_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffff7f))
+#define SET_CH8_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffeff))
+#define SET_CH9_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffdff))
+#define SET_CH10_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffffbff))
+#define SET_CH11_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFIN_FULL)) & 0xfffff7ff))
+#define SET_CH12_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffefff))
+#define SET_CH13_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffdfff))
+#define SET_CH14_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffffbfff))
+#define SET_CH15_FULL(_VAL_) (REG32(ADR_RD_FFIN_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFIN_FULL)) & 0xffff7fff))
+#define SET_HALT_CH0(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffe))
+#define SET_HALT_CH1(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffd))
+#define SET_HALT_CH2(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 2) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffffb))
+#define SET_HALT_CH3(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 3) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffff7))
+#define SET_HALT_CH4(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffef))
+#define SET_HALT_CH5(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffdf))
+#define SET_HALT_CH6(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffffbf))
+#define SET_HALT_CH7(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffff7f))
+#define SET_HALT_CH8(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 8) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffeff))
+#define SET_HALT_CH9(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 9) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffdff))
+#define SET_HALT_CH10(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 10) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffffbff))
+#define SET_HALT_CH11(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 11) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffff7ff))
+#define SET_HALT_CH12(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 12) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffefff))
+#define SET_HALT_CH13(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 13) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffdfff))
+#define SET_HALT_CH14(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 14) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffffbfff))
+#define SET_HALT_CH15(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 15) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffff7fff))
+#define SET_STOP_MBOX(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xfffeffff))
+#define SET_MB_ERR_AUTO_HALT_EN(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 20) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffefffff))
+#define SET_MB_EXCEPT_CLR(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 21) | ((REG32(ADR_MBOX_HALT_CFG)) & 0xffdfffff))
+#define SET_MB_EXCEPT_CASE(_VAL_) (REG32(ADR_MBOX_HALT_CFG)) = (((_VAL_) << 24) | ((REG32(ADR_MBOX_HALT_CFG)) & 0x00ffffff))
+#define SET_MB_DBG_TIME_STEP(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG1)) & 0xffff0000))
+#define SET_DBG_TYPE(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffcffff))
+#define SET_MB_DBG_CLR(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfffbffff))
+#define SET_DBG_ALC_LOG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfff7ffff))
+#define SET_MB_DBG_COUNTER_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG1)) & 0xfeffffff))
+#define SET_MB_DBG_EN(_VAL_) (REG32(ADR_MB_DBG_CFG1)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG1)) & 0x7fffffff))
+#define SET_MB_DBG_RECORD_CNT(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000))
+#define SET_MB_DBG_LENGTH(_VAL_) (REG32(ADR_MB_DBG_CFG2)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff))
+#define SET_MB_DBG_CFG_ADDR(_VAL_) (REG32(ADR_MB_DBG_CFG3)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG3)) & 0x00000000))
+#define SET_DBG_HWID0_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 0) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffe))
+#define SET_DBG_HWID1_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 1) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffd))
+#define SET_DBG_HWID2_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 2) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffffb))
+#define SET_DBG_HWID3_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 3) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffff7))
+#define SET_DBG_HWID4_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 4) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffef))
+#define SET_DBG_HWID5_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 5) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffdf))
+#define SET_DBG_HWID6_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 6) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffffbf))
+#define SET_DBG_HWID7_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 7) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffff7f))
+#define SET_DBG_HWID8_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 8) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffeff))
+#define SET_DBG_HWID9_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 9) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffdff))
+#define SET_DBG_HWID10_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 10) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffffbff))
+#define SET_DBG_HWID11_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 11) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffff7ff))
+#define SET_DBG_HWID12_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 12) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffefff))
+#define SET_DBG_HWID13_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 13) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffdfff))
+#define SET_DBG_HWID14_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 14) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffffbfff))
+#define SET_DBG_HWID15_WR_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 15) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffff7fff))
+#define SET_DBG_HWID0_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 16) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffeffff))
+#define SET_DBG_HWID1_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 17) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffdffff))
+#define SET_DBG_HWID2_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 18) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfffbffff))
+#define SET_DBG_HWID3_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 19) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfff7ffff))
+#define SET_DBG_HWID4_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 20) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffefffff))
+#define SET_DBG_HWID5_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 21) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffdfffff))
+#define SET_DBG_HWID6_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 22) | ((REG32(ADR_MB_DBG_CFG4)) & 0xffbfffff))
+#define SET_DBG_HWID7_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 23) | ((REG32(ADR_MB_DBG_CFG4)) & 0xff7fffff))
+#define SET_DBG_HWID8_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 24) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfeffffff))
+#define SET_DBG_HWID9_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 25) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfdffffff))
+#define SET_DBG_HWID10_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 26) | ((REG32(ADR_MB_DBG_CFG4)) & 0xfbffffff))
+#define SET_DBG_HWID11_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 27) | ((REG32(ADR_MB_DBG_CFG4)) & 0xf7ffffff))
+#define SET_DBG_HWID12_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 28) | ((REG32(ADR_MB_DBG_CFG4)) & 0xefffffff))
+#define SET_DBG_HWID13_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 29) | ((REG32(ADR_MB_DBG_CFG4)) & 0xdfffffff))
+#define SET_DBG_HWID14_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 30) | ((REG32(ADR_MB_DBG_CFG4)) & 0xbfffffff))
+#define SET_DBG_HWID15_RD_EN(_VAL_) (REG32(ADR_MB_DBG_CFG4)) = (((_VAL_) << 31) | ((REG32(ADR_MB_DBG_CFG4)) & 0x7fffffff))
+#define SET_MB_OUT_QUEUE_EN(_VAL_) (REG32(ADR_MB_OUT_QUEUE_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0xfffffffd))
+#define SET_CH0_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffe))
+#define SET_CH1_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffd))
+#define SET_CH2_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffffb))
+#define SET_CH3_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffff7))
+#define SET_CH4_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffef))
+#define SET_CH5_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffdf))
+#define SET_CH6_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffffbf))
+#define SET_CH7_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffff7f))
+#define SET_CH8_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffeff))
+#define SET_CH9_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffdff))
+#define SET_CH10_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffffbff))
+#define SET_CH11_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xfffff7ff))
+#define SET_CH12_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffefff))
+#define SET_CH13_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffdfff))
+#define SET_CH14_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffffbfff))
+#define SET_CH15_QUEUE_FLUSH(_VAL_) (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (((_VAL_) << 15) | ((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0xffff7fff))
+#define SET_FFO0_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffffffe0))
+#define SET_FFO1_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffffc1f))
+#define SET_FFO2_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfffff3ff))
+#define SET_FFO3_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xfff07fff))
+#define SET_FFO4_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xffcfffff))
+#define SET_FFO5_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT1)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT1)) & 0xf1ffffff))
+#define SET_FFO6_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffff0))
+#define SET_FFO7_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfffffc1f))
+#define SET_FFO8_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xffff83ff))
+#define SET_FFO9_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xfff07fff))
+#define SET_FFO10_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 20) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xff0fffff))
+#define SET_FFO11_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT2)) = (((_VAL_) << 25) | ((REG32(ADR_RD_FFOUT_CNT2)) & 0xc1ffffff))
+#define SET_FFO12_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffffff8))
+#define SET_FFO13_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffffff9f))
+#define SET_FFO14_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xfffff3ff))
+#define SET_FFO15_CNT(_VAL_) (REG32(ADR_RD_FFOUT_CNT3)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_CNT3)) & 0xffe07fff))
+#define SET_CH0_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 0) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffe))
+#define SET_CH1_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 1) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffd))
+#define SET_CH2_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 2) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffffb))
+#define SET_CH3_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 3) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffff7))
+#define SET_CH4_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 4) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffef))
+#define SET_CH5_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 5) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffdf))
+#define SET_CH6_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 6) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffffbf))
+#define SET_CH7_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 7) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffff7f))
+#define SET_CH8_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 8) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffeff))
+#define SET_CH9_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 9) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffdff))
+#define SET_CH10_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 10) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffffbff))
+#define SET_CH11_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 11) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xfffff7ff))
+#define SET_CH12_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 12) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffefff))
+#define SET_CH13_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 13) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffdfff))
+#define SET_CH14_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 14) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffffbfff))
+#define SET_CH15_FFO_FULL(_VAL_) (REG32(ADR_RD_FFOUT_FULL)) = (((_VAL_) << 15) | ((REG32(ADR_RD_FFOUT_FULL)) & 0xffff7fff))
+#define SET_CH0_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffe))
+#define SET_CH1_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 1) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffd))
+#define SET_CH2_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 2) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffffb))
+#define SET_CH3_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 3) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffff7))
+#define SET_CH4_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 4) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffef))
+#define SET_CH5_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 5) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffdf))
+#define SET_CH6_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 6) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffffbf))
+#define SET_CH7_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 7) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffff7f))
+#define SET_CH8_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffeff))
+#define SET_CH9_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 9) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffdff))
+#define SET_CH10_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 10) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffffbff))
+#define SET_CH11_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 11) | ((REG32(ADR_MB_THRESHOLD6)) & 0xfffff7ff))
+#define SET_CH12_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 12) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffefff))
+#define SET_CH13_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 13) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffdfff))
+#define SET_CH14_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 14) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffffbfff))
+#define SET_CH15_LOWTHOLD_INT(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 15) | ((REG32(ADR_MB_THRESHOLD6)) & 0xffff7fff))
+#define SET_MB_LOW_THOLD_EN(_VAL_) (REG32(ADR_MB_THRESHOLD6)) = (((_VAL_) << 31) | ((REG32(ADR_MB_THRESHOLD6)) & 0x7fffffff))
+#define SET_CH0_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffffe0))
+#define SET_CH1_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffffe0ff))
+#define SET_CH2_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD7)) & 0xffe0ffff))
+#define SET_CH3_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD7)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD7)) & 0xe0ffffff))
+#define SET_CH4_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffffe0))
+#define SET_CH5_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffffe0ff))
+#define SET_CH6_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD8)) & 0xffe0ffff))
+#define SET_CH7_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD8)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD8)) & 0xe0ffffff))
+#define SET_CH8_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffffe0))
+#define SET_CH9_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffffe0ff))
+#define SET_CH10_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD9)) & 0xffe0ffff))
+#define SET_CH11_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD9)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD9)) & 0xe0ffffff))
+#define SET_CH12_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 0) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffffe0))
+#define SET_CH13_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 8) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffffe0ff))
+#define SET_CH14_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 16) | ((REG32(ADR_MB_THRESHOLD10)) & 0xffe0ffff))
+#define SET_CH15_LOWTHOLD(_VAL_) (REG32(ADR_MB_THRESHOLD10)) = (((_VAL_) << 24) | ((REG32(ADR_MB_THRESHOLD10)) & 0xe0ffffff))
+#define SET_TRASH_TIMEOUT_EN(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 0) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffe))
+#define SET_TRASH_CAN_INT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 1) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffffffd))
+#define SET_TRASH_INT_ID(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfffff80f))
+#define SET_TRASH_TIMEOUT(_VAL_) (REG32(ADR_MB_TRASH_CFG)) = (((_VAL_) << 16) | ((REG32(ADR_MB_TRASH_CFG)) & 0xfc00ffff))
+#define SET_CH0_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffe))
+#define SET_CH1_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 1) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffd))
+#define SET_CH2_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 2) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffffb))
+#define SET_CH3_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 3) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffff7))
+#define SET_CH4_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 4) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffef))
+#define SET_CH5_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 5) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffdf))
+#define SET_CH6_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 6) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffffbf))
+#define SET_CH7_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 7) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffff7f))
+#define SET_CH8_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 8) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffeff))
+#define SET_CH9_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 9) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffdff))
+#define SET_CH10_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 10) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffffbff))
+#define SET_CH11_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 11) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xfffff7ff))
+#define SET_CH12_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 12) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffefff))
+#define SET_CH13_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 13) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffdfff))
+#define SET_CH14_WRFF_FLUSH(_VAL_) (REG32(ADR_MB_IN_FF_FLUSH)) = (((_VAL_) << 14) | ((REG32(ADR_MB_IN_FF_FLUSH)) & 0xffffbfff))
+#define SET_CPU_ID_TB2(_VAL_) (REG32(ADR_CPU_ID_TB2)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB2)) & 0x00000000))
+#define SET_CPU_ID_TB3(_VAL_) (REG32(ADR_CPU_ID_TB3)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_ID_TB3)) & 0x00000000))
+#define SET_IQ_LOG_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0xfffffffe))
+#define SET_IQ_LOG_STOP_MODE(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xfffffffe))
+#define SET_GPIO_STOP_EN(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffef))
+#define SET_GPIO_STOP_POL(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffffffdf))
+#define SET_IQ_LOG_TIMER(_VAL_) (REG32(ADR_PHY_IQ_LOG_CFG1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x0000ffff))
+#define SET_IQ_LOG_LEN(_VAL_) (REG32(ADR_PHY_IQ_LOG_LEN)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_LEN)) & 0xffff0000))
+#define SET_IQ_LOG_TAIL_ADR(_VAL_) (REG32(ADR_PHY_IQ_LOG_PTR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_IQ_LOG_PTR)) & 0xffff0000))
+#define SET_ALC_LENG(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 0) | ((REG32(ADR_WR_ALC)) & 0xfffc0000))
+#define SET_CH0_DYN_PRI(_VAL_) (REG32(ADR_WR_ALC)) = (((_VAL_) << 20) | ((REG32(ADR_WR_ALC)) & 0xffcfffff))
+#define SET_MCU_PKTID(_VAL_) (REG32(ADR_GETID)) = (((_VAL_) << 0) | ((REG32(ADR_GETID)) & 0x00000000))
+#define SET_CH0_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffffc))
+#define SET_CH1_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_STA_PRI)) & 0xffffffcf))
+#define SET_CH2_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_STA_PRI)) & 0xfffffcff))
+#define SET_CH3_STA_PRI(_VAL_) (REG32(ADR_CH_STA_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_STA_PRI)) & 0xffffcfff))
+#define SET_ID_TB0(_VAL_) (REG32(ADR_RD_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID0)) & 0x00000000))
+#define SET_ID_TB1(_VAL_) (REG32(ADR_RD_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID1)) & 0x00000000))
+#define SET_ID_MNG_HALT(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_CFG)) & 0xffffffef))
+#define SET_ID_MNG_ERR_HALT_EN(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_CFG)) & 0xffffffdf))
+#define SET_ID_EXCEPT_FLG_CLR(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_CFG)) & 0xffffffbf))
+#define SET_ID_EXCEPT_FLG(_VAL_) (REG32(ADR_IMD_CFG)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_CFG)) & 0xffffff7f))
+#define SET_ID_FULL(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 0) | ((REG32(ADR_IMD_STA)) & 0xfffffffe))
+#define SET_ID_MNG_BUSY(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 1) | ((REG32(ADR_IMD_STA)) & 0xfffffffd))
+#define SET_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 2) | ((REG32(ADR_IMD_STA)) & 0xfffffffb))
+#define SET_CH0_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 4) | ((REG32(ADR_IMD_STA)) & 0xffffffef))
+#define SET_CH1_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 5) | ((REG32(ADR_IMD_STA)) & 0xffffffdf))
+#define SET_CH2_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 6) | ((REG32(ADR_IMD_STA)) & 0xffffffbf))
+#define SET_CH3_REQ_LOCK(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 7) | ((REG32(ADR_IMD_STA)) & 0xffffff7f))
+#define SET_REQ_LOCK_INT_EN(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 8) | ((REG32(ADR_IMD_STA)) & 0xfffffeff))
+#define SET_REQ_LOCK_INT(_VAL_) (REG32(ADR_IMD_STA)) = (((_VAL_) << 9) | ((REG32(ADR_IMD_STA)) & 0xfffffdff))
+#define SET_MCU_ALC_READY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_STA)) & 0xfffffffe))
+#define SET_ALC_FAIL(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 1) | ((REG32(ADR_ALC_STA)) & 0xfffffffd))
+#define SET_ALC_BUSY(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 2) | ((REG32(ADR_ALC_STA)) & 0xfffffffb))
+#define SET_CH0_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 4) | ((REG32(ADR_ALC_STA)) & 0xffffffef))
+#define SET_CH1_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 5) | ((REG32(ADR_ALC_STA)) & 0xffffffdf))
+#define SET_CH2_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 6) | ((REG32(ADR_ALC_STA)) & 0xffffffbf))
+#define SET_CH3_NVLD(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 7) | ((REG32(ADR_ALC_STA)) & 0xffffff7f))
+#define SET_ALC_INT_ID(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_STA)) & 0xffff80ff))
+#define SET_ALC_TIMEOUT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_STA)) & 0xfc00ffff))
+#define SET_ALC_TIMEOUT_INT_EN(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 30) | ((REG32(ADR_ALC_STA)) & 0xbfffffff))
+#define SET_ALC_TIMEOUT_INT(_VAL_) (REG32(ADR_ALC_STA)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_STA)) & 0x7fffffff))
+#define SET_TX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffffff00))
+#define SET_RX_ID_COUNT(_VAL_) (REG32(ADR_TRX_ID_COUNT)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_COUNT)) & 0xffff00ff))
+#define SET_TX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffffff00))
+#define SET_RX_ID_THOLD(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffff00ff))
+#define SET_ID_THOLD_RX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfffeffff))
+#define SET_RX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 17) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfff1ffff))
+#define SET_ID_THOLD_TX_INT(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 20) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xffefffff))
+#define SET_TX_INT_CH(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 21) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xff1fffff))
+#define SET_ID_THOLD_INT_EN(_VAL_) (REG32(ADR_TRX_ID_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_TRX_ID_THRESHOLD)) & 0xfeffffff))
+#define SET_TX_ID_TB0(_VAL_) (REG32(ADR_TX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID0)) & 0x00000000))
+#define SET_TX_ID_TB1(_VAL_) (REG32(ADR_TX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID1)) & 0x00000000))
+#define SET_RX_ID_TB0(_VAL_) (REG32(ADR_RX_ID0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID0)) & 0x00000000))
+#define SET_RX_ID_TB1(_VAL_) (REG32(ADR_RX_ID1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID1)) & 0x00000000))
+#define SET_DOUBLE_RLS_INT_EN(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 0) | ((REG32(ADR_RTN_STA)) & 0xfffffffe))
+#define SET_ID_DOUBLE_RLS_INT(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 1) | ((REG32(ADR_RTN_STA)) & 0xfffffffd))
+#define SET_DOUBLE_RLS_ID(_VAL_) (REG32(ADR_RTN_STA)) = (((_VAL_) << 8) | ((REG32(ADR_RTN_STA)) & 0xffff80ff))
+#define SET_ID_LEN_THOLD_INT_EN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffe))
+#define SET_ALL_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 1) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffd))
+#define SET_TX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 2) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffffb))
+#define SET_RX_ID_LEN_THOLD_INT(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 3) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xfffffff7))
+#define SET_ID_TX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 4) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffffe00f))
+#define SET_ID_RX_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 13) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0xffc01fff))
+#define SET_ID_LEN_THOLD(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD1)) = (((_VAL_) << 22) | ((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x803fffff))
+#define SET_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 0) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffffe00))
+#define SET_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 9) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xfffc01ff))
+#define SET_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ID_LEN_THREADSHOLD2)) = (((_VAL_) << 18) | ((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0xf803ffff))
+#define SET_CH_ARB_EN(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 0) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffffe))
+#define SET_CH_PRI1(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 4) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffffcf))
+#define SET_CH_PRI2(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 8) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffffcff))
+#define SET_CH_PRI3(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 12) | ((REG32(ADR_CH_ARB_PRI)) & 0xffffcfff))
+#define SET_CH_PRI4(_VAL_) (REG32(ADR_CH_ARB_PRI)) = (((_VAL_) << 16) | ((REG32(ADR_CH_ARB_PRI)) & 0xfffcffff))
+#define SET_TX_ID_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xffffff80))
+#define SET_TX_PAGE_REMAIN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0xfffe00ff))
+#define SET_ID_PAGE_MAX_SIZE(_VAL_) (REG32(ADR_ID_INFO_STA)) = (((_VAL_) << 0) | ((REG32(ADR_ID_INFO_STA)) & 0xfffffe00))
+#define SET_TX_PAGE_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xfffffe00))
+#define SET_TX_COUNT_LIMIT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xff00ffff))
+#define SET_TX_LIMIT_INT(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 30) | ((REG32(ADR_TX_LIMIT_INTR)) & 0xbfffffff))
+#define SET_TX_LIMIT_INT_EN(_VAL_) (REG32(ADR_TX_LIMIT_INTR)) = (((_VAL_) << 31) | ((REG32(ADR_TX_LIMIT_INTR)) & 0x7fffffff))
+#define SET_TX_PAGE_USE_7_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffff00))
+#define SET_TX_ID_USE_5_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffffc0ff))
+#define SET_EDCA0_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 14) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xfffc3fff))
+#define SET_EDCA1_FFO_CNT_3_0(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 18) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xffc3ffff))
+#define SET_EDCA2_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0xf83fffff))
+#define SET_EDCA3_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO)) = (((_VAL_) << 27) | ((REG32(ADR_TX_ID_ALL_INFO)) & 0x07ffffff))
+#define SET_ID_TB2(_VAL_) (REG32(ADR_RD_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID2)) & 0x00000000))
+#define SET_ID_TB3(_VAL_) (REG32(ADR_RD_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RD_ID3)) & 0x00000000))
+#define SET_TX_ID_TB2(_VAL_) (REG32(ADR_TX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID2)) & 0x00000000))
+#define SET_TX_ID_TB3(_VAL_) (REG32(ADR_TX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID3)) & 0x00000000))
+#define SET_RX_ID_TB2(_VAL_) (REG32(ADR_RX_ID2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID2)) & 0x00000000))
+#define SET_RX_ID_TB3(_VAL_) (REG32(ADR_RX_ID3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ID3)) & 0x00000000))
+#define SET_TX_PAGE_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffffe00))
+#define SET_TX_ID_USE2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xfffe01ff))
+#define SET_EDCA4_FFO_CNT(_VAL_) (REG32(ADR_TX_ID_ALL_INFO2)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO2)) & 0xffe1ffff))
+#define SET_TX_PAGE_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffffe00))
+#define SET_TX_ID_USE3(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfffe01ff))
+#define SET_EDCA1_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 21) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xfc1fffff))
+#define SET_EDCA4_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_A)) = (((_VAL_) << 26) | ((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xc3ffffff))
+#define SET_TX_PAGE_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffffe00))
+#define SET_TX_ID_USE4(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 9) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xfffe01ff))
+#define SET_EDCA2_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 17) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xffc1ffff))
+#define SET_EDCA3_FFO_CNT2(_VAL_) (REG32(ADR_TX_ID_ALL_INFO_B)) = (((_VAL_) << 22) | ((REG32(ADR_TX_ID_ALL_INFO_B)) & 0xf83fffff))
+#define SET_TX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfffffe00))
+#define SET_RX_ID_IFO_LEN(_VAL_) (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0xfe00ffff))
+#define SET_MAX_ALL_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INFO)) & 0xffffff00))
+#define SET_MAX_TX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 8) | ((REG32(ADR_ALC_ID_INFO)) & 0xffff00ff))
+#define SET_MAX_RX_ALC_ID_CNT(_VAL_) (REG32(ADR_ALC_ID_INFO)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_ID_INFO)) & 0xff00ffff))
+#define SET_MAX_ALL_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffffe00))
+#define SET_MAX_TX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 9) | ((REG32(ADR_ALC_ID_INF1)) & 0xfffc01ff))
+#define SET_MAX_RX_ID_ALC_LEN(_VAL_) (REG32(ADR_ALC_ID_INF1)) = (((_VAL_) << 18) | ((REG32(ADR_ALC_ID_INF1)) & 0xf803ffff))
+#define SET_RG_PMDLBK(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_0)) & 0xfffffffe))
+#define SET_RG_RDYACK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff9))
+#define SET_RG_ADEDGE_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_0)) & 0xfffffff7))
+#define SET_RG_SIGN_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_0)) & 0xffffffef))
+#define SET_RG_IQ_SWAP(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_0)) & 0xffffffdf))
+#define SET_RG_Q_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_0)) & 0xffffffbf))
+#define SET_RG_I_INV(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_EN_0)) & 0xffffff7f))
+#define SET_RG_BYPASS_ACI(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_0)) & 0xfffffeff))
+#define SET_RG_LBK_ANA_PATH(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_EN_0)) & 0xfffffdff))
+#define SET_RG_SPECTRUM_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_EN_0)) & 0xfffff3ff))
+#define SET_RG_SPECTRUM_BW(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_0)) & 0xffffcfff))
+#define SET_RG_SPECTRUM_FREQ_MANUAL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_0)) & 0xffffbfff))
+#define SET_RG_SPECTRUM_EN(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_0)) & 0xffff7fff))
+#define SET_RG_TXPWRLVL_SET(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_0)) & 0xff00ffff))
+#define SET_RG_TXPWRLVL_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_EN_0)) & 0xfeffffff))
+#define SET_RG_RF_BB_CLK_SEL(_VAL_) (REG32(ADR_PHY_EN_0)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_EN_0)) & 0x7fffffff))
+#define SET_RG_PHY_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffe))
+#define SET_RG_PHYRX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffd))
+#define SET_RG_PHYTX_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_EN_1)) & 0xfffffffb))
+#define SET_RG_PHY11GN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_EN_1)) & 0xfffffff7))
+#define SET_RG_PHY11B_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_EN_1)) & 0xffffffef))
+#define SET_RG_PHYRXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_EN_1)) & 0xffffffdf))
+#define SET_RG_PHYTXFIFO_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_EN_1)) & 0xffffffbf))
+#define SET_RG_PHY11BGN_MD_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_EN_1)) & 0xfffffeff))
+#define SET_RG_FORCE_11GN_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_EN_1)) & 0xffffefff))
+#define SET_RG_FORCE_11B_EN(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 13) | ((REG32(ADR_PHY_EN_1)) & 0xffffdfff))
+#define SET_RG_FFT_MEM_CLK_EN_RX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_EN_1)) & 0xffffbfff))
+#define SET_RG_FFT_MEM_CLK_EN_TX(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_EN_1)) & 0xffff7fff))
+#define SET_RG_PHY_IQ_TRIG_SEL(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_EN_1)) & 0xfff0ffff))
+#define SET_RG_SPECTRUM_FREQ(_VAL_) (REG32(ADR_PHY_EN_1)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_EN_1)) & 0xc00fffff))
+#define SET_SVN_VERSION(_VAL_) (REG32(ADR_SVN_VERSION_REG)) = (((_VAL_) << 0) | ((REG32(ADR_SVN_VERSION_REG)) & 0x00000000))
+#define SET_RG_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffff0000))
+#define SET_RG_PKT_MODE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xfff8ffff))
+#define SET_RG_CH_BW(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 19) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffc7ffff))
+#define SET_RG_PRM(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 22) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xffbfffff))
+#define SET_RG_SHORTGI(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0xff7fffff))
+#define SET_RG_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_0)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_PKT_GEN_0)) & 0x80ffffff))
+#define SET_RG_L_LENGTH(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xfffff000))
+#define SET_RG_L_RATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0xffff8fff))
+#define SET_RG_SERVICE(_VAL_) (REG32(ADR_PHY_PKT_GEN_1)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_1)) & 0x0000ffff))
+#define SET_RG_SMOOTHING(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffe))
+#define SET_RG_NO_SOUND(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffd))
+#define SET_RG_AGGREGATE(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xfffffffb))
+#define SET_RG_STBC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffe7))
+#define SET_RG_FEC(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffffdf))
+#define SET_RG_N_ESS(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffffff3f))
+#define SET_RG_TXPWRLVL(_VAL_) (REG32(ADR_PHY_PKT_GEN_2)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_2)) & 0xffff00ff))
+#define SET_RG_TX_START(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffffe))
+#define SET_RG_IFS_TIME(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 2) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xffffff03))
+#define SET_RG_CONTINUOUS_DATA(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffffeff))
+#define SET_RG_DATA_SEL(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xfffff9ff))
+#define SET_RG_TX_D(_VAL_) (REG32(ADR_PHY_PKT_GEN_3)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_PKT_GEN_3)) & 0xff00ffff))
+#define SET_RG_TX_CNT_TARGET(_VAL_) (REG32(ADR_PHY_PKT_GEN_4)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_PKT_GEN_4)) & 0x00000000))
+#define SET_RG_FFT_IFFT_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 6) | ((REG32(ADR_PHY_REG_00)) & 0xffffff3f))
+#define SET_RG_DAC_DBG_MODE(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_00)) & 0xfffffeff))
+#define SET_RG_DAC_SGN_SWAP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 9) | ((REG32(ADR_PHY_REG_00)) & 0xfffffdff))
+#define SET_RG_TXD_SEL(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 10) | ((REG32(ADR_PHY_REG_00)) & 0xfffff3ff))
+#define SET_RG_UP8X(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_00)) & 0xff00ffff))
+#define SET_RG_IQ_DC_BYP(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_00)) & 0xfeffffff))
+#define SET_RG_IQ_DC_LEAKY_FACTOR(_VAL_) (REG32(ADR_PHY_REG_00)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_00)) & 0xcfffffff))
+#define SET_RG_DAC_DCEN(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_01)) & 0xfffffffe))
+#define SET_RG_DAC_DCQ(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_01)) & 0xffffc00f))
+#define SET_RG_DAC_DCI(_VAL_) (REG32(ADR_PHY_REG_01)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_01)) & 0xfc00ffff))
+#define SET_RG_PGA_REFDB_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffffff80))
+#define SET_RG_PGA_REFDB_TOP(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xffff80ff))
+#define SET_RG_PGA_REF_UND(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_02_AGC)) & 0xfc00ffff))
+#define SET_RG_RF_REF_SAT(_VAL_) (REG32(ADR_PHY_REG_02_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_02_AGC)) & 0x0fffffff))
+#define SET_RG_PGAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xfffffff0))
+#define SET_RG_PGAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffffef))
+#define SET_RG_RFGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 5) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff9f))
+#define SET_RG_RFGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 7) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffff7f))
+#define SET_RG_WAIT_T_RXAGC(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffc0ff))
+#define SET_RG_RXAGC_SET(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 14) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffffbfff))
+#define SET_RG_RXAGC_OW(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffff7fff))
+#define SET_RG_WAIT_T_FINAL(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xffc0ffff))
+#define SET_RG_WAIT_T(_VAL_) (REG32(ADR_PHY_REG_03_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_03_AGC)) & 0xc0ffffff))
+#define SET_RG_ULG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffffff0))
+#define SET_RG_LG_PGA_UND_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffffff0f))
+#define SET_RG_LG_PGA_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfffff0ff))
+#define SET_RG_LG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xffff0fff))
+#define SET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xfff0ffff))
+#define SET_RG_HG_PGA_SAT2_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xff0fffff))
+#define SET_RG_HG_PGA_SAT1_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_04_AGC)) & 0xf0ffffff))
+#define SET_RG_HG_RF_SAT_PGA_GAIN(_VAL_) (REG32(ADR_PHY_REG_04_AGC)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_04_AGC)) & 0x0fffffff))
+#define SET_RG_MG_PGA_JB_TH(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xfffffff0))
+#define SET_RG_MA_PGA_LOW_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xffe0ffff))
+#define SET_RG_WR_RFGC_INIT_SET(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 21) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff9fffff))
+#define SET_RG_WR_RFGC_INIT_EN(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 23) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xff7fffff))
+#define SET_RG_MA_PGA_HIGH_TH_CNT_LMT(_VAL_) (REG32(ADR_PHY_REG_05_AGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_05_AGC)) & 0xe0ffffff))
+#define SET_RG_AGC_THRESHOLD(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xffffc000))
+#define SET_RG_ACI_POINT_CNT_LMT_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xff80ffff))
+#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11B(_VAL_) (REG32(ADR_PHY_REG_06_11B_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_06_11B_DAGC)) & 0xfcffffff))
+#define SET_RG_WR_ACI_GAIN_INI_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffffff00))
+#define SET_RG_WR_ACI_GAIN_SEL_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xffff00ff))
+#define SET_RG_ACI_DAGC_SET_VALUE_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0xff80ffff))
+#define SET_RG_WR_ACI_GAIN_OW_11B(_VAL_) (REG32(ADR_PHY_REG_07_11B_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_07_11B_DAGC)) & 0x7fffffff))
+#define SET_RG_ACI_POINT_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xffffff00))
+#define SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0xfffffcff))
+#define SET_RG_ACI_DAGC_DONE_CNT_LMT_11GN(_VAL_) (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_08_11GN_DAGC)) & 0x00ffffff))
+#define SET_RG_ACI_DAGC_SET_VALUE_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffffff80))
+#define SET_RG_ACI_GAIN_INI_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xffff00ff))
+#define SET_RG_ACI_GAIN_OW_VAL_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0xff00ffff))
+#define SET_RG_ACI_GAIN_OW_11GN(_VAL_) (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_09_11GN_DAGC)) & 0x7fffffff))
+#define SET_RO_CCA_PWR_MA_11GN(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffffff80))
+#define SET_RO_ED_STATE(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 15) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xffff7fff))
+#define SET_RO_CCA_PWR_MA_11B(_VAL_) (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_00_DIG_PWR)) & 0xff80ffff))
+#define SET_RO_PGA_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xffffc000))
+#define SET_RO_RF_PWR_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xfff0ffff))
+#define SET_RO_PGAGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xf0ffffff))
+#define SET_RO_RFGC_FF1(_VAL_) (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) & 0xcfffffff))
+#define SET_RO_PGA_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xffffc000))
+#define SET_RO_RF_PWR_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xfff0ffff))
+#define SET_RO_PGAGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xf0ffffff))
+#define SET_RO_RFGC_FF2(_VAL_) (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) & 0xcfffffff))
+#define SET_RO_PGA_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xffffc000))
+#define SET_RO_RF_PWR_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xfff0ffff))
+#define SET_RO_PGAGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xf0ffffff))
+#define SET_RO_RFGC_FF3(_VAL_) (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) & 0xcfffffff))
+#define SET_RG_TX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffffe0))
+#define SET_RG_TX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffffe0ff))
+#define SET_RG_TX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xffe0ffff))
+#define SET_RG_TX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_10_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_10_TX_DES)) & 0xe0ffffff))
+#define SET_RG_TX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffffe0))
+#define SET_RG_TX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffffe0ff))
+#define SET_RG_TX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xffe0ffff))
+#define SET_RG_TX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_11_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_11_TX_DES)) & 0xe0ffffff))
+#define SET_RG_TX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffffe))
+#define SET_RG_TX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffffef))
+#define SET_RG_TX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xfffffeff))
+#define SET_RG_TX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffffefff))
+#define SET_RG_TX_DES_PWRLVL(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xffe0ffff))
+#define SET_RG_TX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_12_TX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_12_TX_DES)) & 0xe0ffffff))
+#define SET_RG_RX_DES_RATE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffffc0))
+#define SET_RG_RX_DES_MODE(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffffc0ff))
+#define SET_RG_RX_DES_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xffc0ffff))
+#define SET_RG_RX_DES_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_13_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_13_RX_DES)) & 0xc0ffffff))
+#define SET_RG_RX_DES_SRVC_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffffc0))
+#define SET_RG_RX_DES_L_LEN_LO(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffffc0ff))
+#define SET_RG_RX_DES_L_LEN_UP(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xffc0ffff))
+#define SET_RG_RX_DES_TYPE(_VAL_) (REG32(ADR_PHY_REG_14_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_14_RX_DES)) & 0xc0ffffff))
+#define SET_RG_RX_DES_L_LEN_UP_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffffe))
+#define SET_RG_RX_DES_TYPE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 4) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffffef))
+#define SET_RG_RX_DES_RATE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfffffeff))
+#define SET_RG_RX_DES_MODE_COMB(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xffffefff))
+#define SET_RG_RX_DES_SNR(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xfff0ffff))
+#define SET_RG_RX_DES_RCPI(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xff0fffff))
+#define SET_RG_RX_DES_SRVC_LO(_VAL_) (REG32(ADR_PHY_REG_15_RX_DES)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_15_RX_DES)) & 0xc0ffffff))
+#define SET_RO_TX_DES_EXCP_RATE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffffff00))
+#define SET_RO_TX_DES_EXCP_CH_BW_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xffff00ff))
+#define SET_RO_TX_DES_EXCP_MODE_CNT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xff00ffff))
+#define SET_RG_TX_DES_EXCP_RATE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0xf8ffffff))
+#define SET_RG_TX_DES_EXCP_MODE_DEFAULT(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x8fffffff))
+#define SET_RG_TX_DES_EXCP_CLR(_VAL_) (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_16_TX_DES_EXCP)) & 0x7fffffff))
+#define SET_RG_TX_DES_ACK_WIDTH(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffffe))
+#define SET_RG_TX_DES_ACK_PRD(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 1) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xfffffff1))
+#define SET_RG_RX_DES_SNR_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xffc0ffff))
+#define SET_RG_RX_DES_RCPI_GN(_VAL_) (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_17_TX_DES_EXCP)) & 0xc0ffffff))
+#define SET_RG_TST_TBUS_SEL(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfffffff0))
+#define SET_RG_RSSI_OFFSET(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xff00ffff))
+#define SET_RG_RSSI_INV(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xfeffffff))
+#define SET_RG_TST_ADC_ON(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0xbfffffff))
+#define SET_RG_TST_EXT_GAIN(_VAL_) (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_18_RSSI_SNR)) & 0x7fffffff))
+#define SET_RG_DAC_Q_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xfffffc00))
+#define SET_RG_DAC_I_SET(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 12) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xffc00fff))
+#define SET_RG_DAC_EN_MAN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xefffffff))
+#define SET_RG_IQC_FFT_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xdfffffff))
+#define SET_RG_DAC_MAN_Q_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0xbfffffff))
+#define SET_RG_DAC_MAN_I_EN(_VAL_) (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_19_DAC_MANUAL)) & 0x7fffffff))
+#define SET_RO_MRX_EN_CNT(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0xffff0000))
+#define SET_RG_MRX_EN_CNT_RST_N(_VAL_) (REG32(ADR_PHY_REG_20_MRX_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_20_MRX_CNT)) & 0x7fffffff))
+#define SET_RG_PA_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffffff00))
+#define SET_RG_RFTX_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xffff00ff))
+#define SET_RG_DAC_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0xff00ffff))
+#define SET_RG_SW_RISE_TIME(_VAL_) (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_21_TRX_RAMP)) & 0x00ffffff))
+#define SET_RG_PA_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffffff00))
+#define SET_RG_RFTX_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xffff00ff))
+#define SET_RG_DAC_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0xff00ffff))
+#define SET_RG_SW_FALL_TIME(_VAL_) (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_22_TRX_RAMP)) & 0x00ffffff))
+#define SET_RG_ANT_SW_0(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xfffffff8))
+#define SET_RG_ANT_SW_1(_VAL_) (REG32(ADR_PHY_REG_23_ANT)) = (((_VAL_) << 3) | ((REG32(ADR_PHY_REG_23_ANT)) & 0xffffffc7))
+#define SET_RG_MTX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MTX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MTX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) & 0x7fffffff))
+#define SET_RG_MTX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MTX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MTX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) & 0x7fffffff))
+#define SET_RG_MRX_LEN_LOWER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MRX_LEN_UPPER_TH_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MRX_LEN_CNT_EN_0(_VAL_) (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) & 0x7fffffff))
+#define SET_RG_MRX_LEN_LOWER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xffffe000))
+#define SET_RG_MRX_LEN_UPPER_TH_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0xe000ffff))
+#define SET_RG_MRX_LEN_CNT_EN_1(_VAL_) (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) & 0x7fffffff))
+#define SET_RO_MTX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_04)) & 0xffff0000))
+#define SET_RO_MTX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_04)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_04)) & 0x0000ffff))
+#define SET_RO_MRX_LEN_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_05)) & 0xffff0000))
+#define SET_RO_MRX_LEN_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_05)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_05)) & 0x0000ffff))
+#define SET_RG_MODE_REG_IN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffff0000))
+#define SET_RG_PARALLEL_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 20) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xffefffff))
+#define SET_RG_MBRUN_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xfeffffff))
+#define SET_RG_SHIFT_DR_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 28) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xefffffff))
+#define SET_RG_MODE_REG_SI_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 29) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xdfffffff))
+#define SET_RG_SIMULATION_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 30) | ((REG32(ADR_PHY_REG_28_BIST)) & 0xbfffffff))
+#define SET_RG_DBIST_MODE_16(_VAL_) (REG32(ADR_PHY_REG_28_BIST)) = (((_VAL_) << 31) | ((REG32(ADR_PHY_REG_28_BIST)) & 0x7fffffff))
+#define SET_RO_MODE_REG_OUT_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xffff0000))
+#define SET_RO_MODE_REG_SO_16(_VAL_) (REG32(ADR_PHY_READ_REG_06_BIST)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_READ_REG_06_BIST)) & 0xfeffffff))
+#define SET_RO_MONITOR_BUS_16(_VAL_) (REG32(ADR_PHY_READ_REG_07_BIST)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_07_BIST)) & 0xfff80000))
+#define SET_RG_MRX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffffff00))
+#define SET_RG_MRX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 8) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xffff00ff))
+#define SET_RG_MTX_TYPE_1(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0xff00ffff))
+#define SET_RG_MTX_TYPE_0(_VAL_) (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (((_VAL_) << 24) | ((REG32(ADR_PHY_REG_29_MTRX_MAC)) & 0x00ffffff))
+#define SET_RO_MTX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0xffff0000))
+#define SET_RO_MTX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) & 0x0000ffff))
+#define SET_RO_MRX_TYPE_CNT_1(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0xffff0000))
+#define SET_RO_MRX_TYPE_CNT_0(_VAL_) (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) & 0x0000ffff))
+#define SET_RG_HB_COEF0(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xfffff000))
+#define SET_RG_HB_COEF1(_VAL_) (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_30_TX_UP_FIL)) & 0xf000ffff))
+#define SET_RG_HB_COEF2(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xfffff000))
+#define SET_RG_HB_COEF3(_VAL_) (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (((_VAL_) << 16) | ((REG32(ADR_PHY_REG_31_TX_UP_FIL)) & 0xf000ffff))
+#define SET_RG_HB_COEF4(_VAL_) (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_REG_32_TX_UP_FIL)) & 0xfffff000))
+#define SET_RO_TBUS_O(_VAL_) (REG32(ADR_PHY_READ_TBUS)) = (((_VAL_) << 0) | ((REG32(ADR_PHY_READ_TBUS)) & 0xfff00000))
+#define SET_RG_LPF4_00(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_00)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_00)) & 0xffffe000))
+#define SET_RG_LPF4_01(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_01)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_01)) & 0xffffe000))
+#define SET_RG_LPF4_02(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_02)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_02)) & 0xffffe000))
+#define SET_RG_LPF4_03(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_03)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_03)) & 0xffffe000))
+#define SET_RG_LPF4_04(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_04)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_04)) & 0xffffe000))
+#define SET_RG_LPF4_05(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_05)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_05)) & 0xffffe000))
+#define SET_RG_LPF4_06(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_06)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_06)) & 0xffffe000))
+#define SET_RG_LPF4_07(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_07)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_07)) & 0xffffe000))
+#define SET_RG_LPF4_08(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_08)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_08)) & 0xffffe000))
+#define SET_RG_LPF4_09(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_09)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_09)) & 0xffffe000))
+#define SET_RG_LPF4_10(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_10)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_10)) & 0xffffe000))
+#define SET_RG_LPF4_11(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_11)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_11)) & 0xffffe000))
+#define SET_RG_LPF4_12(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_12)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_12)) & 0xffffe000))
+#define SET_RG_LPF4_13(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_13)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_13)) & 0xffffe000))
+#define SET_RG_LPF4_14(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_14)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_14)) & 0xffffe000))
+#define SET_RG_LPF4_15(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_15)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_15)) & 0xffffe000))
+#define SET_RG_LPF4_16(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_16)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_16)) & 0xffffe000))
+#define SET_RG_LPF4_17(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_17)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_17)) & 0xffffe000))
+#define SET_RG_LPF4_18(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_18)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_18)) & 0xffffe000))
+#define SET_RG_LPF4_19(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_19)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_19)) & 0xffffe000))
+#define SET_RG_LPF4_20(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_20)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_20)) & 0xffffe000))
+#define SET_RG_LPF4_21(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_21)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_21)) & 0xffffe000))
+#define SET_RG_LPF4_22(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_22)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_22)) & 0xffffe000))
+#define SET_RG_LPF4_23(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_23)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_23)) & 0xffffe000))
+#define SET_RG_LPF4_24(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_24)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_24)) & 0xffffe000))
+#define SET_RG_LPF4_25(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_25)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_25)) & 0xffffe000))
+#define SET_RG_LPF4_26(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_26)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_26)) & 0xffffe000))
+#define SET_RG_LPF4_27(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_27)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_27)) & 0xffffe000))
+#define SET_RG_LPF4_28(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_28)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_28)) & 0xffffe000))
+#define SET_RG_LPF4_29(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_29)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_29)) & 0xffffe000))
+#define SET_RG_LPF4_30(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_30)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_30)) & 0xffffe000))
+#define SET_RG_LPF4_31(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_31)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_31)) & 0xffffe000))
+#define SET_RG_LPF4_32(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_32)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_32)) & 0xffffe000))
+#define SET_RG_LPF4_33(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_33)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_33)) & 0xffffe000))
+#define SET_RG_LPF4_34(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_34)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_34)) & 0xffffe000))
+#define SET_RG_LPF4_35(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_35)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_35)) & 0xffffe000))
+#define SET_RG_LPF4_36(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_36)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_36)) & 0xffffe000))
+#define SET_RG_LPF4_37(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_37)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_37)) & 0xffffe000))
+#define SET_RG_LPF4_38(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_38)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_38)) & 0xffffe000))
+#define SET_RG_LPF4_39(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_39)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_39)) & 0xffffe000))
+#define SET_RG_LPF4_40(_VAL_) (REG32(ADR_TX_11B_FIL_COEF_40)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_FIL_COEF_40)) & 0xffffe000))
+#define SET_RG_BP_SMB(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 13) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffdfff))
+#define SET_RG_EN_SRVC(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 14) | ((REG32(ADR_TX_11B_PLCP)) & 0xffffbfff))
+#define SET_RG_DES_SPD(_VAL_) (REG32(ADR_TX_11B_PLCP)) = (((_VAL_) << 16) | ((REG32(ADR_TX_11B_PLCP)) & 0xfffcffff))
+#define SET_RG_BB_11B_RISE_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_RAMP)) & 0xffffff00))
+#define SET_RG_BB_11B_FALL_TIME(_VAL_) (REG32(ADR_TX_11B_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11B_RAMP)) & 0xffff00ff))
+#define SET_RG_WR_TX_EN_CNT_RST_N(_VAL_) (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT_RST_N)) & 0xfffffffe))
+#define SET_RO_TX_EN_CNT(_VAL_) (REG32(ADR_TX_11B_EN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_EN_CNT)) & 0xffff0000))
+#define SET_RO_TX_CNT(_VAL_) (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11B_PKT_GEN_CNT)) & 0x00000000))
+#define SET_RG_POS_DES_11B_L_EXT(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xfffffff0))
+#define SET_RG_PRE_DES_11B_DLY(_VAL_) (REG32(ADR_RX_11B_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_DES_DLY)) & 0xffffff0f))
+#define SET_RG_CNT_CCA_LMT(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_0)) & 0xfff0ffff))
+#define SET_RG_BYPASS_DESCRAMBLER(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11B_CCA_0)) & 0xdfffffff))
+#define SET_RG_BYPASS_AGC(_VAL_) (REG32(ADR_RX_11B_CCA_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11B_CCA_0)) & 0x7fffffff))
+#define SET_RG_CCA_BIT_CNT_LMT_RX(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CCA_1)) & 0xffffff0f))
+#define SET_RG_CCA_SCALE_BF(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_1)) & 0xff80ffff))
+#define SET_RG_PEAK_IDX_CNT_SEL(_VAL_) (REG32(ADR_RX_11B_CCA_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11B_CCA_1)) & 0xcfffffff))
+#define SET_RG_TR_KI_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffffff8))
+#define SET_RG_TR_KP_T2(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffffff8f))
+#define SET_RG_TR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xfffff8ff))
+#define SET_RG_TR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_0)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_TR_KP_KI_0)) & 0xffff8fff))
+#define SET_RG_CR_KI_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xfff8ffff))
+#define SET_RG_CR_KP_T1(_VAL_) (REG32(ADR_RX_11B_TR_KP_KI_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_TR_KP_KI_1)) & 0xff8fffff))
+#define SET_RG_CHIP_CNT_SLICER(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffffffe0))
+#define SET_RG_CE_T4_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xffff00ff))
+#define SET_RG_CE_T3_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0xff00ffff))
+#define SET_RG_CE_T2_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) & 0x00ffffff))
+#define SET_RG_CE_MU_T1(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xfffffff8))
+#define SET_RG_CE_DLY_SEL(_VAL_) (REG32(ADR_RX_11B_CE_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_0)) & 0xffc0ffff))
+#define SET_RG_CE_MU_T8(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffffff8))
+#define SET_RG_CE_MU_T7(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffffff8f))
+#define SET_RG_CE_MU_T6(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfffff8ff))
+#define SET_RG_CE_MU_T5(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xffff8fff))
+#define SET_RG_CE_MU_T4(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xfff8ffff))
+#define SET_RG_CE_MU_T3(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xff8fffff))
+#define SET_RG_CE_MU_T2(_VAL_) (REG32(ADR_RX_11B_CE_MU_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CE_MU_1)) & 0xf8ffffff))
+#define SET_RG_EQ_MU_FB_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfffffff0))
+#define SET_RG_EQ_MU_FF_T2(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xffffff0f))
+#define SET_RG_EQ_MU_FB_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xfff0ffff))
+#define SET_RG_EQ_MU_FF_T1(_VAL_) (REG32(ADR_RX_11B_EQ_MU_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_0)) & 0xff0fffff))
+#define SET_RG_EQ_MU_FB_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfffffff0))
+#define SET_RG_EQ_MU_FF_T4(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xffffff0f))
+#define SET_RG_EQ_MU_FB_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xfff0ffff))
+#define SET_RG_EQ_MU_FF_T3(_VAL_) (REG32(ADR_RX_11B_EQ_MU_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_MU_1)) & 0xff0fffff))
+#define SET_RG_EQ_KI_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfffff8ff))
+#define SET_RG_EQ_KP_T2(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xffff8fff))
+#define SET_RG_EQ_KI_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xfff8ffff))
+#define SET_RG_EQ_KP_T1(_VAL_) (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_EQ_CR_KP_KI)) & 0xff8fffff))
+#define SET_RG_TR_LPF_RATE(_VAL_) (REG32(ADR_RX_11B_LPF_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_LPF_RATE)) & 0xffc00000))
+#define SET_RG_CE_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff80))
+#define SET_RG_CE_CH_MAIN_SET(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffffff7f))
+#define SET_RG_TC_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xffff80ff))
+#define SET_RG_CR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0xff80ffff))
+#define SET_RG_TR_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) & 0x80ffffff))
+#define SET_RG_EQ_MAIN_TAP_MAN(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xfffffffe))
+#define SET_RG_EQ_MAIN_TAP_COEF(_VAL_) (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) & 0xf800ffff))
+#define SET_RG_PWRON_DLY_TH_11B(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xffffff00))
+#define SET_RG_SFD_BIT_CNT_LMT(_VAL_) (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SEARCH_CNT_TH)) & 0xff00ffff))
+#define SET_RG_CCA_PWR_TH_RX(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffff8000))
+#define SET_RG_CCA_PWR_CNT_TH(_VAL_) (REG32(ADR_RX_11B_CCA_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_CCA_CONTROL)) & 0xffe0ffff))
+#define SET_B_FREQ_OS(_VAL_) (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_FREQUENCY_OFFSET)) & 0xfffff800))
+#define SET_B_SNR(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xffffff80))
+#define SET_B_RCPI(_VAL_) (REG32(ADR_RX_11B_SNR_RSSI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SNR_RSSI)) & 0xff80ffff))
+#define SET_CRC_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0xffff0000))
+#define SET_SFD_CNT(_VAL_) (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_CRC_CNT)) & 0x0000ffff))
+#define SET_B_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xffff0000))
+#define SET_PACKET_ERR(_VAL_) (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) & 0xfffeffff))
+#define SET_B_PACKET_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
+#define SET_B_CCA_CNT(_VAL_) (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
+#define SET_B_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0xffff0000))
+#define SET_SFD_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FILED_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FILED_0)) & 0x0000ffff))
+#define SET_SIGNAL_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffffff00))
+#define SET_B_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xffff00ff))
+#define SET_CRC_CORRECT(_VAL_) (REG32(ADR_RX_11B_SFD_FIELD_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11B_SFD_FIELD_1)) & 0xfffeffff))
+#define SET_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xfffffff0))
+#define SET_RG_PACKET_STAT_EN_11B(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffefffff))
+#define SET_RG_BIT_REVERSE(_VAL_) (REG32(ADR_RX_11B_PKT_STAT_EN)) = (((_VAL_) << 21) | ((REG32(ADR_RX_11B_PKT_STAT_EN)) & 0xffdfffff))
+#define SET_RX_PHY_11B_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffffffe))
+#define SET_RG_CE_BYPASS_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xffffff0f))
+#define SET_RG_EQ_BYPASS_FBW_TAP(_VAL_) (REG32(ADR_RX_11B_SOFT_RST)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11B_SOFT_RST)) & 0xfffff0ff))
+#define SET_RG_BB_11GN_RISE_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffffff00))
+#define SET_RG_BB_11GN_FALL_TIME(_VAL_) (REG32(ADR_TX_11GN_RAMP)) = (((_VAL_) << 8) | ((REG32(ADR_TX_11GN_RAMP)) & 0xffff00ff))
+#define SET_RG_HTCARR52_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP)) & 0xfffffc00))
+#define SET_RG_HTCARR56_FFT_SCALE(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 12) | ((REG32(ADR_TX_11GN_PLCP)) & 0xffc00fff))
+#define SET_RG_PACKET_STAT_EN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 23) | ((REG32(ADR_TX_11GN_PLCP)) & 0xff7fffff))
+#define SET_RG_SMB_DEF(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 24) | ((REG32(ADR_TX_11GN_PLCP)) & 0x80ffffff))
+#define SET_RG_CONTINUOUS_DATA_11GN(_VAL_) (REG32(ADR_TX_11GN_PLCP)) = (((_VAL_) << 31) | ((REG32(ADR_TX_11GN_PLCP)) & 0x7fffffff))
+#define SET_RO_TX_CNT_R(_VAL_) (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PKT_GEN_CNT)) & 0x00000000))
+#define SET_RO_PACKET_ERR_CNT(_VAL_) (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) & 0xffff0000))
+#define SET_RG_POS_DES_11GN_L_EXT(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xfffffff0))
+#define SET_RG_PRE_DES_11GN_DLY(_VAL_) (REG32(ADR_RX_11GN_DES_DLY)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_DES_DLY)) & 0xffffff0f))
+#define SET_RG_TR_LPF_KI_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfffffff0))
+#define SET_RG_TR_LPF_KP_G_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffffff0f))
+#define SET_RG_TR_CNT_T1(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_0)) & 0xffff00ff))
+#define SET_RG_TR_LPF_KI_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_TR_0)) & 0xfff0ffff))
+#define SET_RG_TR_LPF_KP_G_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TR_0)) & 0xff0fffff))
+#define SET_RG_TR_CNT_T0(_VAL_) (REG32(ADR_RX_11GN_TR_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_TR_0)) & 0x00ffffff))
+#define SET_RG_TR_LPF_KI_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_1)) & 0xfffffff0))
+#define SET_RG_TR_LPF_KP_G_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffffff0f))
+#define SET_RG_TR_CNT_T2(_VAL_) (REG32(ADR_RX_11GN_TR_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_1)) & 0xffff00ff))
+#define SET_RG_TR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TR_2)) & 0xfffffff0))
+#define SET_RG_TR_LPF_KP_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_TR_2)) & 0xffffff0f))
+#define SET_RG_TR_LPF_RATE_G(_VAL_) (REG32(ADR_RX_11GN_TR_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_TR_2)) & 0xc00000ff))
+#define SET_RG_CR_LPF_KI_G(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xfffffff8))
+#define SET_RG_SYM_BOUND_CNT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xffff80ff))
+#define SET_RG_XSCOR32_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_0)) & 0xff80ffff))
+#define SET_RG_ATCOR64_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_0)) & 0x80ffffff))
+#define SET_RG_ATCOR16_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xffff80ff))
+#define SET_RG_ATCOR16_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_1)) & 0xff80ffff))
+#define SET_RG_ATCOR16_RATIO_SB(_VAL_) (REG32(ADR_RX_11GN_CCA_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_1)) & 0x80ffffff))
+#define SET_RG_XSCOR64_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_2)) & 0xff80ffff))
+#define SET_RG_XSCOR64_CNT_LMT1(_VAL_) (REG32(ADR_RX_11GN_CCA_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_2)) & 0x80ffffff))
+#define SET_RG_RX_FFT_SCALE(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffffc00))
+#define SET_RG_VITERBI_AB_SWAP(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xfffeffff))
+#define SET_RG_ATCOR16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_FFT_SCALE)) & 0xf0ffffff))
+#define SET_RG_NORMSQUARE_LOW_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffffff00))
+#define SET_RG_NORMSQUARE_LOW_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xffff00ff))
+#define SET_RG_NORMSQUARE_LOW_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0xff00ffff))
+#define SET_RG_NORMSQUARE_LOW_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_0)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_LOW_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_1)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_SNR_3(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffffff00))
+#define SET_RG_NORMSQUARE_SNR_2(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xffff00ff))
+#define SET_RG_NORMSQUARE_SNR_1(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0xff00ffff))
+#define SET_RG_NORMSQUARE_SNR_0(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_2)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_SNR_7(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffffff00))
+#define SET_RG_NORMSQUARE_SNR_6(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xffff00ff))
+#define SET_RG_NORMSQUARE_SNR_5(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0xff00ffff))
+#define SET_RG_NORMSQUARE_SNR_4(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_3)) & 0x00ffffff))
+#define SET_RG_NORMSQUARE_SNR_8(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_4)) & 0x00ffffff))
+#define SET_RG_SNR_TH_64QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffffff80))
+#define SET_RG_SNR_TH_16QAM(_VAL_) (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SOFT_DEMAP_5)) & 0xffff80ff))
+#define SET_RG_ATCOR16_CNT_PLUS_LMT2(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffffff80))
+#define SET_RG_ATCOR16_CNT_PLUS_LMT1(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xffff80ff))
+#define SET_RG_SYM_BOUND_METHOD(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SYM_BOUND_0)) & 0xfffcffff))
+#define SET_RG_PWRON_DLY_TH_11GN(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffffff00))
+#define SET_RG_SB_START_CNT(_VAL_) (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SYM_BOUND_1)) & 0xffff80ff))
+#define SET_RG_POW16_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xffffff0f))
+#define SET_RG_POW16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0xfffff8ff))
+#define SET_RG_POW16_TH_L(_VAL_) (REG32(ADR_RX_11GN_CCA_PWR)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_PWR)) & 0x80ffffff))
+#define SET_RG_XSCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfffffff8))
+#define SET_RG_XSCOR16_RATIO(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xffff80ff))
+#define SET_RG_ATCOR16_SHORT_CNT_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0xfff8ffff))
+#define SET_RG_ATCOR16_RATIO_CCD(_VAL_) (REG32(ADR_RX_11GN_CCA_CNT)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CCA_CNT)) & 0x80ffffff))
+#define SET_RG_ATCOR64_ACC_LMT(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xffffff80))
+#define SET_RG_ATCOR16_SHORT_CNT_LMT2(_VAL_) (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) & 0xfff8ffff))
+#define SET_RG_VITERBI_TB_BITS(_VAL_) (REG32(ADR_RX_11GN_VTB_TB)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_VTB_TB)) & 0x00ffffff))
+#define SET_RG_CR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xffffff00))
+#define SET_RG_TR_CNT_UPDATE(_VAL_) (REG32(ADR_RX_11GN_ERR_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_ERR_UPDATE)) & 0xff00ffff))
+#define SET_RG_BYPASS_CPE_MA(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffffffef))
+#define SET_RG_PILOT_BNDRY_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfffff8ff))
+#define SET_RG_EQ_SHORT_GI_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xffff8fff))
+#define SET_RG_FFT_WDW_SHORT_SHIFT(_VAL_) (REG32(ADR_RX_11GN_SHORT_GI)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SHORT_GI)) & 0xfff8ffff))
+#define SET_RG_CHSMTH_COEF(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffcffff))
+#define SET_RG_CHSMTH_EN(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 18) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xfffbffff))
+#define SET_RG_CHEST_DD_FACTOR(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0xf8ffffff))
+#define SET_RG_CH_UPDATE(_VAL_) (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_CHANNEL_UPDATE)) & 0x7fffffff))
+#define SET_RG_FMT_DET_MM_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffffff00))
+#define SET_RG_FMT_DET_GF_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xffff00ff))
+#define SET_RG_DO_NOT_CHECK_L_RATE(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_11GN_PKT_FORMAT_0)) & 0xfdffffff))
+#define SET_RG_FMT_DET_LENGTH_TH(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0xffff0000))
+#define SET_RG_L_LENGTH_MAX(_VAL_) (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_FORMAT_1)) & 0x0000ffff))
+#define SET_RG_TX_TIME_EXT(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xffffff00))
+#define SET_RG_MAC_DES_SPACE(_VAL_) (REG32(ADR_RX_11GN_TX_TIME)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_TX_TIME)) & 0xff0fffff))
+#define SET_RG_TR_LPF_STBC_GF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffffff0))
+#define SET_RG_TR_LPF_STBC_GF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffffff0f))
+#define SET_RG_TR_LPF_STBC_MF_KI_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xfffff0ff))
+#define SET_RG_TR_LPF_STBC_MF_KP_G(_VAL_) (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_STBC_TR_KP_KI)) & 0xffff0fff))
+#define SET_RG_MODE_REG_IN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfffe0000))
+#define SET_RG_PARALLEL_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xffefffff))
+#define SET_RG_MBRUN_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xfeffffff))
+#define SET_RG_SHIFT_DR_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xefffffff))
+#define SET_RG_MODE_REG_SI_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xdfffffff))
+#define SET_RG_SIMULATION_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_0)) & 0xbfffffff))
+#define SET_RG_DBIST_MODE_80(_VAL_) (REG32(ADR_RX_11GN_BIST_0)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_0)) & 0x7fffffff))
+#define SET_RG_MODE_REG_IN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffff0000))
+#define SET_RG_PARALLEL_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xffefffff))
+#define SET_RG_MBRUN_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xfeffffff))
+#define SET_RG_SHIFT_DR_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 28) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xefffffff))
+#define SET_RG_MODE_REG_SI_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 29) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xdfffffff))
+#define SET_RG_SIMULATION_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 30) | ((REG32(ADR_RX_11GN_BIST_1)) & 0xbfffffff))
+#define SET_RG_DBIST_MODE_64(_VAL_) (REG32(ADR_RX_11GN_BIST_1)) = (((_VAL_) << 31) | ((REG32(ADR_RX_11GN_BIST_1)) & 0x7fffffff))
+#define SET_RO_MODE_REG_OUT_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfffe0000))
+#define SET_RO_MODE_REG_SO_80(_VAL_) (REG32(ADR_RX_11GN_BIST_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_2)) & 0xfeffffff))
+#define SET_RO_MONITOR_BUS_80(_VAL_) (REG32(ADR_RX_11GN_BIST_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_3)) & 0xffc00000))
+#define SET_RO_MODE_REG_OUT_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xffff0000))
+#define SET_RO_MODE_REG_SO_64(_VAL_) (REG32(ADR_RX_11GN_BIST_4)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_BIST_4)) & 0xfeffffff))
+#define SET_RO_MONITOR_BUS_64(_VAL_) (REG32(ADR_RX_11GN_BIST_5)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_BIST_5)) & 0xfff80000))
+#define SET_RO_SPECTRUM_DATA(_VAL_) (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) & 0x00000000))
+#define SET_GN_SNR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffffff80))
+#define SET_GN_NOISE_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_READ_0)) & 0xffff80ff))
+#define SET_GN_RCPI(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_READ_0)) & 0xff80ffff))
+#define SET_GN_SIGNAL_PWR(_VAL_) (REG32(ADR_RX_11GN_READ_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_11GN_READ_0)) & 0x80ffffff))
+#define SET_RO_FREQ_OS_LTS(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xffff8000))
+#define SET_CSTATE(_VAL_) (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_FREQ_OFFSET)) & 0xfff0ffff))
+#define SET_SIGNAL_FIELD0(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) & 0xff000000))
+#define SET_SIGNAL_FIELD1(_VAL_) (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) & 0xff000000))
+#define SET_GN_PACKET_ERR_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_ERR_CNT)) & 0xffff0000))
+#define SET_GN_PACKET_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0xffff0000))
+#define SET_GN_CCA_CNT(_VAL_) (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) & 0x0000ffff))
+#define SET_GN_LENGTH_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0xffff0000))
+#define SET_GN_SERVICE_FIELD(_VAL_) (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) & 0x0000ffff))
+#define SET_RO_HT_MCS_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffff80))
+#define SET_RO_L_RATE_40M(_VAL_) (REG32(ADR_RX_11GN_RATE)) = (((_VAL_) << 8) | ((REG32(ADR_RX_11GN_RATE)) & 0xffffc0ff))
+#define SET_RG_DAGC_CNT_TH(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xfffffffc))
+#define SET_RG_PACKET_STAT_EN_11GN(_VAL_) (REG32(ADR_RX_11GN_STAT_EN)) = (((_VAL_) << 20) | ((REG32(ADR_RX_11GN_STAT_EN)) & 0xffefffff))
+#define SET_RX_PHY_11GN_SOFT_RST_N(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 0) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffe))
+#define SET_RG_RIFS_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 1) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffd))
+#define SET_RG_STBC_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 2) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffffb))
+#define SET_RG_COR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 3) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffff7))
+#define SET_RG_INI_PHASE(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 4) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffcf))
+#define SET_RG_HT_LTF_SEL_EQ(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 6) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffffbf))
+#define SET_RG_HT_LTF_SEL_PILOT(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 7) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffffff7f))
+#define SET_RG_CCA_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 9) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffdff))
+#define SET_RG_CCA_XSCOR_PWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 10) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffffbff))
+#define SET_RG_CCA_XSCOR_AVGPWR_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 11) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffff7ff))
+#define SET_RG_DEBUG_SEL(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 12) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xffff0fff))
+#define SET_RG_POST_CLK_EN(_VAL_) (REG32(ADR_RX_11GN_SOFT_RST)) = (((_VAL_) << 16) | ((REG32(ADR_RX_11GN_SOFT_RST)) & 0xfffeffff))
+#define SET_IQCAL_RF_TX_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffe))
+#define SET_IQCAL_RF_TX_PA_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 1) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffd))
+#define SET_IQCAL_RF_TX_DAC_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 2) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffffb))
+#define SET_IQCAL_RF_RX_AGC(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 3) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffffff7))
+#define SET_IQCAL_RF_PGAG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_0)) & 0xfffff0ff))
+#define SET_IQCAL_RF_RFG(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 12) | ((REG32(ADR_RF_CONTROL_0)) & 0xffffcfff))
+#define SET_RG_TONEGEN_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_CONTROL_0)) & 0xff80ffff))
+#define SET_RG_TONEGEN_EN(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 23) | ((REG32(ADR_RF_CONTROL_0)) & 0xff7fffff))
+#define SET_RG_TONEGEN_INIT_PH(_VAL_) (REG32(ADR_RF_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_CONTROL_0)) & 0x80ffffff))
+#define SET_RG_TONEGEN2_FREQ(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff80))
+#define SET_RG_TONEGEN2_EN(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 7) | ((REG32(ADR_RF_CONTROL_1)) & 0xffffff7f))
+#define SET_RG_TONEGEN2_SCALE(_VAL_) (REG32(ADR_RF_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_RF_CONTROL_1)) & 0xffff00ff))
+#define SET_RG_TXIQ_CLP_THD_I(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfffffc00))
+#define SET_RG_TXIQ_CLP_THD_Q(_VAL_) (REG32(ADR_TX_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_0)) & 0xfc00ffff))
+#define SET_RG_TX_I_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffffff00))
+#define SET_RG_TX_Q_SCALE(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 8) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffff00ff))
+#define SET_RG_TX_IQ_SWP(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffeffff))
+#define SET_RG_TX_SGN_OUT(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 17) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfffdffff))
+#define SET_RG_TXIQ_EMU_IDX(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 18) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xffc3ffff))
+#define SET_RG_TX_IQ_SRC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_TX_IQ_CONTROL_1)) & 0xfcffffff))
+#define SET_RG_TX_I_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfffffc00))
+#define SET_RG_TX_Q_DC(_VAL_) (REG32(ADR_TX_IQ_CONTROL_2)) = (((_VAL_) << 16) | ((REG32(ADR_TX_IQ_CONTROL_2)) & 0xfc00ffff))
+#define SET_RG_TX_IQ_THETA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffffe0))
+#define SET_RG_TX_IQ_ALPHA(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffe0ff))
+#define SET_RG_TXIQ_NOSHRINK(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xffffdfff))
+#define SET_RG_TX_I_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 16) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0xff00ffff))
+#define SET_RG_TX_Q_OFFSET(_VAL_) (REG32(ADR_TX_COMPENSATION_CONTROL)) = (((_VAL_) << 24) | ((REG32(ADR_TX_COMPENSATION_CONTROL)) & 0x00ffffff))
+#define SET_RG_RX_IQ_THETA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffffe0))
+#define SET_RG_RX_IQ_ALPHA(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 8) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffe0ff))
+#define SET_RG_RXIQ_NOSHRINK(_VAL_) (REG32(ADR_RX_COMPENSATION_CONTROL)) = (((_VAL_) << 13) | ((REG32(ADR_RX_COMPENSATION_CONTROL)) & 0xffffdfff))
+#define SET_RG_MA_DPTH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffff0))
+#define SET_RG_INTG_PH(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 4) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffffc0f))
+#define SET_RG_INTG_PRD(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 10) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffffe3ff))
+#define SET_RG_INTG_MU(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 13) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xffff9fff))
+#define SET_RG_IQCAL_SPRM_SELQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffeffff))
+#define SET_RG_IQCAL_SPRM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 17) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfffdffff))
+#define SET_RG_IQCAL_SPRM_FREQ(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 18) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xff03ffff))
+#define SET_RG_IQCAL_IQCOL_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfeffffff))
+#define SET_RG_IQCAL_ALPHA_ESTM_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfdffffff))
+#define SET_RG_IQCAL_DC_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xfbffffff))
+#define SET_RG_PHEST_STBY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xf7ffffff))
+#define SET_RG_PHEST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xefffffff))
+#define SET_RG_GP_DIV_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 29) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xdfffffff))
+#define SET_RG_DPD_GAIN_EST_EN(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (((_VAL_) << 30) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) & 0xbfffffff))
+#define SET_RG_IQCAL_MULT_OP0(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfffffc00))
+#define SET_RG_IQCAL_MULT_OP1(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) & 0xfc00ffff))
+#define SET_RO_IQCAL_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfff00000))
+#define SET_RO_IQCAL_SPRM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 20) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffefffff))
+#define SET_RO_IQCAL_IQCOL_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 21) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffdfffff))
+#define SET_RO_IQCAL_ALPHA_ESTM_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 22) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xffbfffff))
+#define SET_RO_IQCAL_DC_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 23) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xff7fffff))
+#define SET_RO_IQCAL_MULT_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 24) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfeffffff))
+#define SET_RO_FFT_ENRG_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 25) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfdffffff))
+#define SET_RO_PHEST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 26) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xfbffffff))
+#define SET_RO_GP_DIV_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 27) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xf7ffffff))
+#define SET_RO_GAIN_EST_RDY(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (((_VAL_) << 28) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) & 0xefffffff))
+#define SET_RO_AMP_O(_VAL_) (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) & 0xfffffe00))
+#define SET_RG_RX_I_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffffff00))
+#define SET_RG_RX_Q_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 8) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xffff00ff))
+#define SET_RG_RX_I_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 16) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0xff00ffff))
+#define SET_RG_RX_Q_OFFSET(_VAL_) (REG32(ADR_RF_IQ_CONTROL_0)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_0)) & 0x00ffffff))
+#define SET_RG_RX_IQ_SWP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffe))
+#define SET_RG_RX_SGN_IN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffffd))
+#define SET_RG_RX_IQ_SRC(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 2) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffffff3))
+#define SET_RG_ACI_GAIN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xfffff00f))
+#define SET_RG_FFT_EN(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 12) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffefff))
+#define SET_RG_FFT_MOD(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 13) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xffffdfff))
+#define SET_RG_FFT_SCALE(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 14) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xff003fff))
+#define SET_RG_FFT_ENRG_FREQ(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 24) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xc0ffffff))
+#define SET_RG_FPGA_80M_PH_UP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 30) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0xbfffffff))
+#define SET_RG_FPGA_80M_PH_STP(_VAL_) (REG32(ADR_RF_IQ_CONTROL_1)) = (((_VAL_) << 31) | ((REG32(ADR_RF_IQ_CONTROL_1)) & 0x7fffffff))
+#define SET_RG_ADC2LA_SEL(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffe))
+#define SET_RG_ADC2LA_CLKPH(_VAL_) (REG32(ADR_RF_IQ_CONTROL_2)) = (((_VAL_) << 1) | ((REG32(ADR_RF_IQ_CONTROL_2)) & 0xfffffffd))
+#define SET_RG_RXIQ_EMU_IDX(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 0) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xfffffff0))
+#define SET_RG_IQCAL_BP_ACI(_VAL_) (REG32(ADR_RF_IQ_CONTROL_3)) = (((_VAL_) << 4) | ((REG32(ADR_RF_IQ_CONTROL_3)) & 0xffffffef))
+#define SET_RG_DPD_AM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffe))
+#define SET_RG_DPD_PM_EN(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 1) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffd))
+#define SET_RG_DPD_PM_AMSEL(_VAL_) (REG32(ADR_DPD_CONTROL)) = (((_VAL_) << 2) | ((REG32(ADR_DPD_CONTROL)) & 0xfffffffb))
+#define SET_RG_DPD_020_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfffffc00))
+#define SET_RG_DPD_040_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_0)) & 0xfc00ffff))
+#define SET_RG_DPD_060_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfffffc00))
+#define SET_RG_DPD_080_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_1)) & 0xfc00ffff))
+#define SET_RG_DPD_0A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfffffc00))
+#define SET_RG_DPD_0C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_2)) & 0xfc00ffff))
+#define SET_RG_DPD_0D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfffffc00))
+#define SET_RG_DPD_0E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_3)) & 0xfc00ffff))
+#define SET_RG_DPD_0F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfffffc00))
+#define SET_RG_DPD_100_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_4)) & 0xfc00ffff))
+#define SET_RG_DPD_110_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfffffc00))
+#define SET_RG_DPD_120_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_5)) & 0xfc00ffff))
+#define SET_RG_DPD_130_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfffffc00))
+#define SET_RG_DPD_140_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_6)) & 0xfc00ffff))
+#define SET_RG_DPD_150_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfffffc00))
+#define SET_RG_DPD_160_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_7)) & 0xfc00ffff))
+#define SET_RG_DPD_170_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfffffc00))
+#define SET_RG_DPD_180_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_8)) & 0xfc00ffff))
+#define SET_RG_DPD_190_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfffffc00))
+#define SET_RG_DPD_1A0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_9)) & 0xfc00ffff))
+#define SET_RG_DPD_1B0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfffffc00))
+#define SET_RG_DPD_1C0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_A)) & 0xfc00ffff))
+#define SET_RG_DPD_1D0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfffffc00))
+#define SET_RG_DPD_1E0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_B)) & 0xfc00ffff))
+#define SET_RG_DPD_1F0_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfffffc00))
+#define SET_RG_DPD_200_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_TABLE_C)) & 0xfc00ffff))
+#define SET_RG_DPD_020_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xffffe000))
+#define SET_RG_DPD_040_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_0)) & 0xe000ffff))
+#define SET_RG_DPD_060_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xffffe000))
+#define SET_RG_DPD_080_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_1)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_1)) & 0xe000ffff))
+#define SET_RG_DPD_0A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xffffe000))
+#define SET_RG_DPD_0C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_2)) & 0xe000ffff))
+#define SET_RG_DPD_0D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xffffe000))
+#define SET_RG_DPD_0E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_3)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_3)) & 0xe000ffff))
+#define SET_RG_DPD_0F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xffffe000))
+#define SET_RG_DPD_100_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_4)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_4)) & 0xe000ffff))
+#define SET_RG_DPD_110_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xffffe000))
+#define SET_RG_DPD_120_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_5)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_5)) & 0xe000ffff))
+#define SET_RG_DPD_130_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xffffe000))
+#define SET_RG_DPD_140_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_6)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_6)) & 0xe000ffff))
+#define SET_RG_DPD_150_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xffffe000))
+#define SET_RG_DPD_160_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_7)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_7)) & 0xe000ffff))
+#define SET_RG_DPD_170_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xffffe000))
+#define SET_RG_DPD_180_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_8)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_8)) & 0xe000ffff))
+#define SET_RG_DPD_190_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xffffe000))
+#define SET_RG_DPD_1A0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_9)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_9)) & 0xe000ffff))
+#define SET_RG_DPD_1B0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xffffe000))
+#define SET_RG_DPD_1C0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_A)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_A)) & 0xe000ffff))
+#define SET_RG_DPD_1D0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xffffe000))
+#define SET_RG_DPD_1E0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_B)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_B)) & 0xe000ffff))
+#define SET_RG_DPD_1F0_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xffffe000))
+#define SET_RG_DPD_200_PH(_VAL_) (REG32(ADR_DPD_PH_TABLE_C)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_PH_TABLE_C)) & 0xe000ffff))
+#define SET_RG_DPD_GAIN_EST_Y0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfffffe00))
+#define SET_RG_DPD_GAIN_EST_Y1(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_0)) & 0xfe00ffff))
+#define SET_RG_DPD_LOOP_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_1)) & 0xfffffc00))
+#define SET_RG_DPD_GAIN_EST_X0(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 0) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfffffe00))
+#define SET_RO_DPD_GAIN(_VAL_) (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (((_VAL_) << 16) | ((REG32(ADR_DPD_GAIN_ESTIMATION_2)) & 0xfc00ffff))
+#define SET_TX_SCALE_11B(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 0) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffffff00))
+#define SET_TX_SCALE_11B_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 8) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xffff00ff))
+#define SET_TX_SCALE_11G(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 16) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0xff00ffff))
+#define SET_TX_SCALE_11G_P0D5(_VAL_) (REG32(ADR_TX_GAIN_FACTOR)) = (((_VAL_) << 24) | ((REG32(ADR_TX_GAIN_FACTOR)) & 0x00ffffff))
+#define SET_RG_EN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffe))
+#define SET_RG_TX_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffd))
+#define SET_RG_TX_PA_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffffb))
+#define SET_RG_TX_DAC_EN(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffffff7))
+#define SET_RG_RX_AGC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffef))
+#define SET_RG_RX_GAIN_MANUAL(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffffdf))
+#define SET_RG_RFG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffff3f))
+#define SET_RG_PGAG(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffff0ff))
+#define SET_RG_MODE(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffcfff))
+#define SET_RG_EN_TX_TRSW(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffffbfff))
+#define SET_RG_EN_SX(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffff7fff))
+#define SET_RG_EN_RX_LNA(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffeffff))
+#define SET_RG_EN_RX_MIXER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffdffff))
+#define SET_RG_EN_RX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfffbffff))
+#define SET_RG_EN_RX_LOBUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfff7ffff))
+#define SET_RG_EN_RX_TZ(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffefffff))
+#define SET_RG_EN_RX_FILTER(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffdfffff))
+#define SET_RG_EN_RX_HPF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xffbfffff))
+#define SET_RG_EN_RX_RSSI(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xff7fffff))
+#define SET_RG_EN_ADC(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfeffffff))
+#define SET_RG_EN_TX_MOD(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 25) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfdffffff))
+#define SET_RG_EN_TX_DIV2(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xfbffffff))
+#define SET_RG_EN_TX_DIV2_BUF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xf7ffffff))
+#define SET_RG_EN_TX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xefffffff))
+#define SET_RG_EN_RX_LOBF(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 29) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xdfffffff))
+#define SET_RG_SEL_DPLL_CLK(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0xbfffffff))
+#define SET_RG_EN_CLK_960MBY13_UART(_VAL_) (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_HARD_WIRE_PIN_REGISTER)) & 0x7fffffff))
+#define SET_RG_EN_TX_DPD(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffe))
+#define SET_RG_EN_TX_TSSI(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffd))
+#define SET_RG_EN_RX_IQCAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffffb))
+#define SET_RG_EN_TX_DAC_CAL(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffff7))
+#define SET_RG_EN_TX_SELF_MIXER(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffef))
+#define SET_RG_EN_TX_DAC_OUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffdf))
+#define SET_RG_EN_LDO_RX_FE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffffbf))
+#define SET_RG_EN_LDO_ABB(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffff7f))
+#define SET_RG_EN_LDO_AFE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffeff))
+#define SET_RG_EN_SX_CHPLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffdff))
+#define SET_RG_EN_SX_LOBFLDO(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffffbff))
+#define SET_RG_EN_IREF_RX(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffff7ff))
+#define SET_RG_EN_TX_DAC_VOUT(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffdfff))
+#define SET_RG_EN_SX_LCK_BIN(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xffffbfff))
+#define SET_RG_RTC_CAL_MODE(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffeffff))
+#define SET_RG_EN_IQPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 17) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffdffff))
+#define SET_RG_EN_TESTPAD_IOSW(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfffbffff))
+#define SET_RG_EN_TRXBF_BYPASS(_VAL_) (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (((_VAL_) << 19) | ((REG32(ADR_MANUAL_ENABLE_REGISTER)) & 0xfff7ffff))
+#define SET_RG_LDO_LEVEL_RX_FE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffff8))
+#define SET_RG_LDO_LEVEL_ABB(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_LDO_REGISTER)) & 0xffffffc7))
+#define SET_RG_LDO_LEVEL_AFE(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_LDO_REGISTER)) & 0xfffffe3f))
+#define SET_RG_SX_LDO_CHP_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_LDO_REGISTER)) & 0xfffff1ff))
+#define SET_RG_SX_LDO_LOBF_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_LDO_REGISTER)) & 0xffff8fff))
+#define SET_RG_SX_LDO_XOSC_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_LDO_REGISTER)) & 0xfffc7fff))
+#define SET_RG_DP_LDO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_LDO_REGISTER)) & 0xffe3ffff))
+#define SET_RG_SX_LDO_VCO_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_LDO_REGISTER)) & 0xff1fffff))
+#define SET_RG_TX_LDO_TX_LEVEL(_VAL_) (REG32(ADR_LDO_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_LDO_REGISTER)) & 0xf8ffffff))
+#define SET_RG_EN_RX_PADSW(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffe))
+#define SET_RG_EN_RX_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 1) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffd))
+#define SET_RG_RX_ABBCFIX(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffffb))
+#define SET_RG_RX_ABBCTUNE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffe07))
+#define SET_RG_RX_ABBOUT_TRI_STATE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 9) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffdff))
+#define SET_RG_RX_ABB_N_MODE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffffbff))
+#define SET_RG_RX_EN_LOOPA(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffff7ff))
+#define SET_RG_RX_FILTERI1ST(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffffcfff))
+#define SET_RG_RX_FILTERI2ND(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffff3fff))
+#define SET_RG_RX_FILTERI3RD(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfffcffff))
+#define SET_RG_RX_FILTERI_COURSE(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfff3ffff))
+#define SET_RG_RX_FILTERVCM(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffcfffff))
+#define SET_RG_RX_HPF3M(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_ABB_REGISTER_1)) & 0xffbfffff))
+#define SET_RG_RX_HPF300K(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_1)) & 0xff7fffff))
+#define SET_RG_RX_HPFI(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_ABB_REGISTER_1)) & 0xfcffffff))
+#define SET_RG_RX_HPF_FINALCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 26) | ((REG32(ADR_ABB_REGISTER_1)) & 0xf3ffffff))
+#define SET_RG_RX_HPF_SETTLE1_C(_VAL_) (REG32(ADR_ABB_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_ABB_REGISTER_1)) & 0xcfffffff))
+#define SET_RG_RX_HPF_SETTLE1_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffffc))
+#define SET_RG_RX_HPF_SETTLE2_C(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffff3))
+#define SET_RG_RX_HPF_SETTLE2_R(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 4) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffffcf))
+#define SET_RG_RX_HPF_VCMCON2(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffff3f))
+#define SET_RG_RX_HPF_VCMCON(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 8) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffffcff))
+#define SET_RG_RX_OUTVCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffff3ff))
+#define SET_RG_RX_TZI(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 12) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffcfff))
+#define SET_RG_RX_TZ_OUT_TRISTATE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffffbfff))
+#define SET_RG_RX_TZ_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfffe7fff))
+#define SET_RG_EN_RX_RSSI_TESTNODE(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 17) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfff1ffff))
+#define SET_RG_RX_ADCRSSI_CLKSEL(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_ABB_REGISTER_2)) & 0xffefffff))
+#define SET_RG_RX_ADCRSSI_VCM(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 21) | ((REG32(ADR_ABB_REGISTER_2)) & 0xff9fffff))
+#define SET_RG_RX_REC_LPFCORNER(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 23) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfe7fffff))
+#define SET_RG_RSSI_CLOCK_GATING(_VAL_) (REG32(ADR_ABB_REGISTER_2)) = (((_VAL_) << 25) | ((REG32(ADR_ABB_REGISTER_2)) & 0xfdffffff))
+#define SET_RG_TXPGA_CAPSW(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffffffc))
+#define SET_RG_TXPGA_MAIN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffff03))
+#define SET_RG_TXPGA_STEER(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffffc0ff))
+#define SET_RG_TXMOD_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffff3fff))
+#define SET_RG_TXLPF_GMCELL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfffcffff))
+#define SET_RG_PACELL_EN(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_TX_FE_REGISTER)) & 0xffe3ffff))
+#define SET_RG_PABIAS_CTRL(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_FE_REGISTER)) & 0xfe1fffff))
+#define SET_RG_TX_DIV_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_TX_FE_REGISTER)) & 0xf3ffffff))
+#define SET_RG_TX_LOBUF_VSET(_VAL_) (REG32(ADR_TX_FE_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_TX_FE_REGISTER)) & 0xcfffffff))
+#define SET_RG_RX_SQDC(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffffff8))
+#define SET_RG_RX_DIV2_CORE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 3) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffffe7))
+#define SET_RG_RX_LOBUF(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 5) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffffff9f))
+#define SET_RG_TX_DPDGM_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 7) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffff87f))
+#define SET_RG_TX_DPD_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 11) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffff87ff))
+#define SET_RG_TX_TSSI_BIAS(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 15) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xfffc7fff))
+#define SET_RG_TX_TSSI_DIV(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 18) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffe3ffff))
+#define SET_RG_TX_TSSI_TESTMODE(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 21) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xffdfffff))
+#define SET_RG_TX_TSSI_TEST(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 22) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xff3fffff))
+#define SET_RG_PACASCODE_CTRL(_VAL_) (REG32(ADR_RX_FE_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_RX_FE_REGISTER_1)) & 0xf8ffffff))
+#define SET_RG_RX_HG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffffc))
+#define SET_RG_RX_HG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffffc3))
+#define SET_RG_RX_HG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfffffc3f))
+#define SET_RG_RX_HG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffffc3ff))
+#define SET_RG_RX_HG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xffff3fff))
+#define SET_RG_RX_HG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) & 0xfff8ffff))
+#define SET_RG_RX_MG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffffc))
+#define SET_RG_RX_MG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffffc3))
+#define SET_RG_RX_MG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfffffc3f))
+#define SET_RG_RX_MG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffffc3ff))
+#define SET_RG_RX_MG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xffff3fff))
+#define SET_RG_RX_MG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) & 0xfff8ffff))
+#define SET_RG_RX_LG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffffc))
+#define SET_RG_RX_LG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffffc3))
+#define SET_RG_RX_LG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfffffc3f))
+#define SET_RG_RX_LG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffffc3ff))
+#define SET_RG_RX_LG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xffff3fff))
+#define SET_RG_RX_LG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) & 0xfff8ffff))
+#define SET_RG_RX_ULG_LNA_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 0) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffffc))
+#define SET_RG_RX_ULG_LNAHGN_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 2) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffffc3))
+#define SET_RG_RX_ULG_LNAHGP_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 6) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfffffc3f))
+#define SET_RG_RX_ULG_LNALG_BIAS(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 10) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffffc3ff))
+#define SET_RG_RX_ULG_TZ_GC(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 14) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xffff3fff))
+#define SET_RG_RX_ULG_TZ_CAP(_VAL_) (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (((_VAL_) << 16) | ((REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) & 0xfff8ffff))
+#define SET_RG_HPF1_FAST_SET_X(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffe))
+#define SET_RG_HPF1_FAST_SET_Y(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffd))
+#define SET_RG_HPF1_FAST_SET_Z(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffffb))
+#define SET_RG_HPF_T1A(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffffe7))
+#define SET_RG_HPF_T1B(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffff9f))
+#define SET_RG_HPF_T1C(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 7) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffffe7f))
+#define SET_RG_RX_LNA_TRI_SEL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xfffff9ff))
+#define SET_RG_RX_LNA_SETTLE(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffe7ff))
+#define SET_RG_TXGAIN_PHYCTRL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffffdfff))
+#define SET_RG_TX_GAIN(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffc03fff))
+#define SET_RG_TXGAIN_MANUAL(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xffbfffff))
+#define SET_RG_TX_GAIN_OFFSET(_VAL_) (REG32(ADR_RX_TX_FSM_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_RX_TX_FSM_REGISTER)) & 0xf87fffff))
+#define SET_RG_ADC_CLKSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffffe))
+#define SET_RG_ADC_DIBIAS(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff9))
+#define SET_RG_ADC_DIVR(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffff7))
+#define SET_RG_ADC_DVCMI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffffffcf))
+#define SET_RG_ADC_SAMSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffc3f))
+#define SET_RG_ADC_STNBY(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffffbff))
+#define SET_RG_ADC_TESTMODE(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffff7ff))
+#define SET_RG_ADC_TSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffff0fff))
+#define SET_RG_ADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfffcffff))
+#define SET_RG_DICMP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfff3ffff))
+#define SET_RG_DIOP(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xffcfffff))
+#define SET_RG_SARADC_VRSEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xff3fffff))
+#define SET_RG_EN_SAR_TEST(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 24) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfcffffff))
+#define SET_RG_SARADC_THERMAL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 26) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xfbffffff))
+#define SET_RG_SARADC_TSSI(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xf7ffffff))
+#define SET_RG_CLK_SAR_SEL(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 28) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xcfffffff))
+#define SET_RG_EN_SARADC(_VAL_) (REG32(ADR_RX_ADC_REGISTER)) = (((_VAL_) << 30) | ((REG32(ADR_RX_ADC_REGISTER)) & 0xbfffffff))
+#define SET_RG_DACI1ST(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffffc))
+#define SET_RG_TX_DACLPF_ICOURSE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffff3))
+#define SET_RG_TX_DACLPF_IFINE(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffffcf))
+#define SET_RG_TX_DACLPF_VCM(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffff3f))
+#define SET_RG_TX_DAC_CKEDGE_SEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffffeff))
+#define SET_RG_TX_DAC_IBIAS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfffff9ff))
+#define SET_RG_TX_DAC_OS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffffc7ff))
+#define SET_RG_TX_DAC_RCAL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffff3fff))
+#define SET_RG_TX_DAC_TSEL(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xfff0ffff))
+#define SET_RG_TX_EN_VOLTAGE_IN(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 20) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffefffff))
+#define SET_RG_TXLPF_BYPASS(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffdfffff))
+#define SET_RG_TXLPF_BOOSTI(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xffbfffff))
+#define SET_RG_TX_DAC_IOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 23) | ((REG32(ADR_TX_DAC_REGISTER)) & 0xf87fffff))
+#define SET_RG_TX_DAC_QOFFSET(_VAL_) (REG32(ADR_TX_DAC_REGISTER)) = (((_VAL_) << 27) | ((REG32(ADR_TX_DAC_REGISTER)) & 0x87ffffff))
+#define SET_RG_EN_SX_R3(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffe))
+#define SET_RG_EN_SX_CH(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffd))
+#define SET_RG_EN_SX_CHP(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffffb))
+#define SET_RG_EN_SX_DIVCK(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffff7))
+#define SET_RG_EN_SX_VCOBF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 4) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffef))
+#define SET_RG_EN_SX_VCO(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffdf))
+#define SET_RG_EN_SX_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 6) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffffbf))
+#define SET_RG_EN_SX_DITHER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 8) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffffeff))
+#define SET_RG_EN_SX_VT_MON(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 11) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffff7ff))
+#define SET_RG_EN_SX_VT_MON_DG(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffefff))
+#define SET_RG_EN_SX_DIV(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffdfff))
+#define SET_RG_EN_SX_LPF(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffffbfff))
+#define SET_RG_EN_DPL_MOD(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xffff7fff))
+#define SET_RG_DPL_MOD_ORDER(_VAL_) (REG32(ADR_SX_ENABLE_REGISTER)) = (((_VAL_) << 16) | ((REG32(ADR_SX_ENABLE_REGISTER)) & 0xfffcffff))
+#define SET_RG_SX_RFCTRL_F(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_1)) & 0xff000000))
+#define SET_RG_SX_SEL_CP(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_REGISTER_1)) & 0xf0ffffff))
+#define SET_RG_SX_SEL_CS(_VAL_) (REG32(ADR_SYN_REGISTER_1)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_REGISTER_1)) & 0x0fffffff))
+#define SET_RG_SX_RFCTRL_CH(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfffff800))
+#define SET_RG_SX_SEL_C3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_REGISTER_2)) & 0xffff87ff))
+#define SET_RG_SX_SEL_RS(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfff07fff))
+#define SET_RG_SX_SEL_R3(_VAL_) (REG32(ADR_SYN_REGISTER_2)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_REGISTER_2)) & 0xfe0fffff))
+#define SET_RG_SX_SEL_ICHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffffe0))
+#define SET_RG_SX_SEL_PCHP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffffc1f))
+#define SET_RG_SX_SEL_CHP_REGOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffffc3ff))
+#define SET_RG_SX_SEL_CHP_UNIOP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffc3fff))
+#define SET_RG_SX_CHP_IOST_POL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 18) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfffbffff))
+#define SET_RG_SX_CHP_IOST(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffc7ffff))
+#define SET_RG_SX_PFDSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 22) | ((REG32(ADR_SYN_PFD_CHP)) & 0xffbfffff))
+#define SET_RG_SX_PFD_SET(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 23) | ((REG32(ADR_SYN_PFD_CHP)) & 0xff7fffff))
+#define SET_RG_SX_PFD_SET1(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfeffffff))
+#define SET_RG_SX_PFD_SET2(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 25) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfdffffff))
+#define SET_RG_SX_VBNCAS_SEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 26) | ((REG32(ADR_SYN_PFD_CHP)) & 0xfbffffff))
+#define SET_RG_SX_PFD_RST_H(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 27) | ((REG32(ADR_SYN_PFD_CHP)) & 0xf7ffffff))
+#define SET_RG_SX_PFD_TRUP(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_PFD_CHP)) & 0xefffffff))
+#define SET_RG_SX_PFD_TRDN(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 29) | ((REG32(ADR_SYN_PFD_CHP)) & 0xdfffffff))
+#define SET_RG_SX_PFD_TRSEL(_VAL_) (REG32(ADR_SYN_PFD_CHP)) = (((_VAL_) << 30) | ((REG32(ADR_SYN_PFD_CHP)) & 0xbfffffff))
+#define SET_RG_SX_VCOBA_R(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffffff8))
+#define SET_RG_SX_VCORSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffffff07))
+#define SET_RG_SX_VCOCUSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 8) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfffff0ff))
+#define SET_RG_SX_RXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 12) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xffff0fff))
+#define SET_RG_SX_TXBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 16) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xfff0ffff))
+#define SET_RG_SX_VCOBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xff0fffff))
+#define SET_RG_SX_DIVBFSEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_VCO_LOBF)) & 0xf0ffffff))
+#define SET_RG_SX_GNDR_SEL(_VAL_) (REG32(ADR_SYN_VCO_LOBF)) = (((_VAL_) << 28) | ((REG32(ADR_SYN_VCO_LOBF)) & 0x0fffffff))
+#define SET_RG_SX_DITHER_WEIGHT(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffffc))
+#define SET_RG_SX_MOD_ORDER(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 4) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffffcf))
+#define SET_RG_SX_RST_H_DIV(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 9) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffdff))
+#define SET_RG_SX_SDM_EDGE(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 10) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfffffbff))
+#define SET_RG_SX_XO_GM(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 11) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffe7ff))
+#define SET_RG_SX_REFBYTWO(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xffffdfff))
+#define SET_RG_SX_LCKEN(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xfff7ffff))
+#define SET_RG_SX_PREVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 20) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xff0fffff))
+#define SET_RG_SX_PSCONTERVDD(_VAL_) (REG32(ADR_SYN_DIV_SDM_XOSC)) = (((_VAL_) << 24) | ((REG32(ADR_SYN_DIV_SDM_XOSC)) & 0xf0ffffff))
+#define SET_RG_SX_PH(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 13) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffdfff))
+#define SET_RG_SX_PL(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 14) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xffffbfff))
+#define SET_RG_XOSC_CBANK_XO(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 15) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xfff87fff))
+#define SET_RG_XOSC_CBANK_XI(_VAL_) (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (((_VAL_) << 19) | ((REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) & 0xff87ffff))
+#define SET_RG_SX_VT_MON_MODE(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 0) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffffe))
+#define SET_RG_SX_VT_TH_HI(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 1) | ((REG32(ADR_SYN_LCK_VT)) & 0xfffffff9))
+#define SET_RG_SX_VT_TH_LO(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 3) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffe7))
+#define SET_RG_SX_VT_SET(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 5) | ((REG32(ADR_SYN_LCK_VT)) & 0xffffffdf))
+#define SET_RG_SX_VT_MON_TMR(_VAL_) (REG32(ADR_SYN_LCK_VT)) = (((_VAL_) << 6) | ((REG32(ADR_SYN_LCK_VT)) & 0xffff803f))
+#define SET_RG_EN_DP_VT_MON(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffffe))
+#define SET_RG_DP_VT_TH_HI(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xfffffff9))
+#define SET_RG_DP_VT_TH_LO(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffffe7))
+#define SET_RG_DP_CK320BY2(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 14) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffffbfff))
+#define SET_RG_DP_OD_TEST(_VAL_) (REG32(ADR_DPLL_VCO_REGISTER)) = (((_VAL_) << 21) | ((REG32(ADR_DPLL_VCO_REGISTER)) & 0xffdfffff))
+#define SET_RG_DP_BBPLL_BP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffffe))
+#define SET_RG_DP_BBPLL_ICP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffff9))
+#define SET_RG_DP_BBPLL_IDUAL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 3) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffffe7))
+#define SET_RG_DP_BBPLL_OD_TEST(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 5) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffe1f))
+#define SET_RG_DP_BBPLL_PD(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffffdff))
+#define SET_RG_DP_BBPLL_TESTSEL(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffffe3ff))
+#define SET_RG_DP_BBPLL_PFD_DLY(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 13) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xffff9fff))
+#define SET_RG_DP_RP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfffc7fff))
+#define SET_RG_DP_RHP(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 18) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0xfff3ffff))
+#define SET_RG_DP_BBPLL_SDM_EDGE(_VAL_) (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (((_VAL_) << 31) | ((REG32(ADR_DPLL_CP_PFD_REGISTER)) & 0x7fffffff))
+#define SET_RG_DP_FODIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 12) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xfff80fff))
+#define SET_RG_DP_REFDIV(_VAL_) (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (((_VAL_) << 22) | ((REG32(ADR_DPLL_DIVIDER_REGISTER)) & 0xe03fffff))
+#define SET_RG_IDACAI_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG15(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG14(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xff03ffff))
+#define SET_RG_DP_BBPLL_BS(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER1)) = (((_VAL_) << 24) | ((REG32(ADR_DCOC_IDAC_REGISTER1)) & 0xc0ffffff))
+#define SET_RG_IDACAI_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG13(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG12(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER2)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER2)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG11(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG10(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER3)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER3)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG9(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG8(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER4)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER4)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG7(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG6(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER5)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER5)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG5(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG4(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER6)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER6)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG3(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG2(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER7)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER7)) & 0xff03ffff))
+#define SET_RG_IDACAI_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 0) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xffffffc0))
+#define SET_RG_IDACAQ_PGAG1(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 6) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffff03f))
+#define SET_RG_IDACAI_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 12) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xfffc0fff))
+#define SET_RG_IDACAQ_PGAG0(_VAL_) (REG32(ADR_DCOC_IDAC_REGISTER8)) = (((_VAL_) << 18) | ((REG32(ADR_DCOC_IDAC_REGISTER8)) & 0xff03ffff))
+#define SET_RG_EN_RCAL(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffe))
+#define SET_RG_RCAL_SPD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 1) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffffd))
+#define SET_RG_RCAL_TMR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 2) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffe03))
+#define SET_RG_RCAL_CODE_CWR(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 9) | ((REG32(ADR_RCAL_REGISTER)) & 0xfffffdff))
+#define SET_RG_RCAL_CODE_CWD(_VAL_) (REG32(ADR_RCAL_REGISTER)) = (((_VAL_) << 10) | ((REG32(ADR_RCAL_REGISTER)) & 0xffff83ff))
+#define SET_RG_SX_SUB_SEL_CWR(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfffffffe))
+#define SET_RG_SX_SUB_SEL_CWD(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 1) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffffff01))
+#define SET_RG_SX_LCK_BIN_OFFSET(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff87fff))
+#define SET_RG_SX_LCK_BIN_PRECISION(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 19) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xfff7ffff))
+#define SET_RG_SX_LOCK_EN_N(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 20) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffefffff))
+#define SET_RG_SX_LOCK_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 21) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffdfffff))
+#define SET_RG_SX_SUB_MANUAL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 22) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xffbfffff))
+#define SET_RG_SX_SUB_SEL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xc07fffff))
+#define SET_RG_SX_MUX_SEL_VTH_BINL(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (((_VAL_) << 30) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_I)) & 0xbfffffff))
+#define SET_RG_TRX_DUMMMY(_VAL_) (REG32(ADR_TRX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_TRX_DUMMY_REGISTER)) & 0x00000000))
+#define SET_RG_SX_DUMMMY(_VAL_) (REG32(ADR_SX_DUMMY_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_SX_DUMMY_REGISTER)) & 0x00000000))
+#define SET_RCAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffe))
+#define SET_LCK_BIN_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 1) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffd))
+#define SET_VT_MON_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 2) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffffffb))
+#define SET_DA_R_CODE_LUT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 6) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xfffff83f))
+#define SET_AD_SX_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 11) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffffe7ff))
+#define SET_AD_DP_VT_MON_Q(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 13) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff9fff))
+#define SET_RTC_CAL_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 15) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffff7fff))
+#define SET_RG_SARADC_BIT(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 16) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffc0ffff))
+#define SET_SAR_ADC_FSM_RDY(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 22) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xffbfffff))
+#define SET_AD_CIRCUIT_VERSION(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_1)) = (((_VAL_) << 23) | ((REG32(ADR_READ_ONLY_FLAGS_1)) & 0xf87fffff))
+#define SET_DA_R_CAL_CODE(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 0) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xffffffe0))
+#define SET_DA_SX_SUB_SEL(_VAL_) (REG32(ADR_READ_ONLY_FLAGS_2)) = (((_VAL_) << 5) | ((REG32(ADR_READ_ONLY_FLAGS_2)) & 0xfffff01f))
+#define SET_RG_DPL_RFCTRL_CH(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xfffff800))
+#define SET_RG_RSSIADC_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 11) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xffff87ff))
+#define SET_RG_RX_ADC_I_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 15) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0xff807fff))
+#define SET_RG_RX_ADC_Q_RO_BIT(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) = (((_VAL_) << 23) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_I)) & 0x807fffff))
+#define SET_RG_DPL_RFCTRL_F(_VAL_) (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) & 0xff000000))
+#define SET_RG_SX_TARGET_CNT(_VAL_) (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (((_VAL_) << 0) | ((REG32(ADR_SX_LCK_BIN_REGISTERS_II)) & 0xffffe000))
+#define SET_RG_RTC_OFFSET(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 0) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xffffff00))
+#define SET_RG_RTC_CAL_TARGET_COUNT(_VAL_) (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (((_VAL_) << 8) | ((REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) & 0xfff000ff))
+#define SET_RG_RF_D_REG(_VAL_) (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (((_VAL_) << 0) | ((REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) & 0xffff0000))
+#define SET_DIRECT_MODE(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffe))
+#define SET_TAG_INTERLEAVE_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffd))
+#define SET_DIS_DEMAND(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 2) | ((REG32(ADR_MMU_CTRL)) & 0xfffffffb))
+#define SET_SAME_ID_ALLOC_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 3) | ((REG32(ADR_MMU_CTRL)) & 0xfffffff7))
+#define SET_HS_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_MMU_CTRL)) & 0xffffffef))
+#define SET_SRAM_ACCESS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 5) | ((REG32(ADR_MMU_CTRL)) & 0xffffffdf))
+#define SET_NOHIT_RPASS_MD(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 6) | ((REG32(ADR_MMU_CTRL)) & 0xffffffbf))
+#define SET_DMN_FLAG_CLR(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 7) | ((REG32(ADR_MMU_CTRL)) & 0xffffff7f))
+#define SET_ERR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_CTRL)) & 0xfffffeff))
+#define SET_ALR_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 9) | ((REG32(ADR_MMU_CTRL)) & 0xfffffdff))
+#define SET_MCH_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 10) | ((REG32(ADR_MMU_CTRL)) & 0xfffffbff))
+#define SET_TAG_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 11) | ((REG32(ADR_MMU_CTRL)) & 0xfffff7ff))
+#define SET_ABT_SW_RST_N(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_CTRL)) & 0xffffefff))
+#define SET_MMU_VER(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 13) | ((REG32(ADR_MMU_CTRL)) & 0xffff1fff))
+#define SET_MMU_SHARE_MCU(_VAL_) (REG32(ADR_MMU_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_CTRL)) & 0xff00ffff))
+#define SET_HS_WR(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_HS_CTRL)) & 0xfffffffe))
+#define SET_HS_FLAG(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 4) | ((REG32(ADR_HS_CTRL)) & 0xffffffef))
+#define SET_HS_ID(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_HS_CTRL)) & 0xffff80ff))
+#define SET_HS_CHANNEL(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_HS_CTRL)) & 0xfff0ffff))
+#define SET_HS_PAGE(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 20) | ((REG32(ADR_HS_CTRL)) & 0xff0fffff))
+#define SET_HS_DATA(_VAL_) (REG32(ADR_HS_CTRL)) = (((_VAL_) << 24) | ((REG32(ADR_HS_CTRL)) & 0x00ffffff))
+#define SET_CPU_POR0(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR0_7)) & 0xfffffff0))
+#define SET_CPU_POR1(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR0_7)) & 0xffffff0f))
+#define SET_CPU_POR2(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR0_7)) & 0xfffff0ff))
+#define SET_CPU_POR3(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR0_7)) & 0xffff0fff))
+#define SET_CPU_POR4(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR0_7)) & 0xfff0ffff))
+#define SET_CPU_POR5(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR0_7)) & 0xff0fffff))
+#define SET_CPU_POR6(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR0_7)) & 0xf0ffffff))
+#define SET_CPU_POR7(_VAL_) (REG32(ADR_CPU_POR0_7)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR0_7)) & 0x0fffffff))
+#define SET_CPU_POR8(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 0) | ((REG32(ADR_CPU_POR8_F)) & 0xfffffff0))
+#define SET_CPU_POR9(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 4) | ((REG32(ADR_CPU_POR8_F)) & 0xffffff0f))
+#define SET_CPU_PORA(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 8) | ((REG32(ADR_CPU_POR8_F)) & 0xfffff0ff))
+#define SET_CPU_PORB(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 12) | ((REG32(ADR_CPU_POR8_F)) & 0xffff0fff))
+#define SET_CPU_PORC(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 16) | ((REG32(ADR_CPU_POR8_F)) & 0xfff0ffff))
+#define SET_CPU_PORD(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 20) | ((REG32(ADR_CPU_POR8_F)) & 0xff0fffff))
+#define SET_CPU_PORE(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 24) | ((REG32(ADR_CPU_POR8_F)) & 0xf0ffffff))
+#define SET_CPU_PORF(_VAL_) (REG32(ADR_CPU_POR8_F)) = (((_VAL_) << 28) | ((REG32(ADR_CPU_POR8_F)) & 0x0fffffff))
+#define SET_ACC_WR_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 0) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffffc0))
+#define SET_ACC_RD_LEN(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 8) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffffc0ff))
+#define SET_REQ_NACK_CLR(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 15) | ((REG32(ADR_REG_LEN_CTRL)) & 0xffff7fff))
+#define SET_NACK_FLAG_BUS(_VAL_) (REG32(ADR_REG_LEN_CTRL)) = (((_VAL_) << 16) | ((REG32(ADR_REG_LEN_CTRL)) & 0x0000ffff))
+#define SET_DMN_R_PASS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xffff0000))
+#define SET_PARA_ALC_RLS(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfffeffff))
+#define SET_REQ_PORNS_CHGEN(_VAL_) (REG32(ADR_DMN_READ_BYPASS)) = (((_VAL_) << 24) | ((REG32(ADR_DMN_READ_BYPASS)) & 0xfeffffff))
+#define SET_ALC_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffffff80))
+#define SET_ALC_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xffff7fff))
+#define SET_RLS_ABT_ID(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_RLS_ABORT)) & 0xff80ffff))
+#define SET_RLS_ABT_INT(_VAL_) (REG32(ADR_ALC_RLS_ABORT)) = (((_VAL_) << 31) | ((REG32(ADR_ALC_RLS_ABORT)) & 0x7fffffff))
+#define SET_DEBUG_CTL(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_CTL)) & 0xffffff00))
+#define SET_DEBUG_H16(_VAL_) (REG32(ADR_DEBUG_CTL)) = (((_VAL_) << 8) | ((REG32(ADR_DEBUG_CTL)) & 0xfffffeff))
+#define SET_DEBUG_OUT(_VAL_) (REG32(ADR_DEBUG_OUT)) = (((_VAL_) << 0) | ((REG32(ADR_DEBUG_OUT)) & 0x00000000))
+#define SET_ALC_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffe))
+#define SET_RLS_ERR(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_MMU_STATUS)) & 0xfffffffd))
+#define SET_AL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_MMU_STATUS)) & 0xfffff8ff))
+#define SET_RL_STATE(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 12) | ((REG32(ADR_MMU_STATUS)) & 0xffff8fff))
+#define SET_ALC_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_MMU_STATUS)) & 0xff80ffff))
+#define SET_RLS_ERR_ID(_VAL_) (REG32(ADR_MMU_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_MMU_STATUS)) & 0x80ffffff))
+#define SET_DMN_NOHIT_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffe))
+#define SET_DMN_FLAG(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_STATUS)) & 0xfffffffd))
+#define SET_DMN_WR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_STATUS)) & 0xfffffff7))
+#define SET_DMN_PORT(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_STATUS)) & 0xffffff0f))
+#define SET_DMN_NHIT_ID(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_STATUS)) & 0xffff80ff))
+#define SET_DMN_NHIT_ADDR(_VAL_) (REG32(ADR_DMN_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_STATUS)) & 0x0000ffff))
+#define SET_TX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_STATUS)) & 0xffffff00))
+#define SET_RX_MOUNT(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_TAG_STATUS)) & 0xffff00ff))
+#define SET_AVA_TAG(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_STATUS)) & 0xfe00ffff))
+#define SET_PKTBUF_FULL(_VAL_) (REG32(ADR_TAG_STATUS)) = (((_VAL_) << 31) | ((REG32(ADR_TAG_STATUS)) & 0x7fffffff))
+#define SET_DMN_NOHIT_MCU(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffe))
+#define SET_DMN_MCU_FLAG(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 1) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffffd))
+#define SET_DMN_MCU_WR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 3) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xfffffff7))
+#define SET_DMN_MCU_PORT(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 4) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffffff0f))
+#define SET_DMN_MCU_ID(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 8) | ((REG32(ADR_DMN_MCU_STATUS)) & 0xffff80ff))
+#define SET_DMN_MCU_ADDR(_VAL_) (REG32(ADR_DMN_MCU_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_DMN_MCU_STATUS)) & 0x0000ffff))
+#define SET_MB_IDTBL_31_0(_VAL_) (REG32(ADR_MB_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_0_STATUS)) & 0x00000000))
+#define SET_MB_IDTBL_63_32(_VAL_) (REG32(ADR_MB_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_1_STATUS)) & 0x00000000))
+#define SET_MB_IDTBL_95_64(_VAL_) (REG32(ADR_MB_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_2_STATUS)) & 0x00000000))
+#define SET_MB_IDTBL_127_96(_VAL_) (REG32(ADR_MB_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_IDTBL_3_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_31_0(_VAL_) (REG32(ADR_PKT_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_0_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_63_32(_VAL_) (REG32(ADR_PKT_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_1_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_95_64(_VAL_) (REG32(ADR_PKT_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_2_STATUS)) & 0x00000000))
+#define SET_PKT_IDTBL_127_96(_VAL_) (REG32(ADR_PKT_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_IDTBL_3_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_31_0(_VAL_) (REG32(ADR_DMN_IDTBL_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_0_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_63_32(_VAL_) (REG32(ADR_DMN_IDTBL_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_1_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_95_64(_VAL_) (REG32(ADR_DMN_IDTBL_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_2_STATUS)) & 0x00000000))
+#define SET_DMN_IDTBL_127_96(_VAL_) (REG32(ADR_DMN_IDTBL_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_DMN_IDTBL_3_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_31_0(_VAL_) (REG32(ADR_MB_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_0_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_63_32(_VAL_) (REG32(ADR_MB_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_1_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_95_64(_VAL_) (REG32(ADR_MB_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_2_STATUS)) & 0x00000000))
+#define SET_NEQ_MB_ID_127_96(_VAL_) (REG32(ADR_MB_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_MB_NEQID_3_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_31_0(_VAL_) (REG32(ADR_PKT_NEQID_0_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_0_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_63_32(_VAL_) (REG32(ADR_PKT_NEQID_1_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_1_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_95_64(_VAL_) (REG32(ADR_PKT_NEQID_2_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_2_STATUS)) & 0x00000000))
+#define SET_NEQ_PKT_ID_127_96(_VAL_) (REG32(ADR_PKT_NEQID_3_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_PKT_NEQID_3_STATUS)) & 0x00000000))
+#define SET_ALC_NOCHG_ID(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 0) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffffff80))
+#define SET_ALC_NOCHG_INT(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 15) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xffff7fff))
+#define SET_NEQ_PKT_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 16) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfffeffff))
+#define SET_NEQ_MB_FLAG(_VAL_) (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (((_VAL_) << 24) | ((REG32(ADR_ALC_NOCHG_ID_STATUS)) & 0xfeffffff))
+#define SET_SRAM_TAG_0(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0xffff0000))
+#define SET_SRAM_TAG_1(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_0)) & 0x0000ffff))
+#define SET_SRAM_TAG_2(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0xffff0000))
+#define SET_SRAM_TAG_3(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_1)) & 0x0000ffff))
+#define SET_SRAM_TAG_4(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0xffff0000))
+#define SET_SRAM_TAG_5(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_2)) & 0x0000ffff))
+#define SET_SRAM_TAG_6(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0xffff0000))
+#define SET_SRAM_TAG_7(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_3)) & 0x0000ffff))
+#define SET_SRAM_TAG_8(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0xffff0000))
+#define SET_SRAM_TAG_9(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_4)) & 0x0000ffff))
+#define SET_SRAM_TAG_10(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0xffff0000))
+#define SET_SRAM_TAG_11(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_5)) & 0x0000ffff))
+#define SET_SRAM_TAG_12(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0xffff0000))
+#define SET_SRAM_TAG_13(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_6)) & 0x0000ffff))
+#define SET_SRAM_TAG_14(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 0) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0xffff0000))
+#define SET_SRAM_TAG_15(_VAL_) (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (((_VAL_) << 16) | ((REG32(ADR_TAG_SRAM0_F_STATUS_7)) & 0x0000ffff))
+#define DEF_BRG_SW_RST() (REG32(ADR_BRG_SW_RST)) = (0x00000000)
+#define DEF_BOOT() (REG32(ADR_BOOT)) = (0x00040000)
+#define DEF_CHIP_ID_0() (REG32(ADR_CHIP_ID_0)) = (0x31333131)
+#define DEF_CHIP_ID_1() (REG32(ADR_CHIP_ID_1)) = (0x322d3230)
+#define DEF_CHIP_ID_2() (REG32(ADR_CHIP_ID_2)) = (0x32303041)
+#define DEF_CHIP_ID_3() (REG32(ADR_CHIP_ID_3)) = (0x53535636)
+#define DEF_CLOCK_SELECTION() (REG32(ADR_CLOCK_SELECTION)) = (0x00000000)
+#define DEF_PLATFORM_CLOCK_ENABLE() (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (0x008fffff)
+#define DEF_SYS_CSR_CLOCK_ENABLE() (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (0x00000400)
+#define DEF_MCU_DBG_SEL() (REG32(ADR_MCU_DBG_SEL)) = (0x00000000)
+#define DEF_MCU_DBG_DATA() (REG32(ADR_MCU_DBG_DATA)) = (0x00000000)
+#define DEF_AHB_BRG_STATUS() (REG32(ADR_AHB_BRG_STATUS)) = (0x00000000)
+#define DEF_BIST_BIST_CTRL() (REG32(ADR_BIST_BIST_CTRL)) = (0x00000000)
+#define DEF_BIST_MODE_REG_IN() (REG32(ADR_BIST_MODE_REG_IN)) = (0x001ffe3e)
+#define DEF_BIST_MODE_REG_OUT() (REG32(ADR_BIST_MODE_REG_OUT)) = (0x00000000)
+#define DEF_BIST_MONITOR_BUS_LSB() (REG32(ADR_BIST_MONITOR_BUS_LSB)) = (0x00000000)
+#define DEF_BIST_MONITOR_BUS_MSB() (REG32(ADR_BIST_MONITOR_BUS_MSB)) = (0x00000000)
+#define DEF_TB_ADR_SEL() (REG32(ADR_TB_ADR_SEL)) = (0x00000000)
+#define DEF_TB_RDATA() (REG32(ADR_TB_RDATA)) = (0x00000000)
+#define DEF_UART_W2B() (REG32(ADR_UART_W2B)) = (0x00000000)
+#define DEF_AHB_ILL_ADDR() (REG32(ADR_AHB_ILL_ADDR)) = (0x00000000)
+#define DEF_AHB_FEN_ADDR() (REG32(ADR_AHB_FEN_ADDR)) = (0x00000000)
+#define DEF_AHB_ILLFEN_STATUS() (REG32(ADR_AHB_ILLFEN_STATUS)) = (0x00000000)
+#define DEF_PWM_A() (REG32(ADR_PWM_A)) = (0x400a1010)
+#define DEF_PWM_B() (REG32(ADR_PWM_B)) = (0x400a1010)
+#define DEF_HBUSREQ_LOCK() (REG32(ADR_HBUSREQ_LOCK)) = (0x00001ffd)
+#define DEF_HBURST_LOCK() (REG32(ADR_HBURST_LOCK)) = (0x00000000)
+#define DEF_PRESCALER_USTIMER() (REG32(ADR_PRESCALER_USTIMER)) = (0x00000028)
+#define DEF_BIST_MODE_REG_IN_MMU() (REG32(ADR_BIST_MODE_REG_IN_MMU)) = (0x0000fe3e)
+#define DEF_BIST_MODE_REG_OUT_MMU() (REG32(ADR_BIST_MODE_REG_OUT_MMU)) = (0x00000000)
+#define DEF_BIST_MONITOR_BUS_MMU() (REG32(ADR_BIST_MONITOR_BUS_MMU)) = (0x00000000)
+#define DEF_TEST_MODE() (REG32(ADR_TEST_MODE)) = (0x00000000)
+#define DEF_BOOT_INFO() (REG32(ADR_BOOT_INFO)) = (0x00000000)
+#define DEF_SD_INIT_CFG() (REG32(ADR_SD_INIT_CFG)) = (0x00000000)
+#define DEF_SPARE_UART_INFO() (REG32(ADR_SPARE_UART_INFO)) = (0x00000000)
+#define DEF_TU0_MICROSECOND_TIMER() (REG32(ADR_TU0_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU0_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU0_DUMMY_BIT_0() (REG32(ADR_TU0_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU0_DUMMY_BIT_1() (REG32(ADR_TU0_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TU1_MICROSECOND_TIMER() (REG32(ADR_TU1_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU1_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU1_DUMMY_BIT_0() (REG32(ADR_TU1_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU1_DUMMY_BIT_1() (REG32(ADR_TU1_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TU2_MICROSECOND_TIMER() (REG32(ADR_TU2_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU2_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU2_DUMMY_BIT_0() (REG32(ADR_TU2_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU2_DUMMY_BIT_1() (REG32(ADR_TU2_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TU3_MICROSECOND_TIMER() (REG32(ADR_TU3_MICROSECOND_TIMER)) = (0x00000000)
+#define DEF_TU3_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TU3_DUMMY_BIT_0() (REG32(ADR_TU3_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TU3_DUMMY_BIT_1() (REG32(ADR_TU3_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM0_MILISECOND_TIMER() (REG32(ADR_TM0_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM0_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM0_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM0_DUMMY_BIT_0() (REG32(ADR_TM0_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM0_DUMMY_BIT_1() (REG32(ADR_TM0_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM1_MILISECOND_TIMER() (REG32(ADR_TM1_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM1_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM1_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM1_DUMMY_BIT_0() (REG32(ADR_TM1_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM1_DUMMY_BIT_1() (REG32(ADR_TM1_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM2_MILISECOND_TIMER() (REG32(ADR_TM2_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM2_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM2_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM2_DUMMY_BIT_0() (REG32(ADR_TM2_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM2_DUMMY_BIT_1() (REG32(ADR_TM2_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_TM3_MILISECOND_TIMER() (REG32(ADR_TM3_MILISECOND_TIMER)) = (0x00000000)
+#define DEF_TM3_CURRENT_MILISECOND_TIME_VALUE() (REG32(ADR_TM3_CURRENT_MILISECOND_TIME_VALUE)) = (0x00000000)
+#define DEF_TM3_DUMMY_BIT_0() (REG32(ADR_TM3_DUMMY_BIT_0)) = (0x00000000)
+#define DEF_TM3_DUMMY_BIT_1() (REG32(ADR_TM3_DUMMY_BIT_1)) = (0x00000000)
+#define DEF_MCU_WDOG_REG() (REG32(ADR_MCU_WDOG_REG)) = (0x00000000)
+#define DEF_SYS_WDOG_REG() (REG32(ADR_SYS_WDOG_REG)) = (0x00000000)
+#define DEF_PAD6() (REG32(ADR_PAD6)) = (0x00000008)
+#define DEF_PAD7() (REG32(ADR_PAD7)) = (0x00000008)
+#define DEF_PAD8() (REG32(ADR_PAD8)) = (0x00000008)
+#define DEF_PAD9() (REG32(ADR_PAD9)) = (0x00000008)
+#define DEF_PAD11() (REG32(ADR_PAD11)) = (0x00000008)
+#define DEF_PAD15() (REG32(ADR_PAD15)) = (0x0000000a)
+#define DEF_PAD16() (REG32(ADR_PAD16)) = (0x0000000a)
+#define DEF_PAD17() (REG32(ADR_PAD17)) = (0x0000000a)
+#define DEF_PAD18() (REG32(ADR_PAD18)) = (0x0000000a)
+#define DEF_PAD19() (REG32(ADR_PAD19)) = (0x00007000)
+#define DEF_PAD20() (REG32(ADR_PAD20)) = (0x0000000a)
+#define DEF_PAD21() (REG32(ADR_PAD21)) = (0x0000000a)
+#define DEF_PAD22() (REG32(ADR_PAD22)) = (0x00000009)
+#define DEF_PAD24() (REG32(ADR_PAD24)) = (0x00000008)
+#define DEF_PAD25() (REG32(ADR_PAD25)) = (0x0000000b)
+#define DEF_PAD27() (REG32(ADR_PAD27)) = (0x00000008)
+#define DEF_PAD28() (REG32(ADR_PAD28)) = (0x00000008)
+#define DEF_PAD29() (REG32(ADR_PAD29)) = (0x00000009)
+#define DEF_PAD30() (REG32(ADR_PAD30)) = (0x0000000a)
+#define DEF_PAD31() (REG32(ADR_PAD31)) = (0x0000000a)
+#define DEF_PAD32() (REG32(ADR_PAD32)) = (0x0000000a)
+#define DEF_PAD33() (REG32(ADR_PAD33)) = (0x0000000a)
+#define DEF_PAD34() (REG32(ADR_PAD34)) = (0x0000000a)
+#define DEF_PAD42() (REG32(ADR_PAD42)) = (0x0000000a)
+#define DEF_PAD43() (REG32(ADR_PAD43)) = (0x0000000a)
+#define DEF_PAD44() (REG32(ADR_PAD44)) = (0x0000000a)
+#define DEF_PAD45() (REG32(ADR_PAD45)) = (0x0000000a)
+#define DEF_PAD46() (REG32(ADR_PAD46)) = (0x0000000a)
+#define DEF_PAD47() (REG32(ADR_PAD47)) = (0x00100000)
+#define DEF_PAD48() (REG32(ADR_PAD48)) = (0x00100808)
+#define DEF_PAD49() (REG32(ADR_PAD49)) = (0x00100008)
+#define DEF_PAD50() (REG32(ADR_PAD50)) = (0x00100008)
+#define DEF_PAD51() (REG32(ADR_PAD51)) = (0x00100008)
+#define DEF_PAD52() (REG32(ADR_PAD52)) = (0x00100000)
+#define DEF_PAD53() (REG32(ADR_PAD53)) = (0x0000000a)
+#define DEF_PAD54() (REG32(ADR_PAD54)) = (0x00000000)
+#define DEF_PAD56() (REG32(ADR_PAD56)) = (0x00000000)
+#define DEF_PAD57() (REG32(ADR_PAD57)) = (0x00000008)
+#define DEF_PAD58() (REG32(ADR_PAD58)) = (0x0000000a)
+#define DEF_PAD59() (REG32(ADR_PAD59)) = (0x0000000a)
+#define DEF_PAD60() (REG32(ADR_PAD60)) = (0x0000000a)
+#define DEF_PAD61() (REG32(ADR_PAD61)) = (0x0000000a)
+#define DEF_PAD62() (REG32(ADR_PAD62)) = (0x0000000a)
+#define DEF_PAD64() (REG32(ADR_PAD64)) = (0x00000009)
+#define DEF_PAD65() (REG32(ADR_PAD65)) = (0x00000009)
+#define DEF_PAD66() (REG32(ADR_PAD66)) = (0x00000008)
+#define DEF_PAD68() (REG32(ADR_PAD68)) = (0x00000008)
+#define DEF_PAD67() (REG32(ADR_PAD67)) = (0x00000159)
+#define DEF_PAD69() (REG32(ADR_PAD69)) = (0x0000000b)
+#define DEF_PAD70() (REG32(ADR_PAD70)) = (0x00000008)
+#define DEF_PAD231() (REG32(ADR_PAD231)) = (0x00000008)
+#define DEF_PIN_SEL_0() (REG32(ADR_PIN_SEL_0)) = (0x00000000)
+#define DEF_PIN_SEL_1() (REG32(ADR_PIN_SEL_1)) = (0x00000000)
+#define DEF_IO_PORT_REG() (REG32(ADR_IO_PORT_REG)) = (0x00010000)
+#define DEF_INT_MASK_REG() (REG32(ADR_INT_MASK_REG)) = (0x000000ff)
+#define DEF_INT_STATUS_REG() (REG32(ADR_INT_STATUS_REG)) = (0x00000000)
+#define DEF_FN1_STATUS_REG() (REG32(ADR_FN1_STATUS_REG)) = (0x00000000)
+#define DEF_CARD_PKT_STATUS_TEST() (REG32(ADR_CARD_PKT_STATUS_TEST)) = (0x00000000)
+#define DEF_SYSTEM_INFORMATION_REG() (REG32(ADR_SYSTEM_INFORMATION_REG)) = (0x00000000)
+#define DEF_CARD_RCA_REG() (REG32(ADR_CARD_RCA_REG)) = (0x00000000)
+#define DEF_SDIO_FIFO_WR_THLD_REG() (REG32(ADR_SDIO_FIFO_WR_THLD_REG)) = (0x00000000)
+#define DEF_SDIO_FIFO_WR_LIMIT_REG() (REG32(ADR_SDIO_FIFO_WR_LIMIT_REG)) = (0x00000000)
+#define DEF_SDIO_TX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_TX_DATA_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_THLD_FOR_CMD53RD_REG() (REG32(ADR_SDIO_THLD_FOR_CMD53RD_REG)) = (0x00000000)
+#define DEF_SDIO_RX_DATA_BATCH_SIZE_REG() (REG32(ADR_SDIO_RX_DATA_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_LOG_START_END_DATA_REG() (REG32(ADR_SDIO_LOG_START_END_DATA_REG)) = (0x00000000)
+#define DEF_SDIO_BYTE_MODE_BATCH_SIZE_REG() (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (0x00000000)
+#define DEF_SDIO_LAST_CMD_INDEX_CRC_REG() (REG32(ADR_SDIO_LAST_CMD_INDEX_CRC_REG)) = (0x00000000)
+#define DEF_SDIO_LAST_CMD_ARG_REG() (REG32(ADR_SDIO_LAST_CMD_ARG_REG)) = (0x00000000)
+#define DEF_SDIO_BUS_STATE_DEBUG_MONITOR() (REG32(ADR_SDIO_BUS_STATE_DEBUG_MONITOR)) = (0x00000000)
+#define DEF_SDIO_CARD_STATUS_REG() (REG32(ADR_SDIO_CARD_STATUS_REG)) = (0x00000000)
+#define DEF_R5_RESP_FLAG_OUT_TIMING() (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (0x00000000)
+#define DEF_CMD52_DATA_FOR_LAST_TIME() (REG32(ADR_CMD52_DATA_FOR_LAST_TIME)) = (0x00000000)
+#define DEF_FN1_DMA_START_ADDR_REG() (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (0x00000000)
+#define DEF_FN1_INT_CTRL_RESET() (REG32(ADR_FN1_INT_CTRL_RESET)) = (0x00000000)
+#define DEF_IO_REG_PORT_REG() (REG32(ADR_IO_REG_PORT_REG)) = (0x00010020)
+#define DEF_SDIO_FIFO_ERROR_CNT() (REG32(ADR_SDIO_FIFO_ERROR_CNT)) = (0x00000000)
+#define DEF_SDIO_CRC7_CRC16_ERROR_REG() (REG32(ADR_SDIO_CRC7_CRC16_ERROR_REG)) = (0x00000000)
+#define DEF_SDIO_BLOCK_CNT_INFO() (REG32(ADR_SDIO_BLOCK_CNT_INFO)) = (0x00000000)
+#define DEF_RX_DATA_CMD52_ABORT_COUNT() (REG32(ADR_RX_DATA_CMD52_ABORT_COUNT)) = (0x00000000)
+#define DEF_FIFO_PTR_READ_BLOCK_CNT() (REG32(ADR_FIFO_PTR_READ_BLOCK_CNT)) = (0x00000000)
+#define DEF_TX_TIME_OUT_READ_CTRL() (REG32(ADR_TX_TIME_OUT_READ_CTRL)) = (0x00000000)
+#define DEF_SDIO_TX_ALLOC_REG() (REG32(ADR_SDIO_TX_ALLOC_REG)) = (0x00000000)
+#define DEF_SDIO_TX_INFORM() (REG32(ADR_SDIO_TX_INFORM)) = (0x00000000)
+#define DEF_F1_BLOCK_SIZE_0_REG() (REG32(ADR_F1_BLOCK_SIZE_0_REG)) = (0x00000000)
+#define DEF_SDIO_COMMAND_LOG_DATA_31_0() (REG32(ADR_SDIO_COMMAND_LOG_DATA_31_0)) = (0x000000ec)
+#define DEF_SDIO_COMMAND_LOG_DATA_63_32() (REG32(ADR_SDIO_COMMAND_LOG_DATA_63_32)) = (0xce000000)
+#define DEF_SYSTEM_INFORMATION_REGISTER() (REG32(ADR_SYSTEM_INFORMATION_REGISTER)) = (0x00000000)
+#define DEF_CCCR_00H_REG() (REG32(ADR_CCCR_00H_REG)) = (0x00000000)
+#define DEF_CCCR_04H_REG() (REG32(ADR_CCCR_04H_REG)) = (0x00000000)
+#define DEF_CCCR_08H_REG() (REG32(ADR_CCCR_08H_REG)) = (0x00000000)
+#define DEF_CCCR_13H_REG() (REG32(ADR_CCCR_13H_REG)) = (0x00000000)
+#define DEF_FBR_100H_REG() (REG32(ADR_FBR_100H_REG)) = (0x00000000)
+#define DEF_FBR_109H_REG() (REG32(ADR_FBR_109H_REG)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_0() (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_1() (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_2() (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_3() (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_4() (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_5() (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_6() (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_7() (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_8() (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_9() (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_10() (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_11() (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_12() (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_13() (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_14() (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (0x00000000)
+#define DEF_F0_CIS_CONTENT_REG_15() (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_0() (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_1() (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_2() (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_3() (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_4() (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_5() (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_6() (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_7() (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_8() (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_9() (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_10() (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_11() (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_12() (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_13() (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_14() (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (0x00000000)
+#define DEF_F1_CIS_CONTENT_REG_15() (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (0x00000000)
+#define DEF_SPI_MODE() (REG32(ADR_SPI_MODE)) = (0x00000000)
+#define DEF_RX_QUOTA() (REG32(ADR_RX_QUOTA)) = (0x00000000)
+#define DEF_CONDITION_NUMBER() (REG32(ADR_CONDITION_NUMBER)) = (0x00000004)
+#define DEF_HOST_PATH() (REG32(ADR_HOST_PATH)) = (0x00000001)
+#define DEF_TX_SEG() (REG32(ADR_TX_SEG)) = (0x00000000)
+#define DEF_DEBUG_BURST_MODE() (REG32(ADR_DEBUG_BURST_MODE)) = (0x00000000)
+#define DEF_SPI_TO_PHY_PARAM1() (REG32(ADR_SPI_TO_PHY_PARAM1)) = (0x000e0006)
+#define DEF_SPI_TO_PHY_PARAM2() (REG32(ADR_SPI_TO_PHY_PARAM2)) = (0x000e000e)
+#define DEF_SPI_STS() (REG32(ADR_SPI_STS)) = (0x00000000)
+#define DEF_TX_ALLOC_SET() (REG32(ADR_TX_ALLOC_SET)) = (0x00000000)
+#define DEF_TX_ALLOC() (REG32(ADR_TX_ALLOC)) = (0x00000000)
+#define DEF_DBG_CNT() (REG32(ADR_DBG_CNT)) = (0x00000000)
+#define DEF_DBG_CNT2() (REG32(ADR_DBG_CNT2)) = (0x00000000)
+#define DEF_DBG_CNT3() (REG32(ADR_DBG_CNT3)) = (0x00000000)
+#define DEF_DBG_CNT4() (REG32(ADR_DBG_CNT4)) = (0x00000000)
+#define DEF_INT_TAG() (REG32(ADR_INT_TAG)) = (0x00000000)
+#define DEF_I2CM_EN() (REG32(ADR_I2CM_EN)) = (0x00000074)
+#define DEF_I2CM_DEV_A() (REG32(ADR_I2CM_DEV_A)) = (0x00008000)
+#define DEF_I2CM_LEN() (REG32(ADR_I2CM_LEN)) = (0x00000000)
+#define DEF_I2CM_WDAT() (REG32(ADR_I2CM_WDAT)) = (0x00000000)
+#define DEF_I2CM_RDAT() (REG32(ADR_I2CM_RDAT)) = (0x00000000)
+#define DEF_I2CM_EN_2() (REG32(ADR_I2CM_EN_2)) = (0x00010000)
+#define DEF_UART_DATA() (REG32(ADR_UART_DATA)) = (0x00000000)
+#define DEF_UART_IER() (REG32(ADR_UART_IER)) = (0x00000000)
+#define DEF_UART_FCR() (REG32(ADR_UART_FCR)) = (0x00000001)
+#define DEF_UART_LCR() (REG32(ADR_UART_LCR)) = (0x00000003)
+#define DEF_UART_MCR() (REG32(ADR_UART_MCR)) = (0x00000000)
+#define DEF_UART_LSR() (REG32(ADR_UART_LSR)) = (0x00000000)
+#define DEF_UART_MSR() (REG32(ADR_UART_MSR)) = (0x00000000)
+#define DEF_UART_SPR() (REG32(ADR_UART_SPR)) = (0x00000000)
+#define DEF_UART_RTHR() (REG32(ADR_UART_RTHR)) = (0x000000c8)
+#define DEF_UART_ISR() (REG32(ADR_UART_ISR)) = (0x000000c1)
+#define DEF_DAT_UART_DATA() (REG32(ADR_DAT_UART_DATA)) = (0x00000000)
+#define DEF_DAT_UART_IER() (REG32(ADR_DAT_UART_IER)) = (0x00000000)
+#define DEF_DAT_UART_FCR() (REG32(ADR_DAT_UART_FCR)) = (0x00000001)
+#define DEF_DAT_UART_LCR() (REG32(ADR_DAT_UART_LCR)) = (0x00000003)
+#define DEF_DAT_UART_MCR() (REG32(ADR_DAT_UART_MCR)) = (0x00000000)
+#define DEF_DAT_UART_LSR() (REG32(ADR_DAT_UART_LSR)) = (0x00000000)
+#define DEF_DAT_UART_MSR() (REG32(ADR_DAT_UART_MSR)) = (0x00000000)
+#define DEF_DAT_UART_SPR() (REG32(ADR_DAT_UART_SPR)) = (0x00000000)
+#define DEF_DAT_UART_RTHR() (REG32(ADR_DAT_UART_RTHR)) = (0x000000c8)
+#define DEF_DAT_UART_ISR() (REG32(ADR_DAT_UART_ISR)) = (0x000000c1)
+#define DEF_INT_MASK() (REG32(ADR_INT_MASK)) = (0xffffffff)
+#define DEF_INT_MODE() (REG32(ADR_INT_MODE)) = (0x00000000)
+#define DEF_INT_IRQ_STS() (REG32(ADR_INT_IRQ_STS)) = (0x00000000)
+#define DEF_INT_FIQ_STS() (REG32(ADR_INT_FIQ_STS)) = (0x00000000)
+#define DEF_INT_IRQ_RAW() (REG32(ADR_INT_IRQ_RAW)) = (0x00000000)
+#define DEF_INT_FIQ_RAW() (REG32(ADR_INT_FIQ_RAW)) = (0x00000000)
+#define DEF_INT_PERI_MASK() (REG32(ADR_INT_PERI_MASK)) = (0xffffffff)
+#define DEF_INT_PERI_STS() (REG32(ADR_INT_PERI_STS)) = (0x00000000)
+#define DEF_INT_PERI_RAW() (REG32(ADR_INT_PERI_RAW)) = (0x00000000)
+#define DEF_INT_GPI_CFG() (REG32(ADR_INT_GPI_CFG)) = (0x00000000)
+#define DEF_SYS_INT_FOR_HOST() (REG32(ADR_SYS_INT_FOR_HOST)) = (0x00000001)
+#define DEF_SPI_IPC() (REG32(ADR_SPI_IPC)) = (0x00000000)
+#define DEF_SDIO_IPC() (REG32(ADR_SDIO_IPC)) = (0x00000000)
+#define DEF_SDIO_MASK() (REG32(ADR_SDIO_MASK)) = (0xffffffff)
+#define DEF_SDIO_IRQ_STS() (REG32(ADR_SDIO_IRQ_STS)) = (0x00000000)
+#define DEF_SD_PERI_MASK() (REG32(ADR_SD_PERI_MASK)) = (0xffffffff)
+#define DEF_SD_PERI_STS() (REG32(ADR_SD_PERI_STS)) = (0x00000000)
+#define DEF_DBG_SPI_MODE() (REG32(ADR_DBG_SPI_MODE)) = (0x00000000)
+#define DEF_DBG_RX_QUOTA() (REG32(ADR_DBG_RX_QUOTA)) = (0x00000000)
+#define DEF_DBG_CONDITION_NUMBER() (REG32(ADR_DBG_CONDITION_NUMBER)) = (0x00000004)
+#define DEF_DBG_HOST_PATH() (REG32(ADR_DBG_HOST_PATH)) = (0x00000001)
+#define DEF_DBG_TX_SEG() (REG32(ADR_DBG_TX_SEG)) = (0x00000000)
+#define DEF_DBG_DEBUG_BURST_MODE() (REG32(ADR_DBG_DEBUG_BURST_MODE)) = (0x00000000)
+#define DEF_DBG_SPI_TO_PHY_PARAM1() (REG32(ADR_DBG_SPI_TO_PHY_PARAM1)) = (0x000e0006)
+#define DEF_DBG_SPI_TO_PHY_PARAM2() (REG32(ADR_DBG_SPI_TO_PHY_PARAM2)) = (0x000e000e)
+#define DEF_DBG_SPI_STS() (REG32(ADR_DBG_SPI_STS)) = (0x00000000)
+#define DEF_DBG_TX_ALLOC_SET() (REG32(ADR_DBG_TX_ALLOC_SET)) = (0x00000000)
+#define DEF_DBG_TX_ALLOC() (REG32(ADR_DBG_TX_ALLOC)) = (0x00000000)
+#define DEF_DBG_DBG_CNT() (REG32(ADR_DBG_DBG_CNT)) = (0x00000000)
+#define DEF_DBG_DBG_CNT2() (REG32(ADR_DBG_DBG_CNT2)) = (0x00000000)
+#define DEF_DBG_DBG_CNT3() (REG32(ADR_DBG_DBG_CNT3)) = (0x00000000)
+#define DEF_DBG_DBG_CNT4() (REG32(ADR_DBG_DBG_CNT4)) = (0x00000000)
+#define DEF_DBG_INT_TAG() (REG32(ADR_DBG_INT_TAG)) = (0x00000000)
+#define DEF_BOOT_ADDR() (REG32(ADR_BOOT_ADDR)) = (0x00000000)
+#define DEF_VERIFY_DATA() (REG32(ADR_VERIFY_DATA)) = (0x5e11aa11)
+#define DEF_FLASH_ADDR() (REG32(ADR_FLASH_ADDR)) = (0x00000000)
+#define DEF_SRAM_ADDR() (REG32(ADR_SRAM_ADDR)) = (0x00000000)
+#define DEF_LEN() (REG32(ADR_LEN)) = (0x00000000)
+#define DEF_SPI_PARAM() (REG32(ADR_SPI_PARAM)) = (0x000f000f)
+#define DEF_SPI_PARAM2() (REG32(ADR_SPI_PARAM2)) = (0x00040001)
+#define DEF_CHECK_SUM_RESULT() (REG32(ADR_CHECK_SUM_RESULT)) = (0x00000000)
+#define DEF_CHECK_SUM_IN_FILE() (REG32(ADR_CHECK_SUM_IN_FILE)) = (0x00000000)
+#define DEF_COMMAND_LEN() (REG32(ADR_COMMAND_LEN)) = (0x00000000)
+#define DEF_COMMAND_ADDR() (REG32(ADR_COMMAND_ADDR)) = (0x00000000)
+#define DEF_DMA_ADR_SRC() (REG32(ADR_DMA_ADR_SRC)) = (0x00000000)
+#define DEF_DMA_ADR_DST() (REG32(ADR_DMA_ADR_DST)) = (0x00000000)
+#define DEF_DMA_CTRL() (REG32(ADR_DMA_CTRL)) = (0x000000aa)
+#define DEF_DMA_INT() (REG32(ADR_DMA_INT)) = (0x00000001)
+#define DEF_DMA_FILL_CONST() (REG32(ADR_DMA_FILL_CONST)) = (0x00000000)
+#define DEF_PMU_0() (REG32(ADR_PMU_0)) = (0x0f000040)
+#define DEF_PMU_1() (REG32(ADR_PMU_1)) = (0x015d015d)
+#define DEF_PMU_2() (REG32(ADR_PMU_2)) = (0x00000000)
+#define DEF_PMU_3() (REG32(ADR_PMU_3)) = (0x55550000)
+#define DEF_RTC_1() (REG32(ADR_RTC_1)) = (0x7fff0000)
+#define DEF_RTC_2() (REG32(ADR_RTC_2)) = (0x00000003)
+#define DEF_RTC_3W() (REG32(ADR_RTC_3W)) = (0x00000000)
+#define DEF_RTC_3R() (REG32(ADR_RTC_3R)) = (0x00000000)
+#define DEF_RTC_4() (REG32(ADR_RTC_4)) = (0x00000000)
+#define DEF_D2_DMA_ADR_SRC() (REG32(ADR_D2_DMA_ADR_SRC)) = (0x00000000)
+#define DEF_D2_DMA_ADR_DST() (REG32(ADR_D2_DMA_ADR_DST)) = (0x00000000)
+#define DEF_D2_DMA_CTRL() (REG32(ADR_D2_DMA_CTRL)) = (0x000000aa)
+#define DEF_D2_DMA_INT() (REG32(ADR_D2_DMA_INT)) = (0x00000001)
+#define DEF_D2_DMA_FILL_CONST() (REG32(ADR_D2_DMA_FILL_CONST)) = (0x00000000)
+#define DEF_CONTROL() (REG32(ADR_CONTROL)) = (0x02700008)
+#define DEF_SDIO_WAKE_MODE() (REG32(ADR_SDIO_WAKE_MODE)) = (0x00000000)
+#define DEF_TX_FLOW_0() (REG32(ADR_TX_FLOW_0)) = (0x00000000)
+#define DEF_TX_FLOW_1() (REG32(ADR_TX_FLOW_1)) = (0x00000000)
+#define DEF_THREASHOLD() (REG32(ADR_THREASHOLD)) = (0x09000000)
+#define DEF_TXFID_INCREASE() (REG32(ADR_TXFID_INCREASE)) = (0x00000000)
+#define DEF_GLOBAL_SEQUENCE() (REG32(ADR_GLOBAL_SEQUENCE)) = (0x00000000)
+#define DEF_HCI_TX_RX_INFO_SIZE() (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (0x00040450)
+#define DEF_HCI_TX_INFO_CLEAR() (REG32(ADR_HCI_TX_INFO_CLEAR)) = (0x00000008)
+#define DEF_TX_ETHER_TYPE_0() (REG32(ADR_TX_ETHER_TYPE_0)) = (0x00000000)
+#define DEF_TX_ETHER_TYPE_1() (REG32(ADR_TX_ETHER_TYPE_1)) = (0x00000000)
+#define DEF_RX_ETHER_TYPE_0() (REG32(ADR_RX_ETHER_TYPE_0)) = (0x00000000)
+#define DEF_RX_ETHER_TYPE_1() (REG32(ADR_RX_ETHER_TYPE_1)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_0() (REG32(ADR_PACKET_COUNTER_INFO_0)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_1() (REG32(ADR_PACKET_COUNTER_INFO_1)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_2() (REG32(ADR_PACKET_COUNTER_INFO_2)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_3() (REG32(ADR_PACKET_COUNTER_INFO_3)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_4() (REG32(ADR_PACKET_COUNTER_INFO_4)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_5() (REG32(ADR_PACKET_COUNTER_INFO_5)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_6() (REG32(ADR_PACKET_COUNTER_INFO_6)) = (0x00000000)
+#define DEF_PACKET_COUNTER_INFO_7() (REG32(ADR_PACKET_COUNTER_INFO_7)) = (0x00000000)
+#define DEF_SDIO_TX_RX_FAIL_COUNTER_0() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_0)) = (0x00000000)
+#define DEF_SDIO_TX_RX_FAIL_COUNTER_1() (REG32(ADR_SDIO_TX_RX_FAIL_COUNTER_1)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_0() (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_1() (REG32(ADR_HCI_STATE_DEBUG_MODE_1)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_2() (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_3() (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_4() (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_5() (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_6() (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_7() (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_8() (REG32(ADR_HCI_STATE_DEBUG_MODE_8)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_9() (REG32(ADR_HCI_STATE_DEBUG_MODE_9)) = (0x00000000)
+#define DEF_HCI_STATE_DEBUG_MODE_10() (REG32(ADR_HCI_STATE_DEBUG_MODE_10)) = (0x00000000)
+#define DEF_CS_START_ADDR() (REG32(ADR_CS_START_ADDR)) = (0x00000000)
+#define DEF_CS_ADD_LEN() (REG32(ADR_CS_ADD_LEN)) = (0x00000000)
+#define DEF_CS_CMD() (REG32(ADR_CS_CMD)) = (0x00000000)
+#define DEF_CS_INI_BUF() (REG32(ADR_CS_INI_BUF)) = (0x00000000)
+#define DEF_CS_PSEUDO_BUF() (REG32(ADR_CS_PSEUDO_BUF)) = (0x00000000)
+#define DEF_CS_CHECK_SUM() (REG32(ADR_CS_CHECK_SUM)) = (0x00000000)
+#define DEF_RAND_EN() (REG32(ADR_RAND_EN)) = (0x00000000)
+#define DEF_RAND_NUM() (REG32(ADR_RAND_NUM)) = (0x00000000)
+#define DEF_MUL_OP1() (REG32(ADR_MUL_OP1)) = (0x00000000)
+#define DEF_MUL_OP2() (REG32(ADR_MUL_OP2)) = (0x00000000)
+#define DEF_MUL_ANS0() (REG32(ADR_MUL_ANS0)) = (0x00000000)
+#define DEF_MUL_ANS1() (REG32(ADR_MUL_ANS1)) = (0x00000000)
+#define DEF_DMA_RDATA() (REG32(ADR_DMA_RDATA)) = (0x00000000)
+#define DEF_DMA_WDATA() (REG32(ADR_DMA_WDATA)) = (0x00000000)
+#define DEF_DMA_LEN() (REG32(ADR_DMA_LEN)) = (0x00000000)
+#define DEF_DMA_CLR() (REG32(ADR_DMA_CLR)) = (0x00000000)
+#define DEF_NAV_DATA() (REG32(ADR_NAV_DATA)) = (0x00000000)
+#define DEF_CO_NAV() (REG32(ADR_CO_NAV)) = (0x00000000)
+#define DEF_SHA_DST_ADDR() (REG32(ADR_SHA_DST_ADDR)) = (0x00000000)
+#define DEF_SHA_SRC_ADDR() (REG32(ADR_SHA_SRC_ADDR)) = (0x00000000)
+#define DEF_SHA_SETTING() (REG32(ADR_SHA_SETTING)) = (0x00000002)
+#define DEF_EFUSE_CLK_FREQ() (REG32(ADR_EFUSE_CLK_FREQ)) = (0x610100d0)
+#define DEF_EFUSE_LDO_TIME() (REG32(ADR_EFUSE_LDO_TIME)) = (0x00020002)
+#define DEF_EFUSE_AHB_RDATA_0() (REG32(ADR_EFUSE_AHB_RDATA_0)) = (0x00000000)
+#define DEF_EFUSE_WDATA_0() (REG32(ADR_EFUSE_WDATA_0)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_1() (REG32(ADR_EFUSE_AHB_RDATA_1)) = (0x00000000)
+#define DEF_EFUSE_WDATA_1() (REG32(ADR_EFUSE_WDATA_1)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_2() (REG32(ADR_EFUSE_AHB_RDATA_2)) = (0x00000000)
+#define DEF_EFUSE_WDATA_2() (REG32(ADR_EFUSE_WDATA_2)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_3() (REG32(ADR_EFUSE_AHB_RDATA_3)) = (0x00000000)
+#define DEF_EFUSE_WDATA_3() (REG32(ADR_EFUSE_WDATA_3)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_4() (REG32(ADR_EFUSE_AHB_RDATA_4)) = (0x00000000)
+#define DEF_EFUSE_WDATA_4() (REG32(ADR_EFUSE_WDATA_4)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_5() (REG32(ADR_EFUSE_AHB_RDATA_5)) = (0x00000000)
+#define DEF_EFUSE_WDATA_5() (REG32(ADR_EFUSE_WDATA_5)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_6() (REG32(ADR_EFUSE_AHB_RDATA_6)) = (0x00000000)
+#define DEF_EFUSE_WDATA_6() (REG32(ADR_EFUSE_WDATA_6)) = (0x00000000)
+#define DEF_EFUSE_AHB_RDATA_7() (REG32(ADR_EFUSE_AHB_RDATA_7)) = (0x00000000)
+#define DEF_EFUSE_WDATA_7() (REG32(ADR_EFUSE_WDATA_7)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD0_EN() (REG32(ADR_EFUSE_SPI_RD0_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD1_EN() (REG32(ADR_EFUSE_SPI_RD1_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD2_EN() (REG32(ADR_EFUSE_SPI_RD2_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD3_EN() (REG32(ADR_EFUSE_SPI_RD3_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD4_EN() (REG32(ADR_EFUSE_SPI_RD4_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD5_EN() (REG32(ADR_EFUSE_SPI_RD5_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD6_EN() (REG32(ADR_EFUSE_SPI_RD6_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_RD7_EN() (REG32(ADR_EFUSE_SPI_RD7_EN)) = (0x00000000)
+#define DEF_EFUSE_SPI_BUSY() (REG32(ADR_EFUSE_SPI_BUSY)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_0() (REG32(ADR_EFUSE_SPI_RDATA_0)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_1() (REG32(ADR_EFUSE_SPI_RDATA_1)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_2() (REG32(ADR_EFUSE_SPI_RDATA_2)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_3() (REG32(ADR_EFUSE_SPI_RDATA_3)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_4() (REG32(ADR_EFUSE_SPI_RDATA_4)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_5() (REG32(ADR_EFUSE_SPI_RDATA_5)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_6() (REG32(ADR_EFUSE_SPI_RDATA_6)) = (0x00000000)
+#define DEF_EFUSE_SPI_RDATA_7() (REG32(ADR_EFUSE_SPI_RDATA_7)) = (0x00000000)
+#define DEF_SMS4_CFG1() (REG32(ADR_SMS4_CFG1)) = (0x00000002)
+#define DEF_SMS4_CFG2() (REG32(ADR_SMS4_CFG2)) = (0x00000000)
+#define DEF_SMS4_MODE1() (REG32(ADR_SMS4_MODE1)) = (0x00000000)
+#define DEF_SMS4_TRIG() (REG32(ADR_SMS4_TRIG)) = (0x00000000)
+#define DEF_SMS4_STATUS1() (REG32(ADR_SMS4_STATUS1)) = (0x00000000)
+#define DEF_SMS4_STATUS2() (REG32(ADR_SMS4_STATUS2)) = (0x00000000)
+#define DEF_SMS4_DATA_IN0() (REG32(ADR_SMS4_DATA_IN0)) = (0x00000000)
+#define DEF_SMS4_DATA_IN1() (REG32(ADR_SMS4_DATA_IN1)) = (0x00000000)
+#define DEF_SMS4_DATA_IN2() (REG32(ADR_SMS4_DATA_IN2)) = (0x00000000)
+#define DEF_SMS4_DATA_IN3() (REG32(ADR_SMS4_DATA_IN3)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT0() (REG32(ADR_SMS4_DATA_OUT0)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT1() (REG32(ADR_SMS4_DATA_OUT1)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT2() (REG32(ADR_SMS4_DATA_OUT2)) = (0x00000000)
+#define DEF_SMS4_DATA_OUT3() (REG32(ADR_SMS4_DATA_OUT3)) = (0x00000000)
+#define DEF_SMS4_KEY_0() (REG32(ADR_SMS4_KEY_0)) = (0x00000000)
+#define DEF_SMS4_KEY_1() (REG32(ADR_SMS4_KEY_1)) = (0x00000000)
+#define DEF_SMS4_KEY_2() (REG32(ADR_SMS4_KEY_2)) = (0x00000000)
+#define DEF_SMS4_KEY_3() (REG32(ADR_SMS4_KEY_3)) = (0x00000000)
+#define DEF_SMS4_MODE_IV0() (REG32(ADR_SMS4_MODE_IV0)) = (0x00000000)
+#define DEF_SMS4_MODE_IV1() (REG32(ADR_SMS4_MODE_IV1)) = (0x00000000)
+#define DEF_SMS4_MODE_IV2() (REG32(ADR_SMS4_MODE_IV2)) = (0x00000000)
+#define DEF_SMS4_MODE_IV3() (REG32(ADR_SMS4_MODE_IV3)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC0() (REG32(ADR_SMS4_OFB_ENC0)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC1() (REG32(ADR_SMS4_OFB_ENC1)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC2() (REG32(ADR_SMS4_OFB_ENC2)) = (0x00000000)
+#define DEF_SMS4_OFB_ENC3() (REG32(ADR_SMS4_OFB_ENC3)) = (0x00000000)
+#define DEF_MRX_MCAST_TB0_0() (REG32(ADR_MRX_MCAST_TB0_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB0_1() (REG32(ADR_MRX_MCAST_TB0_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK0_0() (REG32(ADR_MRX_MCAST_MK0_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK0_1() (REG32(ADR_MRX_MCAST_MK0_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL0() (REG32(ADR_MRX_MCAST_CTRL0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB1_0() (REG32(ADR_MRX_MCAST_TB1_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB1_1() (REG32(ADR_MRX_MCAST_TB1_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK1_0() (REG32(ADR_MRX_MCAST_MK1_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK1_1() (REG32(ADR_MRX_MCAST_MK1_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL1() (REG32(ADR_MRX_MCAST_CTRL1)) = (0x00000000)
+#define DEF_MRX_MCAST_TB2_0() (REG32(ADR_MRX_MCAST_TB2_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB2_1() (REG32(ADR_MRX_MCAST_TB2_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK2_0() (REG32(ADR_MRX_MCAST_MK2_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK2_1() (REG32(ADR_MRX_MCAST_MK2_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL2() (REG32(ADR_MRX_MCAST_CTRL2)) = (0x00000000)
+#define DEF_MRX_MCAST_TB3_0() (REG32(ADR_MRX_MCAST_TB3_0)) = (0x00000000)
+#define DEF_MRX_MCAST_TB3_1() (REG32(ADR_MRX_MCAST_TB3_1)) = (0x00000000)
+#define DEF_MRX_MCAST_MK3_0() (REG32(ADR_MRX_MCAST_MK3_0)) = (0x00000000)
+#define DEF_MRX_MCAST_MK3_1() (REG32(ADR_MRX_MCAST_MK3_1)) = (0x00000000)
+#define DEF_MRX_MCAST_CTRL3() (REG32(ADR_MRX_MCAST_CTRL3)) = (0x00000000)
+#define DEF_MRX_PHY_INFO() (REG32(ADR_MRX_PHY_INFO)) = (0x00000000)
+#define DEF_MRX_BA_DBG() (REG32(ADR_MRX_BA_DBG)) = (0x00000000)
+#define DEF_MRX_FLT_TB0() (REG32(ADR_MRX_FLT_TB0)) = (0x00003df5)
+#define DEF_MRX_FLT_TB1() (REG32(ADR_MRX_FLT_TB1)) = (0x000031f6)
+#define DEF_MRX_FLT_TB2() (REG32(ADR_MRX_FLT_TB2)) = (0x000035f9)
+#define DEF_MRX_FLT_TB3() (REG32(ADR_MRX_FLT_TB3)) = (0x000021c1)
+#define DEF_MRX_FLT_TB4() (REG32(ADR_MRX_FLT_TB4)) = (0x00004bf9)
+#define DEF_MRX_FLT_TB5() (REG32(ADR_MRX_FLT_TB5)) = (0x00004db1)
+#define DEF_MRX_FLT_TB6() (REG32(ADR_MRX_FLT_TB6)) = (0x000011fe)
+#define DEF_MRX_FLT_TB7() (REG32(ADR_MRX_FLT_TB7)) = (0x00000bfe)
+#define DEF_MRX_FLT_TB8() (REG32(ADR_MRX_FLT_TB8)) = (0x00000000)
+#define DEF_MRX_FLT_TB9() (REG32(ADR_MRX_FLT_TB9)) = (0x00000000)
+#define DEF_MRX_FLT_TB10() (REG32(ADR_MRX_FLT_TB10)) = (0x00000000)
+#define DEF_MRX_FLT_TB11() (REG32(ADR_MRX_FLT_TB11)) = (0x00000006)
+#define DEF_MRX_FLT_TB12() (REG32(ADR_MRX_FLT_TB12)) = (0x00000001)
+#define DEF_MRX_FLT_TB13() (REG32(ADR_MRX_FLT_TB13)) = (0x00000003)
+#define DEF_MRX_FLT_TB14() (REG32(ADR_MRX_FLT_TB14)) = (0x00000005)
+#define DEF_MRX_FLT_TB15() (REG32(ADR_MRX_FLT_TB15)) = (0x00000007)
+#define DEF_MRX_FLT_EN0() (REG32(ADR_MRX_FLT_EN0)) = (0x00002008)
+#define DEF_MRX_FLT_EN1() (REG32(ADR_MRX_FLT_EN1)) = (0x00001001)
+#define DEF_MRX_FLT_EN2() (REG32(ADR_MRX_FLT_EN2)) = (0x00000808)
+#define DEF_MRX_FLT_EN3() (REG32(ADR_MRX_FLT_EN3)) = (0x00001000)
+#define DEF_MRX_FLT_EN4() (REG32(ADR_MRX_FLT_EN4)) = (0x00002008)
+#define DEF_MRX_FLT_EN5() (REG32(ADR_MRX_FLT_EN5)) = (0x0000800e)
+#define DEF_MRX_FLT_EN6() (REG32(ADR_MRX_FLT_EN6)) = (0x00000838)
+#define DEF_MRX_FLT_EN7() (REG32(ADR_MRX_FLT_EN7)) = (0x00002008)
+#define DEF_MRX_FLT_EN8() (REG32(ADR_MRX_FLT_EN8)) = (0x00002008)
+#define DEF_MRX_LEN_FLT() (REG32(ADR_MRX_LEN_FLT)) = (0x00000000)
+#define DEF_RX_FLOW_DATA() (REG32(ADR_RX_FLOW_DATA)) = (0x00105034)
+#define DEF_RX_FLOW_MNG() (REG32(ADR_RX_FLOW_MNG)) = (0x00000004)
+#define DEF_RX_FLOW_CTRL() (REG32(ADR_RX_FLOW_CTRL)) = (0x00000004)
+#define DEF_RX_TIME_STAMP_CFG() (REG32(ADR_RX_TIME_STAMP_CFG)) = (0x00001c00)
+#define DEF_DBG_FF_FULL() (REG32(ADR_DBG_FF_FULL)) = (0x00000000)
+#define DEF_DBG_WFF_FULL() (REG32(ADR_DBG_WFF_FULL)) = (0x00000000)
+#define DEF_DBG_MB_FULL() (REG32(ADR_DBG_MB_FULL)) = (0x00000000)
+#define DEF_BA_CTRL() (REG32(ADR_BA_CTRL)) = (0x00000008)
+#define DEF_BA_TA_0() (REG32(ADR_BA_TA_0)) = (0x00000000)
+#define DEF_BA_TA_1() (REG32(ADR_BA_TA_1)) = (0x00000000)
+#define DEF_BA_TID() (REG32(ADR_BA_TID)) = (0x00000000)
+#define DEF_BA_ST_SEQ() (REG32(ADR_BA_ST_SEQ)) = (0x00000000)
+#define DEF_BA_SB0() (REG32(ADR_BA_SB0)) = (0x00000000)
+#define DEF_BA_SB1() (REG32(ADR_BA_SB1)) = (0x00000000)
+#define DEF_MRX_WATCH_DOG() (REG32(ADR_MRX_WATCH_DOG)) = (0x0000ffff)
+#define DEF_ACK_GEN_EN() (REG32(ADR_ACK_GEN_EN)) = (0x00000000)
+#define DEF_ACK_GEN_PARA() (REG32(ADR_ACK_GEN_PARA)) = (0x00000000)
+#define DEF_ACK_GEN_RA_0() (REG32(ADR_ACK_GEN_RA_0)) = (0x00000000)
+#define DEF_ACK_GEN_RA_1() (REG32(ADR_ACK_GEN_RA_1)) = (0x00000000)
+#define DEF_MIB_LEN_FAIL() (REG32(ADR_MIB_LEN_FAIL)) = (0x00000000)
+#define DEF_TRAP_HW_ID() (REG32(ADR_TRAP_HW_ID)) = (0x00000000)
+#define DEF_ID_IN_USE() (REG32(ADR_ID_IN_USE)) = (0x00000000)
+#define DEF_MRX_ERR() (REG32(ADR_MRX_ERR)) = (0x00000000)
+#define DEF_WSID0_TID0_RX_SEQ() (REG32(ADR_WSID0_TID0_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID1_RX_SEQ() (REG32(ADR_WSID0_TID1_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID2_RX_SEQ() (REG32(ADR_WSID0_TID2_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID3_RX_SEQ() (REG32(ADR_WSID0_TID3_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID4_RX_SEQ() (REG32(ADR_WSID0_TID4_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID5_RX_SEQ() (REG32(ADR_WSID0_TID5_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID6_RX_SEQ() (REG32(ADR_WSID0_TID6_RX_SEQ)) = (0x00000000)
+#define DEF_WSID0_TID7_RX_SEQ() (REG32(ADR_WSID0_TID7_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID0_RX_SEQ() (REG32(ADR_WSID1_TID0_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID1_RX_SEQ() (REG32(ADR_WSID1_TID1_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID2_RX_SEQ() (REG32(ADR_WSID1_TID2_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID3_RX_SEQ() (REG32(ADR_WSID1_TID3_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID4_RX_SEQ() (REG32(ADR_WSID1_TID4_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID5_RX_SEQ() (REG32(ADR_WSID1_TID5_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID6_RX_SEQ() (REG32(ADR_WSID1_TID6_RX_SEQ)) = (0x00000000)
+#define DEF_WSID1_TID7_RX_SEQ() (REG32(ADR_WSID1_TID7_RX_SEQ)) = (0x00000000)
+#define DEF_HDR_ADDR_SEL() (REG32(ADR_HDR_ADDR_SEL)) = (0x00003e79)
+#define DEF_FRAME_TYPE_CNTR_SET() (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (0x00000000)
+#define DEF_PHY_INFO() (REG32(ADR_PHY_INFO)) = (0x00000000)
+#define DEF_AMPDU_SIG() (REG32(ADR_AMPDU_SIG)) = (0x0000004e)
+#define DEF_MIB_AMPDU() (REG32(ADR_MIB_AMPDU)) = (0x00000000)
+#define DEF_LEN_FLT() (REG32(ADR_LEN_FLT)) = (0x00000000)
+#define DEF_MIB_DELIMITER() (REG32(ADR_MIB_DELIMITER)) = (0x00000000)
+#define DEF_MTX_INT_STS() (REG32(ADR_MTX_INT_STS)) = (0x00000000)
+#define DEF_MTX_INT_EN() (REG32(ADR_MTX_INT_EN)) = (0x00000000)
+#define DEF_MTX_MISC_EN() (REG32(ADR_MTX_MISC_EN)) = (0x00c00c00)
+#define DEF_MTX_EDCCA_TOUT() (REG32(ADR_MTX_EDCCA_TOUT)) = (0x00000200)
+#define DEF_MTX_BCN_INT_STS() (REG32(ADR_MTX_BCN_INT_STS)) = (0x00000000)
+#define DEF_MTX_BCN_EN_INT() (REG32(ADR_MTX_BCN_EN_INT)) = (0x00000000)
+#define DEF_MTX_BCN_EN_MISC() (REG32(ADR_MTX_BCN_EN_MISC)) = (0x00000042)
+#define DEF_MTX_BCN_MISC() (REG32(ADR_MTX_BCN_MISC)) = (0x00000000)
+#define DEF_MTX_BCN_PRD() (REG32(ADR_MTX_BCN_PRD)) = (0x00000064)
+#define DEF_MTX_BCN_TSF_L() (REG32(ADR_MTX_BCN_TSF_L)) = (0x00000000)
+#define DEF_MTX_BCN_TSF_U() (REG32(ADR_MTX_BCN_TSF_U)) = (0x00000000)
+#define DEF_MTX_BCN_CFG0() (REG32(ADR_MTX_BCN_CFG0)) = (0x00000000)
+#define DEF_MTX_BCN_CFG1() (REG32(ADR_MTX_BCN_CFG1)) = (0x00000000)
+#define DEF_MTX_STATUS() (REG32(ADR_MTX_STATUS)) = (0x00000000)
+#define DEF_MTX_DBG_CTRL() (REG32(ADR_MTX_DBG_CTRL)) = (0x00000000)
+#define DEF_MTX_DBG_DAT0() (REG32(ADR_MTX_DBG_DAT0)) = (0x00000000)
+#define DEF_MTX_DBG_DAT1() (REG32(ADR_MTX_DBG_DAT1)) = (0x00000000)
+#define DEF_MTX_DBG_DAT2() (REG32(ADR_MTX_DBG_DAT2)) = (0x00000000)
+#define DEF_MTX_DUR_TOUT() (REG32(ADR_MTX_DUR_TOUT)) = (0x00002c2c)
+#define DEF_MTX_DUR_IFS() (REG32(ADR_MTX_DUR_IFS)) = (0x12d40a05)
+#define DEF_MTX_DUR_SIFS_G() (REG32(ADR_MTX_DUR_SIFS_G)) = (0x12c90100)
+#define DEF_MTX_DBG_DAT3() (REG32(ADR_MTX_DBG_DAT3)) = (0x00000000)
+#define DEF_MTX_NAV() (REG32(ADR_MTX_NAV)) = (0x00000000)
+#define DEF_MTX_MIB_WSID0() (REG32(ADR_MTX_MIB_WSID0)) = (0x00000000)
+#define DEF_MTX_MIB_WSID1() (REG32(ADR_MTX_MIB_WSID1)) = (0x00000000)
+#define DEF_MTX_DBG_DAT4() (REG32(ADR_MTX_DBG_DAT4)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_MISC_EN() (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_AIFSN() (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ0_MTX_Q_BKF_CNT() (REG32(ADR_TXQ0_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ0_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ0_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ0_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ0_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ0_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_MISC_EN() (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_AIFSN() (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ1_MTX_Q_BKF_CNT() (REG32(ADR_TXQ1_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ1_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ1_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ1_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ1_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ1_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_MISC_EN() (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_AIFSN() (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ2_MTX_Q_BKF_CNT() (REG32(ADR_TXQ2_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ2_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ2_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ2_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ2_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ2_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_MISC_EN() (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_AIFSN() (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ3_MTX_Q_BKF_CNT() (REG32(ADR_TXQ3_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ3_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ3_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ3_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ3_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ3_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_MISC_EN() (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_AIFSN() (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (0x0000a502)
+#define DEF_TXQ4_MTX_Q_BKF_CNT() (REG32(ADR_TXQ4_MTX_Q_BKF_CNT)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_RC_LIMIT() (REG32(ADR_TXQ4_MTX_Q_RC_LIMIT)) = (0x00000407)
+#define DEF_TXQ4_MTX_Q_ID_MAP_L() (REG32(ADR_TXQ4_MTX_Q_ID_MAP_L)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_TXOP_CH_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_CH_THD)) = (0x00000000)
+#define DEF_TXQ4_MTX_Q_TXOP_OV_THD() (REG32(ADR_TXQ4_MTX_Q_TXOP_OV_THD)) = (0x00000000)
+#define DEF_WSID0() (REG32(ADR_WSID0)) = (0x00000000)
+#define DEF_PEER_MAC0_0() (REG32(ADR_PEER_MAC0_0)) = (0x00000000)
+#define DEF_PEER_MAC0_1() (REG32(ADR_PEER_MAC0_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_0() (REG32(ADR_TX_ACK_POLICY_0_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_0() (REG32(ADR_TX_SEQ_CTRL_0_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_1() (REG32(ADR_TX_ACK_POLICY_0_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_1() (REG32(ADR_TX_SEQ_CTRL_0_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_2() (REG32(ADR_TX_ACK_POLICY_0_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_2() (REG32(ADR_TX_SEQ_CTRL_0_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_3() (REG32(ADR_TX_ACK_POLICY_0_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_3() (REG32(ADR_TX_SEQ_CTRL_0_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_4() (REG32(ADR_TX_ACK_POLICY_0_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_4() (REG32(ADR_TX_SEQ_CTRL_0_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_5() (REG32(ADR_TX_ACK_POLICY_0_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_5() (REG32(ADR_TX_SEQ_CTRL_0_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_6() (REG32(ADR_TX_ACK_POLICY_0_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_6() (REG32(ADR_TX_SEQ_CTRL_0_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_0_7() (REG32(ADR_TX_ACK_POLICY_0_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_0_7() (REG32(ADR_TX_SEQ_CTRL_0_7)) = (0x00000000)
+#define DEF_WSID1() (REG32(ADR_WSID1)) = (0x00000000)
+#define DEF_PEER_MAC1_0() (REG32(ADR_PEER_MAC1_0)) = (0x00000000)
+#define DEF_PEER_MAC1_1() (REG32(ADR_PEER_MAC1_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_0() (REG32(ADR_TX_ACK_POLICY_1_0)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_0() (REG32(ADR_TX_SEQ_CTRL_1_0)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_1() (REG32(ADR_TX_ACK_POLICY_1_1)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_1() (REG32(ADR_TX_SEQ_CTRL_1_1)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_2() (REG32(ADR_TX_ACK_POLICY_1_2)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_2() (REG32(ADR_TX_SEQ_CTRL_1_2)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_3() (REG32(ADR_TX_ACK_POLICY_1_3)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_3() (REG32(ADR_TX_SEQ_CTRL_1_3)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_4() (REG32(ADR_TX_ACK_POLICY_1_4)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_4() (REG32(ADR_TX_SEQ_CTRL_1_4)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_5() (REG32(ADR_TX_ACK_POLICY_1_5)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_5() (REG32(ADR_TX_SEQ_CTRL_1_5)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_6() (REG32(ADR_TX_ACK_POLICY_1_6)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_6() (REG32(ADR_TX_SEQ_CTRL_1_6)) = (0x00000000)
+#define DEF_TX_ACK_POLICY_1_7() (REG32(ADR_TX_ACK_POLICY_1_7)) = (0x00000000)
+#define DEF_TX_SEQ_CTRL_1_7() (REG32(ADR_TX_SEQ_CTRL_1_7)) = (0x00000000)
+#define DEF_INFO0() (REG32(ADR_INFO0)) = (0x00000000)
+#define DEF_INFO1() (REG32(ADR_INFO1)) = (0x00000100)
+#define DEF_INFO2() (REG32(ADR_INFO2)) = (0x00000200)
+#define DEF_INFO3() (REG32(ADR_INFO3)) = (0x00000300)
+#define DEF_INFO4() (REG32(ADR_INFO4)) = (0x00000140)
+#define DEF_INFO5() (REG32(ADR_INFO5)) = (0x00000240)
+#define DEF_INFO6() (REG32(ADR_INFO6)) = (0x00000340)
+#define DEF_INFO7() (REG32(ADR_INFO7)) = (0x00000001)
+#define DEF_INFO8() (REG32(ADR_INFO8)) = (0x00000101)
+#define DEF_INFO9() (REG32(ADR_INFO9)) = (0x00000201)
+#define DEF_INFO10() (REG32(ADR_INFO10)) = (0x00000301)
+#define DEF_INFO11() (REG32(ADR_INFO11)) = (0x00000401)
+#define DEF_INFO12() (REG32(ADR_INFO12)) = (0x00000501)
+#define DEF_INFO13() (REG32(ADR_INFO13)) = (0x00000601)
+#define DEF_INFO14() (REG32(ADR_INFO14)) = (0x00000701)
+#define DEF_INFO15() (REG32(ADR_INFO15)) = (0x00030002)
+#define DEF_INFO16() (REG32(ADR_INFO16)) = (0x00030102)
+#define DEF_INFO17() (REG32(ADR_INFO17)) = (0x00030202)
+#define DEF_INFO18() (REG32(ADR_INFO18)) = (0x00030302)
+#define DEF_INFO19() (REG32(ADR_INFO19)) = (0x00030402)
+#define DEF_INFO20() (REG32(ADR_INFO20)) = (0x00030502)
+#define DEF_INFO21() (REG32(ADR_INFO21)) = (0x00030602)
+#define DEF_INFO22() (REG32(ADR_INFO22)) = (0x00030702)
+#define DEF_INFO23() (REG32(ADR_INFO23)) = (0x00030082)
+#define DEF_INFO24() (REG32(ADR_INFO24)) = (0x00030182)
+#define DEF_INFO25() (REG32(ADR_INFO25)) = (0x00030282)
+#define DEF_INFO26() (REG32(ADR_INFO26)) = (0x00030382)
+#define DEF_INFO27() (REG32(ADR_INFO27)) = (0x00030482)
+#define DEF_INFO28() (REG32(ADR_INFO28)) = (0x00030582)
+#define DEF_INFO29() (REG32(ADR_INFO29)) = (0x00030682)
+#define DEF_INFO30() (REG32(ADR_INFO30)) = (0x00030782)
+#define DEF_INFO31() (REG32(ADR_INFO31)) = (0x00030042)
+#define DEF_INFO32() (REG32(ADR_INFO32)) = (0x00030142)
+#define DEF_INFO33() (REG32(ADR_INFO33)) = (0x00030242)
+#define DEF_INFO34() (REG32(ADR_INFO34)) = (0x00030342)
+#define DEF_INFO35() (REG32(ADR_INFO35)) = (0x00030442)
+#define DEF_INFO36() (REG32(ADR_INFO36)) = (0x00030542)
+#define DEF_INFO37() (REG32(ADR_INFO37)) = (0x00030642)
+#define DEF_INFO38() (REG32(ADR_INFO38)) = (0x00030742)
+#define DEF_INFO_MASK() (REG32(ADR_INFO_MASK)) = (0x00007fc7)
+#define DEF_INFO_RATE_OFFSET() (REG32(ADR_INFO_RATE_OFFSET)) = (0x00040000)
+#define DEF_INFO_IDX_ADDR() (REG32(ADR_INFO_IDX_ADDR)) = (0x00000000)
+#define DEF_INFO_LEN_ADDR() (REG32(ADR_INFO_LEN_ADDR)) = (0x00000000)
+#define DEF_IC_TIME_TAG_0() (REG32(ADR_IC_TIME_TAG_0)) = (0x00000000)
+#define DEF_IC_TIME_TAG_1() (REG32(ADR_IC_TIME_TAG_1)) = (0x00000000)
+#define DEF_PACKET_ID_ALLOCATION_PRIORITY() (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (0x00000000)
+#define DEF_MAC_MODE() (REG32(ADR_MAC_MODE)) = (0x00000000)
+#define DEF_ALL_SOFTWARE_RESET() (REG32(ADR_ALL_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_ENG_SOFTWARE_RESET() (REG32(ADR_ENG_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_CSR_SOFTWARE_RESET() (REG32(ADR_CSR_SOFTWARE_RESET)) = (0x00000000)
+#define DEF_MAC_CLOCK_ENABLE() (REG32(ADR_MAC_CLOCK_ENABLE)) = (0x00003efb)
+#define DEF_MAC_ENGINE_CLOCK_ENABLE() (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (0x0000f07b)
+#define DEF_MAC_CSR_CLOCK_ENABLE() (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (0x0000ec02)
+#define DEF_GLBLE_SET() (REG32(ADR_GLBLE_SET)) = (0x000e5000)
+#define DEF_REASON_TRAP0() (REG32(ADR_REASON_TRAP0)) = (0x00000000)
+#define DEF_REASON_TRAP1() (REG32(ADR_REASON_TRAP1)) = (0x00000000)
+#define DEF_BSSID_0() (REG32(ADR_BSSID_0)) = (0x00000000)
+#define DEF_BSSID_1() (REG32(ADR_BSSID_1)) = (0x00000000)
+#define DEF_SCRT_STATE() (REG32(ADR_SCRT_STATE)) = (0x00000000)
+#define DEF_STA_MAC_0() (REG32(ADR_STA_MAC_0)) = (0x00000000)
+#define DEF_STA_MAC_1() (REG32(ADR_STA_MAC_1)) = (0x00000000)
+#define DEF_SCRT_SET() (REG32(ADR_SCRT_SET)) = (0x00000000)
+#define DEF_BTCX0() (REG32(ADR_BTCX0)) = (0x00000006)
+#define DEF_BTCX1() (REG32(ADR_BTCX1)) = (0x00000000)
+#define DEF_SWITCH_CTL() (REG32(ADR_SWITCH_CTL)) = (0x00000000)
+#define DEF_MIB_EN() (REG32(ADR_MIB_EN)) = (0x00000000)
+#define DEF_MTX_WSID0_SUCC() (REG32(ADR_MTX_WSID0_SUCC)) = (0x00000000)
+#define DEF_MTX_WSID0_FRM() (REG32(ADR_MTX_WSID0_FRM)) = (0x00000000)
+#define DEF_MTX_WSID0_RETRY() (REG32(ADR_MTX_WSID0_RETRY)) = (0x00000000)
+#define DEF_MTX_WSID0_TOTAL() (REG32(ADR_MTX_WSID0_TOTAL)) = (0x00000000)
+#define DEF_MTX_GROUP() (REG32(ADR_MTX_GROUP)) = (0x00000000)
+#define DEF_MTX_FAIL() (REG32(ADR_MTX_FAIL)) = (0x00000000)
+#define DEF_MTX_RETRY() (REG32(ADR_MTX_RETRY)) = (0x00000000)
+#define DEF_MTX_MULTI_RETRY() (REG32(ADR_MTX_MULTI_RETRY)) = (0x00000000)
+#define DEF_MTX_RTS_SUCCESS() (REG32(ADR_MTX_RTS_SUCCESS)) = (0x00000000)
+#define DEF_MTX_RTS_FAIL() (REG32(ADR_MTX_RTS_FAIL)) = (0x00000000)
+#define DEF_MTX_ACK_FAIL() (REG32(ADR_MTX_ACK_FAIL)) = (0x00000000)
+#define DEF_MTX_FRM() (REG32(ADR_MTX_FRM)) = (0x00000000)
+#define DEF_MTX_ACK_TX() (REG32(ADR_MTX_ACK_TX)) = (0x00000000)
+#define DEF_MTX_CTS_TX() (REG32(ADR_MTX_CTS_TX)) = (0x00000000)
+#define DEF_MRX_DUP_FRM() (REG32(ADR_MRX_DUP_FRM)) = (0x00000000)
+#define DEF_MRX_FRG_FRM() (REG32(ADR_MRX_FRG_FRM)) = (0x00000000)
+#define DEF_MRX_GROUP_FRM() (REG32(ADR_MRX_GROUP_FRM)) = (0x00000000)
+#define DEF_MRX_FCS_ERR() (REG32(ADR_MRX_FCS_ERR)) = (0x00000000)
+#define DEF_MRX_FCS_SUCC() (REG32(ADR_MRX_FCS_SUCC)) = (0x00000000)
+#define DEF_MRX_MISS() (REG32(ADR_MRX_MISS)) = (0x00000000)
+#define DEF_MRX_ALC_FAIL() (REG32(ADR_MRX_ALC_FAIL)) = (0x00000000)
+#define DEF_MRX_DAT_NTF() (REG32(ADR_MRX_DAT_NTF)) = (0x00000000)
+#define DEF_MRX_RTS_NTF() (REG32(ADR_MRX_RTS_NTF)) = (0x00000000)
+#define DEF_MRX_CTS_NTF() (REG32(ADR_MRX_CTS_NTF)) = (0x00000000)
+#define DEF_MRX_ACK_NTF() (REG32(ADR_MRX_ACK_NTF)) = (0x00000000)
+#define DEF_MRX_BA_NTF() (REG32(ADR_MRX_BA_NTF)) = (0x00000000)
+#define DEF_MRX_DATA_NTF() (REG32(ADR_MRX_DATA_NTF)) = (0x00000000)
+#define DEF_MRX_MNG_NTF() (REG32(ADR_MRX_MNG_NTF)) = (0x00000000)
+#define DEF_MRX_DAT_CRC_NTF() (REG32(ADR_MRX_DAT_CRC_NTF)) = (0x00000000)
+#define DEF_MRX_BAR_NTF() (REG32(ADR_MRX_BAR_NTF)) = (0x00000000)
+#define DEF_MRX_MB_MISS() (REG32(ADR_MRX_MB_MISS)) = (0x00000000)
+#define DEF_MRX_NIDLE_MISS() (REG32(ADR_MRX_NIDLE_MISS)) = (0x00000000)
+#define DEF_MRX_CSR_NTF() (REG32(ADR_MRX_CSR_NTF)) = (0x00000000)
+#define DEF_DBG_Q0_FRM_SUCCESS() (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q0_FRM_FAIL() (REG32(ADR_DBG_Q0_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q0_ACK_SUCCESS() (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q0_ACK_FAIL() (REG32(ADR_DBG_Q0_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q1_FRM_SUCCESS() (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q1_FRM_FAIL() (REG32(ADR_DBG_Q1_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q1_ACK_SUCCESS() (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q1_ACK_FAIL() (REG32(ADR_DBG_Q1_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q2_FRM_SUCCESS() (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q2_FRM_FAIL() (REG32(ADR_DBG_Q2_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q2_ACK_SUCCESS() (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q2_ACK_FAIL() (REG32(ADR_DBG_Q2_ACK_FAIL)) = (0x00000000)
+#define DEF_DBG_Q3_FRM_SUCCESS() (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q3_FRM_FAIL() (REG32(ADR_DBG_Q3_FRM_FAIL)) = (0x00000000)
+#define DEF_DBG_Q3_ACK_SUCCESS() (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (0x00000000)
+#define DEF_DBG_Q3_ACK_FAIL() (REG32(ADR_DBG_Q3_ACK_FAIL)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP0() (REG32(ADR_MIB_SCRT_TKIP0)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP1() (REG32(ADR_MIB_SCRT_TKIP1)) = (0x00000000)
+#define DEF_MIB_SCRT_TKIP2() (REG32(ADR_MIB_SCRT_TKIP2)) = (0x00000000)
+#define DEF_MIB_SCRT_CCMP0() (REG32(ADR_MIB_SCRT_CCMP0)) = (0x00000000)
+#define DEF_MIB_SCRT_CCMP1() (REG32(ADR_MIB_SCRT_CCMP1)) = (0x00000000)
+#define DEF_DBG_LEN_CRC_FAIL() (REG32(ADR_DBG_LEN_CRC_FAIL)) = (0x00000000)
+#define DEF_DBG_LEN_ALC_FAIL() (REG32(ADR_DBG_LEN_ALC_FAIL)) = (0x00000000)
+#define DEF_DBG_AMPDU_PASS() (REG32(ADR_DBG_AMPDU_PASS)) = (0x00000000)
+#define DEF_DBG_AMPDU_FAIL() (REG32(ADR_DBG_AMPDU_FAIL)) = (0x00000000)
+#define DEF_ID_ALC_FAIL1() (REG32(ADR_ID_ALC_FAIL1)) = (0x00000000)
+#define DEF_ID_ALC_FAIL2() (REG32(ADR_ID_ALC_FAIL2)) = (0x00000000)
+#define DEF_CBR_HARD_WIRE_PIN_REGISTER() (REG32(ADR_CBR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
+#define DEF_CBR_MANUAL_ENABLE_REGISTER() (REG32(ADR_CBR_MANUAL_ENABLE_REGISTER)) = (0x00001fc0)
+#define DEF_CBR_LDO_REGISTER() (REG32(ADR_CBR_LDO_REGISTER)) = (0x2496db1b)
+#define DEF_CBR_ABB_REGISTER_1() (REG32(ADR_CBR_ABB_REGISTER_1)) = (0x151558dd)
+#define DEF_CBR_ABB_REGISTER_2() (REG32(ADR_CBR_ABB_REGISTER_2)) = (0x01011a88)
+#define DEF_CBR_TX_FE_REGISTER() (REG32(ADR_CBR_TX_FE_REGISTER)) = (0x3cbe84fe)
+#define DEF_CBR_RX_FE_REGISTER_1() (REG32(ADR_CBR_RX_FE_REGISTER_1)) = (0x00657579)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
+#define DEF_CBR_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_CBR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
+#define DEF_CBR_RX_FSM_REGISTER() (REG32(ADR_CBR_RX_FSM_REGISTER)) = (0x00000ca8)
+#define DEF_CBR_RX_ADC_REGISTER() (REG32(ADR_CBR_RX_ADC_REGISTER)) = (0x002a0224)
+#define DEF_CBR_TX_DAC_REGISTER() (REG32(ADR_CBR_TX_DAC_REGISTER)) = (0x00002655)
+#define DEF_CBR_SX_ENABLE_RGISTER() (REG32(ADR_CBR_SX_ENABLE_RGISTER)) = (0x0000647c)
+#define DEF_CBR_SYN_RGISTER_1() (REG32(ADR_CBR_SYN_RGISTER_1)) = (0xaa800000)
+#define DEF_CBR_SYN_RGISTER_2() (REG32(ADR_CBR_SYN_RGISTER_2)) = (0x00550800)
+#define DEF_CBR_SYN_PFD_CHP() (REG32(ADR_CBR_SYN_PFD_CHP)) = (0x07c0894a)
+#define DEF_CBR_SYN_VCO_LOBF() (REG32(ADR_CBR_SYN_VCO_LOBF)) = (0xfcccca27)
+#define DEF_CBR_SYN_DIV_SDM_XOSC() (REG32(ADR_CBR_SYN_DIV_SDM_XOSC)) = (0x2773c93c)
+#define DEF_CBR_SYN_LCK1() (REG32(ADR_CBR_SYN_LCK1)) = (0x00000a7c)
+#define DEF_CBR_SYN_LCK2() (REG32(ADR_CBR_SYN_LCK2)) = (0x01c67ff4)
+#define DEF_CBR_DPLL_VCO_REGISTER() (REG32(ADR_CBR_DPLL_VCO_REGISTER)) = (0x00103014)
+#define DEF_CBR_DPLL_CP_PFD_REGISTER() (REG32(ADR_CBR_DPLL_CP_PFD_REGISTER)) = (0x0001848c)
+#define DEF_CBR_DPLL_DIVIDER_REGISTER() (REG32(ADR_CBR_DPLL_DIVIDER_REGISTER)) = (0x034061e0)
+#define DEF_CBR_DCOC_IDAC_REGISTER1() (REG32(ADR_CBR_DCOC_IDAC_REGISTER1)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER2() (REG32(ADR_CBR_DCOC_IDAC_REGISTER2)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER3() (REG32(ADR_CBR_DCOC_IDAC_REGISTER3)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER4() (REG32(ADR_CBR_DCOC_IDAC_REGISTER4)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER5() (REG32(ADR_CBR_DCOC_IDAC_REGISTER5)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER6() (REG32(ADR_CBR_DCOC_IDAC_REGISTER6)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER7() (REG32(ADR_CBR_DCOC_IDAC_REGISTER7)) = (0x00820820)
+#define DEF_CBR_DCOC_IDAC_REGISTER8() (REG32(ADR_CBR_DCOC_IDAC_REGISTER8)) = (0x00820820)
+#define DEF_CBR_RCAL_REGISTER() (REG32(ADR_CBR_RCAL_REGISTER)) = (0x00004080)
+#define DEF_CBR_MANUAL_REGISTER() (REG32(ADR_CBR_MANUAL_REGISTER)) = (0x00003e7e)
+#define DEF_CBR_TRX_DUMMY_REGISTER() (REG32(ADR_CBR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_CBR_SX_DUMMY_REGISTER() (REG32(ADR_CBR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_CBR_RG_PKT_GEN_0() (REG32(ADR_CBR_RG_PKT_GEN_0)) = (0x00000000)
+#define DEF_CBR_RG_PKT_GEN_1() (REG32(ADR_CBR_RG_PKT_GEN_1)) = (0x00000000)
+#define DEF_CBR_RG_PKT_GEN_2() (REG32(ADR_CBR_RG_PKT_GEN_2)) = (0x00000000)
+#define DEF_CBR_RG_INTEGRATION() (REG32(ADR_CBR_RG_INTEGRATION)) = (0x00000000)
+#define DEF_CBR_RG_PKT_GEN_TXCNT() (REG32(ADR_CBR_RG_PKT_GEN_TXCNT)) = (0x00000000)
+#define DEF_CBR_PATTERN_GEN() (REG32(ADR_CBR_PATTERN_GEN)) = (0xff000000)
+#define DEF_MB_CPU_INT() (REG32(ADR_MB_CPU_INT)) = (0x00000000)
+#define DEF_CPU_ID_TB0() (REG32(ADR_CPU_ID_TB0)) = (0x00000000)
+#define DEF_CPU_ID_TB1() (REG32(ADR_CPU_ID_TB1)) = (0x00000000)
+#define DEF_CH0_TRIG_1() (REG32(ADR_CH0_TRIG_1)) = (0x00000000)
+#define DEF_CH0_TRIG_0() (REG32(ADR_CH0_TRIG_0)) = (0x00000000)
+#define DEF_CH0_PRI_TRIG() (REG32(ADR_CH0_PRI_TRIG)) = (0x00000000)
+#define DEF_MCU_STATUS() (REG32(ADR_MCU_STATUS)) = (0x00000000)
+#define DEF_RD_IN_FFCNT1() (REG32(ADR_RD_IN_FFCNT1)) = (0x00000000)
+#define DEF_RD_IN_FFCNT2() (REG32(ADR_RD_IN_FFCNT2)) = (0x00000000)
+#define DEF_RD_FFIN_FULL() (REG32(ADR_RD_FFIN_FULL)) = (0x00000000)
+#define DEF_MBOX_HALT_CFG() (REG32(ADR_MBOX_HALT_CFG)) = (0x00000000)
+#define DEF_MB_DBG_CFG1() (REG32(ADR_MB_DBG_CFG1)) = (0x00080000)
+#define DEF_MB_DBG_CFG2() (REG32(ADR_MB_DBG_CFG2)) = (0x00000000)
+#define DEF_MB_DBG_CFG3() (REG32(ADR_MB_DBG_CFG3)) = (0x00000000)
+#define DEF_MB_DBG_CFG4() (REG32(ADR_MB_DBG_CFG4)) = (0xffffffff)
+#define DEF_MB_OUT_QUEUE_CFG() (REG32(ADR_MB_OUT_QUEUE_CFG)) = (0x00000002)
+#define DEF_MB_OUT_QUEUE_FLUSH() (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT1() (REG32(ADR_RD_FFOUT_CNT1)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT2() (REG32(ADR_RD_FFOUT_CNT2)) = (0x00000000)
+#define DEF_RD_FFOUT_CNT3() (REG32(ADR_RD_FFOUT_CNT3)) = (0x00000000)
+#define DEF_RD_FFOUT_FULL() (REG32(ADR_RD_FFOUT_FULL)) = (0x00000000)
+#define DEF_MB_THRESHOLD6() (REG32(ADR_MB_THRESHOLD6)) = (0x00000000)
+#define DEF_MB_THRESHOLD7() (REG32(ADR_MB_THRESHOLD7)) = (0x00000000)
+#define DEF_MB_THRESHOLD8() (REG32(ADR_MB_THRESHOLD8)) = (0x00000000)
+#define DEF_MB_THRESHOLD9() (REG32(ADR_MB_THRESHOLD9)) = (0x00000000)
+#define DEF_MB_THRESHOLD10() (REG32(ADR_MB_THRESHOLD10)) = (0x00000000)
+#define DEF_MB_TRASH_CFG() (REG32(ADR_MB_TRASH_CFG)) = (0x01000001)
+#define DEF_MB_IN_FF_FLUSH() (REG32(ADR_MB_IN_FF_FLUSH)) = (0x00000000)
+#define DEF_CPU_ID_TB2() (REG32(ADR_CPU_ID_TB2)) = (0x00000000)
+#define DEF_CPU_ID_TB3() (REG32(ADR_CPU_ID_TB3)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_CFG0() (REG32(ADR_PHY_IQ_LOG_CFG0)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_CFG1() (REG32(ADR_PHY_IQ_LOG_CFG1)) = (0x00000000)
+#define DEF_PHY_IQ_LOG_LEN() (REG32(ADR_PHY_IQ_LOG_LEN)) = (0x00001000)
+#define DEF_PHY_IQ_LOG_PTR() (REG32(ADR_PHY_IQ_LOG_PTR)) = (0x00000000)
+#define DEF_WR_ALC() (REG32(ADR_WR_ALC)) = (0x00000000)
+#define DEF_GETID() (REG32(ADR_GETID)) = (0x00000000)
+#define DEF_CH_STA_PRI() (REG32(ADR_CH_STA_PRI)) = (0x00000213)
+#define DEF_RD_ID0() (REG32(ADR_RD_ID0)) = (0x00000000)
+#define DEF_RD_ID1() (REG32(ADR_RD_ID1)) = (0x00000000)
+#define DEF_IMD_CFG() (REG32(ADR_IMD_CFG)) = (0x00000000)
+#define DEF_IMD_STA() (REG32(ADR_IMD_STA)) = (0x00000000)
+#define DEF_ALC_STA() (REG32(ADR_ALC_STA)) = (0x01000000)
+#define DEF_TRX_ID_COUNT() (REG32(ADR_TRX_ID_COUNT)) = (0x00000000)
+#define DEF_TRX_ID_THRESHOLD() (REG32(ADR_TRX_ID_THRESHOLD)) = (0x01ee3c3c)
+#define DEF_TX_ID0() (REG32(ADR_TX_ID0)) = (0x00000000)
+#define DEF_TX_ID1() (REG32(ADR_TX_ID1)) = (0x00000000)
+#define DEF_RX_ID0() (REG32(ADR_RX_ID0)) = (0x00000000)
+#define DEF_RX_ID1() (REG32(ADR_RX_ID1)) = (0x00000000)
+#define DEF_RTN_STA() (REG32(ADR_RTN_STA)) = (0x00000001)
+#define DEF_ID_LEN_THREADSHOLD1() (REG32(ADR_ID_LEN_THREADSHOLD1)) = (0x000f0641)
+#define DEF_ID_LEN_THREADSHOLD2() (REG32(ADR_ID_LEN_THREADSHOLD2)) = (0x00000000)
+#define DEF_CH_ARB_PRI() (REG32(ADR_CH_ARB_PRI)) = (0x00031201)
+#define DEF_TX_ID_REMAIN_STATUS() (REG32(ADR_TX_ID_REMAIN_STATUS)) = (0x00000000)
+#define DEF_ID_INFO_STA() (REG32(ADR_ID_INFO_STA)) = (0x00000100)
+#define DEF_TX_LIMIT_INTR() (REG32(ADR_TX_LIMIT_INTR)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO() (REG32(ADR_TX_ID_ALL_INFO)) = (0x00000000)
+#define DEF_RD_ID2() (REG32(ADR_RD_ID2)) = (0x00000000)
+#define DEF_RD_ID3() (REG32(ADR_RD_ID3)) = (0x00000000)
+#define DEF_TX_ID2() (REG32(ADR_TX_ID2)) = (0x00000000)
+#define DEF_TX_ID3() (REG32(ADR_TX_ID3)) = (0x00000000)
+#define DEF_RX_ID2() (REG32(ADR_RX_ID2)) = (0x00000000)
+#define DEF_RX_ID3() (REG32(ADR_RX_ID3)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO2() (REG32(ADR_TX_ID_ALL_INFO2)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO_A() (REG32(ADR_TX_ID_ALL_INFO_A)) = (0x00000000)
+#define DEF_TX_ID_ALL_INFO_B() (REG32(ADR_TX_ID_ALL_INFO_B)) = (0x00000000)
+#define DEF_TX_ID_REMAIN_STATUS2() (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (0x01000100)
+#define DEF_ALC_ID_INFO() (REG32(ADR_ALC_ID_INFO)) = (0x00000000)
+#define DEF_ALC_ID_INF1() (REG32(ADR_ALC_ID_INF1)) = (0x00000000)
+#define DEF_PHY_EN_0() (REG32(ADR_PHY_EN_0)) = (0x00000014)
+#define DEF_PHY_EN_1() (REG32(ADR_PHY_EN_1)) = (0x00000000)
+#define DEF_SVN_VERSION_REG() (REG32(ADR_SVN_VERSION_REG)) = (0x00000000)
+#define DEF_PHY_PKT_GEN_0() (REG32(ADR_PHY_PKT_GEN_0)) = (0x00000064)
+#define DEF_PHY_PKT_GEN_1() (REG32(ADR_PHY_PKT_GEN_1)) = (0x00000fff)
+#define DEF_PHY_PKT_GEN_2() (REG32(ADR_PHY_PKT_GEN_2)) = (0x00000003)
+#define DEF_PHY_PKT_GEN_3() (REG32(ADR_PHY_PKT_GEN_3)) = (0x005a0220)
+#define DEF_PHY_PKT_GEN_4() (REG32(ADR_PHY_PKT_GEN_4)) = (0x00000001)
+#define DEF_PHY_REG_00() (REG32(ADR_PHY_REG_00)) = (0x10000000)
+#define DEF_PHY_REG_01() (REG32(ADR_PHY_REG_01)) = (0x00000000)
+#define DEF_PHY_REG_02_AGC() (REG32(ADR_PHY_REG_02_AGC)) = (0x80046771)
+#define DEF_PHY_REG_03_AGC() (REG32(ADR_PHY_REG_03_AGC)) = (0x1f300f6f)
+#define DEF_PHY_REG_04_AGC() (REG32(ADR_PHY_REG_04_AGC)) = (0x663f36d0)
+#define DEF_PHY_REG_05_AGC() (REG32(ADR_PHY_REG_05_AGC)) = (0x106c0000)
+#define DEF_PHY_REG_06_11B_DAGC() (REG32(ADR_PHY_REG_06_11B_DAGC)) = (0x01603fff)
+#define DEF_PHY_REG_07_11B_DAGC() (REG32(ADR_PHY_REG_07_11B_DAGC)) = (0x00600808)
+#define DEF_PHY_REG_08_11GN_DAGC() (REG32(ADR_PHY_REG_08_11GN_DAGC)) = (0xff000160)
+#define DEF_PHY_REG_09_11GN_DAGC() (REG32(ADR_PHY_REG_09_11GN_DAGC)) = (0x00080840)
+#define DEF_PHY_READ_REG_00_DIG_PWR() (REG32(ADR_PHY_READ_REG_00_DIG_PWR)) = (0x00000000)
+#define DEF_PHY_READ_REG_01_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_01_RF_GAIN_PWR)) = (0x00000000)
+#define DEF_PHY_READ_REG_02_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_02_RF_GAIN_PWR)) = (0x00000000)
+#define DEF_PHY_READ_REG_03_RF_GAIN_PWR() (REG32(ADR_PHY_READ_REG_03_RF_GAIN_PWR)) = (0x00000000)
+#define DEF_PHY_REG_10_TX_DES() (REG32(ADR_PHY_REG_10_TX_DES)) = (0x00010405)
+#define DEF_PHY_REG_11_TX_DES() (REG32(ADR_PHY_REG_11_TX_DES)) = (0x06090813)
+#define DEF_PHY_REG_12_TX_DES() (REG32(ADR_PHY_REG_12_TX_DES)) = (0x12070000)
+#define DEF_PHY_REG_13_RX_DES() (REG32(ADR_PHY_REG_13_RX_DES)) = (0x01000405)
+#define DEF_PHY_REG_14_RX_DES() (REG32(ADR_PHY_REG_14_RX_DES)) = (0x06090813)
+#define DEF_PHY_REG_15_RX_DES() (REG32(ADR_PHY_REG_15_RX_DES)) = (0x12010000)
+#define DEF_PHY_REG_16_TX_DES_EXCP() (REG32(ADR_PHY_REG_16_TX_DES_EXCP)) = (0x00000000)
+#define DEF_PHY_REG_17_TX_DES_EXCP() (REG32(ADR_PHY_REG_17_TX_DES_EXCP)) = (0x10110000)
+#define DEF_PHY_REG_18_RSSI_SNR() (REG32(ADR_PHY_REG_18_RSSI_SNR)) = (0x00fc000f)
+#define DEF_PHY_REG_19_DAC_MANUAL() (REG32(ADR_PHY_REG_19_DAC_MANUAL)) = (0x00000000)
+#define DEF_PHY_REG_20_MRX_CNT() (REG32(ADR_PHY_REG_20_MRX_CNT)) = (0x00000000)
+#define DEF_PHY_REG_21_TRX_RAMP() (REG32(ADR_PHY_REG_21_TRX_RAMP)) = (0x3c012801)
+#define DEF_PHY_REG_22_TRX_RAMP() (REG32(ADR_PHY_REG_22_TRX_RAMP)) = (0x24243724)
+#define DEF_PHY_REG_23_ANT() (REG32(ADR_PHY_REG_23_ANT)) = (0x00000011)
+#define DEF_PHY_REG_24_MTX_LEN_CNT() (REG32(ADR_PHY_REG_24_MTX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_REG_25_MTX_LEN_CNT() (REG32(ADR_PHY_REG_25_MTX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_REG_26_MRX_LEN_CNT() (REG32(ADR_PHY_REG_26_MRX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_REG_27_MRX_LEN_CNT() (REG32(ADR_PHY_REG_27_MRX_LEN_CNT)) = (0x1fff0000)
+#define DEF_PHY_READ_REG_04() (REG32(ADR_PHY_READ_REG_04)) = (0x00000000)
+#define DEF_PHY_READ_REG_05() (REG32(ADR_PHY_READ_REG_05)) = (0x00000000)
+#define DEF_PHY_REG_28_BIST() (REG32(ADR_PHY_REG_28_BIST)) = (0x0000fe3e)
+#define DEF_PHY_READ_REG_06_BIST() (REG32(ADR_PHY_READ_REG_06_BIST)) = (0x00000000)
+#define DEF_PHY_READ_REG_07_BIST() (REG32(ADR_PHY_READ_REG_07_BIST)) = (0x00000000)
+#define DEF_PHY_REG_29_MTRX_MAC() (REG32(ADR_PHY_REG_29_MTRX_MAC)) = (0xffffffff)
+#define DEF_PHY_READ_REG_08_MTRX_MAC() (REG32(ADR_PHY_READ_REG_08_MTRX_MAC)) = (0x00000000)
+#define DEF_PHY_READ_REG_09_MTRX_MAC() (REG32(ADR_PHY_READ_REG_09_MTRX_MAC)) = (0x00000000)
+#define DEF_PHY_REG_30_TX_UP_FIL() (REG32(ADR_PHY_REG_30_TX_UP_FIL)) = (0x0ead04f5)
+#define DEF_PHY_REG_31_TX_UP_FIL() (REG32(ADR_PHY_REG_31_TX_UP_FIL)) = (0x0fd60080)
+#define DEF_PHY_REG_32_TX_UP_FIL() (REG32(ADR_PHY_REG_32_TX_UP_FIL)) = (0x00000009)
+#define DEF_PHY_READ_TBUS() (REG32(ADR_PHY_READ_TBUS)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_00() (REG32(ADR_TX_11B_FIL_COEF_00)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_01() (REG32(ADR_TX_11B_FIL_COEF_01)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_02() (REG32(ADR_TX_11B_FIL_COEF_02)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_03() (REG32(ADR_TX_11B_FIL_COEF_03)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_04() (REG32(ADR_TX_11B_FIL_COEF_04)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_05() (REG32(ADR_TX_11B_FIL_COEF_05)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_06() (REG32(ADR_TX_11B_FIL_COEF_06)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_07() (REG32(ADR_TX_11B_FIL_COEF_07)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_08() (REG32(ADR_TX_11B_FIL_COEF_08)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_09() (REG32(ADR_TX_11B_FIL_COEF_09)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_10() (REG32(ADR_TX_11B_FIL_COEF_10)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_11() (REG32(ADR_TX_11B_FIL_COEF_11)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_12() (REG32(ADR_TX_11B_FIL_COEF_12)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_13() (REG32(ADR_TX_11B_FIL_COEF_13)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_14() (REG32(ADR_TX_11B_FIL_COEF_14)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_15() (REG32(ADR_TX_11B_FIL_COEF_15)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_16() (REG32(ADR_TX_11B_FIL_COEF_16)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_17() (REG32(ADR_TX_11B_FIL_COEF_17)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_18() (REG32(ADR_TX_11B_FIL_COEF_18)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_19() (REG32(ADR_TX_11B_FIL_COEF_19)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_20() (REG32(ADR_TX_11B_FIL_COEF_20)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_21() (REG32(ADR_TX_11B_FIL_COEF_21)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_22() (REG32(ADR_TX_11B_FIL_COEF_22)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_23() (REG32(ADR_TX_11B_FIL_COEF_23)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_24() (REG32(ADR_TX_11B_FIL_COEF_24)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_25() (REG32(ADR_TX_11B_FIL_COEF_25)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_26() (REG32(ADR_TX_11B_FIL_COEF_26)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_27() (REG32(ADR_TX_11B_FIL_COEF_27)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_28() (REG32(ADR_TX_11B_FIL_COEF_28)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_29() (REG32(ADR_TX_11B_FIL_COEF_29)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_30() (REG32(ADR_TX_11B_FIL_COEF_30)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_31() (REG32(ADR_TX_11B_FIL_COEF_31)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_32() (REG32(ADR_TX_11B_FIL_COEF_32)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_33() (REG32(ADR_TX_11B_FIL_COEF_33)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_34() (REG32(ADR_TX_11B_FIL_COEF_34)) = (0x00000000)
+#define DEF_TX_11B_FIL_COEF_35() (REG32(ADR_TX_11B_FIL_COEF_35)) = (0x00000005)
+#define DEF_TX_11B_FIL_COEF_36() (REG32(ADR_TX_11B_FIL_COEF_36)) = (0x0000003d)
+#define DEF_TX_11B_FIL_COEF_37() (REG32(ADR_TX_11B_FIL_COEF_37)) = (0x00000162)
+#define DEF_TX_11B_FIL_COEF_38() (REG32(ADR_TX_11B_FIL_COEF_38)) = (0x00000400)
+#define DEF_TX_11B_FIL_COEF_39() (REG32(ADR_TX_11B_FIL_COEF_39)) = (0x00000699)
+#define DEF_TX_11B_FIL_COEF_40() (REG32(ADR_TX_11B_FIL_COEF_40)) = (0x00000787)
+#define DEF_TX_11B_PLCP() (REG32(ADR_TX_11B_PLCP)) = (0x00000000)
+#define DEF_TX_11B_RAMP() (REG32(ADR_TX_11B_RAMP)) = (0x0000403c)
+#define DEF_TX_11B_EN_CNT_RST_N() (REG32(ADR_TX_11B_EN_CNT_RST_N)) = (0x00000001)
+#define DEF_TX_11B_EN_CNT() (REG32(ADR_TX_11B_EN_CNT)) = (0x00000000)
+#define DEF_TX_11B_PKT_GEN_CNT() (REG32(ADR_TX_11B_PKT_GEN_CNT)) = (0x00000000)
+#define DEF_RX_11B_DES_DLY() (REG32(ADR_RX_11B_DES_DLY)) = (0x00000044)
+#define DEF_RX_11B_CCA_0() (REG32(ADR_RX_11B_CCA_0)) = (0x00040000)
+#define DEF_RX_11B_CCA_1() (REG32(ADR_RX_11B_CCA_1)) = (0x00400040)
+#define DEF_RX_11B_TR_KP_KI_0() (REG32(ADR_RX_11B_TR_KP_KI_0)) = (0x00003467)
+#define DEF_RX_11B_TR_KP_KI_1() (REG32(ADR_RX_11B_TR_KP_KI_1)) = (0x00540000)
+#define DEF_RX_11B_CE_CNT_THRESHOLD() (REG32(ADR_RX_11B_CE_CNT_THRESHOLD)) = (0x12243615)
+#define DEF_RX_11B_CE_MU_0() (REG32(ADR_RX_11B_CE_MU_0)) = (0x00390002)
+#define DEF_RX_11B_CE_MU_1() (REG32(ADR_RX_11B_CE_MU_1)) = (0x03456777)
+#define DEF_RX_11B_EQ_MU_0() (REG32(ADR_RX_11B_EQ_MU_0)) = (0x00350046)
+#define DEF_RX_11B_EQ_MU_1() (REG32(ADR_RX_11B_EQ_MU_1)) = (0x00570057)
+#define DEF_RX_11B_EQ_CR_KP_KI() (REG32(ADR_RX_11B_EQ_CR_KP_KI)) = (0x00236700)
+#define DEF_RX_11B_LPF_RATE() (REG32(ADR_RX_11B_LPF_RATE)) = (0x000d1746)
+#define DEF_RX_11B_CIT_CNT_THRESHOLD() (REG32(ADR_RX_11B_CIT_CNT_THRESHOLD)) = (0x04061787)
+#define DEF_RX_11B_EQ_CH_MAIN_TAP() (REG32(ADR_RX_11B_EQ_CH_MAIN_TAP)) = (0x07800000)
+#define DEF_RX_11B_SEARCH_CNT_TH() (REG32(ADR_RX_11B_SEARCH_CNT_TH)) = (0x00c0000a)
+#define DEF_RX_11B_CCA_CONTROL() (REG32(ADR_RX_11B_CCA_CONTROL)) = (0x00000000)
+#define DEF_RX_11B_FREQUENCY_OFFSET() (REG32(ADR_RX_11B_FREQUENCY_OFFSET)) = (0x00000000)
+#define DEF_RX_11B_SNR_RSSI() (REG32(ADR_RX_11B_SNR_RSSI)) = (0x00000000)
+#define DEF_RX_11B_SFD_CRC_CNT() (REG32(ADR_RX_11B_SFD_CRC_CNT)) = (0x00000000)
+#define DEF_RX_11B_PKT_ERR_AND_PKT_ERR_CNT() (REG32(ADR_RX_11B_PKT_ERR_AND_PKT_ERR_CNT)) = (0x00000000)
+#define DEF_RX_11B_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11B_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
+#define DEF_RX_11B_SFD_FILED_0() (REG32(ADR_RX_11B_SFD_FILED_0)) = (0x00000000)
+#define DEF_RX_11B_SFD_FIELD_1() (REG32(ADR_RX_11B_SFD_FIELD_1)) = (0x00000000)
+#define DEF_RX_11B_PKT_STAT_EN() (REG32(ADR_RX_11B_PKT_STAT_EN)) = (0x00100000)
+#define DEF_RX_11B_SOFT_RST() (REG32(ADR_RX_11B_SOFT_RST)) = (0x00000001)
+#define DEF_TX_11GN_RAMP() (REG32(ADR_TX_11GN_RAMP)) = (0x0000233c)
+#define DEF_TX_11GN_PLCP() (REG32(ADR_TX_11GN_PLCP)) = (0x5d08908e)
+#define DEF_TX_11GN_PKT_GEN_CNT() (REG32(ADR_TX_11GN_PKT_GEN_CNT)) = (0x00000000)
+#define DEF_TX_11GN_PLCP_CRC_ERR_CNT() (REG32(ADR_TX_11GN_PLCP_CRC_ERR_CNT)) = (0x00000000)
+#define DEF_RX_11GN_DES_DLY() (REG32(ADR_RX_11GN_DES_DLY)) = (0x00000044)
+#define DEF_RX_11GN_TR_0() (REG32(ADR_RX_11GN_TR_0)) = (0x00750075)
+#define DEF_RX_11GN_TR_1() (REG32(ADR_RX_11GN_TR_1)) = (0x00000075)
+#define DEF_RX_11GN_TR_2() (REG32(ADR_RX_11GN_TR_2)) = (0x10000075)
+#define DEF_RX_11GN_CCA_0() (REG32(ADR_RX_11GN_CCA_0)) = (0x38324705)
+#define DEF_RX_11GN_CCA_1() (REG32(ADR_RX_11GN_CCA_1)) = (0x30182000)
+#define DEF_RX_11GN_CCA_2() (REG32(ADR_RX_11GN_CCA_2)) = (0x20600000)
+#define DEF_RX_11GN_CCA_FFT_SCALE() (REG32(ADR_RX_11GN_CCA_FFT_SCALE)) = (0x0a010100)
+#define DEF_RX_11GN_SOFT_DEMAP_0() (REG32(ADR_RX_11GN_SOFT_DEMAP_0)) = (0x50505050)
+#define DEF_RX_11GN_SOFT_DEMAP_1() (REG32(ADR_RX_11GN_SOFT_DEMAP_1)) = (0x50000000)
+#define DEF_RX_11GN_SOFT_DEMAP_2() (REG32(ADR_RX_11GN_SOFT_DEMAP_2)) = (0x50505050)
+#define DEF_RX_11GN_SOFT_DEMAP_3() (REG32(ADR_RX_11GN_SOFT_DEMAP_3)) = (0x50505050)
+#define DEF_RX_11GN_SOFT_DEMAP_4() (REG32(ADR_RX_11GN_SOFT_DEMAP_4)) = (0x50000000)
+#define DEF_RX_11GN_SOFT_DEMAP_5() (REG32(ADR_RX_11GN_SOFT_DEMAP_5)) = (0x00000000)
+#define DEF_RX_11GN_SYM_BOUND_0() (REG32(ADR_RX_11GN_SYM_BOUND_0)) = (0x00001420)
+#define DEF_RX_11GN_SYM_BOUND_1() (REG32(ADR_RX_11GN_SYM_BOUND_1)) = (0x0000200a)
+#define DEF_RX_11GN_CCA_PWR() (REG32(ADR_RX_11GN_CCA_PWR)) = (0x30000280)
+#define DEF_RX_11GN_CCA_CNT() (REG32(ADR_RX_11GN_CCA_CNT)) = (0x30023002)
+#define DEF_RX_11GN_CCA_ATCOR_RE_CHECK() (REG32(ADR_RX_11GN_CCA_ATCOR_RE_CHECK)) = (0x0000003a)
+#define DEF_RX_11GN_VTB_TB() (REG32(ADR_RX_11GN_VTB_TB)) = (0x40000000)
+#define DEF_RX_11GN_ERR_UPDATE() (REG32(ADR_RX_11GN_ERR_UPDATE)) = (0x009e007e)
+#define DEF_RX_11GN_SHORT_GI() (REG32(ADR_RX_11GN_SHORT_GI)) = (0x00044400)
+#define DEF_RX_11GN_CHANNEL_UPDATE() (REG32(ADR_RX_11GN_CHANNEL_UPDATE)) = (0x82000000)
+#define DEF_RX_11GN_PKT_FORMAT_0() (REG32(ADR_RX_11GN_PKT_FORMAT_0)) = (0x02003030)
+#define DEF_RX_11GN_PKT_FORMAT_1() (REG32(ADR_RX_11GN_PKT_FORMAT_1)) = (0x092a092a)
+#define DEF_RX_11GN_TX_TIME() (REG32(ADR_RX_11GN_TX_TIME)) = (0x00700010)
+#define DEF_RX_11GN_STBC_TR_KP_KI() (REG32(ADR_RX_11GN_STBC_TR_KP_KI)) = (0x00007575)
+#define DEF_RX_11GN_BIST_0() (REG32(ADR_RX_11GN_BIST_0)) = (0x0001fe3e)
+#define DEF_RX_11GN_BIST_1() (REG32(ADR_RX_11GN_BIST_1)) = (0x0000fe3e)
+#define DEF_RX_11GN_BIST_2() (REG32(ADR_RX_11GN_BIST_2)) = (0x00000000)
+#define DEF_RX_11GN_BIST_3() (REG32(ADR_RX_11GN_BIST_3)) = (0x00000000)
+#define DEF_RX_11GN_BIST_4() (REG32(ADR_RX_11GN_BIST_4)) = (0x00000000)
+#define DEF_RX_11GN_BIST_5() (REG32(ADR_RX_11GN_BIST_5)) = (0x00000000)
+#define DEF_RX_11GN_SPECTRUM_ANALYZER() (REG32(ADR_RX_11GN_SPECTRUM_ANALYZER)) = (0x00000000)
+#define DEF_RX_11GN_READ_0() (REG32(ADR_RX_11GN_READ_0)) = (0x00000000)
+#define DEF_RX_11GN_FREQ_OFFSET() (REG32(ADR_RX_11GN_FREQ_OFFSET)) = (0x00000000)
+#define DEF_RX_11GN_SIGNAL_FIELD_0() (REG32(ADR_RX_11GN_SIGNAL_FIELD_0)) = (0x00000000)
+#define DEF_RX_11GN_SIGNAL_FIELD_1() (REG32(ADR_RX_11GN_SIGNAL_FIELD_1)) = (0x00000000)
+#define DEF_RX_11GN_PKT_ERR_CNT() (REG32(ADR_RX_11GN_PKT_ERR_CNT)) = (0x00000000)
+#define DEF_RX_11GN_PKT_CCA_AND_PKT_CNT() (REG32(ADR_RX_11GN_PKT_CCA_AND_PKT_CNT)) = (0x00000000)
+#define DEF_RX_11GN_SERVICE_LENGTH_FIELD() (REG32(ADR_RX_11GN_SERVICE_LENGTH_FIELD)) = (0x00000000)
+#define DEF_RX_11GN_RATE() (REG32(ADR_RX_11GN_RATE)) = (0x00000000)
+#define DEF_RX_11GN_STAT_EN() (REG32(ADR_RX_11GN_STAT_EN)) = (0x00100001)
+#define DEF_RX_11GN_SOFT_RST() (REG32(ADR_RX_11GN_SOFT_RST)) = (0x00000001)
+#define DEF_RF_CONTROL_0() (REG32(ADR_RF_CONTROL_0)) = (0x00000000)
+#define DEF_RF_CONTROL_1() (REG32(ADR_RF_CONTROL_1)) = (0x00008000)
+#define DEF_TX_IQ_CONTROL_0() (REG32(ADR_TX_IQ_CONTROL_0)) = (0x00200020)
+#define DEF_TX_IQ_CONTROL_1() (REG32(ADR_TX_IQ_CONTROL_1)) = (0x00028080)
+#define DEF_TX_IQ_CONTROL_2() (REG32(ADR_TX_IQ_CONTROL_2)) = (0x00000000)
+#define DEF_TX_COMPENSATION_CONTROL() (REG32(ADR_TX_COMPENSATION_CONTROL)) = (0x00000000)
+#define DEF_RX_COMPENSATION_CONTROL() (REG32(ADR_RX_COMPENSATION_CONTROL)) = (0x00000000)
+#define DEF_RX_OBSERVATION_CIRCUIT_0() (REG32(ADR_RX_OBSERVATION_CIRCUIT_0)) = (0x000028ff)
+#define DEF_RX_OBSERVATION_CIRCUIT_1() (REG32(ADR_RX_OBSERVATION_CIRCUIT_1)) = (0x00000000)
+#define DEF_RX_OBSERVATION_CIRCUIT_2() (REG32(ADR_RX_OBSERVATION_CIRCUIT_2)) = (0x00000000)
+#define DEF_RX_OBSERVATION_CIRCUIT_3() (REG32(ADR_RX_OBSERVATION_CIRCUIT_3)) = (0x00000000)
+#define DEF_RF_IQ_CONTROL_0() (REG32(ADR_RF_IQ_CONTROL_0)) = (0x00000202)
+#define DEF_RF_IQ_CONTROL_1() (REG32(ADR_RF_IQ_CONTROL_1)) = (0x00ffc200)
+#define DEF_RF_IQ_CONTROL_2() (REG32(ADR_RF_IQ_CONTROL_2)) = (0x00000000)
+#define DEF_RF_IQ_CONTROL_3() (REG32(ADR_RF_IQ_CONTROL_3)) = (0x00000000)
+#define DEF_DPD_CONTROL() (REG32(ADR_DPD_CONTROL)) = (0x00000000)
+#define DEF_DPD_GAIN_TABLE_0() (REG32(ADR_DPD_GAIN_TABLE_0)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_1() (REG32(ADR_DPD_GAIN_TABLE_1)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_2() (REG32(ADR_DPD_GAIN_TABLE_2)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_3() (REG32(ADR_DPD_GAIN_TABLE_3)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_4() (REG32(ADR_DPD_GAIN_TABLE_4)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_5() (REG32(ADR_DPD_GAIN_TABLE_5)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_6() (REG32(ADR_DPD_GAIN_TABLE_6)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_7() (REG32(ADR_DPD_GAIN_TABLE_7)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_8() (REG32(ADR_DPD_GAIN_TABLE_8)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_9() (REG32(ADR_DPD_GAIN_TABLE_9)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_A() (REG32(ADR_DPD_GAIN_TABLE_A)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_B() (REG32(ADR_DPD_GAIN_TABLE_B)) = (0x02000200)
+#define DEF_DPD_GAIN_TABLE_C() (REG32(ADR_DPD_GAIN_TABLE_C)) = (0x02000200)
+#define DEF_DPD_PH_TABLE_0() (REG32(ADR_DPD_PH_TABLE_0)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_1() (REG32(ADR_DPD_PH_TABLE_1)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_2() (REG32(ADR_DPD_PH_TABLE_2)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_3() (REG32(ADR_DPD_PH_TABLE_3)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_4() (REG32(ADR_DPD_PH_TABLE_4)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_5() (REG32(ADR_DPD_PH_TABLE_5)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_6() (REG32(ADR_DPD_PH_TABLE_6)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_7() (REG32(ADR_DPD_PH_TABLE_7)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_8() (REG32(ADR_DPD_PH_TABLE_8)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_9() (REG32(ADR_DPD_PH_TABLE_9)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_A() (REG32(ADR_DPD_PH_TABLE_A)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_B() (REG32(ADR_DPD_PH_TABLE_B)) = (0x00000000)
+#define DEF_DPD_PH_TABLE_C() (REG32(ADR_DPD_PH_TABLE_C)) = (0x00000000)
+#define DEF_DPD_GAIN_ESTIMATION_0() (REG32(ADR_DPD_GAIN_ESTIMATION_0)) = (0x00000000)
+#define DEF_DPD_GAIN_ESTIMATION_1() (REG32(ADR_DPD_GAIN_ESTIMATION_1)) = (0x00000100)
+#define DEF_DPD_GAIN_ESTIMATION_2() (REG32(ADR_DPD_GAIN_ESTIMATION_2)) = (0x00000000)
+#define DEF_TX_GAIN_FACTOR() (REG32(ADR_TX_GAIN_FACTOR)) = (0x80808080)
+#define DEF_HARD_WIRE_PIN_REGISTER() (REG32(ADR_HARD_WIRE_PIN_REGISTER)) = (0x00004000)
+#define DEF_MANUAL_ENABLE_REGISTER() (REG32(ADR_MANUAL_ENABLE_REGISTER)) = (0x00000fc0)
+#define DEF_LDO_REGISTER() (REG32(ADR_LDO_REGISTER)) = (0x000db71b)
+#define DEF_ABB_REGISTER_1() (REG32(ADR_ABB_REGISTER_1)) = (0x151558dd)
+#define DEF_ABB_REGISTER_2() (REG32(ADR_ABB_REGISTER_2)) = (0x01011a88)
+#define DEF_TX_FE_REGISTER() (REG32(ADR_TX_FE_REGISTER)) = (0x3d3e84fe)
+#define DEF_RX_FE_REGISTER_1() (REG32(ADR_RX_FE_REGISTER_1)) = (0x03457579)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_1() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_1)) = (0x000103a7)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_2() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_2)) = (0x000103a6)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_3() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_3)) = (0x00012001)
+#define DEF_RX_FE_GAIN_DECODER_REGISTER_4() (REG32(ADR_RX_FE_GAIN_DECODER_REGISTER_4)) = (0x00036000)
+#define DEF_RX_TX_FSM_REGISTER() (REG32(ADR_RX_TX_FSM_REGISTER)) = (0x00030ca8)
+#define DEF_RX_ADC_REGISTER() (REG32(ADR_RX_ADC_REGISTER)) = (0x20ea0224)
+#define DEF_TX_DAC_REGISTER() (REG32(ADR_TX_DAC_REGISTER)) = (0x44000655)
+#define DEF_SX_ENABLE_REGISTER() (REG32(ADR_SX_ENABLE_REGISTER)) = (0x0003e07c)
+#define DEF_SYN_REGISTER_1() (REG32(ADR_SYN_REGISTER_1)) = (0xaa800000)
+#define DEF_SYN_REGISTER_2() (REG32(ADR_SYN_REGISTER_2)) = (0x00550800)
+#define DEF_SYN_PFD_CHP() (REG32(ADR_SYN_PFD_CHP)) = (0x07c0894a)
+#define DEF_SYN_VCO_LOBF() (REG32(ADR_SYN_VCO_LOBF)) = (0xfcccca27)
+#define DEF_SYN_DIV_SDM_XOSC() (REG32(ADR_SYN_DIV_SDM_XOSC)) = (0x07700830)
+#define DEF_SYN_KVCO_XO_FINE_TUNE_CBANK() (REG32(ADR_SYN_KVCO_XO_FINE_TUNE_CBANK)) = (0x00440000)
+#define DEF_SYN_LCK_VT() (REG32(ADR_SYN_LCK_VT)) = (0x00007ff4)
+#define DEF_DPLL_VCO_REGISTER() (REG32(ADR_DPLL_VCO_REGISTER)) = (0x0000000e)
+#define DEF_DPLL_CP_PFD_REGISTER() (REG32(ADR_DPLL_CP_PFD_REGISTER)) = (0x00088008)
+#define DEF_DPLL_DIVIDER_REGISTER() (REG32(ADR_DPLL_DIVIDER_REGISTER)) = (0x00406000)
+#define DEF_DCOC_IDAC_REGISTER1() (REG32(ADR_DCOC_IDAC_REGISTER1)) = (0x08820820)
+#define DEF_DCOC_IDAC_REGISTER2() (REG32(ADR_DCOC_IDAC_REGISTER2)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER3() (REG32(ADR_DCOC_IDAC_REGISTER3)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER4() (REG32(ADR_DCOC_IDAC_REGISTER4)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER5() (REG32(ADR_DCOC_IDAC_REGISTER5)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER6() (REG32(ADR_DCOC_IDAC_REGISTER6)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER7() (REG32(ADR_DCOC_IDAC_REGISTER7)) = (0x00820820)
+#define DEF_DCOC_IDAC_REGISTER8() (REG32(ADR_DCOC_IDAC_REGISTER8)) = (0x00820820)
+#define DEF_RCAL_REGISTER() (REG32(ADR_RCAL_REGISTER)) = (0x00004080)
+#define DEF_SX_LCK_BIN_REGISTERS_I() (REG32(ADR_SX_LCK_BIN_REGISTERS_I)) = (0x20080080)
+#define DEF_TRX_DUMMY_REGISTER() (REG32(ADR_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_SX_DUMMY_REGISTER() (REG32(ADR_SX_DUMMY_REGISTER)) = (0xaaaaaaaa)
+#define DEF_DPLL_FB_DIVIDER_REGISTERS_II() (REG32(ADR_DPLL_FB_DIVIDER_REGISTERS_II)) = (0x00ec2ec5)
+#define DEF_SX_LCK_BIN_REGISTERS_II() (REG32(ADR_SX_LCK_BIN_REGISTERS_II)) = (0x00000f13)
+#define DEF_RC_OSC_32K_CAL_REGISTERS() (REG32(ADR_RC_OSC_32K_CAL_REGISTERS)) = (0x00098900)
+#define DEF_RF_D_DIGITAL_DEBUG_PORT_REGISTER() (REG32(ADR_RF_D_DIGITAL_DEBUG_PORT_REGISTER)) = (0x00000000)
+#define DEF_MMU_CTRL() (REG32(ADR_MMU_CTRL)) = (0x00002042)
+#define DEF_HS_CTRL() (REG32(ADR_HS_CTRL)) = (0x00000000)
+#define DEF_CPU_POR0_7() (REG32(ADR_CPU_POR0_7)) = (0x00000000)
+#define DEF_CPU_POR8_F() (REG32(ADR_CPU_POR8_F)) = (0x00000000)
+#define DEF_REG_LEN_CTRL() (REG32(ADR_REG_LEN_CTRL)) = (0x00000f0f)
+#define DEF_DMN_READ_BYPASS() (REG32(ADR_DMN_READ_BYPASS)) = (0x0000ffff)
+#define DEF_ALC_RLS_ABORT() (REG32(ADR_ALC_RLS_ABORT)) = (0x00000000)
+#define DEF_DEBUG_CTL() (REG32(ADR_DEBUG_CTL)) = (0x00000000)
+#define DEF_DEBUG_OUT() (REG32(ADR_DEBUG_OUT)) = (0x00000000)
+#define DEF_MMU_STATUS() (REG32(ADR_MMU_STATUS)) = (0x00000000)
+#define DEF_DMN_STATUS() (REG32(ADR_DMN_STATUS)) = (0x00000000)
+#define DEF_TAG_STATUS() (REG32(ADR_TAG_STATUS)) = (0x00000000)
+#define DEF_DMN_MCU_STATUS() (REG32(ADR_DMN_MCU_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_0_STATUS() (REG32(ADR_MB_IDTBL_0_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_1_STATUS() (REG32(ADR_MB_IDTBL_1_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_2_STATUS() (REG32(ADR_MB_IDTBL_2_STATUS)) = (0x00000000)
+#define DEF_MB_IDTBL_3_STATUS() (REG32(ADR_MB_IDTBL_3_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_0_STATUS() (REG32(ADR_PKT_IDTBL_0_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_1_STATUS() (REG32(ADR_PKT_IDTBL_1_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_2_STATUS() (REG32(ADR_PKT_IDTBL_2_STATUS)) = (0x00000000)
+#define DEF_PKT_IDTBL_3_STATUS() (REG32(ADR_PKT_IDTBL_3_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_0_STATUS() (REG32(ADR_DMN_IDTBL_0_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_1_STATUS() (REG32(ADR_DMN_IDTBL_1_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_2_STATUS() (REG32(ADR_DMN_IDTBL_2_STATUS)) = (0x00000000)
+#define DEF_DMN_IDTBL_3_STATUS() (REG32(ADR_DMN_IDTBL_3_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_0_STATUS() (REG32(ADR_MB_NEQID_0_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_1_STATUS() (REG32(ADR_MB_NEQID_1_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_2_STATUS() (REG32(ADR_MB_NEQID_2_STATUS)) = (0x00000000)
+#define DEF_MB_NEQID_3_STATUS() (REG32(ADR_MB_NEQID_3_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_0_STATUS() (REG32(ADR_PKT_NEQID_0_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_1_STATUS() (REG32(ADR_PKT_NEQID_1_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_2_STATUS() (REG32(ADR_PKT_NEQID_2_STATUS)) = (0x00000000)
+#define DEF_PKT_NEQID_3_STATUS() (REG32(ADR_PKT_NEQID_3_STATUS)) = (0x00000000)
+#define DEF_ALC_NOCHG_ID_STATUS() (REG32(ADR_ALC_NOCHG_ID_STATUS)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_0() (REG32(ADR_TAG_SRAM0_F_STATUS_0)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_1() (REG32(ADR_TAG_SRAM0_F_STATUS_1)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_2() (REG32(ADR_TAG_SRAM0_F_STATUS_2)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_3() (REG32(ADR_TAG_SRAM0_F_STATUS_3)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_4() (REG32(ADR_TAG_SRAM0_F_STATUS_4)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_5() (REG32(ADR_TAG_SRAM0_F_STATUS_5)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_6() (REG32(ADR_TAG_SRAM0_F_STATUS_6)) = (0x00000000)
+#define DEF_TAG_SRAM0_F_STATUS_7() (REG32(ADR_TAG_SRAM0_F_STATUS_7)) = (0x00000000)
diff --git a/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h b/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
new file mode 100644
index 00000000000..e15a481ba30
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv6200_reg_sim.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "ssv6200_reg.h"
+#define BANK_COUNT 49
+static const u32 BASE_BANK_SSV6200[] = {
+	SYS_REG_BASE,
+	WBOOT_REG_BASE,
+	TU0_US_REG_BASE,
+	TU1_US_REG_BASE,
+	TU2_US_REG_BASE,
+	TU3_US_REG_BASE,
+	TM0_MS_REG_BASE,
+	TM1_MS_REG_BASE,
+	TM2_MS_REG_BASE,
+	TM3_MS_REG_BASE,
+	MCU_WDT_REG_BASE,
+	SYS_WDT_REG_BASE,
+	GPIO_REG_BASE,
+	SD_REG_BASE,
+	SPI_REG_BASE,
+	CSR_I2C_MST_BASE,
+	UART_REG_BASE,
+	DAT_UART_REG_BASE,
+	INT_REG_BASE,
+	DBG_SPI_REG_BASE,
+	FLASH_SPI_REG_BASE,
+	DMA_REG_BASE,
+	CSR_PMU_BASE,
+	CSR_RTC_BASE,
+	RTC_RAM_BASE,
+	D2_DMA_REG_BASE,
+	HCI_REG_BASE,
+	CO_REG_BASE,
+	EFS_REG_BASE,
+	SMS4_REG_BASE,
+	MRX_REG_BASE,
+	AMPDU_REG_BASE,
+	MT_REG_CSR_BASE,
+	TXQ0_MT_Q_REG_CSR_BASE,
+	TXQ1_MT_Q_REG_CSR_BASE,
+	TXQ2_MT_Q_REG_CSR_BASE,
+	TXQ3_MT_Q_REG_CSR_BASE,
+	TXQ4_MT_Q_REG_CSR_BASE,
+	HIF_INFO_BASE,
+	PHY_RATE_INFO_BASE,
+	MAC_GLB_SET_BASE,
+	BTCX_REG_BASE,
+	MIB_REG_BASE,
+	CBR_A_REG_BASE,
+	MB_REG_BASE,
+	ID_MNG_REG_BASE,
+	CSR_PHY_BASE,
+	CSR_RF_BASE,
+	MMU_REG_BASE,
+	0x00000000
+};
+
+static const char *STR_BANK_SSV6200[] = {
+	"SYS_REG",
+	"WBOOT_REG",
+	"TU0_US_REG",
+	"TU1_US_REG",
+	"TU2_US_REG",
+	"TU3_US_REG",
+	"TM0_MS_REG",
+	"TM1_MS_REG",
+	"TM2_MS_REG",
+	"TM3_MS_REG",
+	"MCU_WDT_REG",
+	"SYS_WDT_REG",
+	"GPIO_REG",
+	"SD_REG",
+	"SPI_REG",
+	"CSR_I2C_MST",
+	"UART_REG",
+	"DAT_UART_REG",
+	"INT_REG",
+	"DBG_SPI_REG",
+	"FLASH_SPI_REG",
+	"DMA_REG",
+	"CSR_PMU",
+	"CSR_RTC",
+	"RTC_RAM",
+	"D2_DMA_REG",
+	"HCI_REG",
+	"CO_REG",
+	"EFS_REG",
+	"SMS4_REG",
+	"MRX_REG",
+	"AMPDU_REG",
+	"MT_REG_CSR",
+	"TXQ0_MT_Q_REG_CSR",
+	"TXQ1_MT_Q_REG_CSR",
+	"TXQ2_MT_Q_REG_CSR",
+	"TXQ3_MT_Q_REG_CSR",
+	"TXQ4_MT_Q_REG_CSR",
+	"HIF_INFO",
+	"PHY_RATE_INFO",
+	"MAC_GLB_SET",
+	"BTCX_REG",
+	"MIB_REG",
+	"CBR_A_REG",
+	"MB_REG",
+	"ID_MNG_REG",
+	"CSR_PHY",
+	"CSR_RF",
+	"MMU_REG",
+	""
+};
+
+static const u32 SIZE_BANK_SSV6200[] = {
+	SYS_REG_BANK_SIZE,
+	WBOOT_REG_BANK_SIZE,
+	TU0_US_REG_BANK_SIZE,
+	TU1_US_REG_BANK_SIZE,
+	TU2_US_REG_BANK_SIZE,
+	TU3_US_REG_BANK_SIZE,
+	TM0_MS_REG_BANK_SIZE,
+	TM1_MS_REG_BANK_SIZE,
+	TM2_MS_REG_BANK_SIZE,
+	TM3_MS_REG_BANK_SIZE,
+	MCU_WDT_REG_BANK_SIZE,
+	SYS_WDT_REG_BANK_SIZE,
+	GPIO_REG_BANK_SIZE,
+	SD_REG_BANK_SIZE,
+	SPI_REG_BANK_SIZE,
+	CSR_I2C_MST_BANK_SIZE,
+	UART_REG_BANK_SIZE,
+	DAT_UART_REG_BANK_SIZE,
+	INT_REG_BANK_SIZE,
+	DBG_SPI_REG_BANK_SIZE,
+	FLASH_SPI_REG_BANK_SIZE,
+	DMA_REG_BANK_SIZE,
+	CSR_PMU_BANK_SIZE,
+	CSR_RTC_BANK_SIZE,
+	RTC_RAM_BANK_SIZE,
+	D2_DMA_REG_BANK_SIZE,
+	HCI_REG_BANK_SIZE,
+	CO_REG_BANK_SIZE,
+	EFS_REG_BANK_SIZE,
+	SMS4_REG_BANK_SIZE,
+	MRX_REG_BANK_SIZE,
+	AMPDU_REG_BANK_SIZE,
+	MT_REG_CSR_BANK_SIZE,
+	TXQ0_MT_Q_REG_CSR_BANK_SIZE,
+	TXQ1_MT_Q_REG_CSR_BANK_SIZE,
+	TXQ2_MT_Q_REG_CSR_BANK_SIZE,
+	TXQ3_MT_Q_REG_CSR_BANK_SIZE,
+	TXQ4_MT_Q_REG_CSR_BANK_SIZE,
+	HIF_INFO_BANK_SIZE,
+	PHY_RATE_INFO_BANK_SIZE,
+	MAC_GLB_SET_BANK_SIZE,
+	BTCX_REG_BANK_SIZE,
+	MIB_REG_BANK_SIZE,
+	CBR_A_REG_BANK_SIZE,
+	MB_REG_BANK_SIZE,
+	ID_MNG_REG_BANK_SIZE,
+	CSR_PHY_BANK_SIZE,
+	CSR_RF_BANK_SIZE,
+	MMU_REG_BANK_SIZE,
+	0x00000000
+};
diff --git a/drivers/net/wireless/ssv6051/include/ssv_cfg.h b/drivers/net/wireless/ssv6051/include/ssv_cfg.h
new file mode 100644
index 00000000000..79b75619936
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv_cfg.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_CFG_H_
+#define _SSV_CFG_H_
+#define SSV6200_HW_CAP_HT 0x00000001
+#define SSV6200_HW_CAP_GF 0x00000002
+#define SSV6200_HW_CAP_2GHZ 0x00000004
+#define SSV6200_HW_CAP_5GHZ 0x00000008
+#define SSV6200_HW_CAP_SECURITY 0x00000010
+#define SSV6200_HT_CAP_SGI_20 0x00000020
+#define SSV6200_HT_CAP_SGI_40 0x00000040
+#define SSV6200_HW_CAP_AP 0x00000080
+#define SSV6200_HW_CAP_P2P 0x00000100
+#define SSV6200_HW_CAP_AMPDU_RX 0x00000200
+#define SSV6200_HW_CAP_AMPDU_TX 0x00000400
+#define SSV6200_HW_CAP_TDLS 0x00000800
+#define EXTERNEL_CONFIG_SUPPORT 64
+struct ssv6xxx_cfg {
+	u32 hw_caps;
+	u32 def_chan;
+	u32 crystal_type;
+	u32 volt_regulator;
+	u32 force_chip_identity;
+	u8 maddr[2][6];
+	u32 n_maddr;
+	u32 use_wpa2_only;
+	u32 ignore_reset_in_ap;
+	u32 r_calbration_result;
+	u32 sar_result;
+	u32 crystal_frequency_offset;
+	u32 tx_power_index_1;
+	u32 tx_power_index_2;
+	u32 chip_identity;
+	u32 wifi_tx_gain_level_gn;
+	u32 wifi_tx_gain_level_b;
+	u32 rssi_ctl;
+	u32 sr_bhvr;
+	u32 configuration[EXTERNEL_CONFIG_SUPPORT + 1][2];
+	u8 firmware_path[128];
+	u8 flash_bin_path[128];
+	u8 mac_address_path[128];
+	u8 mac_output_path[128];
+	u32 ignore_efuse_mac;
+	u32 mac_address_mode;
+};
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h b/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
new file mode 100644
index 00000000000..7fabbe308f9
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv_firmware_version.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_FIRMWARE_VERSION_H_
+#define _SSV_FIRMWARE_VERSION_H_
+static u32 ssv_firmware_version = 16380;
+#define SSV_FIRMWARE_URl "http://192.168.15.30/svn/software/wifi/tag/smac-release-tag/6051.Q0.1009.21.000000/ssv6xxx/smac/firmware"
+#define FIRMWARE_COMPILERHOST "ssv-ThinkPad-X230"
+#define FIRMWARE_COMPILERDATE "11-06-2017-09:17:18"
+#define FIRMWARE_COMPILEROS "linux"
+#define FIRMWARE_COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
+#endif
diff --git a/drivers/net/wireless/ssv6051/include/ssv_version.h b/drivers/net/wireless/ssv6051/include/ssv_version.h
new file mode 100644
index 00000000000..99be5354f78
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/include/ssv_version.h
@@ -0,0 +1,12 @@
+#ifndef _SSV_VERSION_H_
+#define _SSV_VERSION_H_
+
+static u32 ssv_root_version = 16529;
+
+#define SSV_ROOT_URl "http://192.168.15.30/svn/software/project/release/android/box/rk3x28/6051.Q0.1009.21.400401/ssv6xxx"
+#define COMPILERHOST "icomm-buildserver-T320"
+#define COMPILERDATE "12-08-2017-10:34:54"
+#define COMPILEROS "linux"
+#define COMPILEROSARCH "x86_64-linux-gnu-thread-multi"
+
+#endif
diff --git a/drivers/net/wireless/ssv6051/platform-config.mak b/drivers/net/wireless/ssv6051/platform-config.mak
new file mode 100644
index 00000000000..978ea6799c2
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/platform-config.mak
@@ -0,0 +1,97 @@
+ccflags-y += -DCONFIG_SSV6200_CORE
+
+###########################################################################
+# Compiler options                                                        #
+###########################################################################
+
+# Enable -g to help debug. Deassembly from .o to .S would help to track to 
+# the problomatic line from call stack dump.
+#ccflags-y += -g
+ccflags += -Os
+
+############################################################
+# If you change the settings, please change the file synchronization
+# smac\firmware\include\config.h & compiler firmware
+############################################################
+#ccflags-y += -DCONFIG_SSV_CABRIO_A
+ccflags-y += -DCONFIG_SSV_CABRIO_E
+
+#CONFIG_SSV_SUPPORT_BTCX=y
+
+#ccflags-y += -DDEBUG
+ccflags-y += -DCONFIG_SSV6200_CLI_ENABLE
+
+#PADPD
+#ccflags-y += -DCONFIG_SSV_DPD
+
+#ccflags-y += -DCONFIG_SSV_CABRIO_MB_DEBUG
+#ccflags-y += -DCONFIG_SSV6XXX_DEBUGFS
+
+#SDIO
+ccflags-y += -DCONFIG_SSV_TX_LOWTHRESHOLD
+
+ccflags-y += -DCONFIG_FW_ALIGNMENT_CHECK
+ccflags-y += -DCONFIG_PLATFORM_SDIO_OUTPUT_TIMING=3
+ccflags-y += -DCONFIG_PLATFORM_SDIO_BLOCK_SIZE=128
+#ccflags-y += -DMULTI_THREAD_ENCRYPT
+#ccflags-y += -DKTHREAD_BIND
+#ccflags-y += -DROCKCHIP_WIFI_AUTO_SUPPORT
+ccflags-y += -DCONFIG_SSV_RSSI
+ccflags-y += -DCONFIG_SSV_VENDOR_EXT_SUPPORT
+
+############################################################
+# Rate control update for MPDU.
+############################################################
+ccflags-y += -DRATE_CONTROL_REALTIME_UPDATA
+
+#workaround
+#ccflags-y += -DCONFIG_SSV_CABRIO_EXT_PA
+
+############################################################
+# NOTE:
+#    Only one of the following flags could be turned on.
+# It also turned off the following flags. In this case, 
+# pure software security or pure hardware security is used.
+#
+############################################################
+#ccflags-y += -DCONFIG_SSV_SW_ENCRYPT_HW_DECRYPT
+#ccflags-y += -DCONFIG_SSV_HW_ENCRYPT_SW_DECRYPT
+
+# FOR WFA
+#ccflags-y += -DWIFI_CERTIFIED
+
+#ccflags-y += -DCONFIG_SSV_SDIO_EXT_INT
+
+#######################################################
+ccflags-y += -DCONFIG_SSV6200_HAS_RX_WORKQUEUE
+#ccflags-y += -DUSE_THREAD_RX
+ccflags-y += -DUSE_THREAD_TX
+ccflags-y += -DENABLE_AGGREGATE_IN_TIME
+ccflags-y += -DENABLE_INCREMENTAL_AGGREGATION
+
+# Generic decision table applicable to both AP and STA modes.
+ccflags-y += -DUSE_GENERIC_DECI_TBL
+
+#ccflags-y += -DCONFIG_SSV_WAPI
+
+ccflags-y += -DFW_WSID_WATCH_LIST
+#ccflags-y += -DUSE_BATCH_RX
+#ccflags-y += -DCONFIG_IRQ_DEBUG_COUNT
+
+ccflags-y += -DSSV6200_ECO
+#ccflags-y += -DENABLE_WAKE_IO_ISR_WHEN_HCI_ENQUEUE
+ccflags-y += -DHAS_CRYPTO_LOCK
+ccflags-y += -DENABLE_TX_Q_FLOW_CONTROL
+
+#ccflags-y += -DCONFIG_DEBUG_SKB_TIMESTAMP
+
+
+#enable p2p client to parse GO broadcast noa
+#ccflags-y += -DCONFIG_P2P_NOA
+
+#enable rx management frame check
+#ccflags-y += -DCONFIG_RX_MGMT_CHECK
+
+#force SW Broadcast/Multicast decryption
+ccflags-y += -DUSE_MAC80211_DECRYPT_BROADCAST
+
diff --git a/drivers/net/wireless/ssv6051/rules.mak b/drivers/net/wireless/ssv6051/rules.mak
new file mode 100644
index 00000000000..b3262852249
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/rules.mak
@@ -0,0 +1,19 @@
+
+
+$(KMODULE_NAME)-y += $(KERN_SRCS:.c=.o)
+obj-$(CONFIG_SSV6200_CORE) += $(KMODULE_NAME).o
+
+
+.PHONY: all clean install
+
+all:
+	@$(MAKE) -C /lib/modules/$(KVERSION)/build \
+		SUBDIRS=$(KBUILD_DIR) CONFIG_DEBUG_SECTION_MISMATCH=y \
+		modules
+
+clean:
+	@$(MAKE) -C /lib/modules/$(KVERSION)/build SUBDIRS=$(KBUILD_DIR) clean
+
+install:
+	@$(MAKE) INSTALL_MOD_DIR=$(DRVPATH) -C /lib/modules/$(KVERSION)/build \
+	        M=$(KBUILD_DIR) modules_install
diff --git a/drivers/net/wireless/ssv6051/smac/ampdu.c b/drivers/net/wireless/ssv6051/smac/ampdu.c
new file mode 100644
index 00000000000..2b1ebe89228
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ampdu.c
@@ -0,0 +1,2109 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ap.h"
+#include "sec.h"
+#include "ssv_rc_common.h"
+#include "ssv_ht_rc.h"
+extern struct ieee80211_ops ssv6200_ops;
+
+// Hack: redefine MAX_AMPDU_BUF because buf_size here is a 8-bit char
+// and mainline kernel value is 0x100, which overflows
+#undef IEEE80211_MAX_AMPDU_BUF
+#define IEEE80211_MAX_AMPDU_BUF IEEE80211_MAX_AMPDU_BUF_HT
+
+#define BA_WAIT_TIMEOUT (800)
+#define AMPDU_BA_FRAME_LEN (68)
+#define ampdu_skb_hdr(skb) ((struct ieee80211_hdr*)((u8*)((skb)->data)+AMPDU_DELIMITER_LEN))
+#define ampdu_skb_ssn(skb) ((ampdu_skb_hdr(skb)->seq_ctrl)>>SSV_SEQ_NUM_SHIFT)
+#define ampdu_hdr_ssn(hdr) ((hdr)->seq_ctrl>>SSV_SEQ_NUM_SHIFT)
+#undef prn_aggr_dbg
+#define prn_aggr_dbg(fmt,...)
+static void void_func(const char *fmt, ...)
+{
+}
+
+#define prn_aggr_err(fmt,...) \
+    do { \
+        void_func(KERN_ERR fmt, ##__VA_ARGS__);\
+    } while (0)
+#define get_tid_aggr_len(agg_len,tid_data) \
+    ({ \
+        u32 agg_max_num = (tid_data)->agg_num_max; \
+        u32 to_agg_len = (agg_len); \
+        (agg_len >= agg_max_num) ? agg_max_num : to_agg_len; \
+    })
+#define INDEX_PKT_BY_SSN(tid,ssn) \
+    ((tid)->aggr_pkts[(ssn) % SSV_AMPDU_BA_WINDOW_SIZE])
+#define NEXT_PKT_SN(sn) \
+    ({ (sn + 1) % SSV_AMPDU_MAX_SSN; })
+#define INC_PKT_SN(sn) \
+    ({ \
+        sn = NEXT_PKT_SN(sn); \
+        sn; \
+    })
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+static ssize_t ampdu_tx_mib_dump(struct ssv_sta_priv_data *ssv_sta_priv,
+				 char *mib_str, ssize_t length);
+static int _dump_ba_skb(char *buf, int buf_size, struct sk_buff *ba_skb);
+#endif
+static struct sk_buff *_aggr_retry_mpdu(struct ssv_softc *sc,
+					struct AMPDU_TID_st *cur_AMPDU_TID,
+					struct sk_buff_head *retry_queue,
+					u32 max_aggr_len);
+static int _dump_BA_notification(char *buf,
+				 struct ampdu_ba_notify_data *ba_notification);
+static struct sk_buff *_alloc_ampdu_skb(struct ssv_softc *sc,
+					struct AMPDU_TID_st *ampdu_tid,
+					u32 len);
+static bool _sync_ampdu_pkt_arr(struct AMPDU_TID_st *ampdu_tid,
+				struct sk_buff *ampdu_skb, bool retry);
+static void _put_mpdu_to_ampdu(struct sk_buff *ampdu, struct sk_buff *mpdu);
+static void _add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb);
+static u32 _flush_early_ampdu_q(struct ssv_softc *sc,
+				struct AMPDU_TID_st *ampdu_tid);
+static bool _is_skb_q_empty(struct ssv_softc *sc, struct sk_buff *skb);
+static void _aggr_ampdu_tx_q(struct ieee80211_hw *hw,
+			     struct AMPDU_TID_st *ampdu_tid);
+static void _queue_early_ampdu(struct ssv_softc *sc,
+			       struct AMPDU_TID_st *ampdu_tid,
+			       struct sk_buff *ampdu_skb);
+static int _mark_skb_retry(struct SKB_info_st *skb_info, struct sk_buff *skb);
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage)
+{
+	unsigned int timeout;
+	SKB_info *mpdu_skb_info;
+	u16 ssn = 0;
+	struct sk_buff *mpdu = NULL;
+	struct ampdu_hdr_st *ampdu_hdr = NULL;
+	ktime_t current_ktime;
+	ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
+	ssn = ampdu_hdr->ssn[0];
+	mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn);
+	if (mpdu == NULL)
+		return 0;
+	mpdu_skb_info = (SKB_info *) (mpdu->head);
+	current_ktime = ktime_get();
+	timeout =
+	    (unsigned int)
+	    ktime_to_ms(ktime_sub(current_ktime, mpdu_skb_info->timestamp));
+	if (timeout > SKB_DURATION_TIMEOUT_MS) {
+		if (stage == SKB_DURATION_STAGE_TO_SDIO)
+			pr_debug("*a_to_sdio: %ums\n", timeout);
+		else if (stage == SKB_DURATION_STAGE_TX_ENQ)
+			pr_debug("*a_to_txenqueue: %ums\n", timeout);
+		else
+			pr_debug("*a_in_hwq: %ums\n", timeout);
+	}
+	return timeout;
+}
+#endif
+static u8 _cal_ampdu_delm_half_crc(u8 value)
+{
+	u32 c32 = value, v32 = value;
+	c32 ^= (v32 >> 1) | (v32 << 7);
+	c32 ^= (v32 >> 2);
+	if (v32 & 2)
+		c32 ^= (0xC0);
+	c32 ^= ((v32 << 4) & 0x30);
+	return (u8) c32;
+}
+
+static u8 _cal_ampdu_delm_crc(u8 * pointer)
+{
+	u8 crc = 0xCF;
+	crc ^= _cal_ampdu_delm_half_crc(*pointer++);
+	crc =
+	    _cal_ampdu_delm_half_crc(crc) ^ _cal_ampdu_delm_half_crc(*pointer);
+	return ~crc;
+}
+
+static bool ssv6200_ampdu_add_delimiter_and_crc32(struct sk_buff *mpdu)
+{
+	p_AMPDU_DELIMITER delimiter_p;
+	struct ieee80211_hdr *mpdu_hdr;
+	int ret;
+	u32 orig_mpdu_len = mpdu->len;
+	u32 pad = (4 - (orig_mpdu_len % 4)) % 4;
+	mpdu_hdr = (struct ieee80211_hdr *)(mpdu->data);
+	mpdu_hdr->duration_id = AMPDU_TX_NAV_MCS_567;
+	ret = skb_padto(mpdu, mpdu->len + (AMPDU_FCS_LEN + pad));
+	if (ret) {
+		pr_err("Failed to extand skb for aggregation\n");
+		return false;
+	}
+	skb_put(mpdu, AMPDU_FCS_LEN + pad);
+	skb_push(mpdu, AMPDU_DELIMITER_LEN);
+	delimiter_p = (p_AMPDU_DELIMITER) mpdu->data;
+	delimiter_p->reserved = 0;
+	delimiter_p->length = orig_mpdu_len + AMPDU_FCS_LEN;
+	delimiter_p->signature = AMPDU_SIGNATURE;
+	delimiter_p->crc = _cal_ampdu_delm_crc((u8 *) (delimiter_p));
+	return true;
+}
+
+static void ssv6200_ampdu_hw_init(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	u32 temp32;
+	SMAC_REG_READ(sc->sh, ADR_MTX_MISC_EN, &temp32);
+	temp32 |= (0x1 << MTX_AMPDU_CRC_AUTO_SFT);
+	SMAC_REG_WRITE(sc->sh, ADR_MTX_MISC_EN, temp32);
+	SMAC_REG_READ(sc->sh, ADR_MTX_MISC_EN, &temp32);
+}
+
+bool _sync_ampdu_pkt_arr(struct AMPDU_TID_st *ampdu_tid, struct sk_buff *ampdu,
+			 bool retry)
+{
+	struct sk_buff **pp_aggr_pkt;
+	struct sk_buff *p_aggr_pkt;
+	unsigned long flags;
+	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
+	struct sk_buff *mpdu;
+	u32 first_ssn = SSV_ILLEGAL_SN;
+	u32 old_aggr_pkt_num;
+	u32 old_baw_head;
+	u32 sync_num = skb_queue_len(&ampdu_hdr->mpdu_q);
+	bool ret = true;
+	spin_lock_irqsave(&ampdu_tid->pkt_array_lock, flags);
+	old_baw_head = ampdu_tid->ssv_baw_head;
+	old_aggr_pkt_num = ampdu_tid->aggr_pkt_num;
+	ampdu_tid->mib.ampdu_mib_ampdu_counter += 1;
+	ampdu_tid->mib.ampdu_mib_dist[sync_num] += 1;
+	do {
+		if (!retry) {
+			ampdu_tid->mib.ampdu_mib_mpdu_counter += sync_num;
+			mpdu = skb_peek_tail(&ampdu_hdr->mpdu_q);
+			if (mpdu == NULL) {
+				ret = false;
+				break;
+			} else {
+				u32 ssn = ampdu_skb_ssn(mpdu);
+				p_aggr_pkt = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+				if (p_aggr_pkt != NULL) {
+					char msg[256];
+					u32 sn = ampdu_skb_ssn(mpdu);
+					skb_queue_walk(&ampdu_hdr->mpdu_q, mpdu) {
+						sn = ampdu_skb_ssn(mpdu);
+						sprintf(msg, " %d", sn);
+					}
+					prn_aggr_err("ES %d -> %d (%s)\n",
+						     ssn,
+						     ampdu_skb_ssn(p_aggr_pkt),
+						     msg);
+					ret = false;
+					break;
+				}
+			}
+		} else
+			ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1;
+		skb_queue_walk(&ampdu_hdr->mpdu_q, mpdu) {
+			u32 ssn = ampdu_skb_ssn(mpdu);
+			SKB_info *mpdu_skb_info = (SKB_info *) (mpdu->head);
+			if (first_ssn == SSV_ILLEGAL_SN)
+				first_ssn = ssn;
+			pp_aggr_pkt = &INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+			p_aggr_pkt = *pp_aggr_pkt;
+			*pp_aggr_pkt = mpdu;
+			if (!retry)
+				ampdu_tid->aggr_pkt_num++;
+			mpdu_skb_info->ampdu_tx_status = AMPDU_ST_AGGREGATED;
+			if (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN) {
+				ampdu_tid->ssv_baw_head = ssn;
+			}
+			if ((p_aggr_pkt != NULL) && (mpdu != p_aggr_pkt))
+				prn_aggr_err("%d -> %d (H%d, N%d, Q%d)\n",
+					     ssn, ampdu_skb_ssn(p_aggr_pkt),
+					     old_baw_head, old_aggr_pkt_num,
+					     sync_num);
+		}
+	} while (0);
+	spin_unlock_irqrestore(&ampdu_tid->pkt_array_lock, flags);
+	{
+		u32 page_count = (ampdu->len + SSV6200_ALLOC_RSVD);
+		if (page_count & HW_MMU_PAGE_MASK)
+			page_count = (page_count >> HW_MMU_PAGE_SHIFT) + 1;
+		else
+			page_count = page_count >> HW_MMU_PAGE_SHIFT;
+		if (page_count > (SSV6200_PAGE_TX_THRESHOLD / 2))
+			pr_err("AMPDU requires pages %d(%d-%d-%d) exceeds resource limit %d.\n",
+			       page_count, ampdu->len, ampdu_hdr->max_size,
+			       ampdu_hdr->size,
+			       (SSV6200_PAGE_TX_THRESHOLD / 2));
+	}
+	return ret;
+}
+
+struct sk_buff *_aggr_retry_mpdu(struct ssv_softc *sc,
+				 struct AMPDU_TID_st *ampdu_tid,
+				 struct sk_buff_head *retry_queue,
+				 u32 max_aggr_len)
+{
+	struct sk_buff *retry_mpdu;
+	struct sk_buff *new_ampdu_skb;
+	u32 num_retry_mpdu;
+	u32 temp_i;
+	u32 total_skb_size;
+	unsigned long flags;
+	u16 head_ssn = ampdu_tid->ssv_baw_head;
+	struct ampdu_hdr_st *ampdu_hdr;
+	BUG_ON(head_ssn == SSV_ILLEGAL_SN);
+	num_retry_mpdu = skb_queue_len(retry_queue);
+	if (num_retry_mpdu == 0)
+		return NULL;
+	new_ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, max_aggr_len);
+	if (new_ampdu_skb == 0)
+		return NULL;
+	ampdu_hdr = (struct ampdu_hdr_st *)new_ampdu_skb->head;
+	total_skb_size = 0;
+	spin_lock_irqsave(&retry_queue->lock, flags);
+	for (temp_i = 0; temp_i < ampdu_tid->agg_num_max; temp_i++) {
+		struct ieee80211_hdr *mpdu_hdr;
+		u16 mpdu_sn;
+		u16 diff;
+		u32 new_total_skb_size;
+		retry_mpdu = skb_peek(retry_queue);
+		if (retry_mpdu == NULL) {
+			break;
+		}
+		mpdu_hdr = ampdu_skb_hdr(retry_mpdu);
+		mpdu_sn = ampdu_hdr_ssn(mpdu_hdr);
+		diff = SSV_AMPDU_SN_a_minus_b(head_ssn, mpdu_sn);
+		if ((head_ssn != SSV_ILLEGAL_SN)
+		    && (diff > 0)
+		    && (diff <= ampdu_tid->ssv_baw_size)) {
+			struct SKB_info_st *skb_info;
+			prn_aggr_err("Z. release skb (s %d, h %d, d %d)\n",
+				     mpdu_sn, head_ssn, diff);
+			skb_info = (struct SKB_info_st *)(retry_mpdu->head);
+			skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
+			ampdu_tid->mib.ampdu_mib_discard_counter++;
+			continue;
+		}
+		new_total_skb_size = total_skb_size + retry_mpdu->len;
+		if (new_total_skb_size > ampdu_hdr->max_size)
+			break;
+		total_skb_size = new_total_skb_size;
+		retry_mpdu = __skb_dequeue(retry_queue);
+		_put_mpdu_to_ampdu(new_ampdu_skb, retry_mpdu);
+		ampdu_tid->mib.ampdu_mib_retry_counter++;
+	}
+	ampdu_tid->mib.ampdu_mib_aggr_retry_counter += 1;
+	ampdu_tid->mib.ampdu_mib_dist[temp_i] += 1;
+	spin_unlock_irqrestore(&retry_queue->lock, flags);
+	if (ampdu_hdr->mpdu_num == 0) {
+		dev_kfree_skb_any(new_ampdu_skb);
+		return NULL;
+	}
+	return new_ampdu_skb;
+}
+
+static void _add_ampdu_txinfo(struct ssv_softc *sc, struct sk_buff *ampdu_skb)
+{
+	struct ssv6200_tx_desc *tx_desc;
+	ssv6xxx_add_txinfo(sc, ampdu_skb);
+	tx_desc = (struct ssv6200_tx_desc *)ampdu_skb->data;
+	tx_desc->tx_report = 1;
+}
+
+void _send_hci_skb(struct ssv_softc *sc, struct sk_buff *skb, u32 tx_flag)
+{
+	struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *)skb->data;
+	int ret = AMPDU_HCI_SEND(sc->sh, skb, tx_desc->txq_idx, tx_flag);
+	if ((tx_desc->txq_idx > 3) && (ret <= 0)) {
+		prn_aggr_err("BUG!! %d %d\n", tx_desc->txq_idx, ret);
+	}
+}
+
+static void ssv6200_ampdu_add_txinfo_and_send_HCI(struct ssv_softc *sc,
+						  struct sk_buff *ampdu_skb,
+						  u32 tx_flag)
+{
+	_add_ampdu_txinfo(sc, ampdu_skb);
+	_send_hci_skb(sc, ampdu_skb, tx_flag);
+}
+
+static void ssv6200_ampdu_send_retry(struct ieee80211_hw *hw,
+				     AMPDU_TID * cur_ampdu_tid,
+				     struct sk_buff_head
+				     *ampdu_skb_retry_queue_p,
+				     bool send_aggr_tx)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct sk_buff *ampdu_retry_skb;
+	u32 ampdu_skb_retry_queue_len;
+	u32 max_agg_len;
+	u16 lowest_rate;
+	struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
+	ampdu_skb_retry_queue_len = skb_queue_len(ampdu_skb_retry_queue_p);
+	if (ampdu_skb_retry_queue_len == 0)
+		return;
+	ampdu_retry_skb = skb_peek(ampdu_skb_retry_queue_p);
+	lowest_rate = ssv62xx_ht_rate_update(ampdu_retry_skb, sc, rates);
+	max_agg_len = ampdu_max_transmit_length[lowest_rate];
+	if (max_agg_len > 0) {
+		u32 cur_ampdu_max_size = SSV_GET_MAX_AMPDU_SIZE(sc->sh);
+		if (max_agg_len >= cur_ampdu_max_size)
+			max_agg_len = cur_ampdu_max_size;
+		while (ampdu_skb_retry_queue_len > 0) {
+			struct sk_buff *retry_mpdu =
+			    skb_peek(ampdu_skb_retry_queue_p);
+			SKB_info *mpdu_skb_info =
+			    (SKB_info *) (retry_mpdu->head);
+			mpdu_skb_info->lowest_rate = lowest_rate;
+			memcpy(mpdu_skb_info->rates, rates, sizeof(rates));
+			ampdu_retry_skb =
+			    _aggr_retry_mpdu(sc, cur_ampdu_tid,
+					     ampdu_skb_retry_queue_p,
+					     max_agg_len);
+			if (ampdu_retry_skb != NULL) {
+				_sync_ampdu_pkt_arr(cur_ampdu_tid,
+						    ampdu_retry_skb, true);
+				ssv6200_ampdu_add_txinfo_and_send_HCI(sc,
+								      ampdu_retry_skb,
+								      AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL);
+			} else {
+				prn_aggr_err("AMPDU retry failed.\n");
+				return;
+			}
+			ampdu_skb_retry_queue_len =
+			    skb_queue_len(ampdu_skb_retry_queue_p);
+		}
+	} else {
+		struct ieee80211_tx_rate rates[IEEE80211_TX_MAX_RATES];
+		struct ieee80211_tx_info *info =
+		    IEEE80211_SKB_CB(ampdu_retry_skb);
+		memcpy(rates, info->control.rates, sizeof(info->control.rates));
+		while ((ampdu_retry_skb =
+			__skb_dequeue_tail(ampdu_skb_retry_queue_p)) != NULL) {
+			struct ieee80211_tx_info *info =
+			    IEEE80211_SKB_CB(ampdu_retry_skb);
+			info->flags &= ~IEEE80211_TX_CTL_AMPDU;
+			memcpy(info->control.rates, rates,
+			       sizeof(info->control.rates));
+			ssv6xxx_update_txinfo(sc, ampdu_retry_skb);
+			_send_hci_skb(sc, ampdu_retry_skb,
+				      AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL);
+		}
+	}
+}
+
+void ssv6200_ampdu_init(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	ssv6200_ampdu_hw_init(hw);
+	sc->tx.ampdu_tx_group_id = 0;
+#ifdef USE_ENCRYPT_WORK
+	INIT_WORK(&sc->ampdu_tx_encry_work, encry_work);
+	INIT_WORK(&sc->sync_hwkey_work, sync_hw_key_work);
+#endif
+}
+
+void ssv6200_ampdu_deinit(struct ieee80211_hw *hw)
+{
+}
+
+void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw)
+{
+	ieee80211_free_txskb(hw, skb);
+}
+
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+struct mib_dump_data {
+	char *prt_buff;
+	size_t buff_size;
+	size_t prt_len;
+};
+#define AMPDU_TX_MIB_SUMMARY_BUF_SIZE (4096)
+static ssize_t ampdu_tx_mib_summary_read(struct file *file,
+					 char __user * user_buf, size_t count,
+					 loff_t * ppos)
+{
+	struct ssv_sta_priv_data *ssv_sta_priv =
+	    (struct ssv_sta_priv_data *)file->private_data;
+	char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL);
+	ssize_t summary_size;
+	ssize_t ret;
+	if (!summary_buf)
+		return -ENOMEM;
+	summary_size = ampdu_tx_mib_dump(ssv_sta_priv, summary_buf,
+					 AMPDU_TX_MIB_SUMMARY_BUF_SIZE);
+	ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf,
+				      summary_size);
+	kfree(summary_buf);
+	return ret;
+}
+
+static int ampdu_tx_mib_summary_open(struct inode *inode, struct file *file)
+{
+	file->private_data = inode->i_private;
+	return 0;
+}
+
+static const struct file_operations mib_summary_fops = {.read =
+	    ampdu_tx_mib_summary_read,.open = ampdu_tx_mib_summary_open,
+};
+
+static ssize_t ampdu_tx_tid_window_read(struct file *file,
+					char __user * user_buf, size_t count,
+					loff_t * ppos)
+{
+	struct AMPDU_TID_st *ampdu_tid =
+	    (struct AMPDU_TID_st *)file->private_data;
+	char *summary_buf = kzalloc(AMPDU_TX_MIB_SUMMARY_BUF_SIZE, GFP_KERNEL);
+	ssize_t ret;
+	char *prn_ptr = summary_buf;
+	int prt_size;
+	int buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE;
+	int i;
+	struct sk_buff *ba_skb, *tmp_ba_skb;
+	if (!summary_buf)
+		return -ENOMEM;
+	prt_size = snprintf(prn_ptr, buf_size, "\nWMM_TID %d:\n"
+			    "\tWindow:", ampdu_tid->tidno);
+	prn_ptr += prt_size;
+	buf_size -= prt_size;
+	for (i = 0; i < SSV_AMPDU_BA_WINDOW_SIZE; i++) {
+		struct sk_buff *skb = ampdu_tid->aggr_pkts[i];
+		if ((i % 8) == 0) {
+			prt_size = snprintf(prn_ptr, buf_size, "\n\t\t");
+			prn_ptr += prt_size;
+			buf_size -= prt_size;
+		}
+		if (skb == NULL)
+			prt_size = snprintf(prn_ptr, buf_size, " %s", "NULL ");
+		else {
+			struct SKB_info_st *skb_info =
+			    (struct SKB_info_st *)(skb->head);
+			const char status_symbol[] = { 'N',
+				'A',
+				'S',
+				'R',
+				'P',
+				'D'
+			};
+			prt_size =
+			    snprintf(prn_ptr, buf_size, " %4d%c",
+				     ampdu_skb_ssn(skb),
+				     ((skb_info->ampdu_tx_status <=
+				       AMPDU_ST_DONE)
+				      ? status_symbol[skb_info->ampdu_tx_status]
+				      : 'X'));
+		}
+		prn_ptr += prt_size;
+		buf_size -= prt_size;
+	}
+	prt_size =
+	    snprintf(prn_ptr, buf_size, "\n\tEarly aggregated #: %d\n",
+		     ampdu_tid->early_aggr_skb_num);
+	prn_ptr += prt_size;
+	buf_size -= prt_size;
+	prt_size =
+	    snprintf(prn_ptr, buf_size, "\tBAW skb #: %d\n",
+		     ampdu_tid->aggr_pkt_num);
+	prn_ptr += prt_size;
+	buf_size -= prt_size;
+	prt_size =
+	    snprintf(prn_ptr, buf_size, "\tBAW head: %d\n",
+		     ampdu_tid->ssv_baw_head);
+	prn_ptr += prt_size;
+	buf_size -= prt_size;
+	prt_size =
+	    snprintf(prn_ptr, buf_size, "\tState: %d\n", ampdu_tid->state);
+	prn_ptr += prt_size;
+	buf_size -= prt_size;
+	prt_size = snprintf(prn_ptr, buf_size, "\tBA:\n");
+	prn_ptr += prt_size;
+	buf_size -= prt_size;
+	skb_queue_walk_safe(&ampdu_tid->ba_q, ba_skb, tmp_ba_skb) {
+		prt_size = _dump_ba_skb(prn_ptr, buf_size, ba_skb);
+		prn_ptr += prt_size;
+		buf_size -= prt_size;
+	}
+	buf_size = AMPDU_TX_MIB_SUMMARY_BUF_SIZE - buf_size;
+	ret = simple_read_from_buffer(user_buf, count, ppos, summary_buf,
+				      buf_size);
+	kfree(summary_buf);
+	return ret;
+}
+
+static int ampdu_tx_tid_window_open(struct inode *inode, struct file *file)
+{
+	file->private_data = inode->i_private;
+	return 0;
+}
+
+static const struct file_operations tid_window_fops = {.read =
+	    ampdu_tx_tid_window_read,.open = ampdu_tx_tid_window_open,
+};
+
+static int ampdu_tx_mib_reset_open(struct inode *inode, struct file *file)
+{
+	file->private_data = inode->i_private;
+	return 0;
+}
+
+static ssize_t ampdu_tx_mib_reset_read(struct file *file,
+				       char __user * user_buf, size_t count,
+				       loff_t * ppos)
+{
+	char *reset_buf = kzalloc(64, GFP_KERNEL);
+	ssize_t ret;
+	u32 reset_size;
+	if (!reset_buf)
+		return -ENOMEM;
+	reset_size = snprintf(reset_buf, 63, "%d", 0);
+	ret = simple_read_from_buffer(user_buf, count, ppos, reset_buf,
+				      reset_size);
+	kfree(reset_buf);
+	return ret;
+}
+
+static ssize_t ampdu_tx_mib_reset_write(struct file *file,
+					const char __user * buffer,
+					size_t count, loff_t * pos)
+{
+	struct AMPDU_TID_st *ampdu_tid =
+	    (struct AMPDU_TID_st *)file->private_data;
+	memset(&ampdu_tid->mib, 0, sizeof(struct AMPDU_MIB_st));
+	return count;
+}
+
+static const struct file_operations mib_reset_fops
+    = {.read = ampdu_tx_mib_reset_read,
+	.open = ampdu_tx_mib_reset_open,
+	.write = ampdu_tx_mib_reset_write
+};
+
+static void ssv6200_ampdu_tx_init_debugfs(struct ssv_softc *sc,
+					  struct ssv_sta_priv_data
+					  *ssv_sta_priv)
+{
+	struct ssv_sta_info *sta_info = ssv_sta_priv->sta_info;
+	int i;
+	struct dentry *sta_debugfs_dir = sta_info->debugfs_dir;
+	dev_info(sc->dev, "Creating AMPDU TX debugfs.\n");
+	if (sta_debugfs_dir == NULL) {
+		dev_err(sc->dev, "No STA debugfs.\n");
+		return;
+	}
+	debugfs_create_file("ampdu_tx_summary", 00444, sta_debugfs_dir,
+			    ssv_sta_priv, &mib_summary_fops);
+	debugfs_create_u32("total_BA", 00644, sta_debugfs_dir,
+			   &ssv_sta_priv->ampdu_mib_total_BA_counter);
+	for (i = 0; i < WMM_TID_NUM; i++) {
+		char debugfs_name[20];
+		struct dentry *ampdu_tx_debugfs_dir;
+		int j;
+		struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i];
+		struct AMPDU_MIB_st *ampdu_mib = &ampdu_tid->mib;
+		snprintf(debugfs_name, sizeof(debugfs_name), "ampdu_tx_%d", i);
+		ampdu_tx_debugfs_dir = debugfs_create_dir(debugfs_name,
+							  sta_debugfs_dir);
+		if (ampdu_tx_debugfs_dir == NULL) {
+			dev_err(sc->dev,
+				"Failed to create debugfs for AMPDU TX TID %d: %s\n",
+				i, debugfs_name);
+			continue;
+		}
+		ssv_sta_priv->ampdu_tid[i].debugfs_dir = ampdu_tx_debugfs_dir;
+		debugfs_create_file("baw_status", 00444, ampdu_tx_debugfs_dir,
+				    ampdu_tid, &tid_window_fops);
+		debugfs_create_file("reset", 00644, ampdu_tx_debugfs_dir,
+				    ampdu_tid, &mib_reset_fops);
+		debugfs_create_u32("total", 00444, ampdu_tx_debugfs_dir,
+				   &ampdu_mib->ampdu_mib_ampdu_counter);
+		debugfs_create_u32("retry", 00444, ampdu_tx_debugfs_dir,
+				   &ampdu_mib->ampdu_mib_retry_counter);
+		debugfs_create_u32("aggr_retry", 00444, ampdu_tx_debugfs_dir,
+				   &ampdu_mib->ampdu_mib_aggr_retry_counter);
+		debugfs_create_u32("BAR", 00444, ampdu_tx_debugfs_dir,
+				   &ampdu_mib->ampdu_mib_bar_counter);
+		debugfs_create_u32("Discarded", 00444, ampdu_tx_debugfs_dir,
+				   &ampdu_mib->ampdu_mib_discard_counter);
+		debugfs_create_u32("BA", 00444, ampdu_tx_debugfs_dir,
+				   &ampdu_mib->ampdu_mib_BA_counter);
+		debugfs_create_u32("Pass", 00444, ampdu_tx_debugfs_dir,
+				   &ampdu_mib->ampdu_mib_pass_counter);
+		for (j = 0; j <= SSV_AMPDU_aggr_num_max; j++) {
+			char dist_dbg_name[10];
+			snprintf(dist_dbg_name, sizeof(dist_dbg_name),
+				 "aggr_%d", j);
+			debugfs_create_u32(dist_dbg_name, 00444,
+					   ampdu_tx_debugfs_dir,
+					   &ampdu_mib->ampdu_mib_dist[j]);
+		}
+		skb_queue_head_init(&ssv_sta_priv->ampdu_tid[i].ba_q);
+	}
+}
+#endif
+void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw,
+			      struct ieee80211_sta *sta)
+{
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	struct ssv_softc *sc;
+	u32 temp_i;
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	sc = (struct ssv_softc *)hw->priv;
+	for (temp_i = 0; temp_i < WMM_TID_NUM; temp_i++) {
+		ssv_sta_priv->ampdu_tid[temp_i].sta = sta;
+		ssv_sta_priv->ampdu_tid[temp_i].state = AMPDU_STATE_STOP;
+		spin_lock_init(&ssv_sta_priv->ampdu_tid[temp_i].
+			       ampdu_skb_tx_queue_lock);
+		spin_lock_init(&ssv_sta_priv->ampdu_tid[temp_i].pkt_array_lock);
+	}
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	ssv6200_ampdu_tx_init_debugfs(sc, ssv_sta_priv);
+#endif
+}
+
+void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta,
+			    struct ieee80211_hw *hw, u16 * ssn)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	struct AMPDU_TID_st *ampdu_tid;
+	int i;
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	ampdu_tid = &ssv_sta_priv->ampdu_tid[tid];
+	ampdu_tid->ssv_baw_head = SSV_ILLEGAL_SN;
+#ifdef DEBUG_AMPDU_FLUSH
+	pr_debug("Adding %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n",
+	       sta->addr[0], sta->addr[1], sta->addr[2],
+	       sta->addr[3], sta->addr[4], sta->addr[5],
+	       ampdu_tid->tidno, ampdu_tid);
+	{
+		int j;
+		for (j = 0; j <= MAX_TID; j++) {
+			if (sc->tid[j] == 0)
+				break;
+		}
+		if (j == MAX_TID) {
+			dev_err(sc->dev, "No room for new TID.\n");
+		} else
+			sc->tid[j] = ampdu_tid;
+	}
+#endif
+	list_add_tail_rcu(&ampdu_tid->list, &sc->tx.ampdu_tx_que);
+	skb_queue_head_init(&ampdu_tid->ampdu_skb_tx_queue);
+	skb_queue_head_init(&ampdu_tid->early_aggr_ampdu_q);
+	ampdu_tid->early_aggr_skb_num = 0;
+	skb_queue_head_init(&ampdu_tid->ampdu_skb_wait_encry_queue);
+	skb_queue_head_init(&ampdu_tid->retry_queue);
+	skb_queue_head_init(&ampdu_tid->release_queue);
+	for (i = 0;
+	     i <
+	     (sizeof(ampdu_tid->aggr_pkts) / sizeof(ampdu_tid->aggr_pkts[0]));
+	     i++)
+		ampdu_tid->aggr_pkts[i] = 0;
+	ampdu_tid->aggr_pkt_num = 0;
+	ampdu_tid->cur_ampdu_pkt = _alloc_ampdu_skb(sc, ampdu_tid, 0);
+#ifdef AMPDU_CHECK_SKB_SEQNO
+	ssv_sta_priv->ampdu_tid[tid].last_seqno = (-1);
+#endif
+	ssv_sta_priv->ampdu_mib_total_BA_counter = 0;
+	memset(&ssv_sta_priv->ampdu_tid[tid].mib, 0,
+	       sizeof(struct AMPDU_MIB_st));
+	ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_START;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	skb_queue_head_init(&ssv_sta_priv->ampdu_tid[tid].ba_q);
+#endif
+}
+
+void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta,
+				struct ieee80211_hw *hw, u8 buffer_size)
+{
+    struct ssv_softc *sc = hw->priv;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	ssv_sta_priv->ampdu_tid[tid].tidno = tid;
+	ssv_sta_priv->ampdu_tid[tid].sta = sta;
+	ssv_sta_priv->ampdu_tid[tid].agg_num_max = MAX_AGGR_NUM;
+	if (buffer_size > IEEE80211_MAX_AMPDU_BUF) {
+		buffer_size = IEEE80211_MAX_AMPDU_BUF;
+	}
+	dev_info(sc->dev, "AMPDU buffer_size=%d\n", buffer_size);
+	ssv_sta_priv->ampdu_tid[tid].ssv_baw_size = SSV_AMPDU_WINDOW_SIZE;
+	ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_OPERATION;
+}
+
+static void _clear_mpdu_q(struct ieee80211_hw *hw, struct sk_buff_head *q,
+			  bool aggregated_mpdu)
+{
+	struct sk_buff *skb;
+	while (1) {
+		skb = skb_dequeue(q);
+		if (!skb)
+			break;
+		if (aggregated_mpdu)
+			skb_pull(skb, AMPDU_DELIMITER_LEN);
+		ieee80211_tx_status(hw, skb);
+	}
+}
+
+void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta,
+			   struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	if (ssv_sta_priv->ampdu_tid[tid].state == AMPDU_STATE_STOP)
+		return;
+	ssv_sta_priv->ampdu_tid[tid].state = AMPDU_STATE_STOP;
+	dev_dbg(sc->dev, "ssv6200_ampdu_tx_stop\n");
+	if (!list_empty(&sc->tx.ampdu_tx_que)) {
+#ifdef DEBUG_AMPDU_FLUSH
+		{
+			int j;
+			struct AMPDU_TID_st *ampdu_tid =
+			    &ssv_sta_priv->ampdu_tid[tid];
+			for (j = 0; j <= MAX_TID; j++) {
+				if (sc->tid[j] == ampdu_tid)
+					break;
+			}
+			if (j == MAX_TID) {
+				dev_dbg(sc->dev, "No TID found when deleting it.\n");
+			} else
+				sc->tid[j] = NULL;
+			dev_dbg(sc->dev, "Deleting %02X-%02X-%02X-%02X-%02X-%02X TID %d (%p).\n",
+			       sta->addr[0], sta->addr[1], sta->addr[2],
+			       sta->addr[3], sta->addr[4], sta->addr[5],
+			       ampdu_tid->tidno, ampdu_tid);
+		}
+#endif
+		list_del_rcu(&ssv_sta_priv->ampdu_tid[tid].list);
+	}
+	dev_dbg(sc->dev, "clear tx q len=%d\n",
+	       skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue));
+	_clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_tx_queue,
+		      true);
+	dev_dbg(sc->dev, "clear retry q len=%d\n",
+	       skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].retry_queue));
+	_clear_mpdu_q(sc->hw, &ssv_sta_priv->ampdu_tid[tid].retry_queue, true);
+#ifdef USE_ENCRYPT_WORK
+	dev_dbg(sc->dev, "clear encrypt q len=%d\n",
+	       skb_queue_len(&ssv_sta_priv->ampdu_tid[tid].
+			     ampdu_skb_wait_encry_queue));
+	_clear_mpdu_q(sc->hw,
+		      &ssv_sta_priv->ampdu_tid[tid].ampdu_skb_wait_encry_queue,
+		      false);
+#endif
+	if (ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt != NULL) {
+		dev_kfree_skb_any(ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt);
+		ssv_sta_priv->ampdu_tid[tid].cur_ampdu_pkt = NULL;
+	}
+	ssv6200_tx_flow_control((void *)sc,
+				sc->tx.hw_txqid[ssv_sta_priv->ampdu_tid[tid].
+						ac], false, 1000);
+}
+
+static void ssv6200_ampdu_tx_state_stop_func(struct ssv_softc *sc,
+					     struct ieee80211_sta *sta,
+					     struct sk_buff *skb,
+					     struct AMPDU_TID_st *cur_AMPDU_TID)
+{
+	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+	u8 *skb_qos_ctl = ieee80211_get_qos_ctl(hdr);
+	u8 tid_no = skb_qos_ctl[0] & 0xf;
+	if ((sta->ht_cap.ht_supported == true)
+	    && (!!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) {
+		ieee80211_start_tx_ba_session(sta, tid_no, 0);
+		ampdu_db_log("start ampdu_tx(rc) : tid_no = %d\n", tid_no);
+	}
+}
+
+static void ssv6200_ampdu_tx_state_operation_func(struct ssv_softc *sc,
+						  struct ieee80211_sta *sta,
+						  struct sk_buff *skb,
+						  struct AMPDU_TID_st
+						  *cur_AMPDU_TID)
+{
+}
+
+void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta,
+				   struct sk_buff *skb)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)priv;
+	struct ssv_sta_priv_data *ssv_sta_priv =
+	    (struct ssv_sta_priv_data *)sta->drv_priv;
+	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+	u8 *skb_qos_ctl;
+	u8 tid_no;
+	{
+		skb_qos_ctl = ieee80211_get_qos_ctl(hdr);
+		tid_no = skb_qos_ctl[0] & 0xf;
+		switch (ssv_sta_priv->ampdu_tid[tid_no].state) {
+		case AMPDU_STATE_STOP:
+			ssv6200_ampdu_tx_state_stop_func(sc, sta, skb,
+							 &(ssv_sta_priv->
+							   ampdu_tid[tid_no]));
+			break;
+		case AMPDU_STATE_START:
+			break;
+		case AMPDU_STATE_OPERATION:
+			ssv6200_ampdu_tx_state_operation_func(sc, sta, skb,
+							      &(ssv_sta_priv->
+								ampdu_tid
+								[tid_no]));
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+void _put_mpdu_to_ampdu(struct sk_buff *ampdu, struct sk_buff *mpdu)
+{
+	bool is_empty_ampdu = (ampdu->len == 0);
+	unsigned char *data_dest;
+	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
+	BUG_ON(skb_tailroom(ampdu) < mpdu->len);
+	data_dest = skb_tail_pointer(ampdu);
+	skb_put(ampdu, mpdu->len);
+	if (is_empty_ampdu) {
+		struct ieee80211_tx_info *ampdu_info = IEEE80211_SKB_CB(ampdu);
+		struct ieee80211_tx_info *mpdu_info = IEEE80211_SKB_CB(mpdu);
+		SKB_info *mpdu_skb_info = (SKB_info *) (mpdu->head);
+		u32 max_size_for_rate =
+		    ampdu_max_transmit_length[mpdu_skb_info->lowest_rate];
+		BUG_ON(max_size_for_rate == 0);
+		memcpy(ampdu_info, mpdu_info, sizeof(struct ieee80211_tx_info));
+		skb_set_queue_mapping(ampdu, skb_get_queue_mapping(mpdu));
+		ampdu_hdr->first_sn = ampdu_skb_ssn(mpdu);
+		ampdu_hdr->sta = ((struct SKB_info_st *)mpdu->head)->sta;
+		if (ampdu_hdr->max_size > max_size_for_rate)
+			ampdu_hdr->max_size = max_size_for_rate;
+		memcpy(ampdu_hdr->rates, mpdu_skb_info->rates,
+		       sizeof(ampdu_hdr->rates));
+	}
+	memcpy(data_dest, mpdu->data, mpdu->len);
+	__skb_queue_tail(&ampdu_hdr->mpdu_q, mpdu);
+	ampdu_hdr->ssn[ampdu_hdr->mpdu_num++] = ampdu_skb_ssn(mpdu);
+	ampdu_hdr->size += mpdu->len;
+	BUG_ON(ampdu_hdr->size > ampdu_hdr->max_size);
+}
+
+u32 _flush_early_ampdu_q(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid)
+{
+	u32 flushed_ampdu = 0;
+	unsigned long flags;
+	struct sk_buff_head *early_aggr_ampdu_q =
+	    &ampdu_tid->early_aggr_ampdu_q;
+	spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+	while (skb_queue_len(early_aggr_ampdu_q)) {
+		struct sk_buff *head_ampdu;
+		struct ampdu_hdr_st *head_ampdu_hdr;
+		u32 ampdu_aggr_num;
+		head_ampdu = skb_peek(early_aggr_ampdu_q);
+		head_ampdu_hdr = (struct ampdu_hdr_st *)head_ampdu->head;
+		ampdu_aggr_num = skb_queue_len(&head_ampdu_hdr->mpdu_q);
+		if ((SSV_AMPDU_BA_WINDOW_SIZE - ampdu_tid->aggr_pkt_num)
+		    < ampdu_aggr_num)
+			break;
+		if (_sync_ampdu_pkt_arr(ampdu_tid, head_ampdu, false)) {
+			head_ampdu = __skb_dequeue(early_aggr_ampdu_q);
+			ampdu_tid->early_aggr_skb_num -= ampdu_aggr_num;
+#ifdef SSV_AMPDU_FLOW_CONTROL
+			if (ampdu_tid->early_aggr_skb_num
+			    <= SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND) {
+				ssv6200_tx_flow_control((void *)sc,
+							sc->tx.
+							hw_txqid[ampdu_tid->ac],
+							false, 1000);
+			}
+#endif
+			if ((skb_queue_len(early_aggr_ampdu_q) == 0)
+			    && (ampdu_tid->early_aggr_skb_num > 0)) {
+				dev_warn(sc->dev, "Empty early Q w. %d.\n",
+				       ampdu_tid->early_aggr_skb_num);
+			}
+			spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
+					       flags);
+			_send_hci_skb(sc, head_ampdu,
+				      AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
+			spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+			flushed_ampdu++;
+		} else
+			break;
+	}
+	spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
+	return flushed_ampdu;
+}
+
+volatile int max_aggr_num = 24;
+void _aggr_ampdu_tx_q(struct ieee80211_hw *hw, struct AMPDU_TID_st *ampdu_tid)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct sk_buff *ampdu_skb = ampdu_tid->cur_ampdu_pkt;
+	while (skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue)) {
+		u32 aggr_len;
+		struct sk_buff *mpdu_skb;
+		struct ampdu_hdr_st *ampdu_hdr;
+		bool is_aggr_full = false;
+		if (ampdu_skb == NULL) {
+			ampdu_skb = _alloc_ampdu_skb(sc, ampdu_tid, 0);
+			if (ampdu_skb == NULL)
+				break;
+			ampdu_tid->cur_ampdu_pkt = ampdu_skb;
+		}
+		ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
+		aggr_len = skb_queue_len(&ampdu_hdr->mpdu_q);
+		do {
+			struct sk_buff_head *tx_q =
+			    &ampdu_tid->ampdu_skb_tx_queue;
+			unsigned long flags;
+			spin_lock_irqsave(&tx_q->lock, flags);
+			mpdu_skb = skb_peek(&ampdu_tid->ampdu_skb_tx_queue);
+			if (mpdu_skb == NULL) {
+				spin_unlock_irqrestore(&tx_q->lock, flags);
+				break;
+			}
+			if ((mpdu_skb->len + ampdu_hdr->size) >
+			    ampdu_hdr->max_size) {
+				is_aggr_full = true;
+				spin_unlock_irqrestore(&tx_q->lock, flags);
+				break;
+			}
+			mpdu_skb =
+			    __skb_dequeue(&ampdu_tid->ampdu_skb_tx_queue);
+			spin_unlock_irqrestore(&tx_q->lock, flags);
+			_put_mpdu_to_ampdu(ampdu_skb, mpdu_skb);
+		} while (++aggr_len < max_aggr_num);
+		if ((is_aggr_full || (aggr_len >= max_aggr_num))
+		    || ((aggr_len > 0)
+			&& (skb_queue_len(&ampdu_tid->early_aggr_ampdu_q) == 0)
+			&& (ampdu_tid->ssv_baw_head == SSV_ILLEGAL_SN)
+			&& _is_skb_q_empty(sc, ampdu_skb))) {
+			_add_ampdu_txinfo(sc, ampdu_skb);
+			_queue_early_ampdu(sc, ampdu_tid, ampdu_skb);
+			ampdu_tid->cur_ampdu_pkt = ampdu_skb = NULL;
+		}
+		_flush_early_ampdu_q(sc, ampdu_tid);
+	}
+}
+
+void _queue_early_ampdu(struct ssv_softc *sc, struct AMPDU_TID_st *ampdu_tid,
+			struct sk_buff *ampdu_skb)
+{
+	unsigned long flags;
+	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
+	spin_lock_irqsave(&ampdu_tid->early_aggr_ampdu_q.lock, flags);
+	__skb_queue_tail(&ampdu_tid->early_aggr_ampdu_q, ampdu_skb);
+	ampdu_tid->early_aggr_skb_num += skb_queue_len(&ampdu_hdr->mpdu_q);
+#ifdef SSV_AMPDU_FLOW_CONTROL
+	if (ampdu_tid->early_aggr_skb_num >= SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND) {
+		ssv6200_tx_flow_control((void *)sc,
+					sc->tx.hw_txqid[ampdu_tid->ac], true,
+					1000);
+	}
+#endif
+	spin_unlock_irqrestore(&ampdu_tid->early_aggr_ampdu_q.lock, flags);
+}
+
+void _flush_mpdu(struct ssv_softc *sc, struct ieee80211_sta *sta)
+{
+	unsigned long flags;
+	struct ssv_sta_priv_data *ssv_sta_priv =
+	    (struct ssv_sta_priv_data *)sta->drv_priv;
+	int i;
+	for (i = 0;
+	     i <
+	     (sizeof(ssv_sta_priv->ampdu_tid) /
+	      sizeof(ssv_sta_priv->ampdu_tid[0])); i++) {
+		struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[i];
+		struct sk_buff_head *early_aggr_ampdu_q;
+		struct sk_buff *ampdu;
+		struct ampdu_hdr_st *ampdu_hdr;
+		struct sk_buff_head *mpdu_q;
+		struct sk_buff *mpdu;
+		if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+			continue;
+		early_aggr_ampdu_q = &ampdu_tid->early_aggr_ampdu_q;
+		spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+		while ((ampdu = __skb_dequeue(early_aggr_ampdu_q)) != NULL) {
+			ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
+			mpdu_q = &ampdu_hdr->mpdu_q;
+			spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
+					       flags);
+			while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) {
+				_send_hci_skb(sc, mpdu,
+					      AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
+			}
+			ssv6200_ampdu_release_skb(ampdu, sc->hw);
+			spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+		}
+		if (ampdu_tid->cur_ampdu_pkt != NULL) {
+			ampdu_hdr =
+			    (struct ampdu_hdr_st *)ampdu_tid->cur_ampdu_pkt->
+			    head;
+			mpdu_q = &ampdu_hdr->mpdu_q;
+			spin_unlock_irqrestore(&early_aggr_ampdu_q->lock,
+					       flags);
+			while ((mpdu = __skb_dequeue(mpdu_q)) != NULL) {
+				_send_hci_skb(sc, mpdu,
+					      AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL);
+			}
+			ssv6200_ampdu_release_skb(ampdu_tid->cur_ampdu_pkt,
+						  sc->hw);
+			spin_lock_irqsave(&early_aggr_ampdu_q->lock, flags);
+			ampdu_tid->cur_ampdu_pkt = NULL;
+		}
+		spin_unlock_irqrestore(&early_aggr_ampdu_q->lock, flags);
+	}
+}
+
+bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+#ifdef REPORT_TX_STATUS_DIRECTLY
+	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+	struct sk_buff *tx_skb = skb;
+	struct sk_buff *copy_skb = NULL;
+#endif
+	struct SKB_info_st *mpdu_skb_info_p = (SKB_info *) (skb->head);
+	struct ieee80211_sta *sta = mpdu_skb_info_p->sta;
+	struct ssv_sta_priv_data *ssv_sta_priv =
+	    (struct ssv_sta_priv_data *)sta->drv_priv;
+	u8 tidno;
+	struct AMPDU_TID_st *ampdu_tid;
+	if (sta == NULL) {
+		WARN_ON(1);
+		return false;
+	}
+	tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+	ampdu_db_log("tidno = %d\n", tidno);
+	ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno];
+	if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+		return false;
+#ifdef AMPDU_CHECK_SKB_SEQNO
+	{
+		u32 skb_seqno = ((struct ieee80211_hdr *)(skb->data))->seq_ctrl
+		    >> SSV_SEQ_NUM_SHIFT;
+		u32 tid_seqno = ampdu_tid->last_seqno;
+		if ((tid_seqno != (-1))
+		    && (skb_seqno != NEXT_PKT_SN(tid_seqno))) {
+			prn_aggr_err("Non continueous seq no: %d - %d\n",
+				     tid_seqno, skb_seqno);
+			return false;
+		}
+		ampdu_tid->last_seqno = skb_seqno;
+	}
+#endif
+	mpdu_skb_info_p->lowest_rate =
+	    ssv62xx_ht_rate_update(skb, sc, mpdu_skb_info_p->rates);
+	if (ampdu_max_transmit_length[mpdu_skb_info_p->lowest_rate] == 0) {
+		_flush_mpdu(sc, sta);
+		return false;
+	}
+	mpdu_skb_info_p = (SKB_info *) (skb->head);
+	mpdu_skb_info_p->mpdu_retry_counter = 0;
+	mpdu_skb_info_p->ampdu_tx_status = AMPDU_ST_NON_AMPDU;
+	mpdu_skb_info_p->ampdu_tx_final_retry_count = 0;
+	ssv_sta_priv->ampdu_tid[tidno].ac = skb_get_queue_mapping(skb);
+#ifdef REPORT_TX_STATUS_DIRECTLY
+	info->flags |= IEEE80211_TX_STAT_ACK;
+	copy_skb = skb_copy(tx_skb, GFP_ATOMIC);
+	if (!copy_skb) {
+		dev_err(sc->dev, "create TX skb copy failed!\n");
+		return false;
+	}
+	ieee80211_tx_status(sc->hw, tx_skb);
+	skb = copy_skb;
+#endif
+	{
+		bool ret;
+		ret = ssv6200_ampdu_add_delimiter_and_crc32(skb);
+		if (ret == false) {
+			ssv6200_ampdu_release_skb(skb, hw);
+			return false;
+		}
+		skb_queue_tail(&ssv_sta_priv->ampdu_tid[tidno].
+			       ampdu_skb_tx_queue, skb);
+		ssv_sta_priv->ampdu_tid[tidno].timestamp = jiffies;
+	}
+	_aggr_ampdu_tx_q(hw, &ssv_sta_priv->ampdu_tid[tidno]);
+	return true;
+}
+
+u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct AMPDU_TID_st *cur_AMPDU_TID;
+	u32 flushed_ampdu = 0;
+	u32 tid_idx = 0;
+	if (!list_empty(&sc->tx.ampdu_tx_que)) {
+		list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que,
+					list) {
+			tid_idx++;
+#ifdef DEBUG_AMPDU_FLUSH
+			{
+				int i = 0;
+				for (i = 0; i < MAX_TID; i++)
+					if (sc->tid[i] == cur_AMPDU_TID)
+						break;
+				if (i == MAX_TID) {
+					dev_err(sc->dev, "No matching TID (%d) found! %p\n",
+					       tid_idx, cur_AMPDU_TID);
+					continue;
+				}
+			}
+#endif
+			if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION) {
+				struct ieee80211_sta *sta = cur_AMPDU_TID->sta;
+				struct ssv_sta_priv_data *sta_priv =
+				    (struct ssv_sta_priv_data *)sta->drv_priv;
+				dev_dbg(sc->dev, "STA %d TID %d is @%d\n",
+					sta_priv->sta_idx, cur_AMPDU_TID->tidno,
+					cur_AMPDU_TID->state);
+				continue;
+			}
+			if ((cur_AMPDU_TID->state == AMPDU_STATE_OPERATION)
+			    &&
+			    (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q)
+			     == 0)
+			    && (cur_AMPDU_TID->cur_ampdu_pkt != NULL)) {
+				struct ampdu_hdr_st *ampdu_hdr =
+				    (struct ampdu_hdr_st *)(cur_AMPDU_TID->
+							    cur_ampdu_pkt->
+							    head);
+				u32 aggr_len =
+				    skb_queue_len(&ampdu_hdr->mpdu_q);
+				if (aggr_len) {
+					struct sk_buff *ampdu_skb =
+					    cur_AMPDU_TID->cur_ampdu_pkt;
+					cur_AMPDU_TID->cur_ampdu_pkt = NULL;
+					_add_ampdu_txinfo(sc, ampdu_skb);
+					_queue_early_ampdu(sc, cur_AMPDU_TID,
+							   ampdu_skb);
+				}
+			}
+			if (skb_queue_len(&cur_AMPDU_TID->early_aggr_ampdu_q) >
+			    0)
+				flushed_ampdu +=
+				    _flush_early_ampdu_q(sc, cur_AMPDU_TID);
+		}
+	}
+	return flushed_ampdu;
+}
+
+int _dump_BA_notification(char *buf,
+			  struct ampdu_ba_notify_data *ba_notification)
+{
+	int i;
+	char *orig_buf = buf;
+	for (i = 0; i < MAX_AGGR_NUM; i++) {
+		if (ba_notification->seq_no[i] == (u16) (-1))
+			break;
+		buf += sprintf(buf, " %d", ba_notification->seq_no[i]);
+	}
+	return ((size_t)buf - (size_t)orig_buf);
+}
+
+int _dump_ba_skb(char *buf, int buf_size, struct sk_buff *ba_skb)
+{
+	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(ba_skb->data
+							     +
+							     SSV6XXX_RX_DESC_LEN);
+	AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr;
+	u32 ssn = BA_frame->BA_ssn;
+	struct ampdu_ba_notify_data *ba_notification =
+	    (struct ampdu_ba_notify_data *)(ba_skb->data + ba_skb->len
+					    -
+					    sizeof(struct
+						   ampdu_ba_notify_data));
+	int prt_size;
+	prt_size = snprintf(buf, buf_size, "\n\t\t%04d %08X %08X -",
+			    ssn, BA_frame->BA_sn_bit_map[0],
+			    BA_frame->BA_sn_bit_map[1]);
+	buf_size -= prt_size;
+	buf += prt_size;
+	prt_size = prt_size + _dump_BA_notification(buf, ba_notification);
+	return prt_size;
+}
+
+static bool _ssn_to_bit_idx(u32 start_ssn, u32 mpdu_ssn, u32 * word_idx,
+			    u32 * bit_idx)
+{
+	u32 ret_bit_idx, ret_word_idx = 0;
+	s32 diff = mpdu_ssn - start_ssn;
+	if (diff >= 0) {
+		if (diff >= SSV_AMPDU_BA_WINDOW_SIZE) {
+			return false;
+		}
+		ret_bit_idx = diff;
+	} else {
+		diff = -diff;
+		if (diff <= (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) {
+			*word_idx = 0;
+			*bit_idx = 0;
+			return false;
+		}
+		ret_bit_idx = SSV_AMPDU_MAX_SSN - diff;
+	}
+	if (ret_bit_idx >= 32) {
+		ret_bit_idx -= 32;
+		ret_word_idx = 1;
+	}
+	*bit_idx = ret_bit_idx;
+	*word_idx = ret_word_idx;
+	return true;
+}
+
+static bool _inc_bit_idx(u32 ssn_1st, u32 ssn_next, u32 * word_idx,
+			 u32 * bit_idx)
+{
+	u32 ret_word_idx = *word_idx, ret_bit_idx = *bit_idx;
+	s32 diff = (s32) ssn_1st - (s32) ssn_next;
+	if (diff > 0) {
+		if (diff < (SSV_AMPDU_MAX_SSN - SSV_AMPDU_BA_WINDOW_SIZE)) {
+			prn_aggr_err
+			    ("Irrational SN distance in AMPDU: %d %d.\n",
+			     ssn_1st, ssn_next);
+			return false;
+		}
+		diff = SSV_AMPDU_MAX_SSN - diff;
+	} else {
+		diff = -diff;
+	}
+	if (diff > SSV_AMPDU_MAX_SSN)
+		prn_aggr_err("DF %d - %d = %d\n", ssn_1st, ssn_next, diff);
+	ret_bit_idx += diff;
+	if (ret_bit_idx >= 32) {
+		ret_bit_idx -= 32;
+		ret_word_idx++;
+	}
+	*word_idx = ret_word_idx;
+	*bit_idx = ret_bit_idx;
+	return true;
+}
+
+static void _release_frames(struct AMPDU_TID_st *ampdu_tid)
+{
+	u32 head_ssn, head_ssn_before, last_ssn;
+	struct sk_buff **skb;
+	struct SKB_info_st *skb_info;
+	spin_lock_bh(&ampdu_tid->pkt_array_lock);
+	head_ssn_before = ampdu_tid->ssv_baw_head;
+	if (head_ssn_before >= SSV_AMPDU_MAX_SSN) {
+		spin_unlock_bh(&ampdu_tid->pkt_array_lock);
+		prn_aggr_err("l x.x %d\n", head_ssn_before);
+		return;
+	}
+	head_ssn = ampdu_tid->ssv_baw_head;
+	last_ssn = head_ssn;
+	do {
+		skb = &INDEX_PKT_BY_SSN(ampdu_tid, head_ssn);
+		if (*skb == NULL) {
+			head_ssn = SSV_ILLEGAL_SN;
+			{
+				int i;
+				char sn_str[66 * 5] = "";
+				char *str = sn_str;
+				for (i = 0; i < 64; i++)
+					if (ampdu_tid->aggr_pkts[i] != NULL) {
+						str += sprintf(str, "%d ",
+							       ampdu_skb_ssn
+							       (ampdu_tid->
+								aggr_pkts[i]));
+					}
+				*str = 0;
+				if (str == sn_str) {
+				} else
+					prn_aggr_err("ILL %d %d - %d (%s)\n",
+						     head_ssn_before, last_ssn,
+						     ampdu_tid->aggr_pkt_num,
+						     sn_str);
+			}
+			break;
+		}
+		skb_info = (struct SKB_info_st *)((*skb)->head);
+		if ((skb_info->ampdu_tx_status == AMPDU_ST_DONE)
+		    || (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)) {
+			__skb_queue_tail(&ampdu_tid->release_queue, *skb);
+			*skb = NULL;
+			last_ssn = head_ssn;
+			INC_PKT_SN(head_ssn);
+			ampdu_tid->aggr_pkt_num--;
+			if (skb_info->ampdu_tx_status == AMPDU_ST_DROPPED)
+				ampdu_tid->mib.ampdu_mib_discard_counter++;
+		} else {
+			break;
+		}
+	} while (1);
+	ampdu_tid->ssv_baw_head = head_ssn;
+	spin_unlock_bh(&ampdu_tid->pkt_array_lock);
+}
+
+static int _collect_retry_frames(struct AMPDU_TID_st *ampdu_tid)
+{
+	u16 ssn, head_ssn, end_ssn;
+	int num_retry = 0;
+	int timeout_check = 1;
+	unsigned long check_jiffies = jiffies;
+	head_ssn = ampdu_tid->ssv_baw_head;
+	ssn = head_ssn;
+	if (ssn == SSV_ILLEGAL_SN)
+		return 0;
+	end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE) % SSV_AMPDU_MAX_SSN;
+	do {
+		struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+		struct SKB_info_st *skb_info;
+		int timeout_retry = 0;
+		if (skb == NULL)
+			break;
+		skb_info = (SKB_info *) (skb->head);
+		if (timeout_check
+		    && (skb_info->ampdu_tx_status == AMPDU_ST_SENT)) {
+			unsigned long cur_jiffies = jiffies;
+			unsigned long timeout_jiffies = skb_info->aggr_timestamp
+			    + msecs_to_jiffies(BA_WAIT_TIMEOUT);
+			u32 delta_ms;
+			if (time_before(cur_jiffies, timeout_jiffies)) {
+				timeout_check = 0;
+				continue;
+			}
+			_mark_skb_retry(skb_info, skb);
+			delta_ms =
+			    jiffies_to_msecs(cur_jiffies -
+					     skb_info->aggr_timestamp);
+			prn_aggr_err("t S%d-T%d-%d (%u)\n",
+				     ((struct ssv_sta_priv_data *)skb_info->
+				      sta->drv_priv)->sta_idx, ampdu_tid->tidno,
+				     ssn, delta_ms);
+			if (delta_ms > 1000) {
+				prn_aggr_err("Last checktime %lu - %lu = %u\n",
+					     check_jiffies,
+					     ampdu_tid->timestamp,
+					     jiffies_to_msecs(check_jiffies -
+							      ampdu_tid->
+							      timestamp));
+			}
+			timeout_retry = 1;
+		}
+		if (skb_info->ampdu_tx_status == AMPDU_ST_RETRY) {
+			skb_queue_tail(&ampdu_tid->retry_queue, skb);
+			ampdu_tid->mib.ampdu_mib_retry_counter++;
+			num_retry++;
+		}
+		INC_PKT_SN(ssn);
+	} while (ssn != end_ssn);
+	ampdu_tid->timestamp = check_jiffies;
+	return num_retry;
+}
+
+int _mark_skb_retry(struct SKB_info_st *skb_info, struct sk_buff *skb)
+{
+	if (skb_info->mpdu_retry_counter < SSV_AMPDU_retry_counter_max) {
+		if (skb_info->mpdu_retry_counter == 0) {
+			struct ieee80211_hdr *skb_hdr = ampdu_skb_hdr(skb);
+			skb_hdr->frame_control |=
+			    cpu_to_le16(IEEE80211_FCTL_RETRY);
+		}
+		skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
+		skb_info->mpdu_retry_counter++;
+		return 1;
+	} else {
+		skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
+		prn_aggr_err("p %d\n", ampdu_skb_ssn(skb));
+		return 0;
+	}
+}
+
+static u32 _ba_map_walker(struct AMPDU_TID_st *ampdu_tid, u32 start_ssn,
+			  u32 sn_bit_map[2],
+			  struct ampdu_ba_notify_data *ba_notify_data,
+			  u32 * p_acked_num)
+{
+	int i = 0;
+	u32 ssn = ba_notify_data->seq_no[0];
+	u32 word_idx = (-1), bit_idx = (-1);
+	bool found = _ssn_to_bit_idx(start_ssn, ssn, &word_idx, &bit_idx);
+	bool first_found = found;
+	u32 aggr_num = 0;
+	u32 acked_num = 0;
+	if (found && (word_idx >= 2 || bit_idx >= 32))
+		prn_aggr_err("idx error 1: %d %d %d %d\n",
+			     start_ssn, ssn, word_idx, bit_idx);
+	while ((i < MAX_AGGR_NUM) && (ssn < SSV_AMPDU_MAX_SSN)) {
+		u32 cur_ssn;
+		struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+		u32 skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
+		struct SKB_info_st *skb_info;
+		aggr_num++;
+		if (skb_ssn != ssn) {
+			prn_aggr_err("Unmatched SSN packet: %d - %d - %d\n",
+				     ssn, skb_ssn, start_ssn);
+		} else {
+			skb_info = (struct SKB_info_st *)(skb->head);
+			if (found && (sn_bit_map[word_idx] & (1 << bit_idx))) {
+				if (skb_info->ampdu_tx_status != AMPDU_ST_SENT) {
+					pr_err("BA marks a MPDU of status %d!\n",
+					       skb_info->ampdu_tx_status);
+				}
+				skb_info->ampdu_tx_status = AMPDU_ST_DONE;
+				acked_num++;
+			} else {
+				_mark_skb_retry(skb_info, skb);
+			}
+		}
+		cur_ssn = ssn;
+		if (++i >= MAX_AGGR_NUM)
+			break;
+		ssn = ba_notify_data->seq_no[i];
+		if (ssn >= SSV_AMPDU_MAX_SSN)
+			break;
+		if (first_found) {
+			u32 old_word_idx = word_idx, old_bit_idx = bit_idx;
+			found = _inc_bit_idx(cur_ssn, ssn, &word_idx, &bit_idx);
+			if (found && (word_idx >= 2 || bit_idx >= 32)) {
+				prn_aggr_err
+				    ("idx error 2: %d 0x%08X 0X%08X %d %d (%d %d) (%d %d)\n",
+				     start_ssn, sn_bit_map[1], sn_bit_map[0],
+				     cur_ssn, ssn, word_idx, bit_idx,
+				     old_word_idx, old_bit_idx);
+				found = false;
+			} else if (!found) {
+				char strbuf[256];
+				_dump_BA_notification(strbuf, ba_notify_data);
+				prn_aggr_err("SN out-of-order: %d\n%s\n",
+					     start_ssn, strbuf);
+			}
+		} else {
+			found =
+			    _ssn_to_bit_idx(start_ssn, ssn, &word_idx,
+					    &bit_idx);
+			first_found = found;
+			if (found && (word_idx >= 2 || bit_idx >= 32))
+				prn_aggr_err("idx error 3: %d %d %d %d\n",
+					     cur_ssn, ssn, word_idx, bit_idx);
+		}
+	}
+	_release_frames(ampdu_tid);
+	if (p_acked_num != NULL)
+		*p_acked_num = acked_num;
+	return aggr_num;
+}
+
+static void _flush_release_queue(struct ieee80211_hw *hw,
+				 struct sk_buff_head *release_queue)
+{
+	do {
+		struct sk_buff *ampdu_skb = __skb_dequeue(release_queue);
+		struct ieee80211_tx_info *tx_info;
+		struct SKB_info_st *skb_info;
+		if (ampdu_skb == NULL)
+			break;
+		skb_info = (struct SKB_info_st *)(ampdu_skb->head);
+		skb_pull(ampdu_skb, AMPDU_DELIMITER_LEN);
+		tx_info = IEEE80211_SKB_CB(ampdu_skb);
+		ieee80211_tx_info_clear_status(tx_info);
+		tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
+		if (skb_info->ampdu_tx_status == AMPDU_ST_DONE)
+			tx_info->flags |= IEEE80211_TX_STAT_ACK;
+		tx_info->status.ampdu_len = 1;
+		tx_info->status.ampdu_ack_len = 1;
+#ifdef REPORT_TX_STATUS_DIRECTLY
+		dev_kfree_skb_any(ampdu_skb);
+#else
+#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_TX_DATA)
+		ieee80211_tx_status(hw, ampdu_skb);
+#else
+		ieee80211_tx_status_irqsafe(hw, ampdu_skb);
+#endif
+#endif
+	} while (1);
+}
+
+void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+	struct cfg_host_event *host_event = (struct cfg_host_event *)skb->data;
+	struct ampdu_ba_notify_data *ba_notification =
+	    (struct ampdu_ba_notify_data *)&host_event->dat[0];
+	struct ieee80211_hdr *hdr =
+	    (struct ieee80211_hdr *)(ba_notification + 1);
+	struct ssv_softc *sc = hw->priv;
+	struct ieee80211_sta *sta = ssv6xxx_find_sta_by_addr(sc, hdr->addr1);
+	u8 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	char seq_str[256];
+	struct AMPDU_TID_st *ampdu_tid;
+	int i;
+	u16 aggr_num = 0;
+	struct firmware_rate_control_report_data *report_data;
+	if (sta == NULL) {
+		prn_aggr_err
+		    ("NO BA for %d to unmatched STA %02X-%02X-%02X-%02X-%02X-%02X: %s\n",
+		     tidno, hdr->addr1[0], hdr->addr1[1], hdr->addr1[2],
+		     hdr->addr1[3], hdr->addr1[4], hdr->addr1[5], seq_str);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	_dump_BA_notification(seq_str, ba_notification);
+	prn_aggr_err("NO BA for %d to %02X-%02X-%02X-%02X-%02X-%02X: %s\n",
+		     tidno, sta->addr[0], sta->addr[1], sta->addr[2],
+		     sta->addr[3], sta->addr[4], sta->addr[5], seq_str);
+	ampdu_tid = &ssv_sta_priv->ampdu_tid[tidno];
+	if (ampdu_tid->state != AMPDU_STATE_OPERATION) {
+		dev_kfree_skb_any(skb);
+		return;
+	}
+	for (i = 0; i < MAX_AGGR_NUM; i++) {
+		u32 ssn = ba_notification->seq_no[i];
+		struct sk_buff *skb;
+		u32 skb_ssn;
+		struct SKB_info_st *skb_info;
+		if (ssn >= (4096))
+			break;
+		aggr_num++;
+		skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+		skb_ssn = (skb == NULL) ? (-1) : ampdu_skb_ssn(skb);
+		if (skb_ssn != ssn) {
+			prn_aggr_err("Unmatched SSN packet: %d - %d\n", ssn,
+				     skb_ssn);
+			continue;
+		}
+		skb_info = (struct SKB_info_st *)(skb->head);
+		if (skb_info->ampdu_tx_status == AMPDU_ST_SENT) {
+			if (skb_info->mpdu_retry_counter <
+			    SSV_AMPDU_retry_counter_max) {
+				if (skb_info->mpdu_retry_counter == 0) {
+					struct ieee80211_hdr *skb_hdr =
+					    ampdu_skb_hdr(skb);
+					skb_hdr->frame_control |=
+					    cpu_to_le16(IEEE80211_FCTL_RETRY);
+				}
+				skb_info->ampdu_tx_status = AMPDU_ST_RETRY;
+				skb_info->mpdu_retry_counter++;
+			} else {
+				skb_info->ampdu_tx_status = AMPDU_ST_DROPPED;
+				prn_aggr_err("p %d\n", skb_ssn);
+			}
+		} else {
+			prn_aggr_err("S %d %d\n", skb_ssn,
+				     skb_info->ampdu_tx_status);
+		}
+	}
+	_release_frames(ampdu_tid);
+	host_event->h_event = SOC_EVT_RC_AMPDU_REPORT;
+	report_data =
+	    (struct firmware_rate_control_report_data *)&host_event->dat[0];
+	report_data->ampdu_len = aggr_num;
+	report_data->ampdu_ack_len = 0;
+	report_data->wsid = ssv_sta_priv->sta_info->hw_wsid;
+	skb_queue_tail(&sc->rc_report_queue, skb);
+	if (sc->rc_sample_sechedule == 0)
+		queue_work(sc->rc_sample_workqueue, &sc->rc_sample_work);
+}
+
+void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data
+							     +
+							     SSV6XXX_RX_DESC_LEN);
+	AMPDU_BLOCKACK *BA_frame = (AMPDU_BLOCKACK *) hdr;
+	struct ieee80211_sta *sta;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	struct ampdu_ba_notify_data *ba_notification;
+	u32 ssn, aggr_num = 0, acked_num = 0;
+	u8 tid_no;
+	u32 sn_bit_map[2];
+	struct firmware_rate_control_report_data *report_data;
+	HDR_HostEvent *host_evt;
+	sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
+	if (sta == NULL) {
+		if (skb->len > AMPDU_BA_FRAME_LEN) {
+			char strbuf[256];
+			struct ampdu_ba_notify_data *ba_notification =
+			    (struct ampdu_ba_notify_data *)(skb->data + skb->len
+							    -
+							    sizeof(struct
+								   ampdu_ba_notify_data));
+			_dump_BA_notification(strbuf, ba_notification);
+			prn_aggr_err
+			    ("BA from not connected STA (%02X-%02X-%02X-%02X-%02X-%02X) (%s)\n",
+			     BA_frame->ta_addr[0], BA_frame->ta_addr[1],
+			     BA_frame->ta_addr[2], BA_frame->ta_addr[3],
+			     BA_frame->ta_addr[4], BA_frame->ta_addr[5],
+			     strbuf);
+		}
+		dev_kfree_skb_any(skb);
+		return;
+	}
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	ssn = BA_frame->BA_ssn;
+	sn_bit_map[0] = BA_frame->BA_sn_bit_map[0];
+	sn_bit_map[1] = BA_frame->BA_sn_bit_map[1];
+	tid_no = BA_frame->tid_info;
+	ssv_sta_priv->ampdu_mib_total_BA_counter++;
+	if (ssv_sta_priv->ampdu_tid[tid_no].state == AMPDU_STATE_STOP) {
+		prn_aggr_err
+		    ("ssv6200_ampdu_BA_handler state == AMPDU_STATE_STOP.\n");
+		dev_kfree_skb_any(skb);
+		return;
+	}
+	ssv_sta_priv->ampdu_tid[tid_no].mib.ampdu_mib_BA_counter++;
+	if (skb->len <= AMPDU_BA_FRAME_LEN) {
+		prn_aggr_err("b %d\n", ssn);
+		dev_kfree_skb_any(skb);
+		return;
+	}
+	ba_notification =
+	    (struct ampdu_ba_notify_data *)(skb->data + skb->len
+					    -
+					    sizeof(struct
+						   ampdu_ba_notify_data));
+	aggr_num =
+	    _ba_map_walker(&(ssv_sta_priv->ampdu_tid[tid_no]), ssn, sn_bit_map,
+			   ba_notification, &acked_num);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	if (ssv_sta_priv->ampdu_tid[tid_no].debugfs_dir) {
+		struct sk_buff *dup_skb;
+		if (skb_queue_len(&ssv_sta_priv->ampdu_tid[tid_no].ba_q) > 24) {
+			struct sk_buff *ba_skb =
+			    skb_dequeue(&ssv_sta_priv->ampdu_tid[tid_no].ba_q);
+			if (ba_skb)
+				dev_kfree_skb_any(ba_skb);
+		}
+		dup_skb = skb_clone(skb, GFP_ATOMIC);
+		if (dup_skb)
+			skb_queue_tail(&ssv_sta_priv->ampdu_tid[tid_no].ba_q,
+				       dup_skb);
+	}
+#endif
+	skb_trim(skb, skb->len - sizeof(struct ampdu_ba_notify_data));
+	host_evt = (HDR_HostEvent *) skb->data;
+	host_evt->h_event = SOC_EVT_RC_AMPDU_REPORT;
+	report_data =
+	    (struct firmware_rate_control_report_data *)&host_evt->dat[0];
+	memcpy(report_data, ba_notification,
+	       sizeof(struct firmware_rate_control_report_data));
+	report_data->ampdu_len = aggr_num;
+	report_data->ampdu_ack_len = acked_num;
+#ifdef RATE_CONTROL_HT_PERCENTAGE_TRACE
+	if ((acked_num) && (acked_num != aggr_num)) {
+		int i;
+		for (i = 0; i < SSV62XX_TX_MAX_RATES; i++) {
+			if (report_data->rates[i].data_rate == -1)
+				break;
+			if (report_data->rates[i].count == 0)
+                dev_err(sc->dev, "illegal HT report\n");
+
+			dev_dbg(sc->dev, "i=[%d] rate[%d] count[%d]\n", i,
+			       report_data->rates[i].data_rate,
+			       report_data->rates[i].count);
+		}
+		dev_dbg(sc->dev, "AMPDU percentage = %d%% \n",
+		       acked_num * 100 / aggr_num);
+	} else if (acked_num == 0) {
+		dev_dbg(sc->dev, "AMPDU percentage = 0%% aggr_num=%d acked_num=%d\n",
+		       aggr_num, acked_num);
+	}
+#endif
+	skb_queue_tail(&sc->rc_report_queue, skb);
+	if (sc->rc_sample_sechedule == 0)
+		queue_work(sc->rc_sample_workqueue, &sc->rc_sample_work);
+}
+
+static void _postprocess_BA(struct ssv_softc *sc, struct ssv_sta_info *sta_info,
+			    void *param)
+{
+	int j;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	if ((sta_info->sta == NULL)
+	    || ((sta_info->s_flags & STA_FLAG_VALID) == 0))
+		return;
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+	for (j = 0; j < WMM_TID_NUM; j++) {
+		AMPDU_TID *ampdu_tid = &ssv_sta_priv->ampdu_tid[j];
+		if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+			continue;
+		_collect_retry_frames(ampdu_tid);
+		ssv6200_ampdu_send_retry(sc->hw, ampdu_tid,
+					 &ampdu_tid->retry_queue, true);
+		_flush_early_ampdu_q(sc, ampdu_tid);
+		_flush_release_queue(sc->hw, &ampdu_tid->release_queue);
+	}
+}
+
+void ssv6xxx_ampdu_postprocess_BA(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	ssv6xxx_foreach_sta(sc, _postprocess_BA, NULL);
+}
+
+static void ssv6200_hw_set_rx_ba_session(struct ssv_hw *sh, bool on, u8 * ta,
+					 u16 tid, u16 ssn, u8 buf_size)
+{
+	if (on) {
+		u32 u32ta;
+		u32ta = 0;
+		u32ta |= (ta[0] & 0xff) << (8 * 0);
+		u32ta |= (ta[1] & 0xff) << (8 * 1);
+		u32ta |= (ta[2] & 0xff) << (8 * 2);
+		u32ta |= (ta[3] & 0xff) << (8 * 3);
+		SMAC_REG_WRITE(sh, ADR_BA_TA_0, u32ta);
+		u32ta = 0;
+		u32ta |= (ta[4] & 0xff) << (8 * 0);
+		u32ta |= (ta[5] & 0xff) << (8 * 1);
+		SMAC_REG_WRITE(sh, ADR_BA_TA_1, u32ta);
+		SMAC_REG_WRITE(sh, ADR_BA_TID, tid);
+		SMAC_REG_WRITE(sh, ADR_BA_ST_SEQ, ssn);
+		SMAC_REG_WRITE(sh, ADR_BA_SB0, 0);
+		SMAC_REG_WRITE(sh, ADR_BA_SB1, 0);
+		SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0xb);
+	} else {
+		SMAC_REG_WRITE(sh, ADR_BA_CTRL, 0x0);
+	}
+}
+
+void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work)
+{
+	struct ssv_softc
+	*sc = container_of(work, struct ssv_softc, set_ampdu_rx_add_work);
+	ssv6200_hw_set_rx_ba_session(sc->sh, true, sc->ba_ra_addr, sc->ba_tid,
+				     sc->ba_ssn, 64);
+}
+
+void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work)
+{
+	struct ssv_softc *sc = container_of(work, struct ssv_softc,
+					    set_ampdu_rx_del_work);
+	u8 addr[6] = { 0 };
+	ssv6200_hw_set_rx_ba_session(sc->sh, false, addr, 0, 0, 0);
+}
+
+static void _reset_ampdu_mib(struct ssv_softc *sc,
+			     struct ssv_sta_info *sta_info, void *param)
+{
+	struct ieee80211_sta *sta = sta_info->sta;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	int i;
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	for (i = 0; i < WMM_TID_NUM; i++) {
+		ssv_sta_priv->ampdu_tid[i].ampdu_mib_reset = 1;
+	}
+}
+
+void ssv6xxx_ampdu_mib_reset(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	if (sc == NULL)
+		return;
+	ssv6xxx_foreach_sta(sc, _reset_ampdu_mib, NULL);
+}
+
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ssize_t ampdu_tx_mib_dump(struct ssv_sta_priv_data *ssv_sta_priv,
+			  char *mib_str, ssize_t length)
+{
+	ssize_t buf_size = length;
+	ssize_t prt_size;
+	int j;
+	struct ssv_sta_info *ssv_sta = ssv_sta_priv->sta_info;
+	if (ssv_sta->sta == NULL) {
+		prt_size = snprintf(mib_str, buf_size, "\n    NULL STA.\n");
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		goto mib_dump_exit;
+	}
+	for (j = 0; j < WMM_TID_NUM; j++) {
+		int k;
+		struct AMPDU_TID_st *ampdu_tid = &ssv_sta_priv->ampdu_tid[j];
+		struct AMPDU_MIB_st *ampdu_mib = &ampdu_tid->mib;
+		prt_size =
+		    snprintf(mib_str, buf_size, "\n    WMM_TID %d@%d\n", j,
+			     ampdu_tid->state);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		if (ampdu_tid->state != AMPDU_STATE_OPERATION)
+			continue;
+		prt_size =
+		    snprintf(mib_str, buf_size, "        BA window size: %d\n",
+			     ampdu_tid->ssv_baw_size);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size =
+		    snprintf(mib_str, buf_size, "        BA window head: %d\n",
+			     ampdu_tid->ssv_baw_head);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        Sending aggregated #: %d\n",
+				    ampdu_tid->aggr_pkt_num);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size =
+		    snprintf(mib_str, buf_size, "        Waiting #: %d\n",
+			     skb_queue_len(&ampdu_tid->ampdu_skb_tx_queue));
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size =
+		    snprintf(mib_str, buf_size, "        Early aggregated %d\n",
+			     ampdu_tid->early_aggr_skb_num);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        MPDU: %d\n",
+				    ampdu_mib->ampdu_mib_mpdu_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        Passed: %d\n",
+				    ampdu_mib->ampdu_mib_pass_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        Retry: %d\n",
+				    ampdu_mib->ampdu_mib_retry_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        AMPDU: %d\n",
+				    ampdu_mib->ampdu_mib_ampdu_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        Retry AMPDU: %d\n",
+				    ampdu_mib->ampdu_mib_aggr_retry_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        BAR count: %d\n",
+				    ampdu_mib->ampdu_mib_bar_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        Discard count: %d\n",
+				    ampdu_mib->ampdu_mib_discard_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size = snprintf(mib_str, buf_size,
+				    "        BA count: %d\n",
+				    ampdu_mib->ampdu_mib_BA_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size =
+		    snprintf(mib_str, buf_size, "        Total BA count: %d\n",
+			     ssv_sta_priv->ampdu_mib_total_BA_counter);
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		prt_size =
+		    snprintf(mib_str, buf_size, "        Aggr # count:\n");
+		mib_str += prt_size;
+		buf_size -= prt_size;
+		for (k = 0; k <= SSV_AMPDU_aggr_num_max; k++) {
+			prt_size =
+			    snprintf(mib_str, buf_size, "            %d: %d\n",
+				     k, ampdu_mib->ampdu_mib_dist[k]);
+			mib_str += prt_size;
+			buf_size -= prt_size;
+		}
+	}
+ mib_dump_exit:
+	return (length - buf_size);
+}
+
+static void _dump_ampdu_mib(struct ssv_softc *sc, struct ssv_sta_info *sta_info,
+			    void *param)
+{
+	struct mib_dump_data *dump_data = (struct mib_dump_data *)param;
+	struct ieee80211_sta *sta;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	ssize_t buf_size;
+	ssize_t prt_size;
+	char *mib_str = dump_data->prt_buff;
+	if (param == NULL)
+		return;
+	buf_size = dump_data->buff_size - 1;
+	sta = sta_info->sta;
+	if ((sta == NULL) || ((sta_info->s_flags & STA_FLAG_VALID) == 0))
+		return;
+	prt_size = snprintf(mib_str, buf_size,
+			    "STA: %02X-%02X-%02X-%02X-%02X-%02X:\n",
+			    sta->addr[0], sta->addr[1], sta->addr[2],
+			    sta->addr[3], sta->addr[4], sta->addr[5]);
+	mib_str += prt_size;
+	buf_size -= prt_size;
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	prt_size = ampdu_tx_mib_dump(ssv_sta_priv, mib_str, buf_size);
+	mib_str += prt_size;
+	buf_size -= prt_size;
+	dump_data->prt_len = (dump_data->buff_size - 1 - buf_size);
+	dump_data->prt_buff = mib_str;
+	dump_data->buff_size = buf_size;
+}
+
+ssize_t ssv6xxx_ampdu_mib_dump(struct ieee80211_hw *hw, char *mib_str,
+			       ssize_t length)
+{
+	struct ssv_softc *sc = hw->priv;
+	ssize_t buf_size = length - 1;
+	struct mib_dump_data dump_data = { mib_str, buf_size, 0 };
+	if (sc == NULL)
+		return 0;
+	ssv6xxx_foreach_sta(sc, _dump_ampdu_mib, &dump_data);
+	return dump_data.prt_len;
+}
+#endif
+struct sk_buff *_alloc_ampdu_skb(struct ssv_softc *sc,
+				 struct AMPDU_TID_st *ampdu_tid, u32 len)
+{
+	unsigned char *payload_addr;
+	u32 headroom = sc->hw->extra_tx_headroom;
+	u32 offset;
+	u32 cur_max_ampdu_size = SSV_GET_MAX_AMPDU_SIZE(sc->sh);
+	u32 extra_room = sc->sh->tx_desc_len * 2 + 48;
+	u32 max_physical_len = (len
+				&& ((len + extra_room) < cur_max_ampdu_size))
+	    ? (len + extra_room)
+	    : cur_max_ampdu_size;
+	u32 skb_len = max_physical_len + headroom + 3;
+	struct sk_buff *ampdu_skb = __dev_alloc_skb(skb_len, GFP_KERNEL);
+	struct ampdu_hdr_st *ampdu_hdr;
+	if (ampdu_skb == NULL) {
+		dev_err(sc->dev, "AMPDU allocation of size %d(%d) failed\n",
+			len, skb_len);
+		return NULL;
+	}
+	payload_addr = ampdu_skb->data + headroom - sc->sh->tx_desc_len;
+	offset = ((size_t)payload_addr) % 4U;
+	if (offset) {
+		dev_dbg(sc->dev, "Align AMPDU data %d\n", offset);
+		skb_reserve(ampdu_skb, headroom + 4 - offset);
+	} else
+		skb_reserve(ampdu_skb, headroom);
+	ampdu_hdr = (struct ampdu_hdr_st *)ampdu_skb->head;
+	skb_queue_head_init(&ampdu_hdr->mpdu_q);
+	ampdu_hdr->max_size = max_physical_len - extra_room;
+	ampdu_hdr->size = 0;
+	ampdu_hdr->ampdu_tid = ampdu_tid;
+	memset(ampdu_hdr->ssn, 0xFF, sizeof(ampdu_hdr->ssn));
+	ampdu_hdr->mpdu_num = 0;
+	return ampdu_skb;
+}
+
+bool _is_skb_q_empty(struct ssv_softc *sc, struct sk_buff *skb)
+{
+	u32 ac = skb_get_queue_mapping(skb);
+	u32 hw_txqid = sc->tx.hw_txqid[ac];
+	return AMPDU_HCI_Q_EMPTY(sc->sh, hw_txqid);
+}
+
+static u32 _check_timeout(struct AMPDU_TID_st *ampdu_tid)
+{
+	u16 ssn, head_ssn, end_ssn;
+	unsigned long check_jiffies = jiffies;
+	u32 has_retry = 0;
+	head_ssn = ampdu_tid->ssv_baw_head;
+	ssn = head_ssn;
+	if (ssn == SSV_ILLEGAL_SN)
+		return 0;
+	end_ssn = (head_ssn + SSV_AMPDU_BA_WINDOW_SIZE) % SSV_AMPDU_MAX_SSN;
+	do {
+		struct sk_buff *skb = INDEX_PKT_BY_SSN(ampdu_tid, ssn);
+		struct SKB_info_st *skb_info;
+		unsigned long cur_jiffies;
+		unsigned long timeout_jiffies;
+		u32 delta_ms;
+		if (skb == NULL)
+			break;
+		skb_info = (SKB_info *) (skb->head);
+		cur_jiffies = jiffies;
+		timeout_jiffies =
+		    skb_info->aggr_timestamp +
+		    msecs_to_jiffies(BA_WAIT_TIMEOUT);
+		if ((skb_info->ampdu_tx_status != AMPDU_ST_SENT)
+		    || time_before(cur_jiffies, timeout_jiffies))
+			break;
+		delta_ms =
+		    jiffies_to_msecs(cur_jiffies - skb_info->aggr_timestamp);
+		prn_aggr_err("rt S%d-T%d-%d (%u)\n",
+			     ((struct ssv_sta_priv_data *)skb_info->sta->
+			      drv_priv)->sta_idx, ampdu_tid->tidno, ssn,
+			     delta_ms);
+		if (delta_ms > 1000) {
+			prn_aggr_err("Last checktime %lu - %lu = %u\n",
+				     check_jiffies, ampdu_tid->timestamp,
+				     jiffies_to_msecs(check_jiffies -
+						      ampdu_tid->timestamp));
+		}
+		has_retry += _mark_skb_retry(skb_info, skb);
+		INC_PKT_SN(ssn);
+	} while (ssn != end_ssn);
+	ampdu_tid->timestamp = check_jiffies;
+	return has_retry;
+}
+
+void ssv6xxx_ampdu_check_timeout(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct AMPDU_TID_st *cur_AMPDU_TID;
+	if (!list_empty(&sc->tx.ampdu_tx_que)) {
+		list_for_each_entry_rcu(cur_AMPDU_TID, &sc->tx.ampdu_tx_que,
+					list) {
+			u32 has_retry;
+			if (cur_AMPDU_TID->state != AMPDU_STATE_OPERATION)
+				continue;
+			has_retry = _check_timeout(cur_AMPDU_TID);
+			if (has_retry) {
+				_collect_retry_frames(cur_AMPDU_TID);
+				ssv6200_ampdu_send_retry(sc->hw, cur_AMPDU_TID,
+							 &cur_AMPDU_TID->
+							 retry_queue, true);
+			}
+		}
+	}
+}
+
+void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ampdu_hdr_st *ampdu_hdr = (struct ampdu_hdr_st *)ampdu->head;
+	struct sk_buff *mpdu;
+	unsigned long cur_jiffies = jiffies;
+	int i;
+	SKB_info *mpdu_skb_info;
+	u16 ssn;
+	if (ampdu_hdr->ampdu_tid->state != AMPDU_STATE_OPERATION)
+		return;
+	spin_lock_bh(&ampdu_hdr->ampdu_tid->pkt_array_lock);
+	for (i = 0; i < ampdu_hdr->mpdu_num; i++) {
+		ssn = ampdu_hdr->ssn[i];
+		mpdu = INDEX_PKT_BY_SSN(ampdu_hdr->ampdu_tid, ssn);
+		if (mpdu == NULL) {
+			dev_err(sc->dev, "T%d-%d is a NULL MPDU.\n",
+				ampdu_hdr->ampdu_tid->tidno, ssn);
+			continue;
+		}
+		if (ampdu_skb_ssn(mpdu) != ssn) {
+			dev_err(sc->dev, "T%d-%d does not match %d MPDU.\n",
+				ampdu_hdr->ampdu_tid->tidno, ssn,
+				ampdu_skb_ssn(mpdu));
+			continue;
+		}
+		mpdu_skb_info = (SKB_info *) (mpdu->head);
+		mpdu_skb_info->aggr_timestamp = cur_jiffies;
+		mpdu_skb_info->ampdu_tx_status = AMPDU_ST_SENT;
+	}
+	spin_unlock_bh(&ampdu_hdr->ampdu_tid->pkt_array_lock);
+}
diff --git a/drivers/net/wireless/ssv6051/smac/ampdu.h b/drivers/net/wireless/ssv6051/smac/ampdu.h
new file mode 100644
index 00000000000..faa61c4f929
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ampdu.h
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _AMPDU_H_
+#define _AMPDU_H_
+#include <linux/version.h>
+#include <ssv6200_common.h>
+#define Enable_ampdu_debug_log (0)
+#define Enable_AMPDU_Live_Time (0)
+#define Enable_HW_AUTO_CRC_32 (1)
+#define Enable_AMPDU_Rx (1)
+#define Enable_AMPDU_Tx (1)
+#define Enable_AMPDU_FW_Retry (1)
+#define Enable_AMPDU_delay_work (1)
+#define USE_FLUSH_RETRY
+#define USE_AMPDU_TX_STATUS_ARRAY
+#define SSV_AMPDU_FLOW_CONTROL
+#define AMPDU_CHECK_SKB_SEQNO
+#define REPORT_TX_STATUS_DIRECTLY
+#define SSV_AMPDU_aggr_num_max MAX_AGGR_NUM
+#define SSV_AMPDU_seq_num_max (4096)
+#define SSV_AMPDU_retry_counter_max (3)
+#define SSV_AMPDU_tx_group_id_max (64)
+#define SSV_AMPDU_MAX_SSN (4096)
+#define SSV_AMPDU_BA_WINDOW_SIZE (64)
+#define SSV_AMPDU_WINDOW_SIZE (64)
+#define SSV_GET_MAX_AMPDU_SIZE(sh) (((sh)->tx_page_available/(sh)->ampdu_divider) << HW_MMU_PAGE_SHIFT)
+#define SSV_AMPDU_FLOW_CONTROL_UPPER_BOUND (64)
+#define SSV_AMPDU_FLOW_CONTROL_LOWER_BOUND (48)
+#define SSV_AMPDU_timer_period (50)
+#define SSV_AMPDU_TX_TIME_THRESHOLD (50)
+#define SSV_AMPDU_MPDU_LIVE_TIME (SSV_AMPDU_retry_counter_max*8)
+#define SSV_AMPDU_BA_TIME (50)
+#define SSV_ILLEGAL_SN (0xffff)
+#define AMPDU_BUFFER_SIZE (32*1024)
+#define AMPDU_SIGNATURE (0x4E)
+#define AMPDU_DELIMITER_LEN (4)
+#define AMPDU_FCS_LEN (4)
+#define AMPDU_RESERVED_LEN (3)
+#define AMPDU_TX_NAV_MCS_567 (48)
+#define SSV_SEQ_NUM_SHIFT (4)
+#define SSV_RETRY_BIT_SHIFT (11)
+#define IEEE80211_SEQ_SEQ_SHIFT (4)
+#define IEEE80211_AMPDU_BA_LEN (34)
+#define SSV6200_AMPDU_TRIGGER_INDEX 0
+#define SSV_SN_STATUS_Release (0xaa)
+#define SSV_SN_STATUS_Retry (0xbb)
+#define SSV_SN_STATUS_Wait_BA (0xcc)
+#define SSV_SN_STATUS_Discard (0xdd)
+#define AMPDU_HCI_SEND_TAIL_WITH_FLOWCTRL (0)
+#define AMPDU_HCI_SEND_HEAD_WITH_FLOWCTRL (1)
+#define AMPDU_HCI_SEND_TAIL_WITHOUT_FLOWCTRL (2)
+#define AMPDU_HCI_SEND_HEAD_WITHOUT_FLOWCTRL (3)
+#define SSV_BAR_CTRL_ACK_POLICY_NORMAL (0x0000)
+#define SSV_BAR_CTRL_CBMTID_COMPRESSED_BA (0x0004)
+#define SSV_BAR_CTRL_TID_INFO_SHIFT (12)
+#define AMPDU_STATE_START BIT(0)
+#define AMPDU_STATE_OPERATION BIT(1)
+#define AMPDU_STATE_STOP BIT(2)
+typedef enum {
+	AMPDU_REKEY_PAUSE_STOP = 0,
+	AMPDU_REKEY_PAUSE_START,
+	AMPDU_REKEY_PAUSE_ONGOING,
+	AMPDU_REKEY_PAUSE_DEFER,
+	AMPDU_REKEY_PAUSE_HWKEY_SYNC,
+} AMPDU_REKEY_PAUSE_STATE;
+#define SSV_a_minus_b_in_c(a,b,c) (((a)>=(b))?((a)-(b)):((c)-(b)+(a)))
+#define SSV_AMPDU_SN_a_minus_b(a,b) (SSV_a_minus_b_in_c((a), (b), SSV_AMPDU_seq_num_max))
+#define AMPDU_HCI_SEND(_sh,_sk,_q,_flag) (_sh)->hci.hci_ops->hci_tx((_sk), (_q), (_flag))
+#define AMPDU_HCI_Q_EMPTY(_sh,_q) (_sh)->hci.hci_ops->hci_txq_empty((_q))
+struct ampdu_hdr_st {
+	u32 first_sn;
+	struct sk_buff_head mpdu_q;
+	u32 max_size;
+	u32 size;
+	struct AMPDU_TID_st *ampdu_tid;
+	u16 ssn[MAX_AGGR_NUM];
+	u16 mpdu_num;
+	struct fw_rc_retry_params rates[SSV62XX_TX_MAX_RATES];
+	struct ieee80211_sta *sta;
+};
+enum AMPDU_TX_STATUS_E {
+	AMPDU_ST_NON_AMPDU,
+	AMPDU_ST_AGGREGATED,
+	AMPDU_ST_SENT,
+	AMPDU_ST_RETRY,
+	AMPDU_ST_DROPPED,
+	AMPDU_ST_DONE,
+};
+typedef struct AMPDU_MIB_st {
+	u32 ampdu_mib_mpdu_counter;
+	u32 ampdu_mib_retry_counter;
+	u32 ampdu_mib_ampdu_counter;
+	u32 ampdu_mib_aggr_retry_counter;
+	u32 ampdu_mib_bar_counter;
+	u32 ampdu_mib_discard_counter;
+	u32 ampdu_mib_total_BA_counter;
+	u32 ampdu_mib_BA_counter;
+	u32 ampdu_mib_pass_counter;
+	u32 ampdu_mib_dist[SSV_AMPDU_aggr_num_max + 1];
+} AMPDU_MIB;
+typedef struct AMPDU_TID_st {
+	struct list_head list;
+	volatile unsigned long timestamp;
+	u32 tidno;
+	u16 ac;
+	struct ieee80211_sta *sta;
+	u16 ssv_baw_size;
+	u8 agg_num_max;
+	u8 state;
+#ifdef AMPDU_CHECK_SKB_SEQNO
+	u32 last_seqno;
+#endif
+	struct sk_buff_head ampdu_skb_tx_queue;
+	spinlock_t ampdu_skb_tx_queue_lock;
+	struct sk_buff_head retry_queue;
+	struct sk_buff_head release_queue;
+	struct sk_buff *aggr_pkts[SSV_AMPDU_BA_WINDOW_SIZE];
+	volatile u32 aggr_pkt_num;
+	volatile u16 ssv_baw_head;
+	spinlock_t pkt_array_lock;
+	struct sk_buff *cur_ampdu_pkt;
+	struct sk_buff_head early_aggr_ampdu_q;
+	u32 early_aggr_skb_num;
+	struct sk_buff_head ampdu_skb_wait_encry_queue;
+	u32 ampdu_mib_reset;
+	struct AMPDU_MIB_st mib;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct dentry *debugfs_dir;
+	struct sk_buff_head ba_q;
+#endif
+} AMPDU_TID, *p_AMPDU_TID;
+typedef struct AMPDU_DELIMITER_st {
+	u16 reserved:4;
+	u16 length:12;
+	u8 crc;
+	u8 signature;
+} AMPDU_DELIMITER, *p_AMPDU_DELIMITER;
+typedef struct AMPDU_BLOCKACK_st {
+	u16 frame_control;
+	u16 duration;
+	u8 ra_addr[ETH_ALEN];
+	u8 ta_addr[ETH_ALEN];
+	u16 BA_ack_ploicy:1;
+	u16 multi_tid:1;
+	u16 compress_bitmap:1;
+	u16 reserved:9;
+	u16 tid_info:4;
+	u16 BA_fragment_sn:4;
+	u16 BA_ssn:12;
+	u32 BA_sn_bit_map[2];
+} AMPDU_BLOCKACK, *p_AMPDU_BLOCKACK;
+struct ssv_bar {
+	unsigned short frame_control;
+	unsigned short duration;
+	unsigned char ra[6];
+	unsigned char ta[6];
+	unsigned short control;
+	unsigned short start_seq_num;
+} __packed;
+#if Enable_ampdu_debug_log
+#define ampdu_db_log(format, args...) printk("~~~ampdu [%s:%d] "format, __FUNCTION__, __LINE__, ##args)
+#define ampdu_db_log_simple(format, args...) printk(format, ##args)
+#else
+#define ampdu_db_log(...) do {} while (0)
+#define ampdu_db_log_simple(...) do {} while (0)
+#endif
+#if Enable_AMPDU_delay_work
+void ssv6200_ampdu_delayed_work_callback_func(struct work_struct *work);
+#else
+void ssv6200_ampdu_timer_callback_func(unsigned long data);
+#endif
+void ssv6200_ampdu_init(struct ieee80211_hw *hw);
+void ssv6200_ampdu_deinit(struct ieee80211_hw *hw);
+void ssv6200_ampdu_release_skb(struct sk_buff *skb, struct ieee80211_hw *hw);
+void ssv6200_ampdu_tx_start(u16 tid, struct ieee80211_sta *sta,
+			    struct ieee80211_hw *hw, u16 * ssn);
+void ssv6200_ampdu_tx_operation(u16 tid, struct ieee80211_sta *sta,
+				struct ieee80211_hw *hw, u8 buffer_size);
+void ssv6200_ampdu_tx_stop(u16 tid, struct ieee80211_sta *sta,
+			   struct ieee80211_hw *hw);
+bool ssv6200_ampdu_tx_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
+u32 ssv6xxx_ampdu_flush(struct ieee80211_hw *hw);
+void ssv6200_ampdu_timeout_tx(struct ieee80211_hw *hw);
+struct cfg_host_event;
+void ssv6200_ampdu_no_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
+void ssv6200_ampdu_BA_handler(struct ieee80211_hw *hw, struct sk_buff *skb);
+void ssv6200_ampdu_tx_update_state(void *priv, struct ieee80211_sta *sta,
+				   struct sk_buff *skb);
+void ssv6200_ampdu_tx_add_sta(struct ieee80211_hw *hw,
+			      struct ieee80211_sta *sta);
+void ssv6xxx_ampdu_postprocess_BA(struct ieee80211_hw *hw);
+void ssv6xxx_ampdu_check_timeout(struct ieee80211_hw *hw);
+void ssv6xxx_ampdu_sent(struct ieee80211_hw *hw, struct sk_buff *ampdu);
+extern void ssv6xxx_set_ampdu_rx_add_work(struct work_struct *work);
+extern void ssv6xxx_set_ampdu_rx_del_work(struct work_struct *work);
+void ssv6xxx_mib_reset(struct ieee80211_hw *hw);
+ssize_t ssv6xxx_mib_dump(struct ieee80211_hw *hw, char *mib_str,
+			 ssize_t length);
+void encry_work(struct work_struct *work);
+void sync_hw_key_work(struct work_struct *work);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/ap.c b/drivers/net/wireless/ssv6051/smac/ap.c
new file mode 100644
index 00000000000..0f2ba6a31a0
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ap.c
@@ -0,0 +1,598 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200.h>
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <linux/sched.h>
+#include <net/mac80211.h>
+#include <ssv6200.h>
+#include "lib.h"
+#include "dev.h"
+#include "ap.h"
+#include "ssv_rc_common.h"
+#include "ssv_rc.h"
+int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);
+#define IS_EQUAL(a,b) ( (a) == (b) )
+#define SET_BIT(v,b) ( (v) |= (0x01<<b) )
+#define CLEAR_BIT(v,b) ( (v) &= ~(0x01<<b) )
+#define IS_BIT_SET(v,b) ( (v) & (0x01<<(b) ) )
+#define PBUF_BASE_ADDR 0x80000000
+#define PBUF_ADDR_SHIFT 16
+#define PBUF_MapPkttoID(_PKT) (((u32)_PKT&0x0FFF0000)>>PBUF_ADDR_SHIFT)
+#define PBUF_MapIDtoPkt(_ID) (PBUF_BASE_ADDR|((_ID)<<PBUF_ADDR_SHIFT))
+#define SSV6xxx_BEACON_MAX_ALLOCATE_CNT 10
+#define MTX_BCN_PKTID_CH_LOCK_SHIFT MTX_BCN_PKTID_CH_LOCK_SFT
+#define MTX_BCN_CFG_VLD_SHIFT MTX_BCN_CFG_VLD_SFT
+#define MTX_BCN_CFG_VLD_MASK MTX_BCN_CFG_VLD_MSK
+#define AUTO_BCN_ONGOING_MASK MTX_AUTO_BCN_ONGOING_MSK
+#define AUTO_BCN_ONGOING_SHIFT MTX_AUTO_BCN_ONGOING_SFT
+#define MTX_BCN_TIMER_EN_SHIFT MTX_BCN_TIMER_EN_SFT
+#define MTX_TSF_TIMER_EN_SHIFT MTX_TSF_TIMER_EN_SFT
+#define MTX_HALT_MNG_UNTIL_DTIM_SHIFT MTX_HALT_MNG_UNTIL_DTIM_SFT
+#define MTX_BCN_ENABLE_MASK (MTX_BCN_TIMER_EN_I_MSK)
+#define MTX_BCN_PERIOD_SHIFT MTX_BCN_PERIOD_SFT
+#define MTX_DTIM_NUM_SHIFT MTX_DTIM_NUM_SFT
+#define MTX_DTIM_OFST0 MTX_DTIM_OFST0_SFT
+enum ssv6xxx_beacon_type {
+	SSV6xxx_BEACON_0,
+	SSV6xxx_BEACON_1,
+};
+static const u32 ssv6xxx_beacon_adr[] = {
+	ADR_MTX_BCN_CFG0,
+	ADR_MTX_BCN_CFG1,
+};
+
+void ssv6xxx_beacon_reg_lock(struct ssv_softc *sc, bool block)
+{
+	u32 val;
+	val = block << MTX_BCN_PKTID_CH_LOCK_SHIFT;
+#ifdef BEACON_DEBUG
+	printk("ssv6xxx_beacon_reg_lock   val[0x:%08x]\n ", val);
+#endif
+	SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_MISC, val);
+}
+
+void ssv6xxx_beacon_set_info(struct ssv_softc *sc, u8 beacon_interval,
+			     u8 dtim_cnt)
+{
+	u32 val;
+	if (beacon_interval == 0)
+		beacon_interval = 100;
+#ifdef BEACON_DEBUG
+	printk("[A] BSS_CHANGED_BEACON_INT beacon_int[%d] dtim_cnt[%d]\n",
+	       beacon_interval, (dtim_cnt));
+#endif
+	val =
+	    (beacon_interval << MTX_BCN_PERIOD_SHIFT) | (dtim_cnt <<
+							 MTX_DTIM_NUM_SHIFT);
+	SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_PRD, val);
+}
+
+bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable)
+{
+	u32 regval = 0;
+	int ret = 0;
+	if (bEnable && !sc->beacon_usage) {
+		printk
+		    ("[A] Reject to set beacon!!!.        ssv6xxx_beacon_enable bEnable[%d] sc->beacon_usage[%d]\n",
+		     bEnable, sc->beacon_usage);
+		sc->enable_beacon = BEACON_WAITING_ENABLED;
+		return 0;
+	}
+	if ((bEnable && (BEACON_ENABLED & sc->enable_beacon)) ||
+	    (!bEnable && !sc->enable_beacon)) {
+		printk
+		    ("[A] ssv6xxx_beacon_enable bEnable[%d] and sc->enable_beacon[%d] are the same. no need to execute.\n",
+		     bEnable, sc->enable_beacon);
+		if (bEnable) {
+			printk("        Ignore enable beacon cmd!!!!\n");
+			return 0;
+		}
+	}
+	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, &regval);
+#ifdef BEACON_DEBUG
+	printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
+#endif
+	regval &= MTX_BCN_ENABLE_MASK;
+#ifdef BEACON_DEBUG
+	printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
+#endif
+	regval |= (bEnable << MTX_BCN_TIMER_EN_SHIFT);
+	ret = SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval);
+#ifdef BEACON_DEBUG
+	printk("[A] ssv6xxx_beacon_enable read misc reg val [%08x]\n", regval);
+#endif
+	sc->enable_beacon = (bEnable == true) ? BEACON_ENABLED : 0;
+	return ret;
+}
+
+int ssv6xxx_beacon_fill_content(struct ssv_softc *sc, u32 regaddr, u8 * beacon,
+				int size)
+{
+	u32 i, val;
+	u32 *ptr = (u32 *) beacon;
+	size = size / 4;
+	for (i = 0; i < size; i++) {
+		val = (u32) (*(ptr + i));
+#ifdef BEACON_DEBUG
+		printk("[%08x] ", val);
+#endif
+		SMAC_REG_WRITE(sc->sh, regaddr + i * 4, val);
+	}
+#ifdef BEACON_DEBUG
+	printk("\n");
+#endif
+	return 0;
+}
+
+void ssv6xxx_beacon_fill_tx_desc(struct ssv_softc *sc,
+				 struct sk_buff *beacon_skb)
+{
+	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(beacon_skb);
+	struct ssv6200_tx_desc *tx_desc;
+	u16 pb_offset = TXPB_OFFSET;
+	struct ssv_rate_info ssv_rate;
+	skb_push(beacon_skb, pb_offset);
+	tx_desc = (struct ssv6200_tx_desc *)beacon_skb->data;
+	memset(tx_desc, 0, pb_offset);
+	ssv6xxx_rc_hw_rate_idx(sc, tx_info, &ssv_rate);
+	tx_desc->len = beacon_skb->len - pb_offset;
+	tx_desc->c_type = M2_TXREQ;
+	tx_desc->f80211 = 1;
+	tx_desc->ack_policy = 1;
+	tx_desc->hdr_offset = pb_offset;
+	tx_desc->hdr_len = 24;
+	tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len;
+	tx_desc->crate_idx = ssv_rate.crate_hw_idx;
+	tx_desc->drate_idx = ssv_rate.drate_hw_idx;
+	skb_put(beacon_skb, 4);
+}
+
+inline enum ssv6xxx_beacon_type ssv6xxx_beacon_get_valid_reg(struct ssv_softc
+							     *sc)
+{
+	u32 regval = 0;
+	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_MISC, &regval);
+	regval &= MTX_BCN_CFG_VLD_MASK;
+	regval = regval >> MTX_BCN_CFG_VLD_SHIFT;
+	if (regval == 0x2 || regval == 0x0)
+		return SSV6xxx_BEACON_0;
+	else if (regval == 0x1)
+		return SSV6xxx_BEACON_1;
+	else
+		printk("=============>ERROR!!drv_bcn_reg_available\n");
+	return SSV6xxx_BEACON_0;
+}
+
+bool ssv6xxx_beacon_set(struct ssv_softc *sc, struct sk_buff *beacon_skb,
+			int dtim_offset)
+{
+	u32 reg_tx_beacon_adr = ADR_MTX_BCN_CFG0;
+	enum ssv6xxx_beacon_type avl_bcn_type = SSV6xxx_BEACON_0;
+	bool ret = true;
+	int val;
+	ssv6xxx_beacon_reg_lock(sc, 1);
+	avl_bcn_type = ssv6xxx_beacon_get_valid_reg(sc);
+	if (avl_bcn_type == SSV6xxx_BEACON_1)
+		reg_tx_beacon_adr = ADR_MTX_BCN_CFG1;
+#ifdef BEACON_DEBUG
+	printk("[A] ssv6xxx_beacon_set avl_bcn_type[%d]\n", avl_bcn_type);
+#endif
+	do {
+		if (IS_BIT_SET(sc->beacon_usage, avl_bcn_type)) {
+#ifdef BEACON_DEBUG
+			printk
+			    ("[A] beacon has already been set old len[%d] new len[%d]\n",
+			     sc->beacon_info[avl_bcn_type].len,
+			     beacon_skb->len);
+#endif
+			if (sc->beacon_info[avl_bcn_type].len >=
+			    beacon_skb->len) {
+				break;
+			} else {
+				if (false ==
+				    ssv6xxx_pbuf_free(sc,
+						      sc->
+						      beacon_info[avl_bcn_type].
+						      pubf_addr)) {
+#ifdef BEACON_DEBUG
+					printk
+					    ("=============>ERROR!!Intend to allcoate beacon from ASIC fail.\n");
+#endif
+					ret = false;
+					goto out;
+				}
+				CLEAR_BIT(sc->beacon_usage, avl_bcn_type);
+			}
+		}
+		sc->beacon_info[avl_bcn_type].pubf_addr =
+		    ssv6xxx_pbuf_alloc(sc, beacon_skb->len, TX_BUF);
+		sc->beacon_info[avl_bcn_type].len = beacon_skb->len;
+		if (sc->beacon_info[avl_bcn_type].pubf_addr == 0) {
+			ret = false;
+			goto out;
+		}
+		SET_BIT(sc->beacon_usage, avl_bcn_type);
+#ifdef BEACON_DEBUG
+		printk
+		    ("[A] beacon type[%d] usage[%d] allocate new beacon addr[%08x] \n",
+		     avl_bcn_type, sc->beacon_usage,
+		     sc->beacon_info[avl_bcn_type].pubf_addr);
+#endif
+	} while (0);
+	ssv6xxx_beacon_fill_content(sc, sc->beacon_info[avl_bcn_type].pubf_addr,
+				    beacon_skb->data, beacon_skb->len);
+	val =
+	    (PBUF_MapPkttoID(sc->beacon_info[avl_bcn_type].pubf_addr)) |
+	    (dtim_offset << MTX_DTIM_OFST0);
+	SMAC_REG_WRITE(sc->sh, reg_tx_beacon_adr, val);
+#ifdef BEACON_DEBUG
+	printk("[A] update to register reg_tx_beacon_adr[%08x] val[%08x]\n",
+	       reg_tx_beacon_adr, val);
+#endif
+ out:
+	ssv6xxx_beacon_reg_lock(sc, 0);
+	if (sc->beacon_usage && (sc->enable_beacon & BEACON_WAITING_ENABLED)) {
+		printk("[A] enable beacon for BEACON_WAITING_ENABLED flags\n");
+		ssv6xxx_beacon_enable(sc, true);
+	}
+	return ret;
+}
+
+inline bool ssv6xxx_auto_bcn_ongoing(struct ssv_softc *sc)
+{
+	u32 regval;
+	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_MISC, &regval);
+	return ((AUTO_BCN_ONGOING_MASK & regval) >> AUTO_BCN_ONGOING_SHIFT);
+}
+
+void ssv6xxx_beacon_release(struct ssv_softc *sc)
+{
+	int cnt = 10;
+	printk("[A] ssv6xxx_beacon_release Enter\n");
+	cancel_work_sync(&sc->set_tim_work);
+	do {
+		if (ssv6xxx_auto_bcn_ongoing(sc))
+			ssv6xxx_beacon_enable(sc, false);
+		else
+			break;
+		cnt--;
+		if (cnt <= 0)
+			break;
+	} while (1);
+	if (IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_0)) {
+		ssv6xxx_pbuf_free(sc,
+				  sc->beacon_info[SSV6xxx_BEACON_0].pubf_addr);
+		CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_0);
+	}
+	if (IS_BIT_SET(sc->beacon_usage, SSV6xxx_BEACON_1)) {
+		ssv6xxx_pbuf_free(sc,
+				  sc->beacon_info[SSV6xxx_BEACON_1].pubf_addr);
+		CLEAR_BIT(sc->beacon_usage, SSV6xxx_BEACON_1);
+	}
+	sc->enable_beacon = 0;
+	if (sc->beacon_buf) {
+		dev_kfree_skb_any(sc->beacon_buf);
+		sc->beacon_buf = NULL;
+	}
+#ifdef BEACON_DEBUG
+	printk("[A] ssv6xxx_beacon_release leave\n");
+#endif
+}
+
+void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw,
+			   struct ieee80211_vif *vif, bool aid0_bit_set)
+{
+	struct sk_buff *skb;
+	struct sk_buff *old_skb = NULL;
+	u16 tim_offset, tim_length;
+	if (sc == NULL || hw == NULL || vif == NULL) {
+		printk("[Error]........ssv6xxx_beacon_change input error\n");
+		return;
+	}
+	do {
+		skb = ieee80211_beacon_get_tim(hw, vif,
+					       &tim_offset, &tim_length);
+		if (skb == NULL) {
+			printk("[Error]........skb is NULL\n");
+			break;
+		}
+		if (tim_offset && tim_length >= 6) {
+			skb->data[tim_offset + 2] = 0;
+			if (aid0_bit_set)
+				skb->data[tim_offset + 4] |= 1;
+			else
+				skb->data[tim_offset + 4] &= ~1;
+		}
+#ifdef BEACON_DEBUG
+		printk("[A] beacon len [%d] tim_offset[%d]\n", skb->len,
+		       tim_offset);
+#endif
+		ssv6xxx_beacon_fill_tx_desc(sc, skb);
+#ifdef BEACON_DEBUG
+		printk("[A] beacon len [%d] tim_offset[%d]\n", skb->len,
+		       tim_offset);
+#endif
+		if (sc->beacon_buf) {
+			if (memcmp
+			    (sc->beacon_buf->data, skb->data,
+			     (skb->len - FCS_LEN)) == 0) {
+				old_skb = skb;
+				break;
+			} else {
+				old_skb = sc->beacon_buf;
+				sc->beacon_buf = skb;
+			}
+		} else {
+			sc->beacon_buf = skb;
+		}
+		tim_offset += 2;
+		if (ssv6xxx_beacon_set(sc, skb, tim_offset)) {
+			u8 dtim_cnt = vif->bss_conf.dtim_period - 1;
+			if (sc->beacon_dtim_cnt != dtim_cnt) {
+				sc->beacon_dtim_cnt = dtim_cnt;
+#ifdef BEACON_DEBUG
+				printk("[A] beacon_dtim_cnt [%d]\n",
+				       sc->beacon_dtim_cnt);
+#endif
+				ssv6xxx_beacon_set_info(sc, sc->beacon_interval,
+							sc->beacon_dtim_cnt);
+			}
+		}
+	} while (0);
+	if (old_skb)
+		dev_kfree_skb_any(old_skb);
+}
+
+void ssv6200_set_tim_work(struct work_struct *work)
+{
+	struct ssv_softc *sc =
+	    container_of(work, struct ssv_softc, set_tim_work);
+#ifdef BROADCAST_DEBUG
+	printk("%s() enter\n", __FUNCTION__);
+#endif
+	ssv6xxx_beacon_change(sc, sc->hw, sc->ap_vif, sc->aid0_bit_set);
+#ifdef BROADCAST_DEBUG
+	printk("%s() leave\n", __FUNCTION__);
+#endif
+}
+
+int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq)
+{
+	u32 len;
+	unsigned long flags;
+	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+	len = bcast_txq->cur_qsize;
+	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+	return len;
+}
+
+struct sk_buff *ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq,
+				      u8 * remain_len)
+{
+	struct sk_buff *skb = NULL;
+	unsigned long flags;
+	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+	if (bcast_txq->cur_qsize) {
+		bcast_txq->cur_qsize--;
+		if (remain_len)
+			*remain_len = bcast_txq->cur_qsize;
+		skb = __skb_dequeue(&bcast_txq->qhead);
+	}
+	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+	return skb;
+}
+
+int ssv6200_bcast_enqueue(struct ssv_softc *sc,
+			  struct ssv6xxx_bcast_txq *bcast_txq,
+			  struct sk_buff *skb)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+	if (bcast_txq->cur_qsize >= SSV6200_MAX_BCAST_QUEUE_LEN) {
+		struct sk_buff *old_skb;
+		old_skb = __skb_dequeue(&bcast_txq->qhead);
+		bcast_txq->cur_qsize--;
+		ssv6xxx_txbuf_free_skb(old_skb, (void *)sc);
+		printk("[B] ssv6200_bcast_enqueue - remove oldest queue\n");
+	}
+	__skb_queue_tail(&bcast_txq->qhead, skb);
+	bcast_txq->cur_qsize++;
+	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+	return bcast_txq->cur_qsize;
+}
+
+void ssv6200_bcast_flush(struct ssv_softc *sc,
+			 struct ssv6xxx_bcast_txq *bcast_txq)
+{
+	struct sk_buff *skb;
+	unsigned long flags;
+#ifdef BCAST_DEBUG
+	printk("ssv6200_bcast_flush\n");
+#endif
+	spin_lock_irqsave(&bcast_txq->txq_lock, flags);
+	while (bcast_txq->cur_qsize > 0) {
+		skb = __skb_dequeue(&bcast_txq->qhead);
+		bcast_txq->cur_qsize--;
+		ssv6xxx_txbuf_free_skb(skb, (void *)sc);
+	}
+	spin_unlock_irqrestore(&bcast_txq->txq_lock, flags);
+}
+
+static int queue_block_cnt = 0;
+void ssv6200_bcast_tx_work(struct work_struct *work)
+{
+	struct ssv_softc *sc =
+	    container_of(work, struct ssv_softc, bcast_tx_work.work);
+	struct sk_buff *skb;
+	int i;
+	u8 remain_size;
+	unsigned long flags;
+	bool needtimer = true;
+	long tmo = sc->bcast_interval;
+	spin_lock_irqsave(&sc->ps_state_lock, flags);
+	do {
+#ifdef BCAST_DEBUG
+		printk
+		    ("[B] bcast_timer: hw_mng_used[%d] HCI_TXQ_EMPTY[%d] bcast_queue_len[%d].....................\n",
+		     sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4),
+		     ssv6200_bcast_queue_len(&sc->bcast_txq));
+#endif
+		if (sc->hw_mng_used != 0 || false == HCI_TXQ_EMPTY(sc->sh, 4)) {
+#ifdef BCAST_DEBUG
+			printk
+			    ("HW queue still have frames insdide. skip this one hw_mng_used[%d] bEmptyTXQ4[%d]\n",
+			     sc->hw_mng_used, HCI_TXQ_EMPTY(sc->sh, 4));
+#endif
+			queue_block_cnt++;
+			if (queue_block_cnt > 5) {
+				queue_block_cnt = 0;
+				ssv6200_bcast_flush(sc, &sc->bcast_txq);
+				needtimer = false;
+			}
+			break;
+		}
+		queue_block_cnt = 0;
+		for (i = 0; i < SSV6200_ID_MANAGER_QUEUE; i++) {
+			skb =
+			    ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size);
+			if (!skb) {
+				needtimer = false;
+				break;
+			}
+			if ((0 != remain_size) &&
+			    (SSV6200_ID_MANAGER_QUEUE - 1) != i) {
+				struct ieee80211_hdr *hdr;
+				struct ssv6200_tx_desc *tx_desc =
+				    (struct ssv6200_tx_desc *)skb->data;
+				hdr =
+				    (struct ieee80211_hdr *)((u8 *) tx_desc +
+							     tx_desc->
+							     hdr_offset);
+				hdr->frame_control |=
+				    cpu_to_le16(IEEE80211_FCTL_MOREDATA);
+			}
+#ifdef BCAST_DEBUG
+			printk("[B] bcast_timer:tx remain_size[%d] i[%d]\n",
+			       remain_size, i);
+#endif
+			spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+			if (HCI_SEND(sc->sh, skb, 4) < 0) {
+				printk("bcast_timer send fail!!!!!!! \n");
+				ssv6xxx_txbuf_free_skb(skb, (void *)sc);
+				BUG_ON(1);
+			}
+			spin_lock_irqsave(&sc->ps_state_lock, flags);
+		}
+	} while (0);
+	if (needtimer) {
+#ifdef BCAST_DEBUG
+		printk
+		    ("[B] bcast_timer:need more timer to tx bcast frame time[%d]\n",
+		     sc->bcast_interval);
+#endif
+		queue_delayed_work(sc->config_wq, &sc->bcast_tx_work, tmo);
+	} else {
+#ifdef BCAST_DEBUG
+		printk("[B] bcast_timer: ssv6200_bcast_stop\n");
+#endif
+		ssv6200_bcast_stop(sc);
+	}
+	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+#ifdef BCAST_DEBUG
+	printk("[B] bcast_timer: leave.....................\n");
+#endif
+}
+
+void ssv6200_bcast_start_work(struct work_struct *work)
+{
+	struct ssv_softc *sc =
+	    container_of(work, struct ssv_softc, bcast_start_work);
+#ifdef BCAST_DEBUG
+	printk("[B] ssv6200_bcast_start_work==\n");
+#endif
+	sc->bcast_interval = (sc->beacon_dtim_cnt + 1) *
+	    (sc->beacon_interval + 20) * HZ / 1000;
+	if (!sc->aid0_bit_set) {
+		sc->aid0_bit_set = true;
+		ssv6xxx_beacon_change(sc, sc->hw, sc->ap_vif, sc->aid0_bit_set);
+		queue_delayed_work(sc->config_wq,
+				   &sc->bcast_tx_work, sc->bcast_interval);
+#ifdef BCAST_DEBUG
+		printk("[B] bcast_start_work: Modify timer to DTIM[%d]ms==\n",
+		       (sc->beacon_dtim_cnt + 1) * (sc->beacon_interval + 20));
+#endif
+	}
+}
+
+void ssv6200_bcast_stop_work(struct work_struct *work)
+{
+	struct ssv_softc *sc =
+	    container_of(work, struct ssv_softc, bcast_stop_work.work);
+	long tmo = HZ / 100;
+#ifdef BCAST_DEBUG
+	printk("[B] ssv6200_bcast_stop_work\n");
+#endif
+	if (sc->aid0_bit_set) {
+		if (0 == ssv6200_bcast_queue_len(&sc->bcast_txq)) {
+			cancel_delayed_work_sync(&sc->bcast_tx_work);
+			sc->aid0_bit_set = false;
+			ssv6xxx_beacon_change(sc, sc->hw,
+					      sc->ap_vif, sc->aid0_bit_set);
+#ifdef BCAST_DEBUG
+			printk("remove group bit in DTIM\n");
+#endif
+		} else {
+#ifdef BCAST_DEBUG
+			printk
+			    ("bcast_stop_work: bcast queue still have data. just modify timer to 10ms\n");
+#endif
+			queue_delayed_work(sc->config_wq,
+					   &sc->bcast_tx_work, tmo);
+		}
+	}
+}
+
+void ssv6200_bcast_stop(struct ssv_softc *sc)
+{
+	queue_delayed_work(sc->config_wq,
+			   &sc->bcast_stop_work,
+			   sc->beacon_interval * HZ / 1024);
+}
+
+void ssv6200_bcast_start(struct ssv_softc *sc)
+{
+	queue_work(sc->config_wq, &sc->bcast_start_work);
+}
+
+void ssv6200_release_bcast_frame_res(struct ssv_softc *sc,
+				     struct ieee80211_vif *vif)
+{
+	unsigned long flags;
+	struct ssv_vif_priv_data *priv_vif =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	spin_lock_irqsave(&sc->ps_state_lock, flags);
+	priv_vif->sta_asleep_mask = 0;
+	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+	cancel_work_sync(&sc->bcast_start_work);
+	cancel_delayed_work_sync(&sc->bcast_stop_work);
+	ssv6200_bcast_flush(sc, &sc->bcast_txq);
+	cancel_delayed_work_sync(&sc->bcast_tx_work);
+}
diff --git a/drivers/net/wireless/ssv6051/smac/ap.h b/drivers/net/wireless/ssv6051/smac/ap.h
new file mode 100644
index 00000000000..93b5275715b
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ap.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _AP_H_
+#define _AP_H_
+#define BEACON_WAITING_ENABLED 1<<0
+#define BEACON_ENABLED 1<<1
+void ssv6xxx_beacon_change(struct ssv_softc *sc, struct ieee80211_hw *hw,
+			   struct ieee80211_vif *vif, bool aid0_bit_set);
+void ssv6xxx_beacon_set_info(struct ssv_softc *sc, u8 beacon_interval,
+			     u8 dtim_cnt);
+bool ssv6xxx_beacon_enable(struct ssv_softc *sc, bool bEnable);
+void ssv6xxx_beacon_release(struct ssv_softc *sc);
+void ssv6200_set_tim_work(struct work_struct *work);
+void ssv6200_bcast_start_work(struct work_struct *work);
+void ssv6200_bcast_stop_work(struct work_struct *work);
+void ssv6200_bcast_tx_work(struct work_struct *work);
+int ssv6200_bcast_queue_len(struct ssv6xxx_bcast_txq *bcast_txq);
+struct sk_buff *ssv6200_bcast_dequeue(struct ssv6xxx_bcast_txq *bcast_txq,
+				      u8 * remain_len);
+int ssv6200_bcast_enqueue(struct ssv_softc *sc,
+			  struct ssv6xxx_bcast_txq *bcast_txq,
+			  struct sk_buff *skb);
+void ssv6200_bcast_start(struct ssv_softc *sc);
+void ssv6200_bcast_stop(struct ssv_softc *sc);
+void ssv6200_release_bcast_frame_res(struct ssv_softc *sc,
+				     struct ieee80211_vif *vif);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/dev.c b/drivers/net/wireless/ssv6051/smac/dev.c
new file mode 100644
index 00000000000..214e93fae46
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/dev.c
@@ -0,0 +1,3880 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <linux/kthread.h>
+#include <linux/ktime.h>
+
+#include <net/mac80211.h>
+#include <ssv6200.h>
+#include <hci/hctrl.h>
+#include "linux_80211.h"
+#include "lib.h"
+#include "ssv_rc.h"
+#include "ssv_ht_rc.h"
+#include "dev.h"
+#include "ap.h"
+#include "init.h"
+#include "p2p.h"
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+#include "ssv6xxx_debugfs.h"
+#endif
+struct rssi_res_st rssi_res, *p_rssi_res;
+#define NO_USE_RXQ_LOCK
+#ifndef WLAN_CIPHER_SUITE_SMS4
+#define WLAN_CIPHER_SUITE_SMS4 0x00147201
+#endif
+#define MAX_TX_Q_LEN (64)
+#define LOW_TX_Q_LEN (MAX_TX_Q_LEN/2)
+static u16 bits_per_symbol[][2] = {
+	{26, 54},
+	{52, 108},
+	{78, 162},
+	{104, 216},
+	{156, 324},
+	{208, 432},
+	{234, 486},
+	{260, 540},
+};
+
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+extern struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci;
+extern unsigned int cal_duration_of_ampdu(struct sk_buff *ampdu_skb, int stage);
+#endif
+struct ssv6xxx_calib_table {
+	u16 channel_id;
+	u32 rf_ctrl_N;
+	u32 rf_ctrl_F;
+	u16 rf_precision_default;
+};
+static void _process_rx_q(struct ssv_softc *sc, struct sk_buff_head *rx_q,
+			  spinlock_t * rx_q_lock);
+static u32 _process_tx_done(struct ssv_softc *sc);
+
+void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)args;
+	if (!skb)
+		return;
+	ieee80211_free_txskb(sc->hw, skb);
+}
+
+#define ADDRESS_OFFSET 16
+#define HW_ID_OFFSET 7
+#define CH0_FULL_MASK CH0_FULL_MSK
+#define MAX_FAIL_COUNT 100
+#define MAX_RETRY_COUNT 20
+inline bool ssv6xxx_mcu_input_full(struct ssv_softc *sc)
+{
+	u32 regval = 0;
+	SMAC_REG_READ(sc->sh, ADR_MCU_STATUS, &regval);
+	return CH0_FULL_MASK & regval;
+}
+
+u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type)
+{
+	u32 regval, pad;
+	int cnt = MAX_RETRY_COUNT;
+	int page_cnt =
+	    (size + ((1 << HW_MMU_PAGE_SHIFT) - 1)) >> HW_MMU_PAGE_SHIFT;
+	regval = 0;
+	mutex_lock(&sc->mem_mutex);
+	pad = size % 4;
+	size += pad;
+	do {
+		SMAC_REG_WRITE(sc->sh, ADR_WR_ALC, (size | (type << 16)));
+		SMAC_REG_READ(sc->sh, ADR_WR_ALC, &regval);
+		if (regval == 0) {
+			cnt--;
+			msleep(1);
+		} else
+			break;
+	} while (cnt);
+	if (type == TX_BUF) {
+		sc->sh->tx_page_available -= page_cnt;
+		sc->sh->page_count[PACKET_ADDR_2_ID(regval)] = page_cnt;
+	}
+	mutex_unlock(&sc->mem_mutex);
+	if (regval == 0)
+		dev_err(sc->dev,
+			"Failed to allocate packet buffer of %d bytes in %d type.",
+			size, type);
+	else {
+		dev_dbg(sc->dev,
+			"Allocated %d type packet buffer of size %d (%d) at address %x.\n",
+			type, size, page_cnt, regval);
+	}
+	return regval;
+}
+
+bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr)
+{
+	u32 regval = 0;
+	u16 failCount = 0;
+	u8 *p_tx_page_cnt = &sc->sh->page_count[PACKET_ADDR_2_ID(pbuf_addr)];
+	while (ssv6xxx_mcu_input_full(sc)) {
+		if (failCount++ < 1000)
+			continue;
+		dev_err(sc->dev, "Error in mailbox block after %d iterations\n", failCount);
+		return false;
+	}
+	mutex_lock(&sc->mem_mutex);
+	regval =
+	    ((M_ENG_TRASH_CAN << HW_ID_OFFSET) | (pbuf_addr >> ADDRESS_OFFSET));
+	SMAC_REG_WRITE(sc->sh, ADR_CH0_TRIG_1, regval);
+	if (*p_tx_page_cnt) {
+		sc->sh->tx_page_available += *p_tx_page_cnt;
+		*p_tx_page_cnt = 0;
+	}
+	mutex_unlock(&sc->mem_mutex);
+	return true;
+}
+
+static const struct ssv6xxx_calib_table vt_tbl[SSV6XXX_IQK_CFG_XTAL_MAX][14] = {
+	{
+	 {1, 0xB9, 0x89D89E, 3859},
+	 {2, 0xB9, 0xEC4EC5, 3867},
+	 {3, 0xBA, 0x4EC4EC, 3875},
+	 {4, 0xBA, 0xB13B14, 3883},
+	 {5, 0xBB, 0x13B13B, 3891},
+	 {6, 0xBB, 0x762762, 3899},
+	 {7, 0xBB, 0xD89D8A, 3907},
+	 {8, 0xBC, 0x3B13B1, 3915},
+	 {9, 0xBC, 0x9D89D9, 3923},
+	 {10, 0xBD, 0x000000, 3931},
+	 {11, 0xBD, 0x627627, 3939},
+	 {12, 0xBD, 0xC4EC4F, 3947},
+	 {13, 0xBE, 0x276276, 3955},
+	 {14, 0xBF, 0x13B13B, 3974},
+	 },
+	{
+	 {1, 0xf1, 0x333333, 3859},
+	 {2, 0xf1, 0xB33333, 3867},
+	 {3, 0xf2, 0x333333, 3875},
+	 {4, 0xf2, 0xB33333, 3883},
+	 {5, 0xf3, 0x333333, 3891},
+	 {6, 0xf3, 0xB33333, 3899},
+	 {7, 0xf4, 0x333333, 3907},
+	 {8, 0xf4, 0xB33333, 3915},
+	 {9, 0xf5, 0x333333, 3923},
+	 {10, 0xf5, 0xB33333, 3931},
+	 {11, 0xf6, 0x333333, 3939},
+	 {12, 0xf6, 0xB33333, 3947},
+	 {13, 0xf7, 0x333333, 3955},
+	 {14, 0xf8, 0x666666, 3974},
+	 },
+	{
+	 {1, 0xC9, 0x000000, 3859},
+	 {2, 0xC9, 0x6AAAAB, 3867},
+	 {3, 0xC9, 0xD55555, 3875},
+	 {4, 0xCA, 0x400000, 3883},
+	 {5, 0xCA, 0xAAAAAB, 3891},
+	 {6, 0xCB, 0x155555, 3899},
+	 {7, 0xCB, 0x800000, 3907},
+	 {8, 0xCB, 0xEAAAAB, 3915},
+	 {9, 0xCC, 0x555555, 3923},
+	 {10, 0xCC, 0xC00000, 3931},
+	 {11, 0xCD, 0x2AAAAB, 3939},
+	 {12, 0xCD, 0x955555, 3947},
+	 {13, 0xCE, 0x000000, 3955},
+	 {14, 0xCF, 0x000000, 3974},
+	 }
+};
+
+#define FAIL_MAX 100
+#define RETRY_MAX 20
+int ssv6xxx_set_channel(struct ssv_softc *sc, int ch)
+{
+	struct ssv_hw *sh = sc->sh;
+	int retry_cnt, fail_cnt = 0;
+	u32 regval;
+	int ret = -1;
+	int chidx;
+	bool chidx_vld = 0;
+	dev_dbg(sc->dev, "Setting channel to %d\n", ch);
+	if ((sh->cfg.chip_identity == SSV6051Z)
+	    || (sc->sh->cfg.chip_identity == SSV6051P)) {
+		if ((ch == 13) || (ch == 14)) {
+			if (sh->ipd_channel_touch == 0) {
+				for (chidx = 0; chidx < sh->ch_cfg_size;
+				     chidx++) {
+					SMAC_REG_WRITE(sh,
+						       sh->p_ch_cfg[chidx].
+						       reg_addr,
+						       sh->p_ch_cfg[chidx].
+						       ch13_14_value);
+				}
+				sh->ipd_channel_touch = 1;
+			}
+		} else {
+			if (sh->ipd_channel_touch) {
+				for (chidx = 0; chidx < sh->ch_cfg_size;
+				     chidx++) {
+					SMAC_REG_WRITE(sh,
+						       sh->p_ch_cfg[chidx].
+						       reg_addr,
+						       sh->p_ch_cfg[chidx].
+						       ch1_12_value);
+				}
+				sh->ipd_channel_touch = 0;
+			}
+		}
+	}
+	for (chidx = 0; chidx < 14; chidx++) {
+		if (vt_tbl[sh->cfg.crystal_type][chidx].channel_id == ch) {
+			chidx_vld = 1;
+			break;
+		}
+	}
+	if (chidx_vld == 0) {
+		dev_dbg(sc->dev, "%s(): fail! channel_id not found in vt_tbl\n",
+			__FUNCTION__);
+		goto exit;
+	}
+	if ((ret = ssv6xxx_rf_disable(sc->sh)) != 0)
+		goto exit;
+	do {
+		if ((sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M)
+		    || (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M)) {
+			if ((ret =
+			     SMAC_REG_SET_BITS(sc->sh, ADR_SYN_DIV_SDM_XOSC,
+					       (0x00 << 13),
+					       (0x01 << 13))) != 0)
+				break;
+		} else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_40M) {
+			if ((ret =
+			     SMAC_REG_SET_BITS(sc->sh, ADR_SYN_DIV_SDM_XOSC,
+					       (0x01 << 13),
+					       (0x01 << 13))) != 0)
+				break;
+		} else {
+			dev_warn(sc->dev, "Illegal crystal setting in ssv6xxx_set_channel\n");
+			BUG_ON(1);
+		}
+		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SX_LCK_BIN_REGISTERS_I,
+					     (0x01 << 19), (0x01 << 19))) != 0)
+			break;
+		regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_F;
+		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_1,
+					     (regval << 0),
+					     (0x00ffffff << 0))) != 0)
+			break;
+		regval = vt_tbl[sh->cfg.crystal_type][chidx].rf_ctrl_N;
+		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_SYN_REGISTER_2,
+					     (regval << 0),
+					     (0x07ff << 0))) != 0)
+			break;
+		if ((ret =
+		     SMAC_REG_READ(sc->sh, ADR_SX_LCK_BIN_REGISTERS_I,
+				   &regval)) != 0)
+			break;
+		regval =
+		    vt_tbl[sh->cfg.crystal_type][chidx].rf_precision_default;
+		if ((ret =
+		     SMAC_REG_SET_BITS(sc->sh, ADR_SX_LCK_BIN_REGISTERS_II,
+				       (regval << 0), (0x1fff << 0))) != 0)
+			break;
+		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER,
+					     (0x00 << 14), (0x01 << 14))) != 0)
+			break;
+		if ((ret = SMAC_REG_SET_BITS(sc->sh, ADR_MANUAL_ENABLE_REGISTER,
+					     (0x01 << 14), (0x01 << 14))) != 0)
+			break;
+		retry_cnt = 0;
+		do {
+			mdelay(1);
+			if ((ret =
+			     SMAC_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_1,
+					   &regval)) != 0)
+				break;
+			if (regval & 0x00000002) {
+				if ((ret =
+				     SMAC_REG_READ(sc->sh,
+						   ADR_READ_ONLY_FLAGS_2,
+						   &regval)) != 0)
+					break;
+				ret = ssv6xxx_rf_enable(sc->sh);
+				//dev_info(sc->dev, "Lock to channel %d ([0xce010098]=%x)!!\n", vt_tbl[sh->cfg.crystal_type][chidx].channel_id, regval);
+				sc->hw_chan = ch;
+				goto exit;
+			}
+			retry_cnt++;
+		}
+		while (retry_cnt < RETRY_MAX);
+		fail_cnt++;
+		dev_warn(sc->dev, "calibation fail after %d iterations\n", fail_cnt);
+	}
+	while ((fail_cnt < FAIL_MAX) && (ret == 0));
+ exit:
+	if (ch == 14 && regval == 0xff0) {
+		SMAC_IFC_RESET(sc->sh);
+		ssv6xxx_restart_hw(sc);
+	}
+	if (ch <= 7) {
+		if (sh->cfg.tx_power_index_1) {
+			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+			regval &= RG_TX_GAIN_OFFSET_I_MSK;
+			regval |=
+			    (sh->cfg.tx_power_index_1 << RG_TX_GAIN_OFFSET_SFT);
+			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+		} else if (sh->cfg.tx_power_index_2) {
+			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+			regval &= RG_TX_GAIN_OFFSET_I_MSK;
+			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+		}
+	} else {
+		if (sh->cfg.tx_power_index_2) {
+			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+			regval &= RG_TX_GAIN_OFFSET_I_MSK;
+			regval |=
+			    (sh->cfg.tx_power_index_2 << RG_TX_GAIN_OFFSET_SFT);
+			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+		} else if (sh->cfg.tx_power_index_1) {
+			SMAC_REG_READ(sc->sh, ADR_RX_TX_FSM_REGISTER, &regval);
+			regval &= RG_TX_GAIN_OFFSET_I_MSK;
+			SMAC_REG_WRITE(sc->sh, ADR_RX_TX_FSM_REGISTER, regval);
+		}
+	}
+	return ret;
+}
+
+#ifdef CONFIG_SSV_SMARTLINK
+int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch)
+{
+	*pch = sc->hw_chan;
+	return 0;
+}
+
+int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept)
+{
+	u32 val = 0;
+	if (accept) {
+		val = 0x2;
+	} else {
+		val = 0x3;
+	}
+	SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB13, val);
+	return 0;
+}
+
+int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept)
+{
+	u32 val = 0;
+	SMAC_REG_READ(sc->sh, ADR_MRX_FLT_TB13, &val);
+	if (val == 0x2) {
+		*paccept = 1;
+	} else {
+		*paccept = 0;
+	}
+	return 0;
+}
+#endif
+int ssv6xxx_rf_enable(struct ssv_hw *sh)
+{
+	return SMAC_REG_SET_BITS(sh, 0xce010000, (0x02 << 12), (0x03 << 12)
+	    );
+}
+
+int ssv6xxx_rf_disable(struct ssv_hw *sh)
+{
+	return SMAC_REG_SET_BITS(sh, 0xce010000, (0x01 << 12), (0x03 << 12)
+	    );
+}
+
+int ssv6xxx_update_decision_table(struct ssv_softc *sc)
+{
+	int i;
+	for (i = 0; i < MAC_DECITBL1_SIZE; i++) {
+		SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + i * 4,
+			       sc->mac_deci_tbl[i]);
+		SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_TB0 + i * 4,
+				 sc->mac_deci_tbl[i]);
+	}
+	for (i = 0; i < MAC_DECITBL2_SIZE; i++) {
+		SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN0 + i * 4,
+			       sc->mac_deci_tbl[i + MAC_DECITBL1_SIZE]);
+		SMAC_REG_CONFIRM(sc->sh, ADR_MRX_FLT_EN0 + i * 4,
+				 sc->mac_deci_tbl[i + MAC_DECITBL1_SIZE]);
+	}
+	return 0;
+}
+
+static int ssv6xxx_frame_hdrlen(struct ieee80211_hdr *hdr, bool is_ht)
+{
+#define CTRL_FRAME_INDEX(fc) ((hdr->frame_control-IEEE80211_STYPE_BACK_REQ)>>4)
+	u16 fc, CTRL_FLEN[] = { 16, 16, 16, 16, 10, 10, 16, 16 };
+	int hdr_len = 24;
+	fc = hdr->frame_control;
+	if (ieee80211_is_ctl(fc))
+		hdr_len = CTRL_FLEN[CTRL_FRAME_INDEX(fc)];
+	else if (ieee80211_is_mgmt(fc)) {
+		if (ieee80211_has_order(fc))
+			hdr_len += ((is_ht == 1) ? 4 : 0);
+	} else {
+		if (ieee80211_has_a4(fc))
+			hdr_len += 6;
+		if (ieee80211_is_data_qos(fc)) {
+			hdr_len += 2;
+			if (ieee80211_has_order(hdr->frame_control) &&
+			    is_ht == true)
+				hdr_len += 4;
+		}
+	}
+	return hdr_len;
+}
+
+static u32 ssv6xxx_ht_txtime(u8 rix, int pktlen, int width,
+			     int half_gi, bool is_gf)
+{
+	u32 nbits, nsymbits, duration, nsymbols;
+	int streams;
+	streams = 1;
+	nbits = (pktlen << 3) + OFDM_PLCP_BITS;
+	nsymbits = bits_per_symbol[rix % 8][width] * streams;
+	nsymbols = (nbits + nsymbits - 1) / nsymbits;
+	if (!half_gi)
+		duration = SYMBOL_TIME(nsymbols);
+	else {
+		if (!is_gf)
+			duration =
+			    DIV_ROUND_UP(SYMBOL_TIME_HALFGI(nsymbols), 4) << 2;
+		else
+			duration = SYMBOL_TIME_HALFGI(nsymbols);
+	}
+	duration +=
+	    L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams) +
+	    HT_SIGNAL_EXT;
+	if (is_gf)
+		duration -= 12;
+	duration += HT_SIFS_TIME;
+	return duration;
+}
+
+static u32 ssv6xxx_non_ht_txtime(u8 phy, int kbps,
+				 u32 frameLen, bool shortPreamble)
+{
+	u32 bits_per_symbol, num_bits, num_symbols;
+	u32 phy_time, tx_time;
+	if (kbps == 0)
+		return 0;
+	switch (phy) {
+	case WLAN_RC_PHY_CCK:
+		phy_time = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
+		if (shortPreamble)
+			phy_time >>= 1;
+		num_bits = frameLen << 3;
+		tx_time = CCK_SIFS_TIME + phy_time + ((num_bits * 1000) / kbps);
+		break;
+	case WLAN_RC_PHY_OFDM:
+		bits_per_symbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
+		num_bits = OFDM_PLCP_BITS + (frameLen << 3);
+		num_symbols = DIV_ROUND_UP(num_bits, bits_per_symbol);
+		tx_time = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
+		    + (num_symbols * OFDM_SYMBOL_TIME);
+		break;
+	default:
+		pr_err("ssv6051: unknown phy %u\n", phy);
+		BUG_ON(1);
+		tx_time = 0;
+		break;
+	}
+	return tx_time;
+}
+
+static u32 ssv6xxx_set_frame_duration(struct ieee80211_tx_info *info,
+				      struct ssv_rate_info *ssv_rate, u16 len,
+				      struct ssv6200_tx_desc *tx_desc,
+				      struct fw_rc_retry_params *rc_params,
+				      struct ssv_softc *sc)
+{
+	struct ieee80211_tx_rate *tx_drate;
+	u32 frame_time = 0, ack_time = 0, rts_cts_nav = 0, frame_consume_time =
+	    0;
+	u32 l_length = 0, drate_kbps = 0, crate_kbps = 0;
+	bool ctrl_short_preamble = false, is_sgi, is_ht40;
+	bool is_ht, is_gf;
+	int d_phy, c_phy, nRCParams, mcsidx;
+	struct ssv_rate_ctrl *ssv_rc = NULL;
+	tx_drate = &info->control.rates[0];
+	is_sgi = !!(tx_drate->flags & IEEE80211_TX_RC_SHORT_GI);
+	is_ht40 = !!(tx_drate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
+	is_ht = !!(tx_drate->flags & IEEE80211_TX_RC_MCS);
+	is_gf = !!(tx_drate->flags & IEEE80211_TX_RC_GREEN_FIELD);
+	if ((info->control.short_preamble) ||
+	    (tx_drate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
+		ctrl_short_preamble = true;
+	pr_debug("mcs = %d, data rate idx=%d\n", tx_drate->idx, tx_drate[3].count);
+	for (nRCParams = 0; (nRCParams < SSV62XX_TX_MAX_RATES); nRCParams++) {
+		if ((rc_params == NULL) || (sc == NULL)) {
+			mcsidx = tx_drate->idx;
+			drate_kbps = ssv_rate->drate_kbps;
+			crate_kbps = ssv_rate->crate_kbps;
+		} else {
+			if (rc_params[nRCParams].count == 0) {
+				break;
+			}
+			ssv_rc = sc->rc;
+			mcsidx =
+			    (rc_params[nRCParams].drate -
+			     SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES;
+			drate_kbps =
+			    ssv_rc->rc_table[rc_params[nRCParams].drate].
+			    rate_kbps;
+			crate_kbps =
+			    ssv_rc->rc_table[rc_params[nRCParams].crate].
+			    rate_kbps;
+		}
+		if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
+			frame_time = ssv6xxx_ht_txtime(mcsidx,
+						       len, is_ht40, is_sgi,
+						       is_gf);
+			d_phy = 0;
+		} else {
+			if ((info->band == INDEX_80211_BAND_2GHZ) &&
+			    !(ssv_rate->d_flags & IEEE80211_RATE_ERP_G))
+				d_phy = WLAN_RC_PHY_CCK;
+			else
+				d_phy = WLAN_RC_PHY_OFDM;
+			frame_time = ssv6xxx_non_ht_txtime(d_phy, drate_kbps,
+							   len,
+							   ctrl_short_preamble);
+		}
+		if ((info->band == INDEX_80211_BAND_2GHZ) &&
+		    !(ssv_rate->c_flags & IEEE80211_RATE_ERP_G))
+			c_phy = WLAN_RC_PHY_CCK;
+		else
+			c_phy = WLAN_RC_PHY_OFDM;
+		if (tx_desc->unicast) {
+			if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+				ack_time = ssv6xxx_non_ht_txtime(c_phy,
+								 crate_kbps,
+								 BA_LEN,
+								 ctrl_short_preamble);
+			} else {
+				ack_time = ssv6xxx_non_ht_txtime(c_phy,
+								 crate_kbps,
+								 ACK_LEN,
+								 ctrl_short_preamble);
+			}
+		}
+		if (tx_desc->do_rts_cts & IEEE80211_TX_RC_USE_RTS_CTS) {
+			rts_cts_nav = frame_time;
+			rts_cts_nav += ack_time;
+			rts_cts_nav += ssv6xxx_non_ht_txtime(c_phy,
+							     crate_kbps,
+							     CTS_LEN,
+							     ctrl_short_preamble);
+			frame_consume_time = rts_cts_nav;
+			frame_consume_time += ssv6xxx_non_ht_txtime(c_phy,
+								    crate_kbps,
+								    RTS_LEN,
+								    ctrl_short_preamble);
+		} else if (tx_desc->
+			   do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) {
+			rts_cts_nav = frame_time;
+			rts_cts_nav += ack_time;
+			frame_consume_time = rts_cts_nav;
+			frame_consume_time += ssv6xxx_non_ht_txtime(c_phy,
+								    crate_kbps,
+								    CTS_LEN,
+								    ctrl_short_preamble);
+		} else {;
+		}
+		if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
+			l_length = frame_time - HT_SIFS_TIME;
+			l_length = ((l_length - (HT_SIGNAL_EXT + 20)) + 3) >> 2;
+			l_length += ((l_length << 1) - 3);
+		}
+		if ((rc_params == NULL) || (sc == NULL)) {
+			tx_desc->rts_cts_nav = rts_cts_nav;
+			tx_desc->frame_consume_time =
+			    (frame_consume_time >> 5) + 1;;
+			tx_desc->dl_length = l_length;
+			break;
+		} else {
+			rc_params[nRCParams].rts_cts_nav = rts_cts_nav;
+			rc_params[nRCParams].frame_consume_time =
+			    (frame_consume_time >> 5) + 1;
+			rc_params[nRCParams].dl_length = l_length;
+			if (nRCParams == 0) {
+				tx_desc->drate_idx = rc_params[nRCParams].drate;
+				tx_desc->crate_idx = rc_params[nRCParams].crate;
+				tx_desc->rts_cts_nav =
+				    rc_params[nRCParams].rts_cts_nav;
+				tx_desc->frame_consume_time =
+				    rc_params[nRCParams].frame_consume_time;
+				tx_desc->dl_length =
+				    rc_params[nRCParams].dl_length;
+			}
+		}
+	}
+	return ack_time;
+}
+
+static void ssv6200_hw_set_pair_type(struct ssv_hw *sh, u8 type)
+{
+	u32 temp;
+	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
+	temp = (temp & PAIR_SCRT_I_MSK);
+	temp |= (type << PAIR_SCRT_SFT);
+	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
+	dev_dbg(sh->sc->dev, "==>%s: write cipher type %d into hw\n", __func__, type);
+}
+
+static u32 ssv6200_hw_get_pair_type(struct ssv_hw *sh)
+{
+	u32 temp;
+	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
+	temp &= PAIR_SCRT_MSK;
+	temp = (temp >> PAIR_SCRT_SFT);
+	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
+	dev_dbg(sh->sc->dev, "==>%s: read cipher type %d from hw\n", __func__, temp);
+	return temp;
+}
+
+static void ssv6200_hw_set_group_type(struct ssv_hw *sh, u8 type)
+{
+	u32 temp;
+	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
+	temp = temp & GRP_SCRT_I_MSK;
+	temp |= (type << GRP_SCRT_SFT);
+	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
+	dev_dbg(sh->sc->dev, "Set group key type %d\n", type);
+}
+
+void ssv6xxx_reset_sec_module(struct ssv_softc *sc)
+{
+	ssv6200_hw_set_group_type(sc->sh, ME_NONE);
+	ssv6200_hw_set_pair_type(sc->sh, ME_NONE);
+}
+
+static int hw_update_watch_wsid(struct ssv_softc *sc, struct ieee80211_sta *sta,
+				struct ssv_sta_info *sta_info, int sta_idx,
+				int rx_hw_sec, int ops)
+{
+	int ret = 0;
+	int retry_cnt = 20;
+	struct sk_buff *skb = NULL;
+	struct cfg_host_cmd *host_cmd;
+	struct ssv6xxx_wsid_params *ptr;
+	dev_dbg(sc->dev, "cmd=%d for fw wsid list, wsid %d \n", ops, sta_idx);
+	skb =
+	    ssv_skb_alloc(HOST_CMD_HDR_LEN +
+			  sizeof(struct ssv6xxx_wsid_params));
+	if (skb == NULL || sta_info == NULL || sc == NULL)
+		return -1;
+	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_wsid_params);
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_WSID_OP;
+	host_cmd->len = skb->data_len;
+	ptr = (struct ssv6xxx_wsid_params *)host_cmd->dat8;
+	ptr->cmd = ops;
+	ptr->hw_security = rx_hw_sec;
+	if ((ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE)
+	    && (ptr->cmd != SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE)) {
+		ptr->wsid_idx = (u8) (sta_idx - SSV_NUM_HW_STA);
+	} else {
+		ptr->wsid_idx = (u8) (sta_idx);
+	};
+	memcpy(&ptr->target_wsid, &sta->addr[0], 6);
+	while (((sc->sh->hci.hci_ops->hci_send_cmd(skb)) != 0) && (retry_cnt)) {
+		dev_dbg(sc->dev, "WSID cmd=%d retry=%d!!\n", ops, retry_cnt);
+		retry_cnt--;
+	}
+	dev_dbg(sc->dev, "%s: wsid_idx = %u\n", __FUNCTION__, ptr->wsid_idx);
+	ssv_skb_free(skb);
+	if (ops == SSV6XXX_WSID_OPS_ADD)
+		sta_info->hw_wsid = sta_idx;
+	return ret;
+}
+
+static void hw_crypto_key_clear(struct ieee80211_hw *hw, int index,
+				struct ieee80211_key_conf *key,
+				struct ssv_vif_priv_data *vif_priv,
+				struct ssv_sta_priv_data *sta_priv)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_sta_info *sta_info = NULL;
+	if ((index == 0) && (sta_priv == NULL))
+		return;
+	if ((index < 0) || (index >= 4))
+		return;
+	if (index > 0) {
+		if (vif_priv)
+			vif_priv->group_key_idx = 0;
+		if (sta_priv)
+			sta_priv->group_key_idx = 0;
+	}
+	if (sta_priv) {
+		sta_info = &sc->sta_info[sta_priv->sta_idx];
+		if ((index == 0) && (sta_priv->has_hw_decrypt == true)
+		    && (sta_info->hw_wsid >= SSV_NUM_HW_STA)) {
+			hw_update_watch_wsid(sc, sta_info->sta, sta_info,
+					     sta_priv->sta_idx,
+					     SSV6XXX_WSID_SEC_PAIRWISE,
+					     SSV6XXX_WSID_OPS_DISABLE_CAPS);
+		}
+	}
+	if (vif_priv) {
+		if ((index != 0) && !list_empty(&vif_priv->sta_list)) {
+			struct ssv_sta_priv_data *sta_priv_iter;
+			list_for_each_entry(sta_priv_iter, &vif_priv->sta_list,
+					    list) {
+				if (((sta_priv_iter->sta_info->
+				      s_flags & STA_FLAG_VALID) == 0)
+				    || (sta_priv_iter->sta_info->hw_wsid <
+					SSV_NUM_HW_STA))
+					continue;
+				hw_update_watch_wsid(sc,
+						     sta_priv_iter->sta_info->
+						     sta,
+						     sta_priv_iter->sta_info,
+						     sta_priv_iter->sta_idx,
+						     SSV6XXX_WSID_SEC_GROUP,
+						     SSV6XXX_WSID_OPS_DISABLE_CAPS);
+			}
+		}
+	}
+}
+
+static void _set_wep_sw_crypto_key(struct ssv_softc *sc,
+				   struct ssv_vif_info *vif_info,
+				   struct ssv_sta_info *sta_info, void *param)
+{
+	struct ssv_sta_priv_data *sta_priv =
+	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+	sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
+	sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
+	sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
+	sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
+}
+
+static void _set_wep_hw_crypto_pair_key(struct ssv_softc *sc,
+					struct ssv_vif_info *vif_info,
+					struct ssv_sta_info *sta_info,
+					void *param)
+{
+	int wsid = sta_info->hw_wsid;
+	struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param;
+	int address = 0;
+	int *pointer = NULL;
+	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
+	u32 sec_key_tbl = sec_key_tbl_base;
+	int i;
+	u8 *key = sram_key->sta_key[0].pair.key;
+	u32 key_len = *(u16 *) & sram_key->sta_key[0].reserve[0];
+	struct ssv_sta_priv_data *sta_priv =
+	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+	if (wsid == (-1))
+		return;
+	sram_key->sta_key[wsid].pair_key_idx = 0;
+	sram_key->sta_key[wsid].group_key_idx = 0;
+	sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
+	sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
+	sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
+	sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
+	if (wsid != 0)
+		memcpy(sram_key->sta_key[wsid].pair.key, key, key_len);
+	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
+	    + wsid * sizeof(struct ssv6xxx_hw_sta_key);
+	address += (0x10000 * wsid);
+	pointer = (int *)&sram_key->sta_key[wsid];
+	for (i = 0; i < (sizeof(struct ssv6xxx_hw_sta_key) / 4); i++)
+		SMAC_REG_WRITE(sc->sh, address + (i * 4), *(pointer++));
+}
+
+static void _set_wep_hw_crypto_group_key(struct ssv_softc *sc,
+					 struct ssv_vif_info *vif_info,
+					 struct ssv_sta_info *sta_info,
+					 void *param)
+{
+	int wsid = sta_info->hw_wsid;
+	struct ssv6xxx_hw_sec *sram_key = (struct ssv6xxx_hw_sec *)param;
+	int address = 0;
+	int *pointer = NULL;
+	u32 key_idx = sram_key->sta_key[0].pair_key_idx;
+	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
+	u32 key_len = *(u16 *) & sram_key->sta_key[0].reserve[0];
+	u8 *key = sram_key->group_key[key_idx - 1].key;
+	u32 sec_key_tbl = sec_key_tbl_base;
+	struct ssv_sta_priv_data *sta_priv =
+	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+	if (wsid == (-1))
+		return;
+	if (wsid != 0) {
+		sram_key->sta_key[wsid].pair_key_idx = key_idx;
+		sram_key->sta_key[wsid].group_key_idx = key_idx;
+		sta_priv->has_hw_encrypt = vif_priv->has_hw_encrypt;
+		sta_priv->has_hw_decrypt = vif_priv->has_hw_decrypt;
+		sta_priv->need_sw_encrypt = vif_priv->need_sw_encrypt;
+		sta_priv->need_sw_decrypt = vif_priv->need_sw_decrypt;
+	}
+	if (wsid != 0)
+		memcpy(sram_key->group_key[key_idx - 1].key, key, key_len);
+	sec_key_tbl += (0x10000 * wsid);
+	address = sec_key_tbl + ((key_idx - 1) * sizeof(struct ssv6xxx_hw_key));
+	pointer = (int *)&sram_key->group_key[key_idx - 1];
+	{
+		int i;
+		for (i = 0; i < (sizeof(struct ssv6xxx_hw_key) / 4); i++)
+			SMAC_REG_WRITE(sc->sh, address + (i * 4), *(pointer++));
+	}
+	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
+	    + (wsid * sizeof(struct ssv6xxx_hw_sta_key));
+	pointer = (int *)&sram_key->sta_key[wsid];
+	SMAC_REG_WRITE(sc->sh, address, *(pointer));
+}
+
+static int hw_crypto_key_write_wep(struct ieee80211_hw *hw,
+				   struct ieee80211_key_conf *key,
+				   u8 algorithm, struct ssv_vif_info *vif_info)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey;
+	if (key->keyidx == 0) {
+		ssv6xxx_foreach_vif_sta(sc, vif_info,
+					_set_wep_hw_crypto_pair_key, sramKey);
+	} else {
+		ssv6xxx_foreach_vif_sta(sc, vif_info,
+					_set_wep_hw_crypto_group_key, sramKey);
+	}
+	return 0;
+}
+
+static void _set_aes_tkip_hw_crypto_group_key(struct ssv_softc *sc,
+					      struct ssv_vif_info *vif_info,
+					      struct ssv_sta_info *sta_info,
+					      void *param)
+{
+	int wsid = sta_info->hw_wsid;
+	int j;
+	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
+	u32 sec_key_tbl = sec_key_tbl_base;
+	int address = 0;
+	int *pointer = 0;
+	struct ssv6xxx_hw_sec *sramKey = &(vif_info->sramKey);
+	int index = *(u8 *) param;
+	if (wsid == (-1))
+		return;
+	BUG_ON(index == 0);
+	sramKey->sta_key[wsid].group_key_idx = index;
+	sec_key_tbl += (0x10000 * wsid);
+	address = sec_key_tbl + ((index - 1) * sizeof(struct ssv6xxx_hw_key));
+	if (vif_info->vif_priv != NULL)
+		dev_dbg(sc->dev, "Write group key %d to VIF %d to %08X\n",
+			index, vif_info->vif_priv->vif_idx, address);
+	else
+		dev_err(sc->dev, "NULL VIF.\n");
+	pointer = (int *)&sramKey->group_key[index - 1];
+	for (j = 0; j < (sizeof(struct ssv6xxx_hw_key) / 4); j++)
+		SMAC_REG_WRITE(sc->sh, address + (j * 4), *(pointer++));
+	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
+	    + (wsid * sizeof(struct ssv6xxx_hw_sta_key));
+	pointer = (int *)&sramKey->sta_key[wsid];
+	SMAC_REG_WRITE(sc->sh, address, *(pointer));
+	if (wsid >= SSV_NUM_HW_STA) {
+		hw_update_watch_wsid(sc, sta_info->sta, sta_info,
+				     wsid, SSV6XXX_WSID_SEC_GROUP,
+				     SSV6XXX_WSID_OPS_ENABLE_CAPS);
+	}
+}
+
+static int _write_pairwise_key_to_hw(struct ssv_softc *sc,
+				     int index, u8 algorithm,
+				     const u8 * key, int key_len,
+				     struct ieee80211_key_conf *keyconf,
+				     struct ssv_vif_priv_data *vif_priv,
+				     struct ssv_sta_priv_data *sta_priv)
+{
+	int i;
+	struct ssv6xxx_hw_sec *sramKey;
+	int address = 0;
+	int *pointer = NULL;
+	u32 sec_key_tbl_base = sc->sh->hw_sec_key[0];
+	u32 sec_key_tbl;
+	int wsid = (-1);
+	if (sta_priv == NULL) {
+		dev_err(sc->dev, "Set pair-wise key with NULL STA.\n");
+		return -EOPNOTSUPP;
+	}
+	wsid = sta_priv->sta_info->hw_wsid;
+	if ((wsid < 0) || (wsid >= SSV_NUM_STA)) {
+		dev_err(sc->dev, "Set pair-wise key to invalid WSID %d.\n",
+			wsid);
+		return -EOPNOTSUPP;
+	}
+	dev_dbg(sc->dev, "Set STA %d's pair-wise key of %d bytes.\n", wsid,
+		key_len);
+	sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
+	sramKey->sta_key[wsid].pair_key_idx = 0;
+	sramKey->sta_key[wsid].group_key_idx = vif_priv->group_key_idx;
+	memcpy(sramKey->sta_key[wsid].pair.key, key, key_len);
+	sec_key_tbl = sec_key_tbl_base;
+	sec_key_tbl += (0x10000 * wsid);
+	address = sec_key_tbl + (3 * sizeof(struct ssv6xxx_hw_key))
+	    + wsid * sizeof(struct ssv6xxx_hw_sta_key);
+	pointer = (int *)&sramKey->sta_key[wsid];
+	for (i = 0; i < (sizeof(struct ssv6xxx_hw_sta_key) / 4); i++)
+		SMAC_REG_WRITE(sc->sh, (address + (i * 4)), *(pointer++));
+	if (wsid >= SSV_NUM_HW_STA) {
+		hw_update_watch_wsid(sc, sta_priv->sta_info->sta,
+				     sta_priv->sta_info, sta_priv->sta_idx,
+				     SSV6XXX_WSID_SEC_PAIRWISE,
+				     SSV6XXX_WSID_OPS_ENABLE_CAPS);
+	}
+	return 0;
+}
+
+static int _write_group_key_to_hw(struct ssv_softc *sc,
+				  int index, u8 algorithm,
+				  const u8 * key, int key_len,
+				  struct ieee80211_key_conf *keyconf,
+				  struct ssv_vif_priv_data *vif_priv,
+				  struct ssv_sta_priv_data *sta_priv)
+{
+	struct ssv6xxx_hw_sec *sramKey;
+	int wsid = sta_priv ? sta_priv->sta_info->hw_wsid : (-1);
+	int ret = 0;
+	if (vif_priv == NULL) {
+		dev_err(sc->dev, "Setting group key to NULL VIF\n");
+		return -EOPNOTSUPP;
+	}
+	dev_dbg(sc->dev,
+		"Setting VIF %d group key %d of length %d to WSID %d.\n",
+		vif_priv->vif_idx, index, key_len, wsid);
+	sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
+	vif_priv->group_key_idx = index;
+	if (sta_priv)
+		sta_priv->group_key_idx = index;
+	memcpy(sramKey->group_key[index - 1].key, key, key_len);
+	WARN_ON(sc->vif_info[vif_priv->vif_idx].vif_priv == NULL);
+	ssv6xxx_foreach_vif_sta(sc, &sc->vif_info[vif_priv->vif_idx],
+				_set_aes_tkip_hw_crypto_group_key, &index);
+	ret = 0;
+	return ret;
+}
+
+static enum SSV_CIPHER_E _prepare_key(struct ieee80211_key_conf *key)
+{
+	enum SSV_CIPHER_E cipher;
+	switch (key->cipher) {
+	case WLAN_CIPHER_SUITE_WEP40:
+		cipher = SSV_CIPHER_WEP40;
+		break;
+	case WLAN_CIPHER_SUITE_WEP104:
+		cipher = SSV_CIPHER_WEP104;
+		break;
+	case WLAN_CIPHER_SUITE_TKIP:
+		key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
+		cipher = SSV_CIPHER_TKIP;
+		break;
+	case WLAN_CIPHER_SUITE_CCMP:
+		key->flags |=
+		    (IEEE80211_KEY_FLAG_SW_MGMT_TX |
+		     IEEE80211_KEY_FLAG_RX_MGMT);
+		cipher = SSV_CIPHER_CCMP;
+		break;
+	default:
+		cipher = SSV_CIPHER_INVALID;
+		break;
+	}
+	return cipher;
+}
+int _set_key_wep(struct ssv_softc *sc, struct ssv_vif_priv_data *vif_priv,
+		 struct ssv_sta_priv_data *sta_priv, enum SSV_CIPHER_E cipher,
+		 struct ieee80211_key_conf *key)
+{
+	int ret = 0;
+	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+	struct ssv6xxx_hw_sec *sram_key = &vif_info->sramKey;
+	sram_key->sta_key[0].pair_key_idx = key->keyidx;
+	sram_key->sta_key[0].group_key_idx = key->keyidx;
+	*(u16 *) & sram_key->sta_key[0].reserve[0] = key->keylen;
+	dev_dbg(sc->dev, "Set WEP %02X %02X %02X %02X %02X %02X %02X %02X... (%d %d)\n",
+	       key->key[0], key->key[1], key->key[2], key->key[3], key->key[4],
+	       key->key[5], key->key[6], key->key[7], key->keyidx, key->keylen);
+	if (key->keyidx == 0) {
+		memcpy(sram_key->sta_key[0].pair.key, key->key, key->keylen);
+	} else {
+		memcpy(sram_key->group_key[key->keyidx - 1].key, key->key,
+		       key->keylen);
+	}
+	if (sc->sh->cfg.use_wpa2_only) {
+		dev_warn(sc->dev, "WEP: use WPA2 HW security mode only.\n");
+	}
+	if ((sc->sh->cfg.use_wpa2_only == 0)
+	    && vif_priv->vif_idx == 0) {
+		vif_priv->has_hw_decrypt = true;
+		vif_priv->has_hw_encrypt = true;
+		vif_priv->need_sw_decrypt = false;
+		vif_priv->need_sw_encrypt = false;
+		vif_priv->use_mac80211_decrypt = false;
+		ssv6200_hw_set_pair_type(sc->sh, cipher);
+		ssv6200_hw_set_group_type(sc->sh, cipher);
+		hw_crypto_key_write_wep(sc->hw, key, cipher,
+					&sc->vif_info[vif_priv->vif_idx]);
+	} else {
+		vif_priv->has_hw_decrypt = false;
+		vif_priv->has_hw_encrypt = false;
+		vif_priv->need_sw_decrypt = false;
+		vif_priv->need_sw_encrypt = false;
+		vif_priv->use_mac80211_decrypt = true;
+		ssv6xxx_foreach_vif_sta(sc, vif_info, _set_wep_sw_crypto_key,
+					NULL);
+		ret = -EOPNOTSUPP;
+	}
+	vif_priv->pair_cipher = vif_priv->group_cipher = cipher;
+	vif_priv->is_security_valid = true;
+	return ret;
+}
+
+static int _set_pairwise_key_tkip_ccmp(struct ssv_softc *sc,
+				       struct ssv_vif_priv_data *vif_priv,
+				       struct ssv_sta_priv_data *sta_priv,
+				       enum SSV_CIPHER_E cipher,
+				       struct ieee80211_key_conf *key)
+{
+	int ret = 0;
+	const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP";
+	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+	bool tdls_link = false, tdls_use_sw_cipher = false, tkip_use_sw_cipher =
+	    false;
+	bool use_non_ccmp = false;
+	int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
+	struct ssv_vif_priv_data *another_vif_priv =
+	    (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].vif_priv;
+	if (sta_priv == NULL) {
+		dev_err(sc->dev,
+			"Setting pairwise TKIP/CCMP key to NULL STA.\n");
+		return -EOPNOTSUPP;
+	}
+	if (sc->sh->cfg.use_wpa2_only) {
+		dev_warn(sc->dev, "Pairwise TKIP/CCMP: use WPA2 HW security mode only.\n");
+	}
+	if (vif_info->if_type == NL80211_IFTYPE_STATION) {
+		struct ssv_sta_priv_data *first_sta_priv =
+		    list_first_entry(&vif_priv->sta_list,
+				     struct ssv_sta_priv_data, list);
+		if (first_sta_priv->sta_idx != sta_priv->sta_idx) {
+			tdls_link = true;
+		}
+		dev_dbg(sc->dev, "first sta idx %d, current sta idx %d\n",
+		       first_sta_priv->sta_idx, sta_priv->sta_idx);
+	}
+	if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)
+	    && (sc->sh->cfg.use_wpa2_only == false)) {
+		tdls_use_sw_cipher = true;
+	}
+	if (another_vif_priv != NULL) {
+		if ((another_vif_priv->pair_cipher != SSV_CIPHER_CCMP)
+		    && (another_vif_priv->pair_cipher != SSV_CIPHER_NONE)) {
+			use_non_ccmp = true;
+			dev_dbg(sc->dev, "another vif use none ccmp\n");
+		}
+	}
+	if ((((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_CCMP))
+	     || (use_non_ccmp))
+	    && (sc->sh->cfg.use_wpa2_only == 1) && (cipher == SSV_CIPHER_CCMP)) {
+		u32 val;
+		SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val);
+		if (((val >> 4) & 0xF) != M_ENG_CPU) {
+			SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+				       ((val & 0xf) | (M_ENG_CPU << 4)
+					| (val & 0xfffffff0) << 4));
+			dev_dbg(sc->dev,
+				"orginal Rx_Flow %x , modified flow %x \n", val,
+				((val & 0xf) | (M_ENG_CPU << 4) |
+				 (val & 0xfffffff0) << 4));
+		}
+	}
+	if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) {
+		tkip_use_sw_cipher = true;
+	}
+	if (tkip_use_sw_cipher == true)
+		dev_info(sc->dev, "Using software TKIP cipher\n");
+	if ((((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false)
+	      && (tkip_use_sw_cipher == false)))
+	    || ((cipher == SSV_CIPHER_CCMP)
+		&& (sc->sh->cfg.use_wpa2_only == 1))) {
+		sta_priv->has_hw_decrypt = true;
+		sta_priv->need_sw_decrypt = false;
+		if ((cipher == SSV_CIPHER_TKIP)
+		    || ((!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX) ||
+			 (sta_priv->sta_info->sta->ht_cap.ht_supported ==
+			  false))
+			&& (vif_priv->force_sw_encrypt == false))) {
+			dev_dbg(sc->dev,
+				"STA %d uses HW encrypter for pairwise.\n",
+				sta_priv->sta_idx);
+			sta_priv->has_hw_encrypt = true;
+			sta_priv->need_sw_encrypt = false;
+			sta_priv->use_mac80211_decrypt = false;
+			ret = 0;
+		} else {
+			sta_priv->has_hw_encrypt = false;
+			sta_priv->need_sw_encrypt = false;
+			sta_priv->use_mac80211_decrypt = true;
+			ret = -EOPNOTSUPP;
+		}
+	} else {
+		sta_priv->has_hw_encrypt = false;
+		sta_priv->has_hw_decrypt = false;
+		dev_err(sc->dev, "STA %d MAC80211's %s cipher.\n",
+			sta_priv->sta_idx, cipher_name);
+		sta_priv->need_sw_encrypt = false;
+		sta_priv->need_sw_decrypt = false;
+		sta_priv->use_mac80211_decrypt = true;
+		ret = -EOPNOTSUPP;
+	}
+	if (sta_priv->has_hw_encrypt || sta_priv->has_hw_decrypt) {
+		ssv6200_hw_set_pair_type(sc->sh, cipher);
+		_write_pairwise_key_to_hw(sc, key->keyidx, cipher,
+					  key->key, key->keylen, key,
+					  vif_priv, sta_priv);
+	}
+	if ((vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt)
+	    && (vif_priv->group_key_idx > 0)) {
+		_set_aes_tkip_hw_crypto_group_key(sc,
+						  &sc->vif_info[vif_priv->
+								vif_idx],
+						  sta_priv->sta_info,
+						  &vif_priv->group_key_idx);
+	}
+	return ret;
+}
+
+static int _set_group_key_tkip_ccmp(struct ssv_softc *sc,
+				    struct ssv_vif_priv_data *vif_priv,
+				    struct ssv_sta_priv_data *sta_priv,
+				    enum SSV_CIPHER_E cipher,
+				    struct ieee80211_key_conf *key)
+{
+	int ret = 0;
+	const char *cipher_name = (cipher == SSV_CIPHER_CCMP) ? "CCMP" : "TKIP";
+	bool tkip_use_sw_cipher = false;
+	vif_priv->group_cipher = cipher;
+	if (sc->sh->cfg.use_wpa2_only) {
+		dev_warn(sc->dev, "Group TKIP/CCMP: use WPA2 HW security mode only.\n");
+	}
+	if ((cipher == SSV_CIPHER_TKIP) && (sc->sh->cfg.use_wpa2_only == 1)) {
+		tkip_use_sw_cipher = true;
+	}
+	if (((vif_priv->vif_idx == 0) && (tkip_use_sw_cipher == false))
+	    || ((cipher == SSV_CIPHER_CCMP)
+		&& (sc->sh->cfg.use_wpa2_only == 1))) {
+		dev_dbg(sc->dev, "VIF %d uses HW %s cipher for group.\n",
+			vif_priv->vif_idx, cipher_name);
+#ifdef USE_MAC80211_DECRYPT_BROADCAST
+		vif_priv->has_hw_decrypt = false;
+		ret = -EOPNOTSUPP;
+#else
+		vif_priv->has_hw_decrypt = true;
+#endif
+		vif_priv->has_hw_encrypt = true;
+		vif_priv->need_sw_decrypt = false;
+		vif_priv->need_sw_encrypt = false;
+		vif_priv->use_mac80211_decrypt = false;
+	} else {
+		vif_priv->has_hw_decrypt = false;
+		vif_priv->has_hw_encrypt = false;
+		dev_err(sc->dev, "VIF %d uses MAC80211's %s cipher.\n",
+			vif_priv->vif_idx, cipher_name);
+		vif_priv->need_sw_encrypt = false;
+		vif_priv->need_sw_encrypt = false;
+		vif_priv->use_mac80211_decrypt = true;
+		ret = -EOPNOTSUPP;
+	}
+	if (vif_priv->has_hw_encrypt || vif_priv->has_hw_decrypt) {
+#ifdef USE_MAC80211_DECRYPT_BROADCAST
+		ssv6200_hw_set_group_type(sc->sh, ME_NONE);
+#else
+		ssv6200_hw_set_group_type(sc->sh, cipher);
+#endif
+		key->hw_key_idx = key->keyidx;
+		_write_group_key_to_hw(sc, key->keyidx, cipher,
+				       key->key, key->keylen, key,
+				       vif_priv, sta_priv);
+	}
+	vif_priv->is_security_valid = true;
+	{
+		int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
+		struct ssv_vif_priv_data *another_vif_priv =
+		    (struct ssv_vif_priv_data *)sc->vif_info[another_vif_idx].
+		    vif_priv;
+		if (another_vif_priv != NULL) {
+			if (((SSV6XXX_USE_SW_DECRYPT(vif_priv)
+			      && SSV6XXX_USE_HW_DECRYPT(another_vif_priv)))
+			    || ((SSV6XXX_USE_HW_DECRYPT(vif_priv)
+				 &&
+				 (SSV6XXX_USE_SW_DECRYPT(another_vif_priv))))) {
+				u32 val;
+				SMAC_REG_READ(sc->sh, ADR_RX_FLOW_DATA, &val);
+				if (((val >> 4) & 0xF) != M_ENG_CPU) {
+					SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+						       ((val & 0xf) |
+							(M_ENG_CPU << 4)
+							| (val & 0xfffffff0) <<
+							4));
+					dev_dbg(sc->dev,
+						"orginal Rx_Flow %x , modified flow %x \n",
+						val,
+						((val & 0xf) | (M_ENG_CPU << 4)
+						 | (val & 0xfffffff0) << 4));
+				} else {
+					dev_dbg(sc->dev, " doesn't need to change rx flow\n");
+				}
+			}
+		}
+	}
+	return ret;
+}
+
+static int _set_key_tkip_ccmp(struct ssv_softc *sc,
+			      struct ssv_vif_priv_data *vif_priv,
+			      struct ssv_sta_priv_data *sta_priv,
+			      enum SSV_CIPHER_E cipher,
+			      struct ieee80211_key_conf *key)
+{
+	if (key->keyidx == 0)
+		return _set_pairwise_key_tkip_ccmp(sc, vif_priv, sta_priv,
+						   cipher, key);
+	else
+		return _set_group_key_tkip_ccmp(sc, vif_priv, sta_priv, cipher,
+						key);
+}
+
+static int ssv6200_set_key(struct ieee80211_hw *hw,
+			   enum set_key_cmd cmd,
+			   struct ieee80211_vif *vif,
+			   struct ieee80211_sta *sta,
+			   struct ieee80211_key_conf *key)
+{
+	struct ssv_softc *sc = hw->priv;
+	int ret = 0;
+	enum SSV_CIPHER_E cipher = SSV_CIPHER_NONE;
+	int sta_idx = (-1);
+	struct ssv_sta_info *sta_info = NULL;
+	struct ssv_sta_priv_data *sta_priv = NULL;
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+	if (sta) {
+		sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+		sta_idx = sta_priv->sta_idx;
+		sta_info = sta_priv->sta_info;
+	}
+	BUG_ON((cmd != SET_KEY) && (cmd != DISABLE_KEY));
+	if (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_SECURITY)) {
+		dev_warn(sc->dev, "HW does not support security.\n");
+		return -EOPNOTSUPP;
+	}
+	if (sta_info && (sta_info->hw_wsid == (-1))) {
+		dev_warn(sc->dev,
+			 "Add STA without HW resource. Use MAC80211's solution.\n");
+		return -EOPNOTSUPP;
+	}
+	cipher = _prepare_key(key);
+	dev_dbg(sc->dev,
+		"Set key VIF %d VIF type %d STA %d algorithm = %d, key->keyidx = %d, cmd = %d\n",
+		vif_priv->vif_idx, vif->type, sta_idx, cipher, key->keyidx,
+		cmd);
+	if (cipher == SSV_CIPHER_INVALID) {
+		dev_warn(sc->dev, "Unsupported cipher type.\n");
+		return -EOPNOTSUPP;
+	}
+	mutex_lock(&sc->mutex);
+	switch (cmd) {
+	case SET_KEY:
+		{
+			switch (cipher) {
+			case SSV_CIPHER_WEP40:
+			case SSV_CIPHER_WEP104:
+				ret =
+				    _set_key_wep(sc, vif_priv, sta_priv, cipher,
+						 key);
+				break;
+			case SSV_CIPHER_TKIP:
+			case SSV_CIPHER_CCMP:
+				ret =
+				    _set_key_tkip_ccmp(sc, vif_priv, sta_priv,
+						       cipher, key);
+				break;
+			default:
+				break;
+			}
+			if (sta) {
+				struct ssv_sta_priv_data *first_sta_priv =
+				    list_first_entry(&vif_priv->sta_list,
+						     struct ssv_sta_priv_data,
+						     list);
+				if (first_sta_priv->sta_idx ==
+				    sta_priv->sta_idx) {
+					vif_priv->pair_cipher = cipher;
+				}
+				if (SSV6200_USE_HW_WSID(sta_idx)) {
+					if (SSV6XXX_USE_SW_DECRYPT(sta_priv)) {
+						u32 cipher_setting;
+						cipher_setting =
+						    ssv6200_hw_get_pair_type
+						    (sc->sh);
+						if (cipher_setting != ME_NONE) {
+							u32 val;
+							SMAC_REG_READ(sc->sh,
+								      ADR_RX_FLOW_DATA,
+								      &val);
+							if (((val >> 4) & 0xF)
+							    != M_ENG_CPU) {
+								SMAC_REG_WRITE
+								    (sc->sh,
+								     ADR_RX_FLOW_DATA,
+								     ((val &
+								       0xf) |
+								      (M_ENG_CPU
+								       << 4)
+								      | (val &
+									 0xfffffff0)
+								      << 4));
+								dev_dbg(sc->dev,
+									"orginal Rx_Flow %x , modified flow %x \n",
+									val,
+									((val &
+									  0xf) |
+									 (M_ENG_CPU
+									  << 4)
+									 | (val
+									    &
+									    0xfffffff0)
+									 << 4));
+							} else {
+								dev_dbg(sc->dev, " doesn't need to change rx flow\n");
+							}
+						}
+					}
+					if (sta_priv->has_hw_decrypt) {
+						hw_update_watch_wsid(sc, sta,
+								     sta_info,
+								     sta_idx,
+								     SSV6XXX_WSID_SEC_HW,
+								     SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE);
+						dev_info(sc->dev, "set hw wsid %d cipher mode to HW cipher for pairwise key\n", sta_idx);
+					}
+				}
+			} else {
+				if (vif_info->if_type == NL80211_IFTYPE_STATION) {
+					struct ssv_sta_priv_data *first_sta_priv
+					    =
+					    list_first_entry(&vif_priv->
+							     sta_list,
+							     struct
+							     ssv_sta_priv_data,
+							     list);
+					if (SSV6200_USE_HW_WSID
+					    (first_sta_priv->sta_idx)) {
+						if (vif_priv->has_hw_decrypt) {
+							hw_update_watch_wsid(sc,
+									     sta,
+									     sta_info,
+									     first_sta_priv->
+									     sta_idx,
+									     SSV6XXX_WSID_SEC_HW,
+									     SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE);
+							dev_info(sc->dev, "set hw wsid %d cipher mode to HW cipher for group key\n", first_sta_priv->sta_idx);
+						}
+					}
+				}
+			}
+		}
+		break;
+	case DISABLE_KEY:
+		{
+			int another_vif_idx = ((vif_priv->vif_idx + 1) % 2);
+			struct ssv_vif_priv_data *another_vif_priv =
+			    (struct ssv_vif_priv_data *)sc->
+			    vif_info[another_vif_idx].vif_priv;
+			if (another_vif_priv != NULL) {
+				struct ssv_vif_info *vif_info =
+				    &sc->vif_info[vif_priv->vif_idx];
+				if (vif_info->if_type != NL80211_IFTYPE_AP) {
+					if ((SSV6XXX_USE_SW_DECRYPT(vif_priv)
+					     &&
+					     SSV6XXX_USE_HW_DECRYPT
+					     (another_vif_priv))
+					    ||
+					    (SSV6XXX_USE_SW_DECRYPT
+					     (another_vif_priv)
+					     &&
+					     SSV6XXX_USE_HW_DECRYPT(vif_priv)))
+					{
+						SMAC_REG_WRITE(sc->sh,
+							       ADR_RX_FLOW_DATA,
+							       M_ENG_MACRX |
+							       (M_ENG_ENCRYPT_SEC
+								<< 4) |
+							       (M_ENG_HWHCI <<
+								8));
+						dev_dbg(sc->dev, "redirect Rx flow for disconnect\n");
+					}
+				} else {
+					if (sta == NULL) {
+						if (SSV6XXX_USE_SW_DECRYPT
+						    (another_vif_priv)
+						    &&
+						    SSV6XXX_USE_HW_DECRYPT
+						    (vif_priv)) {
+							SMAC_REG_WRITE(sc->sh,
+								       ADR_RX_FLOW_DATA,
+								       M_ENG_MACRX
+								       |
+								       (M_ENG_ENCRYPT_SEC
+									<< 4) |
+								       (M_ENG_HWHCI
+									<< 8));
+							dev_dbg(sc->dev, "redirect Rx flow for disconnect\n");
+						}
+					}
+				}
+			}
+			if (sta == NULL) {
+				vif_priv->group_cipher = ME_NONE;
+				if ((another_vif_priv == NULL)
+				    || ((another_vif_priv != NULL)
+					&&
+					(!SSV6XXX_USE_HW_DECRYPT
+					 (another_vif_priv)))) {
+					ssv6200_hw_set_group_type(sc->sh,
+								  ME_NONE);
+				}
+			} else {
+				struct ssv_vif_info *vif_info =
+				    &sc->vif_info[vif_priv->vif_idx];
+				if ((vif_info->if_type != NL80211_IFTYPE_AP)
+				    && (another_vif_priv == NULL)) {
+					struct ssv_sta_priv_data *first_sta_priv
+					    =
+					    list_first_entry(&vif_priv->
+							     sta_list,
+							     struct
+							     ssv_sta_priv_data,
+							     list);
+					if (sta_priv == first_sta_priv) {
+						ssv6200_hw_set_pair_type(sc->sh,
+									 ME_NONE);
+					}
+				}
+				vif_priv->pair_cipher = ME_NONE;
+			}
+			if ((cipher == ME_TKIP) || (cipher == ME_CCMP)) {
+				dev_dbg(sc->dev, "Clear key %d VIF %d, STA %d\n",
+				       key->keyidx, (vif != NULL),
+				       (sta != NULL));
+				hw_crypto_key_clear(hw, key->keyidx, key,
+						    vif_priv, sta_priv);
+			}
+			{
+				if ((key->keyidx == 0) && (sta_priv != NULL)) {
+					sta_priv->has_hw_decrypt = false;
+					sta_priv->has_hw_encrypt = false;
+					sta_priv->need_sw_encrypt = false;
+					sta_priv->use_mac80211_decrypt = false;
+				}
+				if ((vif_priv->is_security_valid)
+				    && (key->keyidx != 0)) {
+					vif_priv->is_security_valid = false;
+				}
+			}
+			ret = 0;
+		}
+		break;
+	default:
+		ret = -EINVAL;
+	}
+	mutex_unlock(&sc->mutex);
+	if (sta_priv != NULL) {
+		dev_info(sc->dev, "station mode: hardware encrypt:%d/decrypt:%d, software encrypt:%d/decrypt:%d\n",
+		       (sta_priv->has_hw_encrypt == true),
+		       (sta_priv->has_hw_decrypt == true),
+		       (sta_priv->need_sw_encrypt == true),
+		       (sta_priv->need_sw_decrypt == true));
+	}
+	if (vif_priv) {
+		dev_info
+		    (sc->dev, "vif mode: hardware encrypt:%d/decrypt:%d, software encrypt:%d/decrypt:%d, mac80211 decrypt: %d, valid:%d\n",
+		     (vif_priv->has_hw_encrypt == true),
+		     (vif_priv->has_hw_decrypt == true),
+		     (vif_priv->need_sw_encrypt == true),
+		     (vif_priv->need_sw_decrypt == true),
+		     (vif_priv->use_mac80211_decrypt == true),
+		     (vif_priv->is_security_valid == true));
+	}
+	if (vif_priv->force_sw_encrypt
+	    || (sta_info && (sta_info->hw_wsid != 1)
+		&& (sta_info->hw_wsid != 0))) {
+		if (vif_priv->force_sw_encrypt == false)
+			vif_priv->force_sw_encrypt = true;
+		ret = -EOPNOTSUPP;
+	}
+	dev_dbg(sc->dev, "SET KEY %d\n", ret);
+	return ret;
+}
+
+u32 _process_tx_done(struct ssv_softc *sc)
+{
+	struct ieee80211_tx_info *tx_info;
+	struct sk_buff *skb;
+	while ((skb = skb_dequeue(&sc->tx_done_q))) {
+		struct ssv6200_tx_desc *tx_desc;
+		tx_info = IEEE80211_SKB_CB(skb);
+		tx_desc = (struct ssv6200_tx_desc *)skb->data;
+		if (tx_desc->c_type > M2_TXREQ) {
+			ssv_skb_free(skb);
+			dev_dbg(sc->dev, "free cmd skb!\n");
+			continue;
+		}
+		if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
+			ssv6200_ampdu_release_skb(skb, sc->hw);
+			continue;
+		}
+		skb_pull(skb, SSV6XXX_TX_DESC_LEN);
+		ieee80211_tx_info_clear_status(tx_info);
+		tx_info->flags |= IEEE80211_TX_STAT_ACK;
+		tx_info->status.ack_signal = 100;
+#ifdef REPORT_TX_DONE_IN_IRQ
+		ieee80211_tx_status_irqsafe(sc->hw, skb);
+#else
+		ieee80211_tx_status(sc->hw, skb);
+		if (skb_queue_len(&sc->rx_skb_q))
+			break;
+#endif
+	}
+	return skb_queue_len(&sc->tx_done_q);
+}
+
+#ifdef REPORT_TX_DONE_IN_IRQ
+void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)args;
+	_process_tx_done *(sc);
+}
+#else
+void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)args;
+	struct sk_buff *skb;
+	while ((skb = skb_dequeue(skb_head))) {
+		struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+		struct ssv6200_tx_desc *tx_desc;
+		tx_desc = (struct ssv6200_tx_desc *)skb->data;
+		if (tx_desc->c_type > M2_TXREQ) {
+			ssv_skb_free(skb);
+			dev_dbg(sc->dev, "free cmd skb!\n");
+			continue;
+		}
+		if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
+			ssv6xxx_ampdu_sent(sc->hw, skb);
+		skb_queue_tail(&sc->tx_done_q, skb);
+	}
+	wake_up_interruptible(&sc->rx_wait_q);
+}
+#endif
+void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args)
+{
+	struct ieee80211_hdr *hdr;
+	struct ssv_softc *sc = args;
+	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+	struct ssv6200_tx_desc *tx_desc;
+	struct ssv_rate_info ssv_rate;
+	u32 nav = 0;
+	int ret = 0;
+	tx_desc = (struct ssv6200_tx_desc *)skb->data;
+	if (tx_desc->c_type > M2_TXREQ)
+		return;
+	if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) {
+		hdr = (struct ieee80211_hdr *)(skb->data + SSV6XXX_TX_DESC_LEN);
+		if ((ieee80211_is_data_qos(hdr->frame_control)
+		     || ieee80211_is_data(hdr->frame_control))
+		    && (tx_desc->wsid < SSV_RC_MAX_HARDWARE_SUPPORT)) {
+			ret =
+			    ssv6xxx_rc_hw_rate_update_check(skb, sc,
+							    tx_desc->
+							    do_rts_cts);
+			if (ret & RC_FIRMWARE_REPORT_FLAG) {
+				{
+					tx_desc->RSVD_0 = SSV6XXX_RC_REPORT;
+					tx_desc->tx_report = 1;
+				}
+				ret &= 0xf;
+			}
+			if (ret) {
+				ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
+				tx_desc->crate_idx = ssv_rate.crate_hw_idx;
+				tx_desc->drate_idx = ssv_rate.drate_hw_idx;
+				nav =
+				    ssv6xxx_set_frame_duration(info, &ssv_rate,
+							       skb->len +
+							       FCS_LEN, tx_desc,
+							       NULL, NULL);
+				if (tx_desc->tx_burst == 0) {
+					if (tx_desc->ack_policy != 0x01)
+						hdr->duration_id = nav;
+				}
+			}
+		}
+	} else {
+	}
+	return;
+}
+
+void ssv6xxx_update_txinfo(struct ssv_softc *sc, struct sk_buff *skb)
+{
+	struct ieee80211_hdr *hdr;
+	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+	struct ieee80211_sta *sta;
+	struct ssv_sta_info *sta_info = NULL;
+	struct ssv_sta_priv_data *ssv_sta_priv = NULL;
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)info->control.vif->drv_priv;
+	struct ssv6200_tx_desc *tx_desc = (struct ssv6200_tx_desc *)skb->data;
+	struct ieee80211_tx_rate *tx_drate;
+	struct ssv_rate_info ssv_rate;
+	int ac, hw_txqid;
+	u32 nav = 0;
+	if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+		struct ampdu_hdr_st *ampdu_hdr =
+		    (struct ampdu_hdr_st *)skb->head;
+		sta = ampdu_hdr->ampdu_tid->sta;
+		hdr =
+		    (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET +
+					     AMPDU_DELIMITER_LEN);
+	} else {
+		struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+		sta = skb_info->sta;
+		hdr = (struct ieee80211_hdr *)(skb->data + TXPB_OFFSET);
+	}
+	if (sta) {
+		ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+		sta_info = ssv_sta_priv->sta_info;
+	}
+	if ((!sc->bq4_dtim) &&
+	    (ieee80211_is_mgmt(hdr->frame_control) ||
+	     ieee80211_is_nullfunc(hdr->frame_control) ||
+	     ieee80211_is_qos_nullfunc(hdr->frame_control))) {
+		ac = 4;
+		hw_txqid = 4;
+	} else if ((sc->bq4_dtim) &&
+		   info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
+		hw_txqid = 4;
+		ac = 4;
+	} else {
+		ac = skb_get_queue_mapping(skb);
+		hw_txqid = sc->tx.hw_txqid[ac];
+	}
+	tx_drate = &info->control.rates[0];
+	ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
+	tx_desc->len = skb->len;
+	tx_desc->c_type = M2_TXREQ;
+	tx_desc->f80211 = 1;
+	tx_desc->qos = (ieee80211_is_data_qos(hdr->frame_control)) ? 1 : 0;
+	if (tx_drate->flags & IEEE80211_TX_RC_MCS) {
+		if (ieee80211_is_mgmt(hdr->frame_control) &&
+		    ieee80211_has_order(hdr->frame_control))
+			tx_desc->ht = 1;
+	}
+	tx_desc->use_4addr = (ieee80211_has_a4(hdr->frame_control)) ? 1 : 0;
+	tx_desc->more_data =
+	    (ieee80211_has_morefrags(hdr->frame_control)) ? 1 : 0;
+	tx_desc->stype_b5b4 = (cpu_to_le16(hdr->frame_control) >> 4) & 0x3;
+	tx_desc->frag = (tx_desc->more_data || (hdr->seq_ctrl & 0xf)) ? 1 : 0;
+	tx_desc->unicast = (is_multicast_ether_addr(hdr->addr1)) ? 0 : 1;
+	tx_desc->tx_burst = (tx_desc->frag) ? 1 : 0;
+	tx_desc->wsid = (!sta_info
+			 || (sta_info->hw_wsid < 0)) ? 0x0F : sta_info->hw_wsid;
+	tx_desc->txq_idx = hw_txqid;
+	tx_desc->hdr_offset = TXPB_OFFSET;
+	tx_desc->hdr_len = ssv6xxx_frame_hdrlen(hdr, tx_desc->ht);
+	tx_desc->payload_offset = tx_desc->hdr_offset + tx_desc->hdr_len;
+	if (info->control.use_rts)
+		tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS;
+	else if (info->control.use_cts_prot)
+		tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_CTS_PROTECT;
+	if (tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT)
+		tx_desc->do_rts_cts = IEEE80211_TX_RC_USE_RTS_CTS;
+	if (tx_desc->do_rts_cts == IEEE80211_TX_RC_USE_CTS_PROTECT) {
+		tx_desc->crate_idx = 0;
+	} else
+		tx_desc->crate_idx = ssv_rate.crate_hw_idx;
+	tx_desc->drate_idx = ssv_rate.drate_hw_idx;
+	if (tx_desc->unicast == 0)
+		tx_desc->ack_policy = 1;
+	else if (tx_desc->qos == 1)
+		tx_desc->ack_policy = (*ieee80211_get_qos_ctl(hdr) & 0x60) >> 5;
+	else if (ieee80211_is_ctl(hdr->frame_control))
+		tx_desc->ack_policy = 1;
+	tx_desc->security = 0;
+	tx_desc->fCmdIdx = 0;
+	tx_desc->fCmd = (hw_txqid + M_ENG_TX_EDCA0);
+	if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+#ifdef AMPDU_HAS_LEADING_FRAME
+		tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_CPU;
+#else
+		tx_desc->RSVD_1 = 1;
+#endif
+		tx_desc->aggregation = 1;
+		tx_desc->ack_policy = 0x01;
+		if ((tx_desc->do_rts_cts == 0)
+		    && ((sc->hw->wiphy->rts_threshold == (-1))
+			|| ((skb->len - sc->sh->tx_desc_len) >
+			    sc->hw->wiphy->rts_threshold))) {
+			tx_drate->flags |= IEEE80211_TX_RC_USE_RTS_CTS;
+			tx_desc->do_rts_cts = 1;
+		}
+	}
+	if (ieee80211_has_protected(hdr->frame_control)
+	    && (ieee80211_is_data_qos(hdr->frame_control)
+		|| ieee80211_is_data(hdr->frame_control))) {
+		if ((tx_desc->unicast && ssv_sta_priv
+		     && ssv_sta_priv->has_hw_encrypt)
+		    || (!tx_desc->unicast && vif_priv
+			&& vif_priv->has_hw_encrypt)) {
+			if (!tx_desc->unicast
+			    && !list_empty(&vif_priv->sta_list)) {
+				struct ssv_sta_priv_data *one_sta_priv;
+				int hw_wsid;
+				one_sta_priv =
+				    list_first_entry(&vif_priv->sta_list,
+						     struct ssv_sta_priv_data,
+						     list);
+				hw_wsid = one_sta_priv->sta_info->hw_wsid;
+				if (hw_wsid != (-1)) {
+					tx_desc->wsid = hw_wsid;
+				}
+			}
+			tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_ENCRYPT;
+		} else if (ssv_sta_priv->need_sw_encrypt) {
+		} else {
+		}
+	} else {
+	}
+	tx_desc->fCmd = (tx_desc->fCmd << 4) | M_ENG_HWHCI;
+	if (tx_desc->aggregation == 1) {
+		struct ampdu_hdr_st *ampdu_hdr =
+		    (struct ampdu_hdr_st *)skb->head;
+		memcpy(&tx_desc->rc_params[0], ampdu_hdr->rates,
+		       sizeof(tx_desc->rc_params));
+		nav =
+		    ssv6xxx_set_frame_duration(info, &ssv_rate,
+					       (skb->len + FCS_LEN), tx_desc,
+					       &tx_desc->rc_params[0], sc);
+#ifdef FW_RC_RETRY_DEBUG
+		{
+			dev_dbg
+			    (sc->dev, "[FW_RC]:param[0]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
+			     tx_desc->rc_params[0].drate,
+			     tx_desc->rc_params[0].count,
+			     tx_desc->rc_params[0].crate,
+			     tx_desc->rc_params[0].dl_length,
+			     tx_desc->rc_params[0].frame_consume_time,
+			     tx_desc->rc_params[0].rts_cts_nav);
+			dev_dbg
+			    (sc->dev, "[FW_RC]:param[1]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
+			     tx_desc->rc_params[1].drate,
+			     tx_desc->rc_params[1].count,
+			     tx_desc->rc_params[1].crate,
+			     tx_desc->rc_params[1].dl_length,
+			     tx_desc->rc_params[1].frame_consume_time,
+			     tx_desc->rc_params[1].rts_cts_nav);
+			dev_dbg
+			    (sc->dev, "[FW_RC]:param[2]: drate =%d, count =%d, crate=%d, dl_length =%d, frame_consume_time =%d, rts_cts_nav=%d\n",
+			     tx_desc->rc_params[2].drate,
+			     tx_desc->rc_params[2].count,
+			     tx_desc->rc_params[2].crate,
+			     tx_desc->rc_params[2].dl_length,
+			     tx_desc->rc_params[2].frame_consume_time,
+			     tx_desc->rc_params[2].rts_cts_nav);
+		}
+#endif
+	} else {
+		nav =
+		    ssv6xxx_set_frame_duration(info, &ssv_rate,
+					       (skb->len + FCS_LEN), tx_desc,
+					       NULL, NULL);
+	}
+	if ((tx_desc->aggregation == 0)) {
+		if (tx_desc->tx_burst == 0) {
+			if (tx_desc->ack_policy != 0x01)
+				hdr->duration_id = nav;
+		} else {
+		}
+	}
+}
+
+void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb)
+{
+	struct ssv6200_tx_desc *tx_desc;
+	skb_push(skb, sc->sh->tx_desc_len);
+	tx_desc = (struct ssv6200_tx_desc *)skb->data;
+	memset((void *)tx_desc, 0, sc->sh->tx_desc_len);
+	ssv6xxx_update_txinfo(sc, skb);
+}
+
+int ssv6xxx_get_real_index(struct ssv_softc *sc, struct sk_buff *skb)
+{
+	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+	struct ieee80211_tx_rate *tx_drate;
+	struct ssv_rate_info ssv_rate;
+	tx_drate = &info->control.rates[0];
+	ssv6xxx_rc_hw_rate_idx(sc, info, &ssv_rate);
+	return ssv_rate.drate_hw_idx;
+}
+
+static void _ssv6xxx_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+	struct ieee80211_vif *vif = info->control.vif;
+	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+	struct ssv6200_tx_desc *tx_desc;
+	int ret;
+	unsigned long flags;
+	bool send_hci = false;
+	do {
+		if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
+			if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
+				sc->tx.seq_no += 0x10;
+			hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
+			hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
+		}
+		if (info->flags & IEEE80211_TX_CTL_AMPDU) {
+			if (ssv6xxx_get_real_index(sc, skb) <
+			    SSV62XX_RATE_MCS_INDEX) {
+				info->flags &= (~IEEE80211_TX_CTL_AMPDU);
+				goto tx_mpdu;
+			}
+			if (ssv6200_ampdu_tx_handler(hw, skb)) {
+				break;
+			} else {
+				info->flags &= (~IEEE80211_TX_CTL_AMPDU);
+			}
+		}
+ tx_mpdu:
+		ssv6xxx_add_txinfo(sc, skb);
+		if (vif &&
+		    vif->type == NL80211_IFTYPE_AP &&
+		    (sc->bq4_dtim) &&
+		    info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
+			struct ssv_vif_priv_data *priv_vif =
+			    (struct ssv_vif_priv_data *)vif->drv_priv;
+			u8 buffered = 0;
+			spin_lock_irqsave(&sc->ps_state_lock, flags);
+			if (priv_vif->sta_asleep_mask) {
+				buffered =
+				    ssv6200_bcast_enqueue(sc, &sc->bcast_txq,
+							  skb);
+				if (1 == buffered) {
+					dev_dbg(sc->dev, "ssv6200_tx:ssv6200_bcast_start\n");
+					ssv6200_bcast_start(sc);
+				}
+			}
+			spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+			if (buffered)
+				break;
+		}
+		if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
+			struct ssv_vif_priv_data *vif_priv =
+			    (struct ssv_vif_priv_data *)vif->drv_priv;
+			dev_dbg(sc->dev, "vif[%d] sc->bq4_dtim[%d]\n",
+				vif_priv->vif_idx, sc->bq4_dtim);
+		}
+		tx_desc = (struct ssv6200_tx_desc *)skb->data;
+		ret = HCI_SEND(sc->sh, skb, tx_desc->txq_idx);
+		send_hci = true;
+	} while (0);
+	if ((skb_queue_len(&sc->tx_skb_q) < LOW_TX_Q_LEN)
+	    ) {
+		if (sc->tx.flow_ctrl_status != 0) {
+			int ac;
+			for (ac = 0; ac < sc->hw->queues; ac++) {
+				if ((sc->tx.flow_ctrl_status & BIT(ac)) == 0)
+					ieee80211_wake_queue(sc->hw, ac);
+			}
+		} else {
+			ieee80211_wake_queues(sc->hw);
+		}
+	}
+}
+
+static void ssv6200_tx(struct ieee80211_hw *hw,
+		       struct ieee80211_tx_control *control,
+		       struct sk_buff *skb)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)hw->priv;
+	struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+	skb_info->sta = control ? control->sta : NULL;
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+	skb_info->timestamp = ktime_get();
+#endif
+	skb_queue_tail(&sc->tx_skb_q, skb);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	if (sc->max_tx_skb_q_len < skb_queue_len(&sc->tx_skb_q))
+		sc->max_tx_skb_q_len = skb_queue_len(&sc->tx_skb_q);
+#endif
+	wake_up_interruptible(&sc->tx_wait_q);
+	do {
+		if (skb_queue_len(&sc->tx_skb_q) >= MAX_TX_Q_LEN)
+			ieee80211_stop_queues(sc->hw);
+	} while (0);
+}
+
+int ssv6xxx_tx_task(void *data)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)data;
+	u32 wait_period = SSV_AMPDU_timer_period / 2;
+	dev_info(sc->dev, "TX Task started\n");
+	while (!kthread_should_stop()) {
+		u32 before_timeout = (-1);
+		set_current_state(TASK_INTERRUPTIBLE);
+		before_timeout = wait_event_interruptible_timeout(sc->tx_wait_q,
+								  (skb_queue_len
+								   (&sc->
+								    tx_skb_q)
+								   ||
+								   kthread_should_stop
+								   ()
+								   || sc->
+								   tx_q_empty),
+								  msecs_to_jiffies
+								  (wait_period));
+		if (kthread_should_stop()) {
+			dev_dbg(sc->dev, "Quit TX task loop...\n");
+			break;
+		}
+		set_current_state(TASK_RUNNING);
+		do {
+			struct sk_buff *tx_skb = skb_dequeue(&sc->tx_skb_q);
+			if (tx_skb == NULL)
+				break;
+			_ssv6xxx_tx(sc->hw, tx_skb);
+		} while (1);
+#ifdef CONFIG_DEBUG_SKB_TIMESTAMP
+		{
+			struct ssv_hw_txq *hw_txq = NULL;
+			struct ieee80211_tx_info *tx_info = NULL;
+			struct sk_buff *skb = NULL;
+			int txqid;
+			unsigned int timeout;
+			u32 status;
+			for (txqid = 0; txqid < SSV_HW_TXQ_NUM; txqid++) {
+				hw_txq = &ssv_dbg_ctrl_hci->hw_txq[txqid];
+				skb = skb_peek(&hw_txq->qhead);
+				if (skb != NULL) {
+					tx_info = IEEE80211_SKB_CB(skb);
+					if (tx_info->
+					    flags & IEEE80211_TX_CTL_AMPDU)
+						timeout =
+						    cal_duration_of_ampdu(skb,
+									  SKB_DURATION_STAGE_IN_HWQ);
+					else
+						timeout =
+						    cal_duration_of_mpdu(skb);
+					if (timeout > SKB_DURATION_TIMEOUT_MS) {
+						HCI_IRQ_STATUS(ssv_dbg_ctrl_hci,
+							       &status);
+						dev_dbg(sc->dev, "hci int_mask: %08x\n",
+						       ssv_dbg_ctrl_hci->
+						       int_mask);
+						dev_dbg(sc->dev, "sdio status: %08x\n",
+						       status);
+						dev_dbg(sc->dev, "hwq%d len: %d\n", txqid,
+						       skb_queue_len(&hw_txq->
+								     qhead));
+					}
+				}
+			}
+		}
+#endif
+		if (sc->tx_q_empty || (before_timeout == 0)) {
+			u32 flused_ampdu = ssv6xxx_ampdu_flush(sc->hw);
+			sc->tx_q_empty = false;
+			if (flused_ampdu == 0 && before_timeout == 0) {
+				wait_period *= 2;
+				if (wait_period > 1000)
+					wait_period = 1000;
+			}
+		} else
+			wait_period = SSV_AMPDU_timer_period / 2;
+	}
+	return 0;
+}
+
+int ssv6xxx_rx_task(void *data)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)data;
+	unsigned long wait_period = msecs_to_jiffies(200);
+	unsigned long last_timeout_check_jiffies = jiffies;
+	unsigned long cur_jiffies;
+	dev_info(sc->dev, "RX Task started\n");
+	while (!kthread_should_stop()) {
+		u32 before_timeout = (-1);
+		set_current_state(TASK_INTERRUPTIBLE);
+		before_timeout = wait_event_interruptible_timeout(sc->rx_wait_q,
+								  (skb_queue_len
+								   (&sc->
+								    rx_skb_q)
+								   ||
+								   skb_queue_len
+								   (&sc->
+								    tx_done_q)
+								   ||
+								   kthread_should_stop
+								   ()),
+								  wait_period);
+		if (kthread_should_stop()) {
+			dev_dbg(sc->dev, "Quit RX task loop...\n");
+			break;
+		}
+		set_current_state(TASK_RUNNING);
+		cur_jiffies = jiffies;
+		if ((before_timeout == 0)
+		    || time_before((last_timeout_check_jiffies + wait_period),
+				   cur_jiffies)) {
+			ssv6xxx_ampdu_check_timeout(sc->hw);
+			last_timeout_check_jiffies = cur_jiffies;
+		}
+		if (skb_queue_len(&sc->rx_skb_q))
+			_process_rx_q(sc, &sc->rx_skb_q, NULL);
+		if (skb_queue_len(&sc->tx_done_q))
+			_process_tx_done(sc);
+	}
+	return 0;
+}
+
+struct ssv6xxx_iqk_cfg init_iqk_cfg = {
+	SSV6XXX_IQK_CFG_XTAL_26M,
+#ifdef CONFIG_SSV_DPD
+	SSV6XXX_IQK_CFG_PA_LI_MPB,
+#else
+	SSV6XXX_IQK_CFG_PA_DEF,
+#endif
+	0,
+	0,
+	26,
+	3,
+	0x75,
+	0x75,
+	0x80,
+	0x80,
+	SSV6XXX_IQK_CMD_INIT_CALI,
+	{SSV6XXX_IQK_TEMPERATURE
+	 + SSV6XXX_IQK_RXDC
+	 + SSV6XXX_IQK_RXRC
+	 + SSV6XXX_IQK_TXDC + SSV6XXX_IQK_TXIQ + SSV6XXX_IQK_RXIQ
+#ifdef CONFIG_SSV_DPD
+	 + SSV6XXX_IQK_PAPD
+#endif
+	 },
+};
+
+static int ssv6200_start(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_hw *sh = sc->sh;
+	struct ieee80211_channel *chan;
+    int ret;
+    
+	mutex_lock(&sc->mutex);
+    ret = ssv6xxx_init_mac(sc->sh);
+	if (ret != 0) {
+		dev_err(sc->dev, "Failed to initialize mac, ret=%d\n", ret);
+		ssv6xxx_deinit_mac(sc);
+		mutex_unlock(&sc->mutex);
+		return -1;
+	}
+#ifdef CONFIG_P2P_NOA
+	ssv6xxx_noa_reset(sc);
+#endif
+	HCI_START(sh);
+	ieee80211_wake_queues(hw);
+	ssv6200_ampdu_init(hw);
+	sc->watchdog_flag = WD_KICKED;
+	mutex_unlock(&sc->mutex);
+	mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
+#ifdef CONFIG_SSV_SMARTLINK
+	{
+		extern int ksmartlink_init(void);
+		(void)ksmartlink_init();
+	}
+#endif
+    ret = ssv6xxx_do_iq_calib(sc->sh, &init_iqk_cfg);
+    if (ret != 0) {
+        dev_err(sc->dev, "IQ Calibration failed, ret=%d\n", ret);
+        return ret;
+    }
+
+	dev_info(sc->dev, "Calibration successful\n");
+
+	SMAC_REG_WRITE(sc->sh, ADR_PHY_EN_1, 0x217f);
+	if ((sh->cfg.chip_identity == SSV6051Z)
+	    || (sc->sh->cfg.chip_identity == SSV6051P)) {
+		int i;
+		for (i = 0; i < sh->ch_cfg_size; i++) {
+			SMAC_REG_READ(sh, sh->p_ch_cfg[i].reg_addr,
+				      &sh->p_ch_cfg[i].ch1_12_value);
+		}
+	}
+	chan = hw->conf.chandef.chan;
+	sc->cur_channel = chan;
+	dev_dbg(sc->dev, "%s(): current channel: %d,sc->ps_status=%d\n", __FUNCTION__,
+	       sc->cur_channel->hw_value, sc->ps_status);
+	ssv6xxx_set_channel(sc, chan->hw_value);
+	ssv6xxx_rf_enable(sh);
+	return 0;
+}
+
+static void ssv6200_stop(struct ieee80211_hw *hw)
+{
+	struct ssv_softc *sc = hw->priv;
+	u32 count = 0;
+	struct rssi_res_st *rssi_tmp0, *rssi_tmp1;
+	dev_dbg(sc->dev, "%s(): sc->ps_status=%d\n", __FUNCTION__,
+	       sc->ps_status);
+	mutex_lock(&sc->mutex);
+	list_for_each_entry_safe(rssi_tmp0, rssi_tmp1, &rssi_res.rssi_list,
+				 rssi_list) {
+		list_del(&rssi_tmp0->rssi_list);
+		kfree(rssi_tmp0);
+	}
+	ssv6200_ampdu_deinit(hw);
+	ssv6xxx_rf_disable(sc->sh);
+	HCI_STOP(sc->sh);
+#ifndef NO_USE_RXQ_LOCK
+	while (0) {
+#else
+	while (skb_queue_len(&sc->rx.rxq_head)) {
+#endif
+		dev_dbg(sc->dev, "sc->rx.rxq_count=%d\n", sc->rx.rxq_count);
+		count++;
+		if (count > 90000000) {
+			dev_err(sc->dev, "Could not empty RX queue during shutdown\n");
+			break;
+		}
+	}
+	HCI_TXQ_FLUSH(sc->sh, (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2 |
+			       TXQ_EDCA_3 | TXQ_MGMT));
+	if ((sc->ps_status == PWRSV_PREPARE) || (sc->ps_status == PWRSV_ENABLE)) {
+		ssv6xxx_enable_ps(sc);
+		ssv6xxx_rf_enable(sc->sh);
+	}
+	sc->watchdog_flag = WD_SLEEP;
+	mutex_unlock(&sc->mutex);
+	del_timer_sync(&sc->watchdog_timeout);
+#ifdef CONFIG_SSV_SMARTLINK
+	{
+		extern void ksmartlink_exit(void);
+		ksmartlink_exit();
+	}
+#endif
+	dev_dbg(sc->dev, "%s(): leave\n", __FUNCTION__);
+}
+
+void inline ssv62xxx_set_bssid(struct ssv_softc *sc, u8 * bssid)
+{
+	memcpy(sc->bssid, bssid, 6);
+	SMAC_REG_WRITE(sc->sh, ADR_BSSID_0, *((u32 *) & sc->bssid[0]));
+	SMAC_REG_WRITE(sc->sh, ADR_BSSID_1, *((u32 *) & sc->bssid[4]));
+}
+
+struct ssv_vif_priv_data *ssv6xxx_config_vif_res(struct ssv_softc *sc,
+						 struct ieee80211_vif *vif)
+{
+	int i;
+	struct ssv_vif_priv_data *priv_vif;
+	struct ssv_vif_info *vif_info;
+	lockdep_assert_held(&sc->mutex);
+	for (i = 0; i < SSV6200_MAX_VIF; i++) {
+		if (sc->vif_info[i].vif == NULL)
+			break;
+	}
+	BUG_ON(i >= SSV6200_MAX_VIF);
+	dev_dbg(sc->dev, "ssv6xxx_config_vif_res id[%d].\n", i);
+	priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
+	memset(priv_vif, 0, sizeof(struct ssv_vif_priv_data));
+	priv_vif->vif_idx = i;
+	memset(&sc->vif_info[i], 0, sizeof(sc->vif_info[0]));
+	sc->vif_info[i].vif = vif;
+	sc->vif_info[i].vif_priv = priv_vif;
+	INIT_LIST_HEAD(&priv_vif->sta_list);
+	priv_vif->pair_cipher = SSV_CIPHER_NONE;
+	priv_vif->group_cipher = SSV_CIPHER_NONE;
+	priv_vif->has_hw_decrypt = false;
+	priv_vif->has_hw_encrypt = false;
+	priv_vif->need_sw_encrypt = false;
+	priv_vif->need_sw_decrypt = false;
+	priv_vif->use_mac80211_decrypt = false;
+	priv_vif->is_security_valid = false;
+	priv_vif->force_sw_encrypt = (vif->type == NL80211_IFTYPE_AP);
+	vif_info = &sc->vif_info[priv_vif->vif_idx];
+	vif_info->if_type = vif->type;
+	vif_info->vif = vif;
+	return priv_vif;
+}
+
+static int ssv6200_add_interface(struct ieee80211_hw *hw,
+				 struct ieee80211_vif *vif)
+{
+	struct ssv_softc *sc = hw->priv;
+	int ret = 0;
+	struct ssv_vif_priv_data *vif_priv = NULL;
+	dev_dbg(sc->dev, "[I] %s(): vif->type = %d, NL80211_IFTYPE_AP=%d\n", __FUNCTION__,
+	       vif->type, NL80211_IFTYPE_AP);
+	if ((sc->nvif >= SSV6200_MAX_VIF)
+	    || (((vif->type == NL80211_IFTYPE_AP)
+		 || (vif->p2p))
+		&& (sc->ap_vif != NULL))) {
+		dev_err(sc->dev, "Add interface of type %d (p2p: %d) failed.\n",
+			vif->type, vif->p2p);
+		return -EOPNOTSUPP;
+	}
+	mutex_lock(&sc->mutex);
+	vif_priv = ssv6xxx_config_vif_res(sc, vif);
+	if ((vif_priv->vif_idx == 0) && (vif->p2p == 0)
+	    && (vif->type == NL80211_IFTYPE_AP)) {
+		dev_dbg(sc->dev, "VIF[0] set bssid and config opmode to ap\n");
+		ssv62xxx_set_bssid(sc, sc->sh->cfg.maddr[0]);
+		SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, SSV6200_OPMODE_AP,
+				  OP_MODE_MSK);
+	}
+	if (vif->type == NL80211_IFTYPE_AP) {
+		BUG_ON(sc->ap_vif != NULL);
+		sc->ap_vif = vif;
+		if (!vif->p2p && (vif_priv->vif_idx == 0)) {
+			dev_dbg(sc->dev, "Normal AP mode. Config Q4 to DTIM Q.\n");
+			SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC,
+					  MTX_HALT_MNG_UNTIL_DTIM_MSK,
+					  MTX_HALT_MNG_UNTIL_DTIM_MSK);
+			sc->bq4_dtim = true;
+		}
+	}
+	sc->nvif++;
+	dev_dbg(sc->dev,
+		"VIF %02x:%02x:%02x:%02x:%02x:%02x of type %d is added.\n",
+		vif->addr[0], vif->addr[1], vif->addr[2], vif->addr[3],
+		vif->addr[4], vif->addr[5], vif->type);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	ssv6xxx_debugfs_add_interface(sc, vif);
+#endif
+	mutex_unlock(&sc->mutex);
+	return ret;
+}
+
+static void ssv6200_remove_interface(struct ieee80211_hw *hw,
+				     struct ieee80211_vif *vif)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	dev_err(sc->dev,
+		"Removing interface %02x:%02x:%02x:%02x:%02x:%02x. PS=%d\n",
+		vif->addr[0], vif->addr[1], vif->addr[2], vif->addr[3],
+		vif->addr[4], vif->addr[5], sc->ps_status);
+	mutex_lock(&sc->mutex);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	ssv6xxx_debugfs_remove_interface(sc, vif);
+#endif
+	if (vif->type == NL80211_IFTYPE_AP) {
+		if (sc->bq4_dtim) {
+			sc->bq4_dtim = false;
+			ssv6200_release_bcast_frame_res(sc, vif);
+			SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC,
+					  0, MTX_HALT_MNG_UNTIL_DTIM_MSK);
+			dev_dbg(sc->dev, "Config Q4 to normal Q \n");
+		}
+		ssv6xxx_beacon_release(sc);
+		sc->ap_vif = NULL;
+	}
+	memset(&sc->vif_info[vif_priv->vif_idx], 0,
+	       sizeof(struct ssv_vif_info));
+	sc->nvif--;
+	mutex_unlock(&sc->mutex);
+}
+
+static int ssv6200_change_interface(struct ieee80211_hw *dev,
+				    struct ieee80211_vif *vif,
+				    enum nl80211_iftype new_type, bool p2p)
+{
+    struct ssv_softc *sc = dev->priv;
+	int ret = 0;
+    
+	dev_dbg(sc->dev, "change_interface new: %d (%d), old: %d (%d)\n", new_type,
+	       p2p, vif->type, vif->p2p);
+
+	if (new_type != vif->type || vif->p2p != p2p) {
+		ssv6200_remove_interface(dev, vif);
+		vif->type = new_type;
+		vif->p2p = p2p;
+		ret = ssv6200_add_interface(dev, vif);
+	}
+
+	return ret;
+}
+
+void ssv6xxx_ps_callback_func(unsigned long data)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)data;
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	int retry_cnt = 20;
+#ifdef SSV_WAKEUP_HOST
+	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
+		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
+	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
+	SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + 6 * 4,
+		       (sc->mac_deci_tbl[6] | 1));
+#else
+	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
+		       M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
+	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+		       M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
+	SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
+		       M_ENG_MACRX | (M_ENG_TRASH_CAN << 4));
+#endif
+	skb = ssv_skb_alloc(sizeof(struct cfg_host_cmd));
+	skb->data_len = sizeof(struct cfg_host_cmd);
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->RSVD0 = 0;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_PS;
+	host_cmd->len = skb->data_len;
+#ifdef SSV_WAKEUP_HOST
+	host_cmd->dummy = sc->ps_aid;
+#else
+	host_cmd->dummy = 0;
+#endif
+	sc->ps_aid = 0;
+	while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
+		dev_warn(sc->dev, "PS cmd retry=%d!!\n", retry_cnt);
+		retry_cnt--;
+	}
+	ssv_skb_free(skb);
+	dev_dbg(sc->dev, "SSV6XXX_HOST_CMD_PS,ps_aid = %d,len=%d,tabl=0x%x\n",
+	       host_cmd->dummy, skb->len, (sc->mac_deci_tbl[6] | 1));
+}
+
+void ssv6xxx_enable_ps(struct ssv_softc *sc)
+{
+	sc->ps_status = PWRSV_ENABLE;
+}
+
+void ssv6xxx_disable_ps(struct ssv_softc *sc)
+{
+	sc->ps_status = PWRSV_DISABLE;
+	dev_info(sc->dev, "Power saving disabled\n");
+}
+
+int ssv6xxx_watchdog_controller(struct ssv_hw *sh, u8 flag)
+{
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	int ret = 0;
+	dev_dbg(sh->sc->dev, "ssv6xxx_watchdog_controller %d\n", flag);
+	skb = ssv_skb_alloc(HOST_CMD_HDR_LEN);
+	if (skb == NULL) {
+		dev_warn(sh->sc->dev, "init ssv6xxx_watchdog_controller fail!!!\n");
+		return (-1);
+	}
+	skb->data_len = HOST_CMD_HDR_LEN;
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) flag;
+	host_cmd->len = skb->data_len;
+	sh->hci.hci_ops->hci_send_cmd(skb);
+	ssv_skb_free(skb);
+	return ret;
+}
+
+static int ssv6200_config(struct ieee80211_hw *hw, u32 changed)
+{
+	struct ssv_softc *sc = hw->priv;
+	int ret = 0;
+	mutex_lock(&sc->mutex);
+	if (changed & IEEE80211_CONF_CHANGE_PS) {
+		struct ieee80211_conf *conf = &hw->conf;
+		if (conf->flags & IEEE80211_CONF_PS) {
+			dev_dbg(sc->dev, "Enable IEEE80211_CONF_PS ps_aid=%d\n",
+			       sc->ps_aid);
+		} else {
+			dev_dbg(sc->dev, "Disable IEEE80211_CONF_PS ps_aid=%d\n",
+			       sc->ps_aid);
+		}
+	}
+	if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
+		struct ieee80211_channel *chan;
+		chan = hw->conf.chandef.chan;
+#ifdef CONFIG_P2P_NOA
+		if (sc->p2p_noa.active_noa_vif) {
+			dev_dbg(sc->dev, "NOA operating-active vif[%02x] skip scan\n",
+			       sc->p2p_noa.active_noa_vif);
+			goto out;
+		}
+#endif
+		if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) {
+			if ((sc->ap_vif == NULL)
+			    ||
+			    list_empty(&
+				       ((struct ssv_vif_priv_data *)sc->ap_vif->
+					drv_priv)->sta_list)) {
+				HCI_PAUSE(sc->sh,
+					  (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
+					   | TXQ_EDCA_3 | TXQ_MGMT));
+				sc->sc_flags |= SC_OP_OFFCHAN;
+				ssv6xxx_set_channel(sc, chan->hw_value);
+				sc->hw_chan = chan->hw_value;
+				HCI_RESUME(sc->sh, TXQ_MGMT);
+			} else {
+				dev_dbg(sc->dev,
+					"Off-channel to %d is ignored when AP mode enabled.\n",
+					chan->hw_value);
+			}
+		} else {
+			if ((sc->cur_channel == NULL)
+			    || (sc->sc_flags & SC_OP_OFFCHAN)
+			    || (sc->hw_chan != chan->hw_value)) {
+				HCI_PAUSE(sc->sh,
+					  (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
+					   | TXQ_EDCA_3 | TXQ_MGMT));
+				ssv6xxx_set_channel(sc, chan->hw_value);
+				sc->cur_channel = chan;
+				HCI_RESUME(sc->sh,
+					   (TXQ_EDCA_0 | TXQ_EDCA_1 | TXQ_EDCA_2
+					    | TXQ_EDCA_3 | TXQ_MGMT));
+				sc->sc_flags &= ~SC_OP_OFFCHAN;
+			} else {
+				dev_dbg(sc->dev,
+					"Change to the same channel %d\n",
+					chan->hw_value);
+			}
+		}
+	}
+#ifdef CONFIG_P2P_NOA
+ out:
+#endif
+	mutex_unlock(&sc->mutex);
+	return ret;
+}
+
+#define SUPPORTED_FILTERS \
+    (FIF_ALLMULTI | \
+    FIF_CONTROL | \
+    FIF_PSPOLL | \
+    FIF_OTHER_BSS | \
+    FIF_BCN_PRBRESP_PROMISC | \
+    FIF_PROBE_REQ | \
+    FIF_FCSFAIL)
+static void ssv6200_config_filter(struct ieee80211_hw *hw,
+				  unsigned int changed_flags,
+				  unsigned int *total_flags, u64 multicast)
+{
+	changed_flags &= SUPPORTED_FILTERS;
+	*total_flags &= SUPPORTED_FILTERS;
+}
+
+static void ssv6200_bss_info_changed(struct ieee80211_hw *hw,
+				     struct ieee80211_vif *vif,
+				     struct ieee80211_bss_conf *info,
+				     u32 changed)
+{
+	struct ssv_vif_priv_data *priv_vif = (struct ssv_vif_priv_data *)vif->drv_priv;
+	struct ssv_softc *sc = hw->priv;
+#ifdef CONFIG_P2P_NOA
+	u8 null_address[6] = { 0 };
+#endif
+	mutex_lock(&sc->mutex);
+	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
+		dev_dbg(sc->dev, "BSS Changed use_short_preamble[%d]\n",
+		       info->use_short_preamble);
+		if (info->use_short_preamble)
+			sc->sc_flags |= SC_OP_SHORT_PREAMBLE;
+		else
+			sc->sc_flags &= ~SC_OP_SHORT_PREAMBLE;
+	}
+	if (!priv_vif->vif_idx) {
+		if (changed & BSS_CHANGED_BSSID) {
+#ifdef CONFIG_P2P_NOA
+			struct ssv_vif_priv_data *vif_priv;
+			vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+#endif
+			ssv62xxx_set_bssid(sc, (u8 *) info->bssid);
+			dev_dbg(sc->dev, "BSS_CHANGED_BSSID: %02x:%02x:%02x:%02x:%02x:%02x\n",
+			     info->bssid[0], info->bssid[1], info->bssid[2],
+			     info->bssid[3], info->bssid[4], info->bssid[5]);
+#ifdef CONFIG_P2P_NOA
+			if (memcmp(info->bssid, null_address, 6))
+				ssv6xxx_noa_hdl_bss_change(sc,
+							   MONITOR_NOA_CONF_ADD,
+							   vif_priv->vif_idx);
+			else
+				ssv6xxx_noa_hdl_bss_change(sc,
+							   MONITOR_NOA_CONF_REMOVE,
+							   vif_priv->vif_idx);
+#endif
+		}
+		if (changed & BSS_CHANGED_ERP_SLOT) {
+			u32 regval = 0;
+			dev_dbg(sc->dev, "BSS_CHANGED_ERP_SLOT: use_short_slot[%d]\n",
+			       info->use_short_slot);
+			if (info->use_short_slot) {
+				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_IFS, &regval);
+				regval = regval & MTX_DUR_SLOT_I_MSK;
+				regval |= 9 << MTX_DUR_SLOT_SFT;
+				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_IFS, regval);
+				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_SIFS_G,
+					      &regval);
+				regval = regval & MTX_DUR_BURST_SIFS_G_I_MSK;
+				regval |= 0xa << MTX_DUR_BURST_SIFS_G_SFT;
+				regval = regval & MTX_DUR_SLOT_G_I_MSK;
+				regval |= 9 << MTX_DUR_SLOT_G_SFT;
+				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_SIFS_G,
+					       regval);
+			} else {
+				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_IFS, &regval);
+				regval = regval & MTX_DUR_SLOT_I_MSK;
+				regval |= 20 << MTX_DUR_SLOT_SFT;
+				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_IFS, regval);
+				SMAC_REG_READ(sc->sh, ADR_MTX_DUR_SIFS_G,
+					      &regval);
+				regval = regval & MTX_DUR_BURST_SIFS_G_I_MSK;
+				regval |= 0xa << MTX_DUR_BURST_SIFS_G_SFT;
+				regval = regval & MTX_DUR_SLOT_G_I_MSK;
+				regval |= 20 << MTX_DUR_SLOT_G_SFT;
+				SMAC_REG_WRITE(sc->sh, ADR_MTX_DUR_SIFS_G,
+					       regval);
+			}
+		}
+	}
+	if (changed & BSS_CHANGED_HT) {
+		dev_dbg(sc->dev, "BSS_CHANGED_HT: Untreated!!\n");
+	}
+	if (changed & BSS_CHANGED_BASIC_RATES) {
+		dev_dbg(sc->dev, "ssv6xxx_rc_update_basic_rate!!\n");
+		ssv6xxx_rc_update_basic_rate(sc, info->basic_rates);
+	}
+	if (vif->type == NL80211_IFTYPE_STATION) {
+		dev_dbg(sc->dev, "NL80211_IFTYPE_STATION!!\n");
+		if ((changed & BSS_CHANGED_ASSOC) && (vif->p2p == 0)) {
+			sc->isAssoc = info->assoc;
+			if (!sc->isAssoc) {
+				sc->channel_center_freq = 0;
+				sc->ps_aid = 0;
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x0400);
+#endif
+				SMAC_REG_WRITE(sc->sh, ADR_RX_11B_CCA_CONTROL,
+					       0x0);
+			} else {
+				struct ieee80211_channel *curchan;
+				curchan = hw->conf.chandef.chan;
+				sc->channel_center_freq = curchan->center_freq;
+				dev_dbg(sc->dev, "info->aid = %d\n", info->aid);
+				sc->ps_aid = info->aid;
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x1000);
+#endif
+			}
+		}
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+		else if ((changed & BSS_CHANGED_ASSOC) && vif->p2p == 1) {
+			if (info->assoc)
+				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x0400);
+			else if (sc->ps_aid != 0)
+				SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_EN3, 0x1000);
+		}
+#endif
+	}
+	if (vif->type == NL80211_IFTYPE_AP) {
+		if (changed & (BSS_CHANGED_BEACON
+			       | BSS_CHANGED_SSID
+			       | BSS_CHANGED_BSSID | BSS_CHANGED_BASIC_RATES)) {
+#ifdef BROADCAST_DEBUG
+			dev_dbg(sc->dev, "[A] ssv6200_bss_info_changed:beacon changed\n");
+#endif
+			queue_work(sc->config_wq, &sc->set_tim_work);
+		}
+		if (changed & BSS_CHANGED_BEACON_INT) {
+			dev_dbg(sc->dev, "[A] BSS_CHANGED_BEACON_INT beacon_interval(%d)\n",
+			     info->beacon_int);
+			if (sc->beacon_interval != info->beacon_int) {
+				sc->beacon_interval = info->beacon_int;
+				ssv6xxx_beacon_set_info(sc, sc->beacon_interval,
+							sc->beacon_dtim_cnt);
+			}
+		}
+		if (changed & BSS_CHANGED_BEACON_ENABLED) {
+#ifdef BEACON_DEBUG
+			dev_dbg(sc->dev, "[A] BSS_CHANGED_BEACON_ENABLED (0x%x)\n",
+			       info->enable_beacon);
+#endif
+			if (0 != ssv6xxx_beacon_enable(sc, info->enable_beacon)) {
+				dev_err(sc->dev, "Beacon enable %d error.\n",
+					info->enable_beacon);
+			}
+		}
+	}
+	mutex_unlock(&sc->mutex);
+	dev_dbg(sc->dev, "[I] %s(): leave\n", __FUNCTION__);
+}
+
+static int ssv6200_sta_add(struct ieee80211_hw *hw,
+			   struct ieee80211_vif *vif, struct ieee80211_sta *sta)
+{
+	struct ssv_sta_priv_data *sta_priv_dat = NULL;
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_sta_info *sta_info;
+	u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
+	int s, i;
+	u32 reg_wsid_tid0[] = { ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ };
+	u32 reg_wsid_tid7[] = { ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ };
+	unsigned long flags;
+	int ret = 0;
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	int fw_sec_caps = SSV6XXX_WSID_SEC_NONE;
+	bool tdls_use_sw_cipher = false, tdls_link = false;
+	dev_dbg(sc->dev, "[I] %s(): vif[%d] ", __FUNCTION__, vif_priv->vif_idx);
+	if (sc->force_triger_reset == true) {
+		vif_priv->sta_asleep_mask = 0;
+		do {
+			spin_lock_irqsave(&sc->ps_state_lock, flags);
+			for (s = 0; s < SSV_NUM_STA; s++, sta_info++) {
+				sta_info = &sc->sta_info[s];
+				if ((sta_info->s_flags & STA_FLAG_VALID)) {
+					if (sta_info->sta == sta) {
+						dev_dbg
+						    (sc->dev, "search stat %02x:%02x:%02x:%02x:%02x:%02x to  wsid=%d\n",
+						     sta->addr[0], sta->addr[1],
+						     sta->addr[2], sta->addr[3],
+						     sta->addr[4], sta->addr[5],
+						     sta_info->hw_wsid);
+						spin_unlock_irqrestore(&sc->
+								       ps_state_lock,
+								       flags);
+						return ret;
+					}
+				}
+			}
+			spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+			if (s >= SSV_NUM_STA) {
+				break;
+			}
+		} while (0);
+	}
+	do {
+		spin_lock_irqsave(&sc->ps_state_lock, flags);
+		if (!list_empty(&vif_priv->sta_list)
+		    && vif->type == NL80211_IFTYPE_STATION) {
+			tdls_link = true;
+		}
+		if ((tdls_link) && (vif_priv->pair_cipher != SSV_CIPHER_NONE)
+		    && (vif_priv->pair_cipher != SSV_CIPHER_CCMP)
+		    && (sc->sh->cfg.use_wpa2_only == false)) {
+			tdls_use_sw_cipher = true;
+		}
+		if (((vif_priv->vif_idx == 0) && (tdls_use_sw_cipher == false))
+		    || sc->sh->cfg.use_wpa2_only)
+			s = 0;
+		else
+			s = 2;
+		for (; s < SSV_NUM_STA; s++) {
+			sta_info = &sc->sta_info[s];
+			if ((sta_info->s_flags & STA_FLAG_VALID) == 0) {
+				sta_info->aid = sta->aid;
+				sta_info->sta = sta;
+				sta_info->vif = vif;
+				sta_info->s_flags = STA_FLAG_VALID;
+				sta_priv_dat =
+				    (struct ssv_sta_priv_data *)sta->drv_priv;
+				sta_priv_dat->sta_idx = s;
+				sta_priv_dat->sta_info = sta_info;
+				sta_priv_dat->has_hw_encrypt = false;
+				sta_priv_dat->has_hw_decrypt = false;
+				sta_priv_dat->need_sw_decrypt = false;
+				sta_priv_dat->need_sw_encrypt = false;
+				sta_priv_dat->use_mac80211_decrypt = false;
+				if ((vif_priv->pair_cipher == SSV_CIPHER_WEP40)
+				    || (vif_priv->pair_cipher ==
+					SSV_CIPHER_WEP104)) {
+					sta_priv_dat->has_hw_encrypt =
+					    vif_priv->has_hw_encrypt;
+					sta_priv_dat->has_hw_decrypt =
+					    vif_priv->has_hw_decrypt;
+					sta_priv_dat->need_sw_encrypt =
+					    vif_priv->need_sw_encrypt;
+					sta_priv_dat->need_sw_decrypt =
+					    vif_priv->need_sw_decrypt;
+				}
+				list_add_tail(&sta_priv_dat->list,
+					      &vif_priv->sta_list);
+				break;
+			}
+		}
+		spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+		if (s >= SSV_NUM_STA) {
+			dev_err(sc->dev,
+				"Number of STA exceeds driver limitation %d\n.",
+				SSV_NUM_STA);
+			ret = -1;
+			break;
+		}
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+		ssv6xxx_debugfs_add_sta(sc, sta_info);
+#endif
+		sta_info->hw_wsid = -1;
+		if (sta_priv_dat->sta_idx < SSV_NUM_HW_STA) {
+			SMAC_REG_WRITE(sc->sh, reg_wsid[s] + 4,
+				       *((u32 *) & sta->addr[0]));
+			SMAC_REG_WRITE(sc->sh, reg_wsid[s] + 8,
+				       *((u32 *) & sta->addr[4]));
+			SMAC_REG_WRITE(sc->sh, reg_wsid[s], 1);
+			for (i = reg_wsid_tid0[s]; i <= reg_wsid_tid7[s];
+			     i += 4)
+				SMAC_REG_WRITE(sc->sh, i, 0);
+			ssv6xxx_rc_hw_reset(sc, sta_priv_dat->rc_idx, s);
+			sta_info->hw_wsid = sta_priv_dat->sta_idx;
+		} else if ((vif_priv->vif_idx == 0)
+			   || sc->sh->cfg.use_wpa2_only) {
+			sta_info->hw_wsid = sta_priv_dat->sta_idx;
+		}
+		if ((sta_priv_dat->has_hw_encrypt
+		     || sta_priv_dat->has_hw_decrypt)
+		    && ((vif_priv->pair_cipher == SSV_CIPHER_WEP40)
+			|| (vif_priv->pair_cipher == SSV_CIPHER_WEP104))) {
+			struct ssv_vif_info *vif_info =
+			    &sc->vif_info[vif_priv->vif_idx];
+			struct ssv6xxx_hw_sec *sramKey = &vif_info->sramKey;
+			_set_wep_hw_crypto_pair_key(sc, vif_info, sta_info,
+						    (void *)sramKey);
+			if (sramKey->sta_key[0].pair_key_idx != 0) {
+				_set_wep_hw_crypto_group_key(sc, vif_info,
+							     sta_info,
+							     (void *)sramKey);
+			}
+		}
+		ssv6200_ampdu_tx_add_sta(hw, sta);
+		if (sta_info->hw_wsid >= SSV_NUM_HW_STA) {
+			if (sta_priv_dat->has_hw_decrypt)
+				fw_sec_caps = SSV6XXX_WSID_SEC_PAIRWISE;
+			if (vif_priv->has_hw_decrypt)
+				fw_sec_caps |= SSV6XXX_WSID_SEC_GROUP;
+			hw_update_watch_wsid(sc, sta, sta_info,
+					     sta_priv_dat->sta_idx, fw_sec_caps,
+					     SSV6XXX_WSID_OPS_ADD);
+		} else if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx)) {
+			hw_update_watch_wsid(sc, sta, sta_info,
+					     sta_priv_dat->sta_idx,
+					     SSV6XXX_WSID_SEC_SW,
+					     SSV6XXX_WSID_OPS_HWWSID_PAIRWISE_SET_TYPE);
+			hw_update_watch_wsid(sc, sta, sta_info,
+					     sta_priv_dat->sta_idx,
+					     SSV6XXX_WSID_SEC_SW,
+					     SSV6XXX_WSID_OPS_HWWSID_GROUP_SET_TYPE);
+		}
+		dev_dbg
+		    (sc->dev, "Add %02x:%02x:%02x:%02x:%02x:%02x to VIF %d sw_idx=%d, wsid=%d\n",
+		     sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+		     sta->addr[4], sta->addr[5], vif_priv->vif_idx,
+		     sta_priv_dat->sta_idx, sta_info->hw_wsid);
+	} while (0);
+	return ret;
+}
+
+void ssv6200_rx_flow_check(struct ssv_sta_priv_data *sta_priv_dat,
+			   struct ssv_softc *sc)
+{
+	if (SSV6200_USE_HW_WSID(sta_priv_dat->sta_idx)
+	    && (sta_priv_dat->need_sw_decrypt)) {
+		int other_hw_wsid = (sta_priv_dat->sta_idx + 1) & 1;
+		struct ssv_sta_info *sta_info = &sc->sta_info[other_hw_wsid];
+		struct ieee80211_sta *sta = sta_info->sta;
+		struct ssv_sta_priv_data *sta_priv =
+		    (struct ssv_sta_priv_data *)sta->drv_priv;
+		mutex_lock(&sc->mutex);
+		if ((sta_info->s_flags == 0)
+		    || ((sta_info->s_flags && STA_FLAG_VALID)
+			&& (sta_priv->has_hw_decrypt))) {
+			SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+				       M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) |
+				       (M_ENG_HWHCI << 8));
+			dev_dbg(sc->dev, "redirect Rx flow for sta %d disconnect\n",
+			       sta_priv_dat->sta_idx);
+		}
+		mutex_unlock(&sc->mutex);
+	}
+}
+
+static int ssv6200_sta_remove(struct ieee80211_hw *hw,
+			      struct ieee80211_vif *vif,
+			      struct ieee80211_sta *sta)
+{
+	u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
+	struct ssv_sta_priv_data *sta_priv_dat =
+	    (struct ssv_sta_priv_data *)sta->drv_priv;
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_sta_info *sta_info = sta_priv_dat->sta_info;
+	unsigned long flags;
+	u32 bit;
+	struct ssv_vif_priv_data *priv_vif =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	u8 hw_wsid = -1;
+	BUG_ON(sta_priv_dat->sta_idx >= SSV_NUM_STA);
+	dev_notice(sc->dev,
+		   "Removing STA %d (%02X:%02X:%02X:%02X:%02X:%02X) from VIF %d\n.",
+		   sta_priv_dat->sta_idx, sta->addr[0], sta->addr[1],
+		   sta->addr[2], sta->addr[3], sta->addr[4], sta->addr[5],
+		   priv_vif->vif_idx);
+	ssv6200_rx_flow_check(sta_priv_dat, sc);
+	spin_lock_irqsave(&sc->ps_state_lock, flags);
+	bit = BIT(sta_priv_dat->sta_idx);
+	priv_vif->sta_asleep_mask &= ~bit;
+	if (sta_info->hw_wsid != -1) {
+		hw_wsid = sta_info->hw_wsid;
+	}
+	if (sta_info->hw_wsid >= SSV_NUM_HW_STA) {
+		spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+		hw_update_watch_wsid(sc, sta, sta_info, sta_info->hw_wsid, 0,
+				     SSV6XXX_WSID_OPS_DEL);
+		spin_lock_irqsave(&sc->ps_state_lock, flags);
+	}
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	{
+		ssv6xxx_debugfs_remove_sta(sc, sta_info);
+	}
+#endif
+	memset(sta_info, 0, sizeof(*sta_info));
+	sta_priv_dat->sta_idx = -1;
+	list_del(&sta_priv_dat->list);
+	if (list_empty(&priv_vif->sta_list)
+	    && vif->type == NL80211_IFTYPE_STATION) {
+		priv_vif->pair_cipher = 0;
+		priv_vif->group_cipher = 0;
+	}
+	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+	if ((hw_wsid != -1) && (hw_wsid < SSV_NUM_HW_STA))
+		SMAC_REG_WRITE(sc->sh, reg_wsid[hw_wsid], 0x00);
+	return 0;
+}
+
+static void ssv6200_sta_notify(struct ieee80211_hw *hw,
+			       struct ieee80211_vif *vif,
+			       enum sta_notify_cmd cmd,
+			       struct ieee80211_sta *sta)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_vif_priv_data *priv_vif =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	struct ssv_sta_priv_data *sta_priv_dat =
+	    sta != NULL ? (struct ssv_sta_priv_data *)sta->drv_priv : NULL;
+	struct ssv_sta_info *sta_info;
+	u32 bit, prev;
+	unsigned long flags;
+	spin_lock_irqsave(&sc->ps_state_lock, flags);
+	if (sta_priv_dat != NULL) {
+		bit = BIT(sta_priv_dat->sta_idx);
+		prev = priv_vif->sta_asleep_mask & bit;
+		sta_info = sta_priv_dat->sta_info;
+		switch (cmd) {
+		case STA_NOTIFY_SLEEP:
+			if (!prev) {
+				sta_info->sleeping = true;
+				if ((vif->type == NL80211_IFTYPE_AP)
+				    && sc->bq4_dtim
+				    && !priv_vif->sta_asleep_mask
+				    && ssv6200_bcast_queue_len(&sc->
+							       bcast_txq)) {
+					dev_dbg(sc->dev, "%s(): ssv6200_bcast_start\n", __FUNCTION__);
+					ssv6200_bcast_start(sc);
+				}
+				priv_vif->sta_asleep_mask |= bit;
+			}
+			break;
+		case STA_NOTIFY_AWAKE:
+			if (prev) {
+				sta_info->sleeping = false;
+				priv_vif->sta_asleep_mask &= ~bit;
+			}
+			break;
+		default:
+			break;
+		}
+	}
+	spin_unlock_irqrestore(&sc->ps_state_lock, flags);
+}
+
+static u64 ssv6200_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
+{
+	return jiffies * 1000 * 1000 / HZ;
+}
+
+static u64 ssv6200_get_systime_us(void)
+{
+#if LINUX_VERSION_CODE > KERNEL_VERSION(4,19,0)
+	struct timespec64 ts;
+	ktime_get_boottime_ts64(&ts);
+#else
+	struct timespec ts;
+	get_monotonic_boottime(&ts);
+#endif
+	return ((u64) ts.tv_sec * 1000000) + ts.tv_nsec / 1000;
+}
+
+static u32 pre_11b_cca_control;
+static u32 pre_11b_cca_1;
+static void ssv6200_sw_scan_start(struct ieee80211_hw *hw,
+				  struct ieee80211_vif *vif,
+				  const u8 * mac_addr)
+{
+	((struct ssv_softc *)(hw->priv))->bScanning = true;
+	SMAC_REG_READ(((struct ssv_softc *)(hw->priv))->sh,
+		      ADR_RX_11B_CCA_CONTROL, &pre_11b_cca_control);
+	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
+		       ADR_RX_11B_CCA_CONTROL, 0x0);
+	SMAC_REG_READ(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
+		      &pre_11b_cca_1);
+	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
+		       RX_11B_CCA_IN_SCAN);
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_MRX_FLT_EN3,
+		       0x0400);
+#endif
+}
+
+static void ssv6200_sw_scan_complete(struct ieee80211_hw *hw,
+				     struct ieee80211_vif *vif)
+{
+
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+	bool is_p2p_assoc;
+#endif
+	((struct ssv_softc *)(hw->priv))->bScanning = false;
+	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
+		       ADR_RX_11B_CCA_CONTROL, pre_11b_cca_control);
+	SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh, ADR_RX_11B_CCA_1,
+		       pre_11b_cca_1);
+#ifdef CONFIG_SSV_MRX_EN3_CTRL
+	is_p2p_assoc =
+	    ((struct ssv_softc *)(hw->priv))->vif_info[1].vif->bss_conf.assoc;
+	if (((struct ssv_softc *)(hw->priv))->ps_aid != 0 && (!is_p2p_assoc))
+		SMAC_REG_WRITE(((struct ssv_softc *)(hw->priv))->sh,
+			       ADR_MRX_FLT_EN3, 0x1000);
+#endif
+}
+
+static int ssv6200_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
+			   bool set)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_sta_info *sta_info = sta
+	    ? ((struct ssv_sta_priv_data *)sta->drv_priv)->sta_info : NULL;
+	if (sta_info && (sta_info->tim_set ^ set)) {
+        dev_dbg(sc->dev, "[I] [A] ssvcabrio_set_tim");
+		sta_info->tim_set = set;
+		queue_work(sc->config_wq, &sc->set_tim_work);
+	}
+	return 0;
+}
+
+static int ssv6200_conf_tx(struct ieee80211_hw *hw,
+			   struct ieee80211_vif *vif, u16 queue,
+			   const struct ieee80211_tx_queue_params *params)
+{
+	struct ssv_softc *sc = hw->priv;
+	u32 cw;
+	u8 hw_txqid = sc->tx.hw_txqid[queue];
+	struct ssv_vif_priv_data *priv_vif =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	dev_dbg
+	    (sc->dev, "[I] sv6200_conf_tx vif[%d] qos[%d] queue[%d] aifsn[%d] cwmin[%d] cwmax[%d] txop[%d] \n",
+	     priv_vif->vif_idx, vif->bss_conf.qos, queue, params->aifs,
+	     params->cw_min, params->cw_max, params->txop);
+	if (queue > NL80211_TXQ_Q_BK)
+		return 1;
+	if (priv_vif->vif_idx != 0) {
+		dev_warn(sc->dev,
+			 "WMM setting applicable to primary interface only.\n");
+		return 1;
+	}
+	mutex_lock(&sc->mutex);
+	SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET,
+			  (vif->bss_conf.qos << QOS_EN_SFT), QOS_EN_MSK);
+	cw = (params->aifs - 1) & 0xf;
+	cw |= ((ilog2(params->cw_min + 1)) & 0xf) << TXQ1_MTX_Q_ECWMIN_SFT;
+	cw |= ((ilog2(params->cw_max + 1)) & 0xf) << TXQ1_MTX_Q_ECWMAX_SFT;
+	cw |= ((params->txop) & 0xff) << TXQ1_MTX_Q_TXOP_LIMIT_SFT;
+	SMAC_REG_WRITE(sc->sh, ADR_TXQ0_MTX_Q_AIFSN + 0x100 * hw_txqid, cw);
+	mutex_unlock(&sc->mutex);
+	return 0;
+}
+
+static int ssv6200_ampdu_action(struct ieee80211_hw *hw,
+				struct ieee80211_vif *vif,
+				struct ieee80211_ampdu_params *params)
+{
+	struct ssv_softc *sc = hw->priv;
+	int ret = 0;
+	struct ieee80211_sta *sta = params->sta;
+	enum ieee80211_ampdu_mlme_action action = params->action;
+	u16 tid = params->tid;
+	u16 *ssn = &(params->ssn);
+	u8 buf_size = params->buf_size;
+	if (sta == NULL)
+		return ret;
+#if (!Enable_AMPDU_Rx)
+	if (action == IEEE80211_AMPDU_RX_START
+	    || action == IEEE80211_AMPDU_RX_STOP) {
+		ampdu_db_log("Disable AMPDU_RX for test(1).\n");
+		return -EOPNOTSUPP;
+	}
+#endif
+#if (!Enable_AMPDU_Tx)
+	if (action == IEEE80211_AMPDU_TX_START
+	    || action == IEEE80211_AMPDU_TX_STOP
+	    || action == IEEE80211_AMPDU_TX_OPERATIONAL) {
+		ampdu_db_log("Disable AMPDU_TX for test(1).\n");
+		return -EOPNOTSUPP;
+	}
+#endif
+	if ((action == IEEE80211_AMPDU_RX_START
+	     || action == IEEE80211_AMPDU_RX_STOP)
+	    && (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX))) {
+		ampdu_db_log("Disable AMPDU_RX(2).\n");
+		return -EOPNOTSUPP;
+	}
+	if ((action == IEEE80211_AMPDU_TX_START
+	     || action == IEEE80211_AMPDU_TX_STOP_CONT
+	     || action == IEEE80211_AMPDU_TX_STOP_FLUSH
+	     || action == IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
+	     || action == IEEE80211_AMPDU_TX_OPERATIONAL)
+	    && (!(sc->sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX))) {
+		ampdu_db_log("Disable AMPDU_TX(2).\n");
+		return -EOPNOTSUPP;
+	}
+	switch (action) {
+	case IEEE80211_AMPDU_RX_START:
+#ifdef WIFI_CERTIFIED
+		if (sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS) {
+			ieee80211_stop_rx_ba_session(vif,
+						     (1 << (sc->ba_tid)),
+						     sc->ba_ra_addr);
+			sc->rx_ba_session_count--;
+		}
+#else
+		if ((sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS)
+		    && (sc->rx_ba_sta != sta)) {
+			ret = -EBUSY;
+			break;
+		} else
+		    if ((sc->rx_ba_session_count >= SSV6200_RX_BA_MAX_SESSIONS)
+			&& (sc->rx_ba_sta == sta)) {
+			ieee80211_stop_rx_ba_session(vif, (1 << (sc->ba_tid)),
+						     sc->ba_ra_addr);
+			sc->rx_ba_session_count--;
+		}
+#endif
+		dev_dbg(sc->dev, "IEEE80211_AMPDU_RX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+		       sta->addr[4], sta->addr[5], tid);
+		sc->rx_ba_session_count++;
+		sc->rx_ba_sta = sta;
+		sc->ba_tid = tid;
+		sc->ba_ssn = *ssn;
+		memcpy(sc->ba_ra_addr, sta->addr, ETH_ALEN);
+		queue_work(sc->config_wq, &sc->set_ampdu_rx_add_work);
+		break;
+	case IEEE80211_AMPDU_RX_STOP:
+		sc->rx_ba_session_count--;
+		if (sc->rx_ba_session_count == 0)
+			sc->rx_ba_sta = NULL;
+		queue_work(sc->config_wq, &sc->set_ampdu_rx_del_work);
+		break;
+	case IEEE80211_AMPDU_TX_START:
+		dev_dbg(sc->dev, "AMPDU_TX_START %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+		       sta->addr[4], sta->addr[5], tid);
+		ssv6200_ampdu_tx_start(tid, sta, hw, ssn);
+		ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+		break;
+	case IEEE80211_AMPDU_TX_STOP_CONT:
+	case IEEE80211_AMPDU_TX_STOP_FLUSH:
+	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
+		dev_dbg(sc->dev, "AMPDU_TX_STOP %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+		       sta->addr[4], sta->addr[5], tid);
+		ssv6200_ampdu_tx_stop(tid, sta, hw);
+		ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+		break;
+	case IEEE80211_AMPDU_TX_OPERATIONAL:
+		dev_dbg(sc->dev, "AMPDU_TX_OPERATIONAL %02X:%02X:%02X:%02X:%02X:%02X %d.\n",
+		       sta->addr[0], sta->addr[1], sta->addr[2], sta->addr[3],
+		       sta->addr[4], sta->addr[5], tid);
+		ssv6200_ampdu_tx_operation(tid, sta, hw, buf_size);
+		break;
+	default:
+		ret = -EOPNOTSUPP;
+		break;
+	}
+	return ret;
+}
+
+#ifdef CONFIG_PM
+int ssv6xxx_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan)
+{
+	return 0;
+}
+
+int ssv6xxx_resume(struct ieee80211_hw *hw)
+{
+	return 0;
+}
+#endif
+struct ieee80211_ops ssv6200_ops = {
+	.tx = ssv6200_tx,
+	.start = ssv6200_start,
+	.stop = ssv6200_stop,
+	.add_interface = ssv6200_add_interface,
+	.remove_interface = ssv6200_remove_interface,
+	.change_interface = ssv6200_change_interface,
+	.config = ssv6200_config,
+	.configure_filter = ssv6200_config_filter,
+	.bss_info_changed = ssv6200_bss_info_changed,
+	.sta_add = ssv6200_sta_add,
+	.sta_remove = ssv6200_sta_remove,
+	.sta_notify = ssv6200_sta_notify,
+	.set_key = ssv6200_set_key,
+	.sw_scan_start = ssv6200_sw_scan_start,
+	.sw_scan_complete = ssv6200_sw_scan_complete,
+	.get_tsf = ssv6200_get_tsf,
+	.set_tim = ssv6200_set_tim,
+	.conf_tx = ssv6200_conf_tx,
+	.ampdu_action = ssv6200_ampdu_action,
+#ifdef CONFIG_PM
+	.suspend = ssv6xxx_suspend,
+	.resume = ssv6xxx_resume,
+#endif
+};
+
+int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug)
+{
+	struct ssv_softc *sc = dev;
+	int ac;
+	BUG_ON(hw_txqid > 4);
+	if (hw_txqid == 4)
+		return 0;
+	ac = sc->tx.ac_txqid[hw_txqid];
+	if (fc_en == false) {
+		if (sc->tx.flow_ctrl_status & (1 << ac)) {
+			ieee80211_wake_queue(sc->hw, ac);
+			sc->tx.flow_ctrl_status &= ~(1 << ac);
+		} else {
+		}
+	} else {
+		if ((sc->tx.flow_ctrl_status & (1 << ac)) == 0) {
+			ieee80211_stop_queue(sc->hw, ac);
+			sc->tx.flow_ctrl_status |= (1 << ac);
+		} else {
+		}
+	}
+	return 0;
+}
+
+void ssv6xxx_tx_q_empty_cb(u32 txq_no, void *cb_data)
+{
+	struct ssv_softc *sc = cb_data;
+	BUG_ON(sc == NULL);
+	sc->tx_q_empty = true;
+	smp_mb();
+	wake_up_interruptible(&sc->tx_wait_q);
+}
+
+struct ssv6xxx_b_cca_control {
+	u32 down_level;
+	u32 upper_level;
+	u32 adjust_cca_control;
+	u32 adjust_cca_1;
+};
+struct ssv6xxx_b_cca_control adjust_cci[] = {
+	{0, 43, 0x00162000, 0x20380050},
+	{40, 48, 0x00161000, 0x20380050},
+	{45, 53, 0x00160800, 0x20380050},
+	{50, 63, 0x00160400, 0x20380050},
+	{60, 68, 0x00160200, 0x20380050},
+	{65, 73, 0x00160100, 0x20380050},
+	{70, 128, 0x00000000, 0x20300050},
+};
+
+#define MAX_CCI_LEVEL 128
+static unsigned long last_jiffies = INITIAL_JIFFIES;
+static s32 size = sizeof(adjust_cci) / sizeof(adjust_cci[0]);
+static u32 current_level = MAX_CCI_LEVEL;
+static u32 current_gate = (sizeof(adjust_cci) / sizeof(adjust_cci[0])) - 1;
+void mitigate_cci(struct ssv_softc *sc, u32 input_level)
+{
+	s32 i;
+	if (input_level > MAX_CCI_LEVEL) {
+		dev_dbg(sc->dev, "mitigate_cci input error[%d]!!\n", input_level);
+		return;
+	}
+	if (time_after(jiffies, last_jiffies + msecs_to_jiffies(3000))) {
+		dev_dbg(sc->dev, "jiffies=%lu, input_level=%d\n", jiffies, input_level);
+		last_jiffies = jiffies;
+		if ((input_level >= adjust_cci[current_gate].down_level)
+		    && (input_level <= adjust_cci[current_gate].upper_level)) {
+			current_level = input_level;
+#ifdef DEBUG_MITIGATE_CCI
+			dev_dbg(sc->dev, "Keep the 0xce0020a0[%x] 0xce002008[%x]!!\n",
+			       adjust_cci[current_gate].adjust_cca_control,
+			       adjust_cci[current_gate].adjust_cca_1);
+#endif
+		} else {
+			if (current_level < input_level) {
+				for (i = 0; i < size; i++) {
+					if (input_level <=
+					    adjust_cci[i].upper_level) {
+#ifdef DEBUG_MITIGATE_CCI
+						dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].upper_level=%d, value=%08x\n",
+						     current_gate, input_level,
+						     i,
+						     adjust_cci[i].upper_level,
+						     adjust_cci[i].
+						     adjust_cca_control);
+#endif
+						current_level = input_level;
+						current_gate = i;
+						SMAC_REG_WRITE(sc->sh,
+							       ADR_RX_11B_CCA_CONTROL,
+							       adjust_cci[i].
+							       adjust_cca_control);
+						SMAC_REG_WRITE(sc->sh,
+							       ADR_RX_11B_CCA_1,
+							       adjust_cci[i].
+							       adjust_cca_1);
+#ifdef DEBUG_MITIGATE_CCI
+						dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n",
+						     adjust_cci[current_gate].
+						     adjust_cca_control,
+						     adjust_cci[current_gate].
+						     adjust_cca_1);
+#endif
+						return;
+					}
+				}
+			} else {
+				for (i = (size - 1); i >= 0; i--) {
+					if (input_level >=
+					    adjust_cci[i].down_level) {
+#ifdef DEBUG_MITIGATE_CCI
+						dev_dbg(sc->dev, "gate=%d, input_level=%d, adjust_cci[%d].down_level=%d, value=%08x\n",
+						     current_gate, input_level,
+						     i,
+						     adjust_cci[i].down_level,
+						     adjust_cci[i].
+						     adjust_cca_control);
+#endif
+						current_level = input_level;
+						current_gate = i;
+						SMAC_REG_WRITE(sc->sh,
+							       ADR_RX_11B_CCA_CONTROL,
+							       adjust_cci[i].
+							       adjust_cca_control);
+						SMAC_REG_WRITE(sc->sh,
+							       ADR_RX_11B_CCA_1,
+							       adjust_cci[i].
+							       adjust_cca_1);
+#ifdef DEBUG_MITIGATE_CCI
+						dev_dbg(sc->dev, "##Set to the 0xce0020a0[%x] 0xce002008[%x]##!!\n",
+						     adjust_cci[current_gate].
+						     adjust_cca_control,
+						     adjust_cci[current_gate].
+						     adjust_cca_1);
+#endif
+						return;
+					}
+				}
+			}
+		}
+	}
+}
+
+#define RSSI_SMOOTHING_SHIFT 5
+#define RSSI_DECIMAL_POINT_SHIFT 6
+static void _proc_data_rx_skb(struct ssv_softc *sc, struct sk_buff *rx_skb)
+{
+	struct ieee80211_rx_status *rxs;
+	struct ieee80211_hdr *hdr;
+	__le16 fc;
+	struct ssv6200_rx_desc *rxdesc;
+	struct ssv6200_rxphy_info_padding *rxphypad;
+	struct ssv6200_rxphy_info *rxphy;
+	struct ieee80211_channel *chan;
+	struct ieee80211_vif *vif = NULL;
+	struct ieee80211_sta *sta = NULL;
+	bool rx_hw_dec = false;
+	bool do_sw_dec = false;
+	struct ssv_sta_priv_data *sta_priv = NULL;
+	struct ssv_vif_priv_data *vif_priv = NULL;
+	SKB_info *skb_info = NULL;
+	u8 is_beacon;
+	u8 is_probe_resp;
+	s32 found = 0;
+#ifdef CONFIG_SSV_SMARTLINK
+	{
+		extern int ksmartlink_smartlink_started(void);
+		void smartlink_nl_send_msg(struct sk_buff *skb);
+		if (unlikely(ksmartlink_smartlink_started())) {
+			skb_pull(rx_skb, SSV6XXX_RX_DESC_LEN);
+			skb_trim(rx_skb, rx_skb->len - sc->sh->rx_pinfo_pad);
+			smartlink_nl_send_msg(rx_skb);
+			return;
+		}
+	}
+#endif
+	rxdesc = (struct ssv6200_rx_desc *)rx_skb->data;
+	rxphy = (struct ssv6200_rxphy_info *)(rx_skb->data + sizeof(*rxdesc));
+	rxphypad =
+	    (struct ssv6200_rxphy_info_padding *)(rx_skb->data + rx_skb->len -
+						  sizeof(struct
+							 ssv6200_rxphy_info_padding));
+	hdr = (struct ieee80211_hdr *)(rx_skb->data + SSV6XXX_RX_DESC_LEN);
+	fc = hdr->frame_control;
+	skb_info = (SKB_info *) rx_skb->head;
+	if (rxdesc->wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) {
+		if ((ieee80211_is_data(hdr->frame_control))
+		    && (!(ieee80211_is_nullfunc(hdr->frame_control)))) {
+			ssv6xxx_rc_rx_data_handler(sc->hw, rx_skb,
+						   rxdesc->rate_idx);
+		}
+	}
+	rxs = IEEE80211_SKB_RXCB(rx_skb);
+	memset(rxs, 0, sizeof(struct ieee80211_rx_status));
+	ssv6xxx_rc_mac8011_rate_idx(sc, rxdesc->rate_idx, rxs);
+
+	rxs->mactime = *((u32 *) & rx_skb->data[28]);
+	chan = sc->hw->conf.chandef.chan;
+	rxs->band = chan->band;
+	rxs->freq = chan->center_freq;
+	rxs->antenna = 1;
+	is_beacon = ieee80211_is_beacon(hdr->frame_control);
+	is_probe_resp = ieee80211_is_probe_resp(hdr->frame_control);
+	if (is_beacon)		//+++
+	{
+		struct ieee80211_mgmt *mgmt_tmp = NULL;
+		mgmt_tmp =
+		    (struct ieee80211_mgmt *)(rx_skb->data +
+					      SSV6XXX_RX_DESC_LEN);
+		mgmt_tmp->u.beacon.timestamp =
+		    cpu_to_le64(ssv6200_get_systime_us());
+	}
+	if (is_probe_resp) {
+		struct ieee80211_mgmt *mgmt_tmp = NULL;
+		mgmt_tmp =
+		    (struct ieee80211_mgmt *)(rx_skb->data +
+					      SSV6XXX_RX_DESC_LEN);
+		mgmt_tmp->u.probe_resp.timestamp =
+		    cpu_to_le64(ssv6200_get_systime_us());
+	}
+
+	if (rxdesc->rate_idx < SSV62XX_G_RATE_INDEX && rxphypad->RSVD == 0) {
+		if (is_beacon || is_probe_resp) {
+			sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+			if (sta) {
+				sta_priv =
+				    (struct ssv_sta_priv_data *)sta->drv_priv;
+#ifdef SSV_RSSI_DEBUG
+				dev_dbg(sc->dev, "b_beacon %02X:%02X:%02X:%02X:%02X:%02X rssi=%d, snr=%d\n",
+				       hdr->addr2[0], hdr->addr2[1],
+				       hdr->addr2[2], hdr->addr2[3],
+				       hdr->addr2[4], hdr->addr2[5],
+				       rxphypad->rpci, rxphypad->snr);
+#endif
+				if (sta_priv->beacon_rssi) {
+					sta_priv->beacon_rssi =
+					    ((rxphypad->
+					      rpci << RSSI_DECIMAL_POINT_SHIFT)
+					     +
+					     ((sta_priv->
+					       beacon_rssi <<
+					       RSSI_SMOOTHING_SHIFT) -
+					      sta_priv->
+					      beacon_rssi)) >>
+					    RSSI_SMOOTHING_SHIFT;
+					rxphypad->rpci =
+					    (sta_priv->
+					     beacon_rssi >>
+					     RSSI_DECIMAL_POINT_SHIFT);
+				} else
+					sta_priv->beacon_rssi =
+					    (rxphypad->
+					     rpci << RSSI_DECIMAL_POINT_SHIFT);
+#ifdef SSV_RSSI_DEBUG
+				dev_dbg(sc->dev, "Beacon smoothing RSSI %d\n", rxphypad->rpci);
+#endif
+				mitigate_cci(sc, rxphypad->rpci);
+			} else {
+				mutex_lock(&sc->mutex);
+				list_for_each_entry(p_rssi_res,
+						    &rssi_res.rssi_list,
+						    rssi_list) {
+					if (!memcmp
+					    (p_rssi_res->bssid, hdr->addr2,
+					     ETH_ALEN)) {
+						{
+							p_rssi_res->rssi =
+							    ((rxphypad->
+							      rpci <<
+							      RSSI_DECIMAL_POINT_SHIFT)
+							     +
+							     ((p_rssi_res->
+							       rssi <<
+							       RSSI_SMOOTHING_SHIFT)
+							      -
+							      p_rssi_res->
+							      rssi)) >>
+							    RSSI_SMOOTHING_SHIFT;
+							rxphypad->rpci =
+							    (p_rssi_res->
+							     rssi >>
+							     RSSI_DECIMAL_POINT_SHIFT);
+						}
+						p_rssi_res->cache_jiffies =
+						    jiffies;
+						found = 1;
+						break;
+					} else {
+						if (p_rssi_res->rssi) {
+							if (time_after
+							    (jiffies,
+							     p_rssi_res->
+							     cache_jiffies +
+							     msecs_to_jiffies
+							     (40000))) {
+								p_rssi_res->
+								    timeout = 1;
+							}
+						}
+					}
+				}
+				if (!found) {
+					p_rssi_res =
+					    kmalloc(sizeof(struct rssi_res_st),
+						    GFP_KERNEL);
+					memcpy(p_rssi_res->bssid, hdr->addr2,
+					       ETH_ALEN);
+					p_rssi_res->cache_jiffies = jiffies;
+					p_rssi_res->rssi =
+					    (rxphypad->
+					     rpci << RSSI_DECIMAL_POINT_SHIFT);
+					p_rssi_res->timeout = 0;
+					INIT_LIST_HEAD(&p_rssi_res->rssi_list);
+					list_add_tail_rcu(&
+							  (p_rssi_res->
+							   rssi_list),
+							  &(rssi_res.
+							    rssi_list));
+				}
+				mutex_unlock(&sc->mutex);
+			}
+			if (rxphypad->rpci > 88)
+				rxphypad->rpci = 88;
+		}
+		if (sc->sh->cfg.rssi_ctl) {
+			rxs->signal = (-rxphypad->rpci) + sc->sh->cfg.rssi_ctl;
+		} else {
+			rxs->signal = (-rxphypad->rpci);
+		}
+	} else if (rxdesc->rate_idx >= SSV62XX_G_RATE_INDEX
+		   && rxphy->service == 0) {
+		if (is_beacon || is_probe_resp) {
+			sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+			if (sta) {
+				sta_priv =
+				    (struct ssv_sta_priv_data *)sta->drv_priv;
+#ifdef SSV_RSSI_DEBUG
+				dev_dbg(sc->dev, "gn_beacon %02X:%02X:%02X:%02X:%02X:%02X rssi=%d, snr=%d\n",
+				     hdr->addr2[0], hdr->addr2[1],
+				     hdr->addr2[2], hdr->addr2[3],
+				     hdr->addr2[4], hdr->addr2[5], rxphy->rpci,
+				     rxphy->snr);
+#endif
+				if (sta_priv->beacon_rssi) {
+					sta_priv->beacon_rssi =
+					    ((rxphy->
+					      rpci << RSSI_DECIMAL_POINT_SHIFT)
+					     +
+					     ((sta_priv->
+					       beacon_rssi <<
+					       RSSI_SMOOTHING_SHIFT) -
+					      sta_priv->
+					      beacon_rssi)) >>
+					    RSSI_SMOOTHING_SHIFT;
+					rxphy->rpci =
+					    (sta_priv->
+					     beacon_rssi >>
+					     RSSI_DECIMAL_POINT_SHIFT);
+				} else
+					sta_priv->beacon_rssi =
+					    (rxphy->
+					     rpci << RSSI_DECIMAL_POINT_SHIFT);
+#ifdef SSV_RSSI_DEBUG
+				dev_dbg(sc->dev, "Beacon smoothing RSSI %d\n", rxphy->rpci);
+#endif
+			}
+			if (rxphy->rpci > 88)
+				rxphy->rpci = 88;
+		}
+		if (sc->sh->cfg.rssi_ctl) {
+			rxs->signal = (-rxphy->rpci) + sc->sh->cfg.rssi_ctl;
+		} else {
+			rxs->signal = (-rxphy->rpci);
+		}
+	} else {
+#ifdef SSV_RSSI_DEBUG
+		dev_dbg(sc->dev, "########unicast: %d, b_rssi/snr: %d/%d, gn_rssi/snr: %d/%d, rate:%d###############\n",
+		     rxdesc->unicast, (-rxphy->rpci), rxphy->snr,
+		     (-rxphypad->rpci), rxphypad->snr, rxdesc->rate_idx);
+		dev_dbg(sc->dev, "RSSI, %d, rate_idx, %d\n", rxs->signal,
+		       rxdesc->rate_idx);
+		dev_dbg(sc->dev, "rxdesc->RxResult = %x,rxdesc->wsid = %d\n",
+		       rxdesc->RxResult, rxdesc->wsid);
+#endif
+		sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+		if (sta) {
+			sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+			rxs->signal =
+			    -(sta_priv->
+			      beacon_rssi >> RSSI_DECIMAL_POINT_SHIFT);
+		}
+#ifdef SSV_RSSI_DEBUG
+		dev_dbg(sc->dev, "Others signal %d\n", rxs->signal);
+#endif
+	}
+//    rxs->flag = RX_FLAG_MACTIME_START;          //+++
+	rxs->rx_flags = 0;
+	if (rxphy->aggregate)
+		rxs->flag |= RX_FLAG_NO_SIGNAL_VAL;
+	sc->hw_mng_used = rxdesc->mng_used;
+	if ((ieee80211_is_data(fc) || ieee80211_is_data_qos(fc))
+	    && ieee80211_has_protected(fc)) {
+		sta = ssv6xxx_find_sta_by_rx_skb(sc, rx_skb);
+		if (sta == NULL)
+			goto drop_rx;
+		sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+		vif = sta_priv->sta_info->vif;
+		if (vif == NULL)
+			goto drop_rx;
+		if (is_broadcast_ether_addr(hdr->addr1) || is_multicast_ether_addr(hdr->addr1)) {
+			vif_priv = (struct ssv_vif_priv_data *)vif->drv_priv;
+			rx_hw_dec = vif_priv->has_hw_decrypt;
+			do_sw_dec = vif_priv->need_sw_decrypt;
+		} else {
+			rx_hw_dec = sta_priv->has_hw_decrypt;
+			do_sw_dec = sta_priv->need_sw_decrypt;
+		}
+	}
+	skb_pull(rx_skb, SSV6XXX_RX_DESC_LEN);
+	skb_trim(rx_skb, rx_skb->len - sc->sh->rx_pinfo_pad);
+#ifdef CONFIG_P2P_NOA
+	if (is_beacon)
+		ssv6xxx_noa_detect(sc, hdr, rx_skb->len);
+#endif
+	if (rx_hw_dec || do_sw_dec) {
+		hdr = (struct ieee80211_hdr *)rx_skb->data;
+		rxs = IEEE80211_SKB_RXCB(rx_skb);
+		hdr->frame_control =
+		    hdr->
+		    frame_control & ~(cpu_to_le16(IEEE80211_FCTL_PROTECTED));
+		rxs->flag |= (RX_FLAG_DECRYPTED | RX_FLAG_IV_STRIPPED);
+	}
+#if defined(USE_THREAD_RX) && !defined(IRQ_PROC_RX_DATA)
+	local_bh_disable();
+	ieee80211_rx(sc->hw, rx_skb);
+	local_bh_enable();
+#else
+	ieee80211_rx_irqsafe(sc->hw, rx_skb);
+#endif
+	return;
+ drop_rx:
+	dev_kfree_skb_any(rx_skb);
+}
+
+#ifdef IRQ_PROC_RX_DATA
+static struct sk_buff *_proc_rx_skb(struct ssv_softc *sc,
+				    struct sk_buff *rx_skb)
+{
+	struct ieee80211_hdr *hdr =
+	    (struct ieee80211_hdr *)(rx_skb->data + SSV6XXX_RX_DESC_LEN);
+	struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)rx_skb->data;
+	if (ieee80211_is_back(hdr->frame_control)
+	    || (rxdesc->c_type == HOST_EVENT))
+		return rx_skb;
+	_proc_data_rx_skb(sc, rx_skb);
+	return NULL;
+}
+#endif
+void _process_rx_q(struct ssv_softc *sc, struct sk_buff_head *rx_q,
+		   spinlock_t * rx_q_lock)
+{
+	struct sk_buff *skb;
+	struct ieee80211_hdr *hdr;
+	struct ssv6200_rx_desc *rxdesc;
+	unsigned long flags = 0;
+#ifdef USE_FLUSH_RETRY
+	bool has_ba_processed = false;
+#endif
+	while (1) {
+		if (rx_q_lock != NULL) {
+			spin_lock_irqsave(rx_q_lock, flags);
+			skb = __skb_dequeue(rx_q);
+		} else
+			skb = skb_dequeue(rx_q);
+		if (!skb) {
+			if (rx_q_lock != NULL)
+				spin_unlock_irqrestore(rx_q_lock, flags);
+			break;
+		}
+		sc->rx.rxq_count--;
+		if (rx_q_lock != NULL)
+			spin_unlock_irqrestore(rx_q_lock, flags);
+		rxdesc = (struct ssv6200_rx_desc *)skb->data;
+		if (rxdesc->c_type == HOST_EVENT) {
+			struct cfg_host_event *h_evt =
+			    (struct cfg_host_event *)rxdesc;
+			if (h_evt->h_event == SOC_EVT_NO_BA) {
+				ssv6200_ampdu_no_BA_handler(sc->hw, skb);
+#ifdef USE_FLUSH_RETRY
+				has_ba_processed = true;
+#endif
+			} else if (h_evt->h_event == SOC_EVT_RC_MPDU_REPORT) {
+				skb_queue_tail(&sc->rc_report_queue, skb);
+				if (sc->rc_sample_sechedule == 0)
+					queue_work(sc->rc_sample_workqueue,
+						   &sc->rc_sample_work);
+			} else if (h_evt->h_event == SOC_EVT_SDIO_TEST_COMMAND) {
+				if (h_evt->evt_seq_no == 0) {
+					dev_dbg(sc->dev, "SOC_EVT_SDIO_TEST_COMMAND\n");
+					sc->sdio_rx_evt_size = h_evt->len;
+					sc->sdio_throughput_timestamp = jiffies;
+				} else {
+					sc->sdio_rx_evt_size += h_evt->len;
+					if (time_after
+					    (jiffies,
+					     sc->sdio_throughput_timestamp +
+					     msecs_to_jiffies(1000))) {
+						dev_dbg(sc->dev, "data[%ld] SDIO RX throughput %ld Kbps\n",
+						     sc->sdio_rx_evt_size,
+						     (sc->
+						      sdio_rx_evt_size << 3) /
+						     jiffies_to_msecs(jiffies -
+								      sc->
+								      sdio_throughput_timestamp));
+						sc->sdio_throughput_timestamp =
+						    jiffies;
+						sc->sdio_rx_evt_size = 0;
+					}
+				}
+				dev_kfree_skb_any(skb);
+			} else if (h_evt->h_event == SOC_EVT_WATCHDOG_TRIGGER) {
+				dev_kfree_skb_any(skb);
+//              if(sc->watchdog_flag != WD_SLEEP)     //+++
+				sc->watchdog_flag = WD_KICKED;
+			} else if (h_evt->h_event == SOC_EVT_RESET_HOST) {
+				dev_kfree_skb_any(skb);
+				if ((sc->ap_vif == NULL)
+				    || !(sc->sh->cfg.ignore_reset_in_ap)) {
+					ssv6xxx_restart_hw(sc);
+				} else {
+					dev_warn(sc->dev,
+						 "Reset event ignored.\n");
+				}
+			}
+#ifdef CONFIG_P2P_NOA
+			else if (h_evt->h_event == SOC_EVT_NOA) {
+				ssv6xxx_process_noa_event(sc, skb);
+				dev_kfree_skb_any(skb);
+			}
+#endif
+			else if (h_evt->h_event == SOC_EVT_SDIO_TXTPUT_RESULT) {
+				dev_dbg(sc->dev, "data SDIO TX throughput %d Kbps\n",
+				       h_evt->evt_seq_no);
+				dev_kfree_skb_any(skb);
+			} else if (h_evt->h_event == SOC_EVT_TXLOOPBK_RESULT) {
+				if (h_evt->evt_seq_no == SSV6XXX_STATE_OK) {
+					dev_dbg(sc->dev, "FW TX LOOPBACK OK\n");
+					sc->iq_cali_done = IQ_CALI_OK;
+				} else {
+					dev_dbg(sc->dev, "FW TX LOOPBACK FAILED\n");
+					sc->iq_cali_done = IQ_CALI_FAILED;
+				}
+				dev_kfree_skb_any(skb);
+				wake_up_interruptible(&sc->fw_wait_q);
+			} else {
+				dev_warn(sc->dev, "Unkown event %d received\n",
+					 h_evt->h_event);
+				dev_kfree_skb_any(skb);
+			}
+			continue;
+		}
+		hdr = (struct ieee80211_hdr *)(skb->data + SSV6XXX_RX_DESC_LEN);
+		if (ieee80211_is_back(hdr->frame_control)) {
+			ssv6200_ampdu_BA_handler(sc->hw, skb);
+#ifdef USE_FLUSH_RETRY
+			has_ba_processed = true;
+#endif
+			continue;
+		}
+		_proc_data_rx_skb(sc, skb);
+	}
+#ifdef USE_FLUSH_RETRY
+	if (has_ba_processed) {
+		ssv6xxx_ampdu_postprocess_BA(sc->hw);
+	}
+#endif
+}
+
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args)
+#else
+int ssv6200_rx(struct sk_buff *rx_skb, void *args)
+#endif
+{
+	struct ssv_softc *sc = args;
+#ifdef IRQ_PROC_RX_DATA
+	struct sk_buff *skb;
+	skb = _proc_rx_skb(sc, rx_skb);
+	if (skb == NULL)
+		return 0;
+#endif
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+	{
+		unsigned long flags;
+		spin_lock_irqsave(&sc->rx_skb_q.lock, flags);
+		while (skb_queue_len(rx_skb_q))
+			__skb_queue_tail(&sc->rx_skb_q,
+					 __skb_dequeue(rx_skb_q));
+		spin_unlock_irqrestore(&sc->rx_skb_q.lock, flags);
+	}
+#else
+	skb_queue_tail(&sc->rx_skb_q, rx_skb);
+#endif
+	wake_up_interruptible(&sc->rx_wait_q);
+	return 0;
+}
+
+struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb(struct ssv_softc *sc,
+						 struct sk_buff *skb)
+{
+	struct ieee80211_hdr *hdr =
+	    (struct ieee80211_hdr *)(skb->data + SSV6XXX_RX_DESC_LEN);
+	struct ssv6200_rx_desc *rxdesc = (struct ssv6200_rx_desc *)skb->data;;
+	if ((rxdesc->wsid >= 0) && (rxdesc->wsid < SSV_NUM_STA))
+		return sc->sta_info[rxdesc->wsid].sta;
+	else
+		return ssv6xxx_find_sta_by_addr(sc, hdr->addr2);
+}
+
+struct ieee80211_sta *ssv6xxx_find_sta_by_addr(struct ssv_softc *sc, u8 addr[6])
+{
+	struct ieee80211_sta *sta;
+	int i;
+	for (i = 0; i < SSV6200_MAX_VIF; i++) {
+		if (sc->vif_info[i].vif == NULL)
+			continue;
+		sta = ieee80211_find_sta(sc->vif_info[i].vif, addr);
+		if (sta != NULL)
+			return sta;
+	}
+	return NULL;
+}
+
+void ssv6xxx_foreach_sta(struct ssv_softc *sc,
+			 void (*sta_func)(struct ssv_softc *,
+					  struct ssv_sta_info *, void *),
+			 void *param)
+{
+	int i;
+	BUG_ON(sta_func == NULL);
+	for (i = 0; i < SSV_NUM_STA; i++) {
+		if ((sc->sta_info[i].s_flags & STA_FLAG_VALID) == 0)
+			continue;
+		(*sta_func) (sc, &sc->sta_info[i], param);
+	}
+}
+
+void ssv6xxx_foreach_vif_sta(struct ssv_softc *sc,
+			     struct ssv_vif_info *vif_info,
+			     void (*sta_func)(struct ssv_softc *,
+					      struct ssv_vif_info *,
+					      struct ssv_sta_info *,
+					      void *), void *param)
+{
+	struct ssv_vif_priv_data *vif_priv;
+	struct ssv_sta_priv_data *sta_priv_iter;
+	BUG_ON(vif_info == NULL);
+	BUG_ON((size_t)vif_info < 0x30000);
+	vif_priv = (struct ssv_vif_priv_data *)vif_info->vif->drv_priv;
+	BUG_ON((size_t)vif_info->vif < 0x30000);
+	BUG_ON((size_t)vif_priv < 0x30000);
+	list_for_each_entry(sta_priv_iter, &vif_priv->sta_list, list) {
+		BUG_ON(sta_priv_iter == NULL);
+		BUG_ON((size_t)sta_priv_iter < 0x30000);
+		BUG_ON(sta_priv_iter->sta_info == NULL);
+		BUG_ON((size_t)sta_priv_iter->sta_info < 0x30000);
+		if ((sta_priv_iter->sta_info->s_flags & STA_FLAG_VALID) == 0)
+			continue;
+		(*sta_func) (sc, vif_info, sta_priv_iter->sta_info, param);
+	}
+}
+
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ssize_t ssv6xxx_tx_queue_status_dump(struct ssv_softc *sc, char *status_buf,
+				     ssize_t length)
+{
+	ssize_t buf_size = length;
+	ssize_t prt_size;
+	prt_size =
+	    snprintf(status_buf, buf_size, "\nSMAC driver queue status:.\n");
+	status_buf += prt_size;
+	buf_size -= prt_size;
+	prt_size = snprintf(status_buf, buf_size, "\tTX queue: %d\n",
+			    skb_queue_len(&sc->tx_skb_q));
+	status_buf += prt_size;
+	buf_size -= prt_size;
+	prt_size = snprintf(status_buf, buf_size, "\tMax TX queue: %d\n",
+			    sc->max_tx_skb_q_len);
+	status_buf += prt_size;
+	buf_size -= prt_size;
+	return (length - buf_size);
+}
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/dev.h b/drivers/net/wireless/ssv6051/smac/dev.h
new file mode 100644
index 00000000000..0a6357624b1
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/dev.h
@@ -0,0 +1,445 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DEV_H_
+#define _DEV_H_
+#include <linux/version.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <net/mac80211.h>
+#include "ampdu.h"
+#include "ssv_rc_common.h"
+#include "drv_comm.h"
+#include "sec.h"
+#include "p2p.h"
+#include <linux/kthread.h>
+#define SSV6200_MAX_HW_MAC_ADDR 2
+#define SSV6200_MAX_VIF 2
+#define SSV6200_RX_BA_MAX_SESSIONS 1
+#define SSV6200_OPMODE_STA 0
+#define SSV6200_OPMODE_AP 1
+#define SSV6200_OPMODE_IBSS 2
+#define SSV6200_OPMODE_WDS 3
+#define SSV6200_USE_HW_WSID(_sta_idx) ((_sta_idx == 0) || (_sta_idx == 1))
+#define HW_MAX_RATE_TRIES 7
+#define MAC_DECITBL1_SIZE 16
+#define MAC_DECITBL2_SIZE 9
+#define RX_11B_CCA_IN_SCAN 0x20230050
+//#define WATCHDOG_TIMEOUT (10*HZ)
+#define WATCHDOG_TIMEOUT (99999*HZ)
+extern u16 generic_deci_tbl[];
+#define ap_deci_tbl generic_deci_tbl
+#define sta_deci_tbl generic_deci_tbl
+#define HT_SIGNAL_EXT 6
+#define HT_SIFS_TIME 10
+#define BITS_PER_BYTE 8
+#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
+#define ACK_LEN (14)
+#define BA_LEN (32)
+#define RTS_LEN (20)
+#define CTS_LEN (14)
+#define L_STF 8
+#define L_LTF 8
+#define L_SIG 4
+#define HT_SIG 8
+#define HT_STF 4
+#define HT_LTF(_ns) (4 * (_ns))
+#define SYMBOL_TIME(_ns) ((_ns) << 2)
+#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5)
+#define CCK_SIFS_TIME 10
+#define CCK_PREAMBLE_BITS 144
+#define CCK_PLCP_BITS 48
+#define OFDM_SIFS_TIME 16
+#define OFDM_PREAMBLE_TIME 20
+#define OFDM_PLCP_BITS 22
+#define OFDM_SYMBOL_TIME 4
+#define WMM_AC_VO 0
+#define WMM_AC_VI 1
+#define WMM_AC_BE 2
+#define WMM_AC_BK 3
+#define WMM_NUM_AC 4
+#define WMM_TID_NUM 8
+#define TXQ_EDCA_0 0x01
+#define TXQ_EDCA_1 0x02
+#define TXQ_EDCA_2 0x04
+#define TXQ_EDCA_3 0x08
+#define TXQ_MGMT 0x10
+#define IS_SSV_HT(dsc) ((dsc)->rate_idx >= 15)
+#define IS_SSV_SHORT_GI(dsc) ((dsc)->rate_idx>=23 && (dsc)->rate_idx<=30)
+#define IS_SSV_HT_GF(dsc) ((dsc)->rate_idx >= 31)
+#define IS_SSV_SHORT_PRE(dsc) ((dsc)->rate_idx>=4 && (dsc)->rate_idx<=14)
+#define SMAC_REG_WRITE(_s,_r,_v) \
+        (_s)->hci.hci_ops->hci_write_word(_r,_v)
+#define SMAC_REG_READ(_s,_r,_v) \
+        (_s)->hci.hci_ops->hci_read_word(_r, _v)
+#define SMAC_LOAD_FW(_s,_r,_v) \
+        (_s)->hci.hci_ops->hci_load_fw(_r, _v)
+#define SMAC_IFC_RESET(_s) (_s)->hci.hci_ops->hci_interface_reset()
+#define SMAC_REG_CONFIRM(_s,_r,_v) \
+{ \
+    u32 _regval; \
+    SMAC_REG_READ(_s, _r, &_regval); \
+    if (_regval != (_v)) { \
+        printk("ERROR!!Please check interface!\n"); \
+        printk("[0x%08x]: 0x%08x!=0x%08x\n", \
+        (_r), (_v), _regval); \
+        printk("SOS!SOS!\n"); \
+        return -1; \
+    } \
+}
+#define SMAC_REG_SET_BITS(_sh,_reg,_set,_clr) \
+({ \
+    int ret; \
+    u32 _regval; \
+    ret = SMAC_REG_READ(_sh, _reg, &_regval); \
+    _regval &= ~(_clr); \
+    _regval |= (_set); \
+    if (ret == 0) \
+        ret = SMAC_REG_WRITE(_sh, _reg, _regval); \
+    ret; \
+})
+#define HCI_START(_sh) \
+    (_sh)->hci.hci_ops->hci_start()
+#define HCI_STOP(_sh) \
+    (_sh)->hci.hci_ops->hci_stop()
+#define HCI_SEND(_sh,_sk,_q) \
+    (_sh)->hci.hci_ops->hci_tx(_sk, _q, 0)
+#define HCI_PAUSE(_sh,_mk) \
+    (_sh)->hci.hci_ops->hci_tx_pause(_mk)
+#define HCI_RESUME(_sh,_mk) \
+    (_sh)->hci.hci_ops->hci_tx_resume(_mk)
+#define HCI_TXQ_FLUSH(_sh,_mk) \
+    (_sh)->hci.hci_ops->hci_txq_flush(_mk)
+#define HCI_TXQ_FLUSH_BY_STA(_sh,_aid) \
+  (_sh)->hci.hci_ops->hci_txq_flush_by_sta(_aid)
+#define HCI_TXQ_EMPTY(_sh,_txqid) \
+  (_sh)->hci.hci_ops->hci_txq_empty(_txqid)
+#define HCI_WAKEUP_PMU(_sh) \
+    (_sh)->hci.hci_ops->hci_pmu_wakeup()
+#define HCI_SEND_CMD(_sh,_sk) \
+        (_sh)->hci.hci_ops->hci_send_cmd(_sk)
+#define SSV6XXX_SET_HW_TABLE(sh_,tbl_) \
+({ \
+    int ret = 0; \
+    u32 i=0; \
+    for(; i<sizeof(tbl_)/sizeof(struct ssv6xxx_dev_table); i++) { \
+        ret = SMAC_REG_WRITE(sh_, tbl_[i].address, tbl_[i].data); \
+        if (ret) break; \
+    } \
+    ret; \
+})
+#define SSV6XXX_USE_HW_DECRYPT(_priv) (_priv->has_hw_decrypt)
+#define SSV6XXX_USE_SW_DECRYPT(_priv) (SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) || SSV6XXX_USE_MAC80211_DECRYPT(_priv))
+#define SSV6XXX_USE_LOCAL_SW_DECRYPT(_priv) (_priv->need_sw_decrypt)
+#define SSV6XXX_USE_MAC80211_DECRYPT(_priv) (_priv->use_mac80211_decrypt)
+struct ssv_softc;
+#ifdef CONFIG_P2P_NOA
+struct ssv_p2p_noa;
+#endif
+#define SSV6200_HT_TX_STREAMS 1
+#define SSV6200_HT_RX_STREAMS 1
+#define SSV6200_RX_HIGHEST_RATE 72
+enum PWRSV_STATUS {
+	PWRSV_DISABLE,
+	PWRSV_ENABLE,
+	PWRSV_PREPARE,
+};
+struct rssi_res_st {
+	struct list_head rssi_list;
+	unsigned long cache_jiffies;
+	s32 rssi;
+	s32 timeout;
+	u8 bssid[ETH_ALEN];
+};
+struct ssv_hw {
+	struct ssv_softc *sc;
+	struct ssv6xxx_platform_data *priv;
+	struct ssv6xxx_hci_info hci;
+	char chip_id[24];
+	u64 chip_tag;
+	u32 tx_desc_len;
+	u32 rx_desc_len;
+	u32 rx_pinfo_pad;
+	u32 tx_page_available;
+	u32 ampdu_divider;
+	u8 page_count[SSV6200_ID_NUMBER];
+	u32 hw_buf_ptr[SSV_RC_MAX_STA];
+	u32 hw_sec_key[SSV_RC_MAX_STA];
+	u32 hw_pinfo;
+	struct ssv6xxx_cfg cfg;
+	u32 n_addresses;
+	struct mac_address maddr[SSV6200_MAX_HW_MAC_ADDR];
+	u8 ipd_channel_touch;
+	struct ssv6xxx_ch_cfg *p_ch_cfg;
+	u32 ch_cfg_size;
+};
+struct ssv_tx {
+	u16 seq_no;
+	int hw_txqid[WMM_NUM_AC];
+	int ac_txqid[WMM_NUM_AC];
+	u32 flow_ctrl_status;
+	u32 tx_pkt[SSV_HW_TXQ_NUM];
+	u32 tx_frag[SSV_HW_TXQ_NUM];
+	struct list_head ampdu_tx_que;
+	spinlock_t ampdu_tx_que_lock;
+	u16 ampdu_tx_group_id;
+};
+struct ssv_rx {
+	struct sk_buff *rx_buf;
+	spinlock_t rxq_lock;
+	struct sk_buff_head rxq_head;
+	u32 rxq_count;
+};
+#define SSV6XXX_GET_STA_INFO(_sc,_s) \
+    &(_sc)->sta_info[((struct ssv_sta_priv_data *)((_s)->drv_priv))->sta_idx]
+#define STA_FLAG_VALID 0x00001
+#define STA_FLAG_QOS 0x00002
+#define STA_FLAG_AMPDU 0x00004
+#define STA_FLAG_ENCRYPT 0x00008
+struct ssv_sta_info {
+	u16 aid;
+	u16 s_flags;
+	int hw_wsid;
+	struct ieee80211_sta *sta;
+	struct ieee80211_vif *vif;
+	bool sleeping;
+	bool tim_set;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct dentry *debugfs_dir;
+#endif
+};
+struct ssv_vif_info {
+	struct ieee80211_vif *vif;
+	struct ssv_vif_priv_data *vif_priv;
+	enum nl80211_iftype if_type;
+	struct ssv6xxx_hw_sec sramKey;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct dentry *debugfs_dir;
+#endif
+};
+struct ssv_sta_priv_data {
+	int sta_idx;
+	int rc_idx;
+	int rx_data_rate;
+	struct ssv_sta_info *sta_info;
+	struct list_head list;
+	u32 ampdu_mib_total_BA_counter;
+	AMPDU_TID ampdu_tid[WMM_TID_NUM];
+	bool has_hw_encrypt;
+	bool need_sw_encrypt;
+	bool has_hw_decrypt;
+	bool need_sw_decrypt;
+	bool use_mac80211_decrypt;
+	u8 group_key_idx;
+	u32 beacon_rssi;
+};
+struct ssv_vif_priv_data {
+	int vif_idx;
+	struct list_head sta_list;
+	u32 sta_asleep_mask;
+	u32 pair_cipher;
+	u32 group_cipher;
+	bool is_security_valid;
+	bool has_hw_encrypt;
+	bool need_sw_encrypt;
+	bool has_hw_decrypt;
+	bool need_sw_decrypt;
+	bool use_mac80211_decrypt;
+	bool force_sw_encrypt;
+	u8 group_key_idx;
+};
+#define SC_OP_INVALID 0x00000001
+#define SC_OP_HW_RESET 0x00000002
+#define SC_OP_OFFCHAN 0x00000004
+#define SC_OP_FIXED_RATE 0x00000008
+#define SC_OP_SHORT_PREAMBLE 0x00000010
+struct ssv6xxx_beacon_info {
+	u32 pubf_addr;
+	u16 len;
+	u8 tim_offset;
+	u8 tim_cnt;
+};
+#define SSV6200_MAX_BCAST_QUEUE_LEN 16
+struct ssv6xxx_bcast_txq {
+	spinlock_t txq_lock;
+	struct sk_buff_head qhead;
+	int cur_qsize;
+};
+#ifdef DEBUG_AMPDU_FLUSH
+typedef struct AMPDU_TID_st AMPDU_TID;
+#define MAX_TID (24)
+#endif
+struct ssv_softc {
+	struct ieee80211_hw *hw;
+	struct device *dev;
+	u32 restart_counter;
+	bool force_triger_reset;
+	unsigned long sdio_throughput_timestamp;
+	unsigned long sdio_rx_evt_size;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
+	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
+#else
+	struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
+#endif
+	struct ieee80211_channel *cur_channel;
+	u16 hw_chan;
+	struct mutex mutex;
+	struct ssv_hw *sh;
+	struct ssv_tx tx;
+	struct ssv_rx rx;
+	struct ssv_vif_info vif_info[SSV_NUM_VIF];
+	struct ssv_sta_info sta_info[SSV_NUM_STA];
+	struct ieee80211_vif *ap_vif;
+	u8 nvif;
+	u32 sc_flags;
+	void *rc;
+	int max_rate_idx;
+	struct workqueue_struct *rc_sample_workqueue;
+	struct sk_buff_head rc_report_queue;
+	struct work_struct rc_sample_work;
+#ifdef DEBUG_AMPDU_FLUSH
+	struct AMPDU_TID_st *tid[MAX_TID];
+#endif
+	u16 rc_sample_sechedule;
+	u16 *mac_deci_tbl;
+	struct workqueue_struct *config_wq;
+	bool bq4_dtim;
+	struct work_struct set_tim_work;
+	u8 enable_beacon;
+	u8 beacon_interval;
+	u8 beacon_dtim_cnt;
+	u8 beacon_usage;
+	struct ssv6xxx_beacon_info beacon_info[2];
+	struct sk_buff *beacon_buf;
+	struct work_struct bcast_start_work;
+	struct delayed_work bcast_stop_work;
+	struct delayed_work bcast_tx_work;
+	struct delayed_work thermal_monitor_work;
+	struct workqueue_struct *thermal_wq;
+	int is_sar_enabled;
+	bool aid0_bit_set;
+	u8 hw_mng_used;
+	struct ssv6xxx_bcast_txq bcast_txq;
+	int bcast_interval;
+	u8 bssid[6];
+	struct mutex mem_mutex;
+	spinlock_t ps_state_lock;
+	u8 hw_wsid_bit;
+	int rx_ba_session_count;
+	struct ieee80211_sta *rx_ba_sta;
+	u8 rx_ba_bitmap;
+	u8 ba_ra_addr[ETH_ALEN];
+	u16 ba_tid;
+	u16 ba_ssn;
+	struct work_struct set_ampdu_rx_add_work;
+	struct work_struct set_ampdu_rx_del_work;
+	bool isAssoc;
+	u16 channel_center_freq;
+	bool bScanning;
+	int ps_status;
+	u16 ps_aid;
+	u16 tx_wait_q_woken;
+	wait_queue_head_t tx_wait_q;
+	struct sk_buff_head tx_skb_q;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	u32 max_tx_skb_q_len;
+#endif
+	struct task_struct *tx_task;
+	bool tx_q_empty;
+	struct sk_buff_head tx_done_q;
+	u16 rx_wait_q_woken;
+	wait_queue_head_t rx_wait_q;
+	struct sk_buff_head rx_skb_q;
+	struct task_struct *rx_task;
+	bool dbg_rx_frame;
+	bool dbg_tx_frame;
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct dentry *debugfs_dir;
+#endif
+#ifdef CONFIG_P2P_NOA
+	struct ssv_p2p_noa p2p_noa;
+#endif
+	struct timer_list watchdog_timeout;
+	u32 watchdog_flag;
+	wait_queue_head_t fw_wait_q;
+	u32 iq_cali_done;
+	u32 sr_bhvr;
+};
+enum {
+	IQ_CALI_RUNNING,
+	IQ_CALI_OK,
+	IQ_CALI_FAILED
+};
+enum {
+	WD_SLEEP,
+	WD_BARKING,
+	WD_KICKED,
+	WD_MAX
+};
+void ssv6xxx_txbuf_free_skb(struct sk_buff *skb, void *args);
+void ssv6200_rx_process(struct work_struct *work);
+#if !defined(USE_THREAD_RX) || defined(USE_BATCH_RX)
+int ssv6200_rx(struct sk_buff_head *rx_skb_q, void *args);
+#else
+int ssv6200_rx(struct sk_buff *rx_skb, void *args);
+#endif
+void ssv6xxx_tx_cb(struct sk_buff_head *skb_head, void *args);
+void ssv6xxx_tx_rate_update(struct sk_buff *skb, void *args);
+int ssv6200_tx_flow_control(void *dev, int hw_txqid, bool fc_en, int debug);
+void ssv6xxx_tx_q_empty_cb(u32 txq_no, void *);
+int ssv6xxx_rf_disable(struct ssv_hw *sh);
+int ssv6xxx_rf_enable(struct ssv_hw *sh);
+int ssv6xxx_set_channel(struct ssv_softc *sc, int ch);
+#ifdef CONFIG_SSV_SMARTLINK
+int ssv6xxx_get_channel(struct ssv_softc *sc, int *pch);
+int ssv6xxx_set_promisc(struct ssv_softc *sc, int accept);
+int ssv6xxx_get_promisc(struct ssv_softc *sc, int *paccept);
+#endif
+int ssv6xxx_tx_task(void *data);
+int ssv6xxx_rx_task(void *data);
+u32 ssv6xxx_pbuf_alloc(struct ssv_softc *sc, int size, int type);
+bool ssv6xxx_pbuf_free(struct ssv_softc *sc, u32 pbuf_addr);
+void ssv6xxx_add_txinfo(struct ssv_softc *sc, struct sk_buff *skb);
+void ssv6xxx_update_txinfo(struct ssv_softc *sc, struct sk_buff *skb);
+int ssv6xxx_update_decision_table(struct ssv_softc *sc);
+void ssv6xxx_ps_callback_func(unsigned long data);
+void ssv6xxx_enable_ps(struct ssv_softc *sc);
+void ssv6xxx_disable_ps(struct ssv_softc *sc);
+int ssv6xxx_watchdog_controller(struct ssv_hw *sh, u8 flag);
+int ssv6xxx_skb_encrypt(struct sk_buff *mpdu, struct ssv_softc *sc);
+int ssv6xxx_skb_decrypt(struct sk_buff *mpdu, struct ieee80211_sta *sta,
+			struct ssv_softc *sc);
+void ssv6200_sync_hw_key_sequence(struct ssv_softc *sc,
+				  struct ssv_sta_info *sta_info, bool bWrite);
+struct ieee80211_sta *ssv6xxx_find_sta_by_rx_skb(struct ssv_softc *sc,
+						 struct sk_buff *skb);
+struct ieee80211_sta *ssv6xxx_find_sta_by_addr(struct ssv_softc *sc,
+					       u8 addr[6]);
+void ssv6xxx_foreach_sta(struct ssv_softc *sc,
+			 void (*sta_func)(struct ssv_softc *,
+					  struct ssv_sta_info *, void *),
+			 void *param);
+void ssv6xxx_foreach_vif_sta(struct ssv_softc *sc,
+			     struct ssv_vif_info *vif_info,
+			     void (*sta_func)(struct ssv_softc *,
+					      struct ssv_vif_info *,
+					      struct ssv_sta_info *, void *),
+			     void *param);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+ssize_t ssv6xxx_tx_queue_status_dump(struct ssv_softc *sc, char *status_buf,
+				     ssize_t buf_size);
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/dev_tbl.h b/drivers/net/wireless/ssv6051/smac/dev_tbl.h
new file mode 100644
index 00000000000..5c49d0bde6a
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/dev_tbl.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DEV_TBL_H_
+#define _DEV_TBL_H_
+#include "ssv6200_configuration.h"
+#include "drv_comm.h"
+struct ssv6xxx_dev_table {
+	u32 address;
+	u32 data;
+};
+#define ssv6200_phy_tbl phy_setting
+#define ssv6200_rf_tbl asic_rf_setting
+#define ACTION_DO_NOTHING 0
+#define ACTION_UPDATE_NAV 1
+#define ACTION_RESET_NAV 2
+#define ACTION_SIGNAL_ACK 3
+#define FRAME_ACCEPT 0
+#define FRAME_DROP 1
+#define SET_DEC_TBL(_type,_mask,_action,_drop) \
+    (_type<<9| \
+    _mask <<3| \
+    _action<<1| \
+    _drop)
+u16 generic_deci_tbl[] = {
+	SET_DEC_TBL(0x1e, 0x3e, ACTION_RESET_NAV, FRAME_DROP),
+	SET_DEC_TBL(0x18, 0x3e, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+	SET_DEC_TBL(0x1a, 0x3f, ACTION_DO_NOTHING, FRAME_ACCEPT),
+	SET_DEC_TBL(0x10, 0x38, ACTION_DO_NOTHING, FRAME_DROP),
+	0,
+	0,
+	0,
+	SET_DEC_TBL(0x05, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+	SET_DEC_TBL(0x0b, 0x3f, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+	SET_DEC_TBL(0x01, 0x3d, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+	SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_ACCEPT),
+	SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_ACCEPT),
+	SET_DEC_TBL(0x00, 0x00, ACTION_DO_NOTHING, FRAME_DROP),
+	SET_DEC_TBL(0x00, 0x00, ACTION_UPDATE_NAV, FRAME_DROP),
+	SET_DEC_TBL(0x00, 0x00, ACTION_RESET_NAV, FRAME_DROP),
+	SET_DEC_TBL(0x00, 0x00, ACTION_SIGNAL_ACK, FRAME_DROP),
+	0x2008,
+	0x1001,
+	0x0400,
+	0x0400,
+	0x2000,
+	0x800E,
+	0x0800,
+	0x0B88,
+	0x0800,
+};
+
+#define SET_PHY_INFO(_ctsdur,_ba_rate_idx,_ack_rate_idx,_llength_idx,_llength_enable) \
+         (_ctsdur<<16| \
+         _ba_rate_idx <<10| \
+         _ack_rate_idx<<4| \
+         _llength_idx<<1| \
+         _llength_enable)
+#define SET_PHY_L_LENGTH(_l_ba,_l_rts,_l_cts_ack) (_l_ba<<12|_l_rts<<6 |_l_cts_ack)
+static u32 phy_info_6051z[] = {
+	0x18000000, 0x18000100, 0x18000200, 0x18000300, 0x18000140,
+	0x18000240, 0x18000340, 0x0C000001, 0x0C000101, 0x0C000201,
+	0x0C000301, 0x18000401, 0x18000501, 0x18000601, 0x18000701,
+	0x0C030002, 0x0C030102, 0x0C030202, 0x18030302, 0x18030402,
+	0x18030502, 0x18030602, 0x1C030702, 0x0C030082, 0x0C030182,
+	0x0C030282, 0x18030382, 0x18030482, 0x18030582, 0x18030682,
+	0x1C030782, 0x0C030042, 0x0C030142, 0x0C030242, 0x18030342,
+	0x18030442, 0x18030542, 0x18030642, 0x1C030742
+};
+
+static u32 phy_info_tbl[] = {
+	0x0C000000, 0x0C000100, 0x0C000200, 0x0C000300, 0x0C000140,
+	0x0C000240, 0x0C000340, 0x00000001, 0x00000101, 0x00000201,
+	0x00000301, 0x0C000401, 0x0C000501, 0x0C000601, 0x0C000701,
+	0x00030002, 0x00030102, 0x00030202, 0x0C030302, 0x0C030402,
+	0x0C030502, 0x0C030602, 0x10030702, 0x00030082, 0x00030182,
+	0x00030282, 0x0C030382, 0x0C030482, 0x0C030582, 0x0C030682,
+	0x10030782, 0x00030042, 0x00030142, 0x00030242, 0x0C030342,
+	0x0C030442, 0x0C030542, 0x0C030642, 0x10030742,
+	SET_PHY_INFO(314, 0, 0, 0, 0),
+	SET_PHY_INFO(258, 0, 1, 0, 0),
+	SET_PHY_INFO(223, 0, 1, 0, 0),
+	SET_PHY_INFO(213, 0, 1, 0, 0),
+	SET_PHY_INFO(162, 0, 4, 0, 0),
+	SET_PHY_INFO(127, 0, 4, 0, 0),
+	SET_PHY_INFO(117, 0, 4, 0, 0),
+	SET_PHY_INFO(60, 7, 7, 0, 0),
+	SET_PHY_INFO(52, 7, 7, 0, 0),
+	SET_PHY_INFO(48, 9, 9, 0, 0),
+	SET_PHY_INFO(44, 9, 9, 0, 0),
+	SET_PHY_INFO(44, 11, 11, 0, 0),
+	SET_PHY_INFO(40, 11, 11, 0, 0),
+	SET_PHY_INFO(40, 11, 11, 0, 0),
+	SET_PHY_INFO(40, 11, 11, 0, 0),
+	SET_PHY_INFO(76, 7, 7, 0, 1),
+	SET_PHY_INFO(64, 9, 9, 1, 1),
+	SET_PHY_INFO(60, 9, 9, 2, 1),
+	SET_PHY_INFO(60, 11, 11, 3, 1),
+	SET_PHY_INFO(56, 11, 11, 4, 1),
+	SET_PHY_INFO(56, 11, 11, 5, 1),
+	SET_PHY_INFO(56, 11, 11, 5, 1),
+	SET_PHY_INFO(56, 11, 11, 5, 1),
+	SET_PHY_INFO(76, 7, 7, 6, 1),
+	SET_PHY_INFO(64, 9, 9, 1, 1),
+	SET_PHY_INFO(60, 9, 9, 2, 1),
+	SET_PHY_INFO(60, 11, 11, 3, 1),
+	SET_PHY_INFO(56, 11, 11, 4, 1),
+	SET_PHY_INFO(56, 11, 11, 5, 1),
+	SET_PHY_INFO(56, 11, 11, 5, 1),
+	SET_PHY_INFO(56, 11, 11, 5, 1),
+	SET_PHY_INFO(64, 7, 7, 0, 0),
+	SET_PHY_INFO(52, 9, 9, 0, 0),
+	SET_PHY_INFO(48, 9, 9, 0, 0),
+	SET_PHY_INFO(48, 11, 11, 0, 0),
+	SET_PHY_INFO(44, 11, 11, 0, 0),
+	SET_PHY_INFO(44, 11, 11, 0, 0),
+	SET_PHY_INFO(44, 11, 11, 0, 0),
+	SET_PHY_INFO(44, 11, 11, 0, 0),
+	SET_PHY_L_LENGTH(50, 38, 35),
+	SET_PHY_L_LENGTH(35, 29, 26),
+	SET_PHY_L_LENGTH(29, 26, 23),
+	SET_PHY_L_LENGTH(26, 23, 23),
+	SET_PHY_L_LENGTH(23, 23, 20),
+	SET_PHY_L_LENGTH(23, 20, 20),
+	SET_PHY_L_LENGTH(47, 38, 35),
+	SET_PHY_L_LENGTH(0, 0, 0),
+};
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/drv_comm.h b/drivers/net/wireless/ssv6051/smac/drv_comm.h
new file mode 100644
index 00000000000..f04fbae004c
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/drv_comm.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DRV_COMM_H_
+#define _DRV_COMM_H_
+#define PHY_INFO_TBL1_SIZE 39
+#define PHY_INFO_TBL2_SIZE 39
+#define PHY_INFO_TBL3_SIZE 8
+#define ampdu_fw_rate_info_status_no_use BIT(0)
+#define ampdu_fw_rate_info_status_in_use BIT(1)
+#define ampdu_fw_rate_info_status_reset BIT(2)
+#define SSV_NUM_STA 8
+#define SSV_NUM_VIF 2
+#define SECURITY_KEY_LEN (32)
+enum SSV_CIPHER_E {
+	SSV_CIPHER_NONE,
+	SSV_CIPHER_WEP40,
+	SSV_CIPHER_WEP104,
+	SSV_CIPHER_TKIP,
+	SSV_CIPHER_CCMP,
+	SSV_CIPHER_SMS4,
+	SSV_CIPHER_INVALID = (-1)
+};
+#define ME_NONE 0
+#define ME_WEP40 1
+#define ME_WEP104 2
+#define ME_TKIP 3
+#define ME_CCMP 4
+#define ME_SMS4 5
+struct ssv6xxx_hw_key {
+	u8 key[SECURITY_KEY_LEN];
+	u32 tx_pn_l;
+	u32 tx_pn_h;
+	u32 rx_pn_l;
+	u32 rx_pn_h;
+} __attribute__((packed));
+struct ssv6xxx_hw_sta_key {
+	u8 pair_key_idx:4;
+	u8 group_key_idx:4;
+	u8 valid;
+	u8 reserve[2];
+	struct ssv6xxx_hw_key pair;
+} __attribute__((packed));
+struct ssv6xxx_hw_sec {
+	struct ssv6xxx_hw_key group_key[3];
+	struct ssv6xxx_hw_sta_key sta_key[8];
+} __attribute__((packed));
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/efuse.c b/drivers/net/wireless/ssv6051/smac/efuse.c
new file mode 100644
index 00000000000..9a1f3f5488f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/efuse.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/etherdevice.h>
+#include <ssv6200.h>
+#include "efuse.h"
+
+struct file *openFile(char *path, int flag, int mode)
+{
+	struct file *fp = NULL;
+	fp = filp_open(path, flag, 0);
+	if (IS_ERR(fp))
+		return NULL;
+	else
+		return fp;
+}
+
+int readFile(struct file *fp, char *buf, int readlen)
+{
+	if (fp->f_op && fp->f_op->read)
+		return fp->f_op->read(fp, buf, readlen, &fp->f_pos);
+	else
+		return -1;
+}
+
+int closeFile(struct file *fp)
+{
+	filp_close(fp, NULL);
+	return 0;
+}
+
+void initKernelEnv(void)
+{
+}
+
+void parseMac(char *mac, u_int8_t addr[])
+{
+	long b;
+	int i;
+	for (i = 0; i < 6; i++) {
+		b = simple_strtol(mac + (3 * i), (char **)NULL, 16);
+		addr[i] = (char)b;
+	}
+}
+
+static int readfile_mac(u8 * path, u8 * mac_addr)
+{
+	char buf[128];
+	struct file *fp = NULL;
+	int ret = 0;
+	fp = openFile(path, O_RDONLY, 0);
+	if (fp != NULL) {
+		initKernelEnv();
+		memset(buf, 0, 128);
+		if ((ret = readFile(fp, buf, 128)) > 0) {
+			parseMac(buf, (uint8_t *) mac_addr);
+		} else
+			pr_err("read file error %d=[%s]\n", ret, path);
+		closeFile(fp);
+	} else
+		pr_err("Read open File fail[%s]!!!! \n", path);
+	return ret;
+}
+
+static int write_mac_to_file(u8 * mac_path, u8 * mac_addr)
+{
+	char buf[128];
+	struct file *fp = NULL;
+	int ret = 0, len;
+	fp = openFile(mac_path, O_WRONLY | O_CREAT, 0640);
+	if (fp != NULL) {
+		initKernelEnv();
+		memset(buf, 0, 128);
+		sprintf(buf, "%x:%x:%x:%x:%x:%x", mac_addr[0], mac_addr[1],
+			mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
+		len = strlen(buf) + 1;
+		fp->f_op->write(fp, (char *)buf, len, &fp->f_pos);
+		closeFile(fp);
+	} else
+		pr_err("Write open File fail!!!![%s] \n", mac_path);
+	return ret;
+}
+
+static struct efuse_map SSV_EFUSE_ITEM_TABLE[] = {
+	{4, 0, 0},
+	{4, 8, 0},
+	{4, 8, 0},
+	{4, 48, 0},
+	{4, 8, 0},
+	{4, 8, 0},
+	{4, 8, 0},
+};
+
+static u8 read_efuse(struct ssv_hw *sh, u8 * pbuf)
+{
+	extern struct ssv6xxx_cfg ssv_cfg;
+	u32 val, i;
+	u32 *temp = (u32 *) pbuf;
+	SMAC_REG_WRITE(sh, 0xC0000328, 0x11);
+	SMAC_REG_WRITE(sh, SSV_EFUSE_ID_READ_SWITCH, 0x1);
+	SMAC_REG_READ(sh, SSV_EFUSE_ID_RAW_DATA_BASE, &val);
+	ssv_cfg.chip_identity = val;
+	SMAC_REG_WRITE(sh, SSV_EFUSE_READ_SWITCH, 0x1);
+	SMAC_REG_READ(sh, SSV_EFUSE_RAW_DATA_BASE, &val);
+	if (val == 0x00) {
+		return 0;
+	}
+	for (i = 0; i < (EFUSE_MAX_SECTION_MAP); i++) {
+		SMAC_REG_WRITE(sh, SSV_EFUSE_READ_SWITCH + i * 4, 0x1);
+		SMAC_REG_READ(sh, SSV_EFUSE_RAW_DATA_BASE + i * 4, &val);
+		*temp++ = val;
+	}
+	SMAC_REG_WRITE(sh, 0xC0000328, 0x1800000a);
+	return 1;
+}
+
+static u16 parser_efuse(u8 * pbuf, u8 * mac_addr)
+{
+	u8 *rtemp8, idx = 0;
+	u16 shift = 0, i;
+	u16 efuse_real_content_len = 0;
+	rtemp8 = pbuf;
+	if (*rtemp8 == 0x00) {
+		return efuse_real_content_len;
+	}
+	do {
+		idx = (*(rtemp8) >> shift) & 0xf;
+		switch (idx) {
+		case EFUSE_R_CALIBRATION_RESULT:
+		case EFUSE_CRYSTAL_FREQUENCY_OFFSET:
+		case EFUSE_TX_POWER_INDEX_1:
+		case EFUSE_TX_POWER_INDEX_2:
+		case EFUSE_SAR_RESULT:
+			if (shift) {
+				rtemp8++;
+				SSV_EFUSE_ITEM_TABLE[idx].value =
+				    (u16) ((u8) (*((u16 *) rtemp8)) &
+					   ((1 <<
+					     SSV_EFUSE_ITEM_TABLE
+					     [idx].byte_cnts) - 1));
+			} else {
+				SSV_EFUSE_ITEM_TABLE[idx].value =
+				    (u16) ((u8) (*((u16 *) rtemp8) >> 4) &
+					   ((1 <<
+					     SSV_EFUSE_ITEM_TABLE
+					     [idx].byte_cnts) - 1));
+			}
+			efuse_real_content_len +=
+			    (SSV_EFUSE_ITEM_TABLE[idx].offset +
+			     SSV_EFUSE_ITEM_TABLE[idx].byte_cnts);
+			break;
+		case EFUSE_MAC:
+			if (shift) {
+				rtemp8++;
+				memcpy(mac_addr, rtemp8, 6);
+			} else {
+				for (i = 0; i < 6; i++) {
+					mac_addr[i] =
+					    (u16) (*((u16 *) rtemp8) >> 4) &
+					    0xff;
+					rtemp8++;
+				}
+			}
+			efuse_real_content_len +=
+			    (SSV_EFUSE_ITEM_TABLE[idx].offset +
+			     SSV_EFUSE_ITEM_TABLE[idx].byte_cnts);
+			break;
+		default:
+			idx = 0;
+			break;
+		}
+		shift = efuse_real_content_len % 8;
+		rtemp8 = &pbuf[efuse_real_content_len / 8];
+	} while (idx != 0);
+	return efuse_real_content_len;
+}
+
+void addr_increase_copy(u8 * dst, u8 * src)
+{
+	u8 *a = (u8 *) dst;
+	const u8 *b = (const u8 *)src;
+	a[0] = b[0];
+	a[1] = b[1];
+	a[2] = b[2];
+	a[3] = b[3];
+	a[4] = b[4];
+	if (b[5] & 0x1)
+		a[5] = b[5] - 1;
+	else
+		a[5] = b[5] + 1;
+}
+
+static u8 key_char2num(u8 ch)
+{
+	if ((ch >= '0') && (ch <= '9'))
+		return ch - '0';
+	else if ((ch >= 'a') && (ch <= 'f'))
+		return ch - 'a' + 10;
+	else if ((ch >= 'A') && (ch <= 'F'))
+		return ch - 'A' + 10;
+	else
+		return 0xff;
+}
+
+u8 key_2char2num(u8 hch, u8 lch)
+{
+	return ((key_char2num(hch) << 4) | key_char2num(lch));
+}
+
+extern struct ssv6xxx_cfg ssv_cfg;
+extern char *ssv_initmac;
+void efuse_read_all_map(struct ssv_hw *sh)
+{
+	u8 mac[ETH_ALEN] = { 0 };
+	int jj, kk;
+	u8 efuse_mapping_table[EFUSE_HWSET_MAX_SIZE / 8];
+#ifndef CONFIG_SSV_RANDOM_MAC
+	u8 pseudo_mac0[ETH_ALEN] = { 0x00, 0x33, 0x33, 0x33, 0x33, 0x33 };
+#endif
+	u8 rom_mac0[ETH_ALEN];
+	memset(rom_mac0, 0x00, ETH_ALEN);
+	memset(efuse_mapping_table, 0x00, EFUSE_HWSET_MAX_SIZE / 8);
+	read_efuse(sh, efuse_mapping_table);
+	parser_efuse(efuse_mapping_table, rom_mac0);
+	ssv_cfg.r_calbration_result =
+	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_R_CALIBRATION_RESULT].value;
+	ssv_cfg.sar_result = (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_SAR_RESULT].value;
+	ssv_cfg.crystal_frequency_offset =
+	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_CRYSTAL_FREQUENCY_OFFSET].value;
+	ssv_cfg.tx_power_index_1 =
+	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_TX_POWER_INDEX_1].value;
+	ssv_cfg.tx_power_index_2 =
+	    (u8) SSV_EFUSE_ITEM_TABLE[EFUSE_TX_POWER_INDEX_2].value;
+	if (!is_valid_ether_addr(&sh->cfg.maddr[0][0])) {
+		if (!sh->cfg.ignore_efuse_mac) {
+			if (is_valid_ether_addr(rom_mac0)) {
+				dev_info(sh->sc->dev, "Using MAC address from e-fuse\n");
+				memcpy(&sh->cfg.maddr[0][0], rom_mac0,
+				       ETH_ALEN);
+				addr_increase_copy(&sh->cfg.maddr[1][0],
+						   rom_mac0);
+				goto Done;
+			}
+		}
+		if (ssv_initmac != NULL) {
+			for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) {
+				mac[jj] =
+				    key_2char2num(ssv_initmac[kk],
+						  ssv_initmac[kk + 1]);
+			}
+			if (is_valid_ether_addr(mac)) {
+				dev_info(sh->sc->dev, "Using MAC address from module option\n");
+				memcpy(&sh->cfg.maddr[0][0], mac, ETH_ALEN);
+				addr_increase_copy(&sh->cfg.maddr[1][0], mac);
+				goto Done;
+			}
+		}
+		if (sh->cfg.mac_address_path[0] != 0x00) {
+			if ((readfile_mac
+			     (sh->cfg.mac_address_path, &sh->cfg.maddr[0][0]))
+			    && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) {
+				dev_info
+				    (sh->sc->dev, "Using MAC address from configuration file\n");
+				addr_increase_copy(&sh->cfg.maddr[1][0],
+						   &sh->cfg.maddr[0][0]);
+				goto Done;
+			}
+		}
+		switch (sh->cfg.mac_address_mode) {
+		case 1:
+			get_random_bytes(&sh->cfg.maddr[0][0], ETH_ALEN);
+			sh->cfg.maddr[0][0] = sh->cfg.maddr[0][0] & 0xF0;
+			addr_increase_copy(&sh->cfg.maddr[1][0],
+					   &sh->cfg.maddr[0][0]);
+			break;
+		case 2:
+			if ((readfile_mac
+			     (sh->cfg.mac_output_path, &sh->cfg.maddr[0][0]))
+			    && (is_valid_ether_addr(&sh->cfg.maddr[0][0]))) {
+				addr_increase_copy(&sh->cfg.maddr[1][0],
+						   &sh->cfg.maddr[0][0]);
+			} else {
+				{
+					get_random_bytes(&sh->cfg.maddr[0][0],
+							 ETH_ALEN);
+					sh->cfg.maddr[0][0] =
+					    sh->cfg.maddr[0][0] & 0xF0;
+					addr_increase_copy(&sh->cfg.maddr[1][0],
+							   &sh->
+							   cfg.maddr[0][0]);
+					if (sh->cfg.mac_output_path[0] != 0x00)
+						write_mac_to_file(sh->
+								  cfg.mac_output_path,
+								  &sh->
+								  cfg.maddr[0]
+								  [0]);
+				}
+			}
+			break;
+		default:
+			memcpy(&sh->cfg.maddr[0][0], pseudo_mac0, ETH_ALEN);
+			addr_increase_copy(&sh->cfg.maddr[1][0], pseudo_mac0);
+			break;
+		}
+		dev_info(sh->sc->dev, "MAC address from Software MAC mode[%d]\n",
+			sh->cfg.mac_address_mode);
+	}
+ Done:
+	dev_info(sh->sc->dev, "Chip identity from efuse: %08x\n", ssv_cfg.chip_identity);
+	dev_dbg(sh->sc->dev, "r_calbration_result- %x\n", ssv_cfg.r_calbration_result);
+	dev_dbg(sh->sc->dev, "sar_result- %x\n", ssv_cfg.sar_result);
+	dev_dbg(sh->sc->dev, "crystal_frequency_offset- %x\n",
+		 ssv_cfg.crystal_frequency_offset);
+	dev_dbg(sh->sc->dev, "tx_power_index_1- %x\n", ssv_cfg.tx_power_index_1);
+	dev_dbg(sh->sc->dev, "tx_power_index_2- %x\n", ssv_cfg.tx_power_index_2);
+	dev_dbg(sh->sc->dev, "MAC address - %pM\n", rom_mac0);
+	sh->cfg.crystal_frequency_offset = ssv_cfg.crystal_frequency_offset;
+	sh->cfg.tx_power_index_1 = ssv_cfg.tx_power_index_1;
+	sh->cfg.tx_power_index_2 = ssv_cfg.tx_power_index_2;
+	sh->cfg.chip_identity = ssv_cfg.chip_identity;
+}
diff --git a/drivers/net/wireless/ssv6051/smac/efuse.h b/drivers/net/wireless/ssv6051/smac/efuse.h
new file mode 100644
index 00000000000..c25280c5aba
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/efuse.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_EFUSE_H_
+#define _SSV_EFUSE_H_
+#include "dev.h"
+struct efuse_map {
+	u8 offset;
+	u8 byte_cnts;
+	u16 value;
+};
+enum efuse_data_item {
+	EFUSE_R_CALIBRATION_RESULT = 1,
+	EFUSE_SAR_RESULT,
+	EFUSE_MAC,
+	EFUSE_CRYSTAL_FREQUENCY_OFFSET,
+	EFUSE_TX_POWER_INDEX_1,
+	EFUSE_TX_POWER_INDEX_2
+};
+#define EFUSE_HWSET_MAX_SIZE (256-32)
+#define EFUSE_MAX_SECTION_MAP (EFUSE_HWSET_MAX_SIZE>>5)
+#define SSV_EFUSE_ID_READ_SWITCH 0xC2000128
+#define SSV_EFUSE_ID_RAW_DATA_BASE 0xC200014C
+#define SSV_EFUSE_READ_SWITCH 0xC200012C
+#define SSV_EFUSE_RAW_DATA_BASE 0xC2000150
+void efuse_read_all_map(struct ssv_hw *sh);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/init.c b/drivers/net/wireless/ssv6051/smac/init.c
new file mode 100644
index 00000000000..592c52a2838
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/init.c
@@ -0,0 +1,1347 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/nl80211.h>
+#include <linux/kthread.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
+#include <crypto/hash.h>
+#else
+#include <linux/crypto.h>
+#endif
+#include <ssv6200.h>
+#include <hci/hctrl.h>
+#include <ssv_firmware_version.h>
+#include "dev_tbl.h"
+#include "dev.h"
+#include "lib.h"
+#include "ssv_rc.h"
+#include "ap.h"
+#include "efuse.h"
+#include "sar.h"
+#include "ssv_cfgvendor.h"
+
+#include "linux_80211.h"
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+#include "ssv6xxx_debugfs.h"
+#endif
+
+#define WIFI_FIRMWARE_NAME "ssv6051-sw.bin"
+static const struct ieee80211_iface_limit ssv6xxx_p2p_limits[] = {
+	{
+	 .max = 2,
+	 .types = BIT(NL80211_IFTYPE_STATION),
+	 },
+	{
+	 .max = 1,
+	 .types = BIT(NL80211_IFTYPE_P2P_GO) |
+	 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_AP),
+	 },
+};
+
+static const struct ieee80211_iface_combination
+ ssv6xxx_iface_combinations_p2p[] = {
+	{.num_different_channels = 1,
+	 .max_interfaces = SSV6200_MAX_VIF,
+	 .beacon_int_infra_match = true,
+	 .limits = ssv6xxx_p2p_limits,
+	 .n_limits = ARRAY_SIZE(ssv6xxx_p2p_limits),
+	 },
+};
+
+#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
+    (((a) & 0xff00ff00) >> 8))
+#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
+#define CHAN2G(_freq,_idx) { \
+    .band = INDEX_80211_BAND_2GHZ, \
+    .center_freq = (_freq), \
+    .hw_value = (_idx), \
+    .max_power = 20, \
+}
+#ifndef WLAN_CIPHER_SUITE_SMS4
+#define WLAN_CIPHER_SUITE_SMS4 0x00147201
+#endif
+#define SHPCHECK(__hw_rate,__flags) \
+    ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate +3 ) : 0)
+#define RATE(_bitrate,_hw_rate,_flags) { \
+    .bitrate = (_bitrate), \
+    .flags = (_flags), \
+    .hw_value = (_hw_rate), \
+    .hw_value_short = SHPCHECK(_hw_rate,_flags) \
+}
+extern struct ssv6xxx_cfg ssv_cfg;
+static const struct ieee80211_channel ssv6200_2ghz_chantable[] = {
+	CHAN2G(2412, 1),
+	CHAN2G(2417, 2),
+	CHAN2G(2422, 3),
+	CHAN2G(2427, 4),
+	CHAN2G(2432, 5),
+	CHAN2G(2437, 6),
+	CHAN2G(2442, 7),
+	CHAN2G(2447, 8),
+	CHAN2G(2452, 9),
+	CHAN2G(2457, 10),
+	CHAN2G(2462, 11),
+	CHAN2G(2467, 12),
+	CHAN2G(2472, 13),
+	CHAN2G(2484, 14),
+};
+
+static struct ieee80211_rate ssv6200_legacy_rates[] = {
+	RATE(10, 0x00, 0),
+	RATE(20, 0x01, IEEE80211_RATE_SHORT_PREAMBLE),
+	RATE(55, 0x02, IEEE80211_RATE_SHORT_PREAMBLE),
+	RATE(110, 0x03, IEEE80211_RATE_SHORT_PREAMBLE),
+	RATE(60, 0x07, 0),
+	RATE(90, 0x08, 0),
+	RATE(120, 0x09, 0),
+	RATE(180, 0x0a, 0),
+	RATE(240, 0x0b, 0),
+	RATE(360, 0x0c, 0),
+	RATE(480, 0x0d, 0),
+	RATE(540, 0x0e, 0),
+};
+
+struct ssv6xxx_ch_cfg ch_cfg_z[] = {
+	{ADR_ABB_REGISTER_1, 0, 0x151559fc},
+	{ADR_LDO_REGISTER, 0, 0x00eb7c1c},
+	{ADR_RX_ADC_REGISTER, 0, 0x20d000d2}
+};
+
+struct ssv6xxx_ch_cfg ch_cfg_p[] = {
+	{ADR_ABB_REGISTER_1, 0, 0x151559fc},
+	{ADR_RX_ADC_REGISTER, 0, 0x20d000d2}
+};
+
+int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg)
+{
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	int ret = 0;
+	dev_dbg(sh->sc->dev, "# Do init_cali (iq)\n");
+	skb =
+	    ssv_skb_alloc(HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE +
+			  RF_SETTING_SIZE);
+	if (skb == NULL) {
+		dev_err(sh->sc->dev, "init ssv6xxx_do_iq_calib failure\n");
+		return (-1);
+	}
+	if ((PHY_SETTING_SIZE > MAX_PHY_SETTING_TABLE_SIZE) ||
+	    (RF_SETTING_SIZE > MAX_RF_SETTING_TABLE_SIZE)) {
+		dev_warn(sh->sc->dev, "wrong RF or PHY table size\n");
+		WARN_ON(1);
+		return (-1);
+	}
+	skb->data_len =
+	    HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE;
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_INIT_CALI;
+	host_cmd->len = skb->data_len;
+	p_cfg->phy_tbl_size = PHY_SETTING_SIZE;
+	p_cfg->rf_tbl_size = RF_SETTING_SIZE;
+	memcpy(host_cmd->dat32, p_cfg, IQK_CFG_LEN);
+	memcpy(host_cmd->dat8 + IQK_CFG_LEN, phy_setting, PHY_SETTING_SIZE);
+	memcpy(host_cmd->dat8 + IQK_CFG_LEN + PHY_SETTING_SIZE, ssv6200_rf_tbl,
+	       RF_SETTING_SIZE);
+	sh->hci.hci_ops->hci_send_cmd(skb);
+	ssv_skb_free(skb);
+	{
+		u32 timeout;
+		sh->sc->iq_cali_done = IQ_CALI_RUNNING;
+		set_current_state(TASK_INTERRUPTIBLE);
+		timeout = wait_event_interruptible_timeout(sh->sc->fw_wait_q,
+							   sh->sc->iq_cali_done,
+							   msecs_to_jiffies
+							   (500));
+		set_current_state(TASK_RUNNING);
+		if (timeout == 0)
+			return -ETIME;
+		if (sh->sc->iq_cali_done != IQ_CALI_OK)
+			return (-1);
+	}
+	return ret;
+}
+
+#define HT_CAP_RX_STBC_ONE_STREAM 0x1
+#if defined(CONFIG_PM)
+static const struct wiphy_wowlan_support wowlan_support = {
+#ifdef SSV_WAKEUP_HOST
+	.flags = WIPHY_WOWLAN_ANY,
+#else
+	.flags = WIPHY_WOWLAN_DISCONNECT,
+#endif
+	.n_patterns = 0,
+	.pattern_max_len = 0,
+	.pattern_min_len = 0,
+	.max_pkt_offset = 0,
+};
+#endif
+static void ssv6xxx_set_80211_hw_capab(struct ssv_softc *sc)
+{
+	struct ieee80211_hw *hw = sc->hw;
+	struct ssv_hw *sh = sc->sh;
+	struct ieee80211_sta_ht_cap *ht_info;
+	ieee80211_hw_set(hw, SIGNAL_DBM);
+	hw->rate_control_algorithm = "ssv6xxx_rate_control";
+	//hw->rate_control_algorithm = NULL; // NULL selects default
+	ht_info = &sc->sbands[INDEX_80211_BAND_2GHZ].ht_cap;
+	ampdu_db_log("sh->cfg.hw_caps = 0x%x\n", sh->cfg.hw_caps);
+	if (sh->cfg.hw_caps & SSV6200_HW_CAP_HT) {
+		if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_RX) {
+			ieee80211_hw_set(hw, AMPDU_AGGREGATION);
+			ampdu_db_log("set IEEE80211_HW_AMPDU_AGGREGATION(%d)\n",
+				     ieee80211_hw_check(hw, AMPDU_AGGREGATION));
+		}
+		ht_info->cap = IEEE80211_HT_CAP_SM_PS;
+		if (sh->cfg.hw_caps & SSV6200_HW_CAP_GF) {
+			ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
+			ht_info->cap |=
+			    HT_CAP_RX_STBC_ONE_STREAM <<
+			    IEEE80211_HT_CAP_RX_STBC_SHIFT;
+		}
+		if (sh->cfg.hw_caps & SSV6200_HT_CAP_SGI_20)
+			ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
+		ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_32K;
+		ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
+		memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
+		ht_info->mcs.rx_mask[0] = 0xff;
+		ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
+		ht_info->mcs.rx_highest = cpu_to_le16(SSV6200_RX_HIGHEST_RATE);
+		ht_info->ht_supported = true;
+	}
+	hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
+	if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) {
+		hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_CLIENT);
+		hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_P2P_GO);
+		hw->wiphy->iface_combinations = ssv6xxx_iface_combinations_p2p;
+		hw->wiphy->n_iface_combinations =
+		    ARRAY_SIZE(ssv6xxx_iface_combinations_p2p);
+	}
+	hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
+	if (sh->cfg.hw_caps & SSV6200_HW_CAP_AP) {
+		hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
+		hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
+	}
+	if (sh->cfg.hw_caps & SSV6200_HW_CAP_TDLS) {
+		hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
+		hw->wiphy->flags |= WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
+		dev_info(sc->dev, "TDLS function enabled in sta.cfg\n");
+	}
+	hw->queues = 4;
+	hw->max_rates = 4;
+	hw->max_listen_interval = 1;
+	hw->max_rate_tries = HW_MAX_RATE_TRIES;
+	hw->extra_tx_headroom = TXPB_OFFSET + AMPDU_DELIMITER_LEN;
+	if (sizeof(struct ampdu_hdr_st) > SSV_SKB_info_size)
+		hw->extra_tx_headroom += sizeof(struct ampdu_hdr_st);
+	else
+		hw->extra_tx_headroom += SSV_SKB_info_size;
+	if (sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
+		hw->wiphy->bands[INDEX_80211_BAND_2GHZ] =
+		    &sc->sbands[INDEX_80211_BAND_2GHZ];
+	}
+	if (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX)
+#ifdef PREFER_RX
+		hw->max_rx_aggregation_subframes = 64;
+#else
+		hw->max_rx_aggregation_subframes = 16;
+#endif
+	else
+		hw->max_rx_aggregation_subframes = 12;
+	hw->max_tx_aggregation_subframes = 64;
+	hw->sta_data_size = sizeof(struct ssv_sta_priv_data);
+	hw->vif_data_size = sizeof(struct ssv_vif_priv_data);
+	memcpy(sh->maddr[0].addr, &sh->cfg.maddr[0][0], ETH_ALEN);
+	hw->wiphy->addresses = sh->maddr;
+	hw->wiphy->n_addresses = 1;
+	if (sh->cfg.hw_caps & SSV6200_HW_CAP_P2P) {
+		int i;
+		for (i = 1; i < SSV6200_MAX_HW_MAC_ADDR; i++) {
+			memcpy(sh->maddr[i].addr, sh->maddr[i - 1].addr,
+			       ETH_ALEN);
+			sh->maddr[i].addr[5]++;
+			hw->wiphy->n_addresses++;
+		}
+	}
+	if (!is_zero_ether_addr(sh->cfg.maddr[1])) {
+		memcpy(sh->maddr[1].addr, sh->cfg.maddr[1], ETH_ALEN);
+		if (hw->wiphy->n_addresses < 2)
+			hw->wiphy->n_addresses = 2;
+	}
+#if defined(CONFIG_PM)
+	hw->wiphy->wowlan = &wowlan_support;
+#endif
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) && defined(CONFIG_SSV_VENDOR_EXT_SUPPORT)
+    {
+        int err = 0;
+        struct ssv_softc *softc = (struct ssv_softc *)hw->priv;
+        if (softc)
+        {
+            set_wiphy_dev(hw->wiphy, softc->dev);
+            *((struct ssv_softc **)wiphy_priv(hw->wiphy)) = softc;
+        }
+       	dev_dbg(sc->dev, "Registering Vendor80211\n");
+       	err = ssv_cfgvendor_attach(hw->wiphy);
+       	if (unlikely(err < 0)) {
+       		dev_err(sc->dev, "Couldn not attach vendor commands (%d)\n", err);
+       	}
+    }
+#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(3, 14, 0)) || defined(WL_VENDOR_EXT_SUPPORT) */
+}
+
+void ssv6xxx_watchdog_restart_hw(struct ssv_softc *sc)
+{
+	dev_dbg(sc->dev, "%s()\n", __FUNCTION__);
+	sc->restart_counter++;
+	sc->force_triger_reset = true;
+	sc->beacon_info[0].pubf_addr = 0x00;
+	sc->beacon_info[1].pubf_addr = 0x00;
+	ieee80211_restart_hw(sc->hw);
+}
+
+extern struct rssi_res_st rssi_res;
+void ssv6200_watchdog_timeout(struct timer_list *t)
+{
+	static u32 count = 0;
+	struct rssi_res_st *rssi_tmp0 = NULL, *rssi_tmp1 = NULL;
+	struct ssv_softc *sc = from_timer(sc, t, watchdog_timeout);
+	if (sc->watchdog_flag == WD_BARKING) {
+		ssv6xxx_watchdog_restart_hw(sc);
+		mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
+		return;
+	}
+	if (sc->watchdog_flag != WD_SLEEP)
+		sc->watchdog_flag = WD_BARKING;
+	count++;
+	if (count == 6) {
+		count = 0;
+		if (list_empty(&rssi_res.rssi_list)) {
+			return;
+		}
+		list_for_each_entry_safe(rssi_tmp0, rssi_tmp1,
+					 &rssi_res.rssi_list, rssi_list) {
+			if (rssi_tmp0->timeout) {
+				list_del_rcu(&rssi_tmp0->rssi_list);
+				kfree(rssi_tmp0);
+			}
+		}
+	}
+	mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
+	return;
+}
+
+static void ssv6xxx_preload_sw_cipher(void)
+{
+}
+
+static int ssv6xxx_init_softc(struct ssv_softc *sc)
+{
+	void *channels;
+	int ret = 0;
+	sc->sc_flags = SC_OP_INVALID;
+	mutex_init(&sc->mutex);
+	mutex_init(&sc->mem_mutex);
+	sc->config_wq = create_singlethread_workqueue("ssv6xxx_cong_wq");
+	sc->thermal_wq = create_singlethread_workqueue("ssv6xxx_thermal_wq");
+	INIT_DELAYED_WORK(&sc->thermal_monitor_work, thermal_monitor);
+	INIT_WORK(&sc->set_tim_work, ssv6200_set_tim_work);
+	INIT_WORK(&sc->bcast_start_work, ssv6200_bcast_start_work);
+	INIT_DELAYED_WORK(&sc->bcast_stop_work, ssv6200_bcast_stop_work);
+	INIT_DELAYED_WORK(&sc->bcast_tx_work, ssv6200_bcast_tx_work);
+	INIT_WORK(&sc->set_ampdu_rx_add_work, ssv6xxx_set_ampdu_rx_add_work);
+	INIT_WORK(&sc->set_ampdu_rx_del_work, ssv6xxx_set_ampdu_rx_del_work);
+	sc->mac_deci_tbl = sta_deci_tbl;
+	memset((void *)&sc->tx, 0, sizeof(struct ssv_tx));
+	sc->tx.hw_txqid[WMM_AC_VO] = 3;
+	sc->tx.ac_txqid[3] = WMM_AC_VO;
+	sc->tx.hw_txqid[WMM_AC_VI] = 2;
+	sc->tx.ac_txqid[2] = WMM_AC_VI;
+	sc->tx.hw_txqid[WMM_AC_BE] = 1;
+	sc->tx.ac_txqid[1] = WMM_AC_BE;
+	sc->tx.hw_txqid[WMM_AC_BK] = 0;
+	sc->tx.ac_txqid[0] = WMM_AC_BK;
+	INIT_LIST_HEAD(&sc->tx.ampdu_tx_que);
+	spin_lock_init(&sc->tx.ampdu_tx_que_lock);
+	memset((void *)&sc->rx, 0, sizeof(struct ssv_rx));
+	spin_lock_init(&sc->rx.rxq_lock);
+	skb_queue_head_init(&sc->rx.rxq_head);
+	sc->rx.rx_buf = ssv_skb_alloc(MAX_FRAME_SIZE);
+	if (sc->rx.rx_buf == NULL)
+		return -ENOMEM;
+	memset(&sc->bcast_txq, 0, sizeof(struct ssv6xxx_bcast_txq));
+	spin_lock_init(&sc->bcast_txq.txq_lock);
+	skb_queue_head_init(&sc->bcast_txq.qhead);
+	spin_lock_init(&sc->ps_state_lock);
+#ifdef CONFIG_P2P_NOA
+	spin_lock_init(&sc->p2p_noa.p2p_config_lock);
+#endif
+	if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
+		channels = kmemdup(ssv6200_2ghz_chantable,
+				   sizeof(ssv6200_2ghz_chantable), GFP_KERNEL);
+		if (!channels) {
+			kfree(sc->rx.rx_buf);
+			return -ENOMEM;
+		}
+		sc->sbands[INDEX_80211_BAND_2GHZ].channels = channels;
+		sc->sbands[INDEX_80211_BAND_2GHZ].band = INDEX_80211_BAND_2GHZ;
+		sc->sbands[INDEX_80211_BAND_2GHZ].n_channels =
+		    ARRAY_SIZE(ssv6200_2ghz_chantable);
+		sc->sbands[INDEX_80211_BAND_2GHZ].bitrates =
+		    ssv6200_legacy_rates;
+		sc->sbands[INDEX_80211_BAND_2GHZ].n_bitrates =
+		    ARRAY_SIZE(ssv6200_legacy_rates);
+	}
+	sc->cur_channel = NULL;
+	sc->hw_chan = (-1);
+	ssv6xxx_set_80211_hw_capab(sc);
+	ret = ssv6xxx_rate_control_register();
+	if (ret != 0) {
+		dev_warn(sc->dev, "%s(): Failed to register rc algorithm.\n",__FUNCTION__);
+	}
+	init_waitqueue_head(&sc->tx_wait_q);
+	sc->tx_wait_q_woken = 0;
+	skb_queue_head_init(&sc->tx_skb_q);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	sc->max_tx_skb_q_len = 0;
+#endif
+	sc->tx_task = kthread_run(ssv6xxx_tx_task, sc, "ssv6xxx_tx_task");
+	sc->tx_q_empty = false;
+	skb_queue_head_init(&sc->tx_done_q);
+	init_waitqueue_head(&sc->rx_wait_q);
+	sc->rx_wait_q_woken = 0;
+	skb_queue_head_init(&sc->rx_skb_q);
+	sc->rx_task = kthread_run(ssv6xxx_rx_task, sc, "ssv6xxx_rx_task");
+	ssv6xxx_preload_sw_cipher();
+	timer_setup(&sc->watchdog_timeout, ssv6200_watchdog_timeout, 0);
+	init_waitqueue_head(&sc->fw_wait_q);
+	INIT_LIST_HEAD(&rssi_res.rssi_list);
+	rssi_res.rssi = 0;
+	mod_timer(&sc->watchdog_timeout, jiffies + WATCHDOG_TIMEOUT);
+	//add_timer(&sc->watchdog_timeout);
+	//if(get_flash_info(sc) == 1)
+	sc->is_sar_enabled = get_flash_info(sc);
+	if (sc->is_sar_enabled)
+		queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
+				   THERMAL_MONITOR_TIME);
+	//schedule_delayed_work(&sc->thermal_monitor_work, THERMAL_MONITOR_TIME);
+	return ret;
+}
+
+static int ssv6xxx_deinit_softc(struct ssv_softc *sc)
+{
+	void *channels;
+	struct sk_buff *skb;
+	u8 remain_size;
+	dev_dbg(sc->dev, "%s():\n", __FUNCTION__);
+	if (sc->sh->cfg.hw_caps & SSV6200_HW_CAP_2GHZ) {
+		channels = sc->sbands[INDEX_80211_BAND_2GHZ].channels;
+		kfree(channels);
+	}
+	ssv_skb_free(sc->rx.rx_buf);
+	sc->rx.rx_buf = NULL;
+	ssv6xxx_rate_control_unregister();
+	cancel_delayed_work_sync(&sc->bcast_tx_work);
+	//ssv6xxx_watchdog_controller(sc->sh ,(u8)SSV6XXX_HOST_CMD_WATCHDOG_STOP);
+	del_timer_sync(&sc->watchdog_timeout);
+	cancel_delayed_work(&sc->thermal_monitor_work);
+	sc->ps_status = PWRSV_PREPARE;
+	flush_workqueue(sc->thermal_wq);
+	destroy_workqueue(sc->thermal_wq);
+	do {
+		skb = ssv6200_bcast_dequeue(&sc->bcast_txq, &remain_size);
+		if (skb)
+			ssv6xxx_txbuf_free_skb(skb, (void *)sc);
+		else
+			break;
+	} while (remain_size);
+	if (sc->tx_task != NULL) {
+		dev_dbg(sc->dev, "Stopping TX task...\n");
+		kthread_stop(sc->tx_task);
+		sc->tx_task = NULL;
+		dev_dbg(sc->dev, "Stopped TX task.\n");
+	}
+	if (sc->rx_task != NULL) {
+		dev_dbg(sc->dev, "Stopping RX task...\n");
+		kthread_stop(sc->rx_task);
+		sc->rx_task = NULL;
+		dev_dbg(sc->dev, "Stopped RX task.\n");
+	}
+	destroy_workqueue(sc->config_wq);
+	return 0;
+}
+
+static void ssv6xxx_hw_set_replay_ignore(struct ssv_hw *sh, u8 ignore)
+{
+	u32 temp;
+	SMAC_REG_READ(sh, ADR_SCRT_SET, &temp);
+	temp = temp & SCRT_RPLY_IGNORE_I_MSK;
+	temp |= (ignore << SCRT_RPLY_IGNORE_SFT);
+	SMAC_REG_WRITE(sh, ADR_SCRT_SET, temp);
+}
+
+int ssv6xxx_init_mac(struct ssv_hw *sh)
+{
+	struct ssv_softc *sc = sh->sc;
+	int i = 0, ret = 0;
+
+	u32 *ptr, id_len, regval, temp[0x8];
+	char *chip_id = sh->chip_id;
+	SMAC_REG_READ(sh, ADR_IC_TIME_TAG_1, &regval);
+	sh->chip_tag = ((u64) regval << 32);
+	SMAC_REG_READ(sh, ADR_IC_TIME_TAG_0, &regval);
+	sh->chip_tag |= (regval);
+	SMAC_REG_READ(sh, ADR_CHIP_ID_3, &regval);
+	*((u32 *) & chip_id[0]) = (u32) LONGSWAP(regval);
+	SMAC_REG_READ(sh, ADR_CHIP_ID_2, &regval);
+	*((u32 *) & chip_id[4]) = (u32) LONGSWAP(regval);
+	SMAC_REG_READ(sh, ADR_CHIP_ID_1, &regval);
+	*((u32 *) & chip_id[8]) = (u32) LONGSWAP(regval);
+	SMAC_REG_READ(sh, ADR_CHIP_ID_0, &regval);
+	*((u32 *) & chip_id[12]) = (u32) LONGSWAP(regval);
+	chip_id[12 + sizeof(u32)] = 0;
+	dev_info(sh->sc->dev, "chip id: %s, tag: %llx\n", chip_id, sh->chip_tag);
+	if (sc->ps_status == PWRSV_ENABLE) {
+		SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA,
+			       M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) |
+			       (M_ENG_HWHCI << 8));
+		SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_MNG,
+			       M_ENG_MACRX | (M_ENG_HWHCI << 4));
+#if Enable_AMPDU_FW_Retry
+		SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
+			       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI <<
+								 8));
+#else
+		SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
+			       M_ENG_MACRX | (M_ENG_HWHCI << 4));
+#endif
+		SMAC_REG_WRITE(sc->sh, ADR_MRX_FLT_TB0 + 6 * 4,
+			       (sc->mac_deci_tbl[6]));
+		return ret;
+	}
+	SMAC_REG_SET_BITS(sh, ADR_PHY_EN_1, (0 << RG_PHY_MD_EN_SFT),
+			  RG_PHY_MD_EN_MSK);
+	SMAC_REG_WRITE(sh, ADR_BRG_SW_RST, 1 << MAC_SW_RST_SFT);
+	do {
+		SMAC_REG_READ(sh, ADR_BRG_SW_RST, &regval);
+		i++;
+		if (i > 10000) {
+			dev_err(sh->sc->dev, "MAC reset fail !!!!\n");
+			WARN_ON(1);
+			ret = 1;
+			goto exit;
+		}
+	} while (regval != 0);
+	SMAC_REG_WRITE(sc->sh, ADR_TXQ4_MTX_Q_AIFSN, 0xffff2101);
+	SMAC_REG_SET_BITS(sc->sh, ADR_MTX_BCN_EN_MISC, 0,
+			  MTX_HALT_MNG_UNTIL_DTIM_MSK);
+	SMAC_REG_WRITE(sh, ADR_CONTROL, 0x12000006);
+	SMAC_REG_WRITE(sh, ADR_RX_TIME_STAMP_CFG,
+		       ((28 << MRX_STP_OFST_SFT) | 0x01));
+	SMAC_REG_WRITE(sh, ADR_HCI_TX_RX_INFO_SIZE,
+		       ((u32) (TXPB_OFFSET) << TX_PBOFFSET_SFT) |
+		       ((u32) (sh->tx_desc_len) << TX_INFO_SIZE_SFT) |
+		       ((u32) (sh->rx_desc_len) << RX_INFO_SIZE_SFT) |
+		       ((u32) (sh->rx_pinfo_pad) << RX_LAST_PHY_SIZE_SFT)
+	    );
+	SMAC_REG_READ(sh, ADR_MMU_CTRL, &regval);
+	regval |= (0xff << MMU_SHARE_MCU_SFT);
+	SMAC_REG_WRITE(sh, ADR_MMU_CTRL, regval);
+	SMAC_REG_READ(sh, ADR_MRX_WATCH_DOG, &regval);
+	regval &= 0xfffffff0;
+	SMAC_REG_WRITE(sh, ADR_MRX_WATCH_DOG, regval);
+	SMAC_REG_READ(sh, ADR_TRX_ID_THRESHOLD, &id_len);
+	id_len = (id_len & 0xffff0000) |
+	    (SSV6200_ID_TX_THRESHOLD << TX_ID_THOLD_SFT) |
+	    (SSV6200_ID_RX_THRESHOLD << RX_ID_THOLD_SFT);
+	SMAC_REG_WRITE(sh, ADR_TRX_ID_THRESHOLD, id_len);
+	SMAC_REG_READ(sh, ADR_ID_LEN_THREADSHOLD1, &id_len);
+	id_len = (id_len & 0x0f) |
+	    (SSV6200_PAGE_TX_THRESHOLD << ID_TX_LEN_THOLD_SFT) |
+	    (SSV6200_PAGE_RX_THRESHOLD << ID_RX_LEN_THOLD_SFT);
+	SMAC_REG_WRITE(sh, ADR_ID_LEN_THREADSHOLD1, id_len);
+#ifdef CONFIG_SSV_CABRIO_MB_DEBUG
+	SMAC_REG_READ(sh, ADR_MB_DBG_CFG3, &regval);
+	regval |= (debug_buffer << 0);
+	SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG3, regval);
+	SMAC_REG_READ(sh, ADR_MB_DBG_CFG2, &regval);
+	regval |= (DEBUG_SIZE << 16);
+	SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG2, regval);
+	SMAC_REG_READ(sh, ADR_MB_DBG_CFG1, &regval);
+	regval |= (1 << MB_DBG_EN_SFT);
+	SMAC_REG_WRITE(sh, ADR_MB_DBG_CFG1, regval);
+	SMAC_REG_READ(sh, ADR_MBOX_HALT_CFG, &regval);
+	regval |= (1 << MB_ERR_AUTO_HALT_EN_SFT);
+	SMAC_REG_WRITE(sh, ADR_MBOX_HALT_CFG, regval);
+#endif
+	SMAC_REG_READ(sc->sh, ADR_MTX_BCN_EN_MISC, &regval);
+	regval |= (1 << MTX_TSF_TIMER_EN_SFT);
+	SMAC_REG_WRITE(sc->sh, ADR_MTX_BCN_EN_MISC, regval);
+	SMAC_REG_WRITE(sh, 0xcd010004, 0x1213);
+	for (i = 0; i < SSV_RC_MAX_STA; i++) {
+		if (i == 0) {
+			sh->hw_buf_ptr[i] =
+			    ssv6xxx_pbuf_alloc(sc,
+					       sizeof(phy_info_tbl) +
+					       sizeof(struct ssv6xxx_hw_sec),
+					       NOTYPE_BUF);
+			if ((sh->hw_buf_ptr[i] >> 28) != 8) {
+				dev_err(sh->sc->dev, "opps allocate pbuf error\n");
+				WARN_ON(1);
+				ret = 1;
+				goto exit;
+			}
+		} else {
+			sh->hw_buf_ptr[i] =
+			    ssv6xxx_pbuf_alloc(sc,
+					       sizeof(struct ssv6xxx_hw_sec),
+					       NOTYPE_BUF);
+			if ((sh->hw_buf_ptr[i] >> 28) != 8) {
+				dev_err(sh->sc->dev, "opps allocate pbuf error\n");
+				WARN_ON(1);
+				ret = 1;
+				goto exit;
+			}
+		}
+	}
+	for (i = 0; i < 0x8; i++) {
+		temp[i] = 0;
+		temp[i] = ssv6xxx_pbuf_alloc(sc, 256, NOTYPE_BUF);
+	}
+	for (i = 0; i < 0x8; i++) {
+		if (temp[i] == 0x800e0000)
+			dev_dbg(sh->sc->dev, "Found 0x800e0000 at position %d\n", i);
+		else
+			ssv6xxx_pbuf_free(sc, temp[i]);
+	}
+	for (i = 0; i < SSV_RC_MAX_STA; i++)
+		sh->hw_sec_key[i] = sh->hw_buf_ptr[i];
+	for (i = 0; i < SSV_RC_MAX_STA; i++) {
+		int x;
+		for (x = 0; x < sizeof(struct ssv6xxx_hw_sec); x += 4) {
+			SMAC_REG_WRITE(sh, sh->hw_sec_key[i] + x, 0);
+		}
+	}
+	SMAC_REG_READ(sh, ADR_SCRT_SET, &regval);
+	regval &= SCRT_PKT_ID_I_MSK;
+	regval |= ((sh->hw_sec_key[0] >> 16) << SCRT_PKT_ID_SFT);
+	SMAC_REG_WRITE(sh, ADR_SCRT_SET, regval);
+	sh->hw_pinfo = sh->hw_sec_key[0] + sizeof(struct ssv6xxx_hw_sec);
+	for (i = 0, ptr = phy_info_tbl; i < PHY_INFO_TBL1_SIZE; i++, ptr++) {
+		SMAC_REG_WRITE(sh, ADR_INFO0 + i * 4, *ptr);
+		SMAC_REG_CONFIRM(sh, ADR_INFO0 + i * 4, *ptr);
+	}
+	for (i = 0; i < PHY_INFO_TBL2_SIZE; i++, ptr++) {
+		SMAC_REG_WRITE(sh, sh->hw_pinfo + i * 4, *ptr);
+		SMAC_REG_CONFIRM(sh, sh->hw_pinfo + i * 4, *ptr);
+	}
+	for (i = 0; i < PHY_INFO_TBL3_SIZE; i++, ptr++) {
+		SMAC_REG_WRITE(sh, sh->hw_pinfo +
+			       (PHY_INFO_TBL2_SIZE << 2) + i * 4, *ptr);
+		SMAC_REG_CONFIRM(sh, sh->hw_pinfo +
+				 (PHY_INFO_TBL2_SIZE << 2) + i * 4, *ptr);
+	}
+	SMAC_REG_WRITE(sh, ADR_INFO_RATE_OFFSET, 0x00040000);
+	SMAC_REG_WRITE(sh, ADR_INFO_IDX_ADDR, sh->hw_pinfo);
+	SMAC_REG_WRITE(sh, ADR_INFO_LEN_ADDR,
+		       sh->hw_pinfo + (PHY_INFO_TBL2_SIZE) * 4);
+	dev_dbg(sh->sc->dev, "ADR_INFO_IDX_ADDR[%08x] ADR_INFO_LEN_ADDR[%08x]\n",
+	       sh->hw_pinfo, sh->hw_pinfo + (PHY_INFO_TBL2_SIZE) * 4);
+	SMAC_REG_WRITE(sh, ADR_GLBLE_SET,
+		       (0 << OP_MODE_SFT) | (0 << SNIFFER_MODE_SFT) | (1 <<
+								       DUP_FLT_SFT)
+		       | (SSV6200_TX_PKT_RSVD_SETTING << TX_PKT_RSVD_SFT) |
+		       ((u32) (RXPB_OFFSET) << PB_OFFSET_SFT)
+	    );
+	SMAC_REG_WRITE(sh, ADR_STA_MAC_0, *((u32 *) & sh->cfg.maddr[0][0]));
+	SMAC_REG_WRITE(sh, ADR_STA_MAC_1, *((u32 *) & sh->cfg.maddr[0][4]));
+	SMAC_REG_WRITE(sh, ADR_BSSID_0, *((u32 *) & sc->bssid[0]));
+	SMAC_REG_WRITE(sh, ADR_BSSID_1, *((u32 *) & sc->bssid[4]));
+	SMAC_REG_WRITE(sh, ADR_TX_ETHER_TYPE_0, 0x00000000);
+	SMAC_REG_WRITE(sh, ADR_TX_ETHER_TYPE_1, 0x00000000);
+	SMAC_REG_WRITE(sh, ADR_RX_ETHER_TYPE_0, 0x00000000);
+	SMAC_REG_WRITE(sh, ADR_RX_ETHER_TYPE_1, 0x00000000);
+	SMAC_REG_WRITE(sh, ADR_REASON_TRAP0, 0x7FBC7F87);
+	SMAC_REG_WRITE(sh, ADR_REASON_TRAP1, 0x0000003F);
+	SMAC_REG_WRITE(sh, ADR_TRAP_HW_ID, M_ENG_CPU);
+	SMAC_REG_WRITE(sh, ADR_WSID0, 0x00000000);
+	SMAC_REG_WRITE(sh, ADR_WSID1, 0x00000000);
+	SMAC_REG_WRITE(sh, ADR_RX_FLOW_DATA,
+		       M_ENG_MACRX | (M_ENG_ENCRYPT_SEC << 4) | (M_ENG_HWHCI <<
+								 8));
+#if defined(CONFIG_P2P_NOA) || defined(CONFIG_RX_MGMT_CHECK)
+	SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG,
+		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
+#else
+	SMAC_REG_WRITE(sh, ADR_RX_FLOW_MNG, M_ENG_MACRX | (M_ENG_HWHCI << 4));
+#endif
+#if Enable_AMPDU_FW_Retry
+	SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL,
+		       M_ENG_MACRX | (M_ENG_CPU << 4) | (M_ENG_HWHCI << 8));
+#else
+	SMAC_REG_WRITE(sh, ADR_RX_FLOW_CTRL, M_ENG_MACRX | (M_ENG_HWHCI << 4));
+#endif
+	ssv6xxx_hw_set_replay_ignore(sh, 1);
+	ssv6xxx_update_decision_table(sc);
+	SMAC_REG_SET_BITS(sc->sh, ADR_GLBLE_SET, SSV6200_OPMODE_STA,
+			  OP_MODE_MSK);
+	SMAC_REG_WRITE(sh, ADR_SDIO_MASK, 0xfffe1fff);
+	SMAC_REG_WRITE(sh, ADR_TX_LIMIT_INTR, 0x80000000 |
+		       SSV6200_TX_LOWTHRESHOLD_ID_TRIGGER << 16 |
+		       SSV6200_TX_LOWTHRESHOLD_PAGE_TRIGGER);
+#ifdef CONFIG_SSV_SUPPORT_BTCX
+	SMAC_REG_WRITE(sh, ADR_BTCX0,
+		       COEXIST_EN_MSK | (WIRE_MODE_SZ << WIRE_MODE_SFT)
+		       | WIFI_TX_SW_POL_MSK | BT_SW_POL_MSK);
+	SMAC_REG_WRITE(sh, ADR_BTCX1,
+		       SSV6200_BT_PRI_SMP_TIME | (SSV6200_BT_STA_SMP_TIME <<
+						  BT_STA_SMP_TIME_SFT)
+		       | (SSV6200_WLAN_REMAIN_TIME << WLAN_REMAIN_TIME_SFT));
+	SMAC_REG_WRITE(sh, ADR_SWITCH_CTL, BT_2WIRE_EN_MSK);
+	SMAC_REG_WRITE(sh, ADR_PAD7, 1);
+	SMAC_REG_WRITE(sh, ADR_PAD8, 0);
+	SMAC_REG_WRITE(sh, ADR_PAD9, 1);
+	SMAC_REG_WRITE(sh, ADR_PAD25, 1);
+	SMAC_REG_WRITE(sh, ADR_PAD27, 8);
+	SMAC_REG_WRITE(sh, ADR_PAD28, 8);
+#endif
+	dev_info(sh->sc->dev, "attempt to load firmware %s\n", WIFI_FIRMWARE_NAME);
+	ret = SMAC_LOAD_FW(sh, WIFI_FIRMWARE_NAME, 0);
+
+	SMAC_REG_READ(sh, FW_VERSION_REG, &regval);
+	if (regval == ssv_firmware_version) {
+		SMAC_REG_SET_BITS(sh, ADR_PHY_EN_1, (1 << RG_PHY_MD_EN_SFT),
+				  RG_PHY_MD_EN_MSK);
+		dev_info(sh->sc->dev, "Firmware version %d\n", regval);
+	} else {
+		dev_err(sh->sc->dev, "Firmware version not mapping %d\n", regval);
+		ret = -1;
+	}
+	ssv6xxx_watchdog_controller(sh, (u8) SSV6XXX_HOST_CMD_WATCHDOG_START);
+ exit:
+	return ret;
+}
+
+void ssv6xxx_deinit_mac(struct ssv_softc *sc)
+{
+	int i;
+	for (i = 0; i < SSV_RC_MAX_STA; i++) {
+		if (sc->sh->hw_buf_ptr[i])
+			ssv6xxx_pbuf_free(sc, sc->sh->hw_buf_ptr[i]);
+	}
+}
+
+void inline ssv6xxx_deinit_hw(struct ssv_softc *sc)
+{
+	dev_dbg(sc->dev, "%s(): \n", __FUNCTION__);
+	ssv6xxx_deinit_mac(sc);
+}
+
+void ssv6xxx_restart_hw(struct ssv_softc *sc)
+{
+	dev_info(sc->dev, "Software MAC reset\n");
+	sc->restart_counter++;
+	sc->force_triger_reset = true;
+	HCI_STOP(sc->sh);
+	SMAC_REG_WRITE(sc->sh, 0xce000004, 0x0);
+	sc->beacon_info[0].pubf_addr = 0x00;
+	sc->beacon_info[1].pubf_addr = 0x00;
+	ieee80211_restart_hw(sc->hw);
+}
+
+extern struct ssv6xxx_iqk_cfg init_iqk_cfg;
+static int ssv6xxx_init_hw(struct ssv_hw *sh)
+{
+	int ret = 0, i = 0, x = 0;
+	u32 regval;
+	sh->tx_desc_len = SSV6XXX_TX_DESC_LEN;
+	sh->rx_desc_len = SSV6XXX_RX_DESC_LEN;
+	sh->rx_pinfo_pad = 0x04;
+	sh->tx_page_available = SSV6200_PAGE_TX_THRESHOLD;
+	sh->ampdu_divider = SSV6XXX_AMPDU_DIVIDER;
+	memset(sh->page_count, 0, sizeof(sh->page_count));
+	if (sh->cfg.force_chip_identity) {
+		dev_info(sh->sc->dev, "Force use external RF setting [%08x]\n",
+		       sh->cfg.force_chip_identity);
+		sh->cfg.chip_identity = sh->cfg.force_chip_identity;
+	}
+	if (sh->cfg.chip_identity == SSV6051Z) {
+		sh->p_ch_cfg = &ch_cfg_z[0];
+		sh->ch_cfg_size =
+		    sizeof(ch_cfg_z) / sizeof(struct ssv6xxx_ch_cfg);
+		memcpy(phy_info_tbl, phy_info_6051z, sizeof(phy_info_6051z));
+	} else if (sh->cfg.chip_identity == SSV6051P) {
+		sh->p_ch_cfg = &ch_cfg_p[0];
+		sh->ch_cfg_size =
+		    sizeof(ch_cfg_p) / sizeof(struct ssv6xxx_ch_cfg);
+	}
+	switch (sh->cfg.chip_identity) {
+	case SSV6051Q_P1:
+	case SSV6051Q_P2:
+	case SSV6051Q:
+		dev_info(sh->sc->dev, "Using SSV6051Q setting\n");
+		for (i = 0;
+		     i <
+		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (ssv6200_rf_tbl[i].address == 0xCE010008)
+				ssv6200_rf_tbl[i].data = 0x008DF61B;
+			if (ssv6200_rf_tbl[i].address == 0xCE010014)
+				ssv6200_rf_tbl[i].data = 0x3D3E84FE;
+			if (ssv6200_rf_tbl[i].address == 0xCE010018)
+				ssv6200_rf_tbl[i].data = 0x01457D79;
+			if (ssv6200_rf_tbl[i].address == 0xCE01001C)
+				ssv6200_rf_tbl[i].data = 0x000103A7;
+			if (ssv6200_rf_tbl[i].address == 0xCE010020)
+				ssv6200_rf_tbl[i].data = 0x000103A6;
+			if (ssv6200_rf_tbl[i].address == 0xCE01002C)
+				ssv6200_rf_tbl[i].data = 0x00032CA8;
+			if (ssv6200_rf_tbl[i].address == 0xCE010048)
+				ssv6200_rf_tbl[i].data = 0xFCCCCF27;
+			if (ssv6200_rf_tbl[i].address == 0xCE010050)
+				ssv6200_rf_tbl[i].data = 0x0047C000;
+		}
+		break;
+	case SSV6051Z:
+		dev_info(sh->sc->dev, "Using SSV6051Z setting\n");
+		for (i = 0;
+		     i <
+		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (ssv6200_rf_tbl[i].address == 0xCE010008)
+				ssv6200_rf_tbl[i].data = 0x004D561C;
+			if (ssv6200_rf_tbl[i].address == 0xCE010014)
+				ssv6200_rf_tbl[i].data = 0x3D9E84FE;
+			if (ssv6200_rf_tbl[i].address == 0xCE010018)
+				ssv6200_rf_tbl[i].data = 0x00457D79;
+			if (ssv6200_rf_tbl[i].address == 0xCE01001C)
+				ssv6200_rf_tbl[i].data = 0x000103EB;
+			if (ssv6200_rf_tbl[i].address == 0xCE010020)
+				ssv6200_rf_tbl[i].data = 0x000103EA;
+			if (ssv6200_rf_tbl[i].address == 0xCE01002C)
+				ssv6200_rf_tbl[i].data = 0x00062CA8;
+			if (ssv6200_rf_tbl[i].address == 0xCE010048)
+				ssv6200_rf_tbl[i].data = 0xFCCCCF27;
+			if (ssv6200_rf_tbl[i].address == 0xCE010050)
+				ssv6200_rf_tbl[i].data = 0x0047C000;
+		}
+		break;
+	case SSV6051P:
+		dev_info(sh->sc->dev, "Using SSV6051P setting\n");
+		for (i = 0;
+		     i <
+		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (ssv6200_rf_tbl[i].address == 0xCE010008)
+				ssv6200_rf_tbl[i].data = 0x008B7C1C;
+			if (ssv6200_rf_tbl[i].address == 0xCE010014)
+				ssv6200_rf_tbl[i].data = 0x3D7E84FE;
+			if (ssv6200_rf_tbl[i].address == 0xCE010018)
+				ssv6200_rf_tbl[i].data = 0x01457D79;
+			if (ssv6200_rf_tbl[i].address == 0xCE01001C)
+				ssv6200_rf_tbl[i].data = 0x000103EB;
+			if (ssv6200_rf_tbl[i].address == 0xCE010020)
+				ssv6200_rf_tbl[i].data = 0x000103EA;
+			if (ssv6200_rf_tbl[i].address == 0xCE01002C)
+				ssv6200_rf_tbl[i].data = 0x00032CA8;
+			if (ssv6200_rf_tbl[i].address == 0xCE010048)
+				ssv6200_rf_tbl[i].data = 0xFCCCCC27;
+			if (ssv6200_rf_tbl[i].address == 0xCE010050)
+				ssv6200_rf_tbl[i].data = 0x0047C000;
+			if (ssv6200_rf_tbl[i].address == 0xC0001D00)
+				ssv6200_rf_tbl[i].data = 0x5E000040;
+		}
+		break;
+	default:
+		dev_err(sh->sc->dev, "No RF setting\n");
+		break;
+	}
+	if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_26M) {
+		init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_26M;
+		dev_info(sh->sc->dev, "Crystal frequency: 26 Mhz\n");
+	} else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_40M) {
+		init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_40M;
+		dev_info(sh->sc->dev, "Crystal frequency: 40 Mhz\n");
+	} else if (sh->cfg.crystal_type == SSV6XXX_IQK_CFG_XTAL_24M) {
+		init_iqk_cfg.cfg_xtal = SSV6XXX_IQK_CFG_XTAL_24M;
+		dev_info(sh->sc->dev, "Crystal frequency: 24 Mhz\n");
+		for (i = 0;
+		     i <
+		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (ssv6200_rf_tbl[i].address == ADR_SX_ENABLE_REGISTER)
+				ssv6200_rf_tbl[i].data = 0x0003E07C;
+			if (ssv6200_rf_tbl[i].address ==
+			    ADR_DPLL_DIVIDER_REGISTER)
+				ssv6200_rf_tbl[i].data = 0x00406000;
+			if (ssv6200_rf_tbl[i].address ==
+			    ADR_DPLL_FB_DIVIDER_REGISTERS_I)
+				ssv6200_rf_tbl[i].data = 0x00000028;
+			if (ssv6200_rf_tbl[i].address ==
+			    ADR_DPLL_FB_DIVIDER_REGISTERS_II)
+				ssv6200_rf_tbl[i].data = 0x00000000;
+		}
+	} else {
+		dev_warn(sh->sc->dev, "Illegal crystal setting, using default value of 26 Mhz\n");
+	}
+	for (i = 0;
+	     i < sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+	     i++) {
+		if (ssv6200_rf_tbl[i].address ==
+		    ADR_SYN_KVCO_XO_FINE_TUNE_CBANK) {
+			if (sh->cfg.crystal_frequency_offset) {
+				ssv6200_rf_tbl[i].data &=
+				    RG_XOSC_CBANK_XO_I_MSK;
+				ssv6200_rf_tbl[i].data |=
+				    (sh->cfg.
+				     crystal_frequency_offset <<
+				     RG_XOSC_CBANK_XO_SFT);
+			}
+		}
+	}
+	for (i = 0; i < sizeof(phy_setting) / sizeof(struct ssv6xxx_dev_table);
+	     i++) {
+		if (phy_setting[i].address == ADR_TX_GAIN_FACTOR) {
+			switch (sh->cfg.chip_identity) {
+			case SSV6051Q_P1:
+			case SSV6051Q_P2:
+			case SSV6051Q:
+				dev_dbg(sh->sc->dev, "SSV6051Q setting [0x5B606C72]\n");
+				phy_setting[i].data = 0x5B606C72;
+				break;
+			case SSV6051Z:
+				dev_dbg(sh->sc->dev, "SSV6051Z setting [0x60606060]\n");
+				phy_setting[i].data = 0x60606060;
+				break;
+			case SSV6051P:
+				dev_dbg(sh->sc->dev, "SSV6051P setting [0x6C726C72]\n");
+				phy_setting[i].data = 0x6C726C72;
+				break;
+			default:
+				dev_dbg(sh->sc->dev, "Use default power setting\n");
+				break;
+			}
+			if (sh->cfg.wifi_tx_gain_level_b) {
+				phy_setting[i].data &= 0xffff0000;
+				phy_setting[i].data |=
+				    wifi_tx_gain[sh->cfg.
+						 wifi_tx_gain_level_b] &
+				    0x0000ffff;
+			}
+			if (sh->cfg.wifi_tx_gain_level_gn) {
+				phy_setting[i].data &= 0x0000ffff;
+				phy_setting[i].data |=
+				    wifi_tx_gain[sh->cfg.
+						 wifi_tx_gain_level_gn] &
+				    0xffff0000;
+			}
+			dev_dbg(sh->sc->dev, "TX power setting 0x%x\n", phy_setting[i].data);
+			init_iqk_cfg.cfg_def_tx_scale_11b =
+			    (phy_setting[i].data >> 0) & 0xff;
+			init_iqk_cfg.cfg_def_tx_scale_11b_p0d5 =
+			    (phy_setting[i].data >> 8) & 0xff;
+			init_iqk_cfg.cfg_def_tx_scale_11g =
+			    (phy_setting[i].data >> 16) & 0xff;
+			init_iqk_cfg.cfg_def_tx_scale_11g_p0d5 =
+			    (phy_setting[i].data >> 24) & 0xff;
+			break;
+		}
+	}
+	if (sh->cfg.volt_regulator == SSV6XXX_VOLT_LDO_CONVERT) {
+		dev_info(sh->sc->dev, "Using LDO voltage regulator\n");
+		for (i = 0;
+		     i <
+		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (ssv6200_rf_tbl[i].address == ADR_PMU_2) {
+				ssv6200_rf_tbl[i].data &= 0xFFFFFFFE;
+				ssv6200_rf_tbl[i].data |= 0x00000000;
+			}
+		}
+	} else if (sh->cfg.volt_regulator == SSV6XXX_VOLT_DCDC_CONVERT) {
+		dev_info(sh->sc->dev, "Using DCDC buck regulator\n");
+		for (i = 0;
+		     i <
+		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (ssv6200_rf_tbl[i].address == ADR_PMU_2) {
+				ssv6200_rf_tbl[i].data &= 0xFFFFFFFE;
+				ssv6200_rf_tbl[i].data |= 0x00000001;
+			}
+		}
+	} else {
+		dev_warn(sh->sc->dev, "Illegal regulator setting, using DCDC buck as default\n");
+	}
+	while (ssv_cfg.configuration[x][0]) {
+		for (i = 0;
+		     i <
+		     sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (ssv6200_rf_tbl[i].address ==
+			    ssv_cfg.configuration[x][0]) {
+				ssv6200_rf_tbl[i].data =
+				    ssv_cfg.configuration[x][1];
+				break;
+			}
+		}
+		for (i = 0;
+		     i < sizeof(phy_setting) / sizeof(struct ssv6xxx_dev_table);
+		     i++) {
+			if (phy_setting[i].address ==
+			    ssv_cfg.configuration[x][0]) {
+				phy_setting[i].data =
+				    ssv_cfg.configuration[x][1];
+				break;
+			}
+		}
+		x++;
+	};
+	if (ret == 0)
+		ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_rf_tbl);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1, 0x00000000);
+	SMAC_REG_READ(sh, ADR_PHY_EN_0, &regval);
+	if (regval & (1 << RG_RF_BB_CLK_SEL_SFT)) {
+		dev_dbg(sh->sc->dev, "already do clock switch\n");
+	} else {
+		dev_dbg(sh->sc->dev, "reset PLL\n");
+		SMAC_REG_READ(sh, ADR_DPLL_CP_PFD_REGISTER, &regval);
+		regval |=
+		    ((1 << RG_DP_BBPLL_PD_SFT) |
+		     (1 << RG_DP_BBPLL_SDM_EDGE_SFT));
+		SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval);
+		regval &=
+		    ~((1 << RG_DP_BBPLL_PD_SFT) |
+		      (1 << RG_DP_BBPLL_SDM_EDGE_SFT));
+		SMAC_REG_WRITE(sh, ADR_DPLL_CP_PFD_REGISTER, regval);
+		mdelay(10);
+	}
+	if (ret == 0)
+		ret = SSV6XXX_SET_HW_TABLE(sh, ssv6200_phy_tbl);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xEAAAAAAA);
+	SMAC_REG_READ(sh, ADR_TRX_DUMMY_REGISTER, &regval);
+	if (regval != 0xEAAAAAAA) {
+		dev_warn(sh->sc->dev, "Unexpected register value\n");
+		WARN_ON(1);
+	}
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_PAD53, 0x21);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_PAD54, 0x3000);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_PIN_SEL_0, 0x4000);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, 0xc0000304, 0x01);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, 0xc0000308, 0x01);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_CLOCK_SELECTION, 0x3);
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_TRX_DUMMY_REGISTER, 0xAAAAAAAA);
+	if ((ret = ssv6xxx_set_channel(sh->sc, sh->cfg.def_chan)))
+		return ret;
+	if (ret == 0)
+		ret = SMAC_REG_WRITE(sh, ADR_PHY_EN_1,
+				     (RG_PHYRX_MD_EN_MSK | RG_PHYTX_MD_EN_MSK |
+				      RG_PHY11GN_MD_EN_MSK | RG_PHY11B_MD_EN_MSK
+				      | RG_PHYRXFIFO_MD_EN_MSK |
+				      RG_PHYTXFIFO_MD_EN_MSK |
+				      RG_PHY11BGN_MD_EN_MSK));
+	return ret;
+}
+
+static void ssv6xxx_check_mac2(struct ssv_hw *sh)
+{
+	const u8 addr_mask[6] = { 0xfd, 0xff, 0xff, 0xff, 0xff, 0xfc };
+	u8 i;
+	bool invalid = false;
+	for (i = 0; i < 6; i++) {
+		if ((ssv_cfg.maddr[0][i] & addr_mask[i]) !=
+		    (ssv_cfg.maddr[1][i] & addr_mask[i])) {
+			invalid = true;
+			dev_dbg(sh->sc->dev, " i %d , mac1[i] %x, mac2[i] %x, mask %x \n", i,
+			       ssv_cfg.maddr[0][i], ssv_cfg.maddr[1][i],
+			       addr_mask[i]);
+			break;
+		}
+	}
+	if (invalid) {
+		memcpy(&ssv_cfg.maddr[1][0], &ssv_cfg.maddr[0][0], 6);
+		ssv_cfg.maddr[1][5] ^= 0x01;
+		if (ssv_cfg.maddr[1][5] < ssv_cfg.maddr[0][5]) {
+			u8 temp;
+			temp = ssv_cfg.maddr[0][5];
+			ssv_cfg.maddr[0][5] = ssv_cfg.maddr[1][5];
+			ssv_cfg.maddr[1][5] = temp;
+			sh->cfg.maddr[0][5] = ssv_cfg.maddr[0][5];
+		}
+		dev_warn(sh->sc->dev, "MAC 2 address invalid!!\n");
+		dev_warn(sh->sc->dev, "After modification, MAC1 %pM, MAC2 %pM\n",
+		       ssv_cfg.maddr[0], ssv_cfg.maddr[1]);
+	}
+}
+
+static int ssv6xxx_read_configuration(struct ssv_hw *sh)
+{
+	extern u32 sdio_sr_bhvr;
+	if (is_valid_ether_addr(&ssv_cfg.maddr[0][0]))
+		memcpy(&sh->cfg.maddr[0][0], &ssv_cfg.maddr[0][0], ETH_ALEN);
+	if (is_valid_ether_addr(&ssv_cfg.maddr[1][0])) {
+		ssv6xxx_check_mac2(sh);
+		memcpy(&sh->cfg.maddr[1][0], &ssv_cfg.maddr[1][0], ETH_ALEN);
+	}
+	if (ssv_cfg.hw_caps)
+		sh->cfg.hw_caps = ssv_cfg.hw_caps;
+	else
+		sh->cfg.hw_caps = SSV6200_HW_CAP_HT |
+		    SSV6200_HW_CAP_2GHZ |
+		    SSV6200_HW_CAP_SECURITY |
+		    SSV6200_HW_CAP_P2P |
+		    SSV6200_HT_CAP_SGI_20 |
+		    SSV6200_HW_CAP_AMPDU_RX |
+		    SSV6200_HW_CAP_AMPDU_TX | SSV6200_HW_CAP_AP;
+	if (ssv_cfg.def_chan)
+		sh->cfg.def_chan = ssv_cfg.def_chan;
+	else
+		sh->cfg.def_chan = 6;
+	sh->cfg.use_wpa2_only = ssv_cfg.use_wpa2_only;
+	if (ssv_cfg.crystal_type == 26)
+		sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_26M;
+	else if (ssv_cfg.crystal_type == 40)
+		sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_40M;
+	else if (ssv_cfg.crystal_type == 24)
+		sh->cfg.crystal_type = SSV6XXX_IQK_CFG_XTAL_24M;
+	else {
+		dev_warn(sh->sc->dev, "Please redefine xtal_clock(wifi.cfg)!!\n");
+		WARN_ON(1);
+		return 1;
+	}
+	if (ssv_cfg.volt_regulator < 2)
+		sh->cfg.volt_regulator = ssv_cfg.volt_regulator;
+	else {
+		dev_warn(sh->sc->dev, "Please redefine volt_regulator(wifi.cfg)!!\n");
+		WARN_ON(1);
+		return 1;
+	}
+	sh->cfg.wifi_tx_gain_level_gn = ssv_cfg.wifi_tx_gain_level_gn;
+	sh->cfg.wifi_tx_gain_level_b = ssv_cfg.wifi_tx_gain_level_b;
+	sh->cfg.rssi_ctl = ssv_cfg.rssi_ctl;
+	sh->cfg.sr_bhvr = ssv_cfg.sr_bhvr;
+	sdio_sr_bhvr = ssv_cfg.sr_bhvr;
+	sh->cfg.force_chip_identity = ssv_cfg.force_chip_identity;
+	strncpy(sh->cfg.firmware_path, ssv_cfg.firmware_path,
+		sizeof(sh->cfg.firmware_path) - 1);
+	strncpy(sh->cfg.flash_bin_path, ssv_cfg.flash_bin_path,
+		sizeof(sh->cfg.flash_bin_path) - 1);
+	strncpy(sh->cfg.mac_address_path, ssv_cfg.mac_address_path,
+		sizeof(sh->cfg.mac_address_path) - 1);
+	strncpy(sh->cfg.mac_output_path, ssv_cfg.mac_output_path,
+		sizeof(sh->cfg.mac_output_path) - 1);
+	sh->cfg.ignore_efuse_mac = ssv_cfg.ignore_efuse_mac;
+	sh->cfg.mac_address_mode = ssv_cfg.mac_address_mode;
+	return 0;
+}
+
+static int ssv6xxx_read_hw_info(struct ssv_softc *sc)
+{
+	struct ssv_hw *sh;
+	sh = kzalloc(sizeof(struct ssv_hw), GFP_KERNEL);
+	if (sh == NULL)
+		return -ENOMEM;
+	memset((void *)sh, 0, sizeof(struct ssv_hw));
+	sc->sh = sh;
+	sh->sc = sc;
+	sh->priv = sc->dev->platform_data;
+	if (ssv6xxx_read_configuration(sh))
+		return -ENOMEM;
+	sh->hci.dev = sc->dev;
+	sh->hci.hci_ops = NULL;
+	sh->hci.hci_rx_cb = ssv6200_rx;
+	sh->hci.rx_cb_args = (void *)sc;
+	sh->hci.hci_tx_cb = ssv6xxx_tx_cb;
+	sh->hci.tx_cb_args = (void *)sc;
+	sh->hci.hci_skb_update_cb = ssv6xxx_tx_rate_update;
+	sh->hci.skb_update_args = (void *)sc;
+	sh->hci.hci_tx_flow_ctrl_cb = ssv6200_tx_flow_control;
+	sh->hci.tx_fctrl_cb_args = (void *)sc;
+	sh->hci.hci_tx_q_empty_cb = ssv6xxx_tx_q_empty_cb;
+	sh->hci.tx_q_empty_args = (void *)sc;
+	sh->hci.if_ops = sh->priv->ops;
+	sh->hci.hci_tx_buf_free_cb = ssv6xxx_txbuf_free_skb;
+	sh->hci.tx_buf_free_args = (void *)sc;
+	return 0;
+}
+
+static int ssv6xxx_init_device(struct ssv_softc *sc, const char *name)
+{
+	struct ieee80211_hw *hw = sc->hw;
+	struct ssv_hw *sh;
+	int error = 0;
+	BUG_ON(!sc->dev->platform_data);
+	if ((error = ssv6xxx_read_hw_info(sc)) != 0) {
+		return error;
+	}
+	sh = sc->sh;
+	if (sh->cfg.hw_caps == 0)
+		return -1;
+	ssv6xxx_hci_register(&sh->hci);
+	efuse_read_all_map(sh);
+	if ((error = ssv6xxx_init_softc(sc)) != 0) {
+		ssv6xxx_deinit_softc(sc);
+		ssv6xxx_hci_deregister();
+		kfree(sh);
+		return error;
+	}
+	if ((error = ssv6xxx_init_hw(sc->sh)) != 0) {
+		ssv6xxx_deinit_hw(sc);
+		ssv6xxx_deinit_softc(sc);
+		ssv6xxx_hci_deregister();
+		kfree(sh);
+		return error;
+	}
+	if ((error = ieee80211_register_hw(hw)) != 0) {
+		dev_err(sc->dev, "Failed to register ieee80211 wireless device. ret=%d.\n", error);
+		ssv6xxx_deinit_hw(sc);
+		ssv6xxx_deinit_softc(sc);
+		ssv6xxx_hci_deregister();
+		kfree(sh);
+		return error;
+	}
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	ssv6xxx_init_debugfs(sc, name);
+#endif
+	return 0;
+}
+
+static void ssv6xxx_deinit_device(struct ssv_softc *sc)
+{
+	dev_dbg(sc->dev, "%s(): \n", __FUNCTION__);
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	ssv6xxx_deinit_debugfs(sc);
+#endif
+	ssv6xxx_rf_disable(sc->sh);
+	ieee80211_unregister_hw(sc->hw);
+	ssv6xxx_deinit_hw(sc);
+	ssv6xxx_deinit_softc(sc);
+	ssv6xxx_hci_deregister();
+	kfree(sc->sh);
+}
+
+extern struct ieee80211_ops ssv6200_ops;
+int ssv6xxx_dev_probe(struct platform_device *pdev)
+{
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+	extern struct ssv_softc *ssv_dbg_sc;
+#endif
+#ifdef CONFIG_SSV_SMARTLINK
+	extern struct ssv_softc *ssv_smartlink_sc;
+#endif
+	struct ssv_softc *softc;
+	struct ieee80211_hw *hw;
+	int ret;
+	if (!pdev->dev.platform_data) {
+		dev_err(&pdev->dev, "no platform data specified!\n");
+		return -EINVAL;
+	}
+	hw = ieee80211_alloc_hw(sizeof(struct ssv_softc), &ssv6200_ops);
+	if (hw == NULL) {
+		dev_err(&pdev->dev, "Could not allocate memory for ieee80211 wireless device\n");
+		return -ENOMEM;
+	}
+	SET_IEEE80211_DEV(hw, &pdev->dev);
+	dev_set_drvdata(&pdev->dev, hw);
+	memset((void *)hw->priv, 0, sizeof(struct ssv_softc));
+	softc = hw->priv;
+	softc->hw = hw;
+	softc->dev = &pdev->dev;
+	//SET_IEEE80211_PERM_ADDR(hw, (const u8 *)&softc->sh->maddr[0]);
+	ret = ssv6xxx_init_device(softc, pdev->name);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to initialize device\n");
+		ieee80211_free_hw(hw);
+		return ret;
+	}
+#ifdef CONFIG_SSV6200_CLI_ENABLE
+	ssv_dbg_sc = softc;
+#endif
+#ifdef CONFIG_SSV_SMARTLINK
+	ssv_smartlink_sc = softc;
+#endif
+	wiphy_info(hw->wiphy, "%s\n", "SSV6200 of South Silicon Valley");
+	return 0;
+}
+
+EXPORT_SYMBOL(ssv6xxx_dev_probe);
+int ssv6xxx_dev_remove(struct platform_device *pdev)
+{
+	struct ieee80211_hw *hw = dev_get_drvdata(&pdev->dev);
+	struct ssv_softc *softc = hw->priv;
+	dev_dbg(&pdev->dev, "ssv6xxx_dev_remove(): pdev=%p, hw=%p\n", pdev, hw);
+	ssv6xxx_deinit_device(softc);
+	dev_dbg(&pdev->dev, "ieee80211_free_hw(): \n");
+	ieee80211_free_hw(hw);
+	dev_info(&pdev->dev, "driver unloaded\n");
+	return 0;
+}
+
+EXPORT_SYMBOL(ssv6xxx_dev_remove);
+static const struct platform_device_id ssv6xxx_id_table[] = {
+	{
+	 .name = "ssv6200",
+	 .driver_data = 0x00,
+	 },
+	{},
+};
+
+MODULE_DEVICE_TABLE(platform, ssv6xxx_id_table);
+static struct platform_driver ssv6xxx_driver = {
+	.probe = ssv6xxx_dev_probe,
+	.remove = ssv6xxx_dev_remove,
+	.id_table = ssv6xxx_id_table,
+	.driver = {
+		   .name = "SSV WLAN driver",
+		   .owner = THIS_MODULE,
+		   }
+};
+
+int ssv6xxx_init(void)
+{
+	extern void *ssv_dbg_phy_table;
+	extern u32 ssv_dbg_phy_len;
+	extern void *ssv_dbg_rf_table;
+	extern u32 ssv_dbg_rf_len;
+	ssv_dbg_phy_table = (void *)ssv6200_phy_tbl;
+	ssv_dbg_phy_len =
+	    sizeof(ssv6200_phy_tbl) / sizeof(struct ssv6xxx_dev_table);
+	ssv_dbg_rf_table = (void *)ssv6200_rf_tbl;
+	ssv_dbg_rf_len =
+	    sizeof(ssv6200_rf_tbl) / sizeof(struct ssv6xxx_dev_table);
+	return platform_driver_register(&ssv6xxx_driver);
+}
+
+void ssv6xxx_exit(void)
+{
+	platform_driver_unregister(&ssv6xxx_driver);
+}
+
+EXPORT_SYMBOL(ssv6xxx_init);
+EXPORT_SYMBOL(ssv6xxx_exit);
diff --git a/drivers/net/wireless/ssv6051/smac/init.h b/drivers/net/wireless/ssv6051/smac/init.h
new file mode 100644
index 00000000000..97994d00d4d
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/init.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _INIT_H_
+#define _INIT_H_
+int ssv6xxx_init_mac(struct ssv_hw *sh);
+int ssv6xxx_do_iq_calib(struct ssv_hw *sh, struct ssv6xxx_iqk_cfg *p_cfg);
+void ssv6xxx_deinit_mac(struct ssv_softc *sc);
+void ssv6xxx_restart_hw(struct ssv_softc *sc);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/lib.c b/drivers/net/wireless/ssv6051/smac/lib.c
new file mode 100644
index 00000000000..ccf0974b0f2
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/lib.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200.h>
+#include "lib.h"
+struct sk_buff *ssv_skb_alloc(s32 len)
+{
+	struct sk_buff *skb;
+	skb = __dev_alloc_skb(len + 128, GFP_KERNEL);
+	if (skb != NULL) {
+		skb_put(skb, 0x20);
+		skb_pull(skb, 0x20);
+	}
+	return skb;
+}
+
+void ssv_skb_free(struct sk_buff *skb)
+{
+	dev_kfree_skb_any(skb);
+}
diff --git a/drivers/net/wireless/ssv6051/smac/lib.h b/drivers/net/wireless/ssv6051/smac/lib.h
new file mode 100644
index 00000000000..266cf7afac9
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/lib.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _LIB_H_
+#define _LIB_H_
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+struct sk_buff *ssv_skb_alloc(s32 len);
+void ssv_skb_free(struct sk_buff *skb);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/linux_80211.h b/drivers/net/wireless/ssv6051/smac/linux_80211.h
new file mode 100644
index 00000000000..e268808e3c9
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/linux_80211.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _LINUX_80211_H_
+#define _LINUX_80211_H_
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0)
+#define INDEX_80211_BAND_2GHZ IEEE80211_BAND_2GHZ
+#else
+#define INDEX_80211_BAND_2GHZ NL80211_BAND_2GHZ
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/p2p.c b/drivers/net/wireless/ssv6051/smac/p2p.c
new file mode 100644
index 00000000000..60fd8effd6e
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/p2p.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200.h>
+#include <linux/types.h>
+#include <linux/nl80211.h>
+#include <net/mac80211.h>
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <linux/kthread.h>
+#include <net/mac80211.h>
+#include <ssv6200.h>
+#include "p2p.h"
+#include "dev.h"
+#include "lib.h"
+#ifdef CONFIG_P2P_NOA
+#define P2P_IE_VENDOR_TYPE 0x506f9a09
+#define P2P_NOA_DETECT_INTERVAL (5 * HZ)
+#ifndef MAC2STR
+#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
+#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
+#define COMPACT_MACSTR "%02x%02x%02x%02x%02x%02x"
+#endif
+void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
+			  struct ssv6xxx_p2p_noa_param *p2p_noa_param);
+static inline u32 WPA_GET_BE32(const u8 * a)
+{
+	return (a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3];
+}
+
+static inline u16 WPA_GET_LE16(const u8 * a)
+{
+	return (a[1] << 8) | a[0];
+}
+
+static inline u32 WPA_GET_LE32(const u8 * a)
+{
+	return (a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0];
+}
+
+#define IEEE80211_HDRLEN 24
+enum p2p_attr_id {
+	P2P_ATTR_STATUS = 0,
+	P2P_ATTR_MINOR_REASON_CODE = 1,
+	P2P_ATTR_CAPABILITY = 2,
+	P2P_ATTR_DEVICE_ID = 3,
+	P2P_ATTR_GROUP_OWNER_INTENT = 4,
+	P2P_ATTR_CONFIGURATION_TIMEOUT = 5,
+	P2P_ATTR_LISTEN_CHANNEL = 6,
+	P2P_ATTR_GROUP_BSSID = 7,
+	P2P_ATTR_EXT_LISTEN_TIMING = 8,
+	P2P_ATTR_INTENDED_INTERFACE_ADDR = 9,
+	P2P_ATTR_MANAGEABILITY = 10,
+	P2P_ATTR_CHANNEL_LIST = 11,
+	P2P_ATTR_NOTICE_OF_ABSENCE = 12,
+	P2P_ATTR_DEVICE_INFO = 13,
+	P2P_ATTR_GROUP_INFO = 14,
+	P2P_ATTR_GROUP_ID = 15,
+	P2P_ATTR_INTERFACE = 16,
+	P2P_ATTR_OPERATING_CHANNEL = 17,
+	P2P_ATTR_INVITATION_FLAGS = 18,
+	P2P_ATTR_OOB_GO_NEG_CHANNEL = 19,
+	P2P_ATTR_VENDOR_SPECIFIC = 221
+};
+struct ssv6xxx_p2p_noa_attribute {
+	u8 index;
+	u16 ctwindows_oppps;
+	struct ssv6xxx_p2p_noa_param noa_param;
+};
+extern void _ssv6xxx_hexdump(const char *title, const u8 * buf, size_t len);
+bool p2p_find_noa(const u8 * ies, struct ssv6xxx_p2p_noa_attribute *noa_attr)
+{
+	const u8 *end, *pos, *ie;
+	u32 len;
+	len = ie[1] - 4;
+	pos = ie + 6;
+	end = pos + len;
+	while (pos < end) {
+		u16 attr_len;
+		if (pos + 2 >= end) {
+			return false;
+		}
+		attr_len = WPA_GET_LE16(pos + 1);
+		if (pos + 3 + attr_len > end) {
+			return false;
+		}
+		if (pos[0] != P2P_ATTR_NOTICE_OF_ABSENCE) {
+			pos += 3 + attr_len;
+			continue;
+		}
+		if (attr_len < 15) {
+			printk
+			    ("*********************NOA descriptor does not exist len[%d]\n",
+			     attr_len);
+			break;
+		}
+		if (attr_len > 15)
+			printk("More than one NOA descriptor\n");
+		noa_attr->index = pos[3];
+		noa_attr->ctwindows_oppps = pos[4];
+		noa_attr->noa_param.count = pos[5];
+		noa_attr->noa_param.duration = WPA_GET_LE32(&pos[6]);
+		noa_attr->noa_param.interval = WPA_GET_LE32(&pos[10]);
+		noa_attr->noa_param.start_time = WPA_GET_LE32(&pos[14]);
+		return true;
+	}
+	return false;
+}
+
+bool p2p_get_attribute_noa(const u8 * ies, u32 oui_type,
+			   struct ssv6xxx_p2p_noa_attribute *noa_attr)
+{
+	const u8 *end, *pos, *ie;
+	u32 len;
+	pos = ies;
+	end = ies + ies_len;
+	ie = NULL;
+	while (pos + 1 < end) {
+		if (pos + 2 + pos[1] > end)
+			return false;
+		if (pos[0] == WLAN_EID_VENDOR_SPECIFIC && pos[1] >= 4 &&
+		    WPA_GET_BE32(&pos[2]) == oui_type) {
+			ie = pos;
+			if (p2p_find_noa(ie, 0, noa_attr) == true)
+				return true;
+		}
+		pos += 2 + pos[1];
+	}
+	return false;
+}
+
+void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb)
+{
+	struct cfg_host_event *host_event;
+	struct ssv62xx_noa_evt *noa_evt;
+	host_event = (struct cfg_host_event *)skb->data;
+	noa_evt = (struct ssv62xx_noa_evt *)&host_event->dat[0];
+	switch (noa_evt->evt_id) {
+	case SSV6XXX_NOA_START:
+		sc->p2p_noa.active_noa_vif |= (1 << noa_evt->vif);
+		printk("SSV6XXX_NOA_START===>[%08x]\n",
+		       sc->p2p_noa.active_noa_vif);
+		break;
+	case SSV6XXX_NOA_STOP:
+		sc->p2p_noa.active_noa_vif &= ~(1 << noa_evt->vif);
+		printk("SSV6XXX_NOA_STOP===>[%08x]\n",
+		       sc->p2p_noa.active_noa_vif);
+		break;
+	default:
+		printk("--------->NOA wrong command<---------\n");
+		break;
+	}
+}
+
+void ssv6xxx_noa_reset(struct ssv_softc *sc)
+{
+	unsigned long flags;
+	printk("Reset NOA param...\n");
+	spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
+	memset(&sc->p2p_noa.noa_detect, 0,
+	       sizeof(struct ssv_p2p_noa_detect) * SSV_NUM_VIF);
+	sc->p2p_noa.active_noa_vif = 0;
+	sc->p2p_noa.monitor_noa_vif = 0;
+	spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
+}
+
+void ssv6xxx_noa_host_stop_noa(struct ssv_softc *sc, u8 vif_id)
+{
+	struct ssv6xxx_p2p_noa_attribute noa_attr;
+	if (sc->p2p_noa.noa_detect[vif_id].p2p_noa_index >= 0) {
+		sc->p2p_noa.noa_detect[vif_id].p2p_noa_index = -1;
+		sc->p2p_noa.active_noa_vif &= ~(1 << vif_id);
+		memset(&sc->p2p_noa.noa_detect[vif_id].noa_param_cmd, 0,
+		       sizeof(struct ssv6xxx_p2p_noa_param));
+		printk("->remove NOA operating vif[%d]\n", vif_id);
+		noa_attr.noa_param.enable = 0;
+		noa_attr.noa_param.vif_id = vif_id;
+		ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param);
+	}
+}
+
+void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr *hdr,
+			u32 len)
+{
+	int i;
+	unsigned long flags;
+	struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
+	struct ssv6xxx_p2p_noa_attribute noa_attr;
+	spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
+	if (sc->p2p_noa.monitor_noa_vif == 0)
+		goto out;
+	for (i = 0; i < SSV_NUM_VIF; i++) {
+		if (sc->p2p_noa.noa_detect[i].noa_addr == NULL)
+			continue;
+		if (memcmp(mgmt->bssid, sc->p2p_noa.noa_detect[i].noa_addr, 6)
+		    != 0)
+			continue;
+		if (sc->p2p_noa.active_noa_vif &&
+		    ((sc->p2p_noa.active_noa_vif & 1 << i) == 0))
+			continue;
+		sc->p2p_noa.noa_detect[i].last_rx = jiffies;
+		if (p2p_get_attribute_noa((const u8 *)mgmt->u.beacon.variable,
+					  len - (IEEE80211_HDRLEN +
+						 sizeof(mgmt->u.beacon)),
+					  P2P_IE_VENDOR_TYPE,
+					  &noa_attr) == false) {
+			continue;
+		}
+		if (sc->p2p_noa.noa_detect[i].p2p_noa_index == noa_attr.index) {
+			goto out;
+		}
+		printk(MACSTR "->set NOA element\n", MAC2STR(mgmt->bssid));
+		sc->p2p_noa.active_noa_vif |= (1 << i);
+		sc->p2p_noa.noa_detect[i].p2p_noa_index = noa_attr.index;
+		memcpy(&sc->p2p_noa.noa_detect[i].noa_param_cmd,
+		       &noa_attr.noa_param,
+		       sizeof(struct ssv6xxx_p2p_noa_param));
+		noa_attr.noa_param.enable = 1;
+		noa_attr.noa_param.vif_id = i;
+		memcpy(noa_attr.noa_param.addr, hdr->addr2, 6);
+		ssv6xxx_send_noa_cmd(sc, &noa_attr.noa_param);
+	}
+ out:
+	spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
+}
+
+void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc,
+				enum ssv6xxx_noa_conf conf, u8 vif_idx)
+{
+	unsigned long flags;
+	if (sc->vif_info[vif_idx].vif->type != NL80211_IFTYPE_STATION ||
+	    sc->vif_info[vif_idx].vif->p2p != true)
+		return;
+	spin_lock_irqsave(&sc->p2p_noa.p2p_config_lock, flags);
+	printk("====>[NOA]ssv6xxx_noa_hdl_bss_change conf[%d] vif_idx[%d]\n",
+	       conf, vif_idx);
+	switch (conf) {
+	case MONITOR_NOA_CONF_ADD:
+		memset(&sc->p2p_noa.noa_detect[vif_idx], 0,
+		       sizeof(struct ssv_p2p_noa_detect));
+		sc->p2p_noa.noa_detect[vif_idx].noa_addr =
+		    sc->vif_info[vif_idx].vif->bss_conf.bssid;
+		sc->p2p_noa.noa_detect[vif_idx].p2p_noa_index = -1;
+		sc->p2p_noa.noa_detect[vif_idx].last_rx = jiffies;
+		sc->p2p_noa.monitor_noa_vif |= 1 << vif_idx;
+		break;
+	case MONITOR_NOA_CONF_REMOVE:
+		sc->p2p_noa.monitor_noa_vif &= ~(1 << vif_idx);
+		sc->p2p_noa.noa_detect[vif_idx].noa_addr = NULL;
+		ssv6xxx_noa_host_stop_noa(sc, vif_idx);
+		break;
+	default:
+		break;
+	}
+	spin_unlock_irqrestore(&sc->p2p_noa.p2p_config_lock, flags);
+}
+
+void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
+			  struct ssv6xxx_p2p_noa_param *p2p_noa_param)
+{
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	int retry_cnt = 5;
+	skb =
+	    ssv_skb_alloc(HOST_CMD_HDR_LEN +
+			  sizeof(struct ssv6xxx_p2p_noa_param));
+	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param);
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_SET_NOA;
+	host_cmd->len = skb->data_len;
+	memcpy(host_cmd->dat32, p2p_noa_param,
+	       sizeof(struct ssv6xxx_p2p_noa_param));
+	printk
+	    ("Noa cmd NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]vif[%d]\n\n",
+	     p2p_noa_param->enable, p2p_noa_param->interval,
+	     p2p_noa_param->duration, p2p_noa_param->start_time,
+	     p2p_noa_param->count, p2p_noa_param->addr[0],
+	     p2p_noa_param->addr[1], p2p_noa_param->addr[2],
+	     p2p_noa_param->addr[3], p2p_noa_param->addr[4],
+	     p2p_noa_param->addr[5], p2p_noa_param->vif_id);
+	while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
+		printk(KERN_INFO "NOA cmd retry=%d!!\n", retry_cnt);
+		retry_cnt--;
+	}
+	ssv_skb_free(skb);
+}
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/p2p.h b/drivers/net/wireless/ssv6051/smac/p2p.h
new file mode 100644
index 00000000000..a5bb99c61bb
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/p2p.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _P2P_H_
+#define _P2P_H_
+#include <net/mac80211.h>
+#include <ssv6200.h>
+#include "drv_comm.h"
+#ifdef CONFIG_P2P_NOA
+#define P2P_MAX_NOA_INTERFACE 1
+struct ssv_p2p_noa_detect {
+	const u8 *noa_addr;
+	s16 p2p_noa_index;
+	unsigned long last_rx;
+	struct ssv6xxx_p2p_noa_param noa_param_cmd;
+};
+struct ssv_p2p_noa {
+	spinlock_t p2p_config_lock;
+	struct ssv_p2p_noa_detect noa_detect[SSV_NUM_VIF];
+	u8 active_noa_vif;
+	u8 monitor_noa_vif;
+};
+enum ssv_cmd_state {
+	SSC_CMD_STATE_IDLE,
+	SSC_CMD_STATE_WAIT_RSP,
+};
+struct ssv_cmd_Info {
+	struct sk_buff_head cmd_que;
+	struct sk_buff_head evt_que;
+	enum ssv_cmd_state state;
+};
+enum ssv6xxx_noa_conf {
+	MONITOR_NOA_CONF_ADD,
+	MONITOR_NOA_CONF_REMOVE,
+};
+struct ssv_softc;
+void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb);
+void ssv6xxx_noa_hdl_bss_change(struct ssv_softc *sc,
+				enum ssv6xxx_noa_conf conf, u8 vif_idx);
+void ssv6xxx_process_noa_event(struct ssv_softc *sc, struct sk_buff *skb);
+void ssv6xxx_noa_detect(struct ssv_softc *sc, struct ieee80211_hdr *hdr,
+			u32 len);
+void ssv6xxx_noa_reset(struct ssv_softc *sc);
+#endif
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/sar.c b/drivers/net/wireless/ssv6051/smac/sar.c
new file mode 100644
index 00000000000..44a47a5c7a0
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/sar.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200_reg.h>
+#include <ssv6200_aux.h>
+#include <linux/fs.h>
+#include "dev.h"
+#include "sar.h"
+
+WIFI_FLASH_CCFG flash_cfg = {
+	//16bytes
+	0x6051, 0x3009, 0x20170519, 0x1, 0x0, 0x0,
+	{			//16bytes
+	 {0x47c000, 0x47c000, 0x47c000, 0x9, 0x1d, 0x0},
+	 //16bytes
+	 {0x79807980, 0x79807980, 0x79807980, 0x9, 0x1d, 0x0}
+	 }
+};
+
+WIFI_FLASH_CCFG *pflash_cfg;
+
+struct t_sar_info sar_info[] = {
+	{SAR_LVL_INVALID, 0x0047c000, NULL},
+	{SAR_LVL_INVALID, 0x79807980, NULL}
+};
+
+int sar_info_size = sizeof(sar_info) / sizeof(sar_info[0]);
+
+static u8 get_sar_lvl(u32 sar)
+{
+	static u32 prev_sar = 0;
+	int i;
+	u8 changed = 0x0;
+
+	if (sar == prev_sar)
+		return changed;
+
+	pr_debug("[thermal_sar] %d\n", (int)sar);
+
+	for (i = 0; i < sar_info_size; i++) {
+		if (sar_info[i].lvl == SAR_LVL_INVALID) {	//if driver loaded under LT/HT env, it would cause wrong settings at this time.
+			sar_info[i].lvl = SAR_LVL_RT;
+			sar_info[i].value = sar_info[i].p->rt;
+			changed |= BIT(i);
+		} else if (sar_info[i].lvl == SAR_LVL_RT) {
+			if (sar < prev_sar) {
+				if (sar <= (u32) (sar_info[i].p->lt_ts - 2)) {	//we need check if (g_tt_lt - 1) < SAR_MIN
+					sar_info[i].lvl = SAR_LVL_LT;
+					sar_info[i].value = sar_info[i].p->lt;
+					changed |= BIT(i);
+				}
+			} else if (sar > prev_sar) {
+				if (sar >= (u32) (sar_info[i].p->ht_ts + 2)) {	//we need check if (g_tt_lt + 1) > SAR_MAX
+					sar_info[i].lvl = SAR_LVL_HT;
+					sar_info[i].value = sar_info[i].p->ht;
+					changed |= BIT(i);
+				}
+			}
+		} else if (sar_info[i].lvl == SAR_LVL_LT) {
+			if (sar >= (u32) (sar_info[i].p->lt_ts + 2)) {
+				sar_info[i].lvl = SAR_LVL_RT;
+				sar_info[i].value = sar_info[i].p->rt;
+				changed |= BIT(i);
+			}
+		} else if (sar_info[i].lvl == SAR_LVL_HT) {
+			if (sar <= (u32) (sar_info[i].p->ht_ts - 2)) {
+				sar_info[i].lvl = SAR_LVL_RT;
+				sar_info[i].value = sar_info[i].p->rt;
+				changed |= BIT(i);
+			}
+		}
+	}
+	if (changed) {
+		pr_debug("changed: 0x%x\n", changed);
+	}
+	prev_sar = sar;
+	return changed;
+}
+
+void sar_monitor(u32 curr_sar, struct ssv_softc *sc)
+{
+	//static u32 prev_sar_lvl = SAR_LVL_INVALID; //sar = 0, temparature < -25C
+	u8 changed;
+	changed = get_sar_lvl(curr_sar);
+
+	if (changed & BIT(SAR_TXGAIN_INDEX)) {
+		dev_dbg(sc->dev, "TXGAIN: 0x%08x\n", sar_info[SAR_TXGAIN_INDEX].value);
+		SMAC_REG_WRITE(sc->sh, ADR_TX_GAIN_FACTOR,
+			       sar_info[SAR_TXGAIN_INDEX].value);
+	}
+	if (changed & BIT(SAR_XTAL_INDEX)) {
+		dev_dbg(sc->dev, "XTAL: 0x%08x\n", sar_info[SAR_XTAL_INDEX].value);
+		SMAC_REG_WRITE(sc->sh, ADR_SYN_KVCO_XO_FINE_TUNE_CBANK,
+			       sar_info[SAR_XTAL_INDEX].value);
+	}
+}
+
+/*
+    SET_RG_SARADC_THERMAL(1);     //ce010030[26]
+    SET_RG_EN_SARADC(1);          //ce010030[30]
+    while(!GET_SAR_ADC_FSM_RDY);  //ce010094[23]
+    sar_code = GET_RG_SARADC_BIT; //ce010094[21:16]
+    SET_RG_SARADC_THERMAL(0);
+    SET_RG_EN_SARADC(0);
+*/
+void thermal_monitor(struct work_struct *work)
+{
+	struct ssv_softc *sc =
+	    container_of(work, struct ssv_softc, thermal_monitor_work.work);
+	u32 curr_sar;
+
+	u32 temp;
+	if (sc->ps_status == PWRSV_PREPARE) {
+		dev_dbg(sc->dev, "sar PWRSV_PREPARE\n");
+		return;
+	}
+
+	mutex_lock(&sc->mutex);
+	SMAC_REG_READ(sc->sh, ADR_RX_11B_CCA_1, &temp);
+	if (temp == RX_11B_CCA_IN_SCAN) {
+		dev_dbg(sc->dev, "in scan\n");
+		mutex_unlock(&sc->mutex);
+		queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
+				   THERMAL_MONITOR_TIME);
+		return;
+	}
+	SMAC_REG_READ(sc->sh, ADR_RX_ADC_REGISTER, &temp);
+	//printk("ori %08x:%08x\n", ADR_RX_ADC_REGISTER, temp);
+	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER,
+			  (1 << RG_SARADC_THERMAL_SFT), RG_SARADC_THERMAL_MSK);
+	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, (1 << RG_EN_SARADC_SFT),
+			  RG_EN_SARADC_MSK);
+
+	do {
+		msleep(1);
+		SMAC_REG_READ(sc->sh, ADR_READ_ONLY_FLAGS_1, &temp);
+	} while (((temp & SAR_ADC_FSM_RDY_MSK) >> SAR_ADC_FSM_RDY_SFT) != 1);
+	//printk("SAR_ADC_FSM_RDY_STAT %d\n", (temp & SAR_ADC_FSM_RDY_MSK) >> SAR_ADC_FSM_RDY_SFT);
+	curr_sar = (temp & RG_SARADC_BIT_MSK) >> RG_SARADC_BIT_SFT;
+	SMAC_REG_READ(sc->sh, ADR_RX_ADC_REGISTER, &temp);
+
+	//printk("new %08x:%08x\n", ADR_RX_ADC_REGISTER, temp);
+
+	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER,
+			  (0 << RG_SARADC_THERMAL_SFT), RG_SARADC_THERMAL_MSK);
+	SMAC_REG_SET_BITS(sc->sh, ADR_RX_ADC_REGISTER, (0 << RG_EN_SARADC_SFT),
+			  RG_EN_SARADC_MSK);
+	sar_monitor(curr_sar, sc);
+
+	mutex_unlock(&sc->mutex);
+
+	queue_delayed_work(sc->thermal_wq, &sc->thermal_monitor_work,
+			   THERMAL_MONITOR_TIME);
+}
+
+int get_flash_info(struct ssv_softc *sc)
+{
+	struct file *fp = (struct file *)NULL;
+	int i, ret;
+
+	pflash_cfg = &flash_cfg;
+
+	if (sc->sh->cfg.flash_bin_path[0] != 0x00) {
+		fp = filp_open(sc->sh->cfg.flash_bin_path, O_RDONLY, 0);
+		if (IS_ERR(fp) || fp == NULL) {
+			fp = filp_open(SEC_CFG_BIN_NAME, O_RDONLY, 0);
+		}
+	} else {
+		fp = filp_open(DEFAULT_CFG_BIN_NAME, O_RDONLY, 0);
+		if (IS_ERR(fp) || fp == NULL) {
+			fp = filp_open(SEC_CFG_BIN_NAME, O_RDONLY, 0);
+		}
+	}
+	if (IS_ERR(fp) || fp == NULL) {
+		dev_info(sc->dev, "flash_file %s not found, disable sar\n",
+		       DEFAULT_CFG_BIN_NAME);
+		//WARN_ON(1);
+		ret = 0;
+		return ret;
+	}
+
+	fp->f_op->read(fp, (char *)pflash_cfg, sizeof(flash_cfg), &fp->f_pos);
+
+	filp_close(fp, NULL);
+	ret = 1;
+
+	for (i = 0; i < sar_info_size; i++) {
+		sar_info[i].p = &flash_cfg.sar_rlh[i];
+		dev_dbg(sc->dev, "rt = %x, lt = %x, ht = %x\n", sar_info[i].p->rt,
+		       sar_info[i].p->lt, sar_info[i].p->ht);
+		dev_dbg(sc->dev, "lt_ts = %x, ht_ts = %x\n", sar_info[i].p->lt_ts,
+		       sar_info[i].p->ht_ts);
+	}
+	return ret;
+}
diff --git a/drivers/net/wireless/ssv6051/smac/sar.h b/drivers/net/wireless/ssv6051/smac/sar.h
new file mode 100644
index 00000000000..291d58f236e
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/sar.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _CFG_H_
+#define _CFG_H_
+#include <linux/kthread.h>
+
+#define SAR_XTAL_INDEX     (0)
+#define SAR_TXGAIN_INDEX    (1)
+#define THERMAL_MONITOR_TIME (10 * HZ)
+#define DEFAULT_CFG_BIN_NAME "/lib/firmware/ssv6051_sar.bin"
+#define SEC_CFG_BIN_NAME "/lib/firmware/ssv6xxx_sar.bin"
+enum {
+	SAR_LVL_LT,
+	SAR_LVL_RT,
+	SAR_LVL_HT,
+	SAR_LVL_INVALID
+};
+
+struct flash_thermal_info {
+	u32 rt;
+	u32 lt;
+	u32 ht;
+	u8 lt_ts;
+	u8 ht_ts;
+	u16 reserve;
+};
+typedef struct t_WIFI_FLASH_CCFG {
+	//16bytes
+	u16 chip_id;
+	u16 sid;
+	u32 date;
+	u16 version;
+	u16 reserve_1;
+	u32 reserve_2;
+	//16bytes
+	struct flash_thermal_info sar_rlh[2];
+} WIFI_FLASH_CCFG;
+
+struct t_sar_info {
+	u32 lvl;
+	u32 value;
+	struct flash_thermal_info *p;
+};
+
+void thermal_monitor(struct work_struct *work);
+int get_flash_info(struct ssv_softc *sc);
+void flash_hexdump(void);
+
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/sec.h b/drivers/net/wireless/ssv6051/smac/sec.h
new file mode 100644
index 00000000000..04a0f47c8ce
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/sec.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SEC_H
+#define SEC_H
+#include <linux/types.h>
+#include <linux/ieee80211.h>
+#include <net/mac80211.h>
+#define CCMP_TK_LEN 16
+#define TKIP_KEY_LEN 32
+#define WEP_KEY_LEN 13
+struct ssv_crypto_ops {
+	const char *name;
+	struct list_head list;
+	void *(*init)(int keyidx);
+	void (*deinit)(void *priv);
+	int (*encrypt_mpdu)(struct sk_buff * skb, int hdr_len, void *priv);
+	int (*decrypt_mpdu)(struct sk_buff * skb, int hdr_len, void *priv);
+	int (*encrypt_msdu)(struct sk_buff * skb, int hdr_len, void *priv);
+	int (*decrypt_msdu)(struct sk_buff * skb, int keyidx, int hdr_len,
+			    void *priv);
+	int (*set_tx_pn)(u8 * seq, void *priv);
+	int (*set_key)(void *key, int len, u8 * seq, void *priv);
+	int (*get_key)(void *key, int len, u8 * seq, void *priv);
+	char *(*print_stats)(char *p, void *priv);
+	unsigned long (*get_flags)(void *priv);
+	unsigned long (*set_flags)(unsigned long flags, void *priv);
+	int extra_mpdu_prefix_len, extra_mpdu_postfix_len;
+	int extra_msdu_prefix_len, extra_msdu_postfix_len;
+};
+struct ssv_crypto_data {
+	struct ssv_crypto_ops *ops;
+	void *priv;
+	rwlock_t lock;
+};
+struct ssv_crypto_ops *get_crypto_ccmp_ops(void);
+struct ssv_crypto_ops *get_crypto_tkip_ops(void);
+struct ssv_crypto_ops *get_crypto_wep_ops(void);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/smartlink.c b/drivers/net/wireless/ssv6051/smac/smartlink.c
new file mode 100644
index 00000000000..69e8d5118e0
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/smartlink.c
@@ -0,0 +1,340 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <net/sock.h>
+#include <linux/socket.h>
+#include <linux/net.h>
+#include <asm/types.h>
+#include <linux/netlink.h>
+#include <linux/skbuff.h>
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "lib.h"
+#include "dev.h"
+#define NETLINK_SMARTLINK (31)
+#define MAX_PAYLOAD (2048)
+static struct sock *nl_sk = NULL;
+struct ssv_softc *ssv_smartlink_sc = NULL;
+EXPORT_SYMBOL(ssv_smartlink_sc);
+u32 ssv_smartlink_status = 0;
+static int _ksmartlink_start_smartlink(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+				       u32 * pOutBufLen)
+{
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s\n", __FUNCTION__);
+#endif
+	ssv_smartlink_status = 1;
+	*pOutBufLen = 0;
+	return 0;
+}
+
+int ksmartlink_smartlink_started(void)
+{
+	return ssv_smartlink_status;
+}
+
+EXPORT_SYMBOL(ksmartlink_smartlink_started);
+static int _ksmartlink_stop_smartlink(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+				      u32 * pOutBufLen)
+{
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s\n", __FUNCTION__);
+#endif
+	ssv_smartlink_status = 0;
+	*pOutBufLen = 0;
+	return 0;
+}
+
+static int _ksmartlink_set_channel(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+				   u32 * pOutBufLen)
+{
+	int ret = -10;
+	int ch = (int)(*pInBuf);
+	struct ssv_softc *sc = ssv_smartlink_sc;
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s %d\n", __FUNCTION__, ch);
+#endif
+	if (!sc) {
+		goto out;
+	}
+	mutex_lock(&sc->mutex);
+	ret = ssv6xxx_set_channel(sc, ch);
+	mutex_unlock(&sc->mutex);
+	*pOutBufLen = 0;
+ out:
+	return ret;
+}
+
+static int _ksmartlink_get_channel(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+				   u32 * pOutBufLen)
+{
+	int ret = -10;
+	int ch = 0;
+	struct ssv_softc *sc = ssv_smartlink_sc;
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s\n", __FUNCTION__);
+#endif
+	if (!sc) {
+		goto out;
+	}
+	mutex_lock(&sc->mutex);
+	ret = ssv6xxx_get_channel(sc, &ch);
+	mutex_unlock(&sc->mutex);
+	*pOutBuf = ch;
+	*pOutBufLen = 1;
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s %d\n", __FUNCTION__, ch);
+#endif
+ out:
+	return ret;
+}
+
+static int _ksmartlink_set_promisc(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+				   u32 * pOutBufLen)
+{
+	int ret = -10;
+	int accept = (int)(*pInBuf);
+	struct ssv_softc *sc = ssv_smartlink_sc;
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s %d\n", __FUNCTION__, accept);
+#endif
+	if (!sc) {
+		goto out;
+	}
+	mutex_lock(&sc->mutex);
+	ret = ssv6xxx_set_promisc(sc, accept);
+	mutex_unlock(&sc->mutex);
+	*pOutBufLen = 0;
+ out:
+	return ret;
+}
+
+static int _ksmartlink_get_promisc(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+				   u32 * pOutBufLen)
+{
+	int ret = -10;
+	int accept = (int)(*pInBuf);
+	struct ssv_softc *sc = ssv_smartlink_sc;
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s\n", __FUNCTION__);
+#endif
+	if (!sc) {
+		goto out;
+	}
+	mutex_lock(&sc->mutex);
+	ret = ssv6xxx_get_promisc(sc, &accept);
+	mutex_unlock(&sc->mutex);
+	*pOutBuf = accept;
+	*pOutBufLen = 1;
+#ifdef KSMARTLINK_DEBUG
+	printk(KERN_INFO "%s %d\n", __FUNCTION__, accept);
+#endif
+ out:
+	return ret;
+}
+
+#define SMARTLINK_CMD_FIXED_LEN (10)
+#define SMARTLINK_CMD_FIXED_TOT_LEN (SMARTLINK_CMD_FIXED_LEN+1)
+#define SMARTLINK_RES_FIXED_LEN (SMARTLINK_CMD_FIXED_LEN)
+#define SMARTLINK_RES_FIXED_TOT_LEN (SMARTLINK_RES_FIXED_LEN+2)
+struct ksmartlink_cmd {
+	char *cmd;
+	int (*process_func)(u8 *, u32, u8 *, u32 *);
+};
+static struct ksmartlink_cmd _ksmartlink_cmd_table[] = {
+	{"startairki", _ksmartlink_start_smartlink},
+	{"stopairkis", _ksmartlink_stop_smartlink},
+	{"setchannel", _ksmartlink_set_channel},
+	{"getchannel", _ksmartlink_get_channel},
+	{"setpromisc", _ksmartlink_set_promisc},
+	{"getpromisc", _ksmartlink_get_promisc},
+};
+
+static u32 _ksmartlink_cmd_table_size =
+    sizeof(_ksmartlink_cmd_table) / sizeof(struct ksmartlink_cmd);
+#ifdef KSMARTLINK_DEBUG
+static void _ksmartlink_hex_dump(u8 * pInBuf, u32 inBufLen)
+{
+	u32 i = 0;
+	printk(KERN_INFO "\nKernel Hex Dump(len=%d):\n", inBufLen);
+	printk(KERN_INFO ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
+	for (i = 0; i < inBufLen; i++) {
+		if ((i) && ((i & 0xf) == 0)) {
+			printk("\n");
+		}
+		printk("%02x ", pInBuf[i]);
+	}
+	printk(KERN_INFO "<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
+}
+#endif
+static int _ksmartlink_process_msg(u8 * pInBuf, u32 inBufLen, u8 * pOutBuf,
+				   u32 * pOutBufLen)
+{
+	int ret = 0;
+	u32 i = 0;
+	struct ksmartlink_cmd *pCmd;
+	if (!pInBuf || !pOutBuf || !pOutBufLen) {
+		printk(KERN_ERR "NULL pointer\n");
+		return -1;
+	}
+	for (i = 0; i < _ksmartlink_cmd_table_size; i++) {
+		if (!strncmp
+		    (_ksmartlink_cmd_table[i].cmd, pInBuf,
+		     SMARTLINK_CMD_FIXED_LEN)) {
+			break;
+		}
+	}
+	if (i < _ksmartlink_cmd_table_size) {
+		pCmd = &_ksmartlink_cmd_table[i];
+		if (!pCmd->process_func) {
+			printk(KERN_ERR "CMD %s has NULL process_func\n",
+			       pCmd->cmd);
+			return -3;
+		}
+		ret =
+		    pCmd->process_func(pInBuf + SMARTLINK_CMD_FIXED_LEN,
+				       inBufLen, pOutBuf, pOutBufLen);
+#ifdef CONFIG_SSV_NETLINK_RESPONSE
+		if (ret < 0) {
+			*pOutBufLen = SMARTLINK_RES_FIXED_TOT_LEN;
+		} else {
+			if (*pOutBufLen > 0) {
+				pOutBuf[SMARTLINK_RES_FIXED_LEN] = (u8) ret;
+				pOutBuf[SMARTLINK_RES_FIXED_LEN + 1] = *pOutBuf;
+			} else {
+				pOutBuf[SMARTLINK_RES_FIXED_LEN] = (u8) ret;
+				pOutBuf[SMARTLINK_RES_FIXED_LEN + 1] = 0;
+			}
+			*pOutBufLen = SMARTLINK_RES_FIXED_TOT_LEN;
+		}
+		memcpy(pOutBuf, pCmd->cmd, SMARTLINK_RES_FIXED_LEN);
+#else
+		(void)pOutBuf;
+		(void)pOutBufLen;
+#endif
+		return 0;
+	} else {
+		printk(KERN_INFO "Unknow CMD or Packet?\n");
+	}
+	return 0;
+}
+static u8 gkBuf[MAX_PAYLOAD] = { 0 };
+
+static int ssv_usr_pid = 0;
+void smartlink_nl_recv_msg(struct sk_buff *skb)
+{
+	struct nlmsghdr *nlh;
+#ifdef CONFIG_SSV_NETLINK_RESPONSE
+	struct sk_buff *skb_out;
+#endif
+	int ret = 0;
+	u8 *pInBuf = NULL;
+	u32 inBufLen = 0;
+	u32 outBufLen = 0;
+	nlh = (struct nlmsghdr *)skb->data;
+	ssv_usr_pid = nlh->nlmsg_pid;
+	pInBuf = (u8 *) nlmsg_data(nlh);
+	inBufLen = nlmsg_len(nlh);
+#ifdef KSMARTLINK_DEBUG
+	_ksmartlink_hex_dump(pInBuf, inBufLen);
+#endif
+	outBufLen = 0;
+	memset(gkBuf, 0, MAX_PAYLOAD);
+	ret = _ksmartlink_process_msg(pInBuf, inBufLen, gkBuf, &outBufLen);
+#ifdef CONFIG_SSV_NETLINK_RESPONSE
+	if (outBufLen == 0) {
+		memcpy(gkBuf, "Nothing", 8);
+		outBufLen = strlen(gkBuf);
+	}
+	skb_out = nlmsg_new(outBufLen, 0);
+	if (!skb_out) {
+		printk(KERN_ERR "Failed to allocate new skb\n");
+		return;
+	}
+	nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, outBufLen, 0);
+	NETLINK_CB(skb_out).dst_group = 0;
+	memcpy(nlmsg_data(nlh), gkBuf, outBufLen);
+	ret = nlmsg_unicast(nl_sk, skb_out, ssv_usr_pid);
+	if (ret < 0) {
+		printk(KERN_ERR "Error while sending bak to user\n");
+	}
+#endif
+	return;
+}
+
+void smartlink_nl_send_msg(struct sk_buff *skb)
+{
+	struct nlmsghdr *nlh;
+	struct sk_buff *skb_out;
+	int ret = 0;
+	u8 *pOutBuf = skb->data;
+	u32 outBufLen = skb->len;
+#ifdef KSMARTLINK_DEBUG
+#endif
+	skb_out = nlmsg_new(outBufLen, 0);
+	if (!skb_out) {
+		printk(KERN_ERR "Allocate new skb failed!\n");
+		return;
+	}
+	nlh = nlmsg_put(skb_out, 0, 0, NLMSG_DONE, outBufLen, 0);
+	NETLINK_CB(skb_out).dst_group = 0;
+	memcpy(nlmsg_data(nlh), pOutBuf, outBufLen);
+	ret = nlmsg_unicast(nl_sk, skb_out, ssv_usr_pid);
+	if (ret < 0) {
+		printk(KERN_ERR "nlmsg_unicast failed!\n");
+	}
+	kfree_skb(skb);
+	return;
+}
+
+EXPORT_SYMBOL(smartlink_nl_send_msg);
+int ksmartlink_init(void)
+{
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0)
+	nl_sk = netlink_kernel_create(&init_net,
+				      NETLINK_SMARTLINK,
+				      0,
+				      smartlink_nl_recv_msg, NULL, THIS_MODULE);
+#else
+	struct netlink_kernel_cfg cfg = {
+		.groups = 0,
+		.input = smartlink_nl_recv_msg,
+	};
+	nl_sk = netlink_kernel_create(&init_net, NETLINK_SMARTLINK, &cfg);
+#endif
+	printk(KERN_INFO "***************SmartLink Init-S**************\n");
+	if (!nl_sk) {
+		printk(KERN_ERR "Error creating socket.\n");
+		return -10;
+	}
+	printk(KERN_INFO "***************SmartLink Init-E**************\n");
+	return 0;
+}
+
+void ksmartlink_exit(void)
+{
+	printk(KERN_INFO "%s\n", __FUNCTION__);
+	if (nl_sk) {
+		netlink_kernel_release(nl_sk);
+		nl_sk = NULL;
+	}
+}
+
+EXPORT_SYMBOL(ksmartlink_init);
+EXPORT_SYMBOL(ksmartlink_exit);
diff --git a/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
new file mode 100644
index 00000000000..9be5ea96e7f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/nl80211.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <net/mac80211.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ssv6xxx_debugfs.h"
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+#define QUEUE_STATUS_BUF_SIZE (4096)
+static ssize_t queue_status_read(struct file *file,
+				 char __user * user_buf, size_t count,
+				 loff_t * ppos)
+{
+	struct ssv_softc *sc = (struct ssv_softc *)file->private_data;
+	char *status_buf = kzalloc(QUEUE_STATUS_BUF_SIZE, GFP_KERNEL);
+	ssize_t status_size;
+	ssize_t ret;
+	if (!status_buf)
+		return -ENOMEM;
+	status_size = ssv6xxx_tx_queue_status_dump(sc, status_buf,
+						   QUEUE_STATUS_BUF_SIZE);
+	ret = simple_read_from_buffer(user_buf, count, ppos, status_buf,
+				      status_size);
+	kfree(status_buf);
+	return ret;
+}
+
+static int queue_status_open(struct inode *inode, struct file *file)
+{
+	file->private_data = inode->i_private;
+	return 0;
+}
+
+static const struct file_operations queue_status_fops
+    = {.read = queue_status_read,
+	.open = queue_status_open
+};
+#endif
+int ssv6xxx_init_debugfs(struct ssv_softc *sc, const char *name)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct ieee80211_hw *hw = sc->hw;
+	struct dentry *phy_debugfs_dir = hw->wiphy->debugfsdir;
+	struct dentry *drv_debugfs_dir;
+	drv_debugfs_dir = debugfs_create_dir(name, phy_debugfs_dir);
+	if (!drv_debugfs_dir) {
+		dev_err(sc->dev, "Failed to create debugfs.\n");
+		return -ENOMEM;
+	}
+	sc->debugfs_dir = drv_debugfs_dir;
+	sc->sh->hci.hci_ops->hci_init_debugfs(sc->debugfs_dir);
+	debugfs_create_file("queue_status", 00444, drv_debugfs_dir,
+			    sc, &queue_status_fops);
+#endif
+	return 0;
+}
+
+void ssv6xxx_deinit_debugfs(struct ssv_softc *sc)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	if (!sc->debugfs_dir)
+		return;
+	sc->sh->hci.hci_ops->hci_deinit_debugfs();
+	debugfs_remove_recursive(sc->debugfs_dir);
+	sc->debugfs_dir = NULL;
+#endif
+}
+
+int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc,
+				  struct ieee80211_vif *vif)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct dentry *drv_debugfs_dir = sc->debugfs_dir;
+	struct dentry *vif_debugfs_dir;
+	char vif_addr[18];
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+	snprintf(vif_addr, sizeof(vif_addr), "%02X-%02X-%02X-%02X-%02X-%02X",
+		 vif->addr[0], vif->addr[1], vif->addr[2],
+		 vif->addr[3], vif->addr[4], vif->addr[5]);
+	vif_debugfs_dir = debugfs_create_dir(vif_addr, drv_debugfs_dir);
+	if (!vif_debugfs_dir) {
+		dev_err(sc->dev, "Failed to create interface debugfs for %s.\n",
+			vif_addr);
+		return -ENOMEM;
+	}
+	sc->debugfs_dir = drv_debugfs_dir;
+	vif_info->debugfs_dir = vif_debugfs_dir;
+#endif
+	return 0;
+}
+
+int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc,
+				     struct ieee80211_vif *vif)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)vif->drv_priv;
+	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+	if ((vif_info->debugfs_dir == NULL) || (sc->debugfs_dir == NULL))
+		return 0;
+	debugfs_remove_recursive(vif_info->debugfs_dir);
+	vif_info->debugfs_dir = NULL;
+#endif
+	return 0;
+}
+
+int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)sta->vif->drv_priv;
+	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+	if ((sc->debugfs_dir == NULL) || (vif_info->debugfs_dir == NULL)
+	    || (sta->debugfs_dir == NULL))
+		return 0;
+	debugfs_remove_recursive(sta->debugfs_dir);
+	sta->debugfs_dir = NULL;
+#endif
+	return 0;
+}
+
+int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta)
+{
+#ifdef CONFIG_SSV6XXX_DEBUGFS
+	struct ssv_vif_priv_data *vif_priv =
+	    (struct ssv_vif_priv_data *)sta->vif->drv_priv;
+	struct ssv_vif_info *vif_info = &sc->vif_info[vif_priv->vif_idx];
+	struct dentry *vif_debugfs_dir = vif_info->debugfs_dir;
+	struct dentry *sta_debugfs_dir;
+	char sta_addr[18];
+	if (vif_debugfs_dir == NULL)
+		return 0;
+	snprintf(sta_addr, sizeof(sta_addr), "%02X-%02X-%02X-%02X-%02X-%02X",
+		 sta->sta->addr[0], sta->sta->addr[1], sta->sta->addr[2],
+		 sta->sta->addr[3], sta->sta->addr[4], sta->sta->addr[5]);
+	sta_debugfs_dir = debugfs_create_dir(sta_addr, vif_debugfs_dir);
+	if (!sta_debugfs_dir) {
+		dev_err(sc->dev, "Failed to create interface debugfs for %s.\n",
+			sta_addr);
+		return -ENOMEM;
+	}
+	sta->debugfs_dir = sta_debugfs_dir;
+#endif
+	return 0;
+}
+
+#define DEBUGFS_ADD_FILE(name,parent,mode) do { \
+    if (!debugfs_create_file(#name, mode, parent, priv, \
+                 &ssv_dbgfs_##name##_ops)) \
+        goto err; \
+} while (0)
+#define DEBUGFS_ADD_BOOL(name,parent,ptr) do { \
+    struct dentry *__tmp; \
+    __tmp = debugfs_create_bool(#name, S_IWUSR | S_IRUSR, \
+                    parent, ptr); \
+    if (IS_ERR(__tmp) || !__tmp) \
+        goto err; \
+} while (0)
+#define DEBUGFS_ADD_X32(name,parent,ptr) do { \
+    struct dentry *__tmp; \
+    __tmp = debugfs_create_x32(#name, S_IWUSR | S_IRUSR, \
+                   parent, ptr); \
+    if (IS_ERR(__tmp) || !__tmp) \
+        goto err; \
+} while (0)
+#define DEBUGFS_ADD_U32(name,parent,ptr,mode) do { \
+    struct dentry *__tmp; \
+    __tmp = debugfs_create_u32(#name, mode, \
+                   parent, ptr); \
+    if (IS_ERR(__tmp) || !__tmp) \
+        goto err; \
+} while (0)
+#define DEBUGFS_READ_FUNC(name) \
+static ssize_t ssv_dbgfs_##name##_read(struct file *file, \
+                    char __user *user_buf, \
+                    size_t count, loff_t *ppos);
+#define DEBUGFS_WRITE_FUNC(name) \
+static ssize_t ssv_dbgfs_##name##_write(struct file *file, \
+                    const char __user *user_buf, \
+                    size_t count, loff_t *ppos);
+#define DEBUGFS_READ_FILE_OPS(name) \
+    DEBUGFS_READ_FUNC(name); \
+static const struct file_operations ssv_dbgfs_##name##_ops = { \
+    .read = ssv_dbgfs_##name##_read, \
+    .open = ssv_dbgfs_open_file_generic, \
+    .llseek = generic_file_llseek, \
+};
+#define DEBUGFS_WRITE_FILE_OPS(name) \
+    DEBUGFS_WRITE_FUNC(name); \
+static const struct file_operations ssv_dbgfs_##name##_ops = { \
+    .write = ssv_dbgfs_##name##_write, \
+    .open = ssv_dbgfs_open_file_generic, \
+    .llseek = generic_file_llseek, \
+};
+#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
+    DEBUGFS_READ_FUNC(name); \
+    DEBUGFS_WRITE_FUNC(name); \
+static const struct file_operations ssv_dbgfs_##name##_ops = { \
+    .write = ssv_dbgfs_##name##_write, \
+    .read = ssv_dbgfs_##name##_read, \
+    .open = ssv_dbgfs_open_file_generic, \
+    .llseek = generic_file_llseek, \
+};
diff --git a/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
new file mode 100644
index 00000000000..39caceadda4
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv6xxx_debugfs.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SSV6XXX_DBGFS_H__
+#define __SSV6XXX_DBGFS_H__
+int ssv6xxx_init_debugfs(struct ssv_softc *sc, const char *name);
+void ssv6xxx_deinit_debugfs(struct ssv_softc *sc);
+int ssv6xxx_debugfs_remove_interface(struct ssv_softc *sc,
+				     struct ieee80211_vif *vif);
+int ssv6xxx_debugfs_add_interface(struct ssv_softc *sc,
+				  struct ieee80211_vif *vif);
+int ssv6xxx_debugfs_remove_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);
+int ssv6xxx_debugfs_add_sta(struct ssv_softc *sc, struct ssv_sta_info *sta);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
new file mode 100644
index 00000000000..f0135447b1f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.c
@@ -0,0 +1,1384 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 - 2018 icomm Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#include "dev.h"
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(CONFIG_SSV_VENDOR_EXT_SUPPORT)
+
+#include <linux/kernel.h>
+#include <linux/if_arp.h>
+#include <asm/uaccess.h>
+
+#include <linux/kernel.h>
+#include <linux/kthread.h>
+#include <linux/netdevice.h>
+#include <linux/sched.h>
+#include <linux/etherdevice.h>
+#include <linux/wireless.h>
+#include <linux/ieee80211.h>
+#include <linux/wait.h>
+#include <net/cfg80211.h>
+
+#include <net/rtnetlink.h>
+#include "ssv_cfgvendor.h"
+
+#define wiphy_to_softc(x) (*((struct ssv_softc**)wiphy_priv(x)))
+#define FUNC_NDEV_FMT "%s"
+#define FUNC_NDEV_ARG(ndev) __func__
+
+#define _drv_always_		1
+#define _drv_emerg_			2
+#define _drv_alert_			3
+#define _drv_crit_			4
+#define _drv_err_			5
+#define _drv_warning_		6
+#define _drv_notice_		7
+#define _drv_info_			8
+#define _drv_dump_			9
+#define _drv_debug_			10
+
+struct sk_buff *ssv_cfg80211_vendor_event_alloc(struct wiphy *wiphy, int len,
+						int event_id, gfp_t gfp)
+{
+	struct sk_buff *skb;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))
+	skb = cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp);
+#else
+	skb = cfg80211_vendor_event_alloc(wiphy, NULL, len, event_id, gfp);
+#endif
+	return skb;
+}
+
+#define ssv_cfg80211_vendor_event(skb, gfp) \
+	cfg80211_vendor_event(skb, gfp)
+
+#define ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) \
+	cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len)
+
+#define ssv_cfg80211_vendor_cmd_reply(skb) \
+	cfg80211_vendor_cmd_reply(skb)
+
+/*
+ * This API is to be used for asynchronous vendor events. This
+ * shouldn't be used in response to a vendor command from its
+ * do_it handler context (instead ssv_cfgvendor_send_cmd_reply should
+ * be used).
+ */
+int ssv_cfgvendor_send_async_event(struct wiphy *wiphy,
+				   struct net_device *dev, int event_id,
+				   const void *data, int len)
+{
+	u16 kflags;
+	struct sk_buff *skb;
+
+	kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
+
+	/* Alloc the SKB for vendor_event */
+	skb = ssv_cfg80211_vendor_event_alloc(wiphy, len, event_id, kflags);
+	if (!skb) {
+		dev_err(&wiphy->dev, "skb alloc failed\n");
+		return -ENOMEM;
+	}
+
+	/* Push the data to the skb */
+	nla_put_nohdr(skb, len, data);
+
+	ssv_cfg80211_vendor_event(skb, kflags);
+
+	return 0;
+}
+
+static int ssv_cfgvendor_send_cmd_reply(struct wiphy *wiphy,
+					struct net_device *dev,
+					const void *data, int len)
+{
+	struct sk_buff *skb;
+
+	/* Alloc the SKB for vendor_event */
+	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);
+	if (unlikely(!skb)) {
+		dev_err(&wiphy->dev, "skb alloc failed");
+		return -ENOMEM;
+	}
+
+	/* Push the data to the skb */
+	nla_put_nohdr(skb, len, data);
+
+	return ssv_cfg80211_vendor_cmd_reply(skb);
+}
+
+#define WIFI_FEATURE_INFRA              0x0001	/* Basic infrastructure mode        */
+#define WIFI_FEATURE_INFRA_5G           0x0002	/* Support for 5 GHz Band           */
+#define WIFI_FEATURE_HOTSPOT            0x0004	/* Support for GAS/ANQP             */
+#define WIFI_FEATURE_P2P                0x0008	/* Wifi-Direct                      */
+#define WIFI_FEATURE_SOFT_AP            0x0010	/* Soft AP                          */
+#define WIFI_FEATURE_GSCAN              0x0020	/* Google-Scan APIs                 */
+#define WIFI_FEATURE_NAN                0x0040	/* Neighbor Awareness Networking    */
+#define WIFI_FEATURE_D2D_RTT            0x0080	/* Device-to-device RTT             */
+#define WIFI_FEATURE_D2AP_RTT           0x0100	/* Device-to-AP RTT                 */
+#define WIFI_FEATURE_BATCH_SCAN         0x0200	/* Batched Scan (legacy)            */
+#define WIFI_FEATURE_PNO                0x0400	/* Preferred network offload        */
+#define WIFI_FEATURE_ADDITIONAL_STA     0x0800	/* Support for two STAs             */
+#define WIFI_FEATURE_TDLS               0x1000	/* Tunnel directed link setup       */
+#define WIFI_FEATURE_TDLS_OFFCHANNEL    0x2000	/* Support for TDLS off channel     */
+#define WIFI_FEATURE_EPR                0x4000	/* Enhanced power reporting         */
+#define WIFI_FEATURE_AP_STA             0x8000	/* Support for AP STA Concurrency   */
+
+#define MAX_FEATURE_SET_CONCURRRENT_GROUPS  3
+
+int ssv_dev_get_feature_set(struct net_device *dev)
+{
+	int feature_set = 0;
+
+	feature_set |= WIFI_FEATURE_INFRA;
+
+	feature_set |= WIFI_FEATURE_P2P;
+	feature_set |= WIFI_FEATURE_SOFT_AP;
+
+#if defined(GSCAN_SUPPORT)
+	feature_set |= WIFI_FEATURE_GSCAN;
+#endif
+
+#if defined(RTT_SUPPORT)
+	feature_set |= WIFI_FEATURE_NAN;
+	feature_set |= WIFI_FEATURE_D2D_RTT;
+	feature_set |= WIFI_FEATURE_D2AP_RTT;
+#endif
+
+	return feature_set;
+}
+
+int *ssv_dev_get_feature_set_matrix(struct net_device *dev, int *num)
+{
+	int feature_set_full, mem_needed;
+	int *ret;
+
+	*num = 0;
+	mem_needed = sizeof(int) * MAX_FEATURE_SET_CONCURRRENT_GROUPS;
+	ret =
+	    (int *)kmalloc(mem_needed, in_interrupt()? GFP_ATOMIC : GFP_KERNEL);
+
+	if (!ret) {
+		dev_err(&dev->dev, "failed to allocate %d bytes\n", mem_needed);
+		return ret;
+	}
+
+	feature_set_full = ssv_dev_get_feature_set(dev);
+
+	ret[0] = (feature_set_full & WIFI_FEATURE_INFRA) |
+	    (feature_set_full & WIFI_FEATURE_INFRA_5G) |
+	    (feature_set_full & WIFI_FEATURE_NAN) |
+	    (feature_set_full & WIFI_FEATURE_D2D_RTT) |
+	    (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
+	    (feature_set_full & WIFI_FEATURE_PNO) |
+	    (feature_set_full & WIFI_FEATURE_BATCH_SCAN) |
+	    (feature_set_full & WIFI_FEATURE_GSCAN) |
+	    (feature_set_full & WIFI_FEATURE_HOTSPOT) |
+	    (feature_set_full & WIFI_FEATURE_ADDITIONAL_STA) |
+	    (feature_set_full & WIFI_FEATURE_EPR);
+
+	ret[1] = (feature_set_full & WIFI_FEATURE_INFRA) |
+	    (feature_set_full & WIFI_FEATURE_INFRA_5G) |
+	    /* Not yet verified NAN with P2P */
+	    /* (feature_set_full & WIFI_FEATURE_NAN) | */
+	    (feature_set_full & WIFI_FEATURE_P2P) |
+	    (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
+	    (feature_set_full & WIFI_FEATURE_D2D_RTT) |
+	    (feature_set_full & WIFI_FEATURE_EPR);
+
+	ret[2] = (feature_set_full & WIFI_FEATURE_INFRA) |
+	    (feature_set_full & WIFI_FEATURE_INFRA_5G) |
+	    (feature_set_full & WIFI_FEATURE_NAN) |
+	    (feature_set_full & WIFI_FEATURE_D2D_RTT) |
+	    (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
+	    (feature_set_full & WIFI_FEATURE_TDLS) |
+	    (feature_set_full & WIFI_FEATURE_TDLS_OFFCHANNEL) |
+	    (feature_set_full & WIFI_FEATURE_EPR);
+	*num = MAX_FEATURE_SET_CONCURRRENT_GROUPS;
+
+	return ret;
+}
+
+#define wdev_to_ndev(wdev) NULL
+
+static int ssv_cfgvendor_get_feature_set(struct wiphy *wiphy,
+					 struct wireless_dev *wdev,
+					 const void *data, int len)
+{
+	int err = 0;
+	int reply;
+
+	reply = ssv_dev_get_feature_set(wdev_to_ndev(wdev));
+
+	err =
+	    ssv_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &reply,
+					 sizeof(int));
+
+	if (unlikely(err))
+		dev_err(&wiphy->dev, "vendor Command reply failed, ret:%d\n", err);
+
+	return err;
+}
+
+static int ssv_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy,
+						struct wireless_dev *wdev,
+						const void *data, int len)
+{
+	int err = 0;
+	struct sk_buff *skb;
+	int *reply;
+	int num, mem_needed, i;
+
+	reply = ssv_dev_get_feature_set_matrix(wdev_to_ndev(wdev), &num);
+
+	if (!reply) {
+		dev_err(&wiphy->dev, "could not get feature list matrix\n");
+		err = -EINVAL;
+		return err;
+	}
+
+	mem_needed = VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * num) +
+	    ATTRIBUTE_U32_LEN;
+
+	/* Alloc the SKB for vendor_event */
+	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
+	if (unlikely(!skb)) {
+		dev_err(&wiphy->dev, "skb alloc failed\n");
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, num);
+	for (i = 0; i < num; i++) {
+		nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_FEATURE_SET, reply[i]);
+	}
+
+	err = ssv_cfg80211_vendor_cmd_reply(skb);
+
+	if (unlikely(err))
+		dev_err(&wiphy->dev, "vendor Command reply failed, ret=%d\n", err);
+ exit:
+	kfree((void *)reply);
+	return err;
+}
+
+#if defined(GSCAN_SUPPORT) && 0
+int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
+				    struct net_device *dev, void *data, int len,
+				    wl_vendor_event_t event)
+{
+	u16 kflags;
+	const void *ptr;
+	struct sk_buff *skb;
+	int malloc_len, total, iter_cnt_to_send, cnt;
+	gscan_results_cache_t *cache = (gscan_results_cache_t *) data;
+
+	total = len / sizeof(wifi_gscan_result_t);
+	while (total > 0) {
+		malloc_len =
+		    (total * sizeof(wifi_gscan_result_t)) +
+		    VENDOR_DATA_OVERHEAD;
+		if (malloc_len > NLMSG_DEFAULT_SIZE) {
+			malloc_len = NLMSG_DEFAULT_SIZE;
+		}
+		iter_cnt_to_send =
+		    (malloc_len -
+		     VENDOR_DATA_OVERHEAD) / sizeof(wifi_gscan_result_t);
+		total = total - iter_cnt_to_send;
+
+		kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
+
+		/* Alloc the SKB for vendor_event */
+		skb =
+		    ssv_cfg80211_vendor_event_alloc(wiphy, malloc_len, event,
+						    kflags);
+		if (!skb) {
+			WL_ERR(("skb alloc failed"));
+			return -ENOMEM;
+		}
+
+		while (cache && iter_cnt_to_send) {
+			ptr =
+			    (const void *)&cache->results[cache->tot_consumed];
+
+			if (iter_cnt_to_send <
+			    (cache->tot_count - cache->tot_consumed))
+				cnt = iter_cnt_to_send;
+			else
+				cnt = (cache->tot_count - cache->tot_consumed);
+
+			iter_cnt_to_send -= cnt;
+			cache->tot_consumed += cnt;
+			/* Push the data to the skb */
+			nla_append(skb, cnt * sizeof(wifi_gscan_result_t), ptr);
+			if (cache->tot_consumed == cache->tot_count)
+				cache = cache->next;
+
+		}
+
+		ssv_cfg80211_vendor_event(skb, kflags);
+	}
+
+	return 0;
+}
+
+static int wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy,
+					       struct wireless_dev *wdev,
+					       const void *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	dhd_pno_gscan_capabilities_t *reply = NULL;
+	uint32 reply_len = 0;
+
+	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
+				      DHD_PNO_GET_CAPABILITIES, NULL,
+				      &reply_len);
+	if (!reply) {
+		WL_ERR(("Could not get capabilities\n"));
+		err = -EINVAL;
+		return err;
+	}
+
+	err = ssv_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
+					   reply, reply_len);
+
+	if (unlikely(err))
+		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
+
+	kfree(reply);
+	return err;
+}
+
+static int wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy,
+					       struct wireless_dev *wdev,
+					       const void *data, int len)
+{
+	int err = 0, type, band;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	uint16 *reply = NULL;
+	uint32 reply_len = 0, num_channels, mem_needed;
+	struct sk_buff *skb;
+
+	type = nla_type(data);
+
+	if (type == GSCAN_ATTRIBUTE_BAND) {
+		band = nla_get_u32(data);
+	} else {
+		return -1;
+	}
+
+	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
+				      DHD_PNO_GET_CHANNEL_LIST, &band,
+				      &reply_len);
+
+	if (!reply) {
+		WL_ERR(("Could not get channel list\n"));
+		err = -EINVAL;
+		return err;
+	}
+	num_channels = reply_len / sizeof(uint32);
+	mem_needed =
+	    reply_len + VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * 2);
+
+	/* Alloc the SKB for vendor_event */
+	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
+	if (unlikely(!skb)) {
+		WL_ERR(("skb alloc failed"));
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_CHANNELS, num_channels);
+	nla_put(skb, GSCAN_ATTRIBUTE_CHANNEL_LIST, reply_len, reply);
+
+	err = ssv_cfg80211_vendor_cmd_reply(skb);
+
+	if (unlikely(err))
+		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
+ exit:
+	kfree(reply);
+	return err;
+}
+
+static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy,
+						struct wireless_dev *wdev,
+						const void *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	gscan_results_cache_t *results, *iter;
+	uint32 reply_len, complete = 0, num_results_iter;
+	int32 mem_needed;
+	wifi_gscan_result_t *ptr;
+	uint16 num_scan_ids, num_results;
+	struct sk_buff *skb;
+	struct nlattr *scan_hdr;
+
+	dhd_dev_wait_batch_results_complete(bcmcfg_to_prmry_ndev(cfg));
+	dhd_dev_pno_lock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
+	results = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
+					DHD_PNO_GET_BATCH_RESULTS, NULL,
+					&reply_len);
+
+	if (!results) {
+		WL_ERR(("No results to send %d\n", err));
+		err =
+		    ssv_cfgvendor_send_cmd_reply(wiphy,
+						 bcmcfg_to_prmry_ndev(cfg),
+						 results, 0);
+
+		if (unlikely(err))
+			WL_ERR(("Vendor Command reply failed ret:%d \n", err));
+		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev
+							(cfg));
+		return err;
+	}
+	num_scan_ids = reply_len & 0xFFFF;
+	num_results = (reply_len & 0xFFFF0000) >> 16;
+	mem_needed = (num_results * sizeof(wifi_gscan_result_t)) +
+	    (num_scan_ids * GSCAN_BATCH_RESULT_HDR_LEN) +
+	    VENDOR_REPLY_OVERHEAD + SCAN_RESULTS_COMPLETE_FLAG_LEN;
+
+	if (mem_needed > (int32) NLMSG_DEFAULT_SIZE) {
+		mem_needed = (int32) NLMSG_DEFAULT_SIZE;
+		complete = 0;
+	} else {
+		complete = 1;
+	}
+
+	WL_TRACE(("complete %d mem_needed %d max_mem %d\n", complete,
+		  mem_needed, (int)NLMSG_DEFAULT_SIZE));
+	/* Alloc the SKB for vendor_event */
+	skb = ssv_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
+	if (unlikely(!skb)) {
+		WL_ERR(("skb alloc failed"));
+		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev
+							(cfg));
+		return -ENOMEM;
+	}
+	iter = results;
+
+	nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE, complete);
+
+	mem_needed =
+	    mem_needed - (SCAN_RESULTS_COMPLETE_FLAG_LEN +
+			  VENDOR_REPLY_OVERHEAD);
+
+	while (iter && ((mem_needed - GSCAN_BATCH_RESULT_HDR_LEN) > 0)) {
+		scan_hdr = nla_nest_start(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS);
+		nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_ID, iter->scan_id);
+		nla_put_u8(skb, GSCAN_ATTRIBUTE_SCAN_FLAGS, iter->flag);
+		num_results_iter =
+		    (mem_needed -
+		     GSCAN_BATCH_RESULT_HDR_LEN) / sizeof(wifi_gscan_result_t);
+
+		if ((iter->tot_count - iter->tot_consumed) < num_results_iter)
+			num_results_iter = iter->tot_count - iter->tot_consumed;
+
+		nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_OF_RESULTS,
+			    num_results_iter);
+		if (num_results_iter) {
+			ptr = &iter->results[iter->tot_consumed];
+			iter->tot_consumed += num_results_iter;
+			nla_put(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS,
+				num_results_iter * sizeof(wifi_gscan_result_t),
+				ptr);
+		}
+		nla_nest_end(skb, scan_hdr);
+		mem_needed -= GSCAN_BATCH_RESULT_HDR_LEN +
+		    (num_results_iter * sizeof(wifi_gscan_result_t));
+		iter = iter->next;
+	}
+
+	dhd_dev_gscan_batch_cache_cleanup(bcmcfg_to_prmry_ndev(cfg));
+	dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
+
+	return ssv_cfg80211_vendor_cmd_reply(skb);
+}
+
+static int wl_cfgvendor_initiate_gscan(struct wiphy *wiphy,
+				       struct wireless_dev *wdev,
+				       const void *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	int type, tmp = len;
+	int run = 0xFF;
+	int flush = 0;
+	const struct nlattr *iter;
+
+	nla_for_each_attr(iter, data, len, tmp) {
+		type = nla_type(iter);
+		if (type == GSCAN_ATTRIBUTE_ENABLE_FEATURE)
+			run = nla_get_u32(iter);
+		else if (type == GSCAN_ATTRIBUTE_FLUSH_FEATURE)
+			flush = nla_get_u32(iter);
+	}
+
+	if (run != 0xFF) {
+		err =
+		    dhd_dev_pno_run_gscan(bcmcfg_to_prmry_ndev(cfg), run,
+					  flush);
+
+		if (unlikely(err))
+			WL_ERR(("Could not run gscan:%d \n", err));
+		return err;
+	} else {
+		return -1;
+	}
+
+}
+
+static int wl_cfgvendor_enable_full_scan_result(struct wiphy *wiphy,
+						struct wireless_dev *wdev,
+						const void *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	int type;
+	bool real_time = FALSE;
+
+	type = nla_type(data);
+
+	if (type == GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS) {
+		real_time = nla_get_u32(data);
+
+		err =
+		    dhd_dev_pno_enable_full_scan_result(bcmcfg_to_prmry_ndev
+							(cfg), real_time);
+
+		if (unlikely(err))
+			WL_ERR(("Could not run gscan:%d \n", err));
+
+	} else {
+		err = -1;
+	}
+
+	return err;
+}
+
+static int wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy,
+				     struct wireless_dev *wdev,
+				     const void *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	gscan_scan_params_t *scan_param;
+	int j = 0;
+	int type, tmp, tmp1, tmp2, k = 0;
+	const struct nlattr *iter, *iter1, *iter2;
+	struct dhd_pno_gscan_channel_bucket *ch_bucket;
+
+	scan_param = kzalloc(sizeof(gscan_scan_params_t), GFP_KERNEL);
+	if (!scan_param) {
+		WL_ERR(("Could not set GSCAN scan cfg, mem alloc failure\n"));
+		err = -EINVAL;
+		return err;
+
+	}
+
+	scan_param->scan_fr = PNO_SCAN_MIN_FW_SEC;
+	nla_for_each_attr(iter, data, len, tmp) {
+		type = nla_type(iter);
+
+		if (j >= GSCAN_MAX_CH_BUCKETS)
+			break;
+
+		switch (type) {
+		case GSCAN_ATTRIBUTE_BASE_PERIOD:
+			scan_param->scan_fr = nla_get_u32(iter) / 1000;
+			break;
+		case GSCAN_ATTRIBUTE_NUM_BUCKETS:
+			scan_param->nchannel_buckets = nla_get_u32(iter);
+			break;
+		case GSCAN_ATTRIBUTE_CH_BUCKET_1:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_2:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_3:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_4:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_5:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_6:
+		case GSCAN_ATTRIBUTE_CH_BUCKET_7:
+			nla_for_each_nested(iter1, iter, tmp1) {
+				type = nla_type(iter1);
+				ch_bucket = scan_param->channel_bucket;
+
+				switch (type) {
+				case GSCAN_ATTRIBUTE_BUCKET_ID:
+					break;
+				case GSCAN_ATTRIBUTE_BUCKET_PERIOD:
+					ch_bucket[j].bucket_freq_multiple =
+					    nla_get_u32(iter1) / 1000;
+					break;
+				case GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS:
+					ch_bucket[j].num_channels =
+					    nla_get_u32(iter1);
+					break;
+				case GSCAN_ATTRIBUTE_BUCKET_CHANNELS:
+					nla_for_each_nested(iter2, iter1, tmp2) {
+						if (k >=
+						    PFN_SWC_RSSI_WINDOW_MAX)
+							break;
+						ch_bucket[j].chan_list[k] =
+						    nla_get_u32(iter2);
+						k++;
+					}
+					k = 0;
+					break;
+				case GSCAN_ATTRIBUTE_BUCKETS_BAND:
+					ch_bucket[j].band = (uint16)
+					    nla_get_u32(iter1);
+					break;
+				case GSCAN_ATTRIBUTE_REPORT_EVENTS:
+					ch_bucket[j].report_flag = (uint8)
+					    nla_get_u32(iter1);
+					break;
+				}
+			}
+			j++;
+			break;
+		}
+	}
+
+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+				      DHD_PNO_SCAN_CFG_ID, scan_param, 0) < 0) {
+		WL_ERR(("Could not set GSCAN scan cfg\n"));
+		err = -EINVAL;
+	}
+
+	kfree(scan_param);
+	return err;
+
+}
+
+static int wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy,
+				    struct wireless_dev *wdev, const void *data,
+				    int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	gscan_hotlist_scan_params_t *hotlist_params;
+	int tmp, tmp1, tmp2, type, j = 0, dummy;
+	const struct nlattr *outer, *inner, *iter;
+	uint8 flush = 0;
+	struct bssid_t *pbssid;
+
+	hotlist_params =
+	    (gscan_hotlist_scan_params_t *) kzalloc(len, GFP_KERNEL);
+	if (!hotlist_params) {
+		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes \n", len));
+		return -1;
+	}
+
+	hotlist_params->lost_ap_window = GSCAN_LOST_AP_WINDOW_DEFAULT;
+
+	nla_for_each_attr(iter, data, len, tmp2) {
+		type = nla_type(iter);
+		switch (type) {
+		case GSCAN_ATTRIBUTE_HOTLIST_BSSIDS:
+			pbssid = hotlist_params->bssid;
+			nla_for_each_nested(outer, iter, tmp) {
+				nla_for_each_nested(inner, outer, tmp1) {
+					type = nla_type(inner);
+
+					switch (type) {
+					case GSCAN_ATTRIBUTE_BSSID:
+						memcpy(&(pbssid[j].macaddr),
+						       nla_data(inner),
+						       ETHER_ADDR_LEN);
+						break;
+					case GSCAN_ATTRIBUTE_RSSI_LOW:
+						pbssid[j].
+						    rssi_reporting_threshold =
+						    (int8) nla_get_u8(inner);
+						break;
+					case GSCAN_ATTRIBUTE_RSSI_HIGH:
+						dummy =
+						    (int8) nla_get_u8(inner);
+						break;
+					}
+				}
+				j++;
+			}
+			hotlist_params->nbssid = j;
+			break;
+		case GSCAN_ATTRIBUTE_HOTLIST_FLUSH:
+			flush = nla_get_u8(iter);
+			break;
+		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
+			hotlist_params->lost_ap_window = nla_get_u32(iter);
+			break;
+		}
+
+	}
+
+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+				      DHD_PNO_GEOFENCE_SCAN_CFG_ID,
+				      hotlist_params, flush) < 0) {
+		WL_ERR(("Could not set GSCAN HOTLIST cfg\n"));
+		err = -EINVAL;
+		goto exit;
+	}
+ exit:
+	kfree(hotlist_params);
+	return err;
+}
+
+static int wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy,
+					   struct wireless_dev *wdev,
+					   const void *data, int len)
+{
+	int err = 0, tmp, type;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	gscan_batch_params_t batch_param;
+	const struct nlattr *iter;
+
+	batch_param.mscan = batch_param.bestn = 0;
+	batch_param.buffer_threshold = GSCAN_BATCH_NO_THR_SET;
+
+	nla_for_each_attr(iter, data, len, tmp) {
+		type = nla_type(iter);
+
+		switch (type) {
+		case GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN:
+			batch_param.bestn = nla_get_u32(iter);
+			break;
+		case GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE:
+			batch_param.mscan = nla_get_u32(iter);
+			break;
+		case GSCAN_ATTRIBUTE_REPORT_THRESHOLD:
+			batch_param.buffer_threshold = nla_get_u32(iter);
+			break;
+		}
+	}
+
+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+				      DHD_PNO_BATCH_SCAN_CFG_ID, &batch_param,
+				      0) < 0) {
+		WL_ERR(("Could not set batch cfg\n"));
+		err = -EINVAL;
+		return err;
+	}
+
+	return err;
+}
+
+static int wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy,
+					       struct wireless_dev *wdev,
+					       const void *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	gscan_swc_params_t *significant_params;
+	int tmp, tmp1, tmp2, type, j = 0;
+	const struct nlattr *outer, *inner, *iter;
+	uint8 flush = 0;
+	wl_pfn_significant_bssid_t *pbssid;
+
+	significant_params = (gscan_swc_params_t *) kzalloc(len, GFP_KERNEL);
+	if (!significant_params) {
+		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes \n", len));
+		return -1;
+	}
+
+	nla_for_each_attr(iter, data, len, tmp2) {
+		type = nla_type(iter);
+
+		switch (type) {
+		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH:
+			flush = nla_get_u8(iter);
+			break;
+		case GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE:
+			significant_params->rssi_window = nla_get_u16(iter);
+			break;
+		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
+			significant_params->lost_ap_window = nla_get_u16(iter);
+			break;
+		case GSCAN_ATTRIBUTE_MIN_BREACHING:
+			significant_params->swc_threshold = nla_get_u16(iter);
+			break;
+		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS:
+			pbssid = significant_params->bssid_elem_list;
+			nla_for_each_nested(outer, iter, tmp) {
+				nla_for_each_nested(inner, outer, tmp1) {
+					switch (nla_type(inner)) {
+					case GSCAN_ATTRIBUTE_BSSID:
+						memcpy(&(pbssid[j].macaddr),
+						       nla_data(inner),
+						       ETHER_ADDR_LEN);
+						break;
+					case GSCAN_ATTRIBUTE_RSSI_HIGH:
+						pbssid[j].rssi_high_threshold =
+						    (int8) nla_get_u8(inner);
+						break;
+					case GSCAN_ATTRIBUTE_RSSI_LOW:
+						pbssid[j].rssi_low_threshold =
+						    (int8) nla_get_u8(inner);
+						break;
+					}
+				}
+				j++;
+			}
+			break;
+		}
+	}
+	significant_params->nbssid = j;
+
+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
+				      DHD_PNO_SIGNIFICANT_SCAN_CFG_ID,
+				      significant_params, flush) < 0) {
+		WL_ERR(("Could not set GSCAN significant cfg\n"));
+		err = -EINVAL;
+		goto exit;
+	}
+ exit:
+	kfree(significant_params);
+	return err;
+}
+#endif				/* GSCAN_SUPPORT */
+
+#if defined(RTT_SUPPORT) && 0
+void wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data)
+{
+	struct wireless_dev *wdev = (struct wireless_dev *)ctx;
+	struct wiphy *wiphy;
+	struct sk_buff *skb;
+	uint32 tot_len = NLMSG_DEFAULT_SIZE, entry_len = 0;
+	gfp_t kflags;
+	rtt_report_t *rtt_report = NULL;
+	rtt_result_t *rtt_result = NULL;
+	struct list_head *rtt_list;
+	wiphy = wdev->wiphy;
+
+	WL_DBG(("In\n"));
+	/* Push the data to the skb */
+	if (!rtt_data) {
+		WL_ERR(("rtt_data is NULL\n"));
+		goto exit;
+	}
+	rtt_list = (struct list_head *)rtt_data;
+	kflags = in_atomic()? GFP_ATOMIC : GFP_KERNEL;
+	/* Alloc the SKB for vendor_event */
+	skb =
+	    ssv_cfg80211_vendor_event_alloc(wiphy, tot_len,
+					    GOOGLE_RTT_COMPLETE_EVENT, kflags);
+	if (!skb) {
+		WL_ERR(("skb alloc failed"));
+		goto exit;
+	}
+	/* fill in the rtt results on each entry */
+	list_for_each_entry(rtt_result, rtt_list, list) {
+		entry_len = 0;
+		if (rtt_result->TOF_type == TOF_TYPE_ONE_WAY) {
+			entry_len = sizeof(rtt_report_t);
+			rtt_report = kzalloc(entry_len, kflags);
+			if (!rtt_report) {
+				WL_ERR(("rtt_report alloc failed"));
+				goto exit;
+			}
+			rtt_report->addr = rtt_result->peer_mac;
+			rtt_report->num_measurement = 1;	/* ONE SHOT */
+			rtt_report->status = rtt_result->err_code;
+			rtt_report->type =
+			    (rtt_result->TOF_type ==
+			     TOF_TYPE_ONE_WAY) ? RTT_ONE_WAY : RTT_TWO_WAY;
+			rtt_report->peer = rtt_result->target_info->peer;
+			rtt_report->channel = rtt_result->target_info->channel;
+			rtt_report->rssi = rtt_result->avg_rssi;
+			/* tx_rate */
+			rtt_report->tx_rate = rtt_result->tx_rate;
+			/* RTT */
+			rtt_report->rtt = rtt_result->meanrtt;
+			rtt_report->rtt_sd = rtt_result->sdrtt;
+			/* convert to centi meter */
+			if (rtt_result->distance != 0xffffffff)
+				rtt_report->distance =
+				    (rtt_result->distance >> 2) * 25;
+			else	/* invalid distance */
+				rtt_report->distance = -1;
+
+			rtt_report->ts = rtt_result->ts;
+			nla_append(skb, entry_len, rtt_report);
+			kfree(rtt_report);
+		}
+	}
+	ssv_cfg80211_vendor_event(skb, kflags);
+ exit:
+	return;
+}
+
+static int wl_cfgvendor_rtt_set_config(struct wiphy *wiphy,
+				       struct wireless_dev *wdev,
+				       const void *data, int len)
+{
+	int err = 0, rem, rem1, rem2, type;
+	rtt_config_params_t rtt_param;
+	rtt_target_info_t *rtt_target = NULL;
+	const struct nlattr *iter, *iter1, *iter2;
+	int8 eabuf[ETHER_ADDR_STR_LEN];
+	int8 chanbuf[CHANSPEC_STR_LEN];
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+
+	WL_DBG(("In\n"));
+	err =
+	    dhd_dev_rtt_register_noti_callback(wdev->netdev, wdev,
+					       wl_cfgvendor_rtt_evt);
+	if (err < 0) {
+		WL_ERR(("failed to register rtt_noti_callback\n"));
+		goto exit;
+	}
+	memset(&rtt_param, 0, sizeof(rtt_param));
+	nla_for_each_attr(iter, data, len, rem) {
+		type = nla_type(iter);
+		switch (type) {
+		case RTT_ATTRIBUTE_TARGET_CNT:
+			rtt_param.rtt_target_cnt = nla_get_u8(iter);
+			if (rtt_param.rtt_target_cnt > RTT_MAX_TARGET_CNT) {
+				WL_ERR(("exceed max target count : %d\n",
+					rtt_param.rtt_target_cnt));
+				err = BCME_RANGE;
+			}
+			break;
+		case RTT_ATTRIBUTE_TARGET_INFO:
+			rtt_target = rtt_param.target_info;
+			nla_for_each_nested(iter1, iter, rem1) {
+				nla_for_each_nested(iter2, iter1, rem2) {
+					type = nla_type(iter2);
+					switch (type) {
+					case RTT_ATTRIBUTE_TARGET_MAC:
+						memcpy(&rtt_target->addr,
+						       nla_data(iter2),
+						       ETHER_ADDR_LEN);
+						break;
+					case RTT_ATTRIBUTE_TARGET_TYPE:
+						rtt_target->type =
+						    nla_get_u8(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_PEER:
+						rtt_target->peer =
+						    nla_get_u8(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_CHAN:
+						memcpy(&rtt_target->channel,
+						       nla_data(iter2),
+						       sizeof(rtt_target->
+							      channel));
+						break;
+					case RTT_ATTRIBUTE_TARGET_MODE:
+						rtt_target->continuous =
+						    nla_get_u8(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_INTERVAL:
+						rtt_target->interval =
+						    nla_get_u32(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT:
+						rtt_target->measure_cnt =
+						    nla_get_u32(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_NUM_PKT:
+						rtt_target->ftm_cnt =
+						    nla_get_u32(iter2);
+						break;
+					case RTT_ATTRIBUTE_TARGET_NUM_RETRY:
+						rtt_target->retry_cnt =
+						    nla_get_u32(iter2);
+					}
+				}
+				/* convert to chanspec value */
+				rtt_target->chanspec =
+				    dhd_rtt_convert_to_chspec(rtt_target->
+							      channel);
+				if (rtt_target->chanspec == 0) {
+					WL_ERR(("Channel is not valid \n"));
+					goto exit;
+				}
+				WL_INFORM(("Target addr %s, Channel : %s for RTT \n", bcm_ether_ntoa((const struct ether_addr *)&rtt_target->addr, eabuf), wf_chspec_ntoa(rtt_target->chanspec, chanbuf)));
+				rtt_target++;
+			}
+			break;
+		}
+	}
+	WL_DBG(("leave :target_cnt : %d\n", rtt_param.rtt_target_cnt));
+	if (dhd_dev_rtt_set_cfg(bcmcfg_to_prmry_ndev(cfg), &rtt_param) < 0) {
+		WL_ERR(("Could not set RTT configuration\n"));
+		err = -EINVAL;
+	}
+ exit:
+	return err;
+}
+
+static int wl_cfgvendor_rtt_cancel_config(struct wiphy *wiphy,
+					  struct wireless_dev *wdev,
+					  const void *data, int len)
+{
+	int err = 0, rem, type, target_cnt = 0;
+	const struct nlattr *iter;
+	struct ether_addr *mac_list = NULL, *mac_addr = NULL;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+
+	nla_for_each_attr(iter, data, len, rem) {
+		type = nla_type(iter);
+		switch (type) {
+		case RTT_ATTRIBUTE_TARGET_CNT:
+			target_cnt = nla_get_u8(iter);
+			mac_list =
+			    (struct ether_addr *)kzalloc(target_cnt *
+							 ETHER_ADDR_LEN,
+							 GFP_KERNEL);
+			if (mac_list == NULL) {
+				WL_ERR(("failed to allocate mem for mac list\n"));
+				goto exit;
+			}
+			mac_addr = &mac_list[0];
+			break;
+		case RTT_ATTRIBUTE_TARGET_MAC:
+			if (mac_addr)
+				memcpy(mac_addr++, nla_data(iter),
+				       ETHER_ADDR_LEN);
+			else {
+				WL_ERR(("mac_list is NULL\n"));
+				goto exit;
+			}
+			break;
+		}
+		if (dhd_dev_rtt_cancel_cfg
+		    (bcmcfg_to_prmry_ndev(cfg), mac_list, target_cnt) < 0) {
+			WL_ERR(("Could not cancel RTT configuration\n"));
+			err = -EINVAL;
+			goto exit;
+		}
+	}
+ exit:
+	if (mac_list)
+		kfree(mac_list);
+	return err;
+}
+
+static int wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy,
+					   struct wireless_dev *wdev,
+					   const void *data, int len)
+{
+	int err = 0;
+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
+	rtt_capabilities_t capability;
+
+	err = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability);
+	if (unlikely(err)) {
+		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
+		goto exit;
+	}
+	err = ssv_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
+					   &capability, sizeof(capability));
+
+	if (unlikely(err)) {
+		WL_ERR(("Vendor Command reply failed ret:%d \n", err));
+	}
+ exit:
+	return err;
+}
+
+#endif				/* RTT_SUPPORT */
+static int wl_cfgvendor_priv_string_handler(struct wiphy *wiphy,
+					    struct wireless_dev *wdev,
+					    const void *data, int len)
+{
+	int err = 0;
+	u8 resp[1] = { '\0' };
+
+	dev_dbg(&wiphy->dev, "%s\n", (char *)data);
+	err = ssv_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), resp, 1);
+	if (unlikely(err))
+		dev_err(&wiphy->dev, "vendor Command reply failed, ret=:%d\n", err);
+
+	return err;
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0)
+static const struct wiphy_vendor_command ssv_vendor_cmds[] = {
+	{
+	 {
+	  .vendor_id = OUI_SSV,
+	  .subcmd = RTK_VENDOR_SCMD_PRIV_STR},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_priv_string_handler,
+	 .policy = VENDOR_CMD_RAW_DATA},
+#if defined(GSCAN_SUPPORT) && 0
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_gscan_get_capabilities,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_set_scan_cfg,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_set_batch_scan_cfg,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_initiate_gscan,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_enable_full_scan_result,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_HOTLIST},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_hotlist_cfg,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_significant_change_cfg,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_gscan_get_batch_results,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_gscan_get_channel_list,
+	 .policy = VENDOR_CMD_RAW_DATA},
+#endif				/* GSCAN_SUPPORT */
+#if defined(RTT_SUPPORT) && 0
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = RTT_SUBCMD_SET_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_rtt_set_config,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = RTT_SUBCMD_CANCEL_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_rtt_cancel_config,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = RTT_SUBCMD_GETCAPABILITY},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_rtt_get_capability,
+	 .policy = VENDOR_CMD_RAW_DATA},
+#endif				/* RTT_SUPPORT */
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = ssv_cfgvendor_get_feature_set,
+	 .policy = VENDOR_CMD_RAW_DATA},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = ssv_cfgvendor_get_feature_set_matrix,
+	 .policy = VENDOR_CMD_RAW_DATA}
+};
+#else
+static const struct wiphy_vendor_command ssv_vendor_cmds[] = {
+	{
+	 {
+	  .vendor_id = OUI_SSV,
+	  .subcmd = RTK_VENDOR_SCMD_PRIV_STR},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_priv_string_handler
+	},
+#if defined(GSCAN_SUPPORT) && 0
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_gscan_get_capabilities
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_set_scan_cfg
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_set_batch_scan_cfg
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_initiate_gscan
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_enable_full_scan_result
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_HOTLIST},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_hotlist_cfg
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_significant_change_cfg
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_gscan_get_batch_results
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_gscan_get_channel_list
+	},
+#endif				/* GSCAN_SUPPORT */
+#if defined(RTT_SUPPORT) && 0
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = RTT_SUBCMD_SET_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_rtt_set_config
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = RTT_SUBCMD_CANCEL_CONFIG},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_rtt_cancel_config
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = RTT_SUBCMD_GETCAPABILITY},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = wl_cfgvendor_rtt_get_capability
+	},
+#endif				/* RTT_SUPPORT */
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = ssv_cfgvendor_get_feature_set
+	},
+	{
+	 {
+	  .vendor_id = OUI_GOOGLE,
+	  .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX},
+	 .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
+	 .doit = ssv_cfgvendor_get_feature_set_matrix
+	}
+};
+#endif
+
+static const struct nl80211_vendor_cmd_info ssv_vendor_events[] = {
+	{OUI_SSV, RTK_VENDOR_EVENT_UNSPEC},
+	{OUI_SSV, RTK_VENDOR_EVENT_PRIV_STR},
+#if defined(GSCAN_SUPPORT) && 0
+	{OUI_GOOGLE, GOOGLE_GSCAN_SIGNIFICANT_EVENT},
+	{OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT},
+	{OUI_GOOGLE, GOOGLE_GSCAN_BATCH_SCAN_EVENT},
+	{OUI_GOOGLE, GOOGLE_SCAN_FULL_RESULTS_EVENT},
+#endif				/* GSCAN_SUPPORT */
+#if defined(RTT_SUPPORT) && 0
+	{OUI_GOOGLE, GOOGLE_RTT_COMPLETE_EVENT},
+#endif				/* RTT_SUPPORT */
+#if defined(GSCAN_SUPPORT) && 0
+	{OUI_GOOGLE, GOOGLE_SCAN_COMPLETE_EVENT},
+	{OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_LOST_EVENT}
+#endif				/* GSCAN_SUPPORT */
+};
+
+int ssv_cfgvendor_attach(struct wiphy *wiphy)
+{
+
+	dev_info(&wiphy->dev, "register SSV cfg80211 vendor cmd(0x%x) interface\n",
+		NL80211_CMD_VENDOR);
+
+	wiphy->vendor_commands = ssv_vendor_cmds;
+	wiphy->n_vendor_commands = ARRAY_SIZE(ssv_vendor_cmds);
+	wiphy->vendor_events = ssv_vendor_events;
+	wiphy->n_vendor_events = ARRAY_SIZE(ssv_vendor_events);
+
+	return 0;
+}
+
+int ssv_cfgvendor_detach(struct wiphy *wiphy)
+{
+	dev_info(&wiphy->dev, "unregister SSV cfg80211 vendor interface\n");
+
+	wiphy->vendor_commands = NULL;
+	wiphy->vendor_events = NULL;
+	wiphy->n_vendor_commands = 0;
+	wiphy->n_vendor_events = 0;
+
+	return 0;
+}
+#endif				/* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(SSV_VENDOR_EXT_SUPPORT) */
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
new file mode 100644
index 00000000000..6d8696fcd22
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_cfgvendor.h
@@ -0,0 +1,247 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef _RTW_CFGVENDOR_H_
+#define _RTW_CFGVENDOR_H_
+
+#define OUI_SSV		0x00E04C
+#define OUI_GOOGLE	0x001A11
+#define ATTRIBUTE_U32_LEN                  (NLA_HDRLEN  + 4)
+#define VENDOR_ID_OVERHEAD                 ATTRIBUTE_U32_LEN
+#define VENDOR_SUBCMD_OVERHEAD             ATTRIBUTE_U32_LEN
+#define VENDOR_DATA_OVERHEAD               (NLA_HDRLEN)
+
+#define SCAN_RESULTS_COMPLETE_FLAG_LEN       ATTRIBUTE_U32_LEN
+#define SCAN_INDEX_HDR_LEN                   (NLA_HDRLEN)
+#define SCAN_ID_HDR_LEN                      ATTRIBUTE_U32_LEN
+#define SCAN_FLAGS_HDR_LEN                   ATTRIBUTE_U32_LEN
+#define GSCAN_NUM_RESULTS_HDR_LEN            ATTRIBUTE_U32_LEN
+#define GSCAN_RESULTS_HDR_LEN                (NLA_HDRLEN)
+#define GSCAN_BATCH_RESULT_HDR_LEN  (SCAN_INDEX_HDR_LEN + SCAN_ID_HDR_LEN + \
+									SCAN_FLAGS_HDR_LEN + \
+							        GSCAN_NUM_RESULTS_HDR_LEN + \
+									GSCAN_RESULTS_HDR_LEN)
+
+#define VENDOR_REPLY_OVERHEAD       (VENDOR_ID_OVERHEAD + \
+									VENDOR_SUBCMD_OVERHEAD + \
+									VENDOR_DATA_OVERHEAD)
+typedef enum {
+	/* don't use 0 as a valid subcommand */
+	VENDOR_NL80211_SUBCMD_UNSPECIFIED,
+
+	/* define all vendor startup commands between 0x0 and 0x0FFF */
+	VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001,
+	VENDOR_NL80211_SUBCMD_RANGE_END = 0x0FFF,
+
+	/* define all GScan related commands between 0x1000 and 0x10FF */
+	ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000,
+	ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END = 0x10FF,
+
+	/* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */
+	ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100,
+	ANDROID_NL80211_SUBCMD_NBD_RANGE_END = 0x11FF,
+
+	/* define all RTT related commands between 0x1100 and 0x11FF */
+	ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100,
+	ANDROID_NL80211_SUBCMD_RTT_RANGE_END = 0x11FF,
+
+	ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200,
+	ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END = 0x12FF,
+
+	ANDROID_NL80211_SUBCMD_TDLS_RANGE_START = 0x1300,
+	ANDROID_NL80211_SUBCMD_TDLS_RANGE_END = 0x13FF,
+	/* This is reserved for future usage */
+
+} ANDROID_VENDOR_SUB_COMMAND;
+
+enum wl_vendor_subcmd {
+	RTK_VENDOR_SCMD_UNSPEC,
+	RTK_VENDOR_SCMD_PRIV_STR,
+	GSCAN_SUBCMD_GET_CAPABILITIES =
+	    ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START,
+	GSCAN_SUBCMD_SET_CONFIG,
+	GSCAN_SUBCMD_SET_SCAN_CONFIG,
+	GSCAN_SUBCMD_ENABLE_GSCAN,
+	GSCAN_SUBCMD_GET_SCAN_RESULTS,
+	GSCAN_SUBCMD_SCAN_RESULTS,
+	GSCAN_SUBCMD_SET_HOTLIST,
+	GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG,
+	GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS,
+	GSCAN_SUBCMD_GET_CHANNEL_LIST,
+	ANDR_WIFI_SUBCMD_GET_FEATURE_SET,
+	ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX,
+	RTT_SUBCMD_SET_CONFIG = ANDROID_NL80211_SUBCMD_RTT_RANGE_START,
+	RTT_SUBCMD_CANCEL_CONFIG,
+	RTT_SUBCMD_GETCAPABILITY,
+	/* Add more sub commands here */
+	VENDOR_SUBCMD_MAX
+};
+
+enum gscan_attributes {
+	GSCAN_ATTRIBUTE_NUM_BUCKETS = 10,
+	GSCAN_ATTRIBUTE_BASE_PERIOD,
+	GSCAN_ATTRIBUTE_BUCKETS_BAND,
+	GSCAN_ATTRIBUTE_BUCKET_ID,
+	GSCAN_ATTRIBUTE_BUCKET_PERIOD,
+	GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS,
+	GSCAN_ATTRIBUTE_BUCKET_CHANNELS,
+	GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN,
+	GSCAN_ATTRIBUTE_REPORT_THRESHOLD,
+	GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE,
+	GSCAN_ATTRIBUTE_BAND = GSCAN_ATTRIBUTE_BUCKETS_BAND,
+
+	GSCAN_ATTRIBUTE_ENABLE_FEATURE = 20,
+	GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE,
+	GSCAN_ATTRIBUTE_FLUSH_FEATURE,
+	GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS,
+	GSCAN_ATTRIBUTE_REPORT_EVENTS,
+	/* remaining reserved for additional attributes */
+	GSCAN_ATTRIBUTE_NUM_OF_RESULTS = 30,
+	GSCAN_ATTRIBUTE_FLUSH_RESULTS,
+	GSCAN_ATTRIBUTE_SCAN_RESULTS,	/* flat array of wifi_scan_result */
+	GSCAN_ATTRIBUTE_SCAN_ID,	/* indicates scan number */
+	GSCAN_ATTRIBUTE_SCAN_FLAGS,	/* indicates if scan was aborted */
+	GSCAN_ATTRIBUTE_AP_FLAGS,	/* flags on significant change event */
+	GSCAN_ATTRIBUTE_NUM_CHANNELS,
+	GSCAN_ATTRIBUTE_CHANNEL_LIST,
+
+	/* remaining reserved for additional attributes */
+
+	GSCAN_ATTRIBUTE_SSID = 40,
+	GSCAN_ATTRIBUTE_BSSID,
+	GSCAN_ATTRIBUTE_CHANNEL,
+	GSCAN_ATTRIBUTE_RSSI,
+	GSCAN_ATTRIBUTE_TIMESTAMP,
+	GSCAN_ATTRIBUTE_RTT,
+	GSCAN_ATTRIBUTE_RTTSD,
+
+	/* remaining reserved for additional attributes */
+
+	GSCAN_ATTRIBUTE_HOTLIST_BSSIDS = 50,
+	GSCAN_ATTRIBUTE_RSSI_LOW,
+	GSCAN_ATTRIBUTE_RSSI_HIGH,
+	GSCAN_ATTRIBUTE_HOSTLIST_BSSID_ELEM,
+	GSCAN_ATTRIBUTE_HOTLIST_FLUSH,
+
+	/* remaining reserved for additional attributes */
+	GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE = 60,
+	GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE,
+	GSCAN_ATTRIBUTE_MIN_BREACHING,
+	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS,
+	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH,
+	GSCAN_ATTRIBUTE_MAX
+};
+
+enum gscan_bucket_attributes {
+	GSCAN_ATTRIBUTE_CH_BUCKET_1,
+	GSCAN_ATTRIBUTE_CH_BUCKET_2,
+	GSCAN_ATTRIBUTE_CH_BUCKET_3,
+	GSCAN_ATTRIBUTE_CH_BUCKET_4,
+	GSCAN_ATTRIBUTE_CH_BUCKET_5,
+	GSCAN_ATTRIBUTE_CH_BUCKET_6,
+	GSCAN_ATTRIBUTE_CH_BUCKET_7
+};
+
+enum gscan_ch_attributes {
+	GSCAN_ATTRIBUTE_CH_ID_1,
+	GSCAN_ATTRIBUTE_CH_ID_2,
+	GSCAN_ATTRIBUTE_CH_ID_3,
+	GSCAN_ATTRIBUTE_CH_ID_4,
+	GSCAN_ATTRIBUTE_CH_ID_5,
+	GSCAN_ATTRIBUTE_CH_ID_6,
+	GSCAN_ATTRIBUTE_CH_ID_7
+};
+
+enum rtt_attributes {
+	RTT_ATTRIBUTE_TARGET_CNT,
+	RTT_ATTRIBUTE_TARGET_INFO,
+	RTT_ATTRIBUTE_TARGET_MAC,
+	RTT_ATTRIBUTE_TARGET_TYPE,
+	RTT_ATTRIBUTE_TARGET_PEER,
+	RTT_ATTRIBUTE_TARGET_CHAN,
+	RTT_ATTRIBUTE_TARGET_MODE,
+	RTT_ATTRIBUTE_TARGET_INTERVAL,
+	RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT,
+	RTT_ATTRIBUTE_TARGET_NUM_PKT,
+	RTT_ATTRIBUTE_TARGET_NUM_RETRY
+};
+
+typedef enum wl_vendor_event {
+	RTK_VENDOR_EVENT_UNSPEC,
+	RTK_VENDOR_EVENT_PRIV_STR,
+	GOOGLE_GSCAN_SIGNIFICANT_EVENT,
+	GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT,
+	GOOGLE_GSCAN_BATCH_SCAN_EVENT,
+	GOOGLE_SCAN_FULL_RESULTS_EVENT,
+	GOOGLE_RTT_COMPLETE_EVENT,
+	GOOGLE_SCAN_COMPLETE_EVENT,
+	GOOGLE_GSCAN_GEOFENCE_LOST_EVENT
+} wl_vendor_event_t;
+
+enum andr_wifi_feature_set_attr {
+	ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET,
+	ANDR_WIFI_ATTRIBUTE_FEATURE_SET
+};
+
+typedef enum wl_vendor_gscan_attribute {
+	ATTR_START_GSCAN,
+	ATTR_STOP_GSCAN,
+	ATTR_SET_SCAN_BATCH_CFG_ID,	/* set batch scan params */
+	ATTR_SET_SCAN_GEOFENCE_CFG_ID,	/* set list of bssids to track */
+	ATTR_SET_SCAN_SIGNIFICANT_CFG_ID,	/* set list of bssids, rssi threshold etc.. */
+	ATTR_SET_SCAN_CFG_ID,	/* set common scan config params here */
+	ATTR_GET_GSCAN_CAPABILITIES_ID,
+	/* Add more sub commands here */
+	ATTR_GSCAN_MAX
+} wl_vendor_gscan_attribute_t;
+
+typedef enum gscan_batch_attribute {
+	ATTR_GSCAN_BATCH_BESTN,
+	ATTR_GSCAN_BATCH_MSCAN,
+	ATTR_GSCAN_BATCH_BUFFER_THRESHOLD
+} gscan_batch_attribute_t;
+
+typedef enum gscan_geofence_attribute {
+	ATTR_GSCAN_NUM_HOTLIST_BSSID,
+	ATTR_GSCAN_HOTLIST_BSSID
+} gscan_geofence_attribute_t;
+
+typedef enum gscan_complete_event {
+	WIFI_SCAN_BUFFER_FULL,
+	WIFI_SCAN_COMPLETE
+} gscan_complete_event_t;
+
+/* Capture the RTK_VENDOR_SUBCMD_PRIV_STRINGS* here */
+#define RTK_VENDOR_SCMD_CAPA	"cap"
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(SSV_VENDOR_EXT_SUPPORT)
+extern int ssv_cfgvendor_attach(struct wiphy *wiphy);
+extern int ssv_cfgvendor_detach(struct wiphy *wiphy);
+extern int ssv_cfgvendor_send_async_event(struct wiphy *wiphy,
+					  struct net_device *dev, int event_id,
+					  const void *data, int len);
+#if defined(GSCAN_SUPPORT) && 0
+extern int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
+					   struct net_device *dev, void *data,
+					   int len, wl_vendor_event_t event);
+#endif
+#endif				/* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */
+
+#endif				/* _RTW_CFGVENDOR_H_ */
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
new file mode 100644
index 00000000000..fae819c4340
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.c
@@ -0,0 +1,546 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ssv_ht_rc.h"
+#include "ssv_rc.h"
+#define SAMPLE_COUNT 4
+#define HT_CW_MIN 15
+#define HT_SEGMENT_SIZE 6000
+#define AVG_PKT_SIZE 12000
+#define SAMPLE_COLUMNS 10
+#define EWMA_LEVEL 75
+#define MCS_NBITS (AVG_PKT_SIZE << 3)
+#define MCS_NSYMS(bps) ((MCS_NBITS + (bps) - 1) / (bps))
+#define MCS_SYMBOL_TIME(sgi,syms) \
+    (sgi ? \
+      ((syms) * 18 + 4) / 5 : \
+      (syms) << 2 \
+    )
+#define MCS_DURATION(streams,sgi,bps) MCS_SYMBOL_TIME(sgi, MCS_NSYMS((streams) * (bps)))
+#define MCS_GROUP(_streams,_sgi,_ht40) { \
+    .duration = { \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 54 : 26), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 108 : 52), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 162 : 78), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 216 : 104), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 324 : 156), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 432 : 208), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 486 : 234), \
+        MCS_DURATION(_streams, _sgi, _ht40 ? 540 : 260) \
+    } \
+}
+const struct mcs_group minstrel_mcs_groups_ssv[] = {
+	MCS_GROUP(1, 0, 0),
+	MCS_GROUP(1, 1, 0),
+};
+
+const u16 ampdu_max_transmit_length[RATE_TABLE_SIZE] = {
+	0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0,
+	4600, 9200, 13800, 18500, 27700, 37000, 41600, 46200,
+	5100, 10200, 15400, 20500, 30800, 41100, 46200, 51300,
+	4600, 9200, 13800, 18500, 27700, 37000, 41600, 46200
+};
+
+static u8 sample_table[SAMPLE_COLUMNS][MCS_GROUP_RATES];
+static int minstrel_ewma(int old, int new, int weight)
+{
+	return (new * (100 - weight) + old * weight) / 100;
+}
+
+static inline struct minstrel_rate_stats *minstrel_get_ratestats(struct
+								 ssv62xx_ht *mi,
+								 int index)
+{
+	return &mi->groups.rates[index % MCS_GROUP_RATES];
+}
+
+static void minstrel_calc_rate_ewma(struct minstrel_rate_stats *mr)
+{
+	if (unlikely(mr->attempts > 0)) {
+		mr->sample_skipped = 0;
+		mr->cur_prob = MINSTREL_FRAC(mr->success, mr->attempts);
+		if (!mr->att_hist)
+			mr->probability = mr->cur_prob;
+		else
+			mr->probability = minstrel_ewma(mr->probability,
+							mr->cur_prob,
+							EWMA_LEVEL);
+		mr->att_hist += mr->attempts;
+		mr->succ_hist += mr->success;
+	} else {
+		mr->sample_skipped++;
+	}
+	mr->last_success = mr->success;
+	mr->last_attempts = mr->attempts;
+	mr->success = 0;
+	mr->attempts = 0;
+}
+
+static void minstrel_ht_calc_tp(struct ssv62xx_ht *mi,
+				struct ssv_sta_rc_info *rc_sta, int rate)
+{
+	struct minstrel_rate_stats *mr;
+	unsigned int usecs, group_id;
+	if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
+		group_id = 0;
+	else
+		group_id = 1;
+	mr = &mi->groups.rates[rate];
+	if (mr->probability < MINSTREL_FRAC(1, 10)) {
+		mr->cur_tp = 0;
+		return;
+	}
+	usecs = mi->overhead / MINSTREL_TRUNC(mi->avg_ampdu_len);
+	usecs += minstrel_mcs_groups_ssv[group_id].duration[rate];
+	mr->cur_tp = MINSTREL_TRUNC((1000000 / usecs) * mr->probability);
+}
+
+static void rate_control_ht_sample(struct ssv62xx_ht *mi,
+				   struct ssv_sta_rc_info *rc_sta)
+{
+	struct minstrel_mcs_group_data *mg;
+	struct minstrel_rate_stats *mr;
+	int cur_prob, cur_prob_tp, cur_tp, cur_tp2;
+	int i, index;
+	if (mi->ampdu_packets > 0) {
+		mi->avg_ampdu_len = minstrel_ewma(mi->avg_ampdu_len,
+						  MINSTREL_FRAC(mi->ampdu_len,
+								mi->
+								ampdu_packets),
+						  EWMA_LEVEL);
+		mi->ampdu_len = 0;
+		mi->ampdu_packets = 0;
+	} else
+		return;
+	mi->sample_slow = 0;
+	mi->sample_count = 0;
+	{
+		cur_prob = 0;
+		cur_prob_tp = 0;
+		cur_tp = 0;
+		cur_tp2 = 0;
+		mg = &mi->groups;
+		mg->max_tp_rate = 0;
+		mg->max_tp_rate2 = 0;
+		mg->max_prob_rate = 0;
+		for (i = 0; i < MCS_GROUP_RATES; i++) {
+			if (!(rc_sta->ht_supp_rates & BIT(i)))
+				continue;
+			mr = &mg->rates[i];
+			index = i;
+			minstrel_calc_rate_ewma(mr);
+			minstrel_ht_calc_tp(mi, rc_sta, i);
+#ifdef RATE_CONTROL_HT_PARAMETER_DEBUG
+			if (mr->cur_prob)
+				pr_debug
+				    ("rate[%d]probability[%08d]cur_prob[%08d]TP[%04d]\n",
+				     i, mr->probability, mr->cur_prob,
+				     mr->cur_tp);
+#endif
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+			pr_debug
+			    ("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n",
+			     mg->max_tp_rate, mg->max_tp_rate2,
+			     mg->max_prob_rate);
+			pr_debug("rate[%d]probability[%08d]TP[%d]\n", i,
+			       mr->probability, mr->cur_tp);
+#endif
+			if (!mr->cur_tp)
+				continue;
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+			pr_debug("HT--1 mr->cur_tp[%d]cur_prob_tp[%d]\n",
+			       mr->cur_tp, cur_prob_tp);
+#endif
+			if ((mr->cur_tp > cur_prob_tp && mr->probability >
+			     MINSTREL_FRAC(3, 4))
+			    || mr->probability > cur_prob) {
+				mg->max_prob_rate = index;
+				cur_prob = mr->probability;
+				cur_prob_tp = mr->cur_tp;
+			}
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+			pr_debug("HT--2 mr->cur_tp[%d]cur_tp[%d]\n", mr->cur_tp,
+			       cur_tp);
+#endif
+			if (mr->cur_tp > cur_tp) {
+				swap(index, mg->max_tp_rate);
+				cur_tp = mr->cur_tp;
+				mr = minstrel_get_ratestats(mi, index);
+			}
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+			if (index != i)
+				pr_debug
+				    ("HT--3 index[%d]i[%d]mg->max_tp_rate[%d]\n",
+				     index, i, mg->max_tp_rate);
+#endif
+			if (index >= mg->max_tp_rate)
+				continue;
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+			if (index != i)
+				pr_debug("HT--4 mr->cur_tp[%d]cur_tp2[%d]\n",
+				       mr->cur_tp, cur_tp2);
+#endif
+			if (mr->cur_tp > cur_tp2) {
+				mg->max_tp_rate2 = index;
+				cur_tp2 = mr->cur_tp;
+			}
+		}
+	}
+	mi->sample_count = SAMPLE_COUNT;
+	mi->max_tp_rate = mg->max_tp_rate;
+	mi->max_tp_rate2 = mg->max_tp_rate2;
+	mi->max_prob_rate = mg->max_prob_rate;
+#ifdef RATE_CONTROL_HT_STUPID_DEBUG
+	pr_debug
+	    ("HT sample result max_tp_rate[%d]max_tp_rate2[%d]max_prob_rate[%d]\n",
+	     mi->max_tp_rate, mi->max_tp_rate2, mi->max_prob_rate);
+#endif
+	mi->stats_update = jiffies;
+}
+
+static void minstrel_ht_set_rate(struct ssv62xx_ht *mi,
+				 struct fw_rc_retry_params *rate, int index,
+				 bool sample, bool rtscts,
+				 struct ssv_sta_rc_info *rc_sta,
+				 struct ssv_rate_ctrl *ssv_rc)
+{
+	struct minstrel_rate_stats *mr;
+	mr = minstrel_get_ratestats(mi, index);
+	rate->drate = ssv_rc->rc_table[mr->rc_index].hw_rate_idx;
+	rate->crate = ssv_rc->rc_table[mr->rc_index].ctrl_rate_idx;
+}
+
+static inline int minstrel_get_duration(int index,
+					struct ssv_sta_rc_info *rc_sta)
+{
+	unsigned int group_id;
+	const struct mcs_group *group;
+	if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
+		group_id = 0;
+	else
+		group_id = 1;
+	group = &minstrel_mcs_groups_ssv[group_id];
+	return group->duration[index % MCS_GROUP_RATES];
+}
+
+static void minstrel_next_sample_idx(struct ssv62xx_ht *mi)
+{
+	struct minstrel_mcs_group_data *mg;
+	for (;;) {
+		mg = &mi->groups;
+		if (++mg->index >= MCS_GROUP_RATES) {
+			mg->index = 0;
+			if (++mg->column >= ARRAY_SIZE(sample_table))
+				mg->column = 0;
+		}
+		break;
+	}
+}
+
+static int minstrel_get_sample_rate(struct ssv62xx_ht *mi,
+				    struct ssv_sta_rc_info *rc_sta)
+{
+	struct minstrel_rate_stats *mr;
+	struct minstrel_mcs_group_data *mg;
+	int sample_idx = 0;
+	if (mi->sample_wait > 0) {
+		mi->sample_wait--;
+		return -1;
+	}
+	if (!mi->sample_tries)
+		return -1;
+	mi->sample_tries--;
+	mg = &mi->groups;
+	sample_idx = sample_table[mg->column][mg->index];
+	mr = &mg->rates[sample_idx];
+	minstrel_next_sample_idx(mi);
+	if (minstrel_get_duration(sample_idx, rc_sta) >
+	    minstrel_get_duration(mi->max_tp_rate, rc_sta)) {
+		if (mr->sample_skipped < 20) {
+			return -1;
+		}
+		if (mi->sample_slow++ > 2) {
+			return -1;
+		}
+	}
+	return sample_idx;
+}
+
+static void _fill_txinfo_rates(struct ssv_rate_ctrl *ssv_rc,
+			       struct sk_buff *skb,
+			       struct fw_rc_retry_params *ar)
+{
+	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+	info->control.rates[0].idx =
+	    ssv_rc->rc_table[ar[0].drate].dot11_rate_idx;
+	info->control.rates[0].count = 1;
+	info->control.rates[SSV_DRATE_IDX].count = ar[0].drate;
+	info->control.rates[SSV_CRATE_IDX].count = ar[0].crate;
+}
+
+extern const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13];
+s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc,
+			   struct fw_rc_retry_params *ar)
+{
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+	struct ieee80211_sta *sta = skb_info->sta;
+	struct ssv62xx_ht *mi = NULL;
+	int sample_idx;
+	bool sample = false;
+	struct ssv_sta_rc_info *rc_sta;
+	struct ssv_sta_priv_data *sta_priv;
+	struct rc_pid_sta_info *spinfo;
+	int ret = 0;
+	if (sc->sc_flags & SC_OP_FIXED_RATE) {
+		ar[0].count = 3;
+		ar[0].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+		ar[0].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
+		ar[1].count = 2;
+		ar[1].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+		ar[1].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
+		ar[2].count = 2;
+		ar[2].drate = ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+		ar[2].crate = ssv_rc->rc_table[sc->max_rate_idx].ctrl_rate_idx;
+		_fill_txinfo_rates(ssv_rc, skb, ar);
+		return ssv_rc->rc_table[sc->max_rate_idx].hw_rate_idx;
+	}
+	if (sta == NULL) {
+		dev_err(sc->dev, "Station NULL\n");
+		BUG_ON(1);
+	}
+	sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx];
+	spinfo = &rc_sta->spinfo;
+	if ((rc_sta->rc_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT)
+	    || (rc_sta->rc_wsid < 0)) {
+		struct ssv_sta_priv_data *ssv_sta_priv;
+		int rateidx = 99;
+		ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+		{
+			if ((rc_sta->ht_rc_type >= RC_TYPE_HT_SGI_20) &&
+			    (ssv_sta_priv->rx_data_rate <
+			     SSV62XX_RATE_MCS_INDEX)) {
+				if (ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0]
+				    == 12)
+					rateidx =
+					    (int)rc_sta->pinfo.rinfo[4].
+					    rc_index;
+				else
+					rateidx =
+					    (int)rc_sta->pinfo.rinfo[0].
+					    rc_index;
+			} else {
+				rateidx = (int)ssv_sta_priv->rx_data_rate;
+				rateidx -= SSV62XX_RATE_MCS_INDEX;
+				rateidx %= 8;
+				if (rc_sta->ht_rc_type == RC_TYPE_HT_SGI_20)
+					rateidx += SSV62XX_RATE_MCS_SGI_INDEX;
+				else if (rc_sta->ht_rc_type ==
+					 RC_TYPE_HT_LGI_20)
+					rateidx += SSV62XX_RATE_MCS_LGI_INDEX;
+				else
+					rateidx +=
+					    SSV62XX_RATE_MCS_GREENFIELD_INDEX;
+			}
+		}
+		ar[0].count = 3;
+		ar[2].drate = ar[1].drate = ar[0].drate =
+		    ssv_rc->rc_table[rateidx].hw_rate_idx;
+		ar[2].crate = ar[1].crate = ar[0].crate =
+		    ssv_rc->rc_table[rateidx].ctrl_rate_idx;
+		ar[1].count = 2;
+		ar[2].count = 2;
+		_fill_txinfo_rates(ssv_rc, skb, ar);
+		return rateidx;
+	}
+	mi = &rc_sta->ht;
+	sample_idx = minstrel_get_sample_rate(mi, rc_sta);
+	if (sample_idx >= 0) {
+		sample = true;
+		minstrel_ht_set_rate(mi, &ar[0], sample_idx,
+				     true, false, rc_sta, ssv_rc);
+	} else {
+		minstrel_ht_set_rate(mi, &ar[0], mi->max_tp_rate,
+				     false, false, rc_sta, ssv_rc);
+	}
+	ar[0].count = mi->first_try_count;
+	ret = ar[0].drate;
+	{
+		if (sample_idx >= 0)
+			minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate,
+					     false, false, rc_sta, ssv_rc);
+		else
+			minstrel_ht_set_rate(mi, &ar[1], mi->max_tp_rate2,
+					     false, true, rc_sta, ssv_rc);
+		ar[1].count = mi->second_try_count;
+		if (ret > ar[1].drate)
+			ret = ar[1].drate;
+		minstrel_ht_set_rate(mi, &ar[2], mi->max_prob_rate,
+				     false, !sample, rc_sta, ssv_rc);
+		ar[2].count = mi->other_try_count;
+		if (ret > ar[2].drate)
+			ret = ar[2].drate;
+	}
+	mi->total_packets++;
+	if (mi->total_packets == ~0) {
+		mi->total_packets = 0;
+		mi->sample_packets = 0;
+	}
+	if (spinfo->real_hw_index < SSV62XX_RATE_MCS_INDEX)
+		return spinfo->real_hw_index;
+	_fill_txinfo_rates(ssv_rc, skb, ar);
+	return ret;
+}
+
+static void init_sample_table(void)
+{
+	int col, i, new_idx;
+	u8 rnd[MCS_GROUP_RATES];
+	memset(sample_table, 0xff, sizeof(sample_table));
+	for (col = 0; col < SAMPLE_COLUMNS; col++) {
+		for (i = 0; i < MCS_GROUP_RATES; i++) {
+			get_random_bytes(rnd, sizeof(rnd));
+			new_idx = (i + rnd[i]) % MCS_GROUP_RATES;
+			while (sample_table[col][new_idx] != 0xff)
+				new_idx = (new_idx + 1) % MCS_GROUP_RATES;
+			sample_table[col][new_idx] = i;
+		}
+	}
+}
+
+void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],
+			struct ssv_sta_rc_info *rc_sta)
+{
+	struct ssv62xx_ht *mi = &rc_sta->ht;
+	int ack_dur;
+	int i;
+	unsigned int group_id;
+	if (rc_sta->ht_rc_type == RC_TYPE_HT_LGI_20)
+		group_id = 0;
+	else
+		group_id = 1;
+	for (i = 0; i < MCS_GROUP_RATES; i++) {
+		pr_debug("[RC]HT duration[%d][%d]\n", i,
+		       minstrel_mcs_groups_ssv[group_id].duration[i]);
+	}
+	init_sample_table();
+	memset(mi, 0, sizeof(*mi));
+	mi->stats_update = jiffies;
+	ack_dur = pide_frame_duration(10, 60, 0, 0);
+	mi->overhead = pide_frame_duration(0, 60, 0, 0) + ack_dur;
+	mi->overhead_rtscts = mi->overhead + 2 * ack_dur;
+	mi->avg_ampdu_len = MINSTREL_FRAC(1, 1);
+	mi->sample_count = 16;
+	mi->sample_wait = 0;
+	mi->sample_tries = 4;
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+	mi->max_tp_rate = MCS_GROUP_RATES - 1;
+	mi->max_tp_rate2 = MCS_GROUP_RATES - 1;
+	mi->max_prob_rate = MCS_GROUP_RATES - 1;
+#endif
+#if (HW_MAX_RATE_TRIES == 7)
+	{
+		mi->first_try_count = 3;
+		mi->second_try_count = 2;
+		mi->other_try_count = 2;
+	}
+#else
+	{
+		mi->first_try_count = 2;
+		mi->second_try_count = 1;
+		mi->other_try_count = 1;
+	}
+#endif
+	for (i = 0; i < MCS_GROUP_RATES; i++) {
+		mi->groups.rates[i].rc_index =
+		    ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][i + 1];
+	}
+}
+
+static bool minstrel_ht_txstat_valid(struct ssv62xx_tx_rate *rate)
+{
+	if (!rate->count)
+		return false;
+	if (rate->data_rate < 0)
+		return false;
+	return true;
+}
+
+void ssv6xxx_ht_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
+			       struct ssv_sta_rc_info *rc_sta)
+{
+	struct cfg_host_event *host_event;
+	struct firmware_rate_control_report_data *report_data;
+	struct ssv62xx_ht *mi;
+	struct minstrel_rate_stats *rate;
+	bool last = false;
+	int i = 0;
+	u16 report_ampdu_packets = 0;
+	unsigned long period;
+	host_event = (struct cfg_host_event *)skb->data;
+	report_data =
+	    (struct firmware_rate_control_report_data *)&host_event->dat[0];
+	if (host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) {
+		report_ampdu_packets = 1;
+	} else if (host_event->h_event == SOC_EVT_RC_MPDU_REPORT) {
+		report_data->ampdu_len = 1;
+		report_ampdu_packets = report_data->ampdu_len;
+	} else {
+		dev_warn(sc->dev, "rate control report handler got garbage\n");
+		return;
+	}
+	mi = &rc_sta->ht;
+	mi->ampdu_packets += report_ampdu_packets;
+	mi->ampdu_len += report_data->ampdu_len;
+	if (!mi->sample_wait && !mi->sample_tries && mi->sample_count > 0) {
+		mi->sample_wait = 16 + 2 * MINSTREL_TRUNC(mi->avg_ampdu_len);
+		mi->sample_tries = 2;
+		mi->sample_count--;
+	}
+	for (i = 0; !last; i++) {
+		last = (i == SSV62XX_TX_MAX_RATES - 1) ||
+		    !minstrel_ht_txstat_valid(&report_data->rates[i + 1]);
+		if (!minstrel_ht_txstat_valid(&report_data->rates[i]))
+			break;
+#ifdef RATE_CONTROL_DEBUG
+		if ((report_data->rates[i].data_rate < SSV62XX_RATE_MCS_INDEX)
+		    || (report_data->rates[i].data_rate >=
+			SSV62XX_RATE_MCS_GREENFIELD_INDEX)) {
+			dev_dbg
+			    (sc->dev, "[RC]ssv6xxx_ht_report_handler get error report rate[%d]\n",
+			     report_data->rates[i].data_rate);
+			break;
+		}
+#endif
+		rate =
+		    &mi->groups.
+		    rates[(report_data->rates[i].data_rate -
+			   SSV62XX_RATE_MCS_INDEX) % MCS_GROUP_RATES];
+		if (last)
+			rate->success += report_data->ampdu_ack_len;
+		rate->attempts +=
+		    report_data->rates[i].count * report_data->ampdu_len;
+	}
+	period = msecs_to_jiffies(SSV_RC_HT_INTERVAL / 2);
+	if (time_after(jiffies, mi->stats_update + period)) {
+		rate_control_ht_sample(mi, rc_sta);
+	}
+}
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
new file mode 100644
index 00000000000..275c3356e03
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_ht_rc.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_RC_HT_H_
+#define _SSV_RC_HT_H_
+#include "ssv_rc_common.h"
+#define MINSTREL_SCALE 16
+#define MINSTREL_FRAC(val,div) (((val) << MINSTREL_SCALE) / div)
+#define MINSTREL_TRUNC(val) ((val) >> MINSTREL_SCALE)
+#define SSV_RC_HT_INTERVAL 100
+extern const u16 ampdu_max_transmit_length[];
+s32 ssv62xx_ht_rate_update(struct sk_buff *skb, struct ssv_softc *sc,
+			   struct fw_rc_retry_params *ar);
+void ssv62xx_ht_rc_caps(const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13],
+			struct ssv_sta_rc_info *rc_sta);
+void ssv6xxx_ht_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
+			       struct ssv_sta_rc_info *rc_sta);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_pm.c b/drivers/net/wireless/ssv6051/smac/ssv_pm.c
new file mode 100644
index 00000000000..fc3be2013f6
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_pm.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <ssv6200.h>
+#include "dev.h"
+#include "sar.h"
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_pm.h b/drivers/net/wireless/ssv6051/smac/ssv_pm.h
new file mode 100644
index 00000000000..9be260dd904
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_pm.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_PM_H_
+#define _SSV_PM_H_
+#include <linux/version.h>
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc.c b/drivers/net/wireless/ssv6051/smac/ssv_rc.c
new file mode 100644
index 00000000000..796ff01494b
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_rc.c
@@ -0,0 +1,1716 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/version.h>
+#include <ssv6200.h>
+#include "dev.h"
+#include "ssv_ht_rc.h"
+#include "ssv_rc.h"
+#include "ssv_rc_common.h"
+static struct ssv_rc_rate ssv_11bgn_rate_table[] = {
+	[0] = {.rc_flags = RC_FLAG_LEGACY,
+	       .phy_type = WLAN_RC_PHY_CCK,
+	       .rate_kbps = 1000,
+	       .dot11_rate_idx = 0,
+	       .ctrl_rate_idx = 0,
+	       .hw_rate_idx = 0,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[1] = {.rc_flags = RC_FLAG_LEGACY,
+	       .phy_type = WLAN_RC_PHY_CCK,
+	       .rate_kbps = 2000,
+	       .dot11_rate_idx = 1,
+	       .ctrl_rate_idx = 1,
+	       .hw_rate_idx = 1,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[2] = {.rc_flags = RC_FLAG_LEGACY,
+	       .phy_type = WLAN_RC_PHY_CCK,
+	       .rate_kbps = 5500,
+	       .dot11_rate_idx = 2,
+	       .ctrl_rate_idx = 1,
+	       .hw_rate_idx = 2,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[3] = {.rc_flags = RC_FLAG_LEGACY,
+	       .phy_type = WLAN_RC_PHY_CCK,
+	       .rate_kbps = 11000,
+	       .dot11_rate_idx = 3,
+	       .ctrl_rate_idx = 1,
+	       .hw_rate_idx = 3,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[4] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
+	       .phy_type = WLAN_RC_PHY_CCK,
+	       .rate_kbps = 2000,
+	       .dot11_rate_idx = 1,
+	       .ctrl_rate_idx = 4,
+	       .hw_rate_idx = 4,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[5] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
+	       .phy_type = WLAN_RC_PHY_CCK,
+	       .rate_kbps = 5500,
+	       .dot11_rate_idx = 2,
+	       .ctrl_rate_idx = 4,
+	       .hw_rate_idx = 5,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[6] = {.rc_flags = RC_FLAG_LEGACY | RC_FLAG_SHORT_PREAMBLE,
+	       .phy_type = WLAN_RC_PHY_CCK,
+	       .rate_kbps = 11000,
+	       .dot11_rate_idx = 3,
+	       .ctrl_rate_idx = 4,
+	       .hw_rate_idx = 6,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[7] = {.rc_flags = RC_FLAG_LEGACY,
+	       .phy_type = WLAN_RC_PHY_OFDM,
+	       .rate_kbps = 6000,
+	       .dot11_rate_idx = 4,
+	       .ctrl_rate_idx = 7,
+	       .hw_rate_idx = 7,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[8] = {.rc_flags = RC_FLAG_LEGACY,
+	       .phy_type = WLAN_RC_PHY_OFDM,
+	       .rate_kbps = 9000,
+	       .dot11_rate_idx = 5,
+	       .ctrl_rate_idx = 7,
+	       .hw_rate_idx = 8,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[9] = {.rc_flags = RC_FLAG_LEGACY,
+	       .phy_type = WLAN_RC_PHY_OFDM,
+	       .rate_kbps = 12000,
+	       .dot11_rate_idx = 6,
+	       .ctrl_rate_idx = 9,
+	       .hw_rate_idx = 9,
+	       .arith_shift = 8,
+	       .target_pf = 26,
+	       },
+	[10] = {.rc_flags = RC_FLAG_LEGACY,
+		.phy_type = WLAN_RC_PHY_OFDM,
+		.rate_kbps = 18000,
+		.dot11_rate_idx = 7,
+		.ctrl_rate_idx = 9,
+		.hw_rate_idx = 10,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[11] = {.rc_flags = RC_FLAG_LEGACY,
+		.phy_type = WLAN_RC_PHY_OFDM,
+		.rate_kbps = 24000,
+		.dot11_rate_idx = 8,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 11,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[12] = {.rc_flags = RC_FLAG_LEGACY,
+		.phy_type = WLAN_RC_PHY_OFDM,
+		.rate_kbps = 36000,
+		.dot11_rate_idx = 9,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 12,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[13] = {.rc_flags = RC_FLAG_LEGACY,
+		.phy_type = WLAN_RC_PHY_OFDM,
+		.rate_kbps = 48000,
+		.dot11_rate_idx = 10,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 13,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[14] = {.rc_flags = RC_FLAG_LEGACY,
+		.phy_type = WLAN_RC_PHY_OFDM,
+		.rate_kbps = 54000,
+		.dot11_rate_idx = 11,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 14,
+		.arith_shift = 8,
+		.target_pf = 8},
+	[15] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 6500,
+		.dot11_rate_idx = 0,
+		.ctrl_rate_idx = 7,
+		.hw_rate_idx = 15,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[16] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 13000,
+		.dot11_rate_idx = 1,
+		.ctrl_rate_idx = 9,
+		.hw_rate_idx = 16,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[17] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 19500,
+		.dot11_rate_idx = 2,
+		.ctrl_rate_idx = 9,
+		.hw_rate_idx = 17,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[18] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 26000,
+		.dot11_rate_idx = 3,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 18,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[19] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 39000,
+		.dot11_rate_idx = 4,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 19,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[20] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 52000,
+		.dot11_rate_idx = 5,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 20,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[21] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 58500,
+		.dot11_rate_idx = 6,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 21,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[22] = {.rc_flags = RC_FLAG_HT,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_LGI,
+		.rate_kbps = 65000,
+		.dot11_rate_idx = 7,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 22,
+		.arith_shift = 8,
+		.target_pf = 8},
+	[23] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 7200,
+		.dot11_rate_idx = 0,
+		.ctrl_rate_idx = 7,
+		.hw_rate_idx = 23,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[24] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 14400,
+		.dot11_rate_idx = 1,
+		.ctrl_rate_idx = 9,
+		.hw_rate_idx = 24,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[25] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 21700,
+		.dot11_rate_idx = 2,
+		.ctrl_rate_idx = 9,
+		.hw_rate_idx = 25,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[26] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 28900,
+		.dot11_rate_idx = 3,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 26,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[27] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 43300,
+		.dot11_rate_idx = 4,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 27,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[28] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 57800,
+		.dot11_rate_idx = 5,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 28,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[29] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 65000,
+		.dot11_rate_idx = 6,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 29,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[30] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_SGI,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_SGI,
+		.rate_kbps = 72200,
+		.dot11_rate_idx = 7,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 30,
+		.arith_shift = 8,
+		.target_pf = 8},
+	[31] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 6500,
+		.dot11_rate_idx = 0,
+		.ctrl_rate_idx = 7,
+		.hw_rate_idx = 31,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[32] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 13000,
+		.dot11_rate_idx = 1,
+		.ctrl_rate_idx = 9,
+		.hw_rate_idx = 32,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[33] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 19500,
+		.dot11_rate_idx = 2,
+		.ctrl_rate_idx = 9,
+		.hw_rate_idx = 33,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[34] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 26000,
+		.dot11_rate_idx = 3,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 34,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[35] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 39000,
+		.dot11_rate_idx = 4,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 35,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[36] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 52000,
+		.dot11_rate_idx = 5,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 36,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[37] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 58500,
+		.dot11_rate_idx = 6,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 37,
+		.arith_shift = 8,
+		.target_pf = 26,
+		},
+	[38] = {.rc_flags = RC_FLAG_HT | RC_FLAG_HT_GF,
+		.phy_type = WLAN_RC_PHY_HT_20_SS_GF,
+		.rate_kbps = 65000,
+		.dot11_rate_idx = 7,
+		.ctrl_rate_idx = 11,
+		.hw_rate_idx = 38,
+		.arith_shift = 8,
+		.target_pf = 8},
+};
+
+const u16 ssv6xxx_rc_rate_set[RC_TYPE_MAX][13] = {
+	[RC_TYPE_B_ONLY] = {4, 0, 1, 2, 3},
+	[RC_TYPE_LEGACY_GB] = {12, 0, 1, 2, 7, 8, 3, 9, 10, 11, 12, 13, 14},
+	[RC_TYPE_SGI_20] = {8, 23, 24, 25, 26, 27, 28, 29, 30},
+	[RC_TYPE_LGI_20] = {8, 15, 16, 17, 18, 19, 20, 21, 22},
+	[RC_TYPE_HT_SGI_20] = {8, 23, 24, 25, 26, 27, 28, 29, 30},
+	[RC_TYPE_HT_LGI_20] = {8, 15, 16, 17, 18, 19, 20, 21, 22},
+	[RC_TYPE_HT_GF] = {8, 31, 32, 33, 34, 35, 36, 37, 38},
+};
+
+static u32 ssv6xxx_rate_supported(struct ssv_sta_rc_info *rc_sta, u32 index)
+{
+	return (rc_sta->rc_supp_rates & BIT(index));
+}
+
+static u8 ssv6xxx_rate_lowest_index(struct ssv_sta_rc_info *rc_sta)
+{
+	int i;
+	for (i = 0; i < rc_sta->rc_num_rate; i++)
+		if (ssv6xxx_rate_supported(rc_sta, i))
+			return i;
+	return 0;
+}
+
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+static u8 ssv6xxx_rate_highest_index(struct ssv_sta_rc_info *rc_sta)
+{
+	int i;
+	for (i = rc_sta->rc_num_rate - 1; i >= 0; i--)
+		if (ssv6xxx_rate_supported(rc_sta, i))
+			return i;
+	return 0;
+}
+#endif
+static void rate_control_pid_adjust_rate(struct ssv_sta_rc_info *rc_sta,
+					 struct rc_pid_sta_info *spinfo,
+					 int adj, struct rc_pid_rateinfo *rinfo)
+{
+	int cur_sorted, new_sorted, probe, tmp, n_bitrates;
+	int cur = spinfo->txrate_idx;
+	n_bitrates = rc_sta->rc_num_rate;
+	cur_sorted = rinfo[cur].index;
+	new_sorted = cur_sorted + adj;
+	if (new_sorted < 0)
+		new_sorted = rinfo[0].index;
+	else if (new_sorted >= n_bitrates)
+		new_sorted = rinfo[n_bitrates - 1].index;
+	tmp = new_sorted;
+	if (adj < 0) {
+		for (probe = cur_sorted; probe >= new_sorted; probe--)
+			if (rinfo[probe].diff <= rinfo[cur_sorted].diff &&
+			    ssv6xxx_rate_supported(rc_sta, rinfo[probe].index))
+				tmp = probe;
+	} else {
+		for (probe = new_sorted + 1; probe < n_bitrates; probe++)
+			if (rinfo[probe].diff <= rinfo[new_sorted].diff &&
+			    ssv6xxx_rate_supported(rc_sta, rinfo[probe].index))
+				tmp = probe;
+	}
+	BUG_ON(tmp < 0 || tmp >= n_bitrates);
+	do {
+		if (ssv6xxx_rate_supported(rc_sta, rinfo[tmp].index)) {
+			spinfo->tmp_rate_idx = rinfo[tmp].index;
+			break;
+		}
+		if (adj < 0)
+			tmp--;
+		else
+			tmp++;
+	} while (tmp < n_bitrates && tmp >= 0);
+	spinfo->oldrate = spinfo->txrate_idx;
+	if (spinfo->tmp_rate_idx != spinfo->txrate_idx) {
+		spinfo->monitoring = 1;
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+		pr_debug("Trigger monitor tmp_rate_idx=[%d]\n",
+		       spinfo->tmp_rate_idx);
+#endif
+		spinfo->probe_cnt = MAXPROBES;
+	}
+}
+
+static void rate_control_pid_normalize(struct rc_pid_info *pinfo, int l)
+{
+	int i, norm_offset = RC_PID_NORM_OFFSET;
+	struct rc_pid_rateinfo *r = pinfo->rinfo;
+	if (r[0].diff > norm_offset)
+		r[0].diff -= norm_offset;
+	else if (r[0].diff < -norm_offset)
+		r[0].diff += norm_offset;
+	for (i = 0; i < l - 1; i++)
+		if (r[i + 1].diff > r[i].diff + norm_offset)
+			r[i + 1].diff -= norm_offset;
+		else if (r[i + 1].diff <= r[i].diff)
+			r[i + 1].diff += norm_offset;
+}
+
+#ifdef RATE_CONTROL_DEBUG
+unsigned int txrate_dlr = 0;
+#endif
+static void rate_control_pid_sample(struct ssv_rate_ctrl *ssv_rc,
+				    struct rc_pid_info *pinfo,
+				    struct ssv_sta_rc_info *rc_sta,
+				    struct rc_pid_sta_info *spinfo)
+{
+	struct rc_pid_rateinfo *rinfo = pinfo->rinfo;
+	u8 pf;
+	s32 err_avg;
+	s32 err_prop;
+	s32 err_int;
+	s32 err_der;
+	int adj, i, j, tmp;
+	struct ssv_rc_rate *rc_table;
+	unsigned int dlr;
+	unsigned int perfect_time = 0;
+	unsigned int this_thp, ewma_thp;
+	struct rc_pid_rateinfo *rate;
+	if (!spinfo->monitoring) {
+		if (spinfo->tx_num_xmit == 0)
+			return;
+		spinfo->last_sample = jiffies;
+		pf = spinfo->tx_num_failed * 100 / spinfo->tx_num_xmit;
+		if (pinfo->rinfo[spinfo->txrate_idx].this_attempt > 0) {
+			rate = &pinfo->rinfo[spinfo->txrate_idx];
+			rc_table = &ssv_rc->rc_table[spinfo->txrate_idx];
+			dlr = 100 - rate->this_fail * 100 / rate->this_attempt;
+			perfect_time = rate->perfect_tx_time;
+			if (!perfect_time)
+				perfect_time = 1000000;
+			this_thp = dlr * (1000000 / perfect_time);
+			ewma_thp = rate->throughput;
+			if (ewma_thp == 0)
+				rate->throughput = this_thp;
+			else
+				rate->throughput = (ewma_thp + this_thp) >> 1;
+			rate->attempt += rate->this_attempt;
+			rate->success += rate->this_success;
+			rate->fail += rate->this_fail;
+			spinfo->tx_num_xmit = 0;
+			spinfo->tx_num_failed = 0;
+			rate->this_fail = 0;
+			rate->this_success = 0;
+			rate->this_attempt = 0;
+			if (pinfo->oldrate < 0
+			    || pinfo->oldrate >= rc_sta->rc_num_rate) {
+				WARN_ON(1);
+			}
+			if (spinfo->txrate_idx < 0
+			    || spinfo->txrate_idx >= rc_sta->rc_num_rate) {
+				WARN_ON(1);
+			}
+			if (pinfo->oldrate != spinfo->txrate_idx) {
+				i = rinfo[pinfo->oldrate].index;
+				j = rinfo[spinfo->txrate_idx].index;
+				tmp = (pf - spinfo->last_pf);
+				tmp =
+				    RC_PID_DO_ARITH_RIGHT_SHIFT(tmp,
+								rc_table->arith_shift);
+				rinfo[j].diff = rinfo[i].diff + tmp;
+				pinfo->oldrate = spinfo->txrate_idx;
+			}
+			rate_control_pid_normalize(pinfo, rc_sta->rc_num_rate);
+			err_prop =
+			    (rc_table->target_pf - pf) << rc_table->arith_shift;
+			err_avg = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT;
+			spinfo->err_avg_sc =
+			    spinfo->err_avg_sc - err_avg + err_prop;
+			err_int = spinfo->err_avg_sc >> RC_PID_SMOOTHING_SHIFT;
+			err_der = pf - spinfo->last_pf;
+			spinfo->last_pf = pf;
+			spinfo->last_dlr = dlr;
+			spinfo->oldrate = spinfo->txrate_idx;
+			adj =
+			    (err_prop * RC_PID_COEFF_P +
+			     err_int * RC_PID_COEFF_I +
+			     err_der * RC_PID_COEFF_D);
+			adj =
+			    RC_PID_DO_ARITH_RIGHT_SHIFT(adj,
+							rc_table->arith_shift <<
+							1);
+			if (adj) {
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+				if ((spinfo->txrate_idx != 11)
+				    || ((spinfo->txrate_idx == 11)
+					&& (adj < 0)))
+					pr_debug
+					    ("[RC]Probe adjust[%d] dlr[%d%%] this_thp[%d] ewma_thp[%d] index[%d]\n",
+					     adj, dlr, this_thp, ewma_thp,
+					     spinfo->txrate_idx);
+#endif
+				rate_control_pid_adjust_rate(rc_sta, spinfo,
+							     adj, rinfo);
+			}
+		}
+	} else {
+		if ((spinfo->feedback_probes >= MAXPROBES)
+		    || (spinfo->feedback_probes && spinfo->probe_cnt)) {
+			rate = &pinfo->rinfo[spinfo->txrate_idx];
+			spinfo->last_sample = jiffies;
+			if (rate->this_attempt > 0) {
+				dlr =
+				    100 -
+				    rate->this_fail * 100 / rate->this_attempt;
+#ifdef RATE_CONTROL_DEBUG
+#ifdef PROBE
+				txrate_dlr = dlr;
+#endif
+#endif
+				spinfo->last_dlr = dlr;
+				perfect_time = rate->perfect_tx_time;
+				if (!perfect_time)
+					perfect_time = 1000000;
+				this_thp = dlr * (1000000 / perfect_time);
+				ewma_thp = rate->throughput;
+				if (ewma_thp == 0)
+					rate->throughput = this_thp;
+				else
+					rate->throughput =
+					    (ewma_thp + this_thp) >> 1;
+				rate->attempt += rate->this_attempt;
+				rate->success += rate->this_success;
+				rinfo[spinfo->txrate_idx].fail +=
+				    rate->this_fail;
+				rate->this_fail = 0;
+				rate->this_success = 0;
+				rate->this_attempt = 0;
+			} else {
+#ifdef RATE_CONTROL_DEBUG
+#ifdef PROBE
+				txrate_dlr = 0;
+#endif
+#endif
+			}
+			rate = &pinfo->rinfo[spinfo->tmp_rate_idx];
+			if (rate->this_attempt > 0) {
+				dlr =
+				    100 -
+				    ((rate->this_fail * 100) /
+				     rate->this_attempt);
+				{
+					perfect_time = rate->perfect_tx_time;
+					if (!perfect_time)
+						perfect_time = 1000000;
+					if (dlr)
+						this_thp =
+						    dlr * (1000000 /
+							   perfect_time);
+					else
+						this_thp = 0;
+					ewma_thp = rate->throughput;
+					if (ewma_thp == 0)
+						rate->throughput = this_thp;
+					else
+						rate->throughput =
+						    (ewma_thp + this_thp) >> 1;
+					if (rate->throughput >
+					    pinfo->rinfo[spinfo->
+							 txrate_idx].throughput)
+					{
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+						pr_debug
+						    ("[RC]UPDATE probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n",
+						     spinfo->tmp_rate_idx,
+						     rate->throughput, dlr,
+						     spinfo->txrate_idx,
+						     pinfo->
+						     rinfo
+						     [spinfo->txrate_idx].throughput,
+						     txrate_dlr,
+						     spinfo->feedback_probes);
+#endif
+						spinfo->txrate_idx =
+						    spinfo->tmp_rate_idx;
+					} else {
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+						pr_debug
+						    ("[RC]Fail probe rate idx[%d] [%d][%d%%] Old idx[%d] [%d][%d%%] feedback[%d] \n",
+						     spinfo->tmp_rate_idx,
+						     rate->throughput, dlr,
+						     spinfo->txrate_idx,
+						     pinfo->
+						     rinfo
+						     [spinfo->txrate_idx].throughput,
+						     txrate_dlr,
+						     spinfo->feedback_probes);
+#endif
+						;
+					}
+					rate->attempt += rate->this_attempt;
+					rate->success += rate->this_success;
+					rate->fail += rate->this_fail;
+					rate->this_fail = 0;
+					rate->this_success = 0;
+					rate->this_attempt = 0;
+					spinfo->oldrate = spinfo->txrate_idx;
+				}
+			}
+#ifdef RATE_CONTROL_DEBUG
+			else
+				pr_err("Unexpected error\n");
+#endif
+			spinfo->feedback_probes = 0;
+			spinfo->tx_num_xmit = 0;
+			spinfo->tx_num_failed = 0;
+			spinfo->monitoring = 0;
+#ifdef RATE_CONTROL_PARAMETER_DEBUG
+			pr_debug("Disable monitor\n");
+#endif
+			spinfo->probe_report_flag = 0;
+			spinfo->probe_wating_times = 0;
+		} else {
+			spinfo->probe_wating_times++;
+#ifdef RATE_CONTROL_DEBUG
+			if (spinfo->probe_wating_times > 3) {
+				pr_debug
+				    ("[RC]@@@@@ PROBE LOSE @@@@@ feedback=[%d] need=[%d] probe_cnt=[%d] wating times[%d]\n",
+				     spinfo->feedback_probes, MAXPROBES,
+				     spinfo->probe_cnt,
+				     spinfo->probe_wating_times);
+				spinfo->feedback_probes = 0;
+				spinfo->tx_num_xmit = 0;
+				spinfo->tx_num_failed = 0;
+				spinfo->monitoring = 0;
+				spinfo->probe_report_flag = 0;
+				spinfo->probe_wating_times = 0;
+			}
+#else
+			if (spinfo->probe_wating_times > 3) {
+				spinfo->feedback_probes = 0;
+				spinfo->tx_num_xmit = 0;
+				spinfo->tx_num_failed = 0;
+				spinfo->monitoring = 0;
+				spinfo->probe_report_flag = 0;
+				spinfo->probe_wating_times = 0;
+			}
+#endif
+		}
+	}
+}
+
+#ifdef RATE_CONTROL_PERCENTAGE_TRACE
+int percentage = 0;
+int percentageCounter = 0;
+#endif
+void ssv6xxx_legacy_report_handler(struct ssv_softc *sc, struct sk_buff *skb,
+				   struct ssv_sta_rc_info *rc_sta)
+{
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	struct cfg_host_event *host_event;
+	struct firmware_rate_control_report_data *report_data;
+	struct rc_pid_info *pinfo;
+	struct rc_pid_sta_info *spinfo;
+	struct rc_pid_rateinfo *pidrate;
+	struct rc_pid_rateinfo *rate;
+	s32 report_data_index = 0;
+	unsigned long period;
+	host_event = (struct cfg_host_event *)skb->data;
+	report_data =
+	    (struct firmware_rate_control_report_data *)&host_event->dat[0];
+	if ((report_data->wsid != (-1))
+	    && sc->sta_info[report_data->wsid].sta == NULL) {
+		dev_warn(sc->dev, "RC report has no valid STA.(%d)\n",
+			 report_data->wsid);
+		return;
+	}
+	pinfo = &rc_sta->pinfo;
+	spinfo = &rc_sta->spinfo;
+	pidrate = rc_sta->pinfo.rinfo;
+	if (host_event->h_event == SOC_EVT_RC_AMPDU_REPORT) {
+		period = msecs_to_jiffies(HT_RC_UPDATE_INTERVAL);
+		if (time_after(jiffies, spinfo->last_sample + period)) {
+			if (rc_sta->rc_num_rate == 12)
+				spinfo->txrate_idx = rc_sta->ht.max_tp_rate + 4;
+			else
+				spinfo->txrate_idx = rc_sta->ht.max_tp_rate;
+#ifdef RATE_CONTROL_DEBUG
+			pr_debug("MPDU rate update time txrate_idx[%d]!!\n",
+			       spinfo->txrate_idx);
+#endif
+			spinfo->last_sample = jiffies;
+		}
+		return;
+	} else if (host_event->h_event == SOC_EVT_RC_MPDU_REPORT) {
+		;
+	} else {
+		dev_warn(sc->dev, "RC report handler got garbage\n");
+		return;
+	}
+	if (report_data->rates[0].data_rate < 7) {
+		if (report_data->rates[0].data_rate > 3) {
+			report_data->rates[0].data_rate -= 3;
+		}
+	}
+	if (ssv_rc->
+	    rc_table[rc_sta->pinfo.rinfo[spinfo->txrate_idx].
+		     rc_index].hw_rate_idx == report_data->rates[0].data_rate) {
+		report_data_index =
+		    rc_sta->pinfo.rinfo[spinfo->txrate_idx].index;
+	} else
+	    if (ssv_rc->rc_table
+		[rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].
+		 rc_index].hw_rate_idx == report_data->rates[0].data_rate) {
+		report_data_index =
+		    rc_sta->pinfo.rinfo[spinfo->tmp_rate_idx].index;
+	}
+	if ((report_data_index != spinfo->tmp_rate_idx)
+	    && (report_data_index != spinfo->txrate_idx)) {
+#ifdef RATE_CONTROL_DEBUG
+		dev_dbg
+		    (sc->dev, "Rate control report mismatch report_rate_idx[%d] tmp_rate_idx[%d]rate[%d] txrate_idx[%d]rate[%d]!!\n",
+		     report_data->rates[0].data_rate, spinfo->tmp_rate_idx,
+		     ssv_rc->rc_table[rc_sta->pinfo.
+				      rinfo[spinfo->tmp_rate_idx].rc_index].
+		     hw_rate_idx, spinfo->txrate_idx,
+		     ssv_rc->rc_table[rc_sta->pinfo.
+				      rinfo[spinfo->txrate_idx].rc_index].
+		     hw_rate_idx);
+#endif
+		return;
+	}
+	if (report_data_index == spinfo->txrate_idx) {
+		spinfo->tx_num_xmit += report_data->rates[0].count;
+		spinfo->tx_num_failed +=
+		    (report_data->rates[0].count - report_data->ampdu_ack_len);
+		rate = &pidrate[spinfo->txrate_idx];
+		rate->this_fail +=
+		    (report_data->rates[0].count - report_data->ampdu_ack_len);
+		rate->this_attempt += report_data->rates[0].count;
+		rate->this_success += report_data->ampdu_ack_len;
+	}
+	if (report_data_index != spinfo->txrate_idx
+	    && report_data_index == spinfo->tmp_rate_idx) {
+		spinfo->feedback_probes += report_data->ampdu_len;
+		rate = &pidrate[spinfo->tmp_rate_idx];
+		rate->this_fail +=
+		    (report_data->rates[0].count - report_data->ampdu_ack_len);
+		rate->this_attempt += report_data->rates[0].count;
+		rate->this_success += report_data->ampdu_ack_len;
+	}
+	period = msecs_to_jiffies(RC_PID_INTERVAL);
+	if (time_after(jiffies, spinfo->last_sample + period)) {
+#ifdef RATE_CONTROL_PERCENTAGE_TRACE
+		rate = &pidrate[spinfo->txrate_idx];
+		if (rate->this_success > rate->this_attempt) {
+			dev_dbg(sc->dev, "this_success[%ld] this_attempt[%ld]\n",
+			       rate->this_success, rate->this_attempt);
+		} else {
+			if (percentage == 0)
+				percentage =
+				    (int)((rate->this_success * 100) /
+					  rate->this_attempt);
+			else
+				percentage =
+				    (percentage +
+				     (int)((rate->this_success * 100) /
+					   rate->this_attempt)) / 2;
+			deb_dbg(sc->dev, "Percentage[%d]\n", percentage);
+			if ((percentageCounter % 16) == 1)
+				percentage = 0;
+		}
+#endif
+#ifdef RATE_CONTROL_STUPID_DEBUG
+		if (spinfo->txrate_idx != spinfo->tmp_rate_idx) {
+			rate = &pidrate[spinfo->tmp_rate_idx];
+			if (spinfo->monitoring && ((rate->this_attempt == 0)
+						   || (rate->this_attempt !=
+						       MAXPROBES))) {
+				dev_dbg(sc->dev, "Probe result a[%ld]s[%ld]f[%ld]",
+				       rate->this_attempt, rate->this_success,
+				       rate->this_fail);
+			}
+			rate = &pidrate[spinfo->txrate_idx];
+			dev_dbg(sc->dev, "New a[%ld]s[%ld]f[%ld] \n", rate->this_attempt,
+			       rate->this_success, rate->this_fail);
+		} else {
+			rate = &pidrate[spinfo->txrate_idx];
+			dev_dbg(sc->dev, "New a[%ld]s[%ld]f[%ld] \n", rate->this_attempt,
+			       rate->this_success, rate->this_fail);
+		}
+		dev_dbg(sc->dev, "w[%d]x%03d-f%03d\n", rc_sta->rc_wsid,
+		       spinfo->tx_num_xmit, spinfo->tx_num_failed);
+#endif
+		rate_control_pid_sample(sc->rc, pinfo, rc_sta, spinfo);
+	}
+}
+
+void ssv6xxx_sample_work(struct work_struct *work)
+{
+	struct ssv_softc *sc =
+	    container_of(work, struct ssv_softc, rc_sample_work);
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	struct sk_buff *skb;
+	struct cfg_host_event *host_event;
+	struct ssv_sta_rc_info *rc_sta = NULL;
+	struct firmware_rate_control_report_data *report_data;
+	struct ssv_sta_info *ssv_sta;
+	u8 hw_wsid = 0;
+	sc->rc_sample_sechedule = 1;
+	while (1) {
+		skb = skb_dequeue(&sc->rc_report_queue);
+		if (skb == NULL)
+			break;
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+		{
+			dev_kfree_skb_any(skb);
+			continue;
+		}
+#endif
+		host_event = (struct cfg_host_event *)skb->data;
+		if ((host_event->h_event == SOC_EVT_RC_AMPDU_REPORT)
+		    || (host_event->h_event == SOC_EVT_RC_MPDU_REPORT)) {
+			report_data =
+			    (struct firmware_rate_control_report_data *)
+			    &host_event->dat[0];
+			hw_wsid = report_data->wsid;
+		} else {
+			dev_warn(sc->dev, "rate control sampling got garbage\n");
+			dev_kfree_skb_any(skb);
+			continue;
+		}
+		if (hw_wsid >= SSV_RC_MAX_HARDWARE_SUPPORT) {
+#ifdef RATE_CONTROL_DEBUG
+			dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-0!!\n");
+#endif
+			dev_kfree_skb_any(skb);
+			continue;
+		}
+		ssv_sta = &sc->sta_info[hw_wsid];
+		if (ssv_sta->sta == NULL) {
+			dev_err(sc->dev, "Null STA %d for RC report.\n",
+				hw_wsid);
+			rc_sta = NULL;
+		} else {
+			struct ssv_sta_priv_data *ssv_sta_priv =
+			    (struct ssv_sta_priv_data *)ssv_sta->sta->drv_priv;
+			rc_sta = &ssv_rc->sta_rc_info[ssv_sta_priv->rc_idx];
+			if (rc_sta->rc_wsid != hw_wsid) {
+				rc_sta = NULL;
+			}
+		}
+		if (rc_sta == NULL) {
+			dev_err(sc->dev,
+				"[RC]rc_sta is NULL pointer Check-1!!\n");
+			dev_kfree_skb_any(skb);
+			continue;
+		}
+		if (rc_sta == NULL) {
+#ifdef RATE_CONTROL_DEBUG
+			dev_dbg(sc->dev, "[RC]rc_sta is NULL pointer Check-2!!\n");
+#endif
+			dev_kfree_skb_any(skb);
+			continue;
+		}
+		if (rc_sta->is_ht) {
+			ssv6xxx_legacy_report_handler(sc, skb, rc_sta);
+			ssv6xxx_ht_report_handler(sc, skb, rc_sta);
+		} else
+			ssv6xxx_legacy_report_handler(sc, skb, rc_sta);
+		dev_kfree_skb_any(skb);
+	}
+	sc->rc_sample_sechedule = 0;
+}
+
+static void ssv6xxx_tx_status(void *priv,
+			      struct ieee80211_supported_band *sband,
+			      struct ieee80211_sta *sta, void *priv_sta,
+			      struct sk_buff *skb)
+{
+	struct ssv_softc *sc;
+	struct ieee80211_hdr *hdr;
+	__le16 fc;
+	hdr = (struct ieee80211_hdr *)skb->data;
+	fc = hdr->frame_control;
+	if (!priv_sta || !ieee80211_is_data_qos(fc))
+		return;
+	sc = (struct ssv_softc *)priv;
+	if (conf_is_ht(&sc->hw->conf)
+	    && (!(skb->protocol == cpu_to_be16(ETH_P_PAE)))) {
+		if (skb_get_queue_mapping(skb) != IEEE80211_AC_VO)
+			ssv6200_ampdu_tx_update_state(priv, sta, skb);
+	}
+	return;
+}
+
+static void rateControlGetRate(u8 rateIndex, char *pointer)
+{
+	switch (rateIndex) {
+	case 0:
+		sprintf(pointer, "1Mbps");
+		return;
+	case 1:
+	case 4:
+		sprintf(pointer, "2Mbps");
+		return;
+	case 2:
+	case 5:
+		sprintf(pointer, "5.5Mbps");
+		return;
+	case 3:
+	case 6:
+		sprintf(pointer, "11Mbps");
+		return;
+	case 7:
+		sprintf(pointer, "6Mbps");
+		return;
+	case 8:
+		sprintf(pointer, "9Mbps");
+		return;
+	case 9:
+		sprintf(pointer, "12Mbps");
+		return;
+	case 10:
+		sprintf(pointer, "18Mbps");
+		return;
+	case 11:
+		sprintf(pointer, "24Mbps");
+		return;
+	case 12:
+		sprintf(pointer, "36Mbps");
+		return;
+	case 13:
+		sprintf(pointer, "48Mbps");
+		return;
+	case 14:
+		sprintf(pointer, "54Mbps");
+		return;
+	case 15:
+	case 31:
+		sprintf(pointer, "MCS0-l");
+		return;
+	case 16:
+	case 32:
+		sprintf(pointer, "MCS1-l");
+		return;
+	case 17:
+	case 33:
+		sprintf(pointer, "MCS2-l");
+		return;
+	case 18:
+	case 34:
+		sprintf(pointer, "MCS3-l");
+		return;
+	case 19:
+	case 35:
+		sprintf(pointer, "MCS4-l");
+		return;
+	case 20:
+	case 36:
+		sprintf(pointer, "MCS5-l");
+		return;
+	case 21:
+	case 37:
+		sprintf(pointer, "MCS6-l");
+		return;
+	case 22:
+	case 38:
+		sprintf(pointer, "MCS7-l");
+		return;
+	case 23:
+		sprintf(pointer, "MCS0-s");
+		return;
+	case 24:
+		sprintf(pointer, "MCS1-s");
+		return;
+	case 25:
+		sprintf(pointer, "MCS2-s");
+		return;
+	case 26:
+		sprintf(pointer, "MCS3-s");
+		return;
+	case 27:
+		sprintf(pointer, "MCS4-s");
+		return;
+	case 28:
+		sprintf(pointer, "MCS5-s");
+		return;
+	case 29:
+		sprintf(pointer, "MCS6-s");
+		return;
+	case 30:
+		sprintf(pointer, "MCS7-s");
+		return;
+	default:
+		sprintf(pointer, "Unknow");
+		return;
+	};
+}
+
+static void ssv6xxx_get_rate(void *priv, struct ieee80211_sta *sta,
+			     void *priv_sta,
+			     struct ieee80211_tx_rate_control *txrc)
+{
+	struct ssv_softc *sc = priv;
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	struct ssv_sta_rc_info *rc_sta = priv_sta;
+	struct sk_buff *skb = txrc->skb;
+	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+	struct ieee80211_tx_rate *rates = tx_info->control.rates;
+	struct rc_pid_sta_info *spinfo = &rc_sta->spinfo;
+	struct ssv_rc_rate *rc_rate = NULL;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	int rateidx = 99;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(5,2,0)
+	if (rate_control_send_low(sta, priv_sta, txrc)) {
+		int i = 0;
+		int total_rates =
+		    (sizeof(ssv_11bgn_rate_table) /
+		     sizeof(ssv_11bgn_rate_table[0]));
+#if 1
+		if ((txrc->rate_idx_mask & (1 << rates[0].idx)) == 0) {
+			u32 rate_idx = rates[0].idx + 1;
+			u32 rate_idx_mask = txrc->rate_idx_mask >> rate_idx;
+			while (rate_idx_mask && (rate_idx_mask & 1) == 0) {
+				rate_idx_mask >>= 1;
+				rate_idx++;
+			}
+			if (rate_idx_mask)
+				rates[0].idx = rate_idx;
+			else {
+				WARN_ON(rate_idx_mask == 0);
+			}
+		}
+#endif
+		for (i = 0; i < total_rates; i++) {
+			if (rates[0].idx ==
+			    ssv_11bgn_rate_table[i].dot11_rate_idx) {
+				break;
+			}
+		}
+		if (i < total_rates)
+			rc_rate = &ssv_rc->rc_table[i];
+		else {
+			WARN_ON("Failed to find matching low rate.");
+		}
+	}
+#endif
+	if (rc_rate == NULL) {
+		if (conf_is_ht(&sc->hw->conf) &&
+		    (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING))
+			tx_info->flags |= IEEE80211_TX_CTL_LDPC;
+		if (conf_is_ht(&sc->hw->conf) &&
+		    (sta->ht_cap.cap & IEEE80211_HT_CAP_TX_STBC))
+			tx_info->flags |= (1 << IEEE80211_TX_CTL_STBC_SHIFT);
+		if (sc->sc_flags & SC_OP_FIXED_RATE) {
+			rateidx = sc->max_rate_idx;
+		} else {
+			if (rc_sta->rc_valid == false) {
+				rateidx = 0;
+			} else {
+				if ((rc_sta->rc_wsid >=
+				     SSV_RC_MAX_HARDWARE_SUPPORT)
+				    || (rc_sta->rc_wsid < 0)) {
+					ssv_sta_priv =
+					    (struct ssv_sta_priv_data *)
+					    sta->drv_priv;
+					{
+						if ((rc_sta->ht_rc_type >=
+						     RC_TYPE_HT_SGI_20)
+						    &&
+						    (ssv_sta_priv->rx_data_rate
+						     <
+						     SSV62XX_RATE_MCS_INDEX)) {
+							rateidx =
+							    rc_sta->
+							    pinfo.rinfo
+							    [spinfo->txrate_idx].rc_index;
+						} else {
+							rateidx =
+							    ssv_sta_priv->rx_data_rate;
+						}
+					}
+				} else {
+					if (rc_sta->is_ht) {
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+						rateidx =
+						    rc_sta->ht.
+						    groups.rates[MCS_GROUP_RATES
+								 - 1].rc_index;
+#else
+						rateidx =
+						    rc_sta->pinfo.
+						    rinfo
+						    [spinfo->txrate_idx].rc_index;
+#endif
+					} else {
+						{
+							BUG_ON
+							    (spinfo->txrate_idx
+							     >=
+							     rc_sta->rc_num_rate);
+							rateidx =
+							    rc_sta->
+							    pinfo.rinfo
+							    [spinfo->txrate_idx].rc_index;
+						}
+						if (rateidx < 4) {
+							if (rateidx) {
+								if ((sc->sc_flags & SC_OP_SHORT_PREAMBLE)
+								    ||
+								    (txrc->short_preamble))
+								{
+									rateidx
+									    +=
+									    3;
+								}
+							}
+						}
+					}
+				}
+			}
+		}
+		rc_rate = &ssv_rc->rc_table[rateidx];
+		if (spinfo->real_hw_index != rc_rate->hw_rate_idx) {
+			char string[24];
+			rateControlGetRate(rc_rate->hw_rate_idx, string);
+		}
+		spinfo->real_hw_index = rc_rate->hw_rate_idx;
+		rates[0].count = 4;
+		rates[0].idx = rc_rate->dot11_rate_idx;
+		tx_info->control.rts_cts_rate_idx =
+		    ssv_rc->rc_table[rc_rate->ctrl_rate_idx].dot11_rate_idx;
+		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
+			rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
+		if (rc_rate->rc_flags & RC_FLAG_HT) {
+			rates[0].flags |= IEEE80211_TX_RC_MCS;
+			if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
+				rates[0].flags |= IEEE80211_TX_RC_SHORT_GI;
+			if (rc_rate->rc_flags & RC_FLAG_HT_GF)
+				rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD;
+		}
+	}
+	rates[1].count = 0;
+	rates[1].idx = -1;
+	rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx;
+	rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx];
+	rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx;
+}
+
+int pide_frame_duration(size_t len, int rate, int short_preamble, int flags)
+{
+	int dur = 0;
+	if (flags == WLAN_RC_PHY_CCK) {
+		dur = 10;
+		dur += short_preamble ? (72 + 24) : (144 + 48);
+		dur += DIV_ROUND_UP(8 * (len + 4) * 10, rate);
+	} else {
+		dur = 16;
+		dur += 16;
+		dur += 4;
+		dur += 4 * DIV_ROUND_UP((16 + 8 * (len + 4) + 6) * 10,
+					4 * rate);
+	}
+	return dur;
+}
+
+static void ssv62xx_rc_caps(struct ssv_sta_rc_info *rc_sta)
+{
+	struct rc_pid_sta_info *spinfo;
+	struct rc_pid_info *pinfo;
+	struct rc_pid_rateinfo *rinfo;
+	int i;
+	spinfo = &rc_sta->spinfo;
+	pinfo = &rc_sta->pinfo;
+	memset(spinfo, 0, sizeof(struct rc_pid_sta_info));
+	memset(pinfo, 0, sizeof(struct rc_pid_info));
+	rinfo = rc_sta->pinfo.rinfo;
+	for (i = 0; i < rc_sta->rc_num_rate; i++) {
+		rinfo[i].rc_index = ssv6xxx_rc_rate_set[rc_sta->rc_type][i + 1];
+		rinfo[i].diff = i * RC_PID_NORM_OFFSET;
+		rinfo[i].index = (u16) i;
+		rinfo[i].perfect_tx_time =
+		    TDIFS + (TSLOT * 15 >> 1) + pide_frame_duration(1530,
+								    ssv_11bgn_rate_table
+								    [rinfo
+								     [i].rc_index].rate_kbps
+								    / 100, 1,
+								    ssv_11bgn_rate_table
+								    [rinfo
+								     [i].rc_index].phy_type)
+		    + pide_frame_duration(10,
+					  ssv_11bgn_rate_table[rinfo[i].
+							       rc_index].rate_kbps
+					  / 100, 1,
+					  ssv_11bgn_rate_table[rinfo[i].
+							       rc_index].phy_type);
+		pr_debug("[RC]Init perfect_tx_time[%d][%d]\n", i,
+		       rinfo[i].perfect_tx_time);
+		rinfo[i].throughput = 0;
+	}
+	if (rc_sta->is_ht) {
+		if (ssv6xxx_rc_rate_set[rc_sta->ht_rc_type][0] == 12)
+			spinfo->txrate_idx = 4;
+		else
+			spinfo->txrate_idx = 0;
+	} else {
+		spinfo->txrate_idx = ssv6xxx_rate_lowest_index(rc_sta);
+#ifdef DISABLE_RATE_CONTROL_SAMPLE
+		spinfo->txrate_idx = ssv6xxx_rate_highest_index(rc_sta);
+#endif
+	}
+	spinfo->real_hw_index = 0;
+	spinfo->probe_cnt = MAXPROBES;
+	spinfo->tmp_rate_idx = spinfo->txrate_idx;
+	spinfo->oldrate = spinfo->txrate_idx;
+	spinfo->last_sample = jiffies;
+	spinfo->last_report = jiffies;
+}
+
+static void ssv6xxx_rate_update_rc_type(void *priv,
+					struct ieee80211_supported_band *sband,
+					struct ieee80211_sta *sta,
+					void *priv_sta)
+{
+	struct ssv_softc *sc = priv;
+	struct ssv_hw *sh = sc->sh;
+	struct ssv_sta_rc_info *rc_sta = priv_sta;
+	int i;
+	u32 ht_supp_rates = 0;
+	BUG_ON(rc_sta->rc_valid == false);
+	dev_dbg(sc->dev, "[I] %s(): \n", __FUNCTION__);
+	rc_sta->ht_supp_rates = 0;
+	rc_sta->rc_supp_rates = 0;
+	rc_sta->is_ht = 0;
+#ifndef CONFIG_CH14_SUPPORT_GN_MODE
+	if (sc->cur_channel->hw_value == 14) {
+		dev_dbg(sc->dev, "[RC init ]Channel 14 support\n");
+		if ((sta->supp_rates[sband->band] & (~0xfL)) == 0x0) {
+			dev_dbg(sc->dev, "[RC init ]B only mode\n");
+			rc_sta->rc_type = RC_TYPE_B_ONLY;
+		} else {
+			dev_dbg(sc->dev, "[RC init ]GB mode\n");
+			rc_sta->rc_type = RC_TYPE_LEGACY_GB;
+		}
+	} else
+#endif
+	if (sta->ht_cap.ht_supported == true) {
+		dev_dbg(sc->dev, "[RC init ]HT support wsid\n");
+		for (i = 0; i < SSV_HT_RATE_MAX; i++) {
+			if (sta->ht_cap.mcs.rx_mask[i /
+						    MCS_GROUP_RATES] & (1 << (i
+									      %
+									      MCS_GROUP_RATES)))
+				ht_supp_rates |= BIT(i);
+		}
+		rc_sta->ht_supp_rates = ht_supp_rates;
+		if (sta->ht_cap.cap & IEEE80211_HT_CAP_GRN_FLD) {
+			rc_sta->rc_type = RC_TYPE_HT_GF;
+			rc_sta->ht_rc_type = RC_TYPE_HT_GF;
+		} else if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) {
+			rc_sta->rc_type = RC_TYPE_SGI_20;
+			rc_sta->ht_rc_type = RC_TYPE_HT_SGI_20;
+		} else {
+			rc_sta->rc_type = RC_TYPE_LGI_20;
+			rc_sta->ht_rc_type = RC_TYPE_HT_LGI_20;
+		}
+	} else {
+		if ((sta->supp_rates[sband->band] & (~0xfL)) == 0x0) {
+			rc_sta->rc_type = RC_TYPE_B_ONLY;
+			dev_dbg(sc->dev, "[RC init ]B only mode\n");
+		} else {
+			rc_sta->rc_type = RC_TYPE_LEGACY_GB;
+			dev_dbg(sc->dev, "[RC init ]legacy G mode\n");
+		}
+	}
+#ifdef CONFIG_SSV_DPD
+	if (rc_sta->rc_type == RC_TYPE_B_ONLY) {
+		SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3D3E84FE);
+		SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x1457D79);
+		SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x0);
+	} else {
+		SMAC_REG_WRITE(sh, ADR_TX_FE_REGISTER, 0x3CBE84FE);
+		SMAC_REG_WRITE(sh, ADR_RX_FE_REGISTER_1, 0x4507F9);
+		SMAC_REG_WRITE(sh, ADR_DPD_CONTROL, 0x3);
+	}
+#endif
+	if ((rc_sta->rc_type != RC_TYPE_B_ONLY)
+	    && (rc_sta->rc_type != RC_TYPE_LEGACY_GB)) {
+		if ((sta->ht_cap.ht_supported)
+		    && (sh->cfg.hw_caps & SSV6200_HW_CAP_AMPDU_TX)) {
+			rc_sta->is_ht = 1;
+			ssv62xx_ht_rc_caps(ssv6xxx_rc_rate_set, rc_sta);
+		}
+	}
+	{
+		rc_sta->rc_num_rate =
+		    (u8) ssv6xxx_rc_rate_set[rc_sta->rc_type][0];
+		if ((rc_sta->rc_type == RC_TYPE_HT_GF)
+		    || (rc_sta->rc_type == RC_TYPE_LGI_20)
+		    || (rc_sta->rc_type == RC_TYPE_SGI_20)) {
+			if (rc_sta->rc_num_rate == 12) {
+				rc_sta->rc_supp_rates =
+				    sta->supp_rates[sband->band] & 0xfL;
+				rc_sta->rc_supp_rates |= (ht_supp_rates << 4);
+			} else
+				rc_sta->rc_supp_rates = ht_supp_rates;
+		} else if (rc_sta->rc_type == RC_TYPE_LEGACY_GB)
+			rc_sta->rc_supp_rates = sta->supp_rates[sband->band];
+		else if (rc_sta->rc_type == RC_TYPE_B_ONLY)
+			rc_sta->rc_supp_rates =
+			    sta->supp_rates[sband->band] & 0xfL;
+		ssv62xx_rc_caps(rc_sta);
+	}
+}
+
+static void ssv6xxx_rate_update(void *priv,
+				struct ieee80211_supported_band *sband,
+				struct cfg80211_chan_def *chandef,
+				struct ieee80211_sta *sta, void *priv_sta,
+				u32 changed)
+{
+	pr_debug("%s: changed=%d\n", __FUNCTION__, changed);
+	return;
+}
+
+static void ssv6xxx_rate_init(void *priv,
+			      struct ieee80211_supported_band *sband,
+			      struct cfg80211_chan_def *chandef,
+			      struct ieee80211_sta *sta, void *priv_sta)
+{
+	ssv6xxx_rate_update_rc_type(priv, sband, sta, priv_sta);
+}
+
+static void *ssv6xxx_rate_alloc_sta(void *priv, struct ieee80211_sta *sta,
+				    gfp_t gfp)
+{
+	struct ssv_sta_priv_data *sta_priv =
+	    (struct ssv_sta_priv_data *)sta->drv_priv;
+#ifndef RC_STA_DIRECT_MAP
+	struct ssv_softc *sc = priv;
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	int s;
+	sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	for (s = 0; s < SSV_RC_MAX_STA; s++) {
+		if (ssv_rc->sta_rc_info[s].rc_valid == false) {
+			dev_dbg(sc->dev, "%s(): use index %d\n", __FUNCTION__, s);
+			memset(&ssv_rc->sta_rc_info[s], 0,
+			       sizeof(struct ssv_sta_rc_info));
+			ssv_rc->sta_rc_info[s].rc_valid = true;
+			ssv_rc->sta_rc_info[s].rc_wsid = -1;
+			sta_priv->rc_idx = s;
+			return &ssv_rc->sta_rc_info[s];
+		}
+	}
+	return NULL;
+#else
+	sta_priv->rc_idx = (-1);
+	return sta_priv;
+#endif
+}
+
+static void ssv6xxx_rate_free_sta(void *priv, struct ieee80211_sta *sta,
+				  void *priv_sta)
+{
+	struct ssv_sta_rc_info *rc_sta = priv_sta;
+	rc_sta->rc_valid = false;
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
+static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw)
+#else
+static void *ssv6xxx_rate_alloc(struct ieee80211_hw *hw,
+				struct dentry *debugfsdir)
+#endif
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ssv_rate_ctrl *ssv_rc;
+	sc->rc = kzalloc(sizeof(struct ssv_rate_ctrl), GFP_KERNEL);
+	if (!sc->rc) {
+		pr_err("%s(): Unable to allocate RC structure !\n",
+		       __FUNCTION__);
+		return NULL;
+	}
+	memset(sc->rc, 0, sizeof(struct ssv_rate_ctrl));
+	ssv_rc = (struct ssv_rate_ctrl *)sc->rc;
+	ssv_rc->rc_table = ssv_11bgn_rate_table;
+	skb_queue_head_init(&sc->rc_report_queue);
+	INIT_WORK(&sc->rc_sample_work, ssv6xxx_sample_work);
+	sc->rc_sample_workqueue = create_workqueue("ssv6xxx_rc_sample");
+	sc->rc_sample_sechedule = 0;
+	return hw->priv;
+}
+
+static void ssv6xxx_rate_free(void *priv)
+{
+	struct ssv_softc *sc = priv;
+	if (sc->rc) {
+		kfree(sc->rc);
+		sc->rc = NULL;
+	}
+	sc->rc_sample_sechedule = 0;
+	cancel_work_sync(&sc->rc_sample_work);
+	flush_workqueue(sc->rc_sample_workqueue);
+	destroy_workqueue(sc->rc_sample_workqueue);
+}
+
+static struct rate_control_ops ssv_rate_ops = {
+	.name = "ssv6xxx_rate_control",
+	.tx_status = ssv6xxx_tx_status,
+	.get_rate = ssv6xxx_get_rate,
+	.rate_init = ssv6xxx_rate_init,
+	.rate_update = ssv6xxx_rate_update,
+	.alloc = ssv6xxx_rate_alloc,
+	.free = ssv6xxx_rate_free,
+	.alloc_sta = ssv6xxx_rate_alloc_sta,
+	.free_sta = ssv6xxx_rate_free_sta,
+};
+
+void ssv6xxx_rc_mac8011_rate_idx(struct ssv_softc *sc,
+				 int hw_rate_idx,
+				 struct ieee80211_rx_status *rxs)
+{
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	struct ssv_rc_rate *rc_rate;
+	BUG_ON(hw_rate_idx >= RATE_TABLE_SIZE && hw_rate_idx < 0);
+	rc_rate = &ssv_rc->rc_table[hw_rate_idx];
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)
+	if (rc_rate->rc_flags & RC_FLAG_HT) {
+		rxs->flag |= RC_FLAG_HT;
+		if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
+			rxs->flag |= RX_ENC_FLAG_SHORT_GI;
+	} else {
+		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
+			rxs->flag |= RX_ENC_FLAG_SHORTPRE;
+	}
+#else
+	if (rc_rate->rc_flags & RC_FLAG_HT) {
+		rxs->flag |= RC_FLAG_HT;
+		if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
+			rxs->flag |= RX_FLAG_SHORT_GI;
+	} else {
+		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
+			rxs->flag |= RX_FLAG_SHORTPRE;
+	}
+#endif
+	rxs->rate_idx = rc_rate->dot11_rate_idx;
+}
+
+void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,
+			    struct ieee80211_tx_info *info,
+			    struct ssv_rate_info *sr)
+{
+	struct ieee80211_tx_rate *tx_rate;
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	tx_rate = &info->control.rates[0];
+	sr->d_flags =
+	    (ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].phy_type ==
+	     WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G : 0;
+	sr->d_flags |=
+	    (ssv_rc->
+	     rc_table[tx_rate[SSV_DRATE_IDX].
+		      count].rc_flags & RC_FLAG_SHORT_PREAMBLE) ?
+	    IEEE80211_RATE_SHORT_PREAMBLE : 0;
+	sr->c_flags =
+	    (ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].phy_type ==
+	     WLAN_RC_PHY_OFDM) ? IEEE80211_RATE_ERP_G : 0;
+	sr->c_flags |=
+	    (ssv_rc->
+	     rc_table[tx_rate[SSV_CRATE_IDX].
+		      count].rc_flags & RC_FLAG_SHORT_PREAMBLE) ?
+	    IEEE80211_RATE_SHORT_PREAMBLE : 0;
+	sr->drate_kbps =
+	    ssv_rc->rc_table[tx_rate[SSV_DRATE_IDX].count].rate_kbps;
+	sr->drate_hw_idx = tx_rate[SSV_DRATE_IDX].count;
+	sr->crate_kbps =
+	    ssv_rc->rc_table[tx_rate[SSV_CRATE_IDX].count].rate_kbps;
+	sr->crate_hw_idx = tx_rate[SSV_CRATE_IDX].count;
+}
+
+u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc,
+				   u32 do_rts_cts)
+{
+	int ret = 0;
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+	struct SKB_info_st *skb_info = (struct SKB_info_st *)skb->head;
+	struct ieee80211_sta *sta = skb_info->sta;
+	struct ieee80211_tx_rate *rates = &tx_info->control.rates[0];
+	struct ssv_rc_rate *rc_rate = NULL;
+	u8 rateidx = 0;
+	struct ssv_sta_rc_info *rc_sta = NULL;
+	struct rc_pid_sta_info *spinfo;
+	struct ssv_sta_priv_data *sta_priv = NULL;
+	unsigned long period = 0;
+	if (sc->sc_flags & SC_OP_FIXED_RATE)
+		return ret;
+	if (sta == NULL)
+		return ret;
+	sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	if (sta_priv == NULL) {
+#ifdef RATE_CONTROL_DEBUG
+		dev_dbg(rc->dev, "%s sta_priv == NULL \n\r", __FUNCTION__);
+#endif
+		return ret;
+	}
+	if ((sta_priv->rc_idx < 0) || (sta_priv->rc_idx >= SSV_RC_MAX_STA)) {
+#ifdef RATE_CONTROL_DEBUG
+		dev_dbg(sc->dev, "%s rc_idx %x illegal \n\r", __FUNCTION__,
+		       sta_priv->rc_idx);
+#endif
+		return ret;
+	}
+	rc_sta = &ssv_rc->sta_rc_info[sta_priv->rc_idx];
+	if (rc_sta->rc_valid == false) {
+#ifdef RATE_CONTROL_DEBUG
+		dev_dbg(sc->dev, "%s rc_valid false \n\r", __FUNCTION__);
+#endif
+		return ret;
+	}
+	spinfo = &rc_sta->spinfo;
+	period = msecs_to_jiffies(RC_PID_REPORT_INTERVAL);
+	if (time_after(jiffies, spinfo->last_report + period)) {
+		ret |= RC_FIRMWARE_REPORT_FLAG;
+		spinfo->last_report = jiffies;
+	}
+	{
+		if (spinfo->monitoring) {
+			if (spinfo->probe_report_flag == 0) {
+				ret |= RC_FIRMWARE_REPORT_FLAG;
+				spinfo->last_report = jiffies;
+				spinfo->probe_report_flag = 1;
+				rateidx = spinfo->real_hw_index;
+			} else if (spinfo->probe_cnt > 0
+				   && spinfo->probe_report_flag) {
+				rateidx =
+				    rc_sta->pinfo.rinfo[spinfo->
+							tmp_rate_idx].rc_index;
+				spinfo->probe_cnt--;
+				if (spinfo->probe_cnt == 0) {
+					ret |= RC_FIRMWARE_REPORT_FLAG;
+					spinfo->last_report = jiffies;
+				}
+			} else
+				rateidx = spinfo->real_hw_index;
+		} else
+			rateidx = spinfo->real_hw_index;
+	}
+	if (rateidx >= RATE_TABLE_SIZE) {
+		dev_err(sc->dev, "rateidx over range\n");
+		return 0;
+	}
+	rc_rate = &ssv_rc->rc_table[rateidx];
+#ifdef RATE_CONTROL_STUPID_DEBUG
+	if (spinfo->monitoring && (spinfo->probe_cnt)) {
+		char string[24];
+		rateControlGetRate(rc_rate->hw_rate_idx, string);
+		dev_dbg(sc->dev, "[RC]Probe rate[%s]\n", string);
+	}
+#endif
+	if (rc_rate == NULL)
+		return ret;
+	if (rc_rate->hw_rate_idx != rates[SSV_DRATE_IDX].count) {
+		rates[0].flags = 0;
+		if (rc_rate->rc_flags & RC_FLAG_SHORT_PREAMBLE)
+			rates[0].flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
+		if (rc_rate->rc_flags & RC_FLAG_HT) {
+			rates[0].flags |= IEEE80211_TX_RC_MCS;
+			if (rc_rate->rc_flags & RC_FLAG_HT_SGI)
+				rates[0].flags |= IEEE80211_TX_RC_SHORT_GI;
+			if (rc_rate->rc_flags & RC_FLAG_HT_GF)
+				rates[0].flags |= IEEE80211_TX_RC_GREEN_FIELD;
+		}
+		rates[SSV_DRATE_IDX].count = rc_rate->hw_rate_idx;
+		if (do_rts_cts & IEEE80211_TX_RC_USE_CTS_PROTECT) {
+			rates[SSV_CRATE_IDX].count = 0;
+		} else {
+			rc_rate = &ssv_rc->rc_table[rc_rate->ctrl_rate_idx];
+			rates[SSV_CRATE_IDX].count = rc_rate->hw_rate_idx;
+		}
+		ret |= 0x1;
+	}
+	return ret;
+}
+
+void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx)
+{
+	struct ssv_rate_ctrl *ssv_rc = sc->rc;
+	struct ssv_sta_rc_info *rc_sta;
+	u32 rc_hw_reg[] = { ADR_MTX_MIB_WSID0, ADR_MTX_MIB_WSID1 };
+	BUG_ON(rc_idx >= SSV_RC_MAX_STA);
+	rc_sta = &ssv_rc->sta_rc_info[rc_idx];
+	if (hwidx >= 0 && hwidx < SSV_NUM_HW_STA) {
+		rc_sta->rc_wsid = hwidx;
+		dev_dbg(sc->dev, "rc_wsid[%d] rc_idx[%d]\n", rc_sta[rc_idx].rc_wsid,
+		       rc_idx);
+		SMAC_REG_WRITE(sc->sh, rc_hw_reg[hwidx], 0x40000000);
+	} else {
+		rc_sta->rc_wsid = -1;
+	}
+}
+
+#define UPDATE_PHY_INFO_ACK_RATE(_phy_info,_ack_rate_idx) ( _phy_info = (_phy_info&0xfffffc0f)|(_ack_rate_idx<<4))
+int ssv6xxx_rc_update_bmode_ctrl_rate(struct ssv_softc *sc, int rate_tbl_idx,
+				      int ctrl_rate_idx)
+{
+	u32 temp32;
+	struct ssv_hw *sh = sc->sh;
+	u32 addr;
+	addr = sh->hw_pinfo + rate_tbl_idx * 4;
+	ssv_11bgn_rate_table[rate_tbl_idx].ctrl_rate_idx = ctrl_rate_idx;
+	SMAC_REG_READ(sh, addr, &temp32);
+	UPDATE_PHY_INFO_ACK_RATE(temp32, ctrl_rate_idx);
+	SMAC_REG_WRITE(sh, addr, temp32);
+	SMAC_REG_CONFIRM(sh, addr, temp32);
+	return 0;
+}
+
+void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates)
+{
+	int i;
+	int rate_idx, pre_rate_idx = 0;
+	for (i = 0; i < 4; i++) {
+		if (((basic_rates >> i) & 0x01)) {
+			rate_idx = i;
+			pre_rate_idx = i;
+		} else
+			rate_idx = pre_rate_idx;
+		ssv6xxx_rc_update_bmode_ctrl_rate(sc, i, rate_idx);
+		if (i)
+			ssv6xxx_rc_update_bmode_ctrl_rate(sc, i + 3, rate_idx);
+	}
+}
+
+int ssv6xxx_rate_control_register(void)
+{
+	return ieee80211_rate_control_register(&ssv_rate_ops);
+}
+
+void ssv6xxx_rate_control_unregister(void)
+{
+	ieee80211_rate_control_unregister(&ssv_rate_ops);
+}
+
+void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb,
+				u32 rate_index)
+{
+	struct ssv_softc *sc = hw->priv;
+	struct ieee80211_sta *sta;
+	struct ssv_sta_priv_data *ssv_sta_priv;
+	sta = ssv6xxx_find_sta_by_rx_skb(sc, skb);
+	if (sta == NULL) {
+		return;
+	}
+	ssv_sta_priv = (struct ssv_sta_priv_data *)sta->drv_priv;
+	ssv_sta_priv->rx_data_rate = rate_index;
+}
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc.h b/drivers/net/wireless/ssv6051/smac/ssv_rc.h
new file mode 100644
index 00000000000..911c182897f
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_rc.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_RC_H_
+#define _SSV_RC_H_
+#include "ssv_rc_common.h"
+#define RC_PID_REPORT_INTERVAL 40
+#define RC_PID_INTERVAL 125
+#define RC_PID_DO_ARITH_RIGHT_SHIFT(x,y) \
+ ((x) < 0 ? -((-(x)) >> (y)) : (x) >> (y))
+#define RC_PID_NORM_OFFSET 3
+#define RC_PID_SMOOTHING_SHIFT 1
+#define RC_PID_SMOOTHING (1 << RC_PID_SMOOTHING_SHIFT)
+#define RC_PID_COEFF_P 15
+#define RC_PID_COEFF_I 15
+#define RC_PID_COEFF_D 5
+#define MAXPROBES 3
+#define SSV_DRATE_IDX (2)
+#define SSV_CRATE_IDX (3)
+
+struct ssv_softc;
+struct ssv_rc_rate *ssv6xxx_rc_get_rate(int rc_index);
+void ssv6xxx_rc_hw_rate_idx(struct ssv_softc *sc,
+			    struct ieee80211_tx_info *info,
+			    struct ssv_rate_info *sr);
+u8 ssv6xxx_rc_hw_rate_update_check(struct sk_buff *skb, struct ssv_softc *sc,
+				   u32 do_rts_cts);
+void ssv6xxx_rc_mac8011_rate_idx(struct ssv_softc *sc, int hw_rate_idx,
+				 struct ieee80211_rx_status *rxs);
+void ssv6xxx_rc_hw_reset(struct ssv_softc *sc, int rc_idx, int hwidx);
+void ssv6xxx_rc_update_basic_rate(struct ssv_softc *sc, u32 basic_rates);
+int ssv6xxx_rate_control_register(void);
+void ssv6xxx_rate_control_unregister(void);
+void ssv6xxx_rc_rx_data_handler(struct ieee80211_hw *hw, struct sk_buff *skb,
+				u32 rate_index);
+int pide_frame_duration(size_t len, int rate, int short_preamble, int flags);
+#endif
diff --git a/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h b/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
new file mode 100644
index 00000000000..13f3fdd8072
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/smac/ssv_rc_common.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_RC_COM_H_
+#define _SSV_RC_COM_H_
+#define SSV_RC_MAX_STA 8
+#define MCS_GROUP_RATES 8
+#define SSV_HT_RATE_MAX 8
+#define TDIFS 34
+#define TSLOT 9
+#define SSV_RC_MAX_HARDWARE_SUPPORT 2
+#define RC_FIRMWARE_REPORT_FLAG 0x80
+#define RC_FLAG_INVALID 0x00000001
+#define RC_FLAG_LEGACY 0x00000002
+#define RC_FLAG_HT 0x00000004
+#define RC_FLAG_HT_SGI 0x00000008
+#define RC_FLAG_HT_GF 0x00000010
+#define RC_FLAG_SHORT_PREAMBLE 0x00000020
+enum ssv6xxx_rc_phy_type {
+	WLAN_RC_PHY_CCK,
+	WLAN_RC_PHY_OFDM,
+	WLAN_RC_PHY_HT_20_SS_LGI,
+	WLAN_RC_PHY_HT_20_SS_SGI,
+	WLAN_RC_PHY_HT_20_SS_GF,
+};
+#define RATE_TABLE_SIZE 39
+#define RC_STA_VALID 0x00000001
+#define RC_STA_CAP_HT 0x00000002
+#define RC_STA_CAP_GF 0x00000004
+#define RC_STA_CAP_SGI_20 0x00000008
+#define RC_STA_CAP_SHORT_PREAMBLE 0x00000010
+#define SSV62XX_G_RATE_INDEX 7
+#define SSV62XX_RATE_MCS_INDEX 15
+#define SSV62XX_RATE_MCS_LGI_INDEX 15
+#define SSV62XX_RATE_MCS_SGI_INDEX 23
+#define SSV62XX_RATE_MCS_GREENFIELD_INDEX 31
+enum ssv_rc_rate_type {
+	RC_TYPE_B_ONLY = 0,
+	RC_TYPE_LEGACY_GB,
+	RC_TYPE_SGI_20,
+	RC_TYPE_LGI_20,
+	RC_TYPE_HT_SGI_20,
+	RC_TYPE_HT_LGI_20,
+	RC_TYPE_HT_GF,
+	RC_TYPE_MAX,
+};
+struct ssv_rate_info {
+	int crate_kbps;
+	int crate_hw_idx;
+	int drate_kbps;
+	int drate_hw_idx;
+	u32 d_flags;
+	u32 c_flags;
+};
+struct ssv_rc_rate {
+	u32 rc_flags;
+	u16 phy_type;
+	u32 rate_kbps;
+	u8 dot11_rate_idx;
+	u8 ctrl_rate_idx;
+	u8 hw_rate_idx;
+	u8 arith_shift;
+	u8 target_pf;
+};
+struct rc_pid_sta_info {
+	unsigned long last_sample;
+	unsigned long last_report;
+	u16 tx_num_failed;
+	u16 tx_num_xmit;
+	u8 probe_report_flag;
+	u8 probe_wating_times;
+	u8 real_hw_index;
+	int txrate_idx;
+	u8 last_pf;
+	s32 err_avg_sc;
+	int last_dlr;
+	u8 feedback_probes;
+	u8 monitoring;
+	u8 oldrate;
+	u8 tmp_rate_idx;
+	u8 probe_cnt;
+};
+struct rc_pid_rateinfo {
+	u16 rc_index;
+	u16 index;
+	s32 diff;
+	u16 perfect_tx_time;
+	u32 throughput;
+	unsigned long this_attempt;
+	unsigned long this_success;
+	unsigned long this_fail;
+	u64 attempt;
+	u64 success;
+	u64 fail;
+};
+struct rc_pid_info {
+	unsigned int target;
+	int oldrate;
+	struct rc_pid_rateinfo rinfo[12];
+};
+struct mcs_group {
+	unsigned int duration[MCS_GROUP_RATES];
+};
+struct minstrel_rate_stats {
+	u16 rc_index;
+	unsigned int attempts, last_attempts;
+	unsigned int success, last_success;
+	u64 att_hist, succ_hist;
+	unsigned int cur_tp;
+	unsigned int cur_prob, probability;
+	unsigned int retry_count;
+	unsigned int retry_count_rtscts;
+	u8 sample_skipped;
+};
+struct minstrel_mcs_group_data {
+	u8 index;
+	u8 column;
+	unsigned int max_tp_rate;
+	unsigned int max_tp_rate2;
+	unsigned int max_prob_rate;
+	struct minstrel_rate_stats rates[MCS_GROUP_RATES];
+};
+struct ssv62xx_ht {
+	unsigned int ampdu_len;
+	unsigned int ampdu_packets;
+	unsigned int avg_ampdu_len;
+	unsigned int max_tp_rate;
+	unsigned int max_tp_rate2;
+	unsigned int max_prob_rate;
+	int first_try_count;
+	int second_try_count;
+	int other_try_count;
+	unsigned long stats_update;
+	unsigned int overhead;
+	unsigned int overhead_rtscts;
+	unsigned int total_packets;
+	unsigned int sample_packets;
+	u8 sample_wait;
+	u8 sample_tries;
+	u8 sample_count;
+	u8 sample_slow;
+	struct minstrel_mcs_group_data groups;
+};
+struct ssv_sta_rc_info {
+	u8 rc_valid;
+	u8 rc_type;
+	u8 rc_num_rate;
+	s8 rc_wsid;
+	u8 ht_rc_type;
+	u8 is_ht;
+	u32 rc_supp_rates;
+	u32 ht_supp_rates;
+	struct rc_pid_info pinfo;
+	struct rc_pid_sta_info spinfo;
+	struct ssv62xx_ht ht;
+};
+struct ssv_rate_ctrl {
+	struct ssv_rc_rate *rc_table;
+	struct ssv_sta_rc_info sta_rc_info[SSV_RC_MAX_STA];
+};
+#define HT_RC_UPDATE_INTERVAL 1000
+#endif
diff --git a/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c b/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
new file mode 100644
index 00000000000..10a9a77081d
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/ssv6051-generic-wlan.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/irq.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+#include <asm/io.h>
+#include <linux/printk.h>
+#include <linux/err.h>
+
+static int g_wifidev_registered = 0;
+extern int ssvdevice_init(void);
+extern void ssvdevice_exit(void);
+extern int ssv6xxx_get_dev_status(void);
+
+static __init int ssv_init_module(void)
+{
+	int ret = 0;
+	int time = 5;
+
+	msleep(120);
+
+	g_wifidev_registered = 1;
+	ret = ssvdevice_init();
+
+	while(time-- > 0){
+		msleep(500);
+		if(ssv6xxx_get_dev_status() == 1)
+			break;
+		pr_info("%s : Retry to carddetect\n",__func__);
+	}
+
+	return ret;
+
+}
+static __exit void ssv_exit_module(void)
+{
+
+	if (g_wifidev_registered)
+    {
+        ssvdevice_exit();
+        msleep(50);
+        g_wifidev_registered = 0;
+    }
+
+    return;
+
+}
+
+module_init(ssv_init_module);
+module_exit(ssv_exit_module);
+
+MODULE_AUTHOR("iComm Semiconductor Co., Ltd");
+MODULE_FIRMWARE("ssv*-sw.bin");
+MODULE_FIRMWARE("ssv*-wifi.cfg");
+MODULE_DESCRIPTION("Shared library for SSV wireless LAN cards.");
+MODULE_LICENSE("Dual BSD/GPL");
+
diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
new file mode 100644
index 00000000000..503df1ea6dc
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.c
@@ -0,0 +1,1765 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/export.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+#include <ssv6200_reg.h>
+#include <ssv6200.h>
+#include <hci/hctrl.h>
+#include <smac/dev.h>
+#include "ssv_cmd.h"
+#include <ssv_version.h>
+#include <ssv6200_configuration.h>
+#define SSV_CMD_PRINTF()
+struct ssv6xxx_dev_table {
+	u32 address;
+	u32 val;
+};
+struct ssv6xxx_debug {
+	struct device *dev;
+	struct platform_device *pdev;
+	struct ssv6xxx_hwif_ops *ifops;
+};
+static struct ssv6xxx_debug *ssv6xxx_debug_ifops;
+static char sg_cmd_buffer[CLI_BUFFER_SIZE + 1];
+static char *sg_argv[CLI_ARG_SIZE];
+static u32 sg_argc;
+extern char *ssv6xxx_result_buf;
+#if defined (CONFIG_ARM64) || defined (__x86_64__)
+u64 ssv6xxx_ifdebug_info[3] = { 0, 0, 0 };
+#else
+u32 ssv6xxx_ifdebug_info[3] = { 0, 0, 0 };
+#endif
+EXPORT_SYMBOL(ssv6xxx_ifdebug_info);
+struct sk_buff *ssvdevice_skb_alloc(s32 len)
+{
+	struct sk_buff *skb;
+	skb = __dev_alloc_skb(len + SSV6200_ALLOC_RSVD, GFP_KERNEL);
+	if (skb != NULL) {
+		skb_put(skb, 0x20);
+		skb_pull(skb, 0x20);
+	}
+	return skb;
+}
+
+void ssvdevice_skb_free(struct sk_buff *skb)
+{
+	dev_kfree_skb_any(skb);
+}
+
+static int ssv_cmd_help(int argc, char *argv[])
+{
+	extern struct ssv_cmd_table cmd_table[];
+	struct ssv_cmd_table *sc_tbl;
+	char tmpbf[161];
+	int total_cmd = 0;
+	{
+		sprintf(ssv6xxx_result_buf, "Usage:\n");
+		for (sc_tbl = &cmd_table[3]; sc_tbl->cmd; sc_tbl++) {
+			sprintf(tmpbf, "%-20s\t\t%s\n", sc_tbl->cmd,
+				sc_tbl->usage);
+			strcat(ssv6xxx_result_buf, tmpbf);
+			total_cmd++;
+		}
+		sprintf(tmpbf,
+			"Total CMDs: %d\n\nType cli help [CMD] for more detail command.\n\n",
+			total_cmd);
+		strcat(ssv6xxx_result_buf, tmpbf);
+	}
+	return 0;
+}
+
+static int ssv_cmd_reg(int argc, char *argv[])
+{
+	u32 addr, value, count;
+	char tmpbf[64], *endp;
+	int s;
+	if (argc == 4 && strcmp(argv[1], "w") == 0) {
+		addr = simple_strtoul(argv[2], &endp, 16);
+		value = simple_strtoul(argv[3], &endp, 16);
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, addr, value)) ;
+		sprintf(ssv6xxx_result_buf, " => write [0x%08x]: 0x%08x\n",
+			addr, value);
+		return 0;
+	} else if ((argc == 4 || argc == 3) && strcmp(argv[1], "r") == 0) {
+		count = (argc == 3) ? 1 : simple_strtoul(argv[3], &endp, 10);
+		addr = simple_strtoul(argv[2], &endp, 16);
+		sprintf(ssv6xxx_result_buf, "ADDRESS: 0x%08x\n", addr);
+		for (s = 0; s < count; s++, addr += 4) {
+			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+			sprintf(tmpbf, "%08x ", value);
+			strcat(ssv6xxx_result_buf, tmpbf);
+			if (((s + 1) & 0x07) == 0)
+				strcat(ssv6xxx_result_buf, "\n");
+		}
+		strcat(ssv6xxx_result_buf, "\n");
+		return 0;
+	} else {
+		sprintf(tmpbf, "reg [r|w] [address] [value|word-count]\n\n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		return 0;
+	}
+	return -1;
+}
+
+struct ssv6xxx_cfg ssv_cfg;
+EXPORT_SYMBOL(ssv_cfg);
+static int __string2u32(u8 * u8str, void *val, u32 arg)
+{
+	char *endp;
+	int base = 10;
+	if (u8str[0] == '0' && ((u8str[1] == 'x') || (u8str[1] == 'X')))
+		base = 16;
+	*(u32 *) val = simple_strtoul(u8str, &endp, base);
+	return 0;
+}
+
+static int __string2flag32(u8 * flag_str, void *flag, u32 arg)
+{
+	u32 *val = (u32 *) flag;
+	if (arg >= (sizeof(u32) << 3))
+		return -1;
+	if (strcmp(flag_str, "on") == 0) {
+		*val |= (1 << arg);
+		return 0;
+	}
+	if (strcmp(flag_str, "off") == 0) {
+		*val &= ~(1 << arg);
+		return 0;
+	}
+	return -1;
+}
+
+static int __string2mac(u8 * mac_str, void *val, u32 arg)
+{
+	int s, macaddr[6];
+	u8 *mac = (u8 *) val;
+	s = sscanf(mac_str, "%02x:%02x:%02x:%02x:%02x:%02x",
+		   &macaddr[0], &macaddr[1], &macaddr[2],
+		   &macaddr[3], &macaddr[4], &macaddr[5]);
+	if (s != 6)
+		return -1;
+	mac[0] = (u8) macaddr[0], mac[1] = (u8) macaddr[1];
+	mac[2] = (u8) macaddr[2], mac[3] = (u8) macaddr[3];
+	mac[4] = (u8) macaddr[4], mac[5] = (u8) macaddr[5];
+	return 0;
+}
+
+static int __string2str(u8 * path, void *val, u32 arg)
+{
+	u8 *temp = (u8 *) val;
+	sprintf(temp, "%s", path);
+	return 0;
+}
+
+static int __string2configuration(u8 * mac_str, void *val, u32 arg)
+{
+	unsigned int address, value;
+	int i;
+	i = sscanf(mac_str, "%08x:%08x", &address, &value);
+	if (i != 2)
+		return -1;
+	for (i = 0; i < EXTERNEL_CONFIG_SUPPORT; i++) {
+		if (ssv_cfg.configuration[i][0] == 0x0) {
+			ssv_cfg.configuration[i][0] = address;
+			ssv_cfg.configuration[i][1] = value;
+			return 0;
+		}
+	}
+	return 0;
+}
+
+struct ssv6xxx_cfg_cmd_table cfg_cmds[] = {
+	{"hw_mac", (void *)&ssv_cfg.maddr[0][0], 0, __string2mac},
+	{"hw_mac_2", (void *)&ssv_cfg.maddr[1][0], 0, __string2mac},
+	{"def_chan", (void *)&ssv_cfg.def_chan, 0, __string2u32},
+	{"hw_cap_ht", (void *)&ssv_cfg.hw_caps, 0, __string2flag32},
+	{"hw_cap_gf", (void *)&ssv_cfg.hw_caps, 1, __string2flag32},
+	{"hw_cap_2ghz", (void *)&ssv_cfg.hw_caps, 2, __string2flag32},
+	{"hw_cap_5ghz", (void *)&ssv_cfg.hw_caps, 3, __string2flag32},
+	{"hw_cap_security", (void *)&ssv_cfg.hw_caps, 4, __string2flag32},
+	{"hw_cap_sgi_20", (void *)&ssv_cfg.hw_caps, 5, __string2flag32},
+	{"hw_cap_sgi_40", (void *)&ssv_cfg.hw_caps, 6, __string2flag32},
+	{"hw_cap_ap", (void *)&ssv_cfg.hw_caps, 7, __string2flag32},
+	{"hw_cap_p2p", (void *)&ssv_cfg.hw_caps, 8, __string2flag32},
+	{"hw_cap_ampdu_rx", (void *)&ssv_cfg.hw_caps, 9, __string2flag32},
+	{"hw_cap_ampdu_tx", (void *)&ssv_cfg.hw_caps, 10, __string2flag32},
+	{"hw_cap_tdls", (void *)&ssv_cfg.hw_caps, 11, __string2flag32},
+	{"use_wpa2_only", (void *)&ssv_cfg.use_wpa2_only, 0, __string2u32},
+	{"wifi_tx_gain_level_gn", (void *)&ssv_cfg.wifi_tx_gain_level_gn, 0,
+	 __string2u32},
+	{"wifi_tx_gain_level_b", (void *)&ssv_cfg.wifi_tx_gain_level_b, 0,
+	 __string2u32},
+	{"rssi_ctl", (void *)&ssv_cfg.rssi_ctl, 0, __string2u32},
+	{"xtal_clock", (void *)&ssv_cfg.crystal_type, 0, __string2u32},
+	{"volt_regulator", (void *)&ssv_cfg.volt_regulator, 0, __string2u32},
+	{"force_chip_identity", (void *)&ssv_cfg.force_chip_identity, 0,
+	 __string2u32},
+	{"firmware_path", (void *)&ssv_cfg.firmware_path[0], 0, __string2str},
+	{"flash_bin_path", (void *)&ssv_cfg.flash_bin_path[0], 0, __string2str},
+	{"mac_address_path", (void *)&ssv_cfg.mac_address_path[0], 0,
+	 __string2str},
+	{"mac_output_path", (void *)&ssv_cfg.mac_output_path[0], 0,
+	 __string2str},
+	{"ignore_efuse_mac", (void *)&ssv_cfg.ignore_efuse_mac, 0,
+	 __string2u32},
+	{"mac_address_mode", (void *)&ssv_cfg.mac_address_mode, 0,
+	 __string2u32},
+	{"sr_bhvr", (void *)&ssv_cfg.sr_bhvr, 0, __string2u32},
+	{"register", NULL, 0, __string2configuration},
+	{NULL, NULL, 0, NULL},
+};
+
+EXPORT_SYMBOL(cfg_cmds);
+static int ssv_cmd_cfg(int argc, char *argv[])
+{
+	char temp_buf[64];
+	int s;
+	if (argc == 2 && strcmp(argv[1], "reset") == 0) {
+		memset(&ssv_cfg, 0, sizeof(ssv_cfg));
+		return 0;
+	} else if (argc == 2 && strcmp(argv[1], "show") == 0) {
+		strcpy(ssv6xxx_result_buf, ">> ssv6xxx config:\n");
+		sprintf(temp_buf, "    hw_caps = 0x%08x\n", ssv_cfg.hw_caps);
+		strcat(ssv6xxx_result_buf, temp_buf);
+		sprintf(temp_buf, "    def_chan = %d\n", ssv_cfg.def_chan);
+		strcat(ssv6xxx_result_buf, temp_buf);
+		sprintf(temp_buf, "    wifi_tx_gain_level_gn = %d\n",
+			ssv_cfg.wifi_tx_gain_level_gn);
+		strcat(ssv6xxx_result_buf, temp_buf);
+		sprintf(temp_buf, "    wifi_tx_gain_level_b = %d\n",
+			ssv_cfg.wifi_tx_gain_level_b);
+		strcat(ssv6xxx_result_buf, temp_buf);
+		sprintf(temp_buf, "    rssi_ctl = %d\n", ssv_cfg.rssi_ctl);
+		strcat(ssv6xxx_result_buf, temp_buf);
+		sprintf(temp_buf, "    sr_bhvr = %d\n", ssv_cfg.sr_bhvr);
+		strcat(ssv6xxx_result_buf, temp_buf);
+		sprintf(temp_buf, "    sta-mac = %02x:%02x:%02x:%02x:%02x:%02x",
+			ssv_cfg.maddr[0][0], ssv_cfg.maddr[0][1],
+			ssv_cfg.maddr[0][2], ssv_cfg.maddr[0][3],
+			ssv_cfg.maddr[0][4], ssv_cfg.maddr[0][5]);
+		strcat(ssv6xxx_result_buf, temp_buf);
+		strcat(ssv6xxx_result_buf, "\n");
+		return 0;
+	}
+	if (argc != 4)
+		return -1;
+	for (s = 0; cfg_cmds[s].cfg_cmd != NULL; s++) {
+		if (strcmp(cfg_cmds[s].cfg_cmd, argv[1]) == 0) {
+			cfg_cmds[s].translate_func(argv[3],
+						   cfg_cmds[s].var,
+						   cfg_cmds[s].arg);
+			strcpy(ssv6xxx_result_buf, "");
+			return 0;
+		}
+	}
+	return -1;
+}
+
+void *ssv_dbg_phy_table = NULL;
+EXPORT_SYMBOL(ssv_dbg_phy_table);
+u32 ssv_dbg_phy_len = 0;
+EXPORT_SYMBOL(ssv_dbg_phy_len);
+void *ssv_dbg_rf_table = NULL;
+EXPORT_SYMBOL(ssv_dbg_rf_table);
+u32 ssv_dbg_rf_len = 0;
+EXPORT_SYMBOL(ssv_dbg_rf_len);
+struct ssv_softc *ssv_dbg_sc = NULL;
+EXPORT_SYMBOL(ssv_dbg_sc);
+struct ssv6xxx_hci_ctrl *ssv_dbg_ctrl_hci = NULL;
+EXPORT_SYMBOL(ssv_dbg_ctrl_hci);
+struct Dump_Sta_Info {
+	char *dump_buf;
+	int sta_idx;
+};
+static void _dump_sta_info(struct ssv_softc *sc,
+			   struct ssv_vif_info *vif_info,
+			   struct ssv_sta_info *sta_info, void *param)
+{
+	char tmpbf[128];
+	struct Dump_Sta_Info *dump_sta_info = (struct Dump_Sta_Info *)param;
+	struct ssv_sta_priv_data *priv_sta =
+	    (struct ssv_sta_priv_data *)sta_info->sta->drv_priv;
+	if ((sta_info->s_flags & STA_FLAG_VALID) == 0)
+		sprintf(tmpbf,
+			"        Station %d: %d is not valid\n",
+			dump_sta_info->sta_idx, priv_sta->sta_idx);
+	else
+		sprintf(tmpbf,
+			"        Station %d: %d\n"
+			"             Address: %02X:%02X:%02X:%02X:%02X:%02X\n"
+			"             WISD: %d\n"
+			"             AID: %d\n"
+			"             Sleep: %d\n",
+			dump_sta_info->sta_idx, priv_sta->sta_idx,
+			sta_info->sta->addr[0], sta_info->sta->addr[1],
+			sta_info->sta->addr[2], sta_info->sta->addr[3],
+			sta_info->sta->addr[4], sta_info->sta->addr[5],
+			sta_info->hw_wsid, sta_info->aid, sta_info->sleeping);
+	dump_sta_info->sta_idx++;
+	strcat(dump_sta_info->dump_buf, tmpbf);
+}
+
+void ssv6xxx_dump_sta_info(struct ssv_softc *sc, char *target_buf)
+{
+	int j;
+	char tmpbf[128];
+	struct Dump_Sta_Info dump_sta_info = { target_buf, 0 };
+	sprintf(tmpbf, "  >>>> bcast queue len[%d]\n", sc->bcast_txq.cur_qsize);
+	strcat(target_buf, tmpbf);
+	for (j = 0; j < SSV6200_MAX_VIF; j++) {
+		struct ieee80211_vif *vif = sc->vif_info[j].vif;
+		struct ssv_vif_priv_data *priv_vif;
+		struct ssv_sta_priv_data *sta_priv_iter;
+		if (vif == NULL) {
+			sprintf(tmpbf, "    VIF: %d is not used.\n", j);
+			strcat(target_buf, tmpbf);
+			continue;
+		}
+		sprintf(tmpbf,
+			"    VIF: %d - [%02X:%02X:%02X:%02X:%02X:%02X] type[%d] p2p[%d]\n",
+			j, vif->addr[0], vif->addr[1], vif->addr[2],
+			vif->addr[3], vif->addr[4], vif->addr[5], vif->type,
+			vif->p2p);
+		strcat(target_buf, tmpbf);
+		priv_vif = (struct ssv_vif_priv_data *)(vif->drv_priv);
+		list_for_each_entry(sta_priv_iter, &priv_vif->sta_list, list) {
+			if ((sta_priv_iter->sta_info->
+			     s_flags & STA_FLAG_VALID) == 0) {
+				sprintf(tmpbf, "    VIF: %d  is not valid.\n",
+					j);
+				strcat(target_buf, tmpbf);
+				continue;
+			}
+			_dump_sta_info(sc, &sc->vif_info[priv_vif->vif_idx],
+				       sta_priv_iter->sta_info, &dump_sta_info);
+		}
+	}
+}
+
+static int ssv_cmd_sta(int argc, char *argv[])
+{
+	if (argc >= 2 && strcmp(argv[1], "show") == 0)
+		ssv6xxx_dump_sta_info(ssv_dbg_sc, ssv6xxx_result_buf);
+	else
+		strcat(ssv6xxx_result_buf, "sta show\n\n");
+	return 0;
+}
+
+static int ssv_cmd_dump(int argc, char *argv[])
+{
+	u32 addr, regval;
+	char tmpbf[64];
+	int s;
+	if (!ssv6xxx_result_buf) {
+		pr_warn("ssv6xxx_result_buf = NULL!!\n");
+		return -1;
+	}
+	if (argc != 2) {
+		sprintf(tmpbf,
+			"dump [wsid|decision|phy-info|phy-reg|rf-reg]\n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		return 0;
+	}
+	if (strcmp(argv[1], "wsid") == 0) {
+		const u32 reg_wsid[] = { ADR_WSID0, ADR_WSID1 };
+		const u32 reg_wsid_tid0[] =
+		    { ADR_WSID0_TID0_RX_SEQ, ADR_WSID1_TID0_RX_SEQ };
+		const u32 reg_wsid_tid7[] =
+		    { ADR_WSID0_TID7_RX_SEQ, ADR_WSID1_TID7_RX_SEQ };
+		const u8 *op_mode_str[] = { "STA", "AP", "AD-HOC", "WDS" };
+		const u8 *ht_mode_str[] =
+		    { "Non-HT", "HT-MF", "HT-GF", "RSVD" };
+		for (s = 0; s < SSV_NUM_HW_STA; s++) {
+			if (SSV_REG_READ1
+			    (ssv6xxx_debug_ifops, reg_wsid[s], &regval)) ;
+			sprintf(tmpbf,
+				"==>WSID[%d]\n\tvalid[%d] qos[%d] op_mode[%s] ht_mode[%s]\n",
+				s, regval & 0x1, (regval >> 1) & 0x1,
+				op_mode_str[((regval >> 2) & 3)],
+				ht_mode_str[((regval >> 4) & 3)]);
+			strcat(ssv6xxx_result_buf, tmpbf);
+			if (SSV_REG_READ1
+			    (ssv6xxx_debug_ifops, reg_wsid[s] + 4, &regval)) ;
+			sprintf(tmpbf, "\tMAC[%02x:%02x:%02x:%02x:",
+				(regval & 0xff), ((regval >> 8) & 0xff),
+				((regval >> 16) & 0xff),
+				((regval >> 24) & 0xff));
+			strcat(ssv6xxx_result_buf, tmpbf);
+			if (SSV_REG_READ1
+			    (ssv6xxx_debug_ifops, reg_wsid[s] + 8, &regval)) ;
+			sprintf(tmpbf, "%02x:%02x]\n", (regval & 0xff),
+				((regval >> 8) & 0xff));
+			strcat(ssv6xxx_result_buf, tmpbf);
+			for (addr = reg_wsid_tid0[s]; addr <= reg_wsid_tid7[s];
+			     addr += 4) {
+				if (SSV_REG_READ1
+				    (ssv6xxx_debug_ifops, addr, &regval)) ;
+				sprintf(tmpbf, "\trx_seq%d[%d]\n",
+					((addr - reg_wsid_tid0[s]) >> 2),
+					((regval) & 0xffff));
+				strcat(ssv6xxx_result_buf, tmpbf);
+			}
+		}
+		return 0;
+	}
+	if (strcmp(argv[1], "decision") == 0) {
+		strcpy(ssv6xxx_result_buf, ">> Decision Table:\n");
+		for (s = 0, addr = ADR_MRX_FLT_TB0; s < 16; s++, addr += 4) {
+			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &regval)) ;
+			sprintf(tmpbf, "   [%d]: ADDR[0x%08x] = 0x%08x\n",
+				s, addr, regval);
+			strcat(ssv6xxx_result_buf, tmpbf);
+		}
+		strcat(ssv6xxx_result_buf, "\n\n>> Decision Mask:\n");
+		for (s = 0, addr = ADR_MRX_FLT_EN0; s < 9; s++, addr += 4) {
+			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &regval)) ;
+			sprintf(tmpbf, "   [%d]: ADDR[0x%08x] = 0x%08x\n",
+				s, addr, regval);
+			strcat(ssv6xxx_result_buf, tmpbf);
+		}
+		strcat(ssv6xxx_result_buf, "\n\n");
+		return 0;
+	}
+	if (strcmp(argv[1], "phy-info") == 0) {
+		return 0;
+	}
+	if (strcmp(argv[1], "phy-reg") == 0) {
+		struct ssv6xxx_dev_table *raw;
+		raw = (struct ssv6xxx_dev_table *)ssv_dbg_phy_table;
+		strcpy(ssv6xxx_result_buf, ">> PHY Register Table:\n");
+		for (s = 0; s < ssv_dbg_phy_len; s++, raw++) {
+			if (SSV_REG_READ1
+			    (ssv6xxx_debug_ifops, raw->address, &regval)) ;
+			sprintf(tmpbf, "   ADDR[0x%08x] = 0x%08x\n",
+				raw->address, regval);
+			strcat(ssv6xxx_result_buf, tmpbf);
+		}
+		strcat(ssv6xxx_result_buf, "\n\n");
+		return 0;
+	}
+	if (strcmp(argv[1], "rf-reg") == 0) {
+		struct ssv6xxx_dev_table *raw;
+		raw = (struct ssv6xxx_dev_table *)ssv_dbg_rf_table;
+		strcpy(ssv6xxx_result_buf, ">> RF Register Table:\n");
+		for (s = 0; s < ssv_dbg_rf_len; s++, raw++) {
+			if (SSV_REG_READ1
+			    (ssv6xxx_debug_ifops, raw->address, &regval)) ;
+			sprintf(tmpbf, "   ADDR[0x%08x] = 0x%08x\n",
+				raw->address, regval);
+			strcat(ssv6xxx_result_buf, tmpbf);
+		}
+		strcat(ssv6xxx_result_buf, "\n\n");
+		return 0;
+	}
+	return -1;
+}
+
+static int ssv_cmd_irq(int argc, char *argv[])
+{
+	char *endp;
+	u32 irq_sts;
+	if (argc >= 3 && strcmp(argv[1], "set") == 0) {
+		if (strcmp(argv[2], "mask") == 0 && argc == 4) {
+			irq_sts = simple_strtoul(argv[3], &endp, 16);
+			if (!ssv6xxx_debug_ifops->ifops->irq_setmask) {
+				sprintf(ssv6xxx_result_buf,
+					"The interface doesn't provide irq_setmask operation.\n");
+				return 0;
+			}
+			ssv6xxx_debug_ifops->ifops->
+			    irq_setmask(ssv6xxx_debug_ifops->dev, irq_sts);
+			sprintf(ssv6xxx_result_buf,
+				"set sdio irq mask to 0x%08x\n", irq_sts);
+			return 0;
+		}
+		if (strcmp(argv[2], "enable") == 0) {
+			if (!ssv6xxx_debug_ifops->ifops->irq_enable) {
+				sprintf(ssv6xxx_result_buf,
+					"The interface doesn't provide irq_enable operation.\n");
+				return 0;
+			}
+			ssv6xxx_debug_ifops->ifops->
+			    irq_enable(ssv6xxx_debug_ifops->dev);
+			strcpy(ssv6xxx_result_buf, "enable sdio irq.\n");
+			return 0;
+		}
+		if (strcmp(argv[2], "disable") == 0) {
+			if (!ssv6xxx_debug_ifops->ifops->irq_disable) {
+				sprintf(ssv6xxx_result_buf,
+					"The interface doesn't provide irq_disable operation.\n");
+				return 0;
+			}
+			ssv6xxx_debug_ifops->ifops->
+			    irq_disable(ssv6xxx_debug_ifops->dev, false);
+			strcpy(ssv6xxx_result_buf, "disable sdio irq.\n");
+			return 0;
+		}
+		return -1;
+	} else if (argc == 3 && strcmp(argv[1], "get") == 0) {
+		if (strcmp(argv[2], "mask") == 0) {
+			if (!ssv6xxx_debug_ifops->ifops->irq_getmask) {
+				sprintf(ssv6xxx_result_buf,
+					"The interface doesn't provide irq_getmask operation.\n");
+				return 0;
+			}
+			ssv6xxx_debug_ifops->ifops->
+			    irq_getmask(ssv6xxx_debug_ifops->dev, &irq_sts);
+			sprintf(ssv6xxx_result_buf,
+				"sdio irq mask: 0x%08x, int_mask=0x%08x\n",
+				irq_sts, ssv_dbg_ctrl_hci->int_mask);
+			return 0;
+		}
+		if (strcmp(argv[2], "status") == 0) {
+			if (!ssv6xxx_debug_ifops->ifops->irq_getstatus) {
+				sprintf(ssv6xxx_result_buf,
+					"The interface doesn't provide irq_getstatus operation.\n");
+				return 0;
+			}
+			ssv6xxx_debug_ifops->ifops->
+			    irq_getstatus(ssv6xxx_debug_ifops->dev, &irq_sts);
+			sprintf(ssv6xxx_result_buf, "sdio irq status: 0x%08x\n",
+				irq_sts);
+			return 0;
+		}
+		return -1;
+	} else {
+		sprintf(ssv6xxx_result_buf,
+			"irq [set|get] [mask|enable|disable|status]\n");
+	}
+	return 0;
+}
+
+static int ssv_cmd_mac(int argc, char *argv[])
+{
+	char temp_str[128], *endp;
+	u32 s;
+	int i;
+	if (argc == 3 && !strcmp(argv[1], "wsid") && !strcmp(argv[2], "show")) {
+		for (s = 0; s < SSV_NUM_HW_STA; s++) {
+		}
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "rx")) {
+		if (!strcmp(argv[2], "enable")) {
+			ssv_dbg_sc->dbg_rx_frame = 1;
+		} else {
+			ssv_dbg_sc->dbg_rx_frame = 0;
+		}
+		sprintf(temp_str, "  dbg_rx_frame %d\n",
+			ssv_dbg_sc->dbg_rx_frame);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "tx")) {
+		if (!strcmp(argv[2], "enable")) {
+			ssv_dbg_sc->dbg_tx_frame = 1;
+		} else {
+			ssv_dbg_sc->dbg_tx_frame = 0;
+		}
+		sprintf(temp_str, "  dbg_tx_frame %d\n",
+			ssv_dbg_sc->dbg_tx_frame);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "rxq")
+		   && !strcmp(argv[2], "show")) {
+		sprintf(temp_str, ">> MAC RXQ: (%s)\n    cur_qsize=%d\n",
+			((ssv_dbg_sc->
+			  sc_flags & SC_OP_OFFCHAN) ? "off channel" :
+			 "on channel"), ssv_dbg_sc->rx.rxq_count);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if (argc == 4 && !strcmp(argv[1], "set")
+		   && !strcmp(argv[2], "rate")) {
+		if (strcmp(argv[3], "auto") == 0) {
+			ssv_dbg_sc->sc_flags &= ~SC_OP_FIXED_RATE;
+			return 0;
+		}
+		i = simple_strtoul(argv[3], &endp, 10);
+		if (i < 0 || i > 38) {
+			strcpy(ssv6xxx_result_buf, " Invalid rat index !!\n");
+			return -1;
+		}
+		ssv_dbg_sc->max_rate_idx = i;
+		ssv_dbg_sc->sc_flags |= SC_OP_FIXED_RATE;
+		sprintf(temp_str, " Set rate to index %d\n", i);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "get")
+		   && !strcmp(argv[2], "rate")) {
+		if (ssv_dbg_sc->sc_flags & SC_OP_FIXED_RATE)
+			sprintf(temp_str, " Current Rate Index: %d\n",
+				ssv_dbg_sc->max_rate_idx);
+		else
+			sprintf(temp_str, "  Current Rate Index: auto\n");
+		strcpy(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else {
+		sprintf(temp_str, "mac [security|wsid|rxq]  [show]\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "mac [set|get] [rate] [auto|idx]\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "mac [rx|tx] [eable|disable]\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	}
+	return 0;
+}
+
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+void print_irq_count(void)
+{
+	char temp_str[512];
+	sprintf(temp_str, "irq debug (%s)\n",
+		ssv_dbg_ctrl_hci->irq_enable ? "enable" : "disable");
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "total irq (%d)\n", ssv_dbg_ctrl_hci->irq_count);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "invalid irq (%d)\n",
+		ssv_dbg_ctrl_hci->invalid_irq_count);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "rx irq (%d)\n", ssv_dbg_ctrl_hci->rx_irq_count);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "tx irq (%d)\n", ssv_dbg_ctrl_hci->tx_irq_count);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "real tx count irq (%d)\n",
+		ssv_dbg_ctrl_hci->real_tx_irq_count);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "tx  packet count (%d)\n",
+		ssv_dbg_ctrl_hci->irq_tx_pkt_count);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "rx packet (%d)\n",
+		ssv_dbg_ctrl_hci->irq_rx_pkt_count);
+	strcat(ssv6xxx_result_buf, temp_str);
+}
+#endif
+void print_isr_info(void)
+{
+	char temp_str[512];
+	sprintf(temp_str, ">>>> HCI Calculate ISR TIME(%s) unit:us\n",
+		((ssv_dbg_ctrl_hci->isr_summary_eable) ? "enable" : "disable"));
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "isr_routine_time(%d)\n",
+		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_routine_time));
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "isr_tx_time(%d)\n",
+		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_tx_time));
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "isr_rx_time(%d)\n",
+		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_rx_time));
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "isr_idle_time(%d)\n",
+		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_idle_time));
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "isr_rx_idle_time(%d)\n",
+		jiffies_to_usecs(ssv_dbg_ctrl_hci->isr_rx_idle_time));
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "isr_miss_cnt(%d)\n", ssv_dbg_ctrl_hci->isr_miss_cnt);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "prev_isr_jiffes(%lu)\n",
+		ssv_dbg_ctrl_hci->prev_isr_jiffes);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "prev_rx_isr_jiffes(%lu)\n",
+		ssv_dbg_ctrl_hci->prev_rx_isr_jiffes);
+	strcat(ssv6xxx_result_buf, temp_str);
+}
+
+static int ssv_cmd_hci(int argc, char *argv[])
+{
+	struct ssv_hw_txq *txq;
+	char temp_str[512];
+	int s, ac = 0;
+	if (argc == 3 && !strcmp(argv[1], "txq") && !strcmp(argv[2], "show")) {
+		for (s = 0; s < WMM_NUM_AC; s++) {
+			if (ssv_dbg_sc != NULL)
+				ac = ssv_dbg_sc->tx.ac_txqid[s];
+			txq = &ssv_dbg_ctrl_hci->hw_txq[s];
+			sprintf(temp_str, ">> txq[%d]", txq->txq_no);
+			if (ssv_dbg_sc != NULL)
+				sprintf(temp_str, "(%s): ",
+					((ssv_dbg_sc->
+					  sc_flags & SC_OP_OFFCHAN) ?
+					 "off channel" : "on channel"));
+			sprintf(temp_str, "cur_qsize=%d\n",
+				skb_queue_len(&txq->qhead));
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str,
+				"            max_qsize=%d, pause=%d, resume_thres=%d",
+				txq->max_qsize, txq->paused, txq->resum_thres);
+			if (ssv_dbg_sc != NULL)
+				sprintf(temp_str, " flow_control[%d]\n",
+					!!(ssv_dbg_sc->tx.
+					   flow_ctrl_status & (1 << ac)));
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "            Total %d frame sent\n",
+				txq->tx_pkt);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		sprintf(temp_str,
+			">> HCI Debug Counters:\n    read_rs0_info_fail=%d, read_rs1_info_fail=%d\n",
+			ssv_dbg_ctrl_hci->read_rs0_info_fail,
+			ssv_dbg_ctrl_hci->read_rs1_info_fail);
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str,
+			"    rx_work_running=%d, isr_running=%d, xmit_running=%d\n",
+			ssv_dbg_ctrl_hci->rx_work_running,
+			ssv_dbg_ctrl_hci->isr_running,
+			ssv_dbg_ctrl_hci->xmit_running);
+		strcat(ssv6xxx_result_buf, temp_str);
+		if (ssv_dbg_sc != NULL)
+			sprintf(temp_str, "    flow_ctrl_status=%08x\n",
+				ssv_dbg_sc->tx.flow_ctrl_status);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "rxq")
+		   && !strcmp(argv[2], "show")) {
+		sprintf(temp_str, ">> HCI RX Queue (%s): cur_qsize=%d\n",
+			((ssv_dbg_sc->
+			  sc_flags & SC_OP_OFFCHAN) ? "off channel" :
+			 "on channel"), ssv_dbg_ctrl_hci->rx_pkt);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "isr_time")
+		   && !strcmp(argv[2], "start")) {
+		ssv_dbg_ctrl_hci->isr_summary_eable = 1;
+		ssv_dbg_ctrl_hci->isr_routine_time = 0;
+		ssv_dbg_ctrl_hci->isr_tx_time = 0;
+		ssv_dbg_ctrl_hci->isr_rx_time = 0;
+		ssv_dbg_ctrl_hci->isr_idle_time = 0;
+		ssv_dbg_ctrl_hci->isr_rx_idle_time = 0;
+		ssv_dbg_ctrl_hci->isr_miss_cnt = 0;
+		ssv_dbg_ctrl_hci->prev_isr_jiffes = 0;
+		ssv_dbg_ctrl_hci->prev_rx_isr_jiffes = 0;
+		print_isr_info();
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "isr_time")
+		   && !strcmp(argv[2], "stop")) {
+		ssv_dbg_ctrl_hci->isr_summary_eable = 0;
+		print_isr_info();
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "isr_time")
+		   && !strcmp(argv[2], "show")) {
+		print_isr_info();
+		return 0;
+	}
+#ifdef CONFIG_IRQ_DEBUG_COUNT
+	else if (argc == 3 && !strcmp(argv[1], "isr_debug")
+		 && !strcmp(argv[2], "reset")) {
+		ssv_dbg_ctrl_hci->irq_enable = 0;
+		ssv_dbg_ctrl_hci->irq_count = 0;
+		ssv_dbg_ctrl_hci->invalid_irq_count = 0;
+		ssv_dbg_ctrl_hci->tx_irq_count = 0;
+		ssv_dbg_ctrl_hci->real_tx_irq_count = 0;
+		ssv_dbg_ctrl_hci->rx_irq_count = 0;
+		ssv_dbg_ctrl_hci->isr_rx_idle_time = 0;
+		ssv_dbg_ctrl_hci->irq_rx_pkt_count = 0;
+		ssv_dbg_ctrl_hci->irq_tx_pkt_count = 0;
+		strcat(ssv6xxx_result_buf, "irq debug reset count\n");
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "isr_debug")
+		   && !strcmp(argv[2], "show")) {
+		print_irq_count();
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "isr_debug")
+		   && !strcmp(argv[2], "stop")) {
+		ssv_dbg_ctrl_hci->irq_enable = 0;
+		strcat(ssv6xxx_result_buf, "irq debug stop\n");
+		return 0;
+	} else if (argc == 3 && !strcmp(argv[1], "isr_debug")
+		   && !strcmp(argv[2], "start")) {
+		ssv_dbg_ctrl_hci->irq_enable = 1;
+		strcat(ssv6xxx_result_buf, "irq debug start\n");
+		return 0;
+	}
+#endif
+	else {
+		strcat(ssv6xxx_result_buf,
+		       "hci [txq|rxq] [show]\nhci [isr_time] [start|stop|show]\n\n");
+		return 0;
+	}
+	return -1;
+}
+
+static int ssv_cmd_hwq(int argc, char *argv[])
+{
+#undef GET_FFO0_CNT
+#undef GET_FFO1_CNT
+#undef GET_FFO2_CNT
+#undef GET_FFO3_CNT
+#undef GET_FFO4_CNT
+#undef GET_FFO5_CNT
+#undef GET_FFO6_CNT
+#undef GET_FFO7_CNT
+#undef GET_FFO8_CNT
+#undef GET_FFO9_CNT
+#undef GET_FFO10_CNT
+#undef GET_FFO11_CNT
+#undef GET_FFO12_CNT
+#undef GET_FFO13_CNT
+#undef GET_FFO14_CNT
+#undef GET_FFO15_CNT
+#undef GET_FF0_CNT
+#undef GET_FF1_CNT
+#undef GET_FF3_CNT
+#undef GET_FF5_CNT
+#undef GET_FF6_CNT
+#undef GET_FF7_CNT
+#undef GET_FF8_CNT
+#undef GET_FF9_CNT
+#undef GET_FF10_CNT
+#undef GET_FF11_CNT
+#undef GET_FF12_CNT
+#undef GET_FF13_CNT
+#undef GET_FF14_CNT
+#undef GET_FF15_CNT
+#undef GET_FF4_CNT
+#undef GET_FF2_CNT
+#undef GET_TX_ID_ALC_LEN
+#undef GET_RX_ID_ALC_LEN
+#undef GET_AVA_TAG
+#define GET_FFO0_CNT ((value & 0x0000001f ) >> 0)
+#define GET_FFO1_CNT ((value & 0x000003e0 ) >> 5)
+#define GET_FFO2_CNT ((value & 0x00000c00 ) >> 10)
+#define GET_FFO3_CNT ((value & 0x000f8000 ) >> 15)
+#define GET_FFO4_CNT ((value & 0x00300000 ) >> 20)
+#define GET_FFO5_CNT ((value & 0x0e000000 ) >> 25)
+#define GET_FFO6_CNT ((value1 & 0x0000000f ) >> 0)
+#define GET_FFO7_CNT ((value1 & 0x000003e0 ) >> 5)
+#define GET_FFO8_CNT ((value1 & 0x00007c00 ) >> 10)
+#define GET_FFO9_CNT ((value1 & 0x000f8000 ) >> 15)
+#define GET_FFO10_CNT ((value1 & 0x00f00000 ) >> 20)
+#define GET_FFO11_CNT ((value1 & 0x3e000000 ) >> 25)
+#define GET_FFO12_CNT ((value2 & 0x00000007 ) >> 0)
+#define GET_FFO13_CNT ((value2 & 0x00000060 ) >> 5)
+#define GET_FFO14_CNT ((value2 & 0x00000c00 ) >> 10)
+#define GET_FFO15_CNT ((value2 & 0x001f8000 ) >> 15)
+#define GET_FF0_CNT ((value & 0x0000001f ) >> 0)
+#define GET_FF1_CNT ((value & 0x000001e0 ) >> 5)
+#define GET_FF3_CNT ((value & 0x00003800 ) >> 11)
+#define GET_FF5_CNT ((value & 0x000e0000 ) >> 17)
+#define GET_FF6_CNT ((value & 0x00700000 ) >> 20)
+#define GET_FF7_CNT ((value & 0x03800000 ) >> 23)
+#define GET_FF8_CNT ((value & 0x1c000000 ) >> 26)
+#define GET_FF9_CNT ((value & 0xe0000000 ) >> 29)
+#define GET_FF10_CNT ((value1 & 0x00000007 ) >> 0)
+#define GET_FF11_CNT ((value1 & 0x00000038 ) >> 3)
+#define GET_FF12_CNT ((value1 & 0x000001c0 ) >> 6)
+#define GET_FF13_CNT ((value1 & 0x00000600 ) >> 9)
+#define GET_FF14_CNT ((value1 & 0x00001800 ) >> 11)
+#define GET_FF15_CNT ((value1 & 0x00006000 ) >> 13)
+#define GET_FF4_CNT ((value1 & 0x000f8000 ) >> 15)
+#define GET_FF2_CNT ((value1 & 0x00700000 ) >> 20)
+#define GET_TX_ID_ALC_LEN ((value & 0x0003fe00 ) >> 9)
+#define GET_RX_ID_ALC_LEN ((value & 0x07fc0000 ) >> 18)
+#define GET_AVA_TAG ((value1 & 0x01ff0000 ) >> 16)
+	u32 addr, value, value1, value2;
+	char temp_str[512];
+	addr = ADR_RD_FFOUT_CNT1;
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+	addr = ADR_RD_FFOUT_CNT2;
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
+	addr = ADR_RD_FFOUT_CNT3;
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value2)) ;
+	sprintf(temp_str,
+		"\n[TAG]  MCU - HCI - SEC -  RX - MIC - TX0 - TX1 - TX2 - TX3 - TX4 - SEC - MIC - TSH\n");
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str,
+		"OUTPUT %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
+		GET_FFO0_CNT, GET_FFO1_CNT, GET_FFO3_CNT, GET_FFO4_CNT,
+		GET_FFO5_CNT, GET_FFO6_CNT, GET_FFO7_CNT, GET_FFO8_CNT,
+		GET_FFO9_CNT, GET_FFO10_CNT, GET_FFO11_CNT, GET_FFO12_CNT,
+		GET_FFO15_CNT);
+	strcat(ssv6xxx_result_buf, temp_str);
+	addr = ADR_RD_IN_FFCNT1;
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+	addr = ADR_RD_IN_FFCNT2;
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
+	sprintf(temp_str,
+		"INPUT  %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d - %3d\n",
+		GET_FF0_CNT, GET_FF1_CNT, GET_FF3_CNT, GET_FF4_CNT, GET_FF5_CNT,
+		GET_FF6_CNT, GET_FF7_CNT, GET_FF8_CNT, GET_FF9_CNT,
+		GET_FF10_CNT, GET_FF11_CNT, GET_FF12_CNT, GET_FF15_CNT);
+	strcat(ssv6xxx_result_buf, temp_str);
+	addr = ADR_ID_LEN_THREADSHOLD2;
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+	addr = ADR_TAG_STATUS;
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value1)) ;
+	sprintf(temp_str, "TX[%d]RX[%d]AVA[%d]\n", GET_TX_ID_ALC_LEN,
+		GET_RX_ID_ALC_LEN, GET_AVA_TAG);
+	strcat(ssv6xxx_result_buf, temp_str);
+	return 0;
+}
+
+#ifdef CONFIG_P2P_NOA
+static struct ssv6xxx_p2p_noa_param cmd_noa_param = {
+	50,
+	100,
+	0x12345678,
+	1,
+	255,
+	{0x4c, 0xe6, 0x76, 0xa2, 0x4e, 0x7c}
+};
+
+void noa_dump(char *temp_str)
+{
+	sprintf(temp_str,
+		"NOA Parameter:\nEnable=%d\nInterval=%d\nDuration=%d\nStart_time=0x%08x\nCount=%d\nAddr=[%02x:%02x:%02x:%02x:%02x:%02x]\n",
+		cmd_noa_param.enable, cmd_noa_param.interval,
+		cmd_noa_param.duration, cmd_noa_param.start_time,
+		cmd_noa_param.count, cmd_noa_param.addr[0],
+		cmd_noa_param.addr[1], cmd_noa_param.addr[2],
+		cmd_noa_param.addr[3], cmd_noa_param.addr[4],
+		cmd_noa_param.addr[5]);
+	strcat(ssv6xxx_result_buf, temp_str);
+}
+
+void ssv6xxx_send_noa_cmd(struct ssv_softc *sc,
+			  struct ssv6xxx_p2p_noa_param *p2p_noa_param)
+{
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	int retry_cnt = 5;
+	skb =
+	    ssvdevice_skb_alloc(HOST_CMD_HDR_LEN +
+				sizeof(struct ssv6xxx_p2p_noa_param));
+	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct ssv6xxx_p2p_noa_param);
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_SET_NOA;
+	host_cmd->len = skb->data_len;
+	memcpy(host_cmd->dat32, p2p_noa_param,
+	       sizeof(struct ssv6xxx_p2p_noa_param));
+	while ((HCI_SEND_CMD(sc->sh, skb) != 0) && (retry_cnt)) {
+		pr_debug("NOA cmd retry=%d\n", retry_cnt);
+		retry_cnt--;
+	}
+	ssvdevice_skb_free(skb);
+}
+
+static int ssv_cmd_noa(int argc, char *argv[])
+{
+	char temp_str[512];
+	char *endp;
+	if (argc == 2 && !strcmp(argv[1], "show")) {
+		;
+	} else if (argc == 3 && !strcmp(argv[1], "duration")) {
+		cmd_noa_param.duration = simple_strtoul(argv[2], &endp, 0);
+	} else if (argc == 3 && !strcmp(argv[1], "interval")) {
+		cmd_noa_param.interval = simple_strtoul(argv[2], &endp, 0);
+	} else if (argc == 3 && !strcmp(argv[1], "start")) {
+		cmd_noa_param.start_time = simple_strtoul(argv[2], &endp, 0);
+	} else if (argc == 3 && !strcmp(argv[1], "enable")) {
+		cmd_noa_param.enable = simple_strtoul(argv[2], &endp, 0);
+	} else if (argc == 3 && !strcmp(argv[1], "count")) {
+		cmd_noa_param.count = simple_strtoul(argv[2], &endp, 0);
+	} else if (argc == 8 && !strcmp(argv[1], "addr")) {
+		cmd_noa_param.addr[0] = simple_strtoul(argv[2], &endp, 16);
+		cmd_noa_param.addr[1] = simple_strtoul(argv[3], &endp, 16);
+		cmd_noa_param.addr[2] = simple_strtoul(argv[4], &endp, 16);
+		cmd_noa_param.addr[3] = simple_strtoul(argv[5], &endp, 16);
+		cmd_noa_param.addr[4] = simple_strtoul(argv[6], &endp, 16);
+		cmd_noa_param.addr[5] = simple_strtoul(argv[7], &endp, 16);
+	} else if (argc == 2 && !strcmp(argv[1], "send")) {
+		ssv6xxx_send_noa_cmd(ssv_dbg_sc, &cmd_noa_param);
+	} else {
+		sprintf(temp_str, "## wrong command\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	}
+	noa_dump(temp_str);
+	return 0;
+}
+#endif
+static int ssv_cmd_mib(int argc, char *argv[])
+{
+	u32 addr, value;
+	char temp_str[512];
+	int i;
+	if (argc == 2 && !strcmp(argv[1], "reset")) {
+		addr = MIB_REG_BASE;
+		value = 0x0;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, MIB_REG_BASE, value)) ;
+		value = 0xffffffff;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, MIB_REG_BASE, value)) ;
+		value = 0x0;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0023F8, value)) ;
+		value = 0x100000;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0023F8, value)) ;
+		value = 0x0;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0043F8, value)) ;
+		value = 0x100000;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE0043F8, value)) ;
+		value = 0x0;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE000088, value)) ;
+		value = 0x80000000;
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, 0xCE000088, value)) ;
+		sprintf(temp_str, " => MIB reseted\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if (argc == 2 && !strcmp(argv[1], "list")) {
+		addr = MIB_REG_BASE;
+		for (i = 0; i < 120; i++, addr += 4) {
+			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+			sprintf(temp_str, "%08x ", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+			if (((i + 1) & 0x07) == 0)
+				strcat(ssv6xxx_result_buf, "\n");
+		}
+		strcat(ssv6xxx_result_buf, "\n");
+	} else if (argc == 2 && strcmp(argv[1], "rx") == 0) {
+		sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\t\t%-10s\n",
+			"MRX_FCS_SUCC", "MRX_FCS_ERR", "MRX_ALC_FAIL",
+			"MRX_MISS");
+		strcat(ssv6xxx_result_buf, temp_str);
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_MRX_FCS_SUCC, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_FCS_ERR, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_MRX_ALC_FAIL, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_MISS, &value)) {
+			sprintf(temp_str, "[%08x]\n", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\t%-10s\n",
+				"MRX_MB_MISS", "MRX_NIDLE_MISS",
+				"DBG_LEN_ALC_FAIL", "DBG_LEN_CRC_FAIL");
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_MRX_MB_MISS, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_MRX_NIDLE_MISS, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_DBG_LEN_ALC_FAIL, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_DBG_LEN_CRC_FAIL, &value)) {
+			sprintf(temp_str, "[%08x]\n\n", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_DBG_AMPDU_PASS, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_DBG_AMPDU_FAIL, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_ID_ALC_FAIL1, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, ADR_ID_ALC_FAIL2, &value)) {
+			sprintf(temp_str, "[%08x]\n\n", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "PHY B mode:\n");
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\n",
+				"CRC error", "CCA", "counter");
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0023E8, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value & 0xffff);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0023EC, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", (value >> 16) & 0xffff);
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "[%08x]\t\t\n\n", value & 0xffff);
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "PHY G/N mode:\n");
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "%-10s\t\t%-10s\t\t%-10s\n",
+				"CRC error", "CCA", "counter");
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0043E8, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", value & 0xffff);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+		if (SSV_REG_READ1(ssv6xxx_debug_ifops, 0xCE0043EC, &value)) {
+			sprintf(temp_str, "[%08x]\t\t", (value >> 16) & 0xffff);
+			strcat(ssv6xxx_result_buf, temp_str);
+			sprintf(temp_str, "[%08x]\t\t\n\n", value & 0xffff);
+			strcat(ssv6xxx_result_buf, temp_str);
+		}
+	} else {
+		sprintf(temp_str, "mib [reset|list|rx]\n\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	}
+	return 0;
+}
+
+static int ssv_cmd_sdio(int argc, char *argv[])
+{
+	u32 addr, value;
+	char temp_str[512], *endp;
+	int ret = 0;
+	if (argc == 4 && !strcmp(argv[1], "reg") && !strcmp(argv[2], "r")) {
+		addr = simple_strtoul(argv[3], &endp, 16);
+		if (!ssv6xxx_debug_ifops->ifops->cmd52_read) {
+			sprintf(temp_str,
+				"The interface doesn't provide cmd52 read\n");
+			strcat(ssv6xxx_result_buf, temp_str);
+			return 0;
+		}
+		ret =
+		    ssv6xxx_debug_ifops->ifops->cmd52_read(ssv6xxx_debug_ifops->
+							   dev, addr, &value);
+		if (ret >= 0) {
+			sprintf(temp_str, "  ==> %x\n", value);
+			strcat(ssv6xxx_result_buf, temp_str);
+			return 0;
+		}
+	} else if (argc == 5 && !strcmp(argv[1], "reg")
+		   && !strcmp(argv[2], "w")) {
+		addr = simple_strtoul(argv[3], &endp, 16);
+		value = simple_strtoul(argv[4], &endp, 16);
+		if (!ssv6xxx_debug_ifops->ifops->cmd52_write) {
+			sprintf(temp_str,
+				"The interface doesn't provide cmd52 write\n");
+			strcat(ssv6xxx_result_buf, temp_str);
+			return 0;
+		}
+		ret =
+		    ssv6xxx_debug_ifops->ifops->
+		    cmd52_write(ssv6xxx_debug_ifops->dev, addr, value);
+		if (ret >= 0) {
+			sprintf(temp_str, "  ==> write odne.\n");
+			strcat(ssv6xxx_result_buf, temp_str);
+			return 0;
+		}
+	}
+	sprintf(temp_str, "sdio cmd52 fail: %d\n", ret);
+	strcat(ssv6xxx_result_buf, temp_str);
+	return 0;
+}
+
+static struct ssv6xxx_iqk_cfg cmd_iqk_cfg = {
+	SSV6XXX_IQK_CFG_XTAL_26M,
+	SSV6XXX_IQK_CFG_PA_DEF,
+	0,
+	0,
+	26,
+	3,
+	0x75,
+	0x75,
+	0x80,
+	0x80,
+	SSV6XXX_IQK_CMD_INIT_CALI,
+	{SSV6XXX_IQK_TEMPERATURE
+	 + SSV6XXX_IQK_RXDC
+	 + SSV6XXX_IQK_RXRC
+	 + SSV6XXX_IQK_TXDC + SSV6XXX_IQK_TXIQ + SSV6XXX_IQK_RXIQ},
+};
+
+static int ssv_cmd_iqk(int argc, char *argv[])
+{
+	char temp_str[512], *endp;
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	u32 rxcnt_total, rxcnt_error;
+	sprintf(temp_str, "# got iqk command\n");
+	strcat(ssv6xxx_result_buf, temp_str);
+	if ((argc == 3) && (strcmp(argv[1], "cfg-pa") == 0)) {
+		cmd_iqk_cfg.cfg_pa = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## set cfg_pa as %d\n", cmd_iqk_cfg.cfg_pa);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if ((argc == 3) && (strcmp(argv[1], "cfg-tssi-trgt") == 0)) {
+		cmd_iqk_cfg.cfg_tssi_trgt = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## set cfg_tssi_trgt as %d\n",
+			cmd_iqk_cfg.cfg_tssi_trgt);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else if ((argc == 3) && (strcmp(argv[1], "init-cali") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_INIT_CALI;
+		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do init-cali\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-load") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD;
+		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do rtbl-load\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-load-def") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_LOAD_DEF;
+		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do rtbl-load\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-reset") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_RESET;
+		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do rtbl-reset\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-set") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_SET;
+		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do rtbl-set\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "rtbl-export") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_RTBL_EXPORT;
+		cmd_iqk_cfg.fx_sel = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do rtbl-export\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "tk-evm") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_EVM;
+		cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do tk-evm\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "tk-tone") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_TONE;
+		cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do tk-tone\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 3) && (strcmp(argv[1], "channel") == 0)) {
+		cmd_iqk_cfg.cmd_sel = SSV6XXX_IQK_CMD_TK_CHCH;
+		cmd_iqk_cfg.argv = simple_strtoul(argv[2], &endp, 0);
+		sprintf(temp_str, "## do change channel\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else if ((argc == 2) && (strcmp(argv[1], "tk-rxcnt-report") == 0)) {
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, 0xCE0043E8, &rxcnt_error)) ;
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, 0xCE0043EC, &rxcnt_total)) ;
+		sprintf(temp_str, "## GN Rx error rate = (%06d/%06d)\n",
+			rxcnt_error, rxcnt_total);
+		strcat(ssv6xxx_result_buf, temp_str);
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, 0xCE0023E8, &rxcnt_error)) ;
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, 0xCE0023EC, &rxcnt_total)) ;
+		sprintf(temp_str, "## B Rx error rate = (%06d/%06d)\n",
+			rxcnt_error, rxcnt_total);
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	} else {
+		sprintf(temp_str, "## invalid iqk command\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "## cmd: cfg-pa/cfg-tssi-trgt\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str,
+			"## cmd: init-cali/rtbl-load/rtbl-load-def/rtbl-reset/rtbl-set/rtbl-export/tk-evm/tk-tone/tk-channel\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "## fx_sel: 0x0008: RXDC\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "           0x0010: RXRC\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "           0x0020: TXDC\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "           0x0040: TXIQ\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "           0x0080: RXIQ\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "           0x0100: TSSI\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		sprintf(temp_str, "           0x0200: PAPD\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+		return 0;
+	}
+	skb =
+	    ssvdevice_skb_alloc(HOST_CMD_HDR_LEN + IQK_CFG_LEN +
+				PHY_SETTING_SIZE + RF_SETTING_SIZE);
+	if (skb == NULL) {
+		pr_err("ssv command ssvdevice_skb_alloc failure\n");
+		return 0;
+	}
+	if ((PHY_SETTING_SIZE > MAX_PHY_SETTING_TABLE_SIZE) ||
+	    (RF_SETTING_SIZE > MAX_RF_SETTING_TABLE_SIZE)) {
+		pr_err("Please check RF or PHY table size\n");
+		BUG_ON(1);
+		return 0;
+	}
+	skb->data_len =
+	    HOST_CMD_HDR_LEN + IQK_CFG_LEN + PHY_SETTING_SIZE + RF_SETTING_SIZE;
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_INIT_CALI;
+	host_cmd->len = skb->data_len;
+	cmd_iqk_cfg.phy_tbl_size = PHY_SETTING_SIZE;
+	cmd_iqk_cfg.rf_tbl_size = RF_SETTING_SIZE;
+	memcpy(host_cmd->dat32, &cmd_iqk_cfg, IQK_CFG_LEN);
+	memcpy(host_cmd->dat8 + IQK_CFG_LEN, phy_setting, PHY_SETTING_SIZE);
+	memcpy(host_cmd->dat8 + IQK_CFG_LEN + PHY_SETTING_SIZE, asic_rf_setting,
+	       RF_SETTING_SIZE);
+	if (ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb) == 0) {
+		sprintf(temp_str, "## hci send cmd success\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	} else {
+		sprintf(temp_str, "## hci send cmd fail\n");
+		strcat(ssv6xxx_result_buf, temp_str);
+	}
+	ssvdevice_skb_free(skb);
+	return 0;
+}
+
+#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
+    (((a) & 0xff00ff00) >> 8))
+#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
+static int ssv_cmd_version(int argc, char *argv[])
+{
+	char temp_str[256];
+	u32 regval;
+	u64 chip_tag = 0;
+	char chip_id[24] = "";
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_IC_TIME_TAG_1, &regval)) ;
+	chip_tag = ((u64) regval << 32);
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_IC_TIME_TAG_0, &regval)) ;
+	chip_tag |= (regval);
+	sprintf(temp_str, "CHIP TAG: %llx \n", chip_tag);
+	strcat(ssv6xxx_result_buf, temp_str);
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_3, &regval)) ;
+	*((u32 *) & chip_id[0]) = (u32) LONGSWAP(regval);
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_2, &regval)) ;
+	*((u32 *) & chip_id[4]) = (u32) LONGSWAP(regval);
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_1, &regval)) ;
+	*((u32 *) & chip_id[8]) = (u32) LONGSWAP(regval);
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_CHIP_ID_0, &regval)) ;
+	*((u32 *) & chip_id[12]) = (u32) LONGSWAP(regval);
+	sprintf(temp_str, "CHIP ID: %s \n", chip_id);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "# current Software mac version: %d\n",
+		ssv_root_version);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "SVN ROOT URL %s \n", SSV_ROOT_URl);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "COMPILER HOST %s \n", COMPILERHOST);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "COMPILER DATE %s \n", COMPILERDATE);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "COMPILER OS %s \n", COMPILEROS);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "COMPILER OS ARCH %s \n", COMPILEROSARCH);
+	strcat(ssv6xxx_result_buf, temp_str);
+	if (SSV_REG_READ1(ssv6xxx_debug_ifops, FW_VERSION_REG, &regval)) ;
+	sprintf(temp_str, "Firmware image version: %d\n", regval);
+	strcat(ssv6xxx_result_buf, temp_str);
+	sprintf(temp_str, "\n[Compiler Option!!]\n");
+	strcat(ssv6xxx_result_buf, temp_str);
+	return 0;
+}
+
+static int ssv_cmd_tool(int argc, char *argv[])
+{
+	u32 addr, value, count;
+	char tmpbf[12], *endp;
+	int s;
+	if (argc == 4 && strcmp(argv[1], "w") == 0) {
+		addr = simple_strtoul(argv[2], &endp, 16);
+		value = simple_strtoul(argv[3], &endp, 16);
+		if (SSV_REG_WRITE1(ssv6xxx_debug_ifops, addr, value)) ;
+		sprintf(ssv6xxx_result_buf, "ok");
+		return 0;
+	}
+	if ((argc == 4 || argc == 3) && strcmp(argv[1], "r") == 0) {
+		count = (argc == 3) ? 1 : simple_strtoul(argv[3], &endp, 10);
+		addr = simple_strtoul(argv[2], &endp, 16);
+		for (s = 0; s < count; s++, addr += 4) {
+			if (SSV_REG_READ1(ssv6xxx_debug_ifops, addr, &value)) ;
+			sprintf(tmpbf, "%08x\n", value);
+			strcat(ssv6xxx_result_buf, tmpbf);
+		}
+		return 0;
+	}
+	return -1;
+}
+
+struct _ssv6xxx_txtput {
+	struct task_struct *txtput_tsk;
+	struct sk_buff *skb;
+	u32 size_per_frame;
+	u32 loop_times;
+	u32 occupied_tx_pages;
+};
+struct _ssv6xxx_txtput *ssv6xxx_txtput;
+struct _ssv6xxx_txtput ssv_txtput = { NULL, NULL, 0, 0, 0 };
+
+static int txtput_thread_m2(void *data)
+{
+#define Q_DELAY_MS 20
+	struct sk_buff *skb = NULL;
+	struct ssv6200_tx_desc *tx_desc;
+	int qlen = 0, max_qlen, q_delay_urange[2];
+	max_qlen =
+	    (200 * 1000 / 8 * Q_DELAY_MS) / ssv6xxx_txtput->size_per_frame;
+	q_delay_urange[0] = Q_DELAY_MS * 1000;
+	q_delay_urange[1] = q_delay_urange[0] + 1000;
+	pr_debug("max_qlen: %d\n", max_qlen);
+	while (!kthread_should_stop() && ssv6xxx_txtput->loop_times > 0) {
+		ssv6xxx_txtput->loop_times--;
+		skb = ssvdevice_skb_alloc(ssv6xxx_txtput->size_per_frame);
+		if (skb == NULL) {
+			pr_debug("ssv command txtput_generate_m2 "
+			       "ssvdevice_skb_alloc fail!!!\n");
+			goto end;
+		}
+		skb->data_len = ssv6xxx_txtput->size_per_frame;
+		skb->len = ssv6xxx_txtput->size_per_frame;
+		tx_desc = (struct ssv6200_tx_desc *)skb->data;
+		memset((void *)tx_desc, 0xff, SSV6XXX_TX_DESC_LEN);
+		tx_desc->len = skb->len;
+		tx_desc->c_type = M2_TXREQ;
+		tx_desc->fCmd = (M_ENG_CPU << 4) | M_ENG_HWHCI;
+		tx_desc->reason = ID_TRAP_SW_TXTPUT;
+		qlen = ssv_dbg_ctrl_hci->shi->hci_ops->hci_tx(skb, 0, 0);
+		if (qlen >= max_qlen) {
+			usleep_range(q_delay_urange[0], q_delay_urange[1]);
+		}
+	}
+ end:
+	ssv6xxx_txtput->txtput_tsk = NULL;
+	return 0;
+}
+
+static int txtput_thread(void *data)
+{
+	struct sk_buff *skb = ssv6xxx_txtput->skb;
+	struct ssv6xxx_hci_txq_info2 txq_info2;
+	u32 ret = 0, free_tx_page;
+	int send_cnt;
+	unsigned long start_time, end_time, throughput, time_elapse;
+	throughput =
+	    ssv6xxx_txtput->loop_times * ssv6xxx_txtput->size_per_frame * 8;
+	start_time = jiffies;
+	while (!kthread_should_stop() && ssv6xxx_txtput->loop_times > 0) {
+		ret =
+		    SSV_REG_READ1(ssv6xxx_debug_ifops, ADR_TX_ID_ALL_INFO2,
+				  (u32 *) & txq_info2);
+		if (ret < 0) {
+			pr_debug("%s, read ADR_TX_ID_ALL_INFO2 failed\n",
+			       __func__);
+			goto end;
+		}
+		free_tx_page =
+		    SSV6200_PAGE_TX_THRESHOLD - txq_info2.tx_use_page;
+		send_cnt = free_tx_page / ssv6xxx_txtput->occupied_tx_pages;
+		while (send_cnt > 0 && ssv6xxx_txtput->loop_times > 0) {
+			send_cnt--;
+			ssv6xxx_txtput->loop_times--;
+			ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb);
+		}
+	}
+	end_time = jiffies;
+	ssvdevice_skb_free(skb);
+	time_elapse = ((end_time - start_time) * 1000) / HZ;
+	if (time_elapse > 0) {
+		throughput = throughput / time_elapse;
+		pr_debug("duration %ldms, avg. throughput %d Kbps\n", time_elapse,
+		       (int)throughput);
+	}
+ end:
+	ssv6xxx_txtput->txtput_tsk = NULL;
+	return 0;
+}
+
+int txtput_generate_m2(u32 size_per_frame, u32 loop_times)
+{
+	ssv6xxx_txtput->size_per_frame = size_per_frame;
+	ssv6xxx_txtput->loop_times = loop_times;
+	ssv6xxx_txtput->txtput_tsk =
+	    kthread_run(txtput_thread_m2, NULL, "txtput_thread_m2");
+	return 0;
+}
+
+int txtput_generate_host_cmd(u32 size_per_frame, u32 loop_times)
+{
+#define PAGESIZE 256
+	struct cfg_host_cmd *host_cmd;
+	struct sk_buff *skb;
+	skb = ssvdevice_skb_alloc(size_per_frame);
+	if (skb == NULL) {
+		pr_debug
+		    ("ssv command txtput_generate_host_cmd ssvdevice_skb_alloc fail!!!\n");
+		return 0;
+	}
+	skb->data_len = size_per_frame;
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = TEST_CMD;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_TX_TPUT;
+	host_cmd->len = skb->data_len;
+	memcpy(host_cmd->dat32, skb->data, size_per_frame);
+	ssv6xxx_txtput->occupied_tx_pages =
+	    (size_per_frame / PAGESIZE) + ((size_per_frame % PAGESIZE) != 0);
+	ssv6xxx_txtput->size_per_frame = size_per_frame;
+	ssv6xxx_txtput->loop_times = loop_times;
+	ssv6xxx_txtput->skb = skb;
+	ssv6xxx_txtput->txtput_tsk =
+	    kthread_run(txtput_thread, NULL, "txtput_thread");
+	return 0;
+}
+
+int txtput_tsk_cleanup(void)
+{
+	int ret = 0;
+	if (ssv6xxx_txtput->txtput_tsk) {
+		ret = kthread_stop(ssv6xxx_txtput->txtput_tsk);
+		ssv6xxx_txtput->txtput_tsk = NULL;
+	}
+	return ret;
+}
+
+int watchdog_controller(struct ssv_hw *sh, u8 flag)
+{
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	int ret = 0;
+	pr_debug("watchdog_controller %d\n", flag);
+	skb = ssvdevice_skb_alloc(HOST_CMD_HDR_LEN);
+	if (skb == NULL) {
+		pr_err("init watchdog_controller failure\n");
+		return (-1);
+	}
+	skb->data_len = HOST_CMD_HDR_LEN;
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) flag;
+	host_cmd->len = skb->data_len;
+	sh->hci.hci_ops->hci_send_cmd(skb);
+	ssvdevice_skb_free(skb);
+	return ret;
+}
+
+static int ssv_cmd_txtput(int argc, char *argv[])
+{
+	char tmpbf[64], *endp;
+	u32 size_per_frame, loop_times, pkt_type;
+	ssv6xxx_txtput = &ssv_txtput;
+	if (argc == 2 && !strcmp(argv[1], "stop")) {
+		txtput_tsk_cleanup();
+		return 0;
+	}
+	if (argc != 4) {
+		sprintf(tmpbf, "* txtput stop\n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		sprintf(tmpbf, "* txtput [type] [size] [frames]\n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		sprintf(tmpbf, "    type(packet type):\n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		sprintf(tmpbf, "         0 = host_cmd\n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		sprintf(tmpbf, "         1 = m2_type \n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		sprintf(tmpbf, " EX: txtput 1 14000 9999 \n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		return 0;
+	}
+	pkt_type = simple_strtoul(argv[1], &endp, 10);
+	size_per_frame = simple_strtoul(argv[2], &endp, 10);
+	loop_times = simple_strtoul(argv[3], &endp, 10);
+	sprintf(tmpbf, "type&size&frames:%d&%d&%d\n", pkt_type, size_per_frame,
+		loop_times);
+	strcat(ssv6xxx_result_buf, tmpbf);
+	if (ssv6xxx_txtput->txtput_tsk) {
+		sprintf(tmpbf, "txtput already in progress\n");
+		strcat(ssv6xxx_result_buf, tmpbf);
+		return 0;
+	}
+	watchdog_controller(((struct ssv_softc *)ssv_dbg_sc)->sh,
+			    (u8) SSV6XXX_HOST_CMD_WATCHDOG_STOP);
+	((struct ssv_softc *)ssv_dbg_sc)->watchdog_flag = WD_SLEEP;
+	if (pkt_type)
+		txtput_generate_m2(size_per_frame + SSV6XXX_TX_DESC_LEN,
+				   loop_times);
+	else
+		txtput_generate_host_cmd(size_per_frame + HOST_CMD_HDR_LEN,
+					 loop_times);
+	return 0;
+}
+
+static int ssv_cmd_rxtput(int argc, char *argv[])
+{
+	struct sk_buff *skb;
+	struct cfg_host_cmd *host_cmd;
+	struct sdio_rxtput_cfg cmd_rxtput_cfg;
+	char tmpbf[32], *endp;
+	if (argc != 3) {
+		sprintf(ssv6xxx_result_buf, "rxtput [size] [frames]\n");
+		return 0;
+	}
+	skb =
+	    ssvdevice_skb_alloc(HOST_CMD_HDR_LEN +
+				sizeof(struct sdio_rxtput_cfg));
+	if (skb == NULL) {
+		pr_err("ssv command ssvdevice_skb_alloc fail\n");
+		return 0;
+	}
+	watchdog_controller(((struct ssv_softc *)ssv_dbg_sc)->sh,
+			    (u8) SSV6XXX_HOST_CMD_WATCHDOG_STOP);
+	((struct ssv_softc *)ssv_dbg_sc)->watchdog_flag = WD_SLEEP;
+	cmd_rxtput_cfg.size_per_frame = simple_strtoul(argv[1], &endp, 10);
+	cmd_rxtput_cfg.total_frames = simple_strtoul(argv[2], &endp, 10);
+	sprintf(tmpbf, "size&frames:%d&%d\n", cmd_rxtput_cfg.size_per_frame,
+		cmd_rxtput_cfg.total_frames);
+	strcat(ssv6xxx_result_buf, tmpbf);
+	skb->data_len = HOST_CMD_HDR_LEN + sizeof(struct sdio_rxtput_cfg);
+	skb->len = skb->data_len;
+	host_cmd = (struct cfg_host_cmd *)skb->data;
+	host_cmd->c_type = HOST_CMD;
+	host_cmd->h_cmd = (u8) SSV6XXX_HOST_CMD_RX_TPUT;
+	host_cmd->len = skb->data_len;
+	memcpy(host_cmd->dat32, &cmd_rxtput_cfg,
+	       sizeof(struct sdio_rxtput_cfg));
+	if (ssv_dbg_ctrl_hci->shi->hci_ops->hci_send_cmd(skb) == 0) {
+		strcat(ssv6xxx_result_buf,
+		       "## hci cmd was sent successfully\n");
+	} else {
+		strcat(ssv6xxx_result_buf, "## hci cmd was sent failed\n");
+	}
+	ssvdevice_skb_free(skb);
+	return 0;
+}
+
+static int ssv_cmd_check(int argc, char *argv[])
+{
+	u32 size, i, j, x, y, id, value, address, id_value;
+	char *endp;
+	u32 id_base_address[4];
+	id_base_address[0] = 0xcd010008;
+	id_base_address[1] = 0xcd01000c;
+	id_base_address[2] = 0xcd010054;
+	id_base_address[3] = 0xcd010058;
+	if (argc != 2) {
+		sprintf(ssv6xxx_result_buf, "check [packet size]\n");
+		return 0;
+	}
+	size = simple_strtoul(argv[1], &endp, 10);
+	size = size >> 2;
+	for (x = 0; x < 4; x++) {
+		if (SSV_REG_READ1
+		    (ssv6xxx_debug_ifops, id_base_address[x], &id_value)) ;
+		for (y = 0; y < 32 && id_value; y++, id_value >>= 1) {
+			if (id_value & 0x1) {
+				id = 32 * x + y;
+				address = 0x80000000 + (id << 16);
+				{
+					for (i = 0; i < size; i += 8) {
+						if (SSV_REG_READ1
+						    (ssv6xxx_debug_ifops,
+						     address, &value)) ;
+						address += 4;
+						for (j = 1; j < 8; j++) {
+							if (SSV_REG_READ1
+							    (ssv6xxx_debug_ifops,
+							     address, &value)) ;
+							address += 4;
+						}
+					}
+				}
+			}
+		}
+	}
+	return 0;
+}
+
+struct ssv_cmd_table cmd_table[] = {
+	{"help", ssv_cmd_help, "ssv6200 command usage."},
+	{"-h", ssv_cmd_help, "ssv6200 command usage."},
+	{"--help", ssv_cmd_help, "ssv6200 command usage."},
+	{"reg", ssv_cmd_reg, "ssv6200 register read/write."},
+	{"cfg", ssv_cmd_cfg, "ssv6200 configuration."},
+	{"sta", ssv_cmd_sta, "svv6200 station info."},
+	{"dump", ssv_cmd_dump, "dump ssv6200 tables."},
+	{"hwq", ssv_cmd_hwq, "hardware queue staus"},
+#ifdef CONFIG_P2P_NOA
+	{"noa", ssv_cmd_noa, "config noa param"},
+#endif
+	{"irq", ssv_cmd_irq, "get sdio irq status."},
+	{"mac", ssv_cmd_mac, "ieee80211 swmac."},
+	{"hci", ssv_cmd_hci, "HCI command."},
+	{"sdio", ssv_cmd_sdio, "SDIO command."},
+	{"iqk", ssv_cmd_iqk, "iqk command"},
+	{"version", ssv_cmd_version, "version information"},
+	{"mib", ssv_cmd_mib, "mib counter related"},
+	{"tool", ssv_cmd_tool, "ssv6200 tool register read/write."},
+	{"rxtput", ssv_cmd_rxtput, "test rx sdio throughput"},
+	{"txtput", ssv_cmd_txtput, "test tx sdio throughput"},
+	{"check", ssv_cmd_check, "dump all allocate packet buffer"},
+	{NULL, NULL, NULL},
+};
+
+int ssv_cmd_submit(char *cmd)
+{
+	struct ssv_cmd_table *sc_tbl;
+	char *pch, ch;
+	int ret;
+	ssv6xxx_debug_ifops = (void *)ssv6xxx_ifdebug_info;
+	strcpy(sg_cmd_buffer, cmd);
+	for (sg_argc = 0, ch = 0, pch = sg_cmd_buffer;
+	     (*pch != 0x00) && (sg_argc < CLI_ARG_SIZE); pch++) {
+		if ((ch == 0) && (*pch != ' ')) {
+			ch = 1;
+			sg_argv[sg_argc] = pch;
+		}
+		if ((ch == 1) && (*pch == ' ')) {
+			*pch = 0x00;
+			ch = 0;
+			sg_argc++;
+		}
+	}
+	if (ch == 1) {
+		sg_argc++;
+	} else if (sg_argc > 0) {
+		*(pch - 1) = ' ';
+	}
+	if (sg_argc > 0) {
+		for (sc_tbl = cmd_table; sc_tbl->cmd; sc_tbl++) {
+			if (!strcmp(sg_argv[0], sc_tbl->cmd)) {
+				if ((sc_tbl->cmd_func_ptr != ssv_cmd_cfg) &&
+				    (!ssv6xxx_debug_ifops->dev ||
+				     !ssv6xxx_debug_ifops->ifops ||
+				     !ssv6xxx_debug_ifops->pdev)) {
+					strcpy(ssv6xxx_result_buf,
+					       "Member of ssv6xxx_ifdebug_info is NULL !\n");
+					return -1;
+				}
+				ssv6xxx_result_buf[0] = 0x00;
+				ret = sc_tbl->cmd_func_ptr(sg_argc, sg_argv);
+				if (ret < 0) {
+					strcpy(ssv6xxx_result_buf,
+					       "Invalid command !\n");
+				}
+				return 0;
+			}
+		}
+		strcpy(ssv6xxx_result_buf, "Command not found !\n");
+	} else {
+		strcpy(ssv6xxx_result_buf, "./cli -h\n");
+	}
+	return 0;
+}
diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
new file mode 100644
index 00000000000..d96bfcc5495
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/ssvdevice/ssv_cmd.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SSV_CMD_H_
+#define _SSV_CMD_H_
+#define CLI_BUFFER_SIZE 256
+#define CLI_ARG_SIZE 10
+#define CLI_RESULT_BUF_SIZE (4096)
+#define DEBUG_DIR_ENTRY "ssv"
+#define DEBUG_DEVICETYPE_ENTRY "ssv_devicetype"
+#define DEBUG_CMD_ENTRY "ssv_cmd"
+#define MAX_CHARS_PER_LINE 256
+struct ssv_cmd_table {
+	const char *cmd;
+	int (*cmd_func_ptr)(int, char **);
+	const char *usage;
+};
+struct ssv6xxx_cfg_cmd_table {
+	u8 *cfg_cmd;
+	void *var;
+	u32 arg;
+	int (*translate_func)(u8 *, void *, u32);
+};
+#define SSV_REG_READ1(ops,reg,val) \
+        (ops)->ifops->readreg((ops)->dev, reg, val)
+#define SSV_REG_WRITE1(ops,reg,val) \
+        (ops)->ifops->writereg((ops)->dev, reg, val)
+#define SSV_REG_SET_BITS1(ops,reg,set,clr) \
+    { \
+        u32 reg_val; \
+        SSV_REG_READ(ops, reg, &reg_val); \
+        reg_val &= ~(clr); \
+        reg_val |= (set); \
+        SSV_REG_WRITE(ops, reg, reg_val); \
+    }
+int ssv_cmd_submit(char *cmd);
+#endif
diff --git a/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c b/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
new file mode 100644
index 00000000000..eb848553798
--- /dev/null
+++ b/drivers/net/wireless/ssv6051/ssvdevice/ssvdevice.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
+ * Copyright (c) 2015 iComm Corporation
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 3 of the License, or 
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
+ * See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License 
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/slab.h>
+#include <asm/uaccess.h>
+#include <linux/errno.h>
+#include "ssv_cmd.h"
+#include "ssv_cfg.h"
+#include <linux/fs.h>
+#include <asm/uaccess.h>
+#include <linux/buffer_head.h>
+#include <linux/ctype.h>
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+#endif
+
+char *ssv_initmac = NULL;
+EXPORT_SYMBOL(ssv_initmac);
+module_param(ssv_initmac, charp, 0644);
+MODULE_PARM_DESC(ssv_initmac, "Wi-Fi MAC address");
+
+u32 ssv_devicetype = 0;
+EXPORT_SYMBOL(ssv_devicetype);
+
+#ifdef CONFIG_DEBUG_FS
+static struct dentry *debugfs;
+#endif
+
+struct proc_dir_entry *procfs;
+static char *ssv6xxx_cmd_buf;
+char *ssv6xxx_result_buf;
+extern struct ssv6xxx_cfg_cmd_table cfg_cmds[];
+extern struct ssv6xxx_cfg ssv_cfg;
+char DEFAULT_CFG_PATH[] = "/lib/firmware/ssv6051-wifi.cfg";
+static int ssv6xxx_dbg_open(struct inode *inode, struct file *filp)
+{
+	filp->private_data = inode->i_private;
+	return 0;
+}
+
+static ssize_t ssv6xxx_dbg_read(struct file *filp, char __user * buffer,
+				size_t count, loff_t * ppos)
+{
+	int len;
+	if (*ppos != 0)
+		return 0;
+	len = strlen(ssv6xxx_result_buf) + 1;
+	if (len == 1)
+		return 0;
+	if (copy_to_user(buffer, ssv6xxx_result_buf, len))
+		return -EFAULT;
+	ssv6xxx_result_buf[0] = 0x00;
+	return len;
+}
+
+static ssize_t ssv6xxx_dbg_write(struct file *filp, const char __user * buffer,
+				 size_t count, loff_t * ppos)
+{
+	if (*ppos != 0 || count > 255)
+		return 0;
+	if (copy_from_user(ssv6xxx_cmd_buf, buffer, count))
+		return -EFAULT;
+	ssv6xxx_cmd_buf[count - 1] = 0x00;
+	ssv_cmd_submit(ssv6xxx_cmd_buf);
+	return count;
+}
+
+size_t read_line(struct file * fp, char *buf, size_t size)
+{
+	size_t num_read = 0;
+	size_t total_read = 0;
+	char *buffer;
+	char ch;
+	size_t start_ignore = 0;
+	if (size <= 0 || buf == NULL) {
+		total_read = -EINVAL;
+		return -EINVAL;
+	}
+	buffer = buf;
+	for (;;) {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
+		num_read = kernel_read(fp, &ch, 1, &fp->f_pos);
+#else
+		mm_segment_t fs;
+		fs = get_fs();
+		set_fs(KERNEL_DS);
+		num_read = vfs_read(fp, &ch, 1, &fp->f_pos);
+		set_fs(fs);
+#endif
+		if (num_read < 0) {
+			if (num_read == EINTR)
+				continue;
+			else
+				return -1;
+		} else if (num_read == 0) {
+			if (total_read == 0)
+				return 0;
+			else
+				break;
+		} else {
+			if (ch == '#')
+				start_ignore = 1;
+			if (total_read < size - 1) {
+				total_read++;
+				if (start_ignore)
+					*buffer++ = '\0';
+				else
+					*buffer++ = ch;
+			}
+			if (ch == '\n')
+				break;
+		}
+	}
+	*buffer = '\0';
+	return total_read;
+}
+
+int ischar(char *c)
+{
+	int is_char = 1;
+	while (*c) {
+		if (isalpha(*c) || isdigit(*c) || *c == '_' || *c == ':'
+		    || *c == '/' || *c == '.' || *c == '-')
+			c++;
+		else {
+			is_char = 0;
+			break;
+		}
+	}
+	return is_char;
+}
+
+void sta_cfg_set(void)
+{
+	struct file *fp = (struct file *)NULL;
+	char buf[MAX_CHARS_PER_LINE], cfg_cmd[32], cfg_value[32];
+	size_t s, read_len = 0, is_cmd_support = 0;
+
+	memset(&ssv_cfg, 0, sizeof(ssv_cfg));
+	memset(buf, 0, sizeof(buf));
+	fp = filp_open(DEFAULT_CFG_PATH, O_RDONLY, 0);
+	if (IS_ERR(fp) || fp == NULL) {
+		WARN_ON(1);
+		return;
+	}
+	if (fp->f_path.dentry == NULL) {
+		WARN_ON(1);
+		return;
+	}
+	do {
+		memset(cfg_cmd, '\0', sizeof(cfg_cmd));
+		memset(cfg_value, '\0', sizeof(cfg_value));
+		read_len = read_line(fp, buf, MAX_CHARS_PER_LINE);
+		sscanf(buf, "%s = %s", cfg_cmd, cfg_value);
+		if (!ischar(cfg_cmd) || !ischar(cfg_value)) {
+			pr_warn("Invalid configuration parameter: %s\n", buf);
+			continue;
+		}
+		is_cmd_support = 0;
+		for (s = 0; cfg_cmds[s].cfg_cmd != NULL; s++) {
+			if (strcmp(cfg_cmds[s].cfg_cmd, cfg_cmd) == 0) {
+				cfg_cmds[s].translate_func(cfg_value,
+							   cfg_cmds[s].var,
+							   cfg_cmds[s].arg);
+				is_cmd_support = 1;
+				break;
+			}
+		}
+		if (!is_cmd_support && strlen(cfg_cmd) > 0) {
+			pr_warn("Unsupported configuration command: %s", cfg_cmd);
+		}
+	} while (read_len > 0);
+	filp_close(fp, NULL);
+}
+
+static const struct file_operations ssv6xxx_dbg_fops = {
+	.owner = THIS_MODULE,
+	.open = ssv6xxx_dbg_open,
+	.read = ssv6xxx_dbg_read,
+	.write = ssv6xxx_dbg_write,
+};
+
+extern int ssv6xxx_hci_init(void);
+extern void ssv6xxx_hci_exit(void);
+extern int ssv6xxx_init(void);
+extern void ssv6xxx_exit(void);
+extern int ssv6xxx_sdio_init(void);
+extern void ssv6xxx_sdio_exit(void);
+
+int ssvdevice_init(void)
+{
+	ssv6xxx_cmd_buf =
+	    (char *)kzalloc(CLI_BUFFER_SIZE + CLI_RESULT_BUF_SIZE, GFP_KERNEL);
+	if (!ssv6xxx_cmd_buf)
+		return -ENOMEM;
+	ssv6xxx_result_buf = ssv6xxx_cmd_buf + CLI_BUFFER_SIZE;
+	ssv6xxx_cmd_buf[0] = 0x00;
+	ssv6xxx_result_buf[0] = 0x00;
+#ifdef CONFIG_DEBUG_FS
+	debugfs = debugfs_create_dir(DEBUG_DIR_ENTRY, NULL);
+	if (!debugfs)
+		return -ENOMEM;
+	debugfs_create_u32(DEBUG_DEVICETYPE_ENTRY, S_IRUGO | S_IWUSR, debugfs,
+			   &ssv_devicetype);
+	debugfs_create_file(DEBUG_CMD_ENTRY, S_IRUGO | S_IWUSR, debugfs, NULL,
+			    &ssv6xxx_dbg_fops);
+#endif
+	sta_cfg_set();
+	{
+		int ret;
+		ret = ssv6xxx_hci_init();
+		if (!ret) {
+			ret = ssv6xxx_init();
+		}
+		if (!ret) {
+			ret = ssv6xxx_sdio_init();
+		}
+		return ret;
+	}
+
+	return 0;
+}
+
+void ssvdevice_exit(void)
+{
+
+	ssv6xxx_exit();
+	ssv6xxx_hci_exit();
+	ssv6xxx_sdio_exit();
+
+#ifdef CONFIG_DEBUG_FS
+	debugfs_remove_recursive(debugfs);
+#endif
+	kfree(ssv6xxx_cmd_buf);
+}
+
+EXPORT_SYMBOL(ssvdevice_init);
+EXPORT_SYMBOL(ssvdevice_exit);
-- 
2.34.1



================================================
FILE: kernel-patch/beta/deprecated-patches/6.1.y-101-arm64-add-text_offset.patch
================================================
From 5bebdd36f56da96f08bad5ab34e39bffd3ef872b Mon Sep 17 00:00:00 2001
From: xxxxx <67037522+xxxxx@users.noreply.github.com>
Date: Thu, 7 Mar 2024 11:38:19 +0800
Subject: [PATCH] arm64: Apply the text_offset patch

---
 arch/arm64/Makefile                       |  5 +++++
 arch/arm64/include/asm/boot.h             |  3 ++-
 arch/arm64/include/asm/kernel-pgtable.h   |  2 +-
 arch/arm64/include/asm/memory.h           |  2 +-
 arch/arm64/kernel/Makefile                |  3 ++-
 arch/arm64/kernel/head.S                  | 22 +++++++++++++++++-----
 arch/arm64/kernel/image.h                 |  1 +
 arch/arm64/kernel/setup.c                 |  3 ---
 arch/arm64/kernel/vmlinux.lds.S           |  4 ++--
 arch/arm64/mm/mmu.c                       |  3 ---
 drivers/firmware/efi/libstub/Makefile     |  1 +
 drivers/firmware/efi/libstub/arm64-stub.c |  6 +++---
 12 files changed, 35 insertions(+), 20 deletions(-)

diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index c9496539c..c86cd9445 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -11,6 +11,7 @@
 # Copyright (C) 1995-2001 by Russell King
 
 LDFLAGS_vmlinux	:=--no-undefined -X
+CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET)
 
 ifeq ($(CONFIG_RELOCATABLE), y)
 # Pass --no-apply-dynamic-relocs to restore pre-binutils-2.27 behaviour
@@ -133,6 +134,10 @@ ifeq ($(CONFIG_DYNAMIC_FTRACE_WITH_REGS),y)
   CC_FLAGS_FTRACE := -fpatchable-function-entry=2
 endif
 
+# The byte offset of the kernel image in RAM from the start of RAM.
+TEXT_OFFSET := 0x01080000
+export TEXT_OFFSET
+
 ifeq ($(CONFIG_KASAN_SW_TAGS), y)
 KASAN_SHADOW_SCALE_SHIFT := 4
 else ifeq ($(CONFIG_KASAN_GENERIC), y)
diff --git a/arch/arm64/include/asm/boot.h b/arch/arm64/include/asm/boot.h
index 3e7943fd1..c7f67da13 100644
--- a/arch/arm64/include/asm/boot.h
+++ b/arch/arm64/include/asm/boot.h
@@ -13,7 +13,8 @@
 #define MAX_FDT_SIZE		SZ_2M
 
 /*
- * arm64 requires the kernel image to placed at a 2 MB aligned base address
+ * arm64 requires the kernel image to placed
+ * TEXT_OFFSET bytes beyond a 2 MB aligned base
  */
 #define MIN_KIMG_ALIGN		SZ_2M
 
diff --git a/arch/arm64/include/asm/kernel-pgtable.h b/arch/arm64/include/asm/kernel-pgtable.h
index 32d14f481..da22c57b4 100644
--- a/arch/arm64/include/asm/kernel-pgtable.h
+++ b/arch/arm64/include/asm/kernel-pgtable.h
@@ -85,7 +85,7 @@
 			+ EARLY_PGDS((vstart), (vend), add) 	/* each PGDIR needs a next level page table */	\
 			+ EARLY_PUDS((vstart), (vend), add)	/* each PUD needs a next level page table */	\
 			+ EARLY_PMDS((vstart), (vend), add))	/* each PMD needs a next level page table */
-#define INIT_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR, _end, EARLY_KASLR))
+#define INIT_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR + TEXT_OFFSET, _end, EARLY_KASLR))
 
 /* the initial ID map may need two extra pages if it needs to be extended */
 #if VA_BITS < 48
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index 9dd08cd33..4dae5cbfc 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -192,7 +192,7 @@ extern s64			memstart_addr;
 /* PHYS_OFFSET - the physical address of the start of memory. */
 #define PHYS_OFFSET		({ VM_BUG_ON(memstart_addr & 1); memstart_addr; })
 
-/* the virtual base of the kernel image */
+/* the virtual base of the kernel image (minus TEXT_OFFSET) */
 extern u64			kimage_vaddr;
 
 /* the offset between the kernel virtual and physical mappings */
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 2f361a883..fd925c914 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -2,7 +2,8 @@
 #
 # Makefile for the linux kernel.
 #
-
+CPPFLAGS_vmlinux.lds	:= -DTEXT_OFFSET=$(TEXT_OFFSET)
+AFLAGS_head.o		:= -DTEXT_OFFSET=$(TEXT_OFFSET)
 CFLAGS_armv8_deprecated.o := -I$(src)
 
 CFLAGS_REMOVE_ftrace.o = $(CC_FLAGS_FTRACE)
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index cdbbc95eb..344282cde 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -37,6 +37,8 @@
 
 #include "efi-header.S"
 
+#define __PHYS_OFFSET  (KERNEL_START - TEXT_OFFSET)
+
 #if (PAGE_OFFSET & 0x1fffff) != 0
 #error PAGE_OFFSET must be at least 2MB aligned
 #endif
@@ -49,6 +51,9 @@
  *   MMU = off, D-cache = off, I-cache = on or off,
  *   x0 = physical address to the FDT blob.
  *
+ * This code is mostly position independent so you call this at
+ * __pa(PAGE_OFFSET + TEXT_OFFSET).
+ *
  * Note that the callee-saved registers are used for storing variables
  * that are useful before the MMU is enabled. The allocations are described
  * in the entry routines.
@@ -59,7 +64,7 @@
 	 */
 	efi_signature_nop			// special NOP to identity as PE/COFF executable
 	b	primary_entry			// branch to kernel start, magic
-	.quad	0				// Image load offset from start of RAM, little-endian
+	le64sym	_kernel_offset_le		// Image load offset from start of RAM, little-endian
 	le64sym	_kernel_size_le			// Effective size of kernel image, little-endian
 	le64sym	_kernel_flags_le		// Informative flags, little-endian
 	.quad	0				// reserved
@@ -370,7 +375,7 @@ SYM_FUNC_END(create_idmap)
 
 SYM_FUNC_START_LOCAL(create_kernel_mapping)
 	adrp	x0, init_pg_dir
-	mov_q	x5, KIMAGE_VADDR		// compile time __va(_text)
+	mov_q	x5, KIMAGE_VADDR + TEXT_OFFSET		// compile time __va(_text)
 #ifdef CONFIG_RELOCATABLE
 	add	x5, x5, x23			// add KASLR displacement
 #endif
@@ -415,7 +420,7 @@ SYM_FUNC_END(create_kernel_mapping)
 /*
  * The following fragment of code is executed with the MMU enabled.
  *
- *   x0 = __pa(KERNEL_START)
+ *   x0 = __PHYS_OFFSET
  */
 SYM_FUNC_START_LOCAL(__primary_switched)
 	adr_l	x4, init_task
@@ -469,6 +474,13 @@ SYM_FUNC_START_LOCAL(__primary_switched)
 	ASM_BUG()
 SYM_FUNC_END(__primary_switched)
 
+        .pushsection ".rodata", "a"
+ SYM_DATA_START(kimage_vaddr)
+        .quad           _text - TEXT_OFFSET
+ SYM_DATA_END(kimage_vaddr)
+ EXPORT_SYMBOL(kimage_vaddr)
+        .popsection
+
 /*
  * end early head section, begin head code that is also used for
  * hotplug and needs to have the same protections as the text region
@@ -798,7 +810,7 @@ SYM_FUNC_START_LOCAL(__primary_switch)
 	adrp	x2, init_idmap_pg_dir
 	bl	__enable_mmu
 #ifdef CONFIG_RELOCATABLE
-	adrp	x23, KERNEL_START
+	adrp	x23, __PHYS_OFFSET
 	and	x23, x23, MIN_KIMG_ALIGN - 1
 #ifdef CONFIG_RANDOMIZE_BASE
 	mov	x0, x22
@@ -820,6 +832,6 @@ SYM_FUNC_START_LOCAL(__primary_switch)
 	bl	__relocate_kernel
 #endif
 	ldr	x8, =__primary_switched
-	adrp	x0, KERNEL_START		// __pa(KERNEL_START)
+	adrp	x0, __PHYS_OFFSET
 	br	x8
 SYM_FUNC_END(__primary_switch)
diff --git a/arch/arm64/kernel/image.h b/arch/arm64/kernel/image.h
index 7bc3ba897..c7d38c660 100644
--- a/arch/arm64/kernel/image.h
+++ b/arch/arm64/kernel/image.h
@@ -62,6 +62,7 @@
  */
 #define HEAD_SYMBOLS						\
 	DEFINE_IMAGE_LE64(_kernel_size_le, _end - _text);	\
+	DEFINE_IMAGE_LE64(_kernel_offset_le, TEXT_OFFSET);	\
 	DEFINE_IMAGE_LE64(_kernel_flags_le, __HEAD_FLAGS);
 
 #endif /* __ARM64_KERNEL_IMAGE_H */
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index fea322370..25032cbf8 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -328,9 +328,6 @@ void __init __no_sanitize_address setup_arch(char **cmdline_p)
 	xen_early_init();
 	efi_init();
 
-	if (!efi_enabled(EFI_BOOT) && ((u64)_text % MIN_KIMG_ALIGN) != 0)
-	     pr_warn(FW_BUG "Kernel image misaligned at boot, please fix your bootloader!");
-
 	arm64_memblock_init();
 
 	paging_init();
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 45131e354..329433fda 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -151,7 +151,7 @@ SECTIONS
 		*(.dynsym .dynstr .hash .gnu.hash)
 	}
 
-	. = KIMAGE_VADDR;
+	. = KIMAGE_VADDR + TEXT_OFFSET;
 
 	.head.text : {
 		_text = .;
@@ -353,7 +353,7 @@ ASSERT(__hyp_bss_start == __bss_start, "HYP and Host BSS are misaligned")
 /*
  * If padding is applied before .head.text, virt<->phys conversions will fail.
  */
-ASSERT(_text == KIMAGE_VADDR, "HEAD is misaligned")
+ASSERT(_text == (KIMAGE_VADDR + TEXT_OFFSET), "HEAD is misaligned")
 
 ASSERT(swapper_pg_dir - reserved_pg_dir == RESERVED_SWAPPER_OFFSET,
        "RESERVED_SWAPPER_OFFSET is wrong!")
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 4b302dbf7..8632e111f 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -52,9 +52,6 @@ u64 vabits_actual __ro_after_init = VA_BITS_MIN;
 EXPORT_SYMBOL(vabits_actual);
 #endif
 
-u64 kimage_vaddr __ro_after_init = (u64)&_text;
-EXPORT_SYMBOL(kimage_vaddr);
-
 u64 kimage_voffset __ro_after_init;
 EXPORT_SYMBOL(kimage_voffset);
 
diff --git a/drivers/firmware/efi/libstub/Makefile b/drivers/firmware/efi/libstub/Makefile
index 473ef1842..8693b17f6 100644
--- a/drivers/firmware/efi/libstub/Makefile
+++ b/drivers/firmware/efi/libstub/Makefile
@@ -89,6 +89,7 @@ lib-$(CONFIG_RISCV)		+= riscv-stub.o
 lib-$(CONFIG_LOONGARCH)		+= loongarch-stub.o
 
 CFLAGS_arm32-stub.o		:= -DTEXT_OFFSET=$(TEXT_OFFSET)
+CFLAGS_arm64-stub.o		:= -DTEXT_OFFSET=$(TEXT_OFFSET)
 
 zboot-obj-$(CONFIG_RISCV)	:= lib-clz_ctz.o lib-ashldi3.o
 lib-$(CONFIG_EFI_ZBOOT)		+= zboot.o $(zboot-obj-y)
diff --git a/drivers/firmware/efi/libstub/arm64-stub.c b/drivers/firmware/efi/libstub/arm64-stub.c
index 16f15e36f..bc68c9fdc 100644
--- a/drivers/firmware/efi/libstub/arm64-stub.c
+++ b/drivers/firmware/efi/libstub/arm64-stub.c
@@ -172,7 +172,7 @@ efi_status_t handle_kernel_image(unsigned long *image_addr,
 
 	kernel_size = _edata - _text;
 	kernel_memsize = kernel_size + (_end - _edata);
-	*reserve_size = kernel_memsize;
+	*reserve_size = kernel_memsize + TEXT_OFFSET % min_kimg_align;
 
 	if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && phys_seed != 0) {
 		/*
@@ -191,7 +191,7 @@ efi_status_t handle_kernel_image(unsigned long *image_addr,
 	if (status != EFI_SUCCESS) {
 		if (!check_image_region((u64)_text, kernel_memsize)) {
 			efi_err("FIRMWARE BUG: Image BSS overlaps adjacent EFI memory region\n");
-		} else if (IS_ALIGNED((u64)_text, min_kimg_align) &&
+		} else if (IS_ALIGNED((u64)_text - TEXT_OFFSET, min_kimg_align) &&
 			   (u64)_end < EFI_ALLOC_LIMIT) {
 			/*
 			 * Just execute from wherever we were loaded by the
@@ -213,7 +213,7 @@ efi_status_t handle_kernel_image(unsigned long *image_addr,
 		}
 	}
 
-	*image_addr = *reserve_addr;
+	*image_addr = *reserve_addr + TEXT_OFFSET % min_kimg_align;;
 	memcpy((void *)*image_addr, _text, kernel_size);
 
 	return EFI_SUCCESS;


================================================
FILE: kernel-patch/beta/deprecated-patches/6.12.y-301-dts-add-rockchip-rk3568-alark35-3500-dtb.patch
================================================
From 457ac631dd43a4bf5b807384deacbd85585a414c Mon Sep 17 00:00:00 2001
From: xxx <68696949+xxx@users.noreply.github.com>
Date: Wed, 21 May 2025 14:04:33 +0800
Subject: [PATCH] arch: arm64: rockchip: add rk3568-alark35-3500.dtb

---
 arch/arm64/boot/dts/rockchip/Makefile         |    1 +
 .../boot/dts/rockchip/rk3568-alark35-3500.dts | 1162 +++++++++++++++++
 2 files changed, 1163 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-alark35-3500.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 5e077b5f1..331b939bc 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -143,6 +143,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-cb2-manta.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-jp-tvbox.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-panther-x2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-alark35-3500.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-dg-tn3568.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ec-x.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-alark35-3500.dts b/arch/arm64/boot/dts/rockchip/rk3568-alark35-3500.dts
new file mode 100644
index 000000000..24347d1d7
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-alark35-3500.dts
@@ -0,0 +1,1162 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ *
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	compatible = "rockchip,RK3568 Alark35-3500 hdmi Board", "rockchip,rk3568";
+	model = "Rockchip RK3568 Alark35-3500 hdmi Board";
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+	//earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0
+	/delete-node/ chosen;
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+	vcc5v0_usb: vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_host: ostvcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_usb>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+	};
+
+	vcc5v0_otg: vcc5v0-otg-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_usb>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg_en>;
+	};
+	vcc2v5_sys: vcc2v5-ddr {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc2v5-sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	qsgmii_3v3: gpio-regulator {
+		compatible = "regulator-gpio";
+		regulator-name = "qsgmii_3v3";
+		regulator-min-microvolt = <32768>;
+		regulator-max-microvolt = <3300000>;
+		gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+		gpios-states = <0x1>;
+		states = <32768 0x0 3300000 0x1>;
+	};
+
+	vcc3v3_bu: vcc3v3-bu {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_bu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+	vcc3v3_lcd0_n: vcc3v3-lcd0-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd0_n";
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc3v3_sys>;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+	
+	//todo
+	/*
+	sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <0x134 0x1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x135>;
+		post-power-on-delay-ms = <0xc8>;
+		reset-gpios = <0x136 0x9 0x1>;
+		status = "okay";
+		phandle = <0xbe>;
+	};
+
+	wireless-wlan {
+		compatible = "wlan-platdata";
+		rockchip,grf = <0x33>;
+		wifi_chip_type = "ap6212";
+		sdio_vref = <0x708>;
+		WIFI,poweren_gpio = <0xe0 0x14 0x0>;
+		WIFI,host_wake_irq = <0x136 0xa 0x0>;
+		status = "okay";
+		phandle = <0x1e5>;
+	};
+
+	wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		clocks = <0x134 0x1>;
+		clock-names = "ext_clock";
+		uart_rts_gpios = <0x136 0xd 0x1>;
+		pinctrl-names = "default", "rts_gpio";
+		pinctrl-0 = <0x137>;
+		pinctrl-1 = <0x138>;
+		BT,reset_gpio = <0x136 0xf 0x0>;
+		BT,wake_gpio = <0x136 0x11 0x0>;
+		BT,wake_host_irq = <0x136 0x10 0x0>;
+		status = "okay";
+		phandle = <0x1e6>;
+	};*/
+	/*
+	phone_option {
+		compatible = "phone_option";
+		4g_reset_gpio = <0x82 0x1a 0x0>;
+		4g_pwr_gpio = <0x37 0x16 0x0>;
+		status = "okay";
+	};
+
+	ala-gpio {
+		compatible = "ala-gpio";
+		dev_name = "ala-gpio";
+		status = "okay";
+		ala_gpio_1 = <0x40 0x19 0x0>;
+		ala_gpio_2 = <0x40 0x1a 0x0>;
+		ala_gpio_3 = <0x40 0x1b 0x0>;
+		ala_gpio_4 = <0x40 0x1c 0x0>;
+		ala_gpio_5 = <0x37 0xf 0x0>;
+		ala_gpio_6 = <0x82 0x19 0x0>;
+		ala_gpio_7 = <0x82 0x1b 0x0>;
+		ala_gpio_8 = <0xe0 0x1a 0x0>;
+		ala_gpio_9 = <0xc8>;
+		ala_gpio_10 = <0xc9>;
+		ala_gpio_11 = <0xca>;
+		ala_gpio_12 = <0xcb>;
+		ala_gpio_13 = <0xcc>;
+		ala_gpio_14 = <0xcd>;
+		ala_gpio_15 = <0xd0>;
+		ala_gpio_16 = <0xd1>;
+	};*/
+	gpio-keys {
+		status = "disabled";
+		compatible = "gpio-keys";
+		autorepeat;
+
+		vol-up-key {
+			gpios = <&gpio0 0x1e 0x1>;
+			linux,code = <0x73>;
+			label = "volume up";
+		};
+
+		back-key {
+			gpios = <&gpio0 0x1c 0x1>;
+			linux,code = <0x9e>;
+			label = "back";
+		};
+	};
+	
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <50000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0x0>;
+	};
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+	/*
+	test-power {
+		status = "okay";
+	};*/
+
+};
+&xpcs {
+	status = "okay";
+};
+//50M时钟
+/*
+&gmac1_clkin {
+	clock-frequency = <50000000>;
+};*/
+&gmac1 {
+	status = "okay";
+	phy-supply = <&qsgmii_3v3>;
+	phy-mode = "rmii";
+	clock_in_out = "input";
+	snps,reset-gpio = <&gpio3 RK_PD7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 20000 100000>;
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX &cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RMII_SPEED &gmac1_clkin>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim &gmac1m1_clkinout &gmac1m1_rx_bus2 &gmac1m1_tx_bus2>;
+	phy-handle = <&rmii_phy0>;
+};
+&mdio1 {
+	rmii_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+	};
+};
+/*
+&combphy0_us {
+	status = "okay";
+};
+
+&combphy1_usq {
+	status = "okay";
+};
+
+&combphy2_psq {
+	status = "okay";
+};
+*/
+
+&combphy0 {
+	/* used for USB3 */
+	status = "okay";
+};
+
+&combphy1 {
+	/* used for USB3 */
+	status = "okay";
+};
+
+&combphy2 {
+	/* used for SATA */
+	status = "okay";
+};
+/*
+&bus_npu {
+	bus-supply = <&vdd_logic>;
+	pvtm-supply = <&vdd_cpu>;
+	status = "okay";
+};*/
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu0_opp_table {
+	
+};
+
+&cpu1 {
+};
+
+&cpu2 {
+};
+
+&cpu3 {
+};
+/*
+&dfi {
+	status = "okay";
+};*/
+
+/*
+&dmc {
+	center-supply = <&vdd_logic>;
+	status = "okay";
+};*/
+
+
+&gpu {
+	clock-names = "gpu", "bus";
+	interrupt-names = "gpu", "mmu", "job";
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+/*
+&hdmi {
+	status = "okay";
+	rockchip,phy-table =
+		<92812500  0x8009 0x0000 0x0270>,
+		<165000000 0x800b 0x0000 0x026d>,
+		<185625000 0x800b 0x0000 0x01ed>,
+		<297000000 0x800b 0x0000 0x01ad>,
+		<594000000 0x8029 0x0000 0x0088>,
+		<000000000 0x0000 0x0000 0x0000>;
+};
+
+&hdmi_in {
+	status = "okay";
+};
+
+&hdmi_out {
+	status = "disabled";
+};*/
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: tcs4525@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-compatible = "fan53555-reg";
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1390000>;
+		regulator-init-microvolt = <900000>;
+		regulator-ramp-delay = <2300>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-names = "default", "pmic-sleep",
+				"pmic-power-off", "pmic-reset";
+		pinctrl-0 = <&pmic_int>;
+		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
+		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
+		pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
+
+		rockchip,system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		//fb-inner-reg-idxs = <2>;
+		/* 1: rst regs (default in codes), 0: rst the pmic */
+		pmic-reset-func = <0>;
+		/* not save the PMIC_POWER_EN register in uboot */
+		not-save-power-en = <1>;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		pwrkey {
+			status = "okay";
+		};
+
+		pinctrl_rk8xx: pinctrl_rk8xx {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			rk817_slppin_null: rk817_slppin_null {
+				pins = "gpio_slp";
+				function = "pin_fun0";
+			};
+
+			rk817_slppin_slp: rk817_slppin_slp {
+				pins = "gpio_slp";
+				function = "pin_fun1";
+			};
+
+			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
+				pins = "gpio_slp";
+				function = "pin_fun2";
+			};
+
+			rk817_slppin_rst: rk817_slppin_rst {
+				pins = "gpio_slp";
+				function = "pin_fun3";
+			};
+		};
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_logic";
+				regulator-state-mem {
+					//regulator-off-in-suspend;
+					// 强制开启电源
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_gpu";
+				regulator-state-mem {
+					//regulator-off-in-suspend;
+					// 强制开启电源
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+				regulator-state-mem {
+					//regulator-on-in-suspend;
+					// 强制开启电源
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_npu";
+				regulator-state-mem {
+					//regulator-off-in-suspend;
+					// 强制开启电源
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+				regulator-state-mem {
+					//regulator-off-in-suspend;
+					// 强制开启电源
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+				regulator-state-mem {
+					//regulator-off-in-suspend;
+					// 强制开启电源
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					//regulator-suspend-microvolt = <900000>;
+					// 强制开启电源
+					//regulator-on-in-suspend;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_acodec";
+				regulator-state-mem {
+					//regulator-off-in-suspend;
+					// 强制开启电源
+					regulator-on-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+				regulator-state-mem {
+					//regulator-off-in-suspend;
+					// 强制开启电源
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+				regulator-state-mem {
+					//regulator-off-in-suspend;
+					// 强制开启电源
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image";
+				regulator-state-mem {
+					//regulator-off-in-suspend;
+					// 强制开启电源
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+				regulator-state-mem {
+					//regulator-off-in-suspend;
+					// 强制开启电源
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_3v3";
+				regulator-state-mem {
+					//regulator-off-in-suspend;
+					// 强制开启电源
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_sd";
+				regulator-state-mem {
+					//regulator-off-in-suspend;
+					// 强制开启电源
+					regulator-on-in-suspend;
+				};
+			};
+		};
+		/*
+		rk809_codec: codec {
+			#sound-dai-cells = <1>;
+			compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
+			clocks = <&cru I2S1_MCLKOUT>;
+			clock-names = "mclk";
+			assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>;
+			assigned-clock-rates = <12288000>;
+			assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2s1m0_mclk>;
+			hp-volume = <20>;
+			spk-volume = <3>;
+			mic-in-differential;
+			status = "disabled";
+		};*/
+	};
+};
+
+// debug tty,ttys2
+&uart2 {
+	/* debug-uart */
+	status = "okay";
+};
+&uart0 {
+	status = "okay";
+};
+&pwm3 {
+	compatible = "rockchip,remotectl-pwm";
+
+	status = "okay";
+	remote_pwm_id = <0x3>;
+	handle_cpu_id = <0x1>;
+	remote_support_psci = <0x0>;
+	ir_key1 {
+		rockchip,usercode = <0x4040>;
+		rockchip,key_table = <0xf2 0xe8 0xba 0x9e 0xf4 0x67 0xf1 0x6c 0xef 0x69 0xee 0x6a 0xbd 0x66 0xea 0x73 0xe3 0x72 0xe2 0xd9 0xb2 0x74 0xbc 0x71 0xec 0x8b 0xbf 0x190 0xe0 0x191 0xe1 0x192 0xe9 0xb7 0xe6 0xf8 0xe8 0xb9 0xe7 0xba 0xf0 0x184 0xbe 0x175>;
+	};
+
+	ir_key2 {
+		rockchip,usercode = <0xff00>;
+		rockchip,key_table = <0xf9 0x66 0xbf 0x9e 0xfb 0x8b 0xaa 0xe8 0xb9 0x67 0xe9 0x6c 0xb8 0x69 0xea 0x6a 0xeb 0x72 0xef 0x73 0xf7 0x71 0xe7 0x74 0xfc 0x74 0xa9 0x72 0xa8 0x72 0xe0 0x72 0xa5 0x72 0xab 0xb7 0xb7 0x184 0xe8 0x184 0xf8 0xb8 0xaf 0xb9 0xed 0x72 0xee 0xba 0xb3 0x72 0xf1 0x72 0xf2 0x72 0xf3 0xd9 0xb4 0x72 0xbe 0xd9>;
+	};
+	ir_key3 {
+		rockchip,usercode = <0x1dcc>;
+		rockchip,key_table = <0xee 0xe8 0xf0 0x9e 0xf8 0x67 0xbb 0x6c 0xef 0x69 0xed 0x6a 0xfc 0x66 0xf1 0x73 0xfd 0x72 0xb7 0xd9 0xff 0x74 0xf3 0x71 0xbf 0x8b 0xf9 0x191 0xf5 0x192 0xb3 0x184 0xbe 0x2 0xba 0x3 0xb2 0x4 0xbd 0x5 0xf9 0x6 0xb1 0x7 0xfc 0x8 0xf8 0x9 0xb0 0xa 0xb6 0xb 0xb5 0xe>;
+	};
+};
+
+//power,ok
+&power {
+	status = "okay";
+	// 必须删除,不删除会 paninc,
+	///delete-node/ power-domain@RK3568_PD_NPU;
+};
+/*
+&rockchip_suspend {
+	status = "okay";
+};*/
+/*
+&iep {
+	status = "okay";
+};
+
+&iep_mmu {
+	status = "okay";
+};
+
+&jpegd {
+	status = "okay";
+};
+
+&jpegd_mmu {
+	status = "okay";
+};
+
+&mpp_srv {
+	status = "okay";
+};*/
+
+&pinctrl {
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		soc_slppin_gpio: soc_slppin_gpio {
+			rockchip,pins =
+				<0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+
+		soc_slppin_slp: soc_slppin_slp {
+			rockchip,pins =
+				<0 RK_PA2 1 &pcfg_pull_none>;
+		};
+
+		soc_slppin_rst: soc_slppin_rst {
+			rockchip,pins =
+				<0 RK_PA2 2 &pcfg_pull_none>;
+		};
+	};
+
+
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_otg_en: vcc5v0-otg-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wireless-bluetooth {
+		uart8_gpios: uart8-gpios {
+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+ /*
+  * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7].
+  * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured;
+  * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages
+  *    must be consistent with the software configuration correspondingly
+  *	a/ When the hardware IO level is connected to 1.8V, the software voltage configuration
+  *	   should also be configured to 1.8V accordingly;
+  *	b/ When the hardware IO level is connected to 3.3V, the software voltage configuration
+  *	   should also be configured to 3.3V accordingly;
+  * 3/ VCCIO2 voltage control selection (0xFDC20140)
+  *	BIT[0]: 0x0: from GPIO_0A7 (default)
+  *	BIT[0]: 0x1: from GRF
+  *    Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7:
+  *	L:VCCIO2 must supply 3.3V
+  *	H:VCCIO2 must supply 1.8V
+  */
+/*
+pmuio2-supply = <0x2a>;
+vccio1-supply = <0x2b>;
+vccio3-supply = <0x2c>;
+vccio4-supply = <0x2d>;
+vccio5-supply = <0x2e>;
+vccio6-supply = <0x2e>;
+vccio7-supply = <0x2e>;*/
+
+&pmu_io_domains {
+	status = "okay";
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+};
+/*
+&rk_rga {
+	status = "okay";
+};
+
+&rkvdec {
+	status = "okay";
+};
+
+&rkvdec_mmu {
+	status = "okay";
+};
+
+&rkvenc {
+	venc-supply = <&vdd_logic>;
+	status = "okay";
+};
+
+&rkvenc_mmu {
+	status = "okay";
+};*/
+
+//&rknpu {
+//	rknpu-supply = <&vdd_npu>;
+//	status = "okay";
+	///delete-node/ power-domains;
+	///delete-node/ operating-points-v2;
+//};
+
+//&rknpu_mmu {
+//	status = "okay";
+	///delete-node/ power-domains;
+//};
+/*
+&route_hdmi {
+	status = "okay";
+	connect = <&vp0_out_hdmi>;
+};*/
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vcca_1v8>;
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	max-frequency = <200000000>;
+	full-pwr-cycle-in-suspend;
+	status = "okay";
+};
+
+&sdmmc0 {
+	max-frequency = <150000000>;
+	no-sdio;
+	no-mmc;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	status = "okay";
+};
+
+&sfc {
+	status = "okay";
+};
+/*
+&spdif_8ch {
+	status = "okay";
+};*/
+&spdif{
+	status = "okay";
+};
+&tsadc {
+	status = "okay";
+};
+/*
+&u2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy0_otg {
+	vbus-supply = <&vcc5v0_otg>;
+	status = "okay";
+};
+
+&u2phy1_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd_dwc3 {
+	dr_mode = "otg";
+	extcon = <&usb2phy0>;
+	status = "okay";
+};
+
+&usbdrd30 {
+	status = "okay";
+};
+
+&usbhost_dwc3 {
+	status = "okay";
+};
+
+&usbhost30 {
+	status = "okay";
+};
+*/
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	extcon = <&usb2phy0>;
+	dr_mode = "host";
+	snps,dis_enblslpm_quirk;
+	snps,dis-u1u2-quirk;
+	snps,dis-u2-freeclk-exists-quirk;
+	snps,dis-del-phy-power-chg-quirk;
+	snps,dis-tx-ipgap-linecheck-quirk;
+	snps,dis_rxdet_inp3_quirk;
+	snps,xhci-trb-ent-quirk;
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_otg>;
+	status = "okay";
+};
+&usb2phy1 {
+	/* USB for PCIe/M2 */
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+/*
+&u2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy0_otg {
+	vbus-supply = <&vcc5v0_otg>;
+	status = "okay";
+};
+
+&u2phy1_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};*/
+/*
+&vdpu {
+	status = "okay";
+};*/
+
+&vpu {
+	status = "okay";
+};
+
+&vdpu_mmu {
+	status = "okay";
+};
+
+&vepu {
+	status = "okay";
+};
+
+&vepu_mmu {
+	status = "okay";
+};
+/*
+&vop {
+	status = "okay";
+	vop-supply = <&vdd_logic>;
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>, <&cru PLL_GPLL>;
+};*/
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
+
+
+
+&pcie2x1 {
+	status = "okay";
+	//todo
+	reset-gpios = <&gpio1 0xa 0x0>;
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	status = "okay";
+	rockchip,clk-trcm = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m0_sclktx
+		     &i2s1m0_lrcktx
+		     &i2s1m0_sdi0
+		     &i2s1m0_sdo0>;
+};
+
+&i2c1 {
+	status = "okay";
+	pcf8563: pcf8563@51 {
+		compatible = "nxp,pcf8563";
+		status = "okay";
+		reg = <0x51>;
+		#clock-cells = <0x0>;
+		clock-output-names = "pcf8563_xin32k";
+	};
+};
+
+&i2c2 {
+	alastm8s103: alastm8s103@76 {
+		compatible = "stm,alastm8s103";
+		reg = <0x76>;
+		gpio-base = <0xc8>;
+		status = "okay";
+	};
+};
+
+&wdt {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+&uart7 {
+	status = "okay";
+};
+
+&uart9 {
+	status = "okay";
+};
+
+&pwm5 {
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+	simple-audio-card,mclk-fs = <128>;
+};
+
+


================================================
FILE: kernel-patch/beta/deprecated-patches/6.18.y-101-arm64-add-text_offset.patch
================================================
From 065e31e1d4cf87c20ef43a6215d9860076877deb Mon Sep 17 00:00:00 2001
From: uniqfreq <flippy@sina.com>
Date: Fri, 12 Dec 2025 10:05:57 +0800
Subject: [PATCH] Apply TEXT_OFFSET patch for legacy amlogic uboot

---
 arch/arm64/kernel/head.S  | 2 +-
 arch/arm64/kernel/image.h | 2 ++
 arch/arm64/kernel/setup.c | 4 ++--
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index ca04b338c..67d8756be 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -60,7 +60,7 @@
 	 */
 	efi_signature_nop			// special NOP to identity as PE/COFF executable
 	b	primary_entry			// branch to kernel start, magic
-	.quad	0				// Image load offset from start of RAM, little-endian
+	le64sym	_kernel_offset_le		// Image load offset from start of RAM, little-endian
 	le64sym	_kernel_size_le			// Effective size of kernel image, little-endian
 	le64sym	_kernel_flags_le		// Informative flags, little-endian
 	.quad	0				// reserved
diff --git a/arch/arm64/kernel/image.h b/arch/arm64/kernel/image.h
index 7bc3ba897..a5372ae48 100644
--- a/arch/arm64/kernel/image.h
+++ b/arch/arm64/kernel/image.h
@@ -60,8 +60,10 @@
  * regardless of the endianness of the kernel. While constant values could be
  * endian swapped in head.S, all are done here for consistency.
  */
+#define TEXT_OFFSET 0x01080000
 #define HEAD_SYMBOLS						\
 	DEFINE_IMAGE_LE64(_kernel_size_le, _end - _text);	\
+	DEFINE_IMAGE_LE64(_kernel_offset_le, TEXT_OFFSET);	\
 	DEFINE_IMAGE_LE64(_kernel_flags_le, __HEAD_FLAGS);
 
 #endif /* __ARM64_KERNEL_IMAGE_H */
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 23c05dc7a..861079381 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -323,8 +323,8 @@ void __init __no_sanitize_address setup_arch(char **cmdline_p)
 	efi_init();
 
 	if (!efi_enabled(EFI_BOOT)) {
-		if ((u64)_text % MIN_KIMG_ALIGN)
-			pr_warn(FW_BUG "Kernel image misaligned at boot, please fix your bootloader!");
+		// if ((u64)_text % MIN_KIMG_ALIGN)
+		// 	pr_warn(FW_BUG "Kernel image misaligned at boot, please fix your bootloader!");
 		WARN_TAINT(mmu_enabled_at_boot, TAINT_FIRMWARE_WORKAROUND,
 			   FW_BUG "Booted with MMU enabled!");
 	}


================================================
FILE: kernel-patch/beta/deprecated-patches/6.18.y-301-dts-add-g12a-g12b-gxbb-series-devices.patch
================================================
From 1fd1907bee9a05cb86cce1d8cffa9335a2f2d7f5 Mon Sep 17 00:00:00 2001
From: ophub <68696949+ophub@users.noreply.github.com>
Date: Sat, 31 Jan 2026 16:56:47 +0800
Subject: [PATCH] arch: arm64: dts: amlogic: add g12a, g12b, gxbb Series
 devices

---
 arch/arm64/boot/dts/amlogic/Makefile          |  17 +
 .../dts/amlogic/meson-g12a-s905l3a-cm311.dts  | 182 +++++++++
 .../amlogic/meson-g12a-s905l3a-e900v22c.dts   | 159 ++++++++
 .../dts/amlogic/meson-g12a-s905l3a-m401a.dts  | 165 ++++++++
 .../dts/amlogic/meson-g12a-x96-max-rmii.dts   |  36 ++
 .../amlogic/meson-g12b-a311d-oes-00050000.dts |  17 +
 .../boot/dts/amlogic/meson-g12b-a311d-oes.dts | 377 ++++++++++++++++++
 .../dts/amlogic/meson-g12b-ali-ct2000.dts     |  32 ++
 .../meson-g12b-s922x-oes-plus-00050000.dts    |  17 +
 .../amlogic/meson-g12b-s922x-oes-plus-v2.dts  |  34 ++
 .../dts/amlogic/meson-g12b-s922x-oes-plus.dts | 375 +++++++++++++++++
 .../dts/amlogic/meson-g12b-ugoos-am6-plus.dts | 225 +++++++++++
 .../amlogic/meson-gxbb-beelink-mini-mx.dts    |  21 +
 .../amlogic/meson-gxbb-beelink-mini-mxiii.dts | 177 ++++++++
 .../dts/amlogic/meson-gxbb-mecool-ki-plus.dts |  34 ++
 .../dts/amlogic/meson-gxbb-mecool-kii-pro.dts |  34 ++
 .../dts/amlogic/meson-gxbb-minix-neo-u1.dts   | 190 +++++++++
 .../dts/amlogic/meson-gxbb-mxq-pro-plus.dts   |  57 +++
 18 files changed, 2149 insertions(+)
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a-s905l3a-cm311.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a-s905l3a-e900v22c.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a-s905l3a-m401a.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a-x96-max-rmii.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-a311d-oes-00050000.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-a311d-oes.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-ali-ct2000.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-s922x-oes-plus-00050000.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-s922x-oes-plus-v2.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-s922x-oes-plus.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6-plus.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxbb-beelink-mini-mx.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxbb-beelink-mini-mxiii.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxbb-mecool-ki-plus.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxbb-mecool-kii-pro.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxbb-minix-neo-u1.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxbb-mxq-pro-plus.dts

diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index dc9f2a968..ddf749d30 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -17,12 +17,19 @@ dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12a-fbx8am-brcm.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12a-fbx8am-realtek.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12a-radxa-zero.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12a-s905l3a-cm311.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12a-s905l3a-e900v22c.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12a-s905l3a-m401a.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max-rmii.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-bananapi-m2s.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3-ts050.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-oes.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-oes-00050000.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ali-ct2000.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12b-bananapi-cm4-cm4io.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12b-bananapi-cm4-mnt-reform2.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12b-dreambox-one.dtb
@@ -44,8 +51,18 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2l.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12b-radxa-zero2.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-bananapi-m2s.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-oes-plus.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-oes-plus-00050000.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-oes-plus-v2.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6-plus.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-beelink-mini-mx.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-beelink-mini-mxiii.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-mecool-kii-pro.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-mecool-ki-plus.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-minix-neo-u1.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-mxq-pro-plus.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-s905l3a-cm311.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-s905l3a-cm311.dts
new file mode 100644
index 000000000..2420f01e5
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-s905l3a-cm311.dts
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Create by flippy
+ */
+
+/dts-v1/;
+
+#include "meson-g12a-u200.dts"
+
+/ {
+	compatible = "cm311,m401a,e900v22c", "amlogic,g12a";
+	model = "CM311-1a-YST";
+
+	aliases {
+		serial1 = &uart_A;
+	};
+
+	vddgpu: regulator-vddgpu {
+		compatible = "regulator-fixed";
+		regulator-name = "mali";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <800000>;
+		vin-supply = <&main_12v>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	wifi32k: wifi32k {
+		compatible = "pwm-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+		clocks = <&wifi32k>;
+		clock-names = "ext_clock";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		power_led {
+			led_name = "power_led";
+			gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		green_led {
+			led_name = "green_led";
+			gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			linux,default-trigger = "heartbeat";
+		};
+	/*
+	 *	remote_led {
+	 *		led_name = "remote_led";
+	 *		gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_LOW>;
+	 *		default-state = "off";
+	 *		linux,default-trigger = "rc-feedback";
+	 *	};
+	 */
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+};
+
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	uart-has-rtscts;
+	pinctrl-names = "default";
+};
+
+&mali {
+	mali-supply=<&vddgpu>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+	status = "okay";
+	pinctrl-0 = <&sdio_pins>;
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	bus-width = <4>;
+	cap-sd-highspeed;
+	sd-uhs-sdr50;
+	max-frequency = <100000000>;
+
+	non-removable;
+	disable-wp;
+
+	/* WiFi firmware requires power to be kept while in suspend */
+	keep-power-in-suspend;
+
+	mmc-pwrseq = <&sdio_pwrseq>;
+
+	vmmc-supply = <&vddao_3v3>;
+	vqmmc-supply = <&vddao_1v8>;
+
+	wifi: wifi@1 {
+		reg = <1>;
+		compatible = "sprd,unisoc-wifi";
+	};
+};
+
+/* SD card */
+&sd_emmc_b {
+	status = "okay";
+	bus-width = <4>;
+	cap-sd-highspeed;
+	max-frequency = <50000000>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+	status = "okay";
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	max-frequency = <200000000>;
+};
+
+/* CPU Overclock */
+&cpu_opp_table {
+	opp-100000000 {
+		status = "disabled";
+	};
+
+	opp-250000000 {
+		status = "disabled";
+	};
+
+	opp-500000000 {
+		status = "disabled";
+	};
+
+	opp-667000000 {
+		status = "disabled";
+	};
+
+	opp-1908000000 {
+		opp-hz = /bits/ 64 <1908000000>;
+		opp-microvolt = <1001000>;
+	};
+
+	/* 2016mhz :  not test */
+	//opp-2016000000 {
+	//		opp-hz = /bits/ 64 <2016000000>;
+	//		opp-microvolt = <1021000>;
+	//};
+};
+
+&internal_ephy  {
+	max-speed = <100>;
+};
+
+&ethmac {
+	/delete-property/ resets;
+	/delete-property/ reset-names;
+	phy-handle = <&internal_ephy>;
+	phy-mode = "rmii";
+	status = "okay";
+};
+
+&pwm_ef {
+	pinctrl-0 = <&pwm_e_pins>;
+	pinctrl-names = "default";
+	clocks = <&xtal>;
+	clock-names = "clkin0";
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-s905l3a-e900v22c.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-s905l3a-e900v22c.dts
new file mode 100644
index 000000000..d942f2cd6
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-s905l3a-e900v22c.dts
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Create by flippy
+ */
+
+/dts-v1/;
+
+#include "meson-g12a-u200.dts"
+
+/ {
+	compatible = "skyworth,e900v22c", "amlogic,g12a";
+	model = "SKYWORTH E900V22C";
+
+	vddgpu: regulator-vddgpu {
+		compatible = "regulator-fixed";
+		regulator-name = "mali";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <800000>;
+		vin-supply = <&main_12v>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	wifi32k: wifi32k {
+		compatible = "pwm-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+		clocks = <&wifi32k>;
+		clock-names = "ext_clock";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		
+		power_led {
+			led_name = "power_led";
+                        gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		net_led {
+			led_name = "net_led";
+                        gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			linux,default-trigger = "0.0:00:link";
+		};
+
+		remote_led {
+			led_name = "remote_led";
+                        gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			linux,default-trigger = "rc-feedback";
+		};
+
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+};
+
+&mali {
+	mali-supply=<&vddgpu>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+	status = "okay";
+	pinctrl-0 = <&sdio_pins>;
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	bus-width = <4>;
+	cap-sd-highspeed;
+	sd-uhs-sdr50;
+	max-frequency = <100000000>;
+
+	non-removable;
+	disable-wp;
+
+	/* WiFi firmware requires power to be kept while in suspend */
+	keep-power-in-suspend;
+
+	mmc-pwrseq = <&sdio_pwrseq>;
+
+	vmmc-supply = <&vddao_3v3>;
+	vqmmc-supply = <&vddao_1v8>;
+
+	//wifi: wifi@1 {
+	//	reg = <1>;
+	//	compatible = "unisoc,uwe5622";
+	//};
+};
+
+/* SD card */
+&sd_emmc_b {
+	status = "okay";
+	bus-width = <4>;
+	cap-sd-highspeed;
+	max-frequency = <50000000>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+	status = "okay";
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	max-frequency = <200000000>;
+};
+
+/* CPU Overclock */
+&cpu_opp_table {
+	opp-100000000 {
+		status = "disabled";
+	};
+
+	opp-250000000 {
+		status = "disabled";
+	};
+
+	opp-500000000 {
+		status = "disabled";
+	};
+
+	opp-667000000 {
+		status = "disabled";
+	};
+
+	opp-1908000000 {
+		opp-hz = /bits/ 64 <1908000000>;
+		opp-microvolt = <1001000>;
+	};
+
+	/* 2016mhz :  not test */
+	//opp-2016000000 {
+	//		opp-hz = /bits/ 64 <2016000000>;
+	//		opp-microvolt = <1021000>;
+	//};
+};
+
+&ethmac {
+	/delete-property/ resets;
+	/delete-property/ reset-names;
+	phy-handle = <&internal_ephy>;
+	phy-mode = "rmii";
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-s905l3a-m401a.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-s905l3a-m401a.dts
new file mode 100644
index 000000000..a538d0246
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-s905l3a-m401a.dts
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Create by janko888 2022/11/27
+ */
+ 
+/dts-v1/;
+
+#include "meson-g12a-u200.dts"
+
+/ {
+	compatible = "m401a", "amlogic,g12a";
+	model = "M401A";
+	
+	aliases {
+		serial1 = &uart_A;
+	};
+	
+	vddgpu: regulator-vddgpu {
+		compatible = "regulator-fixed";
+		regulator-name = "mali";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <800000>;
+		vin-supply = <&main_12v>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+	
+	leds {
+		compatible = "gpio-leds";
+
+		power_led {
+			led_name = "power_led";
+			gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		net_led {
+			led_name = "net_led";
+			gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			linux,default-trigger = "0.0:00:link";
+		};
+
+		remote_led {
+			led_name = "remote_led";
+			gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			linux,default-trigger = "rc-feedback";
+		};
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+};
+
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	uart-has-rtscts;
+	pinctrl-names = "default";
+};
+
+&mali {
+	mali-supply=<&vddgpu>;
+};
+
+/* SD card */
+/* No SD card in M401A */
+&sd_emmc_b {
+	status = "disabled";
+	bus-width = <4>;
+	cap-sd-highspeed;
+	max-frequency = <50000000>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+	status = "okay";
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	max-frequency = <100000000>;
+};
+
+/* CPU Overclock */
+&cpu_opp_table {
+	opp-100000000 {
+		opp-hz = /bits/ 64 <100000000>;
+		opp-microvolt = <731000>;
+	};
+
+	opp-250000000 {
+		opp-hz = /bits/ 64 <250000000>;
+		opp-microvolt = <731000>;
+	};
+	
+	opp-500000000 {
+		opp-hz = /bits/ 64 <500000000>;
+		opp-microvolt = <731000>;
+	};
+
+	opp-667000000 {
+		opp-hz = /bits/ 64 <667000000>;
+		opp-microvolt = <731000>;
+	};
+	
+	opp-1000000000 {
+		opp-hz = /bits/ 64 <1000000000>;
+		opp-microvolt = <731000>;
+	};
+
+	opp-1200000000 {
+		opp-hz = /bits/ 64 <1200000000>;
+		//opp-microvolt = <731000>;
+		opp-microvolt = <761000>;
+	};
+
+	opp-1398000000 {
+		opp-hz = /bits/ 64 <1398000000>;
+		//opp-microvolt = <761000>;
+		opp-microvolt = <791000>;
+	};
+
+	opp-1512000000 {
+		opp-hz = /bits/ 64 <1512000000>;
+		//opp-microvolt = <791000>;
+		opp-microvolt = <831000>;
+	};
+
+	opp-1608000000 {
+		opp-hz = /bits/ 64 <1608000000>;
+		//opp-microvolt = <831000>;
+		opp-microvolt = <871000>;
+	};
+
+	opp-1704000000 {
+		opp-hz = /bits/ 64 <1704000000>;
+		//opp-microvolt = <861000>;
+		opp-microvolt = <921000>;
+	};
+	
+	/* some soc has crash under 1800 */
+	opp-1800000000 {
+		opp-hz = /bits/ 64 <1800000000>;
+		opp-microvolt = <981000>;
+		status = "disabled";
+	};
+		
+};
+
+&internal_ephy  {
+	max-speed = <100>;
+};
+
+&ethmac {
+	/delete-property/ resets;
+	/delete-property/ reset-names;
+	phy-handle = <&internal_ephy>;
+	phy-mode = "rmii";
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max-rmii.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max-rmii.dts
new file mode 100644
index 000000000..7090ac100
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max-rmii.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 BayLibre SAS. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-g12a-x96-max.dts"
+
+/ {
+	compatible = "amediatech,x96-max-rmii", "amlogic,u200", "amlogic,g12a";
+	//model = "Shenzhen Amediatech Technology Co., Ltd X96 Max";
+	model = "X96 Max (RMII)";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+};
+
+&ext_mdio {
+	external_phy: ethernet-phy@0 {
+	      compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
+	      reg = <0>;
+	      max-speed = <1000>;
+	      eee-broken-1000t;
+	};
+};
+
+&ethmac {
+        pinctrl-0 = <&eth_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+        phy-mode = "rmii";
+        phy-handle = <&internal_ephy>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-oes-00050000.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-oes-00050000.dts
new file mode 100644
index 000000000..5de85bd80
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-oes-00050000.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2025 retro98boy <retro98boy@qq.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-a311d-oes.dts"
+
+&ethmac {
+	phy-mode = "rgmii-rxid";
+	amlogic,prg-eth-reg0 = <0xffffffff 0x00001629>;
+	amlogic,prg-eth-reg1 = <0xffffffff 0x00050000>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-oes.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-oes.dts
new file mode 100644
index 000000000..202b08682
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-oes.dts
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2025 retro98boy <retro98boy@qq.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-a311d.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "onethingcloud,oes", "amlogic,a311d", "amlogic,g12b";
+	model = "OneThing Cloud OES";
+
+	aliases {
+		serial0 = &uart_AO;
+		ethernet0 = &ethmac;
+		rtc99 = &vrtc;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		kaslr-seed = <0xfeedbeef 0xc0def00d>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0xee6b2800>; /* 4GB */
+	};
+
+	fan0: gpio-fan {
+		compatible = "gpio-fan";
+		gpio-fan,speed-map = <0 0 3000 1>;
+		gpios = <&gpio GPIOC_4 GPIO_ACTIVE_HIGH>;
+		#cooling-cells = <2>;
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		pwr-btn {
+			label = "pwr-btn";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
+		};
+
+		rst-btn {
+			label = "rst-btn";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio GPIOA_0 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		/*
+		 * The circuit design of this device, in its default state (when powered on but the SoC has not started),
+		 * has the red power LED on and the green power LED off.
+		 * Therefore, by simply turning off the red power LED and turning on the green power LED in the kernel,
+		 * it can indicate that the kernel has started.
+		 */
+		pwr-led-green {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		pwr-led-red {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio GPIOA_5 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		/* https://stackoverflow.com/questions/63484352/device-tree-config-for-netdev-trigger-sources-to-control-led-based-on-link-statu */
+		/* cat /sys/class/leds/green\:lan/trigger */
+		lan-led-green {
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio GPIOC_3 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			linux,default-trigger = "mdio_mux-0.0:00:link";
+		};
+
+		lan-led-red {
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio GPIOA_4 GPIO_ACTIVE_HIGH>; /* In fact, a low level lights up the LED. */
+			/*
+			 * The default state is off (low level), meaning that after the SoC starts,
+			 * if no network cable is connected, the red LED lights up by default.
+			 */
+			default-state = "off";
+			linux,default-trigger = "mdio_mux-0.0:00:link";
+		};
+
+		sata1-led-green {
+			function = LED_FUNCTION_DISK;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio GPIOA_14 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			linux,default-trigger = "ata1";
+		};
+
+		sata2-led-green {
+			function = LED_FUNCTION_DISK;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio GPIOA_15 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			linux,default-trigger = "ata2";
+		};
+
+		sata3-led-green {
+			function = LED_FUNCTION_DISK;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio GPIOC_0 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			linux,default-trigger = "ata3";
+		};
+	};
+
+	emmc_pwrseq: emmc-pwrseq {
+		compatible = "mmc-pwrseq-emmc";
+		reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+	};
+
+	dc_in: regulator-dc-in {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_in";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vddao_1v8: regulator-vddao-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vddao_1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&dc_in>;
+	};
+
+	vddcpu_a: regulator-vddcpu-a {
+		compatible = "pwm-regulator";
+		regulator-name = "VDDCPU_A";
+		regulator-min-microvolt = <690000>;
+		regulator-max-microvolt = <1050000>;
+		pwm-supply = <&dc_in>;
+		pwms = <&pwm_ab 0 1250 0>;
+		pwm-dutycycle-range = <100 0>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vddcpu_b: regulator-vddcpu-b {
+		compatible = "pwm-regulator";
+		regulator-name = "VDDCPU_B";
+		regulator-min-microvolt = <690000>;
+		regulator-max-microvolt = <1050000>;
+		pwm-supply = <&dc_in>;
+		pwms = <&pwm_AO_cd 1 1250 0>;
+		pwm-dutycycle-range = <100 0>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vsys_3v3: regulator-vsys-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&dc_in>;
+	};
+
+	usb_pwr: regulator-usb-pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_pwr";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&dc_in>;
+	};
+
+	regulator-sata1-pwr {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+		regulator-name = "sata1_pwr";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&dc_in>;
+	};
+
+	regulator-sata2-pwr {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio GPIOC_5 GPIO_ACTIVE_HIGH>;
+		regulator-name = "sata2_pwr";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&dc_in>;
+	};
+
+	regulator-sata3-pwr {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+		regulator-name = "sata3_pwr";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&dc_in>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vddcpu_b>;
+	operating-points-v2 = <&cpu_opp_table_0>;
+	clocks = <&clkc CLKID_CPU_CLK>;
+	clock-latency = <50000>;
+};
+
+&cpu1 {
+	cpu-supply = <&vddcpu_b>;
+	operating-points-v2 = <&cpu_opp_table_0>;
+	clocks = <&clkc CLKID_CPU_CLK>;
+	clock-latency = <50000>;
+};
+
+&cpu100 {
+	cpu-supply = <&vddcpu_a>;
+	operating-points-v2 = <&cpub_opp_table_1>;
+	clocks = <&clkc CLKID_CPUB_CLK>;
+	clock-latency = <50000>;
+};
+
+&cpu101 {
+	cpu-supply = <&vddcpu_a>;
+	operating-points-v2 = <&cpub_opp_table_1>;
+	clocks = <&clkc CLKID_CPUB_CLK>;
+	clock-latency = <50000>;
+};
+
+&cpu102 {
+	cpu-supply = <&vddcpu_a>;
+	operating-points-v2 = <&cpub_opp_table_1>;
+	clocks = <&clkc CLKID_CPUB_CLK>;
+	clock-latency = <50000>;
+};
+
+&cpu103 {
+	cpu-supply = <&vddcpu_a>;
+	operating-points-v2 = <&cpub_opp_table_1>;
+	clocks = <&clkc CLKID_CPUB_CLK>;
+	clock-latency = <50000>;
+};
+
+&cpu_thermal {
+	trips {
+		cpu_active: cpu-active {
+			temperature = <60000>; /* millicelsius */
+			hysteresis = <5000>; /* millicelsius */
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map2 {
+			trip = <&cpu_active>;
+			cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&ethmac {
+	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	phy-mode = "rgmii";
+	phy-handle = <&rtl8211f>;
+	amlogic,tx-delay-ns = <2>;
+};
+
+&ext_mdio {
+	rtl8211f: rtl8211f@0 {
+		reg = <0>;
+		max-speed = <1000>;
+
+		reset-assert-us = <10000>;
+		reset-deassert-us = <80000>;
+		reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+		interrupt-parent = <&gpio_intc>;
+		/* MAC_INTR on GPIOZ_14 */
+		interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>; /* tested by voltmeter */
+
+		realtek,led-data = <0xc160>;
+	};
+};
+
+&npu {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+	skip-version-detect;
+	reset-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_LOW>; /* tested by voltmeter */
+};
+
+&pwm_ab {
+	status = "okay";
+	pinctrl-0 = <&pwm_a_e_pins>;
+	pinctrl-names = "default";
+	clocks = <&xtal>;
+	clock-names = "clkin0";
+};
+
+&pwm_AO_cd {
+	pinctrl-0 = <&pwm_ao_d_e_pins>;
+	pinctrl-names = "default";
+	clocks = <&xtal>;
+	clock-names = "clkin1";
+	status = "okay";
+};
+
+&sd_emmc_c {
+	status = "okay";
+	pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+
+	max-frequency = <200000000>;
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	non-removable;
+
+	mmc-pwrseq = <&emmc_pwrseq>;
+	vmmc-supply = <&vsys_3v3>;
+	vqmmc-supply = <&vddao_1v8>;
+};
+
+&uart_AO {
+	status = "okay";
+	pinctrl-0 = <&uart_ao_a_pins>;
+	pinctrl-names = "default";
+};
+
+&usb2_phy0 {
+	phy-supply = <&usb_pwr>;
+};
+
+&usb2_phy1 {
+	phy-supply = <&usb_pwr>;
+};
+
+&usb3_pcie_phy {
+	phy-supply = <&usb_pwr>;
+};
+
+&usb {
+	status = "okay";
+	dr_mode = "host";
+	phys = <&usb2_phy0>, <&usb2_phy1>;
+	phy-names = "usb2-phy0", "usb2-phy1";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-ali-ct2000.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-ali-ct2000.dts
new file mode 100644
index 000000000..152e4c6c6
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-ali-ct2000.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2023 flippy
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-gtking-pro.dts"
+#include "meson-g12b-s922x-h.dtsi"
+
+/ {
+	compatible = "ali,ct2000", "amlogic,s922x", "amlogic,g12b";
+	model = "Ali CT2000";
+};
+
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-oes-plus-00050000.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-oes-plus-00050000.dts
new file mode 100644
index 000000000..1e37d9fa3
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-oes-plus-00050000.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2025 retro98boy <retro98boy@qq.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-s922x-oes-plus.dts"
+
+&ethmac {
+	phy-mode = "rgmii-rxid";
+	amlogic,prg-eth-reg0 = <0xffffffff 0x00001629>;
+	amlogic,prg-eth-reg1 = <0xffffffff 0x00050000>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-oes-plus-v2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-oes-plus-v2.dts
new file mode 100644
index 000000000..83c68e363
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-oes-plus-v2.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2025 retro98boy <retro98boy@qq.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-s922x-oes-plus.dts"
+
+/ {
+	model = "OneThing Cloud OES Plus V2.1";
+};
+
+/* Adjust Ethernet PHY configuration */
+&ethmac {
+	phy-mode = "rgmii-rxid";
+	amlogic,invert-rxclk;
+	amlogic,keep-rx-internal-delay;
+	rx-internal-delay-ps = <1000>;
+	amlogic,rx-delay-ns = <8>;
+};
+
+/* Modify fan thermal control strategy */
+&cpu_thermal {
+	trips {
+		cpu_active {
+			temperature = <55000>; /* 55°C */
+			hysteresis = <8000>;   /* 8°C */
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-oes-plus.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-oes-plus.dts
new file mode 100644
index 000000000..d3d5371ba
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-oes-plus.dts
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2025 retro98boy <retro98boy@qq.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-s922x.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "onethingcloud,oes-plus", "amlogic,s922x", "amlogic,g12b";
+	model = "OneThing Cloud OES Plus";
+
+	aliases {
+		serial0 = &uart_AO;
+		ethernet0 = &ethmac;
+		rtc99 = &vrtc;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		kaslr-seed = <0xfeedbeef 0xc0def00d>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0xee6b2800>; /* 4GB */
+	};
+
+	fan0: gpio-fan {
+		compatible = "gpio-fan";
+		gpio-fan,speed-map = <0 0 3000 1>;
+		gpios = <&gpio GPIOC_4 GPIO_ACTIVE_HIGH>;
+		#cooling-cells = <2>;
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		pwr-btn {
+			label = "pwr-btn";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio GPIOA_11 GPIO_ACTIVE_LOW>;
+		};
+
+		rst-btn {
+			label = "rst-btn";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio GPIOA_10 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		/*
+		 * The circuit design of this device, in its default state (when powered on but the SoC has not started),
+		 * has the red power LED on and the green power LED off.
+		 * Therefore, by simply turning off the red power LED and turning on the green power LED in the kernel,
+		 * it can indicate that the kernel has started.
+		 */
+		pwr-led-green {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		pwr-led-red {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		/* https://stackoverflow.com/questions/63484352/device-tree-config-for-netdev-trigger-sources-to-control-led-based-on-link-statu */
+		/* cat /sys/class/leds/green\:lan/trigger */
+		lan-led-green {
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "mdio_mux-0.0:00:link";
+		};
+
+		lan-led-red {
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>; /* In fact, a high level lights up the LED. */
+			/*
+			 * The default state is off (high level), meaning that after the SoC starts,
+			 * if no network cable is connected, the red LED lights up by default.
+			 */
+			default-state = "off";
+			linux,default-trigger = "mdio_mux-0.0:00:link";
+		};
+
+		sata1-led-green {
+			function = LED_FUNCTION_DISK;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio GPIOA_9 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "ata1";
+		};
+
+		sata2-led-green {
+			function = LED_FUNCTION_DISK;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio GPIOA_3 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "ata2";
+		};
+
+		sata3-led-green {
+			function = LED_FUNCTION_DISK;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio GPIOA_4 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "ata3";
+		};
+	};
+
+	emmc_pwrseq: emmc-pwrseq {
+		compatible = "mmc-pwrseq-emmc";
+		reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+	};
+
+	dc_in: regulator-dc-in {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_in";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vddao_1v8: regulator-vddao-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vddao_1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&dc_in>;
+	};
+
+	vddcpu_a: regulator-vddcpu-a {
+		compatible = "pwm-regulator";
+		regulator-name = "VDDCPU_A";
+		regulator-min-microvolt = <690000>;
+		regulator-max-microvolt = <1050000>;
+		pwm-supply = <&dc_in>;
+		pwms = <&pwm_ab 0 1250 0>;
+		pwm-dutycycle-range = <100 0>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vddcpu_b: regulator-vddcpu-b {
+		compatible = "pwm-regulator";
+		regulator-name = "VDDCPU_B";
+		regulator-min-microvolt = <690000>;
+		regulator-max-microvolt = <1050000>;
+		pwm-supply = <&dc_in>;
+		pwms = <&pwm_AO_cd 1 1250 0>;
+		pwm-dutycycle-range = <100 0>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vsys_3v3: regulator-vsys-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&dc_in>;
+	};
+
+	usb_pwr: regulator-usb-pwr {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+		regulator-name = "usb_pwr";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&dc_in>;
+	};
+
+	regulator-sata1-pwr {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio GPIOA_2 GPIO_ACTIVE_HIGH>;
+		regulator-name = "sata1_pwr";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&dc_in>;
+	};
+
+	regulator-sata2-pwr {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio GPIOA_1 GPIO_ACTIVE_HIGH>;
+		regulator-name = "sata2_pwr";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&dc_in>;
+	};
+
+	regulator-sata3-pwr {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio GPIOA_0 GPIO_ACTIVE_HIGH>;
+		regulator-name = "sata3_pwr";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&dc_in>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vddcpu_b>;
+	operating-points-v2 = <&cpu_opp_table_0>;
+	clocks = <&clkc CLKID_CPU_CLK>;
+	clock-latency = <50000>;
+};
+
+&cpu1 {
+	cpu-supply = <&vddcpu_b>;
+	operating-points-v2 = <&cpu_opp_table_0>;
+	clocks = <&clkc CLKID_CPU_CLK>;
+	clock-latency = <50000>;
+};
+
+&cpu100 {
+	cpu-supply = <&vddcpu_a>;
+	operating-points-v2 = <&cpub_opp_table_1>;
+	clocks = <&clkc CLKID_CPUB_CLK>;
+	clock-latency = <50000>;
+};
+
+&cpu101 {
+	cpu-supply = <&vddcpu_a>;
+	operating-points-v2 = <&cpub_opp_table_1>;
+	clocks = <&clkc CLKID_CPUB_CLK>;
+	clock-latency = <50000>;
+};
+
+&cpu102 {
+	cpu-supply = <&vddcpu_a>;
+	operating-points-v2 = <&cpub_opp_table_1>;
+	clocks = <&clkc CLKID_CPUB_CLK>;
+	clock-latency = <50000>;
+};
+
+&cpu103 {
+	cpu-supply = <&vddcpu_a>;
+	operating-points-v2 = <&cpub_opp_table_1>;
+	clocks = <&clkc CLKID_CPUB_CLK>;
+	clock-latency = <50000>;
+};
+
+&cpu_thermal {
+	trips {
+		cpu_active: cpu-active {
+			temperature = <60000>; /* millicelsius */
+			hysteresis = <5000>; /* millicelsius */
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map2 {
+			trip = <&cpu_active>;
+			cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&ethmac {
+	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	phy-mode = "rgmii";
+	phy-handle = <&rtl8211f>;
+	amlogic,tx-delay-ns = <2>;
+};
+
+&ext_mdio {
+	rtl8211f: rtl8211f@0 {
+		reg = <0>;
+		max-speed = <1000>;
+
+		reset-assert-us = <10000>;
+		reset-deassert-us = <80000>;
+		reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+		interrupt-parent = <&gpio_intc>;
+		/* MAC_INTR on GPIOZ_14 */
+		interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>; /* tested by voltmeter */
+
+		realtek,led-data = <0xc160>;
+	};
+};
+
+&pcie {
+	status = "okay";
+	skip-version-detect;
+	reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; /* tested by voltmeter */
+};
+
+&pwm_ab {
+	status = "okay";
+	pinctrl-0 = <&pwm_a_e_pins>;
+	pinctrl-names = "default";
+	clocks = <&xtal>;
+	clock-names = "clkin0";
+};
+
+&pwm_AO_cd {
+	pinctrl-0 = <&pwm_ao_d_e_pins>;
+	pinctrl-names = "default";
+	clocks = <&xtal>;
+	clock-names = "clkin1";
+	status = "okay";
+};
+
+&sd_emmc_c {
+	status = "okay";
+	pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+
+	max-frequency = <200000000>;
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	non-removable;
+
+	mmc-pwrseq = <&emmc_pwrseq>;
+	vmmc-supply = <&vsys_3v3>;
+	vqmmc-supply = <&vddao_1v8>;
+};
+
+&uart_AO {
+	status = "okay";
+	pinctrl-0 = <&uart_ao_a_pins>;
+	pinctrl-names = "default";
+};
+
+&usb2_phy0 {
+	phy-supply = <&usb_pwr>;
+};
+
+&usb2_phy1 {
+	phy-supply = <&usb_pwr>;
+};
+
+&usb3_pcie_phy {
+	phy-supply = <&usb_pwr>;
+};
+
+&usb {
+	status = "okay";
+	dr_mode = "host";
+	phys = <&usb2_phy0>, <&usb2_phy1>;
+	phy-names = "usb2-phy0", "usb2-phy1";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6-plus.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6-plus.dts
new file mode 100644
index 000000000..5acbabc99
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6-plus.dts
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-w400.dtsi"
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+	compatible = "ugoos,am6-plus", "amlogic,s922x", "amlogic,g12b";
+	model = "Ugoos AM6 Plus";
+
+	aliases {
+		rtc0 = &rtc;
+		rtc1 = &vrtc;
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		power-button {
+			label = "power";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-green {
+			label = "power:green";
+			gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	spdif_dit: audio-codec-1 {
+		#sound-dai-cells = <0>;
+		compatible = "linux,spdif-dit";
+		status = "okay";
+		sound-name-prefix = "DIT";
+	};
+
+	sound {
+		compatible = "amlogic,axg-sound-card";
+		model = "AM6-PLUS";
+		audio-aux-devs = <&tdmout_b>;
+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",
+				"TDM_B Playback", "TDMOUT_B OUT",
+				"SPDIFOUT_A IN 0", "FRDDR_A OUT 3",
+				"SPDIFOUT_A IN 1", "FRDDR_B OUT 3",
+				"SPDIFOUT_A IN 2", "FRDDR_C OUT 3";
+
+		clocks = <&clkc CLKID_MPLL2>,
+			 <&clkc CLKID_MPLL0>,
+			 <&clkc CLKID_MPLL1>;
+
+		assigned-clocks = <&clkc CLKID_MPLL2>,
+				  <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <294912000>,
+				       <270950400>,
+				       <393216000>;
+		status = "okay";
+
+		dai-link-0 {
+			sound-dai = <&frddr_a>;
+		};
+
+		dai-link-1 {
+			sound-dai = <&frddr_b>;
+		};
+
+		dai-link-2 {
+			sound-dai = <&frddr_c>;
+		};
+
+		/* 8ch hdmi interface */
+		dai-link-3 {
+			sound-dai = <&tdmif_b>;
+			dai-format = "i2s";
+			dai-tdm-slot-tx-mask-0 = <1 1>;
+			dai-tdm-slot-tx-mask-1 = <1 1>;
+			dai-tdm-slot-tx-mask-2 = <1 1>;
+			dai-tdm-slot-tx-mask-3 = <1 1>;
+			mclk-fs = <256>;
+
+			codec {
+				sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+			};
+		};
+
+		/* spdif hdmi or toslink interface */
+		dai-link-4 {
+			sound-dai = <&spdifout_a>;
+
+			codec-0 {
+				sound-dai = <&spdif_dit>;
+			};
+
+			codec-1 {
+				sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>;
+			};
+		};
+
+		/* spdif hdmi interface */
+		dai-link-5 {
+			sound-dai = <&spdifout_b>;
+
+			codec {
+				sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>;
+			};
+		};
+
+		/* hdmi glue */
+		dai-link-6 {
+			sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+			codec {
+				sound-dai = <&hdmi_tx>;
+			};
+		};
+	};
+};
+
+&arb {
+	status = "okay";
+};
+
+&clkc_audio {
+	status = "okay";
+};
+
+&frddr_a {
+	status = "okay";
+};
+
+&frddr_b {
+	status = "okay";
+};
+
+&frddr_c {
+	status = "okay";
+};
+
+&ir {
+	linux,rc-map-name = "rc-khadas";
+};
+
+&i2c3 {
+	status = "okay";
+	pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+	pinctrl-names = "default";
+
+	rtc: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+	};
+};
+
+&spdifout_a {
+	pinctrl-0 = <&spdif_out_h_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&spdifout_b {
+	status = "okay";
+};
+
+&tdmif_b {
+	status = "okay";
+};
+
+&tdmout_b {
+	status = "okay";
+};
+
+&tohdmitx {
+	status = "okay";
+};
+
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+	clock-names = "lpo";
+	};
+};
+
+&uart_AO {
+	status = "okay";
+	pinctrl-0 = <&uart_ao_a_pins>;
+	pinctrl-names = "default";
+};
+
+&usb {
+	status = "okay";
+	dr_mode = "host";
+	vbus-supply = <&usb_pwr_en>;
+};
+
+&usb2_phy0 {
+	phy-supply = <&usb1_pow>;
+};
+
+&usb2_phy1 {
+	phy-supply = <&usb1_pow>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-beelink-mini-mx.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-beelink-mini-mx.dts
new file mode 100644
index 000000000..792014889
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-beelink-mini-mx.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * meson-gxbb-beelink-mini-mx.dts
+ * Copyright (c) 2022 unifreq
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb-vega-s95.dtsi"
+
+/ {
+	compatible = "azw,mini-mx", "amlogic,meson-gxbb";
+	model = "Beelink Mini MX";
+};
+
+&ethmac {
+
+	amlogic,tx-delay-ns = <4>;
+
+};
+
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-beelink-mini-mxiii.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-beelink-mini-mxiii.dts
new file mode 100644
index 000000000..72f7857d9
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-beelink-mini-mxiii.dts
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb-p20x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-aiu.h>
+
+/ {
+	compatible = "beelink,mini-mxiii", "amlogic,meson-gxbb";
+	model = "Beelink Mini MXIII";
+
+	spdif_dit: audio-codec-0 {
+		#sound-dai-cells = <0>;
+		compatible = "linux,spdif-dit";
+		status = "okay";
+		sound-name-prefix = "DIT";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-power {
+			/* Red in Standby */
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <20>;
+
+		button-reset {
+			label = "reset";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	avdd18_usb_adc: regulator-avdd18_usb_adc {
+		compatible = "regulator-fixed";
+		regulator-name = "AVDD18_USB_ADC";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	sound {
+		compatible = "amlogic,gx-sound-card";
+		model = "MINI-MXIII";
+
+		clocks = <&clkc CLKID_MPLL2>,
+			 <&clkc CLKID_MPLL0>,
+			 <&clkc CLKID_MPLL1>;
+
+		assigned-clocks = <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>,
+				  <&clkc CLKID_MPLL2>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <294912000>,
+				       <270950400>,
+				       <393216000>;
+		status = "okay";
+
+		dai-link-0 {
+			sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+		};
+
+		dai-link-1 {
+			sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>;
+		};
+
+		dai-link-2 {
+			sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+			dai-format = "i2s";
+			mclk-fs = <256>;
+
+			codec-0 {
+				sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+			};
+		};
+
+		dai-link-3 {
+			sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>;
+
+			codec-0 {
+				sound-dai = <&spdif_dit>;
+			};
+		};
+
+		dai-link-4 {
+			sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+			codec-0 {
+				sound-dai = <&hdmi_tx>;
+			};
+		};
+	};
+};
+
+&aiu {
+	status = "okay";
+	pinctrl-0 = <&spdif_out_y_pins>;
+	pinctrl-names = "default";
+};
+
+&ethmac {
+	status = "okay";
+	pinctrl-0 = <&eth_rgmii_pins>;
+	pinctrl-names = "default";
+
+	phy-handle = <&eth_phy0>;
+	phy-mode = "rgmii";
+
+	amlogic,tx-delay-ns = <2>;
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		eth_phy0: ethernet-phy@0 {
+			/* Realtek RTL8211F (0x001cc916) */
+			reg = <0>;
+
+			reset-assert-us = <10000>;
+			reset-deassert-us = <80000>;
+			reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
+			interrupt-parent = <&gpio_intc>;
+			/* MAC_INTR on GPIOZ_15 */
+			interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
+&ir {
+	linux,rc-map-name = "rc-beelink-mxiii";
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&avdd18_usb_adc>;
+};
+
+/* Realtek Wireless SDIO Module */
+&sd_emmc_a {
+	/delete-node/ brcmf;
+
+	rtl8723bs: wifi@1 {
+		reg = <1>;
+		compatible = "realtek,rtl8723bs";
+	};
+};
+
+/* Connected to the Bluetooth module */
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "realtek,rtl8723bs-bt";
+		enable-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
+		host-wake-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>;
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-mecool-ki-plus.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-mecool-ki-plus.dts
new file mode 100644
index 000000000..cb422633a
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-mecool-ki-plus.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Author: Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+#include "meson-gxbb-p201.dts"
+
+/ {
+	compatible = "videostrong,gxbb-ki-plus", "amlogic,meson-gxbb";
+	model = "MeCool KI Plus";
+
+	clock: meson_clock {
+		compatible = "amlogic, gxbb-clock";
+		reg = <0x0 0xc883c000 0x0 0x1000>,
+		      <0x0 0xc8100000 0x0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+		sys_max = <1536000000>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+};
+
+&ir {
+	linux,rc-map-name = "rc-mecool-ki-plus";
+};
+
+&usb_pwr {
+	gpio = <>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-mecool-kii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-mecool-kii-pro.dts
new file mode 100644
index 000000000..0dbcf0f7d
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-mecool-kii-pro.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Author: Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+#include "meson-gxbb-p201.dts"
+
+/ {
+	compatible = "videostrong,gxbb-kii-pro", "amlogic,meson-gxbb";
+	model = "MeCool KII Pro";
+
+	clock: meson_clock {
+		compatible = "amlogic, gxbb-clock";
+		reg = <0x0 0xc883c000 0x0 0x1000>,
+		      <0x0 0xc8100000 0x0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+		sys_max = <1536000000>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+};
+
+&ir {
+	linux,rc-map-name = "rc-mecool-kii-pro";
+};
+
+&usb_pwr {
+	gpio = <>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-minix-neo-u1.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-minix-neo-u1.dts
new file mode 100644
index 000000000..5900ee92c
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-minix-neo-u1.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb-p20x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-aiu.h>
+
+/ {
+	compatible = "minix,neo-u1", "amlogic,meson-gxbb";
+	model = "Minix NEO U1";
+
+	aliases {
+		rtc0 = &rtc;
+		rtc1 = &vrtc;
+	};
+
+	spdif_dit: audio-codec-0 {
+		#sound-dai-cells = <0>;
+		compatible = "linux,spdif-dit";
+		status = "okay";
+		sound-name-prefix = "DIT";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-status {
+			color = <LED_COLOR_ID_WHITE>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <20>;
+
+		button-reset {
+			label = "reset";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	avdd18_usb_adc: regulator-avdd18_usb_adc {
+		compatible = "regulator-fixed";
+		regulator-name = "AVDD18_USB_ADC";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	sound {
+		compatible = "amlogic,gx-sound-card";
+		model = "MINIX-NEO";
+		assigned-clocks = <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>,
+				  <&clkc CLKID_MPLL2>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <294912000>,
+				       <270950400>,
+				       <393216000>;
+		status = "okay";
+
+		dai-link-0 {
+			sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+		};
+
+		dai-link-1 {
+			sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>;
+		};
+
+		dai-link-2 {
+			sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+			dai-format = "i2s";
+			mclk-fs = <256>;
+
+			codec-0 {
+				sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+			};
+		};
+
+		dai-link-3 {
+			sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>;
+
+			codec-0 {
+				sound-dai = <&spdif_dit>;
+			};
+		};
+
+		dai-link-4 {
+			sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+			codec-0 {
+				sound-dai = <&hdmi_tx>;
+			};
+		};
+	};
+};
+
+&aiu {
+	status = "okay";
+	pinctrl-0 = <&spdif_out_y_pins>;
+	pinctrl-names = "default";
+};
+
+&ethmac {
+	status = "okay";
+	pinctrl-0 = <&eth_rgmii_pins>;
+	pinctrl-names = "default";
+
+	phy-handle = <&eth_phy0>;
+	phy-mode = "rgmii";
+
+	amlogic,tx-delay-ns = <2>;
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		eth_phy0: ethernet-phy@0 {
+			/* Realtek RTL8211F (0x001cc916) */
+			reg = <0>;
+
+			reset-assert-us = <10000>;
+			reset-deassert-us = <80000>;
+			reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
+			interrupt-parent = <&gpio_intc>;
+			/* MAC_INTR on GPIOZ_15 */
+			interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
+&ir {
+	linux,rc-map-name = "rc-minix-neo";
+};
+
+&i2c_A {
+	status = "okay";
+	pinctrl-0 = <&i2c_a_pins>;
+	pinctrl-names = "default";
+};
+
+&i2c_B {
+	status = "okay";
+	pinctrl-0 = <&i2c_b_pins>;
+	pinctrl-names = "default";
+
+	rtc: rtc@51 {
+		status = "okay";
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+		wakeup-source;
+	};
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&avdd18_usb_adc>;
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "bcm43438-bt";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-mxq-pro-plus.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-mxq-pro-plus.dts
new file mode 100644
index 000000000..bb804a914
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-mxq-pro-plus.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Flippy
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb-vega-s95.dtsi"
+
+/ {
+	compatible = "crocon,mxq-pro-plus", "amlogic,meson-gxbb";
+	model = "MXQ Pro+ (S905)";
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+                /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
+                secmon_reserved_bl32: secmon@5300000 {
+                        reg = <0x0 0x05300000 0x0 0x2000000>;
+                        no-map;
+                };
+
+		/* 2MiB reserved for ARM Trusted Firmware (BL31) */
+		secmon: secmon {
+			reg = <0x0 0x10000000 0x0 0x200000>;
+			no-map;
+		};
+	};
+
+	memory@0 {
+		device_type = "memory";
+		/*
+		 * The first 16MiB of the DDR memory zone
+		 * is reserved to the Hardware ROM Firmware
+		 */
+		linux,usable-memory = <0x0 0x1000000 0x0 0x7f000000>;
+	};
+};
+
+&ethmac {
+	amlogic,tx-delay-ns = <4>;
+	snps,aal;
+	snps,txpbl = <0x8>;
+	snps,rxpbl = <0x8>;
+};
+
+/*
+&eth_phy0 {
+	interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
+};
+*/
+
+&sd_emmc_c {
+	max-frequency = <200000000>;	
+};


================================================
FILE: kernel-patch/beta/deprecated-patches/6.18.y-302-dts-add-gxl-series-devices.patch
================================================
From 53ff558309689798c7c075d72afb2101ffaa6702 Mon Sep 17 00:00:00 2001
From: ophub <68696949+ophub@users.noreply.github.com>
Date: Sat, 31 Jan 2026 17:11:47 +0800
Subject: [PATCH] arch: arm64: dts: amlogic: add gxl Series devices

---
 arch/arm64/boot/dts/amlogic/Makefile          |  13 +
 .../meson-gxl-s905d-mecool-ki-plus.dts        |  21 ++
 .../amlogic/meson-gxl-s905d-mecool-ki-pro.dts |  16 +
 .../meson-gxl-s905d-mecool-m8s-plus.dts       |  16 +
 .../meson-gxl-s905d-phicomm-n1-thresh.dts     |  13 +
 .../dts/amlogic/meson-gxl-s905l-venz-v10.dts  | 326 ++++++++++++++++++
 .../dts/amlogic/meson-gxl-s905l2-ipbs9505.dts |  20 ++
 .../dts/amlogic/meson-gxl-s905l2-x7-5g.dts    |  29 ++
 .../amlogic/meson-gxl-s905l3b-e900v22e.dts    |  21 ++
 .../dts/amlogic/meson-gxl-s905l3b-m302a.dts   |  48 +++
 .../dts/amlogic/meson-gxl-s905w-x96-mini.dts  |  22 ++
 .../boot/dts/amlogic/meson-gxl-s905w-x96w.dts |  83 +++++
 .../dts/amlogic/meson-gxl-s905x-b860h.dts     |  19 +
 .../amlogic/meson-gxl-s905x-bestv-r3300-l.dts | 227 ++++++++++++
 14 files changed, 874 insertions(+)
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-ki-plus.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-ki-pro.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-m8s-plus.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1-thresh.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905l-venz-v10.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905l2-ipbs9505.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905l2-x7-5g.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905l3b-e900v22e.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905l3b-m302a.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905w-x96-mini.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905w-x96w.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x-b860h.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x-bestv-r3300-l.dts

diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index ddf749d30..ce7b506d5 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -77,15 +77,28 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-libretech-ac.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805y-xiaomi-aquaman.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-mecool-ki-plus.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-mecool-ki-pro.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-mecool-kii-pro.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-mecool-m8s-plus.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1-thresh.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-sml5442tw.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-vero4k-plus.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905l-venz-v10.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905l2-ipbs9505.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905l2-x7-5g.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905l3b-e900v22e.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905l3b-m302a.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-jethome-jethub-j80.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-x96-mini.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-x96w.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-b860h.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-bestv-r3300-l.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-ki-plus.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-ki-plus.dts
new file mode 100644
index 000000000..b4aed5d0d
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-ki-plus.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Author: Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+#include "meson-gxl-s905d-p231.dts"
+
+/ {
+	compatible = "videostrong,gxl-ki-plus", "amlogic,s905d", "amlogic,meson-gxl";
+	model = "MeCool KI Plus";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+};
+
+&ir {
+	linux,rc-map-name = "rc-mecool-ki-plus";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-ki-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-ki-pro.dts
new file mode 100644
index 000000000..af6956207
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-ki-pro.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Author: Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+#include "meson-gxl-s905d-p230.dts"
+
+/ {
+	compatible = "videostrong,gxl-ki-pro", "amlogic,s905d", "amlogic,meson-gxl";
+	model = "MeCool KI Pro";
+};
+
+&ir {
+	linux,rc-map-name = "rc-mecool-ki-pro";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-m8s-plus.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-m8s-plus.dts
new file mode 100644
index 000000000..3ddcf59d2
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-m8s-plus.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Author: Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+#include "meson-gxl-s905d-p231.dts"
+
+/ {
+	compatible = "videostrong,gxl-kii-pro", "amlogic,s905d", "amlogic,meson-gxl";
+	model = "MeCool M8S Plus";
+};
+
+&ir {
+	linux,rc-map-name = "rc-mecool-m8s-plus";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1-thresh.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1-thresh.dts
new file mode 100644
index 000000000..8f178fb7c
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1-thresh.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 He Yangxuan
+ * Copyright (c) 2020 Flippy
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905d-phicomm-n1.dts"
+
+&ethmac {
+	snps,force_thresh_dma_mode;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905l-venz-v10.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905l-venz-v10.dts
new file mode 100644
index 000000000..553377fce
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905l-venz-v10.dts
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-aiu.h>
+
+/ {
+	compatible = "venz,v10", "amlogic,s905l", "amlogic,meson-gxl";
+	model = "Venz V10";
+
+	aliases {
+		serial0 = &uart_AO;
+		ethernet0 = &ethmac;
+		wlan0 = &rtl8189;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	dio2133: analog-amplifier {
+		compatible = "simple-audio-amplifier";
+		sound-name-prefix = "AU2";
+		VCC-supply = <&hdmi_5v>;
+		enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-standby {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+                };
+        };
+
+	cvbs-connector {
+		compatible = "composite-video-connector";
+
+		port {
+			cvbs_connector_in: endpoint {
+				remote-endpoint = <&cvbs_vdac_out>;
+			};
+		};
+	};
+
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&hdmi_tx_tmds_out>;
+			};
+		};
+	};
+
+	hdmi_5v: regulator-hdmi-5v {
+		compatible = "regulator-fixed";
+
+		regulator-name = "HDMI_5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+
+		gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	vddio_boot: regulator-vddio_boot {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDIO_BOOT";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vddao_3v3: regulator-vddao_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDAO_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vddio_ao18: regulator-vddio_ao18 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDIO_AO18";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vcc_3v3: regulator-vcc_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	emmc_pwrseq: emmc-pwrseq {
+		compatible = "mmc-pwrseq-emmc";
+		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+	};
+
+	wifi32k: wifi32k {
+		compatible = "pwm-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+		clocks = <&wifi32k>;
+		clock-names = "ext_clock";
+	};
+
+	sound {
+		compatible = "amlogic,gx-sound-card";
+		model = "VENZ-V10";
+		audio-aux-devs = <&dio2133>;
+		audio-widgets = "Line", "Lineout";
+		audio-routing = "AU2 INL", "ACODEC LOLN",
+				"AU2 INR", "ACODEC LORN",
+				"Lineout", "AU2 OUTL",
+				"Lineout", "AU2 OUTR";
+		assigned-clocks = <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>,
+				  <&clkc CLKID_MPLL2>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <294912000>,
+				       <270950400>,
+				       <393216000>;
+		status = "okay";
+
+		dai-link-0 {
+			sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+		};
+
+		dai-link-1 {
+			sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+			dai-format = "i2s";
+			mclk-fs = <256>;
+
+			codec-0 {
+				sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+			};
+
+			codec-1 {
+				sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
+			};
+		};
+
+		dai-link-2 {
+			sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+			codec-0 {
+				sound-dai = <&hdmi_tx>;
+			};
+		};
+
+		dai-link-3 {
+			sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
+
+			codec-0 {
+				sound-dai = <&acodec>;
+			};
+		};
+	};
+};
+
+&acodec {
+	AVDD-supply = <&vddio_ao18>;
+	status = "okay";
+};
+
+&aiu {
+	status = "okay";
+};
+
+&cec_AO {
+	status = "okay";
+	pinctrl-0 = <&ao_cec_pins>;
+	pinctrl-names = "default";
+	hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+	cvbs_vdac_out: endpoint {
+		remote-endpoint = <&cvbs_connector_in>;
+	};
+};
+
+&ethmac {
+	status = "okay";
+};
+
+&hdmi_tx {
+	status = "okay";
+	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+	pinctrl-names = "default";
+	hdmi-supply = <&hdmi_5v>;
+};
+
+&hdmi_tx_tmds_port {
+	hdmi_tx_tmds_out: endpoint {
+		remote-endpoint = <&hdmi_connector_in>;
+	};
+};
+
+&ir {
+	status = "okay";
+	pinctrl-0 = <&remote_input_ao_pins>;
+	pinctrl-names = "default";
+	linux,rc-map-name = "rc-venz-v10";
+};
+
+&pwm_ef {
+	status = "okay";
+	pinctrl-0 = <&pwm_e_pins>;
+	pinctrl-names = "default";
+	clocks = <&clkc CLKID_FCLK_DIV4>;
+	clock-names = "clkin0";
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+	status = "okay";
+	pinctrl-0 = <&sdio_pins>;
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	bus-width = <4>;
+	cap-sd-highspeed;
+	max-frequency = <100000000>;
+
+	non-removable;
+	disable-wp;
+
+	/* WiFi firmware requires power to be kept while in suspend */
+	keep-power-in-suspend;
+
+	mmc-pwrseq = <&sdio_pwrseq>;
+
+	vmmc-supply = <&vddao_3v3>;
+	vqmmc-supply = <&vddio_boot>;
+
+	rtl8189: wifi@1 {
+		reg = <1>;
+	};
+};
+
+/* SD card */
+&sd_emmc_b {
+	status = "okay";
+	pinctrl-0 = <&sdcard_pins>;
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+
+	bus-width = <4>;
+	cap-sd-highspeed;
+	max-frequency = <50000000>;
+	disable-wp;
+
+	cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
+
+	vmmc-supply = <&vddao_3v3>;
+	vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+	status = "okay";
+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	max-frequency = <200000000>;
+	non-removable;
+	disable-wp;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+
+	mmc-pwrseq = <&emmc_pwrseq>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vddio_boot>;
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
+	status = "okay";
+	pinctrl-0 = <&uart_ao_a_pins>;
+	pinctrl-names = "default";
+};
+
+&usb {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usb2_phy0 {
+	/* HDMI_5V is the supply for the USB VBUS */
+	phy-supply = <&hdmi_5v>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905l2-ipbs9505.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905l2-ipbs9505.dts
new file mode 100644
index 000000000..4503d01da
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905l2-ipbs9505.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>, flippy
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905l2-x7-5g.dts"
+
+/ {
+	compatible = "amlogic,ipbs9505", "amlogic,s905l2", "amlogic,meson-gxl";
+	model = "Wojia TV IPBS9505";
+};
+
+/* eMMC */
+// Reduce the frequency from 200000000 to 100000000 to solve the emmc usage problem
+&sd_emmc_c {
+	max-frequency = <100000000>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905l2-x7-5g.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905l2-x7-5g.dts
new file mode 100644
index 000000000..8efc85e0e
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905l2-x7-5g.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905w-p281.dts"
+
+/ {
+	compatible = "amlogic,x7-5g", "amlogic,s905l2", "amlogic,meson-gxl";
+	model = "Amlogic Meson GXL (S905L2) X7 5G Tv Box";
+};
+
+// the gpu in the S905L2 has one pp core less
+// (i.e. only two in total) than the one in the other S905X/W
+&mali {
+	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+		<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+		<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+		<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+		<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+		<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+		<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+		<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "gp", "gpmmu", "pp", "pmu",
+		"pp0", "ppmmu0", "pp1", "ppmmu1";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905l3b-e900v22e.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905l3b-e900v22e.dts
new file mode 100644
index 000000000..1c0854c82
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905l3b-e900v22e.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * Copyright (c) flippy
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905l2-x7-5g.dts"
+
+/ {
+	compatible = "amlogic,s905l3b", "amlogic,meson-gxl";
+	model = "Skyworth E900V22E";
+};
+
+/* eMMC */
+&sd_emmc_c {
+	status = "okay";
+	max-frequency = <52000000>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905l3b-m302a.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905l3b-m302a.dts
new file mode 100644
index 000000000..3c91ccab5
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905l3b-m302a.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905w-p281.dts"
+
+/ {
+	compatible = "amlogic,m302a", "amlogic,s905w", "amlogic,meson-gxl";
+	model = "Amlogic Meson GXL (S905L3b) MBH-M302A Box";
+	
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+};
+
+// the gpu in the S905L2 has one pp core less
+// (i.e. only two in total) than the one in the other S905X/W
+
+&mali {
+	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+		<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+		<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+		<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+		<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+		<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+		<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+		<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "gp", "gpmmu", "pp", "pmu","pp0", "ppmmu0", "pp1", "ppmmu1";
+};
+
+&sd_emmc_c {
+	status = "okay";
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	max-frequency = <200000000>;
+};
+
+&internal_phy {
+	max-speed = <100>;
+};
\ No newline at end of file
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-x96-mini.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-x96-mini.dts
new file mode 100644
index 000000000..d9a24cc8d
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-x96-mini.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gxl-s905d-p231.dts:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ *   Author: Carlo Caione <carlo@endlessm.com>
+ *           github.com/TThanhXuan, github.com/box-automation1, github.com/unifreq
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905w-p281.dts"
+
+/ {
+	compatible = "amlogic,p281", "amlogic,s905w", "amlogic,meson-gxl";
+	model = "X96 mini";
+};
+
+/* eMMC */
+&sd_emmc_c {
+	max-frequency = <50000000>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-x96w.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-x96w.dts
new file mode 100644
index 000000000..3ab4f66d8
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-x96w.dts
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gxl-s905d-p231.dts:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * - Copyright (c) unifreq
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905w-p281.dts"
+
+/ {
+	compatible = "amlogic,p281", "amlogic,s905w", "amlogic,meson-gxl";
+	model = "X96W";
+
+	aliases {
+		serial0 = &uart_AO;   /* Console */
+		serial1 = &uart_A;    /* Bluetooth */
+		ethernet0 = &ethmac;
+	};
+};
+
+/* SDIO wifi: AP6255 */
+&sd_emmc_a {
+	status = "okay";
+
+	brcmf: wifi@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+	};
+};
+
+/* SD card */
+&sd_emmc_b {
+	status = "okay";
+	bus-width = <4>;
+	cap-sd-highspeed;
+	max-frequency = <50000000>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+	status = "okay";
+	max-frequency = <50000000>;
+};
+
+/* Console UART */
+&uart_AO {
+	status = "okay";
+	pinctrl-0 = <&uart_ao_a_pins>;
+	pinctrl-names = "default";
+};
+
+/* S905W only has access to its internal PHY */
+&ethmac {
+	status = "okay";
+	phy-mode = "rmii";
+	phy-handle = <&internal_phy>;
+};
+
+&internal_phy {
+	status = "okay";
+	pinctrl-0 = <&eth_link_led_pins>, <&eth_act_led_pins>;
+	pinctrl-names = "default";
+	max-speed = <100>;
+};
+
+/* This is connected to the Bluetooth module: AP6255 */
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm4345c5";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-b860h.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-b860h.dts
new file mode 100644
index 000000000..956941fb2
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-b860h.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905x-p212.dts"
+
+/ {
+	compatible = "zte,b860h", "amlogic,p212";
+	model = "ZTE B860H";
+
+};
+
+&sdio_pwrseq {
+	reset-gpios = <&gpio GPIODV_27 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-bestv-r3300-l.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-bestv-r3300-l.dts
new file mode 100644
index 000000000..d67705806
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-bestv-r3300-l.dts
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2025 retro98boy <retro98boy@qq.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905x-p212.dtsi"
+#include <dt-bindings/sound/meson-aiu.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "bestv,r3300-l", "amlogic,s905x", "amlogic,meson-gxl";
+	model = "BesTV R3300-L";
+
+	aliases {
+		rtc1 = &vrtc;
+	};
+
+	memory@0 {
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		rst-btn {
+			label = "rst-btn";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		/*
+		 * The power LED on the device is always on, defaulting to red.
+		 * Pulling GPIODV_24 high changes it to green, indicating that the kernel has started.
+		 */
+		pwr-led-green {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		/*
+		 * GPIOAO_4 is used to turn on the WLAN LED, defaulting to red,
+		 * and GPIODV_27 is used to change the color of the WLAN LED.
+		 */
+		wlan-led-red {
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		/*
+		 * modprobe ledtrig-netdev
+		 * echo netdev > /sys/class/leds/green\:wlan/trigger
+		 * echo wlan0 > /sys/class/leds/green\:wlan/device_name
+		 *
+		 * echo 1 > /sys/class/leds/green\:wlan/link
+		 * or
+		 * echo 1 > /sys/class/leds/green\:wlan/rx
+		 */
+		wlan-led-green {
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "netdev";
+		};
+	};
+
+	dio2128: analog-amplifier {
+		compatible = "simple-audio-amplifier";
+		sound-name-prefix = "AU2";
+		VCC-supply = <&hdmi_5v>;
+		enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+	};
+
+	cvbs-connector {
+		compatible = "composite-video-connector";
+
+		port {
+			cvbs_connector_in: endpoint {
+				remote-endpoint = <&cvbs_vdac_out>;
+			};
+		};
+	};
+
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&hdmi_tx_tmds_out>;
+			};
+		};
+	};
+
+	sound {
+		compatible = "amlogic,gx-sound-card";
+		model = "S905X-P212";
+		audio-aux-devs = <&dio2128>;
+		audio-widgets = "Line", "Lineout";
+		audio-routing = "AU2 INL", "ACODEC LOLN",
+				"AU2 INR", "ACODEC LORN",
+				"Lineout", "AU2 OUTL",
+				"Lineout", "AU2 OUTR";
+		clocks = <&clkc CLKID_MPLL0>,
+			 <&clkc CLKID_MPLL1>,
+			 <&clkc CLKID_MPLL2>;
+
+		assigned-clocks = <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>,
+				  <&clkc CLKID_MPLL2>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <294912000>,
+				       <270950400>,
+				       <393216000>;
+		dai-link-0 {
+			sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+		};
+
+		dai-link-1 {
+			sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+			dai-format = "i2s";
+			mclk-fs = <256>;
+
+			codec-0 {
+				sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+			};
+
+			codec-1 {
+				sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
+			};
+		};
+
+		dai-link-2 {
+			sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+			codec-0 {
+				sound-dai = <&hdmi_tx>;
+			};
+		};
+
+		dai-link-3 {
+			sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
+
+			codec-0 {
+				sound-dai = <&acodec>;
+			};
+		};
+	};
+};
+
+&acodec {
+	AVDD-supply = <&vddio_ao18>;
+	status = "okay";
+};
+
+&aiu {
+	status = "okay";
+};
+
+&cec_AO {
+	status = "okay";
+	pinctrl-0 = <&ao_cec_pins>;
+	pinctrl-names = "default";
+	hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+	cvbs_vdac_out: endpoint {
+		remote-endpoint = <&cvbs_connector_in>;
+	};
+};
+
+&emmc_pwrseq {
+	reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; /* not sure */
+};
+
+&hdmi_5v {
+	/delete-property/ gpio;
+	/delete-property/ enable-active-high;
+};
+
+&hdmi_tx {
+	status = "okay";
+	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+	pinctrl-names = "default";
+	hdmi-supply = <&hdmi_5v>;
+};
+
+&hdmi_tx_tmds_port {
+	hdmi_tx_tmds_out: endpoint {
+		remote-endpoint = <&hdmi_connector_in>;
+	};
+};
+
+&sd_emmc_b {
+	max-frequency = <200000000>;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+};
+
+&sd_emmc_c {
+	mmc-hs400-1_8v;
+};
+
+&uart_A {
+	status = "disabled";
+	/delete-node/ bluetooth;
+};
+
+&usb {
+	dr_mode = "otg";
+};


================================================
FILE: kernel-patch/beta/deprecated-patches/6.18.y-303-dts-add-gxm-sm1-series-devices.patch
================================================
From 608f58454db999d0f9d5f39fd3090123fdbcc2f1 Mon Sep 17 00:00:00 2001
From: ophub <68696949+ophub@users.noreply.github.com>
Date: Sat, 31 Jan 2026 17:33:17 +0800
Subject: [PATCH] arch: arm64: dts: amlogic: add gxm, sm1 Series devices

---
 arch/arm64/boot/dts/amlogic/Makefile          |  25 ++
 .../amlogic/meson-gxm-fake-octopus-planet.dts |  12 +
 .../boot/dts/amlogic/meson-gxm-nexbox-a2.dts  |  60 ++++
 .../dts/amlogic/meson-gxm-octopus-planet.dts  |  58 ++++
 .../boot/dts/amlogic/meson-gxm-phicomm-t1.dts |  32 ++
 .../boot/dts/amlogic/meson-gxm-t95z-plus.dts  |  59 ++++
 .../boot/dts/amlogic/meson-gxm-tx8-max.dts    |  30 ++
 .../dts/amlogic/meson-sm1-h96-max-x3-oc.dts   |  24 ++
 .../boot/dts/amlogic/meson-sm1-h96-max-x3.dts | 273 +++++++++++++++++
 .../amlogic/meson-sm1-hk1box-vontar-x3-oc.dts |  24 ++
 .../amlogic/meson-sm1-hk1box-vontar-x3.dts    | 262 ++++++++++++++++
 .../meson-sm1-skyworth-lb2004-a4091.dts       | 288 ++++++++++++++++++
 .../boot/dts/amlogic/meson-sm1-tx3-bz-oc.dts  |  20 ++
 .../boot/dts/amlogic/meson-sm1-tx3-bz.dts     | 223 ++++++++++++++
 .../boot/dts/amlogic/meson-sm1-tx3-qz-oc.dts  |  20 ++
 .../boot/dts/amlogic/meson-sm1-tx3-qz.dts     | 251 +++++++++++++++
 .../boot/dts/amlogic/meson-sm1-x88-pro-x3.dts |  90 ++++++
 .../amlogic/meson-sm1-x96-max-plus-100m.dts   |  16 +
 .../amlogic/meson-sm1-x96-max-plus-2101.dts   | 254 +++++++++++++++
 .../amlogic/meson-sm1-x96-max-plus-a100.dts   |  21 ++
 .../meson-sm1-x96-max-plus-ip1001m-2.dts      |  44 +++
 .../meson-sm1-x96-max-plus-ip1001m.dts        |  43 +++
 .../dts/amlogic/meson-sm1-x96-max-plus-oc.dts |  24 ++
 .../dts/amlogic/meson-sm1-x96-max-plus-q1.dts |  41 +++
 .../dts/amlogic/meson-sm1-x96-max-plus-q2.dts |  21 ++
 .../dts/amlogic/meson-sm1-x96-max-plus.dts    | 255 ++++++++++++++++
 26 files changed, 2470 insertions(+)
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-fake-octopus-planet.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a2.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-octopus-planet.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-phicomm-t1.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-t95z-plus.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-tx8-max.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-h96-max-x3-oc.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-h96-max-x3.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-hk1box-vontar-x3-oc.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-hk1box-vontar-x3.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-skyworth-lb2004-a4091.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-tx3-bz-oc.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-tx3-bz.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-tx3-qz-oc.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-tx3-qz.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-x88-pro-x3.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-100m.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-2101.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-a100.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-ip1001m-2.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-ip1001m.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-oc.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-q1.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-q2.dts
 create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus.dts

diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index ce7b506d5..8589b093f 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -107,15 +107,21 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-vero4k.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxlx-s905l-p271.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-fake-octopus-planet.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-gt1-ultimate.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-mecool-kiii-pro.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-minix-neo-u9h.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a2.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-octopus-planet.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-phicomm-t1.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-t95z-plus.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-tx8-max.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-tx9-pro.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-ugoos-am3.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
@@ -125,15 +131,34 @@ dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air-gbit.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m2-pro.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m5.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-h96-max-x3-oc.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-h96-max-x3.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-sm1-h96-max.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-hk1box-vontar-x3-oc.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-hk1box-vontar-x3.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l-ts050.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-sm1-s905d3-libretech-cc.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-skyworth-lb2004-a4091.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-tx3-bz-oc.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-tx3-bz.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-tx3-qz-oc.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-tx3-qz.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x88-pro-x3.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air-gbit.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-max-plus-100m.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-max-plus-2101.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-max-plus-a100.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-max-plus-ip1001m-2.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-max-plus-ip1001m.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-max-plus-oc.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-max-plus-q1.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-max-plus-q2.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-max-plus.dtb
 
 # Overlays
 meson-g12a-fbx8am-brcm-dtbs	:= meson-g12a-fbx8am.dtb meson-g12a-fbx8am-brcm.dtbo
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-fake-octopus-planet.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-fake-octopus-planet.dts
new file mode 100644
index 000000000..713fb33e4
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-fake-octopus-planet.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Flippy
+ */
+
+/dts-v1/;
+
+#include "meson-gxm-octopus-planet.dts"
+
+/ {
+	model = "Fake Octopus Planet";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a2.dts
new file mode 100644
index 000000000..eed99ca8a
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a2.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 by sibondt
+ */
+
+/dts-v1/;
+
+#include "meson-gxm-q200.dts"
+
+/ {
+	compatible = "nexbox,a2", "amlogic,s912", "amlogic,meson-gxm";
+	model = "Nexbox a95x-a2";
+};
+
+&ethmac {
+	snps,aal;
+	snps,txpbl = <0x8>;
+	snps,rxpbl = <0x8>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+	status = "okay";
+	pinctrl-0 = <&sdio_pins>;
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	bus-width = <4>;
+	cap-sd-highspeed;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	min-frequency = <400000>;
+	max-frequency = <199999997>;
+
+	non-removable;
+	disable-wp;
+
+	/* WiFi firmware requires power to be kept while in suspend */
+	keep-power-in-suspend;
+
+	mmc-pwrseq = <&sdio_pwrseq>;
+
+	vmmc-supply = <&vddao_3v3>;
+	vqmmc-supply = <&vddio_boot>;
+};
+
+&sd_emmc_b {
+        status = "okay";
+};
+
+&sd_emmc_c {
+        status = "okay";
+};
+
+&uart_A {
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-octopus-planet.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-octopus-planet.dts
new file mode 100644
index 000000000..e318c187d
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-octopus-planet.dts
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Flippy
+ */
+
+/dts-v1/;
+
+#include "meson-gxm-q200.dts"
+
+/ {
+	model = "Octopus Planet";
+
+	leds {
+		compatible = "gpio-leds";
+
+		green_led {
+			label = "green";
+			gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "usb-host";
+		};
+
+		blue_led {
+			label = "blue";
+			gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>;
+			//linux,default-trigger = "mdio_mux-0.2009087f:00:link";
+			linux,default-trigger = "mmc2";
+		};
+
+		red_led {
+			label = "red";
+			gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+	};
+};
+
+&ethmac {
+	snps,aal;
+	snps,txpbl = <0x8>;
+	snps,rxpbl = <0x8>;
+};
+
+&sd_emmc_a {
+        status = "disabled";
+};
+
+&sd_emmc_b {
+        status = "okay";
+};
+
+&sd_emmc_c {
+        status = "okay";
+};
+
+&uart_A {
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-phicomm-t1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-phicomm-t1.dts
new file mode 100644
index 000000000..5168fc37a
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-phicomm-t1.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * Create by flippy
+ */
+
+/dts-v1/;
+
+#include "meson-gxm-q201.dts"
+
+/ {
+	compatible = "phicomm,t1", "amlogic,meson-gxm";
+	model = "Phicomm T1";
+
+	aliases {
+		serial1 = &uart_A;
+	};
+};
+
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-t95z-plus.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-t95z-plus.dts
new file mode 100644
index 000000000..88bd550d3
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-t95z-plus.dts
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>, flippy
+*/
+
+/dts-v1/;
+
+#include "meson-gxm.dtsi"
+#include "meson-gx-p23x-q20x.dtsi"
+
+/ {
+        compatible = "amlogic,q201", "amlogic,s912", "amlogic,meson-gxm";
+        model = "T95Z Plus";
+
+        openvfd {
+                compatible = "open,vfd";
+                dev_name = "openvfd";
+                status = "okay";
+        };
+};
+
+&ethmac {
+        phy-mode = "rgmii";
+        pinctrl-0 = <&eth_pins>;
+        pinctrl-names = "default";
+        reg = <0x0 0xc9410000 0x0 0x10000
+                0x0 0xc8834540 0x0 0x8
+                0x0 0xc8834558 0x0 0xc>;
+
+        /* Select external PHY by default */
+        phy-handle = <&external_phy>;
+
+        amlogic,tx-delay-ns = <2>;
+
+        /* External PHY reset is shared with internal PHY Led signals */
+        snps,reset-gpio = <&gpio GPIOZ_14 0>;
+        snps,reset-delays-us = <0 10000 1000000>;
+        snps,reset-active-low;
+};
+
+&external_mdio {
+        external_phy: ethernet-phy@0 {
+                /* T95Z Plus's phy has phy id = 0381:5c11 */
+                compatible = "ethernet-phy-id0381.5c11", "ethernet-phy-ieee802.3-c22";
+                /* T95Z Plus's phy has phy addr = 1 */
+                reg = <1>;
+                max-speed = <1000>;
+                interrupt-parent = <&gpio_intc>;
+                interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
+        };
+};
+
+&sd_emmc_a {
+        brcmf: wifi@1 {
+                reg = <1>;
+                compatible = "brcm,bcm4329-fmac";
+        };
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-tx8-max.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-tx8-max.dts
new file mode 100644
index 000000000..a34a312ce
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-tx8-max.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 flippy
+ */
+
+/dts-v1/;
+
+#include "meson-gxm-nexbox-a2.dts"
+
+/ {
+	compatible = "tanix,tx8", "amlogic,s912", "amlogic,meson-gxm";
+	model = "Tanix TX8 Max";
+
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "qcom,qca9377-bt";
+		enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max-x3-oc.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max-x3-oc.dts
new file mode 100644
index 000000000..e64d4895d
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max-x3-oc.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Author: flippy <flippy@sina.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-h96-max-x3.dts"
+
+/ {
+	model = "H96 Max X3 @ 2208Mhz";
+};
+
+&cpu_opp_table {
+	opp-2100000000 {
+		opp-hz = /bits/ 64 <2100000000>;
+		opp-microvolt = <1011000>;
+	};
+
+	opp-2208000000 {
+		opp-hz = /bits/ 64 <2208000000>;
+		opp-microvolt = <1021000>;
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max-x3.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max-x3.dts
new file mode 100644
index 000000000..a9d4a6f67
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max-x3.dts
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.
+ * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2021 flippy <uniqfreq@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-ac2xx.dtsi"
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+	compatible = "amlogic,sm1";
+	model = "H96 Max X3";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0xFFFFFFFF>;
+	};
+
+	sound {
+		compatible = "amlogic,axg-sound-card";
+		model = "H96-MAX";
+		audio-aux-devs = <&tdmout_b>;
+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",
+				"TDM_B Playback", "TDMOUT_B OUT";
+
+		clocks = <&clkc CLKID_MPLL2>,
+			 <&clkc CLKID_MPLL0>,
+			 <&clkc CLKID_MPLL1>;
+
+		assigned-clocks = <&clkc CLKID_MPLL2>,
+				  <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <294912000>,
+				       <270950400>,
+				       <393216000>;
+		status = "okay";
+
+		dai-link-0 {
+			sound-dai = <&frddr_a>;
+		};
+
+		dai-link-1 {
+			sound-dai = <&frddr_b>;
+		};
+
+		dai-link-2 {
+			sound-dai = <&frddr_c>;
+		};
+
+		/* 8ch hdmi interface */
+		dai-link-3 {
+			sound-dai = <&tdmif_b>;
+			dai-format = "i2s";
+			dai-tdm-slot-tx-mask-0 = <1 1>;
+			dai-tdm-slot-tx-mask-1 = <1 1>;
+			dai-tdm-slot-tx-mask-2 = <1 1>;
+			dai-tdm-slot-tx-mask-3 = <1 1>;
+			mclk-fs = <256>;
+
+			codec {
+				sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+			};
+		};
+
+		/* hdmi glue */
+		dai-link-4 {
+			sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+			codec {
+				sound-dai = <&hdmi_tx>;
+			};
+		};
+	};
+
+	vddgpu: regulator-vddgpu {
+		compatible = "regulator-fixed";
+		regulator-name = "mali";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <800000>;
+		vin-supply = <&ao_5v>;
+		regulator-always-on;
+	};
+};
+
+&vddcpu {
+	regulator-min-microvolt = <721000>;
+	regulator-max-microvolt = <1022000>;
+	pwms = <&pwm_AO_cd 1 1250 0>;
+};
+
+&arb {
+	status = "okay";
+};
+
+&clkc_audio {
+	status = "okay";
+};
+
+&ethmac {
+	status = "okay";
+
+	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
+	pinctrl-names = "default";
+	//phy-mode = "rgmii-txid";
+	phy-mode = "rgmii";
+	amlogic,tx-delay-ns = <2>;
+	phy-handle = <&external_phy>;
+
+	//rx-internal-delay-ps = <800>;
+
+	snps,aal;
+	snps,rxpbl = <0x8>;
+	snps,txpbl = <0x8>;
+
+	rx-fifo-depth = <4096>;
+	tx-fifo-depth = <4096>;
+
+	nvmem-cells = <&eth_mac>;
+	nvmem-cell-names = "eth_mac";
+};
+
+&ext_mdio {
+	external_phy: ethernet-phy@0 {
+		/* 
+		 * Realtek RTL8211F (0x001cc916) 
+		 * JLSemi JL2101 (0x937c4032)
+		 */
+		reg = <0>;
+		max-speed = <1000>;
+
+		reset-assert-us = <10000>;
+		reset-deassert-us = <80000>;
+		reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+		interrupt-parent = <&gpio_intc>;
+		/* MAC_INTR on GPIOZ_14 */
+		interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&frddr_a {
+	status = "okay";
+};
+
+&frddr_b {
+	status = "okay";
+};
+
+&frddr_c {
+	status = "okay";
+};
+
+&tdmif_b {
+	status = "okay";
+};
+
+&tdmout_b {
+	status = "okay";
+};
+
+&tohdmitx {
+	status = "okay";
+};
+
+&uart_A {
+	status = "okay";
+
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+	};
+};
+
+&mali {
+	mali-supply=<&vddgpu>;
+};
+
+&usb {
+	dr_mode = "host";
+};
+
+/* SDIO */
+&sd_emmc_a {
+	///delete-property/ sd-uhs-sdr104;
+        sd-uhs-sdr50;
+	max-frequency = <100000000>;
+
+        //sd-uhs-ddr50;
+	//max-frequency = <50000000>;
+
+	//sd-uhs-sdr104;
+	//max-frequency = <200000000>;
+};
+
+/* Begin: fix hcy6355 wifi module problem */
+&sdio_pins {
+	mux {
+		/delete-property/ bias-disable;
+		bias-pull-up;
+	};
+};
+/* End: fix hcy6355 wifi module problem */
+
+/* SD card */
+&sd_emmc_b {
+	max-frequency = <50000000>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+	max-frequency = <200000000>;
+};
+
+&cpu_opp_table {
+	opp-100000000 {
+		opp-hz = <0x00 100000000>;
+		opp-microvolt = <730000>;
+	};
+
+	opp-250000000 {
+		opp-hz = <0x00 250000000>;
+		opp-microvolt = <730000>;
+	};
+
+	opp-500000000 {
+		opp-hz = <0x00 500000000>;
+		opp-microvolt = <730000>;
+	};
+
+	opp-667000000 {
+		opp-hz = <0x00 667000000>;
+		opp-microvolt = <730000>;
+	};
+	
+	opp-2016000000 {
+		status = "disabled";
+	};
+	
+	opp-2100000000 {
+		status = "disabled";
+	};
+};
+
+&efuse {
+	eth_mac: eth_mac@0 {
+		reg = <0x0 0x06>;
+	};
+
+	bt_mac: bt_mac@6 {
+		reg = <0x6 0x06>;
+	};
+
+	wifi_mac: wifi_mac@12 {
+		reg = <0x0c 0x06>;
+	};
+
+	usid: usid@18 {
+		reg = <0x12 0x10>;
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-hk1box-vontar-x3-oc.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-hk1box-vontar-x3-oc.dts
new file mode 100644
index 000000000..50ab7732c
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-hk1box-vontar-x3-oc.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Author: flippy <flippy@sina.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-hk1box-vontar-x3.dts"
+
+/ {
+	model = "HK1 Box/Vontar X3 @ 2208Mhz";
+};
+
+&cpu_opp_table {
+	opp-2100000000 {
+		opp-hz = /bits/ 64 <2100000000>;
+		opp-microvolt = <1011000>;
+	};
+
+	opp-2208000000 {
+		opp-hz = /bits/ 64 <2208000000>;
+		opp-microvolt = <1021000>;
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-hk1box-vontar-x3.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-hk1box-vontar-x3.dts
new file mode 100644
index 000000000..f1e1bb38f
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-hk1box-vontar-x3.dts
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.
+ * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2021 flippy <uniqfreq@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-ac2xx.dtsi"
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+	compatible = "amlogic,sm1";
+	model = "HK1 Box/Vontar X3";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0xFFFFFFFF>;
+	};
+
+	sound {
+		compatible = "amlogic,axg-sound-card";
+		model = "HK1-BOX";
+		audio-aux-devs = <&tdmout_b>;
+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",
+				"TDM_B Playback", "TDMOUT_B OUT";
+
+		clocks = <&clkc CLKID_MPLL2>,
+			 <&clkc CLKID_MPLL0>,
+			 <&clkc CLKID_MPLL1>;
+
+		assigned-clocks = <&clkc CLKID_MPLL2>,
+				  <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <294912000>,
+				       <270950400>,
+				       <393216000>;
+		status = "okay";
+
+		dai-link-0 {
+			sound-dai = <&frddr_a>;
+		};
+
+		dai-link-1 {
+			sound-dai = <&frddr_b>;
+		};
+
+		dai-link-2 {
+			sound-dai = <&frddr_c>;
+		};
+
+		/* 8ch hdmi interface */
+		dai-link-3 {
+			sound-dai = <&tdmif_b>;
+			dai-format = "i2s";
+			dai-tdm-slot-tx-mask-0 = <1 1>;
+			dai-tdm-slot-tx-mask-1 = <1 1>;
+			dai-tdm-slot-tx-mask-2 = <1 1>;
+			dai-tdm-slot-tx-mask-3 = <1 1>;
+			mclk-fs = <256>;
+
+			codec {
+				sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+			};
+		};
+
+		/* hdmi glue */
+		dai-link-4 {
+			sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+			codec {
+				sound-dai = <&hdmi_tx>;
+			};
+		};
+	};
+
+	vddgpu: regulator-vddgpu {
+		compatible = "regulator-fixed";
+		regulator-name = "mali";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <800000>;
+		vin-supply = <&ao_5v>;
+		regulator-always-on;
+	};
+	
+	leds {
+		compatible = "gpio-leds";
+		status = "okay";
+		sys_led {
+			label = "sys_led";
+			gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+			linux,default-trigger = "default-on";
+		};
+	};
+};
+
+&vddcpu {
+	regulator-min-microvolt = <721000>;
+	regulator-max-microvolt = <1022000>;
+	pwms = <&pwm_AO_cd 1 1250 0>;
+};
+
+&arb {
+	status = "okay";
+};
+
+&clkc_audio {
+	status = "okay";
+};
+
+&ethmac {
+	status = "okay";
+
+	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&external_phy>;
+
+	//phy-mode = "rgmii-txid";
+	//rx-internal-delay-ps = <800>;
+	phy-mode = "rgmii";
+	amlogic,tx-delay-ns = <2>;
+
+	snps,aal;
+	snps,rxpbl = <0x8>;
+	snps,txpbl = <0x8>;
+
+	rx-fifo-depth = <4096>;
+	tx-fifo-depth = <4096>;
+
+	nvmem-cells = <&eth_mac>;
+	nvmem-cell-names = "eth_mac";
+};
+
+&ext_mdio {
+	external_phy: ethernet-phy@0 {
+		/* 
+		 * Realtek RTL8211F (0x001cc916) 
+		 * JLSemi JL2101 (0x937c4032)
+		 */
+		reg = <0>;
+		max-speed = <1000>;
+
+		reset-assert-us = <30000>;
+		reset-deassert-us = <80000>;
+		reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+		interrupt-parent = <&gpio_intc>;
+		/* MAC_INTR on GPIOZ_14 */
+		interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&frddr_a {
+	status = "okay";
+};
+
+&frddr_b {
+	status = "okay";
+};
+
+&frddr_c {
+	status = "okay";
+};
+
+&tdmif_b {
+	status = "okay";
+};
+
+&tdmout_b {
+	status = "okay";
+};
+
+&tohdmitx {
+	status = "okay";
+};
+
+&uart_A {
+	status = "okay";
+
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+	};
+};
+
+&mali {
+	mali-supply=<&vddgpu>;
+};
+
+&usb {
+	dr_mode = "host";
+};
+
+/* SDIO */
+&sd_emmc_a {
+	///delete-property/ sd-uhs-sdr104;
+	sd-uhs-sdr50;
+	max-frequency = <100000000>;
+
+        //sd-uhs-ddr50;
+	//max-frequency = <50000000>;
+
+	//sd-uhs-sdr104;
+	//max-frequency = <200000000>;
+};
+
+/* Begin: fix hcy6355 wifi module problem */
+&sdio_pins {
+	mux {
+		/delete-property/ bias-disable;
+		bias-pull-up;
+	};
+};
+/* End: fix hcy6355 wifi module problem */
+
+/* SD card */
+&sd_emmc_b {
+	cap-sd-highspeed;
+	max-frequency = <25000000>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+	max-frequency = <200000000>;
+};
+
+&cpu_opp_table {
+	opp-2016000000 {
+		opp-hz = /bits/ 64 <2016000000>;
+		opp-microvolt = <1000000>;
+	};
+};
+
+&efuse {
+	eth_mac: eth_mac@0 {
+		reg = <0x0 0x06>;
+	};
+
+	bt_mac: bt_mac@6 {
+		reg = <0x6 0x06>;
+	};
+
+	wifi_mac: wifi_mac@12 {
+		reg = <0x0c 0x06>;
+	};
+
+	usid: usid@18 {
+		reg = <0x12 0x10>;
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-skyworth-lb2004-a4091.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-skyworth-lb2004-a4091.dts
new file mode 100644
index 000000000..92e659dac
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-skyworth-lb2004-a4091.dts
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.
+ * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2021 flippy <uniqfreq@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-ac2xx.dtsi"
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+	compatible = "skyworth,lb2004", "amlogic,s905x3", "amlogic,sm1";
+	model = "SKYWORTH LB2004-A4091";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0xFFFFFFFF>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		/* Mainline u-boot lacks TCA6507 driver. Currently only using bootloader, TCA6507 LEDs works. */
+		gpio_led {
+			label = "gpio_led";
+			gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "default-on";
+		};
+	};
+
+	sound {
+		compatible = "amlogic,axg-sound-card";
+		model = "LB2004-A4091";
+		audio-aux-devs = <&tdmout_b>;
+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",
+				"TDM_B Playback", "TDMOUT_B OUT";
+
+		clocks = <&clkc CLKID_MPLL2>,
+			 <&clkc CLKID_MPLL0>,
+			 <&clkc CLKID_MPLL1>;
+
+		assigned-clocks = <&clkc CLKID_MPLL2>,
+				  <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <294912000>,
+				       <270950400>,
+				       <393216000>;
+		status = "okay";
+
+		dai-link-0 {
+			sound-dai = <&frddr_a>;
+		};
+
+		dai-link-1 {
+			sound-dai = <&frddr_b>;
+		};
+
+		dai-link-2 {
+			sound-dai = <&frddr_c>;
+		};
+
+		/* 8ch hdmi interface */
+		dai-link-3 {
+			sound-dai = <&tdmif_b>;
+			dai-format = "i2s";
+			dai-tdm-slot-tx-mask-0 = <1 1>;
+			dai-tdm-slot-tx-mask-1 = <1 1>;
+			dai-tdm-slot-tx-mask-2 = <1 1>;
+			dai-tdm-slot-tx-mask-3 = <1 1>;
+			mclk-fs = <256>;
+
+			codec {
+				sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+			};
+		};
+
+		/* hdmi glue */
+		dai-link-4 {
+			sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+			codec {
+				sound-dai = <&hdmi_tx>;
+			};
+		};
+	};
+
+	vddgpu: regulator-vddgpu {
+		compatible = "regulator-fixed";
+		regulator-name = "mali";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <800000>;
+		vin-supply = <&ao_5v>;
+		regulator-always-on;
+	};
+};
+
+&i2c3 {
+	status = "okay";
+
+	/* Mainline u-boot lacks TCA6507 driver. Currently only using bootloader, TCA6507 LEDs works. */
+	tca6507@45 {
+		compatible = "ti,tca6507", "leds,tca6507";
+		reg = <0x45>;
+		status = "okay";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		led@red {
+			reg = <0x00>;
+			linux,default-trigger = "heartbeat";
+		};
+
+		led@green {
+			reg = <0x01>;
+			linux,default-trigger = "heartbeat";
+		};
+
+		led@blue {
+			reg = <0x02>;
+			linux,default-trigger = "none";
+		};
+	};
+};
+
+&vddcpu {
+	regulator-min-microvolt = <721000>;
+	regulator-max-microvolt = <1022000>;
+	pwms = <&pwm_AO_cd 1 1250 0>;
+};
+
+&arb {
+	status = "okay";
+};
+
+&clkc_audio {
+	status = "okay";
+};
+
+&ethmac {
+	status = "okay";
+
+	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&external_phy>;
+
+	phy-mode = "rgmii";
+	amlogic,tx-delay-ns = <2>;
+
+	snps,aal;
+	snps,rxpbl = <0x8>;
+	snps,txpbl = <0x8>;
+
+	rx-fifo-depth = <4096>;
+	tx-fifo-depth = <4096>;
+
+	nvmem-cells = <&eth_mac>;
+	nvmem-cell-names = "eth_mac";
+};
+
+&ext_mdio {
+	external_phy: ethernet-phy@0 {
+		/* 
+		 * Realtek RTL8211F (0x001cc916) 
+		 * JLSemi JL2101 (0x937c4032)
+		 */
+		reg = <0>;
+		max-speed = <1000>;
+
+		reset-assert-us = <30000>;
+		reset-deassert-us = <80000>;
+		reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+		interrupt-parent = <&gpio_intc>;
+		/* MAC_INTR on GPIOZ_14 */
+		interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&frddr_a {
+	status = "okay";
+};
+
+&frddr_b {
+	status = "okay";
+};
+
+&frddr_c {
+	status = "okay";
+};
+
+&ir {
+	status = "disabled";
+};
+
+&tdmif_b {
+	status = "okay";
+};
+
+&tdmout_b {
+	status = "okay";
+};
+
+&tohdmitx {
+	status = "okay";
+};
+
+&uart_A {
+	status = "disabled";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth: bluetooth {
+		compatible = "realtek,rtl8822cs-bt";
+		interrupt-parent = <&gpio_intc>;
+		interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "host-wakeup";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+		vbat-supply = <&vddao_3v3>;
+		vddio-supply = <&vddio_ao1v8>;
+		status = "disabled";
+	};
+};
+
+&mali {
+	mali-supply=<&vddgpu>;
+};
+
+&usb {
+	dr_mode = "host";
+};
+
+/* SDIO */
+&sd_emmc_a {
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-ddr50;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	max-frequency = <208000000>;
+};
+
+/* SD card */
+&sd_emmc_b {
+	status = "disabled";
+};
+
+/* eMMC */
+&sd_emmc_c {
+	mmc-sdr-1_8v;
+	max-frequency = <200000000>;
+};
+
+&cpu_opp_table {
+	opp-2016000000 {
+		opp-hz = /bits/ 64 <2016000000>;
+		opp-microvolt = <1000000>;
+	};
+};
+
+&efuse {
+	eth_mac: eth_mac@0 {
+		reg = <0x0 0x06>;
+	};
+
+	bt_mac: bt_mac@6 {
+		reg = <0x6 0x06>;
+	};
+
+	wifi_mac: wifi_mac@12 {
+		reg = <0x0c 0x06>;
+	};
+
+	usid: usid@18 {
+		reg = <0x12 0x10>;
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-tx3-bz-oc.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-tx3-bz-oc.dts
new file mode 100644
index 000000000..542fbd9e9
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-tx3-bz-oc.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Author: flippy <flippy@sina.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-tx3-bz.dts"
+
+/ {
+	model = "Tanix TX3 (BZ) @ 2208Mhz";
+};
+
+&cpu_opp_table {
+
+	opp-2208000000 {
+		opp-hz = /bits/ 64 <2208000000>;
+		opp-microvolt = <1021000>;
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-tx3-bz.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-tx3-bz.dts
new file mode 100644
index 000000000..a8c12c9b6
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-tx3-bz.dts
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.
+ * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2022 flippy <uniqfreq@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-ac2xx.dtsi"
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+	compatible = "tanix,tx3-bz", "amlogic,sm1";
+	model = "Tanix TX3 (BZ)";
+
+	leds {
+		compatible = "gpio-leds";
+		
+		sys_led {
+			led_name = "sys_led";
+                        gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	sound {
+		compatible = "amlogic,axg-sound-card";
+		model = "TX3";
+		audio-aux-devs = <&tdmout_b>;
+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",
+				"TDM_B Playback", "TDMOUT_B OUT";
+
+		clocks = <&clkc CLKID_MPLL2>,
+			 <&clkc CLKID_MPLL0>,
+			 <&clkc CLKID_MPLL1>;
+
+		assigned-clocks = <&clkc CLKID_MPLL2>,
+				  <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <294912000>,
+				       <270950400>,
+				       <393216000>;
+		status = "okay";
+
+		dai-link-0 {
+			sound-dai = <&frddr_a>;
+		};
+
+		dai-link-1 {
+			sound-dai = <&frddr_b>;
+		};
+
+		dai-link-2 {
+			sound-dai = <&frddr_c>;
+		};
+
+		/* 8ch hdmi interface */
+		dai-link-3 {
+			sound-dai = <&tdmif_b>;
+			dai-format = "i2s";
+			dai-tdm-slot-tx-mask-0 = <1 1>;
+			dai-tdm-slot-tx-mask-1 = <1 1>;
+			dai-tdm-slot-tx-mask-2 = <1 1>;
+			dai-tdm-slot-tx-mask-3 = <1 1>;
+			mclk-fs = <256>;
+
+			codec {
+				sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+			};
+		};
+
+		/* hdmi glue */
+		dai-link-4 {
+			sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+			codec {
+				sound-dai = <&hdmi_tx>;
+			};
+		};
+	};
+
+	vddgpu: regulator-vddgpu {
+		compatible = "regulator-fixed";
+		regulator-name = "mali";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <800000>;
+		vin-supply = <&ao_5v>;
+		regulator-always-on;
+	};
+};
+
+&vddcpu {
+	regulator-min-microvolt = <721000>;
+	regulator-max-microvolt = <1022000>;
+	pwms = <&pwm_AO_cd 1 1250 0>;
+};
+
+&arb {
+	status = "okay";
+};
+
+&clkc_audio {
+	status = "okay";
+};
+
+&ethmac {
+	status = "okay";
+	phy-mode = "rmii";
+	phy-handle = <&internal_ephy>;
+
+	nvmem-cells = <&eth_mac>;
+	nvmem-cell-names = "eth_mac";
+};
+
+&frddr_a {
+	status = "okay";
+};
+
+&frddr_b {
+	status = "okay";
+};
+
+&frddr_c {
+	status = "okay";
+};
+
+&tdmif_b {
+	status = "okay";
+};
+
+&tdmout_b {
+	status = "okay";
+};
+
+&tohdmitx {
+	status = "okay";
+};
+
+&uart_A {
+	status = "okay";
+
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+	};
+};
+
+&mali {
+	mali-supply=<&vddgpu>;
+};
+
+&usb {
+	dr_mode = "host";
+};
+
+/* SDIO */
+&sd_emmc_a {
+	/delete-property/ sd-uhs-sdr104;
+	sd-uhs-sdr50;
+	max-frequency = <100000000>;
+
+        //sd-uhs-ddr50;
+	//max-frequency = <50000000>;
+
+	//sd-uhs-sdr104;
+	//max-frequency = <200000000>;
+};
+
+/* SD card */
+&sd_emmc_b {
+	max-frequency = <50000000>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+	max-frequency = <200000000>;
+};
+
+&cpu_opp_table {
+	opp-2016000000 {
+		opp-hz = /bits/ 64 <2016000000>;
+		opp-microvolt = <1000000>;
+	};
+
+	opp-2100000000 {
+		opp-hz = /bits/ 64 <2100000000>;
+		opp-microvolt = <1011000>;
+	};
+};
+
+&efuse {
+	eth_mac: eth_mac@0 {
+		reg = <0x0 0x06>;
+	};
+
+	bt_mac: bt_mac@6 {
+		reg = <0x6 0x06>;
+	};
+
+	wifi_mac: wifi_mac@12 {
+		reg = <0x0c 0x06>;
+	};
+
+	usid: usid@18 {
+		reg = <0x12 0x10>;
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-tx3-qz-oc.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-tx3-qz-oc.dts
new file mode 100644
index 000000000..f7d05636e
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-tx3-qz-oc.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Author: flippy <flippy@sina.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-tx3-qz.dts"
+
+/ {
+	model = "Tanix TX3 (QZ) @ 2208Mhz";
+};
+
+&cpu_opp_table {
+
+	opp-2208000000 {
+		opp-hz = /bits/ 64 <2208000000>;
+		opp-microvolt = <1021000>;
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-tx3-qz.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-tx3-qz.dts
new file mode 100644
index 000000000..41969e0ce
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-tx3-qz.dts
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.
+ * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2022 flippy <uniqfreq@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-ac2xx.dtsi"
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+	compatible = "tanix,tx3-qz", "amlogic,sm1";
+	model = "Tanix TX3 (QZ)";
+
+	leds {
+		compatible = "gpio-leds";
+		
+		sys_led {
+			led_name = "sys_led";
+                        gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0xFFFFFFFF>;
+	};
+
+	sound {
+		compatible = "amlogic,axg-sound-card";
+		model = "TX3";
+		audio-aux-devs = <&tdmout_b>;
+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",
+				"TDM_B Playback", "TDMOUT_B OUT";
+
+		clocks = <&clkc CLKID_MPLL2>,
+			 <&clkc CLKID_MPLL0>,
+			 <&clkc CLKID_MPLL1>;
+
+		assigned-clocks = <&clkc CLKID_MPLL2>,
+				  <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <294912000>,
+				       <270950400>,
+				       <393216000>;
+		status = "okay";
+
+		dai-link-0 {
+			sound-dai = <&frddr_a>;
+		};
+
+		dai-link-1 {
+			sound-dai = <&frddr_b>;
+		};
+
+		dai-link-2 {
+			sound-dai = <&frddr_c>;
+		};
+
+		/* 8ch hdmi interface */
+		dai-link-3 {
+			sound-dai = <&tdmif_b>;
+			dai-format = "i2s";
+			dai-tdm-slot-tx-mask-0 = <1 1>;
+			dai-tdm-slot-tx-mask-1 = <1 1>;
+			dai-tdm-slot-tx-mask-2 = <1 1>;
+			dai-tdm-slot-tx-mask-3 = <1 1>;
+			mclk-fs = <256>;
+
+			codec {
+				sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+			};
+		};
+
+		/* hdmi glue */
+		dai-link-4 {
+			sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+			codec {
+				sound-dai = <&hdmi_tx>;
+			};
+		};
+	};
+
+	vddgpu: regulator-vddgpu {
+		compatible = "regulator-fixed";
+		regulator-name = "mali";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <800000>;
+		vin-supply = <&ao_5v>;
+		regulator-always-on;
+	};
+};
+
+&vddcpu {
+	regulator-min-microvolt = <721000>;
+	regulator-max-microvolt = <1022000>;
+	pwms = <&pwm_AO_cd 1 1250 0>;
+};
+
+&arb {
+	status = "okay";
+};
+
+&clkc_audio {
+	status = "okay";
+};
+
+&ethmac {
+	status = "okay";
+
+	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
+	pinctrl-names = "default";
+	phy-mode = "rgmii-txid";
+	phy-handle = <&external_phy>;
+
+	rx-internal-delay-ps = <800>;
+
+	snps,aal;
+	snps,rxpbl = <0x8>;
+	snps,txpbl = <0x8>;
+
+	rx-fifo-depth = <4096>;
+	tx-fifo-depth = <4096>;
+
+	nvmem-cells = <&eth_mac>;
+	nvmem-cell-names = "eth_mac";
+};
+
+&ext_mdio {
+	external_phy: ethernet-phy@0 {
+		/* Realtek RTL8211F (0x001cc916) */
+		reg = <0>;
+		max-speed = <1000>;
+
+		reset-assert-us = <10000>;
+		reset-deassert-us = <80000>;
+		reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+		interrupt-parent = <&gpio_intc>;
+		/* MAC_INTR on GPIOZ_14 */
+		interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&frddr_a {
+	status = "okay";
+};
+
+&frddr_b {
+	status = "okay";
+};
+
+&frddr_c {
+	status = "okay";
+};
+
+&tdmif_b {
+	status = "okay";
+};
+
+&tdmout_b {
+	status = "okay";
+};
+
+&tohdmitx {
+	status = "okay";
+};
+
+&uart_A {
+	status = "okay";
+
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+	};
+};
+
+&mali {
+	mali-supply=<&vddgpu>;
+};
+
+&usb {
+	dr_mode = "host";
+};
+
+/* SDIO */
+&sd_emmc_a {
+	/delete-property/ sd-uhs-sdr104;
+	sd-uhs-sdr50;
+	max-frequency = <100000000>;
+
+        //sd-uhs-ddr50;
+	//max-frequency = <50000000>;
+
+	//sd-uhs-sdr104;
+	//max-frequency = <200000000>;
+};
+
+/* SD card */
+&sd_emmc_b {
+	max-frequency = <50000000>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+	max-frequency = <200000000>;
+};
+
+&cpu_opp_table {
+	opp-2016000000 {
+		opp-hz = /bits/ 64 <2016000000>;
+		opp-microvolt = <1000000>;
+	};
+
+	opp-2100000000 {
+		opp-hz = /bits/ 64 <2100000000>;
+		opp-microvolt = <1011000>;
+	};
+};
+
+&efuse {
+	eth_mac: eth_mac@0 {
+		reg = <0x0 0x06>;
+	};
+
+	bt_mac: bt_mac@6 {
+		reg = <0x6 0x06>;
+	};
+
+	wifi_mac: wifi_mac@12 {
+		reg = <0x0c 0x06>;
+	};
+
+	usid: usid@18 {
+		reg = <0x12 0x10>;
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x88-pro-x3.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x88-pro-x3.dts
new file mode 100644
index 000000000..97ed73c47
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x88-pro-x3.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 AI-Speaker.com. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-ac2xx.dtsi"
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+	compatible = "ai-speaker.com,dev3\0amlogic,sm1";
+	model = "AIS DEV3 / X88 Pro Pro X3 / X99 Max Plus / Transpeed X3 Plus";
+
+	fd655_dev {
+		dat_pin = <0x18 0x40 0x00>;
+		dev_name = "fd655_dev";
+		status = "okay";
+		clk_pin = <0x18 0x41 0x00>;
+		compatible = "amlogic,fd655_dev";
+	};
+
+	openvfd {
+		compatible = "open,vfd";
+		dev_name = "openvfd";
+		status = "okay";
+	};
+};
+
+
+&ethmac {
+	status = "okay";
+	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&external_phy>;
+	phy-mode = "rgmii";
+	amlogic,tx-delay-ns = <2>;
+	snps,aal;
+	snps,rxpbl = <0x8>;
+	snps,txpbl = <0x8>;
+	rx-fifo-depth = <4096>;
+	tx-fifo-depth = <4096>;
+	nvmem-cells = <&eth_mac>;
+	nvmem-cell-names = "eth_mac";
+};
+
+&ext_mdio {
+	external_phy: ethernet-phy@0 {
+		/* Realtek RTL8211F */
+		reg = <0>;
+		max-speed = <1000>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <80000>;
+		reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+		interrupt-parent = <&gpio_intc>;
+		/* MAC_INTR on GPIOZ_14 */
+		interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&efuse {
+	eth_mac: eth_mac@0 {
+		reg = <0x0 0x06>;
+	};
+
+	bt_mac: bt_mac@6 {
+		reg = <0x6 0x06>;
+	};
+
+	wifi_mac: wifi_mac@12 {
+		reg = <0x0c 0x06>;
+	};
+
+	usid: usid@18 {
+		reg = <0x12 0x10>;
+	};
+};
+
+// set max cpu speed
+&cpu_opp_table {
+
+	opp-2016000000 {
+		status = "disabled";
+	};
+
+	opp-2100000000 {
+		status = "disabled";
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-100m.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-100m.dts
new file mode 100644
index 000000000..6c8fada1a
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-100m.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: flippy <flippy@sina.com>
+ */
+/dts-v1/;
+
+#include "meson-sm1-x96-max-plus.dts"
+
+/ {
+	model = "AMedia X96 Max+ (eth0 speed:100Mb/s)";
+};
+
+&external_phy  {
+	max-speed = <100>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-2101.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-2101.dts
new file mode 100644
index 000000000..866d7ff7a
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-2101.dts
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.
+ * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2021 flippy <uniqfreq@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-ac2xx.dtsi"
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+	//compatible = "amediatech,x96-max-plus", "amlogic,sm1";
+	//model = "Shenzhen Amediatech Technology Co., Ltd X96 Max+";
+	compatible = "amlogic,sm1";
+	model = "AMedia X96 Max+";
+
+	aliases {
+		serial0 = &uart_AO;
+                serial1 = &uart_A;
+		ethernet0 = &ethmac;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0xFFFFFFFF>;
+	};
+
+	sound {
+		compatible = "amlogic,axg-sound-card";
+		model = "X96-MAX";
+		audio-aux-devs = <&tdmout_b>;
+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",
+				"TDM_B Playback", "TDMOUT_B OUT";
+
+		assigned-clocks = <&clkc CLKID_MPLL2>,
+				  <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <294912000>,
+				       <270950400>,
+				       <393216000>;
+		status = "okay";
+
+		dai-link-0 {
+			sound-dai = <&frddr_a>;
+		};
+
+		dai-link-1 {
+			sound-dai = <&frddr_b>;
+		};
+
+		dai-link-2 {
+			sound-dai = <&frddr_c>;
+		};
+
+		/* 8ch hdmi interface */
+		dai-link-3 {
+			sound-dai = <&tdmif_b>;
+			dai-format = "i2s";
+			dai-tdm-slot-tx-mask-0 = <1 1>;
+			dai-tdm-slot-tx-mask-1 = <1 1>;
+			dai-tdm-slot-tx-mask-2 = <1 1>;
+			dai-tdm-slot-tx-mask-3 = <1 1>;
+			mclk-fs = <256>;
+
+			codec {
+				sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+			};
+		};
+
+		/* hdmi glue */
+		dai-link-4 {
+			sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+			codec {
+				sound-dai = <&hdmi_tx>;
+			};
+		};
+	};
+
+	vddgpu: regulator-vddgpu {
+		compatible = "regulator-fixed";
+		regulator-name = "mali";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <800000>;
+		vin-supply = <&ao_5v>;
+		regulator-always-on;
+	};
+};
+
+&vddcpu {
+	regulator-min-microvolt = <721000>;
+	regulator-max-microvolt = <1022000>;
+	pwms = <&pwm_AO_cd 1 1250 0>;
+};
+
+&arb {
+	status = "okay";
+};
+
+&clkc_audio {
+	status = "okay";
+};
+
+&ethmac {
+	status = "okay";
+
+	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&external_phy>;
+
+	//phy-mode = "rgmii-txid";
+	//rx-internal-delay-ps = <800>;
+	phy-mode = "rgmii";
+	amlogic,tx-delay-ns = <2>;
+
+	snps,aal;
+	snps,rxpbl = <0x8>;
+	snps,txpbl = <0x8>;
+
+	rx-fifo-depth = <4096>;
+	tx-fifo-depth = <4096>;
+
+	nvmem-cells = <&eth_mac>;
+	nvmem-cell-names = "eth_mac";
+};
+
+&ext_mdio {
+	external_phy: ethernet-phy@0 {
+		/* 
+		 * Realtek RTL8211F (0x001cc916) 
+		 * JLSemi JL2101 (0x937c4032)
+		 */
+		reg = <0>;
+		max-speed = <1000>;
+
+		reset-assert-us = <30000>;
+		reset-deassert-us = <80000>;
+		reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+		interrupt-parent = <&gpio_intc>;
+		/* MAC_INTR on GPIOZ_14 */
+		interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&frddr_a {
+	status = "okay";
+};
+
+&frddr_b {
+	status = "okay";
+};
+
+&frddr_c {
+	status = "okay";
+};
+
+&ir {
+	linux,rc-map-name = "rc-x96max";
+};
+
+&tdmif_b {
+	status = "okay";
+};
+
+&tdmout_b {
+	status = "okay";
+};
+
+&tohdmitx {
+	status = "okay";
+};
+
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth: bluetooth {
+                compatible = "realtek,rtl8822cs-bt";
+		enable-gpios  = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
+		device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&mali {
+	mali-supply=<&vddgpu>;
+};
+
+&usb {
+	dr_mode = "host";
+};
+
+/* SDIO */
+&sd_emmc_a {
+	/delete-property/ sd-uhs-sdr104;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	max-frequency = <50000000>;
+
+        //sd-uhs-ddr50;
+	//max-frequency = <50000000>;
+
+	//sd-uhs-sdr104;
+	//max-frequency = <200000000>;
+
+	rtl8822cs: wifi@1 {
+		reg = <1>;
+	};
+};
+
+/* SD card */
+&sd_emmc_b {
+	cap-sd-highspeed;
+	max-frequency = <25000000>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+	max-frequency = <200000000>;
+};
+
+&cpu_opp_table {
+	opp-2016000000 {
+		opp-hz = /bits/ 64 <2016000000>;
+		opp-microvolt = <1000000>;
+	};
+};
+
+&efuse {
+	eth_mac: eth_mac@0 {
+		reg = <0x0 0x06>;
+	};
+
+	bt_mac: bt_mac@6 {
+		reg = <0x6 0x6>;
+	};
+
+	wifi_mac: wifi_mac@c {
+		reg = <0xc 0x6>;
+	};
+
+	usid: usid@18 {
+		reg = <0x12 0x10>;
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-a100.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-a100.dts
new file mode 100644
index 000000000..fe217335c
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-a100.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 taras-filatov, unifreq.
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-sei610.dts"
+
+/ {
+	compatible = "x96-max-a100", "amlogic,sm1";
+	model = "X96 MAX+ A100";
+
+	/delete-node/ memory@0;
+
+	memory@0 {
+		device_type = "memory";
+		// reg = <0x0 0x0 0x0 0x40000000>;
+		linux,usable-memory = <0x0 0x100000 0x0 0xf0800000>;
+	};
+};
\ No newline at end of file
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-ip1001m-2.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-ip1001m-2.dts
new file mode 100644
index 000000000..1c8010a8f
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-ip1001m-2.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.
+ * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2022 flippy <uniqfreq@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-x96-max-plus-oc.dts"
+
+&ethmac {
+	phy-mode = "rgmii-txid";
+	/* After a simple testing, temporarily set rx-internal-delay-ps to 2800 ps, 
+	 * if anyone finds a more suitable value please let me know.
+	 */
+	rx-internal-delay-ps = <2800>;
+};
+
+&ext_mdio {
+	/delete-node/ ethernet-phy@0;
+
+	external_phy: ethernet-phy@1 {
+		/* ICPlus IP1001M: 0x02430d91 */
+		reg = <1>;
+		max-speed = <1000>;
+
+		reset-assert-us = <10000>;
+		reset-deassert-us = <80000>;
+		reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+		interrupt-parent = <&gpio_intc>;
+		/* MAC_INTR on GPIOZ_14 */
+		interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&bluetooth {
+	/* AM7256 module is based on broadcom brcm4354-sdio, 
+	 * so maybe bluetooth is available.
+	 */
+	compatible = "brcm,bcm43438-bt";
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-ip1001m.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-ip1001m.dts
new file mode 100644
index 000000000..1dd885b40
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-ip1001m.dts
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.
+ * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2022 flippy <uniqfreq@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-x96-max-plus-oc.dts"
+
+&ethmac {
+	phy-mode = "rgmii-txid";
+	/* After a simple testing, temporarily set rx-internal-delay-ps to 2800 ps, 
+	 * if anyone finds a more suitable value please let me know.
+	 */
+	rx-internal-delay-ps = <2800>;
+};
+
+&ext_mdio {
+	/delete-node/ ethernet-phy@0;
+
+	external_phy: ethernet-phy@3 {
+		/* ICPlus IP1001M: 0x02430d91 */
+		reg = <3>;
+		max-speed = <1000>;
+
+		reset-assert-us = <10000>;
+		reset-deassert-us = <80000>;
+		reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+		interrupt-parent = <&gpio_intc>;
+		/* MAC_INTR on GPIOZ_14 */
+		interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&bluetooth {
+	/* AM7256 module is based on broadcom brcm4354-sdio, 
+	 * so maybe bluetooth is available.
+	 */
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-oc.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-oc.dts
new file mode 100644
index 000000000..4789734eb
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-oc.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Author: flippy <flippy@sina.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-x96-max-plus.dts"
+
+/ {
+	model = "AMedia X96 Max+ @ 2208Mhz";
+};
+
+&cpu_opp_table {
+	opp-2100000000 {
+		opp-hz = /bits/ 64 <2100000000>;
+		opp-microvolt = <1011000>;
+	};
+
+	opp-2208000000 {
+		opp-hz = /bits/ 64 <2208000000>;
+		opp-microvolt = <1021000>;
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-q1.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-q1.dts
new file mode 100644
index 000000000..0d2d61b26
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-q1.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.
+ * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2022 Flippy
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-x96-air.dts"
+
+/ {
+	compatible = "amediatech,x96-max", "amlogic,sm1";
+	model = "X96 Max Plus Q1";
+
+	aliases {
+		serial0 = &uart_AO;
+		ethernet0 = &ethmac;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0xf0800000>;
+	};
+};
+
+&uart_AO {
+	status = "okay";
+	pinctrl-0 = <&uart_ao_a_pins>;
+	pinctrl-names = "default";
+};
+
+&ethmac {
+	status = "okay";
+	phy-handle = <&internal_ephy>;
+	phy-mode = "rmii";
+};
+
+&internal_ephy  {
+	max-speed = <100>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-q2.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-q2.dts
new file mode 100644
index 000000000..9f974bd8d
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus-q2.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 danboid, flippy
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-h96-max.dts"
+
+/ {
+	compatible = "x96-max-plus-q2,x96-air-q1000", "amlogic,sm1";
+	model = "X96 MAX PLUS Q2, X96 Air Q1000";
+
+};
+
+&uart_A {
+	bluetooth {
+		compatible = "qcom,qca9377-bt";
+		enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+	};
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus.dts
new file mode 100644
index 000000000..4d9f3f658
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-max-plus.dts
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre SAS. All rights reserved.
+ * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2021 flippy <uniqfreq@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-ac2xx.dtsi"
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+	//compatible = "amediatech,x96-max-plus", "amlogic,sm1";
+	//model = "Shenzhen Amediatech Technology Co., Ltd X96 Max+";
+	compatible = "amlogic,sm1";
+	model = "AMedia X96 Max+";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0xFFFFFFFF>;
+	};
+
+	sound {
+		compatible = "amlogic,axg-sound-card";
+		model = "X96-MAX";
+		audio-aux-devs = <&tdmout_b>;
+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",
+				"TDM_B Playback", "TDMOUT_B OUT";
+
+		clocks = <&clkc CLKID_MPLL2>,
+			 <&clkc CLKID_MPLL0>,
+			 <&clkc CLKID_MPLL1>;
+
+		assigned-clocks = <&clkc CLKID_MPLL2>,
+				  <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <294912000>,
+				       <270950400>,
+				       <393216000>;
+		status = "okay";
+
+		dai-link-0 {
+			sound-dai = <&frddr_a>;
+		};
+
+		dai-link-1 {
+			sound-dai = <&frddr_b>;
+		};
+
+		dai-link-2 {
+			sound-dai = <&frddr_c>;
+		};
+
+		/* 8ch hdmi interface */
+		dai-link-3 {
+			sound-dai = <&tdmif_b>;
+			dai-format = "i2s";
+			dai-tdm-slot-tx-mask-0 = <1 1>;
+			dai-tdm-slot-tx-mask-1 = <1 1>;
+			dai-tdm-slot-tx-mask-2 = <1 1>;
+			dai-tdm-slot-tx-mask-3 = <1 1>;
+			mclk-fs = <256>;
+
+			codec {
+				sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+			};
+		};
+
+		/* hdmi glue */
+		dai-link-4 {
+			sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+			codec {
+				sound-dai = <&hdmi_tx>;
+			};
+		};
+	};
+
+	vddgpu: regulator-vddgpu {
+		compatible = "regulator-fixed";
+		regulator-name = "mali";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <800000>;
+		vin-supply = <&ao_5v>;
+		regulator-always-on;
+	};
+};
+
+&vddcpu {
+	regulator-min-microvolt = <721000>;
+	regulator-max-microvolt = <1022000>;
+	pwms = <&pwm_AO_cd 1 1250 0>;
+};
+
+&arb {
+	status = "okay";
+};
+
+&clkc_audio {
+	status = "okay";
+};
+
+&ethmac {
+	status = "okay";
+
+	pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&external_phy>;
+
+	//phy-mode = "rgmii-txid";
+	//rx-internal-delay-ps = <800>;
+	phy-mode = "rgmii";
+	amlogic,tx-delay-ns = <2>;
+
+	snps,aal;
+	snps,rxpbl = <0x8>;
+	snps,txpbl = <0x8>;
+
+	rx-fifo-depth = <4096>;
+	tx-fifo-depth = <4096>;
+
+	nvmem-cells = <&eth_mac>;
+	nvmem-cell-names = "eth_mac";
+};
+
+&ext_mdio {
+	external_phy: ethernet-phy@0 {
+		/* 
+		 * Realtek RTL8211F (0x001cc916) 
+		 * JLSemi JL2101 (0x937c4032)
+		 */
+		reg = <0>;
+		max-speed = <1000>;
+
+		reset-assert-us = <30000>;
+		reset-deassert-us = <80000>;
+		reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+		interrupt-parent = <&gpio_intc>;
+		/* MAC_INTR on GPIOZ_14 */
+		interrupts = <IRQID_GPIOZ_14 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&frddr_a {
+	status = "okay";
+};
+
+&frddr_b {
+	status = "okay";
+};
+
+&frddr_c {
+	status = "okay";
+};
+
+&ir {
+	linux,rc-map-name = "rc-x96max";
+};
+
+&tdmif_b {
+	status = "okay";
+};
+
+&tdmout_b {
+	status = "okay";
+};
+
+&tohdmitx {
+	status = "okay";
+};
+
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth: bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		interrupt-parent = <&gpio_intc>;
+		interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "host-wakeup";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+		vbat-supply = <&vddao_3v3>;
+		vddio-supply = <&vddio_ao1v8>;
+		status = "disabled";
+	};
+};
+
+&mali {
+	mali-supply=<&vddgpu>;
+};
+
+&usb {
+	dr_mode = "host";
+};
+
+/* SDIO */
+&sd_emmc_a {
+	/delete-property/ sd-uhs-sdr104;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	max-frequency = <100000000>;
+
+        //sd-uhs-ddr50;
+	//max-frequency = <50000000>;
+
+	//sd-uhs-sdr104;
+	//max-frequency = <200000000>;
+};
+
+/* SD card */
+&sd_emmc_b {
+	cap-sd-highspeed;
+	max-frequency = <25000000>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+	max-frequency = <200000000>;
+};
+
+&cpu_opp_table {
+	opp-2016000000 {
+		opp-hz = /bits/ 64 <2016000000>;
+		opp-microvolt = <1000000>;
+	};
+};
+
+&efuse {
+	eth_mac: eth_mac@0 {
+		reg = <0x0 0x06>;
+	};
+
+	bt_mac: bt_mac@6 {
+		reg = <0x6 0x06>;
+	};
+
+	wifi_mac: wifi_mac@12 {
+		reg = <0x0c 0x06>;
+	};
+
+	usid: usid@18 {
+		reg = <0x12 0x10>;
+	};
+};


================================================
FILE: kernel-patch/beta/deprecated-patches/6.18.y-304-dts-add-rk3328-rk3399-series-devices.patch
================================================
From e67a875afab25485ee2b61d2a118c1830e6d4003 Mon Sep 17 00:00:00 2001
From: ophub <68696949+ophub@users.noreply.github.com>
Date: Sat, 31 Jan 2026 18:15:08 +0800
Subject: [PATCH] arch: arm64: dts: rockchip: add rk3328, rk3399 Series devices

---
 arch/arm64/boot/dts/rockchip/Makefile         |   20 +
 .../boot/dts/rockchip/rk3328-nanopi-neo3.dts  |  394 +++++
 .../boot/dts/rockchip/rk3399-aio-3399b.dts    | 1122 +++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3399-am40.dts  |  792 +++++++++++
 .../boot/dts/rockchip/rk3399-bozz-sw799.dts   |  505 +++++++
 .../arm64/boot/dts/rockchip/rk3399-dg3399.dts | 1009 +++++++++++++
 .../boot/dts/rockchip/rk3399-dlfr100.dts      |  732 ++++++++++
 .../boot/dts/rockchip/rk3399-fmx1-pro-b.dts   |  764 ++++++++++
 .../boot/dts/rockchip/rk3399-fmx1-pro.dts     |  931 ++++++++++++
 .../boot/dts/rockchip/rk3399-hugsun-zm.dts    |    9 +
 .../boot/dts/rockchip/rk3399-king3399.dts     | 1079 ++++++++++++++
 .../boot/dts/rockchip/rk3399-sv-33a6x.dts     |  777 ++++++++++
 arch/arm64/boot/dts/rockchip/rk3399-taram.dts | 1261 +++++++++++++++++
 .../boot/dts/rockchip/rk3399-tb-ls3399.dts    |  659 +++++++++
 .../boot/dts/rockchip/rk3399-tn3399-v3.dts    |  888 ++++++++++++
 .../arm64/boot/dts/rockchip/rk3399-tpm312.dts | 1011 +++++++++++++
 .../boot/dts/rockchip/rk3399-tvi3315a.dts     |  919 ++++++++++++
 .../boot/dts/rockchip/rk3399-xiaobao.dts      |  779 ++++++++++
 arch/arm64/boot/dts/rockchip/rk3399-yskj.dts  | 1029 ++++++++++++++
 .../boot/dts/rockchip/rk3399-zcube1-max.dts   |  946 +++++++++++++
 arch/arm64/boot/dts/rockchip/rk3399-zysj.dts  | 1187 ++++++++++++++++
 21 files changed, 16813 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-aio-3399b.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-am40.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-bozz-sw799.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-dg3399.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-dlfr100.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-fmx1-pro-b.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-fmx1-pro.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-hugsun-zm.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-king3399.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-sv-33a6x.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-taram.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-tb-ls3399.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-tn3399-v3.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-tpm312.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-tvi3315a.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-xiaobao.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-yskj.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-zcube1-max.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-zysj.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index ad684e383..f7c26410d 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -28,6 +28,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2-v11.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go3.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
@@ -45,9 +46,16 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-aio-3399b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-am40.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-bozz-sw799.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-dg3399.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-dlfr100.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-eaidk-610.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb-ind.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-fmx1-pro-b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-fmx1-pro.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb
@@ -56,9 +64,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-dumo.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-zm.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-king3399.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-kobol-helios64.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
@@ -88,6 +98,16 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-screen.dtbo
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sv-33a6x.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-taram.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-tb-ls3399.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-tn3399-v3.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-tpm312.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-xiaobao.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-yskj.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-tvi3315a.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-zcube1-max.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-zysj.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-armsom-sige1.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-nanopi-zero2.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts
new file mode 100644
index 000000000..b455800e7
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts
@@ -0,0 +1,394 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
+ * Copyright (c) 2022 Julian Pidancet <julian@pidancet.net>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "rk3328.dtsi"
+
+/ {
+	model = "FriendlyElec NanoPi NEO3";
+	compatible = "friendlyarm,nanopi-neo3", "rockchip,rk3328";
+
+	aliases {
+		led-boot = &status_led;
+		led-failsafe = &status_led;
+		led-running = &status_led;
+		led-upgrade = &status_led;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac_clk: gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac_clkin";
+		#clock-cells = <0>;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&reset_button_pin>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "reset";
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <50>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&status_led_pin>;
+		pinctrl-names = "default";
+
+		status_led: led-0 {
+			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+			label = "nanopi-neo3:green:status";
+		};
+	};
+
+	vcc_io_sdio: sdmmcio-regulator {
+		compatible = "regulator-gpio";
+		enable-active-high;
+		gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&sdio_vcc_pin>;
+		pinctrl-names = "default";
+		regulator-name = "vcc_io_sdio";
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-settling-time-us = <5000>;
+		regulator-type = "voltage";
+		startup-delay-us = <2000>;
+		states = <1800000 0x1>,
+			 <3300000 0x0>;
+		vin-supply = <&vcc_io_33>;
+	};
+
+	vcc_sd: sdmmc-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+		pinctrl-0 = <&sdmmc0m1_pin>;
+		pinctrl-names = "default";
+		regulator-name = "vcc_sd";
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_io_33>;
+	};
+
+	vdd_5v: vdd-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_5v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc_rtl8153: vcc-rtl8153-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtl8153_en_drv>;
+		regulator-always-on;
+		regulator-name = "vcc_rtl8153";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&display_subsystem {
+	status = "disabled";
+};
+
+&gmac2io {
+	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+	assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
+	clock_in_out = "input";
+	phy-handle = <&rtl8211e>;
+	phy-mode = "rgmii";
+	phy-supply = <&vcc_io_33>;
+	pinctrl-0 = <&rgmiim1_pins>;
+	pinctrl-names = "default";
+	rx_delay = <0x18>;
+	snps,aal;
+	tx_delay = <0x24>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rtl8211e: ethernet-phy@1 {
+			reg = <1>;
+			pinctrl-0 = <&eth_phy_reset_pin>;
+			pinctrl-names = "default";
+			reset-assert-us = <10000>;
+			reset-deassert-us = <50000>;
+			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+
+	rk805: pmic@18 {
+		compatible = "rockchip,rk805";
+		reg = <0x18>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk805-clkout2";
+		gpio-controller;
+		#gpio-cells = <2>;
+		pinctrl-0 = <&pmic_int_l>;
+		pinctrl-names = "default";
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vdd_5v>;
+		vcc2-supply = <&vdd_5v>;
+		vcc3-supply = <&vdd_5v>;
+		vcc4-supply = <&vdd_5v>;
+		vcc5-supply = <&vcc_io_33>;
+		vcc6-supply = <&vdd_5v>;
+
+		regulators {
+			vdd_log: DCDC_REG1 {
+				regulator-name = "vdd_log";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vdd_arm: DCDC_REG2 {
+				regulator-name = "vdd_arm";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <712500>;
+				regulator-max-microvolt = <1450000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <950000>;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_io_33: DCDC_REG4 {
+				regulator-name = "vcc_io_33";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc_18: LDO_REG1 {
+				regulator-name = "vcc_18";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc18_emmc: LDO_REG2 {
+				regulator-name = "vcc18_emmc";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_10: LDO_REG3 {
+				regulator-name = "vdd_10";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+		};
+	};
+};
+
+&io_domains {
+	pmuio-supply = <&vcc_io_33>;
+	vccio1-supply = <&vcc_io_33>;
+	vccio2-supply = <&vcc18_emmc>;
+	vccio3-supply = <&vcc_io_sdio>;
+	vccio4-supply = <&vcc_18>;
+	vccio5-supply = <&vcc_io_33>;
+	vccio6-supply = <&vcc_io_33>;
+	status = "okay";
+};
+
+&pinctrl {
+	button {
+		reset_button_pin: reset-button-pin {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	ethernet-phy {
+		eth_phy_reset_pin: eth-phy-reset-pin {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	leds {
+		status_led_pin: status-led-pin {
+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sd {
+		sdio_vcc_pin: sdio-vcc-pin {
+			rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		rtl8153_en_drv: rtl8153-en-drv {
+			rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
+	pinctrl-names = "default";
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vcc_io_sdio>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <0>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&u2phy {
+	status = "okay";
+};
+
+&u2phy_host {
+	status = "okay";
+};
+
+&u2phy_otg {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb20_otg {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usbdrd3 {
+	dr_mode = "host";
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	usb-eth@2 {
+		compatible = "realtek,rtl8153";
+		reg = <2>;
+
+		realtek,led-data = <0x87>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-aio-3399b.dts b/arch/arm64/boot/dts/rockchip/rk3399-aio-3399b.dts
new file mode 100644
index 000000000..9890c76ab
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-aio-3399b.dts
@@ -0,0 +1,1122 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3399.dtsi"
+#include "rk3399-op1.dtsi"
+
+/ {
+	model = "AIO-3399B";
+	compatible = "aio,aio-3399b", "rockchip,rk3399";
+
+	aliases {
+		led-boot = &user_led1;
+		led-failsafe = &user_led2;
+		led-running = &user_led1;
+		led-upgrade = &user_led2;
+		mmc0 = &sdio0;
+		mmc1 = &sdmmc;
+		mmc2 = &sdhci;
+		spi1 = &spi1;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1750000>;
+		poll-interval = <100>;
+
+		recovery {
+			label = "Recovery";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <0>;
+		};
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		fan-supply = <&vcc12v_dcin>;
+		pwms = <&pwm0 0 10000 0>;
+		cooling-levels = <0 75 100 150 200 255>;
+		//rockchip,temp-trips = <40000 1 45000 2 50000 3 55000 4 60000 5>;
+		status = "okay";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+		pinctrl-names = "default";
+		pinctrl-0 = <&power_key>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		power {
+			debounce-interval = <100>;
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+			label = "GPIO Key Power";
+			linux,code = <KEY_POWER>;
+			wakeup-source;
+		};
+	};
+	
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+		pinctrl-0 = <&ir_int>;
+		pinctrl-names = "default";
+	};
+
+	leds: gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>;
+
+		user_led1: user-led1 {
+			gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+			label = "green:user_led1";
+		};
+
+		user_led2: user-led2 {
+			gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_LOW>;
+			label = "blue:user_led2";
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_reg_on_h>;
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+		post-power-on-delay-ms = <300>;
+	};
+
+	/*
+	 * Really, this is supplied by vcc_1v8, and vcc1v8_s3 only
+	 * drives the enable pin, but we can't quite model that.
+	 */
+	vcca0v9_s3: vcca0v9-s3 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		regulator-name = "vcca0v9_s3";
+		vin-supply = <&vcc1v8_s3>;
+	};
+
+	/* As above, actually supplied by vcc3v3_sys */
+	vcca1v8_s3: vcca1v8-s3 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-name = "vcca1v8_s3";
+		vin-supply = <&vcc1v8_s3>;
+	};
+
+	vcc12v_dcin: vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v-dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc3v3_ext: vcc3v3-ext {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_ext";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_ext1: vcc3v3-ext1 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+		gpio = <&gpio2 RK_PA1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ext_pon_switch_wifi>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_ext1";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_ext2: vcc3v3-ext2 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+		gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ext_jms561_m2>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_ext2";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_sys";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vcc5v0_sys";
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	/* switched by pmic_sleep */
+	vcc1v8_s3: vcc1v8-s3 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-name = "vcc1v8_s3";
+		vin-supply = <&vcc_1v8>;
+	};
+
+	vcc3v3_sd: vcc3v3-sd {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc0_pwr_h>;
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_sd";
+		vin-supply = <&vcc3v3_ext>;
+	};
+
+	vcc3v3_jms561: vcc3v3-jms561 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&jms561_pw>;
+		startup-delay-us = <200000>;
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_jms561";
+		vin-supply = <&vcc3v3_ext2>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		vin-supply = <&vcc5v0_sys>;
+
+		/* for rockchip boot on */
+		rockchip,pwm_id= <2>;
+		rockchip,pwm_voltage = <1000000>;
+
+	};
+
+	wireless-wlan {
+		compatible = "wlan-platdata";
+		rockchip,grf = <&grf>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_l>;
+		wifi_chip_type = "ap6275s";
+		WIFI,host_wake_irq = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	rtl8367s {
+		compatible = "realtek,rtl8367s";
+		cpu_port = <7>;
+		mii-bus = <&mdio0>;
+		realtek,extif1 = <1 0 12 1 1 1 1 1 4>;	//rtl8367b_extif_init_of
+		realtek,extif2 = <1 3 1 1 1 1 1 1 2>;
+	};
+};
+
+&cpu_thermal {
+		trips {
+				cpu_cool: cpu_cool {
+						temperature = <38000>;
+						hysteresis = <2000>;
+						type = "active";
+				};
+				cpu_normal: cpu_normal {
+						temperature = <43000>;
+						hysteresis = <2000>;
+						type = "active";
+				};
+				cpu_warm: cpu_warm {
+						temperature = <46000>;
+						hysteresis = <2000>;
+						type = "active";
+				};
+				cpu_hot: cpu_hot {
+						temperature = <48000>;
+						hysteresis = <2000>;
+						type = "active";
+				};
+				cpu_max: cpu_max {
+						temperature = <50000>;
+						hysteresis = <2000>;
+						type = "active";
+				};
+		};
+		cooling-maps {
+				map2 {
+						trip = <&cpu_cool>;
+						cooling-device = <&fan 0 1>;
+				};
+				map3 {
+						trip = <&cpu_normal>;
+						cooling-device = <&fan 1 2>;
+				};
+				map4 {
+						trip = <&cpu_warm>;
+						cooling-device = <&fan 2 3>;
+				};
+				map5 {
+						trip = <&cpu_hot>;
+						cooling-device = <&fan 3 4>;
+				};
+				map6 {
+						trip = <&cpu_max>;
+						cooling-device = <&fan 4 5>;
+				};
+		};
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&cru SCLK_MAC>;
+	assigned-clock-rates = <125000000>;
+	clock_in_out = "output";
+	phy-mode = "rgmii";
+	phy-supply = <&vcc3v3_s3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+
+	mdio0: mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+// Let hdmi port support 4k@60fps.
+&hdmi_in_vopl {
+	status = "disabled";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc5v0_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc1v8_pmu>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-name = "vdd_center";
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-name = "vdd_cpu_l";
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_ddr";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc1v8_dvp";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc2v8_dvp: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-name = "vcc2v8_dvp";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc1v8_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcc_sdio";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcca3v0_codec";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-name = "vcc_1v5";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_codec";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcc_3v0";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_s3";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cpu_b_sleep>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-name = "vdd_cpu_b";
+		regulator-ramp-delay = <1000>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpu_sleep>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-name = "vdd_gpu";
+		regulator-ramp-delay = <1000>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";	//hdmi_cec
+};
+
+&i2s2 {
+	status = "okay";	//hdmi_sound
+};
+
+&spi1 {
+	status = "okay";	//lcd pannel
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_cs0>;
+	//cs-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; /*SPI-CS:PC3 and PA6*/
+
+	st7789v@0 {
+		status = "okay";
+		compatible = "sitronix,st7789v";
+		reg = <0>;
+		spi-max-frequency = <12000000>;
+		rgb;
+		fps = <30>;
+		rotate = <90>;
+		buswidth = <8>;
+		dc-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_LOW>;
+		led-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+		debug = <0>; //等级0～7 越高信息越多
+	};
+};
+
+&io_domains {
+	status = "okay";
+
+	bt656-supply = <&vcc1v8_dvp>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vcc_sdio>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pcie_phy {
+	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+	assigned-clock-rates = <100000000>;
+	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+	status = "okay";
+};
+
+&pcie0 {
+	ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+	num-lanes = <4>;
+	max-link-speed = <2>;
+	status = "okay";
+	vpcie0v9-supply = <&vcca0v9_s3>;
+	vpcie1v8-supply = <&vcca1v8_s3>;
+	vpcie3v3-supply = <&vcc3v3_ext>;
+};
+
+&pinctrl {
+	buttons {
+		power_key: power_key {
+			rockchip,pins =
+				<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	gmac { //13 16 19 22 26
+		rgmii_pins: rgmii-pins {
+			rockchip,pins =
+				/* mac_txclk */
+				<3 RK_PC1 1 &pcfg_pull_none_19ma>,
+				/* mac_rxclk */
+				<3 RK_PB6 1 &pcfg_pull_none>,
+				/* mac_mdio */
+				<3 RK_PB5 1 &pcfg_pull_none>,
+				/* mac_txen */
+				<3 RK_PB4 1 &pcfg_pull_none_26ma>,
+				/* mac_clk */
+				<3 RK_PB3 1 &pcfg_pull_none>,
+				/* mac_rxdv */
+				<3 RK_PB1 1 &pcfg_pull_none>,
+				/* mac_mdc */
+				<3 RK_PB0 1 &pcfg_pull_none>,
+				/* mac_rxd1 */
+				<3 RK_PA7 1 &pcfg_pull_none>,
+				/* mac_rxd0 */
+				<3 RK_PA6 1 &pcfg_pull_none>,
+				/* mac_txd1 */
+				<3 RK_PA5 1 &pcfg_pull_none_26ma>,
+				/* mac_txd0 */
+				<3 RK_PA4 1 &pcfg_pull_none_26ma>,
+				/* mac_rxd3 */
+				<3 RK_PA3 1 &pcfg_pull_none>,
+				/* mac_rxd2 */
+				<3 RK_PA2 1 &pcfg_pull_none>,
+				/* mac_txd3 */
+				<3 RK_PA1 1 &pcfg_pull_none_26ma>,
+				/* mac_txd2 */
+				<3 RK_PA0 1 &pcfg_pull_none_26ma>;
+		};
+	};
+
+	ir {
+		ir_int: ir-int {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	power_ext{
+		ext_pon_switch_wifi: ext-pon-switch-wifi {
+			rockchip,pins = <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		ext_jms561_m2: ext-jms561-m2 {
+			rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		jms561_pw: jms561-pw {
+			rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		user_led1_pin: user-led1-pin {
+			rockchip,pins =
+				<1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		user_led2_pin: user-led2-pin {
+			rockchip,pins =
+				<1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcfg_pull_none_16ma: pcfg-pull-none-16ma {
+		bias-disable;
+		drive-strength = <16>;
+	};
+
+	pcfg_pull_none_19ma: pcfg-pull-none-19ma {
+		bias-disable;
+		drive-strength = <19>;
+	};
+
+	pcfg_pull_none_26ma: pcfg-pull-none-26ma {
+		bias-disable;
+		drive-strength = <26>;
+	};
+
+	pcfg_pull_up_15ma: pcfg-pull-up_15ma {
+		bias-pull-up;
+		drive-strength = <15>;
+	};
+
+	pcfg_pull_none_15ma: pcfg-pull-none-15ma {
+		bias-disable;
+		drive-strength = <15>;
+	};
+
+	pcfg_pull_up_16ma: pcfg-pull-up_16ma {
+		bias-pull-up;
+		drive-strength = <16>;
+	};
+
+	pmic {
+		cpu_b_sleep: cpu-b-sleep {
+			rockchip,pins =
+				<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		gpu_sleep: gpu-sleep {
+			rockchip,pins =
+				<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		pmic_int_l: pmic-int-l {
+			rockchip,pins =
+				<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdmmc {		//4 6 8 10 12 14 16 18
+		sdmmc_bus1: sdmmc-bus1 {
+			rockchip,pins =
+				<4 RK_PB0 1 &pcfg_pull_up>;
+		};
+
+		sdmmc_bus4: sdmmc-bus4 {
+			rockchip,pins =
+				<4 RK_PB0 1 &pcfg_pull_up_16ma>,
+				<4 RK_PB1 1 &pcfg_pull_up_16ma>,
+				<4 RK_PB2 1 &pcfg_pull_up_16ma>,
+				<4 RK_PB3 1 &pcfg_pull_up_16ma>;
+		};
+
+		sdmmc_clk: sdmmc-clk {
+			rockchip,pins =
+				<4 RK_PB4 1 &pcfg_pull_none_16ma>;
+		};
+
+		sdmmc_cmd: sdmmc-cmd {
+			rockchip,pins =
+				<4 RK_PB5 1 &pcfg_pull_up_16ma>;
+		};
+
+		sdmmc_cd: sdmmc-cd {
+			rockchip,pins =
+				<0 RK_PA7 1 &pcfg_pull_up>;
+		};
+
+		sdmmc_wp: sdmmc-wp {
+			rockchip,pins =
+				<0 RK_PB0 1 &pcfg_pull_up>;
+		};
+	};
+
+	sdio {
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins =
+				<0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_reg_on_h: bt-reg-on-h {
+			/* external pullup to VCC1V8_PMUPLL */
+			rockchip,pins =
+				<0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins =
+				<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wifi_reg_on_h: wifi-reg_on-h {
+			rockchip,pins =
+				<0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio0 {			//5;10;15;20
+		sdio0_bus1: sdio0-bus1 {
+			rockchip,pins =
+				<2 RK_PC4 1 &pcfg_pull_up>;
+		};
+
+		sdio0_bus4: sdio0-bus4 {
+			rockchip,pins =
+				<2 RK_PC4 1 &pcfg_pull_up_15ma>,
+				<2 RK_PC5 1 &pcfg_pull_up_15ma>,
+				<2 RK_PC6 1 &pcfg_pull_up_15ma>,
+				<2 RK_PC7 1 &pcfg_pull_up_15ma>;
+		};
+
+		sdio0_cmd: sdio0-cmd {
+			rockchip,pins =
+				<2 RK_PD0 1 &pcfg_pull_up_15ma>;
+		};
+
+		sdio0_clk: sdio0-clk {
+			rockchip,pins =
+				<2 RK_PD1 1 &pcfg_pull_none_15ma>;
+		};
+
+		sdio0_cd: sdio0-cd {
+			rockchip,pins =
+				<2 RK_PD2 1 &pcfg_pull_up>;
+		};
+
+		sdio0_pwr: sdio0-pwr {
+			rockchip,pins =
+				<2 RK_PD3 1 &pcfg_pull_up>;
+		};
+
+		sdio0_bkpwr: sdio0-bkpwr {
+				rockchip,pins =
+					<2 RK_PD4 1 &pcfg_pull_up>;
+		};
+
+		sdio0_wp: sdio0-wp {
+			rockchip,pins =
+				<0 RK_PA3 1 &pcfg_pull_up>;
+		};
+
+		sdio0_int: sdio0-int {
+			rockchip,pins =
+				<0 RK_PA4 1 &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_host_wake_l: wifi-host-wake-l {
+			rockchip,pins = 
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdmmc {
+		sdmmc0_det_l: sdmmc0-det-l {
+			rockchip,pins = 
+				<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		sdmmc0_pwr_h: sdmmc0-pwr-h {
+			rockchip,pins = 
+				<2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmu1830-supply = <&vcc_3v0>;
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";	//vdd_log
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vcca1v8_s3>;
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&sdio0 {
+	bus-width = <4>;
+	//clock-frequency = <50000000>;
+	cap-sdio-irq;
+	supports-sdio;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	brcmf: wifi@1 {
+		compatible = "brcm,bcm43752-fmac","brcm,bcm4359-fmac","marvell,sd8897";
+		reg = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_l>;
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	cap-sdio-irq;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
+	status = "okay";
+	//vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vcc3v3_sd>;
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
+	status = "disabled";
+};
+
+&uart2 {
+	status = "okay";	//ttl
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	snps,parkmode-disable-ss-quirk;
+	snps,dis_rxdet_inp3_quirk;
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	snps,parkmode-disable-ss-quirk;
+	snps,dis_rxdet_inp3_quirk;
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-am40.dts b/arch/arm64/boot/dts/rockchip/rk3399-am40.dts
new file mode 100644
index 000000000..195ad7946
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-am40.dts
@@ -0,0 +1,792 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2025 retro98boy <retro98boy@qq.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/leds/common.h>
+#include "rk3399.dtsi"
+
+/ {
+	model = "SMART AM40";
+	compatible = "smart,am40", "rockchip,rk3399";
+
+	aliases {
+		ethernet0 = &gmac;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+		rtc0 = &pt7c4563;
+		/*
+		 * The rk808 circuit design on this board does not have the ability to maintain real-time time after a power outage.
+		 * Registering rk808 as rtc99 (most kernel configurations read time from rtc0) can prevent the kernel from reading the time (2013) from rk808 during startup.
+		 */
+		rtc99 = &rk808;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwr_led>;
+
+		pwr-led {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_YELLOW>;
+			gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwr_btn>;
+
+		pwr-btn {
+			debounce-interval = <100>;
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+			label = "pwr-btn";
+			linux,code = <KEY_POWER>;
+			wakeup-source;
+		};
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-recovery {
+			label = "Recovery";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <18000>;
+		};
+	};
+
+	vcc1v8_s0: regulator-vcc1v8-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vcc_sys: regulator-vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc_phy: regulator-vcc-phy {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_phy_en>;
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc3v3_sys: regulator-vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc5v0_host: regulator-vcc5v0-host {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc3v3_pcie: regulator-vcc3v3-pcie {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_pcie_en>;
+		regulator-name = "vcc3v3_pcie";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	front_hdmi_5v: regulator-front-hdmi-5v {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&front_hdmi_5v_en>;
+		regulator-name = "front_hdmi_5v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	otg_vbus: regulator-otg-vbus {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&otg_vbus_en>;
+		regulator-name = "otg_vbus";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_log: regulator-vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		pwm-supply = <&vcc_sys>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+	};
+
+	virtual_pd: virtual-pd {
+		compatible = "linux,extcon-usbc-virtual-pd";
+		pinctrl-names = "default";
+		pinctrl-0 = <&dp_hpd>;
+		det-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>;
+		vpd-data-role = "display-port";
+		vpd-super-speed;
+	};
+
+	dp-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "dp-sound";
+
+		simple-audio-card,cpu {
+			/* sound-dai = <&i2s2>; */
+			sound-dai = <&spdif>;
+		};
+
+		simple-audio-card,codec {
+			/* sound-dai = <&cdn_dp 0>; */
+			sound-dai = <&cdn_dp 1>;
+		};
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clock-parents = <&clkin_gmac>;
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	clock_in_out = "input";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_rst_l>;
+	phy-handle = <&rtl8211f>;
+	phy-mode = "rgmii";
+	phy-supply = <&vcc_phy>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rtl8211f: rtl8211f@0 {
+			reg = <0>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <30000>;
+			reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+			realtek,led-data = <0x820b>;
+		};
+	};
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vcca0v9_hdmi>;
+	avdd-1v8-supply = <&vcca1v8_hdmi>;
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc6-supply = <&vcc_sys>;
+		vcc7-supply = <&vcc_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc_sys>;
+		vcc10-supply = <&vcc_sys>;
+		vcc11-supply = <&vcc_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_hdmi: LDO_REG2 {
+				regulator-name = "vcca1v8_hdmi";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8: LDO_REG3 {
+				regulator-name = "vcca1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sd: LDO_REG4 {
+				regulator-name = "vcc_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v0_sd: LDO_REG5 {
+				regulator-name = "vcc3v0_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca0v9_hdmi: LDO_REG7 {
+				regulator-name = "vcca0v9_hdmi";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel1_pin>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel2_pin>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <300>;
+
+	pt7c4563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "rtc_xin32k";
+		wakeup-source;
+		interrupt-parent = <&gpio0>;
+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-0 = <&rtc_int>;
+		pinctrl-names = "default";
+	};
+};
+
+&i2s2 {
+	status = "okay";
+};
+
+&io_domains {
+	bt656-supply = <&vcc1v8_s0>;
+	audio-supply = <&vcc1v8_s0>;
+	sdmmc-supply = <&vcc_sd>;
+	gpio1830-supply = <&vcc_3v0>;
+	status = "okay";
+};
+
+&pcie0 {
+	ep-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+	num-lanes = <4>;
+	pinctrl-0 = <&pcie_clkreqn>;
+	pinctrl-names = "default";
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+&pinctrl {
+	buttons {
+		pwr_btn: pwr-btn {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	display {
+		dp_hpd: dp-hpd {
+			rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_input_pull_up>;
+		};
+
+		front_hdmi_5v_en: front-hdmi-5v-en {
+			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	gmac {
+		phy_rst_l: phy-rst-l {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc_phy_en: vcc-phy-en {
+			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		pwr_led: pwr-led {
+			rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie_clkreqn: pci-clkreqn {
+			rockchip,pins = <2 RK_PD2 2 &pcfg_pull_none>;
+		};
+
+		vcc3v3_pcie_en: vcc3v3-pcie-en {
+			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vsel1_pin: vsel1-pin {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		vsel2_pin: vsel2-pin {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	rtc {
+		rtc_int: rtc-int {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		vcc5v0_host_en: vcc5v0-hots-en {
+			rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		otg_vbus_en: otg-vbus-en {
+			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmu1830-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	max-frequency = <150000000>;
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&spdif {
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
+	vqmmc-supply = <&vcc_sd>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&cdn_dp {
+	phys = <&tcphy0_dp>;
+	extcon = <&virtual_pd>;
+	status = "okay";
+};
+
+&tcphy0 {
+	extcon = <&virtual_pd>;
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart4 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&vopl_out_dp {
+	status = "disabled";
+};
+
+&dp_in_vopl {
+	status = "disabled";
+};
+
+&vopb_out_hdmi {
+	status = "disabled";
+};
+
+&hdmi_in_vopb {
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-bozz-sw799.dts b/arch/arm64/boot/dts/rockchip/rk3399-bozz-sw799.dts
new file mode 100644
index 000000000..6a96a11c4
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-bozz-sw799.dts
@@ -0,0 +1,505 @@
+/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/input.h>
+#include "rk3399.dtsi"
+
+/ {
+	model = "RK3399 SW799";
+	compatible = "rockchip,rk3399-sw799", "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdhci;
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc_phy: vcc-phy {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_log: vdd-log  {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		rockchip,pwm_voltage = <900000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+	};
+
+	typec_power {
+		status = "okay";
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		regulator-name = "typec_power";
+		regulator-always-on;
+	};
+
+	usb_power {
+		status = "okay";
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		regulator-name = "typec_power";
+		regulator-always-on;
+	};
+
+	4g_module_power {
+		status = "okay";
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		regulator-name = "4g_module_power";
+		regulator-always-on;
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	phy-supply = <&vcc_phy>;
+	phy-mode = "rgmii";
+	clock_in_out = "input";
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	clock-frequency = <400000>;
+
+	vdd_cpu_b: syr827@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-compatible = "fan53555-reg";
+		vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-initial-state = <3>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: syr828@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-compatible = "fan53555-reg";
+		pinctrl-names = "default";
+		vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-initial-state = <3>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc1v8_pmu>;
+
+		regulators {
+
+			vdd_center: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-name = "vdd_center";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-name = "vdd_cpu_l";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_ddr";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc1v8_dvp";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v0_tp: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcc3v0_tp";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc1v8_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_sdio";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcca3v0_codec";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-name = "vcc_1v5";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcc1v8_codec: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc1v8_codec";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcc_3v0";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_s3";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&sdio0 {
+	bus-width = <4>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	wifi@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+		interrupt-names = "host-wake";
+		brcm,drive-strength = <5>;
+		pinctrl-names = "default";
+	};
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	keep-power-in-suspend;
+	non-removable;
+	supports-emmc;
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <1>;
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		status = "disable";
+	};
+
+	u2phy0_host: host-port {
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		status = "okay";
+	};
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "disable";
+};
+
+&usbdrd_dwc3_0 {
+	status = "disable";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-dg3399.dts b/arch/arm64/boot/dts/rockchip/rk3399-dg3399.dts
new file mode 100644
index 000000000..ae9bad55e
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-dg3399.dts
@@ -0,0 +1,1009 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "dt-bindings/input/input.h"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "dt-bindings/usb/pd.h"
+#include "rk3399.dtsi"
+
+/ {
+	model = "DG-3399";
+	compatible = "ryd,dg-3399", "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdio0;
+		mmc1 = &sdmmc;
+		mmc2 = &sdhci;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwrbtn>;
+
+		key-power {
+			debounce-interval = <100>;
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; // bsp
+			label = "GPIO Key Power";
+			linux,code = <KEY_POWER>;
+			wakeup-source;
+		};
+	};
+/*
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+		pinctrl-0 = <&ir_int>;
+		pinctrl-names = "default";
+	};
+*/
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&sys_led_pin>;
+
+		sys_led: led-0 {
+			label = "green:sys";
+			default-state = "off";
+			linux,default-trigger = "heartbeat";
+			gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; // bsp
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; // bsp
+	};
+
+	vcc12v_dcin: vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc1v8_s0: vcc1v8-s0 {
+		compatible = "regulator-fixed"; // bsp
+		regulator-name = "vcc1v8_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed"; // bsp
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>; // bsp
+		regulator-name = "vcc5v0_host";
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_typec: vcc5v0-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; //bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec_en>;
+		regulator-name = "vcc5v0_typec";
+		regulator-always-on;
+	};
+
+	vcc5v0_usb3: vcc5v0-usb3-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb3_en>; // bsp
+		regulator-name = "vcc5v0_usb3";
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		pwm-supply = <&vcc5v0_sys>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1700000>;
+	};
+
+	usb3_hub: usb3-hub-en {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb3_hub_en>; // bsp
+		regulator-name = "usb3_hub_en";
+		regulator-always-on;
+	};
+
+	gsm_en: gsm-en {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; // bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&gsm_power_en>; // bsp
+		regulator-name = "gsm_power_en";
+		regulator-always-on;
+	};
+/*
+	watchdog: watchdog-en {
+		compatible = "regulator-fixed";
+		enable-active-low;
+		gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; // bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&watchdog_en>; // bsp
+		regulator-name = "watchdog_en";
+		regulator-always-on;
+	};
+
+	watchdog: watchdog {
+		pinctrl-names = "default";
+		pinctrl-0 = <&watchdog_feed>;
+		compatible = "linux,wdt-gpio";
+		always-running;
+		gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+		hw_algo = "toggle";
+		hw_margin_ms = <1500>;
+		status = "disabled";
+	};
+*/
+
+	rt5651-sound {
+		status = "okay";
+		compatible = "simple-audio-card";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_det>;
+
+		simple-audio-card,name = "rt5651";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,hp-det-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; // bsp
+		simple-audio-card,aux-devs = <&speaker_amp>;
+		simple-audio-card,pin-switches = "Speaker";
+		simple-audio-card,widgets =
+			"Microphone", "Headset Microphone",
+			"Microphone", "Internal Microphone",
+			"Headphone", "Headphones",
+			"Speaker", "Speaker";
+		simple-audio-card,routing =
+			"Headphones", "HPOL",
+			"Headphones", "HPOR",
+
+			"Internal Microphone", "micbias1",
+			"IN2P", "Internal Microphone",
+			"IN2N", "Internal Microphone",
+			"IN1P", "Headset Microphone",
+
+			"Speaker Amplifier INL", "HPOL",
+			"Speaker Amplifier INR", "HPOR",
+			"Speaker", "Speaker Amplifier OUTL",
+			"Speaker", "Speaker Amplifier OUTR";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&rt5651>;
+		};
+	};
+
+	speaker_amp: speaker-amplifier {
+		compatible = "simple-audio-amplifier";
+		pinctrl-names = "default";
+		pinctrl-0 = <&spk_ctl>;
+		enable-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; // bsp
+		sound-name-prefix = "Speaker Amplifier";
+		vcc-supply = <&vcc5v0_sys>;
+	};
+/*
+	lcd_bl: lcd-bl {
+			compatible = "gpio-backlight";
+			gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
+	};
+*/
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_lan>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; // bsp
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc5v0_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_hdmi: LDO_REG2 {
+				regulator-name = "vcca1v8_hdmi";
+				regulator-min-microvolt = <1800000>; // bsp 3300000
+				regulator-max-microvolt = <1800000>; // bsp 3300000
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG3 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sd: LDO_REG4 {
+				regulator-name = "vcc_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc3v0_sd: LDO_REG5 {
+				regulator-name = "vcc3v0_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca0v9_hdmi: LDO_REG7 {
+				regulator-name = "vcca0v9_hdmi";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: vcc_lan: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel1_pin>;  // bsp
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel2_pin>; // bsp
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c1 {
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+
+	rt5651: rt5651@1a {
+		#sound-dai-cells = <0>;
+		compatible = "realtek,rt5651";
+		reg = <0x1a>;
+		clocks = <&cru SCLK_I2S_8CH_OUT>;
+		clock-names = "mclk";
+		status = "okay";
+	};
+};
+
+// HDMI
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+// TP I2C
+&i2c4 {
+	i2c-scl-rising-time-ns = <600>;
+	i2c-scl-falling-time-ns = <20>;
+	status = "okay";
+
+	fusb0: typec-portc@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; // bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&fusb0_int>;
+		vbus-supply = <&vcc5v0_typec>;
+		status = "okay";
+	};
+
+	wk2204: wk2xxx@70 {
+		compatible = "wk2xxx,wk2xxxtty";
+		reg = <0x70>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&wk2xxx_irq_pin &wk2xxx_cs_pin>;
+		wk2xxx_irq_pin = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>;
+		wk2xxx_cs_pin = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+		status = "disabled";
+	};
+};
+
+&i2s0_8ch_bus {
+	rockchip,pins =
+		<3 RK_PD0 1 &pcfg_pull_none>,
+		<3 RK_PD1 1 &pcfg_pull_none>,
+		<3 RK_PD2 1 &pcfg_pull_none>,
+		<3 RK_PD3 1 &pcfg_pull_none>,
+		<3 RK_PD6 1 &pcfg_pull_none>,
+		<3 RK_PD7 1 &pcfg_pull_none>,
+		<4 RK_PA0 1 &pcfg_pull_none>;
+};
+
+&i2s0_8ch_bus_bclk_off {
+	rockchip,pins =
+		<3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
+		<3 RK_PD1 1 &pcfg_pull_none>,
+		<3 RK_PD2 1 &pcfg_pull_none>,
+		<3 RK_PD3 1 &pcfg_pull_none>,
+		<3 RK_PD6 1 &pcfg_pull_none>,
+		<3 RK_PD7 1 &pcfg_pull_none>,
+		<4 RK_PA0 1 &pcfg_pull_none>;
+};
+
+&i2s0{
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s_8ch_mclk_pin>, <&i2s0_8ch_bus>;
+	#sound-dai-cells = <0>;
+	rockchip,capture-channels = <8>;
+	rockchip,playback-channels = <8>;
+	status = "okay";
+};
+
+// HDMI sound
+&i2s2 {
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+
+	bt656-supply = <&vcc1v8_s0>; // bsp
+	audio-supply = <&vcc1v8_s0>; // bsp
+	sdmmc-supply = <&vcc_sd>; // bsp
+	gpio1830-supply = <&vcc_3v0>; // bsp
+};
+
+&pcie0 {
+	ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; // ??
+	num-lanes = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_perst>;
+	vpcie12v-supply = <&vcc12v_dcin>;
+	// vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+&pmu_io_domains {
+	pmu1830-supply = <&vcc_3v0>; // bsp
+	status = "okay";
+};
+
+&pinctrl {
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	wifi {
+		wifi_host_wake_l: wifi-host-wake-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; // sch
+		};
+	};
+
+	buttons {
+		pwrbtn: pwrbtn {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+	};
+
+	fusb302x {
+		fusb0_int: fusb0-int {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+	};
+
+	ir {
+		ir_int: ir-int {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie_perst: pcie-perst {
+			rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie_pwr_en: pcie-pwr-en {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+
+		vsel1_pin: vsel1-pin {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+
+		vsel2_pin: vsel2-pin {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+	};
+
+	sdcard {
+		sdmmc0_pwr_h: sdmmc0-pwr-h {
+			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	usb-typec {
+		vcc5v0_typec_en: vcc5v0_typec_en {
+			rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+	};
+
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		vcc5v0_usb3_en: vcc5v0-usb3-en {
+			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+		usb3_hub_en: usb3-hub-en {
+			rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+	};
+
+	headphone {
+		hp_det: hp-det {
+			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+		spk_ctl: spk-ctl {
+			rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	func_gpio {
+		wk2xxx_irq_pin: wk2xxx-irq-pin {
+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+		wk2xxx_cs_pin: wk2xxx-cs-pin {
+			rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+		wakeonlan_pin: wakeonlan-pin {
+			rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+		pwr_hold: pwr-hold {
+			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+		sys_led_pin: sys-led-pin {
+			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		human_induction: human-induction {
+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		infrared_test: infrared-test {
+			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		heartbeat_test: heartbeat-test {
+			rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		watchdog_feed: watchdog-feed {
+			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+		watchdog_en: watchdog-en {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+		gsm_power_en: gsm-power-en {
+			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+		gsm_reset_pin: gsm-reset-pin {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+		gdm_disable_pin: gdm-disable-pin {
+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+		gsm_sim_det: gsm-sim-det {
+			rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+		gpio_a0_pin: gpio-a0-pin {
+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		// tp_rst_pin: tp-rst-pin {
+		// 	rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		// };
+		// tp_int_pin: tp-int-pin {
+		// 	rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		// };
+	};
+
+	gmac {
+		rgmii_sleep_pins: rgmii-sleep-pins {
+			rockchip,pins =<3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; // sch
+		};
+	};
+
+	i2s0 {
+		i2s_8ch_mclk_pin: i2s-8ch-mclk-pin {
+			rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&sdio0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	bus-width = <4>;
+	clock-frequency = <50000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+
+	brcmf: wifi@1 {
+		compatible = "brcm,bcm43455-fmac";
+		reg = <1>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+		interrupt-names = "host-wake";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_l>; // sch
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; // bsp
+	disable-wp;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+	vqmmc-supply = <&vcc_sd>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		phy-supply = <&vcc5v0_typec>;
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk808 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; // bsp
+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; // bsp
+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; // bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+// near MIC
+&spi1 {
+	status = "disabled";
+	display@0 {
+			compatible = "jianda,jd-t18003-t01", "sitronix,st7735r";
+			reg = <0>;
+			pinctrl-names = "default";
+			spi-max-frequency = <32000000>;
+			dc-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+			reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+			rotation = <270>;
+			// backlight = <&lcd_bl>;
+	};
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-dlfr100.dts b/arch/arm64/boot/dts/rockchip/rk3399-dlfr100.dts
new file mode 100644
index 000000000..acdaeaa24
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-dlfr100.dts
@@ -0,0 +1,732 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/input.h>
+#include "rk3399.dtsi"
+
+/ {
+	model = "Dilusense DLFR100";
+	compatible = "dilusense,dlfr100", "rockchip,rk3399";
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host";
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_sd: vcc-sd {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_sd_h>;
+		regulator-name = "vcc_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <100000>;
+		};
+
+		button-down {
+			label = "Volume Down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			press-threshold-microvolt = <300000>;
+		};
+
+		back {
+			label = "Back";
+			linux,code = <KEY_BACK>;
+			press-threshold-microvolt = <985000>;
+		};
+
+		menu {
+			label = "Menu";
+			linux,code = <KEY_MENU>;
+			press-threshold-microvolt = <0x1314000>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+		pinctrl-0 = <&pwr_btn>;
+
+		power {
+			debounce-interval = <100>;
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+			label = "GPIO Key Power";
+			linux,code = <KEY_POWER>;
+			wakeup-source;
+		};
+	};
+
+	rt5640-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "realtek,rt5640-codec";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,widgets =
+			"Microphone", "Mic Jack",
+			"Headphone", "Headphones";
+		simple-audio-card,routing =
+			"Mic Jack", "micbias1",
+			"Headphones", "HPOL",
+			"Headphones", "HPOR";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&rt5640>;
+		};
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_phy>;
+	phy-mode = "rgmii";
+	phy-handle = <&rtl8211e>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rtl8211e: ethernet-phy@1 {
+			reg = <1>;
+			interrupt-parent = <&gpio3>;
+			interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <30000>;
+			reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
+		system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc1v8_pmu>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v0_tp: LDO_REG2 {
+				regulator-name = "vcc3v0_tp";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-name = "vcca1v8_codec";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-0 = <&vsel1_pin>;
+		pinctrl-names = "default";
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-initial-state = <3>;
+		vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		pinctrl-0 = <&vsel2_pin>;
+		pinctrl-names = "default";
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-initial-state = <3>;
+		vsel-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	isl1208@6f {
+		compatible = "isil,isl1208";
+		reg = <0x6f>;
+	};
+};
+
+&i2c1 {
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+
+	rt5640: rt5640@1c {
+		#sound-dai-cells = <0>;
+		compatible = "realtek,rt5640";
+		reg = <0x1c>;
+		realtek,in1-differential;
+		pinctrl-0 = <&i2s_8ch_mclk>;
+		clocks = <&cru SCLK_I2S_8CH_OUT>;
+		clock-names = "mclk";
+	};
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2s0 {
+	rockchip,playback-channels = <8>;
+	rockchip,capture-channels = <8>;
+	status = "okay";
+};
+
+&i2s2 {
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+
+	bt656-supply = <&vcc_3v0>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vcc_sdio>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+&pcie0 {
+	ep-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+	max-link-speed = <1>;
+	num-lanes = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_clkreqn_cpm>;
+	status = "okay";
+
+	pcie@0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		pcie-eth@0,0 {
+			compatible = "realtek,r8168";
+			reg = <0x000000 0 0 0 0>;
+			realtek,led-data = <0x87>;
+		};
+	};
+};
+
+&pinctrl {
+	buttons {
+		pwr_btn: pwr-btn {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	i2s0 {
+		i2s_8ch_mclk: i2s-8ch-mclk {
+			rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vsel1_pin: vsel1-pin {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		vsel2_pin: vsel2-pin {
+			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		pmic_dvs2:pmic-dvs2 {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb2 {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	vcc_sd {
+		vcc_sd_h: vcc-sd-h {
+			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	gmac {
+		phy_intb: phy-intb {
+			rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_rstb: phy-rstb {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&pwm3 {
+	status = "okay";
+};
+
+&sdio0 {
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	clock-frequency = <50000000>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+	clock-frequency = <150000000>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vcc_sdio>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
+&u2phy1_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-fmx1-pro-b.dts b/arch/arm64/boot/dts/rockchip/rk3399-fmx1-pro-b.dts
new file mode 100644
index 000000000..d7b38896c
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-fmx1-pro-b.dts
@@ -0,0 +1,764 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+#include "rk3399-op1.dtsi"
+
+/ {
+	model = "RK3399 FMX1";
+	compatible = "rk3399,fmx1", "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdhci;
+		mmc2 = &sdio0;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	vcc12v_dc: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dc";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dc>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc1v8_s0: vcc1v8-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host";
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vbus_typec: vbus-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec_en>;
+		regulator-name = "vbus_typec";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_lan: vcc3v3-lan-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lan";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		pwm-supply = <&vcc5v0_sys>;
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+		pinctrl-names = "default";
+		pinctrl-0 = <&power_key>;
+
+		key-power {
+			debounce-interval = <100>;
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+			label = "GPIO Key Power";
+			linux,code = <KEY_POWER>;
+			wakeup-source;
+		};
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		vol-up-key {
+			label = "volume up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <1750>;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+	};
+
+	sound-dit {
+		compatible = "audio-graph-card";
+		label = "SPDIF";
+		dais = <&spdif_p0>;
+	};
+
+	spdif-dit {
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+
+		port {
+			dit_p0_0: endpoint {
+				remote-endpoint = <&spdif_p0_0>;
+			};
+		};
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc3v3_lan>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins &rgmii_phy_reset>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vcca0v9_hdmi>;
+	avdd-1v8-supply = <&vcca1v8_hdmi>;
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc5v0_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG1 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_hdmi: LDO_REG2 {
+				regulator-name = "vcca1v8_hdmi";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca_1v8: LDO_REG3 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca0v9_hdmi: LDO_REG7 {
+				regulator-name = "vcca0v9_hdmi";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc_cam: SWITCH_REG1 {
+				regulator-name = "vcc_cam";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_mipi: SWITCH_REG2 {
+				regulator-name = "vcc_mipi";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <0>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c1 {
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c4 {
+	i2c-scl-rising-time-ns = <600>;
+	i2c-scl-falling-time-ns = <20>;
+	status = "okay";
+};
+
+&i2s2 {
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+
+	bt656-supply = <&vcc1v8_s0>;		/* APIO2_VDD */
+	audio-supply = <&vcc1v8_s0>;		/* APIO5_VDD */
+	sdmmc-supply = <&vcc_sdio>;		/* SDMMC0_VDD */
+	gpio1830-supply = <&vcc_3v0>;		/* APIO4_VDD */
+};
+
+&pmu_io_domains {
+	status = "okay";
+
+	pmu1830-supply = <&vcc_1v8>;		/* PMUIO2_VDD */
+};
+
+&pcie_phy {
+	status = "disabled";
+};
+
+&pcie0 {
+	status = "disabled";
+};
+
+&pinctrl {
+	rockchip-key {
+		power_key: power-key {
+			rockchip,pins =
+				<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins =
+				<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb2 {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins =
+				<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb-typec {
+		vcc5v0_typec_en: vcc5v0-typec-en {
+			rockchip,pins =
+				<1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio0 {
+		sdio0_bus4: sdio0-bus4 {
+			rockchip,pins =
+				<2 RK_PC4 1 &pcfg_pull_up_20ma>,
+				<2 RK_PC5 1 &pcfg_pull_up_20ma>,
+				<2 RK_PC6 1 &pcfg_pull_up_20ma>,
+				<2 RK_PC7 1 &pcfg_pull_up_20ma>;
+		};
+
+		sdio0_cmd: sdio0-cmd {
+			rockchip,pins =
+				<2 RK_PD0 1 &pcfg_pull_up_20ma>;
+		};
+
+		sdio0_clk: sdio0-clk {
+			rockchip,pins =
+				<2 RK_PD1 1 &pcfg_pull_none_20ma>;
+		};
+	};
+
+	gmac {
+		rgmii_phy_reset: rgmii-phy-reset {
+			rockchip,pins =
+				<3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+	};
+
+	wifi {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins =
+				<0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wifi_host_wake_l: wifi-host-wake-l {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins =
+				<0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins =
+				<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins =
+				<0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&saradc {
+	status = "okay";
+
+	vref-supply = <&vcc_1v8>;
+};
+
+&sdhci {
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	clock-frequency = <100000000>;
+	sd-uhs-sdr104;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
+	vqmmc-supply = <&vcc_sdio>;
+	card-detect-delay = <800>;
+	status = "okay";
+};
+
+&sdio0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	bus-width = <4>;
+	max-frequency = <50000000>;
+	clock-frequency = <50000000>;
+	disable-wp;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	status = "okay";
+
+	brcmf: wifi@1 {
+		compatible = "brcm,bcm4329-fmac";
+		reg = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_l>;
+	};
+};
+
+&spdif {
+	spdif_p0: port {
+		spdif_p0_0: endpoint {
+			remote-endpoint = <&dit_p0_0>;
+		};
+	};
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;	/* Host wake BT */
+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;	/* BT wake Host, irq*/
+		max-speed = <1500000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_enable_h &bt_wake_l &bt_host_wake_l>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-fmx1-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-fmx1-pro.dts
new file mode 100644
index 000000000..2dafa6c95
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-fmx1-pro.dts
@@ -0,0 +1,931 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3399.dtsi"
+
+// gpio0:0xac
+// gpio1:0x2f
+// gpio2:0xb7
+// gpio3:0x17
+// gpio4:0xba
+
+// 0x01:GPIO_ACTIVE_LOW   0x00:GPIO_ACTIVE_HIGH
+
+// RK_PA0-RK_PA7:0x00-0x07
+// RK_PB0-RK_PB7:0x08-0x0f
+// RK_PC0-RK_PC7:0x10-0x17
+// RK_PD0-RK_PD7:0x18-0x1f
+
+// #define RK_FUNC_GPIO    0
+// #define RK_FUNC_1-7    1-7 
+
+// pcfg-pull-none:0xa3
+// pcfg-pull-up:0xa1
+
+/ {
+	model = "fmx1_pro Board";
+	compatible = "rockchip,fmx1_pro", "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdhci;
+		mmc2 = &sdio0;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	ramoops: ramoops@110000 {
+		compatible = "ramoops";
+        reg = <0x00 0x110000 0x00 0xf0000>;
+		record-size = <0x20000>;
+		console-size = <0x80000>;
+		ftrace-size = <0x00>;
+		pmsg-size = <0x50000>;
+	};
+
+    fiq_debugger: fiq-debugger {
+		compatible = "rockchip,fiq-debugger";
+		rockchip,serial-id = <2>;
+        rockchip,signal-irq = <182>;
+		rockchip,wake-irq = <0>;
+		rockchip,irq-mode-enable = <1>;
+		rockchip,baudrate = <1500000>; 
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart2c_xfer>;
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x00 0x8000000>;
+			linux,cma-default;
+		};
+	};
+
+    clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	vcc12v_dc: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dc";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dc>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+    vcc1v8_s0: vcc1v8-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s0";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&host_vbus_drv>;
+		regulator-name = "vcc5v0_host";
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vbus_typec: vbus-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec_en>;
+		regulator-name = "vbus_typec";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_sd: vcc-sd {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; // sch
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_sd_h>;
+		regulator-name = "vcc3v3_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc3v3_lan: vcc3v3-lan-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lan";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		pwm-supply = <&vcc5v0_sys>;
+	};
+
+    gpio-leds {
+		compatible = "gpio-leds";
+		autorepeat;
+		work {
+			gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
+			label = "r88:green:led";
+			pinctrl-names = "default";
+			pinctrl-0 = <&sys_led_pin>;
+		};
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		vol-up-key {
+			label = "volume up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <1750>;
+		};
+	};
+
+	test-power {
+		status = "okay";
+	};
+
+    spdif_sound: spdif-sound {
+		status = "okay";
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "ROCKCHIP,SPDIF";
+
+		simple-audio-card,cpu {
+			sound-dai = <&spdif>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&spdif_out>;
+		};
+	};
+
+	spdif_out: spdif-out {
+		status = "okay";
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+
+    sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; // sch
+	};
+
+    wireless_wlan: wireless-wlan {
+		compatible = "brcm,bcm4329-fmac";
+		rockchip,grf = <&grf>;
+		wifi_chip_type = "ap6354";
+		sdio_vref = <1800>;
+		WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	wireless_bluetooth: wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default","rts_gpio";
+		pinctrl-0 = <&uart0_rts>;
+		pinctrl-1 = <&uart0_gpios>;
+		BT,reset_gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		BT,wake_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+		BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&gpu {
+	status = "okay";
+	mali-supply = <&vdd_gpu>;
+};
+
+&saradc {
+	vref-supply = <&vcc1v8_s0>;
+	status = "okay";
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&sdio0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000000>;
+	clock-freq-min-max = <200000 100000000>;
+	supports-sdio;
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sdmmc {
+	clock-frequency = <100000000>;
+	clock-freq-min-max = <100000 100000000>;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	supports-sd;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	num-slots = <1>;
+	//sd-uhs-sdr104;
+	vqmmc-supply = <&vcc_sdio>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+	card-detect-delay = <800>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&gmac {
+	phy-supply = <&vcc3v3_lan>;
+	phy-mode = "rgmii";
+	clock_in_out = "input";
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&rgmii_pins>;
+	pinctrl-1 = <&rgmii_sleep_pins>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+	rockchip,grf = <&grf>;
+	bt656-supply = <&vcc1v8_s0>;		
+	audio-supply = <&vcc1v8_s0>;		
+	sdmmc-supply = <&vcc_sdio>;		
+	gpio1830-supply = <&vcc_3v0>;		
+};
+
+&pmu_io_domains {
+	status = "okay";
+    rockchip,grf = <&grf>;
+	pmu1830-supply = <&vcc_1v8>;
+};
+
+&pcie_phy {
+	status = "disabled";
+};
+
+&pcie0 {
+	status = "disabled";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	extcon = <&fusb0>;
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	rockchip,hw-tshut-temp = <120000>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+
+    vdd_cpu_b: syr827@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+        pinctrl-names = "default";
+		pinctrl-0 = <&vsel1_pin>;
+		regulator-compatible = "fan53555-reg";
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		fcs,suspend-voltage-selector = <0>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: syr828@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+        pinctrl-names = "default";
+		pinctrl-0 = <&vsel2_pin>;
+		regulator-compatible = "fan53555-reg";
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-initial-mode = <1>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+    rk808: pmic@1b { // checked
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc5v0_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG1 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_hdmi: LDO_REG2 {
+				regulator-name = "vcca1v8_hdmi";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca_1v8: LDO_REG3 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca0v9_hdmi: LDO_REG7 {
+				regulator-name = "vcca0v9_hdmi";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc_cam: SWITCH_REG1 {
+				regulator-name = "vcc_cam";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_mipi: SWITCH_REG2 {
+				regulator-name = "vcc_mipi";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2c1 {
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c4 {
+    status = "okay";
+    fusb0: fusb30x@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fusb0_int>;
+		vbus-5v-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_LOW>;
+		int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+};
+
+// &cdn_dp {
+// 	status = "okay";
+// 	extcon = <&fusb0>;
+// };
+
+// &hdmi_in_vopl {
+// 	status = "disabled";
+// };
+
+// &dp_in_vopb {
+// 	status = "disabled";
+// };
+
+// &route_hdmi {
+// 	status = "okay";
+// };
+
+&hdmi {
+	avdd-0v9-supply = <&vcca0v9_hdmi>;
+	avdd-1v8-supply = <&vcca1v8_hdmi>;
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+// &hdmi_dp_sound {
+// 	status = "okay";
+// };
+
+&pwm2 {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+	extcon = <&fusb0>;
+
+	u2phy0_host: host-port {
+		status = "okay";
+		phy-supply = <&vcc5v0_host>;
+	};
+
+    u2phy0_otg_port: host-otg {
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_host: host-port {
+		status = "okay";
+		phy-supply = <&vcc5v0_host>;
+	};
+
+    u2phy1_otg_port: host-otg {
+		status = "okay";
+	};
+};
+
+&tcphy0 {
+	extcon = <&fusb0>;
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&spdif {
+	pinctrl-0 = <&spdif_bus_1>;
+	status = "okay";
+	#sound-dai-cells = <0>;
+};
+
+// &i2s0 {
+// 	status = "okay";
+// 	rockchip,i2s-broken-burst-len;
+// 	rockchip,playback-channels = <8>;
+// 	rockchip,capture-channels = <8>;
+// 	#sound-dai-cells = <0>;
+// };
+
+// &i2s1 {
+// 	status = "disabled";
+// };
+
+&i2s2 {
+	rockchip,playback-channels = <2>;
+	rockchip,capture-channels = <2>;
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2c_xfer>;
+	status = "okay";
+};
+
+&pinctrl {
+
+	rockchip-key {
+		power_key: power-key {
+			rockchip,pins =
+				<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio0 {
+		sdio0-bus1 {
+			rockchip,pins = <2 20 1 &pcfg_pull_up_20ma>;
+		};
+
+		sdio0-bus4 {
+			rockchip,pins =
+				<2 20 1 &pcfg_pull_up_20ma>,
+				<2 21 1 &pcfg_pull_up_20ma>,
+				<2 22 1 &pcfg_pull_up_20ma>,
+				<2 23 1 &pcfg_pull_up_20ma>;
+		};
+
+		sdio0-cmd {
+			rockchip,pins = <2 24 1 &pcfg_pull_up_20ma>;
+		};
+
+		sdio0-clk {
+			rockchip,pins = <2 25 1 &pcfg_pull_up_20ma>;
+		};
+		
+	};
+
+	sdmmc {
+		sdmmc_bus1: sdmmc-bus1 {
+			rockchip,pins =
+				<4 8 1 &pcfg_pull_up_8ma>;
+		};
+
+		sdmmc_bus4: sdmmc-bus4 {
+			rockchip,pins =
+				<4 8 1 &pcfg_pull_up_8ma>,
+				<4 9 1 &pcfg_pull_up_8ma>,
+				<4 10 1 &pcfg_pull_up_8ma>,
+				<4 11 1 &pcfg_pull_up_8ma>;
+		};
+
+		sdmmc_clk: sdmmc-clk {
+			rockchip,pins =
+				<4 12 1 &pcfg_pull_none_18ma>;
+		};
+
+		sdmmc_cmd: sdmmc-cmd {
+			rockchip,pins =
+				<4 13 1 &pcfg_pull_up_8ma>;
+		};
+	};
+
+	leds {
+		sys_led_pin: sys-led-pin {
+			rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; // sch
+		};
+	};
+
+    sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+    wireless-bluetooth {
+		uart0_gpios: uart0-gpios {
+			rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+    usb2 {
+        host_vbus_drv: host-vbus-drv {
+			rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb-typec {
+		vcc5v0_typec_en: vcc5v0-typec-en {
+			rockchip,pins =
+				<1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	vcc_sd {
+		vcc_sd_h: vcc-sd-h {
+			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; // sch
+		};
+	};
+
+    pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+        vsel1_pin: vsel1-pin {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; // sch
+		};
+
+		vsel2_pin: vsel2-pin {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; // sch
+		};
+	};
+
+    fusb30x {
+		fusb0_int: fusb0-int {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+    gmac {
+		rgmii_sleep_pins: rgmii-sleep-pins {
+			rockchip,pins =<3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; // sch
+		};
+	};
+};
+
+&vopb {
+	assigned-clocks = <&cru DCLK_VOP0_DIV>;
+	assigned-clock-parents = <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	assigned-clocks = <&cru DCLK_VOP1_DIV>;
+	assigned-clock-parents = <&cru PLL_CPLL>;
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-hugsun-zm.dts b/arch/arm64/boot/dts/rockchip/rk3399-hugsun-zm.dts
new file mode 100644
index 000000000..2737b28bc
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-hugsun-zm.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+
+#include "rk3399-zcube1-max.dts"
+
+/ {
+	model = "Hugsun ZM-RK3399";
+	compatible = "hugsun,zm-rk3399", "rockchip,rk3399";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-king3399.dts b/arch/arm64/boot/dts/rockchip/rk3399-king3399.dts
new file mode 100644
index 000000000..30c1c4c86
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-king3399.dts
@@ -0,0 +1,1079 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3399.dtsi"
+
+/ {
+	model = "Rongpin King3399";
+	compatible = "rongpin,king3399", "rockchip,rk3399";
+
+	aliases {
+		led-boot = &breathe_led;
+		led-failsafe = &breathe_led;
+		led-running = &breathe_led;
+		led-upgrade = &breathe_led;
+		mmc0 = &sdio0;
+		mmc1 = &sdmmc;
+		mmc2 = &sdhci;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <100000>;
+		};
+
+		button-down {
+			label = "Volume Down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			press-threshold-microvolt = <300000>;
+		};
+
+		back {
+			label = "Back";
+			linux,code = <KEY_BACK>;
+			press-threshold-microvolt = <985000>;
+		};
+	};
+
+	keys: gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+
+		power {
+			debounce-interval = <100>;
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+			label = "GPIO Power";
+			linux,code = <KEY_RESTART>;
+			linux,input-type = <1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwr_btn>;
+			wakeup-source;
+		};
+	};
+
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ir_int>;
+	};
+
+	backlight: backlight {
+		status = "disabled";
+		compatible = "pwm-backlight";
+		brightness-levels = <
+			  0   1   2   3   4   5   6   7
+			  8   9  10  11  12  13  14  15
+			 16  17  18  19  20  21  22  23
+			 24  25  26  27  28  29  30  31
+			 32  33  34  35  36  37  38  39
+			 40  41  42  43  44  45  46  47
+			 48  49  50  51  52  53  54  55
+			 56  57  58  59  60  61  62  63
+			 64  65  66  67  68  69  70  71
+			 72  73  74  75  76  77  78  79
+			 80  81  82  83  84  85  86  87
+			 88  89  90  91  92  93  94  95
+			 96  97  98  99 100 101 102 103
+			104 105 106 107 108 109 110 111
+			112 113 114 115 116 117 118 119
+			120 121 122 123 124 125 126 127
+			128 129 130 131 132 133 134 135
+			136 137 138 139 140 141 142 143
+			144 145 146 147 148 149 150 151
+			152 153 154 155 156 157 158 159
+			160 161 162 163 164 165 166 167
+			168 169 170 171 172 173 174 175
+			176 177 178 179 180 181 182 183
+			184 185 186 187 188 189 190 191
+			192 193 194 195 196 197 198 199
+			200 201 202 203 204 205 206 207
+			208 209 210 211 212 213 214 215
+			216 217 218 219 220 221 222 223
+			224 225 226 227 228 229 230 231
+			232 233 234 235 236 237 238 239
+			240 241 242 243 244 245 246 247
+			248 249 250 251 252 253 254 255>;
+		default-brightness-level = <200>;
+		enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+		pwms = <&pwm0 0 25000 0>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_reg_on_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+	};
+
+	/* switched by pmic_sleep */
+	vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8>;
+	};
+
+	vcc3v0_sd: vcc3v0-sd {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc0_pwr_h>;
+		regulator-boot-on;
+		regulator-max-microvolt = <3000000>;
+		regulator-min-microvolt = <3000000>;
+		regulator-name = "vcc3v0_sd";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_gsm: vcc3v3-gsm {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_gsm_en>;
+		regulator-name = "vcc3v3_gsm";
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		regulator-boot-on;
+		gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_typec0: vbus-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec_en>;
+		regulator-name = "vcc5v0_typec0";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_sys: vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	dc_12v: vdd_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	rt5651-sound {
+		compatible = "simple-audio-card";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_det>;
+
+		simple-audio-card,name = "realtek,rt5651-codec";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,hp-det-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
+		simple-audio-card,aux-devs = <&speaker_amp>;
+		simple-audio-card,pin-switches = "Speaker";
+		simple-audio-card,widgets =
+			"Microphone", "Mic Jack",
+			"Headphone", "Headphones",
+			"Speaker", "Speaker";
+		simple-audio-card,routing =
+			"Mic Jack", "micbias1",
+			"Headphones", "HPOL",
+			"Headphones", "HPOR",
+			"Speaker Amplifier INL", "HPOL",
+			"Speaker Amplifier INR", "HPOR",
+			"Speaker", "Speaker Amplifier OUTL",
+			"Speaker", "Speaker Amplifier OUTR";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&rt5651>;
+		};
+	};
+
+	speaker_amp: speaker-amplifier {
+		compatible = "simple-audio-amplifier";
+		pinctrl-names = "default";
+		pinctrl-0 = <&spk_ctl>;
+		enable-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+		sound-name-prefix = "Speaker Amplifier";
+		VCC-supply = <&vcc5v0_sys>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&breathe_led_pin>;
+
+		breathe_led: led-breathe-led {
+			label = "breathe_led";
+			linux,default-trigger = "heartbeat";
+			default-state = "off";
+			gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	fan0: gpio-fan {
+		#cooling-cells = <2>;
+		compatible = "gpio-fan";
+		gpio-fan,speed-map = <0 0 3000 1>;
+		gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hub_rst>;
+		priority = <200>;
+		active-delay = <100>;
+		inactive-delay = <10>;
+		wait-delay = <100>;
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_thermal {
+	trips {
+		cpu_hot: cpu_hot {
+			hysteresis = <10000>;
+			temperature = <55000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map2 {
+			cooling-device =
+				<&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			trip = <&cpu_hot>;
+		};
+	};
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc3v3_s3>;
+	phy-mode = "rgmii";
+	phy-handle = <&rtl8211e>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rtl8211e: ethernet-phy@1 {
+			reg = <1>;
+			interrupt-parent = <&gpio3>;
+			interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <30000>;
+			reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2s0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s_8ch_mclk_pin>, <&i2s0_2ch_bus>;
+	#sound-dai-cells = <0>;
+	rockchip,capture-channels = <8>;
+	rockchip,playback-channels = <8>;
+	status = "okay";
+};
+
+&i2s2 {
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc5v0_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc1v8_pmu>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v0_tp: LDO_REG2 {
+				regulator-name = "vcc3v0_tp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: vcc_lan: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cpu_b_sleep>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpu_sleep>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c1 {
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+
+	rt5651: rt5651@1a {
+		#sound-dai-cells = <0>;
+		compatible = "realtek,rt5651";
+		reg = <0x1a>;
+		clocks = <&cru SCLK_I2S_8CH_OUT>;
+		clock-names = "mclk";
+		status = "okay";
+	};
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+
+	fusb302@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&chg_cc_int_l>;
+		vbus-supply = <&vcc5v0_typec0>;
+
+		typec_con: connector {
+			compatible = "usb-c-connector";
+			data-role = "host";
+			label = "USB-C";
+			op-sink-microwatt = <1000000>;
+			power-role = "dual";
+			sink-pdos =
+				<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
+			source-pdos =
+				<PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
+			try-power-role = "sink";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					typec_hs: endpoint {
+						remote-endpoint = <&u2phy0_typec_hs>;
+					};
+				};
+				port@1 {
+					reg = <1>;
+					typec_ss: endpoint {
+						remote-endpoint = <&tcphy0_typec_ss>;
+					};
+				};
+				port@2 {
+					reg = <2>;
+					typec_dp: endpoint {
+						remote-endpoint = <&tcphy0_typec_dp>;
+					};
+				};
+			};
+		};
+	};
+
+	mma8452: mma8452@1d {
+		compatible = "fsl,mma8452";
+		reg = <0x1d>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PC7 IRQ_TYPE_EDGE_RISING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gsensor_int>;
+	};
+};
+
+&io_domains {
+	status = "okay";
+	bt656-supply = <&vcc_1v8>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vcc_sdio>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmu1830-supply = <&vcc_1v8>;
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	status = "okay";
+};
+
+&pinctrl {
+	buttons {
+		pwr_btn: pwr-btn {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	fan {
+		motor_pwr: motor-pwr {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	ir {
+		ir_int: ir-int {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	gmac {
+		phy_intb: phy-intb {
+			rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_rstb: phy-rstb {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		cpu_b_sleep: cpu-b-sleep {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		gpu_sleep: gpu-sleep {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		pmic_dvs2: pmic-dvs2 {
+			rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	sd {
+		sdmmc0_pwr_h: sdmmc0-pwr-h {
+			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb2 {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_typec_en: vcc5v0-typec-en {
+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		hub_rst: hub-rst {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_reg_on_h: wifi-reg-on-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wifi {
+		wifi_host_wake_l: wifi-host-wake-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	bluetooth {
+		bt_reg_on_h: bt-enable-h {
+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	fusb302 {
+		chg_cc_int_l: chg-cc-int-l {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	leds {
+		breathe_led_pin: breathe-led-pin {
+			rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	gsm {
+		vcc3v3_gsm_en: vcc3v3-gsm-en {
+			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	headphone {
+		hp_det: hp-det {
+			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+		spk_ctl: spk-ctl {
+			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	mma8452 {
+		gsensor_int: gsensor-int {
+			rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	i2s0 {
+		i2s_8ch_mclk_pin: i2s-8ch-mclk-pin {
+			rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca1v8_s3>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&sdio0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	clock-frequency = <50000000>;
+	disable-wp;
+	keep-power-in-suspend;
+	max-frequency = <50000000>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	brcmf: wifi@1 {
+		reg = <1>;
+		compatible = "brcm,bcm43455-fmac";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+		interrupt-names = "host-wake";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_l>;
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	clock-frequency = <150000000>;
+	disable-wp;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+	vmmc-supply = <&vcc3v0_sd>;
+	vqmmc-supply = <&vcc_sdio>;
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy0_dp {
+	port {
+		tcphy0_typec_dp: endpoint {
+			remote-endpoint = <&typec_dp>;
+		};
+	};
+};
+
+&tcphy0_usb3 {
+	port {
+		tcphy0_typec_ss: endpoint {
+			remote-endpoint = <&typec_ss>;
+		};
+	};
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		phy-supply = <&vcc5v0_typec0>;
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+
+	port {
+		u2phy0_typec_hs: endpoint {
+			remote-endpoint = <&typec_hs>;
+		};
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk808 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>;
+		vbat-supply = <&vcc5v0_sys>;
+		vddio-supply = <&vcc_1v8>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart4 {
+	status = "okay";
+};
+
+&spi1 {
+	status = "disabled";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sv-33a6x.dts b/arch/arm64/boot/dts/rockchip/rk3399-sv-33a6x.dts
new file mode 100644
index 000000000..84b7ad9c9
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-sv-33a6x.dts
@@ -0,0 +1,777 @@
+/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3399.dtsi"
+#include "rk3399-op1.dtsi"
+
+/ {
+    model = "SV-33A6X";
+    compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
+
+    chosen {
+        stdout-path = "serial2:1500000n8";
+    };
+
+    
+    clkin_gmac: external-gmac-clock {
+        compatible = "fixed-clock";
+        clock-frequency = <125000000>;
+        clock-output-names = "clkin_gmac";
+        #clock-cells = <0>;
+    };
+    
+    gpio-leds {
+        compatible = "gpio-leds";
+
+    
+    };
+
+    vcca0v9_s3: regulator-vcca0v9-s3 {
+        compatible = "regulator-fixed";
+        regulator-min-microvolt = <900000>;
+        regulator-max-microvolt = <900000>;
+        regulator-name = "vcca0v9_s3";
+        vin-supply = <&vcc1v8_s3>;
+    };
+    
+    vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+        compatible = "regulator-fixed";
+        regulator-name = "vcc1v8_s3";
+        regulator-always-on;
+        regulator-boot-on;
+        regulator-min-microvolt = <1800000>;
+        regulator-max-microvolt = <1800000>;
+        vin-supply = <&vcc_1v8>;
+    };
+
+    vcc3v3_sys: vcc3v3-sys {
+        compatible = "regulator-fixed";
+        regulator-name = "vcc3v3_sys";
+        regulator-always-on;
+        regulator-boot-on;
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+    };
+
+    vcc5v0_host: vcc5v0-host-regulator {
+        compatible = "regulator-fixed";
+        enable-active-high;
+        gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&vcc5v0_host_en>;
+        regulator-name = "vcc5v0_host";
+        vin-supply = <&vcc5v0_sys>;
+    };
+
+    vcc5v0_sys: vcc5v0-sys {
+        compatible = "regulator-fixed";
+        regulator-name = "vcc5v0_sys";
+        regulator-always-on;
+        regulator-boot-on;
+        regulator-min-microvolt = <5000000>;
+        regulator-max-microvolt = <5000000>;
+    };
+    
+    vcc_phy: vcc-phy-regulator {
+        compatible = "regulator-fixed";
+        regulator-name = "vcc_phy";
+        regulator-always-on;
+        regulator-boot-on;
+    };
+    
+    vbus_typec: vbus-5vout {
+        compatible = "regulator-fixed";
+        enable-active-high;
+        gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&vcc5v0_typec0_en_pin>;
+        regulator-name = "vbus_5vout";
+        regulator-min-microvolt = <5000000>;
+        regulator-max-microvolt = <5000000>;
+        vin-supply = <&vcc5v0_sys>;
+
+        regulator-state-mem {
+            regulator-off-in-suspend;
+        };
+    };
+    
+    vdd_log: vdd-log {
+        compatible = "pwm-regulator";
+        pwms = <&pwm2 0 25000 1>;
+        regulator-name = "vdd_log";
+        regulator-min-microvolt = <800000>;
+        regulator-max-microvolt = <1400000>;
+        regulator-always-on;
+        regulator-boot-on;
+
+        /* for rockchip boot on */
+        rockchip,pwm_id= <2>;
+        rockchip,pwm_voltage = <900000>;
+    };
+    
+    xin32k: xin32k {
+        compatible = "fixed-clock";
+        clock-frequency = <32768>;
+        clock-output-names = "xin32k";
+        #clock-cells = <0>;
+    };
+     sound {
+        compatible = "audio-graph-card";
+        label = "Analog";
+        dais = <&i2s0_p0>;
+    };
+
+
+};
+
+&cdn_dp {
+    status = "okay";
+    extcon = <&fusb0>;
+};
+
+&cpu_l0 {
+    cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+    cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+    cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+    cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+    cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+    cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+    status = "okay";
+};
+
+&gmac {
+    assigned-clocks = <&cru SCLK_RMII_SRC>;
+    assigned-clock-parents = <&cru SCLK_MAC>;
+    clock_in_out = "input";
+    assigned-clock-rates = <125000000>;
+    phy-supply = <&vcc_phy>;
+    phy-mode = "rgmii";
+    pinctrl-names = "default";
+    pinctrl-0 = <&rgmii_pins>;
+    snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
+    snps,reset-active-low;
+    snps,reset-delays-us = <0 16000 72000>;
+    tx_delay = <0x25>;
+    rx_delay = <0x20>;
+    wakeup-enable = "0";
+    status = "okay";
+};
+&gpu {
+    mali-supply = <&vdd_gpu>;
+    status = "okay";
+};
+
+&hdmi {
+    ddc-i2c-bus = <&i2c3>;
+    status = "okay";
+};
+
+&hdmi_sound {
+    status = "okay";
+};
+
+&i2c0 {
+    status = "okay";
+
+    rk808: pmic@1b {
+        compatible = "rockchip,rk808";
+        reg = <0x1b>;
+        interrupt-parent = <&gpio1>;
+        interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pmic_int_l>, <&ap_pwroff>, <&clk_32k>;
+        #clock-cells = <1>;
+        clock-output-names = "rk808-clkout1", "rk808-clkout2";
+        rockchip,system-power-controller;
+        wakeup-source;
+
+        vcc1-supply = <&vcc5v0_sys>;
+        vcc2-supply = <&vcc5v0_sys>;
+        vcc3-supply = <&vcc5v0_sys>;
+        vcc4-supply = <&vcc5v0_sys>;
+        vcc6-supply = <&vcc5v0_sys>;
+        vcc7-supply = <&vcc5v0_sys>;
+        vcc8-supply = <&vcc3v3_sys>;
+        vcc9-supply = <&vcc5v0_sys>;
+        vcc10-supply = <&vcc5v0_sys>;
+        vcc11-supply = <&vcc5v0_sys>;
+        vcc12-supply = <&vcc3v3_sys>;
+        vddio-supply = <&vcc_1v8>;
+
+        regulators {
+            vdd_center: DCDC_REG1 {
+                regulator-name = "vdd_center";
+                regulator-min-microvolt = <750000>;
+                regulator-max-microvolt = <1350000>;
+                regulator-ramp-delay = <6001>;
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-state-mem {
+                    regulator-on-in-suspend;
+                    regulator-suspend-microvolt = <900000>;
+                };
+            };
+
+            vdd_cpu_l: DCDC_REG2 {
+                regulator-name = "vdd_cpu_l";
+                regulator-min-microvolt = <750000>;
+                regulator-max-microvolt = <1350000>;
+                regulator-ramp-delay = <6001>;
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-state-mem {
+                    regulator-off-in-suspend;
+                };
+            };
+
+            vcc_ddr: DCDC_REG3 {
+                regulator-name = "vcc_ddr";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-state-mem {
+                    regulator-on-in-suspend;
+                };
+            };
+
+            vcc_1v8: DCDC_REG4 {
+                regulator-name = "vcc_1v8";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-state-mem {
+                    regulator-on-in-suspend;
+                    regulator-suspend-microvolt = <1800000>;
+                };
+            };
+
+            vcc3v3_dsi: LDO_REG1 {
+                regulator-name = "vcc3v3_dsi";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-state-mem {
+                    regulator-off-in-suspend;
+                };
+            };
+
+            vcca1v8_hdmi: LDO_REG2 {
+                regulator-name = "vcca1v8_hdmi";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-state-mem {
+                    regulator-off-in-suspend;
+                };
+            };
+
+            vcc1v8_pmu: LDO_REG3 {
+                regulator-name = "vcc1v8_pmu";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-state-mem {
+                    regulator-on-in-suspend;
+                    regulator-suspend-microvolt = <1800000>;
+                };
+            };
+
+            vccio_sd: LDO_REG4 {
+                regulator-name = "vccio_sd";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-state-mem {
+                    regulator-on-in-suspend;
+                    regulator-suspend-microvolt = <3000000>;
+                };
+            };
+
+            vcc3v3_csi: LDO_REG5 {
+                regulator-name = "vcc3v3_csi";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-state-mem {
+                    regulator-off-in-suspend;
+                };
+            };
+
+            vcc_1v5: LDO_REG6 {
+                regulator-name = "vcc_1v5";
+                regulator-min-microvolt = <1500000>;
+                regulator-max-microvolt = <1500000>;
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-state-mem {
+                    regulator-on-in-suspend;
+                    regulator-suspend-microvolt = <1500000>;
+                };
+            };
+
+            vcca0v9_hdmi: LDO_REG7 {
+                regulator-name = "vcca0v9_hdmi";
+                regulator-min-microvolt = <900000>;
+                regulator-max-microvolt = <900000>;
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-state-mem {
+                    regulator-off-in-suspend;
+                };
+            };
+
+            vcc_3v0: LDO_REG8 {
+                regulator-name = "vcc_3v0";
+                regulator-min-microvolt = <3000000>;
+                regulator-max-microvolt = <3000000>;
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-state-mem {
+                    regulator-on-in-suspend;
+                    regulator-suspend-microvolt = <3000000>;
+                };
+            };
+
+            vcc3v3_s3: SWITCH_REG1 {
+                regulator-name = "vcc3v3_s3";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-state-mem {
+                    regulator-on-in-suspend;
+                };
+            };
+
+            vcc3v3_s0: SWITCH_REG2 {
+                regulator-name = "vcc3v3_s0";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-state-mem {
+                    regulator-off-in-suspend;
+                };
+            };
+        };
+    };
+
+    vdd_cpu_b: regulator@40 {
+        compatible = "silergy,syr827";
+        reg = <0x40>;
+        fcs,suspend-voltage-selector = <0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&vsel1_gpio>;
+        regulator-name = "vdd_cpu_b";
+        regulator-min-microvolt = <712500>;
+        regulator-max-microvolt = <1500000>;
+        regulator-ramp-delay = <1000>;
+        regulator-always-on;
+        regulator-boot-on;
+        vin-supply = <&vcc3v3_sys>;
+
+        regulator-state-mem {
+            regulator-off-in-suspend;
+        };
+    };
+
+
+        vdd_gpu: regulator@41 {
+        compatible = "silergy,syr828";
+        reg = <0x41>;
+        fcs,suspend-voltage-selector = <1>;
+        pinctrl-names = "default";
+        regulator-name = "vdd_gpu";
+        regulator-min-microvolt = <712500>;
+        regulator-max-microvolt = <1500000>;
+        regulator-ramp-delay = <1000>;
+        regulator-always-on;
+        regulator-boot-on;
+        vin-supply = <&vcc3v3_sys>;
+        regulator-state-mem {
+            regulator-off-in-suspend;
+        };
+    };
+    
+
+};
+
+&i2c3 {
+    status = "okay";
+};
+
+&i2c4 {
+
+    status = "okay";
+    i2c-scl-rising-time-ns = <475>;
+    i2c-scl-falling-time-ns = <26>;
+    fusb0: fusb30x@22 {
+        compatible = "fcs,fusb302";
+        reg = <0x22>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&fusb0_int>;
+        interrupt-parent = <&gpio1>;
+        interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+        vbus-supply = <&vbus_typec>;
+        status = "okay";
+        
+        connector {
+            compatible = "usb-c-connector";
+            data-role = "dual";
+            label = "USB-C";
+            op-sink-microwatt = <1000000>;
+            power-role = "dual";
+            sink-pdos =
+                <PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
+            source-pdos =
+                <PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
+            try-power-role = "sink";
+
+            extcon-cables = <1 2 5 6 9 10 12 44>;
+            typec-altmodes = <0xff01 1 0x001c0000 1>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+
+                    usbc_hs: endpoint {
+                        remote-endpoint =
+                            <&u2phy0_typec_hs>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+
+                    usbc_ss: endpoint {
+                        remote-endpoint =
+                            <&tcphy0_typec_ss>;
+                    };
+                };
+
+                port@2 {
+                    reg = <2>;
+
+                    usbc_dp: endpoint {
+                        remote-endpoint =
+                            <&tcphy0_typec_dp>;
+                    };
+                };
+            };
+        };
+        
+        
+        
+        
+    };
+    
+};    
+
+&i2c1 {
+    i2c-scl-rising-time-ns = <300>;
+    i2c-scl-falling-time-ns = <15>;
+    status = "okay";
+};
+
+
+&i2c1 {
+    es8316: codec@10 {
+        compatible = "everest,es8316";
+        reg = <0x10>;
+        clocks = <&cru SCLK_I2S_8CH_OUT>;
+        clock-names = "mclk";
+        #sound-dai-cells = <0>;
+
+        port {
+            es8316_p0_0: endpoint {
+                remote-endpoint = <&i2s0_p0_0>;
+            };
+        };
+    };
+};
+
+
+&i2c8 {
+
+    m24c08: m24c08@50 {
+        compatible = "atmel,24c08";
+        reg = <0x50>;
+    };
+};
+
+&i2s0 {
+    rockchip,playback-channels = <2>;
+    rockchip,capture-channels = <2>;
+    status = "okay";
+
+    i2s0_p0: port {
+        i2s0_p0_0: endpoint {
+            dai-format = "i2s";
+            mclk-fs = <256>;
+            remote-endpoint = <&es8316_p0_0>;
+        };
+    };
+};
+&i2s2 {
+    status = "okay";
+};
+
+&pcie_phy {
+    status = "okay";
+};
+
+&pcie0 {
+    ep-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+    num-lanes = <4>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&pcie_clkreqn_cpm>;
+    status = "okay";
+    vpcie0v9-supply = <&vcca0v9_s3>;
+    vpcie1v8-supply = <&vcca1v8_s3>;
+    vpcie3v3-supply = <&vcc3v3_sys>;
+};
+
+
+&pwm0 {
+    status = "disabled";
+};
+
+&pwm2 {
+    status = "okay";
+    pinctrl-names = "default";
+    pinctrl-0 = <&pwm2_pin_pull_down>;
+};
+
+&pwm3 {
+    status = "disabled";
+};
+
+&saradc {
+    status = "okay";
+};
+
+&sdhci {
+    bus-width = <8>;
+    mmc-hs200-1_8v;
+    supports-emmc;
+    //mmc-hs400-enhanced-strobe;
+    non-removable;
+    keep-power-in-suspend;
+    status = "okay";
+};
+
+&sdmmc {
+    clock-frequency = <150000000>;
+    clock-freq-min-max = <100000 150000000>;
+    supports-sd;
+    bus-width = <4>;
+    cap-mmc-highspeed;
+    cap-sd-highspeed;
+    disable-wp;
+    num-slots = <1>;
+    cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+    //sd-uhs-sdr104;
+    vmmc-supply = <&vcc3v3_s3>;
+    vqmmc-supply = <&vccio_sd>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&sdmmc_clk &sdmmc_cmd  &sdmmc_bus4>;
+    status = "okay";
+};
+
+
+&tcphy0 {
+    extcon = <&fusb0>;
+    status = "okay";
+};
+
+&tcphy0_dp {
+    port {
+        tcphy0_typec_dp: endpoint {
+            remote-endpoint = <&usbc_dp>;
+        };
+    };
+};
+
+&tcphy0_usb3 {
+    port {
+        tcphy0_typec_ss: endpoint {
+            remote-endpoint = <&usbc_ss>;
+        };
+    };
+};
+
+&tcphy1 {
+    status = "okay";
+};
+
+&tsadc {
+    /* tshut mode 0:CRU 1:GPIO */
+    rockchip,hw-tshut-mode = <1>;
+    /* tshut polarity 0:LOW 1:HIGH */
+    rockchip,hw-tshut-polarity = <1>;
+    status = "okay";
+};
+
+&u2phy0 {
+    status = "okay";
+
+    u2phy0_otg: otg-port {
+        status = "okay";
+    };
+
+    u2phy0_host: host-port {
+        phy-supply = <&vcc5v0_host>;
+        status = "okay";
+    };
+
+    port {
+        u2phy0_typec_hs: endpoint {
+            remote-endpoint = <&usbc_hs>;
+        };
+    };
+};
+
+&u2phy1 {
+    status = "okay";
+
+    u2phy1_otg: otg-port {
+        status = "okay";
+    };
+
+    u2phy1_host: host-port {
+        phy-supply = <&vcc5v0_host>;
+        status = "okay";
+    };
+};
+
+&usbdrd3_0 {
+    status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+    status = "okay";
+    dr_mode = "host";
+};
+
+&usbdrd3_1 {
+    status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+    status = "okay";
+    dr_mode = "host";
+};
+
+&uart2 {
+    status = "okay";
+};
+
+&usb_host0_ehci {
+    status = "okay";
+};
+
+&usb_host0_ohci {
+    status = "okay";
+};
+
+&usb_host1_ehci {
+    status = "okay";
+};
+
+&usb_host1_ohci {
+    status = "okay";
+};
+
+&pinctrl {
+
+    pmic {
+        pmic_int_l: pmic-int-l {
+            rockchip,pins =
+                <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
+                
+        };
+        vsel1_gpio: vsel1-gpio {
+            rockchip,pins =
+                <1 17 RK_FUNC_GPIO &pcfg_pull_down>;
+        };
+        vsel2_gpio: vsel2-gpio {
+            rockchip,pins =
+                <1 14 RK_FUNC_GPIO &pcfg_pull_down>;
+        };    
+    };
+
+    usb2 {
+        vcc5v0_host_en: vcc5v0-host-en {
+            rockchip,pins =
+                <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+        };
+    };
+    
+    usb-typec {
+        vcc5v0_typec0_en_pin: vcc5v0-typec0-en-pin {
+            rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+        };
+    };
+    
+    fusb30x {
+        fusb0_int: fusb0-int {
+            rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
+        };
+    };
+
+    pcie {
+        pcie_pwr_en: pcie-pwr-en {
+            rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+        };
+
+        pcie_perst: pcie-perst {
+            rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+        };
+    };
+
+    rockchip-key {
+        power_key: power-key {
+            rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+        };
+    };
+
+
+};
+
+&vopl {
+    status = "okay";    
+};
+
+&vopl_mmu {
+    status = "okay";
+};
+
+&vopb {
+    status = "okay";
+};
+
+&vopb_mmu {
+    status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-taram.dts b/arch/arm64/boot/dts/rockchip/rk3399-taram.dts
new file mode 100644
index 000000000..328111c77
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-taram.dts
@@ -0,0 +1,1261 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "rk3399.dtsi"
+
+/ {
+	model = "Rockchip RK3399";
+	compatible = "Tara,Tara-M", "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+		mmc2 = &sdio0;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc_12v: vcc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_12v";
+		regulator-always-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc1v8_s3: vcc1v8-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s3";
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host";
+	};
+
+	vcc_sd: vcc-sd {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sd";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_sd_h>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		enable-active-high;
+		gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_pwr_en>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcca1v8_s3: vcca1v8-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcca1v8_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcca0v9_s3: vcca0v9-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcca0v9_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc_1v8>;
+	};
+
+	vcc_lan: vcc3v3-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_lan";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	hdmi-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "hdmi-sound";
+		status = "okay";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s2>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&hdmi>;
+		};
+	};
+
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&leds_pins>;
+
+		system-led1 {
+			gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+			label = "system_led1";
+			retain-state-suspended;
+			linux,default-trigger = "default-on";
+			default-state = "on";
+		};
+//风扇GPIO目前写成LED控制，兼容飞牛，默认开启风扇		
+		system-led2 {
+			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+			label = "system_led1";
+			retain-state-suspended;
+			linux,default-trigger = "default-on";
+			default-state = "on";
+		};
+	};
+/*根据温度启停风扇，飞牛此配置无效。
+	fan0: gpio-fan {
+		#cooling-cells = <2>;
+		compatible = "gpio-fan";
+		gpio-fan,speed-map = <0 0 3000 1>;
+		gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};*/
+
+
+	wireless-wlan {
+		compatible = "wlan-platdata";
+		rockchip,grf = <&grf>;
+		wifi_chip_type = "rtl8822cs";
+		sdio_vref = <1800>;
+		//pinctrl-names = "default";
+        //pinctrl-0 = <&wifi_host_wake_irq>,<&wifi_enable_h>;
+		WIFI,host_wake_irq = <&gpio0 RK_PA3 0>; /* GPIO0_a3 */
+		//WIFI,poweren_gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		//clocks = <&rk808 1>;
+		//clock-names = "ext_clock";
+		uart_rts_gpios = <&gpio2 RK_PC3 1>; /* GPIO2_C3 */
+		pinctrl-names = "default", "rts_gpio";
+		//pinctrl-0 = <&uart0_rts>, <&bt_reset_gpio>, <&bt_irq_gpio>;
+		pinctrl-0 = <&uart0_rts>;
+		pinctrl-1 = <&uart0_gpios>;
+		BT,reset_gpio = <&gpio0 RK_PB1 0>; /* GPIO0_B1 */
+        BT,wake_gpio = <&gpio2 RK_PD3 0>; /* GPIO2_D2 */
+        BT,wake_host_irq = <&gpio0 RK_PA4 0>; /* GPIO0_A4 */
+		status = "okay";
+	};
+
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+/*根据温度启停风扇
+&cpu_thermal {
+	trips {
+		cpu_hot: cpu_hot {
+			hysteresis = <10000>;
+			temperature = <30000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map2 {
+			cooling-device =
+				<&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			trip = <&cpu_hot>;
+		};
+	};
+};
+*/
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc3v3_s3>;
+	phy-mode = "rgmii-id";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	tx_delay = <0x2a>;
+	rx_delay = <0x21>;
+	status = "okay";
+	label = "eth0";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vcca0v9_s3>;
+	avdd-1v8-supply = <&vcca1v8_s3>;
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+
+	vdd_cpu_b: syr827@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+		status = "okay";
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: syr828@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_3v0>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_hdmi: LDO_REG2 {
+				regulator-name = "vcca1v8_hdmi";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_pmupll: LDO_REG3 {
+				regulator-name = "vcc1v8_pmupll";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca0v9_hdmi: LDO_REG7 {
+				regulator-name = "vcca0v9_hdmi";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	hym8563: hym8563@51 {
+			status = "disabled";
+			compatible = "haoyu,hym8563";
+			reg = <0x51>;
+
+			irq_gpio = <&gpio1 RK_PC6 IRQ_TYPE_EDGE_FALLING>;
+			#clock-cells = <0x0>;
+			clock-frequency = <32768>;
+			clock-output-names = "hym8563_32k_to_rk808";
+		};
+
+};
+
+&i2s0 {
+	status = "okay";
+	rockchip,i2s-broken-burst-len;
+	rockchip,playback-channels = <8>;
+	rockchip,capture-channels = <8>;
+	#sound-dai-cells = <0>;
+};
+
+&i2c1 {
+	status = "disabled";
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <160>;
+	i2c-scl-falling-time-ns = <30>;
+	status = "disabled";
+
+	fusb0: fusb30x@22 {
+			status = "okay";
+			compatible = "fairchild,fusb302";
+			reg = <0x22>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&fusb0_int>;
+			int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+			vbus-5v-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+		};
+};
+// 电饭煲LED阵列控制，编译时候请在内核勾选is31fl32XX驱动
+&i2c6 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	is31fl3236: led-controller@3c {
+		compatible = "issi,is31fl3236";
+		reg = <0x3c>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+		//red
+		led1: led@1 {
+			label = "led1";
+			reg = <1>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <0>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+		//green
+		led2: led@2 {
+			label = "led2";
+			reg = <2>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <0>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+		//blue
+		led3: led@3 {
+			label = "led3";
+			reg = <3>;
+			led-max-microamp = <10000>;
+			linux,default-trigger = "default-on";
+		};
+		//red
+		led4: led@4 {
+			label = "led4";
+			reg = <4>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <100>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+		//green
+		led5: led@5 {
+			label = "led5";
+			reg = <5>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <100>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+		//blue
+		led6: led@6 {
+			label = "led6";
+			reg = <6>;
+			led-max-microamp = <10000>;
+			linux,default-trigger = "default-on";
+		};
+		//red
+		led7: led@7 {
+			label = "led7";
+			reg = <7>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <200>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+		//green
+		led8: led@8 {
+			label = "led8";
+			reg = <8>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <200>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+		//blue
+		led9: led@9 {
+			label = "led9";
+			reg = <9>;
+			led-max-microamp = <10000>;
+			linux,default-trigger = "default-on";
+		};
+		//red
+		led10: led@10 {
+			label = "led10";
+			reg = <10>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <300>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+		//green
+		led11: led@11 {
+			label = "led11";
+			reg = <11>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <300>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;;
+		};
+		//blue
+		led12: led@12 {
+			label = "led12";
+			reg = <12>;
+			led-max-microamp = <10000>;
+			linux,default-trigger = "default-on";
+		};
+
+		led13: led@13 {
+			label = "led13";
+			reg = <13>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <400>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led14: led@14 {
+			label = "led14";
+			reg = <14>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <400>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led15: led@15 {
+			label = "led15";
+			reg = <15>;
+			led-max-microamp = <10000>;
+			linux,default-trigger = "default-on";
+		};
+
+		led16: led@16 {
+			label = "led16";
+			reg = <16>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <500>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led17: led@17 {
+			label = "led17";
+			reg = <17>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <500>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led18: led@18 {
+			label = "led18";
+			reg = <18>;
+			led-max-microamp = <10000>;
+			linux,default-trigger = "default-on";
+		};
+
+		led19: led@19 {
+			label = "led19";
+			reg = <19>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <600>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led20: led@20 {
+			label = "led20";
+			reg = <20>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <600>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led21: led@21 {
+			label = "led21";
+			reg = <21>;
+			led-max-microamp = <10000>;
+			linux,default-trigger = "default-on";
+		};
+
+		led22: led@22 {
+			label = "led22";
+			reg = <22>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <700>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led23: led@23 {
+			label = "led23";
+			reg = <23>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <700>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led124: led@24 {
+			label = "led24";
+			reg = <24>;
+			led-max-microamp = <10000>;
+			linux,default-trigger = "default-on";
+		};
+
+		led25: led@25 {
+			label = "led25";
+			reg = <25>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <800>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led26: led@26 {
+			label = "led26";
+			reg = <26>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <800>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led27: led@27 {
+			label = "led27";
+			reg = <27>;
+			led-max-microamp = <10000>;
+			linux,default-trigger = "default-on";
+		};
+
+		led28: led@28 {
+			label = "led28";
+			reg = <28>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <900>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led29: led@29 {
+			label = "led29";
+			reg = <29>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <900>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led30: led@30 {
+			label = "led30";
+			reg = <30>;
+			led-max-microamp = <10000>;
+			linux,default-trigger = "default-on";
+		};
+
+		led31: led@31 {
+			label = "led31";
+			reg = <31>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <1000>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led32: led@32 {
+			label = "led32";
+			reg = <32>;
+			//led-max-microamp = <10000>;
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <1000>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led33: led@33 {
+			label = "led33";
+			reg = <33>;
+			led-max-microamp = <10000>;
+			linux,default-trigger = "default-on";
+		};
+
+		led34: led@34 {
+			label = "led34";
+			reg = <34>;
+			led-max-microamp = <10000>;
+			linux,default-trigger = "default-on";
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <1100>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led35: led@35 {
+			label = "led35";
+			reg = <35>;
+			led-max-microamp = <10000>;
+			linux,default-trigger = "default-on";
+			//linux,default-trigger = "timer";
+			//linux,default-trigger-delay-ms = <1100>;
+			//linux,blink-delay-on-ms = <100>;
+			//linux,blink-delay-off-ms = <1200>;
+		};
+
+		led36: led@36 {
+			label = "led36";
+			reg = <36>;
+			led-max-microamp = <10000>;
+			linux,default-trigger = "default-on";
+		};
+	};
+};
+
+&i2s1 {
+	status = "okay";
+	rockchip,i2s-broken-burst-len;
+	rockchip,playback-channels = <8>;
+	rockchip,capture-channels = <8>;
+	#sound-dai-cells = <0>;
+};
+
+&i2s2 {
+    status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+
+	bt656-supply = <&vcc_3v0>;
+	audio-supply = <&vcc_1v8>;
+	sdmmc-supply = <&vcc_sdio>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+&pcie0 {
+	ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+	reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
+	num-lanes = <4>;
+	max-link-speed = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_clkreqn_cpm &sata_en_h>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	//vpcie0v9-supply = <&vcca0v9_s3>;
+	//vpcie1v8-supply = <&vcca1v8_s3>;
+	status = "okay";
+};
+
+&pmu_io_domains {
+	status = "okay";
+
+	pmu1830-supply = <&vcc_1v8>;
+};
+
+&pinctrl {
+
+	rtc {
+		rtc_int: rtc-int {
+		rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+	pcie {
+		sata_en_h: sata-en-h {
+			rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>,
+					<4 RK_PD6 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+
+		pcie_pwr_en: pcie-pwr-en {
+			rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vsel1_pin: vsel1-pin {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		vsel2_pin: vsel2-pin {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	usb2 {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_typec_en: vcc5v0-typec-en {
+			rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+
+	};
+
+	vcc_sd {
+		vcc_sd_h: vcc-sd-h {
+			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	fusb30x {
+		fusb0_int: fusb0-int {
+			rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+        wifi_enable_h: wifi-enable-h {
+            rockchip,pins =
+                <0 RK_PB2 0 &pcfg_pull_none>;
+        };
+	};
+
+	wireless-bluetooth {
+        uart0_gpios: uart0-gpios {
+            rockchip,pins =
+                <2 RK_PC3 0 &pcfg_pull_none>;
+        };
+};
+
+	leds {
+		leds_pins: leds-pins {
+			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>,
+							<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	headphone {
+
+			hp_det: hp-det {
+				rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+
+			spk_con: spk-con {
+				rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+};
+
+	gmac {
+		phy_rst_l: phy-rst-l {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm3 {
+	status = "okay";
+	pinctrl-names = "active";
+};
+
+&saradc {
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	supports-emmc;
+	non-removable;
+	keep-power-in-suspend;
+	mmc-hs400-enhanced-strobe;
+	status = "okay";
+};
+
+&sdmmc {
+	clock-frequency = <150000000>;
+	clock-freq-min-max = <400000 150000000>;
+	supports-sd;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	num-slots = <1>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vcc_sdio>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+	status = "okay";
+};
+
+&sdio0 {
+    clock-frequency = <150000000>;
+	no-sd;
+	no-mmc;
+    supports-sdio;
+    bus-width = <4>;
+    disable-wp;
+    cap-sd-highspeed;
+    cap-sdio-irq;
+    keep-power-in-suspend;
+    mmc-pwrseq = <&sdio_pwrseq>;
+    non-removable;
+    num-slots = <1>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+    sd-uhs-sdr104;
+    status = "disabled";
+};
+
+&spi1 {
+	status = "disabled";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0x00>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+&tcphy0 {
+	extcon = <&fusb0>;
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+};
+
+&u2phy0 {
+	status = "okay";
+	extcon = <&fusb0>;
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+
+	u2phy0_otg: otg-port {
+		//vbus-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+    status = "okay";
+    phys = <&u2phy0_host>;
+    phy-names = "usb";
+};
+
+&usb_host0_ohci {
+    status = "okay";
+    phys = <&u2phy0_host>;
+    phy-names = "usb";
+};
+
+&usb_host1_ehci {
+    status = "okay";
+    phys = <&u2phy1_host>;
+    phy-names = "usb";
+};
+
+&usb_host1_ohci {
+    status = "okay";
+    phys = <&u2phy1_host>;
+    phy-names = "usb";
+};
+
+&usbdrd3_0{
+        status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	dr_mode = "otg";
+	status = "okay";
+	extcon = <&fusb0>;
+};
+
+&usbdrd3_1 {
+    status = "okay";
+};
+
+&cdn_dp {
+    compatible = "rockchip,rk3399-cdn-dp";
+    phys = <&tcphy0_dp>, <&tcphy1_dp>;
+    status = "disabled";
+};
+
+&usbdrd_dwc3_1 {
+    status = "okay";
+    dr_mode = "host";
+    phy-names = "usb2-phy", "usb3-phy";
+    phys = <&u2phy1_otg>, <&tcphy1_usb3>;
+};
+
+&rga {
+	status = "okay";
+};
+
+&vpu_mmu {
+	status = "okay";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-tb-ls3399.dts b/arch/arm64/boot/dts/rockchip/rk3399-tb-ls3399.dts
new file mode 100644
index 000000000..2e09c3108
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-tb-ls3399.dts
@@ -0,0 +1,659 @@
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+
+/ {
+	model = "RK3399 TB-LS3399";
+	compatible = "rockchip,rk3399-tb-ls3399", "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdhci;
+	};
+
+	// fiq_debugger: fiq-debugger {
+	// 	compatible = "rockchip,fiq-debugger";
+	// 	rockchip,serial-id = <2>;
+	// 	rockchip,signal-irq = <182>;
+	// 	rockchip,wake-irq = <0>;
+	// 	rockchip,irq-mode-enable = <1>;
+	// 	rockchip,baudrate = <1500000>;
+	// 	pinctrl-names = "default";
+	// 	pinctrl-0 = <&uart2c_xfer>;
+	// };
+
+	clkin_gmac: clkin-gmac {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc5v0_host: vcc5v0-host {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		enable-active-high;
+	};
+
+	vcc_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-min-microvolt = <3900000>;
+		regulator-max-microvolt = <3900000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_phy: vcc-phy {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_log: vdd-log  {
+		compatible = "pwm-regulator";
+		regulator-name = "vdd_log";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-min-microvolt = <750000>;
+		regulator-max-microvolt = <1350000>;
+		rockchip,pwm_voltage = <900000>;
+		rockchip,pwm_id = <2>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	usb_power: usb-power {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_power";
+		gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+	};
+
+	rt5651_sound: rt5651-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "realtek,rt5651-codec";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,widgets =
+			"Microphone", "Mic Jack",
+			"Headphone", "Headphone Jack";
+		simple-audio-card,routing =
+			"Mic Jack", "MICBIAS1",
+			"IN1P", "Mic Jack",
+			"Headphone Jack", "HPOL",
+			"Headphone Jack", "HPOR";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&rt5651>;
+		};
+	};
+
+	wireless_wlan: wireless-wlan {
+		compatible = "wlan-platdata";
+		rockchip,grf = <&grf>;
+		wifi_chip_type = "ap6212";
+		WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	ddc-i2c-bus = <&i2c3>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&gmac {
+	phy-supply = <&vcc_phy>;
+	phy-mode = "rgmii";
+	clock_in_out = "input";
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	tx_delay = <0x23>;
+	rx_delay = <0x26>;
+	status = "okay";
+};
+
+&i2c0 {
+	i2c-scl-rising-time-ns = <180>;
+	i2c-scl-falling-time-ns = <30>;
+	clock-frequency = <400000>;
+	status = "okay";
+
+	vdd_cpu_b: syr837@40 {
+		compatible = "silergy,syr827";
+		regulator-compatible = "fan53555-reg";
+		regulator-name = "vdd_cpu_b";
+		vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc_sys>;
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-initial-state = <3>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		reg = <0x40>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: syr828@41 {
+		compatible = "silergy,syr828";
+		regulator-compatible = "fan53555-reg";
+		regulator-name = "vdd_gpu";
+		vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc_sys>;
+		regulator-min-microvolt = <735000>;
+		regulator-max-microvolt = <1400000>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		reg = <0x41>;
+		status = "okay";
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc6-supply = <&vcc_sys>;
+		vcc7-supply = <&vcc_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc_sys>;
+		vcc10-supply = <&vcc_sys>;
+		vcc11-supply = <&vcc_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_3v0>;
+
+		regulators {
+
+			vdd_center: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-name = "vdd_center";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-name = "vdd_cpu_l";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_ddr";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc1v8_dvp";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			gps_vdd33: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "gps_vdd33";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc1v8_pmull: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc1v8_pmull";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sd: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcc_sd";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc2v8_dvp: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcc2v8_dvp";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-name = "vcc_1v5";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_codec";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcc_3v0";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_s3";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-name = "vcc3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2c1 {
+	i2c-scl-rising-time-ns = <140>;
+	i2c-scl-falling-time-ns = <30>;
+	status = "okay";
+
+	rt5651: rt5651@1a {
+		compatible = "rockchip,rt5651"; 
+		reg = <0x1a>;
+		clocks = <&cru SCLK_I2S_8CH_OUT>;
+		clock-names = "mclk";
+		hp-det-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
+		spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+		#sound-dai-cells = <0>;
+	};
+};
+
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	rockchip,defaultmode = <16>;
+	status = "okay";
+};
+
+&i2s1 {
+	rockchip,playback-channels = <8>;
+	rockchip,capture-channels = <8>;
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&i2s2 {
+	status = "okay";
+};
+
+&sdio0 {
+	num-slots = <1>;
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	disable-wp;
+	supports-sdio;
+	keep-power-in-suspend;
+	non-removable;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	status = "okay";
+};
+
+&sdmmc {
+	num-slots = <1>;
+	bus-width = <4>;
+	supports-sd;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+	vqmmc-supply = <&vcc_sd>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	supports-emmc;
+	non-removable;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	keep-power-in-suspend;
+	mmc-hs400-enhanced-strobe;
+	status = "okay";
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+&pcie0 {
+	num-lanes = <4>;
+	pinctrl-0 = <&pcie_clkreqnb_cpm>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&io_domains {
+	bt656-supply = <&vcc1v8_dvp>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vcc_sd>;
+	gpio1830-supply = <&vcc_3v0>;
+	status = "okay";
+};
+
+&pmu_io_domains {
+	pmu1830-supply = <&vcc_3v0>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <1>;
+	rockchip,hw-tshut-temp = <120000>;
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk808 1>;
+		clock-names = "lpo";
+		uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>;
+		BT,reset_gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		BT,wake_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+		BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&usbdrd3_0 {
+	extcon = <&u2phy0>;
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&vdec_mmu {
+	status = "okay";
+};
+
+&vpu_mmu {
+	status = "okay";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "disable";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-tn3399-v3.dts b/arch/arm64/boot/dts/rockchip/rk3399-tn3399-v3.dts
new file mode 100644
index 000000000..f4c73069e
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-tn3399-v3.dts
@@ -0,0 +1,888 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 retro98boy <retro98boy@qq.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+
+/ {
+	model = "TIANNUO TN3399_V3";
+	compatible = "tiannuo,tn3399-v3", "rockchip,rk3399";
+
+	aliases {
+		ethernet0 = &gmac;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+		mmc2 = &sdio0;
+		/*
+		 * Note: Since the voltage for the level converter between the rk3399 and hym8563 I2C communication is provided by the rk808 regulator,
+		 * the hym8563 driver can only be successfully probed if it is loaded after the rk808 regulator driver.
+		 */
+		rtc0 = &hym8563;
+		/*
+		 * The rk808 circuit design on this board does not have the ability to maintain real-time time after a power outage (battery R1110 NC).
+		 * Registering rk808 as rtc99 (most kernel configurations read time from rtc0) can prevent the kernel from reading the time (2013) from rk808 during startup.
+		 */
+		rtc99 = &rk808;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	/* Use the 2 pin LED connector (CN11) next to the 12v DC jack to connect the fan */
+	fan0: gpio-fan {
+		compatible = "gpio-fan";
+		gpio-fan,speed-map = <0 0 3000 1>;
+		gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+		#cooling-cells = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpio_fan_en>;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&sys_led>;
+
+		sys-led {
+			label = "sys-led";
+			gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	rt5640-sound {
+		compatible = "simple-audio-card";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_det>;
+		simple-audio-card,name = "rockchip,rt5640-codec";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,widgets =
+			"Microphone", "Internal Microphone",
+			"Headphone", "Headphones",
+			"Speaker", "Internal Speakers";
+		simple-audio-card,routing =
+			"Internal Microphone", "MICBIAS1",
+			"IN1P", "Internal Microphone",
+			"IN1N", "Internal Microphone",
+			"Headphones", "HPOL",
+			"Headphones", "HPOR",
+			"NS4258 INL", "SPOLP",
+			"NS4258 INL", "SPOLN",
+			"NS4258 INR", "SPORP",
+			"NS4258 INR", "SPORN",
+			"Internal Speakers", "NS4258 OUTL",
+			"Internal Speakers", "NS4258 OUTR";
+		simple-audio-card,hp-det-gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
+		simple-audio-card,aux-devs = <&speaker_amp>;
+		simple-audio-card,pin-switches = "Internal Speakers";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rt5640>;
+		};
+	};
+
+	speaker_amp: speaker-amp {
+		compatible = "simple-audio-amplifier";
+		pinctrl-names = "default";
+		pinctrl-0 = <&ns4258_en>;
+		enable-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+		sound-name-prefix = "NS4258";
+		VCC-supply = <&audio_5v>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+	};
+
+	dc12v: regulator-dc12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc12v>;
+	};
+
+	usb_vbus: regulator-usb-vbus {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec0_en>;
+		regulator-name = "usb_vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_sys: regulator-vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc12v>;
+	};
+
+	vcc3v0_sd: regulator-vcc3v0-sd {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc0_pwr_h>;
+		regulator-name = "vcc3v0_sd";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v6_lte: regulator-vcc3v6-lte {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v6_lte_en>;
+		regulator-name = "vcc3v6_lte";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3600000>;
+		regulator-max-microvolt = <3600000>;
+		vin-supply = <&dc12v>;
+	};
+
+	vcca1v8_s3: regulator-vcca1v8-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcca1v8_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcca0v9_s3: regulator-vcca0v9-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcca0v9_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc_1v8>;
+	};
+
+	vcc_lan: regulator-vcc-lan {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_lan";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vdd_log: regulator-vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		pwm-supply = <&vcc3v3_sys>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+	};
+
+	audio_5v: regulator-audio-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "audio_5v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_thermal {
+	trips {
+		cpu_hot: cpu_hot {
+			temperature = <55000>;
+			hysteresis = <5000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map2 {
+			trip = <&cpu_hot>;
+			cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clock-parents = <&clkin_gmac>;
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	clock_in_out = "input";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_rst_l>;
+	phy-handle = <&rtl8211e>;
+	phy-mode = "rgmii";
+	phy-supply = <&vcc_lan>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rtl8211e: rtl8211e@0 {
+			reg = <0>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <30000>;
+			reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vcca0v9_s3>;
+	avdd-1v8-supply = <&vcca1v8_s3>;
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;    /* Provide voltage to the level converter for hym8563 I2C communication */
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v0_touch: LDO_REG2 {
+				regulator-name = "vcc3v0_touch";
+				regulator-always-on;    /* Provide voltage to the level converter for hym8563 I2C communication */
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmupll: LDO_REG3 {
+				regulator-name = "vcc1v8_pmupll";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel1_pin>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel2_pin>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c1 {
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+
+	rt5640: rt5640@1c {
+		compatible = "realtek,rt5640";
+		reg = <0x1c>;
+		clocks = <&cru SCLK_I2S_8CH_OUT>;
+		clock-names = "mclk";
+		realtek,in1-differential;
+		#sound-dai-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ear_ctrl>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <300>;
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+	};
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2s0 {
+	status = "okay";
+};
+
+&i2s1 {
+	rockchip,playback-channels = <2>;
+	rockchip,capture-channels = <2>;
+	status = "okay";
+};
+
+&i2s2 {
+	status = "okay";
+};
+
+&io_domains {
+	bt656-supply = <&vcc1v8_dvp>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vcc_sdio>;
+	gpio1830-supply = <&vcc_3v0>;
+	status = "okay";
+};
+
+&pinctrl {
+	fan {
+		gpio_fan_en: gpio-fan-en {
+			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	gmac {
+		phy_rst_l: phy-rst-l {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rt5640 {
+		ear_ctrl: ear-ctrl {
+			rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+
+		hp_det: hp-det {
+			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		ns4258_en: ns4258-en {
+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		sys_led: sys-led {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	lte {
+		vcc3v6_lte_en: vcc3v6-lte-en {
+			rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vsel1_pin: vsel1-pin {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		vsel2_pin: vsel2-pin {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	sdmmc {
+		sdmmc0_pwr_h: sdmmc0-pwr-h {
+			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_typec0_en: vcc5v0-typec0-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wifi {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wifi_host_wake_l: wifi-host-wake-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmu1830-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca1v8_s3>;
+	status = "okay";
+};
+
+&sdhci {
+	max-frequency = <150000000>;
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&sdio0 {
+	bus-width = <4>;
+	clock-frequency = <50000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	brcmf: wifi@1 {
+		compatible = "brcm,bcm43455-fmac";
+		reg = <1>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "host-wake";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_l>;
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
+	vmmc-supply = <&vcc3v0_sd>;
+	vqmmc-supply = <&vcc3v0_sd>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&usb_vbus>;
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&usb_vbus>;
+		status = "okay";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm4345c5";
+		clocks = <&rk808 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-tpm312.dts b/arch/arm64/boot/dts/rockchip/rk3399-tpm312.dts
new file mode 100644
index 000000000..22b4c9c77
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-tpm312.dts
@@ -0,0 +1,1011 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include "rk3399.dtsi"
+
+/ {
+	model = "Rockchip TPM312";
+	compatible = "rockchip,tpm312","rockchip,rk3399";
+
+	aliases {
+		ethernet0 = &gmac;
+		mmc0 = &sdhci;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	/* switched by pmic_sleep */
+	vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc_phy";
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc5v0_host0: vcc5v0-host0-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host0_en>;
+		regulator-name = "vcc5v0_host0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_host1: vcc5v0-host1-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host1_en>;
+		regulator-name = "vcc5v0_host1";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_otg0: vcc5v0-otg0-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg0_en>;
+		regulator-name = "vcc5v0_otg0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_otg1: vcc5v0-otg1-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg1_en>;
+		regulator-name = "vcc5v0_otg1";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_lte: vcc3v3-lte-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_lte_en>;
+		regulator-name = "vcc3v3_lte";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_wifi: vcc3v3-wifi-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_wifi_en>;
+		regulator-name = "vcc3v3_wifi";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc5v0_usb1: vcc5v0-usb1-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb1_en>;
+		regulator-name = "vcc5v0_usb1";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb2: vcc5v0-usb2-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb2_en>;
+		regulator-name = "vcc5v0_usb2";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb3: vcc5v0-usb3-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb3_en>;
+		regulator-name = "vcc5v0_usb3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb4: vcc5v0-usb4-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb4_en>;
+		regulator-name = "vcc5v0_usb4";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb5: vcc5v0-usb5-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb5_en>;
+		regulator-name = "vcc5v0_usb5";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb6: vcc5v0-usb6-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb6_en>;
+		regulator-name = "vcc5v0_usb6";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_sys_en>;
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	leds: gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwr_led_pin>;
+		pwr_led: pwr-led {
+			label = "red:pwr_led";
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_LOW>; // bsp
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	// fan0: gpio-fan {
+	// 	#cooling-cells = <2>;
+	// 	compatible = "gpio-fan";
+	// 	gpio-fan,speed-map = <0 0 3000 1>;
+	// 	gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
+	// 	status = "okay";
+	// };
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+		pinctrl-names = "default";
+		pinctrl-0 = <&power_key>;
+
+		key-power {
+			debounce-interval = <100>;
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+			label = "GPIO Key Power";
+			linux,code = <KEY_POWER>;
+			wakeup-source;
+		};
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1750000>;
+		poll-interval = <100>;
+
+		recovery {
+			label = "Recovery";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <0>;
+		};
+	};
+
+	es8316-sound {
+		status = "okay";
+		compatible = "simple-audio-card";
+		pinctrl-names = "default";
+		// pinctrl-0 = <&hp_det>;
+
+		simple-audio-card,name = "rockchip,es8316-codec";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		// simple-audio-card,hp-det-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
+		simple-audio-card,aux-devs = <&speaker_amp>;
+		simple-audio-card,pin-switches = "Speaker";
+		simple-audio-card,widgets =
+			"Microphone", "Mic Jack",
+			// "Headphone", "Headphones",
+			"Speaker", "Speaker";
+		simple-audio-card,routing =
+			"Mic Jack", "Bias",
+			// "Headphones", "HPOL",
+			// "Headphones", "HPOR",
+			"Speaker Amplifier INL", "HPOL",
+			"Speaker Amplifier INR", "HPOR",
+			"Speaker", "Speaker Amplifier OUTL",
+			"Speaker", "Speaker Amplifier OUTR";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&es8316>;
+		};
+	};
+
+	speaker_amp: speaker-amplifier {
+		compatible = "simple-audio-amplifier";
+		pinctrl-names = "default";
+		pinctrl-0 = <&spk_ctl>;
+		enable-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; // spk-con-gpio
+		sound-name-prefix = "Speaker Amplifier";
+		vcc-supply = <&vcc5v0_sys>;
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+// &cpu_thermal {
+// 	trips {
+// 		cpu_hot: cpu_hot {
+// 			hysteresis = <10000>;
+// 			temperature = <55000>;
+// 			type = "active";
+// 		};
+// 	};
+
+// 	cooling-maps {
+// 		map2 {
+// 			cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+// 			trip = <&cpu_hot>;
+// 		};
+// 	};
+// };
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_phy>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_3v0>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc3v0_tp: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcc3v0_tp";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc3v0_sd: LDO_REG4 {
+				regulator-name = "vcc3v0_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cpu_b_sleep>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpu_sleep>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+// ES8316
+&i2c1 {
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+
+	es8316: codec@10 {
+		compatible = "everest,es8316";
+		reg = <0x10>;
+		clocks = <&cru SCLK_I2S_8CH_OUT>;
+		clock-names = "mclk";
+		#sound-dai-cells = <0>;
+
+		port {
+			es8316_p0_0: endpoint {
+				remote-endpoint = <&i2s0_p0_0>;
+			};
+		};
+	};
+};
+
+// Used for HDMI
+&i2c3 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c6 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c8 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2s0 {
+	rockchip,playback-channels = <2>;
+	rockchip,capture-channels = <2>;
+	status = "okay";
+	pinctrl-0 = <&i2s0_2ch_bus>;
+	pinctrl-1 = <&i2s0_2ch_bus_bclk_off>;
+
+
+	i2s0_p0: port {
+		i2s0_p0_0: endpoint {
+			dai-format = "i2s";
+			mclk-fs = <256>;
+			remote-endpoint = <&es8316_p0_0>;
+		};
+	};
+};
+
+&io_domains {
+	status = "okay";
+
+	bt656-supply = <&vcc1v8_dvp>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vcc3v0_sd>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmu1830-supply = <&vcc_3v0>;
+};
+
+&pinctrl {
+	panel {
+		bl_en: bl-en {
+			rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		mipi_rst: mipi-rst {
+			rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		mipi_en: mipi-en {
+			rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		vcc12v0_mipi_en: vcc12v0-mipi-en {
+			rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	pmic {
+		cpu_b_sleep: cpu-b-sleep {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+
+		gpu_sleep: gpu-sleep {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+
+		pmic_dvs2: pmic-dvs2 {
+			rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+	};
+
+	usb2 {
+		vcc5v0_host0_en: vcc5v0-host0-en {
+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		vcc5v0_host1_en: vcc5v0-host1-en {
+			rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		vcc5v0_otg0_en: vcc5v0-otg0-en {
+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		vcc5v0_otg1_en: vcc5v0-otg1-en {
+			rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		vcc3v3_lte_en: vcc3v3-lte-en {
+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		lte_rst: lte-rst {
+			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		vcc5v0_usb1_en: vcc5v0-usb1-en {
+			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		vcc5v0_usb2_en: vcc5v0-usb2-en {
+			rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		vcc5v0_usb3_en: vcc5v0-usb3-en {
+			rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		vcc5v0_usb4_en: vcc5v0-usb4-en {
+			rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		vcc5v0_usb5_en: vcc5v0-usb5-en {
+			rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		vcc5v0_usb6_en: vcc5v0-usb6-en {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	vcc {
+		vcc5v0_sys_en: vcc5v0-sys-en {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	wifi {
+		vcc3v3_wifi_en: vcc3v3-wifi-en {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	leds {
+		pwr_led_pin: pwr-led-pin {
+			rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	buttons {
+		power_key: power_key {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+	};
+
+	headphone {
+		spk_ctl: spk-ctl {
+			rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	func_gpio {
+		mpu6500_irq: mpu6500-irq {
+			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		touch_irq: touch-irq {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		touch_rst: touch-rst {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		isp_rst: isp-rst {
+			rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		wk2124_irq: wk2124-irq {
+			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		wk2_rst: wk2-rst {
+			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca1v8_s3>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	keep-power-in-suspend;
+	non-removable;
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy0_usb3 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		status = "okay";
+		phy-supply = <&vcc5v0_otg0>;
+	};
+
+	u2phy0_host: host-port {
+		status = "okay";
+		phy-supply = <&vcc5v0_host0>;
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+		phy-supply = <&vcc5v0_otg1>;
+	};
+
+	u2phy1_host: host-port {
+		status = "okay";
+		phy-supply = <&vcc5v0_host1>;
+	};
+};
+
+// Debug TTL
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&iep_mmu {
+	status = "okay";
+};
+
+&hdmi_in_vopb {
+	status = "disabled";
+};
+
+&hdmi_in_vopl{
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-tvi3315a.dts b/arch/arm64/boot/dts/rockchip/rk3399-tvi3315a.dts
new file mode 100644
index 000000000..78a125672
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-tvi3315a.dts
@@ -0,0 +1,919 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/input.h>
+#include "rk3399.dtsi"
+
+/ {
+	model = "TVI3315A RK3399 Board";
+	compatible = "rockchip,rk3399-tvi3315a", "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdio0;
+		mmc1 = &sdmmc;
+		mmc2 = &sdhci;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	backlight: backlight {
+		status = "disabled";
+		compatible = "pwm-backlight";
+		brightness-levels = <
+			  0   1   2   3   4   5   6   7
+			  8   9  10  11  12  13  14  15
+			 16  17  18  19  20  21  22  23
+			 24  25  26  27  28  29  30  31
+			 32  33  34  35  36  37  38  39
+			 40  41  42  43  44  45  46  47
+			 48  49  50  51  52  53  54  55
+			 56  57  58  59  60  61  62  63
+			 64  65  66  67  68  69  70  71
+			 72  73  74  75  76  77  78  79
+			 80  81  82  83  84  85  86  87
+			 88  89  90  91  92  93  94  95
+			 96  97  98  99 100 101 102 103
+			104 105 106 107 108 109 110 111
+			112 113 114 115 116 117 118 119
+			120 121 122 123 124 125 126 127
+			128 129 130 131 132 133 134 135
+			136 137 138 139 140 141 142 143
+			144 145 146 147 148 149 150 151
+			152 153 154 155 156 157 158 159
+			160 161 162 163 164 165 166 167
+			168 169 170 171 172 173 174 175
+			176 177 178 179 180 181 182 183
+			184 185 186 187 188 189 190 191
+			192 193 194 195 196 197 198 199
+			200 201 202 203 204 205 206 207
+			208 209 210 211 212 213 214 215
+			216 217 218 219 220 221 222 223
+			224 225 226 227 228 229 230 231
+			232 233 234 235 236 237 238 239
+			240 241 242 243 244 245 246 247
+			248 249 250 251 252 253 254 255>;
+		default-brightness-level = <200>;
+		enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; // bsp
+		pwms = <&pwm0 0 25000 0>;
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_reg_on_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; // bsp
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; // bsp 66
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_drv>;
+		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys { // bsp
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; // bsp 76
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_otg: vcc5v0-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; // bsp 154
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg_en>;
+		regulator-name = "vcc5v0_otg";
+		// regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0: vcc5v0-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; // bsp 12
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_en>;
+		regulator-name = "vcc5v0";
+		regulator-always-on;
+	};
+
+	vcc12v0: vcc12v0-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; // bsp 55
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc12v0_en>;
+		regulator-name = "vcc12v0";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-always-on;
+	};
+
+	vcc_sys: vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>; // bsp 3900000
+		regulator-max-microvolt = <5000000>; // bsp 3900000
+	};
+
+	vdd_log: vdd-log { // bsp
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		pwm-supply = <&vcc_sys>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&red_pin>, <&yellow_pin>;
+
+		red_led: red-led {
+			label = "red";
+			default-state = "off";
+			gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; // bsp 155
+		};
+		yellow_led: yellow-led {
+			label = "yellow";
+			default-state = "off";
+			gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; // bsp 34
+		};
+	};
+
+	/* Audio components */
+	es8316-sound {
+		status = "disabled";
+		compatible = "simple-audio-card";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_det_pin>;
+		simple-audio-card,name = "rockchip,es8316-codec";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,widgets =
+			"Microphone", "Mic Jack",
+			"Headphone", "Headphones",
+			"Speaker", "Speaker";
+		simple-audio-card,routing =
+			"MIC1", "Mic Jack",
+			"Headphones", "HPOL",
+			"Headphones", "HPOR",
+			"Speaker Amplifier INL", "HPOL",
+			"Speaker Amplifier INR", "HPOR",
+			"Speaker", "Speaker Amplifier OUTL",
+			"Speaker", "Speaker Amplifier OUTR";
+
+		simple-audio-card,hp-det-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+		// simple-audio-card,aux-devs = <&speaker_amp>;
+		// simple-audio-card,pin-switches = "Speaker";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&es8316>;
+		};
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+/*
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_phy>;
+	phy-mode = "rgmii";
+	phy-handle = <&rtl8211e>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rtl8211e: ethernet-phy@1 {
+			reg = <1>;
+			interrupt-parent = <&gpio3>;
+			interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <30000>;
+			reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+*/
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_phy>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; // bsp
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	tx_delay = <0x2a>;
+	rx_delay = <0x21>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <180>;
+	i2c-scl-falling-time-ns = <30>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>; // bsp
+		interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>; // bsp
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc1v8_pmu>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v0_tp: LDO_REG2 {
+				regulator-name = "vcc3v0_tp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cpu_b_sleep>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpu_sleep>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	// RTC
+	hym8563: hym8563@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+	};
+
+};
+
+// es8316
+&i2c1 {
+	i2c-scl-falling-time-ns = <30>;
+	i2c-scl-rising-time-ns = <140>;
+	status = "okay";
+
+	es8316: es8316@11 {
+		status = "disabled";
+		compatible = "everest,es8316";
+		reg = <0x11>;
+		clocks = <&cru SCLK_I2S_8CH_OUT>;
+		clock-names = "mclk";
+		#sound-dai-cells = <0>;
+	};
+};
+
+// Used for HDMI
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c6 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c7 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+// es8316
+&i2s0 {
+	pinctrl-names = "default";
+	// pinctrl-0 = <&i2s_8ch_mclk_pin>, <&i2s1_2ch_bus>;
+	rockchip,capture-channels = <8>;
+	rockchip,playback-channels = <8>;
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+	bt656-supply = <&vcc1v8_dvp>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vcc_sdio>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmu1830-supply = <&vcc_3v0>;
+};
+
+&pcie_phy {
+	status = "okay";
+};
+
+// USIM_RST <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; // bsp 42
+&pcie0 {
+	status = "okay";
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+};
+
+&pinctrl {
+	gmac {
+		phy_intb: phy-intb {
+			rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_rstb: phy-rstb {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		cpu_b_sleep: cpu-b-sleep {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		gpu_sleep: gpu-sleep {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+
+		pmic_dvs2: pmic-dvs2 {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+	};
+
+	usb2 {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		vcc5v0_otg_en: vcc5v0-otg-en {
+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_reg_on_h: wifi-reg-on-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	wifi {
+		wifi_host_wake_l: wifi-host-wake-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;  // bsp
+		};
+	};
+
+	bluetooth {
+		bt_reg_on_h: bt-enable-h {
+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+
+	leds {
+		red_pin: red-pin {
+			rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		yellow_pin: yellow-pin {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	pcie {
+		pcie_drv: pcie-drv {
+			rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		pcie_usim_rst: pcie-usim-rst {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	power {
+		vcc5v0_en: vcc5v0-en {
+			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		vcc12v0_en: vcc12v0-en {
+			rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		sata_pwr: sata-pwr {
+			rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	lcd {
+		lcd_bl_en: lcd-bl-en {
+			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	es8316 {
+		hp_det_pin: hp-det-pin {
+			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+	};
+
+	misc {
+		vibrator_gpio: vibrator-gpio {
+			rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+	};
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&saradc {
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	keep-power-in-suspend;
+	non-removable;
+	status = "okay";
+};
+
+&sdio0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	clock-frequency = <50000000>;
+	disable-wp;
+	keep-power-in-suspend;
+	max-frequency = <50000000>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	brcmf: wifi@1 {
+		reg = <1>;
+		compatible = "brcm,bcm43455-fmac";
+		// compatible = "brcm,bcm4329-fmac";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; // bsp
+		interrupt-names = "host-wake";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_l>;
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; // bsp
+	clock-frequency = <150000000>;
+	disable-wp;
+	sd-uhs-sdr104;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+	vqmmc-supply = <&vcc_sdio>;
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+&u2phy0_otg {
+	phy-supply = <&vcc5v0_otg>;
+	status = "okay";
+};
+&u2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_otg>;
+	status = "okay";
+};
+&u2phy1_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+	status = "okay";
+
+	bluetooth {
+		// compatible = "brcm,bcm43438-bt";
+		// max-speed = < 1500000 >;
+		compatible = "brcm,bcm4345c5";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;  // bsp
+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;  // bsp
+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; // bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+	};
+};
+
+// Debug TTL
+&uart2 {
+	status = "okay";
+};
+
+&uart4 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-xiaobao.dts b/arch/arm64/boot/dts/rockchip/rk3399-xiaobao.dts
new file mode 100644
index 000000000..0eed7d08f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-xiaobao.dts
@@ -0,0 +1,779 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3399.dtsi"
+
+/ {
+	model = "Codinge Xiaobao NAS";
+	compatible = "codinge,xiaobao-nas", "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdhci;
+		mmc2 = &sdio0;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc_dc: vcc-dc {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_12v: vcc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_12v";
+		regulator-always-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc1v8_s3: vcc1v8-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s3";
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host";
+	};
+
+	vcc_sd: vcc-sd {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sd";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_sd_h>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc5v0_typec: vcc5v0-typec {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec_en>;
+		regulator-name = "vcc5v0_typec";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_12v>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_pwr_en>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc_lan: vcc3v3-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_lan";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		recovery {
+			label = "Recovery";
+			linux,code = <0x168>;
+			press-threshold-microvolt = <18000>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&leds_pins>;
+
+		led1: system-led1 {
+			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+			label = "system_led1";
+			retain-state-suspended;
+			default-state = "on";
+		};
+
+		led2: system-led2 {
+			gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;
+			label = "system_led2";
+			retain-state-suspended;
+			default-state = "off";
+		};
+	};
+
+	pwm-fan {
+		compatible = "pwm-fan";
+		pwms = <&pwm1 0 50000 0>;
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+	freq-sel = <200000000>;
+	dr-sel = <100>;
+	opdelay = <4>;
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_lan>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	ddc-i2c-scl-high-time-ns = <9625>;
+	ddc-i2c-scl-low-time-ns = <10000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_3v0>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG2 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_pmupll: LDO_REG3 {
+				regulator-name = "vcc1v8_pmupll";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel1_pin>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel2_pin>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	hym8563@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+	};
+};
+
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <160>;
+	i2c-scl-falling-time-ns = <30>;
+	status = "okay";
+
+	typec-portc@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fusb0_int>;
+		vbus-supply = <&vcc5v0_typec>;
+	};
+};
+
+&i2s0 {
+	rockchip,capture-channels = <8>;
+	rockchip,playback-channels = <8>;
+	status = "okay";
+};
+
+&i2s1 {
+	rockchip,capture-channels = <2>;
+	rockchip,playback-channels = <2>;
+	status = "okay";
+};
+
+&i2s2 {
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+
+	bt656-supply = <&vcc_3v0>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vcc_sdio>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pcie_phy {
+	status = "okay";
+	drive-impedance-ohm = <50>;
+};
+
+&pcie0 {
+	ep-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+	num-lanes = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_clkreqnb_cpm &fn8274_en_h>;
+	status = "okay";
+};
+
+&pmu_io_domains {
+	status = "okay";
+
+	pmu1830-supply = <&vcc_3v0>;
+};
+
+&pinctrl {
+	pcie {
+		fn8274_en_h: fn8274-en-h {
+			rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_output_high>,
+					<4 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>,
+					<1 RK_PC7 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+
+		pcie_pwr_en: pcie-pwr-en {
+			rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vsel1_pin: vsel1-pin {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		vsel2_pin: vsel2-pin {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	usb2 {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_typec_en: vcc5v0-typec-en {
+			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+	};
+
+	vcc_sd {
+		vcc_sd_h: vcc-sd-h {
+			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	fusb30x {
+		fusb0_int: fusb0-int {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		leds_pins: leds-pins {
+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+					<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&saradc {
+	status = "okay";
+};
+
+&sdio0 {
+	bus-width = <4>;
+	clock-frequency = <50000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vcc_sdio>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	supports-emmc;
+	non-removable;
+	keep-power-in-suspend;
+
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0x00>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
+&u2phy1_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-yskj.dts b/arch/arm64/boot/dts/rockchip/rk3399-yskj.dts
new file mode 100644
index 000000000..61b70dd89
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-yskj.dts
@@ -0,0 +1,1029 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright: Hacking QQ: 1031146367
+/dts-v1/;
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/input.h>
+#include "rk3399.dtsi"
+
+/ {
+	model = "RK3399 YSKJ";
+	compatible = "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdio0;
+		mmc1 = &sdmmc;
+		mmc2 = &sdhci;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-always-on;
+		regulator-boot-on;
+		rockchip,pwm_id = <2>;
+		rockchip,pwm_voltage = <1000000>;
+	};
+	vcc_lcd: vcc-lcd {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_lcd";
+		gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <20000>;
+		enable-active-high;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+	vcc1v8_sys: vccadc-ref {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+	//应该没驱动
+	wdg_sp7x: wdg {
+		compatible = "wdg_sp7x";
+		power-supply = <&vcc_lcd>;
+		fdg-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>;
+		delay_us = <500>;
+		status = "okay";
+	};
+
+	gpio_keys: gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		autorepeat;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwrbtn>;
+
+		button: button@0 {
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+			label = "GPIO Key Power";
+			linux,input-type = <1>;
+			gpio-key,wakeup = <1>;
+			debounce-interval = <100>;
+		};
+	};
+	gpio_leds: gpio-leds {
+		compatible = "gpio-leds";
+
+		red {
+			gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
+			label = "red-led";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_ctl_red>;
+			default-state = "off";
+		};
+
+		green {
+			gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
+			label = "green-led";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_ctl_green>;
+			default-state = "off";
+		};
+
+		blue {
+			gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
+			label = "blue-led";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_ctl_blue>;
+			default-state = "on";
+		};
+	};
+	adc_keys: adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		poll-interval = <100>;
+		keyup-threshold-microvolt = <1800000>;
+
+		button-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <100000>;
+		};
+
+		button-down {
+			label = "Volume Down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			press-threshold-microvolt = <300000>;
+		};
+
+		back {
+			label = "Back";
+			linux,code = <KEY_BACK>;
+			press-threshold-microvolt = <985000>;
+		};
+
+		menu {
+			label = "Menu";
+			linux,code = <KEY_MENU>;
+			press-threshold-microvolt = <1314000>;
+		};
+	};
+	//todo,完善声卡
+	/*
+	rt5651_sound: rt5651-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "realtek,rt5651-codec";
+		simple-audio-card,mclk-fs = <0x100>;
+		simple-audio-card,widgets = "Microphone", "Mic Jack", "Headphone", "Headphone Jack";
+		simple-audio-card,routing = "Mic Jack", "MICBIAS1", "IN1P", "Mic Jack", "Headphone Jack", "HPOL", "Headphone Jack", "HPOR";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rt5651>;
+		};
+	};*/
+
+	spdif-sound {
+		status = "okay";
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "ROCKCHIP,SPDIF";
+
+		simple-audio-card,cpu {
+			sound-dai = <&spdif>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&spdif_out>;
+		};
+	};
+
+	spdif_out: spdif-out {
+		status = "okay";
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0x00>;
+	};
+	/*
+	wireless_wlan: wireless-wlan {
+		compatible = "wlan-platdata";
+		rockchip,grf = <&grf>;
+		wifi_chip_type = "ap6354";
+		sdio_vref = <1800>;
+		WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};*/
+/*
+	wireless_bluetooth: wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default\0rts_gpio";
+		pinctrl-0 = <&uart0_rts>;
+		pinctrl-1 = <&uart0_gpios>;
+		BT,reset_gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		BT,wake_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+		BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};*/
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+	};
+};
+&pinctrl {
+	buttons {
+		pwrbtn: pwrb-tn {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+	leds {
+		led_ctl_red: led-ctl-red {
+			rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	
+		led_ctl_green: led-ctl-green {
+			rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	
+		led_ctl_blue: led-ctl-blue {
+			rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+	wireless-bluetooth {
+		uart0_gpios: uart0-gpios {
+			rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	
+		pmic_dvs2: pmic-dvs2 {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	
+		vsel1_gpio: vsel1-gpio {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	
+		vsel2_gpio: vsel2-gpio {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+	wifi {
+		wifi_host_wake_l: wifi-host-wake-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_phy>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; // bsp
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	tx_delay = <0x35>;
+	rx_delay = <0x29>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	status = "okay";
+};
+&hdmi_in_vopb {
+	status = "okay";
+};
+&vopb_out_hdmi {
+	status = "okay";
+};
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc5v0_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc5v0_sys>;
+		vcc12-supply = <&vcc5v0_sys>;
+		vddio-supply = <&vcc_3v0>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v0_tp: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vcc3v0_tp";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sd: LDO_REG4 {
+				regulator-name = "vcc_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		regulator-compatible = "fan53555-reg";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel1_gpio>;
+		vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		regulator-compatible = "fan53555-reg";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel2_gpio>;
+		vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+&i2c4 {
+	status = "okay";
+	i2c-scl-rising-time-ns = <600>;
+	i2c-scl-falling-time-ns = <20>;
+	//没电再说
+	/*
+	fusb30x@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x85>;
+		int-n-gpios = <0x34 0x02 0x00>;
+		vbus-5v-gpios = <0x3f 0x00 0x00>;
+		status = "okay";
+		phandle = <0x27>;
+	};
+	mpu6500@68 {
+		status = "okay";
+		compatible = "invensense,mpu6500";
+		reg = <0x68>;
+		irq-gpio = <0x34 0x16 0x01>;
+		mpu-int_config = <0x10>;
+		mpu-level_shifter = <0x00>;
+		mpu-orientation = <0x00 0x01 0x00 0x01 0x00 0x00 0x00 0x00 0x01>;
+		orientation-x = <0x01>;
+		orientation-y = <0x00>;
+		orientation-z = <0x00>;
+		mpu-debug = <0x01>;
+	};*/
+};
+
+
+// Used for HDMI
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+// HDMI sound
+&i2s2 {
+	#sound-dai-cells = <0>;
+	status = "okay";
+	//assigned-clocks = <0x08 0xb0>;
+	//assigned-clock-parents = <0x08 0x05>;
+};
+
+&io_domains {
+	status = "okay";
+
+	bt656-supply = <&vcc1v8_dvp>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vcc_sd>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmu1830-supply = <&vcc_3v0>;
+};
+
+
+/*
+// TFT
+&pwm0 {
+	status = "okay";
+};
+*/
+
+&pwm2 {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcc1v8_sys>;
+	status = "okay";
+};
+
+&sdio0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	clock-frequency = <50000000>;
+	disable-wp;
+	keep-power-in-suspend;
+	max-frequency = <50000000>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	/*
+	wireless_wlan: wireless-wlan {
+		compatible = "wlan-platdata";
+		rockchip,grf = <&grf>;
+		wifi_chip_type = "ap6354";
+		sdio_vref = <1800>;
+		WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};*/
+	brcmf: wifi@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+		interrupt-names = "host-wake";
+		brcm,drive-strength = <5>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_l>;
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	//cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; // 没有
+	clock-frequency = <150000000>;
+	disable-wp;
+	sd-uhs-sdr104;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+	vqmmc-supply = <&vcc_sd>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	keep-power-in-suspend;
+	non-removable;
+	supports-emmc;
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		status = "okay";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+	status = "okay";
+/*
+	wireless_bluetooth: wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default\0rts_gpio";
+		pinctrl-0 = <&uart0_rts>;
+		pinctrl-1 = <&uart0_gpios>;
+		BT,reset_gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		BT,wake_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+		BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};*/
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk808 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		max-speed = <4000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+	};
+};
+
+// Debug TTL
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+	//dr_mode = "otg";//原设备树
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&iep_mmu {
+	status = "okay";
+};
+/*
+i2c@ff110000 {
+	compatible = "rockchip,rk3399-i2c";
+	reg = <0x00 0xff110000 0x00 0x1000>;
+	clocks = <0x08 0x41 0x08 0x155>;
+	clock-names = "i2c\0pclk";
+	interrupts = <0x00 0x3b 0x04 0x00>;
+	pinctrl-names = "default";
+	pinctrl-0 = <0x39>;
+	#address-cells = <0x01>;
+	#size-cells = <0x00>;
+	status = "okay";
+	i2c-scl-rising-time-ns = <0x12c>;
+	i2c-scl-falling-time-ns = <0x0f>;
+
+	rt5651@1a {
+		#sound-dai-cells = <0x00>;
+		compatible = "rockchip,rt5651";
+		reg = <0x1a>;
+		clocks = <0x08 0x59>;
+		clock-names = "mclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x3a>;
+		spk-con-gpio = <0x3b 0x0b 0x00>;
+		hp-det-gpios = <0x3c 0x1c 0x01>;
+		phandle = <0xd0>;
+	};
+
+	gsl3673@40 {
+		compatible = "GSL,GSL3673";
+		reg = <0x40>;
+		screen_max_x = <0x600>;
+		screen_max_y = <0x800>;
+		irq_gpio_number = <0x34 0x14 0x08>;
+		rst_gpio_number = <0x3c 0x16 0x00>;
+	};
+
+	camera-module@60 {
+		status = "disabled";
+		compatible = "ovti,ov7750-v4l2-i2c-subdev";
+		reg = <0x60>;
+		device_type = "v4l2-i2c-subdev";
+		clocks = <0x08 0x89>;
+		clock-names = "clk_cif_out";
+		pinctrl-names = "rockchip,camera_default\0rockchip,camera_sleep";
+		pinctrl-0 = <0x3d>;
+		pinctrl-1 = <0x3e>;
+		rockchip,pwr-gpio = <0x3f 0x0a 0x00>;
+		rockchip,camera-module-mclk-name = "clk_cif_out";
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "cmk-cb0695-fv1";
+		rockchip,camera-module-len-name = "lg9569a2";
+		rockchip,camera-module-fov-h = "133.0";
+		rockchip,camera-module-fov-v = "100.1";
+		rockchip,camera-module-orientation = <0x00>;
+		rockchip,camera-module-iq-flip = <0x00>;
+		rockchip,camera-module-iq-mirror = <0x00>;
+		rockchip,camera-module-flip = <0x00>;
+		rockchip,camera-module-mirror = <0x00>;
+		rockchip,camera-module-defrect0 = <0x280 0x1e0 0x00 0x00 0x280 0x1e0>;
+		rockchip,camera-module-defrect1 = <0x280 0x1e0 0x00 0x00 0x280 0x1e0>;
+		rockchip,camera-module-defrect2 = <0x280 0x1e0 0x00 0x00 0x280 0x1e0>;
+		rockchip,camera-module-defrect3 = <0x280 0x1e0 0x00 0x00 0x280 0x1e0>;
+		rockchip,camera-module-flash-support = <0x00>;
+		rockchip,camera-module-mipi-dphy-index = <0x00>;
+		phandle = <0xd5>;
+	};
+
+	camera-module@1 {
+		status = "disabled";
+		compatible = "toshiba,tc358749xbg-v4l2-i2c-subdev";
+		reg = <0x0f>;
+		device_type = "v4l2-i2c-subdev";
+		clocks = <0x08 0x89>;
+		clock-names = "clk_cif_out";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x40>;
+		power-gpios = <0x3f 0x06 0x00>;
+		power18-gpios = <0x3f 0x09 0x00>;
+		power33-gpios = <0x3f 0x05 0x00>;
+		csi-ctl-gpios = <0x3f 0x0a 0x00>;
+		stanby-gpios = <0x3f 0x08 0x00>;
+		reset-gpios = <0x3f 0x07 0x00>;
+		int-gpios = <0x3f 0x0c 0x00>;
+		rockchip,camera-module-mclk-name = "clk_cif_out";
+		rockchip,camera-module-mipi-dphy-index = <0x00>;
+		phandle = <0xd6>;
+	};
+
+	camera-module@10 {
+		status = "disabled";
+		compatible = "omnivision,ov13850-v4l2-i2c-subdev";
+		reg = <0x10>;
+		device_type = "v4l2-i2c-subdev";
+		clocks = <0x08 0x89>;
+		clock-names = "clk_cif_out";
+		pinctrl-names = "rockchip,camera_default\0rockchip,camera_sleep";
+		pinctrl-0 = <0x3d>;
+		pinctrl-1 = <0x3e>;
+		rockchip,pd-gpio = <0x34 0x04 0x01>;
+		rockchip,rst-gpio = <0x3f 0x0a 0x01>;
+		rockchip,camera-module-mclk-name = "clk_cif_out";
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "cmk-cb0695-fv1";
+		rockchip,camera-module-len-name = "lg9569a2";
+		rockchip,camera-module-fov-h = "66.0";
+		rockchip,camera-module-fov-v = "50.1";
+		rockchip,camera-module-orientation = <0x00>;
+		rockchip,camera-module-iq-flip = <0x00>;
+		rockchip,camera-module-iq-mirror = <0x00>;
+		rockchip,camera-module-flip = <0x01>;
+		rockchip,camera-module-mirror = <0x00>;
+		rockchip,camera-module-defrect0 = <0x840 0x620 0x00 0x00 0x840 0x620>;
+		rockchip,camera-module-defrect1 = <0x1080 0xc40 0x00 0x00 0x1080 0xc40>;
+		rockchip,camera-module-defrect3 = <0xcc0 0x990 0x00 0x00 0xcc0 0x990>;
+		rockchip,camera-module-flash-support = <0x01>;
+		rockchip,camera-module-mipi-dphy-index = <0x00>;
+		phandle = <0xd7>;
+	};
+
+	camera-module@36 {
+		status = "disabled";
+		compatible = "omnivision,ov4689-v4l2-i2c-subdev";
+		reg = <0x36>;
+		device_type = "v4l2-i2c-subdev";
+		clocks = <0x08 0x89>;
+		clock-names = "clk_cif_out";
+		pinctrl-names = "rockchip,camera_default\0rockchip,camera_sleep";
+		pinctrl-0 = <0x3d>;
+		pinctrl-1 = <0x3e>;
+		rockchip,rst-gpio = <0x3f 0x0a 0x01>;
+		rockchip,camera-module-mclk-name = "clk_cif_out";
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "LA6111PA";
+		rockchip,camera-module-len-name = "YM6011P";
+		rockchip,camera-module-fov-h = "116";
+		rockchip,camera-module-fov-v = "61";
+		rockchip,camera-module-orientation = <0x00>;
+		rockchip,camera-module-iq-flip = <0x00>;
+		rockchip,camera-module-iq-mirror = <0x00>;
+		rockchip,camera-module-flip = <0x00>;
+		rockchip,camera-module-mirror = <0x01>;
+		rockchip,camera-module-defrect0 = <0xa80 0x5f0 0x00 0x00 0xa80 0x5f0>;
+		rockchip,camera-module-flash-support = <0x00>;
+		rockchip,camera-module-mipi-dphy-index = <0x00>;
+		phandle = <0xd8>;
+	};
+};
+*/
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-zcube1-max.dts b/arch/arm64/boot/dts/rockchip/rk3399-zcube1-max.dts
new file mode 100644
index 000000000..c5544df84
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-zcube1-max.dts
@@ -0,0 +1,946 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "rk3399-op1.dtsi"
+
+/ {
+	model = "ZCuble1 Max";
+	compatible = "rockchip,rk3399-zcube1-max", "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdhci;
+		mmc2 = &sdio0;
+		rtc0 = &hym8563;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwrbtn>;
+
+		key-power {
+			debounce-interval = <100>;
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+			label = "GPIO Key Power";
+			linux,code = <KEY_POWER>;
+			wakeup-source;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&power_led_pin>;
+		status = "okay";
+
+		power_led: led-power {
+			label = "white:power";
+			gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+			linux,default-trigger = "default-on";
+		};
+	};
+
+	vcc12v_dcin: regulator-vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc5v0_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc1v8_s0: regulator-vcc1v8-s0 { // bsp
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s0";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc3v3_sys: regulator-vcc3v3-sys { // bsp
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb_phy: regulator-vcc5v0-usb-phy {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_phy_en>;
+		regulator-name = "vcc5v0_usb_phy";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vdd_log: regulator-vdd-log { // bsp
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-min-microvolt = <400000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc5v0_hdmi: regulator-vcc5v0-hdmi-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; // bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&hdmi_power_en>;
+		regulator-name = "vcc5v0_hdmi";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_reg_on_h>;
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; // bsp
+	};
+
+	es8323_sound: es8323-sound {
+		status = "okay";
+		compatible = "simple-audio-card";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_det_pin>;
+
+		simple-audio-card,name = "es8323";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,hp-det-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
+		simple-audio-card,aux-devs = <&speaker_amp>, <&headphones_amp>;
+		simple-audio-card,pin-switches = "Speaker", "Headphones";
+		simple-audio-card,widgets =
+			"Microphone", "Mic Jack",
+			"Headphone", "Headphones",
+			"Speaker", "Speaker";
+		simple-audio-card,routing =
+			"RINPUT1", "Mic Jack",
+			"LINPUT1", "Mic Jack",
+			"Headphone Amp INL", "LOUT1",
+			"Headphone Amp INR", "ROUT1",
+			"Headphones", "Headphone Amp OUTL",
+			"Headphones", "Headphone Amp OUTR",
+			"Speaker Amp INL", "LOUT1",
+			"Speaker Amp INR", "ROUT1",
+			"Speaker", "Speaker Amp OUTL",
+			"Speaker", "Speaker Amp OUTR";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&es8323>;
+		};
+	};
+
+	/* not amplifier, used as switcher only */
+	headphones_amp: headphones-amp {
+		compatible = "simple-audio-amplifier";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_con_pin>;
+		enable-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
+		sound-name-prefix = "Headphone Amp";
+		VCC-supply = <&vcc5v0_sys>;
+	};
+
+	speaker_amp: analog-amplifier@1 {
+		compatible = "simple-audio-amplifier";
+		pinctrl-names = "default";
+		pinctrl-0 = <&spk_ctl_pin>;
+		enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_LOW>;
+		sound-name-prefix = "Speaker Amp";
+		VCC-supply = <&vcc5v0_sys>;
+	};
+
+	// UART4: RX -> SDA, TX -> SCL
+	i2c9 {
+		compatible = "i2c-gpio";
+		sda-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+		scl-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
+		i2c-gpio,delay-us = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&crypto1 {
+	status = "disabled";
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc3v3_sys>;
+	phy-mode = "rgmii";
+	phy-handle = <&rtl8211f>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_rstb>;
+	tx_delay = <0x1b>;
+	rx_delay = <0x1a>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rtl8211f: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+
+			/*
+			 * RTL8211F Custom LED Mode B
+			 * LED1 (Green):  Link 10/100/1000
+			 * LED2 (Yellow): Active 10/100/1000
+			 */
+			realtek,led-data = <0xc160>;
+
+			reset-assert-us = <20000>;
+			reset-deassert-us = <100000>;
+			reset-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&gpu {
+	status = "okay";
+	mali-supply = <&vdd_gpu>;
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vcca0v9_hdmi>;
+	avdd-1v8-supply = <&vcca1v8_hdmi>;
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+/*
+dp-det-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+hdmi-5v-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+*/
+
+// &cdn_dp {
+// 	status = "okay";
+// };
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-falling-time-ns = <30>;
+	i2c-scl-rising-time-ns = <180>;
+	status = "okay";
+
+	vdd_cpu_b: syr827@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-compatible = "fan53555-reg";
+		pinctrl-0 = <&vsel1_pin>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: syr828@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-compatible = "fan53555-reg";
+		pinctrl-0 = <&vsel2_pin>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc5v0_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <13500000>;
+				regulator-ramp-delay = <6001>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_hdmi: LDO_REG2 {
+				regulator-name = "vcca1v8_hdmi";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG3 {
+				regulator-name = "vcca_1v8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sd: LDO_REG4 {
+				regulator-name = "vcc_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca3v0_sd: LDO_REG5 {
+				regulator-name = "vcca3v0_sd";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca0v9_hdmi: LDO_REG7 {
+				regulator-name = "vcca0v9_hdmi";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2c1 {
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+
+	es8323: es8323@10 {
+		compatible = "everest,es8328", "everest,es8323";
+		reg = <0x10>;
+		clock-names = "mclk";
+		clocks = <&cru SCLK_I2S_8CH_OUT>;
+		#sound-dai-cells = <0>;
+	};
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <RK_PB7 IRQ_TYPE_EDGE_FALLING>; // bsp
+		#clock-cells = <0>;
+		clock-output-names = "xin32k";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+	};
+};
+
+/* RGB Light */
+&i2c2 {
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+
+	aw2028@65 { // no driver
+		compatible = "awinic,aw2028_i2c";
+		reg = <0x65>;
+		// status = "okay";
+		status = "disabled";
+
+	};
+
+	aw2015@64 { // no driver
+		compatible = "awinic,aw2015_led";
+		reg = <0x64>;
+		status = "disabled";
+
+		aw2015,blue {
+			aw2015,name = "blue";
+			aw2015,id = <0>;
+			aw2015,imax = <3>;
+			aw2015,led-current = <255>;
+			aw2015,max-brightness = <255>;
+			aw2015,rise-time-ms = <10>;
+			aw2015,hold-time-ms = <7>;
+			aw2015,fall-time-ms = <10>;
+			aw2015,off-time-ms = <2>;
+		};
+		aw2015,green {
+			aw2015,name = "green";
+			aw2015,id = <1>;
+			aw2015,imax = <3>;
+			aw2015,led-current = <255>;
+			aw2015,max-brightness = <255>;
+			aw2015,rise-time-ms = <9>;
+			aw2015,hold-time-ms = <6>;
+			aw2015,fall-time-ms = <9>;
+			aw2015,off-time-ms = <1>;
+		};
+		aw2015,red {
+			aw2015,name = "red";
+			aw2015,id = <2>;
+			aw2015,imax = <3>;
+			aw2015,led-current = <255>;
+			aw2015,max-brightness = <255>;
+			aw2015,rise-time-ms = <8>;
+			aw2015,hold-time-ms = <5>;
+			aw2015,fall-time-ms = <8>;
+			aw2015,off-time-ms = <0>;
+		};
+	};
+};
+
+// HDMI
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c4 {
+	i2c-scl-rising-time-ns = <600>;
+	i2c-scl-falling-time-ns = <40>;
+	status = "okay";
+};
+
+// es8323
+&i2s1 {
+	rockchip,playback-channels = <2>;
+	rockchip,capture-channels = <2>;
+	status = "okay";
+};
+
+// HDMI sound
+&i2s2 {
+	rockchip,playback-channels = <2>;
+	rockchip,capture-channels = <2>;
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+	audio-supply = <&vcc1v8_s0>;
+	bt656-supply = <&vcc1v8_s0>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmu1830-supply = <&vcc_1v8>;
+};
+
+&pinctrl {
+	buttons {
+		pwrbtn: pwrbtn {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	es8323 {
+		/* speaker ctrl */
+		spk_ctl_pin: spk-ctl-pin {
+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+
+		/* headphone ctrl */
+		hp_con_pin: hp-con-pin {
+			rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		/* detect headphone */
+		hp_det_pin: hp-det-pin {
+			rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	gmac {
+		phy_rstb: phy-rstb {
+			rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		power_led_pin: power-led-pin {
+			rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins =
+				<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vsel1_pin: vsel1-pin {
+			rockchip,pins =
+				<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		vsel2_pin: vsel2-pin {
+			rockchip,pins =
+				<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	sdio {
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_reg_on_h: bt-reg-on-h {
+			/* external pullup to VCC1V8_PMUPLL */
+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wifi_reg_on_h: wifi-reg_on-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	wifi {
+		wifi_host_wake_l: wifi-host-wake-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	usb {
+		vcc5v0_usb_phy_en: vcc5v0-usb-phy-en {
+			rockchip,pins =
+				<1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	hdmi {
+		hdmi_power_en: hdmi-power-en {
+			rockchip,pins =
+				<1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+	};
+
+	i2s0 {
+		i2s_8ch_mclk_pin: i2s-8ch-mclk-pin {
+			rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>; // bsp
+		};
+	};
+};
+
+&pwm0 {
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcc1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	supports-emmc;
+	non-removable;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&sdio0 {
+	bus-width = <4>;
+	clock-frequency = <50000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "disabled";
+
+	brcmf: wifi@1 {
+		compatible = "brcm,bcm4329-fmac";
+		reg = <1>;
+		interrupt-parent = <&gpio0>; // bsp
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "host-wake";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_l>;
+		status = "disabled";
+	};
+};
+
+&tcphy0 {
+	status = "okay";
+	phy-supply = <&vcc5v0_usb_phy>;
+};
+
+&tcphy1 {
+	status = "okay";
+	phy-supply = <&vcc5v0_usb_phy>;
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	usb3_hub: usb3-hub@1 {
+		compatible = "usb5e3,626";
+		reg = <1>;
+	};
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	rockchip,hw-tshut-temp = <110000>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_host: host-port {
+		//phy-supply = <&vcc5v0_usb_phy>;
+		status = "disabled";
+	};
+
+	u2phy0_otg: otg-port {
+		phy-supply = <&vcc5v0_usb_phy>;
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_host: host-port {
+		//phy-supply = <&vcc5v0_usb_phy>;
+		status = "disabled";
+	};
+
+	u2phy1_otg: otg-port {
+		phy-supply = <&vcc5v0_usb_phy>;
+		status = "okay";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usb2_hub: usb2-hub@1 {
+			compatible = "usb5e3,626";
+			reg = <1>;
+		};
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; // bsp
+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		max-speed = <4000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+		status = "disabled";
+	};
+};
+
+// Debug TTL
+&uart2 {
+	status = "okay";
+};
+
+&uart4 {
+	// status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "disabled";
+};
+
+&usb_host0_ohci {
+	status = "disabled";
+};
+
+&usb_host1_ehci {
+	status = "disabled";
+};
+
+&usb_host1_ohci {
+	status = "disabled";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-zysj.dts b/arch/arm64/boot/dts/rockchip/rk3399-zysj.dts
new file mode 100644
index 000000000..1465d4a01
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-zysj.dts
@@ -0,0 +1,1187 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3399.dtsi"
+// 降频opp
+// #include "rk3399-t-opp.dtsi"
+
+/ {
+	model = "ZYSJ RK3399";
+	compatible = "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdio0;
+		mmc1 = &sdmmc;
+		mmc2 = &sdhci;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		brightness-levels = <
+			  0   1   2   3   4   5   6   7
+			  8   9  10  11  12  13  14  15
+			 16  17  18  19  20  21  22  23
+			 24  25  26  27  28  29  30  31
+			 32  33  34  35  36  37  38  39
+			 40  41  42  43  44  45  46  47
+			 48  49  50  51  52  53  54  55
+			 56  57  58  59  60  61  62  63
+			 64  65  66  67  68  69  70  71
+			 72  73  74  75  76  77  78  79
+			 80  81  82  83  84  85  86  87
+			 88  89  90  91  92  93  94  95
+			 96  97  98  99 100 101 102 103
+			104 105 106 107 108 109 110 111
+			112 113 114 115 116 117 118 119
+			120 121 122 123 124 125 126 127
+			128 129 130 131 132 133 134 135
+			136 137 138 139 140 141 142 143
+			144 145 146 147 148 149 150 151
+			152 153 154 155 156 157 158 159
+			160 161 162 163 164 165 166 167
+			168 169 170 171 172 173 174 175
+			176 177 178 179 180 181 182 183
+			184 185 186 187 188 189 190 191
+			192 193 194 195 196 197 198 199
+			200 201 202 203 204 205 206 207
+			208 209 210 211 212 213 214 215
+			216 217 218 219 220 221 222 223
+			224 225 226 227 228 229 230 231
+			232 233 234 235 236 237 238 239
+			240 241 242 243 244 245 246 247
+			248 249 250 251 252 253 254 255>;
+		default-brightness-level = <200>;
+		enable-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; // bsp
+		pwms = <&pwm0 0 25000 0>;
+		// status = "okay";
+		status = "disabled";
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_reg_on_h>;
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; // bsp
+	};
+
+	vcc_phy: vcc-phy-regulator { // bsp
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc1v8_s0: vcc1v8-s0 { // bsp
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	/* switched by pmic_sleep */
+	vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { // ?
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8>;
+	};
+
+	vcc3v3_sd: vcc3v0-sd {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; // bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc0_pwr_h>;
+		regulator-boot-on;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "vcc3v3_sd";
+		vin-supply = <&vcc3v3_sys>;
+		};
+
+	vcc3v3_sys: vcc3v3-sys { // bsp
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; // bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host";
+		regulator-always-on;
+	};
+
+	vbus_typec: vbus-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; //bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec_en>;
+		regulator-name = "vbus_typec";
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_sys: vcc-sys { // bsp
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; //bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_en>;
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vdd_log: vdd-log { // bsp
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+/*
+	// Unused DSI
+	vcc_lcd: vcc-lcd { // bsp
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd_panel_reset>;
+		regulator-boot-on;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "vcc_lcd";
+		startup-delay-us = <20000>;
+		vin-supply = <&vcc_sys>;
+	};
+*/
+
+	rt5651-sound {
+		// status = "okay";
+		status = "disabled";
+		compatible = "simple-audio-card";
+		pinctrl-names = "default";
+		pinctrl-0 = <&rt5651_hpdet>;
+
+		simple-audio-card,name = "realtek,rt5651-codec";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,hp-det-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
+		simple-audio-card,aux-devs = <&speaker_amp>;
+		simple-audio-card,pin-switches = "Speaker";
+		simple-audio-card,widgets =
+			"Microphone", "Mic Jack",
+			"Headphone", "Headphones",
+			"Speaker", "Speaker";
+		simple-audio-card,routing =
+			"Mic Jack", "micbias1",
+			"Headphones", "HPOL",
+			"Headphones", "HPOR",
+			"Speaker Amplifier INL", "HPOL",
+			"Speaker Amplifier INR", "HPOR",
+			"Speaker", "Speaker Amplifier OUTL",
+			"Speaker", "Speaker Amplifier OUTR";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&rt5651>;
+		};
+	};
+
+	speaker_amp: speaker-amplifier {
+		compatible = "simple-audio-amplifier";
+		pinctrl-names = "default";
+		pinctrl-0 = <&rt5651_spkcon>;
+		enable-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+		sound-name-prefix = "Speaker Amplifier";
+		// VCC-supply = <&vcc5v0_sys>;
+		status = "disabled";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwrbtn>;
+
+		key-power {
+			debounce-interval = <100>;
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; // bsp
+			label = "GPIO Key Power";
+			linux,code = <KEY_POWER>;
+			wakeup-source;
+		};
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		vol-up {
+				label = "Volume Up";
+				linux,code = <KEY_VOLUMEUP>;
+				press-threshold-microvolt = <18000>;
+		};
+		vol-down {
+				label = "Volume Down";
+				linux,code = <KEY_VOLUMEDOWN>;
+				press-threshold-microvolt = <18000>;
+		};
+		power {
+				label = "Power";
+				linux,code = <KEY_POWER>;
+				press-threshold-microvolt = <18000>;
+		};
+		menu {
+				label = "Menu";
+				linux,code = <KEY_F1>;
+				press-threshold-microvolt = <18000>;
+		};
+		home {
+				label = "Home";
+				linux,code = <KEY_HOME>;
+				press-threshold-microvolt = <18000>;
+		};
+		back {
+				label = "Back";
+				linux,code = <KEY_BACK>;
+				press-threshold-microvolt = <18000>;
+		};
+		camera {
+				label = "Camera";
+				linux,code = <KEY_CAMERA>;
+				press-threshold-microvolt = <18000>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&sys_led_pin>;
+
+		sys_led: sys-led {
+			label = "system_led";
+			default-state = "on";
+			gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_phy>;
+	phy-mode = "rgmii";
+	phy-handle = <&rtl8211e>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
+	tx_delay = <0x30>;
+	rx_delay = <0x20>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rtl8211e: ethernet-phy@1 {
+			reg = <1>;
+			interrupt-parent = <&gpio3>;
+			interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <30000>;
+			reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; // bsp
+		};
+	};
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b { // bsp checked
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2"; // bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
+		// pinctrl-0 = <&pmic_int_l>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_3v0>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v0_tp: LDO_REG2 {
+				regulator-name = "vcc3v0_tp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: vcc_lan: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cpu_b_sleep>; // bsp
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpu_sleep>; // bsp
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c1 {
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+
+	rt5651: rt5651@1a {
+		#sound-dai-cells = <0>;
+		compatible = "realtek,rt5651";
+		reg = <0x1a>;
+		clocks = <&cru SCLK_I2S_8CH_OUT>;
+		clock-names = "mclk";
+		// status = "okay";
+		status = "disabled";
+	};
+/*
+	// HDMI IN
+	tc358749x@0f {
+		compatible = "toshiba,tc358749x";
+		csi-ctl-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
+		int-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <0x3f>;
+		pinctrl-names = "default";
+		power-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>;
+		power18-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
+		power33-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>;
+		reg = <0x0f>;
+		reset-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>;
+		stanby-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+*/
+};
+
+&i2c2 {
+	i2c-scl-rising-time-ns = <600>;
+	i2c-scl-falling-time-ns = <20>;
+	status = "okay";
+};
+
+// Used for HDMI
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+
+	fusb302@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&chg_cc_int_l>;
+		vbus-supply = <&vbus_typec>;
+
+		typec_con: connector {
+			compatible = "usb-c-connector";
+			data-role = "host";
+			label = "USB-C";
+			op-sink-microwatt = <1000000>;
+			power-role = "dual";
+			sink-pdos =
+				<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
+			source-pdos =
+				<PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
+			try-power-role = "sink";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					typec_hs: endpoint {
+						remote-endpoint = <&u2phy0_typec_hs>;
+					};
+				};
+				port@1 {
+					reg = <1>;
+					typec_ss: endpoint {
+						remote-endpoint = <&tcphy0_typec_ss>;
+					};
+				};
+				port@2 {
+					reg = <2>;
+					typec_dp: endpoint {
+						remote-endpoint = <&tcphy0_typec_dp>;
+					};
+				};
+			};
+		};
+	};
+/*
+	accelerometer@68 {
+		compatible = "invensense,mpu6500";
+		reg = <0x68>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>;
+		status = "okay";
+	};
+*/
+};
+
+// ALC5651
+&i2s0 {
+	rockchip,playback-channels = <8>;
+	rockchip,capture-channels = <8>;
+	// status = "okay";
+	status = "disabled";
+};
+
+// HDMI SOUND OUT
+&i2s2 {
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+	bt656-supply = <&vcc1v8_s0>; // bsp
+	// audio-supply = <&vcca1v8_codec>; // bsp
+	sdmmc-supply = <&vcc_sdio>; // bsp
+	gpio1830-supply = <&vcc_3v0>; // bsp
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmu1830-supply = <&vcc_3v0>;
+};
+
+&pinctrl {
+	buttons {
+		pwrbtn: pwrbtn {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+	};
+
+	pmic {
+		cpu_b_sleep: cpu-b-sleep {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+
+		gpu_sleep: gpu-sleep {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+
+		pmic_dvs2: pmic-dvs2 {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+	};
+
+	sd {
+		sdmmc0_pwr_h: sdmmc0-pwr-h {
+			rockchip,pins =
+				<0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	gmac {
+		phy_intb: phy-intb {
+			rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+
+		phy_rstb: phy-rstb {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins =
+				<2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		vcc5v0_typec_en: vcc5v0-typec-en {
+			rockchip,pins =
+				<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_reg_on_h: wifi-reg-on-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	wifi {
+		wifi_host_wake_l: wifi-host-wake-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	bluetooth {
+		bt_reg_on_h: bt-enable-h {
+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	rt5651 {
+		rt5651_spkcon: rt5651-spkcon {
+			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+
+		rt5651_hpdet: rt5651-hpdet {
+			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	fusb302 {
+		chg_cc_int_l: chg-cc-int-l {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+	};
+
+	leds {
+		sys_led_pin: sys-led-pin {
+			rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+	};
+
+	lcd-panel {
+		lcd_panel_reset: lcd-panel-reset {
+			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		mipi_dsi_en: mipi-dsi-en{
+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		mipi_dsi_reset: mipi-dsi-reset {
+			rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	touchscreen {
+		touch_int_l: touch-int-l {
+			rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+
+		touch_reset_l: touch-reset-l {
+			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+/*
+	// BSP Defined GPIO
+	rk33xx-gpio {
+		compatible = "rockchip,rk33xx_gpio_init";
+		pinctrl-0 = <0xd8>;
+		pinctrl-names = "default";
+		sounds_spk_en = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+		system_5v_en = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
+		system_led = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
+		uart_ic_en = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
+		usb_hub_res = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+	};
+	rkxx_user-gpio {
+		compatible = "rockchip,rkxx_user_gpio";
+		edp_display_en = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
+		g4_power = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
+		g4_reset = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>;
+		ledvcc_en0 = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>;
+		ledvcc_en1 = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>;
+		ledvcc_en2 = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>;
+		lvds_display_en = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+		lvds_on_off = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+		relay_pow_en1 = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>;
+		relay_pow_en2 = <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>;
+		status = "okay";
+		usb_power = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>;
+		user_io01 = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+		user_io02 = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+		user_io03 = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
+		user_io04 = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	};
+*/
+	func_gpio {
+		vcc5v0_en: vcc5v0-en {
+			rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		uart_ic_en: uart-ic-en {
+			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		usb_hub_res: usb-hub-res {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		edp_display_en: edp-display-en {
+			rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		g4_power: g4-power {
+			rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		g4_reset: g4-reset {
+			rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		ledvcc_en0: ledvcc-en0 {
+			rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		ledvcc_en1: ledvcc-en1 {
+			rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		edvcc_en2: ledvcc-en2 {
+			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		lvds_display_en: lvds-display-en {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		lvds_on_off: lvds-on-off {
+			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		relay_pow_en1: relay-pow-en1 {
+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		relay_pow_en2: relay-pow-en2 {
+			rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		user_io01: user-io01 {
+			rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		user_io02: user-io02 {
+			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		user_io03: user-io03 {
+			rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		user_io04: user-io04 {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	wiegand {
+		data0_pin: data0-pin {
+			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		data0_send_pin: data0-send-pin {
+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		data1_pin: data1-pin {
+			rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		data1_send_pin: data2-send-pin {
+			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};	
+	};
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+// IR
+// &pwm3 {
+// 	status = "okay";
+// };
+
+&saradc {
+	vref-supply = <&vcca1v8_s3>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	keep-power-in-suspend;
+	non-removable;
+	status = "okay";
+};
+
+&sdio0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	clock-frequency = <50000000>;
+	disable-wp;
+	keep-power-in-suspend;
+	max-frequency = <50000000>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	// status = "disabled";
+
+	brcmf: wifi@1 {
+		reg = <1>;
+		compatible = "brcm,bcm43455-fmac";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; // bsp
+		interrupt-names = "host-wake";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_l>;
+		status = "okay";
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; // bsp
+	clock-frequency = <150000000>;
+	disable-wp;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vcc_sdio>;
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy0_dp {
+	port {
+		tcphy0_typec_dp: endpoint {
+			remote-endpoint = <&typec_dp>;
+		};
+	};
+};
+
+&tcphy0_usb3 {
+	port {
+		tcphy0_typec_ss: endpoint {
+			remote-endpoint = <&typec_ss>;
+		};
+	};
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		phy-supply = <&vbus_typec>;
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+
+	port {
+		u2phy0_typec_hs: endpoint {
+			remote-endpoint = <&typec_hs>;
+		};
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm4345c5";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; // bsp
+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; // bsp
+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; // bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+		status = "okay";
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart4 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};


================================================
FILE: kernel-patch/beta/deprecated-patches/6.18.y-305-dts-add-rk3566-series-devices.patch
================================================
From 62ae4049b839fb445b26013c20a0a4b3ebd93323 Mon Sep 17 00:00:00 2001
From: ophub <68696949+ophub@users.noreply.github.com>
Date: Sat, 31 Jan 2026 20:05:58 +0800
Subject: [PATCH] arch: arm64: dts: rockchip: add rk3566 Series devices

---
 arch/arm64/boot/dts/rockchip/Makefile         |   5 +
 .../boot/dts/rockchip/rk3566-jp-tvbox.dts     | 736 ++++++++++++++++++
 .../boot/dts/rockchip/rk3566-panther-x2.dts   | 568 ++++++++++++++
 .../dts/rockchip/rk3566-tinker-board-3.dts    |  13 +
 .../dts/rockchip/rk3566-tinker-board-3.dtsi   | 278 +++++++
 .../dts/rockchip/rk3566-tinker-board-3s.dts   |  30 +
 .../dts/rockchip/rk3566-wxy-oec-turbo-4g.dts  | 462 +++++++++++
 7 files changed, 2092 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-jp-tvbox.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-panther-x2.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3.dtsi
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3s.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-wxy-oec-turbo-4g.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index f7c26410d..fb9cf591e 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -150,6 +150,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-nanopi-r3s.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-cb2-manta.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-jp-tvbox.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-panther-x2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-tinker-board-3.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-tinker-board-3s.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-wxy-oec-turbo-4g.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-jp-tvbox.dts b/arch/arm64/boot/dts/rockchip/rk3566-jp-tvbox.dts
new file mode 100644
index 000000000..28d611553
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-jp-tvbox.dts
@@ -0,0 +1,736 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 tdleiyao <tdleiyao@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+	model = "JP TVbox 3566";
+	compatible = "JP-TVbox,rk3566", "rockchip,rk3566";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc1;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x10000000>;
+			linux,cma-default;
+		};
+
+		ramoops: ramoops@110000 {
+			compatible = "ramoops";
+			reg = <0x0 0x110000 0x0 0xf0000>;
+			record-size = <0x20000>;
+			console-size = <0x80000>;
+			ftrace-size = <0x00000>;
+			pmsg-size = <0x50000>;
+		};
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_work: led-work {
+			label = "red:work";
+			gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_work_enable_h>;
+		};
+	};
+
+	vcc12v_dcin: vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_usb_otg: vcc5v0-usb-otg {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb_otg";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		status = "okay";
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+		post-power-on-delay-ms = <100>;
+	};
+
+	spdif_dit: spdif-dit {
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+		status = "okay";
+	};
+
+	spdif_sound: spdif-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "SPDIF";
+
+		simple-audio-card,cpu {
+			sound-dai = <&spdif>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&spdif_dit>;
+		};
+	};
+
+	openvfd: openvfd {
+		compatible = "open,vfd";
+		dev_name = "openvfd";
+		status = "okay";
+		vfd_gpio_clk = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+		vfd_gpio_dat = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&combphy1 {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu0_opp_table {
+
+	opp-408000000 {
+		opp-microvolt = <900000 900000 1200000>;
+	};
+
+	opp-600000000 {
+		opp-microvolt = <900000 900000 1200000>;
+	};
+
+	opp-816000000 {
+		opp-microvolt = <900000 900000 1200000>;
+	};
+
+	opp-1104000000 {
+		opp-microvolt = <900000 900000 1200000>;
+	};
+
+	opp-1416000000 {
+		opp-microvolt = <950000 950000 1200000>;
+	};
+
+	opp-1608000000 {
+		opp-microvolt = <1050000 1050000 1200000>;
+	};
+
+	opp-1800000000 {
+		opp-microvolt = <1150000 1150000 1200000>;
+	};
+
+	opp-1992000000 {
+		opp-hz = /bits/ 64 <1992000000>;
+		opp-microvolt = <1200000 1200000 1200000>;
+	};
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&gmac1 {
+	phy-mode = "rgmii";
+
+	///* input
+	clock_in_out = "input";
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+	pinctrl-0 = <&gmac1m0_miim
+		     &gmac1m0_tx_bus2
+		     &gmac1m0_rx_bus2
+		     &gmac1m0_rgmii_clk
+		     &gmac1m0_clkinout
+		     &gmac1m0_rgmii_bus>;
+	//The end of input */
+
+	/* output
+	clock_in_out = "output";
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+	assigned-clock-rates = <0>, <125000000>;
+	pinctrl-0 = <&gmac1m0_miim
+		     &gmac1m0_tx_bus2_level3
+		     &gmac1m0_rx_bus2
+		     &gmac1m0_rgmii_clk_level2
+		     &gmac1m0_rgmii_bus_level3>;
+	The end of output */
+
+	pinctrl-names = "default";
+
+	snps,reset-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f, also works well here */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	tx_delay = <0x3f>;
+	rx_delay = <0x3f>;
+
+	phy-handle = <&rgmii_phy1>;
+	phy-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: tcs4525@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-compatible = "fan53555-reg";
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1390000>;
+		regulator-init-microvolt = <900000>;
+		regulator-initial-mode = <1>;
+		regulator-ramp-delay = <2300>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-boot-on;
+		regulator-always-on;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
+		system-power-controller;
+		#sound-dai-cells = <0>;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+					regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_npu";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_acodec";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+		};
+
+		codec {
+			mic-in-differential;
+		};
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&pinctrl {
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wireless-wlan {
+		wifi_host_wake_irq: wifi-host-wake-irq {
+			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_work_enable_h: led-work-enable-h {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sata2 {
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	non-removable;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+/* spdif is exposed on con40 pin 18 */
+&spdif {
+	status = "okay";
+};
+
+&sdmmc1 {
+	status = "okay";
+
+	bus-width = <4>;
+	max-frequency = <200000000>;
+	cap-sd-highspeed;
+	sd-uhs-sdr50;
+	sd-uhs-ddr50;
+	sd-uhs-sdr104;
+
+	supports-sdio;
+	disable-wp;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	non-removable;
+	rockchip,default-sample-phase=<90>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	brcmf: wifi@1 {
+		compatible = "brcm,bcm4329-fmac";
+		reg = <1>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "host-wake";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_irq>;
+	};
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart1 {
+	dma-names = "tx", "rx";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk809 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+		max-speed = <1500000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcca1v8_pmu>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "disabled";
+};
+
+&usb2phy1_host {
+	status = "disabled";
+};
+
+&usb2phy1_otg {
+	status = "disabled";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-panther-x2.dts b/arch/arm64/boot/dts/rockchip/rk3566-panther-x2.dts
new file mode 100644
index 000000000..a0a08476f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-panther-x2.dts
@@ -0,0 +1,568 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 tdleiyao <tdleiyao@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566.dtsi"
+
+/ {
+	model = "Panther X2";
+	compatible = "panther,x2", "rockchip,rk3566";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
+		mmc2 = &sdmmc1;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_pwr: led-pwr {
+			label = "led-pwr";
+			default-state = "on";
+			gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_pwr_enable_h>;
+			retain-state-suspended;
+			status = "okay";
+		};
+
+		led_wifi: led-wifi {
+			label = "led-wifi";
+			default-state = "off";
+			gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_wifi_enable_h>;
+			retain-state-suspended;
+			status = "okay";
+		};
+
+		led_eth: led-eth {
+			label = "led-eth";
+			default-state = "off";
+			gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_eth_enable_h>;
+			retain-state-suspended;
+			status = "okay";
+		};
+
+		led_status: led-status {
+			label = "led-status";
+			default-state = "on";
+			gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_status_enable_h>;
+			retain-state-suspended;
+			status = "okay";
+		};
+	};
+
+	vbus: vbus-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vbus>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+		post-power-on-delay-ms = <100>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_3v3>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m0_miim
+		     &gmac1m0_tx_bus2
+		     &gmac1m0_rx_bus2
+		     &gmac1m0_rgmii_clk
+		     &gmac1m0_clkinout
+		     &gmac1m0_rgmii_bus>;
+	snps,reset-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		status = "okay";
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+					regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_npu";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_acodec";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				status = "disabled";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+		};
+	};
+};
+
+&i2s1_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx
+		     &i2s1m1_lrcktx &i2s1m1_lrckrx
+		     &i2s1m1_sdi0   &i2s1m1_sdi1
+		     &i2s1m1_sdi2   &i2s1m1_sdi3
+		     &i2s1m1_sdo0   &i2s1m1_sdo1
+		     &i2s1m1_sdo2   &i2s1m1_sdo3>;
+	status = "disabled";
+};
+
+&pinctrl {
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wireless-wlan {
+		wifi_host_wake_irq: wifi-host-wake-irq {
+			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_pwr_enable_h: led-pwr-enable-h {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_wifi_enable_h: led-wifi-enable-h {
+			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_eth_enable_h: led-eth-enable-h {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_status_enable_h: led-status-enable-h {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vcc_3v3>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	non-removable;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	broken-cd;
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&sdmmc1 {
+	supports-sdio;
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	non-removable;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart1 {
+	dma-names = "tx", "rx";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk809 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+		max-speed = <1500000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcca1v8_pmu>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3.dts b/arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3.dts
new file mode 100644
index 000000000..9f3cdaad1
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Michael Opdenacker <michael.opdenacker@rootcommit.com>
+ */
+
+/dts-v1/;
+
+#include "rk3566-tinker-board-3.dtsi"
+
+/ {
+	model = "Asus Tinker Board 3";
+	compatible = "asus,rk3566-tinker-board-3", "rockchip,rk3566";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3.dtsi
new file mode 100644
index 000000000..d9cb73e71
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3.dtsi
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Michael Opdenacker <michael.opdenacker@rootcommit.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+	aliases {
+		i2c0 = &i2c0;
+		i2c2 = &i2c2;
+		mmc1 = &sdmmc0;
+		serial2 = &uart2;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gpio_leds: gpio-leds {
+		compatible = "gpio-leds";
+
+		act-led {
+			gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger="mmc1";
+		};
+
+		rsv-led {
+			gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger="none";
+		};
+	};
+
+	vcc3v3_sys: regulator-3v3-vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: regulator-5v0-vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_usb_host: regulator-5v0-vcc-usb-host {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&u2_a_vbus_en>;
+		regulator-name = "vcc5v0_usb_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		clock-names = "mclk";
+		clock-output-names = "rk809-clkout1", "rk809-clkout2";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
+		#sound-dai-cells = <0>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		regulators {
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <830000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	eeprom@50 {
+		compatible = "atmel,24c08";
+		reg = <0x50>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&eeprom_wc_n>;
+	};
+
+	rtc_isl1208: rtc@6f {
+		compatible = "isil,isl1208";
+		reg = <0x6f>;
+		interrupt-names = "irq";
+		interrupts-extended = <&gpio0 RK_PD3 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtcic_int_l>;
+	};
+};
+
+&pinctrl {
+	eeprom {
+		eeprom_wc_n: eeprom-wc-n {
+			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	rtc {
+		rtcic_int_l: rtcic-int-l {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		u2_a_vbus_en: u2-a-vbus-en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		u3_a_vbus_en: u3-a-vbus-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3s.dts b/arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3s.dts
new file mode 100644
index 000000000..3624ebc8a
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-tinker-board-3s.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Michael Opdenacker <michael.opdenacker@rootcommit.com>
+ */
+
+/dts-v1/;
+
+#include "rk3566-tinker-board-3.dtsi"
+
+/ {
+	model = "Asus Tinker Board 3S";
+	compatible = "asus,rk3566-tinker-board-3s", "rockchip,rk3566";
+
+	aliases {
+		mmc0 = &sdhci;
+	};
+};
+
+&sdhci {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	max-frequency = <200000000>;
+	mmc-hs200-1_8v;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-wxy-oec-turbo-4g.dts b/arch/arm64/boot/dts/rockchip/rk3566-wxy-oec-turbo-4g.dts
new file mode 100644
index 000000000..bdbd28222
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-wxy-oec-turbo-4g.dts
@@ -0,0 +1,462 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Author: Piotr Oniszczuk piotr.oniszczuk@gmail.com
+ * Based on Quartz64 DT by: Peter Geis pgwipeout@gmail.com
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/clock/rk3568-cru.h>
+#include <dt-bindings/power/rk3568-power.h>
+#include "rk3566.dtsi"
+
+/ {
+	compatible = "rockchip,rk3566-wxy-oec-turbo-4g", "rockchip,rk3566";
+	model = "Rockchip RK3566 WXY OEC Turbo board";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
+		sata2 = &sata2;
+	};
+
+	/delete-node/ display-subsystem;
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+
+	adc_keys: adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		vol-up-key {
+			label = "volume up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <1750>;
+		};
+
+		vol-down-key {
+			label = "volume down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			press-threshold-microvolt = <297500>;
+		};
+	};
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_pins>;
+
+		green_led: green-led {
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+			retain-state-suspended;
+		};
+
+		blue_led: blue-led {
+			color = <LED_COLOR_ID_BLUE>;
+			gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			retain-state-suspended;
+		};
+
+		red_led: red-led {
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			retain-state-suspended;
+		};
+	};
+
+	vcc12v0_dcin: regulator-vcc12v0-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v0_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v0_dcin>;
+	};
+
+	vcc3v3_sys: regulator-vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc12v0_dcin>;
+	};
+
+	vcc_3v3: regulator-vcc-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc5v0_usb_host: regulator-vcc5v0-usb-host {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb_host";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+		gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en>;
+	};
+
+	vcca_1v8: regulator-vcca-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcca_1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vdda_0v9: regulator-vdda-0v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "vdda_0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vdd_fixed: regulator-vdd-fixed {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_fixed";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <950000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vdd_cpu: regulator-vdd-cpu {
+		compatible = "pwm-regulator";
+		pwms = <&pwm0 0 5000 1>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-settling-time-up-us = <250>;
+		pwm-supply = <&vcc5v0_sys>;
+	};
+
+	vdd_logic: regulator-vdd-logic {
+		compatible = "pwm-regulator";
+		pwms = <&pwm1 0 5000 1>;
+		regulator-name = "vdd_logic";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1100000>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-settling-time-up-us = <250>;
+		pwm-supply = <&vcc5v0_sys>;
+	};
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+	phy-mode = "rgmii";
+	clock_in_out = "input";
+	phy-supply = <&vcc_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		    &gmac1m1_tx_bus2
+		    &gmac1m1_rx_bus2
+		    &gmac1m1_rgmii_clk
+		    &gmac1m1_rgmii_bus
+		    &gmac1m1_clkinout>;
+	snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	tx_delay = <0x4f>;
+	rx_delay = <0x2d>;
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+
+		/*
+		 * RTL8211F Custom LED Mode B
+		 * LED1 (Green):  Link 10/100/1000
+		 * LED2 (Yellow): Active 10/100/1000
+		 */
+		realtek,led-data = <0xc160>;
+
+		/* Optional: Specify specific RTL8211F if needed */
+		/* compatible = "realtek,rtl8211f", "ethernet-phy-ieee802.3-c22"; */
+	};
+};
+
+&gpu {
+	mali-supply = <&vdd_logic>;
+	status = "okay";
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&pinctrl {
+
+	usb {
+		vcc5v0_usb_host_en: vcc5v0_usb_host_en {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+	};
+
+	sata {
+		sata_pm_reset: sata-pm-reset {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+	};
+
+	leds {
+		led_pins: led-pins {
+			rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>,
+					<3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>,
+					<0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc_3v3>;
+	pmuio2-supply = <&vcc_3v3>;
+	vccio1-supply = <&vcca_1v8>;
+	vccio3-supply = <&vcc_3v3>;
+	vccio4-supply = <&vcca_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcca_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pcie2x1 {
+	status = "disabled";
+};
+
+&sata2 {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart5 {
+	status = "disabled";
+};
+
+&uart7 {
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vpu {
+	status = "okay";
+};
+
+&vdpu_mmu {
+	status = "okay";
+};
+
+&vepu {
+	status = "okay";
+};
+
+&vepu_mmu {
+	status = "okay";
+};
+
+&rga {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};


================================================
FILE: kernel-patch/beta/deprecated-patches/6.18.y-306-dts-add-rk3568-series-devices.patch
================================================
From 5c37091528a714b35f524d55f716460f88c7a1c4 Mon Sep 17 00:00:00 2001
From: ophub <68696949+ophub@users.noreply.github.com>
Date: Sat, 31 Jan 2026 20:28:06 +0800
Subject: [PATCH] arch: arm64: dts: rockchip: add rk3568 Series devices

---
 arch/arm64/boot/dts/rockchip/Makefile         |  11 +
 .../dts/rockchip/rk3568-9tripod-x3568-v4.dts  | 880 ++++++++++++++++
 .../boot/dts/rockchip/rk3568-dg-tn3568.dts    | 585 +++++++++++
 .../boot/dts/rockchip/rk3568-easepi-r1.dts    | 623 +++++++++++
 arch/arm64/boot/dts/rockchip/rk3568-ec-x.dts  | 778 ++++++++++++++
 .../boot/dts/rockchip/rk3568-mrkaio-m68s.dts  | 161 +++
 .../boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi | 511 +++++++++
 .../boot/dts/rockchip/rk3568-seewo-sv21.dts   | 562 ++++++++++
 .../boot/dts/rockchip/rk3568-swan1-w28.dts    | 733 +++++++++++++
 arch/arm64/boot/dts/rockchip/rk3568-tx68.dts  | 968 ++++++++++++++++++
 .../dts/rockchip/rk3568-watermelon-core.dtsi  | 512 +++++++++
 .../dts/rockchip/rk3568-watermelon-pi-v3.dts  | 546 ++++++++++
 .../dts/rockchip/rk3568-watermelon-pi.dts     | 547 ++++++++++
 .../boot/dts/rockchip/rk3568-wocyber-a3.dts   | 726 +++++++++++++
 14 files changed, 8143 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-dg-tn3568.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-ec-x.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-seewo-sv21.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-swan1-w28.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-tx68.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-watermelon-core.dtsi
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-watermelon-pi-v3.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-watermelon-pi.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-wocyber-a3.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index fb9cf591e..bf8251e6d 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -155,7 +155,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-panther-x2.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-tinker-board-3.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-tinker-board-3s.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-wxy-oec-turbo-4g.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-9tripod-x3568-v4.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-dg-tn3568.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-easepi-r1.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ec-x.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb
@@ -163,6 +167,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h66k.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h68k.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mecsbc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mrkaio-m68s.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
@@ -172,6 +177,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-seewo-sv21.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-swan1-w28.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-tx68.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-watermelon-pi.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-watermelon-pi-v3.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wocyber-a3.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts b/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts
new file mode 100644
index 000000000..4db00489b
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts
@@ -0,0 +1,880 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "9Tripod X3568 v4";
+	compatible = "9tripod,x3568-v4", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
+		mmc2 = &sdmmc2;
+		rtc0 = &rtc0;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-vol-up {
+			label = "volume up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <50000>;
+		};
+
+		button-vol-down {
+			label = "volume down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			press-threshold-microvolt = <500000>;
+		};
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_work: led-0 {
+			gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_BLUE>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_work_en>;
+		};
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	pdm_codec: pdm-codec {
+		compatible = "dmic-codec";
+		num-channels = <2>;
+		#sound-dai-cells = <0>;
+	};
+
+	pdm_sound: pdm-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "microphone";
+
+		simple-audio-card,cpu {
+			sound-dai = <&pdm>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&pdm_codec>;
+		};
+	};
+
+	spdif_dit: spdif-dit {
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+
+	spdif_sound: spdif-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "SPDIF";
+
+		simple-audio-card,cpu {
+			sound-dai = <&spdif>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&spdif_dit>;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable>;
+		post-power-on-delay-ms = <100>;
+		power-off-delay-us = <300>;
+		reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+	};
+
+	dc_12v: regulator-dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	pcie30_avdd0v9: regulator-pcie30-avdd0v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	pcie30_avdd1v8: regulator-pcie30-avdd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_sys: regulator-vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc3v3_pcie: regulator-vcc3v3-pcie {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_pcie_en_pin>;
+		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <5000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb: regulator-vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb_host: regulator-vcc5v0-usb-host {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en>;
+		regulator-name = "vcc5v0_usb_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc5v0_usb_otg: regulator-vcc5v0-usb-otg {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
+		regulator-name = "vcc5v0_usb_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+};
+
+&can1 {
+	assigned-clocks = <&cru CLK_CAN1>;
+	assigned-clock-rates = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&can1m1_pins>;
+	status = "okay";
+};
+
+/* used for usb_host0_xhci */
+&combphy0 {
+	status = "okay";
+};
+
+/* used for usb_host1_xhci */
+&combphy1 {
+	status = "okay";
+};
+
+/* connected to sata2 */
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+	phy-handle = <&rgmii_phy0>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus>;
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+		system-power-controller;
+		#sound-dai-cells = <0>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+		codec {
+			rockchip,mic-in-differential;
+		};
+	};
+};
+
+&i2c5 {
+	status = "okay";
+
+	rtc0: rtc@51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+/* used for AP6275S Bluetooth Sound */
+&i2s3_2ch {
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@3 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <3>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+
+		leds {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			led@1 {
+				reg = <1>;
+				color = <LED_COLOR_ID_GREEN>;
+				function = LED_FUNCTION_LAN;
+				default-state = "keep";
+			};
+
+			/* Note: The LED polarity is inverted */
+			led@2 {
+				reg = <2>;
+				color = <LED_COLOR_ID_AMBER>;
+				function = LED_FUNCTION_LAN;
+				default-state = "keep";
+			};
+		};
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@2 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <2>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
+
+		leds {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			led@1 {
+				reg = <1>;
+				color = <LED_COLOR_ID_GREEN>;
+				function = LED_FUNCTION_LAN;
+				default-state = "keep";
+			};
+
+			/* Note: The LED polarity is inverted */
+			led@2 {
+				reg = <2>;
+				color = <LED_COLOR_ID_AMBER>;
+				function = LED_FUNCTION_LAN;
+				default-state = "keep";
+			};
+		};
+	};
+};
+
+&pcie30phy {
+	status = "okay";
+};
+
+&pcie3x2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_pin>;
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pdm {
+	status = "okay";
+};
+
+&pinctrl {
+	leds {
+		led_work_en: led_work_en {
+			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable: wifi-enable {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_host_en: vcc5v0_usb_host_en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie_reset_pin: pcie-reset-pin {
+			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
+			rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm4 {
+	status = "okay";
+};
+
+/* Required remotectl for IR receiver */
+&pwm7 {
+	status = "disabled";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sata2 {
+	status = "okay";
+};
+
+/* used for eMMC */
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	mmc-hs200-1_8v;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	status = "okay";
+};
+
+/* used for microSD (TF) Slot */
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+/* used for AP6275S WiFi */
+&sdmmc2 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sys>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&spdif {
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+/* used for Debug */
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-0 = <&uart3m1_xfer>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-0 = <&uart4m1_xfer>;
+	status = "okay";
+};
+
+/* used for WiFi/BT AP6275S */
+&uart8 {
+	pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>;
+	status = "okay";
+};
+
+&uart9 {
+	pinctrl-0 = <&uart9m1_xfer>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	extcon = <&usb2phy0>;
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-dg-tn3568.dts b/arch/arm64/boot/dts/rockchip/rk3568-dg-tn3568.dts
new file mode 100644
index 000000000..db14f3d13
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-dg-tn3568.dts
@@ -0,0 +1,585 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 hqnicolas <hqnicolas@msn.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "dg-tn3568";
+	compatible = "dg-tn3568,rk3568", "rockchip,rk3568";
+	bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+		mmc2 = &sdmmc1;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: vcc5v0_sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status: led-status {
+			label = "led-status";
+			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_sys_h>;
+		};
+
+		led_on_board: led-on-board {
+			label = "led-on-board";
+			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+			//linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_on_board_h>;
+		};
+
+		led_eth_y: led-eth-y {
+			label = "led-eth-y";
+			gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+			//linux,default-trigger = "default-on";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_eth_y_h>;
+		};
+
+		led_eth_g: led-eth-g {
+			label = "led-eth-g";
+			gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
+			//linux,default-trigger = "default-on";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_eth_g_h>;
+		};
+	};
+
+	vbus: vbus-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	rk809_sound: rk809-sound {
+		status = "okay";
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "rockchip,rk809-codec";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&rk809_codec>;
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		pwms = <&pwm12 0 40000 0>;
+		fan-supply = <&dc_12v>;
+		//interrupt-parent = <&gpio0>;
+		//interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
+		pulses-per-revolution = <2>;
+	cooling-levels = <0 50 100 150 200 255>;
+	rockchip,temp-trips = < 40000   1
+				50000   2
+				55000   3
+				60000   4
+				70000   5 >;
+	};
+};
+
+&combphy0 {
+	rockchip,dis-u3otg0-port;
+	status = "okay";
+};
+
+&combphy1 {
+	rockchip,dis-u3otg1-port;
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac0 {
+	phy-mode = "rgmii";
+	clock_in_out = "input";
+
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+	assigned-clock-rates = <0>, <125000000>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+
+	tx_delay = <0x2a>;
+	rx_delay = <0x2a>;
+
+	phy-handle = <&rgmii_phy0>;
+	phy-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		#sound-dai-cells = <0>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+					regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_npu";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_acodec";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+		rk809_codec: codec {
+			mic-in-differential;
+			#sound-dai-cells = <0>;
+		};
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m0_sclktx
+				 &i2s1m0_lrcktx
+				 &i2s1m0_sdi0
+				 &i2s1m0_sdo0>;
+	rockchip,trcm-sync-tx-only;
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		status = "okay";
+	};
+};
+
+&pinctrl {
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	leds {
+		led_eth_y_h: led_eth_y_h {
+			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_eth_g_h: led_eth_g_h {
+			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_sys_h: led_sys_h {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_on_board_h: led_on_board_h {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm12 {
+	pinctrl-0 = <&pwm12m1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	non-removable;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	phys = <&usb2phy0_otg>;
+	phy-names = "usb2-phy";
+	extcon = <&usb2phy0>;
+	maximum-speed = "high-speed";
+	snps,dis_u2_susphy_quirk;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	phys = <&usb2phy0_host>;
+	phy-names = "usb2-phy";
+	maximum-speed = "high-speed";
+	snps,dis_u2_susphy_quirk;
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vpu {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts b/arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts
new file mode 100644
index 000000000..12225b631
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "LinkEase EasePi R1";
+	compatible = "linkease,easepi-r1", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		mmc0 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+
+		button-recovery {
+			label = "Recovery";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <1750>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&status_led_pin>;
+
+		status_led: led-status {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	dc_12v: regulator-dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc3v3_sys: regulator-vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	pcie30_avdd0v9: regulator-pcie30-avdd0v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	pcie30_avdd1v8: regulator-pcie30-avdd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	regulator-vdd0v95-25glan {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vdd0v95_25glan_en>;
+		regulator-name = "vdd0v95_25glan";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <950000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_nvme: regulator-vcc3v3-nvme {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_nvme_en>;
+		regulator-name = "vcc3v3_nvme";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	phy-handle = <&rgmii_phy0>;
+	phy-mode = "rgmii-id";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+	status = "okay";
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii-id";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		system-power-controller;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <950000>;
+				regulator-max-microvolt = <950000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		pinctrl-0 = <&eth_phy0_reset_pin>;
+		pinctrl-names = "default";
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		pinctrl-0 = <&eth_phy1_reset_pin>;
+		pinctrl-names = "default";
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
+	};
+};
+
+/* ETH3 */
+&pcie2x1 {
+	reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_sys>;
+	status = "okay";
+};
+
+&pcie30phy {
+	data-lanes = <1 2>;
+	status = "okay";
+};
+
+/* ETH2 */
+&pcie3x1 {
+	num-lanes = <1>;
+	reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_sys>;
+	status = "okay";
+};
+
+/* M.2 Key for 2280 NVMe */
+&pcie3x2 {
+	num-lanes = <1>;
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_nvme>;
+	status = "okay";
+};
+
+&pinctrl {
+	gmac0 {
+		eth_phy0_reset_pin: eth-phy0-reset-pin {
+			rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	gmac1 {
+		eth_phy1_reset_pin: eth-phy1-reset-pin {
+			rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	gpio-leds {
+		status_led_pin: status-led-pin {
+			rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	nvme {
+		vcc3v3_nvme_en: vcc3v3-nvme-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie-nic {
+		vdd0v95_25glan_en: vdd0v95-25glan-en {
+			rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic-int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+/* OTG Only USB2.0, Only device mode */
+&usb_host0_xhci {
+	dr_mode = "peripheral";
+	extcon = <&usb2phy0>;
+	maximum-speed = "high-speed";
+	phys = <&usb2phy0_otg>;
+	phy-names = "usb2-phy";
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_sys>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-ec-x.dts b/arch/arm64/boot/dts/rockchip/rk3568-ec-x.dts
new file mode 100644
index 000000000..a21418115
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-ec-x.dts
@@ -0,0 +1,778 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2023 Flippy <flippy@sina.com>
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "RK3568 EC-X";
+	compatible = "rockchip,ec-x", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		mmc0 = &sdhci;
+	};
+
+	chosen: chosen {
+		bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyS2,1500000";
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x10000000>;
+			linux,cma-default;
+		};
+
+		ramoops: ramoops@110000 {
+			compatible = "ramoops";
+			reg = <0x0 0x110000 0x0 0xf0000>;
+			record-size = <0x20000>;
+			console-size = <0x80000>;
+			ftrace-size = <0x00000>;
+			pmsg-size = <0x50000>;
+		};
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_green_en>, <&led_red_en>, <&led_blue_en>;
+
+		led_green: led-green {
+			label = "green:led1";
+			gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_red: led-red {
+			label = "red:led2";
+			gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+
+		led_blue: led-blue {
+			label = "blue:led3";
+			gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+		};
+
+	};
+
+	vcc12v_dcin: vcc12v-dcin-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc3v8_4g: vcc3v8-4g-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v8_4g";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3800000>;
+		regulator-max-microvolt = <3800000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc1v8_lcd: vcc1v8-lcd-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_lcd";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		enable-active-high;
+		gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc1v8_lcd_pwren_h>;
+
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_sata: vcc3v3-sata-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sata";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc1v8_sys: vcc1v8-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc_usb_hub_en: vcc-usb-hub-en {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_usb_hub_en";
+		regulator-always-on;
+		regulator-boot-on;
+
+		enable-active-high;
+		gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_usb_hub_en_h>;
+
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+ 	fan: pwm-fan {
+ 		compatible = "pwm-fan";
+		cooling-levels = <0 127 163 255>;
+ 		#cooling-cells = <2>;
+ 		fan-supply = <&vcc5v0_sys>;
+ 		pwms = <&pwm0 0 50000 0>;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		power-supply = <&vcc5v0_sys>;
+		max-brightness = <255>;
+		pwms = <&pwm14 0 5000000 0>; //250Hz
+		post-pwm-on-delay-ms = <10>;
+		pwm-off-delay-ms = <10>;
+	};
+};
+
+/* for sata0 & usb_host0_xhci */
+&combphy0 {
+	status = "okay";
+};
+
+/* for sata1 & usb_host1_xhci */
+&combphy1 {
+	status = "okay";
+};
+
+/* for sata2 & pcie2x1 */
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_thermal {
+	trips {
+		cpu_cool: cpu_cool {
+			temperature = <45000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_warm: cpu_warm {
+			temperature = <55000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_hot: cpu_hot {
+			temperature = <65000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map1 {
+			trip = <&cpu_cool>;
+			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+		};
+
+		map2 {
+			trip = <&cpu_warm>;
+			cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+		};
+
+		map3 {
+			trip = <&cpu_hot>;
+			cooling-device = <&fan 3 THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&dsi_dphy0 {
+	status = "okay";
+};
+
+&dsi0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	ports {
+		dsi0_in: port@0 {
+			reg = <0>;
+
+			dsi0_in_vp1: endpoint {
+				remote-endpoint = <&vp1_out_dsi0>;
+			};
+		};
+
+		dsi0_out: port@1 {
+			reg = <1>;
+
+			mipi_out_panel: endpoint {
+				remote-endpoint = <&mipi_in_panel>;
+			};
+		};
+	};
+
+	panel: panel@0 {
+		compatible = "anbernic,rg353p-panel", "newvision,nv3051d";
+		reg = <0>;
+		backlight = <&backlight>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd_reset_en_l>;
+		reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>;
+		vdd-supply = <&vcc1v8_lcd>;
+
+		port {
+			mipi_in_panel: endpoint {
+				remote-endpoint = <&mipi_out_panel>;
+			};
+		};
+	};
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+
+	clock_in_out = "input";
+	phy-mode = "rgmii";
+	tx_delay = <0x34>;
+	rx_delay = <0x2e>;
+
+	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 50000 200000>;
+	phy-handle = <&rgmii_phy0>;
+
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#sound-dai-cells = <0>;
+
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		pwrkey {
+			status = "okay";
+		};
+
+		pinctrl_rk8xx: pinctrl_rk8xx {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			rk817_slppin_null: rk817_slppin_null {
+				pins = "gpio_slp";
+				function = "pin_fun0";
+			};
+
+			rk817_slppin_slp: rk817_slppin_slp {
+				pins = "gpio_slp";
+				function = "pin_fun1";
+			};
+
+			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
+				pins = "gpio_slp";
+				function = "pin_fun2";
+			};
+
+			rk817_slppin_rst: rk817_slppin_rst {
+				pins = "gpio_slp";
+				function = "pin_fun3";
+			};
+		};
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		phy-supply = <&vcc3v3_sys>;
+		reg = <0x1>;
+	};
+};
+
+/* Mini PCIE */
+&pcie2x1 {
+	reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pinctrl {
+	leds {
+		led_green_en: led-green-en {
+			rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_red_en: led-red-en {
+			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_blue_en: led-blue-en {
+			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	lcd {
+		vcc1v8_lcd_pwren_h: vcc18vrlcd-pwren-h {
+			rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		lcd_reset_en_l: lcd-reset-en-l {
+			rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic-int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		vcc_usb_hub_en_h: vcc-usb-hub-en-h {
+			rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm14 {
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcc1v8_sys>;
+	status = "okay";
+};
+
+/* M.2 NGFF */
+&sata0 {
+	status = "okay";
+	target-supply = <&vcc3v3_sata>;
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	status = "okay";
+	dr_mode = "host";
+	phys = <&usb2phy0_otg>;
+	phy-names = "usb2-phy";
+	extcon = <&usb2phy0>;
+	maximum-speed = "high-speed";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp1 {
+	vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
+		reg = <ROCKCHIP_VOP2_EP_MIPI0>;
+		remote-endpoint = <&dsi0_in_vp1>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dts b/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dts
new file mode 100644
index 000000000..9ac1ff9bb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dts
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
+ */
+
+/dts-v1/;
+#include <dt-bindings/leds/common.h>
+#include "rk3568-mrkaio-m68s.dtsi"
+
+/ {
+	model = "EZPRO Mrkaio M68S";
+	compatible = "ezpro,mrkaio-m68s", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+
+		led-boot = &power_led;
+		led-failsafe = &power_led;
+		led-running = &power_led;
+		led-upgrade = &power_led;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&disk_led_pin>, <&power_led_pin>;
+
+		led-disk {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_DISK;
+			gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "disk-activity";
+		};
+
+		power_led: led-power {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	switch_otg: switch-otg-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_otg_switch_en>;
+		regulator-name = "switch_otg";
+		regulator-always-on;
+	};
+
+	vcc5v0_ahci: vcc5v0-ahci-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sata_pwr_en>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vcc5v0_ahci";
+	};
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	phy-mode = "rgmii-id";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+	snps,reset-gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x3c>;
+	rx_delay = <0x2f>;
+	phy-handle = <&rgmii_phy0>;
+	status = "okay";
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	phy-mode = "rgmii-id";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus>;
+	snps,reset-gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x42>;
+	rx_delay = <0x28>;
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		realtek,led-data = <0x6d60>;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		realtek,led-data = <0x6d60>;
+	};
+};
+
+&pinctrl {
+	leds {
+		disk_led_pin: disk-led-pin {
+			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		power_led_pin: power-led-pin {
+			rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sata {
+		sata_pwr_en: sata-pwr-en {
+			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_host_en: vcc5v0-usb-host-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		usb_otg_switch_en: usb-otg-switch-en {
+			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&sata2 {
+	target-supply = <&vcc5v0_ahci>;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi
new file mode 100644
index 000000000..ceff74a31
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi
@@ -0,0 +1,511 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	aliases {
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	dc_12v: dc-12v-regulator {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-name = "dc_12v";
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_sys";
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vcc5v0_sys";
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc5v0_usb_host";
+	};
+
+	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc5v0_usb_otg";
+	};
+};
+
+&combphy0 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1390000>;
+		regulator-name = "vdd_cpu";
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-name = "vdd_logic";
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-name = "vdd_gpu";
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-name = "vdd_npu";
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_acodec";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_3v3";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&pinctrl {
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-seewo-sv21.dts b/arch/arm64/boot/dts/rockchip/rk3568-seewo-sv21.dts
new file mode 100644
index 000000000..781d2a2de
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-seewo-sv21.dts
@@ -0,0 +1,562 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 tdleiyao <tdleiyao@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "seewo SV21";
+	compatible = "seewo,sv21", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac1;
+		ethernet1 = &rtl8153;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+		mmc2 = &sdmmc1;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-recovery {
+			label = "Reset";
+			linux,code = <KEY_RESTART>;
+			press-threshold-microvolt = <1800>;
+		};
+	};
+
+	dc_12v: dc-12v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb_host";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en_pin>;
+		regulator-always-on;
+	};
+
+	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb_otg";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en_pin>;
+	};
+};
+
+&combphy0 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus>;
+	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
+	snps,reset-active-high;
+	snps,reset-delays-us = <0 1000000 2000000>;
+	tx_delay = <0x2a>;
+	rx_delay = <0x2a>;
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
+		system-power-controller;
+		#sound-dai-cells = <0>;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+					regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_npu";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_acodec";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2c5 {
+	status = "okay";
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <0>;
+		clock-output-names = "rtcic_32kout";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+		wakeup-source;
+	};
+};
+
+&i2s1_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx
+		     &i2s1m1_lrcktx &i2s1m1_lrckrx
+		     &i2s1m1_sdi0   &i2s1m1_sdi1
+		     &i2s1m1_sdi2   &i2s1m1_sdi3
+		     &i2s1m1_sdo0   &i2s1m1_sdo1
+		     &i2s1m1_sdo2   &i2s1m1_sdo3>;
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&pinctrl {
+	ethernet {
+		eth_phy_rst: eth-phy-rst {
+			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb_otg_en_pin: vcc5v0-usb-otg-en-pin {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_3v3>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sata2 {
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	broken-cd;
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&sdmmc1 {
+	supports-sdio;
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	non-removable;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	extcon = <&usb2phy0>;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	rtl8153: device@2 {
+		compatible = "usbbda,8153";
+		reg = <2>;
+		realtek,led-data = <0x87>;
+	};
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-swan1-w28.dts b/arch/arm64/boot/dts/rockchip/rk3568-swan1-w28.dts
new file mode 100644
index 000000000..0df599e30
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-swan1-w28.dts
@@ -0,0 +1,733 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 dy008 <dy008@163.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "iMin Swan1 W29 V01";
+	compatible = "imin,swan1", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	vcc12v_dcin: vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_usb: vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_usb_host: vcc5v0-usb-host {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en>;
+		regulator-name = "vcc5v0_usb_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
+		regulator-name = "vcc5v0_usb_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		status = "okay";
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		post-power-on-delay-ms = <0xc8>;
+		power-off-delay-us = <0xc8>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_reg_on_h>;
+		reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+	};
+
+	wireless_wlan: wireless-wlan {
+		compatible = "wlan-platdata";
+		rockchip,grf = <&grf>;
+		wifi_chip_type = "ap6255";
+		status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_h>;
+		sdio_vref = <0x708>;
+		WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
+	};
+
+	cashbox: cashbox {
+		compatible = "rockchip,cashbox-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&cashbox_gpio_en>;
+		ctl-gpio1 = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
+		ctl-gpio2 = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	usb_hub_ctrl: usb-hub-ctrl {
+		compatible = "usb-hub-ctrl";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hub_vcc_en_pin>;
+		hub-vcc-pin = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+		host-b-vcc-pin = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+		hub-rst-pin1 = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>;
+		hub-vcc-en-pin = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		device-host-pin = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>;
+		status = "okay";
+	};
+
+	neostra_gpio: neostra-gpio {
+		compatible = "neostra,neostra-gpio";
+		pinctrl-names = "default";
+		rj11-vcc-pin = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
+		rj11txrx5v-pin = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>;
+		rj11txrx12v-pin = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	usbprinter_gpio: usbprinter-gpio {
+		compatible = "neostra,usbprinter-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&usbprinter_pin>;
+		hub-vcc-pin = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
+		hub-rst-pin = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+		scanbox-vcc-pin = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
+		printer-vcc-pin = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	usbpwr5v0: usbpwr5v0 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;	//<0x02 0x1b 0x00>
+		pinctrl-names = "default";
+		pinctrl-0 = <&usbpwr5v0_en>;
+		regulator-name = "usbpwr5v0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+};
+
+&combphy0 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus>;
+	snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x42>;
+	rx_delay = <0x28>;
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		realtek,led-data = <0x6d60>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+		system-power-controller;
+		#sound-dai-cells = <0>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+		codec {
+			mic-in-differential;
+		};
+	};
+};
+
+&i2c5 {
+	status = "okay";
+
+	hym8563@51 {
+		compatible = "haoyu,hym8563";
+		status = "okay";
+		reg = <0x51>;
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr50;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&sdmmc1 {
+    max-frequency = <150000000>;
+    supports-sdio;
+    bus-width = <4>;
+    disable-wp;
+    cap-sd-highspeed;
+    cap-sdio-irq;
+    keep-power-in-suspend;
+    pinctrl-names = "default";
+    pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+    sd-uhs-sdr104;
+    mmc-pwrseq = <&sdio_pwrseq>;
+    non-removable;
+    status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+ 	uart-has-rtscts;
+ 	status = "okay";
+ 
+ 	bluetooth {
+ 		compatible = "brcm,bcm43438-bt";
+ 		clocks = <&rk809 1>;
+ 		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>;
+ 		vbat-supply = <&vcc3v3_sys>;
+ 		vddio-supply = <&vcc_1v8>;
+ 	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	extcon = <&usb2phy0>;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	phys = <&usb2phy0_host>;
+	phy-names = "usb2-phy";
+	maximum-speed = "high-speed";
+	extcon = <&usb2phy0>;
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&pinctrl {
+
+	ethernet {
+		eth_phy_rst: eth_phy_rst {	//<0x03 0x08 0x00 0x13f>;
+			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_host_en: vcc5v0_usb_host_en {	//<0x00 0x06 0x00 0x13f>;
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {	//<0x00 0x05 0x00 0x13f>;
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	bt {
+		bt_enable: bt_enable {
+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_host_wake: bt_host_wake {
+			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake: bt_wake {
+			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+	
+	wifi {
+		wifi_reg_on_h: wifi_reg_on_h {
+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wifi_host_wake_h: wifi_host_wake_h {
+			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	cashbox {
+		cashbox_gpio_en: cashbox_gpio_en {	//<0x04 0x12 0x00 0x13f 0x04 0x1a 0x00 0x13f>
+			rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
+							<4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb_hub_ctrl {
+		hub_vcc_en_pin: hub_vcc_en_pin {	//<0x00 0x15 0x00 0x13f 0x04 0x18 0x00 0x13f 0x04 0x19 0x00 0x13f>;
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>,
+							<4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
+							<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usbprinter_gpio {
+			usbprinter_pin: usbprinter_pin {	//<0x03 0x04 0x00 0x13f 0x02 0x1e 0x00 0x13f 0x03 0x13 0x00 0x13f 0x02 0x1f 0x00 0x13f>;
+				rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>,
+								<2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>,
+								<3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>,
+								<2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+		};
+
+	usbpwr5v0 {
+
+		usbpwr5v0_en: usbpwr5v0_en {	//<0x02 0x1b 0x00 0x13f>;
+			rockchip,pins = <0x02 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-tx68.dts b/arch/arm64/boot/dts/rockchip/rk3568-tx68.dts
new file mode 100644
index 000000000..13398ed5f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-tx68.dts
@@ -0,0 +1,968 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2024 flippy <flippy@sina.com>
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "TX68";
+	compatible = "rk3568,tx68", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &rtl8125_2;
+		ethernet1 = &rtl8125_1;
+		ethernet2 = &gmac1;
+		ethernet3 = &gmac0;
+		ethernet4 = &rtl8153_1;
+		ethernet5 = &rtl8153_2;
+		mmc0 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_green_en>, <&led_net_en>, <&led_work_en>;
+
+		led_green: led-green {
+			label = "green:user";
+			gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_net: led-net {
+			label = "blue:net";
+			gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_work: led-work {
+			label = "green:work";
+			gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&reset_button_pin>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "reset";
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <50>;
+		};
+	};
+
+
+ 	fan: pwm-fan {
+ 		compatible = "pwm-fan";
+		cooling-levels = <0 127 163 255>;
+ 		#cooling-cells = <2>;
+ 		fan-supply = <&vcc5v0_sys>;
+ 		pwms = <&pwm0 0 50000 0>;
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	rfkill_switchs {
+		compatible = "rfkill-gpio";
+
+		modem {
+			label = "lte-modem";
+			radio-type = "wwan";
+			reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&lte_modem_reset>;
+		};
+	};
+
+	vcc12v_dcin: vcc-12v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_usb: vcc5v0-usb-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb_regulator";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	/* minipcie power : wifi */
+	vcc3v3_pcie2: vcc3v3-pcie2-regulator {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_pcie2";
+		regulator-boot-on;
+		regulator-always-on;
+
+		gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_pcie2_en>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	/* eth 2.5g power */
+	vcc3v3_pcie3: vcc3v3-pcie3-regulator {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_pcie3";
+		regulator-boot-on;
+		regulator-always-on;
+
+		enable-active-high;
+		gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_pcie3_en>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v8_lte: vcc3v8-lte-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vcc3v8_lte_regulator";
+		regulator-min-microvolt = <3800000>;
+		regulator-max-microvolt = <3800000>;
+
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v8_lte_pwr_en>;
+
+		vin-supply = <&vcc12v_dcin>;
+
+	};
+
+	/* m.2 sata power */
+	vcc5v0_sata: vcc5v0-sata {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sata";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		regulator-always-on;
+
+		enable-active-high;
+		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sata_pwr_en>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_ue0_reg: vcc5v0-ue0-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vcc5v0_ue0_regulator";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		regulator-always-on;
+
+		enable-active-high;
+		gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_ue0_reg_en>;
+
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_ue1_reg: vcc5v0-ue1-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vcc5v0_ue1_regulator";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		regulator-always-on;
+
+		enable-active-high;
+		gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_ue1_reg_en>;
+
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+/* for sata0 & usb_host0_xhci */
+&combphy0 {
+	status = "okay";
+};
+
+/* for sata1 & usb_host1_xhci */
+&combphy1 {
+	status = "okay";
+};
+
+/* for sata2 & pcie2x1 */
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	phy-mode = "rgmii";
+	label = "eth3";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 50000 200000>;
+	tx_delay = <0x36>;
+	rx_delay = <0x29>;
+	phy-handle = <&rgmii_phy0>;
+	status = "okay";
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	label = "eth2";
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus>;
+	snps,reset-gpio = <&gpio2 RK_PD7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 50000 200000>;
+	tx_delay = <0x46>;
+	rx_delay = <0x26>;
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#sound-dai-cells = <0>;
+
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		pwrkey {
+			status = "okay";
+		};
+
+		pinctrl_rk8xx: pinctrl_rk8xx {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			rk817_slppin_null: rk817_slppin_null {
+				pins = "gpio_slp";
+				function = "pin_fun0";
+			};
+
+			rk817_slppin_slp: rk817_slppin_slp {
+				pins = "gpio_slp";
+				function = "pin_fun1";
+			};
+
+			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
+				pins = "gpio_slp";
+				function = "pin_fun2";
+			};
+
+			rk817_slppin_rst: rk817_slppin_rst {
+				pins = "gpio_slp";
+				function = "pin_fun3";
+			};
+		};
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+		rk809_codec: codec {
+			#sound-dai-cells = <0>;
+			compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
+			clocks = <&cru I2S1_MCLKOUT_TX>;
+			clock-names = "mclk";
+			assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+			assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2s1m0_mclk>;
+			hp-volume = <20>;
+			spk-volume = <3>;
+			mic-in-differential;
+			status = "okay";
+		};
+	};
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		phy-supply = <&vcc3v3_sys>;
+		reg = <0x1>;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		phy-supply = <&vcc3v3_sys>;
+		reg = <0x1>;
+	};
+};
+
+&pcie2x1 {
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie2>;
+	status = "okay";
+};
+
+&pcie30phy {
+	data-lanes = <1 2>;
+	status = "okay";
+};
+
+&pcie3x1 {
+	num-lanes = <1>;
+	reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie3>;
+	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x00100000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		rtl8125_1: pcie-ethernet@10,0 {
+			compatible = "pci10ec,8125";
+			label = "eth1";
+			reg = <0x000000 0 0 0 0>;
+			realtek,led-data = <0x0200>;
+		};
+	};
+};
+
+&pcie3x2 {
+	num-lanes = <1>;
+	rockchip,init-delay-ms = <100>;
+	reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie3>;
+	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x00200000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		rtl8125_2: pcie-ethernet@20,0 {
+			compatible = "pci10ec,8125";
+			label = "eth0";
+			reg = <0x000000 0 0 0 0>;
+			realtek,led-data = <0x0200>;
+		};
+	};
+};
+
+&pinctrl {
+	button {
+		reset_button_pin: reset-button-pin {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	leds {
+		led_green_en: led-green-en {
+			rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_net_en: led-net-en {
+			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_work_en: led-work-en {
+			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	modem {
+		vcc3v8_lte_pwr_en:  vcc3v8_lte_pwr-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		lte_modem_reset: lte-modem-reset {
+			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		vcc3v3_pcie2_en: vcc3v3_pcie2_en {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc3v3_pcie3_en: vcc3v3_pcie3_en {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic-int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sd {
+		vcc3v3_sd_en: vcc3v3-sd_en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_ue0_reg_en: vcc5v0-ue0-reg-en {
+			rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_ue1_reg_en: vcc5v0-ue1-reg-en {
+			rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sata {
+		sata_pwr_en: sata-pwr-en {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&sata0 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	status = "disabled";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	usb_hub: usb-hub@1 {
+		compatible = "usb5e3,620";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		label = "genesys,gl3523";
+		reg = <0x1>;
+
+		rtl8153_1: usb-ethernet@2 {
+			compatible = "usbbda,8153";
+			reg = <0x2>;
+			label = "eth4";
+			//realtek,led-data = <0x87>;
+		};
+
+		rtl8153_2: usb-ethernet@3 {
+			compatible = "usbbda,8153";
+			reg = <0x3>;
+			label = "eth5";
+			//realtek,led-data = <0x87>;
+		};
+	};
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb>;
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&cpu_thermal {
+	trips {
+		cpu_cool: cpu_cool {
+			temperature = <45000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_warm: cpu_warm {
+			temperature = <55000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_hot: cpu_hot {
+			temperature = <65000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map1 {
+			trip = <&cpu_cool>;
+			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+		};
+
+		map2 {
+			trip = <&cpu_warm>;
+			cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+		};
+
+		map3 {
+			trip = <&cpu_hot>;
+			cooling-device = <&fan 3 THERMAL_NO_LIMIT>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-watermelon-core.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-watermelon-core.dtsi
new file mode 100644
index 000000000..e5fe5e8ba
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-watermelon-core.dtsi
@@ -0,0 +1,512 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2023 unifreq <https://github.com/unifreq>
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	aliases {
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+	};
+
+	chosen: chosen {
+		bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyS2,1500000";
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cma: cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x10000000>;
+			linux,cma-default;
+		};
+
+		ramoops: ramoops@110000 {
+			compatible = "ramoops";
+			reg = <0x0 0x110000 0x0 0xf0000>;
+			record-size = <0x20000>;
+			console-size = <0x80000>;
+			ftrace-size = <0x00000>;
+			pmsg-size = <0x50000>;
+		};
+	};
+
+	adc_keys: adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1750000>;
+
+		button_reset: button-reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			press-threshold-microvolt = <0>;
+		};
+	};
+
+	vcc_5v0_in: vcc-5v0-in {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc_5v0_in";
+	};
+
+	vcc_sysin_b: vcc-sysin-b {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sysin_b";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <4000000>;
+		regulator-max-microvolt = <4000000>;
+		vin-supply = <&vcc_5v0_in>;
+	};
+
+	/* Enabled when PMIC_SLEEP_H down */
+	vcc_3v3: vcc-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	/* Enabled when vcca_1v8_en up */
+	vcc_1v8: vcc-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcca_1v8_en>;
+	};
+
+	vcc_1v8_image: vcc-1v8-image {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8_image";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8>;
+	};
+
+	vcc_1v8_ddr: vcc-1v8-ddr {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8_ddr";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcca1v8_pmu>;
+	};
+
+	vcc_0v6_ddr: vcc_0v6_ddr {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_0v6_ddr";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <600000>;
+		regulator-max-microvolt = <600000>;
+		vin-supply = <&vcc_1v8_ddr>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: tcs4525@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		vin-supply = <&vcc_sysin_b>;
+		regulator-compatible = "fan53555-reg";
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1390000>;
+		regulator-init-microvolt = <900000>;
+		regulator-initial-mode = <1>;
+		regulator-ramp-delay = <2300>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-boot-on;
+		regulator-always-on;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk817: pmic@20 {
+		compatible = "rockchip,rk817";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-names = "default", "pmic-sleep",
+				"pmic-power-off", "pmic-reset";
+		pinctrl-0 = <&pmic_int>;
+		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
+		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
+		pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
+		system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+		//fb-inner-reg-idxs = <2>;
+		/* 1: rst regs (default in codes), 0: rst the pmic */
+		pmic-reset-func = <0>;
+
+		vcc1-supply = <&vcc_sysin_b>;
+		vcc2-supply = <&vcc_sysin_b>;
+		vcc3-supply = <&vcc_sysin_b>;
+		vcc4-supply = <&vcc_sysin_b>;
+		vcc5-supply = <&vcc_sysin_b>;
+		vcc6-supply = <&vcc_sysin_b>;
+		vcc7-supply = <&vcc_sysin_b>;
+		vcc8-supply = <&vcc_sysin_b>;
+		vcc9-supply = <&dcdc_boost>;
+
+		pwrkey {
+			status = "okay";
+		};
+
+		pinctrl_rk8xx: pinctrl_rk8xx {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			rk817_slppin_null: rk817_slppin_null {
+				pins = "gpio_slp";
+				function = "pin_fun0";
+			};
+
+			rk817_slppin_slp: rk817_slppin_slp {
+				pins = "gpio_slp";
+				function = "pin_fun1";
+			};
+
+			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
+				pins = "gpio_slp";
+				function = "pin_fun2";
+			};
+
+			rk817_slppin_rst: rk817_slppin_rst {
+				pins = "gpio_slp";
+				function = "pin_fun3";
+			};
+		};
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_logic";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_gpu";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc3v3_sys: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc3v3_sys";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdda_0v9_p: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9_p";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_acodec";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8_en: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8_en";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image_p: LDO_REG8 {
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image_p";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_image_p: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image_p";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			dcdc_boost: BOOST {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <4700000>;
+				regulator-max-microvolt = <5400000>;
+				regulator-name = "boost";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			otg_switch: OTG_SWITCH {
+				regulator-name = "otg_switch";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+		rk817_codec: codec {
+			mic-in-differential;
+		};
+	};
+};
+
+&pinctrl {
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		soc_slppin_gpio: soc_slppin_gpio {
+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+
+		soc_slppin_rst: soc_slppin_rst {
+			rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
+		};
+
+		soc_slppin_slp: soc_slppin_slp {
+			rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	//fixed, pmuio0-supply = <&vcca1v8_pmu>;
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	//configure by hardware FLASH_VOL_SEL pin, vccio2-supply = <&vcca_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcca1v8_pmu>;
+
+	/*
+	 * v1 & v2 uses vcc_1v8
+	 * v3 uses vcc_3v3
+	 */
+	vccio5-supply = <&vcc_1v8>;
+
+	vccio6-supply = <&vcca1v8_pmu>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vcca_1v8_en>;
+};
+
+&sdhci {
+	bus-width = <8>;
+	supports-emmc;
+	no-sdio;
+	no-sd;
+	non-removable;
+	max-frequency = <200000000>;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	full-pwr-cycle-in-suspend;
+	status = "okay";
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&vepu {
+	status = "okay";
+};
+
+&vepu_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>, <&cru PLL_GPLL>;
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-watermelon-pi-v3.dts b/arch/arm64/boot/dts/rockchip/rk3568-watermelon-pi-v3.dts
new file mode 100644
index 000000000..5b328686a
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-watermelon-pi-v3.dts
@@ -0,0 +1,546 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2023 unifreq <https://github.com/unifreq>
+
+/dts-v1/;
+
+#include "rk3568-watermelon-core.dtsi"
+
+/ {
+	model = "NLnet Watermelon Pi V3";
+	compatible = "nlnet,watermelon-pi-v3", "rockchip,rk3568";
+
+	gpio_leds: gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&sys_led_pin &net_led_pin>;
+
+		sys_led: sys-led {
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+			label = "blue:sys";
+			linux,default-trigger = "heartbeat";
+		};
+
+		net_led: net-led {
+			gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
+			label = "blue:net";
+		};
+	};
+
+	pwm_leds: pwm-leds {
+		compatible = "pwm-leds";
+
+		pwm_led: pwm-led {
+			label = "blue:pwm";
+			pwms = <&pwm5 0 1000000 0>;
+			max-brightness = <255>;
+		};
+
+		backlight: backlight {
+			label = "lcd:backlight";
+			pwms = <&pwm14 0 1000000 0>;
+			max-brightness = <255>;
+			linux,default-trigger = "default-on";
+		};
+	};
+
+	dc_in: dc-in {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_in";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc_5v0_mainboard: vcc_5v0-mainboard {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_mainboard";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_in>;
+	};
+
+	/*
+	 * Default is 3.8v
+	 * Connect to battery positive terminal if it is present
+	 */
+	vcc_3v7_mainboard: vcc-3v7-mainboard {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v7_mainboard";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+		vin-supply = <&dc_in>;
+	};
+
+	vcc_3v3_mainboard: vcc-3v3-mainboard {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_mainboard";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_in>;
+	};
+
+	vcc_3v3_pi6c: vcc-3v3-pi6c {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_pi6c";
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_pwr_en>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_5v0_mainboard>;
+	};
+
+	/* gpio: same as vcc_3v3_pi6c */
+	vcc_3v3_pcie: vcc-3v3-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_pcie";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_mainboard>;
+	};
+
+	/* gpio: same as vcc_3v3_pi6c */
+	vcc_3v7_modem: vcc-3v7-modem {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v7_modem";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+		vin-supply = <&vcc_3v7_mainboard>;
+	};
+
+	vcc5v0_usb_otg0: vcc5v0-usb-otg0 {
+		compatible = "regulator-fixed";
+		regulator-boot-on;
+		regulator-always-on;
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg0_en>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vcc5v0_usb_otg0";
+		vin-supply = <&vcc_5v0_mainboard>;
+	};
+
+	vcc_3v3_sd: vcc-3v3-sd {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_sd";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_mainboard>;
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	fan0: pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		pwms = <&pwm7 0 50000 0>;
+		cooling-levels = <0 102 170 230>;
+		pulses-per-revolution = <2>;
+		fan-supply = <&vcc_5v0_mainboard>;
+	};
+};
+
+&combphy0 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu_thermal {
+	trips {
+		cpu_cool: cpu_cool {
+			temperature = <45000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_warm: cpu_warm {
+			temperature = <55000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_hot: cpu_hot {
+			temperature = <65000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map1 {
+			trip = <&cpu_cool>;
+			cooling-device = <&fan0 THERMAL_NO_LIMIT 1>;
+		};
+
+		map2 {
+			trip = <&cpu_warm>;
+			cooling-device = <&fan0 2 THERMAL_NO_LIMIT>;
+		};
+
+		map3 {
+			trip = <&cpu_hot>;
+			cooling-device = <&fan0 3 THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image_p>;
+	avdd-1v8-supply = <&vcca1v8_image_p>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&pmu_io_domains {
+        /*
+         * v1 & v2 uses vcc_1v8
+         * v3 uses vcc_3v3
+         */
+	vccio5-supply = <&vcc_3v3>;
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x36>;
+	rx_delay = <0x2c>;
+	phy-handle = <&rgmii_phy0>;
+	status = "okay";
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus>;
+	snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x44>;
+	rx_delay = <0x28>;
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		phy-supply = <&vcc_3v3_mainboard>;
+		reg = <0x1>;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		phy-supply = <&vcc_3v3_mainboard>;
+		reg = <0x1>;
+	};
+};
+
+&pcie2x1 {
+	reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_pcie>;
+	status = "okay";
+};
+
+&pcie30phy {
+	data-lanes = <1 2>;
+	status = "okay";
+};
+
+&pcie3x2 {
+	num-lanes = <1>;
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v7_modem>;
+	status = "okay";
+};
+
+&pcie3x1 {
+	num-lanes = <1>;
+	reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_pcie>;
+	status = "okay";
+};
+
+&pwm3 {
+	compatible = "rockchip,remotectl-pwm";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm3_pins>;
+	remote_pwm_id = <3>;
+	handle_cpu_id = <1>;
+	remote_support_psci = <0>;
+	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+	     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+	status = "okay";
+
+	/* China Mobile TV Box */
+	ir_key1 {
+		rockchip,usercode = <0xdd22>;
+		rockchip,key_table =
+			<0x6a	KEY_BACK>,
+			<0x35	KEY_UP>,
+			<0x2d	KEY_DOWN>,
+			<0x66	KEY_LEFT>,
+			<0x3e	KEY_RIGHT>,
+			<0x31	0x161>, //KEY_CENTER
+			<0x77	KEY_HOME>,
+			<0x7f	KEY_VOLUMEUP>,
+			<0x7e	KEY_VOLUMEDOWN>,
+			<0x23	KEY_POWER>,
+			<0x7d	KEY_MENU>,
+			<0x7a	0x192>, //KEY_CHANNELUP
+			<0x79	0x193>, //KEY_CHANNELDOWN
+			<0x72	0x96>, //KEY_EXPLORER (SETTING)
+			<0xf	KEY_SEARCH>, //KEY_SEARCH 'M'
+			<0x6d	KEY_1>,
+			<0x6c	KEY_2>,
+			<0x33	KEY_3>,
+			<0x71	KEY_4>,
+			<0x70	KEY_5>,
+			<0x37	KEY_6>,
+			<0x75	KEY_7>,
+			<0x74	KEY_8>,
+			<0x3b	KEY_9>,
+			<0x78	KEY_0>,
+			<0x2f	KEY_NUMERIC_STAR>,  /* * key */
+			<0x25	KEY_NUMERIC_POUND>; /* # key */
+	};
+};
+
+&pwm5 {
+	pinctrl-0 = <&pwm5_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&pwm7 {
+	pinctrl-0 = <&pwm7_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&pwm14 {
+	pinctrl-0 = <&pwm14m0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&pinctrl {
+	leds {
+		sys_led_pin: sys-led-pin {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		net_led_pin: net-led-pin {
+			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	lcd_display {
+		spi3_sck: spi3-sck {
+			rockchip,pins = <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>;
+		};
+
+		spi3_mosi: spi3-mosi {
+			rockchip,pins = <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>;
+		};
+
+		lcd_reset_pin: lcd-reset-pin {
+			rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		lcd_dc_pin: display_dc_pin {
+			rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up_drv_level_1>;
+		};
+	};
+
+        pcie {
+		pcie_pwr_en: pcie-pwr-en {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	modem {
+		modem_reset_pins: modem-reset-pins {
+			rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_otg0_en: vcc5v0_usb_otg0_en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&sdmmc0 {
+	max-frequency = <150000000>;
+	bus-width = <4>;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	supports-sd;
+	disable-wp;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	card-detect-delay = <800>;
+	status = "okay";
+};
+
+&spi3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi3m1_cs0_hs &spi3_sck &spi3_mosi>;
+	status = "okay";
+
+	lcd_display: lcd-display@0 {
+		compatible = "sitronix,st7735r";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		rotate = <0>;
+		dc-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd_dc_pin &lcd_reset_pin>;
+		backlight = <&backlight>;
+		buswidth = <8>;
+		debug = <0x0>;
+		status = "disabled";
+	};
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc_5v0_mainboard>;
+	pinctrl-0 = <&modem_reset_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	vbus-supply = <&vcc5v0_usb_otg0>;
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	extcon = <&usb2phy0>;
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc_5v0_mainboard>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc_5v0_mainboard>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&vcc_5v0_in {
+	vin-supply = <&vcc_5v0_mainboard>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-watermelon-pi.dts b/arch/arm64/boot/dts/rockchip/rk3568-watermelon-pi.dts
new file mode 100644
index 000000000..f825778bf
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-watermelon-pi.dts
@@ -0,0 +1,547 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2023 unifreq <https://github.com/unifreq>
+
+/dts-v1/;
+
+#include "dt-bindings/usb/pd.h"
+#include "rk3568-watermelon-core.dtsi"
+
+/ {
+	model = "NLnet Watermelon Pi";
+	compatible = "nlnet,watermelon-pi", "rockchip,rk3568";
+
+	gpio_leds: gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&sys_led_pin &net_led_pin>;
+
+		sys_led: sys-led {
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+			label = "blue:sys";
+			linux,default-trigger = "heartbeat";
+		};
+
+		net_led: net-led {
+			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+			label = "blue:net";
+		};
+	};
+
+	backlight: backlight {
+		compatible = "gpio-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&backlight_led_pin>;
+		gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
+		default-on;
+	};
+
+	vbus_typec: vbus_typec {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vbus_typec";
+	};
+
+	vcc_5v0_mainboard: vcc_5v0-mainboard {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_mainboard";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vbus_typec>;
+	};
+
+	vcc_3v3_mainboard: vcc-3v3-mainboard {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_mainboard";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vbus_typec>;
+	};
+
+	vcc_3v3_pi6c: vcc-3v3-pi6c {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_pi6c";
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_pwr_en>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_5v0_mainboard>;
+	};
+
+	/* gpio: same as vcc_3v3_pi6c */
+	vcc_3v3_pcie: vcc-3v3-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_pcie";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_mainboard>;
+	};
+
+	/* gpio: same as vcc_3v3_pi6c */
+	vcc_3v3_modem: vcc-3v3-modem {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_modem";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_mainboard>;
+	};
+
+	vcc5v0_usb_otg0: vcc5v0-usb-otg0 {
+		compatible = "regulator-fixed";
+		regulator-boot-on;
+		regulator-always-on;
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg0_en>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vcc5v0_usb_otg0";
+		vin-supply = <&vcc_5v0_mainboard>;
+	};
+
+	vcc_3v3_sd: vcc-3v3-sd {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_sd";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_mainboard>;
+	};
+
+	hdmi_con: hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	fan0: pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		pwms = <&pwm7 0 50000 0>;
+		cooling-levels = <0 102 170 230>;
+		pulses-per-revolution = <2>;
+		fan-supply = <&vcc_5v0_mainboard>;
+	};
+};
+
+&combphy0 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu_thermal {
+	trips {
+		cpu_cool: cpu_cool {
+			temperature = <45000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_warm: cpu_warm {
+			temperature = <55000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_hot: cpu_hot {
+			temperature = <65000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map1 {
+			trip = <&cpu_cool>;
+			cooling-device = <&fan0 THERMAL_NO_LIMIT 1>;
+		};
+
+		map2 {
+			trip = <&cpu_warm>;
+			cooling-device = <&fan0 2 THERMAL_NO_LIMIT>;
+		};
+
+		map3 {
+			trip = <&cpu_hot>;
+			cooling-device = <&fan0 3 THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image_p>;
+	avdd-1v8-supply = <&vcca1v8_image_p>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x36>;
+	rx_delay = <0x2c>;
+	phy-handle = <&rgmii_phy0>;
+	status = "okay";
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus>;
+	snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x44>;
+	rx_delay = <0x28>;
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&i2c0 {
+	fusb0: usb-typec@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fusb0_int>;
+		vbus-supply = <&vbus_typec>;
+		status = "disabled";
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			power-role = "sink";
+			try-power-role = "sink";
+			op-sink-microwatt = <1000000>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+					PDO_FIXED(9000, 2000, PDO_FIXED_USB_COMM)
+					PDO_FIXED(12000, 1500, PDO_FIXED_USB_COMM)
+					PDO_VAR(5000, 12000, 3000)>;
+		};
+	};
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		phy-supply = <&vcc_3v3_mainboard>;
+		reg = <0x1>;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		phy-supply = <&vcc_3v3_mainboard>;
+		reg = <0x1>;
+	};
+};
+
+&pcie2x1 {
+	reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_pcie>;
+	status = "okay";
+};
+
+&pcie30phy {
+	data-lanes = <1 2>;	
+	status = "okay";
+};
+
+&pcie3x2 {
+	num-lanes = <1>;
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_modem>;
+	status = "okay";
+};
+
+&pcie3x1 {
+	num-lanes = <1>;
+	reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_pcie>;
+	status = "okay";
+};
+
+&pmu_io_domains {
+        /*
+         * v1 & v2 uses vcc_1v8
+         * v3 uses vcc_3v3
+         */
+        vccio5-supply = <&vcc_1v8>;
+};
+
+&pwm3 {
+	compatible = "rockchip,remotectl-pwm";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm3_pins>;
+	remote_pwm_id = <3>;
+	handle_cpu_id = <1>;
+	remote_support_psci = <0>;
+	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+	     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+	status = "okay";
+
+	/* China Mobile TV Box */
+	ir_key1 {
+		rockchip,usercode = <0xdd22>;
+		rockchip,key_table =
+			<0x6a	KEY_BACK>,
+			<0x35	KEY_UP>,
+			<0x2d	KEY_DOWN>,
+			<0x66	KEY_LEFT>,
+			<0x3e	KEY_RIGHT>,
+			<0x31	0x161>, //KEY_CENTER
+			<0x77	KEY_HOME>,
+			<0x7f	KEY_VOLUMEUP>,
+			<0x7e	KEY_VOLUMEDOWN>,
+			<0x23	KEY_POWER>,
+			<0x7d	KEY_MENU>,
+			<0x7a	0x192>, //KEY_CHANNELUP
+			<0x79	0x193>, //KEY_CHANNELDOWN
+			<0x72	0x96>, //KEY_EXPLORER (SETTING)
+			<0xf	KEY_SEARCH>, //KEY_SEARCH 'M'
+			<0x6d	KEY_1>,
+			<0x6c	KEY_2>,
+			<0x33	KEY_3>,
+			<0x71	KEY_4>,
+			<0x70	KEY_5>,
+			<0x37	KEY_6>,
+			<0x75	KEY_7>,
+			<0x74	KEY_8>,
+			<0x3b	KEY_9>,
+			<0x78	KEY_0>,
+			<0x2f	KEY_NUMERIC_STAR>,  /* * key */
+			<0x25	KEY_NUMERIC_POUND>; /* # key */
+	};
+};
+
+&pwm7 {
+	pinctrl-0 = <&pwm7_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&pinctrl {
+
+	leds {
+		sys_led_pin: sys-led-pin {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		net_led_pin: net-led-pin {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	lcd_display {
+		backlight_led_pin: backlight-led-pin {
+			rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		spi3_sck: spi3-sck {
+			rockchip,pins = <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>;
+		};
+
+		spi3_mosi: spi3-mosi {
+			rockchip,pins = <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>;
+		};
+
+		lcd_reset_pin: lcd-reset-pin {
+			rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		lcd_dc_pin: display_dc_pin {
+			rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up_drv_level_1>;
+		};
+	};
+
+	fusb30x {
+		fusb0_int: fusb0-int {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+        pcie {
+		pcie_pwr_en: pcie-pwr-en {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	modem {
+		modem_reset_pins: modem-reset-pins {
+			rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_otg0_en: vcc5v0_usb_otg0_en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&sdmmc0 {
+	max-frequency = <150000000>;
+	bus-width = <4>;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	supports-sd;
+	disable-wp;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	card-detect-delay = <800>;
+	status = "okay";
+};
+
+&spi3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi3m1_cs0_hs &spi3_sck &spi3_mosi>;
+	status = "okay";
+
+	lcd_display: lcd-display@0 {
+		compatible = "sitronix,st7735r";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		rotate = <0>;
+		dc-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd_dc_pin &lcd_reset_pin>;
+		backlight = <&backlight>;
+		buswidth = <8>;
+		debug = <0x0>;
+		status = "disabled";
+	};
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc_5v0_mainboard>;
+	pinctrl-0 = <&modem_reset_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	vbus-supply = <&vcc5v0_usb_otg0>;
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	extcon = <&usb2phy0>;
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc_5v0_mainboard>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc_5v0_mainboard>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&vcc_5v0_in {
+	vin-supply = <&vcc_5v0_mainboard>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-wocyber-a3.dts b/arch/arm64/boot/dts/rockchip/rk3568-wocyber-a3.dts
new file mode 100644
index 000000000..93c186d03
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-wocyber-a3.dts
@@ -0,0 +1,726 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "Wocyber A3";
+	compatible = "rockchip,wocyber-a3", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		brightness-levels = <20 220>;
+		default-brightness-level = <100>;
+		num-interpolated-steps = <200>;
+		power-supply = <&vcc3v3_sys>;
+		pwms = <&pwm4 0 25000 0>;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	dc_12v: regulator-dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_work: led-0 {
+			gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_BLUE>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_work_en>;
+		};
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	vcc3v3_sys: regulator-vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb: regulator-vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb_host: regulator-vcc5v0-usb-host {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en>;
+		regulator-name = "vcc5v0_usb_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc5v0_usb_otg: regulator-vcc5v0-usb-otg {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
+		regulator-name = "vcc5v0_usb_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc3v3_lcd0_n: regulator-vcc3v3-lcd0-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd0_n";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc3v3_sys>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_lcd0_n_en>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vcc3v3_lcd1_n: regulator-vcc3v3-lcd1-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd1_n";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc3v3_sys>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_lcd1_n_en>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&combphy0 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&sata2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sata2_pins>;
+	assigned-clock-rates = <24000000>;
+	status = "okay";
+};
+
+&dsi0_in {
+	status = "disabled";
+	dsi0_in_vp1: endpoint {
+		remote-endpoint = <&vp1_out_dsi0>;
+	};
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy0>;
+	phy-mode = "rgmii";
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 20000 100000>;
+	snps,reset-gpio = <&gpio3 13 1>;
+	rx_delay = <47>;
+	tx_delay = <60>;	
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+	status = "okay";
+};
+
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+		system-power-controller;
+		#sound-dai-cells = <0>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+		codec {
+			rockchip,mic-in-differential;
+		};
+	};
+};
+
+&i2c1 {
+	status = "disabled";
+
+	touchscreen0: goodix@14 {
+		compatible = "goodix,gt1151";
+		reg = <0x14>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB5 IRQ_TYPE_EDGE_FALLING>;
+		AVDD28-supply = <&vcc3v3_lcd0_n>;
+		irq-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touch_int &touch_rst>;
+		reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+		VDDIO-supply = <&vcc3v3_lcd0_n>;
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+		clocks = <&cru &i2s1m0_sclktx>;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pinctrl {
+	display {
+		vcc3v3_lcd0_n_en: vcc3v3_lcd0_n_en {
+			rockchip,pins = <0 RK_PC7 0 &pcfg_pull_none>;
+		};
+		vcc3v3_lcd1_n_en: vcc3v3_lcd1_n_en {
+			rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_work_en: led_work_en {
+			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	touchscreen {
+		touch_int: touch_int {
+			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+		touch_rst: touch_rst {
+			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_host_en: vcc5v0_usb_host_en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pmucru {
+	rockchip,pmugrf = <&pmugrf>;
+	rockchip,grf = <&grf>;
+};
+
+&pwm4 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&backlight {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	extcon = <&usb2phy0>;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru PLL_VPLL>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&xin24m>, <&cru PLL_VPLL>;
+	assigned-clock-rates = <0>, <132000000>, <132000000>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
+
+&vp1 {
+	vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
+		reg = <ROCKCHIP_VOP2_EP_MIPI0>;
+		remote-endpoint = <&dsi0_in_vp1>;
+	};
+};
\ No newline at end of file


================================================
FILE: kernel-patch/beta/deprecated-patches/6.18.y-307-dts-add-rk3588-series-devices.patch
================================================
From c232ed27f5c93dae492884f57071534ca34778e0 Mon Sep 17 00:00:00 2001
From: ophub <68696949+ophub@users.noreply.github.com>
Date: Sat, 31 Jan 2026 20:38:07 +0800
Subject: [PATCH] arch: arm64: dts: rockchip: add rk3588 Series devices

---
 arch/arm64/boot/dts/rockchip/Makefile         |    7 +
 .../dts/rockchip/rk3588-hlink-h88k-v3.dts     |   69 +
 .../dts/rockchip/rk3588-hlink-h88k-v31.dts    | 1614 +++++++++++++++++
 .../boot/dts/rockchip/rk3588-hlink-h88k.dts   |   50 +
 .../arm64/boot/dts/rockchip/rk3588-hlink.dtsi | 1191 ++++++++++++
 .../boot/dts/rockchip/rk3588s-radxa-e52c.dts  |  872 +++++++++
 .../dts/rockchip/rk3588s-radxa-e54c-dsa.dts   |   96 +
 .../dts/rockchip/rk3588s-radxa-e54c-v1.dts    |   90 +
 .../boot/dts/rockchip/rk3588s-radxa-e54c.dts  | 1259 +++++++++++++
 9 files changed, 5248 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-hlink-h88k-v3.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-hlink-h88k-v31.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-hlink-h88k.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-hlink.dtsi
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-radxa-e52c.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-radxa-e54c-dsa.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-radxa-e54c-v1.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-radxa-e54c.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index bf8251e6d..c5d6ec738 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -206,6 +206,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h96-max-v58.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-hlink-h88k.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-hlink-h88k-v3.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-hlink-h88k-v31.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar-ethernet-switch.dtbo
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar-pre-ict-tester.dtbo
@@ -238,6 +241,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-e52c.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-e54c.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-e54c-dsa.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-e54c-v1.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-roc-pc.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-hlink-h88k-v3.dts b/arch/arm64/boot/dts/rockchip/rk3588-hlink-h88k-v3.dts
new file mode 100644
index 000000000..9d48323e0
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-hlink-h88k-v3.dts
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2023 Flippy <flippy@sina.com>
+
+/dts-v1/;
+
+#include "rk3588-hlink.dtsi"
+
+/ {
+	model = "Hlink H88K-V3";
+	compatible = "hlink,h88k", "rockchip,rk3588";
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&gmac0 {
+	phy-mode = "rgmii";
+	tx_delay = <0x42>;
+	rx_delay = <0x34>;
+};
+
+/*
+ * RTL8125B 2.5g ethernet
+ * phy is combphy0_ps
+ */
+&pcie2x1l2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_2_rst>;	
+	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x00400000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		bus-range = <0x40 0x4f>;
+		device_type = "pci";
+		ranges;
+
+		rtl8125_2: pcie-eth@0,0 {
+			compatible = "pci10ec,8125";
+			label = "eth2";
+			reg = <0x410000 0 0 0 0>;
+
+			/* G+ 3v3
+			 * G- LED3: LINK on 100 + 1000 + 2500
+			 * Y+ 3v3
+			 * Y- LED2: ACT on all speed
+			 */
+			r8125,led2 = <0x0200>;
+			r8125,led3 = <0x002a>;
+		};
+	};
+};
+
+&pinctrl {
+	pcie2 {
+		pcie2_2_rst: pcie2-2-rst {
+			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&sdmmc {
+	max-frequency = <200000000>;
+	sd-uhs-sdr104;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-hlink-h88k-v31.dts b/arch/arm64/boot/dts/rockchip/rk3588-hlink-h88k-v31.dts
new file mode 100644
index 000000000..59d96b00f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-hlink-h88k-v31.dts
@@ -0,0 +1,1614 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2025 Flippy <flippy@sina.com>
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588.dtsi"
+
+/ {
+	model = "Hlink H88K V3.1";
+	compatible = "hlink,h88k-v31", "hlink,h88k-v3", "rockchip,rk3588";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdhci;
+		mmc2 = &sdio;
+		rtc0 = &hym8563;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	analog_sound: analog-sound {
+		compatible = "simple-audio-card";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_detect>;
+		simple-audio-card,name = "rockchip,es8388";
+		simple-audio-card,bitclock-master = <&masterdai>;
+		simple-audio-card,format = "i2s";
+		simple-audio-card,frame-master = <&masterdai>;
+		simple-audio-card,hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,pin-switches = "Headphones";
+		simple-audio-card,routing =
+			"Headphones", "LOUT1",
+			"Headphones", "ROUT1",
+			"LINPUT1", "Microphone Jack";
+		simple-audio-card,widgets =
+			"Microphone", "Microphone Jack",
+			"Headphone", "Headphones";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0_8ch>;
+		};
+
+		masterdai: simple-audio-card,codec {
+			sound-dai = <&es8388>;
+			system-clock-frequency = <12288000>;
+		};
+	};
+
+	hdmi0-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi0_con_in: endpoint {
+				remote-endpoint = <&hdmi0_out_con>;
+			};
+		};
+	};
+
+	hdmi1-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi1_con_in: endpoint {
+				remote-endpoint = <&hdmi1_out_con>;
+			};
+		};
+	};
+
+	gpio_leds: gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_red_ai_pin>,
+		            <&led_green_work_pin>,
+		            <&led_blue_sata_pin>,
+		            <&led_amber_net_pin>;
+
+		led_red_ai: led-red-ai {
+			label = "red:ai";
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+
+		led_green_work: led-green-work {
+			label = "green:work";
+			gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_blue_sata: led-blue-sata {
+			label = "blue:sata";
+			gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_amber_net: led-amber-net {
+			label = "amber:net";
+			gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	/* dc-in or typec-in: maximum supported voltage: 22V */
+	vcc12v_dcin: vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	/* vcc4v0_sys
+	 * supply by dc_in
+	 * DC-DC convert by MP2491C
+	 * maximum load current 6A
+	 */
+	vcc4v0_sys: vcc4v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc4v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <4000000>;
+		regulator-max-microvolt = <4000000>;
+		startup-delay-us = <100000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	/* vcc3v3_sys
+	 * supply by dc_in, but enabled by vcc4v0_sys
+	 * DC-DC convert by MP2491C
+	 * maximum load current 6A
+	 */
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <100000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	/* vcc5v0_usb:
+	 * supply by dc_in, but enabled by vcc3v3_sys
+	 * DC-DC convert by MP2491C
+	 * maximum load current 6A
+	 */
+	vcc5v0_usb: vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	/* vbusb5v0 typec
+	 * power switch by TMI6263BH
+	 */
+	vbus5v0_typec: vbus5v0-typec {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus5v0_typec";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		enable-active-high;
+		gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vbus5v0_typec_en>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	/* vcc5v0 usbhost
+	 * power switch by TMI6263BH
+	 */
+	vcc5v0_usb_host: vcc5v0-usb-host {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	/* vcc3v8_modem
+	 * DC-DC convert by MP2315
+	 * maximum load current 3A
+	 */
+	vcc3v8_modem: vcc3v8-modem {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+		gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+		regulator-min-microvolt = <3800000>;
+		regulator-max-microvolt = <3800000>;
+		regulator-name = "vcc3v8_modem";
+		pinctrl-names = "default";
+		pintctrl-0 = <&vcc3v8_modem_pwren>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	/* 
+	 * vcc3v3 hub
+	 */
+	vcc3v3_hub: vcc3v3-hub {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_hub";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	/*
+	 * vdd1v2_hub:
+	 * DC-DC 1.2V for GL3523 USB HUB
+	 * convert by SY8089A1AAC
+	 * maximum load current 2A
+	 */
+	vdd1v2_hub: vdd1v2-hub {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd1v2_hub";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		vin-supply = <&vcc4v0_sys>;
+	};
+
+	/* avdd1v2_hub:
+	 * LDO 1.2V for GL3523 USB HUB
+	 */
+	avdd1v2_hub: avdd1v2-hub {
+		compatible = "regulator-fixed";
+		regulator-name = "avdd1v2_hub";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	/* Actually, pull the reset pin of the USB hub high */
+	usb_hub_en: usb-hub-en {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		pinctrl-names = "default";
+		pintctrl-0 = <&usb_hub_rst_pin>;
+		gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "usb-hub-en";
+		startup-delay-us = <50000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_pcie20: vcc3v3-pcie20 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie20";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc4v0_sys>;
+	};
+
+	vcc3v3_pcie30: vcc3v3-pcie30 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie30";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <100000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v0_lcd: vcc3v0-lcd {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v0_lcd";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+		vin-supply = <&vcc4v0_sys>;
+	};
+
+	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc4v0_sys>;
+	};
+
+	/* wifi regon support some wifi modules like rtl8723be */
+	wifi_regon: wifi-regon {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-name = "wifi_regon";
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc_1v8_s3>;
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		cooling-levels = <0 64 128 192 255>;
+		pwms = <&pwm9 0 50000 0>;
+	};
+
+	rfkill_modem: rfkill {
+		compatible = "rfkill-gpio";
+		label = "rfkill-modem";
+		radio-type = "wwan";
+		reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&modem_reset_pin>;
+		status = "okay";
+	};
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&combphy1_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	status = "okay";
+};
+
+/* gmac0: eth2 */
+&gmac0 {
+	status = "okay";
+	label = "eth2";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+
+	phy-handle = <&rgmii_phy>;
+
+	clock_in_out = "output";
+	phy-mode = "rgmii";
+	tx_delay = <0x3e>;
+	rx_delay = <0x2f>;
+
+	snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+};
+
+&hdmi0 {
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&hdmi0_out {
+	hdmi0_out_con: endpoint {
+		remote-endpoint = <&hdmi0_con_in>;
+	};
+};
+
+&hdmi0_sound {
+	status = "okay";
+};
+
+&hdmi1 {
+	pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd
+		     &hdmim1_tx1_scl &hdmim1_tx1_sda>;
+	status = "okay";
+};
+
+&hdmi1_in {
+	hdmi1_in_vp1: endpoint {
+		remote-endpoint = <&vp1_out_hdmi1>;
+	};
+};
+
+&hdmi1_out {
+	hdmi1_out_con: endpoint {
+		remote-endpoint = <&hdmi1_con_in>;
+	};
+};
+
+&hdmi1_sound {
+	status = "okay";
+};
+
+&hdmi_receiver_cma {
+	status = "okay";
+};
+
+&hdmi_receiver {
+	hpd-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&hdptxphy0 {
+	status = "okay";
+};
+
+&hdptxphy1 {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc4v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc4v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	vdd_npu_s0: vdd_npu_mem_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_npu_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <950000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc4v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "hym8563";
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtc_int>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+		wakeup-source;
+	};
+};
+
+&i2c6 {
+	status = "okay";
+
+	usbc0: husb311@4e {
+		status = "okay";
+		compatible = "hynetek,husb311";
+		reg = <0x4e>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus5v0_typec>;
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			data-role = "dual";
+			label = "USB-C";
+			power-role = "source";
+			source-pdos =
+				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&usbdp_phy0_orientation_switch>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usbc0_role_sw: endpoint {
+						remote-endpoint = <&dwc3_0_role_switch>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					dp_altmode_mux: endpoint {
+						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+					};
+				};
+			};
+		};
+	};
+};
+
+&i2c7 {
+	status = "okay";
+
+	es8388: audio-codec@11 {
+		compatible = "everest,es8388";
+		reg = <0x11>;
+		clocks = <&cru I2S0_8CH_MCLKOUT>;
+		AVDD-supply = <&vcc_3v3_s3>;
+		DVDD-supply = <&vcc_3v3_s3>;
+		HPVDD-supply = <&vcc_3v3_s3>;
+		PVDD-supply = <&vcc_1v8_s3>;
+		assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+		assigned-clock-rates = <12288000>;
+		#sound-dai-cells = <0>;
+	};
+};
+
+&i2s0_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s0_lrck
+		     &i2s0_mclk
+		     &i2s0_sclk
+		     &i2s0_sdi0
+		     &i2s0_sdo0>;
+	status = "okay";
+};
+
+&i2s5_8ch {
+	status = "okay";
+};
+
+&i2s6_8ch {
+	status = "okay";
+};
+
+&i2s7_8ch {
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy: phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+	};
+};
+
+&package_thermal {
+	polling-delay = <1000>;
+
+	trips {
+		package_fan0: package-fan0 {
+			temperature = <55000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		package_fan1: package-fan1 {
+			temperature = <65000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			trip = <&package_fan0>;
+			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+		};
+
+		map1 {
+			trip = <&package_fan1>;
+			cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+/*
+ * pce2x1l0 or sata1 => combphy1_ps
+ * H88K v3.1: pcie2x1l0 is M.2 (A+E Key) socket for WiFi/Bluetooth
+ */
+&pcie2x1l0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_0_rst>;
+	reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+	vpcie3v3-supply = <&vcc3v3_sys>;
+};
+
+/*
+ * pcie2x1l1 or sata2 or usb30_2 => combphy2_psu
+ * combphy2_psu: pcie2x1l1 or sata2 or (usbhost3_0 + usbhost_dwc3_0)
+ * H88K V3.1: pcie2x1l1 used for rtl8125b
+ */
+&pcie2x1l1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pcie2_1_rst>;
+	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+	vpcie3v3-supply = <&vcc3v3_pcie20>;
+
+	pcie@0,0 {
+		reg = <0x00300000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		bus-range = <0x30 0x3f>;
+		device_type = "pci";
+		ranges;
+
+		rtl8125_1: pcie-eth@0,0 {
+			compatible = "pci10ec,8125";
+			label = "eth1";
+			reg = <0x310000 0 0 0 0>;
+
+			/*
+			 * G+ 3v3
+			 * G- LED3: ACT on all speed
+			 * Y+ 3v3
+			 * Y- LED2: LINK on 10 + 100 + 1000 + 2500
+			 */
+			r8125,led2 = <0x002b>;
+			r8125,led3 = <0x0200>;
+		};
+	};
+};
+
+/* rtl8125b eth0 */
+&pcie2x1l2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_2_rst>;
+	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+	vpcie3v3-supply = <&vcc3v3_pcie20>;
+
+	pcie@0,0 {
+		reg = <0x00400000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		bus-range = <0x40 0x4f>;
+		device_type = "pci";
+		ranges;
+
+		rtl8125_2: pcie-eth@0,0 {
+			compatible = "pci10ec,8125";
+			label = "eth0";
+			reg = <0x410000 0 0 0 0>;
+
+			/*
+			 * G+ 3v3
+			 * G- LED3: ACT on all speed
+			 * Y+ 3v3
+			 * Y- LED2: LINK on 10 + 100 + 1000 + 2500
+			 */
+			r8125,led2 = <0x002b>;
+			r8125,led3 = <0x0200>;
+		};
+	};
+};
+
+&pcie30phy {
+	data-lanes = <1 1 1 1>; 
+	status = "okay";
+};
+
+/*
+ * pcie3x4 => pcie30phy
+ * H88K v3.1: pcie3x4 is M.2 (M Key) socket for NVME ssd
+ */
+&pcie3x4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie3_rst>;
+	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+	vpcie3v3-supply = <&vcc3v3_pcie30>;
+};
+
+&pd_gpu {
+	domain-supply = <&vdd_gpu_s0>;
+};
+
+&pd_npu {
+	domain-supply = <&vdd_npu_s0>;
+};
+
+&pinctrl {
+	audio {
+		hp_detect: headphone-detect {
+			rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	bt {
+		bt_wake_host_h: bt-wake-host-h {
+			rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		host_wake_bt_h: host-wake-bt-h {
+			rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_reg_on_h: bt-reg-on-h {
+			rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+	};
+
+	hdmirx {
+		hdmirx_hpd: hdmirx-5v-detection {
+			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	ir {
+		ir_int_pin: ir-int-pin {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	lcd {
+		lcd_dc_pin: lcd-dc-pin {
+			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_drv_level_6>;
+		};
+
+		spi4_custom_pins: spi4-custom-pins {
+			rockchip,pins =
+				/* spi4_clk_m2 */
+				<1 RK_PA2 8 &pcfg_pull_up_drv_level_6>,
+				/* spi4_mosi_m2 */
+				<1 RK_PA1 8 &pcfg_pull_up_drv_level_6>,
+				/* spi4_miso_m0 */
+				<1 RK_PC0 8 &pcfg_pull_up_drv_level_6>;
+		};
+	};
+
+	leds {
+		led_red_ai_pin: led-red-ai-pin {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_green_work_pin: led-green-work-pin {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_blue_sata_pin: led-blue-sata-pin {
+			rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_amber_net_pin: led-amber-net-pin {
+			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	modem {
+		vcc3v8_modem_pwren: vcc3v8-modem-pwren {
+			rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		modem_reset_pin: modem-reset-pin {
+			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie2 {
+		pcie2_0_rst: pcie2-0-rst {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie2_1_rst: pcie2-1-rst {
+			rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie2_2_rst: pcie2-2-rst {
+			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie3 {
+		pcie3_rst: pcie3-rst {
+			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rtc {
+		rtc_int: rtc-int {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		usb_hub_rst_pin: usb-hub-rst-pin {
+			rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vbus5v0_typec_en: vbus5v0-typec-en {
+			rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb_host_en: vcc5v0_usb_host_en {
+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm9 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm9m0_pins>;
+	status = "okay";
+};
+
+&rknn_core_0 {
+	npu-supply = <&vdd_npu_s0>;
+	sram-supply = <&vdd_npu_mem_s0>;
+	status = "okay";
+};
+
+&rknn_core_1 {
+	npu-supply = <&vdd_npu_s0>;
+	sram-supply = <&vdd_npu_mem_s0>;
+	status = "okay";
+};
+
+&rknn_core_2 {
+	npu-supply = <&vdd_npu_s0>;
+	sram-supply = <&vdd_npu_mem_s0>;
+	status = "okay";
+};
+
+&rknn_mmu_0 {
+	status = "okay";
+};
+
+&rknn_mmu_1 {
+	status = "okay";
+};
+
+&rknn_mmu_2 {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&avcc_1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	status = "okay";
+};
+
+&sdmmc {
+	max-frequency = <200000000>;
+	no-sdio;
+	no-mmc;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_s3>;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+	num-cs = <1>;
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		spi-max-frequency = <1000000>;
+		reg = <0x0>;
+
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		pinctrl-1 = <&rk806_dvs1_pwrdn>;
+
+		/* 2800mv-3500mv */
+		low_voltage_threshold = <3000>;
+		/* 2700mv-3400mv */
+		shutdown_voltage_threshold = <2700>;
+		/* 140 160 */
+		shutdown_temperture_threshold = <160>;
+		hotdie_temperture_threshold = <115>;
+
+		/* 0: restart PMU;
+		 * 1: reset all the power off reset registers,
+		 *    forcing the state to switch to ACTIVE mode;
+		 * 2: Reset all the power off reset registers,
+		 *    forcing the state to switch to ACTIVE mode,
+		 *    and simultaneously pull down the RESETB PIN for 5mS before releasing
+		 */
+		pmic-reset-func = <2>;
+
+		system-power-controller;
+
+		vcc1-supply = <&vcc4v0_sys>;
+		vcc2-supply = <&vcc4v0_sys>;
+		vcc3-supply = <&vcc4v0_sys>;
+		vcc4-supply = <&vcc4v0_sys>;
+		vcc5-supply = <&vcc4v0_sys>;
+		vcc6-supply = <&vcc4v0_sys>;
+		vcc7-supply = <&vcc4v0_sys>;
+		vcc8-supply = <&vcc4v0_sys>;
+		vcc9-supply = <&vcc4v0_sys>;
+		vcc10-supply = <&vcc4v0_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc4v0_sys>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc4v0_sys>;
+
+		pinctrl_rk806: pinctrl_rk806 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			rk806_dvs1_null: rk806_dvs1_null {
+				pins = "gpio_pwrctrl1";
+				function = "pin_fun0";
+			};
+
+			rk806_dvs1_slp: rk806_dvs1_slp {
+				pins = "gpio_pwrctrl1";
+				function = "pin_fun1";
+			};
+
+			rk806_dvs1_pwrdn: rk806_dvs1_pwrdn {
+				pins = "gpio_pwrctrl1";
+				function = "pin_fun2";
+			};
+
+			rk806_dvs1_rst: rk806_dvs1_rst {
+				pins = "gpio_pwrctrl1";
+				function = "pin_fun3";
+			};
+
+			rk806_dvs2_null: rk806_dvs2_null {
+				pins = "gpio_pwrctrl2";
+				function = "pin_fun0";
+			};
+
+			rk806_dvs2_slp: rk806_dvs2_slp {
+				pins = "gpio_pwrctrl2";
+				function = "pin_fun1";
+			};
+
+			rk806_dvs2_pwrdn: rk806_dvs2_pwrdn {
+				pins = "gpio_pwrctrl2";
+				function = "pin_fun2";
+			};
+
+			rk806_dvs2_rst: rk806_dvs2_rst {
+				pins = "gpio_pwrctrl2";
+				function = "pin_fun3";
+			};
+
+			rk806_dvs2_dvs: rk806_dvs2_dvs {
+				pins = "gpio_pwrctrl2";
+				function = "pin_fun4";
+			};
+
+			rk806_dvs2_gpio: rk806_dvs2_gpio {
+				pins = "gpio_pwrctrl2";
+				function = "pin_fun5";
+			};
+
+			rk806_dvs3_null: rk806_dvs3_null {
+				pins = "gpio_pwrctrl3";
+				function = "pin_fun0";
+			};
+
+			rk806_dvs3_slp: rk806_dvs3_slp {
+				pins = "gpio_pwrctrl3";
+				function = "pin_fun1";
+			};
+
+			rk806_dvs3_pwrdn: rk806_dvs3_pwrdn {
+				pins = "gpio_pwrctrl3";
+				function = "pin_fun2";
+			};
+
+			rk806_dvs3_rst: rk806_dvs3_rst {
+				pins = "gpio_pwrctrl3";
+				function = "pin_fun3";
+			};
+
+			rk806_dvs3_dvs: rk806_dvs3_dvs {
+				pins = "gpio_pwrctrl3";
+				function = "pin_fun4";
+			};
+
+			rk806_dvs3_gpio: rk806_dvs3_gpio {
+				pins = "gpio_pwrctrl3";
+				function = "pin_fun5";
+			};
+		};
+
+		pwrkey {
+			status = "okay";
+		};
+
+		regulators {
+			vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_gpu_s0";
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_cpu_lit_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_log_s0: dcdc-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_log_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_vdenc_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vdd2_ddr_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_2v0_pldo_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_3v3_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vddq_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avcc_1v8_s0: pldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "avcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avdd_1v2_s0: pldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "avdd_1v2_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3_s0: pldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vcc_3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vccio_sd_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "pldo6_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_ddr_pll_s0: nldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdd_ddr_pll_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			avdd_0v75_s0: nldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "avdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v85_s0: nldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdd_0v85_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+/* LCD:   st7789v, 135(H) x 240(V), 8pin, 4Line SPI
+ * pin1:  LEDA:  LED Anode.
+ * pin2:  GND:   Power Ground.
+ * pin3:  RESET: This signal will reset th device, Signal is active low.
+ * pin4:  RS:    Display data/command selection pin in 4-line serial interface.  --> gpio1 RK_PA4
+ * pin5:  SDA:   SPI interface input/output pin.                                 --> gpio1 RK_PA1
+ * pin6:  SCL:   This pin is used to be serial interface clock                   --> gpio1 RK_PA2
+ * pin7:  VDD:   Power Supply for Analog
+ * pin8:  CS:    Chip selection pin. Low enable, High disable.                   --> gpio1 RK_PA3
+ */
+&spi4 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	assigned-clocks = <&cru CLK_SPI4>;
+	assigned-clock-rates = <200000000>;
+	num-cs = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi4_custom_pins &spi4m2_cs0>;
+	status = "okay";
+
+	panel@0 {
+		compatible = "sitronix,st7789v";
+		reg = <0>;
+		power-supply = <&vcc3v0_lcd>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd_dc_pin>;
+		dc-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+
+		/* 2Mhz */
+                spi-max-frequency = <2000000>;
+
+		//width = <135>;
+		//height = <240>;
+		//fps = <20>;
+		buswidth = <8>;
+		rotate = <90>;
+
+		/* debug: 0-7 */
+		debug = <0>;
+		//spi-cpol;
+		//spi-cpha;
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+&uart8 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn &uart8m1_rtsn>;
+	status = "disabled";
+
+	bluetooth: bluetooth {
+		compatible = "brcm,bcm4345c5";
+		clocks = <&hym8563>;
+		clock-names = "ext_clock";
+
+		//BT_WAKE_HOST
+		host-wakeup-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
+
+		//HOST_WAKE_BT
+		device-wakeup-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
+
+		//BT_REG_ON_H
+		shutdown-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+
+		max-speed = <1500000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_wake_host_h &host_wake_bt_h &bt_reg_on_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8_s3>; 
+	};
+};
+
+/* typec0 phy */
+&u2phy0 {
+	status = "okay";
+};
+
+/* typec0 phy */
+&u2phy0_otg {
+	status = "okay";
+};
+
+/* typec1 phy */
+&u2phy1 {
+	status = "okay";
+};
+
+/* typec1 phy */
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&u2phy2 {
+	status = "okay";
+};
+
+&u2phy2_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&u2phy3 {
+	status = "okay";
+};
+
+&u2phy3_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+/* phy is u2phy2_host */
+&usb_host0_ehci {
+	status = "okay";
+};
+
+/* phy is u2phy2_host */
+&usb_host0_ohci {
+	status = "okay";
+};
+
+/* typec0:
+ *   host: usb_host0_xhci
+ *   usb2.0 phy: usb2phy0_grf/u2phy0/u2phy0_otg
+ *   usb3.0 phy: usbdp_phy0
+ */
+&usb_host0_xhci {
+	dr_mode = "otg";
+	usb-role-switch;
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dwc3_0_role_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
+};
+
+/* phy is u2phy3_host */
+&usb_host1_ehci {
+	status = "okay";
+};
+
+/* phy is u2phy3_host */
+&usb_host1_ohci {
+	status = "okay";
+};
+
+/*
+ * typec1:
+ * host: usb_host1_xhci
+ * usb2.0 phy: usb2phy1_grf/u2phy1/u2phy1_otg
+ * usb3.0 phy: usbdp_phy1
+ * connect to GL3523 HUB
+ */ 
+&usb_host1_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+/* typec0 phy */
+&usbdp_phy0 {
+	mode-switch;
+	orientation-switch;
+	sbu1-dc-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+	sbu2-dc-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		usbdp_phy0_orientation_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+
+		usbdp_phy0_dp_altmode_mux: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&dp_altmode_mux>;
+		};
+	};
+};
+
+/* typec1 phy */
+&usbdp_phy1 {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};
+
+&vp1 {
+	vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI1>;
+		remote-endpoint = <&hdmi1_in_vp1>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-hlink-h88k.dts b/arch/arm64/boot/dts/rockchip/rk3588-hlink-h88k.dts
new file mode 100644
index 000000000..69e08b364
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-hlink-h88k.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2024 Flippy <flippy@sina.com>
+
+/dts-v1/;
+
+#include "rk3588-hlink.dtsi"
+
+/ {
+	model = "Hlink H88K";
+	compatible = "hlink,h88k", "rockchip,rk3588";
+
+	vcc3v3_m2_sata: vcc3v3-m2-sata {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_m2_sata";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc3v3_m2_sata_en>;
+		gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+};
+
+
+&combphy0_ps {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&sata0_pm_reset>;
+};
+
+&pinctrl {
+	sata {
+		sata0_pm_reset: sata0-pm-reset {
+			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+
+		vcc3v3_m2_sata_en: vcc3v3-m2-sata-en {
+			rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+/* phy is combphy0_ps */
+&sata0 {
+	status = "okay";
+	target-supply = <&vcc3v3_m2_sata>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-hlink.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-hlink.dtsi
new file mode 100644
index 000000000..ab4f5cf42
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-hlink.dtsi
@@ -0,0 +1,1191 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "rk3588.dtsi"
+
+/ {
+	compatible = "rockchip,rk3588";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	analog_sound: analog-sound {
+		compatible = "audio-graph-card";
+		label = "rk3588-es8388";
+
+		widgets = "Microphone", "Mic Jack",
+			  "Headphone", "Headphones";
+
+		routing = "MIC2", "Mic Jack",
+			  "Headphones", "HPOL",
+			  "Headphones", "HPOR";
+
+		dais = <&i2s0_8ch_p0>;
+		hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_detect>;
+	};
+
+	gpio_leds: gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_net_en>, <&led_sata_en>,
+			    <&led_user_en>, <&led_work_en>;
+
+		net {
+			label = "blue:net";
+			gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>;
+		};
+
+		sata {
+			label = "amber:sata";
+			gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+		};
+
+		user {
+			label = "green:user";
+			gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+		};
+
+		work {
+			label = "red:work";
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "default-on";
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		cooling-levels = <0 95 145 195 255>;
+		fan-supply = <&vcc5v0_sys>;
+		pwms = <&pwm14 0 50000 0>;
+		#cooling-cells = <2>;
+	};
+
+	reserved_momory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* Reserve 256MB memory for hdmirx-controller@fdee0000
+		 * remove the node if hdmirx is disabled 
+		 */
+		cma_hdmirx: cma-hdmirx {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 (256 * 0x100000)>;
+			status = "disabled";
+		};
+	};
+
+	rfkill: rfkill {
+		compatible = "rfkill-gpio";
+
+		rfkill_modem: rfkill-modem {
+			label = "rfkill-modem";
+			radio-type = "wwan";
+			reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&modem_reset_en>;
+		};
+			
+	};
+
+	vcc12v_dcin: vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		startup-delay-us = <100000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	pcie20_avdd0v85: pcie20-avdd0v85 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie20_avdd0v85";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <850000>;
+		vin-supply = <&vdd_0v85_s0>;
+	};
+
+	pcie20_avdd1v8: pcie20-avdd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie20_avdd1v8";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&avcc_1v8_s0>;
+	};
+
+	pcie30_avdd0v75: pcie30-avdd0v75 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd0v75";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <750000>;
+		regulator-max-microvolt = <750000>;
+		vin-supply = <&avdd_0v75_s0>;
+	};
+
+	pcie30_avdd1v8: pcie30-avdd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd1v8";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&avcc_1v8_s0>;
+	};
+
+	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_pcie30: vcc3v3-pcie30 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie30";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie3_vcc3v3_en>;
+		startup-delay-us = <100000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_usb_host: vcc5v0-usb-host {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	/* usb hub reset pin */
+	vcc5v0_usb_hub: vcc5v0-usb-hub {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb_hub";
+		regulator-always-on;
+		enable-active-high;
+		gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_hub_en>;
+		startup-delay-us = <100000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vbus5v0_typec: vbus5v0-typec {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus5v0_typec";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		enable-active-high;
+		gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&typec5v_pwren>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_mipidcphy0: vcc-mipidcphy0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_mipidcphy0";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipidcphy0_pwr>;
+	};
+
+	vcc_mipidcphy1: vcc-mipidcphy1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_mipidcphy1";
+		enable-active-high;
+		gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipidcphy1_pwr>;
+	};
+
+	vcc_mipidphy0: vcc-mipidphy0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_mipidphy0";
+		enable-active-high;
+		gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipidphy0_pwr>;
+	};
+
+	vcc_mipidphy1: vcc-mipidphy1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_mipidphy1";
+		enable-active-high;
+		gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipidphy1_pwr>;
+	};
+
+	vcc3v3_modem: vcc3v3-modem {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+		gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_modem";
+		pinctrl-names = "default";
+		pintctrl-0 = <&modem_power_en>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+};
+
+&combphy1_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gmac0 {
+	status = "okay";
+	label = "eth0";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+
+	phy-handle = <&rgmii_phy>;
+
+	clock_in_out = "output";
+	phy-mode = "rgmii-rxid";
+	tx_delay = <0x44>;
+
+	snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	vdd_npu_s0: vdd_npu_mem_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_npu_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <950000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "hym8563";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+		wakeup-source;
+	};
+};
+
+&i2c7 {
+	status = "okay";
+
+	es8388: audio-codec@11 {
+		compatible = "everest,es8388", "everest,es8323";
+		reg = <0x11>;
+		clocks = <&cru I2S0_8CH_MCLKOUT>;
+		clock-names = "mclk";
+		assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+		assigned-clock-rates = <12288000>;
+		#sound-dai-cells = <0>;
+
+		port {
+			es8388_p0_0: endpoint {
+				remote-endpoint = <&i2s0_8ch_p0_0>;
+			};
+		};
+	};
+};
+
+&i2s0_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s0_lrck
+		     &i2s0_mclk
+		     &i2s0_sclk
+		     &i2s0_sdi0
+		     &i2s0_sdo0>;
+	status = "okay";
+
+	i2s0_8ch_p0: port {
+		i2s0_8ch_p0_0: endpoint {
+			dai-format = "i2s";
+			mclk-fs = <256>;
+			remote-endpoint = <&es8388_p0_0>;
+		};
+	};
+};
+
+&mdio0 {
+	rgmii_phy: phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+	};
+};
+
+/*
+ * M.2 slot
+ * phy is combphy1_ps
+ */
+&pcie2x1l0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_0_rst>;
+	reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+/*
+ * RTL8125B 2.5g ethernet
+ * phy is combphy2_psu
+ */
+&pcie2x1l1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_1_rst>;
+	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x00300000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		bus-range = <0x30 0x3f>;
+		device_type = "pci";
+		ranges;
+
+		rtl8125_1: pcie-eth@0,0 {
+			compatible = "pci10ec,8125";
+			label = "eth1";
+			reg = <0x310000 0 0 0 0>;
+
+			/* G+ 3v3
+			 * G- LED3: LINK on 100 + 1000 + 2500
+			 * Y+ 3v3
+			 * Y- LED2: ACT on all speed
+			 */
+			r8125,led2 = <0x0200>;
+			r8125,led3 = <0x002a>;
+		};
+	};
+};
+
+&pcie30phy {
+	status = "okay";
+};
+
+/* 
+ * H88K V1/V2: pcie x4 slot
+ * H88K V3: m.2 nvme
+ */  
+&pcie3x4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie3_rst>;
+	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie30>;
+	status = "okay";
+};
+
+&pd_gpu {
+	domain-supply = <&vdd_gpu_s0>;
+};
+
+&pd_npu {
+	domain-supply = <&vdd_npu_s0>;
+};
+
+&pinctrl {
+	hdmirx {
+		hdmirx_det: hdmirx-det {
+			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	ir {
+		ir_int_pin: ir-int-pin {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	leds {
+		led_net_en: led_net_en {
+			rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_sata_en: led_sata_en {
+			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_user_en: led_user_en {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_work_en: led_work_en {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	mipi {
+		mipidcphy0_pwr: mipidcphy0-pwreset-en {
+			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		mipidcphy1_pwr: mipidcphy1-pwreset-en {
+			rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		mipidphy0_pwr: mipidphy0-pwreset-en {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		mipidphy1_pwr: mipidphy1-pwreset-en {
+			rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	modem {
+		modem_power_en: modem-power-en {
+			rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		modem_reset_en: modem-reset-en {
+			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie2 {
+		pcie2_0_rst: pcie2-0-rst {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie2_1_rst: pcie2-1-rst {
+			rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie3 {
+		pcie3_rst: pcie3-rst {
+			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie3_vcc3v3_en: pcie3-vcc3v3-en {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};	
+
+	sound {
+		hp_detect: hp-detect {
+			rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_host_en: vcc5v0_usb_host_en {
+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
+			rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		typec5v_pwren: typec5v-pwren {
+			rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb-typec {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pwm14 {
+	status = "okay";
+};
+
+&rknn_core_0 {
+	npu-supply = <&vdd_npu_s0>;
+	sram-supply = <&vdd_npu_mem_s0>;
+	status = "okay";
+};
+
+&rknn_core_1 {
+	npu-supply = <&vdd_npu_s0>;
+	sram-supply = <&vdd_npu_mem_s0>;
+	status = "okay";
+};
+
+&rknn_core_2 {
+	npu-supply = <&vdd_npu_s0>;
+	sram-supply = <&vdd_npu_mem_s0>;
+	status = "okay";
+};
+
+&rknn_mmu_0 {
+	status = "okay";
+};
+
+&rknn_mmu_1 {
+	status = "okay";
+};
+
+&rknn_mmu_2 {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&avcc_1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	status = "okay";
+};
+
+&sdmmc {
+	max-frequency = <50000000>;
+	no-sdio;
+	no-mmc;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	vmmc-supply = <&vcc_3v3_s3>;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+	num-cs = <1>;
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		spi-max-frequency = <1000000>;
+		reg = <0x0>;
+
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		pinctrl-1 = <&rk806_dvs1_pwrdn>;
+
+		/* 2800mv-3500mv */
+		low_voltage_threshold = <3000>;
+		/* 2700mv-3400mv */
+		shutdown_voltage_threshold = <2700>;
+		/* 140 160 */
+		shutdown_temperture_threshold = <160>;
+		hotdie_temperture_threshold = <115>;
+
+		/* 0: restart PMU;
+		 * 1: reset all the power off reset registers,
+		 *    forcing the state to switch to ACTIVE mode;
+		 * 2: Reset all the power off reset registers,
+		 *    forcing the state to switch to ACTIVE mode,
+		 *    and simultaneously pull down the RESETB PIN for 5mS before releasing
+		 */
+		pmic-reset-func = <2>;
+
+		system-power-controller;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc5v0_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc5v0_sys>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc5v0_sys>;
+
+		pinctrl_rk806: pinctrl_rk806 {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			rk806_dvs1_null: rk806_dvs1_null {
+				pins = "gpio_pwrctrl1";
+				function = "pin_fun0";
+			};
+
+			rk806_dvs1_slp: rk806_dvs1_slp {
+				pins = "gpio_pwrctrl1";
+				function = "pin_fun1";
+			};
+
+			rk806_dvs1_pwrdn: rk806_dvs1_pwrdn {
+				pins = "gpio_pwrctrl1";
+				function = "pin_fun2";
+			};
+
+			rk806_dvs1_rst: rk806_dvs1_rst {
+				pins = "gpio_pwrctrl1";
+				function = "pin_fun3";
+			};
+
+			rk806_dvs2_null: rk806_dvs2_null {
+				pins = "gpio_pwrctrl2";
+				function = "pin_fun0";
+			};
+
+			rk806_dvs2_slp: rk806_dvs2_slp {
+				pins = "gpio_pwrctrl2";
+				function = "pin_fun1";
+			};
+
+			rk806_dvs2_pwrdn: rk806_dvs2_pwrdn {
+				pins = "gpio_pwrctrl2";
+				function = "pin_fun2";
+			};
+
+			rk806_dvs2_rst: rk806_dvs2_rst {
+				pins = "gpio_pwrctrl2";
+				function = "pin_fun3";
+			};
+
+			rk806_dvs2_dvs: rk806_dvs2_dvs {
+				pins = "gpio_pwrctrl2";
+				function = "pin_fun4";
+			};
+
+			rk806_dvs2_gpio: rk806_dvs2_gpio {
+				pins = "gpio_pwrctrl2";
+				function = "pin_fun5";
+			};
+
+			rk806_dvs3_null: rk806_dvs3_null {
+				pins = "gpio_pwrctrl3";
+				function = "pin_fun0";
+			};
+
+			rk806_dvs3_slp: rk806_dvs3_slp {
+				pins = "gpio_pwrctrl3";
+				function = "pin_fun1";
+			};
+
+			rk806_dvs3_pwrdn: rk806_dvs3_pwrdn {
+				pins = "gpio_pwrctrl3";
+				function = "pin_fun2";
+			};
+
+			rk806_dvs3_rst: rk806_dvs3_rst {
+				pins = "gpio_pwrctrl3";
+				function = "pin_fun3";
+			};
+
+			rk806_dvs3_dvs: rk806_dvs3_dvs {
+				pins = "gpio_pwrctrl3";
+				function = "pin_fun4";
+			};
+
+			rk806_dvs3_gpio: rk806_dvs3_gpio {
+				pins = "gpio_pwrctrl3";
+				function = "pin_fun5";
+			};
+		};
+
+		pwrkey {
+			status = "okay";
+		};
+
+		regulators {
+			vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_gpu_s0";
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_cpu_lit_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_log_s0: dcdc-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_log_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_vdenc_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vdd2_ddr_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_2v0_pldo_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_3v3_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vddq_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avcc_1v8_s0: pldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "avcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avdd_1v2_s0: pldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "avdd_1v2_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3_s0: pldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vcc_3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vccio_sd_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "pldo6_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_ddr_pll_s0: nldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdd_ddr_pll_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			avdd_0v75_s0: nldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "avdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v85_s0: nldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdd_0v85_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&u2phy2 {
+	status = "okay";
+};
+
+&u2phy2_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&u2phy3 {
+	status = "okay";
+};
+
+&u2phy3_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usbdp_phy1 {
+	status = "okay";
+};
+
+/* phy is u2phy2_host */
+&usb_host0_ehci {
+	status = "okay";
+};
+
+/* phy is u2phy2_host */
+&usb_host0_ohci {
+	status = "okay";
+};
+
+/* phy is u2phy3_host */
+&usb_host1_ehci {
+	status = "okay";
+};
+
+/* phy is u2phy3_host */
+&usb_host1_ohci {
+	status = "okay";
+};
+
+/*
+ * phy are:
+ *   u2phy1_otg (USB2)
+ *   usbdp_phy1 (USB3)
+ */ 
+&usb_host1_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+/* 
+ * phy is combphy2_psu
+ * but combphy2_psu is used by pcie2x1l1
+ */
+&usb_host2_xhci {
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-e52c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-e52c.dts
new file mode 100644
index 000000000..1b1a32645
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-e52c.dts
@@ -0,0 +1,872 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3588s.dtsi"
+
+/ {
+	model = "Radxa E52C";
+	compatible = "radxa,e52c", "rockchip,rk3582", "rockchip,rk3588s";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdhci;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	keys-0 {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <18000>;
+		poll-interval = <100>;
+
+		button-0 {
+			label = "Maskrom";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <0>;
+		};
+	};
+
+	keys-1 {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&btn_reset>;
+
+		button-1 {
+			label = "Reset Button";
+			gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <100>;
+		};
+	};
+
+	hdmi0-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi0_con_in: endpoint {
+				remote-endpoint = <&hdmi0_out_con>;
+			};
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "led-green-sys", "led-green-wan", "led-green-lan";
+		pinctrl-0 = <&led_green_sys_pin>, <&led_green_wan_pin>, <&led_green_lan_pin>;
+
+		led_green_sys: led-green-sys {
+			gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+			label = "green:sys";
+			linux,default-trigger = "heartbeat";
+		};
+
+		led_green_wan: led-green-wan {
+			gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>;
+			label = "green:wan";
+		};
+
+		led_green_lan: led-green-lan {
+			gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
+			label = "green:lan";
+		};
+	};
+
+	vcc_1v1_nldo_s3: regulator-1v1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	vcc_3v3_s0: regulator-3v3-1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcca: regulator-4v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcca";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <4000000>;
+		regulator-max-microvolt = <4000000>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	vcc5v0_usb_otg0: regulator-5v0-0 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_otg_pwren_h>;
+		regulator-name = "vcc5v0_usb_otg0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	vcc_5v0: regulator-5v0-1 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_5v0_pwren_h>;
+		regulator-name = "vcc_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	vcc_sysin: regulator-5v0-2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sysin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+/*
+ * In the Rockchip RK3582 SoC, some CPU cores end up disabled
+ * and unused because they're marked in the efuses as defective.
+ * The disabling in the DT is performed by the boot loader.
+ */
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	status = "okay";
+};
+
+&hdmi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmim0_tx0_cec
+		     &hdmim1_tx0_hpd
+		     &hdmim0_tx0_scl
+		     &hdmim0_tx0_sda>;
+	status = "disabled";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&hdmi0_out {
+	hdmi0_out_con: endpoint {
+		remote-endpoint = <&hdmi0_con_in>;
+	};
+};
+
+&hdptxphy0 {
+	status = "disabled";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_sysin>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_sysin>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	eeprom@50 {
+		compatible = "belling,bl24c16a", "atmel,24c16";
+		reg = <0x50>;
+		pagesize = <16>;
+		vcc-supply = <&vcc_3v3_pmu>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	vdd_npu_s0: vdd_npu_mem_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_npu_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <950000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_sysin>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c5m2_xfer>;
+	status = "okay";
+
+	rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "rtcic_32kout";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtc_int_l>;
+		wakeup-source;
+	};
+};
+
+&pd_gpu {
+	domain-supply = <&vdd_gpu_s0>;
+};
+
+&pd_npu {
+	domain-supply = <&vdd_npu_s0>;
+};
+
+/* rtl8125b eth0 */
+&pcie2x1l1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie20x1_1_perstn_m1>;
+	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_s3>;
+	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x00300000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		bus-range = <0x30 0x3f>;
+		device_type = "pci";
+		ranges;
+
+		rtl8125_1: pcie-eth@0,0 {
+			compatible = "pci10ec,8125";
+			label = "eth0";
+			reg = <0x310000 0 0 0 0>;
+
+			/* G+: LED0
+			 * G-: LED1
+			 * Y+: 3v3
+			 * Y-: LED2
+			 */
+			// LED0: active high, link on all speed
+			r8125,led0 = <0x102b>;
+
+			// LED1: active low, act on all speed
+			r8125,led1 = <0x0200>;
+
+			// LED2: active low, link on 100 + 1000 + 2500
+			r8125,led2 = <0x002a>;
+		};
+	};
+};
+
+/* rtl8125b eth1 */
+&pcie2x1l2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie20x1_2_perstn_m0>;
+	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_s3>;
+	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x00400000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		bus-range = <0x40 0x4f>;
+		device_type = "pci";
+		ranges;
+
+		rtl8125_2: pcie-eth@0,0 {
+			compatible = "pci10ec,8125";
+			label = "eth1";
+			reg = <0x410000 0 0 0 0>;
+
+			/* G+: LED0
+			 * G-: LED1
+			 * Y+: 3v3
+			 * Y-: LED2
+			 */
+			// LED0: active high, link on all speed
+			r8125,led0 = <0x102b>;
+
+			// LED1: active low, act on all speed
+			r8125,led1 = <0x0200>;
+
+			// LED2: active low, link on 100 + 1000 + 2500
+			r8125,led2 = <0x002a>;
+		};
+	};
+};
+
+&pinctrl {
+	keys {
+		btn_reset: btn-reset {
+			rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	leds {
+		led_green_sys_pin: led-green-sys-pin {
+			rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_green_wan_pin: led-green-wan-pin {
+			rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		led_green_lan_pin: led-green-lan-pin {
+			rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie20x1_1_perstn_m1: pcie-1 {
+			rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		pcie20x1_2_perstn_m0: pcie-2 {
+			rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	regulators {
+		vcc_5v0_pwren_h: regulator-5v0-1 {
+			rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rtc {
+		rtc_int_l: rtc-0 {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		usb_otg_pwren_h: regulator-5v0-0 {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&rknn_core_0 {
+	npu-supply = <&vdd_npu_s0>;
+	sram-supply = <&vdd_npu_mem_s0>;
+	status = "okay";
+};
+
+&rknn_core_1 {
+	npu-supply = <&vdd_npu_s0>;
+	sram-supply = <&vdd_npu_mem_s0>;
+	status = "okay";
+};
+
+&rknn_core_2 {
+	npu-supply = <&vdd_npu_s0>;
+	sram-supply = <&vdd_npu_mem_s0>;
+	status = "okay";
+};
+
+&rknn_mmu_0 {
+	status = "okay";
+};
+
+&rknn_mmu_1 {
+	status = "okay";
+};
+
+&rknn_mmu_2 {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	no-sd;
+	no-sdio;
+	non-removable;
+	vmmc-supply = <&vcc_3v3_s0>;
+	vqmmc-supply = <&vcc_1v8_s3>;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	no-sdio;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_s3>;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	num-cs = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		reg = <0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		spi-max-frequency = <1000000>;
+		system-power-controller;
+
+		vcc1-supply = <&vcc_sysin>;
+		vcc2-supply = <&vcc_sysin>;
+		vcc3-supply = <&vcc_sysin>;
+		vcc4-supply = <&vcc_sysin>;
+		vcc5-supply = <&vcc_sysin>;
+		vcc6-supply = <&vcc_sysin>;
+		vcc7-supply = <&vcc_sysin>;
+		vcc8-supply = <&vcc_sysin>;
+		vcc9-supply = <&vcc_sysin>;
+		vcc10-supply = <&vcc_sysin>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc_sysin>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcca>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: dcdc-reg1 {
+				regulator-name = "vdd_gpu_s0";
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: dcdc-reg2 {
+				regulator-name = "vdd_cpu_lit_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_logic_s0: dcdc-reg3 {
+				regulator-name = "vdd_logic_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: dcdc-reg4 {
+				regulator-name = "vdd_vdenc_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-name = "vdd_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-name = "vdd2_ddr_s3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-name = "vcc_2v0_pldo_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: vcc_3v3_pmu: dcdc-reg8 {
+				regulator-name = "vcc_3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-name = "vddq_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-name = "vcc_1v8_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg1 {
+				regulator-name = "vcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca_1v8_s0: pldo-reg2 {
+				regulator-name = "vcca_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdda_1v2_s0: pldo-reg3 {
+				regulator-name = "vdda_1v2_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca_3v3_s0: pldo-reg4 {
+				regulator-name = "vcca_3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-name = "vccio_sd_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-name = "pldo6_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-name = "vdd_0v75_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdda_ddr_pll_s0: nldo-reg2 {
+				regulator-name = "vdda_ddr_pll_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdda_0v75_s0: nldo-reg3 {
+				regulator-name = "vdda_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdda_0v85_s0: nldo-reg4 {
+				regulator-name = "vdda_0v85_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-name = "vdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg0>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbdp_phy0 {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-e54c-dsa.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-e54c-dsa.dts
new file mode 100644
index 000000000..615bd8c1f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-e54c-dsa.dts
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "rk3588s-radxa-e54c.dts"
+
+/ {
+	/delete-node/ switch0;
+};
+
+&gmac1 {
+	/delete-property/ snps,tso;
+	label = "eth0";
+	tx_delay = <0x0>;
+	rx_delay = <0x0>;
+};
+
+&mdio1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	switch0: switch0@29 {
+		compatible = "realtek,rtl8365mb";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <29>;
+
+		mdio_phys: mdio {
+			compatible = "realtek,smi-mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mdio_phy0: mdio-phy@0 {
+				reg = <0>;
+			};
+
+			mdio_phy1: mdio-phy@1 {
+				reg = <1>;
+			};
+
+			mdio_phy2: mdio-phy@2 {
+				reg = <2>;
+			};
+
+			mdio_phy3: mdio-phy@3 {
+				reg = <3>;
+			};
+		};
+
+		mdio_ports: ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port0: port@0 {
+				reg = <0>;
+				label = "eth0p0";
+				phy-handle = <&mdio_phy0>;
+			};
+
+			port1: port@1 {
+				reg = <1>;
+				label = "eth0p1";
+				phy-handle = <&mdio_phy1>;
+			};
+
+			port2: port@2 {
+				reg = <2>;
+				label = "eth0p2";
+				phy-handle = <&mdio_phy2>;
+			};
+
+			port3: port@3 {
+				reg = <3>;
+				label = "eth0p3";
+				phy-handle = <&mdio_phy3>;
+			};
+
+			port6: port@6 {
+				reg = <6>;
+				label = "cpu";
+				ethernet = <&gmac1>;
+				phy-mode = "rgmii";
+				tx-internal-delay-ps = <2000>;
+				rx-internal-delay-ps = <2100>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-e54c-v1.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-e54c-v1.dts
new file mode 100644
index 000000000..577aec6d4
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-e54c-v1.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
+ * Copyright (c) 2025 flippy (flippy@sina.com)
+ */
+
+/dts-v1/;
+
+#include "rk3588s-radxa-e54c.dts"
+
+/ {
+	/* Ver 1.0 20240715 */
+	model = "Radxa E54C V1.0";
+};
+
+&i2c4 {
+	status = "disabled";
+	/delete-node/ usb-typec@22;
+	/delete-node/ rtc@51;
+};
+
+&i2c5 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c5m2_xfer>;
+	status = "okay";
+
+	fusb302: usb-typec@22 {
+		status = "okay";
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA7 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fusb302_int_l>;
+		vbus-supply = <&vbus_typec0>;
+
+		typec0_connect: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			power-role = "dual";
+			try-power-role = "sink";
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 5000, PDO_FIXED_USB_COMM)
+				     PDO_VAR(5000, 20000, 5000)
+				     PDO_PPS_APDO(5000, 20000, 5000)>;
+			op-sink-microwatt = <100000000>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&usbdp_phy0_orientation_switch>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usbc0_role_sw: endpoint {
+						remote-endpoint = <&dwc3_0_role_switch>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					dp_altmode_mux: endpoint {
+						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+					};
+				};
+			};
+		};
+	};
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "rtcic_32kout";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int_l>;
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-e54c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-e54c.dts
new file mode 100644
index 000000000..0859cd019
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-e54c.dts
@@ -0,0 +1,1259 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
+ * Copyright (c) 2025 flippy (flippy@sina.com)
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588s.dtsi"
+
+/ {
+	/* Ver 1.2 20250328 */
+	model = "Radxa E54C";
+	compatible = "radxa,e54c", "rockchip,rk3582", "rockchip,rk3588s", "rockchip,rk3588";
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdhci;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	hdmi0-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi0_con_in: endpoint {
+				remote-endpoint = <&hdmi0_out_con>;
+			};
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&user_key>;
+		autorepeat;
+
+		user-key {
+			label = "Reset button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+			debounce-interval = <60>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		sys_led:  sys-led {
+			gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+			label = "green:sys";
+			linux,default-trigger = "heartbeat";
+		};
+
+		wan_led: wan-led {
+			gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>;
+			label = "green:wan";
+			linux,default-trigger = "netdev";
+		};
+
+		lan1_led: lan1-led {
+			gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
+			label = "green:lan1";
+			linux,default-trigger = "netdev";
+		};
+
+		lan2_led: lan2-led {
+			gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
+			label = "green:lan2";
+			linux,default-trigger = "netdev";
+		};
+
+		lan3_led: lan3-led {
+			gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
+			label = "green:lan3";
+			linux,default-trigger = "netdev";
+		};
+	};
+
+	/* The main power */
+	dc12v_in: regulator-dc12v-in {
+		compatible = "regulator-fixed";
+		regulator-name = "dc12v-in";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	/* The alternative power
+	 * output mode: FPF2595UCX advanced load−management switch, Max 28v 3.9A, vcc_sysin -> vbus_typec0 5v
+	 *   enabled by GPIO3_C0
+	 * input mode: FUSB302B Programmable USB Type‐C Controller, vbus_typec0 -> vcc_sysin, 5v - 20v
+	 */
+	vbus_typec0: regulator-vbus-typec0 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vbus_typec0_en>;
+		regulator-name = "vbus-typec0";
+	};
+
+	/*
+	 * Supply by dc12v_in through a diode (SS54),
+	 * or by vbus_typec0 through a power electronics switch (WS4684C)
+	 * if dc12v_in and vbus_typec0 are powered at the same time, select dc12v_in
+	 */
+	typec_vin: regulator-typec-vin {
+		compatible = "regulator-fixed";
+		regulator-name = "typec-in";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		vin-supply = <&dc12v_in>;
+	};
+
+	/*
+	 * DC-DC:   MP8759 Max 26V 8A
+	 * input:   typec_vin
+	 * output1: vcc_sysin: direct
+	 * output2: vcc5v0_dip: through a 4A fuse, is used for DIP_14PIN-2_54MM output
+	 */
+	 vcc_sysin: vcc5v0_dip: regulator-vcc5v0-sysin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sysin";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&typec_vin>;
+	};
+
+	/*
+	 * LDO: SGM2200-ADJ Max 26.4v input, 1.5v - 5v 50ma output
+	 * Used for RK806-1 VCCA supply and hym8563 supply
+	 */
+	vcca_4v0: regulator-vcca-4v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcca_4v0";
+		regulator-min-microvolt = <4000000>;
+		regulator-max-microvolt = <4000000>;
+		regulator-boot-on;
+		regulator-always-on;
+		vin-supply = <&typec_vin>;
+	};
+
+	/*
+	 * PMOS switch: AO3401, Max 4A output
+	 * input:  vcc_sysin
+	 * output: vcc_5v0
+	 * enabled by vcc_3v3_s3
+	 */
+	vcc_5v0: regulator-vcc-5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		regulator-always-on;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	/*
+	 * DC-DC: ETA3409/SY8089AAC, Max 2A output
+	 * input: vcc_sysin
+	 * output: vcc_1v1_nldo_s3
+	 * enabled by pmic RK806-1 ext_en pin
+	 */
+	vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	/*
+	 * DC-DC: SY8089AAC, max 2A output
+	 * input: vcc_sysin
+	 * output: vcc_3v3_pcie
+	 * enabled by vcc_2v0_pldo_s3
+	 */
+	vcc_3v3_pcie: regulator-vcc-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_pcie";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	/*
+	 * Through a 0 ohm resistor
+	 * input: vcc_3v3_s3
+	 * output: vcc_3v3_pmu
+	 */
+	vcc_3v3_pmu: regulator-vcc-3v3-pmu {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_pmu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	/*
+	 * Power switch: SGM2576, max 2.5A output
+	 * input: vcc_3v3_s3
+	 * output: vcc_3v3_s0
+	 * enabled by vcc_1v8_s0
+	 */
+	vcc_3v3_s0: regulator-vcc-3v3-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	/*
+	 * Through a 0 ohm resistor
+	 * input: vcc_1v8_s3
+	 * output: vcc_1v8_pmu
+	 */
+	vcc_1v8_pmu: regulator-vcc-1v8-pmu {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8_pmu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8_s3>;
+	};
+
+	/*
+	 * Power switch: SY6280AAC, max 2A output
+	 * input: vcc_sysin
+	 * output to two usb2.0 type A port
+	 * enabled by GPIO4_B5
+	 */
+	vcc5v0_usb_hub: regulator-vcc5v0-usb-hub {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb_hub";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_hub_en>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	/*
+	 * Power switch: SY6280AAC, max 2A output
+	 * input: vcc_sysin
+	 * output to USB3 type A port
+	 * enabled by GPIO0_D4
+	 */
+	vcc5v0_usb3_host: regulator-vcc5v0-usb3-host {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb3_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb3_host_en>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	/*
+	 * DC-DC: SY8088AAC(3v3) + SY8088AAC(1v1), max 1A
+	 * input: vcc_5v0
+	 * output: 3v3 to RTL8367RB AVDDH, 1v1 to RTL8367RB AVDDL
+	 * enabled by GPIO3_A6
+	 */
+	vcc3v3_switch: regulator-vcc3v3-switch {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_switch";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtl8367rb_power_en>;
+		vin-supply = <&vcc_5v0>;
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		cooling-levels = <0 64 128 192 255>;
+		pwms = <&pwm3 0 10000 0>;
+	};
+
+	/* RTL8367RB-VB (num:6367 ver:0020) */
+	switch0: switch0 {
+		compatible = "realtek,rtl8367b";
+		realtek,extif = <6 1 0 1 1 1 1 1 1 2>;
+		mii-bus = <&mdio1>;
+		phy-id = <29>;
+	};
+};
+
+/* pcie2x1l2 phy */
+&combphy0_ps {
+	status = "okay";
+};
+
+/* usb_host2_xhci: usb@fcd00000 phy */
+&combphy2_psu {
+	status = "okay";
+};
+
+/*
+ * In the Rockchip RK3582 SoC, some CPU cores end up disabled
+ * and unused because they're marked in the efuses as defective.
+ * The disabling in the DT is performed by the boot loader.
+ */
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+/*
+ * The stmmac driver used by rk3588 has a bug in VLAN.
+ * Instead of hacking it, use the legacy switch driver
+ * first. Obviously this is not a DSA driver bug.
+ */
+&gmac1 {
+	status = "okay";
+	label = "eth0";
+	phy-mode = "rgmii-rxid";
+	phy-supply = <&vcc3v3_switch>;
+	clock_in_out = "output";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1_miim
+		     &gmac1_tx_bus2
+		     &gmac1_rx_bus2
+		     &gmac1_rgmii_clk
+		     &gmac1_rgmii_bus>;
+
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 10000>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+
+	tx_delay = <0x3f>;
+	rx_delay = <0x10>;
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+		pause;
+	};
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	status = "okay";
+};
+
+&hdmi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmim0_tx0_cec
+		     &hdmim1_tx0_hpd
+		     &hdmim0_tx0_scl
+		     &hdmim0_tx0_sda>;
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&hdmi0_out {
+	hdmi0_out_con: endpoint {
+		remote-endpoint = <&hdmi0_con_in>;
+	};
+};
+
+&hdptxphy0 {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_sysin>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_sysin>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	eeprom@50 {
+		compatible = "belling,bl24c16a", "atmel,24c16";
+		reg = <0x50>;
+		pagesize = <16>;
+		vcc-supply = <&vcc_3v3_pmu>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	vdd_npu_s0: vdd_npu_mem_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_npu_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <950000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_sysin>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c4m2_xfer>;
+	status = "okay";
+
+	fusb302: usb-typec@22 {
+		status = "okay";
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA7 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fusb302_int_l>;
+		vbus-supply = <&vbus_typec0>;
+
+		typec0_connect: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			power-role = "dual";
+			try-power-role = "sink";
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 5000, PDO_FIXED_USB_COMM)
+				     PDO_VAR(5000, 20000, 5000)
+				     PDO_PPS_APDO(5000, 20000, 5000)>;
+			op-sink-microwatt = <100000000>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&usbdp_phy0_orientation_switch>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usbc0_role_sw: endpoint {
+						remote-endpoint = <&dwc3_0_role_switch>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					dp_altmode_mux: endpoint {
+						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+					};
+				};
+			};
+		};
+	};
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "rtcic_32kout";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int_l>;
+	};
+};
+
+/*
+ * To LCD TFT
+ */
+&i2c5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c5m2_xfer>;
+	status = "disabled";
+};
+
+/*
+ * DIP14 output
+ * pin11: I2C6_SCL_M0
+ * pin13: I2C6_SDA_M0
+ */
+&i2c6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c6m0_xfer>;
+	status = "okay";
+};
+
+/*
+ * DIP14 output
+ * pin3: I2C7_SDA_M3
+ * pin5: I2C7_SCL_M3
+ */
+&i2c7 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c7m3_xfer>;
+	status = "okay";
+};
+
+&package_thermal {
+	polling-delay = <1000>;
+
+	trips {
+		package_fan0: package-fan0 {
+			hysteresis = <2000>;
+			temperature = <50000>;
+			type = "active";
+		};
+
+		package_fan1: package-fan1 {
+			hysteresis = <2000>;
+			temperature = <65000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+			trip = <&package_fan0>;
+		};
+		map1 {
+			cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+			trip = <&package_fan1>;
+		};
+	};
+};
+
+/* M.2 M-KEY PCIe */
+&pcie2x1l2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie20x1_2_perstn_m0>;
+	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_pcie>;
+	status = "okay";
+};
+
+&package_thermal {
+	polling-delay = <1000>;
+
+	trips {
+		package_fan0: package-fan0 {
+			temperature = <55000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		package_fan1: package-fan1 {
+			temperature = <65000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		map0 {
+			trip = <&package_fan0>;
+			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+		};
+
+		map1 {
+			trip = <&package_fan1>;
+			cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+		};
+	};
+};
+
+&pd_gpu {
+	domain-supply = <&vdd_gpu_s0>;
+};
+
+&pd_npu {
+	domain-supply = <&vdd_npu_s0>;
+};
+
+&pinctrl {
+	keys {
+		user_key: user-key {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	pcie {
+		pcie20x1_2_perstn_m0: pcie20x1-2-perstn-m0 {
+			rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pow_en: pow-en {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rtc {
+		hym8563_int_l: hym8563-int-l {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rtl8367rb {
+		rtl8367rb_power_en: rtl8367rb-power-en {
+			rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		fusb302_int_l: fusb302-int-l {
+			rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vbus_typec0_en: vbus-typec0-en {
+			rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb_hub_en: vcc5v0-usb-hub-en {
+			rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb3_host_en: vcc5v0-usb3-host-en {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+/* pwm fan */
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm3m1_pins>;
+	status = "okay";
+};
+
+&rknn_core_0 {
+	npu-supply = <&vdd_npu_s0>;
+	sram-supply = <&vdd_npu_mem_s0>;
+	status = "okay";
+};
+
+&rknn_core_1 {
+	npu-supply = <&vdd_npu_s0>;
+	sram-supply = <&vdd_npu_mem_s0>;
+	status = "okay";
+};
+
+&rknn_core_2 {
+	npu-supply = <&vdd_npu_s0>;
+	sram-supply = <&vdd_npu_mem_s0>;
+	status = "okay";
+};
+
+&rknn_mmu_0 {
+	status = "okay";
+};
+
+&rknn_mmu_1 {
+	status = "okay";
+};
+
+&rknn_mmu_2 {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	no-sdio;
+	no-sd;
+	non-removable;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	no-sdio;
+	no-mmc;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_s3>;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&sfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&fspim0_pins>;
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <104000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+/*
+ * DIP14 output
+ * pin8:  SPI0_MOSI_M2
+ * pin10: SPI0_MISO_M2
+ * pin12: SPI0_CLK_M2
+ * pin14: SPI0_CS0_M2
+ */
+&spi0 {
+	pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>;
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	num-cs = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		reg = <0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		spi-max-frequency = <1000000>;
+		system-power-controller;
+
+		vcc1-supply = <&vcc_sysin>;
+		vcc2-supply = <&vcc_sysin>;
+		vcc3-supply = <&vcc_sysin>;
+		vcc4-supply = <&vcc_sysin>;
+		vcc5-supply = <&vcc_sysin>;
+		vcc6-supply = <&vcc_sysin>;
+		vcc7-supply = <&vcc_sysin>;
+		vcc8-supply = <&vcc_sysin>;
+		vcc9-supply = <&vcc_sysin>;
+		vcc10-supply = <&vcc_sysin>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc_sysin>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcca_4v0>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: dcdc-reg1 {
+				regulator-name = "vdd_gpu_s0";
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: dcdc-reg2 {
+				regulator-name = "vdd_cpu_lit_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_logic_s0: dcdc-reg3 {
+				regulator-name = "vdd_logic_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: dcdc-reg4 {
+				regulator-name = "vdd_vdenc_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-name = "vdd_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-name = "vdd2_ddr_s3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-name = "vcc_2v0_pldo_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-name = "vcc_3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-name = "vddq_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-name = "vcc_1v8_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg1 {
+				regulator-name = "vcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca_1v8_s0: pldo-reg2 {
+				regulator-name = "vcca_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdda_1v2_s0: pldo-reg3 {
+				regulator-name = "vdda_1v2_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca_3v3_s0: pldo-reg4 {
+				regulator-name = "vcca_3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-name = "vccio_sd_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-name = "pldo6_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-name = "vdd_0v75_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdda_ddr_pll_s0: nldo-reg2 {
+				regulator-name = "vdda_ddr_pll_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdda_0v75_s0: nldo-reg3 {
+				regulator-name = "vdda_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdda_0v85_s0: nldo-reg4 {
+				regulator-name = "vdda_0v85_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-name = "vdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+/* TYPE-C otg phy */
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy2 {
+	status = "okay";
+};
+
+/* To USB2.0 HUB */
+&u2phy2_host {
+	phy-supply = <&vcc5v0_usb_hub>;
+	status = "okay";
+};
+
+&u2phy3 {
+	status = "okay";
+};
+
+/* To USB3.0 Type-A receptacle */
+&u2phy3_host {
+	phy-supply = <&vcc5v0_usb3_host>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+/*
+ * DIP14 output
+ * pin7: UART8_TX_M0
+ * pin9: UART8_RX_M0
+ */
+&uart8 {
+	pinctrl-0 = <&uart8m0_xfer>;
+	status = "okay";
+};
+
+/* typec0 usb/dp altmode mux phy */
+&usbdp_phy0 {
+	mode-switch;
+	orientation-switch;
+	sbu1-dc-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
+	sbu2-dc-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		usbdp_phy0_orientation_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+
+		usbdp_phy0_dp_altmode_mux: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&dp_altmode_mux>;
+		};
+	};
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+/* typec0 */
+&usb_host0_xhci {
+	dr_mode = "otg";
+	usb-role-switch;
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dwc3_0_role_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+/* To USB3.0 Type-A receptacle */
+&usb_host2_xhci {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};


================================================
FILE: kernel-patch/beta/deprecated-patches/6.18.y-308-dts-add-rk3568-series-devices.patch
================================================
From c9c6d3f181b38cda366823dda30575437a2fd18b Mon Sep 17 00:00:00 2001
From: ophub <68696949+ophub@users.noreply.github.com>
Date: Sat, 31 Jan 2026 21:27:17 +0800
Subject: [PATCH] arch: arm64: dts: rockchip: add rk3568 Series devices

---
 arch/arm64/boot/dts/rockchip/Makefile         |    3 +
 .../boot/dts/rockchip/rk3568-bdy-g18-pro.dts  | 1087 +++++++++++++++++
 .../boot/dts/rockchip/rk3568-nsy-g16-plus.dts | 1083 ++++++++++++++++
 .../boot/dts/rockchip/rk3568-nsy-g68-plus.dts | 1087 +++++++++++++++++
 4 files changed, 3260 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-bdy-g18-pro.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nsy-g16-plus.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nsy-g68-plus.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index c5d6ec738..df027c886 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -157,6 +157,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-tinker-board-3s.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-wxy-oec-turbo-4g.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-9tripod-x3568-v4.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bdy-g18-pro.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-dg-tn3568.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-easepi-r1.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ec-x.dtb
@@ -170,6 +171,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mecsbc.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mrkaio-m68s.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nsy-g16-plus.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nsy-g68-plus.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-photonicat.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bdy-g18-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bdy-g18-pro.dts
new file mode 100644
index 000000000..07792a291
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-bdy-g18-pro.dts
@@ -0,0 +1,1087 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "BDY-G18 AX3000 Router";
+	compatible = "bdy,g18-pro", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		mmc0 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	fiq-debugger {
+		compatible = "rockchip,fiq-debugger";
+		rockchip,serial-id = <2>;
+		rockchip,wake-irq = <0>;
+		/* If enable uart uses irq instead of fiq */
+		rockchip,irq-mode-enable = <1>;
+		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
+		interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart2m0_xfer>;
+		status = "okay";
+	};
+
+	debug: debug@fd904000 {
+		compatible = "rockchip,debug";
+		reg = <0x0 0xfd904000 0x0 0x1000>,
+			<0x0 0xfd905000 0x0 0x1000>,
+			<0x0 0xfd906000 0x0 0x1000>,
+			<0x0 0xfd907000 0x0 0x1000>;
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb: vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_usb>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+	};
+
+	vcc5v0_otg: vcc5v0-otg-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-boot-on;
+		regulator-always-on;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_usb>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg_en>;
+	};
+
+	vcc3v3_lcd0_n: vcc3v3-lcd0-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd0_n";
+		regulator-boot-on;
+		gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		pinctrl-0 = <&vcc3v3_lcd0_n_en>;
+		pinctrl-names = "default";
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+
+	};
+
+	vcc3v3_lcd1_n: vcc3v3-lcd1-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd1_n";
+		regulator-boot-on;
+		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		pinctrl-0 = <&vcc3v3_lcd1_n_en>;
+		pinctrl-names = "default";
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		post-power-on-delay-ms = <200>;
+		reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc1v8_adc: vcc1v8-adc {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_adc";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc2v5_ddr: vcc2v5-ddr {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc2v5-sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_vga: vcc3v3-vga {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_vga";
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&vcc3v3_vga_en>;
+		pinctrl-names = "default";
+		enable-active-high;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	pcie30_avdd0v9: pcie30-avdd0v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	pcie30_avdd1v8: pcie30-avdd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&vcc3v3_pcie_en>;
+		pinctrl-names = "default";
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+    /* Fix the node name typo */
+	vcc3v3_bu: vcc3v3-bu {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_bu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_camera: vcc-camera-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&camera_pwr>;
+		regulator-name = "vcc_camera";
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_cpu: vdd-cpu {
+		compatible = "pwm-regulator";
+		rockchip,pwm_id = <0>;
+		rockchip,pwm_voltage = <900000>;
+		pwms = <&pwm0 0 25000 1>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-init-microvolt = <1150000>;
+		regulator-enable-ramp-delay = <300>;
+		regulator-ramp-delay = <8000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	gmac0_xpcsclk: xpcs-gmac0-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clk_gmac0_xpcs_mii";
+		#clock-cells = <0>;
+	};
+
+	gmac1_xpcsclk: xpcs-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clk_gmac1_xpcs_mii";
+		#clock-cells = <0>;
+	};
+
+	adc_keys: adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+		status = "okay";
+		recovery-key {
+			label = "F12";
+			linux,code = <KEY_F12>;
+			press-threshold-microvolt = <1750>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led-power {
+			label = "led-power";
+			default-state = "on";
+			gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_power_en>;
+		};
+	};
+};
+
+&i2c0 {
+
+	status = "okay";
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default", "pmic-sleep", "pmic-power-off", "pmic-reset";
+		pinctrl-0 = <&pmic_int>;
+		pinctrl-1 = <&soc_slppin_slp &rk817_slppin_slp>;
+		pinctrl-2 = <&soc_slppin_gpio &rk817_slppin_pwrdn>;
+		pinctrl-3 = <&soc_slppin_gpio &rk817_slppin_rst>;
+		rockchip,system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1\0rk808-clkout2";
+		pmic-reset-func = <0>;
+		not-save-power-en = <1>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		pwrkey {
+			status = "okay";
+		};
+
+		pinctrl_rk8xx: pinctrl_rk8xx {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			rk817_slppin_null: rk817_slppin_null {
+				pins = "gpio_slp";
+				function = "pin_fun0";
+			};
+
+			rk817_slppin_slp: rk817_slppin_slp {
+				pins = "gpio_slp";
+				function = "pin_fun1";
+			};
+
+			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
+				pins = "gpio_slp";
+				function = "pin_fun2";
+			};
+
+			rk817_slppin_rst: rk817_slppin_rst {
+				pins = "gpio_slp";
+				function = "pin_fun3";
+			};
+		};
+
+		regulators {
+
+			vdd_logic: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <2>;
+				regulator-name = "vdd_logic";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <1000000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <2>;
+				regulator-name = "vdd_gpu";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <2>;
+				regulator-name = "vcc_ddr";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <1000000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <2>;
+				regulator-name = "vdd_npu";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vccio_acodec";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_3v3";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&pinctrl {
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		
+		vcc5v0_otg_en: vcc5v0-otg-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	regulator-en {
+		vcc3v3_lcd0_n_en: vcc3v3-lcd0-n-en {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc3v3_lcd1_n_en: vcc3v3-lcd1-n-en {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc3v3_vga_en: vcc3v3-vga-en {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		camera_pwr: camera-pwr {
+			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc3v3_pcie_en: vcc3v3-pcie-en {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+	
+		pmic_int: pmic-intl {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	
+		soc_slppin_gpio: soc-slppin-gpio {
+			rockchip,pins = <0 RK_PA2 0 &pcfg_output_low>;
+		};
+	
+		soc_slppin_slp: soc-slppin-slp {
+			rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>;
+		};
+	
+		soc_slppin_rst {
+			rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie30x1_reset_h: pcie30x1-reset-h {
+			rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		pcie30x2_reset_h: pcie30x2-reset-h {
+			rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		pcie2x1_reset_h: pcie2x1-reset-h {
+			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	gmac-reset {
+		gmac0_reset: gmac0-reset {
+			rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		gmac1_reset: gmac1-reset {
+			rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_power_en: led-power-en {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&pcie30_phy_grf {
+};
+
+// 注意两条 pcie reset gpio 均与 NSY不同
+// fe270000
+// 这里需要更换uboot版本,因为只有支持的pcie拆分的才能启动这个
+// 不然开启就挂死,更换版本:https://github.com/Kwiboo/u-boot-rockchip
+// https://lists.denx.de/pipermail/u-boot/2023-August/525793.html
+// 这个pcie,可能需要打补丁,使用radxa 版本
+&pcie3x1 {
+		vpcie3v3-supply = <&vcc3v3_pcie>;
+		reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
+		num-lanes = <0x1>; /*可能不生效,但是拆分需要打补丁,如果是吧,打补丁*/
+		pinctrl-0 = <&pcie30x1_reset_h>;
+		status = "disabled";
+};
+
+//fe280000
+&pcie3x2 {
+		vpcie3v3-supply = <&vcc3v3_pcie>;
+		reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+		num-lanes = <0x2>;
+		pinctrl-0 = <&pcie30x2_reset_h>;
+};
+
+&pcie30phy {
+		data-lanes = <1 2>; //配置lan的通道树
+		status = "okay";
+};
+
+&combphy2 {
+		status = "okay";
+};
+
+&pcie2x1 {
+		reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&pcie2x1_reset_h>;
+		//for kernel.dts
+		rockchip,perst-inactive-ms = <500>;
+		status = "okay";
+};
+
+/*使用DSA驱动模型*/
+&mdio0 {
+	#address-cells = <1>;
+    #size-cells = <0>;
+
+	rtl8367s: switch@29 {
+			compatible = "realtek,rtl8365mb";
+			reg = <29>;
+
+			reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
+			pinctrl-names = "default";
+			reset-assert-us = <20000>;
+			reset-deassert-us = <100000>;
+			pinctrl-0 = <&gmac0_reset>;
+
+			ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+							reg = <0>;
+							label = "wan";
+					};
+
+					port@1 {
+							reg = <1>;
+							label = "lan1";
+					};
+
+					port@2 {
+							reg = <2>;
+							label = "lan2";
+					};
+
+					port@3 {
+							reg = <3>;
+							label = "lan3";
+					};
+
+					port@4 {
+							reg = <4>;
+							label = "lan4";
+					};
+					port@7 {
+							reg = <7>;
+							ethernet = <&gmac0>;
+							phy-mode = "rgmii";
+							tx-internal-delay-ps = <0>;
+							rx-internal-delay-ps = <0>;
+
+							fixed-link {
+									speed = <1000>;
+									full-duplex;
+							};
+					};
+
+			};
+	};
+};
+
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii";
+	clock_in_out = "output";
+	// reset gpio 写到交换机配置里面
+	//snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
+	//snps,reset-active-low;
+	//snps,reset-delays-us = <0x0 20000 100000>;
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX &cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED &cru CLK_MAC0_2TOP>;
+	assigned-clock-rates = <0x0 125000000>;
+	tx_delay = <0x3c>;
+	rx_delay = <0x2f>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim &gmac0_tx_bus2 &gmac0_rx_bus2 &gmac0_rgmii_clk &gmac0_rgmii_bus /*&gmac0_reset*/>;
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+		pause;
+	};
+};
+
+&mdio1 {
+	status = "okay";
+};
+
+&pipe_phy_grf1 {
+	status = "okay";
+};
+
+&combphy1 {
+	rockchip,sgmii-mac-sel = <1>;
+	status = "okay";
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>;
+	assigned-clock-parents = <&gmac1_xpcsclk>;
+	status = "okay";
+	phy-mode = "sgmii";
+	rockchip,pipegrf = <&pipegrf>;
+	//snps,reset-gpio = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
+	//snps,reset-active-low;
+	//snps,reset-delays-us = <0 20000 100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim>;
+	power-domains = <&power RK3568_PD_PIPE>;
+	phys = <&combphy1 PHY_TYPE_SGMII>;
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+	snps,dis_enblslpm_quirk;
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+	snps,dis-u2-freeclk-exists-quirk;
+	snps,dis-del-phy-power-chg-quirk;
+	snps,dis-tx-ipgap-linecheck-quirk;
+	snps,dis_rxdet_inp3_quirk;
+	snps,xhci-trb-ent-quirk;
+	snps,parkmode-disable-ss-quirk;
+	quirk-skip-phy-init;
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";//自动检测
+	//extcon = <&combphy0>;
+	status = "okay";
+	extcon = <&usb2phy0>; //超过rxda测试
+	snps,dis_enblslpm_quirk;
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+	snps,dis-u2-freeclk-exists-quirk;
+	snps,dis-del-phy-power-chg-quirk;
+	snps,dis-tx-ipgap-linecheck-quirk;
+	snps,dis_rxdet_inp3_quirk;
+	snps,xhci-trb-ent-quirk;
+	snps,parkmode-disable-ss-quirk;
+	quirk-skip-phy-init;
+};
+
+&usb_host1_ehci {
+	status = "disabled";
+};
+
+&usb_host1_ohci {
+	status = "disabled";
+};
+
+&usb_host1_xhci {
+	dr_mode = "host";//自动检测
+	snps,dis_enblslpm_quirk;
+	snps,dis-u2-freeclk-exists-quirk;
+	snps,dis-del-phy-power-chg-quirk;
+	snps,dis-tx-ipgap-linecheck-quirk;
+	snps,dis_rxdet_inp3_quirk;
+	snps,xhci-trb-ent-quirk;
+	snps,parkmode-disable-ss-quirk;
+	status = "disabled";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "disabled";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "disabled";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "disabled";
+};
+
+&sata2 {
+	status = "disabled";
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vcc_3v3>;
+	vccio3-supply = <&vcc_3v3>;
+	vccio4-supply = <&vcc_3v3>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "disabled";
+};
+
+&pwm3 {
+	status = "disabled";
+};
+
+&power {
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&vpu {
+	status = "okay";
+};
+
+&rga {
+	status = "okay";
+};
+
+&vepu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+//sdhci@fe310000
+&sdhci {
+	max-frequency = <200000000>;
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	supports-emmc;
+	non-removable;
+	mmc-hs200-1_8v;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	status = "okay";
+};
+
+//dwmmc@fe000000
+&sdmmc2 {
+	max-frequency = <150000000>;
+	fifo-depth = <256>;
+	no-sd;
+	no-mmc;
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	sd-uhs-sdr104;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
+	status = "disabled";
+};
+
+//dwmmc@fe2b0000
+&sdmmc0 {
+	max-frequency = <150000000>;
+	fifo-depth = <256>;
+	no-sdio;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	status = "disabled";
+};
+
+&combphy0 {
+	status = "okay";
+};
+
+&csi_dphy {
+	status = "okay";
+};
+
+/* Add #address-cells, #size-cells */
+&sfc {
+	status = "okay";
+	#address-cells = <1>;  /* One cell for the chip select */
+	#size-cells = <0>;     /* No cell for the size */
+
+	flash@0 {
+		compatible = "spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&rng {
+	status = "okay";
+};
+
+//i2c@fe5a0000
+&i2c1 {
+	status = "disabled";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "disabled";
+};
+
+&wdt {
+	status = "okay";
+};
+
+&uart8 {
+	status = "disabled";
+};
+
+&pwm4 {
+	status = "disabled";
+};
+
+&pwm5 {
+	status = "disabled";
+};
+
+&pwm7 {
+	status = "disabled";
+};
+
+&pwm8 {
+	status = "disabled";
+};
+
+&pwm9 {
+	status = "disabled";
+};
+
+//fe720000
+&saradc {
+	status = "okay";
+	vref-supply = <&vcc1v8_adc>;
+};
\ No newline at end of file
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nsy-g16-plus.dts b/arch/arm64/boot/dts/rockchip/rk3568-nsy-g16-plus.dts
new file mode 100644
index 000000000..4fbbc24f0
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nsy-g16-plus.dts
@@ -0,0 +1,1083 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "NSY-G16 AX3000 Router";
+	compatible = "nsy,g16-plus", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		mmc0 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	fiq-debugger {
+		compatible = "rockchip,fiq-debugger";
+		rockchip,serial-id = <2>;
+		rockchip,wake-irq = <0>;
+		/* If enable uart uses irq instead of fiq */
+		rockchip,irq-mode-enable = <1>;
+		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
+		interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart2m0_xfer>;
+		status = "okay";
+	};
+
+	debug: debug@fd904000 {
+		compatible = "rockchip,debug";
+		reg = <0x0 0xfd904000 0x0 0x1000>,
+			<0x0 0xfd905000 0x0 0x1000>,
+			<0x0 0xfd906000 0x0 0x1000>,
+			<0x0 0xfd907000 0x0 0x1000>;
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb: vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_usb>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+	};
+
+	vcc5v0_otg: vcc5v0-otg-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-boot-on;
+		regulator-always-on;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_usb>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg_en>;
+	};
+
+	vcc3v3_lcd0_n: vcc3v3-lcd0-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd0_n";
+		regulator-boot-on;
+		gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		pinctrl-0 = <&vcc3v3_lcd0_n_en>;
+		pinctrl-names = "default";
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+
+	};
+
+	vcc3v3_lcd1_n: vcc3v3-lcd1-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd1_n";
+		regulator-boot-on;
+		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		pinctrl-0 = <&vcc3v3_lcd1_n_en>;
+		pinctrl-names = "default";
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		post-power-on-delay-ms = <200>;
+		reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc1v8_adc: vcc1v8-adc {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_adc";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc2v5_ddr: vcc2v5-ddr {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc2v5-sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_vga: vcc3v3-vga {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_vga";
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&vcc3v3_vga_en>;
+		pinctrl-names = "default";
+		enable-active-high;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	pcie30_avdd0v9: pcie30-avdd0v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	pcie30_avdd1v8: pcie30-avdd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&vcc3v3_pcie_en>;
+		pinctrl-names = "default";
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	/* Fix the node name typo */
+	vcc3v3_bu: vcc3v3-bu {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_bu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_camera: vcc-camera-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&camera_pwr>;
+		regulator-name = "vcc_camera";
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_cpu: vdd-cpu {
+		compatible = "pwm-regulator";
+		rockchip,pwm_id = <0>;
+		rockchip,pwm_voltage = <900000>;
+		pwms = <&pwm0 0 25000 1>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-init-microvolt = <1150000>;
+		regulator-enable-ramp-delay = <300>;
+		regulator-ramp-delay = <8000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	gmac0_xpcsclk: xpcs-gmac0-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clk_gmac0_xpcs_mii";
+		#clock-cells = <0>;
+	};
+
+	gmac1_xpcsclk: xpcs-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clk_gmac1_xpcs_mii";
+		#clock-cells = <0>;
+	};
+
+	adc_keys: adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+		status = "okay";
+		recovery-key {
+			label = "F12";
+			linux,code = <KEY_F12>;
+			press-threshold-microvolt = <1750>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led-power {
+			label = "led-power";
+			default-state = "on";
+			gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_power_en>;
+		};
+	};
+};
+
+&i2c0 {
+
+	status = "okay";
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default", "pmic-sleep", "pmic-power-off", "pmic-reset";
+		pinctrl-0 = <&pmic_int>;
+		pinctrl-1 = <&soc_slppin_slp &rk817_slppin_slp>;
+		pinctrl-2 = <&soc_slppin_gpio &rk817_slppin_pwrdn>;
+		pinctrl-3 = <&soc_slppin_gpio &rk817_slppin_rst>;
+		rockchip,system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1\0rk808-clkout2";
+		pmic-reset-func = <0>;
+		not-save-power-en = <1>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		pwrkey {
+			status = "okay";
+		};
+
+		pinctrl_rk8xx: pinctrl_rk8xx {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			rk817_slppin_null: rk817_slppin_null {
+				pins = "gpio_slp";
+				function = "pin_fun0";
+			};
+
+			rk817_slppin_slp: rk817_slppin_slp {
+				pins = "gpio_slp";
+				function = "pin_fun1";
+			};
+
+			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
+				pins = "gpio_slp";
+				function = "pin_fun2";
+			};
+
+			rk817_slppin_rst: rk817_slppin_rst {
+				pins = "gpio_slp";
+				function = "pin_fun3";
+			};
+		};
+
+		regulators {
+
+			vdd_logic: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <2>;
+				regulator-name = "vdd_logic";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <1000000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <2>;
+				regulator-name = "vdd_gpu";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <2>;
+				regulator-name = "vcc_ddr";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <1000000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <2>;
+				regulator-name = "vdd_npu";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vccio_acodec";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_3v3";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&pinctrl {
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		
+		vcc5v0_otg_en: vcc5v0-otg-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	regulator-en {
+		vcc3v3_lcd0_n_en: vcc3v3-lcd0-n-en {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc3v3_lcd1_n_en: vcc3v3-lcd1-n-en {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc3v3_vga_en: vcc3v3-vga-en {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		camera_pwr: camera-pwr {
+			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc3v3_pcie_en: vcc3v3-pcie-en {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+	
+		pmic_int: pmic-intl {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	
+		soc_slppin_gpio: soc-slppin-gpio {
+			rockchip,pins = <0 RK_PA2 0 &pcfg_output_low>;
+		};
+	
+		soc_slppin_slp: soc-slppin-slp {
+			rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>;
+		};
+	
+		soc_slppin_rst {
+			rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie30x1_reset_h: pcie30x1-reset-h {
+			rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		pcie30x2_reset_h: pcie30x2-reset-h {
+			rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		pcie2x1_reset_h: pcie2x1-reset-h {
+			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	gmac-reset {
+		gmac0_reset: gmac0-reset {
+			rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		gmac1_reset: gmac1-reset {
+			rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_power_en: led-power-en {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&pcie30_phy_grf {
+};
+
+// 注意两条 pcie reset gpio 均与 NSY不同
+// fe270000
+// 这里需要更换uboot版本,因为只有支持的pcie拆分的才能启动这个
+// 不然开启就挂死,更换版本:https://github.com/Kwiboo/u-boot-rockchip
+// https://lists.denx.de/pipermail/u-boot/2023-August/525793.html
+// 这个pcie,可能需要打补丁,使用radxa 版本
+&pcie3x1 {
+		vpcie3v3-supply = <&vcc3v3_pcie>;
+		reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
+		num-lanes = <0x1>; /*可能不生效,但是拆分需要打补丁,如果是吧,打补丁*/
+		pinctrl-0 = <&pcie30x1_reset_h>;
+		status = "disabled";
+};
+
+//fe280000
+&pcie3x2 {
+		vpcie3v3-supply = <&vcc3v3_pcie>;
+		reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+		num-lanes = <0x2>;
+		pinctrl-0 = <&pcie30x2_reset_h>;
+};
+
+&pcie30phy {
+		data-lanes = <1 2>; //配置lan的通道树
+		status = "okay";
+};
+
+&combphy2 {
+		status = "okay";
+};
+
+&pcie2x1 {
+		reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&pcie2x1_reset_h>;
+		//for kernel.dts
+		rockchip,perst-inactive-ms = <500>;
+		status = "okay";
+};
+
+/*使用DSA驱动模型*/
+&mdio0 {
+	#address-cells = <1>;
+    #size-cells = <0>;
+
+	rtl8367s: switch@29 {
+			compatible = "realtek,rtl8365mb";
+			reg = <29>;
+
+			reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
+			pinctrl-names = "default";
+			reset-assert-us = <20000>;
+			reset-deassert-us = <100000>;
+			pinctrl-0 = <&gmac0_reset>;
+
+			ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+							reg = <0>;
+							label = "wan";
+					};
+
+					port@1 {
+							reg = <1>;
+							label = "lan1";
+					};
+
+					port@2 {
+							reg = <2>;
+							label = "lan2";
+					};
+
+					port@3 {
+							reg = <3>;
+							label = "lan3";
+					};
+
+					port@7 {
+							reg = <7>;
+							ethernet = <&gmac0>;
+							phy-mode = "rgmii";
+							tx-internal-delay-ps = <0>;
+							rx-internal-delay-ps = <0>;
+
+							fixed-link {
+									speed = <1000>;
+									full-duplex;
+							};
+					};
+
+			};
+	};
+};
+
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii";
+	clock_in_out = "output";
+	// reset gpio 写到交换机配置里面
+	//snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
+	//snps,reset-active-low;
+	//snps,reset-delays-us = <0x0 20000 100000>;
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX &cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED &cru CLK_MAC0_2TOP>;
+	assigned-clock-rates = <0x0 125000000>;
+	tx_delay = <0x3c>;
+	rx_delay = <0x2f>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim &gmac0_tx_bus2 &gmac0_rx_bus2 &gmac0_rgmii_clk &gmac0_rgmii_bus /*&gmac0_reset*/>;
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+		pause;
+	};
+};
+
+&mdio1 {
+	status = "okay";
+};
+
+&pipe_phy_grf1 {
+	status = "okay";
+};
+
+&combphy1 {
+	rockchip,sgmii-mac-sel = <1>;
+	status = "okay";
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>;
+	assigned-clock-parents = <&gmac1_xpcsclk>;
+	status = "okay";
+	phy-mode = "sgmii";
+	rockchip,pipegrf = <&pipegrf>;
+	//snps,reset-gpio = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
+	//snps,reset-active-low;
+	//snps,reset-delays-us = <0 20000 100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim>;
+	power-domains = <&power RK3568_PD_PIPE>;
+	phys = <&combphy1 PHY_TYPE_SGMII>;
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+	snps,dis_enblslpm_quirk;
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+	snps,dis-u2-freeclk-exists-quirk;
+	snps,dis-del-phy-power-chg-quirk;
+	snps,dis-tx-ipgap-linecheck-quirk;
+	snps,dis_rxdet_inp3_quirk;
+	snps,xhci-trb-ent-quirk;
+	snps,parkmode-disable-ss-quirk;
+	quirk-skip-phy-init;
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";//自动检测
+	//extcon = <&combphy0>;
+	status = "okay";
+	extcon = <&usb2phy0>; //超过rxda测试
+	snps,dis_enblslpm_quirk;
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+	snps,dis-u2-freeclk-exists-quirk;
+	snps,dis-del-phy-power-chg-quirk;
+	snps,dis-tx-ipgap-linecheck-quirk;
+	snps,dis_rxdet_inp3_quirk;
+	snps,xhci-trb-ent-quirk;
+	snps,parkmode-disable-ss-quirk;
+	quirk-skip-phy-init;
+};
+
+&usb_host1_ehci {
+	status = "disabled";
+};
+
+&usb_host1_ohci {
+	status = "disabled";
+};
+
+&usb_host1_xhci {
+	dr_mode = "host";//自动检测
+	snps,dis_enblslpm_quirk;
+	snps,dis-u2-freeclk-exists-quirk;
+	snps,dis-del-phy-power-chg-quirk;
+	snps,dis-tx-ipgap-linecheck-quirk;
+	snps,dis_rxdet_inp3_quirk;
+	snps,xhci-trb-ent-quirk;
+	snps,parkmode-disable-ss-quirk;
+	status = "disabled";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "disabled";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "disabled";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "disabled";
+};
+
+&sata2 {
+	status = "disabled";
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vcc_3v3>;
+	vccio3-supply = <&vcc_3v3>;
+	vccio4-supply = <&vcc_3v3>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "disabled";
+};
+
+&pwm3 {
+	status = "disabled";
+};
+
+&power {
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&vpu {
+	status = "okay";
+};
+
+&rga {
+	status = "okay";
+};
+
+&vepu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+//sdhci@fe310000
+&sdhci {
+	max-frequency = <200000000>;
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	supports-emmc;
+	non-removable;
+	mmc-hs200-1_8v;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	status = "okay";
+};
+
+//dwmmc@fe000000
+&sdmmc2 {
+	max-frequency = <150000000>;
+	fifo-depth = <256>;
+	no-sd;
+	no-mmc;
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	sd-uhs-sdr104;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
+	status = "disabled";
+};
+
+//dwmmc@fe2b0000
+&sdmmc0 {
+	max-frequency = <150000000>;
+	fifo-depth = <256>;
+	no-sdio;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	status = "disabled";
+};
+
+&combphy0 {
+	status = "okay";
+};
+
+&csi_dphy {
+	status = "okay";
+};
+
+/* Add #address-cells, #size-cells */
+&sfc {
+	status = "okay";
+	#address-cells = <1>;  /* One cell for the chip select */
+	#size-cells = <0>;     /* No cell for the size */
+
+	flash@0 {
+		compatible = "spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&rng {
+	status = "okay";
+};
+
+//i2c@fe5a0000
+&i2c1 {
+	status = "disabled";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "disabled";
+};
+
+&wdt {
+	status = "okay";
+};
+
+&uart8 {
+	status = "disabled";
+};
+
+&pwm4 {
+	status = "disabled";
+};
+
+&pwm5 {
+	status = "disabled";
+};
+
+&pwm7 {
+	status = "disabled";
+};
+
+&pwm8 {
+	status = "disabled";
+};
+
+&pwm9 {
+	status = "disabled";
+};
+
+//fe720000
+&saradc {
+	status = "okay";
+	vref-supply = <&vcc1v8_adc>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nsy-g68-plus.dts b/arch/arm64/boot/dts/rockchip/rk3568-nsy-g68-plus.dts
new file mode 100644
index 000000000..425d9de9b
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nsy-g68-plus.dts
@@ -0,0 +1,1087 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "NSY-G68 AX3000 Router";
+	compatible = "nsy,g68-plus", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		mmc0 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	fiq-debugger {
+		compatible = "rockchip,fiq-debugger";
+		rockchip,serial-id = <2>;
+		rockchip,wake-irq = <0>;
+		/* If enable uart uses irq instead of fiq */
+		rockchip,irq-mode-enable = <1>;
+		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
+		interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart2m0_xfer>;
+		status = "okay";
+	};
+
+	debug: debug@fd904000 {
+		compatible = "rockchip,debug";
+		reg = <0x0 0xfd904000 0x0 0x1000>,
+			<0x0 0xfd905000 0x0 0x1000>,
+			<0x0 0xfd906000 0x0 0x1000>,
+			<0x0 0xfd907000 0x0 0x1000>;
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb: vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_usb>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+	};
+
+	vcc5v0_otg: vcc5v0-otg-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-boot-on;
+		regulator-always-on;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_usb>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg_en>;
+	};
+
+	vcc3v3_lcd0_n: vcc3v3-lcd0-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd0_n";
+		regulator-boot-on;
+		gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		pinctrl-0 = <&vcc3v3_lcd0_n_en>;
+		pinctrl-names = "default";
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+
+	};
+
+	vcc3v3_lcd1_n: vcc3v3-lcd1-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd1_n";
+		regulator-boot-on;
+		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		pinctrl-0 = <&vcc3v3_lcd1_n_en>;
+		pinctrl-names = "default";
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		post-power-on-delay-ms = <200>;
+		reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc1v8_adc: vcc1v8-adc {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_adc";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc2v5_ddr: vcc2v5-ddr {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc2v5-sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_vga: vcc3v3-vga {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_vga";
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&vcc3v3_vga_en>;
+		pinctrl-names = "default";
+		enable-active-high;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	pcie30_avdd0v9: pcie30-avdd0v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	pcie30_avdd1v8: pcie30-avdd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&vcc3v3_pcie_en>;
+		pinctrl-names = "default";
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	/* Fix the node name typo */
+	vcc3v3_bu: vcc3v3-bu {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_bu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_camera: vcc-camera-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&camera_pwr>;
+		regulator-name = "vcc_camera";
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_cpu: vdd-cpu {
+		compatible = "pwm-regulator";
+		rockchip,pwm_id = <0>;
+		rockchip,pwm_voltage = <900000>;
+		pwms = <&pwm0 0 25000 1>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-init-microvolt = <1150000>;
+		regulator-enable-ramp-delay = <300>;
+		regulator-ramp-delay = <8000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	gmac0_xpcsclk: xpcs-gmac0-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clk_gmac0_xpcs_mii";
+		#clock-cells = <0>;
+	};
+
+	gmac1_xpcsclk: xpcs-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clk_gmac1_xpcs_mii";
+		#clock-cells = <0>;
+	};
+
+	adc_keys: adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+		status = "okay";
+		recovery-key {
+			label = "F12";
+			linux,code = <KEY_F12>;
+			press-threshold-microvolt = <1750>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led-power {
+			label = "led-power";
+			default-state = "on";
+			gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_power_en>;
+		};
+	};
+};
+
+&i2c0 {
+
+	status = "okay";
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default", "pmic-sleep", "pmic-power-off", "pmic-reset";
+		pinctrl-0 = <&pmic_int>;
+		pinctrl-1 = <&soc_slppin_slp &rk817_slppin_slp>;
+		pinctrl-2 = <&soc_slppin_gpio &rk817_slppin_pwrdn>;
+		pinctrl-3 = <&soc_slppin_gpio &rk817_slppin_rst>;
+		rockchip,system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1\0rk808-clkout2";
+		pmic-reset-func = <0>;
+		not-save-power-en = <1>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		pwrkey {
+			status = "okay";
+		};
+
+		pinctrl_rk8xx: pinctrl_rk8xx {
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			rk817_slppin_null: rk817_slppin_null {
+				pins = "gpio_slp";
+				function = "pin_fun0";
+			};
+
+			rk817_slppin_slp: rk817_slppin_slp {
+				pins = "gpio_slp";
+				function = "pin_fun1";
+			};
+
+			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
+				pins = "gpio_slp";
+				function = "pin_fun2";
+			};
+
+			rk817_slppin_rst: rk817_slppin_rst {
+				pins = "gpio_slp";
+				function = "pin_fun3";
+			};
+		};
+
+		regulators {
+
+			vdd_logic: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <2>;
+				regulator-name = "vdd_logic";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <1000000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <2>;
+				regulator-name = "vdd_gpu";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <2>;
+				regulator-name = "vcc_ddr";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <1000000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <2>;
+				regulator-name = "vdd_npu";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vccio_acodec";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_3v3";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&pinctrl {
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		
+		vcc5v0_otg_en: vcc5v0-otg-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	regulator-en {
+		vcc3v3_lcd0_n_en: vcc3v3-lcd0-n-en {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc3v3_lcd1_n_en: vcc3v3-lcd1-n-en {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc3v3_vga_en: vcc3v3-vga-en {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		camera_pwr: camera-pwr {
+			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		vcc3v3_pcie_en: vcc3v3-pcie-en {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+	
+		pmic_int: pmic-intl {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	
+		soc_slppin_gpio: soc-slppin-gpio {
+			rockchip,pins = <0 RK_PA2 0 &pcfg_output_low>;
+		};
+	
+		soc_slppin_slp: soc-slppin-slp {
+			rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>;
+		};
+	
+		soc_slppin_rst {
+			rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie30x1_reset_h: pcie30x1-reset-h {
+			rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		pcie30x2_reset_h: pcie30x2-reset-h {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		pcie2x1_reset_h: pcie2x1-reset-h {
+			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	gmac-reset {
+		gmac0_reset: gmac0-reset {
+			rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		gmac1_reset: gmac1-reset {
+			rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_power_en: led-power-en {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&pcie30_phy_grf {
+};
+
+// 注意两条 pcie reset gpio 均与 NSY不同
+// fe270000
+// 这里需要更换uboot版本,因为只有支持的pcie拆分的才能启动这个
+// 不然开启就挂死,更换版本:https://github.com/Kwiboo/u-boot-rockchip
+// https://lists.denx.de/pipermail/u-boot/2023-August/525793.html
+// 这个pcie,可能需要打补丁,使用radxa 版本
+&pcie3x1 {
+		vpcie3v3-supply = <&vcc3v3_pcie>;
+		reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
+		num-lanes = <0x1>; /*可能不生效,但是拆分需要打补丁,如果是吧,打补丁*/
+		pinctrl-0 = <&pcie30x1_reset_h>;
+		status = "okay";
+};
+
+//fe280000
+&pcie3x2 {
+		vpcie3v3-supply = <&vcc3v3_pcie>;
+		reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+		num-lanes = <0x1>;
+		pinctrl-0 = <&pcie30x2_reset_h>;
+};
+
+&pcie30phy {
+		data-lanes = <1 2>; //配置lan的通道树
+		status = "okay";
+};
+
+&combphy2 {
+		status = "okay";
+};
+
+&pcie2x1 {
+		reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&pcie2x1_reset_h>;
+		//for kernel.dts
+		rockchip,perst-inactive-ms = <500>;
+		status = "okay";
+};
+
+/*使用DSA驱动模型*/
+&mdio0 {
+	#address-cells = <1>;
+    #size-cells = <0>;
+
+	rtl8367s: switch@29 {
+			compatible = "realtek,rtl8365mb";
+			reg = <29>;
+
+			reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
+			pinctrl-names = "default";
+			reset-assert-us = <20000>;
+			reset-deassert-us = <100000>;
+			pinctrl-0 = <&gmac0_reset>;
+
+			ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+							reg = <0>;
+							label = "lan1";
+					};
+
+					port@1 {
+							reg = <1>;
+							label = "lan2";
+					};
+
+					port@2 {
+							reg = <2>;
+							label = "lan3";
+					};
+
+					port@3 {
+							reg = <3>;
+							label = "lan4";
+					};
+
+					port@4 {
+							reg = <4>;
+							label = "wan";
+					};
+					port@7 {
+							reg = <7>;
+							ethernet = <&gmac0>;
+							phy-mode = "rgmii";
+							tx-internal-delay-ps = <0>;
+							rx-internal-delay-ps = <0>;
+
+							fixed-link {
+									speed = <1000>;
+									full-duplex;
+							};
+					};
+
+			};
+	};
+};
+
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii";
+	clock_in_out = "output";
+	// reset gpio 写到交换机配置里面
+	//snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
+	//snps,reset-active-low;
+	//snps,reset-delays-us = <0x0 20000 100000>;
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX &cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED &cru CLK_MAC0_2TOP>;
+	assigned-clock-rates = <0x0 125000000>;
+	tx_delay = <0x3c>;
+	rx_delay = <0x2f>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim &gmac0_tx_bus2 &gmac0_rx_bus2 &gmac0_rgmii_clk &gmac0_rgmii_bus /*&gmac0_reset*/>;
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+		pause;
+	};
+};
+
+&mdio1 {
+	status = "okay";
+};
+
+&pipe_phy_grf1 {
+	status = "okay";
+};
+
+&combphy1 {
+	rockchip,sgmii-mac-sel = <1>;
+	status = "okay";
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>;
+	assigned-clock-parents = <&gmac1_xpcsclk>;
+	status = "okay";
+	phy-mode = "sgmii";
+	rockchip,pipegrf = <&pipegrf>;
+	//snps,reset-gpio = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
+	//snps,reset-active-low;
+	//snps,reset-delays-us = <0 20000 100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim>;
+	power-domains = <&power RK3568_PD_PIPE>;
+	phys = <&combphy1 PHY_TYPE_SGMII>;
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+	snps,dis_enblslpm_quirk;
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+	snps,dis-u2-freeclk-exists-quirk;
+	snps,dis-del-phy-power-chg-quirk;
+	snps,dis-tx-ipgap-linecheck-quirk;
+	snps,dis_rxdet_inp3_quirk;
+	snps,xhci-trb-ent-quirk;
+	snps,parkmode-disable-ss-quirk;
+	quirk-skip-phy-init;
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";//自动检测
+	//extcon = <&combphy0>;
+	status = "okay";
+	extcon = <&usb2phy0>; //超过rxda测试
+	snps,dis_enblslpm_quirk;
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+	snps,dis-u2-freeclk-exists-quirk;
+	snps,dis-del-phy-power-chg-quirk;
+	snps,dis-tx-ipgap-linecheck-quirk;
+	snps,dis_rxdet_inp3_quirk;
+	snps,xhci-trb-ent-quirk;
+	snps,parkmode-disable-ss-quirk;
+	quirk-skip-phy-init;
+};
+
+&usb_host1_ehci {
+	status = "disabled";
+};
+
+&usb_host1_ohci {
+	status = "disabled";
+};
+
+&usb_host1_xhci {
+	dr_mode = "host";//自动检测
+	snps,dis_enblslpm_quirk;
+	snps,dis-u2-freeclk-exists-quirk;
+	snps,dis-del-phy-power-chg-quirk;
+	snps,dis-tx-ipgap-linecheck-quirk;
+	snps,dis_rxdet_inp3_quirk;
+	snps,xhci-trb-ent-quirk;
+	snps,parkmode-disable-ss-quirk;
+	status = "disabled";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "disabled";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "disabled";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "disabled";
+};
+
+&sata2 {
+	status = "disabled";
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vcc_3v3>;
+	vccio3-supply = <&vcc_3v3>;
+	vccio4-supply = <&vcc_3v3>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "disabled";
+};
+
+&pwm3 {
+	status = "disabled";
+};
+
+&power {
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&vpu {
+	status = "okay";
+};
+
+&rga {
+	status = "okay";
+};
+
+&vepu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+//sdhci@fe310000
+&sdhci {
+	max-frequency = <200000000>;
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	supports-emmc;
+	non-removable;
+	mmc-hs200-1_8v;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	status = "okay";
+};
+
+//dwmmc@fe000000
+&sdmmc2 {
+	max-frequency = <150000000>;
+	fifo-depth = <256>;
+	no-sd;
+	no-mmc;
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	sd-uhs-sdr104;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
+	status = "disabled";
+};
+
+//dwmmc@fe2b0000
+&sdmmc0 {
+	max-frequency = <150000000>;
+	fifo-depth = <256>;
+	no-sdio;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	status = "disabled";
+};
+
+&combphy0 {
+	status = "okay";
+};
+
+&csi_dphy {
+	status = "okay";
+};
+
+/* Add #address-cells, #size-cells */
+&sfc {
+	status = "okay";
+	#address-cells = <1>;  /* One cell for the chip select */
+	#size-cells = <0>;     /* No cell for the size */
+
+	flash@0 {
+		compatible = "spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&rng {
+	status = "okay";
+};
+
+//i2c@fe5a0000
+&i2c1 {
+	status = "disabled";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "disabled";
+};
+
+&wdt {
+	status = "okay";
+};
+
+&uart8 {
+	status = "disabled";
+};
+
+&pwm4 {
+	status = "disabled";
+};
+
+&pwm5 {
+	status = "disabled";
+};
+
+&pwm7 {
+	status = "disabled";
+};
+
+&pwm8 {
+	status = "disabled";
+};
+
+&pwm9 {
+	status = "disabled";
+};
+
+//fe720000
+&saradc {
+	status = "okay";
+	vref-supply = <&vcc1v8_adc>;
+};


================================================
FILE: kernel-patch/beta/deprecated-patches/6.18.y-309-dts-add-skip-version-detect-for-oes-plus.patch
================================================
From 26a1bdca091fe1987bf892ac2f68001cff2c2ed1 Mon Sep 17 00:00:00 2001
From: ophub <68696949+ophub@users.noreply.github.com>
Date: Sat, 31 Jan 2026 21:53:42 +0800
Subject: [PATCH] oes-plus: Skip detection for some boards marked with
 skip-version-detect in the device tree

---
 .../ethernet/stmicro/stmmac/dwmac-meson8b.c   | 25 +++++++++++++++++--
 drivers/pci/controller/dwc/pcie-designware.c  |  9 +++++++
 2 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index a50782994..3f0874dda 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -29,6 +29,8 @@
 #define PRG_ETH0_EXT_RGMII_MODE		1
 #define PRG_ETH0_EXT_RMII_MODE		4
 
+#define PRG_ETH0_INVERT_RXCLK		BIT(3)
+
 /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
 #define PRG_ETH0_CLK_M250_SEL_MASK	GENMASK(4, 4)
 
@@ -94,6 +96,8 @@ struct meson8b_dwmac {
 	struct clk			*rgmii_tx_clk;
 	u32				tx_delay_ns;
 	u32				rx_delay_ps;
+	bool				keep_rx_delay;
+	bool				invert_rxclk;
 	struct clk			*timing_adj_clk;
 };
 
@@ -303,7 +307,8 @@ static int meson8b_init_rgmii_delays(struct meson8b_dwmac *dwmac)
 		break;
 	case PHY_INTERFACE_MODE_RGMII_RXID:
 		delay_config = tx_dly_config;
-		cfg_rxclk_dly = 0;
+		if(!dwmac->keep_rx_delay)
+			cfg_rxclk_dly = 0;
 		break;
 	case PHY_INTERFACE_MODE_RGMII_TXID:
 		delay_config = rx_adj_config;
@@ -311,7 +316,8 @@ static int meson8b_init_rgmii_delays(struct meson8b_dwmac *dwmac)
 	case PHY_INTERFACE_MODE_RGMII_ID:
 	case PHY_INTERFACE_MODE_RMII:
 		delay_config = 0;
-		cfg_rxclk_dly = 0;
+		if(!dwmac->keep_rx_delay)
+			cfg_rxclk_dly = 0;
 		break;
 	default:
 		dev_err(dwmac->dev, "unsupported phy-mode %s\n",
@@ -341,6 +347,11 @@ static int meson8b_init_rgmii_delays(struct meson8b_dwmac *dwmac)
 				PRG_ETH0_ADJ_DELAY | PRG_ETH0_ADJ_SKEW,
 				delay_config);
 
+	if(dwmac->invert_rxclk)
+		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+					PRG_ETH0_INVERT_RXCLK,
+					PRG_ETH0_INVERT_RXCLK);
+
 	meson8b_dwmac_mask_bits(dwmac, PRG_ETH1, PRG_ETH1_CFG_RXCLK_DLY,
 				cfg_rxclk_dly);
 
@@ -448,6 +459,16 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
 		}
 	}
 
+	/*
+	* Some boards need to enable the internal RX delay of the PHY
+	* while simultaneously enabling the internal RX delay of the MAC,
+	* as implemented in the Amlogic BSP kernel.
+	*/
+	dwmac->keep_rx_delay = of_property_read_bool(pdev->dev.of_node,
+		"amlogic,keep-rx-internal-delay");
+
+	dwmac->invert_rxclk = of_property_read_bool(pdev->dev.of_node, "amlogic,invert-rxclk");
+
 	dwmac->timing_adj_clk = devm_clk_get_optional(dwmac->dev,
 						      "timing-adjustment");
 	if (IS_ERR(dwmac->timing_adj_clk))
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 06eca858e..c4aa47ed7 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -203,6 +203,15 @@ void dw_pcie_version_detect(struct dw_pcie *pci)
 {
 	u32 ver;
 
+    /*
+	* Some boards with Amlogic A311D SoC's AHCI controller breaks
+	* if the version register is read.
+	* Skip detection for some boards marked with skip-version-detect
+	* in the device tree.
+	*/
+	if (of_property_read_bool(pci->dev->of_node, "skip-version-detect"))
+		return;
+
 	/* The content of the CSR is zero on DWC PCIe older than v4.70a */
 	ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_NUMBER);
 	if (!ver)


================================================
FILE: kernel-patch/beta/deprecated-patches/6.6.y-101-arm64-add-text_offset.patch
================================================
From f020c3333bea5fe6ab69504ed8f613c190ef9de3 Mon Sep 17 00:00:00 2001
From: codesnas <67037511+codesnas@users.noreply.github.com>
Date: Thu, 1 Feb 2024 22:26:10 +0800
Subject: [PATCH] Add text_offset

---
 arch/arm64/Makefile                       |  5 +++++
 arch/arm64/include/asm/boot.h             |  3 ++-
 arch/arm64/include/asm/kernel-pgtable.h   |  2 +-
 arch/arm64/include/asm/memory.h           |  2 +-
 arch/arm64/kernel/Makefile                |  3 ++-
 arch/arm64/kernel/head.S                  | 22 +++++++++++++++++-----
 arch/arm64/kernel/image.h                 |  1 +
 arch/arm64/kernel/setup.c                 |  7 -------
 arch/arm64/kernel/vmlinux.lds.S           |  4 ++--
 arch/arm64/mm/mmu.c                       |  3 ---
 drivers/firmware/efi/libstub/Makefile     |  2 ++
 drivers/firmware/efi/libstub/arm64-stub.c |  4 +++-
 drivers/firmware/efi/libstub/kaslr.c      |  4 ++--
 13 files changed, 38 insertions(+), 24 deletions(-)

diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index 26b8c7630..9c93bdca9 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -11,6 +11,7 @@
 # Copyright (C) 1995-2001 by Russell King
 
 LDFLAGS_vmlinux	:=--no-undefined -X
+CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET)
 
 ifeq ($(CONFIG_RELOCATABLE), y)
 # Pass --no-apply-dynamic-relocs to restore pre-binutils-2.27 behaviour
@@ -134,6 +135,10 @@ else ifeq ($(CONFIG_DYNAMIC_FTRACE_WITH_ARGS),y)
   CC_FLAGS_FTRACE := -fpatchable-function-entry=2
 endif
 
+# The byte offset of the kernel image in RAM from the start of RAM.
+TEXT_OFFSET := 0x01080000
+export TEXT_OFFSET
+
 ifeq ($(CONFIG_KASAN_SW_TAGS), y)
 KASAN_SHADOW_SCALE_SHIFT := 4
 else ifeq ($(CONFIG_KASAN_GENERIC), y)
diff --git a/arch/arm64/include/asm/boot.h b/arch/arm64/include/asm/boot.h
index 3e7943fd1..c7f67da13 100644
--- a/arch/arm64/include/asm/boot.h
+++ b/arch/arm64/include/asm/boot.h
@@ -13,7 +13,8 @@
 #define MAX_FDT_SIZE		SZ_2M
 
 /*
- * arm64 requires the kernel image to placed at a 2 MB aligned base address
+ * arm64 requires the kernel image to placed
+ * TEXT_OFFSET bytes beyond a 2 MB aligned base
  */
 #define MIN_KIMG_ALIGN		SZ_2M
 
diff --git a/arch/arm64/include/asm/kernel-pgtable.h b/arch/arm64/include/asm/kernel-pgtable.h
index 85d26143f..d0333cd63 100644
--- a/arch/arm64/include/asm/kernel-pgtable.h
+++ b/arch/arm64/include/asm/kernel-pgtable.h
@@ -83,7 +83,7 @@
 			+ EARLY_PGDS((vstart), (vend), add) 	/* each PGDIR needs a next level page table */	\
 			+ EARLY_PUDS((vstart), (vend), add)	/* each PUD needs a next level page table */	\
 			+ EARLY_PMDS((vstart), (vend), add))	/* each PMD needs a next level page table */
-#define INIT_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR, _end, EARLY_KASLR))
+#define INIT_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR + TEXT_OFFSET, _end, EARLY_KASLR))
 
 /* the initial ID map may need two extra pages if it needs to be extended */
 #if VA_BITS < 48
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index fde4186cc..479c5c336 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -193,7 +193,7 @@ extern s64			memstart_addr;
 /* PHYS_OFFSET - the physical address of the start of memory. */
 #define PHYS_OFFSET		({ VM_BUG_ON(memstart_addr & 1); memstart_addr; })
 
-/* the virtual base of the kernel image */
+/* the virtual base of the kernel image (minus TEXT_OFFSET) */
 extern u64			kimage_vaddr;
 
 /* the offset between the kernel virtual and physical mappings */
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index d95b3d6b4..449e109cf 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -2,7 +2,8 @@
 #
 # Makefile for the linux kernel.
 #
-
+CPPFLAGS_vmlinux.lds	:= -DTEXT_OFFSET=$(TEXT_OFFSET)
+AFLAGS_head.o		:= -DTEXT_OFFSET=$(TEXT_OFFSET)
 CFLAGS_armv8_deprecated.o := -I$(src)
 
 CFLAGS_REMOVE_ftrace.o = $(CC_FLAGS_FTRACE)
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 7b236994f..28020aee8 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -37,6 +37,8 @@
 
 #include "efi-header.S"
 
+#define __PHYS_OFFSET  (KERNEL_START - TEXT_OFFSET)
+
 #if (PAGE_OFFSET & 0x1fffff) != 0
 #error PAGE_OFFSET must be at least 2MB aligned
 #endif
@@ -49,6 +51,9 @@
  *   MMU = off, D-cache = off, I-cache = on or off,
  *   x0 = physical address to the FDT blob.
  *
+ * This code is mostly position independent so you call this at
+ * __pa(PAGE_OFFSET + TEXT_OFFSET).
+ *
  * Note that the callee-saved registers are used for storing variables
  * that are useful before the MMU is enabled. The allocations are described
  * in the entry routines.
@@ -59,7 +64,7 @@
 	 */
 	efi_signature_nop			// special NOP to identity as PE/COFF executable
 	b	primary_entry			// branch to kernel start, magic
-	.quad	0				// Image load offset from start of RAM, little-endian
+	le64sym	_kernel_offset_le		// Image load offset from start of RAM, little-endian
 	le64sym	_kernel_size_le			// Effective size of kernel image, little-endian
 	le64sym	_kernel_flags_le		// Informative flags, little-endian
 	.quad	0				// reserved
@@ -422,7 +427,7 @@ SYM_FUNC_END(create_idmap)
 
 SYM_FUNC_START_LOCAL(create_kernel_mapping)
 	adrp	x0, init_pg_dir
-	mov_q	x5, KIMAGE_VADDR		// compile time __va(_text)
+	mov_q	x5, KIMAGE_VADDR + TEXT_OFFSET		// compile time __va(_text)
 #ifdef CONFIG_RELOCATABLE
 	add	x5, x5, x23			// add KASLR displacement
 #endif
@@ -467,7 +472,7 @@ SYM_FUNC_END(create_kernel_mapping)
 /*
  * The following fragment of code is executed with the MMU enabled.
  *
- *   x0 = __pa(KERNEL_START)
+ *   x0 = __PHYS_OFFSET
  */
 SYM_FUNC_START_LOCAL(__primary_switched)
 	adr_l	x4, init_task
@@ -524,6 +529,13 @@ SYM_FUNC_START_LOCAL(__primary_switched)
 	ASM_BUG()
 SYM_FUNC_END(__primary_switched)
 
+        .pushsection ".rodata", "a"
+ SYM_DATA_START(kimage_vaddr)
+        .quad           _text - TEXT_OFFSET
+ SYM_DATA_END(kimage_vaddr)
+ EXPORT_SYMBOL(kimage_vaddr)
+        .popsection
+
 /*
  * end early head section, begin head code that is also used for
  * hotplug and needs to have the same protections as the text region
@@ -875,7 +887,7 @@ SYM_FUNC_START_LOCAL(__primary_switch)
 	adrp	x2, init_idmap_pg_dir
 	bl	__enable_mmu
 #ifdef CONFIG_RELOCATABLE
-	adrp	x23, KERNEL_START
+	adrp	x23, __PHYS_OFFSET
 	and	x23, x23, MIN_KIMG_ALIGN - 1
 #ifdef CONFIG_RANDOMIZE_BASE
 	mov	x0, x22
@@ -897,6 +909,6 @@ SYM_FUNC_START_LOCAL(__primary_switch)
 	bl	__relocate_kernel
 #endif
 	ldr	x8, =__primary_switched
-	adrp	x0, KERNEL_START		// __pa(KERNEL_START)
+	adrp	x0, __PHYS_OFFSET
 	br	x8
 SYM_FUNC_END(__primary_switch)
diff --git a/arch/arm64/kernel/image.h b/arch/arm64/kernel/image.h
index 7bc3ba897..c7d38c660 100644
--- a/arch/arm64/kernel/image.h
+++ b/arch/arm64/kernel/image.h
@@ -62,6 +62,7 @@
  */
 #define HEAD_SYMBOLS						\
 	DEFINE_IMAGE_LE64(_kernel_size_le, _end - _text);	\
+	DEFINE_IMAGE_LE64(_kernel_offset_le, TEXT_OFFSET);	\
 	DEFINE_IMAGE_LE64(_kernel_flags_le, __HEAD_FLAGS);
 
 #endif /* __ARM64_KERNEL_IMAGE_H */
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 417a8a86b..a0eb10a25 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -335,13 +335,6 @@ void __init __no_sanitize_address setup_arch(char **cmdline_p)
 	xen_early_init();
 	efi_init();
 
-	if (!efi_enabled(EFI_BOOT)) {
-		if ((u64)_text % MIN_KIMG_ALIGN)
-			pr_warn(FW_BUG "Kernel image misaligned at boot, please fix your bootloader!");
-		WARN_TAINT(mmu_enabled_at_boot, TAINT_FIRMWARE_WORKAROUND,
-			   FW_BUG "Booted with MMU enabled!");
-	}
-
 	arm64_memblock_init();
 
 	paging_init();
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 3cd7e76cc..b63529ca9 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -164,7 +164,7 @@ SECTIONS
 		*(.dynsym .dynstr .hash .gnu.hash)
 	}
 
-	. = KIMAGE_VADDR;
+	. = KIMAGE_VADDR + TEXT_OFFSET;
 
 	.head.text : {
 		_text = .;
@@ -368,7 +368,7 @@ ASSERT(__hyp_bss_start == __bss_start, "HYP and Host BSS are misaligned")
 /*
  * If padding is applied before .head.text, virt<->phys conversions will fail.
  */
-ASSERT(_text == KIMAGE_VADDR, "HEAD is misaligned")
+ASSERT(_text == (KIMAGE_VADDR + TEXT_OFFSET), "HEAD is misaligned")
 
 ASSERT(swapper_pg_dir - reserved_pg_dir == RESERVED_SWAPPER_OFFSET,
        "RESERVED_SWAPPER_OFFSET is wrong!")
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 47781bec6..49a49b375 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -52,9 +52,6 @@ u64 vabits_actual __ro_after_init = VA_BITS_MIN;
 EXPORT_SYMBOL(vabits_actual);
 #endif
 
-u64 kimage_vaddr __ro_after_init = (u64)&_text;
-EXPORT_SYMBOL(kimage_vaddr);
-
 u64 kimage_voffset __ro_after_init;
 EXPORT_SYMBOL(kimage_voffset);
 
diff --git a/drivers/firmware/efi/libstub/Makefile b/drivers/firmware/efi/libstub/Makefile
index a1157c2a7..170523e19 100644
--- a/drivers/firmware/efi/libstub/Makefile
+++ b/drivers/firmware/efi/libstub/Makefile
@@ -93,6 +93,8 @@ lib-$(CONFIG_RISCV)		+= kaslr.o riscv.o riscv-stub.o
 lib-$(CONFIG_LOONGARCH)		+= loongarch.o loongarch-stub.o
 
 CFLAGS_arm32-stub.o		:= -DTEXT_OFFSET=$(TEXT_OFFSET)
+CFLAGS_arm64-stub.o		:= -DTEXT_OFFSET=$(TEXT_OFFSET)
+CFLAGS_kaslr.o			:= -DTEXT_OFFSET=$(TEXT_OFFSET)
 
 zboot-obj-$(CONFIG_RISCV)	:= lib-clz_ctz.o lib-ashldi3.o
 lib-$(CONFIG_EFI_ZBOOT)		+= zboot.o $(zboot-obj-y)
diff --git a/drivers/firmware/efi/libstub/arm64-stub.c b/drivers/firmware/efi/libstub/arm64-stub.c
index 452b7ccd3..781680a85 100644
--- a/drivers/firmware/efi/libstub/arm64-stub.c
+++ b/drivers/firmware/efi/libstub/arm64-stub.c
@@ -22,6 +22,8 @@ efi_status_t handle_kernel_image(unsigned long *image_addr,
 				 efi_handle_t image_handle)
 {
 	efi_status_t status;
+	u64 min_kimg_align = efi_get_kimg_min_align();
+
 	unsigned long kernel_size, kernel_codesize, kernel_memsize;
 
 	if (image->image_base != _text) {
@@ -36,7 +38,7 @@ efi_status_t handle_kernel_image(unsigned long *image_addr,
 	kernel_size = _edata - _text;
 	kernel_codesize = __inittext_end - _text;
 	kernel_memsize = kernel_size + (_end - _edata);
-	*reserve_size = kernel_memsize;
+	*reserve_size = kernel_memsize + TEXT_OFFSET % min_kimg_align;
 	*image_addr = (unsigned long)_text;
 
 	status = efi_kaslr_relocate_kernel(image_addr,
diff --git a/drivers/firmware/efi/libstub/kaslr.c b/drivers/firmware/efi/libstub/kaslr.c
index 62d63f7a2..6e359714a 100644
--- a/drivers/firmware/efi/libstub/kaslr.c
+++ b/drivers/firmware/efi/libstub/kaslr.c
@@ -129,7 +129,7 @@ efi_status_t efi_kaslr_relocate_kernel(unsigned long *image_addr,
 	if (status != EFI_SUCCESS) {
 		if (!check_image_region(*image_addr, kernel_memsize)) {
 			efi_err("FIRMWARE BUG: Image BSS overlaps adjacent EFI memory region\n");
-		} else if (IS_ALIGNED(*image_addr, min_kimg_align) &&
+		} else if (IS_ALIGNED(*image_addr - TEXT_OFFSET, min_kimg_align) &&
 			   (unsigned long)_end < EFI_ALLOC_LIMIT) {
 			/*
 			 * Just execute from wherever we were loaded by the
@@ -151,7 +151,7 @@ efi_status_t efi_kaslr_relocate_kernel(unsigned long *image_addr,
 	}
 
 	memcpy((void *)*reserve_addr, (void *)*image_addr, kernel_size);
-	*image_addr = *reserve_addr;
+	*image_addr = *reserve_addr + TEXT_OFFSET % min_kimg_align;;
 	efi_icache_sync(*image_addr, *image_addr + kernel_codesize);
 	efi_remap_image(*image_addr, *reserve_size, kernel_codesize);
 


================================================
FILE: kernel-patch/beta/linux-5.15.y/201-drm-meson-venc-add-support-for-ws7.9.patch
================================================
From 50f2d2574a541855ed5bf14dc9835de424fa3b60 Mon Sep 17 00:00:00 2001
From: xxx <68696949+xxx@users.noreply.github.com>
Date: Wed, 21 May 2025 12:08:39 +0800
Subject: [PATCH] hack: drm/meson: venc: add support for WS7.9

---
 drivers/gpu/drm/meson/meson_venc.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
index 559ab3b5e2..40d6a908b3 100644
--- a/drivers/gpu/drm/meson/meson_venc.c
+++ b/drivers/gpu/drm/meson/meson_venc.c
@@ -866,11 +866,13 @@ meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode)
 			    DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))
 		return MODE_BAD;
 
-	/* support higher resolution than 1920x1080 */
-	if (mode->hdisplay < 640 || mode->hdisplay > 2560)
+	/* support 384x1280 and 1280x384 for the waveshare 7.9"
+	 * as well, support 2560x1600 for 2K resolution
+	 */
+	if (mode->hdisplay < 384 || mode->hdisplay > 2560)
 		return MODE_BAD_HVALUE;
 
-	if (mode->vdisplay < 480 || mode->vdisplay > 1600)
+	if (mode->vdisplay < 384 || mode->vdisplay > 1600)
 		return MODE_BAD_VVALUE;
 
 	return MODE_OK;


================================================
FILE: kernel-patch/beta/linux-5.15.y/301-dts-add-rockchip-rk3399-cdhx-rb30-dtb.patch
================================================
From ca1d980bb838887e89180b609ba33bdddf2f6533 Mon Sep 17 00:00:00 2001
From: xxx <68696949+xxx@users.noreply.github.com>
Date: Wed, 21 May 2025 12:09:17 +0800
Subject: [PATCH] arch: arm64: dts: add cdhx-rb30(rk3399)

---
 arch/arm64/boot/dts/rockchip/Makefile         |   1 +
 .../boot/dts/rockchip/rk3399-cdhx-rb30.dts    | 750 ++++++++++++++++++
 2 files changed, 751 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-cdhx-rb30.dts

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 4a5a18fb56..a37d619f7e 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-cdhx-rb30.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-cdhx-rb30.dts b/arch/arm64/boot/dts/rockchip/rk3399-cdhx-rb30.dts
new file mode 100644
index 0000000000..8a670d47d9
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-cdhx-rb30.dts
@@ -0,0 +1,750 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "dt-bindings/input/input.h"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+// #include "rk3399-t-opp.dtsi"
+
+/ {
+	model = "CDHX RB30";
+	compatible = "cdhx,rb30", "rockchip,rk3399";
+
+	aliases {
+		ethernet0 = &gmac;
+		mmc0 = &sdio0;
+		mmc1 = &sdmmc;
+		mmc2 = &sdhci;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	board_info: board-info {
+		compatible = "board-info";
+		pmic-reset = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwrbtn>;
+
+		key-power {
+			debounce-interval = <100>;
+			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; // bsp
+			label = "GPIO Key Power";
+			linux,code = <KEY_POWER>;
+			wakeup-source;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; // bsp
+	};
+
+	vcc12v_dcin: vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc_lcd: vcc-lcd {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; // bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_lcd_en>;
+		regulator-name = "vcc_lcd";
+		regulator-always-on;
+	};
+
+	vccadc_ref: vccadc-ref {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_phy";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_sd: vcc-sd {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sd";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; // bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host";
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	usb2_hub: usb2-hub-en {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb2_hub_en>; // bsp
+		regulator-name = "usb2_hub";
+		regulator-always-on;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		pwm-supply = <&vcc5v0_sys>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1700000>;
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_phy>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; // bsp
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&hdmi {
+	status = "okay";
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc1v8_dvp: LDO_REG1 {
+				regulator-name = "vcc1v8_dvp";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v0_tp: LDO_REG2 {
+				regulator-name = "vcc3v0_tp";
+				// regulator-always-on;
+				// regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vccio_sd: LDO_REG4 {
+				regulator-name = "vccio_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG7 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel1_pin>; // bsp
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel2_pin>; // bsp
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c1 {
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+// HDMI
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+// ALC5651
+&i2c4 {
+	i2c-scl-rising-time-ns = <600>;
+	i2c-scl-falling-time-ns = <20>;
+	status = "okay";
+};
+
+// HDMI sound
+&i2s2 {
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+	bt656-supply = <&vcc_3v0>;
+	audio-supply = <&vcca1v8_codec>;
+	sdmmc-supply = <&vccio_sd>;
+	gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmu1830-supply = <&vcc_3v0>;
+};
+
+&pinctrl {
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+
+		bt_host_wake_l: bt-host-wake-l {
+			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+
+		bt_wake_l: bt-wake-l {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	wifi {
+		wifi_host_wake_l: wifi-host-wake-l {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	buttons {
+		pwrbtn: pwrbtn {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; // common
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+
+		vsel1_pin: vsel1-pin {
+			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+
+		vsel2_pin: vsel2-pin {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; // bsp
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; // common
+		};
+	};
+
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		usb2_hub_en: usb2-hub-en {
+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+	};
+
+	headphone {
+		spk_ctl: spk-ctl {
+			rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; // bsp: spk-con-gpio
+		};
+		spk_pwr: spk-pwr {
+			rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+	};
+
+	bl_ctrl {
+		bl_en: bl-en {
+			rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; // bsp
+		};
+		vcc_lcd_en: vcc-lcd-en {
+			rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; // bsp
+		};
+	};
+
+	gmac {
+		rgmii_sleep_pins: rgmii-sleep-pins {
+			rockchip,pins =<3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; // bsp
+		};
+	};
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vccadc_ref>;
+};
+
+&sdio0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	bus-width = <4>;
+	clock-frequency = <50000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+	sd-uhs-sdr104;
+
+	brcmf: wifi@1 {
+		compatible = "brcm,bcm43455-fmac";
+		reg = <1>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+		interrupt-names = "host-wake";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_l>; // bsp
+	};
+};
+
+&sdmmc {
+	clock-frequency = <150000000>;
+	clock-freq-min-max = <100000 150000000>;
+	supports-sd;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	num-slots = <1>;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&rk808 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; // bsp
+		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; // bsp
+		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; // bsp
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc_1v8>;
+	};
+};
+
+// Debug TTL
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&iep_mmu {
+	status = "okay";
+};


================================================
FILE: kernel-patch/beta/linux-6.1.y/201-fix-i2ca-and-i2cb-miossing-pins.patch
================================================
From 59d66d6c9465f4fee9c8fc6acc4235be9342baff Mon Sep 17 00:00:00 2001
From: xxx <68696949+xxx@users.noreply.github.com>
Date: Wed, 21 May 2025 12:15:46 +0800
Subject: [PATCH] fix i2cA and i2cB miossing pins

---
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 256c46771d..2a8d05373e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -333,6 +333,8 @@
 
 &i2c_A {
 	clocks = <&clkc CLKID_I2C>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c_a_pins>;
 };
 
 &i2c_AO {
@@ -341,6 +343,8 @@
 
 &i2c_B {
 	clocks = <&clkc CLKID_I2C>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c_b_pins>;
 };
 
 &i2c_C {


================================================
FILE: kernel-patch/beta/linux-6.6.y/201-fix-i2ca-and-i2cb-miossing-pins.patch
================================================
From 9b2af930c2377459c3e67aa45c928acefb89d227 Mon Sep 17 00:00:00 2001
From: xxx <68696949+xxx@users.noreply.github.com>
Date: Wed, 21 May 2025 12:19:23 +0800
Subject: [PATCH] fix i2cA and i2cB miossing pins

---
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index ed00e67e6..460a21a4f 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -339,6 +339,8 @@
 
 &i2c_A {
 	clocks = <&clkc CLKID_I2C>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c_a_pins>;
 };
 
 &i2c_AO {
@@ -347,6 +349,8 @@
 
 &i2c_B {
 	clocks = <&clkc CLKID_I2C>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c_b_pins>;
 };
 
 &i2c_C {