[ { "path": ".gitignore", "content": "build_dir/\n\ncpufp\n" }, { "path": "LICENSE", "content": " GNU GENERAL PUBLIC LICENSE\n Version 3, 29 June 2007\n\n Copyright (C) 2007 Free Software Foundation, Inc. \n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n Preamble\n\n The GNU General Public License is a free, copyleft license for\nsoftware and other kinds of works.\n\n The licenses for most software and other practical works are designed\nto take away your freedom to share and change the works. By contrast,\nthe GNU General Public License is intended to guarantee your freedom to\nshare and change all versions of a program--to make sure it remains free\nsoftware for all its users. We, the Free Software Foundation, use the\nGNU General Public License for most of our software; it applies also to\nany other work released this way by its authors. You can apply it to\nyour programs, too.\n\n When we speak of free software, we are referring to freedom, not\nprice. Our General Public Licenses are designed to make sure that you\nhave the freedom to distribute copies of free software (and charge for\nthem if you wish), that you receive source code or can get it if you\nwant it, that you can change the software or use pieces of it in new\nfree programs, and that you know you can do these things.\n\n To protect your rights, we need to prevent others from denying you\nthese rights or asking you to surrender the rights. Therefore, you have\ncertain responsibilities if you distribute copies of the software, or if\nyou modify it: responsibilities to respect the freedom of others.\n\n For example, if you distribute copies of such a program, whether\ngratis or for a fee, you must pass on to the recipients the same\nfreedoms that you received. You must make sure that they, too, receive\nor can get the source code. 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Therefore, we\nhave designed this version of the GPL to prohibit the practice for those\nproducts. If such problems arise substantially in other domains, we\nstand ready to extend this provision to those domains in future versions\nof the GPL, as needed to protect the freedom of users.\n\n Finally, every program is threatened constantly by software patents.\nStates should not allow patents to restrict development and use of\nsoftware on general-purpose computers, but in those that do, we wish to\navoid the special danger that patents applied to a free program could\nmake it effectively proprietary. To prevent this, the GPL assures that\npatents cannot be used to render the program non-free.\n\n The precise terms and conditions for copying, distribution and\nmodification follow.\n\n TERMS AND CONDITIONS\n\n 0. Definitions.\n\n \"This License\" refers to version 3 of the GNU General Public License.\n\n \"Copyright\" also means copyright-like laws that apply to other kinds of\nworks, such as semiconductor masks.\n\n \"The Program\" refers to any copyrightable work licensed under this\nLicense. Each licensee is addressed as \"you\". \"Licensees\" and\n\"recipients\" may be individuals or organizations.\n\n To \"modify\" a work means to copy from or adapt all or part of the work\nin a fashion requiring copyright permission, other than the making of an\nexact copy. The resulting work is called a \"modified version\" of the\nearlier work or a work \"based on\" the earlier work.\n\n A \"covered work\" means either the unmodified Program or a work based\non the Program.\n\n To \"propagate\" a work means to do anything with it that, without\npermission, would make you directly or secondarily liable for\ninfringement under applicable copyright law, except executing it on a\ncomputer or modifying a private copy. Propagation includes copying,\ndistribution (with or without modification), making available to the\npublic, and in some countries other activities as well.\n\n To \"convey\" a work means any kind of propagation that enables other\nparties to make or receive copies. Mere interaction with a user through\na computer network, with no transfer of a copy, is not conveying.\n\n An interactive user interface displays \"Appropriate Legal Notices\"\nto the extent that it includes a convenient and prominently visible\nfeature that (1) displays an appropriate copyright notice, and (2)\ntells the user that there is no warranty for the work (except to the\nextent that warranties are provided), that licensees may convey the\nwork under this License, and how to view a copy of this License. If\nthe interface presents a list of user commands or options, such as a\nmenu, a prominent item in the list meets this criterion.\n\n 1. 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A\n\"Major Component\", in this context, means a major essential component\n(kernel, window system, and so on) of the specific operating system\n(if any) on which the executable work runs, or a compiler used to\nproduce the work, or an object code interpreter used to run it.\n\n The \"Corresponding Source\" for a work in object code form means all\nthe source code needed to generate, install, and (for an executable\nwork) run the object code and to modify the work, including scripts to\ncontrol those activities. However, it does not include the work's\nSystem Libraries, or general-purpose tools or generally available free\nprograms which are used unmodified in performing those activities but\nwhich are not part of the work. For example, Corresponding Source\nincludes interface definition files associated with source files for\nthe work, and the source code for shared libraries and dynamically\nlinked subprograms that the work is specifically designed to require,\nsuch as by intimate data communication or control flow between those\nsubprograms and other parts of the work.\n\n The Corresponding Source need not include anything that users\ncan regenerate automatically from other parts of the Corresponding\nSource.\n\n The Corresponding Source for a work in source code form is that\nsame work.\n\n 2. Basic Permissions.\n\n All rights granted under this License are granted for the term of\ncopyright on the Program, and are irrevocable provided the stated\nconditions are met. This License explicitly affirms your unlimited\npermission to run the unmodified Program. The output from running a\ncovered work is covered by this License only if the output, given its\ncontent, constitutes a covered work. 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This License gives no\n permission to license the work in any other way, but it does not\n invalidate such permission if you have separately received it.\n\n d) If the work has interactive user interfaces, each must display\n Appropriate Legal Notices; however, if the Program has interactive\n interfaces that do not display Appropriate Legal Notices, your\n work need not make them do so.\n\n A compilation of a covered work with other separate and independent\nworks, which are not by their nature extensions of the covered work,\nand which are not combined with it such as to form a larger program,\nin or on a volume of a storage or distribution medium, is called an\n\"aggregate\" if the compilation and its resulting copyright are not\nused to limit the access or legal rights of the compilation's users\nbeyond what the individual works permit. Inclusion of a covered work\nin an aggregate does not cause this License to apply to the other\nparts of the aggregate.\n\n 6. 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This\n alternative is allowed only occasionally and noncommercially, and\n only if you received the object code with such an offer, in accord\n with subsection 6b.\n\n d) Convey the object code by offering access from a designated\n place (gratis or for a charge), and offer equivalent access to the\n Corresponding Source in the same way through the same place at no\n further charge. You need not require recipients to copy the\n Corresponding Source along with the object code. If the place to\n copy the object code is a network server, the Corresponding Source\n may be on a different server (operated by you or a third party)\n that supports equivalent copying facilities, provided you maintain\n clear directions next to the object code saying where to find the\n Corresponding Source. Regardless of what server hosts the\n Corresponding Source, you remain obligated to ensure that it is\n available for as long as needed to satisfy these requirements.\n\n e) Convey the object code using peer-to-peer transmission, provided\n you inform other peers where the object code and Corresponding\n Source of the work are being offered to the general public at no\n charge under subsection 6d.\n\n A separable portion of the object code, whose source code is excluded\nfrom the Corresponding Source as a System Library, need not be\nincluded in conveying the object code work.\n\n A \"User Product\" is either (1) a \"consumer product\", which means any\ntangible personal property which is normally used for personal, family,\nor household purposes, or (2) anything designed or sold for incorporation\ninto a dwelling. In determining whether a product is a consumer product,\ndoubtful cases shall be resolved in favor of coverage. For a particular\nproduct received by a particular user, \"normally used\" refers to a\ntypical or common use of that class of product, regardless of the status\nof the particular user or of the way in which the particular user\nactually uses, or expects or is expected to use, the product. A product\nis a consumer product regardless of whether the product has substantial\ncommercial, industrial or non-consumer uses, unless such uses represent\nthe only significant mode of use of the product.\n\n \"Installation Information\" for a User Product means any methods,\nprocedures, authorization keys, or other information required to install\nand execute modified versions of a covered work in that User Product from\na modified version of its Corresponding Source. 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But this requirement does not apply\nif neither you nor any third party retains the ability to install\nmodified object code on the User Product (for example, the work has\nbeen installed in ROM).\n\n The requirement to provide Installation Information does not include a\nrequirement to continue to provide support service, warranty, or updates\nfor a work that has been modified or installed by the recipient, or for\nthe User Product in which it has been modified or installed. Access to a\nnetwork may be denied when the modification itself materially and\nadversely affects the operation of the network or violates the rules and\nprotocols for communication across the network.\n\n Corresponding Source conveyed, and Installation Information provided,\nin accord with this section must be in a format that is publicly\ndocumented (and with an implementation available to the public in\nsource code form), and must require no special password or key for\nunpacking, reading or copying.\n\n 7. Additional Terms.\n\n \"Additional permissions\" are terms that supplement the terms of this\nLicense by making exceptions from one or more of its conditions.\nAdditional permissions that are applicable to the entire Program shall\nbe treated as though they were included in this License, to the extent\nthat they are valid under applicable law. If additional permissions\napply only to part of the Program, that part may be used separately\nunder those permissions, but the entire Program remains governed by\nthis License without regard to the additional permissions.\n\n When you convey a copy of a covered work, you may at your option\nremove any additional permissions from that copy, or from any part of\nit. (Additional permissions may be written to require their own\nremoval in certain cases when you modify the work.) You may place\nadditional permissions on material, added by you to a covered work,\nfor which you have or can give appropriate copyright permission.\n\n Notwithstanding any other provision of this License, for material you\nadd to a covered work, you may (if authorized by the copyright holders of\nthat material) supplement the terms of this License with terms:\n\n a) Disclaiming warranty or limiting liability differently from the\n terms of sections 15 and 16 of this License; or\n\n b) Requiring preservation of specified reasonable legal notices or\n author attributions in that material or in the Appropriate Legal\n Notices displayed by works containing it; or\n\n c) Prohibiting misrepresentation of the origin of that material, or\n requiring that modified versions of such material be marked in\n reasonable ways as different from the original version; or\n\n d) Limiting the use for publicity purposes of names of licensors or\n authors of the material; or\n\n e) Declining to grant rights under trademark law for use of some\n trade names, trademarks, or service marks; or\n\n f) Requiring indemnification of licensors and authors of that\n material by anyone who conveys the material (or modified versions of\n it) with contractual assumptions of liability to the recipient, for\n any liability that these contractual assumptions directly impose on\n those licensors and authors.\n\n All other non-permissive additional terms are considered \"further\nrestrictions\" within the meaning of section 10. If the Program as you\nreceived it, or any part of it, contains a notice stating that it is\ngoverned by this License along with a term that is a further\nrestriction, you may remove that term. If a license document contains\na further restriction but permits relicensing or conveying under this\nLicense, you may add to a covered work material governed by the terms\nof that license document, provided that the further restriction does\nnot survive such relicensing or conveying.\n\n If you add terms to a covered work in accord with this section, you\nmust place, in the relevant source files, a statement of the\nadditional terms that apply to those files, or a notice indicating\nwhere to find the applicable terms.\n\n Additional terms, permissive or non-permissive, may be stated in the\nform of a separately written license, or stated as exceptions;\nthe above requirements apply either way.\n\n 8. Termination.\n\n You may not propagate or modify a covered work except as expressly\nprovided under this License. Any attempt otherwise to propagate or\nmodify it is void, and will automatically terminate your rights under\nthis License (including any patent licenses granted under the third\nparagraph of section 11).\n\n However, if you cease all violation of this License, then your\nlicense from a particular copyright holder is reinstated (a)\nprovisionally, unless and until the copyright holder explicitly and\nfinally terminates your license, and (b) permanently, if the copyright\nholder fails to notify you of the violation by some reasonable means\nprior to 60 days after the cessation.\n\n Moreover, your license from a particular copyright holder is\nreinstated permanently if the copyright holder notifies you of the\nviolation by some reasonable means, this is the first time you have\nreceived notice of violation of this License (for any work) from that\ncopyright holder, and you cure the violation prior to 30 days after\nyour receipt of the notice.\n\n Termination of your rights under this section does not terminate the\nlicenses of parties who have received copies or rights from you under\nthis License. If your rights have been terminated and not permanently\nreinstated, you do not qualify to receive new licenses for the same\nmaterial under section 10.\n\n 9. Acceptance Not Required for Having Copies.\n\n You are not required to accept this License in order to receive or\nrun a copy of the Program. Ancillary propagation of a covered work\noccurring solely as a consequence of using peer-to-peer transmission\nto receive a copy likewise does not require acceptance. However,\nnothing other than this License grants you permission to propagate or\nmodify any covered work. These actions infringe copyright if you do\nnot accept this License. Therefore, by modifying or propagating a\ncovered work, you indicate your acceptance of this License to do so.\n\n 10. Automatic Licensing of Downstream Recipients.\n\n Each time you convey a covered work, the recipient automatically\nreceives a license from the original licensors, to run, modify and\npropagate that work, subject to this License. You are not responsible\nfor enforcing compliance by third parties with this License.\n\n An \"entity transaction\" is a transaction transferring control of an\norganization, or substantially all assets of one, or subdividing an\norganization, or merging organizations. If propagation of a covered\nwork results from an entity transaction, each party to that\ntransaction who receives a copy of the work also receives whatever\nlicenses to the work the party's predecessor in interest had or could\ngive under the previous paragraph, plus a right to possession of the\nCorresponding Source of the work from the predecessor in interest, if\nthe predecessor has it or can get it with reasonable efforts.\n\n You may not impose any further restrictions on the exercise of the\nrights granted or affirmed under this License. For example, you may\nnot impose a license fee, royalty, or other charge for exercise of\nrights granted under this License, and you may not initiate litigation\n(including a cross-claim or counterclaim in a lawsuit) alleging that\nany patent claim is infringed by making, using, selling, offering for\nsale, or importing the Program or any portion of it.\n\n 11. Patents.\n\n A \"contributor\" is a copyright holder who authorizes use under this\nLicense of the Program or a work on which the Program is based. The\nwork thus licensed is called the contributor's \"contributor version\".\n\n A contributor's \"essential patent claims\" are all patent claims\nowned or controlled by the contributor, whether already acquired or\nhereafter acquired, that would be infringed by some manner, permitted\nby this License, of making, using, or selling its contributor version,\nbut do not include claims that would be infringed only as a\nconsequence of further modification of the contributor version. For\npurposes of this definition, \"control\" includes the right to grant\npatent sublicenses in a manner consistent with the requirements of\nthis License.\n\n Each contributor grants you a non-exclusive, worldwide, royalty-free\npatent license under the contributor's essential patent claims, to\nmake, use, sell, offer for sale, import and otherwise run, modify and\npropagate the contents of its contributor version.\n\n In the following three paragraphs, a \"patent license\" is any express\nagreement or commitment, however denominated, not to enforce a patent\n(such as an express permission to practice a patent or covenant not to\nsue for patent infringement). To \"grant\" such a patent license to a\nparty means to make such an agreement or commitment not to enforce a\npatent against the party.\n\n If you convey a covered work, knowingly relying on a patent license,\nand the Corresponding Source of the work is not available for anyone\nto copy, free of charge and under the terms of this License, through a\npublicly available network server or other readily accessible means,\nthen you must either (1) cause the Corresponding Source to be so\navailable, or (2) arrange to deprive yourself of the benefit of the\npatent license for this particular work, or (3) arrange, in a manner\nconsistent with the requirements of this License, to extend the patent\nlicense to downstream recipients. \"Knowingly relying\" means you have\nactual knowledge that, but for the patent license, your conveying the\ncovered work in a country, or your recipient's use of the covered work\nin a country, would infringe one or more identifiable patents in that\ncountry that you have reason to believe are valid.\n\n If, pursuant to or in connection with a single transaction or\narrangement, you convey, or propagate by procuring conveyance of, a\ncovered work, and grant a patent license to some of the parties\nreceiving the covered work authorizing them to use, propagate, modify\nor convey a specific copy of the covered work, then the patent license\nyou grant is automatically extended to all recipients of the covered\nwork and works based on it.\n\n A patent license is \"discriminatory\" if it does not include within\nthe scope of its coverage, prohibits the exercise of, or is\nconditioned on the non-exercise of one or more of the rights that are\nspecifically granted under this License. You may not convey a covered\nwork if you are a party to an arrangement with a third party that is\nin the business of distributing software, under which you make payment\nto the third party based on the extent of your activity of conveying\nthe work, and under which the third party grants, to any of the\nparties who would receive the covered work from you, a discriminatory\npatent license (a) in connection with copies of the covered work\nconveyed by you (or copies made from those copies), or (b) primarily\nfor and in connection with specific products or compilations that\ncontain the covered work, unless you entered into that arrangement,\nor that patent license was granted, prior to 28 March 2007.\n\n Nothing in this License shall be construed as excluding or limiting\nany implied license or other defenses to infringement that may\notherwise be available to you under applicable patent law.\n\n 12. No Surrender of Others' Freedom.\n\n If conditions are imposed on you (whether by court order, agreement or\notherwise) that contradict the conditions of this License, they do not\nexcuse you from the conditions of this License. If you cannot convey a\ncovered work so as to satisfy simultaneously your obligations under this\nLicense and any other pertinent obligations, then as a consequence you may\nnot convey it at all. For example, if you agree to terms that obligate you\nto collect a royalty for further conveying from those to whom you convey\nthe Program, the only way you could satisfy both those terms and this\nLicense would be to refrain entirely from conveying the Program.\n\n 13. Use with the GNU Affero General Public License.\n\n Notwithstanding any other provision of this License, you have\npermission to link or combine any covered work with a work licensed\nunder version 3 of the GNU Affero General Public License into a single\ncombined work, and to convey the resulting work. The terms of this\nLicense will continue to apply to the part which is the covered work,\nbut the special requirements of the GNU Affero General Public License,\nsection 13, concerning interaction through a network will apply to the\ncombination as such.\n\n 14. Revised Versions of this License.\n\n The Free Software Foundation may publish revised and/or new versions of\nthe GNU General Public License from time to time. Such new versions will\nbe similar in spirit to the present version, but may differ in detail to\naddress new problems or concerns.\n\n Each version is given a distinguishing version number. If the\nProgram specifies that a certain numbered version of the GNU General\nPublic License \"or any later version\" applies to it, you have the\noption of following the terms and conditions either of that numbered\nversion or of any later version published by the Free Software\nFoundation. If the Program does not specify a version number of the\nGNU General Public License, you may choose any version ever published\nby the Free Software Foundation.\n\n If the Program specifies that a proxy can decide which future\nversions of the GNU General Public License can be used, that proxy's\npublic statement of acceptance of a version permanently authorizes you\nto choose that version for the Program.\n\n Later license versions may give you additional or different\npermissions. However, no additional obligations are imposed on any\nauthor or copyright holder as a result of your choosing to follow a\nlater version.\n\n 15. Disclaimer of Warranty.\n\n THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY\nAPPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT\nHOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY\nOF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,\nTHE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\nPURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM\nIS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF\nALL NECESSARY SERVICING, REPAIR OR CORRECTION.\n\n 16. Limitation of Liability.\n\n IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS\nTHE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY\nGENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE\nUSE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF\nDATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD\nPARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),\nEVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF\nSUCH DAMAGES.\n\n 17. Interpretation of Sections 15 and 16.\n\n If the disclaimer of warranty and limitation of liability provided\nabove cannot be given local legal effect according to their terms,\nreviewing courts shall apply local law that most closely approximates\nan absolute waiver of all civil liability in connection with the\nProgram, unless a warranty or assumption of liability accompanies a\ncopy of the Program in return for a fee.\n\n END OF TERMS AND CONDITIONS\n\n How to Apply These Terms to Your New Programs\n\n If you develop a new program, and you want it to be of the greatest\npossible use to the public, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these terms.\n\n To do so, attach the following notices to the program. It is safest\nto attach them to the start of each source file to most effectively\nstate the exclusion of warranty; and each file should have at least\nthe \"copyright\" line and a pointer to where the full notice is found.\n\n {one line to give the program's name and a brief idea of what it does.}\n Copyright (C) {year} {name of author}\n\n This program is free software: you can redistribute it and/or modify\n it under the terms of the GNU General Public License as published by\n the Free Software Foundation, either version 3 of the License, or\n (at your option) any later version.\n\n This program is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n GNU General Public License for more details.\n\n You should have received a copy of the GNU General Public License\n along with this program. If not, see .\n\nAlso add information on how to contact you by electronic and paper mail.\n\n If the program does terminal interaction, make it output a short\nnotice like this when it starts in an interactive mode:\n\n {project} Copyright (C) {year} {fullname}\n This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\n This is free software, and you are welcome to redistribute it\n under certain conditions; type `show c' for details.\n\nThe hypothetical commands `show w' and `show c' should show the appropriate\nparts of the General Public License. Of course, your program's commands\nmight be different; for a GUI interface, you would use an \"about box\".\n\n You should also get your employer (if you work as a programmer) or school,\nif any, to sign a \"copyright disclaimer\" for the program, if necessary.\nFor more information on this, and how to apply and follow the GNU GPL, see\n.\n\n The GNU General Public License does not permit incorporating your program\ninto proprietary programs. If your program is a subroutine library, you\nmay consider it more useful to permit linking proprietary applications with\nthe library. If this is what you want to do, use the GNU Lesser General\nPublic License instead of this License. But first, please read\n.\n" }, { "path": "README.md", "content": "# cpufp\n\nThis is a cpu tool for benchmarking the peak performance of floating-points and AI ISAs.\n\nIt can automatically sense the local SIMD|DSA ISAs while compiling.\n\n## Support OS and ISA\n\n| Arch |Linux| MacOS| Windows|\n|:--------------|:---:|:----:|:------:|\n| arm64 | yes | yes | no |\n| e2k | yes | no | no |\n| loongarch64 | yes | no | no |\n| riscv64 | yes | no | no |\n| x86-64 | yes | no | no |\n\n## Support x86-64 SIMD|DSA ISA\n\n|Arch|ISA|Feature|Data Type|Description|\n| ------------ | ------------ | ------------ | ------------ | ------------ |\n|SIMD|SSE|Vector|fp32|Before Sandy Bridge|\n|SIMD|SSE2|Vector|fp64|Before Sandy Bridge|\n|SIMD|AVX|Vector|fp32/fp64|From Sandy Bridge|\n|SIMD|FMA|Vector|fp32/fp64|From Haswell/Zen|\n|SIMD|AVX512f|Vector|fp32/fp64|From Skylake X/Zen4|\n|SIMD|AVX512_VNNI|Vector|int8/int16|From IceLake|\n|SIMD|AVX_VNNI|Vector|int8/int16|From Alder Lake|\n|SIMD|AVX512_FP16|Vector|fp16|From Intel Sapphire Rapids|\n|SIMD|AVX512_BF16|Vector|bf16|From AMD Zen4|\n|SIMD|AVX_VNNI_INT8|Vector|int8|From Intel Lunar Lake|\n|SIMD|AVX_VNNI_INT16|Vector|int16|From Intel Lunar Lake|\n|DSA|AMX_INT8|Matrix|int8|From Intel Sapphire Rapids|\n|DSA|AMX_BF16|Matrix|bf16|From Intel Sapphire Rapids|\n|DSA|AMX_FP16|Matrix|fp16|From Intel Granite Rapids|\n\n## Support arm64 SIMD ISA\n\n|Arch|ISA|Feature|Data Type|Description|\n| ------------ | ------------ | ------------ | ------------ | ------------ |\n|SIMD|asimd|Vector|fp32/fp64|From Cortex-A57/A53|\n|SIMD|asimd_hp|Vector|fp16|From Cortex-A75/A55|\n|SIMD|asimd_dp|Vector|int8|From Cortex-A75/A55|\n|SIMD|bf16|Matrix|bf16|From Cortex-X2/A710/A510|\n|SIMD|i8mm|Matrix|int8|From Cortex-X2/A710/A510|\n\n## Support riscv64 VECTOR ISA\n\n|Arch|ISA|Feature|Data Type|Description|\n| ------------ | ------------ | ------------ | ------------ | ------------ |\n|SIMD|V|Vector|fp16/fp32/fp64|From RISC-V \"V\" vector extension. Version 1.0|\n|DSA|ime|Matrix|int8|From SpacemiT-X60|\n\nNOTE: ime is a SpacemiT custom vendor extension.\n\n## Support loongarch64 ISA\n|Arch|ISA|Feature|Data Type|Description|\n| ------------ | ------------ | ------------ | ------------ | ------------ |\n|SIMD|LASX|Vector|fp32/fp64|From Loongson 3A5000|\n|SIMD|LSX|Vector|fp32/fp64|From Loongson 3A5000|\n|Scalar|FP|Scalar|fp32/fp64|From Loongson 3A5000|\n\n## Support e2k ISA\n\n| Arch | ISA |Feature| Vector Width | Data Type |Description\n|:-----|:------|:-----:|:------------:|----------:|:----------\n| SIMD | v6 | Vector| 128 | fp32/fp64 | FMA\n| SIMD | v5 | Vector| 128 | fp32/fp64 | Combined operations\n|Scalar| v1-v4 | Scalar| | fp64 | Combined operations\n| SIMD | v1-v4 | Vector| 64 | fp32 | Combined operations\n\n### Combined operations\n\nE2K has support for instructions that perform two independant operations.\nIt is like FMA, but with additional rounding as these operations is independant.\n\n#### Example `fmul_addd`\n\n```\nfmul_addd src1, src2, src3, dst\n```\n\n##### Description\n\nMultiply double-precision (64-bit) floating-point values from `src1` and `src2`,\nand add the intermediate result to value from `src3`. Store the result in `dst`.\n\n##### Operation\n\n```\ndst[63:0] := src3[63:0] + src1[63:0] * src2[63:0]\n```\n\n##### Latency and Throughput\n\n| Architecture | Latency | Throughput (CPI) | ALC\n|:--------------|:-------:|:----------------:|:---:\n| elbrus-v4 | 8 | 0.16 | `012345`\n| elbrus-v1 | 8 | 0.25 | `01-34-`\n\n* ALC (Arithmetic Logic Complex/Channel) is an execution port for RISC-like instructions\n\n## How to build\n\nbuild x64 version:\n\n`./build_x64.sh`\n\nbuild arm64 version:\n\n`./build_arm64.sh`\n\nbuild riscv64 version:\n\n`./build_riscv64.sh`\n\nbuild loongarch64 version:\n\n`./build_loongarch64.sh`\n\nbuild e2k version:\n\n`./build_e2k.sh`\n\nclean:\n\n`./clean.sh`\n\n## How to benchmark\n\n`./cpufp --thread_pool=[xxx] --idle_time=yyy`\n\n --thread_pool: [xxx] is the list of cpu thread to benchmarking, from setting affinities. Please reference the result of lstopo command. For example, [0,3,5-8,13-15].\n\n --idle_time: the interval time(sec) between any two adjacent benchmarks, default is 0.\n\n## Benchmark results\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
ArchBenchmark
x86-64AMD Ryzen7 9700X
AMD Ryzen7 8845HS
AMD Ryzen9 6900HX
Intel Xeon Gold 6455B
Intel Xeon W9-3495X
Intel Core i5 1340P
Intel Ultra7 255H
Intel Core i3_8121U
Intel N150
ZHAOXIN KX-6640MA
arm64Apple Silicon M4 Max
Apple Silicon M2 Max
Qualcomm Snapdragon X Elite X1E80100
AWS Graviton 3E
Broadcom BCM2712
Broadcom BCM2711
CIX P1 CD8180
HUAWEI Kunpeng 920 7260
HUAWEI Kunpeng D920 2249K
Phytium D2000/8
RockChip RK3588
RockChip RK3399
riscv64SpacemiT K1
Kendryte K230
loongarch64Loongson 3A6000
Loongson 3C5000
Loongson 3A5000M
e2kElbrus 8C2
Elbrus 8C
Elbrus 4C
\n\n## Todo list\n\nAdd armv9(SVE, SVE2 & SME) Supports.\n" }, { "path": "arm64/asm/_ASIMD_.S", "content": ".align 4\n\n.macro preserve_caller_vec\n\tstp d8, d9, [sp, #-16]!\n\tstp d10, d11, [sp, #-16]!\n\tstp d12, d13, [sp, #-16]!\n\tstp d14, d15, [sp, #-16]!\n.endm\n\n.macro restore_caller_vec\n\tldp d14, d15, [sp], #16\n\tldp d12, d13, [sp], #16\n\tldp d10, d11, [sp], #16\n\tldp d8, d9, [sp], #16\n.endm\n\n#ifdef __APPLE__\n.globl _asimd_fmla_vs_f32f32f32\n_asimd_fmla_vs_f32f32f32:\n#else\n.globl asimd_fmla_vs_f32f32f32\nasimd_fmla_vs_f32f32f32:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.fmla.vs.f32f32f32.L1:\n fmla v8.4s, v0.4s, v1.s[0]\n fmla v9.4s, v0.4s, v1.s[0]\n fmla v10.4s, v0.4s, v1.s[0]\n fmla v11.4s, v0.4s, v1.s[0]\n fmla v12.4s, v0.4s, v1.s[0]\n fmla v13.4s, v0.4s, v1.s[0]\n fmla v14.4s, v0.4s, v1.s[0]\n fmla v15.4s, v0.4s, v1.s[0]\n fmla v16.4s, v0.4s, v1.s[0]\n fmla v17.4s, v0.4s, v1.s[0]\n fmla v18.4s, v0.4s, v1.s[0]\n fmla v19.4s, v0.4s, v1.s[0]\n subs x0, x0, #1\n fmla v20.4s, v0.4s, v1.s[0]\n fmla v21.4s, v0.4s, v1.s[0]\n fmla v22.4s, v0.4s, v1.s[0]\n fmla v23.4s, v0.4s, v1.s[0]\n fmla v24.4s, v0.4s, v1.s[0]\n fmla v25.4s, v0.4s, v1.s[0]\n fmla v26.4s, v0.4s, v1.s[0]\n fmla v27.4s, v0.4s, v1.s[0]\n fmla v28.4s, v0.4s, v1.s[0]\n fmla v29.4s, v0.4s, v1.s[0]\n fmla v30.4s, v0.4s, v1.s[0]\n fmla v31.4s, v0.4s, v1.s[0]\n bne .asimd.fmla.vs.f32f32f32.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _asimd_fmla_vv_f32f32f32\n_asimd_fmla_vv_f32f32f32:\n#else\n.globl asimd_fmla_vv_f32f32f32\nasimd_fmla_vv_f32f32f32:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.fmla.vv.f32f32f32.L1:\n fmla v8.4s, v0.4s, v1.4s\n fmla v9.4s, v0.4s, v1.4s\n fmla v10.4s, v0.4s, v1.4s\n fmla v11.4s, v0.4s, v1.4s\n fmla v12.4s, v0.4s, v1.4s\n fmla v13.4s, v0.4s, v1.4s\n fmla v14.4s, v0.4s, v1.4s\n fmla v15.4s, v0.4s, v1.4s\n fmla v16.4s, v0.4s, v1.4s\n fmla v17.4s, v0.4s, v1.4s\n fmla v18.4s, v0.4s, v1.4s\n fmla v19.4s, v0.4s, v1.4s\n subs x0, x0, #1\n fmla v20.4s, v0.4s, v1.4s\n fmla v21.4s, v0.4s, v1.4s\n fmla v22.4s, v0.4s, v1.4s\n fmla v23.4s, v0.4s, v1.4s\n fmla v24.4s, v0.4s, v1.4s\n fmla v25.4s, v0.4s, v1.4s\n fmla v26.4s, v0.4s, v1.4s\n fmla v27.4s, v0.4s, v1.4s\n fmla v28.4s, v0.4s, v1.4s\n fmla v29.4s, v0.4s, v1.4s\n fmla v30.4s, v0.4s, v1.4s\n fmla v31.4s, v0.4s, v1.4s\n bne .asimd.fmla.vv.f32f32f32.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _asimd_fmla_vs_f64f64f64\n_asimd_fmla_vs_f64f64f64:\n#else\n.globl asimd_fmla_vs_f64f64f64\nasimd_fmla_vs_f64f64f64:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.fmla.vs.f64f64f64.L1:\n fmla v8.2d, v0.2d, v1.d[0]\n fmla v9.2d, v0.2d, v1.d[0]\n fmla v10.2d, v0.2d, v1.d[0]\n fmla v11.2d, v0.2d, v1.d[0]\n fmla v12.2d, v0.2d, v1.d[0]\n fmla v13.2d, v0.2d, v1.d[0]\n fmla v14.2d, v0.2d, v1.d[0]\n fmla v15.2d, v0.2d, v1.d[0]\n fmla v16.2d, v0.2d, v1.d[0]\n fmla v17.2d, v0.2d, v1.d[0]\n fmla v18.2d, v0.2d, v1.d[0]\n fmla v19.2d, v0.2d, v1.d[0]\n subs x0, x0, #1\n fmla v20.2d, v0.2d, v1.d[0]\n fmla v21.2d, v0.2d, v1.d[0]\n fmla v22.2d, v0.2d, v1.d[0]\n fmla v23.2d, v0.2d, v1.d[0]\n fmla v24.2d, v0.2d, v1.d[0]\n fmla v25.2d, v0.2d, v1.d[0]\n fmla v26.2d, v0.2d, v1.d[0]\n fmla v27.2d, v0.2d, v1.d[0]\n fmla v28.2d, v0.2d, v1.d[0]\n fmla v29.2d, v0.2d, v1.d[0]\n fmla v30.2d, v0.2d, v1.d[0]\n fmla v31.2d, v0.2d, v1.d[0]\n bne .asimd.fmla.vs.f64f64f64.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _asimd_fmla_vv_f64f64f64\n_asimd_fmla_vv_f64f64f64:\n#else\n.globl asimd_fmla_vv_f64f64f64\nasimd_fmla_vv_f64f64f64:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.fmla.vv.f64f64f64.L1:\n fmla v8.2d, v0.2d, v1.2d\n fmla v9.2d, v0.2d, v1.2d\n fmla v10.2d, v0.2d, v1.2d\n fmla v11.2d, v0.2d, v1.2d\n fmla v12.2d, v0.2d, v1.2d\n fmla v13.2d, v0.2d, v1.2d\n fmla v14.2d, v0.2d, v1.2d\n fmla v15.2d, v0.2d, v1.2d\n fmla v16.2d, v0.2d, v1.2d\n fmla v17.2d, v0.2d, v1.2d\n fmla v18.2d, v0.2d, v1.2d\n fmla v19.2d, v0.2d, v1.2d\n subs x0, x0, #1\n fmla v20.2d, v0.2d, v1.2d\n fmla v21.2d, v0.2d, v1.2d\n fmla v22.2d, v0.2d, v1.2d\n fmla v23.2d, v0.2d, v1.2d\n fmla v24.2d, v0.2d, v1.2d\n fmla v25.2d, v0.2d, v1.2d\n fmla v26.2d, v0.2d, v1.2d\n fmla v27.2d, v0.2d, v1.2d\n fmla v28.2d, v0.2d, v1.2d\n fmla v29.2d, v0.2d, v1.2d\n fmla v30.2d, v0.2d, v1.2d\n fmla v31.2d, v0.2d, v1.2d\n bne .asimd.fmla.vv.f64f64f64.L1\n restore_caller_vec\n ret\n\n" }, { "path": "arm64/asm/_ASIMD_DP_.S", "content": ".align 4\n\n.macro preserve_caller_vec\n\tstp d8, d9, [sp, #-16]!\n\tstp d10, d11, [sp, #-16]!\n\tstp d12, d13, [sp, #-16]!\n\tstp d14, d15, [sp, #-16]!\n.endm\n\n.macro restore_caller_vec\n\tldp d14, d15, [sp], #16\n\tldp d12, d13, [sp], #16\n\tldp d10, d11, [sp], #16\n\tldp d8, d9, [sp], #16\n.endm\n\n#ifdef __APPLE__\n.globl _asimd_dp4a_vs_s32s8s8\n_asimd_dp4a_vs_s32s8s8:\n#else\n.globl asimd_dp4a_vs_s32s8s8\nasimd_dp4a_vs_s32s8s8:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.dp4a.vs.s32s8s8.L1:\n sdot v8.4s, v0.16b, v1.4b[0]\n sdot v9.4s, v0.16b, v1.4b[0]\n sdot v10.4s, v0.16b, v1.4b[0]\n sdot v11.4s, v0.16b, v1.4b[0]\n sdot v12.4s, v0.16b, v1.4b[0]\n sdot v13.4s, v0.16b, v1.4b[0]\n sdot v14.4s, v0.16b, v1.4b[0]\n sdot v15.4s, v0.16b, v1.4b[0]\n sdot v16.4s, v0.16b, v1.4b[0]\n sdot v17.4s, v0.16b, v1.4b[0]\n sdot v18.4s, v0.16b, v1.4b[0]\n sdot v19.4s, v0.16b, v1.4b[0]\n subs x0, x0, #1\n sdot v20.4s, v0.16b, v1.4b[0]\n sdot v21.4s, v0.16b, v1.4b[0]\n sdot v22.4s, v0.16b, v1.4b[0]\n sdot v23.4s, v0.16b, v1.4b[0]\n sdot v24.4s, v0.16b, v1.4b[0]\n sdot v25.4s, v0.16b, v1.4b[0]\n sdot v26.4s, v0.16b, v1.4b[0]\n sdot v27.4s, v0.16b, v1.4b[0]\n sdot v28.4s, v0.16b, v1.4b[0]\n sdot v29.4s, v0.16b, v1.4b[0]\n sdot v30.4s, v0.16b, v1.4b[0]\n sdot v31.4s, v0.16b, v1.4b[0]\n bne .asimd.dp4a.vs.s32s8s8.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _asimd_dp4a_vv_s32s8s8\n_asimd_dp4a_vv_s32s8s8:\n#else\n.globl asimd_dp4a_vv_s32s8s8\nasimd_dp4a_vv_s32s8s8:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.dp4a.vv.s32s8s8.L1:\n sdot v8.4s, v0.16b, v1.16b\n sdot v9.4s, v0.16b, v1.16b\n sdot v10.4s, v0.16b, v1.16b\n sdot v11.4s, v0.16b, v1.16b\n sdot v12.4s, v0.16b, v1.16b\n sdot v13.4s, v0.16b, v1.16b\n sdot v14.4s, v0.16b, v1.16b\n sdot v15.4s, v0.16b, v1.16b\n sdot v16.4s, v0.16b, v1.16b\n sdot v17.4s, v0.16b, v1.16b\n sdot v18.4s, v0.16b, v1.16b\n sdot v19.4s, v0.16b, v1.16b\n subs x0, x0, #1\n sdot v20.4s, v0.16b, v1.16b\n sdot v21.4s, v0.16b, v1.16b\n sdot v22.4s, v0.16b, v1.16b\n sdot v23.4s, v0.16b, v1.16b\n sdot v24.4s, v0.16b, v1.16b\n sdot v25.4s, v0.16b, v1.16b\n sdot v26.4s, v0.16b, v1.16b\n sdot v27.4s, v0.16b, v1.16b\n sdot v28.4s, v0.16b, v1.16b\n sdot v29.4s, v0.16b, v1.16b\n sdot v30.4s, v0.16b, v1.16b\n sdot v31.4s, v0.16b, v1.16b\n bne .asimd.dp4a.vv.s32s8s8.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _asimd_dp4a_vs_u32u8u8\n_asimd_dp4a_vs_u32u8u8:\n#else\n.globl asimd_dp4a_vs_u32u8u8\nasimd_dp4a_vs_u32u8u8:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.dp4a.vs.u32u8u8.L1:\n udot v8.4s, v0.16b, v1.4b[0]\n udot v9.4s, v0.16b, v1.4b[0]\n udot v10.4s, v0.16b, v1.4b[0]\n udot v11.4s, v0.16b, v1.4b[0]\n udot v12.4s, v0.16b, v1.4b[0]\n udot v13.4s, v0.16b, v1.4b[0]\n udot v14.4s, v0.16b, v1.4b[0]\n udot v15.4s, v0.16b, v1.4b[0]\n udot v16.4s, v0.16b, v1.4b[0]\n udot v17.4s, v0.16b, v1.4b[0]\n udot v18.4s, v0.16b, v1.4b[0]\n udot v19.4s, v0.16b, v1.4b[0]\n subs x0, x0, #1\n udot v20.4s, v0.16b, v1.4b[0]\n udot v21.4s, v0.16b, v1.4b[0]\n udot v22.4s, v0.16b, v1.4b[0]\n udot v23.4s, v0.16b, v1.4b[0]\n udot v24.4s, v0.16b, v1.4b[0]\n udot v25.4s, v0.16b, v1.4b[0]\n udot v26.4s, v0.16b, v1.4b[0]\n udot v27.4s, v0.16b, v1.4b[0]\n udot v28.4s, v0.16b, v1.4b[0]\n udot v29.4s, v0.16b, v1.4b[0]\n udot v30.4s, v0.16b, v1.4b[0]\n udot v31.4s, v0.16b, v1.4b[0]\n bne .asimd.dp4a.vs.u32u8u8.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _asimd_dp4a_vv_u32u8u8\n_asimd_dp4a_vv_u32u8u8:\n#else\n.globl asimd_dp4a_vv_u32u8u8\nasimd_dp4a_vv_u32u8u8:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.dp4a.vv.u32u8u8.L1:\n udot v8.4s, v0.16b, v1.16b\n udot v9.4s, v0.16b, v1.16b\n udot v10.4s, v0.16b, v1.16b\n udot v11.4s, v0.16b, v1.16b\n udot v12.4s, v0.16b, v1.16b\n udot v13.4s, v0.16b, v1.16b\n udot v14.4s, v0.16b, v1.16b\n udot v15.4s, v0.16b, v1.16b\n udot v16.4s, v0.16b, v1.16b\n udot v17.4s, v0.16b, v1.16b\n udot v18.4s, v0.16b, v1.16b\n udot v19.4s, v0.16b, v1.16b\n subs x0, x0, #1\n udot v20.4s, v0.16b, v1.16b\n udot v21.4s, v0.16b, v1.16b\n udot v22.4s, v0.16b, v1.16b\n udot v23.4s, v0.16b, v1.16b\n udot v24.4s, v0.16b, v1.16b\n udot v25.4s, v0.16b, v1.16b\n udot v26.4s, v0.16b, v1.16b\n udot v27.4s, v0.16b, v1.16b\n udot v28.4s, v0.16b, v1.16b\n udot v29.4s, v0.16b, v1.16b\n udot v30.4s, v0.16b, v1.16b\n udot v31.4s, v0.16b, v1.16b\n bne .asimd.dp4a.vv.u32u8u8.L1\n restore_caller_vec\n ret\n\n" }, { "path": "arm64/asm/_ASIMD_HP_.S", "content": ".align 4\n\n.macro preserve_caller_vec\n\tstp d8, d9, [sp, #-16]!\n\tstp d10, d11, [sp, #-16]!\n\tstp d12, d13, [sp, #-16]!\n\tstp d14, d15, [sp, #-16]!\n.endm\n\n.macro restore_caller_vec\n\tldp d14, d15, [sp], #16\n\tldp d12, d13, [sp], #16\n\tldp d10, d11, [sp], #16\n\tldp d8, d9, [sp], #16\n.endm\n\n#ifdef __APPLE__\n.globl _asimd_fmla_vs_fp16fp16fp16\n_asimd_fmla_vs_fp16fp16fp16:\n#else\n.globl asimd_fmla_vs_fp16fp16fp16\nasimd_fmla_vs_fp16fp16fp16:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.fmla.vs.fp16fp16fp16.L1:\n fmla v8.8h, v0.8h, v1.h[0]\n fmla v9.8h, v0.8h, v1.h[0]\n fmla v10.8h, v0.8h, v1.h[0]\n fmla v11.8h, v0.8h, v1.h[0]\n fmla v12.8h, v0.8h, v1.h[0]\n fmla v13.8h, v0.8h, v1.h[0]\n fmla v14.8h, v0.8h, v1.h[0]\n fmla v15.8h, v0.8h, v1.h[0]\n fmla v16.8h, v0.8h, v1.h[0]\n fmla v17.8h, v0.8h, v1.h[0]\n fmla v18.8h, v0.8h, v1.h[0]\n fmla v19.8h, v0.8h, v1.h[0]\n subs x0, x0, #1\n fmla v20.8h, v0.8h, v1.h[0]\n fmla v21.8h, v0.8h, v1.h[0]\n fmla v22.8h, v0.8h, v1.h[0]\n fmla v23.8h, v0.8h, v1.h[0]\n fmla v24.8h, v0.8h, v1.h[0]\n fmla v25.8h, v0.8h, v1.h[0]\n fmla v26.8h, v0.8h, v1.h[0]\n fmla v27.8h, v0.8h, v1.h[0]\n fmla v28.8h, v0.8h, v1.h[0]\n fmla v29.8h, v0.8h, v1.h[0]\n fmla v30.8h, v0.8h, v1.h[0]\n fmla v31.8h, v0.8h, v1.h[0]\n bne .asimd.fmla.vs.fp16fp16fp16.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _asimd_fmla_vv_fp16fp16fp16\n_asimd_fmla_vv_fp16fp16fp16:\n#else\n.globl asimd_fmla_vv_fp16fp16fp16\nasimd_fmla_vv_fp16fp16fp16:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.fmla.vv.fp16fp16fp16.L1:\n fmla v8.8h, v0.8h, v1.8h\n fmla v9.8h, v0.8h, v1.8h\n fmla v10.8h, v0.8h, v1.8h\n fmla v11.8h, v0.8h, v1.8h\n fmla v12.8h, v0.8h, v1.8h\n fmla v13.8h, v0.8h, v1.8h\n fmla v14.8h, v0.8h, v1.8h\n fmla v15.8h, v0.8h, v1.8h\n fmla v16.8h, v0.8h, v1.8h\n fmla v17.8h, v0.8h, v1.8h\n fmla v18.8h, v0.8h, v1.8h\n fmla v19.8h, v0.8h, v1.8h\n subs x0, x0, #1\n fmla v20.8h, v0.8h, v1.8h\n fmla v21.8h, v0.8h, v1.8h\n fmla v22.8h, v0.8h, v1.8h\n fmla v23.8h, v0.8h, v1.8h\n fmla v24.8h, v0.8h, v1.8h\n fmla v25.8h, v0.8h, v1.8h\n fmla v26.8h, v0.8h, v1.8h\n fmla v27.8h, v0.8h, v1.8h\n fmla v28.8h, v0.8h, v1.8h\n fmla v29.8h, v0.8h, v1.8h\n fmla v30.8h, v0.8h, v1.8h\n fmla v31.8h, v0.8h, v1.8h\n bne .asimd.fmla.vv.fp16fp16fp16.L1\n restore_caller_vec\n ret\n\n" }, { "path": "arm64/asm/_BF16_.S", "content": ".align 4\n\n.macro preserve_caller_vec\n\tstp d8, d9, [sp, #-16]!\n\tstp d10, d11, [sp, #-16]!\n\tstp d12, d13, [sp, #-16]!\n\tstp d14, d15, [sp, #-16]!\n.endm\n\n.macro restore_caller_vec\n\tldp d14, d15, [sp], #16\n\tldp d12, d13, [sp], #16\n\tldp d10, d11, [sp], #16\n\tldp d8, d9, [sp], #16\n.endm\n\n#ifdef __APPLE__\n.globl _asimd_mmla_fp32bf16bf16\n_asimd_mmla_fp32bf16bf16:\n#else\n.globl asimd_mmla_fp32bf16bf16\nasimd_mmla_fp32bf16bf16:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.mmla.fp32bf16bf16.L1:\n bfmmla v8.4s, v0.8h, v1.8h\n bfmmla v9.4s, v0.8h, v1.8h\n bfmmla v10.4s, v0.8h, v1.8h\n bfmmla v11.4s, v0.8h, v1.8h\n bfmmla v12.4s, v0.8h, v1.8h\n bfmmla v13.4s, v0.8h, v1.8h\n bfmmla v14.4s, v0.8h, v1.8h\n bfmmla v15.4s, v0.8h, v1.8h\n bfmmla v16.4s, v0.8h, v1.8h\n bfmmla v17.4s, v0.8h, v1.8h\n bfmmla v18.4s, v0.8h, v1.8h\n bfmmla v19.4s, v0.8h, v1.8h\n subs x0, x0, #1\n bfmmla v20.4s, v0.8h, v1.8h\n bfmmla v21.4s, v0.8h, v1.8h\n bfmmla v22.4s, v0.8h, v1.8h\n bfmmla v23.4s, v0.8h, v1.8h\n bfmmla v24.4s, v0.8h, v1.8h\n bfmmla v25.4s, v0.8h, v1.8h\n bfmmla v26.4s, v0.8h, v1.8h\n bfmmla v27.4s, v0.8h, v1.8h\n bfmmla v28.4s, v0.8h, v1.8h\n bfmmla v29.4s, v0.8h, v1.8h\n bfmmla v30.4s, v0.8h, v1.8h\n bfmmla v31.4s, v0.8h, v1.8h\n bne .asimd.mmla.fp32bf16bf16.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _asimd_dp2a_vs_fp32bf16bf16\n_asimd_dp2a_vs_fp32bf16bf16:\n#else\n.globl asimd_dp2a_vs_fp32bf16bf16\nasimd_dp2a_vs_fp32bf16bf16:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.dp2a.vs.fp32bf16bf16.L1:\n bfdot v8.4s, v0.8h, v1.2h[0]\n bfdot v9.4s, v0.8h, v1.2h[0]\n bfdot v10.4s, v0.8h, v1.2h[0]\n bfdot v11.4s, v0.8h, v1.2h[0]\n bfdot v12.4s, v0.8h, v1.2h[0]\n bfdot v13.4s, v0.8h, v1.2h[0]\n bfdot v14.4s, v0.8h, v1.2h[0]\n bfdot v15.4s, v0.8h, v1.2h[0]\n bfdot v16.4s, v0.8h, v1.2h[0]\n bfdot v17.4s, v0.8h, v1.2h[0]\n bfdot v18.4s, v0.8h, v1.2h[0]\n bfdot v19.4s, v0.8h, v1.2h[0]\n subs x0, x0, #1\n bfdot v20.4s, v0.8h, v1.2h[0]\n bfdot v21.4s, v0.8h, v1.2h[0]\n bfdot v22.4s, v0.8h, v1.2h[0]\n bfdot v23.4s, v0.8h, v1.2h[0]\n bfdot v24.4s, v0.8h, v1.2h[0]\n bfdot v25.4s, v0.8h, v1.2h[0]\n bfdot v26.4s, v0.8h, v1.2h[0]\n bfdot v27.4s, v0.8h, v1.2h[0]\n bfdot v28.4s, v0.8h, v1.2h[0]\n bfdot v29.4s, v0.8h, v1.2h[0]\n bfdot v30.4s, v0.8h, v1.2h[0]\n bfdot v31.4s, v0.8h, v1.2h[0]\n bne .asimd.dp2a.vs.fp32bf16bf16.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _asimd_dp2a_vv_fp32bf16bf16\n_asimd_dp2a_vv_fp32bf16bf16:\n#else\n.globl asimd_dp2a_vv_fp32bf16bf16\nasimd_dp2a_vv_fp32bf16bf16:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.dp2a.vv.fp32bf16bf16.L1:\n bfdot v8.4s, v0.8h, v1.8h\n bfdot v9.4s, v0.8h, v1.8h\n bfdot v10.4s, v0.8h, v1.8h\n bfdot v11.4s, v0.8h, v1.8h\n bfdot v12.4s, v0.8h, v1.8h\n bfdot v13.4s, v0.8h, v1.8h\n bfdot v14.4s, v0.8h, v1.8h\n bfdot v15.4s, v0.8h, v1.8h\n bfdot v16.4s, v0.8h, v1.8h\n bfdot v17.4s, v0.8h, v1.8h\n bfdot v18.4s, v0.8h, v1.8h\n bfdot v19.4s, v0.8h, v1.8h\n subs x0, x0, #1\n bfdot v20.4s, v0.8h, v1.8h\n bfdot v21.4s, v0.8h, v1.8h\n bfdot v22.4s, v0.8h, v1.8h\n bfdot v23.4s, v0.8h, v1.8h\n bfdot v24.4s, v0.8h, v1.8h\n bfdot v25.4s, v0.8h, v1.8h\n bfdot v26.4s, v0.8h, v1.8h\n bfdot v27.4s, v0.8h, v1.8h\n bfdot v28.4s, v0.8h, v1.8h\n bfdot v29.4s, v0.8h, v1.8h\n bfdot v30.4s, v0.8h, v1.8h\n bfdot v31.4s, v0.8h, v1.8h\n bne .asimd.dp2a.vv.fp32bf16bf16.L1\n restore_caller_vec\n ret\n\n" }, { "path": "arm64/asm/_I8MM_.S", "content": ".align 4\n\n.macro preserve_caller_vec\n\tstp d8, d9, [sp, #-16]!\n\tstp d10, d11, [sp, #-16]!\n\tstp d12, d13, [sp, #-16]!\n\tstp d14, d15, [sp, #-16]!\n.endm\n\n.macro restore_caller_vec\n\tldp d14, d15, [sp], #16\n\tldp d12, d13, [sp], #16\n\tldp d10, d11, [sp], #16\n\tldp d8, d9, [sp], #16\n.endm\n\n#ifdef __APPLE__\n.globl _asimd_mmla_s32s8s8\n_asimd_mmla_s32s8s8:\n#else\n.globl asimd_mmla_s32s8s8\nasimd_mmla_s32s8s8:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.mmla.s32s8s8.L1:\n smmla v8.4s, v0.16b, v1.16b\n smmla v9.4s, v0.16b, v1.16b\n smmla v10.4s, v0.16b, v1.16b\n smmla v11.4s, v0.16b, v1.16b\n smmla v12.4s, v0.16b, v1.16b\n smmla v13.4s, v0.16b, v1.16b\n smmla v14.4s, v0.16b, v1.16b\n smmla v15.4s, v0.16b, v1.16b\n smmla v16.4s, v0.16b, v1.16b\n smmla v17.4s, v0.16b, v1.16b\n smmla v18.4s, v0.16b, v1.16b\n smmla v19.4s, v0.16b, v1.16b\n subs x0, x0, #1\n smmla v20.4s, v0.16b, v1.16b\n smmla v21.4s, v0.16b, v1.16b\n smmla v22.4s, v0.16b, v1.16b\n smmla v23.4s, v0.16b, v1.16b\n smmla v24.4s, v0.16b, v1.16b\n smmla v25.4s, v0.16b, v1.16b\n smmla v26.4s, v0.16b, v1.16b\n smmla v27.4s, v0.16b, v1.16b\n smmla v28.4s, v0.16b, v1.16b\n smmla v29.4s, v0.16b, v1.16b\n smmla v30.4s, v0.16b, v1.16b\n smmla v31.4s, v0.16b, v1.16b\n bne .asimd.mmla.s32s8s8.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _asimd_mmla_u32u8u8\n_asimd_mmla_u32u8u8:\n#else\n.globl asimd_mmla_u32u8u8\nasimd_mmla_u32u8u8:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.mmla.u32u8u8.L1:\n ummla v8.4s, v0.16b, v1.16b\n ummla v9.4s, v0.16b, v1.16b\n ummla v10.4s, v0.16b, v1.16b\n ummla v11.4s, v0.16b, v1.16b\n ummla v12.4s, v0.16b, v1.16b\n ummla v13.4s, v0.16b, v1.16b\n ummla v14.4s, v0.16b, v1.16b\n ummla v15.4s, v0.16b, v1.16b\n ummla v16.4s, v0.16b, v1.16b\n ummla v17.4s, v0.16b, v1.16b\n ummla v18.4s, v0.16b, v1.16b\n ummla v19.4s, v0.16b, v1.16b\n subs x0, x0, #1\n ummla v20.4s, v0.16b, v1.16b\n ummla v21.4s, v0.16b, v1.16b\n ummla v22.4s, v0.16b, v1.16b\n ummla v23.4s, v0.16b, v1.16b\n ummla v24.4s, v0.16b, v1.16b\n ummla v25.4s, v0.16b, v1.16b\n ummla v26.4s, v0.16b, v1.16b\n ummla v27.4s, v0.16b, v1.16b\n ummla v28.4s, v0.16b, v1.16b\n ummla v29.4s, v0.16b, v1.16b\n ummla v30.4s, v0.16b, v1.16b\n ummla v31.4s, v0.16b, v1.16b\n bne .asimd.mmla.u32u8u8.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _asimd_mmla_s32u8s8\n_asimd_mmla_s32u8s8:\n#else\n.globl asimd_mmla_s32u8s8\nasimd_mmla_s32u8s8:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.mmla.s32u8s8.L1:\n usmmla v8.4s, v0.16b, v1.16b\n usmmla v9.4s, v0.16b, v1.16b\n usmmla v10.4s, v0.16b, v1.16b\n usmmla v11.4s, v0.16b, v1.16b\n usmmla v12.4s, v0.16b, v1.16b\n usmmla v13.4s, v0.16b, v1.16b\n usmmla v14.4s, v0.16b, v1.16b\n usmmla v15.4s, v0.16b, v1.16b\n usmmla v16.4s, v0.16b, v1.16b\n usmmla v17.4s, v0.16b, v1.16b\n usmmla v18.4s, v0.16b, v1.16b\n usmmla v19.4s, v0.16b, v1.16b\n subs x0, x0, #1\n usmmla v20.4s, v0.16b, v1.16b\n usmmla v21.4s, v0.16b, v1.16b\n usmmla v22.4s, v0.16b, v1.16b\n usmmla v23.4s, v0.16b, v1.16b\n usmmla v24.4s, v0.16b, v1.16b\n usmmla v25.4s, v0.16b, v1.16b\n usmmla v26.4s, v0.16b, v1.16b\n usmmla v27.4s, v0.16b, v1.16b\n usmmla v28.4s, v0.16b, v1.16b\n usmmla v29.4s, v0.16b, v1.16b\n usmmla v30.4s, v0.16b, v1.16b\n usmmla v31.4s, v0.16b, v1.16b\n bne .asimd.mmla.s32u8s8.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _asimd_dp4a_vs_s32s8u8\n_asimd_dp4a_vs_s32s8u8:\n#else\n.globl asimd_dp4a_vs_s32s8u8\nasimd_dp4a_vs_s32s8u8:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.dp4a.vs.s32s8u8.L1:\n sudot v8.4s, v0.16b, v1.4b[0]\n sudot v9.4s, v0.16b, v1.4b[0]\n sudot v10.4s, v0.16b, v1.4b[0]\n sudot v11.4s, v0.16b, v1.4b[0]\n sudot v12.4s, v0.16b, v1.4b[0]\n sudot v13.4s, v0.16b, v1.4b[0]\n sudot v14.4s, v0.16b, v1.4b[0]\n sudot v15.4s, v0.16b, v1.4b[0]\n sudot v16.4s, v0.16b, v1.4b[0]\n sudot v17.4s, v0.16b, v1.4b[0]\n sudot v18.4s, v0.16b, v1.4b[0]\n sudot v19.4s, v0.16b, v1.4b[0]\n subs x0, x0, #1\n sudot v20.4s, v0.16b, v1.4b[0]\n sudot v21.4s, v0.16b, v1.4b[0]\n sudot v22.4s, v0.16b, v1.4b[0]\n sudot v23.4s, v0.16b, v1.4b[0]\n sudot v24.4s, v0.16b, v1.4b[0]\n sudot v25.4s, v0.16b, v1.4b[0]\n sudot v26.4s, v0.16b, v1.4b[0]\n sudot v27.4s, v0.16b, v1.4b[0]\n sudot v28.4s, v0.16b, v1.4b[0]\n sudot v29.4s, v0.16b, v1.4b[0]\n sudot v30.4s, v0.16b, v1.4b[0]\n sudot v31.4s, v0.16b, v1.4b[0]\n bne .asimd.dp4a.vs.s32s8u8.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _asimd_dp4a_vs_s32u8s8\n_asimd_dp4a_vs_s32u8s8:\n#else\n.globl asimd_dp4a_vs_s32u8s8\nasimd_dp4a_vs_s32u8s8:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.dp4a.vs.s32u8s8.L1:\n usdot v8.4s, v0.16b, v1.4b[0]\n usdot v9.4s, v0.16b, v1.4b[0]\n usdot v10.4s, v0.16b, v1.4b[0]\n usdot v11.4s, v0.16b, v1.4b[0]\n usdot v12.4s, v0.16b, v1.4b[0]\n usdot v13.4s, v0.16b, v1.4b[0]\n usdot v14.4s, v0.16b, v1.4b[0]\n usdot v15.4s, v0.16b, v1.4b[0]\n usdot v16.4s, v0.16b, v1.4b[0]\n usdot v17.4s, v0.16b, v1.4b[0]\n usdot v18.4s, v0.16b, v1.4b[0]\n usdot v19.4s, v0.16b, v1.4b[0]\n subs x0, x0, #1\n usdot v20.4s, v0.16b, v1.4b[0]\n usdot v21.4s, v0.16b, v1.4b[0]\n usdot v22.4s, v0.16b, v1.4b[0]\n usdot v23.4s, v0.16b, v1.4b[0]\n usdot v24.4s, v0.16b, v1.4b[0]\n usdot v25.4s, v0.16b, v1.4b[0]\n usdot v26.4s, v0.16b, v1.4b[0]\n usdot v27.4s, v0.16b, v1.4b[0]\n usdot v28.4s, v0.16b, v1.4b[0]\n usdot v29.4s, v0.16b, v1.4b[0]\n usdot v30.4s, v0.16b, v1.4b[0]\n usdot v31.4s, v0.16b, v1.4b[0]\n bne .asimd.dp4a.vs.s32u8s8.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _asimd_dp4a_vv_s32u8s8\n_asimd_dp4a_vv_s32u8s8:\n#else\n.globl asimd_dp4a_vv_s32u8s8\nasimd_dp4a_vv_s32u8s8:\n#endif\n preserve_caller_vec\n eor v0.16b, v0.16b, v0.16b\n eor v1.16b, v1.16b, v1.16b\n eor v8.16b, v8.16b, v8.16b\n eor v9.16b, v9.16b, v9.16b\n eor v10.16b, v10.16b, v10.16b\n eor v11.16b, v11.16b, v11.16b\n eor v12.16b, v12.16b, v12.16b\n eor v13.16b, v13.16b, v13.16b\n eor v14.16b, v14.16b, v14.16b\n eor v15.16b, v15.16b, v15.16b\n eor v16.16b, v16.16b, v16.16b\n eor v17.16b, v17.16b, v17.16b\n eor v18.16b, v18.16b, v18.16b\n eor v19.16b, v19.16b, v19.16b\n eor v20.16b, v20.16b, v20.16b\n eor v21.16b, v21.16b, v21.16b\n eor v22.16b, v22.16b, v22.16b\n eor v23.16b, v23.16b, v23.16b\n eor v24.16b, v24.16b, v24.16b\n eor v25.16b, v25.16b, v25.16b\n eor v26.16b, v26.16b, v26.16b\n eor v27.16b, v27.16b, v27.16b\n eor v28.16b, v28.16b, v28.16b\n eor v29.16b, v29.16b, v29.16b\n eor v30.16b, v30.16b, v30.16b\n eor v31.16b, v31.16b, v31.16b\n.asimd.dp4a.vv.s32u8s8.L1:\n usdot v8.4s, v0.16b, v1.16b\n usdot v9.4s, v0.16b, v1.16b\n usdot v10.4s, v0.16b, v1.16b\n usdot v11.4s, v0.16b, v1.16b\n usdot v12.4s, v0.16b, v1.16b\n usdot v13.4s, v0.16b, v1.16b\n usdot v14.4s, v0.16b, v1.16b\n usdot v15.4s, v0.16b, v1.16b\n usdot v16.4s, v0.16b, v1.16b\n usdot v17.4s, v0.16b, v1.16b\n usdot v18.4s, v0.16b, v1.16b\n usdot v19.4s, v0.16b, v1.16b\n subs x0, x0, #1\n usdot v20.4s, v0.16b, v1.16b\n usdot v21.4s, v0.16b, v1.16b\n usdot v22.4s, v0.16b, v1.16b\n usdot v23.4s, v0.16b, v1.16b\n usdot v24.4s, v0.16b, v1.16b\n usdot v25.4s, v0.16b, v1.16b\n usdot v26.4s, v0.16b, v1.16b\n usdot v27.4s, v0.16b, v1.16b\n usdot v28.4s, v0.16b, v1.16b\n usdot v29.4s, v0.16b, v1.16b\n usdot v30.4s, v0.16b, v1.16b\n usdot v31.4s, v0.16b, v1.16b\n bne .asimd.dp4a.vv.s32u8s8.L1\n restore_caller_vec\n ret\n\n" }, { "path": "arm64/cpufp.cpp", "content": "#include \"table.hpp\"\n#include \"smtl.hpp\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\nusing namespace std;\n\nextern \"C\"\n{\n#ifdef _ASIMD_\n void asimd_fmla_vs_f32f32f32(int64_t);\n void asimd_fmla_vv_f32f32f32(int64_t);\n void asimd_fmla_vs_f64f64f64(int64_t);\n void asimd_fmla_vv_f64f64f64(int64_t);\n#endif\n\n#ifdef _ASIMD_HP_\n void asimd_fmla_vs_fp16fp16fp16(int64_t);\n void asimd_fmla_vv_fp16fp16fp16(int64_t);\n#endif\n\n#ifdef _ASIMD_DP_\n void asimd_dp4a_vs_s32s8s8(int64_t);\n void asimd_dp4a_vv_s32s8s8(int64_t);\n void asimd_dp4a_vs_u32u8u8(int64_t);\n void asimd_dp4a_vv_u32u8u8(int64_t);\n#endif\n\n#ifdef _BF16_\n void asimd_mmla_fp32bf16bf16(int64_t);\n void asimd_dp2a_vs_fp32bf16bf16(int64_t);\n void asimd_dp2a_vv_fp32bf16bf16(int64_t);\n#endif\n\n#ifdef _I8MM_\n void asimd_mmla_s32s8s8(int64_t);\n void asimd_mmla_u32u8u8(int64_t);\n void asimd_mmla_s32u8s8(int64_t);\n\n void asimd_dp4a_vs_s32s8u8(int64_t);\n void asimd_dp4a_vs_s32u8s8(int64_t);\n void asimd_dp4a_vv_s32u8s8(int64_t);\n#endif\n}\n\ntypedef struct\n{\n std::string isa;\n std::string type;\n std::string dim;\n int64_t loop_time;\n int64_t comp_pl;\n void (*bench)(int64_t);\n} cpubm_t;\nstatic vector bm_list;\n\nstatic double get_time(struct timespec *start,\n struct timespec *end)\n{\n return end->tv_sec - start->tv_sec +\n (end->tv_nsec - start->tv_nsec) * 1e-9;\n}\n\nstatic void reg_new_isa(std::string isa,\n std::string type,\n std::string dim,\n int64_t loop_time,\n int64_t comp_pl,\n void (*bench)(int64_t))\n{\n cpubm_t new_one;\n new_one.isa = isa;\n new_one.type = type;\n new_one.dim = dim;\n new_one.loop_time = loop_time;\n new_one.comp_pl = comp_pl;\n new_one.bench = bench;\n\n bm_list.push_back(new_one);\n}\n\nstatic void thread_func(void *params)\n{\n cpubm_t *bm = (cpubm_t*)params;\n bm->bench(bm->loop_time);\n}\n\nstatic void cpubm_arm64_one(smtl_handle sh,\n cpubm_t &item,\n Table &table)\n{\n struct timespec start, end;\n double time_used, perf;\n char perfUnit = 'G';\n\n int i;\n int num_threads = smtl_num_threads(sh);\n\n // warm up\n for (i = 0; i < num_threads; i++)\n {\n smtl_add_task(sh, thread_func, (void*)&item);\n }\n smtl_begin_tasks(sh);\n smtl_wait_tasks_finished(sh);\n\n clock_gettime(CLOCK_MONOTONIC_RAW, &start);\n for (i = 0; i < num_threads; i++)\n {\n smtl_add_task(sh, thread_func, (void*)&item);\n }\n smtl_begin_tasks(sh);\n smtl_wait_tasks_finished(sh);\n clock_gettime(CLOCK_MONOTONIC_RAW, &end);\n\n time_used = get_time(&start, &end);\n perf = item.loop_time * item.comp_pl * num_threads /\n time_used;\n if (perf > 1e12)\n {\n perfUnit = 'T';\n perf /= 1e12;\n }\n else\n {\n perf /= 1e9;\n }\n\n stringstream ss;\n ss << std::setprecision(5) << perf << \" \" << perfUnit << item.dim;\n\n vector cont;\n cont.resize(3);\n cont[0] = item.isa;\n cont[1] = item.type;\n cont[2] = ss.str();\n table.addOneItem(cont);\n}\n\nstatic void cpubm_do_bench(std::vector &set_of_threads,\n uint32_t idle_time)\n{\n int i;\n\n if (bm_list.size() > 0)\n {\n int num_threads = set_of_threads.size();\n\n printf(\"Number Threads: %d\\n\", num_threads);\n printf(\"Thread Pool Binding:\");\n for (i = 0; i < num_threads; i++)\n {\n printf(\" %d\", set_of_threads[i]);\n }\n printf(\"\\n\");\n\n // set table head\n vector ti;\n ti.resize(3);\n ti[0] = \"Instruction Set\";\n ti[1] = \"Core Computation\";\n ti[2] = \"Peak Performance\";\n\n Table table;\n table.setColumnNum(3);\n table.addOneItem(ti);\n\n // set thread pool\n smtl_handle sh;\n smtl_init(&sh, set_of_threads);\n\n // traverse task list\n cpubm_arm64_one(sh, bm_list[0], table);\n for (i = 1; i < bm_list.size(); i++)\n {\n sleep(idle_time);\n cpubm_arm64_one(sh, bm_list[i], table);\n }\n\n table.print();\n\n smtl_fini(sh);\n }\n else\n {\n printf(\"Sorry, there's no any supported SIMD isa.\\n\");\n }\n}\n\nstatic void parse_thread_pool(char *sets,\n vector &set_of_threads)\n{\n if (sets[0] != '[')\n {\n return;\n }\n int pos = 1;\n int left = 0, right = 0;\n int state = 0;\n while (sets[pos] != ']' && sets[pos] != '\\0')\n {\n if (state == 0)\n {\n if (sets[pos] >= '0' && sets[pos] <= '9')\n {\n left *= 10;\n left += (int)(sets[pos] - '0');\n }\n else if (sets[pos] == ',')\n {\n set_of_threads.push_back(left);\n left = 0;\n }\n else if (sets[pos] == '-')\n {\n right = 0;\n state = 1;\n }\n }\n else if (state == 1)\n {\n if (sets[pos] >= '0' && sets[pos] <= '9')\n {\n right *= 10;\n right += (int)(sets[pos] - '0');\n }\n else if (sets[pos] == ',')\n {\n int i;\n for (i = left; i <= right; i++)\n {\n set_of_threads.push_back(i);\n }\n left = 0;\n state = 0;\n }\n }\n pos++;\n }\n if (sets[pos] != ']')\n {\n return;\n }\n if (state == 0)\n {\n set_of_threads.push_back(left);\n }\n else if (state == 1)\n {\n int i;\n for (i = left; i <= right; i++)\n {\n set_of_threads.push_back(i);\n }\n }\n}\n\nstatic void cpufp_register_isa()\n{\n#ifdef _I8MM_\n reg_new_isa(\"i8mm\", \"mmla(s32,s8,s8)\", \"OPS\",\n 0x10000000LL, 1536LL, asimd_mmla_s32s8s8);\n reg_new_isa(\"i8mm\", \"mmla(u32,u8,u8)\", \"OPS\",\n 0x10000000LL, 1536LL, asimd_mmla_u32u8u8);\n reg_new_isa(\"i8mm\", \"mmla(s32,u8,s8)\", \"OPS\",\n 0x10000000LL, 1536LL, asimd_mmla_s32u8s8);\n \n reg_new_isa(\"i8mm\", \"dp4a.vs(s32,s8,u8)\", \"OPS\",\n 0x10000000LL, 768LL, asimd_dp4a_vs_s32s8u8);\n reg_new_isa(\"i8mm\", \"dp4a.vs(s32,u8,s8)\", \"OPS\",\n 0x10000000LL, 768LL, asimd_dp4a_vs_s32u8s8);\n reg_new_isa(\"i8mm\", \"dp4a.vv(s32,u8,s8)\", \"OPS\",\n 0x10000000LL, 768LL, asimd_dp4a_vv_s32u8s8);\n#endif\n\n#ifdef _ASIMD_DP_\n reg_new_isa(\"asimd_dp\", \"dp4a.vs(s32,s8,s8)\", \"OPS\",\n 0x10000000LL, 768LL, asimd_dp4a_vs_s32s8s8);\n reg_new_isa(\"asimd_dp\", \"dp4a.vv(s32,s8,s8)\", \"OPS\",\n 0x10000000LL, 768LL, asimd_dp4a_vv_s32s8s8);\n reg_new_isa(\"asimd_dp\", \"dp4a.vs(u32,u8,u8)\", \"OPS\",\n 0x10000000LL, 768LL, asimd_dp4a_vs_u32u8u8);\n reg_new_isa(\"asimd_dp\", \"dp4a.vv(u32,u8,u8)\", \"OPS\",\n 0x10000000LL, 768LL, asimd_dp4a_vv_u32u8u8);\n#endif\n\n#ifdef _BF16_\n reg_new_isa(\"bf16\", \"mmla(f32,bf16,bf16)\", \"FLOPS\",\n 0x10000000LL, 768LL, asimd_mmla_fp32bf16bf16);\n reg_new_isa(\"bf16\", \"dp2a.vs(f32,bf16,bf16)\", \"FLOPS\",\n 0x10000000LL, 384LL, asimd_dp2a_vs_fp32bf16bf16);\n reg_new_isa(\"bf16\", \"dp2a.vv(f32,bf16,bf16)\", \"FLOPS\",\n 0x10000000LL, 384LL, asimd_dp2a_vv_fp32bf16bf16);\n#endif\n\n#ifdef _ASIMD_HP_\n reg_new_isa(\"asimd_hp\", \"fmla.vs(fp16,fp16,fp16)\", \"FLOPS\",\n 0x10000000LL, 384LL, asimd_fmla_vs_fp16fp16fp16);\n reg_new_isa(\"asimd_hp\", \"fmla.vv(fp16,fp16,fp16)\", \"FLOPS\",\n 0x10000000LL, 384LL, asimd_fmla_vv_fp16fp16fp16);\n#endif\n\n#ifdef _ASIMD_\n reg_new_isa(\"asimd\", \"fmla.vs(f32,f32,f32)\", \"FLOPS\",\n 0x10000000LL, 192LL, asimd_fmla_vs_f32f32f32);\n reg_new_isa(\"asimd\", \"fmla.vv(f32,f32,f32)\", \"FLOPS\",\n 0x10000000LL, 192LL, asimd_fmla_vv_f32f32f32);\n reg_new_isa(\"asimd\", \"fmla.vs(f64,f64,f64)\", \"FLOPS\",\n 0x10000000LL, 96LL, asimd_fmla_vs_f64f64f64);\n reg_new_isa(\"asimd\", \"fmla.vv(f64,f64,f64)\", \"FLOPS\",\n 0x10000000LL, 96LL, asimd_fmla_vv_f64f64f64);\n#endif\n}\n\nint main(int argc, char *argv[])\n{\n vector set_of_threads;\n uint32_t idle_time = 0;\n\n bool params_enough = false;\n\n int i;\n for (i = 1; i < argc; i++)\n {\n if (strncmp(argv[i], \"--thread_pool=\", 14) == 0)\n {\n parse_thread_pool(argv[i] + 14, set_of_threads);\n params_enough = true;\n }\n else if (strncmp(argv[i], \"--idle_time=\", 12) == 0)\n {\n idle_time = (uint32_t)atoi(argv[i] + 12);\n }\n }\n if (!params_enough)\n {\n fprintf(stderr, \"Error: You must set --thread_pool parameter.\\n\");\n fprintf(stderr, \"You may also set --idle_time parameter.\\n\");\n fprintf(stderr, \"Usage: %s --thread_pool=[xxx] --idle_time=yyy\\n\", argv[0]);\n fprintf(stderr, \"[xxx] indicates all cores to benchmark.\\n\");\n fprintf(stderr, \"Example: [0,3,5-8,13-15].\\n\");\n fprintf(stderr, \"idle_time is the interval time(s) between every two benchmarks.\\n\");\n fprintf(stderr, \"idle_time parameter can be ignored, the default value is 0s.\\n\");\n fprintf(stderr, \"Notice: there must NOT be any spaces.\\n\");\n exit(0);\n }\n\n cpufp_register_isa();\n cpubm_do_bench(set_of_threads, idle_time);\n\n return 0;\n}\n\n" }, { "path": "arm64/cpuid.c", "content": "#include \n#include \n#ifndef __APPLE__\n#include \n#include \n#else\n#include \n#include \n#include \n#include \n#endif\n\nint main()\n{\n#ifndef __APPLE__\n uint64_t hwcaps = getauxval(AT_HWCAP);\n\n#ifdef HWCAP2_I8MM\n if (hwcaps & HWCAP2_I8MM)\n {\n printf(\"_I8MM_\\n\");\n }\n#endif\n\n#ifdef HWCAP2_BF16\n if (hwcaps & HWCAP2_BF16)\n {\n printf(\"_BF16_\\n\");\n }\n#endif\n\n#ifdef HWCAP_ASIMDDP\n if (hwcaps & HWCAP_ASIMDDP)\n {\n printf(\"_ASIMD_DP_\\n\");\n }\n#endif\n\n#ifdef HWCAP_ASIMDHP\n if (hwcaps & HWCAP_ASIMDHP)\n {\n printf(\"_ASIMD_HP_\\n\");\n }\n#endif\n\n#ifdef HWCAP_ASIMD\n if (hwcaps & HWCAP_ASIMD)\n {\n printf(\"_ASIMD_\\n\");\n }\n#endif\n#else\n size_t size = 4;\n uint32_t res;\n\n sysctlbyname(\"hw.optional.arm.FEAT_I8MM\", &res, &size, NULL, 0);\n if (res == 1) {\n printf(\"_I8MM_\\n\");\n }\n\n sysctlbyname(\"hw.optional.arm.FEAT_BF16\", &res, &size, NULL, 0);\n if (res == 1) {\n printf(\"_BF16_\\n\");\n }\n\n sysctlbyname(\"hw.optional.arm.FEAT_DotProd\", &res, &size, NULL, 0);\n if (res == 1) {\n printf(\"_ASIMD_DP_\\n\");\n }\n\n sysctlbyname(\"hw.optional.AdvSIMD_HPFPCv\", &res, &size, NULL, 0);\n if (res == 1) {\n printf(\"_ASIMD_HP_\\n\");\n }\n\n sysctlbyname(\"hw.optional.AdvSIMD\", &res, &size, NULL, 0);\n if (res == 1) {\n printf(\"_ASIMD_\\n\");\n }\n#endif\n\n return 0;\n}\n" }, { "path": "benchmark_result/arm64/AWS_Graviton_3E.md", "content": "# AWS Graviton 3E\n\nArchitecture: Neoverse V1\n\nSetting: Virtual 1 Core\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 332.34 GGOPS     |\n| i8mm            | mmla(u32,u8,u8)         | 332.46 GGOPS     |\n| i8mm            | mmla(s32,u8,s8)         | 332.46 GGOPS     |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 166.23 GGOPS     |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 166.17 GGOPS     |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 166.14 GGOPS     |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 166.18 GGOPS     |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 166.22 GGOPS     |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 166.22 GGOPS     |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 166.22 GGOPS     |\n| bf16            | mmla(f32,bf16,bf16)     | 166.18 GGFLOPS   |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 83.085 GGFLOPS   |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 83.111 GGFLOPS   |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 83.105 GGFLOPS   |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 83.113 GGFLOPS   |\n| asimd           | fmla.vs(f32,f32,f32)    | 41.549 GGFLOPS   |\n| asimd           | fmla.vv(f32,f32,f32)    | 41.542 GGFLOPS   |\n| asimd           | fmla.vs(f64,f64,f64)    | 35.96 GGFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 20.779 GGFLOPS   |\n----------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/arm64/Apple_Silicon_M2_Max.md", "content": "# Apple M2 Max (Macbook Pro 16)\n\nSetting: 8 Avalanche P-Cores + 4 Blizzard E-Cores\n\nOS: MacOS 15.1\n\nFor 1 P-core:\n\n
\n> ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\nWarning: cpu thread policy is not supported by OS\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 347.22 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 353.72 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 361.84 GOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 426.77 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 418.49 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 436.31 GOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 425.79 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 420.44 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 430.16 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 425.55 GOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 51.959 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 53.449 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 53.995 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 215.06 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 210.01 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 105.54 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 107.27 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 54.109 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 51.883 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 8 P-cores:\n\n
\n> ./cpufp --thread_pool=[0-7]\nNumber Threads: 8\nThread Pool Binding: 0 1 2 3 4 5 6 7\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 2.5416 TOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 2.2677 TOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 2.6085 TOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 3.0364 TOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 3.0657 TOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 3.1035 TOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 2.9913 TOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 3.0582 TOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 2.9646 TOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 2.3463 TOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 384.6 GFLOPS     |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 375.38 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 369.55 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 1.5043 TFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 1.5192 TFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 763 GFLOPS       |\n| asimd           | fmla.vv(f32,f32,f32)    | 765.33 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 377.3 GFLOPS     |\n| asimd           | fmla.vv(f64,f64,f64)    | 377.05 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 1 E-core:\n\n
\n> taskpolicy -c background ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\nWarning: cpu thread policy is not supported by OS\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 101.41 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 97.71 GOPS       |\n| i8mm            | mmla(s32,u8,s8)         | 100.49 GOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 101.54 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 96.847 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 98.375 GOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 102.21 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 95.13 GOPS       |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 98.558 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 102.73 GOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 12.526 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 11.987 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 11.877 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 50.557 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 51.691 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 23.584 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 23.78 GFLOPS     |\n| asimd           | fmla.vs(f64,f64,f64)    | 12.689 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 12.744 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 4 E-cores (OS is running and therefore using some of them):\n\n
\n> taskpolicy -c background ./cpufp --thread_pool=[0-3]\nNumber Threads: 4\nThread Pool Binding: 0 1 2 3\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 292.61 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 278.35 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 288.3 GOPS       |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 315.5 GOPS       |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 312.98 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 245.39 GOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 205.68 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 267.14 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 320.75 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 279.87 GOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 37.858 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 36.48 GFLOPS     |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 35.658 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 145.14 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 140.57 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 74.868 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 78.191 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 40.488 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 36.496 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 8 P-cores and 4 E-cores:\n\n
\n> ./cpufp --thread_pool=[0-11]\nNumber Threads: 12\nThread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 2.3888 TOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 2.4141 TOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 2.2572 TOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 2.7256 TOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 2.4714 TOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 2.6389 TOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 2.7067 TOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 2.626 TOPS       |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 2.7011 TOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 2.6723 TOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 345.83 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 341.14 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 340.41 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 1.3411 TFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 1.2838 TFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 645.88 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 668.01 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 339.89 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 337.88 GFLOPS    |\n----------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/arm64/Apple_Silicon_M4_Max.md", "content": "# Apple M4 Max (Macbook Pro 16)\n\nSetting: 12 P-Cores + 4 E-Cores\n\nOS: MacOS 15.1\n\nFor 1 P-core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\nWarning: cpu thread policy is not supported by OS\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 477.42 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 477.76 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 478.18 GOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 472.27 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 472.34 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 472.57 GOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 472.39 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 472.39 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 472.66 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 472.7 GOPS       |\n| bf16            | mmla(f32,bf16,bf16)     | 71.964 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 71.942 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 71.915 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 233.67 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 236.39 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 116.7 GFLOPS     |\n| asimd           | fmla.vv(f32,f32,f32)    | 118.4 GFLOPS     |\n| asimd           | fmla.vs(f64,f64,f64)    | 58.344 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 59.124 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 12 P-cores:\n\n
\n$ ./cpufp --thread_pool=[0-11]\nNumber Threads: 12\nThread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 4.9542 TOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 4.9557 TOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 4.9335 TOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 4.8965 TOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 4.8873 TOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 4.896 TOPS       |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 4.891 TOPS       |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 4.8954 TOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 4.8983 TOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 4.8943 TOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 745.35 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 745.37 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 745.28 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 2.4183 TFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 2.4491 TFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 1.208 TFLOPS     |\n| asimd           | fmla.vv(f32,f32,f32)    | 1.2245 TFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 604.22 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 612.65 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 1 E-core:\n\n
\n$ taskpolicy -c background ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\nWarning: cpu thread policy is not supported by OS\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 66.327 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 68.298 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 75.25 GOPS       |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 65.959 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 66.819 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 69.26 GOPS       |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 67.005 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 66.623 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 64.867 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 65.323 GOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 11.234 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 11.222 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 11.242 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 32.67 GFLOPS     |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 33.329 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 16.367 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 16.262 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 8.1371 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 8.5853 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 4 E-cores (OS is running and therefore using some of them):\n\n
\n$ taskpolicy -c background ./cpufp --thread_pool=[0-3]\nNumber Threads: 4\nThread Pool Binding: 0 1 2 3\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 245.5 GOPS       |\n| i8mm            | mmla(u32,u8,u8)         | 254.44 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 254.65 GOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 250.63 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 254.65 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 254.88 GOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 247.45 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 255.69 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 254.06 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 253.43 GOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 42.842 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 43.632 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 43.273 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 126.73 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 132.21 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 65.895 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 63.022 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 31.509 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 31.543 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 12 P-cores + 4 E-cores:\n\n
\n$ ./cpufp --thread_pool=[0-15]\nNumber Threads: 16\nThread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\nWarning: cpu thread policy is not supported by OS\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 5.4673 TOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 5.5309 TOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 5.5254 TOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 5.4348 TOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 5.4187 TOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 5.4255 TOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 5.4434 TOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 5.4171 TOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 5.4069 TOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 5.3969 TOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 844.34 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 843.35 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 841.86 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 2.6914 TFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 2.735 TFLOPS     |\n| asimd           | fmla.vs(f32,f32,f32)    | 1.3444 TFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 1.3631 TFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 673.16 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 678.52 GFLOPS    |\n----------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/arm64/Broadcom_BCM2711.md", "content": "# Broadcom BCM2711(RaspBerry Pi 4)\n\nSetting: 4 Cortex-A72 Cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n-------------------------------------------------------------\n| Instruction Set | Core Computation     | Peak Performance |\n| asimd           | fmla.vs(f32,f32,f32) | 11.958 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32) | 11.958 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64) | 5.9792 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64) | 5.9792 GFLOPS    |\n-------------------------------------------------------------\n
\n\nFor 4 cores:\n\n
\n$ ./cpufp --thread_pool=[0-3]\nNumber Threads: 4\nThread Pool Binding: 0 1 2 3\n-------------------------------------------------------------\n| Instruction Set | Core Computation     | Peak Performance |\n| asimd           | fmla.vs(f32,f32,f32) | 47.883 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32) | 47.88 GFLOPS     |\n| asimd           | fmla.vs(f64,f64,f64) | 23.933 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64) | 23.943 GFLOPS    |\n-------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/arm64/Broadcom_BCM2712.md", "content": "# Broadcom BCM2712(RaspBerry Pi 5)\n\nSetting: 4 Cortex-A76 Cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 153.48 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 153.48 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 153.47 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 153.48 GOPS      |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 76.738 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 76.738 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 38.369 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 38.369 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 19.185 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 19.185 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 4 cores:\n\n
\n$ ./cpufp --thread_pool=[0-3]\nNumber Threads: 4\nThread Pool Binding: 0 1 2 3\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 613.79 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 614.02 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 613.98 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 613.99 GOPS      |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 306.88 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 306.98 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 153.48 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 153.5 GFLOPS     |\n| asimd           | fmla.vs(f64,f64,f64)    | 74.513 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 76.751 GFLOPS    |\n----------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/arm64/CIX_P1_CD8180.md", "content": "# CIX P1 CD8180(Radxa Orion O6)\n\nSettings: \nCortex-A720 @ 2.5GHz: 0,11 \nCortex-A720 @ 2.4GHz: 9,10 \nCortex-A720 @ 2.3GHz: 5,6 \nCortex-A720 @ 2.2GHz: 7,8 \nCortex-A520 @ 1.8GHz: 1-4\n\nPower policy: Balance\n\nFor single P-Core @ 2.5GHz:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 319.69 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 319.71 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 319.71 GOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 159.86 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 159.88 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 159.85 GOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 159.87 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 159.89 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 159.87 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 159.89 GOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 159.9 GFLOPS     |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 79.947 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 79.949 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 79.948 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 79.944 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 39.971 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 39.972 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 19.985 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 19.984 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 2 P-Cores @ 2.5GHz:\n\n
\n$ ./cpufp --thread_pool=[0,11]\nNumber Threads: 2\nThread Pool Binding: 0 11\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 638.37 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 639.22 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 639.3 GOPS       |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 319.61 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 319.58 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 319.69 GOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 319.67 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 319.61 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 319.6 GOPS       |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 319.65 GOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 319.64 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 159.87 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 159.86 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 159.85 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 159.85 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 79.899 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 79.935 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 39.956 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 39.963 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor single P-Core @ 2.4GHz:\n\n
\n$ ./cpufp --thread_pool=[9]\nNumber Threads: 1\nThread Pool Binding: 9\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 306.95 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 306.94 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 306.98 GOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 153.47 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 153.46 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 153.48 GOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 153.46 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 153.46 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 153.48 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 153.47 GOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 153.49 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 76.745 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 76.732 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 76.734 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 76.75 GFLOPS     |\n| asimd           | fmla.vs(f32,f32,f32)    | 38.369 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 38.367 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 19.186 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 19.185 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 2 P-Cores @ 2.4GHz:\n\n
\n$ ./cpufp --thread_pool=[9,10]\nNumber Threads: 2\nThread Pool Binding: 9 10\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 613.78 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 613.84 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 613.84 GOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 306.92 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 306.9 GOPS       |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 306.95 GOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 306.92 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 306.89 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 306.94 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 306.93 GOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 306.9 GFLOPS     |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 153.47 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 153.46 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 153.45 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 153.46 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 76.725 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 76.726 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 38.368 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 38.364 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor single P-Core @ 2.3GHz:\n\n
\n$ ./cpufp --thread_pool=[5]\nNumber Threads: 1\nThread Pool Binding: 5\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 294.17 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 294.15 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 294.14 GOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 147.07 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 147.08 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 147.07 GOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 147.07 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 147.07 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 147.07 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 147.08 GOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 147.07 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 73.532 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 73.539 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 73.541 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 73.537 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 36.768 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 36.772 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 18.383 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 18.384 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 2 P-Cores @ 2.3GHz:\n\n
\n$ ./cpufp --thread_pool=[5,6]\nNumber Threads: 2\nThread Pool Binding: 5 6\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 586.66 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 587.38 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 587.83 GOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 293.61 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 293.87 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 293.46 GOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 293.87 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 293.94 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 293.91 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 293.86 GOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 293.81 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 146.88 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 146.91 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 146.94 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 146.84 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 73.442 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 73.456 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 36.735 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 36.728 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor single P-Core @ 2.2GHz:\n\n
\n$ ./cpufp --thread_pool=[7]\nNumber Threads: 1\nThread Pool Binding: 7\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 281.34 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 281.37 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 281.35 GOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 140.67 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 140.68 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 140.68 GOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 140.68 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 140.7 GOPS       |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 140.69 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 140.69 GOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 140.67 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 70.338 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 70.335 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 70.346 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 70.345 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 35.169 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 35.172 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 17.587 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 17.585 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 2 P-Cores @ 2.2GHz:\n\n
\n$ ./cpufp --thread_pool=[7,8]\nNumber Threads: 2\nThread Pool Binding: 7 8\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 562.68 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 562.69 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 562.75 GOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 281.34 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 281.32 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 281.32 GOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 281.32 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 281.36 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 281.38 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 281.36 GOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 281.34 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 140.68 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 140.67 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 140.67 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 140.69 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 70.344 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 70.342 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 35.171 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 35.17 GFLOPS     |\n----------------------------------------------------------------\n
\n\nFor single E-core @ 1.8GHz:\n\n
\n$ ./cpufp --thread_pool=[1]\nNumber Threads: 1\nThread Pool Binding: 1\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 114.83 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 114.82 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 114.81 GOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 57.415 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 57.414 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 57.417 GOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 57.411 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 57.417 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 57.418 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 57.415 GOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 22.967 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 28.706 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 28.708 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 28.703 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 28.708 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 14.354 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 14.353 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 7.1768 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 7.1766 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 4 E-Cores @ 1.8GHz:\n\n
\n$ ./cpufp --thread_pool=[1-4]\nNumber Threads: 4\nThread Pool Binding: 1 2 3 4\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 402.75 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 402.79 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 402.79 GOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 201.37 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 201.35 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 201.35 GOPS      |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 201.37 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 201.29 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 201.35 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 201.36 GOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 80.555 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 100.68 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 100.66 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 100.68 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 100.7 GFLOPS     |\n| asimd           | fmla.vs(f32,f32,f32)    | 50.355 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 50.348 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 25.172 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 25.172 GFLOPS    |\n----------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/arm64/HUAWEI_Kunpeng_920_7260.md", "content": "# HUAWEI Kunpeng 920 7260\n\nArchitecture: Taishan V110\n\nSetting: 2 * 64 cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[1]\nNumber Threads: 1\nThread Pool Binding: 1\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 166.3 GOPS       |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 166.32 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 166.31 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 166.29 GOPS      |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 83.161 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 83.151 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 41.576 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 41.579 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 10.395 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 10.394 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 32 cores:\n\n
\n$ ./cpufp --thread_pool=[0-31]\nNumber Threads: 32\nThread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 5.304 TOPS       |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 5.3108 TOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 5.307 TOPS       |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 5.3123 TOPS      |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 2.6555 TFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 2.6564 TFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 1.3252 TFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 1.328 TFLOPS     |\n| asimd           | fmla.vs(f64,f64,f64)    | 331.95 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 331.98 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 64 cores:\n\n
\n$ ./cpufp --thread_pool=[0-63]\nNumber Threads: 64\nThread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 10.601 TOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 10.586 TOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 10.587 TOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 10.593 TOPS      |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 5.2966 TFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 5.2975 TFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 2.6551 TFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 2.6557 TFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 663.98 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 663.73 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 128 cores:\n\n
\n$ ./cpufp --thread_pool=[0-127]\nNumber Threads: 128\nThread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 20.951 TOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 20.27 TOPS       |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 19.736 TOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 16.495 TOPS      |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 10.481 TFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 10.514 TFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 5.1993 TFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 4.117 TFLOPS     |\n| asimd           | fmla.vs(f64,f64,f64)    | 1.2754 TFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 1.049 TFLOPS     |\n----------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/arm64/HUAWEI_Kunpeng_D920_2249K.md", "content": "# HUAWEI Kunpeng D920 2249K\n\nArchitecture: Taishan V110\n\nSetting: 8 cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 166.21 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 166.21 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 166.21 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 166.2 GOPS       |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 83.104 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 83.104 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 41.553 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 41.553 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 10.388 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 10.388 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 8 cores:\n\n
\n$ ./cpufp --thread_pool=[0-7]\nNumber Threads: 8\nThread Pool Binding: 0 1 2 3 4 5 6 7\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 1.3132 TOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 1.3014 TOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 1.3034 TOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 1.3016 TOPS      |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 651.87 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 652.34 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 326.4 GFLOPS     |\n| asimd           | fmla.vv(f32,f32,f32)    | 326.12 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 81.791 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 81.503 GFLOPS    |\n----------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/arm64/Phytium_D2000.md", "content": "# Phytium D2000/8\n\nSetting: 8 FTC663 Cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n-------------------------------------------------------------\n| Instruction Set | Core Computation     | Peak Performance |\n| asimd           | fmla.vs(f32,f32,f32) | 18.376 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32) | 18.375 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64) | 9.1877 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64) | 9.1891 GFLOPS    |\n-------------------------------------------------------------\n
\n\nFor 4 cores:\n\n
\n$ ./cpufp --thread_pool=[0-3]\nNumber Threads: 4\nThread Pool Binding: 0 1 2 3\n-------------------------------------------------------------\n| Instruction Set | Core Computation     | Peak Performance |\n| asimd           | fmla.vs(f32,f32,f32) | 73.51 GFLOPS     |\n| asimd           | fmla.vv(f32,f32,f32) | 73.51 GFLOPS     |\n| asimd           | fmla.vs(f64,f64,f64) | 36.755 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64) | 36.747 GFLOPS    |\n-------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/arm64/Qualcomm_Snapdragon_X_Elite_X1E80100.md", "content": "# Qualcomm Snapdragon X Elite - X1E80100\n\nArchitecture: Oryon-1\n\nSetting: 4 E-cores @ 3.4Ghz + 8 P-cores @ 4.0Ghz\n\nFor single core:\n\n
\n> .\\cpufp.exe --thread_pool=[4]\nNumber Threads: 1\nThread Pool Binding: 4\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 442.36 GOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 434.67 GOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 437.35 GOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 520.02 GOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 525.78 GOPS      |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 515.6 GOPS       |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 510.91 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 516.89 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 518 GOPS         |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 514.3 GOPS       |\n| bf16            | mmla(f32,bf16,bf16)     | 223.53 GFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 256.44 GFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 252.13 GFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 260.4 GFLOPS     |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 259.04 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 127.29 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 125.67 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 65.2 GFLOPS      |\n| asimd           | fmla.vv(f64,f64,f64)    | 65.195 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 12 cores:\n\n
\n> .\\cpufp.exe --thread_pool=[0-11]\nNumber Threads: 12\nThread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| i8mm            | mmla(s32,s8,s8)         | 4.3971 TOPS      |\n| i8mm            | mmla(u32,u8,u8)         | 4.3813 TOPS      |\n| i8mm            | mmla(s32,u8,s8)         | 4.3889 TOPS      |\n| i8mm            | dp4a.vs(s32,s8,u8)      | 5.1953 TOPS      |\n| i8mm            | dp4a.vs(s32,u8,s8)      | 5.221 TOPS       |\n| i8mm            | dp4a.vv(s32,u8,s8)      | 5.209 TOPS       |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 5.2081 TOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 5.2275 TOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 5.222 TOPS       |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 5.2146 TOPS      |\n| bf16            | mmla(f32,bf16,bf16)     | 2.2578 TFLOPS    |\n| bf16            | dp2a.vs(f32,bf16,bf16)  | 2.6124 TFLOPS    |\n| bf16            | dp2a.vv(f32,bf16,bf16)  | 2.6172 TFLOPS    |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 2.6051 TFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 2.6035 TFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 1.3028 TFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 1.3032 TFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 654.67 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 654.44 GFLOPS    |\n----------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/arm64/RockChip_RK3399.md", "content": "# Rockchip RK3399\n\nSetting: 2 Cortex-A72(big) Cores + 4 Cortex-A53(Little) Cores\n\nFor single Little core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n-------------------------------------------------------------\n| Instruction Set | Core Computation     | Peak Performance |\n| asimd           | fmla.vs(f32,f32,f32) | 11.255 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32) | 11.255 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64) | 5.6275 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64) | 5.6277 GFLOPS    |\n-------------------------------------------------------------\n
\n\nFor 4 Little cores:\n\n
\n$ ./cpufp --thread_pool=[0-3]\nNumber Threads: 4\nThread Pool Binding: 0 1 2 3\n-------------------------------------------------------------\n| Instruction Set | Core Computation     | Peak Performance |\n| asimd           | fmla.vs(f32,f32,f32) | 45.029 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32) | 45.027 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64) | 22.509 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64) | 22.513 GFLOPS    |\n-------------------------------------------------------------\n
\n\nFor single big core:\n\n
\n$ ./cpufp --thread_pool=[4]\nNumber Threads: 1\nThread Pool Binding: 4\n-------------------------------------------------------------\n| Instruction Set | Core Computation     | Peak Performance |\n| asimd           | fmla.vs(f32,f32,f32) | 14.348 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32) | 14.348 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64) | 7.1744 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64) | 7.1743 GFLOPS    |\n-------------------------------------------------------------\n
\n\nFor 2 big cores:\n\n
\n$ ./cpufp --thread_pool=[4,5]\nNumber Threads: 2\nThread Pool Binding: 4 5\n-------------------------------------------------------------\n| Instruction Set | Core Computation     | Peak Performance |\n| asimd           | fmla.vs(f32,f32,f32) | 28.698 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32) | 28.698 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64) | 14.349 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64) | 14.347 GFLOPS    |\n-------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/arm64/RockChip_RK3588.md", "content": "# RockChip RK3588\n\nSetting: 4 Cortex-A76(big) Cores + 4 Cortex-A55(Little) Cores\n\nFor single Little core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 58.379 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 58.371 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 58.369 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 58.382 GOPS      |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 29.193 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 29.192 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 14.593 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 14.596 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 7.2971 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 7.2972 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 4 Little cores:\n\n
\n$ ./cpufp --thread_pool=[0-3]\nNumber Threads: 4\nThread Pool Binding: 0 1 2 3\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 233.08 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 233.05 GOPS      |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 233.06 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 233.05 GOPS      |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 116.54 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 116.51 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 58.261 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 58.258 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 29.13 GFLOPS     |\n| asimd           | fmla.vv(f64,f64,f64)    | 29.126 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor single big core:\n\n
\n$ ./cpufp --thread_pool=[4]\nNumber Threads: 1\nThread Pool Binding: 4\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 152.1 GOPS       |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 152.1 GOPS       |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 152.06 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 152.08 GOPS      |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 76.022 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 76.027 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 38.012 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 38.008 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 19.004 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 19.004 GFLOPS    |\n----------------------------------------------------------------\n
\n\nFor 4 big cores:\n\n
\n$ ./cpufp --thread_pool=[4-7]\nNumber Threads: 4\nThread Pool Binding: 4 5 6 7\n----------------------------------------------------------------\n| Instruction Set | Core Computation        | Peak Performance |\n| asimd_dp        | dp4a.vs(s32,s8,s8)      | 601.71 GOPS      |\n| asimd_dp        | dp4a.vv(s32,s8,s8)      | 602.2 GOPS       |\n| asimd_dp        | dp4a.vs(u32,u8,u8)      | 602.22 GOPS      |\n| asimd_dp        | dp4a.vv(u32,u8,u8)      | 602.2 GOPS       |\n| asimd_hp        | fmla.vs(fp16,fp16,fp16) | 300.97 GFLOPS    |\n| asimd_hp        | fmla.vv(fp16,fp16,fp16) | 300.93 GFLOPS    |\n| asimd           | fmla.vs(f32,f32,f32)    | 149.79 GFLOPS    |\n| asimd           | fmla.vv(f32,f32,f32)    | 150.15 GFLOPS    |\n| asimd           | fmla.vs(f64,f64,f64)    | 75.222 GFLOPS    |\n| asimd           | fmla.vv(f64,f64,f64)    | 75.215 GFLOPS    |\n----------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/e2k/Elbrus_4C.md", "content": "# Elbrus-4C\n\nSetting: 4 Sockets x 4 Elbrus-v3\n\nFreqency: 750 MHz\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| v1              | ADD(MUL(f32,f32),f32) | 11.939 GFLOPS    |\n| v1              | ADD(MUL(f64,f64),f64) | 5.9801 GFLOPS    |\n--------------------------------------------------------------\n
\n\nFor 4 cores:\n\n
\n$ ./cpufp --thread_pool=[0-3]\nNumber Threads: 4\nThread Pool Binding: 0 1 2 3\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| v1              | ADD(MUL(f32,f32),f32) | 47.704 GFLOPS    |\n| v1              | ADD(MUL(f64,f64),f64) | 23.913 GFLOPS    |\n--------------------------------------------------------------\n
\n\nFor 16 cores:\n\n
\n$ ./cpufp --thread_pool=[0-15]\nNumber Threads: 16\nThread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| v1              | ADD(MUL(f32,f32),f32) | 189.81 GFLOPS    |\n| v1              | ADD(MUL(f64,f64),f64) | 95.294 GFLOPS    |\n--------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/e2k/Elbrus_8C.md", "content": "# Elbrus-8C\n\nSetting: 4 Sockets x 8 Elbrus-v4\n\nFrequency: 1.2 GHz\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| v4              | ADD(MUL(f32,f32),f32) | 28.704 GFLOPS    |\n| v4              | ADD(MUL(f64,f64),f64) | 14.353 GFLOPS    |\n--------------------------------------------------------------\n
\n\nFor 8 cores:\n\n
\n$ ./cpufp --thread_pool=[0-7]\nNumber Threads: 8\nThread Pool Binding: 0 1 2 3 4 5 6 7\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| v4              | ADD(MUL(f32,f32),f32) | 229.42 GFLOPS    |\n| v4              | ADD(MUL(f64,f64),f64) | 114.56 GFLOPS    |\n--------------------------------------------------------------\n
\n\nFor 32 cores:\n\n
\n$ ./cpufp --thread_pool=[0-31]\nNumber Threads: 32\nThread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| v4              | ADD(MUL(f32,f32),f32) | 896.58 GFLOPS    |\n| v4              | ADD(MUL(f64,f64),f64) | 448.7 GFLOPS     |\n--------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/e2k/Elbrus_8C2.md", "content": "# Elbrus-8C2\n\nSetting: 4 Sockets x 8 Elbrus-v5\n\nFrequency: 1.2 GHz\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| v5              | ADD(MUL(f32,f32),f32) | 57.413 GFLOPS    |\n| v5              | ADD(MUL(f64,f64),f64) | 28.707 GFLOPS    |\n| v4              | ADD(MUL(f32,f32),f32) | 28.727 GFLOPS    |\n| v4              | ADD(MUL(f64,f64),f64) | 14.353 GFLOPS    |\n--------------------------------------------------------------\n
\n\nFor 8 cores:\n\n
\n$ ./cpufp --thread_pool=[0-7]\nNumber Threads: 8\nThread Pool Binding: 0 1 2 3 4 5 6 7\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| v5              | ADD(MUL(f32,f32),f32) | 459.61 GFLOPS    |\n| v5              | ADD(MUL(f64,f64),f64) | 229.72 GFLOPS    |\n| v4              | ADD(MUL(f32,f32),f32) | 229.76 GFLOPS    |\n| v4              | ADD(MUL(f64,f64),f64) | 114.89 GFLOPS    |\n--------------------------------------------------------------\n
\n\nFor 32 cores:\n\n
\n$ ./cpufp --thread_pool=[0-31]\nNumber Threads: 32\nThread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| v5              | ADD(MUL(f32,f32),f32) | 1.835 TFLOPS     |\n| v5              | ADD(MUL(f64,f64),f64) | 917.64 GFLOPS    |\n| v4              | ADD(MUL(f32,f32),f32) | 917.56 GFLOPS    |\n| v4              | ADD(MUL(f64,f64),f64) | 458.77 GFLOPS    |\n--------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/loongarch64/Loongson_3A5000M.md", "content": "# Loongson 3A5000M\n\nSetting: 4 LA464 Cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n-------------------------------------------------------------------------------\n| Instruction Set | Core Computation                       | Peak Performance |\n| LASX            | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 47.831 GFLOPS    |\n| LASX            | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 23.888 GFLOPS    |\n| LSX             | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 23.918 GFLOPS    |\n| LSX             | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 11.957 GFLOPS    |\n| FP_SP           | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 5.9803 GFLOPS    |\n| FP_DP           | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 5.9803 GFLOPS    |\n-------------------------------------------------------------------------------\n
\n\nFor 4 cores:\n\n
\n$ ./cpufp --thread_pool=[0-3]\nNumber Threads: 4\nThread Pool Binding: 0 1 2 3\n-------------------------------------------------------------------------------\n| Instruction Set | Core Computation                       | Peak Performance |\n| LASX            | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 190.92 GFLOPS    |\n| LASX            | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 95.47 GFLOPS     |\n| LSX             | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 95.184 GFLOPS    |\n| LSX             | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 47.652 GFLOPS    |\n| FP_SP           | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 23.847 GFLOPS    |\n| FP_DP           | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 23.876 GFLOPS    |\n-------------------------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/loongarch64/Loongson_3A6000.md", "content": "# Loongson 3A6000\n\nSetting: 4 LA664 Cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n------------------------------------------------------------------------------\n| Instruction Set | Vector Length | Core Computation      | Peak Performance |\n|-----------------|---------------|-----------------------|------------------|\n| LASX            | 256b          | fmadd(f32,f32,f32)    | 79.781 GFLOPS    |\n| LASX            | 256b          | fmadd(f64,f64,f64)    | 39.939 GFLOPS    |\n| LASX            | 256b          | add(mul(f32,f32),f32) | 79.853 GFLOPS    |\n| LASX            | 256b          | add(mul(f64,f64),f64) | 39.937 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| LSX             | 128b          | fmadd(f32,f32,f32)    | 39.916 GFLOPS    |\n| LSX             | 128b          | fmadd(f64,f64,f64)    | 19.97 GFLOPS     |\n| LSX             | 128b          | add(mul(f32,f32),f32) | 39.935 GFLOPS    |\n| LSX             | 128b          | add(mul(f64,f64),f64) | 19.968 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| FP_SP           | scalar        | fmadd(f32,f32,f32)    | 9.9848 GFLOPS    |\n| FP_DP           | scalar        | fmadd(f64,f64,f64)    | 9.979 GFLOPS     |\n------------------------------------------------------------------------------\n
\n\nFor 4 cores:\n\n
\n$ ./cpufp --thread_pool=[0,2,4,6]\nNumber Threads: 4\nThread Pool Binding: 0 2 4 6\n------------------------------------------------------------------------------\n| Instruction Set | Vector Length | Core Computation      | Peak Performance |\n|-----------------|---------------|-----------------------|------------------|\n| LASX            | 256b          | fmadd(f32,f32,f32)    | 319.54 GFLOPS    |\n| LASX            | 256b          | fmadd(f64,f64,f64)    | 159.71 GFLOPS    |\n| LASX            | 256b          | add(mul(f32,f32),f32) | 319.15 GFLOPS    |\n| LASX            | 256b          | add(mul(f64,f64),f64) | 159.61 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| LSX             | 128b          | fmadd(f32,f32,f32)    | 159.75 GFLOPS    |\n| LSX             | 128b          | fmadd(f64,f64,f64)    | 79.876 GFLOPS    |\n| LSX             | 128b          | add(mul(f32,f32),f32) | 159.56 GFLOPS    |\n| LSX             | 128b          | add(mul(f64,f64),f64) | 79.751 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| FP_SP           | scalar        | fmadd(f32,f32,f32)    | 39.937 GFLOPS    |\n| FP_DP           | scalar        | fmadd(f64,f64,f64)    | 39.937 GFLOPS    |\n------------------------------------------------------------------------------\n
\n\n" }, { "path": "benchmark_result/loongarch64/Loongson_3C5000.md", "content": "# Loongson 3C5000\n\nSetting: 16 LA464 Cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n-------------------------------------------------------------------------------\n| Instruction Set | Core Computation                       | Peak Performance |\n| LASX            | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 52.603 GFLOPS    |\n| LASX            | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 26.331 GFLOPS    |\n| LSX             | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 26.323 GFLOPS    |\n| LSX             | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 13.166 GFLOPS    |\n| FP_SP           | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 6.583 GFLOPS     |\n| FP_DP           | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 6.5723 GFLOPS    |\n-------------------------------------------------------------------------------\n
\n\nFor 16 cores:\n\n
\n$ ./cpufp --thread_pool=[0-15]\nNumber Threads: 16\nThread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15\n-------------------------------------------------------------------------------\n| Instruction Set | Core Computation                       | Peak Performance |\n| LASX            | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 841.77 GFLOPS    |\n| LASX            | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 406.52 GFLOPS    |\n| LSX             | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 420.84 GFLOPS    |\n| LSX             | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 210.01 GFLOPS    |\n| FP_SP           | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 105.21 GFLOPS    |\n| FP_DP           | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 104.59 GFLOPS    |\n-------------------------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/riscv64/Kendryte_K230.md", "content": "# Kendryte K230\n\nSetting: 2 C908 Cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n---------------------------------------------------------------\n| Instruction Set | Core Computation       | Peak Performance |\n| vector          | vfmacc.vf(f16,f16,f16) | 25.014 GFLOPS    |\n| vector          | vfmacc.vv(f16,f16,f16) | 25.01 GFLOPS     |\n| vector          | vfmacc.vf(f32,f32,f32) | 12.507 GFLOPS    |\n| vector          | vfmacc.vv(f32,f32,f32) | 12.508 GFLOPS    |\n| vector          | vfmacc.vf(f64,f64,f64) | 6.254 GFLOPS     |\n| vector          | vfmacc.vv(f64,f64,f64) | 6.2541 GFLOPS    |\n---------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/riscv64/SpacemiT_K1.md", "content": "# SpacemiT K1\n\nSetting: 8 SpacemiT-X60 Cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n---------------------------------------------------------------\n| Instruction Set | Core Computation       | Peak Performance |\n| ime             | vmadot(s32,s8,s8)      | 511.53 GOPS      |\n| ime             | vmadotu(u32,u8,u8)     | 511.5 GOPS       |\n| ime             | vmadotus(s32,u8,s8)    | 511.53 GOPS      |\n| ime             | vmadotsu(s32,s8,u8)    | 511.51 GOPS      |\n| ime             | vmadotslide(s32,s8,s8) | 511.51 GOPS      |\n| vector          | vfmacc.vf(f16,f16,f16) | 66.722 GFLOPS    |\n| vector          | vfmacc.vv(f16,f16,f16) | 63.936 GFLOPS    |\n| vector          | vfmacc.vf(f32,f32,f32) | 33.36 GFLOPS     |\n| vector          | vfmacc.vv(f32,f32,f32) | 31.968 GFLOPS    |\n| vector          | vfmacc.vf(f64,f64,f64) | 16.679 GFLOPS    |\n| vector          | vfmacc.vv(f64,f64,f64) | 15.985 GFLOPS    |\n---------------------------------------------------------------\n
\n\nFor cluster 0(with ime extension), 4 cores:\n\n
\n$ ./cpufp --thread_pool=[0-3]\nNumber Threads: 4\nThread Pool Binding: 0 1 2 3\n---------------------------------------------------------------\n| Instruction Set | Core Computation       | Peak Performance |\n| ime             | vmadot(s32,s8,s8)      | 2.046 TOPS       |\n| ime             | vmadotu(u32,u8,u8)     | 2.0462 TOPS      |\n| ime             | vmadotus(s32,u8,s8)    | 2.0461 TOPS      |\n| ime             | vmadotsu(s32,s8,u8)    | 2.0462 TOPS      |\n| ime             | vmadotslide(s32,s8,s8) | 2.0461 TOPS      |\n| vector          | vfmacc.vf(f16,f16,f16) | 266.88 GFLOPS    |\n| vector          | vfmacc.vv(f16,f16,f16) | 255.75 GFLOPS    |\n| vector          | vfmacc.vf(f32,f32,f32) | 133.43 GFLOPS    |\n| vector          | vfmacc.vv(f32,f32,f32) | 127.85 GFLOPS    |\n| vector          | vfmacc.vf(f64,f64,f64) | 66.709 GFLOPS    |\n| vector          | vfmacc.vv(f64,f64,f64) | 63.935 GFLOPS    |\n---------------------------------------------------------------\n
\n\nFor 2 clusters, 8 cores:\n\n
\n$ ./cpufp --thread_pool=[0-7]\nNumber Threads: 8\nThread Pool Binding: 0 1 2 3 4 5 6 7\n---------------------------------------------------------------\n| Instruction Set | Core Computation       | Peak Performance |\n| vector          | vfmacc.vf(f16,f16,f16) | 533.65 GFLOPS    |\n| vector          | vfmacc.vv(f16,f16,f16) | 511.45 GFLOPS    |\n| vector          | vfmacc.vf(f32,f32,f32) | 266.89 GFLOPS    |\n| vector          | vfmacc.vv(f32,f32,f32) | 255.75 GFLOPS    |\n| vector          | vfmacc.vf(f64,f64,f64) | 133.42 GFLOPS    |\n| vector          | vfmacc.vv(f64,f64,f64) | 127.86 GFLOPS    |\n---------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/x64/AMD_Ryzen7_8845HS.md", "content": "# AMD Ryzen7 8845HS\n\nArchitecture: Zen4\n\nSetting: 8 Zen4 Cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| AVX512_VNNI     | DP4A(s32,u8,s8)       | 647.97 GOPS      |\n| AVX512_VNNI     | DP2A(s32,s16,s16)     | 324.27 GOPS      |\n| AVX512_BF16     | DP2A(f32,bf16,bf16)   | 324.92 GFLOPS    |\n| AVX512F         | FMA(f32,f32,f32)      | 163.58 GFLOPS    |\n| AVX512F         | FMA(f64,f64,f64)      | 81.786 GFLOPS    |\n| FMA             | FMA(f32,f32,f32)      | 163.57 GFLOPS    |\n| FMA             | FMA(f64,f64,f64)      | 81.785 GFLOPS    |\n| AVX             | ADD(MUL(f32,f32),f32) | 157.36 GFLOPS    |\n| AVX             | ADD(MUL(f64,f64),f64) | 79.045 GFLOPS    |\n| SSE             | ADD(MUL(f32,f32),f32) | 80.34 GFLOPS     |\n| SSE2            | ADD(MUL(f64,f64),f64) | 40.371 GFLOPS    |\n--------------------------------------------------------------\n
\n\nFor 8 cores:\n\n
\n$ ./cpufp --thread_pool=[0-7]\nNumber Threads: 8\nThread Pool Binding: 0 1 2 3 4 5 6 7\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| AVX512_VNNI     | DP4A(s32,u8,s8)       | 5113.8 GOPS      |\n| AVX512_VNNI     | DP2A(s32,s16,s16)     | 2559.1 GOPS      |\n| AVX512_BF16     | DP2A(f32,bf16,bf16)   | 2551.6 GFLOPS    |\n| AVX512F         | FMA(f32,f32,f32)      | 1283.6 GFLOPS    |\n| AVX512F         | FMA(f64,f64,f64)      | 641.21 GFLOPS    |\n| FMA             | FMA(f32,f32,f32)      | 1271.7 GFLOPS    |\n| FMA             | FMA(f64,f64,f64)      | 632.3 GFLOPS     |\n| AVX             | ADD(MUL(f32,f32),f32) | 1193.6 GFLOPS    |\n| AVX             | ADD(MUL(f64,f64),f64) | 590.85 GFLOPS    |\n| SSE             | ADD(MUL(f32,f32),f32) | 613.54 GFLOPS    |\n| SSE2            | ADD(MUL(f64,f64),f64) | 307.67 GFLOPS    |\n--------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/x64/AMD_Ryzen7_9700X.md", "content": "# AMD Ryzen7 9700X\n\nMicroarchitecture: Zen5\n\nSetting: 8 Zen5 Cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n------------------------------------------------------------------------------\n| Instruction Set | Vector Length | Core Computation      | Peak Performance |\n|-----------------|---------------|-----------------------|------------------|\n| AVX512_VNNI     | 512b          | DP4A(s32,u8,s8)       | 1.4172 TOPS      |\n| AVX512_VNNI     | 512b          | DP2A(s32,s16,s16)     | 708.61 GOPS      |\n| AVX512_BF16     | 512b          | DP2A(f32,bf16,bf16)   | 708.19 GFLOPS    |\n| AVX512F         | 512b          | FMA(f32,f32,f32)      | 354.29 GFLOPS    |\n| AVX512F         | 512b          | FMA(f64,f64,f64)      | 177.09 GFLOPS    |\n| AVX512F         | 512b          | ADD(MUL(f32,f32),f32) | 353.63 GFLOPS    |\n| AVX512F         | 512b          | ADD(MUL(f64,f64),f64) | 176.47 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| AVX512_VNNI     | 256b          | DP4A(s32,u8,s8)       | 708.55 GOPS      |\n| AVX_VNNI        | 256b          | DP4A(s32,u8,s8)       | 708.64 GOPS      |\n| AVX512_VNNI     | 256b          | DP2A(s32,s16,s16)     | 354.38 GOPS      |\n| AVX_VNNI        | 256b          | DP2A(s32,s16,s16)     | 354.22 GOPS      |\n| AVX512_BF16     | 256b          | DP2A(f32,bf16,bf16)   | 354.39 GFLOPS    |\n| FMA             | 256b          | FMA(f32,f32,f32)      | 177.14 GFLOPS    |\n| FMA             | 256b          | FMA(f64,f64,f64)      | 88.565 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f32,f32),f32) | 176.96 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f64,f64),f64) | 88.467 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| AVX512_VNNI     | 128b          | DP4A(s32,u8,s8)       | 354.53 GOPS      |\n| AVX_VNNI        | 128b          | DP4A(s32,u8,s8)       | 354.53 GOPS      |\n| AVX512_VNNI     | 128b          | DP2A(s32,s16,s16)     | 177.27 GOPS      |\n| AVX_VNNI        | 128b          | DP2A(s32,s16,s16)     | 177.24 GOPS      |\n| AVX512_BF16     | 128b          | DP2A(f32,bf16,bf16)   | 177.26 GFLOPS    |\n| FMA             | 128b          | FMA(f32,f32,f32)      | 88.641 GFLOPS    |\n| FMA             | 128b          | FMA(f64,f64,f64)      | 44.308 GFLOPS    |\n| SSE             | 128b          | ADD(MUL(f32,f32),f32) | 88.465 GFLOPS    |\n| SSE2            | 128b          | ADD(MUL(f64,f64),f64) | 44.259 GFLOPS    |\n------------------------------------------------------------------------------\n
\n\nFor 8 cores:\n\n
\n$ ./cpufp --thread_pool=[0-7]\nNumber Threads: 8\nThread Pool Binding: 0 1 2 3 4 5 6 7\n------------------------------------------------------------------------------\n| Instruction Set | Vector Length | Core Computation      | Peak Performance |\n|-----------------|---------------|-----------------------|------------------|\n| AVX512_VNNI     | 512b          | DP4A(s32,u8,s8)       | 11.064 TOPS      |\n| AVX512_VNNI     | 512b          | DP2A(s32,s16,s16)     | 5.5293 TOPS      |\n| AVX512_BF16     | 512b          | DP2A(f32,bf16,bf16)   | 5.5324 TFLOPS    |\n| AVX512F         | 512b          | FMA(f32,f32,f32)      | 2.7598 TFLOPS    |\n| AVX512F         | 512b          | FMA(f64,f64,f64)      | 1.3768 TFLOPS    |\n| AVX512F         | 512b          | ADD(MUL(f32,f32),f32) | 2.7312 TFLOPS    |\n| AVX512F         | 512b          | ADD(MUL(f64,f64),f64) | 1.3605 TFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| AVX512_VNNI     | 256b          | DP4A(s32,u8,s8)       | 5.5604 TOPS      |\n| AVX_VNNI        | 256b          | DP4A(s32,u8,s8)       | 5.5592 TOPS      |\n| AVX512_VNNI     | 256b          | DP2A(s32,s16,s16)     | 2.7816 TOPS      |\n| AVX_VNNI        | 256b          | DP2A(s32,s16,s16)     | 2.7783 TOPS      |\n| AVX512_BF16     | 256b          | DP2A(f32,bf16,bf16)   | 2.7814 TFLOPS    |\n| FMA             | 256b          | FMA(f32,f32,f32)      | 1.3884 TFLOPS    |\n| FMA             | 256b          | FMA(f64,f64,f64)      | 694.02 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f32,f32),f32) | 1.3781 TFLOPS    |\n| AVX             | 256b          | ADD(MUL(f64,f64),f64) | 688.82 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| AVX512_VNNI     | 128b          | DP4A(s32,u8,s8)       | 2.7881 TOPS      |\n| AVX_VNNI        | 128b          | DP4A(s32,u8,s8)       | 2.7881 TOPS      |\n| AVX512_VNNI     | 128b          | DP2A(s32,s16,s16)     | 1.3938 TOPS      |\n| AVX_VNNI        | 128b          | DP2A(s32,s16,s16)     | 1.3938 TOPS      |\n| AVX512_BF16     | 128b          | DP2A(f32,bf16,bf16)   | 1.3958 TFLOPS    |\n| FMA             | 128b          | FMA(f32,f32,f32)      | 696.63 GFLOPS    |\n| FMA             | 128b          | FMA(f64,f64,f64)      | 348.12 GFLOPS    |\n| SSE             | 128b          | ADD(MUL(f32,f32),f32) | 686.34 GFLOPS    |\n| SSE2            | 128b          | ADD(MUL(f64,f64),f64) | 344.64 GFLOPS    |\n------------------------------------------------------------------------------\n
\n\n" }, { "path": "benchmark_result/x64/AMD_Ryzen9_6900HX.md", "content": "# AMD Ryzen9 6900HX\n\nArchitecture: Zen3+\n\nSetting: 8 Zen3+ Cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| FMA             | FMA(f32,f32,f32)      | 151.84 GFLOPS    |\n| FMA             | FMA(f64,f64,f64)      | 75.702 GFLOPS    |\n| AVX             | ADD(MUL(f32,f32),f32) | 150.86 GFLOPS    |\n| AVX             | ADD(MUL(f64,f64),f64) | 75.476 GFLOPS    |\n| SSE             | ADD(MUL(f32,f32),f32) | 75.452 GFLOPS    |\n| SSE2            | ADD(MUL(f64,f64),f64) | 37.737 GFLOPS    |\n--------------------------------------------------------------\n
\n\nFor 8 cores:\n\n
\n$ ./cpufp --thread_pool=[0,2,4,6,8,10,12,14]\nNumber Threads: 8\nThread Pool Binding: 0 2 4 6 8 10 12 14\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| FMA             | FMA(f32,f32,f32)      | 1057.8 GFLOPS    |\n| FMA             | FMA(f64,f64,f64)      | 534.37 GFLOPS    |\n| AVX             | ADD(MUL(f32,f32),f32) | 1037.6 GFLOPS    |\n| AVX             | ADD(MUL(f64,f64),f64) | 516.21 GFLOPS    |\n| SSE             | ADD(MUL(f32,f32),f32) | 518.32 GFLOPS    |\n| SSE2            | ADD(MUL(f64,f64),f64) | 258.92 GFLOPS    |\n--------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/x64/Intel_Core_i3_8121U.md", "content": "# Intel Core i3-8121U\n\nProduct Code Name: Cannon-Lake\n\nSetting: 2 Cannon-Lake Cores\n\nFor single Core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n------------------------------------------------------------------------------\n| Instruction Set | Vector Length | Core Computation      | Peak Performance |\n|-----------------|---------------|-----------------------|------------------|\n| AVX512F         | 512b          | FMA(f32,f32,f32)      | 101.56 GFLOPS    |\n| AVX512F         | 512b          | FMA(f64,f64,f64)      | 50.784 GFLOPS    |\n| AVX512F         | 512b          | ADD(MUL(f32,f32),f32) | 50.783 GFLOPS    |\n| AVX512F         | 512b          | ADD(MUL(f64,f64),f64) | 25.391 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| FMA             | 256b          | FMA(f32,f32,f32)      | 101.55 GFLOPS    |\n| FMA             | 256b          | FMA(f64,f64,f64)      | 50.803 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f32,f32),f32) | 50.744 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f64,f64),f64) | 25.39 GFLOPS     |\n|-----------------|---------------|-----------------------|------------------|\n| FMA             | 128b          | FMA(f32,f32,f32)      | 50.772 GFLOPS    |\n| FMA             | 128b          | FMA(f64,f64,f64)      | 25.376 GFLOPS    |\n| SSE             | 128b          | ADD(MUL(f32,f32),f32) | 12.69 GFLOPS     |\n| SSE2            | 128b          | ADD(MUL(f64,f64),f64) | 6.3453 GFLOPS    |\n------------------------------------------------------------------------------\n
\n\nFor 2 Cores:\n\n
\n$ ./cpufp --thread_pool=[0,1]\nNumber Threads: 2\nThread Pool Binding: 0 1\n------------------------------------------------------------------------------\n| Instruction Set | Vector Length | Core Computation      | Peak Performance |\n|-----------------|---------------|-----------------------|------------------|\n| AVX512F         | 512b          | FMA(f32,f32,f32)      | 197.25 GFLOPS    |\n| AVX512F         | 512b          | FMA(f64,f64,f64)      | 98.624 GFLOPS    |\n| AVX512F         | 512b          | ADD(MUL(f32,f32),f32) | 98.62 GFLOPS     |\n| AVX512F         | 512b          | ADD(MUL(f64,f64),f64) | 49.315 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| FMA             | 256b          | FMA(f32,f32,f32)      | 197.18 GFLOPS    |\n| FMA             | 256b          | FMA(f64,f64,f64)      | 98.594 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f32,f32),f32) | 98.64 GFLOPS     |\n| AVX             | 256b          | ADD(MUL(f64,f64),f64) | 49.304 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| FMA             | 128b          | FMA(f32,f32,f32)      | 98.629 GFLOPS    |\n| FMA             | 128b          | FMA(f64,f64,f64)      | 49.319 GFLOPS    |\n| SSE             | 128b          | ADD(MUL(f32,f32),f32) | 24.658 GFLOPS    |\n| SSE2            | 128b          | ADD(MUL(f64,f64),f64) | 12.326 GFLOPS    |\n------------------------------------------------------------------------------\n
\n\n" }, { "path": "benchmark_result/x64/Intel_Core_i5_1340P.md", "content": "# Intel Core i5-1340P\n\nProduct Code Name: Raptor Lake\n\nSetting: 4 Raptor Cove(P-Core) Cores + 8 Gracemont(E-Core) Cores\n\nFor single P-Core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| AVX_VNNI        | DP4A(s32,u8,s8)       | 586.84 Gops      |\n| AVX_VNNI        | DP2A(s32,s16,s16)     | 293.5 Gops       |\n| FMA             | FMA(f32,f32,f32)      | 146.76 Gflops    |\n| FMA             | FMA(f64,f64,f64)      | 73.373 Gflops    |\n| AVX             | ADD(MUL(f32,f32),f32) | 107.7 Gflops     |\n| AVX             | ADD(MUL(f64,f64),f64) | 53.512 Gflops    |\n| SSE             | ADD(MUL(f32,f32),f32) | 54.49 Gflops     |\n| SSE2            | ADD(MUL(f64,f64),f64) | 27.243 Gflops    |\n--------------------------------------------------------------\n
\n\nFor 4 P-Cores:\n\n
\n$ ./cpufp --thread_pool=[0,2,4,6]\nNumber Threads: 4\nThread Pool Binding: 0 2 4 6\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| AVX_VNNI        | DP4A(s32,u8,s8)       | 2.2454 Tops      |\n| AVX_VNNI        | DP2A(s32,s16,s16)     | 1.1215 Tops      |\n| FMA             | FMA(f32,f32,f32)      | 546.31 Gflops    |\n| FMA             | FMA(f64,f64,f64)      | 267.62 Gflops    |\n| AVX             | ADD(MUL(f32,f32),f32) | 356.72 Gflops    |\n| AVX             | ADD(MUL(f64,f64),f64) | 176.89 Gflops    |\n| SSE             | ADD(MUL(f32,f32),f32) | 183.39 Gflops    |\n| SSE2            | ADD(MUL(f64,f64),f64) | 91.293 Gflops    |\n--------------------------------------------------------------\n
\n\nFor single E-Core:\n\n
\n$ ./cpufp --thread_pool=[8]\nNumber Threads: 1\nThread Pool Binding: 8\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| AVX_VNNI        | DP4A(s32,u8,s8)       | 108.5 Gops       |\n| AVX_VNNI        | DP2A(s32,s16,s16)     | 54.251 Gops      |\n| FMA             | FMA(f32,f32,f32)      | 54.248 Gflops    |\n| FMA             | FMA(f64,f64,f64)      | 27.125 Gflops    |\n| AVX             | ADD(MUL(f32,f32),f32) | 27.126 Gflops    |\n| AVX             | ADD(MUL(f64,f64),f64) | 13.563 Gflops    |\n| SSE             | ADD(MUL(f32,f32),f32) | 27.122 Gflops    |\n| SSE2            | ADD(MUL(f64,f64),f64) | 13.561 Gflops    |\n--------------------------------------------------------------\n
\n\nFor 8 E-Cores:\n\n
\n$ ./cpufp --thread_pool=[8-15]\nNumber Threads: 8\nThread Pool Binding: 8 9 10 11 12 13 14 15\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| AVX_VNNI        | DP4A(s32,u8,s8)       | 791.36 Gops      |\n| AVX_VNNI        | DP2A(s32,s16,s16)     | 395.68 Gops      |\n| FMA             | FMA(f32,f32,f32)      | 395.67 Gflops    |\n| FMA             | FMA(f64,f64,f64)      | 197.83 Gflops    |\n| AVX             | ADD(MUL(f32,f32),f32) | 197.84 Gflops    |\n| AVX             | ADD(MUL(f64,f64),f64) | 98.921 Gflops    |\n| SSE             | ADD(MUL(f32,f32),f32) | 197.83 Gflops    |\n| SSE2            | ADD(MUL(f64,f64),f64) | 98.916 Gflops    |\n--------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/x64/Intel_N150.md", "content": "# Intel N150\n\nProduct Code Name: Twin-Lake\n\nSetting: 4 Gracemont Cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n------------------------------------------------------------------------------\n| Instruction Set | Vector Length | Core Computation      | Peak Performance |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 256b          | DP4A(s32,u8,s8)       | 114.75 GOPS      |\n| AVX_VNNI        | 256b          | DP2A(s32,s16,s16)     | 57.372 GOPS      |\n| FMA             | 256b          | FMA(f32,f32,f32)      | 57.374 GFLOPS    |\n| FMA             | 256b          | FMA(f64,f64,f64)      | 28.608 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f32,f32),f32) | 28.688 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f64,f64),f64) | 14.344 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 128b          | DP4A(s32,u8,s8)       | 114.75 GOPS      |\n| AVX_VNNI        | 128b          | DP2A(s32,s16,s16)     | 57.352 GOPS      |\n| FMA             | 128b          | FMA(f32,f32,f32)      | 56.509 GFLOPS    |\n| FMA             | 128b          | FMA(f64,f64,f64)      | 28.259 GFLOPS    |\n| SSE             | 128b          | ADD(MUL(f32,f32),f32) | 28.685 GFLOPS    |\n| SSE2            | 128b          | ADD(MUL(f64,f64),f64) | 14.34 GFLOPS     |\n------------------------------------------------------------------------------\n
\n\nFor 4 cores:\n\n
\n$ ./cpufp --thread_pool=[0-3]\nNumber Threads: 4\nThread Pool Binding: 0 1 2 3\n------------------------------------------------------------------------------\n| Instruction Set | Vector Length | Core Computation      | Peak Performance |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 256b          | DP4A(s32,u8,s8)       | 369.64 GOPS      |\n| AVX_VNNI        | 256b          | DP2A(s32,s16,s16)     | 184.83 GOPS      |\n| FMA             | 256b          | FMA(f32,f32,f32)      | 179.63 GFLOPS    |\n| FMA             | 256b          | FMA(f64,f64,f64)      | 89.945 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f32,f32),f32) | 91.402 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f64,f64),f64) | 45.469 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 128b          | DP4A(s32,u8,s8)       | 369.7 GOPS       |\n| AVX_VNNI        | 128b          | DP2A(s32,s16,s16)     | 184.84 GOPS      |\n| FMA             | 128b          | FMA(f32,f32,f32)      | 171.99 GFLOPS    |\n| FMA             | 128b          | FMA(f64,f64,f64)      | 86.56 GFLOPS     |\n| SSE             | 128b          | ADD(MUL(f32,f32),f32) | 88.764 GFLOPS    |\n| SSE2            | 128b          | ADD(MUL(f64,f64),f64) | 44.468 GFLOPS    |\n------------------------------------------------------------------------------\n
\n\n" }, { "path": "benchmark_result/x64/Intel_Ultra7_255H.md", "content": "# Intel Ultra7 255H\n\nProduct Code Name: Arrow Lake-H\n\nSetting: 6 Lion Cove P-Cores + 8 Skymont E-Cores + 2 (Unknown Arch) LPE-Cores\n\nFor single P-Core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n------------------------------------------------------------------------------\n| Instruction Set | Vector Length | Core Computation      | Peak Performance |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 256b          | DP4A(s32,u8,s8)       | 647.06 GOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,s8,s8)       | 646.81 GOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,s8,u8)       | 647.17 GOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,u8,u8)       | 646.86 GOPS      |\n| AVX_VNNI        | 256b          | DP2A(s32,s16,s16)     | 323.05 GOPS      |\n| FMA             | 256b          | FMA(f32,f32,f32)      | 161.55 GFLOPS    |\n| FMA             | 256b          | FMA(f64,f64,f64)      | 80.961 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f32,f32),f32) | 132.12 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f64,f64),f64) | 66.11 GFLOPS     |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 128b          | DP4A(s32,u8,s8)       | 323.03 GOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,s8,s8)       | 323.55 GOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,s8,u8)       | 323.24 GOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,u8,u8)       | 323.2 GOPS       |\n| AVX_VNNI        | 128b          | DP2A(s32,s16,s16)     | 161.58 GOPS      |\n| FMA             | 128b          | FMA(f32,f32,f32)      | 80.786 GFLOPS    |\n| FMA             | 128b          | FMA(f64,f64,f64)      | 40.381 GFLOPS    |\n| SSE             | 128b          | ADD(MUL(f32,f32),f32) | 67.709 GFLOPS    |\n| SSE2            | 128b          | ADD(MUL(f64,f64),f64) | 33.791 GFLOPS    |\n------------------------------------------------------------------------------\n
\n\nFor 6 P-Cores:\n\n
\n$ ./cpufp --thread_pool=[0-5]\nNumber Threads: 6\nThread Pool Binding: 0 1 2 3 4 5\n------------------------------------------------------------------------------\n| Instruction Set | Vector Length | Core Computation      | Peak Performance |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 256b          | DP4A(s32,u8,s8)       | 3.4864 TOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,s8,s8)       | 3.4477 TOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,s8,u8)       | 3.416 TOPS       |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,u8,u8)       | 3.4142 TOPS      |\n| AVX_VNNI        | 256b          | DP2A(s32,s16,s16)     | 1.7058 TOPS      |\n| FMA             | 256b          | FMA(f32,f32,f32)      | 854.05 GFLOPS    |\n| FMA             | 256b          | FMA(f64,f64,f64)      | 426.89 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f32,f32),f32) | 710.61 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f64,f64),f64) | 355.38 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 128b          | DP4A(s32,u8,s8)       | 1.7078 TOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,s8,s8)       | 1.7078 TOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,s8,u8)       | 1.7081 TOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,u8,u8)       | 1.7087 TOPS      |\n| AVX_VNNI        | 128b          | DP2A(s32,s16,s16)     | 853.72 GOPS      |\n| FMA             | 128b          | FMA(f32,f32,f32)      | 426.93 GFLOPS    |\n| FMA             | 128b          | FMA(f64,f64,f64)      | 213.29 GFLOPS    |\n| SSE             | 128b          | ADD(MUL(f32,f32),f32) | 354.37 GFLOPS    |\n| SSE2            | 128b          | ADD(MUL(f64,f64),f64) | 178.34 GFLOPS    |\n------------------------------------------------------------------------------\n
\n\nFor single E-Core:\n\n
\n$ ./cpufp --thread_pool=[6]\nNumber Threads: 1\nThread Pool Binding: 6\n------------------------------------------------------------------------------\n| Instruction Set | Vector Length | Core Computation      | Peak Performance |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 256b          | DP4A(s32,u8,s8)       | 561.38 GOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,s8,s8)       | 561.39 GOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,s8,u8)       | 561.43 GOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,u8,u8)       | 561.43 GOPS      |\n| AVX_VNNI        | 256b          | DP2A(s32,s16,s16)     | 280.72 GOPS      |\n| FMA             | 256b          | FMA(f32,f32,f32)      | 140.35 GFLOPS    |\n| FMA             | 256b          | FMA(f64,f64,f64)      | 70.175 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f32,f32),f32) | 70.177 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f64,f64),f64) | 35.089 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 128b          | DP4A(s32,u8,s8)       | 449.23 GOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,s8,s8)       | 449.91 GOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,s8,u8)       | 449.35 GOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,u8,u8)       | 449.5 GOPS       |\n| AVX_VNNI        | 128b          | DP2A(s32,s16,s16)     | 224.62 GOPS      |\n| FMA             | 128b          | FMA(f32,f32,f32)      | 113.49 GFLOPS    |\n| FMA             | 128b          | FMA(f64,f64,f64)      | 56.793 GFLOPS    |\n| SSE             | 128b          | ADD(MUL(f32,f32),f32) | 70.099 GFLOPS    |\n| SSE2            | 128b          | ADD(MUL(f64,f64),f64) | 35.043 GFLOPS    |\n------------------------------------------------------------------------------\n
\n\nFor 8 E-Cores:\n\n
\n$ ./cpufp --thread_pool=[6-13]\nNumber Threads: 8\nThread Pool Binding: 6 7 8 9 10 11 12 13\n------------------------------------------------------------------------------\n| Instruction Set | Vector Length | Core Computation      | Peak Performance |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 256b          | DP4A(s32,u8,s8)       | 4.1754 TOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,s8,s8)       | 4.1767 TOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,s8,u8)       | 4.1732 TOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,u8,u8)       | 4.1708 TOPS      |\n| AVX_VNNI        | 256b          | DP2A(s32,s16,s16)     | 2.0668 TOPS      |\n| FMA             | 256b          | FMA(f32,f32,f32)      | 1.029 TFLOPS     |\n| FMA             | 256b          | FMA(f64,f64,f64)      | 513.76 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f32,f32),f32) | 511.26 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f64,f64),f64) | 254.99 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 128b          | DP4A(s32,u8,s8)       | 3.26 TOPS        |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,s8,s8)       | 3.2669 TOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,s8,u8)       | 3.2702 TOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,u8,u8)       | 3.2616 TOPS      |\n| AVX_VNNI        | 128b          | DP2A(s32,s16,s16)     | 1.6311 TOPS      |\n| FMA             | 128b          | FMA(f32,f32,f32)      | 824.83 GFLOPS    |\n| FMA             | 128b          | FMA(f64,f64,f64)      | 412.47 GFLOPS    |\n| SSE             | 128b          | ADD(MUL(f32,f32),f32) | 509.08 GFLOPS    |\n| SSE2            | 128b          | ADD(MUL(f64,f64),f64) | 254.62 GFLOPS    |\n------------------------------------------------------------------------------\n
\n\nFor single LPE-Core:\n\n
\n$ ./cpufp --thread_pool=[14]\nNumber Threads: 1\nThread Pool Binding: 14\n------------------------------------------------------------------------------\n| Instruction Set | Vector Length | Core Computation      | Peak Performance |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 256b          | DP4A(s32,u8,s8)       | 157.12 GOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,s8,s8)       | 157 GOPS         |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,s8,u8)       | 157.02 GOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,u8,u8)       | 156.96 GOPS      |\n| AVX_VNNI        | 256b          | DP2A(s32,s16,s16)     | 78.469 GOPS      |\n| FMA             | 256b          | FMA(f32,f32,f32)      | 39.237 GFLOPS    |\n| FMA             | 256b          | FMA(f64,f64,f64)      | 19.624 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f32,f32),f32) | 19.63 GFLOPS     |\n| AVX             | 256b          | ADD(MUL(f64,f64),f64) | 9.8176 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 128b          | DP4A(s32,u8,s8)       | 156.93 GOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,s8,s8)       | 157.11 GOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,s8,u8)       | 156.99 GOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,u8,u8)       | 156.87 GOPS      |\n| AVX_VNNI        | 128b          | DP2A(s32,s16,s16)     | 78.453 GOPS      |\n| FMA             | 128b          | FMA(f32,f32,f32)      | 39.312 GFLOPS    |\n| FMA             | 128b          | FMA(f64,f64,f64)      | 19.628 GFLOPS    |\n| SSE             | 128b          | ADD(MUL(f32,f32),f32) | 19.615 GFLOPS    |\n| SSE2            | 128b          | ADD(MUL(f64,f64),f64) | 9.8155 GFLOPS    |\n------------------------------------------------------------------------------\n
\n\nFor 2 LPE-Cores:\n\n
\n$ ./cpufp --thread_pool=[14,15]\nNumber Threads: 2\nThread Pool Binding: 14 15\n------------------------------------------------------------------------------\n| Instruction Set | Vector Length | Core Computation      | Peak Performance |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 256b          | DP4A(s32,u8,s8)       | 316.22 GOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,s8,s8)       | 316.14 GOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,s8,u8)       | 315.76 GOPS      |\n| AVX_VNNI_INT8   | 256b          | DP4A(s32,u8,u8)       | 316.06 GOPS      |\n| AVX_VNNI        | 256b          | DP2A(s32,s16,s16)     | 158.13 GOPS      |\n| FMA             | 256b          | FMA(f32,f32,f32)      | 79.052 GFLOPS    |\n| FMA             | 256b          | FMA(f64,f64,f64)      | 39.483 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f32,f32),f32) | 39.472 GFLOPS    |\n| AVX             | 256b          | ADD(MUL(f64,f64),f64) | 19.759 GFLOPS    |\n|-----------------|---------------|-----------------------|------------------|\n| AVX_VNNI        | 128b          | DP4A(s32,u8,s8)       | 315.74 GOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,s8,s8)       | 316.01 GOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,s8,u8)       | 315.23 GOPS      |\n| AVX_VNNI_INT8   | 128b          | DP4A(s32,u8,u8)       | 316.03 GOPS      |\n| AVX_VNNI        | 128b          | DP2A(s32,s16,s16)     | 157.66 GOPS      |\n| FMA             | 128b          | FMA(f32,f32,f32)      | 79.005 GFLOPS    |\n| FMA             | 128b          | FMA(f64,f64,f64)      | 39.435 GFLOPS    |\n| SSE             | 128b          | ADD(MUL(f32,f32),f32) | 39.406 GFLOPS    |\n| SSE2            | 128b          | ADD(MUL(f64,f64),f64) | 19.723 GFLOPS    |\n------------------------------------------------------------------------------\n
\n\n" }, { "path": "benchmark_result/x64/Intel_Xeon_Gold_6455B.md", "content": "# Intel Xeon Gold 6455B\n\nMicroarchitecture: Sapphire Rapids\n\nSetting: 2 Sockets x 32 Golden Cove Cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| AMX_INT8        | MM(s32,s8,s8)         | 6.3726 Tops      |\n| AMX_INT8        | MM(s32,s8,u8)         | 7.5746 Tops      |\n| AMX_INT8        | MM(s32,u8,s8)         | 7.5733 Tops      |\n| AMX_INT8        | MM(s32,u8,u8)         | 7.5718 Tops      |\n| AMX_BF16        | MM(f32,bf16,bf16)     | 3.7868 Tflops    |\n| AVX512_VNNI     | DP4A(s32,u8,s8)       | 998.07 Gops      |\n| AVX512_VNNI     | DP2A(s32,s16,s16)     | 499.07 Gops      |\n| AVX_VNNI        | DP4A(s32,u8,s8)       | 498.96 Gops      |\n| AVX_VNNI        | DP2A(s32,s16,s16)     | 249.47 Gops      |\n| AVX512_BF16     | DP2A(f32,bf16,bf16)   | 115.16 Gflops    |\n| AVX512_FP16     | FMA(f16,f16,f16)      | 499.08 Gflops    |\n| AVX512F         | FMA(f32,f32,f32)      | 230.28 Gflops    |\n| AVX512F         | FMA(f64,f64,f64)      | 115.17 Gflops    |\n| FMA             | FMA(f32,f32,f32)      | 118.35 Gflops    |\n| FMA             | FMA(f64,f64,f64)      | 62.385 Gflops    |\n| AVX             | ADD(MUL(f32,f32),f32) | 91.59 Gflops     |\n| AVX             | ADD(MUL(f64,f64),f64) | 45.85 Gflops     |\n| SSE             | ADD(MUL(f32,f32),f32) | 46.493 Gflops    |\n| SSE2            | ADD(MUL(f64,f64),f64) | 23.235 Gflops    |\n--------------------------------------------------------------\n
\n\nFor 64 cores:\n\n
\n$ ./cpufp --thread_pool=[0-63]\nNumber Threads: 64\nThread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| AMX_INT8        | MM(s32,s8,s8)         | 390.67 Tops      |\n| AMX_INT8        | MM(s32,s8,u8)         | 380.93 Tops      |\n| AMX_INT8        | MM(s32,u8,s8)         | 391.32 Tops      |\n| AMX_INT8        | MM(s32,u8,u8)         | 380.28 Tops      |\n| AMX_BF16        | MM(f32,bf16,bf16)     | 192.47 Tflops    |\n| AVX512_VNNI     | DP4A(s32,u8,s8)       | 48.114 Tops      |\n| AVX512_VNNI     | DP2A(s32,s16,s16)     | 24.169 Tops      |\n| AVX_VNNI        | DP4A(s32,u8,s8)       | 30.818 Tops      |\n| AVX_VNNI        | DP2A(s32,s16,s16)     | 15.74 Tops       |\n| AVX512_BF16     | DP2A(f32,bf16,bf16)   | 7.09 Tflops      |\n| AVX512_FP16     | FMA(f16,f16,f16)      | 31.473 Tflops    |\n| AVX512F         | FMA(f32,f32,f32)      | 14.329 Tflops    |\n| AVX512F         | FMA(f64,f64,f64)      | 6.5406 Tflops    |\n| FMA             | FMA(f32,f32,f32)      | 7.4039 Tflops    |\n| FMA             | FMA(f64,f64,f64)      | 3.9067 Tflops    |\n| AVX             | ADD(MUL(f32,f32),f32) | 5.4087 Tflops    |\n| AVX             | ADD(MUL(f64,f64),f64) | 2.7339 Tflops    |\n| SSE             | ADD(MUL(f32,f32),f32) | 2.9077 Tflops    |\n| SSE2            | ADD(MUL(f64,f64),f64) | 1.4791 Tflops    |\n--------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/x64/Intel_Xeon_W9_3495X.md", "content": "# Intel Xeon W9-3495X\n\nMicroarchitecture: Sapphire Rapids\n\nSetting: 1 Sockets x 56 Golden Cove Cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| AMX_INT8        | MM(s32,s8,s8)         | 5.6821 TOPS      |\n| AMX_INT8        | MM(s32,s8,u8)         | 5.6854 TOPS      |\n| AMX_INT8        | MM(s32,u8,s8)         | 5.6872 TOPS      |\n| AMX_INT8        | MM(s32,u8,u8)         | 5.6905 TOPS      |\n| AMX_BF16        | MM(f32,bf16,bf16)     | 2.8448 TFLOPS    |\n| AVX512_VNNI     | DP4A(s32,u8,s8)       | 711.46 GOPS      |\n| AVX512_VNNI     | DP2A(s32,s16,s16)     | 355.73 GOPS      |\n| AVX_VNNI        | DP4A(s32,u8,s8)       | 368.94 GOPS      |\n| AVX_VNNI        | DP2A(s32,s16,s16)     | 184.44 GOPS      |\n| AVX512_BF16     | DP2A(f32,bf16,bf16)   | 80.477 GFLOPS    |\n| AVX512_FP16     | FMA(f16,f16,f16)      | 355.76 GFLOPS    |\n| AVX512F         | FMA(f32,f32,f32)      | 158.74 GFLOPS    |\n| AVX512F         | FMA(f64,f64,f64)      | 79.375 GFLOPS    |\n| FMA             | FMA(f32,f32,f32)      | 92.224 GFLOPS    |\n| FMA             | FMA(f64,f64,f64)      | 46.115 GFLOPS    |\n| AVX             | ADD(MUL(f32,f32),f32) | 67.789 GFLOPS    |\n| AVX             | ADD(MUL(f64,f64),f64) | 33.9 GFLOPS      |\n| SSE             | ADD(MUL(f32,f32),f32) | 34.43 GFLOPS     |\n| SSE2            | ADD(MUL(f64,f64),f64) | 17.218 GFLOPS    |\n--------------------------------------------------------------\n
\n\nFor 56 cores:\n\n
\n$ ./cpufp --thread_pool=[0-55]\nNumber Threads: 56\nThread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| AMX_INT8        | MM(s32,s8,s8)         | 293.86 TOPS      |\n| AMX_INT8        | MM(s32,s8,u8)         | 309.81 TOPS      |\n| AMX_INT8        | MM(s32,u8,s8)         | 293.44 TOPS      |\n| AMX_INT8        | MM(s32,u8,u8)         | 293.07 TOPS      |\n| AMX_BF16        | MM(f32,bf16,bf16)     | 141.12 TFLOPS    |\n| AVX512_VNNI     | DP4A(s32,u8,s8)       | 39.629 TOPS      |\n| AVX512_VNNI     | DP2A(s32,s16,s16)     | 19.772 TOPS      |\n| AVX_VNNI        | DP4A(s32,u8,s8)       | 20.503 TOPS      |\n| AVX_VNNI        | DP2A(s32,s16,s16)     | 10.236 TOPS      |\n| AVX512_BF16     | DP2A(f32,bf16,bf16)   | 4.4223 TFLOPS    |\n| AVX512_FP16     | FMA(f16,f16,f16)      | 19.761 TFLOPS    |\n| AVX512F         | FMA(f32,f32,f32)      | 7.7876 TFLOPS    |\n| AVX512F         | FMA(f64,f64,f64)      | 3.8961 TFLOPS    |\n| FMA             | FMA(f32,f32,f32)      | 4.962 TFLOPS     |\n| FMA             | FMA(f64,f64,f64)      | 2.4778 TFLOPS    |\n| AVX             | ADD(MUL(f32,f32),f32) | 3.4637 TFLOPS    |\n| AVX             | ADD(MUL(f64,f64),f64) | 1.7112 TFLOPS    |\n| SSE             | ADD(MUL(f32,f32),f32) | 1.9122 TFLOPS    |\n| SSE2            | ADD(MUL(f64,f64),f64) | 960.12 GFLOPS    |\n--------------------------------------------------------------\n
\n" }, { "path": "benchmark_result/x64/ZHAOXIN_KX_6640MA.md", "content": "# ZHAOXIN KX-6640MA\n\nArchitecture: LuJiaZui\n\nSetting: 4 Cores\n\nFor single core:\n\n
\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Pool Binding: 0\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| AVX             | ADD(MUL(f32,f32),f32) | 13.825 GFLOPS    |\n| AVX             | ADD(MUL(f64,f64),f64) | 5.1625 GFLOPS    |\n| SSE             | ADD(MUL(f32,f32),f32) | 20.738 GFLOPS    |\n| SSE2            | ADD(MUL(f64,f64),f64) | 5.1844 GFLOPS    |\n--------------------------------------------------------------\n
\n\nFor 4 cores:\n\n
\n$ ./cpufp --thread_pool=[0-3]\nNumber Threads: 4\nThread Pool Binding: 0 1 2 3\n--------------------------------------------------------------\n| Instruction Set | Core Computation      | Peak Performance |\n| AVX             | ADD(MUL(f32,f32),f32) | 46.638 GFLOPS    |\n| AVX             | ADD(MUL(f64,f64),f64) | 17.449 GFLOPS    |\n| SSE             | ADD(MUL(f32,f32),f32) | 70.102 GFLOPS    |\n| SSE2            | ADD(MUL(f64,f64),f64) | 17.511 GFLOPS    |\n--------------------------------------------------------------\n
\n\n" }, { "path": "build_arm64.sh", "content": "SRC=arm64\nASM=$SRC/asm\nCOMM=common\nBUILD_DIR=build_dir\nOS=$(uname -o)\n\n# make directory\nif [ -d \"$BUILD_DIR\" ]; then\n rm -rf $BUILD_DIR/*\nelse\n mkdir $BUILD_DIR\nfi\n\n# build common tools\nif [ \"${OS}\" == \"Darwin\" ]; then\ng++ -O3 -std=gnu++17 -c $COMM/table.cpp -o $BUILD_DIR/table.o\ng++ -O3 -std=gnu++17 -pthread -c $COMM/smtl.cpp -o $BUILD_DIR/smtl.o\nelse\ng++ -O3 -c $COMM/table.cpp -o $BUILD_DIR/table.o\ng++ -O3 -pthread -c $COMM/smtl.cpp -o $BUILD_DIR/smtl.o\nfi\n\n# gen benchmark macro according to cpuid feature\ngcc $SRC/cpuid.c -o $BUILD_DIR/cpuid\nSIMD_MACRO=\" \"\nSIMD_OBJ=\" \"\nAS_EXTRA_FLAGS=\"-mcpu=all\"\nif [ \"${OS}\" == \"Darwin\" ]; then\n AS_EXTRA_FLAGS=\"-mcpu=apple-m2\"\nfi\nfor SIMD in `$BUILD_DIR/cpuid`;\ndo\n SIMD_MACRO=\"$SIMD_MACRO-D$SIMD \"\n SIMD_OBJ=\"$SIMD_OBJ$BUILD_DIR/$SIMD.o \"\n as ${AS_EXTRA_FLAGS} -c $ASM/$SIMD.S -o $BUILD_DIR/$SIMD.o\ndone\n\n# compile cpufp\nif [ \"${OS}\" != \"Darwin\" ]; then\ng++ -std=gnu++17 -O3 -I$COMM $SIMD_MACRO -c $SRC/cpufp.cpp -o $BUILD_DIR/cpufp.o\ng++ -std=gnu++17 -O3 -z noexecstack -pthread -o cpufp $BUILD_DIR/cpufp.o $BUILD_DIR/smtl.o $BUILD_DIR/table.o $SIMD_OBJ\nelse\ng++ -O3 -I$COMM $SIMD_MACRO -c $SRC/cpufp.cpp -o $BUILD_DIR/cpufp.o\ng++ -O3 -pthread -o cpufp $BUILD_DIR/cpufp.o $BUILD_DIR/smtl.o $BUILD_DIR/table.o $SIMD_OBJ\nfi\n" }, { "path": "build_e2k.sh", "content": "SRC=e2k\nCOMM=common\nBUILD_DIR=build_dir\n\n# make directory\nif [ -d \"$BUILD_DIR\" ]; then\n rm -rf $BUILD_DIR/*\nelse\n mkdir $BUILD_DIR\nfi\n\n# build common tools\nl++ -O3 -c $COMM/table.cpp -o $BUILD_DIR/table.o\nl++ -O3 -pthread -c $COMM/smtl.cpp -o $BUILD_DIR/smtl.o\n\n# assembler implementation is selected by __iset__ at compile time\nl++ -c $SRC/asm.S -o $BUILD_DIR/asm.o\n\n# compile cpufp\nl++ -O3 -I$COMM -c $SRC/cpufp.cpp -o $BUILD_DIR/cpufp.o\nl++ -O3 -z noexecstack -pthread -o cpufp $BUILD_DIR/cpufp.o $BUILD_DIR/smtl.o $BUILD_DIR/table.o $BUILD_DIR/asm.o\n" }, { "path": "build_loongarch64.sh", "content": "SRC=loongarch64\nASM=$SRC/asm\nCOMM=common\nBUILD_DIR=build_dir\n\n# make directory\nif [ -d \"$BUILD_DIR\" ]; then\n rm -rf $BUILD_DIR/*\nelse\n mkdir $BUILD_DIR\nfi\n\n# build common tools\ng++ -O3 -c $COMM/table.cpp -o $BUILD_DIR/table.o\ng++ -O3 -pthread -c $COMM/smtl.cpp -o $BUILD_DIR/smtl.o\n\n# gen benchmark macro according to cpuid feature\ngcc $SRC/cpuid.c -o $BUILD_DIR/cpuid\nSIMD_MACRO=\" \"\nSIMD_OBJ=\" \"\nfor SIMD in `$BUILD_DIR/cpuid`;\ndo\n SIMD_MACRO=\"$SIMD_MACRO-D$SIMD \"\n SIMD_OBJ=\"$SIMD_OBJ$BUILD_DIR/$SIMD.o \"\n g++ -c $ASM/$SIMD.S -o $BUILD_DIR/$SIMD.o\ndone\n\n# compile cpufp\ng++ -O3 -I$COMM $SIMD_MACRO -c $SRC/cpufp.cpp -o $BUILD_DIR/cpufp.o\ng++ -O3 -z noexecstack -pthread -o cpufp $BUILD_DIR/cpufp.o $BUILD_DIR/smtl.o $BUILD_DIR/table.o $SIMD_OBJ\n" }, { "path": "build_riscv64.sh", "content": "SRC=riscv64\nASM=$SRC/asm\nCOMM=common\nBUILD_DIR=build_dir\n\n# make directory\nif [ -d \"$BUILD_DIR\" ]; then\n rm -rf $BUILD_DIR/*\nelse\n mkdir $BUILD_DIR\nfi\n\n# build common tools\ng++ -O3 -c $COMM/table.cpp -o $BUILD_DIR/table.o\ng++ -O3 -pthread -c $COMM/smtl.cpp -o $BUILD_DIR/smtl.o\n\n# gen benchmark macro according to cpuid feature\ngcc $SRC/cpuid.c -o $BUILD_DIR/cpuid\nSIMD_MACRO=\" \"\nSIMD_OBJ=\" \"\nfor SIMD in `$BUILD_DIR/cpuid`;\ndo\n SIMD_MACRO=\"$SIMD_MACRO-D$SIMD \"\n SIMD_OBJ=\"$SIMD_OBJ$BUILD_DIR/$SIMD.o \"\n as -march=rv64gcv_zfh -c $ASM/$SIMD.S -o $BUILD_DIR/$SIMD.o\ndone\n\n# compile cpufp\ng++ -O3 -march=rv64gcv_zfh -I$COMM $SIMD_MACRO -c $SRC/cpufp.cpp -o $BUILD_DIR/cpufp.o\ng++ -O3 -z noexecstack -pthread -o cpufp $BUILD_DIR/cpufp.o $BUILD_DIR/smtl.o $BUILD_DIR/table.o $SIMD_OBJ\n" }, { "path": "build_x64.sh", "content": "SRC=x64\nASM=$SRC/asm\nCOMM=common\nBUILD_DIR=build_dir\n\n# make directory\nif [ -d \"$BUILD_DIR\" ]; then\n rm -rf $BUILD_DIR/*\nelse\n mkdir $BUILD_DIR\nfi\n\n# build common tools\ng++ -O3 -c $COMM/table.cpp -o $BUILD_DIR/table.o\ng++ -O3 -pthread -c $COMM/smtl.cpp -o $BUILD_DIR/smtl.o\n\n# gen benchmark macro according to cpuid feature\ngcc $SRC/cpuid.c -o $BUILD_DIR/cpuid\nSIMD_MACRO=\" \"\nSIMD_OBJ=\" \"\nfor SIMD in `$BUILD_DIR/cpuid`;\ndo\n SIMD_MACRO=\"$SIMD_MACRO-D$SIMD \"\n SIMD_OBJ=\"$SIMD_OBJ$BUILD_DIR/$SIMD.o \"\n g++ -c $ASM/$SIMD.S -o $BUILD_DIR/$SIMD.o\ndone\n\n# compile cpufp\ng++ -O3 -I$COMM $SIMD_MACRO -c $SRC/cpufp.cpp -o $BUILD_DIR/cpufp.o\ng++ -O3 -z noexecstack -pthread -o cpufp $BUILD_DIR/cpufp.o $BUILD_DIR/smtl.o $BUILD_DIR/table.o $SIMD_OBJ\n" }, { "path": "clean.sh", "content": "BUILD_DIR=build_dir\nrm -rf $BUILD_DIR cpufp\n" }, { "path": "common/smtl.cpp", "content": "#include \"smtl.hpp\"\n\n#include \n#include \n#include \n#ifdef __APPLE__\n#include \n#include \n#include \n#endif\n#include \n#include \n\n#define SMTL_MAX_THREADS 512\n\nenum smtl_status\n{\n SMTL_WORK,\n SMTL_IDLE,\n SMTL_FINI,\n};\n\nstruct queue_node_t\n{\n task_func_t task_func;\n void *params;\n struct queue_node_t *next;\n};\n\nstruct smtl_t\n{\n int num_threads;\n\n struct queue_node_t *task_queues[SMTL_MAX_THREADS];\n int cur_qid;\n\n pthread_t tids[SMTL_MAX_THREADS];\n\n pthread_mutex_t pt_mtx;\n pthread_cond_t pt_cv;\n int thread_holds;\n\n pthread_mutex_t sl_mtxs[SMTL_MAX_THREADS];\n pthread_cond_t sl_cvs[SMTL_MAX_THREADS];\n enum smtl_status status[SMTL_MAX_THREADS];\n};\n\nstruct smtl_tp_t\n{\n int tid;\n int tbind;\n struct smtl_t *sh;\n};\n\nstatic void thread_bind(int cpu)\n{\n#ifndef __APPLE__\n cpu_set_t cpu_set;\n CPU_ZERO(&cpu_set);\n CPU_SET(cpu, &cpu_set);\n if (pthread_setaffinity_np(pthread_self(),\n sizeof(cpu_set_t), &cpu_set) != 0)\n {\n fprintf(stderr, \"Error: cpu[%d] bind failed.\\n\", cpu);\n exit(0);\n }\n#else\n thread_policy_t cpu_set = &cpu;\n kern_return_t res = thread_policy_set(pthread_mach_thread_np(pthread_self()),\n THREAD_AFFINITY_POLICY, (thread_policy_t)&cpu_set, 1);\n if (res == KERN_NOT_SUPPORTED) {\n fprintf(stderr, \"Warning: cpu thread policy is not supported by OS\\n\");\n return;\n }\n if (res != KERN_SUCCESS) {\n fprintf(stderr, \"Error: cpu[%d] bind failed, return code %i\\n\", cpu, res);\n exit(0);\n }\n#endif\n}\n\nstatic void *smtl_thread_func(void *params)\n{\n int err = 0;\n\n struct smtl_tp_t *stp = (struct smtl_tp_t*)params;\n int tid = stp->tid;\n int tbind = stp->tbind;\n struct smtl_t *sh = stp->sh;\n free(stp);\n\n thread_bind(tbind);\n\n pthread_mutex_t *sl_mtx = sh->sl_mtxs + tid;\n pthread_cond_t *sl_cv = sh->sl_cvs + tid;\n\n pthread_mutex_t *pt_mtx = &sh->pt_mtx;\n pthread_cond_t *pt_cv = &sh->pt_cv;\n\n while (1)\n {\n err = pthread_mutex_lock(sl_mtx);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: sl_mtx lock failed.\\n\");\n exit(0);\n }\n while (sh->status[tid] != SMTL_WORK)\n {\n if (sh->status[tid] == SMTL_FINI)\n {\n err = pthread_mutex_unlock(sl_mtx);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: sl_mtx unlock failed.\\n\");\n exit(0);\n }\n return NULL;\n }\n err = pthread_cond_wait(sl_cv, sl_mtx);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: sl_cv wait failed.\\n\");\n exit(0);\n }\n }\n err = pthread_mutex_unlock(sl_mtx);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: sl_mtx unlock failed.\\n\");\n exit(0);\n }\n\n struct queue_node_t *p = sh->task_queues[tid];\n struct queue_node_t *q = NULL;\n sh->task_queues[tid] = NULL;\n while (p != NULL)\n {\n q = p->next;\n p->task_func(p->params);\n free(p);\n p = q;\n }\n\n err = pthread_mutex_lock(pt_mtx);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: pt_mtx lock failed.\\n\");\n exit(0);\n }\n sh->status[tid] = SMTL_IDLE;\n sh->thread_holds--;\n if (sh->thread_holds == 0)\n {\n err = pthread_cond_signal(pt_cv);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: pt_cv signal failed.\\n\");\n exit(0);\n }\n }\n err = pthread_mutex_unlock(pt_mtx);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: pt_mtx unlock failed.\\n\");\n exit(0);\n }\n }\n\n return NULL;\n}\n\nvoid smtl_init(smtl_handle *psh,\n std::vector &set_of_threads)\n{\n int err = 0;\n\n struct smtl_t *sh =\n (struct smtl_t*)malloc(sizeof(struct smtl_t));\n if (sh == NULL)\n {\n fprintf(stderr,\n \"ERROR: smtl_init allocation failed.\\n\");\n exit(0);\n }\n\n int num_threads = set_of_threads.size();\n sh->num_threads = num_threads;\n sh->cur_qid = 0;\n sh->thread_holds = 0;\n\n memset(sh->task_queues, 0,\n num_threads * sizeof(struct queue_node_t*));\n\n err = pthread_mutex_init(&sh->pt_mtx, NULL);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: pt_mtx init failed.\\n\");\n exit(0);\n }\n\n err = pthread_cond_init(&sh->pt_cv, NULL);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: pt_cv init failed.\\n\");\n exit(0);\n }\n\n int i;\n for (i = 0; i < num_threads; i++)\n {\n err = pthread_mutex_init(sh->sl_mtxs + i, NULL);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: sl_mtxs init failed.\\n\");\n exit(0);\n }\n\n err = pthread_cond_init(sh->sl_cvs + i, NULL);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: sl_cvs init failed.\\n\");\n exit(0);\n }\n\n sh->status[i] = SMTL_IDLE;\n\n struct smtl_tp_t *stp =\n (struct smtl_tp_t*)malloc(sizeof(struct smtl_tp_t));\n if (stp == NULL)\n {\n fprintf(stderr, \"ERROR: stp allocation failed.\\n\");\n exit(0);\n }\n stp->sh = sh;\n stp->tid = i;\n stp->tbind = set_of_threads[i];\n\n err = pthread_create(sh->tids + i, NULL,\n smtl_thread_func, stp);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: pthread_create failed.\\n\");\n exit(0);\n }\n }\n *psh = sh;\n}\n\nvoid smtl_fini(smtl_handle sh)\n{\n int err = 0;\n int i;\n for (i = 0; i < sh->num_threads; i++)\n {\n err = pthread_mutex_lock(sh->sl_mtxs + i);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: sl_mtxs lock failed.\\n\");\n exit(0);\n }\n sh->status[i] = SMTL_FINI;\n err = pthread_cond_signal(sh->sl_cvs + i);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: sl_cv signal failed.\\n\");\n exit(0);\n }\n err = pthread_mutex_unlock(sh->sl_mtxs + i);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: sl_mtxs unlock failed.\\n\");\n exit(0);\n }\n }\n\n for (i = 0; i < sh->num_threads; i++)\n {\n err = pthread_join(sh->tids[i], NULL);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: pthread_join failed.\\n\");\n exit(0);\n }\n }\n\n err = pthread_mutex_destroy(&sh->pt_mtx);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: pt_mtx destroy failed.\\n\");\n exit(0);\n }\n err = pthread_cond_destroy(&sh->pt_cv);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: pt_cv destroy failed.\\n\");\n exit(0);\n }\n for (i = 0; i < sh->num_threads; i++)\n {\n err = pthread_mutex_destroy(sh->sl_mtxs + i);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: sl_mtxs destroy failed.\\n\");\n exit(0);\n }\n\n err = pthread_cond_destroy(sh->sl_cvs + i);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: sl_cvs destroy failed.\\n\");\n exit(0);\n }\n\n struct queue_node_t *p = sh->task_queues[i], *q = NULL;\n while (p != NULL)\n {\n q = p->next;\n free(p);\n p = q;\n }\n }\n}\n\nint smtl_num_threads(smtl_handle sh)\n{\n return sh->num_threads;\n}\n\nvoid smtl_add_task(smtl_handle sh,\n task_func_t task_func,\n void *params)\n{\n struct queue_node_t *task =\n (struct queue_node_t*)malloc(sizeof(struct queue_node_t));\n if (task == NULL)\n {\n fprintf(stderr, \"ERROR: add_task allocation failed.\\n\");\n exit(0);\n }\n\n task->task_func = task_func;\n task->params = params;\n task->next = sh->task_queues[sh->cur_qid];\n sh->task_queues[sh->cur_qid] = task;\n sh->cur_qid++;\n if (sh->cur_qid == sh->num_threads)\n {\n sh->cur_qid = 0;\n }\n}\n\nvoid smtl_begin_tasks(smtl_handle sh)\n{\n int i, err = 0;\n sh->thread_holds = sh->num_threads;\n for (i = 0; i < sh->num_threads; i++)\n {\n err = pthread_mutex_lock(sh->sl_mtxs + i);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: sl_mtxs lock failed.\\n\");\n exit(0);\n }\n sh->status[i] = SMTL_WORK;\n err = pthread_cond_signal(sh->sl_cvs + i);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: sl_cvs signal failed.\\n\");\n exit(0);\n }\n err = pthread_mutex_unlock(sh->sl_mtxs + i);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: sl_mtxs unlock failed.\\n\");\n exit(0);\n }\n }\n}\n\nvoid smtl_wait_tasks_finished(smtl_handle sh)\n{\n int err = 0;\n\n pthread_mutex_lock(&sh->pt_mtx);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: pt_mtx lock failed.\\n\");\n exit(0);\n }\n while (sh->thread_holds > 0)\n {\n pthread_cond_wait(&sh->pt_cv, &sh->pt_mtx);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: pt_cv wait failed.\\n\");\n exit(0);\n }\n }\n sh->cur_qid = 0;\n pthread_mutex_unlock(&sh->pt_mtx);\n if (err != 0)\n {\n fprintf(stderr, \"ERROR: pt_mtx unlock failed.\\n\");\n exit(0);\n }\n}\n\n" }, { "path": "common/smtl.hpp", "content": "#ifndef _SMTL_H\n#define _SMTL_H\n\n#include \n\ntypedef struct smtl_t* smtl_handle;\ntypedef void (*task_func_t)(void*);\n\nvoid smtl_init(smtl_handle *psh,\n std::vector &set_of_threads);\n\nvoid smtl_fini(smtl_handle sh);\n\nint smtl_num_threads(smtl_handle sh);\n\nvoid smtl_add_task(smtl_handle sh,\n task_func_t task_func,\n void *params);\n\nvoid smtl_begin_tasks(smtl_handle sh);\n\nvoid smtl_wait_tasks_finished(smtl_handle sh);\n\n#endif\n\n" }, { "path": "common/table.cpp", "content": "#include \"table.hpp\"\n\n#include \nusing namespace std;\n\nTable::Table()\n{\n col = 0;\n}\n\nTable::~Table()\n{\n}\n\nvoid Table::setColumnNum(int col)\n{\n int i;\n\n this->col = col;\n\n colWidths.resize(col);\n\n for (i = 0; i < col; i++)\n {\n colWidths[i] = 2;\n }\n}\n\nvoid Table::addOneItem(std::vector &item)\n{\n int i;\n\n contents.push_back(item);\n pSep.push_back(0);\n\n for (i = 0; i < col; i++)\n {\n int length = item[i].size() + 2;\n if (length > colWidths[i])\n {\n colWidths[i] = length;\n }\n }\n}\n\nvoid Table::addSeparator()\n{\n std::vector dummy;\n contents.push_back(dummy);\n pSep.push_back(1);\n}\n\nvoid Table::print()\n{\n int i, j, k;\n\n int tableWidth = col + 1;\n for (i = 0; i < col; i++)\n {\n tableWidth += colWidths[i];\n }\n\n string vLine(tableWidth, '-');\n cout << vLine << endl;\n\n for (i = 0; i < contents.size(); i++)\n {\n string oneLine(\"|\");\n for (j = 0; j < col; j++)\n {\n if (pSep[i] == 0)\n {\n oneLine += (\" \" + contents[i][j]);\n for (k = 1 + contents[i][j].size();\n k < colWidths[j]; k++)\n {\n oneLine += \" \";\n }\n }\n else if (pSep[i] == 1)\n {\n string curCol(colWidths[j], '-');\n oneLine += curCol;\n }\n oneLine += \"|\";\n }\n cout << oneLine << endl;\n }\n\n cout << vLine << endl;\n}\n\n" }, { "path": "common/table.hpp", "content": "#ifndef _TABLE_HPP\n#define _TABLE_HPP\n\n#include \n#include \n\nclass Table\n{\npublic:\n Table();\n ~Table();\n\n Table(const Table &) = delete;\n Table &operator=(const Table &) = delete;\n\n void setColumnNum(int col);\n void addOneItem(std::vector &item);\n void addSeparator();\n void print();\n\nprivate:\n int col;\n std::vector colWidths;\n std::vector pSep;\n std::vector > contents;\n};\n\n#endif\n\n" }, { "path": "e2k/asm.S", "content": "#if __iset__ < 5\n# define CLEAR addd\n#else\n# define CLEAR qppackdl\n#endif\n\n.macro impl_bench name, op\n .global \\name\n .type \\name, #function\n .align 8\n\\name:\n {\n setwd wsz=34, nfx=0\n setbn rsz=29, rbs=4, rcur=0\n rwd,0 (1ULL << 37) | 15, %lsr\n disp %ctpr1, 0f\n }\n {\n getfd,0 %r0, (32 << 6), %g16\n disp %ctpr2, 1f\n }\n {\n ord,0 %g16, (1ULL << 37), %g16\n return %ctpr3\n nop 2\n }\n0:\n {\n loop_mode\n alc alcf=1, alct=1\n abn abnf=1, abnt=1\n CLEAR,0 0, 0, %b[0]\n CLEAR,1 0, 0, %b[1]\n CLEAR,3 0, 0, %b[30]\n CLEAR,4 0, 0, %b[31]\n ct %ctpr1 ? #NOT_LOOP_END\n }\n {\n rwd,0 %g16, %lsr\n nop 3 // NOTE: low delay may lead to undefined behaviour\n }\n\n // NOTE: `{,p,qp}fmul_add{s,d}` has latency 8 cycles thus we need at least\n // 8 registers for each channel.\n //\n // Example for ALC0:\n // I: read (b0) write (b20)\n // 0: r8 r28 # use r28 as dst\n // 1: r10 r30\n // 2: r12 r32\n // 3: r16 r34\n // 4: r18 r36 # r28 is ready if fmuld (4)\n // 5: r20 r38 # r28 is ready if fmad (5)\n // 6: r22 r40\n // 7: r24 r42\n // 8: r26 r44 # r28 is ready if fmul_addd (8)\n // 9: r28 r46 # read from r28 (+1 just in case)\n1:\n {\n loop_mode\n alc alcf=1, alct=1\n abn abnf=1, abnt=1\n \\op,0 %b[0], %b[0], %b[0], %b[20]\n \\op,1 %b[20], %b[20], %b[20], %b[40]\n \\op,3 %b[1], %b[1], %b[1], %b[21]\n \\op,4 %b[21], %b[21], %b[21], %b[41]\n#if __iset__ >= 4\n // NOTE: v1-v3 does not support fops in ALC2/ALC5\n \\op,2 %b[40], %b[40], %b[40], %b[0]\n \\op,5 %b[41], %b[41], %b[41], %b[1]\n#endif\n ct %ctpr2 ? #NOT_LOOP_END\n }\n {\n ct %ctpr3\n }\n .size \\name, . - \\name\n.endm\n\n .text\n\n#if __iset__ >= 5\n impl_bench bench_qpfmul_adds, qpfmul_adds\n impl_bench bench_qpfmul_addd, qpfmul_addd\n#endif\n\n#if __iset__ >= 6\n impl_bench bench_qpfmas, qpfmas\n impl_bench bench_qpfmad, qpfmad\n#endif\n\n impl_bench bench_pfmul_adds, pfmul_adds\n impl_bench bench_fmul_addd, fmul_addd\n" }, { "path": "e2k/cpufp.cpp", "content": "#include \"table.hpp\"\n#include \"smtl.hpp\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\nusing namespace std;\n\nextern \"C\"\n{\n\n#if __iset__ >= 6\n void bench_qpfmas(int64_t, void *params);\n void bench_qpfmad(int64_t, void *params);\n#endif\n\n#if __iset__ >= 5\n void bench_qpfmul_adds(int64_t, void *params);\n void bench_qpfmul_addd(int64_t, void *params);\n#endif\n\n void bench_pfmul_adds(int64_t, void *params);\n void bench_fmul_addd(int64_t, void *params);\n}\n\ntypedef struct\n{\n std::string isa;\n std::string type;\n std::string dim;\n int64_t loop_time;\n int64_t comp_pl;\n void *params;\n void (*bench)(int64_t, void*);\n} cpubm_t;\nstatic vector bm_list;\n\nstatic double get_time(struct timespec *start,\n struct timespec *end)\n{\n return end->tv_sec - start->tv_sec +\n (end->tv_nsec - start->tv_nsec) * 1e-9;\n}\n\nstatic void reg_new_isa(std::string isa,\n std::string type,\n std::string dim,\n int64_t loop_time,\n int64_t comp_pl,\n void *params,\n void (*bench)(int64_t, void*))\n{\n cpubm_t new_one;\n new_one.isa = isa;\n new_one.type = type;\n new_one.dim = dim;\n new_one.loop_time = loop_time;\n new_one.comp_pl = comp_pl;\n new_one.params = params;\n new_one.bench = bench;\n\n bm_list.push_back(new_one);\n}\n\nstatic void thread_func(void *params)\n{\n cpubm_t *bm = (cpubm_t*)params;\n if (bm->params)\n {\n bm->bench(bm->loop_time, bm->params);\n }\n else\n {\n bm->bench(bm->loop_time, NULL);\n }\n}\n\nstatic void cpubm_e2k_one(smtl_handle sh,\n cpubm_t &item,\n Table &table)\n{\n struct timespec start, end;\n double time_used, perf;\n char perfUnit = 'G';\n\n int i;\n int num_threads = smtl_num_threads(sh);\n\n // warm up\n for (i = 0; i < num_threads; i++)\n {\n smtl_add_task(sh, thread_func, (void*)&item);\n }\n smtl_begin_tasks(sh);\n smtl_wait_tasks_finished(sh);\n\n clock_gettime(CLOCK_MONOTONIC_RAW, &start);\n for (i = 0; i < num_threads; i++)\n {\n smtl_add_task(sh, thread_func, (void*)&item);\n }\n smtl_begin_tasks(sh);\n smtl_wait_tasks_finished(sh);\n clock_gettime(CLOCK_MONOTONIC_RAW, &end);\n\n time_used = get_time(&start, &end);\n perf = item.loop_time * item.comp_pl * num_threads /\n time_used;\n if (perf > 1e12)\n {\n perfUnit = 'T';\n perf /= 1e12;\n }\n else\n {\n perf /= 1e9;\n }\n\n stringstream ss;\n ss << std::setprecision(5) << perf << \" \" << perfUnit << item.dim;\n\n vector cont;\n cont.resize(3);\n cont[0] = item.isa;\n cont[1] = item.type;\n cont[2] = ss.str();\n table.addOneItem(cont);\n}\n\nstatic void cpubm_do_bench(std::vector &set_of_threads,\n uint32_t idle_time)\n{\n int i;\n\n if (bm_list.size() > 0)\n {\n int num_threads = set_of_threads.size();\n\n printf(\"Number Threads: %d\\n\", num_threads);\n printf(\"Thread Pool Binding:\");\n for (i = 0; i < num_threads; i++)\n {\n printf(\" %d\", set_of_threads[i]);\n }\n printf(\"\\n\");\n\n // set table head\n vector ti;\n ti.resize(3);\n ti[0] = \"Instruction Set\";\n ti[1] = \"Core Computation\";\n ti[2] = \"Peak Performance\";\n\n Table table;\n table.setColumnNum(3);\n table.addOneItem(ti);\n\n // set thread pool\n smtl_handle sh;\n smtl_init(&sh, set_of_threads);\n\n // traverse task list\n cpubm_e2k_one(sh, bm_list[0], table);\n for (i = 1; i < bm_list.size(); i++)\n {\n sleep(idle_time);\n cpubm_e2k_one(sh, bm_list[i], table);\n }\n\n table.print();\n\n smtl_fini(sh);\n }\n}\n\nstatic void parse_thread_pool(char *sets,\n vector &set_of_threads)\n{\n if (sets[0] != '[')\n {\n return;\n }\n int pos = 1;\n int left = 0, right = 0;\n int state = 0;\n while (sets[pos] != ']' && sets[pos] != '\\0')\n {\n if (state == 0)\n {\n if (sets[pos] >= '0' && sets[pos] <= '9')\n {\n left *= 10;\n left += (int)(sets[pos] - '0');\n }\n else if (sets[pos] == ',')\n {\n set_of_threads.push_back(left);\n left = 0;\n }\n else if (sets[pos] == '-')\n {\n right = 0;\n state = 1;\n }\n }\n else if (state == 1)\n {\n if (sets[pos] >= '0' && sets[pos] <= '9')\n {\n right *= 10;\n right += (int)(sets[pos] - '0');\n }\n else if (sets[pos] == ',')\n {\n int i;\n for (i = left; i <= right; i++)\n {\n set_of_threads.push_back(i);\n }\n left = 0;\n state = 0;\n }\n }\n pos++;\n }\n if (sets[pos] != ']')\n {\n return;\n }\n if (state == 0)\n {\n set_of_threads.push_back(left);\n }\n else if (state == 1)\n {\n int i;\n for (i = left; i <= right; i++)\n {\n set_of_threads.push_back(i);\n }\n }\n}\n\nstatic void cpufp_register_isa()\n{\n // NOTE: do not use values greater than UINT32_MAX\n const uint32_t loop_time = 0x20000000;\n\n#if __iset__ >= 6\n reg_new_isa(\"v6\", \"FMA(f32,f32,f32)\", \"FLOPS\",\n loop_time, 48LL, NULL, bench_qpfmas);\n reg_new_isa(\"v6\", \"FMA(f64,f64,f64)\", \"FLOPS\",\n loop_time, 24LL, NULL, bench_qpfmad);\n#endif\n\n#if __iset__ >= 5\n reg_new_isa(\"v5\", \"ADD(f32,MUL(f32,f32))\", \"FLOPS\",\n loop_time, 48LL, NULL, bench_qpfmul_adds);\n reg_new_isa(\"v5\", \"ADD(f64,MUL(f64,f64))\", \"FLOPS\",\n loop_time, 24LL, NULL, bench_qpfmul_addd);\n#endif\n\n#if __iset__ >= 4\n reg_new_isa(\"v4\", \"ADD(f32,MUL(f32,f32))\", \"FLOPS\",\n loop_time, 24LL, NULL, bench_pfmul_adds);\n reg_new_isa(\"v4\", \"ADD(f64,MUL(f64,f64))\", \"FLOPS\",\n loop_time, 12LL, NULL, bench_fmul_addd);\n#else\n reg_new_isa(\"v1\", \"ADD(f32,MUL(f32,f32))\", \"FLOPS\",\n loop_time, 16LL, NULL, bench_pfmul_adds);\n reg_new_isa(\"v1\", \"ADD(f64,MUL(f64,f64))\", \"FLOPS\",\n loop_time, 8LL, NULL, bench_fmul_addd);\n#endif\n}\n\nint main(int argc, char *argv[])\n{\n vector set_of_threads;\n uint32_t idle_time = 0;\n\n bool params_enough = false;\n\n int i;\n for (i = 1; i < argc; i++)\n {\n if (strncmp(argv[i], \"--thread_pool=\", 14) == 0)\n {\n parse_thread_pool(argv[i] + 14, set_of_threads);\n params_enough = true;\n }\n else if (strncmp(argv[i], \"--idle_time=\", 12) == 0)\n {\n idle_time = (uint32_t)atoi(argv[i] + 12);\n }\n }\n if (!params_enough)\n {\n fprintf(stderr, \"Error: You must set --thread_pool parameter.\\n\");\n fprintf(stderr, \"You may also set --idle_time parameter.\\n\");\n fprintf(stderr, \"Usage: %s --thread_pool=[xxx] --idle_time=yyy\\n\", argv[0]);\n fprintf(stderr, \"[xxx] indicates all cores to benchmark.\\n\");\n fprintf(stderr, \"Example: [0,3,5-8,13-15].\\n\");\n fprintf(stderr, \"idle_time is the interval time(s) between every two benchmarks.\\n\");\n fprintf(stderr, \"idle_time parameter can be ignored, the default value is 0s.\\n\");\n fprintf(stderr, \"Notice: there must NOT be any spaces.\\n\");\n exit(0);\n }\n\n cpufp_register_isa();\n cpubm_do_bench(set_of_threads, idle_time);\n\n return 0;\n}\n" }, { "path": "loongarch64/asm/_FP_DP_.S", "content": ".globl fp64_fmadd_f64f64f64\nfp64_fmadd_f64f64f64:\n\tmovgr2fr.d $f0, $r0\n\tmovgr2fr.d $f1, $r0\n\tmovgr2fr.d $f2, $r0\n\tmovgr2fr.d $f3, $r0\n\tmovgr2fr.d $f4, $r0\n\tmovgr2fr.d $f5, $r0\n\tmovgr2fr.d $f6, $r0\n\tmovgr2fr.d $f7, $r0\n\tmovgr2fr.d $f8, $r0\n\tmovgr2fr.d $f9, $r0\n\tmovgr2fr.d $f10, $r0\n\tmovgr2fr.d $f11, $r0\n\tmovgr2fr.d $f12, $r0\n\tmovgr2fr.d $f13, $r0\n\tmovgr2fr.d $f14, $r0\n\tmovgr2fr.d $f15, $r0\n\tmovgr2fr.d $f16, $r0\n.fp64.fmadd.f64f64f64:\n fmadd.d $f0, $f16, $f16, $f0\n fmadd.d $f1, $f16, $f16, $f1\n fmadd.d $f2, $f16, $f16, $f2\n fmadd.d $f3, $f16, $f16, $f3\n fmadd.d $f4, $f16, $f16, $f4\n fmadd.d $f5, $f16, $f16, $f5\n fmadd.d $f6, $f16, $f16, $f6\n fmadd.d $f7, $f16, $f16, $f7\n fmadd.d $f8, $f16, $f16, $f8\n fmadd.d $f9, $f16, $f16, $f9\n fmadd.d $f10, $f16, $f16, $f10\n fmadd.d $f11, $f16, $f16, $f11\n fmadd.d $f12, $f16, $f16, $f12\n fmadd.d $f13, $f16, $f16, $f13\n fmadd.d $f14, $f16, $f16, $f14\n fmadd.d $f15, $f16, $f16, $f15\n addi.d $a0, $a0, -1\n bne $a0, $r0, .fp64.fmadd.f64f64f64\n\tjr $r1\n\n" }, { "path": "loongarch64/asm/_FP_SP_.S", "content": ".globl fp32_fmadd_f32f32f32\nfp32_fmadd_f32f32f32:\n\tmovgr2fr.w $f0, $r0\n\tmovgr2fr.w $f1, $r0\n\tmovgr2fr.w $f2, $r0\n\tmovgr2fr.w $f3, $r0\n\tmovgr2fr.w $f4, $r0\n\tmovgr2fr.w $f5, $r0\n\tmovgr2fr.w $f6, $r0\n\tmovgr2fr.w $f7, $r0\n\tmovgr2fr.w $f8, $r0\n\tmovgr2fr.w $f9, $r0\n\tmovgr2fr.w $f10, $r0\n\tmovgr2fr.w $f11, $r0\n\tmovgr2fr.w $f12, $r0\n\tmovgr2fr.w $f13, $r0\n\tmovgr2fr.w $f14, $r0\n\tmovgr2fr.w $f15, $r0\n\tmovgr2fr.w $f16, $r0\n.fp32.fmadd.f32f32f32:\n fmadd.s $f0, $f16, $f16, $f0\n fmadd.s $f1, $f16, $f16, $f1\n fmadd.s $f2, $f16, $f16, $f2\n fmadd.s $f3, $f16, $f16, $f3\n fmadd.s $f4, $f16, $f16, $f4\n fmadd.s $f5, $f16, $f16, $f5\n fmadd.s $f6, $f16, $f16, $f6\n fmadd.s $f7, $f16, $f16, $f7\n fmadd.s $f8, $f16, $f16, $f8\n fmadd.s $f9, $f16, $f16, $f9\n fmadd.s $f10, $f16, $f16, $f10\n fmadd.s $f11, $f16, $f16, $f11\n fmadd.s $f12, $f16, $f16, $f12\n fmadd.s $f13, $f16, $f16, $f13\n fmadd.s $f14, $f16, $f16, $f14\n fmadd.s $f15, $f16, $f16, $f15\n addi.d $a0, $a0, -1\n bne $a0, $r0, .fp32.fmadd.f32f32f32\n\tjr $r1\n\n" }, { "path": "loongarch64/asm/_LASX_.S", "content": ".globl lasx_fp32_fmadd_f32f32f32\n.globl lasx_fp64_fmadd_f64f64f64\n.globl lasx_fp32_add_mul_f32f32_f32\n.globl lasx_fp64_add_mul_f64f64_f64\n\nlasx_fp32_fmadd_f32f32f32:\n xvxor.v $xr0, $xr0, $xr0\n xvxor.v $xr1, $xr1, $xr1\n xvxor.v $xr2, $xr2, $xr2\n xvxor.v $xr3, $xr3, $xr3\n xvxor.v $xr4, $xr4, $xr4\n xvxor.v $xr5, $xr5, $xr5\n xvxor.v $xr6, $xr6, $xr6\n xvxor.v $xr7, $xr7, $xr7\n xvxor.v $xr8, $xr8, $xr8\n xvxor.v $xr9, $xr9, $xr9\n xvxor.v $xr10, $xr10, $xr10\n xvxor.v $xr11, $xr11, $xr11\n xvxor.v $xr12, $xr12, $xr12\n xvxor.v $xr13, $xr13, $xr13\n xvxor.v $xr14, $xr14, $xr14\n xvxor.v $xr15, $xr15, $xr15\n xvxor.v $xr16, $xr16, $xr16\n.lasx.fp32.fmadd.f32f32f32:\n xvfmadd.s $xr0, $xr16, $xr16, $xr0\n xvfmadd.s $xr1, $xr16, $xr16, $xr1\n xvfmadd.s $xr2, $xr16, $xr16, $xr2\n xvfmadd.s $xr3, $xr16, $xr16, $xr3\n xvfmadd.s $xr4, $xr16, $xr16, $xr4\n xvfmadd.s $xr5, $xr16, $xr16, $xr5\n xvfmadd.s $xr6, $xr16, $xr16, $xr6\n xvfmadd.s $xr7, $xr16, $xr16, $xr7\n xvfmadd.s $xr8, $xr16, $xr16, $xr8\n xvfmadd.s $xr9, $xr16, $xr16, $xr9\n xvfmadd.s $xr10, $xr16, $xr16, $xr10\n xvfmadd.s $xr11, $xr16, $xr16, $xr11\n xvfmadd.s $xr12, $xr16, $xr16, $xr12\n xvfmadd.s $xr13, $xr16, $xr16, $xr13\n xvfmadd.s $xr14, $xr16, $xr16, $xr14\n xvfmadd.s $xr15, $xr16, $xr16, $xr15\n addi.d $a0, $a0, -1\n bne $a0, $r0, .lasx.fp32.fmadd.f32f32f32\n\tjr $r1\n\nlasx_fp64_fmadd_f64f64f64:\n xvxor.v $xr0, $xr0, $xr0\n xvxor.v $xr1, $xr1, $xr1\n xvxor.v $xr2, $xr2, $xr2\n xvxor.v $xr3, $xr3, $xr3\n xvxor.v $xr4, $xr4, $xr4\n xvxor.v $xr5, $xr5, $xr5\n xvxor.v $xr6, $xr6, $xr6\n xvxor.v $xr7, $xr7, $xr7\n xvxor.v $xr8, $xr8, $xr8\n xvxor.v $xr9, $xr9, $xr9\n xvxor.v $xr10, $xr10, $xr10\n xvxor.v $xr11, $xr11, $xr11\n xvxor.v $xr12, $xr12, $xr12\n xvxor.v $xr13, $xr13, $xr13\n xvxor.v $xr14, $xr14, $xr14\n xvxor.v $xr15, $xr15, $xr15\n xvxor.v $xr16, $xr16, $xr16\n.lasx.fp64.fmadd.f64f64f64:\n xvfmadd.d $xr0, $xr16, $xr16, $xr0\n xvfmadd.d $xr1, $xr16, $xr16, $xr1\n xvfmadd.d $xr2, $xr16, $xr16, $xr2\n xvfmadd.d $xr3, $xr16, $xr16, $xr3\n xvfmadd.d $xr4, $xr16, $xr16, $xr4\n xvfmadd.d $xr5, $xr16, $xr16, $xr5\n xvfmadd.d $xr6, $xr16, $xr16, $xr6\n xvfmadd.d $xr7, $xr16, $xr16, $xr7\n xvfmadd.d $xr8, $xr16, $xr16, $xr8\n xvfmadd.d $xr9, $xr16, $xr16, $xr9\n xvfmadd.d $xr10, $xr16, $xr16, $xr10\n xvfmadd.d $xr11, $xr16, $xr16, $xr11\n xvfmadd.d $xr12, $xr16, $xr16, $xr12\n xvfmadd.d $xr13, $xr16, $xr16, $xr13\n xvfmadd.d $xr14, $xr16, $xr16, $xr14\n xvfmadd.d $xr15, $xr16, $xr16, $xr15\n addi.d $a0, $a0, -1\n bne $a0, $r0, .lasx.fp64.fmadd.f64f64f64\n\tjr $r1\n\nlasx_fp32_add_mul_f32f32_f32:\n xvxor.v $xr0, $xr0, $xr0\n xvxor.v $xr1, $xr1, $xr1\n xvxor.v $xr2, $xr2, $xr2\n xvxor.v $xr3, $xr3, $xr3\n xvxor.v $xr4, $xr4, $xr4\n xvxor.v $xr5, $xr5, $xr5\n xvxor.v $xr6, $xr6, $xr6\n xvxor.v $xr7, $xr7, $xr7\n xvxor.v $xr8, $xr8, $xr8\n xvxor.v $xr9, $xr9, $xr9\n xvxor.v $xr10, $xr10, $xr10\n xvxor.v $xr11, $xr11, $xr11\n xvxor.v $xr12, $xr12, $xr12\n xvxor.v $xr13, $xr13, $xr13\n xvxor.v $xr14, $xr14, $xr14\n xvxor.v $xr15, $xr15, $xr15\n xvxor.v $xr16, $xr16, $xr16\n xvxor.v $xr17, $xr17, $xr17\n xvxor.v $xr18, $xr18, $xr18\n xvxor.v $xr19, $xr19, $xr19\n xvxor.v $xr20, $xr20, $xr20\n xvxor.v $xr21, $xr21, $xr21\n xvxor.v $xr22, $xr22, $xr22\n xvxor.v $xr23, $xr23, $xr23\n xvxor.v $xr24, $xr24, $xr24\n.lasx.fp32.add.mul.f32f32.f32:\n xvfmul.s $xr0, $xr24, $xr24\n xvfadd.s $xr1, $xr24, $xr24\n xvfmul.s $xr2, $xr24, $xr24\n xvfadd.s $xr3, $xr24, $xr24\n xvfmul.s $xr4, $xr24, $xr24\n xvfadd.s $xr5, $xr24, $xr24\n xvfmul.s $xr6, $xr24, $xr24\n xvfadd.s $xr7, $xr24, $xr24\n xvfmul.s $xr8, $xr24, $xr24\n xvfadd.s $xr9, $xr24, $xr24\n xvfmul.s $xr10, $xr24, $xr24\n xvfadd.s $xr11, $xr24, $xr24\n xvfmul.s $xr12, $xr24, $xr24\n xvfadd.s $xr13, $xr24, $xr24\n xvfmul.s $xr14, $xr24, $xr24\n xvfadd.s $xr15, $xr24, $xr24\n xvfmul.s $xr16, $xr24, $xr24\n xvfadd.s $xr17, $xr24, $xr24\n xvfmul.s $xr18, $xr24, $xr24\n xvfadd.s $xr19, $xr24, $xr24\n xvfmul.s $xr20, $xr24, $xr24\n xvfadd.s $xr21, $xr24, $xr24\n xvfmul.s $xr22, $xr24, $xr24\n xvfadd.s $xr23, $xr24, $xr24\n addi.d $a0, $a0, -1\n bne $a0, $r0, .lasx.fp32.add.mul.f32f32.f32\n\tjr $r1\n\nlasx_fp64_add_mul_f64f64_f64:\n xvxor.v $xr0, $xr0, $xr0\n xvxor.v $xr1, $xr1, $xr1\n xvxor.v $xr2, $xr2, $xr2\n xvxor.v $xr3, $xr3, $xr3\n xvxor.v $xr4, $xr4, $xr4\n xvxor.v $xr5, $xr5, $xr5\n xvxor.v $xr6, $xr6, $xr6\n xvxor.v $xr7, $xr7, $xr7\n xvxor.v $xr8, $xr8, $xr8\n xvxor.v $xr9, $xr9, $xr9\n xvxor.v $xr10, $xr10, $xr10\n xvxor.v $xr11, $xr11, $xr11\n xvxor.v $xr12, $xr12, $xr12\n xvxor.v $xr13, $xr13, $xr13\n xvxor.v $xr14, $xr14, $xr14\n xvxor.v $xr15, $xr15, $xr15\n xvxor.v $xr16, $xr16, $xr16\n xvxor.v $xr17, $xr17, $xr17\n xvxor.v $xr18, $xr18, $xr18\n xvxor.v $xr19, $xr19, $xr19\n xvxor.v $xr20, $xr20, $xr20\n xvxor.v $xr21, $xr21, $xr21\n xvxor.v $xr22, $xr22, $xr22\n xvxor.v $xr23, $xr23, $xr23\n xvxor.v $xr24, $xr24, $xr24\n.lasx.fp64.add.mul.f64f64.f64:\n xvfmul.d $xr0, $xr24, $xr24\n xvfadd.d $xr1, $xr24, $xr24\n xvfmul.d $xr2, $xr24, $xr24\n xvfadd.d $xr3, $xr24, $xr24\n xvfmul.d $xr4, $xr24, $xr24\n xvfadd.d $xr5, $xr24, $xr24\n xvfmul.d $xr6, $xr24, $xr24\n xvfadd.d $xr7, $xr24, $xr24\n xvfmul.d $xr8, $xr24, $xr24\n xvfadd.d $xr9, $xr24, $xr24\n xvfmul.d $xr10, $xr24, $xr24\n xvfadd.d $xr11, $xr24, $xr24\n xvfmul.d $xr12, $xr24, $xr24\n xvfadd.d $xr13, $xr24, $xr24\n xvfmul.d $xr14, $xr24, $xr24\n xvfadd.d $xr15, $xr24, $xr24\n xvfmul.d $xr16, $xr24, $xr24\n xvfadd.d $xr17, $xr24, $xr24\n xvfmul.d $xr18, $xr24, $xr24\n xvfadd.d $xr19, $xr24, $xr24\n xvfmul.d $xr20, $xr24, $xr24\n xvfadd.d $xr21, $xr24, $xr24\n xvfmul.d $xr22, $xr24, $xr24\n xvfadd.d $xr23, $xr24, $xr24\n addi.d $a0, $a0, -1\n bne $a0, $r0, .lasx.fp64.add.mul.f64f64.f64\n\tjr $r1\n\n" }, { "path": "loongarch64/asm/_LSX_.S", "content": ".globl lsx_fp32_fmadd_f32f32f32\n.globl lsx_fp64_fmadd_f64f64f64\n.globl lsx_fp32_add_mul_f32f32_f32\n.globl lsx_fp64_add_mul_f64f64_f64\n\nlsx_fp32_fmadd_f32f32f32:\n vxor.v $vr0, $vr0, $vr0\n vxor.v $vr1, $vr1, $vr1\n vxor.v $vr2, $vr2, $vr2\n vxor.v $vr3, $vr3, $vr3\n vxor.v $vr4, $vr4, $vr4\n vxor.v $vr5, $vr5, $vr5\n vxor.v $vr6, $vr6, $vr6\n vxor.v $vr7, $vr7, $vr7\n vxor.v $vr8, $vr8, $vr8\n vxor.v $vr9, $vr9, $vr9\n vxor.v $vr10, $vr10, $vr10\n vxor.v $vr11, $vr11, $vr11\n vxor.v $vr12, $vr12, $vr12\n vxor.v $vr13, $vr13, $vr13\n vxor.v $vr14, $vr14, $vr14\n vxor.v $vr15, $vr15, $vr15\n vxor.v $vr16, $vr16, $vr16\n.lsx.fp32.fmadd.f32f32f32:\n vfmadd.s $vr0, $vr16, $vr16, $vr0\n vfmadd.s $vr1, $vr16, $vr16, $vr1\n vfmadd.s $vr2, $vr16, $vr16, $vr2\n vfmadd.s $vr3, $vr16, $vr16, $vr3\n vfmadd.s $vr4, $vr16, $vr16, $vr4\n vfmadd.s $vr5, $vr16, $vr16, $vr5\n vfmadd.s $vr6, $vr16, $vr16, $vr6\n vfmadd.s $vr7, $vr16, $vr16, $vr7\n vfmadd.s $vr8, $vr16, $vr16, $vr8\n vfmadd.s $vr9, $vr16, $vr16, $vr9\n vfmadd.s $vr10, $vr16, $vr16, $vr10\n vfmadd.s $vr11, $vr16, $vr16, $vr11\n vfmadd.s $vr12, $vr16, $vr16, $vr12\n vfmadd.s $vr13, $vr16, $vr16, $vr13\n vfmadd.s $vr14, $vr16, $vr16, $vr14\n vfmadd.s $vr15, $vr16, $vr16, $vr15\n addi.d $a0, $a0, -1\n bne $a0, $r0, .lsx.fp32.fmadd.f32f32f32\n\tjr $r1\n\nlsx_fp64_fmadd_f64f64f64:\n vxor.v $vr0, $vr0, $vr0\n vxor.v $vr1, $vr1, $vr1\n vxor.v $vr2, $vr2, $vr2\n vxor.v $vr3, $vr3, $vr3\n vxor.v $vr4, $vr4, $vr4\n vxor.v $vr5, $vr5, $vr5\n vxor.v $vr6, $vr6, $vr6\n vxor.v $vr7, $vr7, $vr7\n vxor.v $vr8, $vr8, $vr8\n vxor.v $vr9, $vr9, $vr9\n vxor.v $vr10, $vr10, $vr10\n vxor.v $vr11, $vr11, $vr11\n vxor.v $vr12, $vr12, $vr12\n vxor.v $vr13, $vr13, $vr13\n vxor.v $vr14, $vr14, $vr14\n vxor.v $vr15, $vr15, $vr15\n vxor.v $vr16, $vr16, $vr16\n.lsx.fp64.fmadd.f64f64f64:\n vfmadd.d $vr0, $vr16, $vr16, $vr0\n vfmadd.d $vr1, $vr16, $vr16, $vr1\n vfmadd.d $vr2, $vr16, $vr16, $vr2\n vfmadd.d $vr3, $vr16, $vr16, $vr3\n vfmadd.d $vr4, $vr16, $vr16, $vr4\n vfmadd.d $vr5, $vr16, $vr16, $vr5\n vfmadd.d $vr6, $vr16, $vr16, $vr6\n vfmadd.d $vr7, $vr16, $vr16, $vr7\n vfmadd.d $vr8, $vr16, $vr16, $vr8\n vfmadd.d $vr9, $vr16, $vr16, $vr9\n vfmadd.d $vr10, $vr16, $vr16, $vr10\n vfmadd.d $vr11, $vr16, $vr16, $vr11\n vfmadd.d $vr12, $vr16, $vr16, $vr12\n vfmadd.d $vr13, $vr16, $vr16, $vr13\n vfmadd.d $vr14, $vr16, $vr16, $vr14\n vfmadd.d $vr15, $vr16, $vr16, $vr15\n addi.d $a0, $a0, -1\n bne $a0, $r0, .lsx.fp64.fmadd.f64f64f64\n\tjr $r1\n\nlsx_fp32_add_mul_f32f32_f32:\n vxor.v $vr0, $vr0, $vr0\n vxor.v $vr1, $vr1, $vr1\n vxor.v $vr2, $vr2, $vr2\n vxor.v $vr3, $vr3, $vr3\n vxor.v $vr4, $vr4, $vr4\n vxor.v $vr5, $vr5, $vr5\n vxor.v $vr6, $vr6, $vr6\n vxor.v $vr7, $vr7, $vr7\n vxor.v $vr8, $vr8, $vr8\n vxor.v $vr9, $vr9, $vr9\n vxor.v $vr10, $vr10, $vr10\n vxor.v $vr11, $vr11, $vr11\n vxor.v $vr12, $vr12, $vr12\n vxor.v $vr13, $vr13, $vr13\n vxor.v $vr14, $vr14, $vr14\n vxor.v $vr15, $vr15, $vr15\n vxor.v $vr16, $vr16, $vr16\n vxor.v $vr17, $vr17, $vr17\n vxor.v $vr18, $vr18, $vr18\n vxor.v $vr19, $vr19, $vr19\n vxor.v $vr20, $vr20, $vr20\n vxor.v $vr21, $vr21, $vr21\n vxor.v $vr22, $vr22, $vr22\n vxor.v $vr23, $vr23, $vr23\n vxor.v $vr24, $vr24, $vr24\n.lsx.fp32.add.mul.f32f32.f32:\n vfmul.s $vr0, $vr24, $vr24\n vfadd.s $vr1, $vr24, $vr24\n vfmul.s $vr2, $vr24, $vr24\n vfadd.s $vr3, $vr24, $vr24\n vfmul.s $vr4, $vr24, $vr24\n vfadd.s $vr5, $vr24, $vr24\n vfmul.s $vr6, $vr24, $vr24\n vfadd.s $vr7, $vr24, $vr24\n vfmul.s $vr8, $vr24, $vr24\n vfadd.s $vr9, $vr24, $vr24\n vfmul.s $vr10, $vr24, $vr24\n vfadd.s $vr11, $vr24, $vr24\n vfmul.s $vr12, $vr24, $vr24\n vfadd.s $vr13, $vr24, $vr24\n vfmul.s $vr14, $vr24, $vr24\n vfadd.s $vr15, $vr24, $vr24\n vfmul.s $vr16, $vr24, $vr24\n vfadd.s $vr17, $vr24, $vr24\n vfmul.s $vr18, $vr24, $vr24\n vfadd.s $vr19, $vr24, $vr24\n vfmul.s $vr20, $vr24, $vr24\n vfadd.s $vr21, $vr24, $vr24\n vfmul.s $vr22, $vr24, $vr24\n vfadd.s $vr23, $vr24, $vr24\n addi.d $a0, $a0, -1\n bne $a0, $r0, .lsx.fp32.add.mul.f32f32.f32\n\tjr $r1\n\nlsx_fp64_add_mul_f64f64_f64:\n vxor.v $vr0, $vr0, $vr0\n vxor.v $vr1, $vr1, $vr1\n vxor.v $vr2, $vr2, $vr2\n vxor.v $vr3, $vr3, $vr3\n vxor.v $vr4, $vr4, $vr4\n vxor.v $vr5, $vr5, $vr5\n vxor.v $vr6, $vr6, $vr6\n vxor.v $vr7, $vr7, $vr7\n vxor.v $vr8, $vr8, $vr8\n vxor.v $vr9, $vr9, $vr9\n vxor.v $vr10, $vr10, $vr10\n vxor.v $vr11, $vr11, $vr11\n vxor.v $vr12, $vr12, $vr12\n vxor.v $vr13, $vr13, $vr13\n vxor.v $vr14, $vr14, $vr14\n vxor.v $vr15, $vr15, $vr15\n vxor.v $vr16, $vr16, $vr16\n vxor.v $vr17, $vr17, $vr17\n vxor.v $vr18, $vr18, $vr18\n vxor.v $vr19, $vr19, $vr19\n vxor.v $vr20, $vr20, $vr20\n vxor.v $vr21, $vr21, $vr21\n vxor.v $vr22, $vr22, $vr22\n vxor.v $vr23, $vr23, $vr23\n vxor.v $vr24, $vr24, $vr24\n.lsx.fp64.add.mul.f64f64.f64:\n vfmul.d $vr0, $vr24, $vr24\n vfadd.d $vr1, $vr24, $vr24\n vfmul.d $vr2, $vr24, $vr24\n vfadd.d $vr3, $vr24, $vr24\n vfmul.d $vr4, $vr24, $vr24\n vfadd.d $vr5, $vr24, $vr24\n vfmul.d $vr6, $vr24, $vr24\n vfadd.d $vr7, $vr24, $vr24\n vfmul.d $vr8, $vr24, $vr24\n vfadd.d $vr9, $vr24, $vr24\n vfmul.d $vr10, $vr24, $vr24\n vfadd.d $vr11, $vr24, $vr24\n vfmul.d $vr12, $vr24, $vr24\n vfadd.d $vr13, $vr24, $vr24\n vfmul.d $vr14, $vr24, $vr24\n vfadd.d $vr15, $vr24, $vr24\n vfmul.d $vr16, $vr24, $vr24\n vfadd.d $vr17, $vr24, $vr24\n vfmul.d $vr18, $vr24, $vr24\n vfadd.d $vr19, $vr24, $vr24\n vfmul.d $vr20, $vr24, $vr24\n vfadd.d $vr21, $vr24, $vr24\n vfmul.d $vr22, $vr24, $vr24\n vfadd.d $vr23, $vr24, $vr24\n addi.d $a0, $a0, -1\n bne $a0, $r0, .lsx.fp64.add.mul.f64f64.f64\n\tjr $r1\n\n" }, { "path": "loongarch64/cpufp.cpp", "content": "#include \"table.hpp\"\n#include \"smtl.hpp\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\nusing namespace std;\n\nextern \"C\"\n{\n#ifdef _FP_SP_\n void fp32_fmadd_f32f32f32(int64_t);\n#endif\n\n#ifdef _FP_DP_\n void fp64_fmadd_f64f64f64(int64_t);\n#endif\n\n#ifdef _LSX_\n void lsx_fp32_fmadd_f32f32f32(int64_t);\n void lsx_fp64_fmadd_f64f64f64(int64_t);\n\n void lsx_fp32_add_mul_f32f32_f32(int64_t);\n void lsx_fp64_add_mul_f64f64_f64(int64_t);\n#endif\n\n#ifdef _LASX_\n void lasx_fp32_fmadd_f32f32f32(int64_t);\n void lasx_fp64_fmadd_f64f64f64(int64_t);\n\n void lasx_fp32_add_mul_f32f32_f32(int64_t);\n void lasx_fp64_add_mul_f64f64_f64(int64_t);\n#endif\n}\n\ntypedef struct\n{\n std::string isa;\n std::string vlen;\n std::string type;\n std::string dim;\n int64_t loop_time;\n int64_t comp_pl;\n void (*bench)(int64_t);\n} cpubm_t;\nstatic int num_simd_256b = 0;\nstatic int num_simd_128b = 0;\nstatic int num_scalar = 0;\nstatic std::vector bm_list;\n\nstatic double get_time(struct timespec *start,\n struct timespec *end)\n{\n return end->tv_sec - start->tv_sec +\n (end->tv_nsec - start->tv_nsec) * 1e-9;\n}\n\nstatic void reg_new_isa(std::string isa,\n std::string vlen,\n std::string type,\n std::string dim,\n int64_t loop_time,\n int64_t comp_pl,\n void (*bench)(int64_t))\n{\n cpubm_t new_one;\n new_one.isa = isa;\n new_one.vlen = vlen;\n new_one.type = type;\n new_one.dim = dim;\n new_one.loop_time = loop_time;\n new_one.comp_pl = comp_pl;\n new_one.bench = bench;\n\n bm_list.push_back(new_one);\n}\n\nstatic void thread_func(void *params)\n{\n cpubm_t *bm = (cpubm_t*)params;\n bm->bench(bm->loop_time);\n}\n\nstatic void cpubm_x64_one(smtl_handle sh,\n cpubm_t &item,\n Table &table)\n{\n struct timespec start, end;\n double time_used, perf;\n char perfUnit = 'G';\n\n int i;\n int num_threads = smtl_num_threads(sh);\n\n // warm up\n for (i = 0; i < num_threads; i++)\n {\n smtl_add_task(sh, thread_func, (void*)&item);\n }\n smtl_begin_tasks(sh);\n smtl_wait_tasks_finished(sh);\n\n clock_gettime(CLOCK_MONOTONIC_RAW, &start);\n for (i = 0; i < num_threads; i++)\n {\n smtl_add_task(sh, thread_func, (void*)&item);\n }\n smtl_begin_tasks(sh);\n smtl_wait_tasks_finished(sh);\n clock_gettime(CLOCK_MONOTONIC_RAW, &end);\n\n time_used = get_time(&start, &end);\n perf = item.loop_time * item.comp_pl * num_threads /\n time_used;\n if (perf > 1e12)\n {\n perfUnit = 'T';\n perf /= 1e12;\n }\n else\n {\n perf /= 1e9;\n }\n\n stringstream ss;\n ss << std::setprecision(5) << perf << \" \" << perfUnit << item.dim;\n\n std::vector cont;\n cont.resize(4);\n cont[0] = item.isa;\n cont[1] = item.vlen;\n cont[2] = item.type;\n cont[3] = ss.str();\n table.addOneItem(cont);\n}\n\nstatic void cpubm_do_bench(std::vector &set_of_threads,\n uint32_t idle_time)\n{\n int i;\n\n if (bm_list.size() > 0)\n {\n int num_threads = set_of_threads.size();\n\n printf(\"Number Threads: %d\\n\", num_threads);\n printf(\"Thread Pool Binding:\");\n for (i = 0; i < num_threads; i++)\n {\n printf(\" %d\", set_of_threads[i]);\n }\n printf(\"\\n\");\n\n // set table head\n std::vector ti;\n ti.resize(4);\n ti[0] = \"Instruction Set\";\n ti[1] = \"Vector Length\";\n ti[2] = \"Core Computation\";\n ti[3] = \"Peak Performance\";\n\n Table table;\n table.setColumnNum(4);\n table.addOneItem(ti);\n\n // set thread pool\n smtl_handle sh;\n smtl_init(&sh, set_of_threads);\n\n // traverse task list\n int bm_idx = 0;\n if (num_simd_256b)\n {\n table.addSeparator();\n for (i = 0; i < num_simd_256b; i++)\n {\n sleep(idle_time);\n cpubm_x64_one(sh, bm_list[bm_idx], table);\n bm_idx++;\n }\n }\n if (num_simd_128b)\n {\n table.addSeparator();\n for (i = 0; i < num_simd_128b; i++)\n {\n sleep(idle_time);\n cpubm_x64_one(sh, bm_list[bm_idx], table);\n bm_idx++;\n }\n }\n if (num_scalar)\n {\n table.addSeparator();\n for (i = 0; i < num_scalar; i++)\n {\n sleep(idle_time);\n cpubm_x64_one(sh, bm_list[bm_idx], table);\n bm_idx++;\n }\n }\n\n table.print();\n\n smtl_fini(sh);\n }\n}\n\nstatic void parse_thread_pool(char *sets,\n std::vector &set_of_threads)\n{\n if (sets[0] != '[')\n {\n return;\n }\n int pos = 1;\n int left = 0, right = 0;\n int state = 0;\n while (sets[pos] != ']' && sets[pos] != '\\0')\n {\n if (state == 0)\n {\n if (sets[pos] >= '0' && sets[pos] <= '9')\n {\n left *= 10;\n left += (int)(sets[pos] - '0');\n }\n else if (sets[pos] == ',')\n {\n set_of_threads.push_back(left);\n left = 0;\n }\n else if (sets[pos] == '-')\n {\n right = 0;\n state = 1;\n }\n }\n else if (state == 1)\n {\n if (sets[pos] >= '0' && sets[pos] <= '9')\n {\n right *= 10;\n right += (int)(sets[pos] - '0');\n }\n else if (sets[pos] == ',')\n {\n int i;\n for (i = left; i <= right; i++)\n {\n set_of_threads.push_back(i);\n }\n left = 0;\n state = 0;\n }\n }\n pos++;\n }\n if (sets[pos] != ']')\n {\n return;\n }\n if (state == 0)\n {\n set_of_threads.push_back(left);\n }\n else if (state == 1)\n {\n int i;\n for (i = left; i <= right; i++)\n {\n set_of_threads.push_back(i);\n }\n }\n}\n\nstatic void cpufp_register_isa()\n{\n#ifdef _LASX_\n reg_new_isa(\"LASX\", \"256b\", \"fmadd(f32,f32,f32)\", \"FLOPS\",\n 0x20000000LL, 256LL, lasx_fp32_fmadd_f32f32f32);\n reg_new_isa(\"LASX\", \"256b\", \"fmadd(f64,f64,f64)\", \"FLOPS\",\n 0x20000000LL, 128LL, lasx_fp64_fmadd_f64f64f64);\n reg_new_isa(\"LASX\", \"256b\", \"add(mul(f32,f32),f32)\", \"FLOPS\",\n 0x20000000LL, 192LL, lasx_fp32_add_mul_f32f32_f32);\n reg_new_isa(\"LASX\", \"256b\", \"add(mul(f64,f64),f64)\", \"FLOPS\",\n 0x20000000LL, 96LL, lasx_fp64_add_mul_f64f64_f64);\n num_simd_256b += 4;\n#endif\n\n#ifdef _LSX_\n reg_new_isa(\"LSX\", \"128b\", \"fmadd(f32,f32,f32)\", \"FLOPS\",\n 0x20000000LL, 128LL, lsx_fp32_fmadd_f32f32f32);\n reg_new_isa(\"LSX\", \"128b\", \"fmadd(f64,f64,f64)\", \"FLOPS\",\n 0x20000000LL, 64LL, lsx_fp64_fmadd_f64f64f64);\n reg_new_isa(\"LSX\", \"128b\", \"add(mul(f32,f32),f32)\", \"FLOPS\",\n 0x20000000LL, 96LL, lsx_fp32_add_mul_f32f32_f32);\n reg_new_isa(\"LSX\", \"128b\", \"add(mul(f64,f64),f64)\", \"FLOPS\",\n 0x20000000LL, 48LL, lsx_fp64_add_mul_f64f64_f64);\n num_simd_128b += 4;\n#endif\n\n#ifdef _FP_SP_\n reg_new_isa(\"FP_SP\", \"scalar\", \"fmadd(f32,f32,f32)\", \"FLOPS\",\n 0x20000000LL, 32LL, fp32_fmadd_f32f32f32);\n num_scalar++;\n#endif\n\n#ifdef _FP_DP_\n reg_new_isa(\"FP_DP\", \"scalar\", \"fmadd(f64,f64,f64)\", \"FLOPS\",\n 0x20000000LL, 32LL, fp64_fmadd_f64f64f64);\n num_scalar++;\n#endif\n}\n\nint main(int argc, char *argv[])\n{\n std::vector set_of_threads;\n uint32_t idle_time = 0;\n\n bool params_enough = false;\n\n int i;\n for (i = 1; i < argc; i++)\n {\n if (strncmp(argv[i], \"--thread_pool=\", 14) == 0)\n {\n parse_thread_pool(argv[i] + 14, set_of_threads);\n params_enough = true;\n }\n else if (strncmp(argv[i], \"--idle_time=\", 12) == 0)\n {\n idle_time = (uint32_t)atoi(argv[i] + 12);\n }\n }\n if (!params_enough)\n {\n fprintf(stderr, \"Error: You must set --thread_pool parameter.\\n\");\n fprintf(stderr, \"You may also set --idle_time parameter.\\n\");\n fprintf(stderr, \"Usage: %s --thread_pool=[xxx] --idle_time=yyy\\n\", argv[0]);\n fprintf(stderr, \"[xxx] indicates all cores to benchmark.\\n\");\n fprintf(stderr, \"Example: [0,3,5-8,13-15].\\n\");\n fprintf(stderr, \"idle_time is the interval time(s) between every two benchmarks.\\n\");\n fprintf(stderr, \"idle_time parameter can be ignored, the default value is 0s.\\n\");\n fprintf(stderr, \"Notice: there must NOT be any spaces.\\n\");\n exit(0);\n }\n\n cpufp_register_isa();\n cpubm_do_bench(set_of_threads, idle_time);\n\n return 0;\n}\n\n" }, { "path": "loongarch64/cpuid.c", "content": "#include \n#include \n\n#define BIT_TEST(bit_map, pos) (((bit_map) & (0x1 << (pos))) ? 1 : 0)\n\nuint32_t read_cpucfg(uint32_t reg)\n{\n uint32_t val = 0;\n asm volatile(\"cpucfg %0, %1\\n\\t\"\n :\"=r\"(val)\n :\"r\"(reg)\n );\n return val;\n}\n\nint main()\n{\n uint32_t f_0x2 = read_cpucfg(0x2);\n\n if (BIT_TEST(f_0x2, 0))\n {\n if (BIT_TEST(f_0x2, 1))\n {\n printf(\"_FP_SP_\\n\");\n }\n if (BIT_TEST(f_0x2, 2))\n {\n printf(\"_FP_DP_\\n\");\n }\n }\n if (BIT_TEST(f_0x2, 6))\n {\n printf(\"_LSX_\\n\");\n }\n if (BIT_TEST(f_0x2, 7))\n {\n printf(\"_LASX_\\n\");\n }\n\n return 0;\n}\n\n" }, { "path": "riscv64/asm/_IME_.S", "content": ".align 4\n\n.macro preserve_caller_vec\n csrr x5, vtype\n csrr x6, vl\n vsetvli x7, x0, e8, m8\n sub sp, sp, x7\n vse8.v v0, (sp)\n sub sp, sp, x7\n vse8.v v8, (sp)\n sub sp, sp, x7\n vse8.v v16, (sp)\n sub sp, sp, x7\n vse8.v v24, (sp)\n.endm\n\n.macro restore_caller_vec\n vsetvli x7, x0, e8, m8\n vle8.v v24, (sp)\n add sp, sp, x7\n vle8.v v16, (sp)\n add sp, sp, x7\n vle8.v v8, (sp)\n add sp, sp, x7\n vle8.v v0, (sp)\n add sp, sp, x7\n vsetvl x7, x6, x5\n.endm\n\n#ifdef __APPLE__\n.globl _ime_vmadot_s32s8s8\n_ime_vmadot_s32s8s8:\n#else\n.globl ime_vmadot_s32s8s8\nime_vmadot_s32s8s8:\n#endif\n preserve_caller_vec\n vsetvli x7, x0, e8, m8\n vxor.vv v0, v0, v0\n vxor.vv v8, v8, v8\n vxor.vv v16, v16, v16\n vxor.vv v24, v24, v24\n.ime.vmadot.s32s8s8.L1:\n vsetvli x7, x0, e8, m1\n vmadot v4, v0, v1\n vmadot v6, v0, v1\n vmadot v8, v0, v1\n vmadot v10, v0, v1\n vmadot v12, v0, v1\n vmadot v14, v0, v1\n vmadot v16, v0, v1\n addi a0, a0, -1\n vmadot v18, v0, v1\n vmadot v20, v0, v1\n vmadot v22, v0, v1\n vmadot v24, v0, v1\n vmadot v26, v0, v1\n vmadot v28, v0, v1\n vmadot v30, v0, v1\n bnez a0, .ime.vmadot.s32s8s8.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _ime_vmadotu_u32u8u8\n_ime_vmadotu_u32u8u8:\n#else\n.globl ime_vmadotu_u32u8u8\nime_vmadotu_u32u8u8:\n#endif\n preserve_caller_vec\n vsetvli x7, x0, e8, m8\n vxor.vv v0, v0, v0\n vxor.vv v8, v8, v8\n vxor.vv v16, v16, v16\n vxor.vv v24, v24, v24\n.ime.vmadotu.u32u8u8.L1:\n vsetvli x7, x0, e8, m1\n vmadotu v4, v0, v1\n vmadotu v6, v0, v1\n vmadotu v8, v0, v1\n vmadotu v10, v0, v1\n vmadotu v12, v0, v1\n vmadotu v14, v0, v1\n vmadotu v16, v0, v1\n addi a0, a0, -1\n vmadotu v18, v0, v1\n vmadotu v20, v0, v1\n vmadotu v22, v0, v1\n vmadotu v24, v0, v1\n vmadotu v26, v0, v1\n vmadotu v28, v0, v1\n vmadotu v30, v0, v1\n bnez a0, .ime.vmadotu.u32u8u8.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _ime_vmadotus_s32u8s8\n_ime_vmadotus_s32u8s8:\n#else\n.globl ime_vmadotus_s32u8s8\nime_vmadotus_s32u8s8:\n#endif\n preserve_caller_vec\n vsetvli x7, x0, e8, m8\n vxor.vv v0, v0, v0\n vxor.vv v8, v8, v8\n vxor.vv v16, v16, v16\n vxor.vv v24, v24, v24\n.ime.vmadotus.s32u8s8.L1:\n vsetvli x7, x0, e8, m1\n vmadotus v4, v0, v1\n vmadotus v6, v0, v1\n vmadotus v8, v0, v1\n vmadotus v10, v0, v1\n vmadotus v12, v0, v1\n vmadotus v14, v0, v1\n vmadotus v16, v0, v1\n addi a0, a0, -1\n vmadotus v18, v0, v1\n vmadotus v20, v0, v1\n vmadotus v22, v0, v1\n vmadotus v24, v0, v1\n vmadotus v26, v0, v1\n vmadotus v28, v0, v1\n vmadotus v30, v0, v1\n bnez a0, .ime.vmadotus.s32u8s8.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _ime_vmadotsu_s32s8u8\n_ime_vmadotsu_s32s8u8:\n#else\n.globl ime_vmadotsu_s32s8u8\nime_vmadotsu_s32s8u8:\n#endif\n preserve_caller_vec\n vsetvli x7, x0, e8, m8\n vxor.vv v0, v0, v0\n vxor.vv v8, v8, v8\n vxor.vv v16, v16, v16\n vxor.vv v24, v24, v24\n.ime.vmadotsu.s32s8u8.L1:\n vsetvli x7, x0, e8, m1\n vmadotsu v4, v0, v1\n vmadotsu v6, v0, v1\n vmadotsu v8, v0, v1\n vmadotsu v10, v0, v1\n vmadotsu v12, v0, v1\n vmadotsu v14, v0, v1\n vmadotsu v16, v0, v1\n addi a0, a0, -1\n vmadotsu v18, v0, v1\n vmadotsu v20, v0, v1\n vmadotsu v22, v0, v1\n vmadotsu v24, v0, v1\n vmadotsu v26, v0, v1\n vmadotsu v28, v0, v1\n vmadotsu v30, v0, v1\n bnez a0, .ime.vmadotsu.s32s8u8.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _ime_vmadotslide_s32s8s8\n_ime_vmadotslide_s32s8s8:\n#else\n.globl ime_vmadotslide_s32s8s8\nime_vmadotslide_s32s8s8:\n#endif\n preserve_caller_vec\n vsetvli x7, x0, e8, m8\n vxor.vv v0, v0, v0\n vxor.vv v8, v8, v8\n vxor.vv v16, v16, v16\n vxor.vv v24, v24, v24\n.ime.vmadotslide.s32s8s8.L1:\n vsetvli x7, x0, e8, m1\n vmadot v4, v0, v2\n vmadot1 v6, v0, v2\n vmadot2 v8, v0, v2\n vmadot3 v10, v0, v2\n vmadot v12, v0, v2\n vmadot1 v14, v0, v2\n vmadot2 v16, v0, v2\n vmadot3 v18, v0, v2\n addi a0, a0, -1\n vmadot v20, v0, v2\n vmadot1 v22, v0, v2\n vmadot2 v24, v0, v2\n vmadot3 v26, v0, v2\n bnez a0, .ime.vmadotslide.s32s8s8.L1\n restore_caller_vec\n ret\n" }, { "path": "riscv64/asm/_VECTOR_.S", "content": ".align 4\n\n.macro preserve_caller_vec\n csrr x5, vtype\n csrr x6, vl\n vsetvli x7, x0, e8, m8\n sub sp, sp, x7\n vse8.v v0, (sp)\n sub sp, sp, x7\n vse8.v v8, (sp)\n sub sp, sp, x7\n vse8.v v16, (sp)\n sub sp, sp, x7\n vse8.v v24, (sp)\n.endm\n\n.macro restore_caller_vec\n vsetvli x7, x0, e8, m8\n vle8.v v24, (sp)\n add sp, sp, x7\n vle8.v v16, (sp)\n add sp, sp, x7\n vle8.v v8, (sp)\n add sp, sp, x7\n vle8.v v0, (sp)\n add sp, sp, x7\n vsetvl x7, x6, x5\n.endm\n\n#ifdef __APPLE__\n.globl _vector_vfmacc_vf_f16f16f16\n_vector_vfmacc_vf_f16f16f16:\n#else\n.globl vector_vfmacc_vf_f16f16f16\nvector_vfmacc_vf_f16f16f16:\n#endif\n preserve_caller_vec\n vsetvli x7, x0, e8, m8\n vxor.vv v0, v0, v0\n vxor.vv v8, v8, v8\n vxor.vv v16, v16, v16\n vxor.vv v24, v24, v24\n.vector.vfmacc.vf.f16f16f16.L1:\n vsetvli x7, x0, e16, m1\n vfmacc.vf v9, f0, v1\n vfmacc.vf v10, f0, v1\n vfmacc.vf v11, f0, v1\n vfmacc.vf v12, f0, v1\n vfmacc.vf v13, f0, v1\n vfmacc.vf v14, f0, v1\n vfmacc.vf v15, f0, v1\n vfmacc.vf v16, f0, v1\n vfmacc.vf v17, f0, v1\n vfmacc.vf v18, f0, v1\n vfmacc.vf v19, f0, v1\n addi a0, a0, -1\n vfmacc.vf v20, f0, v1\n vfmacc.vf v21, f0, v1\n vfmacc.vf v22, f0, v1\n vfmacc.vf v23, f0, v1\n vfmacc.vf v24, f0, v1\n vfmacc.vf v25, f0, v1\n vfmacc.vf v26, f0, v1\n vfmacc.vf v27, f0, v1\n vfmacc.vf v28, f0, v1\n vfmacc.vf v29, f0, v1\n vfmacc.vf v30, f0, v1\n vfmacc.vf v31, f0, v1\n bnez a0, .vector.vfmacc.vf.f16f16f16.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _vector_vfmacc_vv_f16f16f16\n_vector_vfmacc_vv_f16f16f16:\n#else\n.globl vector_vfmacc_vv_f16f16f16\nvector_vfmacc_vv_f16f16f16:\n#endif\n preserve_caller_vec\n vsetvli x7, x0, e8, m8\n vxor.vv v0, v0, v0\n vxor.vv v8, v8, v8\n vxor.vv v16, v16, v16\n vxor.vv v24, v24, v24\n.vector.vfmacc.vv.f16f16f16.L1:\n vsetvli x7, x0, e16, m1\n vfmacc.vv v8, v0, v1\n vfmacc.vv v9, v0, v1\n vfmacc.vv v10, v0, v1\n vfmacc.vv v11, v0, v1\n vfmacc.vv v12, v0, v1\n vfmacc.vv v13, v0, v1\n vfmacc.vv v14, v0, v1\n vfmacc.vv v15, v0, v1\n vfmacc.vv v16, v0, v1\n vfmacc.vv v17, v0, v1\n vfmacc.vv v18, v0, v1\n vfmacc.vv v19, v0, v1\n addi a0, a0, -1\n vfmacc.vv v20, v0, v1\n vfmacc.vv v21, v0, v1\n vfmacc.vv v22, v0, v1\n vfmacc.vv v23, v0, v1\n vfmacc.vv v24, v0, v1\n vfmacc.vv v25, v0, v1\n vfmacc.vv v26, v0, v1\n vfmacc.vv v27, v0, v1\n vfmacc.vv v28, v0, v1\n vfmacc.vv v29, v0, v1\n vfmacc.vv v30, v0, v1\n vfmacc.vv v31, v0, v1\n bnez a0, .vector.vfmacc.vv.f16f16f16.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _vector_vfmacc_vf_f32f32f32\n_vector_vfmacc_vf_f32f32f32:\n#else\n.globl vector_vfmacc_vf_f32f32f32\nvector_vfmacc_vf_f32f32f32:\n#endif\n preserve_caller_vec\n vsetvli x7, x0, e8, m8\n vxor.vv v0, v0, v0\n vxor.vv v8, v8, v8\n vxor.vv v16, v16, v16\n vxor.vv v24, v24, v24\n.vector.vfmacc.vf.f32f32f32.L1:\n vsetvli x7, x0, e32, m1\n vfmacc.vf v9, f0, v1\n vfmacc.vf v10, f0, v1\n vfmacc.vf v11, f0, v1\n vfmacc.vf v12, f0, v1\n vfmacc.vf v13, f0, v1\n vfmacc.vf v14, f0, v1\n vfmacc.vf v15, f0, v1\n vfmacc.vf v16, f0, v1\n vfmacc.vf v17, f0, v1\n vfmacc.vf v18, f0, v1\n vfmacc.vf v19, f0, v1\n addi a0, a0, -1\n vfmacc.vf v20, f0, v1\n vfmacc.vf v21, f0, v1\n vfmacc.vf v22, f0, v1\n vfmacc.vf v23, f0, v1\n vfmacc.vf v24, f0, v1\n vfmacc.vf v25, f0, v1\n vfmacc.vf v26, f0, v1\n vfmacc.vf v27, f0, v1\n vfmacc.vf v28, f0, v1\n vfmacc.vf v29, f0, v1\n vfmacc.vf v30, f0, v1\n vfmacc.vf v31, f0, v1\n bnez a0, .vector.vfmacc.vf.f32f32f32.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _vector_vfmacc_vv_f32f32f32\n_vector_vfmacc_vv_f32f32f32:\n#else\n.globl vector_vfmacc_vv_f32f32f32\nvector_vfmacc_vv_f32f32f32:\n#endif\n preserve_caller_vec\n vsetvli x7, x0, e8, m8\n vxor.vv v0, v0, v0\n vxor.vv v8, v8, v8\n vxor.vv v16, v16, v16\n vxor.vv v24, v24, v24\n.vector.vfmacc.vv.f32f32f32.L1:\n vsetvli x7, x0, e32, m1\n vfmacc.vv v8, v0, v1\n vfmacc.vv v9, v0, v1\n vfmacc.vv v10, v0, v1\n vfmacc.vv v11, v0, v1\n vfmacc.vv v12, v0, v1\n vfmacc.vv v13, v0, v1\n vfmacc.vv v14, v0, v1\n vfmacc.vv v15, v0, v1\n vfmacc.vv v16, v0, v1\n vfmacc.vv v17, v0, v1\n vfmacc.vv v18, v0, v1\n vfmacc.vv v19, v0, v1\n addi a0, a0, -1\n vfmacc.vv v20, v0, v1\n vfmacc.vv v21, v0, v1\n vfmacc.vv v22, v0, v1\n vfmacc.vv v23, v0, v1\n vfmacc.vv v24, v0, v1\n vfmacc.vv v25, v0, v1\n vfmacc.vv v26, v0, v1\n vfmacc.vv v27, v0, v1\n vfmacc.vv v28, v0, v1\n vfmacc.vv v29, v0, v1\n vfmacc.vv v30, v0, v1\n vfmacc.vv v31, v0, v1\n bnez a0, .vector.vfmacc.vv.f32f32f32.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _vector_vfmacc_vf_f64f64f64\n_vector_vfmacc_vf_f64f64f64:\n#else\n.globl vector_vfmacc_vf_f64f64f64\nvector_vfmacc_vf_f64f64f64:\n#endif\n preserve_caller_vec\n vsetvli x7, x0, e8, m8\n vxor.vv v0, v0, v0\n vxor.vv v8, v8, v8\n vxor.vv v16, v16, v16\n vxor.vv v24, v24, v24\n.vector.vfmacc.vf.f64f64f64.L1:\n vsetvli x7, x0, e64, m1\n vfmacc.vf v9, f0, v1\n vfmacc.vf v10, f0, v1\n vfmacc.vf v11, f0, v1\n vfmacc.vf v12, f0, v1\n vfmacc.vf v13, f0, v1\n vfmacc.vf v14, f0, v1\n vfmacc.vf v15, f0, v1\n vfmacc.vf v16, f0, v1\n vfmacc.vf v17, f0, v1\n vfmacc.vf v18, f0, v1\n vfmacc.vf v19, f0, v1\n addi a0, a0, -1\n vfmacc.vf v20, f0, v1\n vfmacc.vf v21, f0, v1\n vfmacc.vf v22, f0, v1\n vfmacc.vf v23, f0, v1\n vfmacc.vf v24, f0, v1\n vfmacc.vf v25, f0, v1\n vfmacc.vf v26, f0, v1\n vfmacc.vf v27, f0, v1\n vfmacc.vf v28, f0, v1\n vfmacc.vf v29, f0, v1\n vfmacc.vf v30, f0, v1\n vfmacc.vf v31, f0, v1\n bnez a0, .vector.vfmacc.vf.f64f64f64.L1\n restore_caller_vec\n ret\n\n#ifdef __APPLE__\n.globl _vector_vfmacc_vv_f64f64f64\n_vector_vfmacc_vv_f64f64f64:\n#else\n.globl vector_vfmacc_vv_f64f64f64\nvector_vfmacc_vv_f64f64f64:\n#endif\n preserve_caller_vec\n vsetvli x7, x0, e8, m8\n vxor.vv v0, v0, v0\n vxor.vv v8, v8, v8\n vxor.vv v16, v16, v16\n vxor.vv v24, v24, v24\n.vector.vfmacc.vv.f64f64f64.L1:\n vsetvli x7, x0, e64, m1\n vfmacc.vv v8, v0, v1\n vfmacc.vv v9, v0, v1\n vfmacc.vv v10, v0, v1\n vfmacc.vv v11, v0, v1\n vfmacc.vv v12, v0, v1\n vfmacc.vv v13, v0, v1\n vfmacc.vv v14, v0, v1\n vfmacc.vv v15, v0, v1\n vfmacc.vv v16, v0, v1\n vfmacc.vv v17, v0, v1\n vfmacc.vv v18, v0, v1\n vfmacc.vv v19, v0, v1\n addi a0, a0, -1\n vfmacc.vv v20, v0, v1\n vfmacc.vv v21, v0, v1\n vfmacc.vv v22, v0, v1\n vfmacc.vv v23, v0, v1\n vfmacc.vv v24, v0, v1\n vfmacc.vv v25, v0, v1\n vfmacc.vv v26, v0, v1\n vfmacc.vv v27, v0, v1\n vfmacc.vv v28, v0, v1\n vfmacc.vv v29, v0, v1\n vfmacc.vv v30, v0, v1\n vfmacc.vv v31, v0, v1\n bnez a0, .vector.vfmacc.vv.f64f64f64.L1\n restore_caller_vec\n ret\n" }, { "path": "riscv64/cpufp.cpp", "content": "#include \"table.hpp\"\n#include \"smtl.hpp\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\nusing namespace std;\n\nextern \"C\"\n{\n#ifdef _IME_\n void ime_vmadot_s32s8s8(int64_t);\n void ime_vmadotu_u32u8u8(int64_t);\n void ime_vmadotus_s32u8s8(int64_t);\n void ime_vmadotsu_s32s8u8(int64_t);\n void ime_vmadotslide_s32s8s8(int64_t);\n#endif\n\n#ifdef _VECTOR_\n void vector_vfmacc_vf_f16f16f16(int64_t);\n void vector_vfmacc_vv_f16f16f16(int64_t);\n void vector_vfmacc_vf_f32f32f32(int64_t);\n void vector_vfmacc_vv_f32f32f32(int64_t);\n void vector_vfmacc_vf_f64f64f64(int64_t);\n void vector_vfmacc_vv_f64f64f64(int64_t);\n#endif\n}\n\ntypedef struct\n{\n std::string isa;\n std::string type;\n std::string dim;\n int64_t loop_time;\n int64_t comp_pl;\n void (*bench)(int64_t);\n} cpubm_t;\nstatic vector bm_list;\n\nstatic double get_time(struct timespec *start,\n struct timespec *end)\n{\n return end->tv_sec - start->tv_sec +\n (end->tv_nsec - start->tv_nsec) * 1e-9;\n}\n\nstatic void reg_new_isa(std::string isa,\n std::string type,\n std::string dim,\n int64_t loop_time,\n int64_t comp_pl,\n void (*bench)(int64_t))\n{\n cpubm_t new_one;\n new_one.isa = isa;\n new_one.type = type;\n new_one.dim = dim;\n new_one.loop_time = loop_time;\n new_one.comp_pl = comp_pl;\n new_one.bench = bench;\n\n bm_list.push_back(new_one);\n}\n\nstatic void thread_func(void *params)\n{\n cpubm_t *bm = (cpubm_t*)params;\n bm->bench(bm->loop_time);\n}\n\nstatic void cpubm_riscv64_one(smtl_handle sh,\n cpubm_t &item,\n Table &table)\n{\n struct timespec start, end;\n double time_used, perf;\n char perfUnit = 'G';\n\n int i;\n int num_threads = smtl_num_threads(sh);\n\n // warm up\n for (i = 0; i < num_threads; i++)\n {\n smtl_add_task(sh, thread_func, (void*)&item);\n }\n smtl_begin_tasks(sh);\n smtl_wait_tasks_finished(sh);\n\n clock_gettime(CLOCK_MONOTONIC_RAW, &start);\n for (i = 0; i < num_threads; i++)\n {\n smtl_add_task(sh, thread_func, (void*)&item);\n }\n smtl_begin_tasks(sh);\n smtl_wait_tasks_finished(sh);\n clock_gettime(CLOCK_MONOTONIC_RAW, &end);\n\n time_used = get_time(&start, &end);\n perf = item.loop_time * item.comp_pl * num_threads /\n time_used;\n if (perf > 1e12)\n {\n perfUnit = 'T';\n perf /= 1e12;\n }\n else\n {\n perf /= 1e9;\n }\n\n stringstream ss;\n ss << std::setprecision(5) << perf << \" \" << perfUnit << item.dim;\n\n vector cont;\n cont.resize(3);\n cont[0] = item.isa;\n cont[1] = item.type;\n cont[2] = ss.str();\n table.addOneItem(cont);\n}\n\nstatic void cpubm_do_bench(std::vector &set_of_threads,\n uint32_t idle_time)\n{\n int i;\n\n if (bm_list.size() > 0)\n {\n int num_threads = set_of_threads.size();\n\n printf(\"Number Threads: %d\\n\", num_threads);\n printf(\"Thread Pool Binding:\");\n for (i = 0; i < num_threads; i++)\n {\n printf(\" %d\", set_of_threads[i]);\n }\n printf(\"\\n\");\n\n // set table head\n vector ti;\n ti.resize(3);\n ti[0] = \"Instruction Set\";\n ti[1] = \"Core Computation\";\n ti[2] = \"Peak Performance\";\n\n Table table;\n table.setColumnNum(3);\n table.addOneItem(ti);\n\n // set thread pool\n smtl_handle sh;\n smtl_init(&sh, set_of_threads);\n\n // traverse task list\n cpubm_riscv64_one(sh, bm_list[0], table);\n for (i = 1; i < bm_list.size(); i++)\n {\n sleep(idle_time);\n cpubm_riscv64_one(sh, bm_list[i], table);\n }\n\n table.print();\n\n smtl_fini(sh);\n }\n else\n {\n printf(\"Sorry, there's no any supported SIMD isa.\\n\");\n }\n}\n\nstatic void parse_thread_pool(char *sets,\n vector &set_of_threads)\n{\n if (sets[0] != '[')\n {\n return;\n }\n int pos = 1;\n int left = 0, right = 0;\n int state = 0;\n while (sets[pos] != ']' && sets[pos] != '\\0')\n {\n if (state == 0)\n {\n if (sets[pos] >= '0' && sets[pos] <= '9')\n {\n left *= 10;\n left += (int)(sets[pos] - '0');\n }\n else if (sets[pos] == ',')\n {\n set_of_threads.push_back(left);\n left = 0;\n }\n else if (sets[pos] == '-')\n {\n right = 0;\n state = 1;\n }\n }\n else if (state == 1)\n {\n if (sets[pos] >= '0' && sets[pos] <= '9')\n {\n right *= 10;\n right += (int)(sets[pos] - '0');\n }\n else if (sets[pos] == ',')\n {\n int i;\n for (i = left; i <= right; i++)\n {\n set_of_threads.push_back(i);\n }\n left = 0;\n state = 0;\n }\n }\n pos++;\n }\n if (sets[pos] != ']')\n {\n return;\n }\n if (state == 0)\n {\n set_of_threads.push_back(left);\n }\n else if (state == 1)\n {\n int i;\n for (i = left; i <= right; i++)\n {\n set_of_threads.push_back(i);\n }\n }\n}\n\nstatic void cpufp_register_isa()\n{\n#ifdef _IME_\n reg_new_isa(\"ime\", \"vmadot(s32,s8,s8)\", \"OPS\",\n 0x10000000LL, 3584LL, ime_vmadot_s32s8s8);\n reg_new_isa(\"ime\", \"vmadotu(u32,u8,u8)\", \"OPS\",\n 0x10000000LL, 3584LL, ime_vmadotu_u32u8u8);\n reg_new_isa(\"ime\", \"vmadotus(s32,u8,s8)\", \"OPS\",\n 0x10000000LL, 3584LL, ime_vmadotus_s32u8s8);\n reg_new_isa(\"ime\", \"vmadotsu(s32,s8,u8)\", \"OPS\",\n 0x10000000LL, 3584LL, ime_vmadotsu_s32s8u8);\n reg_new_isa(\"ime\", \"vmadotslide(s32,s8,s8)\", \"OPS\",\n 0x10000000LL, 3072LL, ime_vmadotslide_s32s8s8);\n#endif\n\n#ifdef _VECTOR_\n size_t avl = 0;\n __asm__ volatile(\"vsetvli %[avl], x0, e16, m1\\n\\t\"\n : [avl] \"=r\" (avl)\n :\n : \"cc\");\n reg_new_isa(\"vector\", \"vfmacc.vf(f16,f16,f16)\", \"FLOPS\",\n 0x10000000LL, 48LL * avl, vector_vfmacc_vf_f16f16f16);\n reg_new_isa(\"vector\", \"vfmacc.vv(f16,f16,f16)\", \"FLOPS\",\n 0x10000000LL, 48LL * avl, vector_vfmacc_vv_f16f16f16);\n\n __asm__ volatile(\"vsetvli %[avl], x0, e32, m1\\n\\t\"\n : [avl] \"=r\" (avl)\n :\n : \"cc\");\n reg_new_isa(\"vector\", \"vfmacc.vf(f32,f32,f32)\", \"FLOPS\",\n 0x10000000LL, 48LL * avl, vector_vfmacc_vf_f32f32f32);\n reg_new_isa(\"vector\", \"vfmacc.vv(f32,f32,f32)\", \"FLOPS\",\n 0x10000000LL, 48LL * avl, vector_vfmacc_vv_f32f32f32);\n\n __asm__ volatile(\"vsetvli %[avl], x0, e64, m1\\n\\t\"\n : [avl] \"=r\" (avl)\n :\n : \"cc\");\n reg_new_isa(\"vector\", \"vfmacc.vf(f64,f64,f64)\", \"FLOPS\",\n 0x10000000LL, 48LL * avl, vector_vfmacc_vf_f64f64f64);\n reg_new_isa(\"vector\", \"vfmacc.vv(f64,f64,f64)\", \"FLOPS\",\n 0x10000000LL, 48LL * avl, vector_vfmacc_vv_f64f64f64);\n#endif\n}\n\nint main(int argc, char *argv[])\n{\n vector set_of_threads;\n uint32_t idle_time = 0;\n\n bool params_enough = false;\n\n int i;\n for (i = 1; i < argc; i++)\n {\n if (strncmp(argv[i], \"--thread_pool=\", 14) == 0)\n {\n parse_thread_pool(argv[i] + 14, set_of_threads);\n params_enough = true;\n }\n else if (strncmp(argv[i], \"--idle_time=\", 12) == 0)\n {\n idle_time = (uint32_t)atoi(argv[i] + 12);\n }\n }\n if (!params_enough)\n {\n fprintf(stderr, \"Error: You must set --thread_pool parameter.\\n\");\n fprintf(stderr, \"You may also set --idle_time parameter.\\n\");\n fprintf(stderr, \"Usage: %s --thread_pool=[xxx] --idle_time=yyy\\n\", argv[0]);\n fprintf(stderr, \"[xxx] indicates all cores to benchmark.\\n\");\n fprintf(stderr, \"Example: [0,3,5-8,13-15].\\n\");\n fprintf(stderr, \"idle_time is the interval time(s) between every two benchmarks.\\n\");\n fprintf(stderr, \"idle_time parameter can be ignored, the default value is 0s.\\n\");\n fprintf(stderr, \"Notice: there must NOT be any spaces.\\n\");\n exit(0);\n }\n\n cpufp_register_isa();\n cpubm_do_bench(set_of_threads, idle_time);\n\n return 0;\n}\n\n" }, { "path": "riscv64/cpuid.c", "content": "\n#include \n#include \n#include \n#include \n#include \n#include \n\n#define ISA_V_HWCAP (1 << ('v' - 'a'))\n\nint main()\n{\n FILE *cpuinfo_file;\n char line[1024];\n char *token;\n const char *delimiter = \":\";\n const char *search_key = \"vendorid\";\n char *vendor_id = NULL;\n\n cpuinfo_file = fopen(\"/proc/cpuinfo\", \"r\");\n if (cpuinfo_file == NULL) {\n printf(\"Failed to open /proc/cpuinfo\\n\");\n return 1;\n }\n\n while (fgets(line, sizeof(line), cpuinfo_file)) {\n if ((token = strtok(line, delimiter)) != NULL) {\n if (strstr(token, search_key) != NULL) {\n token = strtok(NULL, delimiter);\n vendor_id = token + strspn(token, \" \\t\");\n break;\n }\n }\n }\n\n fclose(cpuinfo_file);\n\n if (vendor_id) {\n if (strncmp(vendor_id, \"0x710\", 5) == 0) {\n printf(\"_IME_\\n\");\n }\n }\n\n uint64_t hwcaps = getauxval(AT_HWCAP);\n\n#ifdef ISA_V_HWCAP\n if (hwcaps & ISA_V_HWCAP)\n {\n printf(\"_VECTOR_\\n\");\n }\n#endif\n\n return 0;\n}" }, { "path": "x64/asm/_AMX_BF16_.S", "content": ".globl amx_bf16_mm_f32bf16bf16\n\namx_bf16_mm_f32bf16bf16:\n ldtilecfg (%rsi)\n tilezero %tmm0\n tilezero %tmm1\n tilezero %tmm2\n tilezero %tmm3\n tilezero %tmm4\n tilezero %tmm5\n.amx.bf16.mm.f32bf16bf16:\n tdpbf16ps %tmm4, %tmm5, %tmm0\n tdpbf16ps %tmm4, %tmm5, %tmm1\n tdpbf16ps %tmm4, %tmm5, %tmm2\n tdpbf16ps %tmm4, %tmm5, %tmm3\n sub $0x1, %rdi\n jne .amx.bf16.mm.f32bf16bf16\n ret\n\n" }, { "path": "x64/asm/_AMX_FP16_.S", "content": ".globl amx_fp16_mm_f32f16f16\n\namx_fp16_mm_f32f16f16:\n ldtilecfg (%rsi)\n tilezero %tmm0\n tilezero %tmm1\n tilezero %tmm2\n tilezero %tmm3\n tilezero %tmm4\n tilezero %tmm5\n.amx.fp16.mm.f32f16f16:\n tdpfp16ps %tmm4, %tmm5, %tmm0\n tdpfp16ps %tmm4, %tmm5, %tmm1\n tdpfp16ps %tmm4, %tmm5, %tmm2\n tdpfp16ps %tmm4, %tmm5, %tmm3\n sub $0x1, %rdi\n jne .amx.fp16.mm.f32f16f16\n ret\n" }, { "path": "x64/asm/_AMX_INT8_.S", "content": ".globl amx_int8_mm_s32s8s8\n.globl amx_int8_mm_s32s8u8\n.globl amx_int8_mm_s32u8s8\n.globl amx_int8_mm_s32u8u8\n\namx_int8_mm_s32s8s8:\n ldtilecfg (%rsi)\n tilezero %tmm0\n tilezero %tmm1\n tilezero %tmm2\n tilezero %tmm3\n tilezero %tmm4\n tilezero %tmm5\n.amx.int8.mm.s32s8s8:\n tdpbssd %tmm4, %tmm5, %tmm0\n tdpbssd %tmm4, %tmm5, %tmm1\n tdpbssd %tmm4, %tmm5, %tmm2\n tdpbssd %tmm4, %tmm5, %tmm3\n sub $0x1, %rdi\n jne .amx.int8.mm.s32s8s8\n ret\n\namx_int8_mm_s32s8u8:\n ldtilecfg (%rsi)\n tilezero %tmm0\n tilezero %tmm1\n tilezero %tmm2\n tilezero %tmm3\n tilezero %tmm4\n tilezero %tmm5\n.amx.int8.mm.s32s8u8:\n tdpbsud %tmm4, %tmm5, %tmm0\n tdpbsud %tmm4, %tmm5, %tmm1\n tdpbsud %tmm4, %tmm5, %tmm2\n tdpbsud %tmm4, %tmm5, %tmm3\n sub $0x1, %rdi\n jne .amx.int8.mm.s32s8u8\n ret\n\namx_int8_mm_s32u8s8:\n ldtilecfg (%rsi)\n tilezero %tmm0\n tilezero %tmm1\n tilezero %tmm2\n tilezero %tmm3\n tilezero %tmm4\n tilezero %tmm5\n.amx.int8.mm.s32u8s8:\n tdpbusd %tmm4, %tmm5, %tmm0\n tdpbusd %tmm4, %tmm5, %tmm1\n tdpbusd %tmm4, %tmm5, %tmm2\n tdpbusd %tmm4, %tmm5, %tmm3\n sub $0x1, %rdi\n jne .amx.int8.mm.s32u8s8\n ret\n\namx_int8_mm_s32u8u8:\n ldtilecfg (%rsi)\n tilezero %tmm0\n tilezero %tmm1\n tilezero %tmm2\n tilezero %tmm3\n tilezero %tmm4\n tilezero %tmm5\n.amx.int8.mm.s32u8u8:\n tdpbuud %tmm4, %tmm5, %tmm0\n tdpbuud %tmm4, %tmm5, %tmm1\n tdpbuud %tmm4, %tmm5, %tmm2\n tdpbuud %tmm4, %tmm5, %tmm3\n sub $0x1, %rdi\n jne .amx.int8.mm.s32u8u8\n ret\n\n" }, { "path": "x64/asm/_AVX512F_.S", "content": ".globl avx512f_512b_fma_f32f32f32\n.globl avx512f_512b_fma_f64f64f64\n.globl avx512f_512b_add_mul_f32f32_f32\n.globl avx512f_512b_add_mul_f64f64_f64\n\navx512f_512b_fma_f32f32f32:\n vpxord %zmm0, %zmm0, %zmm0\n vpxord %zmm1, %zmm1, %zmm1\n vpxord %zmm2, %zmm2, %zmm2\n vpxord %zmm3, %zmm3, %zmm3\n vpxord %zmm4, %zmm4, %zmm4\n vpxord %zmm5, %zmm5, %zmm5\n vpxord %zmm6, %zmm6, %zmm6\n vpxord %zmm7, %zmm7, %zmm7\n vpxord %zmm8, %zmm8, %zmm8\n vpxord %zmm9, %zmm9, %zmm9\n vpxord %zmm10, %zmm10, %zmm10\n vpxord %zmm11, %zmm11, %zmm11\n vpxord %zmm12, %zmm12, %zmm12\n vpxord %zmm13, %zmm13, %zmm13\n vpxord %zmm14, %zmm14, %zmm14\n vpxord %zmm15, %zmm15, %zmm15\n.avx512f.512b.fma.f32f32f32.L1:\n vfmadd231ps %zmm0, %zmm0, %zmm0\n vfmadd231ps %zmm1, %zmm1, %zmm1\n vfmadd231ps %zmm2, %zmm2, %zmm2\n vfmadd231ps %zmm3, %zmm3, %zmm3\n vfmadd231ps %zmm4, %zmm4, %zmm4\n vfmadd231ps %zmm5, %zmm5, %zmm5\n vfmadd231ps %zmm6, %zmm6, %zmm6\n vfmadd231ps %zmm7, %zmm7, %zmm7\n vfmadd231ps %zmm8, %zmm8, %zmm8\n vfmadd231ps %zmm9, %zmm9, %zmm9\n vfmadd231ps %zmm10, %zmm10, %zmm10\n vfmadd231ps %zmm11, %zmm11, %zmm11\n vfmadd231ps %zmm12, %zmm12, %zmm12\n vfmadd231ps %zmm13, %zmm13, %zmm13\n vfmadd231ps %zmm14, %zmm14, %zmm14\n vfmadd231ps %zmm15, %zmm15, %zmm15\n sub $0x1, %rdi\n jne .avx512f.512b.fma.f32f32f32.L1\n ret\n\navx512f_512b_fma_f64f64f64:\n vpxord %zmm0, %zmm0, %zmm0\n vpxord %zmm1, %zmm1, %zmm1\n vpxord %zmm2, %zmm2, %zmm2\n vpxord %zmm3, %zmm3, %zmm3\n vpxord %zmm4, %zmm4, %zmm4\n vpxord %zmm5, %zmm5, %zmm5\n vpxord %zmm6, %zmm6, %zmm6\n vpxord %zmm7, %zmm7, %zmm7\n vpxord %zmm8, %zmm8, %zmm8\n vpxord %zmm9, %zmm9, %zmm9\n vpxord %zmm10, %zmm10, %zmm10\n vpxord %zmm11, %zmm11, %zmm11\n vpxord %zmm12, %zmm12, %zmm12\n vpxord %zmm13, %zmm13, %zmm13\n vpxord %zmm14, %zmm14, %zmm14\n vpxord %zmm15, %zmm15, %zmm15\n.avx512f.512b.fma.f64f64f64.L1:\n vfmadd231pd %zmm0, %zmm0, %zmm0\n vfmadd231pd %zmm1, %zmm1, %zmm1\n vfmadd231pd %zmm2, %zmm2, %zmm2\n vfmadd231pd %zmm3, %zmm3, %zmm3\n vfmadd231pd %zmm4, %zmm4, %zmm4\n vfmadd231pd %zmm5, %zmm5, %zmm5\n vfmadd231pd %zmm6, %zmm6, %zmm6\n vfmadd231pd %zmm7, %zmm7, %zmm7\n vfmadd231pd %zmm8, %zmm8, %zmm8\n vfmadd231pd %zmm9, %zmm9, %zmm9\n vfmadd231pd %zmm10, %zmm10, %zmm10\n vfmadd231pd %zmm11, %zmm11, %zmm11\n vfmadd231pd %zmm12, %zmm12, %zmm12\n vfmadd231pd %zmm13, %zmm13, %zmm13\n vfmadd231pd %zmm14, %zmm14, %zmm14\n vfmadd231pd %zmm15, %zmm15, %zmm15\n sub $0x1, %rdi\n jne .avx512f.512b.fma.f64f64f64.L1\n ret\n\navx512f_512b_add_mul_f32f32_f32:\n vpxord %zmm0, %zmm0, %zmm0\n vpxord %zmm1, %zmm1, %zmm1\n vpxord %zmm2, %zmm2, %zmm2\n vpxord %zmm3, %zmm3, %zmm3\n vpxord %zmm4, %zmm4, %zmm4\n vpxord %zmm5, %zmm5, %zmm5\n vpxord %zmm6, %zmm6, %zmm6\n vpxord %zmm7, %zmm7, %zmm7\n vpxord %zmm8, %zmm8, %zmm8\n vpxord %zmm9, %zmm9, %zmm9\n vpxord %zmm10, %zmm10, %zmm10\n vpxord %zmm11, %zmm11, %zmm11\n vpxord %zmm12, %zmm12, %zmm12\n vpxord %zmm13, %zmm13, %zmm13\n vpxord %zmm14, %zmm14, %zmm14\n vpxord %zmm15, %zmm15, %zmm15\n.avx512f.512b.add.mul.f32f32.f32.L1:\n vmulps %zmm0, %zmm0, %zmm0\n vaddps %zmm1, %zmm1, %zmm1\n vmulps %zmm2, %zmm2, %zmm2\n vaddps %zmm3, %zmm3, %zmm3\n vmulps %zmm4, %zmm4, %zmm4\n vaddps %zmm5, %zmm5, %zmm5\n vmulps %zmm6, %zmm6, %zmm6\n vaddps %zmm7, %zmm7, %zmm7\n vmulps %zmm8, %zmm8, %zmm8\n vaddps %zmm9, %zmm9, %zmm9\n vmulps %zmm10, %zmm10, %zmm10\n vaddps %zmm11, %zmm11, %zmm11\n vmulps %zmm12, %zmm12, %zmm12\n vaddps %zmm13, %zmm13, %zmm13\n vmulps %zmm14, %zmm14, %zmm14\n vaddps %zmm15, %zmm15, %zmm15\n sub $0x1, %rdi\n jne .avx512f.512b.add.mul.f32f32.f32.L1\n ret\n\navx512f_512b_add_mul_f64f64_f64:\n vpxord %zmm0, %zmm0, %zmm0\n vpxord %zmm1, %zmm1, %zmm1\n vpxord %zmm2, %zmm2, %zmm2\n vpxord %zmm3, %zmm3, %zmm3\n vpxord %zmm4, %zmm4, %zmm4\n vpxord %zmm5, %zmm5, %zmm5\n vpxord %zmm6, %zmm6, %zmm6\n vpxord %zmm7, %zmm7, %zmm7\n vpxord %zmm8, %zmm8, %zmm8\n vpxord %zmm9, %zmm9, %zmm9\n vpxord %zmm10, %zmm10, %zmm10\n vpxord %zmm11, %zmm11, %zmm11\n vpxord %zmm12, %zmm12, %zmm12\n vpxord %zmm13, %zmm13, %zmm13\n vpxord %zmm14, %zmm14, %zmm14\n vpxord %zmm15, %zmm15, %zmm15\n.avx512f.512b.add.mul.f64f64.f64.L1:\n vmulpd %zmm0, %zmm0, %zmm0\n vaddpd %zmm1, %zmm1, %zmm1\n vmulpd %zmm2, %zmm2, %zmm2\n vaddpd %zmm3, %zmm3, %zmm3\n vmulpd %zmm4, %zmm4, %zmm4\n vaddpd %zmm5, %zmm5, %zmm5\n vmulpd %zmm6, %zmm6, %zmm6\n vaddpd %zmm7, %zmm7, %zmm7\n vmulpd %zmm8, %zmm8, %zmm8\n vaddpd %zmm9, %zmm9, %zmm9\n vmulpd %zmm10, %zmm10, %zmm10\n vaddpd %zmm11, %zmm11, %zmm11\n vmulpd %zmm12, %zmm12, %zmm12\n vaddpd %zmm13, %zmm13, %zmm13\n vmulpd %zmm14, %zmm14, %zmm14\n vaddpd %zmm15, %zmm15, %zmm15\n sub $0x1, %rdi\n jne .avx512f.512b.add.mul.f64f64.f64.L1\n ret\n\n" }, { "path": "x64/asm/_AVX512_BF16_.S", "content": ".globl avx512_bf16_512b_dp2a_f32bf16bf16\n.globl avx512_bf16_256b_dp2a_f32bf16bf16\n.globl avx512_bf16_128b_dp2a_f32bf16bf16\n\navx512_bf16_512b_dp2a_f32bf16bf16:\n vpxord %zmm0, %zmm0, %zmm0\n vpxord %zmm1, %zmm1, %zmm1\n vpxord %zmm2, %zmm2, %zmm2\n vpxord %zmm3, %zmm3, %zmm3\n vpxord %zmm4, %zmm4, %zmm4\n vpxord %zmm5, %zmm5, %zmm5\n vpxord %zmm6, %zmm6, %zmm6\n vpxord %zmm7, %zmm7, %zmm7\n vpxord %zmm8, %zmm8, %zmm8\n vpxord %zmm9, %zmm9, %zmm9\n vpxord %zmm10, %zmm10, %zmm10\n vpxord %zmm11, %zmm11, %zmm11\n vpxord %zmm12, %zmm12, %zmm12\n vpxord %zmm13, %zmm13, %zmm13\n vpxord %zmm14, %zmm14, %zmm14\n vpxord %zmm15, %zmm15, %zmm15\n vpxord %zmm16, %zmm16, %zmm16\n.avx512.bf16.512b.dp2a.fp32bf16bf16.L1:\n vdpbf16ps %zmm16, %zmm16, %zmm0\n vdpbf16ps %zmm16, %zmm16, %zmm1\n vdpbf16ps %zmm16, %zmm16, %zmm2\n vdpbf16ps %zmm16, %zmm16, %zmm3\n vdpbf16ps %zmm16, %zmm16, %zmm4\n vdpbf16ps %zmm16, %zmm16, %zmm5\n vdpbf16ps %zmm16, %zmm16, %zmm6\n vdpbf16ps %zmm16, %zmm16, %zmm7\n vdpbf16ps %zmm16, %zmm16, %zmm8\n vdpbf16ps %zmm16, %zmm16, %zmm9\n vdpbf16ps %zmm16, %zmm16, %zmm10\n vdpbf16ps %zmm16, %zmm16, %zmm11\n vdpbf16ps %zmm16, %zmm16, %zmm12\n vdpbf16ps %zmm16, %zmm16, %zmm13\n vdpbf16ps %zmm16, %zmm16, %zmm14\n vdpbf16ps %zmm16, %zmm16, %zmm15\n sub $0x1, %rdi\n jne .avx512.bf16.512b.dp2a.fp32bf16bf16.L1\n ret\n\navx512_bf16_256b_dp2a_f32bf16bf16:\n vpxor %ymm0, %ymm0, %ymm0\n vpxor %ymm1, %ymm1, %ymm1\n vpxor %ymm2, %ymm2, %ymm2\n vpxor %ymm3, %ymm3, %ymm3\n vpxor %ymm4, %ymm4, %ymm4\n vpxor %ymm5, %ymm5, %ymm5\n vpxor %ymm6, %ymm6, %ymm6\n vpxor %ymm7, %ymm7, %ymm7\n vpxor %ymm8, %ymm8, %ymm8\n vpxor %ymm9, %ymm9, %ymm9\n vpxor %ymm10, %ymm10, %ymm10\n vpxor %ymm11, %ymm11, %ymm11\n vpxor %ymm12, %ymm12, %ymm12\n vpxor %ymm13, %ymm13, %ymm13\n vpxor %ymm14, %ymm14, %ymm14\n vpxor %ymm15, %ymm15, %ymm15\n vpxord %zmm16, %zmm16, %zmm16\n.avx512.bf16.256b.dp2a.fp32bf16bf16.L1:\n vdpbf16ps %ymm16, %ymm16, %ymm0\n vdpbf16ps %ymm16, %ymm16, %ymm1\n vdpbf16ps %ymm16, %ymm16, %ymm2\n vdpbf16ps %ymm16, %ymm16, %ymm3\n vdpbf16ps %ymm16, %ymm16, %ymm4\n vdpbf16ps %ymm16, %ymm16, %ymm5\n vdpbf16ps %ymm16, %ymm16, %ymm6\n vdpbf16ps %ymm16, %ymm16, %ymm7\n vdpbf16ps %ymm16, %ymm16, %ymm8\n vdpbf16ps %ymm16, %ymm16, %ymm9\n vdpbf16ps %ymm16, %ymm16, %ymm10\n vdpbf16ps %ymm16, %ymm16, %ymm11\n vdpbf16ps %ymm16, %ymm16, %ymm12\n vdpbf16ps %ymm16, %ymm16, %ymm13\n vdpbf16ps %ymm16, %ymm16, %ymm14\n vdpbf16ps %ymm16, %ymm16, %ymm15\n sub $0x1, %rdi\n jne .avx512.bf16.256b.dp2a.fp32bf16bf16.L1\n ret\n\navx512_bf16_128b_dp2a_f32bf16bf16:\n pxor %xmm0, %xmm0\n pxor %xmm1, %xmm1\n pxor %xmm2, %xmm2\n pxor %xmm3, %xmm3\n pxor %xmm4, %xmm4\n pxor %xmm5, %xmm5\n pxor %xmm6, %xmm6\n pxor %xmm7, %xmm7\n pxor %xmm8, %xmm8\n pxor %xmm9, %xmm9\n pxor %xmm10, %xmm10\n pxor %xmm11, %xmm11\n pxor %xmm12, %xmm12\n pxor %xmm13, %xmm13\n pxor %xmm14, %xmm14\n pxor %xmm15, %xmm15\n vpxord %zmm16, %zmm16, %zmm16\n.avx512.bf16.128b.dp2a.fp32bf16bf16.L1:\n vdpbf16ps %xmm16, %xmm16, %xmm0\n vdpbf16ps %xmm16, %xmm16, %xmm1\n vdpbf16ps %xmm16, %xmm16, %xmm2\n vdpbf16ps %xmm16, %xmm16, %xmm3\n vdpbf16ps %xmm16, %xmm16, %xmm4\n vdpbf16ps %xmm16, %xmm16, %xmm5\n vdpbf16ps %xmm16, %xmm16, %xmm6\n vdpbf16ps %xmm16, %xmm16, %xmm7\n vdpbf16ps %xmm16, %xmm16, %xmm8\n vdpbf16ps %xmm16, %xmm16, %xmm9\n vdpbf16ps %xmm16, %xmm16, %xmm10\n vdpbf16ps %xmm16, %xmm16, %xmm11\n vdpbf16ps %xmm16, %xmm16, %xmm12\n vdpbf16ps %xmm16, %xmm16, %xmm13\n vdpbf16ps %xmm16, %xmm16, %xmm14\n vdpbf16ps %xmm16, %xmm16, %xmm15\n sub $0x1, %rdi\n jne .avx512.bf16.128b.dp2a.fp32bf16bf16.L1\n ret\n\n" }, { "path": "x64/asm/_AVX512_FP16_.S", "content": ".globl avx512_fp16_512b_fma_f16f16f16\n.globl avx512_fp16_256b_fma_f16f16f16\n.globl avx512_fp16_128b_fma_f16f16f16\n\navx512_fp16_512b_fma_f16f16f16:\n vpxord %zmm0, %zmm0, %zmm0\n vpxord %zmm1, %zmm1, %zmm1\n vpxord %zmm2, %zmm2, %zmm2\n vpxord %zmm3, %zmm3, %zmm3\n vpxord %zmm4, %zmm4, %zmm4\n vpxord %zmm5, %zmm5, %zmm5\n vpxord %zmm6, %zmm6, %zmm6\n vpxord %zmm7, %zmm7, %zmm7\n vpxord %zmm8, %zmm8, %zmm8\n vpxord %zmm9, %zmm9, %zmm9\n vpxord %zmm10, %zmm10, %zmm10\n vpxord %zmm11, %zmm11, %zmm11\n vpxord %zmm12, %zmm12, %zmm12\n vpxord %zmm13, %zmm13, %zmm13\n vpxord %zmm14, %zmm14, %zmm14\n vpxord %zmm15, %zmm15, %zmm15\n.avx512.fp16.512b.fma.f16f16f16.L1:\n vfmadd231ph %zmm0, %zmm0, %zmm0\n vfmadd231ph %zmm1, %zmm1, %zmm1\n vfmadd231ph %zmm2, %zmm2, %zmm2\n vfmadd231ph %zmm3, %zmm3, %zmm3\n vfmadd231ph %zmm4, %zmm4, %zmm4\n vfmadd231ph %zmm5, %zmm5, %zmm5\n vfmadd231ph %zmm6, %zmm6, %zmm6\n vfmadd231ph %zmm7, %zmm7, %zmm7\n vfmadd231ph %zmm8, %zmm8, %zmm8\n vfmadd231ph %zmm9, %zmm9, %zmm9\n vfmadd231ph %zmm10, %zmm10, %zmm10\n vfmadd231ph %zmm11, %zmm11, %zmm11\n vfmadd231ph %zmm12, %zmm12, %zmm12\n vfmadd231ph %zmm13, %zmm13, %zmm13\n vfmadd231ph %zmm14, %zmm14, %zmm14\n vfmadd231ph %zmm15, %zmm15, %zmm15\n sub $0x1, %rdi\n jne .avx512.fp16.512b.fma.f16f16f16.L1\n ret\n\navx512_fp16_256b_fma_f16f16f16:\n vpxor %ymm0, %ymm0, %ymm0\n vpxor %ymm1, %ymm1, %ymm1\n vpxor %ymm2, %ymm2, %ymm2\n vpxor %ymm3, %ymm3, %ymm3\n vpxor %ymm4, %ymm4, %ymm4\n vpxor %ymm5, %ymm5, %ymm5\n vpxor %ymm6, %ymm6, %ymm6\n vpxor %ymm7, %ymm7, %ymm7\n vpxor %ymm8, %ymm8, %ymm8\n vpxor %ymm9, %ymm9, %ymm9\n vpxor %ymm10, %ymm10, %ymm10\n vpxor %ymm11, %ymm11, %ymm11\n vpxor %ymm12, %ymm12, %ymm12\n vpxor %ymm13, %ymm13, %ymm13\n vpxor %ymm14, %ymm14, %ymm14\n vpxor %ymm15, %ymm15, %ymm15\n.avx512.fp16.256b.fma.f16f16f16.L1:\n vfmadd231ph %ymm0, %ymm0, %ymm0\n vfmadd231ph %ymm1, %ymm1, %ymm1\n vfmadd231ph %ymm2, %ymm2, %ymm2\n vfmadd231ph %ymm3, %ymm3, %ymm3\n vfmadd231ph %ymm4, %ymm4, %ymm4\n vfmadd231ph %ymm5, %ymm5, %ymm5\n vfmadd231ph %ymm6, %ymm6, %ymm6\n vfmadd231ph %ymm7, %ymm7, %ymm7\n vfmadd231ph %ymm8, %ymm8, %ymm8\n vfmadd231ph %ymm9, %ymm9, %ymm9\n vfmadd231ph %ymm10, %ymm10, %ymm10\n vfmadd231ph %ymm11, %ymm11, %ymm11\n vfmadd231ph %ymm12, %ymm12, %ymm12\n vfmadd231ph %ymm13, %ymm13, %ymm13\n vfmadd231ph %ymm14, %ymm14, %ymm14\n vfmadd231ph %ymm15, %ymm15, %ymm15\n sub $0x1, %rdi\n jne .avx512.fp16.256b.fma.f16f16f16.L1\n ret\n\navx512_fp16_128b_fma_f16f16f16:\n pxor %xmm0, %xmm0\n pxor %xmm1, %xmm1\n pxor %xmm2, %xmm2\n pxor %xmm3, %xmm3\n pxor %xmm4, %xmm4\n pxor %xmm5, %xmm5\n pxor %xmm6, %xmm6\n pxor %xmm7, %xmm7\n pxor %xmm8, %xmm8\n pxor %xmm9, %xmm9\n pxor %xmm10, %xmm10\n pxor %xmm11, %xmm11\n pxor %xmm12, %xmm12\n pxor %xmm13, %xmm13\n pxor %xmm14, %xmm14\n pxor %xmm15, %xmm15\n.avx512.fp16.128b.fma.f16f16f16.L1:\n vfmadd231ph %xmm0, %xmm0, %xmm0\n vfmadd231ph %xmm1, %xmm1, %xmm1\n vfmadd231ph %xmm2, %xmm2, %xmm2\n vfmadd231ph %xmm3, %xmm3, %xmm3\n vfmadd231ph %xmm4, %xmm4, %xmm4\n vfmadd231ph %xmm5, %xmm5, %xmm5\n vfmadd231ph %xmm6, %xmm6, %xmm6\n vfmadd231ph %xmm7, %xmm7, %xmm7\n vfmadd231ph %xmm8, %xmm8, %xmm8\n vfmadd231ph %xmm9, %xmm9, %xmm9\n vfmadd231ph %xmm10, %xmm10, %xmm10\n vfmadd231ph %xmm11, %xmm11, %xmm11\n vfmadd231ph %xmm12, %xmm12, %xmm12\n vfmadd231ph %xmm13, %xmm13, %xmm13\n vfmadd231ph %xmm14, %xmm14, %xmm14\n vfmadd231ph %xmm15, %xmm15, %xmm15\n sub $0x1, %rdi\n jne .avx512.fp16.128b.fma.f16f16f16.L1\n ret\n\n" }, { "path": "x64/asm/_AVX512_VNNI_.S", "content": ".globl avx512_vnni_512b_dp4a_s32u8s8\n.globl avx512_vnni_512b_dp2a_s32s16s16\n.globl avx512_vnni_256b_dp4a_s32u8s8\n.globl avx512_vnni_256b_dp2a_s32s16s16\n.globl avx512_vnni_128b_dp4a_s32u8s8\n.globl avx512_vnni_128b_dp2a_s32s16s16\n\navx512_vnni_512b_dp4a_s32u8s8:\n vpxord %zmm0, %zmm0, %zmm0\n vpxord %zmm1, %zmm1, %zmm1\n vpxord %zmm2, %zmm2, %zmm2\n vpxord %zmm3, %zmm3, %zmm3\n vpxord %zmm4, %zmm4, %zmm4\n vpxord %zmm5, %zmm5, %zmm5\n vpxord %zmm6, %zmm6, %zmm6\n vpxord %zmm7, %zmm7, %zmm7\n vpxord %zmm8, %zmm8, %zmm8\n vpxord %zmm9, %zmm9, %zmm9\n vpxord %zmm10, %zmm10, %zmm10\n vpxord %zmm11, %zmm11, %zmm11\n vpxord %zmm12, %zmm12, %zmm12\n vpxord %zmm13, %zmm13, %zmm13\n vpxord %zmm14, %zmm14, %zmm14\n vpxord %zmm15, %zmm15, %zmm15\n.avx512.vnni.512b.dp4a.s32u8s8.L1:\n vpdpbusd %zmm0, %zmm0, %zmm0\n vpdpbusd %zmm1, %zmm1, %zmm1\n vpdpbusd %zmm2, %zmm2, %zmm2\n vpdpbusd %zmm3, %zmm3, %zmm3\n vpdpbusd %zmm4, %zmm4, %zmm4\n vpdpbusd %zmm5, %zmm5, %zmm5\n vpdpbusd %zmm6, %zmm6, %zmm6\n vpdpbusd %zmm7, %zmm7, %zmm7\n vpdpbusd %zmm8, %zmm8, %zmm8\n vpdpbusd %zmm9, %zmm9, %zmm9\n vpdpbusd %zmm10, %zmm10, %zmm10\n vpdpbusd %zmm11, %zmm11, %zmm11\n vpdpbusd %zmm12, %zmm12, %zmm12\n vpdpbusd %zmm13, %zmm13, %zmm13\n vpdpbusd %zmm14, %zmm14, %zmm14\n vpdpbusd %zmm15, %zmm15, %zmm15\n sub $0x1, %rdi\n jne .avx512.vnni.512b.dp4a.s32u8s8.L1\n ret\n\navx512_vnni_512b_dp2a_s32s16s16:\n vpxord %zmm0, %zmm0, %zmm0\n vpxord %zmm1, %zmm1, %zmm1\n vpxord %zmm2, %zmm2, %zmm2\n vpxord %zmm3, %zmm3, %zmm3\n vpxord %zmm4, %zmm4, %zmm4\n vpxord %zmm5, %zmm5, %zmm5\n vpxord %zmm6, %zmm6, %zmm6\n vpxord %zmm7, %zmm7, %zmm7\n vpxord %zmm8, %zmm8, %zmm8\n vpxord %zmm9, %zmm9, %zmm9\n vpxord %zmm10, %zmm10, %zmm10\n vpxord %zmm11, %zmm11, %zmm11\n vpxord %zmm12, %zmm12, %zmm12\n vpxord %zmm13, %zmm13, %zmm13\n vpxord %zmm14, %zmm14, %zmm14\n vpxord %zmm15, %zmm15, %zmm15\n.avx512.vnni.512b.dp2a.s32s16s16.L1:\n vpdpwssd %zmm0, %zmm0, %zmm0\n vpdpwssd %zmm1, %zmm1, %zmm1\n vpdpwssd %zmm2, %zmm2, %zmm2\n vpdpwssd %zmm3, %zmm3, %zmm3\n vpdpwssd %zmm4, %zmm4, %zmm4\n vpdpwssd %zmm5, %zmm5, %zmm5\n vpdpwssd %zmm6, %zmm6, %zmm6\n vpdpwssd %zmm7, %zmm7, %zmm7\n vpdpwssd %zmm8, %zmm8, %zmm8\n vpdpwssd %zmm9, %zmm9, %zmm9\n vpdpwssd %zmm10, %zmm10, %zmm10\n vpdpwssd %zmm11, %zmm11, %zmm11\n vpdpwssd %zmm12, %zmm12, %zmm12\n vpdpwssd %zmm13, %zmm13, %zmm13\n vpdpwssd %zmm14, %zmm14, %zmm14\n vpdpwssd %zmm15, %zmm15, %zmm15\n sub $0x1, %rdi\n jne .avx512.vnni.512b.dp2a.s32s16s16.L1\n ret\n\navx512_vnni_256b_dp4a_s32u8s8:\n vpxor %ymm0, %ymm0, %ymm0\n vpxor %ymm1, %ymm1, %ymm1\n vpxor %ymm2, %ymm2, %ymm2\n vpxor %ymm3, %ymm3, %ymm3\n vpxor %ymm4, %ymm4, %ymm4\n vpxor %ymm5, %ymm5, %ymm5\n vpxor %ymm6, %ymm6, %ymm6\n vpxor %ymm7, %ymm7, %ymm7\n vpxor %ymm8, %ymm8, %ymm8\n vpxor %ymm9, %ymm9, %ymm9\n vpxor %ymm10, %ymm10, %ymm10\n vpxor %ymm11, %ymm11, %ymm11\n vpxor %ymm12, %ymm12, %ymm12\n vpxor %ymm13, %ymm13, %ymm13\n vpxor %ymm14, %ymm14, %ymm14\n vpxor %ymm15, %ymm15, %ymm15\n.avx512.vnni.256b.dp4a.s32u8s8.L1:\n vpdpbusd %ymm0, %ymm0, %ymm0\n vpdpbusd %ymm1, %ymm1, %ymm1\n vpdpbusd %ymm2, %ymm2, %ymm2\n vpdpbusd %ymm3, %ymm3, %ymm3\n vpdpbusd %ymm4, %ymm4, %ymm4\n vpdpbusd %ymm5, %ymm5, %ymm5\n vpdpbusd %ymm6, %ymm6, %ymm6\n vpdpbusd %ymm7, %ymm7, %ymm7\n vpdpbusd %ymm8, %ymm8, %ymm8\n vpdpbusd %ymm9, %ymm9, %ymm9\n vpdpbusd %ymm10, %ymm10, %ymm10\n vpdpbusd %ymm11, %ymm11, %ymm11\n vpdpbusd %ymm12, %ymm12, %ymm12\n vpdpbusd %ymm13, %ymm13, %ymm13\n vpdpbusd %ymm14, %ymm14, %ymm14\n vpdpbusd %ymm15, %ymm15, %ymm15\n sub $0x1, %rdi\n jne .avx512.vnni.256b.dp4a.s32u8s8.L1\n ret\n\navx512_vnni_256b_dp2a_s32s16s16:\n vpxor %ymm0, %ymm0, %ymm0\n vpxor %ymm1, %ymm1, %ymm1\n vpxor %ymm2, %ymm2, %ymm2\n vpxor %ymm3, %ymm3, %ymm3\n vpxor %ymm4, %ymm4, %ymm4\n vpxor %ymm5, %ymm5, %ymm5\n vpxor %ymm6, %ymm6, %ymm6\n vpxor %ymm7, %ymm7, %ymm7\n vpxor %ymm8, %ymm8, %ymm8\n vpxor %ymm9, %ymm9, %ymm9\n vpxor %ymm10, %ymm10, %ymm10\n vpxor %ymm11, %ymm11, %ymm11\n vpxor %ymm12, %ymm12, %ymm12\n vpxor %ymm13, %ymm13, %ymm13\n vpxor %ymm14, %ymm14, %ymm14\n vpxor %ymm15, %ymm15, %ymm15\n.avx512.vnni.256b.dp2a.s32s16s16.L1:\n vpdpwssd %ymm0, %ymm0, %ymm0\n vpdpwssd %ymm1, %ymm1, %ymm1\n vpdpwssd %ymm2, %ymm2, %ymm2\n vpdpwssd %ymm3, %ymm3, %ymm3\n vpdpwssd %ymm4, %ymm4, %ymm4\n vpdpwssd %ymm5, %ymm5, %ymm5\n vpdpwssd %ymm6, %ymm6, %ymm6\n vpdpwssd %ymm7, %ymm7, %ymm7\n vpdpwssd %ymm8, %ymm8, %ymm8\n vpdpwssd %ymm9, %ymm9, %ymm9\n vpdpwssd %ymm10, %ymm10, %ymm10\n vpdpwssd %ymm11, %ymm11, %ymm11\n vpdpwssd %ymm12, %ymm12, %ymm12\n vpdpwssd %ymm13, %ymm13, %ymm13\n vpdpwssd %ymm14, %ymm14, %ymm14\n vpdpwssd %ymm15, %ymm15, %ymm15\n sub $0x1, %rdi\n jne .avx512.vnni.256b.dp2a.s32s16s16.L1\n ret\n\navx512_vnni_128b_dp4a_s32u8s8:\n pxor %xmm0, %xmm0\n pxor %xmm1, %xmm1\n pxor %xmm2, %xmm2\n pxor %xmm3, %xmm3\n pxor %xmm4, %xmm4\n pxor %xmm5, %xmm5\n pxor %xmm6, %xmm6\n pxor %xmm7, %xmm7\n pxor %xmm8, %xmm8\n pxor %xmm9, %xmm9\n pxor %xmm10, %xmm10\n pxor %xmm11, %xmm11\n pxor %xmm12, %xmm12\n pxor %xmm13, %xmm13\n pxor %xmm14, %xmm14\n pxor %xmm15, %xmm15\n.avx512.vnni.128b.dp4a.s32u8s8.L1:\n vpdpbusd %xmm0, %xmm0, %xmm0\n vpdpbusd %xmm1, %xmm1, %xmm1\n vpdpbusd %xmm2, %xmm2, %xmm2\n vpdpbusd %xmm3, %xmm3, %xmm3\n vpdpbusd %xmm4, %xmm4, %xmm4\n vpdpbusd %xmm5, %xmm5, %xmm5\n vpdpbusd %xmm6, %xmm6, %xmm6\n vpdpbusd %xmm7, %xmm7, %xmm7\n vpdpbusd %xmm8, %xmm8, %xmm8\n vpdpbusd %xmm9, %xmm9, %xmm9\n vpdpbusd %xmm10, %xmm10, %xmm10\n vpdpbusd %xmm11, %xmm11, %xmm11\n vpdpbusd %xmm12, %xmm12, %xmm12\n vpdpbusd %xmm13, %xmm13, %xmm13\n vpdpbusd %xmm14, %xmm14, %xmm14\n vpdpbusd %xmm15, %xmm15, %xmm15\n sub $0x1, %rdi\n jne .avx512.vnni.128b.dp4a.s32u8s8.L1\n ret\n\navx512_vnni_128b_dp2a_s32s16s16:\n pxor %xmm0, %xmm0\n pxor %xmm1, %xmm1\n pxor %xmm2, %xmm2\n pxor %xmm3, %xmm3\n pxor %xmm4, %xmm4\n pxor %xmm5, %xmm5\n pxor %xmm6, %xmm6\n pxor %xmm7, %xmm7\n pxor %xmm8, %xmm8\n pxor %xmm9, %xmm9\n pxor %xmm10, %xmm10\n pxor %xmm11, %xmm11\n pxor %xmm12, %xmm12\n pxor %xmm13, %xmm13\n pxor %xmm14, %xmm14\n pxor %xmm15, %xmm15\n.avx512.vnni.128b.dp2a.s32s16s16.L1:\n vpdpwssd %xmm0, %xmm0, %xmm0\n vpdpwssd %xmm1, %xmm1, %xmm1\n vpdpwssd %xmm2, %xmm2, %xmm2\n vpdpwssd %xmm3, %xmm3, %xmm3\n vpdpwssd %xmm4, %xmm4, %xmm4\n vpdpwssd %xmm5, %xmm5, %xmm5\n vpdpwssd %xmm6, %xmm6, %xmm6\n vpdpwssd %xmm7, %xmm7, %xmm7\n vpdpwssd %xmm8, %xmm8, %xmm8\n vpdpwssd %xmm9, %xmm9, %xmm9\n vpdpwssd %xmm10, %xmm10, %xmm10\n vpdpwssd %xmm11, %xmm11, %xmm11\n vpdpwssd %xmm12, %xmm12, %xmm12\n vpdpwssd %xmm13, %xmm13, %xmm13\n vpdpwssd %xmm14, %xmm14, %xmm14\n vpdpwssd %xmm15, %xmm15, %xmm15\n sub $0x1, %rdi\n jne .avx512.vnni.128b.dp2a.s32s16s16.L1\n ret\n\n" }, { "path": "x64/asm/_AVX_.S", "content": ".globl avx_256b_add_mul_f32f32_f32\n.globl avx_256b_add_mul_f64f64_f64\n\navx_256b_add_mul_f32f32_f32:\n vxorps %ymm0, %ymm0, %ymm0\n vxorps %ymm1, %ymm1, %ymm1\n vxorps %ymm2, %ymm2, %ymm2\n vxorps %ymm3, %ymm3, %ymm3\n vxorps %ymm4, %ymm4, %ymm4\n vxorps %ymm5, %ymm5, %ymm5\n vxorps %ymm6, %ymm6, %ymm6\n vxorps %ymm7, %ymm7, %ymm7\n vxorps %ymm8, %ymm8, %ymm8\n vxorps %ymm9, %ymm9, %ymm9\n vxorps %ymm10, %ymm10, %ymm10\n vxorps %ymm11, %ymm11, %ymm11\n vxorps %ymm12, %ymm12, %ymm12\n vxorps %ymm13, %ymm13, %ymm13\n vxorps %ymm14, %ymm14, %ymm14\n vxorps %ymm15, %ymm15, %ymm15\n.avx.256b.add.mul.f32f32.f32.L1:\n vmulps %ymm0, %ymm0, %ymm0\n vaddps %ymm1, %ymm1, %ymm1\n vmulps %ymm2, %ymm2, %ymm2\n vaddps %ymm3, %ymm3, %ymm3\n vmulps %ymm4, %ymm4, %ymm4\n vaddps %ymm5, %ymm5, %ymm5\n vmulps %ymm6, %ymm6, %ymm6\n vaddps %ymm7, %ymm7, %ymm7\n vmulps %ymm8, %ymm8, %ymm8\n vaddps %ymm9, %ymm9, %ymm9\n vmulps %ymm10, %ymm10, %ymm10\n vaddps %ymm11, %ymm11, %ymm11\n vmulps %ymm12, %ymm12, %ymm12\n vaddps %ymm13, %ymm13, %ymm13\n vmulps %ymm14, %ymm14, %ymm14\n vaddps %ymm15, %ymm15, %ymm15\n sub $0x1, %rdi\n jne .avx.256b.add.mul.f32f32.f32.L1\n ret\n\navx_256b_add_mul_f64f64_f64:\n vxorpd %ymm0, %ymm0, %ymm0\n vxorpd %ymm1, %ymm1, %ymm1\n vxorpd %ymm2, %ymm2, %ymm2\n vxorpd %ymm3, %ymm3, %ymm3\n vxorpd %ymm4, %ymm4, %ymm4\n vxorpd %ymm5, %ymm5, %ymm5\n vxorpd %ymm6, %ymm6, %ymm6\n vxorpd %ymm7, %ymm7, %ymm7\n vxorpd %ymm8, %ymm8, %ymm8\n vxorpd %ymm9, %ymm9, %ymm9\n vxorpd %ymm10, %ymm10, %ymm10\n vxorpd %ymm11, %ymm11, %ymm11\n vxorpd %ymm12, %ymm12, %ymm12\n vxorpd %ymm13, %ymm13, %ymm13\n vxorpd %ymm14, %ymm14, %ymm14\n vxorpd %ymm15, %ymm15, %ymm15\n.avx.256b.add.mul.f64f64.f64.L1:\n vmulpd %ymm0, %ymm0, %ymm0\n vaddpd %ymm1, %ymm1, %ymm1\n vmulpd %ymm2, %ymm2, %ymm2\n vaddpd %ymm3, %ymm3, %ymm3\n vmulpd %ymm4, %ymm4, %ymm4\n vaddpd %ymm5, %ymm5, %ymm5\n vmulpd %ymm6, %ymm6, %ymm6\n vaddpd %ymm7, %ymm7, %ymm7\n vmulpd %ymm8, %ymm8, %ymm8\n vaddpd %ymm9, %ymm9, %ymm9\n vmulpd %ymm10, %ymm10, %ymm10\n vaddpd %ymm11, %ymm11, %ymm11\n vmulpd %ymm12, %ymm12, %ymm12\n vaddpd %ymm13, %ymm13, %ymm13\n vmulpd %ymm14, %ymm14, %ymm14\n vaddpd %ymm15, %ymm15, %ymm15\n sub $0x1, %rdi\n jne .avx.256b.add.mul.f64f64.f64.L1\n ret\n\n" }, { "path": "x64/asm/_AVX_VNNI_.S", "content": ".globl avx_vnni_256b_dp4a_s32u8s8\n.globl avx_vnni_256b_dp2a_s32s16s16\n.globl avx_vnni_128b_dp4a_s32u8s8\n.globl avx_vnni_128b_dp2a_s32s16s16\n\navx_vnni_256b_dp4a_s32u8s8:\n vpxor %ymm0, %ymm0, %ymm0\n vpxor %ymm1, %ymm1, %ymm1\n vpxor %ymm2, %ymm2, %ymm2\n vpxor %ymm3, %ymm3, %ymm3\n vpxor %ymm4, %ymm4, %ymm4\n vpxor %ymm5, %ymm5, %ymm5\n vpxor %ymm6, %ymm6, %ymm6\n vpxor %ymm7, %ymm7, %ymm7\n vpxor %ymm8, %ymm8, %ymm8\n vpxor %ymm9, %ymm9, %ymm9\n vpxor %ymm10, %ymm10, %ymm10\n vpxor %ymm11, %ymm11, %ymm11\n vpxor %ymm12, %ymm12, %ymm12\n vpxor %ymm13, %ymm13, %ymm13\n vpxor %ymm14, %ymm14, %ymm14\n vpxor %ymm15, %ymm15, %ymm15\n.avx.vnni.256b.dp4a.s32u8s8.L1:\n {vex} vpdpbusd %ymm0, %ymm0, %ymm0\n {vex} vpdpbusd %ymm1, %ymm1, %ymm1\n {vex} vpdpbusd %ymm2, %ymm2, %ymm2\n {vex} vpdpbusd %ymm3, %ymm3, %ymm3\n {vex} vpdpbusd %ymm4, %ymm4, %ymm4\n {vex} vpdpbusd %ymm5, %ymm5, %ymm5\n {vex} vpdpbusd %ymm6, %ymm6, %ymm6\n {vex} vpdpbusd %ymm7, %ymm7, %ymm7\n {vex} vpdpbusd %ymm8, %ymm8, %ymm8\n {vex} vpdpbusd %ymm9, %ymm9, %ymm9\n {vex} vpdpbusd %ymm10, %ymm10, %ymm10\n {vex} vpdpbusd %ymm11, %ymm11, %ymm11\n {vex} vpdpbusd %ymm12, %ymm12, %ymm12\n {vex} vpdpbusd %ymm13, %ymm13, %ymm13\n {vex} vpdpbusd %ymm14, %ymm14, %ymm14\n {vex} vpdpbusd %ymm15, %ymm15, %ymm15\n sub $0x1, %rdi\n jne .avx.vnni.256b.dp4a.s32u8s8.L1\n ret\n\navx_vnni_256b_dp2a_s32s16s16:\n vpxor %ymm0, %ymm0, %ymm0\n vpxor %ymm1, %ymm1, %ymm1\n vpxor %ymm2, %ymm2, %ymm2\n vpxor %ymm3, %ymm3, %ymm3\n vpxor %ymm4, %ymm4, %ymm4\n vpxor %ymm5, %ymm5, %ymm5\n vpxor %ymm6, %ymm6, %ymm6\n vpxor %ymm7, %ymm7, %ymm7\n vpxor %ymm8, %ymm8, %ymm8\n vpxor %ymm9, %ymm9, %ymm9\n vpxor %ymm10, %ymm10, %ymm10\n vpxor %ymm11, %ymm11, %ymm11\n vpxor %ymm12, %ymm12, %ymm12\n vpxor %ymm13, %ymm13, %ymm13\n vpxor %ymm14, %ymm14, %ymm14\n vpxor %ymm15, %ymm15, %ymm15\n.avx.vnni.256b.dp2a.s32s16s16.L1:\n {vex} vpdpwssd %ymm0, %ymm0, %ymm0\n {vex} vpdpwssd %ymm1, %ymm1, %ymm1\n {vex} vpdpwssd %ymm2, %ymm2, %ymm2\n {vex} vpdpwssd %ymm3, %ymm3, %ymm3\n {vex} vpdpwssd %ymm4, %ymm4, %ymm4\n {vex} vpdpwssd %ymm5, %ymm5, %ymm5\n {vex} vpdpwssd %ymm6, %ymm6, %ymm6\n {vex} vpdpwssd %ymm7, %ymm7, %ymm7\n {vex} vpdpwssd %ymm8, %ymm8, %ymm8\n {vex} vpdpwssd %ymm9, %ymm9, %ymm9\n {vex} vpdpwssd %ymm10, %ymm10, %ymm10\n {vex} vpdpwssd %ymm11, %ymm11, %ymm11\n {vex} vpdpwssd %ymm12, %ymm12, %ymm12\n {vex} vpdpwssd %ymm13, %ymm13, %ymm13\n {vex} vpdpwssd %ymm14, %ymm14, %ymm14\n {vex} vpdpwssd %ymm15, %ymm15, %ymm15\n sub $0x1, %rdi\n jne .avx.vnni.256b.dp2a.s32s16s16.L1\n ret\n\navx_vnni_128b_dp4a_s32u8s8:\n pxor %xmm0, %xmm0\n pxor %xmm1, %xmm1\n pxor %xmm2, %xmm2\n pxor %xmm3, %xmm3\n pxor %xmm4, %xmm4\n pxor %xmm5, %xmm5\n pxor %xmm6, %xmm6\n pxor %xmm7, %xmm7\n pxor %xmm8, %xmm8\n pxor %xmm9, %xmm9\n pxor %xmm10, %xmm10\n pxor %xmm11, %xmm11\n pxor %xmm12, %xmm12\n pxor %xmm13, %xmm13\n pxor %xmm14, %xmm14\n pxor %xmm15, %xmm15\n.avx.vnni.128b.dp4a.s32u8s8.L1:\n {vex} vpdpbusd %xmm0, %xmm0, %xmm0\n {vex} vpdpbusd %xmm1, %xmm1, %xmm1\n {vex} vpdpbusd %xmm2, %xmm2, %xmm2\n {vex} vpdpbusd %xmm3, %xmm3, %xmm3\n {vex} vpdpbusd %xmm4, %xmm4, %xmm4\n {vex} vpdpbusd %xmm5, %xmm5, %xmm5\n {vex} vpdpbusd %xmm6, %xmm6, %xmm6\n {vex} vpdpbusd %xmm7, %xmm7, %xmm7\n {vex} vpdpbusd %xmm8, %xmm8, %xmm8\n {vex} vpdpbusd %xmm9, %xmm9, %xmm9\n {vex} vpdpbusd %xmm10, %xmm10, %xmm10\n {vex} vpdpbusd %xmm11, %xmm11, %xmm11\n {vex} vpdpbusd %xmm12, %xmm12, %xmm12\n {vex} vpdpbusd %xmm13, %xmm13, %xmm13\n {vex} vpdpbusd %xmm14, %xmm14, %xmm14\n {vex} vpdpbusd %xmm15, %xmm15, %xmm15\n sub $0x1, %rdi\n jne .avx.vnni.128b.dp4a.s32u8s8.L1\n ret\n\navx_vnni_128b_dp2a_s32s16s16:\n pxor %xmm0, %xmm0\n pxor %xmm1, %xmm1\n pxor %xmm2, %xmm2\n pxor %xmm3, %xmm3\n pxor %xmm4, %xmm4\n pxor %xmm5, %xmm5\n pxor %xmm6, %xmm6\n pxor %xmm7, %xmm7\n pxor %xmm8, %xmm8\n pxor %xmm9, %xmm9\n pxor %xmm10, %xmm10\n pxor %xmm11, %xmm11\n pxor %xmm12, %xmm12\n pxor %xmm13, %xmm13\n pxor %xmm14, %xmm14\n pxor %xmm15, %xmm15\n.avx.vnni.128b.dp2a.s32s16s16.L1:\n {vex} vpdpwssd %xmm0, %xmm0, %xmm0\n {vex} vpdpwssd %xmm1, %xmm1, %xmm1\n {vex} vpdpwssd %xmm2, %xmm2, %xmm2\n {vex} vpdpwssd %xmm3, %xmm3, %xmm3\n {vex} vpdpwssd %xmm4, %xmm4, %xmm4\n {vex} vpdpwssd %xmm5, %xmm5, %xmm5\n {vex} vpdpwssd %xmm6, %xmm6, %xmm6\n {vex} vpdpwssd %xmm7, %xmm7, %xmm7\n {vex} vpdpwssd %xmm8, %xmm8, %xmm8\n {vex} vpdpwssd %xmm9, %xmm9, %xmm9\n {vex} vpdpwssd %xmm10, %xmm10, %xmm10\n {vex} vpdpwssd %xmm11, %xmm11, %xmm11\n {vex} vpdpwssd %xmm12, %xmm12, %xmm12\n {vex} vpdpwssd %xmm13, %xmm13, %xmm13\n {vex} vpdpwssd %xmm14, %xmm14, %xmm14\n {vex} vpdpwssd %xmm15, %xmm15, %xmm15\n sub $0x1, %rdi\n jne .avx.vnni.128b.dp2a.s32s16s16.L1\n ret\n\n" }, { "path": "x64/asm/_AVX_VNNI_INT16_.S", "content": ".globl avx_vnni_int16_256b_dp2a_s32s16u16\n.globl avx_vnni_int16_256b_dp2a_s32u16s16\n.globl avx_vnni_int16_256b_dp2a_s32u16u16\n.globl avx_vnni_int16_128b_dp2a_s32s16u16\n.globl avx_vnni_int16_128b_dp2a_s32u16s16\n.globl avx_vnni_int16_128b_dp2a_s32u16u16\n\navx_vnni_int16_256b_dp2a_s32s16u16:\n vpxor %ymm0, %ymm0, %ymm0\n vpxor %ymm1, %ymm1, %ymm1\n vpxor %ymm2, %ymm2, %ymm2\n vpxor %ymm3, %ymm3, %ymm3\n vpxor %ymm4, %ymm4, %ymm4\n vpxor %ymm5, %ymm5, %ymm5\n vpxor %ymm6, %ymm6, %ymm6\n vpxor %ymm7, %ymm7, %ymm7\n vpxor %ymm8, %ymm8, %ymm8\n vpxor %ymm9, %ymm9, %ymm9\n vpxor %ymm10, %ymm10, %ymm10\n vpxor %ymm11, %ymm11, %ymm11\n vpxor %ymm12, %ymm12, %ymm12\n vpxor %ymm13, %ymm13, %ymm13\n vpxor %ymm14, %ymm14, %ymm14\n vpxor %ymm15, %ymm15, %ymm15\n.avx.vnni.int16.256b.dp2a.s32s16u16.L1:\n vpdpwsud %ymm0, %ymm0, %ymm0\n vpdpwsud %ymm1, %ymm1, %ymm1\n vpdpwsud %ymm2, %ymm2, %ymm2\n vpdpwsud %ymm3, %ymm3, %ymm3\n vpdpwsud %ymm4, %ymm4, %ymm4\n vpdpwsud %ymm5, %ymm5, %ymm5\n vpdpwsud %ymm6, %ymm6, %ymm6\n vpdpwsud %ymm7, %ymm7, %ymm7\n vpdpwsud %ymm8, %ymm8, %ymm8\n vpdpwsud %ymm9, %ymm9, %ymm9\n vpdpwsud %ymm10, %ymm10, %ymm10\n vpdpwsud %ymm11, %ymm11, %ymm11\n vpdpwsud %ymm12, %ymm12, %ymm12\n vpdpwsud %ymm13, %ymm13, %ymm13\n vpdpwsud %ymm14, %ymm14, %ymm14\n vpdpwsud %ymm15, %ymm15, %ymm15\n sub $0x1, %rdi\n jne .avx.vnni.int16.256b.dp2a.s32s16u16.L1\n ret\n\navx_vnni_int16_256b_dp2a_s32u16s16:\n vpxor %ymm0, %ymm0, %ymm0\n vpxor %ymm1, %ymm1, %ymm1\n vpxor %ymm2, %ymm2, %ymm2\n vpxor %ymm3, %ymm3, %ymm3\n vpxor %ymm4, %ymm4, %ymm4\n vpxor %ymm5, %ymm5, %ymm5\n vpxor %ymm6, %ymm6, %ymm6\n vpxor %ymm7, %ymm7, %ymm7\n vpxor %ymm8, %ymm8, %ymm8\n vpxor %ymm9, %ymm9, %ymm9\n vpxor %ymm10, %ymm10, %ymm10\n vpxor %ymm11, %ymm11, %ymm11\n vpxor %ymm12, %ymm12, %ymm12\n vpxor %ymm13, %ymm13, %ymm13\n vpxor %ymm14, %ymm14, %ymm14\n vpxor %ymm15, %ymm15, %ymm15\n.avx.vnni.int16.256b.dp2a.s32u16s16.L1:\n vpdpwusd %ymm0, %ymm0, %ymm0\n vpdpwusd %ymm1, %ymm1, %ymm1\n vpdpwusd %ymm2, %ymm2, %ymm2\n vpdpwusd %ymm3, %ymm3, %ymm3\n vpdpwusd %ymm4, %ymm4, %ymm4\n vpdpwusd %ymm5, %ymm5, %ymm5\n vpdpwusd %ymm6, %ymm6, %ymm6\n vpdpwusd %ymm7, %ymm7, %ymm7\n vpdpwusd %ymm8, %ymm8, %ymm8\n vpdpwusd %ymm9, %ymm9, %ymm9\n vpdpwusd %ymm10, %ymm10, %ymm10\n vpdpwusd %ymm11, %ymm11, %ymm11\n vpdpwusd %ymm12, %ymm12, %ymm12\n vpdpwusd %ymm13, %ymm13, %ymm13\n vpdpwusd %ymm14, %ymm14, %ymm14\n vpdpwusd %ymm15, %ymm15, %ymm15\n sub $0x1, %rdi\n jne .avx.vnni.int16.256b.dp2a.s32u16s16.L1\n ret\n\navx_vnni_int16_256b_dp2a_s32u16u16:\n vpxor %ymm0, %ymm0, %ymm0\n vpxor %ymm1, %ymm1, %ymm1\n vpxor %ymm2, %ymm2, %ymm2\n vpxor %ymm3, %ymm3, %ymm3\n vpxor %ymm4, %ymm4, %ymm4\n vpxor %ymm5, %ymm5, %ymm5\n vpxor %ymm6, %ymm6, %ymm6\n vpxor %ymm7, %ymm7, %ymm7\n vpxor %ymm8, %ymm8, %ymm8\n vpxor %ymm9, %ymm9, %ymm9\n vpxor %ymm10, %ymm10, %ymm10\n vpxor %ymm11, %ymm11, %ymm11\n vpxor %ymm12, %ymm12, %ymm12\n vpxor %ymm13, %ymm13, %ymm13\n vpxor %ymm14, %ymm14, %ymm14\n vpxor %ymm15, %ymm15, %ymm15\n.avx.vnni.int16.256b.dp2a.s32u16u16.L1:\n vpdpwuud %ymm0, %ymm0, %ymm0\n vpdpwuud %ymm1, %ymm1, %ymm1\n vpdpwuud %ymm2, %ymm2, %ymm2\n vpdpwuud %ymm3, %ymm3, %ymm3\n vpdpwuud %ymm4, %ymm4, %ymm4\n vpdpwuud %ymm5, %ymm5, %ymm5\n vpdpwuud %ymm6, %ymm6, %ymm6\n vpdpwuud %ymm7, %ymm7, %ymm7\n vpdpwuud %ymm8, %ymm8, %ymm8\n vpdpwuud %ymm9, %ymm9, %ymm9\n vpdpwuud %ymm10, %ymm10, %ymm10\n vpdpwuud %ymm11, %ymm11, %ymm11\n vpdpwuud %ymm12, %ymm12, %ymm12\n vpdpwuud %ymm13, %ymm13, %ymm13\n vpdpwuud %ymm14, %ymm14, %ymm14\n vpdpwuud %ymm15, %ymm15, %ymm15\n sub $0x1, %rdi\n jne .avx.vnni.int16.256b.dp2a.s32u16u16.L1\n ret\n\navx_vnni_int16_128b_dp2a_s32s16u16:\n pxor %xmm0, %xmm0\n pxor %xmm1, %xmm1\n pxor %xmm2, %xmm2\n pxor %xmm3, %xmm3\n pxor %xmm4, %xmm4\n pxor %xmm5, %xmm5\n pxor %xmm6, %xmm6\n pxor %xmm7, %xmm7\n pxor %xmm8, %xmm8\n pxor %xmm9, %xmm9\n pxor %xmm10, %xmm10\n pxor %xmm11, %xmm11\n pxor %xmm12, %xmm12\n pxor %xmm13, %xmm13\n pxor %xmm14, %xmm14\n pxor %xmm15, %xmm15\n.avx.vnni.int16.128b.dp2a.s32s16u16.L1:\n vpdpwsud %xmm0, %xmm0, %xmm0\n vpdpwsud %xmm1, %xmm1, %xmm1\n vpdpwsud %xmm2, %xmm2, %xmm2\n vpdpwsud %xmm3, %xmm3, %xmm3\n vpdpwsud %xmm4, %xmm4, %xmm4\n vpdpwsud %xmm5, %xmm5, %xmm5\n vpdpwsud %xmm6, %xmm6, %xmm6\n vpdpwsud %xmm7, %xmm7, %xmm7\n vpdpwsud %xmm8, %xmm8, %xmm8\n vpdpwsud %xmm9, %xmm9, %xmm9\n vpdpwsud %xmm10, %xmm10, %xmm10\n vpdpwsud %xmm11, %xmm11, %xmm11\n vpdpwsud %xmm12, %xmm12, %xmm12\n vpdpwsud %xmm13, %xmm13, %xmm13\n vpdpwsud %xmm14, %xmm14, %xmm14\n vpdpwsud %xmm15, %xmm15, %xmm15\n sub $0x1, %rdi\n jne .avx.vnni.int16.128b.dp2a.s32s16u16.L1\n ret\n\navx_vnni_int16_128b_dp2a_s32u16s16:\n pxor %xmm0, %xmm0\n pxor %xmm1, %xmm1\n pxor %xmm2, %xmm2\n pxor %xmm3, %xmm3\n pxor %xmm4, %xmm4\n pxor %xmm5, %xmm5\n pxor %xmm6, %xmm6\n pxor %xmm7, %xmm7\n pxor %xmm8, %xmm8\n pxor %xmm9, %xmm9\n pxor %xmm10, %xmm10\n pxor %xmm11, %xmm11\n pxor %xmm12, %xmm12\n pxor %xmm13, %xmm13\n pxor %xmm14, %xmm14\n pxor %xmm15, %xmm15\n.avx.vnni.int16.128b.dp2a.s32u16s16.L1:\n vpdpwusd %xmm0, %xmm0, %xmm0\n vpdpwusd %xmm1, %xmm1, %xmm1\n vpdpwusd %xmm2, %xmm2, %xmm2\n vpdpwusd %xmm3, %xmm3, %xmm3\n vpdpwusd %xmm4, %xmm4, %xmm4\n vpdpwusd %xmm5, %xmm5, %xmm5\n vpdpwusd %xmm6, %xmm6, %xmm6\n vpdpwusd %xmm7, %xmm7, %xmm7\n vpdpwusd %xmm8, %xmm8, %xmm8\n vpdpwusd %xmm9, %xmm9, %xmm9\n vpdpwusd %xmm10, %xmm10, %xmm10\n vpdpwusd %xmm11, %xmm11, %xmm11\n vpdpwusd %xmm12, %xmm12, %xmm12\n vpdpwusd %xmm13, %xmm13, %xmm13\n vpdpwusd %xmm14, %xmm14, %xmm14\n vpdpwusd %xmm15, %xmm15, %xmm15\n sub $0x1, %rdi\n jne .avx.vnni.int16.128b.dp2a.s32u16s16.L1\n ret\n\navx_vnni_int16_128b_dp2a_s32u16u16:\n pxor %xmm0, %xmm0\n pxor %xmm1, %xmm1\n pxor %xmm2, %xmm2\n pxor %xmm3, %xmm3\n pxor %xmm4, %xmm4\n pxor %xmm5, %xmm5\n pxor %xmm6, %xmm6\n pxor %xmm7, %xmm7\n pxor %xmm8, %xmm8\n pxor %xmm9, %xmm9\n pxor %xmm10, %xmm10\n pxor %xmm11, %xmm11\n pxor %xmm12, %xmm12\n pxor %xmm13, %xmm13\n pxor %xmm14, %xmm14\n pxor %xmm15, %xmm15\n.avx.vnni.int16.128b.dp2a.s32u16u16.L1:\n vpdpwuud %xmm0, %xmm0, %xmm0\n vpdpwuud %xmm1, %xmm1, %xmm1\n vpdpwuud %xmm2, %xmm2, %xmm2\n vpdpwuud %xmm3, %xmm3, %xmm3\n vpdpwuud %xmm4, %xmm4, %xmm4\n vpdpwuud %xmm5, %xmm5, %xmm5\n vpdpwuud %xmm6, %xmm6, %xmm6\n vpdpwuud %xmm7, %xmm7, %xmm7\n vpdpwuud %xmm8, %xmm8, %xmm8\n vpdpwuud %xmm9, %xmm9, %xmm9\n vpdpwuud %xmm10, %xmm10, %xmm10\n vpdpwuud %xmm11, %xmm11, %xmm11\n vpdpwuud %xmm12, %xmm12, %xmm12\n vpdpwuud %xmm13, %xmm13, %xmm13\n vpdpwuud %xmm14, %xmm14, %xmm14\n vpdpwuud %xmm15, %xmm15, %xmm15\n sub $0x1, %rdi\n jne .avx.vnni.int16.128b.dp2a.s32u16u16.L1\n ret\n\n" }, { "path": "x64/asm/_AVX_VNNI_INT8_.S", "content": ".globl avx_vnni_int8_256b_dp4a_s32s8s8\n.globl avx_vnni_int8_256b_dp4a_s32s8u8\n.globl avx_vnni_int8_256b_dp4a_s32u8u8\n.globl avx_vnni_int8_128b_dp4a_s32s8s8\n.globl avx_vnni_int8_128b_dp4a_s32s8u8\n.globl avx_vnni_int8_128b_dp4a_s32u8u8\n\navx_vnni_int8_256b_dp4a_s32s8s8:\n vpxor %ymm0, %ymm0, %ymm0\n vpxor %ymm1, %ymm1, %ymm1\n vpxor %ymm2, %ymm2, %ymm2\n vpxor %ymm3, %ymm3, %ymm3\n vpxor %ymm4, %ymm4, %ymm4\n vpxor %ymm5, %ymm5, %ymm5\n vpxor %ymm6, %ymm6, %ymm6\n vpxor %ymm7, %ymm7, %ymm7\n vpxor %ymm8, %ymm8, %ymm8\n vpxor %ymm9, %ymm9, %ymm9\n vpxor %ymm10, %ymm10, %ymm10\n vpxor %ymm11, %ymm11, %ymm11\n vpxor %ymm12, %ymm12, %ymm12\n vpxor %ymm13, %ymm13, %ymm13\n vpxor %ymm14, %ymm14, %ymm14\n vpxor %ymm15, %ymm15, %ymm15\n.avx.vnni.int8.256b.dp4a.s32s8s8.L1:\n vpdpbssd %ymm0, %ymm0, %ymm0\n vpdpbssd %ymm1, %ymm1, %ymm1\n vpdpbssd %ymm2, %ymm2, %ymm2\n vpdpbssd %ymm3, %ymm3, %ymm3\n vpdpbssd %ymm4, %ymm4, %ymm4\n vpdpbssd %ymm5, %ymm5, %ymm5\n vpdpbssd %ymm6, %ymm6, %ymm6\n vpdpbssd %ymm7, %ymm7, %ymm7\n vpdpbssd %ymm8, %ymm8, %ymm8\n vpdpbssd %ymm9, %ymm9, %ymm9\n vpdpbssd %ymm10, %ymm10, %ymm10\n vpdpbssd %ymm11, %ymm11, %ymm11\n vpdpbssd %ymm12, %ymm12, %ymm12\n vpdpbssd %ymm13, %ymm13, %ymm13\n vpdpbssd %ymm14, %ymm14, %ymm14\n vpdpbssd %ymm15, %ymm15, %ymm15\n sub $0x1, %rdi\n jne .avx.vnni.int8.256b.dp4a.s32s8s8.L1\n ret\n\navx_vnni_int8_256b_dp4a_s32s8u8:\n vpxor %ymm0, %ymm0, %ymm0\n vpxor %ymm1, %ymm1, %ymm1\n vpxor %ymm2, %ymm2, %ymm2\n vpxor %ymm3, %ymm3, %ymm3\n vpxor %ymm4, %ymm4, %ymm4\n vpxor %ymm5, %ymm5, %ymm5\n vpxor %ymm6, %ymm6, %ymm6\n vpxor %ymm7, %ymm7, %ymm7\n vpxor %ymm8, %ymm8, %ymm8\n vpxor %ymm9, %ymm9, %ymm9\n vpxor %ymm10, %ymm10, %ymm10\n vpxor %ymm11, %ymm11, %ymm11\n vpxor %ymm12, %ymm12, %ymm12\n vpxor %ymm13, %ymm13, %ymm13\n vpxor %ymm14, %ymm14, %ymm14\n vpxor %ymm15, %ymm15, %ymm15\n.avx.vnni.int8.256b.dp4a.s32s8u8.L1:\n vpdpbsud %ymm0, %ymm0, %ymm0\n vpdpbsud %ymm1, %ymm1, %ymm1\n vpdpbsud %ymm2, %ymm2, %ymm2\n vpdpbsud %ymm3, %ymm3, %ymm3\n vpdpbsud %ymm4, %ymm4, %ymm4\n vpdpbsud %ymm5, %ymm5, %ymm5\n vpdpbsud %ymm6, %ymm6, %ymm6\n vpdpbsud %ymm7, %ymm7, %ymm7\n vpdpbsud %ymm8, %ymm8, %ymm8\n vpdpbsud %ymm9, %ymm9, %ymm9\n vpdpbsud %ymm10, %ymm10, %ymm10\n vpdpbsud %ymm11, %ymm11, %ymm11\n vpdpbsud %ymm12, %ymm12, %ymm12\n vpdpbsud %ymm13, %ymm13, %ymm13\n vpdpbsud %ymm14, %ymm14, %ymm14\n vpdpbsud %ymm15, %ymm15, %ymm15\n sub $0x1, %rdi\n jne .avx.vnni.int8.256b.dp4a.s32s8u8.L1\n ret\n\navx_vnni_int8_256b_dp4a_s32u8u8:\n vpxor %ymm0, %ymm0, %ymm0\n vpxor %ymm1, %ymm1, %ymm1\n vpxor %ymm2, %ymm2, %ymm2\n vpxor %ymm3, %ymm3, %ymm3\n vpxor %ymm4, %ymm4, %ymm4\n vpxor %ymm5, %ymm5, %ymm5\n vpxor %ymm6, %ymm6, %ymm6\n vpxor %ymm7, %ymm7, %ymm7\n vpxor %ymm8, %ymm8, %ymm8\n vpxor %ymm9, %ymm9, %ymm9\n vpxor %ymm10, %ymm10, %ymm10\n vpxor %ymm11, %ymm11, %ymm11\n vpxor %ymm12, %ymm12, %ymm12\n vpxor %ymm13, %ymm13, %ymm13\n vpxor %ymm14, %ymm14, %ymm14\n vpxor %ymm15, %ymm15, %ymm15\n.avx.vnni.int8.256b.dp4a.s32u8u8.L1:\n vpdpbuud %ymm0, %ymm0, %ymm0\n vpdpbuud %ymm1, %ymm1, %ymm1\n vpdpbuud %ymm2, %ymm2, %ymm2\n vpdpbuud %ymm3, %ymm3, %ymm3\n vpdpbuud %ymm4, %ymm4, %ymm4\n vpdpbuud %ymm5, %ymm5, %ymm5\n vpdpbuud %ymm6, %ymm6, %ymm6\n vpdpbuud %ymm7, %ymm7, %ymm7\n vpdpbuud %ymm8, %ymm8, %ymm8\n vpdpbuud %ymm9, %ymm9, %ymm9\n vpdpbuud %ymm10, %ymm10, %ymm10\n vpdpbuud %ymm11, %ymm11, %ymm11\n vpdpbuud %ymm12, %ymm12, %ymm12\n vpdpbuud %ymm13, %ymm13, %ymm13\n vpdpbuud %ymm14, %ymm14, %ymm14\n vpdpbuud %ymm15, %ymm15, %ymm15\n sub $0x1, %rdi\n jne .avx.vnni.int8.256b.dp4a.s32u8u8.L1\n ret\n\navx_vnni_int8_128b_dp4a_s32s8s8:\n pxor %xmm0, %xmm0\n pxor %xmm1, %xmm1\n pxor %xmm2, %xmm2\n pxor %xmm3, %xmm3\n pxor %xmm4, %xmm4\n pxor %xmm5, %xmm5\n pxor %xmm6, %xmm6\n pxor %xmm7, %xmm7\n pxor %xmm8, %xmm8\n pxor %xmm9, %xmm9\n pxor %xmm10, %xmm10\n pxor %xmm11, %xmm11\n pxor %xmm12, %xmm12\n pxor %xmm13, %xmm13\n pxor %xmm14, %xmm14\n pxor %xmm15, %xmm15\n.avx.vnni.int8.128b.dp4a.s32s8s8.L1:\n vpdpbssd %xmm0, %xmm0, %xmm0\n vpdpbssd %xmm1, %xmm1, %xmm1\n vpdpbssd %xmm2, %xmm2, %xmm2\n vpdpbssd %xmm3, %xmm3, %xmm3\n vpdpbssd %xmm4, %xmm4, %xmm4\n vpdpbssd %xmm5, %xmm5, %xmm5\n vpdpbssd %xmm6, %xmm6, %xmm6\n vpdpbssd %xmm7, %xmm7, %xmm7\n vpdpbssd %xmm8, %xmm8, %xmm8\n vpdpbssd %xmm9, %xmm9, %xmm9\n vpdpbssd %xmm10, %xmm10, %xmm10\n vpdpbssd %xmm11, %xmm11, %xmm11\n vpdpbssd %xmm12, %xmm12, %xmm12\n vpdpbssd %xmm13, %xmm13, %xmm13\n vpdpbssd %xmm14, %xmm14, %xmm14\n vpdpbssd %xmm15, %xmm15, %xmm15\n sub $0x1, %rdi\n jne .avx.vnni.int8.128b.dp4a.s32s8s8.L1\n ret\n\navx_vnni_int8_128b_dp4a_s32s8u8:\n pxor %xmm0, %xmm0\n pxor %xmm1, %xmm1\n pxor %xmm2, %xmm2\n pxor %xmm3, %xmm3\n pxor %xmm4, %xmm4\n pxor %xmm5, %xmm5\n pxor %xmm6, %xmm6\n pxor %xmm7, %xmm7\n pxor %xmm8, %xmm8\n pxor %xmm9, %xmm9\n pxor %xmm10, %xmm10\n pxor %xmm11, %xmm11\n pxor %xmm12, %xmm12\n pxor %xmm13, %xmm13\n pxor %xmm14, %xmm14\n pxor %xmm15, %xmm15\n.avx.vnni.int8.128b.dp4a.s32s8u8.L1:\n vpdpbsud %xmm0, %xmm0, %xmm0\n vpdpbsud %xmm1, %xmm1, %xmm1\n vpdpbsud %xmm2, %xmm2, %xmm2\n vpdpbsud %xmm3, %xmm3, %xmm3\n vpdpbsud %xmm4, %xmm4, %xmm4\n vpdpbsud %xmm5, %xmm5, %xmm5\n vpdpbsud %xmm6, %xmm6, %xmm6\n vpdpbsud %xmm7, %xmm7, %xmm7\n vpdpbsud %xmm8, %xmm8, %xmm8\n vpdpbsud %xmm9, %xmm9, %xmm9\n vpdpbsud %xmm10, %xmm10, %xmm10\n vpdpbsud %xmm11, %xmm11, %xmm11\n vpdpbsud %xmm12, %xmm12, %xmm12\n vpdpbsud %xmm13, %xmm13, %xmm13\n vpdpbsud %xmm14, %xmm14, %xmm14\n vpdpbsud %xmm15, %xmm15, %xmm15\n sub $0x1, %rdi\n jne .avx.vnni.int8.128b.dp4a.s32s8u8.L1\n ret\n\navx_vnni_int8_128b_dp4a_s32u8u8:\n pxor %xmm0, %xmm0\n pxor %xmm1, %xmm1\n pxor %xmm2, %xmm2\n pxor %xmm3, %xmm3\n pxor %xmm4, %xmm4\n pxor %xmm5, %xmm5\n pxor %xmm6, %xmm6\n pxor %xmm7, %xmm7\n pxor %xmm8, %xmm8\n pxor %xmm9, %xmm9\n pxor %xmm10, %xmm10\n pxor %xmm11, %xmm11\n pxor %xmm12, %xmm12\n pxor %xmm13, %xmm13\n pxor %xmm14, %xmm14\n pxor %xmm15, %xmm15\n.avx.vnni.int8.128b.dp4a.s32u8u8.L1:\n vpdpbuud %xmm0, %xmm0, %xmm0\n vpdpbuud %xmm1, %xmm1, %xmm1\n vpdpbuud %xmm2, %xmm2, %xmm2\n vpdpbuud %xmm3, %xmm3, %xmm3\n vpdpbuud %xmm4, %xmm4, %xmm4\n vpdpbuud %xmm5, %xmm5, %xmm5\n vpdpbuud %xmm6, %xmm6, %xmm6\n vpdpbuud %xmm7, %xmm7, %xmm7\n vpdpbuud %xmm8, %xmm8, %xmm8\n vpdpbuud %xmm9, %xmm9, %xmm9\n vpdpbuud %xmm10, %xmm10, %xmm10\n vpdpbuud %xmm11, %xmm11, %xmm11\n vpdpbuud %xmm12, %xmm12, %xmm12\n vpdpbuud %xmm13, %xmm13, %xmm13\n vpdpbuud %xmm14, %xmm14, %xmm14\n vpdpbuud %xmm15, %xmm15, %xmm15\n sub $0x1, %rdi\n jne .avx.vnni.int8.128b.dp4a.s32u8u8.L1\n ret\n\n" }, { "path": "x64/asm/_FMA_.S", "content": ".globl fma_256b_fma_f32f32f32\n.globl fma_256b_fma_f64f64f64\n.globl fma_128b_fma_f32f32f32\n.globl fma_128b_fma_f64f64f64\n\nfma_256b_fma_f32f32f32:\n vxorps %ymm0, %ymm0, %ymm0\n vxorps %ymm1, %ymm1, %ymm1\n vxorps %ymm2, %ymm2, %ymm2\n vxorps %ymm3, %ymm3, %ymm3\n vxorps %ymm4, %ymm4, %ymm4\n vxorps %ymm5, %ymm5, %ymm5\n vxorps %ymm6, %ymm6, %ymm6\n vxorps %ymm7, %ymm7, %ymm7\n vxorps %ymm8, %ymm8, %ymm8\n vxorps %ymm9, %ymm9, %ymm9\n vxorps %ymm10, %ymm10, %ymm10\n vxorps %ymm11, %ymm11, %ymm11\n vxorps %ymm12, %ymm12, %ymm12\n vxorps %ymm13, %ymm13, %ymm13\n vxorps %ymm14, %ymm14, %ymm14\n vxorps %ymm15, %ymm15, %ymm15\n.fma.256b.fma.f32f32f32.L1:\n vfmadd231ps %ymm0, %ymm0, %ymm0\n vfmadd231ps %ymm1, %ymm1, %ymm1\n vfmadd231ps %ymm2, %ymm2, %ymm2\n vfmadd231ps %ymm3, %ymm3, %ymm3\n vfmadd231ps %ymm4, %ymm4, %ymm4\n vfmadd231ps %ymm5, %ymm5, %ymm5\n vfmadd231ps %ymm6, %ymm6, %ymm6\n vfmadd231ps %ymm7, %ymm7, %ymm7\n vfmadd231ps %ymm8, %ymm8, %ymm8\n vfmadd231ps %ymm9, %ymm9, %ymm9\n vfmadd231ps %ymm10, %ymm10, %ymm10\n vfmadd231ps %ymm11, %ymm11, %ymm11\n vfmadd231ps %ymm12, %ymm12, %ymm12\n vfmadd231ps %ymm13, %ymm13, %ymm13\n vfmadd231ps %ymm14, %ymm14, %ymm14\n vfmadd231ps %ymm15, %ymm15, %ymm15\n sub $0x1, %rdi\n jne .fma.256b.fma.f32f32f32.L1\n ret\n\nfma_256b_fma_f64f64f64:\n vxorpd %ymm0, %ymm0, %ymm0\n vxorpd %ymm1, %ymm1, %ymm1\n vxorpd %ymm2, %ymm2, %ymm2\n vxorpd %ymm3, %ymm3, %ymm3\n vxorpd %ymm4, %ymm4, %ymm4\n vxorpd %ymm5, %ymm5, %ymm5\n vxorpd %ymm6, %ymm6, %ymm6\n vxorpd %ymm7, %ymm7, %ymm7\n vxorpd %ymm8, %ymm8, %ymm8\n vxorpd %ymm9, %ymm9, %ymm9\n vxorpd %ymm10, %ymm10, %ymm10\n vxorpd %ymm11, %ymm11, %ymm11\n vxorpd %ymm12, %ymm12, %ymm12\n vxorpd %ymm13, %ymm13, %ymm13\n vxorpd %ymm14, %ymm14, %ymm14\n vxorpd %ymm15, %ymm15, %ymm15\n.fma.256b.fma.f64f64f64.L1:\n vfmadd231pd %ymm0, %ymm0, %ymm0\n vfmadd231pd %ymm1, %ymm1, %ymm1\n vfmadd231pd %ymm2, %ymm2, %ymm2\n vfmadd231pd %ymm3, %ymm3, %ymm3\n vfmadd231pd %ymm4, %ymm4, %ymm4\n vfmadd231pd %ymm5, %ymm5, %ymm5\n vfmadd231pd %ymm6, %ymm6, %ymm6\n vfmadd231pd %ymm7, %ymm7, %ymm7\n vfmadd231pd %ymm8, %ymm8, %ymm8\n vfmadd231pd %ymm9, %ymm9, %ymm9\n vfmadd231pd %ymm10, %ymm10, %ymm10\n vfmadd231pd %ymm11, %ymm11, %ymm11\n vfmadd231pd %ymm12, %ymm12, %ymm12\n vfmadd231pd %ymm13, %ymm13, %ymm13\n vfmadd231pd %ymm14, %ymm14, %ymm14\n vfmadd231pd %ymm15, %ymm15, %ymm15\n sub $0x1, %rdi\n jne .fma.256b.fma.f64f64f64.L1\n ret\n\nfma_128b_fma_f32f32f32:\n xorps %xmm0, %xmm0\n xorps %xmm1, %xmm1\n xorps %xmm2, %xmm2\n xorps %xmm3, %xmm3\n xorps %xmm4, %xmm4\n xorps %xmm5, %xmm5\n xorps %xmm6, %xmm6\n xorps %xmm7, %xmm7\n xorps %xmm8, %xmm8\n xorps %xmm9, %xmm9\n xorps %xmm10, %xmm10\n xorps %xmm11, %xmm11\n xorps %xmm12, %xmm12\n xorps %xmm13, %xmm13\n xorps %xmm14, %xmm14\n xorps %xmm15, %xmm15\n.fma.128b.fma.f32f32f32.L1:\n vfmadd231ps %xmm0, %xmm0, %xmm0\n vfmadd231ps %xmm1, %xmm1, %xmm1\n vfmadd231ps %xmm2, %xmm2, %xmm2\n vfmadd231ps %xmm3, %xmm3, %xmm3\n vfmadd231ps %xmm4, %xmm4, %xmm4\n vfmadd231ps %xmm5, %xmm5, %xmm5\n vfmadd231ps %xmm6, %xmm6, %xmm6\n vfmadd231ps %xmm7, %xmm7, %xmm7\n vfmadd231ps %xmm8, %xmm8, %xmm8\n vfmadd231ps %xmm9, %xmm9, %xmm9\n vfmadd231ps %xmm10, %xmm10, %xmm10\n vfmadd231ps %xmm11, %xmm11, %xmm11\n vfmadd231ps %xmm12, %xmm12, %xmm12\n vfmadd231ps %xmm13, %xmm13, %xmm13\n vfmadd231ps %xmm14, %xmm14, %xmm14\n vfmadd231ps %xmm15, %xmm15, %xmm15\n sub $0x1, %rdi\n jne .fma.128b.fma.f32f32f32.L1\n ret\n\nfma_128b_fma_f64f64f64:\n xorpd %xmm0, %xmm0\n xorpd %xmm1, %xmm1\n xorpd %xmm2, %xmm2\n xorpd %xmm3, %xmm3\n xorpd %xmm4, %xmm4\n xorpd %xmm5, %xmm5\n xorpd %xmm6, %xmm6\n xorpd %xmm7, %xmm7\n xorpd %xmm8, %xmm8\n xorpd %xmm9, %xmm9\n xorpd %xmm10, %xmm10\n xorpd %xmm11, %xmm11\n xorpd %xmm12, %xmm12\n xorpd %xmm13, %xmm13\n xorpd %xmm14, %xmm14\n xorpd %xmm15, %xmm15\n.fma.128b.fma.f64f64f64.L1:\n vfmadd231pd %xmm0, %xmm0, %xmm0\n vfmadd231pd %xmm1, %xmm1, %xmm1\n vfmadd231pd %xmm2, %xmm2, %xmm2\n vfmadd231pd %xmm3, %xmm3, %xmm3\n vfmadd231pd %xmm4, %xmm4, %xmm4\n vfmadd231pd %xmm5, %xmm5, %xmm5\n vfmadd231pd %xmm6, %xmm6, %xmm6\n vfmadd231pd %xmm7, %xmm7, %xmm7\n vfmadd231pd %xmm8, %xmm8, %xmm8\n vfmadd231pd %xmm9, %xmm9, %xmm9\n vfmadd231pd %xmm10, %xmm10, %xmm10\n vfmadd231pd %xmm11, %xmm11, %xmm11\n vfmadd231pd %xmm12, %xmm12, %xmm12\n vfmadd231pd %xmm13, %xmm13, %xmm13\n vfmadd231pd %xmm14, %xmm14, %xmm14\n vfmadd231pd %xmm15, %xmm15, %xmm15\n sub $0x1, %rdi\n jne .fma.128b.fma.f64f64f64.L1\n ret\n\n" }, { "path": "x64/asm/_SSE2_.S", "content": ".globl sse2_128b_add_mul_f64f64_f64\n\nsse2_128b_add_mul_f64f64_f64:\n xorpd %xmm0, %xmm0\n xorpd %xmm1, %xmm1\n xorpd %xmm2, %xmm2\n xorpd %xmm3, %xmm3\n xorpd %xmm4, %xmm4\n xorpd %xmm5, %xmm5\n xorpd %xmm6, %xmm6\n xorpd %xmm7, %xmm7\n xorpd %xmm8, %xmm8\n xorpd %xmm9, %xmm9\n xorpd %xmm10, %xmm10\n xorpd %xmm11, %xmm11\n xorpd %xmm12, %xmm12\n xorpd %xmm13, %xmm13\n xorpd %xmm14, %xmm14\n xorpd %xmm15, %xmm15\n.sse2.128b.add.mul.f64f64.f64.L1:\n mulpd %xmm0, %xmm0\n addpd %xmm1, %xmm1\n mulpd %xmm2, %xmm2\n addpd %xmm3, %xmm3\n mulpd %xmm4, %xmm4\n addpd %xmm5, %xmm5\n mulpd %xmm6, %xmm6\n addpd %xmm7, %xmm7\n sub $0x1, %rdi\n mulpd %xmm8, %xmm8\n addpd %xmm9, %xmm9\n mulpd %xmm10, %xmm10\n addpd %xmm11, %xmm11\n mulpd %xmm12, %xmm12\n addpd %xmm13, %xmm13\n mulpd %xmm14, %xmm14\n addpd %xmm15, %xmm15\n jne .sse2.128b.add.mul.f64f64.f64.L1\n ret\n\n" }, { "path": "x64/asm/_SSE_.S", "content": ".globl sse_128b_add_mul_f32f32_f32\n\nsse_128b_add_mul_f32f32_f32:\n xorps %xmm0, %xmm0\n xorps %xmm1, %xmm1\n xorps %xmm2, %xmm2\n xorps %xmm3, %xmm3\n xorps %xmm4, %xmm4\n xorps %xmm5, %xmm5\n xorps %xmm6, %xmm6\n xorps %xmm7, %xmm7\n xorps %xmm8, %xmm8\n xorps %xmm9, %xmm9\n xorps %xmm10, %xmm10\n xorps %xmm11, %xmm11\n xorps %xmm12, %xmm12\n xorps %xmm13, %xmm13\n xorps %xmm14, %xmm14\n xorps %xmm15, %xmm15\n.sse.128b.add.mul.f32f32_f32.L1:\n mulps %xmm0, %xmm0\n addps %xmm1, %xmm1\n mulps %xmm2, %xmm2\n addps %xmm3, %xmm3\n mulps %xmm4, %xmm4\n addps %xmm5, %xmm5\n mulps %xmm6, %xmm6\n addps %xmm7, %xmm7\n sub $0x1, %rdi\n mulps %xmm8, %xmm8\n addps %xmm9, %xmm9\n mulps %xmm10, %xmm10\n addps %xmm11, %xmm11\n mulps %xmm12, %xmm12\n addps %xmm13, %xmm13\n mulps %xmm14, %xmm14\n addps %xmm15, %xmm15\n jne .sse.128b.add.mul.f32f32_f32.L1\n ret\n\n" }, { "path": "x64/cpufp.cpp", "content": "#include \"table.hpp\"\n#include \"smtl.hpp\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#if defined(_AMX_INT8_) || defined(_AMX_BF16_) || defined(_AMX_FP16_)\n#include \n#define _AMX_TILE_\n#endif\n\nusing namespace std;\n\nextern \"C\"\n{\n#ifdef _SSE_\n void sse_128b_add_mul_f32f32_f32(int64_t, void *params);\n#endif\n\n#ifdef _SSE2_\n void sse2_128b_add_mul_f64f64_f64(int64_t, void *params);\n#endif\n\n#ifdef _AVX_\n void avx_256b_add_mul_f32f32_f32(int64_t, void *params);\n void avx_256b_add_mul_f64f64_f64(int64_t, void *params);\n#endif\n\n#ifdef _FMA_\n void fma_256b_fma_f32f32f32(int64_t, void *params);\n void fma_256b_fma_f64f64f64(int64_t, void *params);\n void fma_128b_fma_f32f32f32(int64_t, void *params);\n void fma_128b_fma_f64f64f64(int64_t, void *params);\n#endif\n\n#ifdef _AVX512F_\n void avx512f_512b_fma_f32f32f32(int64_t, void *params);\n void avx512f_512b_fma_f64f64f64(int64_t, void *params);\n void avx512f_512b_add_mul_f32f32_f32(int64_t, void *params);\n void avx512f_512b_add_mul_f64f64_f64(int64_t, void *params);\n#endif\n\n#ifdef _AVX512_BF16_\n void avx512_bf16_512b_dp2a_f32bf16bf16(int64_t, void *params);\n void avx512_bf16_256b_dp2a_f32bf16bf16(int64_t, void *params);\n void avx512_bf16_128b_dp2a_f32bf16bf16(int64_t, void *params);\n#endif\n\n#ifdef _AVX512_FP16_\n void avx512_fp16_512b_fma_f16f16f16(int64_t, void *params);\n void avx512_fp16_256b_fma_f16f16f16(int64_t, void *params);\n void avx512_fp16_128b_fma_f16f16f16(int64_t, void *params);\n#endif\n\n#ifdef _AVX512_VNNI_\n void avx512_vnni_512b_dp4a_s32u8s8(int64_t, void *params);\n void avx512_vnni_256b_dp4a_s32u8s8(int64_t, void *params);\n void avx512_vnni_128b_dp4a_s32u8s8(int64_t, void *params);\n void avx512_vnni_512b_dp2a_s32s16s16(int64_t, void *params);\n void avx512_vnni_256b_dp2a_s32s16s16(int64_t, void *params);\n void avx512_vnni_128b_dp2a_s32s16s16(int64_t, void *params);\n#endif\n\n#ifdef _AVX_VNNI_\n void avx_vnni_256b_dp4a_s32u8s8(int64_t, void *params);\n void avx_vnni_128b_dp4a_s32u8s8(int64_t, void *params);\n void avx_vnni_256b_dp2a_s32s16s16(int64_t, void *params);\n void avx_vnni_128b_dp2a_s32s16s16(int64_t, void *params);\n#endif\n\n#ifdef _AVX_VNNI_INT8_\n void avx_vnni_int8_256b_dp4a_s32s8s8(int64_t, void *params);\n void avx_vnni_int8_128b_dp4a_s32s8s8(int64_t, void *params);\n void avx_vnni_int8_256b_dp4a_s32s8u8(int64_t, void *params);\n void avx_vnni_int8_128b_dp4a_s32s8u8(int64_t, void *params);\n void avx_vnni_int8_256b_dp4a_s32u8u8(int64_t, void *params);\n void avx_vnni_int8_128b_dp4a_s32u8u8(int64_t, void *params);\n#endif\n\n#ifdef _AVX_VNNI_INT16_\n void avx_vnni_int16_256b_dp4a_s32s16u16(int64_t, void *params);\n void avx_vnni_int16_128b_dp4a_s32s16u16(int64_t, void *params);\n void avx_vnni_int16_256b_dp4a_s32u16s16(int64_t, void *params);\n void avx_vnni_int16_128b_dp4a_s32u16s16(int64_t, void *params);\n void avx_vnni_int16_256b_dp4a_s32u16u16(int64_t, void *params);\n void avx_vnni_int16_128b_dp4a_s32u16u16(int64_t, void *params);\n#endif\n\n#ifdef _AMX_INT8_\n void amx_int8_mm_s32s8s8(int64_t, void* tile_cfg);\n void amx_int8_mm_s32s8u8(int64_t, void* tile_cfg);\n void amx_int8_mm_s32u8s8(int64_t, void* tile_cfg);\n void amx_int8_mm_s32u8u8(int64_t, void* tile_cfg);\n#endif\n#ifdef _AMX_BF16_\n void amx_bf16_mm_f32bf16bf16(int64_t, void* tile_cfg);\n#endif\n#ifdef _AMX_FP16_\n void amx_fp16_mm_f32f16f16(int64_t, void* tile_cfg);\n#endif\n}\n\n#ifdef _AMX_TILE_\nstruct\n{\n uint8_t palette_id;\n uint8_t start_row;\n uint8_t reserved_0[14];\n uint16_t colsb[16];\n uint8_t rows[16];\n} __tilecfg;\n\nvoid init_tile_cfg()\n{\n int i;\n __tilecfg.palette_id = 1;\n __tilecfg.start_row = 0;\n for (i = 0; i < 14; i++)\n {\n __tilecfg.reserved_0[i] = 0;\n }\n for (i = 0; i < 8; i++)\n {\n __tilecfg.colsb[i] = 64;\n __tilecfg.rows[i] = 16;\n }\n for (; i < 16; i++)\n {\n __tilecfg.colsb[i] = 0;\n __tilecfg.rows[i] = 0;\n }\n}\n#endif\n\ntypedef struct\n{\n std::string isa;\n std::string vlen;\n std::string type;\n std::string dim;\n int64_t loop_time;\n int64_t comp_pl;\n void *params;\n void (*bench)(int64_t, void*);\n} cpubm_t;\nstatic int num_dsa = 0;\nstatic int num_simd_512b = 0;\nstatic int num_simd_256b = 0;\nstatic int num_simd_128b = 0;\nstatic vector bm_list;\n\nstatic double get_time(struct timespec *start,\n struct timespec *end)\n{\n return end->tv_sec - start->tv_sec +\n (end->tv_nsec - start->tv_nsec) * 1e-9;\n}\n\nstatic void reg_new_isa(std::string isa,\n std::string vlen,\n std::string type,\n std::string dim,\n int64_t loop_time,\n int64_t comp_pl,\n void *params,\n void (*bench)(int64_t, void*))\n{\n cpubm_t new_one;\n new_one.isa = isa;\n new_one.vlen = vlen;\n new_one.type = type;\n new_one.dim = dim;\n new_one.loop_time = loop_time;\n new_one.comp_pl = comp_pl;\n new_one.params = params;\n new_one.bench = bench;\n\n bm_list.push_back(new_one);\n}\n\nstatic void thread_func(void *params)\n{\n cpubm_t *bm = (cpubm_t*)params;\n if (bm->params)\n {\n bm->bench(bm->loop_time, bm->params);\n }\n else\n {\n bm->bench(bm->loop_time, NULL);\n }\n}\n\nstatic void cpubm_x64_one(smtl_handle sh,\n cpubm_t &item,\n Table &table)\n{\n struct timespec start, end;\n double time_used, perf;\n char perfUnit = 'G';\n\n int i;\n int num_threads = smtl_num_threads(sh);\n\n // warm up\n for (i = 0; i < num_threads; i++)\n {\n smtl_add_task(sh, thread_func, (void*)&item);\n }\n smtl_begin_tasks(sh);\n smtl_wait_tasks_finished(sh);\n\n clock_gettime(CLOCK_MONOTONIC_RAW, &start);\n for (i = 0; i < num_threads; i++)\n {\n smtl_add_task(sh, thread_func, (void*)&item);\n }\n smtl_begin_tasks(sh);\n smtl_wait_tasks_finished(sh);\n clock_gettime(CLOCK_MONOTONIC_RAW, &end);\n\n time_used = get_time(&start, &end);\n perf = item.loop_time * item.comp_pl * num_threads /\n time_used;\n if (perf > 1e12)\n {\n perfUnit = 'T';\n perf /= 1e12;\n }\n else\n {\n perf /= 1e9;\n }\n\n stringstream ss;\n ss << std::setprecision(5) << perf << \" \" << perfUnit << item.dim;\n\n vector cont;\n cont.resize(4);\n cont[0] = item.isa;\n cont[1] = item.vlen;\n cont[2] = item.type;\n cont[3] = ss.str();\n table.addOneItem(cont);\n}\n\nstatic void cpubm_do_bench(std::vector &set_of_threads,\n uint32_t idle_time)\n{\n int i;\n\n if (bm_list.size())\n {\n int num_threads = set_of_threads.size();\n\n printf(\"Number Threads: %d\\n\", num_threads);\n printf(\"Thread Pool Binding:\");\n for (i = 0; i < num_threads; i++)\n {\n printf(\" %d\", set_of_threads[i]);\n }\n printf(\"\\n\");\n\n // set table head\n vector ti;\n ti.resize(4);\n ti[0] = \"Instruction Set\";\n ti[1] = \"Vector Length\";\n ti[2] = \"Core Computation\";\n ti[3] = \"Peak Performance\";\n\n Table table;\n table.setColumnNum(4);\n table.addOneItem(ti);\n\n // set thread pool\n smtl_handle sh;\n smtl_init(&sh, set_of_threads);\n\n // traverse task list\n int idx_g = 0;\n if (num_dsa)\n {\n table.addSeparator();\n }\n for (i = 0; i < num_dsa; i++)\n {\n sleep(idle_time);\n cpubm_x64_one(sh, bm_list[idx_g], table);\n idx_g++;\n }\n\n if (num_simd_512b)\n {\n table.addSeparator();\n }\n for (i = 0; i < num_simd_512b; i++)\n {\n sleep(idle_time);\n cpubm_x64_one(sh, bm_list[idx_g], table);\n idx_g++;\n }\n \n if (num_simd_256b)\n {\n table.addSeparator();\n }\n for (i = 0; i < num_simd_256b; i++)\n {\n sleep(idle_time);\n cpubm_x64_one(sh, bm_list[idx_g], table);\n idx_g++;\n }\n \n if (num_simd_128b)\n {\n table.addSeparator();\n }\n for (i = 0; i < num_simd_128b; i++)\n {\n sleep(idle_time);\n cpubm_x64_one(sh, bm_list[idx_g], table);\n idx_g++;\n }\n\n table.print();\n\n smtl_fini(sh);\n }\n}\n\nstatic void parse_thread_pool(char *sets,\n vector &set_of_threads)\n{\n if (sets[0] != '[')\n {\n return;\n }\n int pos = 1;\n int left = 0, right = 0;\n int state = 0;\n while (sets[pos] != ']' && sets[pos] != '\\0')\n {\n if (state == 0)\n {\n if (sets[pos] >= '0' && sets[pos] <= '9')\n {\n left *= 10;\n left += (int)(sets[pos] - '0');\n }\n else if (sets[pos] == ',')\n {\n set_of_threads.push_back(left);\n left = 0;\n }\n else if (sets[pos] == '-')\n {\n right = 0;\n state = 1;\n }\n }\n else if (state == 1)\n {\n if (sets[pos] >= '0' && sets[pos] <= '9')\n {\n right *= 10;\n right += (int)(sets[pos] - '0');\n }\n else if (sets[pos] == ',')\n {\n int i;\n for (i = left; i <= right; i++)\n {\n set_of_threads.push_back(i);\n }\n left = 0;\n state = 0;\n }\n }\n pos++;\n }\n if (sets[pos] != ']')\n {\n return;\n }\n if (state == 0)\n {\n set_of_threads.push_back(left);\n }\n else if (state == 1)\n {\n int i;\n for (i = left; i <= right; i++)\n {\n set_of_threads.push_back(i);\n }\n }\n}\n\nstatic void cpufp_register_isa()\n{\n\n/* Register AMX DSA */\n#ifdef _AMX_TILE_\n init_tile_cfg();\n syscall(SYS_arch_prctl, 0x1023, 18);\n#endif\n\n#ifdef _AMX_INT8_\n reg_new_isa(\"AMX_INT8\", \"DSA\", \"MM(s32,s8,s8)\", \"OPS\",\n 0x2500000LL, 131072LL, &__tilecfg, amx_int8_mm_s32s8s8);\n reg_new_isa(\"AMX_INT8\", \"DSA\", \"MM(s32,s8,u8)\", \"OPS\",\n 0x2500000LL, 131072LL, &__tilecfg, amx_int8_mm_s32s8u8);\n reg_new_isa(\"AMX_INT8\", \"DSA\", \"MM(s32,u8,s8)\", \"OPS\",\n 0x2500000LL, 131072LL, &__tilecfg, amx_int8_mm_s32u8s8);\n reg_new_isa(\"AMX_INT8\", \"DSA\", \"MM(s32,u8,u8)\", \"OPS\",\n 0x2500000LL, 131072LL, &__tilecfg, amx_int8_mm_s32u8u8);\n num_dsa += 4;\n#endif\n\n#ifdef _AMX_BF16_\n reg_new_isa(\"AMX_BF16\", \"DSA\", \"MM(f32,bf16,bf16)\", \"FLOPS\",\n 0x2500000LL, 65536LL, &__tilecfg, amx_bf16_mm_f32bf16bf16);\n num_dsa++;\n#endif\n\n#ifdef _AMX_FP16_\n reg_new_isa(\"AMX_FP16\", \"DSA\", \"MM(f32,f16,f16)\", \"FLOPS\",\n 0x2500000LL, 65536LL, &__tilecfg, amx_fp16_mm_f32f16f16);\n num_dsa++;\n#endif\n\n/* Register 512b SIMD ISA */\n#ifdef _AVX512_VNNI_\n reg_new_isa(\"AVX512_VNNI\", \"512b\", \"DP4A(s32,u8,s8)\", \"OPS\",\n 0x20000000LL, 2048LL, NULL, avx512_vnni_512b_dp4a_s32u8s8);\n reg_new_isa(\"AVX512_VNNI\", \"512b\", \"DP2A(s32,s16,s16)\", \"OPS\",\n 0x20000000LL, 1024LL, NULL, avx512_vnni_512b_dp2a_s32s16s16);\n num_simd_512b += 2;\n#endif\n\n#ifdef _AVX512_BF16_\n reg_new_isa(\"AVX512_BF16\", \"512b\", \"DP2A(f32,bf16,bf16)\", \"FLOPS\",\n 0x20000000LL, 1024LL, NULL, avx512_bf16_512b_dp2a_f32bf16bf16);\n num_simd_512b++;\n#endif\n\n#ifdef _AVX512_FP16_\n reg_new_isa(\"AVX512_FP16\", \"512b\", \"FMA(f16,f16,f16)\", \"FLOPS\",\n 0x20000000LL, 1024LL, NULL, avx512_fp16_512b_fma_f16f16f16);\n num_simd_512b++;\n#endif\n\n#ifdef _AVX512F_\n reg_new_isa(\"AVX512F\", \"512b\", \"FMA(f32,f32,f32)\", \"FLOPS\",\n 0x20000000LL, 512LL, NULL, avx512f_512b_fma_f32f32f32);\n reg_new_isa(\"AVX512F\", \"512b\", \"FMA(f64,f64,f64)\", \"FLOPS\",\n 0x20000000LL, 256LL, NULL, avx512f_512b_fma_f64f64f64);\n reg_new_isa(\"AVX512F\", \"512b\", \"ADD(MUL(f32,f32),f32)\", \"FLOPS\",\n 0x20000000LL, 256LL, NULL, avx512f_512b_add_mul_f32f32_f32);\n reg_new_isa(\"AVX512F\", \"512b\", \"ADD(MUL(f64,f64),f64)\", \"FLOPS\",\n 0x20000000LL, 128LL, NULL, avx512f_512b_add_mul_f64f64_f64);\n num_simd_512b += 4;\n#endif\n\n/* Register 256b SIMD ISA */\n#ifdef _AVX512_VNNI_\n reg_new_isa(\"AVX512_VNNI\", \"256b\", \"DP4A(s32,u8,s8)\", \"OPS\",\n 0x20000000LL, 1024LL, NULL, avx512_vnni_256b_dp4a_s32u8s8);\n num_simd_256b++;\n#endif\n\n#ifdef _AVX_VNNI_\n reg_new_isa(\"AVX_VNNI\", \"256b\", \"DP4A(s32,u8,s8)\", \"OPS\",\n 0x20000000LL, 1024LL, NULL, avx_vnni_256b_dp4a_s32u8s8);\n num_simd_256b++;\n#endif\n\n#ifdef _AVX_VNNI_INT8_\n reg_new_isa(\"AVX_VNNI_INT8\", \"256b\", \"DP4A(s32,s8,s8)\", \"OPS\",\n 0x20000000LL, 1024LL, NULL, avx_vnni_int8_256b_dp4a_s32s8s8);\n reg_new_isa(\"AVX_VNNI_INT8\", \"256b\", \"DP4A(s32,s8,u8)\", \"OPS\",\n 0x20000000LL, 1024LL, NULL, avx_vnni_int8_256b_dp4a_s32s8u8);\n reg_new_isa(\"AVX_VNNI_INT8\", \"256b\", \"DP4A(s32,u8,u8)\", \"OPS\",\n 0x20000000LL, 1024LL, NULL, avx_vnni_int8_256b_dp4a_s32u8u8);\n num_simd_256b += 3;\n#endif\n\n#ifdef _AVX512_VNNI_\n reg_new_isa(\"AVX512_VNNI\", \"256b\", \"DP2A(s32,s16,s16)\", \"OPS\",\n 0x20000000LL, 512LL, NULL, avx512_vnni_256b_dp2a_s32s16s16);\n num_simd_256b++;\n#endif\n\n#ifdef _AVX_VNNI_\n reg_new_isa(\"AVX_VNNI\", \"256b\", \"DP2A(s32,s16,s16)\", \"OPS\",\n 0x20000000LL, 512LL, NULL, avx_vnni_256b_dp2a_s32s16s16);\n num_simd_256b++;\n#endif\n\n#ifdef _AVX_VNNI_INT16_\n reg_new_isa(\"AVX_VNNI_INT16\", \"256b\", \"DP2A(s32,s16,u16)\", \"OPS\",\n 0x20000000LL, 512LL, NULL, avx_vnni_int16_256b_dp2a_s32s16u16);\n reg_new_isa(\"AVX_VNNI_INT16\", \"256b\", \"DP2A(s32,u16,s16)\", \"OPS\",\n 0x20000000LL, 512LL, NULL, avx_vnni_int16_256b_dp2a_s32u16s16);\n reg_new_isa(\"AVX_VNNI_INT16\", \"256b\", \"DP2A(s32,u16,u16)\", \"OPS\",\n 0x20000000LL, 512LL, NULL, avx_vnni_int16_256b_dp2a_s32u16u16);\n num_simd_256b += 3;\n#endif\n\n#ifdef _AVX512_BF16_\n reg_new_isa(\"AVX512_BF16\", \"256b\", \"DP2A(f32,bf16,bf16)\", \"FLOPS\",\n 0x20000000LL, 512LL, NULL, avx512_bf16_256b_dp2a_f32bf16bf16);\n num_simd_256b++;\n#endif\n\n#ifdef _AVX512_FP16_\n reg_new_isa(\"AVX512_FP16\", \"256b\", \"FMA(f16,f16,f16)\", \"FLOPS\",\n 0x20000000LL, 512LL, NULL, avx512_fp16_256b_fma_f16f16f16);\n num_simd_256b++;\n#endif\n\n#ifdef _FMA_\n reg_new_isa(\"FMA\", \"256b\", \"FMA(f32,f32,f32)\", \"FLOPS\",\n 0x20000000LL, 256LL, NULL, fma_256b_fma_f32f32f32);\n reg_new_isa(\"FMA\", \"256b\", \"FMA(f64,f64,f64)\", \"FLOPS\",\n 0x20000000LL, 128LL, NULL, fma_256b_fma_f64f64f64);\n num_simd_256b += 2;\n#endif\n\n#ifdef _AVX_\n reg_new_isa(\"AVX\", \"256b\", \"ADD(MUL(f32,f32),f32)\", \"FLOPS\",\n 0x20000000LL, 128LL, NULL, avx_256b_add_mul_f32f32_f32);\n reg_new_isa(\"AVX\", \"256b\", \"ADD(MUL(f64,f64),f64)\", \"FLOPS\",\n 0x20000000LL, 64LL, NULL, avx_256b_add_mul_f64f64_f64);\n num_simd_256b += 2;\n#endif\n\n/* Register 128b SIMD ISA */\n#ifdef _AVX512_VNNI_\n reg_new_isa(\"AVX512_VNNI\", \"128b\", \"DP4A(s32,u8,s8)\", \"OPS\",\n 0x20000000LL, 512LL, NULL, avx512_vnni_128b_dp4a_s32u8s8);\n num_simd_128b++;\n#endif\n\n#ifdef _AVX_VNNI_\n reg_new_isa(\"AVX_VNNI\", \"128b\", \"DP4A(s32,u8,s8)\", \"OPS\",\n 0x20000000LL, 512LL, NULL, avx_vnni_128b_dp4a_s32u8s8);\n num_simd_128b++;\n#endif\n\n#ifdef _AVX_VNNI_INT8_\n reg_new_isa(\"AVX_VNNI_INT8\", \"128b\", \"DP4A(s32,s8,s8)\", \"OPS\",\n 0x20000000LL, 512LL, NULL, avx_vnni_int8_128b_dp4a_s32s8s8);\n reg_new_isa(\"AVX_VNNI_INT8\", \"128b\", \"DP4A(s32,s8,u8)\", \"OPS\",\n 0x20000000LL, 512LL, NULL, avx_vnni_int8_128b_dp4a_s32s8u8);\n reg_new_isa(\"AVX_VNNI_INT8\", \"128b\", \"DP4A(s32,u8,u8)\", \"OPS\",\n 0x20000000LL, 512LL, NULL, avx_vnni_int8_128b_dp4a_s32u8u8);\n num_simd_128b += 3;\n#endif\n\n#ifdef _AVX512_VNNI_\n reg_new_isa(\"AVX512_VNNI\", \"128b\", \"DP2A(s32,s16,s16)\", \"OPS\",\n 0x20000000LL, 256LL, NULL, avx512_vnni_128b_dp2a_s32s16s16);\n num_simd_128b++;\n#endif\n\n#ifdef _AVX_VNNI_\n reg_new_isa(\"AVX_VNNI\", \"128b\", \"DP2A(s32,s16,s16)\", \"OPS\",\n 0x20000000LL, 256LL, NULL, avx_vnni_128b_dp2a_s32s16s16);\n num_simd_128b++;\n#endif\n\n#ifdef _AVX_VNNI_INT16_\n reg_new_isa(\"AVX_VNNI_INT16\", \"128b\", \"DP2A(s32,s16,u16)\", \"OPS\",\n 0x20000000LL, 256LL, NULL, avx_vnni_int16_128b_dp2a_s32s16u16);\n reg_new_isa(\"AVX_VNNI_INT16\", \"128b\", \"DP2A(s32,u16,s16)\", \"OPS\",\n 0x20000000LL, 256LL, NULL, avx_vnni_int16_128b_dp2a_s32u16s16);\n reg_new_isa(\"AVX_VNNI_INT16\", \"128b\", \"DP2A(s32,u16,u16)\", \"OPS\",\n 0x20000000LL, 256LL, NULL, avx_vnni_int16_128b_dp2a_s32u16u16);\n num_simd_128b += 3;\n#endif\n\n#ifdef _AVX512_BF16_\n reg_new_isa(\"AVX512_BF16\", \"128b\", \"DP2A(f32,bf16,bf16)\", \"FLOPS\",\n 0x20000000LL, 256LL, NULL, avx512_bf16_128b_dp2a_f32bf16bf16);\n num_simd_128b++;\n#endif\n\n#ifdef _AVX512_FP16_\n reg_new_isa(\"AVX512_FP16\", \"128b\", \"FMA(f16,f16,f16)\", \"FLOPS\",\n 0x20000000LL, 256LL, NULL, avx512_fp16_128b_fma_f16f16f16);\n num_simd_128b++;\n#endif\n\n#ifdef _FMA_\n reg_new_isa(\"FMA\", \"128b\", \"FMA(f32,f32,f32)\", \"FLOPS\",\n 0x20000000LL, 128LL, NULL, fma_128b_fma_f32f32f32);\n reg_new_isa(\"FMA\", \"128b\", \"FMA(f64,f64,f64)\", \"FLOPS\",\n 0x20000000LL, 64LL, NULL, fma_128b_fma_f64f64f64);\n num_simd_128b += 2;\n#endif\n\n#ifdef _SSE_\n reg_new_isa(\"SSE\", \"128b\", \"ADD(MUL(f32,f32),f32)\", \"FLOPS\",\n 0x20000000LL, 64LL, NULL, sse_128b_add_mul_f32f32_f32);\n num_simd_128b++;\n#endif\n\n#ifdef _SSE2_\n reg_new_isa(\"SSE2\", \"128b\", \"ADD(MUL(f64,f64),f64)\", \"FLOPS\",\n 0x20000000LL, 32LL, NULL, sse2_128b_add_mul_f64f64_f64);\n num_simd_128b++;\n#endif\n}\n\nint main(int argc, char *argv[])\n{\n vector set_of_threads;\n uint32_t idle_time = 0;\n\n bool params_enough = false;\n\n int i;\n for (i = 1; i < argc; i++)\n {\n if (strncmp(argv[i], \"--thread_pool=\", 14) == 0)\n {\n parse_thread_pool(argv[i] + 14, set_of_threads);\n params_enough = true;\n }\n else if (strncmp(argv[i], \"--idle_time=\", 12) == 0)\n {\n idle_time = (uint32_t)atoi(argv[i] + 12);\n }\n }\n if (!params_enough)\n {\n fprintf(stderr, \"Error: You must set --thread_pool parameter.\\n\");\n fprintf(stderr, \"You may also set --idle_time parameter.\\n\");\n fprintf(stderr, \"Usage: %s --thread_pool=[xxx] --idle_time=yyy\\n\", argv[0]);\n fprintf(stderr, \"[xxx] indicates all cores to benchmark.\\n\");\n fprintf(stderr, \"Example: [0,3,5-8,13-15].\\n\");\n fprintf(stderr, \"idle_time is the interval time(s) between every two benchmarks.\\n\");\n fprintf(stderr, \"idle_time parameter can be ignored, the default value is 0s.\\n\");\n fprintf(stderr, \"Notice: there must NOT be any spaces.\\n\");\n exit(0);\n }\n\n cpufp_register_isa();\n cpubm_do_bench(set_of_threads, idle_time);\n\n return 0;\n}\n" }, { "path": "x64/cpuid.c", "content": "#include \n\nstruct cpuid_t\n{\n unsigned int eax;\n unsigned int ebx;\n unsigned int ecx;\n unsigned int edx;\n};\n\n#define BIT_TEST(bit_map, pos) (((bit_map) & (0x1 << (pos))) ? 1 : 0)\n\nstatic void cpuid_x86_exec(unsigned int ieax,\n unsigned int iecx,\n struct cpuid_t *cpuid)\n{\n asm volatile (\"cpuid\"\n : \"=a\"(cpuid->eax), \"=b\"(cpuid->ebx), \"=c\"(cpuid->ecx), \"=d\"(cpuid->edx)\n : \"0\"(ieax), \"2\"(iecx));\n}\n\nint main()\n{\n struct cpuid_t cpuid_0x1_0x0, cpuid_0x7_0x0, cpuid_0x7_0x1;;\n\n cpuid_x86_exec(0x1, 0x0, &cpuid_0x1_0x0);\n cpuid_x86_exec(0x7, 0x0, &cpuid_0x7_0x0);\n cpuid_x86_exec(0x7, 0x1, &cpuid_0x7_0x1);\n\n if (BIT_TEST(cpuid_0x7_0x0.edx, 24))\n {\n if (BIT_TEST(cpuid_0x7_0x0.edx, 25))\n {\n printf(\"_AMX_INT8_\\n\");\n }\n if (BIT_TEST(cpuid_0x7_0x0.edx, 22))\n {\n printf(\"_AMX_BF16_\\n\");\n }\n if (BIT_TEST(cpuid_0x7_0x1.eax, 21))\n {\n printf(\"_AMX_FP16_\\n\");\n }\n }\n if (BIT_TEST(cpuid_0x7_0x1.eax, 4))\n {\n printf(\"_AVX_VNNI_\\n\");\n }\n if (BIT_TEST(cpuid_0x7_0x1.edx, 4))\n {\n printf(\"_AVX_VNNI_INT8_\\n\");\n }\n if (BIT_TEST(cpuid_0x7_0x1.edx, 10))\n {\n printf(\"_AVX_VNNI_INT16_\\n\");\n }\n if (BIT_TEST(cpuid_0x7_0x0.ecx, 11))\n {\n printf(\"_AVX512_VNNI_\\n\");\n }\n if (BIT_TEST(cpuid_0x7_0x1.eax, 5))\n {\n printf(\"_AVX512_BF16_\\n\");\n }\n if (BIT_TEST(cpuid_0x7_0x0.edx, 23))\n {\n printf(\"_AVX512_FP16_\\n\");\n }\n if (BIT_TEST(cpuid_0x7_0x0.ebx, 16))\n {\n printf(\"_AVX512F_\\n\");\n }\n if (BIT_TEST(cpuid_0x1_0x0.ecx, 12))\n {\n printf(\"_FMA_\\n\");\n }\n if (BIT_TEST(cpuid_0x1_0x0.ecx, 28))\n {\n printf(\"_AVX_\\n\");\n }\n if (BIT_TEST(cpuid_0x1_0x0.edx, 25))\n {\n printf(\"_SSE_\\n\");\n }\n if (BIT_TEST(cpuid_0x1_0x0.edx, 26))\n {\n printf(\"_SSE2_\\n\");\n }\n\n return 0;\n}\n\n" } ]